1993_Motorola_Communications_Device_Data 1993 Motorola Communications Device Data

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®

MOTOROLA

Communications
Device Data
Motorola offers a broad range of semiconductor communications products for a wide variety
of applications. The Motorola Communications Device Data Book contains specifications
on these parts as well as information on Evaluation Kits, a selection of Application Notes,
Handling and Design Guidelines, and Reliability and Quality information. Functional and
Technical Selection Guides are also included to help you select the appropriate part for your
application.
The MOtorola Communications Device Data Book, formerly Motorola Telecommunications
Device Data Book, has been expanded to include additional Motorola devices for use in
Communications applications. For instance, Phase-Locked Loop and Remote Control devices have been added from the former OL 130/0 CMOS Application-Specific Standard IC
Data Book. Additionally, many new devices have been added since the last revision of this
data book.
New Motorola communications devices are being introduced continually. For the latest releases, additional technical information, and pricing, please contact your nearest Motorola
Semiconductor Sales Office or authorized distributor. A complete listing of sales offices and
authorized distributors is included at the back of this book.

Motorola reserves the right to make changes without further notice to any products herein. Motorola makes
no warranty, representation or guarantee regarding the suitability of its products for any particular purpose,
nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical"
parameters can and do vary in different applications. All operating parameters, including ''Typicals'' must be
validated for each customer application by customer's technical experts. Motorola does not convey any
license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, orfor any other application in which the failure ofthe Motorola product could
create a situation where personal iniury or death may occur. Should Buyer purchase or use Motorola products
for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers,
employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees ariSing out of, directly or indirectly, any claim of personal injury or
death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was
are registered trademarks of
negligent regarding the design or manufacture of the part. Motorola and
Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.

®

© Motorola, Inc. 1993
Previous Edition © 1989
"All Rights Reserved"

Printed in U.S.A.

TABLE OF CONTENTS
Chapter 1 -

Selection Guide

Functional Selection Guides ............................................................... .
Amplifiers/Comparators/Regulators ........................................................ .
Analog Telephone ....................................................................... .
Data Communication Devices ............................................................. .
Digital Signal Processing ................................................................. .
DMA Controllers ......................................................................... .
Evaluation Kits .......................................................................... .
Fiber Distributed Data Interface (FDDI) ..................................................... .
Integrated Processors .................................................................... .
Integrated Services Digital Network (ISDN) ................................................. .
Interface ............................................................................... .
Modems ............................................................................... .
Network Devices ........................................................................ .
Phase-Locked Loop (PLL) Frequency Synthesizers .......................................... .
Remote Control Functions ................................................................ .
RF Communications ..................................................................... .
Speakerphones ......................................................................... .
Subscriber Loop Interface Circuits (SUCs) .................................................. .
Voice Coding ..........................................................................-..
Other Functions ......................................................................... .
Discontinued/Not Recommended For New Design ........................................... .

1-3
1-3
1-3
1-3
1-3
1-4
1-4
1-4
1-4
1-4
1-4
1-5
1-5
1-5
1-5
1-6
1-6
1-6
1-6
1-7
1-7

Technical Selection Guides ................................................................ .

1-9
1-9

RF Communications ..................................................................... .

Narrowband Dual Conversion Receivers ..................................................... .

1-9
1-9
1-9
1-9
1-9
1-10

Low-Power Operational Amplifier .......................................................... .

1-10

Remote Control ......................................................................... .

1-10

Switch Mode Controller ................................................................... .

1-10

EIA-2321EIA-5621V.28 Drivers/Receivers .................................................... .

1-11

AM and Wide band FM Transmitters ......................................................... .
Wideband Single Conversion Receivers ..................................................... .
Wideband IFs .......................................................................... .
Narrowband FM Transmitters .............................................................. .
Narrowband Single Conversion Receivers .................................................... .

EIA-422 Drivers/Receivers ................................................................ .

1-11

Phase-Locked Loop Frequency Synthesizers ................................................ .

1-12

Telecom Circuits ......................................................................... .

1-13

Audio Amplifiers ........................................................................ .
Complete Telephone Circuit ............................................................... .
Companders .......................................................................... .
Dialers ............................................................................... .
Integrated Services Digital Network (ISDN) ............................................... .

1-13
1-13
1-13
1-13

Modems .............................................................................. .
Subscriber Loop Interface Circuits (SUCs) ................................................... .
Speakerphone Circuits ................................................................... .
Speech Networks ....................................................................... .
Switching Regulator .............................................................................. .
Tone Ringers .......................................................................... .
Voice Coding .......................................................................... .
Voice Encoders/Decoders ................................................................ .

MOTOROLA COMMUNICATIONS DEVICE DATA

1-13
1-14
1-14
1-14
1-14
1-14
1-15
1-15
1-15

V

Chapter 2 -

Data Sheets

MC14C88B
MC14C89B, AB
MC1488
MC1489,A
MC26C31
MC26C32
MC2831A
MC2833
MC3356
MC3357
MC3359
MC3361B
MC3362
MC3363
MC3367
MC3371
MC3372
MC34C86
MC34C87
MC3417
MC3418
MC3419-1L
MC3517
MC3518
MC13055
MC13135
MC13136
MC13155
MC13156
MC13175
MC13176
MC14400
MC14401
MC14402
MC14403
MC14405
MC14408
MC14409
MC14410
MC14411
MC14412
MC14413
MC14414
MC14416
MC14417
MC14418
MC14419
MC14469
MC14497
MC33102
MC33110
MC33120
MC33121
MC33129
MC33178
MC33179
MC33218
MC34010
MC34012

vi

EIA-2321EIA-5621V.28 Quad Low Power Driver ............................ .
EIA-2321EIA-5621V.28 Quad Low Power Receivers ........................ .
EIA-2321V.28 Quad Driver .............................................. .
EIA-2321V.28 Quad Receiver ............................................ .
EIA-422 Quad Driver •..................................................
EIA-422 Quad Receiver ................................ '................ .
Low Power FM Transmitter System ........................... , .......... .
Low Power FM Transmitter System ...................................... .
Wideband FSK Receiver ............................................... .
Low Power FM IF ..................................................... .
High Gain Low Power FM IF .......................... : ................. .
Low Power FM IF ............. , ....................................... .
Low Power Dual Conversion FM Receiver ................................ .
Low Power Dual Conversion FM Receiver ................................ .
Low Voltage Single Conversion FM Receiver ............................. .
Low Power Narrowband FM IF .......................................... .
.Low Power Narrowband FM IF .......................................... .
EIA-422 Quad Receiver ................................................ .
EIA-422 Quad Driver .................................................. .
CVSD ModulatorlDemodulator (3-Bit Algorithm) ........................... .
CVSD ModulatorlDemodulator (4-Bit Algorithm) ........................... .
Subscriber Loop Interface Circuit (SUC) ................................. .
CVSD ModulatorlDemodulator (3-Bit Algorithm) ........................... .
CVSD Modulator/Demodulator (4-Bit Algorithm) ........................... .
Wideband FSK Receiver ............................................... .
Dual Conversion Narrowband FM Receiver ............................... .
Dual Conversion Narrowband FM Receiver ............................... .
Wideband FSK Receiver ............................................... .
Wideband FM IF System ............................................... .
UHF FM/AM Transmitter ............................................... .
UHF FM/AM Transmitter ............................................... .
Codec-Filter (Mono-Circuit) ............................................. .
Codec-Filter (Mono-Circuit) ............................................. .
Codec-Filter (Mono-Circuit) .............................................. .
Codec-Filter (Mono-Circuit) ............................................. .
Codec-Filter (Mono-Circuit) ............................................. .
Binary to Pulse Dialer .................................................. .
Binary to Pulse Dialer ................................................... .
2-01-8 Tone Encoder/Dialer ...•..........................................
Bit Rate Generator ........... ;................................. NRFND*
Universal Low Speed Modem (0-600 bps) ................................ .
PCM Band-Pass/Low-Pass Filter ............................. : ......... , .
PCM Dual Low-Pass Filter ...•..........................................
Time Slot Assigner Circuit .............................................. .
Time Slot Assigner Circuit .............................................. .
TIme Slot Assigner Circuit .............................................. .
2-01-8 Keypad-Io-Binary Encoder ........................................ .
Addressable Asynchronous ReceiverlTransmitter .......................... .
PCM Remote Control Transmitter ........................................ .
Dual Sleep-Mode Operational Amplilier ...............................•...
Low Voltage Compander ............................................. ; ..
Subscriber Loop Interface Circuit (SUC) ................................. .
Low Voltage Subscriber Loop Interface Circuit (SUC) ................ '.' .... .
High Performance Current Mode Controller ............................... .
High Output Current, Low Power, Low Noise Operational Ampliliers .......... .
High Output Current, Low Power, Low Noise Operational Ampliliers .......... .
Voice Switched Speakerphone with Microprocessor Interface ............... .
Electronic Telephone Circuit ............................................. .
Telephone Tone Ringer ................................................ .

2-3
2-9
2-14
2-20
2-26
2-29
2-32
2-35
2-38
2-44
2-48
2-54
2-60
2-65
2-72
2-78
2-78
2-95
2-98
2-101
2-101
2-119
2-101
2-101
2-135
2-142
2-142
2-154
2-169
2-170
2-170
Note 1
Note 1
Note 1
Note 1
Note 1
Note 1
Note 1
Note 1
2-187
Note 1
Note 1
Note 1
Note 1
Note 1
Note 1
2-190
2-194
2-202
2-208
2-220
2-232
2-262
2-446
2-292
2-292
2-302
2-313
2-337

MOTOROLA COMMUNICATIONS DEVICE DATA

MC34014
MC34017
MC34018
MC34114
MC34115
MC34118
MC34119
MC34129
MC142100
MC142103
MC143403
MC143404
MC145026
MC145027
MC145028
MC145030
MC145031
MC145032
MC145033
MC145034
MC145035
MC145100
MC145106
MC145145-2
MC145146-2
MC145149
MC145151-2
MC145152-2
MC145155-2
MC145156-2
MC145157-2
MC145158-2
MC145159-1
MC145160
MC145161
MC145162
MC145166
MC145167
MC145168
MC145169
MC145170
MC145173
MC145190
MC145191
MC145192
MC145200
MC145201
MC145402
MC145403
MC145404
MC145405
MC145406
MC145407
MC145408
MC145411
MC145412
MC145413
MC145414
MC145415
MC145416
MC145418

2-345
Telephone Speech Network with Dialer Interface ..............•............
2-362
Telephone Tone Ringer ........•....•........•..........................
2-370
Voice Switched Speakerphone Circuit ....••.•.•••....••.............•....•
2-384
Telephone Speech Network with Dialer Interface ......................•....
2-402
CVSD Modulator/Demodulators •••••••.••.••••.••..••..................•.
2-417
Voice Switched Speakerphone Circuit •••....••.....•....•..•..............
2-437
Low Power Audio Amplifier ....•..•..••.•...••.....•...............•.....
2-446
High Performance Current Mode Controller .•.....•••.....•.....•..........
4 x 4 Crosspoint Switch with Control Memory ..•.............•••... NRFND* 2-459
Encoder/Decoder ••.•..•.•••..••••....••...•.•...........••••.. NRFND* 2-747
Quad Line Driver. . . . . . . . . . • . . . . . . . . . . . . . . • . • . . • . . . . . . . . . . . . . . .. NRFND* 2-460
Quad Line Driver. . . . . • • . . . . • • . . . . . . . . . . . . . . . . . • • . . . . • • . . • . . . . .. NRFND* 2-460
2-461
Encoder ....................••...•••.....•....................•.......
2-461
Decoder •..................•••.........••.....••...•..................
2-461
Decoder .........••...••••••.•..•....•............•.....•••••....•••..
EncoderlDecoder ..............................••..........•... NRFND* 2-477
Encoder ......................••....•••...•................•.. NRFND* 2-485
Decoder ••.....•..........................•................•.. NRFND* 2-485
Encoder/Decoder ..•••...•..•....•...•..............•.......••• NRFND* 2-485
Encoder .........................••.•..• •.. . . . . . . . . . . . . . . . . . . .. NRFND* 2-485
Decoder ........•.......•....••....••••...•..............•..•. NRFND* 2-485
4 x 4 Crosspoint Switch with Control Memory •..................... NRFND* 2-459
2-495
PLL Frequency Synthesizer ...............•......•••....................
2-502
4-Bit Data Bus Input PLL Frequency Synthesizer .•...........•......•......
2-513
4-Bit Data Bus Input PLL Frequency Synthesizer .......................... .
2-524
Dual PLL Frequency Synthesizer ••..•..•••...•.•...................•.....
2-534
Parallel-Input PLL Frequency Synthesizer (Single-Modulus Prescalers) ....... .
2-538
Parallel-Input PLL Frequency Synthesizer (Dual-Modulus Prescalers) ........ .
2-542
Serial-Input PLL Frequency Synthesizer (Single-Modulus Prescalers) ........ .
2-546
Serial-Input PLL Frequency Synthesizer (Dual-Modulus Prescalers) ...•••...•.
2-550
Serial-Input PLL Frequency Synthesizer (Single-Modulus Prescalers) ........ .
2-553
Serial-Input PLL Frequency Synthesizer (Dual-Modulus Prescalers) •..........
2-565
Serial-lnputPLL Frequency Synthesizer with Analog Phase Detector ...•......
2-574
4-Bit Parallel Dual PLL for 46149 MHz Cordless Telephones .....•••...••••...
2-581
Dual PLLfor 30/39 MHz Cordless Telephones .••..•.........•.....•.......
2-587
60 MHz Universal Programmable Dual PLL Frequency Synthesizer .........••
2-574
4-Bit Parallel Dual PLL for 46149 MHz Cordless Telephones ................. .
2-574
Serial-Input Dual PLL for 46/49 MHz Cordless Telephones .................. .
2-606
4-Bit Input Dual PLL for 46/49 MHz Cordless Telephones ......•.............
2-606
Serial-Input Dual PLL for 46149 MHz Cordless Telephones .................. .
2-615
PLL Frequency Synthesizer with Serial Interface .....•.....................
2-631
Dual Band PLL Frequency Synthesizer ...•..................•....••.....•
2-632
1.1 GHz PLL Frequency Synthesizer .................................... .
2-632
1.1 GHz PLL Frequency Synthesizer .........•.•.........................
2-651
1.1 GHz Low Voltage PLL Frequency Synthesizer ...•••..................•.
2-670
2.0 GHz PLL Frequency Synthesizer .••.....••........................•..
2-670
2.0 GHz PLL Frequency Synthesizer ....•....•............ o' ••••••••••••••
2-689
Serial 13-BII Linear Codec (AID and D/A) ..........•••......•..............
2-700
EIA-2321V.28 Driver/Receiver (3 x 5) ..................•...................
2-700
EIA-2321V.28 Drivers/Receivers (4 x 4) ............................•......•
2-700
EIA-2321V.28 Drivers/Receivers (5 x 3) .......•.................•..........
2-706
EIA-2321V.28 Driver/Receiver (3 x 3) ..•••..•.••...........................
EIA-2321V.28 5 V Only Driver/Receiver (3 x 3) •........••.....•...•........
2-714
2-700
EIA-2321V.28 Drivers/Receivers (5 x 5) ..•..••.•...........................
Bit Rate Generator .....•.....•....•.....•••...•••..•...•....... NRFND* 2-720
2-721
Pulse/Tone Repertory Dialer ...•••..••••..••.•....•••......•.............
2-721
PulseITone Repertory Dialer .............•..•.•..........................
Dual Tunable Low-Pass Sampled Filter •••..••....•.•............. NRFND* 2-728
Dual Tunable Linear Phase Low-Pass Sampled Data Filter ..•....... NRFND* 2-729
Tone/Pulse Dialer with 10 Number Memory Plus 3 Emergency Numbers ...... .
2-730
80 kbps Digital Loop Transceiver (Master) ....••....•......................
Note 1

MOTOROLA COMMUNICATIONS DEVICE DATA

vii

MC145419
MC145421
MC145422
MC145425
MC145426
MC145428
MC145429
MC145432
MC145433
MC145436
MC145439
MC145440
MC145441
MC145442
MC145443
MC145444
MC145445
MC145447
MC145450
MC145472
MC1454LC72
MC145474
MC145475
MC145480
MC145488
MC145500
MC145501
MC145502
MC145503
MC145505
MC145512
MC145532
MC145540
MC145542
MC145554
MC145557
MC145564
MC145567
MC145572
MC145574
MC145583
MC145601
MC145610
MC145611
MC145705
MC145706
MC145707
TCA3385
TCA3388
MJD243
MJD253
MJE270
MJE271
MPS6717
4N35

80 kbps Digital Loop Transceiver (Slave) ................................. .
Universal Digital Loop Transceivers 11- UDLT II ................... NRFND*
Universal Digital Loop Transceivers - UDLT ...................... NRFND*
ISDN Universal Digital Loop Transceiver 11- UDLT II ............... NRFND*
Universal Digital Loop Transceiver - UDLT ....................... NRFND*
Data Set Interface .............................................. NRFND*
Teleset Audio Interface Circuit ................................... NRFND*
2600 Hz Signaling Filter ......................................... NRFND*
Tunable Notch/Band-Pass Filter .....••...................................
Dual Tone Multiple Frequency (DTMF) Decoder ........................... .
Encoder/Decoder .............................................. NRFND*
300 Baud Modem Filter (Bell 103) ....................................... .
300 Baud Modem Filter (CCITT V.21) ................................... ..
300 Baud Modem (CCITT V.21) ......................................... .
300 Baud Modem (Bell 103) ............................................ .
300 Baud Modem with DTMF Generator (CCITT V.21) ..................... .
300 Baud Modem (BeIl103/CCITT V.21) ................................. .
Calling Line ID (CLlD) Receiver with Ring Detector ........................ .
1200 Baud Modem (Bell 202lCCITT V.23) •................................
ISDN (2B10) U-Interface Transceiver .................................... .
ISDN (2B10) Low Power U-Interface Transceiver ......................... .
ISDN SIT Interface Transceiver ......................................... .
ISDN SIT Interface Transceiver ......................................... .
5 Volt PCM Codec-Filter ............................................... .
Dual Data Link Controller (DDLC) (ISDN LAPDILAPB) ..................... .
Codec-Filter (Mono-Circuit; 16-Pin) ...................................... .
Codec-Filter (Mono-Circuit; 18-Pin) ...................................... .
Codec-Filter (Mono-Circuit; 22-Pin) ...................................... .
Codec-Filter (Mono-Circuit; 16-Pin) ...................................... .
Codec-Filter (Mono-Circuit; 16-Pin) ...................................... .
PulseITone Repertory Dialer ............................................ .
ADPCM Transcoder ...................•.................•..............
ADPCM Codec ....................................................... .
CT2 Speech and Framing IC ......•.....................................
PCM Codec-Filter (16-Pin) ............................................. .
PCM Codec-Filter (16-Pin) ............................................. .
PCM Codec-Filter (20-Pin) ............................................. .
PCM Codec-Filter (20-Pin) ............................................. .
ISDN U-Interface Transceiver II ......................................... .
ISDN SIT Interface Transceiver II ....................................... .
EIA-2321V.28 3.3 V-5 V Driver/Receiver (3 x 5) ........................... .
Time Slot Interchange Circuit .................................... NRFND*
Pulse Tone Dialer with Laster Number Redial ............................. .
PCM Conference Circuit ........................................ NRFND*
EIA-2321V.28 5 V Only Driver/Receiver w/lntegrated Standby Mode (2 x 3) .... .
EIA-2321V.28 5 V Only Driver/Receiver w/lntegrated Standby Mode (3 x 2) .... .
EIA-2321V.28 5 V Only Driver/Receiver w/lntegrated Standby Mode (3 x 3) .... .
Telephone Ring Signal Converter ........................................ .
Speech Circuit ........................................................ .
4-A Silicon Power Transistor ............................................ .
4-A Silicon Power Transistor ............................................ .
Complementary Silicon Power Transistors ................................ .
PNP Power Transistor ................................................. .
One Watt Amplifier Transistors .......................................... .
DIP Optoisolators Transistor Outputs (6-Pin) .............................. .

Note 1
2-737
2-738
2-737
2-7:38
2-739
2-740
2-741
Note 1
2-742
2-747
Note 1
Note 1
2-748
2-748
2-756
Note 1
2-765
Note 1
2-775
2-775
2-801
2-801
2-822
2-844
2-854
2-854
2-854
2-854
2-854
2-721
2-875
2-890
2-906
2-907
2-907
2-907
2-907
2-922
2-924
2-926
2-927
Note 1
2-928
2-929
2-929
2-929
2-935
2-943
2-947
2-947
2-951
2-951
2-953
2-954

Note 1: The listed device has been discontinued. Contact your local Motorola sales office for possible alternatives for your application.
*NRFND: The listed device is not recommended for new design.

viii

MOTOROLA COMMUNICATIONS DEVICE DATA

Chapter 3 - Evaluation Kits
MC145190EVK
MC145191 EVK
MC145460EVK
MC14LC5494EVK
MC145536EVK
MC145537EVK

1.1 GHz PLL Frequency Synthesizer Evaluation Kit ........................ .
1.1 GHz PLL Frequency Synthesizer Evaluation Kit ........................ .
Calling Line ID (CLlD) Receiver Evaluation Kit ............................ .
ISDN U-Interface Transceiver Evaluation Kit .............................. .
Codec-Filter/ADPCM Transcoder Evaluation Kit ........................... .
MC145540 ADPCM Codec Evaluation Kit ................................ .

3-3
3-3
3-5
3-7
3-11
3-13

Chapter 4 - Application Notes and Technical Articles
TELECOM

AN872
AN893
ARTICLE 1
AN943
AN949
AN968
AR239
AN933
AN937
AN940
AN957
AN958
AN959
AN960
AN1002
AN1003
AN1004
AN1006
EB 112
ARTICLE 4
AN1077
AN1081
AN946
AN948
EB 111
ARTICLE 5
ARTICLE 6
AN 151 0

MCl4402 Mono-Circuit Applications Information ........................... .
Understanding Telephone Key Systems .................................. .
Telephone Quality CVSD Codecs Using New Bipolar Linear/12L I.C ........... .
UDLT Evaluation Board ................................................ .
A Voice/Data Modem Using the MC145422126, MC145428, and MC14403 .... .
A Digital Voice/Data Telephone Set ...................................... .
Implementing Integrated Office Communications .......................... .
A Variety of Uses for the MC34012' and MC34017 Tone Ringers ............. .
A Telephone Ringer Which Complies with FCC and EIA Impedance Standards .
Telephone Dialing Techniques using the MC6805 .......................... .
Interfacing the Speakerphone to the MC3401 0/11/13 Speech Networks ....... .
Transmit Gain Adjustments for the MC34014 Speech Network .............. .
A Speakerphone with Receive Idle Mode ................................. .
Equalization of DTMF Signals Using the MC34014 ........................ .
A Handsfree Featurephone Design Using the MC34114 Speech Network
and the MC34018 Speakerphone ICs ................................. .
A Featurephone Design, with Tone Ringer and Dialer, Using the
MC34118 Speakerphone ICs ......................................... .
A Handsfree Featurephone Design Using the MC34114 Speech Network
and the MC34118 Speakerphone ICs ................................. .
Linearize the Volume Control of the MC34118 Speakerphone ............... .
The Application of a Telephone Tone Ringer as a Ring Detector ............. .
LSI fOrTelecommunications ............................................ .
Adding Digital Volume Control to Speakerphone Circuits ................... .
Minimize "Pop" in the MC34119 Low Power Audio Amplifier ................. .
Limited Distance Modem ............................................... .
Data Multiplexing ..................................................... .
The Application of a Duplexer ........................................... .
IC Trio Simplifies Speech Synthesis ..................................... .
Turn I/O Data Port Into Speech Port ..................................... .
A Mode Indicator for the MC34118 Speakerphone Circuit ................... .

4-3
4-8
4-15
4-21
4-31
4-37
4-44
4-49
4-58
4-65
4-83
4-95
4-97
4-99
4-101
4-119
4-132
4-150
4-151
4-152
4-156
4-160
4-163
4-173
4-183
4-185
4-189
4-190

PLL FREQUENCY SYNTHESIZERS

AN535
AN827
AN969
AN980
AN1207
AN254 #1
AN254#2
AN254#3
AN254-4

Phase-Locked Loop Design Fundamentals ............................... .
The Technique of Direct Programming by Using a Two-Modulus Prescaler .... .
Operation of the MC145159 PLL Frequency Synthesizer with
Analog Phase Detector .............................................. .
VHF Narrowband FM Receiver Using the MC3362 and MC3363 Dual
Conversion Receivers (MC145152) ................................... .
MC145170 in Basic HF and VHF Oscillators .............................. .
Analyze, Don't Estimate, Phase-Lock Loop ............................... .
Optimize Phase-Lock Loops To Meet Your Needs...
. .................... .
Suppress Phase-Lock Loop Sidebands Without Introducing Instability ........ .
Programmable Calculator Computes PLL Noise, Stability ................... .

4-195
4-206

Operation of the MCl4469 ............................................. .
Infrared Sensing and Data Transmission Fundamentals .................... .
Evaluation systems for Remote Control Devices on an Infrared Link .......... .
Software Method for Decoding Output from MCl4497/MC3373 Combination .. .
Simplified Remote Control Circuits (MC145030) ........................... .

4-263
4-270
4-275
4-285
4-290

4-211
4-222
4-236
4-242
4-245
4-249
4-252

REMOTE CONTROL

AN806A
AN1016
ANl126
AN1203
AR255

MOTOROLA COMMUNICATIONS DEVICE DATA

ix

Chapter 5 -

Glossary ..........................................................

5-1

Terms and Abbreviations ........ . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Useful Addresses ...........................................................................

5-3
5-8

Handling and Design Guidelines ................ . . . . . . . . . . . . . . . . . . . .

6-1

Chapter 7 -

Quality and Reliability.. . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . .

7-1

Chapter 8 -

Mechanical Data .................... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8-1

x

Chapter 6 -

MOTOROLA COMMUNICATIONS DEVICE DATA

Selection Guides

MOTOROLA COMMUNICATIONS DEVICE DATA

-

Selection Guides
1-1

Selection Guides
1-2

MOTOROLA COMMUNICATIONS DEVICE DATA

Functional Selection Guide
This selection guide includes all Motorola devices characterized in this book. Other devices also used in communications applications, but associated· with other product families, appear in the following documents.
Document No.
DL 110/D

DL111/D
DL118/D
DL1221D

DL126/D
DL128/D
DL150/D
SG73/D
SG96/D
SG127/D
SG169/D
MC ...
DSP •••

Title
Volume 1 & 2, RF Device Data
Bipolar Power Transistor Data
Optoelectronics Device·Data
MECL Device Data
Small-Signal Transistors/FETs/Diodes
Linear and Interface ICs Data
TVS/Zener Device Data
Master Selection Guide
Linear and Interface Integrated Circuits Selector Guide
Surface Mount Products Selector Guide
MOS Digital-Analog IC Quarterly Update
Data Sheets
Data Sheets

AMPLIFIERSlCOMPARATORSlREGULATORS
Function
Device #
Dual Sleep-Mode Operational Amplifier. . • . • • • • • • • .. • .. . .. . . .. . . . . . . . . . ••
MC33102
High Performance Current Mode Controller ••••••••••••.........•......••
MC33129
High Output Current, Low Power, Low Noise Operational Amplifiers •••••••..
MC33178
High Output Current, Low Power, Low Noise Operational Amplifiers •••••••..
MC33179
Low Power Audio Amplifier ............................................
MC34119
High Performance Current Mode Controller .......................•......
MC34129

Page #
2-208
2-446
2-292
2-292
2-437
2-446

ANALOG TELEPHONE
Device #
MC34010
MC34012
MC34014
MC34017
MC34114
MC145412
MC145413
MC145416
MC145436
MC145512
TCA3385
TCA3388

Function
Electronic Telephone Circuit .......................................... .
Telephone Tone Ringer ............................................... .
Telephone Speech Network with Dialer Interface ...••..•.•••.•••.••..•...•
Telephone Tone Ringer ..•...........................••••••.••••.••••••.
Telephone Speech Network with Dialer Interface ••...•.•••••••••.•..••••..
PulselTone Repertory Dialer .......................................... .
PulselTone Repertory Dialer ......................................... ..
Tone/Pulse Dialer with 10 Number Memory Plus 3 Emergency Numbers .•.•.
Dual Tone Multiple Frequency (DTMF) Decoder .•...•.•..........•......•
PulselTone Repertory Dialer .......................................... .
Telephone Ring Signal Converter ...................................... .
Speech Circuit ••............• '..•••.........•.•••••••..•.............••

Page #
2-313
2-337

2-345
2-362
2-384
2-721
2-721
2-730
2-742
2-721
2-935
2-943

DATA COMMUNICATION DEVICES
Device #
MC145488
MC68661
MC68681

Function
Dual Data Link Controller (DDLC) (ISDN LAPD/LAPB) .•.•................
Enhanced Peripheral Communication Interface ......•.•••.•••••••••••.•..
Universal Asynchronous ReceiverlTransmitter .........•...••......... , .•.

Page #
2-844
MC68661/D
MC68681/D

DIGITAL SIGNAL PROCESSING
Device #
DSP56ADC16
DSP56000
DSP56001
DSP56002
DSP56116
DSP56156
DSP56200

Function
Analog-to-Digital Converter ............................................
24-bit Digital Signal Processor .........................................
24-bit Digital Signal Processor •.....••••••........•.•.•.•••••.••••.••..
24-bitDigital Signal Processor .....• ;..................................
16-bit Digital Signal Processor .........................................
16-bit Digital Signal Processor .........................................
Cascadable Adaptive Finite Impulse Response Digital Filter. • • • • • • • • • . • • • •.

MOTOROLA COMMUNICATIONS DEVICE DATA

Page #
DSP56ADC16/D

DSP56000/D
DSP56001ID
DSP56002ID
DSP561161D
DSP561561D

DSP56200/D

Functional Selection Guide
1-3

DMA CONTROLLERS
Device I
MC68440
MC68450

Function
Page I
Dual DMAC .............•................••.•••..••••••.•........... MC684401D
DMA Controller (DMAC) . . . • . . . . . . . . . . . .. . . • • . . . • . . • . . . • • • • . . . . . . . . . . .. MC68450/D

EVALUATION KITS
Device I
MC145190EVK
MC145191EVK
MC145460EVK
MC14lC5494EVK
MC145536EVK
MC145537EVK

Function
1.1 GHz Pll Frequency Synthesizer Evaluation Kit .....................•.
1.1 GHz Pll Frequency Synthesizer Evaluation Kit •••....................
Calling Line ID (CLlD) Receiver Evaluation Kit ••.•.•.•....................
ISDN U-Interface Transceiver Evaluation Kit .•.•..••• "•••••••••••.••.•..•.
Codec-Filter/ADPCM Transcoder Evaluation Kit ......................... .
MC145540 ADPCM Codec Evaluation Kit .....................•.......•..

Pagel
3-3
3-3
3-5
3-7
3-11
3-13

FIBER DISTRIBUTED DATA INTERFACE (FDDI)
Device I
MC68834
MC68836
MC68837
MC68838
MC68839
MC68840

Function
Stream Cipher Chip ........••••.•••••...•...........•................
FOOl Clock Generator ..•..•...•..•••••••••••••••.•••....•.•.••...••.•
Elasticity Buffer and Link Manager .....................•....•.•.........
Media Access Controller ..••••••.••••••....••........•................
FOOl System Interface .....................•......•...................
Integrated FOOl ................•...••.....•.•.... : .................. .

Pagel
MC68836UM/AD
MC68837UMlAD
MC68838UMlAD

INTEGRATED PROCESSORS
Device I
MC68302
MC68340
MC68360

Function
Page I
Integrated Multiprotocol Processor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .• MC68302UM/AD
MC68302ADUMIAD
Integrated Processor with DMA ••••.••.•••••.••••••.•.•.•..•.•......... MC68340UM/AD
Quad Integrated Communication Controller (QUICC) ...... . . . . . . . . . . . . . . .. MC68360UM/AD

INTEGRATED SERVICES DIGITAL NETWORK (ISDN)
Device I
MC145472
MC1454lC72
MC145474
MC145475
MC145572
MC145574

Function
ISDN (2B1Q) U-Interface Transceiver ........••....... , ................ .
ISDN (2B1Q) U-Interface Transceiver •••••••.••••••..•.•................
ISDN SIT Interface Transceiver ...•..•..••..••.•....••................•
ISDN SIT Interface Transceiver •.....••••...........•....•......•.•.•.•
ISDN U-Interface Transceiver II ......••................................
ISDN SIT Interface Transceiver II ............•....... ; •.................

Pagel
2-775
2-775
2-801
2-801

Function
Quad low Power Line Driver. . . . . . . . . . • • . . . . . . . . . . . . . . . . . . • . . . . . . . . . . ..
Quad low Power Line Receivers •••. . • • • • . . • • . • • • • . . • • • • • . . • . . . • • • • . . .•
Quad MDTl Line Driver ...•.•••••••.•.••••••.•••.• ; ...•.•.•...•••...••
Quad MDTl Line Receivers ••.•••••..•.••..•....•.....•.........•...••
Quad EIA-422-A Line Driver •..••••••••••••••.•..••.••••••...••.•...•.•
Quad EIA-422-A Line Receiver. • • • • • • . • . . . . . . . • . . • . . . . . . • . . • . . • . . . • . . ..
Quad EIA-422-A Line Receiver. • . . . . • . . • . . . . . . . . . • . . . . . . . . . . . . . . . . . . • •.
Quad EIA-422-A line Driver ...................••.......•..............
Drivers/Receivers (315) .•..••......••••.•••.••..•.•••••••.••....•.•....
Drivers/Receivers (4/4) .........•.......••..•......................•...
Drivers/Receivers (513) . . • • . . . . . . . . . . . . . • . • . • . . . . . . . . . . . . . . . . . . . . . . . . ..
EIA-232-ElV.28 Driver/Receiver ..•.•..•.•..••..•••••.••••..••..........
5-Vol! Only Driver/Receiver ..•....•....•.•.••.•...••...••..•...........
Drivers/Receivers (5/5) . • • • • • • • • • . . • . . . • •• . . • . . . . . • . . . . . . • • . . . . . . . . . . ..
3.3 Volt to 5 Volt EIA-232-E V.28 Driver/Receiver ...•............... c. . . ..
5 V Only Driver/Receiver w/lntegrated Standby Mode (2-Driver/3-Receiver) ..
5 V Only Driver/Receiver wllntegrated Standby Mode (3-Driverl2-Receiver) "..
5 V Only Driver/Receiver wllntegrated Standby Mode (3-Driver/3-Recelver) •.

Page I
2-3
2-9
2-14
2-20
2-26
2-29
2-95
2-98
2-700
2-700
2-700
2-706
2-714
2-700
2-926
2-929
2-929
2-929

2~922

2-924

INTERFACE
Device I
MC14C88S
MC14C89B, AS
MC1488
"
MC1489, A
MC26C31
MC26C32
MC34C86
MC34C87
MC145403
MC145404
MC145405
MC145406
MC145407
MC145408
MC145583
MC145705
MC145706
MC145707

Functional Selection Guide
1-4

MOTOROLA COMMUNICATIONS DEVICE DATA

MODEMS
Device #
MC145442
MC145443
MC145444
MC145447

Function
Single Chip 300 Baud Modem (CCITT V.21) ............................ .
Single Chip 300 Baud Modem (Bell 103) ................................ .
Single Chip 300 Baud Modem with DTMF Generator (CCITT V.21) •.......••
Calling Line 10 (CLIO) Receiver with Ring Detector ........•...••••••••.•.

Page #
2-748
2-748
2-756
2-765

Function
Broadband Interface Controller ........................................ .
Twisted Pair Modem ..........•.••.••••••••.•••..............•......••
Carrierband Modem ...•••••••••••.•••••••..••..............••••••••..
LocalTalk Adaptor ........... ;: ...................................... .
X.25 Protocol Controller .............................................. .
Multi-Link LAPD Controller CCITT 0.920/0.921 .•........................
Token Bus Controller .•........•.............•.•.••••••.•.. -..........•

Page #
MC68184UMlAD
MC68185UM/AD
MC68194UM/AD
MC68195UM/AD
MC68605UM/AD
MC68606UM/AD
MC68824UM/AD

NETWORK DEVICES
Device #
MC68184
MC68185
MC68194
MC68195
MC68605
MC68606
MC68824

PHASE-LOCKED LOOP (PLL) FREQUENCY SYNTHESIZERS
Device #
MC145106
MC145145-2
MC145146-2
MC145149
MC145151-2
MC145152-2
MC145155-2
MC145156-2
MC145157-2
MC145158-2
MC145159-1
MC145160
MC145161
MC145162
MC145166
MC145167
Mc::~45168

MCl45169
MCl45170
MC145173
MC145190
MC145191
MC145192
MC145200
MC145201,

Function
PLL Frequency Synthesizer. . . . . . . . . . . . .. . . . . . . • .. .. . .. . . . .. . . . .. . . . ...
4-Bit Data Bus Input PLL Frequency Synthesizer ..•••.••••....•..........
4-Bit Data Bus Input PLL Frequency Synthesizer •........•....•..••...•••
Dual PLL Frequency Synthesizer . • • . • . .. . . . .. . • . .. . . . . . • . . . . . • . • • • • • ...
Parallel-Input PLL Frequency Synthesizer (Single-Modulus Prescalers) ..•...
Parallel-Input PLL Frequency Synthesizer (Dual-Modulus Prescalers) .......
Serial-Input PLL Frequency Synthesizer (Single-Modulus Prescalers) ....•••
Serial-Input PLL Frequency Synthesizer (Dual-Modulus Prescalers) ••••• . • ••
Serial-Input PLL Frequency Synthesizer (Single-Modulus Prescalers) •••.•..
Serial-Input PLL Frequency Synthesizer (Dual-Modulus Prescalers) .••.. . • ..
Serial-Input PLL Frequency Synthesizer with Analog Phase Detector .•. . . . ..
4-Bit Parallel Dual PLL for 46/49 MHz Cordless Telephones. • • • . • • • . • • . . ...
Dual PLLfor 30/39 MHz Cordless Telephones. . . . . .. • • • • • • • • • . .. . . .. . . ...
60 MHz Universal Programmable Dual PLL Frequency Synthesizer •..•.....
4-Bit Parallel Dual PLL for 46/49 MHz Cordless Telephones. . . . . . . . . . • . • • •.
Serial-Input Dual PLL for 46/49 MHz Cordless Telephones ........•..•.••••
4-Bit Input Dual PLL for 46/49 MHz Cordless Telephones ........•••••.•...
Serial-Input Dual PLL for 46149 MHz Cordless Telephones •••••............
PLL Frequency Synthesizer with Serial Interface (160 MHz) .•.....•........
Dual Band PLL Frequency Synthesizer. . . .. . . . . • .. . .. .. . • • • • • • . • .. . . . ...
1.1 GHz PLL Frequency Synthesizer (30/130 MHz) .......•..••.•.••••.••.
1.1 GHz PLL Frequency Synthesizer. . .. . . • . . • • .. .. • • • .. • • . .. .. • . .. . . ...
Low Voltage 1.1 GHz PLL Frequency Synthesizer .........•...•..••••••.•
2.0 GHz PLL Frequency Synthesizer. . . .. . . . .. . • . .. . . • . • • • • • • . • • . • . . • ...
2.0 GHz PLL Frequency Synthesizer. • • .. . • • .. • • . • . • • . •• • • . . . . . . . . . . . ...

Page #
2-~95

2-502
2-513
2-524
2-535
2-538
2-542
2-546
2-550
2-553
2-565
2-574
2-581
2-587
2-5742-574
2-606
2-606
2-615
2-631
2-632
2-632
2-651
2-670
2-670

REMOTE CONTROL FUNCTIONS
Device#MCl4469
MCl4497
MC145026
MC145027
MC145028

Function
Addressable Asynchronous ReceiverlTransmltter •..........••.••••.••••.•
PCM Remote Control Transmitter. . . . . . .. . . . .. . .. .. . . . . • • • • .. • • • • • • • • ...
Encoder. . • . . . • . . • . . . . . . . . . . . . . • • . . . . • . . . . . . . . . . • . . . . . . • . . . . • . . . . • • .•
Decoder ........................•....•.........•.................•.•
Decoder .............•...•.••.••••••••••••....•.•••••..•....•.......

MOTOROLA COMMUNICATIONS DEVICE DATA

Page #
2-194
2-202
2-461
2-461
2-461

Functional Selection Guide
1-5

RF COMMUNICATIONS
Device #
MC2831A
MC2833
MC3356
MC3357
MC3359
MC3361B
MC3362
MC3363
MC3367
MC3371
MC3372
MC13055
MC13135
MC13136
MC13155
MC13156
MC13175
MC13176
MRFIC2001
MRFIC2002
MRFIC2003
MRFIC2004
MRFIC2006

Function
Low Power FM Transmitter System ........................................ .
Low Power FM Transmitter System ........................................ .
Wideband FSK Receiver ..........•.......................................
Low Power FM IF ................•...............................•......•
High Gain Low Power FM IF ...........................................••••
Low Power FM IF .....................................•....•••..•.•......
Low Power Dual Conversion FM Receiver .•.................................
Low Power Dual Conversion FM Receiver .................................. .
Low Voltage Single Conversion FM Receiver ................................ .
Low Power Narrowband FM IF ..........................................••.
Low Power Narrowband FM IF ...........................................•.
Wideband FSK Receiver ................................................. .
Dual Conversion Narrowband FM Receiver ................................. .
Dual Conversion Narrowband FM Receiver ................................. .
Wideband FSK Receiver ...................•••....•.......................
Wideband FM IF System •••••••••••••...•..••••....••.••••••••••••••••••••
UHF FMlAM Transmitter ...........................................•...•••
UHF FMlAM Transmitter ...................•.••....••••....•..............
900 MHz Downconverter LNAlMixer ....................................... .
900 MHz Transmit Mixer ................................................. .
900 MHz GaAs Antenna Switch ........................................... .
900 MHz Driver and Ramp .............................................•..
900 MHz Two Stage Power Amplifier ....................................... .

Page #
2-32
2-35
2-38

Function
Voice Switched ,Speakerphone with Microprocessor Interface .................. .
Voice Switched Speakerphone Circuit ...................................... .
Voice Switched Speakerphone Circuit ...................................... .

Page #
2-302
2-370
2-417

2-44
2-48
2-54
2-60
2-65
2-72
2-78
2-78
2-135
2-142
2-142
2-154
2-169
2-170
2-170
MRFIC2001/D
MRFIC2002lD
MRFIC2003lD
MRFIC2004lD
MRFIC20061D

SPEAKERPHONES
Device #
MC33218
MC34018
MC34118

SUBSCRIBER LOOP INTERFACE CIRCUITS (SLlCs)
Device #
MC3419-1L
MC33120
MC33121

Function
Subscriber Loop Interface Circuit ................................•..•.......
Subscriber Loop Interface Circuit .......................................... .
Low Voltage Subscriber Loop Interface Circuit ............................... .

Page #
2-119
2-232
2-262

VOICE CODING
Device #

Function

Page #

MC3417
MC3418
MC3517
MC3518
MC33110
MC34115
MC145402
MC145480
MC145500
MC145501
MC145502
MC145503
MC145505
MC145532
MC145540
MC145542
MC145554
MC145557
MC145564
MC145567

CVSD Modulator/Demodulator (3-Bit Algorithm) ............................. .
CVSD Modulator/Demodulator (4-Bit Algorithm) ........................•.•..•
CVSD Modulator/Demodulator (3-Bit Algorithm) ...............•..............
CVSD Modulator/Demodulator (4-Bit Algorithm) .............•••..•..•.•...•.•
Low Voltage Compander ...........................•.....•................
CVSD Modulator/Demodulators ........................................... .
Serial 13-Bit Linear Codec (AID and D/A) ................................... .
5 V PCM Codec-Filter .................................................... .
Codec-Filter (Mono-Circuit; 16-Pin) ...............•......................•..
Codec-Filter (Mono-Circuit; 18-Pin) ........................................ .
Codec-Filter (Mono-Circuit; 22-Pin) .........................................'
Codec-Filter (Mono-Circuit; 16-Pin) ....................................... ..
Codec-Filter (Mono-Circuit; 16-Pin) .........•...............................
ADPCM Transcoder ..................................................... .
ADPCM Codec .......................................•..................
CT2 Speech and Framing IC ....................•.........•................
PCM Codec-Filter (16-Pin) •.....................•................••.......•
PCM Codec-Filter (16-Pin) ................................................ .
PCM Codec-Filter (20-Pin) ................................................ .
PCM Codec-Filter (20-Pin) ................................................ .

2-101
2-101
2-101
2-101
2-220
2-402
2-689
2-822
2-854
2-854
2-854
2-854
2-854
2-875
2-890
2-906
2-907
2-907
2-907
2-907

Functional Selection Guide

1·6

MOTOROLA COMMUNICATIONS DEVICE DATA

OTHER FUNCTIONS
Device #
MJD243
MJD253
MJE270
MJE271
MPS6717
4N35/36/37

Function
4-A Silicon Power Transistor .............................................. .
4-A Silicon Power Transistor .............................................. .
NPN Power Transistor ................................................... .
PNP Power Transistor ................................................... .
NPN One Watt Amplifier Transistors ....................................... .
Optoisolators ........................................................... .

Page #
2-947
2-947
2-951
2-951
2-953
2-954

DISCONTINUED/NOT RECOMMENDED FOR NEW DESIGN
Device #

Function

MC14400
MC14401
MC14402
MC14403
MC14405
MC14408
MC14409
MC14410
MC14411
MC14412
MC14413-1, -2
MC14414-1, -2
MC14416
MC14417
MC14418
MC14419
MC142100
MC142103
MC143403
MC143404
MC145030
MC145031
MC145032
MC145033
MC145034
MC145035
MC145100
MC145411
MC145414
MC145415
MC145418
MC145419
MC145421
MC145422
MC145425
MC145426
MC145428
MC145429
MC145432
MC145433
MC145439
MC145440
MC145441
MC145445
MC145450
MC145601
MC145610
MC145611

Single-Chip Codec-Filter (Mono-Circuit)
Single-Chip Codec-Filter (Mono-Circuit)
Single-Chip Codec-Filter (Mono-Circuit)
Single-Chip Codec-Filter (Mono-Circuit)
Single-Chip Codec-Filter (Mono-Circuit)
Binary to Pulse Dialer
Binary to Pulse Dialer
2-of-8 Tone Encoder/Dialer
Bit Rate Generator
Universal Low Speed Modem (0-600 bps)
PCM Band-PasslLow-Pass Filter
PCM Dual Low-Pass Filter
Time Slot Assigner Circuit
Time Slot Assigner Circuit
Time Slot Assigner Circuit
2-of-8 Keypad-to-Binary Encoder
4 x 4 Crosspoint Switch with Control Memory
Encoder
Quad Line Driver
Quad Line Driver
Encoder/Decoder
Encoder
Decoder
Encoder/Decoder
Encoder
Decoder
4 x 4 Crosspoint Switch with Control Memory
Bit Rate Generator
Dual Tunable Low-Pass Sampled Filter
Dual Tunable Linear Phase Low-Pass Sampled Data Filter
80 kbps Digital Loop Transceiver (Master)
80 kbps Digital Loop Transceiver (Slave)
Universal Digital Loop Transceiver II (UDLT II)
Universal Digital Loop Transceiver (UDLT)
Universal Digital Loop Transceiver II (UDLT II)
Universal Digital Loop Transceiver (UDLT)
Data Set Interface
Teleset Audio Interface Circuit (TAlC)
2600 Hz Signaling Filter
Tunable Notch/Band-Pass Filter
Encoder/Decoder
300 Baud Modem Filter (Bell 103)
300 Baud Modem Filter (CCITT V.21)
300Baud Modem (BeIl103/CCITT V.21)
1200 Baud Modem (BeIl202lCCITT V.23)
Time Slot Interchange Circuit (TSIC)
Pulse Tone Dialer with Last Number Redial
PCM 8-Channel Conference Circuit

MOTOROLA COMMUNICATIONS DEVICE DATA

Functional Selection Guide

1-7

Functional Selection Guide
1-8

MOTOROLA COMMUNICATIONS DEVICE DATA

Technical Selection Guide
RF COMMUNICATIONS
AM and Wideband FM Transmitters

""

",

"t' :)L
<
~:~

MaxRF

Output ',"

In,~ut
Freq.

Max
M"d.

,

Fr~q.

Data
!'late
'"

Vce : ,Icc

MC13175

2-5 V

40 rnA

8.0
d9m

500 MHz

5MHz

10M

AM/FM Transmitter; Single Frequency
PLL, fOUT = 8 x fREF

P/648
D/7519

2-170

MC13176

2-5 V

40 rnA

8.0
d9m

1 GHz

5MHz

10M

AM/FM Transmitter; Single Frequency
PLL, fOUT = 32 x fREF

P/648
D/7519

2-170

Power

I"

'Case,!

Wideband Single Conversion Receivers

,

":"

,,12dB,I,,:,

'np~i:;:

,»"",

,Co I"'"

' Datii

'~~t~""

"

Vc;c'

,Icd

SINAD
Sensitivity
(Typ>

MC3356

3-9 V

25 rnA

30J.lV

200
MHz

10.7
MHz

Yes

Yes

50k

Includes squelch and data
shaper

P/738
DW/751D

2-38

MC13156

2-7 V

3mA

2J.lV

500
MHz

21.4
MHz

No

Yes

1M

CT-2 FM demodulator
split IF

DW/751E

2-169

"

;/',':"';
"'''t-~:";

'i"D,e"i,ce

,

""1

!'IF'
"F~eq.,

IF;'

"

Mute ::.!'I SS '

,~i;:j~),: 1'1);'

Suffix! ,,'

,~,,2\l~!L

>

):'caga,,

Wideband IFs

Narrowband FM Transmitters

MC2831A

3-8 V

5.0 rnA

-30d9m

50 MHz

50 kHz

4.8k

FM Transmitter - Includes low
battery checker, tone oscillator

P/648
D/7519

2-32

MC2833

3-8 V

10 rnA

-30 d9m to
+10d9m

150 MHz

50 kHz

4.8k

FM Transmitter - Includes two
frequency multiplier/amplifier
transistors

P/648
D/7519

2-35

Narrowband Single Conversion Receivers

MC3357

4-8 V

5mA

5J.lV

45 MHz

455 kHz

Yes

No

> 4.8k

Ceramic Quad
Detector/Resonator

P/648

2-44

MC3359

4-9 V

7mA

2J.lV

45 MHz

455 kHz

Yes

No

> 4.8k

Scan Output Option

P/707
DW/751D

2-48

MC33619

2-8 V

6mA

2J.lV

60 MHz

455 kHz

Yes

No

>4.8k

Lowest Cost Receiver

P/648
D/7519

2-54

MC3367

1-5V

1 rnA

1 J.lV

75 MHz

455 kHz

Yes

No

>4.8k

1 Cell Operation

DW/751F

2-72

MC3371

2-8 V

6mA

2J.lV

60 MHz

455 kHz

Yes

No

>4.8k

RSSI

P/648
D/7519

2-78

MC3372

2-8 V

6mA

2J.lV

60 MHz

455 kHz

Yes

No

> 4.8k

RSSI, Ceramic Quad
Detector/Resonator

P/648
D/7519

2-78

MOTOROLA COMMUNICATIONS DEVICE DATA

Technical Selection Guide
1-9

RF COMMUNICATIONS (continued)
Narrowband Dual Conversion Receivers

0.7J.lV

180
MHz

10.7
MHz

455
kHz

No

Yes

>4.8k

Includes buffered
VCOoutput

DWTl51E

2-60

MC3363

2-7 V

4mA

O.4J.lV

180
MHz

10.7
MHz

455
kHz

Yes

Yes

>4.8k

Includes RF
Preamp and Mute

DWTl51F

2-65

MC13135

2-7 V

4mA

IJ.lV

180
MHz

10.7
MHz

455
kHz

No

Yes

> 4.8k

Voltage buffered
RSSI, LC Quad
Detector

DWTl51E

2-142

MC13136

2-7 V

4mA

1 J.lV

180
MHz

10.7
MHz

455
kHz

No

Yes

>4.8k

Voltage buffered
RSSI, Ceramic
Quad Detector

DWTl51E

2-142

LOW-POWER OPERATIONAL AMPLIFIER

REMOTE CONTROL

Depends on
Decoder(1)

Depends on
Decoder(l)

Depends on
Decoder(1)

Simplex

MC145026

P/648

2-461

D/75 I 8

Decoder

P/648
DWTl51G

(I)See MC145027, MC145028

SWITCH MODE CONTROLLER

1000
(Totem Pole MOSFET
Driver Output)

4.2 to 12

Current

1.25 ± 2.0%

300

MC34129
MC33129

Oto

+ 70

-40 to + 85

P/646
DTl51A

2-446

P/646

2-446

DTl51 A

Technical Selection Guide
1-10

MOTOROLA COMMUNICATIONS DEVICE DATA

EIA-23215621V.28 DRIVERS/RECEIVERS

4

4

+5.0

EIA-232/EIA-562
V.28

MC14C89B
MC14C89AB

P/646,0/751A

2-9

4

+5.0

EIA-2321V.28

MC1489
MC1489A

P/646,0/751A

2-20

EIA-232/EIA-562
V.28

MC14C88B

P/646,0/751A

2-3

±7.0to±12

EIA-2321V.28

EIA-2321V.28; Onboard ring
monitor circuit
2-929

EIA-2321V.28; Charge Pump,
PowerOown

+5.0

EIA-422 DRIVERS/RECEIVERS

4

4

+5.0

Pin compatible with AM26LS31. Enable and
disable common to all four drivers. Typical ESO
protection of 2 KV.

MC26C31

P/648, 0/751 B

2-26

4

+ 5.0

Pin compatible wilh AM26LS32. Enable and
disable common to all four receivers. Typical ESO
protection of 2 KV.

MC26C32

P/648, 0/751 B

2-29

4

+5.0

Pin compatible with MC3486. Typical ESO
protection of 2 KV.

MC34C86

P/648, 0/751 B

2-95

+5.0

Pin compatible with MC3487. Typical ESO
protection of 2 KV.

MC34C87

P/648, 0/751 B

2-98

MOTOROLA COMMUNICATIONS DEVICE DATA

Technical Selection Guide
1-11

PHASE-LOCKED LOOP FREQUENCY SYNTHESIZERS

15@ 5V

20@ 5V

3.0 to 9.0

3.0 to 9.0

Two single-ended three-state
7.5@5V

Analog

7.5@5V

Single-ended three-state,
double-ended

MC145149

P/738
DW/751D

2-524

MC145159-1

P/738
DW/751D
FN/775

2-565

MC145145-2

P/707
DW/751D

2-502

MC145146-2

P/738
DW/751D

2-513

MC145151-2

P/710
DW/751F
FN1776

2-535

MC145152-2

P/710
DW/751F
FN/776

2-538

MC145155-2

P/707
DW/751D
FN/775

2-542

MC145156-2

P/707
DW/751D
FN/775

2-546

MC145157-2

P/648
DW/751G
FN/775

2-550

MC145158-2

P/648
DW/751G
FN/775

2-553

Parallel

MC145160

P/707
DW/751D

2-574

Serial

MC145161

P/648
DW/751G

2-581

MC145162

P/648
DW/751G

2-587

MC145166

P/648
DW/751G

2-574

Serial

No

4-Bit

Parallel

Double-ended

Single-ended three-state,
double-ended

60@3V

2.5 to 5.5

3.0 @3V

Two single-ended three-state

Serial

Yes

Parallel

100 @ 3 V
160 @ 5 V

2.5 to 6.0

3.0@3V
7.0 @5V

Single-ended three-state,
double-ended

No

30/130 @
5V

4.5 to 5.5

25@5V

Single-ended three-state,
Current source/sink

Yes

1100@5V

4.5 to 5.5

7.0 @5V

Current source/sink,
double-ended

Yes

4.5 to 5.5

Technical Selection Guide
1-12

MOTOROLA COMMUNICATIONS DEVICE DATA

TELECOM CIRCUITS

Audio Amplifiers

~~D
400 mW, 8.0 to 100 n, 2.0 to 16 V, differential outputs, chip-

2-437

disable input pin.

Complete Telephone Circuit
POTS circuit + MPU Dialing

2-313

Speech network, tone ringer, DC loop current interface,
DTMF dialer with serial port control

MC34010

2.7 to 7 V, no precision externals, 80 dB range, -40 to
+ 85'C, independent compressor and expander

MC33110

P/646
D/751 A

MC145412

P1707

2-721

Companders

Basic Compander

-Dialers
·.t••iE"t,'

PulselTone Repertory Dialer

10 number memory including LNR. Uses color burst XTAL.
3 x 4 or 4 x 4 keyboard compatibility. 3216B make break ratio
(MC145512 ONLY)

.~

.v

~v'nv

MC145512
Tone/Pulse Dialer

10 number memory including LNR plus 3 emergency numbers. Dial mode output pin. Uses color burst XTAL.

MC145416

P1738

2-730

Dual Tone Multiple Frequency
Receiver

Pin compatible with SS1204. Single +5 V supply. Detects all
16 tones. Provides guard time controls for improved speech
immunity. Output in 4-bit hexadecimal code.

MC145436

P/646
DW1751G

2-742

MC145472

FEl847B

2-775

MC1454LC72

FEl847B
FU847

2-775

MC145474

Ll736B

2-801

Integrated Services Digital Network (ISDN)

~1lII!I
Line Cards, NT1 s, Pair Gain,
ISDN Compatible Bridge Routers, ISDN Terminals

ANSI T1.601 compliant, pin selectable LTor NT operation, industry standard IDL interface, slave-slave timing mode, control
and status provided through four-wire serial control port.
500 mW die shrink version of the MC145472

NetworkTermination (NT1), PC
Based and Standalone ISDN
Terminal Adaptors, ISDN Telephone, ISDN Video Phones

Conforms to CCITT 1.430 and ANSI T1.605, pin selectable NT
and TE modes, Interchip Digital Link (IDL), serial control port
(SCP), full multiframing capabilities, NT1 star mode, SIT and
IDL loopbacks.

Line Cards, NT1 s, Pair Gain,
ISDN Compatible Bridge Routers, ISDN Terminals
NetworkTermination (NT1), PC
Based and Standalone ISDN
Terminal Adaptors, ISDN Telephone, ISDN Video Phones,
PBX Applications, Combination
Network TerminationlTerminal
Adaptor (NT1ITA)

1------+-----+-----1
MC145475

DW1751D

2-801

Enhanced version of the MC14LC5472, low power; 300 mW,
ANSI T1.601 compliant, pin selectable LT or NT operation, IDL
and GCI interfaces, timeslot assigner, parallel or serial control
ports

MC145572

FN1777
FEl824A

2-922

Conforms to CCITT 1.430 and ANSI T1.605, pin selectable NT
and TEmodes, Interchip Digital Link (IDL), serial control port
(SCP), full multiframing capabilities, NT1 star mode, SIT and
IDL loopbacks, backwards software compatible with the
MC145474175, low power consumption, general circuit interface (GCI), timeslot assigner, NT terminal mode, slave/slave
mode.

MC145574

Not
Available
until2Q94

2-924

MOTOROLA COMMUNICATIONS DEVICE DATA

Technical Selection Guide

1·13

TELECOM CIRCUITS (continued)
Modems
Single Chip 300 Baud Modem

CCITT V.21 compatible. Capable of driving -9 dBm into
600 Q. Internal mid-supply generator. Uses color burst XTAL.
Adjustable transmit level and CD delay timing.

MC145442

P1738
DW1751D

2-748

Single Chip 300 Baud Modem

Bell 103 compatible. Capable of driving -9 dBm into 600 Q.
Internal mid-supply generator. Uses color burst XTAL. Adjustable transmit level and CD delay timing.

MC145443

P1738
DW1751D

2-748

Single Chip 300 Baud Modem

CCITT V.21 compatible. Capable of driving 0 dBm into
600 Q. Uses color burst XTAL. Adjustable transmit level and
CD delay timing. On-chip DTMF generator and imprecise call
progress detection. 3-wire serial interface.

MC145444

H/804
DW17510

2-756

Adjust Box, Telephones, Fax
Machines, Answering Machines, Key Systems, Trans- .
action Terminals

Low-power mode, 3.5 V to 6.5 V operating range, high-performance Bell 202IV.23 demodulator, on chip ring detector,
pin selectable oscillator frequencies: 3.68 MHz, 3.58 MHz, or
455 kHz

MC145447

P/648
DW1751G

2-765

Subscriber Loop Interface Circuits (SLICs)
PBX Applications

All gains externally programmable, most BORSHT functions,
current limit adjustable to 100 mA

MC3419-1L

Ll726

2-119

Central Office, Remote
Terminals, PBX Applications

All gains externally programmable, most BORSHT functions,
current limit adjustable to 50 mA, 58 dB
Longitudinal Balance, -42 to -58 V

MC33120

P1738
FN1776

2-232

Central Office, Remote
Terminals, PBX Applications

All gains externally programmable, most BORSHT functions,
current limit adjustable to 50 mA, 58 dB
Longitudinal Balance, -21.6 to -42 V

MC33121

P1738
FN1776

2-262

Complete Speakerphone with
MPU Interface

All level detection, attenuators, and switching controls, mike
amp, MPU interface for: volume control, mode selection,
mike mute.

MC33218

P1724
DW1751E

2-302

Complete Speakerphone with
Speaker Amplifier

All level detection (2 pt.), attenuators, and switching controls,
mike and speaker amp

MC34018

PI710
DW1751F

2-370

Complete Speakerphone with
Hybrid, Filter

All level detection (4 pt.), attenuators, and switching controls,
mike amp with mute, hybrid, and filter

MC34118

PI710
DW1751F

2-417

Basic Phone Line Interface

Loop current interface, speech network, line length compensation, speech/dialing modes, Bell system compliant.

MC34014

P1707
D17510

2-345

Basic Phone Line Interface

Loop current interface, speech network, line length compensation, speech/dialing modes, Bell system and foreign
countries.

MC34114

P1707
D17510

2-384

European Speech Network

Loop current interface, speech network, line length compensation, speech/dialing modes, programmable masks for
French, UK, low voltages, and PABX systems.

TCA3388

DP1738
FP/751

2-943

Speakerphone Circuits

Speech Networks

Switching Regulator
For phone line power applications, soft start, current limiting,
2% accuracy

Technical Selection Guide

1-14

MOTOROLA COMMUNICATIONS DEVICE DATA

TELECOM CIRCUITS (continued)
Tone Ringers

Adjustable Tone Ringer

Single ended output, meets FCC requirements, adjustable
REN, different warble rates

MC34012
-1, -2,-3

P/626
01751

2-337

Adjustable Tone Ringer

Differential output, meets FCC requirements, adjustable
REN, different warble rates

MC34017
-1,-2,-3

P/626
01751

2-362

Adjustable Tone Ringer

Differential output, meets FCC requirements, adjustable
REN, different warble rates

MC34217

P/626
01751

2-362

Ring Signal Converter

Switching regulator to convert ringing voltage to regulated
DC output. Provides ring detect output

TCA3385

P/626
FP1751

2-935

ISDN, PABX, DSP Interface,
Cordless Telephone, Radio

5 V single power supply PCM codec-filter. Pin selectable
Mu-Law or A-Law companding with serial PCM interface

MC145480

P1738
DW1751 0

2-822

ISDN, Telephone Central Oflice, PABX, DSP Interface

PCM codec-filter with pin selectable Mu-Law or A-Law compandlng and serial PCM Interface

Voice Coding

2-954

MC145502

L/736
P1708
FN1776
U620
P/648
DW1751G

Digital Cordless Telephone
Base Station, Tl Multiplexer

5 V ADPCM transcoder that Is CCITT G.721 , G.723, and
G.726 compliant lor 24 and 32 kpbs with proprietary 16 kpbs
mode. Mu-Law and A-Law compatible.

MCI45532

U620
DW1751G

2-875

Digital Cordless Telephone!
Base Station, Voice Storage

PCM codee-filter with ADPCM transcoder that operates at
2.7 V. CCITT G.721, G.723, and G.726 compliant at 16, 24,
and 32 kpbs. Includes high-gain mic amp, receiver power
driver, auxiliary driver, sldetone and gain controls.

MCI45540

P1710
DW1751F

2-890

CT2 Digital Cordless
Telephone and Base Station

2.7 V ADPCM eodec with CT2 burst-mode control logic. This
device is a complete voice coder with framing and system
control features for CT2 applications.

MC145542

TBD

2-906

ISDN, Telephone Central 01fice, PABX, DSP Interface

Dual power supply PCM codec-filter. Industry standard pinout with serial PCM interface.

P/648
U620
DW1751G

2-907

P1738
L/732
DW1751 0
Voice Encoders/Decoders

MOTOROLA COMMUNICATIONS DEViCE DATA

Technical Selection Guide

1-15

Technical Selection Guide
1-16

MOTOROLA COMMUNICATIONS DEVICE DATA

Data Sheets

MOTOROLA COMMUNICATIONS DEVICE DATA

..

2-1

2·2

MOTOROLA COMMUNICATIONS DEVICE DATA

MOTOROLA

MC14C888

SEMICONDUCTOR-----TECHNICAL DATA

Advance Information
Quad Low Power Line Driver

QUAD LOW POWER
LINE DRIVER

The MC14C88S is a low power monolithic quad line driver, using SiMOS
technology, which conforms to EIA-232-D, EIA-562, and CCITT V.28. The
inputs feature TTL and CMOS compatibility with minimal loading. The outputs
feature internally controlled slew rate limiting, eliminating the need for external
capacitors. Power off output impedance exceeds 300 n, and current limiting
protects the outputs in the event of short circuits.
Power supply current is less than 160 ~A over the supply voltage range of
±4.5 to ±15 V. EIA-232-D performance is guaranteed with a minimum supply
voltage of ±6.5 V.
The MC14C88S is pin compatible with the MC1488, SN75188, SN75C188,
DS1488, and DS14C88. This device is available in 14 pin plastic DIP, and
surface mount packaging.
Features:
• SiMOS Technology for Low Power Operation «5.0 mW)

SILICON MONOLITHIC
INTEGRATED CIRCUIT

PSUFFIX
PLASTIC PACKAGE
CASE 646

• Meets Requirements of EIA-232-D, EIA-562, and CCITT V.28
• Quiescent Current Less Than 160 ~

• TTUCMOS Compatible Inputs
• Minimum 300

n Output Impedance when Powered Off

• Supply Voltage Range: ±4.5 to ±15 V
o SUFFIX
PLASTIC PACKAGE
CASE 751A
(SO-14)

• Pin Equivalent to MC1488
• Current Limited Output: 10 mA Minimum
• Operating Ambient Temperature: -40° to 85°C

PIN CONNECTIONS

Simplified Block Diagram
(Each Driver)

Vee

Output A

3

Input 61

4

Input 62

5

Output 6

6

Gnd

7

Output

(Top View)

ORDERING INFORMATION
Device
MC14C88BP
MC14C88BD

MOTOROLA COMMUNICATIONS DEVICE DATA

Temperature
Range
-40° to +85°C

Package
Plastic DIP
SO-14

MC14C88B
2-3

MAXIMUM RATINGS (TA

=+25°C, unless otherwise noted.)

Rating

Symbol

Value

Vee
VEE
Vee-VEE

+17
-17
34

Unit

Power Supply Voltage

Vdc

Vee(max)

VEE(mi~
(Vee-

EE)max

Input Voltage (All Inputs)

Vln

VEE-{)·3, VEE+39

Vdc

Applied Output Voltage, when Vee=VEE"Il V
Applied Output Voltage, when Vee=VEE=O V

Vx

VEE-6.0 V, Vee+6.O V
±15

Vdc

Output Current

10

Self Limiting

rnA

Operating Junction Temperature

TJ

-65, +150

·e

Devices should not be operated at these limits. The "Recommended Operating Conditions· table provides for actual
device operation.

RECOMMENDED OPERATING CONDITIONS
Characteristic

Symbol

Min

Vee
VEE

+4.5
-15

Typ

Input Voltage (All Inputs)

Yin

0

-

Applied Output Voltage (Vee=VEE=O V)

Vo

-2.0

0

Output DC Load

RL

3.0

Operating Ambient Temperature Range

TA

Power Supply Voltage

Max

Unit

+15
-4.5

Vdc

Vee

Vdc

+2.0

Vdc

7.0

kn

-40

-

+B5

°e

Min

Typ

Max

Unit

All limits are not necessarily functional concurrently.

ELECTRICAL CHARACTERISTICS (-40°C S TA S +85°C, unless otherwise noted.)"
Characteristic

Symbol

Supply Current (lout = 0, see Figure 2)
ICC @ 4.75 V S Vee, -VEE S 15 V
Outputs High
Outputs Low
lEE
Outputs High
Outputs Low

IlA
ICC (OH)
ICC (OL)
lEE (OH)
lEE (OL)

Output Voltage - High, Yin S O.B V (RL = 3.0 kn, see Figure 3)
Vee =+4.75 V, VEE =-4.75 V
Vee = +5.0 V, VEE = -5.0 V
Vee = +6.5 V, VEE = -6.5 V
Vee = +12 V, VEE = -12 V
Vee = +13.2 V, VEE =-13.2V (RL= 00)
Output Voltage - Low, Yin ;;, 2.0 V
Vee = +4.75 V, VEE = -4.75 V
Vee = +5.0 V, VEE = -5.0 V
Vee =+6.5 V, VEE =-6.5 V
Vee =+12V, VEE =-12 V
Vee = +13.2 V, VEE = -13.2 V (RL = 00)

VOL

-

-13.2
lOS

Output Source Resistance
(Vee = VEE = 0 V, -2.0 V S Vout S +2.0 V)

RO

VIL
VIH
@

-160
-160
3.7
4.0
5.0
10

Output Short Circuit Current'· (see Figure 4) (Vee = IVEEI = 15 V)
Normally High Output, shorted to ground
Normally Low Output, shorted to ground

• Typ,cals reflect performance

-

-

VOH

~

Input Voltage
Low Level
High.Level

-

3.B
4.3
6.1
10.5
13.2
-3.B
-4.2
-6.0
-10.5
-13.2

160
160

-

-

13.2
-3.7
-4.0
-5.0
-10

-

rnA

+10

-

-10
+35

300

-

-

0
2.0

-

O.B
Vee

-35

Vdc

Q

Vdc

TA = 2S'C

•• Only one output shorted at a time, for not more than 1 second.

MC14C888

2-4

MOTOROLA COMMUNICATIONS DEVICE DATA

ELECTRICAL CHARACTERISTICS CONTINUED (-40°C $ TA $ +B5°C, unless otherwise noted.)'
Characteristic
Input Current
Vin = 0 V, VCC = IVEEI = 4.75 V
Vin = 0 V, VCC = IVEEI = 15 V
Vin = 4.5 V, VCC = IVEEI = 4.75 V
Vin = 4.5 V, VCC = IVEEI = 15 V

Symbol

Min

Typ

Max

-10
-10
0
0

-0.1
-0.1
+0.1
+0.1

0
0
+10
+10

Min

Typ

Max

Unit

!1A

lin

TIMING CHARACTERISTICS (-40°C $ TA $ +85°C, unless otherwise noted.)'
Characteristic
Output Rise Time
VCC = 4.75 V, VEE = -4.75 V
-3.3 V "VO" 3.3 V
CL=15pF
CL = 1000 pF
-3.0 V "VO" 3.0 V
CL = 15 pF
CL = 1000 pF
VCC= 12.0 V, VEE=-12.0V
-3.0 V,,; VO"; 3.0 V
CL = 15 pF
CL = 2500 pF
10%"VO,,90%
CL = 15 pF
Output Fall Time
VCC = 4.75 V, VEE = -4.75 V
3.3 V" Vo ";-3.3 V
CL = 15 pF
CL = 1000 pF
3.0 V" Vo ";-3.0 V
CL= 15 pF
CL = 1000 pF
VCC = 12.0 V, VEE = -12.0 V
3.0 V" Vo ";-3.0 V
CL = 15 pF
CL = 2500 pF
90%,,;VO,,;10%
CL= 15 pF
Output Slew Rate, 3.0 kQ < RL < 7.0 kQ, 15 pF < CL < 2500 pF
Propagation Delay A (CL = 15 pF, see Figure 1)
VCC = 12.0 V, VEE = -12.0 V
Input to Output - Low to High
Input to Output - High to Low
Propagation Delay B (CL = 15 pF, see Figure 1)
VCC = 4.75 V, VEE = -4.75 V
Input to Output - Low to High
Input to Output - High to Low
• TYPlcals reflect pertormance

@

Symbol

Unit
Il s

tRl
0.22
0.22

0.66
1.52

2.1
2.1

0.20
0.20

0.51
1.16

1.5
1.5

0.20
0.20

0.62
0.82

1.5
1.5

0.53

1.41

3.2

tR2

tR3
Ils
tFl
0.22
0.22

0.93
1.28

2.1
2.1

0.20
0.20

0.72
1.01

1.5
1.5

0.20
0.20

0.70
0.94

1.5
1.5

0.53

1.71

3.2

tF2

tF3
SR

4.0

-

30

VlIlS
Ils

tpLH
tpHL

-

tpLH
tpHL

-

-

0.9
2.3

3.0
3.5

0.4
1.5

2.0
2.5

TA =25'C

MOTOROLA COMMUNICATIONS DEVICE DATA

MC14C888
2-5

Figure 1. Timing Diagram

J-

S.G.
OV

1.5 V

!-tPHt
~---VOH

VOUT

NOTES: S.G. set to: I = 20 kHz lor Propagation Delay
A
and I = 64 kHz lor Propagation Delay 6; DU\
Cycle = 50%; tR, tF S 5.0 ns
out

90%

'--1---------.....J-------

3.3 V ---------1~
3.0V - - - - - + 1

---~-+~-----------------iYH~~-------OV

-----VOL

STANDARDS COMPLIANCE
The MC14C88 is designed to comply with EIA-232-D
(formerly RS-232), the newer EIA-562 (which is a higher
speed version of the EIA-232), and CCITT's V.28. EIA-562
was written around modern integrated circuit technology,
whereas EIA-232 retains many of the specs written around
Parameter
Maximum Data Rate

the electro-mechanical circuitry in use at the time of its
creation. Yet the user will find enough similarities to allow
a certain amount of compatibility among equipment built to
the two standards. Following is a summary of the key
specifications relating to the systems and the drivers.
EIA-562

EIA-232-D

38.4 kbaud Asynchronous
64 kbaud Synchronous

20 kbaud

Maximum Cable Length

50 feet

Based on cable capacitance/data rate

Maximum Slew Rate

S 30 ViIlS anywhere on the waveform

S 30 V/IlS anywhere on the waveform
~ 4.0 ViIlS between +3.0 and -3.0 V

Transition Region

-3.0 to +3.0 V

-3.3 to +3.3 V

Transition TIme

For UI ~ 25 ms, tR S 1.0 ms
For 25 ms > UI > 1251!S, tR S 4% UI
For UI < 1251ls, tR S5.0 Ils

For UI ~ SOils, 220 ns 
u

::;

~

r-~:!~~~~~f:::::::::::t-

~VCC--+---='----1

'"

Il.
Il.

=>
en

~u

8.0

4.0 1---'I===---t__
Vin
(0.8 or 2.0 V)

0

.

VEE

o -8.0 I-_-+~~~:;.:::,,~_-I_

-55

IE~)

u

-110

-121---+--

IEE(Ol)
4.0

32

-16~--~--~--~--~--~-~~

6.0

8.0

10

12

14

4.0

16

6.0

8.0

VCC AND -VEE. (V)

30

g§

=>
u

....
5
lE
u
tc

~

15

.. 1
I
~SC Normally low Output

-----

20
10

Vin

r - (0.8 or 2.0 V)
-10

...............

en

g-20

I---

-30
4.0

6.0

I

VCC

8.0

~

~,~
12

MOTOROLA COMMUNICATIONS DEVICE DATA

§;

0

16

I

14

16

I
VOH@VCC=-VEP4.5V

I
VOL

@ VCC

=-VEE = 4.5 V

VOL

@ VCC

=-VEE = 12 V

-5.0
-10

:SC Normall~ High Output
I'
i
I

10

5.0

5Il.
5o

I

VCC AND -VEE. (V)

w

!:i'"

-=-

I

14

VOH @VCC=-VEE=12V
10

I

12

Figure 5. Typical Output Voltage
versus Temperature

I

i'fi

10
VCC AND -VEE. (V)

Figure 4. Typical Short Circuit Current
versus Supply Voltage

l....

t Vout

Rl

~ -4.0

-15
-40

I

I
+22
TA. AMBIENT TEMPERATURE (OC)

Rl=3.0 kQ
+85

MC14C888

2·7

APPLICATIONS INFORMATION
Description
The MC14C88 was designed to be a direct replacement
for the MC1488 in that it meets all EIA-232 specifications.
However, Use is extended as the MC14C88 also meets the
faster EIA-562 and CCITT V.28 specifications. Slew rate
limited outputs conform to the mentioned specifications and
eliminate the need for external output capacitors. Low power
consumption is made possible by BiMOS technology. Power
supply current is limited to less than 160 !lA, plus load
currents over the supply voltage range of ±4.5 V to ±15 V
(see Figure 2).
Outputs
The output low or high voltage depends on the state of
the inputs, the load current, and the supply voltage (see
Table 1 and Figure 3). The graphs apply to each driver regardless of how many other drivers within the package are
supplying load current.

input voltage drop below VEE by more than 0.3 V or rise
above VEE by more than 39 V, excessil(e currents will flow
at the input pin. Open input pins are equivalent to logic high,
but good design practices dictate that inputs should never
be left open.
Operating Temperature Range
The ambient operating temperature range is listed as -40°
to +85°C and meets EIA-232-D, EIA-562 and CCITT V.28
specifications over this temperature range. The maximum
ambient temperature is listed as +85°C. However, a lower
ambient may be required depending on system use, i.e. specifically how many drivers within a package are used, and
at what current levels they are operating. The maximum power which may be dissipated within the package is determined
by:
PD

Table 1. Function Tables

=

where: RaJA the package thermal resistance (typically,
100°CIW for the DI P package,125°CIW for the
SOIC package);
TJmax = the maximum operating junction
temperature (150°C); and
TA = the ambient temperature.

Driver 1
Input A

Output A

H
L

L
H

Drivers 2 through 4
Input "1

Input "2

Output"

H
L
X

H
X
L

L
H
H

H = High level, L = Low level, X = Don't care.

Driver Inputs
The driver inputs determine the state of the outputs in accordance with Table 1. The nominal threshold voltage for the
inputs is 1.4 Vdc, and for proper operation, the input voltages
should be restricted to the range Gnd to Vcc. Should the

MC14C888

2-8

- T.lmax - TA
~ JA
max -

PD = { [(VCC - VOH) • 1I0HI] or [ (VOL - VEE) •
1I0LI] leach driver + (VCC • ICC) + (VEE· lEE)
where: VCC and VEE are the positive and negative
supply voltages;
VOH and VOL are measured or estimated from
Figure 3;
ICC and lEE are the quiescent supply currents
measured or estimated from Figure 2.
As indicated, the first term (in brackets) must be calculated
and summed for each of the four drivers, while the last terms
are common to the entire package.

MOTOROLA COMMUNICATIONS DEVICE DATA

MOTOROLA

SEMICONDUCTOR-----TECHNICAL DATA

Advance Information
Quad Low Power Line Receiver

MC14C89B
MC14C89AB

QUAD LOW POWER
LINE RECEIVER

The MC14C89B and MC14C89AB are low power monolithic quad line
receivers, using bipolar technology, which conform tothe EIA-232-E, EIA-562 and
CCITT V.28 Recommendations. The outputs feature LSTTL and CMOS
compatibility for easy interface to +5.0 V digital systems. Internal time-domain
filtering eliminates the need for external filter capacitors in most cases.
The MC14C89B has an input hysteresis of 0.35 V, while the MC14C89AB
hysteresis is 0.95 V. The response control pins allow adjustment of the threshold
level if desired. Additionally, an external capacitor may be added for additional
noise filtering.
The MC14C89B and MC14C89AB are each available in a 14 pin dual-in-line
plastic DIP and SOIC package.
Features:
• Low Power Consumption

•

-$

14

PSUFFIX
PLASTIC PACKAGE
CASE 646

• Meets EIA-232-E, EIA-562, and CCITT V.28 Recommendations
• TTUCMOS Compatible Outputs
• Standard Power Supply: + 5.0 V ± 10%

DSUFFIX
PLASTIC PACKAGE
CASE 751A
(SO-14)

• Pin Equivalent to MC1489, MC1489A, TI's SN75C189/A, SN75189/A and
National Semiconductor's DS14C89/A
• External Filtering Not Required in Most Cases
• Threshold Level Externally Adjustable

PIN CONNECTIONS

• Hysteresis: 0.35 V for MC14C89B, 0.95 V for MC14C89AB
• Available in Plastic DIP, and Surface Mount Packaging
Input A

• Operating Ambient Temperature: -40° to +85°C

VCC

Response
Control A

InputD
Response
Control D

Output A

Simplified Block Diagram
(Each Receiver)

Input B

OutputD

Response
Control B
VCC

Input

Input
C
Response
Control C

Output B
Ground

0+--._-...,

OutputC

(Top View)
Response o-t--_-~
Control

t--f--jI---0 Output
ORDERING INFORMATION
Device

Package

MC14C89BP

Plastic DIP

MC14C89BD

SO-14

MC14C89ABP
MC14C89ABD

MOTOROLA COMMUNICATIONS DEVICE DATA

Temperature
Range

-40° to +85°C

Plastic DIP
SO-14

MC14C89B.MC14C89AB
2-9

MAXIMUM RATINGS
Rating
Power Supply Vollage
VCC(max)
VCC(min)

Symbol

Value

VCC

+ 7.0
-0.5

Unit
Vdc

Input Voltage

Yin

±30

Vdc

Output Load Current

10

Self-Limiting

-

Junction Temperature

-65, +150
°C
TJ
..
..
Devices should not be operated at these limits. The "Recommended Operating Conditions" table provides lor actual
device operation.

RECOMMENDED OPERATING CONDITIONS
Characteristic
Power Supply Voltage
Input Vollage
Output Current Capability
Operating Ambient Temperature
All limits are not necessanly luncllonal concurrently.

Symbol

Min

Typ

Max

Unit

VCC

4.5

5.0

5.5

Vdc

Yin

-25

25

Vdc

10

-7.5

6.0

rnA

TA

-40

-

85

°C

Min

Typ

Max

Unit

-

330

700

3.5
3.5
2.5
2.5

3.8
4.8
3.7
4.7

-

-

0.1
0.1

0.4
0.4

-35

-

-13.9
+10.3

35

0.75
1.6
0.75
1.0

0.95
1.90
0.95
1.3

1.25
2.25
1.25
1.5

Vdc

3.0

5.5

7.0

kO

Min

Typ

Max

Unit

-

0.08

0.30

I1S

-

3.35
2.55

6.0
6.0

liS

1.0

1.5

-

liS

ELECTRICAL CHARACTERISTICS (-40°C:;; TA:;; 85°C, unless otherwise noted.)*
Characteristic

Symbol

Supply Current (lout = 0)
ICC @ +4.5 V" VCC" +5.5 V

ICC

Output Voltage - High, Vin " 0.4 V (See Figures 2 and 3)
VCC=4.5V
lout = -20 IlA
VCC=5.5V
lout = -3.2 rnA
VCC=4.5V
VCC=5.5V
Output Voltage - Low, Vin ;, 2.4 V
lout = 3.2 rnA
VCC=4.5V
VCC=5.5V

VOH

Output Short Circuit Current" (VCC = 5.5 V, see Figure 4)
Normally High Output shorted to ground
Normally Low Output shorted to V

lOS

VOL

cc

Input Threshold Voltage (V CC = 5.0 V)
(MC14C89AB, see Figure 5)
Low Level
High Level
(MC14C89B, see Figure 6)
Low Level
High Level

VIL
VIH
VIL
VIH

Input Impedance (+4.5 V < VCC < +5.5 V -25 V < Vin < +25 V)

IlA
Vdc

-

rnA

-

Typlcals reflect perlorrnance @ TA = 25°C
•• Only one output shorted at a time, lor not more than 1.0 seconds.

TIMING CHARACTERISTICS (TA = +25°C, unless otherwise noted.)
Characteristic
OutputTransition Time (10% to 90%)
4.5 V "VCC ,,5.5 V
Propagation Delay Time
4.5 V "VCC" 5.5 V
Output Low-to-High
Output High-to-Low
Input Noise Rejection (see Figure 9)

MC14C89B.MC14C89AB
2-10

Symbol

IT

tpLH
tpHL

MOTOROLA COMMUNICATIONS DEVICE DATA

Figure 1. Timing Diagram

J-

S.G.

OV
VCC

1.5 V

!-IPHL
~--_+-----------

90%

____+___r - - - voH

VOUI

Nole: S.G. sel 10: 1= 20 kHz;
Duty Cycle = 50%;
lA, IF :;; 5.0 ns

Vout

I'-----------J~--------~--------VOL

STANDARDS COMPLIANCE
circuitry in use at the time of its creation. Yet the user will
find enough similarities to allow a certain amount of
compatibility among equipment built to the two standards.
Following is a summary of the key specifications relating to
the systems and the receivers.

The MC14C89B and MC14C89AB are designed to comply
with EIA-232-E (formerly RS-232), the newer EIA-562 (which
is a higher speed version of the EIA-232), and CCITT V.2B
Recommendations. EIA-562 was written around modern
integrated circuit technology, whereas EIA-232 retains many
of the specifications written around the electro-mechanical
Parameter

EIA-232-E

Max Data Rate

EIA-562
38.4 kBaud Asynchronous
64 kBaud Synchronous

20 kBaud

Max Cable Length

SO feet

Based on cable capacitance/data rate

Transition Region

-3.0 V to +3.0 V

-3.0 V to +3.0 V

MARK (one, off)

More negative than -3.0 V

More negative than -3.3 V

SPACE (zero, on)

More positive than +3.0 V

More positive than +3.3 V

Fail Sale

Output =Binary 1

Output =Binary 1

Open Circuit Input Voltage

< 12.01V

Not Specified

Slew Rate (at the driver)

:;; 30 V/JlS anywhere on the waveform

:;; 30 V/JlS anywhere on the waveform,
~ 4.0 VlJls between +3.0 V and -3.0 V

Loaded Output Voltage (at the driver)

5.0 V :>IVOI:> 15 V for loads between
3.0 kQ and 7.0 kQ

IVOI ~ 3.7 V for a load of 3.0 kQ

Figure 3. Typical Output Voltage versus Temperature

Figure 2. Typical Output versus Supply Voltage

5.
0

VOH(IO~I =

4.
~
w 0

20/lA)

VOH(l o 't = -32 rnA)

~



I:::l
0I:::l

0

9

-

I

MC1~CB9A

5

o

-

~ 4
0
w

B
MC14CB9B
TA=25'C _



0

~

2

0

0

I:::l
0-

2.
0

0

9

1.
0

o

4.5

VOL(loul = 3.2 rnA)
4.7

4.9
5.1
VCC, SUPPLY VOLTAGE (V)

MOTOROLA COMMUNICATIONS DEVICE DATA

c

VOH(loul = - 0 JlA)

VOH(loul = J.2 rnA)

MC14CB9AB
MC14C89B
VCC=5V

0
1
0
VOL(lout = 3.2 rnA)

5.3

5.5

~o

-7.5
25
57.5
TA, AMBIENTTEMPEAATUAE ('C)

85

MC14C89B.MC14C89AB
2-11

Figure 5. Typical Threshold Voltage
versus Temperature

Figure 4. Typical Short Circuit Current
versus Temperature
2
0

15

i

10

!z
~

5

U
I-

0

g5

13a:

Normally Low Output Shorted to VCC

1
8

~

1
6

'"~

MC14C89A
B
MC14C89B
VCC=5.5V

0

en
w
a:

~-5.0

:J:

a:

II-

~

::>

-15
--40

"£;

Nonnally High Output Shorted to Ground
-7.5

25

57.5

MC14C89AB
4.5 V < VCC <5.5 V

0

--'
0

:J:

en -10

VIH

"C:.w
'C

1
4
1
2
1
0

VIL
-7.5

85

"w~
'"~
0

>

5
0

MC14C89B
4.5V

0

--'
0

:J:

en
w
a:

:J:

II-

::>

"-

£;

0

1
4

--'
0

VIH

en
w
a:

:J:

lI-

::>

"£;

VIL
-7.5

4
0
3
0

:J:

1
2
1
0

57.5

2
0

\ \
\
\

1
0

57.5

VIL@Vbat=-10V

..........

-=

I'--

-=

~~at=-3.0V--

10kQ

TA, AMBIENT TEMPERATURE (OC)

C

+ RRC

..i Vbat

NominalVIL

85

f1t
n.

\

I
25

85

Figure 7. Typical Effect of Response
Control Pin Bias

Figure 6. Typical Threshold Voltage
versus Temperature
2
0

25

TA, AMBIENTTEMPERATURE (0C)

TA, AMBIENTTEMPERATURE (OC)

20kQ

30kQ

-

4.5 V < VCC < 5.5 V
I
40kQ
50kQ

BIAS RESISTANCE (RRcl

Figure 8. Typical Noise Pulse Rejection
5.
0
~
w

0

::>

t:::
"::;;
--'

«

w

en

--'
::>

"-

c

W

4.
5

MC14C89AB
MC14C89B
--\----I-----l---+-- Pulse Rate = 300 kHz
RC Pin Open

4.
0
3.
5
3.
0
2.
5

1.6

1.8

2.0

2.2

2.4

2.6

2.8

PW, INPUT PULSE WIDTH (l1s)

MC14C89B.MC14C89AB
2-12

MOTOROLA COMMUNICATIONS DEVICE DATA

APPLICATIONS INFORMATION
Description
The MC14CB9AB and MC14CB9B are designed to be
direct replacements for the MC14B9A and MC14B9. Both
devices meet all the EIA-232 specifications and also the
faster EIA-562 and CCITT V.28 specifications. Noise pulse
rejection circuitry eliminates the need for most response
control filter capacitors but does not exclude the possibility
as filtering is still possible at the Response Control (RC) pins.
Also, the Response Control pins allow for a user defined
selection of the threshold voltages. The MC14CB9AB and
MC14CB9B are manufactured with a bipolar technology
using low power techniques and consume at most 700 /lA,
plus load currents with a +5.0 V supply.
Outputs
The output low or high voltage depends on the state of
the inputs, the load current, the bias of the Response Control
pins, and the supply voltage. Table 1 applies to each receiver,
regardless of how many other receivers within the package
are supplying load current.
Table 1. Function Table
Receivers
Output·
Input·
H
L
H

L

·The asterisk denotes A, B, C, or D.

Receiver Inputs and Response Control
The receiver inputs determine the state of the outputs in
accordance with Table 1. The nominal VIL and VIH thresholds
are 0.95 V and 1.90 V respectively for the MC14CB9AB. For
the MC14C89B, the nominal VIL and VIH thresholds are 0.95
and 1.30, respectively. The inputs are able to withstand
± 30 V referenced to ground. Should the input voltage
exceed ground by more than ± 30 V, excessive currents will
flow at the input pin. Open input pins will generate a logic
high output, but good design practices dictate that Inputs
should never be left open.
The Response Control (RC) pins are coupled to the inputs
through a resistor string. The RC pins provide for adjustment
of the threshold voltages of the IC while preserving the
amount of hysteresis. Figure 10 shows a typical application
to adjust the threshold voltages. The RC pins also provide
access to an internal resistor string which permits low pass
filtering of the input signal within the IC. Like the input pins,
the RC pins should not be taken above or below ground by
more than ± 30 V or excessive currents will flow at these
pins. The dependence of the low level threshold voltage (VIL)
upon RRC and Vbat can be described by the following
equation,
VIL '" {VO.09 - Vba{ RRC (1

(5.32 kn + 6.67

~

~~5

+n2 .02 kn ] } (1)

~~~6 n 2 )

505 n

VIH can be found by calculating for VIL using equation (1)
then adding the hystereSiS for each device (0.35 for the

MOTOROLA COMMUNICATIONS DEVICE DATA

MC14CB9B or 0.95 V for the MC14CB9AB). Figure 7 plots
equation (1) for two values of Vbat and a range of RRC.
If an RC pin is to be used for low pass filtering, the
capacitor chosen can be calculated by the equation,
CRC '"

1

(2)

2.02 kn 2/t L3 dB

where f-3 dB represents the desired-3 dB roll-off frequency of
the low pass filter.
Figure 10. Application to Adjust Thresholds

Input Pin}:esponse Control Pin
RRC

+

i-Vbat
Another feature of the MC14CB9AB and MC14CB9B is
input noise rejection. The inputs have the ability to ignore
pulses which exceed the VIH and VIL thresholds but are less
than 1.0 !1S in duration. As the duration of the pulse exceeds
1.0 Ils, the noise pulse may still be ignored depending on
its amplitude. Figure 8 is a graph showing typical input noise
rejection as a function of pulse amplitude and pulse duration.
Figure B reflects data taken for an input with an unconnected
RC pin and applied to the MC14C89AB and MC14C89B.
Operating Temperature Range
The ambient operating temperature range is listed as
-40°C to +85°C, and the devices are designed to meet the
EIA-232-E, EIA-562 and CCITT V.28 specifications over this
temperature range. The Timing Characteristics are
guaranteed to meet the specifications at +25°C. The
maximum ambient operating temperature is listed as +85°C.
However, a lower ambient may be required depending on
system use, (i.e."specifically how many receivers within a
package are used) and at what current levels they are
operating. The maximum power which may be diSSipated
within the package is determined by:
PD(max)

=

=

TJ(max)-TA
RaJA

TJ(max)

thermal resistance (typ., 1OO°CIW for the
DIP and 125°CIW for the SOIC packages);
maximum operating junction temperature
(150°C); and
ambient temperature.

where: VCC
VOH, VOL

{[(VCC - VOH) • ilOHI] or
[(VoLl • ilOUneach receiver +(VCC • ICC)
positive supply voltage;
measured or estimated from Figure 2
and 3;
measured quiescent supply current.

where: RaJA

=
TA =
PD =

ICC

=
=
=

As indicated, the first term (in brackets) must be calculated
and summed for each of the four receivers, while the last
term is common to the entire package.

MC14C89B.MC14C89AB

2-13

MOTOROLA

-

SEMICONDUCTOR
TECHNICAL DATA

MC1488
QUAD MDTL LINE DRIVER
R8-232C

QUAD LINE DRIVER

SILICON MONOLITHIC
INTEGRATED CIRCUIT

The MC1488 is a monolithic quad line driver designed to interface data terminal equipment with data communications equipment
in conformance with the specifications of EIA Standard No. RS·232C.
Features:
•

Current Limited Output
±10 rnA typ

•

Power-Off Source Impedance
300 Ohms min

L SUFFIX
CERAMIC PACKAGE
CASE 632

• Simple Slew Rate Control with External Capacitor
•

Flexible Operating Supply Range

•

Compatible with All Motorola MDTL and MTTL Logic Families

DSUFFIX
PLASTIC PACKAGE
CASE 751A
14
(SO-14)

P SUFFIX
PLASTIC PACKAGE
CASE 646

#

.
1':'

PIN CONNECTIONS

TYPICAL APPLICATION
INTERCONNECTING
CABLE

LINE DRIVER

MCI488

LINE RECEIVER
MCI489

..r--, "-

---i
"1.. _ _ "

I

~

_'NTERCONNECTING

MOlL LOGIC INPUT~"--

CABLE

I

~MDTl LOGIC OUTPUT

CIRCUIT SCHEMATIC
(1/40F CIRCUIT SHOWN)
VCC 1 4 0 - - - - - -.....- - - - - - -.....- - -.....- - - - , - - - ,
B.2t
PINS 4, 9, 12 OR 2
INPUT

INPUT
PINS5, 10, 13

70

300
OUTPUT
PINSS,B,l1 OR 3

10k
lk

70

VEE 10------~---~----~--4-----4---~
MDTL and MTTL are trademarks of Motorola Inc.

MC1488
2-14

MOTOROLA COMMUNICATIONS DEVICE DATA

MAXIMUM RATINGS (TA = + 25"C unless otherwise noted.)
Rating

Symbol

Value

Unit

Power Supply Voltage

VCC
VEE

+15
-15

Vdc

Input Voltage Range

VIR

-15'" VIR '"
7.0

Vdc

Output Signal Voltage

Vo

±15

Vdc

Po
1/R9JA

1000
6.7

mW
mWI"C

Power Derating (Package Limitation, Ceramic
and Plastic Dual-ln·Line Package)
Derate above TA = + 25"C
Operating Ambient Temperature Range

TA

Storage Temperature Range

Tstl'l

ELECTRICAL CHARACTERISTICS (VCC

=

+9.0 ± 1% Vdc, VEE

=

o to

-9.0 ± 1% Vdc, TA

=

Characteristic

Figure

Symbol

Input Current -

Low Logic State (VIL

1

IlL

Input Current -

High

= 0)
Logic State (VIH = 5.0 V)

1

IIH

2

VOH

Output Voltage - High Logic State
(VIL = 0.8 Vdc, RL = 3.0 kn, VCC
(VIL = 0.8 Vdc, RL = 3.0 kn, VCC

=
=

+ 9.0 Vdc, VEE = - 9.0 Vdc)
+ 13.2 Vdc, VEE = - 13.2 Vdc)

Output Voltage - Low Logic State
(VIH = 1.9 Vdc, RL = 3.0 k!l, VCC
(VIH = 1.9 Vdc, RL = 3.0 kn, VCC

=
=

+ 9.0 Vdc, VEE = - 9.0 Vdc)
+ 13.2 Vdc, VEE = -13.2 Vdc)

2

"C

+75

-65 to + 175

"C

0 to 75"C unless otherwise noted.)
Min

-

Typ

Max

Unit

1.0

1.6

mA

-

10

p.A
Vdc

+6.0
+9.0

+7.0
+ 10.5

-

-6.0
-9.0

-7.0
-10.5

-

Vdc

VOL

Positive Output Short-Circuit Current (1)

3

10S+

+6.0

+10

+12

mA

Negative Output Short-Circuit Current (1)

3

10S-

-6.0

-10

-12

mA

300

=

=

=

4

ro

Positive Supply Current (RI = x)
(VIH = 1.9 Vdc, VCC = + 9.0 Vdc)
(VIL = 0.8 Vdc, VCC = +9.0 Vdc)
(VIH = 1.9 Vdc, VCC = + 12 Vdc)
(VIL = 0.8 Vdc, VCC = + 12 Vdc)
(VIH = 1.9 Vdc, VCC = + 15 Vdc)
(VIL = 0.8 Vdc, VCC = + 15 Vdc)

5

ICC

Negative Supply Current (RL = x)
(VIH = 1.9 Vdc, VEE = - 9.0 Vdc)
(VIL = 0.8 Vdc, VEE = - 9.0 Vdc)
(VIH = 1.9 Vdc, VEE = -12 Vdc)
(VIL = 0.8 Vdc, VEE = -12 Vdc)
(VIH = 1.9 Vdc, VEE = -15 Vdc)
(VIL = 0.8 Vdc, VEE = -15 Vdc)

5

Output Resistance (VCC

Power Consumption
(VCC = 9.0 Vdc, VEE
(VCC = 12 Vdc, VEE

VEE

0, IVol

±2.0 V)

-

-

mA

-

-

+15
+4.5
+19
+5.5

-

+20
+6.0
+25
+7.0
+34
+12

-

-

-

-13

-

-

-

333
576

lEE

-18

-

-

-17
-500
-23
-500
-34
-2.5

= - 9.0 Vdc)
= -12 Vdc)

Propagation Delay Time

(ZI

Fall Time

(zi

Propagation Delay Time

(ZI

Rise Time

(ZI

= 3.0
= 3.0
= 3.0
= 3.0

=

+90 +1%
- Vdc VEE

=

-90 +1%
Vdc, TA
-

mA
p.A
mA
p.A
mA
mA
mW

Pc

SWITCHING CHARACTERISTICS (VCC

Ohms

=

+25"C.)

k and 15 pF)

6

tpLH

-

275

350

ns

k and 15 pF)

6

tTHL

45

75

ns

k and 15 pF)

6

tpHL

-

110

175

ns

k and 15 pF)

6

tTLH

-

55

100

ns

(1) Maximum Package Power Dissipation may be exceeded if all outputs are shorted simultaneously.

MOTOROLA COMMUNICATIONS DEVICE DATA

MC1488

2·15

CHARACTERISTIC DEFINITIONS

FIGURE 1 - INPUT CURRENT
+9 V

FIGURE 2 - OUTPUT VOLTAGE
+9 V

-9 V

-9 V

14

FIGURE 3 - OUTPUT SHORT-CIRCUIT CURRENT

FIGURE 4 - OUTPUT RESISTANCE (POWER-OFFI

+1.9 V

105+

I

Vo
±2 Vdc
±6.6 mA Max

105-

+0.8 V

FIGURE 6 - SWITCHING RESPONSE

FIGURE 5 - POWER-SUPPLY CURRENTS

Vee

ein-D---I"'-:--3-k--l..---evo

+1.9 V

r

V1J

'5PF

+3V,...--_ _ _--,

~
1.5V

V,l

ein

. lPHL

--------0 V

Vo··-- - - - - - .

+0.8 V

ITHL--'--_ _ _--J"--ITLH
VEE

MC1488

2-16

ITHl and ITLH Measured 10% 10 90%

MOTOROLA COMMUNICATIONS DEVICE DATA

TYPICAL CHARACTERISTICS
(TA = +250 C unless otherwise noted.)
FIGURE B -

FIGURE 7 - TRANSFER CHARACTERISTICS
versus POWER-SUPPLY VOLTAGE
+12

~

c5

~
~

;o

"'

+3.0

·3.0

I-

6.0
'6>

~

~

~CC - JEe= ± 6 V

'-'

I::J

I

o

0.4

VI

I-

a'"

-3.0

O.B V

105-

~ -9.0

1.6

I.B

-12

2.0

o

-55

+20
+16

-;;

+12

~ 1--

'\

.s +B.O

00

I-

fi:i +4.0

I-

~

101=~0

'\.

-4.0

l-

~CL

i;

-B.O

!2

-12

I.S V

1.000

"-

-

3 kll LOAO LINE

~
~~

/

..J-

~

'\
i\
\.

105 1"-

:fvo

~4

O.BV, VCC=VEE=±SV

-20
-16

10.000

-

•
VI

-16

II IIIII

r--- r--

I\.

'"'"
i3

100

+125

+25
+75
T. TEMPERATURE IDC)

FIGURE 10 - OUTPUT VOLTAGE
AND CURRENT-LIMITING CHARACTERISTICS

1000

10

-=

:t:

FIGURE 9 - OUTPUT SLEW RATE
versus LOAD CAPACITANCE

1.0

VEE = S V

o

I

0.6
O.B
1.0
1.2
1.4
Vin.INPUT VOLTAGE IVOLTS)

II IIIII

...

i;: -6.0

-12
0.2

•
:~

::J

~

o

+3.0

:=

C;;

-=
I I

-

105+

+6.0

::J

3k

I

-S.O

+S.O

Z
W

~~

>
~

~

Jc=v~=±s1

+6.0

II::J

-;; +12

VCC~VEE}'12V

+S.O

SHORT-CIRCUIT OUTPUT CURRENT
versus TEMPERATURE

-12

CL. CAPACITANCE IpF)

-B.O
-4.0
+4.0
+B.O
• VO.OUTPUTVOLTAGEIVOLTS)

+12

+16

FIGURE 11 - MAXIMUM OPERATING TEMPERATURE
versus POWER-SUPPLY VOLTAGE

~
0

16

--...

14

~

w

to

«

:;
0

>

12
10

>
-'
It B.O

VCC

-

I

Cf14

1.

-

~

6.0

-v

'-'

>

-v

",

..!.!. ,3}

.~

l:l
U

..... t'-...

3j}

I--

~ 4.0

> 2.0

i"'--..

3k

6 3k

I--

::J

'"
'"

...............

I-- -55

MOTOROLA COMMUNICATIONS DEVICE DATA

-!1

I VEE I

1+25
+75
T. TEMPERATURE IDC)

+125

MC1488
2-17

APPLICATIONS INFORMATION

The Electronic Industries Association IEIAI RS232C specification
detail the requirements for the interface between data processing
equipment and date communications equipment. This standard
specifies not only the number and type of interface leads, but also the
voltage levels to be used. The MC1488 quad driver and its companion
circuit, the MC1489 quad receiver, provide a complete interface system
between DTL or TTL logic levels and the RS232C defined levels. The
RS232C requirements as applied to drivers are discussed herein.

FIGURE 13 - POWER-8UPPLV PROTECTION
TO MEET POWER-OFF FAULT CONDITIONS

---- -----..... ----

VCC

14

~M-C-14.L.8-8~

914

rMC1~88-~

I ........
I

I

,o-t-<)
... __ .....
I

o-~-;-- . . , :
o-{ -i ___ ,'o-~ -0

The required driver voltages are defined as between 5 and 15·
volts in magnitude and are positive for 8 logic "0" and negative for
a logic "I". These voltages are so defined when the drivers are
terminated with a 3000 to 7000·ohm resistor. The MC1488 meets
this voltage requirement by converting a DTLlTTL logic level into
RS232C levels with one stage of inversion.
The RS232C specification further requires that during transi·
tions. the driver output slew rate must not exceed 30 volts per
microsecond. The inherent slew rate of the MC1488 is much too

I

I

O--t-J---"', I
I!
o-J-------""'-----------

FIGURE 12 - SLEW RATE versus CAPACITANCE

I

,I

I

0- r~

~1
I

-. - - --

FOR ISC = 10 rnA
would be excessive. Therefore, if the system is designed to permit
low impedances to ground at the power-supplies of the drivers. a
diode stlould be placed in each power-supply lead to prevent overheating in this fault condition. These two diodes, as shown in
Figure 13, could be used to decouple all the driver packages in a
system. (These same diodes will allow the MC1488 to withstend
momentary shorts to the ±25-volt limits specified in the earlier
Standard RS232B.1 The addition of the diodes also permits the
MC1488 to withstand faults with power-supplies of less than the
9.0 volts stated above.
The maximum short-circuit current allowable under fa'ult conditions is more than guaranteed by the previously mentioned
10 mA output current limiting.

10 00

00

F= 3 IV'"'

Other Applications

IL 11111
1.0

10

100

1000

10.000

C. CAPACITANCE IpF)

fast for this requirement. The current limited output of the device

can be used to control this slew rate by connecting a capacitor to
each driver output. The required capacitor can be easily determined
by using the relationship C = lOS x ilT/il V from which Figure 12 is
derived. Accordingly, a 330·pF capacitor on each output will

guarantee a worst case slew rate of 30 volts per microsecond.
The interface driver is also required to withstand an accidental
short to any other conductor in an interconnecting cable. The worst
possible signal on any conductor would be another driver using a
plus or minus 15·volt, 500·mA source. The MC1488 is designed to
indefinitely withstand such a short to all four outputs in a package
as long as the power·supply voltages are greater than 9.0 volts (i.e.,
VCC;;;'9.0 V; VEE.,;;-9.0 VI. In some power-supply designs, a loss
of system power causes a low impedance on the power-supply outputs. When this occurs. a low impedance to ground would exist at
the power inputs to the MC1488 effectively shorting the 300-ohm
output resistors to ground. If all four outputs were then shorted
to plus or minus 15 volts, the power dissipation in these resistors

MC1488
2-18

The MC1488 is an extremely versatile line driver with a myriad
of possible applications. Several features of the drivers enhance
this versatility:
1. Output Current Limiting - this enables the circuit designer
to define the output voltage levels independent of power-supplies
and can be accomplished by diode clamping of the output pins.
Figure 14 shows the MC1488 used as a DTL to MOS translator
where the high-level voltage output is clamped one diode above
ground. The resistor divider shown is used to reduce the output
voltage below the 300 mV above ground MOS onput level limit.
2. Power-Supply Range - as can be seen from the schematic
drawing of the drivers, the positive and negative driving elements
of the device are essentially independent and do not require matching power-supplies. I n fact, the positive supply can vary from a
minimum seven volts (required for driving the negative pulldown
sectionl to the maximum specified 15 volts. The negative supply
can vary from approximately -2.5 volts to the minimum specified
-15 volts. The MCI488 will. drive the output [0 within 2 volts of
the positive or negative supplies as long as the current output limits
are not exceeded. The combination of the current-I imiting and
supply-voltage features allow a wide combination of possible outputs within the same quad package. Thus if only a portion of the
four drivers are used for driving RS232C lines, the remainder could
be used for DTL to MOS or even DTL to DTL translation. Figure 15
. shows one such combination ..

MOTOROLA COMMUNICATIONS DEVICE DATA

FIGURE 14 - MDTL/MTTL·TO·MOS TRANSLATOR
+12 V

MOTl
MTTl
INPUT

MOTl 2
INPUT

iO--.....-

.....'V'v-4>--__ MOS OUTPUT
(WITH VSS: GNO)

1k
10k

-12 V

FIGURE 15 - LOGIC TRANSLATOR APPLICATIONS

-12 V

MOTl n4 --'--'_....

~~~~

):>-+--<1--....- -......-

...

~007T~ ~U+~~~

INPUT 5
MOTl ,,--,-r---..
MHTlOUTPUT
MHTl
P--I--<>----.....- - - - e -0.7 V to 10 V
INPUT 10
12
MOTl "-..I-r---..
MaS OUTPUT
MMOS
):>-+--<1>-1>--'lN'I,---.....-... -10 V to 0 V
1NPUT ~13---r;:=:::;::=---,J
10 k

-12 V

MOTOROLA COMMUNICATIONS DEVICE DATA

+12 V

MC1488

2-19

MOTOROLA

-

SEMICONDUCTOR
TECHNICAL DATA

MCl489
MCl489A
QUADMDTL
LINE RECEIVERS
RS·232C

QUAD LINE RECEIVERS

SI LICON MONOLITHIC
INTEGRATED CIRCUIT

The MC1489 monolithic quad line receivers are designed to inter·
face data terminal equipment with data communications equipment
in conformance with the specifications of EIA Standard No. RS·232C.

•

Input Resistance - 3.0 k to 7.0 kilohms

•

Input Signal Range - ±30 Volts

•

I nput Threshold Hysteresis Built In

•

Response Control
a) Logic Threshold Shifting
b) Input Noise Filtering

LSUFFIX
CERAMIC PACKAGE
CASE 632

P SUFFIX
PLASTIC PACKAGE
CASE 646

#

DSUFFIX
PLASTIC PACKAGE
CASE 751A
14
(50·14)

.•.•

TYPICAL APPLICATION
LINE RECEIVER

LINE DRIVER
MCI488

MC1489

...r--,

Input A

1

c~-::::~:

2

--i
-t.. __ '

12 Response
Control 0

Response

I

MOTllOGICINPUT~

CABLE

I

Control B

I

INTERCONNECTING
..

I.

MDTL LOGIC OUTPUT

I
Ground 7

EQUIVALENT CIRCUIT SCHEMATIC (1/4 OF CIRCUIT SHOWN)
14
VCC

9k

1.7 k

5k

RF
3 OUTPUT

RESPONSE CONTROL 1

"-

3.8 k
INPUT 1

"'10k

I

RF

MC1489

6.71e{}·

MC1489A

1.6 Ie{}

1 GROUNO

MOTL and MTTL are trademarks of Motorola Inc.

MC1489.MC1489A
2-20

MOTOROLA COMMUNICATIONS DEVICE DATA

MAXIMUM RATINGS (TA = + 25"C unless otherwise noted)
Symbol

Value

Unit

Power Supply Voltage

VCC

10

Vdc

Input Voltage Range

VIR

±30

Vdc

Output Load Current

IL

20

mA

Po
1/6JA

1000
6.7

mW
mWf'C

TA

Oto +75

"C

Tstg

-65to +175

"C

Rating

Power Dissipation (Package Limitation, Ceramic
and Plastic Dual In-Line Package)
Derate above TA = + 25"C
Operating Ambient Temperature Range
Storage Temperature Range

ELECTRICAL CHARACTERISTICS (Response control pin is open.) (VCC

=

+5.0 Vdc ± 10%, TA

= 0 to

+75"C unless

otherwise noted)
Characteristics
Positive Input Current
Negative Input Current
Input Turn-On Threshold Voltage
(TA = + 25"C, VOL" 0.45 V)

Symbol

Min

Typ

Max

Unit

(VIH = +25 Vdc)
(VIH = +3.0 Vdc)

IIH

3.6
0.43

-

8.3

mA

(VIL = -25 Vdc)
(VIL = -3.0 Vdc)

IlL

-3.6
-0.43

VIH
MC1489
MC1489A

Input Turn-Off Threshold Voltage
(TA = + 25"C, VOH .. 2.5 V, IL = -0.5 mAl

1.0
1.75

-

-

1.95

'-

-8.3

-

Vdc
1.5
2.25
Vdc

VIL
MC1489
MC1489A

Output Voltage High

(VIH = 0.75 V, IL = -0.5 mAl
(Input Open Circuit, IL = -0.5 mAl

VOH

Output Voltage Low

(VIL = 3.0 V, IL = 10 mAl

mA

-

0.75
0.75

0.8

1.25
1.25

2.5
2.5

4.0
4.0

5.0
5.0

Vdc

VOL

-

0.2

0.45

Vdc

Output Short-Circuit Current

lOS

-

-3.0

-4.0

mA

Power Supply Current (All Gates "on," lout = 0 mA, VIH = + 5.0 Vdc)

ICC

-

16

26

mA

Power Consumption

Pc

-

80

130

mW

-

25

85

ns

120

175

ns

25

50

ns

10

20

ns

(VIH = + 5.0 Vdc)

SWITCHING CHARACTERISTICS (VCC = 5.0 Vdc +1%,
TA = + 25°C, See Figure 1.)
Propagation Delay Time

(RL = 3.9 kG)

tpLH

Rise Time

(RL = 3.9 kG)

lTLH

Propagation Delay Time

(RL = 390 kG)

tpHL

Fall Time

(RL = 390 kG)

tTHL

-

FIGURE 2 -

RESPONSE CONTROL NODE

TEST CIRCUITS
FIGURE 1 - SWITCHING RESPONSE
+5 Vdc
':'

RL

All diodes

lN3064
E,n

Eo

f

.....
EO
tTHL

CL

1.5 V

l

C~

CL

1/4

MC1489A

.-tPLH

'TLH and tTHL

RESPONSE NOOE

p-------------eVO

measured
10% - 90%

tTLH
1.5 V

C, capacitor IS tor noise filtermg.
R, resistor is for threshold shifting.

= 15 pF = total parasitic capacitance. which includes
probe and wiring capacitances

MOTOROLA COMMUNICATIONS DEVICE DATA

MC1489.MC1489A
2-21

TYPICAL CHARACTERISTICS
(Vee

= 5.0 Vdc,

TA

= +250 e

unless otherwise noted)

FIGURE 3 - INPUT CURRENT

FIGURE 4 - MC1489 INPUT THRESHOLD
VOLTAGE ADJUSTMENT

+10

6.0

+8.0
_

,V

-2.0

,/'
f'

-8.0
-10
-25

~

I

-20

-15

-10

-5.0

3.0

0

+5.0

I

I

I

+10

+15

+20

...>

2.0

0

1.0

...:::>~

"Y

./

~ -4.0

-6.0

..'"
w

./

:::>

z

~ 4.0

V

~ +2.0
cz:

~

:g

./

1
...z +40.
'"...

5.0

/

+6.0

II

_RT

_5k

r-- Vth
t- +5 V

rI-I--

r-

RT

13 k

>

v

5.0

..

+25

'"~

-RT

3.0

0

...>
...~

2.0

0

1.0

-

RT

r--5 k

RT

-

~

11k
Vth

-5 V

t-

-3.0

·2.0

-1.0

+1.0

I

I

2.4
2.2
~

2 2.0

..'"

-

-

w

~

0

1.8

-

, - , rVILH -VIHL

=:

~

1.2

~
or

1.0

l-

0.8

:I:

-

-1.0

+1.0

~
-"

+2.0

+3.0

r--'
f--

-

='V'h_

.f

-

+2.0

-t-3.0

-::- I--

-

,

-

MCI489 VIL

I

:i

;;; 0.2

:-

I

0
-60

+4.0

-

MCI489A VIH

MCl489VIH

~ 0.6
~
0.4

r-

I
-2.0

-

RT-

~

1.6

> 1.4

0

t---

I-

'-- f--

-3.0

I
I

-=-V,h

:::>

6
>

I
I

RT

Vth

+5 V

.

FIGURE 6 -INPUT THRESHOLD VOLTAGE
versus TEMPERATURE

'T.

4.0

?=

VI, INPUT VOLTAGE {VOLTS!

6.0

w

Vth

·5 V

f-f--

VILH VIHL

FIGURE 5 - MC1489A INPUT THRESHOLD
VOLTAGE ADJUSTMENT

~

RT

11 k

' - - , ,'--

VIn.INPUT VOLTAGE (VOLTSI

~

f-f--

~

Vth

+5

....

6

RT

+60

VI, INPUT VOLTAGE {VOLTS!

MCI489A VIL _
I
I

I
.. 120

T. TEMPERATURE lOCI

FIGURE 7 - INPUT THRESHOLD versus
POWER-SUPPLY VOLTAGE
2.0

VIH MCl489A

~

~

..'"
w

~

0

>

=:
0

~

cz:

1.0

~

VIH MCl489
VIL MCl489
VIL MCl489A

...
:I:

I-

~
~

4.0

12

8.0

VCC, POWER SUPPLY VOLTAGE {VOLTS!

MC1489.MC1489A

2-22

MOTOROLA COMMUNICATIONS DEVICE DATA

APPLICATIONS INFORMATION

General Information
The Electronic Industries Association (EIA) has released
the RS-232C specification detailing the requirements for
the interface between data processing equipment and
data communications equipment. This standard specifies not only the number and type of interface leads,
but also the voltage levels to be used. The MC1488 quad
driver and its companion circuit, the MC1489 quad receiver, provide a complete interface system between
DTL or TTL logic levels and the RS-232C defined levels.
The RS-232C requirements as applied to receivers are
discussed herein.
The required input impedance is defined as between
3000 ohms and 7000 ohms for input voltages between
3.0 and 25 volts in magnitude; and any voltage on the
receiver input in an open circuit condition must be less
than 2.0 volts in magnitude. The MC1489 circu.its meet
these requirements with a maximum open circuit voltage of one VBE.
The receiver shall detect a voltage between - 3.0 and
-25 volts as a Logic "1" and inputs between +3.0 and
+25 volts as a Logic "0." On some interchange leads,
an open circuit of power "OFF" condition (300 ohms or
more to ground) shall be decoded as an "OFF" condition
or Logic "1." For this reason, the input hysteresis
thresholds of the MC1489 circuits are all above ground.
Thus an open or grounded input will cause the same
output as a negative or Logic "1" input.
Device Characteristics
The MC1489 interface receivers have internal feedback
from the second stage to,the input stage providing input

FIGURE 8 - TYPICAL TURN-ON THRESHOLD versus
CAPACITANCE FROM RESPONSE CONTROL PIN TO GND

hysteresis for noise rejection. The MC1489 input has
typical turn-on voltage of 1.25 volts and turn-off of 1.0
volt for a typical hysteresis of 250 mV. The MC1489A
has typical turn-on of 1.95 volts and turn-off of 0.8 volt
for typically 1.15 volts of hysteresis.
Each receiver section has an external response control node in addition to the input and output pins,
thereby allowing the designer to vary the input threshold voltage levels. A resistor can be connected between
this node and an external power-supply. Figures 2, 4
and 5 illustrate the input threshold voltage shift possible
through this technique.
This response node can also be used for the filtering
of high-frequency, high-energy noise pulses. Figures 8
and 9 show typical noise-pulse rejection for external
capacitors of various sizes.
These two operations on the response node can be
combined or used individually for many combinations
~f interfacing applications. The MC1489 circuits are particularly useful for interfacing between MOS circuits and
MDTUMTTL logic systems. In this application, the input
threshold voltages are adjusted (with the appropriate
supply and resistor values) to fall in the center of the
MOS voltage logic levels. (See Figure 10)
The response node may also be used as the receiver
input as long as the designer realizes that he may not
drive this node with a low impedance source to a voltage greater than one diode above ground or less than
one diode below ground. This feature is demonstrated
in Figure 11 where two receivers are slaved to the same
line that must still meet the RS-232C impedance
requirement.

FIGURE 9 - TYPICAL TURN·ON THRESHOLD versus
CAPACITANCE FROM RESPONSE CONTROL PIN TO GND

~

'"2:w
'":::>

I-

...~c 3t---l"'---t-......l..-lp.,r--l------...j

w

11':0-----...l.-------1-------.J
100

1000

PW.INPUT PULSE WIDTH Insl

MOTOROLA COMMUNICATIONS DEVICE DATA

10,000

100

1000

10,000

PW,INPUT PULSE WIDTH Insl

MC1489.MC1489A
2-23

APPLICATIONS INFORMATION

(continued)

FIGURE 10 - TVPICAL TRANSLATOR APPLICATION MOS TO DTL OR'TTL
+5 ¥de

Oll or TTL

,..- -,

__ -I

:

'l-.L'

+5 Vde •

.".

FIGURE 11"": TYPICAL PARALLELING OF TWO MC1489,A RECEIVERS TO MEET RS·232C

vec

. RESPONSE·CONTROL PIN

,-----------------l
112 MC 1489

OUTPUT
INPUT

8k

1

I
I
VCCo-~----------------~

OUTPUT
INPUT '--__"'I8
"kl'lr--J.>-+__________......__t'VVv-+_{
RESPONSE·CONTRO L PIN

MC1489.MC1489A
2-24

MOTOROLA COMMUNICATIONS DEVICE DATA

APPLICATIONS INFORMATION

(continued)

FIGURE 11 - TYPICAL PARALLEUNG OF TWO MC1489,A RECEIVERS TO MEET RS-232C
VCC

RESPONSE·CONTROL PIN

r-----------------l
112 MCI489

OUTPUT
INPUT

8k

)

':'
VCCO-~----------------~

I
I
I
I
I

8 kl\r---i>-i----------......--;...'VV+_{
INPUT '--__"'VI
RESPONSE·CONTROL PIN

OUTPUT

I
I
I
I
I
I

_______ JI

MOTOROLA COMMUNICATIONS DEVICE DATA

MC1489.MC1489A

2-25

MOTOROLA

-

SEMICONDUCTOR
TECHNICAL DATA

MC26C31

Product Preview

Quad EIA·422·A Line Driver

PSU~

CMOS
The MC26C31 is a quad differential line driver designed for digital data
transmission over balanced lines. The MC26C31 meets all the requirements of
standard EIA-422-A while retaining the low-power characteristics of CMOS.
The MC26C31 accepts TTL or CMOS input levels and translates these to
EIA-422-A output level. This part uses special output circuitry that enables the
individual drivers to power down without loading down the bus. The MC26C31 also
includes special circuitry which will set the outputs to a high impedance mode
during power up ordown. preventing spurious glitches. This device has enable and
disable circuitry common for all four drivers.
The MC26C31 is pin compatible with the AM26LS31.
All pins are protected against damage due to electrostatic discharges.
•
•
•
•
•
•
•
•
•

Maximum Supply Current: 3 mA
2000-V ESD Protection on the Inputs and Outputs
TTUCMOS Input Compatible
Typical Propagation Delay: 6 ns
Typical Output Skew: 1 ns
Meets Vo = 6.0 V (and Vo = 0.25 V). VCC = 0 V. 10 < 100 !lA Requirement
Meets the Requirements of Standard EIA-422-A
Operation from single 5-V Supply
High-Impedance Mode for Outputs Connected to System Buses

_

PLASTIC PACKAGE
CASE 648

o SUFFIX
SOGPACKAGE
CASE 751B
ORDERING INFORMATION
MC26C31P
MC26C31D

Plastic DIP
SOG Package

BLOCK DIAGRAM

ENB

ENB

INPUT 0

14

INPUTB

INPUTC

13

10

11

6

INPUT A

5

2

3

OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT
02
01
C2
C1
B2
81
A2
A1

This document contains Inlonnation on a new product under development. Motorola reserves the rlghl to change or discontinue this product wllhout notice.

REV. 3
MC26C31
2-26

MOTOROLA COMMUNICATIONS DEVICE DATA

TRUTH TABLE
Control Inputs EJE

Input

Non-Inverting
Output

Inverting
Output
Z

UH

X

Z

All other combinations of
enable inputs

H

H

L

L

L

H

X=DontCare
Z = High Impedance

H = High Logic State
L = Low Logic State

MAXIMUM RATINGS
Symbol

Value

Unit

VCC

7

V

DC Input Voltage

Vln

-1.5toVCC+l.5

V

DC Output Voltage'

Vout

-0.5 to VCC +0.5

V

DC Output Current, per Pin

lout

150

rnA
rnA

Rating
Power Supply Voltage

DC VCC or GND Current, per Pin

100

150

Storage Temperature

Tstg

-65 to +150

°c

Power Dissipation

Po

500

mW

2000

V

ESD (Human Body model)
• Power-on conditions.
OPERATING CONDITIONS
Rating

Symbol

Min

Max

Unit

VCC

4.5

5.5

V

DC Input Voltage

Vln

0

VCC

V

Operating Temperature Range

TA

-40

+85

°c

Input Rise and Fall Time

tr,tf

-

500

ns

Power Supply Voltage

DC CHARACTERISTICS (VCC = 4.5 to 5.5 V, TA = - 40 to + 85°C, unless otherwise stated)
Symbol

Min

Typ

Max

Unit

Input Voltage (Low Logic State)

Parameter

VIL

-

-

0.8

V

Input Voltage (High Logic State)

VIH

2.0

-

-

V

Output Voltage (Low Logic State) Isink = 20 rnA

VOL

-

0.3

0.5

V

Output Voltage (High Logic State) Isource = 20 rnA

VOH

2.5

2.8

-

V

Output Differential Voltage RL = 100 n (Note 1)

VOD

2.0

-

V

D(VOD)

-

±0.4

V

-

3.0

V

-

±0.4

V

-

±1.0

I1A

3.0

rnA

Input CurrentVIH = VCC, GND, VIH or VIL

lin

Quiescent Supply Current lout = 0 f.1A

ICC

-

Output Short Circuit Current (Note 2)

lOS

-30

-100

-150

rnA

-

-

±1.0

I1A
I1A

Output Differential Voltage Difference RL = 100 n (Note 1)
Output Offset Voltage RL = 100 n (Note 1)

VOS

Output Offset Voltage Difference RL = 100 n (Note 1)

D(VOS)

Output Leakage Current (HI-Z State) Vout = VCC or GND
Input Leakage Current (Power Off)

10(Z)
Vout=6V
Vout = - 0.25 V

loxh
loxl

100
-100

NOTES:
1. See EIA specifications EIA-422-A for exact test conditions.
2. Only one output may be shorted at a time.

MOTOROLA COMMUNICATIONS DEVICE DATA

MC26C31
2-27

AC CHARACTERISTICS (VCC = 4.5 to 5.5 V, TA = - 40 to + 85'C, unless otherwise stated)
Parameter

Typ

Max

Unit

Propagation Delay Input to Output (S1 Open)

Symbol
tpLH
tpHL

Min

-

6

12

ns

Output Skew (S1 Open)'

Skew

-

1.0

4

ns

Differential Output
Rise TIme
Fall Time (S1 Open)

t(TLH)
t(THL)

-

4

8

ns

Output Enable TIme
(S1 Closed)

tpZH
tpZL

-

16
15

-

ns

Output Disable TIme
(S1 Closed)

tpHZ
tpLZ

-

6
9

-

ns

• Skew: difference in propagation delays between complementary outputs.

AC TEST CIRCUIT AND SWITCHING TIME WAVEFORMS
3V1.5V

INPUT

1.5V

OV

J

49.90
4990

1.5 V

-VOH
1.5V

OUTPUT A

:--..: ~SKEW
----..:
:.-tPHL

~

SI
49.90

'

OUTPUTB

Figure 1. AC Test Circuit

\

1.5V

1..-

IpLH -..:

_'C:.:

To 1.5V

'1.5V
'-.- - - - - - - - - "

VOH

- VOL

Figure 2. Propagation Delays and Skew Waveforms

3V-,
1.5 V

ENABLE INPUT
OV

-:

OUTPUT A

-,

,

OUTPUTB

:~tpLZ

tpZL_:

,',

3V-

-1.5V
O.BV
VOL

tPZH-:

:-..lPHZ

,

VOH-0.5V

,

VOH

2.0 V
-1.5V

Figure 3. Enable and Disable Times

INPUT

OV

OUTPUT
(DIFFERENTIAL)

90%

,90%
10%

,

10% '

-:

:-trLH

tTHL-:

:--

Figure 4. Differential Rise and Fall Times

TYPICAL APPLICATIONS

"'''E~ /

~""

---------'rt<'

DATA~,-.

~OUTPUT

Figure 5. Two-Wire Balanced Systems (EIA-422-A)

MC26C31
2"28

MOTOROLA COMMUNICATIONS DEVICE DATA

MOTOROLA

-

SEMICONDUCTOR
TECHNICAL DATA

MC26C32
Product Preview
Quad EIA·422·A Line Receiver
CMOS
The MC26C32 is a quad differential line receiver designed for digital data
transmission over balanced lines. The MC26C32 meets all the requirements of
standard EIA-422-A while retaining the low-power characteristics of CMOS.
The MC26C32 has an input sensitivity of 200 mV over the common mode input
voltage range of ± 7 V. In addition, each receiver chain has internal hysteresis
circuitry to improve noise margin and discourage output· instability for slowly
changing input waveforms.
The MC26C32 is pin compatible with the AM26LS32.
All pins are protected against damage due to electrostatic discharges.
•
•
•
•
•
•
•
•

Typical Power Supply Current: 6 mA
2000-V ESD Protection on the Inputs and Outputs
Typical Propagation Delay: 18 ns
Typical Input Hysteresis: 75 mV
Meets the Requirements of Standard EIA-422-A
Operation from single 5-V Supply
High-Impedance Mode for Outputs Connected to System Buses
TTUCMOS Compatible Outputs

_

POOFAX
PLASTIC PACKAGE
CASE 648

DSUFFIX
SOG PACKAGE
CASE 751B

ORDERING INFORMATION
MC26C32P
MC26C32D

Plastic DIP
SOG Package

BLOCK DIAGRAM
INPUT INPUT
ENB

ENB

02

01

INPUT INPUT
C2

C1

11

OUTPUT

o

INPUT INPUT
B2

B1

13

OUTPUT
C

OUTPUT
B

INPUT INPUT
A2
A1

3
OUTPUT
A

This document contains infonnation on a new product under development Motorola reserves the ~ght to change or discontinue this product without notice.

REV. 3

MOTOROLA COMMUNICATIONS DEVICE DATA

MC26C32
2-29

TRUTH TABLE
Control Inputs !:IE

Input

Output·

UH

X

Z

All olher combinations of
emible Inputs

VIO 
1

VCC_
40-_

DSUFFIX
PLASTIC PACKAGE
CASE 751B
50-16

13

PIN ASSIGNMENTS

50-_ _...,

Variable
Reactance
Output
Decoupling

12

Modulator
Input

11

60-......- -....

7

VCC2 4
MicAmp
Input 5

10

MicAmp 6
Output
Tone 7
Switch
Tone
Output

f---¢9

8

11 Battery
Checker

MAXIMUM RATINGS (TA = 25·C unless otherwise noted)
Pin

Symbol

Value

Power Supply Voltage

4, 12

VCC

10

Vdc

Operating Supply Voltage Range

4,12

VCC

3.0 to 8.0

Vdc

Battery Checker Output Sink Current

10

ILED

25

mA

Junction Temperature

-

TJ

+150

·C

TA

-30 to +75

·C

Tstg

-65 to +150

·C

Rating

Operating Ambient Temperature Range
Storage Temperature Range

MC2831 A
2-32

Unit

MOTOROLA COMMUNICATIONS DEVICE DATA

ELECTRICAL CHARACTERISTICS (Vce1

= 4.0 Vdc, VCC2 = 4.0 Vdc, TA = 25'C, unless otherwise noted)

Characteristic
Drain Current
Drain Current

Symbol

Pin

Min

Typ

Max

ICC1

12

150

290

420

I'A

ICC2

4

2.2

3.6

6.5

rnA

VTB

11

1.0

1.2

1.4

Vdc

VOSAT

10

-

0.15

0.5

Vdc

5,6

27

30

33

dB

Unit

BATTERY CHECKER
Threshold Voltage (LED Off -> On)
Output Saturation Voltage
(Pin 11 = 0 V, Pin 10 Sink Current = 5.0 mAl
MIC AMPLIFIER
Voltage Gain, Closed Loop
(Vin = 1.0 mV rms , fin = 1.0 kHz)

-

Output dc Voltage

-

6

1.1

1.4

1.7

Vdc

-

6

0.8

1.2

1.6

Vp-p

THO

6

-

0.7

-

%

-

8

50

-

mV rms

1.4

-

Vdc

8

-

1.8

5.0

%

-

7

1.1

1.4

1.7

Vdc

Output Swing (Vin

= 30 mVrms , fin = 1.0 kHz)

Total Harmonic Distortion
(VO = 31 mV rms , fin = 1.0 kHz)
PILOT TONE OSCILLATOR (250

,(l

LOADING)

= 5.0 kHz)

Output AF Voltage (fo
Output dc Voltage

Total Harmonic Distortion
(fo = 5.0 kHz, VAF = 150 mV rms )
Tone Switch Threshold
FM MODULATOR (120

,(l

8

LOADING)

= 16.6 MHz)

14

-

40

-

Output dc Voltage

-

14

-

1.3

-

Modulation Sensitivity (Note 1)
(Vin = 1.0 V ± 0.2 V)

-

3,14

6.0

10

18

HzlmVdc

Maximum Deviation (Note 1)
(Vin = 0 V to +2.0 V)

-

3,14

±2.5

±5.0

±12.5

kHz

RF Frequency Range

-

14

-

60

MHz

Output RF Voltage (fo

00

VRFO

-

mV rms
Vdc

•

Note 1. Modulation sensItIVIty and maximum deviation are measured at 49.815 MHz. which IS the third harmonic of the crystal frequency.

MOTOROLA COMMUNICATIONS DEVICE DATA

MC2831A
2-33

FIGURE 2 - TEST CIRCUIT

Mod Out
0.0047

r
Modln

2

15

3

14

RFOut
(16.605 MHzl

0.01
4

13
MC2831A

MicAmpln

5

12

VCCI

MicAmpOut

6

11

Battery
Checker In

Tone Switch

7

10

LED

Tone Output

8

9

Ll Toko America

0.047

7PA Type
126AN - 6708X '

VCC2

Ll
20mH
Oac Coil

FIGURE 3 - SINGLE CHIP FM VHF TRANSMITTER AT 49.7 MHz
4.71'H --+ 16.5667 MHz
~---J~~~D~----,

1.0

0.471'H

>rH--+"'~

Dynamic
Microphone

-=

NOTES:
SI is a normally closed push button type switch.

Battery checker circuit (Pins 10, 111 is not used in this application.

The crystal used is fundamental mode, calibrated for parallel resonance
with a 32 pF load. The 49.7 MHz output is generated in the output buffer,
which generates useful harmonics to 60 MHz.

All capacitors in microfarads, inductors in Henries and resistors in
Ohms, unless otherwise specified.

The network on the output at Pin 14 provides output tuning and impedance matching to 50 n at 49.7 MHz. Harmonics are suppressed by more
than 25 dB.

MC2831A
2.,34

MOTOROLA COMMUNICATIONS DEVICE DATA

MOTOROLA

-

SEMICONDUCTOR
TECHNICAL DATA

MC2833
LOW POWER FM TRANSMITTER SYSTEM
MC2833 is a one-chip FM transmitter subsystem designed for
cordless telephone and FM communication equipment. It includes
a microphone amplifier, voltage controlled oscillator and two auxiliary transistors.
.

LOW POWER
FM TRANSMITTER
SYSTEM

• Wide Range of Operating Supply Voltage (2.8-9.0 V)
• Low Drain Current (Icc = 2.9 mA Typ)
• Low Number of External Parts Required
• -30 dBm Power Output to 60 MHz Using Direct RF Output
• + 10 dBm Power Output Attainable Using On-Chip Transistor
Amplifiers

,.
1

PSUFFIX
PLASTIC PACKAGE
CASE 648

DSUFFIX
PLASTIC PACKAGE
CASE 751B
SO-16

FUNCTIONAL BLOCK DIAGRAM

16

2

15

3

14

PIN ASSIGNMENTS
Variable
Reactance 1
Output
Oecoupling

Mic
Amp
4

13

12

5

J,
6

11

10

B

9

RF
Output

MicAmp
Output 4

Tr2
Base

MicAmp
Input

Tr2
Emitter

Gnd
Tr 1
Emitter
Tr 1
Base

7

MOTOROLA COMMUNICATIONS DEVICE DATA

Modulator
Input

Tr2
Collector
VCC
Trl
Collector

MC2833
2-35

MAXIMUM RATINGS
Symbol

Valua

Power Supply Voltage

Ratings

VCC

10 (max)

V

Operating Supply Voltage Range

VCC

2.8-9.0

V

Unit

Junction Temperature

TJ

+150

·C

Operating Ambient Temperature

TA

-30to +75

·C

Tst9

-65 to +150

·C

Storage Temperature Range

ELECTRICAL CHARACTERISTICS (VCC = 4.0 V, TA = 25'C, unless otherwise. noted)
Characteristics
Drain Current (No inpLit signal)
FM MODULATOR
Output RF Voltage (fo

= 16.6 MHz)

Vout RF

14

60

90

130

Output DC Voltage (No input signal)

Vdc

14

2.2

2.5

2.8

V

Modulation Sensitivity (fo = 16.6 MHz)
(Vin = 0.8 V to 1.2 V)

SEN

3.0
14

7.0

10

15

HzlmVdc

Maximum Deviation (fo = 16.6 MHz)
(Vin = 0 V to 2.0 V)

Fdev

3.0
14

3.0

Av

4.0
5.0

-

5.0

-

10
-

mVrms

kHz

MIC AMPLIFIER
Closed Loop Voltage Gain (Vin = 3.0 mVrms)
(fin = 1.0 kHz)

-

27

30

33

-

-

dB

Output DC Voltage (No input signal)

Vout dc

4.0

1.1

1.4

1.7

V

Output Swing Voltage (Vin = 30 mVrms)
(fin = 1.0 kHz)

Vout pop

4.0

0.8

1.2

1.6

Vp-p

THO

4.0

-

0.15

2.0

%

Total Harmonic Distortion (Vin = 3.0 mVrms)
(fin = 1.0 kHz)

AUXILIARY TRANSISTOR STATIC CHARACTERISTICS
Symbol

Min

Typ

Max

Unit

V(BR)CBO

15

45

V

V(BRICEO

10

15

-

V(BR)CSO

-

70

-

V

6.2

-

V

ICBO

-

-

200

nA

hFE

40

150

-

-

fT

-

500

-

MHz

Collector Base Capacitance (VCE = 3.0 V)
(IC = 0)

CCB

-

2.0

-

pF

Collector Substrate Capacitance (VCS = 3.0 V)
(IC = 0)

CCS

-

3.3

-

pF

Characteristics

= 5.0 !LA)
Collector Emitter Breakdown Voltage (lC = 200 !LA)
Collector Substrate Breakdown Voltage (lC = 50 ",A)
Emitter Base Breakdown Voltage (IE = 50 ",A)
Collector Base Cut Off Current (VCB = 10 V)
(IE = 0)
DC Current Gain (lC = 3.0 mAl
(VCE = 3.0 V)
Collector Base Breakdown Voltage (lC

V(BR)EBO

V

AUXILIARY TRANSISTOR DYNAMIC CHARACTERISTICS
Current Gain Bandwidth Product (VCE = 3.0 V)
(lC = 3.0 mAl

MC2833
2-36

MOTOROLA COMMUNICAT)ONS DEV)CE DATA

-

FIGURE 1 - TEST CIRCUIT

Mod Out
39 pF

0.0047"F

P

Crystal: fa = 16.605 MHz
CL=30pF
Co = 6.1 pF
RS = 10 n Max

b.

15

68 pF-=-

Mod In

14 .....--0RF Out

MicAmp
Out

4

MC2833

13t----oBase 2

220 k
MicAmp
In

121----0 Emitter 2
6.3 k
6

111----0 Collector 2

7

101-_---,

-=Emitter 1

+

!~~
8

Base 1

FIGURE 2 -

~O.OI"F

91----0 Collector 1

SINGLE CHIP FM VHF TRANSMITTER AT 49.7 MHz

)lIDI'IM,..,--t-II---~

390 k

~470PF
VCC = 3.0 V to 8.0 V

NOTES: The crystal used is fundamental mode. calibrated for parallel
resonance with a 32 pF load. The 49.7 MHz output is
generated in the output buffer, which is being used as a
frequency tripler in this application.
The networks in the output stages provide frequency

selectivity and impedance matching at 49.7 MHz.

MOTOROLA COMMUNICATIONS DEVICE DATA

The RF output is + 10 dBm (10 mW into 50 n load) at 49.7
MHz, with all harmonics reduced by more than 50 dB.
All capacitors in microfarads, inductors in Henries and
resistors in Ohms unless otherwise specified.

0.22 p.H inductors are Toko B199SN·Tl048Z
3.3 "H inductor is Toka BI99KN-Tl055Z

MC2833
2-37

MOTOROLA

-

SEMICONDUCTOR
TECHNICAL DATA

MC3356
WIDEBAND FSK RECEIVER

WIDEBAND

· .. includes Oscillator. Mixer. Limiting IF Amplifier. Quadrature
Detector. Audio Buffer. Squelch. Meter Drive. Squelch Status output. and Data Shaper comparator. The MC3356 is designed for
use in digital data communications equipment.

FSK

RECEIVER
MONOLITHIC SILICON
INTEGRATED CIRCUIT

• Data Rates up to 500 kilobaud
• Excellent Sensitivity: -3 dB Limiting Sensitivity
30 I1Vrms @ 100 MHz
• Highly versatile. full-function device. yet few external parts are
required

P SUFFIX
PLASTIC PACKAGE
CASE 738

FIGURE 1 -

FUNCTIONAL BLOCK DIAGRAM

FIGURE 2 -

PIN CONNECTIONS

RF

vee

RF
Ground

RF Input

1

( - - - - - - - 19

Ground

I
I

: r-;;==::':;:::::---t.:.:..r-....-oO~~~:t

+ Comparator

I
I

Vee

I

- Comparator

J

--------..;,

Ceramic

Filter

Data Output

Squelch

Squelch Status

'--~--'---r+---1"""'D Status
Squelch Cpntrol

Buffered Output

12
10

11

Demodulator
Filter
Quad Input

Quadrature Detector

r -::.::;:- -, Tank
Vee

MC3356
2-38

I

I

1

1

1
,I
IL _____ ..J,I

MOTOROLA COMMUNICATIONS DEVICE DATA

MAXIMUM RATINGS
Symbol

Value

VCC(max)

15

Vdc

VCC

3.0 to 9.0

Vdc

Rating
Power Supply Voltage
Operating Power Supply Voltage Range (Pins 6, 10)
Operating R.F. Supply Voltage Range (Pin 4)

Unit

R.F. Vec

3.0 to 12.0

Vdc

Junction Temperature

TJ

150

'c

Operating Ambient Temperature Range

TA

-40 to +75

'c

Tst\1

-65to +150

'e

PD

1.25

Storage Temperature Range
Power Dissipation, Package Rating

W

ELECTRICAL CHARACTERISTICS (VCC = 5.0 Vdc, fo = 100 MHz, fosc = 110.7 MHz, 

u

~ 200

.......

:;;

N
0.1

100
1.0

10

INPUT ImVrmsl

o

0.010

0.1

1.0
10.
PIN 20 INPUT ImVrmsl

100

1000

General Description
This device is intended for single and double conversion VHF receiver systems, primarily for FSK data
transmission up to 500 K baud (250 kHz). It contains an
oscillator, mixer,limiting IF, quadrature detector, signal
strength meter drive, and data shaping amplifier.
The oscillator is a common base Colpitts type which
can be crystal controlled, as shown in Figure 1, or L-C
controlled as shown in the other figures. At higher VCC,
it has been operated as high as 400 MHz. A mixer/
oscillator voltage gain of 2 up to approximately 200
MHz, is readily achievable.
The mixer functions well from an input signal of 10
!LVrms, below which the squelch is unpredictable, up
to about 10 mVrms, before any evidence of overload.
Operation up to 1.0 Vrms input is permitted, but nonlinearity of the meter output is incurred, and some oscillator pulling is suspected. The AM rejection above 10
mVrms is degraded.
The limiting IF is a high frequency type, capable of
being operated up to 50 MHz. It is expected to be used
at 10.7 MHz in most cases, due to the availability of
standard ceramic resonators. The quadrature detector
is internally coupled to the IF, and a 5.0 pF quadrature
capacitor is internally provided. The - 3dB limiting sensitivity of the IF itself is approximately 50 !LV (at Pin 7),
and the IF can accept signals up to 1.0 Vrms without
distortion or change of detector quiescent dc level.
The IF is unusual in that each of the last 5 stages of
the 6 state limiter contains a signal strength sensitive,
current sinking device. These are parallel connected and
buffered to produce a signal strength meter drive which
is fairly linear for IF input signals of 10 !LV to 100 mVrms.
(See Figure 5.)
A simple squelch arrangement is provided whereby
the meter current flowing through the meter load resistance flips a comparator at about 0.8 Vdc above
ground. The signal strength at which this occurs can be

MC3356
2-40

adjusted by changing the meter load resistor. The comparator( +) input and outputare available to permit controlof hysteresis. Good positive action can be obtained
for IF input signals of above 30 I1Vrms. The 130 kfl
resistor shown in the test circuit provides a small
amount of hysteresis. Its connection between the 3.3 k
resistor to ground and the 3.0 k pot, permits adjustment
of squelch level without changing the amount of
hysteresis.
The squelch is internally connected to both the quadrature detector and the data shapero The quadrature
detector output, when squelched, goes to a dc level
approximately equal to the zero signal level, unsquelched. The squelch causes the data shaper to produce a high (VCC) output.
The data shaper is a complete "floating" comparator,
with back to back diodes across its inputs. The output
of the quadrature detector can be fed directly to either
input of this amplifier to produce an output that is either
at VCC or VEE, depending upon the received frequency.
The impedance of the biasing can be varied to produce
an amplifier which "follows" frequency detuning to
some degree, to prevent data pulse width changes.
When the data shaper is driven directly from the demodulator output, Pin 13, there may be distortion at Pin
13 due to the diodes, but this is not important in the
data application. A useful note in relating high/low input
frequency to logic state: low IF frequency corresponds
to low demodulator output. If the oscillator is above the
incoming RF frequency, then high RF frequency will
produce a logic low. (Input to (+ )input of Data Shaper
as shown in figures 1 and 3.)

MOTOROLA COMMUNICATIONS DEVICE DATA

FIGURE 6 -

APPLICATION WITH FIXED BIAS ON DATA SHAPER

Data Out

Car. Det. Out

.5.0 V
18 k

15 k
AF In

-1-2-1

~
=

470

001

18 k ~
3.3 k
I
I
I
I
I
I
L~-r-~J__~~__~1~9__~~18~-Ll~7__-Ll~6__~1~5__-Ll~4__~__~~~~II~-,
RF Input Ground
Data Camp! + } Camp! _) Squelch Squelch Demod
Output
Status Control
Out
Filter Input

MC3356

10

Bead

1'0.1

82

Application Notes
The MC3356 is a high frequency/high gain receiver
that requires following certain layout techniques in designing a stable circuit configuration. The objective is
to minimize or eliminate, if possible, any unwanted
feedback.
Shielding, which includes the placement of input and
output components, is important in minimizing electrostatic or electromagnetic coupling. The MC3356 has its
pin connections such that the circuit designer can place
the critical input and output circuits on opposite ends
of the chip. Shielding is normally required for inductors
in tuned circuits.
The MC3356 has separate VCC's and grounds for the
RF and IF sections which allows good external circuit
isolation by minimizing common ground paths.
Note that the circuits of figures 1 and 3 have RF, oscillator, and IF circuits predominantly referenced to the
plus supply rails. Figure 6, on the other hand, shows a
suitable means of ground referencing. The two methods
produce identical results when carefully executed. It is
important to treat Pin 19 as a ground node for either
approach. The RF input should be "grounded" to

MOTOROLA COMMUNICATIONS DEVICE DATA

Pin 1 and then the input and the mixer/oscillator
grounds (or RF VCC bypasses) should be connected by
a low inductance path to Pin 19.IF and detector sections
should also have their bypasses returned by a separate
path to Pin 19. VCC and RF VCC can be decoupled to
minimize feedback, although the configuration of Figure
3 shows a successful implementation on a common 5.0
supply. Once again, the message is: define a supply
node and a ground node and return each section to
those nodes by separate, low impedance paths.
The test circuit of Figure 3 has a 3 db limiting level
of 30 fLV which can be lowered 6 db by a 1:2 untuned
transformer at the input as shown in figures 6 and 7.
For applications that require additional sensitivity, an
RF amplifier can be added, but with no greater than 20
db gain. This will give a 2.0 to 2.5 fLV sensitivity and any
additional gain will reduce receiver dynamic range without improving its sensitivity. Although the test circuit
operates at + 5.0 V, the mixer/oscillator optimum performance is at +8.0 V to 12 V. A minimum of +8.0 V
is recommended in high frequency applications (above
150 MHz), or in PLL applications where the oscillator
drives a prescaler.

MC3356

2-41

FIGURE 7 - APPLICATION WITH SELF-ADJUSTING BIAS ON DATA SHAPER

Data

+5.0 V

Car. Oet. Out

Out
OVor4.0V

130 k

3.3 k
15 k

47k

47 k

~.-0_'0_1-C~~~~~~~~~~L7~~~~~~~~~~1~2~~:1-'~-_-_-,------------,
Dernod
Filter

Quad
Input

f

MC3356

= 10.7
150 pF

APPLICATION NOTES. continued
Depending on the external circuit, inverted or noninverted data is available at Pin 18. Inverted data makes
the higher frequency in the FSK signal a 'one' when the
local oscillator is above the incoming RF. Figure 6 schematic shows the comparator with hysteresis. In this circuit the dc reference voltage at Pin 17 is about the same
as the demodulated output voltage (Pin 13) when no
signal is present. This type circuit is preferred for systems where the data rates can drop to zero. Some systems have a low frequency limit on the data rate, such
as systems using the MC3850 ACIA that has a start or
stop bit. This defines the low frequency limit that can
appear in the data stream. Figure 6 circuit can then be

MC3356
2-42

changed to a circuit configuration as shown in Figure
7. In Figure 7 the reference voltage for the comparator
is derived from the demodulator output through a low
pass circuit where T is much lower than the lowest fre. quency data rate. This and similar circuits will compensate for small tuning changes (or drift) in the quadrature
detector.
Squelch status (Pin 15) goes high (squelch off) when
the input signal becomes greater than some preset level
set by the resistance between Pin 14 and ground. Hysteresis is added to the circuit externally by the resistance
from Pin 14 to Pin 15.

MOTOROLA COMMUNICATIONS DEVICE DATA

s::

@
JJ

o

FIGURE 8 -

~

INTERNAL SCHEMATIC

o

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1.0 k

o

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,

f20 pF ~ "2

330

500

"b-J "'

~ 2.0 k

2.0 k

85

n

2.0 k

2.0 k

10 k

94

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f-l;!67 ~70

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5.0 k

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30 k
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~'~=

33k

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33 k

10 k

10
k

120 k

57~

iii:

(')

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~~

6

FIGURE 3 - CIRCUIT SCHEMATIC

060

9

m'oo'

0"'-1

056(1

~.

"l

~L

33 k

50 k

7

055

;;;,C2

O'-....J

58~

059

MOTOROLA

-

SEMICONDUCTOR
TECHNICAL DATA

Me33S9
HIGH GAIN
LOW POWER

FM IF

LOW POWER NARROWBAND FM IF

SILICON MONOLITHIC
INTEGRATED CIRCUIT

· .. includes oscillator, mixer, limiting amplifier, AFC, quadrature
discriminator, op/amp, squelch, scan control, and mute switch.
The MC3359 is designed to detect narrowband FM signals using
a 455 kHz ceramic filter for use in FM dual conversion communications equipment. The MC3359 is similar to the MC3357 except
that the MC3359 has an additional limiting IF stage, an AFC output,
and an opposite polarity Broadcast Detector. The MC3359 also
requires fewer external parts.

PSUFFIX
PLASTIC PACKAGE
CASE 707

20.

DWSUFFIX
PLASTIC PACKAGE
CASE 7510

• Low Drain Current: 3.6 mA (Typ) @ VCC = 6.0 Vdc
• Excellent Sensitivity: Input Limiting Voltage --3.0 dB = 2.0/LV (Typ)
• Low Number of External Parts Required

FIGURE 2 - PIN CONNECTIONS AND
FUNCTIONAL BLOCK DIAGRAM

crvstal {

1

Csc.
2
MilCer

RGURE 1 -

TYPICAL APPLICATION IN A SCANNER RECEIVER

Output

limiter
Input
Decou piing 6

Decoupling

""'I'o!-

o

DERIVED USING
OPTIMUM UC
OSCILLATOR VALUES
AND HOLDING
IF FREQUENCY AT
455 kHz

~ -30
~

-60
0.1

/"

I-""

-8

-6

-4
-2
0
2.0
RELATIVE FREQUENCY [kHz[

4.0

1.0

MC3359

8.0

10

I I IIIIIIIIIIII
S+N+-I';'"3KH FM
I I Illilll zl I
25°C
-

I
--- wc _

~

l'

VCC = 6.0 Vdc

S+~ [ [iidJ1[A~I[

-40
N

10
FREQUENCY [MHz[

6.0

OVERALL GAIN, NOISE, AND A.M. REJECTION

-50

IIIIII

~

,/"DETECTOR OUTPUT PIN 10

=>

-50

2-50

-

V

-10

:!".

_

V

~

-10

-40

/'"

FIGURE 9 -

iii'
:!".
>-

if)

AF~ OUTP0TPIN 111
/"

10

-30 -

100

= 6.0 Vdc

VCC

-10

10

~

~

10

DETECTOR AND AFC RESPONSES

2.0

10

a;

I Illill --till

5.0

5

3RD 10RDER 1M PRODUCTS

-50 -40
-30
INPUT, 50 II [dBm[

FIGURE 8 -

"U

/

I

r

6.0

~

~

40

/

3 B LI[MIJA!-

1.0
FREQUENCY [MHz[

7.0

//
II

,//

V

V

8.0

/

"l

OUTPUTTAKEN AT
PIN 3 WITH FILTER
REMOVED
VCC = 6.0 Vdc

1\

RI[NI~T[ W

FIGURE 7 -

20
10

100 fLV

-70
0.1

40

...........

R~SpJNJE ~A~l~ ~N

A SPECIAL PROTOTYPE.

/

/

20

~
=>

IF OUTPUT

-

~

-'
,..:

LIMITING I.F. FREQUENCY RESPONSE

II

-10

Y~~V_ I -

60

9

FIGURE 5 -

100

-60
0.001

O,oi

1.0
0.1
INPUT [mVrmsl

I

10

100

MOTOROLA COMMUNICATIONS DEVICE DATA

FIGURE 10 - OUTPUT COMPONENTS OF
SIGNAL, NOISE, AND DISTORTION

FIGURE 11 - AUDIO OUTPUT AND TOTAL
CURRENT DRAIN versus SUPPLY VOLTAGE
8.0
7.0

111111 II III

0;
:!;!.

!3

~
fa = 10.7 MHz
-10 f--I''I'W-t+I-HtI--H-H+ltttl-H-H-I+H+H--I-H fm = I kHz
I1f = :!:3.okHz
20 I-+H+tl~++-+I-H+Ht-f-t-t+1-tHlH-+-+I TEST CIRCUIT OF
~
FIGURE 3.

~ - 3D H-H-t+I-HtI---H'Nc1+1tttl-H-I N+ 0

~
~ -40

c:::r-

----

15.0 r-!z

!5 -

o

~ 4.0

a
~ 3.0

f-t-t+1-ttffi+1+t+H1tI

TIffirrrr~lffitr~~~-H-H~

IIIII

~ 2.0

I~"

--

I~C. MUT~ ON

~

f--

8::

- 50 ~1+tlJI--.1...t-~t-J.=t:I:j::jjllll#=l=l=l=l=f:I##=I=l==F##1ll

-

~UOIO O~TPUT

6.0
'U

r---

~

1.0

o

-~o~ol~~llllo~.o~I~~llWo.'-W~~WI.~o~~lllll~o~-w~w,oo

4.0

8.0

7.0
6.0
Vcc. SUPPLY VOLTAGE IVdcl

5.0

INPUT ImVrms

o

9

FIGURE 12 - UC OSCILLATOR, TEMPERATURE
AND POWER SUPPLY SENSITIVITY

,"""

10.704

"'" '-

>-

10.698

afE 10.696

5O~~~~~~~~~~~-L

~
............

!

"::"CC

1'....."
TEMP

10.694

-..........::: ~

.........

10.692
40
50
AM81ENT TEMPERATURE I'CI

3D

FIGURE 14 -

1000

~100
«
~

:5

-

C5"""-

~

70
50

-

"

;;:--

70

10

180

13

llIIIII

p::::.. ~

ISO

I

~

90~

~~.

!W,

3D

120

AND PHASE ISOLID lINESI

iE

o~~~~~~~~~~N~-+lH+H*--~I-+~~~~~~ 50
O'FlGURE'.

"-

Dr- VCC::

'6.0Vd~'--t-++ttHllt---+-+++ttltf--+-+-f"kHftti

Dr-I

1111111

1.0 K

10 K

l.oM

100 K

3D

10M

FIGURE 15 - THE OP AMP AS A BANDPASS FILTER
I

1.0

I

0.8

~

....

0.6 -

I!:
~

0.4

:;:
2 2,
~

1.0 ~

7 g
0

20

12-

1.0

FREQUENCY IHzl

C5

"-

7.0

60

C4

3D

10
5.0

~

'~

L

300

r~200

~

o-l

-.,.;
GAIN
v'"
PHASE f"
I'-USE CIRCUIT ABOVE
401--l--HH+tttF",-+-+-P\.!:/'IIl---'>,d-H-++FOR OPEN lOOP GAIN

UC OSCILLATOR RECOMMENDED
COMPONENT VALUES

700
500

tOM

i_''.1"1

tOK

--- "'--"

! 10.700

10.690 20

OP AMP GAIN AND PHASE RESPONSE

62
tOM

10.702

ffi

FIGURE 13 -

Vcc. SUPPLY VOLTAGE IVdcl
60
61

59

58

10.706

~

" I'--

20
3D
OSCILLATOR FREQUENCY IMHzl

MOTOROLA COMMUNICATIONS DEVICE DATA

'"£
~

0

GIVE~ I, ~
AIloJ

CENTE!

II

FREQ~EN~Y

I I I

GAIN AT CENTER FREQUENCY

=

R3 =

f~Cl
2~fol

Rl

=

=

4QIRI _ R3

I
100

I

I (( ((

0OOlt,~~~

O'17~OOl"12

I-Vin

'I\'

R2
-:-1500

V,e!

-

13

+

Voul

":'

R1R3

R2

\

\
./

"

I

Vrms 18K

0.2

70

I

2.0

5.0

i'-

10
20
FREQUENCY 1kHz!

50

100

MC3359
2-51

~s:

UlO
I\:IW

m
r-~------------~-------------------r--------------------,

13~

12

3.5

I!~ ~50 kl
~3

kI

065

?14

I III
071

,.

066

V

I "'-l

~C6-'

070

~63

072

06~

012

068r069

013
'014
33 k ~ 33 k

33 k

15k 062(

33k~ 33 k

3.5 k

061
1k

50 kS 2.5 k

750 U

OSCILLATOR - MIXER

:

50 k

I

(
OP AMP

(BROADCAST DETECTOR

--------------------------------~----------~--------rLIMITING IF AMPLIFIER

DETECTOR AND AFC

_9

m4
.,
022

§

"

"

"

,

"

0189

lOOk 110 k

:0

o

10 k 10 k

10 k 10 k

019·

s;

8:s::
:s::
c
z

(')

:!:;
oz
en
o
~

(')
m

o

~
»

021
17

10 k

33 k

33 k

33 k

33 k

50 k
33 k 10 k

L _________________________________

1~)

-I
~

FIGURE 16 - CIRCUIT SCHEMATIC

33k

5k

057'

___________________ - - -

CIRCUIT DESCRIPTION
The MC3359 is a low-power FM IF circuit designed primarily
for use in voice-communication scanning receivers. It is also
finding a place in narrowband data links.
In the typical application (Figure 1), the mixer-oscillator combination converts the input frequency (10.7 MHz) down to 455
kHz, where, after external bandpass filtering, most of the amplification is done. The audio is recovered using a conventional
quadrature FM detector. The absence of an input signal is indicated by the presence of noise above the desired audio frequencies. This "noise band" is monitored by an active filter
and a detector. A squelch-trigger circuit indicates the presence
of noise (or a tone) by an output which can be used to control
scanning. At the same time. an internal switch is operated
which can be used to mute the audio.

APPLICATION
The oscillator is an internally biased Colpitts type with the
collector, base, and emitter connections at Pin 4, 1, and 2, respectively. The crystal is used in fundamental mode, calibrated
for parallel resonance at 32 pF load capacitance. In theory this
means that the two capacitors in series should be 32 pF, but
in fact much larger values do not significantly affect the oscillator frequency, and provide higher oscillator output.
The oscillator can also be used in the conventional UC Colpitts configuration without loss of mixer conversion gain. This
oscillator is, of course, much more sensitive to voltage and
temperature as shown in Figure 12. Guidelines for choosing L
and C values are given in Figure 14.
The mixer is doubly balanced to reduce spurious responses.
The mixer measurements of Figure 4 and 6 were made using
an external 50 fl source and the internal 1.8 k at Pin 3. Voltage
gain curves at several VCC voltages are shown in Figure 4. The
Third Order Intercept curves of Figure 6 are shown using the
conventional dBm scales. Measured power gain (with the 50
fl input) is approximately 18 dB but the useful gain is much
higher because the mixer input impedance is over 3 kfl. Most
applications will use a 330 fl 10.7 MHz crystal filter ahead of
the mixer. For higher frequencies, the relative mixer gain is
given in Figure 8.
Following the mixer, a ceramic bandpass filter is recommended. The 455 kHz types come in bandwidths from ± 2 kHz
to ± 15 kHz and have input and output impedances of 1.5 k to
2.0 k. For this reason, the Pin 5 input to the 6 stage limiting IF

MOTOROLA COMMUNICATIONS DEVICE DATA

has an internal 1.8 k resistor. The IF has a 3 dB limiting sensitivity of approximately 100 /LV at Pin 5 and a useful frequency
range of about 5 MHz as shown in Figure 5. The frequency
limitation is due to the high resistance values in the IF, which
were necessary to meet the low power requirement. The output of the limiter is internally connected to the quadrature detector, including the 10 pF quadrature capacitor. Only a parallel
UC is needed externally from Pin 8 to VCC. A shunt resistance
can be added to widen the peak separation of the quadrature
detector.
The detector output is amplified and buffered to the audio
output, Pin 10, which has an output impedance of approximatley 300 fl. Pin 9 provides a high impedance (50 k) point in
the output amplifier for application of a filter or de-emphasis
capacitor. Pin 11 is the AFC output, with high gain and high
output impedance (1 M). If not needed, it should be grounded,
or it can be connected to Pin 9 to double the recovered audio.
The detector and AFC responses are shown in Figure 7.
Overall performance of the MC3359 from mixer input to audio output is shown in Figure 9 and 10. The MC3359 can also
be operated in "single conversion" equipment; i.e., the mixer
can be used as a 455 kHz amplifier. The oscillator is disabled
by connecting Pin 1 to Pin 2. In this mode the overall performance is identical to the 10.7 MHz results of Figure 9.
A simple inverting op amp is provided with an output at Pin
13 providing dc bias (externally) to the input at Pin 12, which
is referred internally to 2.0 V. A filter can be made with external
impedance elements to discriminate between frequencies.
With an external AM detector, the filtered audio signal can be
checked for the presence of either noise above the normal
audio, or a tone signal.
The open loop response of this op amp is given in Figure
13. Bandpass filter design information is provided in Figure 15.
A low bias to Pin 14 sets up the squelch-trigger circuit such
that Pin 15 is high, a source of at least 2.0 mA and the audio
mute (Pin 16) is open-circuit. If Pin 14 is raised to 0.7 V by the
noise or tone detector, Pin 15 becomes open circuit and Pin
16 is internally short circuited to ground. There is no hysteresis.
Audio muting is accomplished by connecting Pin 16 to a highimpedance ground-reference point in the audio path between
Pin 10 and the audio amplifier. No dc voltage is needed, in fact
it is not desirable because audio "thump" would result during
the muting function. Signal swing greater than 0.7 V below
ground on Pin 16 should be avoided.

MC3359
2-53

MOTOROLA

-

SEMICONDUCTOR

MC3361B

TECHNICAL DATA

Advance Information
LOW POWER

FM IF

LOW POWER NARROWBAND FM IF
The MC3361 B includes an Oscillator, Mixer, Limiting Amplifier,
Quadrature Discriminator, Active Filter, Squelch, Scan Control,
and Mute Switch. This device is designed for use in FM dual
conversion communications equipment.

SILICON MONOLITHIC
INTEGRATED CIRCUIT

• Operates From 2.0 V to 8.0 V Supply
• Low Drain Current 3.9 mA Typ (W VCC

= 4.0 Vdc

• Excellent Sensitivity: Input Limiting Voltage -3.0 dB = 2.6 /LV Typ
• Low Number of External Parts Required
• Operating Frequency Up to 60 MHz
P SUFFIX
PLASTIC PACKAGE
CASE 648

D SUFFIX
PLASTIC PACKAGE
CASE 7518
(SO·16)
FIGURE 1 -

Gnd

FUNCTIONAL BLOCK DIAGRAM

PIN CONNECTIONS

Scan Squelch Filter Filter Recovered
Mute Control
In
Output Input Audio

Crystal {
Osc.
Mixer Output

3

Audio Mute

Scan Control
limiter Input

5

Squelch Input

Filter Output
Decoupling { 6

9 Demodulator

Output

Crystal
Osc

Decoupling

ORDERING INFORMATION
Coil

This document contains information on a new product. Specifications and information herein are

subject to change without notice.

MC3361B

2-54

MOTOROLA COMMUNICATIONS DEVICE DATA

MAXIMUM RATINGS (TA

=

25'C unless otherwise noted)

Rating

Unit

Pin

Symbol

Value

Power Supply Voltage

4

Vcc(max)

10

Vdc

Operating Supply Voltage Range

4

VCC

2.0 to 8.0

Vdc

-

Detector Input Voltage

8

1.0

Vp-p

Input Voltage (VCC '" 4.0 Volts)

16

V16

1.0

VRMS

Mute Function

14

V14

-0.5 to +5.0

Vpk

Junction Tomperature

-

TJ

150

'c

TA

-30 to + 70

'c

TstQ

-65 to + 150

'c

Operating Ambient Temperature Range
Storage Temperature Range

ELECTRICAL CHARACTERISTICS (VCC = 4.0 Vdc, fo = 10.7 MHz, M = ±3.0 kHz, fmod = 1.0 kHz, TA = 25'C,
unless otherwise noted.)
Characteristic

Pin

Drain Current (No Signal)

Min

Typ

Max

2.9
4.4

3.9
5.4

4.9
6.4

4
Squelch Off
Squelch On

Unit
mA

Recovered Audio Output Voltage (Vin = 10 mVRMS)

9

130

160

200

mVRMS

Input Limiting Voltage (-3.0 dB Limiting)

16

-

2.6

6.0

p.V

Total Harmonic Distortion

9

-

0.86

-

Recovered Output Voltage (No Input Signal)

9

60

120

250

9

-3.0

-0.6

-

dB

450

dB
Vdc

Drop Voltage AF Gain Loss

%
mVRMS

Detector Output Impedance

-

-

Filter Gain (10 kHz) (Vin = 0.3 mVRMS)

-

40

50

-

Filter Output Voltage

11

1.0

1.3

1.6

Mute Function Low

14

-

30

50

Mute Function High

14

1.0

11

-

Mf1

Scan Function Low (Mute Off) (V12 = 1.0 Vdc)

13

-

0

0.4

Vdc

Scan Function High (Mute On) (V12 = Gnd)

13

3.0

3.5

-

Vdc

Trigger Hysteresis

-

-

45

100

mV

Mixer Conversion Gain

3

-

28

-

dB

Mixer Input Resistance

16

-

3.3

-

kf1

Mixer Input Capacitance

16

-

2.2

-

pF

MOTOROLA COMMUNICATIONS DEVICE DATA

f1

f1

MC3361B
2-55

FIGURE 2 - TEST CIRCUIT

0.01

1-__H___...____-oMixer Input

VCCo-.....- - I

10.7 MHz
51

1 - . , . - - - - - - - - - - - 0 Audio Mute

muRata
CFU455D2

1--------....- - 0 Scan Control
0.1

1.0
1---4I1---...,+~I(f-------.....O Filier Amp Out

0.1
1-......t.............WV--+-l(-----o Filter Amp In
1.0
I---'W\r--...- - - - - o AF Output

r--0.1.J

I
I

I
I
L ___ .J Quad Coil

FL 1 -

muRata Erie North America
CFU455D2 or equivalent

Quadrature Coil- Toko America Type 7MC-8128Z
or equivalent
C-

",F. unless noted

FIGURE 4 - AUDIO OUTPUT. DISTORTION
versus TEMPERATURE

FIGURE 3 - AUDIO OUTPUT. DISTORTION
versus SUPPLY VOLTAGE
190
180

-

r- TA

J

25"e

_ 170
CI)

::;;

ff 160
....

2 150

V-

Audio Output

-

8.0

240

7.0

220

£:

6.0 is
~
5.0 l2
CI)

15

en

!; 160

0140

3.0 is

~14O

o

::>

.og

«130

2
Distortion

120

1.0

L----

15

100

---Audio Output _

5

~ 120

7.0

4.0 V

I'-....

Distortion

6.0

~
o
;::

5.0 ~
1;;
4.0

e

3.0
2.0

1.0

~
::>

o

§

~

80

110
2.0

MC3361B
2-56

«

8.0

1

~180

4.0~

15

-Vee

200

!;

o

-

4.0
6.0
Vee. SUPPLY VOLTAGE IV)

8.0

-40

-20

0
+,-20
+40
+60
TA. AMBIENT TEMPERATURE lOCI

+80

MOTOROLA COMMUNICATIONS DEVICE DATA

'"

~
~

9~
"':I;
,,~

~~
g~

~~

H

t:

":i!u

II!

""Ii:

MOTOROLA COMMUNICATIONS DEVICE DATA

MC3361B
2-57

FIGURE 6 -INPUT LIMITING VOLTAGE
+1.0

FIGURE 7 - OVERALL GAIN, NOISE, AND AM REJECTION
+10

Il~~io Out~ut 11.01k~zl

0

I

-1.0

iD- IO

:!;!-2.0

'"

~ -3.0

[::

-...:::::::
S + N (30% AMI
~

~ -40

-4.0

a::

-5. 0

' .....

-50

N

-60

J

1.0

0.01
0.1
INPUT SIGNAL (mVRMsl

-70
0.001

0.01

FIGURE 8 - FILTER AMP RESPONSE
0

60

0

1.0

10

FILTER AMP GAIN

60

-I-

,

~40
z

30
0

iii

50

~40

"

13

0
0

0
0
1.0 k

0.1
INPUT SIGNAL (mVRMsl

FIGURE 9 -

70

50

13

II

~

~

::l

-6.0
0.001

~ ~I mHZ FJ

10 Hz-loo kHz

:!;!

IIII

iD

S~

Voltmeter Frequency Range:

10
10 k

100 k
t, FREQUENCY (Hzl

0

tOM

1.0

2.0

3.0
4.0
5.0
Vcc, SUPPLY VOLTAGE (VI

6.0

7.0

8.0

FIGURE 10 - SUPPLY CURRENT

8.0

u 6.0

1
15

II! 4.0

Sq~elch On

.-...- ..-r-

Squelch Off

--

~

.-...-

::::l
U

~

:t
ill

2.0

o
o

MC33618
2-58

2.0

4.0
6.0
Vcc, SUPPLY VOLTAGE (Vdcl

8.0

MOTOROLA COMMUNICATIONS DEVICE DATA

FIGURE 11- TYPICAL APPLICATION

VCC

=

Scan Control
to PLL

4.0 V

R7
1B k
R9
100 k

1st IF 10.7 MHz
from Input
Front End
C13
10

+

C12

l4.7

Rl0
1.0 k
RB
4.7 k

+

Cl0
0.001

Rl
51

VR2 (Squelch Control)
10 k

R5
3.3 k

Cll
0.1
R4
6.B k

R3
3.3 k

":'

C7
0.022l
CB
0.047

AF Output
to Audio
Power Amp.

VRl
22 k
":'

Units:
R: n
C : /LF
unless noted

FL 1 -

muRata Erie North America
Type CFU455D2 or equivalent

Quadrature Coil - Taka America
Type 7MC-B12BZ or equivalent

MOTOROLA COMMUNICATIONS DEVICE DATA

MC3361B

2-59

MOTOROLA

-

SEMICONDUCTOR
TECHNICAL DATA

MC3362
LOW POWER NARROWBAND FM RECEIVER

LOW-POWER
DUAL CONVERSION
FM RECEIVER

· .. includes dual FM conversion with oscillators, mixers, quadrature detector, and meter drive/carrier detect circuitry. The
MC3362 also has buffered first and second local oscillator outputs
and a comparator circuit for FSK detection.

SILICON MONOLITHIC
INTEGRATED CIRCUIT

• Wide Input Bandwidth:
- 200 MHz using Internal Local Oscillator
- 450 MHz using External Local Oscillator
• Complete Dual Conversion Circuitry
• Low Voltage: VCC

=

~-

2.0 to 7.0 Vdc

• Low Drain Current (3.6 mA (Typ) @ Vee

=

3.0 Vdc)

• Excellent Sensitivity: Input 0.7 }LV (Typ) for 12 dB SINAD
• Data Shaping Comparator

1

• Received Signal Strength Indicator (RSSI) with 60 dB
Dynamic Range

P SUFFIX
PLASTIC PACKAGE
CASE 724

• Low Number of External Parts Required
• Manufactured in Motorola's MOSAIC Process Technology

24

RF Input
to 200 MHz

FIGURE 1 -

""~
DW SUFFIX
PLASTIC PACKAGE
CASE 751E
SO-24

TYPICAL APPLICATION IN A PLL FREQUENCY
SYNTHESIZED RECEIVER

FIGURE 2 - PIN CONNECTIONS AND
FUNCTIONAL BLOCK DIAGRAM

VCC
Detector

2

1st Mixer Input 1

3
0.41 I'H

4

2nd LO Output 2

5

2nd LO Emitter 3

2nd LO Base 4
2nd Mixer Output 5

16
10 k

Limiter Input 7

0.1

15
Data
14
13

VCC

Limiter
Decoupling

17 2nd Mixer Input

Limiter
Decoupling

15 Comparator Output

Lp = 680 I'H I
Cp = 180 pF 1
I

L

r, _
...L

'- ______ J

Carrier Detect "

Quadrature Coil 12

MC3362
2-60

14 Comparator Input

-

13 Detector Output

MOTOROLA COMMUNICATIONS DEVICE DATA

MAXIMUM RATINGS (TA

= 25°C, unless otherwise noted)

Rating

Pin

Symbol

Value

Power Supply Voltage

6

VCC(max)

8.0

Vdc

Operating Supply Voltage Range (Recommended)

6

VCC

2.0 to 7.0

Vdc

1,24

Vl-24

Input Voltage (VCC ;;, 5.0 Vdc)

Unit

1.0

Vrms

TJ

150

°c

Operating Ambient Temperature Range

-

TA

-40 to +85

°c

Storage Temperature Range

-

Tst~

-65 to + 150

°c

Junction Temperature

ELECTRICAL CHARACTERISTICS (VCC

= 5.0 Vdc, fo = 49.7 MHz, Deviation
unless otherwise noted)

Characteristic
Drain Current (Carrier Detect Low -

Pin

See Figure 5)

6

-

Input for -3.0 dB Limiting
Recovered Audio (RF signal level
Noise Output (RF signal level

=

=

10 mY)

13

0 mY)

13

Carrier Detect Threshold (below VCe!

10

Meter Drive Slope

10

Input for 20 dB (S + N)/N (See Figure 7)

Second Mixer Conversion Voltage Gain

-

Detector Output Resistance

13

First Mixer 3rd Order Intercept (Input)
First Mixer Input Resistance (Rp)
First Mixer Input Capacitance (Cp)
First Mixer Conversion Voltage Gain

FIGURE 3 -

=

3.0 kHz, TA

Min

-

=

25°C, Test Circuit of Figure 3

Typ

Max

4.5

7.0

mA

0.7

2.0

JLVrms

350

mVrms

0.64

-

100

-

nAidB

0.7

JLVrms

250

Units

mVrms
Vdc

18

-

21

-

dB

1.4

-

k!1

-22
690
7.2

dBm
!1
pF
dB

TEST CIRCUIT

10.5 Turns
Coilcraft
UNI-l0/142

6

MC3362

FL1:
muRata CFU455D
or
Taka LFC-4551

19

7

18

8

17

9

16

10

15

11

14

12

13

0.1

FL2:
muRata SFE10.7MA
ar
Toko SK107M3-AO-l0

+1.0JLF
Toka RMC-2A6597HM
VCCo-__--------------------------------~--~~--~--_o VEE

MOTOROLA COMMUNICATIONS DEVICE DATA

MC3362
2-61

FIGURE 4 -

12
11
10
9.0

«

I

I

.1

'"

I

5.0

7.0

,,/

/'

5.0

«

./

.s

'-'

./

ICC, Carr. Det.' High IRF'in

4.0

.S?

3.0

./

!----

ICc,ICarr. Det~ Low IRFlin = 10

6.0

/'

8.0

6.0

800

./

MC3362

..:; 7.0

DRAIN CURRENT, RECOVERED AUDIO versus SUPPLY

8.0

:=~'~
A

FIGURE 5 -

IMETER versus INPUT

fl

2.0

4.0
2.0
-130 -120 -110 -100 -90

-80

-70

-60

-50 -40

-30

1.0

0

+20
+10

First Mixer Output

-2 0

0..

'><"

First Mixer Input

-50

.,ij

,,/

-.....~V'

,,/

-60
~"
-7 0
-130 -120 -110 -100
90

A

FIGURE 8 -

~

f--

~

.,,0 V

100
3.0

80 -70
RF INPUT IdBm!

~V

,/

-60

-50

40

-10
iii

0

30

FIGURE 9 -

-40

",/

-5 0
-60

/

",/

V
L -90 -80

-70
-80
-100

MC3362
2-62

/
-70

3.0

- _\

~ 2.0
M

\ '-

->

3rd Order Intermod.

-30

-20

-60

-50

-40 -30

--...

I-'"

,-

1.0

/

-60 -50 -40
RF INPUT IdBm!

N

DETECTOR OUTPUT versus FREQUENCY

,,/

V

pro,ducts ,

I---

S+N30%AM

"""

/ ' "i'

I

~

'" -50 MC3362I 13 10k
10 k
-60
001+ :;t;+001
-70
-80
-130 -120 -110 -100 -90 -80 -70
RF INPUT IdBm!

/1

Desired Productv

S + N, N, AMR versus INPUT

~

v/

-30

8.0

4.0

/

0

~

o

7.0

~

z·
Z -40

1ST MIXER 3RD ORDER INTERMODULATION

",/

6.0

5.0

S+N

~ -30

0

-2 0

4.0

+

e>:;: f-<-RF Input to Transformer

-10

->

200

2.0

::s::

;; -20

.bV

r:x;:::"

./

-40

..---

-.....

'0V

Second Mixer Input V

'"
~ -30

M

Recovered Audio -

FIGURE 7 -

SIGNAL LEVELS

Second Mixer Output
~

I

400

VCC IV!

0

E

600
500

300

jl

0

-1 0

----- --::::

~;::

k:::::::;;; ~ ~ F-\

RF INPUT IdBm!

FIGURE 6 -

>-

Ii

1.0

3.0

.:.:l~

700

~VJ-.....

-10

o

-40

-30

-20

-10

0

- -

10

~

20

30

40

RELATIVE INPUT FREQUENCY 1kHz!

MOTOROLA COMMUNICATIONS DEVICE DATA

CIRCUIT DESCRIPTION
The MC3362 is a complete FM narrowband receiver
from antenna input to audio preamp output. The low
voltage dual conversion design yields low power drain,
excellent sensitivity and good image rejection in narrowband voice and data link applications.
In the typical application (Figure 1), the first mixer
amplifies the signal and converts the RF input to 10.7
MHz. This IF signal is filtered externally and fed into the
second mixer, which further amplifies the signal and
converts it to a 455 kHz IF signal. After external bandpass filtering, the low IF is fed into the limiting amplifier
and detection circuitry. The audio is recovered using a
conventional quadrature detector. Twice-IF filtering is
provided internally.
The input signal level is monitored by meter drive
circuitry which detects the amount of limiting in the
limiting amplifier. The voltage at the meter drive pin
determines the state of the carrier detect output, which
is active low.

APPLICATION
The first local oscillator can be run using a freerunning LC tank, as a VCO using PLL synthesis, or
driven from an external crystal oscillator. It has been
run to 190 MHz.* A buffered output is available at Pin
20. The second local oscillator is a common base Colpitts type which is typically run at 10.245 MHz under
crystal control. A buffered output is available at Pin
2. Pins 2 and 3 are interchangeable.
The mixers are doubly bahinced to reduce spurious
responses. The first and second mixers have conversion gains of 18 dB and 22 dB (typical), respectively,
as seen in Figure 6. Mixer gain is stable with respect
to supply voltage. For both conversions, the mixer
impedances and pin layout are designed to allow the
user to employ low cost, readily available ceramic filters. Overall sensitivity and AM rejection are shown
in Figure 7. The input level for 20 dB (5 + N)/N is 0.7
p.V using the two-pole post-detection filter pictured.

Following the first mixer, a 10.7 MHz ceramic bandpass filter is recommended. The 10.7 MHz filtered signal is then fed into one second mixer input pin, the
other input pin being connected to VCC.
The 455 kHz IF is typically filtered using a ceramic
bandpass filter then fed into the limiter input pin. The
limiter has 10 p.V sensitivity for -3.0 dB limiting, flat
to 1.0 MHz.
The output of the limiter is internally connected to
the quadrature detector, including a quadrature
capacitor. A parallel LC tank is needed externally from
Pin 12 to VCC. A 68 kG shunt resistance is included
which determines the peak separation of the quadrature detector; a smaller value will increase the spacing and linearity but decrease recovered audio and
sensitivity.
A data shaping circuit is available and can be coupled to the recovered audio output of Pin 13. The circuit is a comparator which is designed to detect zero
crossings of FSK modulation. Data rates of 2000 to
35000 baud are detectable using the circuit of Figure
1. Hysteresis is available by connecting a high-valued
resistor from Pin 15 to Pin 14. Values below 120 kG
are not recommended as the input signal cannot overcome the hysteresis.
The meter drive circuitry detects input signal level
by monitoring the limiting of the limiting amplifier
stages. Figure 4 shows the unloaded current at Pin 10
versus input power. The meter drive current can be
used directly (RSSI) or can be used to trip the carrier
detect circuit at a specified input power. To do this,
pick an RF trip level in dBm. Read the corresponding
current from Figure 4 and pick a resistor such that:
R10 = 0.64 Vdc 1110
Hysteresis is available by connecting a high-valued
resistor RH between Pins 10 and ,11. The formula is:
Hyst. = VCC/(RH x 10- 7 ) dB

*If the first local oscillator (Pins 21 andlor 22) is driven from
a strong external source (100 mVrms), the mixer can be
used to over 450 MHz.

MOTOROLA COMMUNICATIONS DEVICE DATA

MC3362
2-63

J~

-(])-

-ro-

,~

-ill-

~fL

~
~

y

~

A Y
.~.

. .0

~+---{j§] Recovered Audio
--'1oW Mute Input

MC3363
2-65

MAXIMUM RATINGS (TA

=

25°C unless otherwise noted)

Rating

Pin

Symbol

Value

Power Supply Voltage

8

VCC(max)

8.0

Vdc

Operating Supply Voltage Range
(Recommended)

8

VCC

2.0 to 7.0

Vdc

Input Voltage (VCC

=

5.0 Vdc)

Unit

1,28

V1-28

1.0

Vrms

Mute Output Voltage

19

V19

-0.7 to 8.0

Vpk

Junction Tem'perature

-

TJ

150

°c

Operating Ambient Temperature Range

-

TA

-40 to +85

°c

Storage Temperature Range

-

Tstg

-65to +150

°c

ELECTRICAL CHARACTERISTICS (VCC = 5.0 Vdc, fo = 49.7 MHz, Deviation = ±3.0 kHz, TA
Test Circuit of Figure 2 unless otherwise noted)
Characteristic

Pin

= 25°C,

Typ

Max

Drain Current (Carrier Detect Low)

8

-

4.5

8.0

rnA

-3.0 dB Limiting Sensitivity (RF Amplifier Not Used)

-

-

0.7

2.0

/LVrms

Unit

-

1.0

-

/LVrms

1,28

-

690

-

Ohm

1,28

7.2

-

18

2nd Mixer Conversion Voltage Gain (Avc 2, Open Circuit)

-

-

-

21

-

2nd Mixer Input Sensitivity (20 dB SIN) (10.7 MHz i/p)

21

-

10

-

/LVrms
/LVrms

20 dB SIN Sensitivity (RF Amplifier Not Used)
1st Mixer Input Resistance (Parallel -

Rp)

1st Mixer Input Capacitance (Parallel -

Cp)

1st Mixer Conversion Voltage Gain (Avc 1, Open Circuit)

-

Min

Mod 1.0 kHz,

pF
dB
dB

Limiter Input Sensitivity (20 dB SIN) (455 kHz i/p)

9

-

100

-

RF Transistor DC Current Drain

4

1.0

1.5

2.5

mAdc

16

120

200

mVrms

16

-

-

mVrms

16

Recovered Audio (RF Signal Level
Noise Output Level (RF Signal

=

=

1.0 mV)

0 mV)

70

-

2%

-

%

400

-

Ohm
Vdc
Vdc

Detector Output Impedance

16

-

Data (Comparator) Output Voltage - High
-Low

18
18

-

VCC

0.1

0.1

-

Data' (Comparator) Threshold Voltage Difference

17

70

110

150

mV

Meter Drive Slope

12

70

100

135

nAidB

Carrier Detect Threshold (Below VccI

12

0.53

0.64

0.77

Vdc

Mute Output Impedance - High
-Low

19
19

10
25

-

Mohm
Ohm

THO of Recovered Audio (RF Signal

MC3363
2-66

=

1.0 mV)

-

-

-

MOTOROLA COMMUNICATIONS DEVICE DATA

s::

a

FIGURE 2 -

:Il

VCC

o

TEST CIRCUIT

= 5.0 Vdc

>
(')

o

s::
s::
c
z

o
~

1st Mixer Input
50 MHz

CRF 1: muRata SFE 10.7 M
or Equivalent

5z

CRF 2: muRata CFU 455D
or Equivalent

en
o
~

L1: Coilcraft UNI 10/142 lOY, Turns

om

LC1: Toko RMC2A6597HM

o

»~

From PLL Phase Detector

To PLL Phase Detector

+

1

11O~F

0.1

10k

":"

~

4IID

, ,

0

Mute Output

0

Comparator Output

390 k

'> I

1m

'IMo

'l/iiio

5.0 k

10 k

L....l~~~~
-vv..------,~

(')
NCo)

~B

L = 680~H
C = 180 pF

- - v Carrier Detect Output

Recovered Audio
Output

Comparator Test Input

0.Q1

i:

0

L..---------O Mute Input

CIRCUIT DESCRIPTION
The MC3363 is a complete FM narrowband receiver
from RF amplifier to audio preamp output. The low voltage dual conversion design yields low power drain,
excellent sensitivity and good image rejection in narrowband voice and data link applications.
In the typical application, the input RF signal is amplified by the RF transistor and then the first mixer amplifies the signal and converts the RF input to 10.7 MHz.
This IF signal is filtered externally and fed into the second mixer, which further amplifies the signal and converts itto a 455 kHz IF signal. After external bandpass
filtering, the low IF is fed into the limiting amplifier and
detection circuitry. The audio is recovered using a conventional quadrature detector. Twice-IF filtering is provided internally.
The input signal level is monitored by meter drive
circuitry which detects the amount of limiting in the
limiting amplifier. The voltage at the meter drive pin
determines the state of the carrier detect output, which
is active low.

APPLICATION
The first local oscillator is designed to serve as the
VCO in a PLL frequency synthesized receiver. The
MC3363 can operate together with the MC145166n to
provide a two-chip ten channel frequency synthesized
receiver in the 46/49 cordless telephone band. The
MC3363 can also be used with the MC14515X series of
CMOS PLL synthesizers and MC120XX series ofECL
prescalers in VHF frequency synthesized applications to
200 MHz.
For single channel applications the. first local oscillator can be crystal controlled. The circuit of Figure 4
has been used successfully up to 60 MHz. For higher
frequencies an external oscillator signal can be injected
into Pins 25 and/or 26 - a level of approximately 100
mVrms is recommended. The first mixer's transfer characteristic is essentially flat to 450 MHz when this
approach is used (keeping a constant 10.7 MHz IF frequency). The second local oscillator is a Colpitts type
which is typically run at 10.245 MHz under crystal
control.
The mixers are doubly balanced to reduce spurious
responses. The first and second mixers have conversion
gains of 18 dB and 21 dB (typical), respectively. Mixer.
gain is stable with respect to supply voltage. For both
conversions, the mixer impedances and pin layout are
designed to allow the user to employ low cost, readily
available ceramic filters.
Following the first mixer, a 10.7 MHz ceramic bandpass filter is recommended. The 10.7 MHz filtered signal
is then fed into the second mixer input Pin 21, the other
input Pin 22 being connected to VCC.
The 455 kHz IF is filtered by a ceramic narrow bandpass filter then fed into the limiter input Pin 9. The limiter
. has 10 !LV sensitivity for -3.0 dB limiting, flat to 1.0
MHz.

MC3363

2-68

The output of the limiter is internally connected to
the quadrature detector, including a quadrature capacitor. A parallel LC tank is needed externally from Pin 14
to VCC. A 68 kOhm shunt resistance is included which
determines the peak separation ofthe quadrature detector; a smaller value will lower the Q and expand the
deviation range and linearity, but decrease recovered
audio and sensitivity.
A data shaping circuit is available and can be coupled
to the recovered audio output of Pin 16. The circuit is
a comparator which is designed to detect zero crossings
of FSK modulation. Data rates of 2000 to 35000 baud
are detectable using the comparator. Best sensitivity is
obtained when data rates are limited to 1200 baud maximum. Hysteresis is available by connecting a high-valued resistor from Pin 17 to Pin 18. Values below 120
kOhm are not recommended as the input signal cannot
overcome the hysteresis.
The meter drive circuitry detects input signal level by
monitoring the limiting of the limiting amplifier stages.
Figure 5 shows the unloaded current at Pin 12 versus
input power. The meter drive current can be used
directly (RSSI) or can be used to trip the carrier detect
Circuit at a specified input power.
A muting op amp is provided and can be triggered
by the carrier detect output (Pin 13). This provides a
carrier level triggered squelch circuit which is activated
when the RF input atthe desired input frequency falls
below a preset level. The level at which this occurs is
determined by the resistor placed between the meter
drive output (Pin 12) and VCC. Values between 80-130
kOhms are recommended. This type of squelch is pictured in Figures 3 and 4.
Hysteresis is available by connecting a high-valued
resistor Rh between Pins 12 and 13. The formula is:
Hyst = VCC/ (Rh x 10- 7) dB
The meter drive can also be used directly to drive a
meter or to provide AGC. A current to voltage converter
or other linear buffer will be needed for this application.
A second possible application of the op amp would
be in a noise triggered squelch circuit, similar to that
used with the MC3357/MC3359/MC3361 FM 1.F.'s.ln this
case the op amp would serve as an active noise filter,
the output of which would be rectified and compared
to a reference on a squelch gate. The MC3363 does not
have a dedicated squelch gate, but the NPN RF input
stage or data shaping comparator might be used to
provide this function if available. The op amp is a basic
type with the inverting input and the output available.
This application frees the meter drive to allow it to be
used as a linear signal strength monitor.
The circuit of Figure 4 is a complete 50 MHz receiver
from antenna input to audio preamp output. It uses few
components and has good performance. The receiver
operates on a single channel and has input sensitivity
of <0.3 !LV for 12 dB SINAD.

MOTOROLA COMMUNICATIONS DEVICE DATA

s::

~

FIGURE 3 - TYPICAL APPLICATION IN A PLL FREQUENCY SYNTHESIZED RECEIVER

~

>

VCC

=

5.0 Vdc

o

o
s::
s::
c
z

(')

27 pF

:!:;

oz
en
o
~

(')

m

RF Input
49.670 to
49.970 MHz

CRF1: muRata SFE 10.7M
CRF2: muRata CFU 4550
LC1: Toko RMC2A6597HM

2.0T

0.01

~I

III

o

:!i
»

-+_____ From PLL Phase Detector

L-_ _ _ _ _ _ _ _

':"

CRl
10.245 M
3.0 k

To
MC145166n
Dual PLL
Frequency
Synthesizer

Vcc (Regulated)

IPin 27
Mute
Control

I
T
100 k

i1 (
1.0 /LH

LCl

L

'='

•

Cr

t 3.3
Pull-Up Resistc
k to 20 k

I Pin 26
L = 0.08/LH

I

Pin 25

Recovered Audio
Output

r
fosc: 200 MHz

Pin 24
L = 680/LH
C = 180 pF

5:

o

~W

m~

CDW

Note: Pull Up resistor is
used to run the oscillator above 50 MHz_

1\)5:
':"0
Ow

~

FIGURE 4 -

SINGLE CHANNEL CRYSTAL CONTROLLED FM RECEIVER

VCC = 5.0Vdc

Antenna
49.830 MHz
1.0 k

CRF1: muRata SFE 10.7M
CRF2: muRata CFU 4550
LC1: Toko RMC2A6597HM

20 k
1.2/LH

1000

CRl
10.245 M

=

CR2 39.130 MHz

~

+

T f

10 /LF

0.1~
10 k

i!:

a
o

L...fj]]

II

>

8i!:

Data Output

Mute
Control

i!:

c
z
C5
~
5z
en
o
m
<
C5
m
o
»~

•

68 k

LCll

,
I

~I

L ___ J
L=680/LH
C = 180 pF

-=

100 k

+I(
Cl0 1.0 ,.F

•

Recovered Audio
Output

s::
~
o:II
o

>

FIGURE 5 - CIRCUIT SCHEMATIC

8s::

27

s::
c

6

z

('5

~

8

(5

7

23

zen

6~.

o
~
('5
m

5

o

»~

Bias

ht

2 '-'

rr

120 ,

13

3 ••• Bias

15

14

19

11
17

16

18

20

1
3:

o

I\)W

..:...~

-W

MOTOROLA

-

SEMICONDUCTOR
TECHNICAL DATA

MC3367
LOW VOLTAGE FM NARROWBAND RECEIVER
· .. with single conversion circuitry including oscillator, mixer, IF
amplifiers, limiting IF circuitry, and quadrature discriminator. The
MC3367 is perfect for narrowband audio and data applications up
to 75 MHz which require extremely low power consumption. Battery powered applications down to VCC = 1.1 V are possible. The
MC3367 also includes an on-board voltage regulator, low battery
detection circuitry, a receiver enable allowing a power down
"sleep mode," two undedicated buffer amplifiers to allow simultaneous audio and data reception, and a comparator for enhancing FSK (Frequency Shift Keyed) data reception.

LOW VOLTAGE
SINGLE CONVERSION
FM RECEIVER
SILICON MONOLITHIC
INTEGRATED CIRCUIT

• Low Supply Voltage: VCC = 1.1 to 3.0 Vdc
• Low Power Consumption: PD = 1.5 to 5.0 mW
• Input Bandwidth 75 MHz
• Excellent Sensitivity: Input Limiting Voltage (- 3.0 dB)
= 0.2l'Vrms
• Volta.ge Regulator Available (Source Capability 3.0 rnA)
• Receiver Enable to Allow Active/Standby Operation

OW SUFFIX
PLASTIC PACKAGE
CASE 751F
SO-28

• Low Battery Detection Circuitry
• Self Biasing Audio Buffer with Nominal Gain AV = 4.0
• Data Buffer with Nominal Gain AV = 3.2
• Comparator with> 25 kHz (50 kbaud) Capability
• Standard 2a-Lead Surface Mount (SOIC) Package

FIGURE 1 -

MC3367

2-72

BLOCK DIAGRAM

PIN CONNECTIONS

Mixer Dcpl.
Mixer Out
Mixer In
Osc. Dcpl.
Osc. Base
Osc. Emit.
Isrc Dcpl.
IF Gnd
VCC2
Rec. Audio
Quad Tank
Quad Tank
Demod. Gnd
Comparator I/P..".J.;.;_ _-,-'

2nd IF Amp In
Data Buffer Out
Data Buffer In
1st IF Amp Out
VCC3
1st IF Amp In
Audio Buffer Out
Audio Buffer In
Low Battery Det.
1.2 V Select
VCC
Vreg
Receiver Enable
Comparator O/P

MOTOROLA COMMUNICATIONS DEVICE DATA

ABSOLUTE MAXIMUM RATINGS (Voltages referred to Pin 12; TA
Parameter

= 25'C)

Pin

Value

Supply Voltage

18

5.0

Vdc

RF Input Signal

3

1.0

Vrms

Audio Buffer Input

21

1.0

Vrms

Data Buffer Input

26

1.0

Vrms

Comparator Input

14

1.0

Vrms

'c
'c

Junction Temperature

-

150

Storage Temperature

-

-65 to +150

Units

Devices should not be operated at or outside these values. The "Recommended Operating Limits"
provide for actual device operation.

RECOMMENDED OPERATING CONDITIONS
Pin

Value

Units

Supply Voltage

Parameter

18

1.1 to 3.0

Vdc

Receiver Enable Voltage

16

o or VCC

Vdc

1.2 V Select Voltage

19

VCC

Vdc

RF Input Signal

3

0.001 to 100

mVrms
MHz

RF Input Frequency

3

o to 75

Intermediate Frequency (IF)

-

455

kHz

Audio Buffer Input

21

mVrms

Data Buffer Input

26

o to 75
o to 75

Comparator Input

14

10 to 300

mVrms

Ambient Temperature

-

o to 70

'c

mVrms

FIGURE 2 - TEST CIRCUIT
(All capacitors in p.F unless otherwise stated. Resistors in ohms. Inductors in Henries.)
FLl = FL2 =
Toko LFC-455FII
or
muRata CFU 455D/E/F

28
2

27

3

26

4

25

5

24

6

0.1~

1.0
Cp = 180 P

T
"::"

Toko RMC
2A 6597HM

22

8

21

9

20

10

19

11

18

12

17

13

16

14

MOTOROLA COMMUNICATIONS DEVICE DATA

23

7

56 k

330
~0.1

100 k

VCC

+

~1.0

15
100 k

MC3367
2-73

ELECTRICAL CHARACTERISTICS (Vcc ~ 1.3 V, fo ~ 45 MHz, fmod ~ 1.0 kHz, Deviation ~ 3.0 kHz, TA ~ 25°C,
Test Circuit of Figure 2 unless otherwise noted)
Characteristic

I

Pin

I

Min

Typ

Max

Units

3.0

mA
fLA

OVERALL MC3367 PERFORMANCE
Drain Current - Pin 15
-Pin 15

~

VCC
OVdc

~

Recovered Audio (RF Input
Noise Output (RF Input

~

~

10 mY)

0 mY)

Input for -3.0 dB Limiting

-

-

1.4
0.5

10
10

-

4.5

3

-

0.2

13

-

mVrms

mVrms
fLVrms

MIXER
Mixer Input Resistance (Rp)
Mixer Input Capacitance (Cp)
FIRST IF AMPLIFIER

I First IF Amp Voltage Gain

25

dB

AUDIO BUFFER
Voltage Gain

-

Input Resistance

21

Maximum Input for Undistorted Output

21

Maximum Output Swing

22

Output Resistance

22

-

4.0

-

125

-

70
800
680

VN

k!1
mVrms

mVpp
!1

DATA BUFFER
Voltage Gain

26

-

3.2

Input Resistance
Maximum Input for Undistorted Output

26

-

70

Maximum Output Swing

27

-

600

Output Resistance

27

-

1.5

14

-

7.0

-

1.09

8.0

-

VN

M!1
mVrms

mVpp
k!1

COMPARATOR
Minimum Input for Triggering
Maximum Input Frequency (RL
Rise Time (10-90%; RL
Fall Time (90-10%; RL

~

~

~

100 k(1)

100 k!1)
100 k!1)

14
15
15

25
5.0
0.4

-

mVrms

-

Vdc

kHZ
fLs
fLS

LOW BATTERY DETECTOR
Low Battery Trip Point
Low Battery Output - VCC
-VCC

18.
~
~

0.9 V
1.3 V

20
20

0.2
VCC

-

Vdc
Vdc

VOLTAGE REGULATOR
Regulated Output (see Figure 6)
Source Capability

MC3367

2-74

MOTOROLA COMMUNICATIONS DEVICE DATA

FIGURE 3 -

80

60

1200
V22

r

40

v

1400

22
50

DRAIN versus SUPPLY

1600

---t>-h
~1.0~

70

i

FIGURE 4 -

RECOVERED AUDIO versus SUPPLY

1000

j

I
I

800

u

~

30

600

20

400

V9

10

I

200

o
o

0.5

1.0

1.5

FIGURE 5 -

2.0
VeelVI

2.5

3.0

3.5

o

o

4.0

S + N, N versus INPUT

SOO

+10

800

-20
-30
-40
-50
-60

2.0
VeelVI

2.5

3.0

3.5

4.0

1000

+20

o

1.5

1.0

FIGURE 6 - VREG versus SUPPLY

+30

-10

0.5

S+N

.;::-1-

700 Rl

:>

r--....

.§.

....
->

R"-."

6
~e"
27
0.1 R = 56kU

t..-I-Rl7 330
I- Rllsso

I

200

~
22

500
400
300

N

e=1000pF
e~ Output

-70130_120 -110 -100 -90 -80 -70 -60 -50

="

600

100
40

30

o0

0.5

1.0

1.5

2.0

2.5
3.0
VeelVI

3.5

4.0

4.5

5.0

CIRCUIT DESCRIPTION

APPLICATION

The MC3367 is an FM narrowband receiver capable
of operation to 75 MHz. The low voltage design yields
low power drain and excellent sensitivity in narrowband
voice and data link applications. In the typical application the mixer amplifies the incoming RF or IF signal
and converts the RF or IF frequency to 455 kHz. This
signal is then filtered by a 455 ceramic filter and applied
to the first intermediate frequency (IF) amplifier input.
This amplifier amplifies the 455 kHz IF before it is filtered
by a second ceramic filter. The modulated IF signal is
then applied to the limiting IF amplifier and detector
circuitry. Audio is recovered by a conventional quadrature detector.
Features available include buffers for audio/data
amplification and active filtering, on board voltage regulator, low battery detection circuitry with programmable level, and receiver disable circuitry. The MC3367
is an FM utility receiver to be used for voice and/or
narrowband data reception, especially suitable where
extremely low power consumption and high design
flexibility are required.

The MC3367 can be used as a high performance FM
IF for use in low power dual conversion receivers.
Because of the MC3367's extremely good sensitivity
(0.6/LV for 20 dB (S + N)/N, see Figure 5), it can also
be used as a stand alone single conversion narrowband receiver to 75 MHz for applications not sensitive
to image frequency interference.
The oscillator is a Colpitts type which can be run as
an LC oscillator or under crystal control. The crystal
in Figure 2 is a 3rd overtone series mode type, and
the 1.2 /LH coil (L1) and 1.0 kG resistor are needed to
ensure proper operation. For fundamental mode crystals, the inductor L1 can be omitted.
The best adjacent channel and sensitivity response
occur when two 455 kHz ceramic filters are used, as
shown in Figure 2. Either can be replaced by a 0.1 /LF
coupling capacitor to reduce cost, but some degradation in sensitivity and/or stability is suspected.
The detector is a quadrature type, with the connection from the limiter output to the detector input provided internally as with the MC3359 and the MC3361.

MOTOROLA COMMUNICATIONS DEVICE DATA

MC3367
2-75

~i:

atO
~
FIGURE 7 - CIRCUIT SCHEMATIC

11

2

24

23

25 28

9

12

17

13.7 k

3~

40
5
6

0

.~

'1

70
80

13~

180

l $
I

100 k

s::
o

100
k

d
~

>

8
s::
s::
c

11 k

z

(')

~

(5

z
en
cm
<
(')

m

c

?i»

19

20 16

14

15

26

27

21

22

A 455 kHz LC tank circuit must be provided externally.
One of the tank pins (Pin 11) must be decoupled using
a 0.1 /LF capacitor. The 56 kG damping resistor shown
in Figure 2 determines the peak separation (and thus
the detector bandwidth) of the detector. Smaller values will increase the separation and bandwidth but
decrease recovered audio and sensitivity.
The data buffer is a non-inverting amplifier with a
nominal voltage gain of 3.2 VN. This buffer needs its
dc bias (approx. 250 mV) provided externally or else
debiasing will occur. A single-pole RC filter as shown
in Figure 5 connecting the recovered audio output to
the data buffer input provides the necessary dc bias and
some post-detection filtering. The buffer can also be
used as an active filter.
The audio buffer is a non-inverting amplifier with a
nominal voltage gain of 4.0 VN. This buffer is selfbiasing so its input should be ac coupled. The two
buffers, when used as active filters, can be used
together to allow simultaneous audio and very lowspeed data reception. Another possible configuration
is to receive audio only and include a noise-triggered
squelch.
The comparator is a non-inverting type with an open
collector output. Typically the pull-up resistor used
between Pin 15 and VCC is 100 kG. With RL = 100 kG

MOTOROLA COMMUNICATIONS DEVICE DATA

the comparator is capable of operation up to 25 kHz.
This circuit is self-biasing, so its input should be ac
coupled.
The regulator is a 0.95 V reference capable of sourcing
3.0 mAo This pin (pin 17) needs to be decoupled using
a 1.0-10 /LF capacitor to maintain stability of the
MC3367.
All three VCC's on the MC3367 (Vce. VCC2. VCC3) run
on the same supply voltage. Vce is typically decoupled
using capacitors only. VCC2 and VCC3 should be
bypassed using the RC bypasses shown in Figure 2.
Eliminating the resistors on the VCC2 and VeC3
bypasses may be possible in some applications, but a
reduction in sensitivity and quieting will likely occur.
The low battery detection circuit gives an NPN open
collector output at Pin 20 which drops low when the
MC3367 supply voltage drops below 1.1 V. Typically it
would be pulled up via a 100 kG resistor to supply.
The 1.2 V Select pin, when connected to the MC3367
supply, programs the low battery detector to trip at VCC
< 1.1 V. Leaving this pin open raises the trip voltage on
the low battery detector.
Pin 16 is a receiver enable, which is connected to Vee
for normal operation. Connecting this pin to ground
shuts off receiver and reduces current drain to Ice <
0.5/LA.

MC3367

2-n

MOTOROLA

-

MC3371
MC3372

SEMICONDUCTOR
TECHNICAL DATA

Advance Information

Low Power
Narrowband FM IF

LOW POWER

FM IF

The MC3371 and MC3372 perform single conversion FM reception and
consist of an oscillator, mixer, limiting IF amplifier, quadrature discriminator, active filter, squelch switch, and meter drive circuitry. These devices
are designed for use in FM dual conversion communication equipment.
The MC3371/MC3372 are similar to the MC3361/MC3357 FM IFs, except
that a signal strength indicator replaces the scan function controlling driver
which is in the MC3361/MC3357. The MC3371 is designed for the use of
parallel LC components, while the MC3372 is designed for use with either
a 455 kHz ceramic discriminator, or parallel LC components.
These devices also require fewer external parts than earlier products.
The MC3371 and MC3372 are available in dual-in-line and surface mount
packaging.
•
•
•
•
•
•
•

,.#
,
PSUFFIX
PLASTIC PACKAGE
CASE 648

Wide Operating Supply Voltage Range: VCC =2.0 to 9.0 V
Input Limiting Voltage Sensitivity of -3.0 dB
Low Drain Current: ICC = 3.2 mA, @ VCC = 4:0 V, Squelch Off
Minimal Drain Current Increase When Squelched
Signal Strength Indicator: 60 dB Dynamic Range
Mixer Operating Frequency Up to 100 MHz
Fewer External Parts Required than Earlier Devices

D SUFFIX
PLASTIC PACKAGE
CASE 7518
(SO-16)

PIN CONNECTIONS

Cry~al{

MAXIMUM RATINGS

Osc.

Pin

Symbol

Value

Unit

Power Supply Voltage

4

Vcc(max)

10

Vdc

RF Input Voltage (VCC ;;. 4.0 Vdc)

16

V,6

1.0

Vrms
Vp _p

Rating

SILICON MONOLITHIC
INTEGRATED CIRCUIT

Detector Input Voltage

a

Va

1.0

Squelch Input Voltage (VCC ;;. 4.0 Vdc)

12

V,2

6.0

Vdc

Mute Function

14

V,4

-0.7 to 10

Vpk

Mute Sink Current

14

1,4

50

mA

Junction Temperature

-

TJ

150

·C

Storage Temperature Range

-

TstA

-65 to +150

·C

1

Mixer Output
Meter Drive
limiter Input
. {
Decouphng

Squelchlnpu!

6
Recovered
Audio

Quad Coil

Devices should not be operated at these values. The "Recommended Operating Conditions" table
provides conditions for actual device operation.

RECOMMENDED OPERATING CONDITIONS
Rating

Pin

Symbol

Value

Unit

4

VCC

2.0 to 9.0
2.4 to 9.0

Vdc

RF Input Voltage

16

Vrf

0.0005 to 10

mVrms

RF Input Frequency

16

frf

0.1 to 100

MHz

Oscillator Input Voltage

1

Vlocal

80 to 400

mVrms

Supply Voltage

(@TA = 25·C)
(-30·C .. TA" +75·C)

Intermediate Frequency

-

fif

455

kHz

Limiter Amp Input Voltage

5

Vif

o to 400

mVrms

Filter Amp Input Voltage

10

Vfa

0.1 to 300

mVrms

Squelch Input Voltage

12

Vso

o or 2

Vdc

MC3371D

SO-16

Mute Sink Current

14

Isa

0.1 to 30

mA

Plastic DIP

Ambient Temperature Range

-

MC3371P

TA

-30 to +70

·C

MC3372D

..

ThiS document contains information on a new product. SpeCifications and information herein are

subject to change without notice.

MC3371.MC3372
2-78

ORDERING INFORMATION
Device

MC3372P

Temperature
Range

- 30· to + 70·C

Package

SO-16
Plastic DIP

MOTOROLA COMMUNICATIONS DEVICE DATA

AC ELECTRICAL CHARACTERISTICS (VCC ~ 4.0 Vdc, fo ~ 5B.1125 MHz, df ~ ±3.0 kHz, fmod ~ 1.0 kHz, 50 n source, flocal
~ 57.6575 MHz, Vlocal ~ 0 dBm, TA ~ 25'C unless otherwise noted)
Characteristic

Pin

Input for 12 dB SINAD
Matched Input - (See Figures 10, 11 & 12)
Unmatched Input - (See Figures 7A & 7B)

-

Input for 20 dB NOS

-

Recovered Audio Output Voltage
Vrf ~ -30 dBm

Symbol

Meter Drive Output Voltage (No Modulation)
Vrf ~ -100 dBm
Vrf ~ -70 dBm
Vrf ~ -40 dBm

13

Filter Amp Gain
Rs ~ 600 n, fs

-

AV(Amp)

Mixer Conversion Gain
Vrf ~ -40 dBm, RL ~ 1.B kn

-

AV(Mix)

Signal to Noise Ratio
Vrf ~ -30 dBm

-

sin

Total Harmonic Distortion
Vrf ~ -30 dBm, BW ~ 400 Hz to 30 kHz

-

~

1.0 mVrms

Typ

Max

1.0
5.0

-

3.5

-

120

200

320

-B.O

-1.5

-

-

1.1
2.0

0.3
1.5
2.5

0.5
1.9
3.1

47

50

-

14

20

-

36

67

-

-

0.6

3.4

-

450

-

MDrv
MV1
MV2
MV3

THO

9

Zo

Detector Output Voltage (No Modulation)
Vrf ~ -30 dBm

9

DVO

Meter Drive
Vrf ~ -100 to -40 dBm

13

MO

Meter Drive Dynamic Range
RFln
IFln (455 kHz)

13

Mixer Third Order Input Intercept Point
f1 ~ 58.125 MHz
f2 ~ 58.1375 MHz

-

Mixer Input Resistance

16

Rin

Mixer Input Capacitance

16

Cin

p.Vrms
mVrms

AFloss

Detector Output Impedance

Unit
p.Vrms

15

AFO

-

10 kHz, Vfa

-

-

VNOS

Recovered Audio Drop Voltage Loss
Vrf ~ -30 dBm, VCC ~ 4.0 V to 2.0 V

~

Min

VSIN

dB
Vdc

dB
dB
dB

%
n
Vdc

-

1.45

-

-

O.B

-

-

60
BO

-

p.AldB

MVD

dB

dBm

ITOMix

-

-22

-

-

3.3

-

kn

2.2

Min

Typ

Max

Unit

-

3.2
3.6
1.0

4.2
4.8
2.0

0.9

1.6

2.3

1.5
2.0

2.5
5.0

3.5
8.0

34

57

80

pF

DC ELECTRICAL CHARACTERISTICS (VCC ~ 40 Vdc TA ~ 25'C, unless otherwise noted)
Characteristic

Pin

Drain Current (No Input Signal)
Squelch Off, Vsq ~ 2.0 Vdc
Squelch On, Vsq ~ 0 Vdc
Squelch Off, VCC ~ 2.0 to 9.0 V

4

Detector Output (No Input Signal)
DC Voltage, VB ~ VCC

9

Filter Output (No Input Signal)
DC Voltage
Voltage Change, VCC ~ 2.0 to 9.0 V

11

Trigger Hysteresis

-

MOTOROLA COMMUNICATIONS DEVICE DATA

Symbol

mA
Icc1
Icc2
dlcc1

-

Vdc

V9

Vdc
V11
dV"
Hys

mV

MC3371.MC3372
2-79

TYPICAL CURVES (UNMATCHED INPUT)

FIGURE 1 -

5.0

°c~

0

II
Vee = 4.0 Vdc

~
z
~ 4.0

TA~

0

RF Input = - 30 dBm I - fo = 10.7 MHz

~

3.0

!,,!

0

2.0

'li 1\

.....
~

f2 1.0
C

0
-55

/'

.--

~

-35

-15

85

105

0
-140 -120

125

-100

0
30dBm

54

"--1

48

6
70dBm

4

-I---

~-20
:2

1/

0-40

-60 -40
RF INPUT (dBm)

/

~-5 0

2

-60

/

110dBm

0
-55

-35

-15

FIGURE 5 -

5.0
25
45
65
TA. AMBIENT TEMPERATURE ('e)

TAI=

7
4

I

1
)11

8
15
2

105

125

-70

-ro

TA

3O'e

+7~'e- 1:::=

I--~A

-60

-60

FIGURE 6 -

MIXER GAIN versus SUPPLY VOLTAGE

30

1

85

~

~MHZ

~

6. 0

-40

/

MC3371.MC3372
2-80

8.0

Vee = 4.0 Vdc _
T1 = 27'C
1

-30
-w
RF INPUT (dBm)

-W

10

MIXER GAIN versus FREQUENCY

v1J IT

0

3.0 4.0
5.0
6.0 7.0
Vee. SUPPLY VOLTAGE (V)

-

40

0

3.0
2.0

_

3rd Order Products

Vcr = '4.0'
TA = +27'C
RFin = -40 dBm

30

fo = 10.7 MHz- r-RFin -4OdBm
1.8fnLoad - f - -

1.0

-

/

-10dB~
-15dii:;;

6. 0

20

\ + 25'e

.~

9.0

-20

/'"

.I

a:

8

0

- -30'C

V

~-30

0

-80

I
100lMHZ
Desired pro

-1 0

Vee = 4.0Vdc_
fo = 10.7 MHz

2

~

-30'e-

MIXER OUTPUT versus RF INPUT

FIGURE 4 -

RSSI OUTPUT versus TEMPERATURE

60

5

T~

Vee = 4.0 Vdc _
fo ,10.7 M~Z

I

i .s: ~TA

OTA=+75'e

5.0
25
45
65
TA. AMBIENT TEMPERATURE ('e)

FIGURE 3 -

13o

lO

1/

0

\/

F

1

+wk.

TA - +25'e~ IV

z
o

~

RSSI versus RF INPUT

FIGURE 2 -

TOTAL HARMONIC DISTORTION
versus TEMPERATURE

9.0

10

0
1.0

-20 dB:;;-

r\

1\\
[\\' 5.0 dBm
r\\
f\\

10
100
f. FREOUENCY (MHz)-

oJ~

-5.0dBm

woo

MOTOROLA COMMUNICATIONS DEVICE DATA

FIGURE 7A -

MC3371 FUNCTIONAL BLOCK DIAGRAM AND TEST FIXTURE SCHEMATIC

RSSIOutput

RF Input

VCC

=

4.0Vdc

Filter In
0.1

51 k
Cl
0.01

SQln

11

Filter Out

51
11

15

O.01

510 k

Mute
16

470

13

8.2 k

J

AFOut
to Audio
Power Amp

12

51 k

53 k

7

0.1

r-----,I Quad Coil TOKO

0.1

I

20 k

I

+
I 2A6597 HK 110 mml
I or

IL ___ ...JI 7MC·8128Z 17 mml

muRata
CFU455D2
or
equivalent

MOTOROLA COMMUNICATIONS DEVICE DATA

Units:
R:fl,C: IJ.F
Unless otherwise noted,
capacitors marked "sm"
are silver mica.

MC3371.MC3372
2-81

FIGURE 7B -

MC3372 FUNCTIONAL BLOCK DIAGRAM AND TEST FIXTURE SCHEMATIC

ASSIOutput

AF Input

VCC

= 4,0 Vdc

Filter In
0,1

51 k
C1
0,01

SO In

51

11

15

470

O.D1

510 k

Mute

16

11

Filter Out

13

8,2 k

J

AFOut
to Audio
Power Amp

12

51 k

53k

C14
27p

o

A12
4,3 k

Ceramic
Resonator

muAata
CDB455C16
muAata
CFU455D2
or
equivalent

MC3371.MC3372
2·82

I

C15
0,1

Units:

A: n, C: JLF
Unless otherwise noted,
capacitors marked "sm"
are silver mica.

MOTOROLA COMMUNICATIONS DEVICE DATA

PIN DESCRIPTION
OPERATING CONDITIONS VCC
(see

= 4.0 Vdc, RFln = 100 JLV, fmod = 1.0 kHz, fdev = 3.0 kHz.

MC3371 at fRF

=

10.7 MHz

re 10).
Internal Equivalent
Circuit
The base of the Colpitts oscillator. Use
a high impedance and low capacitance
probe or a "sniffer" to view the waveform without altering the frequency.
Typical level is 450 mVp-p.

OSCI

Vcc

15 k
OSC1 .....~,.....Nv-

2

OSC2

3

MXOut

The emitter of the Colpitts oscillator.
Typical signal level is 200 mVp-p. Note
that the signal is somewhat distorted
compared to that on pin 1.

05C2

Output of the Mixer. Riding on the
455 kHz is the RF carrier component.
The typical level is approximately
60mVp-p.
MixerOut

4

VCC

Supply Voltage - 2.0 to 9.0 Vdc is the
operating range. VCC is decoupled to
ground.

5

IFln

Input to the IF amplifier after passing
through the 455 kHz ceramic filter. The
signal is attenuated by the filter. The
typical level is approximately
50 mVp-p.
IFln

DECI
DEC2
6
7

DECI
DEC2

MOTOROLA COMMUNICATIONS DEVICE DATA

IF Decoupling. External 0.1 JLF capacitors connected to VCC.

MC3371.MC3372

2-83

PIN DESCRIPTION
OPERATING CONDITIONS VCC
(see

=

4.0 Vdc, RFln

100 ,.,V, fmod

=

1.0 kHz, fdev

=

3.0 kHz. MC3371 at fRF

=

10.7 MHz

10).

Pin

Symbol

8

Quad
Coil

Internal Equivalent
Circuit

Quad Coil

VCC

9

=

Description

Waveform

Quadrature Tuning Coil. Composite
(not yet demodulated) 455 kHz IF
signal is present. The typical level is
500 mVp-p.

Recovered Audio. This is a composite
FM demodulated output having signal
and carrier component. The typical
level is 1.4 Vp-p.

RA

Vcc

RAOut

10

Filln

11

FilOut

The filtered recovered audio has the
carrier component removed and is
typically 800 mVp-p.

Filter Amplifier Input

Filter Amplifier Output. The typical
signal level is 400 mVp-p.

VCC240"'A

~

FilterOut

11

MC3371.MC3372

2·84

MOTOROLA COMMUNICATIONS DEVICE DATA

PIN DESCRIPTION
OPERATING CONDITIONS VCC = 4.0 Vdc, RFln = 100 /LV, fmod = 1.0 kHz, fdev = 3.0 kHz. MC3371 at fRF = 10.7 MHz
(see
Pin

ure 10).
Symbol

Internal Equivalent
Circuit

Description
Squelch Input. See discussion in
application text.

13

RSSI

RSSI Output. Referred to as the
Received Signal Strength Indicator or
.ASSI. The chip sources up to 60 /LA
over the linear 60 dB range. This pin
may be used many ways, such as:
AGe, meter drive and carrier triggered
squelch circuit.

Vee

Bias

~
13

14

RSSIOut

Mute Output. See discussion in
application text.

MUTE

K"'",::'

40 k

':"

15

":'

GND

GND

~

16

Ground. The ground area should be
continuous and unbroken. In a twosided layout, the component side has
the ground plane. In a one-sided layout, the ground plane fills around the
traces on the circuit side of the board
and is not interrupted.

15
~

MIXln

Vee

Mixerl"

~
3.3 k

Mixer InputSeries Input Impedance:
(C, 10 MHz: 309 -j33 n

«,

45 MHz: 200 - j13

n

10 k

MOTOROLA COMMUNICATIONS DEVICE DATA

MC3371oMC3372

2·85

PIN DESCRIPTION
OPERATING CONDITIONS VCC

=

4.0 Vdc, RFln

=

100 }1V, fmod

=

1.0 kHz, fdev

=

3.0 kHz. MC3372 at fRF

=

45 MHz

(see Figure 121.
Pin

Symbol

Internal Equivalent
Circuit

6

Description

IF Amplifierlnpu!

5

DECl

IFln~
6

53 k

DEC

IF Decoupling. External 0.1 }1F capacitors connected to Vcc.

60 }1A

7

IFOut

vee

~

IF Amplifier Output Signal level is
typically 300 mVp-p.

7IFOU!

50 }1A

~

8

120l'A

Quadrature Detector Input. Signal
level is typically 150 mVp-p.

Quadl n

~
8

Quadln

Vee

50l'A

9

RA

Recovered Audio. This is a composite

FM demodulated output having signal
and carrier components. Typical level
is 800 mVp-p.

Vee

RAOU!

The filtered recovered audio has the
carrier signal removed and is typically
500 mVp-p.

"Other pins are the same as pins in MC3371.

MC3371.MC3372
2-86

MOTOROLA COMMUNICATIONS DEVICE DATA

FIGURE 8 -

MC3371 CIRCUIT SCHEMATIC

Vee

oSe1 ......-~N\r~
ose2

r-

~

15
GND

RAOut

FIGURE 9 -

MC3372 CIRCUIT SCHEMATIC

Mixer Out
3

Vee

ose1 ......-~N\r'"'
ose2

r-

~

15
GND

RAOut
6

53 k

DEe+-----~~--------~~----------------~~~--~

7

IFOut+---~r---------------------------------~~r----±~

MOTOROLA COMMUNICATIONS DEVICE DATA

MC3371.MC3372
2-87

CIRCUIT DESCRIPTION
The MC3371 and MC3372 are low power narrowband
FM receivers with an operating frequency of up to
60 MHz. Its low voltage design provides low power drain,
excellent sensitivity, and good image rejection in narrowband voice and data link applications.
This part combines a mixer, an IF (intermediate frequency) limiter with a logarithmic response signal
strength indicator, a quadrature detector,.an active filter
and a squelch trigger circuit. In a typical application, the
mixer amplifier converts an RF input signal to a 455 kHz
IF signal. Passing through an external bandpass filter, the
IF signal is fed into a limiting amplifier and detection
circuit where the audio signal is recovered. A conventional quadrature detector is used.
The absence of an input signal is indicated by the presence of noise above the desired audio frequencies. This
"noise band" is monitored by an active filter and a detector. A squelch switch is used to mute the audio when
noise or a tone is present. The input signal level is monitored by a meter drive circuit which detects the amount
of IF signal in the limiting amplifier.

APPLICATION
The oscillator is an internally biased Colpitts type with
the collector, base, and emitter connections at Pins 4, 1
and 2 respectively. This oscillator can be run under crystal
control. For fundamental mode crystals use crystal characterized parallel resonant for 32 pF load. For higher frequencies, use 3rd overtone series mode type crystals.
The coil (L2) and resistor RD (R13) are needed to ensure
proper and stable operation at the LO frequency (see
Figure 12,45 MHz application circuit).
The mixer is doubly balanced to reduce spurious radiation. Conversion gain stated in the AC Electrical Characteristics table is typically 20 dB. This power gain measurement was made under stable conditions using a 50!l
source at the input and an external load provided by a
455 kHz ceramic filter at the mixer output which is connected to the VCC (Pin 4) and IF input (Pin 5). The filter
impedance closely matches the 1.8 k!l internal load resistance at Pin 3 (mixer output). Since the input impedance
at Pin 16 is strongly influenced by a 3.3 k!l internal biasing
resistor and has a low capacitance, the useful gain is
actually much higher than shown by the standard power
gain measurement. The Smith Chart plot in Figure 16
shows the measured mixer input impedance versus input
frequency with the mixer input matched to a 50!l source
impedance at the given frequencies. In order to assure
stable operation under matched conditions, it is necessary to provide a shunt resistor to ground. Figures 10, 11
and 12 show the input networks used to derive the mixer
input impedance data.
Following the mixer, a ceramic bandpass filter is recommended for IF filtering (i.e. 455 kHz types having a
bandwidth of ± 2.0 kHz· to ± 15 kHz with an input and
output impedance from 1.5 k!l to 2.0 kill. The 6 stage
limiting IF amplifier has approximately 92 dB of gain. The
MC3371 and MC3372 are different in the limiter and quadrature detector circuits. The MC3371 has a 1.8 k!l and a
51 k!l resistor providing internal DC biasing and the out-

MC3371oMC3372

2-88

put of the limiter is internally connected, both directly
and through a 10 pF capacitor to the quadrature detector;
whereas, in the MC3372 these components are not provided internally. Thus, in the MC3371, no external components are necessary to match the 455 kHz ceramicfilter,
while in the MC3372, external 1.8 k!l and 51 k!l biasing
resistors are needed between Pins 5 and 7, respectively
(see Figures 11 and 12).
In the MC3371, a parallel LCR quadrature tank circuit
is connected externally from Pin 8 to VCC (similar to the
MC3361). In the MC3372, a quadrature capacitor is
needed externally from Pin 7 to Pin 8 and a parallel LC
or a ceramic discriminator with a damping resistor is also
needed from Pin 8 to VCC (similar to the MC3357). The
above external quadrature circuitry provides 90° phase
shift at the IF center frequency and enables recovered
audio.
The damping resistor determines the peak separation
of the detector and is somewhat critical. As the resistor
is decreased, the separation and the bandwidth is
increased but the recovered audio is decreased. Receiver
sensitivity is dependent on the value of this resistor and
the bandwidth of the 455 kHz ceramic filter.
On the chip the composite recovered audio, consisting
of carrier component and modulating signal, is passed
through a low pass filter amplifier to reduce the carrier
component and then is fed to Pin 9 which has an output
impedance of 450 !l. The signal still requires further filtering to eliminate the carrier component, deemphasis,
volume control, and further amplification before driving
a loudspeaker. The relative level of the composite
recovered audio signal at Pin 9 should be considered for
proper interaction with an audio post amplifier and a
given load element. The MC13060 is recommended as a
low power audio amplifier.
The meter output indicates the strength of the IF level
and the output current is proportional to the logarithm
of the IF input signal amplitude. A maximum source current of 60 /LA is available and can be used to drive a
meter and to detect a carrier presence. This is referred
to as a Received Strength Signal Indicator (RSSI). The
output at Pin 13 provides a current source. Thus, a resistor to ground yields a voltage proportional to the input
carrier signal level. The value of this resistor is estimated
by (VCC(Vdc) - 1.0 V)/60 /LA; so for VCC = 4.0 Vdc, the
resistor is approximately 50 k!l and provides a maximum
voltage swing of about 3.0 V.
A simple inverting op amp has an output at Pin 11 and
the inverting input at Pin 10. The noninverting input is
connected to 2.5 V. The op amp may be used as a noise
triggered squelch or as an active noise filter. The bandpass filter is designed with external impedance elements
to discriminate between frequencies. With an external
AM detector, the filtered audio signal is checked for a
tone signal or for the presence of noise above the normal
audio band. This information is applied to Pin 12.
An external positive bias to Pin 12 sets up the squelch
trigger circuit such that the audio mute (Pin 14) is open
or connected to ground. If Pin 12 is pulled down to 0.9 V
or below by the noise ortone detector, Pin 14 is internally
shorted to ground. There is about 57 mV of hyteresis at
Pin 12 to prevent jitter. Audio muting is accomplished by
connecting Pin 14 to the appropriate point in the audio

MOTOROLA COMMUNICATIONS DEVICE DATA

path between Pin 9 and an audio amplifier. The voltage
at Pin 14 should not be lower than -0.7 V; this can be
assured by connecting Pin 14 to the point that has no dc
component.
Another possible application of the squelch switch may
be as a carrier level triggered squelch circuit, similar to

FIGURE 10 -

VCC = 4.0 Vdc

the MC3362/MC3363 FM receivers. In this case the meter
output can be used directly to trigger the squelch switch
when the RF input at the input frequency falls below the
desired level. The level at which this occurs is determined
by the resistor placed between the meter drive output
(Pin 13) and ground (Pin 15).

TYPICAL APPLICATION FOR MC3371 AT 10.7 MHz

RSSIOutput
R2
10 k

1st IF 10.7 MHz
from Input
Front End

Units:
R: n,C:/lF
Unless otherwise noted
capacitors marked "sm"
are silver mica.

R3

100 k

C15Y
91p

It:

~r-+!'::";-:::;''''

Rll
560

L

L1
TKANS9443HM
.J 6.B /lH ± 6%

+-__",R5_ _~ VRl ISquelch Controll
4.7k R6

10 k

560
RB

Cl
0.Q1

~t--

16

muRata
CFU455D2
or
equivalent

MOTOROLA COMMUNICATIONS DEVICE DATA

AF Out
__-o to Audio
Power Amp

C14

~0.1

MC3371.MC3372

2-89

FIGURE 11 -

Vcc

= 4.0Vdc

TYPICAL APPLICATION FOR MC3372 AT 10.7 MHz

RSSIOutput
R2
10 k
.. Units:

+ C9

1st IF 10.7 MHz
from Input
Front End

R: fl,C: p.F

R3
100 k

Unless otherwise noted
capacitors marked "sm"
are silver mica.

Jl0
C16Y
91p

t:

~~~:":-="-'L1

R13

~

560

L

TKANS9443HM
.J 6.B p.H ± 6%

....._ _"R5_ _~VRl (Squelch Cantrall
4.7k R6

10 k

560
RB

Cl
0.01

3.3 k
AFOut
~I--+--oto Audio

16

Power Amp

C14
27p
muRata
CFU455D2
or
equivalent

\

R12
4.3 k

muRata

CJ CDB455C16

C15

~0.1

\

MC3371oMC3372

2-90

MOTOROLA COMMUNICATIONS DEVICJ; DATA

FIGURE 12 -

TYPICAL APPLICATION FOR MC3372 AT 45 MHz

RSSIOutput
to Meter ITriplett -100 kVI

Vcc = 4.0 Vdc

R2
12 k
Units:
~

~~~~

100 k

Unless otherwise noted
capacitors marked "sm"
are silver mica .

...-_ _"RI/'5..---IO.~ VRI ISquelch Controll
4.7 k R6
10 k
560
RS
3.3 k

~I-----o

Af Out
to Audio
Power Amp

C14
27p
R12 0
4.3 k

muRata
CDB455C16

C15

muRata
CfU45502
or

:;P·l

equivalent

FIGURE 13 -

RSSI OUTPUT versus RF INPUT

FIGURE 14 -

3.5
3.0
2.5
t-

~

~

o

L

2.0

u

L

L

U)

/'

o. 5
o

-120

t-

::>

o 1. 5

~

fRf = 10.7 MHz
VCC = 4.0 Vdc
Reference figure 10 -

1.0

/'

-so

-60
Rf INPUT IdBml

I

-40

MOTOROLA COMMUNICATIONS DEVICE DATA

-20

/"

I. 0

o. 5

-.l
-100

L
/'

~ 2.0

./

1.5

/'

2. 5

~

,/

in

c::

3.0

r--

L

~

RSSI OUTPUT versus RF INPUT

3.5

0 ~
-120

V

/

r--fRf = 45 MHz
VCC = 4.0 Vdc
t-Reference figure 12 t - -

/'
-100

-80
-60
Rf INPUT IdBml

-40

-20

MC3371.MC3372
2-91

FIGURE 15 -

S + N. N. AMR versus INPUT

0
0

S+N
..-<

'- \.\.

S-l 0
::<:.
~-2 0

..

2
2- 30

"\."'-""-

+

til

fRF = 10.7 MHzVCC = 4.0 V TA = 25°C
-

'-I\.
I\..\.

-40

S+N 30% AM

I\.

"- ..........

-50
-60
-130

-110

-90

N

-70
-50
RF INPUT IdBml

-30

-10

'REFERENCE FIGURES 10, 11 & 12

FIGURE 16 -

MIXER INPUT IMPEDANCE versus FREQUENCY

+j50

-j50

MC3371.MC3372

2·92

MOTOROLA COMMUNICATIONS DEVICE DATA

FIGURE 17 -

MC3371P PC BOARD COMPONENT VIEW WITH MATCHED INPUT AT 10.7 MHz

COMPONENT SIDE
~

VCC GND

~ DDQ+

~~~D20 C11

J:3 Dvcc
(140 Cl:3(12

AF OUT

T2D~

©
O o

Rlfil
OVR2

m
~-=~~MHZ
Clfil

MC:3:371

16
15

INPUT IF
lfil.7 MHZ

8

©
0
..:

~1 ~ a2~Q
MC3371 ?o~ DJ4~CUT
~R5 ~ n n ~
• .:

J2

IF lfil.7 MHZ
FRONT END

VRl ~ V

..£.,

J

FIGURE 18 -

VR4 c)7 VRl

ETER
OUT

..£..
cc

MC3371P PC BOARD CIRCUIT OR SOLDER SIDE AS VIEWED THRU COMPONENT SIDE

Above PC Board is laid out for the circuit in Figure 10.

MOTOROLA COMMUNICATIONS DEVICE DATA

MC3371.MC3372
2-93

FIGURE 19 -

MC3372P PC BOARD COMPONENT VIEW WITH MATCHED INPUT AT 10.7 MHz

COMPONENT SIDE
~

cg+

VCCGNO

~

0

Om
~~:C)D ~ n~C)Ofl12 ]~'
~

J3 VCC

1:~~nuY yl ~

A©F
OUT

O

D

J2 '64 12
R2

o

BNC

MC3372
IF 10.7MHZ
FRONT ENO

MC3372
R9 C2

Y

g

RS

VRI

10©.7
MHZ

0

D

+40~ru

~
J

FIGURE 20 -

7
C16

~8~ n n L2~
'-" t7 5 f:YJ ~R13
R"lY

INPUT If

~H~4SJl

0

BNC

Ll

n.. nDJ4~
n ~
rio

~

t6 yRI

METER
OUT

cc

MC3372P PC BOARD CIRCUIT OR SOLDER SIDE AS VIEWED THRU COMPONENT SIDE

Above PC Board is laid out for the circuit in Figure 11.

MC3371.MC3372
2-94

MOTOROLA COMMUNICATIONS DEVICE DATA

MOTOROLA

-

SEMICONDUCTOR
TECHNICAL DATA

MC34C86
Product Preview

Quad EIA·422·A Line Receiver

PSU~

CMOS
The MC34C86 is a quad differential line receiver designed for digital data
transmission over balanced lines. The MC34C86 meets all the requirements of
standard EIA-422-A while retaining the low-power characteristics of CMOS.
The MC34C86 has an input sensitivity of 200 mVoverthe common mode input
voltage range of ± 7 V. In addition, each receiver chain has internal hysteresis
circuitry to improve noise margin and discourage output instability for slowly
changing input waveforms.
The MC34C86 is pin compatible with the MC3486.
All pins are protected against damage due to electrostatic discharges.
•
•
•
•
•
•
•
•

Typical Power Supply Current: 6 mA
2000-V ESD Protection on the Inputs and Outputs
Typical Propagation Delay: 18 ns
Typical Input Hysteresis: 75 mV
Meets the Requirements of Standard EIA-422-A
Operation from Single 5-V Supply
High-Impedance Mode for Outputs Connected to System Buses
TTUCMOS Compatible Outputs

_

PLASTIC PACKAGE
CASE 648

o SUFFIX
SOGPACKAGE
CASE 751B
ORDERING INFORMATION
MC34C86P
MC34C86D

Plastic OIP
SOG Package

BLOCK DIAGRAM

ClO
CONTROL

INPUT INPUT
02
01

11
OUTPUT

o

INPUT INPUT
C2
Cl

5

OUTPUT
C

INPUT INPUT
B2
Bl

13

OUTPUT
B

INPUT INPUT
PJB
A2
AI
CONTROL

3
OUTPUT
A

This document contains infonnatlon on a new product under development. Motorola reserves the right to change or discontinue this product without notice.

REV. 3

MOTOROLA COMMUNICATIONS DEVICE DATA

MC34C86
2-95

TRUTH TABLE
Control Input

Input

Output

L

X

Z

H

VID " VTH (Max)

1

H

VID ,; VTH (Min)

0

Open

1

H
X = Don't Care
Z = High Impedance

H = High Logic State
L = Low Logic State

MAXIMUM RATINGS
Rating
Power Supply Voltage

Symbol

Value

Unit

VCC

7

V

VI

±12

V

VID

±14

V

Input Voltage
Input Differential Voltage
Enable Control Input Voltage

Yin

VCC+0.5

V

Storage Temperature

Tstg

-65 to +150

°c

±25

rnA

2000

V

Maximum Current per Output

10

ESD (Human Body model)

OPERATING CONDITIONS
Rating
Power Supply Voltage

Symbol

Min

Max
5.5

V

+85

°c

500

ns

VCC

4.5

Operating Temperature Range

TA

-40

Input Rise and Fall Time

t r, tf

-

Unit

DC CHARACTERISTICS (VCC = 4.5 to 5.5 V, TA = -40 to + 85°C, unless otherwise stated) (See Note 1)
Parameter

Typ

Max

Unit

ICC

-

6

12

rnA

IL

-

-

± 1.0

IlA

Symbol

Power Supply Current, VCC = Max
Enable Input Current, Yin = VCC or GND

Min

Input Voltage -

Low Logic State (Enable Control)

VIL

-

-

0.8

V

Input Voltage -

High Logic State (Enable Control)

VIH

2

-

-

V

VTH

0.2

-

-

V

Differential Input Voltage, - 7 V < VLCM < 7 V

Vout=VOH
Vout = VOL

Input Hysteresis, VLCM = 0 V
Comparator Input Current

Vhys
Yin = + 10 V, Other Input = GND
Yin = -10 V, Other Input = GND

lin

-

-

-0.2

75

-

mV

1.4
-2.5

-

rnA

-

kQ

-

Comparator Input Resistance, -12 V < VLCM < + 12 V

Rin

4

4.8

Output Voltage (Low Logic State) VID = - 1 V, lout = 6 mA (Note 2)

VOL

-

0.13

Output Voltage (High Logic State) VID = + 1 V, lout = - 6 mA (Note 2)

VOH

3.8

4.8

-

V

10Z

-5

-

5

IlA

Output Leakage Current (High Logic State) Vout = VCC or GND

0.33

V

NOTES:
1. All currents into device pins are shown as positive, out of device pins are negative. All voltages referenced to ground unless otherwise noted.
2. See EIA specifications EIA-422-A for exact test conditions.

MC34C86

2-96

MOTOROLA COMMUNICATIONS DEVICE DATA

AC CHARACTERISTICS (VCC = 4.5 to 5.5 V. TA = - 40 to + 85°C. unless otherwise stated)
Symbol

Parameter
Propagation Delay Input to OUlput. CL = 50 pF. VDIFF = 2.5 V

tPLH
tPHL

Skew = IpHL - tpLH

Skew

I

Propagation Delay Enable to Output
CL =50 pF. RL =1000 n. VDIFF = 2.5 V

tpLZ
tpHZ

Propagation Delay Enable to Output
CL =50 pF. RL =1000 n. VDIFF =2.5 V

tpZL
tpZH

Min

Typ

Max

Unit

-

18

30

ns

-

1

-

ns

12

-

14

-

ns

ns

AC TEST CIRCUIT AND SWITCHING TIME WAVEFORMS
TEST
POINT

VCC

-.>t-.....-o-'~~

OUTPUT--.---.....

Sl

RL=2kn

+2.SV
INPUT
-2.SV

OV

.

-+'

:-tPLH

tPHL-:

1.3 V

OUTPUT

S2~

:1.3 V

Sl AND S2 CLOSED

Figure 1. Test Circuit

Figure 2. Propagation Delays

3V-r----------------~

ENABLE INPUT •

oV

~ 1.3 V

\ .1.3 V

..../:

'-------

--.: :..- tpZH
tPHZ~:
• ·r--S~l~O~P=.EN~--~S~l~C~LO~S~E~D~·
OUTPUT A
SO% S2 CLOSED
S2 CLOSED •
:--: tpZL

so"!. Sl CLOSED
° S20PEN

OUTPUTB

tpLZ:--'
•

Sl CLOSED
S2CLOSED

I

VOH

I

Figure 3. Enable and Disable Times

TYPICAL APPLICATIONS

ENAa£~

/

~""

DATA~,-._____________~OUTPUT
Figure 4. Two-Wire Balanced Systems (EIA-422-A)

MOTOROLA COMMUNICATIONS DEVICE DATA

MC34C86

2-97

MOTOROLA

-

SEMICONDUCTOR
TECHNICAL DATA

MC34C87
Product Preview

Quad EIA·422·A Line Driver

"U~

CMOS
The MC34C87 is a quad differential line driver designed for digital data
transmission over balanced lines. The MC34C87 meets all the requirements of
standard EIA-422-A while retaining the low-power characteristics of CMOS.
The MC34C87 accepts TTL or CMOS input levels and translates these to
EIA-422-A output level. This part uses special output circuitry that enables the
individual drivers to power down without loading down the bus. The MC34C87 also
includes special circuitry which will set the outputs to a high impedance mode
during power up or down, preventing spurious glitches. Each enable pin controls
2 drivers.
The MC34C87 is pin compatible with the MC3487.
All pins are protected against damage due to electrostatic discharges.
•
•
•
•
•
•
•
•

Maximum Power Supply Current: 3 mA
2000-V ESD Protection on the Inputs and the Outputs
TTUCMOS Input Compatible
Typical Propagation Delay: 6 ns
Typical Output Skew: 1 ns
Meets Vo 6.0 V (and Vo
0.25 V), VCC 0 V, 10 < 100 itA Requirement
Operation from Single 5-V Supply
High-Impedance Mode for Outputs Connected to System Buses

=

=-

_

PLASTIC PACKAGE
CASE 648

o SUFFIX
SOGPACKAGE
CASE 751B
ORDERING INFORMATION
MC34C87P
MC34C87D

Plastic DIP
SOG Package

=

BLOCK DIAGRAM
C/O

CONTROL

!S

GNO

INPUT 0

INPUTC

INPUTB

INPUT A

11

OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT
02
01
C2
Cl
B2
Bl
A2
AI

This document contains Infonnatlon on a new product under development. Motorola reserves the right to change or discontinue this product without notice.

REV. 3

MC34C87

2-98

MOTOROLA COMMUNICATIONS DEVICE DATA

TRUTH TABLE
Control Input

Input

Non-Inverting
Output

Inverting
Output
Z

L

X

Z

H

H

H

L

H

L

L

H

X = Don't Care
Z = High Impedance

H = High Logic State
L = Low Logic State

MAXIMUM RATINGS
Rating

Symbol

Value

V
V

VCC

7

DC Input Voltage

Vin

-1.5 to VCC + 1.5

DC Output Voltage'

Power Supply Voltage

Unit

Vout

- 0.5 to VCC + 0.5

V

DC Output Current, per Pin

lout

150

rnA

DC VCC or GND Current, per Pin

IDD

150

rnA

Tstg

-65 to +150

°c

PD

500

mW

2000

V

Storage Temperature
Power Dissipation
ESD (Human Body model)
• Power-on conditions.

OPERATING CONDITIONS
Rating
Power Supply Voltage
DC Input Voltage

Symbol

Min

Max

Unit

VCC

4.5

5.5

V

Yin

0

VCC

V

Operating Temperature Range

TA

-40

+ 85

°c

Input Rise and Fall1ime

tr, tf

-

500

ns

DC CHARACTERISTICS (VCC = 4.5 to 5.5 V, TA = - 40 to + 85°C, unless otherwise stated)
Symbol

Min

Typ

Max

Unit

Input Voltage (Low Logic State)

VIL

-

-

0.8

V

Input Voltage (High Logic State)

VIH

2.0

-

-

V

Output Voltage (Low Logic State) Isink = 20 rnA

VOL

-

0.3

0.5

V

Output Voltage (High Logic State) Isource = - 20 rnA

VOH

2.5

2.8

-

V

Output Differential Voltage RL = 100 n (Note 1)

VOD

2.0

-

-

V

D(VOD)

-

-

±OA

V

VOS

-

-

3.0

V

D(VOS)

-

-

±0.4

V

lin

-

-

± 1.0

JlA

Parameter

Output Differential Voltage Difference RL = 100 n (Note 1)
Output Offset Voltage RL = 100 n (Note 1)
Output Offset Voltage Difference RL = 100 n (Note 1)
Input Current Yin = Vcc, GND, VIH or VIL
Quiescent Supply Current lout = 0 JlA

ICC

-

-

3.0

rnA

Output Short Circuit Current (Note 2)

lOS

-30

-100

-150

rnA

Output Leakage Current (Hi-Z State) Vout = VCC or GND
Output Leakage Current (Power Off)

Vout= 6 V
Vout = - 0.25 V

10(Z)

-

-

±1.0

j.LA

loxh
loxl

-

-

100
-100

JlA

-

-

NOTES:
1. See EIA specifications EIA-422-A for exact test conditions.
2. Only one output may be shorted at a time.

MOTOROLA COMMUNICATIONS DEVICE DATA

MC34C87
2-99

AC CHARACTERISTICS (VCC = 4.5 \0 5.5 V, TA = - 40 \0 + a5·C, unless otherwise stated)
Symbol

Parameter
Propagation Delay Input to Output (Sl Open)

tpLH
tpHL

Output Skew (Sl Open)"

Skew

Differential Output
Rise lime
Fall lime (Sl Open)

trLH
trHL

Output Enable lime
(Sl Closed)

tpZH
tpZL

Output Disable lime
(Sl Closed)

tpHZ
tpLZ

Min

Typ

Max

Unit

-

6

12

ns

-

1.0

4

ns

-

4

a

ns

-

ns

-

16
15
6
9

ns

• Skew: difference in propagation delays between complementary outputs.

AC TEST CIRCUIT AND SWITCHING TIME WAVEFORMS
3V-,r-------------~

INPUT
OV

•_49",.9,.,.0'\r--o-~ o...--J

. If

4990

1.5 V

-VOH
OUTPUT A

, ,
, "

1.5V

1.5V

VOL

:~I ~SKBN

51

-,

49.90
OUTPUTB

,-tPHL
\

, 1.5V

lPLH - :

I
,F1.5V' VOH

....
, _ _ _ _ _ _ _ _ _ _ _ _...J '

-

VOL

Figure 6. Propagation Delays and Skew Waveforms

Figure 5. AC Test Circuit

3V-,
1.5 V

ENABLE INPUT
OV

1.5V

-:, ,:-tPLZ

tpZL-:

:-

3V- r-------------~
INPUT
OV

OUTPUT A

~:

:.- tpHZ

tpZH

--+-:

," VOH

OUTPUT B

VOH'- 0.5 V

2.0 V
-1.5V

Figure 7. Enable and Disable Times

OUTPUT
(DIFFERENTIAL)

90%
10% ' ,
- : :-'TLH

trHL-: : -

Figure 8. Differential Rise and Fall TImes

TYPICAL APPLICATIONS

-~~/

~""

DATA~,-,_____________~OUTPUT
Figure 9. Two-Wire Balanced Systems (EIA-422-A)

MC34C87

2-100

MOTOROLA COMMUNICATIONS DEVICE DATA

MOTOROLA

-

SEMICONDUCTOR
TECHNICAL DATA

MC3417, MC3517
MC3418, MC3518
Specifications and Applications
Information

CONTINUOUSLY VARIABLE
SLOPE DELTA
MODULATOR/DEMODU LATOR
LASER-TRIMMED
INTEGRATED CIRCUIT

CONTINUOUSLY VAR IABLE SLOPE
DELTA MODULATOR/DEMODULATOR
Providing a simplified approach to digital speech encoding/
decoding, the MC3517/18 series of CVSDs is designed for military
secure communication and commercial telephone applications.
A single IC provides both encoding and decoding functions.
•

Encode and Decode Functions on the Same Chip with
a Digital Input for Selection

•

Utilization of Compatible 12L - Linear Bipolar Technology

-LSUFFIX

PSUFFIX

CERAMIC PACKAGE
CASE 620

PLASTIC PACKAGE
CASE 648

DWSUFFIX

•

CMOS Compatible Digital Output

•

Digital Input Threshold Selectable (VCC/2 reference
provided on chip)

•

MC3417/MC3517 has a 3·Bit Algorithm (General
Communications)

•

MC3418/MC3518 has a 4·8it Algorithm (Commercial Telephone)

PLASTIC PACKAGE
CASE 751G
SO-16L

PIN CONNECTIONS

Analog
Input

(-)

16

VCC

Analog
Feedback

(+)

15

Decode

3

14

Clock

4

13

Digital Data
Input (-)

12

Digital
Threshold

Syllabic

Filter

CVSD BLOCK DIAGRAM

Gain
Control

Encode/
Decode

Ref
Input (+)

Clock

Analog Input 1
Analog Feedback 2

Filter
Input (-l

Digital
Data Input 13

Digital

~9~_ _ _-J~===::::;:::::j

__J

11

Analog

nIv:':----iff1-Tf-~~
Output

6

10

Output

f-_ _-I-'-II'" Co;nc;dence

Vee

9

8

Encode!

Coincidence

Output

VCC/2
Output
Digital

Output

Output
Syllabic

ORDERING INFORMATION

Gain Control

Analog

Ref

Filter

Output

Inpllt
(+)

Input
(-)

MOTOROLA COMMUNICATIONS DEVICE DATA

Device

Package

MC3417L
MC3418DW
MC3418L
MC3418P
MC3517L
MC3518L

Ceramic DIP
Plastic SOIC
Ceramic DIP
Plastic DIP
Ceramic DIP
Ceramic DIP

Temperature
Range

O·Cto
O·Cto
O·Cto
O·Cto
-55·Cto
-55·Cto

+70·C
+70·C
+70·C
+70·C
+125·C
+125·C

MC3417.MC3418.MC3517.MC3518
2-101

MAXIMUM RATINGS
(All voltages referenced to VEE, TA

= 25 0 C unless otherwise noted.)

Rating
Power Supply Voltage
Differential Analog Input Voltage
Digital Threshold Voltage

Logic Input Voltage
(Clock, Digital Data, Encode/Decode)
Coincidence Output Voltage
Syllabic Filter Input Voltage
Gain Control Input Voltage

Symbol

Value

Unit

VCC
VID
VTH

-0.4 to +18
±5.0

Vdc
Vdc
Vdc
Vdc

VLogic

-0.4 to VCC
-0.4 to +18

VOICon)
VI(Syl)

-0.4 to VCC

-0.4 to +18

-0.4 to VCC
VI(GC)
VI(Ael) VCC/2 - 1.0 to VCC
-25
IAef

Reference Input Voltage

VCC/2 Output Current

Vdc
Vdc
Vdc
Vdc
rnA

ELECTRICAL CHARACTERISTICS
(VCC

=

12V,VEE

=

Gnd, TA

= O°Cto

+ 70°C for MC3417/18, TA

=

-55°C to

+ 125°C for

MC3517/18 unless otherwise noted.)

MC3417/MC3517
Characteristic
Power Supply Voltage Range (Figure 1)
Power Supply Current (Figure 1)
(@ Idle Channel)
(VCC = 5.0 V, All except MC3418P,DW)
(VCC = 5.0 V, MC3418P,DW)
(VCC = 15 V, All except MC3418P,DW)
(VCC = 15 V, MC3418P,DW)
Gain Control Current Range (Figure 2)
Analog Comparator Input Range
(Pins 1 and 2)
(4.75 V .. VCC .. 16.5 V)
Analog Output Range (Pin 7)
(4.75 V .. VCC .. 16.5 V, 10

=

MC34181MC3518

Symbol

Min

Typ

Max

Min

Typ

Max

Unit

VCCR

4.75

12

16.5

4.75

12

16.5

Vdc
mA

ICC

-

,

3.7

5.0

6.0

10

-

-

-

-

-

-

0.002

-

3.0

0.002

mA

1.3

-

VCC-l.3

1.3

-

3.0

VI

VCC-l.3

Vdc

Va

1.3

-

VCC-l.3

1.3

-

VCC-l.3

Vdc

-

0.5
0.5
0.06
-0.06

1.5
1.5
0.5
-0.5

-

0.15

0.6

-

0.02

0.2

-

2.0

6.0

0.1
1.0

0.3
10

-

-

-

1.0
0.8
1.0
0.8

2.5
2.5
3.0
2.0

0.12

0.01

Input Bias Currents (Figure 3)
(Comparator in Active Region)
Analog Input (11)
Analog Feedback (12)
Syllabic Filter Input (13)
Reference Input (15)

liB

Input Offset Current
(Comparator in Active Region)
Analog Input/Analog Feedback
111-121- Figure 3
Integrator Amplifier
115-161- Figure 4

110

Input Offset Voltage
VII Converter (Pins 3 and 4) -

Via

J.LA

gm

tpLH
tpHL
tpLH
tpHL

-

-

0.25
0.25
0.06
-0.06

1.0
1.0
0.3
-0.3

0.05

0.4

0.01

0.1

2.0

6.0

0.3
10

-

-

J.LA

Figure 5

Propagation Delay Times (Note 1)
Clock Trigger to Digital Output
(CL = 25 pF to Gnd)
Clock Trigger to Coincidence Output
(CL = 25 pF to Gnd)
(RL = 4.0 kG to VCe)

5.0
5.5
10
11

IGCR

±5.0 mAl

Transconductance
VII Converter, 0 to 3.0 mA
Integrator Amplifier, 0 to ± 5.0 mA Load

3.7
3.7
6.0
6.0

Coincidence Output Voltage Low Logic State
(lOL(Con) = 3.0 mAl

VOL(Con)

-

Coincidence Output Leakage Current High Logic State
(VOH = 15 V, O°C .. TA" 70°C)

IOH(Con)

-

0.1
1.0

mV
mA/mV

J.Ls
1.0
O.B
1.0
0.8

2.5
2.5
3.0
2.0

0.25

-

0.12

0.25

Vdc

0.5

-

0.01

0.5

J.LA

NOTE 1. All propagation delay times measured 50% to 50% from the negative going (from VCC to +0.4 V) edge of the clock.

MC3417.MC3418.MC3517.MC3518
2-102

MOTOROLA COMMUNICATIONS DEVICE DATA

ELECTRICAL CHARACTERISTICS (continued)
MC3417/MC3517
Min

Typ

Max

Min

Applied Digital Threshold Voltage Range
(Pin 12)

VTH

+1.2

-

VCC-2.0

+1.2

Digital Threshold Input Current
(1.2 V .. Vth .. VCC - 2.0 V)
(VIL applied to Pins 13, 14 and 15)
(VIH applied to Pins 13, 14 and 15)

II(th)

Typ

-

Max

Unit

VCC-2.0

Vdc
/-LA

-10

5.0
-50

10

±5.0

-

-

±5.0

-10
-

VCC/2 Generator Maximum Output Current
(Source only)

IRef

+10

-

-

+10

-

-

VCC/2 Generator Output Impedance
(0 to +10 mAl

zRef

-

3.0

6.0

-

3.0

6.0

0

er

-

-

±3.5

-

-

±3.5

%

-

Vth- 0.4
lB

Gnd
Vth+ O.4

-

Vth- 0.4
lB

Maximum Integr,ator Amplifier
Output Current

-

-

VCC/2 Generator Tolerance
(4.75 V .. VCC .. 16.5 V)

Logic Input Voltage (Pins 13, 14 and 15)
Low Logic State
High Logic State

VIL
VIH

Dynamic Total Loop Offset Voltage
IVoffset
(Note 2) - Figures 3, 4 and 5
IGC = 12/-LA.VCC = 12V
TA = 25"C (All except 341BP,DW)
(MC341 BP,DW)
O"C .. TA" +70"C (MC3417/1BL)
(MC341BP,DW)
-55"C .. TA" +125"C (MC3517/1B)
IGC = 33/-LA.VCC = 12V
TA = 25"C
O"C .. TA" +70"C (MC3417/1B)
-55"C .. TA" + 125"C (MC3517/1B)
IGC = 12 /-LA. VCC = 5.0 V
TA = 25"C (All except MC3418P,DW)
(MC341 BP,DW)
O"C .. TA" +70"C (MC3417/18L)
(MC3418P,DW)
-55"C .. TA" + 125"C (MC3517/18)
IGC = 33 /-LA, VCC = 5.0 V
TA = 25"C
O"C .. TA" +70"C (MC3417/18)
-55"C .. TA" + 125"C (MC3517/18)
Digital Output Voltage
(lOL = 3.6 mAl
(lOH = - 0.35 mAl
I

MC34181MC3518

Symbol

Characteristic

Syllabic Filter Applied Voltage (Pin 3)
(Figure 2)
Integrating Current (Figure 2)
(lGC = 12/-LA)
(lGC = 1.5 mAl (All except 3418P,DW)
(MC3418P,DW)
(lGC = 3.0 mAl
Dynamic Integrating Current Match
(lGC = 1.5 mAl Figure 6
(All except MC3418P,DW)
(MC341BP,DW)
Input Current - High Logic State
(VIH = 18 V)
Digital Data Input

-

-

5.0
-50

-

mA
mA

Vdc

mV

-

-

-

-

-

-

±2.5
±3.0
±4.5

-

-

±4.0
±4.5
±5.5

-

-

-

-

±5.0
±7.5
±10

-

-

-

-

-

±6.0
±B.O
±10

-

0.4

-

±0.5
±0.5
±0.75
±0.75
±1.5

±1.0
±1.0
±1.3
±1.3
±2.5

-

-

±1.5
±3.0
±2.3
±3.B
±4.0

-

±2.0
±3.5
±2.B
±4.3
±5.0

Vdc

VOL
VOH
VI(Syl)
IIlntl

-

0.1
VCC-l.0 VCC-0.2

-

0.1
VCC-l.0 VCC-0.2

0.4

-

+3.2

-

VCC

+3.2

-

VCC

Vdc

8.0
1.45

10
1.5

12
1.55

2.75

3.0

3.25

B.O
1.45
1.42
2.75

10
1.5
1.5
3.0

12
1.55
1.58
3.25

/-LA
mA
mA
mA

±100

±250

±100
±100

±250
±280

-

-

-

mV

VO(Ave)

-

-

-

-

-

+5.0
+5.0
+5.0

-

-10
-360
-36

-

/-LA

IIH

Clockln~

Encode/Decode Input
Input Current - Low Logic State
(VIL = 0 V)
Digital Data Input
Clockln~ "
Encode/Decode Input
Clock Input, VIL = 0.4 V

Gnd
Vth + 0.4

-

-

-

-

-

-

-

-

-

+5.0
+5.0
+5.0

J.LA

IlL

-

-

-72

-

-

-

-10
-360
-36

-72

NOTE 2. Dynamic total loop offset (IVoffset) equals VIO (comparator) (Figure 3) minus VIOX (Figure 5). The input offset voltages of the analog comparator
and of the integrator amplifier include the effects of input offset current through the input resistors. The slope polarity switch current mismatch
appears as an average voltage across the 10 k integrator resistor. For the MC3417/MC3517, the clock frequency is 16 kHz. For the MC3418/
MC3518, the clock frequency is 32 kHz. Idle channel performance is guaranteed if this dynamic total loop offset is less than one-half of the
change in integrator output voltage during one clock cycle (ramp step size). Laser trimming is used to insure good idle channel performance.

MOTOROLA COMMUNICATIONS DEVICE DATA

MC3417.MC3418.MC3517.MC3518
2-103

DEFINITIONS AND FUNCTION OF PINS
Pin 1 - Analog Input
This is the analog comparator inverting input where
the voice signal is applied. It may be ac or dc coupled
depending on the application. If the voice signal is to
be level shifted to the internal reference voltage, then
a bias resistor between Pins 1 and 10 is used. The resistor is used to establish the reference as the new dc
average of the ac coupled signal. The analog comparator was designed for low hysteresis (typically less than
0.1 mV) and high gain (typically 70 dB).
Pin 2 - Analog Feedback
This is the non inverting input to the analog signal
comparator within the IC. In an encoder application it
should be connected to the analog output ofthe encoder
circuit. This may be Pin 7 or a low pass filter output
connected to Pin 7. In a decode circuit Pin 2 is not used
and may be tied to VCC/2 on Pin 10, ground or left open.
The analog input comparator has bias currents of
1.5 p,A max, thus the driving impedances of Pins 1 and
2 should be equal to avoid disturbing the idle channel
characteristics of the encoder.
Pin 3 - Syllabic Filter
This is the point at which the syllabic filter voltage is
returned to the IC in order to control the integrator step
size. It is an NPN input to an op amp. The syllabic filter
consists of an RC network between Pins 11 and 3, Typical time constant values of 6.0 ms to 50 ms are used
in voice codecs.
Pin 4 - Gain Control Input
The syllabic filter voltage appears across Cs of the
syllabic filter and is the voltage between VCC and
Pin 3. The active voltage to current (V -I) converter
drives Pin 4 to the same voltage at a slew rate of
typically 0.5 V/p,s. Thus the current injected into Pin 4
(lGC) is the syllabic filter voltage divided by the Rx
resistance. Figure 7 shows the relationship between
IGC (x-axis) and the integrating current, lint (y-axis).
The discrepancy, which is most significant at very low
currents, is due to circuitry within the slope polarity
switch which enables trimming to a low total loop
offset. The Rx resistor is then varied to adjust the loop
gain of the codec, but should be no larger than 5.0 kG
to maintain stability.
Pin 5 - Reference Input
This pin is the noninverting input of the integrator
amplifier. It is used to reference the dc level ofthe output
signal. In an encoder circuit it must reference the same
voltage as Pin 1 and is tied to Pin 10.
Pin 6 - Filter Input
This inverting op amp input is used to connect the
integrator external components. The integrating current (lint) flows into Pin 6 when the analog input (Pin 1)
is high with respect to the analog feedback (Pin 2) in

MC3417.MC3418.MC3517.MC3518
2-104

the encode mode or when the digital data input
(Pin 13) is high in the decode mode. For the opposite
states, lint flows out of Pin 6. Single integration systems require a capacitor and resistor between Pins 6
and 7. Multipole configurations will have different circuitry. The resistance between Pins 6 and 7 should
always be between 8.0 kG and 13 kG to maintain good
idle channel characteristics.
Pin 7 - Analog Output
This is the integrator op amp output. It is capable
of driving a 600-ohm load referenced to VCC/2 to
+ 6.0 dBm and can otherwise be treated as an op amp
output. Pins 5, 6, and 7 provide full access to the integrator op amp for designing integration filter networks. The slew rate of the internally compensated
integrator op amp is typically 0.5 V//Ls. Pin 7 output
is current limited for both polarities of current flow at
typically 30 mAo
Pin 8 - VEE
The circuit is designed to work in either single or dual
power supply applications. Pin 8 is always connected
to the most negative supply.
Pin 9 - Digital Output
The digital output provides the results of the delta
modulator's conversion. It swings between VCC and
VEE and is CMOS or TTL compatible. Pin 9 is inverting
with respect to Pin 1 and non-inverting with respect to
Pin 2. It is clocked on the falling edge of Pin 14. The
typical 10% to 90% rise and fall times are 250 ns and
50 ns respectively for VCC = 12 V and CL = 25 pF to
ground.
Pin 10 - Vccl2 Output
An internal low impedance mid-supply reference is
provided for use of the MC3417/18 in single supply
applications. The internal regulator is a current source
and must be loaded with a resistor to insure its sinking
capability. If a + 6.0 dBmo signal is expected across
a 600 ohm input bias resistor, then Pin 10 must sink
2.2 V/600 G = 3.66 mAo This is only possible if Pin 10
sources 3.66 mA into a resistor normally and will
source only the difference under peak load. The reference load resistor is chosen accordingly. A 0.1 p,F
bypass capacitor from Pin 10 to VEE is also recommended. The VCC/2 reference is capable of sourcing
10 mA and can be used as a reference elsewhere in
the system circuitry.
Pin 11 - Coincidence Output
The duty cycle of this pin is proportional to the voltage
across CS. The coincidence output will be low whenever
the content of the internal shift register is all 1s or all
Os. In the MC3417 the register is 3 bits long while the
MC3418 contains a 4 bit register. Pin 11 is an open collector of an NPN device and requires a pull-up resistor.

MOTOROLA COMMUNICATIONS DEVICE DATA

Ifthe syllabic filter is to have equal charge and discharge
time constants, the value of Rp should be much less
than RS. In systems requiring different charge and discharge constants, the charging constant is RSCS while
the decaying constant is (RS + Rp)CS. Thus longer
decays are easily achievable. The NPN device should
not be required to sink more than 3.0 rnA in any configuration. The typical 10% to 90% rise and fall times
are 200 ns and 100 ns respectively for RL = 4.0 kG to
+ 12 V and CL = 25 pF to ground.
Pin 12 - Digital Threshold
This input sets the switching threshold for Pins 13,
14, and 15. It is intended to aid in interfacing different
logic families without external parts. Often it is connected to the VCC/2 reference for CMOS interface or can
be biased two diode drops above VEE for TTL interface.

tained for 0.5 J-LS before and after the clock trigger for
proper clocking.
Pin 14 - Clock Input
The clock input determines the data rate of the
codec circuit. A 32K bit rate requires a 32 kHz clock.
The switching threshold of the clock input is set by
Pin 12. The shift register circuit toggles on the falling
edge of the clock input. The minimum width for a
positive-going pulse on the clock input is 300 ns,
whereas for a negative-going pulse, it is 900 ns.
Pin 15 - Encode/Decode
This pin controls the connection of the analog input
comparator and the digital input comparator to the
internal shift register. If high, the result of the analog
comparison will be clocked into the register on the failing edge at Pin 14. If low, the digital input state will be
entered. This allows use ofthe Ie as an encoder/decoder
or simplex codec without external parts. Furthermore,
it allows non-voice patterns to be forced onto the transmission line through Pin 13 in an encoder.

Pin 13 - Digital Data Input
In a decode application, the digital data stream is
applied to Pin 13. In an encoder it may be unused or
may be used to transmit signaling message under the
control of Pin 15. It is an inverting input with respect to
Pin 9. When Pins 9 and 13 are connected, a toggle flipflop is formed and a forced idle channel pattern can be
transmitted. The digital data input level should be main-

Pin 16-VCC
The power supply range is from 4.75 to 16.5 volts
between Pin VCC and VEE.

FIGURE 1 - POWER SUPPLY CURRENT

FIGURE 2 - IGCR. GAIN CONTROL RANGE and
lint - INTEGRATING CURRENT

VCC

-

ICC
1 k
16

VCC

u.

u.

~110.1

~llo.I/1F

/IF
16

1 k
2

15
14

4

6

15

CVSD 13
MC3517
MC3518
12

4

6

11

14

·Clock

CVSD
13
MC3517
MC3518
12

Digital

Data Input

11
10

10
10.I/1F
8

3

Clock

9

0.05
IlF

8

9

~

O.I/1F
Digital
Output

Note: Digital Output"" Digital Data Input

"'For static testing, the clock is only necessary for
preconditioning to obtain proper state for a given input.

MOTOROLA COMMUNICATIONS DEVICE DATA

MC3417.MC3418.MC3517.MC3518
2-105

FIGURE 3 - INPUT BIAS CURRENTS, ANALOG
COMPARATOR OFFSET VOLTAGE AND CURRENT

FIGURE 4 - INTEGRATOR AMPLIFIER OFFSET
VOLTAGE AND CURRENT

VCC

VCC
u.

VIO(comparator)

1 k

16

16
2

15
14
CVSD
MC3517
MC3518

15
14

3

Clock

0.1 ",F

13

CVSD
MC3517 13
MC3518
12

4
5

12
11

11

+ 0-+-<"-"---'---1

10
8

~I
I;
.... -=-=0

(I ntegrator
Amplifier

9

10.1

10

8

9

",F

Offset

Voltage)

Note: The analog comparator offset voltage Is tested
under dynamic conditions and therefore must
be measured with appropriate filtering.

FIGURE 5 - VII CONVERTER OFFSET VOL TAGE,
VloandVIOX

FIGURE 6 - DYNAMIC INTEGRATING CURRENT MATCH

*32 kHz MC3418/MC3518
16 kHz MC3417iMC3517

16
15
14

3
4

Clock*

6

CVSD
MC3517
MC3518

Clock*

13
12
11
10

Vo(AV)
(Note 1)

8

9

'32 kHz MC3418iMC3518
16 kHz MC3417iMC3517
Notes: 1. Vo(AV1. Dynamic Integrating Current Match, is the average
Note: V'OX is the average voltage of the triangular

voltage of the triangular waveform observed at the measurement points, across 10 kfl resistor with IGC = 1.5 rnA.
2. See Note 2 of the Electrical Characteristics. Page 3.

waveform observed at the measurement points.

MC3417.MC3418.MC3517.MC3518
2-106

MOTOROLA COMMUNICATIONS DEVICE DATA

TYPICAL PERFORMANCE CURVES
FIGURE 8 - NORMALIZED DYNAMIC
INTEGRATING CURRENT MATCH versus VCC

FIGURE 7 - TYPICAL lint versus IGC IMean ± 20)
100
70
0:: 50

+80

~

z

.3

3D

::1
1l

20

'"z

10
7.0
5.0

~
;!;

3.0

i
I

+60

~ ~
;; !<

+40

Q
ill
N

+2 0

u.s

I

"...ffi

5'

.A

'"

'"

~I

A'"

il'1 VCC'12V
TA"25'C

~

2.0

~~

1.0

2.0

1.0

I
3.0

5.0 7.0

20

10

50

-2 0

~~

-4 0

> ~

-6 0

afB

II

3D

~ ~

70

-80
5.0

100

-

...--

6.0

IGC. GAIN CONTROL CURRENT (PA) -PIN 4

V

TA' 25'C

feLK '" 32 kHz

(Sea Figure 6,
Normalized to 10 kn
'" IGC '1.5 mAl

7.0

8.0

9.0

10

12

11

13

14

15

VCC. SUPPLY VOLTAGE (VOLTS)

FIGURE 9 - NORMALIZED DYNAMIC INTEGRATING
CURRENT MATCH versus CLOCK FREQUENCY

FIGURE 10 - DYNAMIC TOTAL LOOP
OFFSET versus CLOCK FREQUENCY

+5 0

+1.0

i"-,
0

1£
Q

~

Q

9

\

0

~

g

...

1\

..

u

31

\

TA·25'C
VCC"12V
51--- (Sae Figure 6,

3D

40

50

70

100

\

"

IGC'12"A

i'

'\

r

IGC"33"A

1\

Vee = 12V
TA = 25"C

-2.0

r-- (See Note 2of Electrical
ICharajristt'lage3.11

10

200

~ I'-- ......
1\

j

\

-100

~

-1.0

z
>
Q

NormalizBdto
10 kn '" IGC • 1.5 mAl

20

r-- ;-- ~~

t;

"r'\

5

I---...

>"
.s

+251'--

10

...-

V

-

...-- V

0

ICLK. CLOCK FREQUENCY (kHz)

\

20
30
50
70
100
ICLK. CLOCK FREOUENCY (kHz)

200

FIGURE 11 - BLOCK DIAGRAM OF THE CVSD ENCODER
Clock

Audio
In

Integrator

MOTOROLA COMMUNICATIONS DEVICE DATA

Slope
PolarIty
Switch

Slope
Magnitude
Control

MC3417.MC3418.MC3517.MC3518
2-107

FIGURE 12 - CVSD WAVEFORMS

FIGURE 13 - BLOCK DIAGRAM OF THE CVSD DECODER

Clock

~
~igital--.

Audio

Out

.--

Integrator

MC3417.MC3418.MC3517.MC3518
2-108

Level Detect

Sampler

Algorithm

Slope
Magnitude
Control

Slope
Polarity

Switch

MOTOROLA COMMUNICATIONS DEVICE DATA

FIGURE 14 - 16 kHz SIMPLEX VOICE CODEC
(Using MC3417, Single Pole Companding and Single Integration)
Digital Input

+5.0

Push

Digital Output

to Talk

Key

(Norm.
open)

16K Bits
Encode/i58'Code

Anal
;g
Inpu

-0---1

+

• )IF

A-

1

A+

2

600

VT H 12

l

Ana log

Out put

1.0
k

1>- ~'-

Input

7
Analog

Out

J.
I

Shift Register

I

VCC/2
Ref

coin
Out

~""'''''''"

Sy,RS
In 3

~Ok

6Filter

Ref

18 k Cs
0.33 )IF

It:=

GC4

Switch

O.I)lF

3.3 k Rp

11

Logic

I

I

Cl

16 V CC

,----<

5
Ref

-=

1.

.--

10
10
k

Clock

Camp

013
600

0.1 )IF

Out
9

15

-=

Clock
16 kHz

~ +5.0

Digital

10 k

fVEE

1.3 k

2.4 Meg
Rmin

Rx

~

Vs

CIRCUIT DESCRIPTION
The continuously variable slope delta modulator
(CVSD) is a simple alternative to more complex conventional conversion techniques in systems requiring digital
communication of analog signals. The human voice is
analog, but digital transmission of any signal over great
distance is attractive. Signal/noise ratios do not vary with
distance in digital transmission and multiplexing,
switching and repeating hardware is more economical and
easier to design. However, instrumentation A to D converters do not meet the communications requirements.
The CVSD A to D is well suited to the requirements of
digital communications and is an economically efficient
means of digitizing analog inputs for transmission.
The Delta Modulator
The innermost control loop of a CVSD converter is
a simple delta modulator. A block diagram CVSD Encoder
is shown in Figure 11. A delta modulator consists of a
comparator in the forward path and an integrator in
the feedback path of a simple control loop. The inputs
to the comparator are the input analog signal and the
integrator output_ The comparator output reflects the

MOTOROLA COMMUNICATIONS DEVICE DATA

sign of the difference between the input voltage and
the integrator output. That sign bit is the digital output
and also controls the direction of ramp in the integrator.
The comparator is normally clocked so as to produce
a synchronous and band limited digital bit stream.
If the clocked serial bit stream is transmitted,
received, and del ivered to a similar integrator at a remote
point, the remote integrator output is a copy of the
transmitting control loop integrator output. To the
extent that the integrator at the transmitting locations
tracks the input signal, the remote receiver reproduces
the input signal. Low pass filtering at the receiver output
will eliminate most of the quantizing noise, if the clock
rate of the bit stream is an octave or more above the
bandwidth of the input signal. Voice bandwidth is 4 kHz
and clock rates from 8 k and up are possible. Thus the
delta modulator digitizes and transmits the analog input
to a remote receiver. The serial, unframed nature of the
data is ideal for communications networks. With no
input at the transmitter, a continuous one zero alternation
is transmitted. If the two integrators are made leaky, then
during any loss of contact the receiver output decays to

MC3417.MC3418.MC3517.MC3518
2-109

CIRCUIT DESCRIPTION (continued)
zero and receive restart begins without framing when the
receiver reacquires. Similarly a delta modulator is tolerant
of sporadic bit errors. Figure 12 shows the delta modulator waveforms while Figure 13 shows the corresponding
CVSD decoder block diagram.
The Companding Algorithm
The fundamental advantages of the delta modulator
are its simplicity and the serial format of its output.
Its limitations are its ability to accurately convert the
input within a limited digital bit rate. The analog input
must be band limited and amplitude limited. The frequency limitations are governed by the nyquist rate while
the amplitude capabilities are set by the gain of the
integrator.
The frequency limits are bounded on the upper end;
that is, for any input bandwidth there exists a clock
frequency larger than that bandwidth which will trans·
mit the signal with a specific noise level. However, the
amplitude' limits are bounded on both upper and fower
ends. For a signal level, one specific gain will achieve an
optimum noise level. Unfortunately, the basic delta
modulator has a small dynamic range over which the
noise level is constant.
The continuously variable slope circuitry provides
increased dynamic range by adjusting the gain of the
integrator. For a given clock frequency and input
bandwidth the additional circuitry increases the delta
modulator's dynamic range. External to the basic
delta modulator is an algorithm which monit,ors the
past few outputs of the delta 1)10dul,ator in a simple
shift register. The register is 3 or 4 bits long depending on
the appl ication. The accepted CVSD algorithm simply
monitors the contents of the shift register and indicates

if it contains all 1s or Os. This condition is called coincidence. When it occurs, it indicates that the gain of the
integrator is too small. The coincidence output charges
a single pole low pass filter. The voltage output of this
syllabic filter control,s the integrator gain through a pulse
amplitude modulator whose other input is the sign bit
or up/down control.
The simplicity of the all ones, all zeros algorithm
should not be taken lightly. Many other control algorithms using the shift register have been, tried. The key to
the accepted algorithm is that it provides a measure of
the average power or level of the input signal. Other
. techniques provide more instantaneous information
about the shape of the input curve. The purpose of
the algorithm is to control the gain of the integrator
and to increase the dynamic range. Thus a measure of
the average input level is what is needed.
The algorithm is repeated 'in the receiver and thus
the level data is recovered in the receiver. Because the
algorithm only operates on the past serial data, it changes
the nature of the bit stream without changing the channel
bit rate.
The effect of the algorithm is to compand the input
signal. If a CVSD encoder is played into a basic delta
modulator, the output of the delta modulator will reflect
the shape of the input signal but all of the output will
be at an equal level. Thus the algorithm at the output is
needed to restore the level variations. The bit stream
in the channel is as if it were from a standard delta modulator .with a constant level input.
The delta modulator encoder with the CVSD algorithm
provides an efficient method for digitizing a voice input
in a manner which is especially convenient for digital
communciations requirements.

APPLICATIONS INFORMATION
CVSD DESIGN CONSIDERATIONS

Asimple CVSD encoder using the MC3417 or MC3418
is shown in Figure 14. These ICs are general purpose
CVSD building blocks which allow the system designer
to tailor the encoder's transmission characteristics to
the application. Thus, the achievable transmissioncapabilities are constrained by the fundamental limitatio'ns
of delta modulation and the design of encoder parameters. The performance is not dictated by the internal
configuration of the MC3417 and MC3418. There are
seven design considerations involved in designing
these basic CVSD building blocks into a specific codec
application, and they are as follows:
1. Selection of clock rate

MC3417.MC3418.MC3517.MC3518
2-110

2.
3.
4.
5.
6.
7.

Required number of shift register bits
Selection of loop gain
Selection of minimum step size
Design of integration filter transfer function
Design of syllabic filter transfer function
Design of low pass filter at the receiver

The circuit in Figure 14 is the most basic CVSD circuit
possible. For ma~y applications in secure radio or other
intelligible voice channel requirements, it is entirely
sufficient. In this circuit, items 5 and 6 are reduced to
their simplest form. The syllabic and integration filters
are both single pole networks. The selection of items
1 th rough 4 govern the codec performance.

MOTOROLA COMMUNICATIONS DEVICE DATA

s::

a
o

CVSD CIRCUIT SCHEMATIC

::D

Vee

5:

16

8
s::
s::
c
z

20 k

20 k

50 itA

12 k

50 itA

9
0 Digital
Output

•

(')

~

(5

zen

o

~

Analog 1
Input

Analog
Feedback

(')

m

o

»~

Digital

13

01-1_ _-'

Data Input

Output

e
Digital

12

Threshold 0

I•

01-1--...,

r
4 Gain
~----------oo Control

14
Clock

i:1

(')

.......';'I

Filter

Encode/ 15
Decode-

(0)

i:

Analog 7
Output

(')

.......
(0)

~

i:

(')

...';'Icn

(0)

i:
1\)(')

......
... m
,(0)

... cn

6
Vee/2

Ref

Output

Input

Filter
Input

aP
VEE

CVSD DESIGN CONSIDERATIONS (continued)
Layout Considerations
Care should be exercised to isolate all digital signal
paths (Pins 9, 11, 13, and 14) from analog signal paths
(Pins 1-7 and 10) in order to achieve proper idle channel
performance.
Clock Rate
With minor modifications the circuit in Figure 14
may be operated anywhere from 9.6 kHz to 64 kHz
clock rates. Obviously the higher the clock rate the higher
the SIN performance. The circuit in Figure 14 typically
produces the SIN performance shown in Figure 15.
The selection of clock rate is usually dictated by the
bandwidth of the transmission medium. Voice band·
width systems will require no higher than 9600 Hz.
Some radio systems will allow 12 kHz. Private 4·wire
telephone systems are often operated at 16 kHz and
commercial telephone performance can be achieved
at 32K bits and above. Other codecs may use bit rates
up to 200K bits/sec.

Selection of Loop Gain
The gain of the circuit in Figure 14 is set by resistor
Rx. Rx must be selected to provide the proper integrator
step size for high level signals such that the companding
ratio does not exceed about 25%. The companding ratio
is the active low duty cycle of the coincidence output on
Pin 11 ofthe codec circuit. Thus the system gain is dependent on:
1. The maximum level and frequency of the input
signal.
2. The transfer function of the integration filter.
For voice codecs the typical input Signal is taken to be
a sine wave at 1 kHz of 0 dBmo level. In practice, the
useful dynamic range extends about 6 dB above the design
level. In any system the companding ratio should not
exceed 30%.
To calculate the required step size current, we must
describe the transfer characteristics of the integration
filter. In the basic circuit of Figure 14, a single pole of
160 Hz is used.
Rl = 10 kG, Cl = 0.1 /LF

FIGURE 15 - SIGNAL·TO·NOISE PERFORMANCE
OF MC3417 WITH SINGLE INTEGRATION. SINGLE·POLE
AND COMPANDING AT 16K BITS - TYPICAL

Vo _

1

Ii - C(S + l/RC) Wo =

10 3 =
15

l...--/
/

Clock Rate = 16 kHz
I

10

Test Tone = 1 kHz Sine Wave
Noise Weightillg C. Message

-30

~

I

-20

-10

10

INPUT LEVEL (dB) RELATIVE TO SLOPE OVERLOAO

Shift Register Length (Algorithm)
The MC3417 has a three-bit algorithm and the MC3418
has a four-bit algorithm. For clock rates of 16 kHz and
below, the 3-bit algorithm is well suited. For 32 kHz
and higher clock rates, the 4-bit system is preferred.
Since the algorithm records a fixed past history of the
input signal, a longer shift register is required to obtain
the same internal hsitory. At 16 bits and below, the
4-bit algorithm will produce a slightly wider dynamic
range at the expense of level change response. Basically
the MC3417 is designed for low bit rate systems and the
MC3418 is intended for high performance, high bit rate
system. At bit rates above 64K bits either part will
work well.

MC3417.MC3418.MC3517.MC3518
2·112

21Tf

Wo =

21Tf

f=159.2Hz

I

I
II
5.0
-40

"

K
-S-+-w-o

Note that the integration _filter produces a single-pole
response from 300 to 3 kHz. The current required to
move the integrator output a specific voltage from zero
is simply:
V + ( Cl x---.Q
dV )
I' = ---.Q
I
Rl
dt
Now a 0 dBmo sine wave has a peak value of 1.0954
volts. In 1/8 of a cycle of a sine wave centered around
the zero crossing, the sine wave changes by approximately
its peak value. The CVSD step should trace that change.
The required current for a 0 dBm 1 kHz sine wave is:
1_=
I

1.1V
+0.1Il F (1.1)=0.935mA
*2(10 kG)
0.125 ms

*The maximum voltage across Rl when maximum
slew is required is:
1.1 V
2
Now the voltage range of the syllabic filter is the
power supply voltage, thus:
Rx = 0.25(VCC) 0.935 mA
A similar procedure can be followed to establish the
proper gain for any input level and integration filter type.

MOTOROLA COMMUNICATIONS DEVICE DATA

CVSD DESIGN CONSIDERATIONS (continued)
Minimum Step Size
The final parameter to be selected for the simple codec
in Figure 14 is idle channel step size. With no input signal,
the digital output becomes a one·zero alternating pattern
and the analog output becomes a small triangle wave.
Mismatches of internal currents and offsets limit the
minimum step size which will produce a perfect idle
channel pattern. The MC3417 is tested to ensure that
a 20 mVp·p minimum step size at 16 kHz will attain a
proper idle channel. The idle channel step size must be
twice the specified total loop offset if a one-zero idle
pattern is desired. In some applications a much smaller
minimum step size (e.g., 0.1 mV) can produce quiet
performance without providing a 1-0 pattern.
To set the idle channel step size, the value of Rmin
must be selected. With no input signal, the slope control
algorithm is inactive. A long series of ones or zeros never
occurs. Thus, the voltage across the syllabic filter capacitor (CS) would decay to zero. However, the voltage
divider of RS and Rmin (see Figure 14) sets the minimum
allowed voltage across the syllabic filter capacitor. That
voltage must produce the desired ramps at the analog
output. Again we write the filter input current equation:
I' = Vo
I
Rl

+ C dVo
dt

For values of Vo near VCC/2 the VoiR term is negligible; thus

where t.T is the clock period and t. Vo is the desired
peak-to-peak value of the idle output. For a 16K-bit
system using the circuit in Figure 14
1'= O.lJ.LF 20mV = 33J.LA
I
62.5J.Ls
The voltage on Cs wh ich produces a 33 J.LA current is
determined by the value of Rx.
liRx = Vsmin;for33J.LA, Vsmin =41.6 mV
In Figure 14 RS is 18 H2. That selection is discussed
with the syllabic filter considerations. The voltage divider
of RS and Rmin must produce an output of 41.6 mV.
VCC

RS

RS

+ Rmin

= VSmin

Rmin = 2.4 Mil

Having established these four parameters - clock rate,
number of shift register bits, loop gain and minimum
step size - the encoder circuit in Figure 14 will function
at near optimum performance for input levels around
OdBm.

INCREASING CVSD PERFORMANCE
Integration Filter Design
The circuit in Figure 14 uses a single-pole integration
network formed with a 0.1 J.LF capacitor and a 10 kil
resistor. It is possible to improve the perform"ance of the
circuit in Figure 14 by 1 or 2 dB by using a two-pole
integration network. The improved circuit is shown.
The first pole is still placed below 300 Hz to provide
the 1IS voice content curve and a second pole is placed
somewhere above the 1 kHz frequency. For -telephony
circuits, the second pole can be placed above 1.8 kHz
to exceed the 1633 touchtone frequency. In other communication systems, values as low as 1 kHz may be
selected. In general, the lower in frequency the second
pole is placed, the greater the noise improvement. Then,
to ensure the encqder loop stability, a zero is added to
keep the phase shift less than 1800 . This zero should
be placed slightly above the low-pass output filter break
frequency so as not to reduce the effectiveness of the
second pole. A network of 235 Hz, 2 kHz and 5.2 kHz
is typical for telephone applications while 160 Hz,
1.2 kHz and 2.8 kHz might be used in voice only channels.
(Voice only channels can use an output low-pass filter
which breaks at about 2.5 kHz.) The two-pole network
in Figure 16 has a transfer function of:

MOTOROLA COMMUNICATIONS DEVICE DATA

FIGURE 16 - IMPROVEO FILTER CONFIGURATION

R2

Analog Output o-....JVI/\r--<~-+-<.

600

R1600

Cl
0.1 "F

13 k

These component values are for the telephone channel circuit poles described in
the text. The R2, C2 product can be provided with different values of Rand C. R2
should be chosen to be equal to the termination resistor on Pin 1.

MC3417.MC341S.MC3517.MC351S
2-113

INCREASING CVSD PERFORMANCE (continued)
Thus the two poles and the zero can be selected arbitrarily
as long as the zero is at a higher frequency than the first
pole. The values in Figure 16 represent one implementation of the telephony filter requirement.
The selection of the two-pole filter network effects
the selection of the loop gain value and the minimum step
size resistor. The required integrator current for a given
change in voltage now becomes:
li= Vo+(R 2 C2 +R 1C 1
RO
RO
RO

+C1\~Vo+

!

~T

R1C1R2C2)~V02
~.
R2C2C l +
--.
RO
~T2
The calculation of desired gain resistor Rx then proceeds
exactly as previously described.
Syllabic Filter Design
The syllabic filter in Figure 14 is a simple single-pole
network of 18 kit and 0.33 pF. This produces a 6.0 ms
time constant for the averaging of the coincidence output
signal. The voltage across the capacitor determines the
integrator current which in turn establishes the step size.
The integrator current and the resulting step size determine the companding ratio and the SIN performance.
The companding ratio is defined as tbe voltage across
CSIVCC·
The SIN performance may be improved by modifying
the voltage to current transformation produced by Rx.
If different portions ofthe total Rx are shunted by diodes,
the integrator current can be other than (VCC - VS)/R x .
These breakpoint curves must be designed experimentally for the particular system application. In general,
one would wish that the current would double with
input level. To design the desired curve, supply current
to Pin 4 of the codec from an external source. Input a
signal level and adjust the current until the SIN perfor-

mance is optimum. Then record the syllabic filter voltage and the current. Repeat this for all desired signal
levels. Then derive the resistor diode network which
produces that curve on a curve tracer.
Once the network is designed with the curve tracer,
it is then inserted in place of Rx in the circuit and the
forced optimum noise performance will be ach ieved
from the active syllabic algorithm.
Diode breakpoint networks may be very simple or
moderately complex and can improve the usable dynamic
range of any codec. In the past they have been used in
high performance telephone codecs.
Typical resistor-d iode networks are shown in Figure 17.
FIGURE 17 - RESISTOR-DIODE NETWORKS

01
R1

02 03
R2

~
01

If the performance of more complex diode networks
is desired, the circuit in Figure 18 should be used. It
simulates the companding characteristics of nonlinear
Rx ei.ements in a different manner.
Output Low Pass Filter
A low pass filter is required at the receiving circuit
output to eliminate quantizing noise. In general, the lower
the bit rate, the better the filter must be. The filter in
Figure 20 provides excellent performance for 12 kHz
to 40 kHz systems.

TELEPHONE CARRIER QUALITY CODEC USING MC3418
Two specifications of the integrated circuit are specifically intended to meet the performance requirements
of commercial telephone systems. First, slope polarity
switch current matching is laser trimmed to guarantee
proper idle channel performance with 5 mV minimum
step size and a typical 1% current match from 15 pA
to 3 mAo Thus a 300 to 1 range of step size variation is
possible. Second, the MC3418 provides the four-bit
algorithm currently used in subscriber loop telephone
systems. With these specifications and the circuit of Figure 18, a telephone quality codec can be mass produced.

MC3417.MC3418.MC3517.MC3518
2·114

The circuit in Figure 18 provides a 30 dB SINc ratio
over 50 dB of dynamic range for a 1 kHz test tone at
a 37.7K bit rate. At 37.7K bits, 40 voice channels may
be multiplexed on a standard 1.544 megabit Tl facility.
Th is codec has also been tested for 10- 7 error rates with
asynchronous and synchronous data up to 2400 baud
and for reliable performance with DTMF signaling. Thus,
the design is applicable in telephone quality subscriber
loop carrier systems, subscriber loop concentrators and
small PABX installations.

MOTOROLA COMMUNICATIONS DEVICE DATA

TELEPHONE CARRIER QUALITY COOEC USING MC3418 (continued)
The Active Companding Network
The unique feature of the codec in Figure 18 is the
step size control circuit which uses a companding ratio
reference. the present step size. and the present syllabic
filter output to establish the optimum companding
ratios and step sizes for any given input level. The companding ratio of a CVSO codec is defined as the duty
cycle of the coincidence output. It is the parameter measured by the syllabic filter and is the voltage across Cs
divided by the voltage swing of the coincidence output.
In Figure 18. the voltage swing of Pin 11 is 6.0 volts.
The operating companding ratio is analoged by the voltage between Pins 10 and 4 by means ofthe virtual short
across Pins 3 and 4 of the V to I op amp within the
integrated circuit. Thus. the instantaneous companding
ratio of the codec is always available at the negative
input of Al.
The diode 01 and the gain of A1 and A2 provide a
companding ratio reference for any input level. If the
output of A2 is more than 0.7 volts below VCC/2. then
the positive input of A 1 is (VCC/2 - 0.7). The on diode
drop at the input of Al represents a12% companding
ratio (12% = 0.7 V/6.0 V).
The present step size ofthe operating codec is directly
related to the voltage across Rx. which established the

integrator current. In Figure 18. the voltage across Rx
is amplified by the differential amplifier A2 whose output is single ended with respect to Pin 10 of the IC.
For large signal inputs. the step size is large and the
output of A2 is lower than 0.7 volts. Thus 01 is fully on.
The present step size is not' a factor in the step size
control. However. the difference between 12% companding ratio and the instantaneous companding ratio
at Pin 4 is amplified by A1. The output of A1 changes
the voltage across Rx in a direction which reduces the
difference between the companding reference and the
operating ratio by changing the step size. The ratio of
R4 and R3 determines how closely the voltage at Pin 4
will be forced to 12%. The selection of R3 and R4 is
initially experimental. However. the resulting companding control is dependent on Rx. R3. R4. and the full diode
drop 01. These values are easy to reproduce from codec
to codec.
For small input levels. the companding ratio reference
becomes the output of A2 rather than the diode drop.
The operating companding ratio on Pin 4 is then compared to a companding ratio smaller than 12% which is
determined by the voltage drop across Rx and the gain
of A2 and A1. The gain of A2 is also experimentally
determined. but once determined. the circuitry is easily

FIGURE 18 - TELEPHONE QUALITY DEL TAMOD CODER
(Both double integration and active companding control are used to obtain improved CVSD performance.
Laser trimming of the integrated circuit provides reliable idle channel and step size range characteristics.)

Voice/Non~Voice

Clock

Input
37.7 kHz

SELECT

Digital
Output
(Vee /2 )

+12 V
15

Analog
Input

16

14

O.221J F

0--1

Vee

2

lN914

Non-Voice 3.6k
Input

(Digital
Input)

Analog
Output

1 k

VSyl
R2
3.6 k

200 k

33 k

e2
0.0251'F

R3
RO

AI, A2,

13 k

iiiiCi458
O.I1'F

MOTOROLA COMMUNICATIONS DEVICE DATA

0.1 p.F

MC3417.MC3418.MC3517.MC3518
2·115

TELEPHONE CARRIER QUALITY CODEC USING MC3418 (continued)
FIGURE 19 - SIGNAL·TO·NOISE PERFORMANCE
AND FREQUENCY RESPONSE

(Showing the improvement ~ealized with
the circuit in Figure 18.)

a. SIGNAL·TO·NOISE PERFORMANCE OF TELEPHONY
QUALITY DELTAMODULATOR
35

II!

"

Z

w
!!l

30t----~====~~~=====tl
50 dB

a
z
~

.J

~

4 BIT ALGORITHM
37.7K BITS
1 kHz TEST TONE
C MESSAGE WEIGHT
25+---4---------------------------~

CJ

Cii

20
-48

-36
-24
-12
o
INPUT LEVEL IN dBmO

12

b. FREQUENCY RESPONSE versus INPUT LEVEL
(SLOPE OVERLOAD CHARACTERISTIC)

OdBm INPUT
E

II!

"

~

0
-10

.J

-20

>
w

-30

w

.J

I- -40
::;)

"-

I- -50

4 BIT ALGORITHM
37.7 K BITS

::;)

a

repeated.
With no input signal, the companding ratio at Pin 4
goes to zero and the voltage across Rx goes to zero.
The voltage at the output of A2 becomes zero since
there is no drop across Rx. With no signal input, the
actively controlled step size vanished.
The minimum step size is established by the 500 k
resistor between VCC and VCcJ2 and is therefore inde·
pendently selectable.
The signar to noise results of the active. companding
network are shown in Figure 19. A smooth 2 dB drop is
realized from +12 dBm to -24 under the control of Al.
At -24 dBm, A2 begins to degenerate the companding
reference and the resulting step size is reduced so as to
extend the dynamic range of the codec by 20 dBm.
The slope overload characteristic is also shown. The
active companding network produces improved perfor·
mance with frequency. The 0 dBm slope overload point is
raised to 4.8 kHz because of the gain available in control·
ling the voltage across Rx. The curves demonstrate that
the level linearity has been maintained or improved. *
The codec in Figure 18 is designed specifically for
37.7K bit systems. However, the benefits of the active
companding network are not limited to high bit rate
systems. By modifying the crossover region (changing
the gain of A2), the active technique may be used to
improve the performance of lower bit rate systems.
The performance and repeatability of the codec in
Figure 18 represents a significant step forward in the art
and colit of CVSD codec designs.

* A larger value for C2 is required in the decoder circuit

-60

than in the encoder to adjust the level linearity with
frequency. In Figure 18, 0.050 J.lF would work well.

o

2 kHz

4 kHz

6 kHz

8 kHz 10 kHz

INPUT FREQUENCY IN Hz
FIGURE 20 - HIGH PERFORMANCE ELLIPTIC FILTER FOR CVSD OUTPUT
C1
R7
Rl

R2

87.6k

175k

C3

C4

157 pF 78 pF

(1~~7

k

R4
1.11 M
Designed for 0.28 dB ripple In the past band

wn = 3 kHz
Ws = ~ 6 kHz
AdB at Ws and above 29.5 dB

MC3417.MC3418.MC3517.MC3518
2-116

MOTOROLA COMMUNICATIONS DEVICE DATA

FIGURE 21 - FULL DUPLEX/32K BIT CVSD VOICE CODEC USING MC3517/18 AND MC3503/6 OP AMP

Digital Output
Force Idle
Channel

+5 V

9

C2

16
2
Analog Input

o---j

5

11
MC3417
or
MC3418

3

RXI

D.1I

OJ

-=

i[

Cll

[[

4

8

14
Clock

-=

+5 V

14
12

16

'"

0.
[[

Analog Output

R7

Rl1
C9

R6

11
Digital

C5

9

Test
C7

RIO

C6

MC3417
or
MC3418

OJ

'"

[[

3

R9

RM2
R5

C8

CS2

RX2

4

6

RS
13
C4
Digital Input

Cadee Components

Input Filter Specifications

Filter Components

RXI. RX2- 3.3 kil
RPI. Rp2 - 3.3 kil
RSI. RS2 - 100 kil
Rll. RI2 - 20 kil
R12 - 1 kil
RMI. RM2 -5 Mil (MC3417)

12 dB/Octave Rotloff above 3.3 kHz
6 dB/Octave Roll off below 50 Hz

RI-965il
R2 - 72 kil
R3 - 72 kil
R4 - 63.46 kil
R5 - 127 kil
R6 - 365.5 kil
R7 - 1.645 Mil
R8 - 72 kil
R9 - 72 kfl
RIO - 29.5 kfl
All - 72 kfl

Minimum step size

=

20 mV

RMI. RM2 - 15 Mil (MC3418)

Output Filter Specifications
Break Frequency - 3.3 kHz
Stop Band -

9 kHz

Stop Band Atten. - 50 dB
RoUaff - > 40 dB/Octave

Minimum step size = 6 mV

CSI. CS2 - 0.05 /IF
Cll. CI2 - 0.05/lF
2 MC3417 (or MC3418)
1 MC3403 (or MC3406)

Cl - 3.3 /IF
C2 - 837 pF
C3 -

C4
C5
C6
C7
C8
C9

536 pF

- 1000 pF
- 222 pF
- 77 pF
-38pF
- 837 pF
- 536 pF

Note: All Res. 0.1% to 1%.
All Cap. 1.0%

Note: All Res. 5%
All Cap. 5%

MOTOROLA COMMUNICATIONS DEVICE DATA

MC3417.MC3418.MC3517.MC3518
2-117

COMPARATIVE CODEC PERFORMANCE
The salient feature of CVSD codecs using the MC3517
and MC3518 family is versatility. The range of codec
complexity tradeoffs and bit rate is so wide that one
cannot grasp the interdependency of parameters for
voice applications in a few pages.
Design of a specific codec must be tailored to the
digital channel bandwidth, the analog bandwidth, the
quality of signal transmission required and the cost
objectives. To illustrate the choices available, the data in
Figure 22 compares the signal-to·noise ratios and dynamic
range of various codec design options at 32K bits.
Generally, the relative merits of each design feature will
remain intact in any appl ication. Lowering the bit rate
will reduce the dynamic range and noise performance
of all techniques. As the bit rate is increased, the overall
performance of each technique will improve and the need
for more complex designs diminishes.
Non·voice applications of the MC3517 and MC3518
are also possible. In those cases, the signal bandwidth
and ampl itude characteristics must be defined before
the specification of codec parameters can begin. However, in general, the design can proceed along the lines of
the voice applications shown here, taking into account the
different signal bandwidth requirements.

MC3417.MC3418.MC3517.MC3518
2-118

FIGURE 22 - COMPARATIVE CODEC PERFORMANCE SIGNAL·TO·NOISE RATIO FOR 1 kHz TEST TONE

35

~
w
OJ

~

'"
z

30
25

1/

z

bV
V

20

u

~

a
-I""'"

15
10
5.0

I--

/Vc

V/ V

V

-

V /"
V

- --

J-

/V

ail

\
---r----.-.

32K
CVSO with
MC341) or MC3418

t--

~V

V
-45

-40

-35

-30

-25

-20

-15

-10

-5.0

AMPLITUDE IdBI

These curves demonstrate the improved performance obtained
with several codec designs of varying complexity.

Curve a -

Complex companding and double integration
(Figure 18 - MC3418)
Curve b - Double integration (Figure 14 using Figure 16MC3418)
Curve c - Single integration (Figure 14 - MC3418) with
6.0 mV step size
Curve d - Single integration (Figure 14 - MC3417) with
25 mV step size

MOTOROLA COMMUNICATIONS DEVICE DATA

MOTOROLA

-

SEMICONDUCTOR
TECHNICAL DATA

MC3419-1L
SUBSCRIBER LOOP INTERFACE CIRCUIT

SUBSCRIBER LOOP

INTERFACE CIRCUIT

· .. designed as the heart of a circuit to provide BORSHT functions
for telephone service in Central Office, PABX, and Subscriber Carrier equipment. This circuit provides dc power for the telephone
(.!!attery), Qvervoltage protection, §.upervision features such as
hook status and dial pulsing, two-wire differential to four-wire
single-ended conversions and suppression of longitudinal signals
at the two-wire input (t!.vbrid), and facilitates ringing insertion,
Bing trip detection and lesting.

(SLlC)
BIPOLAR LASER-TRIMMED
INTEGRATED CIRCUIT

• Totally Upward Compatible with the MC3419
• All Key Parameters Externally Programmable

-

• Current Sensing Outputs Monitor Status of Both Tip and Ring
Leads for Auxiliary Functions such as: Ground Key, Ring Trip,
Message Waiting Lamp, etc.
.

!II -

18

• On-Hook Power Below 5.0 mW
• Digital Hook Status Output
•
•
•
•

Powerdown Input
Ground Fault Protection
Operates from Single - 20 V to - 56 V Power Source
Size and Weight Reduction Over Conventional Approaches

1

.

L SUFFIX
CERAMIC PACKAGE
CASE 726

• The sale of this product is licensed under Patent No. 4,004,109.
All royalties related to this patent are included in the unit price.
FUNCTIONAL BLOCK DIAGRAM
VCC

r--------- ------,

Bl Mirror I

I
I

~----------

J

:;!

I

EP

I
I
I
I
IL __ ~

,,~

BP

0

h

__

Mirror

I

I

~

 100 Mn)

3

IVCC

-

40

200

/LA

On-Hook Power Dissipation
(RL> 100 Mn)

3

Po

-

1.0

-

mW

Power Supply Noise Rejection
(1.0 kHz @ 1.0 VRMS)

3

VTXNee

-40

-

-

dB

Quiet Battery Noise Rejection
(1.0 kHz @ 1.0 VRMS)

3

VTXNqb

-6.0

-

dB

Sense Current
Tip
Ring

4
0.17
0.17

0.19
0.19

Fault Currents
Tip to VCC
Ring to VCC
Tip to Ring
Tip and Ring to VCC

1

Analog Ground Current

1

Hook Status Output Current
(RL < 2.5 kn, VHSO = +0.4 Vdc)
VHSO = -0.4 Vdc)
(RL> 10 kn, VHSO = +12 Vdc)
VHSO = -12 Vdc)

MOTOROLA COMMUNICATIONS DEVICE DATA

mA/mA
ITSO/ITSI
IRSO/IRSI

IVAG
IpDI
VIH
VIL

1

0.15
0.15

mA
ITip
IRing
ILoop
ITip and IRin(l

Powerdown Logic Levels

-

-

-

-1.2

-

0
2.5
120
2.5

-

-

-

0.1

2.0

/LA

-1.0

-10

/LA
Vdc
Vdc

-

IHSO
+1.0
-0.4

-

+3.0
-1.5
0
0

-4.0

-

+50
-2.0

mA
mA
/LA
/LA

MC3419-1L
2-121

FIGURE 1 -

AC TEST CIRCUIT
1.0~F

VCC
MJE271

2
3
4
5

RL
600
2.0W Ring

VAG

EP

RXI

BP

TXO

TSI

POI

CC

HSO

18

OV

17
16
15
90.09 k
14

~ IHSO(+I

-12 V

'HSO(-I17.4 k

6
7
8
9

RSI

TSO

BN

RSO

EN

HST

VEE

VOB

13
12
11
10

43 k

232 k
-48V

(Tip & Ringl AC Termination Impedance, RO = 600
DC Feed Resistance, RF = 400 n
FIGURE 2 -

n

LONGITUDINAL BALANCE TEST CIRCUIT

VCC
MJE271

2
3

368

Tip

4

+
VL

5
17.4 k

368

;~'O'
'"

Transmit and Receive Gain = 0 dB
Al = MC1741N or Equivalent

6

EP

RXI

BP

TXO

TSI

POI

CC

HSO

RSI

TSO

BN

RSO

8

EN

HST

9

VEE

VOB

18

OV

17
16
15
90.09 k
14
13
12

7

VLON

VAG

11
10
232 k

43 k

-48V
(TIp & Ringl AC Termination Impedance, RO = 600
DC Feed Resistance, RF = 400 n

MC3419-1L
2-122

n

Transmit and Receive Gain = 0 dB
Al = MC1741 N or Equivalent

MOTOROLA COMMUNICATIONS DEVICE DATA

~--------~~~-4~--OOV

90.09 k

1-----48V
1-----51 V
(Tip & Ring) AC Termination Impedance, RO = 600
DC Feed Resistance, RF = 400 n

n

Transmit and Receive Gain = a dB
Al = MC1741N or Equivalent

FIGURE 4 - TSO AND RSO SUPERVISORY OUTPUT TEST CIRCUIT

VCC

2

-

3

VAG

EP

RXI

BP

TXO

TSI

POI

CC

HSO

RSI

TSO

BN

RSO

EN

HST

VEE

VaB

ITSI

-8.0 V

-40 V

8

18
17
16
15
14
1 3 _ ITSO
-12V
12

-12 V
- - . IRSO

11
261 k

9

10

-48 V

MOTOROLA COMMUNICATIONS DEVICE DATA

MC3419-1L
2-123

FIGURE 5 - QUIET BATTERY CURRENT IVQB
versus LOOP CURRENT IL

FIGURE 6 - LONGITUDINAL CAPACITY

4.0
Tvpical
~

V

,g

....

~

a:
a:
=>
u
>
a:

S

3. 0

2.0

 10 kn, the HSO pin is inactive, i.e., VHSO = logic supply Voltage.

15

POI

Powerdown Input pin. This pin is used to deny service to the subscriber. A logic level "0" (VIL <
-4.0 V) powers down the MC3419-1 except for HSO, TSO and RSO. The voltage range of this
high impedance input pin is ± 15 V.

16

TXO

Transmit current Output. This output sinks current to VaB and is proportional to ITSI + IRSI by a
ratio of K1 where: K1 = 0.51. Its saturation voltage is VaB + 2.5 V typo (+ 3.5 V over the
temperature range). This pin is only active during the off-hook power-up condition.

17

RXI

Receive Input. This input sums ac currents from TXO and the receive voltage input (VRX) and
sources all the dc current to TXO. It has a low input impedance (15 n) typically biased 4.5 V
below the VAG pin voltage during off-hook power-up conditions. During powerdown conditions,
the voltages on RXI and TXO can drift up to VAG.

18

VAG

Analog Ground Voltage reference input. The input impedance of this pin is much greater than 1.0 Mn.
It should be ac coupled to system ground and could be direct coupled if system ground is
between 0 V and -12 V. AC coupling requires 300 kn to VCC and 0.1 /LF to system ground. If
Vec and system ground are common, tie VAG directly to Vcc. If dc loop currents are allowed to
go higher than 60 mA, VAG should be biased from -2.5 V to -12 V to avoid problems at high
ambient temperatures.

a

MOTOROLA COMMUNICATIONS DEVICE DATA

MC3419·1L

2·125

FUNCTIONAL DESCRIPTION
Referring to the functional block diagram on page 1,
line sensing resistors (RR and RT) at,the TSI and RSI
pins convert voltages at the Tip and'Ring terminals into
currents which are fed into current mirrors· A1 and A2.
An output of A 1 is mirrored by A3 and summed together
with an output of A2 at the TXO terminal. Thus, a drfferential to single~ended conversion is performed from
the ac line signals to the TXO output.
All the dc current at the TXO output is, fed back
through the RXI terminals to the B1 mirror input. The
inputs to B1 and B2 are made equal by mirroring the
B1 input current to the B2 input through a unity gein
output of the B1 mirror. Both B1 and B2 mirrors have
high gain outputs (x95) which drive the subscriber lines
with balanced currents that are equal in amplitude and
1800 out of phase. The feedback from the TXO output,
through the B-Circuit mirrors, to the'subscriber line
produces a dc feed resistance significantly less, but
proportional to the loop sensing resistors.
In most line-interface systems, the ac termination
impedance is desired to be greater than the dc feed
impedance. A differential ac generator on the subscriber
loop would be terminated by the dc feed impedance if
the total ac current at the rxo output were returned to
the B1 input along with the dc current. Instead, the
MC3419-1 system diverts part of the ac current from the
B-Circuit mirrors. This decreases the ac feedback cur~
rent, causing the ac termination impedance at the line
interface to be greater than the dc feed impedance.
The ac current that is diverted from the B1 mirror
input is coupled to a current-to-voltage converter circuit
that has a low input impedance. This circuit consists of
an op amp (external to the MC3419-1) and a feedback
resistor which produces the transmit output voltage
(Vrx) at the 4-wire interface. Transmission gain is programmed by the op amp feedback resistor (RVTX)'
Rec~ption gain is realized by converting the ac coupled receive input voltage (VRX) to a current through
an external resistor (RRX) at the low impedance RXI
terminal. This current is slimmed at RXI with the dc and
ac feedback current from the A-Circuit mirrors and
drives the B1 mirror input. The B-Circuitmirror outputs
drive the 2-wire port with balanced ac current propor- '
tional to the receive input voltage., Reception gain is
programmed by the RRX resistor.
Since receive input signals are transmitted through
the MC3419-1 to the 2-wire port, and the 2-wire port
signals are returned to the 4-wire transmit output, a
means of cancellation must be provided to maintain
4-wire signal separation (transhybrid rejection). Cancellation is complicated because the gain from the receive port to the transmit port depends on the impedance

*A current mirror is a circuit which behaves as a current controlled
current source. It has a single low-impedance input terminal with respect to a reference pOint and one or more high impedance outputs.

MC3419-1L
2-126

of the subscriber loop. A passive "balance network" is
used to achieve transhybrid rejection by cancelling, at
the low impedance input to the transmit op amp, the
current reflected by the loop impedance to the 4-wire
transmit output. For a resistive loop impedance, a single
resistor provides the cancellation. For reactive loops,
the balance network should be reactive.
Longitudinal (common-mode) currents that may be
present on the subscriber lines are suppressed in the
MC'3'419-1 by two niethods. The first is inherent in the
mirror configuration. Positive-going longitudinal curren,ts into Tip and Ring create comnion-mode voltages
that cause a decreasing current through the Tip Sensing
resistor and an increasing current through the Ring
Sensing resistor~ When these equal and opposite signal
currents are reflected through the A-Circuit mirrors and
summed together at TXO, the total current at TXO remains unchanged. Therefore, the ac currents due to the
common-mode signal are cancelled before reaching the
transmit output.
The second longitudinal suppression method is more
dominant, since it limits the amplitude of commonmode voltages that appear at the Tip and Ring terminals.
A common-mode suppression circuit detects common-mode inputs and drives the loop with balanced
currents to reduce the input amplitude. Subtracting currents from outputs of the A 1 and A2 mirrors produces
a signal current at the CC terminal in response to the
common-mode voltage at Tip and Ring. A transconductance amplifier (C-Circuit) generates a current proportional to the CC terminal voltage which is summed
with the current from the RXI terminal at the inputs of
current mirrors B1 and B2. The weighting and polarity
of the summing networks produce common-mode B1
and B2 mirror output currents at the 2-wire port. The
common-mode input impedance is inversely proportional to the gain oftlle longitudinal suppression circuit.
RC and Cc compensate the common-mode ,feedback
loop. At 60 Hz with typical component values, the 2-wire
common-mode impedance is less than 5 n.
The longitudinal suppression circuit output currents
are generated by modulating dc current fed to the loop
by the B1 and B2 current mirrors. This configuration
avoids the increased power dissipation attributed to
current mode loop drive because dc and longitudinal
currents are not cumulatively sourced to the loop.
However, driving common-mode currents through the
B-circuit current mirrors in this manner limits the longitudinalsuppression capability. The suppression circuit
is unable to reverse 2-wire current polarities to maintain
a low-impedance termination when longitudinal currents exceed the dc, loop current. At low dc loop currents, the common-mode signal capability, known as
, longitudinal capacity, is limited by the loop current (Figure 6). At high-loop currents, longitudinal capacity is
limited by the maximum voltage swing of the CC terminal and is therefore independent of dc loop current.

MOTOROLA COMMUNICATIONS DEVICE DATA

FIGURE 7 - BASIC SLiC CIRCUIT

MDA220

r-----~--~------------------~~----------------------~--------~Gnd
1 Vee
2
VAG 18
EP
17
RXI
BP

r-- --,

TXO

4

ITSI-

...J

a:
>

TSI

5

ee

6

Ring

RSI

POI

HSO 14
TSO

RpR

7

I

SN

8

IL __

EN

16
15

RSO
HST

Hook

13

'------------------_Status
Output

12

' - - - - - - - - - - - - - - - - - - - -__ Tip

Sense

11

'----------------------~~Ring

Sense

VEE 9 10 Vas

RH

RC

'----------------------~--

The hook status control circuit supplies the bias currents to activate the B-Circuit op amps and other sections of the MC3419-1. To activate the bias currents, the
control circuit compares the current through the sense
resistors, RR and RT, and the load resistance RL with
the current through the hook status threshold programming resistor, RH, by using outputs from both A1 and
A2 mirrors. The A 1 mirror output sources current to the
RH resistor. (This reduces all internal currents to near
zero during the on-hook state in order to eliminate unnecessary power consumption.) If this current is large
enough the voltage on the HST pin will trip an internal
comparator, then another circuit compares the current
from the A1 output with that of an A2 output. These
currents must match within ± 15%. If so, HSO will be
activated and the bias circuits will turn on provided the
voltage on PDI is greater than -1.2 V. The HSO pin can
have either a pull-up resistor or a pull-down resistor
and when activated it will switch to VCC (0 volts).
Once the MC3419-1 is powered up, a circuit with a
gain of 20 feeds current to the RH resistor in order to
keep the bias circuitry active. (The sense resistors are
paralleled with the Darlington transistors which reduces

__~--4_----------------------------__ -48V
the sense input currents.) Should the sense input currents drop below one-twentieth of the required powerup current, the bias currents will be removed, forcing
a power-down condition.
Current mode analog signal processing is critically
dependent on voltage to current conversion at the
2-wire and 4-wire inputs. Precise, low-noise voltage
sensing through resistors RT, RR and RRX requires
'quiet, low impedance terminations at terminals TSI, RSI
and RXI respectively. For 2-wire signals, terminal VaB
isolates the loop-sensing resistors and current mirrors
from noise at the high-current VEE terminal. External
filtering from VCC to VaB ("quiet battery" terminal)
ensures loop voltages are sensed without interference
from system supply noise. VEE noise rejection at audio
frequencies is typically 60 dB or greater.
Receive input terminal RXI is referenced to the VAG
terminal which references the 4-wire input to the
"analog ground" ofthe 4-wire signal source, thus isolating the input from power ground voltage transients.
This isolation offers 70 dB of noise rejection at audio
frequencies.

SYSTEM EQUATIONS
K1 - The c,urrent gain from ITSI + IRSI to TXO only
during an off-hook power-up condition. K1 = 0.51 ±
1%.
K2 - The current gain from RXI to the collectors of the
off-chip Darlington transistors only during an off-hook
power-up condition. K2 = 95 ± 1%.

MOTOROLA COMMUNICATIONS DEVICE DATA

For simplicity, the following equations do not use K1
or K2. Instead the actual numerical value is used, for
instance (1 + [2]K1K2) = 1 + 1.02 x 95 = 97.9 is approximately 98.
RL - Loop resistance. This is a load resistance from Tip
to Ring and can be either ac or dc depending on context.

MC3419-1L
2-127

LOOP CURRENT REGULATIONS
FIGURE9!_)

FIGURE8!_)

Gnd

Caa

FIGURE9!b)

FIGURE8!b)
I
130
I
120
110
100
2.0 kn
90
ffi
80
t-5.0k.ll
a::
a::
70
::>
u
1Olkn
60
"0
9 50
2O kn
.d< 40
l
30
20 r-- 39 1kn
10
I
o
10

1
....

1--10
r--.o.

1~

' .'-[\.

.........

a
a::

.'\.

"" ...... ~
-..

rr-

..

~

_-

.d<
..

_-_._- --

...

~
~

100
1.0 k
RL. LOOP RESISTANCE (.11)

100
90
80
70

Standard 400 .11
Feed Resistance
2.23 (1 N53061 ~
1.95 lN5305 ~
1.67 (1 N5303)
1.39 (lN53011
1.12 (lN5298)
0.8411 N5295)
0.56 (lN52911 "

:
40

30
20
10

....

11111
11111
1111

-

130
120
110

10 k

r""==

.--

o

II

1111

100
1.0 k
. RL. LOOP RESISTANCE (.Ill

10

10 k

SYSTEM EQUATIONS (continued)
ZL - Loop impedance. This is used only to connote a
complex impedance loading on Tip and Ring.
IL -

ignoring the effects of RL
R _ IVaaliRR + RT + 1200.11)
F9811Vaal -4.0 V)

Loop current. The dc current flow through RL.

RF - Dc feed resistance. The synthesized resistance
from which battery (Vee and VEE) current is fed to RL.
The battery feed resistance is balanced differential feed.
See Figure 7. (This assumes VaB = VEE.) The first order
equation is:
R _ RR

F-

+ RT + 1200.11
98

(1)

Because of the diode voltage drops on TSI and RSI, the
actual dc feed resistance is higher. The second order
equation is:
R _ IVaal(98 RL + RR + RT + 1200 .11) _ R
F98 (I(Vaal -4.0 V)
L

MC3419-1L
2-128

(2)

(3)

So:

~
R

= R = 49RF (IVaal -4.0 V) _ 600
T
. IVaal

(41

The minimum value for RR and RT is 5.0 kil.
The first order value of RF can not be greater than the
desired value of the termination impedance (usually
600 il or 900 0). To achieve dc feed resistances that are
greater, a resistor can be placed between VaB and VEE
along with a filter capacitor eaB which restores the
desired termination impedance and filters power supply
noise. A diode should also be placed between VaB and
VEE to prevent damage in case a catastrophic power
supply failure occurs.

MOTOROLA COMMUNICATIONS DEVICE DATA

IVOB - This is the current that is sourced from the VOB
pin and is proportional to the currents into and out of
RSI and TSI. When the SLiC is in the off-hook power-up
mode, IVOB is also proportional to IL'
IVOB

= 2.151RSI

+ 0.7 ITSI

(5)
(6)

IVOB = 0.029 IL

RFO - Dc feed resistance. The synthesized resistance
from which battery current is fed to RL, see Figure 8.
(This assumes VOB is tied to VEE through a resistor
ROB.) ROB synthesizes additional dc feed resistance to
the RF value previously stated.
When using ROB, the dc feed is effectively balance fed
from VCC and VOB instead of VEE. The sense resistors
(RR and RT) should be selected to make RF (first order)
less than the termination impedance.
R
_ iVEEi(98RL + RR + RT + 1200 + 2.85ROB)
FO - 9 8 ( i V E E i -4.0 V)

7.0

--"",-'UII'rIUU'

~ g,O I-+-+~f-++--== ",~==-j-+--+-t-1--t--+--l
;:; 8,0
7.0 ,:
0: 6,0
5,0
~4.0
0: 3,0
2,0
1,0

ffi

g

o ,"

200

220
240
260
280
300
320
RH, HOOK STATUS THRESHOLD RESISTANCE (k!l)

340

Figure 11 shows such a graph using 17.4 kO as the
values fO,r RR and RT' Note the oscillatory condition to
the right of the crossing point. Selection of RH in this
region is usually not a problem since the majority of
telephone lines do not fall into this resistance range. RH
always ties to VOB and HST and will give reliable hook
status information regardless of power supply voltages
and PDI.
RO - Termination impedance of the 2-wire port. This
impedance is greater than the dc feed resistance RF
because of a current splitting network in the feedback
loop, RTX1 and RTX2'
K3 - A constant, formed by RTX1 and RTX2, between
o and 1, which determines the ratio of the first order
value of RF to RO'
R _ RR + RT + 1200 il
01 + 97K3

=

CTX

=

K3 RTXl
= -,--::-i(3
-

Zin

RR + RT + 1200 il
. .
7RTX2
The result IS In /LF.

(26)
(27)

GTX - The voltage gain from the 2-wire port to VTX
which is adjustable by RVTX'
G _ 1.02 (1 - K3) RVTX
TX - RR + RT + 1200 il

=

RVTX

GTX(RR + RT + 1200 il)
. 1.02 (1 _ K3)

(28)

(29)

GRX - The voltage gain from the VRX input to the 2wire port which is adjustable by RRX'
G
_
-95 RL (RR + RT + 1200!l)
RX - RRX [(RR + RT + 1200 il) + RL(l + 97K3)]

(30)

G
_ -95 RL RO
RX - RRX(RL + RO)

(31)

R
_
95 RL RO
RX - GRX(RL + RO)

(32)

RRX + RB
CRX > 2", f RRXRB

(33)

RR + RT + 1200 il - RO
97RO

(20)

RTX2 + Zin
RTXl + RTX2 + Zin

(21)

Transhybrid Rejection - The voltage gain from VRX to
VTX. It is expressed in dB, the number should be negative and the larger the value the better. Transhybrid
rejection is achieved by summing a current from the
VRX input (RB) with the TXO current that flows to the
current to voltage converter. RB balances a resistive
load, RL'

=

Zin - The input impedance of the current to voltage
converter op amp. This impedance is usually negligible,
it can be used to sway the selection of a 1% component
,value.

MC3419-1L
2-130

RTX2

Where f is the minimum passband frequency, usually
200 Hz.

and
K3

It is beneficial to make RTX1 as large as possible. Typical
values range from 15 k to 24 kO.

(19)

So:
K3

RTXl < 0.01 IL(max) (RR + RT + 600 il) - IVAGlmax - 3,9 V
0.01 IL(max)
(25)

RB =

RRX(l + 97K3) (RO + RLl
97RL (1-K3)

(34)

MOTOROLA COMMUNICATIONS DEVICE DATA

FIGURE 12 -

BALANCE NETWORK foR CAPACITIVE LINES
CRX

RRX

1+

MJE271
EP

DVRX

VAG

VAG
Rb1

BP
Tip
RXI

CB
TSI
RL

CL

RTXl

+

TXO

RR

RVTX

Rb2

RTX2

RSI

CTX

VTX

Ring
BN

'*:----::r---j EN

FIGURE 13 -

BALANCE NETWORK FOR COMPLEX LOAD IMPEDANCES

MJE271
~'--"':::"~---lEP

VAGr-----l-------l~---._-----1

r ----,

i
RXI~--..

I

:
I

I
I

I
I

I
I
I

'----'I/IIIr----I TSI

RBI

I
I

RVTX

RB2 I
L.: ___
.J

+

RTX2 CTX

...---/VI/I,.----IRSI

VTX

To scale Zb to its maximum values
BN

'I:::---::r---jEN

R
- R
- RRX (1 + 97K3)
b1 - b2 194 (1 - K3)

(35)

Zb = .!!itl.(ZLl
2RO

(36)

When the 2-wire port has a parallel Rand C load, then
(see Figure 12):
RRX(RR + RT + 12000)
97RL (1 - K3)

(37)

R
_ RRX(RR + RT + 12000)
b2 97RO(1 - K3)

(38)

C _ RLCL
b - Rb2

(39)

Rb1 =

When it is desirable to balance complex load imped-

MOTOROLA COMMUNICATIONS DEVICE DATA

RORRX(1 + 97K3)
97(1 - K3)

(40)

R
- RRX(1 + 97K3) _ R
b2 97(1 _ K3)
b1

(41)

Zb = ZL

(42)

Rb1 and Rb2 values are interchangeable.

MC3419-1L
2-131

SYSTEM EQUATIONS (continued)
The Tip and Ring Sense Output currents are proportional to the currents out of and into TSI and RSI,
respectively.

= ITSI

(43)

IRSO = IRSI
6

(44)

_ IVTic - vecl -2.0 V
.
ITSO 6 (RT + 600!l)
for VTlp < Vee

(45)

_ IVRing - vaBI -2.0 V
.
IRSO 6(RR + 600!l)
for VR,ng > VaB

(46)

ITSO

6

Figure 15 is an application circuit showing solid state
ringing insertion using an MOC3030 zero-crossing detector optocoupled triac to replace the conventional
electromechanical relay. This device inserts the ringing
signal on a zero voltage crossing which eliminates noise
in adjacent cable pairs and removes the signal on a zero
current crossing which eliminates inductive voltage
spikes that commonly destroy relay contacts. The ring'
ing generator provides a continuous 40 V to 120 V RMS
signal from 15 to 66 Hz superimposed upon
-48 Vdc.Ringing cadencing is inserted with the Ring
Enable Input. The 2N6558 and MPSA42 replace the
MJE270 for systems that use ringing generator voltages
greater than 70 VRMS' The MDA220 diode bridge is
replaced with a series 1N4007 on the Tip lead and a
shunting ,1N4004 to VEE and to allow ringing voltage

Digital interfacing to the MC3419-1 PDI pin and the
HSO pin is shown in Figures 14a, 14b and 14c.lfthe PDI
pin is not used it should be terminated to VCC and if
HSO is not used, it can be left open.

FIGURE 14 -INTERFACE-TO-DIGITAL LOGIC

+5.0V
10 k VOO
POI

-12V

HSO

MC3419
VEE

L---;:=--...l

62
k.
POI

-48V

-12V

HSO

MC3419-1
750 k

VEE

(a)

-48 V

Interface-to-Negative
Supply CMOS Logic

(b)

Interface-to-LSTTL

+12 V

+12V_---,
62 k
MC14xxx

k!l
VCC

':'

POI

':'

HSO

MC3419-1
1.0 M!l

-48V
(c)

Interface-to-Positive Supply CMOS Logic

MC3419·1L
2·132

MOTOROLA COMMUNICATIONS DEVICE DATA

s::

~

FIGURE 15 - PBX LINE CIRCUIT

~

>

o

REl

o
s::
s::
c:

MPSA56

Logic Power

z

RE2

~

RGl

o

oz

Ring Enable
Ringing Generator

i ___
~ Ji
L

en

r------~

I

c

1

1

RHSO

~

om

I

1

I

~_~~!. __ J

1

RRT

,

C

Hook Status
Output

~
»

GroundVcc

1

VCC
Analog Ground

RRX
] }

Receive Input

-I BP

Tip

RTXl

I

:
--.A,N\r--

RpR

•

lN4007

~I
1N4007

I! ~

! l 2Nt

*' !

I""

"."~]

6558

T

MK1 V
135

i

I
,

....L..

n::1

RTX2
RVTX

1 'I

!j

RH

LI------r~
lN4004

COB

9 VEE
VOB

I
I

Transmit Output

i

-1E-.,,

.
J~------~L-------------------

,

....L..

¢lN5303

L
' _______ •
s:

~

....

1\)'"

'CD

W'"

WI""

1

- - - -

I

Indicates Optional Components

Negative Battery

SYSTEM EQUATIONS (continued)
on the Ring lead to exceed the power supply voltages,
a 1N4007 and an MK1V-135 (Sidac) are used for protection. The forward voltage drop across the 1N4007,
during normal operation, will not affect the parametric
characteristics of the MC3419-1 since it is "inside" a
feedback circuit. If the MJE270 is used, the MK1V-135
should be replaced with a lower voltage Sidac or
MO'sorb transient suppressor.
An optocoupled trans.istor circuit is used for ring trip
detection on long lines. It samples only the ac and dc
ringing signal current and uses a simple one pole filter
to eliminate the low level ac signal. Under worst case
conditions this circuit will ring trip in 1V. to 4 cycles. In

systems serving only short loops «700 0), if RG1 and
RG2 are 620 0 or greater, the optotransistor circuit is
not needed, the Hook Status Output will perform ring
trip on a Zero Crossing. The Ring Enable input and the
Hook Status Output interface with standard CMOS and
TTL logic.
The op arrip in this circuit is an integral part of the
following codecs, filters or combos:
MC3417/B - MC145414
MC14404/6n - MC14413/4
MC14401/2/3/5

LONG LINES OFF-PREMISE LINES
Specifications
RF
IL(maxl

- 200n
-60mA

RO
RX Gain

-

RL(maxl

-

TX Gain

-

1900n

600n
Ode
200-3400 Hz
Ode
200-3400 Hz

Off-Hook
On-Hook

-

<2500n
>10 kn

VLogic
VEE

-

Protection

-

1000 V

VRinging

-

+5.0V
-42 to -56
Volts
(40 V to 120
VRMSI+VEE

Ringer Equivalent.- 5

Parts Ust
MPSA56
2N3905
2N6558
MPSA42
MJE271
1N4007
MK1V135
1N4007
1N4007
1N5303
1N4004
MC3419-1

RR
RT
RpT
RpR
Rm
RG2
RE1
RE2
RRT
RC
.RH
RHSO

9.09 k
1% Matched
9.09 k
1% if desired
47 n
5%
75n
5%
620n
5%
100n 5%
91 n
5%
3.0 k
5%
20 k
5%
24 k
5%
127 k 1-3%
10 k
5%

MOC3030
4N25

RTX1
RTS2
RRX
Re
RVTX
CT
CR
Cc
CRX
CTX
CRT
Cae

12.1 k
1%
5.76 k
1%
28.7 k
1%
28.0 k
10/0
28.S k
1%
0.004 p.F
0.004 p.F
0.001 p.F
1.0 p.F/20 V
2.0 p.F/4O V
20 p.F/5.0 V
10 p.F/60 V

SHORT LINES ON-PREMISE LINES
Specifications
500n
700n
<50 ms
2.5
600 n

RF
RL(maxl
Ring Trip
Ringer Equivalent
RO

Parts Ust
MJE271
MJE270
MPSA56
2N3905
1N4007
1N4007

MC3419~1L

2-134

-5.0 de
Ode
+5.0 Volts
-20 to -56 Volts
(40 V to 70 VRMSI + VEE

RX Gain
TX Gain
VLogic
VEE
VRinging

MOC3030
RR
RT
RG1
RG2
RE1
RE2

19.6 k
19.6 k
620 n
620n
91 n
3.0 k

1%
1%
5%
5%
5%
5%

CT
CR
Cc
CRX
CTX

0.004
0.004
0.004
0.1
0.5

p.F
p.F
p.F
p.F
p.F

RHSO
RTX1
RTX2
RRX
Re
RVTX
RC

10
19.6
42.2
69.8
301
127
56

k
k
k
k
k
k
k

5%
1%
1%
1%
1%
1%
5%

MOTOROLA COMMUNICATIONS DEVICE DATA

MOTOROLA

MC13055

SEMICONDUCTOR-----TECHNICAL DATA

Advance Information
Wideband FSK Receiver

WIDEBAND
FSK
RECEIVER

The MC13055 is intended fo RF data link systems using carrier frequencies up
to 40 MHz and FSK (frequency shift keying) data rates up to 2.0 M Baud
(1.0 MHz). This design is similar to the MC3356, except that it does not include
the oscillator/mixer. The IF bandwidth has been increased and the detector output
has been revised to a balanced configuration. The received signal strength
metering circuit has been retained, as has the versatile data slicer/comparator.
• Input Sensitivity 20 IlV @ 40 MHz
• Signal Strength Indicator Linear Over 3 Decades
• Available in Surface Mount Package
• Easy Application, Few Peripheral Components

MONOLITHIC SILICON
INTEGRATED CIRCUIT

".

PSUFFIX

1

PLASTIC PACKAGE
CASE 648

DSUFFIX
PLASTIC PACKAGE
CASE 751B

Figure 1. Block Diagram and Application Circuit

(SO-16)

PIN CONNECTIONS
Squelch
Adjust
(meter)

Comparator Gnd 1
Comparator Vcc 2
IF Ground

3

IFVCC

4

LimHer Input 5
Limiter Bias { :
QuadBias

B

13 Carrier Detect

Meter Drive

2
11 }

o

Detector
Out

9

Quad Input

L2

This document contains Information on a new product. Specifications and Information herein are subject to change without notice.

MOTOROLA COMMUNICATIONS DEVICE DATA

MC13055
2·135

MAXIMUM RATINGS
Rating

Symbol

Value

Unit

VCC(max)
V2,V4

15

Vdc

3.0 to 12

Vdc

Junction Temperature

TJ

150

°C

Operating Ambient Temperature Range

TA

-4010+85

°C

Tstg

-65 to +150

°C

Po

1.25

W

Power Supply Voltage
Operating Supply Voltage Range

Storage Temperature Range
Power Dissipation, Package Rating

ELECTRICAL CHARACTERISTICS (VCC = 5.0 Vdc, 10 = 40 MHz, lmod = 1.0 MHz, .1.1 = ±1.0 MHz, TA = 25°C, test circuit 01 Figure 2.)
Characteristics

Measure

Min

Typ

Max

12+14

20

25

10

-

mA

7.0

9.0

IlAIdB

1.3

Data Comparator Pull-Down Current

116

-

Meter Drive Slope versus Input

112

4.5

Total Drain Current

Carrier Detect Pull-Down Current

113

Carrier Detect Pull-Up Current

113

-

500

-

Carrier Detect Threshold Voltage

V12

700

800

900

DC Output Current

110,111
V10-V11

-

430

Recovered Signal

350

-

Sensitivity lor 20 dBS + NIN, BW = 5.0 MHz
S + NIN atVln= 50 I1V
Input Impedance

@

40 MHz

-"

VIN

-

20

V10-V11

-

30

Pin 5, Ground

Rin
Cin

Quadrature Coil Loading

Pln9108

Rin
Cin

4.2
4.5
7.6
5.2

Unit
"mAO

mA

I1A
mV
I1A
mVrms
I1Vrms
dB
kll
pF
kQ

pF

Figure 2. Test Circuit

100pF

H>--+---+---o Carrier
Detect Output
H>---f----+---o Meter Drive
Detector
K>--_.......-+--.() Output
3.9k

Colis - Shielded
Coilcrait UNI-10/142
L1 Gray 8·112 Turns, nominal 300 nH
L2 Black 10-112 Turns, nominal 380 nH

39pF

r

------

.,

I
I
IL _ _ _ _ _ _ _ _ .JI

MC13055
2-136

3.9k

or
TOKO Series E526HNA
L1 Part No.1 00301
L2 Part No.1 00079

MOTOROLA COMMUNICATIONS DEVICE DATA

Figure 3. Overall Gain, Noise, AM Rejection

--

0

/'

m -to

:8-

Figure 4. Meter Current versus Signal

Outputfmod = 1.0 MHz f-f-al=t.OMHz

~ 600
0-

~ -20

~

zUJ

.....

/

'"'

-6 0

0

a: 300
UJ

"

t:u

::E
~-

/

I

"

-80

-tOO

Figure 5. Untuned Input: Limiting Sensitivity
versus Frequency

E

'"

:8- -to

~

'enzt::"

r-

-30

5

7

~ -90
-tOO

_V

o

to

20

ffi
a:
a:
o
a:

f...- ~

V

01

.~

tij

::E

~

30

40

50

60

70

80

90

tOO

to

20

30

~

1

0
'"
t:: -5
en
~-60

/

'"

z
~ -70

1\ I

::J

''\

~-8 0

Limiting
Sensitivity

~

1 1 1
1 1

~-90
t.O

3.0

5.0
7.0
9.0
tt
VCC. SUPPLY VOLTAGE (Vdc)

50

60

70

80

90

tOO

Figure 8. Detector Current and Power Supply
Current versus Supply Voltage

403
1--1- 40.2
40.t
-I-40.06
39.9 ~
39.B ~
39.7...J
39.68
39.5 ~
::>
I..39.40
39.3
39.2

Quadrature
Coil Tuning

40 MHz

40

I. INPUT FREQUENCY (MHz)

Figure 7. Limiting Sensitivity and Detuning
versus Supply Voltage
~-40

20k
8

::>

I. INPUT FREQUENCY (MHz)

E

9

MCl3055
7

V

I -V

51

::L

20k

8

~ -50
E

~ -60
~ -70
~ -80

5

;;: 70G InputOd8m -+_+_1--t_lnp~o-ltEP

O.l~

~ -40 I--

o

-20

-60
-40
INPUT SIGNAL (dBm)

Figure 6. Untuned Input: Meter Current
versus Frequency
800r---r--,---,--,--r---::-:---------,

9
MC13055

51

r-

-80

0.1

0.1
Inp~o-l

-20 I--

~

h

o

-20

-60
-40
SIGNAL INPUT (dBm)

t2V

LL
V"/

200
tOO

7'-..

.-- 3.0V

~
.L,j ~

::>

" " /--..
""
I'J'

-tOO

./..
L~

a: 400
a:

I
" Noise
~ -30
....
/
>
-4o /
"
UJ
~ AMRt.OkHz
a:
-5 01-30%

g

VCC = 5.0 V. 7.0 V

500

¥

.....

t3

MOTOROLA COMMUNICATIONS DEViCE DATA

t5

t200
~
::; tooo
0'

~r

0-

z
UJ
a:
a:

::>

I-

BOO

~~

0

a:

§
UJ

t:u

400

-+

200

~

.§.

.... r-

L V

600

0

60;;:

~
~ rltO + Itt

I.......

.....

....

./

o t.O

:::;

30 !!5
en
a:

~:4

20~
~
to :£

I

o

50 !z
UJ
a:
a:
40 13

1/

+

3.0

5.0
7.0
9.0
tt
Vcc. SUPPLY VOLTAGE (Vdc)

t3

t5

o

~

MC13055
2-137

Figure 9. Recovered Audio versus Temperature

Figure 10. Carrier Detect Threshold versus Temperature
:[ 1000

~ 4.0

~

- -

2.0
::::>
0

a

~

Q -2.0

o

~ -4.0
w
~ -13.0

::a

a:o

--

"

9

~

I--

900

1' ....

....... I'-...

~ 800

t;

~

700

r--...... ......
r-....

i"'"'-

......

a:

-13.0
-10

....

w

ii:

~

:; -12

600

N

-130

-40

-20

0
20
40
60
80 100
TA. AMBIENT TEMPERATURE (Oe)

120

:; 500
-130

140

Figure 11. Meter Current versus Temperature
600

~

-10
500

z>-w

a: 400
a:
::::>
u
a:
w 300

~

V

tu

".

~~O-

I--.
-40

-li0

200

~

l..--~

100
-130 -40

......
"""'"

-130

..........

0 2 0 4 0 6 0 8 0 100
TA. AMBIENTTEMPERATURE (Oe)

120

140

Figure 12. Input Limiting versus Temperature

lIiDutO~Bm
-20

-20

E

~ -50

~

>

~

5j

~~

- -

~

::;;

~

h
~

-40

"

.......

~~

......

.~

~ -70

.~

E

::;;

~~

........ ..:,... t....... ' ........
...... ..... r1'';:
.... .,:

-20
0
20
40
60 80
TA. AMBIENTTEMPERATURE (Oe)

-130

m

en

1'....

100

::::i

~
~

- .....

120

r-- I'-80

:Z -90

-

,.-

;'
,.~

:>

-130 -40 -20

140

0
20
40
60
80 100
TA. AMBIENTTEMPERATURE (Oe)

120

140

Figure 13. Input Impedance, Pin 5
1.0

1.0

MC13055
2-138

MOTOROLA COMMUNICATIONS DEVICE DATA

Figure 14. Test Fixture (Component Layout)

1+-1-- - - - - - --------1-1
4"

(Circuit Side View)

4"

1+-1-- ---4,,------t-1
MOTOROLA COMMUNICATIONS DEVICE DATA

MC13055
2-139

"'3:
.!on
-""

....

Om

Figure 15. Intemal Schematic
2

~

3t~~
~

~

"~Tl

.~ ~
M

oJ_ ('

~

H> 13

93,.J§..

M·. .
70

fIT

..,...

~

~

s.r

Y~"

-<

~

92

91

93

~r

T

-'

14

8~182
1
15
.~ 8

9

~

46

65

0-

3:

~
o

-~~~ttJ;jlt~l'

~

z

o
~

5z

en

o

~
om
o

:!:i
l>

=

~~~~

,

~

e
c

,,28

~

28

:D

3:

....25

.,.....

s'Q1

?

-1 H~ H"1
...... 58

~

~57
~

...... 56

~55

~

,..-I

...... 54
,..A

27

1""29

l...!
46
";2

;;r

2B

~

;;r

38

~
10

)

11

48

¢

";1

~r"'50

49

GENERAL DESCRIPTION
The MC13055 Is an extended frequency range FM IF,
quadrature detector, signal strength detector and data shapero
It is intended primarily for FSK data systems. The design is
very similar to MC3356 except that the oscillator/mixer has
been removed, and the frequency capability ofthe IF has been
raised about 2:1. The detector output configuration has been
changed to a balanced, open-collector type to permit
symmetrical drive of the data shaper (comparator). Meterdrive
and squelch features have been retained.
The limiting IF is a high frequency type, capable of being
operated up to 100 MHz. It is expected to be used at 40 MHz
in most cases. The quadrature detector is internally coupled
to the IF, and a 2.0 pF quadrature capacitor is Internally
provided. The 20 dB quieting sensitivity is approximately
20 !lV, tuned input, and the IF can accept Signals up to
220 mVrms without distortion or change of detector quiescent
, DC level.
The IF is unusual in that each of the last 5 stages of the 6
stage limiter contains a signal strength sensitive, current
sinking device. These are parallel connected and buffered to

MOTOROLA COMMUNICATIONS DEVICE DATA

produce a signal strength meter drive which is fairly linear for
IF input signals of 20!lV to 20 mVrms. (See Figure 4.)
A simple squelch arrangement is provided whereby the
meter current flowing through the meter load resistance flips
a comparator at about 0.8 Vdc above ground. The signal
strength at which this occurs can be adjusted by changing the
meter load resistor. The comparator (+) input and output are
available to permit control of hysteresis. Good positive action
can be obtained for IF input signals of above 20 !lVrms. A
resistor (R) from Pin 13 to Pin 12 will provide Vce/R of
feedback current. This current can be correlated to an amount
of signal strength hysteresis by using Figure 4.
The squelch is internally connected to the data shapero
Squelch causes the data shaper to produce a high (Vec)
output.
The data shaper is a complete "floating" comparator, with
diodes across its inputs. The outputs of the quadrature
detector can be fed directly to either or preferably both inputs
of the comparator to produce a squared output swinging from
Vce to ground in inverted or noninverted form.

MC13055
2-141

MC13135
MC13136

MOTOROLA

SEMICONDUCTOR·-----TECHNICAL DATA

DUAL CONVERSION
NARROWBAND
FM RECEIVERS

Advance Information
FM Communications Receivers
The MC131351MC13136 are the second generation of single chip, dual
conversion FM communications receivers developed by Motorola. Major
improvements in signal handling, RSSI and first oscillator operation have been
made. In addition, recovered audio distortion and audio drive have improved.
Using Motorola's MOSAICTM 1.5 process, these. receivers offer low noise, high
gain and stability over a wide operating voltage range.
Both the MC13135 and MC13136 include a Colpitts oscillator, VCO tuning
diode, low noise first and second mixer and LO, high gain limiting IF, and RSSI.
The MC13135 is designed for use with an LC quadrature detector and has an
uncommitted op amp that can be used either for an RSSI buffer or as. a data
comparator. The MC13136 can be used with either a ceramic discriminator or an
LC quad coil and the op amp Is internally connected for a voltage buffered RSSI
output.
These devices can be used as stand-alone VHF receivers or as the lower IF
of a triple conversion system. Applications include cordless telephones, short
range data links, walkie-talkies, low cost land mobile, amateur radio receivers,
baby monitors and scanners.
• Complete Dual Conversion FM Receiver - Antenna Input to Audio Output

SILICON MONOLITHIC
INTEGRATED CIRCUIT

PSUFFIX
PLASTIC PACKAGE
CASE 724

DWSUFFIX
PLASTIC PACKAGE
CASE 751E
(SO·24L)
ORDERING INFORMATION

• Voltage Buffered RSSI with 70 dB of Usable Range
Device

• Low Voltage Operation - 2.0 to 6.0 Vdc (2 Cell NiCad Supply)
• Low Current Drain - 3.5 mA Typ

MC13135P

• Low Impedance Audio Output < 25 n

MC13135DW

• VHF Colpitts First LO for Crystal or VCO Operation

MC13136P

• Isolated Tuning Diode

MC13136DW

Temperature
Range

Package
Plastic DIP

- 40· to +85·C

S0-24L
Plastic DIP
SO-24L

• Buffered First LO Output to Drive CMOS PLL Synthesizer
PIN CONNECTIONS

MC13135

lsi LO Basa
lslLO Emmer

1 I--,;I-I:>lr--,

YaricapC

lSi LO Base

2

YaricapA

IstLOEmllter

MC13136

1 1-....::;:jL...{~--,

VaricapC

2

YaricapA

lsi Mixer In 1

1st Mixer In 1

2nd LO Eniuer

5

2nd LO Base nefl----'::l-l>-'
2nd Mixer Out

1st MixerOut

Vcc2

71---0---1

5

lsi MixarOut

2nd LO Base

eiil---':I-I>--' )(1

vcc2

2nd MixerOUI

7l---<:J----I

2nd LO Emmer

Audio Out
Buffered ASSI Outpul

OpAmpOul
Decouple 1

RSSI

OpAmpln-

Decoupla 1

OpAmpln+

Decoupla 2

Quad Coil

11

~--t-t::=

UmHerOUtput
Quadlnpul

this document contains information on a new product. Specifications and information herein are subject to change without notice.

MC1313S.MC13136
2-142

MOTOROLA COMMUNICATIONS DEVICE DATA

MAXIMUM RATINGS
Rating
Power Supply Voltage
RF Input Voltage

22

Junction Temperature

-

Storage Temperature Range

Symbol

Value

VCC (max)

6.5

Vdc

RFln

1.0

Vrms

TJ

+150

·C

Tstg

-65to+150

·C

Unit

Pin
4,19

Unit

RECOMMENDED OPERATING CONDITIONS
Rating
Power Supply Voltage
Maximum 1st IF
Maximum 2nd IF
Ambient Temperature Range

Pin

Symbol

Value

4,19

VCC

2.0 to 6.0

Vdc

flF1

21

MHz

flF2

3.0

MHz

TA

-40to+85

·C

-

ELECTRICAL CHARACTERISTICS (TA=25·C, VCC=4.0Vdc, fo=49.7MHz,fMOD= 1.0kHz, Deviation=±3.0kHz, f1stLO=39MHz, f2nd
LO= 10.245 MHz, IF1 = 10.7 MHz, IF2= 455 kHz, unless otherwise noted. All measurements performed in the testcircuitof Figure 1.)
Condition

Symbol

No Input Signal

ICC

Sensitivity (Input for 12 dB SINAD)

Matched Input

VSIN

Recovered Audio
MC13135
MC13136

VRF= 1.0mV

AFO

Characteristic
Total Drain Current

limiter Output Level
(Pin 14, MC13136)

VLlM

Min

Typ

Max

Unit

-

4.0

6.0

mAde

1.0

-

I1Vrms
mVrms

170
215

220
265

270
315

130

100

-

mVrms

1st Mixer Conversion Gain

VRF=-40dBm

MXgaln1

2nd Mixer Conversion Gain

VRF=-40dBm

MXgain2

First LO Buffered Output

-

VLO

Total Harmonic Distortion

VRF=-30dBm

THO

-

1.2

3.0

%

Demodulator Bandwidth

-

BW

-

50

kHz

RSSI

-

70

-

RSSI Dynamic Range
First Mixer 3rd Order Intercept
(Input)
Second Mixer 3rd Order
Intercept (RF Input)
First LO Buffer Output Resistance
First Mixer Parallel Input Resistance
First Mixer Parallel Input Capacitance
First Mixer Output Impedance
Second Mixer Input Impedance
Second Mixer Output Impedance
Detector Output Impedance

MOTOROLA COMMUNICATIONS DEVICE DATA

TOIMix1
Matched
Unmatched
Matched
Input

-

TOIMix2

12
13

-

-17

-

-27

-11

-

RLO

-

-

R
C

-

722

ZO

-

330

ZO

-

40
1.8

-

ZO

-

25

-

ZI

3.3

dB
dB
mVrms

dB
dBm

dBm
0
0
pF
0
kO
kO
0

MC13135.MC13136
2-143

TEST CIRCUIT INFORMATION
Although the MC13136 can be operated with a ceramic
discriminator, the recovered audio measurements for both the
MC13135 and MC13136 are made with an LC quadrature
detector. The typical recovered audio will depend on the
external circuit; either the Q of the quad coil, or the RC
matching network for the ceramic discriminator. On the
MC13136, an external capacitor between Pins 13 and 14 can
be used with a quad coil for slightly higher recovered audio.

See Figures 10 through 13 for additional information.
Since adding a matching circuit to the RF input increases the
signal level to the mixer, the third order intercept (TOI) point is
better with an unmatched input (50 Q from Pin 21 to Pin 22).
Typical values for both have been included in the Electrical
Characterization Table. TOI measurements were taken at the
pins with a high impedance probe/spectrum analyzer system.
The first mixer input impedance was measured at the pin with a
network analyzer.

Figure 1a. MC13135 Test Circuit
Vcc

r-------.-~-----I

1

11

JO.1

241
varicap~

~

1
22 1
0.001
I+-----~-__l~ 62pF
0.2~H

1.0k

J:-::::---<
1BOp
*0.Q1 ':' I':'

RF
Inpul

L--------=.:...r-----., Ceramic
RHer
10.7MHz

360

39k

0.1~

0.1

*

14 1

1
1

L ___ --=_ _________ ...1

Rgure 1b. MC13136 Quad De1ectorTestCircuit
VCC

39k

0.1 ~

1
1

13

1

L _______I..._-_--<_..._---''-t-------1~rvv-.......,

MC1313S.MC13136

2-144

MOTOROLA COMMUNICATIONS DEVICE DATA

Figure 3. RSSI Output versus RF Input

Figure 2. Supply Current versus Supply Voltage
1400

6.0

<§.
!z
w

5.0
4.0

a:
a:

::::l

{;)

~
""-

::::l

~

2.0

/

{;)

.E 1.0

o

S

I

- -

RFin = 49.7 MHz
'MOD = 1.0 kHz
'OE~ = ± 3.0 ,kHz

1.0

2.0

3.0

4.0

5.0

6.0

~ 1000

i!:;
§

-

~ 400

7.0

~
~

10

~

5.0

;;
::;

fil
Ii.

{;)

-120

-100

-88

-40

-60

Figure 5. Oscillator Frequency
versus Varactor Bias

10

a

--

RLsoJ -

8.0

~

47.5

ill ¥

47.0

6.0 a:

;;;.

4.0 _

::::l

~

>-

gw

46.5

~

46.0

"-

2.0 ;;
R~f=IS0MH2

1.0

1.5

2.0

2.5

3.0

3.5

o

4.0

v~

en

-"-~

-20

48.0

w
"""

{;)

C~f=SOMHz

0.5

-140

Figure 4. Varactor Capacitance, Resistance
versus Bias Voltage

K

o

/

~

200

8.0

25

15

,/

600

/'

-

V

RF INPUT (dBm)

z

u::l

'MOD = 1.0 kHz
'OEV = ± 3.0 kHz

800

in

{;)

C3

VCC=4.0V

f---- RFin = 49.67 MHz

Vcc, SUPPLY VOLTAGE (V)

g 20 ~ c~LsOMHl
...... ' ~
w

--

~

.1:;

V

o

u:-

----

3.0

I--- ~

_1200

45.5

~

/

/'

/

1

sooJ~~o .~
1
2

27p

-

0.61J.lH

24

V,neap

,fs~
R..

1.0MQ

~ O.2J.lF

VB

S.Op ~

45.0
1.0

Ii.

a:

2.0

3.0

4.0

5.0

VB, VARACTOR BIAS VOLTAGE, VPin24 to VPin 23 (Vdc)

VB, VARACTOR BIAS VOLTAGE (Vdc)

Figure 6. Signal Levels versus RF Input

Figure 7. Signal + Noise, Noise, and
AM Rejection versus Input Power

30.---,---,---,---,---,----,---,---,

6.0

10
S+N

m

-10

a:

~ -20
~

~ ~0r---1----+--~~~~~~~~~--+---~

z-40

~ -10r---~---+--~~--+----+~~r.7~~'-~
~

w

-50 1---t-~h""¥'"7"9----+----+----+---i

-00

-00

-M

-00

-00

-40

RFin, RF INPUT (dBm)

MOTOROLA COMMUNICATIONS DEVICE DATA

-M

-W

'" -30
~

...........

'""-

~

VCC =4.0 Vdc
f-50 f- RFin = 49.67 MHz
-60 r- 'MOD = 1.0 kHz
'OEV = ± 3.0 kHz
-70
-130
-90
-110

S + N 30% AM

'"

~N

-70

-50

-30

RFin, RF INPUT (dBm)

MC13135.MC13136
2-145

Figure 9. First Mixer Third Order Intermodulation
(Unmatched Input)

Figure 8. Op Amp Gain and Phase
versus Frequency
50
30

120

i'

Phase

Gain....

m 10

:2.

~

;f

\

........

z

iE
w
~

160

\

'"e.w
w

//

m

./

:2.-20
I-

:::>

a.

'":I: !3-40
0
Desired Producy V
w
'"'"w :::;;~-60
V~
./
-SO
....
",
c(

to-

-10

20

80

i"""'r-.

to-

200 a.

_1\

./ / J

I ~rdOrder

~

0

-30

\

-50
10k

lOOk

loOM

240

-100
-100

260

10M

Figure 10. Recovered Audio versus
Deviation for MC13135

Figure 11. Distortion versus
Deviation for MC13135

13

_

6.0

'"g

5.0

R=68kn

z

a:::;; 4.0

1000

~

~

~
C

~

-

S.O

~
z 7.0

R=68kn

a

~

I
-20

RF INPUT (dBm)

c

1

I
-4S

" FREQUENCY (Hz)

~00r-~----~------'--------r-------'

~
.§.1500

Intermod
Products

-60

-SO

4
t.--

~

;§
~~~~~~~---1--------+--------4

~

3.0

~

6

:I:
I-

±3.0

±5.0

±7.0

±9.0

±3.0

±5.0

±9.0

±7.0

'DEV, DEVIATION (kHz)

'DEV, DEVIATION (kHz)

Figure 12. Recovered Audio versus
Deviation for MC13136

Figure 13. Distortion versus
Deviation for MC13136

1000,..-,----,.,..------,r----,---,------,
ISOO

a

C

~
aw
~

w

~
~

~ 200 i-=""",-t"'R'-= 1.2 kfI --+---t---~--l

C=100pF
O~--~----~--~----~--~--~

±U

±U

±M

±M

±n

'DEV, DEVIATION (kHz)

MC1313S.MC13136
2-146

±M

±M

O~--~----~--~----~--~--~

±U

±U

±M

±M

±n

±M

±M

'DEV, DEVIATION (kHz)

MOTOROLA COMMUNICATIONS DEVICE DATA

CIRCUIT DESCRIPTION
The MC 13135/13136 are complete dual conversion
receivers. They include two local oscillators, two mixers, a
limiting IF amplifier and detector, and an op amp. Both provide
a voltage buffered RSSI with 70 dB of usable range, isolated
tuning diode and buffered LO output for PLL operation, and a
separate VCC pin for the first mixer and LO. Improvements
have been made in the temperature performance of both the
recovered audio and the RSSI.

Vee
Two separate VCC lines enable the first LO and mixer to
continue running while the rest of the circuit is powered down.
They also isolate the RF from the rest of the internal circuit.
Local Oscillators
The local oscillators are grounded collector Colpitts, which
can be easily crystal-controlled or VCO controlled with the
on-board varactor and external PLL. The first LO transistor is
internally biased, but the emitter is pinned-out and IQ can be
increased for high frequency or VCO operation. The collector is
not pinned out, so for crystal operation, the LO is generally
limited to 3rd overtone crystal frequencies; typically around 60
MHz. For higher frequency operation, the LO can be provided
extemally as shown in Figure 16.
Buffer
The buffer on the 1st LO output converts the single-ended
LO output to a differential signal to drive the mixer. Capacitive
coupling between the LO and buffer minimizes the effects of
the change in oscillator current on the mixer. The buffered LO
output is pinned-out for use with a PLL, with a typical output
voltage of 320 mVp-p at VCC =4.0 V and with a 5.1 k resistor
from Pin 3 to ground. As seen in Figure 14, the buffered LO
output varies with the supply voltage and a smaller external
resistor may be needed for low voltage operation. The LO
buffer operates up to 60 MHz, typically.
Figure 14. Buffered LO Output Voltage
versus Supply Voltage
600

400
300
200

---I

RPin3 =3.0 kG

500

.........-

/
./
V
I-""

100
2.5

--

...... ~

~

'"R;,in3 =5.1 kG

Mixers
The first and second mixer are of similar design. Both are
double balanced to suppress the LO and input frequencies to
give only the sum and difference frequencies out. This
configuration typically provides 40 to 60 dB of LO suppression.
New design techniques provide improved mixer linearity and
third order intercept without increased noise. The gain on the
output of the 1st mixer starts to roll off at about 20 MHz, so this
receiver could be used with a 21 MHz first IF. It is designed for
use with a ceramic filter, with an output impedance of 330 Q. A
series resistor can be used to raise the impedance for use with
a crystal filter, which typically has an input impedance of 4.0
kQ. The second mixer input impedance is approximately 4.0
kQ; it requires an external 360 G parallel resistor for use with a
standard ceramic filter.
Limiting IF Amplifier and Detector
The limiter has approximately 110 dB of gain, which starts
rolling off at 2.0 MHz. Although not designed for wideband
operation, the bandwidth of the audio frequency amplifier has
been widened to 50 kHz, which gives less phase shift and
enables the receiver to run at higher data rates. However, care
should be taken not to exceed the bandwidth allowed by local
regulations.
The MC13135 is designed for use with an LC quadrature
detector, and does not have sufficient drive to be used with a
ceramic discriminator. The MC13136 was designed to use a
ceramic diSCriminator, but can also be run with an LC quad coil,
as mentioned in the Test Circuit Information section. The data
shown in Figures 12 and 13 was taken using a muRata
FX2577 ceramic discriminator which has been specially
matched to the MC13136. Both the choice of discriminators
and the external matching circuit will affect the distortion and
recovered audio.
RSSVOpAmp
The Received Signal Strength Indicator (RSSI) on the
MC13135/13136 has about 70 dB of range. The resistor
needed to translate the RSSI current to a voltage output has
been included on the internal circuit, which gives it a tighter
tolerance. A temperature compensated reference current also
improves the RSSI accuracy over temperature. On the
MC13136, the op amp on board is connected to the output to
provide a voltage buffered RSSI. On the MC13135, the op amp
is not connected internally and can be used for the RSSI or as
a data slicer (see Figures 17c and 20b).

~

3.0

3.5

4.0

4.5

5.0

5.5

Vee, SUPPLY VOLTAGE (Vdc)

MOTOROLA COMMUNICATIONS DEVICE DATA

MC1313S.MC13136

2-147

Figure 15. PLL Controlled Narrowband FM Receiver at 46149 MHz

MC13135

Vee

*0.1
Va~cap

2.71<
47k

0.001

22

1
31~

21

0.2ItH

0.01*
OSC
Oul

OSC
In

01
02

Anl
POl
PD2
LO

3.0p

"'

150PF ( Input

":"

":"

Ceramic
Filler
10.7 MHz
*0.1
360

18

An2
MCl45166

Recovered ",".
dio
10
0.1

Umiler
10k

11

12
0.1*

RSSI
Output
14
13

Figure 16.144 MHz Single Channel Application Circuit
1.t LO External Oscillator Circuit
vee

15k

Preamp for MC13135 at 144.455 MHz
Vee

*

1.0!1F

Ll

12p

lOOp

470

MC1313S.MC13136
2-148

01- MPS517B
Xl- 44.4B5MHz3rdOvertone
Se~es Resonant Crystal
L1- 0.07111H Inductor
(146-02508)

01- MPS5179
L2- 0.05!1H
L3- 0.0711H

MOTOROLA COMMUNICATIONS DEVICE DATA

Figure 17a. Single Channel Narrowband FM Receiver at 49.7 MHz
MC13135
24
23

~0.1

22
Buffered LO
Output

-+--If---II-----,,.,.,.--..-i-'--...,,---,---'

0.001

1'V'l+----=+-----irl1 62PF --t--'IIIIIr-~r------t---

limiter

Recovered
Audio

10k

tl

'----ir-+-----------j-t2
0.1*

RSSI
Output

14
13
455kHz
Quad Coli
Taka
7MG-8128Z

Figure 17b. PC Board Component View

NOTES:

1. O.2IlH tunable (unshielded) Inductor

2. 39 MHz Series mode resonant
3rd Overtone Crystal

3. 1.5 IlH tunable (shielded) inductor
4. 10.245 MHz Fundamental mode crystal,
32 pF load
5. 455 kHz ceramic filter, muRala CFU 4558
or equivalent

6. Quadrature coil, Toke 7MC-B128Z (7mm)
or Toke RMC·2A6597HM (10mm)
7. 10.7 MHz ceramic filter, muRata SFE10.7MJ-A
or equivalent

Figure 17c. Optional Data Slicer Circuit
(Using Internal Op Amp)

Vee

MOTOROLA COMMUNICATIONS DEVICE DATA

MC13135.MC13136
2-149

Figure 18. PC BoardSolder Side View'

(Cireu" Side Voew)

Figure 19. PC Board Component View

NOTES:

1.

0.2 ~H tunable (unshielded) inductor

2.

39 MHz Series mode resonant
3rd Overtone Crystal

3.
4.

1.5 ~H tunable (shielded) inductor
10.245 MHz Fundamental mode crystal.

32 pF load
5.

6.
7.

MC13135.MC13136
2-150

455 kHz ceramic Hltar. muRal. CFU 4558
or equivalent
Ceramic discriminator. muRata FX2577
or equivalent
10.7 MHz ceramic filter. muRata SFE10.7MJ-A
or equivalent

MOTOROLA COMMUNICATIONS DEVICE DATA

Figure 20a. Single Channel Narrowband FM Receiver at 49.7 MHz

MC13136
24

0.1~

23

Buffered L0-1-_+_---1 I-----:-:::-..---t-------'
Output-

;-:n

0.001

22

+-__

'--_ _ _ _2_1

I

0.2J1H

0.Q1*

':'

62PF
150pF

<

RFtnput
50 II Source

':'

20

Ceramic
Fitter
10.7 MHz

360

10
0.1

Recovered Audio

Limiter
10k

11
RSSI
Output
12

0.1*
muRata
455kHz
Resonator
FX2577

Figure 20b. Optional Audio Amplifier Circuit

Speaker

27k

MOTOROLA COMMUNICATIONS DEVICE DATA

MC13135.MC13136
2-151

NiS:
.!..O

Figure 21. MC13135 Internal Schematic

en ...
NW

...

W

en

Vcc1

i

,

•
is:

......o
W

~

VEE

I I

I
FiJStlO

FiJStIlIXOl"

SecondlO

Second Mixer

~

Vcc2

Lf---r-ov:

~

14

r-..,

~

o
):

I

VEE

d

::Il

012

VEE

13

~

II

~

II

8s:
s:
c
z

(5

~

5
z
en

2k

~~:

!

+-W. I

I I!J ,I ,I ,I ,I II II

017

I

o
~

(5

m

o

~
»

VEE

I I
limiting IF Amplffier

Detector and Audio AmpDfler

VEE

s::

~
:D
o

5:

Figure 22. MC13136 Internal Schematic
Vcc1

15k

8s::
s::
c
z

o

:!:i
5z

5p

en
o
m
<

o

m

o
~

VEE

,

I
FirslLO

I

FirsiMixer

Second Mixer

SecondLO

»

~

$

th~~~c2

Vcc2

~12

VEE

VEE
13

I I

Vcc2

I I

I I

I I

I I

I I

I I

I

I

I

I

Vcc2

~17

2k

-•
o==

~~:

t

1.

1

I

~J

II

II

II

II

II II

Co)

~

o==

-",,Co)

~~

II

VEE
Umiting IF Amplifier

14

II
Detector and Audio Amplifier

VEE

MOTOROLA

MC13155

SEMICONDUCTOR-----TECHNICAL DATA

Advance Information
Wideband FM IF

WIDEBAND FM IF

The MC13155 is a complete wideband FM detector designed for
satellite TV and other wideband data and analog FM applications. This
device may be cascaded for higher IF gain and extended Receive
Signal Strength Indicator (RSSI) range.

SILICON MONOLITHIC
INTEGRATED CIRCUIT

• 12 MHz Video/Baseband Demodulator
• Ideal for Wideband Data and Analog FM Systems
• Limiter Output for Cascade Operation
• Low Drain Current: 7.0 mA
• Low Supply Voltage: 3.0 to 6.0 V
• Operates to 300 MHz
MAXIMUM RATINGS
Pin

Symbol

Value

Unit

Power Supply Voltage

Rating

11,14

VEE (max)

6.5

Vdc

Input Voltage

1,16

Vin

1.0

Vrms

TJ

+150

·C

Tstg

-65to+150

·C

-

Junction Temperature
Storage Temperature Range

DSUFFIX
PLASTIC PACKAGE
CASE 751B
(50-16)

NOTE: Devices should not be operated at or outside these values. The "Recommended Operating
CondHlons" provide for actual device operation.

PIN CONNECTIONS

Simplified Block Diagram

Input

Input
Decouple

Buflared
RSSI
Decouple Output
15

13

Limiter
Output

10

16

Input

>--0-+-+

Input

>-0--1--+

L _ _----'

Decouple

VCC1

VEE1

OUtput

RSSI Buffer

Output

RSSI

Vcc2

VEE2

Limiter Out

Limiter Out

Quad CoIl

Quad Coil

I
I

(Top View)

L_
2
Decouple

Balanced
Outputs

7
Limiter
Output

NOTE: This device requires carelullayout and decoupling to ensure stable operation.

ORDERING INFORMATION
Device
MC13155D

Temperature
Range

Package

- 40· to + 85·C

50·16

This document contains Inlonnatlon on a new product. Specifications and Inlonnation herein are subject to change wHhout notice.

MC13155
2-154

MOTOROLA COMMUNICATIONS DEVICE DATA

RECOMMENDED OPERATING CONDITIONS
Pin

Symbol

Value

Unit

Power Supply Voltage (TA= 25·C)
- 40·C STA S 85·C

Rating

11,14
3,6

VEE
VCC

-3.0to-6.0
Grounded

Vdc

Maximum Input Frequency

1,16

~n

300

MHz

-

TJ

-40to+85

·C

Ambient Temperature Range

DC ELECTRICAL CHARACTERISTICS (TA = 25·C, no input signai.)
Characteristic
Drain Current
(VEE = - 5.0 Vdc)
(VEE = - 5.0 Vdc)
Drain Current Total (see Figure 3)
(VEE = - 5.0 Vdc)
(VEE = - 6.0 Vdc)
(VEE = - 3.0 Vdc)

Pin

Symbol

Min

Typ

Max

Unit

11
14
14

111
114
114

2.0
3.0
3.0

2.8
4.3
4.3

4.0
6.0
6.0

mA

11,14

ITotai

5.0
5.0
5.0
4.7

7.1
7.5
7.5
6.6

10
10.5
10.5
9.5

mA

AC ELECTRICAL CHARACTERISTICS (TA = 25·C, IIF = 70 MHz, VEE =- 5.0 Vdc Figure 2, unless otherwise noted.)
Pin

Min

Typ

Max

Unit

Input lor - 3 dB Umiting Sensitivity

1,16

-

1.0

2.0

mVrrns

Differential Detector Output Voltage (Vin = to mVrrns)
(Idev = ± 3.0 MHz) (VEE = - 6.0 Vdc)
(VEE = - 5.0 Vdc)
(VEE = - 3.0 Vdc)

4,5
470
450
380

590
570
500

700
680
620

Characteristic

mVp•p

Detector DC Offset Voltage

4,5

-250

-

250

mVdc

RSSISlope

13

1.4

2.1

2.8

flA/dB

RSSI Dynamic Range

13

31

35

39

dB

RSSIOutput
(Vin = 100 IlVrrns)
(Vin = 1.0 mVrrns)
(Vin = 10 mVrrns)
(Vin = 100 rhVrrns)
(Vin = 500 mVrrns)

12

16
-

2.1
2.4
24
65
75

36
-

RSSI Buffer Maximum Output Current

(Vin = 10 mVrms)

Differential Limiter Output
(Vin = 1.0 mVrrns)
(Vin = 10 mVrrns)

13
7,10

Demodulator Video 3.0 dB Bandwidth

4,5

Input Impedance (Figure 14)
@70MHz Rp (VEE = - 5.0 Vdc)
Cp (C2=C15 = 100 p)

1,16

Differential IF Power Gain

1,7,10,16

100

-

2.3
140
180
12
450
4.8
46

-

f!A

mAdc
mVrrns

MHz
(l

pF
dB

NOTE: PosHlve currents Bre out of the pins of the device.

MOTOROLA COMMUNICATIONS DEVICE DATA

MC13155
2-155

CIRCUIT DESCRIPTION
indicator (RSSI) circuit which provides a current output
linearly proportional to the IF input signal level for
approximately 35 dB range of input level,

The MC13155 consists of a wideband three-stage limiting
amplifier, a wideband quadrature detector which may be
operated up to 200 MHz, and a received signal strength

Figure 2. Test Circuit

Vin

)>--t-s:-+-I----H---i
-=- 49.9

1.0n

27

~}-~-1-0n-;~

INI
DECI

1-....,..-----1r----..,.--~-0

VCCI

VEE

DETOI

Video
Oulput

Limiterl~
OUlput

DET02

1-....,..-----"01"""""-----0 VEE

VCC2

1--......- - - . . - - - - - -......-0 VEE

LlMOl

1.0n

330

QUADI

499
20p
L1 - Coilcraft part number 146-09JOOS

260n

APPLICATION INFORMATION
Evaluation PC Board
The evaluation PCB shown in Figures 19 and 20 is very
versatile and is designed to cascade two ICs. The center
section of the board provides an area for attaching all surface
mount components to the circuit side and radial leaded
components to the component ground side of the PCB (see
Figures 17 and 18). Additionally, the peripheral area
surrounding the RF core provides pads to add supporting
and interface circuitry as a particular application dictates.
This evaluation board will be discussed and referenced in
this section.
Limiting Amplifier
Differential input and output ports interfacing the three
stage limiting amplifier provide a differential power gain of
typically 46 dB and useable frequency range of 300 MHz.

MC13155
2-156

The IF gain flatness may be controlled by decoupling of the
internal feedback network at Pins 2 and 15.
Scattering parameter (S-parameter) characterization of the
IF as a two port linear amplifier is useful to implement
maximum stable power gain, input matching, and stability over
. a desired bandpass response and to ensure stable operation
outside the bandpass as well. The MC13155 is unconditionally
stable over most of its useful operating frequency range;
however, it can be made unconditionally stable over its entire
operating range with the proper decoupling of Pins 2 and 15.
Relatively small decoupling capacitors of about 100 pF have
a significant effect on the wideband response and stability.
This is shown in the scattering parameter tables where
S-parameters are shown for various values of C2 and C15 and
at VEE of - 3.0 and - 5.0 Vdc.

MOTOROLA COMMUNICATIONS DEVICE DATA

TYPICAL PERFORMANCE AT TEMPERATURE
(See Figure 2. Test Circuit)

Figure 4. RSSI Output versus Frequency and
Input Signal Level

Figure 3. Drain Current versus Supply Voltage
100

-

- TAJ25DC
ITotal = 114 + 111

r

I
I

~

I

1.0

2.0

5o

114

3.0

~

i

:5.0
-50

5en
~

./

/~
/'
./
-30

22.0
21.5
-50

100

1000

~
./

,.

~
.....:::: v . /

1
~
a

5.0

r- f=70MHz

4.0

z

~ 3.5

/-3.0Vdc

..........

33.0

i;:!: 2.5

-10

10

30

SO

70

VEE = - 5.0 Vdc

4.5

90

2.0
-SO

110

~

~

114

".......
."...

/

-- -- 30

-10

~

10

~ i,..-

!--

30

50

70

90

110

TA, AMBIENT TEMPERATURE (DC)

TA, AMBIENT TEMPERATURE (DC)

Figure 7. RSSI Output versus Ambient
Temperature and Supply Voltage

Figure 8. RSSI Output versus Input Signal Voltage
(Vin at Temperature)

L

23.5

~22.5

10

./

24.0

23.0

8.0

VEE = - 6.0 Vd~ ,.........,...-5.0VdC

24.5

:=

7.0

5.5

25.0

<
.::.
5

6.0

-

_40IdB~

o

r--. .........
r--. .......

Figure 6. Detector Drain Current and Limiter Drain
Current versus Ambient Temperature

7.0

5.5

~

-301dBJ

Figure 5. Total Drain Current versus Ambient
Temperature and Supply Voltage

...J

~ 6.0

40

f, FREQUENCY (MHz)

7.5

12

5.0

r-..

VEE, SUPPLY VOLTAGE (·Vdc)

8.0

i::!: 6.5

4.0

~ r-....

-201dBl

20

9.0
... 8.5

~
a:
G
z
~

-10IdB~

60

/I
f/

;

JdBl

80

-==

Ir

0.0
0.0

-- - ""

VEE = - 5.0Vdc

<

'/

/
/

/'" ,.
/'

./

-30

-

100
VEE = - 6.0 Vdc

~

<80

~

5

""

:1.

VEE=-5.0Vdc ",

/"

/

-

I

MOTOROLA COMMUNICATIONS DEVICE DATA

90

60

0

~3.~VdC-

-10
10
30
SO
70
TA, AMBIENT TEMPERATURE (DC)

5

110

en

Ul

a:
~

40

20
0
0.1

1.0

10

100

1000

Vln"INPUT VOLTAGE (mVnns)

MC13155
2-157

Figure 9. Differential Detector Output Voltage versus
Ambient Temperature and Supply Voltage

w

~

750

~

700

~

650

5"'-600
a:::$'OE

fd~
~:
....J.s;:

550
500

."

>

-50

-30

-

£fis

...

~~160



m

-10

Vln=lbmvrrns

o'§'.I60

V

,/'

f=70MHz
VEE =-5.0 Vde

200

~I

...... -3.0Vde

,/

350

5

~

V-5.0Vde

.......::::V

220

!j

o

, . / '"

/' /"

400

It

~

~

~!!:. 450

iIi
ffi

~

VE~-6.0Vde

........:

Figure 10. Differential Limiter Output Voltage versus
Ambient Temperature (Vin = 1 and 10 mVrms)

slN

0
-10
iii' -20

:s.
z

Z

/

k..-<;...

-30

......

,

"

J; -40
-50
-60
-70

-90

......

fe= 70 MHz
fmod = 1.0 MHz
fdev = ± 5.0 MHz
VEE =-5.0 Vdc
-70

"- ............N

-50

-30

-10

10

IF INPUT (dBm)

MOTOROLA COMMUNICATIONS DEVICE DATA

In the S-parameters measurements, the IF is treated as a
two-port linear class A amplifier. The IF amplifier is measured
with a single-ended Input and output configuration in which
the Pins 16 and 7 are terminated in the series combination of
a 47 n resistor and a 10 nF capacitor to VCC ground (see
Figure 11- S-Parameter Test Circuit).
The S-parameters are in polar form as the magnitude
(MAG) and angle (ANG). Also listed in the tables are the
calculated values for the stabiliiy factor (K) and the Maximum

Available Gain (MAG). These terms are related in the
following equations:
K (1-IS11 12 -I S2212 + I A 12) 1 (21 S12 S21 I)

=

where: I A I = I S11 S22 - S12 S21 I.
MAG 10 log I S211 /I S121 + 10 log I K- (K2 -1)1/21
where: K > 1. The necessary and sufficient conditions for
unconditional stability are given as K > 1:

=

81

=1 + I S11 12 -I S22 12 -I A 12 > 0

Figure 14. S-Parameter Test Circuit
IF
Input

SMA

)

~

INI
DEel
Vee1

1-_--_---......-0

VEE

DETOI
DET02
Vcc2
SMA
LIMOI

I--~I--~I---«
1.0n

':'

IF
Output

QUADI

MOTOROLA COMMUNICATIONS DEVICE DATA

MC13155
2-159

-

S-Parameters (VEE - - 5 0 Vdc TA - 25°C C2 and C15 - 0 pF)
K

MAG

MHz

MAG

ANG

MAG

ANG

MAG

ANG

MAG

ANG

MAG

dB

1.0

0.94

-13

8.2

143

0.001

7.0

0.87

-22

2.2

32

2.0

0.78

-23

23.5

109

0.001

-40

0.64

-31

4.2

33.5

5.0

0.48

1.0

39.2

51

0.001

-97

0.34

-17

8.7

33.7

7.0

0.59

15

40.3

34

0.001

-41

0.33

-13

10.6

34.6

10

0.75

17

40.9

19

0.001

-82

0.41

-1.0

5.7

36.7

20

0.95

7.0

42.9

-6.0

0.001

-42

0.45

0

1.05

46.4

50

0.98

-10

42.2

-48

0.001

-9.0

0.52

-3.0

0.29

-

70

0.95

-16

39.8

-68

0.001

112

0.54

-16

1.05

46.4

100

0.93

-23

44.2

-93

0.001

80

0.53

-22

0.76

150

0.91

-34

39.5

':'139

0.001

106

0.50

-34

0.94

-

Frequency

InputSll

ForwardS21

Rev S12

OutputS22

200

0.87

-47

34.9

-179

0.002

77

0.42

-44

0.97

-

500

0.89

-103

11.1

-58

0.022

57

0.40

-117

0.75

-

700

0.61

-156

3.5

-164

0.03

0

0.52

179

2.6

13.7

900

0.56

162

1.2

92

0.048

-44

0.47

112

4.7

4.5

1000

0.54

131

0.8

42

0.072

-48

0.44

76

5.1

0.4

K

MAG

S-Parameters (VEE = - 5.0 Vdc, TA '" 25°C, C2 and C15 = 100 pF)
Frequency

InputSll

Forward S21

OutputS22

Rev S12

MHz

MAG

ANG

MAG

ANG

MAG

ANG

MAG

ANG

MAG

dB

1.0

0.98

-15

11.7

174

0.001

-14

0.84

-27

1.2

37.4

2.0

0.50

-2.0

39.2

85.5

0.001

-108

0.62

-35

6.0

35.5

5.0

0.87

8.0

39.9

19

0.001

100

0.47

-9.0

4.2

39.2

7.0

0.90

5.0

40.4

9.0

0.001

-40

0.45

-8.0

3.1

40.3

10

0.92

3.0

41

1.0

0.001

-40

0.44

-5.0

2.4

41.8

20

0.92

-2.0

42.4

-14

0.001

-87

0.49

-6.0

2.4

41.9

50

0.91

-8.0

41.2

-45

0.001

85

0.50

-5.0

2.3

42

70

0.91

-11

39.1

-63

0.001

76

0.52

-4.0

2.2

41.6

100

0.91

-15

43.4

-84

0.001

85

0.50

-11

1.3

43.6

150

0.90

-22

38.2

-126

0.001

96

0.43

-22

1.4

41.8

200

0.86

-33

35.5

-160

0.002

78

0.43

-21

1.3

39.4

500

0.80

-66

8.3

-9.0

0.012

75

0.57

-63

1.7

23.5

700

0.62

-96

2.9

-95

0.013

50

0.49

-111

6.3

12.5

900

0.56

-120

1.0

-171

0.020

53

0.44

-150

13.3

2.8

1000

0.54

-136

0.69

154

0.034

65

0.44

-179

12.5

-0.8

MC13155
2-160

MOTOROLA COMMUNicATIONS DEVICE DATA

S-Parameters (VEE =- 50 Vdc , TA =25°C, C2 and C15 =680 pF)

K

MAG

MHz

MAG

ANG

MAG

ANG

MAG

ANG

MAG

ANG

MAG

dB

1.0

0.74

4.0

53.6

110

0.001

101

0.97

-35

0.58

-

2.0

0.90

3.0

70.8

55

0.001

60

0.68

-34

1.4

45.6

5.0

0.91

0

87.1

21

0.001

-121

0.33

-60

1.1

49

7.0

0.91

0

90.3

11

0.001

-18

0.25

-67

1.2

48.4

Frequency

Input S11

Forward S21

RevS12

OutputS22

10

0.91

-2.0

92.4

2.0

0.001

33

0.14

-67

1.5

47.5

20

0.91

-4.0

95.5

-16

0.001

63

0.12

-15

1.3

48.2

50

0.90

-8.0

89.7

-50

0.001

-43

0.24

26

1.8

46.5

70

0.90

-10

82.6

-70

0.001

92

0.33

21

1.4

47.4

100

0.91

-14

77.12

-93

0.001

23

0.42

-1.0

1.05

49

150

0.94

-20

62.0

-122

0.001

96

0.42

-22

0.54

200

0.95

-33

56.9

-148

0.003

146

0.33

-62

0.75

-

500

0.82

-63

12.3

-12

0.007

79

0.44

-67

1.8

26.9

700

0.66

-98

3.8

-107

0.014

84

0.40

-115

4.8

14.6

900

0.56

-122

1.3

177

0.028

78

0.39

-166

8.0

4.7

1000

0.54

-139

0.87

141

0.048

76

0.41

165

7.4

0.96

K

MAG

S-Parameters (VEE =- 3.0 Vdc, TA =25°C, C2 and C15 =0 pF)

Frequency

InputS11

Forward S21

RevS12

OutputS22

MHz

MAG

ANG

MAG

ANG

MAG

ANG

MAG

ANG

MAG

dB

1.0

0.89

-14

9.3

136

0.001

2.0

0.84

-27

3.2

30.7

105

0.001

-90

0.67

-37

3.5

34.3

0.40

-13

10.6

2.0

0.76

-22

24.2

5.0

0.52

5.0

35.7

46

0.001

-32

7.0

0.59

12

38.1

34

0.001

-41

0.40

-10

9.1

10

0.78

15

37.2

16

0.001

-92

0.40

-1.0

5.7

,

33.3
34.6
36.3

20

0.95

5.0

38.2

-9.0

0.001

47

0.51

-4.0

0.94

-

50

0.96

-11

39.1

-50

0.001

-103

0.48

-6.0

1.4

43.7

70

0.93

-17

36.8

-71

0.001

-76

0.52

-13

2.2

41.4

100

0.91

-25

34.7

-99

0.001

-152

0.51

-19

3.0

39.0

150

0.86

-37

33.8

-143

0.001

53

0.49

-34

1.7

39.1

200

0.81

-49

27.8

86

0.003

76

0.55

-56

2.4

35.1

500

0.70

-93

6.2

-41

0.015

93

0.40

-110

2.4

19.5

700

0.62

-144

1.9

-133

0.049

56

0.40

-150

3.0

8.25

900

0.39

-176

0.72

125

0.11

-18

0.25

163

5.1

-1.9

1000

0.44

166

0.49

80

0.10

-52

0.33

127

7.5

-4.8

MOTOROLA COMMUNICATIONS DEVICE DATA

MC13155
2-161

S-Parameters (VEE = - 3 0 Vdc TA = 25°C, C2 and C15 = 100 pF)
Frequency

Input 811

Forward 821

Output 822

Rev 812

K

MAG

MHz

MAG

ANG

MAG

ANG

MAG

ANG

MAG

ANG

MAG

dB

1.0

0.97

-15

11.7

171

0.001

-4.0

0.84

-27

1.4

36.8

2.0

0.53

2.0

37.1

80

0.001

-91

0.57

-31

6.0

34.8

5.0

0.88

7.0

37.7

18

0.001

-9.0

0.48

-7.0

3.4

39.7

7.0

0.90

5.0

37.7

8.0

0.001

-11

0.49

-7.0

2.3

41

10

0.92

2.0

38.3

1.0

0.001

-59

0.51

-9.0

2.0

41.8
42.5

20

0.92

-2.0

39.6

-15

0.001

29

0.48

-3.0

1.9

50

0.91

-8.0

38.5

-46

0.001

-21

0.51

-7.0

2.3

41.4

70

0.91

-11

36.1

-64

0.001

49

0.50

-8.0

2.3

40.8

100

0.91

-15

39.6

-85

0.001

114

0.52

-13

1.7

37.8

150

0.89

-22

34.4

-128

0.001

120

0.48

-23

1.6

40.1

200

0.86

-33

32

-163

0.002

86

0.40

-26

1.7

37.8
22.1

500

0.78

-64

7.6

-12

0.013

94

0.46

-71

1.9

700

0.64

-98

2.3

-102

0.027

58

0.42

-109

4.1

10.1

900

0.54

-122

0.78

179

0.040

38.6

0.35

-147

10.0

-0.14

1000

0.53

-136

0.47

144

0.043

23

0.38

-171

15.4

-4.52

K

MAG

S-Parameters (VEE =-3.0Vdc, TA = 25°C, C2 and C15= 680 pF)
Frequency

Input 811

Forward 821

Output 822

Rev 812

MHz

MAG

ANG

MAG

ANG

MAG

ANG

MAG

ANG

MAG

dB

1.0

0.81

3.0

37

101

0.001

-19

0.90

-32

1.1

43.5

2.0

0.90

2.0

47.8

52.7

0.001

-82

0.66

-39

0.72

-

5.0

0.91

0

58.9

20

0.001

104

0.37

-56

2.3

44

7.0

0.90

-1

60.3

11

0.001

-76

0.26

-55

2.04

44

10

0.91

-2.0

61.8

3.0

0.001

105

0.18

-52

2.2

43.9
44.1

20

0.91

-4.0

63.8

-15

0.001

59

0.11

-13

2.0

50

0.90

-8.0

60.0

-48

0.001

96

0.22

33

2.3

43.7

70

0.90

':'11

56.5

-67

0.001

113

0.29

15

2.3

43.2

100

0.91

-14

52.7

-91

0.001

177

0.36

5.0

2.0

43

150

0.93

-21

44.5

-126

0.001

155

0.35

-17

1.8

42.7
34.1

200

0.90

-43

41.2

-162

0.003

144

0.17

-31

1.6

500

0.79

-65

7.3

-13

0.008

80

0.44

-75

3.0

22

700

0.65

-97

2.3

-107

0.016

86

0.38

-124

7.1

10.2

900

0.56

-122

0.80

174

0.031

73

0.38

-174

12

0.37

1000

0.55

-139

0.52

137

0.50

71

0.41

157

11.3

-3.4

MC13155
2-162

MOTOROLA COMMUNICATIONS DEVICE DATA

DC Biasing Considerations
The DC biasing scheme utilizes two VCC connections
(Pins 3 and 6) and two VEE connections (Pins 14 and 11).
VEE1 (Pin 14) is connected internally to the IF and RSSI
circuits' negative supply bus while VEE2 (Pin 11) is connected
internally to the quadrature detector's negative bus. Under
positive ground operation, this unique configuration offers the
ability to bias the RSSI and IF separately from the quadrature
detector. When two ICs are cascaded as shown in the 70
MHz application circuit and provided by the PCB (see Figures
17 and 18), the first MC13155 is used without biasing its
quadrature detector, thereby saving approximately 3.0 mAo A
total current of 7.0 mA is used to fully bias each IC, thus the
total current in the application circuit is approximately 11 mAo
Both VCC pins are biased by the same supply. VCC1 (Pin 3) is
connected internally to the positive bus of the first half of the
IF limiting amplifier, while VCC2 is internally connected to the
positive bus of the RSSI, the quadrature detector circuit, and
the second half of the IF limiting amplifier (see Figure 15).
This distribution of the VCC enhances the stability of the IC.
RSSI Circuitry
The RSSI circuitry provides typically 35 dB of linear
dynamic range and its output voltage swing is adjusted by
selection of the resistor from pin 12 to VEE. The RSSI slope is

typically 2.1 !lA/dB; thus, for a dynamic range of 35 dB, the
current output is approxim'ately 74 !lA. A 47 k resistor will
yield a RSSI output voltage swing of 3.5 Vdc. The RSSI
buffer output at Pin 13 is an emitter-follower and needs an
external emitter resistor of 10k to VEE.
In a cascaded configuration (see circuit application in
Figure 16), only one of the RSSI Buffer outputs (Pin 13) is
used; the RSSI outputs (Pin 12 of each IC) are tied together
and the one closest to the VEE supply trace is decoupled
to VCC ground. The two pins are connected to VEE through
a 47 k resistor. This resistor sources a RSSI current which
is proportional to the signal level at the IF input; typically,
1.0 mVrms (-47 dBm) is required to place the MC13155
into limiting. The measured RSSI output voltage response
of the application circuit is shown in Figure 12. Since the
RSSI current output is dependent upon the input signal level
at the IF input, a careful accounting of filter losses, matching
and other losses and gains must be made in the entire
receiver system. In the block diagram of the application
circuit shown below, an accounting of the signal levels at
points throughout the system shows how the RSSI
response in Figure 12 is justified.

Block Diagram of 70 MHz Video Receiver Application Circuit
Input
Level:

Inp~

-57dB
31611Vms

-B2dBm
lBI1Vms

-72dBm
5611Vms

>-tr:l-s fT

J-L:yl:~~

:J;:
-

-25dB
(Insertion Loss)

Transformer
10 dB

- 47 dBm 1.0 mVms

Minimum Inputto Acquire
Limhing in MC13155

10 t-..,....J>N\r-1,........,IH 16

16
MC13155

MC13155

'-----:4::"0-::dB:":G:":a":"in--.J

Cascading Stages
The limiting IF output is pinned-out differentially,
cascading is easily achieved by AC coupling stage to
stage. In the evaluation PCB, AC coupling is shown,
however, interstage filtering may be desirable in some
applications. In which case, the S-parameters provide a
means to implement a low loss interstage match and better
receiver sensitivity.
Where a linear response of the RSSI output is desired
when cascading the ICs, it is necessary to provide at least
10 dB of interstage loss. Figure 12 shows the RSSI response
with and without interstage loss. A 15 dB resistive attenuator
is an inexpensive way to linearize the RSSI response. This
has its drawbacks since it is a wideband noise source that is
dependent upon the source and load impedance and the
amount of attenuation that it provides. A better, although
more costly, solution would be a bandpass filter designed to
the desired center frequency and bandpass response while

MOTOROLA COMMUNICATIONS DEVICE DATA

-32dBm
5.611Vms

-15 dB
(Attenuator)

40 dB Gain

carefully selecting the insertion loss. A network topology
shown below may be used to provide a bandpass response
with the desired insertion loss.
Network Topology
1.0n

10

r
I

0.2211 II ~
7

L

1.0n

MC13155
2-163

Quadrature Detector
The quadrature detector Is coupled to the IF with Intemal
2.0 pF capacitors between Pins 7 and 8 and Pins 9 and 10.
For wideband data applications, such as FM video and
satellite receivers, the drive to the detector can be increased
with additional extemal capacitors between these pins, thus,
the recovered video signal level output is increased for a
given bandwidth (see Figure 11 A and Figure 11 B).
The wideband performance of the detector is controlled by
the loaded Q of the LC tank circuit. The following equation
defines the components which set the detector circuit's
bandwidth:
Q= RTIXL
(1)
where: RT is the equivalent shunt resistance across the LC
Tank and XL is the reactance of the quadrature inductor at the
IF frequency (XL = 27tfL).
The inductor and capaCitor are chosen to form a resonant
LC Tank with the PCB and parasitic device capacitance at the
desired IF center frequency as predicted by:
fc = (21t ~(LCp» -1
(2)
where: L is the parallel tank inductor and Cp is the equivalent
parallel capacitance of the parallel resonant tank circuit.
The following is a design example for a wideband
detector at 70 MHz and a loaded Q of 5. The loaded Q of
the quadrature detector is chosen somewhat less than the
Q of the IF bandpass. For an IF frequency of 70 MHz and
an IF bandpass of 10.9 MHz, the IF bandpass Q is
approximately 6.4.

Example:
Let the external Cext = 20 pF. (The minimum value here
should be greater than 15 pF making it greater than the
internal device and PCB parasitic capacitance, Cint 3.0 pF).

=

Cp = Cint + Cext = 23 pF
Rewrite Equation 2 and solve for L:
L = (0.159)2 /(Cp fc 2)
L = 198 nH, thus, a standard value is chosen.
L = 0.22 IlH (tunable shielded inductor).

MC13155
2·164

The value of the total damping resistor to obtain the
required loaded Q of 5 can be calculated by rearranging
Equation 1:
RT = Q(27tfL)
RT = 5 (21C)(70)(0.22) = 483.8

n

The intemal resistance, Rint between the quadrature tank
Pins 8 and 9 is approximately 3200 n and is considered in
determining the external resistance, Rext which is
calculated from:
Rext = ((RT)(Rint))/ (Rint - RT)
Rext = 570, thus, choose the standard value.
Rext=560 n
SAW Filter
In wideband video data applications, the IF occupied
bandwidth may be several MHz wide. A good rule of thumb is
to choose the IF frequency about 10 or more times greater
than the IF occupied bandwidth. The IF bandpass filter is a
SAW filter in video data applications where a very selective
re~onse is needed (i.e., very sharp bandpass response).
The evaluation PCB is laid out to accommodate two SAW
filter package types: 1) A five-leaded plastic SIP package.
Recommended part numbers are Siemens X6950M which
operates at 70 MHz; 10.4 MHz 3 dB passband, X6951M
(X252.8) which operates at 70 MHz; 9.2 MHz 3 dB passband;
and X6958M which operates at 70 MHz, 6.3 MHz 3 dB
passband, and 2) A four-leaded TO-39 metal can package.
Typical insertion loss in a wide bandpass SAW filter is 25 dB.
The above SAW filters require source and load
impedances of 50 n to assure stable operation. On the PC
board layout, space Is provided to add a matching network,
such as a 1:4 surface mount transformer between the SAW
filter output and the inputto the MC13155. A 1:4 transformer,
made by Coilcraft and Mini Circuits, provides a suitable
interface (see Figures 16, 17 and 18). In the circuit and
layout, the SAW filter and the MC13155 are differentially
configured with interconnect traces which are equal in length
and symmetrical. This balanced feed enhances RF stability,
phase linearity, and noise performance.

MOTOROLA COMMUNICATIONS DEVICE DATA

Det
Out

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MOTOROLA COMMUNICATIONS DEVICE DATA

:!

1~

-y

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u
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::: >w

i!'i
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"""

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jl,t.
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MC13155
2-165

Figure 16. 70 MHz Video Receiver Application Circuit

220
SAW Riter Is Siemens
Part NlIl1ber X6950M

RSSI
Output

MC13155
IN2
DEC2

RSSIB

10k

47k

~ lOOn

LlM02

820
820

MC13155
IN2
DEC2
VEEI

lOOn
RSSIB

De1ec1or
Ou1pul

RSSI
VEE2
LlM02
QUAD2

560

L- Coilcraft part number 146-{)8J08S

MC13155
2-166

MOTOROLA COMMUNICATIONS DEVICE bATA

Figure 17. Component Placement (Circuit Side)

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MOTOROLA COMMUNICATIONS DEVICE DATA

MC13155
2-167

Figure 19. Circuit Side View

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aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa

I·

4.0"

Figure 20. Ground Side View

MC13155
2-168

MOTOROLA COMMUNICATIONS DEVICE DATA

MOTOROLA

MC13156

SEMICONDUCTOR - - - - TECHNICAL DATA

Product Preview
Wideband FM IF System

WIDE BAND FM IF SYSTEM
for DIGITAL and
ANALOG APPLICATIONS

The MC13156 is a wideband FM IF subsystem targeted at high
performance data and analog applications. Excellent high frequency
performance is achieved, with low cost, through use of Motorola's
MOSAIC 1.5™ RF bipolar process. The MC13156 has an onboard
Colpitts VCO for PLL controlled multichannel operation. The mixer is
useful to beyond 200 MHz and may be used in a differential, balanced,
or single-ended configuration. The IF amplifier is split to accommodate
two low cost cascaded filters. RSSI output is derived by summing the
output of both IF sections. A precision data shaper has a hold function
to preset the shaper for fast recovery of new data.
Applications for the MC13156 include CT-2, wideband data links, and
other radio systems utilizing GMSK, FSK or FM modulation.

SILICON MONOLITHIC
INTEGRATED CIRCUIT

24

DWSUFFIX
PLASTIC PACKAGE
CASE 751E
(SO-24L)

• 3.0 to 6.0 Vdc Operation
• Typical Sensitivity at 200 MHz of 6.0 flV for 12 dB SINAD
• RSSI Range 01>70 dB
• High Performance Data Shaper for Enhanced CT-2 Operation
• Internal 330 Q Termination for 10.7 MHz Filters

ORDERING INFORMATION

• Split IF for Improved Filtering and Extended RSSI Range
• 3rd Order Intercept (Input) Target of -10 dBm

Device

Temperature
Range

MC13156DW - 40° to + 85°C

Package
SO-24L

Pin Connections and Block Diagram
OS
Hold

5.0pF

RF
In2

Mix
Out

IFln

IF
DEC 1

IF
DEC2

IF Out

VCC2

This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notlc8.

MOTOROLA COMMUNICATIONS DEVICE DATA

MC13156
2-169

MOTOROLA

MC13175
MC13176

SEMICONDUCTOR - - - - - TECHNICAL DATA

Advance Information
UHF FM/AM Transmitter

UHF FM/AM
TRANSMITTER

The MC13175 and MC13176 are one chip FM/AM transmitter subsystems
designed for AM/FM communication systems. They include a Colpitts crystal
reference oscillator, UHF oscillator, + 8 (MC13175) or + 32 (MC13176)
prescaler and phase detector forming a versatile PLL system. Targeted
applications are in the 260 to 470 MHz band and 902 to 928 MHz band covered
by FCC Title 47; Part 15. Other applications include local oscillator sources in
UHF and 900 MHz receivers, UHF and 900 MHz video transmitters, RF Local
Area Networks (LANs), and high frequency clock drivers. The MC13175176
offer the following features:

SILICON MONOLITHIC
INTEGRATED CIRCUIT

• UHF Current Controlled Oscillator
• Uses Easily Available 3rd Overtone or Fundamental Crystals for
Reference
• Fewer External Parts Required
• Low Operating Supply Voltage (1.8 to 5.0 Vdc)
• Low Supply Drain Currents
• Power Output Adjustable (Up to +10 dBm)

DSUFFIX

• Differential Output for Loop Antenna or Balun Transformer Networks

PLASTIC PACKAGE
CASE 751B
(SO-16)

• Power Down Feature
• ASK Modulated by Switching Output On and Off
• (MC13175) fo

=8 x fref; (MC13176) fo =32 x fref

Figure 1. Typical Application as 320 MHz AM Transmitter
AM Modulator
1.3k

PIN CONNECTIONS

5,
Coi\craft

1~5J08

Osc1

Imod

NC

Out Gnd

NC

Out 2

Osc4

Out 1

5,

.L""l00-p -r

... (MC13176)

vcc

*
'T'

30p
(MC13175)

MC13175-30p
MC13176·16Op

~

022j1
MC13175
CrystaJ
3rd Overtone
40.0000 MHz

1.0k=

Oo;;;--I

,(3)

'I

Vee

MC13176
Crystal

ICont

Enable

PDout

Reg. Gnd

Xtale

Xtalb

I
..L

Fundamental_
10 MHz

...Vee

NOTES: 1. 50 n coaxial balun, 1/10 wavelength at 320 MHz equals 1.5 inches.
2. Pins 5,10 & 15 are ground and connected to VEE which is the component/DC ground plane side of
PCB. These pins must be decoupled to Vee; decoupling capacitors should be placed as close as
possible to the pins.
3. The crystal oscillator circuit may be adjusted for frequency with the variable inductor (MC13175);
recommended source is Coilcraft "slot seven" 7mm tuneable inductor, Part #7M3-821. 1.0k resistor.
Shunting the crystal prevents it from oscillating in the fundamental mode.

ORDERING INFORMATION
Device
MC13175D
MC13176D

Temperature
Range
- 40° to +85°C

Package
SO-16
SO-16

This document contains information on a new product. Specifications and information herein are subject to change without notice.

MC1317S.MC13176
2·170

MOTOROLA COMMUNICATIONS DEVICE DATA

MAXIMUM RATINGS (TA =25·C, unless otherwise noted.)
Symbol

Value

Unit

Power Supply Voltage

VCC

7.0 (max)

Vdc

Operating Supply Voltage Range

VCC

1.8 to 5.0

Vdc

Junction Temperature

TJ

+150

·C

Operating Ambient Temperature

TA

-40to+85

·C

TstQ

-65to +150

·C

Rating

Storage Temperature

ELECTRICAL CHARACTERISTICS (Figure 2; VEE = - 3.0 Vdc, TA = 25·C, unless otherwise noted.)"
Characteristic

Pin

Supply Current (Power down: 111 & 116 = 0)
Supply Current (Enable [Pin 111 to VCC thru 30 k, 116 = 0)
Total Supply Current (Transmit Mode)
(Imod = 2.0 rnA; 10 = 320 MHz)

-

Differential Output Power (10 = 320 MHz; Vrel [Pin 91
= 500 mVp_p; 10 = N x Irel)
Imod = 2.0 rnA (see Figure 7, 8)
Imod=OmA

13& 14

Hold-In Range (± dlrel x N)
MC13175 (see Figure 7)
MC13176 (see Figure 8)

13& 14

Phase Detector Output Error Current
MC13175
MC13176

7

Oscillator Enable 'Time (see Figure 22b)

Symbol

Min

Typ

IEEI

-0.5

-

-

!lA

IEE2

-18

-14

rnA

IEE3

-39

-34

-

-

+4.7
-45

-

3.5
4.0

6.5
8.0

-

20
22

25
27

-

4.0

-

lerror

16

BWAM

Spurious Outputs (Imod = 2.0 rnA)
Spurious Outputs (Imod = 0 rnA)

13& 14
13& 14

Pson
Psoff

Maximum Divider Input Frequency
Maximum Output Frequency

13& 14

-

2.0
±diH

lenable

Idiv
10

Unit

rnA
dBm

Pout

11,8

Amplitude Modulation Bandwidth (see Figure 24)

Max

25
-50
-50
950
950

,-

MHz

!lA
ms
MHz
dBc

-

-

MHz

"Forlestlng purposes, vee Is ground (see Figure 2).

Figure 2_ 320 MHz Test Circuit

VEE
(1)

MC13175-30p
MCI3176-33p
MC13175
Crystal
3rd OVertone
40 MHz

-"1.

0.0111- - MC13176 I
o 82
3
Crystal
':"
. 11
Fundamental Vce
1 Ok
_
10 MHz
.
I

~+()
':" ':"

NOTES: 1. Vee Is ground; while VEE Is negalive wHh respect 10 ground.
2. Pins 5, 10 and 15 are broughllo the circuli side 01 the PCB via plated through holes. They are
connected together wHh a trace on the PCB and each Pin Is decoupled to Vee (ground).
3. Recommended source Is Collcral! "slot seven" Inductor, part number7M3-821.

MOTOROLA COMMUNICATIONS DEVICE DATA

MC1317S.MC13176
2-171

PIN DESCRIPTIONS
Pin

Symbol

1&4

Osc 1,
Osc4

Internal Equivalent
Circuit

~e

J

10k
1
OSc 1

10k
4

'"

""

Osc4

~

n

~

~

5

Description/External
Circuit Requirements

VEE

CCOlnputs
The oscillator is a current controlled type. An:external oscillator
coil is connected to Pins 1 and 4 which forms a parallel resonance
LC tank circuit with the internal capacitance of the
IC and with parasitic capacitance of the PC board. Three
base-emitter capacitances in series configuration form the
capacitance for the parallel tank. These are the base-emitters
at Pins 1 and 4 and the base-emitter of the differential amplifier.
The equivalent series capacitance in the differential amplifier is
varied by the modulating current from the frequency control circuit
(see Pin 6, Intemal circuit). A more thorough discussion
is found In the Applications Information section.

Supply Ground (VEE)
In the PCB layout, the ground pins (also applies to Pins 10 and
15) should be connected direcfly to chassis ground. Decoupling
capacitors to VCC should be placed directly at
the ground returns.

VEE

J- ~
5

VEE ";'

6

ICont

Frequency Control
For VCC = 3.0 Vdc, the voltage at Pin 6 is approximately 1.55 Vdc.
The oscillator is current controlled by the error current from the
phase detector. This current is amplified to drive the current
source in the oscillator section which controls the frequency of the
oscillator. Figures 9 and 10 show the dfosc versus ICont, Figure 5
shows the Mosc versus ICont at- 40°C, + 25°C and + 85°C for 320
MHz. The CCO may be FM modulated as shown in Figure 17,
MC13176320 MHz FM Transmitter. A detailed discussion is found
in the Applications Information section.

Vee

T

~

Reg
6

-

>-L<

IConi

7

~~

PDout

Phase Detector Output
The phase detector provides ± 30 I1A to keep the CCO locked at
the desired carrier frequency. The output Impedance of the phase
detector is approximately 53 kn. Under closed loop conditions
there is a DC voltage which Is dependent upon the free running
oscillator and the reference oscillator frequencies. The circuitry
between Pins 7 and 6 should be selected for adequate loop filtering necessary to stabilize and filter the loop response. Low pass
filtering between Pin 7 and 6 is needed so that the corner frequency Is well below the sum of the divider and the reference oscillator
frequencies, but high enough to allow for fast response to keep
the loop locked. Refer to the Applications Information section regarding loop filtering and FM modulation.

Vee
4.Ok

4.0k

~

~~

"-

~~

POout

7

f
8

Xtale

Vee

.

~~

9

Xtalb

8 Xtale

*

.~

MC13175.MC13176
2-172

~

'*'

r
t

~

~

l{
a.Ok.1V!
'I

t

'-I

t

Crystal Oscillator Inputs
The internal reference oscillator is configured as a common
emitter Colpitts. It may be operated with either a fundamental
or overtone crystal depending on the carrier frequency and the
Internal prescaler. Crystal oscillator circuits and specifications
of crystals are discussed in detail in the applications section.
With VCC = 3.0 Vdc, the voltage at Pin 8 is approximately 1.8 Vdc
and at Pin 9 is approximately 2.3 Vdc. 500 to 1000 mVp-p should
be present at Pin 9. The Colpitts is biased at 200 11A; additional
drive may be acquired by Increasing the bias to approximately 500
I'A. Use 6.2 k from Pin 8 to ground.

MOTOROLA COMMUNICATIONS DEVICE DATA

PIN DESCRIPTIONS
Pin

Symbol

9

Xtalb

10

Reg. Gnd

Internal Equivalent
Circuit

DescriptioillExternal
Circuit Requirements

Vee

Crystal Oscillator Inputs
The intemal reference oscillator is configured as a common
emitter Colpitts. It may be operated with either a fundamental
or overtone crystal depending on the carrier frequency and the
internal prescaler. Crystal oscillator circuits and specifications
of crystals are discussed in detail In the applications section.
With VCC = 3.0 Vdc, the voltage at Pin 8 is approximately 1.B Vdc
and at Pin 9 Is approximately 2.3 Vdc. 500 to 1000 mVp-p should
be present at Pin 9. The Colpitts Is biased at 200 11A; additional
drive may be acquired by increasing the bias to approximately 500
I1A. Use 6.2 k from Pin 8 to ground.

Reg

11

Enable

12

VCC

Device Enable
The potential at Pin 11 is approximately 1.25 Vdc. When Pin 11
is open, the transmitter is disabled in a power down mode and
draws less than 1.0 I1A ICC if the MOD at Pin 16 is also open (i.e.,
It has no current driving It). To enable the transmitter a current
source of 10 I1A to 90 I1A is provided. Figures 3 and 4 show the
relationship between ICC, VCC and Ireg . enable. NotethatiCC is flat
at approximately 10 mA for Ireg . enable = 5.0 to 100 I1A (Imod = 0).

Supply Voltage (VCC)
The operating supply voltage range is from 1.8 Vdc to 5.0 Vdc. In
the PCB layout, the VCC trace must be kept as wide as possible to
minimize inductive reactances along the trace; it is best to have it
completely fill around the surface mount components and traces
on the circuit side of the PCB.

Vee

J
t2

Vee
13& 14

Out 1 and
Out2

Vee
15

16

Regulator Ground
An additional ground pin is provided to enhance the stability of the
system. Decoupling to the VCC (RF ground) Is essential; it should
be done at the ground return for Pin 10.

OuCGnd

Imod

MOTOROLA COMMUNICATIONS DEVICE DATA

Differential Output
The output is configured differentially to easily drive a loop
antenna. By using a transformer or balun, as shown in the
application schematic, the device may then drive an unbalanced
low impedance load. Figure 6 shows how much the Output Power
and Free-Running Oscillator Frequency change with temperature
at 3.0 Vdc; Imod = 2.0 mAo
Output Ground
This additional ground pin provides direct access for the output
ground to the circuit board VEE.
AM Modulation/Power Output Level
The DC voltage at this pin is 0.8 Vdc with the current source active. An extemal resistor is chosen to provide a source current of
1.0 to 3.0 mA, depending on the desired output power level at a
given VCC. Figure 23 shows the relationship of Power Output to
Modulation Current, Imod. AtVCC = 3.0 Vdc, 3.5 dBm power output
can be acquired with about 35 mA ICC.
For FM modulation, Pin 16 is used to set the desired output power
level as described above.
For AM modulation, the modulation signal must ride on a positive
DC bias offset which sets a static (modulation off) modulation
current. Extemal circuitry for various schemes is further discussed
in the Applications Information section.

MC13175.MC13176
2-173

Figure 4. Supply Current versus
Regulator Enable Current

Figure 3, Supply Current
versus Supply Voltage
100
10

/

<§.
zw

8.0

:::J

6.0

I-

a:
a:

(,)

lreg. enable = 90 IlA
Imod=O

VCC= 3.0 Vdc
Imod=O

~

0..
0..

:::J

4.0

'"0

.E 2.0

I
./

o
o

1.0

2.0
3.0
VCC. SUPPLY VOLTAGE (Vdc)

4.0

0.1

Figure 5. Change Oscillator Frequency
versus Oscillator Control Current

1.0
10
100
lreg. anable. REGULATOR ENABLE CURRENT (1lA)

~

VCC=3.0Vdc
>lmod = 2.0 rnA
~ + 5.0 I----.:~p...o;:::---il-- 1= 320 MHz (ICont = 0; TA = 25 °C)
~
Free-Running Oscillator

~

~

+4.0

;: +3.0
(,)

ill

+2.0

~ O~----~~~~--~~~-+-----+----~

@
IE +1.0

~

a:

a:

0

~

~ -5.0 1-....,...--+---+-""O'c---f----oI:--~h:"'6:.:.°--l ~
25°C

6-101---4---+--~-~~-~1---4

.9

~

6

Po

'"'"" ,.,

¥

~

-20
0
20
40
60
ICont. OSCILLATO~ CONTROL CURRENT (1lA)

Figure 7. MC13175 Reference Oscillator
Frequency versus Phase Detector Current

i:; 41.0

ill

,.

,/

~ 40.8

u. 40.6

~

~ 40.4
<3
l3 40.2

\~

~\

"

w

~ 40.0
~
~ 39.8
~

j39..:630

-20

~

i'
:Eo

ffi

4.5~
0..

5

4.0 I!:

5
3.5,p

"-

3.0
100

Figure 8. MC13176 Reference Oscillator
Frequency versus Phase Detector Current

IE

Closed Loop Response:
VCC =3.0 Vdc
10.21-~'T"+-----I-----i--- fo= 32xfrel
Vref= 500 mVp-p

10.11------'k-'3oooo;::--I-----i----_t-----t-----j

~
~ 101-----+---~~~~~--_t-

Imod= 1.0mA
ICC=25mA

w

(,)

~ 9.9~----+-----1

~o=-0.2dBm

~..:. 9.8L-_-J..._ _

~

-10
0
10
20
17. PHASE DETECTOR CURRENT (1lA)

MC13175.MC13176
2-174

~
5
~

Imod=2.0mA
ICC=36mA
PO=5.4dBm

5.0

;: 10.3

a:

~

Vcc = 3.0 Vdc
Imod=2.0mA
f = 320 MHz (ICont = 0; TA = 25°C)
Free-Running Oscillator

o
50
TA. AMBIENT TEMPERATURE (OC)

-50

f

Closed Loop Response:
VCC = 3.0 Vdc
10 = 8.0 x lrel
Vrel = 500 mVp-p

\\

-,...

"'"

/'

.9 -3.0

80

,. ~

Xr

-1.0
-2.0

5.5

dlosc

~ -15L--~--~--~--~-~~~~ ~ -4.0
-40

1000

Figure 6. Change in Oscillator Frequency and
Output Power versus Ambient Temperature

~+10r-----r---~r----'----~----~-----'

§

I

1.0

5.0

30

_f!!.

-30

-20

........_ _..L....._---L_

..L.....~

-10
0
10
20
17. PHASE DETECTOR CURRENT (1lA)

__.:I

30

MOTOROLA COMMUNICATIONS DEVICE DATA

Figure 10. Change in Oscillator Frequency
versus Oscillator Control Current

Figure 9. Change In Oscillator Frequency
versus Oscillator Control Current

¥
>

~

5I
e:

10

0

gj -10

!5--'

§

-

20

<§.

£>

\

\

I'"

-20

0-30

VCC=3.0Vde
Imod=2.0mA
TA=25°C
lose (IConl @ 0) 320 MHz

f"....

-- r--

~

-

:::l

~
gj

-40
-100

10
0

-10

"\

'\.

'~

!5

<3- 20

l3
0-30
l3

r---

l3


Do

§

Figure 13. Lag-Lead Low Pass Filter
0
Vin

t2 = 2a/ron = (2) (0.707)/(5
1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0
COnt

MC1317S.MC13176
2-176

10

11

12 13

0

103) = 0.283 ms

tl = (Kv/ron2) - t2= (34,1 - 0.283) = 33.8 ms

MOTOROLA COMMUNICATIONS DEVICE DATA

Since sin Se cannot exceed ±1.0, as Se approaches ±Jr.I2 the
hold-in range is equal to the DC loop gain, Kv • N.

For C = 0.4711;
then, R1 = t1/C = 33.8 • 10-3/0.47. 10- 6 =72 k
thus, R2 = t2/C =0.283 • 10-3/0.47 • 10-6 = 0.60 k
In the above example, the following standard value components are used,
C =0.47 11; R2

= 620 and R'1 =72 k -

±l>.wH
where, Kv

53 k - 18 k

In the above example,

(R'1 is defined as R1 - 53 k, the output impedance of the
phase detector.)
Since the output of the phase detector is high impedance
(-50 k) and serves as a current source, and the input to the
frequency control, Pin 6 is low impedance (impedance of the
two diode to ground is approximately 500 Q), it is imperative
that the second order low pass filter design above be
modified. In order to minimize loading of the R2C shunt
network, a higher impedance must be established to Pin 6.
A simple solution is achieved by adding a low pass network
between the passive second order network and the input to
Pin 6. This helps to minimize the loading effects on the
second order low pass while further suppressing the
sideband spurs of the crystal oscillator. A low pass filter with
R3 = 1.0 k and C2 = 1500 P has a corner frequency (fc) of
106 kHz; the reference sideband spurs are down greater
than - 60 dBc.

±l>.wH = ± 27.3 Mradlsec
±l>.fH = ± 4.35 MHz
Extended Hold-in Range
The hold-in range of about 3.4% could cause problems
over temperature in cases where the free-running oscillator
drifts more than 2 to 3% because of relatively high
temperature coefficients of the ferrite tuned CCO inductor.
This problem might worsen for lower frequency applications
where the external tuning coil is large compared to internal
capacitance at Pins 1 and 4. To improve hold-in range
performance, it is apparent thai the gain factors involved
must be carefully considered.
Kn = is either 1/8 in the MC13175 or 1/32 in the MC13176.
Kp = is fixed internally and cannot be altered.
Ko = Figures 9 and 10 suggest that there is capability of
greater control range with more current swing.
However, this swing must be symmetrical about
the center of the dynamic response. The suggested
zero current operating point for ±1 00 IlA swing
of the CCO is at about + 70 IlA offset point.
Ka = External loop amplification will be necessary since
the phase detector only supplies ± 30 IlA.

Figure 14. Modified Low Pass Loop Filter
Pin 7

18k

I

1.0k

~-6-2-oI~A-2~t

'----r.--

O.47rr C

Pin 6
0

C3T1S00P
_

vc-c --'

In the design example in Figure 15, an external resistor
(R5) of 15 k to VCC (3.0 Vdc) provides approximately 100
!lA of current boost to supplement the existing 50 IlA
internal source current. R4 (1.0 k) is selected for
approximately 0.1 Vdc across it with 100 IlA. R1, R2 and
R3 are selected to set the potential at Pin 7 and the base
of 2N4402 at approximately 0.9 Vdc and the emitter at
1.55 Vdc when error current to Pin 6 is approximately
zero 1lA. C1 is chosen to reduce the level of the crystal
sidebands.

Hold-In Range
The hold-in range, also called the lock range, tracking
range and synchronization range, is the ability of the CCO
frequency, fo to track the input reference signal, fref • N as
it gradually shifted away from the free running frequency, ff.
Assuming that the CCO is capable of sufficient frequency
deviation and that the internal loop amplifier and filter are not
overdriven, the CCO will track until the phase error, Se
approaches ±Jr.I2 radians. Figures 5 through 8 are a direct
measurement of the hold-in range (i.e . .1.fre f • N = ±l>.fH • 27t).

Figure 15. External Loop Amplifier

-----'1
I

VCC=3.0Vdc

A3

4.7k

AS

1Sk
Oscillator
Control
CircuHry

1.6V
Phase
Detector
Output

1.0k

17

I
I
I
______ -.JI

MOTOROLA COMMUNICATIONS DEVICE DATA

2N4402

I
I

L _____ _

MC1317S.MC13176
2-177

Figure 16 shows the improved hold-in range of the loop.
The afref is moved 950 kHz with over 200 ).LA swing of control
current for an improved hold-in range of ±15.2 MHz or ± 95.46
Mradlsec.
Figure 16. MC13176 Reference Oscillator
Frequency versus Oscillator Control Current

'N'

:I:

~10.6

15 10 4
5

.

~

1'\

1'1\

a: 10.2

S
....I

~w

o

t"-r-.
10

1"- ...
I"-

9.8

Closed Loop Response
fo =32xfre f
Vcc= 3.0Vdc
ICC=38mA
Pout =4.8 dB
lmod = 2.0 mA
Vref = 500 mVp•p

...
r"- ...

~

m9.6
.;:. 9.4

~oo

-00

0

~

fc

= 7.55 kHz or Wc =47 kradlsec

The application example in Figure 17a of a 320 MHz FM
transmitter demonstrates the FM capabilities of the IC. A high
value series resistor (100 k) to Pin 6 sets up the current
source to drive the modulation section of the chip. Its value is
dependent on the peak to peak level of the encoding data
and the maximum desired frequency deviation. The data
Input is AC'coupled with a large coupling capacitor which is
selected for the modulating frequency. The component
placements on the circuit side and ground side of the PC
board are shown in Figures 28 and 29, respectively. Figure
18a illustrates the Input data of a 10kHz modulating signal at
1.6 Vp-p. Figures 18b and lBe depict the deviation and
resulting modulation spectrum showing the carrier null at - 40
dBc. Figure 18d shows the unmodulated carrier power output
at 3.5 dBm for VCC 3.0 Vdc.
For voice applications using a dynamic or an electret
microphone, an op amp is used to amplify the microphone's
low level output. The microphone amplifier circuit is shown
in Figure 19. Figure 17b shows an application example for
NBFM audio or direct FSK in which the reference crystal
oscillator is modulated.

=

a:

_e! -150

fc = 0.159/RC;
For R = 1.0 k + R7 (R7 = 53k) and C = 390 pF

100

16, OSCILLATOR CONTROL CURRENT (llAl

Lock-In Range/Capture Range
If a signal is applied to the loop not equal to free running
frequency, ff, then the loop will capture or lock-in the signal
by making fs fo (i:e. if the initial frequency difference is
not too great). The lock-in range can be expressed as aWL
- ± 2ilwn
FM Modulation
Noise extemal to the loop (phase detector input) is
minimized by narrowing the bandwidth. This noise is minimal
in a PLL system since the reference frequency is usually
derived from a crystal oscillator. FM can be achieved by
applying a modulation current superimposed on the control
current of the CCO. The loop bandwidth must be narrow
enough to prevent the loop from responding to the
modulation frequency components, thus, allowing the CCO
to deviate in frequency. The loop bandwidth is related to the
natural frequency wn. In the lag-lead design example where
the natural frequency, wn = 5.0 kradlsec and a damping
factor, il = 0.707, the loop bandwidth = 1.64 kHz.
Characterization data of the closed loop responses for both
the MC13175 and MC13176 at 320 MHz (Figures 7 and 8,
respectively) show satisfactory performance using only a
simple lOw-pass loop filter network. The loop filter response
is strongly influenced by the high output impedance of the
push-pull current output of the phase detector.

Figure 19. Microphone Amplifier

=

MC1317S.MC13176
2-178

Data
Input

Voice
Input

>

VCC

L......t--4-.J

Electret
Microphone

Local Oscillator Application
To reduce intemal loop noise, a relatively wide loop
bandwidth is needed so that the loop tracks out or cancels
the noise. This is emphasized to reduce inherent CCO and
divider noise or noise produced by mechanical shock and
environmental vibrations. In a local oscillator application the
CCO and divider noise should be reduced by proper
selection of the natural frequency of the loop. Additional low
pass filtering of the output will likely be necessary to reduce
the crystal sideband spurs to a minimal level.

MOTOROLA COMMUNICATIONS DEVICE DATA

Figure 17a. 320 MHz MC13176D FM Transmitter

Coilcraft
146-04JOB
SM

~RFOulpul

~-<-_ _ _ _~ SIQp* ... 10Anienna

(---'lM--I

vee

130k

Data Input
(1.6Vp-p)

~ Sip

Sip

~220P

~6.8(4)
Crystal
Fundamental (5)
10MHz

:t

NOTES: 1. 50 n coaxial balun. 2 Inches long.
2. Pins 5, 10 and 15 are grounds and connnected to VEE which Is Ihe component's side ground plane. These
pins must be decoupled 10 VCC; decoupling capacitors should be placed as close as possible to the pins.
3. RFClls 180 nH Coilcraft surface mount Inductor or 190 nH Collcraft 146-oSJOB.
4. Recommended source is a Coilcraft ·slot seven" 7.0 mm luneable Inductor, part #7M3-682.
5. The cryslalls a parallel resonant, fundamental mode calibraled with 32 pF load capacitance.

Figure 17b. 320 MHz NBFM Transmitter

Vee
fiO.----fVec (3.6 Vdc-Lhhlum Battery)

130k
33k

lOOp "J;

180p

(5) MMBV432l
NOTES: 1. 50 n coaxial balun, 2 Inches long.
2. Pins 5, 10 and 15 are grounds and connnected to VEE which Is the componenfs side ground plane. These
pins must be decoupled 10 VCC; decoupling capacitors should be placed as close as possible to Ihe pins.
3. RFClls lBO nH Collcraft surface mount Inductor.
4. RFC2 and RFC3 are high impedance crystal frequency of 10 MHz; B.2 I1H molded Inductor gives XL > 1000 n.
5. A single varactor like the MV21 05 may be used whereby RFC2 is nol needed.
6. The crystal Is a parallel resonant, fundamental mode calibrated with 32 pF load capaCitance.

MOTOROLA COMMUNICATiONS DEVICE DATA

Audio or
Data Input

MC13175.MC13176
2-179

Figure l8a.lnput Data Waveform

Figure l8b. Frequency Deviation

Figure l8c. Modulation Spectrum

Figure l8d. Unmodulated Carrier

Reference Crystal Oscillator (Pins 8 and 9)
Selection of Proper Crystal: A crystal can operate in a
number of mechanical modes. The lowest resonant
frequency mode is its fundamental while higher order modes
are called overtones. At each mechanical resonance, a
crystal behaves like a RLC series·tuned circuit having a large
inductor and a high Q. The inductor Ls is series resonance
with a dynamic capacitor, C s determined by the elasticity of
the crystal lattice and a series resistance Rs , which accounts
for the power dissipated in heating the crystal. This series
RLC circuit is in parallel with a static capacitance, Cp which
is created by the crystal block and by the metal plates and
leads that make contact with it.
Figure 20 is the equivalent circuit for a crystal in a single
resonant mode. It is assumed that other modes of resonance
are so far off frequency that their effects are negligible.
Series resonant frequency, fs is given by;
fs = 1/21t(LsCs )1/2
and parallel resonant frequency, fp is given by;

Figure 20. Crystal Equivalent Circuit

the frequency separation at resonance is given by;

=

=

.M fp-fs fs[1 - (1 + Cs/C p)1/2)
Usuallyfp is less than 1% higherthanfs , andacrystalexhibitsan
extremely wide variation of the reactance with frequency between fp and fs- A crystal oscillator circuit is very stable with fre·
quency. This high rate of change of impedance with frequency
stabilizes the oscillator, because any significant change in os-

fp = fs(1 + Cs/C p)1/2

MC13175.MC13176
2-180

MOTOROLA COMMUNICATIONS DEVICE DATA

cillator frequency will cause a large phase shift in the feedback
loop keeping the oscillator on frequency.
Manufacturers specify crystal for either series or parallel
resonant operation. The frequency for the parallel mode is
calibrated with a specified shunt capacitance called a "load
capacitance". The most common value is 30 to 32 pF. If the
load capacitance is placed in series with the crystal, the
equivalent circuit will be series resonance at the specified
parallel-resonant frequency. Frequencies up to 20 MHz use
parallel resonant crystal operating in the fundamental mode,
while above 20 MHz to about 60 MHz, a series resonant
crystal specified and calibrated for operation in the overtone
mode is used.
Application Examples
Two types of crystal oscillator circuits are used in the
applications circuits: 1) Fundamental mode common emitter
Colpitts (Figures 1, 17a, 17b, and 21). 2) Third overtone
impedance inversion Colpitts (also Figures 1 and 21).
The fundamental mode common emitter Colpitts uses a
parallel resonant crystal calibrated with a 32 pf load
capacitance. The capacitance values are chosen to provide
excellent frequency stability and output power of > 500
mVp-p at Pin 9. In Figures 1 and 21, the fundamental mode
reference oscillator is fixed tuned relying on the repeatability
of the crystal and passive network to maintain the frequency,
while in the circuit shown in Figure 17, the oscillator
frequency can be adjusted with the variable inductor for the
precise operating frequency.
The third overtone impedance inversion Colpitts uses
a series resonance crystal with a 25 ppm tolerance. In
the application examples (Figures 1 and 21), the
reference oscillator operates with the third overtone
crystal at 40.0000 MHz. Thus, the MC13175 is operated
at 320 MHz (fd8 = crystal; 320/8 = 40.0000 MHz. The
resistor across the crystal ensures that the crystal will
operate in the series resonant mode. A tuneable inductor
is used to adjust the oscillation frequency; it forms a
parallel resonant circuit with the series and parallel
combination of the external capacitors forming the divider
and feedback network and the base-emitter capacitance
of the device. If the crystal is shorted, the reference
oscillator should free-run at the frequency dictated by the
parallel resonant LC network.
The reference oscillator can be operated as high as 60
MHz with a third overtone crystal. Therefore, it is
possible to use the MC13175 up to at least 480 MHz and
the MC13176 up to 950 MHz (based on the maximum
capability of the divider network).
Enable (Pin 11)
The enabling resistor at Pin 11 is calculated by:
Rreg. enable = VCC - 1.0 Vdc/l reg. enable

MOTOROLA COMMUNICATIONS DEVICE DATA

From Figure 4, Ireg . enable is chosen to be 75 1lA. So, for a
VCC = 3.0 Vdc Rreg . enable = 26.6 kn, a standard value 27
kn resistor is adequate.
Layout Considerations
Supply (Pin 12): In the PCB layout, the VCC trace must
be kept as wide as possible to minimize inductive reactance
along the trace; it is best that VCC (RF ground) completely
fills around the surface mounted components and
interconnect traces on the circuit side of the board. This
technique is demonstrated in the evaluation PC board.
Battery/Selection/Lithium Types
The device may be operated from a 3.0 V lithium battery.
Selection of a suitable battery is important. Because one of
the major problems for long life battery powered equipment
is oxidation of the battery terminals, a battery mounted in a
clip-in socket is not advised. The battery leads or contact
post should be isolated from the air to eliminate oxide
build-up. The battery should have PC board mounting tabs
which can be soldered to the PCB. Consideration should be
given for the peak current capability of the battery. Lithium
batteries have current handling capabilities based on the
composition of the lithium compound, construction and the
battery size. A 1300 mAlhr rating can be achieved in the
cylindrical cell battery. The Rayovac CR2/3A
lithium-manganese dioxide battery is a crimp sealed, spiral
wound 3.0 Vdc, 1300 mAlhr cylindrical cell with PC board
mounting tabs. It is an excellent choice based on capacity
and size (1.358" long by 0.665" in diameter).
Differential Output (Pins 13, 14)
The availability of micro-coaxial cable and small baluns
in surface mount and radial-leaded components allows for
simple interface to the output ports. A loop antenna may be
directly connected with bias via RFC or 50 n resistors.
Antenna configuration will vary depending on the space
available and the frequency of operation.
AM Modulation (Pin 16)
Amplitude Shift Key: The MC13175 and MC13176 are
designed to accommodate Amplitude Shift Keying (ASK).
ASK modulation is a form of digital modulation corresponding
to AM. The amplitude of the carrier is switched between two
or more values in response to the PCM code. For the binary
case, the usual choice is On-Off Keying (often abbreviated
OOK). The resultant amplitude modulated waveform consists
of RF pulses called marks, representing binary 1 and spaces
representing binary O.

MC13175.MC13176
2-181

Figure 21. ASK 320 MHz Application Circuit
Rmod
3.3k

(4)

1--'VIrv---o On-Off Keyed Input
TIL Level 10 kHz
Coilcraft
150-0SJ08
SM

~RFout

~L----"'150p ~

(2) 0----+---1
VEE

I---Nv--';:-I (5)

100p
(MC13176)

J:

30p
~
(MC13175) ~

MC13175-30p
MC13176-180p

VCC

0.~2~t~~:c~:.~l

MC13175

3rd~~~~bne
40.0000 MHz

NOTES: 1.50 n coaxial balun, 1/10 wavelength line (1.5") provides the best
match to a 50 n load.
2. Pins 5, 10 and 15 are ground and connnected to VEE which is

the component/DC ground plane side of PCB. These pins must
be decoupled to VCC; decoupling capaCitors should be placed
as close as possible to the pins.
3. The crystal oscillator circuit may be adjusted for frequency with

I

1.0k
~

Crystal
Fundamental
10MHz

T

VCC

.I.

=

4. The On-Off keyed signal turns the output of the transmitter off and on with
TTL level pulses through Rmod at Pin 16. The "On" power and ICC is set
by the resistor which sets Imod = VTTL - 0.8/ Rmod. (see Figure 23).
5. 51 simulates an enable gate pulse from a microprocessor which will
enable the transmitter. (see Figure 4 to detennine precise value of the
enabling resistor based on the potential of the gate pulse and the
desired enable.)

the variable indUctor (MCI3175); 1.0 k resistor shunting the
crystal prevents it from oscillating in the fundamental mode.
Recommended source is Coilcraft "slot seven" 7.0 mm tuneable
inductor, part #7M3-821.

Figure 21 shows a typical application in which the output
power has been reduced for linearity and current drain. The
current draw on the device is 16 mA ICC (average) and
- 22_5 dBm (average power output) using a 10kHz
modulating rate for the on-off keying. This equates to 20 mA
and - 2.3 dBm "On", 13 mA and - 41 dBm "Off". In Figure
22a, the device's modulating waveform and encoded carrier

MC13175.MC13176
2·182

are displayed. The crystal oscillator enable time is needed
to set the acquisition timing. It takes typically 4.0 msec to
reach full magnitude of the oscillator waveform (see Figure
22b, Oscillator Waveform, at Pin 8). A square waveform of
3.0 V peak with a period that is greater than the oscillator
enable time is applied to the Enable '(Pin 11).

MOTOROLA COMMUNICATIONS DEVICE DATA

Figure 228. ASK Input Waveform and Modulated Carrier

Pin 16
OOK Inpul Modulation
10kHz TIL Wavefonn

On·Off Keying En·
coded
Carrier Envelope

Figure 22b. Oscillator Enable Time, Tenable

PinS
Oscillator Waveform

Figure 23. Power Output versus Modulation Current
10

. / l-

5.0

:& 0

/"

8'"5.0

VCC=3.0Vdc
f=32O MHz

;[
~

ffi

-10

~
a.

.P

,/

-15

-20
-25
0.1

,. . /
1.0
lmod, MODULATION CURRENT (mA)

MOTOROLA COMMUNICATIONS DEVICE DATA

10

Analog AM
In analog AM applications, the output amplifier's linearity
must be carefully considered. Figure 23 is a plot of Power
Output versus Modulation Current at 320 MHz, 3.0 Vdc. In
order to achieve a linear encoding of the modulating
sinusoidal waveform on the carrier, the modulating signal
must amplitude modulate the carrier in the linear portion of
its power output response. When using a sinewave
modulating signal, the signal rides on a positive DC offset
called Vmod which sets a static (modulation off) modulation
current, Imod. Imod controls the power output of the IC. As
the modulating signal moves around this static bias point the
modulating current varies causing power output to vary or
to be AM modulated. When the Ie is operated at modulation
current levels greater than 2.0 mAdc the differential output
stage starts to saturate.

MC1317S.MC13176
2-183

In the design example, shown in Figure 24, the operating
point is selected as a tradeoff between average power output
and quality of the AM.
ForVcc=3.0Vdc;ICc=18.5mAandl mo d=0.5mAdcand
a static DC offset of 1.04 Vdc, the circuit shown in Figure 24
completes the design. Figures 25a, 25b and 25cshow ihe results of - 6.9 dBm output power and 100% modulation by the
10kHz and 1.0 MHz modulating sil'lewave signals. The amplitude of the input signals is approximately 800 mVp-p.
Where Rmod = (VCC - 1.04 Vdc)/0.5 mA = 3.92 k, use
a standard value resistor of 3.9 k.

Figure 24. Analog AM Transmitter

1---3.OVdc Rmod
Data~
Input~

800mVp-p

+

6.811

Figure 25a. Power Output of Unmodulated Carrier

Figure 25b. Input Signal and AM Modulated
Carrier for fmod = 10 kHz .

MC1317S.MC13176
2-184

Figure 25c. Input Signal and AM Modulated
Carrierfor fmod = 1.0 MHz

MOTOROLA COMMUNICATIONS DEVICE DATA

Figure 26. Circuit Side View of MC1317XD

••••••••••••••••••••••••••••••••• • ••

••••.••••••••••••••••••••••
•••••••••••••••••••••••••••
...........................

···1
•••••••
.•.......

···························i·ii·il·i·i:·ii·=i:i···

• • • 11

•••••••••••••••••••••••••••

••••••
••••••

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•• •••••••
•••••••
•• ••••••••
••••••••
• ••••••••

\

••••••••••
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•• ••••••••
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•••••••••
•••••••••
•••••••••
•

4"

• ••••••••
•••••••••
•••••••••
•••••••••
•••••••••••
:::::::==:: ••••••••••••
••••••••••••••••••• •••••••••••••••••

••••••••••••••••••••••••••••••••••••••
••••••••••••••••••••••••••••••••••••••
••••••••••••••••••••••••••••••••••••••
••••••••••••••••••••••••••••••••••••••

I-

4"

--------1

Figure 27. Ground Side View

4"

IMOTOROLA COMMUNICATIONS DEVICE DATA

4"

~-~--------+l_1

MC13175.MC13176
2-185

Figure 28. Surface Mounted Components Placement
(on Circuit Side)

Figure 29. Radial Leaded Components Placement
(on Ground Side)

MC1317S.MC13176
2-186

MOTOROLA COMMUNICATIONS DEVICE DATA

MOTOROLA

-

SEMICONDUCTOR
TECHNICAL DATA

MC14411

Bit Rate Generator
The MC14411 bit rate generator is constructed with complementary MOS
enhancement mode devices. It utilizes a frequency divider network to provide a
wide range of output frequencies.
A crystal-controlled oscillator is the clock source forthe network. A 2-bit address
is provided to select one of four multiple output Clock rates.
Applications include a selectable frequency source for equipment in the data
communications market, such as teleprinters, printers, CRT terminals, and
microprocessor systems.
•
•
•
•
•
•
•
•
•
•

LSUFFIX
CERAMIC
CASE 623

PSUFFIX

Single 5.0 Vdc (±5"10) Power Supply
Internal Oscillator Crystal Controlled for Stability (1.8432 MHz)
16 Different Output Clock Rates
50% Output Duty Cycle
Programmable Time Bases for One of Four Multiple Output Rates
Buffered Outputs Compatible with Low Power TTL
Noise Immunity 45% of VDD Typical
Diode Protection on All Inputs
External Clock may be Applied to Pin 21
Internal Pull-Up'Resistor on Reset Input

PLASTIC
CASE 709

DWSUFFIX

=

SOG
CASE 751E

NOT
RECOMMENDED
FOR EW DESIGN

PIN ASSIGNMENTS
L, PSUFFIX

BLOCK DIAGRAM

RATE SELECT B _ _ _ _ _ _ _ _ _ _ _--,
(RSB)

DIVIDER

CRYSTAL OUT"
(XTALoul)

RESET'" -----~-~_+------~

DIVIDERS

Fl
F2
F3
F4
F5
F6
F7
F8
F9
FlO
Fll
F12
F13
F14

F15
F16
'See Figure 2 for 1ypical cryslal oscillaiOr circuits.
"When RESET =0, outputs Fl-FI4 =0, outputs FI5-FI6 =1.

MOTOROLA COMMUNICATIONS DEVICE DATA

1_

F3
F5
F7
Fa

2

FlO
F9
Fl1

RATE SELECT A _ _ _ _ _ _ _ _ _ _ _ _ _-,
(RSAl

CRYSTAL IN
(XTALin)

Fl

F14
RESET
NOT USED
VSS

3
4
5
6
7
8

24
23
22
21
20
19
18
17

VDD
RSA
RSB
XTALin

9
10
11
12

16
15
14
13

F4
F6
F12
F13

XTALout
F16
F15
F2

DWSUFFIX
Fl
F3

1.
2

24
23

VDD
RSA

F5
F7

3
22 RSB
XTALin
4
21
20L o u t
F a5X T A
FlO 6
19 F16
F9 7
18 F15
Fl1 8
17 F2
F14
RESET
VSS
F13

9
10
11
12

16
15
14
13

F4
F6
F12
NC

NC = NO CONNECTION

MC14411

2-187

MAXIMUM RATINGS (Voltages referenced to VSS, Pin 12)
Symbol
VDD
Yin
I
TA
Tstg

Rating

Value

Unit

D.c Supply Voltage Range

5.25 to-0.5

V

Input Voltage, All Inputs

VDD+0.5to
VSS-0.5

V

D.c .current Drain par Pin

10

rnA

Operating Temperature Range

-40to+85

D.c

Storage Temperature Range

-65to+150

D.c

This device contains circuitry to protect the inputs against damage due to high static voltages
or electric fields; however, it is advised that normal precautions be taken to avoid application of
any voltage higher than maximum rated voltages
to this high-impedance circuit. For proper operation it is recommended that Yin and Vout be constrained to the range VSS S (Vin orVoutl S VDD.
Unused Inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or
VDD)·

ELECTRI.cAL CHARACTERISTICS

Symbol

Supply Voltage

Vout

Operating Voltage

VIL
VIH

IOH
IOL
lin

Min

Max

Min

Typ

Max

Min

Max

Unit

-

4.75

5.25

4.75

5.0

5.25

4.75

5.25

V

"0" Level
"I" Level

5.0
5.0

-

0.05

-

0
5.0

0.05

-

0.05

4.95

V
V

Input Voltage

Vo = 4.5 or 0.5 V
Vo = 0.50r4.5 Vdc

5.0
5.0

-

1.5

-

-

1.5

3.5

2.25
2.75

1.5

3.5

-

3.5

-

V
V

Source
Sink

5.0
5.0

-0.23
+0.23

-

-0.20
+0.20

-1.7
+0.78

-

-0.16
+0.16

-

rnA
rnA

Pins 21 , 22, 23
Pin 10

-

-

-

±O.OOOOI

-

±1.0

5.0

Output Drive .current
VOH=2.5V
VOL=0.4V
Input .current

-

4.95

-

±0.1

-

-1.5

-

-

-

-

±0.1
-7.5

I1A
I1A

-

-

pF

15

mW

Quiescent Dissipation

5.0

Po

Power Dissipation "t
(Dynamic plus Quiescent)
(.cL = 15 pF)

5.0

trLH

Output Rise Time"
tr = (3.0 nslpF) CL + 25 ns

5.0

-

-

-

70

200

-

-

ns

trHL

Output Fall Time"
tf = (1.5 ns/pF) CL + 47 ns

5.0

-

-

-

70

200

-

-

ns

Input Clock Frequency

5.0

1.85

-

1.85

MHz

-

200

-

ns

-

500

-

ns

twIRl

RESET Pulse Width

2.5

-

PQ

tw(C)

0.015

-

-

Clock Pulse Width

-

-

Input .capacitance (Vin = 0)

2.5

5.0

4.95

.cin

fCL

t

VDO

Characteristic

VDD

+ 85DC

+ 25DC

-4O"C

Po = (7.5 mW/MHZ) f + PQ

-

-

1.85

-

200

-

200

-

500

-

500

-

mW

For dissipation at different external capacitance (CL) refer to corresponding formula:
PT (CL = PD + 2.6 x.l0-3 (CL -15 pF) VDD2f
where: PT, PD in mW, .cL in pF, VDD in Vdc, and f in MHz.

•• The formula given Is for the typical characteristics only.

=t_

2o_ns _

INPUT

VSS

:{[o
OUTPUT

Voo
VOH

_ _......:..!.L:..:%.::..;

VOL

tnH=:::;j
Figure 1_ Dynamic Signal Waveforms

MC14411
2-188

MOTOROLA COMMUNICATIONS DEVICE DATA

Table 1. Output Clock Rates

Rate Select

Output Rates (Hz)

B

A

Rate

Output
Number

X64

X16

XB

Xl

0

0

Xl

Fl

614.4k

153.6k

76.8k

9600
7200

0

1

X8

F2

460.8 k

115.2 k

57.6k

1

0

X16

F3

307.2 k

76.8 k

38.4 k

4800

1

1

X64

F4

230.4 k

57.6 k

28.8k

3600

F5

153.6k

38.4 k

19.2k

2400

F6

115.2k

28.8 k

14.4 k

1800

F7

76.8 k

19.2k

9600

1200

F8

38.4 k

9600

4800

600

F9

19.2 k

4800

2400

300

FlO

12.8 k

3200

1600

200

Fll

9600

2400

1200

150

F12

8613.2

2153.3

1076.6

134.5

F13

7035.5

1758.8

879.4

109.9

F14

4800

1200

600

75

F15

921.6k

921.6k

921.6k

921.6k

F16*

1.843M

1.843 M

1.843M

1.843M

*F16 is a buffered oscillator output

XTALin
21

D

-,::;=

5 pF

+--,

BIT RATE CLOCK OUTPUTS

::!: 12 pF ..L
'---_-+--.J
-=
20
XTALaut

Crystal Specifications
Parallel
RS

Co
Temperature Range
Test Level
Test Set

Rf=15MO±10%

Crystal Mode
Frequency 1.B432 MHzor±0.05% @13pF
540 0 max
7.0 pFmax
oto 70°C
lmW
TS - 330fTSM or Equivalent

'Suggested CIYSIaI Suppliers: TypeD, CTS Knights

Figure 2. Typical Crystal Oscillator Circuit

MOTOROLA COMMUNICATIONS DEVICE DATA

MC14411
2-189

MOTOROLA

-

SEMICONDUCTOR
TECHNICAL DATA

MC14419

2-01-8 Keypad-to-Binary
Tone Encoder
CMOS

PSUFFIX
PLASTIC
CASE64B

The MCl4419 is designed for phone and dialer system applications, but finds
many applications as a keypad-to-binary encoder. The device contains a 2-of-8 to
binary encoder, a strobe generator, and an illegal state detector. The encoder has
four row inputs and four column inputs and is designed to accept inputs from 16
keyswitches arranged in a 4 x 4 matrix. For an output on the four data lines, one
and only one row along with one and only one column input line must be activated.
All other combinations are,suppressed by the illegal state detector to eliminate
false data output.
The strobe generator produces a strobe pulse when any of the 10 keys
corresponding to numerals 0-9 are depressed. The strobe output can be used to
eliminate erroneous data entry due to contact bounce. For a strobe outputto occur,
the key row and column input lines must remain stable for 80 clock pulses after
activation. When the contact bouncer has settled and 80 clock pulses have
occurred, the output will be a single strobe pulse equal in width to that of the clock
low state. The strobe generator will output one and only one pulse each time a
numerical key is depressed. After the pulse has occurred, noise and bounce due
to contact break will not cause another strobe pulse. With a 16 kHz clock frequency, the pulse occurs 5 ms after the last bounce.
•
•
•
•
•
•
•

PIN ASSIGNMENTS
PSUFFIX

PVDD
PCLK
14 P ST
13 P D4
12 P D3
11 P D2
10 P Dl
9 PC4

Rll 1.
R2
R3

I
I

16

2

15

3

R41 4
Cll 5

Suppressed Output for Illegal Input Codes
On-Chip Pull-Up Resistors for Rowand Column Inputs
Clock Input Conditioning Circuit
Low Current Drain in Standby Mode: 5.0 IIA Typical @ 5.0 Vdc
Subsystem Complement to the MCl4408/14409 Phone Pulse Converter
Codes for Numbers 0-9 Produce a Strobe Pulse
One Key Roll-Over Feature

C21 6
C3
VSS

I
I

7
8

BLOCK DIAGRAM
Rl
R2
R3
R4

ROW {2:1
INPUTS

COLUMN {
INPUTS

NOT
RECOMMENDED
FOR NEW
DESIGN

MC14419
2-190

15j
BCD
DETECTOR

Cl
C2
C3

:
7

r-

STROBE
GENERATOR

14

C4

8

VDD=PIN16
VSS= PIN 8

CLK

T
ST

~
~

13:--+ D4 ""I
2'()F-8TO
BINARY
D3
ENCODER 12
AND
ILLEGAL
11~D2
CODE
DETECTOR

f--+

10

f--+

Dl

DATA
OUTPUTS

J

MOTOROLA COMMUNICATIONS DEVICE DATA

MAXIMUM RATINGS (Voltages referenced to VSS, Pin B)
Rating

Value

Unit

VDD

+6.0 to-0.5

V

Yin

VDD + 0.5 to
VSS-0.5

V

Symbol

DC Supply Voltage Range
Input Voltage, All Inputs
DC Current Drain per Pin
Operating Temperature Range
Storage Temperature Range

I

10

rnA

TA

-40 to + B5

°c

Tstg

- 65 to + 150

°C

This device contains circuitry to protect the inputs against damage due to high static voltages
or electric fields; however, it is advised that normal precautions be taken to avoid application of
any voltage higher than maximum rated voltages
to this high-impedance circuil. For proper operation it is recommended that Yin and Vout be constrained to the range VSS';; (Vin or Vout)';; VDD.

ELECTRICAL CHARACTERISTICS

Characteristic

Operating Voltage

"0" Level
"1" Level

Noise Immunity
(AVout'; O.B Vdc)
Output Drive Current
VOH=2.5V

Source

+B5°C

+ 25°C

Min

Max

Min

Typ

Max

Min

Max

Unit

VOO

-

3.0

6.0

3.0

5.0

6.0

3.0

6.0

V

Vout

5.0
5.0

-

0.01

-

0.05

4.99

0
5.0

0.01

-

-

4.99

-

4.95

-

V
V

VNL

5.0

1.5

-

1.5

2.25

1.4

-

Vdc

VNH

5.0

1.4

-

1.5

2.25

-

1.5

-

Vdc

IOH

5.0

-0.23

-

-0.20

-1.7

-

-0.16

-

mAdc

IOL

5.0

+0.23

+0.20

+0.7B

-

+0.16

-

mAdc

Symbol

Supply Voltage

-40°C

VOOV
dc

IIH

5.0

-

-

-

10

-

-

Pull-Up Resistor Source Current
(Rowand Column Inputs)
(Vin= VSS)

IlL

5.0

265

460

190

250

330

125

215

Input Capacitance (Vin = VSS)

Cin

-

-

-

-

5.0

-

-

-

3.0
5.0
6.0

-

3.0
15
60

-

1.0
5.0
20

3.0
15
60

-

6.0
30
120

Sink

VOL = 0.4 V
Input Leakage Current (Vin = VOO)

Standby Supply Current
(fclock = 16 kHz, No Keys Depressed)

pAdc
j.lAdc

pF
j.lAdc

10DS

Function of Clock Frequency*
(No Keys Depressed)

-

-

-

10DS = 0.091lA I kHz + 3.0 IlA

5.0

j.lAdc

* The formula given is for the typical characteristics only.
SWITCHING CHARACTERISTICS (CL = 50 pF, TA = 25°C)
Symbol

VOO

Min

Typ

Max

Unit

Output Rise and Fall Times, 01-D4 (Figure 1)

Characteristic

tr, tf

5.0

-

300

-

ns

Propagation Delay Time, Row or Column Input
to Data Output (Figure 1)

tpLH,
tpHL

5.0

-

1000

-

ns

Clock Pulse Frequency Range

PRF

3.0 to 6.0

4.0

16

20 ns

20 ns

kHz

BO

PRF Clock
Frequency (kHz)

tST*
Strobe Pulse Delay Time (ms)

4.0

20

ROWOR
COLUMN
INPUTS

VDD

8.0

10

Dn

VOH

16

5.0

VOL

32

2.5

80

1.0

VSS

OUTPUT

Figure 1_ Switching Time Waveforms

MOTOROLA COMMUNICATIONS DEVICE DATA

*tST = (1/PRF) . 80, with PRF in kHz, tST in ms

MC14419
2-191

Table 2. Truth Table
Inputs
Row

Column

Key"

R4

R3

R2

Rl

C4

C3

1

1

1

1

0

1

2

1

1

1

0

Outputs

C2

Cl

04

03

02

01

Strobe

1

1

0

0

0

0

1

1

1

0

1

0

0

1

0

JL
JL
JL

3

1

1

1

0

1

0

1

1

0

0

1

1

A

1

1

1

0

0

1

1

1

1

1

0

0

4

1

1

0

1

1

1

1

0

0

1

0

0

5

1

1

0

1

1

0

0

1

0

1

0

1

6

1

1

0

1

1

1

1

1

0

1

1

0

B

1

1

0

1

0

1

1

1

1

1

0

1

7

1

0

1

1

1

0

1

0

0

1

1

1

B

1

0

1

1

1

1

0

1

1

0

0

0

9

1

0

1

1

1

1

1

1

1

0

0

1

c

0

JL
JL
JL
0

JL
JL
JL

.

1

0

1

1

0

0

1

1

1

1

1

0

0

0

1

1

1

1

1

1

0

1

0

1

0

0

0

0

1

1

1

1

1

0

1

0

0

0

0

JL

#

0

1

1

1

1

0

1

1

1

0

1

1

0

0

0

1

1

1

0

1

1

1

1

1

1

1

0

0

0

0

0

0

All Other Combinations
"See Figure 3 for keypad designation.

CONTACT
MAKE
BOUNCE

NOISE
SPIKE

ROW OR -----,~IT:l'"7"'T"7-r.
COLUMN
INPUT

I+- 1sT -+II--

n

CONTACT
BREAK
BOUNCE

I
PWST"

STROBE
ES
GENERATOR _ _ _ _ _ _ _80_C_LO_C_K_P_UL_S_
. ..I '-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
OUTPUT
..
"PWST = Strobe Pulse Width = Low State Clock Pulse Width (PWLl.

Figure 2. Strobe Generator Timing Diagram

MC14419
2-192

MOTOROLA COMMUNICATIONS DEVICE DATA

KEYPAD WITH OPST
N.O. SWITCHES

VOO

4x4KEYPAO

15

A,

10
COMMON

Rl

01
11
02

R2

12

MC14419

03

OR

13

R3

04

KEYPAD WITH SPST
N.O. SWITCHES

14
05

R4
C4

C3

C2

Cl

COMMON

Figure 3. Typical Keypad Interface Application

MOTOROLA COMMUNICATIONS DEVICE DATA

MC14419
2-193

MOTOROLA

-

SEMICONDUCTOR
TECHNICAL DATA

MC14469

I

Addressable Asynchronous
Receiver/Transmitter
.
CMOS

PSUFFIX

The MC14469 receives one or two 11-bit words in a serial data stream. One of
the incoming words contains the address and when the address matches, the
MC14469 then transmits information in two 11-bit word data streams. Each of the
transmitted words contains 8 data bits, an even parity bit, and start and stop bits.
The received word contains 7 address bits with the address olthe MC14469 set
on seven pins. Therefore, 27 or 128 units can be interconnected in simplex or
full-duplex data transmission. In addition to the address received, seven command
bits may be received for general-purpose data or control use.
The MC14469 finds application in transmitting data from remote analog-todigital converters, remote MPUs, or remote digital transducers to the master
computer or MPU.
•
•
•
•
•
•
•
•

PLASTIC
CASE 711

FN SUFFIX
PLCC
CASE 777

Supply Voltage Range: 4.5 V to 18 V
Low Quiescent Current: 75 !LA Maximum @ 5 V, 25°C
Guaranteed Data Rates to 4800 Baud @ 5 V, to 9600 Baud @ 12 V
Receive - Serial to Parallel
Transmit - Parallel to Parallel
Transmit and Receive Simultaneously in Full Duplex
Crystal or Resonator Operation for On-Chip Oscillator
See Application Note AN806A
Chip Complexity: 1200 FETs or 300 Equivalent Gates

ORDERING INFORMATION
MC14469P
MC14469FN

Plastic DIP
PLCC

PIN ASSIGNMENTS
PSUFFIX
OSCl

VDD

OSC2
RESET
AO
Al
A2
A3

CO
Cl
C2
C3
C4
C5

A4
AS

C6
CS

A6
IDO
IDl
ID2

YAP
SEND
SO
Sl

ID3
ID4
ID5
ID6
ID7
RI
Vss

MC14469
2-194

FNSUFFIX

12
13

29
28

14
15
16
17
18
19
20

27
26
25
24
23
22
21

S2
53

54
55
56
57

:;:

It;; ~
omen
«a:O

0

~~8o~~

1 44 43 42 41 40
39
7
8
9
10
11
12
13
14
15
31
16
17
29
18 19 20 21 22 23 24 25 26 27 28
6 5 4 3

A2
A3
A4
AS
A6
NC
IDO
IDl
ID2
ID3
104

(3
rn

'"
9

_
Q b

•

a: :::>~ ()
z

1°g:

S5 33

C4
C5
C6
CS
YAP
NC
SEND
SO
Sl
S2
S3

18(l1j

NC = NO CONNECTION

TRO

MOTOROLA COMMUNICATIONS DEVICE DATA

BLOCK DIAGRAM

RECEIVE
(AG-A6)
ADDRESS

(CO-C6)
COMMAND DATA

B

J7t

ADDRESS CONTROL
AND DATA COMPARATOR

COMMAND
LATCHES

RVAL

~

>-

RECEIVE
DATA
STROBE

"Ft

CLOCK

COMPARE
RECEIVE
DATA
(RI)

I
I

-

STROBE

STATIC SHIFT REGISTER

CLOCK

I
COMMAND
STROBE (CS)

TIMING AND CONTROL
AND PARITY CHECK

RECEIVE DATA
STROBE ENABLE

I

SEND ENABLE
LATCH (SEL)
VALID ADDRESS
PULSE (VAP)

TRANSMIT

(S0-57)
STATUS

100-107
INPUT DATA

STATIC SHIFT REGISTER

2
SEND

LOAD
SELECT

OUTPUT
LOGIC

TRANSMIT
DATA (TRO)

CONTROL AND PARITY
GENERATOR

SEND ENABLE
DATA RATE CLOCK

RVAL

CLOCKS
OSCl

DATA RATE CLOCK

OSC2

RECEIVE DATA STROBE
RECEIVE DATA STROBE ENABLE

MOTOROLA COMMUNICATIONS DEVICE DATA

MC14469
2-195

MAXIMUM RATINGS (Voltages referenced to VSS)
Rating
DC Supply Voltage
Input Voltage, All Inputs

Symbol

Value

Unit

VDD

-0.5to+18

V

Yin

-0.5 to VDD + 0.5

V

I

10

mA

TA

-40to+85

"C

Tstg

-65to+150

"C

DC Current Drain per Pin
Operating Temperature Range
Storage Temperature Range

This device contains circuitry to protect the inputs against damage due to high static voltages
or electric fields; however, it is advised that normal precautions be taken to avoid application of
any voltage higher than maximum rated voltages
to this high-Impedance circuit. For proper operation It Is recommended that Yin and Vout be cOnstrained to the range VSS ~ (Vin orVoutl ~VDD.

Unused inputs must always be tied to an
appropriate logic voltage level (e.g., either
VSS orVDD)·

ELECTRICAL CHARACTERISTICS (Voltages referenced to VSS)
-40"C
Characteristic

Min

Max

Min

Max

Min

Max

Unit

VOL

5.0
10
15

-

0.05
0.05
0.05

-

-

0.05
0.05
0.05

-

-

0.05
0.05
0.05

V

5.0
10
15

4.95
9.95
14.95

4.95
9.95
14.95

-

4.95
9.95
14.95

-

V

-

5.0
10
15

-

1.5
3.0
4.0

-

1.5
3.0
4.0

-

1.5
3.0
4.0

V

5.0
10
15

3.5
7.0
11

-

-

3.5
7.0
11

-

-

3.5
7.0
11

-

-

-O.B
-0.16
-0.4
-1.2

-

-

-0.6
-0.12
-0.3
-1.0

0.44
1.1
3.0

-

0.36
0.9
2.4

-0.16
-0.035
-0.08
-0.27

-0.13
-0.03
-0.06
-0.2

0.085
0.14
0.42

-

0

Yin =VDD or 0
"I" Level

+ 85"C

VDO

Output Voltage
"0" Level

+ 25"C

Symbol

VOH

Vin=OorVDD

-

-

-.

-

Input Voltage (Except OSC1)
"0" Level

VIL

Vo = 4.5 or 0.5 V
Vo = 9.0 or 1.0 V
Vo = 13.5 or 1.5 V
"I" Level

VIH

Vo = 0.5 or 4.5 V
Vo = 1.0 or 9.0 V
Vo = 1.5 or 13.5 V

Output Drive Current (Except OSC2)
VOH=2.5V
VOH=4.6V
VOH=9.5V
VOH= 13.5V
VOL=0.4V
VOL = 0.5 V
VOL=I.5V
Output Drive Current (OSC2 Only)
VOH=2.5V
VOH=4.6V
VOH=9.5V
VOH= 13.5V
VOL = 0.4 V
VOL=0.5V
VOL=I.5V

OSC Frequency"

Source

IOH

5.0
5.0
10
15

-1.0
-0.2
-0.5
-1.4

Sink

.iOL

5.0
10
15

0.52
1.3
3.6

-

-

Source

IOH

5.0
5.0
10
15

-0.19
-0.04
-0.09
-0.29

Sink

IOL

5.0
10
15

0.1
0.17
0.5

-

fOSC

4.5
12

0
0

400
800

0
0

365
730

0.07
0.1
0.3

-

V

mA

mA

-

-

mA

mA

-

kHz

0

310
620

lin

15

-

±0.3

-

±0.3

-

±1.0

I1A

Pull-Up Current (AO-A6, IDO-I07)

IUp

15

12

120

10

100

8.0

85

I1A

Input Capacitance (Vln = 0)

Cin

-

-

-

-

7.5

-

-

Quiescent Current (Per Package)

IDD

5.0
10
15

-

75
150
300

-

+4.5

+18

Input Current

Supply Voltage

VDD

-

-

-

75
150
300

+4.5

+18

-

-

pF

-

I1A

-

565
1125
2250

+4.5

+18

V

"310kHz at 85"C guarantees 4800 baud; 620 kHz at 85°C guarantees 9600 baud.

MC14469
2-196

MOTOROLA COMMUNICATIONS DEVICE DATA

RECEIVE DATA (RI)

I-

-'STrTTTTTT
~ L L L L L L
MCl4469
PIN DESIGNATION
MC6850
PIN DESIGNATION

I-

-I

ADDRESS

~ J" J" J" J" J" J" ~JSp

I,!!~
~ ~ SP •

I

ADDRESS
IDENTIFIER
(HIGH LOGIC LEVEL)

AO A1 A2 A3 A4 AS A6

"I

COMMAND

CO C1 C2 C3 C4 C5 C6
DO 01 02 03 04 05 06

DO 01 02 03 D4 05 06

COMMAND
IDENTIFIER
(LOW LOGIC LEVEL)

TRANSMIT DATA (TRO)

""-----

INPUT DATA - - - - - <..~I·----- STATUS ------~I

r::::o-

r

_ _ _-'1 ST

r

r

r

r

r

r , ~n r;::;:'1 --, --, --, --, --, --, --, --, :-l

L .L .L .L .L .L .L .L .LP~ST L .L .L .L .L .L .L .L -L p .....I_SP_ __

MC14469
PIN DESIGNATION
MC6850
PIN DESIGNATION
ST =START BIT
P =PARITY BIT
SP = STOP BIT

r

100 101 102 103 104 105 106 107

SO Sl S2 S3 54 S5 S6 S7

DO 01 02 03 04 05 06 07

DO 01 02 03 04 05 06 07

AO - A6 =ADDRESS BITS
CO- C6 =COMMAND BITS
00- 07 = ACIA BUS BITS

100 - 107 =MCl4469 IDENTIFICATION CODE
SO -S7 =MCl4469 STATUS CODE

Figure 1. Data Format and Corresponding Data Position and Pins for MC14469 and MC6850

ADDRESS
,-------A-----,

M
~

SOl 2 3 4 5 6 7

M

COMMAND
~
S.-------A-----P SOl 2 3 4 5 6 7

S

TP:.......--------~=:_=.:~::-==---------

III~ ~ ~ ~ ~ ~ :r"LE.Qill~~~~~~ LfrJ

RECEIVER INPUT (RI)

I
I
VALID ADDRESS PULSE--f1

NAP)

--------------------------------------------------I

INTERNAL VALID
:1
ADDRESS LATCH---r
(VAL)
I

:Ir------.LJ

INTERNAL SEND
ENABLE LATCH ---r
(SEL)

I
I

h. .__-:-__________________

COMMAND STROBE _ _ _ _ _ _ _ _ _.....
OUTPUT (CS)

....:...._----'rT-l. ._________________

SENDINPUT _ _ _ _ _ _ _ _ _
(SEND)

I
M
M
I S S
I
B
S
B
S
IXOxOxOxOxOxT P'.L!:.I"L!J.:J.:J.:J.:J.:J.:.L;
IS'xOxOxOxOxOxOxT)(I.LI:..J.!I
P' P_ _
TRANSMIT OUT _ _ _ _ _ _ _ _ _ _ _ _---1. s°Xox
J.::J..:J.:J.:J.:J.:J.:J.:.L;

fS

(TRO)

T01234567
10

P

T01234567
STATUS

Figure 2. Typical Receive/Send Cycle

MOTOROLA COMMUNICATIONS DEVICE DATA

MC14469
2-197

PIN DESCRIPTIONS
AO-AS
Address Inputs
These inputs are the address setting pins which contain the
address match for the received signal. Pins Ao-AS have
on-chip pull-up resistors.
CD-CS
Command Word
These pins are the readout of the general-purpose command word which is the second word of the received signal.
CS
Command Strobe
This is the output for the command strobe signifying a valid
set of command data (CO-CS). The pulse width is one oscillator cycle. For eample, when a 307.2 kHz ceramic resonator is
usd, the pulse width is approximately 3 1lS.
100-107
Input Data Pins
These pins contain the input data for the first eight bits of
data to be transmitted. Pins 100-107 have on-chip pull-up
resistors.
OSC1,OSC2
Oscillator Input and Oscillator Output
These pins are the oscillator input and output (see
Figure 3).
RESET
Reset
When this pin is pulled low for a minimum of 700 ns, the
circuit is reset and ready for operation.
RI
Receive Input
This is the receive input pin.
S0-S7
Second or Status Input Data
These pins contain the input data for the second 8 bits of
data to be transmitted.
SEND
Send
This pin accepts the send command after receipt of an
address.
TRO
Transmit Register Output Signal
This pin transmits the outgoing signal. Note that it Is Inverted
from the incoming signal. It must go through one stage of inversion Hit is to drive another MC14469.

MC14469
2-198

VAP
Valid Address Pulse
This is the output for the valid address pulse upon receipt
of a matched incoming address.
VOO
Positive Power Supply
This pin is the package positive power supply connection.
This pin may range from + 4.5 V to + 18 V with respectto VSS.
VSS
Negative Power Supply
This pin Is the negative power supply connection. Normally
this pin is system ground.

OPERATING CHARACTERISTICS
The receipt of a start bit on the receive input (RI) line
causes the receive clock to start at a frequency equal to that
of the oscillator divided by 64. All received data is strobed in
at the center of a receive clock period. The start bit is followed
by 8 data bits. Seven of the bits are compared against states
of the address of the particular circuit (Ao-AS). Address is
latched 31 clock cycles after the end of the start bit of the
incoming address. The eighth bit signifies an address word
"1" or a command word ·0". Next, a parity bit is received and
checked by the internal logic for even parity. Finally a stop
bit is received. At the completion of the cycle if the address
matches, a valid address pulse (VAP) occurs. Immediately
following the address word, a command word is received. It
also contains a start bit, eight data bits, even parity bit, and
a stop bit. The 8 data bits are composed of a seven-bit command, and a "0" which indicates a command word. At the end
of the command word a command strobe pulse (CS) occurs.
A positive transition on the send input initiates the transmit
sequence. Send must occur within 7 bit times of CS. Again
the transmitted data is made up of two eleven-bit words, i.e.,
address and command words. The data portion of the first
word is made up from input data inputs (100-ID7), and the
data for the second word from second input data (So-S7) Inputs. The data on inputs 100-107 is latched one clock before
the falling edge of the start bit. The data on inputs S0-S7
is latched on the rising edge of the start bit. The transmitted
signal is the inversion of the received signal, which allows the
use of an inverting amplifier to drive the lines. TRO begins
either 1/2 or 1-112 bit times after send, depending where send
occurs.
The oscillator can be crystal controlled or ceramic resonator controlled for required accuracy. OSCl can be driven
from an external oscillator (see Figure 3).

MOTOROLA COMMUNICATIONS DEVICE DATA

VDATA
1.0kQ
1...-_ _....._ _ _....._ _ _ _ _. -_ _ DATA LINE

r----.-+----+-----+~~ GROUND LINE

OSCl

OSC2

.....___1...5"'MI\Q~_ _.. Note: for extemally
generated ctock,
drive OSC1, float OSC2 .

....-------iDI----.
Xl

VDD

1. 0 l1 F
Xl = Ceramic Resonator: 307.2 kHz ± 1 kHz for 4800 baud rale.
Cl and C2 are sized per the ceramic resonator supplier's recommen·
dation.

MC14469

~~--iVSS

Ceramic Resonator Suppliers:'
1. Morgan Matroc, tnc., Bedford, OH, 216/232-8600
2. Radio Materials Co., Attica, IN, 317n62-2491
*

Motorola cannot recommend one supplier over another and in no way
suggests that this Is a complete listing of ceramic resonator suppliers.

Figure 3, Oscillator Circuit

Figure 4. Rectified Power from Data Lines Circuit

CO
Cl

CHANNEL
SELECT

C2
CS

SELECT
CHANNEL,
START
CONVERSION

SEND

END
CONVERSION

MCl4469

ANALOG
INPUTS

SO
Sl
S2
S3

54

DIGITAL
OUTPUTS

S5
S6
S7
a·CHANNEL

NO
CONVERTER
ASSEMBLY

Figure 5, A-D Converter Interface

MOTOROLA COMMUNICATIONS DEVICE DATA

MC14469
2-199

V+
1k

MPS·DOS
10 k
10 k

10 k

RI
VSS

RI
VDD

1--+--'

MC68S0
ACIA
OR
UART

VSS

-=-

10 k

RI
VDD

TRO
VSS

ID7

-=-

S7 MC14469
0
AO,IDO
A1,ID1
A2,ID2
A3,ID3
A4,ID4
CS
AS,IDS
A61D6
SEND

10k

RI
VDD

TRO

ID7

-=-

10k

-=-

A1,ID1
A2,ID2
A3,ID3
A4,ID4
AS,IDS
A61D6

ADDRESS
0000001

VSS

ID7

-=-

S7 MC14469
1

TRO

-=-

S7 MC14469
127

-=ADDRESS
1111111

CS
SEND

CS
SEND

-=- ~£~~~~S
MASTER
STATION

REMOTE MC14469
STATIONS

Note: For simplex operation the 107 must be tied high, 57 must be tied low and the
7·blt ID must be the same as the 7·bit address (or set to some unused address)
to prevent erroneous responses. ,

Figure 6. Single Line, Simplex Data Transmission

vDD
1k

1k

10 k

10 k

;:t

mL(
RI

TRO
VSS
MC6850
ACIA
OR
UART

1
I
I

::
::

I

JJ

1
1
1

10 k

10 k

;r

rl:

10 k ~

10 k ,

1
1

-

RI
VDD

-=- 1

ADDRESS
0000000

AO
A1
"-:- A2
~ A3
I-- A4
f-- AS
f-- A6

TRO
VSS 1---< ......

1
1

'-

I-I--

:::::J

I-I--

A1
A2
A3
A4
AS
A6

YAP
SEND

rl:

10k ~

10 k

TRO
VSS I--- - - - - - - -E91' I~D~
Cl I C2

Note: Maximum key contact resistance = 1kG

Figure 3. 64-Key Keyboard
A

START BIT

B

C

o

E

F

INSTRUCTION,_ _ _-t

FSK

AM

KEY WORD

r-

ONE WORD

!t-__

D_EB_OU_NC_E__
20ms

~!~~9~m~s~~!________~~~____~1

----1:

~I

99ms

_~~I

Figure 4. Transmitted Waveforms and Timing (not drawn to scale)

MOTOROLA COMMUNICATIONS DEVICE DATA

MC14497
2-205

AI

A2

~

LJ

LJ

A3

A4

~

~S

LJ
Figure 5. Scanner Output Timing Diagram

loon

-=

0.10

-=

lN4001
100n

~
Y

Y

18

~

lkO

MC14497

-=

KEYBOARD

~
~
~
-=

'Visible Indicator

-=

-=

Cl and C2 are sized per lIle ceramic resonator supplier's recommendation.
Ceramic Resonator Suppliers:
1. Morgan Matrox, Inc., Bedford, OH, 2161232·8600
2. Radio Materials Co., Attica, IN, 3171762·2491
Motorola cannot recommend one supplier over another and in no way suggests that this is a complete listing of ceramic resonalor suppliers.

Figure 6. Typical Application Circuit

MC14497
2-206

MOTOROLA COMMUNICATIONS DEVICE DATA

AGCBURST

2.84ms

1.155ms

540
fl s

B

A

Start Bit

590
fl s

1.1 ms

540
fls

D

C

540
fl s

F

E

590
fl s

590
fl s

540
flS

1.16ms

540
fls

540
fls

Notes:
1. 14 = 28.4 kHz.
2. Indicaled time durations are approximated.

Figure 7. AM Mode Transmitted Wavetrain with 455 kHz Oscillator

Table 2. Transmitted Codes
Channel

F

E

0

0

0

CodeWord
0
B
C

A

Keyboard
In
Out

Channel

F

E

1

0

CodeWord
0
C
B

A

Keyboard
In
Out

0

0

0

EB

A4

32

0

0

0

EBa

1

0

0

1

E1

A4

33

0

0

1

E1a

A4

2

0

1

0

E2

A4

34

0

1

0

E2a

A4

3

0

1

1

E3

A4

35

0

1

1

E3a

A4

4

1

0

0

E4

A4

36

1

0

0

E4a

5

1

0

1

E5

A4

37

1

0

1

E5a

A4
A4

6

1

1

0

E6

A4

3B

1

1

0

E6a

A4

7

1

1

1

E7

A4

39

1

1

1

E7a

A4

0

0

0

E8

A1

40

0

0

0

E8a

A1

8

0

0

0

1

1

0

0

1

A4

9

0

0

1

E1

A1

41

0

0

1

E1a

A1

10

0

1

0

E2

A1

42

0

1

0

E2a

A1

11

0

1

1

E3

A1

43

0

1

1

E3a

A1

12

1

0

0

E4

A1

44

1

0

0

E4a

A1

13

1

0

1

E5

A1

45

1

0

1

E5a

A1

14

1

1

0

E6

A1

46

1

1

0

E6a

A1

15

1

1

1

E7

A1

47

1

1

1

E7a

A1

0

0

0

E8

A3

48

0

0

0

E8a

A3

17

0

0

1

E1

A3

49

0

0

1

E1a

A3

18

0

1

0

E2

A3

50

0

1

0

E2a

A3

19

0

1

1

E3

A3

51

0

1

1

E3a

A3

20

1

0

0

E4

A3

52

1

0

0

E4a

A3

21

1

0

1

E5

A3

53

1

0

1

E5a

A3

22

1

1

0

E6

A3

54

1

1

0

E6a

A3

23

1

1

1

E7

A3

55

1

1

1

E7a

A3

16

0

1

0

1

1

0

0

0

0

E8

A2

56

0

0

0

E8a

A2

25

0

0

1

E1

A2

57

0

0

1

E1a

A2

26

0

1

0

E2

58

0

1

0

E2a

A2

27

0

1

1

E3

59

0

1

1

E3a

A2

28

1

0

0

E4

60

1

0

0

E4a

A2

29

1

0

1

E5

A2
A2
A2
A2

61

1

0

1

E5a

A2

30

1

1

0

E6

A2

62

1

1

0

E6a

A2

1

1

1

E7

A2

Not
Transmitted

1

1

1

E7a

A2

24

31

0

0

1

1

1

1

1

1

1

1

1

1

NOTE: Although the "a" suffix applies to a phantom input when
using a keyboard with up to 64 keys, the coding is identical with
a 32-key keyboard when switch FK3 is closed.

MOTOROLA COMMUNICATIONS DEVICE DATA

MC14497

2·207

MOTOROLA

MC33102

SEMICONDUCTOR-----TECHNICAL DATA

Advance Information
Sleep-Mode™ Two-State,
Micropower Operational Amplifier

DUAL SLEEP-MODETM
OPERATIONAL AMPLIFIERS
SILICON MONOLITHIC
INTEGRATED CIRCUIT

The MC33102 dual operational amplifier is an innovative design concept
employing Sleep-Mode™ technology. Sleep-Mode amplifiers have two
separate states, a sleepmode and an awakemode. In sleep mode, the
amplifier is active and waiting for an input signal. When a signal is applied
causing the amplifier to source or sink 160 I1A (typically) to the load, it will
automatically switch to the awakemode which offers higher slew rate, gain
bandwidth, and drive capability.
• Two States: "Sleepmode" (Micropower) and "Awake mode"
(High Performance)
• Switches from Sleepmode to Awakemode in 4.0 I1s when Output Current
Exceeds the Threshold Current (RL = 600 Q)
• Independent Sleepmode Function for Each Op Amp

o SUFFIX
PLASTIC PACKAGE
CASE 751
(SO-8)

B~
1

• Standard Pinouts - No Additional Pins or Components Required
• Sleepmode State - Can Be Used in the Low Current Idle State as a Fully
Functional Micropower Amplifier
• Automatic Return to Sleepmode when Output Current Drops Below
Threshold
• No Deadband/Crossover Distortion; as Low as 1.0 Hz in the Awakemode

PSUFFIX
PLASTIC PACKAGE
CASE 626

• Drop-in Replacement for Many Other Dual Op Amps
• ESD Clamps on Inputs Increase Reliability without Affecting Device
Operation
TYPICAL SLEEPMODElAWAKEMODE PERFORMANCE
Sleepmode
(Typical)

Awakemode
(Typical)

45

750

IlA

Low Inpul Offset Voltage

0.15

0.15

mV

High Output Current Capability

0.15

50

mA

Low T.C. of Input Offset Voltage

1.0

1.0

IlV/o C

High Gain Bandwidth (@20kHz)

0.33

4.6

MHz

High Slew Rate

0.16

1.7

V/IlS

28

9.0

nVNHz

Characteristic
Low Current Drain

Low Noise (@ 1.0 kHz)

Unit

PIN CONNECTIONS

Vee

Output 1

Output 2
Inputs 1 {
}

VEE

~puts

(Dual Package,

MAXIMUM RATINGS
Ratings
Supply Voltage (VCC to VEE)

Top View)
Symbol

Value

Unit
V

Vs

+36

VI DR
VIR

(Note 1)

Output Short Circuit Duration (Note 2)

tsc

(Note 2)

sec

Maximum Junction Temperature
Storage Temperature

TJ
Tstg

+150
-{l5 to +150

°C

Maximum Power Dissipation

PD

(Note 2)

mW

Input Differential Voltage Range
Input Voltage Range

V

NOTES: 1. Either or both Input voltages should not exceed vee or VEE.
2. Power dissipation mustbe considered to ensure maximum junction temperature (TJ) is not
exceeded (refer to Figure 1).

ORDERING INFORMATION
Device

Temperature Range

MC33102D
MC33102P

-40° to +85°C

Package
SO-8
Plastic DIP

This document contains information on a new product. Specifications and information herein are subject to change without notice.

MC33102
2-208

MOTOROLA COMMUNICATIONS DEVICE DATA

Simplified Block Diagram

Fractional
load Current
Detector

-

Current
Threshold
Detector

Awake to
Sleepmode
Delay Circuit

%otll

i
"'-.-=:--+--'

IHysteresis

>-+---1----1>--1
CStorage

~ IEnable

;h

Vout

Sleepmode
Current
Regulator

Enable

Awakemode
Current
Regulator

DC ELECTRICAL CHARACTERISTICS (VCC = +15 V, VEE =-15 V, TA = 25°C, unless otherwise noted.)
Figure

Symbol

Input Offset Voltage (RS = 50 n, VCM = 0 V, Va = 0 V)
Sleepmode
TA = +25°C
TA = -40° to +85°C
Awakemode
TA = +25°C
TA = -40° to +85°C

2

IVlol

Input Offset Voltage Temperature Coefficient
(RS = 50 n, VCM = 0 V, Va = 0 V)
TA = -40° to +85°C (Sleepmode and Awakemode)

3

tNIOlllT

4,6

ItB

Characteristics

Input Bias Current (VCM = 0 V, Va = 0 V)
Sleepmode
TA = +25°C
TA = -40° to +85°C
Awakemode
TA = +25°C
TA = -40° to +85°C
Input Offset Current (VCM = 0 V, Va = 0 V)
Sleepmode
TA = +25°C
TA = -40° to +85°C
Awakemode
TA = +25°C
TA = -40° to +85°C

MOTOROLA COMMUNICATIONS DEVICE DATA

Min

Max

Unit
mV

-

0.15

-

0.15

-

-

-

Typ

-

-

2.0
3.0
2.0
3.0
jlV/oC

-

1.0

-

-

8.0

50
60

-

100

nA

-

500
600
nA

IttOI

-

0.5

-

5.0

-

5.0
6.0
50
60

MC33102
2-209

DC ELECTRICAL CHARACTERISTICS (VCC = +15 V, VEE = -15 V, TA = 25°C, unless otherwise noted.)
Characteristics
Common Mode Input Voltage Range
(&VIO = 5.0 mV, Vo = 0 V)
Sleepmode and Awakemode
Large Signal Voltage Gain
Sleepmode (RL = 1.0 Ma)
TA=+25°C
TA = -40° to +85°C
Awakemode (VO = ±10 V, RL = 600 a)
TA=+25°C
TA = -40° to +85°C
Output Voltage Swing (VIO = ±1.0 V)
Sleepmode (VCC = +15 V, VEE = -15 V)
RL=1.0Ma
RL= 1.0 Ma
Awakemode (VCC= +15 V, VEE=-15V)
RL=600a
RL= 600 a
RL=2.0kn
RL=2.0kn
Awakemode (VCC = +2.5 V, VEE = -2.5 V)
RL=600a
RL=600a

Figure

Symbol

5

VICR

-

7

Max

-14.8
+14.2

kVN

AVOL
25
15

200

50
25

700

-

-

V

VO+
Vo-

+13.5

VO+
VoVo+
Vo-

+12.5

Vo+
Vo-

Power Supply Rejection (VCcNEE = +15 V/-15 V,
5.0 V/-15 V, +15 V/~.O V)
Sleepmode and Awakemode

12

-

-

+13.3

+1.1

13,14

Output Short Circuit Current (Awakemode)
(VIO = ±1.0 V, Output to Ground)
Source
Sink

15,16

+14.2
-14.2
+13.6
-13.6
+14
-14

-12.5
-1.1

80

90

-

CMR

V

-13.3

+1.6
-1.6

PSR

dB
dB

100

(1A

IITH11

IITH21

200
250

160
200

-

-

142
180

90
140
mA

Iisci
50
50

17

-

-13.5

-

80

Output Transition Current
Sleepmode to Awakemode (Source/Sink)
(Vs =±15 V)
(Vs=±2.5V)
Awakemode to Sleepmode (Source/Sink)
(Vs =±15 V)
(Vs=±2.5V)

Unit

+13

8,9,10

11

MC33102
2-210

Typ

V
-13

Common Mode Rejection (VCM = ±13 V)
Sleepmode and Awakemode

Power Supply Current (per Amplifier) (ACL = 1, Vo = OV)
Sleepmode (Vs = ±15 V) .
TA=+25°C
TA = -40° to +85°C
Sleepmode (VS = ±2.5 V)
TA=+25°C
TA = -40° to +85°C
Awakemode (Vs = ±15 V)
TA=+25°C
TA = -40° to +85°C

Min

110
110

(1A

10

-

45
48

65
70

38
42

-

750
800

800
900

65

MOTOROLA COMMUNICATIONS DEVICE DATA

AC ELECTRICAL CHARACTERISTICS (VCC = +15 V, VEE = -15 V, TA = 25°C, unless otherwise noted.)
Figure

Symbol

Slew Rate (Vin = -5.0 V to +5.0 V, CL = 50 pF, AV = 1.0)
Sleepmode (RL = 1.0 Mn)
Awakemode (RL = 600 n)

Characteristics

18

SR

Gain Bandwidth Product
Sleepmode (I = 10kHz)
Awakemode (I = 20 kHz)

19

Sleepmode to Awakemode Transition Time
(ACL = 0.1, Vin = a V to +5.0 V)
RL= 600n
RL= 10 kn

20,21

Awakemode to Sleep mode Transition Time

22

Unity Gain Frequency (Open-Loop)
Sleepmode (RL = 100 kn, CL = a pF)
Awakemode (RL = 600 n, CL = a pF)
23,25

Phase Margin
Sleepmode (RL = 100 kn, CL = a pF)
Awakemode (RL = 600 n, CL = a pF)

24,26

29

Power Bandwidth (Awakemode)
(VO = 10 Vp_p , RL = 100 kn, THD $1%)
Total Harmonic Distortion (VO = 2.0 Vp_p, AV = 1.0)
Awakemode (RL = 600 n)
1= 1.0 kHz
1= 10kHz
1= 20 kHz
DC Output Impedence (VO =
Sleepmode
Awakemode

a V, AV= 10, IQ = 10 IlA)

Differential Input Resistance (VCM =
Sleepmode
Awakemode

30

31

0.10
1.0

0.16
1.7

-

0.25
3.5

0.33
4.6

-

MHz

GBW

Ils

ttr1

ttr2

AM

0M

-

4.0
15

-

-

1.5

-

32

Equivalent Input Noise Current (I = 1.0 kHz)
Sieepmode
Awakemode

33

-

200
2500

-

-

13
12

-

-

60
60

-

-

120

-

-

20

-

-

dB

Degrees

CS

dB
kHz

THD

%

-

-

0.005
0.016
0.031

-

-

1.0 k
96

-

-

1.3
0.17

-

-

0.4
4.0

-

-

-

28
9.0

-

-

0.01
0.05

n

RO

Mn

pF

-

en

in

sec
kHz

Cin

Equivalent Input Noise Voltage (I = 1.0 kHz, RS = 100 n)
Sleepmode
Awakemode

Unit

V/IlS

Rin

a V)

MOTOROLA COMMUNICATIONS DEViCE DATA

Max

BWp

a V)

Differential Input Capacitance (V CM =
Sleepmode
Awakemode

Typ

IU

Gain Margin
Sleepmode (RL = 100 kn, CL = a pF)
Awakemode (RL = 600 n, CL = a pF)

Channel Separation (I = 100 Hz to 20 kHz)
Sleepmode and Awakemode

Min

nVNHz

pAf{Hz

-

-

MC33102
2-211

Figure 1. Maximum Power Dissipation
versus Temperature

§:

Figure 2. Distribution of Input Offset Voltage

.§. 2500

~~~~~~~~~~mooo.~~
[Ill Percent Sleepmode

z

o

~

~ 2000

en
is
a:
~

.......

I'--

1500

o
0.

~

1000

~
12

'"
r--

MC33102D

~

~
::;; 500

~

.§.
Cl

a..

u::

MC33102P

............

::J
0.

~
o

---- --r-=:::::
...........

30I---t--r-+--

LL

~ r-....

o
25
50
85
TA, AMBIENT TEMPERATURE (OC)

0-55 -40 -25

• Percent Awakemode
40 r----,--;---r--f--+_

w

!z

20 r--i---i--+--

~~

101---!---f--mr\l-

w

125

0.8

Figure 3. Input Offset Voltage Temperature
Coefficient Distribution

Figure 4. Input Bias Current versus
Common Mode Input Voltage
:«10.5

!!ill
C
en
a:
W

u::

30 •

oS

Percent Sleep mode
Percent Awakemode

IZ
W

a:
a:
::J 9.5

25~-+--+-~--~--

0

en

::J
0.

~
~

15
~

11i

201---+--+---+---lilE

I::J
0.

15r--1--r-1--

10~

\.

,"
" """

"

8.5

Awakemode

Cl

0

10I---t-+-H.

::;; 7.5
0.
w

0.

5.1---+--+---l!i;
o

W

....I

en

Q5.0 -4.0 -3.0 -2.0 -1.0
0
1.0 2.0 3.0 4.0 5.0
TCVIO, INPUT OFFSET VOLTAGE TEMPERATURE COEFFICIENT (jtVf<'C)

Figure 5. Input Common Mode Voltage Range
versus Temperature

----- --- ---'--""
VCC=+15V
VEE=-15V
,1,VIO= 5.0 mV

I

VE~55 -40

MC33102
2-212

i .

1
...........

~

~

--- --=-

...-=-

---- r-

Awakemode

o
25
50
85
TA, AMBIENT TEMPERATURE (OC)

/.

"=-"

~

~

~

~

~

125

70

iii

'"
~

~
15

60

li!

~M
~
~

100 oS

~

----

~

- - -Awakemode

15

a:

r\~

\

~u

-

~
o

Sleep~~

a:

Sleepmode
-25

100

§M
o

Awakemode

~

80

Figure 6. Input Bias Current versus Temperature :«

:«

Sleepm~de

o

m

-10
-5.0
0
5.0
10
VCM, COMMON MODE INPUT VOLTAGE (V)

<=

!z
Il!

90 §

~Ieepmode

~

W

VCC=+15V
VEE=-15V
TA = 25°C

'\..

W

-

1.0

§l
B:;

VCC=+15V
VEE =-15 V
VCM =OV

~w
!!!

I

0_55 -40 -25

o
25
50
85
TA, AMBIENT TEMPERATURE (OC)

~§
0

~

~~
~

~

40 w

\,

~~

2O~

o

125

MOTOROLA COMMUNICATIONS DEVICE DATA

Figure 8. Output Voltage Swing
versus Supply Voltage

Figure 7. Open-Loop Voltage Gain
versus Temperature
35

ill 130

z

«

'"
'"~
w

0

>

120
110

n.
0

g

:Z
w

n.
0
..:l
0

-

-- --

Awakemode (RL = 600 f l ) - - -

Sleepmode (RL = 1.0 M fl)

100

t-.....

90

:il

80
-55 -40 -25

0
25
50
85
TA, AMBIENT TEMPERATURE ('C)

~
w

'"~
0

30

f-

=>

n.

-;;;: 25
Cl.

0

>

f-

0

:9

lO

~ Awakemode (RL = 600 fl)

0

10

:9
~

~

'"

z
§

25

'"~

20

f-

15

III

0

10

§:
=>
n.
f=>

'I'10 k
t, FREQUENCY (Hz)

:9

1"-. ....
100 k

0
0

1"--....

Ul

a:

UJ
Cl

r-. . .

60

::;;

z

0

![

VCC=+15V
VEE=-15V
0
0: 20 VCM=OV
::;;
dVCM=±1.5V
0
TA=25'C

IIIIIII

100

1.0 k

10 k

Sleepmode

111111

o 100~§~~~,~,1t~~~ffitr-t~~-t~m

@......
~

11~~~k I

p:::!

80 l-H-fl'tIlIIr--."..-j.....
-=F'I~II\;~~++tmlk"c-l Awakemode
I

~,.....

I"-

"

10 k

120r-rT~"nm'''+'p-SR''Trrrnr-r"rrm'-'''lrrmlllllll'-TOTTIrm

z

n.

~

40

::;;
0

VCC=+15V
VEE =-15 V
t=1.0kHz
TA = 25'C

Figure 12. Power Supply Rejection
versus Frequency

Awakemode

Sleepmo~i'-

0

::;;

r--- r-

Awakemode

100
1.0 k
RL, LOAD RESISTANCE TO GROUND (fl)

500 k

![ 100
UJ

18

v,.
/

Figure 11. Common Mode Rejection
versus Frequency

;::

15

Cl.

Awakemode
(RL = 600 flr.

VCC=+15V
VEE=-15V
5 AV=+1.0
0 TA=25'C

f:::r80

6.0
9.0
12
VCC, I VEEI, SUPPLY VOLTAGE (V)

Figure 10. Maximum Peak-to-Peak Output
Voltage Swing versus Load Resistance

en
w

Sleepmode
(RL = 1.0 M fl)

1.0 k

z

/'

3.0

125

,

1\

20
15 -

.Y"

15

f-

=>

~

30

C.

=>
n.
f=>

Sleepmode (RL = 1.0 M fl)..&Ii

20

>

30

'"'-'~

~~

25

Figure 9. Output Voltage versus Frequency

w

.#

TA = 25'C

:!:.

60

w

~
o:

r'-..

~
lOOk

t, FREQUENCY (Hz)

MOTOROLA COMMUNICATIONS DEVICE DATA

loOM

40 VCC = +15 V
20 VEE=-15V
dVCC=±1.5V
TA=25'C

~

......

-PSR
Sleepmode......

1111111 I II
11111
11111

III

1.0 k
10k
t, FREQUENCY (Hz)

I

-PSR
IJ,wakemod

II~

!S, .....

lOOk

1.0M

MC33102
2-213

Figure 14. Awakemode to Sleepmode
Current Threshold versus Supply Voltage

Figure 13. Sleep mode to Awakemode
Current Threshold versus Supply Voltage

190.---....-----r-----.-----....-~-.,....,

'[

9" 190

:'1

o

l:la:

::t:

~

~

~

~ 170~--~~~----~~~~------~----~

~ 150~-----F~~~~~~~------t------1

w

a:
u

a:
u. 140 r_-----l-------+-"......~O:::+-------="...-=--~

~ 150r_-----r------r_-----r~~~r_----~

~ 130r_----_r------r-----_r--~~~~---1

~

160r_-----r-----3~~--_r--~~r_----~

::::>

~

140 3!:-:.0,.---"L6.0::----:9:L:.O
,----:1!:-2.;.;...----f:15::---~

1203'":.0,---:'6.':"'0--~9:':.O,--:--1'='2----:'15::------"18

Vee, I VEEI, SUPPLY VOLTAGE (V)

Vee, IVEEI, SUPPLY VOLTAGE (V)

Figure 15. Output Short Circuit Current
versus Output Voltage

<-

1~ 150

.5.

....
z

120
w
a:
a:
::::> 100
u

,Sink
Sou;;--

!::
::::>

u
a:
U

80

Ii:
0

60

~ 140

::::>

'" ","
'" "

~ 130

aa: 120
U

en

....
::::>
a..
....
::::>

40 I- Vee=+15V
VEE=-15V
VID= ±1.0V
0
20 '- RL<10n
u
Awakemo1e
en
3.0

6.0
9.0
I Vo I, OUTPUT VOLTAGE (V)

12

"
\

~

=

15

90
80
70_55 -40 -25

w

u:: 55

1.0 ~

::::;

a..

w

a..

50

a..
....
z

w 45 ,a:
a:
::::>
u 40
~
a..
a..

::::>

en
c

'""

r--.....

........

0
25
50
85
TA, AMBIENT TEMPERATURE (ee)

125

1

a:
w

::t!
a:

"- ~

Figure 18. Slew Rate versus Temperature

.21a:

60

Source

-~

~ 100

§

Figure 17. Power Supply Current Per Amplifier
versus Temperature

<~

~

110

§?

Vce=+15V
VEE =-15 V
VID=±1.0V
RL < 10 n
Awakemode

r--....

Sink

Ii:

'\

::c

Figure 16. Output Short Ciruit Current
versus Temperature

--

1/

0.8
Awakemode (mA)
0.6

/siee mode(!J.A)

/'

35
30_55 -40 -25

MC33102
2-214

-

---

0.4

ec=+15 V 0.2
VEP-15V
No Load
o
0
25
50
85
125
TA, AMBIENT TEMPERATURE (ec)

",0.18

::t!
ffi
a..
....

~~ 0.16

a:

a:

~en

~
a..

en

iii

a
~

VCC=+15V
VEE=-15V
tNn =-5.0V10+5.0V -r---I:,....=---f-------l1.8

~

1.6w

~

~

1.4~en

~

~

en
1"'-c"JIF--t----1'---r--+---+----i1.2

E
0.10-55 -40 -25

0
25
50
85
TA, AMBIENTTEMPERATURE (ee)

MOTOROLA COMMUNICATIONS DEVICE DATA

Figure 20. Sleepmode to Awakemode
Transition Time

Figure 19. Gain Bandwidth Product
versus Temperature

- --- --

~
:::>
Cl

~
D-

~

l!5

:;:

5.0 ~
~

Awakemo!e (MHz)

t;

350
Sljepmrde (kHz)

~ 300

«
C!>

:;: 250 VC!J5V
ID
VEE =-15 V
C!>
1=20 kHz
200
-55 -40 -25

-

r--

f-

~

gCl

:>

4.0 ~

6w

4.5

Cl

a
II:

------

C!>

Cl

~

3.5 ~
z
..:

-

a

>
~
w

ID
Z

«
C!>

D-

~

>

ci.

C!>

0
25
50
85
TA, AMBIENTTEMPERATURE ('C)

125

Figure 21. Sleepmode to Awakemode
Transition Time

t, TIME (5.0 IIS/DIV)

Figure 22. Awakemode to Sleepmode Transition Time
versus Supply Voltage
2.0.----.---,----.---,------,

fa

e.
w

1.51-----t----t----t-----:;;....-==-----j

::;
i=

a 1.01-----t-----boo"""---t----t----j
i=

en

:;:

:=

~ 0.5 t-~"e:._t_---i---=:;;;;o-t''''''''==--+==....-f

o~--~---~--~---~--~

3.0

t, TIME (2.0 IlSiDIV)

6.0

Figure 23. Gain Margin versus
Differential Source Resistance
70
sJepU

iii"

t3

'"

z

aII:
:'iz

«C!>
E

..:

wakemode

11

~

9.0
VCC=+15
VEE=-15V

7.0 RpRl + R2
Vo=OV
TA=25'C

~
~

MOTOROLA COMMUNICATIONS DEVICE DATA

m-

60

~

50

a

~ 40
w

~ 30
D-

E 20
IS!

Vo

R2

100
1.0k
Rr, DIFFERENTIAL SOURCE RESISTANCE (Q)

18

Figure 24. Phase Margin versus
Differential Source Resistance

15

:>!.

9.0
12
15
VCC, IVEE I, SUPPLY VOLTAGE (V)

10k

I~~pmo~e

lllJlllIl
VCC=+lS\l'
VEE=-15V
Rr=Rl +R2
VO=OV

"'

TAI2?~CIIIIII

-

wakemod

111111111

~
~

"Vo

R2

100
1.0k
10k
RT, DIFFERENTIAL SOURCE RESISTANCE (Q)

toO k

MC33102
2-215

Figure 26. Phase Margin versus
Output Load Capacitance

Figure 25. Open-Loop Gain Margin versus
Output Load Capacitance

m
:s!.

14

z

12

a:
!;

AV~ )oJo

-ttl
~.Ok

SO

~

III

;i

~

Av= 100

/1
,/
10k

lOOk
f, FREQUENCY (Hz)

~

~

L

w

~

-I II
10M

1.0M

10

a:

AV=I.0

~e

1.0

-

Awakemode

S'010

100

70

I

8en

:::l

111111

I

~ 40

a: 0.4
a:

u
w
en
i5

z

I:::l

:J:

0.2

r-....

111111

I

111111

I

11111'1
100

1.0 k
f, FREQUENCY (Hz)

Figure 35. Sleepmode Large Signal
Transient Response

t, TIME (SO IlsIDlV)

MOTOROLA COMMUNICATIONS DEVICE DATA

Sleepmode
(RL=I.0MQ)

I-

Z

30

"-

20

w
u
a:
w

en
0

10

V
/1'

V
-~

~

V

;'
. / Awakemode
(RL= 600 Q)

I

I

10 k

50

w

Sfeepmode

~

.s

VCC=+ISV

a:

Awakemode

"-

100 k

TA=2SoC

= =)11)1)

I-

10k

~ 60 VEE=-ISV

zw

~

1.0k
f, FREQUENCY (Hz)

Figure 34. Percent Overshoot
versus Load Capacitance

~VO

VCC=+ISV
VEE=-ISV
TA = 2SoC
0.6 (RS=10k)
0.8

111111
Sleepmod

~

AV~10

~

=

w
en

Figure 33. Current Noise versus Frequency

~

fFrVO

~ 100 VCC=+ISV
:>
VEE=-ISV
.s
TA=2SoC

VCC=+ISV
VEE=-ISV
VCM=OV
Vo=OV
TA=2SoC
Awakemode

lOOk

I II
1.0k

100
CL, LOAD CAPACITANCE (pF)

Figure 36. Awakemode Large Signal
Transient Response

t, TIME (S.O IlS/DIV)

MC33102
2-217

Figure 38. Awakemode Small Signal
Transient Response

Figure 37. Sleepmode Small Signal
Transient Response

t, TIME (50 I'slDlV)

t, TIME (50 I'slDlV)

CIRCUIT INFORMATION
The MC33102 was designed primarily for applications
where high performance (which requires higher current drain)
is required only part of the time. The two-state feature of this
op amp enables it to conserve power during idle times, yet
to be powered up and ready for an input signal. Possible
applications include laptop computers, automotive, cordless
phones, baby monitors, and battery operated test equipment.
Although most applications will require low power
consumption, this device can be used in any application
where better efficiency and higher performance is needed.
The Sleep-ModeTM amplifier has two states; a sleepmode
and an awake mode. In the sleepmode state the amplifier is
active and functions as a typical micropower op amp. When
a signal is applied to the amplifier causing it to source or sink
sufficient current (see Figure 13), the amplifier will
automatically switch to the awakemode. See Figures 20 and
21 for transition times with 600 Q and 10 kQ loads.

The awakemode uses higher drain current to provide a
high slew rate, gain bandwidth, and output current capability.
In the awakemode, this amplifier can drive 27 Vp-p into a
600 Q load with Vs ±15 V.
An intemal delay circuit is used to prevent the amplifier
from returning to the sleepmode at every zero crossing. This
delay circuit also eliminates the crossover distortion
commonly found in micropower amplifiers. This amplifier can
process frequencies as low as 1.0 Hz without the amplifier
retuming to sleepmode, depending on the load.
The first stage PNP differential amplifier provides low noise
performance in both the sleep and awake modes, and an
all NPN output stage provides symmetrical source and sink
AC frequency response.

=

APPLICATIONS INFORMATION
The MC33102 will begin to function at power supply
voltages as low as Vs = ±1.0 V at room temperature. (At this
voltage, the output voltage swing will be limited to a few
hundred millivolts). The input voltages must range between
VCC and VEE supply voltages as shown in the maximum
rating table. Specifically, allowing the Input to go more
negative than 0.3 V below VEE may cause product
damage. Also, exceeding the input common mode voltage
range on either input may cause phase reversal, even if the
inputs are between VCC and VEE.
When power is initially applied, the part may start to
operate in the awakemode. This is because of the currents
generated due to charging of internal capacitors. When this
occurs and the sleepmode state is desired, the user will have
to wait approximately 1.5 seconds before the device will
switch back to the sleepmode. To prevent this from occurring,
ramp the power supplies from 1.0 V to full supply. Notice that
the device is more prone to switch into the awakemode when
VEE is adjusted than with a similar change in VCC.
The amplifier is designed to switch from sleepmode to
awakemode whenever the output current exceeds a preset

MC33102
2-218

current threshold (lTH) of approximately 160 J.lA. As a result,
the output switching threshold voltage (VST) is controlled by
the output loading resistance (RL). This loading can be a load
resistor, feedback resistors, or both. Then:
VST

=(160 J.lA)' RL

Large valued load resistors require a large output voltage
to switch, but reduce unwanted transitions to the
awakemode. For instance, in cases where the amplifier is
connected with a large closed-loop gain (ACU, the input offset
voltage (VIO) is multiplied by the gain at the output and could
produce an output voltage exceeding VST with no input
signal applied.
.
Small values of RL allow rapid transition to the awakemode
because most of the transition time is consumed slewing in
the sleepmode until VST is reached (see Figures 20, 21).
The output switching threshold voltage VST is higher for
larger values of RL, requiring the amplifier to slew longer in
the slower sleepmode state before switching to the
awakemode.

MOTOROLA COMMUNICATIONS DEVICE DATA

The transition time (ttr1) required to switch from sleep to
awake mode is:

=to + ITH (RLlSRsleepmode)
where: to = Amplifier delay «1.0 !1S)
ITH = Output threshold current for mode
ttr1

transition (160 !lA)
RL = Load resistance
SRsleepmode = Sleepmode slew rate (0.16 Vll1s)

Although typically 160 I1A, ITH varies with supply voltage
and temperature. In general, any current loading on the
output which causes a current greater than ITH to flow will
switch the amplifier into the awakemode. This includes
transition currents such as that generated by charging load
capacitances. In fact, the maximum capacitance that can be
driven while attempting to remain in the sleepmode is
approximately 1000 pF.
CL(max) = ITH/SRsleepmode
160 11A1(0.16 VI!1S)
1000 pF

To minimize this problem, a resistor may be added in series
with the output of the device (inserted as close to the device
as possible) to isolate the op amp from both parasitic and
load capacitance.
The awakemode to sleepmode transition time is controlled
by an internal delay circuit, which is necessary to prevent
the amplifier from going to sleep during every zero crossing.
This time is a function of supply voltage and temperature as
shown in Figure 22.
Gain bandwidth product (GBW) in both modes is an
important system design consideration when using a
sleepmode amplifier. The amplifier has been designed to
obtain the maximum GBW in both modes. ·Smooth" AC
transitions between modes with no noticeable change in the
amplitude of the output voltage waveform will occur as long
as the closed-loop gains (ACL) in both modes are
substantially equal at the frequency of operation. For smooth
AC transitions:
(ACLsleepmode) (BW) < GBWsleepmo

=
=

where: ACLsleepmode

Any electrical noise seen at the output of the MC33102
may also cause the device to transition to the awakemode.

BW

=

=

Closed-loop gain in
the sleep mode
The required system bandwidth
or operating frequency

TESTING INFORMATION
To determine if the MC33102 is in the awakemode or the
sleepmode, the power supply currents (10+ and 10-) must be
measured. When the magnitude of either power supply
current exceeds 400 !lA the device is in the awakemode.
When the magnitudes of both supply currents are less than
400 !lA, the device is in the sleep mode. Since the total supply
current is typically ten times higher in the awakemode than
the sleepmode, the two states are easily distinguishable.
The measured value of 10+ equals the 10 of both devices
(for a dual op amp) plus the output source current of device
A and the output source current of device B. Similarly, the
measured value of 10- is equal to the 10- of both devices plus
the output sink current of each device. lout is the sum

MOTOROLA COMMUNICATIONS OEVICE OATA

of the currents caused by both the feedback loop and load
resistance. The total lout needs to be subtracted from the
measured 10 to obtain the correct 10 of the dual op amp.
An accurate way to measure the awakemode lout current
on automatic test equipment is to remove the lout current on
both Channel A and B.Then measure the 10 values before
the device goes back to the sleepmode state. The transition
will take typically 1.5 seconds with ±15 V power supplies.
The large signal sleepmode testing in the characterization
was accomplished with a 1.0 MQ load resistor which ensured
the device would remain in sleepmode despite large
voltage swings.

MC33102

2-219

MOTOROLA

-

SEMICONDUCTOR

MC33110

TECHNICAL DATA

, Low Voltage Compander
The MC33110 contains two variable gain circuits configured for
compressing and expanding the dynamic range of an audio signal. One circuit is' configured as an expander, while the other
circuit can be configured as a compressor or expander. Each circuit has a full wave rectifier to provide average value information
to a variable gain cell located in either the input stage or the
feedback path. An internal, temperature stable bandgap reference
provides the necessary precision voltages and currents required.
The MC33110 will operate from a supply voltage of 2.1 to 7.0 V,
over a temperature range of -40° to + 85°C. The device is
designed to accommodate an 80 dB dynamic 'range from -60 dB
to +20 dB, referenced to 100 mVrms.
Applications include cordless telephone, CB, walkie-talkie, most
voice RF links, and any application where the signal-to-noise ratio
can be improved by reducing the transmitted dynamic range.
Other applications include speakerphone and voice activated
intercom, dictating machine, standard telephone, etc.
The MC33110 is packaged in a 14 pin DIP for through-the-hole
applications and an SO-14 surface mount.

LOW VOLTAGE COMPANDER
SILICON MONOLITHIC
INTEGRATED CIRCUIT

P SUFFIX
PLASTIC PACKAGE
CASE 646

DSUFFIX

• Operating Supply Voltage: 2.1 to 7.0 V
• No Precision External Components Required
• SO dB Dynamic Range Compressed to 40 dB, Re-expandable
to 80 dB

PLASTIC PACKAGE
CASE 751A
(50-14)

• Unity Gain Level: 100 mVrms
• Adjustable Response Time
• Ambient Operating Temperature: -40° to +S5°C
• Temperature Compensated Reference
• Applications Include Cordless Phone, CB Radio,
Speakerphone, etc.

PIN CONNECTIONS
(TOP VIEW)

VCC

Vref

NC

NC
SIMPLIFIED BLOCK DIAGRAM

COMPo FIlTER

EXP. FILTER

------------,

COMPo OUTPUT

EXP. OUTPUT

COMP.INPUT

EXP.INPUT

I 12

VB
8 COMPo FEEDBACK

GND

Exp.
Output
VCc-<*---f--::---'

VS-..

FIGURE 3 -

EXPANDER TRANSFER CHARACTERISTICS

1000~!llrlllll~II~!II~

~ 100~1'II'm;II!IIII~11
~

§;

....
~

~ 1°~1111111.
s

~

1.0 L-J....l-LLLllLJ.LLL....LJLllllil......LJL...J....LLLill.L...J..-'-LLLillJJ

0.1

1.0

10
100
Vin, INPUT VOLTAGE ImVrms)

0.1 '--"--'--'.L.L...1...J..U-U_'--'----'--L..J....U.........--'---'----'--'--'...J....L.LU
1.0
10
100
1000
Vin, INPUT VOLTAGE ImVrms)

1000

FIGURE 5 -

FIGURE 4 - COMPRESSOR TRANSFER CHARACTERISTICS

+10

'"
'0

/

W

~
~
o
> -10
!:;

:=::::>

)-20
-3

oV

V

/

o

/

/

/

+20

/
~

0

~
~
o
> -2 0

i2

!:;
o

~-40

>

o dB = 100 mVrms

-60

-40

FIGURE 6 -

POWER SUPPLY REJECTION (COMPRESSOR)

-20
Vin, INPUT VOLTAGE IdB)

oV

/

-6

+20

FIGURE 7 -

/

o dB = 100 mVrms

-20

-30

/

/

/

/

-10
Vin, INPUT VOLTAGE (dB)

+10

POWER SUPPLY REJECTION (EXPANDER)

50
11111111

30

CI

~l210"~

;z:

CVB - 100/LF

[;

I 1111111

o

....-:
",-

-cn=li7~ /"'-

-10
10

Ci B

MC33110
2-224

1111~rl
100

CVB'=

40

V

VIIII~ F""

~ 20
~ 10

/

w

40

a:

EXPANDER TRANSFER CHARACTERISTICS

VB I I

o

CVB = 47/LF

~ 20

a:

5

vr

11 (11111

1.0 k
t, FREQUENCY 1Hz)

10 k

II

10

100 k

itt /

~ 30
[;

Pin 10 Input Signal = 0 mV

?"

C)=11Jol~

;z:

V'"

Uo'Ji

o

10

i I I iI /V
Cv! J1101/L~
111111

100

r

.....

Pin 5 Input Signal = 0 mV
ll=lmlll
1.0 k
10 k
t, FREQUENCY (Hz)

II

100 k

MOTOROLA COMMUNICATIONS DEVICE DATA

COMPRESSOR
FIGURE

a-

EXPANDER

POWER SUPPLY REJECTION (COMPRESSOR)

FIGURE 9 -

POWER SUPPLY REJECTION (EXPANDER)

40

IIIIIII

30

o

Cva

= 220 JLF

Cva

100 JLF

T="I~

o
-10
10

~ !,)"

V

Ci

B

~30r-4-rTTttffir~-r~~--~-H+Hfr--r1-~~

V

""I""-~II]V

Of-Cva

40

.........
z
a

Ei

= 47 JLF

~20~~+++H~14-r~~--~-H+H*--r~K+~
a:

Pin 10 Input Signal

~r

C,
V

10

1=1 1

100

FIGURE 10 -

= - 20 dB

=15((11111

III

10 k

1.0 k
t, FREQUENCY (Hz)

10

100 k

FREQUENCY RESPONSE (COMPRESSOR)

1,0

FIGURE 11 -

1

1 II

Vin

~-1. 0

= 100 mVrms

=

J-'l
316 mVrms

~

f-

:::>

:::>
~-3, 0

~ 7. 0

2

w

~ -5.0

~ 5. 0

~

~

a:

:. -7. 0

~ 3. 0

~
::J

I
Vin

~9. 0

f-

::>

FREQUENCY RESPONSE (EXPANDER)

f-

:::>

-9.0

Vin

01. 0

= 1.0 Vrms

I I

-1 1
100

1.0 k
10 k
t, FREQUENCY (Hz)

FIGURE 12 -

20 k

100 k

FREQUENCY RESPONSE (COMPRESSOR)

FIGURE 13 -

0

0

~-1 0

0

~
~ -2 0

Vin

=

0

Viln

~I H'lvrms

100 JLVrms

~ -30

~

~

a:
f-

:::>

-40

20k

100 k

FREQUENCY RESPONSE (EXPANDER)

1111111

Viln

~I )010vrms

Vi~ ~I }Wmvrms

---~

:=:::>

\

0-50

0
0
100

I II
1.0k
10k
t, FREQUENCY (Hz)

100

0

0

Vin - 100 mVrms

-I. 0

1.0k
t, FREOUENCY (Hz)

10k

20k

MOTOROLA COMMUNICATIONS DEVICE DATA

100 k

-60

100

1.0k
10k
t, FREOUENCY (Hz)

20k

100 k

MC33110
2-225

FIGURE 14 -

ATTACK AND DECAY TIMES (COMPRESSOR)

FIGURE 15 -

100

100

0

80

ATTACK AND DECAY TIMES (EXPANDER)

./

./
,/'

0
DeCay~

0

./

'"

V

c

o
o

-2.0

FIGURE 16 -

4.0
6.0
C, CAPACITANCE AT PIN 12 (/tF)

60

,/

z

-

~-

./

/'

./

,/

0

/"

0

I

./

8.0

frl
'" 40
:3

/'

~

f--

20

o

o

10

ATTACK AND DECAY TIMES (COMPRESSOR)

./

V

2.0

FIGURE 17 -

/'

4.0
6.0
C, CAPACITANCE AT PIN 3 (/tF)

8.0

10

ATTACK AND DECAY TIMES (EXPANDER)

Output
(Pin 11)

Input
(Pin 10)

=

Attack Time = Time to 63% of 4V1.
Decay Time = Time to 63% of 4V2.

FIGURE 18 -

Attack Time
Time to 63% of 4V1.
Decav Time = Time to 63% of 4 V2.

MAXIMUM INPUT SIGNAL

FIGURE 19 -

CHANNEL SEPARATION

120

3.0

0

~

~

,.,

compr~ssor

100

m

:s
z

o

fi80

~

0

/'

'"
60

I/~

Expander

0
2.0

MC33110

2-226

-

1J11tIt
Compressor to Expander

3.0

4.0
5.0
VCC, SUPPLY VOLTAGE (\I)

6.0

7.0

40
1,00

-

Expander to Compressor

1.0k

10k

20k

100 k

f, FREQUENCY (Hz)

MOTOROLA COMMUNICATIONS DEVICE DATA

COMPRESSOR

EXPANDER

FIGURE 20 - COMPRESSOR GAIN TRACKING
versus TEMPERATURE

FIGURE 21 - EXPANDER GAIN TRACKING
versus TEMPERATURE

+ 1.0.---,----,----,-----.----,-----,-,

+1.0,---,----,----,----,---,---,-,

.:~:;:.:.:.:.:«-:-............. -.••...
:::.;.;.;.:.:.;.:.:.:.:.:.:.:.: .•...,..................

.............. .

~

Shaded area depicts typical drift range
1----+---+--100 p.Vrms '" Vin '" 1 Vrms
-

[

'[

[

-1.0L-_--'-_ _--L_ _...L._ _-'---_ _L-_~-"
-40
-20
0
20
40
60
85
TA, AMBIENT TEMPERATURE (OCI

-~4LO--_-2LO--~0L--~20~-~40--~60--~-"85
TA, AMBIENT TEMPERATURE (OCI

FIGURE 22 -

COMPRESSOR THO versus TEMPERATURE

FIGURE 23 -

EXPANDER THO versus TEMPERATURE

+20

+10

i"--..

-10
-40

'"

u

"'-.

-20

l\l

+

...............

-........... ...........

o
20
40
TA, AMBIENT TEMPERATURE (OCI

........

""- "'-....r-

I'----.. ....

60

85

-20
-40

-20

--- --

r--

o
20
40
TA, AMBIENT TEMPERATURE lOCI

---r-..
60

85

FUNCTIONAL DESCRIPTION
Introduction
The MC33110 compander (COMpressor and
exPANDER) is composed of two variable gain circuits
which provide compression and expansion of the signal
dynamic range. The compressor will take a signal with
an 80 dB dynamic range (100 /LV to 1.0 Vrms), and reduce
that to a 40 dB dynamic range by attenuating strong signals, while amplifying low level signals. The expander
does the opposite in that the 40 dB signal range is
increased to a dynamic range of 80 dB by amplifying

MOTOROLA COMMUNICATIONS DEVICE DATA

strong signals and attenuating low level signals. The 0 dB
level is internally set at 100 mVrms - that is the signal
level which is neither amplified nor attenuated. Both circuits contain the necessary precision full wave rectifier,
variable gain cell, and temperature compensated references required for accurate and stable performance.
Note: All dB values mentioned in this data sheet, unless
otherwise noted, are referred to 100 mVrms.

MC33110

2-227

Compressor
The compressor is an operational amplifier with a fixed
input resistor and a variable gain cell in its feedback path
as shown in Figure 24.
FIGURE 24 - COMPRESSOR

12

4.7k

IControl

10 k
A Gain

Vcc
10
Input

>--.()..-+--"V\I'v--~-~-------i

10 k

VB

The amplifier output is sampled by the precision rectifier
which, in turn, supplies a DC signal (lControl). representative of the rectifier's AC signal, to the variable gain cell.
The reference current (I ref) is an internally generated precision current. The effective impedance of the variable
gain cell varies with the ratio of the two currents, and
decreases as IControl increases, thereby providing
compression. The output is related to the input by the
following equation:
Vout

=

0.3162 x ~

(Equation 1)

In terms of dB levels, the relationship is:
Vout(dB) = 0.5 x Vin(dB)

(Equation 2)

where 0 dB = 100 mVrms (see Figure 2 and 4).
The inputs and output are internally biased at
VB (VCC/2), and must therefore be capacitor coupled to
external circuitry. Pin 10 input impedance is nominally
10 kfl (±20%), and the maximum functional input signal
is shown in Figure 18. Bias currents required by the op
amp and the variable gain cell are internally supplied.
Due to clamp diodes at the input (to VCC and ground),
the input signal must be maintained between the supply
rails .. If the input signal goes more than 0.5 V above VCC
or below ground, excessive currents will flow and distortion will show up at the output.
. When no AC signals are present at the input, the variable gain cell will attempt to set such a high gain that
the circuit may become unstable. Forthis reason resistors
Rl and R2, and capacitor Cl are added to provide DC
stability. The pole formed by Rl, R2 and Cl should have

MC33110
2-228

a pole frequency no more than 1110th of the lowest frequency of interest. The pole frequency is calculated from:
f

=

Rl + R2
21T x Rl R2Cl

(Equation 3)

for the component values shown, the pole frequency is
=16 Hz.
Likewise, the capacitor between Pins 11 and 8 should
be selected such that, in conjunction with the input
impedance at Pin 8 (=3200 fl, ±20%), the resulting pole
frequency is no more than 1/10 of the lowest frequency
of interest. With the components shown, the pole frequency is <30 Hz. This pole frequency is calculated from:
f

=

1

21T x 3.2 k x C

(Equation 4)

The output of the rectifier is filtered by the capacitor at
Pin 12, which, in conjunction with an internal 10 k resistor,
provides the time constant forthe attack and decay times.
Figure 14 and 16 indicate how the times vary with the
capacitor value. The attack time for the compressor is
always faster than the decay time due to the fact that the
rectifier is fed from the output rather than the input. Since
the output is initially larger than expected (immediately
after the input has increased), the external capacitor is
charged more quickly during the initial part of the time
constant. When the input is decreased, the time {;onstant
is closer to that calculated by t = RC. If the attack and
decay times are decreased by using a smaller capacitor,
performance at low frequencies will degrade.

MOTOROLA COMMUNICATIONS DEVICE DATA

Expander
The expander is an operational amplifier with a fixed
feedback resistor and a variable gain cell in its input path
as shown in Figure 25.

FIGURE 25 - EXPANDER

4.7 k

J
Vee

2.2p.F

10 k
10 k

Input >-~)--+--""'-+---"lI\h-----I

>-......-c>--.... Output
Iref

The input signal is sampled by the precision rectifier
which, in turn, supplies a DC signal (lControl), representative of the AC input signal, to the variable gain cell. The
reference current (lref) is an internally generated precision current. The effective impedance ofthe variable gain
cell varies with the ratio of the two currents, and
decreases as IControl increases, thereby providing
expansion. The output is related to the input by the following equation:
Vout

= 10 x (Vin)2

(Equation 5)

In terms of dB levels, the relationship is:
Vout(dB)

= 2.0 x Vin(dB)

above VCC or below ground, excessive currents will flow,
and distortion will show up at the output.
The output of the rectifier is filtered by the capacitor at
Pin 3, which, in conjunction with an internal 10k resistor,
provides the time constant for the attack and decay times.
Figure 15 and 17 indicate how the times vary with the
capacitor value. If the attack and decay times are
decreased by using a smaller capacitor, performance at
low frequencies will degrade.

(Equation 6)

where a dB = 100 mVrms (see Figure 3 and 5).
The inputs and output are internally biased at VB
(VCC/2), and must therefore be capacitor coupled to
external circuitry. The input impedance at Pin 5 is nominally 3.2 k!1 (±20%), and the maximum functional input
signal is shown in Figure 18. Bias currents required by
the op amp and the variable gain cell are internally supplied. Due to clamp diodes at the input (to VCC and
ground), the input signal must be maintained between
the supply rails. If the input signal goes more than 0.5 V

MOTOROLA COMMUNICATIONS DEVICE DATA

Power Supply
The MC3311 a requires a power supply voltage between
2.1 V and 7.0 V, and a nominal current of 3.5 rnA. The
supply voltage should be well filtered and free of ripple.
A minimum of 4.7 p.F in parallel with a 0.01 JLF capacitor
is recommended for filtering and RF bypass.
VB (Pin 6) is an internally generated mid supply reference, and is used internally as an AC ground. The external capacitor at Pin 6 filters this voltage, and its value
affects the power supply noise rejection as shown in Figures 6 through 9. This reference voltage may be used to
bias external circuitry as long as the current draw is limited to <10 pA

MC33110

2-229

APPLICATIONS INFORMATION
Signal-to-Noise Improvement
Among the basic reasons for the original development
of compander type circuits was to improve the signal-tonoise ratio of long distance telecom circuits, and of voice
circuits which are transmitted over RF links (CBs, walkietalkies, cordless phones, etc.). Since much of the noise
heard at the receiving end of a transmission is due to
noise picked up, for example, in the airway portion of the
RF link, the compressor was developed to increase the
low-level signals at the transmitting end. Then any noise
picked in the RF link would be a smaller percentage of
the transmitted signal level. At the receiving end, the
signal is then expanded back to its original level, retaining
the same high signal-to-noise ratio. While the above
explanation indicates it is not necessary to attenuate
strong signals (at the transmitting end), a benefit of doing
this is the reduced dynamic range which must be handled

FIGURE 26 -

by the system transmitter and receiver. The MC3311 0 was
designed for a two-to-one compression and expansion,
i.e. an 80 dB dynamic signal is compressed to a 40 dB
dynamic range, transmitted to the receiving end and then
expanded back to an 80 dB dynamic range.
The MC33110 compander is not limited to RF or long
distance telephony applications. It can be used in any
system requiring an improved signal-to-noise ratio such
as telephones, speakerphones, tape recorders, digital
recording, and many others.

Second Expander
Should the application require it, the MC3311 0 can be
configured as'two expanders by reconfiguring the compressor side as shown in Figure 26.

SECOND EXPANDER

12

4.7 k

l2.21-'F

IControl
Input

10 k

10

10 k

>----,<)---1f----""""''Vv-------\
>-~:>---+-~~

Output

Iref

This circuit will provide the same performance as the
expander at Pins 3 through 5.

Power Supplies, Grounding
The PC board layout, the quality of the power supplies
and the ground system at the IC are very important in
order to obtain proper operation. Noise, from any source,
coming into the device on VCC or ground, can cause a
distorted output, or incorrect gain level.
VCC must be decoupled to the appropriate ground at
the IC (within 1" max) with a 4.7 p,F capacitor and a 0.01 p,F
ceramic. A tantalum capacitor is recommended for the
larger value if very high frequency noise is present since
electrolytic capacitors simply have too much inductance
at those frequencies. The quality of the power supply
voltage should be checked at the IC with a high frequency
scope. Noise spikes (always present if digital circuits are

MC33110
2-230

near this IC) can easily exceed 400 mV, and if they get
into the IC, the output can have noise or distortion. Noise
can be reduced by inserting resistors and/or inductors
between the supply and the IC.
If switching power supplies are used, there will usually
be spikes of 0.5 V or greater at frequencies of 50 kHz to
1.0 MHz. These spikes are generally more difficult to
reduce because of their greater energy content. In
extreme cases, a three terminal regulator (MC78L05ACP),
with appropriate high frequency filtering, should be used
and dedicated to the analog portion of the circuit.
The ripple content of the supply should not allow its
magnitude to exceed the values in the Recommended
Operating Conditions table.

MOTOROLA COMMUNICATIONS DEVICE DATA

The PC board tracks supplying VCC and ground to the
MC33110 should preferably not be at the tail end of the
bus distribution, after passing through a maze of digital
circuitry. The analog circuitry containing the MC33110
should be close to the power supply, or the connector
where the supply voltages enter the board. If VCC is supplying considerable current to other parts of the board,
then it is preferable to have dedicated lines from the
supply or connector directly to the MC33110 and associated circuitry.
PC Board Layout
Although this device is intended for use in the audio
frequency range, the amplifiers have a bandwidth of,

"'300 kHz, and can therefore oscillate at frequencies outside the voiceband should there be excessive stray capacitance or other unintended feedback loops. A solid
ground plane is strongly recommended to minimize coupling of any digital noise into the analog section. Use of
wire wrapped boards should definitely be avoided.
Since many applications of the MC33110 compander
involve voice transmission over RF links, care must be
taken in the design of the product to keep RF signals out
of the MC33110 and associated circuitry. This involves
proper layout of the PC boards, the physical arrangement
'of the boards, shielding, proper RF ground, etc.

GLOSSARY
ATTACK TIME - The settling time for a circuit after its
input signal has been increased.
ATTENUATION - A decrease in magnitude of a communication signal, usually expressed in dB.
BANDWIDTH - The range of information carrying frequencies of a communication system.
CHANNEL SEPARATION - The ability of one circuit to
reject outputting signals which are being processed by
another circuit. Also referred to as crosstalk, it is usually
expressed in dB.
COMPANDER - A contraction of the words compressor
and expander. A compander is composed of two circuits,
one of each kind.
COMPRESSOR - A circuit which compresses or reduces
the dynamic range of a signal by attenuating strong signals and amplifying low level signals.
dB - A power or voltage measurement unit, referred to
another power or voltage. It is generally computed as:
10 x log (P1/P2) for power measurements, and
20 x log (V11V2) for voltage measurements.
dBm - An indication of signal power. 1.0 mW across
6000 or 0.775 V rms, is typically defined as 0 dBm for
telecom applications. Any voltage level is converted to
dBm by:
dBm = 20 x log (Vrms/0.775), or
dBm = [20 x log (Vrms)] + 2.22.

MOTOROLA COMMUNICATIONS DEVICE DATA

dBrn -Indicates a dBm measurement relative to 1.0 pW
power level into 600 O. Generally used for noise measurements, 0 dBrn = -90 dBm.
dBrnC - Indicates a dBrn measurement using a Cmessage weighting filter.
DECAY TIME - The settling time for a circuit after its
input signal has been decreased.
EXPANDER - A circuit which expands or increases the
dynamic range of a signal by amplifying strong signals
and attenuating low level signals.
GAIN - The change in signal amplitude (increase or
decrease) after passing through an amplifier, or other
circuit stage. Usually expressed in dB, an increase is a
positive number and a decrease is a negative number.
POWER SUPPLY REJECTION RATIO - The ability of a
circuit to reject outputting noise, or ripple, which is present on the power supply lines. PSRR is usually expressed
in dB.
SIGNAL-TO-NOISE RATIO - The ratio of the desired signal to unwanted signals (noise) within a defined frequency range. The larger the number, the better.
VOICEBAND- That portion ofthe audio frequency range
used for transmission across the telephone system. Typically, it is 300 to 3400 Hz.

MC33110
2-231

MOTOROLA

-

SEMICONDUCTOR

MC33120

TECHNICAL DATA

Subscriber Loop Interface Circuit

SUBSCRIBER lOOP
INTERFACE CIRCUIT

The MC33120 is designed 10 provide the interface between the 4-wire
side of a central office, or PBX, and the 2-wire subscriber line. Interface
functions include battery feed, proper loop termination AC impedance,
hookswitch detection, adjustable transmit, receive, and transhybrid gains,
and single/double fault indication. Additionally the MC33120 provides a
minimum of 58 dB of longitudinal balance (4-wire and 2-wire).
The transmit and receive signals are referenced to analog ground, while
digital signals are referenced to digital" ground, easing the interface to
codecs, filters, etc. The 2 status outputs (hookswitch and faults) and the
Power Down Input are TTUCMOS compatible. The Power Down Input
permits local shutdown of the circuit.
Internal drivers allow the external loop current pass transistors to be
standard bipolar transistors (non-Darlington).
The MC33120 is available in a 20 pin DIP and a 28 pin PLCC surface
mount package.
• 58 dB Longitudinal Balance Guaranteed; 4-wire and 2-wire
• Transmit, Receive, and Transhybrid Gains Externally Adjustable
• Return Loss Externally Adjustable
• Proper Hookswitch Detection With 30 Jill Leakage
• Single/Double Fault Indication With Shutdown for Thermal Protection
• Critical Sense Resistors Included Internally
• Standard Power Supplies: - 42 V to :.. 58 V, and +5.0 V, ±10%
• On-Hook Transmission
• Power Down Input (TTL and CMOS Compatible)
• Operating Ambient Temperature: - 40°C to +85°C
• Available in a 20 Pin DIP and 28 Pin PLCC Package

(SlIC)
THIN FILM
SILICON MONOLITHIC
INTEGRATED CIRCUIT

-

PSUFFIX
PLASTIC PACKAGE
CASE 738

1

FNSUFFIX
PLCC
CASE 776

ORDERING INFORMATION
Temperature
Range

Device
MC33120P

- 40° to +85'C

Package
Plastic DIP
PLCC

MC33120FN

SIMPLIFIED BLOCK DIAGRAM

c-ri~~==f====~::;~;:~=rT==;::~~::;:~::;;;~~~===?o-r----c.._r----1=>---

VDD (+5.0 V)
VDG
(Dig. Gnd)
PDIIST2
8T1

4f-+--<:.._-

VAG
(Ana. Gnd)

'-;:::::::=~~~~- RXI

>-.---0-- TXO
1-----.;.;.;...----0....._.- RFO
1 - - - - - - - - - 0 - - CF
r-~.....---------o_-VQB

V~EE~t:::::::::::::::~~-~:-~~~~~~!:~:-~~~~~:~::::~----------------.J

(Battery)

*Indicates Trimmed Resistor

MC33120
2-232

MOTOROLA COMMUNICATIONS DEVICE DATA

ABSOLUTE MAXIMUM RATINGS
Characteristic
Supply Voltage
with respect to VCC
with respect to VOG

Symbol

Value

Unit

VEE
VOO

-60, +0.5
-0.5, +7.0

Vdc

Input Voltage
@ POI, with respect to VOG
@Pins1-5, 16-20

Yin

Storage Temperature Range

Tstg

-65to +150

·C

TJ

150

·C

Junction Temperature
Devices should not be operated at these values. The

Vdc
-0.5, +7.0
VEEtoVCC

~Recommended

Operating Conditions table provides conditions for
ft

actual device operation.

RECOMMENDED OPERATING CONDITIONS
Unit

Symbol

Min

Typ

Max

VEE
VOO

-58
+4.5

-48
+5.0

-42
+5.5

(with respect to Vcc)
(with respect to Vcc)
(with respect to VAG)

VAG
VOG

-3.0
-3.0
-3.0

0
0
0

+10
+7.0
+10

Vdc

(with respect to VEE)
(with respect to VCC and VAG)

VOO

-

-

+63.5

Vdc

Characteristic

Vdc

Supply Voltage
(with respect to Vcc)
(with respect to VOG)

+3.5

-

ILOOP

15

-

50

rnA

POI Input Voltage

VpDI

0

-

VOO

Vdc

Sink Current
ST1
ST2

IST1L
IST2L

0
0

Transmit Signal Level at TIp & Ring
Receive Signal Level at VRX

STX
SRX

-48
-48

Loop Current

Loop Resistance
. Exterrial Transistor Beta
Operating Ambient Temperature (See text lor derating)

-

-

RL

0

HFE

40

-

TA

-40

-

rnA
1.0
1.0
+3.0
+3.0

dBm

2.0

kn

500

AlA

+85

·C

All limits are not necessarily functional concurrently.

ELECTRICAL CHARACTERISTICS (VEE = - 48 V, VOO = +5.0 V, unless otherwise noted, VCC = VAG = VOG = 0 V, TA = 25·C,
see Figure 1, unless otherwised noted.)
Characteristic

Symbol

Min

Typ

Max

IEEN
IEEF

-2.7
-75

-1.2
-58

-45

lOON
IOOF

5.5

1.4
9.0

2.7
15

40
40

62
52

37
37

52
48

Unit

POWER SUPPLIES
VEE Current
On Hook (RL > 10 Mil, VEE = - 58 V)
Off Hook (RL = 0 il, VEE = - 58 V)"
VOO Current
On Hook (RL > 10 Mil, VDO = +5.5 V)
Off Hook (RL = 0 il, VOO = +5.5 V)
VEE Ripple Rejection
1= 1.0 kHz, at VTX (4-wire)
1= 1.0 kHz, at TIp/Ring (2-wire)
VOO Ripple Rejection
1= 1.0 kHz, at VTX (4-wire)
1= 1.0 kHz, at TIp/Ring (2-wire)

rnA

PSRR

-

-

dB

-

-

*Includes loop current.

MOTOROLA COMMUNICATIONS DEVICE DATA

MC33120
2-233

ELECTRICAL CHARACTERISTICS (VEE =-48 V, VDD = +5.0 V,unlessotherwisenoted, VCC = VAG

I

Characteristic

I

Symbol

I

Min

= VDG,TA = 25'C, see Figure 1)

I

Typ

I

Max

I

Unit

LOOP FUNCTIONS
Loop Current
Maximum (RRF = 4.7 k, RL = 10 0)
Nominal (RRF = 4.7 k, RL = 600 0)
Minimum (RRF = 4.7 k, RL = 1800 0)
Battery Feed Resistance (RRF = 4.7 k, RL = 1800 Or

mA

43

ILMAX
ILOOP
ILMN

41
37
19

53
48

40
21

-

RBF

475

508

675

Hookswitch Threshold
On-to-Off Hook
Off-to-On Hook

RNF
RFN

2.0

-

3.1
7.0

Fault Detection Threshold
Ring-to-Ground (RL = 600 0)
Tip-to-Battery (RL = 600 0)

RRG
RTB

600
600

660
660

-

GTXl

-

0.328

-

-0.3
-0.1
-0.15

0.0
0.0
0.0
±0.1

+0.3
+0.1
+0.15

-

0.05

-

-

a
kO

10

a

·Calculaled from 1(48JILMN) - I BOO)

GAIN LEVELS
Transmit Voltage Gain (CP, CN to TXO)
Transmit Voltage Gain (VTXNL)
VL = dBm, I = 1.0 kHz
VL = dBm, 1= 3.4 kHz, with respect to GTX2
VL = +3.0 dBm, I = 1.0 kHz, with respect to GTX2
VL = - 48 dBm, I = 1.0 kHz, with respect to GTX2

a
a

dB
GTX2

-

-

Transmit Distortion (at Pin 11)
(I = 300 Hz to 4.0 kHz, - 40 dBm:s VT-R :s +5.0 dBm)

THDT

Receive Current Gain (lEP/IRXI)

GRXI

94

102

110

GRX2

-0.3
-0.1
-0.15

0.0
0.0
0.0
±D.l

+0.3
+0.1
+0.15

-

0.05

-

RL

30

>40

THR

-

44

58
58

64
64

2-Wire Balance; I = 330 Hz, Zac = 600 a (@ Tip/Ring)
4-Wire Balance, I = 330 Hz, Zac = 600 a (@ VTX)

58
58

64
64

2-Wire Balance, I = 3.3 kHz, Zac = 600 a (@ Tip/Ring)
4-Wlre Balance, I = 3.3 kHz, Zac = 600 a (@ VTX)

53
53

60
60

2-Wire Balance, I = 1.0 kHz, Zac = 900 a (@ Tip/Ring)
4-Wire Balance, I = 1.0 kHz, Zac = 900 a (@ VTX)

-

62
62

Receive Voltage Gain (VLNRXI) (RL = 600 0)
VRXI =OdBm, I = 1.0 kHz
VRXI = dBm, I = 3.4 kHz, with respect to GRX2
VRXI = +3.0 dBm, I = 1.0 kHz, with respect to GRX2
VRXI = - 46 dBm, I = 1.0 kHz, with respect to GRX2

a

Receive Distortion
(I = 300 Hz to 4.0 kHz, - 40 dBm :s VRXI :s +5.0 dBm)
Return Loss (Relerence = 600

a resistive, I = 1.0 kHz)

Transhybrid Rejection (RL = 600 0, I = 1.0 kHz, Figure 4)

VN

%
mA/mA
dB

-

THDR

-

-

%
dB
dB

LONGITUDINAL SIGNALS (VCM = 5.12 Vrms, see Figures 1 and 2)
2-Wire Balance, I = 1.0 kHz, Zac = 600 a (@ Tip/Ring)
4-Wire Balance, I = 1.0 kHz, Zac = 600 a (@ VTX)

LB

Signal Balance, I = 1,0 kHz (Figure 3)
Longitudinal Impedance, RS = 9100 a
Maximum Longitudinal Current per side
I = 1.0 kHz, ILOOP .; ILMN, CT = 0.1 IlF

MC33120
2-234

ZLONG

-

-

40

55

-

150

180

210

ILM
8.5

16

dB

-

a
mA

MOTOROLA COMMUNICATIONS DEVICE DATA

ELECTRICAL CHARACTERISTICS (VEE=- 48 V, VOO =+5.0 V, unless otherwise noted, VCC = VAG = VOG, T A =25'C, see Figure 1)

I

I

Characteristic

Symbol

I

Min

I

Typ

I

Max

I

Unit

LOGIC INTERFACE
8T1 Output Voltage
Low (18T1 = 1.0 rnA, VOO = 5.5 V)
High (18T1 = - 100 1lA, VOO = 4.5 V)

VOL
VOH

VOG
2.4

0.17
3.2

0.4

Vdc

8T2 Output Voltage
Low (18T2 = 1.0 rnA, VOO = 5.5 V)
High (18T2 = - 100 (.lA, VOO = 4.5 V)

VOL
VOH

VOG
2.4

0.17
4.3

0.4

TIme Oelay
Hookswitch Closure to 8T1 Change
Hookswilch Opening to 8T1 Change

t8T11
18T12

-

10
200

-

-

19

-

ms

18
10

-

ms
(.lS

-800
-800

-300

-

0.8
VOO

-

(.lS

Hookswitch Closure to 90% of Loop Current (C;- = 0.1 (.IF)
POI Taken High-to-Low to 10% of Loop Current
POI Taken Low-to-High to 90% of Loop Current

tH8
t8T21
t8T22

POI Input Current
VpOI = 3.0 V, RL = 600 n, VOO = 5.0 V
VPOI = 0 V, RL = 600 n, VOO = 5.5 V

-

IlA

IIH
-1250

-

POI Input Voltage
Low
High

V

VIL
VIH

VOG
2.0

-

MISCELLANEOUS
Vas Voltage (Vas - VEE)
@IL=20mA
@IL=40mA

Vas

-

0.82
0.95

TXO Offset Voltage (VTXO - VAG) @ RL = 600 n

VTXO

-400

+30

TXO Output Current

ITXO

±275

±800

RXI Offset Voltage (VRXI- VAG) @ RL = 600 n
VAG Input Current @ RL = 600 n
Idle Channel Noise (with C-message filter, RL = 600 n)
@TXO(Pin 11)
@TIp/Ring
Thermal Resistance - Junction to Ambient
(Either package, in still air, soldered to a PC board)

MOTOROLA COMMUNICATIONS DEVICE DATA

-

-

Vdc

-

+400

VRX08

-

0.8

-

IVAG

-

0.2

-

mVdc

IlA pk
mVdc
(.lA
dSrnc

NIC4
NIC2
°JA
(@TA=+25'C)
(@ T A = +85'C)

-

-10
-5.0

-

62
36

-

-

'CIW

-

MC33120
2-235

FIGURE 1 -

20
19

IEPtp

P

r

VL

L

-

RP

RC

IL

RL

TIP

1.0 k
9.1 k

RING

RS
RS

17
16

TEST CIRCUIT

VOO

VCC

ST2IPOI

+5.0 V

12

BP

POI/ST2
CT
0.1
13
STI r - - t - - - - - - - S T I

CP

VOG

EP

...

TSI

14

VAG

'"

M

8::i

CN

RRX
Receive
1-....----'V'V'v--- ln (VRXI)
30.9 k
RRO
20.3 k
RFO

BN

TXO

EN

CF

RSI

9.1 k
1.0 k

15

RC

RP

lOI I
Componen1s shown for a 600 Q syslem.
Three grounds are connected directly together.

VOB

VEE

11

301
6
20

-48 V

*

Note: Pin numbers reler to DIP package.

FIGURE 2 -

LONGITUDINAL BALANCE TEST

(Per IEEE·455)

TIP
MC33120 TEST
CIRCUIT (FIG. 1)

~

368
0.01%

4·Wire Balance = 20 (log V#VCM)
2·Wire Balance = 20 (log V2NCM)

RING

Y5.12vrms

FIGURE 3 -

SIGNAL BALANCE TEST

TIP
MC33120 TEST
CIRCUIT (FIG. 1)

368
0.01%

RING

Vin
OdBm
1.0 kHz

Signal Balance = 20 (log VeNin)

MC33120
2-236

MOTOROLA COMMUNICATIONS DEVICE DATA

s::
o

d

e
()

o
s::
s::
c

FIGURE 4 - APPLICATION CIRCUIT

z

o
~

5z

-

CIl

o

~
om
o
»~

:1

, I"

VCC

19 EP
MJD253

-

TIP

RL~

RING

V
EE

RP
100

1.0 k, 2%

18 BP

:tj~'
RS

5 RSI
4 CN

VDG

STl

114

VAG
MC3312D
RXlll0 ,

'\7 ,

~I

RFO

1.0 k, 2%
BN

•

STl1 13

17 CP

MJD243

STVPDI

5.0I'F! CT

RC

9.1 k
RC

••

STV:: 12

...........-]

IL

o +5.0 V

Txolll

CRO
1.0 l'FI

RTX1

W
10 k

300

EN
Component values shown
for a 600 n system.

0
-48 V

Note: Pin numbers relerto DIP package.

iii:

o

I\)W

.W

1\)'"
WI\)

"-.Ie

1 'I

VEE

~0.1

CF~

CCF (11'F)

vaB~~
COB (10 I'F)
~

• Receive In (VRXI)
600

PIN DESCRIPTION
Pin
Name

DIP

PLCC

VCC

20

28

Connect to noise-free Battery ground_ Carries loop current and some bias currents_

Description

EP

19

27

Connect to the emitter of the PNP pass transistor.

BP

18

26

Connect to the base of the PNP pass transistor.

CP

17

24

Connect to TIP through a current limiting protection resistor (RC)' CP is the non inverting input to the
internal transmit amplifier (Figure 28). Input impedance is 31 kf.!.

TSI

16

23

Sense input. Connect to TIP through a current limiting protection resistor (RS) which also sets the
longitudinal impedance. Input impedance is ~100 il to VCC.

VDD

15

22

Connectto a +5.0 V, ±1 0% supply, referenced to digital ground. Powers logic section and provides some
bias currents for the loop current drivers.

VDG

14

20

Digital Ground. Reference for ST1, ST2 and VDD. Connect to system digital ground.

STI

13

18

Status Output (TTUCMOS). Indicates hook switch status - High when on-hook, low when off-hook,
and pulse dialing information. Used with ST2 to indicate fault conditions.

ST2IPDI

12

17

Status output and an input (TTUCMOS). As an output, ST2 can indicate hook status - Low when
on-hook, high when off-hook. Used with STI to indicate fault conditions. As an input, it can be taken
low (when off-hook) to deny subscriber loop current.

TXO

11

16

Transmit voltage output. Amplitude is ~1/3 that across CP and CN. Nominally capable of 800 J1A output
current. DC referenced to VAG.

RXI

10

14

Receive current input. Current at this pin is multiplied by 102 at EP and EN to generate loop current.
RXI is a virtual ground at VAG level. Current flow is out of this pin.

VAG

9

13

Analog ground, reference for TXO and RX!. Connect to system analog ground.

RFO

8

12

A resistor between this pin and RXI sets the maximum loop current and DC feed resistance. Minimum
resistor value is 3.3 k (see Figures 5-7).

CF

7

10

A low leakage capacitor between this pin and VAG provides DC and AC signal separation. A series
resistor is required for battery supply turn-on/off transient protection (Figure 4).

VOB

6

8

Ouiet Battery. A capacitor between VOB and VCC filters noise and ripple from VEE, providing a quiet
battery source for the speech amplifiers. A series resistor is required for battery supply turn-on/off
transient protection (Figure 4).

RSI

5

7

Sense input. Connect to RING through a current limiting protection resistor which also sets the
longitudinal impedance. Input impedance is ~100 il to VOB.

CN

4

6

Connect to RING through a current limiting protection resistor. CN is the inverting input to the internal
transmit amplifier (Figure 28). Input impedance is 31 kil.

BN

3

4

Connect to the base of the NPN pass transistor.

EN

2

3

Connect to the emitter of the NPN pass transistor.

VEE

1

2

Connect to battery voltage. Nominally - 48 V, it can range from - 42 to - 58 V.

(Pins 1, 5, 9. 11, 15. 19, 21, and 25 are not internally connected on the PLCC package).

MC33120
2-238

MOTOROLA COMMUNICATIONS DEVICE DATA

FIGURE 6 - LOOP CURRENT versus LOOP
RESISTANCE AND RRF

FIGURE 5 - LOOP CURRENT versus LOOP
RESISTANCE AND RRF

50

..-g

..-g

40

0-

0-

w

w

::J
U

::J
U

:z

:z

a:
a:

a:
a: 30

0.

0.

0

0

9

20

9

RS=9.1 k -10kO
VEE=-42V
TA = 25°C

10 0

400

800
1200
LOOP RESISTANCE (0)

1600

10 0

2000

800
1200
LOOP RESISTANCE (0)

400

FIGURE 7 - LOOP CURRENT versus LOOP
RESISTANCE AND RRF

1600

2000

FIGURE 8 - OFF-HOOK TO ON-HOOK
THRESHOLD versus RRF

15 k

r- -58 VSVEES-42 V
5.1 kSRSSll k
13 k r- 4.5VSVOOS5.5V
r- TA = 25°C

§:
c
5
:I:

..-g

./
./

en
w
a: 11 k

0-

:z
w

..".,-

:I:
0-

a:
a:

w

::J
U

U

./

~ 9.0k

0.

0

,/'

Ii)
u;

9

::: 7.0 k

./

0

9
5.0 k

""

/"

w

3.0k

4.0k

LOOP RESISTANCE (0)

5.0k

6.0k
7.0k
RRF(O)

8.0k

9.0k

FIGURE 10"": IDD versus LOOP CURRENT

FIGURE 9 - ON-HOOK TO OFF-HOOK
THRESHOLD versus RS

5.0 k

-58 V1:5 VEE:5 ~2 V
- 3.9k:5 RRF :510 k
§:
4.5V:5VOO:55.5V
9 4.0k _ TA
= 25°C
o

..-g

15
VEE =-48 V
TA=25°C
VOO = +5.0 V
RRF =47000

c

.E?
>-=
:z

:I:

ffi
a:

w

a:
a:
u 10
en

:I:

:;:; 3.0 k
~
;::':
en
iii
2.0 k
a:

/"

MOTOROLA COMMUNICATIONS DEVICE DATA

.../

Dl

-'

<
:z

a:
w

0~

7.0k
8.0k
9.0k
10k
RS SENSE RESISTANCE (0)

/

:$

-"
6.0k

/'~

::J

§
1.0 k
5.0k

11 k

10k

12k

~

5.0
20

30

40

45

LOOP CURRENT, ILOOP (rnA)

MC33120
2-239

FIGURE 12 - FAULT THRESHOLD (OFF-HOOK)
versus LOOP RESISTANCE

FIGURE 11 - FAULT THRESHOLD
(ON-HOOK) versus RS

3.0 k

~

a:

2.0k

§?
ffl
a:

i!:

!:;

~

..... ...........-

Tip-to-VEE

---- ---- ---

l..---

............... ;;7

I.Sk

:::>

it

...............

1.0k S.Ok

RS=11 k

§: 2.4k

9-

9

7.0 k

. . -Ring-to-Ground

/ L/
// /

§?
rJ)

~ 1.2k

!:;

00

11 k

/.
V /

/

i!:

~ 600

9.0 k

/
//

~

~ 1.8k

./

/

""": V

-

/
/

~

a:

/

§ 1.8k

/
I 1/
// /
........-::
/
/
::;.

:I:
rJ)

W

~

/

1.2k

!:;

:::>

it 600

:::-

,.."

SOO

/

./

SOO

a:

1.8k

!l!

1.2 k

!:;
~

600

9
§?

S.11!:;
:I:

:::>

it 200

oS.Ok

.

>=

-7.0k

'v

MC33120
2-240

60

/7.Sk

TA=2SoC
Ring-to-Ground
and/or Tip-ta-VEE
S.1 k
2.0k

1.0k
1.Sk
LOOP RESISTANCE, RL (n)

III

w

Tip-ta-Ground
----~

11k

0-

a:

i'
i'

~

a:

-'
0-

VEE =-48 V
TA = 2SoC
20 rnA,; ILOOP'; 40 rnA

1(1

2-Wire

w

;;.- ~

9.0 k
RS (n)

/
V/
1/

W

Ul

Ring-to-VEE

~

-

/ 1/ /
/J / VEE =-58 V

~

4-Wi~~

ill
0

:I:

2.0k

FIGURE 16 - VDD RIPPLE REJECTION
versus FREQUENCY

a:

rJ)

./

/
./ /
SOO

2.0 k

80

0

V/

7.S k
S.lk

-42V"vEE';-58J
TA=2SoC
200n< RL < 1.0 kQ
(See Text)

-'

VEE =--42 V
TA = 2SoC
Ring-to-Ground
and/or Tip-to-VEE

'is.l k

i!:

FIGURE 15 - FAULT THRESHOLD
(OFF-HOOK) versus RS
1.0 k

/i"'"

RS=llk/J

~

/

1/

S.1 k

9-

/r.Sk

/

./'

~

1.0k
I.Sk
LOOP RESISTANCE, RL (n)

_ 2.4k

/

/

7.Sk

3.0 k

9.1 k

RS=11 k

./

./

FIGURE 14 - FAULT THRESHOLD (OFF-HOOK)
versus LOOP RESISTANCE

FIGURE 13 - FAULT THRESHOLD (OFF-HOOK)
versus LOOP RESISTANCE

3.0 k

9.1k

'"/'

./

RS (n)

§: 2.4k

,.VV~

3.0 k

1.1.

_ --42 V,; VEE ';-S8 V
TA=2SoC
_ 2.Sk - RL = Open

40

100

1.0 k

110"",1::::

--"'

10 k

20 k

t, FREQUENCY (Hz)

MOTOROLA COMMUNICATIONS DEVICE DATA

FIGURE 17 -

FIGURE 18 - VEE RIPPLE REJECTION versus
FREQUENCY AND CQB

VEE RIPPLE REJECTION

versus FREQUENCY
80

80

iII
:!l.
z 60
0

~~

;:::
u
~

c;:

:!l.

VEE=-48V
TA = 25°C
20 mA ~ ILOOP ~ 40 mA
COB= lO IlF

20

§w

60

w

~

c;:

V

a:

...J
0..
0..

~.......... i"""

40

V
",.",.

1.0k

10 k

20

20 k

1.0

.1_

~
w

(!l

~ 0.4

!:i0

~I-

§
cl

-

0.3
0.2

>

~
0.1

...........
~

V

>
l=>
0..
l-

5.0

I'---

......... ........ VOO = +5.5 V

...............
4.0

~ ........

.

=>

Voo = +4.5 V

0

:i:

I

0

> 3.0

"""

...............
.........

...........

0.5

1.0

1.5

2.0

2.0

FIGURE 21 -

.1"

I"--...

...............
o

..........

""-..

'"

-50
-100
-150
IoH, OUTPUT CURRENT (1lA)

IOL' OUTPUT CURRENT (mA)

0.6

ST1, VOH versus IOH

TA=25°C

o
o

2-wire

10
20
COB, CAPACITOR (IlF)

FIGURE 20 -

(!l

:::J

r

6.0

4.5 V~VOo~ 5.5 V
TA = 25°C

~ 0.5
w

1.0kHz
300 Hz
4.0 kHz

V

FIGURE 19-5T1, VOL versus IOl
.1

~

4-wire

",.

I, FREOUENCY (Hz)

0.6

~

1.0kHz
300 Hz
4.0 kHz

-

..,.

'7'

Lil

I'-.

~-

---=

I-"'"

100

20

z

r-........ r--

-t-"'2-Wire
40

iII

........

I

w

Lil
a:
0..
0..

-

VEE =-48 V
TA = 25°C
20 mA ~ ILOOP ~ 40 mA

ST2, VOL versus IOl

FIGURE 22 -

-200

ST2, VOH versus IOH

6.0

.L

4.5V~VOO~5.5V

~ 0.5

w

TA = 25°C

!:§

g
~

0..

~

~

,

(!l

w

(!l

!:ig

0.4

5.0

l-

=>

0.3

r==>

o

o/
o

VOO=5.5V

_

VOO = 4.5 V

I

0

~ 0.2
0.1

4.0

_

:i:
0

> 3.0

I,..--"

TA = 25°C

~
0.25

0.5

0.75

IOL' OUTPUT CURRENT (mA)

MOTOROLA COMMUNICATIONS DEVICE DATA

1.0

2.0

o

-100

-200

-300

-400

-500

IOH, OUTPUT CURRENT (IlA)

MC33120
2-241

FIGURE 23 -IC POWER DISSIPATION versus
LOOP RESISTANCE AND VEE

FIGURE 24 - TRANSISTOR POWER DISSIPATION
versus LOOP RESISTANCE AND RRF
[ 1.6
a:

1.5

r-....

VEE =-48 V, _
except as noted
TA=25°C
VOO=+5.0V -

t-- RRF = 6200

r-."

400

~
~

VEp-56V
........RRF = 3900

""" --""1-0.

........ r-....

.RRi=10k
H~
l

o

~ 1.2

r=

r-....
I

0.5

-

...........

800

~

1200

0.8

~

--....

~

13

0.4

~

~RF=10~ ~

a:

~

0

K+=6doo,

~ ~"'h.

w

2000

VEE =-48 V,
except as noted TA = 25°C
Rp=1000

~RRF=~900

Cl

1600

I I

VEE=-56V
RRF =3900

:c

RRF = 3900...........

0.7

!2
en
en

o

~~

I
400

800

1200

1600

LOOP RESISTANCE (0)

LOOP RESISTANCE (0)

FIGURE 25 - MAXIMUM LONGITUDINAL CURRENT
versus LOOP CURRENT

FIGURE 26 - MAXIMUM LONGITUDINAL CURRENT
versus CT, RT AND FREQUENCY

2000


::;;

40

~

V"

./

/

~

Rr=20kf=60Hz
00.1

ST2 RT

~

1.0
CT(I'F)

VEE = -48 V
TA=25°C
CT ILOOP = 20 rnA
RS=9.1k
10

MOTOROLA COMMUNICATIONS DEVICE DATA

FUNCTIONAL DESCRIPTION
Introduction
The MC33120 is a solid state SLiC (Subscriber Line
Interface Circuit) which provides the interface between the
two wire telephone line and the four wire side of a Central
Office or PBX. Most of the BORSCHT functions are provided,
specifically:
-

Battery feed of the loop current to the line, with programmable maximum current for short lines and battery feed resistance for long lines.
- Overvoltage protection through internal clamp diodes and
external resistors and diodes.
- Supervision, in that hook status is indicated in the presence
of ;::30 kn leakage, and regardless of whether or not the circuit is powered down intentionally by the Central Office or
PBX. Fault conditions are detected and indicated to the
system. Dialing (pulse and DTMF) information is passed
through the MC33120 to the 4-wire side.
- Hybrid function, in thatthe MC33120 is a 2-to-4 wire converter. Transmit, receive, return loss, and transhybrid gains
are independently adjustable.
The MC33120 does not provide ring insertion, ring trip,
digital coding/decoding of the speech signals, nor test functions. These must be provided external to this device.
The MC33120 controls two external transistors (one NPN
and one PNP) through which the loop current flows. By
appropriate circuit design, the power dissipation (which can
exceed 3.0 watts under certain worst case conditions) is

FIGURE 27 -

100

RP 1.0k

TIP

RC 9.1 k

I
I
lSI I
CP

approximately equally distributed among the two transistors
and the IC, thereby lowering junction temperatures and
increasing long term reliability. In most situations, heatsinks
will not be required.
The MC33120 incorporates critical sense resistors internally, which are trimmed for optimum performance. With this
technique, the external resistors on the two wire side, which
generally must be high wattage for transient protection reasons, can be non-precision.
Longitudinal balance is tested to a minimum of 58 dB @
1 .0 kHz (refer to Electrical Characteristics and Figure 1) for
both the two wire and four wire side, and typically measures
in the mid-60s. The longitudinal current capability is tested
to a minimum of 8.5 mArms per side (refer to Electrical
Characteristics and Figure 1) at a loop current of 20 mA.
Following is a description of the individual sections. Figure
4 is the reference schematic.
DC Loop Current
The DC loop current is determined by the battery voltage
(VEE)' the load resistance across lip and Ring, and the
resistor at RFO. Varying the 4 resistors RS and RC will
influence the loop current a small amount «5%). The curves
of Figures 5-7 indicate the loop current versus loop resistance, different values of RRF, and for various values of VEE.
The graphs represent performance at TA = 25°C and after
the IC had reached a steady state temperature (>5 minutes).

DC LOOP CURRENT PATH

--

Analog
Ground

ICp

RS
RS

~ IAXI

-

ICN

1.Ok
100

RP

RRF

31 k

ILOOP

RFO

vaB
=O.BV

---------------------~

MOTOROLA COMMUNICATIONS DEVICE DATA

MC33120
2-243

Figure 27 is representative of the DC loop current path
(bold lines). On a long line (RL > 1.0 kn), the loop current
can be determined from the following equation:
I
_ (IVEEI-3.6V)o13
LOOP - RRF + {(RL + 5) 0 13}

The battery feed resistance (aVTIP/aIL) is =400 n, but
depends on the loop current, VEE, RRF, and is a valid
parameter only on long lines where the current limit is not
in effect. On short lines, the feed resistance is high since
the loop current is clamped at a constant level. The AC
impedance (Return Loss) however, is not determined nor
affected by the DC parameters. See the Applications Section
for Return Loss information.

(Equation 1)

On short lines (RL < 1.0 kn), the three diodes across the
12.4 k resistor clamp the voltage at RFO, thereby preventing
the RXI current from increasing as the load resistance is
decreased. The maximum loop current is:
.

ILOOP (MAX) =

Transmit Path
The transmit path, shown in Figure 28, consists of an
internal amplifier which has inputs at CP and CN, and its
output at TXO. The gain is internally fixed at 0.328 V/V
(-9.7 dB). The output is in phase with the signal at CP
(normally the same as TIP), and is out of phase with the
signal at CN. The Signal at TXO is also out of phase with
that at VRX, the receive signal input, described in another
section.

1.85 V 0 102 (T
250C)
RRF
A=
(Equation 2)

Due to the temperature dependence of a diode's forward
voltage, the maximum loop current will change with temperature by = -0.3%/oC.

FIGURE 28 - TRANSMIT PATH

TIP

1.0 k

RC

r------------.., VAG

CP 117

31

k

91---"=--"'---'

AC

VOO

V

I
I

11
AV= I TXO
0.328 I

I
31 k -= AC
OB
I
MC3312D:.JI
IL ____________
The TXO output can swing =3.0 Vp-p, with a nominal
current capability of ±800 ILA peak (±275 ILA minimum). The
load on TXO is the parallel combination of RTX1 and the
RRO network (described later). TXO is nominally internally
biased at the VAG DC level, but has an offset which varies
with loop current.
In normal applications, the signal at CP/CN is reduced
slightly from that at Tip/Ring by the voltage divider composed
of the external RC resistors, and the internal 31 k resistors.
The value of the RC resistors depends on the transient
protection needed, described in another section, with 1.0 kn
resistors being suitable for most applications. The resulting
signal at TXO needs to be gained up to obtain 0 dB from
Tip/Ring to VTX (the 4-wire ou.\put). The common method
involves an external op amp, as shown in Figure 28, with
a gain of RTX2/RTX1. The gain from VL to VTX is:

»f---VTX

Nole: Op amp may be part

of acodeclfilter.

If a codee/filter is used, many of which include an internal
op amp, a separate op amp is not needed. CTX is primarily
for DC blocking (of the TXO offset), and is usually large (1.0
ILF) so as to not affect the gain.

mirrored to the two transistor drivers which provide a gain
of 102. The two external transistors are then two current
sources, in series, operating at the same value. An additional
internal circuit (not shown) balances the two current sources
to maintain operation in their linear region.
The load current (through RL) is slightly different from the
transistor current due to the sense resistors RC and RS. The
sense resistors add to the DC loop current, but subtract from
the AC load current.
In normal operation, the current at RXI is composed of a
DC current (from RFO), an AC current (from VRX) which
is the receive signal, and an AC current from TXO, which
is the feedback signal to set the return loss (setting the return
loss is discussed in the section on AC Terminating Impedance). The resulting AC signal at Tip is inverted from that
at VRX, while the signal at Ring is in phase with VRX.
The resistors RP are for transient protection, and their
value (defined in another section) depends on the amount
of protection required. A·nominal value of 100 n is suitable
for most applications.
The system receive gain, from VRX to Tip/Ring, is not
described in this section since in normal applications, it
involves the feedback which sets the AC terminating impedance. The Applications Section discusses these in detail.

Receive Path
The receive path, shown in Figure 29, consists of the input
at RXI, the transistor driver amplifiers, the external transistors, and the load at Tip/Ring.
.
RXI is a virtual ground (DC level = VAG) and is a current
input. Current flow is out of the pin. The RXI current is

Logic Interface (Hook status, pulse dialing, faults)
The logic interface section provides hookswitch status,
fault information, and pulse dialing information to the 4-wire
side of the system at the ST1 and ST2 outputs. Figure 30
is a representative diagram.

VTX
RTX2 031 k 0 0.328
VL = RTX1 0 (RC + 31 k)

MC33120
2-244

(Equation 3)

MOTOROLA COMMUNICATIONS DEVICE DATA

FIGURE 29 - RECEIVE PATH

FIGURE 30 - LOGIC INTERFACE

r--------------------------, VDD
1
I
BOOIlA + 15
1
1
1
1
CP I 17

Hook
Switch

+5.0 V

r----,H...-...:.=..i--.-""""..........~ Status 2

To Loop
Current
Drivers

Extemal
Power Down
Control
Input

Hook Status
Detection

L--'.;;~~~---r-fF:;;au~lt-l.r Fault
RS

Detection

RSI15

1
1

.....---.:.:.r:..;.;..--..

I1

Status 1

141 VD

MC33120
L __________________________
~1

The logic outputs operate according to the truth table in
Table 1:
TABLE 1 - STATUS OUTPUT TRUTH TABLE
Hook
Status
On Hook
Off Hook
On Hook
Off Hook

Fault
Detection
No Fault
No Fault
Fault
Fault

Outputs
ST1

ST2

Hi
Lo
Lo
Lo

Lo
Hi
Lo
Lo

Circuit Condition
Internally powered down
Powered up
Internally powered down
Internally powered down

Referring to Figure 30, STI is configured as an active NPN
pulldown with a 15 kQ pullup resistor. ST2 has a 800 j.lA
current source pullup, and a 1.0 mA current source for a
pulldown. Current limiting this output controls the discharge
from the external capacitor when ST2 switches low.
The condition where bothSTI and ST2 are high is not
valid, but may occur momentarily during an off-hook to

MOTOROLA COMMUNICATIONS DEVICE DATA

on-hook transition. The condition where both STI and ST2
are low may occur momentarily during an on-hook to off-hook
transition - this should not be interpreted as a fault condition.
STI and ST2 are nUCMOS compatible and are powered
by the +5.0 V supply (VDD). Refer to the Applications Section
for more details.
Power Supplies, Grounds
The MC33120 requires 2 power supplies: battery voltage
between - 42 V and - 58 V (VEE)' and an auxiliary voltage
between +4.5 V and +5.5 V (VDD)'
VEE is nominally - 48 V, with a typical range of - 42 V
to - 58 V, and must be referenced to VCC (battery ground).
A 0.1 j.lF bypass capacitor should be provided between VCC
and VEE. The VEE current (lEE) is nominally 1.2 mA when
on-hook, 10 to 14 mA more than the loop current when
off-hook, and ~8.0 mA when off-hook but powered down by
using the PDI pin. Ripple and noise rejection from VEE is
a minimum of 40 dS (with a 10 j.lF capacitor at Vas), and

MC33120
2-245

is dependent on the size and quality of the VOB capacitor
(COB) since VOB is the actual internal supply voltage for
the speech amplifiers. The absolute maximum for VEE is
- 60 V, and should not be exceeded by the combination of
the battery voltage, its tolerance, and its ripple.
VOO is normally supplied from the line card's digital +5.0
V supply, and is referenced to VOG (digital ground). A 0.1
IlF capacitor should be provided between VOO and VOG.
The VOO current (100) is nominally 1.7 mA when on-hook
and between 6.0 and 11 mA when off-hook (see Figure 10).
When the MC33120 is intentionally powered down using the
POI pin, 100 changes by <1.0 mA from the normal off-hook
value.
.
VAG is the analog ground for the MC33120, and is the
reference for the speech signals (RXI and TXO). Current flow
is Into the pin, and is typically <0.5 !lAo
Normally, VCC, VOG and VAG are to be at the same OC

level. However, if strong transients are expected at Tip and
Ring, as in a Central Office application, VCC should not be
connected directly to VOG and VAG in order to prevent
possible damage to the +5.0 V system. The MC33120 is
designed to tolerate as much as ±30 V between VCC and
the other two grounds on a transient basis only. This
feature permits VCC and the other grounds to be kept
separate (on an AC basis) on the line card by transient
suppressors; or to be connected together farther into the
system (at the power supplies). See the Applications Section
on ground arrangements and transient protection for further
information on connecting the MC33120 to the system supplies.
For operation of the MC33120 at supply voltages other
than - 42 to - 58 V (such as - 24 V or - 28 V), contact your
local Motorola sales office.

APPLICATIONS INFORMATION
This section contains information on the following topics:
Design Procedure .............................. pg. 15
Power Dissipation Calculations
and Considerations .......................... pg. 22
Selecting the Transistors ....................... pg. 23
Design Procedure
This section describes the step-by-step sequence for
designing in the MC33120 SLiC into a typical line card
application for either a PBX or Central Office. The sequence
is important so that each new component value which is
calculated does not affect components previously determined. Figure 4 (Typical Application Circuit) is the reference
circuit for most of this discussion. The recommended sequence (detailed below), consists of establishing the OC
aspects first, and then the AC aspects:
1) Oetermine the maximum loop current for the shortest line,
select RRF. Power dissipation must be considered here.
2) Select the main protection resistors (RP), and diodes,
based on the expected transient voltages. Transient protection configuration must also be considered here.
3) Select RC based on the expected transient voltages.
4) Select RS based on the desired longitudinal impedance at
Tip and Ring. Transient voltages are also a factor here.
5) Calculate RRO based on the desired AC terminating impedance (return loss).
6) Calculate RRX based on the desired receive gain.
7) Calculate RTX2 and RTXl based on the desired transmit
gain.
8) Calculate the balance resistor (RB), or network, as appropriate for desired transhybrid rejection.
9) Logic Interface
Preliminary
There is a primary AC feedback loop which has its main
sense points at CP and CN (see Figure 34). The loop extends
from there to TXO, through RRO to RXI, through the internal
amplifiers to the transistor drivers, through RP to Tip and
Ring, and through the RCs to CP and CN. Components within
this loop, such as RP, RC, the transistors, and the compensation capacitors need not be tightly matched to each other
in order to maintain good longitudinal balance. The tolerance

MC33120
2-246

Longitudinal Current capability ................ pg. 23
PC Board Layout Considerations ............... pg.24
Alternate Circuit Configurations. . . . . . . . . . . . . . .. pg. 26

requirements on these components, and others, are described in subsequent sections. Any components, however,
which are placed outside the loop for additional line card
functions, such as test relay contacts, fuses, resistors in
series with Tip and Ring, etc. will affect longitudinal balance,
signal balance, and gains if their values and mismatch is not
carefully considered. The MC33120 cannot compensate for
mismatch among components outside the loop.
The compensation capaCitors (0:01 IlF) shown at the
transistor collectors (Figure 4) compensate the transistor
driver amplifiers, providing the required loop stability. The
required tolerance on these capacitors can be determined
from the following guidelines:
AI 0% mismatch (±5% tolerance) will degrade the longitudinal balance by =1.0 dB on a 60 dB device, and by =3.0 dB
on a 70 dB device.
A 20% mismatch (±1 0% tolerance) will degrade thlliongitudinal balance by =3.0 dB on a 60 dB device, and by =6.0 dB
on a 70 dB device.
High quality ceramic capaCitors are recommended since they
serve the secondary function of providing a bleedoff path for
RF signals picked up on the phone line. These capacitors
should be connected to a good quality RF ground.
The capaCitors used at COB and CF must be low leakage
to obtain proper performance. Leakage at the COB capaCitor
will affect the DC loop current characteristics, while leakage
at the CF capacitor will affect the AC gain parameters.
1) Maximum Loop Current and Battery Feed Resistance
The maximum loop current (at RL = 0) is determined by
the RRF resistor between RFO and RXI. The current limit
is accomplished by three internal series diodes (see Figure
27) which clamp the voltage across RRF as the loop resistance decreases, thereby limiting the current at RXI. Since
the loop current is 102 x IRXI, thll loop current is therefore

MOTOROLA COMMUNICATIONS DEVICE DATA

clamped. The graphs of Figures 5-7 indicate the maximum
loop current at an ambient temperature of +25'C, and after
the IC has reached thermal equilibrium (approx. 10 minutes).
Although the maximum loop current is primarily a function
of the RRF resistor, it is also affected by ambient temperature, and slightly by VEE. The ambient temperature effects
are due to the temperature dependence of the diodes'
forward voltage drop, causing the maximum loop current to
change by ~ - 0.3%I'C. Changing VEE affects the maximum
current in that the power dissipation is changed, thereby
changing the die temperature, which affects the diodes'
voltage.
The maximum loop current is affected slightly «5%) by
the choice of the RS and RC resistors, since the sense
currents through those resistors add to the current supplied
by the transistors.
The battery feed resistance is determined by RRF, and is
not adjustable independently of the current limit. Defined as
L\.VTIP/L\.IL, it is ~400 Q, and is a valid parameter only on long
lines where the current limit is not in effect. On short lines,
the feed resistance is high since the loop current is clamped
at a near constant level. The AC impedance (return loss)
however, is not determined nor affected by these DC parameters. Return loss is discussed in another section.
If the application requires that the current limit value have
a low temperature dependence, refer to the section following
this design sequence which describes an alternate
configuration.
2) Main Protection Resistors (RP) and Transient Currents
The purpose of the protection resistors (RP), along with
the 4 clamp diodes shown in Figure 4, is to absorb the bulk
of the transient energy when transient voltages come in from
the phone line. The resistor value must be selected to limit
the transient current to a value which can be tolerated by
the diodes, while dissipating the energy. The recommended
value shown (100 Q) will limit the current from a 1500 V
transient to 15 A, which can be carried by 1N4002 diodes
under surge conditions. The resistors must be of a type which
can tolerate the high instantaneous energy associated with
transients. Resistor manufacturers should be consulted for
this information.
Referring to Figure 4, a positive transient on either Tip or
Ring, or both, will cause the transient current to be delivered
to Ground. A negative transient will cause the transient
current to come from the VEE supply line. Therefore, the PC
board track supplying VCC and VEE to the MC33120 must
be designed to carry the transient currents as well as the
normal operating currents. Additionally, since a negative
transient will cause a current flow out of the power supply's
negative output, which is opposite to the normal flow of
current, provisions must be made for this reverse current
flow. One suggested method is to place a zener transient
suppressor (1 N5290A) across the battery supply pins (VCC
to VEE) physically adjacent to the MC33120. The inductance associated with PC board tracks and wiring will result
in insufficient protection for the MC33120 if the suppressor
is located at the opposite end of the line card, or at the power
supplies.
Transient currents can be reduced by increasing the value
of RP, with an upper limit determined by the DC conditions
on the longest line (highest loop resistance) and minimum
VEE supply voltage. These conditions determine the

MOTOROLA COMMUNICATIONS DEVICE DATA

minimum DC voltage across the transistors, which must be
sufficient to handle the largest AC (transmit and receive)
signals. If too large a value is selected for RP, the AC signals
will be clipped. It is recommended that each transistor have
no less than one volt (DC) across their collector to emitter.
System AC speCifications may require more than this.
Since the RP resistors are within the loop, their tolerance
can be ±5% with no substantial degradation of longitudinal
balance. A ±10% tolerance (20% mismatch) will degrade
balance by ~4.0 dB on a 55 dB device.
FIGURE 32 -

RC PROTECTION RESISTORS

AV=

1

0.328 1

1
_ _ _ _ _ _ _ _ _ _MC33120
_ _ _ J1
1 _VEE
~

3) Selecting the RC Resistors
The primary purpose of the RC resistors is to protect the
CP and CN pins from transient voltages and destructive
currents. Internally, these pins have clamp diodes to VCC
and VEE rated for a maximum of 1.0 A under surge conditions only (Figure 32). The 1.0 kQ resistors shown in the
figures, for example, will provide protection against surges
up to 1.0 kV. Resistor manufacturers must be consulted for
the proper type of resistor for this environment.
The RC resistors are in series with internal 31 kQ resistors,
and therefore form a voltage divider to the inputs of the
transmit amplifier, as shown in Figure 32. This will affect the
transmit gain, receive gain, return loss, and transhybrid
rejection (described in subsequent sections). The tolerance
of the RC resistors depends on the value selected for them,
since any mismatch between them will create a differential
voltage at CP and CN when longitudinal voltages are present
on Tip and Ring. To ensure a minimum of 58 dB of longitudinal balance, the resistors' absolute value must not differ by
more than 39 Q. With a nominal value of 1.0 kQ, their
tolerance must be ±2%, or less. If their nominal value is 390 Q
or less, their tolerance can be ±5%.
4) Longitudinal Impedance (ZLONG) - Selecting the RS
Resistors
The longitudinal impedance is determined by the RS
resistors at the TSI and RSI pins according to the following
equation:
ZLONG = RS + 100
51

(Equation 4)

ZLONG is defined as VLONG/ILONG as shown in Figure 33; for RS = 9.1 kQ, ZLONG = 180 Q. The calculated
value of ZLONG includes the fact that the RS resistors are
in parallel with the synthesized impedance. The tolerance
of the RS resistors therefore depends on how much mismatch can be tolerated between the longitudinal impedances
at Tip and at Ring. Calculations indicate the two RS resistors

MC33120
2-247

can have a ±5% tolerance, and still comfortably provide a
minimum of 58 dB longitudinal balance.
The resistors must be able to withstand transient voltages
expected at Tip and Ring. The TSI and RSI pins have internal

FIGURE 33 -

clamp diodes rated for a maximum of 1.0 A under surge
conditions only (Figure 33). Resistor manufacturers must be
consulted for the proper type of resistor for this environment.

LONGITUDINAL IMPEDANCE

RS

Common
Mode
Detector
&
Amplifier

RS

~

'T-=

RING

VLONG

Buffer

EN
' - - - - - - - " 7V'FE-"-lEI

MC33120

-48 V o---J.....' - - - - - - - - = : = . . j___________________ ...J

AC

5) AC Terminating Impedance and Source Impedance (ZaGl
- Return Loss
The return loss measurement is a measure of how closely
the AC impedance of the SLiC circuit matches the characteristic impedance of the phone line, or a reference impedance.
The reference impedance can be, in some cases, a pure
resistance (commonly 600 Q or 900 Q), a series resistor and
capacitor (900 Q + 2.16 (IF), or a more complex network.

FIGURE 34 -

VCC

RC 1.0k Cp

r

To achieve proper return loss with the MC33120, the RRO
impedance shown in Figure 34 is to have the same configuration as the reference impedance, but with values scaled
according to the equations mentioned below.
CRO, used primarily for DC blocking, is generally a large
value (1.0 (IF) so as to not affect the impedance of RRO.
However, it can be included in the RRO network if a complex
network is required.

AC TERMINATING IMPEDANCE

r-------------------...,
I
I
I

3t k

TSf

-=

RSf

AC

I
I
BN I

RC t.Ok CN

iI
2

IL ___________________
To VEE
MC33120 I
~

MC33120
2-248

IA =IRXI

MOTOROLA COMMUNICATIONS DEVICE DATA

Zac is the impedance looking into the circuit from Tip and
Ring (set by RRO), and is defined as VL/IL. Half of Zac is
from Tip to VCC, and the other half is from Ring to VaB (an
AC ground). Each half is made up of a synthesized impedance (ZT/2) in parallel with RS and (RC + 31 k).
Therefore Zac is equal to:
Zac = [ZT/2 IIRSII(RC + 31 k)] • 2

same as the complex load, but with all impedance values
increased according to the scaling factor of Equation 9.
[(RC + 31 k)IIRS] • 1.037. 10 6
.
SF = (RC + 31 k) • [(RC + 31 k)IIRS _ (Zac /2 )] (Equation 9)
Zac is computed at a nominal frequency of interest. A first
order approximation of Equation 9 is:

(Equation 5)

SF = 1.037 • 106/(RC + 31 k)
and ~ = {RSII(RC + 31 k)} • (Zac/2 )
2
{RSII(RC + 31 k)} - (Zac/2)

For example:

(Equation 6)

If the AC load is:

The synthesized impedance ZT is created as follows:
An incoming Signal VL produces a differential voltage at
CP and CN, and therefore at TXO equal to:
V

_ VL' 31 k. 0.328
TXO (RC + 31 k)

(Equation 9a)

IfL-.
;}~ ~c:J
~

Then RRO should be:

To TIP.
and Ring

(Equation 7)

R~~l
From

31.15k (RRO)

.........:r 62 nF (CRO)

TXO

The signal at TXO creates an AC current IRXI through
RRO. RXI is a virtual ground, and CRO is insignificant for
first order calculations.
IRXI is gained up by a factor of 102 to produce the current
IT through the transistors.
ZT is therefore VL/IT. The relationship between ZT and
RRO is:
_ ZT' 1.037.10 6
RRO (31 k + RC)

If the AC load is:

Then RRO should be:

820~J
220

0,115
~F

To Tip
and Ring

R~~~
3.3 nF

From

TXO

(Equation 8)

28,4 k
7,61 k

---l

CRO

CRO must remain in series with the network to provide
DC blocking, If the load network does not include a series
capacitor (as in the second example above), CRO should
be large (1.0 ~F) so its impedance does not affect the RRO
network. The above procedure will yield a return loss measurement which is constant with respect to frequency, The
RRO resistor, or network, must have a tolerance equal to
or better than the required system tolerance for return loss
and receive gain.

While equation 8 gives the exact value for RRO, a first order
approximation is Zac • 33.5.
a) Resistive Loads (withRC = 1.0 k, RS = 9.1 k):
For a 600 n resistive system, ZT calculates to 626 n,
and RRO calculates to 20.3 kn.
For a 900 n resistive system, ZT calculates to 961 n,
and RRO calculates to 31.14 kn.
b) Complex Loads
For complex (non-resistive) loads, the MC33120 must be
made to look like a termination impedance equal to that
complex load. This is accomplished by configuring RRO the

6) Receive Gain (GRX)
The receive gain involves the same circuit as Figure 34,
but with the addition of the RRX resistor (or network) which
sets the receive gain. See Figure 35,

RECEIVE GAIN

FIGURE 35 -

EP
BP

CP

- t
IRXI

TSI
MC33120

RXI

RSI

RRX
VRX

RRO

CN

ITXO

BN

TXO

EN

MOTOROLA COMMUNICATIONS DEVICE DATA

MC33120
2-249

The receive gain (GRX), defined as the voltage gain from
VRX to VL, is calculated as follows:
RXI is a virtual ground, and Rac is the AC impedance of
the load (phone line).
The AC current generated in the transistors is 102 olRXIo
which is equal to 102 ° (IR - ITXO)'
IR = VRX/RRX, and
ITXO = VTXO = VL ° 31 k ° 0.328
RRO
RRO ° (31 k + RC)

(Equation 10)

The preceeding procedure will yield a receive gain which is
constant with respect to frequency. The RRX resistor, or
network, must have a tolerance equal to or better than the
required system tolerance for receive gain.
7) Transmit Gain (GTX)
Setting the transmit gain involves selecting RTX1 and
RTX2 in Figure 28. The voltage gain from VL to VTX is
calculated from the following:
RTX2
RTX1

Using equations 5 and 8, involving Zac, RS and RC, and
the above equations yields:
VL

102 ° (RacllZad

VRX

RRX

- - = GRX =

Therefore, RRX =

(Equation 11)

102 ° (RacllZad

(Equation 12)

GRX

Equation 12 applies only for the case where Rac and Zac
have the same configuration. If they also have the same
magnitude, then set RRX = 51 ° Rac to set a receive gain
of 0 dB. The AC source impedance of the above circuit to
Zac, use
Tip and Ring is Zac. For the case where Rac
the following equation:
VL
102
(Equation 13)
VRX =
1.037 ° 106
]
R X [1
R ° ZL + (31 k + RC) ° RRO

'*

where ZL =

[R~c II RS II (RC + 31 k)] ° 2

(Equation 14)

a) Resistive Loads
For a 600 Q resistive system, set RRX = 30.6 kQ, and for
a 900 Q resistive system, set RRX = 45.9 kQ.
b) Complex Loads
For complex (non-resistive) loads, the RRX resistor needs
to be replaced with a network having the same configuration
as the complex load, but with all impedance values scaled
up by a factor of 51 (for 0 dB gain). If a gain other than 0
dB is desired, the scaling factor is determined from Equation
12. This methods applies only if the RRO network has been
made complex comparable to the load according to the
procedure in the previous section (Equations 5-9a) , such that
Rac = Zac· Using a scaling factor of 51, and the previous
examples, yields:
If the AC load is:

Then RRX should be:

L.J

r-I

I~ 2.16 ~~

~~

--------

To TiP.

~R~

If the AC load is:

MC33120
2-250

~~25nF

;
;
To Tip
TO~VRX
and Ring RXI
I 11.2k 41.8k
I

J

(Equation 15)

For 0 dB gain, set RTX2 = 3.15 x RTX1 (for RC = 1.0 k).
The actual values of RTX2 and RTX1 are not critical- only
their ratio so as to provide the proper gain at the op amp.
Once the ratio is established, the two resistors can be
selected from a set of standard resistor values. The minimum
value for RTX1 is limited by the drive capability of TXO, which
is a nominal ±800 IJA peak (±2751JA minimum). As a general
rule, RTX1 should be between 6.0 kQ and 20 kQ. The load
on TXO is the parallel combination of RTX1 and RRO.
CTX is for DC blocking, and is typically a large value
(1.0 IlF) so as to not be a significant impedance. In general,
it should not be used for low frequency rolloff as that will
affect the transhybrid rejection (discussed in the next section). Low frequency roll off should be done after the op amp.
High frequency rolloff can be set by placing a capaCitor
across RTX2.
For complex loads (at Tip and Ring), if RRO and RRX have
been made complex comparable to the load as described
in the previous sections, neither RTX1 nor RTX2 needs to
be complex since both the transmit and receive signals which
appear at TXO will be flat with respect to frequency.
RTX1 and RTX2 must have a tolerance equal to or better
than the required system tolerance for the transmit gain.
8) Balance Network (RS) - Transhybrid Rejection
When a receive signal is applied to VRX to produce a
signal at Tip and Ring, the two-to-four wire arrangement of
a hybrid (the MC33120) results in a reflected signal at TXO.
Transhybrid rejection involves canceling that reflected Signal
before it appears at VTX. The method used is to insert the
RB resistor (or network) as shown in Figure 36. The current
IB' supplied form VRX, cancels the current ITX1 supplied
from TXO (Node A is a virtual ground). Good transhybrid
cancellation requires that the currents be equal in magnitude
and 1800 out of phase at node A.
Using the equations for transmit and receive gains, the
current ITX1 is equal to:
335
(Equation 16)
I
_
. ° VRX ° Zac ° ZL ° 31 k
TX1 - RRX ° [Zac + ZLI ° RTX1 ° (RC + 31 k)

_______ _

Then RRX should be:

820 Ei·115 ~F
220

TO~~VRX
RXI
I 45.9 k
42 nF I

° 31 k ° 0.328
° (RC + 31 k)

a) For the case where RRO and RRX are comparable in
configuration to ZL:
Since IS = VRX/RB, then RB can be determined from:
RB=

RRX ° RTX1 ° (RC + 31 k)
33.5 ° [ZaclIZLlo 31 k

(Equation 17)

MOTOROLA COMMUNICATIONS DEVICE DATA

FIGURE 36 TIP

BALANCE RESISTOR

r-----------..,
=

I RXI
I
I
I

..!Ex
RRX
RTX1

--

TXO

I
RING

I

Equation 17 provides a value for an RB resistor which will
provide the correct magnitude for lB' The correct phase
relationship is provided by the fact that the signal at TXO
is out of phase with that at VRX. The phase relationship will
be 180 0 only if RRO and RRX are of a configuration identical
to that of the load. This applies regardless of whether the
load, ZL, (and RRO and RRX) are purely resistive or of a
complex nature. Equation 17 reduces to a non-complex
resistance if RRX, Zac, and ZL are all comparably complex.
For the case where Zac = ZL, RRX = 51 • Zac, and
RC = 1.0 k, Equation 17 reduces to:
RB = 3.15. RTX1

1m

~~:!~ ____ ~L.:~~J

(Equation 18)

b) For the case where Zac and ZL do not have the same
frequency characteristics:
For the case where, for reasons of cost andlor simplicity,
the load (RL) is considered resistive (whereas in reality it
is not a pure resistance) and therefore resistors, rather than
networks, were selected for RRO and RRX, using a simple
resistor for RB may not provide sufficient transhybrid rejection due to a phase angle difference between VRX and TXO.
The terminating impedance may therefore not necessarily
be matched exactly to the line impedance, but the resulting
circuit still provides sufficiently correct performance for receive gain, transmit gain, and return loss. The rejection can
be improved in this case by replacing RB with the configuration shown in Figure 37. Even on a very short phone line
there is a reactive component to the load due to the two
compensation capacitors (CC, Figure 4) at the transistor
collectors. The two capacitors can be considered in series
with each other, and across the load as shown in Figure 37.
To simplify the explanation, the current source and Zac of
Figure 36 are replaced with the Thevenin voltage source and
series Zac. Since ZL and Zac are not matched, there will
FIGURE 37 -

vRX

IB~

RTX2

RB

VTX

0

be a phase shift from VRX to the signal across Tip and Ring.
This phase shift is also present at TXO. The same phase
shift is generated at node B in the RB network by making
RB1 equal to Zac, and ZL equal to the load. RB2 is then
calculated from:
RRX. RTX1 • (RC + 31 k)
RB2=
(Equation 19)
33.5 • Zac • 31 k
For example, for a system where the load is considered a
600 il resistor (RRO = 20.3 kil, RRX = 30.6 kil, RTX1 =
10 kil, and RC = 1.0 kil), RB1 would be a 600 il resistor,
ZL (in the RB network) would be a 600 il resistor in parallel
with a 0.005 flF capacitor, and RB2 calculates to 15.715 kil.
The RB resistor, or network, must have a tolerance equal
to or better than the required system tolerance for trans hybrid
rejection.
9} Logic Interface
The logic circuit (output ST1, and the 1/0 labeled ST2/PDI)
is depicted in Figure 30, and functions according to the truth
table in Table 1.
a} Output Characteristics
ST1 is a traditional NPN pull-down with a 15 kil pull-up
resistor. Figures 19 and 20 indicate its output characteristics.
ST2 is configured with the following items: a} a 1.0 mA
current source for a pull-down which is active only when ST2
is internally set low; b) an 800 IJ.A current source pull-up
which is active only when ST2 is internally set high; c) a
positive feedback aspect within this output circuit which
provides considerable hysteresis for stability reasons. Its
output characteristics are shown in Figures 21 and 22. Due
to this configuration, any external pull-up resistance which
is applied to this pin must be greater than 15 kil, or the output
may not reliably switch from high to low. Any external
pull-down resistance does not affect this output's ability to

BALANCE NETWORK

.--+--~~r---------~----~VRX

RRX
RTX1
ITX1

-----,
RB1

1RB
1

1
=1

RB2
1
_ _ _ _ _ .J

,..-"V\I\r.., RTX2
:>-----VTX

MOTOROLA COMMUNICATIONS DEVICE DATA

MC33120
2·251

switch from low-to-high, but does affect the maximum longitudinal currents which can be accepted by the circuit (see
the section on Longitudinal Current capability). The capacitor
(CT) is required to provide a time delay, for stability reasons,
during transitions between off-hook and on-hook. This capacitor additionally affects maximum longitudinal currents, as
well as stability during pulse dialing (explained below).

line as it would cycle between a power-up and power-down
condition with each dialing pulse.
d) Fault Detection
Faults are defined as excessive leakage from Tip to VEE
and/or ground, and from Ring to VEE and/or ground. A single
fault is anyone of the above conditions, while a double ,fault
is defined as excessive leakage from Tip to VEE and from
Ring to VCC, as depicted in Figure 38. Refer to Figures 11-15
for the resistance, RLK, which will cause the MC33120 to
switch to a power-down condition. If the leakage resistance
is less than that indicated in the graphs, the MC33120 will
power-down itself and the two external transistors, thereby
protecting them from overheating. Both status outputs (ST1
and ST2) will be at a logic low, indicating a fault condition.
A fault condition is detected by monitoring an imbalance in
the magnitudes of the currents at TSI and RSI, and/or a
polarity reversal at Tip and Ring.
The,MC33120 will detect the following conditions:
1) When on-hook (see Figure 11):
a) <2.0 kQ between Ring and VCC, with no hysteresis
at this threshold, or
b) <2.5 kQ between Tip and VEE, with no hysteresis at
this threshold, or
c) Both a and b simultaneously.
Leakage from Tip to VCC and/or Ring to VEE are not
detected as faults while the MC33120 is on-hook.
2) When off-hook (600 Q between Tip and Ring):
a) <500 Q between Tip and VCC, or
b) <600 Q between Tip and VEE, or
c) <500 Q between Ring and VEE, or
d) <600 Q between Ring and VCC, or
e) Both band d simultaneously
A simultaneous occurrence of conditions a) and c) is not
detected as a fault. See Figures 12-15 for the threshold
variation with RL. Resetting of the fault detection circuit
requires that the leakage resistance be increased to a value
between 10 kQ and 20 kn, depending on VEE, RL, and RS'
Both ST1 and ST2 should be monitored for hookswitch status
to preclude not detecting a fault condition.
Figure 15 indicates the variation in fault thresholds for
Tip-to-VCC and Ring-to-Battery faults, and is valid only for
loop resistances of 200 Q to 1,0 kQ. On loops larger than

b) Hook Status
The MC33120 uses the sense currents at CP and CN to
activate the hook status circuit. The sensing is configured
such that the circuit monitors the impedance across Tip/Ring,
which results in the hookswitch thresholds being virtually
independent of the battery voltage. The off-hook to on-hook
threshold is affected by the choice of RRF according to the
graph of Figure 8, but is not affected by the value of RS.
The on-hook to off-hook threshold is affected by the value
of RS according to the graph of Figure 9, but is not affected
by RRF. Varying the RC resistors does not affect the thresholds significantly.
When the telephone is on-hook (ST1 = Hi, ST2 = Low),
the MC33120 is internally powered down, the external transistors are shut off, and power consumption is at a minimum.
Upon closure of the phone's hookswitch, ST1 will switch low
within 10 Ils. ST2 will then change state slowly due to the
external capacitor (CT = 5.0 IlF). There is a =8.0 millisecond
delay for ST2 to reach the threshold necessary to activate
the internal bias circuit, which in turn activates the external
drive transistors to supply loop current. This delay is necessary to prevent instabilities during the transition to off-hook.
Upon opening the telephone's hookswitch, ST1 will switch
high within =200 Ils. ST2 then requires =60 ms to reach the
threshold to switch off the internal bias circuit, which in turn
shuts down the external drive transistors.
c) Pulse Dialing
During pulse dialing, ST1 will change state concurrent with
the hookswitch. ST2 is kept from switching during pulse
dialing by the external capacitor (CT), which keeps the
MC33120 in a powered up condition and stable. If the CT
capacitor is too small, the voltage at ST2 could droop to the
POI threshold (see section e below) during each pulse. This
could cause the MC33120 to create additional noise on the

ON·HOOK

n

Vee

r------,
MC33120

I
I
I

ST1

I-}

I
lI
I
I
I
I
I
v~-----.J

=

FIGURE 38 -

FAULT DETECTION

OFF·HOOK

n

Vee

r------,
MC33120

I

ST1

0

ST2

I

I-}

I
lI
I
I
I
I

V;t------.J

n r------,I
Vee

MC33120

r2K

I
I

ST2

MC33120
2-252

OFF·HOOK

I
I

ST1

=0

ST2

I

I-}

I
lI
I
I
I
I

=0

V;t------.J

MOTOROLA COMMUNICATIONS DEVICE DATA

1.0 kil, the MC33120 does not reliably indicate the fault
condition at ST1 and ST2, but may indicate on-hook status
instead. This does not apply to Tip-to-Battery and
Ring-to-VCC faults which are correctly detected for lines
beyond 1.0 kil.

e) POI Input
The ST2 output can also be used as an input (POI input)
to power down the circuit, denying loop current to the
subscriber (by shutting off the external pass transistors),
regardless of the hookswitch position. Powering down is
accomplished by pulling POI to a logic low with an open
collector output, or an NPN transistor as shown in Figure
30. The switching threshold is ~+ 1.5 V. The current out of
POI, when pulled low, is ~800 1lA. Releasing POI allows the
MC33120 to resume normal operation.
If the external telephone is off-hook while the MC33120
is powered down, sense currents at CP and TSI will result
in some loop current flowing through the loop and back into
CN and RSI. This current is generally on the order of 1.0
to 3.0 mA, determined primarily by the RS resistors, loop
resistance, and VEE. ST1 will continue to indicate the telephone's actual hook status while POI is held low. The
on-to-off hook threshold is the same as that during normal
operation, but the off-to-on hook threshold is >250 kil.
When powered down with the POI pin, the receive gain
(VRXI to Tip/Ring) is muted by >90 dB, and the transmit gain
(Tip/Ring to TXO) is muted by >30 dB.

Power Dissipation, Calculation and Considerations
a) Reliability
The maximum power dissipated by the MC33120 must be
considered, and managed, so as to not exceed the junction
temperature listed in the Absolute Maximum Ratings. Exceeding this temperature on a recurring basis will reduce long
term reliability, and possibly degrade performance. The junction temperature also affects the statistical lifetime of the
device, due to long term thermal effects within the package.
Today's plastic integrated circuit packages are as reliable as
ceramic packages under most environmental conditions.
However, when the ultimate in system reliability is required,
thermal managements must be considered as a prime system design goal.
Modern plastic package assembly technology utilizes gold
wire bonded to aluminum bonding pads throughout the
electronics industry. When exposed to high temperatures for
protracted periods of time an intermetallic compound can
form in the bond area resulting in high impedance contacts
and degradation of device performance. Since the formation
of intermetallic compounds is directly related to device junction temperature, it is incumbent on the designer to determine
that the device junction temperature is consistent with system
reliability goals.
Based on the results of almost ten years of +125°C
operating life testing, Table 2 has been derived indicating the
relationship between junction temperature and time to 0.1 %
wire bond failure.

MOTOROLA COMMUNICATIONS DEVICE DATA

TABLE 2 - STATISTICAL L1FETtME
Junction
Temperature (0C)

Time
(Hours)

Time
(Years)

80
90
100
110
120
130
140

1,032,200
419,300
178,700
79,600
37,000
17,800
8,900

117.8
47.9
20.4
9.4
4.2
2.0
1.0

Motorola MEeL DeVice Data. OL 122

The "time" in Table 2 refers to the time the device is operating
at that junction temperature. Since the MC33120 is at a low
power condition (nominally 68 mW) when on-hook, the duty
cycle must be considered. For example, if a statistical duty
cycle of 20% off-hook time is used, operation at 130°C
junction temperature (when off-hook) would result in a statistical lifetime of ~1 0 years.
b) Power and Junction Temperature Calculation
The power within the IC is calculated by subtracting the
power dissipated in the two wire side (the transistors and
the load) from the power delivered to the IC by the power
supplies. Refer to Figure 4 and 27.
Po ~ IVoo • 1001 + IVEE • IEEI- {ILOOP • IVEP - VEND
(Equation 20)
The terms VEP and VEN are the OC voltages, with respect
to ground, at the EP and EN pins. These voltages can be
measured, or can be approximated by:
VEP ~ - {3~ il • lLOOP)
VEN ~ VEE + 2.1 V + (ILOOP' 35 il)
Refer to Figure 23. The junction temperature is then calculated from:
(Equation 21)
where T A is the ambient air temperature at the IC package,
and 8JA is the junction-to-ambient thermal resistance shown
in Figure 39. The highest junction temperature will occur at
maximum VEE and VOO, maximum loop current, and maximum ambient temperature.
If the above calculations indicate the junction temperature
will exceed the maximum specified, then it is necessary to
reduce the maximum loop current, ambient temperature,
and/or VEE supply voltage. Air flow should not be restricted
near the IC by tall components or other objects since even
a small amount of air flow can substantially reduce junction
temperature. For example, typically an air flow of 300 LFPM
(3.5 mph) can reduce the effective 8JA by 14 to 20% from
that which occurs in still air. Additionally, providing as much
copper area as possible at the IC pins will assist in drawing
away heat from within the IC package. For additional information on this subject, refer to the "Thermal Considerations"
section of Motorola MECL System Design Handbook
(HB205), and the "System Oesign Considerations" section
of Motorola MECL Device Data (0L122).

MC33120
2-253

TABLE 3 - TRANSISTOR POWER DURING A FAULT

FIGURE 39 - THERMAL RESISTANCE
(JUNCTION TO AMBIENT)

70

60

r........ t'-..

"'- ~

~o

iii 50

Still air, soldered
10 a G-l0 PC Board

:----.. r-....

'"

f"".

"-

40

30
25

35

65

75

"

85

Selecting the Transistors
The specifications for the two loop current pass transistors
involve their current gain, voltage rating, and power dissipation capabilities at the highest ambient temperatures. Power
dissipation during both normal operation and faults must be
considered when determining worst case situations. Generally, more power is dissipated during a fault condition than
during normal operation.
The transistors' minimum beta is recommended to be 40
at the loop currents involved in the application. A lower beta
could degrade gain and balance performance. Maximum
beta should be less than 500 to prevent possible oscillations.
Darlington type transistors should not be used. The voltage
rating should be a minimum of 80 V, although the choice of
protection scheme may require a higher rating.
Referring to Figure 27, during normal operation the loop
current and the voltage across the transistors are both at
a maximum when the load impedance (RU is at a minimum.
The loop current is determined by RRF and the graphs of
Figures 5-7. The voltage across each transistor is determined from the following:

VT=

iVEEi- 2.1 - [(65 + 2RP + RL) • ILOOP]
--==-______
-=-_=-::..c=.:....:
2

(Equation 22)

The power in each transistor is then (VT • ILOOP)' The
voltage across the two transistors will always be nearly equal
during normal operation, resulting in equal power dissipation.
The graph of Figure 24 indicates the power dissipated in each
transistor where RP = 100 n.
During a fault condition, depicted in Figure 38, if the
leakage resistance from Tip to VEE or from Ring to VCC
is less than that shown in Figures 12-14 (when off-hook),
the MC33120 will power down the transistors to protect them
from overheating. Should the leakage resistance be slightly
higher than that shown in the graphs, however, and the fault
detection has not been activated, the power in one transistor
(in a single fault, both transistors in a double fault) will be
higher than normal. The power will depend on VEE, RL, RP
and the leakage resistance. Table 3 is a guide of the power
in the transistor dissipating the higher power level.

MC33120
2-254

VEE

RS

RL

PPNP

PNPN

-58
-48
-58
-48
-58
-48
-58
-58

9.1 k
9.1 k
9.1 k
9.1 k
9.1 k
9.1 k
5.1 k
11 k

200
200
600
600
1.0 k
1.0 k
200
200

1.64
1.05
1.37
0.746
0.897
0.232
1.8
1.53

1.34
0.957
1.11
0.616
0.68
0.194
1.55
1.3

The power (in watts) in the two right columns indicates the
power dissipated by that transistor if it is carrying the maximum fault current. The system designer should attempt to
predict possible fault conditions for the system, and then
measure the conditions on the transistors during the worse
case fault(s).
For most applications involving a nominal VEE of - 48 V
(with a maximum of - 58 V), a maximum loop current of 30
to 40 mA, and a maximum TA of +85°C, the MJD243 and
MJD253 DPAK transistors are recommended. When
mounted as described in their data sheet, they will handle
both the normal loop current as well as most fault conditions.
If faults are not expected to occur in a particular application,
then smaller package transistors, such as MPS6717 and
MPS6729, may be used. Each application must be evaluated
individually when selecting the transistors.
Other possible transistors which can be considered:
PNP
MJD253-1
MJE253
MJD32
MJD42
MJD350
TIP30A,B,C

NPN
MJD243-1
MJE243
MJD31
MJD41
MJD340
TIP29A,B,C

Longitudinal Current Capability
The maximum longitudinal current which can be handled
without distortion is a function of loop current. battery feed
resistance, the longitudinal impedance, and the components
on ST2.
Since the pass transistors cannot pass current in the
reverse direction, the DC loop current provides one upper
boundary for the peak longitudinal current plus peak speech
signal current. The battery feed resistance determines, in
effect, the DC voltage across the transistors, which is a
measure of the headroom available for the circuit to handle
the peak longitudinal voltage plus peak speech signal voltage. The longitudinal impedance, determined by the RS
resistors (equation 4), determines the longitudinal current for
a given longitudinal voltage.
While analysis of the above items may yield one value of
maximum longitudinal current, a different limit (which may
be higher or lower) is imposed by the capacitor CT, and any
pulldown resistance RT, on Pin 12 (ST2). This is due to the
fact that the sense currents at TSland RSI will be alternately
mismatched as Tip and Ring move up and down together
in the presence of longitudinal signals. When the longitudinals are strong, the internal fault detect circuit is activated
with each 1/2 cycle, which attempts to switch ST2 low (see
the section on Fault Detection). The speed at which ST2 can

MOTOROLA COMMUNICATIONS DEVICE DATA

switch low is a function of both the external capacitor, CT
and any pulldown resistance, RT.
The graphs of Figures 25 and 26 indicate the maximum
longitudinal current which can be handled (in Tip and in Ring)
without distortion or causing ST2 to switch low.
PC Board Layout Considerations
PC board considerations include thermal, RFIIEMI, transient conditions, interconnection of the four wire side to the
codec/filter, and others. Wirewrapped boards should be
avoided - breadboarding should be done on a (at least)
reasonably neat PC board.
a) Thermal
Power dissipated by the MC33120 and the two transistors
must be removed to prevent excessively high junction temperatures. The equations for calculating junction temperatures are mentioned elsewhere in this data sheet. Heat is
removed by both air flow and copper foil on the PC board.
Since even a small amount of air flow substantially reduces
junction temperatures compared to still air, tall components
or other objects should not be placed such that they block
air flow across the heat generating devices. Increasing,
wherever possible, the area of the copper foil at the IC pins
will provide additional heat removal capability. A ground plane
can generally help here, while at the same time helping to
reduces RFI problems.
b) RFI/EMI
While the MC33120 is intended for use at audio frequencies, the internal amplifiers have bandwidths in excess of

FtGURE 40 -

~

1.0 MHz, and can therefore respond to externally induced
RFI and EM!. Interference signals can come in on the phone
line, or be radiated on to the PC board from nearby radio
stations or from high frequency circuitry (digital & microprocessor circuitry) in the vicinity of the line card.
Usually RFI entering from the phone line at Tip and Ring
can be removed by the compensation capacitors (Ccl provided they are connected to a good. quality RF ground
(generally the same ground which connects to VCC on the
MC33120). The ground track should be as wide and as direct
as possible to minimize lead inductance. Generally better
results can be obtained if an RF bleedoff to earth (or chassis)
ground can be provided where the twisted pair phone line
comes into the system.
To minimize problems due to noise radiating directly onto
the PC board from nearby high frequency circuitry, all components associated with the MC33120 should be physically as
close as possible to the IC. The most sensitive pins in this
respect are the CP, CN, RSI, TSI, VAG and RXI pins. Keeping
the tracks short minimizes their "antenna" effect.
c) Transient Conditions
When transient voltages come in to Tip and Ring, the
transient currents, which can be several amperes, must be
carried by the ground line (Vccl and/or the VEE line. These
tracks, along with the protection and clamping devices, must
be designed for these currents at the frequencies involved.
If the tracks are narrow, not only may they be destroyed by
the high currents, but their inductance can allow the voltage
at the IC, and other nearby components, to rise to damaging
levels.

PROTECTION DIODES

r---------------------,

~~V

MC33120

CP
To Digital
Ground
TSI

VAG

To Analog

~ Ground

RSI

RXI

14V

TXO

eN

RFO
BN

All zener diodes are 7.0 V, except
where noted.

14V

VB

I
VEE L _____________________
9.0V
JI

MC33120
2-255

MOTOROLA COMMUNICATIONS DEVICE DATA

------,._------------

ponents on the +5.0 V line if their grounds have a direct
connection at the line card. The MC33120 is designed to
allow VCC to move as much as ±30 V with respect to VOG
and VAG on a transient basis only. VCC and the other
grounds should preferably be connected together at the
power supply rather than at the IC. Internally, the MC33120
has clamp diodes on the 4-wire side pins as shown in Figure
40.
If the codec has a single ground pin, as in Figure 41, it
will be the reference for both the digital and analog Signals,
and must be connected to both VAG and VOG on the
MC33120. If the codec has separate digital and analog
grounds, as in Figure 42 (the MC145503 internally generates
the analog ground), then each ground should be connected
to the appropriate ground on the MC33120.

The protection circuits shown in Figure 4, and in other
figures in this data sheet, are such that the bulk of the
transient energy is dissipated by external components (the
protection resistors and the clamp diodes). The MC33120
has internal diodes to limit voltage excursions on the pins,
and to pass a small amount of the transient current typically less than 1.0 ampere peak. The arrangement of the
diodes is shown in Figure 40.
d) Interconnection of the four-wire side
The connections on the four-wire side to the codec and
other digital circuitry involves keeping digital noise out of the
speech paths, and also ensuring that potentially destructive
transients on Tip and Ring do not get through to the +5.0 V
system.
Basically, digital connections to STI and ST2 should be
referenced to the VOO and VOG pins, while the transmit and
receive analog signals should be referenced to the analog
ground (VAG)' VCC should be connected to a clean battery
ground, and generally should not be connected directly to
VOG and/or VAG (on the line card) when strong transients
are anticipated. Even with a good layout, VCC can move
several volts when a transient hits, possibly damaging comFIGURE 41 -

e) Other
A 0.1 ~F capacitor should be provided across VCC to VEE
on the MC33120 to help keep idle channel noise to a
minimum.
The COB capacitor (on the VOB pin) forms a pole with
an internal 7.5 kQ resistor to filter noise from the VEE pin,

CONNECTION TO A CO DEC WITH A SINGLE GROUND

, . - - - - - - - - - - - - - - - - - - - - - - Battery Ground
, . - - - - - - - - - - - - - . - Digital Ground
+5.0V

,.-----------+---

......._ - - - -5.0 V
M
C

3
3
1
2

o

----------'===.=;=====:::...- Battery Supply

'---...,o"'.t-ll-.....

FIGURE 42 -

CONNECTION TO A CODEC WITH SEPARATE GROUNDS

, . - - - - - - - - - - - - - - - - - - - - - - BatteryGround
, . - - - - - - - - - - - - . . . , . . - . Digital Ground

r-_=-=-==-=---=-==-=--=_+-::-:--+5.0 V
r,----------, 0.1

1-1~-_ ___l--
a.

30

.........

()

o
o

-' 20 - - RS=9.1 k -VEE = -48 V
TA = 25"C
10
400

r--.... r-....

RRFl =43kQ
RRF2 = 820 Q

I I
800
1200
LOOP RESISTANCE (Q)

1600

FIGURE 45 - ALTERNATE PROTECTION SCHEME

RFO

The LM385-1.2 is a precIsion temperature stable zener
diode. As the load impedance at Tip and Ring is reduced,
the voltage at RFO goes increasingly negative. When the
zener diode is turned on, the current into RXI is then clamped
at a value determined by RRFI and the zener diode. To
calculate the two resistors, use the following procedure:
RRFI must be >0.7 • (RRFI + RRF2);
Determine RRFI to set the current limit on a short line by
using the following equation:
102 • 1.23 V
ILOOP (MAX) - 3.0 mA

MC33120

(Equation 23)

9100Q
RP

Then using Equation 1 calculate RRF for the long line
current. RRF2 is then determined by;
RRF2 = RRF - RRFI

2000

b) Protection Scheme
The protection circuit shown in Figure 45 has the advantage of drawing z90% of the transient current frorn ground
(VCe) on a negative transient, rather than from the VEE line
as the circuit of Figure 4 does. The majority of the transient
current flows through the RP resistors and the Mosorbs while
a small arnount (zl 0%) flows through the sense resistors and
the CP, CN, RSI pins. On a positive transient, all the current
(except at RSI) is directed to ground. The diode in the NPN's
collector prevents reverse current through the base-collector
junction of the transistor during a negative transient.

RRF2

RRFI =

-

r--

(Equation 24)

Figure 44 illustrates one example using the above circuit.
Comparing this graph to the 5100 n curve of Figure 6 shows
a substantial decrease in the current lirnit (at RL = 0),
resulting in reduced power consumption and dissipation. Use

MOTOROLA COMMUNICATIONS DEVICE DATA

1.0kQ

0.01
100V

-48v----~~~-4~14~V~

VEE L
All zener diodes are 7.0 V except as noled.

_________ _

MC33120
2·257

CIRCUIT PERFORMANCE
The following three circuits are presented as typical application examples, and the accompanying graphs indicate their
measured performance. The first circuit (Figure 46) has a
600 n pure resistance as the AC load. The second circuit
(Figures 47) has as an AC load a 900 n resistor in series
with a 2.16 I1F capacitor. The third circuit (Figure 48) has

as an AC load, a complex network composed of an 820 n
resistor in parallel with 0.115 I1F, and those in series with a
220 n resistor. In the graphs of Figures 49-51, FiL = Return
Loss, THR = Transhybrid Rejection, GTX = Transmit Gain,
GRX = Receive Gain.

FIGURE 46 - 600 a SYSTEM
20

VCC

....--0

VDD 1-'1,;,,5

+5.0 V

0.1

100

ST2IPDlI-'I~2+--_-_ _-ST2IPDI

19

EP

MJD253 18

BP

5.011F
ST11-1""3+_ _

CP

VDG 1-1;,,;, 4........--..---'

0.01

1.0k,2%

17

+-___ STI

1-_--L_ _.....9.""1",k_ _ _1:.::...j6 TSI
RAC
6000
1 - -......- - ' \ f I / v - - - - ' 4 RSI
9.1 k
I....A,fI/v--~CN

RXI ~....--__t--'V'IIIr__.------- Receive
In (VRX)
RFO

F=--=-tBN
300
CF I-'---'\M---,

'------=-t EN
Q - -.......---'-i

VEE

-48 V

vaB 6

20

FIGURE 47 - 900 a + 2.1611F SYSTEM

9.1 k

*

1.011F

~

IOI1F

VDD 1-1:,:.5-,-_0 +5.0 V

20

VCC

19

EP

MJD253 18

BP

ST11-1:.::
3

17

CP

VDG 1-1:..;4--6---1_...J

0.1
ST2IPDll-l""2+--....--_ _-ST2IPDI

+ __+ ____-

STI

16

I - -......--....,..rv---:.::...j TSI
1---.---'\fI/v----"-i RSI
9.1 k

'-'\fI/v _ _ _4:; CN

F';";;";;;"""";:; BN

RXI ~....--_r_'\M...---I ....- - - - - -.... Receive
In (VRX)
31.6k
RFO

7

31.6k

62nF____'\M-~~
~OI-'I,;"I--

1. I1F

. 2 EN

0---+--':; VEE

-48 V

MC33120
2-258

300
CF I-!--"'VI.--....

Vae 6

~

20

~

~

TransmH
Out (VTX)

1.011F

IOI1F

MOTOROLA COMMUNICATIONS DEVICE DATA

FIGURE 48 - 220 n + 820 ill/0.115

20

VCC

VOO

~F

15

-=
19
MJ0253 18

100

1.0k,2%

17

9.1k

16

820

EP

POI

BP

STI

CP

VOG

'"
M
M

220

9.1k

ST2IPOI

13

STI

14

11.2k

u

RXI

:a

RSI

12

+5.0 V
0.1

VAG

0

TSI

SYSTEM

31.6 k

CN

. r-

RFO

Receive
In (VRX)

31.6k

MJ0243

BN

TXO
10 k

300
EN

CF

~

20
-48 V

VQB

VEE

.

1.0~F

+

'Out
moo""
(VTX)

10~F

=f0.l
=f

FIGURE 49 -

CIRCUIT PERFO,RMANCE, 600 n SYSTEM

90

RL

70
iii'
;;

FIGURE 50 - CIRCUIT PERFORMANCE
900 n + 2.16 ~F SYSTEM

-

50

~~V'

0
iii'

~ 30

50

~

V

TH~

""

........

ill,,,:rIHfISfmI
L1JJffilITRI
~
::>

ffl

r:r::

30

.---"--- '--

-0.1 100

c:::J:.:
I

~
::>

~

ffl

r:r::

V'

20

~

'--

1.0 k

t, FREQUENCY (Hz)

MOTOROLA COMMUNICATIONS DEVICE DATA

10 k

L-

"

C--'--

~
1.0k
10k

-0.2 100

t, FREQUENCY (Hz)

MC33120
2-259

FIGURE 52 - RETURN LOSS TEST CIRCUIT
FOR FIGURES 46 TO 51

FIGURE 51 - CIRCUIT PERFORMANCE
820 nt/0.1151'F + 220 n SYSTEM

80
60

V
--

'\
MC33120

Circuit
~II
""'
L..-----....--CH (Figures 46,

~ l"- i-

I- I-f0

/"

47 or 48)

'--

R

~tlJJl¥ffi IIIIII
o

I

G~

1.0k

-0.2 100

I

Relerence Network = RAC of Figures 46 to 48.
Return Loss = 20 log VA + VB
VA-VB

10 k

f, FREQUENCY (Hz)

GLOSSARY
ATTENUATION - A decrease in magnitude of a communication Signal, usually expressed in dB.
BALANCE NETWORK - That part of the SUC circuit which
provides transhybrid rejection.
BANDWIDTH - The range of information carrying frequencies of a communication system.
BATTERY - The voltage which provides the loop current, and
in some cases powers the SUC circuit. The name derives from
the fact that COs have always used batteries, in conjunction
with AC power, to provide this voltage.
BATTERY FEED RESISTANCE - The equivalent Thevenin
DC resistance of the SUC circuit for supplying loop current.
Traditionally it is 400 O.
C-MESSAGE FILTER - A frequency weighting which
evaluates the effects of noise on a typical subscriber's system.
CENTRAL OFFICE - Abbreviated CO, it is a main telephone
office, usually within a few miles of its subscribers, that houses
switching gear for interconnection within its exchange area,
and to the rest of the telephone system. A typical CO can
handle up to 10,000 subscriber numbers.

dBm - An indication of signal power. 1.0 mW across 600 0,
or 0.775 V rms, is defined as dBm. Any other voltage level
is converted to dBm by:

a

dBm = 20 -log (Vrms/0.775), or
dBm = [20 - log (Vrms)] + 2.22.
dBmp -Indicates dBm measurement using a psophometric
weighting filter.
dBrn - Indicates a dBm measurement relative to 1.0 pW
power level into 600 O. Generally used for noise measurements, 0 dBrn = ...gO dBm.
dBrnC -Indicates a dBrn measurement using a C-message
weighting filter.
DTMF - Dual Tone Multifrequency. It is the '10ne dialing"
system based on outputting two non-harmonic related frequencies simultaneously to identify the number dialed. Eight
frequencies have been assigned to the four rows and four
columns of a keypad.
FAULT - An incorrect condition where TIp is accidentally
connected to the battery voltage, or Ring is connected to
ground, or both. The most common fault is Ring to ground.

CODEC - Coder!Decoder - Interfacing between the SUC
and the digital switch, it converts the SUC's transmit signal to
digital, and converts the digital receive signal to analog.

FOUR WIRE CIRCUIT - The portion of a telephone, or
central office, which operates on two pairs of wires. One pair
is for the transmit path, and one pair is for the receive path.

dB - A power or voltage measurement unit, referred to
another power or voltage. It is generally computed as:

FULL DUPLEX - A transmission system which permits
communication in both directions simultaneously. The standard handset telephone system is full duplex.

10 -log (PI! P2)
for power measurements, and
20 -log (VI! V2)
for voltage measurements.

MC33120
2·260

GAIN - The change in Signal amplitude (increase or
decrease) after passing through an amplifier, or other circuit
stage. Usually expressed in dB, an increase is a positive
number, and a decrease is a negative number.

MOTOROLA COMMUNICATIONS DEVICE DATA

HALF DUPLEX - A transmission system which permits
communication in one direction at a time. CB radios, with
"push-to-talk" switches, and voice activated speakerphones,
are half duplex.
HOOKSWITCH - A switch, within the telephone, which
connects the telephone circuit to the subscriber loop. The
name derives from old telephones where the switch was
activated by lifting the receiver off and onto a hook on the side
of the phone.
HYBRID -

Another name for a two-to-four wire converter.

IDLE CHANNEL NOISE - Residual background noise when
transmit and receive signals are absent.
LINE CARD - The PC board and circuitry in the CO or PBX
which connects to the subscriber's phone line. A line card may
hold circuitry for one subscriber, or a number of subscribers.
LONGITUDINAL BALANCE - The ability of the SUC to
reject longitudinal signals on Tip and Ring.
LONGITUDINAL SIGNALS -

Common mode signals.

LOOP - The loop formed by the two subscriber wires (Tip and
Ring) connected to the telephone at one end, and the central
office (or PBX) at the other end. Generally, it is a floating
system not referred to ground, or AC power.
LOOP CURRENT - The DC current which flows through the
subscriber loop. It is typically provided by the central office or
PBX, and ranges from 20 to 120 mAo
OFF HOOK - The condition when the telephone is connected
to the phone system, permitting the loop current to flow. The
central office detects the DC current as an indication that the
phone is busy.
ON HOOK - The condition when the telephone is disconnected from the phone system, and no DC loop current flows.
The central office regards an on-hook phone as available for
ringing.
PABX - Private Automatic Branch Exchange. In effect, a
miniature central office, it is a customer owned switching
system servicing the phones within a facility, such as an office
building. A portion of the PABX connects to the Bell (or other
local) telephone system.
PROTECTION, PRIMARY - Usually consisting of carbon
blocks or gas discharge tubes, it absorbs the bulk of a lightning
induced transient by clamping the voltages to less than
±1500V.
PROTECTION, SECONDARY - Usually located on the line
card, it protects the SUC and associated circuits from
transient surges. Typically, it must be capable of clamping a
±1.5 kV surge of 1.0 ms duration.
PULSE DIALING - A dialing system whereby the loop
current is interrupted a number of times in quick succession.
The number of interruptions corresponds to the number
dialed, and the interruption rate is typically 10 per second. The
old rotary phones, and many new pushbutton phones, use
pulse dialing.

MOTOROLA COMMUNICATIONS DEVICE DATA

RECEIVE PATH - Within the CO or PBX it is the speech path
from the internal switching system towards the phone line (Tip
& Ring).
REN - Ringer Equivalence Number. An indication of the
impedance or loading factor of a telephone bell or ringer
circuit. An REN of 1.0 equals =8.0 kn. The Bell system
typically permits a maximum of 5.0 REN (1.6 kQ) on an
individual subscriber line. A minimum REN of 0.2 (40 kn) is
required by the Bell system.
RETURN LOSS - Expressed in dB, it is a measure of how
well the SUC's AC impedance matches the line's AC
characteristic impedance. With a perfect match, there is no
reflected signal, and therefore infinite return loss. It is
calculated from:
RL = 20 • log (ZUNE + ZCKT)
(ZUNE - ZCKT)

RING - One of the two wires connecting the central office to
a telephone. The name derives from the ring portion of the
plugs used by operators (in older eqUipment) to make the
connection. Ring is traditionally negative with respect to Tip.
SLIC - Subscriber Line Interface Circuit. It is the circuitry
within the CO or PBX which connects to the user's phone line.
SUBSCRIBER line.

The customer at the telephone end of the

SUBSCRIBER LINE - The system consisting of the user's
telephone, the interconnecting wires, and the central office
equipment dedicated to that subscriber (also referred to as a
loop).
TIP - One of the two wires connecitng the central office to a
telephone. The name derives from the tip of the plugs used by
operators (in older equipment) to make the connection. Tip is
traditionally positive with respect to Ring.
TRANSHYBRID REJECTION - The rejection (in dB) of the
reflected signal in the transmit path resulting from a receive
signal applied to the SUC.
TRANSMIT PATH - Within the CO or PBX it is the speech
path from the phone line (Tip & Ring) towards the internal
switching system.
TWO WIRE CIRCUIT - Refers to the two wires connecting
the central office to the subscriber's telephone. Commonly
referred to as Tip and Ring, the two wires carry both transmit
and receive signals in a differential manner.
TWO-TO-FOUR WIRE CONVERTER - A circuit which has
four wires (on one side) - two (signal & ground) for the
outgoing signal, and two for the incoming signal. The outgoing
signal is sent out differentially on the two wire side (the other
side), and incoming differential signals received on the two
wire side are directed to the four wire side. Additional circuit
within cancels the reflected outgoing signal to keep it separate
from the incoming signal.
VOICEBAND - That portion of the audio frequency range
used for transmission across the telephone system. Typically
it is 300 to 3400 Hz.

MC33120
2-261

_

MOTOROLA

SEMICONDUCTOR

MC33121

TECHNICAL DATA

Low Voltage Subscriber
Loop Interface Circuit

LOW VOLTAGE SUBSCRIBER
LOOP INTERFACE CIRCUIT
(SLIC)

The MC33121 is designed to provide the interface between the 4-wire
side of a central office, or PBX, and the 2-wire subscriber line. Interface
functions include battery feed, proper loop termination AC impedance,
hookswitch detection, adjustable transmit, receive, and transhybrid gains,
and single/double fault indication. Additionally, the MC33121 provides a
minimum of 58 dB of longitudinal balance (4-wire and 2-wire).
The transmit and receive signals are referenced to analog ground, while
digital signals are referenced to digital ground, easing the interface to
codecs, filters, etc. The 2 status outputs (hookswitch and faults) and the
Power Down Input are TTUCMOS compatible. The Power Down Input
permits local shutdown of the circuit.
Internal drivers allow the external loop current pass transistors to be
standard bipolar transistors (non-Darlington).
The MC33121 is available in a 20 pin DIP and a 28 pin PLCC surface
mount package.
• 58 dB Longitudinal Balance Guaranteed; 4-wire and 2-wire
• Transmit, Receive, and Transhybrid Gains Externally Adjustable
• Return Loss Externally Adjustable
• Proper Hookswitch Detection With 30 kQ Leakage
• Single/Double Fault Indication With Shutdown for Thermal Protection
• Critical Sense Resistors Included Internally
• Standard Power Supplies: - 21.6 V to - 42 V, and + 5.0 V, ± 10%
• On-Hook Transmission
• Power Down Input (TTL and CMOS Compatible)
• Operating Ambient Temperature: - 40°C to + 85°C
• Available in a 20 Pin DIP and 28 Pin PLCC Package

THIN FILM
SILICON MONOLITHIC
INTEGRATED CIRCUIT

-

PSUFFIX
PLASTIC PACKAGE
CASE 738

1

FN SUFFIX
PLCC
CASE 776

ORDERING INFORMATION
Temperature
Range

Device
MC33121P
MC33121FN

- 40° to + 85°C

Package
Plastic DIP
PLCC

SIMPLIFIED BLOCK DIAGRAM
VCC~
EP

~
Tip

DL

f

BP
CP
TSI

~*

>4
.J...

I

EN

I

rt

I
Current
Mirror

~*

/I
~

VEE
(Battery)
* Indicates Trimmed Resistor

VDD (+S.OV)
VDG
(Dig. Gnd)

I

-

r-a..

J

1

.J{

*

II

Current
Mirror

PDI/ST2

I

J

~
_

Ir

~~_ ~ ~l

~

;xJ~
~CN
BN

MC33121
2-262

Hook Status and I
Fau~ Detection

I

Current
Mirror

~

I

"*

T Vcc

I

I
...

~

Ring

I

~

VEE

RSI

0 1

Current
Mirror

Current
Mirror

I

II
~

[

Current
Mirror

Bias

~

I

>-- STl
VAG
(Ana. Gnd)
RXI
TXO

RFO
CF
VaB
MC33121

MOTOROLA COMMUNICATIONS DEVICE DATA

. ...
~

-

.

MAXIMUM RATINGS
Characteristic
Supply Voltage
(with respect to VCC)
(with respect to VOG)

Symbol

Value

VEE
VOO

- 60, +0.5
- 0.5, +7.0

Unit
Vdc

Voltage
@ POI, (with respect to VOG)
@ CP,CN
EP, TSI
BP
RSI, EN
BN

Vdc

Vin
-0.5, +7.0
VEE - 0.5, VCC +0.5
VCC -7.0, VCC +0.5
VCC - 14, VCC +0.5
VEE - 0.5, VEE +14
VEE - 1.0, VEE +21

Junction Temperature

TJ

150

'c

Storage Temperature

Tstg

-65to+150

'C

Devices should not be operated at these limits. The ~Recommended Operating Conditions" tab!e provides for actual device operation.

RECOMMENDED OPERATING CONDITIONS
Characteristic

Symbol

Min

Typ

Max

VEE
VOO

-42
+4.5

-24
+5.0

-21.6
+5.5

(with respect to VCC)
(with respect to VCC)
(with respect to VAG)

VAG
VOG

-3.0
-3.0
-3.0

0
0
0

+10
+7.0
+10

(with respect to VEE)
(with respect to VCC and VAG)

VOO

-

47.5

Supply Voltage
(with respect to VCC)
(with respect to VOG)

Unit
Vdc

3.5

-

IL

15

-

50

rnA

POt Input Voltage

VpOI

0

-

VOO

Vdc

Sink Current
STI
ST2

IST1L
tST2L

0
0

-

1.0
1.0

Transmit Signal Level at Tip & Ring
Receive Signal Level at VRX

STX
SRX

-48
-48

-

+3.0
+3.0

dBm

RL

0
0

-

2.0 k
800

n

Loop Current

Loop Resistance

-

rnA

VEE=-42V
VEE=-24V

External Transistor Beta

Hie

40

-

500

AlA

Operating Ambient Temperature (See text lor derating)

TA

-40

-

+85

'c

IEEN
IEEF

-2.7
-72

lOON
IOOF

AlIlimils are not necessarily functional concurrently.

POWER SUPPLIES
VEE Current
On Hook (RL > 10 Mn, VEE = -42 V)
Off Hook (RL = 0 n, VEE = - 42 V)'
VOO Current
On Hook (RL > 10 Mn, VOO = +5.5 V)
Off Hook (RL = 0 n, VOO = +5.5 V)
VEE Ripple Rejection
1= 1.0 kHz, @ VTX (4-wire)
1= 1.0 kHz, @ Tip/Ring (2-wire)
VOO Ripple Rejection
1= 1.0 kHz, @ VTX (4-wire)
1= 1.0 kHz, @ Tip/Ring (2-wire)

rnA

-

-1.0
-55

-41

4.0

1.4
7.0

2.7
14

40
40

62
52

-

37
37

52
48

-

-

dB

PSRR

*Includes loop current.

MOTOROLA COMMUNICATIONS DEVICE DATA

MC33121
2-263

Characteristic
LOOP FUNCTIONS
mA

Loop Current
Maximum (RRF = 4.7 k, RL = 10 Q)
Nominal (RRF = 4.7 k, RL = 367 Q)
Minimum (RRF = 4.7 k, RL = 796 Q)
Battery Feed Resistance (RRF

= 4.7 k, RL = 796 Qr

IL(max)
IL
lL(min)

37
21
16

41
27
17.5

-

RBF

475

575

675

51
34
Q

ill

Hookswitch Threshold
On-to-Off Hook
Off-to-On Hook

RNF
RFN

2.0

Fault Detection Threshold
Ring-to-Ground (RL = 367 Q)
Tip-to-Battery (RL = 367 Q)

RRG
RTB

GTX1

4.1
7.7

-

600
600

1100
1100

-

-

0.328

-

-

10
Q

·Calculated from [(24/IL(min)) - 796]

GAIN LEVELS
Transmit Voltage Gain (CP, CN to TXO)

-

0
0
0
±0.1

-

0.05

-

GRX1

94

102

110

GRX2

-0.3
-0.1
-0.15

0.3
0.1
0.15

-

0
0
0
±0.1

-

0.05

-

RL

30

>40

-

dB

THR

-

44

-

dB

58
58

64
64

-

dB

58
58

64
64

-

53
53

60
60

-

-

62
62

-

THDT

Receive Current Gain (lEP/IRX;)
Receive Voltage Gain (VUVRXI) (RL = 600 Q)
VRXI = 0 dBm, f = 1.0 kHz
VRXI = 0 dBm, f = 3.4 kHz, with respect to GRX2
VRXI = +3.0 dBm, f = 1.0 kHz, with respect to GRX2
VRXI = - 48 dBm, f = 1.0 kHz, with respect to GRX2

= 600 Q resistive, f = 1.0 kHz)
= 600 Q resistive, f = 1.0 kHz,

0.3
0.1
0.15
-

%
mA/mA
dB

Receive Distortion
(f = 300 Hz to 4.0 kHz, - 40 dBm ,; VRXI ,; +5.0 dBm)
Return Loss (Reference

-0.3
-0.1
-0.15

GTX2

Transmit Distortion (at Pin 11)
(f = 300 Hz to 4.0 kHz, - 40 dBm ,; VT-R ,; +5.0 dBm)

Transhybrid Rejection (RL

VIV
dB

Transmit Voltage Gain (VTXIVU
VL = 0 dBm, f = 1.0 kHz
VL = 0 dBm, f = 3.4 kHz, with respect to GTX2
VL = +3.0 dBm, f = 1.0 kHz, with respect to GTX2
VI = - 48 dBm, f = 1.0 kHz, with respect to GTX2

THOR

Figure 4)

%

LONGITUDINAL SIGNALS (VCM = 1.0 Vrms, see Figures 1 and 2)
2-Wire Balance, f = 1.0 kHz, Zac
4-Wire Balance, f = 1.0 kHz, Zac

= ,600 Q (@ Tip/Ring)
= 600 Q (@ VTX)
2-Wire Balance, f = 330 Hz, Zac = 600 Q (@ Tip/Ring)
4-Wire Balance, f = 330 Hz, Zac = 600 Q (@ VTX)
= 600 Q (@ Tip/Ring)
= 600 Q (@ VTX)
2-Wire Balance, f = 1.0 kHz, Zac = 900 Q (@ Tip/Ring)
4-Wire Balance, f = 1.0 kHz, Zac = 900 Q (@ VTX)
Signal Balance, f = 1.0 kHz (Figure 3)
Longitudinal Impedance, RS = 9100 Q

LB

2-Wire Balance, f = 3.3 kHz, Zac
4-Wire Balance, f = 3.3 kHz, Zac

Maximum Longitudinal Current, per side
f = 1.0 kHz, ILoop = IL(rnin), CT = 0.1 ~F
VEE =- 42, VCM = 5.12 Vrrns

MC33121
2-264

ZLong

-

-

40

55

-

150

180

210

Q

rnA

ILong(max)
8.5

16

-

MOTOROLA COMMUNICATIONS DEVICE DATA

ELECTRICAL CHARACTERISTICS (VEE= - 24 V, VDD= +5.0 V, unless otherwise noted. VCC=VAG=VDG= 0 V, TA= 25'C, see Figure 1.)

I

I

Characteristic

Symbol

I

Min

I

Typ

I

Max

I

Unit

I

LOGIC INTERFACE
ST1 Output Voltage
Low (IST1 = 1.0 mA, VDD = 5.5 V)
High (IST1 = - 100 ~A, VDD = 4.5 V)

VOL
VOH

VDG
2.4

0.17
3.2

0.4

Vdc

ST2 Output Voltage
Low (IST2 = 1.0 mA, VDD = 5.5 V)
High (IST2 = - 100 ~A, VDD = 4.5 V)

VOL
VOH

VDG
2.4

0.17
4.3

0.4

lime Delay
Hookswitch Closure to ST1 Change
Hookswitch Opening to ST1 Change

tST11
tST12

-

10
200

-

19

-

Hookswitch Closure to 90% of Loop Current (CT = 0.1 ~F)
PDI Taken High-to-Low to 10% of Loop Current
PDI Taken Low-to-High to 90% of Loop Current

tHS
tST21
tST22

PDllnput Current
VPDI = 3.0 V, RL = 367 n, VDD = 5.0 V
VPDI = 0 V, RL = 367 n, VDD = 5.5 V

-

1B
10

-

-1250

VIL
VIH

ms
ms
~s

~A

IIH

PDllnput Voltage
Low
High

~s

-

VDG
2.0

-BOO
-BOO

-

-300

Vdc
O.B
VDD

MISCELLANEOUS
Vas Voltage (Vas - VEE)
@IL=20mA
@IL=40mA

Vas

0.B2
0.95

VTXO

-400

+30

ITXO

±275

±BOO

-

~Apk

VRXOS

-

O.B

-

mVdc

0.2

-

-

TXO Offset Voltage (VTXO - VAG) @ RL = 600

n

TXO Output Current
RXI Offset Voltage (VRXI- VAG) @ RL = 600 n
VAG Input Current@ RL = 600

Vdc

-

n

Idle Channel Noise (with C-message filter, RL = 600
@TXO(Pin 11)
@lip/Ring

IVAG

-

+400

n)

Thermal Resistance - Junction to Ambient
(Either package, in still air, soldered to a PC board)

MOTOROLA COMMUNICATIONS DEVICE DATA

mVdc

~A

dSrnc
NIC4
NIC2
8JA
(@ TA = +25'C)
(@TA=+B5'C)

-

-10
-5.0

-

-

62
36

-

'CIW
-

-

MC33121
2-265

Figure 1. Test Circuit
20

IEP

rr=

19

~

r

VL

-

RP

RC

IL

17

1.0 k
9.1 k

Tip

16

VCC

BP

STI

CP

VOG

TSI

L

13

STI

14

VAG
RRX

RSI

RXI

CN

RFO

BN

TXO

EN

CF

Receive
In (VRXil

RC

RP

1

PDl/ST2
CT
0.1

MC33121

9.1k
1.0 k

01

+5.0V

12

ST2/PDI

EP

RS
RS

RL

15

VOO

I

11

301

Components shown for a 600 Q system.
Three grounds are connected directly together.

VaB

VEE

20

-24V

:;J::

Figure 2. Longitudinal Balance Test
(Per IEEE·455)

MC33121 Test

Circuit (Figure 1)

4·Wire Balance = 20 Oog V
0

30

RS=9.1 k
VEE = -42 V

RS=9.1 k
VEE = -28 V
TA=25'C
10 0
200

LT~A~=_25~'~C~__~~~~__~~~~~~__~.

10 0

400

800
1200
RL. LOOP RESISTANCE (n)

1600

2000

Figure 7. Loop Current versus Loop
Resistance and RRF
50

15

~

9
o

VEE:>-24 V
5.1 k:>RS:>ll k
4.5 V:> VOO :>5.5 V
TA = 25'C

13

a: 11

F
w

a:
a:
::> 30

/""'

~
~ 9.0
en

0

a.
0

9

g;
9

7.0
5.0

100~~--~2=00~-L--7.40~0--~~6=00~-L--=OO~0--~-1~000

./

3.0

4.0

./

5.0

6.0
7.0
RRF(kn)

RL. LOOP RESISTANCE (n)

Figure 9. On-Hook to Off-Hook Threshold versus RS

~
4.0

~

F

~ 3.0

~
en

a.

2.0

.,/

VEE =

V

/

/

L
/"

~

l

-2",Y ,/

~,/

IZ
W

........ ........----

-42V:>VEE:>-24V
TA = 25'C
Voo= +5.0V
RRF = 4700 n

0

~ 10

....co

VVEE=-42V

""a:w
z

I-

~

C

9
7.0
8.0
9.0
10
RS. SENSE RESISTANCE (kn)

MOTOROLA COMMUNICATIONS DEVICE DATA

10

a:
a:

V

6.0

9.0

::>

I-

E
1.0
5.0

8.0

Figure 10. 100 versus Loop Current
15

~

:I:

iiia:

/

/

/

iiia:

.:3' 20 10 k

~

./

ffl

!i<
w

3.9 k,;; RRF,;; 10k
I- 4.5 V,;;Voo:> 5.5 V
TA = 25'C

1000

V

:I:

§.

5.0

800

Figure 8. Off-Hook to On-Hook
Threshold versus RRF

RS=9.1 k
VEE = -24 V
TA = 25'C

4700

400
600
RL. LOOP RESISTANCE (n)

11

12

5.0
20

-

30
IL. LOOP CURRENT (rnA)

l-

40

45

MC33121
2-269

Figure 12. Fault Threshold (Off-Hook)
versus Loop Resistance·

Figure 11. Fault Threshold (On-Hook) versus RS
4.0

~

9a

:c
en
w
a:

~ l

2.5

=>

2.0

V

---- -- --

:s

a:

~

---

1.5
1.0

~

~

~

Lt

--

5.0

~

../
TiP-tol-VEE
VEE~ -24 V . /
TIp-to-VEE
VEE ~ -42 V

3.0

f=

3.0

I

I- TA 25 C
3.5 I- RL ~ Open

~

9a

:c
en
w
a:
:c

...... V

Ring-to-Ground

I-

VEE~~

----Ring-to-Ground _
VEE ~ -42 V

I
I

7.0
9.0
RS, SENSE RESISTANCE (kQ)

~

=>

Lt

'"
...J

a:

2.4

~

2.4

500

a
:c

en
w
a:
:c

I-

~

1.S

RS=11k~

1.2

=>

:s

/::;;

0.6

200

'i

--

./""

Lt
a:

----------......-

...............

9.1 k

7.5 k

400
600
RL, LOOP RESISTANCE (Q)

9a

---5.1k

~

a:

~

=>

1.2

0.6

...J

0.6

o

SOO

~

0.4

f\.

'"

a:

=-:::.... ::.---

0.2

o

5.0

MC33121
2-270

VEE~2V

../

>-

l....--::::

--;;;-o-GrOund
-24 V SVi=E 5 -42 V

7.0
9.0
RS, SENSE RESISTANCE (kQ)

"""7.5k

l----I - o

200

V-

~~

- f-- ~.1k

400

600

SOO

Figure 16. VOO Ripple Rejection versus Frequency

------Ring-to-VEE VEE = -24 V

:::------

9.1k

RL, LOOP RESISTANCE (Q)

TA ~ 25'C
200Q< RL 

~

Lt

'"

----

......- V

RS=11k~

w

f=

a:

Ring-to-VEE

:c
en
w
a:
:c

2000

1000
1500
RL, LOOP RESISTANCE (Q)

a
:c 1.S
en

Figure 15. Fault Threshold (Off-Hook) versus RS

~

/"
5.1k

VEE ~ -24 V
TA = 25'C
Ring-to-Ground
and/or Tip-to-VEE

2.4

9

1.0

O.S

./'"
7.5 k

Figure 14. Fault Threshold (Off-Hook)
versus Loop Resistance
3.0

9

Vs.1k

-

11

VEE ~ -2S V
TA ~ 25'C
Ring-to-Ground
and/or TIp-to-VEE

V

/ V
V/
I
../
1.S
/ //
I
// /
1.2 -RS~~
/L
/
./
.
/
'
/
V
0.6
,... V
L

Figure 13. Fault Threshold (Off-Hook)
versus Loop Resistance
3.0

. /V / V

VEE ~ -42 V
TA ~ 25'C
Ring-to-Ground
and/or TIp-to-VEE

11

mill

:Eo

~

TA~25'C_

4-Wrr~

iIi

z

VEE ~ -24 V
20 rnA 5 ILS40 rnA

........
60

u

2-Wire

w

Ul
a:

~

~

~

c.
c. 40

c:

:......'"

r-.........

20
0.02

0.1

1.0

10

20

t, FREQUENCY (kHz)

MOTOROLA COMMUNICATIONS DEVICE DATA

Figure 18. VEE Ripple Rejection
versus Frequency and COB

Figure 17. VEE Ripple Rejection versus Frequency
80

80

10
:3-

z

0

10

z

~i'2--

(3

- --

w

a:
~

:3-

~

60

Ul
00-

VEE = -24 V
TA = 25°C
20 mA ,; iLOOP ,; 40 mA

40

il:

0

r-...
V2-Wire

(3
.........

r-

~

Ul

i'---

il:

~

-- -- - ./'"
-- vI- ---~

40 ./"'

/"

10

1.0

20
1.0

20

10
20
COB, CAPACITOR (J.lF)

Figure 20. ST1, VOH versus IOH

Figure 19. ST1, VOL versus IOL

~
w

(!l

~
0

I-

0.3

>

--

0-

I-

::>
0

..:.

0.2

V-

0

>

~
w 5.0

~
........... .......... Voo = +5.5 V

(!l

0.4

::>

6.0

,1_

4.5 V ,; Voo ,; 5.5 V
TA =25°C

0.5

0.1

~

.....,.......

0

>

I-

::>

~

0I-

4.0

~

...............

::>
0

:i:

~

1.0
IOL, OUTPUT CURRENT (mA)

1.5

2.0

o

~
w

~

I

::>
0

4.5 V,; Voo ';5.5 V
TA = 25°C

0.2

>

-200

Voo =5.5 V

~ 5.0
w

(!l

~
~ 4.0

0I-

..:.
0

-150

Figure 22. ST2, VOH versus IOH

o

0.3

I-

r----..........

r--...

6.0

,~

0.4

::>

-100

r--....

IOH, OUTPUT CURRENT (J.lA)

0

>

...........
-50

Figure 21. ST2, VOL versus IOL

(!l

...........

...............

:f? 3.0

2.0
0.5

0.6
0.5

~

Voo = +4.;v-.. ..........

TA = 25°C

o
o

1.0 kHZ}
300 Hz
2-wire
4.0 kHz

...........

t, FREOUENCY (kHz)

.1

1.0 kHZ}
300 Hz
4-wire
4.0 kHz

;/

0.1

0.6

L

i--"

./"'

a:

00-

l---::

7"

w

VEE = -24 V
TA = 25°C
20 mA,; IL';40 mA
COB = 10 J.lF

20
0.02

60

-

~r-

0.1

V

o

O'

I-- Voo - 4.5 V

~

o

~ 3.0
>

TA =25°C

~
2.0
0.25

0.50

0.75

IOL, OUTPUT CURRENT (mA)

MOTOROLA COMMUNICATIONS DEVICE DATA

1.0

o

-100

-200

-300

-400

-500

IOH, OUTPUT CURRENT (J.lA)

MC33121
2-271

Figure 23. IC Power Dissipation versus
Loop Resistance and RRF

~ 0.4

0.7
~

0.6

0.5
22
c
a:
w 0.4

r--

s:0

RRF = 6200

" ""-

I -t--

0..

0.3 I - - :-"" RRF=IOk

I

0.2

o

---

r-..
t::--

en

...~ 0.3 ~

200
400
Rlo LOOP RESISTANCE (0)

~

~.2k

i!: 0.2

z
o

::----

'"'~\

10k'"'"-

~

en

-=

600

VEE=-2BV
TA = 25°C
Rp=IOOO

1'222

....... ,RRF=39oo

if
CiS

Q

a:

VEE = -2B V
TA = 25°C
Voo= +5.0 V

..............

z

Q

Figure 24. Transistor Power Dissipation
versus Loop Resistance and RRF

BOO

~ 0.1

~

0

Figure 25. Maximum Longitudinal Current
versus Loop Current

~

~ ::::::-

RRF=3.;;-

o

--

200
400
Rlo LOOP RESISTANCE (0)

~

20

-::::-I---r-

RS =llk

--

MC33121
2-272

~
!t
w

_l-- ~ l--

a:
a:

800

At
~

RS=9.1 k

I

Rr= 200 k
12 '=I.OkHz
.;

::::J

VEE=-2BV
TA = 25°C
Cr IL=20mA

--;'::;OOk
'=60Hz

:: 8.0

::l!

-42 V$ VEE $-24 V
, = 60 Hz and 1.0 kHz
Cp 0.1 IlF lor 1.0 kHz
Cp 1.0 IlF lor 60 Hz

30
IL, LOOP CURRENT (rnA)

ST2

~ 16

__ r-

--t:::- ~ ,..-

600

Figure 26. Maximum Longitudinal Current
versus CT. RT and Frequency

1
RS=5.1 k

f-

a~

9
40

~

RT=20k
4.0 f=I.OkH~~,-i.RT=20k
'=60Hz
00.1

1.0
Cr(IlF)

10

MOTOROLA COMMUNICATIONS DEVICE DATA

FUNCTIONAL DESCRIPTION
Introduction
The MC33121 is a solid state SLiC (Subscriber Line
Interface Circuit) which provides the interface between the
two wire telephone line and the four wire side of a Central
Office or PBX. Most of the BORSCHT functions are
provided, specifically:

-

Battery feed of the loop current to the line, with programmable maximum current for short lines and battery feed resistance for long lines.
- Overvoltage protection through internal clamp diodes and
external resistors and diodes.
- Supervision, in that hook status is indicated in the presence
of 2:30 kQ leakage, and regardless of whether or not the circuit is powered down intentionally by the Central Office or
PBX. Fault conditions are detected and indicated to the
system. Dialing (pulse and DTMF) information is passed
through the MC33121 to the 4-wire side.
- Hybrid function, in that the MC33121 is a 2-to-4 wire converter. Transmit, receive, return loss, and transhybrid gains
are independently adjustable.
The MC33121 does not provide ring insertion, ring trip,
digital coding/decoding of the speech Signals, nor test functions. These must be provided external to this device.
The MC33121 controls two external transistors (one NPN
and one PNP) through which the loop current flows. By
appropriate circuit design, the power dissipation (which can
exceed 3.0 W under certain worst case conditions) is

approximately equally distributed among the two transistors
and the IC, thereby lowering junction temperatures and
increasing long term reliability. In most situations, heatsinks
will not be required.
The MC33121 incorporates critical sense resistors internally, which are trimmed for optimum performance. With this
technique, the external resistors on the two wire side, which
generally must be high wattage for transient protection
reasons, can be non-precision.
Longitudinal balance is tested to a minimum of 58 dB @
1.0 kHz (refer to Electrical Characteristics and Figure 2) for
both the two-wire and four-wire side, and typically measures
in the mid-60s. The longitudinal current capability is tested
to a minimum of 8.5 mArms per side (refer to Electrical
Characteristics and Figure 2) at a loop current of 20 mAo
Following is a description of the individual sections.
Figure 4 is the reference schematic.
DC Loop Current
The DC loop current is determined by the battery
voltage (VEE), the load resistance across Tip and Ring,
and the resistor at RFO. Varying the 4 resistors RS and
RC will influence the loop current a small amount «5%).
The curves of Figures 5 to 7 indicate the loop current
versus loop resistance, different values of RRF, and for
various values of VEE. The graphs represent performance
at TA = 25°C and after the IC had reached a steady state
temperature (>5 minutes).

Figure 27. DC Loop Current Path

100

rt--i-=- Analog

Ground

Tip

~ IRXI
RRF

I RFO
I
I
I
I
I
I Vas

s.on
-24 V VEE
~=~

-=- 0.8 V
---------------------

MOTOROLA COMMUNICATIONS DEVICE DATA

MC33121
2·273

Figure 27 is representative of the DC loop current path
(bold lines). On a long line (RL > 400 n), the loop current
can be determined from the following equation:
I _ (IVEEI- 3.6 V) • 13
L - RRF + {(RL + 5) .13}

The value of the RC resistors depends on the transient
protection needed, described in another section, with 1.0 kn
resistors being suitable for most applications. The resulting
signal at TXO needs to be gained up to obtain 0 dB from
Tip/Ring to VTX (the 4-wire output). The common method
involves an external op amp, as shown in Figure 28, with
a gain of RTX2/RTX1. The gain from VL to VTX is:

(1)

On short lines (RL < 400 n), the three diodes across the
12.4 k resistor clamp the voltage at RFO, thereby preventing
the RXI current from increasing as the load resistance is
decreased. The maximum loop current is:
I
_ 1.85V.l02 (TA = 25°C)
L(max) RRF

VTX

VL =

RTX2 • 31 k. 0.328
RTX1. (RC + 31 k)

(3)

If a codec/filter is used, many of which include an
internal op amp, a separate op amp is not needed. CTX is
primarily for DC blocking (of the TXO offset), and is
usually large (1.0 IlF) so as to not affect the gain.

(2)

Due to the temperature dependence of a diode's forward
voltage, the maximum loop current will change with temperature by ~ -0.3%/oC.
The battery feed resistance (.1.VTIP/.1.ILl is ~400 n, but
depends on the loop current, VEE, RRF, and is a valid
parameter only on long lines where the current limit is not
in effect. On short lines, the feed resistance is high since
the loop current is clamped at a near constant level. The
AC impedance (Return Loss) however, is not determined nor
affected by the DC parameters. See the Applications Section
for Return Loss information.

Receive Path
The receive path, shown in Figure 29, consists of the input
at RXI, the transistor driver amplifiers, the external transistors, and the load at Tip/Ring.
RXI is a virtual ground (DC level = VAG) and is a current
input. Current flow is out of the pin. The RXI current is
mirrored to the two transistor drivers which provide a gain
of 102. The two external transistors are then two current
sources, in series, operating at the same value. An additional
internal circuit (not shown) balances the two current sources
to maintain operation in their linear region.
The load current (through RLl is slightly different from the
transistor current due to the sense resistors RC and RS. The
sense resistors add to the DC loop current, but subtract from
the AC load current.
In normal operation, the current at RXI is composed of
a DC current (from RFO), an AC current (from VRX) which
is the receive signal, and an AC current from TXO, which
is the feedback Signal to set the return loss (setting the return
loss is discussed in the section on AC Terminating Impedance). The resulting AC signal at Tip is inverted from that
at VRX, while the Signal at Ring is in phase with VRX.
The resistors RP are for transient protection, and their
value (defined in another section) depends on the amount
of protection required. A nominal value of 100 n is suitable
for most applications.
The system receive gain, from VRX to Tip/Ring, is not
described in this section since in normal applications, it
involves the feedback which sets the AC terminating impedance. The Applications Section discusses these in detail.

Transmit Path
The transmit path, shown in Figure 28, consists of an
internal amplifier which has inputs at CP and CN, and its
output at TXO. The gain is internally fixed at 0.328 V/V
(-9.7 dB). The output is in phase with the signal at CP
(normally the same as TIP), and is out of phase with the
signal at CN. The signal at TXO is also out of phase
with that at VRX, the receive signal input, described in
another section.
The TXO output can swing ~3.0 Vp-p, with a nominal
current capability of ±800 ~ peak (±275 IlA minimum). The
load on TXO is the parallel combination of RTXl and the
RRO network (described later). TXO is nominally internally
biased at the VAG DC level, but has an offset which varies
with loop current.
In normal applications, the signal at CP/CN is reduced
slightly from that at Tip/Ring by the voltage divider composed
of the external RC resistors, and the internal 31 k resistors.

Figure 28. Transmit Path

RC

, - - - - - - - - - - - , VAG
CP 117
31 k
91--'-=----.----,
I
AC Voo
I

1.0 k

CN I 4

1.0 k

I
Ring

MC33121
2-274

RC

111

>-A-V~=~ITh~o-J~Rn~l~
V

0.328

I
31 k -= AC
OB
I
L
I ___________
MC33121_ :

~--Vn

Rn2
Note: Op amp may be part
of a codec/filter.

MOTOROLA COMMUNICATIONS DEVICE DATA

Logic Interface (Hook status, pulse dialing, faults)
The logic interface section provides hookswitch status,
fault information, and pulse dialing information to the 4-wire
side of the system at the ST1 and ST2 outputs. Figure 30
is a representative diagram.
The logic outputs operate according to the truth table in
Table 1:
Table 1. Status Output Truth Table
Hook
Status
On-Hook
Off-Hook
On-Hook
Off-Hook

Fault
Detection
No Fault
No Fault
Fault
Fault

Outputs
ST
1

ST2

Hi

La

La
La
La

Hi
La
La

Circuit Condition
Internally powered down
Powered up
Internally powered down
Internally powered down

Referring to Figure 3D, ST1 is configured as an active NPN
pulldown with a 15 kQ pullup resistor. ST2 has a 800 flA

current source pull up, and a 1.0 mA current source for a
pulldown. Current limiting this output controls the discharge
from the external capacitor when ST2 switches low.
The condition where both ST1 and ST2 are high is not
valid, but may occur momentarily during an off-hook to
on-hook transition. The condition where both ST1 and ST2
are low may occur momentarily during an on-hook to off-hook
transition - this should not be interpreted as a fault condition. ST1 and ST2 are TTUCMOS compatible and are
powered by the +5.0 V supply (VDD). Refer to the Applications Section for more details.
Power Supplies, Grounds
The MC33121 requires 2 power supplies: battery voltage
between - 21.6 V and - 42 V (VEE), and an auxiliary voltage
between +4.5 V and +5.5 V (VDD).
VEE is nominally - 24 V, with a typical range of - 21.6 V
to - 42 V, and must be referenced to VCC (battery ground).
A 0.1 flF bypass capacitor should be provided between VCC

Figure 29. Receive Path

Figure 30. Logic Interface

r--t--'=--o

+5.0 V

r----,'---<~-=-t_....- _ -

Hook
Switch

Status 2
External
Power Down
Control Input

Fault
Detection

sFault

RS

.......----"'-+-'''-'--_ Status 1

MOTOROLA COMMUNICATIONS DEVICE DATA

MC33121
2-275

and VEE. The VEE current (lEE) is nominally 1.0 mA when
on-hook, 8.0 to 12 mA more than the loop current when
off-hook, and =5.0. mA when off-hook but powered down by
using the PDI pin. Ripple and noise rejection from VEE is
a minimum of 40 dB (with a 10 JlF capacitor at VaB), and
is dependent on the size and quality of the VaB capacitor
(COB) since VaB is the actual internal supply voltage for the
speech amplifiers. The absolute maximum for VEE is - 60 V,
and should not be exceeded by the combination of the
battery voltage, its tolerance, and its ripple.
VDD is normally supplied from the line card's digital
+5.0 V supply, and is referenced to VDG (digital ground).
A 0.1 JlF capacitor should be provided between VDD and
VDG. The VDD current (IDD) is nominally 1.7 mA when
on-hook and between 6.0 and 8.0 mA when off-hook (see
Figure 10). When the MC33121 is intentionally powered
down using the PDI pin, IDD changes by <1.0 mA from
the normal off-hook value.

VAG is the analog ground· for the MC33121, and is the
reference for the speech signals (RXI and TXO). Current flow
is Into the pin, and is typically <0.5 JlA.
Normally, VCC, VDG and VAG are to be at the same DC
level. However, if strong transients are expected at Tip and
Ring, as in a Central Office application, or any application
where the phone line is outdoors, VCC should not be connected directly to VDG and VAG in order to prevent possible
damage to the +5.0 V system. The MC33121 is designed
to tolerate as much as ±30 V between VCC and the other
two grounds on a transient basis only. This feature permits
VCC and the other grounds to be kept separate (on an AC
basis) on the line card by transient suppressors, or to be
connected together farther into the system (at the power
supplies). See the Applications Section on ground arrangements and transient protection for further information on
connecting the MC33121 to the system supplies.

APPLICATIONS INFORMATION
This section contains information on the following topics:
Design Procedure .............................
Power Dissipation Calculations
and Considerations .........................
Selecting the Transistors ......................
Longitudinal Current Capability ................
PC Board Layout Considerations ...............
Alternate Circuit Configurations ................

pg. 15
pg. 22
pg. 23
pg. 23
pg. 23
pg. 26

Design Procedure
This section describes the step-by-step sequence for
designing in the MC33121 SLiC into a typical line card
application for either a PBX or Central Office. The sequence
is important so that each new component value which is
calculated does not affect components previously determined. Figure 4 (Typical Application Circuit) is the reference
circuit for most of this discussion. The recommended sequence (detailed below), consists of establishing the DC
aspects first, and then the AC aspects:
1) Determine the maximum loop current for the shortest line,
select RRF. Power dissipation must be considered here.
2) Select the main protection resistors (RP), and diodes,
based on the expected transient voltages. Transient protection configuration must also be considered here.
3) Select RC based on the expected transient voltages.
4) Select RS based on the desired longitudinal impedance at
Tip and Ring. Transient voltages are also a factor here.
5) Calculate RRO based on the desired AC terminating impedance (return loss).
6) Calculate RRX based on the desired receive gain.
7) Calculate RTX2 and RTXl based on the desired transmit
gain.
8) Calculate the balance resistor (RB), or network, as appropriate for desired transhybrid rejection.
9) Logic Interface
Preliminary
There is a primary AC feedback loop which has its main
sense points at CP and CN (see Figure 34). The loop extends
from there to TXO, through RRO to RXI, through the internal
amplifiers to the transistor drivers, through RP to Tip and

MC33121
2-276

Ring, and through the RCs to CP and CN. Components
within this loop, such as RP, RC, the transistors, and the
compensation capacitors need not be tightly matched to
each other in order to maintain good longitudinal balance.
The tolerance requirements on these components, and
others, are described in subsequent sections. Any components, however, which are placed outside the loop for
additional line card functions, such as test relay contacts,
fuses, resistors in series with Tip and Ring, etc. will affect
longitudinal balance, signal balance, and gains if their
values and mismatch is not carefully considered. The
MC33121 cannot compensate for mismatch among components outside the loop.
The compensation capacitors (0.01 JlF) shown at the
transistor collectors (Figure 4) compensate the transistor
driver amplifiers, providing the required loop stability. The
required tolerance on these capacitors can be determined
from the following guidelines:
• Al 0% mismatch (±5% tolerance) will degrade the longitudinal balance by =1.0 dB on a 60 dB device, and by =3.0 dB
on a 70 dB device.
• A 20% mismatch (±1 0% tolerance) will degrade the longitudinal balance by =3.0 dB on a 60 dB device, and by =6.0 dB
on a 70 dB device.
High quality ceramic capacitors are recommended since they
serve the secondary function of providing a bleedoll path
for RF signals picked up on the phone line. These capacitors
should be connected to a good quality RF ground.
The capacitors used at COB and CF must be low leakage
to obtain proper performance. Leakage at the COB capacitor
will affect the DC loop current characteristics, while leakage
at the CF capacitor will affect the AC gain parameters, and
possibly render the IC inoperative.
1) Maximum Loop Current and Battery Feed Resistance
The maximum loop current (at RL = 0) is determined by
the RRF resistor between RFO and RXI. The current limit
is accomplished by three internal series diodes (see Figure
27) which clamp the voltage across RRF as the loop resistance decreases, thereby limiting the current at RXI. Since
the loop current is 102 x IRXI, the loop current is therefore
clamped. The graphs of Figures 5 to 7 indicate the maximum

MOTOROLA COMMUNICATIONS DEVICE DATA

loop current at an ambient temperature of +25°C, and after
tlie IC has reached thermal equilibrium (approx. to minutes).
Although the maximum loop current is primarily a function of the RRF resistor, it is also affected by ambient
temperature, and slightly by VEE. The ambient temperature
effects are due to the temperature dependence of the
diodes' forward voltage drop, causing the maximum loop
current to change by ~ - 0.3%/oC. Changing VEE affects
the maximum current in that the power dissipation is
changed, thereby changing the die temperature, which
affects the diodes' Voltage.
The maximum loop current is affected slightly «5%) by
the choice of the RS and RC resistors, since the sense
currents through those resistors add to the current supplied
by the transistors.
The battery feed resistance is determined by RRF, and
is not adjustable independently of the current limit. Defined
as Ll.VTIP/Ll.IL, it is ~400 Q, and is a valid parameter only on
long lines where the current limit is not in effect. On short
lines, the feed resistance is high since the loop current is
clamped at a near constant level. The AC impedance (Return
Loss) however, is not determined nor affected by these DC
parameters. Return loss is discussed in another section.
If the application requires that the current limit value
have a low temperature dependence, refer to the section
following this design sequence which describes an
alternate configuration.
2) Main Protection Resistors (RP) and
Transient Currents
The purpose of the protection resistors (RP), along with
the 4 clamp diodes shown in Figure 4, is to absorb the bulk
of the transient energy when transient voltages come in from
the phone line. The resistor value must be selected to limit
the transient current to a value which can be tolerated by
the diodes, while dissipating the energy. The recommended
value shown (100 Q) will limit the current from a 1500 V
transient to 15 A, which can be carried by 1N4002 diodes
under surge conditions. The resistors must be of a type which
can tolerate the high instantaneous energy associated with
transients. Resistor manufacturers should be consulted for
this information.
Referring to Figure 4, a positive transient on either Tip or
Ring, or both, will cause the transient current to be delivered
to Ground. A negative transient will cause the transient
current to come from the VEE supply line. Therefore, the PC
board track supplying VCC and VEE to the MC33121 must
be designed to carry the transient currents as well as the
normal operating currents. Additionally, since a negative
transient will cause a current flow out of the power supply's
negative output, which is opposite to the normal flow of
current, provisions must be made for this reverse current
flow. One suggested method is to place a zener transient
suppressor (1 N6287 for -42 V, 1N6282 for -28 V and -24 V)
across the battery supply pins (VCC to VEE) physically
adjacent to the MC33121. The inductance associated with
PC board tracks and wiring will result in insufficient protection
for the MC33121 if the suppressor is located at the opposite
end of the line card, or at the power supplies.
Transient currents can be reduced by increasing the value
of RP, with an upper limit determined by the DC conditions
on the longest line (highest loop resistance) and minimum
VEE supply voltage. These conditions determine the
minimum DC voltage across the transistors, which must be

MOTOROLA COMMUNICATIONS DEVICE DATA

sufficient to handle the largest AC (transmit and receive)
signals. If too large a value is selected for RP, the AC Signals
will be clipped. It is recommended that each transistor have
no less than one volt (DC) across their collector to emitter.
System AC specifications may require more than this.
Since the RP resistors are within the loop, their tolerance
can be ±5% with no substantial degradation of longitudinal
balance. A ±10% tolerance (20% mismatch) will degrade
balance by ~4.0 dB on a 65 dB device.
Figure 32. RC Protection Resistors

3) Selecting the RC Resistors
The primary purpose of the RC resistors is to protect the
CP and CN pins from transient voltages and destructive
currents. Internally, these pins have clamp diodes to VCC
and VEE rated for a maximum of 1.0 A under surge conditions
only (Figure 32). The 1.0 kQ resistors shown in the figures,
for example, will provide protection against surges up to
1.0 kV. Resistor manufacturers must be consulted for the
proper type of resistor for this environment.
The RC resistors are in series with internal 31 kQ resistors,
and therefore form a voltage divider to the inputs of the
transmit amplifier, as shown in Figure 32. This will affect the
transmit gain, receive gain, return loss, and transhybrid
rejection (described in subsequent sections). The tolerance
of the RC resistors depends on the value selected for them,
since any mismatch between them will create a differential
voltage at CP and CN when longitudinal voltages are present
on Tip and Ring. To ensure a minimum of 58 dB of longitudinal balance, the resistors' absolute value must not differ by
more than 39 Q. With a nominal value of 1.0 kQ, their
tolerance must be ±2%, or less. If their nominal value is
390 Q or less, their tolerance can be ±5%.

4) Longitudinal Impedance (ZLong) Selecting the RS Resistors
The longitudinal impedance is determined by the RS
resistors at the TSI and RSI pins according to the
following equation:
ZLong =

RS + 100
51

(4)

ZLong is defined as VLong/ILong as shown in Figure 33; for
RS ~ 9.1 kQ, ZLong = 180 Q. The calculated value of ZLong
includes the fact that the RS resistors are in parallel with the
synthesized impedance. The tolerance of the RS resistors
therefore depends on how much mismatch can be tolerated
between the longitudinal impedances at Tip and at Ring.
Calculations indicate the two RS resistors can have a ±5%
tolerance, and still comfortably provide a minimum of 58 dB
longitudinal balance.

MC33121
2-277

The resistors must be able to withstand transient voltages
expected at Tip and Ring. The T81 and R81 pins have internal
clamp diodes rated for a maximum of 1.0 A under surge
conditions only (Figure 33). Resistor manufacturers must be
consulted for the proper type of resistor for this environment.
5) AC Terminating Impedance and Source Impedance
(Zacl- Return Loss
The return loss measurement is a measure of how closely
the AC impedance of the SLiC circuit matches the characteristic impedance of the phone line, or a reference impedance.

The reference impedance can be, in some cases, a pure
resistance (commonly 600 Q or 900 Q), a series resistor and
capacitor (900 Q + 2.16 IlF), or a more complex network.
To achieve proper return loss with the MC33121, the RRO
impedance shown in Figure 34 is to have the same configuration as the reference impedance, but with values scaled
according to the equations mentioned below.
CRO, used primarily for DC blocking, is generally a large
value (1.0 IlF) so as to not affect the impedance of RRO.
However, it can be included in the RRO network if a complex
network is required.

Figure 33. Longitudinal Impedance

i - --- -- - - -- - -- - - - l

,--,=;-=;--_ _ _ _ _ _V-'-cc-i

r -___________E~P

RS

Common
Mode
Detector
&
Amplifier

RS

EN I
Buffer
L-------,.V-c-E~E
MC33121
-24 V O>---b...b'--------------==cL ________________

I
I
I
I
I
I
I
I
I
I
I
I
I

-.J

Figure 34. AC Terminating Impedance
~r-~----------------l

3060

,IA
,--,;;::::c:-'--;

I
I
I
:

I
I VAG

RC1.O k

TSI
RSI

3060

I
I
I
I
I
I

I __________________
To VEE
MC33121 I
L
--l

MC33121
2·278

IA ~ IRXI

MOTOROLA COMMUNICATIONS DEVICE DATA

same as the complex load, but with all impedance values
increased according to the scaling factor of Equation 9.

Zac is the impedance looking into the circuit from Tip and
Ring (set by RRO), and is defined as VUIL. Half of Zac is
from Tip to VCC, and the other half is from Ring to VaB (an
AC ground). Each half is made up of a synthesized impedance (ZT/2) in parallel with RS and (RC + 31 k). Therefore,
Zac is equal to:
Zac = [ZT/2 IIRSII(RC + 31 k)] • 2

[(RC + 31 k)IIRSj. 1.037 • 10 6
SF = (RC + 31 k) • [(RC + 31 k)IIRS - (Zacl2)]

(5)

SF = 1.037 • 106/(RC + 31 k)
and ~ = (RSII(RC + 31 k)] • (Zacl 2 )
2
(RSII(RC + 31 k)} - (Zac/2)

If the AC load is:

The synthesized impedance ZT is created as follows:
An incoming signal VL produces a differential voltage at
CP and CN, and therefore at TXO equal to:

=J

5L
J~F

900~-

Then RRO should be:

R~~i 31.t5k(RRO)

ToTip
and Ring

From

(7)

---I 62 nF (CRO)

TXO

The signal at TXO creates an AC current IRXI through
RRO. RXI is a virtual ground, and CRO is insignificant for
first order calculations.
IRXI is gained up by a factor of 102 to produce the current
IT through the transistors.
ZT is therefore VLilT. The relationship between ZT and
RRO is:
RRO =

(9a)

For example:

(6)

V
_ VL· 31 k. 0.328
TXO (RC + 31 k)

(9)

Zac is computed at a nominal frequency of interest. A first
order approximation of Equation 9 is:

ZT. 1.037.106
(31 k + RC)

If the AC load is:

820E:.115
~F
220

Then RRO should be:

R~~

J

To Tip
and Ring

3.3 nF

F

CRO

;~--1

(8)

28.4 k
7.61 k

CRO must remain in series with the network to provide
DC blocking. If the load network does not include a series
capacitor (as in the second example above), CRO should
be large (1.0 llF) so its impedance does not affect the RRO
network. The above procedure will yield a return loss measurement which is constant with respect to frequency. The
RRO resistor, or network, must have a tolerance equal to
or better than the required system tolerance for return loss
and receive gain.

While equation 8 gives the exact value for RRO, a first order
approximation is Zac • 33.5.
a) Resistive Loads (with RC = 1.0 k, RS = 9.1 k):
For a 600 n resistive system, ZT calculates to 626 Q, and
RRO calculates to 20.3 kn.
For a 900 n resistive system, ZT calculates to 961 n, and
RRO calculates to 31.14 kn.
b) Complex Loads
For complex (nonresistive) loads, the MC33121 must be
made to look like a termination impedance equal to that
complex load. This is accomplished by configuring RRO the

6) Receive Gain (GRX)
The receive gain involves the same circuit as Figure 34,
but with the addition of the RRX resistor (or network) which
sets the receive gain. See Figure 35.

Figure 35. Receive Gain

r------,

I
I VAG

r -__________~E~P

n

BP I

]-----=,

I
I

RC 1.0 k

t-~-~~---A.J'V\r---t

I RXI
I
I
I TXO
I
I
I
I
L-________~EN~
I
L _____ J

IRXI

RRX

MC33121

MOTOROLA COMMUNICATIONS DEVICE DATA

RRO

cRoT

t

ITXO

MC33121

2-279

- - - - - - - -----------_.

-------

The receive gain (GRX), defined as the voltage gain from
VRX to VL, is calculated as follows:
RXI is a virtual ground, and Rae is the AC impedance of the
load (phone line),
The AC current generated in the transistors is 102 • IRXI,
which is equal to 102 • (IR - ITXO).
IR = VRX/RRX, and
ITXO = VTXO = VL • 31 k • 0.328
RRO
RRO • (31 k + RC)

(10)

The preceeding procedure will yield a receive gain which is
constant with respect to frequency. The RRX resistor, or
network, must have a tolerance equal to or better than the
required system tolerance for receive gain.

7) Transmit Gain (GTX)
Setting the transmit gain involves selecting RTX1 and RTX2
in Figure 28. The voltage gain from VL to VTX is calculated
from the following:
RTX2 • 31 k. 0.328
RTXl • (RC + 31 k)

Using equations 5 and 8, involving Zac, RS and RC, and the
above equations yields:
VL
102 • (RacllZacl
--=GRX=
VRX
RRX

(11)

Therefore, RRX = 102. (RacllZacl
GRX

(12)

Equation 12 applies only for the case where Rac and Zac

have the same configuration. If they also have the same
magnitude, then set RRX = 51 • Rac to set a receive gain
of 0 dB. The AC source impedance of the above circuit to
Tip and Ring is Zac. For the case where Rae " Zac, use the
following equation:
102
VL

VRX -

J

RRX.[J....+
1.037.106
ZL
(31k + RC). RRO

(13)

where ZL = [ R:c II RS II (RC + 31 k)] .2

(14)

a) Resistive Loads
For a 600 n resistive system, set RRX = 30.6 kn, and
for a 900 n resistive system, set RRX = 45.9 kn.
b) Complex Loads
For complex (non resistive) loads, the RRX resistor needs
to be replaced with a network having the same configuration
as the complex load, but with all impedance values scaled
up by a factor of 51 (for 0 dB gain). If a gain other than 0
dB is desired, the scaling factor is determined from Equation
12. This method applies only if the RRO network has been
made complex comparable to the load according to the
procedure in the previous section (Equations 5-9a), such that
Rac = Zac. Using a scaling factor of 51, and the previous
examples, yields:

If the AC load is:

Then RRX should be:

=J

J~
~F
900 ~ - _

-------,

TO~~V
Tolip
and Ring

If the AC load is:

MC33121
2-280

i'

RX

~FTo lip

J

r-1 ~.25 nF i

TO~

and Ring RXI

8) Balance Network (RB) - Transhybrid Rejection
When a receive signal is applied to VRX to produce a signal
at Tip and Ring, the two-to-four wire arrangement of a hybrid
(the MC33121) results in a reflected signal at TXO. Transhybrid rejection involves canceling that reflected signal before
it appears at VTX. The method used is to insert the RB
resistor (or network) as shown in Figure 36. The current IB,
supplied from VRX, cancels the current ITXl supplied from
TXO (Node A is a virtual ground). Good transhybrid cancellation requires that the currents be equal in magnitude and
180 0 out of phase at Node A.
Using the equations for transmit and receive gains, the
current ITXl is equal to:

33.5. VRX. Zac. ZL. 31 k
ITXl = RRX. [Zac + ZU. RTX1 • (RC + 31 k)

(16)

a) For the case where RRO and RRX are comparable in
configuration to ZL:
Since IB = VRX/RB, then RB can be determined from:

r--------,

!

For 0 dB gain, set RTX2 = 3.15 x RTXl (for RC = 1.0 k).
The actual values of RTX2 and RTXl are not critical - only
their ratio so as to provide the proper gain at the op amp.
Once the ratio is established, the two resistors can be
selected from a set of standard resistor values. The minimum
value for RTXl is limited by the drive capability of TXO, which
is a nominal ±800!iA peak (±275!iA minimum). As a general
rule, RTX1 should be between 5.0 kn and 20 kn. The load
on TXO is the parallel combination of RTXl and RRO.
CTX is for DC blocking, and is typically a large value
(1.0 !iF) so as to not be a significant impedance. In general,
it should not be used for low frequency rolloff as that will
affect the transhybrid rejection (discussed in the next section). Low frequency rolloff should be done after the op amp.
High frequency roll-off can be set by placing a capacitor
across RTX2.
For complex loads (at 1ip and Ring), if RRO and RRX have
been made complex comparable to the load as described
in the previous sections, neither RTXl nor RTX2 needs to
be complex since both the transmit and receive signals which
appear at TXO will be flat with respect to frequency.
. RTXl and RTX2 must have a tolerance equal to or better
than the required system tolerance for the transmit gain.

~

Then RRX should be:

820 r ; : . 1 1 5
220

IL 45.9
k
42 i _
_ _ _ _nF

RXI

(15)

IL..11.2
k 41.8 k
______ J

VRX

RB=

RRX • RTXl • (RC + 31 k)
33.5 • [ZacllZLl • 31 k

(17)

MOTOROLA COMMUNICATIONS DEVICE DATA

Figure 36. Balance Resistor
Tip

-

IRX

RRX
RTXl

Ring

-

I
IL MC33121
VL_
x 0.328
________
__ I

ITX1

...J

Equation 17 provides a value for an RB resistor which will
provide the correct magnitude for lB. The correct phase
relationship is provided by the fact that the signal at TXO
is out of phase with that at VRX. The phase relationship will
be 1800 only if RRO and RRX are of a configuration identical
to that of the load. This applies regardless of whether the
load, ZL, (and RRO and RRX) are purely resistive or of a
complex nature. Equation 17 reduces to a non-complex
resistance if RRX, Zac, and ZL are all comparably complex.
For the case where Zac = ZL, RRX = 51 • Zac, and
RC = 1.0 k, Equation 17 reduces to:
RB = 3.15. RTXl

vRX

IB~

RTX2

RB

0

To simplify the explanation, the current source and Zac of
Figure 36 are replaced with the Thevenin voltage source and
series Zac. Since ZL and Zac are not matched, there will be
a phase shift from VRX to the signal across Tip and Ring.
This phase shift is also present at TXO. The same phase
shift is generated at node B in the RB network by making
RBI equal to Zac, and ZL equal to the load. RB2 is then
calculated from:
RRX. RTXl • (RC + 31 k)
(19)
RB2 = - - - - - ' - - - 33.5 • Zac • 31 k
For example, for a system where the load is considered a
600 Q resistor (RRO = 20.3 kQ, RRX = 30.6 kQ, RTXl =
10 kQ, and RC = 1.0 kQ), RBI would be a 600 Q resistor,
ZL (in the RB network) would be a 600 Q resistor in parallel
with a 0.005 ~F capacitor, and RB2 calculates to 15.715 kQ.
The RB resistor, or network, must have a tolerance
equal to or better than the required system tolerance for
transhybrid rejection.

(18)

b) For the case where Zac and ZL do not have the same
frequency characteristics:
For the case where, for reasons of cost an!:l/or simplicity,
the load (RU is considered resistive (whereas in reality it
is not a pure resistance) and therefore resistors, rather than
networks, were selected for RRO and RRX, using a simple
resistor for RB may not provide sufficient transhybrid rejection due to a phase angle difference between VRX and TXO.
The terminating impedance may therefore not necessarily
be matched exactly to the line impedance, but the resulting
circuit still provides sufficiently correct performance for receive gain, transmit gain, and return loss. The rejection can
be improved in this case by replacing RB with the configuration shown in Figure 37. Even on a very short phone line
there is a reactive component to the load due to the two
compensation capacitors (CC, Figure 4) at the transistor
collectors. The two capacitors can be considered in series
with each other, and across the load as shown in Figure 37.

9) Logic Interface
The logic circuit (output ST1, and the 1/0 labeled ST2/PDI)
is depicted in Figure 30, and functions according to the
Status Output Truth Table (Table 1).
a) Output Characteristics
STI is a traditional NPN pull-down with a 15 kQ pull-up
resistor. Figures 19 and 20 indicate its output characteristics.
ST2 is configured with the following items: a) a 1.0 mA
current source for a pull-down which is active only when ST2
is internally set low; b) an 800 ~A current source pull-up
which is active only when ST2 is internally set high; c) a
positive feedback aspect within this output circuit which

Figure 37. Balance Network

RRX

-----,
I RB
I
I
I
RB2
_ _ _ _ ..JI

RTX1

I
I

Ring

ITX1

l ______M~~1~J

RTX2

o
MOTOROLA COMMUNICATIONS DEVICE DATA

>-4---.. VTX

MC33121
2-281
-----------------,,-----

c) Pulse Dialing
During pulse dialing, STI will change state concurrent with
the hookswitch. ST2 is kept from switching during pulse
dialing by the external capacitor (CT), which keeps the
MC33121 in a powered up condition and stable. If the CT
capacitor is too small, the voltage at ST2 could drop to the
PDlthreshold (see section e below) during each pulse. This
could cause the MC33121 to create additional noise on the
line as it would cycle between a power-up and power-down
condition with each dialing pulse.

provides considerable hysteresis for stability reasons. Its
output characteristics are shown in Figures 21 and 22. Due
to this configuration, any external pull-up resistance which
is applied to this pin must be greater than 15 kO, or the output
may not reliably switch from high to low. Any external
pull-down resistance does not affect this output's ability to
switch from low-to-high, but does affect the maximum longitudinal currents which can be accepted by the circuit (see the
section on Longitudinal Current Capability). The capacitor
(CT) is required to provide a time delay, for stability reasons,
during transitions between off-hook and on-hook. This capacitor additionally affects maximum longitudinal currents,
as well as stability during pulse dialing (explained below).

d) Fault Detection
Faults are defined as excessive leakage from Tip to VEE
and/or ground, and from Ring to VEE and/or ground. A single
fault is anyone of the above conditions, while a double fault
is defined as excessive leakage from Tip to VEE and from
Ring to VCC, as depicted in Figure 38. Refer to Figures 11-15
for the resistance, RLK, which will cause the MC33121 to
switch to a power-down condition. If the leakage resistance
is less than that indicated in the graphs, the MC33121 will
power-down itself and the two external transistors, thereby
protecting them from overheating. Both status outputs (STI
and ST2) will be at a logic low, indicating a fault condition.
A fault condition is detected by monitoring an imbalance in
the magnitudes of the currents at TSI and RSI, and/or a
polarity reversal at Tip and Ring.
The MC33121 will detect the following conditions:
1) When on-hook (see Figure 11):
a) <2.6 kO between Ring and VCC (depending on RS
and VEE), with no hysteresis at this threshold, or
b) <3.7 kn between Tip and VEE (depending on RS and
VEE), with no hysteresis at this threshold, or
c) Both a and b simultaneously.
Leakage from Tip to VCC and/or Ring to VEE are not
detected as faults while the MC33121 is on-hook.
2) When off-hook (367 0 between Tip and Ring):
a) <400 0 between Tip and VCC (RS = 6.2 kO), or
b) <1800 0 between Tip and VEE, or
c) <4000 between Ring and VEE (RS = 6.2 kO), or
d) <1800 0 between Ring and VCC, or
e) Both band d simultaneously

b) Hook Status
The MC33121 uses the sense currents at CP and CN to
activate the hook status circuit. The senSing is configured
such that the circuit monitors the impedance across Tip/Ring,
which results in the hookswitch thresholds are minimally
affected by the battery voltage. The off-hook to on-hook
threshold is affected by the choice of RRF according to the
graph of Figure 8, but is not affected by the value of RS.
The on-hook to off-hook threshold is affected by the value
of RS according to the graph of Figure 9, but is not affected
by RRF. Varying the RC resistors does not affect the thresholds significantly.
When the telephone is on-hook (STI = High, ST2 = Low),
the MC33121 is internally powered down, the externaltransistors are shut off, and power consumption is at a minimum.
Upon closure of the phone's hookswitch, STI will switch low
within 10 !ls. ST2 will then change state slowly due to the
external capacitor (CT = 5.0 !IF). There is a =8.0 ms delay
for ST2 to reach the threshold necessary to activate the
internal bias circuit, which in turn activates the external drive
transistors to supply loop current. This delay is necessary
to prevent instabilities during the transition to off-hook.
Upon opening the telephone's hookswitch, STI will switch
high within =200 !ls. ST2 then requires =60 ms to reach the
threshold to switch off the internal bias circuit, which in turn
shuts down the external drive transistors.

Figure 38. Fault Detection
On-Hook

n

MC33121

ST2

MC33121
2-282

~

VEE

I
I
I

STI

VEE

Off-Hook

VCC~-----1

I-}

I
I
I
I
I

I

L_ _ _ _ _ ~

n

MC33121

STI

=0

ST2

Ring

I

Ru<
VEE

Off-Hook

VCC~-----1

~

VEE

I
I
I
I-}
I
I
I

':'

I

I

MC33121

I
I
I

STI

=0

ST2

I

L_ _ _ _ _ ~

.l.VCC , - - - - - 1

VEE

~

VEE

L_ _ _ _ _

I-}

I
I
I
I
I

=0

I

~

MOTOROLA COMMUNICATIONS DEVICE DATA

A simultaneous occurrence of conditions a) and c) is not
detected as a fault. See Figures 12 to 15 for the threshold
variation with RL and VEE. Resetting of the fault detection
circuit requires that the leakage resistance be increased to
a value between 10 kQ and 20 kQ, depending on VEE, RL,
and RS. Both STI and ST2 should be monitored for
hookswitch status to preclude not detecting a fault condition.
Figure 15 indicates the variation in fault thresholds for
Tip-to-VCC and Ring-to-Battery faults, and is valid only for
loop resistances of 200 Q to BOO Q. On loops larger than
BOO Q, the MC33121 does not reliably indicate the fault
condition at STI and ST2, but may indicate on-hook status
instead. This does not apply to Tip-to-Battery and
Ring-to-VCC faults which are correctly detected for lines
beyond BOO Q.

Based on the results of almost ten years of +125°C
operating life testing, Table 2 has been derived indicating
the relationship between junction temperature and time to
0.1 % wire bond failure.
Table 2. Statistical Lifetime
Junction
Temperature (0C)

Time
(Hours)

Time
(Years)

80
90
100
110
120
130
140

1,032,200
419,300
178,700
79,600
37,000
17,800
8,900

117.8
47.9
20.4
9.4
4.2
2.0
1.0

Motorola MECL DeVice Data, DL 122

e) POI Input
The ST2 output can also be used as an input (POI Input)
to power down the circuit, denying loop current to the
subscriber (by shutting off the external pass transistors),
regardless of the hookswitch position. Powering down is
accomplished by pulling POI to a logic low with an open
collector output, or an NPN transistor as shown in Figure
30. The switching threshold is ~1.5 V. The current out of POI,
when pulled low, is ~BOO flA. Releasing POI allows the
MC33121 to resume normal operation.
If the external telephone is off-hook while the MC33121
is powered down, sense currents at CP and TSI will result
in some loop current flowing through the loop and back into
CN and RSI. This current is generally on the order of 1.0
to 3.0 mA, determined primarily by the RS resistors, loop
resistance, and VEE. STI will continue to indicate the telephone's actual hook status while POI is held low. The
on-to-off hook threshold is the same as that during normal
operation, but the off-to-on hook threshold is >250 kQ.
When powered down with the POI pin, the receive gain
(VRXI to Tip/Ring) is muted by >90 dB, and the transmit gain
(Tip/Ring to TXO) is muted by >30 dB.
Power Dissipation, Calculation and Considerations
a) Reliability
The maximum power dissipated by the MC33121 must be
considered, and managed, so as to not exceed the junction
temperature listed in the Maximum Ratings Table. Exceeding this temperature on a recurring basis will reduce long
term reliability, and possibly degrade performance. The
junction. temperature also affects the statistical lifetime of
the device, due to long term thermal effects within the
package. Today's plastiC integrated circuit packages are as
reliable as ceramic packages under most environmental
conditions. However, when the ultimate in system reliability
is required, thermal managements must be considered as
a prime system design goal.
Modern plastic package assembly technology utilizes gold
wire bonded to aluminum bonding pads throughout the
electronics industry. When exposed to high temperatures for
protracted periods of time an intermetallic compound can
form in the bond area resulting in high impedance contacts
and degradation of device performance. Since the formation
of intermetallic compounds is directly related to device junction temperature, it is incumbent on the designer to determine
that the device junction temperature is consistent with system reliability goals.

The "Time" in Table 2 refers to the time the device is
operating at that junction temperature. Since the MC33121
is at a low power condition (nominally 40 mW) when on-hook,
the duty cycle must be considered. For example, if a statistical duty cycle of 20% off-hook time is used, operation at
130°C junction temperature (when off-hook) would result in
a statistical lifetime of ~1 a years.
b) Power and Junction Temperature Calculation
The P9wer within the IC is calculated by subtracting the
power dissipated in the two-wire side (the transistors and
the load) from the power delivered to the IC by the power
supplies. Refer to Figure 4 and 27.
Po = IVoo

0

1001 + IVEE

0

IEEI- (lL

0

IVEP - VEN!)

(20)

The terms VEP and VEN are the OC voltages, with respect
to ground, at the EP and EN pins. These voltages can be
measured, or can be approximated by:
VEP ~- (30 Q o III
VEN ~ IVEEI + 2.1 V + (IL 0 35 Q)
Refer to Figure 23. The junction temperature is then calculated from:
(21 )

TJ = TA + (PO o9JA)

where TA is the ambient air temperature at the IC package,
and 9JA is the junction-to-ambient thermal resistance shown
in Figure 39. The highest junction temperature will occur at
maximum VEE and VOO, maximum loop current, and maximum ambient temperature.
If the above calculations indicate the junction temperature
will exceed the maximum specified, then it is necessary to
reduce the maximum loop current, ambient temperature,
and/or VEE supply voltage. Air flow should not be restricted
near the IC by tall components or other objects since even
a small amount of air flow can substantially reduce junction
temperature. For example, typically an air flow of 300 LFPM
(3.5 mph) can reduce the effective 9JA by 14 to 20% from
that which occurs in still air. Additionally, providing as much
copper area as possible at the IC pins will assist in drawing
away heat from within the IC package. For additional information on this subject, refer to the "Thermal Considerations"
section of Motorola MECL System Design Handbook, and
the "System Oesign Considerations" section of Motorola
MECL Device Data.

MC33121
2-283

MOTOROLA COMMUNICATIONS OEVICE OATA

---------

-------- -------

measure the conditions on the transistors during the worse
case fault(s).

Figure 39. Thermal Resistance
(Junction-to-Ambient)
70

Table 3. Transistor Power During a Fault

I.........
60

MC33121
Still air. soldered
to a G-l0 PC Board

r-....
I.........

r-....
.........

.........
'-...,

'-....

40

30
25

35

45

65

75

"

85

Selecting the Transistors
The specifications for the two loop current pass transistors
involve their current gain, voltage rating, and power dissipation capabilities at the highest ambient temperatures. Power
dissipation during both normal operation and faults must be
considered when determining worst case situations. Generally, more power is dissipated during a fault condition than
during normal operation.
The transistors' minimum beta is recommended to be 40
at the loop currents involved in the application. A lower beta
could degrade gain and balance performance. Maximum
beta should be less than 500 to prevent possible oscillations.
Darlington type transistors should not be used. The voltage
rating should be consistent with the maximum VEE, expected
transients, and the protection scheme used.
Referring to Figure 27, during normal operation the loop
current and the voltage across the transistors are both at
a maximum when the load impedance (RLl is at a minimum.
The loop current is determined by RRF and the graphs of
Figures 5-7. The voltage across each transistor is determined from the following:
IVEEI- 2.1 - [(65 + 2RP + RLl • III
VT=

2

(22)

The power in each transistor is then (VT • Ill. The voltage
across the two transistors will always be nearly equal during
normal operation, resulting in equal power dissipation. The
graph of Figure 24 indicates the power dissipated in each
transistor where RP = 100 n.
During a fault condition, depicted in Figure 38, if the
leakage resistance from Tip to VEE or from Ring to VCC is
less than that shown in Figures 12-14 (when off-hook), the
MC33121 will power down the transistors to protect them
from overheating. Should the leakage resistance be slightly
higher than that shown in the graphs, however, and the fault
detection has not been activated, the power in one transistor
(in a single fault, both transistors in a double fault) will be
higher than normal. The power will depend on VEE, RL, RP
and the leakage resistance. Table 3 is a guide of the power
in the transistor dissipating the higher power level.
The power (in watts) in the two right columns indicates the
power dissipated by that transistor if it is carrying the maximum fault current. The system designer should attempt to
predict possible fault conditions for the system, and then

MC33121
2·284

VEE

RL

PPNP

PNPN

--42
-24
--42
-24

150
150
600
600

0.835
0.257
0.601
0.109

0.615
0.176
0.185
0.057

For most applications involving a maximum loop current
of 30-40 mA, and a maximum TA of +85°C, and where faults
may occur, the MJD243 and MJD253 DPAK transistors are
recommended. When mounted as described in their data
sheet, they will handle both the normal loop current as well
as most fault conditions. If faults are not expected to occur
in a particular application, then smaller package transistors,
such as MPS6717 and MPS6729, may be used. Each
application must be evaluated individually when selecting
the transistors.
Other possible transistors which can be considered:
PNP
MJD253-1
MJE253
MJD32
MJD42
MJD350
TIP30A,B,C

NPN
MJD243-1
MJE243
MJD31
MJD41
MJD340
TIP29A,B,C

Longitudinal Current Capability
The maximum longitudinal current which can be handled
without distortion is a function of loop current, battery feed
resistance, the longitudinal impedance, and the components
on ST2.
Since the pass transistors cannot pass current in the
reverse direction, the DC loop current provides one upper
boundary for the peak longitudinal current plus peak speech
signal current. The battery feed resistance determines, in
effect, the DC voltage across the transistors, which is a
measure of the headroom available for the circuit to handle
the peak longitudinal voltage plus peak speech signal voltage. The longitudinal impedance, determined by the RS
resistors (equation 4), determines the longitudinal current for
a given longitudinal voltage.
While analysis of the above items may yield one value
of maximum longitudinal current, a different limit (which may
be higher or lower) is imposed by the capacitor CT, and any
pulldown resistance RT, on Pin 12 (ST2). This is due to the
fact that the sense currents at TSI and RSI will be alternately
mismatched as Tip and Ring move up and down together
in the presence of longitudinal signals. When the longitudinals are strong, the internal fault detect circuit is activated
with each 1/2 cycle, which attempts to switch ST2 low (see
the section on Fault Detection). The speed at which ST2 can
switch low is a function of both the external capacitor, CT
and any pulldown resistance, Ry.
The graphs of Figures 25 and 26 indicate the maximum
longitudinal current which can be handled (in Tip and in Ring)
without distortion or causing ST2 to switch low.
PC Board Layout Considerations
PC board considerations include thermal, RFI/EMI, transient conditions, interconnection of the four wire side to the
codec/filter, and others. Wirewrapped boards should be

MOTOROLA COMMUNICATIONS DEVICE DATA

avoided - breadboarding should be done on a (at least)
reasonably neat PC board.
a) Thermal
Power dissipated by the MC33121 and the two transistors
must be removed to prevent excessively high junction temperatures. The equations for calculating junction temperatures are mentioned elsewhere in this data sheet. Heat is
removed by both air flow and copper foil on the PC board.
Since even a small amount of air flow substantially reduces
junction temperatures compared to still air, tall components
or other objects should not be placed such that they block
air flow across the heat generating devices. Increasing,
wherever possible, the area of the copper foil at the IC pins
will provide additional heat removal capability. A ground
plane can generally help here, while at the same time helping
to reduces RFI problems.
b) RFI/EMI
While the MC33121 is intended for use at audio frequencies, the internal amplifiers have bandwidths in excess of
1.0 MHz, and can therefore respond to externally induced
RFI and EM!. Interference signals can come in on the phone
line, or be radiated on to the PC board from nearby radio,
stations or from high frequency circuitry (digital & microprocessor circuitry) in the vicinity of the line card.
Usually RFI entering from the phone line at Tip and Ring
can be removed by the compensation capacitors (CC) provided they are connected to a good quality RF ground
(generally the same ground which connects to VCC on the
MC33121). The ground track should be as wide and as direct
as possible to minimize lead inductance. Generally better
results can be obtained if an RF bleedoff to earth (or chassis)

ground can be provided where the twisted pair phone line
comes into the system.
To minimize problems due to noise radiating directly onto
the PC board from nearby high frequency circuitry, all components associated with the MC33121 should be physically as
close as possible to the IC. The most sensitive pins in this
respect are the CP, CN, RSI, TSI, VAG and RXI pins.
Keeping the tracks short minimizes their "antenna" effect.
c) Transient Conditions
When transient voltages come in to Tip and Ring, the
transient currents, which can be several amperes, must be
carried by the ground line (VCC) and/or the VEE line. These
tracks, along with the protection and clamping devices,
must be designed for these currents at the frequencies
involved. If the tracks are narrow, not only may they be
destroyed by the high currents, but their inductance can
allow the voltage at the IC, and other nearby components,
to rise to damaging levels.
The protection circuits shown in Figure 4, and in other
figures in this data sheet, are such that the bulk of the
transient energy is dissipated by external components (the
protection resistors and the clamp diodes). The MC33121
has internal diodes to limit voltage excursions on the pins,
and to pass a small amount of the transient current typically less than 1.0 A peak. The arrangement of the diodes
is shown in Figure 40.
d) Interconnection of the four-wire side
The connections on the four-wire side to the codec and
other digital circuitry involves keeping digital noise out of
the speech paths, and also ensuring that potentially
destructive transients on Tip and Ring do not get through
to the +5.0 V system.

Figure 40. Protection Diodes

+5.0 V

I STI

MC33121

I
I
I ST2
CP
To Digital
Ground
TSI
To Analog
Ground

RSI
14V

I TXO
CN

I

RFO

I
I CF
VOB

All zener diodes are 7.0 V,
except where noted.

14V

9.0V

I
I

-------------------~

MOTOROLA COMMUNICATIONS DEVICE DATA

MC33121
2-285

Basically, digital connections to STI and ST2 should be
referenced to the VDD and VDG pins, while the transmit and
receive analog signals should be referenced to the analog
ground (VAG). VCC should be connected to a clean battery
ground, and generally should not be connected directly to
VDG and/or VAG (on the line card) when strong transients
are anticipated. Even with a good layout, VCC can move
several volts when a transient hits, possibly damaging
components on the +5.0 V line if their grounds have a
direct connection at the line card. The MC33121 is designed to allow VCC to move as much as ±30 V with
respect to VDG and VAG on a transient basis only. VCC and
the other grounds should preferably be connected together
at the power supply rather than at the IC. Internally, the
MC33121 has clamp diodes on the 4-wire side pins as
indicated in Figure 40.
If the codec has a single ground pin, as in Figure 41, it
will be the reference for both the digital and analog signals,
and must be connected to both VAG and VDG on the
MC33121. If the codec has separate digital and analog
grounds, as in Figure 42 (the MC145503 internally generates

the analog ground), then each ground should be connected
to the appropriate ground on the MC33121.
e) Other
A 0.1 I!F capacitor should be provided across VCC to
VEE on the MC33121 to help keep idle channel noise to
a minimum.
The CaB capacitor (on the VaB pin) forms a pole with an
internal 7.5 kQ resistor to filter noise from the VEE pin,
providing an internal quiet battery supply for the speech
amplifiers. Power supply rejection will depend on the value
and quality of this capacitor at the frequencies of concern.
Tantalum capacitors generally have better high frequency
characteristics then electrolytics. See Figure 17 and 18 for
ripple rejection characteristics (the four-wire data was measured at pin 11 (TXO)). Figure 16 indicates ripple rejection
from the +5.0 V supply (VDD).
In general, pc board tracks carrying analog signals (on the
four-wire side and TIp/Ring) should not be routed through
the digital section where they could pick up digital noise. Any
tracks longer than a few inches should be considered an

Figure 41. Connection to a CODEC With a Single Ground
. - - - - - - - - - - - - - - - - - - - - - - - Battery Ground
.------------_-DigitaIGround
+5.0V

.-----------+---

Ivee -v; H~------ -5.0 V

I
I

VDG~~~~~~-+~~~----,

MC",::r

~O~~
__-+~__~
I

E1~!L_~Egj

'----:OC":.t-ifl-+---------~;::;:;.;====~;::;:;.;=-- Battery Supply
Figure 42. Connection to a CODEC With Separate Grounds
. - - - - - - - - - - - - - - - - - - - - - - - BatteryGround
. . . . - - - - - - - - - - - -.......... DigitaiGround
+5.0V

r-----------+-::-:--

1--<0----- -5.0 V

VAG~--------.---+~--------,

I

MC3312~I'D
~ol

tOI!F

MC33121
2-286

H VaB

VEE

'-----1-='''-----1

I

L-----O-~.t-f-I4---------------------------­ Battery Supply

MOTOROLA COMMUNICATIONS DEVICE DATA

antenna and should be checked for potential noise or RFI
pickup which could affect the circuit operation.
Alternate Circuit Configurations
a) Loop Current Limit
Replacing the RRF resistor with the circuit in Figure 43
will change the DC loop current characteristics in two ways
from the graphs of Figures 5-7; a) the maximum loop current
on a short line can be reduced while increasing the current
on a long line, and b) the temperature dependence of the
maximum current is reduced to the TC of the external
reference diode.

a small amount (=10%) flows through the sense resistors
and the CP, CN, RSI pins. On a positive transient, all the
current is directed to ground. The diode in the NPN's collector
prevents reverse current through the base-collector junction
of the transistor during a negative transient.

Figure 44. Loop Current versus Loop Resistance
Alternate Loop Current Limit Configuration
50

Figure 43. Alternate Current Limit Circuit
vAG
RXI h

~

RRFI

..............
LM385-1.2

RRF2
RFO

I

The LM385-1.2 is a precIsion temperature stable zener
diode. As the load impedance at Tip and Ring is reduced,
the voltage at RFO goes increasingly negative. When the
zener diode is turned on, the current into RXI is then clamped
at a value determined by RRFI and the zener diode. To
calculate the two resistors, use the following procedure:
RRFI must be >0.7 • (RRFI + RRF2);
Determine RRFI to set the current limit on a short line
by using the following equation:
RRFI =

102 • 1.23 V
IL(max) - 3.0 mA

--

r--

RRF1.4.3kO
RS.9.1 k
VEE' -24 V RRF2 • 820 0
TA·25°C
I
10 0
200
400
600
Rlo LOOP RESISTANCE (0)

800

Figure 45_ Alternate Protection Scheme

(23)

MC33121

Then using Equation 1 calculate RRF for the long line
current. RRF2 is then determined by;
RRF2 = RRF - RRFI

(24)

Figure 44 illustrates one example using the above
circuit. Comparing this graph to the 5100 Q curve of
Figure 7 shows a substantial decrease in the current limit
(at RL = 0), resulting in reduced power consumption and
dissipation. Use of this circuit does not affect the
hookswitch or fault thresholds.
b) Protection Scheme
The protection circuit shown in Figure 45 has the advantage of drawing =90% of the transient current from ground
(VCC) on a negative transient, rather than from the VEE line
as the circuit of Figure 4 does. The majority of the transient
current flows through the RP resistors and the Mosorbs while

MOTOROLA COMMUNICATIONS DEVICE DATA

-;-;--+.....__1:...:4c..:V-'

-24 V _ _

VEEL _ _ _ _ _ _ _ _ _
All zener diodes are 7.0 V except as noted.

MC33121

2-287

CIRCUIT PERFORMANCE
The following three circuits are presented as typical application examples, and the accompanying graphs indicate
their measured performance. The first circuit (Figure 46) has
a 600 Q pure resistance as the AC load. The second circuit
(Figures 47) has as an AC load a 900 Q resistor in series
with a 2.16 IlF capacitor. The third circuit (Figure 48) has

as an AC load, a complex network composed of an 820 Q
resistor in parallel with 0.115 IlF, and those in series with
a 220 Q resistor. In the graphs of Figures 49-51, RL = Return
Loss, THR = Transhybrid Rejection, GTX = Transmit Gain,
GRX = Receive Gain.

Figure 46. 600 Q System
20
19
MJ0253 18
17
16

VCC

VOO

EP

POI

ST2IPDI

BP

ST1

ST1

CP

VOG

TSI

RAC
600n

VAG
MC33121

MJ0243

RSI

AXI

CN

RFO

BN

TXO

EN

CF

Receive
In (VRJ()

10k
300
20
-28V

VaB

VEE

::r:: 0.1

±

IOIlF

Figure 47.900 nand 2.161lF System
20
19
MJ0253 18
17
9.1 k

16

RAC
ooon
2.16 11F

VCC

VOO

EP

POI

BP

ST1

CP

VOG

TSI

VAG

15
12

ST2IPDI

13

STI

14
9

MC33121
RSI

9.1k
4

1--..--------- Receive

AXI

In (VRx)

31.6 k
CN

RFO

BN

TXO

~TransmH
r --

62nF
MJ0243

11
10 k

1.01lF

300
EN

CF
20

-28 V

MC33121
2-288

VEE

~0.1

VaB

±

:J
IOIlF

Out(VTxl

1.01lF

MOTOROLA COMMUNICATIONS DEVICE DATA

Figure 48.2200 and 820 0110.115

20
19
MJ0253 18
17
16
820

Vcc

VOO

EP

POI

BP

STI

CP

VOG

~F

System

15
12

+5.0 V
0.1
ST2/POI

13

STI

14

VAG

TSI

MC33121
RXI 1-+--_-...J\f'I/Ir-"W\r-t_---- Receive
In (VRX)
31.6 k

RSI

220

CN

RFO
31.6 k

MJ0243

BN

10 k

300
EN

-28 V

CF
VQB

VEE

~0.1

t:;

~
Ii;

30

40

~

rn

~ t-- l -

f. FREQUENCY (Hz)

MOTOROLA COMMUNiCATiONS DEVICE DATA

10 k

'"

V

~ 20

~

v

30

t:;

.~:~
1.0 k

V

:::>

t.-

-0.1 100

IOIlF

50

R':"'-- r-- f-

11i

:::>

1.01lF

~

20

1.0 1lF i j - - Out(VTxl

Figure 50. Circuit Performance
900 0 and 2.16 ~F System

90

~ 50

6

±

Figure 49. Circuit Performance, 600 0 System

70

~Transmit

TXO

THR,\

--

......

f'.
L--

Ii;~

.~~--~=

~
1.0 k
10 k

-0.2 100

f. FREQUENCY (Hz)

MC33121
2-2~9

Figure 51. Circuit Performance
820 Q//0.115 J.lF and 220 Q System

Figure 52. Return Loss Test Circuit
for Figures 46 to 51

80
RL
60

~

in

:s-

40

If"

T

'\

cD II

---t;~
.~'---~.~

CI)

~ I--- r-.

!:i

~

ill
a:

20

---------=-----

-0.2 100

1.0k

VB

"-'

L--

o

.f
1

MC33121
Circuil
(Figures 46,

~____________*-__~:__~~4~7~o~r4~8~)~

Reference Nelwork = RAC of Figures 4610 4B.
Return Loss =20 1091 VA + VB 1
VA-VB

10k

f, FREQUENCY (Hz)

GLOSSARY
ATTENUATION - A decrease in magnitude of a communication signal, usually expressed in dB.
BALANCE NETWORK - That part of the SUC circuit which
provides transhybrid rejection.
BANDWIDTH - The range of information carrying frequencies of a communication system.
BATTERY - The voltage which provides the loop current,
and in some cases powers the SUC circuit. The name derives
from the fact that COs have always used batteries, in
conjunction with AC power, to provide this voltage.
BATTERY FEED RESISTANCE - The equivalent Thevenin
DC resistance of the SUC circuit for supplying loop current.
Traditionally it is 400 Q.
C-MESSAGE FILTER - A frequency weighting which
evaluates the effects of noise on a typical subscriber's system.

dBmp - Indicates dBm measurement using a psophometric
weighting filter.
dBrn - Indicates a dBm measurement relative to 1.0 pW
power level into 600 Q. Generally used for noise measurements, dBrn = -90 dBm.

a

dBrnC -Indicates a dBrn measurement using a C-message
weighting filter.
DTMF - Dual Tone Multifrequency. It is the "tone dialing"
system based on outputting two non-harmonic related frequencies simultaneously to identify the number dialed. Eight
frequencies have been assigned to the four rows and four
columns of a keypad.

CENTRAL OFFICE - Abbreviated CO, it is a main telephone
office, usually within a few miles of its subscribers, that houses
switching gear for interconnection within its exchange area,
and to the rest of the telephone system. A typical CO can
handle up to 10,000 subscriber numbers.

FAULT - An incorrect condition where Tip is accidentally
connected to the battery voltage, or Ring is connected to
ground, or both. The most common fault is Ring to ground.

CODEC - Coder/Decoder - Interfacing between the SUC
and the digital switch, it converts the SUC's transmit signal to
digital, and converts the digital receive signal to analog.

FOUR WIRE CIRCUIT - The portion of a telephone, or
central office, which operates on two pairs of wires. One pair
is for the transmit path, and one pair is for the receive path.

dB - A power or voltage measurement unit, referred to
another power or voltage. It is generally computed as:
10 • log (P1 / P2) for power measurements, and
20. log (V1 / V2) for voltage measurements.

FULL DUPLEX - A transmission system which permits
communication in both directions simultaneously. The standard handset telephone system is full duplex.

dBm - An indication of signal power. 1.0 mW across 600 Q,
or 0.775 Vrms, is defined as a dBm. Any other voltage level is
converted to dBm by:
dBm = 20. log (Vrms/0.775), or
dBm = [20 • log (Vrms)] + 2.22.

GAIN - The change in signal amplitude (increase or
decrease) after passing through an amplifier, or other circuit
stage. Usually expressed in dB, an increase is a positive
number, and a decrease is a negative number.

MC33121
2-290

MOTOROLA COMMUNICATIONS DEVICE DATA

HALF DUPLEX - A transmission system which permits
communication in one direction at a time. CB radios, with
"push-to-talk" switches, and voice activated speakerphones,
are half duplex.
HOOKSWITCH - A switch, within the telephone, which
connects the telephone circuit to the subscriber loop. The
name derives from old telephones where the switch was
activated by lifting the receiver off and onto a hook on the side
of the phone.
HYBRID -

Another name for a two-to-four wire converter.

IDLE CHANNEL NOISE - Residual background noise when
transmit and receive Signals are absent.
LINE CARD - The PC board and circuitry in the CO or PBX
which connects to the subscriber's phone line. A line card may
hold circuitry for one subscriber, or a number of subscribers.
LONGITUDINAL BALANCE - The ability of the SLiC to
reject longitudinal signals on Tip and Ring.
LONGITUDINAL SIGNALS -

Common mode signals.

LOOP - The loop formed by the two subscriber wires (Tip
and Ring) connected to the telephone at one end, and the
central office (or PBX) at the other end. Generally, it is a
floating system not referred to ground, or AC power.
LOOP CURRENT - The DC current which flows through the
subscriber loop. It is typically provided by the central office or
PBX, and ranges from 20 to 120 mA.
OFF-HOOK - The condition when the telephone is connected to the phone system, permitting the loop current to
flow. The central office detects the DC current as an indication
that the phone is busy.
ON-HOOK - The condition when the telephone is disconnected from the phone system, and no DC loop current flows.
The central office regards an on-hook phone as available for
ringing.
PABX - Private Automatic Branch Exchange. In effect, a
miniature central office, it is a customer owned switching
system servicing the phones within a facility, such as an office
building. A portion of the PABX connects to the Bell (or other
local) telephone system.
PROTECTION, PRIMARY - Usually conSisting of carbon
blocks or gas discharge tubes, it absorbs the bulk of a lightning
induced transient by clamping the voltages to less than
±1500 V.
PROTECTION, SECONDARY - Usually located on the line
card, it protects the SUC and associated circuits from
transient surges. Typically, it must be capable of clamping a
±1.5 kV surge of 1.0 ms duration.
PULSE DIALING - A dialing system whereby the loop
current is interrupted a number of times in quick succession.
The number of interruptions corresponds to the number
dialed, and the interruption rate is typically 10 per second. The
old rotary phones, and many new pushbutton phones, use
pulse dialing.
RECEIVE PATH - Within the CO or PBX it is the speech
path from the internal switching system towards the phone
line (Tip & Ring).

MOTOROLA COMMUNICATIONS DEVICE DATA

REN - Ringer Equivalence Number. An indication of the
impedance or loading factor of a telephone bell or ringer
circuit. An REN of 1.0 equals ~8.0 kQ. The Bell system
typically permits a maxirnum of 5.0 REN (1.6 kQ) on an
individual subscriber line. A minimum REN of 0.2 (40 kQ) is
required by the Bell system.
RETURN LOSS - Expressed in dB, it is a measure of how
well the SUC's AC impedance matches the line's AC
characteristic impedance. With a perfect match, there is no
reflected signal, and therefore infinite return loss. It is
calculated from:
RL = 20 • log (lUne + lCKT)
(lUne - lCKT)
RING - One of the two wires connecting the central office to
a telephone. The name derives from the ring portion of the
plugs used by operators (in older equipment) to make the
connection. Ring is traditionally negative with respect to Tip.
SLIC - Subscriber Une Interface Circuit. It is the circuitry
within the CO or PBX which connects to the user's phone line.
SUBSCRIBER - The customer at the telephone end of the
line.
SUBSCRIBER LINE - The system consisting of the user's
telephone, the interconnecting wires, and the central office
equipment dedicated to that subscriber (also referred to as a
loop).
TIP - One of the two wires connecting the central office to a
telephone. The name derives from the tip of the plugs used by
operators (in older equipment) to make the connection. Tip is
traditionally positive with respect to Ring.
TRANSHYBRID REJECTION - The rejection (in dB) of the
reflected signal in the transmit path resulting from a receive
signal applied to the SUC.
TRANSMIT PATH - Within the CO or PBX it is the speech
path from the phone line (Tip & Ring) towards the internal
switching system.
TWO WIRE CIRCUIT - Refers to the two wires connecting
the central office to the subscriber's telephone. Commonly
referred to as Tip and Ring, the two wires carry both transmit
and receive signals in a differential manner.
TWO-TO-FOUR WIRE CONVERTER - A circuit which has
four wires (on one side) - two (signal & ground) for the
outgoing signal, and two for the incoming signal. The outgoing
signal is sent out differentially on the two wire side (the other
side), and incoming differential signals received on the two
wire side are directed to the four wire side. Additional circuit
within cancels the reflected outgoing signal to keep it separate
from the incoming signal.
VOICEBAND - That portion of the audio frequency range
used for transmission across the telephone systern. Typically,
it is 300 to 3400 Hz.

MC33121
2-291

MC33178
MC33179

MOTOROLA

SEMICONDUCTOR-----TECHNICAL DATA

High Output Current Low Power,
Low Noise Bipolar Operational
Amplifiers
The MC33178/9 series is a family of high quality monolithic amplifiers
employing Bipolar technology with innovative high performance concepts for
quality audio and data signal processing applications. This device family
incorporates the use of high frequency PNP input transistors to produce
amplifiers exhibiting low input offset voltage, noise and distortion. In addition, the
amplifier provides high output current drive capability while consuming only
420 J.lA of drain current per amplifier. The NPN output stage used, exhibits no
deadband crossover distortion, large output voltage swing, excellent phase and
gain margins, low open-lOOp high frequency output impedance, symmetrical
source and sink AC frequency performance.
The MC33178/9 family offers both dual and quad amplifier versions, tested
over the vehicular temperature range. These devices are available in DIP and
SOIC packages.

HIGH OUTPUT CURRENT
LOW POWER, LOW NOISE
OPERATIONAL AMPLIFIERS

DUAL

.~

PSUFFIX
PLASTIC PACKAGE
CASE 626

1

DSUFFIX
PLASTIC PACKAGE
CASE 751
(SO-8)

8~
1

• 600 Q Output Drive Capability
o Large Output Voltage Swing
• Low Offset Voltage: 0.15 mV (Mean)
• Low T.C. of Input Offset Voltage: 2.0 J.lvrC
• Low Total Harmonic Distortion: 0.0024%
(@ 1.0 kHz w/600 Q Load)
• High Gain Bandwidth: 5.0 MHz

PIN CONNECTIONS
Outpull

, Vee

1

7

Output 2

Inpuls I { :
VEE

• High Slew Rate: 2.0 V/J.lS
• Dual Supply Operation: ±2.0 V to ±18 V
• ESD Clamps on the Inputs Increase Ruggedness
without Affecting Device Performance

: } Inputs 2
4

(Top View)

Equivalent Circuit Schematic (Each Amplifier)

QUAD
PSUFFIX
PLASTIC PACKAGE
CASE 646
DSUFFIX
PLASTIC PACKAGE
CASE 751A
(SO-I 4)

PIN CONNECTIONS

ORDERING INFORMATION
OpAmp
Function

Fully
Compensated

Dual

MC33178D
MC33178P

Quad

MC33179D
MC33179P

MC33178·MC33179
2·292

Temperature
Range

Package
SO-8
Plastic DIP

-40° to +85°C

SO-14
Plastic DIP

MOTOROLA COMMUNICATIONS DEVICE DATA

MAXIMUM RATINGS
Rating

Symbol

Value

Unit

Vs

+36

V

VIDR

(Note 1)

V

Input Voltage Range

VIR

(Note 1)

V

Output Short Circuit Duration (Note 2)

tsc

Indefinite

sec
°c

Supply Voltage (VCC to VEE)
Input Differential Voltage Range

Maximum Junction Temperature

TJ

+150

Storage Temperature Range

Tstg

-60 to +150

°C

Maximum Power Dissipation

PD

(Note 2)

mW

DC ELECTRICAL CHARACTERISTICS (VCC = +15 V, VEE = -15 V, TA = 25°C, unless otherwise noted.)
Figure

Symbol

Input Offset Voltage (RS = 50 n, VCM = 0 V, Va = 0 V)
(VCC = +2.5 V, VEE = -2.5 V to VCC = +15 V, VEE = -15 V)
TA=+25°C
TA = -40° to +85°C

Characteristics

2

IVIOI

Average Temperature Coefficient of Input Offset Voltage
(RS = 50 n, VCM = 0 V, Va = 0 V)
TA = -40° to +85°C

2

I!NIO/AT

3,4

liB

Input Bias Current (VCM = 0 V, Va = 0 V)
TA=+25°C
TA = -40° to +85°C
Input Offset Current (VCM = 0 V, Va = 0 V)
TA = +25°C
TA = -40° to +85°C
Common Mode Input Voltage Range
(AVIO = 5.0 mV, Va = 0 V)
Large Signal Voltage Gain (Va = -10 V to +10 V, RL = sao n)
TA = +25°C
TA = -40° to +85°C
Output Voltage Swing (VID = ±1.0 V)
(VCC = +15 V, VEE = -15 V)
RL=300n
RL=300n
RL=SOOn
RL=SOOn
RL=2.0kn
RL = 2.0 kn
(VCC = +2.5 V, VEE = -2.5 V)
RL=600n
RL=SOOn

11101

Min

Typ

Max

-

0.15

3.0
4.0

mV

6,7

VICR
AVOL

-

!lV/oC

-

2.0

-

100

-

-

500
600

-

5.0

50
60

-13

-14
+14

+13

200 k

-

5

Unit

-

50 k
25 k

nA

nA

-

-

-

V
VN

-

8,9,10

V
VO+
VoVO+
VoVO+
Vo-

+12
-

+13

-

VO+
Vo-

1.1

-

+12
-12
+13.S
-13
+14
-13.8

-

-12

-13

-

1.6
-1.6

-1.1

Common Mode Rejection (Vin = ±13 V)

11

CMR

80

110

-

dB

fower Supply Rejection
, VCcNEE = +15 V/-15 V, +5.0 V/-15 V, +15 V/-5.0 V

12

PSR

80

110

-

dB

Output Short Circuit Current (VID = ±1.0 V, Output to Ground)
Source (VCC = 2.5 V to 15 V)
Sink (VEE = -2.5 V to -15 V)

13,14

ISC
+50
-50

+80
-100

-

Power Supply Current (Va = 0 V)
(VCC = 2.5 V, VEE = -2.5 V to VCC = +15 V, VEE = -15 V)
MC33178 (Dual)
TA=+25°C
TA = -40° to +85°C
MC33179 (Quad)
TA= +25°C
TA = -40° to +85°C

15

rnA

rnA

ID

-

-

-

1.4
1.S

-

1.7

2.4
2.6

-

-

NOTES: 1. Either or both Input voltages should not exceed VCC or VEE.
2. Power dissipation must be considered to ensure maximum junction temperature (TJ) is not exceeded. (See power dissipation
performance characteristic, Figure 1.)

MOTOROLA COMMUNICATIONS DEVICE DATA

MC3317S.MC33179
2-293

AC ELECTRICAL CHARACTERISTICS (VCC = +15 V, VEE = -15 V, TA = 25°C, unless otherwise noted.)
Characteristics
Slew Rate
(Vin =-10Vto+l0 V, RL=2.0 ko, CL= 100 pF, AV= +1.0 V)

Figure

SymbDI

Min

Typ

Max

Unit

16,31

SR

1.2

2.0

V/p.s

17

GBW

2.5

5.0

18,19

AVO

-

50

-

Gain Bandwidth Product (I = 100 kHz)
AC Voltage Gain (RL = 600 D, Vo = 0 V, 1= 20 kHz)
Unity Gain Frequency (Open-Loop) (RL = 600 0, CL = 0 pF)

IU

Gain Margin (RL = 600 0, CL = 0 pF)

20,22,23

Am

Phase Margin (RL = 600 0, CL = 0 pF)

21,22,23

~

Channel Separation (I = 100 Hz to 20 kHz)

24

CS

Power Bandwidth (VO = 20 Vp_p, RL = 600 0, THO S; 1.0%)

BWp

Distortion (RL = 600 0" Vo = 2.0 Vp_p, AV = +1.0 V)
(1= 1.0 kHz)
(1= 10 kHz)
(1=20 kHz)

25

Open-Loop Output Impedance
(VO= 0 V, 1=3.0 MHz, AV= 10V)

26

THO

200

en

-

8.0
7.5

In

-

0.33
0.15

RIN

28

~

Z

o

~

!!;

~

Figure 1. Maximum Power Dissipation
versus Temperature
2400

is

~

::E 1200

800 MC

~

400

rP

0

~O

~178

"

-40 -20

.......

"

....... ....

2.0
1.0

Iii

0

-"

5
IL

.........

='"

~

"" ~
.........
I"'CIII

0 20 40 60 80 100 120 140 160 180
TA, AMBIENTTEMPERATURE (OC)

MC3317S.MC33179
2-294

~

~
0

.......

3.0

g

!::l

~331r9i3'- :-......

i~

10

dB
Degrees
dB
kHz
%

D
kD
pF
nV/fHz

pA/fHz

Figure 2. Input Offset Voltage versus
Temperature for 3 Typical Units

~
w

I"""'J

io-.

150

dB
MHz

4.0

I

2000 ~C33118PI9

a: 1600

32

-

llal

CIN

Equivalent Input Noise Current
1= 10 Hz
1= 1.0kHz

-120

0.0024
0.014
0.024

Differential Input Capacitance (VCM = 0 V)
27

15
60

-

Differential Input Resistance (VCM = 0 V)
Equivalent Input Noise Voltage (RS = 100 0,)
1=10Hz·
1= 1.0kHz

3.0

MHz

~

UnHI

VCC=+15V
VEE=-15V RS=10D
VCM=OV

-

UnH2
UnU

-1.0
-2.0
-3.0

-4.~

-25

0
25
50
75
TA, AMBIENTTEMPERATURE (OC)

100

125

MOTOROLA COMMUNICATIONS DEVICE DATA

Figure 4. Input Bias Current
versus Temperature

Figure 3. Input Bias Current
versus Common Mode Voltage
120

160

1

1\
140

zw 120

0:
0:

::::>
0

--- ---- -

'--

I-

100

(J)

«

ii'i

80

I0..

o

-15

-10

-

0

10

./

./"

90

en

«

./

ii'i
I-

::::>

80

0..

~

70

./

-

60
-55

15

V
./

-25

0
25
50
75
TA, AMBIENT TEMPERATURE ('C)

100

125

Figure 6. Open-Loop Voltage Gain
versus Temperature

Figure 5. Input Common Mode Voltage
Range versus Temperature

~

.....

./"

::::>

Q:l

-5.0
0
5.0
VCM, COMMON MODE VOLTAGE (V)

VCC=+15V
VEE=-15V
VCM=OV

100

0:
0:

I

20

110 -

zw

I-

60 I- VCC=+15V
VEE =-15 V
~
40 I - TA=25'C
~
::::>

1

w



0..
I-

15

::::>

o. 10
o

> 5.0

V

RL =600n

~r

~

V"

~

5.0
10
15
VCC, IVEEI, SUPPLY VOLTAGE (V)

20

MC33178.MC33179

2-295

Figure 9. Output Saturation Voltage
versus Load Current
VCC

~

I

~

r=--

g

I - - TA =-55·C

w

!j VCC-l.0V

Figure 10. Output Voltage
versus Frequency
28

Source

TA=+l25·C

~24

~ VCC-2.0V

!3

!j 16

rI

,
i:i VEE +2.0 V -Sink

g

!3

.2:::

}

VCC=+15V
VEE=-15V
RL=600n
AV=+1.0V
THD=sl.0%
TA=25·C

§ B.O -_
~4.0

VCC=+5.0Vto+1BV
VEE=-5·0VIo-1BV

TA=+l25·C

I
5.0

12 _

D..

--TA=-55·

5o VEE +100 V

\

~

J

~
~

\

~2O
w

J

z

10
15
IL. LOAD CURRENT (:!mA)

-

o

10k

1.0k

20

120

vJcI11~~~

.....
r-...

AVCM~AVO
o

III

i

100

VEE=-15V
VCM=OV
6VCM=±1.5V
TA=-55· 10 +125·C

~
D..

~

~-

II:

If

lOOk

100M

-r-

I
II

~

--

I
I
I
20
II

40

~

0
-15

VCC=+15V
VEE=-15V

20

AVO

TA=-55· 10 +125·C
VCC=+15V
VEE=-15V
j'o.6VCC=±1.5V

i'

I'

VEE

r-..

AVotAOM
PSR=2!l.og ( - -)
AVCC

o

100

1.0k
10k
f. FREQUENCY (Hz)

lOOk

100M

Figure 14. Output Short Circuit Current
versus Temperature

-9.0

-3.0
0
3.0
VO. OUTPUT VOLTAGE (V)

~

"""

90
BO

(3

I'-....

i--

I---

Ii:

I
15

~

-

........ ~
f.,..,:"..

-

~

'" ,
~ t-...

60
50-55

,I
.1.
VCC=+15VVEE=-15V _
VID=±1.0V
RL < Ion

Sink

Sour~

~ 70

\
9.0

~

!::

\

Vr±lr

MC3317S.MC33179

2-296

~i~k- -

I'"

(3

~

-=

10

Ia

So rca

60

1.0M

.§. 100

~
II:

~

.AOM

:;c-

1100

u
!::

~

60

~ 40

.....

P~~

'"

~ BO

Figure 13. Output Short Circuit Current
versus Output Voltage

§ BO

Js~

t5w

i'.

1.0k
10k
f. FREQUENCY (Hz)

120

i5100

AVCM
CMR =2!l.og ( - xAOM )
AVO

10

.... ~

lOOk
f. FREQUENCY (Hz)

Figure 12. Power Supply Rejection
versus Frequency Over Temperature

Figure 11. Common Mode Rejection
versus Frequency Over Temperature

i

.......

-25

0
25
50
75
TA. AMBIENT TEMPERATURE (·C)

100

.....
125

MOTOROLA COMMUNICATIONS DEVICE DATA

Figure 16. Normalized Slew Rate
versus Temperature

Figure 15. Supply Current versus Supply
Voltage with No Load
~625

M! 500

/'
IV
II
1/

1375
w
a:
250

a

g; 125

'"g

-

I
!
TA=+125°C

a:

~
Q.

1.15

,

-

-

Tr+25°1
_I
TA = -55°C

!;i

~

0.95

~ 0.90

1il 0.85

gj
M

U

ro

M

M

~

re

0.80

V

/

/

0.75
-55

re

50

10

I-

~ 8.0

~

~

-

~ 6.0

b

§:

C!l

>. -20 >
< -30

-

-40
75

100

-50
lOOk

125

VCC=+15V
VEE=-15V
RL= 600 n
TA = 25°C
CL=OpF

lD 30

~ 20

1ii
w

10

~ 0
El-l0

>

1"= ~

-

TA = 25°C
RL=oo
CL=OpF

.......... I'~

I'"

2B r-;

"p.

r\

}

~

,; -20 lA) Phase VCC =18 V, VEE=-18 V
~r-< -30 2A) Phase VCC 1.5 V, VEE =-1.5 V
lB) Gain VCC = 18 V, VEE = -18 V
~
-40
2B) Gain VCC= 1.5 V, VEE=-1.5 V
-50
lOOk
100M
10M
f, FREQUENCY (Hz)

\ 1\

MOTOROLA COMMUNICATIONS DEVICE DATA

160 ;;;

180~

1\

200~

~
, ..... 1"-

'"

220~

24Oi\S.

,

1.0M

15

80
100
120
160

~

'""""

260

-e-

280
100M

10M

Figure 20. Open-Loop Gain Margin
versus Temperature

140

1

fIT

120 w

f, FREQUENCY (Hz)

Figure 19. Voltage Gain and Phase
versus Frequency

~

125

80
100

II 1111

TA, AMBIENT TEMPERATURE (OC)

40

100

ain

o

:g

50

I
75

Moffi

10

0
!j -10

(-VCC=+15V
VEE=-15V
(-f=100kHz
z
1ii 2.0 (-RL=600n
CL=OpF

50

I
50

.....

~

4.0

25

I
25

l00pF

= =1

_Ph se

30

lD
:E.. 20

-25

I
0

+, 600n

.....

40

~

0
-55

I
l~F

J1- T .
I:

Ml

~
g
w

20
18

Inpul Noise Voliage Test Circuli

16
14

Va

fr

12

5z

10
c 8.0

i'l!
a:

tb

6.0

a: 4.0
2.0

~
~

.

c

Figure 28. Input Referred Noise Current
versus Frequency

Figure 27. Input Referred Noise Voltage
versus Frequency

0'0

l!
!

!z
i'l!
a:

S!
c
w

ffi

TA=~~,~
10k

Figure 29. Percent Overshoot versus
Load Capacitance
100

vc~=l,~J

90 I80 r- VEE=-15V
TA = 25°C
~
70

l5
0
:J:
UJ

a:

w

R =6000

,

1:5 40

!z
w
<>
a:
w
0..

30
20

/

(RS= IOkn)

~
~

0
10

~Ai~~~1I1I
100

1.0k
t, FREQUENCY (Hz)

10k

lOOk

I
I

V
/;

'

• • 11

II,

/
/

~

VCC=+15V
VEE=-15V

0.1

•

/

/

50

~

0.2

Figure 30. Nonlnvertlng Amplifier Slew Rate

1/

60

~.,

0.4

a:
a:

10k

:n~ul ~Ol~! b~~~nl ~e~t d;rc:,i: I

~

It
1.0k
t, FREQUENCY (Hz)

11111

G
0.3
w

VCC=+15V
VEE=-15V
100

0.5

/
Yi '

RL=2.0kn

"

/1:

!:

:

I

:

/:

....

1

100
1.0k
CL, LOAD CAPACITANCE (PF)

Figure 31. Small Signal Transient Response

10k

I

I, TIME (2.0 J!s/DIV)

Figure 32. Large Signal Transient Response

I, TIME (2.0 nsJDIV)

I, TIME (5.0 IlsIDlV)

Figure 33. Telephone Line Interface Circuit

MOTOROLA COMMUNICATIONS DEVICE DATA

MC33178.MC33179
2-299

To
Receiver

10k

~---~I----<

J

10k
1.01lF

200k
120k

0.051lF

300

From
2.0k
Microphone _---"N'v.---1lI----t

820

J\~P

lN4678

10k

IIV:""

APPLICATION INFORMATION
This unique device uses a boosted output stage to combine
a high output current witlJ a drain current lower than similar
bipolar input op amps. Its 60° phase margin and 15 dB gain
margin ensure stability with up to 1000 pF of load capacitance
(see Figure 23). The ability to drive a minimum 600 D load
makes it particularly suitable for telecom applications. Note
that in the sample circuit in Figure 33 both A2. and A3 are
driving equivalent loads of approximately 600 D .
The low input offset voltage and moderately high slew rate
and gain bandwidth product make it attractive for a variety of
other applications. For example, although it is not single
supply (the common mode input range does not include
ground), it is specified at +5.0 V with a typical common mode
rejection, of 110 dB. This makes it an excellent choice for use
with digital circuits. The high common mode rejemion, which
is stable overtemperature, coupled with a low noise figure and
low distortion is an ideal,op' amp lor audio circuits.
The output stage of the op amp is current limited and
therefore has a certain amount of protection in the event of a
short circuit. However, because of its high current output, it is
especially importanl not to allow the device to exceed the
maximum junction te,mperature, particularly with the
MC33179 (quad op amp). Shorting more than one amplifier

MC3317S.MC33179

2·300

could easily exceed the junction temperature to the extent of
causing permanent damage.
Stability

As usual with most high frequency amplifiers, proper lead
dress, component placement, and PC board layout should be
exercised for optimum frequency performance. For example,
long unshielded input or oulputleads may result in unwanted
inpuVoutput coupling. In order to preserve the relatively
low input capacitance associated with these amplifiers,
resistors connected to the inputs should be Immediately
adjacent to the input pin to minimize additional stray input
capacitance. This not only minimizes the input pole frequency
for optimum frequency response, but also minimizes
extraneous "pick up· at this node. Supplying decoupling with
adequate capacitance immediately adjacent to the supply pin
Is also important, particularly over temperature, since many
types of decoupling capacitors exhibit great impedance
changes over temperature.
Additional stability problems can be caused by high load
capacitances and/or a high source resistance. Simple
compensation schemes can be used to alleviate these effects.

MOTOROLA COMMUNICATIONS DEVICE DATA

If a high source of resistance is used (R1 > 1.0 kn). a
compensation capacitor equal to or greater than the input
capacitance olthe op amp (10 pF) placed across the feedback
resistor (see Figure 34) can be used to neutralize that pole and
prevent outer loop oscillation. Since the closed loop transient
response will be a function of that capacitance it is important
to choose the optimum value for that capacitor. This can be
determined by the following formula:
(1)

Cc

For moderately high capacitive loads (500 pF < CL <
1500 pF) the addition of a compensation resistor on the order
of 20 n between the output and the feedback loop will help to
decrease miller loop oscillation (see Figure 35). For high
capacitive loads (CL > 1500 pF) a combined compensation
scheme should be used (see Figure 36). Both the
compensation resistor and the compensation capacitor affect
the transient response and can be calculated for optimum
performance. The value of Cc can be calculated using formula
(1). The formula to calculate RC is as follows:

=(1 +[R1/R2])2. CL (Zo/R2)

where: Zo is the output impedance of the op amp.

(2)

RC

Figure 34. Compensation for
High Source Impedance

=Zo • R1/R2

Figure 35. Compensation Circuit for
Moderate Capacltve Loads

R2

R2

Cc

RC
R1
R1

Figure 36. Compensation Circuit for
High Capacitive Loads

R2

Cc

RC
R1

MOTOROLA COMMUNICATIONS DEVICE DATA

MC33178.MC33179
2-301

MOTOROLA

MC33218

SEMICONDUCTOR-----TECHNICAL DATA

Advance Information
Voice Switched Speakerphone
with Microprocessor Interface
The Motorola MC33218 Voice Switched Speakerphone Circuit incorporates
the necessary amplifiers, attenuators, level detectors, and control algorithm to
form the heart of a high quality, hands-free speakerphone system. Included are
a microphone amplifier with mute, transmit and receive attenuators, a background
monitoring system for both transmit and receive paths, and level detectors for
each path. An AGC system reduces the receive gain on long lines where loop
current and power are in short supply. A dial tone detector prevents loss of dial
tone.
Additionally, the MC33218 has a serial data port which allows microprocessor
,control of various functions such as volume control, mute, attenuator range selection, and selection of receive, transmit, idle, or normal mode. The data port can
be operated up to 1.0 MHz.
The MC33218 is available in a 24 pin, narrow body DIP, and a wide body SOIC
package.
• Supply Voltage Range: 2.5 to 6.5 V
• Attenuator Range: 52 dB or 26 dB (Selectable)
• Background Noise Monitor for Each Path
• Microphone Amplifier with Mute Function
• 2 Point Signal Sensing
• Microprocessor Port for 8-bit Serial Data Entry Controls:
• Digital Volume Control (16 Steps)
• Attenuator Range Selection (52 dB or 26 dB)
• Mute Microphone Amplifier
• Force to Receive, Transmit, Idle, or Normal Operating Mode
• Chip Deselect Pin Powers Down Entire IC

VOICE SWITCHED
SPEAKERPHONE with
~PROCESSORINTERFACE

-PW~

PLASTIC PACKAGE
CASE 724

1

DWSUFFIX
PLASTIC PACKAGE
CASE 751E
(SO-24L)

PIN CONNECTIONS

Simplified Block Diagram

CP2

Vee

XDl

TAO

CPT

MCO

TLI

MCI

TLO

POR

VB

DR

Cr
CD
NC

ClK

CPR

RXO

DIN
RXI

RLI

RAO

RLO

GND
(Top View)

ORDERING INFORMATION
Device
MC3321BDW
MC33218P

Temperature
Range
- 40° to + 85°C

Package
SO-24L
Plastic DIP

This document contains Information on a new product. Specifications and In!onmatlon herein are sublect to change without notice.

MC33218
2-302

MOTOROLA COMMUNICATIONS DEVICE DATA

MAXIMUM RATINGS
Characteristic

Symbol

Supply Voltage
Maximum Junction Temperature
Storage Temperature Range

Min

Max

Unit

VCC

-0.5

+7.0

Vdc

TJ

-

+150

·C

Tstg

-65

+150

·C

Devices should not be operated at or outside these values. The "Recommended OperaUng Umlts" table
provides for actual device operaUon.

RECOMMENDED OPERATING LIMITS
Symbol

Min

Typ

Max

Unit

VCC

3.5
2.5

6.5
6.5

Vdc

Maximum Attenuator Input Signal

Vln(max)

-

350

mVrms

Clock and Data Rate (Serial Port)

FData

0

-

1.0

MHz

Characteristic
Supply Voltage

(Non-AGC Range)
(AGCRange)

Operating Temperature Range

TA

-40

+85

·C

ELECTRICAL CHARACTERISTICS (TA = 25·C, VCC = 5.0 V, CD S 0.8 V, fCLK = 1.0 MHz, unless otherwise noted.)

I

I Symbol I

Characteristic

Min

I

Typ

I'

Max

Unit

POWER SUPPLY
Supply Current (Enabled, CD = 0)
Idle Mode
Receive Mode
Transmit Mode

ICC

Supply Current (Disabled, CD = 1)

ICC

CD Input Resistance
VB Output Voltage (IVB = 0)
VB Output Resistance

,

rnA
3.0

4.0
5.0
5.0
50

85

IIA

RCD

170

250

300

kQ

VB

2.1

2.2

2.3

Vdc

ROVB

-

300

-

-

+150
0
-105

-

-

6.0

-

W

ATTENUATOR CONTROL
CT Voltage (Full Attenuation Range)
RxMode
Idle Mode
TxMode

VCT-VB

CrCurrent
Source (Switching to Rx Mode)
Sink (Switching to Tx Mode)
Idle

ICTR
ICTT
lerl

Receive Dial Tone Detector Threshold

VDT

MOTOROLA COMMUNICATIONS DEVICE DATA

-55

65
-3.0
-40

-40
85
0
-20

-25
115
3.0
-8.0

mV

IIA

mV

MC33218
2-303

ELECTRICAL CHARACTERISTICS (TA

I

= 25°C, VCC =5.0 V, COSO.8 V, fCLK =1.0 MHz, unless otherwise noted.)

Characteristic

I Symbol I

Min

I

Typ

I

Max

Unit

ATTENUATORS

=

Receive Attenuator Gain (f 1.0 kHz)
Full Volume, Full Attenuation Range
RxMode
Tx Mode
Idle Mode
Range (Rx to T x Mode)
Full Volume, Half Attenuation Range
Rx Mode
Tx Mode
Idle Mode
Range (Rx to T x Mode)
Volume Control Range (Rx Mode)
AGC Attenuation Range (VCC

=3.5 to 2.7 V)

RAO Offset Voltage With Respect to VB
(Rx Mode)
(Tx Mode)
Transmit Attenuator Gain (f
Full Attenuation Range
TxMode
RxMode
Idle Mode
Range (Tx to Rx Mode)
Half Attenuation Range
TxMode
RxMode
Idle Mode
Range (Tx to Rx Mode)

RAO, TAO
High Voltage (IL
1.0 rnA)
Low Voltage (IL = +1.0 rnA)

=-

Open Loop Gain (f < 100 Hz)
Gain Bandwidth

==

Output High Voltage (lout
1.0 rnA)
Output Low Voltage (lout + 1.0 rnA)
Transmit Path Muting (4 Gain) Pin 21 to Pin 23
Microphone Amp (RFdbk 300 kO), plus Transmit Attenuator in Rx Mode

=

6.0
-46
-25
52

9.0
-43
-22
55

GRX
GRXT
GRXI
4GRX

-10
-37
-28
23

-7.0
-34
-25
26

-4.0
-31
-22
29

VCR

31

37

41

GAGC

-

6.0

-

dB

VRAO

-

-10
0

-

dB
dB
mVdc

-

dB
GTX
GTXR
GTXI
4GTX

3.0
-49
-19
49

6.0
-46
-16
52

9.0
-43
-13
55

GTX
GTXR
GTXI
4GTX

-9.0
-36
-19
23

-6.0
-33
-16
26

-3.0
-30
-13
29

VTAO

-

0
-60

3.7
VB-1.0

4.1
VB-1.4

80

GBW

-

0.8

VMCOH
VMCOL

3.7
0

4.1
140

80

125

VTAOH
VTAOL

-

mVdc

-

-

Vdc

VB-3.0

MCOVOS
AVOL

0

250

GMT

mVdc
dB
MHz
Vdc
mVdc
dB

-

Receive Amplifier

DC Voltage (Rx Mode)

VRXO

==

Output High Voltage (lout
1.0 rnA)
Output Low Voltage (lout +1.0 rnA)

MC33218
2-304

3.0
-49
-28
49

Microphone Amplifier

Output Offset with Respect to VB

AMPLIFIERS -

GRX
GRXT
GRXI
4GRX

=1.0 kHz)

TAO Offset Voltage With Respect to VB
(RxMode)
(Tx Mode)

AMPLIFIERS -

dB

VRXOH
VRXOL

-

VB

3.7

4.0
100

-

-

250

Vdc
Vdc
mVdc

MOTOROLA COMMUNICATIONS DEVICE DATA

ELECTRICAL CHARACTERISTICS ( TA = 25°C, VCC = 5.0 V, CD S 0.8 V, fCLK = 1.0 MHz, unless otherwise noted.)

I

Characteristic

I Symbol I

Min

ITH

0.8

I

Typ

I

Max

Unit

I'AlI'A

LEVEL DETECTORS AND BACKGROUND NOISE MONITORS
Transmit/Receive Switching Threshold

1.0

1.2

5.0

-

W

-0.1

-

I'A

CPR, CPT Leakage Current

ICPLK

-

Tx and Rx Level Detector
Source Current
Sink Current

ILDOH
ILDOL

-

-2.6
2.0

POR Input Resistance

RpOR

70

Data In/Clock Input Resistance
(High) Vin = 5.0 V
(Low) Vin = 0.9 V

RCLK
35
70

Data Ready Input Resistance
(High) Vin = 5.0 V
(Low) Vin = 0.9 V

RDR

Logic Input Threshold

CPR, CPT Output Resistance

RCp

-

-

mA
I'A

115

160

kQ

55
120

85
160

10
25

20
45

30
65

VTH

-

1.5

-

V

THOR

-

0.3

3.0

%

THDT

-

0.3

3.0

CLOCK AND DATA

kQ

kQ

SYSTEM
Rx Mode Distortion
Rx Amplifier and Attenuator
(I = 1.0 kHz, Vin = 350 mVrms)
Tx Mode Distortion
Tx Attenuator and Microphone Amplilier
(1= 1.0 kHz, Vin = 3.5 mVrms)

TEMPERATURE CHARACTERISTICS (VCC = 5.0 V, CD -< 0.8 V, ICLK = 1.0 MHz, unless otherwise noted.)
Typical
Value
@-40°C

Typical
Value
@ + 25°C

Typical
Value
@ +85°C

VCC Supply Current
Idle Mode (Enabled, CD = 0)
All Modes (Disabled, CD = 1)

4.7
60

4.2
50

3.7
75

VB

2.1

2.2

2.3

Parameter

Receive Attenuator Range (I = 1.0 kHz) Full Volume
Full Attenuation Range
Hall Attenuation Range

52
26

52
26

53
27

Transmit Attenuator Range (I = 1.0 kHz)
Full Attenuation Range
Hall Attenuation Range

52
26

52
26

53
27

Transmit Path Muting (8 Gain; Pin 21 to 23)
Microphone Amp (RFdbk = 300 kQ), plus Transmit Attenuator in Rx Mode

128

127

128

Volume Control Range (Rx Mode)

34

36

40

MOTOROLA COMMUNICATIONS DEVICE DATA

Unit
mA

I1A
V
dB

dB

dB
dB

MC33218
2-305

PIN FUNCTION DESCRIPTION
Name

Pin No.

CP2

1

Description
A capacitor at this pin stores a voltage representing the transmit background noise level.

XDI

2

Input to the transmit background noise monitor.

CPT

3

An RC sets the time constant for the transmit background noise monitor.

TLI

4

Input to the transmit level detector.

TLO

5

Output of the transmit level detector.

VB

6

A reference voltage, and analog ground for the amplifiers.

CT

7

An RC sets the response time to switch among the various modes.

CD

8

Chip deselect (Logic input). When low, the IC Is active. When high, the entire IC Is powered
down and non·functlonal.

NC

9

No intemal connection.

CPR

10

An RC sets the time constant for the receive background noise monitor.

RLI

11

Input to the receive level detector.

RLO

12

Output of the receive level detector.

GND

13

Ground pin for the entire IC.

RAO

14

Output of the receive attenuator.

RXO

15

Output of the receive path input ampllfler, and Input of the receive attenuator.

RXI

16

Inverting Input of the receive path Input amplHier.

CLK

17

Serial Port Clock. 1.0 MHz maximum, data Is entered on clock's rising edge.

DIN

18

Serial Port Data Input. Enter an 8-bit word, B7 first, BO last.

DR

19

Serial Port Data Ready. Taking this line high latches new data in the registers.

POR

20

Power On Reset. Upon power up and/or enabling, all bits are set to O.

MCI

21

Inverting input of the microphone amplifier.

MCO

22

Output of the microphone amplifier, and Input of the transmit attenuator.

TAO

23

Output of the transmit attenuator.

Vce

24

Power Supply pin. Operating range Is 2.5 V to 6.5 Vdc.

Bits

Code

B7,B6

00
01
10
11

Normal voice switched operation.
Force to receive mode.
Force to idle mode.
Force to transmit mode.

B5

a

Attenuator range is 52 dB.
Attenuator range is 26 dB.

1

MC33218
2-306

Function

Bits

Code

B4

0
1

83-

0000
1111

BO"

Function
Microphone amplifier Is active.
Microphone amplHier is mute.
Maximum receive volume.
Minimum receive volume.

"BII BO Is Ihe LSB for Ihe volume control.

MOTOROLA COMMUNICATIONS DEVICE DATA

Figure 1. Serial Port Timing Diagram

Cloc
k
Data
In
Data
Ready

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _-'---'Fdtt

NOTES: 1. Maximum clock and data rate Is 1.0 MHz. There Is no required minimum rate.
2. B7 Is to be entered first, BO last.

3.
4.
5.
6.

Data Is entered on the clock rising edge.
Clock can continue to toggle aiter BO is entered if Data Ready goes high before the clock's next rising edge.
Clock·to·data setup and hold times, and minimum ~tl to be detennined.
Upon power up, all bits are Internally set to logic O.

Figure 2. Typical Application
0.1

From
Microphone
0.11.

VCC

lOOk

~~----~~~~~~Ir--+-.

1.0k

r--rI

I

DRI

IlProcessor I

Data I
Clock I

I

---r
Data
Register
and
Decode
Logic

J"'1.I1..1
.IlI111..

L_~!..J
Disable

Attenuator
Control Circuit

-=

I

100llF

Rx
Attenuator

VCC

5.1k

0.1

10k
10k

VCC lOOk

O.IT
Speaker
Amplifier

MOTOROLA COMMUNICATIONS DEVICE DATA

Receive Input
from2-4
Wire Converter

MC33218
2-307

Figure 4, Attenuator Gain versus VCT
(Half Attenuation Range)

Figure 3. Attenuator Gain versus VCT
20
10

~

00

Attenuator

...........

~

z

~ -10

r--.....

t-

_
~

(!J

./'

-3~

-40
-50

V

"

./

./
...........

x -20
(!J

10~---.-----r----.-----.----.-----'

Tran~mH

r--..... ""
V
............

'"
........

z

~ -10~~~~---1----~-----t-----±~~~

Receive _
Attenuator

~
(!J

............

./' V

~

~
(!J

r--....
..............

-40~--~----~----~--~----~--~

-60

-100

-20~--~----~--~~~~-+-----+----~

-50

50
VCT-VB(mV)

100

-40

150

-20

20

40

60

80

VCT-VB(mV)

Figure 5. Level Detector DC Transfer Characteristics

Figure 6. Level Detector AC Transfer Characteristics
200

2.0~

-so

>


U)

a:
w

~

!l..

a:

40

20

l000IlF

VBCapacit~

--

~

I--~

II-

......

./

V

3.5

i-"""'"

V

......

TAO

V

>

RAO

4.0

4.5

5.0

5.5

6.0

6.5

Vcc. SUPPLY VOLTAGE (V)

Figure 14. Data Ready, Data In, and
Clock Input Characteristics
2oo.-----,------r-----r-----,,----,

100

BO

3.0

:t 2.0 ~

Figure 13. VB Power Supply Rejection
versus Frequency

0

Mb.R~ V

w

~ 4.0

Vcc- 5.OV

-r---

~
1.5
~

iii
:Eo
z

L-

~ 5.0

2.0

1.0

7.0

-

~160

!z

~12Or------r-----;------+-~~-r----~

~1001lF

~

u

VB Capacitor

~ BO~----~----_+--~~r-----_r----~

!l..

;;;

~li4O~----~~~_+--,-~~~,-_r----~

U)

!l..

0

100

1.0k
I. FREQUENCY (Hz)

MOTOROLA COMMUNICATIONS DEVICE DATA

10k

°0~~==1~.0~--~2.~0----~3~.0----~4~~--~5.0
Vln. INPUT VOLTAGE (V)

MC33218
2-309

Figure 15. Receive Attenuator Gain versus VCC
10
0

iil

:s.
:z
<
C!I
w
~
w
0
w

a:

xa:

I
-20 I
-30 I
-40 II
-10

--

Receive Mode

C!I

-50
-60

2.0

3.0

4.0

5.0

6.0

Vee, SUPPLY VOLTAGE (V)

APPLICATIONS INFORMATION
Introduction
The MC33218 provides the necessary circuitry to perform
a voice switched, half duplex, speakerphone function. The
half duplex function is necessary to prevent oscillation
resulting from the high gain and acoustic coupling. It includes
transmit and receive attenuators, preamps, level detectors,
and background noise monitors. An attenuator control circuit
automatically adjusts the gain of the transmit and receive
attenuators based on the microprocessor inputs and/or the
relative strengths of the voice signals present.
Power Supply. Va. and Chip Disable
The power supply voltage at Pin 24 is to be between 3.5
and 6.5 V for normal operation, with reduced operation
possible down to 2.5 V (see AGC section).
The output voltage at VB (Pin 6) is approximately equal
to (VCC - 0.7)/2, and provides the AC ground for the system.
The output impedance at VB is approximately 300 Q (see
Figure 9), and in conjunction with the external capacitor at
VB, forms a low pass filter for power supply rejection. The
choice of VB capacitor is application dependent based on
whether the circuit is powered by the telephone line or a
power supply.
The Chip Disable (Pin 8) permits powering down the IC
for power conservation. With CD between 0 and 0.8 V, normal
operation is in effect. With CD between 2.0 V and VCC, the
IC is powered down. When the IC is re-enabled, the
speakerphone should return to normal mode (bits BO - B7
equal to 0).
Transmit and Receive Attenuators
The transmit and receive attenuator sections are
complementary, performing a log-antilog function. When one
is at maximum gain, the other is at maximum attenuation;
they are never both fully on or fully off. Both attenuators are
controlled by a single output from the attenuator control which
ensures the sum of their gains will remain constant at a
typical value of - 40 dB. Their purpose is to provide the
half-duplex operation required in a speakerphone. They are
identical, and consist of a pre-amp, an input clamp, an
attenuator, and a current to voltage converter. An internal
control voltage determines the gain of each attenuator.
The inputs to the attenuators should not exceed
400 mVrms to prevent distortion.

MC33218
2-310

Attenuator Control Section
There are five inputs to the attenuator control section: one
each from the transmiVreceive level comparator, dial tone
detector, control logic block and transmit and receive
background noise monitors. A single output sets the gain of
both the transmit and receive attenuators.
A DC feedback loop samples the output current of the
attenuator that is at full gain and compares it to a reference
current. The resultant error current then drives an external
resistor and capacitor at the CT pin which corrects the control
voltage, maintaining the desired attenuator gain. The
external RC on the CT pin determines the response time of
the speakerphone.
Background Noise Monitors
The purpose of background noise monitors is to
distinguish speech (which consists of bursts) from
background noise (a relatively constant level). There are two
background noise monitors - one for the receive path and
one for the transmit path. Each is operated on by a level
detector, which provides a DC voltage representative of the
noise level. The voltages at the CPT and CPR pins have
slow rise times (determined by an external RC), but fast
decay times. When speech is present, the voltage on the
non-inverting input of an internal comparator will rise faster
than the voltage at the inverting input (due to the burst
characteristic of speech), causing its output to change. This
output is sensed by the Attenuator Control Block. The time
constant of the external RCs (Pins 3 and 10) determine the
response time to background noise variations.
Dial Tone Detector
Since the dial tone is considered continuous noise, the
background noise monitor would tend to force the attenuators
back to idle mode. The dial tone detector prevents the IC
from changing to idle mode, thus preventing the dial tone
from fading away., The dial tone detector is a comparator with
one side connected to the input of the receive attenuator and
the other input connected to VB with a 15 mV offset. If the
circuit is in the receive mode and the incoming signal is
greater than 15 mV, the comparator's output will change,
disabling the receive idle mode. The receive attenuator gain
will then be determined solely by the volume control.

MOTOROLA COMMUNICATIONS DEVICE DATA

AGC
In the receive mode, the AGC circuit decreases the gain
of the receive attenuator when the supply voltage at VCC falls
below 3.5 V to prevent the speaker from clipping or distorting.
The purpose of this feature is to reduce the power (and
current) used by the speaker when a line-powered
speakerphone is connected to a long telephone line, where
the available power is limited. Reducing the speaker power
controls the voltage sag at Vee and prevents clipping and
distortion on the speaker output.
Microprocessor Control
The data register and decode logic are used to interface
the data from the serial port to the required internal circuitry.
This enables microprocessor control olthe following functions:
Volume Control (16 levels)
Microphone Mute
Attenuator Range (52 dB or 26 dB)
Mode Select: Normal, Transmit, Receive, Idle
The logic inputs should not exceed Vee, and they should
never be allowed to go below ground. The maximum clock
frequency is 1.0 MHz.
On power up, the internal registers are reset to all zeros
(normal mode). An internal capacitor on the Power-on-Reset
pin prevents the registers from accepting data input before
the supply voltage has stabilized.
Volume Control
The volume control enables the receive attenuator gain
to be increased or decreased in 16 equal 2.5 dB steps,
independent of temperature, by microprocessor control.
On power up, the volume control will be reset to
maximum (bits B3 - BO will be 0000). Bit BO is the least
significant bit (LSB), and bit B3 is the most significant bit
(MSB). The transmit attenuator gain will be varied in a
complementary manner.
Microphone Amplifier Mute
When activated by the microprocessor by pulling bit B4
high, it reduces the gain of the amplifier by approximately
- 75 dB. For additional muting, force the Mode Select (bits
B6 and B7) to receive during mute. This will ensure the
transmit attenuator is at 46 dB of attenuation (in full
range) and will provide a combined attenuation of 120 dB
in the transmit path.
Attenuator Range Selection
Bit B5, the Attenuator Range Selector, provides a
choice of 52 dB attenuation range (- 46 dB to + 6.0 dB,
nominally) or 26 dB range (- 32 db to - 6.0 dB). At half
attenuation, the volume control range will be reduced to
approximately 26 dB (see Figure 6).

Mode
The MC33218 can be forced to transmit, receive, or
idle mode by microprocessor input by using bits B7 and
B6. The attenuatorswill beinthetransmit mode for a (VeT-VB)
of -105 mV and the receive mode for a (VeT-VB) of + 150
mV. At idle mode, (VeT-VB) is approximately zero. The
mode selection provides manual or remote control for testing,
to overcome noise on the line, or to increase the transmit
path attenuation during mute.
RFllnterference
Potential radio frequency interference (RFI) problems
should be addressed early in the electrical and mechanical
design of the speakerphone. RFI may enter the circuit
through Tip and Ring, through the microphone wiring to the
microphone amplifier, or through any of the PC board traces.
The most sensitive pins on the MC33218 are the inputs to
the level detectors (RLI, TLI) since, when there is no speech
present, the inputs are high impedance and these op amps
are in a near open loop condition. The board traces to these
pins should be kept short, and the resistor and capacitor for
each of these pins should be physically close to the pins.
Any other high impedance input pin should also be
considered sensitive to RFI signals.
In the Final Analysis
Proper operation of a speakerphone is a combination of
proper mechanical (acoustic) design as well as proper
electronic design. The acoustics of the enclosure must be
considered early in the design of a speakerphone. In general,
electronics cannot compensate for poor acoustics, low
speaker quality, or any combination of the two. Proper
acoustic separation of the speaker and microphone is
essential. The physical location of the microphone, along with
the characteristics of the selected microphone, will playa
large role in the quality of the transmitted sound. The
microphone and speaker vendors can usually provide
additional information on the use of their products.
In the final analysis, the circuit shown in this data sheet
will have to be fine tuned to match the acoustics of the
enclosure, the specific hybrid, and the specific speaker and
microphone selected. The components shown in this data
sheet should be considered as starting points only. The
gains of the transmit and receive paths are easily adjusted
at the microphone and speaker amplifiers, respectively. The
switching response can then be fine tuned by varying (in
small steps) the components at the level detector inputs
until satisfactory operation is obtained for both long and
short lines.
For additional information on speakerphone design,
please refer to the data sheet for the MC34118
Speakerphone IC.

GLOSSARY
AGC - Automatic gain control. In the speakerphone, the gain
C-Message Filter - A frequency weighting which
evaluates the effects of noise on a typical subscriber's
of the attenuators is reduced as the supply voltage
decreases to prevent clipping or distortion on the output.
system.
Attenuation - A decrease in magnitude of a communication
Channel Separation - The ability of one circuit to reject
signal, usually expressed in dB.
outputting signals which are being processed by another
circuit. Also referred to as crosstalk, it is usually expressed
Bandwidth - The range of information carrying frequencies
in dB.
'
of a communication system.

MOTOROLA COMMUNICATIONS DEVICE DATA

MC33218
2-311

dB - A power or voltage measurement unit, referred to
another power or voltage. It is generally computed as:
10 x log (P1/P2) for power measurements, and
20 x log (V1N2) for voltage measurements.

Off-Hook - The condition when the telephone is connected
to the phone system, permitting the loop current to flow. The
central office detects the DC current as an indication that the
phone is busy.

dBm - An indication of signal power. 1.0 mW across 600
is typically defined as 0 dBm for telecom
applications. Any voltage level is converted to dBm by:
dBm 20 x log (Vrms/0.775), or
dBm = [20 x log (Vrms)) + 2.22.

On-Hook - The condition when the teleph0r;l_e is
disconnected from the phone system, and no DC loop current
flows. The central office regards an on-hook phone as
available for ringing.

n, or 0.775 Vrms,

=

dBmp -Indicates dBm measurement using a psophometric
weighting filter.
dBrn· - Indicates a dBm measurement relative to 1.0 pW
power level into 600 n. Generally used for noise
measurements, 0 dBrn = - 90 dBm.
dBrnC -Indicates a dBrn measurement using a C-message
weighting filter.
DTMF - Dual Tone Multi Frequency. It is the "tone dialing"
system based on outputting two non-harmonic related
frequencies simultaneously to identify the number dialed.
Eight frequencies have been assigned to the four rows and
four columns of a typical keypad.
Four-Wire Circuit - The portion of a telephone or central
office, which operates on two pairs of wires. One pair is for
the Transmit path (generally from the microphone), and one
pair is for the Receive path (generally from the receiver).
Full-Duplex - A transmission system which permits
communication in· both directions simultaneously. The
standard handset telephone is. full-duplex.

Power Supply Rejection Ratio - The ability of a circuit to
reject outputting noise, or ripple, which is present on the
power supply lines. PSRR is usually expressed in dB.
Pulse Dialing - A dialing system whereby the loop current
is interrupted a number of times in quick succession. The
number of interruptions corresponds to the number dialed,
and the interruption rate is typically 10 times per second. The
old rotary phones, and many new pushbutton phones, use
pulse dialing.
Receive Path - Within the telephone, it Is the speech path
from the phone line to the earpiece.
Ring - One of the two wires connecting the central office
to a telephone. The name derives from the ring portion of
the plugs used by operators (in older equipment) to make
the connection. Ring is traditionally negative with respect to
lip.
Sidetone - The sound fed back to the receiver as a result
of speaking into the microphone. It is a natural consequence
of the 2-to-4 wire conversion system. Sidetone was
recognized by Alexander Graham Bell as necessary for a
person to be able to speak properly while using a handset.

Gain - The change in signal amplitude (increase or
decrease) after passing through an amplifier, or other circuit
stage. Usually expressed in dB, an increase is a positive
number, and a decrease is a negative number.

Signal to Noise Ratio - The ratio of the desired signal to
unwanted signals (noise) within a defined frequency range.
The larger the number, the better.

Half-Duplex - A transmission system which permits
communication in one direction at a time. CB radios, with
"push-to-talk" switches, and voice activated speakerphones,
are half-duplex.

Speech Network - A circuit which provides 2-to-4 wire
conversion, i.e. connects the microphone and receiver (or
the transmit and receive paths) to the Tip and Ring phone
lines. Additionally, it provides sidetone control, and in many
cases, the DC loop current interface.

Hookswltch - A switch which connects the telephone circuit
to the subscriber loop. The name derives from old telephones
where the switch was activated by lifting the receiver off and
onto a hook on the side of the phone.
Hybrid - Another name for a two-to-four wire converter.
Line Length Compensation - Also referred· to as loop
compensation, it involves changing the gain of the
transmit and receive paths, within a telephone, to
compensate for different signal levels at the end of
different line lengths. A short line (close to the CO) will
attenuate signals less, and therefore less gain is needed.
Compensation circuits generally use the loop current as
an indication of the line length.
Loop - The loop formed by the two subscriber wires (Tip
and Ring) connected to the telephone at one end, and the
central office (or PBX) at the other end. Generally it is a
floating system, not referred to ground or AC power.
Loop Current - The DC current which flows through the
subscriber loop. It is typically provided by the central office
or PBX, and ranges from 20 to 120 mAo

MC33218
2-312

Tip - One of the two wires connecting the central office to
a telephone. The name derives from the tip of the plugs used
by operators (in older equipment) to make the connection.
lip is traditionally positive with respect to Ring.
Transmit Path - Within the telephone, it is the speech path
from the microphone to the phone line.
Two-ta-Four Wire Converter - A circuit which has four wires
(on one side); two (signal and ground) for the outgoing signal,
and two for the incoming signal. The outgoing signal is sent
out differentially on the two-wire side (the other side), and
incoming differential signals received on the two-wire side
are directed to the four-wire side. Additional circuitry within
cancels the reflected outgoing signal to keep it separate from
the incoming signal.
Voiceband - That portion of the audio frequency range used
for transmission across the telephone system. Typically, it
is 300 to 3400 Hz.

MOTOROLA COMMUNICATIONS DEVICE DATA

MOTOROLA

-

SEMICONDUCTOR
TECHNICAL DATA

MC34010
Advance Information
ELECTRONIC
TELEPHONE
CIRCUIT

ELECTRONIC TELEPHONE CIRCUIT
• Provides All Basic Telephone Station Apparatus Functions in a
Single IC, Including DTMF Dialer, Tone Ringer, Speech Network
and Line Voltage Regulator

BIPOLAR LlNEARlI2L

• DTMF Generator Uses Low-Cost Ceramic Resonator with Accurate Frequency Synthesis Technique
• Tone Ringer Drives Piezoelectric Transducer and Satisfies EIA
RS-470 Impedance Signature Requirements
• Speech Network Provides Two-Four Wire Conversion with
Adjustable Sidetone Utilizing an Electret Transmitter
• On-Chip Regulator Insures Stable Operation Over Wide Range
of Loop Lengths
• 12L Technology Provides Low 1.4 Volt Operation and High Static
Discharge Immunity

.!4JIff'
1

FN SUFFIX
44-PIN
PLCC
CASEm

• Microprocessor Interface Port for Automatic Dialing Features

FIGURE 1 -

PSUFFIX
PLASTIC PACKAGE
CASE 711

ELEMENTS OF THE ELECTRONIC TELEPHONE

Hook Switch

r----7

Piezo

I

Sound
Element

eo"ml,

FD~

Reso~a~r _ _ _ _

-- -

I

-------,

I"

I

~

Tip

I
I

1
4

2

3 A

5

6 B

7

B 9 C

*

0 # D
Keypad

I
I

Tone
Ringer

DTMF

I
I

1--.,

MPU

,.......
I

MPU
Interface

Speech
Network

Line
Voltage
Regulator

Ring

I

Receiver

Electret

This document contains information on a new product. Specifications and information herein
are subject to change without notice.

MOTOROLA COMMUNICATIONS DEVICE DATA

MC34010
2-313

MAXIMUM RATINGS (Voltage References to V -)

PIN CONNECTIONS

Parameter

Value

Unit

V + Terminal Voltage (Pin 34)

+20, -1.0

V

VR Terminal Voltage (Pin 29)

+2.0, -1.0

V

RXO Terminal Voltage (Pin 27)

+2.0, -1.0

V

TRS Terminal Voltage (Pin 37)

+35, -1.0

V

TRO (With Tone Ringer Inactive) Terminal Voltage

+2.0, -1.0

Rl-R4 Terminal Current (Pins 1-4)
Cl-C4
(Pins 5-8)

V

±100

mA

CL, TO, DD, 1/0, A +

+122, -1.0

V

Operating Ambient Temperature Range

-20 to +60

"C

Storage Temperature Range

-65 to +150

"C

1/0
DD
CL
CR1
CR2
MM
AGC
MIC

GENERAL CIRCUIT DESCRIPTION
Introduction
The MC34010 Electronic Telephone Circuit (ETC)
provide all the necessary elements of a tone dialing
telephone in a single IC. The functional blocks of the
ETC include the DTMF dialer, speech network, tone
ringer, and dc line interface circuit (Figure 1). The
MC34010 also provides a microprocessor interface
port that facilitates automatic dialing features.
Low voltage operation is a necessity for telephones
in networks where parallel telephone connections are
common. An electronic speech network operating in
parallel with a conventional telephone may receive line
voltages below 2.5 volts. DTMF dialers operate at similarly low-line voltages when signaling through battery
powered station carrier equipment. These low voltage
requirements have been addressed by realizing the
MC34010 in a bipolar/1 2L technology with appropriate
circuit techniques. The resulting speech and dialer circuits maintain specified performance with instantaneous input voltage as low as 1.4 volts.
Line Voltage Regulator
The dc line interface circuit (Figure 3) determines the
dc input characteristic of the telephone. At low input
voltages (less than 3 volts) the ETC draws only the
FIGURE 3 -

DC LINE INTERFACE BLOCK DIAGRAM

FIGURE 2 -

I
I
I
I

I

I
I
IL ______________________
ETC I
~

MC34010
2-314

MPU INTERFACE CODES

GJ 0

0

0

r-

R1

~

0

0

r-

R2

CD 0

[}]

0

r-

R3

G 0

0

0

t - R4

I

C1

0

I
C2

I

C3
Keypad

I
C4

Key

Row

Column

Code (83-BOI

1
2
3
4
5
6
7
9
0
A
B
C
D

1
1
1
2
2
2
3
3
3
4
1
2
3
4

*

4
4

1
2
3
1
2
3
1
2
3
2
4
4
4
4
1
3

1111
0111
1011
1101
0101
1001
1110
0110
1010
0100
0011
0001
0010
OOpO
1100
1000

8

I

TRF
TRO
TRI
TRS
TRC
FB
V+
BP
LR
LC
VVR
CAL
RXO
RXI
RM
STA
TXO
TXI
TXL

Rl
R2
R3
R4
Cl
C2
C3
C4
DP
TO
MS
A+

#

MOTOROLA COMMUNICATIONS DEVICE DATA

GENERAL CIRCUIT DESCRIPTION (continued)

Speech Network
The speech network (Figure 5) provides the two-tofour wire interface between the telephone line and the
instrument's transmitter and receiver. An electret microphone biased from VR drives the transmit amplifier.
For very loud talkers, the peak limiter circuit reduces
the transmit input level to maintain low distortion. The
transmit amplifier output signal is inverted at the STA
terminal and driven through an external R-C network to
control the receiver sidetone level. The switched ac resistance at the RM terminal reduces receiver signal
when dialing and suppresses clicks due to hook or keypad switch transitions. When transmitting, audio signal
currents (iTXO and iRXO) flow through the voltage regulator pass transistor (T1) to drive the telephone line.
This feature has two consequences: 1) In the transmitting mode the receiver sidetone current iRXO contributes to the total signal on the line along with iTXO;
2) The ac impedance of the telephone is determined by
the receiver impedance and the voltage gain from the
line to the receiver amplifier output.

speech and dialer bias currents through the VR regulator. As input voltage increases, Q1 conducts the
excess dc line current through resistor R4. The 1.5 volt
level shift prevents saturation of Q2 with telephone line
signals up to 2.0 volts peak (+ 5.2 dBm). A constant
current (dummy load) is switched off when the DTMF
dialer is activated to reduce line current transients. Figure 4 illustrates the dc voltage/current characteristic of
an MC34010 telephone.
FIGURE 4 - DC V-I CHARACTERISTIC OF THE ETC
7.0
'" 6.0
.:
rn
-0-

-5:g
5.0
xw "

I1V

~~4.0

=

111

~cD
~ 3.0
CD ,9

R4

:g

:5 0

Operable

2.0
1.0
10

20

30
40
Line Current (mAl

50

60

120

DTMF Dialer
Keypad interface comparators activate the DTMF row
and column tone generators (Figure 6) when a row and
column input are connected through a SPST keypad.
The keypad interface is designed to function with contact resistances up to 1.0 k!l and leakage resistances as
low as 150 k!l. Single tones may be initiated by depressing two keys in the same row or column.

FIGURE 5 - SPEECH NETWORK BLOCK DIAGRAM

Sidetone

Transmit
Amplifier

--ITXO
Rll

R5
Telephone
Line

~

,----,
I Telephone
I Handset
I

C7

I
I
I
I

I

CB
R7

I
I
I
I
I
RXII

C3 +

I

I Electret
I Microphone
I

I
I Receiver

LA~P~f~
R6

MOTOROLA COMMUNICATIONS DEVICE DATA

Cl0
--IRXO

I
I

L_R.!!!'~v.!!!..J

MC34010
2-315

The programmable counters employ a novel design
to produce non-integer frequency ratios. The various
DTMF tones ani synthesized with frequency division
errors less than ±0.16% (Table 1). Consequently an inexpensive ceramic resonator can be used instead of a
quartz crystal as the DTMF frequency reference. Total

frequency error less than ± 0.8% can be achieved with
±0.3% ceramic resonator. The row and column D/A
converters produce 16-step approximations of sinusoidal waveforms. Feedback through terminal FB reduces the DTMF output impedance to approximately
2.0 kG to satisfy return loss specifications.

FIGURE 6 - DTMF DIALER BLOCK DIAGRAM

r------------------------,
I
I
I

I

Cl I

I

.-----~~~

I

I FB

C14

Keypad
Comparators
& Logic

Telephone
Line

1

Keypad

I

I

Mute Signal to
Speech Network
and Line
Interface Circuit

I

I
I

I
I

I

I

L_________ -0- cR;------l-----~C...J
500 kHz Ceramic
Resonator

\I \I

C1TXRTC2

Tone Ringer
The tone ringer (Figure 7) generates a warbling
square wave output drive to a piezo sound element
when the ac line voltage exceeds a predetermined
threshold level. The threshold detector uses a current
mode comparator to prevent onloff chatter when the
output current reduces the voltage available at the
ringer input. When the average current into the tone
ringer exceeds the threshold level, the ringer output
TRO commences driving the piezo transducer. This output current sourced from TRI increases the average current measured by the threshold detector. As a result,
hysteresis is produced beween the tone ringer on and
off thresholds. The output frequency at TRO alternates
between fd8 and foIl 0 at a warble rate of f o /640, where
fo is the ringer oscillator frequency.
Microprocessor Interface
The MPU interface connects the keypad and DTMF
sections of the ETC to a microprocessor for storing and
retrieving numbers to be dialed. Figure 8 shows the
major blocks of the MPU interface section and the interconnections between the keypad interface, DTMF
generator and microprocessor. Each button of a 12 or
16 number keypad is represented by a four-bit code
(Figure 2). This four-bit code is used to load the programmable counters to generate the appropriate row
and column tones. The code is transferred serially to or
from the microprocessor when the shift register is

MC34010
2-316

v-

clocked by the microprocessor. Data is transferred
through the lID terminal, and the direction of data flow
is determined by the Data Direction (DD) input terminal.
In the manual dialing mode, DD is a logic "0" and the
four-bit code from the keypad is fed to the DTMF generator by the digital multiplexer and also output on the
lID terminal through the four-bit shift register. The data
sequence on the lID terminal is B3, B2, Bl, BO and is
transferred on the negative edge of the clock input (Cl).
In this mode the shift register load enable circuit cycles
the register between the load and read modes such that
multiple read cycles may be run for a single-key closure.
Six complete clock cycles are required to output data
from the ETC and reload the register for a second look.
In the automatic dialing mode, DD is a logic "1" and
the four-bit code is serially entered in the sequence B3,
B2, Bl, BO into the four-bit shift register. Thus, only four
clock cycles are required to transfer a number into the
ETC. The keypad is disabled in this mode. A logic "1"
on the Tone Output (TO) will disable tone outputs until
valid data from the microprocessor is in place. Subsequently TO is switched to a logic "0" to enable the
DTMF generator. Figures 9 and 10 show the timing waveforms for the manual and automatic dialing modes
and Table 2 specifies timing limitations.
The keypad decoder's exclusive OR circuit generates
the DP and MS output signals. The DP output indicates
(when at a logic "1 ") that one, and only one, key is
MOTOROLA COMMUNICATIONS DEVICE DATA

depressed, thereby indicating valid data is available to
the MPU. The DP output can additionally be used to
initiate a data transfer sequence to the microprocessor.
The MS output (when ata Logic "1") indicates the DTMF
generator is enabled and the speech network is muted.
Pin A + is to be connected to a source of 2.5 to 10
volts (generally from the microprocessor circuit) to enable the pullup circuits on the microprocessor interface
outputs (DP, MS, 1/0). Additionally, this voltage will

power the entire circuitry (except Tone Ringer) in the
absence of voltage at V +. This permits use of the transmit and receive amplifiers, keypad interface, and DTMF
generator for non-typical telephone functions.
See Figure 45 for a typical interconnection to an
MC6821 PIA (Peripheral Interface Adapter). Connection
to a port on any other class of microprocessor will be
similar.

FIGURE 7 - TONE RINGER BLOCK DIAGRAM

R2

C17

E----wv--o Tip

+ C16

R1

971:
1--------

TRF

TRI

' - - - - - - - - - - - 0 Ring

I

I

I
I
I

I
I

I
I

TRCI

I

I

I

R31

I
I
IL

I

+640

Piezo
Tone
Ringer

I

____________________

ETC I

~~~-~

FIGURE 8 - MICROPROCESSOR INTERFACE BLOCK DIAGRAM

r-------------------------,,TO
Exclusive ·OR

8

DP

"
~~" ~:g
O.c:: 0 c: ~

MS

a:w Uw :i:

•••

DTMF Generator
1

2

4

5

3
6

7

8

9

*

0

#

--1/.,

l'I

Keypad ~
Comparators

I
I
I
I
I
I
I
I
I
I
I
I ETC

Keypad
Decoder

IV

Shift
Register
Load
Enable

•

4
~

--V

~

'------i

i1'"
Digital
MUX

11
4·Bit
Shift
Register

•

I
I
IDD
I

11/0

MPU

II CL

r

L ____ ."- ____________ ~~-----..J

vMOTOROLA COMMUNICATIONS DEVICE DATA

MC34010
2-317

FIGURE 9 -

OUTPUT DATA CYCLE

NOTE: TO may be low (Tone generator enabled) if desired.

DD~,\\~~____~'_K_e_y_D_e_p_re_s_se_d______________________________________K_e_Y_R_e_le_a_se_d-+t___

,
I
I

I

MS\\~~

r-----------------;L

~--~

I

I

l

I

DP ____________~ tDPCL

1-1

FIGURE 10 DO

----.J

Tone Generation Interval

H

1-ltTODD

TO

INPUT DATA CYCLE

Jr---+-'-----.~Jr---------,~J

L

I

MS

,I

----.J

I
I

I

I

I
I

I

DP

I

I
HtDDCL

tDs_lI_

H

HtDH

tCLTO

tH

H-I tL

JlIUlJLJUUlJL

I/O~~~
1st Digit
TABLE 1 -

Row
Row
Row
Row

1
2
3
4

Column
Column
Column
Column

1
2
3
4

2nd Digit

FREQUENCY SYNTHESIZER ERRORS

DTMF
Standard
(Hz)

Tone Output
Frequency with
500 kHz Oscillator

% Deviation
from Standard

697
770
852
941

696.4
769.2
853.2
939.8

-0.086
-0.104
+0.141
-0.128

1209
1336
1477
1633

1207.7
1336.9
1479.3
1634.0

-0.108
+0.067
+0.156
+0.061

TABLE 2 Symbol

TIMING LIMITATIONS

Paramater

Min Typ Max Unit

fCL
tH

Clock Frequency
Clock High Time

tL

Clock Low Time

15

tr,tf
tDV

Clock Rise, Fall Time
Clock Transition to
Data Valid
TIme from DP High
to CL Low
TIme from DO High
to CL Low
Data Setup Time
Data Hold Time
Time from CL Low
toTO Low
Time from TO High
to DO High

-

tDPCL
tDDCL
tDS
tDH
tcLTO
tTODD

MC34010
2-318

3rd Digit

0
15

20

-

10
10
10

-

20

-

20
20

Ref

30

kHz
p.s Figs.
9,10
p.s Figs.
9,10
2.0 p.s
10 p.s Fig. 9

-

-

p.s Fig. 9

-

p.s Fig. 10

p.s Fig. 10
p.s Fig. 10
p.s Fig. 10
p.s Fig. 10

MOTOROLA COMMUNICATIONS DEVICE DATA

PIN DESCRIPTION
(See Figure 45 for external component identifications.)
PIN
(PLCC)

PIN
(DIP)

Function

Designation

1-4

1-4

Rl-R4

Keypad inputs for Rows 1 through 4. When open, internal 8.0 kG resistors pull up the row inputs
to a regulated (~0.5 voltl supply. In normal operation, a row and a column input are connected
through a SPST switch by the telephone keypad. Row inputs can also be activated by a Logic
"0" «250 mY) from a microprocessor port.

7-10

5-8

Cl-C4

Keypad inputs for Columns 1 through 4. When open, internal 8.0 kG resistors pull down the
column inputs to V -. In normal operation, connecting any column input to any row input
produces the respective row and column DTMF tones. In addition to being connected to a row
input, column inputs.can be activated by a Logic "1" (>250 mV and <1.0 volt).

11

9

DP

Depressed Pushbutton (OutputL- Normally low; A Logic "1" indicates one and only one, button
of the DTMF keypad is depressed.

12

10

TO

Tone Output (Input)

13

11

MS

Mute/Single Tone (Output) - A Logic "1" indicates the tone generator is enabled. A Logic "0"
indicates tone generator is disabled.

14

12

A+

MPU Power Supply (Input) - Enables pullups on the microprocessor section outputs.
Additionally, this voltage will power the entire circuit (except Tone Ringer) in the absence of
voltage at V + .

15

13

I/O

Input/Output - Serial Input or Output data (determined by DO input) to or from the
microprocessor for storing or retrieving telephone numbers. Guaranteed to be a Logic "1" on
powerup if DO = Logic "0."

16

14

DO

Data Direction (Input) - Determines direction of data flow through I/O pin. As a Logic "1," I/O
is an input to the DTMF generator. As a Logic "0," I/O outputs keypad entries to the
microprocessor.

17

15

CL

Clock (Input) - Serially shifts data in or out of I/O pin. Data is transferred on negative edge
typically at 20 kHz.

18,19

16,17

CR1, CR2

Ceramic Resonator oscillator input and feedback terminals, respectively. The DTMF dialer is
intended to operate with a 500 kHz ceramic resonator from which row and column tones are
synthesized.

31

28

CAL

Amplitude CAlibration terminal for DTMF dialer. Resistor R14 from the CAL pin to V- controls
the DTMF output signal level at Tip and Ring.

38

35

FB

FeedBack terminal for DTMF output. Capacitor C14 connected from FB to V + provides ac
feedback to reduce the output impedance to Tip and Ring when tone dialing.

32

29

VR

Voltage Regulator output terminal. VR is the output of a 1.1 volt voltage regulator which supplies
power to the speech network amplifiers and DTMF generator during signaling. To improve
regulator efficiency at low line current conditions, an external PNP pass·transistor T1 is used in
the regulator circuit. Capacitor C9 frequency compensates the VR regulator to prevent oscillation.

36

33

BP

Base of a PNP Pass-transistor. Under long-loop conditions where low line voltages would cause
VR to fall below 1.1 volts, BP drives the PNP transistor Tl into saturation, thereby minimizing
the voltage drop across the pass transistor. At line voltages which maintain VR above 1.1 volts,
BP biases Tl in the linear region thereby regulating the VR voltage. Transistor Tl also couples
the ac speech signals from the transmit amplifier to Tip and Ring at V+.

37

34

V+

The more positive input to the regulator, speech, and DTMF sections connected to Tip and Ring
through the polarity guard diode bridge.

33

30

V-

The dc common (more negative input) connected to Tip and Ring through the polarity guard
bridge.

35

32

LR

DC Load Resistor. Resistor R4 from LR to V - determines the dc input resistance at Tip and Ring.
This resistor is external not only to enable programming the dc resistance but also to avoid
high on-chip power dissipation with short telephone lines. It acts as a shunt load conducting
the excess dc line current. At low line voltages «3.0 volts), no current flows through LR.

34

31

LC

DC Load Capacitor. Capacitor Cll from LC to V - forms a low-pass filter which prevents the
resistor at LR from loading ac speech and DTMF signals.

22

20

MIC

MICrophone negative supply terminal. The dc current from the electret microphone is returned
to V - through the MIC terminal which is connected to the collector of an on-chip NPN transistor.
The base of this transistor is controlled either internally by the mute signal from the DTMF
generator, or externally by the logic input pin MM.

When a Logic "1," disables the DTMF generator. Keypad is not disabled.

(continued)

MOTOROLA COMMUNICATIONS DEVICE DATA

MC34010
2-319

PIN DESCRIPTION (continued)
PIN
(PLCC)

PIN
(DIP)

Designation

Function

20

18

MM

Microphone Mute. The MM pin provides a means to mute the microphone in response to a
digital control signal. When this pin is connected to a Logic "1" (>2.0 V) the microphone dc
return path through the MIC terminal is disabled.

25

22

TXI

Transmit amplifier Input. TXI is the input to the transmit amplifier from an electret microphone.
AC coupling capacitors allow the dc offset atTXI to be maintained approximately 0.6 V above
V - by feedback through resistor Rll from TXO.

24

21

TXL

Transmit Input Limiter. An internal variable resistance element at the TXL terminal controls the
transmitter input level to prevent clipping with high signal levels. Coupling capacitors C4 and
C5 prevent dc current flow through TXL. The dynamic range of the transmit peak limiter is
controlled by resistors R12 and R13.

26

23

TXO

Transmit Amplifier Output. The transmit amplifier output drives ac current through the voltage
regulator pass-transistor Tl via resistor Rl0. The dc bias voltage at TXO is typically 0.6 volts
above V-. The transmit amplifier gain is controlled by the Rll/(R12 + R13) ratio.

21

19

AGC

Automatic Gain Control low-pass filter terminal. Capacitor C3 connected between AGC and VR
sets the attack and decay time of the transmit limiter circuit. This capacitor also aids in reducing
clicks in the receiver due to hook-switch transients and DTMF onloff transients. In conjunction
with internal resistors. C3 (1.0 I'FI forms a timer which mutes the receiver amplifier for
approximately 20 milliseconds after the user goes off-hook or releases a DTMF Key.

30

27

RXO

Receiver Amplifier Output. This terminal is connected to the open-collector NPN outputtransistor
of the receiver amplifier. DC bias current for the output device is sourced through the receiver
from VR. The bias voltage at RXO is typically 0.6 volts above the V -. Capacitor Cl0 from RXO
to VR provides frequency compensation for the receiver amplifier.

29

26

RXI

Receiver Amplifier Input. RXI is the input terminal of the receiver amplifier which is driven by
ac signals from V + and STA. Input coupling capacitor C8 allows RXI to be biased approximately
0.6 volts above the V-via feedback resistor R6.

28

25

RM

Receiver Amplifier Mute. A switched resistance at the RM terminal attenuates the receiver
amplifier input signal produced by DTMF dialing tones at V +. RM also mutes clicks atthe receiver
which result from keypad or hook switch transitions. The ac resistance at RM is typically 540 n
in the mute mode and 200 kO otherwise. Coupling capacitors C7 and C8 prevent dc current flow
through RM.

27

24

STA

SideTone Amplifier output. STA is the output of the sidetone inverter amplifier whose input is
driven by the transmit signal at TXO. The inverted transmit signal from STA subtracts from the
receiver amplifier input current from V +, thus reducing the receiver sidetone level. Since the
transmitted signal at V + is phase shifted with respect to TXO by the reactive impedance of the
phone line, the signal from STA must be similarly phase-shifted in order to provide adequate
sidetone reduction. This phase relationship between the transmit signal at TXO and the sidetone
cancellation signal from STA is controlled by R8, R9, and C6.

41

37

TRS

Tone Ringer Input Sense. TRS is the most positive input terminal of the tone ringer and the
reference for the threshold detector.

42

38

TRI

Tone Ringer Input terminal. TRI is the positive supply voltage terminal for tone ringer circuitry.
Current is supplied to TRI through resistor R2. When the average voltage across R2 exceeds an
internal reference voltage (typically 1.6 volts) the tone ringer output is enabled.

44

40

TRF

Tone Ringer Input Filter capacitor terminal. Capacitor C16 connected from TRF to TRS forms a
low-pass filter. This filter averages the signal across resistor R2 and presents this dc voltage to
the input of the threshold detector. Line voltage transients are rejected if the duration is
insufficient to charge C16 to 1.6 volts.

40

36

TRC

Tone Ringer oscillator Capacitor and resistor terminal. The relaxation oscillator frequency fo is
set br resistor R3 and capacitor C13 connected from TRC to V-. Typically, fo = (R3C13 + 8.0
I's)- .

43

39

TRO

Tone Ringer Output terminal. The frequency of the square wave output signal at TRO alternates
from f0l8 to foll0 at a warble rate of fol640. Typical output frequencies are 1000 Hz and 800 Hz
with a 12.5 Hz warble rate. TRO sources or sinks up to 20 mA to produce an output voltage
swing of 18 volts peak-to-peak across the piezo transducer. Tone ringer volume control can be
implemented by a variable resistor in series with the piezo transducer.

MC34010
2-320

MOTOROLA COMMUNICATIONS DEVICE DATA

ELECTRICAL CHARACTERISTICS (TA = 25°C)
KEYPAD INTERFACE CIRCUIT
Test
Method

Symbol

Min

Typ

Max

Unit

Row Input Pullup Resistance
mth Row Terminal: m = 1,2,3,4

7

RRm

4.0

8.0

11

kO

Column Input Pulldown Resistance
nth Column Terminal: n = 1,2,3,4

8

RCn

4.0

8.0

11

kO

7&8

Km,n

0.88

1.0

1.12

380

500

Characteristic

Ratio of Row-to-Column Input Resistances
RRm, m = 1,2,3,4
Km,n =
RCn n = 1,2,3,4

-

7a

VROC

280

Row Threshold Voltage for mth
Row Terminal: m = 1,2,3,4

9

VRm

0.70 VROC

-

Column Threshold Voltage for nth
Column Terminal: n = 1,2,3,4

10

VCn

-

-

0.39 VROC

Vdc

29

VR/A+

0.95

1.1

1.3

V

A + Input Current Off-Hook

28a

IAloff)

300

500

700

I"A

A + Input Current On-Hook

28b

IAlon)

4.0

6.0

9.0

mA

Input Resistance 100, TO, CL)

30

Rin

50

100

150

kO

Input Current 11/0)

31

lin

-

80

200

I"A

A+

V

0.8

V

Row Terminal Open Circuit Voltage

-

mVdc
Vdc

MICROPROCESSOR INTERFACE
Voltage Regulator Output
A + Regulator

Input High Voltage 100, TO, CL, 1/0)

-

VIH

2.0

Input Low Voltage 100, TO, CL, 1/0)

-

VIL

-

-

Output High Voltage IMS, OP, 1/0)

32

VOH

2.4

4.0

-

V

Output Low Voltage IMS, OP, 1/0)

33

VOL

-

0.1

0.4

V

LINE VOLTAGE REGULATOR
Voltage Regulator Output

la

VR

1.0

1.1

1.2

Volts

V + Current in OTMF Mode

2a

lOT

8.0

12

14

mA

Change in lOT with Change in V + Voltage

2b

alOT

-

0.8

2.0

mA

3.5
8.0

5.0
11

7.0
15

-2.0

2.0

3.5

V + Current in Speech Mode
V+=1.7V
V+ = 5.0 V

lb
lc

Speech to OTMF Mode Current Oifference

3

LR Level Shift
V+ = 5.0 V, ILR = 10 mA
V+ = 18V,ILR = 110mA

mA

ISp

alTA

4a
4b

mA
Vdc

aVLR
2.5
2.8

2.9
3.3

3.5
4.0

LC Terminal Resistance

5

RLC

30

50

75

kO

Load Regulation

6

aVR

-20

-6.0

20

mVdc

MOTOROLA COMMUNICATIONS DEVICE DATA

MC34010
2-321

ELECTRICAL CHARACTERISTICS (continued)
SPEECH NETWORK
Characteristic

Test
Method

Symbol

20

VMIC

Min

Typ

Max

Unit

60

125

mVdc

MIC Terminal Leakage Current

21a

IMIC

-

0.0

12.0

pA

MM Terminal Input Resistance

21b

RMM

50

100

170

leO

TXO Terminal Bias

22a

BTXO

0.46

0.53

0.62

-

TXI Terminal Input Bias Current

22b

ITXI

-

50

250

nA

TXO Terminal Positive Swing

22c

VTXOI+)

60

mVdc

22d

VTXOI-)

-

25

TXO Terminal Negative Swing

130

200

mVdc

Transmit Amplifier Closed-Loop Gain

23a

GTX

16.5

19

20

VN

Sidetone Amplifier Gain

23b

GSTA

0.41

0.45

0.55

VN

24

ISTA

50

100

250

pA

RXO Terminal Bias

25a

BRXO

0.46

0.62

0.62

25b

IRXI

100

400

nA

RXO Terminal Positive Swing

25c

VRXOI+)

-

-

RXI Terminal Input Bias Current

1.0

20

mVdc

RXO Terminal Negative Swing

25d

VRXOI-)

-

40

100

mVdc

TXL Terminal OFF Resistance

26a

RTXLIOFF)

125

200

300

kO

TXL Terminal ON Resistance

26b

RTXLION)

-

20

100

0

RM Terminal OFF Resistance

27a

RRMIOFF)

125

180

300

kO

RM Terminal ON Resistance

27b

RRMION)

410

570

770

0

MIC Terminal Saturation Voltage

STA Terminal Output Current

DTMF GENERATOR
Row Tone Frequency

Column Tone Frequency

Row
Row
Row
Row

1
2
3
4

11a,11b

fRm

692.9
765.3
848.9
935.1

696.4
769.2
853.2
939.8

699.9
773.0
857.5
944.5

Hz

Column
Column
Column
Column

1
2
3
4

11c, 11d

fCn

1201.6
1330.2
1471.9
1625.2

1207.7
1336.9
1479.3
1633.4

1213.7
1343.6
1486.7
1641.5

Hz

Row Tone Amplitude

11e

VRow

0.34

0.39

0.50

V rms

Column Tone Amplitude

11f

VCol

0.43

0.48

0.62

V rms

Column Tone Pre-emphasis

11g

dBCR

0.5

1.8

3.0

dB

12

0/0 Dis

-

4.0

6.0

0/0

13

Ro

1.0

2.5

3.0

kO

DTMF Distortion
. DTMF Output Resistance

MC34010
2-322

MOTOROLA COMMUNICATIONS DEVICE DATA

ELECTRICAL CHARACTERISTICS (continued)
TONE RINGER
Characteristic

Test
Method

Symbol

Min

Typ

Max

Unit

14

VTRI

20

21.5

23

Vdc

70
0.4

120
0.8

170
1.5

pA
mA

TRI Terminal Voltage
TRS Terminal Input Current
VTRS = 24 volts
VTRS = 30 volts

15a
15b

TRF Threshold Voltage

16a

VTRF

1.2

1.6

1.9

Vdc

TRF Threshold Hysteresis

16b

ilVTRF

100

200

400

mVdc

TRF Filter Resistance

17

RTRF

30

50

75

kil

High Tone Frequency

18

fH

920

1000

1080

Hz

Low Tone Frequency

18

fL

736

800

864

Hz

Warble Frequency

18

tw

11.5

12.5

13.5

Hz

Tone Ringer Output Voltage

19

Vo(p-p)

18

20

22

Vp-p

ITRS

FIGURE 11 -

2
3
4
5
6
7
8
9
10
11
12
13
14
15

100 PF

r

16

*=
1100 pF

17
18
19
20

R1

TRF

R2

TRO

R3

TRI

R4

TRS

C1

TRC

C2

FB
V+

C3

BP

C4
DP
TO
MS

D.U.T.

LR
LC
V-

A+

VR

110

CAL

DD

RXO

a:

RXI

CR1

RM

CR2

STA

MM

TXO

AGC

TXI

MIC

Notes:
1.
2.
3.
4.

GENERAL TEST CIRCUIT

TXL

40
39
38
37
36
35
34
33
32
31
30

+

2.0 k

25
24
23
22
21

200 k
10 k

1

TXAC

0 01
.

*Selected ceramic resonator: 500 kHz:::!: 2.0 kHz.
Capacitances in I-LF unless noted.
All resistances in ohms.
Pin outs shown are for the 40 pin DIP.

MOTOROLA COMMUNICATIONS DEVICE DATA

MC34010
2-323

FIGURE 13 - TEST TWO

FIGURE 12 - TEST ONE

34

ISp

34

600

n

l

5
General
Test
Circuit

+

29
1----4.():J VR

a. Measure VR with Vs

b. Measure ISp with Vs

= 1.7 V
= 1.7 V

General
Test
Circuit

=

a. Measure lOT with Vs

+
Vs

11.5 V

c. Measure ISp with Vs = 5.0 V

b. Measure lOT with Vs = 26 V. Calculate
~IOT = lOT
lOTI
26 V
11.5 V

FIGURE 14 - TEST THREE

FIGURE 15 - TEST FOUR

I-

S1
34

34
600

n

+

General
Test
Circuit

With 51 open measure ITR. Close S1 and again measure
ITR. Calculate:

~ITR

= ITR

1-

S1
Closed

MC34010
2-324

ITRI
S1
Open

General
Test
Circuit

8. Set Vs = 5.0 V and ILR = 10 mAo Measure VLR.
Calculate ~VLR = Vs ~ VLR

b. Repeat Test 4a with Vs

=

18 V and ILR

=

110 mA

MOTOROLA COMMUNICATIONS DEVICE DATA

FIGURE 16 -

FIGURE 17 - TEST SIX

TEST FIVE

34
5.0 V
General
Test
Circuit

General
Test
Circuit

With S1 open measure VLC.
Close S1 and measure ILC.
Calculate:
5.0 - VLC
RLC = -"-IL-C-

FIGURE 18 -

(

IRm

Set IBP = 0.0 pA and measure VR.
Set IBP = 150 pA and measure VR. Calculate:

~VR=VRI- VRI
0.0 pA

FIGURE 19 - TEST EIGHT

TEST SEVEN

34

S1

2

+
3
4

General
Test
Circuit

150 pA

l5.0V

-

~
~.OV

34
5

+
6
7
8

l5.0V
General
Test
Circuit

-

-

Subscript m corresponds to row number.

a. Set S1 to Terminal 2 and measure voltage at Terminal 1
(VROc)·
b. Set S1 to Terminal 1 (m = 1) and measure IR1. Calculate:

Subscript n corresponds to column number.

a. Set S1 to Terminal 5 (n = 1) and measure IC1. Calculate:
RC1 = 1.0V + IC1
b,c,d. Repeat Test 8a for n = 2,3,4.

RR1 = VROC + IR1
c,d,e. Repeat Test 7b for m = 2,3,4.

MOTOROLA COMMUNICATIONS DEVICE DATA

MC34010
2-325

FIGURE 21 - TEST TEN

FIGURE 20 - TEST NINE

34

34

+
General
Test
Circuit

+

29

29

General
Test
Circuit

20
10 k
m corresponds to row number.

n corresponds to column number.

a. Set 51 to Terminal 1 (m = 1) with Vl = 1.0 Vdc. Verify
VMIC is Low (VMIC < 0.3 Vdc). Decrease Vl to 0.70 VROC
and verify VMIC switches high. (VMIC > 0.5 Vdc). VROC
is obtained from Test 7a.
b,c,d. Repeat Test ,9a for rows 2,3, and 4. (m

= 2,3,4)

a. Set Sl to Terminal 5 (n = 1) with Vl = 0 Vdc. Verify
VMIC is low (VMIC < 0.3 Vdc). Increase Vl to 0.39 VROC
and verify VMIC switches high, (VMIC > 0.5 Vdc). VROC
is obtained from Test 7a.
b,c,d. Repeat Test lOa for columns 2,3, and 4. (n

= 2,3,4)

FIGURE 22 - TEST ELEVEN

34

600

n
+

General
Test
Circuit

a. With V, = 0.0 V set Sl to Terminal' (m
measure frequency of tone at V +.

= ') and

b. Repeat Test "a for rows 2,3 and 4. (m = 2,3,4).
c. With V, = 1.0 V set S, to Terminal 5. (n
measure frequency of tone at V +.

= 1) and

d. Repeat Test for columns 2,3, and 4. (n = 2,3,4).
e. Set Sl to Terminal 4 and V, = 0.0 V. Measure row tone
amplitude at V+ (VROW).
f. Set S, to Terminal Band Vl = 1.0 V. Measure column
tone amplitude at V +. (VcoL!.

m corresponds to row number.
n corresponds to column number.

MC34010

2-326

g. Using results of Tests 'le and l1f, calculate:
VCOL
dBCR = 20 1091O VROW

MOTOROLA COMMUNICATIONS DEVICE DATA

FIGURE 23 -

TEST TWELVE

FIGURE 24 -

4.-------.

.-----'-j

.r.

OV

600

34

35

n

r-~e-~vv--~

5

TEST THIRTEEN

34

5

General
Test
Circuit

-.r.0 V

IS

General
Test
Circuit

'6
V,
'0 kHz Single
Pole LPF

Note: The notch filters must have 50 dB attenuation at their
respective center frequencies.
Measure V + and V, with a true rms voltmeter. Calculate:
V,(rms)
% DIS = V+(rms) x '00

FIGURE 25 -

TEST FOURTEEN

,...----....,38
~~.-............ VTRI

Measure IS at V,
Calculate:
Ro = '.0 V

= '.8 V and V, = 2.8 V.

+[151 2.8- VIS\ '.8 V ]

FIGURE 26 -

TEST FIFTEEN

.--------. 38

r----------.
37

37
General
Test
Circuit

General
Test
Circuit

+
l20V

a. Measure ITRS with V, = 24 V.
Set I = '.0 mA and measure VTRI.

MOTOROLA COMMUNICATIONS DEVICE DATA

b. Measure ITRS with V, = 30 V.

MC34010

2·327

FIGURE 27 - TEST SIXTEEN

FIGURE 28 - TEST SEVENTEEN
r-----..., 40

r--""""'---'39
t----OVTRO
38
General
Test
Circuit

38

37
General
Test
Circuit

a. Increase VI from 21 V until VTRO switches on. Note that
VTRO will be an 16 Vpp square wave. Record this value
of VI. Calculate:
VTRF

ITRF

1--1--.....:.......,

Measure ITRF. Calculate: RTRF

= 1.0

+ ITRF.

= VI - 20 V

b. Decrease VI from its setting in Test 16a until VTRO
ceases switching. Record this value of VI. Calculate:
IlVTRF

= V11- VII
Test
16a

Test
16b

FIGURE 29 - TEST EIGHTEEN
VDD
110 k
.......- - - ' 3 9

1-------'-.....,

0.01 /LF

38
VDD

General
Test
Circuit

37

+
~OV

16
15
14
r - - - - - - - - + - - - l 4 IC2 13
5
12
r-------16
11

1
2
1 - - - - -....--1 3

7

8

VDD

1--+---1--'

I--+-~I---I

1--1---,

101----+---~e_~O)

9

39 k

5.1 k

Measure the frequencies

MC34010

2-328

10 k

ICI - MC14011B
IC2 - MC14538B
VDD = 12 V
TI-2N3904

two fH. fl.

MOTOROLA COMMUNICATIONS DEVICE DATA

FIGURE 31 - TEST TWENTY

FIGURE 30 - TEST NINETEEN

r-------, 39
I - - - - - - { ) VTRO
38

34

37

Measure VTRO peak-to-peak voltage swing.
Using VTRI from Test 14 Calculate:
Vo(p-p) = VTRI - 20 V

15.0V

General
Test
Circuit

General
Test
Circuit

Measure VMIC

+ VTRO

FIGURE 33 - TEST TWENTY-TWO

FIGURE 32 - TEST TWENTY-ONE

34
34

VTXO

23
General
Test
Circuit
IMM

General
Test
Circuit

18
20

VTXI

-

~s,
+

+

+

..I.5.0V

22

I

a. With S1 open, measure VTXO. Using VR obtained in Test
1 Calculate: BTXO = VTXO + VR
a. Set V1 = 2.0 V and measure IMIC.
b. Set V1 = 5.0 V and measure IMM.
Calculate: RMM = 5.0 V + IMM

b. With S1 open, measure VTXO and VTXI. Calculate:
ITXI = (VTXO - VTxll + 200 kG
c. Close 51 and set I = -10 pA. Measure VTXO. Calculate:
VTXO( +) = VR - VTXO where VR is obtained from
Test 1.
d. Close 51 and set I =

VTXO( -)

MOTOROLA COMMUNICATIONS DEVICE DATA

=

+ 10 pA. Measure VTXO.

VTXO·

MC34010

2-329

FIGURE 34 - TEST TWENTY-THREE

FIGURE 35 - TEST TWENTY-FOUR

r----.34

r-----.34

1-=------,

r"------,

+
24
23

General
Test
Circuit

TXAC

VTX£I..5.0 V

2'0:F~f

General
Test
Circuit

ISTA

24

= 1.0 kHz

+
~.3V

vi

'------'

J....

-.."

a. Set the generator for vi = 3.0 mV rms. Measure ac
voltage VTXO. Calculate:

Measure ISTA.

GTX=~

vi
b. Measure ac voltage VSTA. Using VTXO from Test 23a
calculate:
G

-~

STA - VTXO

FIGURE 36 - TEST TWENTY-FIVE

FIGURE 37 - TEST TWENTY-SIX
.------,34

r-----,34

r"------,

1-'------,+

,.r:;.o

+
General
Test
Circuit

X· OV

27
26

VRXO

General
Test
Circuit

VRXI

V

ITXL
Sl

+

~~
:::~~
1.0Vrms "'"
1.0 kHz

Ii

.J.....

a. With Sl open, measure VRXO. Using VR obtained in Test
1, calculate: BRXO = VRXO .,. VR·
b. With Sl open, measure VRXO and VRXI. Calculate:
IRXI = (VRXO - VRX1) .,. 100 kO
c. Close Sl and set 1= -10 pA. Measure VRXO. Using VR
obtained in Test 1, calculate: VRXO (+) = VR - VRXO.
d. Close Sl and set 1= +10 pA and measure VRXO.
VRXO( -) = VRXO·

MC34010
2~30

a. Set Sl to position A with S2 open. Measure ITXL.
Calculate: RTXL (OFF) = 0.4 V .,. ITXL.
b. Set Sl to position B and close S2' Measure ac voltages vi
and VTXL. Calculate:
RTXL (ON) =

~V x 5.1

vi- TXL

kO

MOTOROLA COMMUNICATIONS DEVICE DATA

FIGURE 38 - TEST TWENTY-SEVEN

FIGURE 39 - TEST TWENTY-EIGHT

,...-----.34

1-------. +

General
Test
Circuit

S1nr.
IRM

25

A

34

IA
-12

.I:.OV

+

-.1.:.0 V
4V

General
Test
Circuit

t I:o~

VRM~

~ 2'OJLF~~
1.0 Vrms ........
1.0 kHz

~Vi

a. With S2 open and S1 in position
A measure IRM.

a. Set V + = 1.4 V. Measure IA(OFF)

Calculate: RRM(OFF)=0.4 V.;. IRM

b. Set V + = 0.6 V. Measure IA(ON)

b. Close S2 and switch S1 to position B. Measure ac
voltages Vi and VRM.
Calculate:
V
RRM(ON) = ~vM x 10 kfl
vi - RM

FIGURE 40 - TEST TWENTY-NINE

FIGURE 41 - TEST THIRTY
12.----'
r-----~

34

34

10
12
+

2.4~

-

General
Test
Circuit

14

lO.6V
29

-

15

General
Test
Circuit

VRiA+

+

Measure VRiA+

MOTOROLA COMMUNICATIONS DEVICE DATA

Measure lin at each of three inputs. For each, calculate:
Rin = 5.0 Vilin

MC34010

2-331

FIGURE 42 -

TEST THIRTY-ONE

FIGURE 43 -

TEST THIRTY-TWO

12.-----.
r---I=-in---i

12
9

34

+
5.0 V..I.

..li8:ill:0V

34

11

General
Test
Circuit

13

+ 48 k

48 k 48 k

General
Test
Circuit

5.0Vl
Measure lin.

a.
b.

c.

FIGURE 44 -

TEST THIRTY-THREE

34
11

~

r

13

General
Test
Circuit

7'

14
15
.IL

VI/Ol

-=-

l5.0V

~

7

15t

0.8 v
V

_It I-t ;;. 20 J.Ls

a. 5et VOO to 0.8Y Measure VOL voltages at Pins 9 and 11.
b. Close 51. Force Vila to 0.8 V and VOO to 2.0 V. Apply
4 clock pulses to Pin 15. Open 51 and decrease VOO to
0.8 V. Measure VOL at Pin 13.

APPLICATIONS INFORMATION
Figure 45 specifies a typical application circuit for the
MC34010. Complete listings of external components are
provided at the end of this section along with nominal
component values.
The hook switch and polarity guard bridge configuration in Figure 45 is on"l of several options. If two
bridges are used, one for the tone ringer and the other
for speech and dialer circuits, then the hook switch can
be simplified. Component values should be varied to
optimize telephone performance parameters for each

MC34010
2-332

application. The relationships between the application
circuit components and certain telephone parameters
are briefly described in the following:
On-Hook Input Impedance
Rl, C17, and Z3 are the significant components for
on-hook impedance. C17 dominates at low frequencies,
Rl at high frequencies and Z3 provides the non-linearity
required for 2.5 V and 10 V impedance signature tests.
C17 must generally be';; 1.0 J.LF to satisfy 5.0 Hz impedance specifications.

MOTOROLA COMMUNICATIONS DEVICE DATA

Tone Ringer Output Frequencies
R3 and C13 control the frequency (fo) of a relaxation
oscillator. Typically fo = (R3C13 + S.O ,us)-l. The output tone frequencies are fo/l 0 and fo/a. The warble rate
is fo/640. The tone ringer will operate with fo from 1.0
kHz to 10 kHz. R3 should be limited to values between
150 k and 300 k.
Tone Ringer Input Threshold
After Rl, C17, and Z3 are chosen to satisfy on-hook
impedance specifications, R2 is chosen for the desired
ring start threshold. Increasing R2 reduces the ac input
voltage required to activate the tone ringer output. R2
should be limited to values between O.S k and 2.0 kn.
Off-Hook DC Resistance
R4 conducts the dc line current in excess ofthe speech
and dialer bias current. Increasing R4 increases the
input resistance ofthe telephone for line currents above
10 mAo R4 should be selected between 30 nand 120 n.
Off-Hook AC Impedance
The ac input impedance is equal to the receive amplifier load impedance (at RXO) divided by the receive
amplifier gain (voltage gain from V + to RXO). Increasing the impedance of the receiver increases the impedance ofthetelephone.lncreasing the gain ofthe receiver
amplifier decreases the impedance of the telephone.
DTMF Output Amplitude
R14 controls the amplitude of the row and column
DTMF tones. Decreasing R14 increases the level oftones
generated at V +. The ratio of the row and column tone
amplitudes is internally fixed. R14 should be greater
than 20 n to avoid excessive current in the DTMF output
amplifier.
Transmit Output level
Rl0 controls the maximum signal amplitude produced at V + by the transmit amplifier. Decreasing Rl0
increases the transmit output signal at V +. Rl0 should
be greater than 220 n to limit current in the transmit
amplifier output.
Transmit Gain
The gain from the microphone to the telephone line
varies directly with Rll. Increasing Rll increases the
signal applied to Rl0 and the ac current driven through
Rl0 to the telephone line. The closed loop-gain from
the microphone to the TXO terminal should be greater
than 10 to prevent transmit amplifier oscillations.
Note: Adjustments to transmit level and gain are complicated by the addition of receiver sidetone current to the transmit amplifier output current at
V +. Normally the sidetone current from the
receiver will increase the transmit signal (if the
current in the receiver is in phase with that in
Rl0). Thus the transmit gain and sidetone levels
cannot be adjusted independently.

MOTOROLA COMMUNICATIONS DEVICE DATA

Receiver Gain
Feedback resistor R6 adjusts the gain at the receiver
amplifier. Increasing R6 increases the receiver amplifier
gain.
Sidetone level
Sidetone reduction is achieved by the cancellation of
receiver amplifier input signals from R9 and R5. RS, R15,
and C6 determine the phase of the sidetone balance
signal in R9. The ac voltage at the junction of RS and
R9 should be lS0' out of phase with the voltage at V +.
R9 is selected such that the signal current in R9 is
slightly greater than that in R5. This insures that the
sidetone current in the receiver adds to the transmit
amplifier output current.
Hook-Switch Click Suppression
When the telephone is switched to the off-hook condition C3 charges from 0 volts to a 300 mV bias voltage.
During this time interval, receiver clicks are suppressed
by a low impedance at the RM terminal. If this click
suppression mechanism is desired during a rapid
succession of hook switch transitions, then C3 must be
quickly discharged when the telephone is on-hook, R16
and 53 provide a rapid discharge path for C3 to reset
the click suppression timer. R16 is selected to limit the
discharge current in 53 to prevent damage to switch
contacts.
Microprocessor Interface
The six microprocessor interface lines (DP, TO, M5,
DD, I/O, and Cl) can be connected directly to a port, as
shown in Figure 47. The DP line (Depressed Pushbutton)
is also connected to an interrupt line to signal the microprocessor to begin a read data sequence when storing
a number into memory. The MC34010A clock speed
requirement is slow enough (typically 20 kHz) so that it
is not necessary to divide down the processor's system
clock, but rather a port output can be toggled. This facilitates synchronizing the clock and data transfer, eliminating the need for hardware to generate the clock.
The DD pin must be maintained'at a logic "0" when
the microprocessor section is not in use, so as to permit
normal operation of the keypad.
When the microprocessor interface section is not in
use, the supply voltage at Pin 12 (A+) may be disconnected to conserve power. Normally the speech circuitry is powered by the voltage supplied at the V +
terminal (Pin 34) from the telephone lines. During this
time, A+ powers only the active pullups on the three
microprocessor outputs (DP, MS, and I/O). When the
telephone is "on-hook," and V + falls below 0.6 volts,
power is then supplied to the telephone speech and
dialer circuitry from A+. Powering the circuit from the
A+ pin permits communication with a microprocessor,
and/or use ofthe transmit and receiver amplifiers, while
the telephone is "on-hook."

MC34010
2-333

NS:

WO

Ww
......

C
.....
C

FIGURE 45 -

ELECTRONIC TELEPHONE APPLICATION CIRCUIT

S1

DTMF Pad
Row-Column Switch Closure
2
4
7

5

3
6

8

9

0

#

VCC

40
TRF

R1
2 R2
3
R3
4
R4
5
C1
6
C2
7
C3

TRO
TRI
TRS

FB
V+
BP

DP

Control

s::

I

Port
Aor B

VSS

Jl

o
o

o
s::
s::
c
z

o
~

6z

C/l

o
m
<

o

m

o
~
»

13
14
15
16
17

~

s;:

t

''''

-=-

clcf
-=- -=

C17

R1

37

o

TRC

C4

MC6800
System

E~TIP

38

36

R

TO

Z3

,~

39

LR
MC34010

35
34
33
32
31

LC

MS

V-

A+

VR

I/O

CAL

DD

RXO

C[

RXI

30
29
28

CR1

RM

CR2

STA

MM

TXO
TXI

MIC

TXL

R8 •••

,-"
C3

-L (;9.J.,t I

., fI..1 ,, ___ ,.. __

~R5

27

24

AGC

R14

R9
AA

3d

~~

S1, S2 controlled
by hook switch; Illustrated
in "on-hook"
condition.

n Electret Microphone

~~
R16
'RX used with 2-Terminal mike only.

RING

EXTERNAL COMPONENTS
(Component Labels Referenced to Figure 45)

Capacitors
Cl, C2
C3

Nominal
Value
100 pF
1.0 /LF, 3.0 V

Description
Ceramic Resonator oscillator capacitors.
Transmit limiter low-pass filter capacitor: controls attack and decay time of transmit peak limiter.

C4,C5

O.l/LF

Transmit amplifier input capacitors: prevent dc current flow into TXL pin and attenuate low-frequency
noise on microphone lead.

C6

0.05/LF

Sidetone network capacitor: provides phase-shift in sidetone path to match that caused by telephone
line reactance.

C7,CB

0.05/LF

Receiver amplifier input capacitors: prevent dc current flow into RM terminal and attenuates low frequency
noise on the telephone line.
VR regulator capacitor: frequency compensates the VR regulator to prevent oscillation.

C9

2.2 /LI'; 3.0 V

Cl0

O.Ol/LF

Cll

O.l/LF

DC load filter capacitor: prevents the dc load circuit from attenuating ac signals on V + .

C12

0.Q1 /LF

Telephone line bypass capacitor: terminates telephone line for high frequency signals and prevents
oscillation in the VR regulator.

C13

620 pF

Tone ringer oscillator capacitor: determines clock frequency for tone and warble frequency synthesizers.

C14

0.1 /LF

DTMF output feedback capacitor: ac couples feedback around the DTMF output amplifier which reduces
output impedance.

C15

4.7 /LF, 25 V

Tone ringer input capacitor: filters the rectified tone ringer input signal to smooth the supply potential
for oscillator and output buffer.

C16

1.0 /LI'; 10V

Tone ringer filter capacitor: integrates the voltage from current sense resistor R2 at the input of the
threshold detector.

C17

1.0 /LF, 250 Vac
Non-polarized

Tone ringer line capacitor: ac couples the tone ringer to the telephone line; partially controls the onhook input impedance of telephone.

Resistors

Receiver amplifier output capacitor: frequency compensates the receiver amplifier to prevent oscillation.

Nominal
Value

Description

Rl

6.B k

Tone ringer input resistor: limits current into the tone ringer from transients on the telephone line and
partially controls the on-hook impedance of the telephone.

R2

1.B k

Tone ringer current sense resistor: produces a voltage at the input of the threshold detector in proportion
to the tone ringer input current.

R3

200 k

Tone ringer oscillator resistor: determines the clock frequency for tone and warble frequency synthesizers.

R4

B2,l.0W

DC load resistor: conducts all dc line current in excess of the current required for speech or dialing
circuits; controls the off-hook dc resistance of the telephone.

R5,R7

150 k, 56 k

Receiver amplifier input resistors: couple ac input signals from the telephone line to the receiver amplifier;
signal in R5 subtracts from that in R9 to reduce sidetone in receiver.

R6
RB,R9
Rl0
Rll
R12, R13

200 k

Receiver amplifier feedback resistor: controls Ihe gain of the receiver amplifier.

1.5k,30k

Sidetone network resistors: drive receiver amplifier input with the inverted output signal from the transmitter; phase of signal in R9 should be opposite that in R5.

270

Transmit amplifier load resistor: converts output voltage of transmit amplifier into a current that drives
the telephone line; controls the maximum transmit level.

200 k
4.7 k, 4.7 k

Transmit amplifier feedback resistor: controls the gain of the transmit amplifier.
Transmit amplifier input resistors: couple signal from microphone to transmit amplifier; control the dynamic
range of the transmit peak limiter.
DTMF calibration resistor: controls the output amplitude of the DTMF dialer.

R14

36

R15

2.0 k

R16

100

Hook switch click suppression current limit resistor (optional): limits current when S3 discharges C3 after
switching to the on-hook condition.

RX

3.0 k

Microphone bias resistor: sources current from VR to power a 2-terminal electret microphone; RX is not
used with 3-terminal microphones.

Sidetone network resistor (optional): reduces phase shift in sidetone network at high frequencies.

MOTOROLA COMMUNICATIONS DEVICE DATA

MC34010
2-335

EXTERNAL COMPONENTS (continued)
Semiconductors

=

MDA101A, or equivalent,
or 4-1N4005
T1 = 2N4126 or equivalent
Zl = 18 V, 1.5 W, lN5931A
Z2 = 30 V, 1.5 W, lN5936A
Z3 = 4.7 V, 1/2 W, lN750
XR - muRata Erie CSB 500 kHz
Resonator, or equivalent
Piezo - PBL 5030BC Toko Buzzer
or equivalent
Bl

Electret Mic

Receiver

2 Terminal, Primo EM-95 (Use RX)
or equivalent
3 Terminal, Primo 07A181P (Remove RX)
or equivalent

Primo Model DH-34 (300 0) or equivalent

Motorola Inc. does not endorse or·warrant the suppliers referenced.

MC34010
2-336

MOTOROLA COMMUNICATIONS DEVICE DATA

MOTOROLA

-

SEMICONDUCTOR
TECHNICAL DATA

MC34012·1
MC34012·2
MC34012·3

TELEPHONE TONE RINGER

TELEPHONE
TONE RINGER

• Complete Telephone Bell Replacement Circuit with Minimum
External Components
• On-Chip Diode Bridge and Transient Protection
•

Direct Drive for Piezoelectric Transducers

•

Base Frequency Options-MC34012-1: 1.0 kHz
MC34012-2: 2.0 kHz
MC34012-3: 500 Hz

BIPOLAR LlNEAR/12L

• Input Impedance Signature Meets Bell and EIA Standards
•

Rejects Rotary Dial Transients

PLASTIC PACKAGE
CASE 626

APPLICATION CIRCUIT

180 k
1 RG
e-___--I
T·

4.7 k

RC 1-'8==---___-----'

1. 0 l'F

I,P_~_-V~_~f_ _+-___~2 ACl
~

C

_________-+___~3 AC2

5.01'F

RF 1-'7'---_-,
1.01'F
+ 10V

+ 25 V

RS 1-6=---_-.

Ring
1.8 k
RI

5

Piezo Sound
Element

MC34012-1: C = 1000 pF
MC34012-2: C = 500 pF
MC34012-3: C = 2000 pF

MOTOROLA COMMUNICATIONS DEVICE DATA

MC34012·1.MC34012·2.MC34012·3
2·337

APPLICATION CIRCUIT PERFORMANCE
Characteristic
Output Tone Frequencies
MC34012-1
MC34012-2
MC34012-3
Warble Frequency

Typical Value

Units

83211040

Hz

1664/2080
416/520
13

Output Voltage
(VI;;' 60 V rms , 20 Hz)

V p_p

20

Output Duty Cycle

50

%

Ringing Start Input Voltage (20 Hz)

36

V rms

Ringing Stop Input Voltage (20 Hz)

28

V rms

Maximum ac Input Voltage (,;; 68 Hz)

150

V rms

Impedance When Ringing
VI =40Vrms, 15 Hz
VI = 130 V rms , 23 Hz

20
10

kn

I mpedance When Not Ringing
VI = 10 V rms, 24 Hz
VI = 2.5 V rms, 24 Hz
VI = lOV rms , 5.0 Hz
VI = 3.0 V rms, 200-3200 Hz
Maximum Transient Input Voltage
(T';; 2.0 ms)

28
>1.0
55
>1.0

kn
Mn
kn
Mn

1500

V

PIN DESCRIPTIONS
Name

Description

AC1,AC2

The input terminals to the full-wave diode bridge. The ac ringing signal from the telephone line
energizes the ringer through this bridge.

RS

The positive output of diode bridge to which an external current sense resistor is connected.

RI

The positive supply terminal for the oscillator, frequency divider and output buffer circuits.

RF

The terminal for the filter capacitor used in detection of ringing input signals.

RO

The tone ringer output terminal through which the sound element is driven.

RG

The negative output of the diode bridge and the negative supply terminal of the tone generating

RC

The oscillator terminal for the external resistor and capacitor which control the tone ringer
frequencies.

circuitry,

MC34012-1.MC34012-2.MC34012-3
2-338

MOTOROLA COMMUNICATIONS DEVICE DATA

ELECTRICAL CHARACTERISTICS (TA = 25"C)
Characteristic

Test

Ringing Start Voltage
(VStart = VI @ Ring Start)
VI>O
VI----w-1f--Q'-::-_._--,

RS

C4
RI

RF-----,

I
I

I
Ring

I
I
I

7.0V

>-----9-:-=-------'

Threshold
Comparator

I
I
I
I
I
RO

I

R21

I
I

I

Warble

~

I

I

Piezo
Sound
Element

L _______ Frequen~ ~~r-iG_~_ _ _ _ _ ..J

MOTOROLA COMMUNICATIONS DEVICE DATA

MC34012-1.MC34012-2.MC34012-3
2-339

CIRCUIT DESCRIPTION

The MC34012 Tone Ri nger derives its power supply by
rectifying the ac ringing signal. It uses this power to
activate a tone generator and drive a piezo-ceramic
transducer. The tone generation circuitry includes a
relaxation oscillator and frequency dividers which
produce high and low frequency tones as well as the
tone warble frequency. The relaxation oscillator frequency fo is set by resistor R2 and capacitor C2
connected to pin RC. The oscillator will operate with fo
from 1.0 kHz to 10 kHz with the proper choice of external
components (See Figure 1).
The frequency of the tone ringer output signal at pin
RO alternates between fo/4 to fo/5. The warble rate at
which the frequency changes is f o /320 for the
MC34012-1, f o /640 for the MC34012-2, or fo/160 for
the MC34012-3. With a 4.0 kHz oscillator frequency, the
MC34012-1 produces 800 Hz and 1000 Hz tones with a
12.5 Hz warble rate. The MC34012-2 generates 1600 Hz
and 2000 Hz tones with a similar 12.5 Hz warble
frequency from an 8.0 Hz oscillator frequency. The
MC34012-3 will produce 400 Hz and 500 Hz tones with
a 12.5 Hz warble rate from a 2.0 kHz oscillator frequency.
The tone ringer output circuit can source or sink 20 mA
with an output voltage swing of 20 volts peak-to-peak.
Volume control is readily implemented by adding a
variable resistance in series with the piezo transducer.
Input signal detection circuitry activates the tone
ringer output when the ac line voltage exceeds
programmed threshold level. Resistor R3 determines the
ringing signal amplitude at which an output.?ignal will
be generated at RO. The ac ringing signal is rectified by
the internal diode bridge. The rectified input signal

produces a current through R3 which is input at terminal
RI. The voltage across resistor R3 is filtered by capacitor
C3 at the input to the threshold circuit. When the voltage
on capacitor C3 exceeds 1.7 volts, the threshold comparator enables the tone ringer output. Line transients
produced by pulse dialing telephones do not charge
capacitor C3 sufficiently to activate the tone ringer
output.
Capacitors Cl and C4 and resistor Rl determine the
10 volt, 24 Hz signature test impedance. C4 a Iso provides
filtering for the output stage power supply to prevent
droop in the square wave output signal. Six diodes in
series with the rectifying bridge provide the necessary
non-linearity for the 2.5 volt, 24 Hz signature tests.
An internal shunt voltage regulator between the RI
and RG terminals provides dc voltage to power output
stage, oscillator, and frequency dividers. The dc voltage
at RI is limited to approximately 22 volts in regulation. To
protect the IC from telephone line transients,an SCR is
triggered when the regulator current exceeds 50 mA.
The SCR diverts current from the shunt regulator and
reduces the power dissipation within the IC.

EXTERNAL COMPONENTS
Rl

Line input resistor. R1 controls the tone

ringer input impedance. It also influences
ringing threshold voltage and limits current
from line transients.

IRange: 2.0 k!1 to 10 k!1).
Cl

Line input capacitor. Cl ae couples the tone

ringer to the telephone line and controls
ringer input impedance at low frequencies.

FIGURE 1 - OSCILLATOR PERIOD (1/'01 versus
OSCILLATOR R2 C2 PRODUCT

(Range: 0.4 I'F to 2.0 I'FI.
R2

Oscillator resistor.

(Range: 150 k!1 to 300 k!1).
C2

Oscillator capacitor.
(Range: 400 pF to 2000 pFI.

R3

Input current sense resistor. R3 controls the
ringing threshold voltage. Increasing R3

80 0

..-/

-~ 60 0

V

3

o

"-

decreases the ring-start voltage.

(Range: 0.8 k!1 to 2.0 k!1l.

../

- 400

C3

,./'
,./'

200
./'

V

100

150 k~R2 ~ 300 k
- I-400 pF ~ C2 ~ 2000 pF

Ringing threshold filter capacitor. C3 filters the
ac voltage across R3 at the input of the ringing
threshold comparator. It also provides dialer
transient rejection.

(Range: 0.5 I'F to 5.0 I'F).
200

300
R2C211.-----,

.----}

~~ceiver

Ring 0 - - - - - '

To

I-I--t~ Dialer

Circuit

Input

MOTOROLA COMMUNICATIONS DEVICE DATA

From
Microphone

Input

PulsefTone
Select

MC34014
2-345

PIN DESCRIPTION (See Figure 1)
Pin # Pin#
SOIC DIP Name
1

1

MIC

Description
Microphone negative supply. Bias current from the electret microphone is

Pin# Pin#
SOIC DIP Name
10

V-

Negative supply. The most negative
input connected to Tip and Ring through
the polarity guard diode bridge.

12

11

VR

Regulated voltage output. The VR volt~
age is regulated at 1.2 V and biases the
microphone and the-speech circuits. An
internal series pass PNP transistor allows
for regulation with a line voltage as low
as 1.5 V. Capacitor C8 stabilizes the
regulator.

13

12

LC

DC load capacitor. An external capacitor
C7 and an internal resistor form a low
pass filter between V + and LR to pre~
vent ac signals from being loaded by the
de load resistor R5. Forcing LC to Vwill turn off the de load current and
increase the V + voltage.

14

13

LR

DC load resistor. Resistor R5 from LR to
V - determines the de resistance of the
telephone, and removes power dissipa~
tion from the chip. The LR pin is biased
2.8 volts below the V + voltage (4.5 volts
in the tone dialing mode).

15

14

V+

Positive supply. V + is the positive line
voltage (from Tip & Ring) through the
polarity guard bridge. All sections of the
MC34014 are powered by V +.

17

15

VDD

VOD regulator. VDO is the output of a
shunt type regulator with a nominal volt~
age of 3.3 V. The nominal output current
is increased from 550 /-LA to 2 mA when
dialing. Capacitor C9 stabilizes the regu~
lator and sustains"the VDO voltage dur~
ing pulse dialing.

18

16

TI

Tone input. The DTMF signal from a
dialer circuit is input at TI through an
external resistor R7. The current at TI is
amplified to drive the line at V +.
Increasing R7 will reduce the DTMF out~
put levels. The input impedance at TI is
nominally 1.25 kO.

19

17

MS

Mode select. This pin is connected
through an internal 600 k!1 resistor to the
base of an NPN transistor. A Logic "1"
(>2.0 V) selects the pulse dialing mode.
A Logic "0" «0.3 V) selects the tone
dialing mode.

20

8

MT

Mute input. MT is connected through an
internal 100 k!l resistor to the base of a
PNP transistor, with the emitter at VOD.
A Logic "0" «1.0 V) will mute the network for either pulse or tone dialing. A
Logic "1" (>VDD - 0.3 V) puts the
MC34014 into the speech mode.

returned to V - through this pin, through
an open collector NPN transistor whose
base is controlled by an internal mute
signal. During dialing, the transistor is
off, disabling the microphone.
2

2

TXI

Transmit amplifier input. Input impedance
is 10 kO. Signals from the microphone

3

3

TXO

Transmit amplifier output. The ae signal
current from this output flows through
the VR series pass transistor via RS to
drive the line at V +. Increasing R9 will
decrease the signal at V +. The output is
biased at =0.65 V to allow for maximum
swing of ae signals. The closed loop
gain from TXI to TXO is internally set at
26 dB.

4

4

STA

Sidetone amplifier output. Input to this
amplifier is TXO. The signal at STA can~
eels the sidetone signals in the receive
amplifier. The signal level at STA
increases with loop length.

5

5

CC

Compensation Capacitor. A capacitor
from CC to ground will compensate the
loop length equalization circuit when
additional stability is required. In most
applications, CC remains open.

7

6

EQ

Equalization amplifier output. A portion
of the V + signal is present on this pin to
provide negative feedback around the
transmit amplifier. The feedback
decreases with increasing loop length,
causing the ac impedance of the circuit
to increase.

S

7

RXI

Receive amplifier input. Input impedance
is >100 k!1. Signals from the line and
sidetone amplifier are summed at RXI.

9

8

RXO

Receive Amplif.ier output. RXO is biased
by a 2.5 mA current source. Feedback
maintains the de bias voltage at =0.65 V.
Increasing R4 (between RXO and RXI)
will increase the receive gain. C4 stabi~
lizes the amplifier. C3 couples the signals
to the receiver. The 2.5 mA current
source is reduced to 0.4 mA when
dialing.

are input through capacitor C5 to TXI.

10

MC34014
2·346

9

RMT

Receiver Mute. The ac receiver current is
returned to V - through an open collec~
tor NPN transistor and a parallel 10 kfl
resistor. The base of the NPN is con~
trolled by an internal mute signal. During
dialing the transistor is off, leaving the
10 k!1 resistor in series with the receiver.

Description

11

MOTOROLA COMMUNICATIONS DEVICE DATA

FIGURE 1 - TEST CIRCUIT

C8
2.0
R9
200

R8
500 n
EQ

n

VR
11
Equalization TXO 3
Amp

~

Tip 0 - - - - - - - )...

Ring
18 V

6

R6
10 k
C5
0.05 2

-=

V+
14

10 k

TXI
10 k

Transmit
Amp

R1
150 k
R5
47, 'I2W

13 LR
C7
0.2
LC
12

-=

~

CC
R2
STA 10 k

R7
22 k

200 k
DTMF Input '>-~\NI...-~......._-~~~\NI___---<_~ V +

4

C2
0.05

RXI

R4
33 k

VR

1.25 k

3.75 k

C3

RXO

Driver

C4
JO.05

50

Receiver
(150 nl

V+
9 RMT
VDD
VDD
Output ...----<;;>--.....- - -.....
C9
15

0.1l

600 k

Mute

MT

18

>--~~~~-----------~

PulsefTone >-_--"M"'S"'-<>'-1'-7_ _ _ _ _ _ _ _ _ _ _ _ _ _ _....I
Select

NOTE: Pin numbers are for 18 pin DIP.

MOTOROLA COMMUNICATIONS DEVICE DATA

MC34014
2·347

ABSOLUTE MAXIMUM RATINGS (Voltages referred to V -, T A = 25'C) (See Note 1.)
Value

Parameter
V+ Voltage

Units

-1.0, +18

Vdc

-1.0, +6

Vdc

VLR

-1.0, V+ - 3.0

Vdc

MT, MS Inputs

-1.0, VDD +1.0

Vdc

VDD (externally applied, V +

=

0)

Storage Temperature

-65, + 150

'C

..

NOTE 1: De~lces should not be operated at these values. The "Recommended Operating Conditions" provide

conditions for actual device operation.
RECOMMENDED OPERATING CONDITIONS
Value

Units

+1.5to +15
+3.3 to +15

Vdc
Vdc

ITXO (instantaneous)

o to 10

mA

Ambient Temperature

-20 to +60

'C

Parameter
V + Voltage (Speech Mode)
(Tone Dialing Mode)

ELECTRICAL CHARACTERISTICS (Refer to Figure 1) (TA
Parameter

=

25'C)

I

Symbol

Min

Typ

Max

2.6
3.0
7.0
4.1
4.6

3.2
3.7
8.2
4.9
5.4

3.8
4.4
9.5
5.7
6.2

4.0
5.5
6.0

6.6
8.4
8.8

8.5
12.5
14.0

-

-

Units

LINE INTERFACE
V+ Voltage
Iloop = 20 mA (Speech/Pulse Mode)
Iloop = 30 mA (Speech/Pulse Mode)
Iloop = 120 mA (Speech/Pulse Mode)
Iloop = 20 mA (Tone Mode)
11000
30 mA (Tone Mode)

V+

V + Current (Pin 12 Grounded)
V+ = 1.7 V (Speech Mode)
V+ = 12 V (Speech/Pulse Modes)
V+ = 12 V (Tone Mode)

1+

=

LR Level Shift (V + -' VLR)
(Speech/Pulse Mode)
(Tone Mode)

IlVLR

LC Terminal Resistance

Vdc

mA

Vdc

-

~

2.7
4.3

RLC

36

57

94

kG

VR
IlVRLD
IlVRLN

1.1

1.2
20
25

1.3

-

-

Vdc
mV
mV

VDD

3.0

3.3

3.8

Vdc

-

Vdc
mV

VOLTAGE REGULATORS
VR Voltage (V+ = 1.7 V)
Load Regulation (0 mA < IR
Line Regulation (2.0 V < V +

< 6.0 mAl
< 6.5 V)

VDD Voltage (V + = 4.5 V)
Load Regulation (0 < IDD < 1.6 mAl
(Dialing MO = 20 mAl (See Figure 4)
Receive gain change as Iloop is increased to 60 mA
Distortion

-16
-5.0

-

Typ

Max

2.4
3.9
4.6
5.6
6.6

-

Vdc

-

30
-4.5
2.0
11

31
-3.6

dB
dB
%
dBrnc

-15
-3.0
2.0

-13
-2.0

dB
dB
%

-

Sidetone Level
VRXON + (Figure 3)

dB
Iloop
Iloop

=
=

-

20 mA
60 mA

Sidetone Cancellation

[V~~O

Unit

-

-

-36
-21

20

26

-

dB

3.2

4.8

S.2

dB

- [VRXO.
V+ (Figure 3) ] dB Iloop = 20 mA

(Figure 4)] dB

DTMF Driver
V+Nin (Figure 2)

11000 = 20 mA

AC Impedance
Speech mode (incl. CS. See Figure 4)
Zac = (600)V+/(VS - V+)
Tone mode (including C6)

-

= 20 mA
= 60 mA
20 mA < 11000 < 60 mA
Iloop
Iloop

n

-

750
300
1650

-

NOTE: TYPlcals are not tested or guaranteed.

FIGURE 3 - TRANSMIT AND SIDETONE LEVEL TEST

FIGURE 4 -

AC IMPEDANCE. RECEIVE AND SIDETONE
CANCELLATION TEST

150 k
,--'IN'v-oO V +
10 k

0.05

STA

V+~~-~----,

0.05

10 k

V+r-~--~--,
MC34014

r:-:-::--'V'>Ar-..,STA

v+ o--'VIl'v-~h'----4 RXI

t------jRXI
33 k

"""""",,--.----iRXO

cel-

0.02

~:::~ \oop

LR
"\. 250

mV~ms

(VS)

1.0 kHz

MC34014
2·350

MOTOROLA COMMUNICATIONS DEVICE DATA

DESIGN GUIDELINES (Refer to Figure 1)
age versus loop current characteristics. and .provides the required regulated voltages for internal
and external use.
The dialer interface provides three modes of operation: speech (non-dialing). pulse dialing. and tone
(DTMF) dialing. When switching to either dialing mode
some parameters of the various sections are changed
in order to optimize the circuit operation for that mode.
The following table summarizes those changes:

INTRODUCTION
The MC34014 is a speech network meant for connection to the Tip & Rill9 lines through a polarity guard
bridge. The circuit incorporates four amplifiers: transmit. receive. sidetone. and equalization. Some parameters of each amplifier are set by external components.
and in addition. the gains of the sidetone and equalization amplifiers vary with loop current.
The line interface portion determines the dc volt-

TABLE 1 -

OPERATING PARAMETERS AS A FUNCTION OF OPERATING MODE
Speech

Pulse

2.7 V

2.7 V

4.3 V

550pA

2.0 mA

2.0 mA

Transmit Amplifier

Functional

Functional

Inoperative

MIC Switch (Pin 11

On

Off

Function
LR Level Shift (V + - VLR)
VDD Source Current

Equalization Amplifier
Sidetone Amplifier
Receive Amplifier Output Current
RMT (Pin 9) Impedance
DTMF Amplifier
CC Voltage

Tone

Off

See Transfer Curves -

Figure 8

See Transfer Curves -

Figure 6

2.5 mA

400pA

8.00

10 kn

10 kO

Inoperative

Inoperative

Functional

VLRI3

VLR

VLR

400pA

resistance of the circuit. raising the voltage at V + to
ensure adequate voltage at VOO for the external tone
dialer. See Figure 7 for typical voltage versus loop current characteristics.
Capacitor C7 at Pin 12 provides high frequency rolloff
(above 10Hz) so that R5 does not load down the speech
and DTMF signals.
The voltage at VR is an internally regulated 1.2 volt
supply which provides the bias currents for the microphone and the transmit amplifier output (Pin 3). as well
as internal bias for the various amplifiers. Capacitor Ca
stabilizes the regulator. The use of an (internal) PNP
transistor allows VR to be regulated with a V + voltage
as low as 1.5 volts.

DC LINE INTERFACE (Figure 5)
The dc line interface circuit (Pins 10. 12-14) sets the
dc voltage characteristics with respect to the loop current. The loop current enters at Pin 14 where the internal
circuitry of the MC34014 draws 5-6 mAo Pin 3 sinks
(typically) 3 mA through Rg. The remainder of the loop
current is passed through Q301 and R5' The resulting
voltage across the entire circuit is therefore equal to the
voltage across R5. plus the level shift voltage from Pin
13 (LR) to Pin 14 (V +). nominally 2.7 volts in the speech
and pulse modes. In the tone mode. the level shift increases to 4.3 volts. the internal current changes slightly
(Figure 6). and the current required at Pin 3 decreases
to near zero. These changes increase the equivalent dc
FIGURE 5 -

DC UNE INTERFACE

--

Iloop
Tip 0 - - - - - - .

Ring 0 - - - - - - '

5-6 mA
(Internal
Circuit)
R5
470

LC

=
MOTOROLA COMMUNICATIONS DEVICE DATA

*

C7

0.2 p.F

10

V-

=
MC34014
_ ." 2-351

FIGURE 6 - INTERNAL CURRENT versus VOLTAGE

FIGURE 7 - CIRCUIT VOLTAGE versus LOOP CURRENT

10

10

,....-

/'
TONE MODE

8.0
6.0

V

V

V

,.... .Y
1\
PULSE, SPEECH MODES

V

V

VDD = 3.0 V
R5j R7'IR9 =IOPEr- ' - -

I

oV
o

2.0

TO~E ~IODE

6.0

~

~
~4.0

6.0
8.0
V+ {VOLTSI

4.0

10

........-V

I

2.0

.

V

,....-

a

+
>

I

2.0

8.0

V V

,....- V

........-

........- "'\

V

SPEECH, PULSE MODES

........-

I
I

R5 1=47n I-- I-R9 = 200n
R7 1= O~EN I-- ' - -

II

12

V

20

40

60

80

100

120

Iloop ImAI

TRANSMIT AMPLIFIER
The transmit amplifier (from TXI to TXO) is inverting,
with a fixed internal gain of 20 VN (26 dB), and a typical
input impedance of 10 k!l (Figure 8). The input bias currents are internally supplied, allowing capacitive coupling of the microphone signals to the amplifier.
In the speech and pulse modes, the dc bias level at
TXO is typically 0.52 x VR (=0.63 V), which permits
the output to swing 0.55 volts in both positive and
negative directions without clipping. The ac voltage
signal at TXO (the amplified speech signal) is converted to an ac current by Rg. The ac current passes

through the VR series pass transistor to V +, modulating the loop current. The voltage signal at V + is out
of phase with the signal at TXI.
In the tone dialing mode, the TXO dc bias level is
clamped at approximately VR-10 mY, rendering the amplifier inoperative. This action also reduces the TXO bias
current from 3.0 mA to less than 125 pA.
MIC (Pin 1) is connected to an open-collector NPN
transistor, and provides the ground path for the microphone bias current. In either dialing mode, the transistor
is off, disabling the microphone.

FIGURE 8 - TRANSMIT SECTION
Tip 0 - - - - - ,

Ring O - - - - . . . J

VR
500

R8

R9
200 n

TXO
STA
R3
R2
Cl

Note: All capacitor values in JLF.

MC34014

2-352

:;J; 0.05

To
Receive
Circuit

MOTOROLA COMMUNICATIONS DEVICE DATA

SIDETONE AMPLIFIER
The sidetone amplifier provides inversion of the
TXO signal for the reduction of the sidetone signal at
the receive amplifier (Figure 8). Resistors R2 and R3
determine the amount of sidetone cancellation. Capacitor Cl provides phase shift to compensate for the
phase shift created by the complex impedance of the
Tip & Ring lines.
The gain of the sidetone amplifier varies with the voltage at LR (Pin 13), in effect making it a function of the
loop current. The maximum gain is -15 dB (0.17 VN)
at low loop currents, and the minimum gain is -21 dB
(0.09 VN) at high loop current (see Figure 9 for transfer
curves). For example, using 47 n for R5, the gain would
begin to decrease at =30 mA, and would stop decreasing at =57 mA (speech mode). The dc bias voltage at
STA (Pin 4) changes slightly (=50 mV) with variations
in loop current. The output is inverted from TXO, which
is the input to this amplifier. Since the transmit amplifier
is inoperative in the tone dialing mode, the sidetone
amplifier is also inoperative in that mode.

FIGURE 9 - SIDETONE AMPLIFIER GAIN
-15
.......

-16

\ It-PULSEMODE

_-17
~
en
e -18

"

\

1\

\

l-

e

~

-19

z

1\

1\

ill -20

...'" -21

SPEECH MODE- ~

I\,

-22
0.2

0.6

1.0

loop current, the receive gain will vary by =1.5 dB. If
capacitor Cl is not used, the above equation is simplified by deleting the terms containing XC.
The output at RXO is inverted from V + in the receive
mode. In the transmit mode, the V + -to-RXO phase relationship depends on the amount of sidetone cancellation (determined by R2 and R3 and Cl), and can vary
from 0° to 180°.
In the speech mode, the output current capability (at
RXO) is typically 2.0 mA. In either dialing mode, the
current capability is reduced to 400 p.A in order to reduce
internal current consumption. This feature is beneficial
when this device is used in conjunction with a line-p'owered speakerphone circuit, such as the MC34018, where
the majority of the loop current is needed for the
speakerphone.
RMT (Pin 9) is the return path for the receiver's ac
current. This pin is internally connected to an open collector NPN transistor, paralleled by a 10 kn resistor. In
the speech mode, the transistor is on, providing a low
impedance from RMT to ground. In either dialing mode,
the transistor is off, muting the receive signal. This prevents loud "clicks" or loud DTMF tones from being
heard in the receiver during dialing. When switching
from either dialing mode to the speech mode (MT
switches from low to high), the RMT pin switches back
to a low impedance after a delay of 2-20 ms. The delay
reduces clicks in the receiver associated with switching
from the dialing to speech mode.

1.4
VLR IVOLTSI

1.8

2.2

2.6

RECEIVE AMPLIFIER
The gain of the receive amplifier (from V + to RXO)
is determined according to the following equation (refer
to Figure 10):
VRXO = R4 + (XC//R2) (AEQ) (ATXO) (ASTA)xRAXR4
Rl
((XC//R2) + R3) (RA + R6) x R2
V+
Where RA = RsI/10 kn (10 kn = Rin of Tx Amp)
AEO = Gain of Equalization Amp
ATXO = Gain of Transmit Amp (20 VN)
ASTA = Gain of sidetone Amp
Xc = Impedance of Cl at frequency of
interest
The waveform at STA (Pin 4) is in phase with that at
V + (for receive signals), hence the plus sign between
the terms. Due to the variations of AEO and ASTA with

MOTOROLA COMMUNICATIONS DEVICE DATA

EOUILIZATION AMPLIFIER
The equalization amplifier gain varies with loop. current, and is configured in the circuit so as to cause a
variation of the network ac impedance (when looking in
from the Tip & Ring lines). The gain varies with the
voltage at LR (Pin 13), in effect making it a function of
the loop current. The maximum gain is -2.5 dB (0.75
VN) at high loop current, and the minimum gain is -12
dB (0.25 VN) and low loop current (see Figure 11 for
transfer curve). For example, using 47 n for R5, the gain
would begin to increase at =30 mA, and would stop
increasing at =57 mA (speech mode). The output signal
is in phase with the signal at V +, which is the input to
this amplifier.
The dc bias level at EO (Pin 6) varies with the voltage
at LR (Pin 13) according to the curve of Figure 12. In
most applications, this level shift is of little consequence, and may be ignored. If a particular circuit configuration should be sensitive to the shift, however,
the output signal at EO may be ac coupled to the rest
of the circuit.
The equalization amplifier remains functional in all
three modes, although in the tone mode, its function
has no consequence when the circuit is configured as
shown in Figure 1.
VDD REGULATOR
The VDD regulator is a shunt type regulator which
supplies a nominal 3.3 volts for external dialers, and/or

MC34014
2-353

other circuitry. In the speech mode, the output current
capability at Pin 15 is typically 550 /LA. In either dialing
mode, the current capacity is increased to 2.0 mA.
VDO will be regulated whenever V+ is >300 mV
above the regulated value. As V + is lowered, and the
internal pass transistor becomes saturated, the circuit
steers current away from the external load through an
internal current source, in order that the VOO capacitor
(C9) does not load down speech and DTMF signals at
V +. As V + is lowered below 1 volt, Pin 15 switches
to a high impedance state to prevent discharging of
any storage capacitors, or batteries used for memory
retention.
The VOO voltage is unaffected by the choice of operating mode.

V+
Vi

(RE, R7 in k.{l)
where RE = RLII2 k.{l (2 k.{l
impedance)

=

internal dynamic

Using 22 k.{l for R7, and 600 .{l for RL, the voltage
gain is a nominal 4.3 dB. The minimum loop current
at which the circuit of Figure 1 will operate without
distortion is 12 mA.
The OTMF amplifier is functional only in the tone
dialing mode, and the waveform at V+ is inverted
from that at TI. The TI pin requires a dc bias current
(into the pin) of 20-50 /LA, which may be supplied by
the Tone dialer circuit, or by using the biasing scheme
of Figure 14.

DIALER INTERFACE
The dialer interface consists of the mode control
pins, MT and MS (pins 18 and 17), and the DTMF current amplifier.
The MT pin, when at a Logic "1" (> VOO - 0.3 V),
sets the circuit into the speech mode, independent of
the state of the MS pin. When the MT pin is at a Logic
"0" « 1.0 V), the dialing mode is determined by the MS
pin. When MS is at a Logic "1" (> 2.0 V), the circuit is
in the pulse dialing mode, and when at a Logic "0" «
0.3 V) the tone (OTMF) mode is in effect.
The input impedance of the MT pin is typically 100
k.{l, with the input current flowing out of the pin
(from VOD). The input impedance of the MS pin is
typically 600 k.{l, and the input current flows into the
pin (Figure 1).
The OTMF amplifier (Figure 13) is a current amplifier
which transmits OTMF signals to the V + pin, and consequently onto the Tip & Ring lines. Waveforms from a
OTMF dialer are input at TI (Pin 16) through a current
limiting resistor (R7)' Negative feedback around the amplifier reduces the overall gain so that return loss specifications may be met. The voltage gain is calculated
using the following equation:

Tip 0 - - - - - ,

80 RE
(1 + 0.795R7 + 0.4RER7)

CC(PIN 5)
The CC pin (Compensation Capacitor) has two functions: 1) to provide equalization loop stability where the
normal stabilizing components are ineffective; and 2)
to allow optional control of the equalization functions.
In most applications, the capacitor at LC (Pin 12) provides the required stability, and no further compensation is required. In applications where changes are
forced at Pin 12 and/or 13 (e.g., see Figure 23), the LC
capacitor's effectiveness may be lost. The addition of a
10 /LF capacitor to Pin 5 will provide the required additional compensation.
The CC pin may be used to force the loop length compensation circuits to specific modes. Grounding CC will
set the sidetone and equalization amplifiers at the low
loop current values. Connecting" CC to VR will set the
amplifiers at the"high loop current values.
Variations in the curves of Figures 9 and 11 may be
obtained by using external resistors from LR to CC, and
from CC to V - .

FIGURE 10 - RECEIVE CIRCUIT
C2

R1

C3

R4

Receiver
Ring 0 - - - - - '

RXI

RXO

R3
9

STA

10

RMT

k

4

V+

EQ

TXI

R6

MC34014
2-354

R8
MOTOROLA COMMUNICATIONS DEVICE DATA

FIGURE 11 -

EQUALIZATION AMPLIFIER GAIN

FIGURE 12 -

5.0

-2,0

,/

-3,0

I

-4,0

r f-

-5,0

4,0

V

PULSE MODE

/

~-8,0

SPEECH MODE

~ 3.0 -PULSE MODE_

10

Z.
w

I

1,0

II

-11

/

-12
0.2

,../
0,6

1.0

1.4

V

~
!3 2,0
§;
@

r-I

II

/
,I

~-9,0

,../

2.2

1,8

/

SPEECH MODE

/

.L.I--f/
1.0

VLR (VOLTS)

FIGURE 13 -

~

II- -

/

o
o

2.6

V

. /V

iJi

/
/

f2+ -7,0

"C _

/

I

8-6.0

co

EQ (PIN 6) DC VOLTAGE

2.0
3.0
VLR (VOLTS)

4.0

5.0

DTMF TONE DIALER

RL

Office
or
PBX

VDD
15

VDD
1

2

3

4

5

6

7

8

9

*

0

#

Keypad

Vi

Tone
Dialer

~

R7
22 k

Output

(Equivalent Dynamic
Impedance of Internal
Circuitry)

TI
16

MT

Mute
18

V-

=

3.75 k
1.25 k

1.25
k
10

=

FIGURE 14 -

50

=

RL = Phone Line ac
Impedance

INPUT BIASING

VDD
75 K
DTMF
R7
TI
Input >-----1f----'V'.IV-4-16-<)
0.1

MOTOROLA COMMUN)CATIONS DEV(CE DATA

MC34014
2-355

APPLICATIONS INFORMATION

AC IMPEDANCE
One of the basic problems with early telephones is
that the performance varied with different line lengths
(distance from the Central Office to the telephone). If a
particular phone were optimized for short loops and
then connected to a long loop, both the transmitted and
receive signals would be difficult to hear. On the other
hand, phones optimized for long loops would then be
annoyingly loud on short loops. The process of equalization is one whereby the performance is forced to vary
with loop length inversly to the expected variations.
Monitoring of loop length is accomplished by monitoring the loop current at the telephone. In the MC34014,
loop length equalization is provided by varying the ac
impedance of the telephone circuit. In this manner the
MC34014 mimics a passive network, with varistors providing the equalization.
Figure '5 depicts the situation in the receive mode.
The receive signal coming from the Central Office is Vs
and is independent of the loop length. ZR is the ac
impedance of the Central Office, nominally 900 n. Zl is

the characteristic impedance of the phone line, and is
a nominal 600 n. The signal applied to the line (V1) is
therefore a portion of VS. That signal is attenuated by
the distributive impedance of the phone line, with a resulting signal V2 at the telephone. The amplitude of V2
depends on the amount of attenuation, the impedance
ofthe phone line at the telephone and the ac impedance
of the telephone (Zac!, according to:
V2

V;x Zac

= --'---=Zac

+ Zl

where V, is the equivalent signal source at the receive end of the phone line, providing the signal V2
through the impedance equal to the characteristic
impedance of the line (Zl). The value of V, depends
on how much V1 has been attenuated by the length
of phone line. By increasing Zac on long loops, V2 is
a greater portion of V" resulting in a stronger receive
signal at the telephone.

FIGURE 15 - RECEIVE MODE

Central
Office

Phone Line

r----'

t

/.IlllD w
I

ZR
V1

L ____

.

DDllD w

I I

Ij~... - I

ODllD

N

DDDD ......

r

Telephone

r---- 1

t

V2

I ODDD~~

Figure 16 depicts the situation in the transmit mode.
In this mode, the MC34014 is an ac current source, with
a finite output impedance, modulating the loop current.
The voltage signal V, is therefore equal to the ac signal
current acting on Zac in parallel with the characteristic

Zac

IL ____

impedance of the phone line (Zl). The signal is attenuated by the distributive impedance of the phone line,
and so only a portion of that signal (V2) appears at the
Central Office. By increasing Zac on long loops, V, is
increased, resulting in a higher signal level at V2.

FIGURE 16 - TRANSMIT MODE

Central
Office

Telephone

r--------

i

I
I
I

r----'I
I
I
I

I

I
I

I
I

I

Zac

I
I

I
IL _______ _

MC34014

2-356

900

I
I

I

I
I
I

_ ___ .JI

MOTOROLA COMMUNICATIONS DEVICE DATA

The ac impedance of the telephone circuit is determined by the transmit amplifier, equalization amplifier,
and external resistors RS, RS, and RS. In Figure 17, a
portion of the receive signal at V + appears at EQ. That
signal is reduced at TXI by the RS-RS divider (the electret
microphone is a high impedance). The signal at TXI is
then amplified by 20, and that signal (at TXQ) is converted to an ac current by RS. The ac impedance of the
circuit is therefore V +/ITXQ, and is defined by the following equation:
Z
_ (1 + RalRS) (RS)
ac - 20 x A x (RS/RS)
where A

Since the gain of the equalization amplifier varies by
a factor of 3, the ac impedance will vary the same
amount. Using the resistor values indicated in Figure 1,
the ac impedance will vary from 2S0 !1 (short loop) to
S40 !1 (long loop).
When calculating or measuring the ac impedance, capacitor Cs (=S.O k!1 at 1.0 kHz) and the dynamic impedance of the MC34014 (=10 k!1) must be taken into account. If the microphone has an impedance lower than
that of a typical electret, then its dynamic impedance
must be accounted for in the above equation.

= the

gain of the equalization amplifier
(0.25 to 0.75)

FIGURE 17 -

DETERMINING AC IMPEDANCE

From
Tip & Ring V+
VR
VR

EQ

RS

R9

RS
10 k

IITXO

TXI

TXO

Mike

-=

MIC

If a variation in Zac of less than 3: 1 is desired, the
circuit configuration of Figure lS may be used. The ac
impedance is the parallel combination of Rx and the

FIGURE 18 10

~

impedance presented by the remainder of the circuit.
With the values shown in Figure lS, the ac impedance
varies from 400 !1 to SOO !1.

REDUCED AC IMPEDANCE VARIATION
Rx
1.S k

V+

From Tip & Ring
VR

VR

RS

R9
145 n

500

!ITXO
TXO

MIC

MOTOROLA COMMUNICATIONS DEVICE DATA

-=

MC34014

2-357

TRANSMIT DESIGN PROCEDURE
Referring to Figure 17, first select R9 for the desired
maximum output level at Tip & Ring, assuming a signal
level at TXO of 1.0 V p-p. The maximum signal level at
Tip & Ring will be approximately:
(VTXO) (Zl)
R9
where Zl is the characteristic ac impedance of the
phone line. Capacitor Cs and the =10 kG dynamic
impedance of the MC34014 must also be considered
in the above computation, since they are in parallel
with ZL.
The next step is to select the RS/RS ratio, according
to the required Zac, using the equation on the previous
page. Then RS is selected to set the microphone sensitivity. RS is typically in the range of 0.5 k to 1.5 kG,
and is dependent on the characteristics of the microphone. RS is then calculated from the above mentioned ratio.

FIGURE 19 -

ALTERNATE MICROPHONE BIAS

HANDSET/HANDS-FREE TELEPHONE
Figure 23 indicates a circuit using the MC34014
speech network, MC3401S speakerphone circuit, and the
MC34017 tone ringer to provide a complete telephone/
speakerphone. Switch HS (containing one normally
open and one normally closed contact) is the hook
switch actuated by the handset, shown in the on-hook
position. When the handset is off-hook (HSl open, HS2
closed), power is applied to the MC34014, and consequently the handset, and the CS pin of the MC3401S is
held high so as to disable it. Upon closing the two poles
of switch SS, and placing switch HS in the on-hook position, power is then applied to both the MC34014 and
the MC3401S, and CS is held low, enabling the speakerphone function. Anytime the handset is removed from
switch HS, the circuit reverts to the handset mode. The
diode circuitry sets the MC34014 to the pulse dialing
mode to mute the handset microphone and receiver
when using the speakerphone. To compensate for the
different equalization response of the MC34014 when in

FIGURE 20 -

INTERFACING A DYNAMIC MICROPHONE

VR

v+

1.0 k

R8
16 k
50 /L F

1:

R6
20 k

MC34014

Electret
Microphone

0.1

Dynamic

27 k

MC34014

160

Microphone
(1500)
MIC

The overall gain from the microphone to V + will vary
with loop current due to the influence of the equalization
amplifier on TXI. The signal at EO is out of phase with
that at TXI, therefore the signal at V + decreases as loop
current (and the EO signal) increases. Variations are typically 2.0 to 5.0 dB and depend largely on the impedance
characteristics of the microphone.
ALTERNATE MICROPHONE BIASING
In the event that the microphone cannot be properly
biased from the 1.2 volt VR supply, a higher voltage can
be obtained by biasing from the V + supply. The configuration shown in Figure 19, provides a higher voltage
to the microphone, and also filters the speech signals
at V + from reaching it, preventing an oscillatory loop
from forming. The maximum voltage limit of the
microphone must be considered when biasing this way.
If a dynamic microphone is to be used in place of an
electret unit, the circuit in Figure 20 will buffer its low
impedance from the MC34014 circuit, maintaining the
high impedance required at the junction of RS and RS'
The circuit shown provides a gain of =2.S for the microphone signals, and can be adjusted by varying the
lS0 G resistor.

MC34014

2-358

the pulse dialing mode (Figures 9 and 11), the 47 G resistor normally found at Pin 13 ofthe MC34014 is instead
divided into two resistors (33 G and 150). This arrangement provides similar equalization response in both the
handset and in the speakerphone modes. Since the LC
capacitor (Pin 12) is ineffective in the speakerphone
mode, a capacitor is added at Pin 5 (CC) to provide compensation for the equalization loop when the speakerphone mode is in effect.
SWITCHABlE TONE/PULSE TELEPHONE
Figure 21 indicates a switchable tone/pulse telephone
circuit using the MC145412 tone/pulse dialer, MC34014
speech network, and the MC34017 tone ringer. The dialer is programmable, and can store up to 10 phone
numbers. As can be seen, the interface to the MC34014
is straightforward.
PULSE ONLY TELEPHONE
Figure 22 indicates a pulse only telephone circuit using the MC145409 pulse dialer, MC34014 speech network, and the MC34017 tone ringer. The dialer has last
number redial, and provides a pacifier tone to the receiver during dialing.

MOTOROLA COMMUNICATIONS DEVICE DATA

FIGURE 21 -

COMPLETE TELEPHONE WITH PULSEfTONE DIALING

Tip

Ring

Pieza

~

C6 0.02
Rl k
240

I"F

VDD

1 2

OPL
DTMF

Rl
R2

Keypad

R3

•

0 #

MO

.

100 k

N

R4
C3
C2

~

OH

U
:::;

TSO

Cl

Receiver

100 k

Tone
OSCl
3.58 MHz

D

Mode
OSCOVSS

FIGURE 22 -

COMPLETE TELEPHONE WITH PULSE DIALING

Tip

Ring

Pieza

~

C6 0.02
Rl k
240

I"F

~~i:H
VDD
OPL

Rl

Keypad

R2

4

.

R3
0

#

R4
C3
C2
Cl

MO

+

en

.

OH

:::;

TSO

0

;g

U

Receiver

~~.b5"F
100 k

2M
390 pF

RCl

DRS

RC2

MBR

RC3
220 k

VSS

MOTOROLA COMMUNICATIONS DEVICE DATA

MC34014

2·359

NiS:

WO

01 Co)
0"..

o
....
"..
FIGURE 23 -

SWITCHABLE HANDSET/HANDSFREE SYSTEM

l

10 k
3.0 k

l

30 k 1

2N3906

~RTX
0.1
3
"
TXI

."------ bf.i
1.0+

l2;~~T

''----

tt'
Switch

s:

~

,,7 RLI [)
...
.068 8 RLO

~

r-t-+-trvv-:-'-t-+-...:0:::.,,11f-----".j9 MCI

"'_

Privacy

.

ACF 25
24

12.0 k 1

'/

~

pw;;..!

05

bi

25 n

Speaker

~,:+
4.7

'r

~1110 MCO
CP1
4.7k

,,~!

."
......_ _+--'."'06"'8'---'1~4

=T

VCC 20
lS0.05
SKI
Cs 18

~~

AGCt:1~

CP2
XOI
S
KG

,,4.7

XOCA43 200 k
V- 22'
VB 21
+

V+ 16
15

SKO~

'~~1
a

4'7

+
47
1N4148 =
51 k

/I

24 k

lQ..!:i.

=

15

1

r--I-rT-----~+~j-----------~

FA

510 .05

0.05

~'

0.05

/T~'?'

4 STA s: VOO 15 22 k
5 C
n
14
10
6 C
V+
EQ ;;:
LA
0.05

3.3 k
10"
10 k

151 k

MT 18
f-MS 17 H---

~

Piezo~d

~8~_ _~

MC34017

~

+

*2.2

4
Diodes: 1N4148 except where noted. (

5

15 k

1

Phone

Une

:::)

Recommended External Components

Piezo Sounder
Models KSN 1113-1116
Motorola, Inc.
Albuquerque, N.M.
505-822-8801

Microphone/Receiver
Microphone model EM-95
Receiver model DH-34
Primo Microphone, Inc.
Elk Grove Village, III.
312-595-1022

TRANSIENT PROTECTION & RFI SUPPRESSION
Protection from voltage transients is necessary in
most telephone circuits, and may take the form of zener
diodes, RC or LC filters, transient suppressors, or a combination of the above.
Potential radio frequency interference problems
should be addressed early in the electrical and mechanical design of the telephone. RFI may enter the cir-

MOTOROLA COMMUNICATIONS DEVICE DATA

Microphone Model KUC2123
Hosiden Electronics
Chicago, III.
312-956-7707

cuitry through the Tip & Ring lines, through the microphone and/or receiver leads in the handset cord, or
through any of the wiring or PC board traces. Ceramic
decoupling capacitors, ferrite beads, and other RFI
suppression techniques may be needed. Good PC board
design techniques, such as the avoidance of loops,
should be used. Long tracks on high impedance nodes
should be avoided.

MC34014
2-361

MOTOROLA

-

SEMICONDUCTOR
TECHNICAL DATA

MC34017

TELEPHONE TONE RINGER

TELEPHONE
TONE RINGER

• Complete Telephone Bell Replacement Circuit with Minimum
External Components
•

BIPOLAR LlNEAR/12L

• On-Chip Diode Bridge and Transient Protection
• Direct Drive for Piezoelectric Transducers
• Push Pull Output Stage for Greater Output Power Capability
• Base Frequency Options- MC34017-1: 1.0 kHz
MC34017-2: 2.0 kHz
MC34017-3: 500 Hz
• Input Impedance Signature Meets Bell and EIA Standards
• Rejects Rotary Dial Transients

PLASTIC PACKAGE
CASE 626

APPLICATION CIRCUIT

160 k
15 k

*

C

'--

8

Ring

Tip

--I(
1.0/LF

6.8 k

~~'

~.!

+

-

7

6

5

RG

RC

RS

~.!

+

5.0/LF
25 V

2.2 /LF
3.0 V

MC34017·X

AC 1

ROl

R02

1

2

3

RI
4

*

Piezo Sound
Element
MC34017-1: C = 1000 pF
MC34017-2: C = 500 pF
MC34017-3: C = 2000 pF

MC34017
2-362

MOTOROLA COMMUNICATIONS DEVICE DATA

APPLICATION CIRCUIT PERFORMANCE (Refer to Circuit on First Page.)
Characteristic
Output Tone Frequencies
MC34017-1
MC34017-2
MC34017-3
Warble Frequency

Typical Value

Units
Hz

808/1010

161612020
4041505
12.5
37

Output Voltage
(VI'" 60 Vrms ' 20 Hz)

Vp_p

Output Duty Cycle

50

%

Ringing Start Input Voltage (20 Hz)

36

Vrms

Ringing Stop Input Voltage (20 Hz)

21

Vrms

Maximum ac Input Voltage ('" 68 Hz)

150

Vrms

impedance When Ringing
Vi = 40 Vrms ' 15 Hz
VI = 130 Vrms ' 23 Hz

>16
12

Impedance When Not Ringing
VI = 10 Vrms ' 24 Hz
VI = 2.5 Vrms ' 24 Hz
VI = 10 Vrms ' 5.0 Hz
VI = 3.0 Vrms ' 200-3200 Hz

28
>1.0
55
>200

kn
Mn
kn
kn

1500

V

0.5
0.9

-

kn

Maximum Transient Input Voltage
(T'" 2.0 ms)
Ringer Equivalence: Class A
Class B

PIN DESCRIPTIONS
Description

Name
AC 1, AC2

The input terminals to the full-wave diode bridge. The ac ringing signal from the telephone line
energizes the ringer through this bridge.

RS

The input of the threshold comparator to which diode bridge current is mirrored and sensed
through an external resistor (R3). Nominal threshold is 1.2 volts. This pin internally clamps at 1.5
volts.

RI

The positive supply terminal for the oscillator, frequency divider and output buffer circuits.

R01, R02

The tone ringer output terminals through which the sound eiement is driven.

RG

The negative terminal of the diode bridge and the negative supply terminal of the tone
generating circuitry.

RC

The oscillator terminal for the external resistor and capacitor which control the tone ringer
frequencies (R2, C2).

MAXIMUM RATINGS (Voltages Referenced to RG , Pin 7)
Parameter
Operating AC Input Current (Pins 1, 8)

Value

Unit

20

mA, RMS

±300

mA, peak

Voltage Applied at RC (Pin 6)

5.0

V

Voltage Applied at RS (Pin 5)

5.0

V

Transient Input Current (Pins 1,8) (T<2.0 ms)

-2.0to VRI

V

1.0

W

Operating Temperature Range

-20 to +60

'C

Storage Temperature Range

-65 to +150

'C

Voltage Applied to Outputs '(Pins 2, 3)
Power Dissipation (@ 25'C)

MOTOROLA COMMUNICATIONS DEVICE DATA

MC34017
2-363

ELECTRICAL CHARACTERISTICS (TA = 25°C)
Characteristic

Test

Ringing Start Voltage
(VStart = VI @ Ring Start)
VI>O
VI:_-------'

J

I
I
I

oII:

MC34017
2-364

MOTOROLA COMMUNICATIONS DEVICE DATA

CIRCUIT DESCRIPTION
The MC34017 Tone Ringer derives its power supply
by rectifying the ac ringing signal. It uses this power to
activate a tone generator and drive a piezo-ceramic
transducer. The tone generation circuitry includes are,
laxation oscillator and frequency dividers which produce high and low frequency tones as well as the tone
warble frequency. The relaxation oscillator frequency fo
is set by resistor R2 and capacitor C2 connected to pin
RC. The oscillator will operate with fo from 1.0 kHz to
10kHz with the proper choice of external components
(See Figure 1).
The frequency of the tone ringer output signal at R01
and R02 alternates between fo/4 to fo/5. The warble
rate at which the frequency changes is fo/320 for the
MC34017-1, fo/640 for the MC34017-2, and fo/160 for
the MC34017-3. With a 4.0 kHz oscillator frequency, the
MC34017-1 produces 800 Hz and 1000 Hz tones with a
12.5 Hz warble rate. The MC34017-2 generates 1600 Hz
and 2000 Hz tones with a similar 12.5 Hz warble frequency from an 8.0 kHz oscillator frequency. The
MC34017-3 will produce 400 Hz and 500 Hz tones with
a 12.5 Hz warble rate from a 2.0 kHz oscillator frequency.
The tone ringer output circuit can source or sink 20 mA
with an output voltage swing of 37 volts peak-to-peak.
Volume control is readily implemented by' adding a
variable resistance in series with the piezo transducer.
Input signal detection circuitry activates the tone
ringer output when the ac line voltage exceeds programmed threshold level. Resistor R3 determines the
ringing signal amplitude at which an output signal at
R01 and R02 will be generated. The ac ringing signal
is rectified by the internal diode bridge. The rectified
input signal produces a voltage across R3 which is referenced to RG. The voltage across resistor R3 is filtered
by capacitor C3 at the input to the threshold circuit.
FIGURE 1 - OSCILLATOR PERIOD (1/fol versus
OSCILLATOR R2 C2 PRODUCT

,.,. ,.

800

j

600

When the voltage on capacitor C3 exceeds 1.2 volts, the
threshold comparator enables the tone ringer output.
Line transients produced by pulse dialing telephones
do not charge capacitor C3 sufficiently to activate the
tone ringer output.
Capacitors C1 and C4 and resistor R1 determine the
10 volt, 24 Hz signature test impedance. C4 also provides filtering for the output stage power supply to prevent droop in the square wave output signal. Six diodes
in series with the rectifying bridge provide the necessary non-linearity for the 2.5 volt, 24 Hz signature tests.
An internal shunt voltge regulator between the RI and
RG terminals provides dc voltage to power output stage,
oscillator, and frequency dividers. The dc voltage at RI
is limited to approximately 22 volts in regulation. To
protect the IC from telephone line transients, an SCR is
triggered when the regulator current exceeds 50 mAo
The SCR diverts current from the shunt regulator and
reduces the power dissipation within the IC.

EXTERNAL COMPONENTS
Rl

Line input resistor. Rl affects the tone
ringer input impedance. It also influences
ringing threshold voltage and limits current
from line transients.
(Range: 2.0 kO to 10 kOI.

Cl

Line input capacitor. Cl ac couples the tone
ringer to the telephone line and controls ringer
input impedance at low frequencies.
(Range: 0.4 p,F to 2.0 p,FI.

R2

Oscillator resistor.
(Range: 150 kO to 300 kOI.

C2

Oscillator capacitor.
(Range: 400 pF to 3000 pFI.

R3

Input current sense resistor. R3 controls the
ringing threshold voltage. Increasing R3
decreases the ring-start voltage.
(Range: 5.0 kO to 18 kOI.

C3

Ringing threshold filter capacitor. C3 filters the
ac voltage across R3 at the input of the ringing
threshold comparator. It also provides dialer
transient rejection.
(Range: 0.5 p,F to 5.0 p,FI .

C4

Ringer supply capacitor. C4 filters supply
voltage for the tone generating circuits.
It also provides an ac current path for the
10 Vrms ringer signature impedance.
(Range: 1.0 p,F to 10 p,FI.

/'

'So

. /I-'

400
200
./

/'

V

(.'

150 k,,; R2,,; 300 k
400 pF ,,; C2 ,,; 3000 pF

200

100

300

400

r-500

R2C2 (/LSI
(1110 = 1.45 R2C2

+

10/LSI

MOTOROLA COMMUNICATIONS DEVICE DATA

MC34017

2-365

FIGURE 2 - TEST ONE

6.8 k*
VI
2

AC l

AC2

ROl

RG

3900

Vo

DUT

RC

8
7

=

6

160 k*

1.-;t-_3-1 R02
0.047 JLF

4

RS~5~-'~~:~'~1~2:F

RI

MC34017-1: C = 1000 pF*
MC34017-2: C = 500 pF*
MC34017-3: C = 1000 pF*

L-_ _ _ _ _ _ _--1-.0~JL-F;

J

a. Increase VI from + 33 volts while monitoring
VO' VStart ( +) equals VI when Vo commences
switching.
b. Decrease VI from -33 volts while monitoring
VO' VStart(-) equals VI when Vo commences
switching.
c. Decrease VI from +40 volts while monitoring
VO' VStop equals VI when Vo ceases
switching.
d. Set VI to +50 volts. Close Sl. Measure

l
(Normally open)

0.1 JLF

10 k

5.6 k
VDD

R

frequencies fH' fl' and

tw·

200 k
16
15
14
IC2

13

0.01 JLF

12
11
10

=

9

IC1-MC14011B
IC2-MC1453BB
VDD = 12 V
*Indicates 1% tolerance
(5% otherwise)

MC34017
2-366

Ql-2N3904

L---------~--~)fW

MC34017-1: R = 110 kO*
MC34017-2: R = 55 kO*
MC34017-3: R = 110 kO*

MOTOROLA COMMUNICATIONS DEVICE DATA

FIGURE 3 -

TEST TWO

6.B k*
AC 1

+

I r

IR01
_2

50 V-=-

5.0 V

ll +

=

RG 7

R01

~

DUT
S2

_3

RC ~~~~~--.160k*
6

R02

IR02

C

10V
4 RI

til +

RS ~~~~~--.15k*
5

~

-=- VRC

J

With VRC = 4.0 volts, close S1' Switch S2 to Pin 2 and measure
current at Pin 2 (101). Repeatedly switch VRC between 4.0 volts
and 0 volts until Pin 2 current changes polarity. Measure the
opposite polarity current (102). Calculate:
IR0 1 = 11011 + Jl021
Switch S2 to Pin 3 and repeat.
Calculate:
IR02 = 11011 + 11021

MC34017-1 C = 1000 pF*
MC34017-2 C = 500 pF*
MC34017-3 C = 1000 pF*
*Indicates 1% tolerance (5% otherwise)

FIGURE 4 -

2 R01
390

S1

n

TEST THREE

RG 7
DUT

....-M,-" 160 k*

Measure voltage at Pin 1.

RC ~-6

C
4

=

RI

RS

5

=

*Indicates 1% tolerance (5% otherwise)

MC34017-1: C = 1000 pF*
MC34017-2: C = 500 pF*
MC34017-3: C = 1000 pF*

!

MOTOROLA COMMUNICATIONS DEVICE DATA

MC34017
2-367

FIGURE 5 -

V
2

AC 1

AC 2

ROl

RG

DUT
3
4

TEST FOUR

RC

8
7

=

6

160 k*
C

R02
RI

RS

5

15 k*

a. Set II to 30 rnA. Measure voltage at Pin 1
(Volt)·
b. Set II to 100 rnA. Measure voltage at Pin 1
(Von)'

MC34017-1 C = 1000 pF*
MC34017-2 C = 500 pF*
MC34017-3 C = 1000 pF*

(Each test < 30 ms)
*Indicates 1% tolerance (5% otherwise)

FIGURE 6 -

6.8 k*

+

-=-

I

2
50V

AC 1

AC 2

ROl

RG

DUT
3 R02
4

RI

MC34017-1: C = 1000 pF*
MC34017-2: C = 500 pF*
MC34017-3: C = 1000 pF*

TEST FIVE

8
7

=

6
RC !-=--....-'lM,.--i 160 k* Measure voltage at Pin 5 (Vclamp)'
C

RS r--.---'VVIr--'
5
15 k*

Vclamp

1..

*Indicates 1% tolerance (5% otherwise)

MC34017
2-368

MOTOROLA COMMUNICATIONS DEVICE DATA

FIGURE 7 - TEST SIX

6.B k*
AC l

+
2

RG 7

ROl

20 k

OUT

-=-

-+______~~2.0k

r-____

3 R02

RC t--1>---'V'I/Ir~
6
160 k*

4

5
C
R8 t--1>---'V'I/Ir~ 15 k*

RI

MC34017-1: C = 1000 pF*
MC34017-2: C = 500 pF*
MC34017-3: C = 1000 pF*
*Indicates 1% tolerance (5% otherwise)

MOTOROLA COMMUNICATIONS DEVICE DATA

81

+

-=- VRC
I-=-

With VRC = 4.0 volts, close 8 1. Measure dc voltage between
Pins 2 and 3 (Vol). Repeatedly switch VRC between 4.0 volts
and 0 volts until Pins 2 and 3 change state. Measure the new
voltage between Pins 2 and 3 (Vo2).
Calculate:
Va = IVoll + IVo21

MC34017
2-369

MOTOROLA

-

SEMICONDUCTOR
TECHNICAL DATA

MC34018
Specifications and Applications
Information
VOICE SWITCHED SPEAKERPHONE CIRCUIT

VOICE SWITCHED
SPEAKERPHONE CIRCUIT
SILICON MONOLITHIC
INTEGRATED CIRCUIT

The MC34018 Speakerphone integrated circuit incorporates the
necessary amplifiers, attenuators, and control functions to produce a high quality hands-free speakerphone system. Included
are a microphone amplifier, a power audio amplifier for the
speaker, transmit and receive attenuators, a monitoring system
for background sound level, and an attenuation control system
which responds to the relative transmit and receive levels as well
as the background level. Also included are all necessary regulated
voltages for both internal and external circuitry, allowing linepowered operation (no additional power supplies required). A
Chip Select pin allows the chip to be powered down when not in
use. A volume control function may be implemented with an
external potentiometer. MC34018 applications include speakerphones for household and business use, intercom systems, automotive telephones, and others.
• All necessary level detection and attenuation controls for a
hands-free telephone in a single integrated circuit

1'SUFFIX
PLASTIC PACKAGE
CASE 710

• Background noise level monitoring with long time constant
• Wide operating-dynamic range through signal compression
• On-chip supply and reference voltage regulation
• Typical 100 mW output power (into 25 Ohms) with peak limiting
to minimize distortion

DWSUFFIX
PLASTIC PACKAGE
CASE 751F
SO-28

• Chip Select pin for active/standby operation
• Linear Volume Control Function
• Standard 28-pin plastic DIP ,package (0.600 inch wide) and SOIC
package
'

BLOCK DIAGRAM

ELECTRET
MIC

,--------------------,I
TRANSMIT CHANNEL

SPEAKER

~

~I

R:CEIVE CHANNEL

I DC INPUT

SPEAKERPHONE IC SYSTEM

L--~~~---~--------~EN~~
RECEIVE VOLUME CONTROL

MC34018

2-370

TELEPHONEr
LINE

\7

INPUT

MOTOROLA COMMUNICATIONS DEVICE DATA

PIN DESCRIPTION
Pin Name Description
1 RR

A resistor to ground provides a reference current
for the transmit and receive attenuators.

2 RTX

A resistor to ground determines the nominal gain
of the transmit attenuator. The transmit channel
gain is inversely proportional to the RTX
resistance.

3 TXI

Input to the transmit attenuator. Input resistance
is nominally 5.0 k ohms.

4 TXO

Output of the transmit attenuator. The TXO output signal drives the input of the transmit level
detector, as well as the external circuit which
drives the telephone line.

5 TLI

Input of the transmit level detector. An external
resistor ac coupled to the TLI pin sets the detection level. Decreasing this resistor increases the
sensitivity to transmit channel signals.

6 TLO

Output of the transmit level detector. The external
resistor and capacitor set the time the comparator
will hold the system in the transmit mode after
speech ceases.

7 RLI

Input of the receive level detector. An external
resistor ac coupled to the RLI pin sets the detection level. Decreasing this resistor increases the
sensitivity to receive channel signals.

8 RLO

9 MCI

Output of the receive level detector. The external
resistor and capacitor set the time the comparator
will hold the system in the receive mode after the
receive signal ceases.
Microphone amplifier input. Input impedance is
nominally 10 k ohms and the dc bias voltage is
approximately equal to VB.

10 MCO Microphone amplifier output. The mic amp gain
is internally set at 34 dB (50 VN).
11

CPl

12 CP2

13 XDI

14 SKG

A parallel resistor and capacitor connected between this pin and VCC holds a voltage corresponding to the background noise level. The
transmit detector compares the CPl voltage with
the speech signal from CP2.
A capacitor at this pin peak detects the speech
signals for comparison with the background
noise level held at CPl.
Input to the transmit detector system. The microphone amplifier output is ac coupled to the XDI
pin through an external resistor.
High current ground pin for the speaker amp output stage. The SKG voltage should be within 10
mV of the ground voltage at Pin 22.

15 SKO, Speaker amplifier output. The SKO pin will source
and sink up to 100 rnA when ac coupled to the
speaker. The speaker amp gain is internally set
at 34 dB (50 VN).
16 V+

Input dc supply voltage. V + can be powered from
Tip and Ring if an ac decoupling inductor is used
to prevent loading ac line signals. The required
V + voltage is 6.0 to 11 V (7.5 V nominal) at 7.0
rnA.

MOTOROLA COMMUNICATIONS DEVICE DATA

Pin Name Description
17 AGC A capacitor from this pin to VB stabilizes the
speaker amp gain control loop, and additionally
controls the attack and decay time of this circuit.
The gain control loop limits the speaker amp input to prevent clipping at SKO. The internal resistance at the AGC pin is nominally 110 k ohms.
18 CS

Digital chip select input. When at a Logic "0"
«0.7 V) the VCC regulator is enabled. When at a
Logic "1" (> 1.6 V), the chip is in the standby
mode drawing 0.5 rnA. An open CS pin is a Logic
"0". Input impedance is nominally 140 k ohms.
The input voltage should not exceed 11 V.

19 SKI

Input to the speaker amplifier. Input impedance
is nominally 20 k ohms.

20 VCC

A 5.4 V regulated output which powers all circuits
except the speaker amplifier output stage. VCC
can be used to power external circuitry such as
a microprocessor (3.0 mA max). A filter capacitor
is required. The MC34018 can be powered by a
separate regulated supply by connecting V + and
VCC to a voltage between 4.5 V and 6.5 V while
maintaining CS at a Logic "1".

21

VB

An output voltage equal to approximately VCC/2
which serves as an analog ground for the speakerphone system. Up to 1.5 mA of external load
;:urrent may be sourced from VB. Output impedance is 250 ohms. A filter capacitor is required.

22

Gnd

Ground pin for the IC (except the speaker
amplifier).

23 XDC Transmit detector output. A resistor and capacitor
at this pin hold the system in the transmit mode
during pauses between words or phrases. When
the XDC pin voltage decays to ground, the attenuators switch from the transmit mode to the idle
mode. The internal resistor at XDC is nominally
2.6 k ohms (see Figure 1).
24 VLC

Volume control input. Connecting this pin to the
slider of a variable resistor provides receive mode
volume control. The VLC pin voltage should be
less than or equal to VB.

25 ACF

Attenuator control filter. A capacitor connected to
this pin reduces noise transients as the attenuator
control switches levels of attenuation.

26 RXO Output of the receive attenuator. Normally this
pin is ac coupled to the input of the speaker
amplifier.
27 RXI

Input of the receive attenuator. Input resistance
is nominally 5.0 k ohms.

28 RRX

A resistor to ground determines the nominal gain
of the receive attenuator. The receive channel
gain is directly proportional to the RRX
resistance.

Note: Pin numbers are identical for the DIP and sOle packages,

MC34018
2-371

ABSOLUTE MAXIMUM RATINGS
(Voltages referred to Pin 22) (TA

=

25'C)
Value

Units

V + Terminal Voltage (Pin 16)

+ 12, -1.0

V

CS (Pin 18)

+12, -1.0

V

Speaker Amp Ground (Pin 14)

+3.0, -1.0

V

VlC (Pin 24)

VCC, -1.0

V

-65to +150

'c

Parameter

Storage Temperature

"Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed.
They are not meant to imply that the devices should be operated at these limits.
The "Electrical Characteristics" tables provide conditions for actual device operation.

RECOMMENDED OPERATING CONDITIONS
Parameter
V + Terminal Voltage (Pin 16)

Value

Units

+6.0 to + 11

V

o to

CS (Pin 18)

+11

V

ICC (Pin 20)

o to 3.0

VlC (Pin 24)

0.55VB to VB

V

o to 250
o to 5.0

mV rms

Speaker Amp Ground (Pin 14)

-10 to +10

mVdc

Ambient Temperature

-20 to +60

'c

Receive Signal (Pin 27)
Microphone Signal (Pin 9)

mA

mV rms

ELECTRICAL CHARACTERISTICS (Refer to Figure 1)
Parameter

I Symbol

Pin

Min

Typ

Max

Units

-

-

9.0
800

mA
/-LA

4.9

5.4
65
6.0
80

5.9
150
20
300

Vdc
mV
ohms
mV

2.9
250

3.3

Vdc
ohms

2.0
40
-20

6.0
44
-16

10
48
-12

dB
dB
dB

1.8

2.3

3.2

Vdc

-

-

100

mV

SUPPLY VOLTAGES
V + Supply Current
V+ = 11 V, Pin 18
V+ = 11 V, Pin 18

=
=

IV+

16

0.7 V
1.6 V

VCC Voltage (V+ = 7.5 V)
Line Regulation (6.5 V < V + < 11 V)
Output Resistance (Icc = 3.0 mAl
Dropout Voltage (V + = 5.0 V)
VB Voltage (V+ = 7.5 V)
Output Resistance (lB = 1.7 mAl

VCC
ilVCC IN
ROVCC
VCCSAT

20

VB
ROVB

21

2.5

-

-

ATTENUATORS
Receive Attenuator Gain (@ 1.0 kHz)
Rx Mode, Pin 24 = VB; Pin 27 = 250 mV rms
Range (Rx to Tx Modes)
Idle Mode, Pin 27 = 250 mV rms

GRX
ilGRX
GRXI

RXO Voltage (Rx Mode)

VRXO

Delta RXO Voltage (Switch from RX to TX Mode)

ilVRXO

26,
27

RXO Sink Current (Rx Mode)

IRXOl

75

-

-

/-LA

RXO Source Current (Rx Mode)

IRXOH

1.0

-

3.0

mA

RXI Input Resistance

RRXI

3.5

5.0

8.0

kfi

Volume Control Range (Rx Attenuator Gain, Rx Mode,
0.6 VB < Pin 24 < VB)

VCR

24.5

-

32.5

dB

MC34018
2-372

MOTOROLA COMMUNICATIONS DEVICE DATA

ELECTRICAL CHARACTERISTICS (continued)
Parameter

Symbol

Pin

Min

Typ

Max

Units

4.0
40
-16.5

6.0

B.O

44
-13

4B
-B.5

dB
dB
dB

1.8

2.3

3.2

Vdc

-

-

100

mV

ATTENUATORS
Transmit Attenuator Gain (@ 1.0 kHz)
Tx Mode, Pin 3 = 250 mV rms
Range, (Tx to Rx Mode)
Idle Mode, Pin 3 = 250 mV rms

GTX
aGTX
GTXI

TXO Voltage (Tx Mode)

VTXO

3,
4

Delta TXO Voltage (Switch from Tx to Rx Mode)

aVTXO

TXO Sink Current (Tx Mode)

I'rXOL

75

-

-

p.A

ITXOH

1.0

-

3.0

mA

RTXI

3.5

5.0

B.O

kG

-

-

150
6.0
75

-

mV
mV
mV

33

34

35

dB

RSKI

15

22

37

kG

VSKO

2.4

3.0

3.6

Vdc

VSKOH

5.5

-

-

Vdc

VSKOL

-

-

600

mV

-

-

2.0

p.A

-

2.0

p.A

0.8

-

1.2

-

0
4.0

TXO Source Current (Tx Mode)
TXI Input Resistance
ACF Voltage (VCC - Pin 25 Voltage)
Rx Mode
Rx Mode
Idle Mode

aVACF

20,
25

SPEAKER AMPLIFIER

= 20 mVrms )

Speaker Amp Gain (Pin 19
SKI Input Resistance
SKO Voltage (Pin 19

= Cap Couple to GND)

SKO High Voltage (Pin 19
at Pin 15)

= 0.1

SKO Low Voltage (Pin 19
at Pin 15)

=

V, -100 mA load

-0.1 V, +100 mA load

GSPK

15,
19

MICROPHONE AMPLIFIER
Mike Amp Gain (Pin 9

=

10 mV rms, 1.0 kHz)

Mike Amp Input Resistance
LOGAMPS
RLO Leakage Current (Pin B = VB +' 1.0 V)

ILKRLO

TLO Leakage Current (Pin 6 = VB + 1.0 V)

ILKTLO

6

ITH

5,7
25

VXDC

23

ICP2

12

5.0

Rx Mode - RXI to SKO
(Pin 27 = 10 mV rms, 1.0 kHz)

RXD

27,
15

Tx Mode - MCI to TXO
(Pin,9 = 5.0 mV rms , 1.0 kHz)

TXD

4,9

Transmit-Receive Switching Threshold
(Ratio of ITLI to IRLI - at 20 p.A - to switch Tx-Rx
Comparator)

8

TRANSMIT DETECTOR
XDC Voltage -

Idle Mode
Tx Mode

CP2 Current Source

-

Vdc
Vdc

10

13

p.A

-

1.5

-

%

-

2.0

-

%

DISTORTION

NOTES: 1, V+ = 7,5 V. CS = 0.7 V except where noted.
2. RxMode: Pin7 = -100pA,Pin5 = +100pA,exceptwherenoted.
Tx Mode: Pin 5, 13 = -100 pA, Pin 7 = +100 pA, Pin 11 = a volts,
Idle Mode: Pin 5 = -100 pA, Pin 7, 13 = + 100 pA.
3. Current into a pin designated as +; current out of a pin designated as 4. Voltages referred to Pin 22. TA = + 25°C,

MOTOROLA COMMUNICATIONS DEVICE DATA

MC34018
2-373

TEMPERATURE CHARACTERISTICS (-20 to +SO·C)
Parameter

Typical
Change

Pin

V+Supply Current (V+ = 11 V, Pin 18 = 0.7 V)
V+ Supply Current (V+ = 11 V, Pin 18 = 1.6 V)
VCC Voltage (V + = 7.5 V)
Attenuator Gain (Max and Min Settings)
Delta RXO, TXO Voltages
Speaker Amp Gain
Microphone Amp Gain
Microphone Amp Input Resistance
Tx-Rx Switching Threshold (@ 20 !£A)

16
16
20

Units

-0.2
-0.4
+0.1
±0.003
±0.24
±0.003
±0.001
+0.4
±0.2

4,26
15,19
9,10
9
5,7

%rC
%rC
%rC

dBrC
%rc

dBrC
dBrC
%rC

nAl"C

DESIGN GUIDELINES (Refer to Figure 1)
ATTENUATORS
The transmit and receive attenuators are complementary in function, i.e., when one is at maximum gain
the other is at maximum attenuation, and vice versa.
They are never both on or both off. Their main purpose
is to control the transmit and receive paths to provide
the half-duplex operation required of a speakerphone.
The attenuators are controlled solely by the voltage at
the ACF pin (Pin 25). The ACF voltage is provided by
the Attenuatar Control block, which receives 3 inputs:
a) the Rx-Tx Comparator, b) the Transmit Detector Comparator, and c) the Volume Control. The response of the
attenuators is based on the difference ofthe ACF voltage
from VCC, and therefore a simple method for monitoring the circuit operation is to monitor this voltage difference (referred to as IlVacf). If IlVacf is approximately
6 millivolts the transmit attenuator is fully on and the
receive attenuator is fully off (transmit mode). If IlVacf
is approximately 150 millivolts the circuit is in the re. ceive mode. If IlVacf is approximately 75 millivolts, the
circuit is in the idle mode, and the two attenuators are
at gain settings approximately half way (in dB) between
their fully on and fully off positions.
The maximum gain and attenuation values are determined by the three resistors RR, RTX, and RRX (Refer
to Figures 2, 3 and 4). RR affects both attenuators according to its value RELATIVE to RTX and RRX, which
is why Figure 4 indicates the variations versus the ratio.
of the other resistors to RR. (GRX and GTX are the maximum gains, and ARX and ATX are the maximum attenuations). RTX affects the gain and attenuation of only
the transmit attenuator according tothe curves of Figure
2, while RRX affects only the receive attenuator according to Figure 3. As can be seen from the figures, the
gain difference (from on to off) is a reasonably constant
45 dB until the upper gain limit is approached. A value
of 30 k is recommended for RR as a starting point, and
then RTX and RRX selected to suit the particular design
goals.
The input impedance of the attenuators (at TXI and
RXI) is typically 5.0 kG, and the maximum input signal
which will not cause output distortion is 250 mV rms
(707 mVp-p). The 4300 ohm resistor and 0,01 JLF capacitor at RXO (in Figure 1) filters out high frequency
components in the receive path. This helps minimize
high frequency acoustic feedback problems which may

MC34018
2-374

occur if the filter were not present. The filter's insertion
loss is 1.5 dB at 1.0 kHz. The outputs of the attenuators
are inverted from their inputs.
Referring to the attenuator control block, the IlVacf
voltage at its output is determined by three inputs. The
relationship of the inputs and output is summarized in
the fOllowing truth table:

Tx-Rx
Comp
Transmit
Transmit

Receive

Receive

Transmit
Oet
Comp

Volume
Control

4.Vacf

Mode

Transmit
Idle
Transmit
Idle

No Effect
No Effect
Affects t.vacf
Affects AVacf

6.0 mV
75 mV
50-150 mV
50-150 mV

Transmit
Idle

Receive

Receive

As can be seen from the truth table, the Tx-Rx comparator dominates. The Transmit Detector Comparator
is effective only in the transmit mode, and the Volume
Control is effective only in the receive mode.
The Tx-Rx comparator is in the transmit position
when there is sufficient transmit signal present over and
above any receive signal. The Transmit Detector Comparator then determines whether the transmit signal is
a result of background noise (a relatively stable signal),
or speech which consists of bursts. If the signal is due
to background noise, the attenuators will be put into
the i,jle mode (IlVacf = 75 mY). If the signal consists
of speech, the attenuators will be switched to the transmit mode (IlVacf = 6.0 mV.) A further explanation of
this function will be found in the section on the Transmit
Detector Circuit.
The Tx-Rx comparator is in the receive position when
there is sufficient receive signal to overcome the background noise AND any speech signals. The IlVacf voltage will now be 150 mV IF the volume control is at the
maximum position, i.e. VlC (Pin 24) = VB. IF VlC is
less than VB, the gain of the receive attenuator, and the
attenuation of the transmit attenuator, will vary in a
complementary manner as shown in Figure 5. It can be
seen that at the minimum recommended operating
level (VlC = 0.55 VB) the gain of the transmit attenuator
is actually greater than that of the receive attenuator.
The effect of varying VlC is to vary IlVacf, with a resulting variation in the gains of the attenuators. Figure
6 shows the gain variations with IlVacf.

MOTOROLA COMMUNICATIONS DEVICE DATA

The capacitor at ACF (Pin 25) smooths the transition
between operating modes. This keeps down any
"clicks" in the speaker or transmit signal when the ACF
voltage switches.
The gain separation of the two attenuators can be
reduced from the typical 45 dB by adding a resistor
between Pins 20 (VCe) and 25 (ACF). The effect is a
reduction of the maximum tJ. Vacf voltage in the receive
mode, while not affecting tJ.Vacf in the transmit mode.
As an example, adding a 12 kG resistor will reduce tJ.Vacf
by approximately 15 mV (to 135 mY), decrease the gain
of the receive attenuator by approximately 5.0 dB, and
increase the gain of the transmit attenuator by a similar
amount. If the circuit requires the receive attenuator
gain to be +6.0 dB in the receive mode, RRX must be
adjusted (to = 27 k) to re-establish this value. This
change will also increase the receive attenuator gain in
the transmit mode by a similar amount. The resistor at
TLI may also require changing to reset the sensitivity
of the transmit level detector.
LOG AMPLIFIERS
(Transmit and Receive Level Detectors)
The log amps monitor the levels of the transmit and
receive signals, so as to tell the Tx-Rx comparator which
mode should be in effect. The input signals are applied
to the amplifiers (at TLI and RLI) through AC coupling
capacitors and current limiting resistors. The value of
these components determines the sensitivity of the respective amplifiers, and has an effect on the switching
times between transmit and receive modes. The feedback elements for the amplifiers are back-to-back diodes
which provide a logarithmic gain curve, thus allowing
operation over a wide range of signal levels. The outputs of the amplifiers are rectified, having a quick rise
time and a slow decay time. The rise time is determined
primarily by the external capacitor (at TLO or RLO) and
an internal 500 ohm resistor, and is on the order of a
fraction of a millisecond. The decay time is determined
by the external resistor and capacitor, and is oil the
order of a fraction of a second. The switching time is
not fixed, but depends on the relative values· of the
transmit and receive signals, as well as these external
components. Figure 7 indicates the dc transfer characteristics of the log amps, and Figure 8 indicates the
transfer characteristics with respect to an ac input signal. The dc level at TLI, RLI, TLO, and RLO is approximately VB.
The Tx-Rx comparator responds to the voltages at
TLO and RLO, which in turn are functions ofthe currents
sourced out of TLI and RLI, respectively. If an offset at
the comparator input is desired, e.g., to prevent noise
from switching the system, or to give preference to
either the transmit or receive channel, this may be
achieved by biasing the appropriate input (TLI or RLI).
A resistor to ground will cause a DC current to flow out
of that input, thus forcing the output of that amplifier
to be biased slightly higher than normal. This amplifier
then becomes the preferred one in the system operation. Resistor values from 500 k to 10 M ohms are recommended for this purpose.

MOTOROLA COMMUNICATIONS DEVICE DATA

SPEAKER AMPLIFIER
The speaker amplifier has a fixed gain of 34 dB (50
VN), and is noninverting. The input impedance is nominally 22 kG as long as the output signal is below that
required to activate the Peak Limiter. Figure 9 indicates
the typical output swing available at SKO (Pin 15). Since
the output current capability is 100 mA, the lower curve
is limited to a 5.0 volt swing. The output impedance
depends on the output signal level and is relatively low
as long as the signal level is not near the maximum
limits. At 3 volts POp the output impedance is <0.5 ohms,
and at 4.5 volts pop it is <3 ohms. The output is short
circuit protected at approximately 300 mAo
When the amplifier is overdriven, the peak limiter
causes a portion of the input signal to be shunted to
ground, in order to maintain a constant output level.
The effect is that of a gain reduction caused by a reduction of the input impedance (at SKI) to a value not
less than 2.0 kG.
The capacitor at Pin 17 (AGC) determines the response time of the peak limiter circuit. When a large
input signal is applied to SKI, the voltage at AGC (Pin
17) will drop quickly as a current source is applied to
the external capacitor. When the large input signal is
reduced, the current source is turned off, and an internal
110 kG resistor discharges the capacitor so the voltage
at AGC can return to its normal value (1.9 Vdc). The
capacitor additionally stabilizes the peak limiting feedback loop.
Ifthere is a need to mute the speaker amplifier without
disabling the rest of the circuit, this may be accomplished by connecting a resistor from the AGC pin to
ground. A 100 kG resistor will reduce the gain by 34 dB
(0 dB from SKI to SKO), and a 10 k resistor will reduce
the gain by almost 50 dB.
TRANSMIT DETECTOR CIRCUIT
The transmit detector circuit, also known as the background noise monitor, distinguishes speech (which consists of bursts) from the background noise (a relatively
constant signal). It does this by storing a voltage level,
representative of the average background noise, in the
capacitor at CP1 (Pin 11). The resistor and capacitor at
this pin have a time constant of approximately 5 seconds (in Figure 1). The voltage at Pin 11 is applied to
the inverting input of the Transmit Detector Comparator. In the absence of speech signals, the noninverting
input receives the same voltage level minus an offset
of 36 mY. In this condition, the output of the comparator
will be low, the output transistor turned off, and the
voltage at XDC (Pin 23) will be at ground. If the Tx-Rx
comparator is in the transmit position, the attenuators
will be in the idle mode (tJ.Vacf=75 mY). When speech
is presented to the microphone, the signal burst appearing at XDI reaches the noninverting input of the
transmit detector comparator before the voltage at the
inverting input can change, causing the output to switch
high, driving the voltage at XDC up to approximately 4
volts. This high level causes the attenuator control block
to switch the attenuators from the idle mode to the
transmit mode (assuming the Tx-Ri< comparator is in

MC34018

2-375

the transmit mode). As long as the speech continues to
arrive, and is maintained at a level above the background, the voltage at XDC will be maintained at a high
level, and the circuit will remain in the transmit mode.
The time constant of the components at XDC will determine how much time the circuit requires to return to
the idle mode after the cessation of microphone speech
signals, such as occurs during the normal pauses in
speech.
The series resistor and capacitor at XDI (Pin 13) determine the sensitivity of the transmit detector circuit.
Figure 10 indicates the change in DC voltage levels at
CP2 and CP1 in response to a steady state sine wave
applied at the input of the 0.068 JLF capacitor and 4700
ohm resistor (the voltage change at CP1 is 2.7 times
greater than the change at CP2). Increasing the resistor,
or lowering the capacitor, will reduce the response at
these pins. The first amplifier (between XDI and CP2) is
logarithmic in order that this circuit be able to handle
a wide range of signal levels (or in other words, it responds equally well to people who talk quietly and to
people who shout). Figure 7 indicates the dc transfer
characteristics of the log amp.
Figure 11 indicates the response at Pins 11, 12, and
23 to a varying signal at the microphone. The series of
events in Figure 11 is as follows:
1) CP2 (Pin 12) follows the peaks of the speech
signals, and decays at a rate determined by the 10
JLA current source and the capacitor at this pin.
2) CP1 (Pin 11) increases at a rate determined by
the RC at this pin after CP2 has made a positive transition. It will follow the decay pattern of CP2.
3) The noninverting input ofthe Transmit Detector
Comparator follows CP2, gained up by 2.7, and reduced by an offset of 36 mV. This voltage, compared
to CP1, determines the output of the comparator.
4) XDC (Pin 23) will rise quickly to 4 Vdc in response to a positive transition at CP2, but will decay
at a rate determined by the RC at this pin. When XDC
is above 3.25 Vdc, the circuit will be in the transmit
mode. As it decays towards ground, the attenuators
are taken to the idle mode.
MICROPHONE AMPLIFIER
The microphone amplifier is noninverting, has an internal gain of 34 dB (50 VN), and a nominal input impedance of 10 kll. The output impedance is typically <15
ohms. The maximum p-p voltage swing available at the
output is approximately 2.0 volts less than VCC, which
is substantially more than what is required in most applications. The input at MCI (Pin 9) should be ac coupled
to the microphone so as to not upset the bias voltage.
Generally, microphone sensitivity may be adjusted by
varying the 2 k microphone bias resistor, rather than by
attempting to vary the gain of the amplifier.
POWER SUPPLY
The voltage supplyfor the MC34018 at V + (Pin 16)
should be in the range of 6.0 to 11 volts, although the
circuit will operate down to 4.0 volts. The voltage can
be supplied either from Tip and Ring, or from a separate

MC34018

2-376

supply. The required supply current, with no signal to
the speaker, is shown in Figure 12. The upper curve
indicates the normal operating current when Chip Select (Pin 18) is at a Logic "0". Figure 13 indicates the
average dc current required when supplying various
power levels to a 25 ohm speaker. Figure 13 also indicates the minimum supply voltage required to provide
the indicated power levels. The peak in the power supply current at 5.0-5.4 volts occurs as the VCC circuit
comes into regulation.
It is imperative that the V + supply (Pin 16) be a good
ac ground for stability reasons. If this pin is not well
filtered (by a 1000 JLF capacitor AT THE IC), any variation
at V+ caused by the required speaker current flowing
through this pin can cause a low frequency oscillation.
The result is usually that the circuit will cut the speaker
signal on and off at the rate of a few hertz. Experiments
have shown that only a few inches of wire between the
supply and the IC can cause the problem if the filter
capacitor is not physically adjacent to the IC.lt is equally
imperative that both ground pins (Pins 14 and 22) have
a low loss connection to the power supply ground.

Vcc

VCC (Pin 20) is a regulated output voltage of 5.4 volts,
+ / - 0.5 V. Regulation will be maintained as long as V +
is (typically) 80 mV greater than the regulated value of
VCC. Up to 3 milliamps can be sourced from this supply
for external use. Th~ output impedance is <20 ohms.
The 47 JLF capacitor indicated for connection to Pin
20 is essential for stability reasons. It must be located
adjacent to the IC.
Ifthe circuit is deselected (see section on Chip Select),
the VCC voltage will go to 0 volts.
If the MC34018 is to be powered from a regulated
supply (not the Tip and Ring lines) of less than 6.5 volts,
the configuration of Figure 14 may be used so as to
ensure that VCC is regulated. The regulated voltage is
applied to both V + and VCC, with CS held at a Logic
"1" so as to turn off the internal regulator (the Chip
Select function is not available when the circuit is used
in this manner). Figure 15 indicates the supply current
used by this configuration, with no signal at the speaker.
When a signal is sentto the speaker, the curves of Figure
13 apply.
VB
VB is a regulated output voltage with a nominal value
of 2.9 volts, +/-0.4 volts. It is derived from VCC and
tracks it, holding a value of approximately 54% of VCC.
1.5 milliamps can be sourced from this supply at a typical output impedance of 250 ohms.
The 47 JLF capacitor indicated for connection to the
VB pin is required for stability reasons, and must be
adjacent to the IC.
If the circuit is deselected (see section on Chip Select).
the VB voltage will go to 0 volts.

MOTOROLA COMMUNICATIONS DEVICE DATA

CHIP SELECT
The Chip Select pin (Pin 18) allows the chip to be
powered down anytime its functions are not required.
A Logic "1" level in the range of 1.6 V to 11 V deselects
the chip, and the resulting supply current (at V +) is

shown in Figure 12. The input resistance at Pin 18 is
>75 kil. The VCC and VB regulated voltages go to 0.0
when the chip is deselected. Leaving Pin 18 open is
equivalent to a Logic "0" (chip enabled).

FIGURE 1 - TEST CIRCUIT

FIGURE 2 - TRANSMIT ATTENUATOR versus RTX

-r-

+1 0
0
-1 01'-.

-20
dB

FIGURE 3 - RECEIVE ATTENUATOR versus RRX

Max Gain

+10 I--

IlVael = 6.0 mV
r-..... ........

<- ................

I"'--

-10
-20

/ I"'--30
i'
rMax
Att~;"ation
-40
,IlVacf = 150 mV

-50

= 30k
-6Ol-RR
VLC = VB

./

.>

-

.;'

,,;

dB -30

k

-40

r-.......

r""-

lOOk
RTX (OHMSI

MOTOROLA COMMUNICATIONS DEVICE DATA

.;'

-50
-60 r-~R = 30k
VLC = VB
-70

-.70

10K

_ I Maxi Gai~ I
IlVacf = 150 mV

1M

lK

Max Attenuation
IlVael = 6.0 mV

I-Usable Rang;~
10k

lOOK

RRX(OHMSI

MC34018
2-377

FIGURE 4 - GAIN AND ATTENUATION
versus RESISTOR RATIOS

-

f- GTX vs. RTXlRR

+10

. /~

-20

. /K

RTX = 91K
I-- Rr = 3~K

-5

,/'
1,\

1""'-- ......

-60

AJxv~RXlRR

-70

aiac!

6O

0.5

0.1

ATX vs. RTXlRR
aVac! = 150 mV

r r II

5.0

"- V
/'-

"-

i/

-35
-40

10

GRls/

V

-30
VLC = VB

1.0
RATIO

"-N.

-2 5

~

_

1/

GTX

-20

~

.Y

-50

~ircUi.t i~

-1 oI--Receive
dB -15 f--- Mode

':X'

dB -30 I-- GRX vs. RRXlRR
aVac! = 150 mV
-40

-

.1. .~
+ 5 I-- RRX = 18K

r-..

aVac! = 6.0 mV

-10

FIGURE 5 - ATTENUATOR GAIN versus VLC

~

0.2

V

I-

Minimum ""Recommended
Lrvel I

0.6

0.4

"

1.0

0.8

VLCNB

FIGURE 7 - LOG AMP TRANSFER CHARACTERISTICS

FIGURE 6 - ATTENUATOR GAIN versus .".,..,-=--t---t--1--t----l
:>

./'
r--...

V

-30

"

./'

-20
-2 5

V

""-

140

OUTPUT
VOLTAGE -

°0~--~---~20---L----~4~0--~----~60~~----~80

160

LOG AMP TRANSFER CHARACTERISTICS

DC INPUT CURRENT (/LAI

FIGURE 9 - SPEAKER AMP OUTPUT versus SUPPLY VOLTAGE
10

~

8.0

V

§!

~ 6.0

./

~

./

~ 4.0

/

NoLoad 25, Load_

"/

/...' /'

2.0
°0~--~10~~~~3~0--~--~50~--~--~--~

/'"

"--1

//

~

MC34018
2-378

(RLO, TLO, CP21 -

>-.....- . f - - O - -

VB

150r--"'--~-~-..--..--""--""--...,

INPUT VOLTAGE (mVp·pl

-f----+----/-----I

4.0

5.0

6.0

7.0
8.0
V+ (VOLTSI

9.0

10

11

MOTOROLA COMMUNICATIONS DEVICE DATA

FIGURE 10 - RESPONSE AT CP2 AND CP1
600

--

w

~ 400

:2
u
~

V

300

~
u

/'

/

':;

a
>

-

!J. VCP1IPin 111

:> 500

.§.

20 o

~ 100

I

!J. VCP2 (Pin 121

I
I /'
/

oV
50

100

150

200

250

VMCO (mV-RMSI
FIGURE 11 - TRANSMIT DETECTOR OPERATION

Inp~t ~~lnal--1111111111111111111111111111111111111111111--1--IIIIIIIIIIIIIIIIIIIHIIIIIIIIIIIIIIIIIIIIIIII--I
;.-'t----------

'" Ie'" '"

Jr

1- "'" mVI

I
q----------,

Solid Line = CPl
(Pin 111
Dotted Line =
Noninverting
Input of Transmit
Detector Compo

I

I

XDC (Pin 231

dV

\

2.7 x !J. Vl

"

10ILA

" -C- H

r

W.~I

'J

r----, (----,

36 mV

I

,

I

I

\

I

I

fL----------j

I

\r
,

I

, I
I

t
NOTE: Above values are typical based
on components shown in figure 1.
FIGURE 13 - SUPPLY CURRENT

FIGURE 12 - SUPPLY CURRENT versus SUPPLY VOLTAGE

versus SUPPLY VOLTAGE versus SPEAKER POWER

B.O
7.0
6.0

/

/

35

~=o

1\

\.

100mW
BOmW

30

I

~

-----, ':?~

Privacy

~
~

>

8
s::
s::

c
z
C5
~

(5

z
o

rn

!;l!
C5

m

o
»~

rri>--1
0.05*

.-----.~
4-

f[

~
,..1

4 Jk

7 RLI

g

n
-

.068

.,,,

41 100 k

RLO ""

VB 20

47

Handset
Jack

J

.1'''

flf.',
l0L.
•:
.. ,
510

~4

20 k

~..

+..
!:II:.

• 00

"'"

.2N3906

w,.

V- 2
22 1
.;:1t"; ; ;

~ ".~
'" ~o ~
11~1.
~.
m ,,"
~ ~'IO"'"
,.
•
"~
15

7
,JWVJ

~n~ ~

.-

25

~~f..;;:C.",
1.0

2.2M.

s::

.01

1.0
TXO
ACF 24
,,'" • ru
~
1Htn
".1 I--:;r.
no < =i"f" ~.

C

Switch

20k

27 .05
RXI 26't""
2.2k
RXO
,,4.7

" 4

M

3.0 k

y 9 bJ

''',. • 1.0 H

3.3 k

24k

10"

i.!.MIC

m

"' ,,~.
" .I.....I---~,,'MutefTOTone
"'" ~,.~"'-'!."
rMT

~

18

TI

4 TXO
STA n
;: VDD ..
15
5 CC 0
V+ 13

~, ~ J
~ '-' ~ ,. '"

'"

T' "
"..

• 00

•

•

'""

+-

.,_-

...

10
"L
.05

2

"'"
II 2

:~
[-oJS;1l
J"M

~

10.!
_

,,"./

MjV'

~

TI,

~".,~_r:,.
~ ~
'tlo;HS2

u.

,

_

-=-~'. "
...
S~~
h
~
!~~15jf~~t:3~3~~::~~.0~5~:::::::::::::::i==~~~==~~~::~!=~~~
~
"~'-f ~'001
~>---7

CPl

CS 117"
18 1

.068, 14 SKG

+

51 k

.,~.

10 V' lN4737

r-

'0"7.

4.3 k

8 RXO

240 k

VR 11

lN4004

". ;,

6.8 k

II'

8

~>----;

MC34017 6
5

160 k
.15 k

~t2.2
on-

Phone
Line

~

1. Diodes are 1N4001 unless otherwise noted.
2. 4 Transistors are 2N3904.
3. Recommended Transformer: Microtran T5115.

FIGURE 20 - DIGITAL TRANSMITIIDLE/RECEIVE INDICATION
MC34018

RLO
8

TLO
6

56 k

56 k

>,--4>--_

r TxllDLE

--1 Rx

>'7......__'---~

rTx

=.J Idle

Comparators A & 8 = LM393 (Dual)

MOTOROLA COMMUNICATIONS DEVICE DATA

MC34018
2-383

MOTOROLA

-

SEMICONDUCTOR
TECHNICAL DATA

MC34114

Specifications and Applications
Information

TELEPHONE SPEECH
NETWORK WITH
DIALER INTERFACE

TELEPHONE SPEECH NETWORK
WITH DIALER INTERFACE
The MC34114 is a monolithic integrated telephone speech network designed to replace the bulky magnetic hybrid circuit of a
telephone set. The MC34114 incorporates the necessary functions
oftransmit amplification, receive amplification, and sidetone control, each with externally adjustable gain. Loop length equalization
varies the gains based on loop current. The microphone amplifier
has a balanced, differential input stage designed to reduce RFI
problems. A MUTE input mutes the microphone and receive
amplifiers during dialing. A regulated output voltage is provided
for biasing of the microphone, and a separate output voltage
powers an external dialer, microprocessor, or other circuitry. The
MC34114 is designed to operate at a minimum of 1.2 volts, making
party line operation possible.
A circuit using the MC34114 can be made to comply with Bell
Telephone, British Telecom (BT). and NTT (Nippon Telegraph &
Telephone) standards. It is available in a standard 18-pin DIP, and
a 20-pin SOIC (surface mount) package.

SILICON MONOLITHIC

~
I~~~~~~
I

P SUFFIX
PLASTIC PACKAGE
CASE 707

• Operation Down to 1.2 Volts

OW SUFFIX
PLASTIC PACKAGE
CASE 7510

• Externally Adjustable Transmit, Receive, and Sidetone Gains
• Differential Microphone Amplifier Input Minimizes RFI
Susceptibility
• Transmit, Receive, and Sidetone Equalization on Both Voice
and DTMF Signals

PIN CONNECTIONS
(Top View)
(DIP Package)

• Regulated 1.7 Volts Output for Biasing Microphone
• Regulated 3.3 Volts Output for Powering External Dialer or
MPU
• Microphone and Receive Amplifiers Muted During Dialing
• Differential Receive Amplifier Output Eliminates Coupling
Capacitor
• Operates with Receiver Impedances of 50 Ohms and Higher
• Complies with NTT, Bell Telephone and BT Standards
SIMPLIFIED BLOCK DIAGRAM

Tip

VCC
LR

MUTE

VB

MS

VR

ZB

Gnd

RXA

MCI

RXI

MC2

RXOI

MCO
Ring

VDD

RAGC

RX02

TXI

ORDERING INFORMATION
Package
IS-Pin Plastic DIP
20-Pin Surface Mount
MUTE

MC34114
2-384

Part No.
MC34114P
MC34114DW

MS

MOTOROLA COMMUNICATIONS DEVICE DATA

ABSOLUTE MAXIMUM RATINGS
Parameter
Vee Supply Voltage
Voltage at VDD (Externally Applied, Vee

= 0)

Voltage at MUTE, MS (Vee> 1.5 Volts)
Voltage at MUTE, MS (Vee

= 0)

Voltage at RAGe (0 < Vee < 12 Volts)

Value

Units

-1.0, +12

Vdc

-1.0, +6.0

Vdc

-1.0, VDD+0.5

Vdc

-1.0, +6.0

Vdc

-1.0, +6.0

Vdc

Current through Vee, LR

130

mA

Current into ZB (Pin 15)

3.0

mA

-65, +150

°e

Storage Temperature

" Maximum Ratings " are those values beyond which the safety of the device cannot be
guaranteed. They are not meant to imply that the devices can be operated at these limits. The
"Recommended Operating Conditions" provides conditions for actual device operation.

RECOMMENDED OPERATING LIMITS
Parameter

Min

Typ

+1.2
+3.3.

-

Loop Current (into Vee! (Speech, Pulse Mode)
(Tone Dialing Mode)

4.0
15

Receiver Impedance

50

Voltage at MUTE, MS (Vee> 1.5 Volts)

0

Vee Voltage (Speech, Pulse Mode)
(Tone Dialing Mode)

-

Rl (Resistor from Vee to VB)

100

Ambient Temperature

-20

-

Symbol

Min

Iccsp

4.0
S.O
10

Max

Units

+10.5
+10.5

Vdc

120
120

mA

VDD

n
Vdc

1800

n

+70

°e

Typ

Max

Units

5.0
11
12
13
14
16
18

5.5
12
14

-70

1.7
0.2
±20

1.85
0.5
+70

Vdc
Vdc
mVdc

3.1
-70

3.3
±30

3.7
+70

Vdc
mVdc
mA

0.8
2.2

1.0
2.5

-

-

0.02
180

0.5

All limits are not necessarily functional concurrently.

ELECTRICAL CHARACTERISTICS (TA = 25°C, See Figure 1)
Parameter
SUPPLY CURRENT
Supply Current into Vee (Pin 2 open, R12 = 25 k, VDD unloaded)
Speech Mode (Figure 2) Vee = 1.2 Volts
Vee = 3.5 Volts
Vee = 8.0 Volts
Vee = 10.5 Volts
Tone Mode (Figure 4)
Vee = 3.3 Volts
Vee = 8.0 Volts
Vee = 10 Volts

mA

Icct

-

VR

1.6

-

VOLTAGE REGULATORS
VR Voltage (lR = 65 /LA. Vee = 2.5 V, Figure 5)
Load Regulation (0 < IR < 300 /LA, Vee = 2.5 V)
Line Regulation (lR = 65 /LA. 2.5 < Vee < 10.5 V)
VDD Voltage (Vee'" 3.8 V, IDD = 0, Figure 6)
Line Regulation (lDD = 0,5.0 V < Vee < 10.5 V)
Maximum Output Current (Vee = 3.8 V, VDD '" 3.0 V)
Speech Mode
Pulse, Tone Mode
Input Leakage Current (Vee = 0, 3.3 Volts applied to VDD)
Mute open or at VDD
Mute = 0 Volts

MOTOROLA COMMUNICATIONS DEVICE DATA

VDD
IDDMAX

/LA

Ilkg

-

MC34114

2-385

ELECTRICAL CHARACTERISTICS -

continued (TA = 25'C, See Figure 1)

I

Parameter

Symbol

Min

Typ

Max

Units

dB

MICROPHONE AMPLIFIER
Gain (Mute

=

VOO)

GMIC

28

30

32

Input Common Mode Rejection Ratio (1.0 kHz)

CMRR

20

26

-

dB

Input Impedance (Each Input)

RINMIC

14

20

27

kO

= Hi)
= Hi)

VMCOOC

0.85
0.6

1.1
0.71
0.08

1.25
0.93

Vdc

> 2.7 V)

VMCOAC

(VCC > 3.4 V, Mute
(VCC = 1.2 V, Mute
(Mute = 0 V)

MCO DC Bias Voltage

MCO Max Voltage Swing

=
=

(THO
(THO

5%, VCC
5%, VCC

=

1.2 V)

MCO Output Impedance

Gain Reduction when Muted (Mute

=

=

5%)

0 Volts, f

=

1.0 kHz)

-

2.0
500

-

270

IMCO
GMUT

55

70

ZMCO

MCO Output Current Capability (THO

-

160

-

-

Vp-p
mVp-p

0
p.A
dB

RECEIVE AMPLIFIER
RXI Bias Current (Mute

=

IIBR

-

50

-

1.2 V)
3.0. V)

RXOC

580
585

630
650

695
720

mVdc

> 3.0 V)

RXVOS

-35

0

+35

mVdc

Hi)

RX01, RX02 Bias Voltage (VCC
(VCC

=
>

RX01-RX02 Offset Voltage (VCC

RX01-RX02 Max Voltage Swing (Figure 9)
(THO = 5%, Receiver = 00)
(THO = 5%, Receiver = 150 0)

VRXAC

Internal Feedback Resistor (for muting)

RFINT

-

IRX

2.6

TXI Input Impedance

RTXI

0.85

ZB Input Impedance

RZB

RXOl & RX02 Source Current

-

-

nA

Vp-p
mVp-p

1.0

-

3.2

3.5

mA

1.0

1.15

kO

2.2
800

kO

INTERNAL CURRENT AMPLIFIERS

RXA Output Impedance
AC Current Gain
TXI to VCC (VRAGC = 0 V)
TXI.to VCC (VRAGC = 1.3 V)
ZB to RXA (VRAGC = 0 V, RXA = AC Gnd)
ZB to RXA (VRAGC = 1.3 V, RXA = AC Gnd)
TXI to RXA (VRAGC = 0 V, RXA = AC Gnd)
TXI to RXA (VRAGC = 1.3 V, RXA = AC Gnd)

RRXA

-

GTX

-

GZB
GSTA

-

500
10
100
50
0.5
0.25
1.22
0.61

-

-

0
kO
AlA

-

DC INTERFACE
LR Level Shift (VCC-VLR)
(lLOOP = 20 rnA, Mute = VOO)
(lLOOP = 80 rnA, Mute = VOO)
(ILOOP = 20 mA, Mute & MS = 0 V)
(lLOOP = 80 rnA, Mute & MS = 0 V)
VCC Boost (lLOOP = 20 mA, Mute & MS
switched from Hi to Lo, Rl = 620 0)
RAGC Current (VRAGC
(VRAGC

MC34114
2-386

=
=

OV)
1.0 V)

Vdc

-

-

AVLRT

-

2.8
3.5
3.8
5.0

AVLRB

0.7

1.0

1.2

Vdc

IRAGC

-

-40
-12

-

p.A

AVLRS

-

-

-

MOTOROLA COMMUNICATIONS DEVICE DATA

ELECTRICAL CHARACTERISTICS -

continued (TA = 25"<:, See Figure 1)

Parameter

I

Symbol

Min

RMUT

-

Typ

Max

Units

LOGIC INPUTS
MUTE Input Impedance (VCC > 1.2 V)
(VCC = 0 V, 0 < Mute < 6.0 V)
Input Low Voltage
Input High Voltage
Holdover (Delay for Receive amplifier to return
to full gain after Pin 17 switches from 0 to VDD)

VILMT
VIHMT
TMUT

MS Input Impedance (VCC > 1.2 V)
(VCC = 0 V, Mute = open or VDD)
(VCC = 0, Mute = 0)
Input Low Voltage
Input High Voltage

I

RMS

0
VDD-0.5
8.0

-

-

VILMS
VIHMS

60
>60

-

kO
MO
Vdc
Vdc
mSec

-

1.0
VDD
25

60
>50
4.0

-

-

kO
MO
kO
Vdc
Vdc

Units

11

-

0
2.0

-

0.3
VDD

Min

Typ

Max

SYSTEM SPECIFICATIONS (f = 1.0 kHz unless noted, TA = 25'e, Refer to Figure 1)
Parameter

I

Symbol

LINE INTERFACE
Vcc DC Voltage (Pin 1)
Bell Telephone Standard and NTT Specs. (R2 = 430, R3 = 130)
Speech Mode
ILOOP = 10 rnA
ILOOP = 20 rnA
ILOOP = 30 rnA
ILOOP = 120 rnA
Tone Mode
ILOOP = 20 rnA
ILOOP = 30 rnA
British Telecom Standard
(R2 = 43 0 + 2.5 V Zener, R3 = 130)
Speech Mode
ILOOP = 10 rnA
ILOOP = 20 rnA
ILOOP = 30 rnA
ILOOP = 70 rnA

VCC

AC Terminating Impedance (lLOOP = 20 rnA. Figure 11)

ZAC

Vdc
1.7
3.0
3.5
8.5
3.9
4.5

2.0
3.4
4.1
9.9
4.1
5.1

2.3
3.7
4.5
10.5
4.3
5.5

-

-

4.3
5.9
6.9
10

-

500

600

700

-7.2
-13.5

-6.1
-11

-5.0
-9.5

-7.5

0

RECEIVE PATH
Gain (VCC to RX01-RX02, Figures 14, 15)
ILOOP = 20 rnA
ILOOP = 100 rnA

dB

GRX

60Gain (GRX @ 100 rnA versus 20 rnA)

60GRX

Muted Gain (Mute = Logic 0, ILOOP = 20 rnA)

GRXM

Distortion (at RX01-RX02, Vec = 250 mVrms)
f=300Hz
f= 1.0 kHz
f = 3.4 kHz

THOR

Output Noise Across RX01-RX02 (@ 1.0 kHz)

NRXO

-6.0

-4.5

dB

-

-22

-20

dB

-

0.3
0.2
0.02

-

2.0
-

4.0

-

36
29

38.5
32.5

40.5
35.5

-7.5

-6.0

-4.5

-

%

",Vrms

TRANSMIT PATH
Gain (MC1-MC2 to VCC, Figures 12, 13)
ILOOP = 20 rnA
ILOOP = 100 rnA
60Gain (GTX @ 100 rnA versus 20 rnA)
Max Vce Voltage Swing (THO = 5%, Figure 8)
ILOOP = 20 rnA
ILOOP = 100 rnA

dB

GTX

60GTX
VTXMAX

Gain Reduction when muted (MC1-MC2 to Vec, Mute = 0 V)

GTXM

Distortion (0 dBm @ Vcc)
f = 300 Hz
f = 1.0 kHz
f = 3.4 kHz

THDT

Output Noise at Vce (@ 1.0 kHz)

NTXO

-

3.0
2.3

-

-

-

68

-

-

0.5
1.5
1.3

3.0
-

17

-

-

dB
Vp-p

dB
%

",Vrms

SIDETONE
Sidetone Gain (Gain from VCC to RX01-RX02 with
signal applied to MC1/MC2, ILOOP = 20 rnA)

MOTOROLA COMMUNICATIONS DEVICE DATA

MC34114

2-387

PIN DESCRIPTIONS
Pin Number
(SOIC)

(DIP)

VCC

1

1

Power supply pin for the IC. Supply voltage is derived from loop current. Transmit amp output
operates on this pin.

LR

2

2

Resistors R2 + R3 at this pin set the DC characteristics of the circuit. The majority of the loop
current flows through these resistors. Other components may be used to produce required DC
characteristics for individual regulatory agencies.

VB

3

3

A resistor or appropriate network (Rl I connected from this pin to VCC sets the AC terminating
impedance (return loss spec).

VR

4

4

A 1.7 volt regulated output which can be used to bias the microphone. Additionally, this
voltage powers a portion of the internal circuitry. Can nominally supply 300-500 pA

GND

5

5

Ground pin for the entire IC. Normally this is not connected to, nor to be confused with earth
ground.

Symbol

Description

MCl

6

6

Inverting differential input to the microphone amplifier. Input impedance is typically 20 kil.

MC2

7

7

Non-inverting differential input to the microphone amplifier. Input impedance is typically 20 kil.

MCO

8

8

Microphone amplifier output. Amplifier's gain is fixed at 30 dB.

RAGC

10

9

Loop current sensing input. The voltage at this pin, determined by the loop current and R3,
operates the loop length equalization circuit.

TXI

11

10

Input to the transmit amplifier from the microphone amplifier, DTMF source, and other sources.
Input impedance ~ 1.0 kil.

RX02

12

11

Receive amplifier non-inverting differential output. Current capability to the receiver is typically
set at ± 3.0 mA peak.

RX01

14

12

Receive amplifier inverting differential output. Current capability to the receiver is typically
±3.0 mA peak. Gain is set by R8.

RXI

15

13

Summing input to the receive amplifier. This pin is an AC virtual ground.

RXA

16

14

Summed outputs of the receive current amplifier, sidetone amplifier, and an AGC point.
Normally connected to the receive amplifier input (RXII through a coupling capacitor.

ZB

17

15

Input to the receive current amplifier. A balance network (ZBI is connected between this pin
and VCC. The network affects the receive level and sidetone performance. Input impedance is
~500 il in series with a diode.

MS

18

16

Mode Select Input. A logic "1" sets the IC for pulse dialing. A logic "0" sets the IC for tone
(DTMFI dialing. Effective only if MUTE is at a logic "0". Input impedance is ~ 60 kil.

MUTE

19

17

Mute input. A logic "1" sets normal speech mode. A logic "0" mutes the microphone and
receive amplifiers and allows MS to be functional. Input impedance is ~60 kil referenced to
VDD. An internal fixed delay of 11 mSec minimizes clicks in the receiver when returning to the
speech mode.

VDD

20

18

A regulated 3.3 volt output for an external dialer. Output source current capability is 1.0 mA in
speech mode, 2.5 mA in tone dialing mode.

MC34114
2-388

MOTOROLA COMMUNICATIONS DEVICE DATA

FIGURE 1 -

BLOCK DIAGRAM AND TEST CIRCUIT

10

MCO

C6

From

10 k 0.1

Dialer

R7

,--J\I\oIl.-1!-< DTMF
Note: Pin numbers shown are for the DIP package.
A 1-A4 are current amplifiers.

FIGURE 2 -

R12 = 24 k

FIGURE 3 -

-

0
/, ~ ~
1&V Rl
W

-

-

R121 20 k

~

r-r

~

o
o

R12 25 k

ICC versus VCC (SPEECH MODEl

16

12

VR~"""""----'

4

16

-

= 30 k

6

Vee IVOLTS!

MOTOROLA COMMUNICATIONS DEVICE DATA

10

ICC versus VCC (PULSE DIALING MODEl

20

12

~ 'R12=36k

Speech Mode _
Pin,2 = 'Ten
1.2

(PulsefTone
Select!

o
o

I--20 k
f-R12
R12 24 k I-- I-R12=30k
I-rR12 = 36 k

t:::::

---

r-

-

Pulse Dialing' Mode
Pin 2 = Open
10

4
Vee IVOLTS!

MC34114
2-389

FIGURE 4 -

16

r-r--

FIGURE 5 -

ICC versus VCC (TONE DIALING MODE)

20

--

I--!----

R12=20k 1-"....
~ I-"
R12::24k
I
~
R12 = 30 k
R12 = 36 k

L.-::

I---

-

VR versus IR versus VCC

1.8

I---

~I - -

-

I-"

......

r-.. r-......

1.6

1'-... .....

4~ "'\ "-

r'\:

~

6V

VCC = 2 V

10 V

"

~

1.2
Tone Dialing Mode
Pin 21 = Op~n

o
o

4

1.0

10

6

o

200

100

FIGURE 6 -

400

300

500

IR I!-
C>

Speech Mod,;"\

>

2.5

z

«

'\.

'"
u 0.7

~

Pulse or Tone
Dialing Modes

""" -

............

0.6

r-.....

2

VCC > 4 Volts

o

0.4

0.5

2.5

1.5
100 (rnA)

FIGURE 8 -

-

............

0.5

o

0.2

U

M
M
VRAGC (DC VOLTS)

FIGURE 9 -

MAXIMUM TRANSMIT SIGNAL AT VCC

1]

1.2

1.4

MAXIMUM RECEIVER SIGNAL

5
R12 = 20 k

r

J,

fJ

fI

V

--

117
7" ............
R12

~ .......... }12 ~~
..........

......... "-

b<::

30 k

MC34114

2·390

t---

R12 =36k

I
If
1.2

"""
'"
""" """
--........: t--...

Receiver
>1 kO

2

24 k

= 20k!
V;::,rR12
R12 = 24 k Receiver

5

/

1

rR12=30k =1500
1'/,r,R12 = 36k

II

5

THO = 5%
See Figure 1

4
6
VCC (DC VOLTS)

10

See Figure 1
THO = 5%
1.2

10

2
VCC (DC VOLTS)

MOTOROLA COMMUNICATIONS DEVICE DATA

SYSTEM PERFORMANCE
FIGURE 10 -

FIGURE 11 -

TIP/RING VOLTAGE versus LOOP CURRENT

14

800

Dialing Mod';,..

I-

~V

........
...-

......

./

V . /V

v

-

........ i-"""
!-"""

t::: ........ ~echMode

unoo

V

-

Q
~600

~

~500

\.

'"z~400
~

/

r-

'/

\I

z

~

Dialing Modes

300

"-

See Figure 1
f = 1 kHz

See Figure 1
200

o

40
60
80
LOOP CURRENT ImA)

20

FIGURE 12 -

100

120

o

TRANSMIT GAIN versus LOOP CURRENT

40
60
80
LOOP CURRENT ImA)

20

FIGURE 13 -

40

100

120

TRANSMIT GAIN versus FREQUENCY

40

" "-

/

38

1/

'\

"-

I

~

!:::

::;;
34
U)

f

= 1 kHz

I-- - ZUNE = 600n
32 I-- _ MC1-MC2 to VCC
See Figure 1

20

II

~

""'"

40
60
80
LOOP CURRENT ImA)

FIGURE 14 -

/

~36
z
I-

~34

.~

...........

I-

See Figure 1
ZUNE = 600n
32 - MC1-MC2 to VCC
- ILOOP = 30 rnA
30

o

~

38

I

a;:E 36
z

30

s~eech ~ode

::;;

:I:

a:

o

~

AC TERMINATING IMPEDANCE versus
LOOP CURRENT

100

T

120

I

I
1k

300

4k

FREQUENCY 1Hz,

RECEIVE GAIN versus LOOP CURRENT

FIGURE 15.,-- RECEIVE GAIN versus FREQUENCY

-3

2

-6
Speech Mode

-9

...........

-4

...........

m

:E-12
z


~

[E 580
Oil

'"z~

a:

;;; 540

-8

:::;;
a:
~

-9
-20

MC34114

20
40
TA. AMBIENT TEMPERATURE (OCI

60

70

-

~ -S;;;Mode

<[

ILOOP = 20 rnA_
See Figure 1

w

2·392

60

20
40
TA. AMBIENT TEMPERATURE (OCI

70

FIGURE 21 - AC TERMINATING IMPEDANCE
versus TEMPERATURE

RECEIVE GAIN versus TEMPERATURE

-5

-6

,-'

36

TA. AMBIENT TEMPERATURE (OCI

FIGURE 20 -

I--""

37

35
-20

70

/

-

500
-20

--

~ ~ D;~ling Mode

--

-

~

-

ILOOP = 20 rnA_
See Figure 1
I
I
20
40
TA. AMBIENT TEMPERATURE (OCI

60

70

MOTOROLA COMMUNICATIONS DEVICE DATA

FUNCTIONAL DESCRIPTION
INTRODUCTION
The MC34114 is a speech network which provides the
hybrid function and the DC loop current interface of a
telephone, and is meant to connect to Tip and Ring
through a polarity guard bridge. The transmit, receive,
and sidetone gains are externally adjustable, and additionally, line length compensation varies the gains with
variations in loop current. The microphone amplifier
employs a differential input to minimize RFI
susceptibility.
The loop current interface portion determines the dc
voltage versus current characteristics, and provides the
required regulated voltages for internal and external
use.
The dialer interface provides three modes of operation: speech (non-dialing), pulse dialing and tone
(DTMF) dialing. When switching among the modes,
some parameters are changed in order to optimize the
circuit operation for that mode. The following table
summarizes those changes:

TABLE 1 - OPERATING PARAMETERS versus
OPERATING MODE
Function
Speech
Pulse
Tone
LR Level Shift
(VCC - VLR)

2.8 V

2.8 V

3.8 V

VDD Current
Capability

1.0mA

2.5 mA

2.5 mA

Microphone
Amplifier

Functional

Muted

Muted

Receive Amp.
Internal Feedback
Resistor

Switched
Out

Switched
In

Switched
In

DC LINE INTERFACE AND LINE LENGTH
COMPENSATION
The DC line interface circuit (Pins 1, 2, 3) sets the DC
voltage characteristics with respect to loop current. See
Figure 22.

FIGURE 22 - DC LINE INTERFACE EQUIVALENT

Tip 0------,
VCC
Ring 0-----'
22/,F

R1
600

MC34114

VB

1

C1
ICC

Excess
Loop ~R::2:--..:::..;+.::2--------------I
LR
Current
43

RAGC 9

R3
13

The DC voltage at VCC is determined by the level shift
from VCC to LR, plus the voltage across R2 and R3. ICC
is the internal bias current required by the MC34114,
nominally in the range of 10 rnA. ICC can be reduced,
if necessary, by increasing R12, consistent with the
transmit and receive signal requirements (see the
Transmit Path section). See Figures 2-4, 8 and 9.
In the speech and pulse dialing modes current source
11 is off, and the level shift is due to 01's base-emitter
drop (=1.4 V), 1.0 volt across the 20 k resistor, and the
voltage across Rl, which varies with VCC from 0.15 volts
to =1.0 volt. When the loop current coming in from Tip
and Ring exceeds the ICC requirement, the excess current flows through 01, R2 and R3, to set the slope of
the V-I characteristic for the circuit (01 has an equivalent
resistance of =100). See Figure 10.

MOTOROLA COMMUNICATIONS DEVICE DATA

AGC Control

+

ToAGC
Points

In the tone dialing mode, current source 11 is on, drawing an additional 1.7 rnA through Rl, increasing the level
shift by =1.0 volts (for Rl = 6000). This feature ensures
that, at low loop currents, sufficient voltage is present
at VCC for the DTMF signals, and that the VDD regulator
supplies sufficient voltage to an external dialer. The ICC
current increases by =1.3 rnA in this mode.
Rl must be kept in the range of 100 to 1800 O. If it is
too large, insufficient current will flow into VB to bias
up the circuit. If it is too small, insufficient filtering at
VB will result unless Cl is increased accordingly. Speech
signals must be well filtered from VB.
The voltage across R3 determines the operation of
the AGC circuit (line length compensation). As the voltage at RAGe increases from =0.4 volts to =1.2 volts,
the AGC Control varies the current gain of the two AGC

MC34114
2-393

points (Figure 1) from 1.0 to 0.5, thereby reducing the
gain of the transmit and receive paths by 6.0 dB. See
Figure 7. Pin 9 is a high impedance input.
The values of R2 and R3 can be varied as required to
comply with various regulatory agencies, to compensate for additional circuitry powered by the loop current
(microprocessor, etc.), or to change the starting point
of the AGC function. If the AGC is not used, Pin 9 should
be connected to ground for high gains, or to VR for low
gains.

. MC2, and out of phase with MC1. The inputs (see Figure
23) have a nominal impedance of 20 kG, and are
matched to provide a high common mode rejection
(typically 26 dB).
FIGURE 23 -

To Next
Stage

VOLTAGE REGUL~TORS
The MC34114 has two internal voltage regulators
which are used to power external as well as internal
circuitry.
The VR regulator provides 1.7 volts at a maximum
current of 500 /LA (see Figure 5). This output is normally
used to set the DC bias into TXI (Pin 10), and to bias
the electret microphone. VR will typically be =300 mV
less than VCC when VCC is below 2.0 volts.
The VDD regulator provides 3.3 volts at a maximum
of 1.0 mA in the speech mode, and 2.5 mA in the pulse
or tone dialing modes (see Figure 6). It is normally used
to power an external dialer, and other associated circuitry. VDD is normally =0.5 volts less than VCC until
VDD regulates. It is a shunt type regulator which automatically switches to a high impedance mode when
VCC falls below 1.4 volts. This feature prevents excessive battery drain in the event a memory sustaining
battery is used with the external dialer. Leakage current
(with VCC = 0) is typically 0.02 p.A with an applied
voltage of up to 6.0 volts at VDD, with pin 17 open or
at VDD. If Pin 17 is at ground, a current of several
hundred microamps will flow into VDD and out of pin
17 (see paragraph on Logic Interface).
MICROPHONE AMPLIFIER
The microphone amplifier (Pins 6, 7, 8) has a differential input, single ended output, and a fixed internal
gain of +30 dB (31.1 VN). The output is in phase with

FIGURE 24 -

~~M~O

INPUT STAGE

Me1 o--.-'Yw-i

MC2

To preserve a high CMRR against unwanted signals
induced in the microphone leads, the microphone
should be biased with two equal value resistors as
shown in Figure 1.
The output (MCO) has a DC bias voltage of =1.1 volts
(VCC > 3.0 volts), and can nominally swing =2.0 volts
p-p (500 mV p-p at VCC = 1.2 volts). The output impedance is =270 G, and has a peak current capability of
=160 p.A for 5% THD.
When the MC34114 is switched to either dialing
mode, the microphone amplifier is muted by =70 dB
(300 Hz-4 kHz), effectively disabling the microphone.
The DC voltage at MCO is =80 mV when muted.
TRANSMIT PATH
The AC transmit path consists of the components
shown in Figure 24 (taken from Figure 1).

TRANSMIT PATH

If-----'IiV',_ _ _-o--.--i

~~5

ZLiNE

VR-'VI/I.~

The voltage output at MCO is converted to a current
into TXI by C5, R6, and TXI's 1.0 k input impedance
(with a slight error due to R12). A1 and A2 are current
amplifiers with a combined gain of 100. The AGC point
has a current gain of 1.0 at low looll currents, and

MC34114
2·394

decreases to 0.5 as loop current increases. Therefore
the current gain from TXI to VCC varies from 100 to 50
as loop current is increased. The resulting current output ilt VCC acts on R1 and the line impedance (nominally
600 G each, C1 is an AC short) to generate a voltage

MOTOROLA COMMUNICATIONS DEVICE DATA

FIGURE 25 - RECEIVE PATH

VB
TIp

R8

I _
Rl0
L
_ _ _R9
_ _ JI

Ring
Cl

1

}Cl0
-::-

signal at VCC, and consequently, at Tip and Ring. The
voltage gain from MC1-MC2 to Tip and Ring is therefore
(first order):
GTX - Am x 100 x AGC x R111ZUNE
(R6 + 1.0 k)

(Equation 1)

RX02) is internally configured for inverting unity gain.
The voltage gain from Tip and Ring to RX01-RX02
(differential) is (first order):
R8 x AGC
GRX = (ZB + 500)

(Equation 2)

where Am is the gain of the microphone amplifier (31.1
VN). At low loop currents GTX =84 VN (38.5 dB), and
decreases to =42 VN (32.5 dB) at higher loop currents,
for the component values shown in Figure 1 (@ 1.0 kHz).
For more precise calculations, consideration should
be given to the effects of C5 (in series with R6), R12 and
R7 (each in parallel with TXl's 1.0 k impedance), and
C10 and the ZB network (each in parallel with R1 and
ZUNE). The cumulative effects of these additional components is =1.5 dB.
The voltage signal at VCC is out of phase with that at
TXI, and in phase with that at MC1.
The maximum available voltage swing at VCC is a
function of the impedance at VCC (R1IIZUNE), the DC
bias current at A2's output, and the VCC DC voltage.
A2's bias current is determined by the bias current
through R12 (VR/{R12 + 1.0 k}) which is gained up by
A1, A2 and the AGC point. Figure 8 indicates the maximum voltage swing at VCC (with 5% THO).

where ZB = R10 + R911C9 (=R10 + R9).
For more precise calculations, the effects of C9 and
C8 must be considered. C9 provides a phase shift to aid
sidetone cancellation (see paragraph on Sidetone), and
C8 can be selected to provide low frequency roll-off.
High frequency roll-off can be obtained by adding a
feedback capacitor across R8. For the component values
shown in Figure 1, the receive gain measured =0.495
VN (- 6.1 dB) at low loop currents, and reduces to =0.25
VN ( -12 dB) at higher loop currents (@ 1.0 kHz).
When the MC34114 is switched to either dialing mode
(Mute = low), the receive gain is muted by the switching
in of the internal feedback resistor (RFINT from RX01
to RXI) - typically 1.0 kn. The effective feedback resistor for the amplifier is now the parallel combination of
R8 and RFINT. The amount of muting (in dB) can be
calculated from:

RECEIVE PATH
The AC receive path consists of the components
shown in Figure 25 (taken from Figure 1).
R1, typically 600 n, provides the AC termination
(return loss) for the receive signals coming in on Tip
and Ring (C1 is an AC short). The receive signal creates
an AC current through the ZB network and the 500 n
resistor at the ZB pin. A4 reduces that current by 1/2,
and then feeds it through the AGC point which has a
gain of 1.0 at low loop currents. The AGC gain is reduced
to 0.5 as loop current increases. The AC current out of
the AGC point feeds through C8 to RXI, the receive
amp's summing node (If C8 is large, RXA can be considered a virtual ground, and no AC current flows
through the internal 10k resistor). The voltage swing
at RX01 is then determined by the current through C8
and the R8 feedback resistor. The second op amp (at

The internal resistor is switched in coincident with Mute
(Pin 17) switching low. However, when Mute is switched
high, a delay (nominally 11 mSec) occurs before the
internal resistor is switched out. This feature prevents
dialing transients (particularly during pulse dialing)
from being heard as loud clicks in the receiver.

MOTOROLA COMMUNICATIONS DEVICE DATA

GRXM = 20 x log (R8 + RFINT)
RFINT

(Equation 3)

The DC bias voltages at RXI, RX01 and RX02 is =0.65
volts. The bias current at RXI is =50 nA into the pin.
The maximum voltage swing at RX01 and RX02 is a
function of the receiver impedance (typically
100-1500), and the value ofthe two Irx current sources
in Figure 25. Irx' set by R12 (between VR and TXI), is
equal to:
VR x 50x AGC
(Equation 4)
Irx = (R12 + 1.0 k)
Figure 9 indicates the maximum voltage swing available
to the receiver.

MC34114

2-395

SIDETONE CANCELLATION
Sidetone cancellation is provided by current amplifier
A3 (see Figure 1) which generates a current representative of the transmit signal to cancel the reflected sidetone signal coming in through ZB and A4. To achieve
perfect cancellation (no AC current out of RXA), it is
necessary that:
ZB = (40 x Rl/1ZUNE) - 500!1

(Equation 5)

where ZB is the network composed of RS, Rl0, and CS,
and ZUNE is the AC impedance of the line. The reactive
components of the line's impedance can be compensated for by making the ZB network comparably reactive. In Figure 1, CS provides a phase shift to compensate for the phase shift created by the phone line.
LOGIC INTERFACE (Mute and MS)
The two logic inputs (Mute and MS) are used to switch
the MC34114 between the speech and dialing modes
according to the following table:
TABLE 2 -

Mute

MS

High
Low
Low

X

High
Low

LOGIC INPUTS

Mode

Speech
Pulse Dialing
Tone Dialing

Table 2, together with Table 1, describes the condition
of the MC34114 in the various modes. Figure 26 shows
the input configuration for the Mute and MS pins.
FIGURE 26 -

LOGIC INPUTS

To Internal
Circuit
To Level
Shift Ckt.

The Mute input has a nominal input impedance of 60
k!1, referenced to VDD' This pin may be left open for a
logic "1," or connected to VDD. A logic "1" is defined
as between VDD-0.5 volts and VDD. A logic "0" is
defined as between ground and 1.0 volt. The switching
threshold is =2.3 volts. When Mute is switched low
(speech to dialing), the changes listed in Table 1 will
occur within 10 /Ls. Upon switching high (back to speech
mode), however, the receive amplifier feedback resistor
will be switched out after a delay of (typically) 11 ms.
This feature prevents dialing transients (particularly
during pulse dialing) from being heard as loud clicks in

MC34114
2-396

the receiver. The other functions listed in Table 1 transfer within 10 /LS.
The MS pin is functional only when Mute is low and
its only function is to provide an additional voltage level
shift between VCC and LR in the tone dialing mode (see
the section on DC Interface). The input impedance is
=60 k!1 when VCC > 1.5 volts. A logic "0" iS'between
ground and 0.3 volts, and a logic "1" is between 2.0
volts and VDD' The switching threshold is typically 0.75
volts. If unused, this pin must be connected to ground
or VDD, and not left open.
When VCC = 0 (on-hook condition), and a voltage in
the range of 0 to 6.0 volts is applied to Mute, a leakage
current of (typically) 0.02 /LA will flow if Mute and VDD
are at the same voltage. If Mute is at a voltage different
from VDD, current will flow through the internal resistors andlor diode. If a memory sustaining battery is used
in conjunction with an external dialer, and is configured
so that its voltage appears at VDD, Mute must be
allowed to float or be connected to VOO - otherwise
current (in the range of 100-200 ILA) will flow from the
battery through VDD and out of the Mute pin.
When VCC = 0, and a voltage in the range of 0 to 6.0
volts is applied to MS, a leakage current of (typically)
0.01 /LA will result as long as Mute is open or at VDD.
If Mute is at ground, an equivalent 3.5 k!1 parasitic resistance exists between MS and Mute.
When VCC < 1.5 volts, the Mute function is nonexistent and the MC34114 will be in the speech mode.

APPLICATIONS INFORMATION
DESIGN SEQUENCE
The design sequence for incorporating the MC34114
into most applications will be as follows (refer to Figure
1):
1) Decide on the AC terminating impedance (return
loss), and select Rl to be that value (typically 600 .0). If
there are other devices powered by the' loop current
which will be in parallel with Rl (such as a pulse dialing
circuit) which lower the effective terminating impedance, Rl cari be increased accordingly.
2) Select the maximum value of R12 which will provide the minimum required transmit and receive signals
according to Figures 8 and S.
3) Select the sum {R2 + R3} to provide the desired
Tip and Ring DC voltage versus loop current characteristics. Then select R3 for the desired starting point of
the loop length compensation. The compensation
begins when the voltage across R3 is =0.4 volt.
4) Select R4 and R5 (they should be equal) to properly
bias the microphone. The microphone's manufacturer
should be consulted for this information.
5) Select R6 for proper transmit gain. See equation
1. Then select C5 to provide low frequency roll-off.
Adjust R6 as required.
6) Select the ZB network (RS, Rl 0, CS) to provide sidetone cancellation. See equation 5.
7) Select R8 for proper receive gain (depends on the
specific receiver used). See equation 2. Then select C8
to provide low frequency roll-off. Adjust R8 as required.

MOTOROLA COMMUNICATIONS DEVICE DATA

Additional comments on Figure 1 components:
1) Capacitors C1, C2, and C7 are required to stabilize
the respective regulators. In most applications it should
not be necessary to change from the values shown in
Figure 1.
2) C3 and C4 can be selected to provide low frequency roll-off for the microphone signals.
3) C10 filters noise generated by the MC34114, and
should be close to the VCC pin. Its recommended value
(0.01 ILF) is such that it does not noticeably affect the
system parameters. It can be increased, if desired, to
provide high frequency roll-off for both transmit and
receive signals. This, however, will affect the return loss
specification at higher frequencies.
4) Since TXI is a (relatively) low impedance current
input, it is a convenient point for injecting any signals
which are to be transmitted out onto Tip and Ring. C6
and R7 are shown for transmitting the DTMF signals
from a dialer. Additional RC networks can be connected
to TXI for transmitting signals from speakerphones,
modems, or other signal sources. The voltage gain from
each signal source to Tip and Ring is:
GS -_ lUNEIIR1 x 100 x AGC
(R x

(Equation 6)

+ lcx)

where Rx and lcx represent the impedances of the R
and C for the particular signal source. If several signal
sources are connected to TXI, the parallel combination
of R6, R12, the internal 1.0 k resistor, and any other RCs
at this pin must be considered when setting the gain
for each signal.
FIGURE 27 -

5) The 12 volt zener diode shown in Figure 1 is for
transient protection, and normally does not conduct.
Transient and overvoltage protection MUST be provided externally so that the Absolute Maximum Ratings
are not exceeded.
BASIC TELEPHONE CIRCUIT
Figure 27 depicts a complete basic telephone using
the MC34114speech network, the MC145412 pulse/tone
dialer, and the MC34017 tone ringer.
The MC34114 provides the speech network/hybrid
functions, and its component values are calculated as
described previously in this data sheet. The resistor
from VCC to VB is 820 G (rather than 600 fi) in this
example since it is in parallel with the 2.0 kG resistor in
the pulse dialing transistor network (providing and
effective 600 G termination).
The MC145412 dialer is a pulse/tone dialer with 10
number memory, including last number redial. Power
to the dialer is from the MC34114's VDD output, diode
connected with a memory sustaining battery.
The MC34017 tone ringer (see its data sheet for
details) is connected directly to Tip and Ring as it is not
necessary to disconnect it when off-hook. This circuit
has an REN =0.5, and meets all EIA-470 and Bell system
requirements for impedance, anti-bell tapping, and
turn-on/off thresholds.
OPERATION WITH A POWER SUPPLY
Figure 28 indicates how to incorporate the MC34114
into a circuit where a power supply is used.

BASIC PULSEfTONE TELEPHONE

Hook Switch

1M 300 k
VR
OH

Keypad
1 2 3 A
4 5 6 B
7 8 9 C
0 # D

TSO OPL
LR
43

R1

MC34114
Speech
Network

AGe

MC145412
Dialer

100/LF

~ 510
Me1

OJ·

0.1

c::
0

.s:

c.

e...

13
Me2
MO

Mute

VDD

VDD

~

0.1

Gnd

-=

-=

MS
1k

3V~

0.1 24 k

0.39
24 k

MOTOROLA COMMUNICATIONS DEVICE DATA

VR

MC34114
2-397

FIGURE 28 -

USE WITH A POWER SUPPLY

Tip

Ring

620

VB
221

NC LR
OPL

RAGC
Gnd

MC145412
Dialer

A transformer (T1) is required at Tip and Ring to provide the isolation required between the phone line and
any AC power and earth ground. ,(The transformer must
be rated to handle the loop current.) Since the loop
current does not pass through the MC34114, loop length
compensation is not possible in this circuit, and pin 2
(LR) is left open. The RAGC pin is grounded, setting the
transmit and receive gains to their maximum.
The transformer provides a path for the power supply
to reach the MC34114, while simultaneously coupling
speech signals between Tip/Ring and the MC34114. The
two series diodes provide transient clamping, as does
the 12 volt zener diode. Although a + 9.0 volt supply is
shown, other voltages can be used as long as the
MC34114 receives between 4.0 and 10.5 volts at VCC.
Because of the isolation requirement, the MC145412
dialer requires a relay (RL 1) to break the loop current
during pulse dialing. The relay is normally off, and energized only during pulse dialing. The 1.0 I£F capacitor
(rated 250 volts min., NPO) across the relay contacts
helps absorb transients generated during pulse dialing.
ALTERNATE MICROPHONE CONFIGURATIONS
The MC34114 is designed for use with electret microphones, although dynamic microphones can be used.
Carbon microphones are not recommended as they
generally require considerable bias current which is not
available from the MC34114's regulators.
When using an electret microphone which requires
more than 1.7 volts, but less than 1.0 mA for bias, it can
be biased from VDD instead.
If a three terminal electret microphone (containing an
internal biasing resistor or equivalent) is used, it should
be connected to the MC34114 as shown in Figure 29.
The common mode rejection of the balanced circuit
shown in Figure 1 is not present however, and care
should be taken to prevent unwanted signals (radio sta-

MC34114
2-398

MC34114
Speech
Network

tions, noise, etc.) from being picked up by the microphone leads.
FIGURE 29 -

3-TERMINAL MICROPHONE

Figure 30 indicates use ofthe MC34114 with a dynamic
microphone. The output level of dynamic microphones
is generally lower than electret units, and so the gain
of the transmit path will have to be adjusted
accordingly.
FIGURE 30 -

DYNAMIC MICROPHONE

MC1

MC34114

Dynamic
Microphone
MC2

MOTOROLA COMMUNICATIONS DEVICE DATA

s:

a

FIGURE 32 -

PULSEfTONE FEATUREPHONE WITH MEMORY -

CD;.cn
+~_.
0:-.a.

,.-0"

=

10

~: ~~ c:P~:~~~:;~:!r~~:~~:~':t~:~d3 poles.

o==

"'ID ........

1D,p.

S5 = Speakerphone on/off switch - 1 pole.
Switches shown in on·hook position.
31 All diodes 1N4002.
41 These resistors depend on the specifi~ microphones.

&..:4:;,:7~k~~.:..:..:....J
'

-;c:g.
co

;.
..... -CD3.
_."'ox_
:::::IO~S"'"

..... ~m..,m

:r:I:<:::I:::I

CD~CD~Q.

n
n1 I~
s:
0

"'-r

:Il
m
l>

iii

C;;>g

.c
c:

Mute

-=-

-=-

'11~:Il
m

III

3S'

~

o·~
:::I
~

~

I
-I

~
zen

s:

::j

::z:
....
:II

...':"'0

CD
0.

~

:::J ::::

~.~~[~

tIICDC:

+

NOTES:

n ""

mO' cnn(')
0.3 -jo>:r::C

CD:II~

Meo

:::::I

~:r;-!!!.«

_CDWo oo:rm~l>
;-.gm:r ::JnCDa.~~

MT
RAGe

0
~

1\)'"
,,p.

."

:a

iii'"_C'"onQ.a3CD~m
~,~<:E ~r+:E'C <'CD 0

:0

0

"-I
~

....
....

~i:

82
0""

FIGURE 33 - PULSEfTONE FEATUREPHONE WITH MEMORY -

......

:T

LINE POWERED

3CD '":::J
3o.
o en
<·S

HS1~

""

fl

8.2
From

~

TSO

1M'

3.9

k~

N~

,

MC34114

~

Network

5 Gnd

en en

...

CD
CD
......

"0"' ....
m0
_..CD'

<>",.c
~.~.;

~~:j'~O
~"'~c.~

:::l :::l
'" <0 <>

g~ a:!!C
:::JQ)CDCC

~ fJ~
-g '", g

m

Speech

m;g.~sa

a.-'COCDCi)

<>
_.

CDo=o.
::::J 0 CD
... CD :E '2.
0 0 :j" 0

'::r ....

~-g.0'~2

15 ZB

CD.~

:::::!.Q)

,

;,~

""'i0

o <
-

5.
"ITI
.-+ _. ~
en ~ ~ g-~

g3~~mmg.~
CD
y;-~ g.~~~~3

-'mCDO_

s:

ao
::0

>
~
s:
c

z

('j

:!:i
~
CJ)

Cl

~
m

('j

Cl

~

>

CD <

.

:::l '"

o.~~S:S:~g,
co-a.nn CD ....,
Sen
~w-c:
-.::::T»......Io~m::::J

NOTES:
1) HS = Handset operated switch - 3 poles.
55 = Speakerphone onloff switch - 1 pole.
Switches shown in on-hook position.
2) Microphone biasing resistor values depend on the specific
microphone.
3) All diodes 1N4002.

prg

~oo=:a.g.
mC::°ocnCOcng
en

"0

en

"0 ..

~g-~m-gm~

~8~[~[~

20

~ ~

g a1

~

~'~CD n~oCS

14

n"O:::r
g-'Nl>" ~8

!:!'.O W'

VB
15

.." ~-a:::r ~~.
0

I:: -. 0

~ S~ ffi

CT

en g.",:g ~~.3
::'I = _. 0"0
..... cO· a. g CD? CD

I

o en

TL02 AL02 22
181..19 AXO

~I'F~I'F

... ::'I..,,!:!,. .." . ..,,~
~ OJ cO' 0 cO' cO'
en :::s I:: :::s t: I:: _.

a

Volume
Control

coo.-.:::s-.-.O
"'"0 CD 0

CD

CD

::'I

~CDWcDWWO'

07WcnWN-.

EMI SUSCEPTIBILITY
Potential EMI susceptibility problems should be
addressed early in the electrical and mechanical design
of the telephone. EMI may enter the circuit through Tip
and Ring, through the microphone wiring, or through
any of the PC board traces. The most seri'sitive pins on
the MC34114 are the microphone amplifier inputs (MC1,
MC2). Board traces to these pins should be kept short,
and the associated components should preferably be

physically close to the pins. TXI, RXI, and ZB should
also be considered sensitive to EMI signals.
The microphone wires within the handset cord can
act as an antenna, and pick up nearby radio stations. If
this is a problem in the final design, adding RF filters
(consisting of ferrite beads and small (0.001 JLF) ceramic
capacitors) to the PC board where the wires attach to
the board can generally reduce the problem.

SUGGESTED VENDORS
Microphones
Primo Microphones Inc.
Bensenville, III. 60106
312-595-1022
Model EM-60
Telecom Transformers
Microtran Co., Inc.
Valley Stream, N.Y. 11528
516-561-6050
Ask for Applications
Bulletin F232

MURA Corp.
Westbury, N.Y. 11590
516-935-3640
Model EC-983-7

Hosiden America Corp.
Elk Grove Village, III. 60007
312-981-1144
Model KUC2123

Stancor Products
Logansport, IN 46947
219-722-2244

PREM Magnetics, Inc.
McHenry, III. 60050
815-385-2700

Onan Power/Electronics
Minneapolis, MN 55437
612-921-5600
Motorola Inc. does not endorse or warrant the suppliers referenced.
Compliance with FCC or other regulatory agencies of the circuits described herein is not implied or guaranteed by
Motorola Inc.

MOTOROLA COMMUNICATIONS DEVICE DATA

MC34114
2-401

MOTOROLA

-

SEMICONDUCTOR
TECHNICAL DATA

MC34115

Specifications and Applications
Information

CONTINUOUSLY VARIABLE
SLOPE DELTA
MODULATOR/DEMODULATOR

CONTINUOUSLY VARIABLE SLOPE
DELTA MODULATOR/DEMODULATOR
Providing a simplified approach to digital speech encodingl
decoding, the MC34115 CVSD is designed for speech synthesis
and commercial telephone applications. A single IC provides both
encoding and decoding functions.
• Encode and Decode Functions Selectable with a Digital Input
• Utilization of Compatible 12L - Linear Bipolar Technology
• CMOS Compatible Digital Output
• Digital Input Threshold Selectable (VCC/2 reference provided
on chip)
• 3-Bit Algorithm

1

P SUFFIX

PLASTIC PACKAGE
CASE 648

CVSD BLOCK DIAGRAM
PIN CONNECTIONS

Encode!
Decode

Analog Input
Anelog Feedback

VCC
Analog
Input (-I 1

1
2

Analog
Feedback (+ I

Digital Data Input 13
Digital Threshold

Syllabic
Filter

.,.t-2p,;---~~~H~~_ _-,
Logic

11 Coincidence
Output

Digital Output O-,-9t-----4-----t---i
Syllabic Filter
Gain Control

5
Analog
Output

MC34115
2-402

15 Encodel
Decode

Gain
Control

Digital Data
Input (-I

Ref
Input (+1

Digital
Threshold

Filter
Input(-I 6

Coincidence
Output

Analog
Output

Vcd2

Output

DigHal
Output

Ref
Filter
Input Input
1+1 (-I

MOTOROLA COMMUNICATIONS DEVICE DATA

MAXIMUM RATINGS
(All voltages referenced to VEE, TA = 25'C unless otherwise noted.) (See Note 2.)
Symbol

Value

Power Supply Voltage

Rating

VCC

-0.4 to + 18

Vdc

Differential Analog Input Voltage

VID

±5.0

Vdc

Digital Threshold Voltage

Unit

VTH

-0.4 to VCC

Vdc

VLogic

-0.4 to +18

Vdc

Coincidence Output Voltage

VO(Conl

-0.4 to +18

Vdc

Syllabic Filter Input Voltage

VI(Svl)

-0.4 to VCC

Vdc

Gain Control Input Voltage

VI(GC)

-0.4 to VCC

Vdc

Reference Input Voltage

VI(Ref)

VCC/2-1.0 to VCC

Vdc

VCC/2 Output Current

IRef

-25

rnA

Operating Ambient Temperature Range

TA

Operating Junction Temperature

TJ

+150

·C

TstQ

-55to +125

·C

Logic Input Voltage
(Clock, Digital Data, Encode/Decode)

Storage Temperature Range

o to

+70

·C

ELECTRICAL CHARACTERISTICS
(VCC

= 12 V

VEE

= Gnd

TA

= O°C to

+ 70°C unless otherwise noted)

Characteristic

Symbol

Min

Typ

Max

Unit

Power Supply Voltage Range (Figure 1)

VCC

4.75

12

16.5

Vdc

Power Supply Current (Figure 1)
(Idle Channel)
VCC = 5.0 V
VCC = 15V

ICC

rnA

-

4.6
7.0
16 k

SR

-

IGCR

0.002

Analog Comparator Input Range (Pins 1 and 2)
4.75 V.:; VCC .:; 16.5 V

VI

Analog Output Range (Pin 7)
4.75 V.:; VCC':; 16.5 V, 10

Vo

Clock Rate
Gain Control Current Range (Figure 2)

=

liB

Input Offset Current
Comparator in Active Region
Analog Input/Analog Feedback
111-121- Figure 3
Integrator Amplifier
115-161- Figure 4

110

Input Offset Voltage
V/I Converter (Pins 3 and 4) -

VIO

-

Samples/s

3.0

rnA

1.3

-

VCC -1.3

Vdc

1.3

-

VCC -1.3

Vdc

±5.0 rnA

Input Bias Currenis (Figure 3)
Comparator in Active Region
Analog Input (11)
Analog Feedback (12)
Syllabic Filter Input (13)
Reference Input (15)

7.5
12

pA

-

-

0.5
0.5
0.06
-0.06

2.5
2.5
0.5
-0.5

pA

-

0.15

0.8

0.02

0.2

-

2.0

10

0.1
1.0

0.3
10

-

-

1.0
0.8
1.0
0.8

3.0
3.0
3.5
2.5

mV

Figure 5

Transconductance
V/I Converter, 0 to 3.0 rnA
Integrator Amplifier, 0 to + 5.0 mA Load
Propagation Delay Times (Note 1)
Clock Trigger to Digital Output
CL = 25 pF to Gnd
Clock Trigger to Coincidence Output
CL = 25 pF to Gnd
RL = 4.0 kG to VCC

gm

tpLH
tpHL
tpLH
tpHL

mA/mV

-

IL s

NOTES 1. All propagatIon delay tImes measured 50% to 50% from the negatIve gOing (from Vee to + 0.4 VI edge of the clock.
2. Devices should not be operated at these values. The "Electrical Characteristics" provide conditions for actual device operation.

MOTOROLA COMMUNICATIONS DEVICE DATA

MC34115
2-403

ELECTRICAL CHARACTERISTICS (continued)
Characteristic

Symbol

Min

Typ

Max

Unit

Coincidence Output Voltage Low Logic State
10L(Con) = 3.0 mA

VOL(Con)

-

0.12

0.25

Vdc

Coincidence Output Leakage Current High Logic State
VOH=15V

10H(Con)

-

0.01

0.5

pA

-

VCC -2.0

Vdc

Applied Digital Threshold Voltage Range (Pin 12)

VTH

Digital Threshold Input Current
1.2 V '" Vth '" VCC -2.0 V
VIL applied to Pins 13, 14 and 15
VIH applied to Pins 13, 14 and 15

Il(th)

Maximum Integrator Amplifier Output Current

+1.2

pA

-

5.0
-50

-

-

3.0

6.0

n

Er

-

±3.5

%

VIL
VIH

Gnd
Vth +0.4

-

10

±5.0

VCcJ2 Generator Maximum Output Current
(Source only)

IRef

+10

VCcJ2 Generator Output Impedance
Oto+l0mA

zRef

VCC/2 Generator Tolerance
4.75 V ",VCC'" 16.5 V
Logic Input Voltage (Pins 13, 14 and 15)
Low Log ic State
High Logic State
Dynamic Total Loop Offset Voltage
(Note 3) - Figures 3, 4 and 5
IGC = 33 pA, VCC = 12 V
TA = 25'C
O'C '" TA '" +70'C
IGC = 33 pA, VCC = 5.0 V
TA = 25'C
O'C '" TA '" +70'C
Digital Output Voltage (Pin 9)
10L = 3.6 mA
10H = -0.35 mA
Syllabic Filter Applied Voltage (Pin 3)
Integrating Current (Figure 2)
IGC = 12pA
IGC = 1.5 mA
IGC = 3.0 mA
Dynamic Integrating Current Match (Figure 6)
IGC = 1.5 mA

-

-10

-

mA
mA

Vdc

-

Vth -0.4
16.5
mV

:EVoffset

-

±2.5
±3.0

±7.0
±10

±4.0
±4.5

±B.O
±12
0.4

Vdc

VOL
VOH

VCC -1.0

0.1
VCC -0.2

VUSvll

+3.2

-

VCC

Vdc

B.O
1.4
2.75

10
1.5
3.0

12
1.6
3.25

pA
mA
mA

±100

±300

mV

-

Illntl

VO(Ave)

Input Current - High Logic State
VIH = 16.5V
Digital Data Input
Clock Input
Encode/Decode Input

IIH

Input Current - Low Logic State
VIL = 0 V.
Digital Data Input
Clock Input
Encode/Decode Input
Clock Input, VIL = 0.4 V

IlL

-

pA

-

-

+5.0
+5.0
+5.0
pA

-

-

-10
-360
-36

-72

NOTE 3. Dynamic total loop offset (l:Voffset) equals VIO (comparator) (Figure 3) minus VIOX (Figure 5). The input offset voltages of the analog
comparator and of the integrator amplifier include the effects of input offset current through the input resistors. The slope polarity switch
current mis!'T1atch appears as an average voltage across the 10 k integrator resistor. The clock frequency is 16 kHz. Idle channel performance
is guaranteed if this dynamic total loop offset is less than one-half of the change in integrator output voltage during one clock cycle (ramp
step size).
.

MC34115
2-404

MOTOROLA COMMUNICATIONS DEVICE DATA

DEFINITIONS AND FUNCTION OF PINS
Pin 1 - Analog Input
This is the analog comparator inverting input where
the voice signal is applied. It may be ac or dc coupled
depending on the application. If the voice signal is to
be level shifted to the internal reference voltage, then
a bias resistor between Pins 1 and lOis used. The resistor is used to establish the reference as the new dc
average of the ac coupled signal. The analog comparator was designed for low hysteresis (typically less than
0.1 mV) and high gain (typically 70 dB).
Pin 2 - Analog Feedback
This is the non-inverting input to the analog signal
comparator within the IC. In an encoder application it
should be connected to the analog output ofthe encoder
circuit. This may be Pin 7 or a low pass filter output
connected to Pin 7. In a decode circuit Pin 2 is not used
and may be tied to VCC/2 on Pin 10, ground or left open.
The analog input comparator has bias currents of 2.5
/-LA max, thus the driving impedances of Pins 1 and 2
should be equal to avoid disturbing the idle channel
characteristics of the encoder.
Pin 3 - Syllabic Filter
This is the point at which the syllabic filter voltage is
returned to the IC in order to control the integrator step
size. It is an NPN input to an op amp. The syllabic filter
consists of an RC network between Pins 11 and 3. Typical time constant values of 6 ms to 50 ms are used in
voice codecs.
Pin 4 - Gain Control Input
The syllabic filter voltage appears across Cs of the
syllabic filter and is the voltage between VCC and Pin
3. The active voltage to current (V-I) converter drives
Pin 4 to the same voltage at a slew rate of typically 0.5
V//-Ls. Thus the current injected into Pin 4 (lGC) is the
syllabic filter voltage divided by the Rx resistance. Figure 7 shows the relationship between IGC (x-axis) and
the integrating current, lint (y-axis). The discrepancy,
which is most significant at very low currents, is due to
circuitry within the slope polarity switch which enables
trimming to a low total loop offset. The Rx resistor is
then varied to adjust the loop gain of the codec, but
should be no larger than 5.0 ko' to maintain stability.
Pin 5 - Reference Input
This pin is the non-inverting input of the integrator
amplifier. It is used to reference the dc level ofthe output
signal. In an encoder circuit it must reference the same
voltage as Pin 1 and is tied to Pin 10.
Pin 6 - Filter Input
This inverting op amp input is used to connect the
integrator external components. The integrating current
(lInt) flows into Pin 6 when the analog input (Pin 1) is
high with respect to the analog feedback (Pin 2) in the

MOTOROLA COMMUNICATIONS DEVICE DATA

encode mode or when the digital data input (Pin 13) is
high in the decode mode. For the opposite states, lint
flows out of Pin 6. Single integration systems require a
capacitor and resistor between Pins 6 and 7. Multipole
configurations will have different circuitry. The resistance between Pins 6 and 7 should typically be between
8 ko' and 13 ko' to maintain good idle channel
characteristics.
Pin 7 - Analog Output
This is the integrator op amp output. It is capable of
driving a 600-ohm load referenced to VCC/2 to + 6 dBm
and can otherwise be treated as an op amp output. Pins
5, 6, and 7 provide full access to the integrator op amp
for designing integration filter networks. The slew rate
of the internally compensated integrator op amp is typically 0.5 V//-Ls. Pin 7 output is current limited for both
polarities of current flow at typically 30 mAo
Pin 8 - VEE
The circuit is designed to work in either single or dual
power supply applications. Pin 8 is always connected
to the most negative supply.
Pin 9 - Digital Output
The digital output provides the results of the delta
modulator's conversion. It swings between VCC and
VEE and is CMOS or TTL compatible. Pin 9 is inverting
with respect to Pin 1 and non-inverting with respect to
Pin 2. It is clocked on the falling edge of Pin 14. The
typical 10% to 90% rise and fall times are 250 ns and
50 ns respectively for VCC = 12 V and CL = 25 pF to
ground.
Pin 10 - VCcJ2 Output
An internal low impedance mid-supply reference is
provided for use of the MC34115 in single supply applications. The internal regulator is a current source and
must be loaded with a resistor to insure its sinking capability. If a + 6 dBmo signal is expected across a 600
ohm input bias resistor, then Pin 10 must sink 2.2 V/600
0, = 3.66 mA. This is only possible if Pin 10 sources
3.66 mA into a resistor normally and will source only
the difference under peak load. The reference load resistor is chosen accordingly. A 0.1 /-LF bypass capacitor
from Pin 10 to VEE is also recommended. The VCC/2
reference is capable of sourcing 10 mA and can be used
as a reference elsewhere in the system circuitry.
Pin 11 - Coincidence Output
The coincidence output will be low whenever the content of the internal 3 bit shift register is all ls or all Os.
Pin 11 is an open collector of an NPN device and requires a pull-up resistor. If the syllabic filter is to have
equal charge and discharge time constants, the value
of Rp should be much less than RS. In systems requiring
different charge and discharge constants, the charging

MC34115
2-405

DEFINITIONS AND FUNCTION OF PINS (continued)
constant is RSCS while the decaying constant is (RS +
Rp)CS. Thus longer decays are easily achievable. The
NPN device should not be required to sink more than
3 mAo The typical 10% to 90% rise and fall times are
200 ns and 100 ns respectively for RL = 4 kO to + 12 V
and CL = 25 pF to ground.
Pin 12 - Digital Threshold
This input sets the switching threshold for Pins 13,
14, and 15. It is intended to aid in interfacing different
logic families without external parts. Typically it is connected to the VCC/2 reference for CMOS interface or can
be biased two diode drops above VEE for TTL interface.
Pin 13 - Digital Data Input
In a decode application, the digital data stream is applied to Pin 13. In an encoder it may be unused or may
be used to transmit signaling message under the control
of Pin 15. It is an inverting input with respect to Pin 9.
When Pins 9 and 13 are connected, a toggle flip-flop is
formed and a forced idle channel pattern can be transmitted. The digital data input level should be maintained
for 0.5 JLS before and after the clock trigger for proper
clocking.

Pin 14 - Clock Input
The clock input determines the data rate of the codec
circuit. A 16K bit rate requires a 16 kHz clock. The switching threshold of the .clock input is set by Pin. 12. The
shift register circuit toggles on the falling edge of the
clock input. The minimum width for a positive-going
pulse on the clock input is 300 ns, whereas for a
negative-going pulse, it is 900 ns.
Pin 15 - Encode/Decode
This pin controls the connection of the analog input
comparator and the digital input comparator to the internal shift register. If high, the result of the analog comparison will be clocked into the register on the falling
edge at Pin 14. If low, the digital input state will be
entered. This allows use ofthe IC as an encoder/decoder
or simplex codec without external parts. Furthermore,
it allows non-voice patterns to be forced onto the transmission line through Pin 13 in an encoder.
Pin 16-VCC
The power supply range is from 4.75 to 16.5 volts
between pin VCC and VEE.

FIGURE 2 - IGCR, GAIN CONTROL RANGE and
lint - INTEGRATING CURRENT

FIGURE 1 - POWER SUPPLY CURRENT

IGC
VCC
0.11'F

1.0 k
16
1.0 k

2
3

J

VCC

= VB
Rx

O.lI'F

~
15

1O l'F

14

15
14

CVSD 13
MC34115
12
5

4

Clock

CVSD 13
MC34115
5
12

4
10 k

6

11

7

10

8

9

0.05 JLF

~

Rx" 5.0 k

11

7

10

8

9

Digital
Output.

O.lI'F~

O.lI'F

~

6

'Clock
Digital
Data Input

Note: Digital Output

= Digital Data Input

*For static testing, the clock is only necessary for preconditioning to obtain proper state for a given input.

MC34115
2-406

MOTOROLA COMMUNICATIONS DEVICE DATA

FIGURE 3 - INPUT BIAS CURRENTS, ANALOG
COMPARATOR OFFSET VOLTAGE AND CURRENT

FIGURE 4 - INTEGRATOR AMPLIFIER OFFSET
VOLTAGE AND CURRENT

VCC
VIO
(comparator)

+

VCC

0.1

11

1.0 k

12

1.0 k

:J;/LF
16
:J; 10 /L F

2

15
2

3
Clock

CVSD 14
MC34115
4
13

3

O.I/LF

4
10 k

-

12

15

10 k

5

+

11

6

10

7
8

10.I/LF

9

7

(Integrator
Amplifier
Offset
Voltage)

8

-=

Note: The analog comparator offset voltage is tested under
dynamic conditions and therefore must be measured with
appropriate filtering.

FIGURE 5 -

VII CONVERTER OFFSET VOLTAGE,
VIO and VIOX

FIGURE 6 -

DYNAMIC INTEGRATING CURRENT MATCH
VCC

VCC

16

16
2

15

3

14

60 mV

+ II -

Clock

4

CVSD 13
MC34115
5
12

O.I/LF

VIOX
(Integrator
Amplifier
Offset
Voltage
plus Slope
Polarity
Switch
Mismatch)

6

'Clock Frequency

+

II -

15

3

14

4

10

8

9

1

= 16 kHz

Note: VIOX is the average voltage of the triangular waveform
observed at the measurement points.

MOTOROLA COMMUNICATIONS DEVICE DATA

+
Vo(AV)
(Note 1)

'Clock Frequency

CVSD
MC34115

13

5

12

6

11

7

10

8

9

11

7

Clock

3.0 k

O.I/LF

0.1 /LF

+

IGC

5.0 k

2
4.5 V

= 16 kHz

Notes: 1. Vo(AV), Dynamic Integrating Current Match, is the average voltage of the triangular waveform observed at
the measurement points, across 10 kG resistor with
IGC = 1.5 mA.
2. See Note 3 of the Electrical Characteristics. Page 3.

MC34115

2-407

TYPICAL PERFORMANCE CURVES
FIGURE 8 - NORMALIZED DYNAMIC
INTEGRATING CURRENT MATCH versus VCC

FIGURE 7 - TYPICAL lint versus IGC (Mean ± 2u)

100

+80

g§ 70
u

I 50

1

30

A

t--

i'5
a: 20
a:

a

10

~

7.0

~ +60

~~
~~
C

~

A~

t-Z

~z z~

k
E

:---,

~~
«u

14

15

I----

:---',

t'-

"

~i
c t-~

8.0 9.0 10
11
12
13
VCC, SUPPLY VOLTAGE (VOlTSI

+1.0

+50

N

7.0

FIGURE 10 - DYNAMIC TOTAL LOOP
OFFSET versus CLOCK FREQUENCY

FIGURE 9 - NORMALIZED DYNAMIC INTEGRATING
CURRENT MATCH versus CLOCK FREQUENCY

u

fClK = 16 kHz
(See Figure 6,
Normalized to 10 kfl
@ IGC = 1.5 mAl

V

IGC, GAIN CONTROL CURRENT (!---------------------~

z

o
~

(5

z
en
o

!l!
om
o

»?:i

Ref

Output

Input

6
Filter
Input

sP
VEE

CIRCUIT DESCRIPTION
The continuously variable slope delta modulator
(CVSD) is a simple alternative to more complex conventional conversion techniques in systems requiring
digital communication of analog signals. The human
voice is analog, but digital transmission of any signal
over great distance is attractive. Signal/noise ratios do
not vary with distance in digital transmission and multiplexing, switching and repeating hardware is more
economical and easier to design. However, instrumentation A to D converters do not meet the communications requirements. The CVSD A to D is well suited to
the requirements of digital communications and is an
economically efficient means of digitizing analog inputs
for transmission.
The Delta Modulator
The innermost control loop of a CVSD converter is a
simple delta modulator. A block diagram CVSD Encoder
is shown in Figure 11. A delta modulator consists of a
comparator in the forward path and an integrator in the
feedback path of a simple control loop. The inputs to
the comparator are the input analog signal and the intregrator output. The comparator output reflects the
sign of the difference between the input voltage and
the integrator output. That sign bit is the digital output
and also controls the direction of ramp in the integrator.
The comparator is normally clocked so as to produce a
synchronous and band limited digital bit stream.
If the clocked serial bit stream is transmitted, received,
and delivered to a similar integrator at a remote point,
the remote integrator output is a copy of the transmitting control loop integrator output. To the extent that
the integrator at the transmitting locations tracks the
input signal, the remote receiver reproduces the input
signal. Low pass filtering atthe receiver output will eliminate most of the quantizing noise, if the clock rate of
the bit stream is an octave or more above the bandwidth
of the input signal. Voice bandwidth is 4 kHz and clock
rates from 8 k and up are possible. Thus the delta modulator digitizes and transmits the analog input to a remote receiver. The serial, unframed nature of the data
is ideal for communications networks. With no input at
the transmitter, a continuous one zero alternation is
transmitted. If the two integrators are made leaky, then
during any loss of contact the receiver output decays
to zero and receive restart begins without framing when
the receiver reacquires. Similarly a delta modulator is
tolerant of sporadic bit errors. Figure 12 shows the delta
modulator waveforms while Figure 13 shows the corresponding CVSD decoder block diagram.
The Companding Algorithm
The fundamental advantages of the delta modulator
are its simplicity and the serial format of its output. Its
limitations are its ability to accurately convert the input
within a limited digital bit rate. The analog input must

MOTOROLA COMMUNICATIONS DEVICE DATA

be band limited and amplitude limited. The frequency
limitations are governed by the nyquist rate while the
amplitude capabilities are set by the gain of the
integrator.
The frequency limits are bounded on the upper end;
that is, for any input bandwidth there exists a clock
frequency larger than that bandwidth which will transmit the signal with a specific noise level. However, the
amplitude limits are bounded on both upper and lower
ends. For a signal level, one specific gain will achieve
an optimum noise level. Unfortunately, the basic delta
modulator has a small dynamic range over which the
noise level is constant.
The continuously variable slope circuitry provides
increased dynamic range by adjusting the gain of the
integrator. For a given clock frequency and input bandwidth the additional circuitry increases the delta
modulator's dynamic range. External to the basic delta
modulator is an algorithm which monitors the past few
outputs ofthe delta modulator in a simple shift register.
The register is 3 bits long. The accepted CVSD algorithm
simply monitors the contents of the shift register and
indicates if it contains all1s or as. This condition is called
coincidence. When it occurs, it indicates that the gain
of the integrator is too small. The coincidence output
charges a single pole low pass filter. The voltage output
ofthis syllabic filter controls the integrator gain through
a pulse amplitude modulator whose other input is the
sign bit or up/down control.
The simplicity of the all ones, all zeros algorithm
should not be taken lightly. Many other control algorithms using the shift register have been tried. The key
to the accepted algorithm is that it provides a measure
of the average power or level of the input signal. Other
techniques provide more instantaneous information
about the shape of the input curve. The purpose of the
algorithm is to control the gain of the integrator and to
increase the dynamic range. Thus a measure of the average input level is what is needed.
The algorithm is repeated in the receiver and thus the
level data is recovered in the receiver. Because the algorithm only operates on the past serial data, it changes
the nature of the bit stream without changing the channel bit rate.
The effect of the algorithm is to compand the input
signal. If a CVSD encoder is played into a basic delta
modulator, the output ofthe delta modulator will reflect
the shape of the input signal but all of the output will
be at an equal level. Thus the algorithm at the output
is needed to restore the level variations. The bit stream
in the channel is as if it were from a standard delta
modulator with a constant level input.
The delta modulator encoder with the CVSD algorithm provides an efficient method for digitizing a voice
input in a manner which is especially convenient for
digital communications requirements.

MC34115
2-411

FIGURE 14 - 16 kHz SIMPLEX VOICE CODEC
(Using MC34115, Single Pole Companding and Single Integration)
Digital Input
+5.0

Push
to Talk
Key

Digital Output
(Norm.
open)

15

-=-

A-

1

A+

2

Comp

1>- ~'>-e

13
600
VTH12

"

I
10
0.1 ",F

l

Ana log
Outp ut

1.0
k

-=-

10
k

5
Ref
Input
7

Analog
Out

.-

..-

0-

600

.---

I16 VCC

14

9

I~

Shift
Register

Vccl2
Ref

1

Coin
Out 3.3 k Rp
11

Logic

2.0 VI
disables the IC to conserve power. Input
impedance is nominally 90 kO.

14

CT

An RC at this pin sets the response time
for the circuit to switch modes.

15

VB

4

VCC

A supply voltage of + 2.8 to + 6.5 volts
is required. at ~ 5.0 mAo As VCC falls
from 3.5 to 2.8 volts. an AGC circuit
reduces the receive attenuator gain by
~ 25 dB (when in the receive model.

An output voltage ~VCC/2. This voltage
is a system ac ground. and biases the
volume control. A filter cap is required.

16

CPT

An RC at this pin sets the time constant
for the transmit background monitor.

17

TLl2

Input to the transmit level detector on
the mike/speaker side.

18

TL02

Output of the transmit level detector on
the mike/speaker side. and input to the
transmit background monitor.

19

RL02

Output of the receive level detector on
the mike/speaker side.

5

Name

HTO+

Output of the second hybrid amplifier.
The gain is internally set at -1.0 to
provide a differential output. in
conjunction with HTO -. to the hybrid
transformer.

Name

Description

Description

1

Pin

6

HTO-

Output of the first hybrid amplifier. The
gain of the amp is set by external
resistors.

20

RLl2

7

HTI

Input and summing node for the first
hybrid amplifier. DC level is ~VB.

Input to the receive level detector on the
mike/speaker side.

21

RXI

8

TXO

Output of the transmit attenuator. DC
level is approximately VB.

Input to the receive attenuator and dial
tone detector. Max input level is 350 mV
RMS. Input impedance is ~10 kO.

9

TXI

Input to the transmit attenuator. Max.
signal level is 350 mVrms. Input
impedance is ~10 kO.

22

RXO

Output of the receive attenuator. DC
level is approximately VB.

23

TLl1

10

MCO

Output of the microphone amplifier. The
gain of the amplifier is set by external
resistors.

Input to the transmit level detector on
the line side.

24

TL01

Output of the transmit level detector on
the line side.

11

MCI

Input and summing node of the
microphone amplifier. DC level is

25

RL01

Output of the receive level detector on
the line side. and input to the receive
background monitor.

26

RLl1

Input to the receive level detector on the
line side.

27

CPR

An RC at this pin sets the time constant
for the receive background monitor.

28

GND

Ground pin for the entire IC.

12

MUT

~

VB.

Mute input. A logic low «0.8 VI sets
normal operation. A logic high (>2.0 VI
mutes the microphone amplifier without
affecting the rest of the circuit. Input
impedance is nominally 90 kO.

Note: Pin numbers are identical for the DIP package and the sOle package.

MOTOROLA COMMUNICATIONS DEVICE DATA

MC34118
2-421

~s::

.... 0

~w
~

....
....
....
CD

FIGURE 2 -

MC34118 BLOCK DIAGRAM

Vec

IC~

~
=

I~·

~

. _.. _.

n_. __11/
.___ •

~

a
e
o

I

~
~

VB

22

J

c

15

z

(')

~
5z

en
o
~

(')
m

o
»~

~
I~

120 RLl2 VLC'!'i3 -

o

Volume

~I
Speaker
Amp
MC34119

=

T

=

I
I
I
II

I

~.1.
15 I
-=- mV
I

Dial Tone
Detector

T

L ____ VB_...J

FUNCTIONAL DESCRIPTION
INTRODUCTION
The fundamental difference between the operation of
a speakerphone and a handset is that of half-duplex
versus full-duplex. The handset is full duplex since conversation can occur in both directions (transmit and
receive) simultaneously. A speakerphone has higher
gain levels in both paths, and attempting to converse
full duplex results in oscillatory problems due to the
loop that exists within the system. The loop is formed
by the receive and transmit paths, the hybrid, and the
acoustic coupling (speaker to microphone). The only
practical and economical solution used to date is to
design the speakerphone to function in a half duplex
mode - i.e., only one person speaks at a time, while
the other listens. To achieve this requires a circuit which
can detect who is talking, switch on the appropriate path
(transmit or receive), and switch off (attenuate) the other
path. In this way, the loop gain is maintained less than
unity. When the talkers exchange function, the circuit
must quickly detect this, and switch the circuit appropriately. By providing speech level detectors, the circuit
operates in a "hands-free" mode, eliminating the need
for a "push-to-talk" switch.
The handset, by the way, has the same loop as the
speakerphone. But since the gains are considerably
lower, and since the acoustic coupling from the earpiece
to the mouthpiece is almost non-existent (the receiver
is normally held against a person's ear), oscillations
don't occur.
The MC34118 provides the necessary level detectors,
attenuators, and switching control for a properly operating speakerphone. The detection sensitivity and timing are externally controllable. Additionally, the
MC34118 provides background noise monitors which
make the circuit insensitive to room and line noise,
hybrid amplifiers for interfacing to Tip and Ring, the
microphone amplifier, and other associated functions.
Please refer to the Block Diagram (Figure 2) when reading the following sections.
ATTENUATORS
The transmit and receive attenuators are complementary in function, i.e., when one is at maximum gain
(+ 6.0 dB), the other is at maximum attenuation (-46
dB), and vice versa. They are never both fully on or both
fully off. The sum oftheir gains remains constant (within
a nominal error band of ± 0.1 dB) at a typical value of
- 40 dB (see Figure 10). Their purpose is to control the
transmit and receive paths to provide the half-duplex
operation required in a speakerphone.
The attenuators are non-inverting, and have a - 3.0
dB (from max gain) frequency of =100 kHz. The input
impedance of each attenuator (TXI and RXI) is nominally
10 kO (see Figure 3), and the input signal should be
limited to 350 mVrms (990 mVp-p) to prevent distortion.
That maximum recommended input signal is independent of the volume control setting. The diode clamp on

MOTOROLA COMMUNICATIONS DEVICE DATA

the inputs limits the input swing, and therefore the maximum negative output swing. This is the reason for
VRXOL and VTXOL specification being defined as they
are in the Electrical Characteristics. The output impedance is <10 0 until the output current limit (typically
2.5 mAl is reached.

FIGURE 3 -

TXI
(RXI)

ATTENUATOR INPUT STAGE

d:I:10 k

B

4.0 k

96 k

To Attenuator
llnput

The attenuators are controlled by the single output of
the Control Block, which is measurable at the CT pin
(Pin 14). When the CT pin is at +240 millivolts with
respect to VB, the circuit is in the receive mode (receive
attenuator is at + 6.0 dB). When the CT pin is at - 240
millivolts with respect to VB, the circuit is in the transmit
mode (transmit attenuator is at +6.0 dB). The circuit is
in an idle mode when the CT voltage is equal to VB,
causing the attenuators' gains to be halfway between
their fully on and fully off positions (- 20 dB each). Monitoring the CT voltage (with respect to VB) is the most
direct method of monitoring the circuit's mode.
The inputs to the Control Block are seven: 2 from the
comparators operated by the level detectors, 2 from the
background noise monitors, the volume control, the
dial-tone detector, and the AGC circuit. These seven
inputs are described below.
LEVEL DETECTORS
There are four level detectors - two on the receive
side and two on the transmit side. Refer to Figure 4 the terms in parentheses form one system, and the
other terms form the second system. Each level detector
is a high gain amplifier with back-to-back diodes in the
feedback path, resulting in non-linear gain, which permits operation over a wide dynamic range of speech
levels. Refer to the graphs of Figures 11, 12 and 13 for
their dc and ac transfer characteristics. The sensitivity
of each level detector is determined by the external
resistor and capacitor at each input (TLl1, TLl2, RLl1,
and RLl2). Each output charges an external capacitor
through a diode and limiting resistor, thus providing a
dc representation of the input ac signal level. The outputs have a quick rise time (determined by the capacitor
and an internal 350 0 resistor), and a slow decay time
set by an internal current source and the capacitor. The
capacitors on the four outputs should have the same
value (± 10%) to prevent timing problems.
Referring to Figure 2, on the receive side, one level
detector (RLI1) is atthe receive input receiving the same

MC34118
2-423

FIGURE 4 -

Signal
Input

>-l
0.1/L F

Signal 0.1 /L F
Input

LEVEL DETECTORS

>1

5.1 k

r - - -

-L;;eiDe;;'~

I
350

n

I
I

r======-=.=.=r -,
I
I
Note: External component values are
application dependent.

signal as at Tip and Ring, and the other (RLl2) is at the
output of the speaker amplifier. On the transmit side,
one level detector (TLl2) is at the output of the microphone amplifier, while the other (TLl1) is at the hybrid
output. Outputs RL01 and TL01 feed a comparator, the
output of which goes to the Attenuator Control Block.
Likewise, outputs RL02 and TL02 feed a second comparator which also goes to the Attenuator Control Block.
The truth table for the effects of the level detectors on
the Control Block is given in the section describing the
Control Block.

BACKGROUND NOISE MONITORS
The purpose of the background noise monitors is to
distinguish speech (which consists of bursts) from background noise (a relatively constant signal level). There
are two background noise monitors - one for the
receive path and one for the transmit path. Referring to
Figure 4, the receive background noise monitor is operated on by the RLl1-RL01 level detector, while the transmit background noise monitor is operated on by the
TLl2-TL02 level detector. They monitor the background
noise by storing a dc voltage representative of the
respective noise levels in capacitors at CPR and CPT.
The voltages at these pins have slow rise times (determined by the external RC), but fast decay times. If the
signal at RLl1 (or TLl2) changes slowly, the voltage at
CPR (or CPT) will remain more positive than the voltage
at the non-inverting input of the monitor's output comparator. When speech is present, the voltage on the noninverting input of the comparator will rise quicker than
the voltage at the inverting input (due to the burst characteristic of speech), causing its output to change. This
output is sensed by the Attenuator Control Block.
The 36 mV offset at the comparator's input keeps the
comparator from changing state unless the speech level

MC34118
2·424

exceeds the background noise by =4.0 dB. The time
constant of the external RC (=4.7 seconds) determines
the response time to background noise variations.

VOLUME CONTROL
The volume control input at VLC (Pin 13) is sensed as
a voltage with respect to VB. The volume control affects
the attenuators onlyin the receive mode. It has no effect
in the idle or transmit modes.
When in the receive mode, the gain of the receive
attenuator will be + 6.0 dB, and the gain of the transmit
attenuator will be -46 dB only when VLC is equal to
VB. As VLC is reduced below VB, the gain of the receive
attenuator is reduced (see Figure 14), and the gain of
the transmit attenuator is increased such that their sum
remains constant. Changing the voltage at VLC changes
the voltage at CT (see the Attenuator Control Block section), which in turn controls the attenuators.
The volume control setting does not affect the maximum attenuator input signal at which noticeable distortion occurs.
The bias current at VLC is typically 60 nA out of the
pin, and does not vary significantly with the VLC voltage
or with VCC'
DIAL TONE DETECTOR
The dial tone detector is a comparator with one side
connected to the receive input (RXI) and the other input
connected to VB with a 15 mV offset (see Figure 5). If
the circuit is in the receive mode, and the incoming
signal is greater than 15 mV (10 mVrms), the comparator's output will change, disabling the' receive idle
mode. The receive attenuator will then be at a setting
determined solely by the volume control.
The purpose of this circuit is to prevent the dial tone

MOTOROLA COMMUNICATIONS DEVICE DATA

(which would be considered as continuous noise) from
fading away as the circuit would have the tendency to
switch to the idle mode. By disabling the receive idle
mode, the dial tone remains at the normally expected
full level.
FIGURE 5 -

AGC
The AGC circuit affects the circuit only in the receive
mode, and only when the supply voltage (VCe) is less
than 3.5 volts. As VCC falls below 3.5 volts, the gain of
the receive attenuator is reduced according to the graph
of Figure 15. The transmit path attenuation changes
such that the sum of the transmit and receive gains
remains constant.
The purpose of this feature is to reduce the power
(and current) used by the speaker when a line-powered
speakerphone is connected to a long line, where the
available power is limited. By reducing the speaker
power, the voltage sag at VCC is controlled, preventing
possible erratic operation.
ATTENUATOR CONTROL BLOCK
The Attenuator Control Block has the seven inputs
described above:
The output of the comparator operated by RL02 and
TL02 (microphone/speaker side) - designated C1.
- The output of the comparator operated by RL01 and
TL01 (Tip/Ring side) - designated C2.
- The output of the transmit background noise monitor - designated C3.
- The output ofthe receive background noise monitor
- designated C4.
- The volume control.
- The dial tone detector.
- The AGC circuit.
The single output of the Control Block controls the two
attenuators. The effect of C1-C4 is as follows:
-

Inputs

=

C1

C2

C3

C4'

Tx
Tx
Rx
Rx
Tx
Tx
Rx
Rx

Tx
Rx
Tx
Rx
Tx
Rx
Tx
Rx

1
y
y
X

X
y
y
1
X

Don't Care; y

0
0
0
X
=

control. At max. volume, the receive attenuator is fully on (+6.0
dB), and the transmit attenuator is at max. attenuation (- 46 dB).
3) "Fast Idle" means both transmit and receive speech are present
in approximately equal levels. The attenuators are quickly
switched (30 ms)to idle until one speech level dominates the other.
4) "Slow Idle" means speech has ceased in both transmit and receive
paths. The attenuators are then slowly switched (1 second) to the
idle mode.
5) Switching to the full transmit or receive modes from any other
mode is at the fast rate (=30 ms).

DIAL TONE DETECTOR

To
Attenuator
Control
Block

x

A definition of the above terms:
1) "Transmit" means the transmit attenuator is fully on (+ 6.0 dB),
and the receive attenuator is at max. attenuation (-46 dB).
2) "Receive" means both attenuators are controlled by the volume

0
0
0

Output
Mode

Transmit
Fast Idle
Fast Idle
Receive
Slow Idle
Slow Idle
Slow Idle
Slow Idle

C3 and C4 are not both O.

MOTOROLA COMMUNICATIONS DEVICE DATA

A summary of the truth table is as follows:
1) The circuit will switch to transmit if: a) both transmit level detectors sense higher signal levels relative to
the respective receive level detectors (TLl1 versus RLl1,
TLl2 versus RLl2), and b) the transmit background noise
monitor indicates the presence of speech.
2) The circuit will switch to receive if: a) both receive
level detectors sense higher signal levels relative to the
respective transmit level detectors, and b) the receive
background noise monitor indicates the presence of
speech.
3) The circuit will switch to the fast idle mode if the
level detectors disagree on the relative strengths of the
signal levels, and at least one of the background noise
monitors indicates speech. For example, referring to the
Block Diagram (Figure 2). if there is sufficient signal at
the microphone amp output (TLl2) to override the
speaker signal (RLl2), and there is sufficient signal at
the receive input (RLl1) to override the signal at the
hybrid output (TLl1), and either or both background
monitors indicate speech, then the circuit will be in the
fast idle mode. Two conditions which can cause the fast
idle mode to occur are a) when both talkers are attempting to gain control of the system by talking at the same
time, and b) when one talker is in a very noisy environment, forcing the other talker to continually override
that noise level. In general, the fast idle mode will occur
infrequently.
4) The circuit will switch to the slow idle mode when
a) both talkers are quiet (no speech present). or b) when
one talker's speech level is continuously overriden by
noise at the other speaker's location.
The time required to switch the circuit between transmit, receive, fast idle and slow idle is determined in part
by the components at the CT pin (Pin 14). (See the section on Switching Times for a more complete explanation of the switching time components.) A schematic
of the CT circuitry is shown in Figure 6, and operates
as follows:
-

-

RT is typically 120 k!1, and CT is typically 5.0 fLF.
To switch to the receive mode, 11 is turned on (12 is
off), charging the external capacitor to + 240 mV
above VB. (An internal clamp prevents further charging of the capacitor.)
To switch to the transmit mode, 12 is turned on (11
is off) bringing down the voltage on the capacitor to
- 240 mV with respect to VB.

MC34118
2-425

-

-

To switch to idle quickly (fast idle), the current
sources are turned off, and the internal 2.0 kG resistor is switched in, discharging the capacitor to VB
with a time constant = 2.0 k x CT.
To switch to idle slowly (slow idle), the current
sources are turned off, the switch at the 2.0 kG resistor is open, and the capacitor discharges to VB
through the external resistor RTwith a time constant
= RT x CT.
FIGURE 6 -

CT ATTENUATOR CONTROL BLOCK CIRCUIT

VB
RT
CT

MICROPHONE AMPLIFIER
The microphone amplifier (Pins 10, 11) has the noninverting input internally connected to VB, while the
inverting input and the output are pinned out. Unlike
most op-amps, the amplifier has an all-NPN output
stage, which maximizes phase margin and g.ainbandwidth. This feature ensures stability at gains less
than unity, as well as with awide range of reactive loads.
The open loop gain is typically 80 dB (f <100 Hz), and
the gain-bandwidth is typically 1.0 MHz (See Figure 16).
The maximum pop output swing is typically 1.0 volt less
than Vce with an output impedance of <10 G until cur~
rent limiting is reached (typically 1.5 mAl. Input bias
current at MCI is typically 40 nA out of the pin.
FIGURE 7 -

volts, and the voltage at this pin must be kept within
the range of ground and VCC (see Figure 17). If the mute
function is not used, the pin should be grounded.
HYBRID AMPLIFIERS
The two hybrid amplifiers (at HTO +, HTO -, and HTI),
in conjunction with an external transformer, provide the
two-to-four wire converter for interfacing to the telephone line. The gain of the first amplifier (HTI to HTO -)
is set by external resistors (gain = - RHF/RHI in Figure
2), and its output drives the second amplifier, the gain
of which is internally set at -1.0. Unlike most op-amps,
the amplifiers have an all-NPN output stage, which maximizes phase margin and gain-bandwidth. This feature
ensures stability at gains less than unity, as well as with
a wide range of reactive loads. The open loop gain of
the first amplifier is typically 80 dB, and the gain
bandwidth of each amplifier is =1.0 MHz (see Figure
16). The maximum pop output swing of each amplifier
is typically 1.2 volts less than VCC with an output impedance of <10 G uritil current limiting is reached (typically
8.0 mAl. The output current capability is guaranteed to
be a minimum of 5.0 mAo The bias current at HTI is
typically 30 nA out of the pin.
The connections to the coupling transformer are
shown in the Block Diagram (Figure 2). The block
labeled ZBal is the balancing network necessary to
match the line impedance.
FILTER
The operation of the filter circuit is determined by the
external components. The circuit within the MC34118,
from pins FI to FO is a buffer with a high input impedance (>1.0 MO), and a low output impedance «50 0).
The configuration of the external components determines whether the circuit is a high-pass filter (as shown
in Figure 2), a low-pass filter, or a band-pass filter.
As a high pass filter, with the components shown in
Figure 8, the filter will keep out 60 Hz (and 120 Hz) hum
which can be picked up by the external telephone lines.

MICROPHONE AMPLIFIER AND MUTE
RMF

FIGURE 8 -

_3~01Z[]50
305 Hz

From
Mike

MCI

r,I VCC

Mute

:
I
I

RMI

_J
I

~
I
5k

I

I
I _
'=' _ _ _ "::"_..J
I
75 k

-30

I
fN

Gain=_RMF
RMI

MC34118

2-426

R1
56 k

C1

>-l

VB

~r--vcZ1

~I
~I

for C1 = C2

I

100 k

I

Fd

4700 pF 4700 pF

~

The muting function (Pin 12), when activated, will
reduce the gain of the amplifier to = -39 dB (with RMI
= 5.1 kG) by shorting the output to the inverting input
(see Figure 7). The mute input has a threshold of =1.5

HIGH PASS FILTER

I
I

'='

~

260 /LA '='

I
I

I

~~1~_J

As a low pass filter (Figure 9), it can be used to roll off
the high end frequencies in the receive circuit, which
aids in protecting against acoustic feedback problems.

MOTOROLA COMMUNICATIONS DEVICE DATA

The output voltage at VB (Pin 15) is =(VCC - 0.7)/2,
and provides the ac ground for the system. The output
impedance at VB is =400 n (see Figure 19), and in conjunction with the external capacitor at VB, forms a low
pass filter for power supply rejection. Figure 20 indicates the amount of rejection with different capacitors.
The choice of capacitor is application dependent based
on whether the circuit is powered by the telephone line
or a power supply.
Since VB biases the microphone and hybrid amplifiers, the amount of supply rejection at their outputs is
directly related to the rejection at VB, as well as their
respective gains. Figure 21 depicts this graphically.
The Chip Disable (Pin 3) permits powering down the
IC to conserve power and/or for rTllitiflg purposes. With
CD ';;0.8 volts, normal operation is in effect. Wit,h CD
;;'2.0 volts and .;;VCC, the IC is powered down. In the
powered down mode, the microphone and the .hybrid
amplifiers are disabled, and their outputs go to a high
impedance state. Additionally, the bias is removed from
the level detectors. The bias is not removed from the
filter (Pins 1, 2), the attenuators (Pins 8, 9, 21, 22), or
from Pins 13, 14, and 15 (the attenuators are disabled,
however, and will not pass a signal). The input impedance at CD is typically 90 kn, has a threshold of =1.5
volts, and the voltage at this pin must be kept within
the range of ground and VCC (see Figure 17). If CD is
not used, the pin should be grounded.

With an appropriate choice of an input coupling capacitor to the low pass filter, a band pass filter is formed.
FIGURE 9 - LOW PASS FILTER
40 k

20 k

_3.~t:l;J· C~B
:

I
:

-30

i; JC1C~ R2

for R1

0.01
R2
13 k

Rl
13 k

fN

=

fN

'220 k

FI
C2

0.001I
-

+1

L

FO

.J

MC34118

Vin

= R2

POWER SUPPLY, VB, AND CHIP DISABLE
The power supply voltage at VCC (Pin 4) is to be
between 3.5 and 6.5 volts for normal operation, with
reduced operation possible down to 2.8 volts (see Figure 15 and the AGC section). The power supply current
is shown in Figure 18 for both the power-up and powerdown mode.

FIGURE 10 -

FIGURE 11 - LEVEL DETECTOR DC TRANSFER
CHARACTERISTICS

ATTENUATOR GAIN versus VCT (PIN 14)

......

/'

TRANSMIT
~TTENUATOR

........

-10

./

I'-..

a;
::2

'z -20

«

'"

-50

-240

/'

RECEIVE
ATTENUATOR

f'... . /

V

'"
-160

/

'"z
«

/

SO

---

~

=

u

~CC;;'?5V
0

+SO

=>

60

0

40

1=
=>

r-.....

-60

,/

~ 100
w

I-

"

V

120

:I:

,,/ ..........

-30
-40

-

140

+10

+160

VCT - Va ImVI

MOTOROLA COMMUNICATIONS DEVICE DATA

r-....
+240

20

I

350!}

-r

Va
~
2.0/LF ,
lin
IRLIl RLl2
VOU!
4.0
TLll:TLl21 IRL01. RL02
~ILA
I
T~021 I
I

II
II

p-0l.

-20

'J'

-40
-60
DC INPUT CURRENT lILA)

-so

-100

MC34118
2-427

FIGURE 12 - LEVEL DETECTOR AC TRANSFER
CHARACTERISTICS

FIGURE 13 - LEVEL DETECTOR AC TRANSFER
CHARACTERISTICS versus FREQUENCY

+5.0

~~ll ~
Vin ;.10mV

:>

.s

Vin = 1.0 mVrms"
10 mVrms"
40 mVrms,

~

~
::;;
0

-5.0

A

fE

~

w

'"~

-10

:J:

U

>-

~

I!:
~

-15

Vin

-20

0~0--~--~20----L---~40--~--~S~0--~--~80

300

RECEIVE ATTENUATOR versus VOLUME
CONTROL

-10

I

II
-40

z -18

~
in Receive MOdej-

-24

.~- Minimur Recomrended Lrel

-50

i

0.2

0.4

0.8

~

SO

Gain

~

/

......

Circuit in Receive Mode

V

I I I ~
, -, T I

0.5VB"VLC" B

3.0

3.1
3.2
VCC IVOLTS)

~«"
Valid for
o.. CD, MUT .. VCC

40

/'
20

20

MC34118
2-428

lOOK

3.5

I

14

~

10K
FREQUENCY IHzl

3.4

L

144 gJ

1.0K

3.3

100

180 ~

--'

10K

FIGURE 17...., INPUT CHARACTERISTICS @ CD, MUT

m

II;I!!~
Microphone
Amp Phase

80

3.0K

~ r-

V

2.9

Hybrid Amp o
Phase
36 ffi
I"72 ~
en
I"108 a...
~

t+Ill_ni

.

1.0

FIGURE 16 - MICROPHONE AMPLIFIER AND 1ST HYBRID
AMPLIFIER OPEN LOOP GAIN AND PHASE

+100

3500

Q~p~

11

~ -12

g'"
Circ~it

I I

1

;;;

"

...01

V

-S.O

V

II

-30

I

FIGURE 15 - RECEIVE ATTENUATION GAIN versus VCC

+10

/'

I

1.0K
f, FREQUENCY 1Hz)

INPUT SIGNAL ImVrmsl

FIGURE 14 -

Vin = 1.0'mV~m}

S

IRLll,RLl
TLll, TLl21
0.04~

Xl0kVB +
Vin
Vout 2.0,..F
~.O
@1.0kHz
IRL01, RL02
~~,..A
TL01, TL02)

0

I f - - f - - @ 1.0 kHz

:--L ~l
I "i-..I

~

tOM

o

o

--

L

V

L

..- V

1.0

2.0

3.0
4.0
5.0
INPUT VOLTAGE IVOLTS)

S.5 VCC + 1.0 V

MOTOROLA COMMUNICATIONS DEVICE DATA

FIGURE 18 -

FIGURE 19 -

SUPPLY CURRENT versus SUPPLY VOLTAGE

6.0
5.0

~I

I""

4.0

III

~

3.0

I
..l---l--I

-

v;
~
0

~

I

o
o

./
1.0

-

1.5
1.0

I

1.0

2.0

>'"

I

2.0

-

2.5 I--

CD", O.SV

U 3.0
9

VB OUTPUT CHARACTERISTICS

0.5

2.0'" CD '" VCC t-- t--

............,

- ~d=6.0 c::::::::

-

r--

~C=3.5V

I
2.0

3.0
4.0
VCC (VOLTSI

5.0

6.0

0.5

FIGURE 20 - VB POWER SUPPLY REJECTION versus
FREQUENCY AND VB CAPACITOR

1.0
IB LOAD CURRENT (mAl

-

~

b...

1.5

2.0

FIGURE 21 - POWER SUPPLY REJECTION OF THE
MICROPHONE AND HYBRID AMPLIFIERS

60
so

iii

:s

/500

HtO

/J} i

50

Joo J40 dB is
desirable.
- The MTX line helps define the maximum sidetone
coupling (GST) allowed in the system, which can be
found from the following equation:
G

R4
_
ST - 2 x R2 x GFO

(Equation 14)

Using the component values of Figure 23 in Equation
14 yields a maximum sidetone of a dB. Experience has
shown, however, that a minimum of 6.0 dB loss is
preferable.
The above equations can be used to determine the
resistor values for the level detector inputs. Equation 6
can be used to determine the Rl/R3 ratio, and Equation
10 can be used to determine the R4/R2 ratio. In Figure
24, Rl-R4 each represent the combined impedance of
the resistor and coupling capacitor at each level detector
input. The magnitude of each RC's impedance should
be kept within the range of 2.0 k-15 kn in the voiceband
(due to the typical signal levels present) to obtain the
best performance from the level detectors. The specific
Rand C at each location will determine the frequency
response of that level detector.

APPLICATION INFORMATION
DIAL TONE DETECTOR
The threshold for the dial tone detector is internally
set at 15 mV (10 mVrms) below VB (see Figure 5). That
threshold can be reduced by connecting a resistor from
RXI to ground. The resistor value is calculated from:

R=10k[~e-l]
where VB is the voltage at Pin 15, and flV is the amount
of threshold reduction. By connecting a resistor from
Vce to RXI, the threshold can be increased. The resistor
value is calculated from:
R = 10 k

[vcefl~

their full on and full off positions, the idle mode can be
biased towards the transmit or the receive side. With
this done, gaining control of the circuit from idle will
be easier for that side towards which it is biased since
that path will have less attenuation at idle.
By connecting a resistor from CT (Pin 14) to ground,
the circuit will be biased towards the transmit side. The
resistor value is calculated from:
R = RT

R = RT

MC34118
2·434

[VCCfl~

VB - 1]

R, RT, and flV are the same as above. Switching time
will be somewhat affected in each case due to the different voltage excursions required to get to transmit and
receive from idle. For practical considerations, the flV
shift should not exceed 100 mV.
VOLUME CONTROL
If a potentiometer with a standard linear taper is used
for the volume control, the graph of Figure 14 indicates
that the receive gain will not vary in a linear manner
with respect to the pot's position. In situations where
this may be objectionable, a potentiometer with an
audio taper (commonly used in radio volume controls)
will provide a more linear relationship as indicated in
Figure 26. The slight non-linearity at each end of the
graph is due to the physical construction of the potentiometer, and will vary among different manufacturers.
FIGURE 26 - RECEIVE ATTENUATOR GAIN versus
POTENTIOMETER POSITION USING AUDIO TAPER

+10

I--

where flV is the amount of the threshold increase.

TRANSMIT/RECEIVE DETECTION PRIORITY
Although the MC34118 was designed to have an idle
mode such that the attenuators are halfway between

1]

where R is the added resistor, RT is the resistor normally
between Pins 14 and 15 (typically 120 kfl), and flV is
the difference between VB and the voltage at CT at idle
(refer to Figure 10).
By connecting a resistor from CT (Pin 14) to VCC, the
circuit will be biased towards the receive side. The resistor value is calculated from:

VB - 1]

BACKGROUND NOISE MONITORS
For testing or circuit analysis purposes, the transmit
or receive attenuators can be set to the "on" position,
by disabling the background noise monitors, and applying a signal so as to activate the level detectors. Grounding the CPR pin will disable the receive background
noise monitor, thereby indicating the "presence of
speech" to the attenuator control block. Grounding CPT
does the same for the transmit path.
Additionally, the receive background noise monitor is
automatically disabled by the dial tone detector whenever the receive signal exceeds the detector's threshold.

[~e -

~

b--..
'-...

~ -10

z
=

'1

/

~

>==

i5

I

500

100

./

B.O

> 4.0

V

.......

'"a:z
t!l

~

V

~

g

/

z

20

~

II

DC V-I CHARACTERISTICS

24

I

I
20

40

60

100

BO

120

RECEIVE GAIN

I I

",
.

FigUre23~

~iin = ~SPiRNL I

I vyKII'
5.0K

1.0K
FREQUENCY IHzI

Figure 31 shows how the same circuit can be configured to be powered from a 3.5-6.0 volt power supply
rather than the phone line.

LOOP CURRENT ImAI
FIGURE 31 FIGURE 28 -

AC TERMINATION IMPEDANCE

,-

~

BOO

1/

Filter

'\

I

To _ - - - ' - - . , e . . . . . J

HTO+

Q

~ 400

600

vT;c: I

100/LF
Note 1I

T

OJ~~ure231
I

I IIIII

I

100

1.0K
FREQUENCY IHzI
TRANSMIT GAIN -

5.0K

MICROPHONE TO TIP/RING

50
48

~

z: 44

«

'"

42
40

II

~
+ 5.1 k
..'!M
~

I

100

""

/

46

T
MCI

Figure 23

Wiil

R ~LlNE

Gain = VLlNENM
I I I I I,"
I

I

I

1.0K
FREQUENCY IHzl

MOTOROLA COMMUNICATIONS DEVICE DATA

5.0K

]

-+10......

TOCD_:

II II

o

~

':I:'
-:::t

200

FIGURE 29 -

Switch

To

'\

:z:
N

Hook
To
HTO-

1000

u;- 600
:;;

OPERATING FROM A POWER SUPPLY

To CD ....._ _ _ _.....J_
(MC341191

IIC~:
r+oJ

From
Power
Supply

Dis- 1 I This capacitor must
able
be physically adjacent
to Pin 4 of the MC34118.

ADDING A DIALER
Figure 32 shows the addition of a dialer to the circuit
of Figure 23, with the additional components shown in
bold. The MC145412 pulse/tone dialer is shown configured for DTMF operation. The DTMF output (Pin 18) is
fed to the hybrid amplifiers at HTI, and the DTMF levels
at Tip/Ring are adjusted by varying the 39 kG resistor.
The Mute Output (active low at Pin 11) mutes the microphone amplifier, and attenuates the DTMF signals in the
receive path (by means of the 10 k/3.0 k divider). The
MC34118 is forced into the fast idle mode during dialing.
The 3.0 volt battery provides for memory retention of
the dialer's 10 number storage when the circuit is
unpowered.
RFI INTERFERENCE
Potential radio frequency interference problems
should be addressed early in the electrical and mechanical design of the speakerphone. RFI may enter the cir-

MC34118
2-435

cuit through Tip and Ring, through the microphone wiring to the microphone amplifier, or through any of the
PC board traces. The most sensitive pins on the
MC34118 are the inputs to the level detectors (RLl1,
RLl2, TLl1, TLl2) since, when there is no speech present,
the inputs are high impedance and these op amps are
in Ii near open loop condition. The board traces to these
pins should be kept short, and the resistor and capacitor
for each of these pins should be physically close to the
pins. Any other high impedance input pin (MCI, HTI, FI,
VLC) should be considered sensitive to RFI signals.
IN THE FINAL ANALVSIS ...
Proper operation of a speakerphone is a combination
of proper mechanical (acoustic) design as well as proper
electronic design. The acoustics of the enclosure must
be considered early in the design of a speakerphone. In
general, electronics cannot compensate for poor acoustics, low speaker quality, or any combination of the two.
Proper acoustic separation of the speaker and microphone, as described in the Design Equations, is essential. The physical location of the microphone, along with
the characteristics of the selected microphone, will play
a large role in the quality of the transmitted sound. The
microphone and speaker vendors can usually provide
additional information on the use of their products.
In the final analysis, the circuits shown in this data
sheet will have to be "fine tuned" to match the acoustics
of the enclosure, the specific hybrid, and the specific
microphone and speaker selected. The component values shown in this data sheet should be considered as
starting points only. The gains of the transmit and
receive paths are easily adjusted at the microphone and
speaker amplifiers, respectively. The switching

FIGURE 32 -

response can then be fine tuned by varying (in small
steps) the components at the level detector inputs until
satisfactory operation is obtained for both long and
short lines.

SUGGESTED VENDORS
Microphones
Primo Microphones Inc.
Bensenville, IL 60106
312-595-1022
Model EM-60

MURACorp.
Westbury, N.Y. 11590
516-935-3640
Model EC-983-7

Hosiden America Corp.
Elk Grove Village, IL 60007
312-981-1144
Model KUC2123
25 .n Speakers
Panasonic Industrial Co.
Seacaucus, N.J. 07094
201-348-5233
Model EAS-45P19S
Telecom Transformers
Microtran Co., Inc.
Valley Stream, N.Y. 11528
516-561-6050
Various models - ask for
catalog and Application
Bulletin F232

Stancor Products
Logansport, IN 46947
219-722-2244
Various models - ask for
catalog

Onan Power/Electronics
PREM Magnetics, Inc.
Minneapolis, MN 55437
McHenry, IL 60050
612-921-5600
815-385-2700
Model TC 38-6
Various models - ask
for catalog
Motorola Inc. does not endorse or warrant the
suppliers referenced.

ADDING A DIALER TO THE SPEAKERPHONE

vee
4

4 5 6 B
7 8 9 e
• 0 # D

MC34118
2-436

MOTOROLA COMMUNICATIONS DEVICE DATA

MOTOROLA

-

SEMICONDUCTOR
TECHNICAL DATA

MC34119

Specifications and Applications
Information
LOW POWER
AUDIO AMPLIFIER
LOW POWER AUDIO AMPLIFIER

SILICON MONOLITHIC
INTEGRATED CIRCUIT

The MC34119 is a low power audio amplifier integrated Circuit
intended (primarily) for telephone applications, such as in
speakerphones. It provides differential speaker outputs to maximize output swing at low supply voltages (2.0 volts minimum).
Coupling capacitors to the speaker are not required. Open loop
gain is 80 dB, and the closed loop gain is set with two external
resistors. A Chip Disable pin permits powering down and/or
muting the input sjgnal. The MC34119 is available in a standard
8-pin DIP or a surface mount package.
• Wide Operating Supply Voltage Range (2-16 volts) Telephone line Powered Applications

Allows

• Low Quiescent Supply Current (2.7 mA Typical) for Battery
Powered Applications

P SUFFIX
PLASTIC PACKAGE
CASE 626

• Chip Disable Input to Power Down the IC
• Low Power-Down Quiescent Current (65 p.A Typical)
• Drives a Wide Range of Speaker Loads (8 Ohms and Up)
• Output Power Exceeds 250 mW with 32 Ohm Speaker
• Low Total Harmonic Distortion (0.5% Typical)

1~

• Gain Adjustable from <0 dB to >46 dB for Voice Band
• Requires Few External Components

8

D SUFFIX
PLASTIC PACKAGE
CASE 751
SO-8

BLOCK DIAGRAM AND TYPICAL APPLICATION CIRCUIT
Rf
75 k

r-------- 6 VCC
------,

Ci

I

Audio~·l
Input/!

I

p

Cl
1.0 ILF

C2*
5.0 ILF

PIN CONNECTIONS

cDDa

I

Vin 4

5 VOl

2

FCI

3

6

VCC

I

Vin

4

5

VOl

~~2~~~~~~

(Top View)

FC21

-=-

7

V02
Gnd

FC2

I

I
I

_

MC34119

L...:_-.,. ____ 7
ORDERING INFORMATION
Device

* = Optional
Differential Gain = 2 x

~

MC34119P
MC34119D

MOTOROLA COMMUNICATIONS DEVICE DATA

Temperature
Range
- 20'C to + 70'C

Package
Plastic DIP
Plastic SOIC

MC34119
2·437

ABSOLUTE MAXIMUM RAT1NGS
Parameter
Supply Voltage

Value

Units

-1.0to +18

Vdc

Maximum Output Current at VOl, V02

±250

rnA

Maximum Voltage @ Vin' FC1, FC2, CD

-1.0, VCC+l.0

Vdc

Applied Output Voltage to VOl, V02 when disabled

-1.0, VCC+l.0

Vdc

·C
Junction Temperature
-55, +140
Devices should not·be operated at the.e value •. The "Recommended Operating Limit." provide
for actual device opera~ion.

RECOMMENDED OPERATING LIMITS
.Parameter

Symbol

Min

VCC

+2.0

Load Impedance

RL

8.0

Peak Load Current

IL

-

Supply Voltage

I

Typ

-

Max

Units

+16

Vdc

100

0

±200

rnA

Differential Gain (5.0 kHz bandwidth)

AVD

0

-

46

dB

Voltage @ CD (Pin 1)

VCD

0

.-

VCC

Vdc

Ambient Temperature

TA

-20

-

+70

·C

ELECTRICAL CHARACTERISTICS (TA = 25·C)
Characteristics

Symbol

Mi~

Typ

>30

Max

Units

AMPUFIERS lAC CHARACTERISTICS)
AC Input Resistance (@ Vin)
Open Loop Gain (Amplifier #1, f < 100 Hz)
Closed Loop Gain (Amplifier #2)
(VCC = 6.0 V, f = 1.0 kHz, RL = 320)
Gain Bandwidth Product
Output Power, VCC = 3.0 V, RL = 160, THD .. 10%
VCC = 6.0 V, RL = 320, THD .. 10%
VCC = 12 V, RL = 100 n, THD .. 10%

ri

-

AVOL1

80

-

AV2

-0.35

0

+0.35

GBW

-

Pout3
Pout6
Pout12

55
250
400

-

-

0.5
0.5
0.6

1.0

50

-

-

Total Harmonic Distortion (f = 1.0 kHz)
(Vce = 6.0 V, RL = 320, Pout = 125 mW)
(Vce '" 3.0 V, RL = 8.0 0, Pout = 20 mW)
(VCC'" 12 V, RL = 320, Pout = 200 mW)

THD

Power Supply Rejection (VCC = 6.0 V, !:,vCC = 3.0 V)
(Cl = "", C2 = 0.01 !£F)
(Cl = 0.1 !£F, C2 = 0, f = 1.0 kHz)
(Cl = 1.0 !£F, C2 = 5.0 !£F, f = 1.0 kHz)

PSRR

Muting (VCC = S.O V, 1.0 kHz .. f .. 20 kHz, CD = 2.0 V)

GMT

-

1.5

MO
dB
. dB

-

MHz

-

mW

-

%

12
52

>70

-

dB

dB

AMPUFIERS (DC CHARACTERISTICS)
Output DC Level @ VOl, V02, VCC = 3.0 V, RL = 16 n
(Rf = 75 k)
VCC = 6.0 V
VCC = 12V
Output High Level (lout = -75 rnA, 2.0 V .. VCC .. 16 V)
Output Low Level (lout - 75 rnA, 2.0 V .. VCC" 16 V)

VO(3)
VO(S)
VO(12)
VOH
VOL

1.0

-

1.15
2.65
5.65
VCC-l.0
0.16

1.25

-

Vdc

Vdc
Vdc

-30

0

+30

mV

liB

-

-100

-200

RFCl

100

150

220

nA
kG

RFC2

18

25

40

kG

ICC3
ICC16
ICCD

-

2.7
3.3
65

4.0
5.0
100

mA

Output DC Offset Voltage (V01-V02)
(VCC = 6.0 V, Rf = 75 kO, RL = 32 0)
Input Bias Current @ Vin (VCC = 6.0 V)

!.vO

Equivalent Resistance @ FCl (VCC = 6.0 V)
Equivalent Resistance @ FC2 (VCC = 6.0 V)
CHIP DISABLE (Pin 1)
Input Voltage - Low
Input Voltage --' High
Input Resistance (VCC - VCD - 16 V)
POWER SUPPLY
Power Supply Current .
(VCC = 3.0 V, RL = "", CD = 0.8 V)
(VCC = 16 V, RL = "", CD = 0.8 V)
(VCC = 3.0 V, RL = "", CD = 2.0 V)

..

ItA

Note: Currents Into a pm are positive, currents out of a pin are negative.

MC34119
2-438

MOTOROLA COMMUNICATIONS DEVICE DATA

PIN DESCRIPTION
Symbol

Pin

CD

1

FC2

2

Description
Chip Disable - Digital input. A Logic "0" «0.8 V) sets normal operation. A Logic "1"
the power down mode. Input impedance is nominally 90 kn.

(~2.0

V) sets

A capacitor at this pin increases power supply rejection, and affects turn-on time. This pin can be left
open if the capacitor at Fe1 is sufficient.

FCI

3

Analog Ground for the amplifiers. A 1.0 !LF capacitor at this pin (with a 5.0 !LF capacitor at Pin 2)
provides (typically) 52 dB of power supply rejection. Turn-on time of the circuit is affected by the
capacitor on this pin. This pin can be used as an alternate input.

Vin

4

Amplifier input. The input capacitor and resistor set low frequency rolloff and input impedance. The
feedback resistor is connected to this pin and VOl.

= (VCC

VOl

5

Amplifier Output #1. The dc level is

VCC
GND

6

DC supply voltage (+ 2.0 to + 16 volts) is applied to this pin.

- 0.7 V)/2.

7

Ground pin for the entire circuit.

V02

8

Amplifier Output #2. This signal is equal in amplitude, but 180' out of phase with that at VOl. The dc
level is = (VCC - 0.7 V)/2.

TYPICAL TEMPERATURE PERFORMANCE (-20' < TA < +70'C)
Function
Input Bias Current (@ Vin)
Total Harmonic Distortion
(VCC = 6.0 V, RL = 32 n, Pout = 125 mW, f = 1.0 kHz)

Typical Change

Units

±40

pAI'C
%/oC

+0.003

Power Supply Current
(VCC = 3.0 V, RL = 00, CD = 0 V)
(VCC = 3.0 V, RL = 00, CD = 2.0 V)

!LAf'C

-2.5
-0.03

DESIGN GUIDELINES
GENERAL
The MC34119 is a low power audio amplifier capable
of low voltage operation (VCC = 2.0 V minimum) such
as that encountered in line-powered speakerphones.
The circuit provides a differential output (V01-V02) to
the speaker to maximize the available voltage swing at
low voltages. The differential gain is set by two external
resistors. Pins FCl and FC2 allow controlling the amount
of power supply and noise rejection, as well as providing alternate inputs to the amplifiers. The CD pin permits
powering down the IC for muting purposes and to conserve power.
AMPLIFIERS
Referring to the block diagram, the internal configuration consists of two identical operational amplifiers. Amplifier #1 has an open loop gain of ~80 dB
(at f "" 100 Hz). and the closed loop gain is set by
external resistors Rf and Ri. The amplifier is unity gain
stable, and has a unity gain frequency of approximately 1.5 MHz. In order to adequately cover the telephone voice band (300-3400 Hz), a maximum closed
loop gain of 46 dB is recommended. Amplifier #2 is
internally set to a gain of - 1.0 (0 dB).
The outputs of both amplifiers are capable of sourcing
and sinking a peak current of 200 mAo The outputs can
typically swing to within =0.4 volts above ground, and
to within =1.3 volts below VCC, at the maximum current. See Figures 18 and 19 for VOH and VOL curves.
The output dc offset voltage (V01-V02) is primarily
a function of the feedback resistor (Rf). and secondarily
due to the amplifiers' input offset voltages. The input
offset voltage of the two amplifiers will generally be

MOTOROLA COMMUNICATIONS DEVICE DATA

similar for a particular IC, and therefore nearly cancel
each other at the outputs. Amplifier #l's bias current,
however, flows out ofVin (Pin 4) and through Rf, forcing
VOl to shift negative by an amount equal to [Rf x IlBl.
V02 is shifted positive an equal amount. The output
offset voltage specified in the Electrical Characteristics
is measured with the feedback resistor shown in the
Typical Application Circuit, and therefore takes into
account the bias current as well as internal offset voltages of the amplifiers. The bias current is constant with
respect to VCC.
Fe1 and FC2
Power supply rejection is provided by the capacitors
(Cl and C2 in the Typical Application Circuit) at FCl and
FC2. C2 is somewhat dominant at low frequencies, while
Cl is dominant at high frequencies, as shown in the
graphs of Figures 4-7. The required values of Cl and
C2 depend on the conditions of each application. A line
powered speakerphone, for example, will require more
filtering than a circuit powered by a well regulated
power supply. The amount of rejection is a function of
the capacitors, and the equivalent impedance looking
into FCl and FC2 (listed in the Electrical Characteristics
as RFC1 and RFC2).
In addition to providing filtering, Cl and C2 also
affect the turn-on time of the circuit at power-up, since
the two capacitors must charge up through the internal 50 k and 125 k!1resistors. The graph of Figure 1
indicates the turn-on time upon application of VCC of
+6.0 volts. The turn-on time is =60% longer for VCC
= 3.0 volts, and =20% less for VCC = 9.0 volts. Turnoff time is <10 iLs upon removal of VCc.

MC34119
2-439

FIGURE 1 - TURN-ON TIME versus C1, C2 AT POWER-ON

--

360
300

/'

V

Cl = 5.0/'oF/

i-""

PD = (140°C - TA)/OJA
whereTA is the ambient temperature;
and 0JA is the package thermal resistance (1 OO°C/W for
the standard DIP package, and 180°C/W for the surface
mount package.)

./

......

60

V

o

o

V

./

V-

I--""
Cl = 1.0 /'oF

"'"

VCC switching trom010 +6.~vOlts·1 -

I
I
2.0

4.0
6.0
C2, CAPACITANCE I/'oFI

power. The maximum power which can safely be dissipated within the MC34119 is found from the following
equation:

8.0

10

CHIP DISABLE
The Chip Disable (Pin 1) can be used to power down
the IC to conserve power, or for muting, or both. When
at a Logic "0" (0 to 0.8 volts), the MC34119 is enabled
for normal operation. When Pin 1 is at a Logic "1" (2.0
to VCC volts), the IC is disabled. If Pin 1 is open, that is
equivalent to a Logic "0," although good design practice
dictates that an input should never be left open. Input
impedance at Pin 1 is a nominal 90 kG. The power supply current (when disabled) is shown in Figure 15.
Muting, defined as the change in differential gain
from normal operation to muted operation, is in excess
of 70 dB. The turn-off time of the audio output, from
the application of the CD signal, is <2.0 /Ls, and turn
on-time is 12-15 ms. Both times are independent of Cl,
C2, and VCC.
When the MC34119 is disabled, the voltages at FCl
and FC2 do not change as they are powered from VCC.
The outputs, VOl and V02, change to a high impedance
condition, removing the signal from the speaker. If signals from other sources are to be applied to the outputs
(while disabled), they must be within the range of VCC
and Ground.
POWER DISSIPATION
Figures 8-10 indicate the device dissipation (within
the IC) for various combinations of VCC, RL, and'ioad

The power dissipated within the MC34119, in a given
application, is found from the following equation:
PD = (VCC x ICC) + (lRMS x VCC) - (RL x IRMS2)
where ICC is obtained from Figure 15;
and IRMS is the RMS current at the load;
and RL is the load resistance.

Figures 8-10, along with Figures 11-13 (distortion
curves), and a peak working load current of ±200 mA,
define the operating range for the MC34119. The operating range is further defined in terms of allowable load
power in Figure 14 for loads of 8.0 G, 16 G, and 32 G.
The left (ascending) portion of each of the three curves
is defined by the power level at which 10% distortion
occurs. The center flat portion of each curve is defined
by the maximum output current capability of the
MC34119. The right (descending) portion of each curve
is defined by the maximum internal power dissipation
of the IC at 25°C. At higher ambient temperatures, the
maximum load power must be reduced according to
the above equations. Operating the device beyond the
current and junction temperature limits will degrade
long term reliability.
LAYOUT CONSIDERATIONS
Normally a snubber is not needed at the output of the
MC34119, unlike many other audio amplifiers. However,
the PC board layout, stray capacitances, and the manner
in which the speaker wires are configured, may dictate
otherwise. Generally the speaker wires should be
twisted tightly, and be not more than a few inches in
length.

TYPICAL CHARACTERISTICS
FIGURE 2 - AMPLIRER #1 OPEN LOOP GAIN AND PHASE

FIGURE 3 - DIFFERENTIAL GAIN versus FREQUENCY

100
80

36

plas~

-I'-..........

1
~ 60
--'

~

1

"Gain

« 40

1

_3
CD
:s 2

-l!l~~R!~I!~k
t
°fr' .

z
:;;:
~
'" 24

It

c

20

VRt = 75 k, Ri = 3.0 k

~w /
ffi 16

I'-

k-~ ...HT11i1

RI
0.1 p.F Ri
Input >-I

....

-#1

~lvoUl
#2

o

100

MC34119
2-440

1.0K

10K
t, FREQUENCY IHzI

lOOK

1.0M

o

100

1.0K
t, FREQUENCY IHzI

V01

1111 I I
10K 20K

I

tit

MOTOROLA COMMUNICATIONS DEVICE DATA

POWER SUPPLY REJECTION versus FREQUENCY
FIGURE 4 -

C2

= 10,.F

FIGURE 5 -

0

0
I-C1 ;;'1.0,.F

-

0
I-C1 = 0.1 p.F
0

~30

-

a:
a:

lr O_Cl

=

r-Cl

I::1,J

.......

.........

0

~30
a:
a:

OrCl

-........

o
0
200

r-Cl ;;.1.0 p.F

0

lr

t-

0

1.0K

.............

0
0
200

20K

10K

r-

~O

1.0K

t, FREQUENCY IHzl

FIGURE 6 -

C2

C2 = 5.0 ,.F

= 1.0,.F

10K

t, FREQUENCY IHzl

FIGURE 7 -

C2

20K

=0

60

0
Cl - 5.0 p.F
0

Cl

~30

vr

Cl - 0.1 p.F

-

~

'"<>-2 0
0

o

200

....
Cl

f--Cl

...........

1%

0

1

50

= 1.0 p.F

~'30
a:
a:

.......

'"
<>- 20

t, FREQUENCY IHzl

MOTOROLA COMMUNICATIONS DEVICE DATA

_.... --

f-"'"

:--

= 1.0 p.F
~F

f-"'"

.........

::::--

_f-'

.....

~

---

I J.,...}-

1

10K

f-Cl

~

10 f-Cl1 = 6.1

..............

=0
1.0K

40

1 1

= 5.01LF

20K

o

200

r

1 1
1.0K

t, FREQUENCY IHzl

10K

20K

MC34119
2-441

FIGURE 8 -

1000

~

is
~

FIGURE 9 -

DEVICE DISSIPATION
8.0.0 LOAD

1200

V

Vee=\6VJ'
100o

/Vee = 12V

800

-

j

600

vee=~

~ 200 I I

f..-.....
/'

I

3.0 V_ f - -

Vee

0

.....V .....

'j
oV

V

V

I--

1400 I

/

V

/

60

30

90

120

150

~

/

-

'/

1200
1000

I

o
o

100

~

~

/

600

i5
~4O

~

//

I

011

200

V

V

---

,.I

-~

"

'L

o .......
o

-

200

300

I

I
I
II V

I_I-- Vee = 3.0 V, RL = 8.00
Vee = 6,OV,RL = 320 --..J

I
I

I

I

-

I I Vee = 16V,_Vee = 6,OV,_ /-Vee = 12V_
RL = 320
7 I RL = 320 RL = 160
'IV
\!
\
""iJ-

400

500

oVL.
o

....

200

100

300

II-I- -

Vee = 3,0 V, RL = 160

-

I_--Vee = 3,OV,RL = 8.00

1-"- Vee = 3.0 V, RL = 8,00

Vee = 6,0 V, RL = 320

Vee = 6,0 V, RL = 320

I I

"'I

I.

I

I

I

~/'

200

I
I
I

I

I
Vee = 16V,
RL = 320 Limit

I

Vee = 12V,RL = 320
400
300

OUTPUT POWER ImWI

Vee = 16V,
RL = 320 Limit

I

1/

J

500

400

OUTPUT POWER ImWI

FIGURE 13 - DISTORTION versus POWER
f = 1.3.0 kHz. AVD = 12 dB

DISTORTION versus POWER

= 3.0 kHz. AVD = 34 dB

Vee = 6,0 V, RL = 16 fi /
100

=

Vee = 3,OV,RL = 160

1-1-

I- - Vee = 3.0 V, RL = 160

8

MC34119
2-442

!.

0

0

oV

10

LOAD POWER ImWI

f

2

I
I

vee = 3.0 V

FIGURE 12 -

6

f = 1.0 kHz. AVD

vee = 6,0 V

100

400

DISTORTION versus POWER
34 dB

FIGURE 11 -

Vee = 12::'::'

/'

~

g 800
z
a

300

200

LOAD POWER ImWI

DEVICE DISSIPATION
32.0 LOAD

r-- -Ve~ = 16~......

Vee = 6.0 V I -

J.--

3,0~

Vee

LOAD POWER ImWI

FIGURE 10 -

Vee = 12V

/

I
o I /
o /
I t.,...-'"
200

.......1

./

:,..-"

o

DEVICE DISSIPATION
16.0 LOAD

I

I\

I II

I
500

o
o

100

\

Vee = 6.0V,
_
RL = 160 Limit j
y

"

200

300

!l

Vee = 12V
RL = 320
\

400

500

OUTPUT POWER ImWI

MOTOROLA COMMUNICATIONS DEVICE DATA

FIGURE 15 - POWER SUPPLY CURRENT

FIGURE 14 - MAXIMUM ALLOWABLE LOAD POWER
500

4.0

\

RL-32n/

RL = co

\

400
RL

~

..s
300
a:

= 16n

/I

~

roo

/

'I

TA

= 25°e -

I--

r-...

RL

\

= B.on

~

~
...... 1--.,

..........

-

Derate at higher temperatures
B
10
Vee (VOLTSI

1.0

......

r-

12

14

eo

o )
o

16

2.0

FIGURE 16 - SMALL SIGNAL RESPONSE

4.0

6.0

Vee
12

8.0
10
Vee (VOLTSI

\..

INPUT
1.0 mViDiv

INPUT
60 mViDiv
20 JLSIDiv

20 JLSIDiv

FIGURE 19 - VOL @ V01, V02 versus LOAD CURRENT

FIGURE 18 - VCe-VOH @ V01, V02 versus LOAD CURRENT
1.5

1.4

1.4

1.2 -TA

_ 1.3
~ 1.2

./

6
't,1.1

./

./

....-"2.0 V '" Vee'" 16 V-

I

./

1.0

./
./

TA

o

40

MOTOROLA COMMUNICATIONS DEVICE DATA

/

~ o. B
~

7

6 0.6

./

>

./

0.4
0.2

I
I
80
120
LOAD eURRENT (mAl

/

= 25°e_

./
160

200

I

I

Jee = ~.OV7

= 25°e

1.0

./

!:i

0.8 k-""

16

OUTPUT
1.0 VlDiv

\.

0.9

14

FIGURE 17 - LARGE SIGNAL RESPONSE

OUTPUT
20 mViDiv

.fi'

-

0

~

~ 2.0

\.

'\.

I

oo

3.0

1\

n

100

eD

\

-

o
o

/
Vee

= 3.0 V

......-I'"

.-- ~

Vee" 6.0 V

I
I

I-""
40

80
120
LOAD eURRENT (mAl

160

200

MC34119
2-443

FIGURE 20 -

INPUT CHARACTERISTICS @ CD (PIN 1)

FIGURE 21 -

AUDIO AMPLIFIER WITH HIGH INPUT IMPEDANCE
75 k

200

./

160

./

,/
0

0

V

/

40

V

/

./

o ../

""

I

Valid lor VCO '" VCC

I
1-

o

8.0
VCO IVOLTSI

4.0

12

L..:_____ _

16

7

Differential Gain = 34 dB
Frequency Response: See Figure 3

Input Impedance
= 50 dB

= 125 kG

PSRR

FIGURE 22 -

AUDIO AMPLIFIER WITH BASS SUPPRESSION

FIGURE 23 -

75 k

0.05

0.05

FREQUENCY RESPONSE OF FIGURE 22

36

~"~~+-~

v-

32

~
~

=

0.1
Input )-j

C!l

24

i-'"

~

~ 16

V
it
c

I

V

8.0

I
I

_

L~

MC34119

______ 7

o

1.0K

100

10K

20K

I. FREQUENCY IHzI

FIGURE 24 -

AUDIO AMPLIFIER WITH BANDPASS

1000 pF

FIGURE 25 -

FREQUENCY RESPONSE OF FIGURE 24

100 k

36

100 k
0.05

.....

32

0.05

m

~"~~+-~

:E

z

«

24

C!l

=Input)-j0.1

"-

/

~

15 16 L'

~

c

I

8.0

o

I

100

1L.:
_____ _

1.0K

10K

20K

f. FREQUENCY IHzI

7

MC34119
2-444

MOTOROLA COMMUNICATIONS DEVICE DATA

FIGURE 26 - SPLIT SUPPLY OPERATION
Rf 75 k

Ci
Audio
Input

0.1

)--11-1V\1\r<~-o-'-+----1

I

I

I

MC34119
L _______

7 ______

VEE
(-1.0 to -8.0 V)

I

Disable
10 k

NOTE; If Vee and VEE are not symmetrical about ground then Fel must be
connected through a capacitor to ground as shown on the front page.

MOTOROLA COMMUNICATIONS DEVICE DATA

Chip

~

VEE

MC34119
2-445

MOTOROLA

-

SEMICONDUCTOR
TECHNICAL DATA

MC34129
MC33129
Specifications and Applications
Information

HIGH PERFORMANCE
CURRENT MODE CONTROLLER

HIGH PERFORMANCE CURRENT MODE CONTROLLER
The MC34129 series are high performance current mode switch·
ing regulators specifically designed for use in low power digital
telephone applications. These integrated circuits feature a unique
internal fault timer that provides automatic restart for overload
recovery. For enhanced system efficiency, a start/run comparator
is included to implement bootstrapped operation of VCC. Other
functions contained are a temperature compensated reference,
reference amplifier, fully accessible error amplifier, sawtooth os·
cillator with sync input, pulse width modulator comparator, and
a high current totem pole driver ideally suited for driving a power
MOSFET.
Also included are protective features consistin·g of soft·start,
undervoltage lockout, cycle·by·cycle current limiting, adjustable
dead time, and a latch for single pulse metering.
Although these devices are primarily intended for use in digital
telephone systems, they can be used cost effectively in many
other applications.
• Current Mode Operation to 300 kHz
• Automatic Feed Forward Compensation

SILICON MONOLITHIC
Ir~TEGRATED CIRCUIT

".
14#
1

P SUFFIX·
PLASTIC PACKAGE
CASE 646

DSUFFIX
PLASTIC PACKAGE
CASE 751A
SO·14

• Latching PWM for Cycle·By·Cycle Current Limiting
• Continuous Retry after Fault Timeout
• Soft·Start with Maximum Peak Switch Current Clamp
• Internally Trimmed 2% Bandgap Reference
• High Current Totem Pole Driver
• Input Undervoltage Lockout

PIN CONNECTIONS

• Low Start·Up and Operating Current
• Direct Interface with Motorola SENSEFET Products

Drive Output 1
Drive Ground 2

SIMPLIFIED BLOCK DIAGRAM

13 Start/Run Output

Ramp Input 3

Start/Run Output

SynC/I~~:~~ 4

11 Feedback!
PWM Input
10 Error Amp
Inverting Input
9 Error Amp
Non-Inverting Input

vee
"-----'

8 V re! 1.25 V

(Top Viewl

7

Gnd~

vre ! 2.5 V 0 - ' ' - - - - <

Non-Inverting
Input
Inverting
Input

'---'-'0 Feedback!
1 PWM Input
Drive Out

ORDERING INFORMATION
Device

MC34129D
Drive Gnd

SynC/I~~~b~! 0-='------'

'--------"<> Ramp

Input

MC34129P

Temperature
Range

o to
o to

+70°C
+70°C

Package
SO·14 Plastic DIP
Plastic DIP

MC33129D

-40 to +85°C

SO·14 Plastic DIP

MC33129P

-40 to +85°C

Plastic DIP

SENSEFET is a trademark of Motorola Inc.

MC34129.MC33129
2-446

MOTOROLA COMMUNICATIONS DEVICE DATA

MAXIMUM RATING
Symbol

Valua

Unit

IZ(VCC)

50

rnA

IZIStartlRunl

50

rnA

-

-0.3 to 5.5

V

Sync Input Voltage

Vsvnc

-0.3 to VCC

V

Drive Output Current, Source or Sink

IDRV

1.0

A

Current, Reference Outputs (Pins 6, 8)

Iref

20

rnA

PD
RIIJA

552
145

mW
.C/W

PD
RIIJA

800
100

mW
.C/W

Operating Junction Temperature

TJ

+150

·C

Operating Ambient Temperature
MC34129
MC33129

TA

Rating
VCC Zenar Current
StartlRun Output Zenar Current
Anaiog Inputs (Pins 3, 5, 9, 10, 11, 12)

Power Dissipation and Thermal Characteristics
D Suffix Package 50-14 Case 751A-Ol
Maximum Power Dissipation @ TA = 70·C
Thermal Resistance Junction to Air
P Suffix Package Case 646-06
Maximum Power Dissipation @ TA = 70·C
Thermal Resistance Junction to Air

·C

oto

+70
-40 to +85

Storage Temperature Range

Tsto

-65 to +150

·C

ELECTRICAL CHARACTERISTICS (VCC = 10 V, TA = 25·C [Note 11 unless otherwise noted)

I

Characteristic

Symbol

I

Min

I

Typ

Max

1.250
2.500

1.275
2.625

Unit

REFERENCE SECTIONS
Reference Output Voltage, TA
1.25 V Ref., IL = 0 rnA
2.50 V Ref., IL = 1.0 rnA

= 25·C

Reference Output Voltage, TA
1.25 V Ref., IL = 0 rnA
2.50 V Ref., IL = 1.0 rnA

= Tlow to Thigh

1.225
2.375

V

Vref
1.200
2.250

Line Regulation (VCC = 4.0 V to 12 V)
1.25 V Ref., IL = 0 rnA
2.50 V Ref., IL = 1.0 rnA

Regline

Load Regulation
1.25 V Ref., IL
2.50 V Ref., IL

Regload

=
=

V

Vref

1.300
2.750
mV

-

-10 to +500 pA
-0.1 to +1.0 rnA

-

-

2.0
10

12
50

-

1.0
3.0

12
25

1.5

-

10

-

25

-

mV

ERROR AMPLIFIER
Input Offset Voltage (Vin
TA = 25·C
TA = Trow to Thiah

= 1.25 V)

Input Offset Current (Vin

= 1.25 V)

Input Bias Current (Vin
TA = 25·C
TA = Tlow to Thiah

VIO

110

= 1.25 V)

liB

-

nA

-

200

-

V

87

-

dB

-

= 1.25 V)
Gain Bandwidth Product (VO = 1.25 V, f = 100 kHz)
Power Supply Rejection Ratio (VCC = 5.0 to 10 V)
Output Source Current (VO = 1.5 V)

AVOL

Note 1. Trow = O"C for MC34129
= - 4O"C for MC33129

nA

65

V,CR

Output Voltage Swing
High State (lSource = 0 pAl
Low State (lSink = 500 pAl

10

0.5 to 5.5

Input Common-Mode Voltage Range
Open-Loop Voltage Gain (VO

-

mV

GBW

500

750

PSRR

65

85

-

ISource

40

80

-

VOH
VOL

1.75

1.96
0.1

kHz
dB

pA
V

-

2.25
0.15

Thigh = + 7O"C for MC34129
= + 85"C for MC33129

MOTOROLA COMMUNICATIONS DEVICE DATA

MC34129.MC33129
2-447

I

ELECTRICAL CHARACTERISTICS (VCC

= 10 V, TA = 25"C [Note 11 unless otherwise noted)

I

Characteristic

Symbol

I

Min

I

Max

Unit

275

400

mV

-120

-250

pA

Typ

PWM COMPARATOR
Input Offset Voltage (Vin = 1.25 V)

VIO

150

Input Bias Current

liB

-

Propagation Delay, Ramp Input to Drive Output

tPLH(lN/DRV)

250

-

ns

SOFT-START

= 0 V)
= 1.25 V)

0.75

Capacitor Charge Current (Pin 12

Icha

1.2

1.50

pA

Buffer Input Offset Voltage (Vin

VIO

-

15

40

mV

VOL

-

0.15

0.225

V

tDLY

200

400

600

/Ls

=

Buffer Output Voltage (lSink

100 /LA)

FAULT TIMER
Restart Delay Time
STARTIRUN COMPARATOR
Threshold Voltage (Pin 12)

Vth

-

2.0

-

V

Threshold Hysteresis Voltage (Pin 12)

VH

-

350

-

mV

VOL

9.0

10

10.3

V

-

0.4

2.0

pA

Output Voltage (lSink

=

500 pAl

Output Off-State Leakage Current (VOH
Output Zener Voltage (lZ

=

=

15 V)

IS/R(leak)

10 rnA)

Vz

(VCC

+ 7.6)

-

V

OSCILLATOR

=

=

fOSC

BO

100

120

kHz

Idischa

240

350

460

pA

Sync Input Current
High State (Vin = 2.0 V)
Low State (Vin = O.B V)

IIH
IlL

-

40
15

125
35

Sync Input Resistance

Rin

12.5

32

50

VOH
VOL

B.3

-

B.9
1.4

I.B

-

225

-

Frequency (RT

25.5 k!l, CT

390 pF)

Capacitor CT Discharge Current (Pin 5

=

1.2 V)

pA

kG

DRIVE OUTPUT
V

Output Voltage
High State (lSource = 200 rnA)
Low State (lSink = 200 rnA)
Low State Holding Current
Output Voltage Rise Time (CL
Output Voltage Fall TIme (CL

IH

= 500 pF)
= 500 pF)

ns

30

100

225

350

kG

ICC

1.0

2.5

4.0

rnA

Vz

12

14.3

-

V

100

RpD

tf

Output Pull-Down Resistance

/LA

-

-

tr

ns

UNDERVOLTAGELOCKOUT
Start-Up Threshold
Hysteresis
TOTAL DEVICE
Power Supply Current
RT = 25.5 kG, CT = 390 pF, CL
Power Supply Zener Voltage (lz
Note 1. Tlow = O"C for MC34129
= - 40"C for MC33129

MC34129.MC33129
2-448

=

=

500 pF

10 rnA)
Thigh =
=

+ 70"C for MC34129
+ 85"C for MC33129

MOTOROLA COMMUNICATIONS DEVICE DATA

FIGURE 1 - TIMING RESISTOR versus OSCILLATOR
FREQUENCY
1.0M
VCC lOV=
TA 25°C
500 K

FIGURE 2 - OUTPUT DEAD-TIME versus
OSCILLATOR FREQUENCY

100

=

o CT

= 5.0 nF

"-

§
200 K

c:

5i

0

I"-

i'....

u;

:i! 100 K

I'

"-

=2~j=f:o:;

T

nF

./

I

, nFf

../

V

/

,/

500 't=20~:; 11100 ~I=
pF '-- P~ pF r----i-

I

L

<.:l

Z

~ 50 K

0

"-

.f
20 K

10

FIGURE 3 -

~

g
<.:l

G

100
20
50
fose, OSCILLATOR FREQUENCY 1kHz)

1. oV

V

5.0

10

500

~
z

«

40

<.:l
<.:l

«

~

o

~
0
:>
0

u

i-s, 0

""',

Vo~1.25V

0
+25
+50
+75
TA, AMBIENT TEMPERATURE 1°C)

RL
TA

Gain

'-."

~

0

-20
1.0K

+125

= 25°C

r"r--

.;,

+100

~ ~

Phase

~

~
-25

V~C ~ 11b V

~
0
'-.

500

200

ERROR AMP OPEN-LOOP GAIN AND
PHASE versus FREQUENCY

g

i'--..

5l
o

'"

20

~

~

~ -4.0

100
50
20
fose, OSCILLATOR FREQUENCY IkHzl

60

I
Vcc ~ 10 vRT ~ 25.5k
CT ~ 390 pF-

...........

0

VCC 10
TA = 25°C

FIGURE 4 -

~

c:

-55

200

V=

0

P~)OO~Fr f--

OSCILLATOR FREQUENCY CHANGE
versus TEMPERATURE

'-.

~
=>

~

500 PFr\200

8. 0
4. 0

,/

../

CTll~1~ f- 2io ni\ f-- liOnr

10 K
5.0

~

"'

10K

lOOK
f, FREQUENCY 1Hz)

1

~

1.0M

180
10M

FIGURE 6 - ERROR AMP LARGE-SIGNAL
TRANSIENT RESPONSE

FIGURE 5 - ERROR AMP SMALL-SIGNAL
TRANSIENT RESPONSE

1.05 V

1.5 V

:>

:>

15

:>

1.0V

E

15

:>

1.0V

E

~

:i:l

0.95 V

0.5 V
0.5/LsIDIV

MOTOROLA COMMUNICATIONS DEVICE DATA

1.0/LsIDIV

MC34129.MC33129
2-449

FIGURE 8 -

FIGURE 7 - ERROR AMP OPEN-LOOP DC GAIN
versus LOAD RESISTANCE

90
iii

..

:s
z

",.

/'

so

V

w

'"~

> 70
Do

9

z

~

.::.

w

'"~

« O.S

~
z

/
I

0

0

-

1.0
~

~

!;(

'"

~

60
RL, OUTPUT LOAD RESISTANCE (kfll

I!:
::J

60

w

0

>
z
0

3.2

~

en

~

I::J

'"~

...........
-4.0

~
~

-12

I

a:

100

200
300
ISink' OUTPUT SINK CURRENT (/LAI

~O

o

500

I

........

VCC

"'"
TA

/"

4.0

S.O
VCC, SUPPLY VOLTAGE (VI

-r-...,

'"
<..>

1\
\
\
2.0
4.0
6.0
S.O
Iref, REFERENCE OUTPUT SOURCE CURRENT (mAl

\

~

~

~

...... ~

§
w
<..>

0..
\

\

,
10

1i'
i
a:

'\.

\

~ -S.O

.'\. R:'- ........
........... ~5'C-,- = -40'C\ f--- :-S5'C

12

16

-12

TA =

'""
\
1\

\

-~'C\ f- 25'C\-S5'C\ f - \
\

-16
.

1\

Ita: -20
~-24



I-

~

J

2.4

~
0

a:

0

TA = 25'C
Vref 2.5 V, RL = 2.5 k

~

::J

S.O

REFERENCE OUTPUT VOLTAGE versus
SUPPLY VOLTAGE

~
w

0.6

-..,..-

~

I

/

/

2.0
4.0
6.0
ISink' OUTPUT SINK CURRENT (mAl

FIGURE 10 -

!;( 0.4

5

oV
o

100

PinsSt09
Pins 2, 5,7,10,12 to Gnd
TA = 25'C

O.S

--

0.2

0

J

,

"

w

0.4

I::J

=

FIGURE 9 - SOFT-START BUFFER OUTPUT SATURATION
versus SINK CURRENT
1.0
1
VCC I= 10J

'"~

0.6

0

~

~

/

a:

VCC 10V
Vo = 1.25 V RL to 1.25 Vref_
TA = 25'C

o

I--VCCI= 10V I
f-- Pins Sto 9, 6 to 10
Pins 2, 5, 7 to Gnd
f-- TA = 25'C

::J

60

50

ERROR AMP OUTPUT SATURATION
versus SINK CURRENT

\
0

0.4
O.S
1.2
1.6
Iref' REFERENCE OUTPUT SOURCE CURRENT (mAl

1\
\
2.0

MOTOROLA COMMUNICATIONS DEVICE DATA

FIGURE 13 -

~
w

*Vref = 1.225 V.....

to

~

Z

5 -2.0

/' /

~

~

I

I-

::J

[3

a

/

-6.0

~

-8.0

/

a:

'Vref

=~1.250

/

5

"'" "
"
"-

1

~

§; - 8.0
::J

r=

::J

a

-12

15

100

;;

125

Vee

~

--

Source Saturation
ILO~d to Groindl

~

Sink Saturation
ILoad to Veel

3. 0

I-

::J

~

2. 0

J

1. 0

a

I

I--~

""

~

"" '\.""'\ '\.

Vee = 10V
RL = 2.5 k
'V rlef at TA 250 e

i

/

I
I

'\.

RGURE 16 -

'\.
\.

I

\.
'\

o
25
50
75
TA. AMBIENT TEMPERATURE lOCI

-25

'-....

........

I

I

-55

"'r-...

.........

100

125

DRIVE OUTPUT WAVEFORM

vee llOV TA 25°C -

.......

..........

-

a:

::J

/

/

V

-16

FIGURE 15 - DRIVE OUTPUT SATURATION
versus LOAD CURRENT
0
:;;:; -1. 0 ......
~
~
~ -2. 0
z
a
!;ii -3. 0

/

w

u

~

o
25".50
75
TA. AMBIENT TEMPERATURE lOCI

V

I-

a:
~ -20

-25

/ ...........

f/

~

"

T

I V

4.0

w

1'--

'Vref = 2.500 V _'Vref = 2.625 V
-j-.......

p-::::;: 7 "

V

to

Z

..............

........... ...........

2.5 V REFERENCE OUTPUT VOLTAGE
versus TEMPERATURE

*Vref = 2.375 V....

w

-...... -:-.....

Vee = 10 V
RL = x
'vref atTA 250 e

I

~

V ___ *Vref = 1.275 V

/-

I

II

w
u

15

.....
/

I

§; -4.0

FIGURE 14 -

1.25 V REFERENCE OUTPUT VOLTAGE
versus TEMPERATURE

..-

-

Gnd
0

""

200
400
10. OUTPUT LOAD CURRENT ImAI

600

FIGURE 17 10
,I
f--- RT
eT
:

w

ES

200

100

10

20

30

40

50

Clayout (pF) ON PINS 1-5 (MCI45027); PINS 1-5 AND 12-15 (MC145028)

Figure 12. f max vs Clayout -

MC145026.MC145027.MC145028.SC41343.SC41344
2-470

Decoders Only

MOTOROLA COMMUNICATIONS DEVICE DATA

NO

DISABLEVT
ON THE 1ST
ADDRESS MISMATCH

STORE
THE
4-BIT
DATA

NO

DISABLEVT
ON THE 1ST
DATA MISMATCH

NO

LATCH DATA
ONTO OUTPUT
PINS AND
ACTIVATEVT

YES

DISABLE
VT

Figure 13_ MC145027 Flowchart

MOTOROLA COMMUNICATIONS DEVICE DATA

MC145026.MC145027.MC145028.SC41343.SC41344
2-471

DISABLE VT ON THE 1ST
ADDRESS MISMATCH
AND IGNORE THE REST
OFTHISWORD

DISABLEVT

Figure 14. MC145028 Flowchart

MC145026.MC145027.MC145028.SC41343.SC41344
2-472

MOTOROLA COMMUNICATIONS DEVICE DATA

MC145027 AND MC145028 TIMING

EOW

To verify the MC145027 or MCl4502B timing, check the
waveforms on C1 (Pin 7) and R2IC2 (Pin 10) as compared
to the incoming data waveform on Din (Pin 9).
The R-C decay seen on C1 discharges down to 1/3 VDD
before being reset to VDD. This point of reset (labelled "DOS"
in Figure 15) is the point in time where the decision is made
whether the data seen on Din is a 1 or O. DOS should not be
too close to the Din data edges or intermittent operation may
occur.

DOS

I
I

EOT

Figure 16. R-C Decay on Pin 10 (R2IC2)
The other timing to be checked on the MC145027 and
MC14502B is on R2IC2 (see Figure 16). The R-C decay is
continually reset to VDD as data is being transmitted. Only
between words and after the end-of-transmission (EOT) does
R2IC2 decay significantly from VDD. R2IC2 can be used to
identify the internal end·of-word (EOW) timing edge which is
generated when R2IC2 decays to 213 VDD. The internal EOT
timing edge occurs when R2IC2 decays to 1/3 VDD. When
the waveform is being observed, the R-C decay should go
down between the 2/3 and 1/3 VDD levels, but not too close
to either level before data transmission on Din resumes.
Verification of the timing described above should insure a
good match between thll MC145026 transmitter and the
MC145027 and MC14502B receivers.

Cl
OV -

",,:E~~
Ov=J·

DOS

Figure 15. R-C Decay on Pin 7 (Cl)

VDD

VDD

VDD

VDD

-= 14

5
TRINARY
ADDRESSES

:c O•lIlF
16

O.IIlF

-=

:c

5
Rl

MC145027
OR
SC41343

7

MCI45026

I
4·BIT
BINARY
DATA

16

Din 9

15 Dout

CI

{

10

TRINARY
ADDRESSES
5
15
14
13
12
11

D6
D7
08
D9

-=
VT

R2

-=

1
esc - 2.3 RrcGTc'

f

_

R1Cl

REPEAT OF ABOVE

=3.95 RrcGTc

REPEAT OF ABOVE

R2C2 =77 RrcCrc
Example RIC Values (All Resistors and Capacitors are ±5%)
(Crc' = GTc + 20 pF)
fosc (kHz)

Rrc

Crc'

RS

R1

C1

R2

C2

362
181
88.7
42.6
21.5
8.53
1.71

10k
10k
10k
10k
10 k
10 k
50 k

120pF
240pF
490pF
1020pF
2020pF
5100pF
5100pF

20k
20k
20k
20k
20k
20k
lOOk

10k
10 k
10k
10k
10 k
10 k
50 k

470pF
910pF
2000 pF
3900 pF
8200 pF
0.021lF
0.021lF

100 k
lOOk
lOOk
lOOk
100 k
200k
200k

910pF
1800pF
3900pF
7500pF
0.015 1lF
0.021lF
O.IIlF

Figure 17. Typical Application

MOTOROLA COMMUNICATIONS DEVICE DATA

MC145026.MC145027.MC145028.SC41343.SC41344
2-473

APPLICATIONS INFORMATION
INFRARED TRANSMITTER
In Figure 18, the MC145026 encoder is set to run at an
oscillator frequency of about 4 to 9 kHz. Thus, the time required
for a complete two-word encoding sequence is about 20 to
40 ms. The data output from the encoder gates an RC
oscillator running at 50 kHz; the oscillator shown starts rapidly
enough to be used in this application. When the "send" button
is not depressed, both the MC145026 and oscillator are in a
low-power standby state. The RC oscillator has to be trimmed
for 50 kHz and has some drawbacks for frequency stability.
A superior system uses a ceramic resonator oscillator running
at 400 kHz. This oscillator feeds a divider as shown in Figure
19. The unused inputs of the MC14011 UB must be grounded.
The MLED81 IRED is driven with the 50-kHz square wave
at about 200 to 300 mA to generate the carrier. If desired, two
IREDs wired in series can be used (see Application Note
AN1016 for more information). The bipolar IRED switch,
shown in Figure 18, offers two advantages over a FET. First,
a logic FET has too much gate capacitance for the
MC14011 UB to drive without waveform distortion. Second, the
bipolar drive permits lower supply voltages, which are an
advantage in portable battery-powered applications.
The configuration shown in Figure 18 operates over a supply
range of 4.5 to 18 V. A low-voltage system which operates
down to 2.5 V could be realized if the oscillator section of a
MC74HC4060 is used in place of the MC14011UB. The data
output of the MC145026 is inverted and fed to the RESET pin
of the MC74HC4060. Alternately, the MC74HCU04 could be
used for the oscillator.
Information on the MC14011 UB isin booknumberDL 131/D.
The MC74HCU04 and MC74HC4060 are found in book
number DL 129/D.
INFRARED RECEIVER
The receiver in Figure 20 couples an I R-sensitive diode
to input preamp A 1, followed by band-pass amplifier A2 with
a gain of about 10. Limiting stage A3 follows, with an output
of about 800 mVp-p. The limited 50 kHz burst is detected
by comparator A4 that passes only positive pulses, and·.
peak- detected and filtered by a diode/RC networkto extract
the data envelope from the burst. Comparator A5 boosts

MC145026.MC145027.MC145028.SC41343.SC41344
2-474

the signal to logic levels compatible with the MC 145027/28
data input. The Din pin of these decoders is a standard
CMOS high-impedance input which must not be allowed
to float. Therefore, direct coupling from A5 to the decoder
input is utilized.
Shielding should be used on at least A 1 and A2, with good
ground and high-sensitivity circuit layout techniques applied.
For operation with supplies higher than + 5 V, limiter A4's
positive output swing needs to be limited to 3 to 5 V. This
is accomplished via adding a zener diode in the negative
feedback path, thus avoiding excessive system noise. The
biasing resistor stack should be adjusted such that V3 is 1.25
to 1.5 V.
This system works up to a range of about 10 meters. The
gains of the system may be adjusted to suit the individual
design needs. The 100 n resistor in the emitter of the first
2N5088 and the 1 kn resistor feeding A2 may be altered if
different gain is required. In general, more gain does not
necessarily result in increased range. This is due to noise floor
limitations. The designer should increase transmitter power
and/or increase receiver aperature with fresnal lensing to
greatly improve range. See applications note AN1016 for
additional information.
Information on the MC34074 is in data book DL 128/D.
TRINARY SWITCH MANUFACTURERS
Midland Ross-Electronic Connector Div.
617/491-5400
Greyhill
312/354-1 040
Augat/Alcoswitch
617/685-4371
Aries Electronics
201/996-6841
The above companies may not have the switches in a DIP.
For more info, call them or consult EEM or Gold Book. Ask
for SPOT with center OFF.
Alternative: A SPST can be placed in series between a
SPDT and the Encoder or Decoder to achieve trinary action.
Motorola cannot recommend one supplier over another and
in no way suggests that this is a complete listing of trinary
switch manufacturers.

MOTOROLA COMMUNICATIONS DEVICE DATA

V+

SELECT FOR
200 rnA TO 300 rnA

MlEDBl

USE OF 2 MlEDBl s
IS OPTIONAL

~

MPSA13
OR
MPSW13

SEND

--L

~

MC140l1UB
Dout
MC145026

220kn

ADJUST/SELECT FOR
f=50kHz(APPROX.l00kQ)

Figure 18. IRED Transmitter Using RC Oscillator to Generate Carrier Frequency

MC14024

P - - - - - . - { ClK

Q3

50 kHZ TO
DRIVER
TRANSISTOR

lMQ
Xl = 400 kHz CERAMIC RESONATOR
PANASONIC EFD·A4ooK04B
OR EQUIVALENT

Xl

MCl4011UB

01-----'
470pF

I

470pF

I

Dout
FROM MC145026

Figure 19. Using a Ceramic Resonator to Generate Carrier Frequency

MOTOROLA COMMUNICATIONS DEVICE DATA

MC145026.MC145027.MC145028.SC41343.SC41344
2-475

+5V
10k!:!

r

Al

r

22k!:!

---

lOI1F

-=

lOI1F

-=-

#

1 mH - TOKO TYPE 7PA OR 10PA
OR EQUIVALENT

O.OlI1F

O.OlI1F

~

Vl

2.2k!:!

OPTICAL
FILTER

r

-=-

ll1F

V,

-=-

lN914

-=-

-=-

"~" I

O.OlI1F

4.7k!:!
lN914
1M!:!

lOOk!:!

1M!:!
10k!:!
lN914

1 k!:!

Vl
1/4 MC34074

V2
1/4 MC34074

1000pF

22k!:!

I

V3

47k!:!

1/4 MC34074

-=-

r

390 k!:! FOR APPROX. 4 kHz
180 k!:! FOR APPROX. 9 kHz

1000 pF

+5V
750 k!:! FOR APPROX. 4 kHz
360 k!:! FOR APPROX. 9 kHz

-=

R2IC2

Cl
Din

MC145027128

4.7k!:!

-=-

-=VT

4

V2=2.7V

y~

390!:!

DATA OUT
MC145027 ONLY

2.2k!:!

Vl =2.5V

1r

10 I1FIlO I1F 'l-0I1-F-+---- V3= 1.3 V

+5V

-=-

-=-

-=-

2.7k!:!

-=-

Figure 20. Infrared Receiver

MC145026.MC145027.MC145028.SC41343.SC41344
2-476

MOTOROLA COMMUNICATIONS DEVICE DATA

MOTOROLA

-

SEMICONDUCTOR
TECHNICAL DATA

MC145030
Advance Information

Remote Control Encoder/
Decoder

PSUFFIX
PLASTIC DIP
CASE73B

CMOS
The MC145030 encodes and decodes nine bits of information, which allows
512 different codes.
The encoder section samples the 9-bit parallel address input, encodes the
bits into Manchester Code, and sends the serial information via the ENCout pin.
The address is issued twice per encoding sequence; initialization occurs with
a rising edge on ENC ENS.
The decoder accepts serial Information at the DECin pin, and decodes the
Manchester information. The decoded address is compared with the local
address. If a match occurs, DECout toggles once per sequence. The active-high
DRST input is used to clear DECout.
The Status pin, when high, indicates the device is encoding. During decoding
or standby, Status is low.

OW SUFFIX
SOG
CASE 751D

ORDERING INFORMATION
MC145030P
MC145030DW

• Applications:
Cordless Phones and Half-Duplex Remote Control
• Interfaces with RF, Ultrasonic, or Infrared Modulators and Demodulators
• Operating Temperature Range: - 40 to 85°C
• Operating Voltage Range: 2 to 6 V
• Standby Supply Current: 20 ~A Maximum @ 2.0 V
• Operating Supply Current: 700 ~A Maximum @ 2.5 V
• Address Inputs Have On-Chip Pull-Up Devices
• RC Oscillator, No Crystal Required
• On-Chip Amplifier in Decode Section
• Power-On Reset Forces DECout Low and Initializes the Decoder
and Encoder Sections
• See Application Notes AN1016 and AN1126 and Article Reprint AR:?55
BLOCK DIAGRAM

ENCODE
ENABLE _.:..:10'--t!>
(ENC ENB)
L..----_-r--....l

Plastic DIP
SOG Package

PIN ASSIGMENT
AO

1-

20

OSCin

A8

2

19

OSCoutl

A1

3

18

OSCout2

A2

4

17

VSS

A3

5

16 J ENCout

A4

6

15 J DECout

AS

7

14 ] VDD

A6

8

13 ] DRST

A7

9

12 ] DECin

10

11

ENCENB

~ STATUS

NOT RECOMMENDED
FOR NEW DESIGN
'--_ _ _ _ _---'1'-<1•

STATUS

AO
ENCODER OUT
(ENCouu

A1

A2
A3

A4

ADDRESS
GENERATOR

AS
A6

PIN 14=VDD
PIN 17=VSS

POWER-ON RESET

A7

AS
DECODER IN
(DECin)

ADDRESS
COMPARATOR

TOGGLE 15
FLlP·FLOP

DECODER OUT
(DECouU

DECODER
RESET _!:!...._ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _- - I
(DRST)
This document contains information on a new product. Specifications and Information herein are subject to change without notice.

MOTOROLA COMMUNICATIONS DEVICE DATA

MC145030

2-477

---------_._-----

----

MAXIMUM RATINGS· (Voltages Referenced 10 VSS)
Symbol

Parameter

Unit

-0.5to+7.0

V

Vln

DC Input Voltage

- 0.5 to VDD + 0.5

V

Vout

DC Output Voltage

- 0.5 to VDD + 0.5

V

VDD

DC Supply Voltage

Value

lin

DC Input Current, per Pin

±10

mA
mA

lout

DC Output Current, per Pin

±10

IDD

DC Supply Current, VDD and VSS Pins

±30

mA

PD

Power Dissipation, per Packaget

500

mW

-5510+ 150

°C

260

°C

Tstg
TL

Storage Temperature
Lead Temperature (1 O-Second Soldering)

This device contains protection circuitry
to guard against damage due to high static
voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum
rated voltages to this high-Impedance circuit. For proper operation, Yin and Vout
should be constrained to the range VSS S
(Vin or Vout) S VDD·
Except for the Address Inputs, unused
inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or
VDD)·TheAddresslnputsmaybeleftopen;
see Pin Descriptions. Unused outputs must
be left open.

• MaXimum Ratings are those values beyond which damage to the deVice may occur. Functional operation should be restricted to the limits in the Electrical Characteristics tables
or Pin Description section.
t Power Dissipation Temperature Derating: - 12 mWrC from 65 to B5°C
ELECTRICAL CHARACTERISTICS (TA = 25°C, Voltages Referenced to VSS)
Voo
V

Guaranteed
Limit

Unit

Power Supply Voltage Range

-

2.0 to 6.0

V

VIL

Maximum Low-Level Input Voltage (Except DECin)

2.5
6.0

0.3
1.2

V

VIH

Minimum High-Level Input Voltage (Except DECin)

2.5
6.0

1.9
4.5

V

Vslg

Minimum Output Voltage of Signal Source Driving DECin

Square-Wave Source
See Figure 1

2.5
6.0

200
200

mVp_p

VOL

Maximum Low-Level Output Voltage

lout = 0 vA
lout = 0.4 mA

2.5

0.15
0.4

V

lout = 0 IiA
lout = 1.0mA

6.0

0.15
0.4

lout = 0 IiA
lout = - 0.4 mA

2.5

2.35
2.0

lout = 0 IiA
lout=-1.0 mA

6.0

5.B5
5.5

Yin = VDD orVss

6.0

±60
±0.3

IiA
vA
IiA

Symbol
VDD

VOH

Test Condition

Parameter

Minimum High-Level Output Voltage

V

lin

Maximum Input Current

IIH

Maximum High-Level Input Leakage Current

AO-AB

Vln=VDD

6.0

0.3

IlL

Maximum Low-Level pun-up Current

AO-AB

Vin=VSS

6.0

-100

IOZ

Maximum Three-State Leakage Current

Vout = VOD or VSS

6.0

±500

nA

IDD

Maximum Quiescent Supply Current

Device In Standby Mode
Yin = VSS orVDD for ENC
ENB, DECin, DRST,
OSCin
Yin = VSS, VOD, or Open for
AO-AB
lout = 0 vA

2.0
6.0

20
100

IiA

Idd

Maximum RMS Operating Supply Current

Oscillator Frequency = 500 kHz
Vln= VSsorVDDforENC
ENB, DECln, DRST,
OSCin
Yin = VSS, VDD, or Open for
AO-AB
lout = 0 vA

2.5
6.0

700
2500

vA

MC145030
2-478

DECin
ENC ENB, DRST, OSCin

ENCout

MOTOROLA COMMUNICATIONS DEVICE DATA

AC ELECTRICAL CHARACTERISTICS (TA = 25°C, CL = 50 pF, VDD = 2.5 to 6 V unless otherwise stated)
Symbol
fosc
tpLH,
tpHL

Parameter

Figure
#

VDD
V

Guaranteed
Limit

2

-

500

kHz

384-608

OSCCycles
OSCCycles

Maximum Oscillator Frequency (= 50% Duty Cycle)·
System Propagation Delay, ENC ENB (of an encoding device) to
DECout (of a decoding device)

Id

Debounce Time, ENC ENB (guarantees 1 encoding sequence)

tw

Minimum Input Pulse Width, ENC ENB or DRST

Cin

Maximum Input Capacitance

3,5

4

Unit

-

608

2.5
6.0

200
80

ns .

-

10

pF

·See Pin Descriptions and Application Example for component tolerances.

5kQ
,....--A,/'I/'v----if-1!0.111F

DEVICE
UNDER
TEST

OSCout2

Figure 2. Switching Waveform

Figure 1. Decoder Input Sensitivity Test

t)

ENCENB
_ _ _-,

DR~

Figure 3. Switching Waveforms

50%t

w

-VDD

~_ _ _ VSS

Figure 4. Switching Waveform

TEST POINT
DEVICE
UNDER
TEST

OUTPUT

r

·Includes all probe and fixture capacitance.

Figure 5. Test Circuit

MOTOROLA COMMUNICATIONS DEVICE DATA

MC145030

2-479

PIN DESCRIPTIONS
INPUT PINS
AD-AS
Local Address Inputs (Pins 1, 3-9, 2)
These binary inputs provide the address for both the.
encoder and decoder; 512 addresses are possible. The local
address is sent serially from ENCout with 2 sync bits
appearing first, fOllowed by AO. The decoder compares the
local address with the received· address stream.
On-chip pullup devices are provided on the address inputs
to facilitate interface to SPST switches or jumpers to VSS.
During standby, AD-A8 are in the high-impedance state (i.e.,
the pull-up devices are inactive to minimize standby power
consumption).
The inputs are left open (or tied to VDD) for a high level
and tied to VSS for a low level.
ENCENB
Edge-Sensitive Encode Enable (Pin 10)
A low-to-high transition on this pin aborts any decoding
sequence in progress and initiates an encoding sequence.
This input is debounced 608 oscillator cycles. See Figures
8 and 9.
DECln
Decoder In (Pin 12)
Decoder In is the input to the on-chip amplifier. The
incoming signal is usually capacitively-coupled to this pin.
Direct coupling may be used if the signal level is rail-to-rail
(VSS to VDD)·
DRST
Level-Sensitive Decoder Reset (Pin 13)
When this input is taken high, DECout is cleared to a low
level. This pin may be used to override a response from a
DECin data stream.
OUTPUT PINS
STATUS
Encode/Decode Status (Pin 11)
This pin is high during the encoding sequence and low
during decoding or idle.
When Status is low, the ENCout pin is in the highimpedance state.

...1-0----SYNC
BITS

It I

DECin

DECout
Toggle Flip-Flop Decoder Output (Pin 15)
The encoder sends the same address twice to complete
a sequence. If one or both of the decoded addresses matches
the local address, DECout toggles once per sequence (unless
overri~den by DRST). See Figures 6 and 7.
ENCout
Three-State Encoder Output (Pin 16) .
This is the serial output of the Manchester-encoded local
address. AO appears before A8 in the bit stream. The local
address is sent twice to complete a sequence which is
initialized by ENC ENB. When a sequence is complete,
ENCo!!t returns to the high-impedance state. See Figures 8
and 9.
OSCILLATOR PINS
OSCln, OSCout1, OSCout2
Oscillator Input, Oscillator Outputs 112 (Pins 20,19,18)
As shown in Figure 10, these pins are used in conjunction
with external resistors and a capacitor to form an oscillator.
Polystyrene or mylar capacitors are recommended. Susceptibility to extemally induced noise Signals may occur if
resistors utilized are greater than 1 MQ. See Figure 10 for
component tolerances.
When the on-chip oscillator is used, the frequency may be
up to 500 kHz. The oscillator is active only during encoding
or decoding.
When an external frequency source is used to drive OSCin,
OSCou t1 and OSC out2 may be left floating. The signal applied
to OSCin should swing rail-to-rail and may be de to 500 kHz.
POWER SUPPLY PINS
VSS
Negative Power Supply (Pin 17)
This pin is the negative supply potential and is usually
ground.
VDD
Positive Power Supply (Pin 14)
This pin is the positive supply potential and may range from
+ 2 to + 6 V with respect to VSS.

I

COMPLETE DECODING SEQUENCE-----<·...

INITIAL
ADDRESS

TRAILING SYNC
BIT
BITS

It I I + I

REPEATED
ADDRESS

TRAILING
BIT

11f==~==~ nf==~~==tt
I I

*
------------~--------~~~-----------~I

DECout

I +I

!
I

INITIAl ADDRESS = MATCH,
REPEATED ADDRESS = DON'T CARE
INITiAl ADDRESS = UNMATCH,
REPEATED ADDRESS = MATCH
BOTH ADDRESSES UNMATCHED

Figure 6. Decoder Timing Diagram

MC145030
2-480

MOTOROLA COMMUNICATIONS DEVICE DATA

DO NOT START
OSCILLATOR

NO

START

OSCILLATOR

INITIALIZE
DECODER

NO

NO

NO

NO

Conditions:
Encode Enable = Low, High, or .j.
Decoder Reset Low

=

Figure 7. Decoder Flowchart

MOTOROLA COMMUNICATIONS DEVICE DATA

MC145030
2-481

NO

NO

DISABLE DECODER, SET STATUS PIN HIGH,
ENCODER OUT PIN: HIGH Z ~ LOW LEVEL,
START OSCILLATOR, IGNORE ENCODE ENABLE INPUT

SAMPLE ADDRESS
INPUTS,
ISSUE ENCODED
ADDRESS

RE·ISSUE
ENCODED
ADDRESS

STOP OSCILLATOR, RESET STATUS PIN LOW,
ENCODER OUT PIN: LOW LEVEL ~ HIGH Z,
DECODER READY, ENCODER READY

Figure 8. Encoder Flowchart

MC145030

2·482

MOTOROLA COMMUNICATIONS DEVICE DATA

~

@
:D

o
s::
o
o
~
~

c

z

o
~

6z

en

o
<

m

ENCENBI

o

m

I.

~

1

o

>

!!
co
c

iil
!D
m

=

n

o

~

=!
3
:j"
co

~

1

I

(
ENCout

......

I
I

I.
1

:!:

1\)"'"
,(II
","0
W

0)

WO

1

2ndl

1

1st 1
AOi
1st 1 2nd 1 AO 1 A1 1 A2 1 A3 I A4 1 A5 I AS 1 A7 I AS I
1 12·BIT
ISYNCISYNCI LOWI LOWI HIGH 1HIGH IHIGH 1LOWIHIGHI LOW 1 LOW I ! ] ISYNCISYNCILOW 1LOW 1HIGHIHIGHIHIGH 1LOWIHIGH 1 LOW 1LOW 1~I
FRAME
1
1...... 1 1 1 1 1 1 1 1 1
IBITIBITI
I)
1.1
111111
DELAY I BIT 1 BIT)
/............
TRAILING BIT
//',
TRAILING BIT
HIGH
//
..................
/ / ' ,
IMPEDANCE
/
............
2·BIT
//
',1.5.BIT
/
............
FRAME
/
,
FRAME
//
............
PAUSE
//
"
PAUSE
(/
ENCout 1

1

OSC oul2 t

o
....

• I
ENPODEDADDRESS (REPEAT1ED),------I

ENCout~~

c

iii·
co

COMPLETE ENCODING SEQUENCE

BITFRAME
(ENCODED LOW LEVEL)

'...,
1

1

HIGH IMPEDANCE

C

Rl

20
OSCin

C

Rl

R2
19
18
OSCoull OSCou12

20
OSCin
12
16
15
11

R2
19
18
OSCout1 OSCou12
AO
Al

DECin
0

ENCout
DECoul

8
:g
13
:::;

A2
A3
A4

A5
A6

STATUS

+V

A7
A8

-=
17

10

-=

-=
12

EXAMPLE RIC VALUES
fOSC
(APPROX.)

R1

R2

C

ENCODE ENABLE
SWITCH DEBOUNCE
TIME (APPROX.)

452 kHz
220 kHz
70 kHz
4.1 kHz

30kQ
47kQ
47kQ
330kQ

5.6kQ
10kQ
10kQ
47kQ

100 pF
100 pF
510pF
2200 pF

1.3ms
2.8ms
8.7ms
148ms

16

REPEAT
OF
ABOVE

I

I

12
16

GUIDELINES: 100pF"C,,0.1 ~F
2 (R2) < Rl < 10 (R2)
10kQ"R2,,500kQ
Rl"l MQ

REPEAT
OF
ABOVE

The maximum oscillator frequency difference allowable from encoding IC to decoding IC is ± 11 %. The ambient temperature and
supply voltage differences between ICs affect this frequency difference. Therefore, the tolerances of the frequency-determining
components R2 and C are determined by the rule of thumb:
[t.R2 + t.C +t.fIC+t.ftemp+t.fsupl ,,± 11%,

where

R2 = tolerance of R2 in percent
C = tolerance of C in percent
flC = IC frequency variation from part to part (expected value: ± 4%)
ftemp = IC frequency variation over temperature (expected value: ± 2% @ 25°C ± 40°)
fsup IC frequency variation with supply (expected value: ± 2% @ 5 V ± 0.5 V)
For the above variances: [t.R2 + t.C + (±4%) + (± 2%) + (±2%)],,± 11%
[t.R2 + t.CI " ± 3%
Choose R2 with a ± 1% tolerance and C2 with a ± 2% tolerance. R1 may be ± 5%.

=

Figure 10. Application Example

MC145030
2·484

MOTOROLA COMMUNICATIONS DEVICE DATA

MOTOROLA

_ SEMICONDUCTOR
TECHNICAL DATA

MC145031
MC145032
MC145033
MC145034
MC145035

Advance Information

Encoders and Decoders
CMOS
For remote control devices, the MC145031/34 function as encoders and the
MC145032135 function as decoders. The MC145033 functions as both an encoder
and a decoder.
The encoders convert parallel address and data inputs into the Manchester code
format and output the information serially via the DO-D3 pins.
The decoders revert the serial Manchester-coded input back into binary and
compare the incoming address with local one. If both addresses match, a valid
data output (VD) signal is asserted and the proper data appears at the Dout pin.
The difference between the MC145031/2 and MC145034/5 is the VD output
pin. The VD output of the MC145031/2 is a toggle function while the MC145034/5
is a ·one shot" valid address output pulse if a correct data sequence and matched
address are received.
The MC145033 encoder/decoder has a status output. The status pin, when high,
indicates the device is encoding. During decoding or standby, status is low.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•

Typical Applications: Remote Control, Security Systems, and Keyless Entry
Manchester Coding
RC Oscillator, No Crystal Required
Binary Address and Data Inputs
Two-Word Transmit Sequence
Built-In Input Data Amplifier
Schmitt-Trigger Serial Input for Excellent Noise Immunity
Code Break Output with Adjustable Error Code Transmission TIme Window
Operating Voltage Range: 2 to 6 V
Operating Temperature Range: -40 to +85°C
MC145031 Encoder/MC145032 Decoder Pair: 13 Address and
4 Data Lines or 17 Address Lines
MC145033 Encoder/Decoder: 15 Address Lines
MC145034 Encoder/MC145035 Decoder Pair: 13 Address and
4 Data Lines or 17 Address Lines
Address/Data Inputs have On-Chip Pull-Up Devices
See Application Note AN1126

OW SUFFIX
28

SOG
CASE 751F

ORDERING INFORMATION
MCl45031DW
MC145032DW
MC145033DW
MC145034DW
MCl45035DW

SOG Package
SOG Package
SOG Package
SOG Package
SOG Package

OT RECOMMENDED
FOR NEW DESIGN

This document contains infonnatlon on a new product. Specifications and information herein are subiect to change without notice.

MOTOROLA COMMUNICATIONS DEVICE DATA

MC145031.MC145032.MC145033.MC145034.MC145035
2-485

BLOCK DIAGRAM OF MC145031132133134135

OSC·R1
I

OSC-R2
I

OSCILL:ATOR
WITH ENABLE
AND DIVIDER

I

J

TxEN
(MC145031133134 ONLY)

ADDRESS/DATA

I

I
I
I

OSC-C
I

I--

STATUS
(MC145033 ONLy)

!

L-.

-

ENCODER CONTROL

MANCHESTER
ENCODER

-

POWER
ON
RESET

GENERATOR

-.---'--

r----

--

MODE
(MC145032135 ONLY)
RxD
(MC145032133135 ONLY)

AMP

Dout
(MC145031/33134 ONLy)

-

.--ADDRESS/DATA

f----

COMPARATOR
/WINDOW
GENERATOR

-.---

MANCHESTER
DECODER

RESET
(MC145032133135 ONLY)
CE
(MC145032I33I35 ONLY)

-

"--

PIN 28 = VDD
PIN 27=VSS

MONOSTABLE
OSC.

~

MC145031.MC145032.MC145033.MC145034.MC145035
2-486

FLIP
FLOP

r-o

--

DATA
OUTPUT

-

-

VD
(MC145032133135 ONLY)

-

DATA
00-03
(MC145032135 ONLy)

CB

(MC145032133135 ONLY)

MOTOROLA COMMUNICATIONS DEVICE DATA

PIN ASSIGNMENTS

MC145033 ENCODERIDECODER

MC145031 ENCODER

MC145032 DECODER

AO

VDD

AO

VDD

AO

VDD

AI

VSS

AI

VSS

AI

VSS

A2

OSC-R2

A2

OSC-R2

OSC-C
A4

OSC-R2

OSC-C

OSC-Rl

A3

NC

VD

NC

CB

OSC-C
OSC-Rl

OSC-Rl

A4

A5

VD

CB

NC

RxD

NC

RESET

A8

MODE

A9

RxD
RESET

A9

Doul

A9

Al0

TxEN

Al0

All

A16/D3

All

AI61D3

All

CE

A12

A15/D2

A12

A15/D2

A12

STATUS

A13/DO

A14/Dl

A13/DO

A14/Dl

A13

A14

CE

Doul
TxEN

MC145035 DECODER

MC145034 ENCODER
AO [ 1 •

28

VDD

AO

AI [ 2

27

VSS

AI

A2 [ 3

26

OSC-R2

A3 [ 4

25

OSC-C

A3

A4 [ 5

24

OSC-Rl

A4

OSC-Rl

A5 [ 6

23

NC

A5

VD

A6 [ 7

22

NC

A7 [ 8

21

NC

A8 [ 9

20

NC

VDD
VSS
OSC-R2
OSC-C

CB
A7

RxD
RESET

A9 [ 10

19

Doul

A9

Al0 [ 11

18

TxEN

Al0

CE

All [ 12

17

A16/D3

All

A16/D3

A12 [ 13

16

A15/D2

A12

A15/D2

A13/DO [ 14

15

A14/Dl

A13/DO

A14/Dl

MODE

NC = No Connection

MOTOROLA COMMUNICATIONS DEVICE DATA

MC145031.MC145032.MC145033.MC145034.MC145035
2-487

MAXIMUM RATINGS· (Voltages Referenced to VSS)
Symbol

Parameter

Unit

-0.5 to +0.7

V

Yin

DC Input Voltage

-0.5 to VDD +0.5

V

Vout

DC Output Voltage

-0.5 to VDD + 0.5

V

VDD

DC Supply Voltage

Value

lin

DC Input Current, per Pin

±10

mA
mA

lout

DC Output Current, per Pin

±10

100

DC Supply Current, VDD and VSS Pins

±30

rnA

Po

Power Dissipation, per Packaget

500

mW

-65 to +150

°C

260

°C

Istg

Storage Temperature

TL

Lead Temperature (10-second soldering)

This device contains protection circuitry to
guard against damage due to high static voltages or electric fields. However, precautions
must be taken to avoid application of any voltage higher than maximum rated voltages to
this high Impedance circuit. For proper operation, Yin and Vout should be constrained to the
range VSS s: (Vln or Vout) s: VDD.
Except for the Address inputs, unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). The
Address inputs may be left open, see Pin Descriptions. Unused outputs must be left open.

• Maximum Ratings are those values beyond which damage to the device may occur.
t Power Dissipation Temperature Derating: -12 mW/"C from 65°C to 85°C
ELECTRICAL CHARACTERISTICS (TA = -40 to + 85°C, CL = 50 pF, VDD = 2.5 to 6 V unless otherwise stated)
Symbol
VDD

Test Condition

Parameter
Power Supply Voltage Range

VDD
V

Guaranteed
limit

Unit

-

2.0 to 6.0

V

VIL

Maximum Low-Level Input Voltage

Except RxD

2.5
6.0

0.3
1.2

V

VIH

Minimum High-Level Input Voltage

Except RxD

2.5
6.0

1.9
4.5

V

VOL

Maximum Low-Level Output Voltage

10ut=0 I1A
lout=0.4mA

2.5

0.15
0.4

V

lout = 0 I1A
lout = 1,0 mA

6.0

0.15
0.4

lout = 0 I1A
lout = -0.4 mA

2.5

2.35
2.0

lout = 0 I1A
lout=-1.0 mA

6.0

5.85
5.5

6.0

±80
±0.3

I1A

VOH

Minimum High-Level Output Voltage

RxD Yin = VDD or VSS
TxEN, RESET, OSC-R2

V

lin

Maximum Input Current

IIH

Maximum High-Level Input Leakage Current

AD-AI6 Vin=VDD

6.0

0.3

I1A

IlL

Maximum Low-Level Pull-Up Current

AD-AI6 Vin=VSS

6.0

-100

I1A

IOZ

Maximum Three-State Leakage Current

6.0

±500

nA

100

Maximum Quiescent Supply Current (per Package)

Device in Standby mode,
Yin = VDD or VSS for TxEN,
Decoder in, RESET,
OSC-R2.
Yin = VSS, VDD, or open for
AD-AI6.
lout = 0 I1A

2.5
6.0

25
100

I1A

Idd

Maximum RMS Operating Supply Current (per Package)

Oscillator Frequency
=500 kHz.
Yin = VSS orVDD for TxEN,
RESET, OSC-R2.
Yin = VSS, VDD, or open for
AD-AI 6.
10ut=0 I1A

2.5
6.0

700
2500

I1A

IOL

Code Break Sink Current

5

mA

Yin

Minimum RxD Input Level For Decoder

200

mVp-p

Dout Vout = VDD or VSS

CB

MC145031.MC145032.MC145033.MC145034.MC145035
2-488

Square wave, see Figure 1

6.0

MOTOROLA COMMUNICATIONS DEVICE DATA

-

.

AC ELECTRICAL CHARACTERISTICS (TA 25°C CL - 50 pI': VOO - 25 to 6 V unless otherwise stated)

Vee

Symbol
fOSC

Figure #

Parameter
Maximum Oscillator Frequency (50% Duty Cycle)
Debounce TIme, TxEN (guarantees 1 encoding sequence)

tw

Minimum Input Pulse Width, TxEN or RESET

Cin

Maximum Input Capacitance

Vsig

DEVICE
UNDER
TEST

21

~II'F
Y

Guaranteed
Limit

2

Id

SkU

V

3

2.5
6.0

Unit

500

kHz

500

OSC
cycles

200
80

ns

10

pF

-

o~, ~""SC ---Jlr----_-:~
__

Figure 1. Decoder In Sensitivity Test

Figure 2. Switching Waveform

. .----:::

R::~ ----t,~

Figure 3. Switching Waveform

GENERAL DESCRIPTION
ENCODER
The encoder circuit encodes the parallel binary input
address!data into Manchester code and outputs the information serially.
Each transmitted word is preceded by a two-bit dead time
interval. Once the TxEN (transmit enable) pin is triggered by
a high level, a two-word transmit sequence following a 12-bit
preamble is serially output at the Dout terminal. The transmit
sequences repeat continuously if TxEN remains high. The
minimum is one complete sequence; if TxEN goes low, the
transmission continues until the end of the current transmit
sequence.
The data rate is set at one eighth of the system clock, which
is an RC oscillator.
One transmission cycle comprises:
1.
2.
3.
4.
5.
One

12·bit preamble
2-bit dead time interval
First word
2-bit dead time interval
Second word
transmitted word consists of:

1. 2 star! bits
2. The address/data bits
3. 2 stop bits

MOTOROLA COMMUNICATIONS DEVICE DATA

DECODER
The decoder circuit accepts a serial Manchester-coded
input at the RxD pin. The data stream is then decoded and
compared with the local address set by the parallel address
inputs. When a correct .transmit sequence (two identical
words) is received and the incoming address matches the
local one, the valid data (VD) output on the MC145035 goes
high and the decoded data may then be read at the Data
outputs (Do-D3) if the Mode pin is high (see the Mode pin
description). VD remains high unless an erroneous address!
data is detected or the transmit sequence is terminated.
Forthe MC145032and MC145033, the VD output isa toggle
function. That is, VD changes state once each time a valid
sequence of bits is received. If needed, VD can be reset to
a low level via the Reset pin.
If the decoder detects an error in the incoming transmit
sequence, a time window is opened at the end of that
sequence. If two consecutive erroneous transmit sequences
are received within that window, the code break (CB) output
goes low until the window's duration is over. During the opened
window, the CB output can be reset by either the reset input
or a correct transmit sequence that follows. The window
duration is controlled by an external capacitor connected to
pin CEo The duration of the CB output is equal to TB, which
is half of error window time constant TE.

MC145031.MC145032.MC145033.MC145034.MC145035
2-489

PIN DESCRIPTIONS
VDD
Power Supply (Pin 28)
Power supply. This pin may range from +2 to +6 V with
respect to VSS.
VSS
Ground (Pin 27)
Power supply ground.
TxEN
Transmit Enable {Pin 18)-MC145031133134 Only
A low-to-high transition on the Transmit Enable pin initiates
a transmit sequence. Transmission is continuous if TxEN remains high.
Dout
Data Out {Pin 19)-MC145031133134 Only
Three-state encoder output. It serially outputs the Manchester-coded transmit data, when initiated by TxEN.
VD
Valid Address Output (Pin 23)
MC145032133 Only: This "toggle" output changes state
whenever a correct transmit sequence is received and the
address matches the local one (see Figure 4). A high level
on VO can be cleared by either a correct transmit sequence
that follows or the RESET input.
VALID
RECEIVED
SEQUENCES

CB
Code Break {Pin 22)-MC145032133135 Only
Decoder code-break open-drain output. CB goes low if two
additional consecutive erroneous transmit sequences following the 1st error have been received within the window set
by extemal capacitor CEo While in an active state, it can be
cleared by the RESET input.
An external PNP transistor may be utilized to charge up the
CE (timing capacitor) to disable the low frequency oscillator..
As a result, the TB counter stops. In this case, the CB output
remains activated until a "resef signal is applied to reset the
CE flip-flop (see Figures 6 and 7).

r------------,

I
I
I
I VD
I
~--+I----~
I
I
I
I
I
IL _ _ _ _ _ _ _ _ _ _ _ _ J

R

RESET

Figure 6. One Shot VD Output Circuit (MC145035)

VDOUTPUT ~
(TOGGLE)

,---------,I
+V

Figure 4. Valid Address Output Timing
(MC145032 and MC145033)

1.0kO

MC145035 Only: VO goes high if, and only if, a correct
transmit sequence is received and the address matches the
local one. The VO output remains high unless an erroneous
address/data is detected or the transmit sequence is
terminated. The minimum duration of VO is guaranteed by an
external RC. See Figures 5 and 7.
VALID
RECEIVED
SEQUENCES

VDOUTPUT
(ONE SHOT)

--I I-- ADJUSTED
PULSE WIDTH

1000

VIAEXT.RC

Figure 5. Valid Address Output Timing (MC145035)

RESET
Reset (Pin 20)
MC145032133 Only: A positive pulse on this pin resets the
CB output and VO output.
MC145035 Only: A positive pulse on this pin resets the CB
output and the VO output. Its resets VO only when there is
no RxD received (see Figure 7).

MC145031.MC145032.MC145033.MC145034.MC145035
2-490

FROM
CODE
BREAK
I DETECTOR

I
TB
I
I
-_ _ _ _ _,.--+
________
IL _ _ _ _ _ _ _L

RESET

~

Figure 7. Code Break Window Control

MOTOROLA COMMUNICATIONS DEVICE DATA

Gil

r-1

D

1:

0

C RQ

RESET

LOWFREO.
OSCILLATOR
ERROR CODE _ _ _ _ _ _ _ _---,
DETECTED
I st ERROR CODE
DETECTED
SCHMITI
TRIGGER

ERROR WINDOW
TE

Figure 8. Error Window TE and Code Break Window Generator TB

Ao-A12 and Al31Do-Al61D3
Address Inputs (Pins 1-17)
MC145031131134/35 Only: Bidirectional address/data pins.
These pins forma binary input port during encoding. The pins
become a three-state data output during decoding if the Mode
pin is tied to VDD.
MC145033 Only: Binary address inputs. These pins form a
binary input port during the encoding sequence. These inputs
become the local address during the decoding sequence.

OSC-R2, OSC-Rl, OSC-C
Oscillator (Pins 26, 24, and 25)
The oscillator frequency is determined by the external RC
network (see Figure 10). There is only a 4% change in system
oscillating frequency as the supply voltage varies from 2 to
6V.
The encoder system OSCillating frequency can be varied
±10% with reference to decoder system oscillator frequency
for valid detection.

STATUS
Encode/Decode Status (Pin 16)
MC145033 Only. This pin is high during the encoding
sequence and low during decoding or idle. When Status is
low, the Dout pin is in a high-impedance state.

r

RxD
Serial Data Input (Pin 21)
MC145032133135 Only. Serial data input to the Manchester
decoder. Minimum encoded data signal level is 200 mVp-p
(see Figure 9).

I
I
I
I
IL. _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

r--------------,I

I
I
I

I
I
INPUT -.lL --'.....1-1
MANCHESTER
I
DATA - , , DECODER
I
EXTERNAL
DATA
SCHMITI
I
AC
AMPLIFIER TRIGGER
I
COUPLING IL. _ _ _ _ _ _ _ _ _ _ _ _ _ _ .JI
RxD

Figure 9. RxD Pin Coupling

MOTOROLA COMMUNICATIONS DEVICE DATA

R2

RI
C

O~C~2_ _ _ _ _ _ .QS.2:q".______

~SC-RI

I
I
I
I
I

~

I = 0.38 (Hz)
RIC

lorIs 150 kHz where R2=2RI
The system oscillating frequency is eight times the encoded data rate.

Figure 10. RC Oscillator
MODE
Mode Select Input (Pin 19)
MC145032135 Only. This pin defines the A13/DG-A16/D3
lines to be address or data lines. It is intemally pulled high.
L=Address Lines
H=Dala Lines

MC145031.MC145032.MC145033.MC145034.MC145035
2-491

TWO ERROR WORDS AX

signaling that an outsider is trying to break the code of this
system (noise cannot activate the code break output).
If only one error code is detected within the window, the
window period is automatically extended from the last invalid
word to check if there are two or more error codes. If so, the
CB signal is activated; if not, TE is closed after a defined
period. See Figures 8 and 11.
TE and TB are generated from a Schmitt-trigger low
frequency oscillator of which the period (TC) is controlled by
CEo The period of this low frequency oscillator is defined as
TC as indicated in Figure 8.
TE is generated by an a-stage counter.
TB is generated by a 7-stage counter.
TE = 256 TC and TB = 128 Te.
The relation between TC and CE is listed below with a 5.0-V
supply.

INVALID
WORDRx

--1

ERROR WINDOW
EXTEND
TE

r-.-- ---: 1

~

I-

256Tc--j

Figure 11. Error Window and CB Output Timing

CE
External Capacitor
(Pin 18-MC145032135; Pin 17-MC145033)
Error window duration control input. The built-in Schmitt
trigger oscillator frequency is controlled by external capacitor
CEo The error window (TE) is equal to 256 times the internal
oscillator cycle.
.
If an unmatched data word (error code) is detected, an
internal window TE is generated. If two or more errors are
detected within the TE period, the CB signal is activated,

n

ENCODER
~EN~

ENCODER
Dout

I~

DECODER
RxD

DECODER
VDOUTPUT

,- - -

In order to minimize false CB triggers, one error code is
allowed for every TE period (256 TC).
Suppose CE 4.7IlF, TC 1430 ms, and TE 256 TC.
On an average, it takes 210 trials in order to succeed in
breaking the system coding. Total time taken in breaking the
system coding # of trials x TC x 256.

=

,
,

ONE TRANSMIT SEQUENCE-:

=

=

=

____________________________________

: PREAMBLE

,,

Cycle Time (TC)
1430ms
330ms
26ms
12ms
5.6ms
2.5ms
1.0ms
0.3ms

Timing Capacitor (CE)
4.71lF
1.01lF
O.lIlF
0.047 1lF
0.0221lF
O.OlIlF
0.00471lF
O.OOlIlF

n

~;

~.

__________________________

,
: - ONE TRANSMIT SEQUENCE-:

L

------~----------~

t: RECEIVING DELAY

Figure 12. MCl45031/32133 Encoding and Decoding Timing Diagram

MC145D31.MC145D32.MC145D33.MC145D34.MC145D35
2-492

MOTOROLA COMMUNICATIONS DEVICE DATA

ENCODER
TxEN
ENCODER
Doul
PREAMBLE
,
;..:..~------.. ,:

,

ONE TRANSMIT SEQUENCE

DECODER
RxD
PREAMBLE
DECODER
VDOUTPUT
(CASE 1)

L

,

,

,-+- T=Tl -

DECODER
VDOUTPUT
(CASE 2)

------------~~~:---,~

T 

f; 0z

!f?

2

20 19
18

OSCin

•

~

P1

OSCo'ut

17

P2

+2out

16

P3

FS

15

P4

Oefout

P5

Cl
-'

10

11

14
12 13

CX)

0
Z

0..

0..

.....

<0

0..

SOGPACKAGE
VOO

VSS

fin

PO

OSCin

NC

OSCout

P1

+20ut

P2

FS

P3

cjlOefout

P4

LO

NC

P8

P5

P7

P6

NC = NO CONNECTION

MAXIMUM RATINGS (Voltages Referenced to VSS)
Parameter
DC Supply Voltage
Input Voltage, All Inputs
DC Input Current, per Pin
Operating Temperature Range
Storage Temperature Range

MC145106
2-496

Symbol

Value

Unit

VDD

-0.5 to + 12

V

Yin

- 0.5 to VDD + 0.5

V

I

±10

rnA

TA

-40to+85

°C

Tstg

-6510+150

°C

This device contains circuitry to protect
the inputs against damage due to high static voltages or electric fields; however, it is
advised that normal precautions be taken
to avoid application of any voltage higher
than maximum rated voliages to this high
impedance circuit. For proper operation it is
recommended that Yin and Vout be constrained to the range VSS S (Vin or Voutl S
VDD·

MOTOROLA COMMUNICATIONS DEVICE DATA

ELECTRICAL CHARACTERISTICS (TA = 25'C Unless Otherwise Stated, Voltages Referenced to VSS)
All Types

Symbol

Voo
Vdc

Min

Typ'

Max

Power Supply Voltage Range

VOO

-

4.5

-

12

V

Supply Current

IDD

5.0
10
12

-

-

10
35
50

rnA

-

6
20
28

-

1.5
3.0
3.6

V

-

-

Characteristic

Input Voltage

Input Current
FS, Pull-Up Resistor Source Current)

"0" Level

VIL

5.0
10
12

-

"1" Level

VIH

5.0
10
12

3.5
7.0
8.4

lin

5.0
10
12

-5.0
-15
-20

-20
-60
-80

-50
-150
-200

5.0
10
12

-

-

-0.3
-0.3
-0.3

-

-

0.3
0.3
0.3

"0" Level

(PO-P8)

(FS)

"1" Level

(PO-P8, Pull-Down Resistor Sink Current)

-

-

5.0
10
12

-

5.0
10
12

7.5
22.5
30

30
90
120

75
225
300

-

(OSCin, fin)

"0" Level

5.0
10
12

-2.0
-6.0
-9.0

-6.0
-25
-37

-15
-62
-92

(OSCin, fin)

"1" Level

5.0
10
12

2.0
6.0
9.0

6.0
25
37

15
62
92

5.0
10
12

-0.7
-1.1
-1.5

-1.4
-2.2
-3.0

-

5.0
10
12

0.9
1.4
2.0

1.8
2.8
4.0

-

-

1.0
1.5

0.2
0.3

-

5.0
10
12

-

1.0
0.5

Output Drive Current
(VO=4.5V)
(Va = 9.5 V)
(Va = 11.5V)

(VO=0.5V)
(VO=0.5V)
(Va = 0.5 V)

Sink

J.lA

rnA

IOH
Source

Unit

IOL

Input Amplitude
(fin @ 4.0 MHz)
(OSCin @ 10.24 MHz)

-

Input Resistance
(OSCin, fin)

Rin

-

-

Input Capacitance
(OSCin, fin)

Cin

-

-

6.0

-

pF

Three-State Leakage Current
($Delout)

IOZ

5.0
10
12

-

-

-

-

J.lA

-

1.0
1.0
1.0

Input Frequency
(- 40 to + 85'C)

fin

4.5
12

0
0

-

4.0
4.0

MHz

OSCin

4.5
12

0.1
0.1

-

10.24
10.24

MHz

Oscillator Frequency
(- 40 to + 85'C)

...

Vp-p
Sine
MQ

'Data labelled ''Typ IS not to be used for design purposes but IS Intended as an Indication of the IC's potential performance.

MOTOROLA COMMUNICATIONS DEVICE DATA

MC145106
2-497

TYPICAL CHARACTERISTICS·
25

25

~
~

20

0..
0..

~

Detout
Signal for control of external VCO, output high when finiN
is less than the reference frequency; output low when finiN
is greater than the reference frequency. Reference frequency
is the divided down oscillator - input frequency typically 5.0
or 10 kHz.
FS
Reference Oscillator Frequency Division Select
When using 10.24 MHz OSC frequency, this control selects
10 kHz, a "0" selects 5.0 kHz.
+2out
Reference OSC frequency divided by 2 output; when using
10.24 MHz OSC frequency, this output is 5.12 MHz for
frequency tripling applications.
VDD
Positive Power Supply
VSS
Ground

NOTE
Phase Detector Gain = VDot41t

MOTOROLA COMMUNICATIONS DEVICE DATA

(receive) frequencies are provided to mixer #1. When these
signals are provided with crystal oscillators, the result is a three
crystal 360 channel, 50 kHz step synthesizer. When using the
offset loop (bottom) in Figure 5 to provide the indicated
injection frequencies for mixer #1 (two for transmit and two
for receive) 360 additional channels are possible. This results
in a 720 channel, 25 kHz step synthesizer which requires only
two crystals and provides AfT offset capability. The receive
offset value is determined by the 11.31 MHz crystal frequency
and is 10.7 MHz for the example.
The VHF marine synthesizer in Figure 4 depicts a single
. loop approach for FM transceivers. The veo operates on
frequency during transmit and is offset downward during
receive. The offset corresponds to the receive IF (10.7 MHz)
for channels having identical receive/transmit frequencies
(simplex), and is (10.7 -4.6 = 6.1) MHz for duplex channels.
Carrier modulation is introduced in the loop during transmit.

PLL SYNTHESIZER APPLICATIONS
The MC1451 06 is well suited for applications in CB radios
because of the channelized frequency requirements. A typical
40 channel CB transceiver synthesizer, using a single crystal
reference, is shown in Figure 3 for receiver IF values of
10.695 MHz and 455 kHz.
In addition to applications in CB radios, the MC145106 can
be used as a synthesizer for several other systems. Various
frequency spectrums can be achieved through the use of
proper offset, prescaling, and loop programming techniques.
In general, 300-400 channels can be synthesized using a
single loop, with many additional c;hannels available when
multiple loop approaches are employed. Figures 4 and 5 are
examples of some possibilities.
In the aircraft synthesizer of Figure 5, the VHF loop (top)
will provide a 50 kHz, 360 channel system with 10.7 MHz AfT
offset when only the 11.0500 MHz (transmit) and 12.1200 MHz

~
osc

MHz

-=

LLh"

C§ 9

.-HD:
I 10.2~ ~~
-= r-

H

MCI45106
PROGRAMMABLE
DIVIDER

LD

I

PHASE
5.0-P- DETECTOR

I-

LOOP
FILTER

26.965 - 27.405 MHz

I-

VCO

I-

BUFFER

(TRANSMIT)
f-P"-'i6.510
- 26.950 MHz
(RECEIVE)

I I

VDD
SWITCH WAFERS

GND

I

RfT
MIXER

BUFFER

1.365-1.805 MHz (TRANSMIT)
10.91-1.35 MHz (RECEIVE)

'--

X5

25.6 MHz

10.24 MHz
TO RECEIVER
2ND MIXER

ll6270 -16.710 MHz

RECEIVER 1st
LOCAL OSC SIGNAL

MIXER

Figure 3. Single Crystat CB Synthesizer Featuring On-Frequency VCO During Transmit

MOTOROLA COMMUNICATIONS DEVICE DATA

MC145106
2-499

o

TRANSMIT RANGE
156.025-157.425 MHz
'157.4

VCOAND
BUFFER

PROGRAMMABLE INPUTS
N= 97TO 153 '152

RECEIVER L.O. RANGE
145.575 -152.575 MHz
'151.3

MODULATION

NOTES:
o Receiver IF =10.7 MHz
o Low Side Injection
o Duplex Offset =4.6 MHz
o Step Size = 25 kHz
o Frequencies in MHz unless noted.
o Values in parentheses are for a 5.0 kHz reference frequency.
o Example frequencies for Channel 28 shown by ,
#Can be eliminated by adding 184 to + N for Duplex Channels.

SIMPLEX~
14.29
(28.58)

1..DUPLEX

D D

14.75#
(29.50)

Figure 4. VHF Marine Transceiver SyntheSizer

MC145106
2-500

MOTOROLA COMMUNICATIONS DEVICE DATA

LOCK DETECT

TRANSMIT
118.000 -135.975 MHz
(25 kHz STEPS)

VHF LOOP
PROGRAMMING
750 kHz - 2545 kHz
N=150-509

VDD

LOOP
FILTER

VCOAND
BUFFER

MIXER
#1

+10

RECEIVE
128.700 -146.675 MHz

GND

{

TRANSMIT
11.0500 MHz
11.0525 MHz
RECEIVE
12.1200 MHz
12.1225 MHz

810 kHz-812.5 kHz
N=324-325

LOOP
FILTER

VCOAND
BUFFER

MIXER

AMP
OSC

#2

TRANSMIT
10.24 MHz
RECEIVE
11.31 MHz
(SELECT FREQUENCY TO
GIVE DESIRED R/T OFFSET)

Figure 5. VHF Aircraft 720 Channel Two Crystal Frequency Synthesizer

MOTOROLA COMMUNICATIONS DEVICE DATA

MC145106
2-501

MOTOROLA

-

SEMICONDUCTOR
TECHNICAL DATA

MC145145·2
Advance Information
4·Bit Data Bus Input
PLL Frequency Synthesizer

PSUFFIX

PLASTIC DIP
CASE 707

Interfaces with Single-Modulus Prescalers
The MC145145-2 is programmed by a 4-bit input, with strobe and address
lines. The device features consist of a reference oscillator, 12-bit programmable
reference divider, digital phase detector, 14-bit programmable divide-by-N
counter and the necessary latch circuitry for accepting the 4-bit input data. When
combined with a loop filter and VCO, the MC145145-2 can provide all of the
remaining functions for a PLL frequency synthesizer operating up to the device
frequency limit. For higher VCO frequency operation, a down mixer or a fixed
divide prescaler can be used between the VCO and the MC145145-2.
The MC145145-2 is an improved performance drop-in replacement for the
MC145145-1. Power consumption has decreased and ESD and latch-up
performance have improved.
• General Purpose Applications
CATV
TV Tuning
AM/FM Radios
Scanning Receivers
Two Way Radios
Amateur Radio
• Low Power Consumption Through the Use of CMOS Technology
• 3.0 to 9.0 V Supply Range
• Single Modulus 4-Bit Data Bus Programming
• On- or Off-Chip Reference Oscillator Operation
• ... N Range = 3 to 16,383, ... R Range = 3 to 4,095
• "Linearized" Digital Phase Detector Enhances Transfer Function Linearity
• Two Error Signal Options:
Single Ended (Three-State)
Double Ended
• Chip Complexity: 5,692 FETs or 1,423 Equivalent Gates
REFout

---oc

BLOCK DIAGRAM

DWSUFFIX

SOG
CASE 751D

ORDERING INFORMATION
MC145145P2
MC145145DW2

Plaslic DIP
SOG Package

PIN ASSIGNMENTS
PLASTIC DIP

01 [ 1-

18

DO [ 2

17

03

fin [ 3

16

REFout

02

VSS [ 4

15

$R

VDO [ 5

14

$V

OSCin [ 6

13

LD

OSCout [ 7

12

POout

AO [ 8

11

ST

Al [ 9

10

A2

SOG PACKAGE

OSCin
OSCout _ _ _ _- - l

DO------------------~
Dl----------~
D2----------~_t

D3 ==:=;:::=::::~--1i11
AO
Al
A2---...:=::r:-:.!!.J
ST------'

Dl [ 1-

20

02

00 [ 2

19

03

NC [ 3

18

REFout

fin [ 4
VSS [ 5

17

$R

16

$V

VDO r

6

15 ~ LO

OSCin

7

14

OSCOut

8

13

AO

9

12

Al

10

11

P POout
P ST

PA2
PNC

NC ~ NO CONNECTION

This document contains information on a new product. Specifications and information herein are subject to change without notice.

MC145145-2
2-502

MOTOROLA COMMUNICATIONS DEVICE DATA

This device contains protection
circuitry to guard against damage due
to high static voltages or electric fields.
However, precautions must be taken to
avoid applications of any voltage higher
than maximum rated voltages to these
high-Impedance circuits. For proper
operation, Yin and Vout should be
constrained to the range VSSS(Vin or
Vout)SVDD·
Unused inputs must always be tied to
an appropriate logic voltage level (e.g.,
either VSS or VDD), except for inputs
with pull-up devices. Unused outputs
must be left open.

MAXIMUM RATINGS· (Voltages Referenced to VSS)
Symbol
VDD

Parameter
DC Supply Voltage

Unit

-0.5to+10

V

-0.5 to VDD+0.5

V

Input or Output Current (DC or Transient). per Pin

±10

mA

IDD,ISS

Supply Current, VDD or VSS Pins

±30

mA

PD

Power Dissipation, per Packaget

500

mW

-65 to +150

°C

260

°C

Vln, Vout
lin, lout

Tstg
TL

Input or Output Voltage (DC or Transient)

Value

Storage Temperature
Lead Temperature, 1 mm from Case for 10 Seconds

• Maximum Ratings are those values beyond which damage to the device may occur. Functional
operation should be restricted to the limits in the Electrical Characteristics tables or Pin Descriptions section.
.
t Power Dissipation Temperature:
Plastic DIP: -12 mW/"C from 65 to 85°C
SOG Package: -7.0 mW/"C from 65 to 85°C

ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
-40°C

VDD
Symbol

Parameter

VDD

Power Supply Voltage Range

Iss

Dynamic Supply Current

Test Conditions

~n = OSCin = 10 MHz,

1 Vp-p ac-coupled sine wave
R=128, A=32, N=128
ISS

Quiescent Supply Current

Vln=VDDorVSS
lout = O!IA

25°C

+ 85°C

V

Min

Max

Min

Max

Min

Max

-

3.0

9.0

3.0

9.0

3.0

9.0

V

3.0
5.0
9.0

-

3.0
5.0
9.0

800
1200
1600

-

3.5
10
30

Unit

3.0
7.5
24

rnA

800
1200
1600

-

1600
2400
3200

!IA

3.0
7.5
24

Vln

Input Voltage - fin, OSCin

Input ac-coupled sine wave

-

500

-

500

-

500

-

VIL

Low-Level Input Voltage fin,OSCin

Vout fR or fV Leading: Negative Pulses
Frequency fV < fR or fV Lagging: Positive Pulses
Frequency fV fR and Phase Coincidence:
High-Impedance State

=

VSS
Ground
Circuit Ground.
VOO
Positive Power Supply
The positive supply voltage may range from 3.0 to 9.0 V
with respect to VSS.
OSCin/OSCout
Reference Oscillator Input/Output
These pins form an on-chip reference oscillator when
connected to terminals of an extemal parallel resonant
crystal. Frequency setting capacitors of appropriate value
must be connected from OSCin to ground and OSCout to
ground. OSCin may also serve as input for an externallygenerated reference signal. This signal is typically accoupled to OSCin, but for larger amplitude signals (standard
CMOS-logic levels) dc coupling may also be used. In the
external reference mode, no connection is required to
OSCout·
AD-A2
Address Inputs
AO, A 1, and A2 are used to define which latch receives the
information on the data input lines. The addresses refer to the
following latches:
A2 A1

ST
Strobe Transfer
The rising edge of strobe transfers data into the addressed
latch, the falling edge of strobe latches data into the latch. This
pin should normally be held low to avoid loading latches with
invalid data.

AO Selected

Function

00 01

LD
Lock Detector Signal
High level when loop is locked (fR, fV of same phase and
frequency). Pulses low when loop is out of lock.
li>V.Ii>R
Phase Detector Outputs
These phase detector outputs can be combined externally
for a loop error signal. A single-ended output is also available
for this purpose (see PDout).
If frequency fV is greater than fR or if the phase of fV is
leading, then error information is provided by li>v pulsing low.
li>R remains essentially high.
If the frequency fV is less than fR or if the phase of fV is
lagging, then error information is provided by li>R pulsing low.
li>v remains essentially high.
If the frequency of fV fR and both are in phase, then both
li>v and li>R remain high except for a small minimum time period
when both pulse low in phase.

=

REFout
Buffered Reference Output
Buffered output of on-chip reference oscillator or externally
provided reference-input signal.

02 03

0

0

0

Latch 0

+N Bits

0

1

2

0

0

1

Latch 1

+NBits

4

5

6

7

0

1

0

Latch 2

+NBits

8

9

10

11

3

0

1

1

Latch 3

+N Bits

12

13

- -

1

0

0

Latch 4

Reference Bits

0

1

2

1

0

1

Latch 5

Reference Bits

4

5

6

7

1

1

0

Latch 6

Reference Bits

8

9

10

11

1

1

1

-

-

3

- - - -

MOTOROLA COMMUNICATIONS DEVICE DATA

MC145145-2
2-507

DESIGN CONSIDERATIONS
PHASE-LOCKED LOOP-LOW-PASS FILTER DESIGN

A)

V

K,pKVCO
NR1C

mn

Nmn

~ =

2~KVCO

F(s) = _1_
R1 SC+1

8)

~KVCO

mn=

NC(R1+R2l

~=
F(s) =

C)

POout-

mn=
VCO

~ =

O.5mn (

N
VCO

R2C+~


.)

R2SC + 1
(R1+R2l sC + 1

V~KVCO
NCR1

mn R2C

ASSUMING GAIN A IS VERY LARGE, THEN:
F(s) =

R2SC+ 1
R1SC

NOTE: Sometimes R1 is split into two series resistors each R1 +2. A capacitor Cc is then placed from the midpoint to ground
to further filter v and R. The value of Cc should be such that the comer frequency of this network does not significantly
affect ron.
DEFINITIONS:
N = Total Division Ratio In feedback loop
~ (Phase Detector Gain) = VDoI47t for PDout
~ (Phase Detector Gain) = VDoI27t for v and R

2nalvco

KVCO (VCO Gain)= /!"vVCO

for a typical design wn (Natural Frequency) '" 27tfr (at phase detector input).
10
Damping Factor: 1;=1
RECOMMENDED READING:
Gardner, Floyd M., Phaselock Techniques (second edition). New York, Wiley-Interscience, 1979.
Manassewitsch, Vadim, Frequency Synthesizers: Theory and Design (second edition). New York, Wiley-Interscience, 1980.
Blanchard, Alain, Phase·Locked Loops: Application to Coherent Receiver Design. New York, Wiley-Interscience, 1976.
Egan, William F., Frequency Synthesis by Phase Lock. New York, Wlley-Intersclence, 1981.
Rohde, Ulrich L., Digital PLL Frequency Synthesizers Theory and Design. Englewood Cliffs, NJ, Prentice·Hall, 1983.
Be~ln, Howard M., Design of Phase·Locked Loop Circuits, with Experiments. Indianapolis, Howard W. Sams and Co., 1978.
Kinley, Harold, The PLL Synthesizer Cookbook. Blue Ridge Summit, PA, Tab Books, 1980.
AN535, Phase-Locked Loop Design Fundamentals, Motorola Semiconductor Products, Inc., 1970.
AR254, Phase-Locked Loop Design Articles, Motorola Semiconductor Products, Inc., Reprinted with permission from Electronic DeSign,
1987.

MC145145-2
2-508

MOTOROLA COMMUNICATIONS DEVICE DATA

CRYSTAL OSCILLATOR CONSIDERATIONS
The following options may be considered to provide a
reference frequency to Motorola's CMOS frequency synthesizers.
Use of a Hybrid Crystal Oscillator
Commercially available temperature-compensated crystal
oscillators (TCXOs) or crystal-controlled data clock
oscillators provide very stable reference frequencies. An
oscillator capable of sinking and sourcing 50 IlA at CMOS
logic levels may be direct or dc coupled to OSCin. In general,
the highest frequency capability is obtained utilizing a
direct-coupled square wave having a rail-to-rail (VDD to VSS)
voltage swing. If the oscillator does not have CMOS logic
levels on the outputs, capacitive or ac coupling to OSCin may
be used. OSCout, an unbuffered output, should be left
floating.
For additional information about TCXOs and data clock
oscillators, please consult the latest version of the eem
Electronic Engineers Master Catalog, the Gold Book, or
similar publications.
Design an Off-Chip Reference
The user may design an off-chip crystal oscillator using
ICs specifically developed for crystal oscillator applications,
such as the MC12061 MECL device. The reference signal
from the MECL device is ac coupled to OSCin. For large
amplitude Signals (standard CMOS logic levels), dc coupling
is used. OSCout, an unbuffered output, should be left floating.
In general, the highest frequency capability is obtained with
a direct-coupled square wave having rail-to-rail voltage
swing.
Use of the On-Chip Oscillator Circuitry
The on-chip amplifier (a digital inverter) along with an
appropriate crystal may be used to provide a reference source
frequency. A fundamental mode crystal, parallel resonant at
the desired operating frequency, should be connected as
shown in Figure 7.
ForVDD= 5.0 V, the crystal should be specified for a loading
capacitance, CL, which does not exceed 32 pF for
frequencies to approximately 8.0 MHz, 20 pF for frequencies
in the area of 8.0 to 15 MHz, and 10 pF for higher frequencies.
These are guidelines that provide a reasonable compromise
between IC capacitance, drive capability, swamping variations in stray and IC input/output capacitance, and realistic
CL values. The shunt load capacitance, CL, presented across
the crystal can be estimated to be:

Power is dissipated in the effective series resistance of the
crystal, Re, in Figure 9. The drive level specified by the crystal
manufacturer is the maximum stress that a crystal can
withstand without damaging or excessive shift in frequency.
R1 in Figure 7 limits the drive level. The use of R1 may not
be necessary in some cases (Le., R1=0 al.
To verify that the maximum dc supply voltage does not
overdrive the crystal, monitor the output frequency as a
function of voltage at OSCout. (Care should be taken to
minimize loading.) The frequency should increase very
slightly as the dc supply voltage is increased. An overdriven
crystal will decrease in frequency or become unstable with
an increase in supply voltage. The operating supply voltage
must be reduced or R1 must be increased in value if the
overdriven condition exists. The user should note that the
oscillator start-up time is proportional to the value of R1.
Through the process of supplying crystals for use with
CMOS inverters, many crystal manufacturers have developed expertise in CMOS oscillator design with crystals.
Discussions with such manufacturers can prove very helpful.
(see Table 1).
-

FREQUENG,Xl
SYNTHESIZER

I

,--J\N"\r-----,

~
OSCin

CIT

0
T

OSCout

RIO

C2

"May be deleted in certain cases. See text.
Figure 7. Pierce Crystal Oscillator Circuit
Ca
0

Cin

I
I

[l17o I
I

0

Cout

Figure 8. Parasitic Capacitances of the Amplifier

CL - CinCout
C
C
C1 • C2
- Cin+Cout + a + 0 + C1 + C2
where
Cin = 5.0 pF (see Figure 8)
Cout = 6.0 pF (see Figure 8)
Ca = 1.0 pF (see Figure 8)
Co = the crystal's holder capacitance (see Figure 9)
C1 and C2 = extemal capacitors (see Figure 7)
The oscillator can be "trimmed" on-frequency by making a
portion or all of C1 variable. The crystal and associated
components must be located as close as possible to the OSCin
and OSCout pins to minimize distortion, stray capacitance,
stray inductance, and startup stabilization time. In some
cases, stray capacitance should be added to the value for Cin
and Couto

MOTOROLA COMMUNICATIONS DEVICE DATA

I
<>-l

D1-02
Co

Note: Values are supplied by crystal manufacturer
(parallel resonant crystal).
Figure 9. Equivalent Crystal Networks

MC145145-2
2-509

------------

----

Table 1. Partial List of Crystal Manufacturers
Name

Address

Phone

United States Crystal Corp.
Crystek Crystal
Statek Corp.

3605 McCart St., Ft. Worth, TX 76110
2371 Crystal Dr., Ft. Myers, FL 33907
512 N. Main St., Orange, CA 92668

(817) 921-3013
(813) 936-2109
(714) 639-7810

Note: Motorola cannot recommend one supplier over another and in no way suggests that this
is a complete listing of crystal manufacturers.

3.S8105MHz

r--..--1Dr--.-~
UHFNHF
TUNER
OR CATV
FRONT END

MC12071
PRESCALER

112 MCl458

Figure 10. TV/CATV Tuning System

RECOMMENDED READING

APPLICATIONS

Technical Note TN-24, Statek Corp.
Technical Note TN-7, Statek Corp.
E. Hafner, ''The Piezoelectric Crystal Unit - Definitions and
Method of Measurement", Proc. IEEE, Vol. 57, No.2 Feb.,
1969.
D. Kemper, L. Rosine, "Quartz Crystals for Frequency
Control", Electro-Technology, June, 1969.
P. J. Ottowitz,"A Guide to Crystal Selection", Electronic
Design, May, 1966.

The features ofthe MCl45145-2 permit bus operation with
a dedicated wire needed only for the strobe input. In a
microprocessor-controlled system this strobe input is
accessed when the PLL is addressed. The remaining data
and address inputs will directly interface to the microprocessor's data and address buses.
The + R programmability is used to advantage in Figure
10. Here, the nominal +R value is 3667, but by
programming small changes in this value, fine tuning is
accomplished. BeUer tuning resolution is achievable with
this method than by changing the +N, due to the use of
the large fixed prescaling value of +256 provided by the
MC12071.
The two loop synthesizer, in Figure 11, takes advantage
of .these features to control the phase locked loop with a
minimum of dedicated lines while preserving optimal loop
performance. Both 25-Hz and 100-Hz steps are provided
while the relatively large reference frequencies of 10kHz
or 10.1 kHz are maintained.

MC145145-2
2-510

MOTOROLA COMMUNICATIONS DEVICE DATA

10.1000
MHz

cbT

±
OSCout
OSCin

7.9996 TO
32.0184 MHz
(100·Hz STEPS)

I
REFout

LD
PDout

1.9999 TO
8.0046 MHz
(25·Hz STEPS)

-

DO

,,/

01
-:

02

MC145145·2
LOOP 1

, - 0 - 03

R
v

-

AO
Al
finl

A2
ST

VDD

VSS

.l

I

I

i

I

I

OSCout
OSCin

REFout

LD

DO

:-1

3.9996 TO 4.9995 MHz
AND

--I--------lX
16.0085 TO 17.0084 MH z
(10.1kHz STEPS)

CHOICE OF
DETECTOR
ERRORSIGNALS

PDout

r-

R

r--

v

r-

fin2

H

01
02

f-o-

MC145145·2
LOOP 2

03

4.000 to 15.0100 MHz
(10·kHz STEPS)

AO
Al
A2
ST

ADDRESS AND DATA

t

VDD

VSS

I

I

CHIP SELECT

v~----_.J/

TO CONTROLLER
NOTES:
1. Table 2 provides program sequence for the + Nl (Loop 1) and + N2 (Loop 2) Counters.
2. +Rl =1000, fRl =10.1 kHz, +R2=1010, fR2=10 kHz.
3. fVCOl = Nl (fRl)+ N2(fR2)= Nl (fR2 +lif) + N2(fR2) where L'>f= 100 Hz
4. Other fRl and fR2 values may be used with appropriate +Nl and +N2 changes.

Figure 11. Two Loop Synthesizer Provides 25- and 100-Hz Frequency Steps While Maintaining High
Detector Comparison Frequencies of 10 and 10.1 kHz

MOTOROLA COMMUNICATIONS DEVICE DATA

MC145145-2
2-511

Table 2. Programming Sequence for Two-Loop Synthesizer of Figure 11
+Nl

"1,,

!

"~,,

+

!

495

"1,,

~

"B"

4.0000
3.9900

+

+

+

3.0tOO

8.t195

4.0200
4.0100

8.0196
8.0197

+

8.0295

+

"0"

303

3.0300

lL

+
"B"
,,~

+

!

1684

+

Increasing
In 1OO-Hz Steps

!

r

+

8.0095
8.0096
8.0097

+

1585
1586

7.9996
7.9997

3.0100
4.0100
4.0000

"B"

"A"

fveOl (MHz)

301
401
400
303
402
401

"C"

!

"A"

"E"

+

4.9995

,!

,!
,!

"E"

,

fve02 (MHz)

400
399

3.9996
4.0097

"B"

+
"A"

,!
r,

+N2

flnl (MHz)

396
397

1600
1599

15.100
16.0000
15.9900

+

15.0100

+

1501
16.0085
16.0186

+

17.0084

lJ.9995
19.9996
19.9997

+

20.0095
20.0085
20.0086
201184
20.0185
20.0186

"~,,
"C"

"0"

+

20.0284
Increasing
In 1OO-Hz Steps

3i.0084
"E"

+
"P'

!

32.0085
32.0086

!

321184

MC145145-2
2-512

MOTOROLA COMMUNICATIONS DEVICE DATA

MOTOROLA

-

SEMICONDUCTOR
TECHNICAL DATA

MC145146·2
Advance Information
4·Bit Data Bus Input
PLL Frequency Synthesizer

PSUFFIX
PLASTIC DIP
CASE73B

Interfaces with Dual-Modulus Prescalers
The MC145146-2 is programmed by a 4-bit input, with strobe and address
lines. The device features consist of a reference oscillator, 12-bit programmable
reference divider, digital phase detector, 10-bit programmable divide-by-N
counter, 7-bit divide-by-A counter and the necessary latch circuitry for accepting
the 4-bit input data. When combined with a loop filter and VCO, the MC145146-2
can provide all of the remaining functions for a PLL frequency synthesizer
operating up to the device frequency limit. For higher VCO frequency operation,
a down mixer or a dual-modulus prescaler can be used between the VCO and
the MC145146-2.
The MC145146-2 is an improved performance drop-in replacement for the
MC145146-1. Power consumption has decreased and ESD and latch-up
performance have improved.
• General Purpose Applications
CATV
TV Tuning
AM/FM Radios
Scanning Receivers
Two Way Radios
Amateur Radio
• Low Power Consumption Through the Use of CMOS Technology
• 3.0 to 9.0 V Supply Range
• Programmable Reference Divider for Values Between 3 and 4095
• On- or Off-Chip Reference Oscillator Operation
• Dual-Modulus 4-Bit Data Bus Programming
• + N Range = 3 to 1023, + A Range = 0 to 127
• "Linearized" Digital Phase Detector Enhances Transfer Function Linearity
• Two Error Signal Options:
Single Ended (Three State)
Double Ended
• Chip Complexity: 5,692 FETs or 1,423 Equivalent Gates

DWSUFFIX
SOG
CASE 75tD

ORDERING INFORMATION
MCt45t46P2
Plastic DIP
MCt45t46DW2 SOG Package

PIN ASSIGNMENT
01

1.

20 ~ 02

DO

2

19 ~

lin

3

18 ~ IR

VSS

4

17

0 R

POout

5

16

b v

03

VOO

6

15 ~

OSCin

7

14

OSCout

8

13

AO

9

12

0 MC
0 LO
0 ST

At

10

11

P A2

BLOCK DIAGRAM

tv

OSCin - ......--1
OSCout _ _ _ _ _.J
LO
OO--------~~r+--_,
Ot----------1~r+--_io

02----------1~~--_44,

03==r~n~=t11tr==ttFh.-l~§~

A2
At
AO
ST _.....!::::::::::::::::T-'-'-"-'

POout

tv

,-:-:-,.--:-!-lrli.-,

"'V

"'R

~n

>----

MODULUS CONTROL (MC)

This document contains infonmatlon on a new product. Specifications and Infonmation herein are subject to change wHhout notice.

MOTOROLA COMMUNICATIONS DEVICE DATA

MC145146-2
2-513

MAXIMUM RATINGS· (Voltages Referenced to VSS)
Symbol
VDD
Vln, Vout

Parameter

Unit

Value

DC Supply Voltage
Input or Output Voltage (DC or Transient)

-0.Sto+l0

V

-0.5 to VDD+O.S

V

rnA

Input or Output Current (DC or Transient), per Pin

±10

IDD,ISS

Supply Current, VDD or VSS Pins

±30

rnA

Po

Power Dissipation, per Packaget

500

mW

Tstg

Storage Temperature

-65 to +150

·C

260

·C

lin, lout

TL

Lead Temperature, 1 mm from Case for 10 Seconds

* Maximum Ratings are those values beyond which damage to the deVIce may occur. Functional
operation should be restricted to the limits In the Electrical Characteristics tables or Pin Descript tions section.
Power Dissipation Temperature Derating:
Plastic DIP: -12 mWI"C from 65 to 8S·C
SOG Package: -7.0 mWI"C from 55 to 85·C

These devices contain protection circuitry to guard against damage due to
high static voltages or electric fields.
However, precautions must be taken to
avoid applications of any voltage higher
than maximum rated voltages to these
high-impedance circuits. For proper
operation, Yin and Vout shOUld be constrained to the range VSS S (Vin or
Vou!lSVDD·
Unused Inputs must always be tied to
an appropriate logic voltage level (e.g.,
eHher VSS or VDD), except for Inputs
wHh pull-up devices. Unused outputs
must be left open.

ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

Parameter

VDD

Power Supply Voltage Range

25·C

-40·C

VDD
Symbol

+8S·C

Test Condition

V

Min

Max

Min

Max

Min

Max

-

3.0

9.0

3.0

9.0

3.0

9.0

V

3.0
5.0
9.0

-

Iss

Dynamic Supply Current

fin=OSCin= 10 MHz,
1 Vp-p ae-coupled sine wave
R=128, A=32, N=128

3.0
5.0
9.0

ISS

Quiescent Supply Current

Vin=VDDorVss
10ut=0 I1A

Yin

Input Voltage - ~n, OSCln

Input ac-coupled sine wave

VIL

Low-Level Input Voltage fln,OSCln

Vout~2.1 V

VIH

High-Level Input Voltagefln,eSCln

VIL

VIH

800
1200
1600

-

3.5
10
30

Unit

3.0
7.5
24

mA

800
1200
1600

-

1600
2400
3200

I1A

3.0
7.5
24

-

500

-

500

-

500

-

Vout~3.SV
Vout~6.3V

Input dccoupled
square wave

3.0
5.0
9.0

-

0
0
0

-

0
0
0

-

0
0
0

VoutSO.9V
VoutSl.5V
VoutS2.7V

Input dccoupled
square wave

3.0
5.0
9.0

3.0
5.0
9.0

-

3.0
5.0
9.0

-

3.0
5.0
9.0

-

Low-Level Input Voltage except fin, OSCin

3.0
5.0
9.0

-

0.9
1.5
2.7

-

0.9
1.5
2.7

-

0.9
1.5
2.7

High-Level Input Voltageexcept ~n, OSCin

3.0
5.0
9.0

2.1
3.5
6.3

-

2.1
3.5
6.3

-

2.1
3.5
6.3

-

mVp-p
V

V

V

V

lin

Input Current (fin, OSCin)

Vin=VDD orVSS

9.0

±2.0

±50

±2.0

±25

±2.0

±22

I1A

IlL

Input Leakage Current
(all Inputs except fin, OSCln)

Vln=VSS

9.0

-

-0.3

-

-0.1

-

-1.0

I1A

IIH

Input Leakage Current
(all Inputs except ~n, OSCln)

Vln=VDD

9.0

-

0.3

-

0.1

-

1.0

I1A

Cln

Input Capacitance

-

-

10

-

10

-

10

pF

(continued)

MC145146-2
2-514

MOTOROLA COMMUNICATIONS DEVICE DATA

ELECTRICAL CHARACTERISTICS-Continued (Voltages Referenced to VSS)
Symbol

Perameter

Test Condition

25·C

-40·C

Voo

+S5·C

V

Min

Max

Min

Max

Min

Max

Unit

VOL

low-level Output Voltage
-OSCout

lout" 0 J1A
Vln=VDD

3_0
5.0
9.0

-

0.9
1.5
2.7

-

0.9
1.5
2.7

-

0.9
1.5
2.7

V

VOH

High-level Output Voltage
-OSCout

10ut" 0 IiA
Vln=VSS

3.0
5.0
9.0

2.1
3.5
6.3

-

2.1
3.5
6.3

-

2.1
3.5
6.3

-

-

V

VOL

low-level Output Voltage
- Other Outputs

10ut" 0 IiA

3.0
5.0
9.0

-

0.05
0.05
0.05

-

0.05
0.05
0.05

-

0.05
0.05
0.05

V

VOH

High-level Output Voltage
- Other Outputs

lout" 0 J1A

3.0
5.0
9.0

2.95
4.95
S.95

2.95
4.95
S.95

low-level Sinking Current
- Modulus Control (MC)

Vout=0.3V
Vout=0.4V
Vout=0.5V

3.0
5.0
9.0

1.3
1.9
3.B

10H

High-level Sourcing Current
- Modulus Control (MC)

Vou t=2.7V
Vou t=4.6V
Vout=B.5V

3.0
5.0
9.0

-0.6
-0.9
-1.5

10l

low-level Sinking Current
- lock Detect (lD)

Vout=0.3V
Vout=0.4V
Vou t=0.5V

3.0
5.0
9.0

0.25
0.64
1.3

10H

High-level Sourcing Current
- lock Detect (lD)

Vout=2.7V
Vout=4.6V
Vout=B.5V

3.0
5.0
9.0

-0.25
-0.64
-1.3

10l

low-level Sinking Current
- Other Outputs

Vout=0.3V
Vout=0.4V
Vout=0.5V

3.0
5.0
9.0

0.44
0.64
1.3

10H

High-level Sourcing Current
- Other Outputs

Vout=2.7V
Vout=4.6V
Vout=B.5V

3.0
5.0
9.0

-0.44
-0.64
-1.3

-0.35
-0.51
-1.0

-

-0.22
-0.36
-0.7

-

V

10l

-

10Z

Output leakage Current
-PDout

Vout= VDD or VSS
Output In Off State

9.0

-

±0.3

-

±0.1

-

±1.0

J1A

COul

Output Capacitance -

PDout - Three-State

-

-

10

-

10

-

10

pF

PDout

MOTOROLA COMMUNICATIONS DEVICE DATA

1.1
1.7
3.3
-0.5
-0.75
-1.25
0.2
0.51
1.0
-0.2
-0.51
-1.0
0.35
0.51
1.0

2.95
4.95
S.95
0.66
1.0B
2.1
-0.3
-0.5
-O.B
0.15
0.36
0.7
-0.15
-0.36
-0.7
0.22
0.36
0.7

mA

mA

mA

mA

mA

mA

MC145146-2
2-515

AC ELECTRICAL CHARACTERISTICS (CL =50 pF, Input tr=tf= 10 ns)
Figure
#

VDD
V

Guaranteed Limit
25°e

Guaranteed Limit
-40 oe to + osoe

Maximum Propagation Delay, fin to MC

1,6

3.0
5.0
9.0

110
60
35

120
70
40

ns

Output Pulse Width, ~R, ~V, and LD with fR in
Phase with

2,6

3.0
5.0
9.0

25 to 200
20 to 100
10t070

25 to 260
20 to 125
10t060

ns

trLH

Maximum Outpu1 Transition lime, MC

3,6

3.0
5.0
9.0

115
60
40

115
75
60

ns

trHL

Maximum Output Transition lime, MC

3,6

3.0
5.0
9.0

60
34
30

70
45
36

ns

trLH, trHL

Maximum Output Transition lime, LD

3,6

3.0
5.0
9.0

160
90
70

200
120
90

ns

trLH, trHL

Maximum Output Transition lime, Other Outputs

3,6

3.0
5.0
9.0

160
60
60

175
100
65

ns

Symbol

Parameter

tpLH, tpHL

tw

tv

Unit

tsu

Minimum Set-Up Time, Data to ST

4

3.0
5.0
9.0

10
10
10

TBD
TBD
TBD

ns

tsu

Minimum Set-Up Time, Address to ST

4

3.0
5.0
9.0

25
20
15

TBD
TBD
TBD

ns

th

Minimum Hold lime, Address to ST

4

3.0
5.0
9.0

10
10
10

TBD
TBD
TBD

ns

It!

Minimum Hold lime, Data to ST

4

3.0
5.0
9.0

25
20
15

TBD
TBD
TBD

ns

tw

Minimum Input Pulse Width, ST

5

3.0
5.0
9.0

40
30
20

TBD
TBD
TBD

ns

SWITCHING WAVEFORMS
INPUT
.
tpLH-+t

-

VDD

~A'~V'Ld~50-%-- tw---~r

VSS

'fA in phase with tv "----------'-

~i

OUTPUT ~

•

Figure 2.

'--

DATAOA~50%
_

Figure 1.

ADDAESS

t

tSU~1h
trHL

ST

VDD

. _

50%
-----'

VSS

- VDD
'-_ _ _ __
VSS

Figure 4.
TEST POINT

Figure 3.

OUTPUT
DEVICE
UNDER
TEST

'Includes all probe and jig capacitance.

Figure 5.

MC145146-2
2-516

Figure 6. Test Circuit

MOTOROLA COMMUNICATIONS DEVICE DATA

FREQUENCY CHARACTERISTICS (Voltages Relerenced to VSS, CL =50 pF, Input tr=tl= 10 ns unless otherwise specilied)
-40'C

Voo
Symbol

Parameter

Test Condition

V

Ii

Input Frequency (lin, aSCin)

R;,S, A;,O, N;,a
Yin = 500 mVp-p ac-coupled
sine wave

3.0
5.0
9.0

R;,a, A;,O, N"a
Yin = 1.0 Vp-p ac-coupled
sine wave

3.0
5.0
9.0

R"a, A"O, N"a
Vin=VOO to VSS
dc-coupled square wave

n

n

3.0
5.0
9.0

Min

-

-

-

n

+S5'C

25'C

Max

Min

Max

Min

Max

Unit

6.0
15
15

-

6.0
15
15

-

6.0
15
15

MHz

-

12
20
22

-

-

7.0
20
22

MHz

12
22
25

-

a.o
22
25

MHz

12
22
25
13
25
25

-

-

-

-

-

-

A~~~~~~~fA ______~ ~--------~i ~______~ ~________~I ~
n,

-

VVHL

tv

FEEDBACK
(fin +N) _ _ _ _-'-..J

n

n

' i-------------+-----,

U

U
, ,

:, I,

I

' I,

LJ

U

U
, ,
U

PDoul -------I

~A

~V

LD

VL
-VH
HIGH IMPEDANCE

W
-VL
r----------r------------,------VH

VH = High voltage level
VL = Low voltage level
• At this pOint, when both IR and fV are in phase, the output is lorced to near mid supply.
Note: The POout generates error pulses during out-ol-Iock conditions. When locked in phase and Irequency,
the output is high impedance and the voltage at that pin is determined by the low-pass lilter capacitor.

Figure 7. Phase/Frequency Detectors and Lock Detector Output Waveforms

MOTOROLA COMMUNICATIONS DEVICE DATA

MC145146-2
2-517

PIN DESCRIPTIONS
Do-D3
Data Inputs (Pins 2, 1,20,19)
Information at these inputs is transferred to the internal
latches when the ST input is in the high state. 03 (Pin 19)
is the most significant bit.
fin
Frequency Input (Pin 3)
Input to +N Portion of Synthesizer. fin is typically derived
from loop VCO and is ac coupled into Pin 3. For larger
amplitude signals (standard CMOS-logic levels) dc coupling
may be used.
VSS
Ground (Pin 4)
Circuit Ground.
PDout
Single-Ended Phase Detector Output (Pin 5)
Three-state output of phase detector for use as loop error
signal.
Frequency fV>fR or fV Leading: Negative Pulses
Frequency fV R
2MtvCO
KVCO (VCO Gain) = !J.VVCO
for a typical design wn (Natural Frequency) = 21tfr (at phase detector Input).
10
Damping Factor: ~ = 1
RECOMMENDED READING:
Gardner, Floyd M., Phase/oc/( Techniques (second edition). New York, Wiley·lntersclence, 1979.
Manassewitsch, Vadim, Frequency Synthesizers: Theory and Design (second edition). New York, Wlley-Intersclence, 1980.
Blanchard, Alain, Phase-Locked Loops: Application to Coherent Receiver Design. New York, Wiley-Interscience, 1976.
Egan, William F., Frequency Synthesis by Phase Lock. New York, Wiley-Interscience, 1981.
Rohde, Ulrich L., Digital PLL Frequency Synthesizers Theory and Design. Englewood Cliffs, NJ, Prentice-Hail, 1983.
Berlin, Howard M., Design of Phase-Locked Loop Circuits, with Experiments. Indianapolis, Howard W. Sams and Co., 1978.
Kinley, Harold, The PLL Synthesizer Cookbook. Blue Ridge Summit, PA, Tab Books, 1980.
AN535, Phase·Locked Loop Design Fundamentals, Motorola Semiconductor Products, Inc., 1970.
AR254, Phase-Locked Loop Design Articles, Motorola Semiconductor Products, Inc., Reprinted with permission from Electronic Design,
1987.

MOTOROLA COMMUNICATIONS DEVICE DATA

MC145146-2
2-519

DESIGN CONSIDERATIONS
CRYSTAL OSCILLATOR CONSIDERATIONS
The following options may be considered to provide a
reference frequency to Motorola's CMOS frequency
synthesizers. The most desirable is discussed first.
Use Of A Hybrid Crystal Oscillator
Commercially availE!ple temperature-compensated
crystal oscillators (TCXOs) or crystal-controlled data clock
oscillators provide very stable reference frequencies. An
oscillator capable of sinking and sourcing 50 ~A at CMOS
logic levels may be direct or dc coupled to OSCin. In
general, the highest frequency capability is obtained
utilizing a direct-coupled square wave having a rail-Io-rail
(VDD to VSS) voltage swing. If the oscillator does not have
CMOS logic levels on the outputs, capacitive or ac
coupling to OSCin may be used. OSCout, an unbuffered
output, should be left floating.
For additional information about TCXOs and data clock
oscillators, please consult the latest version of the eem
Electronic Engineers Master Catalog, the Gold Book, or
similar publications.
Design An Off-chip Reference
The user may design an off-chip crystal oscillator using
ICs specifically developed for crystal oscillator applications, such as the MC12061 MECl device. The reference
signal from the MECl device is ac coupled to OSCin. For
large amplitude signals (standard CMOS logic levels),
dc coupling is used. OSCout, an unbuffered output,
should be left floating. In general, the highest frequency
capability is obtained with a direct-coupled square wave
having rail-to-rail voltage swing.
Use Of The On-chip Oscillator Circuitry
The on-chip amplifier (a digital inverter) along with an
appropriate crystal may be used to provide a reference
source frequency. A fundamental mode crystal, parallel
resonant at the desired operating frequency, should be
connected as shown in Figure B.
For VDD=5.0 V, the crystal should be specified for a
loading capacitance, Cl, which does not exceed 32 pF for
frequencies to approximately B.O MHz, 20 pF for frequencies in the area of B.O to 15 MHz, and 10 pF for higher
frequencies. These are guidelines that provide a reasonable compromise between IC capacitance, drive capability, swamping variations in stray and IC input/output
capacitance, and realistic Cl values. The shunt load
capacitance, Cl, presented across the crystal can be
.
estimated to be:

time. In some cases, stray capacitance should be added
to the value for Cin and Cout.
Power is dissipated in the effective series resistance
of the crystal, Re, in Figure 10. The drive level specified
by the crystal manufacturer is the maximum stress that
a crystal can withstand without damaging or excessive
shift in frequency. R1 in Figure Blimits the drive level. The
use of R1 may not be necessary in some cases (i.e.,
R1=0 ohms).
To verify that the maximum dc supply voltage does not
overdrive the crystal, monitor the output frequency as a
function of voltage at OSCout. (Care should be taken to
minimize loading.) The frequency should increase very
slightly as ihe dc supply voltage is increased. An
overdriven crystal will decrease in frequency or become
unstable with an increase in supply voltage. The
operating supply voltage must be reduced or R1 must be
increased in value if the overdriven condition exists. The
user should note that the oscillator start-up time is
proportional to the value of R1.
Through the process of supplying crystals for use with
CMOS inverters, many crystal manufacturers have
developed expertise in CMOS oscillator design with
crystals. Discussions with such manufacturers can prove
very helpful. See Table 1.

o

OSCin

OSCout

RI"

I-+-'VIIIr--'

CIJ J C2

"May be deleted in certain cases. See text.

Figure 8. Pierce Crystal Oscillator Circuit

0

c.

l

~

I

InJ

0

Cout

J

Figure 9. Parasitic Capacitances of the Amplifier

C1 • C2
CinCout
Cl= - C
C , +Ca+Co + C1 C2
m+ out
+
where
Cin =5.0 pF (see Figure 9)
Cout =6.0 pF (see Figure 9)
C a = 1.0 pF (see Figure 9)
Co =the crystal's holder capacitance (see Figure 10)
C1 and C2=external capacitors (see Figure B)
The oscillator can be "trimmed" on-frequency by making
a portion or all of C1 variable. The crystal and associated
components must be located as close as possible to the
OSCin and OSCout pins to minimize distortion, stray
capacitance, stray inductance, and startup stabilization

MC145146-2
2-520

Note: Values are supplied by crystal manufacturer
(parallel resonant crystal).

Figure 10. Equivalent Crystal Networks

MOTOROLA COMMUNICATIONS DEVICE DATA

Table 1. Partial List of Crystal Manufacturers
Name

Address

Phone

United States Crystal Corp.
Crystek Crystal
Statek Corp.

3605 McCartSt., Ft. Worth, TX 76110
2371 Crystal Dr., Ft. Myers, FL 33907
512 N. Main St., Orange, CA 92668

(817) 921·3013
(813) 936-2109
(714) 639-7810

Note: Motorola cannot recommend one supplier over another and in no way suggests that this
is a complete listing of crystal manufacturers.

RECOMMENDED READING
Technical Note TN-24, Statek Corp.
Technical Note TN-7, Statek Corp.
E. Hafner, "The Piezoelectric Crystal Unit - Definitions and
Method of Measurement", Proc. IEEE, Vol. 57, No.2 Feb.,
1969_
D. Kemper, L. Rosine, "Quartz Crystals for Frequency
Control", Electro-Technology, June, 1969.
P. J. Otlowitz, "A Guide to Crystal Selection", Electronic
Design, May, 1966.

DUAL-MODULUS PRESCALING
OVERVIEW
The technique of dual-modulus prescaling is well established as a method of achieving high performance frequency
synthesizer operation at high frequencies. Basically, the
approach allows relatively low-frequency programmable
counters to be used as high-frequency programmable
counters with speed capability of several hundred MHz. This
is possible without the sacrifice in system resolution and
performance that results if a fixed (single-modulus) divider is
used for the prescaler.
In dual-modulus prescaling, the lower speed counters must
be uniquely configured. Special control logic is necessary to
select the divide value P or P+ 1 in the prescaler for the
required amount of time (see modulus control definition).
Motorola's dual-modulus frequency synthesizers contain this
feature and can be used with a variety of dual-modulus
prescalers to allow speed, complexity and cost to be tailored
to the system requirements. Prescalers having P, P+ 1 divide
values in the range of +3/+4 to +128/+129 can be controlled
by most Motorola frequency synthesizers.
Several dual-modulus prescaler approaches suitable for
use with the MC145146-2 are:
MC12009
MC12011
MC12013
MC12015
MC12016
MC12017
MC12018
MC12022A
MC12032A

+5/+6
+8/+9
+10/+11
+32/+33
+40/+41
+64/+65
+128/+129
+64/65 or +128/129
+64/65 or + 128/129

440 MHz
500 MHz
500 MHz
225 MHz
225 MHz
225 MHz
520 MHz
1.1 GHz
2.0 GHz

MOTOROLA COMMUNICATIONS DEVICE DATA

DESIGN GUIDELINES
The system total divide value, Ntotal (NT) will be dictated
by the application, I.e.
NT =

frequency into the prescaler
= N • P+A
frequency into the phase detector

N is the number programmed into the + N counter, A is
the number programmed into the + A counter, P and P + 1
are the two selectable divide ratios available in the
dual-modulus pre scalers. To have a range of NT values in
sequence, the + A counter is programmed from zero through
P -1 for a particular value N in the + N counter. N is then
incremented to N + 1 and the + A is sequenced from 0 through
P-1 again.
There are minimum and maximum values that can be
achieved for NT. These values are a function of P and the
size of the + Nand + A counters. The constraint N '2A always
applies. If Amax = P -1, then Nmin '2 P -1. Then NTmin = (P -1)
P+A or (P-1) P since A is free to assume the value of O.
NTmax = Nmax • P + Amax
To maximize system frequency capability, the dual-modulus
prescaler output must go from low to high after each group
of P or P + 1 input cycles. The prescaler should divide by P
when its modulus control line is high and by P + 1 when its
modulus control is low.
For the maximum frequency into the prescaler (fVCO max),
the value used for P must be large enough such that:
1. fVCO max divided by P may not exceed the frequency
capability of fin (input to the + Nand + A counters).
2. The period offVCO divided by P must be greaterthanthe
sum of the times:
a. Propagation delay through the dual-modulus
prescaler.
b. Prescaler setup or release time relative to its
modulus control signal.
c. Propagation time from fin to the modulus control
output for the frequency synthesizer device.

MC145146-2
2-521

A sometimes useful simplification in the programming code
can be achieved by choosing the values for P of 8, 16, 32,
or 64. For these cases, the desired value of NT results when
NT in binary is used as the program code to the +N and +A
counters treated in the following manner:
1. Assume the +A counter contains "a" bits where 2a ;;::P.
2. Always program all higher order +A counter bits above
"a" toO.
3. Assume the +N counter and the +A counter (with all
the higher order bits above "a" ignored) combined into
a single binary counter of n+a bits in length
(n '" number of divider stages in the + N counter). The
MSB of this "hypothetical" counter is to correspond to
the MSB of + N and the LSB is to correspond to the
LSB of +A. The system divide value, NT, now results
when the value of NT in binary is used to program the
"new' n + a bit counter.
By using the two devices, several dual-modulus values are
achievable (shown in Figure 11).

As a result the reference oscillator can frequently be
chosen to serve multiple system functions such as a
second local oscillator in a receiver design or a
microprocessor system clock. Typical applications that
take advantage of these MC145146-2 features including
the dual modulus capability are shown in Figures 12, 13,
and 14.

MC

,.---!-l-,r-l

-1

DEVICE A

I~

1 !I-

DEVICE B

DEVICE

DEVICE~

APPLICATIONS
The features of the MC145146-2 permit bus operation with
a dedicated wire needed only for the strobe input. In a
microprocessor-controlled system this strobe input is accessed when the phase lock loop is addressed. The remaining
data and address inputs will directly interface to the
microprocessor's data and address buses.
The device architecture allows the user to establish any
integer reference divide value between 3 and 4095. The
wide selection of + R values permits a high degree of
flexibility in choosing the reference oscillator frequency.

MC12009

MC12011

MC10131

+20/+21

+321+33

+40/+41

MC10138

+50/+51

+801+81

+100/+101

MC10154

+40/+41
OR
+80/+81

+64/+65
OR
+128/+129

MC12013

+80/+81

NOTE: MC12009, MC12011, and MC12013 are pin equivalent.
MC12015, MC12016, and MC12017 are pin equivalent.

Figure 11. Dual Modulus Values

LD

13
LD

OSCout

PDout

OSCin

R

-=-

6
4

-=-

MCl45146-2
VDD
VSS

5
17

OPTIONAL
LOOP ERROR
SIGNAL

v 16

CONTROL VOLTAGE
TO FM AND AM
OSCILLATORS

MOD
14
CONTROL
fin

FROM
FMOSC
FROM
AMOSC
NOTES:
1. For FM: Channel spacing =fR = 25 kHz, R= 160.
For AM: Channel spacing=fR= 1 kHz, R=4000.
2. Various channel spacings and reference oscillator frequencies can be chosen since any
Rvalue from 3 to 4095 can be established.
3. Data and address lines are inactive and high impedance when pin t2 is low. Their interface
with the controller may therefore be shared wHh other system functions ndesired.

Figure 12. FMlAM Broadcast Radio Synthesizer

MC145146-2
2-522

MOTOROLA COMMUNICATIONS DEVICE DATA

CHOICE OF
REF.OSC.
FREQUENCY
(ON-CHIP OSC.
OPTIONAL)

,-

--

I
I

L

7

LOCK DETECT
RECEIVER L.O.
SIGNAL
443.325 __ 443.950 MHz
(25 kHz STEPS)

PDout

OSCin

VDD

- } FOR USE WITH EXTERNAL
_
PHASE DETECTOR (OPTIONAL)

~R

MC145146-2

TRANSMITIER SIGNAL
459.025-459.650 MHz
(25 kHz STEPS)

~V

MOD
CONTROL
VSS

-=

03

fin
ST
12

DO

~---....,v

TO SHARED CONTROLLER BUS

CHIP
SELECT TO
CONTROLLER

NOTES:
1. Receiver I.F.=10.7 MHz, low side injection.
2. Duplex operation with 5 MHz receive/transmit separation.
3. fR=25 kHz, ... R chosen to correspond with desired reference oscillator frequency.
4. Ntotal= 17,733 to 17,758=N. P+A; N=277, A=5 to 30 for P=64.

Figure 13_ Synthesizer for UHF Mobile Radio Telephone Channels Demonstrates use of the MC145146-2 in
Microprocessor/Microcomputer Controlled Systems Operating to Several Hundred MHz
RECEIVER
2ND. L.O.
33.300 MHz

CHOICE OF
REF.OSC.
FREQUENCY
(ON-CHIP OSC.
OPTIONAL)

-

-- -}

r- I

-

FOR USE WITH EXTERNAL
PHASE DETECTOR (OPTIONAL)

...-----.

LOCK DETECT
SIGNAL

OSCout
PDout

OSCin

VDD
4

~R

MC145146-2

~V

CO~~~OL 1--"''----=:..::..:.::.:..:..::::.=:..:'-'='-----,
VSS

,

./ CHIP
v
SELECTTO
TO SH ARED CONTROLLER BUS CONTROLLER

TRANSMITIER SIGNAL
825.030 -- 844.980 MHz
(30 kHz STEPS)

~----~~-------

+321 +33 DUAL MODULUS PRESCALER

NOTES:
1. Receiver 1st I.F. = 45 MHz, low side injection; Receiver 2nd I.F. = 11.7 MHz, low side injection.
2. Duplex operation with 45 MHz receive/transmit separation.
3. fR=7.5 kHz, +R= 1480.
4. Ntotal=N. 32+A=27,501 to 28,166; N=859 to 880; A=O to 31.
5. Only one implementation is shown. Various other configurations and dual modulus prescaling values to +128/+ 129 are possible.

Figure 14. 666 Channel, Computer Controlled, Mobile Radio Telephone Synthesizer for
BOO-MHz Cellular Radio Systems

MOTOROLA COMMUNICATIONS DEVICE DATA

MC145146-2
2-523

MOTOROLA

-

SEMICONDUCTOR
TECHNICAL DATA

MC145149

Dual PLL Frequency Synthesizer
Interfaces with Dual-Modulus Prescalers
PSUFFIX
PLASTIC DIP
CASE 738

The MC145149 contains two PLL Frequency Synthesizers which share a
common serial data port and common reference oscillator. The device
contains two 14-stage R counters, two 10-stage N counters, and two 7-stage
A counters. ,.A. II six counters arc fully programmable thiOUgh a serial port. The
divide ratios are latched into the appropriate counter latch according to the
last data bits (control bits) entered.
When combined with external low-pass filters and voltage controlled
oscillators (VCOs), the MC145149 can provide all the remaining functions
for two PLL frequency synthesizers operating up to the device's frequency
limit. For higher VCO frequency operation, a down mixer or dual-modulus
prescaler can be used between the VCO and the synthesizer IC.
• Low Power Consumption Through Use of CMOS Technology
• Wide Operating Voltage Range: 3 to 9 V
• Operating Temperature Range: - 40 to + 85°C

• + R Range=3 to 16,383
• + N Range=3 to 1023
• + A Range=O to 127
•
•
•
•

Two "Linearized" Three-State Digital Phase Detectors with No Dead Zone
Two Lock Detect Signals (LD1 and LD2)
Two Open-Drain Port Expander Outputs (SW1 and SW2)
Compatible with the Serial Peripheral Interface (SPI) on CMOS MCUs

MC145149
2-524

OW SUFFIX
SOG
CASE751D

ORDERING INFORMATION
MC145149P
Plastic DIP
MC145149DW SOG Package

PIN ASSIGNMENT
lDl [1e

20

VSSI

MCI [ 2

19

PDoul1

ENB [ 3

18

VDDI

fint [ 4

17

SWI

DATA [ 5

16

OSCout

ClK [ 6

15

OSCin

fin2 [ 7

14

SW2

StRout [ 8

13

VDD2

MC2 [ 9

12

PDout2

lD2 [ 10

11

VSS2

MOTOROLA COMMUNICATIONS DEVICE DATA

BLOCK DIAGRAM

r-------~~~~--------------------------------------1~7SWI
PIN 18 = VDDI
PIN 20 = VSSI
ENS .;03_________________+- --..,
1

J-+-+--.-r---""
19 PDoutl

OSCin
OSCout .!"-_--'

" - - PLLl

~ PLL2

~------~~rr-l~--+_--------------------------~14SW2
PIN 13=VDD2
PIN 11 =VSS2

12 PDout2

DATA

MOTOROLA COMMUNICATIONS DEVICE DATA

MC145149
2-525

MAXIMUM RATINGS' (Voltages Referenced to VSS)
Parameter

Symbol
VDD
Yin, Vout

DC Supply Voltage
Input or Output Voltage (DC or Transient) except
SW1,SW2

Value
-0.5 to +10

V

-0.5 to VDD+0.5

V

-0.5 to 15

V

Input or Output Current (DC or Transient), per Pin

±10

rnA

IDD, ISS

Supply Current, VDD or VSS Pins

±30

rnA

PD

Power Dissipation, per Package t

500

mW

Tsto

Storage Temperature

-65 to +150

°c

Vout
lin,lout

Output Voltage (DC or Transient)-SW1, SW2

This device contains circuitry to protect against damage due to high static
voltages or electric fields, however, it is
advised that normal precautions be taken to avoid applications of any voltage
higher than maximum rated voltages to
this high-impedance circuil. For proper
operation, it is recommended that Yin
and Vout be constrained to the range
VSS" (VinorVout)" VDDexceptSW1
and SW2 which may range up to 15 V.

Unit

Lead Temperature (8-Second Soldering)
260
TL
• Maximum Ratings are those values beyond which damage to the device may occur.
t Power Dissipation Temperature Derating:
Plastic DIP: -12 mW/OC from 65 to 85°C
SOG Package: -7 mW/oC from 65 to 85°C

Unused inputs must always be tied to
an appropriate logic voltage level (e.g.,
either VSS or VDD). Unused outputs
should be left fioating .

°C

ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
-40°C

Voo
Symbol

Characteristic

VDD

Power Supply Voltage Range

VOL

Output Voltage
Vin=O VorVDD
10ut=0 ~A

VOH

VIL

Input Voltage
Vout=0.5 V or VDD-0.5 V
(Ail Outputs Except OSCoutl

VIH

IOL

IOL

IOH

IOL

Output Current-MC1, MC2
Vou t=2.7V
Vou t=4.6V
Vou t=8.5 V
Vou t=0.3V
Vout=O.4 V
Vou t=0.5 V
Output Current-SW1, SW2
Vout=0.3 V
Vou t=O.4 V
Vou t=0.5 V
Output Current-Other Outputs
Vout=2.7V
Vou t=4.6 V
Vou t=8.5 V
Vou t=0.3 V
Vout=O.4 V
Vou t=0.5 V

+ 85°C

Min

Max

Min

Max

Min

Max

Unit

-

3

9

3

9

3

9

V

-

0.05
0.05
0.05

-

0.05
0.05
0.05

V

o Level

3
5
9

-

0.05
0.05
0.05

1 Level

3
5
9

2.95
4.95
8.95

-

2.95
4.95
8.95

-

2.95
4.95
8.95

-

-

0.9
1.5
2.7

-

0.9
1.5
2.7

-

0.9
1.5
2.7

2.1
3.5
6.3

-

-

2.1
3.5
6.3

-

-

2.1
3.5
6.3

-

-

-0.50
-0.75
-1.25

-

-0.30
-0.50
-0.80

-

1.10
1.70
3.30

-

-

0.66
1.08
2.10

o Level

3
5
9

1 Level

3
5

9
IOH

25°C

V

-

-

-

9

-0.60
-0.90
-1.50

-

3
5
9

'1.30
1.90
3.80

-

3
5
9

0.80
1.50
3.50

-

Source

3
5
9

-0.44
-0.64
-1.30

Sink

3
5
9

0.44
0.64
1.30

Source

Sink

Sink

3
5

-

-

-

-

-

mA

-

-

-

mA

0.48
0.90
2.10

-

-

0.24
0.45
1.50

-

-0.35
-0.51
-1.00

-

-0.22
-0.36
-0.70

-

-

0.35
0.51
1.00

-

-

0.22
0.36
0.70

-

-

-

-

-

V

-

mA

-

-

lin

Input Current-DATA, CLK, ENB

9

-

±0.3

-

±0.1

-

±1.0

~

lin

Input Current-fin, OSCin

9

-

±50

-

±25

-

±22

~A

Cin

Input Capacitance

-

-

10

-

10

-

10

pF

Three-State Output Capacitance-PDout

-

-

10

-

10

-

10

pF

Cout

(continued)

MC145149
2-526

MOTOROLA COMMUNICATIONS DEVICE DATA

ELECTRICAL CHARACTERISTICS -

continued (Voltages Referenced to VSS)

Vee
Symbol

Characteristic

IDD

Quiescent Current
Vin=OVorVDD
10ut=0 IlA

IOZ

Three-State leakage Current-PDout

IOZ

Off-State leakage Current-SW1, SW2

Vout=O V or 9 V
Vout=9 V

-40°C

25°C

+85°C

V

Min

Max

Min

Max

Min

Max

Unit

3
5
9

BOO
1200
1600

-

BOO
1200
1600

-

1600
2400
3200

IlA

9

-

±0.3

-

±0.1

±3.0

IlA

9

-

0.3

-

0.1

-

3.0

IlA

Vee
V

Min

Max

Unit

-

115
60
40

ns

SWITCHING CHARACTERISTICS (TA = 25°C, Cl = 50 pF)

Symbol

Characteristic

Figure #

trlH

Output Rise Time, MC1 and MC2

1,6

3
5
9

-

trHl

Output Fall Time, MC1 and MC2

1,6

3
5
9

-

-

60
34
30

ns

trlH,
trHl

Output Rise and Fall Time, lD and SIRout

1,6

3
5
9

-

140
BO
60

ns

tplH,
tpHl

Propagation Delay Time, fin to MC1 or MC2

2,6

3
5
9

-

ns

-

-

125
BO
50

tsu

Setup Time, DATA to ClK

3

3
5
9

30
20
1B

-

ns

tsu

Setup Time, ClK to ENB

3

3
5
9

70
32
25

-

ns

-

-

Hold Time, ClK to DATA

3

3
5
9

12
12
15

-

ns

tree

Recovery Time, ENB to ClK

3

3
5
9

5
10
20

-

ns

tr,tf

Input Rise and Fall Times, Any Input

4

3
5
9

-

-

5
2
0.5

Ils

3
5
9

40
35
25

-

ns

th

tw

Input Pulse Width, ENB and ClK

MOTOROLA COMMUNICATIONS DEVICE DATA

5

-

-

MC145149

2-527

FREQUENCY CHARACTERISTICS (Voltages Relerenced to VSS, CL = 50 pF, Input tr = tl = 10 ns unless otherwise indicated)
Symbol

Parameter

Test Conditions

Input Frequency
(fin, aSCin)

Ii

Vee
V

-40°C
Max

-

6

R;;,a, A;;,O, N;;,a
Vin=500 mVp·p
ac·coupled sine wave

3
9

-

R;;,a, A;;,O, N;;,a
Vin=VOO to VSS
dc·coupled square wave

3

-

5

5

-

9

25°C

Min

Min

Min

Max

Unit

-

6

MHz

-

15
15

-

15
15

-

6

-

15
15

-

6

15
15

-

6

-

15
15

+85°C

Max

15
15

-

6

MHz

SWITCHING WAVEFORMS

r---VDD
tTlH

trHl

ANY
OUTPUT

MC
Figure 2.

Figure 1.

DATA
Vss
tsu

ClK

tr

VSS

ANY
INPUT

ENS
VSS

Figure 4.

PREVIOUS DATA
LATCHED

Figure 3.

ENB,

cl0"":s-o-OI<-0-----

~L VDD

-_-_tw_-_-------.:
.....

OUTPUT
DEVICE
UNDER
TEST

Vss

Figure 5.

MC145149

2·528

Figure 6.

MOTOROLA COMMUNICATIONS DEVICE DATA

PIN DESCRIPTIONS
INPUTS
OSCln, OSCout
Reference Oscillator Input/Output (Pins 15,16)
These pins form a reference oscillator when connected
to terminals of an external parallel-resonant crystal.
Frequency-setting capacitors of appropriate value must be
connected from OSCin and OSCout to ground.
OSCin may also serve as input for an externally-generated
reference signal. The signal is typically ac-coupled to OSCin,
but for signals with CMOS logic levels, de coupling may be
used. When used with an external reference, OSCout should
be left open.
fin1, fin2
Frequency Inputs (Pins 4, 7)
Input frequency from an external VCO output. Each
rising-edge signal on fin1 decrements the N counter, and
when appropriate, the A counter of PLL 1. Similarly, fin2
decrements the counters of PLL 2.
These inputs have inverters biased on the linear region
which allows ac coupling for signals as low as 500 mVp-p.
With square wave signals which swing from VSS to VDD,
dc coupling may be used.
DATA,CLK
Data, Clock Inputs (Pins 5, 6)
Shift register data and clock inputs. Each low-to-high
transition on the clock pin shifts one bit of data into the on-chip
shift registers. Refer to Figure 7 for the following discussion.
The last bit entered is a steering bit that determines which
set of latches are activated. A logic high selects the latches
for PLL 1. A logic low selects PLL 2.
The second-to-Iast bit controls the appropriate port
expander output, SW1 or SW2. A logic low forces the output
low. A logic high forces the outputto the high-impedance state.
The third-to-Iast bit determines which storage latch is
activated. A logic low selects the +A and +N counter latches.
A logic high selects the reference counter latch.
When writing to either set of +A and ... N counter latches,
20 clock cycles are typically used. However, if a byte-oriented
MCU is utilized, 24 clock cycles may be used with the first
4 bits being "Don't Care."
When writing to either reference counter latch, 17 clock
cycles are typically used. However, if a byte-Oriented MCU
is utilized, 24 clock cycles may be used with the first 7 bits
being "Don't Care".
ENB
Latch Enable Input (Pin 3)
A positive pulse on this input transfers data from the shift
registers to the selected latches, as determined by the control
and steering data bits. A logic low level on this pin allows the
user to shift data into the shift registers without affecting the
data in the latches or counters. Enable is normally held low
and is pulsed high to transfer data into the latches.
OUTPUTS
PDout1, PDout2
Single-Ended Phase Detector Outputs (Pins 19, 12)
Each single-ended (threlHltate) phase detector output
produces a loop error signal that is used with a loop filter to
control a VCO (see Figure 8).
Frequency fV>fR or fV Leading: Negative Pulses
Frequency fVR

T/R

4 3 2 1282726
25
24
6
7
23
22
21
20
10
11
19
12 13 1415 16 1718

v

N9

zzzzzzz

NIl
Nl0

tv

N8

NO

N7

Nl

N6

N2

N5

N3

N4

Plastic DIP
SOG Package
PLCC Package

~$lg>~g~~

RAO
RAI
RA2
R
v

aSCout

ORDERING INFORMATION
MC145151P2
MC145151DW2
MC145151 FN2

PLCC

aSCin

VOO

FN SUFFIX
PLCC
CASE 776

The PLCC (FN suffix)
package will be phased
out for this device and is
NOT RECOMMENDED
FOR NEW DESIGNS.

PIN ASSIGNMENTS

fin

DWSUFFIX
SOG
CASE 751F

NO

MOTOROLA COMMUNICATIONS DEVICE DATA

....-

N

c<:>

~

1.0

CD

NIl
Nl0
N13
N12

T/R
N9
N8

r-

MC145151-2
2-535

BLOCK DIAGRAM
RA2
RA1
RAO

OSCout

14 x 8 ROM REFERENCE DECODER
14

LD

14·BIT + RCOUNTER

OSCin

PDout
14-BIT + NCOUNTER

W

14

R
TIR

tv
NOTE: NO-N13 inputs and Inputs RAO, RA 1, and RA2 have pull·up resistors that are not shown.

T/R

PIN DESCRIPTIONS
INPUT PINS
fin
Frequency Input (Pin 1)
Input to the + N portion of the synthesizer. fin is typically
derived from loop VCO and is ac coupled into the device. For
larger amplitude signals (standard CMOS logic levels) dc
coupling may be used.
RAD-RA2
Reference Address Inputs (Pins 5, 6, 7)
These three inputs establish a code defining one of eight
possible divide values for the total reference divider, as
defined by the table below.
Pull-up resistors ensure that inputs left open remain at a
logic 1 and require only a SPST switch to alter data to the
zero state.

RA2

RA1

RAO

Totel
Divide
Value

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

8
128
256
512
1024
2048
2410
8192

Reference Address Code

ND-N11
N Counter Programming Inputs (Pins 11-20, 22-25)
These inputs provide the data that is preset into the + N
counter when it reaches the count of zero. NO is the least
significant and N13 is the most significant. Pull-up resistors
ensure that inputs left open remain at a logic 1 and require
only a SPST switch to alter data to the zero state.

MC145151-2
2-536

TransmiUReceive Offset Adder Input (Pin 21)
This input controls the offset added to the data provided
at the N inputs. This is normally used for offsetting the VCO
frequency by an amount equal to the IF frequency of the
transceiver. This offset is fixed at 856 when T/A is low and
gives no offset when T/A is high. A pull-up resistor ensures
that no connection will appear as a logic 1 causing no offset
addition.
OSCin, OSCout
Reference Oscillator InpuUOutput (Pins 27, 26)
These pins form an on-chip reference oscillator when
connected to terminals of an external parallel resonant
crystal. Frequency setting capacitors of appropriate value
must be connected from OSCin to ground and OSCout to
ground. OSCin may also serve as the input for an
externally-generated reference signal. This signal is typically
ac coupled to OSCin, but for larger amplitude signals
(standard CMOS logic levels) dc coupling may also be used.
In the external reference mode, no connection is required
to OSCout.
OUTPUT PINS
PDout
Phase Detector A Output (Pin 4)
Three-state output of phase detector for use as loop error
signal. Double-ended outputs are also available for this
purpose (see cjlv and cjlA).
Frequency Iv > fA or fV Leading: Negative Pulses
Frequency fV < fA or fV Lagging: Positive Pulses
Frequency fV = fA and Phase Coincidence: HighImpedance State

MOTOAOLA COMMUNICATIONS DEVICE DATA

connected to the phase detector input. With this output
available. the ... N counter can be used independently.

4lR.41V
Phase Detector B Outputs (Pins 8. 9)
These phase detector outputs can be combined externally
for a loop-error signal. A single-ended output is also available
for this purpose (see PDout).
If frequency fV is greater than fR or if the phase of fV is
leading. then error information is provided by 4lv pulsing low.
4lR remains essentially high.
If the frequency fV is less than fR or if the phase of fV is
lagging. then error information is provided by 4lR pulsing low.
4lv remains essentially high.
If the frequency of fV fR and both are in phase. then both
4lv and 4lR remain high except for a small minimum time
period when both pulse low in phase.

LD
Lock Detector Output (Pin 28)
Essentially a high level when loop is locked (fR. fV of same
phase and frequency). Pulses low when loop is out of lock.
POWER SUPPLY PINS
VDD
Positive Power Supply (Pin 3)
The positive power supply potential. This pin may range
from + 3 to + 9 V with respect to VSS.

=

VSS
Negative Power Supply (Pin 2)
The most negative supply potential. This pin is usually
ground.

tv

N Counter Output (Pin 10)
This is the buffered output olthe ... N counter that is intemally

TYPICAL APPLICATIONS
2.04BMHz

D
OSCin

OSCout
VOLTAGE
PDout I-WIr-_-.. CONTROLLED
OSCILLATOR

MCI45151·2

5-5.5 MHz

I
01110001000=5MHz
10101111100=5.5 MHz

Figure 1. 5 MHz to 5.5 MHz Local Oscillator Channel Spacing

=1 kHz

LOCK DETECT SIGNAL

OSCout RA2

I

RAI

RAO

LD

1----1 OSCin
VDD
VSS

MCI45151·2

TRANSMIT: 440.0 - 470.0 MHz
RECEIVE: 41 B.6 - 448.6 MHz
(25 kHz STEPS)

tv
PDout
R

tv

10.0417 MHz
(ON·CHIPOSC.
OPTIONAL)
RECEIVE

a

o

TRANSMIT
.L (ADDS 856 TO
... NVALUE)

CHANNEL PROGRAMMING
... N= 2284 TD 3484

NOTES:
1. fR = 4.1667 kHz; ... R = 2410; 21.4·MHz low side injection during receive.
2. Frequency values shown are for the 440-470 MHz band. Similar implementation applies to \he 406-440 MHz band. For
470-512 MHz. consider reference oscillator frequency X9 for mixer Injection signal (90.3750 MHz).

Figure 2. Synthesizer for Land Mobile Radio UHF Bands

Data Sheet Continued on Page 2-556
MOTOROLA COMMUNICATIONS DEVICE DATA

MC145151-2
2-537

MOTOROLA

-

SEMICONDUCTOR
TECHNICAL DATA

MC145152·2

Parallel.lnput PLL Frequency
Synthesizer
Interfaces with Dual-Modulus Prescalers
The MC145152-2 is programmed by sixteen parallel inputs for the Nand
A counters and three input lines for the R counter. The device features consist
of a reference oscillator, selectable-reference divider, two-output phase
detector, 1O-bit programmable divide-by-N counter, and 6-bit programmable
+ A counter.
The MC145152-2 is an improved-performance drop-in replacement for the
MC145152-1. Power consumption has decreased and ESD and latch-up
performance have improved.
• Low Power Consumption Through Use of CMOS Technology
• 3.0 to 9.0 V Supply Range
• On- or Off-Chip Reference Oscillator Operation
• Lock Detect Signal
• Dual Modulus/Parallel Programming
• 8 User-Selectable + R Values: 8, 64, 128, 256, 512, 1024, 1160, 2048
• + N Range = 3 to 1023, + A Range = 0 to 63
• Chip Complexity: 8000 FETs or 2000 Equivalent Gates

PLASTtCDtP

1·

28

LO

VSS

2

27

OSCin

VOD

3

26

OSCout

RAO

4

25

A4

RA1

5

24

AS

RA2

6

23

AO

R

7

22

A2

R I---Jv I---Jv

3

16

OSCout

v

R

4

15

REFout

R

VDD

5

14

SW2

PDout

6

13 ] SW1

VSS

7

12 ] ENB

lD

8

~n

9

PLCC PACKAGE

20

RAO

19

OSCin

~
a:

;:;:

3

18

OSCout

3

2

4

17

REFout

VDD

5

16

PDout

6

VSS

11 ] DATA
10 ] ClK

1·

a:

.S

0

z

~

0

UJ

a: 0

1 20 19
18

OSCout

NC

17

REFout

15

SW2

16

SW2

7

14

SW1

SW1

NC

8

13

ENB

ENB

lD

9

12

DATA

~n

10

11

ClK

9

c

--'

•

10

11

12

~

0

'"--'

z

0

~

i5

NC = NO CONNECTION

MC145155-2
2-542

MOTOROLA COMMUNICATIONS DEVICE DATA

BLOCK DIAGRAM
RA2

RAI
RAO

14 x8 ROM REFERENCE DECODER
14

OSCout

LD

14-BIT + RCOUNTER

OSCin

PDout
REFout
fin

14-BIT + NCOUNTER
 fR or fV Leading: Negative Pulses
Frequency fV < fR or fV Lagging: Positive Pulses
Frequency fV = fR and Phase Coincidence:
High-Impedance State
$R,$V
Phase Detector B Outputs
These phase detector outputs can be combined externally
for a loop-error signal. A single-ended output is also available
for this purpose (see PDout).
If frequency fV is greater than fR or if the phase of fV is
leading, then error information is provided by $V pulsing low.
$R remains essentially high.
If the frequency fV is less than fR or if the phase of fV is
lagging, then error information is provided by $R pulsing low.
$V remains essentially high.
If the frequency of fV = fR and both are in phase, then both
$V and $R remain high except for a small minimum time
period when both pulse low in phase.

SW1,SW2
Band Switch Outputs
SW1 and SW2 provide latched open-drain outputs
corresponding to data bits numbers one and two. These
outputs can be tied through external resistors to voltages as
high as 15 Vdc, independent of the VDD supply voltage.
These are typically used for band switch functions. A logic
1 causes the output to assume a high-impedance state, while
a logic 0 causes the output to be low.
REFout
Buffered Reference Oscillator Output
Buffered output of on-chip reference oscillator or externally
provided reference-input signal.
POWER SUPPLY PINS
VDD
Positive Power Supply
The positive power supply potential. This pin may range
from +3 to +9 V with respect to VSS.
VSS
Negative Power Supply
The most negative supply potential. This pin is usually
ground.

LD
Lock Detector Output
Essentially a high level when loop is locked (fR, fV of same
phase and frequency). LD pulses low when loop is out of lock.

TYPICAL APPLICATIONS

UHFNHF
TUNER OR

CATV
FRONT END

LED DISPLAY

Figure 1. Microprocessor-Controlled Tv/CATV Tuning System with Serial Interface

MC145155-2
2-544

MOTOROLA COMMUNICATIONS DEVICE DATA

TO

FM
OSC

>----41--. AMlFM

OSCILLATORS

AM

OSC-------~~

TO DISPLAY

Figure 2. AMlFM Radio Synthesizer

Data Sheet Continued on Page 2-556
MOTOROLA COMMUNICATIONS DEVICE DATA

MC145155-2
2-545

MOTOROLA

-

SEMICONDUCTOR
TECHNICAL DATA

MC145156-2

Serial-Input PLL Frequency
Synthesizer

~-

Interfaces with Dual-Modulus Prescalers
The MC145156-2 is programmed by a clocked, serial input, 19-bit data
stream. The device features consist of a reference oscillator, selectablereference divider, digital-phase detector, 10-bit programmable divide-by-N
counter, 7-bit programmable divide-by-A counter, and the necessary shift
register and latch circuitry for accepting serial input data.
The MC145156-2 is an improved-performance drop-in replacement for
the MC145156-1. Power consumption has decreased and ESD and latch-up
performance have improved.
• Low Power Consumption Through Use of CMOS Technology
• 3.0 to 9.0 V Supply Range
• On- or Off-Chip Reference Oscillator Operation with Buffered Output
• Compatible with the Serial Peripheral Interface (SPI) on CMOS MCUs
• Lock Detect Signal
• Two Open-Drain Switch Outputs
• Dual Modulus/Serial Programming
• 8 User-Selectable + R Values: 8, 64, 128, 256, 640, 1000, 1024, 2048
• + N Range = 3 to 1023, + A Range = 0 to 127
• "Linearized" Digital Phase Detector Enhances Transfer Function Linearity
• Two Error Signal Options: Single Ended (Three-State) or Double Ended
• Chip Complexity: 6504 FETs or 1626 Equivalent Gates

~.

•

PSUFFIX
PLASTIC
CASE 738

DWSUFFIX
SOG
CASE 751D

FN SUFFIX
PLCC
CASEn5

ORDERING INFORMATION
MC145156P2
MC145156DW2
MC145156FN2

Plastic DIP
SOG Package
PLCC Package

The PLCC (FN suffix)
package will be phased
out for this device and is
NOT RECOMMENDED
FOR NEW DESIGNS.

PIN ASSIGNMENTS
PLASTIC DIP and
SOGPACKAGE

MC145156-2
2-546

RAI

1-

20 ) RAe

RA2

2

19

W 3

18

+R

4

17

PeSCout
P REFout

VOO

5

16

~

~

~
~

PLCC PACKAGE

....> ~

eSCln

3
+R

4

TEST

VOO

5

SW2

POout

6

SWI

VSS

7

ENB

MC

8

POout

6

15

Vss

7

14

MC

8

13

LD

9

12

~
~

10

11

P elK

DATA

2

~ ~ a~
1

•

20
eSCout
REFout
16

TEST
SW2

9 10

11

12

c

""

~

....I

~

....I

0

~

SWI
In

Z

w

MOTOROLA COMMUNICATIONS DEVICE DATA

BLOCK DIAGRAM
RA2
RA 1

12 x 8 ROM REFERENCE DECODER

RAO

12
12·BIT + R COUNTER

OSCin

lD

OSCout
REFout

PDout

MC

~n

V
R

SW2

VDD
ENB

SWI

DATA
ClK

\-+ ACOUNTER BITS-\-- +NCOUNTER BITs-----J

PIN DESCRIPTIONS
INPUT PINS
fin
Frequency Input (Pin 10)
Input to the positive edge triggered + Nand + A counters.
fin is typically derived from a dual-modulus prescaler and is
ac coupled into the device. For larger amplitude signals
(standard CMOS logic levels) dc coupling may be used.
RAO, RA1, RA2
Reference Address Inputs (Pins 20,1,2)
These three inputs establish a code defining one of eight
possible divide values for the total reference divider, as
defined by the table below:
Reference Address Code
RA2

RAt

RAO

a
a
a
a

a
a

a

1
1
1
1

1
1

a
a
1
1

t

a
1

a
1

a
1

Total
Divide
Value

8
64
128
256
640
1000
1024
2048

CLK, DATA
Shift Register Clock, Serial Data Inputs (Pins 11, 12)
Each low-to-high transition clocks one bit into the on-chip
19-bit shift register. The Data input provides programming
information for the 10-bit + N counter, the 7-bit + A counter,
and the two switch signals SWI and SW2. The entry format
is as follows:

MOTOROLA COMMUNICATIONS DEVICE DATA

rn
.....

'"

"'",
rnrn
::;; .....

c(

c(z

·1·

-I- ·1·

L

'"~
z

i·

LAST DATA BIT IN (BIT NO. 19)
FIRST DATA BIT IN (BIT NO.

f: ~

t;

t

1)~

ENB
Latch Enable Input (Pin 13)
When high (1), ENB transfers the contents of the shift
register into the latches, and to the programmable counter
inputs, and the switch outputs SWI and SW2. When low (0),
ENS inhibits the above action and thus allows changes to
be made in the shift register data without affecting the counter
programming and switch outputs. An on-chip pull-up
establishes a continuously high level for ENS when no
extemal signal is applied. ENB is normally low and is pulsed
high to transfer data to the latches.
OSCin, OSCout
Reference Oscillator Input/Output (Pins 19, 18)
These pins form an on-chip reference oscillator when
connected to terminals of an external parallel resonant
crystal. Frequency setting capacitors of appropriate value
must be connected from OSCin to ground and OSCout to
ground. OSCin may also serve as the input for an
externally-generated reference signal. This signal is typically
ac coupled to OSCin, but for larger amplitude Signals
(standard CMOS logic levels) dc coupling may also be used.
In the external reference mode, no connection is required
to OSCout.

MC145156-2
2-547

TEST
Factory Test Input (Pin 16)
Used in manufacturing. Must be left open or tied to VSS.
OUTPUT PINS

=

PDout
.
Phase Detector A Output (Pin 6)
Three-state output of phase detector for use as loop error
signal. Double-ended outputs are also available for this
purpose (see eIlv and eIlR).
Frequency fV > fR or Iv Leading: Negative Pulses
Frequency fV < fR or Iv Lagging: Positive Pulses
Frequency fV fR and Phase Coincidence: HighImpedance State

=

eIlR,eIlV
Phase Detector B Outputs (Pins 4, 3)
These phase detector outputs can be combined extemally
for a loop-error signal. A single-ended output is also available
for this purpose (see PDout).
If frequency Iv is greater than fR or if the phase of Iv is
leading, then error information is provided by eIlv pulsing low.
eIlR remains essentially high.
If the frequency fV is less than fR or if the phase of Iv is
lagging, then error information is provided by eIlR pulsing low.
eIlv remains essentially high.
If the frequency of fV = fR and both are in phase, then both
eIlv and eIlR remain high except for a small minimum time
period when both pulse low in phase.
MC
Dual-Modulus Prescale Control Output (Pin 8)
Signal generated by the on-chip control logic circuitry for
contrOlling an extemal dual-modulus prescaler. The MC level
will be low at the beginning of a count cycle and will remain
low until the ... A counter has counted down from its
programmed value. At this time, MC goes high and remains
high until the + N counter has counted the rest of the way
down from its programmed value (N - A additional counts

MC145156-2
2-548

since both ... Nand ... A are counting down during the first
portion of the cycle). MC is then set back low, the counters
preset to their respective programmed values, and the above
sequence repeated. This provides for a total programmable
divide value (NT) N • P + A where P and P + 1 represent
the dual-modulus prescaler divide values respectively for
high and low MC levels, N the number programmed into the
... N counter, and A the number programmed into the ... A
counter.
LD
Lock Detector Output (Pin 9)
Essentially a high level when loop is locked (fR, fV of same
phase and frequency). LD pulses low when loop is out of lock.
SW1,SW2
Band Switch Outputs (Pins 14, 15)
SW1 and SW2 provide latched open-drain outputs
corresponding to data bits numbers one and two. These
outputs can be tied through external resistors to voltages as
high as 15 Vdc, independent of the VDD supply Voltage.
These are typically used for band switch functions. A logic
1 causes the output to assume a high-impedance state, while
a logic 0 causes the output to be low.
REFout
Buffered Reference Oscillator Output (Pin 17)
Buffered output of on-chip reference oscillator or extemally
provided reference-input signal.
POWER SUPPLY PINS
VDD
Positive Power Supply (Pin 5)
The positive power supply potential. This pin may range
from +3 to +9 V with respect to VSS.
VSS
Negative Power Supply (Pin 7)
The most negative supply potential. This pin is usually
ground.

MOTOROLA COMMUNICATIONS DEVICE DATA

TYPICAL APPLICATIONS
+12V
LOCK DETECT SIGNAL

3.2 MHz

D

+12V

I
+V

OSCin

OSCout

..........----FMB+

' - - - - - - - AM B+
OPTIONAL
LOOP
ERROR SIGNAL
oIlRI-....I\Io./lr--.....-l

RA2 RA1 RAO LD

PDout

VOD
VSS

MC145156-2

VCO

oIlvl-....I\Io./lr--........-l

NOTE:
For AM: channel spacing =5 kHz, + R =+ 640 (code 100)
For FM: channel spacing = 25 kHz, + R = + 128 (code 010)

Figure 1. AMlFM Radio Broadcast Synthesizer

3.2MHzl~)

D
+V

VCORANGE
NAV: 97.300-107.250 MHz
COM·T: 118.000-135.975 MHz
COM·R: 139.400-157.375 MHz

OSCin OSCout
PDout

VDD
VSS

MC145156-2

oIlR 1---J\,i'l/lr---4t-1
VCO
oIlv I---J\,i'l/lr-_t-I

RIT

NOTES:
1. For NAV: fR =50 kHz, + R =64 using 10.7-MHz lowslde injection, Ntotal =1946-2145.
For COM-T: fR =25 kHz, + R =128, Nto1a1 =472Q-5439.
For COM·R: fR =25 kHz, + R =128, using 21.4-MHz highslde injection, Nto1a1 =5576-6295.
2. A+32133 dual modulus approach Is provided by substituting an MC12015 forthe MC12016. The devices are pin equivalent
3. A 6.4·MHz oscillatorcrys1a1 can be used by selecting + R = 128 (code 010) for NAV and + R = 256 (code 011) for COM.
4. MC12013 + MC10131 combination may also be used to form the + 40/41 prescaler.

Figure 2. Avionics Navigation or Communication Synthesizer

Data Sheet Continued on Page 2-556
MOTOROLA COMMUNICATIONS DEVICE DATA

MC145156-2
2-549

MOTOROLA

-

SEMICONDUCTOR
TECHNICAL DATA

MC145157-2

,.
16.
2.

Serial-Input PLL Frequency
Synthesizer
Interfaces with Single-Modulus Prescalers
The MC145157-2 has a fully programmable 14-bit reference counter, as
well as a fully programmable + N counter. The counters are programmed
serially through a common data input and latched Into the appropriate counter latch, according to the last data bit (control bit) entered.
The MC145157-2 Is an improved-performance drop-In replacement for the
MC145157-1. Power consumption has decreased and ESD and latch-up
performance have improved.
• Low Power Consumption Through Use of CMOS Technology
• 3.0 to 9.0 V Supply Range
• Fully Programmable Reference and + N Counters
• + R Range =3 to 16383
• + N Range =3 to 16383
• fV and fR Outputs
• Lock Detect Signal
• Compatible with the Serial Peripheral Interface (SPI) on CMOS MCUs
• "Linearized" Digital Phase Detector
• Single-Ended (Three-State) or Double-Ended Phase Detector Outputs
• Chip Complexity: 6504 FETs or 1626 Equivalent Gates

PSUFFIX
PLASTIC
CASE 648

DWSUFFIX
SOG
CASE 751G

FNSUFFIX
PLCC
CASE 775

ORDERING INFORMATION
MC145157P2
MC145157DW2
MC145157FN2

Plastic DIP
SOG Package
PLCC Package

The PLCC (FN suffix)
package will be phased
out for this device and is
NOT RECOMMENDED
FOR NEW DESIGNS.

PIN ASSIGNMENTS

PLASTIC DIP and
SOGPACKAGE

PLCC PACKAGE
"S
0

0

OSCin

"'A

'i>V

.5

0

en

:3

3

2

0

AEFout

........>
II:

0

z

1 20 19
18

•

IA
PDout
VSS

SlRout
DATA

fA

16

NC

15

ENB

9 10
c
....

.§

11
0

z

14
12 13
~

0

AEFout

17

SlRout
ENB

~

~

NC = NO CONNECTION

MC145157-2
2-550

MOTOROLA COMMUNICATIONS DEVICE DATA

BLOCK DIAGRAM

14-BITSHIFT REGISTER
14
ENB

fR

REFERENCE COUNTER LATCH
lD

14
14·BIT + RCOUNTER

OSCin
OSCout

PDout

REFout

ejlv

14-BIT + NCOUNTER

fin

ejlR
14

+ N COUNTER LATCH

tv

14

DATA

14-BIT SHIFT REGISTER

SJRout

ClK

the user to change the data in the shift registers without
affecting the counters. ENB is normally low and is pulsed high
to transfer data to the latches.

PIN DESCRIPTIONS
INPUT PINS
fin
Frequency Input
Input frequency from VCO output. A rising edge signal on
this input decrements the + N counter. This input has an
inverter biased in the linear region to allow use with ac coupled
signals as low as 500 mVp-p. For larger amplitude signals
(standard CMOS logic levels) dc coupling may be used.
ClK,DATA
Shift Clock, Serial Data Inputs
Each low-to-high transition of the clock shifts one bit of data
into the on-chip shift registers. The last data bit entered
determines which counter storage latch is activated; a logic
1 selects the reference counter latch and a logic 0 selects the
+ N counter latch. The entry format is as follows:

I~I~IIIIIIIII

1

FIRST DATA BIT INTO SHIFT REGISTER ---..J

ENB
Latch Enable Input
A logic high on this pin latches the data from the shift register
into the reference divider or + N latches depending on the
control bit. The reference divider latches are activated if the
control bit is at a logic high and the + N latches are activated
if the control bit is at a logic low. A logic low on this pin allows

MOTOROLA COMMUNICATIONS DEVICE DATA

OSCin, OSCout
Reference Oscillator Input/Output
These pins form an on-chip reference oscillator when
connected to terminals of an external parallel resonant
crystal. Frequency setting capacitors of appropriate value
must be connected from OSCin to ground and OSCout to
ground. OSCin may also serve as the input for an
externally-generated reference signal. This signal is typically
ac coupled to OSCin, but for larger amplitude signals
(standard CMOS logic levels) dc coupling may also be used.
In the external reference mode, no connection is required
to OSCout.
OUTPUT PINS
PDout
Single-Ended Phase Detector A Output
This single-ended (three-state) phase detector output
produces a loop error signal that is used with a loop filter to
control a VCO.
Frequency fV > fR or fV Leading: Negative Pulses
Frequency fV < fR or fV Lagging: Positive Pulses
Frequency fV fR and Phase Coincidence: HighImpedance State

=

MC145157-2
2-551

tPR,tPV
Double-Ended Phase Detector B Outputs
These outputs can be combined externally for a loop-error
signal. A single-ended output is also available forthis purpose
(see PDout).
If frequency fV is greater than fR or if the phase of fV is
leading, then error information is provided by tPV pulsing low.
tPR remains essentially high.
If the frequency fV is less than fR or if the phase of fV is
lagging, then error information is provided by tPR pulsing low.
tPV remains essentially high.
If the frequency of fV = fR and both are in phase, then both
tPV and tPR remain high except for a small minimum time
period when both pulse low in phase.
fR,fv
R Counter Output, N Counter Output
Buffered, divided reference and fin frequency outputs. The
fR and fV outputs are connected internally to the + Rand +
N counter outputs respectively, allowing the counters to be
used independently, as well as monitoring the phase detector
inputs.

REFout
Buffered Reference Oscillator Output
This output can be used as a second local oscillator,
reference oscillator to another frequency synthesizer, or as
the system clock to a microprocessor controller.
S/Rout
Shift Register Output
This output can be connected to an external shift register
to provide band switching, control information, and counter
programming code checking.
POWER SUPPLY PINS
VDD
Positive Power Supply
The positive power supply potential. This pin may range
.from +3 to +9 V with respect to VSS.
VSS
Negative Power Supply
The most negative supply potential. This pin is usually
ground.

LD
Lock Detector Output
Thib output is essentially at a high level when the loop is
locked (fR, fV of same phase and frequency), and pulses low
when loop is out of lock.

Data Sheet Continued on Page 2-556
MC145157-2
2-552

MOTOROLA COMMUNICATIONS DEVICE DATA

MOTOROLA

-

SEMICONDUCTOR
TECHNICAL DATA

MC145158-2

Serial-Input PLL Frequency
Synthesizer

•1

16
1.

Interfaces with Dual-Modulus Prescalers
The MC145158-2 has a fully programmable 14-bit reference counter, as
well as fully programmable + Nand + A counters. The counters are programmed serially through a common data input and latched into the
appropriate counter latch, according to the last data bit (control bit) entered.
The MC145158-2 is an improved-performance drop-in replacement for
the MC145158-1. Power consumption has decreased and ESD and latch-up
performance have improved.
•
•
•
•
•
•
•
•
•
•
•
•

Low Power Consumption Through Use of CMOS Technology
3.0 to 9.0 V Supply Range
Fully Programmable Reference and + N Counters
+RRange=3t016383
+NRange=3t01023
Dual Modulus Capability; + A Range = 0 to 127
fV and fR Outputs
Lock Detect Signal
Compatible with the Serial Peripheral Interface (SPI) on CMOS MCUs
"Linearized" Digital Phase Detector
Single-Ended (Three-State) or Double-Ended Phase Detector Outputs
Chip Complexity: 6504 FETs or 1626 Equivalent Gates

OSCin

1-

16

~ 
II:

20 19
18

REFout

VDD

5

17

fR

NC

6

16

NC

PDout

7

15

MC

VSS

8

14
12 13

9

10

11

c
.....

~

0

z

:s0

ENB

>!i
~

NC = NO CONNECTION

MOTOROLA COMMUNICATIONS DEVICE DATA

MC145158-2
2·553

BLOCK DIAGRAM

14-BIT SHIFT REGISTER
14
ENB ------f--~'__I

REFERENCE COUNTER LATCH

lD

14
14-BIT + R COUNTER

OSCin
OSCOUI ----'------,-..

PDOUI

REFoul ----u<...

DATA
" - - - MC

ClK

-1~==~---L--=======:.J--=======::J
PIN DESCRIPTIONS

I---- + A - - - f .I"'.- - + N -----+1·1

INPUT PINS
fin
Frequency Input
Input frequency from VCO output A rising edge signal on
this input decrements the + A and + N counters_ This input
has an inverter biased in the linear region to allow use with
ac coupled signals as low as 500 mVp-p_ For larger amplitude
signals (standard CMOS logic levels) dc coupling may be
used_
ClK,DATA
Shift Clock, Serial Data Inputs
Each low-to-high transition of the ClK shifts one bit of data
into the on-chip shift registers_ The last data bit entered
determines which counter storage latch is activated; a logic
1 selects the reference counter latch and a logic 0 selects the
+ A, + N counter latch_ The data entry fomnat is as follows:

-'
0

g:

ID

z ~

0

u

IDID

ID

::E-'

::E

en

en en

,--.1

FIRST DATA BIT INTO SHIFT REGISTER

ENB
latch Enable Input
A logic high on this pin latches the data from the shift register
into the reference divider or + N, + A latches depending on
the control bit The reference divider latches are activated if
the control bit is at a logic high and the + N, + A latches are
activated if the control bit is at a logic low: A logic low on this
pin allows the user to change the data in the shift registers
without affecting the counters_ ENB is normally low and is
pulsed high to transfer data to the latches_
OSCin, OSCout
Reference Oscillator Input/Output
These pins form an on-chip reference oscillator when
connected to terminals of an external parallel resonant crystal.
Frequency setting capacitors of appropriate value must be
connected from OSCin to ground and OSCout to ground_
OSCin may also serve as the inputfor an externally-generated
reference signal_ This signal is typically ac coupled to OSCin,
but for larger amplitude signals (standard CMOS logic levels)
dc coupling may also be used_ In the external reference mode,
no connection is required to OSCout-

MC145158·2
2·554

MOTOROLA COMMUNICATIONS DEVICE DATA

OUTPUT PINS
PDout
Phase Detector A Output
This single ended (three-state) phase detector output
produces a loop error signal that is used with a loop filter to
control a VCO.
Frequency fV > fR or fV Leading: Negative Pulses
Frequency fV < fR or fV Lagging: Positive Pulses
Frequency fV fR and Phase Coincidence: HighImpedance State

=

cjlR,cjlV
Phase Detector B Outputs
Double-ended phase detector outputs. These outputs can
be combined externally for a loop-error signal. A single-ended
output is also available for this purpose (see PDout).
If frequency fV is greater than fR or if the phase of fV is
leading, then error information is provided by cjlv pulsing low.
cjlR remains essentially high.
If the frequency fV is less than fR or if the phase of fV is
lagging, then error information is provided by cjlR pulsing low.
cjlv remains essentially high.
If the frequency of fV fR and both are in phase, then both
cjlv and cjlR remain high except for a small minimum time
period when both pulse 10.." in phase.

=

MC
Dual-Modulus Prescale Control Output
This output generates a signal by the on-chip control logic
circuitry for contrOlling an external dual-modulus prescaler.
The MC level is low at the beginning of a count cycle and
remains low until the + A counter has counted down from its
programmed value. At this time, MC goes high and remains
high until the + N counter has counted the rest olthe way down
from its programmed value (N - A additional counts since both
+ Nand + A are counting down during the first portion of the
cycle). MC is then set back low, the counters preset to their
respective programmed values, and the above sequence
repeated. This provides for a total programmable divide value

MOTOROLA COMMUNICATIONS DEVICE DATA

(NT) = N • P + A where P and P + 1 representthe dual-modulus
prescaler divide values respectively for high and low modulus
control levels, N the number programmed into the + N counter,
and A the number programmed into the + A counter. Note that
when a prescaler is needed, the dual-modulus version offers
a distinct advantage. The dual·modulus prescaler allows a
higher reference frequency at the phase detector input,
increasing system performance capability, and simplifying the
loop filter design.
fR,tv
R Counter Output, N Counter Output
~uffered, divided reference and fin frequency outputs. The
fR and fV outputs are connected internally to the + Rand
+ N counter outputs respectively, allowing the counters to be
used independently, as well as monitoring the phase detector
inputs.
LD
Lock Detector Output
This output is essentially at a high level when the loop is
locked (fR, fV of same phase and frequency), and pulses low
when loop is out of lock.
REFout
Buffered Reference Oscillator Output
This output can be used as a second local oscillator,
reference oscillator to another frequency synthesizer, or as
the system clock to a microprocessor controller.
POWER SUPPLY PINS
VDD
Positive Power Supply
The positive power supply potential. This pin may range
from + 3 to + 9 V with respect to VSS.
VSS
Negative Power Supply
The most negative supply potential. This pin is usually
.
ground.

MC145158-2
2-555

MC14515X-2 FAMILY CHARACTERISTICS AND DESCRIPTIONS
MAXIMUM RATINGS· (Voltages Referenced to VSS)
Parameter

Symbol
VDD
Yin. Vout
Vout
lin. lout

100. ISS

DC Supply Voltage

- 0.5 to + 10.0

V

- 0.5 to VDD + 0.5

V

-0.5to+15

V

Input or Output Current (DC or Transient).
per Pin

±10

mA

Supply Current. VDD or VSS Pins

±30

mA

Input or Output Voltage (DC or Transient)
except SW1. SW2
Output Voltage (DC or Transient).
SW1. SW2 (Rpull-up = 4.7 kn)

Po

Power Dissipation. per Packaget

Tstg

Storage Temperature

TL

500

mW

-65to+150

°c

260

°c

Lead Temperature. 1 mm from Case for
10 seconds

These devices contain protection circuit-

Unit

Value

ry to protect against damage due to high
static voltages or electric fields. However.
precautions must be taken to avoid applications of any voltage higher than maximum rated vOltag~ to these high-impedance circuits. For proper operation. Vln
andVoutshouldbe nstrainedtotherange
VSS S (Vin or Vout) S VDD exceptfor SWl
andSW2.
SWl and SW2 can be tied through external resistors to voltages as high as 15 V dc.
Independent of the supply voltage.
Unused inputs must always be tied to an
appropriate logic voltage level (e.g .• either
VSS orVDD). exceptfor inputs with pull-up
devices. Unused outputs must be left open.

• Maximum Ratings are !liose values beyond which damage to the device may occur.
Functional operation should be restricted to the limits in the Electrical Characteristics
tables or Pin Descriptions section.
t Power Dissipation Temperature Derating:
Plastic DIP: - 12 mWrC from 65 to 85°C
PLCC Package: - 12 mWrC from 65 to 85°C
SOG Package: - 7 mW/oC from 65 to 85°C

ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
Symbol
VDD
Iss

ISS

Quiescent Supply Current
(not Including pull-up
current component)

+85°C

Max

Min

Max

Min

Max

Unit

-

3

9

3

9

3

9

V

fin = OSCin = 10 MHz.
1 Vp-p ac-coupled sine
wave
R = 128. A = 32. N = 128

3
5
9

-

3.5
10
30

-

3
7.5
24

mA

-

3
7.5
24

Yin = VDD or VSS
lout = 0 ~

3
5
9

-

800
1200
1600

-

800
1200
1600

~

-

1600
2400
3200

500

-

500

-

500

-

0
0
0

-

0
0
0

-

0
0
0

-

3.0
5.0
9.0

-

Yin

Input Voltage - fin. OSCln

Input ac-coupled sine wave

-

VIL

Low-Level Input Voltage -

Vout 2: 2.1 V
Vout 2: 3.5 V
Vout:!:6.3V

Input dccoupled
square wave

3
5
9

VoutSO.9V
VoutSl.5V
VoutS2.7V

Input dccoupled
square wave

3
5
9

3.0
5.0
9.0

~n.OSCln

25°C

Min

Test Condition

Power Supply Voltage
Range
Dynamic Supply Current

-40°C

VDD
V

Parameter

-

-

-

-

mVp-p
V

VIH

High-Level Input Voltage
-fin.OSCin

-

3.0
5.0
9.0

VIL

Low-Level Input Voltageexcept ~n. OSCin

3
5
9

-

0.9
1.5
2.7

-

0.9
1.5
2.7

-

-

0.9
1.5
2.7

VIH

High-Level Input Voltage
- except fin. OSCin

3
5
9

2.1
3.5
6.3

-

2.1
3.5
6.3

-

2.1
3.5
6.3

-

lin

Input Current (fin. OSCin)

Yin = VDD orVss

9

±2

±50

±2

±25

±2

±22

~

IlL

Input Leakage Current
(Data. eLK. ENBwithout pull-ups)

Vln= VSS

9

-

-0.3

-

-0.1

-

-1.0

~

-

V

V

V

(conllnued)

MC145151-2 through MC145158-2
2-556

MOTOROLA COMMUNICATIONS DEVICE DATA

ELECTRICAL CHARACTERISTICS (Continued)

Symbol

Parameter

IIH

Input Leakage Current (all
Inputs except fin, OSCin)

IlL

Pull-up Current (all inputs
with pull-ups)

Cin

Input Capacitance

VOL

Low-Level Output
Voltage - OSCout

VOH

High-Level Output
Voltage - OSCout

-40°C

+85°C

Min

Max

Min

Max

Min

Max

Unit

Vin=VOD

9

-

0.3

-

0.1

-

1.0

I'A

Vin=VSS

9

-20

-400

-20

-200

-20

-170

I1A

lout = 0 I'A
Vin=VOO
lout=OI'A
Vin=VSS

-

-

10

-

10

-

10

pF

3
5
9

-

-

-

0.9
1.5
2.7

-

-

0.9
1.5
2.7

V

-

0.9
1.5
2.7

3
5
9

2.1
3.5
6.3

-

2.1
3.5
6.3

-

-

V

-

2.1
3.5
6.3

0.05
0.05
0.05

-

0.05
0.05
0.05

-

0.05
0.05
0.05

V

2.95
4.95
B.95

-

2.95
4.95
B.95

-

V

-

15

-

15

-

V

1.10
1.70
3.30

-

0.66
1.0B
2.10

-

-0.50
-0.75
-1.25

-

-

-0.30
-0.50
-O.BO

-

0.20
0.51
1.00

-

0.15
0.36
0.70

-0.20
-0.51
-1.00

-0.15
-0.36
-0.70

-0.22
-0.36
-0.70

-

VOL

Low-Level Output
Voltage - Other Outputs

lout = 0 I'A

3
5
9

-

VOH

High-Level Output
Voltage - Other Outputs

lout= 0 I1A

3
5
9

2.95
4.95
B.95

Drain-to-Source
Breakdown Voltage SW1,SW2

Rpull-up = 4.7 kQ

-

15

10L

Low-Level Sinking
Current-MC

Vout=0.3V
Vout= 0.4 V
Vout=0.5V

3
5
9

1.30
1.90
3.BO

10H

High-Level Sourcing
Current-MC

Vout=2.7V
Vout=4.6V
Vout=B.5V

3
5
9

-0.60
-0.90
-1.50

10L

Low-Level Sinking
Current-LD

Vout= 0.3 V
Vout= 0.4 V
Vout=0.5V

3
5
9

0.25
0.64
1.30

10H

High-Level Sourcing
Current-LO

Vou t=2.7V
Vout= 4.6 V
Vout= B.5 V

3
5
9

-0.25
-0.64
-1.30

10L

Low-Level Sinking
Current - SW1, SW2

Vout=0.3V
Vou t=0.4 V
Vou t=0.5 V

3
5
9

O.BO
1.50
3.50

10L

Low-Level Sinking
Current - Other Outputs

Vout= 0.3V
Vout= 0.4V
Vout= 0.5V

3
5
9

10H

High-Level Sourcing
Current - Other Ou1puts

Vout=2.7V
Vout=4.6V
Vout= B.5V

10Z

Output Leakage Current POout

V(BR)DSS

25°C

VOO
V

Test Condition

-

-

-

-

-

mA

mA

mA

-

O.4B
0.90
2.10

0.44
0.64
1.30

-

0.35
0.51
1.00

3
5
9

-0.44
-0.64
-1.30

-

-

-0.35
-0.51
-1.00

-

Vout= VOD orVSS
Output in Off State

9

-

to.3

-

to.l

-

t 1.0

I1A

10Z

Output Leakage Current- Vout = VOO or VSS
SW1, SW2
Output in Off State

9

-

to.3

-

to.l

-

t3.0

I1A

Cout

Output Capacitance PDout

-

-

10

-

10

-

10

pF

POout - Three-State

MOTOROLA COMMUNICATIONS DEVICE DATA

-

0.24
0.45
1.05
0.22
0.36
0.70

-

rnA

rnA

mA

rnA

MC145151-2 through MC145158-2
2-557

AC ELECTRICAL CHARACTERISTICS (eL = 50 pF, Input tr = tf = 10 ns)
VDD
V

Guaranteed Limit
25°C

Guaranteed Limit
-40to 85°C

Maximum Propagation Delay, fin to Me
(Figures 1 and 4)

3
5
9

110
60
35

120
70
40

ns

Maximum Propagation Delay, ENB to SW1. SW2
(Figures 1 and 5)

3
5
9

160
80
50

180
95
60

ns

3
5
9

25 to 200
20 to 100
10 to 70

25 to 260
20 to 125
10t080

ns

Symbol
tpLH, tpHL

tPHL

tw

Parameter

Output Pulse Width. $R, $V. and LD with fR in Phase with
(Figures 2 and 4)

tv

Unit

trLH

Maximum Output Transition TIme, Me
(Figures 3 and 4)

3
5
9

115
60
40

115
75
60

ns

tTHL

Maximum Output Transition TIme. Me
(Figures 3 and 4)

3
5
9

60
34
30

70
45
38

ns

trLH. trHL

Maximum Output Transition TIme, LD
(Figures 3 and 4)

3
5
9

180
90
70

200
120
90

ns

trLH. trHL

Maximum Output Transition TIme, Other Outputs
(Figures 3 and 4)

3
5
9

160
80
60

175
100
65

ns

SWITCHING WAVEFORMS

VDD

tPLH-l

~~r

OUTPUT~

'I

$R, $V. LD'

L

~"'1-5_0-,_y,-_-_~~_tw~~~_-_-_-_-I-,r-~
....

"fR in phase with

Figure 1.

tv.
Figure 2.

trHL

ANY
OUTPUT

Figure 3.

f

VDD
TEST POINT

TEST POINT
OUTPUT

OUTPUT
DEVICE
UNDER
TEST

-Includes ali probe and jig capacitance.

Figure 4. Test Circuit

MC145151-2 through MC145158·2
2-558

15kr.!

DEVICE
UNDER
TEST

'Includes ali probe and jig capacitance.

Figure 5. Test Circuit

MOTOROLA COMMUNICATIONS DEVICE DATA

TIMING REQUIREMENTS (Inpul Ir = II = 10 ns unless otherwise indicaled)
Symbol

Parameter

VDD
V

Guaranteed Limit
25°C

Guaranteed Limit
-40 to 85°C

3
5

dclo 5.0
dcl07.1
dclo 10

dc 10 3.5
dcl07.1
dclo 10

MHz

30
20
18

30
20
18

ns

40
20
15

40
20
15

ns

70
32
25

70
32
25

ns

5
10
20

5
10
20

ns

50
35
25

70
35
25

ns

5
4
2

5
4
2

I1S

Iclk

Serial Data Clock Frequency, Assuming 25% Duty Cycle
NOTE: Reier 10 ClK Iw(H) below
(Figure 6)

9

Isu

Minimum Selup Time, Data 10 ClK
(Figure 7)

3
5

Ih

Minimum Hold Time, ClK 10 Dala
(Figure 7)

3
5

Isu

Minimum Selup Time, ClK 10 ENB
(Figure 7)

3
5

I rec

Minimum Recovery Time, ENB 10 ClK
(Figure 7)

3
5

Iw(H)

Minimum Pulse Width, ClK and ENB
(Figure 6)

3
5

Ir,11

Maximum Inpul Rise and Fall Times (Figure 8)

9

9

9

9

9
Any Inpul

3
5

9

Unit

SWITCHING WAVEFORMS

~~~

~voo

Iw(H)

DATA
VSS
Isu

VSS

1 '
. 4fclk

CLK
VSS

'Assumes 25% Duty Cycle.

Figure 6.

ENB
VSS
PREVIOUS
DATA
LATCHED

If

ANY
OUTPUT

VSS

Figure 7.

Figure 8.

MOTOROLA COMMUNICATIONS DEVICE DATA

MC145151-2 through MC145158-2
2-559

FREQUENCY CHARACTERISTICS (Voltages Relerences to VSS, CL = 50 pF, Input tr = tl =1 0 ns unless otherwise indicated)

Symbol
Ii

25·C

85·C

Min

Max

Min

Max

Min

Max

Unit

RR

0

U
0

v

I
U
0

LD

0

U
00

I
U
o

00

*

U
I
0

-

VH
VL
VH
VL
VH
HIGH IMPEDANCE

I

VL
VH
VL
VH

00

U
U

VL
VH

00

VL

VH = High Voltage Level
VL = Low Voltage Level
'At this point, when both.fR and tv are in phase, the output Is lorced to near mid-supply.
NOTE: The POout generates error pulses during out-ol-Iock conditions. When locked in phase and Irequency
the output is high and the voltage at this pin is determined by the low-pass fiiter capacitor.

Figure 9. Phase Detector/Lock Detector Output Waveforms

MC145151-2 through MC145158-2
2-560

MOTOROLA COMMUNICATiONS DEViCE DATA

PHASE-LOCKED LOOP-LOW-PASS FILTER DESIGN

eon

A)

~

=

V

K", KVCO
NR1C

-~

2~KVCO

-

1
F(s)= R1 SC + 1

eon -

8)

-

V

KcI> KVCO
NC(Rl +R21

~ =0.5 eon (R2C+ ~~VCO)
_R-,,2,-SC_+_1_
F(s) = (Rl+R21 sC + 1

C)

PDoul-

eon =
VCo

r

~

=

V~KVCO
NCRl

eon R2C
-2-

Rl
ASSUMING GAIN A IS VERY LARGE, THEN:
F(s) = R2SC + 1
RlsC

Nole: Sometimes Rl is split Into two series resistors each Rl + 2. A capacitor Cc Is then placed from the midpoint to ground to further
filter cl>v and cl>R. The value of Cc should be such that lhe corner frequency of this network does not significantly affect CIln.
DEFINITIONS:
N = Total Division Ratio in feedback loop
~ (Phase Detector Gain) = VDoI41t for PDout
~ (Phase Detector Gain) VDoI21t for cl>v and cl>R

=

KVCO (VCO Gain) = ~fvCO
.
.
VCO
21tfr
for a typical design wn (Natural Frequency) = 10 (at phase detector input).
Damping Factor: ~ :; 1
RECOMMENDED READING:
Gardner, Floyd M., Phaselock Techniques (second edition). New York, Wiley-Intersclence, 1979.
Manassewitsch, Vadim, Frequency Synthesizers: Theory and Design (second edition). New York, Wlley-Intersclence, 1980.
Blanchard, Alaln, Phase-Locked Loops: Application to Coherent Receiver Design. New York, Wiley-Interscience, 1976.
Egan, William F., Frequency Synthesis by Phase Lock. New York, Wiley-Intersclence, 1981.
Rohde, Ulrich L., Digital PLL Frequency Synthesizers Theory and Design. Englewood Cliffs, NJ, Prentice-Hall, 1983.
Berlin, Howard M., Design of Phase-Locked Loop Circuits, with Experiments. Indianapolis, Howard W. Sains and Co., 1978.
Kinley, Harold, The PLL Synthesizer Cookbook. Blue Ridge Summit, PA, Tab Books, 1980.
AN535, Phase-Locked Loop Design Fundamentals, Motorola Semiconductor Products, Inc., 1970.
AR254, Phase-Locked Loop Design Articles, Motorola Semiconductor Products, Inc., Reprinted with permission from Electronic Design,
1987.

MOTOROLA COMMUNICATIONS DEVICE DATA

MC145151-2 through MC145158-2
2-561

DESIGN CONSIDERATIONS
CRYSTAL OSCILLATOR CONSIDERATIONS
The following options may be considered to provide a
reference frequency to Motorola's CMOS frequency synthesizers.
Use of a Hybrid Crystal Oscillator
Commercially available temperature-compensated crystal
oscillators (TCXOs) or crystal-controlled data clock oscillators
provide very stable reference frequencies. An oscillator
capable of sinking and sourcing 50 ~ atCMOS logic levels
may be direct or dc coupled to OSCin. In general, the highest
frequency capability is obtained utilizing a direct-coupled
square wave having a rail-to-rail (VDD to VSS) voltage swing.
If the oscillator does not have CMOS logic levels on the
outputs, capacitive or ac coupling to OSCin may be used.
OSCout,
an unbuffered output, should be left floating.
For additional Information about TCXOs and data clock
oscillators, please consult the latest version of the eem
Electronic Engineers Master Catalog, the Gold Book, or
similar publications.
Design an Off-Chip Reference
The user may design an off-chip crystal oscillator using ICs
specifically developed for crystal oscillator applications, such
as the MC12061 MECL device. The reference signal from the
MECL device is ac coupled to OSCin. For large amplitude
signals (standard CMOS logic levels), dc coupling is used.
OSCout, an unbuffered output, should be left floating. In
general, the highest frequency capability is obtained with a
direct-coupled square wave having rail-to-rail voltage swing.
Use of the On-Chip Oscillator Circuitry
The on-chip amplifier (a digital inverter) along with an
appropriate crystal may be used to provide a reference source
frequency. A fundamental mode crystal, parallel resonant at
the desired operating frequency, should be connected as
shown in Figure 10.

r

-

-

-

-

I

-

Rf

I

L_

FREQUENCYI
SYNTHESIZE'R I

___

o

OSCin

R1'

I
_-.J
OSCout

I-+--'VIIIr--'

'May be deleted in certain cases. See text.
Figure 10_ Pierce Crystal Oscillator Circuit

=

For VDD
5.0 V, the crystal should be specified for a
loading capacitance, CL, which does not exceed 32 pF for
frequencies to approximately 8.0 MHz, 20 pF for frequencies
in the area of 8.0 to 15 MHz, and 10 pF for higherfrequencies.
These are guidelines that provide a reasonable compromise
between IC capacitance, drive capability, swamping varia-

MC145151-2 through MC145158-2
2-562

tions in stray and IC input/output capacitance, and realistic
CL values. The shunt load capacitance, CL, presented across
the crystal can be estimated to be:
CL=

CinCout
Cin + Cout

C

C

C1 • C2

+ a+ 0 + - - C1 + C2

where:
Cin
Cout
Ca =
Co
C1 and C2

= 5 pF (see Figure 11)
= 6 pF (see Figure 11)
1 pF (see Figure 11)
= the crystal's holder capacitance (see Figure 12)
= external capacitors (see Figure 10)

~O_-'I_-+~~a~__rl__-OO
Cin *

.;

*Cout

.;

Figure 11. Parasitic Capacitances of the Amplifier

Co

NOTE: Values are supplied by crystal manufacturer
(parallel resonant crystal).

Figure 12. Equivalent Crystal Networks
The oscillator can be "trimmed" on-frequency by making a
portion or all of C1 variable. The crystal and associated
components must be located as close as possibletothe OSCin
and OSCout pins to minimize distortion, stray capacitance,
stray inductance, and startup stabilization time. In some
cases, stray capacitance should be added to the value for Cin
and Couto
Power is dissipated in the effective series resistance of the
crystal, Re, in Figure 12. The drive level speCified by the crystal
manufacturer is the maximum stress that a crystal can
withstand without damaging or excessive shift in frequency.
R1 in Figure 10 limits the drive level. The use of R1 may not
be necessary In some cases (I.e., R1 = 0 Q).
To verify that the maximum dc supply voltage does not
overdrive the crystal, monitor the output frequency as a
function of voltage at OSCout. (Care should be taken to
minimize loading.) The frequency should increase very slightly
as the dc supply voltage is increased. An overdriven crystal
will decrease in frequency or become unstable with an
increase in supply voltage. The operating supply voltage must
be reduced or R1 must be increased in value if the overdriven
condition exists. The user should note that the oscillator
start-up time is proportional to the value of R1.
Through the process of supplying crystals for use with
CMOS inverters, many crystal manufacturers have developed expertise in CMOS oscillator design with crystals.
Discussions with such manufacturers can prove very helpful
(see Table 1).

MOTOROLA COMMUNICATIONS DEVICE DATA

Recommended Reading
Technical Note TN-24, Statek Corp.
Technical Note TN-7, Statek Corp.
E. Hafner, "The Piezoelectric Crystal Unit - Definitions and
Method of Measurement", Proc. IEEE, Vol. 57, No.2 Feb.,
1969.
D. Kemper, L. Rosine, "Quartz Crystals for Frequency
Control", Electro-Technology, June, 1969.
P. J. Ottowitz, "A Guide to Crystal Selection", Electronic
Design, May, 1966.
Table 1. Partial List of Crystal Manufacturers
Address

Phone

United States
Crystal Corp.

Name

3605 McCart St.,
Ft. Worth, TX
76110

(817) 921-3013

Crystek Crystal

2371 Crystal Dr.,
Ft. Myers, FL
33907

(813) 936-2109

Statek Corp.

512 N. Main St.,
Orange,CA
92668

(714) 639-7810

NOTE: Motorola cannot recommend one supplier over another and In
no way suggests that this is a complete listing of crystal manufacturers.
DUAL-MODULUS PRESCALING
Overview
The technique of dual-modulus prescaling is well established as a method of achieving high performance frequency
synthesizer operation at high frequencies. Basically, the
approach allows relatively low-frequency programmable
counters to be used as high-frequency programmable
counters with speed capability of several hundred MHz. This
is possible without the sacrifice in system resolution and
performance that results if a fixed (single-modulus) divider is
used for the prescaler.
In dual-modulus prescaling, the lower speed counters must
be uniquely configured. Special control logic is necessary to
select the divide value P or P + 1 in the prescaler for the
required amount of time (see modulus control definition).
Motorola's dual-modulus frequency synthesizers contain this
feature and can be used with a variety of dual-modulus
prescalers to allow speed, complexity and cost to be tailored
to the system requirements. Prescalers having P, P + 1 divide
values in the range of + 3/+ 4 to + 128/+ 129 can be controlled
by most Motorola frequency synthesizers.
Several dual-modulus prescaler approaches suitable for
use with the MC145152-2, MC145156-2, or MC145158-2 are:
MC12009
MC12011
MC12013
MC12015
MC12016
MC12017
MC12018
MC12022A
MC12032A

+5/+6
+8/+9
+ 10/+11
+32/+33
+40/+41
+64/+65
+ 1281+ 129
+ 64/65 or + 1281129
+ 64/65 or + 1281129

440 MHz
500 MHz
500 MHz
225 MHz
225 MHz
225 MHz
520 MHz
1.1 GHz
2.0GHz

MOTOROLA COMMUNICATIONS DEVICE DATA

Design Guidelines
The system total divide value, Ntotal (NT) will be dictated
by the application:

=

N
T

frequency into the prescaler
frequency into the phase detector

=N • P + A

N is the number programmed into the + N counter, A is the
number programmed into the + A counter, P and P + 1 are
the two selectable divide ratios available in the dual-modulus
prescalers. To have a range of NT values in sequence, the
+ A counter is programmed from zero through P - 1 for a
particular value N in the + N counter. N is then incremented
to N + 1 and the + A is sequenced from 0 through P -1 again.
There are minimum and maximum values that can be
achieved for NT. These values are a function of P and the size
of the + Nand + A counters.
The constraint N ;:: A always applies. If Amax P - 1, then
Nmin ;:: P - 1. Then NTmin = (P - 1) P + A or (P - 1) P since
A is free to assume the value of o.

=

NTmax = Nmax • P + Amax
To maximize system frequency capability, the dual-modulus
prescaler output must go from low to high after each group
of P or P + 1 input cycles. The prescaler should divide by P
when its modulus control line is high and by P + 1 when its
MC is low.
For the maximum frequency into the prescaler (fVCOmax),
the value used for P must be large enough such that:
1. fVCOmax divided by P may not exceed the frequency
capability of fin (input to the + Nand + A counters).
2. The period of fVCO divided by P must be greater than
the sum of the times:
a. Propagation delay through the dual-modulus prescaler.
b. Prescaler setup or release time relative to its MC
signal.
c. Propagation time from fin to the MC output for the
frequency synthesizer device.
A sometimes useful simplification in the programming code
can be achieved by choosing the values for P of 8, 16, 32,
or 64. For these cases, the desired value of NT results when
NT in binary is used as the program code to the + Nand +
A counters treated in the following manner:
1. Assume the + A counter contains "a" bits where 2 a ;:: P.
2. Always program all higher order + A counter bits above
"a" to o.
3. Assume the + N counter and the + A counter (with all the
higher order bits above "a" ignored) combined into a
single binary counter of n + a bits in length (n number
of divider stages in the + N counter). The MSB of this
"hypothetical" counter is to correspond to the MSB of
+ N and the LSB is to correspond to the LSB of + A. The
system divide value, NT, now results when the value of
NT in binary is used to program the "new" n + a bit
counter.
By using the two devices, several dual-modulus values are
achievable (shown in Figure 13).

=

MC145151-2 through MC145158-2
2-563

Me

DEVICE

B
DEVICE A
MCl 0131

MC12009

MC12011

+20/+21

+32/+33

MC12013
+ 40/+ 41

MCl 0138 +50/+51

+80/+81

+ 100/+ 101

+40/+41

+641+65

+80/+81

MCl 0154

or

or

+80/+81

+ 128/+ 129

NOTE: MC12009, MC12011, and MC12013 are pin equivalent.
MC12015, MC12016, and MC12017 are pin equivalent.

Figure 13.

MC145151-2 through MC145158-2
2-564

MOTOROLA COMMUNICATIONS DEVICE DATA

MOTOROLA

-

SEMICONDUCTOR
TECHNICAL DATA

Serial-Input PLL Frequency
Synthesizer with Analog Phase
Detector
Interfaces with Dual-Modulus Prescalers
The MC145159-1 has a programmable 14-bit reference counter, as well as fully
programmable divide-by-N/divide-by-A counters. The counters are programmed
serially through a common data input and latched into the appropriate counter
latch, according to the last data bit (control bit) entered.
When combined with a loop filter and VCO, this device can provide all the
remaining functions for a PLL frequency synthesizer operating up to the device's
frequency limit. For higher VCO frequency operations, a down mixer or a dual
modulus prescaler can be used between the VCO and the PLL.
• General Purpose Applications:
TV Tuning
CATV
Scanning Receivers
AM/FM Radios
Two Way Radios
Amateur Radio
• Low Power Consumption Through Use of CMOS Technology
• 3.0 to 9.0 V Supply Range
• On- or Off-Chip Reference Oscillator Operation
• Compatible with the Serial Peripheral Interface (SPI) on CMOS MCUs
• + R Range 3 to 16383
• + N Range 16 to 1023, + A Range 0 to 127
• High-Gain Analog Phase Detector
• See Application Note AN969

=
=

=

PIN ASSIGNMENTS

PLASTIC DIP
and SOG PACKAGE
20

RR

OSCin

2

19

VDD'

SRout

OSCout

3

18

CH

ENB

CHARGE

4

17

APDout

DATA

16

VSS'

VDD

VSS'

RR

~-

•

FNSUFFIX
PLCC
CASE 775

1

~~

ORDERING INFORMATION
MC145159Pl
MC145159FNI
MC145159DWI
MC145159VFl

Plastic DIP
PLCC
SOG
SSOP

The PLCC (FN suffix)
package will be phased
out for this device and is
NOT RECOMMENDED
FOR NEW DESIGNS.

CR

'S
.S;;
0
u u

'"0 0'"
3

2

'0

rP£,~

-

1 20
CH
APDout

CLK

VSS'
CR

6

15

CR

VSS

7

14

SRout

~n
LD

MC

8

13

ENB

MC

9 10

11

....

....
""
u

LD

9

12

DATA

VSS

fin

10

11

CLK

FSO

MOTOROLA COMMUNICATIONS DEVICE DATA

OW SUFFIX
SaG
CASE 751D

VFSUFFIX
SSOP
CASETBD

FSO

VDD

PSUFFIX
PLASTIC
CASE73B

PLCC PACKAGE

SSOP PACKAGE

1-

RO

MC145159-1

0

~

SHout

12
j:!i

;5

m
z
w

MC145159-1
2-565

BLOCK DIAGRAM

ENB - - - - - - - - - - ,
OSCout -----------,

~~~~~~~~~~]--t----::::::::=====SRO~
, - - - - - - - . - - CHARGE
CH
ANALOG

OSCin

>:~-IIt-----!~~~~~~~~~~~jftj

"

R

DETECTOR
PHASE

RR

RO
CR
APDout
VDD'

L-++++~~~~~= VSS'
MC
FSO

lD
ClK

--l-----~=====--l_=====:.J

*FSO is not and cannot be used as a digital phase detector output.

MAXIMUM RATINGS· (Voltages Referenced to VSS)
Symbol
VOO
Yin, Vout
lin, lout
100, ISS

Parameter
DC Supply Voltage
Input or Output Voltage (DC or Transient)

Unit

- 0.5 to + 10.0

V

- 0.5 to VOO + 0.5

V

Input or Output Current (DC or Transient), per Pin

±10

mA

Supply Current, VOO or VSS Pins

±30

mA

Po

Power Dissipation, per Package

Tstg

Storage Temperature

Tl

Value

Lead Temperature (B-Second Soldering)

500

mW

-65to+ 150

·C

260

·C

This device contains circuitry to protect
the Inputs against damage due to high statIc voltages or electric fields; however, it is
advised that normal precautions be taken
to avoid applications of any voltage higher
than maximum rated voltages to this highImpedance circuit. For proper operation it is
recommended that Yin and Vout be constrained to the range VSS S (Vln or Voutl s
VOO·
Unused inputs must always be tied to an
appropriate logic voltage level (e.g., either
VSsorVOO)·

* Maximum Ratings are those values beyond which damage to the device may occur.

MC145159-1
2-566

MOTOROLA COMMUNICATIONS DEVICE DATA

ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS except ICR and IAPD which are referenced to VSS')
-40'C
Characteristic
Power Supply Voltage Range
Output Voltage
Yin = OVorVDD
lout = 0 IIA
(Except OSCout and APDout)

Output Voltage
OSCout
Yin = 0 VorVDD

Input Voltage' - OSCin
VO=2.1 VorO.9V
Vo = 3.5 Vor 1.5 V
Vo = 6.3 Vor2.7 V
Vo = 0.9 Vor 2.1 V
Vo = 1.5 Vor3.5 V
Vo = 2.7Vor 6.3 V

Min

Max

Min

Max

Min

Max

Unit

VDD

-

3

9

3

9

3

9

V

0.05
0.05
0.05

-

0.05
0.05
0.05

V

2.95
4.95
8.95

-

VOL

3
5
9

-

0.05
0.05
0.05

-

1 Level

VOH

3
5
9

2.95
4.95
8.95

-

2.95
4.95
8.95

o Level

VOL

3
5
9

-

0.9
1.5
2.7

-

-

0.9
1.5
2.7

-

-

0.9
1.5
2.7

1 Level

VOH

3
5
9

2.1
3.5
6.3

-

2.1
3.5
6.3

-

2.1
3.5
6.3

aV

-

-

VIL

3
5
9

0.9
1.5
2.7

-

1.05

o Level

-

0.9
1.5
2.7

-

0.9
1.5
2.7

1 Level

VIH

3
5
9

2.1
3.5
6.3

-

2.1
3.5
6.3

-

2.1
3.5
6.3

-

0
0
0

-

0
0
0

-

-

0
0
0

3.0
5.0
9.0

-

3.0
5.0
9.0

-0.50
-0.75
-1.25

-

-0.30
-0.50
-0.80

-

1.10
1.70
3.30

-

-

0.66
1.08
2.10

-

-90

-110

-

-

170

350

-

-

o Level
1 Level

VIL
3
5
9

-

-

VIH

-

3
5
9

3.0
5.0
9.0

3
5
9

-0.60
-0.90
-1.50

IOL

3
5
9

1.30
1.90
3.80

Output Current, CR, VCR = 4.5 V, RR = 240 k

ICR

9

Output Current, APDout
RO = 240 k, VCH = 0 V, VAPDout = 4.5 V

IAPD

9

-

3
5
9

-0.44
-0.64
-1.30

IOL

3
5
9

0.44
0.64
1.30

-

Input Current - Data, CLK, ENB

lin

9

-

Input Current - fin, OSCin

lin

9

-

Output Current - MC
Vout=2.7V
Vout=4.6V
Vout= 8.5 V
Vout= 0.3 V
Vout= 0.4 V
Vout= 0.5 V

Output Current - Other Outputs
Vout=2.7V
Vout=4.6V
Vout=8.5V
Vout=0.3V
Vout= 0.4 V
Vout= 0.5 V

85'C

Vee

o Level

aVoltage, VCH - VAPDout, IAPOout ~ 0 IIA
Input Voltage
Vout = 0.5 V or VDD - 0.5 V
(All Outputs Except OSCout)

25'C

Symbol

-

IOH
Source

Sink

IOH
Source

Sink

Input Capacitance

Cin

Three-State Output Capacitance - FSO

Cout

Quiescent Current
Yin = 0 VorVDD
lout = 0 IIA

100

3
5
9

Three-State Leakage Current, Vout = 0 V or 9 V

IOZ

9

-

-

-

-

V

V
V

V

-

V

-

rnA

-

IIA
IIA
rnA

-0.35
-0.51
-1.00

-

-0.22
-0.36
-0.70

0.35
0.51
1.00

-

0.22
0.36
0.70

-

±0.3

-

±0.1

-

±1.0

±2

±50

±2

±25

±2

±22

IIA
IIA

-

10

-

10

-

10

pF

10
800
1200
1600
±0.3

10
800
1200
1600
±0.1

10

pF

1600
2400
3200

IIA

±3.0

IIA

'DC-coupled square wave.

MOTOROLA COMMUNICATIONS DEVICE DATA

MC145159-1
2-567

SWITCHING CHARACTERISTICS (fA

=25°C, Cl =50 pF)

Characteristic

Figure #

Symbol

VOO

Min

Max

Unit

4,9

ITlH

3
5
9

-

115
60
40

ns

MC

4,9

ITHl

3
5
9

-

-

ns

-

60
34
30

Output Rise and Fall Time - lO and SRout

4,9

ITlH,
ITHl

3
5
9

-

140
80
60

ns

Propagation Delay Time - fin to MC

5,9

tPlH,
tpHl

3
5
9

-

125
80
50

ns

Data to ClK

6

tsu

3
5
9

30
20
18

ns

ClKtoENB

6

3
5
9

70
32
25

-

Output Rise Time -

Output Fall Time -

Setup Times -

MC

Hold Time - ClK to Data

6

th

3
5
9

12
12
15

Recovery Time -

6

trec

3
5
9

5
10
20

7

tr,tf

3
5
9

-

5
2
0.5

I1S

3
5
9

40
35
25

-

ns

ENB to ClK

Input Rise and Fall Times ~ ClK, OSCln, fin

Input Pulse Width -

ENB and ClK

8

tw

ns

ns

-

NOTE: Refer to the graphs and text in application note AN969 for maximum frequency information.

MC145159-1
2-568

MOTOROLA COMMUNICATIONS DEVICE DATA

frequencies present at the internal phase detector inputs. A
polystyrene or mylar capacitor is recommended.

PIN DESCRIPTIONS
INPUT PINS
OSCin, OSCout
Oscillator Input and Oscillator Output
These pins form an on-chip reference oscillator when connected to terminals of an external parallel-resonant crystal.
Frequency-setting capacitors of appropriate value must be
connected from OSCin to VssandOSCoutto VSS. OSCin may
also serve as input for an externally-generated reference signal. This signal will typically be ac coupled to OSCin, but for
larger amplitude signals (standard CMOS logic levels), dc
coupling may also be used. In the external reference mode, no
connection is required to OSCout.
fin
Frequency Input
Input to the positive edge triggered divide-by-N and divideby-A counters. fin is typically derived from a dual modulus
prescaler and is ac coupled. This input has an inverter biased
in the linear region to allow use with ac-coupled signals as low
as 500 mV peak-to-peak or direct- coupled signals swinging
from VOO to VSS.
DATA
Serial Data Input
Counter and control information is shifted into this input. The
last data bit entered goes into the one-bit control shift register.
A logic 1 allows the reference counter information to be loaded
into its 14-bit latch when Enable goes high. A logic 0 entered
as the control bit disables the reference counter latch. The divide-by-Aldivide-by-N counter latch is loaded, regardless of
the contents of the control register, when ENS goes high. The
data entry format is shown in Figure 1.
ENB
Transparent latch Enable
A logic high on this input allows data to be entered into the
divide-by-Aldivide-by-N latch and, if the control bit is high,
into the reference counter latch. Counter programming is
unaffected when ENS is low. ENS should be kept normally low
and pulsed high to transfer data to the latches.
ClK
Shift Register Clock
A low-to-high transition on this input shifts data from the
serial data input into the shift registers.
COMPONENT PINS
CR
Ramp Capacitor
The capacitor connected from this pin to VSS' is charged
linearly, at a rate determined by RR. The voltage on this
capacitor is proportional to the phase difference of the

RR
Ramp Current Bias Resistor
A resistor connected from this pin to VSS' determines the
rate at which the ramp capacitor is charged, thereby affecting
the phase detector gain (see Figure 2).
CH
Hold Capacitor
The charge stored on the ramp capacitor is transferred to
the capacitor connected from this pin to either VDD' or VSS'.
The ratio of CR to CH should be large enough to have no affect
on the phase detector gain (CR > 10 CH). A low-leakage
capacitor should be used.
RO
Output Bias Current Resistor
A resistor connected from this pin to VSS' biases the output
N-Channel transistor, thereby setting a current sink on the
analog phase detector output. This resistor adjusts the APDout
bias current (see Figure 3).
OUTPUT PINS
APDout
Analog Phase Detector Output
This output produces a voltage that controls an external
VCO. The voltage range of this output (VDD + 9 V) is from
below + 0.5 V to + 8 V or more. The source impedance of
this output is the equivalent of a source follower with an externally variable source resistor. The source resistor depends
upon the output bias current controlled by the output bias current resistor, RO. The bias current is adjustable from 0.01 mA
to 0.5 rnA. The output voltage is not more than
1.05 V below the sampled point on the ramp. With a constant
sample of the ramp voltage at 9 V and the hold capacitor of
50 pF, the instantaneous output ripple is about 5 mV peakto-peak.

=

CHARGE
Ramp Charge Indicator
This output is high from the time fR goes high to the time
fV goes high (fR and fV are the frequencies at the phase
detector inputs). This high voltage indicates that the ramp
capacitor, CR, is being charged.
FSO
Three·State Frequency Steering Output
If the counted down input frequency on fin is higher than
the counted down reference frequency of OSCin, this olltput
goes low. If the counted down VCO frequency is lower than
that of the counted down OSCin, this output goes high.
The repetition rate of the frequency steering output pulses
is approximately equal to the difference of the frequencies

LATCHED WHEN
CONTROL BIT = 1
SHIFT
REGISTER
OUT

DATA IN

Figure 1. Data Entry Format

MOTOROLA COMMUNICATIONS DEVICE DATA

MC145159·1
2·569

The repetition rate of the frequency steering output pulses
is approximately equal to the difference of the frequencies
of the two counted down inputs from the VCO and OSCin.
See Application Note AN969 for further information.
LD
Lock Detector Indicator
This output is high during lock and goes low to indicate a
non-lock condition. The frequency and duration olthe non-lock
pulses will be the same as either polarity olthe frequency
steering output.
MC
Dual Modulus Prescaler Control
The modulus control level is low at the beginning of a count
cycle and remains low until the divide-by-A counter has
counted down from its programmed value. At that time, the
modulus control goes high and remains high until the
divide-by-N counter has counted the rest of the way down from
its programmed value (N - A additional counts since both
divide-by-N and divide-by-A are counting down during the first
portion of the cycle). Modulus control is then set back low,
the counters preset to their respective programmed values,
and the above sequence repeated. This provides for a total
programmable divide value of NT = N • P + A, where P and
P + 1 represent the dual modulus prescaler divide values
respectively for high and low modulus control levels, N is the
number programmed into the divide-by-N counter, and A is
the number programmed into the divide-by-A counter.

c;

e

w
u

~

'"

1i5
w

II:
D..

:::;:

"'"

II:

II:

II:

1000
700
500

SRout
Shift Register Output
This pin is the non-inverted output of the last stage of the
32-bitserial data shift register. It is not latched by the ENB
line. If unused, SRout should be floated.
POWER SUPPLY PINS
VDD
Positive Power Supply
Positive power supply input for all sections of the device
except the analog phase detector. VDD and VDD' should be
powered up at the same time to avoid damage to the
MC145159-1. VDD must betiedtothe same potential as VDD'.
VSS
Negative Power Supply
Circuit ground for all sections of the MC145159-1 except
the analog phase detector. VSS must be tied to the same
potential as VSS'.
VSS'
Analog Phase Detector Circuit Ground
Separate power supply and ground inputs are provided to
help reduce the effects in the analog section of noise coming
from the digital sections of this device and the surrounding
circuitry.
VDD'
Analog Power Supply
Separate power supply and ground inputs are provided to
help reduce the effects in the analog section of noise coming
from the digital sections of this device and the surrounding
circuitry.

 =

ICHARGE
21tfRCR

where
Kef> = phase detector gain, ICHARGE is from Figure 2
fR = reference frequency
CR = ramp capacitor (in farads)

MC145159-1
2-570

MOTOROLA COMMUNICATIONS DEVICE DATA

SWITCHING WAVEFORMS

VDD
-VSS

tn-tL

tPLH-i

ANY
OUTPUT

I":..-.t..~

MC~
Figure 4.

"4

j+-

'--

Figure 5.

' - - - - - - Vss

-VDD

CLK
OSCin. fin

PREVIOUS
DATA
LATCHED

VSS

Figure 6.

Figure 7.

OUTPUT

ENS. CLK

1,'"":50=%===::-tw....;...-------=--=--=-L- VDD

'J

DEVICE
UNDER
TEST

Vss
Figure 8.

MOTOROLA COMMUNICATIONS DEVICE DATA

Figure 9. Test Circuit

MC145159-1
2-571

DESIGN CONSIDERATIONS

CinCout

CRYSTAL OSCILLATOR CONSIDERATIONS
The following options may be considered to provide a
reference frequency to Motorola's CMOS frequency synthesizers.
Use Of A Hybrid Crystal Oscillator
Commercially available temperature-compensated crystal
oscillators (TCXOs) or crystal-controlled data clock oscillators provide very stable reference frequencies. An oscillator
capable of sinking and sourcing 50 I!A at CMOS logic levels
may be direct or dc coupled to OSCin. In general, the highest
frequency capability is obtained utilizing a direct-coupled
square wave having a rail-to-rail (VDD to VSS) voltage swing.
If the oscillator does not have CMOS logic levels on the
outputs, capacitive or ac coupling to OSCin may be used.
OSCout, an unbuffered output, should be left floating.
For additional information about TCXOs and data clock
oscillators, please consult the latest version of the eem
Electronic engineers Master Catalog, the Gold Book, or
similar publications.
Design An Off-chip Reference
The user may design an off-chip crystal oscillator using ICs
specifically developed for crystal oscillator applications, such
as the MC12061 MECL device. The reference signal from the
MECL device is ac coupled to OSCin. For large amplitude
signals (standard CMOS logic levels), dc coupling is used.
OSCout, an unbuffered output, should be left floating. In
general, the highest frequency capability is obtained with a
direct-coupled square wave having rail-to-rail voltage swing.
Use Of The On-chip Oscillator Circuitry
The on-Chip amplifier (a digital inverter) along with an
appropriate crystal may be used to provide a reference source
frequency. A fundamental mode crystal, parallel resonant at
the desired operating frequency, should be connected as
shown in Figure 10.
For VDD = 5 V, the crystal should be specified for a loading
capacitance, CL, which does not exceed 32 pF for
frequencies to approximately 8 MHz, 20 pF for frequencies
in the area of 8 to 15 MHz, and 10 pF for higher frequencies.
These are guidelines that provide a reasonable compromise
between IC capacitance, drive capability, swamping variations in stray and IC inpuVoutput capacitance, and realistic
CL values. Assuming Rl 0 n. the shunt load capacitance,
CL, presented across the crystal can be estimated to be:
where

=

r

-

I

-

-

-

-

Rf

I
L_

FREQUENCYl
SYNTHESIZER I

___
eSCin

R1*

D~1r--'

I
_~
eSCout

'May be deleted In certain cases. See text.
Figure 10. Pierce Crystal Oscillator Circuit

MC145159-1
2-572

= Cin + Cout + Ca + Cstray +

CL

Cl • C2
Cl C2
+

=
=

Cin
5 pF (see Figure 11)
Cout 6 pF (see Figure 11)
Ca = 1 pF (see Figure 11)
Cl and C2 external capacitors (see Figure 10)
Cstray the total' equivalent external circuit stray capacitance appearing across the crystal terminals

=

=

eSCin O-,-...LTI-'I--trr>>-

OSCi"

IP

LOCK
DET

TRANSMIT
ROM

PHASE
DET2

PD2

MCl45160 ONLY

MODE

1
REFERENCE
COUNTER
DIVIDE·BV·2048

~I
11

,.------

5kHz
~

Ir

-

DECODE
LOGIC

4kHz

I

•

I
I

•

I
I

•

I
I

•

I

0
MC145160 and
MC145166
ONLY

01
02
0

~------

MCl45160

,.-----

4·BITLATCH ~ENB

VSS

5k

------- -.,I
I
I
I
I
I
I

f

MCl451670NLV

CLK

Vss

DATA
• ON·CHIP PULL DOWN

MOTOROLA COMMUNICATIONS DEVICE DATA

L _________________ ~

MC145160eMC1451660MC145167
2-575

MAXIMUM RATINGS· (Voltages Referenced to VSS)
Symbol
VDD
Vln
lin, lout
IDD,ISS
Tsto

Rating
DC Supply Voltage
Input Voltage, All Inputs
DC Current Drain Per Pin
DC Current Drain VDD or VSS Pins
Storage Temperature Range

Value

Unit

-0.5 to +6.0

V

-0.5toVDD+0.5

V

10

mA

30

mA

-65 to +150

·C

• Maximum Ratings are those values beyond which damage to the device may occur. Functional
operation should be restricted to the limits in the Electrical Characteristics tables or Pin Descriptions section.

This device contains protection circuitry to guard against damage due to
high static voltages or electric fields.
However, precautions must be taken to
avoid applications of any voltage higher
than maximum rated voltages to this
high-impedance circuit. For proper operation, Vin and Vout should be
constrained to the range VSS" (Vin
or VoW" VDD·
Unused inputs must always be tied to
an appropriate logic voltage level (e.g.,
either VSS or VDD). Unused outputs
must be left open.

ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS, TA=25·C)
Guaranteed Limit
Symbol

Characteristic

VDD

Power Supply Voltage Range

VOL

Output Voltage
(lout=O)

VOH

VIL

(Vin=VDDorO)

Input Voltage
(Vout=0.5 Vor VDD-0.5 V)"

VIH

VDD

Min

Max

Unit

-

2.5

5.5

V

o Level

2.5
5.5

-

-

0.05
0.05

V

1 Level

2.5
5.5

2.45
5.45

-

oLevel

2.5
5.5

-

0.75
1.65

1 Level

2.5
5.5

1.75
3.85

IOH

Output Current (Vout= 2.2 V)
(Vout=5.0 V)

Source

2.5
5.5

-0.18
-0.55

IOL

(Vout=0.3 V)
(Vout=0.5 V)

Sink

2.5
5.5

0.18
0.55

OSCin, flnl , ftn2

2.5
5.5

IlL

Input Current
(Vin=O)

-

Cout

Output Capacitance

IDD

Standby Current, SB=VSS or Open

2.5
5.5

Idd

Operating Current
(200 mVp-p input at finl and fin2, SB=VDD)

2.5
5.5

-

IOZ

Three-State Leakage Current
(Vout=O or 5.5 V)

5.5

-

IIH

Cin

(Vin=VDD-0.5)

Input Capacitance

MC145160.MC145166.MC145167
2-576

DATA, S8, Mode

2.5
5.5

OSCin, finl, fin2

2.5
5.5

DATA, S8, Mode

2.5
5.5

-

-30
-66

V

mA

pA

-0.05
-0.11
30
66

pA

50
121
8.0

pF

8.0

pF

1.4
3.6

rnA

2.8
6.2

mA

±1.0

I1A

MOTOROLA COMMUNICATIONS DEVICE DATA

SWITCHING CHARACTERISTICS (TA = 25°C, CL = 50 pF)
Guaranteed Limit
Max

Unit

ITLH

Output Rise Time

1,5

3.0
5.0

-

200
100

ns

ITHL

Output Fall Time

1,5

3.0
5.0

-

200
100

ns

-

t r, tf

Input Rise and Fall Time, OSCin

5.0
4.0

I's

fmax

Input Frequency
Input = Sine Wave 200 mVp·p

-

12
60
60

MHz

Symbol

tsu

Characteristic

Figure #

VDD

2

3.0-5.0
3.0-5.0
3.0-5.0

OSCin
finl
~n2

Setup Time (MC145167)

DATAtoCLK

3

ENBtoCLK
th
tree
tw

3.0
5.0

Min

-

-

ns

200
100

-

3.0
5.0

100
50

3.0
5.0

Hold Time (MC145167), CLK to DATA

3

3.0
5.0

80
40

-

ns

Recovery Time (MC145167), ENB to CLK

3

3.0
5.0

80
40

-

ns

Input Pulse Width (MC145167), CLK and ENB

4

3.0
5.0

80
60

-

ns

-

SWITCHING WAVEFORMS

If

trHL
ANY
OUTPUT

Figure 1.

DATA

Figure 2.

03

Isu
50"10

CLK--':";'~

ENB-----------------------------------------~

Figure 3.

ENB,
CLK

~50"lo

Iw

L

Figure 4.

MOTOROLA COMMUNiCATIONS DEVICE DATA

MC145160.MC145166.MC145167
2·577

ClK, DATA
Clock, Data
These pins provide the BCD input by using serial channel
programming instead of parallel. Logical high represents a 1.
Each low-to-high transition of the clock shifts one bit of data
into the on-chip shift register.

PIN DESCRIPTIONS
INPUTS
OSCin/OSCout
Reference Oscillator InpuUOutput
'
These pins form a reference oscillator when connected
to an external parallel-resonant crystal. For a 46/49 MHz
cordless phone application, a 10,24-MHz crystal is needed,
OSCin may also serve as input for an externally generated reference signal. This signal is typically ac coupled to
OSCin, but for larger amplitude signals (standard CMOS logic
levels) dc coupling may also be used. In the external
reference mode, no connection is required for OSCout.

ENB
Enable
The enable pin controls the data transfer from the shift
register to the 4-bit latch. A positive pulse latches the data.
OUTPUTS

MODE
Mode is for determining whether the part is to be used in
the base or handset of a cordless phone. Internally, this pin
is used in the decoding logic for selecting the ROM address.
When high, the device is set in the base mode, and when
low, it is set in the handset mode. This input has an internal
pull-down device.
'
SB
Standby Input
The standby pin is used to save power when not
transmitting, When high, both the transmit and receive loops
are in operation. When low, the transmit loop is disabled,
thereby reducing power consumption. This input has an
internal pull-down device.

5k,4k
5-kHz and 4-kHz Tone Signals
These are 5-kHz and 4-kHz tone signals derived from the
reference oscillator, these are N-channel open-drain outputs.
lD
lock Detect Signal
The lock detect signal is associated with the transmit loop.
The lock output goes high to indicate an out-of-Iock condition.
This is a P-channel open-drain output.
PD1, PD2
Phase Detector Outputs
These are three-state outputs of the transmit and receive
phase detectors for use as loop error signals.
Frequency fv > fr or fv leading: Output = Negative pulses
Frequency fv < fr or fv lagging: Output = Positive pulses
Frequency fv = fr and phase coincidence:
Output = High-impedance state

DO-D3
Data Inputs
These inputs provide the BCD code for selecting the one
of ten channels to be locked in both the transmit and receive
loop. When address data other than 1-10 are input, the
decoding logic defaults to channel 10. The frequency
assignments with reference to Mode and DO-D3 are shown
in Table 1. These inputs have internal pull-down devices.

OSCB
Buffered Reference Oscillator
Buffered output of the on-Chip reference oscillator or
externally provided reference. This output is available on the
MC145160 only.
POWER SUPPLY
VSS
Negative Power Supply
This pin is the negative supply potential and is usually
ground.

fin1, fin2
Frequency Inputs
fin1 and fin2 are inputs to the divide-by-N receive and
transmit counters, respectively. These signals are typically
derived from the loop VCO and are ac coupled. For larger
amplitude signals (standard CMOS logic levels), dc coupling
may be used. The minimum input level is 200 mVp-p.

VDD
Positive Power Supply
This pin is the positive supply potential and may range from
+ 2.5 to + 5.5 V with respect to VSS.

Table 1_ MC145166/67 Divide Ratios and VCO Frequencies
Channels

Base (Mode=l)

Handset (Mode=O)
fin2-Transmit

fin1-Receive

fin2-Transmit

fin1-Receive

03

02

01

DO

CH#

Fvco (MHz)

+N

Fvco (MHz)

+N

Fvco (MHz)

+N

Fvco (MHz)

+N

0
0
0
0
0
0
0
1
1
1

0
0
0
1
1
1
1
0
0
0

0
1
1
0
0
1
1
0
0
1

1
0
1
0
1
0
1
0
1
0

1
2
3
4
5
6
7
8
9
10

49.670
49.845
49.860
49.770
49.875
49.830
49.890
49,930
49,990
49,970

9934
9969
9972
9954
9975
9966
9978
9986
9998
9994

35.915
35.935
35.975
36.015
36.035
36.075
36.135
36,175
36,235
36,275

7183
7187
7195
7203
7207
7215
7227
7235
7247
7255

46.610
46.630
46.670
46,710
46,730
46.770
46.830
46,870
46,930
46,970

9322
9326
9334
9342
9346
9354
9366
9374
9386
9394

38,975
39,150
39,165
39,075
39.180
39.135
39.195
39,235
39,295
39,275

7795
7830
7833
7815
7836
7827
7839
7847
7859
7855

NOTES:
1. Other input combinations will be defaulted to channell 0
2. Half the frequency of fin2 for MC145160
3. 0 = logic low, 1 = logic high.

MC145160.MC145166.MC145167
2·578

MOTOROLA COMMUNICATIONS DEVICE DATA

VCC(3.6V)

lkn
L -_ _

lOIlF

~

I

O.OlI1 F

':'

I
12 pF
I ~ '----- TO 1ST
:
MIXER

1.. .-----

39kn

27 pF

100kn 68 P F r Y
l 47 PFfLtMP:9::6C

2.7kQ

47kn
lN5462A

f ':'

: 33 pF

r ':

3.3kQ

MPS9426C
10 pF

0

10.24 MHz

3 pF
T02N0--l
MIXER

OSCout

~nl

V+
15

POl
VOO
DO
PD2
MCl45166
01
02

12

OSCin

03

[0

~n2

14
13
11
10
9

VSS

':'

V+
LOCK DETECT (LO)

2.7kn
TO PIN 1
OF
MC2831A

r-----;~--_r-.

RFTxAMP

47kn

MPS9426C

MPS9426C

lN5462A

Figure 5. MC145166 Circuit Example

MOTOROLA COMMUNICATIONS DEVICE DATA

MC145160.MC145166.MC145167
2-579

1\)5:

&.0
Q) .....

0",",

U1

.....
~

0.455 MHz

i:
o
.....

U1
"'"'
.....

en
en

i:
o
.....

Ci
.....

g:

"TI

cij'

MC145166

c

~

!"

c

PHASE
DET
A

'U

rr-

»

"C

'!:!.

PD·R

46.610 MHz

--=l

i'j'

!!l-

0'
::s

-1

~

0 5kHZ

:;'

~s:

::x:
N

PHASE
DET
B

()

s::

@

o

a.
III

o

~

::J'

()

::s
(I)

~

s::
s::
c
z

o
~

oz

en
om
<

o
m

o
~
:I>

DC

r-8

MODE D3 D2

D1 DO

L.P. FILTER

rr

'U

o

PD·T

r r
..L

m-

:D

o

I

I

L.P. FILTER

j])

..L

MOTOROLA

-

SEMICONDUCTOR
TECHNICAL DATA

MC145161
Advance Information
Dual PLL for 30/39 MHz
Cordless Telephones

PSUFFIX
PLASTIC DIP
CASE 648

CMOS
The MC145161 is a dual phase-locked loop (PLL) frequency synthesizer
intended for use primarily in 30/39 MHz cordless phones with up to 10 channels.
This part contains two mask-programmable counter ROMs for receive and
transmit loops with two independent phase detect circuits. A common reference
oscillator and reference divider are shared by the receive and transmit circuits.
Frequency selection is accomplished via a 4-bit serial input.
Other features include a lock detect circuit for the transmit loop, illegal code
default, and a 5-kHz tone output.
• Applications: Bases and Handsets of Cordless Phones for the
Australian Market
• Synthesizes Up to Ten Channel Pairs
• Maximum Operating Frequency: 60 MHz @ Vin=200 mVp-p
• Operating Temperature Range: -40 to + 75°C
• Operating Voltage Range: 2.5 to 5.5 V
• On-Chip Oscillator Circuit Supports External Crystal
• Lock Detect Signal
• Operating Power Consumption: 3.0 mA @ 3.0 V
• Standby Mode for Power Savings: 1.5 mA @ 3.0 V

DWSUFFIX
SOG
CASE 751G
ORDERING INFORMATION
MC145161P
MC145l61DW

Plastic DIP
SOG Package

PIN ASSIGNMENT
OSCin

OSCout
MODE

VDD

SB

~nl

5k

PDl

DATA

VSS

ClK

PD2

NC

ill

ENB

~n2
NC = NO CONNECTION

This document contains information on a new product. Specifications and information herein are subject to change without notice.

MOTOROLA COMMUNICATIONS DEVICE DATA

MC145161
2-581

BLOCK DIAGRAM OF THE MC145161

Iv=5kHz
lin1

13-BIT DIVIDE-BV-N
RECEIVE COUNTER

14

~

13

PHASE
DET1

PD1

[\ 13
VDD

RECEIVE
ROM

LOCK
DET

TRANSMIT
ROM
3

,,
,,,

IFJ

10

• .[0

.1"'-------- - -.,

--,,
,,

,,
,

9

,,

ftn2

L __________

,,
,,

~

[\14

14-BIT
DIVIDE-BV-N
TRANSMIT
COUNTER

5kHz

PHASE
DET2

Iv

11

PD2

'AA.

oSCln

OSCoul

16

{>-

2

REFERENCE
COUNTER
DIVIDE-BV-2048

1

MODE

5kHz

-

Ir

I--

-

DECODE
LOGIC

I-~

4

fl

4-BITLATCH

---L

EN B

4-BITSIR

----L
----L

DliJA

5k~

VSS

CLK

• ON-CHIP PULL DOWN
PIN 12=VSS
PIN 15=VDD

MC145161
2-582

MOTOROLA COMMUNICATIONS DEVICE DATA

MAXIMUM RATINGS' (Voltages Referenced to VSS)
Symbol
VOO
Yin
lin, lout
IOO,ISS
Tstg

Rating
DC Supply Voltage
Input Voltage, All Inputs
DC Current Drain Per Pin
DC Current Drain VOO or VSS Pins
Storage Temperature Range

Value

Unit

-0.5 to +6.0

V

-0.5 to VOO +0.5

V

10

rnA

30

mA

-65 to +150

DC

• Maximum Ratings are those values beyond which damage to the device may occur. Functional
operation should be restricted to the limits in the Electrical Characteristics tables or Pin Descriptions section.

This device contains protection
circuitry to guard against damage due
to high static voltages or electric fields.
However, precautions must be taken to
avoid applications of any voltage higher
than maximum rated voltages to this
high-impedance circuit. For proper operation, Yin and Vout should be constrained to the range VSS:;; (Vin or
Vout):;;VOO·
Unused inputs must always be tied to
an appropriate logic voltage level (e.g.,
either VSS or VOO). Unused outputs
must be left open.

ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS, TA = 25DC)
Guaranteed Limit
Symbol

Characteristic

c

VOO

Power Supply Voltage Range

VOL

Output Voltage
(lout=O)

VOH

VIL

(Vin = VOO or 0)

Input Voltage
(Vout=0.5 V or VOO-0.5 V)

VIH

VOO

-

oLevel

2.5
5.5

1 Level

2.5
5.5

oLevel

2.5
5.5

Min

Max

Unit

2.5

5.5

V

0.05
0.05

V

-

2.45
5.45

-

1 Level

2.5
5.5

1.75
3.85

IOH

Output Current (Vout=2.2 V)
(Vout=5.0 V)

Source

2.5
5.5

-0.18
-0.55

IOL

(Vout=0.3 V)
(Vout=0.5 V)

Sink

2.5
5.5

0.18
0.55

OSCin, ~nl, fin2

2.5
5.5

Data, SB, Mode

2.5
5.5

IlL

IIH

Input Current
(Vin=O)

(Vin=VOO-0.5)

OSCin, finl, fin2

2.5
5.5

-

-

-

Cin

Input Capacitance

-

-

Cout

Output Capacitance

-

100

Standby Current, SB= VSS or Open

2.5
5.5

Idd

Operating Current
(200 mVp-p input at finl and ~n2, SB=VOO)

2.5
5.5

-

IOZ

Three-State Leakage Current
(Vout=O or 5.5 V)

5.5

-

Data, SB, Mode

MOTOROLA COMMUNICATIONS DEVICE DATA

2.5
5.5

-

0.75
1.65

V

-

mA

-30
-66

IlA

-

-0.05
-0.11
30
66

IlA

50
121
8.0

pF

-

8.0

pF

-

1.4
3.6

rnA

2.8
6.2

mA

±1.0

IlA

MC145161

2·583

SWITCHING CHARACTERISTICS (TA=25·C, Cl =50 pF)
Guaranteed Limit
Symbol

Characteristic

Figure #

VOO

Min

Max

Unit

200
100

ns

200
100

ns

5.0
4.0

I1S

3.0--5.0
3.0-5.0
3.0--5.0

-

12
60
60

MHz

3.0
5.0

100
50

ns

3.0
5.0

200
100

-

ns

lTlH

OUlpul Rise Time

1,5

3.0
5.0

lTHl

OUlpUI Fall Time

1,5

3.0
5.0

Ir,ll

Inpul Rise and Fall Time, OSCin

2

3.0
5.0

Imax

Inpul Frequency
Input = Sine Wave 200 mVp-p

tsu

OSCin
~nl
~n2

Setup Time

DATAtoClK

3

ENBtoClK

III
tree
tw

Hold Time, ClK to DATA

3

3.0
5.0

80
40

Recovery Time, ENB to ClK

3

3.0
5.0

80
40

3.0
5.0

80
60

Input Pulse Width, ClK and ENB

4

ns
ns

-

-

SWITCHING WAVEFORMS

tf

trHl

ANY
OUTPUT

Figure 1.

DATA

Figure 2.

D3

tsu

ClK _....:5",0"1..:::..oJ

Isu~trec

ENB-----------------------------

50%

PREVIOUS
DATA LATCHED

Figure 3.

ENB, ------1f~

ClK

tw

50%

L

Figure 4.

MC145161
2-584

MOTOROLA COMMUNICATIONS DEVICE DATA

ClK, DATA
Clock, Data (Pins 6, 5)
These pins provide the BCD input by using serial channel
programming. Logical high represents a 1. Each low-to-high
transition of the clock shifts one bit of data into the on-chip
shift register.
ENB
Enable (Pin 8)
The enable pin controls the data transfer from the shift
register to the 4-bit latch. A positive pulse latches the data.

PIN DESCRIPTIONS
INPUTS
OSCin/OSCout
Reference Oscillator Input/Output (Pins 16, 1)
These pins form a reference oscinator when connected
to an external parallel-resonant crystal. For a 30/39 MHz
cordless phone application, a 10.24-MHz crystal is
needed. OSCin may also serve as input for an externally
generated reference signal. This signal is typically ac
coupled to OSCin, but for larger amplitude signals
(standard CMOS logic levels) dc coupling may also be
used. In the external reference mode, no connection is
required for OSCout.

OUTPUTS
5k
5-kHz Tone Signal (Pin 4)
This 5-kHz tone signal is derived from the reference
oscillator; this is an N-channel open-drain output.
lD
lock Detect Signal (Pin 10)
The lock detect signal is associated with the transmit loop.
The lock output goes high to indicate an out-of-Iock condition.
This is a P-channel open-drain output.

MODE
(Pin 2)
Mode is for determining whether the part is to be used in
the base or handset of a cordless phone. Internally, this pin
is used in the decoding logic for selecting the ROM address.
When high, the device is set in the base mode, and when low,
it is set in the handset mode. This input has an internal
pull-down device.

POl, PD2
Phase Detector Outputs (Pins 13, 11)
These are three-state outputs of the transmit and receive
phase detectors for use as loop error signals.
Frequency fv>fr or fv leading: Output=Negative pulses
Frequency fv,

--;=l

PO-R

-1

~

05kHZ

:::I

5'

L.P.FllTER

rr

c.>

~

co

s::

a
o
:Il

>
g

==
Ii
g
a.

PHASE
DET
B

~

:::I
«II

z

o
~

5z

CJl

om
o

~

>

DC

~

MODE DATA ClK ENB

VDD

L.P. FilTER

rr

"'II

s

PD·T

.L

m

s::
s::
c

o
~

I

I

[i)

.L

MOTOROLA

-

SEMICONDUCTOR
TECHNICAL DATA

MC145162
Advance Information

60 MHz Universal Programmable
Dual PLL Frequency Synthesizer
CMOS

.-

PSUFFIX
PLASTIC DIP
CASE 648

1

The MC145162 is a dual phase-locked loop (PLL) frequency synthesizer
especially designed for CT-1 cordless phone applications worldwide. This
frequency synthesizer is also for any products with frequency operation at 60 MHz
or below.
The device features fully programmable receive, transmit, reference, and
auxiliary reference counters accessed through an MCU serial interface. This
feature allows this device to operate In any CT-1 cordless phone application. The
device consists of two independent phase detectors for transmit and receive
loops. A common reference oscillator, driving two independent reference
frequency counters, provides independent reference frequencies for transmit and
receive loops. The auxiliary reference counter allows the user to select an
additional reference frequency for receive and transmit loops if required.
•
•
•
•
•
•
•
•
•
•
•
•
•

Operating Voltage Range: 2.5 to 5.5 V
Operating Temperature Range: - 40 to + 75°C
Operating Power Consumption: 3.0 mA @ 2.5 V
Maximum Operating Frequency: 60 MHz @ 200 mVp-p, VDD 2.5 V
3 or 4 Pins Used for Serial MCU Interface
Buill-In MCU Clock Output with Frequency of Reference Oscillator + 3/+ 4
Power Saving Mode Controlled by MCU
Lock Detect Signal
On-Chip Reference Oscillator Supports External Crystals to 16.0 MHz
Reference Frequency Counter Division Range: 16to 4095
Auxiliary Reference Frequency Counter Division Range: 16to 16,383
Transmit Counter Division Range: 16 to 65,535
Receive Counter Division Range: 16to 65,535

=

SOG
CASE 7519

ORDERING INFORMATION
MC145162P
MC145162D

Plastic DIP

SOG

PIN ASSIGNMENT

ill

ClK [ 1·

16P

ADin [ 2

ISP TxPDout

14~

~n·T

ENB

4

13

TxPS/trx

MCUCLK

S

12

VDD

VSS

6

11

RxPs/fRx

aSCout

7

10

aSCin

8

9

Din [ 3

This document contains Information on a new product. Specifications and Information herein are subject to change without notice.

MOTOROLA COMMUNICATIONS DEVICE DATA

DSUFFIX

RxPDout
fin·R

REV. 1

MC145162
2-587

BLOCK DIAGRAM

OSCin

7

OSCout

TRANSMIT
SELECT

MCUCLK

ADin

15 TxPDout

2
MCU INTERFACE PROGRAMMING
MODE CONTROL

CLK
Din
ENB

Tx
PHASE
DETECTOR

4

16

CONTROL REGISTER

iJ'i

TxPSlfrx
RxPSlfRx

RECEIVE
SELECT

Rx
PHASE
DETECTOR

10

RxPDout

VDD=PIN 12
VSS=PIN6

MC145162
2-588

MOTOROLA COMMUNICATIONS DEVICE DATA

MAXIMUM RATINGS' (Voltages Referenced to VSS)
Symbol
VDD
Yin
lin. lout
IDD. ISS
Tstg

Rating

Value

Unit

-0.5to + 6.0

V

- 0.5 to VDD + 0.5

V

DC Current Drain Per Pin

10

rnA

DC Current Drain VDD or VSS Pins

30

rnA

-65 to +150

'C

DC Supply Voltage
Input Voltage. All Inputs

Storage Temperature Range

This device contains protection circuitry
to guard against damage due to high static
voltages or electric fields. However. precautions must be taken to avoid application of any voltage higher than maximum
rated voltages to this high-impedance circuit. For proper operation. Yin and Vout
should be constrained to the range VSS ,;
(Vin or Vout) ,; VDD·
Unused pins must always be tied to an
appropriate logic voltage level (e.g .• either
VSS or VDD). Unused outputs must be left
open.

'Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the limits in the Electrical Characteristics tables or
Pin Descriptions section.

ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS. TA = 25'C)
Guaranteed Limit
Characteristic

Symbol
VDD

Power Supply Voltage Range

VOL

Output Voltage
(lout = 0)

VOH

VIL

(Vin

=VDD or 0)

Input Voltage
(Vout = 0.5 V or VDD - 0.5 V)

VIH

VDD

Min

Max

Unit

-

2.5

5.5

V

o Level

2.5
5.5

-

0.1
0.1

1 Level

2.5
5.5

o Level

2.5
5.5

1 Level

2.5
5.5

1.75
3.85

-

2.45
5.45

-

0.75
1.65

10H

Output Current (Vout = 2.2 V)
(Vout = 5.0 V)

Source

2.5
5.5

-0.18
-0.55

-

10L

(Vout = 0.3 V)
(Vout = 0.5 V)

Sink

2.5
5.5

0.18
0.55

-

OSCin. fin-To fin-R

2.5
5.5

-

ADin. CLK. Din. ENB

2.5
5.5

OSCin. fin-To fin-R
ADin. CLK. Din. ENB

IlL

IIH

Input Current
(Vin = 0)

(Vin

=VDD -

0.5)

V

V

rnA

-

-

-30
-66

-

-

-1.0
-1.0

2.5
5.5

-

30
66

2.5
5.5

-

5.0
5.0

J.tA

I'A

10Z

Three-State Leakage Current (Vout = 0 V or 5.5 V)

5.5

-

±100

nA

Cin

Input Capacitance

-

-

8.0

pF

Output Capacitance

-

-

8.0

pF

Standby Current
(All Counters are in Power-Down Mode with Oscillator On)

2.5
5.5

-

0.3
1.5

rnA

Operating Current
(200 mVp-p input at fin-T

2.5
5.5

3.0
10

rnA

Cout
IDD(stdby)
IDD

=60 MHz and fin-R =60 MHz. OSC = 10.24 MHz)

MOTOROLA COMMUNICATIONS DEVICE DATA

-

MC145162
2-589

SWITCHING CHARACTERISTICS (TA = 25"C. Cl = 50 pF)
Guaranteed Limit
Figure #

Vee

Max

Unit

tTlH

Output Rise Time

1

2.5
5.5

-

200
100

ns

ITHl

Output Fall Time

1

2.5
5.5

-

200
100

ns

tr• tf

Input Rise and Fall Time. OSCin

2

2.5
5.5

-

5.0
4.0

~s

tw

Input Pulse Width. ClK and ENS

3

2.5
5.5

80
60

-

ns

-

Symbol

Characteristic

Input Frequency
(Input = Sine Wave @ ;, 200 mVp-p

fmax

MHz

2.5-5.5
2.5-5.5
2.5-5.5

-

16
60
60

5

2.5-5.5
2.5-5.5

100
200

-

ns

OSCin
fin-T
fin-R
Data to ClK
ENSto ClK

Min

tsu

Setup Time

th

Hold Time. ClK to Data

5

2.5
5.5

80
40

-

ns

trec

Recovery Time. ENS to ClK

5

2.5
5.5

80
40

-

ns

tsul

Setup Time. ENS to ClK

4

2.5-5.5

80

-

ns

thl

Hold Time. ClK to ENS

4

2.5-5.5

600

-

ns

SWITCHING WAVEFORMS
tTHl
ClK. OSCin.

ANY
OUTPUT

lin-T.lin-R

y

_tr
tf~
~9:-0--%--------'- VDD
10%
VSS

Figure

ENS.

cJ

1.

Figure

tw

ADin.
Din

lVDD

50%

2.

VSS
Figure 3_
-

VDD

ClK
-

VDD

Vss

ClK

~1

Vss

ENS

TIl

t'oo

Vss

Figure 4_

MC145162
2-590

ENB High During Serial Transfer

ENS

___---It

50%

-tree

'--_ _ _ _
- VDD
PREVIOUS
DATA
lATCHED

VSS

Figure 5_ ENB Low During Serial Transfer

MOTOROLA COMMUNICATIONS DEVICE DATA

PIN DESCRIPTIONS
OSCln/OSCout
Reference Oscillator Input/Output (Pins 8. 7)
These pins form a reference oscillator when connected to
an external parallel-resonant crystal. Figure 6 shows the relationship of different crystal frequencies and reference
frequencies for cordless phone applications in various countries. OSCin may also serve as input for an extemally
generated reference signal which is typically ac coupled.
MCUCLK
System Clock (Pin 5)
This output pin provides a signal -of the crystal frequency
(OSCoutl divided by 3 or 4 that is controlled by a bit in the control register.
This signal can be a ciock source for the MCU or other systemclocks.
ADin. Din. CLK. ENB
Auxiliary Data In. Data In. Clock. Enable (Pins 2. 3. 1. 4)
These four pins provide an MCU serial interface for programming the reference counter, the transmit-channel
counter, and the receive-channel counter. They also provide
various controls of the PLL including the power saving mode
and the programming format.
TxPS/trx. RxPSlfRx
Transmit Power Save. Receive Power Save (Pins 13. 11)
For a normal application, these output pins provide the status of the internal power saving mode operation. If the
transmit-channels counter circuitry is in power down mode,
TxPS/trx outputs a high state. lithe receive-channels counter
circuitry is in power down mode, RxPS/fRx is set high. These
outputs can be applied for controlling the extemal power
switch forthe transmitter and the receiver to save MCU control
pins.
In the TX/Rx channel counter test mode, the TxPS/trx and
RxPS/fRx pins output the divided value of the transmit

channel counter (trx) and the receive channel counter (fRx),
respectively. This test mode operation is controlled by the control register. Details of the counter test mode are in the TX/Rx
Channel Counter Test section of this data sheet.
fln-Tlfln-R
Transmit/Receive Counter Inputs (Pins 14. 9)
fin-T and fin-R are inputs to the transmit and the receive
counters, respectively. These signals are typically driven from
the loop VCO and ac-coupled. The minimum input signal level
is 200 mVp-p @ 60.0 MHz.
.TxPDout/RxPDout
Transmit/Receive Phase Detector Outputs (Pins 15. 10)
These are three-state outputs of the transmit and receive
phase detectors for use as loop error signals (see Figure 7 for
phase detector output waveforms).
leading: output negative pulse.
Frequency fV > fR or
lagging: output positive pulse.
Frequency fV < fR or
Frequency fV fR and phase coincidence: output highimpedance state.
fR is the divided-down reference frequency at the phase detector input and fV is the divided-down VCO frequency at the
phase detector input.

=

=
=

tv
tv

=

LD
Lock Detect (Pin 16)
The lock detect signal is associated with the transmit loop.
The output at a high level indicates an out-of-Iock condition
(see Figure 7 for the IT> output waveform).
VDD
Positive Power Supply (Pin 12)
VDD is the most positive power supply potential ranging
from 2.5 to 5.5 V with respect to VSS.
VSS
Negative Power Supply (Pin 6)
VSS is the most negative supply potential and is usually connected to ground.

A

B~

fAt

eSCln
C

0"'-0--

fA2

eSCout

Crystal

+NValue

fRl-+B

fR2-+C

11.150 MHz

446

6.25 kHz

".0 kHz

11.150 MHz

223

12.5 kHz

10.240 MHz

512

5.0 kHz

12.000 MHz

600

5.0 kHz

Figure 6. Reference Frequencies for Cordless Phone Applications of Various Countries

MOTOROLA COMMUNICATIONS DEVICE DATA

MC145162
2-591

. IR, REFERENCE
(OSCin + REFERENCE COUNTER)

lv, FEEDBACK
(~n - T + Tx COUNTER OR
lin - R+ Rx COUNTER) _ _-';'...:..J

,

,
TXPDB~
RxPDout

*

~~~h~~u~--~-•

I

I

I

I

rn~~~h~'__~n~'

VH
HIGH IMPEDANCE

____~__

VH = High voltage level
VL = Low voltage level
"At this point, when both 'R and Iv are in phas.e, the output is lorced to near mid supply.
Note: The TxPDout and RxPDout generate error pulses during out-ol-Iock conditions. When locked in phase and frequency, the
output is high impedance and the voltage at that pin is determined by the low-pass filter capacitor.

Figure 7. Phase Detector/lock Detector Output Waveforms

MCU PROGRAMMING SCHEME
The MCU programming scheme is defined in two formats
controlled by the ENB input. If the enable signal is high
during the serial data transfer, control register/reference
frequency programming is selected. If the ENB is low,
programming of the transmit and receive counters is
selected. During programming of the transmit and receive
counters, both ADin and Din pins can input the data to the
transmit and receive counters. Both counters' data is
clocked into the Pll internal shift register at the leading
edge of the ClK signal. It is not necessary to reprogram
the reference frequency counter/control register when
using the enable signal to program the transmiVreceive
channels.
In programming the control register/reference frequency
scheme, the most significant bit (MSB) of the programming
word identifies whether the input data is the control word
or the reference frequency data word. If the MSB is 1, the
input data is the control word (Figure 8). Also see Figure
NO TAG and Table 1 for control register and bit function.
If the MSB is 0, the input data is the reference frequency
(Figure 9).
The reference frequency data word is a 32-bit word
containing the 12-bit reference frequency data, the 14-bit
auxiliary reference frequency counter information, the
reference frequency selection plus, the auxiliary reference
frequency counter enable bit (Figure 9).
If the AUX REF ENB bit is high, the 14-bit auxiliary
reference frequency counter provides an additional phase

MC145162

2-592

reference frequency output forthe loops. If AUX REF ENB
bit is low, the auxiliary reference frequency counter is
forced into power-down mode for current saving. (Other
power down modes are also provided through the control
register per Table 2 and Figure 8.) At the falling edge of
the ENB signal, the data is stored in the registers.
There are two. interfacing schemes for the universal
channel mode: the three-pin and the four-pin interfacing
schemes. The three-pin interfacing scheme is suited for
use with the MCU SPI (serial peripheral interface) (Figure
10), while the four-pin interfacing scheme is commonly
used for general I/O port connection (Figure 11).
For the three-pin interfacing scheme, the auxiliary data
select bit is set to O. All 32 bits of data, which define both
the 16-bittransmit counter and the 16-bit receive counter,
latch into the Pll internal register through the data in pins
at the leading edge of ClK. See Figures 12 and 13.
For the four-pin interfacing scheme, the auxiliary data
select bit is set to 1. In this scheme, the 16-bit transmit
counter's data enters into the ADin pin at the same time
as the 16-bit receive counter's data enters into the Din pin.
This simultaneous entry of the transmit and receive
counters causes the programming period of the four-pin
scheme to be half that of the three-pin scheme (see
Figures 14 and 15).
While programming Tx/Rx Channel Counter, the ENB
pin must be pulsed to provide falling edge to latch the
shifted dataafterthe rising edge of the last clock. Maximum
data transfer rate is 500 kbps.

MOTOROLA COMMUNICATIONS DEVICE DATA

CONTROL REGISTER IDENTIFIER = 1

MSB

lSB

ClK

ENB

J

L

Note: ENB must be high during the serial transfer.

Figure S. Programming Format of the Control Register

Table 1. Control Register Function Bits Description
Test Bit

Set to 1 for TxlRx channel counter test mode
Set to 0 for normal application

Aux Data Select

Set to 1 lor both ADin and Din pins inputting the transmit 16·bits data and receive 16-bits data respectively.
Set to 0 lor normal application interfacing with MCU serial peripheral Interface. Does not use ADin pin; tie ADin to VSS.

REFout + 3/+ 4

Iisello 1, REFout output Irequency is equal to OSCout + 3.
II set to 0, REFout output is OSCout + 4.

TxPD Enable

II set to 1, the transmit counter, transmit phase detector, and the associated circuitry is in power·down mode.
Tx PS/trx is set "High".

RxPD Enable

If set to 1, the receive counter, receive phase detector, and the associated circuitry is In power·down mode.
Rx PS/IRx is set "High".

Rei PO Enable

If set to 1, both 12-bit and 14-bit relerence frequency counters are in power-down mode.

Table 2. Control Register Power Down Bits Function
TxPD
Enable

RxPD
Enable

REF PO
Enable

Tx·Channel Counter

Rx-Channel Counter

Relerence
Frequency Counter

0

0

0

-

0

1

-

-

0

-

Power Down

0

1

0

-

Power Down

0

1

1

-

Power Down

1

0

0

Power Down

-

-

1

0

1

Power Down

-

Power Down

1

1

0

Power Down

Power Down

1

1

1

Power Down

Power Down

Power Down

Power Down

MOTOROLA COMMUNICATIONS DEVICE DATA

MC145162
2-593

_..

__ _ _ . _ - - - - - - - - - - - .... .....

REFERENCE FREQUENCY COUNTER
IDENTIFIER = 0

REFERENCE
FREQUENCY
SELECT

REFERENCE
FREQUENCY
COUNTER
DIVIDE RATIO

REFERENCE
FREQUENCY
SELECT

AUX REFERENCE
FREQUENCY COUNTER
DIVIDE RATIO
r -____-JA~____~,

14-BITS AUX REF FREQ
DATA

ClK

ENB

~

L

No1e: ENB must be high during the serial transfer.

Figure 9. Programming Format of the AuxlllarylReference Frequency Counters

Din
MCU
USING
SERIALj'ERIPHERAL
INTERrACE PORT

UNIVERSAL PLL

C;lK

AUX DATA BIT = 0
ENB

Figure 10. MCU Interface Using SPI

ADin

MCU
USING
NORMAL VO PORT

UNIVERSAL Pll
CLK

AUX DATA Blh 1

ENB

Figure 11. MCU Interface Using Normal 110 Ports with Both Din and ADln for Faster Programming Time

MC145162
2·594

MOTOROLA COMMUNICATIONS DEVICE DATA

CONTROL REGISTER IDENTIFIER = 1

CONTROL REGISTER DATA

r--------------------J~~--------------------~

AUX DATA SELECT = 0 ---------------------------'

ClK

L
Note: ENS must be high during the serial transfer.

Figure 12. Programming Format for Control Register (3-Pin Interfacing Scheme)

16·SIT Tx COUNTER
OIVIDE RATIO

ClK

ENS

16·SIT Rx COUNTER
DIVIDE RATIO

~~~
_ _ _ _-----IlL

Note: ENS must be low during the serial transfer.

Figure 13. Programming Format for Transmit and Receive Counters (3-Pin Interfacing Scheme)

CONTROL REGISTER IDENTIFIER = 1

CONTROL REGISTER DATA

AUX DATA SELECT = 1 - - - - - - - - - - - - - - - '

ClK

ENS

~

L

Note: ENS must be high during the serial transfer.

Figure 14. Programming Format for Control Register (4-Pin Interfacing Scheme)

MOTOROLA COMMUNICATIONS DEVICE DATA

MC145162
2-595

-<
-<..

16-SITTxCOUNTER

)

~_____DI_VD_E_R_ATI_O__~.

Din

CLK

ENS

»___________

~6.SIT RxCOUNTER

.

DIVIDE RATIO

n

~

>------------------

r:l-

~~

LAST

_____________

L_C_w_~

_______________~n~_______

Nole: ENS must be low during lhe serial transfer.

Figure 15. Programming Format for Transmit and Receive Counters (4-Pln Interfacing Scheme)

Table 3. Global CT-1 Reference Frequency Setting vs Channel Frequencies
Country

Channels Frequency

fRi

fR2

5.0 kHz

5.0 kHz

-

1.7147 MHz

6.25 kHz

1.0 kHz

1.7134140 MHz

6.25 kHz

1.0 kHz

U.S.A.

46149 MHz (10,15,25 Channels)

France

26141 MHz

Spain

31141 MHz

5.0 kHz

Australia

30139 MHz

U.K.
New Zealand

REFERENCE FREQUENCY SELECTION
AND PROGRAMMING
Figure 16 shows the bit function of the reference frequency
programming word. The user can either select the "fixed"
reference frequency for all channels accordingly or provide
a specific reference frequency for a particular channel by using
two reference frequency counters (e.g., for an application in
France, the base set transmit channel common fixed
reference frequency is 6.25 kHz or 12.5 kHz). (See Table 3
and Figure 6 for reference frequencies for various countries.)
However, transmit channels 6, 8, and 14 can be set to 25 kHz,
and channel 8 reference frequency can be set to 50 kHz. But
this reference frequency may not be applied to the receiving
side; therefore, the receiving side reference frequency must
be generated by another reference frequency counter. The
higher the reference frequency, the better the phase noise
performance and faster the lock time, but the PLL consumes
more current if both reference frequency counters are in
operation.

MC145162
2-596

6.25 kHzl12.S kHz

In general, the 12-bit reference frequency counter plus the
+ 4 and + 25 module can offer all the reference frequencies

for global CT-1 transmit and receive channel requirements.
Users can select their own reference frequency by introducing
the additional 14-bit auxiliary reference frequency counter.
Again, the 14-bit auxiliary reference frequency counter can
be shut down by the auxiliary reference enable bit in the
reference counter programming word by setting the bit to O.
At this state, the fR2 is automatically connected to point C (the
+ 25 block output), and fRt can be connected to point A or
B by setting the fR 1-S1 and fR1-S2 bits in the reference counter
program word. The 14-bit auxiliary reference frequency
counter data will be in "Don't Care" state.
If the 14-bit auxiliary reference frequency counter is enabled
(auxiliary reference enable = 1), then fR2 is automatically
connected to point 0 (14-bit counter output), and fR1 can be
selected to connect to point A, B, or C, depending on the bit
setting of fR 1-S1 and fR 1-S2.
Table 4 and Figure 16 describe the functions of the auxiliary
reference enable bit and the fR 1-S1 and fR1-S2 bits selection.

MOTOROLA COMMUNICATIONS DEVICE DATA

A
X~~+--l12.BITPROGRAMMABLE·

~ OSCin

REFERENCE COUNTER

D

L

14·BIT PROGRAMMABLE
D
OSCout ------_~ AUXILlARYREFERENCE t - - - - - - O
COUNTER
MAXIMUM
CRYSTAL FREQUENCY
16.0 MHz

Tx
PHASE
DETECTOR
Tx.()
SELECT

0

TxPDout

ill
Rx
PHASE
DETECTOR

RxPDout

0

REF FREQUENCY COUNTER IDENTIFIER = 0
REFERENCE
FREQUENCY
SELECT

REFERENCE
FREQUENCY
COUNTER

REFERENCE
FREQUENCY
SELECT

AUXILIARY REFERENCE
FREQUENCY COUNTER

14·BITS AUX REF FREQ
DATA

JL

CLK

L

ENB~
Note: ENB must be high during the serial transfer.

Figure 16. Reference Frequency Counter/Selection Programming Mode

Table 4. Bit Function and the Reference Frequency Selection Bit Setting of the
Reference Frequency Counter Programming Word
AUXREF
Enable

Auxiliary Reference Frequency
Counter Mode

Module
Select

fRl
SI

fRl
S2

fRl Routing

0

14-Bit Auxiliary Reference Frequency
Counter Disable

fR2 -t C

0
0
1
1

0
1
0
1

N/A
fRI-tA
fRI-t B
N/A

1

14-BII Auxiliary Reference Frequency
Counter Enable

fR2-t D

0
0
1
1

0
1
0
1

N/A
'RI-tA
'RI-tB
'RI-tC

NlA = Not Applicable

MOTOROLA COMMUNICATIONS DEVICE DATA

MC145162
2-597

POWER SAVING OPERATION
This PLL has a programmable power-saving scheme.
The transmit and receive counters and the reference
frequency counter can be powered down individually by
setting the TxPD enable, RxPD enable, and Ref PD
enable bits of the control register. The functions of the
power down control bits are explained in Table 2 and the
programming format is in Figure 8.

POWER SUPPLY

The output pins TxPSIfTx and RxPS/fRx output the
status of the internal power saving setting. If the bit TxPD
enable is set "high" (transmit counter is set to power-down
mode), then the TxPS/fTx pin will also output a "high"
state. This TxPS/fTx output can control an external power
switch to switch off the transmitter, as shown in Figure
17. This scheme can be applied to the RxPS/fRx output
to control the receiver power saving operation as
required.

UNIVERSAL DUAL PLL

Tx POWER-DOWN
ENABLE FLAG

Rx POWER-DOWN
ENABLE FLAG

Figure 17. TxPS/fyx and RxPSlfRx Outputs to Control Power Switches
of the Transmitter and the Receiver

MC145162
2-598

MOTOROLA COMMUNICATIONS DEVICE DATA

TXlRX CHANNEL COUNTER TEST
In normal applications. the TxPS/trx and the RxPS/fRxoutput pins indicate the power saving mode status. However. the
user can examine the Tx and Rx channel counter outputs by
setting the Test bit in the control register to 1. The final value

of the transmit-channel counter and the receive-channel
counter multiplex oulto TxPS/fTxand RxPS/fRx respectively.
The user can verify the divided-down output waveform associated with the RF input level in the PLL circuitry
implementation (Figure 18).

16·BITTx PROGRAMMABLE
CHANNELS COUNTER

trx

TxPS

IF TEST BIT IS SET TO 1. THE trx
AND fRx ARE MUXED OUT AT PINS
TxPS/trx AND RxPS/fRx.
RESPECTIVELY. FOR RxfTx
CHANNEL COUNTER TEST.

CONTROL REGISTER IDENTIFIER = 1

W\M~I-

16·BIT Rx PROGRAMMABLE
CHANNELS COUNTER

RxPS

Figure 18. RF Buffer Sensitivity

MOTOROLA COMMUNICATIONS DEVICE DATA

MC145162
2-599

Table 5; France CT-1 Base Set Frequency

Channel
Number

TxChannei
Frequency
(MHz)

Tx Counter Value
(Ref. Freq. =
6.25 kHz)

fin-R Input
Frequency (MHz)
[lstlF=10.7 MHz]

Rx Counter Value
(Ref. Freq. =
6.25 kHz)

1

26.4875

4238

30.7875

4926

2

26.4750

4236

30.7750

4924

3

26.4625

4234

30.7625

4922

4

26.4500

4232

30.7500

4920

5

26.4375

4230

30.7375

4918

6

26.4250

4228

30.7250

4916

7

26.4125

4226

30.7125

4914

8

26.4000

4224

30.7000

4912

9

26.3875

4222

30.6875

4910

10

26.3750

4220

30.6750

4908

11

26.3625

4218

30.6625

4906

12

26.3500

4216

30.6500

4904

13

26.3375

4214

30.6375

4902

14

26.3250

4212

30.6250

4900

15

26.3125

4210

30.6125

4898

Table 6. France CT-1 Handset Frequency

MC145162
2-600

Channel
Number

TxChannei
Frequency
(MHz)

Tx Counter Value
(Ref. Freq. =
6.25 kHz)

fin-R Input
Frequency (MHz)
[1st IF=10.7 MHz]

Rx Counter Value
(Ref. Freq. =
6.25 kHz)
5950

1

41.4875

6638

37.1875

2

41.4750

6636

37.1750

5948

3

41.4625

6634

37.1625

5946

4

41.4500

6632

37.1500

5944

5

41.4375

6630

37.1375

5942

6

41.4250

6628

37.1250

5940

7

41.4125

6626

37.1125

5938

8

41.4000

6624

37.1000

5936
5934

9

41.3875

6622

37.0875

10

41.3750

6620

37.0750

5932

11

41.3625

6618

37.0625

5930

12

41.3500

6616

37.0500

5928

13

41.3375

6614

37.0375

5926

14

41.3250

6612

37.0250

5924

15

41.3125

6610

37.0125

5922

MOTOROLA COMMUNICATIONS DEVICE DATA

Table 7. Spain CT-1 Base Set Frequency
Channel
Number

TxChannel
Frequency
(MHz)

Tx Counter Value
(Rei. Freq. =
5.00 kHz)

fln-R Input
Frequency (MHz)
[1 stlF=l 0.695 MHz]

Rx Counter Value
(Rei. Freq. =
5.00 kHz)

1

31.0250

6205

29.2300

5846

2

31.0500

6210

29.2550

5851

3

31.0750

6215

29.2800

5856

4

31.1000

6220

29.3050

5861

5

31.1250

6225

29.3300

5866

6

31.1500

6230

29.3550

5871

7

31.1750

6235

29.3800

5876

8

31.2000

6240

29.4050

5881

9

31.2500

6250

29.4550

5891

10

31.2750

6255

29.4800

5896

11

31.3000

6260

29.5050

5901

12

31.3250

6265

29.5300

5906

Channel
Number

TxChannel
Frequency
(MHz)

Tx Counter Value
(Ref. Freq. =
5.00 kHz)

fln-R Input
Frequency (MHz)
[lstlF=10.7 MHz]

Rx Counter Value
(Rei. Freq. =
5.00 kHz)
4066

Table 8. Spain CT-1 Handset Frequency

1

39.9250

7985

20.3300

2

39.9500

7990

20.3550

4071

3

39.9750

7995

20.3800

4076

4

40.0000

8000

20.4050

4081

5

40.0250

8005

20.4300

4086

6

40.0500

8010

20.4550

4091

7

40.0750

8015

20.4800

4096

8

40.1000

8020

20.5050

4101

9

40.1500

8030

20.5550

4111

10

40.1750

8035

20.5800

4116

11

40.2000

8040

20.6050

4121

12

40.2250

8045

20.6300

4126

Channel
Number

TxChannel
Frequency
(MHz)

1

1.7820

2

Table 9. New Zealand CT-1 Base Set Frequency
lin-R Input
Frequency (MHz)
[1st IF=10.7 MHz]

Rx Counter Value
(Rei. Freq. =
6.25 kHz)

1782 ""'\

29.7625

4762

1.7620

1762

29.7500

4760

3

1.7420

1742

29.7375

4758

4

1.7220

1722

29.7250

4756

5

1.7020

1702..-/

29.7125

4754

6

34.3500

5496,

29.7000

4752

7

34.3625

5498

29.6875

4750

8

34.3750

5500

29.6750

4748

9

34.3875

5502

29.6625

4746

10

34.4000

5504../

29.6500

4744

Tx Counter Value

MOTOROLA COMMUNICATIONS DEVICE DATA

> Rei Freq
= 1.0 kHz

>Ref Freq
- 6.25 kHZ

MC145162
2-601

Table 10. New Zealand CT-1 Handset Frequency
Channel
Number

Tx Channel
Frequency
(MHz)

Tx Counter Value
(Ref. Freq. =
6.25 kHz)

1

40.4625

6474

2.2370 ""'\

fin-R Input
Frequency (MHz)

Rx Counter Value
2237 ""'\

2

40.4500

6472

2.2170

3

40.4375

6470

2.1970

2217

4

40.4250

6468

2.1770

5

40.4125

6466

2.1570 J

2157J

6

40.4000

6464

23.6500)

3784)

7

40.3875

6462

23.6625

8

40.3750

6460

23.6750

9

40.3625

6458

23.6875

10

40.3500

6456

23.700a...J

>- Ref Freq
- 455 kHz

2197

>- Ref Freq
= 1.0 kHz

2177

3786

(>

Ref Freq
- 10.7 kHz

3788

(> Ref Freq
- 6.25 kHz

3790

3792J

Table 11. Australia CT-1 Base Set Frequency
Channel
Number

Tx Channel
Frequency
(MHz)

Tx Counter Value
(Ref. Freq. =
5.00 kHz)

fin-R Input
Frequency (MHz)
[1st IF=10.695 MHz]

Rx Counter Value
(Ref. Freq. =
5.00 kHz)

1

30.0750

6015

29.0800

5816

2

30.1250

6025

29.1300

5826

3

30.1750

6035

29.1800

5836

4

30.2250

6045

29.2300

5846

5

30.2750

6055

29.2800

5856

6

30.1000

6020

29.1050

5821

7

30.1500

6030

29.1550

5831

8

30.2000

6040

29.2050

5841

9

30.2500

6050

29.2550

5851

10

30.3000

6060

29.3050

5861

Table 12. Australia CT-1 Handset Frequency

MC145162
2-602

Channel
Number

Tx Channel
Frequency
(MHz)

Tx Counter Value
(Ref. Freq. =
5.00 kHz)

fin-R Input
Frequency (MHz)
[1st IF=10.7 MHz]

Rx Counter Value
(Ref. Freq. =
5.00 kHz)

1

39.7750

7955

19.3800

3876

2

39.8250

7965

19.4300

3886

3

39.8750

7975

19.4800

3896

4

39.9250

7985

19.5300

3906

5

39.9750

7995

19.5800

3916

6

39.8000

7960

19.4050

3881

7

39.8500

7970

19.4550

3891

8

39.9000

7980

19.5050

3901

9

39.9500

7990

19.5550

3911

10

40.0000

8000

19.6050

3921

MOTOROLA COMMUNICATIONS DEVICE DATA

Table 13. U.K. CT-1 Base Set Frequency
Channel
Number

TxChannel
Frequency
(MHz)

Tx Counter Value
(Ref. Freq. =
1.00 kHz)

fln-R Input
Frequency (MHz)
[latlF=10.7 MHz)

Rx Counter Value
(Ref. Freq. =
6.25 kHz)

1

1.6420

1642

36.75625

5881

2

1.6620

1662

36.76875

5883

3

1.6820

1682

36.78125

5885

4

1.7020

1702

36.79375

5887

5

1.7220

1722

36.80625

5889

6

1.7420

1742

36.81875

5891

7

1.7620

1762

36.83125

5893

8

1.7820

1782

36.84375

5895

Channel
Number

TxChannel
Frequency
(MHz)

Table 14. U.K. CT-1 Handset Frequency
Tx Counter Value
(Ref. Freq. =
6.25 kHz)

fin-R Input
Frequency (MHz)
[1 at IF=455 kHz)

Rx Counter Value
(Ref. Freq. =
1.00 kHz)

1

47.45625

7593

2.097

2097

2

47.46875

7595

2.117

2117

3

47.48125

7597

2.137

2137

4

47.49375

7599

2.157

2157

5

47.50625

7601

2.177

2177

6

47.51875

7603

2.197

2197

7

47.53125

7605

2.217

2217

8

47.54375

7607

2.237

2237

MOTOROLA COMMUNICATIONS DEVICE DATA

MC145162
2-603

Table 15. U.S.A. CT-l Base Set Frequency
Channel
Number

Tx Channel
Frequency
(MHz)

Tx Counter Value
(Ref. Freq. =
5.00 kHz)

fin-R Input
Frequency (MHz)
[1st IF=10.695 MHz]

Rx Counter Value
(Ref. Freq. =
5.00 kHz)

1

46.610

9322

38.975

7795

2

46.630

9326

38.150

7830

3

46.670

9334

38.165

7833

4

46.710

9342

39.075

7815

5

46.730

9346

39.180

7836

6

46.770

9354

39.135

7827

7

46.830

9366

39.195

7839

8

46.870

9374

39.235

7847

9

46.930

9386

39.295

7859

10

46.970

9394

39.275

7855

Table 16. U.S.A. CT-l Handset Frequency

MC145162
2-604

Channel
Number

Tx Channel
Frequency
(MHz)

Tx Counter Value
(Ref. Freq. =
5.00 kHz)

fin-R Input
Frequency (MHz)
[1st IF=10.7 MHz]

Rx Counter Value
(Ref. Freq. =
5.00 kHz)

1

49.670

9934

35.915

7183

2

49.845

9969

35.935

7187

3

49.860

9972

35.975

7195

4

49.770

9954

36.015

7203

5

49.875

9975

36.035

7207

6

49.830

9966

36.075

7215

7

49.890

9978

36.135

7227

8

49.930

9986

36.175

7235

9

49.990

9998

36.235

7247

10

49.970

9994

36.275

7255

MOTOROLA COMMUNICATIONS DEVICE DATA

Table 17. Korea CT-1 Base Set Frequency
Channel
Number

TxChannel
Frequency
(MHz)

Tx Counter Value
(Ref. Freq. =
5.00 kHz)

fin-R Input
Frequency (MHz)
[1st IF=10.695 MHz]

Rx Counter Value
(Ref. Freq. =
5.00 kHz)

1

46.610

9322

38.975

7795

2

46.630

9326

38.150

7830

3

46.670

9334

38.165

7833

4

46.710

9342

39.075

7815

5

46.730

9346

39.180

7836

6

46.770

9354

39.135

7827

7

46.830

9366

39.195

7839

8

46.870

9374

39.235

7847

9

46.930

9386

39.295

7859

10

46.970

9394

39.275

7855

11

46.510

9302

39.000

7800

12

46.530

9306

39.015

7803

13

46.550

9310

39.030

7806

14

46.570

9314

39.045

7809

15

46.590

9318

39.060

7812

Channel
Number

TxChannel
Frequency
(MHz)

Table 18. Korea CT-1 Handset Frequency
Tx Counter Value
(Ref. Freq. =
5.00 kHz)

fin-R Input
Frequency (MHz)
[lstlF=10.7 MHz]

Rx Counter Value
(Ref. Freq. =
5.00 kHz)

1

49.670

9934

35.915

7183

2

49.845

9969

35.935

7187

3

49.860

9972

35.975

7195

4

49.770

9954

36.015

7203

5

49.875

9975

36.035

7207

6

49.830

9966

36.075

7215

7

49.890

9978

36.135

7227

8

49.930

9986

36.175

7235

9

49.990

9998

36.235

7247

10

49.970

9994

36.275

7255

11

49.695

9939

35.815

7163

12

49.710

9942

35.835

7167

13

49.725

9945

35.855

7171

14

49.740

9948

35.875

7175

15

49.755

9951

35.895

7179

MOTOROLA COMMUNICATIONS DEVICE DATA

MC145162

2-605

MOTOROLA

-

SEMICONDUCTOR
TECHNICAL DATA

MC145168
MC145169

Advance Information
Dual PLLs for 46/49 MHz
Cordless Telephones
CMOS

PSUFFIX
PLASTIC DIP
CASE64B

These devices are dual phase-locked loop frequency synthesizers intended
for use primarily in 46/49 MHz cordless phones with up to 15 channels. These
parts conlain two mask-programmable counter ROMs for receive and transmit
loops with two independent phase detect circuits. A common reference oscillator
and reference divider are shared by the receive and transmit circuits.
Other features include a lock detect circuit for the transmit loop, illegal code
default, a buffered oscillator output for mixing purposes in the system, and a
5.0-kHz tone output.

DWSUFFIX
SOG
CASE 751G

•
•
•
•
•
•
•
•

Maximum Operating Frequency: 60 MHz @ Vin=200 mVp-p
Operating Temperature Range: -40 to + 75°C
Operating Voltage Range: 2.5 to 5.5 V
On-Chip Oscillator Circuit Supports External Crystal
Operating Power Consumption: 3.0 mA @ 3.0 V
Lock Detect Signal
Standby Mode for Power Savings: 1.5 mA @ 3.0 V
Two Versions:
MC145168 - Up to 15-Channel ROM with 4-Bit Binary Code Input for
Channel Pair Selection
MC145169 - Up to 15-Channel ROM with Serial Interface for Channel
Pair Selection
• Custom 20-Channel ROM Versions of the MC145169 are Possible; Consult
Factory

ORDERING INFORMATION

MC145168
OSCeut
MODE

MCI4516BP
MCI4516BDW

Plastic DIP
SOG Package

MC145169P
MC145169DW

Plastic DIP
SOG Package

MC145169
OSCin
VDD

OSCout

OSCin

MODE

VDD

SB

~nl

SB

linl

5k

POI

5k

POI.

DO

VSS

DATA

VSS

01

PD2

CLK

PD2

02

1J)

NC

1J)

03

~n2

ENB

'in2
NC = NO CONNECTION

This document contains inlonnation on a new product. Specifications and Inlonnatlon herein are subject to change without notice.

MC145168.MC145169
2-606

MOTOROLA COMMUNICATIONS DEVICE DATA

BLOCK DIAGRAM

'A,

IV
14-BIT DIVIDE-BY-N
RECEIVE COUNTER

14

r-

13

PHASE
DET1

PD1

Ir
1'14
VDO

RECEIVE
ROM

--:J-----_
9

TRANSMIT
ROM

10

• ,ill

1'14

14-BIT DIVIDE-BY-N
TRANSMIT COUNTER

fin2

IP

LOCK
DET

3*

Iv

r--

11

PHASE
DET2

PD2

-------

16
OSCin

1
OSCOU!

t>-

2*

!
REFERENCE
COUNTER 11 BITS
DIVIDE-BY-2048

,..------ -,
I

5*

,, 6*
, 7*
,,
8*
,

r--

5kHz

0
0

I

-

MODE

DECODE
LOGIC

0

MC145168
(FOR MAXIMUM
UP TO 15
CHANNELS)

0

L ______

---1
5k

--

5-BITLAT

4

- ----

CH~

ENB

PIN 12 = VSS
PIN 15=VDD

MC145169
(FOR MAXIMUM
UPT020
CHANNELS")

5

5-BIT SIR

~CL K
~DATA,

~-----------------~

*On chip pull-down,
**The standard MC145169 is 15 channels; see Tables 1 and 2. Cus10m versions up to 20 channels are possible.

MOTOROLA COMMUNICATIONS DEVICE DATA

MC145168.MC145169
2-607

MAXIMUM RATINGS' (Voltages Referenced to VSS)
Symbol
VDD
Yin
lin. lout
IDD.ISS
TstQ

Rating
DC Supply Voltage
Input Voltage. All Inputs
DC Current Drain Per Pin
DC Current Drain VDD or VSS Pins
Storage Temperature Range

Value

Unit

-0.5 to +6.0

V

-0.5 to VDD+0.5

V

10

mA

30

mA

-65 to + 150

°C

• Maximum Ratings are those values beyond which damage to the device may occur. Functional
operation should be restricted to the limits in the Electrical Characteristics tables or Pin Descriptions section.

This device contains protection circuitry to guard against damage due to
high static voltages or electric fields.
However. precautions must be taken to
avoid applications of any voltage higher
than maximum rated voltages to this
high-impedance circuit. For proper operation. Yin and Vout should be constrained to the range VSS:;; (Vin or
Vout) ",VDD·
Unused inputs must always be tied to
an appropriate logic voltage level (e.g .•
either VSS or VDD). Unused outputs
must be left open.

ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS. TA = 25°C)
Guaranteed Limit
Symbol

Characteristic

VDD

Power Supply Voltage Range

VOL

Output Voltage
(lout = 0)

VOH
VIL

(Vin = VDD or 0)
Input Voltage
(Vout = 0.5 V or VDD - 0.5 V)

VIH

Max

-

2.5

5.5

V

o Level

2.5
5.5

-

0.05
0.05

V

1 Level

2.5
5.5

2.45
5.45

o Level

2.5
5.5

-

1 Level

2.5
5.5

1.75
3.85

-

-

0.75
1.65

Source

2.5
5.5

-0.18
-0.55

-

10L

(Vout = 0.3 V)
(Vout = 0.5 V)

Sink

2.5
5.5

0.18
0.55

-

OSCin. fin1. fin2

2.5
5.5

-

-30
-66

DATA. S8. Mode

2.5
5.5

-

-0.05
-0.11

OSCin. ~n1. fin2

2.5
5.5

-

30
66

DATA. S8. Mode

2.5
5.5

-

50
121

IIH

(Vin = VDD - 0.5)

V

-

Output Current (Vout = 2.2 V)
(Vout = 5.0 V)

Input Current
(Vin = 0)

Unit

-

10H

IlL

mA

JlA

JlA

Input Capacitance

-

-

Cout

Output Capacitance

-

-

8.0

pF

IDD

Standby Current. S8 = VSS or Open

2.5
5.5

-

-

1.4
3.6

rnA

Idd

Operating Current
(200 mVp-p input at fin1. fin2. S8 = VDD)

2.5
5.5

-

2.8
6.2

rnA

10Z

Three-State Leakage Current
(Vout = 0 V or 5.5 V)

5.5

-

±1.0

JlA

Cin

MC145168.MC145169

2·608

Min

VOO

8.0

pF

MOTOROLA COMMUNICATIONS DEVICE DATA

SWITCHING CHARACTERISTICS (TA=25'C, CL=50pF)
Guaranteed Limit
Symbol

Characteristic

Figure #

VDD

lTLH

Output Rise Time

1,5

3.0
5.0

lTHL

Output Fall Time

1,5

3.0
5.0

tr,tl

Input Rise and Fall Time, OSCin

2

3.0
5.0

Imax

Input Frequency
Input=Sine Wave 200 mVp·p

th
trec
tw

Max

Unit

-

200
100

ns

200
100

ns

5.0
4.0

Ils

12
60
60

MHz

-

DATA to CLK

3

3.0
5.0

100
50

-

ENStoCLK

3

3.0
5.0

200
100

-

Hold Time (MC145169), CLK to DATA

3

3.0
5.0

80
40

Recovery Time (MC145169), ENS to CLK

3

3.0
5.0

80
40

Input Pulse Width (MC145169), CLK and ENS

4

3.0
5.0

80
60

-

Setup Time (MC145169)

tsu

3.0-5.0
3.0-5.0
3.0-5.0

OSCin
linl
lin2

Min

ns

ns
ns
ns

SWITCHING WAVEFORMS
trlH

tl

trHl

ANY

OUTPUT _ _J r

Figure 1.

Figure 2.

DATA

ClK

--="'-'
tsue;trec

50%
ENS ---------------------------~ PREVIOUS
DATA LATCHED

Figure 3.

ENS,

ClK

~O%

tw

~

L

Figure 4.

MOTOROLA COMMUNICATIONS DEVICE DATA

MC145168.MC145169
2-609

PIN DESCRIPTIONS
INPUTS
OSCln/OSCout
Reference Oscillator Input/Output (Pins 16, 1)
These pins form a reference oscillator when connected to
an external parallel-resonant crystal. For a 46/49 MHz
cordless phone application, a 10.24 MHz crystal is needed.
OSCin may also serve as input for an externally generated
reference signal. This signal is typically ac coupled to OSCin,
but for larger amplitude signals (standard CMOS logic levels)
dc coupling may also be used. In the external reference
mode, no connection is required for OSCout.
MODE
Mode Select (Pin 2)
Mode is for determining whether the part is to be used in the
base or handset of a cordless phone. Internally, this pin is
used in the decoding logic for selecting the ROM address.
When high, the device is set in the base mode, and when low,
it is set in the handset mode. This input has an internal
pull-down device.

S8
Standby (Pin 3)
The standby pin is used to save power when not
transmitting. When high, both the transmit and receive loops
are in operation. When low, the transmit loop is disabled,
thereby reducing power consumption. This input has an
internal pull-down device.

00-03 (MC145168 ONLy)
Data Inputs (Pins 5, 6, 7, 8)
These inputs provide the 4-bit binary code for selecting the
one of 15 channels for the transmit and receive loops. When
address data other than 1-15 are input, the decoding logic
defaults to channel 1. The frequency aSSignments, with
reference to Mode and 00-03, are shown in Tables 1 and 2.
These inputs have internal pull-down devices.
fin1, fin2
Frequency Inputs (Pins 14, 9)
fin1 andfin2areinputstothedivide-by-Nreceiveandtransmit
counters, respectively. These signals are typically derived
from the loop VCO and are ac coupled. The minimum input
level is 200 mVp-p. For larger amplitude Signals (standard
CMOS logic levels), dc coupling may be used.

MC145168.MC145169
2·610

DATA, ClK (MC145169 ONLy)
Data, Clock (Pins 5, 6)
These pins provide the binary input by using serial channel
programming. A logic high represents a 1. Each low-to-high
transition olthe clock shifts·one bit of data into the on-chip shift
register. Data is entered MSB first (see Figure 3).
ENB (MC145169 ONLy)
Enable (Pin 8)
The enable pin controls the data transfer from the shift
register to the latch. A positive pulse transfers the data. This
pin should normally be held low to avoid loading erroneous
data into the latch.
OUTPUTS
5k
5·kHz Tone Signal (Pin 4)
This is a 5 kHz tone signal derived from the reference
oscillator. This pin is a push-pull output.
lD
lock Detect Signal (Pin 10)
The lock detect signal is associated with the transmit loop.
The lock output goes high to indicate an out-of-Iock condition.
This is a P-channel open-drain output.
PD1/PD2
Transmit/Receive Phase Detector Outputs (Pins 13, 11)
These are three-state outputs of the transmit and receive
phase detectors for use as loop error signals.
Frequency fv > fr or fv leading: Negative pulses
Frequency fv < fr or fv lagging: Positive pulses
Frequency fv fr and phase coincidence: High-impedance
state
NOTE: Iv is the output 01 the N counter. fr is the output 01 the
reference counter.

=

POWER SUPPLY
VDD (Pin 15)
This pin is the positive supply potential and may range from
+2.5 to +5.5 V with respect to VSS.
VSS (Pin 12)
This pin is the negative supply potential and is usually
ground.

MOTOROLA COMMUNICATIONS DEVICE DATA

Table 1. Handset Frequencies of Each Corresponding Channel in a 46149 MHz
Cordless Phone for the Korean Market
Channels

RXFreq.

Receive (Note 3)

TXFreq.

Transmit

03

02

01

00

CHI

(MHz)

fln1 (MHz)

+N

(MHz)

fl n 2(MHz)

+N

Mode

0

0

0

1

1

46.610

35.915

7183

49.670

49.670

9934

0

0

0

1

0

2

46.630

35.935

7187

49.845

49.845

9969

0

0

0

1

1

3

46.670

35.975

7195

49.860

49.860

9972

0

0

1

0

0

4

46.710

36.015

7203

49.770

49.770

9954

0

0

1

0

1

5

46.730

36.035

7207

49.875

49.875

9975

0

0

1

1

0

6

46.770

36.075

7215

49.830

49.830

9966

0

0

1

1

1

7

46.830

36.135

7227

49.890

49.890

9978

0

1

0

0

0

8

46.870

36.175

7235

49.930

49.930

9986

0

1

0

0

1

9

46.930

36.235

7247

49.990

49.990

9998

0

1

0

1

0

10

46.970

36.275

7255

49.970

49.970

9994

0

1

0

1

1

11

46.510

35.815

7163

49.695

49.695

9939

0

1

1

0

0

12

46.530

35.835

7167

49.710

49.710

9942

0

1

1

0

1

13

46.550

35.855

7171

49.725

49.725

9945

0

1

1

1

0

14

46.570

35.875

7175

49.740

49.740

9948

0

1

1

1

1

15

46.590

35.895

7179

49.755

49.755

9951

0

NOTES:
1. O=logic low, 1 = logic high.
2. Power-up and Illegal inputs are defaulted to channell in the MC145169. Illegal inputs are defaulted to channell in MC145168.
3.-First IF frequency of receive is 10.695 MHz; Second IF is 455 kHz.
fin
4. +N= fref where ~n is the VCO frequency and fref Is the reference frequency (5.0 kHz).

Table 2. Base Frequencies of Each Corresponding Channel in a 46149 MHz
Cordless Phone for the Korean Market
Channels

RX Freq.

ReceIve (Note 3)

03

02

01

00

CHI

(MHz)

fin1 (MHz)

+N

0

0

0

1

1

49.670

38.975

7795

0

0

1

0

2

49.845

39.150

0

0

1

1

3

49.860

0

1

0

0

4

0

1

0

1

0

1

1

0

1

1

TXFreq.
(MHz)

TransmIt
fin2(MHz)

+N

Mode

46.610 -

46.610

9322

1

7830

46.630

46.630

9326

1

39.165

7833

46.670

46.670

9334

1

49.770

39.075

7815

46.710

46.710

9342

1

5

49.875

39.180

7836

46.730

46.730

9346

1

0

6

49.830

39.135

7827

46.770

46.770

9354

1

1

1

7

49.890

39.195

7839

46.830

46.830

9366

1

0

0

0

8

49.930

39.235

7847

46.870

46.870

9374

1

1

0

0

1

9

49.990

39.295

7859

46.930

46.930

9386

1

1

0

1

0

10

49.970

39.275

7855

46.970

46.970

9394

1

1

0

1

1

11

49.695

39.000

7800

46.510

46.510

9302

1

1

1

0

0

12

49.710

39.015

7803

46.530

46.530

9306

1

1

1

0

1

13

49.725

39.030

7806

46.550

46.550

9310

1

1

1

1

0

14

49.740

39.045

7809

46.570

46.570

9314

1

1

1

1

1

15

49.755

39.060

7812

46.590

46.590

9318

1

NOTES:
1. 0 = logic low, 1 = logic high.
2. Power·up and Illegal inputs are defaulted to channell in the MC145169.lIIegal inputs are defaulted to channell in MC145168.
3. First IF frequency of receive is 10.695 MHz; Second IF is 455 kHz.

~n

4. +N = fref where fin is the VCO frequency and fref is the reference frequency (5.0 kHz).

MOTOROLA COMMUNICATIONS DEVICE DATA

MC145168.MC145169
2-611

VCC (3.6 V)

lkn
I

12 pF

IIf~T01ST
~MIXER
IOI1F

J

,--~_I

I

O.OII1 F

':'

2.7kQ

47kQ

Ii

27pF

@~ M~; ::1"~ ~
MPS9426C

MPS9426C

1N5462A

10 pF

D

10.24 MHz

3pF
T02N0--l
MIXER

OSCout
15
5

OSCin
finl
POI

VOO
00

P02

01
[5

02
12

03

14
13
11
10

fin2

VSS
':'

MC145168
V+

LOCK OETECT (LO)

10pF

2.7kO
TO PIN 1

, - - - - - I I - - - t - - . OF
MC2831A
RFTxAMP
47kO

MPS9426C

lN5462A

MPS9426C

Figure 5. MC145168 Circuit Example

MC14516S.MC145169
2-612

MOTOROLA COMMUNICATIONS DEVICE DATA

s:

~

:Il

0

0.455 MHz

!j;:
(')

0

s:
s:
c
z

(5

~

(5

z

en
0

m

<

!!

III
C

iil
!"
0

(5

r
r

0

"C

m

»~

MCl45168

"'D

l>

fin·R

"Eo

PHASE
DET
A

0'

~

0
:::I

5'

PD·R

OSCout

46.510 MHz

r-

f

CJ

10.24MHz

11 HITlS

I

:l

-I

~

0 5 kHz

'"

;::
J:

L.P. FILTER

rr

OSCin

N

(')
0

a.

iD
~

fin·T

PHASE
DET
B

"'D

:::I'
0
:::I
CD

I

I

r r

UI

(:,

~

!!!.
III
OJ
f/I

;::

CD

...0
..."'"
(11

."

co

~

...

0
1\)"'"
,(11

."

...

...

."
WIO

DC
NOTE: Channel is set at #11

~

VDD -----0
MODE

03 02

01

DO

L.P. FILTER

...L

...
:::I'
OJ
:::I
:::I

PD·T

ill

...L

NS:

--

~O

--

01:001:0

(II

0)

0.455 MHz

co

i:
o
it
I'd

!!

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MOTOROLA

-

SEMICONDUCTOR
TECHNICAL DATA

MC145170
Advance Information

PLL Frequency Synthesizer
with Serial Interface

P SUFFIX

CMOS
The MC145170 is a single-chip synthesizer capable of direct usage in the MF,
HF, and VHF bands. A special architecture makes this PLL the easiest to program
in the industry. Either a bit- or byte-oriented format may be used. Due to the
patented BitGrabber™ registers, no address/steering bits are required for
random access of the three registers. Thus, tuning can be accomplished via a
2-byte serial transfer to the 16-bit N register.
The device features fully programmable Rand N counters, an amplifier at the
fin pin, on-chip support of an external crystal, a programmable reference output,
and both single- and double-ended phase detectors with linear transfer functions.
A new feature on the MC145170 is the C register (configuration register). The
C register allows the part to be configured to meet various applications. A
patented feature allows the C register to shut off unused outputs, thereby
minimizing noise and interference.
In order to reduce lock times and prevent erroneous data from being loaded
into the counters, a patented jam-load feature is included. Whenever a new divide
ratio is loaded into the N register, both the Nand R counters are jam loaded
with their respective values and begin counting down together. The phase
detectors are also initialized during the jam load.
• Operating Voltage Range: 2.5 to 6.0 V
• Maximum Operating Frequency:
160 MHz @ Vin = 500 mVp-p, 4.5-V Minimum Supply
100 MHz @ Vin = 500 mVp-p, 3.0-V Minimum Supply
• Operating Temperature Range: - 40 to 85°C
• R Counter Division Range: 5 to 32,767 Plus Direct Access to Phase Detector
Input
• N Counter Division Range: 40 to 65,535
Direct Interface to Motorola SPI and National MICROWIRETM Serial Data
Ports
• 180 MHz Versions Available (Part Numbers MC145170P1 and MC145170D1),
Consult Factory*
• Chip Complexity: 4800 FETs or 1200 Equivalent Gates
• See Application Note AN1207

PLASTIC DIP
CASE 648

DSUFFIX

SOG
CASE 7518

16

ORDERING INFORMATION
MC145170P
MC145170D

Plastic DIP
SOG Package

PIN ASSIGNMENT
OSCin
OSC oul

1·

16

VDD

2

15

v

14

R

REFoul
fin

4

Din
ENS l
CLK

7

DOU!

13

PDOU!

12

VSS

11

LD

10

tv
IR

*The functional voltage range for the suffix-l devices is 2.7 to 5.5 V. 180 MHz operation is with a 4.5 V minimum supply.
BitGrabber is a trademark of Motorola. Inc. MICROWIRE is a trademarl< of National Semiconductor Corp.
This document contains information on a new product. Specifications and Information herein are subject to change without notice.

MOTOROLA COMMUNICATIONS DEVICE DATA

REV. 1

MC145170
2-615

BLOCK DIAGRAM
OSCin
OSCout

REFout
lD

ClK
SHIFT
REGISTER
AND
CONTROL
lOGIC

Din

PDout

16

Dout
CPR
CPV

ENB

fin

4

tv

~
AMP

MAXIMUM RATINGS' (Voltages Referenced to VSS)
Symbol

Parameter

Unit

-0.5 to +6.0

V

Vin

DC Input Voltage

-0.5 to VDD +0.5

V

Vout

DC Output Voltage

-0.5 \0 VDD +0.5

V

VDD

DC Supply Voltage

Value

lin

DC Input Current, per Pin

±10

mA
rnA

lout

DC Output Current, per Pin

±20

IDD

DC Supply Current, VDD and VSS Pins

±30

rnA

PD

Power Dissipation, per Package

300

mW

Tstg

Storage Temperature

-65 to +150

DC

260

DC

TL

Lead Temperature, 1 mm from Case
for 10 seconds

This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However,
precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance
circuit. For proper operation, Vin and Vout
should be constrained to the range VSS!!>
(Vin or Vout)!!> VDD·
Unused inputs must always be tied to an
appropriate logic voltage level (e.g., either
VSS or VDD). Unused outputs must be left
open.

• Maximum Ratings are those values beyond which damage to the device may occur. Functional
operation should be restricted to the limits in the Electrical Characteristics tables or Pin Descriptions section.

MC145170
2-616

MOTOROLA COMMUNICATIONS DEVICE DATA

ELECTRICAL CHARACTERISTICS (Voltages Relerenced to VSS. TA = -40 to + 85°C)
Symbol
VDD

Parameter

Test Condition

Power Supply Voltage Range

Vee
V

Guaranteed
Limit

Unit

-

2.5 to 6.0

V

Vil

Maximum low-level Input Voltage
(Din. ClK. ENB)

2.5
4.5
6.0

0.50
1.35
1.80

V

VIH

Minimum High-level Input Voltage
(Din. ClK. ENB)

2.5
4.5
6.0

2.00
3.15
4.20

V

VHys

Minimum Hysteresis Voltage (ClK. EN B)

2.5
6.0

0.15
0.20

V

VOL

Maximum low-level Output Voltage
(Any Output)

lout = 20 ).LA

2.5
6.0

0.1
0.1

V

VOH

Minimum High-level Output Voltage
(Any Output)

lout = -20 ).LA

2.5
6.0

2.4
5.9

V

IOl

Minimum low-level Output Current
(PDout. REFout. IR. IV. lD. oilR. oilv)

Vout= 0.3 V
Vout=0.4V
Vout=0.5V

2.5
4.5
6.0

0.12
0.36
0.50

mA

IOH

Minimum High-level Output Current
(PDout. REFout. IR.Iv. lD. oilR. oilv)

Vout= 2.2 V
Vo ut=4.1 V
Vout=5.5V

2.5
4.5
6.0

-0.12
-0.36
-0.50

mA

IOl

Minimum low-level Output Current
(Doutl

Vout= 0.4 V

4.5

1.6

mA

IOH

Minimum High-level Output Current
(Doutl

Vout= 4.1 V

4.5

-1.6

mA

lin

Maximum Input leakage Current
(Din. ClK. ENB. OSCin)

Yin = VDD or VSS

6.0

±1.0

).LA

lin

Maximum Input Current
(lin)

Yin = VDD or VSS

6.0

±120

).LA

IOZ

Maximum Output leakage Current (PDoutl

Yin = VDD or VSS.
Output in High-Impedance State

6.0

± 100

nA

6.0

±5

).LA

IDD

Maximum Quiescent Supply Current

Yin = VDD or VSS; Outputs Open;
Excluding lin Amp Input Current Component

6.0

100

).LA

Idd

Maximum Operating Supply Current

lin = 160 MHz @ 500 mVp-p;
OSCin = 10 MHz @ 1 Vp-p;
IR.Iv. REFout = Inactive and No Connect;
OSCout. oI>v.  32

ClK
Serial Data Clock Input (Pin 7)
low-to-high transitions on Clock shift bits available at Din,
while high-to-Iow transitions shift bits from Dout. The chip's
16-1I2-stage shift register is static, allowing clock rates down
to dc in a continuous or intermittent mode.
Eight clock cycles are required to access the C register.
Sixteen clock cycles are needed for the N register. Either 15
or 24 cycles can be used to access the R register (see Table
1 and Figures 13, 14, and 15). .
ClK typically switches near 50% of VDD and has a
Schmitt-triggered input buffer. Slow ClK rise and fall times
are allowed. See the last paragraph of Din for more
information.
CAUTION
To guarantee proper operation of the power-on reset
(POR) circuit, the ClK pin must be held at the potential of either the VSS or VDD pin during power up.
Do not float or toggle the ClK input during power
up.

ENS
Active low Enable Input (Pin 6)
This pin is used to activate the serial interface to allow the

MOTOROLA COMMUNICATiONS DEVICE DATA

transfer of data tolfrom the device. When ENS is in an inactive
high state, shifting is inhibited, Dout is forced to the
high-impedance state, and the port is held in the initialized
state. To transfer data to the device, ENS (which must start
inactive high) is taken low, a serial transfer is made via Din
and ClK, and ENS is taken back high. The low-to-high
transition on ENS transfers data to the C, N, or R register
depending on the data stream length per Table 1.
CAUTION
Transitions on ENS must notbe attempted while ClK
is high. This puts the device out of synchronization
with the microcontroller. Resynchronization occurs
when ENS is high and ClK is low.
This input is also Schmitt-triggered and switches near 50%
of VDD, thereby minimizing the chance of loading erroneous
data into the registers. See the last paragraph of Din for more
information.
Dout
Three-State Serial Data Output (Pin 8)
Data is transferred out of the 16-1/2 stage shift register
through Dout on the high-to-Iow transition of ClK. This output
is a No Connect, unless used in one of the manners discussed
below.
Dout could be fed back to an MCU/MPU to perform a
wrap-around test of serial data. This could be part of a system
check conducted at power up to test the integrity of the
system's processor, PC board traces, solder joints, etc.
The pin could be monitored atan in-line QA test during board
manufacturing.
Finally, Dout facilitates troubleshooting a system.
REFERENCE PINS
OSCinlOSCout
Reference Oscillator Input/Output (Pins 1, 2)
These pins form a reference oscillator when connected to
terminals of an extemal parallel-resonant crystal. Frequencysetting capacitors of appropriate values as recommended by
the crystal supplier are connected from each pin to ground
(up to a maximum of 30 pF each, including stray capacitance). An external feedback resistor of 1 to 15 Mil is
connected directly across the pins to ensure linear operation
of the amplifier. The MC145170 is designed to operate with
crystals up to 15 MHz with a 4.5 to 6.0 V supply. With supplies
less than 4.5 V, up to 12-MHz crystals may be used. (See
Figure 9.)
If desired, an external clock source can be ac coupled to
OSCin. A 0.01-I1F coupling capaCitor is used for measurement
purposes and is the minimum size recommended for
applications. An external feedback resistor of approximately
10 Mil is required across the OSCin and OSCout pins in the
ac-coupled case (see Figure 8). OSCout is an internal node
on the device and should not be used to drive any loads (i.e.,
OSCout is unbuffered). However, the buffered REFout is
available to drive external loads.
The external signal level must be at least 1 Vp-p; the
maximum frequencies are given in the Loop Specifications
table. These maximum frequencies apply for R Counter divide
ratios as indicated in the table. For very small ratios, the
maximum frequency Is limited to the divide ratio times 2 MHz
when the internal phaselfrequency detectors are used
(Reason: the phaselfrequency detectors are limited to a
maximum input frequency of 2 MHz).

MC145170
2-621

If an external source is available which swings from at least
the VIL to VIH levels listed in the Electrical Characteristics
table, then dc coupling can be used. In the dc-coupled case,
no external feedback resistor Is needed. OSCout must be a
No Connect to avoid loading an internal node on the
MC145170, as noted above. For frequencies below 1 MHz,
dc coupling must be used. The R counter is a static counter
and may be operated down to dc. However, wave shaping
by a CMOS buffer may be required to ensure fast rise and
fall times into the OSCin pin.
Each rising edge on the OSCin pin causes the R counter
to decrement by one.
REFout
Reference Frequency Output (Pin 3)
This output is the buffered output of the crystal-generated
reference frequency or externally provided reference source.
This output may be enabled, disabled, or scaled via bits in
the C register (see Figure 13).
REFout can be used to drive a microprocessor clock input,
thereby saving a crystal. Upon power up, the on-chip
power-on-initialize circuit forces REFout to the OSCin
divided-by-B mode.
REFout is capable of operation to 10 MHz; see the Loop
Specifications table. Therefore, divide values for the
reference divider are restricted to two or higher for OSCin
frequencies above 10 MHz.
If unused, the pin should be floated and should be disabled
via the C register to minimize dynamic power consumption
and electromagnetic interference (EM I).
COUNTER OUTPUT PINS
fR
R Counter Output (Pin 9)
This signal is the buffered output of the 15-stage R counter.
fR can be enabled or disabled via the C register (patented).
The output is disabled (static low logic level) upon power up.
If unused, the output should be left disabled and unconnected
to minimize interference with extemal circuitry.
The fR signal can be used to verify the R counter's divide
ratio. This ratio extends from 5 to 32,767 and is determined
by the binary value loaded Into the R register. Also, direct
access to the phase detector via the OSCin pin is allowed by
choosing a divide value of 1 (see Figure 14). The maximum
frequency which the phase detectors operate is 2 MHz.
Therefore, the frequency of fR must not exceed 2 MHz unless
an external phase detector is used. The maximum frequency
for driving external phase detectors is TBD.
When activated, the fR signal appears as normally low and
pulses high.

tv

N Counter Output (Pin 10)
This signal is the buffered output of the 16-stage N counter.
fV can be enabled or disabled via the C register (patented).
The output is disabled (statiC low logic level) upon power up.
If unused, the output should be left disabled and unconnected
to minimize interference with external circuitry.
The fV signal can be used to verify the N counter's divide
ratio. This ratio extends from 40 to 65,535 and is determined
by the binary value loaded into the N register. The maximum
frequency which the phase detectors operate is 2 MHz.
Therefore, the frequency of fV must not exceed 2 MHz unless
an external phase detector is used. The maximum frequency
for driving external phase detectors is TBD.

MC145170

2-622

When activated, the fV signal appears as normally low and
pulses high.
LOOP PINS
fin
Frequency Input (Pin 4)
This pin is a frequency input from the VCO. This pin feeds
the on-chip amplifier which drives the N counter. This signal
Is normally sourced from an extemal voltage-controlled
oscillator (VCO), and is ac-coupled into fin. A 1OO-pF coupling
capacitor Is used for measurement purposes and is the
minimum size recommended for applications (see Figure 7).
The frequency capability of this Input is dependent on the
supply voltage as listed in the Loop Specifications table. For
small divide ratios, the maximum frequency is limited to the
divide ratio times 2 MHz when the Intemal phaselfrequency
detectors are used (Reason: the phaselfrequency detectors
are limited to a maximum frequency of 2 MHz).
For signals which swing from at least the VIL to VIH levels
listed In the Electrical Characteristics table, dc coupling may
be used. Also, for low frequency signals, dc coupling Is a
requirement. The N counter is a static counter and may be
operated down to dc. However, wave shaping by a CMOS
buffer may be required to ensure fast rise and fall times into
the fin pin.
Each rising edge on the fin pin causes the N counter to
decrement by 1.
PDout
Single-Ended Phase!Frequency Detector Output
(Pin 13)
This Is a three-state output for use as a loop error signal
when combined with an external low-pass filter. Through use
of a Motorola patented technique, the detector's dead zone
has been eliminated. Therefore, the phaselfrequency detector
is characterized by a linear transfer function. The operation
of the phaselftequency detector Is described below and is
shown in Figure 16.
POL bit (C7) in the C register low (see Figure 13)
Frequency of fV > fR or Phase of Iv Leading fR: negative
pulses from high impedance
Frequency of fV < fR or Phase of fV Lagging fR: positive
pulses from high impedance
Frequency and Phase of fV fR: essentially high-impedance state; voltage at pin determined by loop filter
POL bit (C7) high
Frequency of Iv > fR or Phase of fV Leading fR: positive
pulses from high impedance
Frequency of fV < fR or Phase of Iv Lagging fR: negative
pulses from high impedance
Frequency and Phase of fV
fR: essentially highimpedance state; voltage at pin determined by loop filter
This output can be enabled, disabled, and inverted via the
C register. If desired, PDout can be forced to the highimpedance state by utilization of the disable feature in the C
register (patented).

=

=

=

=

q.Randq.v
Double-Ended Phase/Frequency Detector Outputs
(Pins 14, 15)
These outputs can be combined externally to generate a
loop error Signal. Through use of a Motorola patented
technique, the detector's dead zone has been eliminated.
Therefore, the phaselfrequency detector is characterized by

MOTOROLA COMMUNICATIONS DEVICE DATA

a linear transler lunction. The operation 01 the phase/frequency detector is described below and is shown in Figure 16.
POL bit (C7) in the C register = low (see Figure 13)
Frequency 01 IV > IR or Phase 01 IV Leading 'R: Ijlv =
negative pulses, IjlR = essentially high
Frequency 01 IV < IR or Phase 01 IV Lagging 'R: Ijlv
essentially high, IjlR = negative pulses
Frequency and Phase 01 IV = 'R: Ijlv and CPR remain
essentially high, except lor a small minimum time period
when both pulse low in phase
POL bit (C7) = high
Leading 'R: IjlR =
Frequency 01 IV > fR or Phase 01
negative pulses, Ijlv = essentially high
Frequency 01 IV < IR or Phase 01 IV Lagging 'R: CPR =
essentially high, Ijlv = negative pulses
Frequency and Phase 01 IV = 'R: CPv and CPR remain
essentially high, except lor a small minimum time period
when both pulse low in phase
These outputs can be enabled, disabled, and interchanged
via the C register (patented).

=

tv

This output can be enabled and disabled via the C register
(patented). Upon power up, on-chip initialization circuitry
disables LD to a static low logic level to prevent a false "lock"
signal. If unused, LD should be disabled and left open.
POWER SUPPLY
VDD
Most Positive Supply Potential (Pin 16)
This pin may range from +2.5 to 6.0 V with respect to VSS.
For optimum performance, VDD should be bypassed to
VSS using low-inductance capacitor(s) mounted very close
fa the MC145170. Lead lengths on the capacitor(s) should
be minimized. (The very fast switching speed of the device
causes current spikes on the power leads.)
VSS
Most Negative Supply Potential (Pin 12)
This pin is usually ground. For measurement purposes, the
VSS pin is tied to a ground plane.

LD
Lock Detector Output (Pin 11)
This output is essentially at a high level with narrow
low-going pulses when the loop is locked (IR and IvaI the
same phase and Irequency). The output pulses low when IV
and fR are out of phase or different frequencies (see Figure
16).

MOTOROLA COMMUNICATIONS DEVICE DATA

MC145170
2-623

ENB

I

l

ClK

MSB
Din

C7 -

C6 -

~

C7

lSB

~

C6

~

~

CS

C4

~

C3

~

C2

~

Ct

~

CO

~

POL:

Selects the output polarity of the phaselfrequency detectors. When set high, this bit inverts
PDout and interchanges the 

ClK

C'l

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DON7 CARE BITS

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SEE BELOW

SEE BELOW

SEE BELOW

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ENB

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N

0

en

C'l

0'

n

~

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CD

III

n

II
:::II

III

CD

0
0
0
0
0
0
0
0

0
0
0
.0
0
0
0
0

0
0
0
0
0
0
0
0

0

2
3
4
5
6
7

NOTAUOWED
RCOUNTER = +1 (DIRECT ACCESS TO REFERENCE SIDE OF PHASEIFREQUENCY DETECTOR)
NOTAUOWED
NOTAUOWED
NOT AUOWED
R COUNTER = +5
R COUNTER =+6
RCOUNTER =+7

7
7

F
F

F
F

E
F

RCOUNTER =+32,766
RCOUNTER = +32,767

!

'---v-----'

c:

1/1

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.0'1

01'"

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OCTAL VALUE

.-J

HEXADECIMAL VALUE

!

L

DECIMAL EQUIVALENT

ENB

~~________________________________________________________________..J

0
0
0
0

0
0
0
0

0
0
0
0
0
0
0

0
0
0
0
0
0
0

F
F

F
F

0
1
2
3

NOT ALLOWED
NOT ALLOWED
NOT ALLOWED
NOT ALLOWED

2
2
2
2
2
2
2

5
6
7
8
9
A
B

NOT ALLOWED
NOT ALLOWED
NOT ALLOWED
N COUNTER = + 40
N COUNTER =+41
N COUNTER = +42
N COUNTER = + 43

F
F

E N COUNTER = + 65,534
F N COUNTER = +65

L

HEXADECIMAL VALUE

DECIMAL EQUIVALENT

Figure 15. N Register Access and Format (16 Clock Cycles Are Used)

fR
REFERENCE
OSCin+ R

Iv

FEEDBACK
(~n+N)

PDout

n'---------'I,n';

______-I'

!-:

"I

,

I

VL

*

-VH

------------+------ HIGH IMPEDANCE

Ur-'
I

-VL

---~~~:------~wr----,T'~---~---~~

!
U.
-~~
LJ~'------'U~'----~ur'-----r---~:

I

LD

i

=

VH High voltage level
VL = Low voltage level
'At this point, when both fR and tv are in phase, the output source is forced to near mid-supply.
NOTE: The PDout generates error pulses during out-of-Iock conditions. When locked In phase and frequency, the output Is high impedance
and the voltage althat pin is determined by the low-pass filter capacitor. PDout, q.R, and q.V are shown with the polarity bit (POL) = low;
see Figure 13 for POL.

Figure 16. Phase/Frequency Detectors and Lock Detector Output Waveforms

MC145170

2-626

MOTOROLA COMMUNICATIONS DEVICE DATA

DESIGN CONSIDERATIONS
CRYSTAL OSCILLATOR CONSIDERATIONS
The following options may be considered to provide a
reference frequency to Motorola's CMOS frequency synthesizers.
Use of a Hybrid Crystal Oscillator
Commercially available temperature-compensated crystal
oscillators (TCXOs) or crystal-controlled data clock oscillators
provide very stable reference frequencies. An oscillator
capable of CMOS logic levels at the output may be direct or
dc coupled to OSCin. If the oscillator does not have CMOS
logic levels on the outputs, capacitive or ac coupling to OSCin
may be used (see Figure 8).
For additional information about TCXOs and data clock
oscillators, please consult the latest version of the eem
Electronic Engineers Master Catalog, the Gold Book, or
similar publications.
Design an Off-Chip Reference
The user may design an off-chip crystal oscillator using
discrete transistors or ICs specifically developed for crystal
oscillator applications, such as the MC12061 MECl device.
The reference signal from the MECl device is ac coupled to
OSCin (see Figure 8). For large amplitude signals (standard
CMOS logic levels), dc coupling is used.
Use of the On-Chip Oscillator Circuitry
The on-Chip amplifier (a digital Inverter) along with an
appropriate crystal may be used to provide a reference source
frequency. A fundamental mode crystal, parallel resonant at
the desired operating frequency, should be connected as
shown in Figure 17.
The crystal should be specified for a loading capacitance
(Cl) which does not exceed 20 pF when used at the highest
operating frequency. larger Cl values are possible for lower
frequencies. Assuming R1 = 0 the shunt load capacitance
(CLl presented across the crystal can be estimated to be:

n.

CinCout
C1 • C2
Cl = _....::..:.--=:::o- + Ca + Cstray + - - Cin + Cout
C1 + C2
where
Cin = 5 pF (see Figure 18)
Cout = 6 pF (see Figure 18)
Ca = 1 pF (see Figure 18)
C1 and C2 =extemal capacitors (see Figure 17)
Cstray =the total equivalent external circuit stray capacitance appearing across the crystal terminals
The oscillator can be "trimmed" on-frequency by making a
portion or all of C1 variable. The crystal and associated
components must be located as close as possible to the
OSCin and OSCout pins to minimize distortion, stray
capacitance, stray inductance, and startup stabilization time.
Circuit stray capacitance can also be handled by adding the
appropriate stray value to the values for Cin and Couto For
this approach, the term Cstray becomes 0 in the above
expression for Cl.
Power is dissipated in the effective series resistance of the
crystal, Re, in Figure 19. The maximum drive level specified
by the crystal manufacturer represents the maximum stress
that the crystal can withstand without damage or excessive
shift in operating frequency. R1 in Figure 17 limits the drive
level. The use of R1 is not necessary in most cases.

MOTOROLA COMMUNICATIONS DEVICE DATA

To verify that the maximum dc supply voltage does not
cause the crystal to be overdriven, monitor the output
frequency at the REFout pin (OSCout is not used because
loading impacts the oscillator). The frequency should increase
very slightly as the dc supply voltage is increased. An
overdriven crystal decreases in frequency or becomes
unstable with an increase in supply voltage. The operating
supply voltage must be reduced or R1 must be increased in
value if the overdriven condition exists. The user should note
that the oscillator start-up time is proportional to the value of
R1.
Through the process of supplying crystals for use with
CMOS Inverters, many crystal manufacturers have developed expertise in CMOS oscillator design with crystals.
Discussions with such manufacturers can prove very helpful
(see Table 2).

I - - - - -

FREQUENcil
SYNTHESIZER

I

L_

I

___
OSCin

_~
OSCout

Rf

'May be needed in certain cases. See text.
Figure 17. Pierce Crystal Oscillator Circuit

~

aSCin oe-""""I--rl--iDv--'--'j---'I--oe OSCout

-Lt', I

I

"In

.;

L __ II

Ic

__ -1

II

-L

out I

.;

Cstray

Figure 18. Parasitic Capacitances of the Amplifier
andCstray

Nete: Values are supplied by crystal manufacturer
(parallel resonant crystal).
Figure 19. Equivalent Crystal Networks

MC145170

2-627

Recommended Reading
Technical Note TN-24, Statek Corp.
Technical Note TN-7, Statek Corp.
E. Hafner, "The Piezoelectric Crystal Unit-Definitions and
Method of Measurement", Proc. IEEE, Vol. 57, No.2, Feb.
1969.
D. Kemper, L. Rosine, "Quartz Crystals for Frequency

Control", Electro-Technology, June 1969.
P. J. Ottowitz, "A Guide to Crystal Selection", Electronic
Design, May 1966.
D. Babin, "Designing Crystal Oscillators", Machine Design,
March 7, 1985.
D. Babin, "Guidelines for Crystal Oscillator Design",
Machine Design, April 25, 1985.

Table 2. Partial List of Crystal Manufacturers
Phone

Name

Address

United States Crystal Corp.
Crystek Crystal
Statek Corp.
Fox Electronics

3605 McCart Ave., Ft. Worth, TX 76110
2371 Crystal Dr., Ft. Myers, FL 33907
512 N. Main St., Orange, CA 92668
5570 Enterprise Parkway, Ft. Myers, FL 33905

(817)
(813)
(714)
(813)

921-3013
936-2109
639-7810
693-0099

Note: Motorola cannot recommend one supplier over another and In no way suggests that this is a
complete listing of crystal manufacturers.

MC145170
2-628

MOTOROLA COMMUNICATIONS DEVICE DATA

PHASE-LOCKED LOOP-LOW PASS FILTER DESIGN

(A)

PDoul

'r'OO

"'n=

RI

t; =

C-:r
F(s) =

(9)

PDOUI

T~

"'n=

RI

KpKVCO
NRIC
N"'n
2KKVCO
RISC+ I

KpKVCO
NC(RI + R2)

R2

C

t; = 0.5 "'n

J

F(s) =

-)
( R2C + N
KKVCO

R2sC + I
(RI + R2)sC + I

(C)

"'n=

R
V

----'o/I."r-~t_I

veo
t; =
ASSUMING GAIN A IS VERY LARGE, THEN:
F(s) =

NOTE:
For (C), Rl is frequently split into two series resistors; each resistor is equal to Rl divided by 2. A capacitor Cc is then placed from the
midpoint to ground to further filter the error pulses. The value of Cc should be such that the corner frequency of this network does nol
significantly affect "'n.
DEFINITIONS:
N = Tolal Division Ratio in Feedback Loop
K (Phase Detector Gain) = VDDI 41t V/radian for PDout
K (Phase Detector Gain) = VDD/21t V/radian for V and R
2MtvCO
KVCO (VCO Gain) = - - !NVCO
For a nominal design starting point, the user rnighl consider a damping factor t;~0.7 and a natural loop frequency "'n ~ (21tfR/50)
where fR is the frequency al the phase detector input. Larger "'n values result in faster loop lock times and, for similar sideband filtering, higher fA-related VCO sidebands.
RECOMMENDED READING:
Gardner, Floyd M., Phaselock Techniques (second edition). New York, Wiley-Interscience, 1979.
Manassewilsch, Vadim, Frequency Synthesizers: Theory and Design (second edition). New York, Wiley-Interscience, 1980.
Blanchard, Alain, Phase-Locked Loops: Application to Coherent Receiver Design. New York, Wiley-Inlerscience, 1976.
Egan, William F., Frequency Synthesis by Phase Lock. New York, Wiley-Interscience, 1981.
Rohde, Ulrich L., Digital PLL Frequency Synthesizers Theory and Design. Englewood Cliffs, NJ, Prentice-Hall, 1983.
Berlin, Howard M., Design of Phase-Locked Loop Circuits, with Experiments. Indianapolis, Howard W. Sams and Co., 1978.
Kinley, Harold, The PLL Synthesizer Cookbook. Blue Ridge Summit, PA, Tab Books, 1980.
Seidman, Arthur H., Integrated Circuits Applications Handbook, Chapter 17, pp. 538-586. New York, John Wiley & Sons.
Fadrhons, Jan, "Design and Analyze PLLs on a Programmable Calculator," EDN. March 5, 1980.
AN535, Phase-Locked Loop Design Fundamentals, Molorola Semiconductor Products, Inc., 1970.
AR254, Phase-Locked Loop Design Articles, Motorola Semiconductor Products, Inc., Reprinted with permission from Electronic Design,
1987.
AN1207, The MC145170 in Basic HF and VHF Oscillators, Motorola Semiconductor Products, Inc., 1992

MOTOROLA COMMUNICATIONS DEVICE DATA

MC145170
2-629

V+
VDD
R
v

.>___.......:.15;.,. OUTPUT B
(OPEN·DRAIN
OUTPUn

~n

_ _.:.:11_ _-1

iiii __.:.:10'--_-1

r -_ _ _ _......;;13. TEST2

L__~==:t=======~----..!.. TEST 1

SUPPLY
PIN 12CONNECTIONS:
= VCC (V+ TO INPUT AMP AND 64/65 PRESCALER)
PIN 5 = VPD (V+ TO PHASE/FREQUENCY DETECTORS A AND B)
PIN 14 = VDD (V+ TO BALANCE OF CIRCUln
PIN 7 = GND (COMMON GROUND)

MAXIMUM RATINGS· (Voltages Referenced 10 GND, unless otherwise stated)
Symbol
VCC, VDD
VpD

Yin
Vout

Parameter

Value

DC Supply Voltage (Pins 12 and 14)

Unit

-0.5 to +6.0

V

VDD -0.5 to +9.5
VDD -0.5 to + 6.0

V

DC Input Voltage

-0.5 to VDD +0.5

V

DC Output Voltage (except OUTPUT B, PDout, R,

-0.5 to VDD +0.5

V

DC Supply Voltage (Pin 5)

MC145190
MC145191

This device contains protection clr·
cuitry to guard against damage due to
high static voltages or electric fields.
However, precautions must be taken to
avoid applications of any voltage high·
erthan maximum rated voltages to this
high·impedance circuit.

vl
-0.5 to VpD + 0.5

V

DC Input Current, per Pin (Includes VPD)

±10

mA

lout

DC Output Current, per Pin

±20

mA

IDD

DC Supply Current, VDD and GND Pins

±30

mA

PD

Power Dissipation, per Package

300

mW

-65to+150

DC

260

DC

Vout

lin,IPD

Tstg
TL

DC Output Voltage (OUTPUT B, PDout, R, V)

Storage Temperature
Lead Temperature, 1 mm from Case for 10 seconds

• Maximum Ratings are those values beyond which damage to the device may occur. Func·
tional operation should be restricted to the limits in the Electrical Characteristics tables or
Pin Descriptions section.

MOTOROLA COMMUNICATIONS DEVICE DATA

MC145190.MC145191

2-633

ELECTRICAL CHARACTERISTICS
(VDD = VCC = 4.5 to 5.5 V. Voltages Referenced to GND. TA = -40 to +85°C. unless otherwise stated;
MCI45190: VPD = 8.0 to 9.5 V; MC145191: VPD = 4.5 to 5.5 V with VDD S VPD.
Symbol

Parameter

Test Condition

Guaranteed
Limit

Unit

VIL

Maximum Low-Level Input Voltage
(Din. CLK. ENB. REFin)

Device In Reference Mode

0.3xVDD

V

VIH

Minimum High-Level Input Voltage
(Din. CLK. ENB. REFin)

Device In Reference Mode

0.7xVDD

V

Vhys

Minimum Hysteresis Voltage (CLK. ENB)

300

mV

VOL

Maximum Low-Level Output Voltage
(REFout. OUTPUT A)

lout = 20 flA. Device In Reference Mode

0.1

V

VOH

Minimum High-Level Output Voltage
(REFout. OUTPUT A)

lout = -20 !lA. Device In Reference Mode

VDD-O.l

V

IOL

Minimum Low-Level Output Current
(REFout. LD. oiJR. oiJV)

Vout = 0.4 V

0.36

mA

IOH

Minimum High-Level Output Current
(REFout. LD. oiJR. oiJV)

Vout = VDD - 0.4 V for REFout. LD
Vout = VpD - 0.4 V for oiJR. ojJy

-0.36

mA

IOL

Minimum Low-Level Output Current
(OUTPUT A. OUTPUT B)

Vout=0.4V

1.0

mA

IOH

Minimum High-Level Output Current
(OUTPUT A. Only)

Vout = VDD -

-0.6

mA

lin

Maximum Input Leakage Current
(Din. CLK. ENB. REFin)

Yin = VDD or GND. Device In XTAL Mode

±1.0

flA

lin

Maximum Input Current
(REFin)

Vln = VDD or GND. Device In Reference Mode

±150

!lA

IOZ

Maximum Output Leakage Current (PDoutl

Vout = VPD - 0.5 V or 0.5 V.
Output in High-Impedance State

±150
±200

nA

IOZ

Maximum Output Leakage Current
(OUTPUT B)

Vout = VPD or GND.
Output in High-Impedance State

±10

flA

Maximum Standby Supply Current
(VDD + VPD Pins)

Vln = VDD or GND; Outputs Open; Device in Standby Mode.
Shut-Down Crystal Mode or REFoutStatic-Low Reference
Mode; OUTPUT B Controlling VCC per Rgure 21

50·

flA

Maximum Phase Detector
Quiescent Current (VPD Pin)

Bit C6 = High Which Selects Phase Detector A.
POout = Open. PDout = Static Low or High. Bit C4 = Low
Which is not Standby. IRx = 113!lA

600·

!lA

Bit C6 = Low Which Selects Phase Detector B. oIlR and
ojJy = Open. oIlR and ojJy = Static low or High. Bit
C4 = low Which Is not Standby

30·

fin = 1.1 GHz; REFln = 13 MHz @ 1 Vp-p;
OUTPUT A = Inactive and No Connect;
REFout + 8; oiJV. oIlR. PDout. lD = No Connect;
Din. ENB. ClK = VDD or GND. Phase Detector B Selected
(BItC6=low)

"

ISTBY

IpD

IT

Total Operating Supply Current
(VDD + VPD + VCC Pins)

0.4 V

MC145190
MC145191

mA

'MC145191 only
·*The nominal value = 7 mAo This is not a guaranteed limit.

MC145190.MC145191
2-634

MOTOROLA COMMUNICATIONS DEVICE DATA

ANALOG CHARACTERISTICS-CURRENT SOURCE/SINK OUTPUT-PDout
(lout" 2 rnA, VDD = VCC = 4.5 to 5.5 V, VDD "VpD. Voltages Referenced to GND)
Test Condition

Parameter
Maximum Source Current Variation (Part-to-Part)

VPO

Guaranteed
Limit

Unit

B.O

±20

%

9.5

±20

4.5

±20

5.5

±20

B.O

12

9.5

12

MC145190: Vout = 0.5 x VPD

MC145191: Vout = 0.5 xVPD

Maximum Sink-vs-Source Mismatch (Note 3)

MC145190: Vout = 0.5 x VPO

MC145191: Vout = 0.5 x VPO

Output Voltage Range (Note 3)

MC145190: lout variation" 20%

MC145191: lout variation" 20%

4.5

12

5.5

12

B.O

0.5 to 7.5

9.5

0.5 to 9.0

4.5

0.5 to 4.0

5.5

0.5 to 5.0

%

%

%

V

V

NOTES:
1. Percentages calculated using the following formula: (Maximum Value - Minimum Value)/Maximum Value.
2. See Rx Pin Description for external resistor values.
3. This parameter is guaranteed for any specific temperature within -40 to +B5°C.
4. The analog characteristics for PDout are preliminary and subject to change for the MC145190.

AC INTERFACE CHARACTERISTICS (VOD = 4.5 to 5.5 V, TA = - 40 to +B5°C, CL = 50 pF, Input tr = tf = 10 ns;
MC145190: VPD = B.O to 9.5 V; MC145191: VpD = 4.5 to 5.5 V wilh VDD "VpD)
Symbol

Parameter
Serial Data Clock Frequency (Note: Refer to Clock tw below)

Figure #

Guaranteed
Limit

Unit

1

dc to 4.0

MHz

tpLH,
tpHL

Maximum Propagation Delay, CLK to OUTPUT A (Selected as Data Out)

1,5

105

ns

tpLH,
tpHL

Maximum Propagation Delay, ENB to OUTPUT A (Selected as Port)

2,5

100

ns

2,6

120

ns

. 1,5,6

100

ns

10

pF

Figure #

Guaranteed
Limit

Unit

fclk

tpZL, tpLZ

Maximum Propagation Delay, ENB to OUTPUT B

trLH, trHL

Maximum Output Transition Time, OUTPUT A and OUTPUT B;
trHLONLY, on OUTPUT B

Cin

Maximum Input Capacitance - Din, ENB, CLK

TIMING REQUIREMENTS
(VDD = VCC = 4.5 to 5.5 V, TA = -40 to +B5°C, Inputtr = tf= 10 ns unless otherwise indicated)
Symbol

Parameter

tsu, th

Minimum Setup and Hold Times, Din vs CLK

3

20

ns

tsu, th,
trec

Minimum Setup, Hold and Recovery Times, ENB vs CLK

4

100

tw

Minimum Pulse Width, ENB

4

.

ns

tw

Minimum Pulse Width, CLK

1

125

ns

Maximum Input Rise and Fall Times - CLK, ENB

1

100

I1 s

t r, tf

cycles

'The minimum limit is 3 REFin cycles or 195 fin cycles, whichever is greater.

MOTOROLA COMMUNICATIONS DEVICE DATA

MC145190.MC145191
2-635

SWITCHING WAVEFORMS

~--VDD

-VDD

ClK
GND
OUTPUT A

---t r:::=;'T-~LZ__tP-',z~,~

OUTPUT A
(DATA OUT)
OUTPUTB

310% '

Figure 2.

Figure 1.

Din

=f'~'~
SO%

-

tsu

CLK

f.

r

'~

th

E~B
SO%

:::

'=t
-

tw

~'r----

tsu
VDD

SO%

-

GND

-

VDD
GND
VDD

CLK

GND

Figure 3.

Figure 4.

V+
TEST POINT

TEST POINT
7.S kG

DEVICE
UNDER
TEST

'Includes all probe and fixture capacitance.

"Includes all probe and fixture capacitance.

Figure 5. Test Circuit

Figure 6. Test Circuit

MC145190.MC145191

2-636

DEVICE
UNDER
TEST

MOTOROLA COMMUNICATIONS DEVICE DATA

LOOP SPECIFICATIONS (VDD = VCC = 4.5 to 5.5 V unless otherwise indicated, TA = -40 to +B5°C)
Figure

Guaranteed
Operating Range

Test Condition

#

Min

Max

Unit

Vin

Input Voltage Range, lin

100 MHz S lin < 250 MHz
250 MHz S lin S 1100 MHz

7

400
200

1500
1500

mVp-p

Irel

Input Frequency, REFin Externally Driven In
Relerence Mode

Vin = 400 mVp-p
Vin = 1 Vp-p
R Counter set to divide ratio such that
'R S 2 MHz; REF Counter set to divide ratio sugh that REFout S 10 MHz

B

12
4.5'

27
27

MHz

Crystal Frequency, Crystal Mode

C1 S 30 pF, C2 S 30 pF, Includes
Stray Capacitance; R Counter and
REF Counter same as above

9

2

15

MHz

Output Frequency, REFout

CL=30pF

10,12

dc

10

MHz

dc

2

MHz

Symbol

txTAL

lout
I
tw
trLH,
trHL

Parameter

Operating Frequency 01 the Phase Detectors
Output Pulse Width, R, v, LD - MC145191

'R in Phase with tv, CL = 50 pF,
VPD = 5.5 V, VDD = VCC = 5.0 V

11,12

20

100

ns

Output Transition limes, LD, V,
R-MC145191

CL = 50 pF, VPD = 5.5 V,
VDD = VCC = 5.0 V

11,12

-

65

ns

-

5

pF

Input Capacitance, REFin
Cin
'II lower Irequency IS desired, use wave shaping or higher amplitude sinusoidal signal.

TEST
POINT

OUTPUT A

REFin
OUT
DEVICgUTA
UNDER
TEST

(fv)

DEVICE
UNDER
TEST

TEST
POINT
V+
"Characteristic Impedance

Figure 8. Test Circuit-Reference Mode

Figure 7. Test Circuit
r -.....-+-I REFin OUTPUT A
DEVICE
UNDER
TEST

TEST
POINT
(fR)

REFout

rC2

V+

Figure 10. Switching Waveform
Figure g_ Test Circuit-Crystal Mode
TEST POINT

OUTPUT

~O%
50"k

tw

------t~;t

DEVICE
UNDER
TEST

~1.::.0~:::.._ _ _ _ _ _....;

-

trHL

Figure 11. Switching Waveform

MOTOROLA COMMUNICATIONS DEVICE DATA

trLH

"Includes all probe and
fixture capacitance.

Figure 12. Test Circuit

MC145190.MC145191

2·637

PIN DESCRIPTIONS
DIGITAL INTERFACE PINS
Din
Serial Data Input (Pin 19)
The bit stream begins with the most significant bit (MSB)
and is shifted in on the low-to-high transition of ClK. The bit
pattern is 1 byte (8 bits) long to access the C or configuration
register, 2 bytes (16 bits) to access the first buffer of the R
register, or 3 bytes (24 bits) to access the A register (see Table
1). The values in the C, R, and A registers do not change during
shifting because the transfer of data to the registers is
controlled by ENB.
CAUTION
The value programmed for the N-counter must be
greater than or equal to the value of the A-counter.
The 13 least significant bits (lSBs) of the R register are
double-buffered. As indicated above, data is latched into the
first buffer on a 16-bit transfer. (The 3 MSBs are not
double-buffered and have an immediate effect after a 16-bit
transfer.) The second buffer of the R register contains the
13 bits forthe R counter. This second buffer is loaded with the
contents of the first bufferwhen the A register is loaded (a 24-bit
transfer). This allows presenting new values to the R, A, and
N counters simultaneously. If this is not required, then the
16-bittransfer may be followed by pulsing ENB low with no
signal on the ClK pin. This is an alternate method of
transferring data io the second buffer of the R register (see
Figure 16).
The bit stream needs neither address nor steering bits due
to the innovative BitGrabber registers. Therefore, all bits in the
stream are available to be data forthe three registers. Random
access of any register is provided. That is, the registers may
be accessed in any sequence. Data is retained in the registers
over a supply range of 4.5 to 5.5 V. The formats are shown
in Figures 13, 15, and 16.
Din typically switches near 50% of VDD to maximize noise
immunity. This input can be direclly interfaced to CMOS
devices with outputs guaranteed to switch near rail-to-rail.
When interfacing to NMOS orTTl devices, either a level shifter
(MC74HCI4A, MC14504B) or pull-up resistor of 1 kO to 10
kO must be used. Parameters to consider when sizing the
resistor are worst-case IOl of the driving device, maximum
tolerable power consumption, and maximum data rate.
Table 1. Register Access
(MSBs are shifted in first; CO, RO, and AO are the LSBs)
Number
of Clocks

Accessed
Register

Bit
Nomenclature

8
16
24
Other Values s 32
Values> 32

C Register
R Register
A Register
Not Allowed
See Figures
22-25

C7, C6, C5, ... , CO
R15, R14, R13, ... , RO
A23, A22, A21, ... , AO

ClK
Serial Data Clock Input (Pin 18)
low-to-high transitions on ClK shift bits available at the
Din pin, while high-to-low transitions shift bits from
OUTPUT A (when configured as Data Out, see Pin 16). The
24-1/2-stage shift register is static, allowing clock rates
down to dc in a continuous or intermittent mode.

MC145190.MC145191

2·638

Eight clock cycles are required to access the C register.
Sixteen clock cycles are needed for the first buffer of the R
register. Twenty-four cycles are used to access the A register.
See Table 1 and Figures 13, 15, and 16. The number of
clocks required for cascaded devices is shown in Figures 23
through 25.
ClK typically switches near 50% of VDD and has a
Schmitt-triggered input buffer. Slow ClK rise and fall times are
allowed. See the last paragraph of Din for more information.
CAUTION
To guarantee proper operation of the Power-On
Reset (POR) circuit, the ClKpin must begrounded
or held low during power up.
ENB
Active low Enable Input (Pin 17)
This pin is used to activate the serial interface to allow the
transfer of data tolfrom the device. When ENB is in an inactive
high state, shifting is inhibited and the port is held in the
initialized state. To transfer data to the device, ENB (which
must start inactive high) is taken low, a serial transfer is made
via Din and ClK, and ENB is taken back high. The low-to-high
transition on ENB transfers data to the C or A registers and
first buffer of the R register, depending on the data stream
length per Table 1.
Transitions on ENB must not be attempted while ClK is high.
This puts the device out of synchronization with the
microcontroller. Resynchronization occurs when ENB is high
and ClK is low.
This input is also Schmitt-triggered and switches near 50%
of VDD, thereby minimizing the chance of loading erroneous
data into the registers. See the last paragraph of Din for more
information.
CAUTION
ENB must not be floated ortoggled during power up.
It is preferable to hold ENB althe potential olthe VDD
pin during power up to guarantee proper operation of
the POR circuit.
OUTPUT A
Configurable Digital Output (Pin 16)
OUTPUT A is selectable as fR, fV, Data Out, or Port. Bits
A22 and A23 in the A register control the selection; see
Figure 15.
I! A23 = A22 = high, OUTPUT A is configured as fRo This
signal is the buffered output of the 13-stage R counter. The
fR signal appears as normally low and pulses high, and can
be used to verify the divide ratio olthe R counter. This ratio
extends from 5t08191 and is determinedbythe binary value
loaded into bits RO-RI2 in the R register. Also, direct
access to the phase detectors via the REFin pin is allowed
by choosing a divide value of 1 (see Figure 16). The
maximum frequency at which the phase detectors operate
is2 MHz. Therefore, thefrequencyoffR should not exceed
2 MHz.
If A23 = high and A22 = low, OUTPUT A is configured as
fV. This signal is the buffered output of the 12-stage N counter.
The fV signal appears as normally low and pulses high, and
can be used to verify the operation of the prescaler, A counter,
and N counter. The divide ratio between the fin input and the
fV signal is N x 64 + A. N is the divide ratio of the N counter
and A is the divide ratio of the A counter. These ratios are
determined by bits loaded into the A register. See Figure 15.
The maximum frequency atwhich the phase detectors operate

MOTOROLA COMMUNICATIONS DEVICE DATA

The maximum frequency at which the phase detectors operate
is 2 MHz. Therefore, the frequency of fV should not exceed
2 MHz.
If A23 low and A22 high, OUTPUT A Is configured as
Data Out. This signal is the serial output of the 24-1/2-stage
shift register. The bit stream is shifted out on the high-to-Iow
transition of the ClK input. Upon power up, OUTPUT A is
automatically configured as Data Out to facilitate cascading
devices.
If A23 A22 low, OUTPUT A is configured as Port. This
signal is a general-purpose digital output which may be used
as an MCU port expander. This signal is low when the Port
bit (C1) of the C register is low, and high when the Port bit
is high.

=

=

=

=

OUTPUTB
Open-Drain Digital Output (Pin 15)
This signal is a general-purpose digital output which may
be used as an MCU port expander. This signal is low when
the Out B bit (CO) of the C register is low. When the Out
B bit is high, OUTPUT B assumes the high-impedance
state. OUTPUT B may be pulled up through an external
resistor or active circuitry to any voltage less than or equal
to the potential of the VPD pin. Note: the maximum voltage
allowed on the VPDPin is9.5VfortheMC145190and5.5 V
for the MC145191.
Upon power-up, power-on reset circuitry forces OUTPUT
B to a low level.
REFERENCE PINS
REFin and REFout
Reference Input and Reference Output (Pins 20 and 1)
Configurable pins for a Crystal or an External Reference.
This pair of pins can be configured in one of two modes: the
crystal mode orthe reference mode. Bits R13, R14, and R15
in the R register control the modes as shown in Figure 16.
In crystal mode, these pins form a reference oscillator when
connected totermlnals of an external parallel-resonant crystal.
Frequency-setting capacitors of appropriate values as
recommended by the crystal supplier are connected from each
of the two pins to ground (up to a maximum of 30 pF each,
including stray capacitance). An extemal resistor of 1 MQ to
15 MQ is connected directly across the pins to ensure linear
operation of the amplifier. The device is designed to operate
with crystals up to 15 MHz; the required connections are
shown in Figure 9. To tum on the oscillator, bits R15, R14,
and R13 must have an octal value of one (001 in binary,
respectively). This is the active-crystal mode shown in
Figure 16. In this mode, the crystal oscillator runs and the R
Counter divides the crystal frequency, unless the part is in
standby. If the part Is placed in standby via the C register, the
oscillator runs, but the R counter is stopped. However, if bits
R15 to R13 have a value of 0, the oscillator is stopped, which
saves additional power. This is the shut-down crystal mode
(shown in Figure 16) and can be engaged whether in standby
or not.
In the reference mode, REFin (Pin 20) accepts a signal up
to 27 MHz from an external reference oscillator, such as a
TCXO. A signal swinging from at least the Vil to VIH levels
listed In the Electrical Characteristics table may be directly
coupled to the pin. If the signal is less than this level, ac
coupling must be used as shown in Figure 8. Due to an
on-board resistor which is engaged in the reference modes,
an external biasing resistor tied between REFin and REFout
is not required.

MOTOROLA COMMUNICATIONS DEVICE DATA

With the reference mode, the REFout pin is configured as
the output of a divider. As an example, if bits R15, R14, and
R13 have an octal value of seven, the frequency at REFout
Is the REFin frequency divided by 16. In addition, Figure 16
shows how to obtain ratios of eight, four, and two. A ratio of
one-to-one can be obtained with an octal value of three. Upon
power up, a ratio of eight is automatically initialized. The
maximum frequency capability of the REFout pin is 10 MHz.
Therefore, for REFln frequencies above 10 MHz, the
one-to-one ratio may not be used. Likewise, for REFin
frequencies above 20 MHz, the ratio must be more than two.
If REFout is unused, an octal value of two should be used
for R15, R14, and R13 and the REFout pin should be floated.
A value of two allows REFin to be functional while disabling
REFout, which minimizes dynamic power consumption and
electromagnetic interference (EM I).
LOOP PINS
fin and fin
Frequency Inputs (Pins 11 and 10)
These pins are frequency inputs from the VCO. These pins
feed the on-board RF amplifier which drives the 64/65
prescaler. These inputs may be fed differentially. However,
they usually are used in a single-ended configuration (shown
in Figure 7). Note that fin is driven while fin must be tied to
ground via a capacitor.
Motorola does not recommend driving fin while terminating
fin because this configuration is not tested for sensitivity. The
sensitivity is dependent on the frequency as shown in the loop
Specifications table.
PDout
Single-Ended Phase/Frequency Detector Output (Pin 6)
This is a three-state current-source/sink output for use as
a loop error signal when combined with an extemallow-pass
filter. The phaselfrequency detector is characterized by a
lineartransferiunction. The operation olthe phaselfrequency
detector is described below and is shown in Figure 17.
POL bit (C7) in the C register = low (see Figure 13)
Frequency of fV > fR or Phase of fV leading fR:
current-sinking pulses from high impedance
.
Frequency of fV < fR or Phase of fV Lagging fR:
current-sourcing pulses from high Impedance
Frequency and Phase of Iv = fR: essentially highimpedance state; voltage at pin determined by loop filter
POL bit (C7) high
Frequency of fV > fR or Phase of Iv Leading fR:
current-sourcing pulses from high impedance
Frequency of fV < fR or Phase of Iv Lagging fR:
current-sinking pulses from high impedance
fR: essentially highFrequency and Phase of fV
impedance state; voltage at pin determined by loop filter
This output can be enabled, disabled, and inverted via the
C register. If desired, PDout can be forced to the highimpedance state by utilization of the disable feature in the C
register (bit C6). This is a patented feature. Similarly, PDout
Is forced to the high-impedance state when the device is put
into standby (STBY bit C4 high).
The PDout circuit is powered by VPD. The phase detector gain is controllable by bits C3, C2, and C1: gain (in
amps per radian) PDout current divided by 27t.

=

=

=

=

MC145190.MC145191
2-639

eIIR and eIIv (Pins 3 and 4)
Double-Ended Phase/Frequency Detector Outputs
These outputs can be combined externally to generate
a loop error signal. Through use of a Motorola patented
technique, the detector's dead zone has been eliminated.
Therefore, the phase/frequency detector is characterized
by a linear transfer function. 'The operation of the
phaselfrequency detector is described below and is shown
in Figure 17.
POL bit (C7) in the C register = low (see Figure 13)
Frequencyoffy > fR or Phase ofiV Leading fR: eIIV= negative
pulses, eIIR = essentially high
Frequency of fV < fR or Phase of fV Lagging fR: eIIv =
essentially high, eIIR = negative pulses
Frequency and Phase of fV = fR: eIIv and eIIR remain
essentially high, except for a small minimum time period
when both pulse low in phase
POL bit (C7) = high
Frequencyoflv > fR or Phase ofiV Leading fR: eIIR = negative
pulses, eIIv = essentially high
Frequency of fV < fR or Phase of fV Lagging fR: eIIR =
essentially high, eIIv = negative pulses
Frequency and Phase of fV = fR: eIIv and eIIR remain
essentially high, except for a small minimum time period
when both pulse low in phase
These outputs can be enabled, disabled, and interchanged
via C register bits C6 or C4. This is a patented feature. Note
that when disabled or in standby, eIIR and eIIv are forced to their
rest condition (high state).
The eIIR and eIIv output signal swing is approximately from
GND to VpD.
LD
Lock Detector Output (Pin 2)
This output is essentially at a high level with narrow
low-going pulses when the loop is locked (fR and fV of the
same phase and frequency). The output pulses low when
fV and fR are out of phase ordifferentfrequencies. LD is the
logical ANDing of eIIR and eIIV (see Figure 17).
This output can be enabled and disabled via the C register.
This is a patented feature. Upon power up, on-chip initialization
circuitry disables LD to a static low logic level to prevent a false
"lock" signal. If unused, LD should be disabled and left open.
The LD output signal swing is approximately from GND to
VDD·
.
Rx
External Resistor (Pin 8)
A resistortied between this pin and GND, in conjunction with
bits in the C register, determines the amount of current that
the PDout pin sinks and sources. When bits C2 and C3 are
both set high, the maximum current is obtained at PDout; see
Tables 2 and 3 for other values of current. To achieve a
maximum current of 2 mA, the resistor should be about 47 kn
when VPD is 9 V or about 18kn when VPD is 5.0 V. See Figure
14 if lower maximum current values are desired.
When the eIIR and eIIv outputs are used, the Rx pin may be
floated.

TEST POINT PINS
TEST 1
Modulus Control Signal (Pin 9)
This pin may be used in conjunction with the Test 2 pin for
access to the on-board 64/65 prescaler. When Test 1 is low,
the prescaler divides by 65. When high, the prescaler divides
by 64.
CAUTION
This pin is an unbuffered output and mustbe floated
in an actual application. This pin must be attached to
an isolated pad with no trace. There is the possibility
that the final production version of the device will
have this lead clipped at the body of the package.
TEST 2
Prescaler Output (Pin 13)
This pin may be used to access to the on-board 64/65
prescaler output.
.
CAUTION
This pin is an unbuffered output and must be floated
in an actual application. This pin must be attached to
an isolated pad with no trace. There is the possibility
that the final production version of the device will
have this lead clipped at the body of the package.
POWER SUPPLY PINS
VDD
Positive Power Supply (Pin 14)
This pin supplies powertothe main CMOS digital portion
of the device. The voltage range is + 4.5 to + 5.5 V with
respect to the GND pin.
For optimum performance, VDD should be bypassed to
GND using a low-inductance capacitor mounted very close
to these pins. Lead lengths on the capacitor should be
minimized.
VCC
Positive Power Supply (Pin 12)
This pin supplies power to the RF amp and 64/65
prescaler. The voltage range is +4.5 to +5.5 V with respect
totheGNDpin.lnthestandbymode, the VCC pin still draws
a few milliamps from the power supply. This current drain
can be eliminated with the use of transistor Q1 as shown
in Figure 21.
For optimum performance, VCC should be bypassed to
G NO using a low-inductance capacitor mounted very close
to these pins. Lead lengths on the capacitor should be
minimized.
VPD
Positive Power Supply (Pin 5)
This pin supplies power to both phaselfrequency detectors
A and B. The voltage applied on this pin must be no less than
the potential applied to the VDD pin. The maximum voltage
can be +9.5 V with respect to the GND pin for the MC145190
and +5.5 V for the MC145191.
Foroptimumperiormance, VPDshouldbebypassedtoGND
using a low-inductance capacitor mounted very close to these
pins. Lead lengths on the capacitor should be minimized.
GND
Ground (Pin 7)
Common ground.

MC145190.MC145191
2-640

MOTOROLA COMMUNICATIONS DEVICE DATA

can be +9.5 V with respect to the GND pin for the MC145190
and +5.5 V for the MC145191.
For optimum performance, VPD should be bypassed to
GND using a low-inductance capacitor mounted very close
to these pins. Lead lengths on the capacitor should be

minimized.
GND

Ground (Pin 7)
Common ground.

ENB~~_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~r+
*

elK

MSB

lSB

• At this point, the new byte is transferred to the C register and stored. No other registers are affected.

C7 -

C6 -

POL:

Selects the output polarity of the phase/frequency detectors. When set high, this bit inverls
PDout and interchanges the ~R function with W as depicted in Figure 17. Also see the phase
detector output pin descriptions for more information. This bit is cleared low at power up.

PDAlB:

Selects which phase/frequency detector is to be used. When set high, enables the output of
phaselfrequency detector A (PDout) and disables phase/frequency detector B by forcing ~R
and ~V to the static high state. When cleared low, phase/frequency detector B is enabled (~R
and ~V) and phaselfrequency detector A is disabled with PDout forced to the high·impedance
state. This bit is cleared low at power up.

CS C4 -

LDE:

Enables the lock detector output (LD) when set high. When the bit is cleared low, the LD output
is forced to a static low level. This bit is cleared low at power up.

STBY:

When set, places the CMOS section of device, which is powered by the VDD and VPD pins,
in the standby mode for reduced power consumption: PDout is forced to the high·impedance
state, ~R and ~V are forced high, the A, N, and R counters are inhibited from counting, and
the Rx current is shut off. In standby, the state of LD is determined by bit CS. CS low forces
LD low (no change). CS high forces LD static high. During standby, data is retained In the A,
R, and C registers. The condition of REF/OSC circuitry Is determined by the control bits in
the R register: R13, R14, and R1S. However, if REFout = static low i~ selected, the internal
feedback resistor is disconnected and the Input is inhibited when in standby; in addition, the
REFln input only presents a capacitive load. NOTE: Standby does not "affect the other modes
of the REF/OSC circuitry.

When C4 is reset low, the pari is taken out of standby in 2 steps. First, the REFin (only in one mode) resistor
is reconnected, all counters are enabled, and the Rx current is enabled. Any fR and tv signals
are inhibited from toggling the phaselfrequency detectors and lock detector. Second, when the
first tv pulse occurs, the R counter is jam loaded, and the phaselfrequency and lock detectors
are initialized. Immediately after the jam load, the A, N, and R counters begin counting down
together. At this pOint, the fR and tv pulses are enabled to the phase and lock detectors. (Pat·
ented feature.)
C3, C2 -12, 11:

Controls the PDout source/sink current per Tables 2 and 3. With both bits high, the maximum
current (as set by Rx per Figure 14) is available. Also, see Cl bit description.

Cl -

Pori:

When the OUTPUT A pin is selected as ·Porl" via bits A22 and A23, Cl determines the state
of OUTPUT A. When Cl is set high, OUTPUT A is forced high; Cl low forces OUTPUT A
low. When OUTPUT A Is NOT selected as ·Port," Cl controls whether the PDout step size
is 10% or 2S%. (See Tables 2 and 3.) When low, steps are 10%. When high, steps are 2S%.
Default is 10% steps when OUTPUT A is selected as ·Port." The Pori bit is not affected by
the standby mode.

Out B:

Determines the state of OUTPUT B. When CO is set high, OUTPUT B is high-impedance; CO
low forces OUTPUT B low. The Out B bit Is not affected by the standby mode. This bit Is cleared
low at power up.

CO -

Figure 13. C Register Access and Format (8 Clock Cycles are Used)

MOTOROLA COMMUNICATIONS DEVICE DATA

MC145190.MC145191
2-641

100

\1\\
~,
\

90

80

f3
a:

SO

::;!
z
a:
w

~
li.

I

II

II

I

I

,

i!S.

~

I

PDout CURRENT SET TO 100%;
PDout VOLTAGE IS FORCED TO ONE·HALF OF VpD.

\ \'i\
\ 1\." \
'\
~ i\

C

60

I

\\ \

70

a:

I

40

"""'-

"

.......

.......

30

20

- --- -

I........

r--....
........ ........ ........
........
~ I"......
~

" r:::

10
,

o

MC145191

r- r-.

r-

'-

r- t -

VPD=S.SV VPD=S.OV
Vpr4Y -

I

0.1

0.2

0.3

0.4

O.S

0.6

0.7 0.8

0.9

1.0

1.1

1.2

1.3

1.4

1.S

1.6

1.7

1.8

1.9 2.0

2.1

I
2.2

2.3

lout, SOURCE CURRENT (rnA)
NOTE: The MC145191 is optimized for Rx values in the 18 kn to 40 kQ range. For example, to achieve 0.3 rnA of output
current, it is preferable to use a 30·kn resistor for Rx and bit settings for 25% (as shown In Table 3).

Figure 14. Nominal Source Current for the PDout Pin

Table 2. PDout Current, C1 = Low with OUTPUT A NOT
Selected as "Port"; Also, Default Mode When
OUTPUT A Selected as "Port"

=

Table 3. PDout Current, C1 High with OUTPUT A NOT
Selected as "Port"

C3

C2

PDout Current

C3

C2

PDout Current

0
0
1
1

0
1
0
1

70%
80%
90%
100%

0
0
1
1

0
1
0
1

25%
50%
75%
100%

MC145190.MC145191
2-642

MOTOROLA COMMUNICATIONS DEVICE DATA

s::

~

I

:II

o

>

ENBI

t

8
s::
s::
c

NOTE 3

z

(5

~

CLK

o
z

!!
ca

m

:u
CD
ca
~
CD

en
o
m
<
(5

o

~
~

c

...!JIiil
l>

Din

.

l>

R
CD
UI
UI

DI

:J

'-----.---'

'l1

BOTH BITS
MUST BE
HIGH

Do

3

!!l.

~

""n
g
~

~

if

DI

0
0
I

I

0

'-.--J

PORT
DOUT

Iv
IR

o
o
o

0
0
0
0
0

0

o
o

0
I
2

3
4
5
7

BINARY OUTPUT A
VALUE FUNCTION
(NOTE I)

F

F

ENCOUNTER = +4094

F

F

F

'----v--------'

UI

HEXADECIMAL VALUE
FOR N COUNTER

CD

.s

0
0
0

4
4

'-.--J

iil

c:

NOT ALLOWED
NOT ALLOWED
NOT ALLOWED
NOT ALLOWED
NOT ALLOWED
N COUNTER = +5
N COUNTER =+6
NCOUNTER =+7

2

E
F
0
I

ACOUNTER
ACOUNTER
ACOUNTER
ACOUNTER

=+0
=+ I
=+2
=+3

ACOUNTER = + 62
ACOUNTER = + 63
NOT ALLOWED
NOT ALLOWED

N COUNTER = +4095
F
F NOT ALLOWED
'----.----J
HEXADECIMAL VALUE
FOR ACOUNTER

s:

(")
....
t;
....
8
i::
(")
....

1\)"'"
,Ut

~iD
w
....

NOTES:
1. A power-on initialize circuit forces the OUTPUT A function to default to Data Out.
.
2. The values programmed for the N counter must be greater than or equal to the values programmed for the A counter. This results in a total divide value = N x 64 + A.
3. At this point, the three new bytes are transferred to the A register. In addition, the 13 LSBs in the first buffer of the R register are transferred to the R register's second buffer.
Thus, the R, N, and A counters can be presentetl new divide ratios at the same time. The first buffer of the R register is not affected. The C register is not affected.

l~,

ENB

________________________________~nLr
t

t

4

5

NOTE NOTE
ClK

3
4
5
6
7

L

CRYSTAL MODE, SHUT DOWN
CRYSTAL MODE, ACTIVE
REFERENCE MODE, REFin ENABLED and REFout
STATIC lOW
REFERENCE MODE, REFout = REFln (BUFFERED)
REFERENCE MODE, REFout = REFIn12
REFERENCE MODE, REFout = REFinl4
REFERENCE MODE, REFout = REFjn18 (NOTE 3)
REFERENCE MODE, REFout = REFinll6

o
o

o
o
o
o
o
o
o

0

o

0
0
0

o

o
o

0
0

o
o

0
0

o
o

0

o

0
I
2
3
4
5
6
7
8

NOT ALLOWED
DIRECT ACCESS TO REFERENCE SIDE OF PHASEIFREQUENCY DETECTORS
NOT ALLOWED
NOT ALLOWED
NOT ALLOWED
RCOUNTER=+5
RCOUNTER=+6
RCOUNTER=+7
RCOUNTER=+8

OCTAL VALUE
IFF
IF
F

BINARY VALUE

E RCOUNTER=+8190
F R COUNTER = +8191

--.t H~ VALUE

NOTES:
I. Bits RI5 through RI3 control the configurable "OSO or 4-slage divider" block (see Block Diagram).
2. Bits RI2 through RO controllhe "13-slage R counter" block (see Block Diagram).
3. A power-on initialize circuit forces a default REFin to REFout ratio of eight.
4. Atthlspoint,bitsRI3,RI4,andRI5arestoredandsenttothe"OSOor4-Slage Divider"blockinthe BlockDlagram.
Bits RO through R12 are loaded Into the first buffer In the double-buffered section of the R register. Therefore, the
R counter divide ratio Is not altered yet and relalns the previous ratio loaded. The Oand A registers are notaff9CIed.
5. At this point, bits RO through RI2 are transferred to the second buffer of the R register. The R counter begins
dividing by the new ratio after completing the restofthe present count cycle. OlK must below during the ENB pulse,
as shown. Also, see note 3 of Figure 15 for an alternate method of loading the second buffer In the R register. The
o and A registers are not affected. The first buffer of the R register Is not affected.

Figure 16_ R Register Access and Format (16 Clock Cycles Are Used)

MC145190.MC145191
2-644

MOTOROLA COMMUNICATIONS DEVICE DATA

REFERENci~

REFin+ R

FEEDBACl
fin+(Nx64+A)

PDout

~R

n~------~n~------~n~--------~~~~
,

n :: W.---------t----iI
u
U
--'-i---""""';';I-----.U
,

LD

-

VL

SOURCING CURRENT

,'-------In'------;,

HIGH IMPEDANCE

j------;

SINKING CURRENT
VH

, ,
,

,

~V

*

"

"

-VL

I,

U

VH

-VL
' u ,'

- - - - - + - - VH

U'
j--:

-VL

VH = High voltage level
VL = Low voltage level
•At this point, when both fR and tv are in phase, the output source and sink circuits are turned on for a short interval.
NOTE: The PDouteilher sources or sinks current during out-of-Iockcondltions. When locked in phase and frequency, the
output is high impedance and the voltage althat pin is determined by the low-pass filler capacitor. PDout, ~R, and
v are shown with the polarity bit (POL) = low; see Figure 13 for POL.
Figure 17_ Phase/Frequency Detectors and Lock Detector Output Waveforms

DESIGN CONSIDERATIONS
CRYSTAL OSCILLATOR CONSIDERATIONS
The following options may be considered to provide a
reference frequency to Motorola's CMOS frequency synthesizers.
Use of a Hybrid Crystal Oscillator
Commercially available temperature-compensated crystal
oscillators (TCXOs) or crystal-controlled data clock oscillators
provide very stable reference frequencies. An oscillator
capable of CMOS logic levels at the output may be direct or
dc coupled to REFin. If the oscillator does not have CMOS
logic levels on the outputs, capacitive or ac coupling to REFin
may be used (see Figure 8).
For additional infonmation about TCXOs and data clock
oscillators, please consult the latest version of the eem
Electronic Engineers Master Catalog, the Gold Book, or
similar publications.
Design an Off-Chip Reference
The user may design an off-chip crystal oscillator using
discrete transistors or ICs specifically developed for crystal
oscillator applications, such as the MC12061 MECL device.
The reference signal from the MECL device is ac coupled to
REFin (see Figure 8). For large amplitude signals (standard
CMOS logic levels), dc coupling may be used.
Use of the On-Chip Oscillator Circuitry
The on-chip amplifier (a digital inverter) along with an
appropriate crystal may be used to provide a reference source
frequency. A fundamental mode crystal, parallel resonant at
the desired operating frequency, should be connected as
shown in Figure 18.

MOTOROLA COMMUNICATIONS DEVICE DATA

The crystal should be specified for a loading capacitance
(CLl which does not exceed approximately 20 pF when used
at the highest operating frequency of 15 MHz. Assuming
Rl = 0 n, the shunt load capacitance (CLl presented across
the crystal can be estimated to be:
CinCout
Cl • C2
CL = - - - + Ca + Cstray + - - Cin+Cout
Cl + C2
where
Cin =5 pF (see Figure 19)
Cout ;" 6 pF (see Figure 19)
C a = 1 pF (see Figure 19)
Cl and C2 =extemal capacitors (see Figure 18)
Cstray =the total equivalent external circuit stray capacitance appearing across the crystal terminals
The oscillator can be '1rimmed" on-frequency by making a
portion or all of Cl variable. The crystal and associated
components must be located as close as possible to the REFin
and REFout pins to minimize distortion, stray capacitance,
stray inductance, and startup stabilization time. Circuit stray
capacitance can also be handled by adding the appropriate
stray value to the values for Cin and Cout. For this approach,
the tenm Cstray becomes 0 in the above expression for CL.
Power is dissipated in the effective series resistance of the
crystal, Re , in Figure 20. The maximum drive level specified
by the crystal manufacturer represents the maximum stress
that the crystal can withstand without damage or excessive
shift in operating frequency. Rl In Figure 18 limits the drive
level. The use of Rl is not necessary in most cases.

MC145190.MC145191
2-645

To verify that the maximum dc supply voltage does not
cause the crystal to be overdriven, monitor the output
frequency (fR) at OUTPUT A as a function of supply voltage.
(REFout is not used because loading impacts the oscillator.)
The frequency should increase very slightly as the dc supply
voltage is increased. An overdriven crystal decreases in
frequency or becomes unstable with an increase in supply
voltage. The operating supply voltage must be reduced or R1
must be increased in value if the overdriven condition exists.
The user should note that the oscillator start-up time is
proportional to the value of R1.
Through the process of supplying crystals for use with
CMOS inverters, many crystal manufacturers have developed expertise in CMOS oscillator design with crystals.
Discussions with such manufacturers can prove very helpful
(see Table 4).
RECOMMENDED READING
Technical Note TN-24, Statek Corp.
Technical Note TN-7, Statek Corp.
E. Hafner, "The Piezoelectric Crystal Unit-Definitions and
Method of Measurement", Proc. IEEE, Vol. 57, No.2, Feb.
1969.
D. Kemper, L. Rosine, "Quartz Crystals for Frequency
Control", Electro-Technology, June 1969.
P. J. Ottowitz, "A Guide to Crystal Selection", Electronic
DeSign, May 1966.
D. Babin, "Designing Crystal Oscillators", Machine Design,
March 7,1985.
D. Babin, "Guidelines for Crystal Oscillator Design",
Machine Design, April 25, 1985.

I" - - - - I

L_

FREQUENCi"l
SYNTHESIZER

I

___
REFin

_~
REFout

Rf

"May be needed in certain cases. See text.

Figure 18. Pierce Crystal Oscillator Circuit

~

REFin o>----"I--Tj--V--rj---""-I-o REFout

-'- C·

I

In

.;

IL __ II __ .JIcout I-'II
..L
Cstray

Figure 19. Parasitic Capacitances of the Amplifier
and Cstray

1

0

o----l j--o2
Co

Note: Values are supplied by crystal manufacturer
(parallel resonant crystal).

Figure 20. Equivalent Crystal Networks

Table 4. Partial List of Crystal Manufacturers
Name

Address

Phone

United States Crystal Corp.
Crystek Crystal
Statek Corp.
Fox Electronics

3605 McCart Ave., Ft. Worth, TX 76110
2371 Crystal Dr., Ft. Myers, FL 33907
512 N. Main St., Orange. CA 92668
5570 Enterprise Parkway, Ft. Myers, FL 33905

(817) 921·3013
(813) 936-2109
(714) 639-7810
(813) 693-0099

Note: Motorola cannot recommend one supplier over another and in no way suggests that this is a
complete listing of crystal manufacturers.

MC145190.MC145191

2-646

MOTOROLA COMMUNICATIONS DEVICE DATA

PHASE-LOCKED LOOP-LOW PASS FILTER DESIGN

-V
_ B. VKq.Kvco C

(A)

KIj>KVCO
NC

ron-

I; - 2

N

mn RC
2

Z(s) = 1 +S~RC
NOTE:
For (A), using KIj> in amps per radian with the filter's impedance transfer function, Z(s), maintains units of volts per radian for the
detectorlfiltercombinatlon. Additional sideband filtering can be accomplished by adding a capacitor C' across R. The corner (oc = l/RC'
should be chosen such that (On is not significantly affected.

(B)

ron =

Rl

$R --"""''v---<~
$V --"""''v----<.....-l

vco

V

K!I!KVCO
NCR1

ronR2C

I; = - - 2 ASSUMING GAIN A IS VERY LARGE, THEN:

NOTE:
For (B), Rl is frequently split into two series resistors; each resistor is equal to Rl divided by 2. A capacitor Cc is then placed from
the mldpointto ground to further filter the error pulses. The value of Cc should be such thatthe corner frequency ofthis network does
not significantly affect (On.
DEFINITIONS:
N = Total Division Ratio in Feedback Loop
K$ (Phase Detector Gain) = IPDout/2lt amps per radian for PDout
K$ (Phase Detector Gain) = VpD/2lt volts per radian for $V and $R
KVCO (VCO Transfer Function) =

2ltL\tvCO
fj, VVCO
radians per volt

For a nominal deSign starting pOint, the user might consider a damping factor 1;=0.7 and a natural loop frequency (On = (2ltfR/50)
where fR is the frequency at the phase detector input. Larger (On values result in faster loop lock times and, for similar sideband
filtering, higher fR-related VCO sidebands.
Either loop filter (A) or (B) is frequently followed by additional sideband filtering to further attenuate fwrelated VCO sidebands.
This additional filtering may be active or passive.
RECOMMENDED READING:
Gardner, Floyd M., Phaselock Techniques (second edition). New York, Wiley-Interscience, 1979.
Manassewitsch, Vadim, Frequency Synthesizers: Theory and Design (second edition). New York, Wiley-Interscience, 1980.
Blanchard, Alain, Phase-Locked Loops: Application to Coherent Receiver Design. New York, Wiley-Interscience, 1976.
Egan, William F., Frequency SyntheSiS by Phase Lock. New York, Wiley-Interscience, 1981.
Rohde, Ulrich L., Digital PLL Frequency Synthesizers Theory and Design. Englewood Cliffs, NJ, Prentice-Hall, 1983.
Berlin, Howard M., Design of Phase-Locked Loop Circuits, with Experiments. Indianapolis, Howard W. Sams and Co., 1978.
Kinley, Harold, The PLL Synthesizer Cookbook. Blue Ridge Summit, PA, Tab Books, 1980.
Seidman, Arthur H., Integrated Circuits Applications Handbook, Chapter 17, pp. 538-586. New York, John Wiley & Sons.
Fadrhons, Jan, "Design and Analyze PLLs on a Programmable Calculator," EDN. March 5, 1980.
AN535, Phase-Locked Loop Design Fundamentals, Motorola Semiconductor Products, Inc., 1970.
AR254, Phase-Locked Loop Design Articles, Motorola Semiconductor Products, Inc., Reprinted with permission from
Electronic Design, 1987.

MOTOROLA COMMUNICATIONS DEVICE DATA

MC145190.MC145191
2-647

D

r

REFoul

OPTIONAL lOOP {
ERROR SIGNALS
(NOTE 1)

REFin

2 lD

Din

eIlR

ClK

4 eIlv

ENB

+V
7

VPD

OUTPUT A

PDout

OUTPUTB

GND

VDD

Rx
NC

r-l
"::' 1000 pF

9
10

TEST 2

TEST 1

VCC

ij;;

fin

r

20

+5V

•

19
MCU

18
17
GENERAL-PURPOSE
DIGITAL OUTPUT

16
15

"::'

14
13

NC

12
11

>--- UHF OUTPUT
BUFFER
NOTES:
1. When used, the eIlR and eIlv outputs are fed to an extemal comblner/loop filter. See the Phase-Locked
Loop - Low-Pass Filter Design page for additional information.
2. TransistorOl is required onlyifthe standby feature is needed. 01 permits the bipolar section of the device
to be shutdown via use of the general-purpose digital pin, OUTPUT B.lfthe standby feature Is not needed,
tie pin 12 directly to the power supply.
3. For optimum performance, bypass the Vee, VDD, and VPD pins to GND with low-inductance capacitors.
4. The R counter Is programmed for a divide value = REFinflR. Typically, fR is the tuning resolution required
for the veo. Also, the veo frequency divided by fR = NT = N x 64 + A; this determines the values (N, A)
that must be programmed Into the N and A counters, respectively.

Figure 21. Example Application

DEVICE #1
Din

ClK

ENB

DEVICE #2
OUTPUT A
(DATAOUn

Din

I

t

ClK

ENB

OUTPUT A
(DATA OUT)

CMOS
MCU
OPTIONAL

Figure 22_ Cascading Two Devices

MC145190.MC145191
2-648

MOTOROLA COMMUNICATIONS DEVICE DATA

s::

~

i3 1
s;:

ENii

I

l

+

()

0

~I

c
z
0

:!:i

61
Z

ClK

Din

en

~JLflflJ\MLJU\JU1MJUUU\JUL'
~ a ~:: n a ~ ~:~ ~ co ~ a H~: ~ ~ a ~:~ 8 a H ~ 8co ~
X

X

X

C7

C6

X

X

X

X

X

\.
v )

0

m
<
0
m

X

C7

C6

"

C REGISTER BITS OF DEVICE #2
IN FIGURE 22

::

J

v

C REGISTER BITS OF DEVICE #1
IN FIGURE 22

0

»~

• At this point, the new bytes are transferred to the C registers of both devices and stored. No other registers are affected.

Figure 23. Accessing the C Registers of Two Cascaded Devices

r

ENiil

•

CLK

Din

~JlflJ\MLJ\ML-fLNL1\JiFLs-fLMML
~ H ~:: a H H:: H B a:: n a H:~ H ~ B:~~ ~ 8 a:: a ~
X

X

A23

'-

:s::
(')

...

...ti

co

Ii'

:s::
(')

...

",,,,,
lUI
en
...
""CO
CO'"

A22

A16

A15

AS

~

A7

AO

A23

/'-.....

A REGISTER BITS OF DEVICE #2
IN FIGURE 22

A9

AS

-.....y-

AO

~

A REGISTER BITS OF DEVICE #1
IN FIGURE 22

·At this point, the new bytes are transferred to the A registers of both devices and stored. Additionally, for both devices, the 13 LSBs in each olthe first buffers olthe R registers are
transferred to the respective R register's second buffer. Thus, the R, N, and A counters can be presented new divide ratios at the same time. The first buffer of each R register is not affected.
Neither C register is affected.

Figure 24. Accessing the A Registers of Two Cascaded Devices

N5:
mo
til ...
0

...
....
til

8

~

o...

......ti
CD

WBl

~

t

t

Note 1 Note 2

CLK

Din

~JlfLfLJ1-MJifLfLs-fLfLfL~J1fL~ x8 ~:~ ~ ~ ~:~ a H ~ ~~ H ~ ~:~ B ~ H:~ H ~ ~ :~ 8 ~
X

R15

'-...

R14

RB

R7

'V
R REGISTER BITS OF DEVICE 112
IN FIGURE 22

s:

@
e5

S;

RO

./

X

X

R15

RB

~

z

o
z

rn

o
<
C'i
m
o
m

»~

~

NOTES APPLICABLE TO EACH DEVICE:
1. Atthis point, bits R13, R14, and R15 are stored and sent to the "OSC or4-Stage Divider" block in the Block Diagram. Bits RO through R12 are loaded into the first buffer in the doublebuffered section of the R register. Therefore, the R counter divide ratio is not altered yet and retains the previous ratio loaded. The C and A registers are not affected.
2. At this point, the bits RO through R12 are transferred to the second buffer of the R register. The R counter begins dividing by the new ratio after completing the rest of the present count
cycle. ClK must be low during the ENB pulse, as shown. Also, see note of Figure 24 for an alternate method of loading the second buffer in the R register. The C and A registers
are not affected. The first buffer of the R register is not affected.

(")

~

RO

R REGISTER BITS OF DEVICE #1
IN FIGURE 22

o
s:
s:
c
C'i

R7

Figure 25. Accessing the R Registers of Two Cascaded Devices

_

MOTOROLA

SEMICONDUCTOR
TECHNICAL DATA

MC145192
Advance Information
Low·Voltage 1.1 GHz
PLL Frequency Synthesizer
Includes On-Board 64/65 Prescaler
The MC145192 is a low-voltage single-package synthesizer with serial interface
capable of direct usage up to 1.1 GHz. A special architecture makes this PLL very
easy to program because a byte-oriented format is utilized. Due to the patented
BitGrabber™ registers, no address/steering bits are required for random access
of the three registers. Tuning can be accomplished via a 3-byte serial transfer to
the 24-bit A register. The interface is both SPI and MICROWIRETM compatible.
The device features a single-ended current source/sink phase detector A output
and a double-ended phase detector B output. Both phase detectors have linear
transfer functions (no dead zones). The maximum current of the single-ended
phase detector output is determined by an external resistor tied from the Rx pin
to ground. This current can be varied via the serial port.
The MC145192 phase/frequency detector B C\>R and C\>v outputs can be powered
from 2.7 to 5.5 V. This is optimized for 3-V systems. The phase/frequency detector
A PDoutoutput must be powered from 4.5 to 5.5 V, and is optimized for a 5-V supply.
This part includes a differential RF input which may be operated in a
single-ended mode. Also featured are on-board support of an external crystal and
a programmable reference output. The R, A, and N counters are fully programmable. The C register (configuration register) allows the part to be configured to
meet various applications. A patented feature allows the C register to shut off
unused outputs, thereby minimizing system noise and interference.
In order to have consistent lock times and prevent erroneous data from being
loaded into the counters, on-board circuitry synchronizes the update of the A
register if the A or N counters are loading. Similarly, an update of the R register is
synchronized if the R counter is loading.
The double-buffered R register allows new divide ratios to be presented to the
three counters (R, A, and N) simultaneously.
• Maximum Operating Frequency: 1100 MHz @ Vin =200 mVp-p
• Operating Supply Current: 6 mA Nominal at 2.7 V
• Operating Supply Voltage Range (VDD and VCC Pins): 2.7 to 5.0 V
• Operating Supply Voltage Range of Phase Freq. Detector A (VPD Pin): 4.5 to 5.5 V
• Operating Supply Voltage Range of Phase Detector B (VPD Pin): 2.7 to 5.5 V
• Current Source/Sink Phase Detector Output Capability: 2 mA Maximum
• Gain of Current Source/Sink Phase/Frequency Detector Controllable via Serial Port
• Operating Temperature Range: -40 to + 85°C
• R Counter Division Range: 5 to 8191 Plus Direct Access to Phase Detector Input
• Dual-Modulus Capability Provides Total Division up to 262,143
• High-Speed Serial Interface: 2 Mbps
• OUTPUT A Pin, When Configured as Data Out, Permits Cascading of Devices
• Two General-Purpose Digital Outputs - OUTPUT A: Totem-Pole (Push-Pull)
with Four Output Modes
OUTPUT B: Open-Drain
• Patented Power-Saving Standby Feature with Orderly Recovery for Minimizing
Lock Times, Standby Current: 50 !iA

4'

ORDERING INFORMATION
MC145192F

SOG Package

PIN ASSIGNMENT
REFout

1.

20

REFin

LD

19

Din

R

18

eLK

Y

17

ENB

YPD

16

OUTPUT A

PDou!

15

OUTPUTB

GND

14

VDD

Rx

13

TEST 2

12

Vee

11

fin

TEST 1

iiii

10

This document contains information on a new product. Specifications and information herein are subject to change without notice.
BitGrabber is a trademark of Motorola Inc. MICROWIRE is a trademark of National Semiconductor Corp.

MOTOROLA COMMUNICATIONS DEVICE DATA

FSUFFIX
SOG
CASE 751J

REV. 1

MC145192
2-651

BLOCK DIAGRAM
Data Out
20

REFin

OSCOR
4·STAGE
DIVIDER
(CONFIGURABlE)

fR

13·STAGE RCOUNTER

PORT
fy

SELECT
LOGIC

16 OUTPUT A

REFout

lD

ClK

SHIFT
REGISTER
AND
CONTROL
lOGIC

19

Din

Rx
PDout

24

~R
~V

ENB

>----....:..::. OUTPUT B

(OPEN·DRAIN
OUTPUT)

fin _ _1;. :.1_ _-1

t;;;

r -_ _ _ _......;.;13. TEST 2

0_ _-I
_---'Ic:.

SUPPLY CONNECTIONS:
PIN 12 = VCC (V+ TO INPUT AMP AND 64/65 PRESCAlER)
' - - - - - - - - _ - - - - - - - - - - - - - - _ TEST 1
PIN 5 = VpD (V+ TO PHASE/FREQUENCY DETECTORS A AND B)
PIN 14 = VDD (V+ TO BALANCE OF CIRCUIT)
PIN 7 = GND (COMMON GROUND)

MAXIMUM RATINGS' (Voltages Referenced to GND, unless otherwise stated)
Symbol
VCC, VDD

Parameter
DC Supply Voltage (Pins 12 and 14)

Value

Unit

-0.5 to +6.0

V

VPD

DC Supply Voltage (Pin 5)

VDD -0.5 to + 6.0

V

Vin

DC Input Voltage

-0.5 to VDD + 0.5

V

Vout

DC Output Voltage (except OUTPUT B, PDout, ~R,

-0.5 to VDD +0.5

V

Vout

DC Output Voltage (OUTPUT B, PDout, ~R, ~V)

~)

-0.5 to VPD + 0.5

V

DC Input Current, per Pin (Includes VpD)

±10

rnA

lout

DC Output Current, per Pin

±20

rnA

IDD

DC Supply Current, VDD and GND Pins

±30

rnA

PD

Power Dissipation, per Package

300

mW

Tstg

Storage Temperature

-65 to + 150

°C

260

°C

lin,lPD

TL

.

lead Temperature, 1 mm from Case for 10 seconds

This device contains protection cir·
cuitry to guard against damage due to
high static voltages or electric fields.
However, precautions must be taken to
avoid applications of any voltage high·
erthan maximum rated voltages to this
high·impedance circuit.

* Maximum Ratings are those values beyond which damage to the device may occur. Func·
tional operation should be restricted to the limits in the Electrical Characteristics tables or
Pin Descriptions section.

MC145192
2-652

MOTOROLA COMMUNICATIONS DEVICE DATA

ELECTRICAL CHARACTERISTICS
(VDD = VCC = 2.7 to 5.0 V. Voltages Referenced to GND. TA = -40 to +85·C. unless othelWlse stated;
Phase/Frequency Detector A VpD = 4.5 to 5.5 V with VDD ,; VpD; Phase/Frequency Detector B VPD = 2.7 to 5.5 V with VDD'; VpD.
Symbol

Parameter

Test Condition

Guaranteed
Limit

Unit

Vil

Maximum low-level Input Voltage
(Din. ClK, ENB. REFln)

Device In Reference Mode

0.2xVDD

V

VIH

Minimum High-level Input Voltage
(Din. ClK. ENB, REFin)

Device in Reference Mode

0.8xVDD

V

VHys

Minimum Hysteresis Voltage (ClK. ENB)

VDD=2.7V
VDD=5.0V

100
300

mV

VOL

Maximum low-level Output Voltage
(REFout, OUTPUT A)

lout = 20 I1A. Device In Reference Mode

0.1

V

VOH

Minimum High-level Output Voltage
(REFout. OUTPUT A)

lout = -20 I1A. Device In Reference Mode

VDD-O.I

V

IOl

Minimum low-level Output Current
(REFout, lD)

Vout=0.4 V

0.25

mA

IOl

Minimum low-level Output Current

Vout=0.4V
VDD. VPD = 2.7 V

0.36

mA

(~R,M

IOl

Minimum low-level Output Current
(OUTPUT A)

Vout=0.4V

0.6

mA

IOl

Minimum low-level Output Current
(OUTPUT B)

Vout= 0.4 V

1.0

mA

IOH

Minimum High-level Output Current
(REFout, lD)

Vout = VDD - 0.4 V

-0.25

mA

IOH

Minimum High-level Output Current

Vout = VPD - 0.4 V
VDD. VPD = 2.7 V

-0.36

mA

Minimum High-level Output Current
(OUTPUT A Only)

Vout = VDD - 0.4 V

-0.35

mA

lin

Maximum Input leakage Current
(Din. ClK. ENB. REFln)

Yin = VDD or GND, Device In XTAl Mode

±1.0

!LA

lin

Maximum Input Current
(REFin)

Yin = VDD or GND. Device In Reference Mode

±150

!LA

IOZ

Maximum Output leakage Current (PDout)

Vout = VpD - 0.5 V or 0.5 V,
Output In High-Impedance State

±200

nA

(OUTPUT B)

Vout = VPD or GND
Output in High-Impedance State

±IO

!LA

(~R.M

IOH

ISTBY

IpD

Maximum Standby Supply Current
(VDD + VPD Pins)

Yin = VDD or GND; Outputs Open; Device in Standby Mode.
Shut-Down Crystal Mode or REFourStatic-low Reference
Mode; OUTPUT B Controlling Vce per Figure 21

50

!LA

Maximum Phase Detector
Quiescent Current (VPD Pin)

Bit C6 = High Which Selects Phase Detector A.
PDout = Open. PDout = Static low or High. Bit C4 = low
Which is not Standby. lAx = 113 !LA. VPD = 5.5 V

600

!LA

Bit C6 = low Which Selects Phase Detector B••R and

30

'ilv = Open ••R and 'ilv = Static low or High. Bit
C4 = low Which Is not Standby
IT

Total Operating Supply Current
(VDD + VPD + VCC Pins)

fin = 1.1 GHz; REFin = 13 MHz @ I Vp-p;
OUTPUT A = Inactive and No Connect; VDD = VCC.
REFout••V••R. PDout. lD = No Connect;
Din. ENB. ClK = VDD or GND. Phase Detector B Selected
(BitC6=low)

*

mA

• The nominal values are:
6 mAat VDD = 2.7Vand VPD = 2.7 V
9 mAat VDD= 5.0 V and VPD = 5.5 V
These are not guaranteed limits.

MOTOROLA COMMUNICATIONS DEVICE DATA

MC145192
2·653

ANALOG CHARACTERISTICS-CURRENT SOURCE/SINK OUTPUT-PDout
(lout'" 2 rnA, VDD = VCC = 2.7 to 5.0 V, Voltages Referenced to GND, VDD = VCC '" VpD)
Parameter

Test Condition

Maximum Source Current Variation (Part-to-Part)

Vout = 0.5 x VPD

Maximum Slnk-vs-Source Mismatch (Note 3)

Vout = 0.5 x VpD

Output Voltage Range (Note 3)

lout variation", 20%

VPD

Guaranteed
Umit

Unit

4.5

±20

%

5.5

±20

4.5

12

5.5

12

4.5

0.5 to 4.0

5.5

0.5 to 5.0

%

V

NOTES:
1. Percentages calculated using the following formula: (Maximum Value - Minimum Value) I Maximum Value.
2. See Rx Pin Description for external resistor values.
3. This parameter is guaranteed for a given temperature within -40 to + 85°C.

AC INTERFACE CHARACTERISTICS
(VDD = VCC= 2.7 to 5.0 V, TA =-40to + 85°e, Cl =50 pF,lnputtr= tf= 10 ns; VPD = 2.7 to 5.5 V with VDD ",VPD)
Parameter

Symbol
fclk

Serial Data Clock Frequency (Note: Refer to Clock Iw below)

Figure #

Guaranteed
Umit

Unit

1

dcto 2.0

MHz

tplH,tPHl

Maximum Propagation Delay, ClK to OUTPUT A (Selected as Data Out)

1,5

200

ns

tPlH, tPHl

Maximum Propagation Delay, ENB to OUTPUT A (Selected as Port)

2,5

200

ns

tpZl, tPLZ

Maximum Propagation Delay, ENB to OUTPUT B

2,6

200

ns

trlH, trHl

Maximum Output Transition Time, OUTPUT A and OUTPUT B; trHlonly, on OUTPUT B

1,5,6

200

ns

10

pF

Figure #

Guaranteed
Umit

Unit

Minimum Setup and Hold Times, Din vs elK

3

50

ns

tsu,th, tree Minimum Setup, Hold and Recovery Times, ENB vs ClK

4

100

ns
cycles

Cin

Maximum Input Capacitance - Din, ENB, ClK,

TIMING REQUIREMENTS
(VDD = Vee = 2.7 to 5.0 V, TA = -40 to + 85°C, Inputtr = tf = 10 ns unless otherwise indicated)
Symbol
tsu, th

Parameter

tw

Minimum Pulse Width, ENB

4

*

tw

Minimum Pulse Width, ClK

1

125

ns

tr,tf

Maximum Input Rise and Fall Times, CLK

1

100

I1S

"The minimum limit is 3 REFin cycles or 195 fin cycles, whichever is greater.

MC145192
2·654

MOTOROLA COMMUNICATiONS DEVICE DATA

SWITCHING WAVEFORMS

~--VDD

elK
GND
OUTPUT A

:0

OUTPUTS

Figure 2.

-VALID
VDD
50%
GND

J:

tw
~'r----

ENS

50%

)

- tsu

- t s u y th
-

GND

t w = t - VGDNDD

th-tree

VDD

50%

ClK

50%

10%

Figure 1.

Din

tPZl~
--5

PLZ
,'r)

OUTPUT A
(DATA OUT)

-

VDD

ClK
GND

Figure 3.

Figure 4.

J

+VPD

TEST POINT

TEST POINT

7.5kn
DEVICE
UNDER
TEST

DEVICE
UNDER
TEST

'Includes all probe and fixture capacitance.

'Includes all probe and fixture capacitance.

Figure 5. Test Circuit

Figure 6. Test Circuit

MOTOROLA COMMUNICATIONS DEVICE DATA

MC145192
2-655

LOOP SPECIFICATIONS (VOO = VCC = 2.7 to 5.0 V unless otherwise indicated, TA = -40 to +85°C)
Guaranteed
Operating
Range
Fig #

Min

Max

Unit

Vin

Input Voltage Range, lin

100 MHz S ~n < 250 MHz
250 MHz S lin S 1100 MHz

7

400
200

1500
1500

mVp-p

Irel

Input Frequency, REFin Externally Driven In
Relerence Mode

Vin = 400 mVp-p, R Counter set to divide
ratio such that IR S 1 MHz, REF Counter set
to divide ratio such that REFout S 5 MHz
VOO=2.7V
VOO=3.0V
VOO=3.5V
VOO =4.5 to 5 V

8

Vin = 1 Vp-p, R Counter set to divide ratio
such that IR S 1 MHz, REF Counter set to
divide ratio such that REFout S 5 MHz
VOO=2.7V
VOO=3.0V
VOO=3.5V
VOO = 4.5 to 5 V

8

Crystal Frequency, Crystal Mode

Cl S 30 pF, C2 S 30 pF, Includes Stray
Capacitance; R Counter and REF Counter
same as above

Output Frequency, REFout

CL=30 pF

Symbol

txTAL

lout
I
tw
ITLH,
ITHL
Cin

MC145192
2-656

Parameter

Test Condition

MHz

1
4.5
5.5
12

20
20
20
27
MHz

1
1.5
2
4.5

20
20
20
27

9

2

10

MHz

10,
12

dc

5

MHz

Operating Frequency 01 the Phase Detectors

dc

1

MHz

Output Pulse Width ( 32

C Register
R Register
A Register
Not Allowed
See Figures
22-25

C7, C6, C5, ... , CO
R15, R14, RI3, ... , RD
A23, A22, A21, ... , AO

MC145192
2-657

ClK
Serial Data Clock Input (Pin 18)
low-to-high transitions on ClK shift bits available at the Din
pin, while high-to-Iow transitions shift bits from OUTPUT A
(when configured as Data Out, see Pin 16). The 24-1 /2-stage
shift register is static, allowing clock rates down to dc in a
continuous or intermittent mode.
Eight clock cycles are required to access the C register.
Sixteen clock cycles are needed for the first buffer of the R
register. Twenty-four cycles are used to access the A register.
See Table 1 and Figures 13, 15, and 16. The number of clocks
required for cascaded devices is shown in Figures 23 through
25.
ClK typically switches near 50% of VDD and has a
Schmitt-triggered input buffer. Slow ClK rise and fall times
are allowed. See the last paragraph of Din for more
information.
CAUTION
To guarantee proper operation of the Power-On
Reset (POR) circuit, the ClK pin must notbe floating
or toggled during power up. It is prefereable to hold
the ClK pin low during power up.
ENB
Active low Enable Input (Pin 17)
This pin is used to activate the serial interface to allow the
transfer of data to/from the device. When ENB is in an inactive
high state, shifting is inhibited and the port is held in the
initialized state. To transfer data to the device, ENB (which
must start inactive high) is taken low, a serial transfer is made
via Din and ClK, and ENB is taken back high. The low-to-high
transition on ENB transfers data to the C or A registers and
first buffer of the R register, depending on the data stream
length per Table 1.
Transitions on ENB must not be attempted while ClK is
high. This puts the device out of synchronization with the
microcontroller. Resynchronization occurs when ENB is high
and ClK is low.
This input is also Schmitt-triggered and switches near 50%
of VDD, thereby minimizing the chance of loading erroneous
data into the registers. See the last paragraph of Din for more
information.
CAUTION
ENB must not be floated or toggled during power up.
It is preferable to hold ENB althe potential olthe VDD
pin during power up to guarantee proper operation of
the POR circuit.
OUTPUT A
Conflgurable Digital Output (Pin 16)
OUTPUT A is selectable as fR, fV, Data Out, or Port. Bits
A22 and A23 in the A registercontrol the selection; see Figure
15.
If A23 = A22 = high, OUTPUT A is configured as fRo This
signal is the buffered output of the 13-stage R counter. The
fR signal appears as normally low and pulses high. The fR
signal can be used to verify the divide ratio of the R counter.
This ratio extends from 5 to 8191 and is determined by the
binary value loaded into bits RO-RI2 in the R register. Also,
direct access to the phase detectors via the REFin pin is
allowed by choosing a divide value of 1 (see Figure 16). The
maximum frequency at which the phase detectors operate is
1 MHz. Therefore, the frequency of fR should not exceed
1 MHz.

MC145192
2-658

If A23 = high and A22 = low, OUTPUT A is configured as
fV. This signal is the buffered output of the 12-stage N counter.
The fV signal appears as normally low and pulses high. The
fV signal can be used to verify the operation of the prescaler,
A counter, and N counter. The divide ratio between the fin input
and the fV Signal is N x 64 + A. N is the divide ratio of the N
counter and A is the divide ratio of the A counter. These ratios
are determined by bits loaded into the A register. See
Figure 15. The maximum frequency at which the phase
detectors operate is 1 MHz. Therefore, the frequency of fV
should not exceed 1 MHz.
If A23 = low and A22 = high, OUTPUT A is configured as
Data Out. This signal is the serial output of the 24-1/2-stage
shift register. The bit stream is shifted out on the high-to-Iow
transition of the ClK input. Upon power up, OUTPUT A is
automatically configured as Data Out to facilitate cascading
devices.
If A23 = A22 = low, OUTPUT A is configured as Port. This
signal is a general-purpose digital output which may be used
as an MCU port expander. This signal is low when the Port
bit (Cl) of the C register is low, and high when the Port bit
is high.
OUTPUTB
Open-Drain Digital Output (Pin 15)
This signal is a general-purpose digital output which may
be used as an MCU port expander. This signal is low when
the Out B bit (CO) of the C register is low. When the Out B
bit is high, OUTPUT B assumes the high-impedance state.
OUTPUT B may be pulled up through an external resistor or
active circuitry to any voltage less than or equal to the potential
of the VPD pin. Note: the maximum voltage allowed on the
VPD pin is 5.5 V for the MC145192.
Upon power-up, power-on reset circuitry forces OUTPUT
B to a low level.
REFERENCE PINS
REFin and REFout
Reference Input and Reference Output (Pins 20 and 1)
Configurable pins for a Crystal or an External Reference.
This pair of pins can be configured in one of two modes: the
crystal mode orthe reference mode. Bits R13, R14, and R15
in the R register control the modes as shown in Figure 16.
In crystal mode, these pins form a reference oscillator when
connected to terminals of an external parallel-resonant crystal.
Frequency-setting capaCitors of appropriate values, as
recommended by the crystal supplier, are connected from
each of the two pins to ground (up to a maximum of 30 pF
each, including stray capacitance). An external resistor of
1 Mn to 15 Mn is connected directly across the pins to ensure
linear operation of the amplifier. The device is designed to
operate with crystals up to 10 MHz; the required connections
are shown in Figure 9. To turn on the oscillator, bits R15, R14,
and R13 must have an octal value of one (001 in binary,
respectively). This is the active-crystal mode shown in
Figure 16. In this mode, the crystal oscillator runs and the R
Counter divides the crystal frequency, unless the part is in
standby. If the part is placed in standby via the C register, the
oscillator runs, but the R counter is stopped. However, if bits
R15 to R13 have a value of 0, the oscillator is stopped, which
saves additional power. This is the shut-down crystal mode
(shown in Figure 16) and can be engaged whether in standby
or not.

MOTOROLA COMMUNICATIONS DEVICE DATA

With the reference mode, the REFout pin is configured as
the output of a divider. As an example, if bits R15, R14, and
R13 have an octal value of seven, the frequency at REFout is
the REFln frequency divided by 16. In addition, Figure 16
shows how to obtain ratios of eight, four, and two. A ratio of
one-to-one can be obtained with an octal value of three. Upon
power up, a ratio of eight is automatically Initialized. The maximum frequency capability of the REFout pin is 5 MHz for VDD
to VSS swing. Therefore, for REFin frequencies above 5 MHz,
the one-to-one ratio may not be used for large signal swing requirements. Likewise, for REFin frequencies above 10 MHz,
the ratio must be more than two.
lf REFout is unused, an octal value of two should be used for
R15, R14, and R13 and the REFout pin should be floated.
A value of two allows REFin to be functional while disabling
REFout, which minimizes dynamic power consumption and
electromagnetic interference (EM I).
LOOP PINS
fin and fin
Frequency Inputs (Pins 11 and 10)
These pins are frequency inputs from the VCO. These pins
feed the on-board RF amplifier which drives the 64/65 prescaler. These inputs may be fed differentially. However, they
are usually used in a single-ended configuration (shown in
Figure 7). Note that fin is driven while iiii must be tied to ground
via a capaCitor.
Motorola does not recommend driving iiii while terminating
fin because this configuration is not tested for sensitivity. The
sensitivity is dependent on the frequency as shown In the Loop
Specifications table.
PDout
Single-Ended Phase/Frequency Detector Output (Pin 6)
This is a three-state current-source/sink output for use as a
loop error signal when combined with an external low-pass filter. The phase/frequency detector is characterized by a linear
transfer function. The operation of the phase/frequency detector is described below and is shown in Figure 17.
POL bit (C7) in the C register = low (see Figure 13)
Frequency of fV > fR or Phase of fV Leading fR: currentsinking pulses from high impedance
Frequency of fV < fR or Phase of fV Lagging fR: currentsourcing pulses from high impedance
Frequency and Phase of fV = fR: essentially high-impedance state; voltage at pin determined by loop filter
POL bit (C7) = high
Frequency of fV > fR or Phase of fV Leading fR: currentsourcing pulses from high impedance
Frequencyoffv < fR or Phase offV LaggingfR: current-sinkIng pulses from high impedance
Frequency and Phase of fV = fR: essentially highimpedance state; voltage at pin determined by loop filter
This output can be enabled, disabled, and inverted via the
C register. If desired, PDout can be forced to the highimpedance state by utilization of the disable feature in the C
register (bit C6l. This is a patented feature. Similarly, PDout is
forced to the high-impedance state when the device is put into
standby (STBY bit C4 = high).
The PDout circuit is powered by VPD. The phase detector
gain is controllable by bits C3, C2, and C1: gain (In amps per
radian) = PDout current divided by 21t.

MOTOROLA COMMUNICATIONS DEVICE DATA

eIIR and eIIv (Pins 3 and 4)
Double-Ended Phase/Frequency Detector Outputs
These outputs can be combined externally to generate a
loop error signal. Through use of a Motorola patented technique, the detector's dead zone has been eliminated.
Therefore, the phaselfrequency detector is characterized by
a linear transfer function. The operation olthe phase/frequency detector is described below and is shown in Figure 17.
POL bit (C7) in the C register = low (see Figure 13)
Frequencyoffv>fRorPhaseoffvLeadingfR:eIIv=negative
pulses, eIIR = essentially high
Frequency offV < fR or Phase offV Lagging fR: eIIv = essentially high, eIIR = negative pulses
Frequency and Phase of fV = fR: eIIv and eIIR remain essentially high, except for a small minimum time period when
both pulse low in phase
POL bit (C7) = high
Frequencyoffv> fR or Phase offV LeadingfR: eIIR = negative
pulses, eIIv = essentially high
Frequency of fV < fR or Phase of fV Lagging fR: eIIR = essentially high, eIIv = negative pulses
Frequency and Phase of fV = fR: eIIv and eIIR remain essentially high, except for a small minimum time period when
both pulse low in phase
These outputs can be enabled, disabled, and interchanged
via C register bits C6 or C4. This is a patented feature. Note
that when disabled or in standby, eIIR and eIIv are forced to their
rest condition (high state).
The eIIR and eIIv output Signal swing is approximately from
GNDtoVpD·
LD
Lock Detector Output (Pin 2)
This output is essentially at a high level with narrow lowgoing pulses when the loop is locked (fR and fV of the same
phase and frequency). The output pulses low when tv and fR
are out of phase or different frequencies. LD Is the logical
ANDing of eIIR and eIIv (see Figure 17).
This output can be enabled and disabled via the C register.
This is a patented feature. Upon power up, on-chip initialization circuitry disables LD to a static low logic level to prevent
a false "lock" signal. If unused, LD should be disabled and left
open.
.
The LD output signal swing is approximately from GND to
VDD·
Rx
External Resistor (Pin 8)
A resistor tied between thispinandGND, in conjunction with
bits in the C register, determines the amount of current that the
PDout pin sinks and sources. When bits C2 and C3 are both
set high, the maximum current is obtained at PDout; see Tables
2 and 3 for other current values. To achieve a maximum current of 2 rnA, the resistor should be about 18 kn when VPD Is
5 V. See Figure 14 if lower maximum current values are desired.
When the eIIR and eIIv outputs are used, the Rx pin may be
floated.

MC145192
2-659

TEST POINT PINS
TEST 1
Modulus Control Signal (Pin 9)
..
This pin may be used in conjunction with the Test 2 pin for
access to the on-board 64/65 prescaler. When Test 1 is low,
the prescaler divides by 65. When high, the prescaler divides
by 64.
.
CAUTION
This pin is an unbuffered output and must be floated
in an actual application. This pin must be attached to
an isolated pad with no trace. There is the possibility
that the final production version of the device will
have this lead clipped at the body of the package.
TEST 2
Prescaler Output (Pin 13)
This pin may be used to access to the on-board 64/65
prescaler output.

olthe device. The voltage range is +2.7 to +5.0 V with respect
to the GND pin.
Foroptimum performance, VDD should be bypassedtoGND
using a low-inductance capacitor mounted very close to these
pins. Lead lengths on the capacitor should be minimized.
VCC
Positive Power Supply (Pin 12)
This pin supplies power to the RF amp and 64/65 prescaler.
The voltage range is +2.7 to +5.0 V with respect to the GND
pin. In standby mode, the VCC pin still draws a few milliamps
from the power supply. This current drain can be eliminated
with the use of transistor Q1 as shown in Figure 21.
Foroptimum performance, VCC should be bypassed to GND
using a low-inductance capacitor mounted very close to these
pins. Lead lengths on the capacitor should be minimized.

POWER SUPPLY PINS

VPD
Positive Power Supply (Pin 5)
This pin supplies power to both phaselfrequency detectors
A and B. The voltage applied on this pin must be no less than
the potential applied to the VDD pin. The voltage range for VPD
is 4.5 to 5.5 V with respect to the GND pin when using PDOUT
and 2.7 to 5.5 V when using «!JR, W outputs.
Foroptimum performance, VPD should be bypassed to GND
using a low-inductance capacitor mounted very close to these
pins. Lead lengths on the capacitor should be minimized.

VDD
Positive Power Supply (Pin 14)
This pin supplies power to the main CMOS digital portion

GND
Ground (Pin 7)
Common ground.

CAUTION
This pin is an unbuffered output and must be floated
in an actual application. This pin must be attached to
an isolated pad with no trace. There is the possibility
that the final production version of the device will
have this lead clipped at the body of the package.

MC145192

2-660

MOTOROLA COMMUNICATIONS DEVICE DATA

ENB

l

I

+
*

CLK
LSB

MSB
Din

~

C7

~

C6

~

C5

~

C4

~

C3

~

C2

~

Cl

~

CO

~

• At this point, the new byte is transferred to the C register and stored. No other registers are affected.

C7 -

C6 -

POL:

Selects the output polarity of the phase/frequency detectors. When set high, this bit inverts PDout
and interchanges the $R function with $V as depicted in Figure 17. Also see the phase detector output
pin descriptions for more information. This bit is cleared low at power up.

PDAlB:

Selects which phase/frequency detector is to be used. When set high, enables the output of phase/frequency detector A (PDout) and disables phase/frequency detector B by forcing $R and $V to the static
high state. When cleared low, phase/frequency detector B Is enabled ($R and $V) and phase/frequency
detector A is disabled with PDout forced to the high-impedance state. This bit is cleared low at power
up.

C5 C4 -

LDE:

Enables the lock detector output when set high. When the bit is cleared low, the LD output is forced
to a static low level. This bit is cleared low at power up.

STBY:

When set, places the CMOS section of device, which is powered by the VDD and VPD pins, in the
standby mode for reduced power consumption: PDout is forced to the high-impedance state, $R and
v are forced high, the A, N, and R counters are inhibited from counting, and the Rx current is shut
off. In standby, the state of LD Is determined by bit C5. C5 low forces LD low (no change). C5 high
forces LD static high. During standby, data is retained In the A, R, and C registers. The condition
of REF/OSC circuitry is determined by the control bits in the R register: R13, R14, and R15. However,
if REFout = static low is selected, the Internal feedback resistor is disconnected and the input is inhibited
when in standby; In addition, the REFin input only presents a capacitive load. NOTE: Standby does
not affect the other modes of the REF/OSC circuitry.
When C4 Is reset low, the part is taken out of standby in 2 steps. First, the REFin (only in one mode)
resistor is reconnected, all counters are enabled, and the Rx current is enabled. Any fR and tv signals
are inhibited from toggling the phase/frequency detectors and lock detector. Second, when the first
tv pulse occurs, the R counter is jam loaded, and the phase/frequency and lock detectors are initialized. Immediately aiter the jam load, the A, N, and R counters begin counting down together. At
this point, the fR and tv pulses are enabled to the phase and lock detectors. (Patented feature.)

C3, C2 -12, 11:

Controls the PDout source/sink current per Tables 2 and 3. With both bits high, the maximum current
(as set by Rx per Figure 14) Is available. Also, see Cl bit description.

Cl -

Port:

When the OUTPUT A pin is selected as "Port" via bits A22 and A23, Cl determines the state of
OUTPUT A. When Cl is set high, OUTPUT A Is forced high; Cl low forces OUTPUT A low. When
OUTPUT A Is not selected as "Port," Cl controls whether the PDout step size is 10% or 25%. (See
Tables 2 and 3.) When low, steps are 10%. When high, steps are 25%. Default is 10% steps when
OUTPUT A is selected as "Port." The Port bit is not affected by the standby mode.

Out B:

Determines the state of OUTPUT B. When CO Is set high, OUTPUT B Is high-Impedance; CO low
forces OUTPUT B low. The Out B bit is not affected by the standby mode. This bit is cleared low
at power up.

CO -

Figure 13. C Register Access and Format (8 Clock Cycles are Used)

MOTOROLA COMMUNICATIONS DEVICE DATA

MC145192
2-661

100

\ \\

90

\' \

80

\\~

70

~

a:
~
(f)

60

a:

50

en
w

--'

«z

a:
w
>xw
,;:
a:

PDoul CURRENT SET TO 100%;
PDout VOLTAGE IS FORCED TO VpD DIVIDED BY 2.

\ 1\'\
\
~ \ '\

"" 1"-'r"-"
"

40

"

.......

~

30
20

...........

'"

r--.... ...........

.........

10

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

1.1

'" - -- -

.........
~
.........

1.2

"""

1.3

.........

j'-. ........ j'-. l"-

i"'--

1.4

1.5

r-

i"'--_

l"- I'--

1.6

1.7

I.B

1.9

2.0

VpD=5.5V VpD = 5.0 V
vpr4Y I
2.1

I
2.2

2.3

lout, SOURCE CURRENT (mA)
NOTE: The MC145192 is optimized for Rx values in the 18 kn to 40 kn range. For example, to achieve 0.3 rnA of output
current, it is preferable to use a 30-kn resistor for Rx and· bit settings for 25% (as shown in Table 3).

Figure 14. Nominal Source Current for the PDout Pin

Table 2. PDout Current, C1 = Low with OUTPUT A NOT
Selected as "Port"; Also, Default Mode When
OUTPUT A Selected as "Port"

MC145192
2-662

C3

C2

PDout Current

a

a

0
1
1

a

70%
80%
90%
100%

1
1

Table 3. PDout Current, C1 = High with OUTPUT A NOT
Selected as "Port"
C3

C2

PDout CUrrent

a
a

a

25%
50%
75%
100%

1
1

1
0
1

MOTOROLA COMMUNICATIONS DEVICE DATA

s::

a
~

~I

~

~

tI

s::
c

NOTE 3

z

o
~

oz
C/l

c
~

o

m

c

»~

CLK

:!!

Ir::I
C

...iil
!"
:a-

::a

Din

111

Ir::I

.

iii

S"

~
111

III
III
III
~

Do

.

"TI
0

3
!!l.

i

0

0"

n

:0;-

0

Ii

Ii"
III
III

iil

c:

III
CD

.s

is:

...o
N""
lUI

Q) ...

~IS

'----...---'

II
0
0

0
0
1

~

PORr
DalaOut
fv
fR

BOTH BITS
MUST BE
HIGH

0
0
0
0
0
0
0
0

0
0
0
0
0
0
0
0

0
2
3
4
5
6
7

NOT ALLOWED
NOT ALLOWED
NOT ALLOWED
NOT ALLOWED
NOT ALLOWED
NCOUNTER = +5
N COUNTER = +6
N COUNTER =+7

~

BINARY OUTPUT A
VALUE FUNCTION
(NOTE 1)

F

F

E N COUNTER = +4094

F

F

F

.,

HEXADECIMAL VALUE
FOR N COUNTER

0
0
0
0

0

1
2
3

ACOUNTER
ACOUNTER
ACOUNTER
ACOUNTER

=+0
= +1
=+2
=+3

3

E ACOUNTER =+62
F ACOUNTER =+63

4
4

0
1

NOT ALLOWED
NOT ALLOWED

N COUNTER = +4095
F
F NOT ALLOWED
'--v--'
HEXADECIMAL VALUE
FOR ACOUNTER

Notes:
1. A power-on initialize circuit forces the OUTPUT A function to default to Data Out.
2. The values programmed for the N counter must be greater than or equal to the values programmed for the A counter. This results in a total divide value = N x 64 + A.
3. At this point, the three new bytes are transferred to the A register. In addition, the 13 LSBs in the first buffer of the R register are transferred to the R register's second buffer.
Thus, the R, N, and A counters can be presented new divide ratios at the same time. The first buffer of the R register is not affected. The C register is not affected.

l

ENB

J1f

NOTE NOTE
4
5

CLK
LSB
RO

Din

3
4
5
6
7

L

CRYSTAL MODE,"SHUT DOWN
CRYSTAL MODE, ACTIVE
REFERENCE MODE, REFin ENABLED and REFout
STATIC LOW
REFERENCE MODE, REFout = REFin (BUFFERED)
REFERENCE MODE, REFout = REFinl2
REFERENCE MODE, REFout = REFinl4
REFERENCE MODE, REFout = REFinl8 (NOTE 3)
REFERENCE MODE, REFout = REFinl16

o

o
1
2
3
4
5
6
7
8

o
o

o
o
o
o

o
o

NOT ALLOWED
DIRECT ACCESS TO REFERENCE SIDE OF PHASE/FREQUENCY DETECTORS
NOT ALLOWED
NOT ALLOWED
NOT ALLOWED
R COUNTER = +5
R COUNTER =+6
R COUNTER =+ 7
RCOUNTER=+8

OCTAL VALUE
1
1

BINARY VALUE

F
F

F
F

E RCOUNTER=+8190
F R COUNTER =+8191

--.J H~ VALUE

NOTES:
1, Bits R15 through R13 control the configurable "ose or 4-stage divider" block (see Block Diagram),
2, Bits R12 through RO control the "13-stage R counter" block (see Block Diagram),
3, A power-on initialize circuit forces a default REFin to REFout ratio of eight
4, At this point, bits R13, R14, and R15 are stored and sent to the "ose or 4-Stage Divider" block in the Block Diagram, Bits RO-R12 are loaded
into the first buffer in the double-buffered section of the R register, Therefore, the R counter divide ratio is not altered yet and retains the previous ratio loaded, The e and A registers are not affected,
5, At this point, bits RO-R12 are transferred to the second buffer of the R register. The R counter begins dividing by the new ratio after completing the rest of the present count cycle. eLK must be low during the ENB pulse, as shown. Also, see note 3 of Figure 15 for an alternate
method of loading the second buffer in the R register. The e and A registers are not affected. The first buffer of the R register is not affected.

Figure 16. R Register Access and Format (16 Clock Cycles Are Used)
fR
REFERENCE
REFin + R

tv

FEEDBACK
fin+(Nx64+A)

PDout
$R

$v

LD

n

n
LJ,

n
VL

n
,

,

*

-

'UI-,- - - - - - - - \ - - - - HIGH IMPEDANCE
-

U

SINKING CURRENT

r-------~:TI-----------r-----VH

W

"

-VL

---~~---------~~--------;LJ

I

SOURCING CURRENT

:, I'
' '
U

"

VH
-VL

'~'- - - - - r - - - - V H

u

-VL

VH = High voltage level
VL =Low voltage level
• At this point, when both fR and tv are in phase. the output source and sink circuits are turned on for a short interval.
NOTE: The PDout either sources or sinks current during out-of-Iock conditions. When locked in phase and frequency, the output is high
impedance and the voltage at that pin is determined by the low-pass filter capacitor. PDout. $R, and $V are shown with the polarity bit
(POL) = low; see Figure 13 for POL.

Figure 17. Phase/Frequency Detectors and Lock Detector Output Waveforms

MC145192
2-664

MOTOROLA COMMUNICATIONS DEVICE DATA

DESIGN CONSIDERATIONS
CRYSTAL OSCILLATOR CONSIDERATIONS
The following options may be considered to provide a reference frequency to Motorola's CMOS frequency synthesizers.
Use of a Hybrid Crystal Oscillator
Commercially available temperature-compensated crystal
oscillators (TCXOs) or crystal-controlled data clock oscillators
provide very stable reference frequencies. An oscillator capable of CMOS logic levels at the output may be direct or dc
coupled to REFin. If the oscillator does not have CMOS logic
levels on the outputs, capacitive or ac coupling to REFin may
be used (see Figure 8).
For additional information about TCXOs and data clock
oscillators, please consult the latest version of the eem Electronic Engineers Master Catalog, the Gold Book, or similar
publications.

To verify that the maximum dc supply voltage does not
cause the crystal to be overdriven, monitor the output
frequency (fR) at OUTPUT A as a function of supplyvoltage.
(R EF out is not used because loading impacts the oscillator.)
The frequency should increase very slightly as the dc supply voltage is increased. An overdriven crystal decreases in
frequency or becomes unstable with an increase in supply
voltage. The operating supply voltage must be reduced or
R 1 must be increased in value if the overdriven condition exists. The user should note that the oscillator start-up time is
proportional to the value of R1.
Through the process of supplying crystals for use with
CMOS inverters, many crystal manufacturers have developed expertise in CMOS oscillator design with crystals.
Discussions with such manufacturers can prove very helpful (see Table 4).

Design an Off-Chip Reference
The user may design an off-chip crystal oscillator using discrete transistors or ICs specifically developed for crystal
oscillator applications, such as the MC12061 MECL device.
The reference signal from the MECL device is ac coupled to
REFin (see Figure 8). For large amplitude signals (standard
CMOS logic levels), dc coupling may be used.

I
L
REFin

RI'

Use of the On-Chip Oscillator Circuitry
The on-chip amplifier (a digital inverter) along with an appropriate crystal may be used to provide a reference source
frequency. A fundamental mode crystal, parallel resonant at
the desired operating frequency, should be connected as
shown in Figure 18.
The crystal should be specified for a loading capacitance
(CLl which does not exceed approximately 20 pF when used
at the highest operating frequency of 10 MHz. Assuming
R1 = 0 n, the shunt load capacitance (CLl presented across
the crystal can be estimated to be:

CIT T C2
'May be needed in certain cases. See text.

Figure 18. Pierce Crystal Oscillator Circuit

CinCout
C1 • C2
CL = ----=-=--=~ + Ca + Cstray + - - - Cin + Cout
C1 + C2

REFin

0

Cin = 5 pF (see Figure 19)
Cout = 6 pF (see Figure 19)
C a = 1 pF (see Figure 19)

~

I

o REFout

Cstray

C1 and C2 =external capacitors (see Figure 18)
Cstray =the total equivalent external circuit stray capacitance appearing across the crystal terminals

MOTOROLA COMMUNICATIONS DEVICE DATA

I

--L
--L
-r Cin IL __ II __ .JI Cout -1II
~
~

where

The oscillator can be "trimmed" on-frequency by making a
portion or all of C1 variable. The crystal and associated components must be located as close as possible tothe REFin and
REFout pins to minimize distortion, stray capacitance, stray
inductance, and startup stabilization time. Circuit stray capacitance can also be handled by adding the appropriate stray
value to the values forCin and Couto Forthis approach, the term
Cstray becomes 0 in the above expression for CL.
Power is dissipated in the effective series resistance of
the crystal, Re , in Figure20. The maximum drive level specified by the crystal manufacturer represents the
maximum stress that the crystal can withstand without
damage or excessive shift in operating frequency. R1 in
Figure 181imits the drive level. The use of R1 is not necessary in most cases.

REFout

Rf

Figure 19. Parasitic Capacitances of the
Amplifier and Cstray

I

0

2

0---1 1---0

Note: Values are supplied by crystal manufacturer
(parallel resonant crystal).

Figure 20. Equivalent Crystal Networks

MC145192
2-665

RECOMMENDED READING
Technical Note TN-24, Statek Corp.
Technical Note TN-7, Statek Corp.
E. Hafner, "The Piezoelectric Crystal Unit-Definitions and
Method of Measurement", Proc. IEEE, Vol. 57, No.2, Feb.
1969.
D. Kemper, L. Rosine, "Quartz Crystals for Frequency

Control", Electro-Technology, June 1969.
P. J. Ottowitz, "A Guide to Crystal Selection", Electronic
Design, May 1966.
D. Babin, "Designing Crystal Oscillators", Machine Design,
March 7, 1985.
D. Babin, "Guidelines for Crystal Oscillator Design",
Machine Design, April 25, 1985.

Table 4. Partial List of Crystal Manufacturers
Name

Phone

Address

United States Crystal Corp.
Crystek Crystal
Statek Corp.
Fox Electronics

3605 McCart Ave., Ft. Worth, TX 76110
2371 Crystal Dr., Ft. Myers, FL 33907
512 N. Main St., Orange, CA 92668
5570 Enterprise Parkway, Ft. Myers, FL 33905

(817) 921-3013
(813) 936-2109
(714) 639-7810
(813) 693-0099

. .

Note: Motorola cannot recommend one suppher over another and In no way suggests that thiS IS a complete hstlng of crystal manufacturers .
PHASE-LOCKED LOOP-LOW-PASS FILTER DESIGN
(A)

~= V~

PDOut~VCO
C

B.V

J

~ = 2

K",KVCOC
N

~RC

2

Z(s) = 1 +s~RC
NOTE:
For (A), using ~ in amps per radian with the filter's impedance transfer function, Z(s), maintains units of volts per radian for the detectorl
filter combination. Additional sideband filtering can be accomplished by adding a capaCitor C' across R. The comer roc = 1IRC' should be
chosen such that ron is not significantly affected.
R2

(8)

~=

Rl

V

f-----i~

UHF OUTPUT

SUFFER
NOTES:
1_ When used, the $R and $V outputs are fed to an external combiner/loop filter_ See the Phase-Locked
loop - Low-Pass Filter Design page for additional information_
2_ Transistor01 is required only if the standby feature is needed_ 01 permits the bipolar section of the device
to be shut down via use of the general-purpose digital pin, OUTPUT B. If the standby feature is not needed, tie pin 12 directly to the power supply.
3. Foroptimum performance, bypass the Vee, VDD, andVpD pins to GND with low-inductance capacitors.
4. The R counter is programmed for a divide value = REFin/fR. Typically, fR is the tuning resolution required
for the veo. Also, the veo frequency divided by fR =NT =N x 64 + A; this determines the values (N,
A) that must be programmed into the N and A counters, respectively.

Figure 21, Example Application

DEVICE #1
Din

ClK

ENS

DEVICE #2
OUTPUT A
(DATA OUT)

Din

I

f

ClK

ENS

OUTPUT A
(DATA OUT)

CMOS
MCU
OPTIONAL

Figure 22. Cascading TWo Devices

MOTOROLA COMMUNICATIONS DEVICE DATA

MC145192
2-667

N5:
mo

01 ....

e» ....
en
....

IS

ENB

I

l

t

CLK

~JlYLfLl\JlfLMJtfLJLJ\JtfLJLJ\JUL*

Din

~

ay]':I a
It

X

X

S

It

C7H C6

'--

U';=l
v

CD

a-X]

"

X

~U);

.H

S

s)

X

~

a ~ ;;=1
It

X

X

C REGISTER BITS OF DEVICE #2
IN FIGURE 22

X

~

C7

~

'-

It

C6

~ ;;

Bco ~
J

v

C REGISTER BITS OF DEVICE #1
IN FIGURE 22

*At this point, the new bytes are transferred to the C registers of both devices and stored. No other registers are affected.

Figure 23. Accessing the C Registers of Two Cascaded Devices

I

~l
s::

~
~

CLK

s;:
()

o
s::
s::
c

Om

t

~~JUU\~JUU\J1-fLJ1Jl1\JLfL@ 8 8:: ~ B
X

X

A23

A22

a:: 8

A16

~ ~:~ ~ ~
A15

z

'-----v--

~

A REGISTER BITS OF DEVICE #2
IN FIGURE 22

(')

oz
en

o

~

(')
m

o
»~

AS

A7

a:: 8 a
AD

A23

~ :~:

/\....

a

A9

~ ~ :~ ~ ~
AS

Y"""

AD

.-/

A REGISTER BITS OF DEVICE #1
IN FIGURE 22

*Atthis point, the new bytes are transferred to theA registers of both devices and stored. AddHionally, for both devices, the 13 LSBs in each of the first buffers of the R registers are
transferred to the respective R register's second buffer. Thus, the R, N, and A counters can be presented new divide ratios at the same time. The first buffer of each R register is not affected.
NeHher C register is affected.

Figure 24. Accessing the A Registers of TWo Cascaded Devices

;::

@
JJ

0

r

»
()

0
;::
;::

c
C5
~
6

z

m

0

!!
ca
c
Cil

<

C5

!II

z

C/)

m
0

?:j

»

I\)

&"

[31J f321

n

ft)

I/)

!!!.

..

~

ENBl

ClK

:0

t

I33l

t

Nole 1 Nole 2

~JlflJ\s-fLfL.fL~s-J31U32U33yJiflJ\~

ca

::r

ft)

:tI
:tI
ft)

ceo
!!l
ft)

iil

a

Din

~ 8
X

X

a::

~ ~ ~:: ~ H ~
R15

'--

R14

RB

R7

::

-vR REGISTER BITS OF DEVICE #2
IN FIGURE 22

HRO ~
/

X

a::

8x

a ~:: ~ ~ ~ :~ B ~
R15

RB

R7

RO

~~
R REGISTER BITS OF DEVICE #1
IN FIGURE 22

~

0

..
0

10

n

8.
ft)

a.
C

ft)

:S.

..

n
ft)

2:

o-"

N"'"
,U1
01-"
OlIO
ION

Notes Applicable To Each Device:
1. At this point. bits R13. R14, and R15 are stored and sent to the
or 4-Stage Divider" block in the Block Diagram. Bits RD through R12 are loaded into the first buffer in the doublebuffered section of the R register. Therefore, the R counter divide ratio is not altered yet and retains the previous ratio loaded. The and A registers are not affected.
2. At this point, the bits RD through R12 are transferred to the second buffer of the R register. The R counter begins dividing by the new ratio after completing the rest of the present count
cycle. elK must be low during the ENB pulse, as shown. Also, see note of Figure 24 for an altemate method of loading the second buffer in the R register. The e and A registers
are not affected. The first buffer of the R register is not affected.

'ose

e

MOTOROLA

-

SEMICONDUCTOR
TECHNICAL DATA

MC145200
MC145201

Product Preview

2.0 GHz PLL Frequency
Synthesizers
Include On-Board 64/65 Prescalers
The MC145200 and MC145201 are single-package synthesizers with serial
interfaces capable of direct usage up to 2.0 GHz. A special architecture makes
these PLLs very easy to program because a by1e-oriented format is utilized. Due
to the patented BitGrabber™ registers, no address/steering bits are required for
random access of the three registers. Thus, tuning can be accomplished via a
3-by1e serial transfer to the 24-bit A register. The interface is both SPI and
MICROWIRETM compatible.
Each device features a single-ended current source/sink phase detector output
and a double-ended phase detector output. Both phase detectors have linear
transfer functions (no dead zones). The maximum current of the single-ended
phase detector output is determined by an external resistor tied from the Rx pin
to ground. This current can be varied via 1he serial port.
The MC145200 features logic-level converters and high-voltage phase/
frequency detectors; the detector supply may range up to 9.5 V. The MC145201
has lower-voltage phase/frequency detectors optimized for single-supply systems
of 5 V±10%.
Each part includes a differential RF input which may be operated in a
single-ended mode. Also featured are on-board support of an external crystal and
a programmable reference output. The R, A, and N counters are fully programmable. The C register (configuration register) allows the parts to be configured
to meet various applications. A patented feature allows the C register to shut off
unused outputs, thereby minimizing system noise and interference.
In order to have consistent lock times and prevent erroneous data from being
loaded into the counters, on-board circuitry synchronizes the update of the A
register if the A or N counters are loading. Similarly, an update of the R register
is synchronized if the R counter is loading.
The double-buffered R register allows new divide ratios to be presented to the
three counters (R, A, and N) simultaneously.
•
•
•
•

•
•
•
•
•
•
•
•
•

.#
1

FSUFFIX
SaG PACKAGE
CASE 751J

ORDERING INFORMATION
MC145200F
MC145201F

SaG Package
SaG Package

PIN ASSIGNMENT
REFaut

REFin

LD

Din

-____1~5~ OUTPUT B
(OPEN·DRAIN
OUTPUT)

fin _ _1",,1_ _-1
...-_ _ _ _---:13. TEST2

iiri _---:1;:..0_--I
SUPPLY CONNECTIONS:
PIN 12 = VCC (V+ TO INPUT AMP AND 64165 PRESCAlER)
PIN 5 = VpD (V+ TO PHASEIFREQUENCY DETECTORS AAND B)
PIN 14 = VDD 0/+ TO BALANCE OF CIRCUIT)
PIN 7 = GND (COMMON GROUND)

L-_ _ _ _ _~--------------=_

TEST 1

MAXIMUM RATINGS· (Voltages Referenced to GND, unless otherwise stated)
Symbol

Parameter

Value

Unit

-0.5 to +6.0

V

VDD -0.5 to + 9.5
VDD -0.5 to + 6.0

V

VCC,
VDD

DC Supply Voltage (Pins 12 and 14)

VPD

DC Supply Voltage (Pin 5)

Vin

DC Input Voltage

-0.5 to VDD +0.5

V

Vout

DC Output Voltage
(except OUTPUT B, PDout, $R, $v)

-0.5 to VDD +0.5

V

Vout

DC Output Voltage (OUTPUT B, PDout, 'i>R, $v)

Iln,lPD

MCI45200
MCI45201

-0.5 to VPD + 0.5

V

DC Input Current, per Pin (Includes VPD)

±10

mA
mA

lout

DC Output Current, per Pin

±20

100

DC Supply Current, VDD and GND Pins

±30

mA

Po

Power Dissipation, per Package

300

mW

Tstg

Storage Temperature

TL

Lead Temperature,
1 mm from Case for 10 seconds

-65 to +150

·C

260

·C

This device contains protection circuitry
to guard against damage due to high static
voltages or electric fields. However, precautions must be taken to avoid applications of
any voltage higher than maximum rated
voltages to this high-impedance circuit.

• Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the limits in the Electrical Characteristics tables or
Pin DeSCriptions section.

MOTOROLA COMMUNICATIONS DEVICE DATA

MC145200.MC145201
2-671

ELECTRICAL CHARACTERISTICS
(VDD = Vee = 4.5 to 5.5 V, Voltages Referenced to GND, TA = -40 to + 85"C, unless otherwise stated;
MC145200: VpD= 8.0 to 9.5 V; MC145201: VPD = 4.5 to 5.5 V with VDD ,;VpD.
Symbol

Parameter

Test Condition

Guaranteed
Limit

Unit

Vil

Maximum low-level Input Voltage
(Din, ClK, ENB, REFin)

Device in Reference Mode

0.3xVDD

V

VIH

Minimum High-level Input Voltage
(Din, elK, ENB, REFin)

Device in Reference Mode

0.7xVDD

V

Vhys

Minimum Hysteresis Voltage (ClK, ENB)

300

mV

VOL

Maximum low-level Output Voltage
(REFout, OUTPUT A)

lout = 20 ItA, Device in Reference Mode

0.1

V

VOH

Minimum High-level Output Voltage
(REFout, OUTPUT A)

lout = -20 IlA, Device in Reference Mode

VDD-O.1

V

IOL

Minimum low-level Output Current
(REFout, lD, v

-0.36

mA

IOl

Minimum low-Level Output Current
(OUTPUT A, OUTPUT B)

Vout= 0.4 V

1.0

rnA

IOH

Minimum High-Level Output Current
(OUTPUT A Only)

Vout = VDD - 0.4 V

-0.6

rnA

lin

Maximum Input Leakage Current
(Din, ClK, ENB, REFin)

Yin = VDD or GND, Device in XTAL Mode

± 1.0

IlA

lin

Maximum Input Current
(REFin)

Yin = VDD or GND, Device in Reference Mode

± 100

IlA

IOZ

Maximum Output Leakage Current (PDout)

Vout = VpD - 0.5 or 0.5 V
Output in High-Impedance State

± 150
±200

nA

IOZ

Maximum Output Leakage Current
(OUTPUT B)

Vout = VpD or GND,
Output in High-Impedance State

±10

IlA

Maximum Standby Supply Current
(VDD + VPD Pins)

Yin = VDD or GND; Outputs Open; Device in Standby Mode,
Shut-Down Crystal Mode or REFout-Static-Low Reference
Mode; OUTPUT B Controlling VCC per Figure 21

50*

IlA

Maximum Phase Detector
Quiescent Current (VPD Pin)

Bit C6 = High Which Selects Phase Detector A,
PDout = Open, PDout = Static Low or High, Bit C4 = Low
Which is not Standby, IRx = 1131lA

600*

IlA

Bit C6 = Low Which Selects Phase Detector B, R and R, PDout, LD = No Connect;
Din, ENB, CLK = VDD or GND, Phase Detector B Enabled
(Bit C6 = Low)

**

mA

*MCI452010NLY.
**The nominal value = 12 mAo This is not a guaranteed limit.

MC145200.MC145201
2-672

MOTOROLA COMMUNICATIONS DEVICE DATA

ANALOG CHARACTERISTICS-CURRENT SOURCE/SINK OUTPUT-PDout
(lout" 2 mA, VDD = VCC = 4.5 to 5.5 V, VDD "VpD. Voltages Referenced to GND)
Parameter

Test Condition

Maximum Source Current Variation

VPD

Guaranteed
Limit

Unit

8.0

±20

%

9.5

±20

4.5

±20

5.5

±20

8.0

12

9.5

12

MC145200: Vout = 0.5 x VpD

MC145201: Vout = 0.5 x VPD

Maximum Sink-vs-Source Mismatch (Note 3)

MC145200: Vout = 0.5 x VPD

MC145201: Vout = 0.5 x VPD

Output Voltage Range (Note 3)

MC145200: lout variation" 20%

MC145201: lout variation" 20%

4.5

12

5.5

12

8.0

0.5 to 7.5

9.5

0.5 to 9.0

4.5

0.5 to 4.0

5.5

0.5 to 5.0

%

%

%

V

V

NOTES:
1. Percentages calculated using the following formula: (Maximum Value - Minimum Value)/Maximum Value.
2. See Rx Pin Description for external resistor values.
3. This parameter is guaranteed for a given temperature within -40 to + 85°C.

AC INTERFACE CHARACTERISTICS (VDD = 4.5 to 5.5 V, TA =- 40 to + 85°C, Cl = 50 pF, Inputtr = tf= 10 ns;
MC145200: VpD = 8.0 to 9.5 V; MC145201: VpD = 4.5 to 5.5 V with VDO "VpO)
Symbol
fclk

Parameter
Serial Data Clock Frequency (Note: Refer to Clock tw below)

Figure Ills)

Guaranteed
Limit

Unit

1

dc to 4.0

MHz

tplH, tpHl

Maximum Propagation Delay, ClK to OUTPUT A (Selected as Data Out)

1,5

105

ns

tplH, tpHl

Maximum Propagation Delay, ENS to OUTPUT A (Selected as Port)

2,5

100

ns

tpZl, tpLZ

Maximum Propagation Delay, ENS to OUTPUT S

2,6

120

ns

trlH, trHl

Maximum Output Transition TIme, OUTPUT A and OUTPUT S;
trHlonly, on OUTPUT B

1,5,6

100

ns

10

pF

Figure#(s)

Guaranteed
Limit

Unit

Minimum Setup and Hold TImes, Din vs ClK

3

20

ns

Minimum Setup, Hold and Recovery TImes, ENB vs ClK

4

100

ns

tw

Minimum Pulse Width, ENB

4

*

cycles

tw

Minimum Pulse Width, ClK

1

125

ns

Maximum Input Rise and Fall TImes, ClK

1

100

IlS

Cin

Maximum Input Capacitance - Din, ENB, ClK,

TIMING REQUIREMENTS
(VDD = 4.5 to 5.5 V, TA = -40 to + 85°C, Input tr = tf = 10 ns unless otherwise indicated)
Symbol
tsu, th
tsu, th, trec

tr, tf

Parameter

*The minimum limit is 3 REFin cycles or 195 fin cycles, whichever Is greater.

SWITCHING WAVEFORMS

MOTOROLA COMMUNICATIONS DEVICE DATA

MC145200.MC145201
2-673

'---VDD
ClK
GND
OUTPUT A
OUTPUT A
(DATA OUT)
OUTPUTS

:E

Figure 2.

-VALID
VDD
50%
GND

-tsuyt

VDD

50%
-

GND

J:

tw
~'r-su

ENS

50%

)

-

h

ClK

50%

10%

Figure 1.

Din

tPZl~
)

)

PLZ

-t

th-

tw=t-

VGDNDD

-tree

-

VDD

ClK
GND

Figure 3.

Figure 4.

TEST POINT

TEST POINT
7.5kQ

DEVICE
UNDER
TEST

DEVICE
UNDER
TEST

r

+V

J

Cl'

'Includes all probe and fixture capacitance.

'tncludes all probe and fixture capacitance.

Figure 5. Test Circuit

Figure 6. Test Circuit

MC145200.MC145201
2-674

MOTOROLA COMMUNICATIONS DEVICE DATA

LOOP SPECIFICATIONS (VDD = VCC = 4.5 to 5.5 V unless otherwise indicated, TA = -40 to + 85°C)
Guaranteed
Operating Range
Symbol

Fig#

Min

Max

Unit

Vin

Input Voltage Range, lin

500 MHz,;; lin';; 2000 MHz

7

200

1500

mVp-p

Irel

Input Frequency, REFin Externally Driven In
Relerence Mode

Vln = 400 mVp-p
Vin= 1 Vp-p
R Counter set to divide ratio such that
IR ,;; 2 MHz, REF Counter set to divide ratio such that REFout';; 10 MHz

8

12
4.5'

27
27

MHz

Crystal Frequency, Crystal Mode

C1 ,;; 30 pF, C2 ,;; 30 pF, Includes
Stray Capacitance; R Counter and
REF Counter same as above

9

2

15

MHz

Output Frequency, REFout

CL=30pF

IxTAL

lout
I
tw
trLH,
trHL
Cin

Parameter

Test Condition

10,12

Operating Frequency 01 the Phase Detectors

dc

10

MHz

dc

2

MHz

Output Pulse Width, LD, CPR, and
CPV, - MC145201

IR in Phase with lV, CL = 50 pF,
VPD = 5.5 V, VDD = VCC = 5.0 V

11,12

20

100

ns

Output Transition TImes, LD, CPV, and
CPR - MC145201

CL = 50 pF, VPD = 5.5 V,
VDD = VCC = 5.0 V

11,12

-

65

ns

-

TBD
5

pF

Input Capacitance

lin
REFln

'II lower Irequency IS desired, use wave shaping or higher amplitude sinUSOidal signal.

O.OlI1Fr------,
REFin OUTPUT A

TEST
POINT

OUTPUT A
(Iv)

DEVICE
UNDER
TEST

DEVICE
UNDER
TEST
TEST
POINT

-Characteristic Impedance

Figure 8_ Test Circuit-Reference Mode

Figure 7. Test Circuit

.---.....-

TEST
POINT

......-1 REFin OUTPUT A
DEVICE
UNDER
TEST

(fR)

REFoul

Figure 9. Test Clrcuit-Crystal Mode

Figure 10. Switching Waveform

TEST POINT

OUTPUT

~r90;.:t%.::;Oo/.:::.o__t_W~~~_-_-_--:1r-~

5:/1=_

ITHL

::fL

Figure 11. Switching Waveform

MOTOROLA COMMUNICATIONS DEVICE DATA

ITLH

DEVICE
UNDER
TEST
-Includes all probe and
fixture capacitance.
Figure 12_ Test Circuit

MC145200.MC145201
2-675

PIN DESCRIPTIONS
DIGITAL INTERFACE PINS
Din
Serial Data Input (Pin 19)
The bit stream begins with the most significant bit (MSB)
and is shifted in on the low-to-high transition of ClK. The bit
pattern is 1 byte (8 bits) long to access the C or configuration
register, 2 bytes (16 bits) to access the first buffer of the A
register, or 3 bytes (24 bits) to access the A register (see Table
1). The values in the C, A, and A registers do not change during
shifting because the transfer of data to the registers is
controlled by ENB.
CAUTION
The value programmed for the N-counter must be
greater than or equal to the value of the A-counter.
The 13 least significant bits (lSBs) of the A register are
double-buffered. As indicated above, data is latched into the
first buffer on a 16-bit transfer. (The 3 MSBs are not
double-buffered and have an immediate effect after a 16-bit
trarisfer.) The second buffer of the A register contains the 13
bits for the A counter. This second buffer is loaded with the
contents of the first buffer when the A register is loaded (a
24-bit transfer). This allows presenting new values to the A,
A, and N counters simultaneously. If this is not required, then
the 16-bit transfer may be followed by pulsing ENB low with
no signal on the ClK pin. This is an alternate method of
transferring data to the second buffer of the A register (see
Figure 16).
The bit stream needs neither address nor steering bits due
to the innovative BitGrabber registers. Therefore, all bits in
the stream are available to be data for the three registers.
Aandom access of any register is provided. That is, the
registers may be accessed in any sequence. Data is retained
in the registers over a supply range of 4.5 to 5.5 V. The formats
are shown in Figures 13, 15, and 16.
Din typically switches near 50% of VDD to maximize noise
immunity. This input can be directly interfaced to CMOS
devices with outputs guaranteed to switch near rail-to-rail.
When interfacing to NMOS or TTL devices, either a level
shifter (MC74HC14A, MC14504B) or pull-up resistor of 1 kn
to 10 kn must be used. Parameters to consider when sizing
the resistor are worst-case IOl of the driving device, maximum
tolerable power consumption, and maximum data rate.
Table 1. Register Access
(MSBs are shifted in first· CO RO and AO are the LSBs)
Number
of Clocks

Accessed
Re91ster

Bit
Nomenclature

8
16
24
Other Values s 32
Values> 32

C Register
R Register
A Register
Not Allowed
See Figures
22-25

C7, C6, C5, ... , CO
R15, R14, R13, ... , RO
A23, A22, A21, ... , AO

Eight clock cycles are required to access the C register.
Sixteen clock cycles are needed for the first buffer of the A
register. Twenty-four cycles are used to access the A register.
See Table 1 and Figures 13, 15, and 16. The number of clocks
required for cascaded devices is shown in Figures 23 through
25.
ClK typically switches near 50% of VDD and has a
Schmitt-triggered input buffer. Slow ClK rise· and fall times
are allowed. See the last paragraph of Din for more
information.
CAUTION
To guarantee proper operation of the Power-On Aeset (POA) circuit, the ClK pin must be grounded or
held low during power up.
ENB
Active low Enable Input (Pin 17)
This pin is used to activate the serial interface to allow the
transfer of data to/from the device. When ENB is in an
inactive high state, shifting is inhibited and the port is held
in the initialized state. To transfer data to the device, ENB
(which must start inactive high) is taken low, a serial transfer
is made via Din and ClK, and ENB is taken back high. The
low-to-high transition on ENB transfers data to the C or A
registers and first buffer of the A register, depending on the
data stream length per Table 1.
Transitions on ENB must not be attempted while ClK is
high. This puts the device out of synchronization with the
microcontroller. Aesynchronization occurs when ENB is high
and ClK is low.
This input is also Schmitt-triggered and switches near 50%
of VDD, thereby minimizing the chance of loading erroneous
data into the registers. See the last paragraph of Din for more
information.
CAUTION
ENB must not be floated or toggled during power up.
It is preferable to hold ENB althe potential olthe VDD
pin during power up to guarantee proper operatiqn of
the POA circuit.
OUTPUT A
Configurable Digital Output (Pin 16)
OUTPUT A is selectable as fA, fV, Data Out, or Port. Bits
A22 and A23 in the A register control the selection; see Figure
15.
If A23 = A22 = high, OUTPUT A is configured as fA. This
signal is the buffered output of the 13-stage A counter. The
fA signal appears as normally low and pulses high, and can
be used to verify the divide ratio of the A counter. This ratio
extends from 5 to 8191 and is determined by the binary value
loaded into bits AO through A12 in the A register. Also, direct
access to the phase detectors via the AEFin pin is allowed
by choosing a divide value of 1 (see Figure 16). The
maximum frequency at which the phase detectors operate
is 2 MHz. Therefore, the frequency of fA should not exceed
2 MHz.
If A23 high and A22 low, OUTPUT A is configured as
fV. This signal is the buffered output of the 12-stage N counter.
The fV signal appears as normally low and pulses high, and
can be used to verify the operation of the prescaler, A counter,
and N counter. The divide ratio between the fin input and the
fV signal is N x 64 + A. N is the divide ratio of the N counter
and A is the divide ratio of the A counter. These ratios are
determined by bits loaded into the A register. See Figure 15.

=

ClK
Serial Data Clock Input (Pin 18)
low·to·high transitions on ClK shift bits available at the
Din pin, while high-to-Iow transitions shift bits from
OUTPUT A (when configured as Data Out, see Pin 16). The
24-1/2-stage shift register is static, allowing clock rates down
to dc in a continuous or intermittent mode.

MC145200.MC145201
2-676

=

MOTOAOlA COMMUNICATIONS DEVICE DATA

The maximum frequency at which the phase detectors operate
is 2 MHz. Therefore, the frequency of fV should not exceed
2 MHz.
If A23 = low and A22 = high, OUTPUT A is configured as
Data Out. This signal is the serial output of the 24-1/2-stage
shift register. The bit stream is shifted out on the high-to-low
transition of the ClK input. Upon power up, OUTPUT A is
automatically configured as Data Out to facilitate cascading
devices.
If A23 = A22 = low, OUTPUT A is configured as Port. This
signal is a general-purpose digital output which may be used
as an MCU port expander. This signal is low when the Port
bit (C1) of the C register is low, and high when the Port bit
is high.
OUTPUTB
Open-Drain Digital Output (Pin 15)
This signal is a general-purpose digital output which may
be used as an MCU port expander. This signal is low when
the Out B bit (CO) of the C register is low. When the Out B
bit is high, OUTPUT B assumes the high-impedance state.
OUTPUT B may be pulled up through an external resistor or
active circuitry to any voltage less than or equal to the potential
of the VPD pin. Note: the maximum voltage allowed on the
VPD pin is 9.5 V for the MC145200 and 5.5 V for the
MC145201.
Upon power-up, power-on reset circuitry forces OUTPUT B
to a low level.
REFERENCE PINS
REFln and REFout
Reference Input and Reference Output (Pins 20 and 1)
Configurable pins for a Crystal or an External Reference.
This pair of pins can be configured in one of two modes: the
crystal mode or the reference mode. Bits R13, R14, and R15
in the R register control the modes as shown in Figure 16.
In crystal mode, these pins form a reference oscillator when
connected toterminals of an external parallel-resonant crystal.
Frequency-setting capacitors of appropriate values as
recommended by the crystal supplier are connected from each
of the two pins to ground (up to a maximum of 30 pF each,
including stray capacitance). An external resistor of 1 MQ to
15 MQ is connected directly across the pins to ensure linear
operation of the amplifier. The device is designed to operate
with crystals up to 15 MHz; the required connections are
shown in Figure 8. To turn on the oscillator, bits R15, R14,
and R13 must have an octal value of one (001 in binary,
respectively). This is the active-crystal mode shown in
Figure 16. In this mode, the crystal oscillator runs and the R
Counter divides the crystal frequency, unless the part is in
standby. If the part is placed in standby via the C register, the
oscillator runs, but the R counter is stopped. However, if bits
R15 to R13 have a value of 0, the oscillator is stopped, which
saves additional power. This is the shut-down crystal mode
(shown in Figure 16) and can be engaged whether in standby
or not.
In the reference mode, REFin (Pin 20) accepts a signal
up to 27 MHz from an external reference oscillator, such as
a TCXO. A signal swinging from at least the Vil to VIH levels
listed in the Electrical Characteristics table may be directly
coupled to the pin. If the signal is less than this level, ac
coupling must be used as shown in Figure 8. Due to an
on-board resistor which is engaged in the reference modes,

MOTOROLA COMMUNICATIONS DEVICE DATA

an external biasing resistor tied between REFin and REFout
is not required.
With the reference mode, the REFout pin is configured
as the output of a divider. As an example, if bits R15, R14,
and R13 have an octal value of seven, the frequency at
REFout is the REFin frequency divided by 16. In addition,
Figure 16 shows how to obtain ratios of eight, four, and two.
A ratio of one-to-one can be obtained with an octal value
of three. Upon power up, a ratio of eight is automatically
initialized. The maximum frequency capability of the REFout
pin is 10 MHz. Therefore, for REFin frequencies above
10.MHz, the one-to-one ratio may not be used. Likewise, for
REFin frequencies above 20 MHz, the ratio must be more
than two.
If REFout is unused, an octal value of two should be used
for R15, R14, and R13 and the REFout pin should be floated.
A value of two allows REFin to be functional while disabling
REFout, which minimizes dynamic power consumption and
electromagnetic interference (EMI).
LOOP PINS
fin and fin
Frequency Inputs (Pins 11 and 10)
These pins are frequency inputs from the VCO. These pins
feed the on-board RF amplifier which drives the 64/65
prescaler. These inputs may be fed differentially. However,
they usually are used in a single-ended configuration (shown
in Figure 7). Note that fin is driven while fin must be tied to
ground via a capacitor.
Motorola does not recommend driving fin while terminating
fin because this configuration is not tested for sensitivity. The
sensitivity is dependent on the frequency as shown in the loop
Specifications table.
PDout
Single-Ended Phase/Freq. Detector Output (Pin 6)
This is a three-state current-source/sink output for use as
a loop error signal when combined with an external low-pass
filter. The phase/frequency detector is characterized by a
linear transfer function. The operation of the phase! frequency
detector is described below and is shown in Figure 17.
POL bit (C7) in the C register = low (see Figure 13)
Frequency of fV > fR or Phase of fV leading fR:
current-sinking pulses from high impedance
Frequency of fV < fR or Phase of fV Lagging fR:
current-sourcing pulses from high impedance
Frequency and Phase of fV = fR: essentially highimpedance state; voltage at pin determined by loop filter
POL bit (C7) high
Frequency of
> fR or Phase of fV leading fR:
current-sourcing pulses from high impedance
Frequency of fV < fR or Phase of fV lagging fR:
current-sinking pulses from high impedance
Frequency and Phase of fV
fR: essentially highimpedance state; voltage at pin determined by loop filter
This output can be enabled, disabled, and inverted via the
C register. If desired, PDout can be forced to the highimpedance state by utilization of the disable feature in the
C register (bit C6). This is a patented feature. Similarly, PDout
is forced to the high-impedance state when the device is put
into standby (STBY bit C4 high).

=
tv

=

=

MC145200.MC145201
2-677

$R and $V (Pins 3 and 4)
Double-Ended Phase/Frequency Detector Outputs
These outputs can be combined externally to generate a
loop error signal. Through use of a Motorola patented
technique, the detector's dead zone has been eliminated.
Therefore, the phaselfrequency detector is characterized by
a linear transfer function. The operation of the phaselfrequency detector is described below and is shown in Figure 17.
POL bit (C7) in the C register = low (see Figure 13)
Frequency ollV > fR or Phase ollV LeadingfR: $V= negative
pulses, $R = essentially high
Frequency of fV < fR or Phase of fV Lagging fR: $V =
essentially high, $R = negative pulses
Frequency and Phase of
= fR: $V and $R remain
essentially high, except for a small minimum time period
when both pulse low in phase
POL bit (C7) = high
FrequencyoffV>fR or PhaseoffV LeadingfR: $R = negative
pulses, $V = essentially high
Frequency of fV < fR or Phase of fV Lagging fR: $R =
essentially high, $V = negative pulses
Frequency and Phase of fV = fR: $V and $R remain
essentially high, except for a small minimum time period
when both pulse low in phase
These outputs can be enabled, disabled, and interchanged
via C register bitsC6 or C4. This is a patented feature. Note
that when disabled or in standby, $R and $V are forced to their
rest condition (high state).
The $R and $V output signal swing is approximately from
GND to VPD.

tv

LD
Lock Detector Output (Pin 2)
This output is essentially at a high level with narrow
low-going pulses when the loop is locked (fR andfvofthesame
phase and frequency). The output pulses low when fV and
fR are out of phase or different frequencies. LD is the logical
ANDing of $R and $V (see Figure 17).
This output can be enabled and disabled via the C register.
This is a patented feature. Upon power up, on-chip
initialization circuitry disables LD to a static low logic level to
prevent a false "lock" signal. If unused, LD should be disabled
and left open.
The LD output signal swing is approximately from GND to
VDD·
Rx
External Resistor (Pin 8)
A resistor tied between this pin and GND, in conjunction
with bits in the C register, determines the amount of current
that the PDout pin sinks and sources. When bits C2 and C3
are both set high, the maximum current is obtained at PDout;
see Tables 2 and 3 for other values of current. To achieve
a maximum current of 2 mA, the resistor should be about
47 kr.! when VPD is 9 V or. about 18 kr.l when VPD is 5.0 V.
See Figure 14 if lower maximum current values are desired.
When the $R and $V outputs are used, the Rx pin may be
fioated.

CAUTION
This pin is an unbuffered output and must be floated
in an actual application. This pin must be attached to
an isolated pad with no trace. There is the possibility
that the final production version of the device will
have this lead clipped at the body of the package.
TEST 2
Prescaler Output (Pin 13)
This pin may be used to access to the on-board 64/65
prescaler output.
CAUTION
This pin is an unbuffered output and must be floated
in an actual application. This pin must be attached to
an isolated pad with no trace. There is the possibility
that the final production version of the device will
have this lead clipped at the body of the package.

POWER SUPPLY PINS
VDD
Positive Power Supply (Pin 14)
This pin supplies power to the main CMOS digital portion
of the device. The voltage range is + 4.5 to + 5.5 V with
respect to the GND pin.
Foroptimumperformance, VDD should be bypassedtoGND
using a low-inductance capacitor mounted very close
to these pins. Lead lengths on the capacitor should be
minimized.
VCC
Positive Power Supply (Pin 12)
This pin supplies power to the RF amp and 64165 prescaler.
The voltage range is + 4.5 to + 5.5 V with respect to the GND
pin. In the standby mode, the VCC pin still draws a few
milliamps from the power supply. This current drain can be
eliminated with the use of transistor Q1 as shown in
Figure 21.
For optimum performance, VCC should be bypassed to
GND using a low-inductance capacitor mounted very close
to these pins. Lead lengths on the capacitor should be
minimized.
VPD
Positive Power Supply (Pin 5)
This pin supplies power to both phaselfrequency detectors
A and B. The voltage applied on this pin must be no less
than the potential applied to the VDD pin. The maximum
voltage can be +9.5 V with respect to the GND pin for the
MC145200 and +5.5 V for the MC145201.
For optimum performance, VpD should be bypassed to
GND using a low-inductance capacitor mounted very close
to these pins. Lead lengths on the capacitor should be
minimized.
GND
Ground (Pin 7)
Common ground.

TEST POINT PINS
TEST 1
Modulus Control Signal (Pin 9)
This pin may be used in conjunction with the Test 2 pin for
access to the on-board 64/65 prescaler. When Test 1 is low,
the prescaler divides by 65. When high, the prescaler divides
by 64.

MC145200.MC145201
2-678

MOTOROLA COMMUNICATIONS DEVICE DATA

ENB

l

I

CLK
MSB
Din

~

C7

LSB

~

C6

~

C5

~

C4

~

C3

~

C2

~

Cl

~

CO

~

• At this point, the new byte is transferred to the C register and stored. No other registers are affected.

C7 - POL:

Selects the output polarity of the phase/frequency detectors. When set high, this bit inverts PDout
and interchanges the $R function with $V as depicted in Figure 17. Also see the phase detector output
pin descriptions for more information. This bit is cleared low at power up.

C6 - PDAIB:

Selects which phase/frequency detector is to be used. When set high, enables the output of phase/
frequency detector A (PDout) and disables phase/frequency detector B by forcing $R and $V to the
static high state. When cleared low, phase/frequency detector B is enabled ($R and $V) and phase/frequency detector A is disabled with PDout forced to the high-impedance state. This bit is cleared low
at power up.

C5 -

LDE:

Enables the lock detector output (LD) when set high. When the bit is cleared low, the LD output is
forced to a stalic low level. This bit is cleared low at power up.

C4 - STBY:

When set, places the CMOS section of device, which is powered by the VDD and VpD pins, in the
standby mode for reduced power consumption: PDout is forced to the high-impedance state, $R and
$V are forced high, the A, N, and R counters are inhibited from counting, and the Rx current is shut
off. In standby, the state of LD is determined by bit C5. C5 low forces LD low (no change). C5 high
forces LD static high. During standby, data is retained in the A, R, and C registers. The condition
of REF/OSC circuitry is determined by the control bits in the R register: R13, R14, and R15. However,
if REFout= static low is selected, the intemal feedback resistor is disconnected and the input is inhibited
when in standby; in addition, the REFin input only presents a capacitive load. NOTE: Standby does
not affect the other modes of the REF/OSC circuitry.
When C4 is reset low, the part is taken out of standby in 2 steps. First, the REFin (only in one mode)
resistor is reconnected, all counters are enabled, and the Rx current is enabled. Any fR and fV signals
are inhibited from toggling the phaselfrequency detectors and lock detector. Second, when the first
tv pulse occurs, the R counter is jam loaded, and the phase/frequency and lock detectors are initialized.
Immediately after the jam load, the A, N, and R counters begin counting down together. At this point,
the fR and fV pulses are enabled to the phase and lock detectors. (Patented feature.)

C3, C2 -12, 11:

Controls the PDout source/sink current per Tables 2 and 3. With both bits high, the maximum current
(as set by Rx per Figure 14) is available. Also, see Cl bit description.

Cl - Port:

When the OUTPUT A pin is selected as "Port" via bits A22 and A23, Cl determines the state of OUTPUT A. When Cl is set high, OUTPUT A is forced high; Cllow forces OUTPUT A low. When OUTPUT
A is NOT selected as "Port," Cl controls whether the PDout step size is 10% or 25%. (See Tables
2 and 3.) When low, steps are 10%. When high, steps are 25%. Default is 10% steps when OUTPUT
A is selected as "Port." The Port bit is not affected by the standby mode.

CO - Out B:

Determines the state of OUTPUT B. When CO is set high, OUTPUT B is high-impedance; CO low
forces OUTPUT B low. The Out B bit is not affected by the standby mode. This bit is cleared low
at power up.

Figure 13. C Register Access and Format (8 Clock Cycles are Used)

MOTOROLA COMMUNICATIONS DEVICE DATA

MC145200.MC145201
2-679

100

\ \\

'\ \\

90

:\

80

70

ae
a:

a:

-'
«
z

w

><
w

I

I

I

I

I

I

50

40

I\.

'\

""
"

1".......

Ii

~

30

..........

~ ~ .......... ..........
r---.... ........ ......... ........
.........

--r:::

r--..

r- r-

10

0.1

0.2

0.3

0.4

0.5

I

~

20

o

I

~

a:
f-

I

PDout CURRENT SET TO 100%;
PDout VOLTAGE IS FORCED TO ONE-HALF OF VPD.

\ r\,' ~
\
~ \

60

:::?
(J)
C7.i
w

I

0.6

0.7

0.8

0.9

1.0

1.1

1.2

1.3

1.4

1.5

-

r-

MC145201

1.6

ro- r-

r-

1.7

1.8

--

1.9

2.0

VPD=5.5V VPD = 5.0 V
vpr4T -

I
2.1

I
2.2

2.3

lout. SOURCE CURRENT (rnA)
NOTE: The MC145201 is optimized for Rx values in the 18 kQ to 40 kQ range. For example. to achieve 0.3 mA of output
current. it is preferable to use a 30-kQ resistor for Rx and bit settings for 25% (as shown in Table 3).

Figure 14. Nominal Source Current for the PDout Pin

Table 2. PDout Current, C1 = Low with OUTPUT A NOT
Selected as "Port"; Also, Default Mode When
OUTPUT A Selected as "Port"
C3
0
0
1
1

MC145200.MC145201
2-680

C2
0
1
0
1

Table 3. PDout Current, C1 = High with OUTPUT A NOT
Selected as "Port"

PDout Current

C3

C2

PDout Current

70%
80%
90%
100%

0
0
1
1

0
1
0
1

25%
50%
75%
100%

MOTOROLA COMMUNICATIONS DEVICE DATA

s:::

~

~~

:D

o

>

~

t

()

o

s:::
s:::
c

NOTE 3

z

o
~
z

(5

en
o

CLK

:!!
c

'"iii

....

!l1

~

o
~
>

III

om

J:>

::u

Din

'"iii
....iil"

J:>

n
n

III
III
III
I»

0

:::I

'---.---'

3

BOTH BITS
MUST BE
HIGH

a..
"l}

a

i0

II
0

1

0"
n

;I;"

0
'<
n

iD

III
I»

iii

c:

III
CD

.s

:s:
o....

""
liS
CI

C?

:s:
o
....
N""
,UI

OIN
CD CI

........

'--.,---J

PORT
DOUT
fv
fR

0
0
0

0
0
0
0

2
3
4
5
7

NOTALLOWED
NOTALLOWED
NOTALLOWED
NOT ALLOWED
NOT ALLOWED
NCOUNTER = +5
NCOUNTER = +6
NCOUNTER =+7

'--.,---J

BINARY OUTPUT A
VALUE FUNCTION
(NOTEll

F

F

E NCOUNTER = +4094

F

F

F

~

HEXADECIMAL VALUE
FOR N COUNTER

0

0

0
0

2
3

ACOUNTER
ACOUNTER
ACOUNTER
ACOUNTER

=+0
=+ 1
=+2
=+3

3

E
F

ACOUNTER =+62
ACOUNTER = + 63

4
4

0
1

NOT ALLOWED
NOT ALLOWED

F

F

NOT ALLOWED

N COUNTER = +4095
~

HEXADECIMAL VALUE
FOR ACOUNTER

NOTES:
1. A power-on initialize circuit forces the OUTPUT A function to default to Data Out.
2. The values programmed for the N counter must be greater than or equal to the values programmed for the A counter. This results in a total divide value = N x 64 + A.
3. At this point, the three new bytes are transferred to the A register. In addition, the 13 LSBs in the first buffer of the R register are transferred to the R register's second buffer.
Thus, the R, N, and A counters can be presented new divide ratios at the same time. The first buffer of the R register is not affected. The C register is not affected.

nIt

l

ENB

t

NOTE NOTE
4
5

CLK

Din

3
4
5
6
7

L

o

CRYSTAL MODE, SHUT DOWN
CRYSTAL MODE, ACTIVE
REFERENCE MODE, REFin ENABLED and REFoul
STATIC LOW
REFERENCE MODE, REFout = REFin (BUFFERED)
REFERENCE MODE, REFout = REFinl2
REFERENCE MODE, REFout = REFinl4
REFERENCE MODE, REFout = REFinl8 (NOTE 3)
REFERENCE MODE, REFout = REFinlt6

o

o
o

o

o
o

o
o

o
t
2
3
4
5
6
7
8

NOT ALLOWED
DIRECT ACCESS TO REFERENCE SIDE OF PHASE/FREQUENCY DETECTORS
NOT ALLOWED
NOT ALLOWED
NOT ALLOWED
RCOUNTER=+5
RCOUNTER =+6
RCOUNTER=+7
RCOUNTER =+8

OCTAL VALUE
t
t
BINARY VALUE

NOTES:

F

FER COUNTER =+8190
F F RCOUNTER=+8191

--1 H~ VALUE

1.
2.
3.
4.

Bits R15 through R13 control the configurable "OSC or 4-stage divider" block (see Block Diagram).
Bits R12 through RD control the "13-stage R counter" block (see Block Diagram).
A power-on initialize circuit forces a default REFin to REFout ratio of eight.
Althis point, bits R13, R14, and R15 are stored and senlto the "OSC or 4-Stage Divider" block in the Block Diagram. Bits RD through R12 are loaded
Into the first buffer in the double-buffered section of the R register. Therefore, the R counter divide ratio is not altered yet and retains the previous
ratio loaded. The C and A registers are not affected.
5. At this point, bits RD through R12 are transferred to the second buffer of the R register. The R counter begins dividing by the new ratio aiter
completing the rest of the present count cycle. CLK must be low during the ENB pulse, as shown. Also, see note 3 of Figure 15 for an alternate
method of loading the second buffer in the R register. The C and A registers are not affected. The first buffer of the R register is not affected.

R Register Access and Format (16 Clock Cycles Are Used)

'-------in

',:
1------1:n

n

VL

*

-

SOURCING CURRENT

1--------+--- HIGH IMPEDANCE

U'

j--------1U,'
:I
I'-'--'U
" ----tU"
U
I

n-=~~

I

t

"

-

SINKING CURRENT
VH

-VL

--'--j-----'-i',

VH

-VL

Vii

r--

-VL

VH = High voltage level
VL = Low voltage level
•At this point, when both fR and tv are in phase, the output source and sink circuits are turned on for a short interval.
NOTE: The PDout either sources or sinks current during out·of-Iock conditions. When locked in phase and frequency, the output is high impedance and the voltage althat pin is determined by the low-pass filter capacitor. PDout,  in amps per radian with 1he filter's Impedance transfer function, Z(s), maintains units of volts per radian for the de1ectorl
filter combination. Additional sideband filtering can be accomplished by adding a capacitor C' across R. The corner COc = 1/RC' should be
chosen such that con Is not significantly affected.

(B)

R1

V

~ =

"'nR2C
2

R ----w'r----4.......-1
VCo

CPV ----"oIIIV--....-t

~KVCO
NCR1

"'n=

ASSUMING GAIN A IS VERY LARGE, THEN:

NOTE:
For (B), R1 is frequently split into two series resistors; each resistor is equal to Rl divided by 2. A capacitor Cc Is then placed from the
midpoint to ground to further filter the error pulses. The value of Cc should be such that the comer frequency of this network does not
significantly affect COn.
DEFINITIONS:
N = Total Division Ratio In Feedback Loop
K (Phase Detector Gain) =IpDout/2,. amps per radian for PDout
Kcp (Phase Detector Gain) =VPD/2,. volts per radian for v and R

2l!8ivco

KVCO (VCO Transfer Function) = dVVCO

radians per volt

For a nominal design starting point, the user might consider a damping factor ~=0.7 and a natural loop frequency con = (2mR/50) where
fR Is the frequency at the phase detector input. Larger COn values resuH in faster loop lock times and, for similar sideband filtering, higher
fR-related VCO sidebands.
Either loop filter (A) or (B) is frequently followed by additional sideband filtering to further attenuate fR-related VCO sidebands. This additional filtering may be active or passive.
RECOMMENDED READING:
Gardner, Floyd M., Phaselock Techniques (second edition). New York, Wiley-Interscience, 1979.
Manassewitsch, Vadim, Frequency Synthesizers: Theory and Design (second edition). New York, Wiley-Interscience, 1980.
Blanchard, Alain, Phase-Locked Loops: Application to Coherent Receiver Design. New York, Wiley-Interscience, 1976.
Egan, William F., Frequency Synthesis by Phase Lock. New York, Wlley-Intersclence, 1981.
Rohde, Ulrich L., Digital PLL Frequency Synthesizers Theory and Design. Englewood Cliffs, NJ, Prentice-Hall, 1983.
Berlin, Howard M., Design of Phase-Locked Loop Circuits, with Experiments. Indianapolis, Howard W. Sams and Co., 1978.
Kinley, Harold, The PLL Synthesizer Cookbook. Blue Ridge Summit, PA, Tab Books, 1980.
Seidman, Arthur H., Integrated Circuits Applications Handbook, Chapter 17, pp. 538-586. New York, John Wiley & Sons.
Fadrhons, Jan, "Design and Analyze PLLs on a Programmable Calculator," EDN. March 5, 1980.
AN535, Phase-Locked Loop Design Fundamentals, Motorola Semiconductor Products, Inc., 1970.
AR254, Phase-Locked Loop Design Articles, Motorola Semiconductor Products, Inc., Reprinted with permission from Electronic Design,
1987.

MOTOROLA COMMUNICATIONS DEVICE DATA

MC145200.MC145201
2·685

0

J

REFout

REFin

2 LD
OPTIONAL LOOP {
ERROR SIGNALS
(NOTE 1)

4

+V
7

8
NC

r-i
.". 1000pF

Din

ciR

CLK

---

UHF OUTPUT

BUFFER

NOTES:
1. When used, the ciR and cl>v outputs are fed to an external combineriloop filter. See the Phase-Locked
Loop - Low-Pass Filter Design page for additional information.
2. TranslstorOlls required only If the standby feature is needed. 01 permits the bipolar section of the device
to be shut down via use of the generaf-purpose digital pin, OUTPUT B. If the standby feature is not needed, tie pin 12 directly to the power supply.
3. For optimum performance, bypass the Vee, VDD, and VPD pins to GNDwilh low-inductance capacitors.
4. The R counter is programmed for a divide value = REFinflR. Typically, fR is the tuning resolution required
for the veo. Also, the veo frequency divided by fR = NT = N x 64 + A; this determines the values (N,
A) that must be programmed into the N and A counters, respectively.

Figure 21. Example Application

DEVICE #1
Din

CLK

ENB

DEVICE #2
OUTPUT A
(DATA OUT)

Din

I

f

CLK

ENB

OUTPUT A
(DATA OUT)

CMOS
MCU
OPTIONAL

Figure 22. Cascading Two Devices

MC145200.MC145201

2-686

MOTOROLA COMMUNICATIONS DEVICE DATA

;s:

a
~I

We

>

I

l

+

()

0

~I

ClK

~MM~MMJLfLMJUL*

51
z

Din

~ U 8:: ~ ~ ~ ~ :~ H U B a~: ~ H U B:~ U B

c
z
0
~

en

X

X

X

0

C7

C6

CO

X

X

X

X

X

C7

a

C6

~ :~ Uco ~

\ . )

C REGISTER BITS OF DEVICE #2
IN FIGURE 22

C REGISTER BITS OF DEVICE #1
IN FIGURE 22

v

m
S
m

()

X

,--)

v

0

»~

•At this pOint, the new bytes are transferred to the C registers of both devices and stored. No other registers are affected.

Figure 23. Accessing the C Registers of Two Cascaded Devices

r

ENBl
ClK

Din

5:

o
....

i

•
5:
o
....

1\) ....

,III

0\1\)

!!3g

~JLfU\Jtfl-J\JU1JLJUmJtFLJUU\JlfL
~ ~ xU:: ~ U B:: ~
X

A23

A22

A16

BA15 H~:

BASH

'------v-

A7

B:~ ~ ~ B:~: BAS a H:: H ~
AO

A23

~'---

A REGiSTER BITS OF DEViCE #2
IN FiGURE 22

AS

---v-

AO

~

A REGISTER BiTS OF DEViCE #1
IN FIGURE 22

•At this point, the new bytes are transferred to the A registers of both devices and stored. Additionally, for both devices, the 13 LSBs in each of the first buffers of the R registers are
transferred to the respective R register's second buffer. Thus, the R, N, and A counters can be presented new divide ratios at the same time. The first buffer of each R register is not affected •
Neither C register is affected.

Figure 24. Accessing the A Registers of Two Cascaded Devices

N5:

610
co ...
co.,..

~

i:o
....,..
en

...

~

ool.

~

+

+

Note 1 Note2

ClK

Din

~JlMs-fLfl-J\~s-fl-fLfLJLfl-JlJUL~

X

~

X

It

It

H;;

~ R1S ~ R14 ~;;
\.....

,t

HRS BR7 ~ ;;
'V

R REGISTER BITS OF DEVICE #2
IN FIGURE 22

s::

a
o

t~

BRO ~
,/

X ";;

~

t~

X "RIS

B ;J-~

z

o
~
o
z
(J)

o
~

om
o
»~

~

R7

H;;

~

RO

~

R REGISTER BITS OF DEVICE #1
IN FIGURE 22

NOTES APPLICABLE TO EACH DEVICE:
1. At this point, bits R13, R14, and R15 are stored and sentto the 'OSC or 4-Stage Divider" block in the Block Diagram. Bits ROthrough R12 are loaded into the first buffer in the doublebuffered section of the R register. Therefore, the R counter divide ratio is not altered yet and retains the previous ratio loaded. The C and A registers are not affected.
2. At this point, the bits RO through R12 are transferred to the second buffer of the R register. The R counter begins dividing by the new ratio after completing the rest of the present count
cycle. CLK must be low during the ENB pulse, as shown. Also, see note of Figure 24 for an alternate method of loading the second buffer in the R register. The C and A registers
are not affected. The first buffer of the R register is not affected.

s;;

s::
c

RS

~,/

:IJ

8s::

It

Figure 25. Accessing the R Registers of Two Cascaded Devices

MOTOROLA

-

SEMICONDUCTOR
TECHNICAL DATA

MC145402
Advance Information

Serial 13-Bit Linear Codec
(AID and D/A)

~

lr'~UU

The MC145402 is a 13~bit linear monotonic digital-to-analog and analog-todigital converter implemented in a single silicon-gate CMOS IC. Potential applications include analog interface for Digital Signal Processor (DSP) applications,
high speed modems, telephone systems, SONAR, Adaptive Differential Pulse
Code Modulation (ADPCM) converters, echo cancellers, repeaters, voice synthesizers, and music synthesizers.
•
•
•
•
•
•
•
•
•
•

LSUFFIX
CERAMIC
CASE 620

PIN ASSIGNMENT

60 dB Signal-to-(Noise Plus Distortion) Ratio Typical
On-Chip Precision Voltage Reference
Serial Data Ports
Two's Complement Coding
±5 V Supply Operation
Sample Rates from 100 Hz to 16 kHz (Both AID and D/A), 100 Hz to 21.3 kHz
(AID Only), and 100 Hz to 64 kHz (D/A Only)
.
Input Sample and Hold Provided On-Chip
5 V CMOS Inputs; Outputs Capable of Driving Two LSTTL Loads
Available in a 16-Pin DIP
Low Power Consumption: 50 mW Typical, 1 mW Power Down

VAG [ 1.

Aoul

2

Ain
POI

3

CCI

5

4

MSI

6

TOF

7

Vss

8

PVOO
PROO
14 P RCE
13 P ROC
12 P TOC
11 PTOO
10 P TOE
9 P VOG
16
15

BLOCK DIAGRAM

MSI CCI POI

MOTOROLA COMMUNICATIONS DEVICE DATA

VOO VSS

VAG

VOG

MC145402
2-689

This device contains circuitry to protect the
inputs against damage due to high static voltages
or electrical fields; however, it is advised that
normal precautions be taken to avoid applications
01 any voltage higher than maximum rated
voltages to this high impedance circuit. For proper
operation it is recommended that Vln and Vout be
constrainedtothe range VSS S (Vin orVoutl SVDD
on analog inputs/outputs and VDG S (Vin or Vout)
S VDD on digital inputs/outputs. Reliability 01
operation is enhanced il unused digital inputs are
tied to an appropriate logic voltage level (e.g.,
eitherVDG orVDD) and unused analog Inputs are
tied to VAG.

ABSOLUTE MAXIMUM RATINGS (Voltages Referenced to VSS)
Rating

Symbol

DC Supply Voltage

Value

Unit
V

VDD-VSS

-0.5 to 11

Voltage, Any Pin to VSS

V

-0.5 to VDD +0.5

V

DC Current Drain per Pin (Exclud
ing VDD, VSS)

I

10

mA

TA

-40 to +85

°c

Tstg

-85to+150

°c

Operating Temperature Range
Storage Temperature Range

RECOMMENDED OPERATING CONDITIONS
Pins

Oto 70·C
Min

25·C
Typ

Oto 70·C
Max

DC Supply Voltage

VDDtoVSS

9.5

10

10.5

V

Power Dissipation, PDI = 1

VDDtoVSS

50

80

mW

Parameter

Power Dissipation, PDI = 0

VDDto VSS
Full Cycle AID and D/A
Short Cycle AID
Short Cycle D/A

Conversion Rate

MSI

1

5

mW
kHz

-

16
21.3
64
512

kHz

4096

kHz

-

0.1
0.1
0.1

CCI

3.2

TDC,RDC

16xlMSI

-

AI,AO

-

3.27
9.5

Conversion Sequence Rate
Date Rate

-

Full Scale Analog Levels (Referenced to 600 0)

Unit

-

Vp
dBm

DIGITAL ELECTRICAL CHARACTERISTICS (VDD = 5 V, VSS = - 5 V, VAG = VDG = 0 V, TA = 0 to 70·C)
Symbol

Min

Max

Unit

High Level Input Voltage

Characteristic

VIH

3.5

-

V

Low Level Input Voltage

VIL

Input Current

lin

Input Capacitance
High Level Output Voltage
Low Level Output Voltage

-

Cin
TDD
TDD

lout=-20J!A
10ut=-1 mA

VOH

4.9
4.3

lout=-20J!A
10ut=-1 mA

VOL

-

1.5

V

±1.0

J!A

10

pF

-

V

-

0.1
0.4

V

CODER AND DECODER PERFORMANCE (VDD = 5 V ± 5%, VSS = -5 V ± 5%, VAG = VDG = 0 V,
odBmO = 1 60 Vrms -- 6 30 dBm (600 0) , TA - 0 to 70·C , MSI - TDE -- RCE -- 8 kHz TDC - RDC -- 2 048 MHz CCI -- 256 kHz)

-

-

-

Decoder (D/A)

Coder (AID)
Characteristic
Resolution
Conversion Time

Full Cycle AID and D/A
Short Cycle AID
Short Cycle D/A

Min

Typ

Max

Min

13

-

13

13

62.5
46.9

-

10,000
10,000

62.5

-

-

-

±1

-

Differential Nonlinearity
Gain Error

-0.35

Offset

-15

Idle Channel Noise, 3 kHz Low-Pass
Signal-to-Noise
(Referenced to 1.02 kHz through
a IMSI/2 Low-Pass Filter)

MC145402
2-690

3.2dBmO
OdBmO
-10dBmO
-20dBmO
-30dBmO
-40dBmO
-50dBmO

-

-

-75
61
60
57
50
40
30
20

-

15.6

-

+0.35

-0.35

+15

-

-

-20

-

-

-

-

Typ

-

-

-79
62
60
59
52
42
32
22

Max

Unit

13

Bits

10,000

-

J!s

±1

LSB

10,000

+0.35

dB

-

LSB

+20

-

mV
dBmO
dB

MOTOROLA COMMUNICATIONS DEVICE DATA

ANALOG ELECTRICAL CHARACTERISTICS (Voo = 5 V ± 5%, VSS = -5 V ± 5%, VAG = VOG = 0 V,

o dBmO = 1.60 Vrms = 6.30 dBm (600 n), TA = 0 to 70'C, MSI = TOE = RCE = 8 kHz, TOC = ROC = 2.048 MHz, CCI = 256 kHz)
Pin

Symbol

Min

Typ

Max

Input Current

AI

lin

-

0.Q1

±1

jJ.A

AC Input Impedance

AI

Zin

0.5

-

Mn

input Capacitance

AI

Cin

-

15

pF

Output Voltage Range

AO

Vout

-3.4

-

3.4

V

Power Supply Rejection Ratio
(100 mV RMS on VOO orVSS, 0-50 kHz)

AO, TOO

PSRR

-

40

-

dB

Crosstalk, Ain to Aout and ROD to TOO referenced to 0 dBmO @ 1.02 kHz

AO, TOO

-

-

-90

-75

dB

Characteristic

Unit

Slew Rate

AO

SR

1.5

3

-

V/jJ.s

Settling Time (Full Scale)

AO

tsettle

-

8

-

(!S

SWITCHING CHARACTERISTICS
(VOO = + 5 V± 5%, VSS =-5 V± 5%, VAG = VOG = 0 V, TA = 0 to 70'C, CL =50 pF, See Figure 1)
Symbol

Min

Max

Unit

Input Rise Time

RCE, ROC, TOC, TOE, CCI, MSI

tr

-

100

ns

Input Fall Time

RCE, ROC, TOC, TOE, CCI, MSI

tf

-

100

ns

Output Rise Time

TOO

tr

80

ns

Output Fall Time

TOO

tf

-

80

ns

Characteristic

Pulse Width High

ROC, MSI, CCI, TOC, RCE

twH

100

Pulse Width Low

TOE, MSI, TOC, RCE, ROC

twL

100

CCI Pulse Width Low

twL

500

-

MSI Clock Frequency

fMSI

0.1

64

CCI Clock Frequency

ns
ns
ns
kHz

fCCI

3.2

512

kHz

TOC and ROC Clock Frequency

fOC

16xfMSI

4.1

MHz

TOC Rising Edge to TOO Data Valid During TOE High

tpl

ns

tp2

-

150

TOE Rising Edge to TOO Data Valid During TOC High

150

ns

TOE Rising Edge to TOO Low-Impedance Propagation Delay

tp3

0

100

ns

TOE Falling Edge to TOO High-Impedance Propagation Delay

tp4

-

40

ns

TOE Rising Edge to TOC Falling Edge Setup Time

tsul
tsu2

20
100

ROC Bit 0 Falling Edge to Last CCI Falling Edge Prior to MSI

tsu3

20

MSI Rising Edge to CCI Falling Edge Setup Time

tsu4
tsu5

20
100

Last CCI Rising Edge (Prior to MSI) to TOE Rising Edge

tsu6

100

Last CCI Rising Edge (Prior to MSI) to First TOC Rising Edge

tsu6'

100

First TOC Falling Edge to Last CCI Rising Edge Prior to MSI

tsu7

0

RCE Rising Edge to ROC Falling Edge Setup Time

tsu8
tsu9

20
100

ROD Valid to ROC Falling Edge Setup Time

lsul0

60

th

100

ROD Hold Time from ROC Falling Edge

MOTOROLA COMMUNICATIONS DEVICE DATA

-

ns
ns
ns
ns
ns
ns
ns
ns
ns

MC145402
2-691

Isu6 - - - . t

TOE

TOC
Isu7

TOO

MSI

CCI

CCI

LAST

RCE

\\.._ __

ROC

~_B_11__~~~___B_1__~X

ROD

BO

x:=

Figure 1. AC Timing Diagram

PIN DESCRIPTIONS
VDD
Positive Supply (Pin 16)
The most positive power supply, typically + 5 V in split power supply configurations or +10 V in single supply systems.
VSS
Negative Supply (Pin 8)
The most negative power supply, typically -5 V in split
power supply configurations or 0 V in single supply systems.
VAG
Analog Ground (Pin 1)
This is the analog signal reference point. This pin is normally tied to 0 V in split supply operation or VD0/2 in single supply
systems.
VDG
Digital Ground (Pin 9)
This is the ground reference for all of the digital input and
output pins. CMOS compatible logic Signals swing from VDG
to VDD where VDG can be established anywhere from VDD
-4.75 V to VSS.

MC145402
2-692

Aout
Analog Output (Pin 2)
This is the output of the decoder's sample and hold circuit
and is a 100% duty cycle analog output of the last digital word
received and decoded by the decoder. Aout is updated approximately 60 ns after the rising edge of the last CCI prior
to MSI (see Figure 2). Aout is capable of driving a 10 kn,
50pF load.
Ain
Analog Input (Pin 3)
This is the high·impedance input to the coder. An AID cycle
begins on the first falling edge of CCI following the rising edge
of MSI. Ain is sampled approximately 50 ns after the rising
edge of CCI prior to the start of the AID cycle.
PDI
Power-Down Input (Pin 4) .
In normal operation this Input should be tied high. A logic
low on this input puts the device into a minimum power dissipation mode. During power-down, all functions stop. Two
complete MSI conversion cycles are required to establish
normal operation after leaving the power-down mode.

MOTOROLA COMMUNICATIONS DEVICE DATA

CCI
Convert Clock Input (Pin 5)
This input controls the complete conversion sequence during one MSI cycle and must receive a clock which is 32 times
the frequency of MSI. The only exception to 32 times the frequency of MSI is during short-cycle operation. See General
Modes of Operation section. CCI must be synchronous and
approximately rising edge aligned with MSI.
MSI
Master Sync Input (Pin 6)
This pin determines the conversion rate for both the coder
and the decoder. One AID and D/A conversion takes place
during each period of the digital clock applied to this input
(except in short-cycle operation, see General Modes of
Operation section). MSI must be synchronous and approximately rising edge aligned with CCI.
TDC
Transmit Data Clock (Pin 12)
Digital data from the coder is serially transmitted from TDD
on rising TDC edges wheneverTDE is a logic high. TDC must
be approximately rising edge aligned with TDE. Generally, if
TDC is low when TDE rises, the first rising edge of TDC
clocks the first data bit. If TDC is high when TDE rises, the
first bit will be clocked by TDE and the first rising edge of TDC
after TDE rises will clock out the second data bit.
TOE
Transmit Data Enable (Pin 10)
This pin is used to initiate the serial transfer of data from
the coder and provides three-state control of the TDD pin.
The rising edge of TDE (or TDC if it follows TDE) signals
the start of data transfer from the TDD pin. A resulting high
logic level on TDE also releases TDD from its high-impedance state. TDE must remain high throughout the data
transfer to keep TDD in the low-impedance state and must
return to a low state prior to each data transfer. If n:iE remains high for more than 16 rDC clocks, the 16 bits of TDD
data will be recirculated. (Note: The AID cycle begins on the
first falling edge of CCI after the rising edge of MSI. The
internal transmit latch is updated one and one half CCI periods prior to the start of the AID cycle. A pulse generated
by the logical AND of TDE and the first TDC transfers data
to the transmit shift register, and this pulse must not occur
when the transmit latch is updated. See Figure 2 and see
tsu6, tsu6', and tsu7 of Figure 1.
TOO
Transmit Digital Data (Pin 11)
This is the three-state output data pin from the coder and
is controlled by the TDE and TDC pins. TDD is in the high-impedance state whenever TDE is a logic low. The first data
bit is output from TDD on the rising edge of TDE (or TDC if
it follows TDE) and each subsequent bit is output on rising
edges of TDC. Two output data formats are available as described in the TDF pin description below.
TDF
Transmit Data Format (Pin 7)
The 13-bit digital output of the coder is available in one of
two 16-bit two's complement formats as determined by the
state of this pin. A logic 0 at this pin causes the data from
TDD to be in a 16-bit sign-extended format as follows:
SSSSM ... L where S, M, and L represent the sign, most significant bit, and the least significant bit, respectively. A logic

MOTOROLA COMMUNICATIONS DEVICE DATA

1 on this pin formats the data as follows: SM ... LSSS (see
Figure 3). RDD data is not affected by the state of this pin
and if a "digital loopback" is needed (TDD data looped back
into RDD), this pin should be high.
ROC
Receive Data Clock (Pin 13)
Receive digital data is accepted by the decoder on the first
13 falling edges of RDCafter an RCE rising edge.
RCE
Receive Clock Enable (Pin 14)
This pin identifies the beginning of a date transfer into the
RDD pin of the decoder. The first 13 falling edges of RDC
after an RCE rising edge will clock data into the decoder data
input, RDD. RCE must return low prior to each data transfer.
Since receive data is latched into the receive latch on the last
CCI falling edge prior to MSI, date transfers may not span
this falling edge of CCI without loss of data.
ROD
Receive Digital Data (Pin 15)
This pin is the data input to the decoder and is controlled
by the RDC and RCE pins described above. Two's complement data are loaded in the following sequence: SM ... L
where S, M, and L represent the sign, most significant bit,
and the least significant bit, respectively. Only the first 13 bits
clocked by RDC after RCE rises will be accepted for decoding. Any additional bits will be ignored (see Figure 3).

GENERAL INFORMATION
GENERAL MODES OF OPERATION
The MC145402 has three modes of operation; a "full" cycle
mode and two "short" cycle modes. The full cycle mode allows
simultaneous analog-to-digital (AID) and digital-to-analog
(D/A) operation. The short cycle modes allow either AID only
or D/A only operation. Two MSI cycles are required for the
MC145402 to detect which operating mode has been
selected. See Figure 2 for full versus short cycle clocking.
Full Cycle Operation
When operating in the full cycle mode, the MC145402
performs a 13-bit AID conversion followed by a 13-bit D/A conversion. Full cycle operation is selected by using a CCI
frequency that is 32 times the frequency of MSI. MSI is the
sample rate frequency.
Short Cycle Analog to Digital Operation
If CCI is 24 times the frequency of MSI, short cycle analog
to digital operation is selected. This allows a 13-bit AID
conversion only. In this mode, the D/A is not operational and
any data applied to the RDD input is ignored.
Short Cycle Digital to Analog Operation
Short cycle digital to analog operation is selected by using
a CCI clock frequency that is eight times the MSI sample rate.
During short cycle D/A operation, AID operation is disabled
and digital data read from TDD is not valid.
CLOCKING RECOMMENDATIONS
For optimum differential nonlinearity performance, all data
transitions on TDD and RDD should be limited to the first four
CCI cycles following the rising edge of MSI. This may be
achieved by setting MSI TDE RCE having a duration of
16 data clock cycles, and TDC = RDC ;;:: 4 x CCI clock
frequency. Figure 6 shows acircuitthat generates this clocking
configuration; see Application Circuits section.

=

=

MC145402
2-693

SIGNAL TO DISTORTION RATIO
Figures 4 and 5 show graphs of typical signal to distortion
ratios versus signal level for the MC145402. The presented
data is referenced to a 1020 Hz input sinusoidal frequency
with signal levels referenced to 600 0 and transmission level
point adjusted (e.g., 0 dBmO at 600 0 with a TLP of 6.30 dB
is 4.53 V peak~to-peak). For comparison, ideal signal to noise
ratios for 9-, 10-, 11-, 12-, and 13-bit AID and D/A converters
are also shown. The equation used for an ideal RMS to RMS
signal to distortion ratio is:
SID = N x 6 dB + 1.76 dB
where N is the number of bits of resolution, 6 dB per bit,
and 1.76 =20log (-./31..[2).
(-./31..[2) is approximately the RMS to RMS ratio of a sine
wave to white noise.
The signal to noise plus distortion ratio is measured through
a brickwall low-pass filter set to the Nyquist frequency of the
AID and D/A sample rate. For an 8 kHz sample rate, the
low-pass filter is set to block all signals above 4 kHz.
APPLICATION CIRCUITS
Figure 6 shows a typical circuit for generating the clock
frequencies for the MC145402. This circuit uses an
MC74HC4040 and a 2.048 MHz crystal to generate the
256 kHz frequency for internal sequencing, 1.024 MHz for the
date clocks, and an 8 kHz sample frequency. A 4.096 MHz
crystal could be used for a sample rate of 16 kHz.
Figure 7 shows the MC145402 interfaced to the DSP56000
digital signal processor. The DSP56000 can internally
generate the clocks for the MC145402 using the SSI serial
interface. SCK provides the sequencing and data clocks
(non-gated continuous dock) and SC2 (setup as the. Frame
Sync Out, FSL =0) provides the sample rate and data enables
for the MC145402. The divlde-by-four circuit to generate the
CCI clock is recommended for optimum MC145402 performance, and allows the DSP56000 to clock data in and out of
the MC145402 quickly, leaving time available for processing
by the DSP before another sample is available. SCO and SC1
could be used to gate the enables to select up to four devices
on the SSI bus.

TELEPHONE SYSTEM TRANSMISSION LEVEL
POINT FOR A LINEAR AID OR D/A CONVERTER
REFERENCED TO MU-LAW COMPANDING
Mu-Iaw companding, as specified by AT&T and CCITI,
requires 8159 quantization levels to implement both AID and
D/A conversion schemes. This is to be mirrored about signal
ground for the negative part of the wave form.
To implement a 13-bit (± 12-bit) linear converter scheme
requires 8192 quantization levels mirrored about signal
ground. To specify this converter such that it can be used to
interface with, or as an alternative to, telephony based Mu-Iaw
applications, the following is an explanation of the gain
translation.
A 13-bit linear converter scheme has 8192 quantization
levels. The goal is to be able to convert between these two
encoding schemes with minimal distortion. This dictates
setting the LSBs to the same level. For this to be achieved
requires the reference voltage of the linear converter to be
819218159 times the reference voltage of the Mu-Iaw
converter. The peak amplitude of a Mu-Iaw converter is 3.17
dBmO. The peak level olthe linearconverterwill be 8192/8159
times the peak level of the Mu-Iaw converter, which is
819218159 x 3.17 dBmO. However, you cannot multiply a gain
factor by a dBm value without using common term units and
math (i.e., we must convert this gain factor to a dB equivalent),
which is:
2010910 (819218159) = 0.03 dB

With the gain factor in dB, we can add it to the Mu-Iaw peak
level:
3.17 dBmO + 0.03 dB = 3.20 dBmO

Therefore, the linear converter peak level is 3.20 dBmO.
This is another way of saying the 0 dBmO level for the linear
converter is 3.20 dB below the maximum amplitude.
To determine the absolute 0 dBmO level for the linear
converter from the peak level, we calculate the peak level in
dBm by:
3.27 VpK 112)21 (600 0)
10log10

1 mW

= 9.50dBm (600 0)

and 3.20 dB below this level is the 0 dBmO absolute
amplitude, which is
9.50 dBm - 3.20 dB = 6.30 dBm (600 0)

Therefore, the calibration level, or transmission level point
(TLP), for this part is 6.30 dBm (600 0), which is 1.6 Vrms
based on the reference voltage of 3.27 V.

MC145402
2-694

MOTOROLA COMMUNICATIONS DEVICE DATA

;!:

0

d
0
s;:

FULL CYCLE AID-IlIA 1

:u

8

24

16

32

I

0

0

;!:
;!:

MSI

c
z
5

~

0

z
en

CCI

0

~

0

m

0

»~

AO UPDATED AND
TOD DATA TRANSFERRED INTO
THE TRANSMIT LATCH

AI SAMPLED

!!
ID
c

iii

!"

..
:::::
0

SHORT CYCLE AID ONLY

-"

I«

AID CONVERSION

en

~

MSI

"II

~
DI
:::I

a.

en

CCI

:::I"

!

AI SAMPLED

j

TOD DATA TRANSFERRED
INTO THE TRANSMIT LATCH

:t
3
S'

ID

MSI

CCI

3:

...

o

1\)"

,UI

m§

AOUPDATED

RDD DATA LATCHED INTO
THE RECEIVE LATCH

.1.

RDD DATA LATCHED INTO
THE RECEIVE LATCH
AID CONVERSION

I

•

Figure 3. MC145402 Digital Data Timing

MC145402

2-696

MOTOROLA COMMUNICATIONS DEVICE DATA

80

iD

70

~

Z

0

~

::2

en
15

13·BIT
COMPARED TO 9-13 BIT IDEAL AID; MSI = 8 kHz;
MEASURED THROUGH ALOW·PASS FILTER
WITH A BANDWIDTH OFfMSV2

12·BIT
II·BIT
10·BIT

60

9·BIT
50

+
w

en
5
~
en
:::;
a:

40

::2

30

en
'"

20

;;!
z

en
:::;
a:

10

-50

-40

-30

-20

-10

10

INPUT LEVEL (dBmO)
(1020 Hz REFERENCED TO 600n)

Figure 4. MC145402 Encoder (AID) Signal to Noise Plus Distortion Ratio

80
iD

70

~

13·BIT
r;:==~====~==~====~--lr--~~~
COMPARED TO 9-13 BIT IDEAL D/A; MSI = 8 kHz;
MEASURED THROUGH A LOW·PASS FILTER
WITH A BANDWIDTH OFfMSI/2

12.BIT

I---+---,,,e:..---,,j.£---'='-J
II·BIT

~

60 1-====t====+===l===~"""7"L-J.L__?:A~:...1Jl0l:!.BillITr.t

~
15

50

~

9·BIT
~--~---+---I-"e:..---,~~"e:..-+~~~F---~

+
w

en
5
~
en
:::;
a:

40 ~--~---+~~~~-7~~~-~---I---~

::2

;;!

z

'"enen

20

~L--z~~L-~~-~I---~---+---I---~

10

~~~~~~~---I---~---+---I---~

:::;

a:

o-60
~--~~--~----~----~----~----~--~
-50
-40
-30
-20
-10
10
INPUT LEVEL (dBmO)
(1020 Hz REFERENCED TO 600n)

Figure 5. MC145402 Decoder (D/A) Signal to Noise Plus Distortion Ratio

MOTOROLA COMMUNICATIONS DEVICE DATA

MC145402
2-697

I\.)S:
0,0
10 ...

CD"",

U1

"'o"

I\.)

SERIAL
DATA
OUT

SERIAL
DATA
IN

MC74HC4040
MC145402

01

+5 V ~ VCC
"TI

..c"
c
iil
~

02

13

2.04SMHz

14

D~

04

06b
07

~:0

o
s;:
()
o
s:
s:
c
z

(5

~

oz
(JJ

o
<

m
(5

m

o
~

>

i

0"

13·BIT
DIA

0
I"
Aout 1

13-BIT
AID

Ain loll

ANALOG
VOLTAGE
OUT

~

RCE

TDF

1

TDD
TDC

OS

15MQ

~

3..c"
c

RDC

05

U1

s:

RDD

MC74HCU04

;;:

g

15

03 6

~
"0
5"
!!!.

..,.~

1.024
MHz

8kHz

09

T~'i J~~

010

"-r1~O

1.

011
012

+5V

CCI
CONTROL

MC74HCU04AND MC74HC11
POWER CONNECTIONS
VCC, PIN 14=+5 V
GND, PIN7=OV

,r

VSSlo
Iv

T

-5V

VDG

PDt

•

VAG

11

0

VDD ~----~'I-- +5 V
MIS

R

:::I

TDE

1/3
MC74HC11
256 kHz

ANALOG
VOLTAGE
IN

•

•

OV

128 'sample

+5V

32 'sample 'sample

1/2 MC74HC74

+5V

+5V
1/2 MC74HC73

VCC

0

Q

ClK

RQ

K

Q
ClK _
Q

DSP56000

VOO
256
kHz

R

1.024
MHz

SCK

POI
CCI
TOC
MC145402

Yin

RCE

Aout

Vout

TOE

+5V
SC2

Ain

ROC

ClK

Q

1/2 MC74HC74

K

MSI

Q

1/2 MC74HC73

TOF

8kHz
VAG

VSS

SRO

TOO

STD

ROD

VSS

VOG

-5V

Figure 7. The MC145402, 13-Bit Linear Codec, Interfaced to a Motorola DSP56000, Digital Signal Processor, SSI Port

MOTOROLA COMMUNICATIONS DEVICE DATA

MC145402
2-699

MOTOROLA

-

SEMICONDUCTOR
TECHNICAL DATA

Drivers/Receivers
EIA-232-E and CCITT V.28
These devices are silicon gate CMOS ICs that combine both the transmitter
and receiver to fulfill the electrical specifications of EIA Standard 232-E and CCITT
V.28. The drivers feature true TTL input compatibility, slew rate limiting outputs,
300-0 power-off source impedance, and output typically switching to within 25%
of the supply rails. The receivers can handle up to ±25 V while presenting 3 to
7 kO impedance. Hysteresis in the receivers aid in the reception of noisy signals.
By combining both drivers and receivers in a single CMOS chip, these devices
provide effiCient, low-power solutions for both EIA-232-E and V.28 applications.
These devices offer the following performance features:
Drivers
•
•
•
•
•

±5 to ±12 V Supply Range
300-0 Power-Off Source Impedance
Output Current Limiting
TTL and CMOS Compatible Inputs
Driver Slew Rate Range Limited to 30 Vlv.s Maximum

Receivers
•
•
•
•

±25 V Input Range
3 to 7 kQ Input Impedance
0.8 V of Hysteresis for Enhanced Noise Immunity
TTL and CMOS Compatible Outputs

Available Driver/Receiver Combinations
Device

Drivers

Receivers

Figure

No. of Pins

MC145403

3

5

1

20

MC145404

4

4

2

20

MC145405

5

3

3

20

MC14540B

5

5

4

24

MC145403
MC145404
MC145405
MC145408

ro_
.-

PSUFFIX
PLASTIC
CASE73B

PSUFFIX
PLASTIC
CASE 724

~

DWSUFFIX
SO
CASE751D

2441J;

DWSUFFIX
SO
CASE 751E

Alternative EIA-232 devices to consider are:
Three Supply
MC145406 (3x3)

Single Supply
MC145407 (3x3)
MC145705 (2x3) with Power Down
MC145706 (3x2) with Power Down
MC145707 (3x3) with Power Down

ORDERING INFORMATION
MC145403P
MC145404P
MC145405P
MC14540BP

}

MC145403DW }
MC145404DW
MC145405DW
MC14540BDW

MC145403.MC145404.MC145405.MC145408
2-700

Plastic DIP

SO Package

MOTOROLA COMMUNICATIONS DEVICE DATA

PIN ASSIGNMENTS
(DIP and SO)

VOO

Vee

Rxl

001

20 Vee

VOO

Vee

VOO

Vee

Txl

011

Rxl

001

Rxl

001

Rxl

001

Rx2

002

Txl

011

Txl

011

Txl

011

Tx2

012

Rx2

002

Rx2

002

Tx2

012

Rx3

003

Rx3

003

Tx2

012

Rx2

002

Tx3

013

Tx2

012

Rx3

003

Tx3

013

Rx4

004

Rx4

004

Tx3

013

Tx4

014

Tx4

014

RxS

005

Rx4

004

Rx3

003

RxS

005

Tx3

013

Tx4

014

TxS

015

Tx5

015

Vss

VSS

GNO

Vss

GNO

VSS

GNO

MC145403
3 Drivers/5 Receivers

MC145404
4 Drivers/4 Receivers

VOO 1 •

MC145405
5 Drivers/3 Receivers

MC145408
5 Drivers/5 Receivers

FUNCTIONAL DIAGRAM

RECEIVER

DRIVER

Vee

VOO
15kn
Rxo-~--~~--+-~

5.4kn

MOTOROLA COMMUNICATIONS DEVICE DATA

00

01

MC145403.MC145404.MC145405.MC145408
2-701

ABSOLUTE MAXIMUM RATINGS (Voltages referenced to GNO, except where noled)
Symbol

Value

Unit

DC Supply Voltage (VOO ~ Vcc)

VOO
VSS
Vcc

-0.510 + 13.5
+ 0.5 10-13.5
-0.5 to +6.0

V

Input Voltage Range

VIR

Rating

Rxl-Rxn
Oil-Din

V
VSS-15toVOO+15
0.5IoVCC+15

DC Current Drain per Pin

I

±OO

rnA

Power Dissipation

Po

1

W

Operating Temperature Range

TA

-40 to +85

°C

Tstg

-8510 + 150

°c

Storage Temperature Range

This device contains circuitry 10 protect the inpuIs and outputs against damage due to high statIc voltages or electric fields; however, It Is advised
that normal precautions be taken to avoid applications of any voltage higher than maximum rated
voltages to this high Impedance circuit.
For proper operation it is recommended that
Vout and Vln be constrained to the ranges described as follows:
Digital 110: Driver Inputs (01):
(GNO :$ VOl :$ VCC)·
Receiver Outputs (~O):
(GNO :$ VOO :$ Vcc).
EIA-232 1/0: Driver Outputs (Tx):
(VSS :$ VTxl-Txn :$ VOO)·
Receiver Inputs (Rx):
VSS-15V:$VRxl-Rxn :$VOO+15V).
Reliability of operation Is enhanced if unused
outputs are tied 011 10 an appropriate logic voltage
level (e.g., either GNO or VCC for 01, and GNO for
Rx).

DC ELECTRICAL CHARACTERISTICS (All polarities referenced to GNO = 0 V, TA = - 40 to + 85°C)
Parameter
DC Supply Voltage

Quiescent Supply Current (Outputs Unloaded, Inputs Low)

VOO=+12V
VSS=-12V
VCC=+5V

Symbol

Min

Typ

Max

Unit

VOO
VSS
VCC

4.5
-4.5
4.5

5to 12
-510-12
5

13.2
-13.2
5.5

V

-

425
-400
110

635
-600
200

I1A

100
ISS
ICC

RECEIVER ELECTRICAL SPECIFICATIONS
(Voltage polarities referenced to GNO = 0 V, VOO = +12 V, VSS =-12 V, TA=-401o + 85°C, Vce =+5 V, ±5%)
Symbol

Min

Typ

Max

Unit

Input Tum-on Threshold
VOO = VOL

Rxl-Rxn

Von

1.35

1.8

2.35

V

Input Turn-oil Threshold
VOO=VOH

Rxl-Rxn

Voll

0.75

1

1.25

V

Vhys

0.6

0.8

-

V

Rin

3

5.4

7

kO
V

Characteristic

Input Threshold Hysteresis
d=Von-VolI
Input Resistance
(VSS -15 V):$ V Rxl-Rxn:$ (VOO + 15 V)
High Level Output Voltage
VRx = -3 to -25 V' (DOl-DOn)

lout = - 20 I1A
lout=-1.0rnA

VOH

4.9
3.8

4.9
4.3

-

Low Level Output Voltage
VRx = +3to+25 V' (DOl-DOn)

lout=+2rnA
lout=+4rnA

VOL

-

0.02
0.5

0.5
0.7

V

*This is the range of input voltages as specified by EIA-232-E to cause a receiver 10 be In the high or low.

MC145403.MC145404.MC145405.MC145408
2-702

MOTOROLA COMMUNICATIONS DEVICE DATA

DRIVER ELECTRICAL SPECIFICATIONS
(Voltage Polarities Referenced to Gnd = 0 V, Vdd = +12 V, Vss =-12 V, Ta =-40to + 85°C, Vcc = +5 V, ±5%)
Characteristic
Olgitallnput Voltage
Logic 0
Logic 1

011-01n

Input Current
VOI=GNO

011-01n

Symbol

Min

VIL
VIH

-

VOI=VCC
Tx1-Txn

Output Low Voltage"
VOl = Logic 1, RL = 3 kQ
VOO = + 5.0 V, VSS = -5.0 V

Tx1-Txn

-

0.8

2

-

7

-

-

Unit

-

-

V
3.5
4.3
9.2

3.9
4.7
9.5

-

VOL

Input Current
(Figure 5)

Tx1-Txn

Zoff

Output Short Circuit Current

Tx1-Txn

ISC

VOO=+12V, VSS=-12V

V
-4
-4.5
-10

-4.3
-5.2
-10.3

-

300

-

-

Q

rnA

-

Tx Shorted to GNO""
Tx Shorted to ±15 V"""

jlA

±1.0

VOH

VOO=+6.0V, VSS=-6.0V
VOO=+12.0V, VSS=-12.0V

"

Max

V

IlL
IIH

Output High Voltage
VOl = Logic 0, RL = 3 kQ
VOO = +5.0 V, VSS = -5.0 V
VOO = + 6.0 V, VSS = -6.0 V
VOO = +12.0 V, VSS =-12.0V

Typ

-

±22
±60

±60
±100

Voltage specifications are in terms of absolute values.
Specification is for one Tx output pin to be shorted at a time. Should all three driver outputs be shorted simultaneously, device power
dissipation limits will be exceeded.
This condition could exceed package limitations.

SWITCHING CHARACTERISTICS
(VCC = +5 V, ±5%, VDD = + 12 V, VSS = -12 V, TA = -40 to + 85°C; See Figures 2 and 3)

Drivers
Characteristic
Propagation Oelay lime Tx
Low-to-High
RL = 3 kQ, CL= 50 pF

Symbol

Min

Typ

Max

Unit
ns

tpLH

Hlgh-te-Low
RL=3kQ,CL=50pF

-

500

1000

-

700

1000

tpHL

Output Slew Rate
Minimum Load
RL = 7 kQ, CL = 0 pF (VOO = 6 to 12 V, VSS =-6 to-12 V)

SR

Maximum Load
RL = 3 kQ, CL = 2.5 pF (VOO = 6to 12 V, VSS =-610-12 V)

Vljls

-

±6

±30

4

-

-

Min

Typ

Max

360

610

Receivers (Cl =50 pF)
Characteristic
Propagation Oelay lime
Low-to-High

Symbol
tPLH

High-Io-Low

tPHL

Outpul Rise lime

Ir

Outpul Fall Time

If

MOTOROLA COMMUNICATIONS DEVICE DATA

-

Unit
ns

130

610

250

400

ns

40

100

ns

MC145403.MC145404.MC145405.MC14540B
2-703

PIN DESCRIPTIONS

22
20

18
16

VCC
Digital Power Supply
The digital supply pin, which is connected to the logic power
supply (+5.5 V maximum).

Txl
012

Tx2

013

Tx3

014

Tx4

14

Vln=±2V

GND
Ground
Ground retum pin is typically connected to the signal ground
pin of the EIA-232-E connector (Pin 7) as well as to the logic
power supply ground.

7

11

VDD
Most Positive Device Pin
The most positive power supply pin, which is typically + 5 to
+12V.

Vin
Rout=T

=

VSS
Most Negative Device Pin
The most negative power supply pin, which is typically-5
to-12V.

Figure 1. Power Off Source Resistance
Illustrated for MC14540B

DRIVERS
01

'-----OV
VOH

Tx

D01-DOn
Data Output Pins
These are the receiver digital output pins which swing from
VCC to GND. Each output pin is capable of driving one LSTTL
input load.

RECEIVERS

Rx --1'50%

DI1-Dln
Data Input Pins
These are the high impedance digital input pins to the drivers. Input voltage levels on these pins are LSTTL compatible
and must be between VCC and GND. A weak pull-up on each
input sets all unused 01 pins to VCC, causing the corresponding unused driver outputs to be at VSS.

DO

If

Figure 2. Switching Characteristics

,-.

Tx

l

+3V
~
-3V

4-

Rx1-Rxn
Receive Data Input Pins
These are the EIA-232-E receive signal inputs. A voltage
between + 3 and + 25 V is decoded as a space, and causes the
corresponding DO pin to swing to ground (0 V). A voltage between -3 and -25 V is decoded as a mark, and causes the
corresponding DO pin to swing to Vcc.

tsHL

SLEW RATE =

+3V
-3V

F~ts~LH-

Tx1-TXn
Transmit Data Output Pins
These are the EIA-232-E transmit signal output pins, which
swing from VDD to VSS. A logic 1 althe 01 input causes the corresponding Tx output to swing to VSS. A logic 0 at the 01 input
causes the corresponding Tx out to swing to VDD. The actual
levels and slew rate achieved will depend on the output loading (RL II CLl.

6V

tSLHORtsHL

Figure 3. Slew Rate Characteristics

MC145403.MC145404.MC145405.MC145408
2-704

MOTOROLA COMMUNICATIONS DEVICE DATA

If by design, neither of the above conditions are allowed
to exist, then the diodes D1 and D2 are not required.

APPLICATION INFORMATION
POWER SUPPLY CONSIDERATIONS
Figure 4 shows a technique to guard against excessive
device current.
The diode D1 prevents excessive current from flowing
through an internal diode from the VCC pin to the VDD pin
when VDD < VCC by approximately 0.6 V or greater. This high
current condition can exist for a short period of time during
power up/down. Additionally, if the + 12 V supply is switched
off while the + 5 V is on and the off supply is a low impedance
to ground, the diode D1 will prevent current flow through the
internal diode.
The diode D2 is used as a voltage clamp, to prevent VSS
from drifting positive to VCC, in the event that power is
removed from VSS (Pin 12). If VSS power is removed, and
the impedance from the VSS pin to ground is greater than
approximately 3 kn, this pin will be pulled to VCC by internal
circuitry causing excessive current in the VCC pin.

ESD PROTECTION
ESD protection on IC devices that have their pins
accessible to the outside world is essential. High static
voltages applied to the pins when someone touches them
either directly or indirectly can cause damage to gate oxides
and transistor junctions by coupling a portion of the energy
from the I/O pin to the power supply buses of the IC. This
coupling will usually occur through the internal ESD
protection diodes. The key to protecting the IC is to shunt as
much of the energy to ground as possible before it enters the
IC. Figure 4 shows a technique which will clamp .the ESD
voltage at approximately ±15 V using the MMVZ15VDLT1.
Any residual voltage which appears on the supply pins is
shunted to ground through the capacitors C1-C3. This
scheme has provided protection to the interface part up to
± 10 kV, using the human body model test.

+12V

1

7. 7. : ~ '. ~ 7. 7. 7.
~

.~

,.~

~. ~

7. ~ . ~
.~

f

01
C1

7

+5V

1N4001
Voo

1

...

1

24 Vcc

~

1N4001
Rx1

2

Tx1

3n.

Rx2

4 R

Tx2

5

R
0

23

001

22

011

21

002

~20

1

012

0

r

Rx3

6

Tx3

7,..

Rx4

8 R

Tx4

9,..

RXS

10 R

TXS

11

VSS

12

R
0

19

003

18

013

17 004
0

16 014
15

0

005

14 015
13 1 GNO

02
~

-12V

1N5818

-

Figure 4.

MOTOROLA COMMUNICATIONS DEVICE DATA

MC145403.MC145404.MC145405.MC145408

2-705

MOTOROLA

-

SEMICONDUCTOR
TECHNICAL DATA

MC145406

Driver/Receiver
EIA-232-E and CCITT V.28 (Formerly RS-232-D)
The MC145406 is a silicon-gate CMOS IC that combines three drivers and
three receivers to fulfill the electrical specifications of standards EIA-232-E
and CCITT V.28. The drivers feature true TTL input compatibility, slewrate-limited output, 300-0 power-off source impedance, and output typically
switching to within 25% of the supply rails. The receivers can handle up to
± 25 V while presenting 3 to 7 kO impedance. Hysteresis in the receivers aids
reception of noisy signals. By combining both drivers and receivers in a single
CMOS chip, the MC145406 provides efficient, low-power solutions for
EIA-232-E and V.28 applications.

PSUFFIX
PLASTIC
CASE 648

DWSUFFIX

SOG
CASE 751G

Drivers
• ±5 V to ± 12 V Supply Range
• 300-0 Power-Off Source Impedance
• Output Current Limiting
• TTL Compatible
• Maximum Slew Rate = 30 V/IlS
Receivers
• ±25 V Input Voltage Range When VDD = 12 V, VSS = -12 V
• 3 to 7 kO Input Impedance
• HysteresiS on Input Switchpoint

PIN ASSIGNMENT
VDD

VCC

Rxl

DOl

Txl

DI1

Rx2

D02

Tx2

DI2

Rx3

D03

Tx3

DI3

FUNCTION DIAGRAM
RECEIVER

VDD

VDD
15kO

Rx----*-~~--~------~

DO
5.4 k

GND

VSS
D= DRIVER
R=RECEIVER
HYSTERESIS
VDD

Vcc
LEVEL
SHIFT

1------ DI
1.4 V

VSS
'Protection circuit

MC145406
2-706

MOTOROLA COMMUNICATIONS DEVICE DATA

MAXIMUM RATINGS (Voltage polarities referenced to GNO)
Rating

Symbol

Value

Unit

DC Supply Voltages (VOo:! Vee)

VOO
VSS
Vee

- 0.5 to + 13.5
+ 0.5 to - 13.5
-0.5to+6.0

V

Input Voltage Range
Rxl-3 Inputs
011-3 Inputs

VIR

V
(VSS -15) to (VOO + 15)
- 0.5 10 (Vee + 0.5)

DC Current Per Pin

rnA

± 100

Power Dissipation

Po

1.0

W

Operating Temperature Range

TA

-40 to + 85

'e

Tstg

-85to+150

'e

Storage Temperature Rate

This device contains protection circuitry 10 protect the inputs against damage due to high static
voltages or electric fields; however, It is advised
that normal precautions be taken to avoid application of any voltage higher than maximum rated
voltages to this high Impedance circuit. For proper
operation, it is recommended that the voltages at
the 01 and DO pins be constrained to the range
GNO S VOl SVee and GNO S VOO S Vee. Also,
the voltage at the Rx pin should be constrained to
(VSS -15 V) S VRxl-3 S (VOO + 15 V), and Tx
should be constrained to VSS S VTxl-3 S VOO.
Unused Inputs must always be tied to an appropriate logic voltage level (e.g., GNO orVee for
01 and Ground for Rx.)

DC ELECTRICAL CHARACTERISTICS (All polarities referenced to GNO = 0 V, TA = - 40 to + 85'e)
Symbol

Min

Typ

Max

DC Supply Voltage
VOO
VSS
Vee (VOo:! Vee)

Parameter

VOO
VSS
Vee

4.5
-4.5
4.5

5to12
-510-12
5.0

13.2
-13.2
5.5

Quiescent Supply Current (Outputs unloaded, inputs low)
VOo= +12V
VSS=-12V
Vee=+5V

100
ISS
ICC

-

140
340
300

400
600
450

Unit
V

/IA

RECEIVER ELECTRICAL SPECIFICATIONS
(Voltage polarities referenced to GNO = OV, VOO = +5 to +12V, VSS =-5 to-12V, Voo~Vee, TA = -40 to +85'e)
Symbol

Min

Typ

Max

Unit

Input Turn-on Threshold
V001-003 = VOL, Vee = 5.0 V ±5%

Characteristic
Rxl-Rx3

Von

1.35

1.80

2.35

V

Input Turn-oll Threshold
V001-003 = VOH, Vee = 5.0 V ±5%

Rxl-Rx3

Voll

0.75

1.00

1.25

V

Input Threshold Hysteresis
Vee = 5.0 V±5%

Rxl-Rx3

Von-Voll

0.6

0.8

-

V

Input Resistance
(VSS -15 V) S VRxl-Rx3 S (VOO + 15 V)

Rxl-Rx3

Rln

3.0

5.4

7.0

kll

4.9
3.8

4.9
4.3

-

-

0.01
0.02
0.5

0.1
0.5
0.7

High-level Output Voltage (VRxl-Rx3 = -3 V 10 (VSS - 15 V»" 001-003
10H = -20 /lA, Vee = +5.0 V
IOH=-1 mA, Vee=+5.0V

VOH

low-level Output Voltage (VRxl-Rx3 = +3 V to (VOO + 15 V»* 001-003
10l = +20 /lA, Vee = +5.0 V
10l = +2 mA, Vee = +5.0 V
10l = +4 mA, Vee = +5.0 V

VOL

V

V

"This Is the range of input voltages as specified by EIA-232-E to cause a receiver to be in the high or low logic state.

MOTOROLA COMMUNICATIONS DEVICE DATA

MC145406
2-707

ELECTRICAL SPECIFICATIONS (Voltage polarities referenced to GNO = 0 V, VCC= + S V± So/., TA= -40 to +8S0C)
Characteristic

Symbol

Digital Input Voltage
Logic 0
Logic 1

011-013

Input Current
V011-013 = VCC

011-013

Max

2.0

lin

3.S
4.3
9.2

3.9
4.7
9.S

-4.0
-4.S
-10.0

-4.3
-S.2
-10.3

-

300

-

-

Output Low Voltage* (VOI1--3 = Logic 1, RL = 3.0 kQ)
Tx1-Tx3
VOO = +S.O V, VSS = -S.O V
VOO = +6.0 V, VSS = -6.0 V
VOO=+12.0V, VSS=-12.0V

VOL

Tx1-Tx3

-

Unit
V

-

VOH

Tx1-Tx3
Output Short-Circuit Current (VOO = + 12.0 V, VSS = -12.0 V)
Tx1-Tx3 shorted to GNO**
Tx1-Tx3 shorted to±1S.0 V***

Typ

VIL
VIH

Tx1-Tx3
Output High Voltage (VOI1--3 = Logic 0, RL = 3.0 kil)
VOO = +S.O V, VSS = -S.O V
VOO = +6.0 V, VSS = -6.0
VOO=+12.0V, VSS=-12.0V

Off Source Resistance (Figure 1)
VOO = VSS = GNO = 0 V, VTx1-Tx3 = ±2.0 V

Min

0.8

-

±1.0

j1A
V

-

-

V

-

Q
rnA

ISC

-

-

±22
±60

±60
±100

* The voltage specifications are in terms of absolute values.
** Specification Is for one Tx output pin to be shorted at a time. Should all three driverou1puts be shorted simultaneously, device power dissipation
limits will be exceeded.
*** This condition could exceed package limitations.
SWITCHING CHARACTERISTICS (VCC = +S V±So/., TA =-40 to +8SoC; See Figures 2 and 3)

Drivers
Characteristic
Propagation Delay 'Time
Low-to-Hlgh

Symbol

Min

Typ

Max

Tx1-Tx3
RL = 3 kQ, CL = SO pF

Hlgh-to-Low

ns
tpLH
tPHL

RL = 3 kQCL = SO pF
Output Slew Rate
Tx1-Tx3
Minimum Load
RL = 7 kQ, CL= 0 pF, VOO = +6to +12 V, VSS =-6to-12 V

Unit

-

300

SOO

-

300

SOO

SR

V/jlS

-

±9

±30

Maximum Load
RL = 3 kQ, CL =2S00 pF
VOO=+12V, VSS=-12V
VOO = +S V, VSS =-S V

4

-

-

-

-

-

Min

Typ

Max

1S0

42S

Receivers (CL = 50 pF)
Characteristic
Propagation Delay 'Time
Low-to-Hlgh

Symbol
001-003
tPLH

High-to-Low

tpHL

Output Rise 'Time

001-003

Output Fall 'Time

001-003

MC145406
2-708

tr
tf

-

Unit
ns

1S0

42S

2S0

400

ns

40

100

ns

MOTOROLA COMMUNICATIONS DEVICE DATA

PIN DESCRIPTIONS
VDD
Positive Power Supply (Pin 1)
The most positive power supply pin, which is typically +5
to +12V.
12 012

Tx2 5

10 013

Tx3 7

Vin =±2 V

VCC
Digital Power Supply (Pin 16)
The digital supply pin, which is connected to the logic
power supply (maximum +5.5 V). VCC mustbe less than
or equal to VOO.

Figure 1. Power-Off Source Resistance (Drivers)

DRIVERS

' - - - - - OV
VOH

RECEIVERS

VSS
Negative Power Supply (Pin 8)
The most negative power supply pin, which is typically -5
to -12 V.

--raV
'------OV

v...---- VOH
-VOL

Figure 2. Switching Characteristics

DRIVERS

GND
Ground (Pin 9)
Ground retum pin is typically connected to the signal ground
pin of the EIA·232-E connector (Pin 7) as well as to the logic
power supply ground.
Rx1, Rx2, Rx3
Receive Data Input (Pins 2, 4, 6)
These are the EIA-232-E receive signal inputs whose voltages can range from (VOO + 15 V) to (VSS -15 V). A voltage
between +3 and (VOO + 15 V) is decoded as a space and
causes the corresponding 00 pin to swing to ground (0 V);
a voltage between -3 and (VOO -15 V) is decoded as a mark
and causes the 00 pin to swing up to VCC. The actual turn-on
input switchpoint is typically biased at 1.8 V above ground,
and includes 800mV of hysteresis for noise rejection. The
nominal input impedance is 5 kQ. An open or grounded input
pin is interpreted as a mark, forcing the 00 pin to Vcc.
D01, D02, D03
Data Output (Pins 11, 13, 15)
These are the receiver digital output pins, which swing from
VCC to GNO. A space on the Rx pin causes 00 to produce
a logic 0; a mark produces a logic 1. Each output pin is capable
of driving one LSTTL input load.
DI1, DI2, DI3
Data Input (Pins 10, 12,14)
These are the high-impedance digital input pins to the drivers. TTL compatibility is accomplished by biasing the input
switchpoint at 1.4 V above GNO. However, 5-V CMOS compatibility is maintained as well. Input voltage levels on these
pins must be between VCC and GNO.
Tx1, Tx2,Tx3
Transmit Data Output(Pins 3, 5, 7)
These are the EIA-232-E transmit signal output pins, which
swing toward VOO and VSS. A logic 1 at a 01 input causes
the corresponding Tx output to swing toward VSS. A logic 0
causes the output to swing toward VOO (the output voltages
will be slightly less than VOO or VSS depending upon the output load). Output slew rates are limited to a maximum of 30
V per !lS. When the MC145406 is off (VOO = VSS = VCC =
GNO), the minimum output impedance is 300 Q.

SLEW RATE (SR) = -3 V - (3 V) OR 3 V - (-3 V)
tSLH
tsHL

Figure 3. Slew Rate Characterization

MOTOROLA COMMUNICATIONS OEVICE OATA

MC145406

2-709

APPLICATIONS INFORMATION
The MC145406 has been designed to meet the electrical
specifications of standards EIA-232-E and CCITT V.2B. EIA232-E defines the electrical and physical interface between
Data Communication Equipment (DCE) and Data Terminal·
Equipment (DTE).A DCE is connected to a DTE using acable
that typically carries up to 25 leads. These leads, referred
to as interchange circuits, allow the transfer of timing, data,
control, and test signals. Electrically this transfer requires
level shifting between the TTUCMOS logic levels of the
computer or modem and the high voltage levels of EIA-232-E,
which can range from ±3 to ±25 V. The MC145406, provides
the necessary level shifting as well as meeting other aspects
of the EIA-232-E specification.
DRIVERS
As defined by the specification, an EIA-232-E driver
presents a voltage of between ±5 to ±15 V into a load of
between 3 to 7 k!l A logic 1 at the driver input results in a
voltage of between -5 to -15 V. A logic 0 results in a voltage
between +5 to + 15V. When operating VDD and VSS at ±7 to
±12 V, the MC145406 meets this requirement. When
operating at ±5 V, the MC145406 drivers produce less than
±5 V at the output (when terminated), which does not meet
EIA-232-E specification. However, the output voltages when
using a ±5 V power supply are high enough (around ±4 V)
to permit proper reception by an EIA-232-E receiver, and can
be used in applications where strict compliance to EIA-232-E
is not required.
Another requirement olthe MC145406 drivers is that they
withstand a short to another driver in the EIA-232-E cable.
The worst-case condition that is permitted by EIA-232-E is
a ±15 V source that is current limited to 500 mAo The
MC145406 drivers can withstand this condition momentariIy.ln most short circuit conditions the source driver will have
a series 300 n output impedance needed to satisfy the
EIA-232-E driver requirements. This will reduce the short
circuit current to under 40 mA which is an acceptable level
for the MC145406 to withstand.
Unlike some other drivers, the MC145406 drivers feature
an intemally-limited output slew rate that does not exceed 30
V per Ils.
RECEIVERS
The job of an EIA-232-E receiver is to level-shift voltages
in the range of -25 to +25 V down to TTUCMOS logic levels
(0 to +5 V). A voltage of between -3 and -25 V on Rx1 is
defined as a mark and produces a logic 1 at D01. A voltage
between +3 and +25 V is a space and produces a logic zero.
While receiving these signals, the Rx inputs must present a
resistance between 3 and 7 kn. Nominally, the input resistance
of the Rx1-Rx3 inputs is 5.4 kn
The inputthreshold olthe Rx1-Rx3 inputs is typically biased
at 1.B V above ground (GND) with typically BOO mV of
hysteresis included to improve noise immunity. The 1.B V bias

MC145406
2-710

forces the appropriate DO pin to a logic 1 when its Rx input
is open or grounded as called for in the EIA-232-E
specification. Notice that TTL logic levels can be applied to
the Rx inputs in lieu of normal EIA-232-E signal levels. This
might be helpful in situations where access to the modem or
computer through the EIA-232-E connector is necessary with
TTL devices. However, it is important not to connect the
EIA-232-E outputs (Tx1-Tx3) to TTL inputs since TTL
operates off +5 V only, and may be damaged by the high output
voltage of the MC145406.
The DO outputs are to be connected to a TTL or CMOS
input (such as an input to a modem chip). These outputs
will swing from VCC to ground, allowing the designer to
operate the DO and DI pins from digital power supply. The
Tx and Rx sections are independently powered by VDD and
VSS so that one may run logic at +5 V and the EIA-232-E
signals at ± 12 V.
POWER SUPPLY CONSIDERATIONS
Figure 4 shows a technique to guard against excessive
device current.
The diode D1 prevents excessive current from flowing
through an internal diode from the VCC pin to the VDD pin
when VDD < VCC by approximately 0.6 V. This high current
condition can exist for a short period of time during power
up/down. Additionally, if the + 12 V supply is switched off
while the + 5 V is on and the off supply is a low impedance
to ground, the diode D1 will prevent current flow through
the internal diode.
The diode D2 is used as a voltage clamp, to prevent VSS
from drifting positive to VCC, in the event that power is
removed from VSS (Pin 12). If VSS power is removed, and
the impedance from the VSS pin to ground is greater than
approximately 3 kn, this pin will be pulled to V CC by internal
circuitry causing excessive current in the VCC pin.
If by design, neither of the above conditions are allowed
to exist, then the diodes D1 and D2 are not required.
ESD PROTECTION
ESD protection on IC devices that have their pins accessible
to the outside world is essential. High static voltages applied
to the pins when someone touches them either directly or
indirectly can cause damage to gate oxides and transistor
junctions by coupling a portion of the energy from the I/O pin
to the power supply buses of the IC. This coupling will usually
occur through the internal ESD protection diodes. The key to
protecting the IC is to shunt as much of the energy to ground
as possible before it enters the IC. Figure 4 shows a technique
which will clamp the ESD voltage at approximately ±15 V
using the MMVZ15VDLT1. Any residual voltage which
appears on the supply pins is shunted to ground through the
capacitors C1-C3. This scheme has provided protection to
the interface part up to ± 10 kV, using the human body model
test.

MOTOROLA COMMUNICATIONS DEVICE DATA

VOO
MMBZ15VOLT x 6

01

't1

IN4001

VCC
O.II1F

If---<
C2
L.-

TO
CONNECTOR

-J0-

':"

Txl

0 0 1 4 - Rxl

012

-{9>0-

Tx2 5

NC 13 002-c0-

NCll 003-0«}- Rx3

MOOE
GNO
12

12

10

[B

vAG
COT

O.II1F
VSS BYPASS

10kO

10kO
CFB

14
15

SaT

RING

VOO
VCC
MC145406

3

RxO

600:600

VOO

3.579
MHz

11

16 RxA1

,

D

7
CCOA"
O.II1F

VSS

GNO

O.lI1F
'Line protection circuit
"Refer to the applications information for vatues of CCDA and RTLA

-5V

Figure 5. 5-V 300-Baud Modem with EIA-232-E Interface

MOTOROLA COMMUNICATIONS DEVICE DATA

MC145406
2-711

MC34119
SPEAKER
DRIVER

MCl45503
FILTERI
CODEC

MC145412113/16
PULSEfTONE
DIALER

RINGING
MC145426
UDLT

1 2 3
4 5 6
7 8 9
• 0 #

LINE
INTERFACE
(TRANSFORMER
AND
PROTECTION)

HOOKSWITCH

TWISTED
PAIR

SYNC

CONNECTION
TO EXTERNAL
TERMINAL
ORPC

MC145406
RS-232
DRIVER
RECEIVER

MC145428
DATA
SET
INTERFACE

+5V
GND
-5V

MC34129
SWITCHING
POWER
SUPPLY
(ISOLATED)

LINE
FILTER

Figure 6. Line-Powered Voice/Data Telephone with Electrically Isolated EIA-232-E Interface

MC145406
2-712

MOTOROLA COMMUNICATIONS DEVICE DATA

:s::
0

d:Il
0

NC NC NC

>

1

(')

14 V Rl
CC

0

:s::
:s::
c
z
0

:!i
5z

en
m
<
0
m

:'"

0

co

0

»~

51 01 5
_ 6

MC74HC74
7 GNO

VOO

!!

CD

4

c

iil

m

R5

'?

~

'tI

1/1

3

NC

2

8 NC
02 9 NC
52
NC
C2
NC

NC

NC

02

05Rj-LJ

C

if
Il.

12

g~
Q2

2.048 MHz

DB·25

VOO

VOO
128 kHz
8MHz

12

C

Ii
DI
:::I

n

5T

3:

NC

CD

NC 5T

91"81 51 41

L...U!._+-I-_ _l!.J11 RxD

0
Il.

502

r
L-_ _ _...l

CD

3

512VO LB

MCl45422

~

~21

LOl F,;-:i:----,
L02 20

1000
220 ~ pF' ~ 220

::r

Hr1

m
~

8

tl
~

m

SiD

i'

!Il
'i
DI
!!I.
CD

.:\.

s::

(')

N"'"
,01

.... "'"

-0
Co)Q)

9

l~IP

7
"::"

"::"

01

O.lI1F
..

'For optional filtering.
"TRl should be cut when this capacitor is used.

~ 02
ST-STRAP
NC - NO CONNECTION
VCC=5V
GND=OV
VOD AND VSS ARE DISCUSSED IN THE EIA·232·D SECTION

10k
'VIII>

T1

:

1.011 P '

16
4
10

I

I

NC

NC

RING

MOTOROLA

-

SEMICONDUCTOR
TECHNICAL DATA

MC14S407
Advance Information
S-Yolt-Only Driver/Receiver
EIA-232-E and CCITT V.28

P SUFFIX
PLASTIC
CASE 738

The MC145407 is a silicon-gate CMOS IC that combines three drivers and
three receivers to fulfill the electrical specifications of EIA-232-E and CCITT V.28
while operating from a single +5 V power supply. A voltage doubler and inverter
convert the +5V to ±10 V. This is accomplished through an on-board 20-kHz
oscillator and four inexpensive external electrolytic capacitors. The three drivers
and three receivers of the MC145407 are virtually identical to those of the
MC145406. Therefore, for applications requiring more than three drivers and/or
three receivers, an MC145406 can be powered from an MC145407. since the
MC145407 charge pumps have been designed to guarantee ± 5 V at the output of up to six drivers. Thus, the MC145407 provides a high-performance,
low- power, stand-alone solution or, with the MC145406, a +5 V only, highperformance two-chip solution.
Drivers
• ±7.5 V Output Swing
• 300-0 Power-Off Impedance
• Output Current Limiting
• TTL and CMOS Compatible Inputs
• Slew Rate Range Limited from
4 V/IlS to 30 VIllS
Receivers
• +25 V Input Range
• 3 to 7 kO Input Impedance
• 0.8-V Hysteresis for Enhanced
Noise Immunity

OW SUFFIX

SOG
CASE751D

PIN ASSIGNMENT

Charge Pumps
• +5Vto±10VDual
Charge Pump Architecture
• Supply Outputs Capable of
Driving Three On-Chip Drivers
and Three Drivers on the
MC145406 Simultaneously
• Requires Four Inexpensive
Electrolytic Capacitors
• On-Chip 20-kHz Oscillator

C1+

C2+

FUNCTION DIAGRAM

GNO

VCC

C2-

C1-

Vss

VDD

Ax1

D01

Tx1

DI1

Ax2

002

Tx2

012

Ax3

D03

Tx3

DI3

CHARGE PUMPS

D=OAIVEA
A=AECEIVEA

+
C4

C3

VDD

VDD

C1- C1 +

C2+

C2VCC

15kn

VCC

Ax--~~~~--~------~

DO

300n
Tx

5.4 k

~'VII\,..-+-.

LEVEL
SHIFT

Vss

'Preclection circuil
Vss
This document contains Information on a new product. Specification and information herein are subject to change without notics.

MC145407

2-714

MOTOROLA COMMUNICATIONS DEVICE DATA

This device contains protection circuitry to
protect the inputs against damage due to high
static voltages or electric fields; however, it is
advised that normal precautions be taken to avoid
application of any voltage higher than maximum
rated voltages to this high impedance circuil. For
proper operation, it is recommended that the
voltages at the DI and DO pins be constrained to
the range GND ~ VDI ~ VCC and GND ~ VOO ~
VCC. Also, the voltage at the Rx pin should be
constrained to (VSS -15 V) ~ VRx1-Rx3 ~
(VDO + 15 V), and Tx should be constrained to
VSS ~ VTx1-Tx3'; VDD·
Unused inputs must always be tied to appropriate logic voltage level (e.g., GNO or VCC for 01,
and GND for Rx.)

MAXIMUM RATINGS (Voltage polarities referenced to GND)
Rating
DC Supply Voltages

Symbol

Value

Unit

VCC

-0.5 to 6.0

V
V

Input Voltage Range
Rx1-Rx3 Inputs
D11-D13 Inputs

VIR

DC Current Per Pin

I

± 100

PD

1

W

TA

-40 to +85

°c

Tstg

-85 to +150

°c

VSS-15toVDD+15
-0.5 to (VCC + 0.5)

Power Dissipation
Operating Temperature Range
Storage Temperature Range

rnA

DC ELECTRICAL CHARACTERISTICS (All polarities referenced to GNO = 0 V; C1, C2, C3, C4 = 10 I'F; TA =-40 to +85°C)
Symbol

Min

Typ

Max

OC Supply Voltage

VCC

4.5

5

5.5

V

Quiescent Supply Current
(Outputs unloaded, inputs low)

ICC

-

1.2

3.0

rnA

VDD

8.5
7.5
6

10
9.5
9

11

V

-

-8.5
-7.5
-6

-10
-9.2
-8.6

Parameter

Output Voltage
Iload= 5 rnA
Iload = 10 rnA

Iload=OmA

Iload = 0 rnA
Iload= 5 rnA
Iload = 10 rnA

VSS

Unit

-11

-

RECEIVER ELECTRICAL SPECIFICATIONS
(Voltage polarities referenced to GND = 0 V; VCC = +5 V ±10%; C1, C2, C3, C4 = 10 IlF; TA = -40 to +85°C)
Symbol

Min

Typ

Max

Unit

Input Turn-on Threshold
VD01-D03 = VOL

Rx1-Rx3

Von

1.35

1.8

2.35

V

Input Turn-off Threshold
VD01-D03 = VOH

Rx1-Rx3

Voff

0.75

1.0

1.25

V

Input Threshold Hysteresis (Von - Voff)

Rx1-Rx3

Vhys

0.6

0.8

-

Input Resistance

Rx1-Rx3

Rin

3.0

5.4

7.0

High-Level Output Voltage
VRx1-Rx3 = -3 V to -25 V
IOH=-2O I'A
IOH=-1 rnA

D01-D03

VOH

Low-Level Output Voltage
VRx1-Rx3 = +3 V to +25 V
10L = +20 !lA
IOL=+1.6mA

001-003

Characteristic

MOTOROLA COMMUNICATIONS DEVICE DATA

V
kQ

V
VCC-O.1
VCC-0.7

4.3

-

V

VOL

-

0.01
0.5

0.1
0.7

MC145407
2-715

DRIVER ELECTRICAL SPECIFICATIONS
(Voltage polarities referenced to GNO = OV: VCC=+S V±10%; C1, C2, C3, 04= 10 I1F; TA =-40 to +8S0C)
Characteristic

Symbol

Oigitallnput Voltage
Logic 0
Logic 1

011-013

Input Current
GNO SVOI1-013SVCC

011-013

Min

Typ

Max

-

0.8

VIL
VIH

2.0

lin

-

-

Output High Voltage
V011-013 = Logic 0, RL = 3.0

Tx1-Tx3
Tx1-Tx6*

VOH

k.Q

6
S

7.S
6.S

Output Low Voltage
V011-013 = Logic 1, RL = 3.0

Tx1-Tx3
Tx1-Tx6*

VOL

k.Q

-6
-S

-7.S
-6.S

Off Source Impedance (Figure 1)

Tx1-Tx3

Zoff

300

-

Output Short-Circuit Current
VCC=+S.SV

Tx1-Tx3

ISC

V

±1.0

!LA

-

V
V

°

rnA

-

Tx1-Tx3 shorted to GNO"
Tx1-Tx3 shorted to ± 1S V'"

Unit

-

±60
±100

• Specifications for an MC145407 powering an MC145406 with three additional drivers/receivers •
•• Specification is for one Tx output pin to be shorted at a time. Should all three driver outputs be shorted simultaneously, device power dissipation
limits could be exceeded .
••• This condition could exceed package limitations.
SWITCHING CHARACTERISTICS (VCC =+S V±10%; C1, C2, C3, 04= 10 I1F; TA =-4010 +8SoC; See Figures 2 and 3)

Drivers
Symbol

Characteristic
Propagation Oelay Time
Low-to-Hlgh
RL = 3 kO, CL =SO pF or2S00 pF

Typ

Max

Tx1-Tx3

Hlgh-to-Low
RL = 3 kO, CL= SO pF or2S00 pF
Output Slew Rate
Minimum Load: RL = 7 k.Q, CL = 0 pF

Min

Tx1-Tx3

Unit
IJ.S

tPLH

-

O.S

1

tPHL

-

O.S

1

-

9.0

±30

4.0

-

-

Min

Typ

Max

-

-

1

2S0

400

ns

40

100

ns

SR

Maximum Load: RL = 3 k.Q, CL = 2S00 pF

V/IJ.S

Receivers (CL = so pF)
Characteristic
Propagation Oelay Time
Low-to-High

Symbol
001-003
tPLH

High-to-Low

tPHL

Output Rise Time

001-003

tr

Output Fall Time

001-003

tf

MC145407
2-716

Unit
I1S

1

MOTOROLA COMMUNICATIONS DEVICE DATA

PIN DESCRIPTIONS
VCC
Digital Power Supply (Pin 19)
The digital supply pin, which is connected to the logic power
supply. This pin should have a 0.33-I1F capacitor to ground.
GND
Ground (Pin 2)
Ground return pin is typically connected to the signal ground
pin of the EIA-232-E connector (Pin 7) as well as to the logic
power supply ground.
VDD
Positive Power Supply (Pin 17)
This is the positive output of the on-chip voltage doubler
and the positive power supply input of the driver/receiver
sections of the device. This pin requires an external storage
capacitor to filter the 50% duty cycle voltage generated by the
charge pump.
VSS
Negative Power Supply (Pin 4)
This is the negative output of the on-chip voltage
doubler/ inverter and the negative power supply input of
the driver/receiver sections olthe device. This pin requires
an external storage capacitor to filter the 50% duty cycle
voltage generated by the charge pump.
' - - - - - OV

RECEIVERS

-+3V

'------OV
r----VOH
-VOL

Figure 2. Switching Characteristics

DRIVERS

C2+, C2-, CI-, C1+
Voltage Doubler and Inverter (Pins 1, 3, 18, 20)
These are the connections to the internal voltage doubler
and inverter, which generate the VOO and VSS voltages.
Rx1, Rx2, Rx3
Receive Data Input (Pins 5, 7, 9)
These are the EIA-232-E receive signal inputs. A voltage
between + 3 and + 25 V is decoded as a space and causes
the corresponding DO pin to swing to ground (0 V). A
voltage between -3 and -25 V is decoded as a mark, and
causes the DO pin to swing up to Vcc.
D01, D02, 003
Data Output (Pins 16,14,12)
These are the receiver digital output pins, which swing from
VCC to GND. Each output pin is capable of driving one lSTTl
input load.
D11, D12, DI3
Data Input (Pins 16,13,11)
These are the high-impedance digital input pins to the
drivers. Input voltage levels onthese pins must be between
VCC and GND.
TX1,Tx2,Tx3
Transmit Data Output (Pins 6,8,10)
These are the EIA-232-E transmit signal output pins,
which swing toward VDD and VSS. A logic 1 at a DI input
causes the corresponding Tx output to swing toward VSS.
A logic 0 causes the output to swing toward VDD. The
actual levels and slew rate achieved will depend on the
output loading (Rl IICl).

SLEW RATE. (SR) = -aV-(3V) OR ~
tSLH
tSHL

Figure 3. Slew Rate Characterization

MOTOROLA COMMUNICATIONS DEVICE DATA

MC145407
2-717

APPLICATIONS INFORMATION
ESD CONSIDERATIONS
ESD protection on IC devices that have their pins
accessible to the. outside world is essential. High static
voltages applied to the pins when someone touches them
either directly or indirectly can cause damage to gate
oxides and transistor junctions by coupling a portion of the
energy from the 1/0 pin to the power supply busses of the
IC. This coupling.will usually occur through the internal
ESD protection diodes. The key to protecting the IC is to
shunt as much of the energy to ground as possible before
it enters the IC. Figure 7 shows a technique which will
clamp the ESD voltage at approximately + 15 V using the
MMVZ15VDLT1. Any residual voltage which appears on
the supply pins is shunted to ground through the O. H1F
capaCitors.

in driving a companion MC145406 or MC145403. If there
is no requirement to support a second interface device
andlor the charge pump is not being used to power any
other components, the MC145407 is capable of complying
with EIA-232-E and V.28 with smaller value charge pump
caps. Table 1 summarizes driver performance with both
2.2-J.l.F and 1.0-IlF charge pump caps.
Table 1. Typical Performance
Parameter

The MC145407 is characterized in the electrical tables
-using 1O-J.l.F charge pump caps to illustrate its capability

1.0 IlF

7.3

7.2

TxVOH @8SoC

7.2

7.1

TxVOL@2SoC

-6.5

-6.4

TXVOL@8SoC

OPERATION WITH SMALLER VALUE CHARGE PUMP
CAPS

2.21lF

TxVOH @2SoC

-6.1

-6.0

Tx Slew Rate @ 25°C

B.O V/JlS

B.OV/IJ.S

Tx Slew Rate @ BSoC

7.0 V/Jls

7.0 V/JlS

+5V

~F
Xin
ROSI
COSI
1
OTMF ~ f----'-I
OSI
INPUT
20k!l
17
0.1 JlF
TxA
15
RxA2
10ka

TIP~

RTx
10 JlF 600
+

RING-TI
VOO
O.IJlF
VooBYPASS

16

Xout

~
CJ 3.579

8

MHz

CD

11
TxO
5
RxO
MCI45442

RxAl

0.1 JlF

10JlF

10JlF
C2+
15 011
16 001
13
012

10k!l

EIA·232·E
08-25
CONNECTOR

OR

MCI45443 SOT

CFB

1

0.1 JlF
VSS BYPASS

18

~F

Exl
FB

CCOA
0.1 JlF

* Line protection circuit

Figure 4. 5-V, aOO-Baud Modem with EIA-232-E Interface

MC145407
2-718

MOTOROLA COMMUNICATIONS DEVICE DATA

+5V

VOO

VCC

Rx1

001

Tx1

011

4 Rx2
Tx2

MC145406

002
012

Rx3

003

Tx3

013

VSS

GNO

16

C2+

15

10llF

GNO

10llF

14

C2-

13
12
11

VSS

VOO

Rx1

MC145407 001

Rx2
Tx2
10llF

Rx3
10

16

011 15
14
002
13
012
12
003
11
013

Tx1

10

17

Tx3

Figure 5. MC145406/MC145407 5-V Only Solution for up to Six EIA-232-E Drivers and Receivers
+5V
+10V

20
19
18
4

17

C1+
Vec
C1VOO

O.1IlF

Jl

O.1IlF

16
15

7

14
13
12

10

11

Figure 6. TWo Supply Configuration (MC145407 Generates VSS Only)
+5V
MMBZ15VDLT x 6
20

O.1IlF

19
18
4

17
16
15

Rx2

TO
CONNECTOR

7

Tx2
Rx3
Tx3

14
13

9

12

10

11

001

:P

O.1IlF

011
002
012
003
013

Figure 7. ESC Protection Scheme

MOTOROLA COMMUNICATIONS DEVICE DATA

MC145407

2·719

MOTOROLA

-

SEMICONDUCTOR
TECHNICAL DATA

'---_M_C_14_5_4_1_1_---'1

Bit Rate Generator
The MC145411 bit rate generator is constructed with complementary MOS
enhancement mode devices. It utilizes a frequency divider network to provide a
wide range of output frequencies.
A crystal controlled oscillator is the clock source for the network. A two-bit
address is provided to select one of four multiple output clock rates.
Applications include a selectable frequency source for equipment in the data
communications market, such as teleprinters, printers, CRT terminals, and
microprocessor systems.
• Single 5-V (±5%) Power Supply
• Internal Oscillator Crystal Controlled for Stability (to 4 MHz)
• 21 Different Bit Rates
• 9 Different Bit Rate Output Pins
• Programmable Time Bases for One of Four Multiple Output Rates
• 50% Output Duty Cycle
• Buffered Outputs Compatible with Low Power TTL
• Noise Immunity = 45% of VDD Typical
• Diode Protection on All Inputs
• External Clock May be Applied to Pin 13
• Internal Pull-up Resistor on Reset Input

••
1

PSUFFIX
PLASTIC
CASE 648

PIN ASSIGNMENT
F1

VDD

F3

RSA

F5

RSS

F6

XTALin

F7

XTALout

Fa

F9

RESET

F2

VSS

F4

N

BLOCK DIAGRAM
RSA
RSs

CRYSTALin
'CRYSTALout

RESET

15
14

1 F1
10 F2
2 F3

13
12

OSCILLATOR
CIRCUIT

DIVIDER

DIVIDERS

F4
F5
4 F6

F7
Fa

7

'See Figure 2 for typical
crystal oscillator circuits

'--_ _ _ _ _ _ _ _ _ _ _ _1:..:. .1 F9

"When Reset = 0, outputs F1-FS = 0, output F9 = 1.

MC145411
2"720

RATE
SELECT
LOGIC

VDD= PIN 16
VSS= PIN 8

MOTOROLA COMMUNICATIONS DEVICE DATA

MOTOROLA

-

SEMICONDUCTOR
TECHNICAL DATA

MC145412
MC145413
MC145512

Advance Information

Pulse/Tone Repertory Dialer
Low Power Silicon-Gate CMOS
The MC145412113 and MC145512 are silicon gate, monolithic CMOS
intergrated circuits which convert keyboard inputs into either pulse or DTMF
outputs. They are packaged in a standard 1B-pin (0.3" wide) plastic DIP.
• 3 x 4 or 4 x 4 Keyboard Compatibility Which Allows the Use of 2-of-7, 2-of-B,
or Form A Type Keyboards
• MC145413 Adds Keyboard Selectable Pause Switch Function
• Single Pin Switchabie Between DTMF, 10 pps and 20 pps
• 500-Hz Tone Signal Output in the Pulse Dialing Mode
• Memory Storage for Ten 1B-Digit Numbers, Including Last Number Redial
• Uses 3.579545-MHz Colorburst Crystal
• Telephone Line Powered
• Silicon Gate CMOS Technology for 1.7 to 5.5 V Low Power Operation
• Stand Alone DTMF Dialer/Stand Alone Pulse Dialer
• Mute Output Used to Isolate Receiver from Dialing Output
• Memory Programming Options by Keyboard Configuration

_.su~

PLASTIC
CASE 707

1

ORDERING INFORMATION
Denotes
Plastic DIP
40/60 MIB Ratio
32166 M/B Ratio

PIN ASSIGNMENT
DTMFOUT

VDD
COL 4

OPL

COLI

ROWt
ROW 2

COL 3

ROW 3
ROW 4

VSS
TSO

OH
MO

OSCin
OSCout

BLOCK DIAGRAM

MS

TSO
MS

to

COL4
COLt
COL 2
COL 3
ROWt
ROW 2
ROW 3
ROW 4

DlA
CONVERSION
& MIXING

..-JL~ OPL
~­
~ MO

OH

VOO=PIN 1
VSS= PIN6

OSCin
OSCout

This document contains Information on a new product. Specification and Information herein are subject to change without notice.

MOTOROLA COMMUNICATIONS DEVICE DATA

MC145412.MC145413.MC145512
2-721

ABSOLUTE MAXIMUM RATINGS (VSS = 0 V)
Rating

Symbol

Value

VDD

- 0.5 to + B.O

V

TA

-30to+60

°C

Tstg

-65to+150

DC Supply Voltage
Operating Temperature
Storage Temperature
DC Current Drain Per Pin
Maximum Voltage
On Any Pin Relative to VSS
On Any Pin Relative to VDD

I

10

Vinl
Vin2

-0.5
+0.5

Unit

°C
. mA
V

ELECTRICAL CHARACTERISTICS (TA= -30 to +60°C, VDD = 2.5 V, VSS = 0 V, Unless Otherwise Noted)
Characteristic

Symbol

Min

Typ

Max

Unit

Pulse Mode
DTMFMode

VDD

2.0
2.5

-

5.5
5.5

V

Pulse Mode (MS = VDD)
DTMF Mode (MS = VSS)

IDD

-

0.25
t.O

0.7
2.0

mA

Vstby

1.7

DC Supply Voltage
Operating Current
Memory Retention Voltage
Memory Retention Current
Input Voltage, Row/Column/OH
Row Column Input Impedance

(VDD=I.7V)
(VDD=2.5V)

VIL
VIH

O.BVDD

ToVDD
ToVSS

Zin

-

MS Pin Input Impedance
(VDD = 2.5 V) TSO Pin
MOPin
OPL Pin
(VDD = 4.0) MO Pin
OPL Pin

-

V

2.0
2.5

I1A

...,.

0.2VDD

V

-

-

50
10

-

pF

Zin

50

200

-

k11

10L

0.5
1.0
1.0
3.0
4.5

0.7
2.0
2.0

-

mA

Cin

-

100
2

k11
k11

10H

0.5

0.7

-

MO,OPLPins

Ilkg

-

-

1.0

I1A

Row Tone
Column Tone

Vout

260
330

310
390

370
460

mVrms

-80

dBm

TSO Output Source Current (Vout = 2.0 V)

DTMF Output Level Referenced to VDoI2
(VDD = 2.5 to 4.0 V, RL= 600 11 to VDD)

1.0
1.2

-

-

R

Input Capacitance (All Inputs)

Output Leakage Current

-

"0" Level
"I" Level

OH Pull-Up Resistance

Output Sink Current

Istby

-

DTMF Output Tone Leakage (VDD = 3.5, RL = 600 n, 300 to 4000 Hz)
DTMF Output Tone Distortion (VDD = 3.5, RL = 600 n, 300 to 4000 Hz)
Pre-Emphasis

1

-

-

-'

mA

5

%

2

2.5

dB

DTMF Output Leakage Current While Not Dialing Tones (VDD = 2.5 V)

-

-

1.0

I1A

DTMF Output Sink Current While Dialing Tones

20

-

-

I1A

MC145412.MC145413.MC145512
2-722

MOTOROLA COMMUNICATIONS DEVICE DATA

SWITCHING CHARACTERISTICS (TA = 25°C, VDD = 2.5 V, Osc. Freq.= 3.579545 MHz, Unless Otherwise Noted)
Symbol

Min

Typ

Max

I

-

250

-

Hz

Key Debounce lime

tDB

16

-

20

ms

DTMF Tone Duration for Keypad Dialing

tw1

60

78

-

ms

tw2

90

102

110

ms

tiD

90

98

110

ms

0.8
0.4

1.0
0.5

1.2
0.6

s

Characteristic
Row/Column Scan Frequency

DTMF Tone Duration lor Memory Dialing
DTMF (Memory Dialing)

Inter-Digit Pause lime

Pulse 10 pps
20pps
trms

-

1

-

kHz

MC145412113
MC145512

MBR

-

40/60
32168

%

MS = Open
MS=VDD

IOPL

MS Pin Scan Rate
MakelBreak Ratio
(MC = Open orVDD)
Outpulsing Rate
MUTE Output (MO) Overlap lime
TSO Output Frequency
TSO Output Duration
DTMF Cycle lime

tMO

-

2

fTso
trso

-

500

-

35

-

40

-

5
10

-

-

+1.0

(Memory Dialing
(Keypad Dialing)

DTMF Frequency Deviation
Predigit Mute
MC145412113

!(j

Pulse 10 pps
20pps
Pulse 10 pps
20 pps
DTMF

MC145512

PIN DESCRIPTIONS
VDD,VSS
Power Supply (Pins 1, 6)
DC power is supplied to the part on these two pins, with VDD
being the most positive. Permissible ranges are from 1.7 to
5.5V.
MS
Mode Select (Pin 10)
The MS pin is a three-state input for switching between
DTMF, 10 pps, and 20 pps dialing modes. Mode selection is
done during the first key entry debounce period after the dialer
has completed a dialing sequence or has just come off hook.
When this pin is not scanned it is high impedance.
This pin is a combination input and weak output. The input
circuitry has the capability to determine each of these three
states. When the pin is open, the weak driver will be able to
clock the pin at 1 kHz. The relationship between pin input
voltage and operating mode is shown in Table 1.
Table 1_ Mode Select Options
MS

Dialing Mode

VDD

20 pps Pulse Dialing

Open

10 pps Pulse Dialing

VSS

DTMFDialing

MOTOROLA COMMUNICATIONS DEVICE DATA

Unit

-

-

10
20

-

pps
ms
Hz
ms
tonesls
%

ms
40
20
32
16
1

-

-

OH
On-Hook (Pin 12)
Connecting the OH pin to VDO or allowing it to float sets
the device in the On-hook mode. Connecting this pin to VSS
selects the Off-hook mode. When in the On-hook mode,
repertory memory can be programmed without a dialing
output.
TSO
Tone Signal Output (Pin 7)
TSO emits 500-Hz tone signals after valid key inputs are
accepted providing audio feedback for key depressions
(except when DTMF tones are generated). This pin also
outputs a tone during on-hook programming.
DTMFOUT
Dual Tone Multifrequency Output (Pin 18)
When the MS pin is set to VSS the DTMF OUT pin outputs
tones corresponding to the row and column of the key depressed. Simultaneously depressing two or more keys in a
single row (or column) will generate the corresponding row (or
column) tone on 4 x 4 keypad mode only.
In pulse dialing mode (MS =VDD or float) and during onhook programming this pin is high impedance. While outputtingtones, this pin hasadcbiasat(VDD-VSS)/2. DTMFOUT
is an open-drain output requiring an external pull-up to VDD.
This pull-up resistor must satisfy the instantaneous current
requirements of the internal feedback network in addition to
the load applied to the pin.

MC145412.MC145413.MC145512
2-723

OPL
Outpulsing (Pin 17)
This pin outputs pulses at 10 pps (MS is open) or 20 pps
(MS VDD). The MC145412113 have a makelbreak ratio of
40/60, while the MC145512 has a makelbreak ratio of 32168.
In the DTMF dialing mode (MS = VSS), this output is high impedance. During on-hook programming this pin will not
outpulse. This pin is an open drain N-channel output which
pulls low to break the loop current.

=

MO
Mute Output (Pin 11)
The Mute Output is an open drain N-channel output that
pulls to VSS during OPL outpulsing and during off-hook key depressions and memory dialing in DTMF mode.
COL l-COL 4 and ROW l-ROW 4
KEYBOARD INPUTS (Pins 2, 3, 4, 5, 13, 14, 15, 16)
The keyboard inputs allow either a single contact (Class A)
keyboard, or a standard 2-of-8 or 2-of-7 keyboard with VSS
tied to common. A valid key entry occurs when either a single
row is tied to a single column, or a single row and column are
simultaneously connected to VSS. Connecting pin 2, COL 4,
to VDD sets the part to 3 x 4 keyboard mode. Keyboard mode
selection is performed during application of power.
Typical keyboard configurations are shown in Figure 1.
OSCin, OSCout
Oscillator Input and Oscillator Output (Pins 8, 9)
A 3.579545-MHz crystal is required as the frequency reference forthe on-chip oscillator. Crystal biasing is accomplished
by an internal 'resistor and capacitors.

GENERAL DEVICE DESCRIPTION
The MC1454121MC145512 and the MC145413 provide
users with switchable pulse and DTMF dialing functions. The
MC1454121MC145512 change dialing modes via the MS pin.
The MC145413 allows users to switch dialing modes via the
keyboard in addition to the MS pin. All devices have 10
memories, LNR (last number redial) inclusive, each 18 digits
long.
On application of power, there is a 64-ms initialization period
during which the oscillator is enabled and the keyboard inputs
are disabled. During initialization COL 4 is scanned to set the
keyboard mode. If the COL 4 input is high (VDD), the dialer
is set to the 3 x 4 keypad mode; otherwise, the 4 x 4 keypad
mode is selected. Changing modes is not possible after this
initialization period.
During normal dialing, the oscillator starts when a key is
depressed. The key input is debounced for 32 ms. During this
debounce period the RAM and dialing circuits are disabled
and the mode select pin is scanned to determine the dialing
mode (either 10 pps, 20 pps, or DTMF). After debounce, the
keypad entry is checked and the input is latched into LNR
memory followed by a stop code. This process continues until
18 digits have been entered. If a 19th digit is entered, it will
over-write the first digit and will be followed by a stop code.
When dialing, the device fetches data from memory until a
stop code is encountered or 18 digits have been dialed.
During manual DTMF dialing, a minimum tone duration of

MC145412.MC145413.MC145512
2-724

60-ms DTMF is output and will continuously output in 32-ms
iricrements as long as the key is depressed. The DTMF OUT
pin is designed to drive an external PNP transistor which can
be used to modulate tip and ring voltage at the DTMF
.
frequencies.
CLASS A (SPST)

STANDARD 2·0F·7 (DPST)

-'-

COL - - 0

0 - - ROW

VSS

-Cl~o--COL

0 - - ROW

STANDARD 2·0F·7 (DPST)

c l:

:

r--- COL

VDD ----,
VSS _L-J

__

r--- ROW

VDD - - - - ,
VSS _L-J

__

Figure 1. Keyboard Configurations
If the first key is for redial or recall, the device will respond
accordingly, either redialing the last number entered, or
recalling and dialing the number selected by a subsequent
key depression. Responses to dialing sequences for 4 x 4
key-boards are shown in Figure 2, and 3 x 4 keyboard
responses are shown in Figure 3.
The MC145412 series can be configured with an external
battery to provide memory retention power and allow on-hook
programming of the repertory memory. If the part is in the
on-hook mode and a key is depressed, the oscillator will start
and the key entry will be stored in the last number redial
memory. Dialing outputs will not be activated while the device
is in the on-hook condition. Dialing inputs will be stored in last
number redial memory, as during off-hook operation. Afterthe
number has been entered in the on-hook mode, it can be
stored in repertory memory. For the 4 x 4 keyboard, pressing
the STORE key (* for 3 x 4 keyboard), followed by a digit (1
through 9) will store the number in the repertory memory
location specified by the digit.
The RECALL key for the 4 x 4 keypad is used to recall and
dial numbers stored in the repertory memory. The digit
immediately following the RECALL key designates the
memory location of the number to be auto'dialed. For the 4
x 4 keyboard, a last number redial can be accomplished if the
REDIP key (COL 4, ROW 1) is the first key depressed after
an on-hook to off-hook transition. Otherwise the REDIP key
will effect a 4 second pause. If the pulse mode is selected,
redial can be accomplished if the first key depressed on a
transition to off-hook is #. For the 3 x 4 keyboard, redial occurs
if the first key depressed is *,0.
The PAUSE key (COL 4, ROW 2) for the MC1454121
MC145512 will cause a 4 second pause. The PAUSEIS key
(COL 4, ROW 2) is a feature offered on the MC145413.
Depressing this key will cause a 4 second delay, and will switch
dialing modes, PAUSE (and PAUSElS) is stored in memory
for pauses (and mode switching) during auto-dialing.

MOTOROLA COMMUNICATIONS DEVICE DATA

1. MANUAL DIALING - OFF·HOOK (PULSE OF DTMF MODE)

~~~----~
ALL DIGITS ENTERED WILL BE STORED IN THE LAST NUMBER REDIAL REGISTER. PRESSING· OR # WILL DIAL OUTTHE DTMF SIGNAL IN TONE MODE ONLY.
2. MANUAL DIALING WITH AUTO ACCESS PAUSE - OFF·HOOK (PULSE OR DTMF MODE)

~ .. • .. ~IRED/pl~· . . . . ~
~

•••••

~

..... ~ c=J ~ ..... ~

~

I PAUSE I

~ ••••• ~

MCl454121MCl455120NLY
PULSEMODEONLY

THE AUTO ACCESS PAUSE WILL NOT OCCUR DURING MANUAL DIALING IN DTMF MODE. IT IS RETRIEVED DURING RECALL OR REDIAL.
3. STORING NUMBERS INTO MEMORY - ON·HOOK/OFF·HOOK (PULSE OR DTMF MODE)

~

•••••

~

I STORE I

~

A = 1-9 MEMORY ADDRESS

THIS OPERATION TRANSFERS THE DIGITS 01 TO ON FROM THE LAST NUMBER REDIAL REGISTER TO AN ADDRESS SPACE SPECIFIED BY "A". DIALING
OUTPUTS ARE NOT ACTIVATED DURING ON·HOOK PROGRAMING
4. MEMORY REDIAL - OFF·HOOK (PULSE OR DTMF MODE)
I RECALL I

~

A = 1-9 MEMORY ADDRESS

5. LAST NUMBER REDIAL - OFF·HOOK (PULSE OR DTMF MODE)
I REDIP I
OR

c=:!:J

PULSE~.oDE ONLY

REDIALS THE NUMBER THAT WAS PREVIOUSLY ENTERED INTO THE LAST NUMBER REDIAL REGISTER.
6. PULSE·TO·TONE MODE SWITCH - OFF·HOOK (PULSE OR DTMF MODE)

~

•••••

~

IPAUSE/SI

~

•••••

~

MC1454130NLY

7. CASCADED DIALING - OFF·HOOK (PULSE OR DTMF MODE)

~ ..... ~
I RECALLI

Q!J '// h

I REDIP I ' l/

h

;,///.IRECALLI

~

I RECALL I ~

I RECALL I ~

CASCADE MANUAL DIALING WITH RECALL
A = 1-9 MEMORY ADDRESS
CASCADE MEMORY RECALLS
AI, A2 = 1-9 MEMORY ADDRESSES
CASCADE LAST NUMBER REDIAL WITH MEMORY RECALL
A = 1-9 MEMORY ADDRESS

, / / / . WAIT UNTIL PREVIOUS REDIAL OR RECALL SIGNALS HAVE BEEN SENT BEFORE SUBSEQUENT ENTRIES ARE MADE.
8. SIGNALING· AND nONES - OFF·HOOK (DTMF MODE ONLy)

c=J
c=!:J
COL 1

OUTPUTS· TONE
OUTPUTS # TONE
4 X 4 KEY MATRIX
COL 2
COL3

697Hz

CQ CJ:J [IJ

COL 4
I REDIP I ROW 1

770Hz

~ ~ ~

I PAUSE I ROW 2

852Hz

~

~~

I STORE I ROW 3

941 Hz

c=:::::=J ~ c=:!:J

I RECALL I ROW 4

1209
Hz

1336
Hz

MCl45413 PAUSE/S KEY FOR PAUSE &
SWITCHING DIALING MODES

1477
Hz

Figure 2. 4 x 4 Keyboard Dialing Sequences

MOTOROLA COMMUNICATIONS DEVICE DATA

MC145412.MC145413.MC145512
2-725

1. MANUAL DIALING - OFF·HOOK (PULSE OF DTMF MODE)

~~~----~
ALL KEY ENTRIES EXCEPT' AND # WILL BE STORED IN THE LAST NUMBER REDIAL REGISTER. PRESSING' OR # WILL NOT DIAL OUT THE DTMF SIGNAL
IN TONE MODE. FOR SIGNALING, ' OR # SHOULD BE PRESSED TWICE.
2. MANUAL DIALING WITH AUTO ACCESS PAUSE - OFF·HOOK (PULSE OR DTMF MODE)

..... ~c=JC!:J~ ..... ~
~ ..... ~ LiJ ~ ..... ~ PULSEMODEONLY
~

THE AUTO ACCESS PAUSE WILL NOT OCCUR ON MANUAL DIALING IN DTMF MODE. IT IS RETRIEVED DURING RECALL OR REDIAL.
3. STORING NUMBERS INTO MEMORY - ON·HOOK (PULSE OR DTMF MODE)

~

..••. ~ c:::::J ~

A= 1-9 MEMORY ADDRESS

THIS OPERATION TRANSFERS THE DIGITS 01 TO ON FROM THE LAST NUMBER REDIAL REGISTER TO AN ADDRESS SPACE SPECIFIED BY "A".
4. MEMORY REDIAL - OFF·HOOK (PULSE OR DTMF MODE)

c:::::J ~

A= 1-9 MEMORY ADDRESS

5. LAST NUMBER REDIAL - OFF·HOOK (PULSE OR DTMF MODE)

c:::::J~
THIS OPERATION REDIALS THE LAST NUMBER ENTERED OFF·HOOK AND RETRIEVES DATA FROM MEMORY ADDRESS O.

6. PULSE·TQ..TONE MODE SWITCH - OFF·HOOK (PULSE OR DTMF MODE)

~

••••• ~ IMANUAL SWITCH I~ ••••• ~

MODE SELECT (MS) PIN HAS TO BE MANUALLY SWITCHED TO DETERMINE THE DIALING MODE. DIALING MODE SELECTION WITH MANUAL SWITCH IS
NOT PROGRAMMED INTO THE LAST NUMBER REDIAL MEMORY.
7. CASCADED DIALING - OFF·HOOK (PULSE OR DTMF MODE)

..... ~ CJc:::D
c:::::J ~ '// /. CJ ~
~

c:::::J ~ 1'/// c:::::J ~

CASCADE MANUAL DIALING WITH RECALL
A= 1-9 MEMORY ADDRESS
CASCADE MEMORY RECALLS
A1, A2 = 1-9 MEMORY ADDRESS
CASCADE LAST NUMBER REDIAL WITH MEMORY RECALL
A= 1-9 MEMORY ADDRESS

' // / " WAIT UNTIL PREVIOUS REDIAL OR RECALL SIGNALS HAVE BEEN SENT BEFORE SUBSEQUENT ENTRIES ARE MADE.
8. SIGNALING' AND # TONES - OFF-HOOK (DTMF MODE ONLy)

CJ CJ

OUTPUTS ' TONE

~~

OUTPUTS#TONE

3 x4 KEY MATRIX
COL 1
COL 2
COL 3

697Hz

~[2JGJ

ROW 1

770Hz

~~~

ROW 2

852Hz

[2J~~

ROW 3

941 Hz

c:::::J ~ CU

ROW 4

1209
Hz

1336
Hz

1477
Hz

Figure 3. 3 x 4 Keyboard Dialing Sequences

MC145412.MC145413.MC145512
2-726

MOTOROLA COMMUNICATIONS DEVICE DATA

HOOKSWITCH 1t-'0:;,.F;.,.;F.H""o""oK"--_ _ _ _ _ _ _ _ _.....1 oN.HOOKL..1_ _ _ _ _ _ _ _ _ _ __
KEYINPUTS

~

DIGIT '2" 1

1 DIGIT't" 1 " " 1 - - - - - - , 1

REDIAL . - 1 - - - - - - - - -

I
I
I
(PULSED~:~ ~I~I '"" ~I

Innn nnnn

3::::D~:L~

\C

T50

1

I

I
1

OSCILJION

1250HZ

i

I

I

:)

~'----------

COL.5CAN~ROW5CAN

PULSE MODE

1

I

1--1 ~ tD~d I

1-

OSCILLATION

}-

-----lJ1.r

----JUL

I
r---;-!l---r-;

OPL

DTMFMODE
DTMFOUT

Figure 4. Timing Diagram

MOTOROLA COMMUNICATIONS DEVICE DATA

MC145412.MC145413.MC145512
2-727

_

MOTOROLA

SEMICONDUCTOR
TECHNICAL DATA

MC145414

Dual Tunable Low-Pass
Sampled Data Filters
The MC145414 is sampled data, switched capacitorfilter IC intended to provide
band limiting and signal restoration filtering. It is capable of operating from either
a single or split power supply and can be powered-down when not in use. Included
on the IC are two totally uncommitted op amps for use elsewhere in the system
as I-to-V converters, gain adjust buffers, etc.
•
•
•
•
•
•
•
•

Two General Purpose 5th Order Elliptic Low-Pass Filters
Low Operating Power Consumption - 30 mW (Typical)
Power Down Capability - 1 mW (Maximum)
±5 to ±8 V Power Supply Ranges
TTL or CMOS Compatible Inputs Using VLS Pin
Two Operational Amplifiers Available to Reduce Component Count
Useful in LPC or CVSD Speech Applications
Passband Edges Tunable With Clock Frequency From 1.25 kHz to 10kHz

-,.

PSUFFIX

PLASTIC
CASE 648

PIN ASSIGNMENT
VAG
+A

1-

16

2

15

Aln

14

-A

NOT
RECOMM NDED
FOR NEW DESIGN

LSUFFIX

CERAMIC
CASE 620

VOO

13

Aout
Bin

BO

12

Bout

-B

11

CLKI

AO

4

+B

7

VSS

8

10

CLK2
VLS

ORDERING INFORMATION
MC145414

Suffix Denotes
L Ceramic Package
P Plastic Package

1=

BLOCK DIAGRAM

~~
AO~

Aout

~~~

+B--{;,/
Bin -~----M-I

Bout

CLOCK 1
VOO ------r--==--,_r.:=-=~_ CLOCK2
VSS
VLS

MC145414
2-728

MOTOROLA COMMUNICATIONS DEVICE DATA

MOTOROLA

-

SEMICONDUCTOR
TECHNICAL DATA

MC145415

Dual Tunable Linear Phase
Low-Pass Sampled Data Filters
The MC145415 is sampled data, switched capacitor filter IC intended to provide
band limiting and signal restoration filtering. It is capable of operating from either
a single or split power supply and can be powered-down when not in use. Included
on the IC are two uncommitted comparators for use elsewhere in the system.
• Two Linear Phase, 5th Order Low-Pass Filters
• Low Operating Power Consumption - 20 mW (Typical)
• ± 2.5 to ± 8 V Power Supply Ranges
• CMOS Compatible Inputs Using VDG Pin
• Two Comparators Available to Reduce Component Count
• Useful in High Speed Data Modem Applications
• Pass-Band Edges Tunable With Clock Frequency from 1.25 kHz to 10kHz

NOT RECOMMENDED
FOR NEW DESIGN
BLOCK DIAGRAM

14
10
loop

Aout
ClK

VAG
13

Bout

-B

B0

_

B

5

A

3

--A
4 AO

VOG =PIN9
VOO= PIN 16
VSS=PIN B

MOTOROLA COMMUNICATIONS DEVICE DATA

LSUFFIX
CERAMIC
CASE 620

PSUFFIX
PLASTIC
CASE 648

PIN ASSIGNMENT

0
0
0

VOO

0
0

Boul

1-

16

2

15

-A

3

14

AD

4

Aoul
13 ] Bin

Ain

BO

5

12

-B

6

11

+B

7

10 ~ ClK

Vss

B

9

loop

VOG

ORDERING INFORMATION

MC145415 tSUffiX Denotes
L

Ceramic Package

P

Plastic Package

Bin

+B~+ ~2+A
6

~uu
}ltfrfJMfl

This device contains circuilry 10 protect the
inputs against damage due to high static voltages or electric fields; however, it is advised
that normal precautions be taken to avoid
application of any voltage higher than maximum rated voltages to this high impedance circuit. For proper operation it is recommended
that Vin and Vout be constrained to the range
VSS:S; (Vin or Vout) :s; VOO.
Unused inpuls must always be tied to an appropriate logic voltage level (e.g., either VSS or
VOO)·

MC145415

2-729

-

~OTOROLA

SEMICONDUCTOR
TECHNICAL DATA

MC145416
Tone/Pulse Dialer with
10 Number Memory
Plus 3 Emergency Numbers
Low-Power, Silicon-Gate CMOS
The MC145416 is a member of lhe Motorola HCMOS dialer family. In addition
to the necessary basic features of pulse, tone, or mixed dialing, and lOx 18 digit
memories inclusive of LNR, it provides the advanced features of flash, 3 x 18
dedicated memories, Signal output inhibited during memory storage, note pad
programming, and convenient operation sequence by 5 x 4 keyboard interface.
The power-on memory reset has the highest priority if the voltage drops below
the minimum voltage level, regardless of hook switch status, to ensure no wrong
data in memory content.
The pin·out is compatible with other members of dialer family except the
additional two pins at one end of the device (pins 1 and 20).
Options: MC145416-1 40/60 make-break ratio with indefinite pause
MC145416-2 33/67 make-break ratio with 4-ms pause
The MC145416 offers the following performance features:
• Stand-Alone Pulse, DTMF, or Mixed Dialing
• Pacifier Tone Output at Pulse Dialing
• Dialing Mode, Pin Selectable, and Changed by Keyboard Entry
• Uses Low Cost 3.57954-MHz TV Color Burst Crystal
• PABX Pause Storage
• Cascaded Memory Redial and Dialing Mode Storage
• Dialing Mode Indication Output for Driving an LED
• lOx 8 Digit Memory Storage Inclusive of LNR plus 3 x 8 Digit Dedicated
Memory
• 40/60 Make Break Ratio, 33167 in Metal Option #
• Flash Function for Transfer Call in a PABX Environment

.-

PSUFFIX
PLASTIC
CASE 738
OW SUFFIX

SOG
CASE 751D

PIN ASSIGNMENT
1·

20

Rl

2

19

OTMFOUT

C4

3

18

PO

Cl

4

17

R2

C2

5

16

R3

C3

6

15

R4
R5

MI
VOO

VSS

7

14

PTO

8

13

HS

XI

9

12

MO

11

MS

X2 [ 10

BLOCK DIAGRAM
TO----;
OTO
MI------ir-----,
MS _ _ _ _-+_---,

.,..

Cl
C2
C3
C4

Rl
R2
R3

R4
R5

PULSE
ANOMUTE
OUTPUT
LOGIC

9"
~

PO

MO

HS---+----~

MC145416

2-730

MOTOROLA COMMUNICATIONS DEVICE DATA

ABSOLUTE MAXIMUM RATING (Voltages referenced to GNO, except where noted)
Rating

Symbol

DC Supply Voltage
Input Voltage (All Pins)
DC Current Drain per Pin
Power Dissipation
Operating Temperature Range
Storage Temperature Range

Value

Unit

VOO

-0.5 to +8.0

V

Vin

-0.5 to VOO +0.5

V

I

±10

mAdc

Pd

30

mW

TA

-30 to +70

DC

-40to+150

DC

Tstg

This device contains circuitry to protect the inputs against damaga due to high static voltages
or electrical fields; however, it is advised that
normal precautions be taken to avoid applications of any voltage higher than the maximum
rated voltages to this high Impedance circuit.
For proper operation it Is recommended that Vin
and Vout be constrained to the range VSSS(Vin
or Vout) S VOO. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., eitherVSS orVOO).

ELECTRICAL CHARACTERISTICS (All polarities referenced to VSS = 0 V, VOO = 2.5 V, Unless Otherwise Noted)
Symbol

Min

Typ

Max

Unit

Pulse Mode
OTMFMode

VOO

2.0
2.5

-

6
6

V

Pulse Mode (VOO = 1.7 V)
OTMF MODE (VOO = 2.5 V)

100

-

200
0.5

500
2.0

rnA

-

Parameter
DC Supply Voltage
Supply Current
Memory Retention Voltage (On-Hook)

Vstby

1.7

(VOO=2.5V)
(VOO= 1.7V)

Istby

-

Input Voltage "0" Level
"l"Level

VIL
VIH

Row/Column Input Impedance
(Pins 3, 4, 5, 6,14,15,16,17,20)

ToVOO
ToVSS

Rin

Mode Select Input Impedance (Pin 11)

ToVOO
ToVSS

Rin

Memory Retention Current (On-Hook)
Row/Column (Pins 3, 4, 5, 6,14,15,16,17,20)

0.8xVOO

0.05

-

I1A

-

V

2.5
2.0

I1A

0.2xVOO

V

100
5

-

100
100

-

50

-

kQ

-

100

J!A

OH Pull-Up Resistance (Pin 13)

R

Input Current MS, HS (Pins 11, 13)

lin

-

IOL
IOL
IOH

0.5
1.0
0.25

1.0
2.0
1.5

-

rnA

Output Leakage Current (Pins 12, 18)

loul

1.0

I1A

Cln

-

-

Input Capacitance (All Pins)

10

-

pF

Vo

260
327

309
389

367
462

mVrms

-

-

-80

dBm

5

7

%

Db

1.5

-

3.0

dB

VIDC

-10%

1/2 VOO

+10%

Output Sink Current (VO = 0.5 V)

OTO Output Tone Level (Pin 19)
. OTO Output Tone Leakage (Pin 19)

MO(Pln 12)
PO (Pin 18)
MI (Pin 1)

Row Tone (RL = 600 Q to VOO)
Column Tone (VOO = 3.5 V)
(VOO = 3.5 V, RL = 600 Q)

°bm

OTO Output Tone Distortion (Pin 19)
(300 Hz-4 kHz, VOO = 3.5 V, RL = 600 Q)
Output Ratio Column/Row Tone
(Pins 3, 4, 5, 6,14,15,16,17,20)
OTO DC Level (Pin 19)

MOTOROLA COMMUNICATIONS DEVICE DATA

VOO=3.5V

-

kQ
kQ

MC145416
2-731

SWITCHING CHARACTERISTICS (VOO - 2 5 V CL - 50 pF tA = 25°C)
Characteristic

Symbol

Row/Column Scan Frequency

Min

f

Key Oebounce lime

tOB

HS Reset lime

-

tR

OTOOuration

Normal
Redial

too

Flash Output Duration

tFO

OTO Interdigit Duration (Normal and Redial)

tID

80
80

Typ

Hz
ms

160

ms

-

ms

-

ms

40

ms

800

tpop

-

Pacifier Tone Duration

'Tso

30

tlOP
MBR

-

800

42158

40/60

tMO

MO Output Predigit (Pulse Mode)

tMOP
tp

PIN DESCRIPTIONS
VDD
Positive Power Supply (Pin 2)
The digital supply pin is connected to the positive side of
the system power supply.
VSS
Ground (Pin 7)
Ground retum pin is typically connected to the system
ground.
MS
Mode Select (Pin 11)
This is a three-state input. A logic 0 selects Tone mode, a
log'ic 1 selects the Pulse mode at 20 pps, and an open
connection selects Pulse mode at 10 pps. If the input is
changed while dialing is in progress, the mode change will
occur afterlhe last interdigit pause for the previous dial mode.
PTO
Pacifier Tone Output (Pin 8)
Recognition of any valid key input in Pulse mode will cause
an 800-Hz square wave to be output from this pin. The
minimum output time is 30 ms or as long as valid key
depression lasts. This pin is high impedance when no signal
is output.
HS
Hook Status (Pin 13)
A logic 1 or open condition sets the device on on-hook
status. A logic 0 is an off-hook condition.
PO
Pulse and Flash Output (Pin 18)
This is an N-channel open-drain output. It outputs dialing
pulses at a 10-pps or 20-pps rate. The flash output from this
pin is a 600-ms pulse. This pin is high impedance when no
signal is output.
MO
Mute Output (Pin 12)
This is an N-channel open-drain output. In the manual tone
dialing mode this output goes low for the period of the tone

MC145416

2·732

Hz
ms
ms
37/63

%

33167

MO Overlap (Pulse Mode/Redial)
Pause

ms

60

!Tso

(P/OW)
(P2iDW2)

-

600

Pacifier Tone Frequency
Pulse Interdigit Duration

Unit

12t026

MO Output Predeigit (OTMF Mode)

Make/Break

Max

250

-

800

ms

40
3

-

ms
5

s

duration. It will remain low until the end of the mute overlap
time.
In manual pulse dialing, this output will go low for the period
of break and make time, and will remain low until completion
of the mute overlap time.
When redialing from LNR, or memory, this pin will go low
starting with first digit signal output with predigit period, and
will remain low until the last digit is output plus the overlap
mute period. This pin remains high (1) during memory store.
R1-R5/C1-C4
Row/Column Inputs (Pins 3~, 14-17, and 20)
A logic 0 simultaneously presented to a single row and a
single column is defined as a valid key entry. The keypad starts
to be sampled and the input accepted if it is still valid aller
12 to 26 ms debounce time. Depression of multiple keys is
an invalid entry.
X11X2
OSCIN and OSCOUT (Pins 9 and 10)
An inverter works as an on-board oscillator when
connected to a parallel mode 3.5795-MHz crystal. The frequency accuracy of the crystal directly affects the accuracy
of the DTMF frequency. Crystal biasing is accomplished by
an intemal resistor and capacitors.
DTO
DTMF Output (Pin 19)
When the MS pin is set to a logic 0 (VSS) the DTMF output
pin will output tones corresponding to the row and column
of the key depressed. The tone out duration will last as long
as a valid key is pressed, with a minimum of 80 ms
guaranteed.
In LNR the tone output and interdigit pause are of a fixed
duration. When the MS pin is logic 1 or open for pulse dialing,
the DTO pin is high impedance.
MI
Mode Indicator Output (Pin 1)
This pin will be at a logic 0 when dialing in the DTMF mode
and a logic 1 when dialing in the Pulse mode. The pin remains
in the logic state determined by the last dial mode.

MOTOROLA COMMUNICATIONS DEVICE DATA

OPERATIONAL INFORMATION
The MC145416 allows the use of either a single contact
(Class A) keyboard, or a standard 2-of-8 keyboard with VSS
tied to common. A valid key entry occurs when either a single
row is tied to a single column or a single row and column are
simultaneously connected to VSS.
Figure 1 illustrates the two types of keying methods.
Figure 2 illustrates the 4 x 5 functional keyboard layout and
the standard row and column frequencies.

COLI

697
ROW

770

FREQ.
852

CLASS A
941
COL - - 0

0--

COL2

COL3

COL4

000~
~00~
~00~

~00IFLASHI
D0~ILNFVPSI
1209

ROW

1336

ROW 1
ROW 2
ROW 3
ROW 4
ROW 5

1477

COLUMN FREQ.
STANDARD 2·0F·8

vSS

-Cl~o--COL

MR
MS
PSIS
FLASH
LNRlPS

= MEMORY RECALL
= MEMORY STORE
= MODE CHANGE/PAUSE
= 600 ms at PO PIN
= LAST NUMBER REDIALIPAUSE

o--ROW

Figure 1. Keyboard Configurations

MOTOROLA COMMUNICATIONS DEVICE DATA

Figure 2. 4 x 5 Keyboard Matrix

MC145416

2-733

FUNCTIONAL INFORMATION
A.

MANUALDIALING-OFF·HOO~ ~----~

1) Dialing Tone (DTMF) output will oontinue as long as a valid key is depressed.
2) Mode change can be set on· or off-hook before keyboard enby.
3) In Tone Mode
a) All digits, including' and #, will have DTMF output.
b) All digits, including' and #, and Pause will be stored in the LNR register.
c) Flash, PSIS, MS (Memory Store), and MR (Memory Recall) will cause a PTO output to be generated as long as a key remains pressed.
4) In Pulse Mode (10 or20pps)
a) Numeric Input 0-9, Pause, and PSIS will be stored in the LNR register.
b) Numeric inputs 0-9, • and #, Flash, LNR, PSIS, MS, and MR will cause a PTO output to be generated for as long as the key remains pressed.

I

B. LAST NUMBER REDIAL - OFF·HOOK LNRlPS

I

1) When this is the first key depressed after off·hook, exluding Mode Select Switch, It causes the last number entered from the keypad to be dialed out.
2) Mixed dialing from the keypad can be stored and redialed with pulse to tone mixed dial out or can be converted to all tone wHh the Mode Select Switch,
retaining the four second pause.
ENTERED ...
Mode Select Switch to Pulse Mode, ENTER:
~
~
~

..... Q:J

PULSE INPUT
REDIALED ...
ON·HOOK to OFF·HOOK
Mode Select Switch In Pulse Mode, ENTER:
REDIALED •.•
ON·HOOK to OFF·HOOK
Mode Select Switch in Tone Mode, ENTER:

ILNRlPS'

Q:J .....

I

I

MODE
Change With Pause

DTMF INPUT

',Dial out Is the same as original entry.

, LNRlPS , ' Dial out changes to:

~

Q:J ..... ~

..... Q:J

DTMF OUTPUT

I

PAUSE

I

DTMF OUTPUT

3) Numbers dialed from memory 1-9, and Nl, N2, and N3 will not be stored in the LNR register.
4) Numbers stored with the MS pin set to DTMF cannot be converted to pulse with the PSIS key because the part does not know to go to 10 or 20 pps.
C. DIALING WITH AUTO ACCESS PAUSE - OFF·HOOK
ENTERED ...
Mode SwHch in either Pulse or Tone Mode
REDIALED ...
ON·HOOK to OFF·HOOK
Mode Select Switch Unchanged, ENTER:

~

..... Q:J

ILNRlPS'

Q:J ..... ~

, LNR/PS , ' Dial out is the same as original entry.

~

..... Q:J

PAUSE

Q:J ..... ~

1) A pause Is stored In a data number sequence by prassing the LNRlPS key during keypad entry.
2) More than one pause can be entered in sequence for extended pauses.
3) An Indefinite pause duration can be provided with a custom metal option.
a) The indefinite pause will not occur during normal tone or pulse dialing.
b) On redial, this pause can be terminated by pressing any other key,
D. DIALING WITH AUTO ACCESS PAUSE AND MODE CHANGE - OFF·HOOK
ENTERED ...
Mode Select Switch in Pulse Mode (10 or 20 pps)

~

..... Q:J

PULSE DIALING
ENTERED ...
Mode Switch In Tone Mode

~

Q:J ..... ~
I

MODE
Change WHh Pause

..... Q:J

TONE DIALING

~

I

I

~

TONE DIALING

Q:J ..... ~
I

PAUSE
Change With Pause

TONE DIALING

1) Dialing in the Pulse Mode and depressing the PSIS key will inHiate a four second auto access pause with the mode change to DTMF.
2) Starting in the Tone Mode, depressing the PSIS key will not cause a mode change to occur, but will Insert a four second pause in the dial sequence,

MC145416

2-734

MOTOROLA COMMUNICATIONS DEVICE DATA

E. MEMORY STORAGE AND RECALL - OFF·HOOK
1) A 10tal of 18 digHs can be stored.
2) Pause and Mode Switch (PSIS) key each count as one digit.
3) After pressing MS (Memory Store) key, all outputs are InhlbHed except the PTO output. Succeeding numeric inputs including PSIS, are counted as data. Following
the second MS (Memory Store) key input, the first numeric Input Is counted as address (A= 1-9 orNl, N2, or N3). Any non·numeric key entered, including 0, will be
Ignored, and the part will walt for another entry.
ENTERED ...
a) Mode Select Switch in Pulse Mode (10 or 20 pps)
Memory Store Sequence ...

[§J~····0~0····[§J[§J0
PULSE MODE
A=I-9
I MODE I TONE MODE
orNl, N2, N3

Change With Pause
ON·HOOK to OFF·HOOK ENTERED ...
Memory Recall Sequence ...

~

0

A=I-9 Dialoutis:

~

••••

0

PULSE MODE
b) Mode Select Switch to DTMF
Memory Recall Sequence ...

~

0

A=I-9 Dialoutis:

~

••••

I

MODE
Change Wrth Pause

0

TONE MODE
ENTERED ...
a) Mode Select Switch In Tone Mode
Memory Store Sequence ...

0···· [§J

I

I

0···· [§J

PAUSE

I

~

0

A=I-9 Dial out Is:

~

••••

orNl,N2,N3

0

TONE MODE
b) Mode Select Switch in Pulse Mode (10 or 20 pps)

~

MemoryRecaIiSequence...

TONE MODE

[§J~····0~0····[§J[§J0
TONE MODE
A=I-9
I PAUSE I TONE MODE
Change With Pause

ON·HOOK to OFF·HOOK ENTERED ...
Memory Recall Sequence ...

TONE MODE

0

A=I-9 Dial out is:

~ ••••

I

0

PULSE MODE

I

0···· [§J

PAUSE

I

TONE MODE

0···· [§J

I

MODE
Change With Pause

TONE MODE

4) Number storage during conversation is allowed by following the above procedure.
5) Memory registers can be programmed sequentially wHhout going on-hook between each entry.
F. CASCADED DIALING - OFF·HOOK
1) Memory Cascaded ...
a) Numbers stored with the Mode Select Switch set to pulse (10 or 20 pps) can be dialed out as follows:
ENTERED...

~

[§J

ENTERED ...

~

IPSIS I [§J

Nl will dial out as stored, N2 will convert to DTMF.
PTO output will remain active during the dial out of N2.

ENTERED ...

IPSIS I ~ [§J

Both Nl and N2 will dial out in DTMF, wHh PTO active.

Both Nl and N2 will dial out as originally stored.

b) Numbers stored wHh the Mode Select Switch set to pulse (10 or 20 pps) can also be dialed out In DTMF by swHchlng the Mode Select Switch to the Tone Mode,
on· or off-hook. By using the Mode Select SwHch instead of PSIS, PTO will not be active. A dial out conversion back to pulse cannot be accomplished with the
use of PSIS when the Mode Select SwHch is in the Tone Mode.
c) In cascade operation, the keyboard is InhibHed upon pressing the first key (i.e., Nl key). The out pulsing must be completed before acceptance of the next key
input.
2) Cascade dialing can be accomplished from any memory location in any order, including LNR ...
a) Numbers stored with the Mode Select SwHch set to pulse (10 or 20 pps)

0

ENTERED...

~

ENTERED ...

~ ~

~ Both MR Aand LNR dial out in pulse.

0

Both LNR and MR A dial out in pulse

b) Since a redial from any memory location will not distrub the content of the LNR register, it is not necessary to re-enter the last dialed number again.
c) In cascade operation, the keyboard is inhibHed upon pressing the first control key (I.e., MR key). The out pulsing must be completed before acceptance of the
next control key input.
3) The second control key, or number Input, has to be entered after completion of the previous dialing.
G. FLASH -OFF·HOOK

~

1) Press\ng the FLH key will cause a 600-ms pulse to be generated at the pulse output pin. This pulse will not be stored in eHherthe LNR register or the memory
registers. The mute output will go low for 600 ms and the PTO output will be active for as long as this key is depressed.

MOTOROLA COMMUNICATIONS DEVICE DATA

MC145416

2-735

HOOK SWITCH

KEY INPUTS

3.58 MHz

~

______________~Il~__________

lOFF.HOOK

I

DIGIT?

--<

DIGIT'l"

PACIFIER

MO

--1JIII
I I-I

PO

REDIAL

)~-----1( ·OSCILLATION

OSCILLATION

PULSE MODE

I

•

)~---

~--~IU~-------

trsOH

I
lMOP

U

-I I-

,..---------,

tMOP

800msH

.-------,

TONE MODE
PACIFIER

MO

I

---II

L - -_ _ _ _ _ _

-I

I-

DTMFOUT

Figure 3. Timing Diagram

MC145416
2-736

MOTOROLA COMMUNICATIONS DEVICE DATA

MOTOROLA

-

SEMICONDUCTOR
TECHNICAL DATA

MC145421
MC145425

Advance Information

ISDN Universal Digital Loop
Transceivers II
(UDLT II)
The MC145421 and MC145425 UDLTs are high-speed data transceivers
capable of providing 160 kbps full-duplex data communication over 26 AWG and
larger twisted-pair cable up to 1 km in length. These devices are primarily used
in digital subscriber voice and data telephone systems. In addition, the devices
meet and exceed the CCITT recommendations for data transfer rates of ISDNs
on a single twisted pair. The devices utilize a 512 kbaud MDPSK burst modulation
technique to supply the 160 kbps full-duplex data transfer rates. The 160 kbps
rate is provided through four channels. There are two B channels, which are 64
kbps each. In addition, there are two D channels which are 16 kbps each.
The MC145421 and MC145425 UDLTs are designed for upward compatibility
with the existing MC145422 and MC145426 80 kbps UDLTs, as well as compatibility with existing and evolving telephone switching hardware and software
architectures.
The MC145421 (MASTER) UDLT is designed for use at the telephone switch
line card while the MC145425 (SLAVE) UDLT is designed for use at the remote
digital telset or data terminal.
• Employs CMOS Technology, in Order to Take Advantage of Its Proven Capability for Complex Analog and Digital LSI Functions
• Provides Synchronous Full Duplex 160 kbps Voice and Data Communication
in a 2B+2D Format for ISDN Compatibility
• Provides the CCITT Basic Access Data Transfer Rate (2B+D) for ISDNs on a
Single Twisted Pair up to 1 km
• Compatible with Existing and Evolving Telephone Switch Architectures and
Call Signalling Schemes
• Protocol Independent
• Single +5 V Power Supply

R
FO

16 kbps 01
16 kbps 02
64kbps B1
64kbps B2

N
MMEND D
NEW DESIGN

SLAVE
ISDNUDLT

MASTER
ISDN UDLT
160 kbps FULL·DUPLEX
DATA TRANSMISSION

PSUFFIX
PLASTIC
CASE 709

24~

SOG
CASE 751F

PIN ASSIGNMENT
MC145421- Master
(Plastic and SOG Packages)
VSS

VDD

LI

L02

[8

Rx

VD

RE2

L01

011

RE1
TOc/RDC

DCLK

CCI

010

MSI

020

TE1

SE

TE2

PO

Tx

MC145425-Slave
(Plastic and SOG Packages)
VSS

16 kbps 01
16 kbps 02
64kbps B1
64kbps B2

VDD

Vrel

L01

LI

L02

[8

Rx

VD

BCLK

011

CLKOUT

021

XTL

DCLK

CCI

010

TONE

020

EN1

MulA

EN2

PO

MOTOROLA COMMUNICATIONS DEVICE DATA

DWSUFFIX

Tx

MC145421.MC145425
2-737

MOTOROLA

-

SEMICONDUCTOR
TECHNICAL DATA

MC145422
MC145426

Advance Information

Universal Digital-Loop
Transceivers (UDLT)
The MC145422 and MC145426 UDLTs are high-speed data transceivers that
provide 80-kbps full-duplex data communication over 26 AWG and larger twisted
pair cable up to two kilometers in distance. Intended primarily for use in digital
subscriber voice/data telephone systems, these devices can also be used In
remote data acquisition and control systems. These devices utilize a 256 kilobaud
modified differential phase shift keying burst modulation technique for transmission to minimize RFI/EMI and crosstalk. Simultaneous power distribution and
duplex data communication can be obtained using a single twisted pair wire.
These devices are designed for compatibility with existing, as well as evolving,
telephone switching hardware and software architectures.
The UDLT chip-set consists of the MC145422 master UDLT for use at the
telephone switch linecard and the MC145426 slave UDLT for use at the remote
digital telset and/or data terminal.
The devices employ CMOS technology in order to take advantage of its reliable
low-power operation and proven capability for complex analog/digital LSI
functions.

PSUFFIX
PLASTIC
CASE70B

OW SUFFIX
SOG
CASE 751E

ORDERING INFORMATION
MC145422P, MC145426P
MC145422DW, MC145426DW

Plastic
SOG

• Provides Full Duplex Synchronous 64 kpbs Voice/Data Channel and Two
8 kbps Signaling Data Channels Over One 26 AWG Wire Pair Up to
Two Kilometers
• Compatible with Existing and Evolving Telephone Switch Architectures and
Call Signaling Schemes
• Automatic Detection Threshold Adjustment for Optimum Performance Over
Varying Signal Attenuations
• Protocol Independent
• Single 5 V Power Supply
• 22-Pin Package
• Application Notes AN943, AN949, AN968, AN946, and AN948
MC145422 Master UDLT

NOT
RECOMMENDED
FOR NEW DESIGN

• Pin Controlled Power-Down and Loop-Back Features
• Signaling and Control I/O Capable of Sharing Common Bus Wiring with
Other UDLTs
• Variable Data Clock - 64 kHz to 2.56 MHz
• Pin Controlled Insertion/Extraction of 8 kbps Channel Into LSB of 64 kbps
Channel for Simultaneous Routing of Voice and Data Through PCM Voice
Path of Telephone Switch
.
MC145426 Slave UDLT
•
•
•
•
•

Compatible with MC145500 Series PCM Codec-Filters
Pin Controlled Loop-Back Feature
Automatic Power-Up/Down Feature
On-Chip Data Clock Recovery and Generation
Pin Controlled 500 Hz D3 or CCITT Format PCM Tone Generator for Audi
ble Feedback Applications

This document contains infonnation on a new product. Specifications and In!onnatlon herein are subject to change without notice.

MC145422.MC145426
2-738

MOTOROLA COMMUNICATIONS DEVICE DATA

MOTOROLA

-

SEMICONDUCTOR
TECHNICAL DATA

MC145428
Data Set Interface
Asynchronous-to-Synchronous and
Synchronous-to-Asynchronous Converter

LSUFFIX
CERAMIC,
CASE 732

The MC145428 Data Set Interface provides asynchronous-to-synchronous and
synchronous-to-asynchronous data conversion. It is ideally suited for voice/data
digital telsets supplying an EIA-232 compatible data port into a synchronous
transmission link. Other applications include: data multiplexers, concentrators,
data-only switching, and PBX-based local area networks. This low-power CMOS
device directly interfaces with either the 64 kbps or 8 kbps channel of Motorola's
MC145422 and MC145426 Universal Digital Loop Transceivers (UDLTs), as well
as the MC145421 and MC145425 Second Generation Universal Digital Loop
Transceivers (UDLT II).
• Provides the Interface Between Asynchronous Data Ports and Synchronous
Transmission Links
• Up to 128 kbps Asynchronous Data Rate Operation
• Up to 2.1 Mbps Synchronous Data Rate Operation
• On-Board Bit Rate Clock Generator with Pin Selectable Bit Rates of 300,
1200, 2400, 4800, 9600, 19200, and 38400 bps or an Externally Supplied
16 Times Bit Rate Clock
• Accepts Asynchronous Data Words of 8 or 9 Bits in Length
• False Start Detection Provided
• Automatic Sync Insertion and Checking
• Single 5 V Power Supply
• Low Power Consumption of 5 mW Typical
• Application Notes AN943 and AN946

PSUFFIX
PLASTIC
CASE 738

DWSUFFIX

SOG
CASE 751D

PIN ASSIGNMENT
TxS

VDD

TxD

RESET

DL
BRCLK

DCO
DOE
CM

BRl

ECOMMENDED
DESIGN

DCLK
DIE

8R3

DCI

SB

RxS

VSS

RxD

BLOCK DIAGRAM
TxS.-------------,
TxD---+j

DCO

DL-HL;::J

.-----It........l_ _ _ _ _-'--_...,..~ DOE

BR1-BR3
BCLK
BRCLK.----t

DIE

DCLK
~-,~-_r----~r-~~--CM
RESET

RxD+-----I
SB

DCI

RxS.--------------...J

MOTOROLA COMMUNICATIONS DEVICE DATA

MC145428

2-739

MOTOROLA

-

SEMICONDUCTOR
TECHNICAL DATA

MC145429

Telset Audio Interface Circuit
The MCl45429 is a silicon-gate CMOS Telset Audio Interface Circuit (TAlC)
intended for microcomputer controlled digital or analog telset applications. The
device provides the interface between a codeclfilter or analog speech network
and the telset mouthpiece, earpiece, ringer/speaker amplifier, and an auxiliary
input and output. The configuration of the device is programmed via a serial digital
data port. Features provided on the device Include:
•
•
•
•
•
•
•
•
•
•
•
•
•

Independent Adjustment of Earpiece, Speaker, and Ringer Volume
Transient Suppression Circuitry to Prevent Acoustic "Pops·
Receive Low-Pass Filter for 8-kHz Attenuation
Sixteen Possible Audio Configurations
Power-Down Mode with Data Retention
20-dB Mouthpiece Input Gain
Receive to Transmit Loopback Test Mode
Provision for Auxiliary Input and Output
Externally Adjustable Auxiliary Input Gain
PCM Mono-Circuit Compatible Power Supply
Digital Output for Speaker Amplifier Control
Versatile Logic Input Levels·
18-Pin Package

NOT RECOMMENDED
FOR NEW DESIGN

-,p

PSUFFIX
PLASTIC
CASE 707

1

LSUFFIX
CERAMIC
CASE 726

PIN ASSIGNMENT
VAG [ 1-

18

VDG [ 2

17

SAE[ 3

P VDD

PTxO
16 P Mpl

DCE [ 4

15

P EpO

DC [ 5

14

PSO

D[ 6

13

SCI [ 7

12

pAxO
P AxF

PDi[ 8

11

VSS [ 9

10

P-Ax
PRxl

SIMPLIFIED BLOCK DIAGRAM
LOW·PASS
FILTER

VDD=PIN 18
VAG=PIN 1
VDG=PIN2
VSS=PIN 9

AxO
Mpl
o---+-VAG
TRANSMIT
SIGNAL
SELECTOR

DCE ---=----~
DC~----~

DIGITAL CONTROL LOGIC

D --""----+1
This document contains information on a new product. SpecHlcatlons and Information herain ara sublect to change without notice.

MC145429
2-740

MOTOROLA COMMUNICATIONS DEVICE DATA

MOTOROLA

-

SEMICONDUCTOR
TECHNICAL DATA

MC145432

2600 Hz Tone Signaling Filter
This device contains a bypassable 6-pole, 2600 Hz notch filter, a 2-pole
2600 Hz band-pass filter, and a 2600 Hz sine wave generator for SF signaling!
detection applications.

LSUFFIX
CERAMIC
CASE 726

• ±5 V to ±8 V Single or Split Supply Operation
• Low Power Consumption: 80 mW @ 10 V
200mW@ l5V
• On-Board Crystal Oscillator or External Clocks
• Notch Filter Gain Adjustable
• Uncommitted Op Amp Capable of Driving 600 n Loads
• TTL or CMOS Compatible Inputs
• l8-Pin Package

.-

PSUFFIX
PLASTIC
CASE 707

PIN ASSIGNMENT
VDD

NOT
RECOMMENDED
FO NEW DESIGN

B+

BO

BBPO
TO
NE
CO

BLOCK DIAGRAM

VLS

AO
4

2600·Hz
6·POLE
NOTCH FILTER

L..-_ _ _.;..3

A-

~:
~·B-

L..-_ _ _ _ _.;:,.5 NO

CLOCK
CIRCUIT
2600·Hz
SINE WAVE
GENERATOR

2600·Hz
2-POLE
BAND-PASS
FILTER

TO

BPO

VDD~PIN

18

VAG~PIN1
VSS~

PINg

14
CS

..:.6_ _ _ _-'

MOTOROLA COMMUNICATIONS DEVICE DATA

MC145432
2-741

MOTOROLA

-

SEMICONDUCTOR
TECHNICAL DATA

MC145436

Dual Tone Multiple Frequency
Receiver
The MC145436 is a silicon gate CMOS LSI device containing the filter and
decoder for detection of a pair of tones conforming to the DTMF standard with
outputs in hexadecimal. Switched capacitor filter technology is used together with
digital circuitry forthe timing control and output circuits. The MC145436 provides
excellent power line noise and dial tone rejection and is suitable for applications
in central office equipment, PABX, and keyphone systems, remote control
equipment and consumer telephony products.
The MC145436 offers the following performance features:
•
•
•
•
•
•
•

PSUFFIX
PLASTIC
CASE 646

OW SUFFIX
SOG
CASE 751G

Single + 5 V Power Supply
Detects All 16 Standard Digits
Uses Inexpensive 3.58-MHz Crystal
Provides Guard Time Controls to Improve Speech Immunity
Output in 4-Bit Hexadecimal Code
Built-in 60 Hz and Dial Tone Rejection
Pin Compatible with SSI-204

PIN ASSIGNMENTS
PLASTIC
02 [ 1-

14

04

01 [ 2

13

08

ENB [ 3

12

OV

VOO [ 4
GT [ 5

11

ATB

10

Xin

[ 6

9

Xout

Ain [ 7

8

GNO

Xen

SOG

BLOCK DIAGRAM
02

04

08

OV
NC

GT

ATB

TIMING
CIRCUIT

11

OV

Xin

Xout
Ain

8_ _ _-, GNO

1..

NC = NO CONNECTION
OUTPUT
DECODER
ENB
01

ATB

+-----------.

Xen

Xin
Xout

MC145436
2·742

02

04

08

MOTOROLA COMMUNICATIONS DEVICE DATA

MAXIMUM RATINGS (Voltages Referenced to GNO Unless Otherwise Noted)
Rating

Symbol

DC Supply Voltage

Value

Unit

VOO

-0.510+6.0

V

Input Voltage, Any Pin Except Ain

Vln

-0.5toVOD+0.5

V

Input Voltage, Ain

Yin

VOO-l010VOO+0.5

V

I

±10

mAdc

Po

30

mW

.OC Current Drain per Pin
Power Dissipation
Operating Temperature Range

TA

-4010+85

·C

Storage Temperature Range

Tsm

-65to+150

·C

This device contains circuitry to protect the
Inputs against damage due to high static voltages or electric fields; however, it is advised
that normal precautions be taken to avoid
applications of any voltage higher than the
maximum rated voltages to this high Impedance circuit.
For proper operation it Is recommended that
Yin and Vout be constrained to the range VSS s
(Vin or Vout) S VDO. Reliability of operation is
enhanced if unused Inputs are tied to and appropriate logic voltage level (e.g., eitherVSS or
VOO)·

ELECTRICAL CHARACTERISTICS
(All Polarities Referenced to VSS =0 V, VOO =5.0 V ±10%, TA =- 40 to + 85·C, Unless Otherwise Noted)
Symbol

Min

Typ

Max

DC Supply Voltage

VDO

4.5

5

5.5

V

Supply Current (fCLK =3.58 MHz)

100

7

15

mA

200
±1

I1A

1.5

V

Parameter

Input Current
ENB, Xin, Xen

GT

Input Voltage Low

ENB, GT,X en

VIL

-

Input Voltage High

ENB, GT,X en

VIH

3.5

lout Data and OV Pins: Vout =4.5 V (Source)

10H

800

-

lout Data and OV Pins: Vout =0.4 V (Sink)

10L

1.0

-

90

100

-

-

-

10

6

-

Input Impedance
Fanout
Input CapaCitance

lin

Ain

Rin

ATB

Fout

Xen , ENB

Cln

Unit

V
JlA
mA
kn

pF

ANALOG CHARACTERISTICS (VOD = 5.0 V ±10%, TA = - 40 to + 85·C, Unless Otherwise Noted)
Min

Typ

Max

Unit

Signal Level for Detection (Ain)

-35

-2

dBm

Twist = High Tone/Low Tone

-10

-

10

dB

Frequency Detect Bandwidth

±(1.5 +2 Hz)

±2.5

±3.5

%fO

-

-

0.8

Vrms

0

dB

-

-

-12

dB

10

mVp-p

2

-

Parameter

60-Hz Tolerance
Dial Tone Tolerance (Nole 1)
(Dial Tone 330 + 440)
Noise Tolerance (Notes 1 and 2)

.".

Power Supply Noise (WIde Band)
Talk Off (Mltel Tape #CM7290)

Hits

NOTES:
1. Referenced to lower amplitude tone.
2. Bandwidth limited (0 to 3.4 kHz) Gaussian Noise.

MOTOROLA COMMUNICATIONS DEVICE DATA

MC145436
2-743

AC CHARACTERISTICS (VDD = 5.0 V ± 10%, TA = -40·C to + 8S·C)
Chara.cteristlc
Tone On Time
For Rejection

For Detection

Pause Time
For Rejection

For Detection

Symbol

Min

TONEon

40

TONEoff

-

40

-

ms

20

-

ms

20

40
30

ms

-

7

-

-

ItS

th

4.2

4.6

5

ms

tw(GT)

18

-

liS

~ag(DV)

-

-

5

ms

120

500

ns

110

300

ns

tdet

22
32

Release Time
GT=l

GT=O

trel

28
18

Data Setup Time

tsu

Data Hold Time

DV Reset Lag Time

Unit

-

ms

GT=O

GT

Max

-

40
50

Detect Time
GT=l

PulseWidlh

Typ

ENS High to Output DV (Note 1)

tEHDV

ENS Low to Output High-Z (Note 1)

tELDZ

NOTE:
1. [lata out: CL = 35 pF II RL = 500 n.

TIMING DIAGRAM

ANALOG INPUT
(Ain)

TONE BURST 2

01,02
04,08

HIGH-Z - tsu

OV

tELOZ

tEHOV

tELOZ

ENB
tw(GT)
GT

MC145436
2-744

MOTOROLA COMMUNICATIONS DEVICE DATA

PIN DESCRIPTIONS

Voo

Positive Power Supply
The digital supply pin, which is connected to the positive
side of the power supply.
VSS
Ground
Ground return pin is typically connected to the system
ground.
01,02,04,08
Oata Output
These digital outputs provide the hexadecimal codes corresponding to the detected digit. The digital outputs become
valid after a tone pair has been detected and are cleared when
a valid pause is timed. See Table 1 for hexadecimal codes.These output pins are high impedance when the enable
pin is at logic O.
EN
Enable
Outputs D1, D2, D4, DB are enabled when ENB is at a logic
1, and high impedance (disabled) when ENB is at a logic O.
GT
Guard Time
The Guard Time control input provides two sets of detected
time and release time, both within the allowed ranges of tone
on and tone off (see Figure 1). A longer tone detecllime rejects
signals too short to be considered valid. With GT = 1, talk off
performance is improved, since it reduces the probability that
tones simulated by speech will maintain signal conditions long
enough to be accepted. In addition, a shorter release time reduces the probability that a pause simulated by an interrupt in
speech will be detected as a valid pause. On the other hand,
a shorter tone detect time with a long release time would be

Table 1. Hexadecimal Codes
Output Code
Digit

D8

D4

D2

1

0

0

a

1

2

a
a

a
a

1

a

1

1

0

1
1

a
a

0

0

a

1

1

0

7

0

1

1

1

a
a

0

3
4
5
6

D1

1

8

1

9

1

a

1

a
a
a

1

0

1

0

1

1

a
a

a
a

.

1

#

1

1

A
8

1

1

1

1

1

c

1

1

1

1

D

a

a

a

0

MOTOROLA COMMUNICATIONS DEVICE DATA

appropriate for an extremely noisy environment where fast acquisition time and immunity to dropouts would be required. In
general, the tone signal time generated by a telephone is
100 ms, nominal, followed by a pause of about 100 ms. A
high-to-Iow or low-to-high transition on the GT pin resets the
internal logic and the MC145436 is immediately ready to accept a new tone input. If left open, this pin is internally pulled
to ground.
Xen
Oscillator Enable
A logic 1 on Xen enables the on-chip crystal oscillator. When
using alternate time base from the ATB pin, Xen should be tied
to VSS.
Ain
Analog Input
This pin accepts the analog input and is internally biased so
that the input signal may be ac coupled. The input may be dc
coupled so long as it does not exceed the positive supply (see
Figure 2).
XinlXout
Oscillator In and Oscillator Out
These pins connect to an internal crystal oscillator. In operation, a parallel resonant crystal is connected from Xin to Xout,
as well as a 1-MQ resistor in parallel with the crystal. When
using the alternate clock source from ATB, Xin should be tied
to VDD.
ATB
Alternate Time Base
This pin serves as a frequency reference when more than
one MC145436 is used, so that only one crystal is required for
multiple MC145436s. When doing so, all ATB pins should be
tied together as shown in Figure 3. When only one MC145436
is used, this pin should be left unconnected. The output frequency of ATB is 447.4 kHz.
DV
Data Valid
DV signals a detection by going high after a valid tone pair
is sensed and decoded at output pins D1, D2, D4, D8. DV remains high until a loss of the current DTMF signal occurs or
until a transition in GT occurs.

I
I
I
I
I

GUARDTIME~

iI v~
I
I
I

-=

Figure 1. Guard Time

1

MC145436
2-745

r---

Vin< VOO
O.OlIlF
Ain

1 VOO
1
1
1

--l
1
1
1

100kn

1=
1

L __ _

Figure 2. Analog Input (Operational Information based on PDIP package)

Xin
COL 1
ATB

VOO
Xin
ATB

MC145436

Xen

=
TO OTHER
MCl45436s

Figure 3. Multiple MC145436s

MC145436
2-746

STD
OTMF
(Hz)

COL2

COL3

COL 4

697GJ00~
770 GJ GJ GJ ~

ROW 1
ROW 2

852[2J~~~

ROW 3

GJ00~

ROW4

941

1209

1336

1477

1633

STO OTMF (Hz)

Figure 4. 4 x 4 Keyboard Matrix

MOTOROLA COMMUNICATIONS DEVICE DATA

MOTOROLA

_ SEMICONDUCTOR
-------------TECHNICAL DATA

MC145439
MC142103

Encoder/Decoder (Transcoder)
For Transmission Applications
The MC145439 and MC142103 are high speed CMOS integrated circuits
designed to perform the coding translation of clocked serial data into two streams
of return to zero (RZ) digital pulses, which are externally mixed to form either AM I,
H083, 86ZS, or 88ZS (MC1421 03-AMI or H083 only) ternary signals for driving
transmission lines. They perform the reverse operation by translating two streams
of clocked pulses [which have been derived from an incoming AMI, H083, 86ZS,
or 88ZS (MC142103-AMI or H083 only) ternary encoded signal] into a single
stream of clocked binary data. They also feature loopback and error monitoring
functions. The coding and decoding functions perform independently at clock rates
from 0 (dc) to 9 mbps. The H083 coding and decoding are performed in a manner
consistent with the CCITT G.703 recommendations.
Both Devices:
• Low Power CMOS Operation
• Single 5-V Power Supply Operation

~-

MC145439
PLASTIC
CASE 738

1

~

)\1iHn~ ~

MC142103
PLASTIC
CASE 648

1

REC0

•
•
•
•

Error Monitor Functions Provided
Loopback Feature Provided
Encode and Oecode Clock Rates to 9 mbps
Pin Selectable Modes of Operation
o TTL Compatible Inputs and Outputs
MC145439 Only:
• 20-Pin Package
• NRZ to AMI, H083, 86ZS, 88ZS; AMI, HD83, 86ZS, 88ZS to NRZ
• Force Alarm and Output Enable Function
• Pin Compatible with HC-5560
MC142103 Only:
• 16-Pin Package
• NRZ to AMI, HD83; AMI, H083 to NRZ
• Pin Selectable H083 or AMI Operation
• Pin Compatible with C022103 and MJ1471

PIN ASSIGNMENTS

N

BLOCK DIAGRAM

-----------<_----+

MSI (OR HDB3/AMI
MS2(MCI454390NLY)
OUTPUT ENABLE
(MCI454390NLy) ------+---1---1
NRZin
FA (MCI45439 ONLy) - - . .~"

MC145439
FA [ 10

20

VDD

MSI [ 2

19

OE

3

18

N.C.

ECLK [ 4

17

Pout

MS2 [ 5

16

Nout

NRZout [ 6

15

Nin

DCLK [ 7

14

LOOP

RAIS

8

13

Pin

AIS

9

12

CLK

VSS

10

11

ERR

NAZin

------_--+----_

-=====:====~

LOOP
ECLK -

Pin-----~

Nin

DCLK

-----.t.T--l=~=~==j=:::

---t-------f'-IL--r----1--

MC142103
10

16 ] VDD

2

15 J Paul

HDB3/AMI l 3

14 ] Nout

NRZin
ECLK

r

NRZoul

4

13 ] Nin

DCLK

5

12

RAIS

6

11

AIS

7

lOP

VSS

8

9

bLOOP
b Pin
CLK

b ERR

L......:.......---..::~===-_-======~ AIS
ERR
This document contains information on a new product. SpeCification and information herein are subject to change without notice.

MOTOROLA COMMUNICATIONS DEVICE OATA

MC145439.MC142103
2-747

MOTOROLA

-

SEMICONDUCTOR
TECHNICAL DATA

MC145442
MC145443

Single Chip 300-Saud Modem
The MC145442 and MC145443 silicon-gate CMOS single-chip low-speed
modems contain a complete frequency shift keying (FSK) modulator, demodulator,
and filter. These devices are with CCID V.21 (MC145442) and Bell 103
(MC145443) specifications. Both devices provide full-duplex or half-duplex
300-baud data communication over a pair of telephone lines. They also include
a carrier detect circuit for the demodulator section and a duplexer circuit for direct
operation on a telephone line through a simple transformer.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•

MC145442 Compatible with CCID V.21
MC145443 Compatible with Bell 103
Low-Band and High-Band Band-Pass Filters On-Chip
Simplex, Half-Duplex, and Full-Duplex Operation
Originate and Answer Mode
Analog Loopback Configuration for Self Test
Hybrid Network Function On-Chip
Carrier Detect Circuit On-Chip
Adjustable Transmit Level and CD Delay Timing
On-Chip Crystal Oscillator (3.579 MHz)
Single + 5 V Power Supply Operation
Internal Mid-Supply Generator
Power-Down Mode
Pin Compatible with MM74HC943
Capable of Driving -9 dBm into a 600 Q Load

.-

PSUFFIX
PLASTIC
CASE 738

1

OW SUFFIX

SOG
CASE751D

PIN ASSIGNMENT
OSI [ 1·

20 PTLA

[B [ 2

19 P VAG

CO[ 3

18

PExl

17

PTxA

coT[

4

RxO [ 5

16 P RxA1

VOO [ 6

15

COA [ 7

14

Xout

r

8

PRxA2
PSOT
13 PMODE

Xi" [ 9

12 P VSS

FB

11

10

PTxO

BLOCK DIAGRAM
COT
COA
CO

RxO
FB
OSI
[B

--

MOOE:=~i=======~~~J
SOT
TxO

~L---r~-=l----o....

~

......1

SAMPLING CLOCK: 77.82 kHz
SAMPLING CLOCK: 19.46 kHz

MC145442.MC145443
2-748

Exl

__

TLA...".,'-----C=;:..::.:.:.J

'Refer to the FB pin description.

TxA

,

............ -'

19

t

VOO
12

10

VAG

VSS

MOTOROLA COMMUNICATIONS DEVICE DATA

This device contains circuitry to protect the
Inputs against damage due to high static voltages
or electric fields; however, it is advised that normal
precautions be taken to avoid application of any
voltage higher than maximum rated voltages to
this high impedance circuil. For proper operation
it is recommended that Yin and Vout be con·
strained to the range VSS s; (Vin orVout) s; VOo).

ABSOLUTE MAXIMUM RATINGS (Voltages Referenced to VSS)
Rating

Symbol

Value

Unit

VOO

-0.5 to +7.0

V

DC Input Voltage

Yin

-0.5 to VOO +0.5

V

DC Output Voltage

Vout

-0.5 to VOO +0.5

V

IIK,IOK

±20

rnA

Supply Voltage

Clamp Diode Current, per Pin
DC Output Current, per Pin

lout

±2B

rnA

Power Dissipation

Po

500

mW

Operating Temperature Range

TA

-40to+BS

°C

Tstg

-6Sto+1S0

°C

Storage Temperature Range

Unused inputs must always be tied to an
appropriate logic voltage level (e.g., eitherVSS or
VOO)·

RECOMMENDED OPERATING CONDITIONS
Parameter
Supply Voltage
DC Input or Output Voltage
Input Rise or Fall Time
Crystal Frequency'

Symbol

Min

Max

Unit

VOO

4.5

5.5

V

Yin, Vout

0

VOO

V

tr,tf

-

500

ns

fcrystal

3.2

5.0

MHz

'Changlng the crystal frequency from 3.579 MHz will change the output frequenCies.
The change in output frequency will be proportional to the change In crystal frequency.
DC ELECTRICAL CHARACTERISTICS (VOO = 5.0 V ± 10%, TA = -40°C to + BSOC)
Symbol

Min

High-Level Input Voltage
Xin, TxO, Mode, SOT

Characteristic
LB

VIH

VOO-O.B
3.15

Low-Level Input Voltage
Xin, TxO, Mode, SOT

LB

VIL

High-Level Output Voltage
IOH= 2O IlA
IOH=2mA
IOH= 2O IlA

CO, RxO
CO, RxO
Xout

Low-Level Output Voltage
IOL= 2O IlA
IOL=2mA
IOL= 2O IlA

CO, RxO
CO, RxO
Xout

Input Current
RxAl,RxA2
Xin
Ouiesent Supply Current

-

-

VOO-O.l
3.7

-

VOH

VOL

LB, TxO, Mode, SOT

(Xin or fcrystal = 3.579 MHz)

lin

100

Power-Down Supply Current
Input Capacitance
All Other Inputs

Xin

Cin

Typ

Max

Unit

-

V

.O.B
1.1

V
V

-

-

VOO-O.OS

-

-

-

0.1
0.4

0.05

-

10
-

±1.0
±12
±10

IlA

-

-

-

V

7

10

rnA

200

300

IlA

10

-

pF

-

10

VAG Output Voltage (10 = ± 10 1lA)

VAG

2.4

2.5

2.6

COA Output Voltage (10 = ± 10 IlA)

VCOA

1.1

1.2

1.3

V

Rf

10

20

30

kQ

Line Driver Feedback Resistor

MOTOROLA COMMUNICATIONS DEVICE DATA

V

MC145442.MC145443
2·749

AC ELECTRICAL CHARACTERISTICS
(VDD = 5.0V± 10%, TA=-40·Cto + 85·C, Crystal Frequency = 3.579 MHz±0.1%; See Figure 1)
Characteristic

Min

Typ

Max

Unit

-13
-10

-12
-9

-11
-8

-

-56

-

dBm

Hybrid Inputlmpedance RxA1, RxA2

40

50

FB Output Impedance

-

16

kn

-48

-

-

dBm

-48

-

-12

dBm

-

36

-

dB

TRANSMITTER
dBm

Power Output on TxA
RL = 1.2 kg, RrLA = 00
RL = t.2 kQ, RrLA = 5.5 kn
Second Harmonic Power
RL= 1.2 kQ
RECEIVE FILTER AND HYBRID

Adjacent Channel Rejection

kQ

DEMODULATOR
Receive Carner Amplitude
Dynamic Range
Bit Jitler (SIN = 30 dB, Input = - 38 dBm, Bit Rate = 300 baud)
Bit Bias
Carrier Detect Threshold
(CDA = t.2 V or CDA grounded through a 0.1-J!F capacitor)

On to Off
Off to On

100
5

-44
-47

J!s
%
dBm

TLA
Transmit Level Adjust (Pin 20)
This pin is used to adjust the transmit level. Transmit level
adjustment range is typically from -12 dBm to -9 dBm. (See
Applications Information.)

PIN DESCRIPTIONS
VDD
Positive Power Supply (Pin 6)
This pin is normally tied to 5.0 V.
VSS
Negative Power Supply (Pin 12)
This pin is normally tied to 0 V.
VAG
Analog Ground (Pin 19)
Analog ground is internally biased to (VDD - VSS)/2. This
pin must be decoupled by a capacitor from VAG to VSS and
a capacitor from VAG to VDD. Analog ground is the common
bias line used in the switched capacitor filters, limiter, and
slicer in the demodulation circuitry.

TxD
Transmit Data (Pin 11)
Binary information Is input to the transmit data pin. Data
entered for transmission is modulated using FSK techniques.
A logic high input level represents a mark and a logic low
represents a space (see Table 1).

Table 1_ 8ell103 and CCITT V.21
Frequency Characteristics
Bell 103 (MC145443)
Originate Mode

8

RrLA
VDD

20
17
15

600n
600n

11
Din
TxA

Transmit

Receive

Transmit

Receive

Space

1070Hz

2025Hz

2025 Hz

1070 Hz

Mark

1270Hz

2225 Hz

2225 Hz

1270 Hz

RxA2

CCITT V_21 (MC145442)

MCI45442
MC145443
16

TEST

Answer Mode

Data

Originate Mode

Answer Mode

Date

Transmit

Receive

Transmit

Receive

Space

1180Hz

1850 Hz

1850 Hz

1180 Hz

Mark

980Hz

1650 Hz

1850 Hz

980 Hz

Daut

NOTE: Actual frequencies maybe ±5 Hz assuming 3.579545-MHz
crystal Is used.
Figure 1_ AC Characteristics Evaluation Circuit

MC145442.MC145443
2-750

MOTOROLA COMMUNICATIONS DEVICE DATA

TxA
Transmit Carrier (Pin 17)
This is the output of the line driver amplifier. The transmit
carrier is the digitally synthesized sine wave output of the
modulator derived from a crystal oscillator reference. When
a 3.579 MHz crystal is used the frequency outputs shown
in Table 1 apply. (See Applications Information.)

MAXIMUM LEVEL Of OUT·Of·BAND ENERGY
RELATIVE TO THE TRANSMIT CARRIER LEVEL INTO 600 n (kHz)
3.4 4

E
ro

16

64

256

~

u:l

ru
a:
il! -20

LB
Analog Loopback (Pin 2)
When a high level is applied to this pin (SOT must be low),
the analog loopback test is enabled. The analog loopback
test connects the TxA pin to the RxA2 pin and the RxA 1 to
analog ground. In loopback, the demodulator frequencies are
switched to the modulation frequencies for the selected
mode. (See Tables 1 and 2 and Figures 4c and 4d.)
When LB is connected to analog ground (VAG), the modulator generates an echo cancellation tone of 2100 Hz for
MC145442 CCITT V.21 and 2225 Hz for MC145443 Bell 103
systems. For normal operation, this pin should be at a logic
low level (VSS).
The power-down mode is enabled when both LB and SOT
are connected to a logic high level (see Table 2).

..J

Table 2. Functional Table

~ -25

(.)

15 dB/OCTAVE

I-

':!!
en

~

I-

-55

- - - - - - - - - - - - - -"'--------'"-

-60

Figure 2. Out-ol-Band Energy
Exl
External Input (Pin 18)
The external input is the non·inverting input to the line driv·
er. It is provided to combine an auxiliary audio signal or
speech signal to the phone line using the line driver. This
pin should be connected to VAG if not used. The average level
must be the same as VAG to maintain proper operation. (See
Applications Information.)
DSI
Driver Summing Input (Pin 1)
The driver summing input may be used to connect an external signal, such as a DTMF dialer, to the phone line. A series
resistor, RDSI, is needed to define the voltage gain AV (see
Applications Information and Figure 6). When applying a signal to do DSI pin, the modulator should be squelched by
bringing SOT (Pin 14) to a logic high level. The voltage gain,
AV, is calculated by the formula AV = -Rf/RDSI (where Rf ~
20 kO). For example, a 20 kO resistor for RDSI will provide
unity gain (AV = -20 knJ20 kO = -1). This pin must be
left open if not used.
RxD
Receive Data (Pin 6)
The receive data output pin presents the digital binary data
resulting from the demodulation of the receive carrier. If no
carrier is present, CD high, the receive data output (RxD)
is clamped high.
RxA2, RxA1
Receive Carrier (Pins 15, 16)
The receive carrier is the FSK input to the demodulator
through the receive band-pass filter. RxA 1 is the non-inverting input and RxA2 is the inverting input of the receive hybrid
(duplexer) operational amplifier.

MOTOROLA COMMUNICATIONS DEVICE DATA

MODE
Pin 13

SOT
Pin 14

LB
Pin 2

1

0

0

Originate Mode
Answer Mode

Operating Mode

0

0

0

X

0

VAG (VOO/2)

X

0

1

Analog Loopback

X

1

0

Squelch Mode

X

1

VAG (VOO/2)

Squelch Mode

X

1

1

Echo Tone

Power Down

MODE
Mode (Pin 13)
This input selects the pair of transmit and frequencies
used during modulation and demodulation. When a logic
high level is placed on this input, originate (Bell) or channel
1 (CCITT) is selected. When a low level is placed on this
input, answer (Bell) or channel 2 (CCITT) is selected. (See
Tables 1 and 2 and Figure 4.)
COT
Carrier Detect Timing (Pin 4)
A capacitor on this pin to VSS sets the amount of time the
carrier must be present before CD goes low (see Applications Information for the capacitor values).
CD
Carrier Detect Output (Pin 3)
This output is used to indicate when a carrier has been
sensed by the carrier detect circuit. This output goes to
a logic low level when a valid signal above the maximum
threshold level (defined by CDA, Pin 7) is maintained on
the input to the hybrid circuit longer then the response (defined by CDT, Pin 4). This pin is held at the logic low level
until the signal falls below the maximum threshold level for
longer than the turn off time. (See Applications Information and Figure 5.)
CDA
Carrier Detect Adjust (Pin 7)
An external voltage may be applied to this pin to adjust
the carrier detect threshold. The threshold hysteresis is internally fixed at 3 dB (see Applications Information).

MC145442.MC145443
2-751

Xout. Xin
Crystal Oscillator (Pins 8, 9)
A crystal reference oscillator is formed when a 3.579 MHz
crystal is connected between these two pins. Xout (Pin 8) is
the output of the oscillator circuit, and Xin (Pin 9) is the input
to the oscillator circuit. When using an external clock, apply
the clock to the Xin (Pin 9) pin and leave Xout (Pin 8) open.
An internal 10-MQ resistor and internal capacitors, typically
10 pF on Xin and 16 pF on Xout, allow the crystal to be connected without any other external components. Printed circuit
board layout should keep external stray capacitance to a
minimum.
FB
Filter Bias (Pin 10)
This is the negative input to the ac amplifier. In normal
operation, this pin is connected to analog ground through
a O. 1 ~F bypass capacitor in order to cancel the input offset
voltage of the limiter. It has a nominal input impedance of
16 kn. (see Figure 3).
SOT
Transmit Squelch (Pin 14)
When this input pin is at a logic high level, the modulator
is disabled. The line driver remains active if LB is at a logic
low level (see Table 2) .
When both LB and SaT are connected to a logic high level,
see Table 2, the entire chip is in a power down state and
all circuitry except the crystal oscillator is disabled. Total power supply current decreases from 10 mA (Max) to 300 ~A
(Max).
FROM
BAND·PASS
FILTER

>---.---.

~

TO
CARRIER DETECT CIRCUIT
AND DEMODULATOR

O.lIlF

Figure 3. AC Amplifier Circuit

MC145442.MC145443
2-752

GENERAL DESCRIPTION
The MC145442 and MC145443 are full-duplex low-speed
modems. They provide a 300 baud FSK signal for bidirectional
data transmission over the telephone network. They can be
operated in one of four basic configurations as determined
by the state of MODE (Pin 13) and LB (Pin 2). The normal
(nonloopback) and self test (loopback) modes in both answer
and originate modes will be discussed.
For an originate or channell mode, a logic high level is
placed on MODE (Pin 13) and a logic low level is placed on
LB (Pin 2). in this mode, transmit data is input on TxD, where
it is converted to a FSK signal and routed through a low·band
band-pass filter. The filtered output signal is then buffered by
the Tx op-amp line driver, which is capable of driving -9 dBm
onto a 600 Q line. The receive Signal is connected through
a hybrid duplexer circuit on pins 15 and 16, RxA2 and RxA 1.
The signal then passes through the anti-aliasing filter, the
sample-and-hold circuit, is switched into the high-band
band-pass filter, and then switched into the ac amplifier circuit.
The output of the ac amplifier circuit is routed to the
demodulator circuit and demodulated. The resulting digital
data is then output through RxD (Pin 5). The carrier detect
circuit receives its signal from the output of the ac amplifier
circuit and goes low when the incoming signal is detected (see
Figure 4a).
In the answer or channel 2 mode, a logic low level is placed
on MODE (Pin 13) and on LB (Pin 2). In this mode, the data
follows the same path except the FSK signal is routed to the
high-band band-pass filter and the sample-and-hold signal is
routed through the low-band band-pass filter. (See Figure 4b.)
In the analog loopback originate or channell mode, a logic
high level is placed on MODE (Pin 13) and on LB (Pin 2). This
mode is used for a self check of the modulator, demodulator,
and low-band pass-band filter circuit. The modulator side is
configured exactly like the originate mode above except the
line driver output (TxA, Pin 17) is switched to the negative input
of the hybrid op-amp. The RxA2 input pin is open in this mode
and the non-inverting input of the hybrid circuit is connected
to VAG. The sample-and-hold output bypasses the filterso that
the demodulator receives the modulated Tx data (see Figure
4c). This test checks all internal device components except
the high-band band-pass filter, which can be checked in the
answer or channel 2 mode test.
In the analog loopback or chanel2 mode, a logic low level
is placed on MODE (Pin 13) and a logic high level on LB
(Pin 2). This mode is used for a self check of the modulator,
demodulator, and high·band pass-band filter circuit. This
configuration is exactly like the originate loopback mode
above, except the signal is routed through the high-band
pass·band filter (see Figure 4d).

MOTOROLA COMMUNICATIONS DEVICE DATA

RxA2 -,1.:<.5...A.J'\I'v--<,....--'.I"I'v_-,

RxAI -,1,,-S-'1/1.1\,..._>-1
RxD
DSI
TxD ...:1.:..1_ _ _ _ _ _ _-1

17

TxA

18

Exl

(a) OriginateiChannell Mode (Mode =High, [8 =Low)

I----~CD

RxA 1 -,-,IS~f\A_*-l
I----""I~

RxD

r-----"'-C DSI
TxD ...:1.:..1_ _ _ _ _ _ _-1

>-....--!.17,...

TxA

18" -C Exl

' - -_ _ _......,!;

(b) Answer/Channel2 Mode (Mode =Low, [8 =Low)

RxA2

.1Eo

RxA 1 ...:.IS"---I-I\fVI,_-<"'l
RxD
DSI
TxD ..,1.:..1_ _ _ _ _ _ _ _ _ _---1

17

18

TxA

Exl

(c) Originate/Channell Mode and Analog Loop-Back State (Mode =High, [8 =Low)

RxA2.lEo
I----~CD

RxAI ....1",S-f-JV\fIr-_o
I----""I~ RxD

r----I-~ DSI

TxD ...:1.;..1_ _ _ _ _ _ _ _ _ _----t

>~.....,.1'-i7~ TxA
18"-C Exl

' - -_ _ _......,!;

=

=

(d) Answer/Channel2 Mode and Analog Loop-Back State (Mode Low, [8 Low)

Figure 4. Basic Operating Modes
MOTOROLA COMMUNICATIONS DEVICE DATA

MC145442.MC145443
2-753

APPLICATIONS INFORMATION
CARRIER DETECT TIMING ADJUSTMENT
The value of a capacitor, CCDT at COT (Pin 4) determines
how long a received modem signal must be present above
the minimum threshold level before CD (Pin 3) goes low. The
CCDT capacitor also determines how long the CD pin stays
low after the received modem signal goes below the minimum
threshold. The CD pin is used to distinguish a strong modem
signal from random noise. The following equations show the
relationship between tCDL, the time in seconds required for
CD to go low; tCDH, the time in seconds required for CD to
go high; and CCDT, the capacitor value in 11F.
Valid signal to CD response time: tCDL '" 6.4 x CCDT
Invalid Signal to CD off time:
tCDH '" 0.54 x CCDT
Example: tCDL '" 6.4 x 0.1 I1F '" 0.64 seconds
tCDH '" 0.54 x 0.1 I1F '" 0.054 seconds
CARRIER DETECT THRESHOLD ADJUSTMENT
The carrier detect threshold is set by internal resistors to
activate CD with a typical -44 dBm (into 600 0) signal and
deactivate CD with a typical -47 dBm signal applied to the
input of the hybrid circuit. The carrier detect threshold level
can be adjusted by applying an external voltage on CDA (Pin
7). The following equations may be used to find the CDA
voltage required for a given threshold voltage. (Von and Voff
are in Vrms.)
VCDA = 244 x Von
VCDA = 345 x Voff
Example (Internally set)
Von = 4.9 mV '" -44 dBm: VCDA = 244 x 4.9 mV = 1.2 V
Voff = 3.5 mV '" -47 dBm: VCDA = 345 x 3.5 mV = 1.2 V
Example (externally set)
Von = 7.7 mV '" -40 dBm: VCDA = 244 x 7.7 mV = 1.9 V
Voff = 5.4 mV '" -43 dBm: VCDA = 345 x 5.4 mV = 1.9 V
The CDA pin has an approximate Thevenin equivalent
voltage of 1.2 V and an output impedance of 100 kn. When
using the internall.2-V reference a O.I-I1F capacitor should
be connected between this pin and VSS (see Figure 5).
TRANSMIT LEVEL ADJUSTMENT
The power output at TxA (Pin 17) is determined by the value
of resistor RTLA that is connected between TLA (Pin 20) to
VDD (Pin 6). Table 3 shows the ATLA values and the

corresponding power output for a 600 0 load. The voltage at
TxA is twice the value of that at ring and tip because TxA feeds
the signal through a 600 0 resistor ATx to a 600 0 line
transformer (see Figure 7). When choosing resistor ATLA,
keep in mind that -9 dBm is the maximum output level allowed
from a modem onto the telephone line (in the U.S.).ln addition,
keep in mind that maximizing the power output from the
modem optimizes the signal-to-noise ratio, improving accurate data transmission.
Table 3. Transmit Level Adjust
Output Transmit Levet
(Typical Into 600 !l)

RTLA

-12dBm
-11 dBm
-10dBm
-9dBm

19.8k!l
9.2k!l
5.5k!l

~

THE LINE DRIVER
The line driver is a power amplifier used for driving the
telephone line. Both the inverting and noninverting input to
the line .driver are available for transmitting externally
generated tones.
Exl (Pin 18) is the noninverting input to the line driver and
gives a fixed gain of 2 (Ai = 50 kn). The average signal level
must be the same as VAG to maintain proper operation. This
pin should be connected to VAG if not used.
The driver summing input (DSI, Pin 1) may be used to
connect an external signal, such as a DTMF dialer, to the
phone line. When applying a signal to the DSI pin, the
modulator should be squelched by bringing SaT (Pin 14) to
a logic high level. DSI must be left open if not used.
In addition, the DSI pin is the inverting side of the line driver
and allows adjustable gain with a series resistor ADSI (see
Figure 6). The voltage gain, AV, is determined by the
equation:

AV=-~
ADSI

where Af '" 20 kn.
Example: A resistor value of 20 kn for ADS I will provide
unity gain.
AV=- (20 knl20 kn) =-1

HYBRID

6ms
RETRIGGERABLE
ONE·SHOT

RxAl

SAMPLING
CLOCK
4

CCDA

O.II1F

COT

I --,
I :r: I
L:::'--.l

CCDT

O.II1F

Figure 5. Carrier Detect Circuit

MC145442.MC145443
2-754

MOTOAOLA COMMUNICATIONS DEVICE DATA

r-----:-----,
MOOU~TOR

I
I
I

OUTPUT
RO=Rf

TxA
17

L ________ -.l
Figure 6. Line Driver Using the DSllnput

+5V
O.II1F

t

O.II1F

19~

6

.-----L":":""'----JL..:::..--,

VCC

VOO
'--'VVv-=2,,!0 T~
OTMF
ROSI
COSI Rr~ 1
INPUT~
17 OSI
O.II1F
15 TxA
RxA2
MCl4544213

Ion

1-'--.....9

TIP~

AxAl

CI+ 20

co 1-___-+--'

Voo
O.II1F

~--:-_-,1~8 Ex!

1-

ClTx2 t-=*i-I>I-if-*'I'"

TxEN

Txl ~#I>f-*'I'"

STBY

Ax2 1"7'-41_--+----1 7

FB

~-4---'c..;..:;;---,'-=i

O.lI1F

MC145407

012

TxO 1-----+---'9 001
AxO
011
SOT

AING-----13

Cl-

Xout

EIA·232·0
OB·25
CONNECTOR

Rx3 9

VAG
GNO
2

CCOT
O.lI1F

• Line Protection Circuit

Figure 7. Typical MC1454421MC145443 Applications Circuit

MOTOROLA COMMUNICATIONS DEVICE DATA

MC145442.MC145443
2·755

MOTOROLA

-

SEMICONDUCTOR
TECHNICAL DATA

MC145444

20

Advance Information
Single Chip 300-aaud Modem
MC145444 is a silicon gate CMOS frequency shift keying (FSK) modem
intended for use with telemeter systems or remote control systems over the
telephone network.
This device is compatible with CCITT V.21 and contains the entire circuit that
provides a full-duplex or half-duplex 300 baud data communication over a pair
of telephone lines. This device also includes the DTMF generator and call progress
tone detector (CPTD).
The differential line driver has the capability of driving 0 dBm into a 600 n load
with a single +5 V power supply.
The transmit level is controlled by the programmable attenuator in 1 dB steps.
Devices functions are controlled through a 3-wire serial interface.
•
•
•
•
•
•
•
•
•

•

H SUFFIX
PLASTIC
CASE 804

20_

DWSUFFIX
PLASTIC
CASE751D

PIN ASSIGNMENT

Capable of Driving 0 dBm into a 600 n Load
DTMF Generator On-Chip
Imprecise Call Progress Detector On-Chip
A Transmit Attenuator Programmable in 1 dB Steps
3-wire Serial Interface
Compatible with CCITT V.21
2100 Hz Answer Tone Generator On-Chip
Analog Loop-Back Configuration for Self Test
Simplex, Half-Duplex, and Full-Duplex Operation

RxBD
FTLC
GNDA
CDA

~
4

RxGC

19

RxA

18

TxA1

17

TxA2

GND

16

DSI

TLA
X1

15

VCC
ENB

7

14
13

9
10

12
11

X2

SO
RxD

SCK
DATA
TxD

BLOCK DIAGRAM
RxBD
RxA

FTLC
RxD

RxGC

SO
CDA
TxD
DSI
TLA
TxA1
TxA2
ENB
DATA
SCK

X1

X2

GNDA

GND

VCC

This document contains information on a new product. Specification and information herein are subject to change without notice.

MC145444

2·756

MOTOROLA COMMUNICATIONS DEVICE DATA

ABSOLUTE MAXIMUM RATINGS
Rating
DC Supply Voltage
DC Input Voltage
DC Output Voltage
Clamp Diode Current per Pin
DC Current per Pin

Symbol

Value

Unit

VCC

-0.5 to + 7.0

V

Vin

-0.5 to VCC +0.5

V

Vout

-0.5 to VCC +0.5

V

IIK,IOK

±20

mA

lout

±25

mA

Power Dissipation

PD

500

mW

Storage Temperature Range

Tstg

-65 to + 150

°c

RECOMMENDED OPERATING CONDITIONS
Parameter

Symbot

Min

VCC

4.5

DC Input Voltage

Vin

DC Output Voltage

Vout

a
a
a
a

DC Supply Voltage

Input Rise Time

tr

Input Fall Time

tf

Crystal Frequency

-

fosc

Operating Temperature Range

Max

Unit

5

5.5

V
V

-

VCC

-

VCC

V

-

500

ns

-

500

3.579545

-20

TA

Typ

25

-

ns
MHz

70

°c

DC ELECTRICAL CHARACTERISTICS (VCC = + 5.0 Vdc ± 10%, TA = -20 to + 70°C)
Characteristic
Input Voltage

Output Voltage

Symbot

Max

Unit

-

1.1

tOH=20J.LA

VCC-0.1

VCC-0.01

IOL= 20 J.LA
IOL=2mA

-

0.Q1

Vin = VCC or GND

-

±1.0

tcc

FSK Mode

8

ICC

Power-Down Mode 1

-

-

300

J.LA

ICC

Power-Down Mode 2

-

-

1

J.LA

VIL

H Level

VOH

L Level

VOL
lin

Power-Down Supply Current

Typ

-

VIH

L Level

Quiescent Supply Current

Min

-

H Level

Input Current DATA, SCK, E, TxD

Conditions

3.15

-

-

V

V

0.1
0.4
±10.0

-

J.LA
mA

TRANSMIT CARRIER CHARACTERISTICS (V CC = +5.0 Vdc ± 10%, TA = - 20 to + 70°C)
Min

Typ

Max

Unit

Mark "1"

hM

974

980

986

Hz

Space "0"

f1S

1174

1180

1186

Mark "1"

f2M

1644

1650

1656

Space "0"

f2S

1844

1850

1856

fans

2094

2100

2106

Characteristic
Carrier Frequency Channel 1

Carrier Frequency Channel 2

Symbol

Answer Tone
Transmit Carrier Level

VO"

Second Harmonic Energy

V2h"

Out-of-Band Energy

VOE"

Conditions

Crystal Frequency
3.579545 MHz

Attenuator = a dB
RTLA=oo

-

6

-

-

-46

-

Figure 1

dBm
dBm
dBm

" VTXA 1 - VTXA2, RL = 1.2 kQ

MOTOROLA COMMUNICATIONS DEVICE DATA

MC145444

2-757

TRANSMIT ATTENUATOR CHARACTERISTICS (VCC = +5.0 Vdc ± 10%, TA = -20 to + 70'C)
Max

Unit

Attenuator Range

ARNG

0

-

15

dB

Attenuator Accuracy

AACC

-0.5

-

+0.5

dB

Min

Typ

Max

Unit

50

-

-

kQ

Characteristic

Symbol

Conditions

Min

Typ

RECEIVER CHARACTERISTICS (Includes Hybrid, Demodulator and Carrier Detector)
(VCC = + 5 0 Vdc + 10%, TA = -20 to + 70'C)
Characteristic

Symbol

Input Impedance

RIRX

Receiver Carrier Amplitude

RxA Pin (Pin 19)

-

-12

dBm

CDA = 1.2V
lin = 1.0 kHz

-

-44

-

dBm

-

-47

-

2

-

-

dB

COl = 0, COO = 0

-

450

-

ms

-48

VIRX

Carrier Detect

OFF to ON

VCDON

Threshold

ON to OFF

VCDOF

Hysterisis (VCDON - VCCDOF)
Carrier Detect Timing

Conditions

HVS

OFF to ON
TCDON

ON to OFF
TCDOFF

COl = 0, COO = 1

-

15

-

COl = 0, COl = 1

-

15

-

COl = 1, COO = 1

-

80

-

COl = 0, COO = 0

-

30

-

COl = 0, COO = 1

-

30

-

COl = 0, COO = 1

-

15

-

COl = 1, COO = 1

-

10

-

BAND-PASS FILTER CHARACTERISTICS (RxA to FTLC) (VCC = +5.0 Vdc±10%, TA =-20 to + 70'C)
Characteristic

Symbol

FTLC Output Impedance

Conditions

Min

Typ

Max

Unit

10

-

50

kQ

-

50

-

dB

-

10

-

dB

Low-Band Filter
930-1230 Hz

-

700

-

J.ls

High-Band Filter
1600-1900 Hz

-

800

-

Min

Typ

Max

-

3

-

-

4

-

0

-

3

-

5

-

%

-1

-

1

%

-

ms

ROFT

Adjacent Channel Rejection

REJ

Pass-Band Gain

VRXA = -12 dBm

GpAS

Group Delay

DTMF CHARACTERISTICS (VCC = +5.0 Vdc+l0%,
TA =- 20 to + 70'C)
Characteristic
Tone Output Level

High Group Pre Emphasis

Symbol

I Low Group
I High Group

Vlh'
PE

DTMF Distortion

DIST

DTMF Frequency Variation

!1fy

Out-ol-Band Energy
Setup Time

Conditions

VII'

Attenuator = 0 dB
RTLA==
Crystal Frequency
3.579545 MHz

Figure 1

VOE'

Iosc

-

4

Unit
dBm

dB

dB

• VTXA 1 - VTXA2, RL = 1.2 kQ

MC145444
2-758

MOTOROLA COMMUNICATIONS DEVICE DATA

CPTD CHARACTERISTICS (VCC = +5.0 Vdc ±10%, TA = -20 to + 70'C)
Characteristic

Symbol

Bandpass Filter Center Frequency

fc

Bandpass Filter - 3 dB Band Width

dBW

Tone Detect Level

OFFtoON
ON to OFF

VTDOF

Tone Detect Timing

OFFtoON

TTDON

ON to OFF

TTDOF

Conditions

Min

VTDON
CDA= 1.2 V
fin = 400 Hz

-

Typ

Max

Unit

400

-

140

-

Hz

-44

-

dBm

-47

-

-

10

-

25

-

Min

Typ

Hz

ms

DEMODULATOR CHARACTERISTICS (VCC = + 5.0 Vdc ± 10%, TA = -20 to + 70'C)
Characteristic

Symbol

Conditions

ID

Input Level = - 24 dBm

BER

Input Level = - 24 dBm
CCITT Line Simulation
511 Bit Pattern
SIN = 5dB

Bit' Bias
Bit Error Rate

Max

Unit

-

5

-

0.00001

-

Min

Typ

Max

50

-

-

ns

-

ns

-

ns
ns

%

-

SWITCHING CHARACTERISTICS (VCC = +5.0 Vdc ±10%, TA = -20 to + 70'C)
Characteristic
Setup Times

Symbol
DATA to SCK

Hold Time

Conditions

tsu

SCKtoENB

50

SCKto DATA

th

50

-

ENBtoSCK

Unit

trec

50

-

-

Input Rise Time

tr

-

-

2

Input Fall Time

tf

-

-

2

~s

tw

50

-

-

ns

Recovery Time

Input Pulse Width

3.4k 4k

ENB,SCK

16 k

256 k

r\

f (Hz)

~---"'~

"""~-+I-

'L..-

- - - - - -

-Vcc
-GND
-Vcc
-GND

SCK
-25

~s

-15dB/OCT.
,

-Vcc
ENB------J

~------GND

PREVIOUS
DATA LATCHED
-55

-------------~------~

1 t--:,-----,=1r--vcc
ENB_-",50::":"!.:"'~:::lf
-~---1f

50

-GND

Figure 1. Out-ot-Band Energy

MOTOROLA COMMUNICATIONS DEVICE DATA

Figure 2. Switching Characteristics

MC145444

2-759

PIN DESCRIPTION
VCC
Positive Power Supply (Pin 15)
This pin is normally tied to the + 5.0 Vdc. A 0.1 IlF decoupling capacitor should be used.
GND
Ground Pin (Pin 5)
This pin is normally tied to the 0 V.
GNDA
Analog Ground (Pin 3)
Analog ground is internally biased to (VCC-VSS)/2. It
should be tied to ground through a q.1 IlF and 100 IlF
capacitor.
X1
Crystal Oscillator Output (Pin 7)
Connecting a 3.579545 MHz ±O.1 % crystal between X1
and X2 will cause the transmit frequencies to be within
±64 MHz of nominal. X1 is capable of driving several CMOS
gates. An external clock may be applied to X2. X1 should
then be left open.
X2
Crystal Oscillator Input (Pin 8)
Refer to X1.
SCK
Shift Resister Clock Input (Pin 13)
This pin is the clock input for the 15-bit shift register. Serial
data is loaded into the shift register on the rising edge of this
clock.
DATA
Serial Data Input (Pin 12)
This pin is the 15-bit serial data input. This data determines
the mode, OTMF signal, transmit attenuation, carrier detect
time, channel, and transmit squelch.
ENB
Enable Input (Pin 14)
Oata is loaded into the 15-bit shift register when this pin
is at a logic low. When this pin transitions from a logic high
to low, the data is transferred to the internal latch on the falling
edge of ENB. New data loaded into the shift register will not
affect the device operation until this pin transitions from high
to low. (See Figure 2.)
TxD
Transmit Data Input (Pin 11)
This pin is the transmit data input, The mark frequency is
generated when this pin is at the logic high level. The space
frequency is generated when the pin is at a logic low.
RxD
Receive Data Output (Pin 10)
This pin is the receive data output. A high logic level of
this pin indicates that the mark carrier frequency has been
received, and a low logic level indicates the space carrier
frequency has been received.
SD
Carrier/Call Progress Tone Detect (Pin 9)
This pin is the output from the carrier detector or call progress tone detector. This pin works as a carrier detector in
the FSK mode and as the call progress tone detector in the

MC145444

2-760

CPTO mode. The output goes to a logic low level when the
input signal reaches the minimum threshold of the detect level that is adjusted by the COA voltage. When SO = H, the
receive data output (RxO) is clamped high to avoid errors
that may occur with loop noise. The SO pin is also clamped
high in the other modes except during the power down mode.
TxA1
Non-Inverting Transmit Analog Carrier Output (Pin 18)
This pin is the line driver non-inverting output of the FSK
and tone transmit analog signals. A + 6 dBm (Max) differential output voltage can be obtained by connecting a 1.2 kQ
load resistor between Tx1 and Tx2. Attention must be set
so as not to exceed this level when an external input is added to the OSI pin. A telephone line (600 Q) is driven through
an external 600 Q resistor. In this case, the output level becomes about a half of the differential output.
TxA2
Inverting Transmit Analog Carrier Output (Pin 17)
This pin is the line driver inverting output. The signal is
equal in magnitude, but 1800 out of phase with the TxA 1 (refer
to TxA1).
RxA
Receive Signal Input (Pin 19)
This pin is the receive signal input. The pin has an input
impedance of 50 kQ (Min).
RxGC
Receive Gain Adjust (Pin 20)
This pin is used to adjust the receive buffer gain. To adjust
the gain, the signal from the RxBO through a divider is added
as a feedback. This pin may be held open when the gain
adjustment is not needed.
RxBO
Receiver Buffer Output (Pin 1)
This pin is the receive buffer output.
DSI
Driver Summing Input (Pin 16)
This pin is the inverting input of the line driver. An external
signal is transmitted through an external series resistor ROSI.
The differential gain Gdsi = (VTXA1 - VTXA2)NOSI is determined by the following equation.
'
GDSI = -2RflADSI, AI = 20 kQ

OSI should be left open when not used.
CDA
Carrier Detect LevellCPTD Level Control (Pin 4)
The carrier/call progress tone detect level is programmed
with a COA pin Voltage.
When this pin is held open, the COA voltage is set to 1.2
V with an internal divider. The detect level is set at -44 dBm
(Typ) for off to on, and -47 dBm (Typ) for on to off.The minimum hysteresis is 2 dB. This pin has a very high input impedance so it should be connected to GNO with a 0.1 IlF capacitor to keep it well regulated. An external voltage may be
applied to this pin to adjust the carrier detect threshold. The
following equations may be used to find the CDA voltage
required for a given threshold voltage.
VCDA = 245 x Von
VCDA = 347 x Voff

MOTOROLA COMMUNICATIONS DEVICE DATA

FTLC
Filter Test (Pin 2)
This pin is a high-impedance filter output. It may be used
to check the receive filter. This pin also may be used as a
demodulator input. In normal operation, this pin is connected
to the GNDA through a 0.1 flF bypass capacitor. This pin handles very small signals so care must be used with the
capacitor's wiring.

FSKMode
The transmitter and the receiver work as a FSK
modulator/demodulator. The SD pin output is the carrier's
detect signal.
Table 1. Function Mode Truth Table
M2

M1

MO

0

0

0

FSK

0

0

1

Analog Loop Back

0

1

0

CPTD

0

1

1

Answer Tone

1

0

0

DTMF

1

0

1

Single Tone

SERIAL INTERFACE

1

1

0

Power-Down 1

The following 6 functions are set up with the 15-bit serial
data.

1

1

1

Power-Down 2

TLA
Transmit Carrier Level Adjust (Pin 6)
This pin is used to adjust the transmit carrier level that is
determined by the value of the resistor (RTLA) connected
between this pin and the GND. The maximum transmit level
is obtained when this pin is connected to GND (RTLA = 0).

FUNCTION MODE

:1 M2 1
:1 A3 1
:[i9J

Analog Loopback Mode

M1

MO

A2

A1

AD

TONE FREQUENCY

:1 T3 1 T2

T1

TO

CHANNEL

:~

CARRIER DETECT TIME

:1 CD1 1 COO 1

TRANSMIT ATTENUATOR
TRANSMIT SQUELCH

Function Mode

TxA1 connects to the receiver internally and FSK signals
are demodulated. The frequency of the receiver is set up with
the same frequency as the transmitter. The SD pin output is
the carrier detect signal. An IC self test is supported with this
function.

CPTDMode
The receiver detects a 400 Hz call progress tone. The detect
signal comes from the SD pin. The transmitter is disabled.

Answer Tone Mode
Figure 3 presents the 15-bit serial data timing, starting with
the carrier detect time, CD1 followed by the channel, the tone
frequency, the transmit squelch, the transmit attenuator and
the function mode. This data is loaded into the internal shift
register at the rising edge of the SCK signal and latched at
the falling edge of the ENS signal.
FUNCTION MODE
Modes are selected from the following 3-bit data (M2-MO,
see Table 1).
The following paragraphs describe each function. Table 2
presents each output status.

The transmitter works as 2100 Hz answer tone generator.
The receiver is disabled.

DTMFMode
The transmitter works as a DTMF tone generator. The
receiver is disabled.

Single Tone Mode
The transmitter output is one of DTMF 8 frequencies. The
receiver is disabled.

Table 2. Output Status
Output
RxD

SO

TxA1, TxA2

Received
Digital Data

Carrier
Detect

FSK

CPTD

H

CPTD

VCC/2

Answer Tone

H

H

Answer Tone

DTMF

H

H

DTMFTone

Single Tone

H

H

Single Tone

Hi-Z

Hi-Z

Hi·Z

Function Mode
FSK
Analog Loop Back

Power Down 1, 2

MOTOROLA COMMUNICATIONS DEVICE DATA

MC145444

2-761

Power-Down Mode 1
Inlernal circuits except the oscillator are disabled, and all
outputs except the X1 pin goes to the high impedance state.
The supply current decreases to 300 ~A (Max).
Power-Down Mode 2
All circuits including the oscillator stop working and all
outputs go to the high impedance state. The supply current
decreases to 1.0 ~A (Max).
TRANSMIT ATTENUATOR
Four-bit serial data (A3-AO) sets up the analog transmit
level inthe FSK, answer tone, DTMF, analog loop back and
single tone mode. The range of the transmit allenuator is
0-15 dB in 1 dB steps. The external Signal (DSI) is not
affected by this attenuator.
TONE FREQUENCY
The DTMF tones or the single tone mode is selected by
the 4-bit serial data (T3-TO).

Table 3. Transmit Attenuator Truth Table
A3

A2

A1

AO

Attenuation (dB)

0

0

0

0

0

0

0

0

1

1

0

0

1

0

2

0

0

1

1

3

0

1

0

0

4

0

1

0

1

5

0

1

1

0

6

0

1

1

1

7

1

0

0

0

8

1

0

0

1

9

1

0

1

0

10

1

0

1

1

11

1

1

0

0

12

1

1

0

1

13

1

1

1

0

14

1

1

1

1

15

DATA

SCK

E--------------------------------------------~~
Figure 3. Serial Data Timing
Table 4. Tone Frequency Truth Table
Tone Frequency (Hz)
DTMFMode

MC145444

2-762

T3

T2

T1

TO

Low Group

High Group

Keyboard
Equivalent

Single
Tone Mode

0

0

0

0

941

1633

D

941

0

0

0

1

697

1209

1

697

0

0

1

0

697

1336

2

697

0

0

1

1

697

1477

3

697

0

1

0

0

770

1209

4

770

0

1

0

1

770

1336

5

770

0

1

1

0

770

1477

6

770

0

1

1

1

852

1209

7

852

1

0

0

0

852

1336

8

1336

1

0

0

1

852

1477

9

1477

1

0

1

0

941

1336

0

1

0

1

1

941

1209

.

1336

1

1

0

0

941

1477

#

1477

1

1

0

1

697

1633

A

1633

1

1

1

0

770

1633

B

1633

1

1

1

1

852

1633

C

1633

1209

MOTOROLA COMMUNICATIONS DEVICE DATA

TRANSMIT SQUELCH
The 1-bit serial data (SO) controls the transmit analog
signal. The FSK signal, DTMF tones, single tone, and answer
tone are disabled. The external signal to the DSI will be
transmitted at that time. The internal line driver works at all
times except during the power-down mode.

sa

Von

Vaff

RM----~~+H+++H++HK~H+r_--------

Squelch

1

Enable

0

Disable

~Ion

CHANNEL
The transmit and receive channel is set up with a 1-bit serial
data (CH) when the function mode is either in FSK or analog
loop back.
When the function mode is either on the FSK or analog loop
back mode, the transmit and receive channel is set up with
a 1-bit serial data (CH).
CH

Channel

1

1 (Originate)

0

2 (Answer)

l~tOff

I
Figure 4. Carrier Detect Timing

POWER-ON RESET
When the power is switched on, this device has the following
conditions.

CARRIER DETECT TIME
The carrier detect time (see Figure 4 and Table 5) is set
by 2-bit serial data (CD1, COO). ton indicates the amount of
time the carrier is greater than Von threshold must be present
before SO goes low.
toll, on the other hand, indicates the amount of delay time
SO goes high aiterthe carrier level becomes lower than Voll
threshold.

Function Mode

FSK

Transmit Attenuator

o dB

Transmit Squelch

Enable

Channel

1 (Originate)

Table 5. Carrier Detect Time Truth Table
Carrier Detect Time (Typ)
CD1

COO

ton (ms)

0

0

450

30

0

1

15

30

1

0

15

15

1

1

80

10

toll (ms)

MOTOROLA COMMUNICATIONS DEVICE DATA

MC145444

2-763

r---------_I

GNDA

FTLC

O.lI'F ~

RxA

1----'

RxGC
CDA

O.lI'F

RxBO

T

TxD 1-----1
RxD 1-----1

851-----1

TLA
":"

DATA 1-----1
SCK 1-----1
ENB 1----1

DSI

Xl
3.57945 MHz

CJ
X2

VCC

1------...--4 + 5 V

GND 1 - - - - -....

~

LINE PROTECTION CIRCUIT

J,.

DIGITAL GROUND

~

ANALOG GROUND

Figure 5. Application Circuit

MC145444
2-764

MOTOROLA COMMUNICATIONS DEVICE DATA

MOTOROLA

-

SEMICONDUCTOR
TECHNICAL DATA

MC145447

Calling Line Identification (CLIO)
Receiver with Ring Detector
The MC145447 is a silicon gate HCMOS IC designed to demodulate Bell 202
and V.23 1200-baud FSK asynchronous data. The primary application for this
device is in products that will be used to receive and display the calling number,
or message waiting indicator sent to subscribers from participating central office
facilities of the public switched network. The device also contains a carrier detect
circuit and ring detector which may be used to power up the device.
Applications forthis device include adjunct boxes, answering machines, feature
phones, fax machines, and computer interface products.
The MC145447 offers the following performance features.
•
•
•
•
•
•
•

PSUFFIX
PLASTIC DIP
CASE 648

1• •

ORDERING INFORMATION

Ring Detector On Chip
Ring Detect Output for MCU Interrupt
Power Down Mode, Less Than 1 ~A
Single Supply: +3.5 to +6.0 V
Pin Selectable Clock Frequencies: 3.68 MHz, 3.58 MHz, or 455 kHz
Two Stage Power Up for Power Management Control
Demodulates Bell 202 and V.23

MC145447P
MC145447DW

Plastic DIP
SOG Package

PIN ASSIGNMENT
TI [

1•
RI[ 2

ROil [ 3

BLOCK DIAGRAM

16P VDD
15P DOC
14P DOR

RDI2 [ 4

13P COO

NC [ 5

12p ROO

Rf [ 6
PWRUP [ 7
VSS [ 8
TIP
RING

DWSUFFIX
SOG
CASE 751G

11 P ClKSIN
10 P OSCin
9P OSCout

NC = NO CONNECTION
.--_ _ _-'1.'-4~ DATA OUT RAW
(DOR)
DATA OUT
COOKED (DOC)

RING DET IN 1 (ROil)

~

C:.:.=J----'

q

CARRIER DETECT OUT
(COO)

~

RING DETECT OUT

~

(ROO)

PWRUP _.!....7_-l
11

1---'"

ClK SELECT IN (ClKSIN)
3.58 MHz, 3.68 MHz,
OR 455 kHz

OSCin _1"'0---------1

-.1Lo VDD (16)
OSCout..--"-------------'

~

VSS(8)

NO CONNECT (5)

MOTOROLA COMMUNICATIONS DEVICE DATA

MC145447
2-765

ABSOLUTE MAXIMUM RATINGS (Voltages referenced to GND, except where noted)
Symbol

Rating
DC Supply Voltage

Value

Unit

VDD

-0.5 to +6.0

V

Yin

-0.5 to VDD+0.5

V

I

±10

mA

Input Voltage, All Pins
DC Current Drain Per Pin
Power Dissipation

PD

20

Operating Temperature Range

TA

a to +70

Tst!l

-40 to +150

Storage Temperature Range

ELECTRICAL CHARACTERISTICS
(All polarities referenced to VSS 0 V, VDD

=

This device contains circuitry to protect
the inputs against damage due to high static
voltages or electric fields. However, it is advised that normal precautions be taken to
avoid applications of any voltage higher
than maximum rated voltages to this high
impedance circuit. For proper operation it Is
recommended that Yin and Vout be constrained to the range VSS S; (Vin or Vout) S;
VDD·
Reliability of operation is enhanced if unused inputs are tied to an appropriate logic
voltage level (e.g., either VSS or VDD).

mW
)

°C
°C

=+5 V ±10%, unless otherwise noted, TA =0 to + 70°C)
Symbol

Min

Typ

Max

DC Supply Voltage

VDD

3.5

5

6

V

Supply Current (All Output Pins Unloaded) (See Figure 1)
RT O. PWRUP 1, XTAL 3.58 MHz

IDD

-

2.4

3

mA

Supply Current (All Output Pins Unloaded) (See Figure 1)
PWRUP = 0, RT = Don't Care, XTAL = 3.58 MHz

IDD

-

6.2

8

mA

ISTBY

-

-

1

).LA

-

VDDXO.3

Parameter

=

=

=

Standby Current (All Output Pins Unloaded) (See Figure 1)
RT = 1, PWRUP = 1
Input Voltage a Level (CLKSIN, OSCin)

VIL

-

Input Voltage 1 Level (CLKSIN, OSCin)

VIH

VDDXO.7

Output Voltage High: VDD = 5 V (DOR, DOC, OSCoutl

VOH
IOH = 40).LA
IOH S; 1 ).LA

Output Voltage Low: VDD = 5 V (DOR, DOC, OSCout)

,

VOL

Input Leakage Current (OSCin, CLKSIN, PWRUP, RT, RDI1, and RDI2)

Input Threshold Voltage Positive Going: VDD
(RDI1, RT, PWRUP) (See Figure 3)

=5 V

Input Threshold Voltage Negative Going: VDD = 5 V
(RDI1, RT, PWRUP) (See Figure 3)
RDI2 Threshold
TIP/RING Input dc Resistance

ANALOG CHARACTERISTICS (VDD

-

-

lin

-

-

±1

).LA

-

0.4

V

VT+

2.5

2.75

3.0

V

VT-

2.0

2.3

2.6

V

RD2VT

1.0

1.1

1.2

V

Rin

-

500

-

kQ

Input Sensitivity: TIP and RING (Pins 1 and 2, VDD = +5 V)

Carrier Detect Sensitivity

MC145447
2-766

V

VOL

=+5 V, TA =+25°C, unless otherwise noted, 0 dBm =0.7746 Vrms @

a dBm)

V

0.4
0.05

Characteristic

Band-Pass Filter (BPF)
Frequency Response (relative to 1700 Hz @

V
V

2.4
4.95

IOL= 1.6mA
IOL S; 1 ).LA

Output Voltage Low: VDD = 5 V (RDO, RT, CDO) IOL = 2.0 mA

-

Unit

60 Hz
500 Hz
2700 Hz
;;, 3300 Hz

6000)

Min

Typ

-40

-45

-

-

-64
-4
-3
-34

-

-48

Max

Unit
dBm
dB

dBm

MOTOROLA COMM,uNICATIONS DEVICE DATA

SWITCHING CHARACTERISTICS (VDD = +5 V, CL = 50 pF, TA = +25°C)
Description

Symbol

Min

Typ

Max

Unit

tOOSC

-

2

ms

tsuPO

15

-

-

OSC Startup
Power-Up Low to FSK (Setup Time)
Carrier Detect Acquisition Time

tOAQ

-

14

End of Data to Carrier Detect High

tOCH

B

-

ms
ms
ms

TIMING DIAGRAM

I

2 SECONDS

0.5

SECOND

I

I

RI

n
I ~
H

I
I
I
I
I
I
I
I

I
I
I
I
I
I

I
I

PWRUP

I

DATA

Rf

ROO

0.5

SECOND

tSUPD

tI

II I

I

tDAQ~1

tDCH~

COO

I
DOC
COOKED DATA

RAW DATA

~tDOSC

II

OSC

I
I

DOR

II
I

I

CLOCK 3.58 MHz, 3.6864 MHz, OR 455 kHz

MOTOROLA COMMUNICATIONS DEVICE DATA

MC145447
2-767

VDD
TI
AI
ADll
ADI2 4
NC 5

16

AT
PWAUP

15
14
13
12
11
10
9

-=
AT
0
X

PWAUP
1
1
0

DOC
DOA
CDO
ADO
CLKSIN
OSCin
OSCout

}~
VDD

0

3.579 MHz

OSCin
'DD
lIlA MAX DISABLE
2.4 rnA TYP ENABLE
6.2 rnA TYP ENABLE

10MQ

T

I

30
pF

Figure 1. 100 Test Circuit

PIN DESCRIPTIONS
TI
Tip Input (Pin 1)
This input pin is normally connected to the tip side of the
twisted pair. It is internally biased to 1/2 supply voltage when
the device is in the power up mode. This pin must be dc
isolated from the line.
RI
Ring Input (Pin 2)
This input is normally connected to the ring side of the
twisted pair. It is internally biased to 112 supply voltage when
the device is in the power up mode. This pin must be dc
isolated from the line.

VSS
Ground (Pin 8)
Ground return pin is typically connected to the system
ground.
OSCout
Oscillator Output (Pin 9)
This pin will have either a crystal or a ceramic resonator
tied to it with the other end connected to OSCin.
OSCin
Oscillator Input (Pin 10)
This pin will have either a crystal or a ceramic resonator
tied to it with the other end connected to OSCout. OSCin may
also be driven directly from an appropriate external source.

ROil
Ring Detect Input 1 (Pin 3)
This input is normally coupled to one of the twisted pair
wires through an attenuating network. It detects energy on
the line and enables the oscillator and precision ring
detection circuitry.

CLKSIN
Clock Select Input (Pin 11)
A logic 1 on this input configures the device to accept either
a 3.579-MHz or 3.6B64-MHz crystal. A logiC 0 on this pin
configures the part to operate with a 455-kHz resonator.
For crystal and resonator specifications see Table 1.

RDI2
Ring Detect Input 2 (Pin 4)
This input to the preCision ring detection circuit is normally
coupled to one of the twisted pair wires through an attenuating
network. A valid ring signal as determined from this input
sends the ROO (Pin 12) to a logic O.

ROO
Ring Detect Out (Pin 12)
This open-drain output goes low when a valid ringing signal
is detected. ROO remains low as long as the ringing signal
remains valid. This signal can be used for auto power up, when
connected to pin 7.

RT
Ring Time (Pin 6)
An RC network may be connected to this pin. The RC time
constant is chosen to hold this pin voltage below 2.2 V
between the peaks of the ringing signal. RT is an internal
power-up control and activates only the circuitry necessary
to determine if the incoming ring is valid.

COO
Carrier Detect Output (Pin 13)
When low, this open drain output indicates that a valid
carrier is present on the line. COO remains low as long as
the carrier remains valid. An B-ms hysteresis is built in to allow
for a momentary drop out of the carrier. COO may be used
in the auto power up configuration when connected to
PWRUP.

PWRUP
Power Up (Pin 7)
A logic 0 on the PWRUP input causes the device to be
in the active mode ready to demodulate incoming data. A
logic 1 on this pin causes the device to be in the standby
mode, if the RT input pin is at a logic 1. This pin may be
controlled by ROO and COO for auto power-up operation.
For other applications, this pin may be controlled externally.

MC145447
2·768

DOR
Data Out Raw (Pin 14)
This pin presents the output of the demodulator whenever
COO is low. This data stream includes the alternate 1 and 0
pattern, and the 150 ms of marking, which precedes the data.
At all other times, DOR is held high.

MOTOROLA COMMUNICATIONS DEVICE DATA

DOC
Data Out Cooked (Pin 15)
This output presents the output of the demodulator
whenever CDO is low, and when an internal validation
sequence has been successfully passed. The output does not
include the alternate 1 and 0 pattern. At all other times, DOC
is held high.
VDD
Positive Power Supply (Pin 16)
The digital supply pin, which is connected to the positive
side of the power supply.

APPLICATIONS INFORMATION
The MC145447 has been designed to be one of the main
functional blocks in products targeted for the CLASS (Custom
Local Area Signaling Service). market. CLASS is a set of
subscriber features now being presented to the consumer by
the RBOCs (Regional Bell Operating Companies) and
independent TELCOs. Among CLASS features, such as
distinctive ringing and selective call forwarding, the subscriber
will also have available a service known as Calling Number
Delivery (CND) and message waiting. With these services,
a subscriber will have the ability to display at a minimum, a
message containing the phone number of the calling party,
the date, and the time. A message containing only this
information is known as a single format message, as shown
in Figure 9. An extended message, known as multiple format
message, can contain additional information as shown in
Figure 10.
The interface should be arranged to allow simplex data
transmission from the terminating central office, to the CPE
(Customer Premises Equipment), only when the CPE is in an
on-hook state. The data will be transmitted in the silent period
between the first and second power ring after a voice path
has been established.
The data signaling interface should conform to Bell 202,
which is described as follows:
•
•
•
•
•

Analog, phase coherent, frequency shift keying
Logical 1 (Mark) = 1200 ± 12 Hz
Logical 0 (Space) = 2200 ±22 Hz
Transmission rate = 1200 bps
Application of data = serial, binary, asynchronous

The transmission level from the terminating C.O. will be
-13.5 dBm ± 1.0. The expected worst case attenuation
through the loop is expected to be -20 dB. The receiver
therefore, should have a sensitivity of approximately -34.5
dBm to handle the worst case installations.
Additional information on CLASS services can be obtained
from:
BELLCORE CUSTOMER SVS.
1-800-521-2673
201-699-5800 FOREIGN CALLS
201-699-0936 FAX
The document number is: TA-NWT-000030
Title: "Voice Band Data Transmission Interface Generic
Requirements"
Figure 7 is a conceptual deSign of how the MC145447 can
be implemented into a product which will retrieve the incoming
message and convert it to EIA-232 levels for transmission to
the serial port of a PC. With this message and appropriate

MOTOROLA COMMUNICATIONS DEVICE DATA

software, the PC can be used to look up the name and any
additional information associated with the caller that had been
previously stored.
Figure 8 is a conceptual design of an adjunct unit in parallel
with an existing phone. This arrangement gives the subscriber
CND service without having to replace existing equipment.
Table 1. Oscillator Specifications
Clock Select Pin 11 = 1
Crystal Mode
Frequency
Rf
C1 and C2

Parallel
3.579 MHz or 3.6864 MHz
10 MQ
30 pF

Source:
Fox Electronics
5570 Enterprise Pkwy.
Ft. Myers, FL 33905
Tel. 813·693·0099

Clock Select Pin 11 = 0
Resonator
Frequency
Rf
C1 and C2

#CSB455J
455 kHz ±a.5%
1.0MQ
100 pF

Source:
Murata Manufacturing Co. Ltd.
2200 Lake Park Dr.
Smyma, GA 30080
Tel. 404-436-1300
Note:
Motorola cannot recommend one supplier over another and
in no way suggests that this is a complete listing.
FULL-TIME POWER-UP APPLICATION WITH RING
DETECTOR CIRCUIT DISABLED
Some MC145447 applications require that the Calling
Line Identification Receiver be constantly powered. To
ensure that the device is properly reset, a Logic 1 must be
applied to PWRUP (Pin 7) for a minimum of 10 IlS after VDD
has reached its full value. It is also necessary that the RT
pin (Pin 6) be high while PWRUP is high. This may be
accomplished with an external ring detect signal or MCU
generated signal applied to PWRUP. Alternatively, a power
on reset RC network may be used as shown in Figure 6.
Rpu and Cpu must be chosen such that the voltage at
PWRUP meets the logic 1 input threshold requirements for
10 IlS afterVDD has reached its full value. The powersupply
rise time on VDD (Pin 16) must also be taken into account
when determining Rpu and Cpu. See Figure 3 for a
description of the change in input thresholds (VT + and VT-)
with respect to VDD for PWRUP. Also, some applications
may not require the ring detect function. In this case, RDI1
(Pin 3) and RDI2 (Pin 4) should be tied to VSS and RT tied
to VDD as shown in Figure 6.

MC145447

2-769

DESIGN INFORMATION
The circuit in Figure 2 illustrates in greater detail the
relationship between device pins 3, 4, 6, and 7.
The external component values shown in Figure 2 are
the same as those shown in Figures 7 and 8. When VDD
is applied to the circuit in these two figures, the RC network
will charge cap C1 to VDD holding RT (Pin 6) off. If the
PWRUP (Pin 7) is also held at VDD, the MC145447 will be
in a power down mode, and will consume 1 IlA of supply
current (Max).
The resistor network (R2-R4) attenuates the incoming
power ring applied to the top of R2. The values given have
been chosen to provide a sufficient voltage at RDI1 (Pin 3)
to turn on the Schmitt trigger input with approximately a 40
Vrms or greater power ring input from tip and ring. When VT+
of the Schmitt is exceeded, Q1 will be driven to saturation
discharging cap C1 on RT. This will initialize a partial power
up, with only the portions of the part involved with the ring
signal analysis enabled, including RDI2 (Pin 4). At this time
the MC145447 power consumption is increased to approximately 2.4 mA (typ).
EXTERNAL
COMPONENTS

,

INTERNAL
COMPONENTS

__________ 7'

~~u~------------,

Rl
270kQ

TO
BRIDGE

470kQ
R2
R3
18kQ

R4
15kQ

Figure 2.
The value of R1 and C1 must be chosen to hold the RT
pin voltage below the VT+ of the RT Schmitt between the
individual cycles of the power ring. The values shown will work
for ring frequencies of 15.3 Hz (min).
With RDI2 now enabled, a portion of the power ring above
1.2 V is fed to the ring analysis circuit. This circuit is a digital
integrator which looks at the duty cycle of the incoming signal.
When the input to RDI2 is above 1.2 V, the integrator is
counting up at an 800 Hz rate. When the input to RDI2 falls
below 1.2 V, the integrator counts down at a 400 Hz rate.

MC145447

2·770

3.5

,,YT+

3.25
3.0

/

2.75
2.5
2.25

,/"

2.0

/

1.75
1.5

./'"

L
~

./'"

V

~

V

VT-

,.....

V

,-/'

1.25
1.0

U

M

M

M

U

~

~

M

M

VDD

Figure 3. VOO versus VT+ and VTA ring is qualified when an internal count of binary 48 is
reached. The ring is disqualified when the count drops to a
binary 32. The number of ring cycles required to qualify the
signal will depend on the amplitude of the voltage presented
to RDI2. The shortest amount of time needed to do the
qualification is approximately 60 ms. The shortest amount of
time required for dequalification will be approximately 40 ms.
Once the ring signal is qualified, the RDO pin will be sent
low. This can be fed back to PWRUP as shown in Figure 7,
or with a pull-up resistor, can be used as an interrupt to an
MCU as shown in Figure 8. In either case, once the PWRUP
pin is below VT_, the part will be fully powered up, and ready
to receive FSK. During this mode, the device current will
increase to approximately 6.2 mA (typ). The state of the RT
pin is now a "don't care" as far as the part is concerned.
Normally, however, this pin will be allowed to return to VDD.
After the FSK message has been received, the PWRUP
pin can be allowed to return to VDD and the part will return
to the standby mode, consuming less than 1 IlA of supply
current. The part is now ready to repeat the same sequence
for the next incoming message.
TYPICAL DEMODULATOR PERFORMANCE
The following describes the performance of the MC145447
demodulator in the presence of noise over a simulated Bell
3002 telephone loop.
The Bell 3002 loop represents a worst case local telephone
loop in North America. The characteristics of this loop, which
affect performance, are high frequency attenuation and
Envelope Delay Distortion (EDD) or group delay.
The minimum receiver sensitivity of the MC145447 under
these conditions is typically -45 dBm.
The MC145447 achieves a Bit Error Rate (BER) of 1 x 10-5
at a Signal-to-Noise Ratio (SNR) of 15 dB in V.23 operation
and at an SNR of 18 dB in Bell 202 operation (see Figures
4 and 5).
All measurements in dBm are referenced to 600 Q: 0 dBm
= 0.7746 Vrms.
All measurements were taken using the MC145460EVK
evaluation board.

MOTOROLA COMMUNICATIONS DEVICE DATA

:::::

~
w
Cl

~

II:

1.,.-

~

~

/

OJ

1/

e4

19'

5

fY

!If
.(l"rv

W

~

Cl

~-

/'
10

12

14

16

1B

20

10

22

Figure 4. MC145447 V.23 Operation
(Typical BER vs SNR)

VOO

10kQ
500 pF

RING

I
J

II

L

10k(}

VOO

I

16

18

20

22

16

"'!:-

0)1'1

TI

1

RI

2

14

OOR

ROil

3

13

COO

ROl2

4

12

ROO

N/C

5

11

CLKSIN

10

OSCin

9
I---

OSCout

--=RT 6
PWRUP

7

+5V

-=-

14

Figure 5. MC145447 Bell 202 Operation
(Typical BER vs SNR)

50o pF

I

12

SNR - Signal to Noise Ratio (dB)

SNR - Signal 10 Noise Rallo (dB)

TIP

f5

JY

II:

P'"

/

13'

4

iii

-<

II:

2

~
w

,0

w

/

II:

/'

iii 3
Cl

i

6

II:

W

7

W

~

Cpu

'----'
Rpu
L-

8

DOC

15

J-

VOO

.---JDI--3.579 MHz

30pF

T

10MQ

1

30PF

Figure 6.

MOTOROLA COMMUNICATIONS DEVICE DATA

MC145447

2-771

APPLICATION CIRCUIT
500pF
C3

MC145447

f-----:L-=

VDD

10kQ

O.II'F
16

TI

1N4004x4

15
14
13
12

RI
RDII
RDI2 4
500 pF

NC

11 CLKSIN

AT

10 OSCin

PWRUP7

TO PC
VDD

I
IL _ _ _ ..l
MC!45407

OSCout

0

..L

470kQ
18kQ

15kQ

TO PC

DOC
DOR
CDO
RDO

3.579 MHz

+5V

+5V

30 PF

4.7 MQ
NOTE: C1 and C2 "0.2I'F required for line
isolation. C1 through C4 are 250 V
min., non-polarized.

I

T

10MQ

T

30pF

'---l"

O.33 I'F

Figure 7_ Partial Implementation of PC Interface to Tip and Ring

FIRST RING
2 SECONDS

I I

I

0.5
SEC

0.5
SEC

SECOND RING
2 SECONDS

RI

AT
- - - - - - - - - -i-------j 1
~

__
0_.211_F.I

..-

3.68 MHz

-=

l

DISPLAY

J

Figure 8. Adjunct Box Concept for Calling Number Display

FIRST RING
2 SECONDS

I

I

0.51
SEC

0.51
SEC

"II

ATI

PWRUP

COO
DOC

h
I
I
I
I

1

1

I

I

INTERRUPT
FORMCU

7.f

1

1

_I

1•••1

I
I
I
I
I

I
I
I
I
I

DATA

DOR:

OSC

If

DATA

RI

ROO

SECOND RING
2 SECONDS

DATA

3_.5_8_MH_Z_,3_~~__4,_OR_4_55_k_HZ____________

1-1_ _ _ _ _ _ _ _ _

I
I
I

//

I:

! //
~~r------------------~~

NOTES
1. MCU must assert PWRUP to MCI45447.
2. No data detected, MCU powers down the MCI45447.

Timing Diagram for Figure 8
MOTOROLA COMMUNICATIONS DEVICE DATA

MC145447

2-773

4s ---------------t~.~-----2s~

I

0~5_+

.".,., 'E--Jr

STD RING/20 Hz

DATA WORD

TYPE WORD

L...-"":":":'=----'

...............

MARKS

SUM

CH - - - - - - - - - - - 1 SUPERFRAME (12 ms)

1. . .

-J

IRQ1,IRQ2
BR1 UPDATED FROM
RECEIVED M4 CHANNEL
nebe STATUS BIT UPDATED
R6 UPDATED FROM
RECEIVED eoc CHANNEL

----------·~I

1
_60,+8,-2QUATS

1. .

> - - - - - - - - - - - - 1 SUPERFRAME (12 ms)

LT
TxDATA

----------~.I

4

1

1

QUAT 117

QUAT 117

TRANSMITIED M4 UPDATED
FROM BRO
TRANSMITIED M5 AND M6 CHANNELS
UPDATED FROM BR2
TRANSMITIED eoc UPDATED FROM R6
Tx SFS PULSE OUTPUT ON PIN 25.
SEE NOTE.

TRANSMITIED eoc UPDATED FROM R6

NOTE:
Due to internal superframe delays the actual sync word marker on the TxP and TxN pins occurs 8 quats prior to the
Tx SFS pulse. This causes the Tx SFS pulse to appear during Quat 113 ± 1 at pin 25. Internal to the MC145472 the
Tx SFS pulse is generated during Quat 117.

Figure 18. LT Mode Maintenance Channel Updates

MC145472.MC14LC5472
2-798

MOTOROLA COMMUNICATIONS DEVICE DATA

IDLRx
IDLSVNC
IDLCLK
IDL Tx

SCPEN
SCPCLK
SCPRx
SCPTx

AUTOMATIC eae
PROCESSOR

XTALin
XTALaut

Figure 19. U-Interface Loop-Back Block Diagram

IDLSVNC
IDLCLK

SCPEN
SCPCLK
SCPRx
SCPTx

AUTOMATIC eae
PROCESSOR

XTALin
XTALaut

Figure 20. IDL Interface Loop-Back Block Diagram

MOTOROLA COMMUNICATIONS DEVICE DATA

MC145472.MC14LC5472
2-799

Superframe Framer-to-Deframer Loop-Back
Superframe Framer-to-Deframer Loop-back is shown in
Figure 21. As the shaded portion of the.block diagram shows,
this loop-back mode takes Band D channel data in at the
IDL Rx pin and M channel data via the SCP, performs all of
the superframe framing and subsequent deframing functions,
and sends the same data back out the IDL Tx pin and SCPo
This loop-back mode is intended primarily for diagnostic
purposes.
External Analog Loop-Back
External Analog Loop-back is shown in Figure 22. As the
shaded portion of the block diagram shows, this loop-back
mode takes Band D channel data in at the IDL Rx pin and

AUTOMATIC eoc
PROCESSOR

transmits the data out the Tx Driver pins. The 2B10 signal
passes through the external line interface circuitry and back
into the receiver input pins. The signal is then recovered and
sent out the IDL Tx pin. Note that the external line interface
has been physically disconnected from the U-Interface
twisted wire pair.
Since the entire 2B10 superframe is being looped back,
loop-back data includes the 2B+D channels and all of the
M channels. For instance, data wrillen by an external
microcontroller to the eoc, M4, and MS/M6 registers, (R6,
BRO, and BR2), is looped back and can be read from the
eoc, M4, and MS/M6 registers, (R6, BR1, and BR3).

XTALln
XTALout

Figure 21. Superframe Framer-to-Deframer Loop-Back Block Diagram

AUTOMATIC aoc
PROCESSOR

XTALin
XTALout

Figure 22. External Analog Loop-Back Block Diagram
MC145472.MC14LC5472

2-800

MOTOROLA COMMUNICATIONS DEVICE DATA

MOTOROLA

-

SEMICONDUCTOR
TECHNICAL DATA

MC145474
MC145475

Technical Summary

ISDN SIT Interface Transceiver
This technical summary provides a brief description of the MC145474 and
MC145475 SfT Interface Transceivers. A complete data book for the
MC145474n5 is available and can be ordered from your local Motorola
Semiconductor Sales Office (order number MC145474/D).
The MC145474n51SDN SfT transceiver provides an economical VLSI Layer 1
interface for the transportation of two 64 kpbs B channels and one 16 kpbs
o channel between the network termination or NT and terminal equip- ment
applications or TEs. Both the MC145474 and the MC145475 conform to CCITT
1.430 and ANSI Tl.605 specifications.
The MC145474/75 provides the modulation/line drive and demodulation/line
receive functions required of the interface. In addition, the MC145474n5 provides the activation/deactivation, error monitoring, framing, bit, and octet timing.
The MC145474n5 provides the control signals for the interface to the Layer 2
devices. Complete multiframe capability is provided.
The MC145474n5 features to Interchip Digital Link (IDL) for the exchange of
2B+D channel information between ISDN components and systems. The
MC145474n5 provides an industry standard serial control port (SCP) to program
the operation of the tranceiver.

22~

PSUFFIX
PLASTIC
CASE 7368

OW SUFFIX

SOG

26

CASE 751F

ORDERING INFORMATION
MC145474P
MC145475DW

Plastic

SOG

• Conforms to CCITT 1.430 and ANSI T1.605 Specifications
• Detects Far-End Code Violations (FECVs) in the NT Mode
• Incorporates the IDL
• Pin Selectable NT or TE Modes of Operation
• Industry Standard Microprocessor SCP
• Supports 1: 1 Transformers for Transmit and Receive
• Exceeds the Recommended Range of Operation in all Configurations
• Complete Multiframing Capability Supported (SC1-SC5 and Q Channel)
• Optional B Channel Idle, Invert, or Exchange
• Supports Full Range of SfT and IDL Loopbacks
• Supports Transmit Power Down and Absolute Minimum Power Mode
• Supports Crystal or External Clock Input Modes
• MC145475 Bonded Out for NT1 Star Mode of Operation
• CMOS Design for Low Power Operation
• The MC14LC5494EVK may be used to evaluate the MC145474

This document contains information on a new product. Specification and information herein are subject to change without notice.

MOTOROLA COMMUNICATIONS DEVICE DATA

MC145474.MC145475
2-801

BLOCK DIAGRAM
ISET
TxP

2B+D
IDLVO
CONTROL

MODULATE
CONTROL

M+ABITS

TxN

DREOIFlX
DGRNT/FSYNC
MAIN
CONTROL
LOGIC

RESET
TE/NT
XTAL
EXTAL
SCPEN
SCPCLK
SCPTx -C
SCPRx
IRQ II

DEMODULATION
CONTROL
+
TIMING
RECOVERY

S+QBITS

RxP
RxN

PIN ASSIGNMENT

MC145475

MC145474

SOGPACKAGE

PLASTIC PACKAGE

DGRNTIFSYNC

5

ANDin

6

28P RESET
27p TxP
26P TxN
25P XTAL
24 P EXTAL
23 P EXTAlJ2

Vss

7

22

VDD

FSYNCIANDout

8

21

AONT

DREOIFIX

ISET

1-

RxN

2

RxP

3

TOO

4

ISET

RESET

RxN

TxP

RxP

TxN

TOO
DGRNT/FSYNC
Vss

XTAL
EXTAL
VDD
IRQ

IDLSYNC

SCPEN

9

20

IRQ

IDLCLK

SCPCLK

CLAss/ECHOin

10

19

LBACTIVE

IDLRX

SCPRX

IDLSYNC

11

18

SCPEN

IDL TX

SCPTX

IDLCLK

12

17

SCPCLK

MC145474.MC145475
2-802

IDLRX

13

16

SCPRX

IDL TX

14

15

SCPTX

MOTOROLA COMMUNICATIONS DEVICE DATA

ABSOLUTE MAXIMUM RATINGS
Rating
Supply Voltage
Input Voltage (any pin to VSS)

Symbol

Value

Unit

VOO

-0.3to+7.0

V

Vln

- 0.3 to VOO + 0.3

V

I

±10

rnA

TA

-40to+85

"C

Tstg

-85to +150

"C

DC Current, any pin (excluding VDD, VSS,
TxP, and TxN)
Operating Temperature
Storage Temperature

This device contains circuitry to protect
the Inputs against damage due to high
static voltages or electrical fields; however,
it Is advised that nonnal precautions be
taken to avoid applications of any voltage
higher than maximum rated voltages to this
high-impedance circuit. For proper operation, It is recommended that Yin and Vout
be constrained to the range V SS S (Vin or
Voutl 2: VDO. Reliability of operation is
enhanced if unused digital inputs are tied to
an appropriate logic voltage level (e.g.,
either VSS or VOD).

DIGITAL DC ELECTRICAL CHARACTERISTICS (CMOS MODE, BR13(6) = 0)
(TA = - 40 to + 85"C, VDD = 5.0 V ± 10%, Voltages referenced to VSS)
Characteristics

Symbol

Min

Max

Unit

VIH

3.5

-

V

VIL

-0.3

1.5

V

5

I1A

10

I1A

Cin

-

10

pF

VOH

2.4

-

V

Input High Voltage
Input Low Voltage
Input Leakage Current

@

5.5 V

lin

High-Impedance Input Current @ 4.5/0.5 V

Ilkg(Z)

Input Capacitance
Output High Voltage (IOH = -400 1lA)

VOL

-

0.5

V

VIH(X)

3.5

-

V

XTAL Input Low Level

VIL(X)

-

0.5

V

EXTAL Output Current (YOH = 4.6 V)

IOH(X)

-

-400

I1A

EXTAL Output Current (VOL = 0.4 V)

IOL(X)

-

400

I1A

1FiQ Output Low Current (VOL = 0.4 V)

1.7

mA

1FiQ Output Off-State Impedance

100

-

kn

Output Low Voltage (IOL = 5.0 mAl
XTAL Input High Level

DIGITAL DC ELECTRICAL CHARACTERISTICS (TTL MODE, BR13(6)
(TA = - 40 to + 85"C, VDD = 5.0 V ±10%, Voltages referenced to VSS)

=1)
Symbol

Min

Max

Unit

Input High Voltage

Characteristics

VIH

2.0

-

V

Input Low Voltage

VIL

-0.3

0.8

V

Nota: The MC145474175 can be programmed to accept TTL levels on all digital Input pins (this does not Include XTAL and EXTAL). The
MC145474175Is configured for TTL mode by writing a 1to BR13(6). Programming the MC145474175forTTLmode has no effect on eitherthe digital
output pins, the crystal circuit, TxPlTxN, or RxP/RxN. Thus, the only dc electrical characteristics that differ, when operating in the CMOS mode,
are the input voltages accepted on the digital Inputs.

ANALOG CHARACTERISTICS (TA = - 40 to + 85"C, VOO = 5.0 V ± 10%, Voltages referenced to VSS)
Characteristics

Min

Typ

Max

13.5

15

16.5

mA

(TxP - TxN) Voltage Limit

-

1.17

Vpeak

Input Ampliftude (RxP - RxN)

35

-

-

mVpeak

TxPlTxN Drive Current

MOTOROLA COMMUNICATIONS DEVICE DATA

RL=50n

Unit

MC145474.MC145475
2-803

POWER D1SSIPTION (TA = - 40 to + 85"C, VDD = 5.0 V ± 10%, Voltages referenced to VSS)
Min

Typ

Max

Unit

DC Supply Voltage (VDD)

4.5

5.0

5.5

V

Worst Case Power Consumption

-

-

175

mW

1

75

mW

2

-

-

40

mW

2

Characteristics

=1)
Absolute Minimum Power (NR1(1) =1)

Transmit Power Down (NR1(2)

Notes

NOTES:
1. The worst case power consumption occurs when the MC145474175 is transmitting a96 kHz test tone (BRH (0) = 1) into a50 n load resistor.
The 15.36 MHz clock is being provided by the crystal as depicted in Figure 1.
2. The power consumption figures for transmit power-down and absolute minimum power are both determined with the crystal circuit as depicted in Figure 1 still connected and operational.
IDL TIMING CHARACTERISTICS (NT MODE, IDL SLAVE) (TA = - 40 to + 85"C, VDD = 5.0 V ± 10%, Voltages referenced to VSS)
Characteristics

Ref #

1

Time Between Successive IDL SYNCs

Min

Max

Unit

Note 1

2

IDL SYNC Active after IDL CLK Falling Edge (Hold Time)

30

3

IDL SYNC Active before IDL CLK Falling Edge (Setup Time)

30

-

ns
ns

4

IDL CLK Period

5

IDL CLK Width High

70

Note 2

-

ns

6

IDL CLK Width Low

70

ns

7

IDL Rx Valid before IDL CLK Falling Edge (Setup Time)

30

-

8

IDL Rx Valid fater IDL CLK Falling Edge (Hold Time)

30

-'

ns

9

IDL Tx Time to High Impedance

30

ns

10

IDL Tx High Impedance to Active State

70

ns

11

IDL CLK to IDL Tx Active

-

70

ns

ns

NOTES:
1. IDL SYNC is an 8 kHz signal. The phase relationship between IDL SYNC and IDL CLK is as described earlier.
2. IDL CLK Input frequency can be run at 1.536 MHz, 1.544 MHz, 2.046 MHYz, 2.56 MHz, or 4.098 MHz.

XTAL
30pF

I
10Mn

Vss

D

15.36 MHz
AT CUT QUARTZ
CRYSTAL

EXTAL

I

30PF

Vss
Figure 1. Crystal Circuit

MC145474.MC145475
2-804

MOTOROLA COMMUNICATIONS DEVICE DATA

IDl TIMING CHARACTERISTICS (NT MODE IDl MASTER OR TE MODE WITH THE IDl ClK RATE SET TO 2.56 MHz)
(TA =- 40 to + 85°C, VDD = 5.0 V ± 10%, Voltages referenced to VSS)
Ref #

Characteristics

1

Time Between Successive IDl SYNCs

Min

Max

Unit

Note 1

2

IDl SYNC Active aiter IDl ClK Falling Edge (Hold Time)

160

230

ns

3

IDl SYNC Active before IDl ClK Falling Edge (Setup Time)

160

230

ns

4

IDl ClK Period

5

IDl ClK Width High

Note 2

6

IDl ClK Width low

Note 2

7

IDl Rx Valid before IDl ClK Falling Edge (Setup Time)

30

-

ns

8

IDl Rx Valid fater IDl ClK Falling Edge (Hold Time)

30

-

ns

9

I Dl Tx Time to High Impedance

0

30

ns

10

IDl Tx High Impedance to Active State

-

45

ns

11

IDl ClK to IDl Tx Active

-

45

ns

Note 2

NOTES:
1. IDl SYNC is an 8 kHz signal. The phase relationship between IDl SYNC and IDl ClK is as described earlier.
2. In NT Mode IDl Master or TE Mode, the IDl ClK is generated internally in the MC145474f75. When configured for 2.56 MHz operation,
IDl ClK is the crystal frequency divded by 6 and has a 50% duty cycle.

IDl TIMING CHARACTERISTICS (NT MODE IDl MASTER OR TE MODE WITH THE IDl ClK RATE SET TO 2.048 MHz)
(TA =- 40 to + 85°C, VDD =5.0 V +
- 10%, Voltages referenced to VSS)
Ref #

Characteristics

1

Time Between Successive IDl SYNCs

Min

Max

Unit

Note 1

2

IDl SYNC Active aiter IDl ClK Falling Edge (Hold Time)

210

280

ns

3

IDl SYNC Active before IDl ClK Falling Edge (Setup Time)

210

280

ns

Note 2

4

IDl ClK Period

5

IDl ClK Width High

Note 2

6

IDl ClK Width low

Note 2

7

IDl Rx Valid before IDl ClK Falling Edge (Setup Time)

30

-

ns

8

IDl Rx Valid fater IDl ClK Falling Edge (Hold Time)

30

-

ns

9

IDl Tx Time to High Impedance

0

30

ns

10

IDl Tx High Impedance to Active State

-

45

ns

11

IDl ClK to IDl Tx Active

-

45

ns

NOTES:
1. IDl SYNC is an 8 kHz signal. The phase relationship between IDl SYNC and IDl ClK is as described earlier.
2. In NT Mode IDl MasterorTE Mode, the IDl ClK is generated Internally in the MC145474f75. When configured for2.04B MHz operation,
IDl ClK is the crystal frequency divded by 7.5 and has a 53.3% duty cycle.

~---------------------------------------~
IDlTx

---I

IDlRx

Figure 2. IDl Timing Characteristics
MOTOROLA COMMUNICATIONS DEVICE DATA

MC145474.MC145475
2-805

SCP TIMING CHARACTERISTICS
Ref #

Characteristics

Min

Max

12

SCPEN Active before Rising Edge of SCPCLK

50

13

SCPCLK Rising Edge before SCPEN Active

50

-

14

$CP Rx Valid before SCPCLK Rising Edge (Setup Time)

35

-

Unit
ns
ns
ns

15

SCP Rx Valid after SCPCLK Rising Edge (Hold Time)

20

16

SCPCLK Period (See Note 1)

244

-

17

SCPCLK Width (Low)

30

-

ns

18

SCPCLK Width (High)

30

-

ns

ns
ns

19

SCP Tx Active Delay

0

50

ns

20

SCPEN Active to SCP Tx Active

0

50

ns

21

SCPCLK Falling Edge to SCP Tx High Impedance

-

30

ns

22

SCPEN Inactive before SCPCLK Rising Edge

50

-

ns

23

SCPCLK Rising Edge before SCPEN Active

50

-

ns

24

SCPCLK Falling Edge to SCP Tx Valid Data

0

50

ns

NOTES:
1. Maximum SCPCLK frequency is 4.096 MHz.

SCPCLK

SCPRx
(Note 1)

SCPTx
(Nole2)

SCPRx
(Note 3)

SCPTx
(Note 3)

NOTES:
1. During a nibble read, four bits are presented on SCP Rx.
2. During a nibble read, SCP Tx will be active for the duration of the 4-bit transmission as shown.
3. A byte transaction consists of two 8-bit exchanges. During the first exchange, whether a read or a write, 8 bits (the byte register address)
are presented on SCP Rx. In the second exchange, 8 bits are presented on SCP Tx during a byte read. During a byte write, the second
exchange consists of 8 bits presented to SCP Rx.

Figure 3. SCP Timing Characteristics

MC145474.MC145475
2-806

MOTOROLA COMMUNICATIONS DEVICE DATA

NT1 STAR MODE TIMING CHARACTERISTICS
Characteristics
Propagation Delay from ANDln to ANDout. while receiving INFO 0

ANDin

ANDout

Figure 4. NT1 Star Mode

D CHANNEL TIMING CHARACTERISTICS (TE Mode)
Ref #

Min

Max

Unit

26
27

DREQ Valid before Falling Edge of IDL SYNC

Characteristics

30

ns

DREQ Valid after Falling Edge of IDL SYNC

30

28

DGRNT Valid before Failing Edge of IDL SYNC

390

-

ns
ns

DREQ

IDLSYNC

Figure 5. D·Channel Timing

IDLSYNC

DGRNT

Figure 6. D·Channel Timing

MOTOROLA COMMUNICATIONS DEVICE DATA

MC145474.MC145475

2·807

PIN DESCRIPTIONS
ISET
Current Set
A current programming resistor is connected between this
pin and ground.
RxP, RxN
Receive Positive, Receive Negative
The SfT interface pseudo-ternary signal is input through
these pins.
TEiNT
Terminal EquipmenVNetwork Termination
This pin is an input and selects the TE or NT mode of
operation.
DGRANT/FSYNC
D Channel GranVFrame Synchronization
This pin is a dual function output and operates as DGRANT
when TE mode is selected, and FSYNC when NT mode is
selected.
DGRANT: The DGRANT output is asserted when the
MC145474/75 has determined that it can access the D channel.
FSYNC: FSYNC is asserted when the MC145474175 has
achieved frame synchronization.
ANDin
NT1 Star Mode D Channel AND Gate Input
This pin is an input to the MC145475 and is used in NT1
star mode.
VSS
Negative Power Supply
This pin is the most negative power supply pin and digital
logic ground. It is normally 0 V.
FSYNC/ANDout
Frame Synchronization!
NT1 Star D Mode Channel AND Gate Output
This pin is a dual function output and operates as FSYNC
when TE mode is selected and ANDout when NT mode is
selected. This pin is available only on the MC145475.
FSYNC: FSYNC is asserted when the MC145475 has achieved
frame synchronization.
ANDout: This pin is an output from the MC145475 and is used in
NT1 star mode.
DREOIFIX
D Channel RequesV
Fixed/Adaptive Timing Select
This pin is a dual function input and operates as DREQwhen
TE mode is selected and FIX when NT mode is selected.
DREQ: The DREQ input should be asserted when access to the
D channel is desired
FIX: This input is used to select fixed or adaptive timing mode in
an NT configured MC145474175.
CLASS/ECHOin
D Channel Class Selectionl
NT1 Star Mode Echo Channel Input
This pin is a dual function input and operates as CLASS
when TE mode is selected and ECHOin when NT mode is
selected. This pin is available only on the MC145475.
CLASS: This pin selects the desired class or priority to be used
when transmitting data on the D channel.
ECHOin: This pin is an input to the MC145475 and is used in NT1
star mode.

MC145474.MC145475
2-808

IDLSYNC
IDL Frame Synchronization Signal
The 8 kHz IDL frame synchronization signal is transmitted
or received through this pin. When the MC145474175 is
operating as an IDL slave, this pin is an input to the device.
Conversely, when the device is operating as an IDL master,
this pin is an output.
IDLCLK
IDL Clock Signal
The IDL clock signal is transmitted through this pin. When
the MC145474175 is operating as an IDL slave, this pin is an
input to the device. Conversely, when the device is operating
as an IDL master, this pin is an output.
IDL Rx
IDL Receive Input
This pin is an input to the MC145474175. 2B+D data is
received through this pin and then modulated onto the SfT
interface.
IDL Tx
IDL Transmit Output
This pin is an outputfrom the MC145474175. Demodulated
2B + D data from the SfT interface is transmitted through this
pin.
SCPRx
SCP Receive Input
The serial control port receive line is used to input control, status, and data information into the MC145474/75 SfT
transceiver.
SCPTx
SCP Transmit Output
The serial control port (SCP) transmit line is used to output
control, status, and data information from the MC145474175
SfT transceiver.
SCPCLK
SCP Clock Signal
The serial control port clock is used to clock control, status,
and data information into and out of the MC145474/75 SfT
transceiver.
SCPEN
SCP Enable Signal
This signal when held low selects the SCP for the transfer
of control, status, and data information into and out of the
MC145474175 SfT transceiver.
LB ACTIVE
Loopback Active
This pin is always an output from the device. If any of the
loopbacks are invoked, or any combination of the loopbacks
are invoked then this pin will be held high.
IRQ
Interrupt Request Line
The interrupt request active low pin is an active low open
drain output used to signal MPU or MCU devices that an
interrupt condition exists in the MC145474175 SfTtransceiver.
AONT
Active Only NT
This pin is always an input to the device. The active only
NT feature is applicable only to the NT mode of operation and
is available as an output pin on the MC145475 and as an SCP
control bit (BR7(6)) in both versions of the device.

MOTOROLA COMMUNICATIONS DEVICE DATA

VDD
Positive Power Supply
This pin is the positive power supply input to the
MC145474175 and is 5.0 V ± 10% with respect to VSS.
XTAU2
7.68 MHz Clock Output
This pin is always an output from the device. The
MC145474175 srr transceiver's 15.36 MHz clock is intemally
divided by two and the output of this divider (7.68 MHz)
presents itself on the XTAU2 pin.
XTAL and EXTAL
Crystal Input and Crystal Output
The MC145474175 srr transceiver requires a 15.36 MHz
clock source for operation. This can be provided by a
15.36 MHz resonant crystal circuit using XTAL and EXTAL
as the terminals of the circuit, or an external 15.36 MHz clock
source can be input to the device via the XTAL pin. An inverter
is internally connected between XTAL and EXTAL with XTAL
as the input to the inverter and EXTAL as the output.
TxP, TxN
Transmit Positive, Transmit Negative
These pins act as differential current limited voltage source
drive pairs for creating the logical line Signals.
RESET
MC145474175 Reset
When low, a hardware reset is applied to the MC145474175.

WIRING CONFIGURATIONS
INTRODUCTION
The MC145474175 ISDN srr transceiver conforms to
CCITT 1.430 and ANSI T1.605 specifications. It is a Layer 1
srr transceiver designed for use at the Sand T reference
points. It is designed for both point-to-point and multipoint
operation. The srr transceiver is designed for use in either
the network terminating (NT) mode or in terminal equipment
(TE) applications. Two 64 kpbs B channels and one 16 kpbs
channel are transmitted in a full duplex fashion across the
interface.
Suggested wiring configurations follow. These configurations are deemed to be the most common but by no means
the only wiring configurations. Note that when operating in the
TE mode, only one TE has the 100 n termination resistors
in the transmit and receive paths. Figures 7 through 10
illustrate where to connect the termination resistors for the
described loop configurations.

o

POINT-TO-POINT OPERATION
In the point-to-point mode of operation one NT communicates with one TE. As such, 100 n termination resistors must

be connected across the transmit and receive paths of both
the NT and TE transceivers. Figure 7 illustrates this wiring
configuration.
When using the MC145474175 in this configuration, the NT
must be in adaptive timing. This is accomplished by holding
the OREQ/FIX pin low (i.e., connecting it to VSS). CCITT 1.430
and ANSI Tl.605 specifythatthe srr transceiver must be able
to operate up to a distance of 1 km in the point-to-point mode.
This is the distance 01, shown in Figure 7.
SHORT PASSIVE BUS OPERATION
The short passive bus is intended for use when up to eight
TEs are required to communicate with one NT. TEs can be
distributed at any point along the passive bus, the only
requirement being that the termination resistors be located
at the end of the passive bus. Figure 8 illustrates this wiring
configuration. CCITT 1.430 and ANSI Tl.605 specify a maximum operational distance from the NT of 200 meters. This
corresponds to the distance 02, as shown in Figure 8.
EXTENDED PASSIVE BUS OPERATION
A wiring configuration whereby the TEs are restricted to a
grouping at the far end of the cable, distant from the NT, is
shown as the "Extended Passive Bus." This configuration is
as illustrated in Figure 9. The termination resistors are to be
positioned as illustrated in the diagram.
.
The essence of this configuration is that a restriction is
placed on the distance between the TEs. The distance 03,
as illustrated in Figure 9, corresponds to the maximum
distance between the grouping olTEs. CCITT 1.430 and ANSI
Tl.605 specify a distance of 25 to 50 meters forthe separation
between the TEs, and a distance of 500 meters for the total
length. These distances correspond to the distances 03 and
04, as shown in Figure 9.
Note that the "NT configured" MC145474175 should be
placed in the adaptive timing mode for this configuration. This
is achieved by holding the OREQUEST/FIX pin low.
BRANCHED PASSIVE BUS OPERATION
A wiring configuration which has somewhat similar
characteristics to those of the "Extended Passive Bus" is
known as the "Branched Passive Bus" and is illustrated in
Figure 10. In this configuration the branching occurs at the
end of the bus. The branching occurs after a distance 01 from
the NT. The distance 05 corresponds to the maximum
separation between the TEs.
NT1 STAR MODE OF OPERATION
A wiring configuration which may be used to support multiple
T interfaces is known as the "NTl Star Mode of Operation."
This mode of operation is supported by the MC145475. This
mode is described later. Note that the NTl Star mode contains
multiple NTs. Each of these NTs can be connected to either
a passive bus (short, extended, or branched) or to a single
TE.

~-----------------Dl----------------~

NT

TE

TxP

RxP

TxN

RxN
MC145474175

MC145474175

RxP
RxN

Figure 7. Point to Point
MOTOROLA COMMUNICATIONS OEVICE OATA

MC145474.MC145475

2-809

02

TR

TR

NT

8
8 ----

I-- TxP
I-- TxN

I
I

t

TxP TxN

t

RxP RxN

TxP TxN

t

RxP RxN

TxP TxN

MC145474175

RxP
RxN

RxP RxN

MC145474175

MC145474175

MC145474175

TE

TE

TE

Figure 8. Short Passive Bus
NT

04

TxP
TxN
MC145474175
RxP
RxN

TxP TxN

RxP RxN

TxP TxN

RxP RxN

MC145474175

MC145474175

TE

TE

1---03--1
Figure 9. Extended Passive Bus
05

TE

01

.r-

RxP

I

RxN

TxP
TxN

88 --

4 - TxP

TR

L-

MC145474175

I

J

TxP TxN

NT

TR

TxN
MC145474175

RxP

'--i> RxN

RxP RxN

MC145474175

TE

Figure 10. Branched Passive Bus

MC145474.MC145475
2-810

MOTOROLA COMMUNICATIONS DEVICE DATA

ACTIVATION/DEACTIVATION OF
SIT TRANSCEIVER
INTRODUCTION
CCITT 1.430 and ANSI T1.605 define five information states
for the SfT transceiver. When the NT is in the fully operational
state illransmits INFO 4. When the TE is in the fully operational
state itlransmits INFO 3. INFO 1 is transmitted by the TEwhen
it wants to wake up the NT. INFO 2 is transmitted by the NT
when it wants to wake up the TE, or in response to the TEs
transmitted INFO 1. These slates cause unique patterns of
symbols to be transmitted over the SfT interface. Only when
the SfT loop is in the fully activated state are the 2B+D
channels of data transmitted over the interface.
TRANSMISSION STATES FOR NT MODE SfT
TRANSCEIVER
When configured as an NT, an SfT transceiver can be in
any of the following transmission states shown in Table 1.
Table 1. NT Mode Transmission States
Information
State

Description

INFOO

The NT transmits 1s in every bit position. This
corresponds to no signal being transmitted.

INFO 2

The NT sets its 91, 92, D, and E channels to O.
The A bit is set to O.

INFO 4

INFO 4 corresponds to frames containing
operational data on the 91, 92, D, and E
channels. The A bit is setto 1.

TRANSMISSION STATES FOR TE MODE SfT
TRANSCEIVER
When configured as a TE, an SfT transceiver can be in any
of the following transmission states shown in Table 2.
ACTIVATION OF SfT LOOP BY NT
The NT activates the loop by transmitting INFO 2 to the TE
or TEs. This is accomplished in the MC145474f75 by setting

NR2(3) to a 1. Note that this bit is internally reset to 0 after
the internal activation state machine has recognized its active
transition.
Table 2. TE Mode Transmission States
Information
State

Description

INFO 0

The TE transmits 1s in every bit position. This
corresponds to no signal being transmitted.

INFO 1

The TE transmits a continuous signal with the
following pattern: positive zero, negative zero,
six ones. This signal is asynchronous to the NT.

INFO 3

INFO 3 corresponds to frames containing
operational data on the 91, 92, and D
channels. If INFO 4 or INFO 2 is being
received, INFO 3 will be synchronized to it.

The TE or TEs on receiving INFO 2 will synchronize to it
and transmit back INFO 3 tothe NT. The NT on receiving INFO
3 from the TE will respond with INFO 4, thus activating the
loop.
ACTIVATION OF SfT LOOP BY TE
The TE can activate an inactive loop by transmitting INFO
1 to the NT. This is accomplished in the MC145474f75 by
setting NR2(3) to a 1. Note that this bit is internally reset to
o after the internal activation state machine has recognized
its active transition.
The NT upon detecting INFO 1 from the TE will respond
with INFO 2. The TE upon receiving a signal from the NT will
cease transmission of INFO 1, reverting to an INFO 0 state.
After synchronizing to the received signal and having fully
verified that it is INFO 2, the TE will respond with INFO 3, thus
activating the loop.
FULL ACTIVATION
When the SfT interface is fully activated, INFO 3 is
transmitted by the TE and INFO 4 by the NT. Figure 11 shows
the binary organization and phase relationship of these signals
from the TE's perspective.

Bl Bl Bl B1Bl Bl Bl Bl E D A FA NB2B2B2B2B2B2B2B2 E D M B1Bl Bl B1Bl B1Bl Bl E D S B2B2B2B2B2B2B2B2 E D L F L

2 BAUD TURNAROUND

10.4 j1S

Figure 11. Two Baud Turnaround in TE

MOTOROLA COMMUNICATIONS DEVICE DATA

MC145474.MC145475
2-811

THE INTERCHIP DIGITAL LINK
The interchip digital link (IDl) is a four-wire interface used
forfull-duplex communication between ICs on the board-level.
The interface consists of a transmit path, a receive path, an
associated clock and a sync signal. These signals are known
as IDl TX,lDl RX,lDl ClK, and IDl SYNC, respectively. The
clock determines the rate of exchange of data in both the
transmit and receive directions, and the sync signal controls
when this exchange is to take place. Five channels of data
are exchanged in a 20-bit package every 8 kHz. These
channels consist of two 64 kbps 8 channels and one 16 kbps
D channel used for full-duplex communication between the
NT and TE. Figure 12 shows phase alignment and order of
transmission.
In addition to these 28 + D channels there are two 8 kbps
channels. These two additional channels, known as the IDl
A and IDl M channels, are for local communication only (i.e.,
they are not transmitted from NT to TE or vice versa). Use
of these channels is optional. The IDl A and IDL M channels
have no effect on the operation of the srr transceiver. There
are two modes of operation for an IDl device: IDL master and
IDl slave. If an IDl device is configured as an IDl master,
then IDL SYNC and IDl ClK are outputs from the device.
Conversely, if an IDl device is configured as an IDL slave,
then IDl SYNC and IDL ClK are inputs to the device.
Ordinarily the MC145474175 is configured as an IDL slave
when acting as an NT, and as an IDl master when acting as
a TE. The exception to this rule is the option to configure the
NT as an IDL master. Note that an NT configured
MC145474175 comes out of reset in the IDL slave mode.

THE SERIAL CONTROL PORT
INTRODUCTION
The MC145474175 is equipped with a serial control port
(SCP). This SCP is used by external devices (such as an
MC145488 DDLC) to communicate with the srr transceiver.
The SCP is an industry standard serial control port and is
compatible with Motorola's SPI used on several single chip
MCUs.
The SCP is a four-wire bus with control and status bits as
well as data being passed to and from the srr transceiver in
a full-duplex fashion. The SCP interface consists of a transmit
path, a receive path, an associated clock, and an enable
signal. These signals are known as SCP Tx, SCP Rx,

SCPClK, and SCPEN. The clock determines the rate of
exchange of data in both the transmit and receive directions,
and the enable signal govems when this exchange is to take
place.
The operation/configuration of the srr transceiver is
programmed by setting the state of the control bits within the
srr transceiver. The control,· status, and data information
reside in eight 4-bit wide nibble registers and sixteen 8-bit wide
byte registers. The nibble registers are accessed via an 8-bit
SCP bus transaction. The 16 byte-wide registers are accessed
by first writing to a pointer register within the eight 4-bit wide
nibble registers. This pOinter register (NR(7)) will then contain
the address of the byte wide register to be read from or written
to, on the following SCP transaction. Thus, an SCP byte
access is in essence a 16-bit operation. Note that this 16-bit
operation can take place by means of two 8-bit accesses or
a single 16-bit access.
SCP TRANSACTIONS
There are four types of SCP transactions. These are:
1. SCP nibble read
2. SCP nibble write
3. SCP byte read
4. SCP byte write
SCP Nibble Read
A nibble read is an 8-bit SCP transaction. Figure 13
illustrates this process. To initiate an SCP nibble read the
SCPEN pin must be brought low. Following this, a Read/Write
(Rm) bit followed by three primary address bits (AO-A3),are
shifted (MS8 first) into an intermediate buffer register on the
first four rising edges of SCPClK, following the high-to-Iow
transition of SCPEN. If a read operation is to be performed
then Rm should be a 1. The three address bits clocked in
after the R!W bit select which nibble register is to be read.
The contents of this nibble register are shifted out on SCP
Tx on the subsequent four falling edges of SCPClK (i.e., the
four falling edges of SCPClK after the rising edge of
SCPClK which clocked in the last address bit, lS8). SCPEN
should be brought back high after the transaction, before
another falling edge of SCPClK is encountered. Note that
SCP Rx is ignored during the time that SCP Tx is being
driven. Also note that SCP Tx comes out of high impedance
only when it is transmitting data.

--'n. _______________________________

IDLSYNC _ _ _

IDLCLK

4

6

7

10 11

12 13 14

15 16 17 18

19

20

IDLRx

IDL Tx

HIGH
M ~IM::;;P-=E:::;;DA,;;,N:.:.C=-E_

-,;;.;;;,=,;;.;.:.::....,
Figure 12. Interchip Digital Link

MC145474.MC145475
2-812

MOTOROLA COMMUNICATIONS DEVICE DATA

W

SCPCLK

-----------------------~---------HIGH IMPEDANCE
~ HIGH IMPEDANCE

SCPTx

NOTES:
1. RJW = 1 for a read operation.
2. Data is shifted out on SCP Tx on the falling edges of SCPCLK, MSB first.
3. Data is shifted into the chip from SCP Rx on the rising edges of SCPCLK, MSB first.

Figure 13. Serial Control Port Nibble Read Operation

SCP Tx

HIGH IMPEDANCE

NOTES:
1. RJW = 0 for a write operation.
2. Data is shifted out on SCP Tx on the falling edges of SCPCLK, MSB first.
3. Data is shifted into the chip from SCP Rx on the rising edges of SCPCLK, MSB first.

Figure 14. Serial Control Port Nibble Write Operation

SCP Nibble Write
A nibble write is an a·bit SCP transaction. Figure 14
illustrates this process. To initiate an SCP nibble write the
SCPEN pin must be brought low. Following this an RIW bit
followed by three primary address bits are shifted (MSB first)
into an intermediate buffer register on the first four rising edges
of SCPCLK following the high to low transition of SCPEN. If
a write operation is to be performed then RIW should be a
O. The three address bits clocked in after the RiW bit select
the nibble register to be written to. The data shifted in on the
next four rising edges of SCPCLK is then written to the
selected register. Throughout this whole operation the SCP
Tx pin remains in high-impedance state. Note that if a selected
register or bit in a selected register is "read only" then a write
operation has no effect.
SCP Byte Read
A byte read is a 16-bit SCP transaction. Figure 15 illustrates
this process. To initiate an SCP byte read the SCPEN must

MOTOROLA COMMUNICATIONS DEVICE DATA

be brought low. Following this an RIW bit is shifted in from
SCP Rx on the next rising edge of SCPCLK. This bit
determines the operationto be performed, read or write. If RiW
is a 1 then a read operation is selected. Conversely, if RiW
is a 0 then a write operation is selected. The next three bits
shifted in from SCP Rx on the three subsequent rising edges
of SCPCLK are primary address bits as mentioned previously.
If all three bits are 1, then nibble register 7 is selected (NR7).
This is a pointer register, selection of which informs the device
that a byte operation is to be performed. When NR7 is
selected, the following four bits shifted in from SCP Rx on the
following four rising edges of SCPCLK, are automatically
written to NR7. These four bits are the address bits for the
byte operation. In a read operation the next eight falling edges
of SCPCLK will shift out the data from the selected byte
register on SCP Tx.
As mentioned previously, an SCP byte access is a 16-bit
transaction. This can take place in one 16-bit exchange

MC145474.MC145475

2-813

(Figure 15) or two 8-bit exchanges (Figure 16). If the
transaction is performed in two 8-bit exchanges the SCPEN
should be returned high after the first eight bits have been
shifted into the part. When SCPEN comes low again the MSB
of the selected byte will present itself on SCP Tx. The following
eight falling edges of SCPCLK will shift out the remaining eight
bits of the byte register. Note that the order in which data is
written into the part and read out of the part is independent
of whether the byte access is done in one 16-bit exchange
or in two 8-bit exchanges.
SCP Byte Write
A byte write is also a 16-bit SCP transaction. Figure 17
illustrates this process. To initiate an SCP byte write the
SCPEN must be brought low. As before, the next bit
determines whether the operation is to be read or write. If the
first bit is a 0 then a write operation is selected. Again the next
three bits read in from SCP Rx on the subsequent three rising
edges of SCPCLK must all be 1 in order to select the painter

nibble register (NR7). The following four bits shifted in are
automatically written into NR7. As in an SCP byte read these
bits are the address bits for the selected byte register
operation. The next eight rising edges of SCPCLK shift in the
data from the SCP Rx. This data is then stored in the selected
byte register. Throughout this operation SCP Tx will be in a
high-impedance state. Note that if the selected byte is read
only, then this operation will have no effect.
As mentioned previously an SCP byte access is a 16-bit
transaction. This can take place in one 16-bit exchange
(Figure 17) or two 8-bit exchanges (Figure 18). If the
transaction is performed in two 8-bit exchanges, then SCPEN
should be returned high after the first eight bits have been
shifted into the part. When SCPEN comes low again, the next
eight rising edges of SCPCLK shift data in from SCP Rx. This
data is then stored in the selected byte. Figure 18 illustrates
this process.

SCPCLK

HIGH IMPEDANCE
SCPTx

HIGH IMPEDANCE

NOTES:

1. ANi = 1 for a read operation.
2. Data is shifted out on SCP Tx on the falling edges of SCPCLK, MSB first.
3. Data is shifted into the chip from SCP Ax on the rising edges of SCPCLK, MSB first.

Figure 15. Serial Control Port Byte Read Operation

L - - -_ _ _

SCPCLK

---Ir~

~1L-____

--l

W
HIGH
IMPEDANCE

HIGH IMPEDANCE
SCPTx

Figure 16. Serial Control Port Byte Read Operation (Double 8-Bit Transaction)

MC145474.MC145475
2-814

MOTOROLA COMMUNICATIONS DEVICE DATA

SCPCLK

SCPRx

HIGH IMPEDANCE

SCPTx

NOTES:

1. RiW = 0 for a write operation.
2. Data is shifted out on SCP Tx on the falling edges of SCPCLK, MSB first.
3. Data is shifted into the chip from SCP Rx on the rising edges of SCPCLK. MSB first.

Figure 17. Serial Control Port Byte Write Operation

'--___-----Ips
SCPCLK

lllr

SCPRx

HIGH IMPEDANCE

SCPTx

Figure 18. Serial Control Port Byte Write Operation (Double 8·Blt Transaction)

MOTOROLA COMMUNICATIONS DEVICE DATA

MC145474.MC145475
2·815

NIBBLE MAP DEFINITION
There are eight nibble registers (NRO through NR7) in the
MC145474175. Control and status information reside in these
nibble registers. These nibble registers are accessed via the
SCP (see Tables 3 and 4 ).

BYTE MAP DESCRIPTION
There are sixteen byte registers (BRO through BR 15) in the
MC145474175. Control, status, and maintenance information
reside in these byte registers. These byte registers are
accessed via the SCP (see Tables 5 and 6).

Table 3. SCP Nibble Map for NT Operation
(3)

(1)

(2)

NRO

Software Reset

Transmit Power Down

Absolute Minimum Power

(0)

Retum to Normal

NR1

Activation Indication (AI)

Error Indication (EI)

NR2

Activation Request (AR)

Deactivate Request (DR)

Activation Timer #1 Expire

NR3

IRQ #3 Change In Rx INFO

IRQ #2 Multiframe Reception

IRQ #6 FECV Detection

NR4

IRQ #3 Enable

IRQ #2 Enable

IRQ #6 Enable

NR5

Idle B1 Channel on SfT Loop

Idle B2 Channel on SfT Loop

Invert B1 Channel

Invert B2 Channel

NR6

2B+D IDL Non-Tranparent Loopback

Activate IDL M FIFO

Activate IDL A FIFO

Exchange B1 & B2 at IDL

Frame Sync (FS)

Table 4. SCP Nibble Map for TE Operation
(3)

(2)

NRO

Software Reset

Transmit Power Down
Error Indication (EI)

(1)
Absolute Minimum Power

(0)

Retum to Normal

NR1

Activation Indication (AI)

NR2

Activation Request (AR)

NR3

IRQ #3 Change in Rx INFO

IRQ #2 Multiframe Reception

NR4

IRQ #3 Enable

IRQ #2 Enable

IRQ #1 Enable

NR5

Enable B1 Channel on SfT Loop

Enable B2 Channel on 8fT Loop

Invert B1 Channel

Invert B2 Channel

NR6

2B+ 0 IDL Non-Tranparent Loopback

Activate IDL M FIFO

Activate IDL A FIFO

Exchange B1 & B2 at IDL

MC145474.MC145475

2-816

Multiframlng Detect

Frame Sync (FS)

Activation Timer #3 Expire

Class

IRQ #1 0 Channel
Collision

MOTOROLA COMMUNICATIONS DEVICE DATA

Table 5. SCP Byte Map for NT Operation
(7)

(5)

(6)

BRO

M7

M6

(4)

(3)

(2)

(0)

(1)

MS

M4

M3

M2

Ml

MO

A3

A2

Al

AO

o BitOuality
Indicate

INT Every M.
Frame

BRl

A7

A6

AS

A4

BR2

SC1.lto
Loop

SC1.2to
Loop

SC1.3to
Loop

SC1.4to
Loop

BR3

01 from Loop

02 from Loop

03 from Loop

04 from Loop

BR4

Fr. Viol.
CountB7

Fr. Viol.
Count B6

Fr. Viol.
CountBS

Fr. Viol.
CountB4

Fr. Viol.
Count B3

Fr. Viol.
CountB2

Fr. Viol.
Count Bl

Fr. Viol.
Count BO

BRS

BPVCount
B7

BPVCount
B6

BPV Count
BS

BPVCount
B4

BPVCount
B3

BPVCount
B2

BPV Count
Bl

BPVCount
BO

BR6

Bl srr LB
Transparent

Bl srr LB
Non-Trans.

B2 srr LB
Transparent

B2 srr LB
Non-Trans.

IDL Bl LB
Transparent

IDL Bl LB
Non-Trans.

IDL B2 LB
Transparent

IDL B2 LB
Non-Trans.

BR7

Act. Proc.
Disabled

Reserved

Enable
Multiframing

InvertE
Channel

IDL Master
Mode

IDLCLK
Speed LSB

Act. Timer
#2

IDLM FIFO

IDLAFIFO

,,1/2 Full

,,1/2 Full

Act.IDLM
FIFO HOZ

Act.IDLA
FIFOHOZ

Enable IRO
#4

Enable IRO
#5

IRO #4,IDL
A FIFO

IRO#SIDL
M FIFO

BR9

SC2.1to
Loop

SC2.2to
Loop

SC2.3to
Loop

SC2.4to
Loop

SC3.1to
Loop

SC3.2to
Loop

SC3.3to
Loop

SC3.4to
Loop

BR10

SC4.1to
Loop

SC4.2to
Loop

SC4.3to
Loop

SC4.4to
Loop

SCS.lto
Loop

SCS.2to
Loop

SCS.3to
Loop

SC5.4to
Loop

BR11

Do Not
React to
INFO 1

Do Not
React to
INF03

RxlNFO
State Bl

RxlNFO
State BO

TxlNFO
State Bl

Tx INFO
State BO

EXT srr
Loopback

Tx 96 kHz
Test Signal

Reserved

Reserved

BRS

BR12

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

BR13

NTl Star
Mode

TTL Input
Levels

IDL CLK
Speed MSB

Mute B20n
IDL

Mute Bl on
IDL

Force E to
Zero

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

BR14
BR1S

MOTOROLA COMMUNICATIONS DEVICE DATA

MC145474.MC145475
2-817

Table 6. SCP Byte Map for TE Operation
(6)

(7)

(5)

(4)

(2)

(3)

(I)

(0)

M4

M3

M2

MI

MO

AS

A4

A3

A2

AI

AD

Q3to Loop

Q4toLoop

SCI.2Irom
Loop

SCI.3Irom
Loop

SCI.4lrom
Loop

Fr. Viol.
CountB7

Fr. Viol.
CountB6

Fr. Viol.
CountB5

Fr. Viol.
CountB4

Fr. Viol.
CountB3

Fr. Viol.
CountB2

Fr. Viol.
CountBI

Fr. Viol.
CountBO

BRS

BPVCount
B7

BPVCount
B6

BPVCount
BS

BPVCount
B4

BPVCount
B3

BPVCounl
B2

BPVCount
BI

BPV Count
BO

BR6

BI SrrLB
Transparent

BI SrrLB
Non-Trans.

B2SrrLB
Transparent

B2 srr LB
Non-Trans.

IDL Bl LB
Transparent

IDL Bl LB
Non-Trans.

IDLB2 LB
Transparent

IDL B2 LB
Non-Trans.

BR7

Act. Proc.
Ignored

DChannel
Proc.
Ignored

MapEto
IDLon D
Channel

IDL Free
Run

IDLCLK
Speed LSB

LAPDPol.
ConI.

BRB

IDLM FIFO
s 112 Full

IDLAFIFO
S 1/2 Full

Acl.lDLM
FIFOHOZ

Acl.lDLA
FIFO HOZ

Enable IRQ
#4

Enable IRQ
#5

IRQ#4IDL
A FIFO

IRQ#5IDL
MFIFO

BR9

SC2.1lrom
Loop

SC2.21rom
Loop

SC2.31rom
Loop

SC2.4lrom
Loop

S03.1lrom
Loop

SC3.2lrom
Loop

SC3.3lrom
Loop

SC3.4lrom
Loop

BRIO

SC4.llrom
Loop

SC4.21rom
Loop

SC4.31rom
Loop

SC4.4lrom
Loop

SC5.1lrom
Loop

SCS.21rom
Loop

SCS.31rom
Loop

SCS.41rom
Loop

RxlNFO
StateBI

RxlNFO
State BO

TxlNFO
StateBI

TxlNFO
State BO

EXTSrr
Loopback

Tx 96 kHz
Test Signal

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

TTL Input
Levels

IDLCLK
SpeedMSB

Mute B20n
IDL

MuteBlon
IDL

Reserved

Reserved

Reserved

BRO

M7

M6

M5

BRI

A7

A6

BR2

QI to Loop

Q2toLoop

BR3

SC1.1 Irom
Loop

BR4

BRll
BRI2

Reserved

BRI3
BR14
BRIS

Reserved

D CHANNEL OPERATION
INTRODUCTION
The SIT interface is designed for full duplex transmission
of two 64 kbps B channels and one 16 kbps D channel,
between one NT device and one or more TEs. The TEs gain
access to the B channels by sending Layer 2 frames to the
network over the D channel. CCITT 1.430 and ANSI Tl.605
specify a D channel access algorithm for TEs to gain access
to the D channel. The MCI45474175 SIT transceiver is fully
compliant with the D channel access algorithm as defined
in CCITT 1.430 and ANSI Tl.605. The SCP bits and pins
directly pertaining to D channel operation are shown in Tables
7 and 8.
D channel data is clocked into the MC145474175 via IDl
Rx on the falling edges of IDl ClK. Data is clocked out onto
IDl Tx on the rising edges of IDl CLK. This is in accordance
with the IDl specification as outlined earlier.
GAINING ACCESS TO THE D CHANNEL IN TE MODE
The pins DREQ and DGRANT are used in the TE mode
of operation to request and grant access to the D channel.
An external device wishing to send a layer 2 frame should
bring DREQ high, and maintain it high for the duration of the
layer 2 frame. DGRANT is an output signal used to indicate
to an external device that the D channel is clear. Note that

MC145474.MC145475

2-818

INT Every
M Frame

Force IDL
Transmit

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

the DGRANT signal actually goes high on~ received E echo
bit prior to the programmed priority class selection. DGRANT
goes high at a count of (n - 1) to accommodate the delay
between the input of D channel data via the IDl interface and
the line transmission of those bits towards the NT. If at the
time of the IDl SYNC pulse falling edge, the DGRANT and
the DREQ signals are both detected high, the TE mode
Table 7. D Channel SCP Bit Description
MC145474ns
NT Mode

MC145474n5
TEMode

SCP Bit

Description

SCP Bit

BR7(4)

Invert the Echo
Channel

NR2(O)

Class

Description

BR13(2)

Force the Echo
Channel to '0'

NR3(1)

Interrupt on D Channel
Collision

BR13(7)

NTI Star Mode

NR4(1)

Interrupt Enable for
NR3(1)

BR7(1)

LAPD Polarity Control

BR7(4)

Map Echo Bits to D
TImeslots on IDL Tx

BR7(6)

D Channel Procedures
Ignored

MOTOROLA COMMUNICATIONS DEVICE DATA

transceiver will begin FIFO buffering of the input D channel
bits from the IDL interface. This FIFO is four bits deep. Note
that DGRANT goes high on the' boundaries of the demodulated E bits. In order for the contention algorithm to work on
the D channel, HDLC data must be used. The MC145474175
modulates the D channel data onto the srr bus in the form
that it is received from the IDL bus. Thus, the data must be
presented to it in HDLC format. Note that one of the
applications of the MC145488 DDLC is for use with the
MC145474175 in the terminal mode. The MC145488 will
perform the HDLC conversion and perform the necessary D
channel handshaking.
Table 8. D Channel Operation Pin Description
Pin #

MC145474

MC145475

5

DGRANT

DGRANT

7

DREO

ANDin

B

ANDout

9

DREO

10

CLASS/ECHOin

Note that the active polarity of the DREQ and DGRANT
signals may be reversed by setting the LAPD polarity control
bit (BR7(1)) in the SCPo When BR7(1) is a 0 the active polarity
is as described above. Conversely, when BR7(1) is a 1 the
MC145474175 will drive DGRANTto a logic 0 when DGRANT
is active and to a logic 1 when DGRANT is inactive. Also, when
BR7(1) is 1, DREQ will be considered to be active low.
GAINING ACCESS TO THE D CHANNEL IN NT MODE
When configured as an NTthe MC145474175 has automatic
access to the D channel. This is because the srr interface
is designed for communication between a single NT and one
or more TEs. As such, the NT does not have to compete for
access to the D channel. Thus, there are no DREQ or
DGRANT functions associated with the NT mode of operation.
Data present in the D bit positions of the IDL frame on IDL
Rx are modulated onto the D bit timeslots on the srr loop.
Demodulated D channel data from the TErrEs is transmitted
onto IDL Tx in accordance with the IDL specification. The
ECHO function of an NT configured srr transceiver is
performed internally in the MC145474175. To assist in testing
an srr loop the MC145474175 features the SCP test bits
BR7(4) and BR13(2). Setting BR7(4) in the NT mode will invert
the E echo channel (i.e., the logical inverse of the demodulated
D channel data from the TErrEs is transmitted in the E
channel). Setting BR13(2) to a 1 will force the E channel to
all Os. Refer to Section 8 for a more detailed description of
these test bits. Setting BR13(7) to a 1 puts the "NT configured"
MC145474175 srr transceiver into the NTl Star mode of
operation. In this mode, the bits to be ECHOed back to the
TErrEs are obtained from the ECHOin pin.

MULTIFRAMING
A Layer 1 signalling channel between the NT and TE is
provided in the MC145474175 in accordance with CCITT 1.430
and ANSI Tl.605. In the NT to TE direction, this Layer 1
channel is the S channel. In the TE to NT direction it is the

MOTOROLA COMMUNICATIONS DEVICE DATA

Q channel. The S channel is subdivided into five subchannels:
SC1, SC2, SC3, SC4, and SC5. The MC145474175 is capable
of transmitting and receiving data In all S subchannels as well
as the Q channel by simply reading orwriting to the appropriate
SCP registers. Interrupts are also available to indicate the
reception of multiframe information. See the MC145474175
Data Book for a complete description.

NT1 STAR MODE OPERATION
Appendix B of ANSI Tl.605 describes an example of an
NT that will support multiple T interfaces. This is to
accommodate multipoint operation with more than eight TEs.
The MC145475 can be configured for NTl Star mode of
operation. This mode is for use in wire ORing multiple NT
configured srr chips on the IDL side. Each NT has a common
IDL SYNC, IDL CLK, IDL Tx, and IDL Rx, as shown in Figure
19. Each NT is then connected to its own individual srr loop
containing either a single TE or a group of TEs. As such, the
contention for either of the B channels or for the D channel
is now extended from a Single passive bus to a grouping of
passive busses.
ISDN employs the use of HDLC data on the D channel.
Access to either of the B channels is requested and either
granted or denied by the user sending Layer 2 frames on the
D channel. In normal operation where there is only one NT,
the TEs are granted access to the D channel in accordance
with their priority and class. By counting the required number
of E channel echo bits being 1, the TEs know when the
D channel is clear. Thus in the NT1 Star mode of operation,
where there are multiple passive busses competing for the
same Bl, B2, and D channels, the same E echo channel must
be transmitted from each NT to its passive bus. This is
accomplished in the MC145475 by means of the ANDin,
ANDout, and ECHOin pins.
Figure 13 shows how to connect the multiple number of NTs
in the NTl Star mode. Successive connection of the ANDout
(this is the output of an intemal AND gate whose inputs are
the demodulated D bits and the data on the ANDin pin) and
ANDin pins, and the common connections of the ECHOin
pins, succeeds in senc;ling the same E echo channel to each
group of TErrEs. To configure a series of NTs for NTl Star
mode, BR13(7) must be set to 1 in each NT. Data transmitted
on IDL Tx in NTl Star mode, will have the following format:
a logic 0 is VSS, a logic 1 causes IDL Tx to go to a
high-impedance state. This then permits the series wire ORing
of the IDL bus. Note that one of the NTs must have its ANDin
pin pulled high.

TRANSMISSION LINE INTERFACE CIRCUITRY
The MC145474175 is an ISDN srr transceiver fully
compliant with CCITT 1.430 and ANSI Tl.605. As such it is
designed to interface with a four wire transmission medium,
one pair being the transmit path, the other pair the receive
path. TxP and TxN, a fully differential output transmit pairfrom
the MC145474175, are designed to interface to the transmit
pair of the transmission medium via auxiliary discrete
components and a 1:1 turns ratio transformer. RxP and RxN
are a high-impedance differential input pair used for coupling
the receive line signal through a 1:1 turns ratio transformer
(see Figures 20 and 21).

MC145474.MC145475

2-819

IC#1

1

MCl45475
BR13(7) 1

=

ANCjn
-

DEMODULATED
D CHANNEL DATA

-

DATA TO BE TRANSMITIED TO TEs
AS E CHANNEL DATA

~~

ANDout
ECHOin
IDLSYNC
IDLCLK
IDLRx
IDL Tx

IDLSYNC
IDLCLK
IDLRx
IDL Tx

IC#2
MCl45475
BR13(7) 1

=

ANDin
-

DEMODULATED
DCHANNEL DATA

-

DATA TO BETRANSMITIED TO TEs
AS E CHANNEL DATA

AN~ut

ECHOin
IDLSYNC
IDLCLK
IDLRx I
IDL Tx

IC#N
MC145475
BR13(7) 1

=

ANCjn
-

DEMODULATED
D CHANNEL DATA

-

DATA TO BE TRANSMITIED TO TEs
AS E CHANNEL DATA

ANDJ)ut

T

ECHOin
IDLSYNC
IDLCLK
IDLRx
IDL Tx

Figure19. NT1 Star Mode of Operation

MC145474.MC145475
2-820

MOTOROLA COMMUNICATIONS DEVICE DATA

+5V

R

R

TxP
+5V

-

100 n TERMINATION

R

R
TxN

SIT LOOP

MC145474 OR MCl45475

~

-

NOTE: 4R + winding resistance = 26.4 n

Figure 20. Transmit Line Interface Circuit

+5V

1.0mH
500n
500n
RxP 1--ii_~--""--Bi__............-rvYY"'l
+5V

4.3kQ

100 n TERMINATION

soon

500n

RxN

47pF

r--!!!...-t-----!!..----.....".A.IVU
1.0mH

S/TLOOP---'il~~

~

MC145474 OR MCl45475

•

PROTECTION

Figure 21. Receive Line Interface Circuit

MOTOROLA COMMUNICATIONS DEVICE DATA

MC145474.MC145475
2-821

MOTOROLA

-

SEMICONDUCTOR
TECHNICAL DATA

MC145480
Advance Information
5 V PCM Codec-Filter
The MC1454BO is a general purpose per channel PCM Codec-Filter with pin
selectable Mu-Law or A-Law companding, and is offered in 20-pin DIP and SOG
packages. This device performs the voice digitization and reconstruction as well
as the band limiting and smoothing required for PCM systems. This device is
designed to operate in both synchronous and asynchronous applications and
contains an on-chip precision reference voltage.
This device has an input operational amplifier whose output Is the input to the
encoder section. The encoder section immediately low-pass filters the analog
signal with an active R-C filter to eliminate very high frequency noise from being
modulated down to the passband by the switched capacitor filter. From the active
R-C filter, the analog signal is converted to a differential signal. From this point,
all analog signal processing Is done differentially. This allows processing of an
analog signal that is twice the amplitude allowed by a single-ended design, which
reduces the significance of noise to both the inverted and non-Inverted signal
paths. Another advantage of this differential design is that noise injected via the
power supplies Is a common-mode Signal that Is cancelled when the Inverted and
non- inverted signals are recombined. This dramatically Improves the power
supply rejection ratio.
After the differential converter, a differential switched capacitor filter bandpasses the analog signal from 200 Hz to 3400 Hz before the signal is digitized
by the differential compressing AID converter.
The decoder accepts PCM data and expands it using a differential D/Aconverter.
The output of the D/A is low-pass filtered at 3400 Hz and slnXlX compensated
by a differential switched capacitor filter. The signal Is then filtered by an active
R-C filter to eliminate the out of band energy of the switched capacitor filter.
The MC1454BO PCM codec-filter accepts a variety of clock formats, including
Short Frame Sync, Long Frame Sync, IDL, and GCI timing environments. This
device also maintains compatibility with Motorola's family of Telecommunication
products, including the MC14LC5472 U-Interface Transceiver, MC145474175 SIT
Interface Transceiver, MC145532 ADPCM Transcoder, MC145422126 UDLT-1,
MC145421/25 UDLT-2, and MC3419/MC33120 SLiC.
The MC145480 PCM codec-filter utilizes CMOS due to its reliable low-power
performance and proven capability for complex analog/digital VLSI functions.
•
•
•
•
•
•
•
•
•

PSUFFIX
PLASTIC DIP
CASE73B

OW SUFFIX

SOG
CASE 7510

PIN ASSIGNMENT
RO+
RO-

VAG
TI+

PI

TITG

POPO+

MulA

VOD
FSR

Vss
FST

DR

DT

BeLKR
POI

BCLKT
MCLK

Single 5 V Power Supply
Typical Power Dissipation of 23 mW, Power Down of 0.01 mW
Fully Differential Analog Circuit Design for Lowest Noise
Transmit Band-Pass and Receive Low-Pass Filters on Chip
Active R-C Pre-Filtering and Post-Filtering
Mu-Law and A-Law Companding by Pin Selection
On-Chip Precision Reference Voltage (1.575 V)
Push-Pull 300 n Power Drivers with External Gain Adjust
MC145536EVK is the evaluation kit that also includes the MC145532 ADPCM
Transcoder

This document contains Infonnation on a new product. Specifications and Information herein are subject to chango wHhout notice.

MC145480
2-822

MOTOROLA COMMUNICATIONS DEVICE DATA

~

RO+
RO-

DR
DAC

FREQ

PI
FSR
PO-

BCLKR

SHARED
DAC
PO+

-+----<

-

I I

VDD VSS

VAG II

MulA
SEQUENCE
AND
CONTROL

1.575 V
REF

~

MCLK
BCLKT
FST

TG
TITI+

>-6----~ ~

ADC

FREQ
DT

Figure 1. MC14548D PCM Codec-Filter Block Diagram

DEVICE DESCRIPTION
A PCM codec-filter is used for digitizing and reconstructing
the human voice. These devices are used primarily for the
telephone network to facilitate voice switching and transmission. Once the voice is digitized, it may be switched by digital
switching methods or transmitted long distance (T1, microwave, satellites, etc.) without degradation. The name codec
is an acronym from "COder" forthe analog-to-digital converter
(ADC) used to digitize voice, and "DECoder" for the
digital-to-analog converter (DAC) used for reconstructing
voice. A codec is a single device that does both the ADC and
DAC conversions.
To digitize intelligible voice requires a signal-to-distortion
ratio of about 30 dB over a dynamic range of about 4D dB.
This may be accomplished with a linear 13-bit ADC and DAC,
but will far exceed the required signal-to-distortion ratio at
larger amplitudes than 40 dB below the peak amplitude. This
excess performance is at the expense of data per sample.
Two methods of data reduction are implemented by
compressing the 13-bit linear scheme to companded pseudologarithmic a-bit schemes. The two companding schemes are:
Mu-255 Law, primarily in North America and Japan, and
A-Law, primarily used in Europe. These companding schemes
are accepted worldwide. These companding schemes foll~w
a segmented or "piecewise-linear" curve formatted as sign
bit, three chord bits, and four step bits. For a given chord, all
sixteen of the steps have the same voltage weighting. As the
voltage of the analog input increases, the four step bits
increment and carry to the three chord bits which increment.

MOTOROLA COMMUNICATIONS DEVICE DATA

When the chord bits increment, the step bits double their
voltage weighting. This results in an effective resolution of s!x
bits (sign + chord + four step bits) across a 42 dB dynamiC
range (seven chords above 0, by 6 dB per chord).
In a sampling environment, Nyquist theory says that to
properly sample a continuous signal, it must be sampled at
a frequency higher than twice the signal's highest frequency
component. Voice contains spectral energy above 3 kHz, but
its absence is not detrimental to intelligibility. To reduce the
digital data rate, which is proportional to the sampling rate,
a sample rate of a kHz was adopted, consistent with a
bandwidth of 3 kHz. This sampling requires a low-pass filter
to limit the high frequency energy above 3 kHz from distorting
the in band signal. The telephone line is also subject to 50/60
Hz power line coupling, which must be attenuated fro~ ~he
signal by a highpass filter before the analog-to-dlgltal
converter.
The digital-to-analog conversion process recons~ructs a
staircase version of the desired inband signal, which has
spectral images of the inband si.gnal modulated ab~ut the
sample frequency and its harmOniCs. These spectral Images
are called aliasing components, which need to be attenuated
to obtain the desired signal. The low-pass filter used to
attenuate these aliasing components is typically called a
reconstruction or smoothing filter.
The MC1454aO PCM codec-fiIter has the codec, both
presampling and reconstruction filters, a precision voltage
refer- ence on chip, and requires no external components.

MC145480

2-823

PIN DESCRIPTION
POWER SUPPLY
VOO
Positive Power Supply (Pin 6)
This Is the most positive power supply and is typically
connected to +5 V. This pin should be decoupledto VSS with
a 0.1 !!F ceramic capacitor.
VSS
Negative Power Supply (Pin 15)
This is the most negative power supply and is typically
connected to 0 V.
VAG
Analog Ground Output (Pin 20)
This output pin provides a mid-supply analog ground
regulated to 2.4 V. This pin should be decoupled to VSS with
a 0.01 !!F to 0.1 !!F ceramic capacitor. All analog signal
processing within this device is referenced to this pin. If the
audio signals to be processed are referenced to VSS, then
special precautions must be utilized to avoid noise between
VSS and the VAG pin. Refer to the applications information in
this document for more information. The VAG pin becomes
high impedance when this device is in the powered down
mode.
CONTROL
MulA
MulA Law Select (Pin 16)
This pin controls the compression for the encoder and the
expansion for the decoder. Mu-Law companding is selected
when this pin is connected to VDD and A-Law companding
is selected when this pin is connected to VSS.
PDI
Power Down Input (Pin 10)
This pin puts the device into a low power dissipation mode
when a logic 0 is applied. When this device is powered down,
all of the clocks are gated off and all bias currents are turned
off, which causes RO+, RO-, PO-, PO+, TG, VAG, and DT
to become high impedance. The device will operate normally
when a logic 1 is applied to this pin. The device goes through
a power-up sequence when this pin is taken to a logic 1 state,
which prevents the DT PCM output from going low
impedance for at least two FST cycles. The filters must settle
out before the DT PCM output or the RO+ or RO- receive
analog outputs will represent a valid analog signal.

input to the transmit filter.
TITransmit Analog Input (Inverting) (Pin 18)
This is the inverting input of the transmit gain setting
operational amplifier. Gain setting resistors are usually
connected from this pin to TG and from this pin to the analog
signal source. The common mode range of the TI+ and TIpins is from 1.2 V to VDD -2 V. This is an FET gate input.
Connecting both TI+ and TI- pins to VDD will place this
amplifier's output (TG) into a high-impedance state, thus
allowing the TG pin to serve as a high-impedance input to the
transmit filter.
TG
Transmit Gain (Pin 17)
This is the output of the transmit gain setting operational
amplifier and the input to the transmit band-pass filter. This
op amp is capable of driving a 2 kn load. Connecting both
TI+ and TI- pins to VDD will place this amplifier's output (TG)
into a high-impedance state, thus allowing the TG pin to serve
as a high-impedance input to the transmit filter. All signals at
this pin are referenced to the VAG pin. This pin is high impedance when the device is in the powered down mode.
RO+
Receive Analog Output (Non-Inverting) (Pin 1)
This is the non-inverting output of the receive smoothing
filter from the digital-to-analog converter. This output is
capable of driving a 2 kn load to 1.575 V peak referenced
to the VAG pin. This pin is high impedance when the device
is in the powered down mode.
ROReceive Analog Output (Inverting) (Pin 2)
This is the inverting output of the receive smoothing filter
from the digital-to-analog converter. This output is capable of
driving a 2 kn load to 1.575 V peak referenced to the VAG
pin. This pin is high impedance when the device is in the
powered down mode.
PI
Power Amplifier Input (Pin 3)
This is the inverting input to the PO- amplifier. The
non-inverting input to the PO- amplifier is internally tied to
the VAG pin. The PI and PO- pins are used with external
resistors in an inverting op amp gain circuit to set the gain
of the PO+ and PO- push-pull power amplifier outputs.
Connecting PI to VDD will power down the power driver
amplifiers and the PO+ and PO- outputs will be high
impedance.

ANALOGIN.TERFACE
TI+
Transmit Analog Input (Non-Inverting) (Pin 19)
This is the non-inverting input of the transmit input gain
setting operational amplifier. This pin accommodates a
differential to single ended circuit for the input gain setting
op amp. This allows input signals that are referenced to the
VSS pin to be level shifted to the VAG pin with minimum noise.
This pin may be connected to the VAG pin for an inverting
amplifier configuration if the input signal is already
referenced to the VAG pin. The common mode range of the
TI+ and TI- pins is from 1.2 V, to VDD minus 2 V. This is
an FET gate input. Connecting both TI+ and TI- pins to VDD
will place this amplifier's output (TG) into a high-impedance
state, thus allowing the TG pin to serve as a high-impedance

MC145480
2-824

POPower Amplifier Output (Inverting) (Pin 4)
This is the inverting power amplifier output, which is used
to provide a feedback signal to the PI pin to set ·the gain of
the push-pull power amplifier outputs. This pin is capable of
driving a 300 n load to PO+. The PO+ and PO- outputs are
differential (push-pull) and capable of driving a 300 n load to
3.15 V peak, which is 6.3 V peak-to-peak. The bias voltage
and signal reference of this output is the VAG pin. The VAG
pin cannot source or sink as much current as this pin, and
therefore low impedance loads must be between PO+ and
PO-. Connecting PI to VDD will power down the power driver
amplifiers and the PO+ and PO- outputs will be high
impedance. This pin is also high impedance when the device
is powered down by the PDI pin.

MOTOROLA COMMUNICATIONS DEVICE DATA

PO+
Power Amplifier Output (Non-Inverting) (Pin 5)
This is the non-inverting power amplifier output, which is
an inverted version of the signal at PO-. This pin is capable
of driving a 300 n load to PO-. Connecting PI to VDD will
power down the power driver amplifiers and the PO+ and
PO- outputs will be high impedance. This pin is also high
impedance when the device is powered down by the PDI
pin. See PI and PO- for more information.
DIGITAL INTERFACE
MClK
Master Clock (Pin 11)
This is the master clock input pin. The clock signal applied
to this pin is used to generate the internal 256 kHz clock and
sequencing signals for the switched-capacitor filters, ADC,
and DAC. The internal prescaler logic compares the clock on
this pin to the clock at FST (8 kHz) and will automatically accept
256, 512, 1536, 1544, 2048, 2560, or 4096 kHz. For MClK
frequencies of 256 and 512 kHz, MClK must be synchronous
and approximately rising edge aligned to FST. For optimum
performance at frequencies of 1.536 MHz and higher, MClK
should be synchronous and approximately rising edge aligned
to the rising edge of FST. In many applications, MClK may
be tied to the BClKT pin.
FST
Frame Sync, Transmit (Pin 14)
This pin accepts an 8 kHz clock that synchronizes the output
of the serial PCM data at the DT pin. This input is compatible
with various standards including IDl, long Frame Sync, Short
Frame Sync, and GCI formats. If both FST and FSR are held
low for several 8 kHz frames, the device will power down.
BClKT
Bit Clock, Transmit (Pin 12)
This pin controls the transfer rate of transmit PCM data.
In thelDl and GCI modes it also controls the transfer rate
of the receive PCM data. This pin can accept any bit clock
frequency from 64 to 4096 kHz for long Frame Sync and
Short Frame Sync timing. This pin can accept clock
frequencies from 256 kHz to 4.096 MHz in IDl mode, and
from 512 kHz to 6.176 MHz for GCI timing mode.
DT
Data, Transmit (Pin 13)
This pin is controlled by FST and BClKT and is high
impedance except when outputting PCM data. When
operating in the IDl or GCI mode, data is output in either the
B1 or B2 channel as selected by FSA. This pin is high
impedance when the device is in the powered down mode.
FSR
Frame Sync, Receive (Pin 7)
When used in the long Frame Sync or Short Frame Sync
mode, this pin accepts an 8 kHz clock, which synchronizes
the input of the serial PCM data at the DR pin. FSR can be
asynchronous to FST in the long Frame Sync or Short Frame
Sync modes. When an ISDN mode (IDl or GCI) has been
selected with BClKR, this pin selects either B1 (logic 0) or
B2 (logic 1) as the active data channel.
BClKR
Bit Clock, Receive (Pin 9)
When used in the long Frame Sync or Short Frame Sync
mode, this pin accepts any bit clock frequency from 64 to 4096
kHz. When this pin is held at a logic 1, FST, BClKT, DT, and

MOTOROLA COMMUNICATIONS DEVICE DATA

DR become IDl Interface compatible. When this pin is held
at a logic 0, FST, BClKT, DT, and DR become GCI Interface
compatible.
DR
Data, Receive (Pin 8)
This pin is the PCM data input, and when in a long Frame
Sync or Short Frame Sync mode is controlled by FSR and
BClKA. When in the IDl or GCI mode, this data transfer is
controlled by FST and BClKT. FSR and BClKR select the
B channel and ISDN mode, respectively.

FUNCTIONAL DESCRIPTION
ANALOG INTERFACE AND SIGNAL PATH
The transmit portion of this device includes a low-noise,
three-terminal op amp capable of driving a 2 kg load. This
op amp has inputs of TI+ (Pin 19) and TI- (Pin 18) and its
output is TG (Pin 17). This op amp is intended to be configured
in an inverting gain circuit. The analog signal may be applied
directly to the TG pin if this transmit op amp is independently
powered down by connecting the TI+ and TI- inputs to the
VDD power supply. The TG pin becomes high impedance
when the transmit op amp is powered down. The TG pin is
internally connected to a 3-pole anti-aliasing pre-filter. This
pre-filter incorporates a 2-pole Butterworth active low-pass
filter, followed by a single passive pole. This pre-filter is
followed by a single-ended to differential converter that is
clocked at 512 kHz. All subsequent analog processing utilizes
fully differential circuitry. The next section is a fully-differential,
5-pole switched-capacitor low-pass filter with a 3.4 kHz
frequency cutoff. After this filter is a 3-pole switched-capacitor
high-pass filter having a cutoff frequency of about 200 Hz. This
highpass stage has a transmission zero at dc that eliminates
any dc coming from the analog input or from accumulated op
amp offsets in the preceding filter stages. The last stage of
the highpass filter is an autozeroed sample and hold amplifier.
One bandgap voltage reference generator and digital-toanalog converter (DAC) are shared by the transmit and
receive sections. The autozeroed, switched-capacitor bandgap reference generates precise positive and negative
reference voltages that are virtually independent of temperature and power supply voltage. A binary-weighted capacitor
array (CDAC) forms the chords of the companding structure,
while a resistor string (RDAC) implements the linear steps
within each chord. The encode process uses the DAC, the
voltage reference, and a frame-by-frame autozeroed
comparator to implement a successive-approximation conversion algorithm. All of the analog circuitry involved in the
data conversion (the voltage reference, RDAC, CDAC, and
comparator) are implemented with a differential architecture.
The receive section includes the DAC described above, a
sample and hold amplifier, a 5-pole, 3400 Hz switched
capacitor low-pass filter with sinXlX correction, and a 2-pole
active smoothing filter to reduce the spectral components of
the switched capacitor filter. The output of the smoothing filter
is buffered by an amplifier, which is output at the RO+ and
RO- pins. These outputs are capable of driving a 4 kn load
differentially or a 2 kg load to the VAG pin. The MC145480
also has a pair of power amplifiers that are connected in a
push-pull configuration. The PI pin is the inverting input to the
PO- power amplifier. The non-inverting input is internally tied
to the VAG pin. This allows this amplifier to be used in an
inverting gain circuit with two extemal resistors. The PO+
amplifier has a gain of minus one, and is internally connected

MC145480
2-825

to the PO- output. This complete power amplifier circuit is
a differential (push-pull) amplifier with adjustable gain that is
capable of driving a 300 n load to +12 dBm. The power
amplifier may be powered down independently of the rest of
the chip by connecting the PI pin to VDD.

3.14 dB below the maximum level for an unclipped tone signal.
The timing for the PCM data transfer is independent of the
companding scheme selected. Refer to Figure 2 for a
summary and comparison of the four PCM data interface
modes of this device.

POWER DOWN
There are two methods of putting this device into a low
power consumption mode, which makes the device
nonfunctional and consumes virtually no power. PDI is the
power down input pin which, when taken low, powers down
the device. Another way to power the device down is to hold
both the FST and FSR pins low. When the chip is powered
down, the VAG, TG, RO+, RO-, PO+, PO-, and DT outputs
are high impedance. To return the chip to the power up state,
PDI must be high and either the FST or the FSR frame sync
pulse must be present. The DT output will remain in a
high-impedance state for at least two FST pulses after power
up.
MASTER CLOCK
Since this codec-filter design has a single DAC architecture,
the MCLK pin is used as the master clock for all analog signal
processing including analog-to-digital conversion, digital-toanalog conversion, and for transmit and receive filtering
functions of this device. The clock frequency applied to the
MCLK pin may be 256 kHz, 512 kHz, 1.536 MHz, 1.544 MHz,
2.048 MHz, 2.56 MHz, or 4.096 MHz. This device has a
prescalerthat automatically determines the proper divide ratio
to use for the MCLK input, which achieves the required 256
kHz internal sequencing clock. The clocking requirements of
the MCLK input are independent of the PCM data transfer
mode (i.e., Long-Frame Sync, Short-Frame Sync, IDL mode
or GCI mode).
DIGITALVO
The MC145480 is pin selectable for Mu-Law or A-Law. Table
1 shows the 8-bit data word format for positive and negative
zero and full scale for both companding schemes (see Tables
3 and 4 at the end of this document for a complete PCM word
conversion table). Table 2 shows the series of eight PCM
words for both Mu-Law and A-Law that correspond to a digital
milliwatt. The digital mW is the 1 kHz calibration signal
reconstructed by the DAC that defines the absolute gain or
o dBmO Transmission Level Point (TLP) of the DAC. The
dBmO level for Mu-Law is 3.17 dB below the maximum level
for an unclipped tone signal. The 0 dBmO level for A-Law is

Long Frame Sync
Long Frame Sync Is the industry name for one type of
clocking format that controls the transfer of the PCM data
words. (Refer to Figure 2a) The "Frame Sync" or "Enable"
is used for two specific synchronizing functions. The first is
to synchronize the PCM data word transfer, and the second
is to control the internal analog-to-digital and digital-to-analog
conversions. The term "Sync" refers to the function of
synchronizing the PCM data word onto or off olthe multiplexed
serial PCM data bus, which is also known as a PCM highway.
The term "Long" comes from the duration of the frame sync
measured in PCM data clock cycles. Long Frame Sync timing
occurs when the frame sync is used directly as the PCM data
output driver enable. This results in the PCM output going low
impedance with the rising edge of the transmit frame sync,
and remaining low impedance for the duration of the transmit
frame sync.
The implementation of Long Frame Sync has maintained
compatibility and been optimized for external clocking
simplicity. This optimization includes the PCM data output
going low impedance with the logical AND of the transmit
frame sync (FST) with the transmit data bit clock (BCLKT).
The optimization also includes the PCM data output (DT)
remaining low impedance until the middle of the LSB (seven
and a half PCM data clock cycles) or until the FST pin is taken
low, whichever occurs last. This requires the frame sync to
be approximately rising edge aligned with the initiation of the
PCM data word transfer, but the frame sync does not have
a precise timing requirementforthe end olthe PCM data word
transfer. The device recognizes Long Frame Sync clocking
when the frame sync is held high for two consecutive falling
edges of the transmit data clock. The transmit logic decides
on each frame sync whether it should interpret the next frame
sync pulse as a Long or a Short Frame Sync. This decision
is used for receive circuitry also. The device is designed to
prevent PCM bus contention by not allowing the PCM data
output to go low impedance for at least two frame sync cycles
after power is applied or when coming out olthe powered down
mode.

o

Table 1. PCM Codes for Zero and Full Scale
Mu-Law

A-Law

Sign Bit

Chord Bits

Step Bits

Sign Bit

Chord Bits

+ Full Scale

1

000

0000

1

010

1010

+ Zero

1

1 11

1111

1

101

0101

-Zero

0

111

1111

0

101

0101

- Full Scale

0

000

0000

0

010

1010

Level

MC145480
2-826

Step Bits

MOTOROLA COMMUNICATIONS DEVICE DATA

Table 2. PCM Codes for Digital mW
Mu-Law

A-Law

Phase

Sign Bit

Chord Bits

Step Bits

Sign Bit

Chord Bits

Step Bits

!tI8

0

001

1110

0

011

0100

3!t18

0

000

1011

0

010

0001

5!t18

0

000

1011

0

010

0001

7!t18

0

001

1110

0

011

0100

9!t18

1

001

1110

1

011

0100

11!t18

1

000

1011

1

010

0001

13!t18

1

000

1011

1

010

0001

15!t18

1

001

1110

1

011

0100

The receive side of the device is designed to accept the
same frame sync and data clock as the transmit side and to
be able to latch its own transmit PCM data word. Thus the
PCM digital switch needs to be able to generate only one type
of frame sync for use by both transmit and receive sections
of the device.
The logical AND of the receive frame sync with the receive
data clock tells the device to start latching the S-bit serial word
into the receive data input on the falling edges of the receive
data clock. The internal receive logic counts the receive data
clock cycles and transfers the PCM data word to the
digital-to-analog converter sequencer on the ninth data clock
rising edge.
This device is compatible with four digital interface modes.
To ensure that this device does not reprogram itself for a
different timing mode, the BClKR pin must change logic state
no less than every 125 1lS. The minimum PCM data bit clock
frequency of 64 kHz satisfies this requirement.
Short Frame Sync
Short Frame Sync is the industry name for the type of
clocking format that controls the transfer of the PCM data
words (refer to Figure 2b). The "Frame Sync" or "Enable"
is used for two specific synchronizing functions. The first is
to synchronize the PCM data word transfer, and the second
is to control the internal analog-to-digital and digitalto-analog conversions. The term "Sync" refers to the function
of synchronizing the PCM data word onto or off of the
multiplexed serial PCM data bus, which is also known as
a PCM highway. The term "Short" comes from the duration
of the frame sync measured in PCM data clock cycles. Short
Frame Sync timing occurs when the frame sync is used as
a "pre-synchronization" pulse that is used to tell the internal
logic to clock out the PCM data word under complete control
of the data clock. The Short Frame Sync is held high for
one falling data clock edge. The device outputs the PCM
data word beginning with the following rising edge of the data
clock. This results in the PCM output going low Impedance
with the rising edge of the transmit data clock, and remaining
low impedance until the middle of the lSB (seven and a half
PCM data clock cycles).
The device recognizes Short Frame Sync clocking when
the frame sync is held high for one and only one falling edge
of the transmit data clock. The transmit logic decides on each
frame sync whether it should interpret the next frame sync
pulse as a long or a Short Frame Sync. This decision is used

MOTOROLA COMMUNICATIONS DEVICE DATA

for receive circuitry also. The device is designed to prevent
PCM bus contention by not allowing the PCM data output to
go low impedance for at least two frame sync cycles after
power is applied or when coming out of the powered down
mode.
The receive side of the device is designed to accept the
same frame sync and data clock as the transmit side and to
be able to latch its own transmit PCM data word. Thus the
PCM digital switch needs to be able to generate only one type
of frame sync for use by both transmit and receive sections
of the device.
The falling edge of the receive data clock latching a high
logic level at the receive frame sync input tells the device to
start latching the S-bit serial word into the receive data input
on the following eight falling edges of the receive data clock.
The internal receive logic counts the receive data clock cycles
and transfers the PCM data word to the digital-to-analog
converter sequencer on the rising data clock edge after the
lSB has been latched into the device.
This device is compatible with four digital interface modes.
To ensure that this device does not reprogram itself for a
different timing mode, the BClKR pin must change logic state
no less than every 1251lS. The minimum PCM data bit clock
frequency of 64 kHz satisfies this requirement.
Interchip Digital Link (IDL)
The Interchip Digital Link (IDl) Interface is one of two
standard synchronous 2B+D ISDN timing interface modes
with which this device is compatible. In the IDl mode, the
device can communicate In either of the two 64 kbps
B channels (refer to Figure 2c for sample timing). The IDl
mode is selected when the BClKR pin is held high for two
or more FST (IDl SYNC) rising edges. The digital pins that
control the transmit and receive PCM word transfers are
reprogrammed to accommodate this mode. The pins affected
are FST, FSR, BClKT, DT and DR. The IDl Interface consists
of four pins: IDl SYNC (FST), IDl ClK (BClKT), IDl TX (DT),
and IDl RX (DR). The IDl interface mode provides access
to both the transmit and receive PCM data words with common
control clocks of iDl Sync and IDl Clock. In this mode, the
FSR pin controls whether the B1 channel or the B2 channel
is used for both transmit and receive PCM data word transfers.
When the FSR pin is low, the transmit and receive PCM words
are transfered in the B1 channel, and for FSR high the B2
channel is selected. The start of the B2 channel is ten IDl
ClK cycles after the start of the B1 channel.

MC145480
2-827

FST(FSR)
BCLKT (BCLKR)
DT
DON'T CARE
Figure 2a. Long Frame Sync (Transmit and Receive have individual clocking)

FST(FSR)
BCLKT (BCLKR)
DT

DR

2

I

DON'T CARE

I

6
3

7
DON'T CARE

4

Figure 2b. Short Frame Sync (Transmit and Receive have Individual clocking)

IDL SYNC (FST)
IDL CLOCK (BCLKT)
IDL TX (DT)
IDLRX (DR)
B1·CHANNEL (FSR = 0)
Figure 2c. IDL Interface -

FSC (FST)

__

~n~

BCLKR

B2·CHANNEL (FSR = 1)

=1 (Transmit and Receive have common clocking)

_______________________________

DCL(BCLKT)
DoudDT)
Din (DR)

DON'T
CARE

3

4

7

4

7

B1·CHANNEL (FSR = 0)
Figure 2d. GCllnterface -

BCLKR

Is H
I sl

4

6

4

7
7

lsi
lsi

DON'T CARE

B2·CHANNEL (FSR = 1)

=0 (Transmit and Receive have common clocking)

Figure 2. Digital Timing Modes for the PCM Data Interface

MC145480
2-828

MOTOROLA COMMUNICATIONS DEVICE DATA

The IDl SYNC (FST, Pin 14) is the input for the IDl frame
synchronization signal. The signal at this pin is nominally high
for one cycle of the IDl Clock signal and is rising edge aligned
with the IDl Clock signal. (Refer to Figure 4 and the IDl Timing
specifications for more details.) This event identifies the
beginning of the IDl frame. The frequency of the IDl Sync
signal is 8 kHz. The rising edge of the IDl SYNC (FST) should
be aligned approximately with the rising edge of MClK. MClK
must be one of the clock frequencies specified in the Digital
Switching Characteristics table, and is typically tied to IDl ClK
(BClKT).
The IDlClK (BClKT, Pin 12) is the inputforthe PCM data
clock. AlilDl PCM transfers and data control sequencing are
controlled by this ciock following the IDl SYNC. This pin
accepts an IDl data clock frequency of 256 kHz to 4.096 MHz.
The IDl TX (DT, Pin 13) is the output for the transmit PCM
data word. Data bits are output for the B1 channel on
sequential rising edges of the IDl ClK signal beginning after
the IDl SYNC pulse. If the B2 channel is selected, then the
PCM word transfer starts on the eleventh IDl ClK rising edge
after the IDl SYNC pulse. The IDl TX pin will remain low
impedance forthe duration of the PCM word until the lSB after
the falling edge of IDl ClK. The IDl TX pin will remain in a
high impedance state when not outputting PCM data or when
a valid IDl Sync signal is missing.
The IDl RX (DR, Pin 8) is the input for the receive PCM
data word. Data bits are inputforthe B1 channel on sequential
falling edges of the IDl ClK signal beginning after the IDl
SYNC pulse. If the B2 channel is selected, then the PCM word
is latched in starting on the eleventh IDl ClK falling edge after
the IDl SYNC pulse.

specified in the Digital Switching Characteristics table, and
is typically tied to DCl (BClKT).
The DCl (BClKT, Pin 12) is the input for the clock that
controls the PCM data transfers. The clock applied at the DCl
input is twice the actual PCM data rate. The GCI frame begins
with the logical AND of the FSC with the DCL. This event
initiates the PCM data word transfers for both transmit and
receive. This pin accepts a GCI data clock frequency of
512 kHz to 6.176 MHz for PCM data rates of 256 kHz to 3.088
MHz.
The GCI Dout (DT, Pin 13) is the output for the transmit
PCM data word. Data bits are output for the B1 channel on
alternate rising edges of the DCl clock signal, beginning with
the FSC pulse. If the B2 channel is selected, then the PCM
word transfer starts on the seventeenth DCl rising edge after
the FSC rising edge. The Dout pin will remain low impedance
for 15-112 DCl clock cycles. The Dout pin becomes high
impedance after the second falling edge of the DCl clock
during the lSB of the PCM word. The Dout pin will remain
in a high-impedance state when not outputting PCM data
or when a valid FSC signal is missing.
The Din (DR, Pin 8) is the input for the receive PCM data
word. Data bits are latched in for the B1 channel on alternate
rising edges of the DCl clock Signal, beginning with the
second DCl clock after the rising edge of the FSC pulse. If
the B2 channel is selected then the PCM word is latched in
starting on the eighteenth DCl rising edge after the FSC rising
edge.

General Circuit Interface (GCI)
The General Circuit Interface (GCI) is the second of two
standard synchronous 2B + D ISDN timing interface modes
with which this device is compatible. In the GCI mode, the
device can communicate in either of the two 64 kbps
B-channels. (Refer to Figure 2d for sample timing.) The GCI
mode is selected when the BClKR pin is held low for two
or more FST (FSC) rising edges. The digital pins that control
the transmit and receive PCM word transfers are reprogrammed to accommodate this mode. The pins affected are
FST, FSR, BClKT, DT and DR. The GCI Interface consists
of four pins: FSC (FST), DCl (BClKT), Dout (DT), and Din
(DR). The GCI interface mode provides access to both the
transmit and receive PCM data words with common control
clocks of FSC (frame synchronization clock) and DCl (data
clock). In this mode, the FSR pin controls whether the B1
channel or the B2 channel is used for both transmit and
receive PCM data word transfers. When the FSR pin is low,
the transmit and receive PCM words are transfered in the
B1 channel, and for FSR high the B2 channel is selected.
The start of the B2 channel is 16 DCl cycles after the start
of the B1 channel.
The FSC (FST, Pin 14) is the input for the GCI frame
synchronization signal. The signal atthis pin is nominally rising
edge aligned with the DCl clock signal. (Refer to Figure 6
and the GCI Timing specifications for more details.) This event
identifies the beginning of the GCI frame. The frequency of
the FSC synchronization signal is 8 kHz. The rising edge of
the FSC (FST) should be aligned approximately with the rising
edge of MClK. MClK must be one of the clock frequencies

The MC145480 is manufactured using high-speed CMOS
VlSI technology to implement the complex analog signal
processing functions of a PCM codec-filter. The fully
differential analog circuit design techniques used for this
device result in superior performance for the switched
capacitor filters, the analog-to-digital converter (ADC) and the
digital-to-analog converter (DAC). Special attention was given
to the design of this device to reduce the sensitivities of noise,
including power supply rejection and susceptibility to radio
frequency noise. This special attention to design includes a
fifth order low-pass filter, followed by a third order high-pass
filter whose output is converted to a digital signal with greater
than 75 dB of dynamic range, all operating on a single 5 V
power supply. This results in a Mu-law lSB size for small
audio signals of about 38611V. The typical idle channel noise
level of this device is less than one lSB. In addition to the
dynamic range of the codec/filter function of this device, the
input gain-setting op amp has the capability of greater than
35 dB of gain intended for an electret microphone interface.
This device was designed for ease of implementation, but
due to the large dynamic range and the noisy nature of the
environmentforthis device (digital switches, radio telephones,
DSP front-end, etc.) special care must be taken to assure
optimum analog transmission performance.

MOTOROLA COMMUNICATIONS DEVICE DATA

PRINTED CIRCUIT BOARD LAYOUT
CONSIDERATIONS

PC BOARD MOUNTING
It is recommended that the device be soldered to the PC
board for optimum noise performance. If the device is to be
used in a socket, it should be placed in a low parasitic pin
inductance (generally, low-profile) socket.

MC145480
2-829

Power Supply, Ground, and Noise
Considerations
This device is intended to be used in switching applications
which often require plugging the PC board into a rack with
power applied. This is known as "hot-rack insertion." In these
applications care should be taken to limit the voltage on any
pin from going positive of the VDD pins, or negative of the
VSS pins. One method is to extend the ground and power
contacts of the PCB connector. The device has input
protection on all pins and may source or sink a limited
amount of current without damage. Current limiting may be
accomplished by series resistors between the signal pins and
the connector contacts.
The most important considerations for PCB layout deal with
noise. This includes noise on the' power supply, noise
generated by the digital circuitry on the device, and cross
coupling digital or radio frequency signals into the audio
signals of this device. The best way to prevent noise is to:
1. Keep digital signals as far away from audio signals as
possible.
2. Keep radio frequency signals as far away from the
audio signals as possible.
3. Use short, low inductance traces for the audio circuitry
to reduce inductive, capacitive, and radio frequency
noise sensitivities.
4. Use short, low inductance traces for digital and RF
circuitry to reduce inductive, capacitive, and radio
frequency radiated noise.
5. Bypass capacitors should be connected from the VDD
and VAG pins to VSS with minimal trace length. Ceramic
monolithic capacitors of about 0.1 IlF are acceptable
to decouple the device from its own noise. The VDD
capacitor helps supply the instantaneous currents of
the digital circuitry in addition to decoupling the noise
which may be generated by other sections of the
device or other circuitry on the power supply. The VAG
decoupling capacitor helps to reduce the impedance
of the VAG pin to VSS at frequencies above the bandwidth of the VAG generator, which reduces the
susceptibility to RF noise.
6. Use a short, wide, low inductance trace to connect the
VSS ground pin to the power supply ground. The VSS
pin is the digital ground and the most negative power
supply pin for the analog circuitry. All analog signal
processing is referenced to the VAG pin, but because
digital and RF circuitry will probably be powered by
this same ground, care must be taken to minimize high
frequency noise in the VSS trace. Depending on the
application, a double sided PCB with a VSS ground
plane connecting all of the digital and analog VSS pins
together would be a good grounding method. A multilayer PC board with a ground plane connecting all of
the digital and analog VSS pins together would be the
optimal ground configuration. These methods will result in the lowest resistance and the lowest inductance
in the ground circuit. This is important to reduce voltage
spikes in the ground circuit resulting from the high
speed digital current spikes. The magnitude of digitally
induced voltage spikes may be hundreds of times
larger than the analog signal the device is required to
digitize.

MC145480
2-830

7. Use a short, wide, low inductance trace to connect the
VDD power supply pin to the 5 V power supply. Depending on the application, a double sided PCB with
VDD bypass capacitors to the VSS ground plane, as
described above, may complete the low impedance
coupling for the power supply. For a multilayer PC
board with a power plane, connecting all of the VDD
pins to the power plane would be the optimal power
distribution method. The integrated circuit layout and
packaging considerations for the 5 V VDD power circuit
are essen- tially the same as for the VSS ground circuit.
8. The VAG pin is the reference for all analog signal
processing. In some applications the audio signal to
be digitized may be referenced to the VSS ground. To
reduce the susceptibility to noise at the input of the
ADC section, the three terminal op amp may be used
in a differential to single ended circuit to provide level
conversion from the VSS ground to the VAG ground with
noise cancellation. The op amp may be used for more
than 35 dB of gain in microphone interface circuits,
which will require a compact layout with minimum trace
lengths as well as isolation from noise sources. It is
recommended that the layout be as symmetrical as
possible to avoid any imbalances which would reduce
the noise cancelling benefits of this differential op amp
circuit. Refer to the application schematics for examples of this circuitry.
If possible, reference audio signals to the VAG pin
instead of to the VSS pin. Handset receivers and telephone line interface circuits using transformers may
be audio signal referenced completely to the VAG pin.
Refer to the application schematics for examples of
this circuitry. The VAG pin cannot be used for ESD or
line protection.
9. For applications using multiple MC145480 PCM codec-filters, the VAG pins cannot be tied together. The
VAG pins are capable of sourcing and sinking current
and will each be driving the node, which will result in
large contention currents, crosstalk susceptibilities,
and increased noise.
10. The MC145480 is fabricated with advanced high speed
CMOS technology'that is capable of responding to
noise pulses on the clock pins of 1 ns or less. It should
be noted that noise pulses of such short duration may
not be seen with oscilloscopes that have less bandwidth than 600 MHz. The most often encountered
sources of clock noise spikes are inductive or capacitive coupling of high-speed logic Signals, and ground
bounce. The best solution for addressing clock spikes
from coupling is to separate the traces and use short
low inductance PC board traces. To address ground
bounce problems, all integrated circuits should have
high frequency bypass capacitors directly across their
power supply pins, with low inductance traces for
ground and power supply. A less than optimum solution
may be to limit the bandwidth of the trace by adding
series resistance and/or capacitance at the input pin.

MOTOROLA COMMUNICATIONS DEVICE DATA

MAXIMUM RATINGS (Voltages Referenced to VSS Pin)
Rating

Symbol

Value

Unit

VDD

- 0.5 to 6

V

Voltage on any Analog Input or Output Pin

VSS - 0.3 to VDD + 0.3

V

Voltage on any Digital Input or Output Pin

VSS - 0.3 to VDD + 0.3

V

TA

-40 to + 85

°c

Tstg

- 85 to+150

°c

DC Supply Voltage

Operating Temperature Range
Storage Temperature Range

POWER SUPPLY (TA = - 40 to + 85°C)
Characteristics
DC Supply Voltage
Active Power Dissipation

(No Load, PI " VDD - 0.5 V)
(No Load, PI ~ VDD - 1.5 V)

Power Down Dissipation (VIH for logic levels must be " 3.0 V)
PDI=VSS
FST and FSR = VSS, PDI = VDD

Min

Typ

Max

4.75

5.0

5.25

V

-

23
25

33
35

mW

0.01
0.1

0.5
1.0

mW

-

Unit

DIGITAL LEVELS (VDD = + 5 V ± 5%, VSS = 0 V, TA = - 40 to + 85°C)
Symbol

Min

Max

Unit

Input Low Voltage

Characteristics

VIL

-

0.6

V

Input High Voltage

VIH

2.2

-

V

Output Low Voltage (DT pin, iOL= 2.5 rnA)

VOL

-

0.4

V

-

V

Output High Voltage (DT pin, IOH = - 2.5 rnA)

VOH

VDD-0.5

Input Low Current (VSS ~ Yin ~ VDD)

IlL

-10

+10

Input High Current (VSS ~ Yin ~ VDD)

IIH

-10

+10

ItA
ItA

Output Current in High Impedance State (VSS ~ DT ~ VDD)

IOZ

-10

Input Capacitance of Digital Pins (except DT)
Input Capacitances of DT pin when High-Z

MOTOROLA COMMUNICATIONS DEVICE DATA

+ 10

J.lA

Cin

-

10

pF

Cout

-

15

pF

MC145480
2-831

ANALOG ELECTRICAL CHARACTERISTICS (VDD

=+ 5 V ± 5%, VSS =0 V, TA =- 40 to + 85°C)

Characteristics

Min

Input Current

TI+,TI-

AC Input Impedance to VAG (1 kHz)

TI+,TI-

Input Capacitance

TI+,TI-

-

Input Offset Voltage of TG Op Amp

TI+,TI-

-

Input Common Mode Voltage Range

TI+, TI-

1.2

Input Common Mode Rejection Ratio

TI+, TI-

-

-

Mn

10

pF

-

±5

mV

VDD-2.0

V

60

-30

-

-

3000

-

±1.0

-

TG, RO+, and RO-

2

-

Output Impedance (0 to 3.4 kHz)

RO+or RO-

-

Output Load Capacitance

RO+or RO-

TG, RO+, RO-

Output Current (0.5 V S Vout S VDD - 0.5 V)
Output Load Resistance to VAG

DC Output Offset Voltage of RO+ or Ro- Referenced to VAG
VAG Output Voltage Referenced to VSS (No Load)
VAG Output Current with ± 25 mV Change In Output Voltage
Power Supply Rejection Ratio
(0 to 100 kHz @100 mVrrns applied to VDD,
C-Message Weighting, all analog signals
referenced to VAG pin.)

Transmit
Receive

-

0
0.5
1.0

Unit

-

-

Equivalent Input Noise (C-Mess) Between TI+ and TI- at TG
Output Load Capacitance for TG Op Amp

=
=

I1A

1.0

95

DC Open Loop Gain of TG Op Amp (RL ~ 10 kil)

Output Voltage Range for TG
(RL 10 k!l to VAG)
(RL 2 kn to VAG)

Max
±1.0

-

-

Gain Bandwidth Product (10kHz) of TG Op Amp (RL ~ 10 kn)

Typ
±0.1

1

100

dB
kHz
dB
dBmC
pF
V

VDD-0.5
VDD-l.0

-

mA
kn
n

O

-

500

pF

-

-

±25

mV

2.6

V

2.2

2.4

±2.0

±10

50
50

80
75

-

±0.05

±1.0

I1A

-

-

Mn

±20

mV

±50

mV

mA
dBC

Power Drivers PI, PO+, POInput Current (VAG - 0.5 V S PI S VAG + 0.5 V)

PI

-

Input Resistance (VAG - 0.5 V S PI S VAG + 0.5 V)

PI

10

Input Offset Voltage

PI

Output Offset Voltage of PO+ Relative to PO- (Inverted Unity Gain for PO-)

±10

Output Current (VSS + 0.7 V S PO+ or PO- S VDD - 0.7 V)

-

PO+ or PO- Output Resistance (Inverted Unity Gain for PO-)
Gain Bandwidth Product (10kHz, Open Loop for PO-)
Load Capacitance (PO+ or PO-to VAG, or PO+to PO-)
Gain of PO+ Relative to PO- (RL

=300 n, + 3 dBmO, 1 kHz)

Total Signal to Distortion at PO+ and PO- with a 300 n Differential Load
Power Supply Rejection Ratio
(0 to 25 kHz @ 100 mVrms applied to VDD.
PO- Connected to PI. Differential or measured
referenced to VAG pin.)

MC145480
2-832

-

Ot04kHz
4to 25 kHz

1
1000

-

mA
n
kHz

0

-

1000

pF

-0.2

0

+0.2

dB

45

60

40

55
40

-

-

dBC
dB

MOTOROLA COMMUNICATIONS DEVICE DATA

ANALOG TRANSMISSION PERFORMANCE
(VDD = + 5 V ± 5%, VSS = 0 V, All Analog Signals Referenced to VAG, 0 dBmO = 0.775 Vrms = +0 dBm @ 600 n, FST = FSR = 8 kHz,
BCLKT = MCLK = 2.048 MHz Synchronous Operation, TA = - 40 to + 85°C, Unless Otherwise Noted)

Min

Absolute Gain (0 dBmO @ 1.02 kHz, TA=25°C, VDD = 5.0 V)

oto +70°C

Absolute Gain Variation with Temperature

-40 to +85°C
Absolute Gain Variation with Power Supply (TA = 25°C)
Gain vs Level Tone (Mu-Law, Relative to -10 dBmO, 1.02 kHz)
+ 3 to-40 dBmO @ Oto +85°C
+ 3 to-40dBmO @-40toO°C
- 40 to - 50 dBmO @ 0 to +85°C
-40 to-50dBmO @-40toO°C
- 50 to - 55 dBmO @ 0 to +85°C
-50 to-55dBmO @-40toO°C
Gain vs Level Pseudo Noise, CCITT G.712
(A-Law, Relative to -10 dBmO)

-10to-40dBmO
-40to-50 dBmO
-50 to-55 dBmO

Total Distortion, 1.02 kHz Tone (Mu-Law, C-Message Weighting)
+3dBmO
Oto-30 dBmO
- 40 dBmO @ 0 to +85°C
-40 dBmO @ -40 to O°C
-45 dBmO
Total Distortion, Pseudo Noise, CCITT G.714 (A-Law)
- 3dBmO
- 6 to - 27 dBmO
-34dBmO
- 40 dBmO @ 0 to +85°C
- 40 dBmO @ - 40 to O°C
-55dBmO
Idle Channel Noise (For End-to-End and AID, See Note 1)
(Mu-Law, C-Message Weighted)
(A-Law, Psophometric Weighted)
Frequency Response (Relative to 1.02 kHz @ 0 dBmO)
15Hz
50 Hz
60 Hz
200 Hz
300 to 3000 Hz
3300 Hz
3400 Hz
4000 Hz
4600 Hz to 100 kHz
Inband Spurious (1.02 kHz @ 0 dBmO, Transmit and Receive)
300 to 3000 Hz
Out-of-Band Spurious at RO+ (300 to 3400 Hz @ 0 dBmO in)
4600 to 7600 Hz
7600 to 8400 Hz
8400 to 100,000 Hz
Idle Channel Noise Selective (8 kHz, Input = VAG, 30 Hz Bandwidth)
Absolute Delay (1600 Hz)
Group Delay Referenced to 1600 Hz
500 to 600 Hz
600 to 800 Hz
800 to 1000 Hz
1000 to 1600 Hz
1600 to 2600 Hz
2600 to 2800 Hz
2800 to 3000 Hz
Crosstalk of 1020 Hz @ 0 dBmO from AID or D/A (Note 2)
Intermodulation Distortion of two Frequencies of Amplitudes
(- 4 to - 21 dBmO from the Range 300 to 3400 Hz)

--

-

D/A

AID

End-to-End
Characteristics

Min

Max

Min

Max

Units

-

-0.25

+0.25

-0.25

+0.25

dB

-

-

±0.03
±0.05

dB

±0.04

dB

Max

-

-

-48
-30

-40
-30
-70

-41

±0.03

-

-0.25
-0.25
-0.8
-0.8
-1.3
-1.3

+0.25
+0.25
+0.8
+0.8
+1.3
+1.3

-0.20
-0.25
-0.5
-0.9
-1.0
-1.8

+0.20
+0.25
+0.5
+0.9
+ 1.0
+ 1.8

-0.25
-0.60
-1.00

+ 0.25
+0.30
+0.45

-0.25
-0.30
-0.45

+ 0.25
+ 0.30
+0.45

±0.03
±0.05

dB

dB

34
36
30
28.5
25

-

34
36
30
28.5
25

-

30.0
35.0
34.0
28.5
28.0
13.5

-

30.0
36.0
34.5
29.5
28.5
14.5

-

-

18
-68

-

11
-78

dBC

-

dB

dBrncO
dBmOp
dB

-

-1.0
-0.20
-0.35
-0.8

-

-40
-30
-26
-0.4
+0.15
+0.15
0
-14
-32
-48

315
210
130
70
35
70
95
. 145

-0.5
-0.5
-0.5
-0.5
-0.15
-0.35
-0.8

-

-40
-40
-40
-30

-

0
0
0
0
+0.15
+0.15
0
-14
30
dB
-48
dB
-30
-40
-30
-70

dBmO

205

I1S

-

I1S

-

85
110
175

-75

-

-70

-41

-

-41

dB
dB

NOTES: 1. Extrapolated from a 1020 Hz @ - 50 dBmO distortion measurement to correct for encoder enhancement.
2. Selectively measured while stimulated with 2667 Hz @ - 50 dBmO.

MOTOROLA COMMUNICATIONS DEVICE DATA

MC145480
2-833

DIGITAL SWITCHING CHARACTERISTICS, LONG FRAME SYNC AND SHORT FRAME SYNC
(VDD = +5 V±5%, VSS = OV, All Digital Signals Referenced to VSS, TA =-40 to + 85°C, Cl = 150 pF, Unless Otherwise Noted)
Ref#

Characteristics

1

Master Clock Frequency for MClK

Min

TyP

Max

-

256
512
1536
1544
2048
2560
4096

-

Unit
kHz

1

MClK Duty Cycle for 256 kHz Operation

45

2

Minimum Pulse Width High for MClK (Frequencies of 512 kHz or Greater)

50

3

Minimum Pulse Width low for MClK (Frequencies of 512 kHz or Greater)

50

Rise Time for All Digital Signals

-

5

Fall Time for All Digital Signals

-'

-

6

Setup Time from MClK low to FST High

50

-

7

Setup Time from FST High to MClK low

50

-

-

ns

4096

kHz

4

8

Bit Clock Data Rate for BClKT or BClKR

64

9

Minimum Pulse Width High for BClKT or BClKR

50

10

Minimum Pulse Width low for BClKT or BClKR

50

11

Hold Time from BClKT (BClKR) low to FST (FSR) High

20

12

Setup Time for FST (FSR) High to BClKT (BClKR) low

80

13

Setup Time from DR Valid to BClKR low

0

14

Hold Time from BClKR low to DR Invalid

50

55

-

%
ns
ns

50

ns

50

ns

-

ns

-

ns
ns
ns
ns
ns
ns

LONG FRAME SPECIFIC TIMING

-

ns

-

-

60

ns

60

ns

Delay Time from the later of the 8th BClKT Falling Edge, or the Failing Edge of FST to
DT Output High Impedance

10

-

60

ns

Minimum Pulse Width low for FST or FSR

50

-

-

ns

-

-

15

Hold Time from 2nd Period of BClKT (BClKR) low to FST (FSR) low

16

Delay Time from FST or BClKT, Whichever Is Later, to DT for Valid MSB Data

17

Delay Time from BClKT High to DT for Valid Chord and Step Bit Data

18
19

50

SHORT FRAME SPECIFIC TIMING
20

Hold Time from BClKT (BClKR) low to FST (FSR) low

50

21

Setup Time from FST (FSR) low to MSB Period of BClKT (BClKR) low

50

22

Delay Time from BClKT High to DT Data Valid

10

23

Delay Time from the 8th BClKT low to DT Output High Impedance

10

MC145480
2-834

ns
ns

60

ns

60

ns

MOTOROLA COMMUNICATIONS DEVICE DATA

MCLK

BClKT

FST

DT

BClKA

FSA

DA

Figure 3. Long Frame Sync Timing

MOTOROLA COMMUNICATIONS DEVICE DATA

MC145480
2-835

MClK

BClKT

FST

DT

BClKA

FSA

DA

Figure 4. Short Frame Sync Timing

MC145480
2-836

MOTOROLA COMMUNICATIONS DEVICE DATA

DIGITAL SWITCHING CHARACTERISTICS FOR IDL MODE
(VDD =5.0 V ± 5%, TA =- 40 to + 85°C, Cl =150 pF, See Figure 5, Note 1.)
Ref#

Characteristics

Min

Max

Unit

Note 2

31

Time Between Successive IDl Syncs

32

Hold Time of IDl SYNC After Falling Edge of IDl ClK

20

Setup Time of IDl SYNC Before Falling Edge IDl ClK

60

-

ns

33
34

IDl Clock Frequency

256

4096

kHz

35

IDl Clock Pulse Width High

50

-

ns

36

IDl Clock Pulse Width low

50

-

ns

37

Data Valid on IDl RX Before Falling Edge of IDl ClK

20

-

ns

38

Data Valid on IDl RX After Falling Edge of IDl ClK

75

-

ns

39

Falling Edge of IDl ClK to High Z on IDl TX

10

50

ns'

40

Rising Edge of IDl ClK to low Z and Data Valid on IDl TX

10

60

ns

41

Rising Edge of IDl ClK to Data Valid on IDl TX

-

50

ns

ns

NOTES: 1. Measurements are made from the point at which the logic signal achieves the guaranteed minimum or maximum logiC level.
2. In IDl mode, both transmit and receive 8-bit PCM words are accessed durtng Bl channel or both transmit and receive. 8-bit PCM words
are accessed durtng the B2 channel as shown in Figure 5. IDl accesses must occur at a rate of 8 kHz (1251's interval).

~----------------------------{31r-------------------------------~

IDLE SYNC
(FST)

IDLCLOCK
(BCLKT)

IDL TX
(DT)

IDLRX
(DR)

Figure 5. IDL Interface Timing

MOTOROLA COMMUNICATIONS DEVICE DATA

MC145480

2-837

DIGITAL SWITCHING CHARACTERISTICS FOR GCI MODE
(VDD =5.0 V ± 5%, TA =- 40 to + 85°C, Cl =150 pF, See Figure 6, Note 1.)
Ref#

Min

Characteristics

42

Time Between Successive FSC Pulses

Max

Unit

Note 2

43

DCl Clock Frequency

512

44

DCl Clock Pulse Width High

50

-

ns

45

DCl Clock Pulse Width low

50

-

ns

46

Hold Time of FSC After Falling Edge of DCl

20

ns

47

Setup Time of FSC to DCl Falling Edge

60

-

48

Rising Edge of DCl (After Rising Edge of FSC) to low Impedance and Valid Data of Dout

60

ns

49

Rising Edge of FSC (While DCl is High) to low Impedance and Valid Data of Dout

60

ns

50

Rising Edge of DCl to Valid Data on Dout

-

60

ns

51

Second DCl Falling Edge During lSB to High Impedance of Dout

10

50

ns

52

Setup Time of Din Before Rising Edge of DCl

20

-

ns

53

Hold Time of Din After DCl Rising Edge

-

60

ns

6176

kHz

ns

NOTES: 1. Measurements are made from the point at which the logic signal achieves the guaranteed minimum or maximum logic level.
2.. In GCI mode, both transmit and receive 8-bit PCM words are accessed during B1 channel or both transmit and receive 8-bit PCM
words are accessed during the B2 channel as shown in Figure 6. GCI accesses must occur at a rate of 8 kHz (12511S interval).

FSC
(FST)

DCl

(BClKn

D'

(Olin

FSC
(FST)

oCl
(BClKT)

Figure 6. GCllnterface Timing

MC145480
2-838

MOTOROLA COMMUNICATIONS DEVICE DATA

+

1

AUDIO OUT

2

-

3

~

...!..
...E....
6

+5V

'1

7
8
9
10

RO+

VAG

RO-

TI+

PI

TI-

PO-

TG

I

20
19

VOO

VSS

FSR

FST

DR

OT
BClKT

BClKR

MClK

POI

~

O.lI1F
ANALOG IN

1~ I1F

10kU

I-

18
17

10kU

1

WkQ

J

1.0

MulA 16

PO+

-1
10kQ

+5V

15
':'

14

8k Hz

13

PC MOUT

12

2.048 MHz

11

PC MIN

Figure 7. MC145480 Test Circuit with Differential Input and Output

AUDIO OUT
Rl;' 2kU

1
10kU

.1.
3

AUDIO OUT
Rl;' 150 U

:r=;r

6811F

+

10kQ

4

.J.

10 k

6
7

O.l 11F

8
9

I

I

10

RO+

VAG

RO-

TI+

PI

TI-

PO-

TG

20

17

PO+

VSS

FSR

FST

DR

OT
BClKT
MClK

10kU

j

18

VOO

POI

10kU

19

MulA 16

BClKR

J-. O.lI1F

I
10kQ

1

10kU

.J
1.

+5V

15
14

':'

13
12

8 kHz
PCMOUT
2. 048 MHz

11

PCMIN

Figure 8. MC145480 Test Circuit with Input and Output Referenced to VSS

MOTOROLA COMMUNICATIONS DEVICE DATA

MC145480

2-839

+5V

.-------+

2.D4BMHz
(BClKT, BClKR, MClK)

.----L----.:::..--1-~---.t::::::::t:;___,
OSC IN

OSC
OSC
OUT 1 OUT2
MC74HC4060

VCC
0.111

BkHz
(FST, FSR)

Q4

QH-I--i

Q

112 MC74HC73

'-0

K

R
+5V

L

BkHz
4

256

6

7

2.04BMHz

Figure 9. Long Frame Sync Clock Circuit for 2.048 MHz
+5V
lkQ
SIDETONE
O.I I1F I
420pF

2

4

RO+

VAG

RO-

TI+

PI

TI-

PO-

TG

PO+

MulA

VDD

VSS

FSR

FST

REC
+5V
7
O. II1F I

DR
+5V

BClKR

20
19
MIC

lB
17
16
15

+5V

420pF

14
-=
1-'-'---------IDl SYNC -B kHz

DT f 13
- - ! ! : . . - - - - - - - - - IDl TX
12
BCLKT 1-"'----....
- - - - - IDlClOCK-2.D4BMHz

-'=======-________
10

L __

PDI

MClK

11

IDlRX

~----------------------------------------~:~~V
Figure 10. MC145480 Analog Interface to Handset with IDL Clocking

MC145480
2-840

MOTOROLA COMMUNICATIONS DEVICE DATA

1.0~F

10k!:!

r---!
1

RO= 600!:!

TIP

[311 ~

---2..

10k!:!
10k!:!

RO

3

t5V

1

RO-

Tit

19

TI-

18

PI
PO-

TG

17

5

POt

MulA

16

6
7

I

0.1~F

VAG

4
N=1

RING

9

VSS

FSR

FST

14

10

BClKR
PDI

1

T

0.1

~F

10kn
t5V

15

VDD

8 DR

-:!:-

20

ROt

DT

13

BClKT

12

MClK

11

-:....

FSC-8 kHz
Dout

DCl-4.096 MHz

1

B1-0V
B2-t5V

Figure 11. MC145480 Transformer Interface to 600

1.0~F

10kn

r-----1
RO=600n

TIP

~
-48V~
~
RING

~

10kn

ROt

VAG

--.£.

RO-

Tit

3
4

N=0.5
5
t5V

1

0.1~FI

20

r--110kn~

1/4RO

n Telephone Line with Gel Clocking

6
7
8

~

PI

TI

PO-

TG

POt

MulA

VDD

VSS

FSR

FST

DR
BClKR
PDI

DT
BClKT
MClK

19

10.1~F

T

18
17
16

20kn
t5V

15
14
13
12

-=

8 kHz
PCMOUT
2.048 MHz

11

PCMIN

Figure 12. MC145480 Step-Up Transformer Interface to 600

MOTOROLA COMMUNICATIONS DEVICE DATA

n Telephone Line

MC145480
2-841

Table 3. Mu-Law Encode-Decode Characteristics
Chord
Number

Number
of Steps

Step
Size

Normalized
Encode
Decision
Levels
8159

8

16

256

Digital Code
1
Sign

1

I
I
I 4 I 5 I 6 I 7 I 8
I Chord I Chord I Chord I Step I Step I Step I Step
2

3

0

0

0

7903
4319

16

128

2143

16

64

1055

16

32

511

16

16

239

16

8

103

16

4

35

1

1

2
1

3
1

1

1

1

4191

1

1

1

1

2079

1

1

1

1

1023

1

1

1

1

495

1

1

1

1

231

1

1.

1

1

99

1

1

1

1

33

:

0

0

1

1

0

1

0

1

0

1

1

1

1

0

0

1

1

0

1

1

1

1

0

1

1

1

1

1

1

1

0

2

1

1

1

1

1

1

1

1

0

:

:

:

:

:

:

:

:

:

:

:

31
15

1

1

95
2

8031

0

223
3

0

0

479
4

0

0

991
5

0

1

2015
6

0

:

4063
7

Normalized
Decode
Levels

:

:

:

0
NOTES:
1. Characteristics are symmetrical about analog zero with sign bit = 0 for negative analog values.
2. Digital code includes inversion of all magnitude bits.

MC145480
2-842

MOTOROLA COMMUNICATIONS DEVICE DATA

Table 4. A-Law Encode-Decode Characteristics
Chord
Number

Number
of Sleps

Slep
Size

Normalized
Encode
Decision
Levels

4096
7

16

128

Digital Code

1
Sign

1

3968
2176

I

2

I

3

I

4

16

64

5

16

32

4

16

16

3

16

8

2

16

4

1088
1024
544

a

1

a

1

a

1

a

1

a

1

1

1

a

a

a

1

a

a

1

1

1

1

a

68
64

1

32

2

2

a

a

1

a

4032

a

1

a

1

2112

a

1

a

1

1056

a

1

a

1

528

a

1

a

1

264

a

1

a

1

132

:

:

:

:

:

:

:

128

:

:

1

1

1

1

:

a

1

a

1

66

a

1

a

1

1

:

1

1

a

1

Normalized
Decode
Levels

1

:

256
136

I 6 I 7 I 8
I Slep I Slep I Slep

:

512
272

5

I Chord I Chord I Chord I Slep

2048
6

I

:

NOTES:
1. Characteristics are symmetrical about analog zero with sign bit = a for negative analog values.
2. Digital code includes inversion of all even numbered bits.

MOTOROLA COMMUNICATIONS DEVICE DATA

MC145480
2-843

MOTOROLA

-

SEMICONDUCTOR
TECHNICAL DATA

MC145488
Technical Summary
Dual Data Link Controller
This Technical Summary gives a brief overview of the MC145488 Dual Data
Link Controller. The MC145488 is a two-channel ISDN LAPD controller with an
on-chip direct memory access (DMA) controller. It is intended for ISDN terminal
and switch applications where one or two channels of data will use HDLC-type
protocols. The DDLC can also be used in local area, wide area network, and bridge
router applications. Each serial interface can be clocked at data rates up to 10
Mbps. The DDLC can operate with microprocessors using clock frequencies up
to 20.5 MHz.
The DDLC is ideally suited for use with the MC145474 SfT transceiver. The
interchip digital link (IDL) easily connects the chips together, providing a powerful
layer one/layer two ISDN solution. A serial control port is provided to efficiently
control the MC145474 or other ISDN family devices. The DDLC is compatible
with 68000 and 80186 bus structures.

FN SUFFIX

PLCC
CASE 779

Note
This document is a summary of principal features and operation of
the DDLC. Please refer to the MC145488 DDLC data book for the
complete description and electrical specifications. It can be ordered
from your local Motorola sales office or from the Motorola Literature
Distribution Center as MC1454881D.
• Two Independent Full-Duplex Bit-Oriented Protocol Controllers Support
- HDLC, SDLC, CCITT X.25, CCITT Q.921 (LAPD), and V.120 at Basic
- and Primary Rates
• Four Channel On-Chip DMA Controller
- 64 Kbyte Address Range with Expansion Control
- Internal Programmable Wait-State Generator
- Two Buffer Descriptors for Each Receiver Channel
• Compatible with 68000 and 80186 Bus Structures
- Non-multiplexed 16- or 8-Bit Data Bus
- Frame sizes up to 4096 bytes
• Bit-Level HDLC Processing Including:
- Flag Generation/Detection
- Abort Generation/Detection
- Zero Insertion/Deletion
- CRC-CCITT Generation/Checking
- Residue Bit Handler
• TEI/SAPI Address Comparison
- Three Address Comparisons
- Wildcard Bits for Block Comparisons
• Transparent Mode for Codec Compatibility
• Programmable Interrupt Vector Generation
• Two Independent Timers Configurable as a Watchdog Timer
• Flexible Serial Interface with:
- IDL Interface for Connection to Other ISDN Family Devices
- Timeslot Interface for Connection to PBX-Type Backplanes
- Modem Interface for Other Applications
• Supports CCITT Specification 1.460
• Supports DMI Specification 3.1 Modes 0, 1, 2, and 3
• Serial Control Port for ISDN Family Device Control
• Low-Power CMOS with Automatic Power-Down
• Serial Data Rates Up to 10 Mbps
• DDLC Master Clock Up to 20.5 MHz
MICROWIRE is a trademark of National Semiconductor, Inc.

MC145488
2-844

MOTOROLA COMMUNICATIONS DEVICE DATA

BLOCK DIAGRAM

SERIAL
CONTROL
PORT
STATUS!
CONTROL
REGISTERS

CHANNEL 0
PROTOCOL
CONTROLLER

10UTOM
INTERFACE

a:

@

f3w
UU

I
MOOEM
IL _ _
INTERFACE
_ _ _ _ .J

011:
a: a:

Il.w
01-

a:z
u~

CHANNELl
PROTOCOL
CONTROLLER

10UTOM
INTERFACE

OMA
CONTROLLER
TX&RX
FIFOs

PIN ASSIGNMENTS

10LSYNC 1

015

10LCLK 1

014

CTSl

013

RTSl

012

RxOl

011

TxOl

VSS

COl
VSS
VOO
SCPEN

010
6HEAO
PLCC
(TOP VIEW)

09
08
07

COO

06

TxOO

05

RxOO

04

RTSO

03

CTSO

02

10LCLK0

01

10LSYNCO

00

MOTOROLA COMMUNICATIONS DEVICE DATA

MC145488
2-845

GENERAL DESCRIPTION
DDLC OVERVIEW
The MC145488 Dual Data Link Controller (DDLG) is a
high-performance two-channel protocol controller with an
on-chip direct memory access controller (DMAC). Each
channel has a full-duplex transceiver with independent
protocol controllers to handle the bit-level tasks of HDLC-type
bit-oriented protocols, including LAPB and LAPD. Each
channel also has dedicated DMA controllers for transmit and
receive. A transparent mode is provided which bypasses the
protocol circuitry so that serial data may be directly transferred
between the host processor's memory and the serial interface.
The DDLC's microprocessor interface is configurable to 68000
or 80186 systems and may be used in 8-bit or 16-bit bus
modes. The DDLC's master clock can be obtained from
microprocessor clocks up to 20.5 MHz.
Each channel has a serial data interface which operates
up to and above Tl or El primary rate speeds in three modes:
IDL, Timeslot, and Modem. In the IDL (Interchip Digital Link)
mode for ISDN applications, the IDL bus is supported. When
in the IDL D channel mode, the DREQ and DGRNT access
control lines to the ISDN D channel, through the MC145474
srr transceiver, are enabled. The timeslot mode is used to
connect the DDLC to PBX-type PCM highway backplanes.
Both long-frame and short-frame timing are supported as well
as synchronous transmit and receive. In the modem mode,
each channel has its own separate transmit and receive clock
inputs along with modem control lines (RTS, CTS, and CD).
The two channels are independent and may be in different
interface modes.
A serial control port (SCP) is provided to pass control
information to other devices in a system. The SCP is
compatible with Motorola's Serial Peripheral Interface (SPI)
and National Semiconductor's MICROWIRETM Plus. Two
internal timers may be used for general purpose, low
resolution timing of HDLC-type protocols. One of the timers
may be configured as a watchdog timer to reset the entire
system in the event of a hardware or software failure.
Power consumption is an important aspect of ISDN terminal
designs, and the DDLC was designed to use the minimum
power possible while maintaining maximum functionality. The
DDLC keeps power consumption to a minimum with an
automatic power-down feature that tums off sections of
circuitry that are not being used. Only those circuits that are
actually used (e.g., when the CS pin is activated for a register
read/write or when the DMA controller performs a bus
transaction) enter the normal power state for the duration of
the access and for any time required for internal processing.
Two internal loopback functions and special chip and
system test modes are available. The loopbacks are controlled
by the host for on-line maintenance. The test modes are
activated by bits in the master control register and provide
access to the internal state machines.
HDLC PROTOCOL OVERVIEW
HDLC (High-Level Data Link Control) and its descendants,
LAPB (Link Access ProtOCOl-Balanced) and LAPD (Link
Access Protocol for the D channel), are bit-oriented
synchronous protocols which are widely used in data
communications systems. LAPB and LAPD share the basic
format of HDLC but differ in minor aspects (see Figure 1).
In the packet mode, the DDLC transmits and receives data
in a format called a frame or packet. All frames start with an
opening flag and end with a closing flag. Between the flags,

MC145488
2-846

a frame contains an address field, control field, information
field, and a cyclic redundancy check field (CRG).
n BITS

1

INFORMATION

I

16 BITS
CRC

BBITS

I I
FLAG

Figure 1. HDLC Frame Format
Flag
Theflag is the unique binary pattern (01111110).11 provides
the frame boundary and a reference for the position of each
field of the frame.
Address Field
The 8- or 16-bits following the opening flag comprise the
address field. The address field is used to distinguish between
the various devices in a network. The DDLC has address
recognition circuitry included, which relieves the host from this
task.
Control Field
The 8 or 16 bits following the address field are the control
field. Commands and responses between the devices in a
network are exchanged in this field.
Information Field
This field follows the control field and precedes the CRC
field. The information field contains the data to be transferred
and may be a null field.
Cycle Redundancy Check Field
The 16-bits preceding the closing flag are the Cycle
Redundancy Check (CRC) field. This field detects bit errors
in the address, control, and information fields. Checking is with
the standard CCITT polynominal x16x12x5 + 1 for both the
transmitter and receiver. The transmitter calculates the CRC
on all bits of the frame (except for the flags) and transmits
the complement of the resulting remainder as the CRC field.
The receiver performs the similar computation on all bits
(except for the flags) and compares the result to FOB8.
Zero Insertion and Deletion
Zero insertion and deletion, which allows the content of the
frame to be transparent, is automatically performed by the
DDLC. A binary 0 is inserted by the transmitter after any
succession of five 1s within a frame (between flags). This
eliminates the possibility of data imitating a flag character. The
receiver deletes all Os that were inserted by the transmitter
to regenerate the original data.
Abort
The function of prematurely terminating a data frame is
called an abort. The transmitter aborts a frame by sending
between seven and fourteen consecutive 1s. When the
receiver detects an abort character, it responds by clearing
the FIFO and clearing the buffer in memory. It then begins
searching for a new frame.
Idle and Interframe Time Fill
For LAPB and other applications, there are three states that
the data link may be in: in-frame, inter-frame time fill, and idle.
In-frame is the period from the beginning of an opening flag
and the end of a clOSing flag. Inter-frame time fill is the period
between frames when continuous flags are transmitted. Idle
is an out-of-frame period when continuous 1s are on the link.
In LAPD, on the D channel, there are only two states: inframe
and idle. Continuous flags are not transmitted between
frames.

MOTOROLA COMMUNICATIONS DEVICE DATA

BLOCK DIAGRAM DESCRIPTION
This section is a brief overview of the internal blocks of the
DDLC. The blocks include two protocol controllers that handle
the bit-level aspects of HDLC-like packet protocols and four
FI FOs that buffer the data, a four-channel DMA controller, and
a microprocessor interface block that connects the DDLC to
the host system. Figure 3 is a simplified block diagram of the
DDLC. While the DDLC has two data transceivers, only one
is shown for simplicity.
TRANSMIT BIT HANDLER
Two identical bit-level protocol transmitters are provided
which perform HDLC-type framing. This section describes the
operation of only one transmitter, but it applies to both.
Packet Operation
The transmitter is designed to operate with as little
intervention from the host processor as possible. To transmit
a frame of data, the host merely informs the DDLC of the
starting address of the data frame in memory and the length
of the frame in bytes. The DDLC then transmits an opening
flag and the data (LSB first) from memory. When the
transmitter detects that the end of the data buffer has been
reached, a CRC field and a closing flag are appended. The
transmitter generates an abort character if the FIFO
underruns. During inter-frame periods, the DDLC can be
configured to transmit either continuous flags (7E hex) or
continuous marks (FF hex).

IDLE

L--i==~__ ABORT
DATA READY OR
FLAG IDLE

'---,:::==-__
FLAG SENT AND

ABORT OR
NOCTS

l~r~1 .m~
~ ~ ~ I~fTAI "~U=~R

ABORT
SENT
ABORT

NOCTSOR

12

(!l

a:

NOCTS

~:5;!i

I

u..LSj2§ CR1SENT
SEND
FLAG

~. ABORT OR

L......--L-..:2 --.J

State Diagram
Figure 2 is the state diagram for the transmitter in packet
operation.
Abort
The DDLC can be configured to transmit a standard HDLC
abort character. It can also transmit an abort character which
is compatible with DMI 3.1 modes 2 or 3 for restricted
B-channel applications. An abort character will be transmitted
when the TX Fifo underruns, when the Force Abort bit is set
in the Transmit Control Register, or when the CTS pin is
deasserted.
Flow Control Mechanisms
The DDLC provides two flow control mechanisms: one for
basic rate ISDN applications and the other for standard
modem applications. The following paragraphs describe the
operation of the two schemes.
ISDN D Channel Contention
When the DDLC is operating on the 0 channel with the
companion MC145474 srr transceiver, the DREQ and
DGRNT lines must be used to comply with the basic rate 0
channel contention algorithm. When the DDLC has a data
frame to transmit, it asserts DREQ (high). When DGRNT is
detected high from the MC145474 transmission from the
DDLC begins in the IDL D-bit time slots when DREQ and
DGRNT are both active. If DGRNT is deasserted (goes low)
in the middle of a frame, the DDLC automatically aborts the
frame in progress and prepares to retransmit the entire frame
when the 0 channel becomes available again. This is done
without interrupting the host.
Modem Flow Control
The transmitter indicates to a modem that it has data ready
to transmit with signals similar to 0 channel operation. In this
mode, Request-To-Send (RTS) is directly controlled by the
Transmit Enable (TE) bit. When TE is high, the RTS pin is
asserted (low). During inter-frame periods, either flags or
marks (as selected) are transmitted but the RTS pin remains
asserted until the user negates the TE bit. Transmission of
a frame, if one is ready, actually begins when the modem
asserts Clear-to-Send (CTS low). If CTS is negated for more
than one Tx CLK period while a frame is in transmission, the
frame is aborted and the DMA pOinters are reset so that the
frame can be retransmitted without interrupting the host.
Interrupts
There is one interrupt generated by the transmitter state
machine. Transmit Frame Complete indicates that an entire
frame and its closing flag have been successfully transmitted.
Ordinarily, this interrupt is used for basic rate ISDN 0 channel
operation. Two other interrupts associated with the transmitter
are generated by the DMA controller and are discussed in the
section describing the DMA controller.
Transmit FIFO
The transmitter has a FIFO which buffers it from the DMA
controller. It is four characters deep and nine bits wide. The
ninth bit is a Tag bit which is set when the the last byte of a
frame is read from memory by the DMA controller. After the
tagged byte, the DDLC sends a closing CRC and flag
sequence.

NOCTS

Figure 2. Transmitter State Diagram HDLC Operation

MOTOROLA COMMUNICATIONS DEVICE DATA

MC145488
2-847

SERIAL CONTROL PORT

t

~
~

SERIAL BUS

SERIAL
INTERFACE

TxBIT
HANDLER

-!

Rx BIT
HANDLER

10F2

~

I

TIMERS

I
Tx
FIFO

j+-f.--

L-

f-

Rx
FIFO

DMA
CONTROLLER

~

, - - MPU BUS
MPU
INTERFACE

f---

!

-j

!

1

INTERRUPTS

Figure 3. DDLC Block Diagram (One Transceiver Shown)
Transparent Operation
The transmitter has the capability of operating with
unframed data such as PCM-encoded voice or proprietary
protocols. Raw data may be transmitted from memory with
byte alignment maintained through the FIFO and transmitter.
Byte alignment signals must be provided. In the modem mode,
the alignment signal is externally generated. In IDL and
timeslot operation, it is internally generated but user programmable. The DDLC transmits data continuously as long
as there is data to transmit.

is cleared and the receiver begins searching for a flag. No
interrupt is generated.

Interframe Time Fill
The bit sequence that is transmitted between frames is
determined by the value of the ITF bit in the Transmit Control
register. The interframe time fill can be either the X.25 flag
character (7E hex) or the LAPD marks (1) idle.

FLAG
FOUND

State Diagram
Figure 4 shows the state diagram of the receiver.

NO
FLAG

FLAG
FOUND

RECEIVE BIT HANDLER
The receiver provides the complementary functions to the
transmitter. This section describes the operation of one
receiver, but it applies to both receivers.
Packet Operation
The receiver is reset and idle until the Receive Enable bit
is set, at which time it begins searching for a flag character.
When a flag is found, the selected address field of the frame,
if desired, is checked and if a match is found, the DDLC passes
the frame of data to the allocated buffer in memory. If no
address match is found, the DDLC clears the FIFO, resets
the DMA pointers, and searches for a new frame. Zeros
inserted by the transmitter are removed from the data before
placing the bytes in memory. When the closing flag is detected,
the CRC field is checked and if found to be correct, the DDLC
queues an interrupt indicating that a good data frame has been
received and is in memory. If the CRC is found to be in error,
the DDLC automatically resets the buffer pointers to the start
of the buffer and searches for a new frame.
Each receiver has two receive buffers, A and B. This permits
one buffer to be actively receiving a frame while software is
obtaining the data from and reinitializing the other buffer. If
an incoming frame is longer than the length defined for the
active receive buffer, the DDLC will switch to the second buffer
if it is enabled.
If an abort character is found, the buffer pointers in the DMA
controller are reset and the aborted frame is ignored. The FI FO

MC145488
2-848

OUT OF
FRAME

FLAG
FOUND
NO
FLAG

ABORT OR
ADDRESS
MISMATCH

Figure 4. Receiver State Diagram HDLC Operation
Non-Octet Aligned Packets
The receiver has the capability of operating in non-octet
aligned packet systems. The residue bit count indicating the
number of orphan data bits at the end of the information field
is placed in the RC bits of the Receive Status register. These
bits are valid until overwritten by another frame. In non-octet
aligned systems, the software should check the residue count
soon after receiving a Receive Buffer Complete Interrupt to
ensure that the residue count is not overwritten by the next
frame. Orphan bits are LSB justified in memory. Note: The
DDLC does not transmit non-octet aligned frames.
Address Recognition (Filtering)
The receiver can filter received frames by comparing their
address fields to user programmable addresses. Two
addresses may be programmed with another (broadcast, FF

MOTOROLA COMMUNICATIONS DEVICE DATA

hex) hardwired into the receiver. Address filtering may be
performed on either the first OR second octet following the
opening flag of a frame. Typically, in ISDN terminal
applications, the TEl address (second) field will be of interest.
In network applications, the SAP I (first) field will be checked.
A separate Wildcard register allows selected bits of Compare
Address 0 to be ignored during the comparison procedure.
If received frames are rejected by address recognition, the
receiver is reset and searches for a new frame. Address
recognition may be disabled by clearing the Address Compare
Enable bit to O.
Receive FIFO
The receiver has a FI FO that is similar to the transmitter's.
It is four characters deep and ten bits wide (eight bits for data
and two bits for the Tag). Serial bytes are produced by the
receiver and converted to parallel. As each byte is formed,
it is pushed into the FI FO. A comparator in the controller keeps
track of the occupancy of the FIFO and requests that the DMA
controller place a word of data (16-bits) in memory when there
are two or more bytes in the FIFO. In 8-bit operation, the FIFO
requests service when one or more bytes of data read are
ready to be placed in memory. If the FIFO overruns because
the DMA controller did not service a request, an interrupt is
queued. When a receiver is operating at 64 kbps in the 16-bit
mode, DMA requests from that FIFO occur at approximately
250 Ils intervals.
Transparent Operation
The DDLC receiver provides a transparent operation mode
for passing raw octet-aligned serial data to memory via DMA.
This feature is useful for storing PCM voice or proprietary
protocols in memory. When using the DDLC to pass PCM
voice to memory, maximum buffer size of 4096 bytes should
be used. The Receive Buffer Overrun Interrupt is used in
conjunction with Receive Buffers A and B that are available
for each channel when transparent mode is used. Because
the transparent mode requires that data be in eight-bit
quantities, synchronization procedures for defining octet
boundaries are required. In the modem mode, the sync signal
is externally generated and input on the CD pin. In IDL mode
timeslot operation, the sync signal is internally generated but
user programmable. Once byte alignment is obtained in the
receiver, it is maintained through the DMA controller into
memory.
Interrupts
There are two interrupts generated by the receiver. The.
receiver queues an interrupt when a frame has been
successfully received. The receive idle interrupt indicates that
15 or more consecutive 1s were received. This interrupt is
considered normal operation. The current status of receive
idle and carrier detect is available in the Receive Status
register, but the user must remember that they can change
immediately aiter being read. The carrier detect pin also
generates an interrupt when it changes state.
DMA CONTROLLER
In orderto relieve the host software from critically timed data
transfers to or from the protocol controllers, the DDLC
provides four DMA channels, one for each transmitter and
receiver.
DMA Operation
When the DMA controller detects a service request from
one of the FIFOs, it prepares the address and data from the
transfer then requests ownership of the system bus from the
host. When ownership is granted, the DMA controller assumes

MOTOROLA COMMUNICATIONS DEVICE DATA

control of the bus and transfers data either to or from memory.
Transfers are 16 bits or 8 bits, depending on the selected bus
width. When the number of bytes in a received frame is odd,
the last byte is placed in the most significant byte of the last
word. The least significant byte contains unknown data. The
receive byte count contains the correct number of bytes
received (including the CRC). When odd length frames are
transmitted, the last word read from memory has the last byte
transmitted in the most significant byte, and the least
Significant byte of that word is discarded.
The DMA controller uses a round robin strategy to service
internal DMA requests. A channel that was just serviced is
not polled again until all other channels have been polled and
serviced, if needed. The DDLC services one DMA request
per bus arbitration cycle. The DDLC does not perform burst
DMAs, so other devices can have access to the microprocessor bus. This type of operation improves system performance
and guarantees that the DDLC is well behaved.
It is impossible to precisely predict what the DDLC bus
occupancy will be, but worst case with both channels
operating full-duplex at 64 kbps (aggregate rate of 256 Kbps)
in a 16-bit 68000 system with a 12 MHz MCLK, approximately
0.66% of the host bus bandwidth is consumed by the DDLC.
Bus occupancy increases linearly with data rate. At very high
data rates, latency from the bus request to the bus grant and
interrupt service latency become the limiting factors. It must
also be kept in mind that the DDLC can generate interrupts
quickly, especially with a large number of small data packets
at a high clock rate.
Buffer Descriptors
As previously stated, the DDLC has four DMA channels.
Pointer registers and counters are required so that the DMA
controller knows where to place or fetch data in memory.
Transmit Buffer Descriptors
When the host has a frame of data to transmit, it informs the
DMA controller where the data resides in memory. A 16-bit
register, the Transmit Base Address register, points to the first
word ofthe transmitted frame and provides a 64 kbyte address
range. The host programs the address of the first word to be
transmitted into this register. The length of the data frame must
also be given to the DMA controller, so a 12-bit Transmit
Frame Length register is used to indicate the length of the
frame in bytes. Frames of up to 4096 bytes in length may be
transmitted.
Back to back frames can be transmitted by updating the
transmit buffers when the Transmit DMA Complete interrupt
is generated.
Note
Once a transmit buffer descriptor has been prepared, it
must not be disturbed until the transmit DMA complete
or transmit frame complete interrupts are generated.
Receive Buffer Descriptors
The receive buffer descriptors have a 16-Bit Receive Buffer
Base Address register, a 12-Bit Buffer Length register, and
a 12-Bit Frame Length register. The 16-Bit Base Address
register provides 64 kbyte address range and contains the
address of the first word of the data buffer to accept a data
frame. The 12-Bit Frame Length register indicates the length
of the memory buffer in bytes. Buffers of up to 4096 bytes may
be built. The DMA controller never places data outside of the
boundaries set-up by these two registers. The Frame Length
register indicates the number of bytes (including the CRC)
received.

MC145488

2-849

Each channel has a pair of buffer descriptors. These may
be used alternately so that while one buffer is filling, another
buffer is ready in-waiting. " back-to-back data frames are
received, after the first buffer has been closed the second is
immediately ready for the next frame. There must be at least
one buffer ready to accept data when the Rx Enable bit is set.
Figure 6 describes the activity of the receiver with four buffers
in memory.
If a packet is being received and no buffers are ready, the
receive FIFO will overrun, the Receiver Enable bit is reset,
and an interrupt is queued indicating the overrun. If both
descriptors are ready, then Buffer A is filled first. If a received
frame is larger than a buffer, the Buffer (A or B) Overrun
Interrupt is queued, but the receiver continues to receive and
the DMA controller places the data in the alternate buffer (if
it is available). If an altemate buffer is not ready, the Rx FIFO
Overrun Interrupt is generated and the receiver is reset.
Once a data frame has been completely received, the
number of bytes received is indicated in the Frame Length
register. The number in this register is valid only when the
Receive DMA Complete bit (Buffer A or Buffer B) in the
Receive Status register is set to '1 '.
Note: As with the transmitter, once a receive buffer
descriptor has been prepared, it must not be disturbed until
the closing flag has been found and DMA activity on the buffer
has stopped.
Address Expansion
The DDLC provides signals for expansion of the 64 kbyte
address space. The OWN pins are activated with timing
identical to the address pins to enable external address
expansion circuitry onto the address bus. Using the OWN pins
with the RiW pin, the transmit and receive buffers may all be
on separate 64 kbyte pages in memory.
Transmit Channel Operation
Figure 6 is a simplified state diagram of the DMAcontrolier's
operation when a transmit channel requests service.

RECEIVER

/

BUFFER A START ADDR·ABOO HEX
BUFFER A LENGTH·200 HEX
BUFFER B START ADDR·ADOO HEX
BUFFER B LENGTH·200 HEX
BUFFER A START ADDR·B300 HEX
BUFFER A LENGTH·200 HEX
BUFFER B START ADDR·B500 HEX
BUFFER B LENGTH-200 HEX

Tx DMA REQUEST
BUFFER

1 - - - EMPTY

BUS GRANTED

Figure 5. Transmit DMA State Diagram
Four interrupts are produced by the transmitter DMA
channel. Transmit DMA Complete indicates that the last byte
of data has been transferred from the buffer into the transmit
FIFO. FIFO Underrun indicates the DMA requests were not
serviced and the FI FO underran. Bus Error is generated when
the BERR pin is activated during a DMA cycle. Address Error
is generated when either lACK or CS are activated during a
DMA cycle.
Receive Channel Operation
Figure 8 is a simplified state diagram for operation of the
DMA controller when a receive channel requests service.

ABOO

B300

BUFFER
1

BUFFER
3

ADOO

B500

BUFFER
2

BUFFER
4

I

SYSTEM MEMORY

I

Figure 6. Alternate Receive Buffer Operation

MC145488
2-850

MOTOROLA COMMUNICATIONS DEVICE DATA

MICROPROCESSOR INTERFACE
The microprocessor block interfaces the internal 16-bit bus
to the host 8- or 16-bit bus. The block also performs all timing
conversion and buffering. This block has three modes of
operation described in this section: system slave, system
master, and interrupt generator.
System Slave Mode
When the DDLC is in this mode, it appears as fast memory
to the host processor. The host can read from or write to the
registers in the DDLC. This mode is entered when the CS pin
is activated. Internal address decoding circuitry is selected
and the desired register is connected to the intemal bus for
access by the host.
System Master (OMA) Mode
During DMA operation, the DDLC becomes a system
master and controls the system bus. When one of the internal
FIFOs requests a DMA transfer, the DDLC negotiates with
the system host for ownership of the bus. After successful
negotiation, one DMA request is serviced, and then the bus
is relinquished. The DDLC has the capability of reading or
writing data from or to memory. If the memory system is slow,
the DDLC inserts wait states (user selectable) until the
memory is ready to complete the access. The DDLC has the
capability of recovering from system faults such as address
or bus errors.
Interrupt Operation
The DDLC has 27 vectored interrupt sources to inform the
host of its status. One group of interrupts is normal operation
interrupts. These inform the host that a particular task was
completed and that new tasks are desired. Another group is
bit handler faults, which inform the host that a DDLC channel
detected a fault from which it cannot recover without
assistance from the host. A third group is the timer and SCP
interrupts. The last group of interrupts is the system faults.
These include DMA bus and address errors. The interrupts
are presented to the host as a vector number in an interrupt
acknowledge cycle. The interrupts are encoded into the low
four bits so the DDLC vector space consumes 16 out of 256
locations. Software can program the base vector number, so
the DDLC vectors can be located anywhere within the vector
table. For applications not using vectored interrupts, the
equivalent vector number is accessible in the Master Status
register.
SERIAL INTERFACE
The serial interface block has a variety of configurations that
make it compatible with most common interfaces. Each serial
interface is independent, so two different configurations may
be active simultaneously. The serial interface has an IDL
mode, a timeslot mode, and a general purpose modem mode.
The serial interface supports long frame and short frame
timing. It also supports subrate multiplexing. The serial mode
is selected by programming the appropriate bits in the Serial
Interface Control register.
A full set of serial interface control and handshake pins are
provi~ed. The name and functionality change to reflect the
serial mode of operation. Separate receive and transmit clock
inputs are provided for all modes except IDL and timeslot
modes.

MOTOROLA COMMUNICATIONS DEVICE DATA

The serial interface also supports transfer of transparent
data. Depending on which type of serial interface is used, an
external synchronization signal must be provided to maintain
byte alignment. In IDL mode, the byte synchronization is
programmed by the microprocessor.
SERIAL CONTROL PORT
A Serial Control Port, similar to the Serial Peripheral
Interface (SPI) on Motorola single-chip microprocessors, is
provided to communicate with external devices via a serial
link. The SCP functions are multiplexed onto other serial pins
so when the SCP is enabled, certain modem control features
are lost. Please refer to the MC145488/D Data Book for
complete details.
TIMERS
Two timers are provided for general purpose low-resolution
protocol uses. The clock to the timer is derived from the
Master MPU Clock (MCLK). The baud rate generator in the
SCP block is used to drive the timer divide chain. This clock is
then divided by 1024 and applied to an eight-bit
down-counter. The counter is readable and writable by the
host and may be set to any value. The counter counts down
toward zero from the current value. A non-maskable interrupt
is generated when the counter underflows from FF to FE. The
timers continue counting down after reaching FE. The status
bit from the previous interrupt must be cleared before a new
interrupt is generated. The timer function and interrupt are
enabled by setting the TImer Enable bit in the TImer register
to one. The timer interrupt status bits must be read while set
before they can be cleared. The timers are intended for low
accuracy uses such as protocol timers. Figure 7 describes
the clock selection choices for the timers.
Watchdog Timer
TImerO may be configured as a watchdog timerforthe entire
host system. When the Watchdog Enable bit is set, an extra
divide by 16 is added to the clock input of the counter. When
the counter underflows from FF to FE, the Reset pin becomes
an output for 16 MCLK cycles and a logic low is output. This
provides a system reset to the host. The host can write any
value (except FE hex) to the TImer register to setup any
timeout. TIme-outs of up to 5.6 seconds are available with a
12 MHz MCLK.
POWER CONSUMPTION
The DDLC is designed utilizing high-performance CMOS
technology. As as result, average power consumption is very
low. However, because there are wide address and data
buses, peak currents may exceed 150 mA for short periods
of time (less than 20 ns) while the drivers are charging or
discharging the buses.

REGISTER SET
The DDLC has many user accessible registers. These
registers control the blocks or indicate status. Other registers,
used by the DMA section, are used as buffer descriptors and
counters. For a more detailed description, please refer to the
DDLC data book. The address for each register is the
hexadecimal offset from the base address of the chip select.
The registers may be accessed as 8-bit registers or 16-bit
registers. Table 1 is a map of the registers and their principal
function.

MC145488
2-851

00

02
04
06

10
12
14
20
22

24
26
28

2A

2C
2E

30
32
34

36
38
3A
3C

3E
40
42
44

46
48
4A
4C
4E
50
52

54
56

58
5A
5C
5E

Table 1. Register Memory Map

MC145488
2-852

MOTOROLA COMMUNICATIONS DEVICE DATA

RESET
BYTE
COUNT

ERR1REOF

POLL
REQUESTS

RxDMA
REQUEST

NORMAL
EOF

PREPARE
DATA

I

NokoF
NO
BUFFER
AVAILABLE

PREPARE
ALTERNATE
BUFFER

•

BUFFER
FULL

CLOSE
BUFFER

PREPARE
ADDRESS
BUFFER
AVAILABLE

BUFFER NOT
FULL

t
REQUEST
BUS

----,
t---

NO
BG

BUSG~ANTED
~
NORMAL _
TERMINATION

BUS
CYCLE

~O

I - - DTACK

BUSiRROR

DISABLE
CHANNEL

Figure 7. Receive DMA State Diagram

TIMER 0

MCLK

+1024

UP·TIMER MODE
DOWN·WATCHDOG MODE

PRESCALE SELECT

TIMER 1

Figure 8. Timer Clock Selection

MOTOROLA COMMUNICATIONS DEVICE DATA

MC145488
2-853

MOTOROLA

-

SEMICONDUCTOR
TECHNICAL DATA

MC145500
MC145501
MC145502
MC145503
MC145505

Advance Information

PCM Codec-Filter
Mono-Circuit
The MC145500, MC145501, MC145502, MC145503, and MC145505 are all
per channel PCM codec-filter mono-circuits. These devices perform the voice
digitization and reconstruction as well as the band limiting and smoothing
required for PCM systems. The MC145500 and MC145503 are general purpose
devices that are offered in a 16-pin package. They are designed to operate in
both synchronous and asynchronous applications and contain an on chip
precision reference voltage. The MC145501 is offered in an 18-pin package and
adds the capability of selecting from three peak overload voltages (2.5, 3.15, and
3.78 V). The MC145505 is a synchronous device offered in a 16-pin DIP and
wide body SOIC package intended for instrument use. The MC145502 is the
full-featured device which presents all of the options of the chip. This device is
packaged in a 22-pin DIP and a 28-pin chip carrier package and contains all the
features of the MC145500 and MC145501 plus several more. Most of these
features can be made available in a lower pin count package tailored to a specific
user's application. Contact the factory for further details.
These devices are pin-for-pin replacements for Motorola's first generation of
MC14400/01/02l03/05 PCM mono-circuits and upwardly compatible with the
MCl4404/06/07 codecs and other industry standard codecs. They also maintain
compatibility with Motorola's family of MC33120 and MC3419 SLiC products.
The MC145500 family of PCM codec-filter mono-circuits utilizes CMOS due
to its reliable low-power performance and proven capability for complex analogi
digital VLSI functions.
MC145500
•
•
•
•
•
•

16-Pin Package
Transmit Bandpass and Receive Low-Pass Filter on Chip
Pin Selectable MulA Law Companding with Corresponding Data Format
On Chip Precision Reference Voltage (3.15 V)
Power Dissipation of 50 mW, Power Down of 0.1 mW at ± 5 V
Automatic Prescaler Accepts 128 kHz, 1.536, 1.544, 2.048, and 2.56 MHz for
Internal Sequencing

MC145501 - All of the Above Plus:
• 18-Pin Package
• Selectable Peak Overload Voltages (2.5, 3.15, 3.78 V)
• Access to the Inverting Input of the Txllnput Operational Amplifier

J.
J.,

16

1

LSUFFIX
CERAMIC
CASE 620
MC145500/03/05

18

22

1

PSUFFIX
PLASTIC
CASE 648
MC145503/05

LSUFFIX
CERAMIC
CASE 726
MC145501

LSUFFIX
CERAMIC
CASE 736
MC145502

PSUFFIX
PLASTIC
CASE 708
MC145502

MC145502 - All of the Above Plus:
•
•
•
•

16.

22-Pin and 28-Pin Packages
Variable Data Clock Rates (64 kHz to 4.1 MHz)
Complete Access to the Three Terminal Transmit Input Operational Amplifier
An External Precision Reference May Be Used

MC145503 - All of the Above Features of the MC145500 Plus:
• 16-Pin Package
• Complete Access to the Three Terminal Transmit Input Operational Amplifier
MC145505 -

OW SUFFIX
SO
CASE 751G
MC145503/05

FN SUFFIX
PLCC
CASE 776
MC145502

Same as MC145503 Except:

• 16-Pin Package
• Common 64 kHz to 4.1 MHz Transmit/Receive Data Clock

This document contains information on a new product. Specifications and information herein are subject to change without notice.

MC145500.MC145501.MC145502.MC145503.MC145505
2-854

MOTOROLA COMMUNICATIONS DEVICE DATA

MC145500/01/02l03/05 PCM CODEC/FILTER MONO-CIRCUIT BLOCK DIAGRAM

r - - - " \ + - - - - E 3 RDD
RxOD.......--<

1 + - - - E 3 RCE
RDC

1+----8

CCI

MSI

Vref c : - - - - - - - - - - - - - - - - - - - I H
RSIc:-----------------~H

Txl

'-----'

-Tx D---1

TDD

+Tx D - - - I

TDE
TDC

NOTES: ~ Controlled by VLS
Rx ~ 100 kQ (internal resistors)

PIN ASSIGNMENTS
(Drawings Do Not Reflect Relative Size)
MC145500L
VAG

MC145505L, P

MC145503L, P
VDD

VAG

VDD

RDD

RxO

RDD

VAG

MC145501L
VDD

RSI

VDD

RDD

VAG

RDD

RCE

RxO

RCE

RxO

RCE

Txl

RDC

Txl

RDC

DCLK

RDC

TOC

-Tx

TDC

CCI

TOC

TDD

TOD

PDI

TDE

PDI

TDD

VSS

TDE

VLS

MSI

RCE

+ Tx

VSS

MC145502L, P

MC145503DW

10

TOE

9

VLS

Vref

RSI

VAG

VDD

16

VDD

VDD

RxO

RDD

RxO [ 2

15

RDD

RxO

RDD

+ Tx

RCE

+ Tx [ 3

14

RCE

RxG

RCE

Txl

RDC

Txl [ 4

13

DCLK

RxO

RDC

TOC

-Tx [ 5

12

CCI

+ Tx

TOC

MulA

TOD

MulA [ 6

11

TOD

PDI

TOE

PDf [ 7

10

TDE

VSS [ 8

9

VLS

CCI
TDD

MulA

TOE

PDI

MSI

VSS

VLS

MOTOROLA COMMUNICATIONS DEVICE DATA

VLS

MC145502FN

VAG

Txl

MSI

VSS

MC145505DW
VAG [ 1-

- Tx

TOE
PDI

~~~~~$~
RxG
RxO
+ Tx
NC
NC
Txl
-Tx

3 2 1282726
25
24
23
28-PIN PQLCC 22
(TOP VIEW)
21
20
10
11
19
12 13 1415 16 1718

RCE
RDC
TDC
NC
NC
CCI
TOD

NC; NO CONNECTION

MC145500.MC145501.MC145502.MC145503.MC145505
2-855

This device contains circuitry to protect against damage due to high static
voltages or electric fields; however, it is
advised that normal precautions be taken to avoid application of any voltage
higher than maximum rated voltages to
this high impedance circuit. For proper
operation it is recommended that Vin
and Vout be constrained to the range
VSSS (Vin or Voutl S VDD.
Unused inputs must always be tied to
an appropriate logic voltage level (e.g.,
VSS, VDD, VLS, or VAG)·

ABSOLUTE MAXIMUM RATINGS (Voltage Referenced to VSS)
Rating

Symbol

DC Supply Voltage
Voltage, Any Pin to VSS
DC Drain Per Pin (Excluding VDD, VSS)

Value

Unit

VDD-VSS

-0.510 13

V

V

- 0.5 to VDD + 0.5

V

I

10

mA

Operating Temperature Range

TA

-40to+85

°C

Storage Temperature Range

Tstg

-85to+150

°C

RECOMMENDED OPERATING CONDITIONS (TA = - 40 10 + 85°C)
Characteristic
DC Supply Voltage
Dual Supplies: VDD = - VSS, (VAG = VLS = 0 V)
Single Supply: VDD to VSS (VAG is an Output, VLS = VDD or VSS)
MC145500, MC145501, MC145502, MC145503, MC145505 (Using Intemal
3.15 V Reference)
MC145501, MC145502 Using Intemal2.5 V Reference
MC145501, MC145502 Using Internal 3.78 V Reference
MC145502 Using External 1.5 V Reference, Referenced to VAG

Min

Typ

Max

4.75

5.0

6.3

Unit
V

8.5
7.0
9.5
4.75

-

12.6
12.6
12.6
12.6
mW

Power Dissipation
CMOS Logic Mode (VDD to VSS = 10 V, VLS = VDD)
TIL Logic Mode (VDD = + 5 V, VSS = - 5 V, VLS = VAG = 0 V)

-

40
50

Power Down Dissipation

-

0.1

1.0

mW

Frame Rate Transmit and Receive

7.5

8.0

8.5

kHz

-

128
1536
1544
2048
2560

-

64

-

4096

-

3.15
3.78
3.15
2.5
1.51 x Vref
1.26x Vref
Vref

-

Symbol

Min

Max

-

0.3xVDD

Data Rate
MCI45500, MC145501, MCI45503
Must Use One of These Frequencies, Relative to MSI Frequency of 8 kHz

Data Rate for MC145502, MC145505
Full Scale Analog Input and Output Level
MC145500, MC145503, MCI45505
MC145501, MC145502 (Vref= VSS)

MC145502 Using an Extemal Reference Voltage Applied at Vref Pin

RSI=VDD
RSI=VSS
RSI=VAG
RSI=VDD
RSI=VSS
RSI=VAG

70
90

kHz

kHz
Vp

DIGITAL LEVELS (VSS to VDD =4.75 Vto 12.6 V, TA =-40 10 + 85°C)
Characteristic
Input Voltage Levels (TDE, TDC, RCE, RDC, RDD, DC, MSI, CCI, PDf)
CMOS Mode (VLS;' VDD, VSS Is Digital Ground)

"0"

"1"
TIL Mode (VLS S VDD - 4.0 V, VLS is Digital Ground)

"0"
"1"

Output Current for TDD (Transmit Digital Data)
CMOS Mode (VLS = VDD, VSS = 0 V and is Digital Ground)
(VDD = 5 V, Vout = 0.4 V)
(VDD = 10 V, Vout = 0.5 V)
(VDD '= 5 V, Vout = 4.5 V)
(VDD = 10 V, Vout = 9.5 V)
TTL Mode (VLS S VDD - 4.75 V, VLS = 0 V and is Digital Ground) (VOL = 0.4V)
(VOH=2.4V)

MC145500.MC145501.MC145502.MC145503.MC145505
2-856

VIL
VIH
VIL
VIH

0.7xVDD

VLS+2.0V

Unit
V

-

VLS+ 0.8 V

mA

IOL
IOH
IOL
IOH

1.0
3.0
-1.0
-3.0
1.6
-0.2

-

-

MOTOROLA COMMUNICATIONS DEVICE DATA

ANALOG TRANSMISSION PERFORMANCE
(VDD = + 5 V ± 5%, VSS =-5 V ±5%, VLS = VAG =0 V, Vref = RSI =VSS (Internal 3.15 V Reference), 0 dBmO = 1.546 Vrms
600 n, TA =- 40 to + B5°C, TDC = RDC = CC = 2.04B MHzl, TDE = RCE = MSI = B kHz, Unless Otherwise Noted)

AID

End-to-End
Characteristic

Min

Max

Min

Max

Unit

-0.30

+ 0.30

-0.30

+0.30

dB

-

±0.03

-

±0.03

dB

-

±0.1

±0.1

dB

±0.02

-

±0.02

dB

+0.4
+ O.B
+ 1.6

-0.2
-0.4
-O.B

+0.2
+0.4
+O.B

-0.2
-0.4
-O.B

+0.2
+0.4
+ O.B

dB

-

-0.25
-0.30
-0.45

+ 0.25
+0.30
+ 0.45

-0.25
-0.30
-0.45

+0.25
+0.30
+ 0.45

Absolute Gain Variation with Temperature 0 to + 70°C

-

Absolute Gain Variation with Temperature - 40 to +B5'C

-

-

Absolute Gain Variation with Power Supply (VDD

=-5 V)

=5 V, VSS =-5 V, 5%)

Gain vs Level Tone (Relative to - 10 dBmO, 1.02 kHz)

+ 3 to-40 dBmO
-40 to-50 dBmO
- 50 to-55 dBmO

Gain vs Level Pseudo Noise (A-Law Relative to - 10 dBmO)
CCITIG.714
-10 to -40 dBmO
-40 to -50 dBmO
- 50 to - 55 dBmO
Total Distortion - 1.02 kHz Tone (C-Message)

Total Distortion With Pseudo Noise (A-Law)
CCITIG.714

o to-30 dBmO
-40dBmO
-45dBmO
-3dBmO
- 6 to-27 dBmO
-34dBmO
-40dBmO
-55dBmO

Idle Channel Noise (For End-End and AID, See Note 1)
Mu-Law, C-Message Weighted
A-Law, Psophometric Weighted
Frequency Response (Relative to 1.02 kHz @ 0 dBmO)

15t060Hz
300 to 3000 Hz
3400 Hz
4000 Hz
;,4600 Hz

Inband Spurious (1.02 kHz @ 0 dBmO, Transmit and RxO)

-

-0.4
-O.B
-1.6

-

-

-

-

-

35
29
24

-

27.5
35
33.1
2B.2
13.2

-

-

36
30
25

-

dBC

28
35.5
33.5
2B.5
13.5

-

28.5
36
34.2
30.0
15.0

-

dB

-

15
-69

-

-23
+0.15
0
-14
-32

-

-

-43

-30
-40
-30

-

-

-

15
-69

-

-23
+ 0.3
0
-2B
-60

-

-

dB

36
29
24

-

-0.3
-1.6

D/A

Min

Max

-

Absolute Gain (0 dBmO @ 1.02 kHz, TA = 25°C, VDD = 5 V, VSS

=+ 6 dBm @

-

-0.15
-O.B

-

-

-

-

-

9
-7B

dBrnCO
dB mOp

-

dB

-

0.15
+0.15
0
-14
-30

-

-43

dBmO

-

-30
-40
-30

-0.15
-O.B

300 to 3000 Hz
Out-of-Band Spurious at RxO (300 - 3400 Hz @ 0 dBmO In)
4600 to 7600 Hz
7600 to B400 Hz
B400 to 100,000 Hz
Idle Channel Noise Selective @ B kHz, Input =VAG, 30 Hz Bandwidth
Absolute Delay @ 1600 Hz (TDC = 2.04B MHz, TDE = 8 kHz)
Group Delay Referenced to 1600 Hz (TDC
TDE = B kHz)

dB

-

-

-

-

-

-

-

310

-

-

-40
-40
-30
-20

-

200
140
70
40
75
110
170

-

90
120
160

-

-75

-

-BO

dB

-41

dB

-70

-70

dBmO

1BO

I's

=2048 kHz,

I's
500 to 600 Hz
600 to 800 Hz
BOO to 1000 Hz
1000 to 1600 Hz
1600 to 2600 Hz
2600 to 2800 Hz
2BOO to 3000 Hz

-

-

-

-

-

Crosstalk of 1020 Hz @ 0 dBmO From AID or D/A (Note 2)

-

-

Intermodulation Distortion of Two Frequencies of Amplitudes - 4 to
- 21 dBmO from the Range 300 to 3400 Hz

-

-

-

-41

-

-

NOTES:
1. Extrapolated from a 1020 Hz @ - 50 dBmO distortion measurement to correct for encoder enhancement.
2. Selectively measured while the AID is stimulated with 2667 Hz @ - 50 dBmO.

MOTOROLA COMMUNICATIONS DEVICE DATA

MC145500.MC145501.MC145502.MC145503.MC145505
2-857

ANALOG ELECTRICAL CHARACTERISTICS (VOO=-VSS=5 Vt06V± 5%, TA=-40to+B5'C)
Characteristic
Input Current

Typ

Max

lin

-

±0.01

±0.2

Zin

5
0.1

10
0.2

-

-

-

10

pF

-

<± 30

-

mV

VSS+l.0

-

VOO-2.0

V

70

-

dB

-

kHz

Symbol
+Tx, - Tx (Txl for MC145500)
+Tx,-Tx
Txl for MC145500

AC Input Impedance to VAG (1 kHz)
Input Capacitance

+Tx,-Tx

Input Offset Voltage of Txl Op Amp
Input Common Mode Voltage Range

+Tx,-Tx

VICR

Input Common Mode Rejection Ratio

+Tx,-Tx

CMRR

Min

-

Unit

I1A
MO

BWp

-

1000

AVOL

-

75

Equivalent Input Noise (C-Message) Between +Tx and - Tx, at Txl

-

-20

-

dBmCO

Output Load Capacitance for Txl Op Amp

0

-

100

pF

VSS+O.B
VSS + 1.5

-

VOO-l.0
VOO-l.5

±5.5

-

Txl Unity Gain Bandwidth

RL2:10ka

Txl Open Loop Gain

RL2:10kO

Output Voltage Range Txl Op Amp, RxO or RxO
RL = 10 ka to VAG
RL= 600 OtoVAG

Vout

Output Current Txl, RxO, RxO

VSS + 1.5 V S VoutS VOO-l.5 V

Output Impedance RxO, RxO'

Oto 3.4 kHz

Zout

-

3

dB

V

-

rnA

-

0

200

pF

±100
±150

mV
kO

-

-

Internal Gainsetting Resistors for RxG to RxO and RxO

62

100

225

External Reference Voltage Applied to Vref (Referenced to VAG)

0.5

-

VOO-l.0

V

Vref Input Current

-

-

20

I1A

VAG Output Bias Voltage

-

-

V

O.B

rnA

±30

I1A

Output Load Capacitance for RxO and RxO'

0

Output dc Offset Voltage Referenced to VAG Pin

RxO
RxO'

VAG Output Current

Source
Sink

Output Leakage Current Ouring Power Oown for the Txl Op Amp, VAG,
RxO, and RxO

IVAG

0.53VOO+
0.47VSS

-

-

0.4
10.0

Positive Power Supply Rejection Ratio,
0-100 kHz @ 250 mV, C-Message Weighting

Transmit
Receive

45
55

50
65

Negative Power Supply Rejection Ratio,
0-100 kHz @ 250 mV, C-Message Weighting

Transmit
Receive

50
50

55
60

• Assumes that RxG

IS

-

-

dBC
dBC

not connected for gain modifications to RxO.

MC145500.MC145501.MC145502.MC145503.MC145505
2·858

MOTOROLA COMMUNICATIONS DEVICE DATA

MODE CONTROL LOGIC (VSS to VDD = 4.75 V to 12.6 V, TA = - 40 to + 85°C)
Characteristic

Min

VLS Voltage for TTL Mode (TTL Logic Levels Referenced to VLS)

VSS

VLS Voltage for CMOS Mode (CMOS Logic Levels of VSS to VDD)

VDD-0.5

MulA Select Voltage
Mu·LawMode
Sign Magnitude Mode
A·Law Mode

VDD-0.5
VAG-0.5
VSS

Typ

Max

Unit

-

VDD-4.0

V

VDD

V

-

VDD
VAG +0.5
VSS + 0.5

V

RSI Voltage for Reference Select Input (MC145501 and MC145502)

3.78 V Mode
2.5 V Mode
3.15 V Mode

VDD-0.5
VAG-0.5
VSS

Vref Voltage for Internal or External Reference (MC145502 Only)
Internal Reference Mode
External Reference Mode

VSS
VAG + 0.5

Analog Test Mode Frequency, MS = CCI (MC145500, MC145501, MC145502 Only)
See Pin Description; Test Modes

-

-

VDD
VAG +0.5
VSS + 0.5

V

V

-

-

128

VSS + 0.5
VDD -1.0

-

kHz

SWITCHING CHARACTERISTICS (VSS to VDD = 9.5 V to 12.6 V, TA = - 40 to + 85°C, CL = 150 pF, CMOS or TTL Mode)
Characteristic

Symbol

Output Rise Time
Output Fall Time
Input Rise Time
Input Fall Time
Pulse Width

TDD

trLH
trHL

TDE, TDC, RCE, RDC, DC, MSI, CCI

trLH
trHL

TDE Low, TDC, RCE, RDC, DC, MSI, CCI

DCLK Pulse Frequency (MC145502105 ONLY)

TDC, RDC, DC

CCI Clock Pulse Frequency (MSI = 8 kHz)
CCI is internally tied to TDC on the MC145500101/03, therefore, the
transmit data clock must be one of these frequencies. This pin will ac·
cept one of these discrete clock frequencies and will
compensate to produce internal sequencing.
Propagation Delay Time
TDE Rising to TDD Low Impedance
TDE Falling to TDD High Impedance
TDC Rising Edge to TDD Data, During TDE High
TDE Rising Edge to TDD Data, During TDC High

Min

-

-

Typ

Max

Unit

30
30

80
80

ns

-

4
4

I's

-

tw

100

-

fCL

64

-

fCL1
fCL2
fCL3
fCL4
fCL5

-

128
1536
1544
2048
2560

tp1

-

90
90

4096

-

ns
kHz
kHz

ns
TTL
CMOS
TTL
CMOS
TTL
CMOS
TTL
CMOS

tp2
tp3
tp4

-

-

90
90
90
90

180
150
55
40
180
150
180
150

-

-

TDC Falling Edge to TDE Rising Edge Setup Time

tsu1

20

-

-

ns

TDE Rising Edge to TDC Falling Edge Setup Time

tsu2

100

-

ns

TDE Falling Edge to TDC Rising Edge to Preserve the Next TDD Data

tsu8

20

-

-

-

ns

-

ns

tsu3

20

RCE Rising Edge to RDC Falling Edge Setup Time

tsu4

100

-

RDD Valid to RDC Falling Edge Setup Time

tsu5

60

-

CCI Falling Edge to MSI Rising Edge Setup Time

tsu6

20

MSI Rising Edge to CCI Falling Edge Setup Time

tsu7

100

th

100

-

TDE, TDC, RCE, RDC, RDD, DC, MSI, CCllnput Capacitance

-

TDE,TDC, RCE, RDC, RDD, DC, MSI, CCI Input Current
TDD CapaCitance During High Impedance (TDE Low)

RDC Falling Edge to RCE Rising Edge Setup Time

RDD Hold Time from RDC Falling Edge

TDD Input Current During High Impedance (TDE Low)

MOTOROLA COMMUNICATIONS DEVICE DATA

ns

ns
ns
ns

-

ns

-

10

pF

-

±0.01

±10

I1A

-

12

15

pF

±0.1

± 10.0

I1A

MC145500·MC145501.MC145502.MC145503.MC145505

2-859

DEVICE DESCRIPTIONS
A codec-filter is a device which is used for digitizing and
reconstructing the human voice. These devices were
developed primarily for the telephone network to facilitate
voice switching and transmission. Once the voice is digitized,
it may be switched by digital switching methods or transmitted
long distance (Tl, microwave, satellites, etc.) without
degradation. The name codec is an acronym from "Coder"
for the AID used to digitize voice, and "Decoder" for the D/A
used for reconstructing voice. A codec is a single device that
does both the AID and D/A conversions.
To digitize intelligible voice requires a signal to distortion
of about 30 dB for a dynamic range of about 40 dB. This may
be accomplished with a linear 13-bit AID and D/A, but will far
exceed the required signal to distortion at amplitudes greater
than 40 dB below the peak amplitude. This excess
performance is at the expense of data per sample. Two
methods of data reduction are implemented by compressing
the 13-bit linear scheme to companded 8-bit schemes. These
companding schemes follow a segmented or "piecewise-linear" curve formatted as sign bit, thre.e chord bits, and four step
bits. For a given chord, all 16 of the steps have the same
voltage weighting. As the voltage of the analog input
increases, the four step bits increment and carry to the three
chord bits which increment. With the chord bits incremented,
the step bits double their voltage weighting. This results in an
effective resolution of 6-bits (sign + chord + four step bits)
across a 42 dB dynamic range (7 chords above zero, by 6
dB per chord). There are two companding schemes used;
Mu-255 Law specifically in North America, and A-Law
specifically in Europe. These companding schemes are
accepted world wide. The tables show the linear quantization
levels to PCM words for the two companding schemes.
In a sampling environment, Nyquist theory says that to
properly sample a continuous signal, it must be sampled at
a frequency higher than twice the signal's highest frequency
component. Voice contains spectral energy above 3 kHz, but
its absence is not detrimental to intelligibility. To reduce the
digital data rate, which is proportional to the sampling rate,
a sample rate of 8 kHz was adopted, consistent with a
bandwidth of 3 kHz. This sampling requires a low-pass filter
to limit the high frequency energy above 3 kHz from distorting
the inband signal. The telephone line is also subject to 50/60
Hz power line coupling which must be attenuated from the
signal by a high-pass filter before the AID converter.
The D/A process reconstructs a staircase version of the
desired inband signal which has spectral images of the inband
signal modulated about the sample frequency and its
harmonics. These spectral images are called aliasing
components which need to be attenuated to obtain the desired
signal. The low-pass filter used to attenuate filter aliasing
components is typically called a reconstruction or smoothing
filter.
The MC145500 series PCM codec-filters have the codec,
both presampling and reconstruction filters, a precision
voltage reference on chip, and require no external components. There are five distinct versions of the Motorola
MC145500 Series.
MC145500
The MC145500 PCM codec-filter is intended for standard
byte interleaved synchronous and asynchronous applications. The TDC pin on this device is the input to both the TDC
and CCI functions in the pin description. Consequently, for
MSI = 8 kHz, TDC can be one of five discrete frequencies.

MC145500.MC145501.MC145502.MC145503.MC145505
2-860

These are 128 kHz (40 to 60% duty cycle) 1.536, 1.544, 2.048,
or 2.56 MHz. (For other data clock frequencies see MC145502
or MC145505.) The internal reference is set for 3.15 V peak
full scale, and the full scale input level at Txl and output level
at RxO is 6.3 V peak-to-peak. This is the + 3 dBmO level of
the PCM codec-filter. All other functions are described in the
pin description.
MC145501
The MC145501 PCM codec-filter offers the same features
and is for the same application as the MC145500, but offers
two additional pins and features. The reference select input
allows the full scale level of the device to be set at 2.5 Vp,
3.15 Vp, or 3.78 Vp. The -Tx pin allows for external transmit
gain adjust and simplifies the interface to the MC3419 SLiC.
Otherwise, it is identical to MC145500.
MC145502
The MC145502 PCM codec-filter is the full feature 22-pin
device. It is intended for use in applications requiring maximum
flexibility. The MC145502 contains all the features of the
MC145500 and MC145501. The MC145502 is intended for
bit interleaved or byte interleaved applications with data clock
frequencies which are nonstandard or time varying. One of
the five standard frequencies (listed above) is applied to the
CCI input, and the data clock inputs can be any frequency
between 64 kHz and 4.096 MHz. The Vref pin allows for use
of an external shared reference or selection of the internal
reference. The RxG pin accommodates gain adjustments for
the inverted analog output. All three pins of the input
gain-selting operational amplifier are present, providing
maximum flexibility for the analog interface.
MC145503
The MC145503 PCM codec-filter is intended for standard
byte interleaved synchronous or asynchronous applications.
TDC can be one of five discrete frequencies. These are 128
kHz (40 to 60% duty cycle), 1.536, 1.544,2.048, or 2.56 MHz.
(For other data clock frequencies see MC145502 or
MC145505.) The internal reference is set for 3.15 V peak full
scale, and the full scale input level at Txl and output level at
RxO is 6.3 V peak-to-peak. This is the + 3 dBmO level of the
PCM codec-filter. The +Tx and - Tx inputs provide maximum
flexibility for analog interface. All other functions are described
in the pin description.
MC145505
The MC145505 PCM codec-filter is intended for byte
interleaved synchronous applications. The MC145505 has all
the features of the MC145503 but internally connects TDC
and ROC (see pin description) to the DC pin. One of the five
standard frequencies (listed above) should be applied to CCI.
The data clock input (DC) can be any frequency between 64
kHz and 4.096 MHz.

PIN DESCRIPTIONS
DIGITAL
VLS
Logic Level Select input and TTL Digital Ground
VLS controls the logic levels and digital ground reference
for all digital inputs and the digital output. These devices can
operate with logic levels from full supply (VSS to VDD) or
with TTL logic levels using VLS as digital ground. For VLS =
VDD,aIlI/Oisfulisupply(VsStoVDDswing)withCMOSswitch
points. For VSS < VLS < (VDD - 4 V), all inputs and
outputs are TTL compatible with VLS being the digital ground.

MOTOROLA COMMUNICATIONS DEVICE DATA

The pins controlled by VLS are inputs MSI, CCI, TDE, TDC,
RCE, RDC, RDD, PDI, and output TDD.

edge of the next frame. MSI must be available separate from
TDE for bit interleaved applications.

MSI
Master Synchronization Input
MSI is used for determining the sample rate of the transmit
side and as a time base for selecting the internal prescale
dividerforthe convert clock input (CCI) pin. The MSI pin should
be tied to an 8 kHz clock which may be a frame sync or system
sync signal. MSI has no relation to transmit or receive data
timing, except for determining the internal transmit strobe as
described under the TDE pin description. MSI should be
derived from the transmit timing in asynchronous applications.
In many applications MSI can be tied to TDE. (MSI is tied
internally to TDE in MC145503/05.)

TOO
Transmit Digital Data Output
The output levels at this pin are controlled by the VLS
pin. For VLS connected to VDD, the output levels are from
VSS to VDD. For a voltage of VLS between VDD - 4 V and
VSS, the output levels are TTL compatible with VLS being
the digital ground supply. The TDD pin is a three-state output
controlled by the TDE pin. The timing of this pin is controlled
byTDCandTDE. When inTTLmode, this output maybe made
high-speed CMOS compatible using a pull-up resistor. The
data format (Mu-Law, A-Law, or sign magnitude) is controlled
by the MulA pin.
ROC
Receive Data Clock Input
RDC can be any frequency from 64 kHz to 4.096 MHz. This
pin is often tied to the TDC pin for applications that can use
a common clock for both transmit and receive data transfers.
The receive shift register is controlled by the receive clock
enable (RCE) pin to clock data into the receive digital data
(RDD) pin on falling RDC edges. These three signals can be
asynchronous with all other digital pins. The RDC input is
internally tied to the TDC input on the MC145505 and called
DC.
RCE
Receive Clock Enable Input
The rising edge of RCE should identify the sign bit of a
receive PCM word on RDD. The next falling edge of RDC,
after a rising RCE, loads the first bit of the PCM word into the
receive register. The next seven falling edges enter the remainder olthe PCM word. On the ninth rising edge, the receive
PCM word is transferred to the receive buffer register and the
AID sequence is interrupted to commence the decode process. In asynchronous applications with an 8 kHz transmit
sample rate, the receive sample rate should be between 7.5
and 8.5 kHz. Two receive PCM words may be decoded and
analog summed each transmit frame to allow on chip conferencing. The two PCM words should be clocked in as two single
PCM words, a minimum of 31.251ls apart, with a receive data
clock of 512 kHz or faster.

CCI
Convert Clock Input
CCI is designed to accept five discrete clock frequencies.
These are 128 kHz, 1.536 MHz, 1.544 MHz, 2.048 MHz, or
2.56 MHz. The frequency at this input is compared with MSI
and prescale divided to produce the internal sequencing clock
at 128 kHz (or 16 times the sampling rate). The duty cycle
of CCI is dictated by the minimum pulse width except for
128 kHz, which is used directly for internal sequencing and
must have a 40 to 60% duty cycle. In asynchronous
applications, CCI should be derived from transmit timing. (CCI
is tied internally to TDC in MC145500101/03.)
TDC
Transmit Data Clock Input
TDC can be any frequency from 64 kHz to 4.096 MHz, and
is often tied to CCI if the data rate is equal to one of the five
discrete frequencies. This clock is the shift clock for the
transmit shift register and its rising edges produce successive
data bits at TDD. TDE should be derived from this clock. (TDC
and RDC are tied together internally in the MC145505 and
are called DC.) CCI is internally tied to TDCon the MC1455001
01/03. Therefore, TDC must satisfy CCltiming requirements
also.

TOE
Transmit Data Enable Input
TDE serves three major functions. The firstTDE rising edge
following an MSI rising edge generates the internal transmit
strobe which initiates an AID conversion. The internal transmit
strobe also transfers a new PCM data word into the transmit
shift register (sign bit first) ready to be output at TDD. The
TOE pin is the high impedance control for the transmit digital
data (TDD) output. As long as this pin is high, the TDD output
stays low impedance. This pin also enables the output shift
register for clocking out the 8-bit serial PCM word. The logical
AND of the TDE pin with the TDC pin clocks out a new data
bitatTDD. TDE should be held high for eight consecutive TDC
cycles to clock out a complete PCM word for byte interleaved
applications. The transmit shift register feeds back on itself
to allow multiple reads of the transmit data. If the PCM word
is clocked out once per frame in a byte interleaved system,
the MSI pin function is transparent and may be connected to

TOE.
The TDE pin may be cycled during a PCM word for bit
interleaved applications. TDE controls both the high impedance state of the TDD output and the internal shift clock. TDE
must fall before TDC rises (tsu8) to ensure integrity of the next
data bit. There must be at least two TDC falling edges between
the last TDE rising edge of one frame and the first TDE rising

MOTOROLA COMMUNICATIONS DEVICE DATA

ROD
Receive Digital Data Input
RDD is the receive digital data input. The timing for this pin
is controlled by RDC and RCE. The data format is determined
by the MulA pin.
MulA
Select
This pin selects the companding law and the data format
at TDD and RDD.
MulA = VDD; Mu255 Companding D3 Data Format with
Zero Code Suppress
MulA = VAG; Mu255 Companding with Sign Magnitude
Data Format
MulA VSS; A-law Companding with CCITT Data Format
Bit Inversions

=

CODE

+ FULL SCALE
+ ZERO
-ZERO
-FULL SCALE

SIGN!
MAGNITUDE

Mu-LAW

1111 1111
1000 0000
0000 0000
0111 1111

1000 0000
1111 1111
0111 1111
0000 0010

A·LAW
(CCITT)

1010
1101
0101
0010

1010
0101
0101
1010

MC145500.MC145501.MC145502.MC145503.MC145505
2-861

SIGN·
BIT

CHORD BITS

STEP BITS

NOTE: Starting from sign magnitude. to change format:
To Mu-LawMSB is unchanged (sign)
Invert remaining seven bits
If code is 0000 0000. change to 0000 0010 (for zero
code suppression)
ToA-LawMSB is unchanged (sign)
Invert odd numbered bits
Ignore zero code suppression

POl
Power Down Input
The power down input disables the bias circuitry and gates
off all clock inputs. This puts the VAG. Txl. RxO. RxO. and TOO
outputs into a high-impedance state. The power dissipation
is reduced to 0.1 mW when POI is a low logic level. The circuit
operates normally with POI
VDD or with a logic high as
defined by connection at VLS. TOO will not come out of high
impedance for two MSI cycles after POI goes high.

=

DCLK
Data Clock Input
In the MC145505. TDC and ROC are internally connected
to DCLK.
ANALOG
VAG
Analog Ground inputlOutput Pin
VAG is the analog ground power supply inputloutput. All
analog signals into and out of the device use this as their
ground reference. Each version of the MC145500 PCM
codec-filter family can provide its own analog ground supply
internally. The dc voltage of this internal supply is 6% positive
of the midway between VDD and VSS. This supply can sink
more than 8 mA but has a current source limited to 400 jJA.
The output of this supply Is internally connected to the analog
ground input of the part. The node where this supply and the
analog ground are connected is brought out to the VAG pin.
In symmetric dual supply systems (±5. ±S. etc.). VAG may be
externally tied to the system analog ground supply. When
RxO or RxO drive low impedance loads tied to VAG. a pull-up
resistor to VDD will be required to boost the source current
capability if VAG is not tied to the supply ground. All analog
Signals for the part are referenced to VAG. including noise;
therefore. decoupling capacitors (0.1 jlF) should be used
from VDD to VAG and VSS to VAG.
Vref
Positive Voltage Reference Input (MC145502 Only)
The Vref pin allows an external reference voltage to be
used for the AID and D/A conversions. If Vref is tied to VSS.
the internal reference is selected. If Vref > VAG. then the
external mode is selected and the voltage applied to Vref is
used for generating the internal converter reference voltage.
In either internal or external reference mode. the actual
voltage used for conversion is multiplied by the ratio selected
by the RSI pin. The RSI pin circuitry is explained under its
pin description below. Both the intemal and extemal
references are inverted within the PCM codec-liIter for

MC145500.MC145501.MC145502.MC145503.MC145505
2·862

negative input voltages such that only one reference Is
required.
External Mode - In the external reference mode (Vref >
VAG). a 2.5 V reference like the MC1403 may be connected
from Vref to VAG. A single extemal reference may be shared
by tying together a number of Vref pins and VAG pins from
different codec-filters. In special applications. the extemal reference voltage may be between 0.5 and 5 V. However. the
reference voltage gain selection circuitry associated with RSI
must be considered to arrive at the desired codec-filter gain.
Intemal Mode - In the intemal reference mode (Vref
VSS). an internal 2.5 V reference supplies the reference
voltage for the RSI circuitry. The Vref pin is functionally
connected to VSS forthe MC145500. MC145501. MC145503.
and MC145505 pinouts.

=

RSI
Reference Select Input (MC145501/02 Only)
The RSllnput allows the selection ofthree different overload
or full scale AID and D/A converter reference voltages independent of the internal or external reference mode. The RSI
pin is a digital input that senses three different logic states:
VSS. VAG. and VDD. For RSI VAG. the reference voltage is
used directlyfortheconverters. The internal reference is 2.5 V.
For RSI
VSS. the reference voltage is multiplied by
the ratio of 1.26. which results in an internal converter reference of 3.15 V. For RSI
VDD. the reference voltage is
. multiplied by 1.51. which results in an intemal converter reference of 3.78 V. The device requires a minimum of 1.0 V of
headroom between the internal converter reference to VDD.
VSS has this same absolute valued minimum. also measured
from VAG pin. The various modes of operation aresummarized
in Table 2. The RSI pin is functionally connected to VSS for
the MC145500. MC145503. and MC145505 pinouts.

=

=

=

RxO,RiO
Receive Analog Outputs
These two complimentary outputs are generated from the
output of the receive filter. They are equal in magnitude and
out of phase. The maximum signal output of each is equal
to the maximum peak-to-peak signal described with the
reference. If a 3.15 V reference is used with RSI tied to VAG
and a + 3 dBmO sine wave is decoded. the RxO output will
be a 6.3 V peak-ta-peak signal. RxO will also have an
inverted Signal output of 6.3 V peak-ta-peak. External loads
may be connected from RxO to RxO for a 6 dB push-pull
Signal gain or from either RxO or RxO to VAG. With a 3.15
V reference each output will drive 600 n to + 9 dBm. With
RSI tied to VDD. each output will drive 900 n to + 9 dBm.
RxG
Receive Output Gain Adjust (MC145502 Only)
The purpose of the RxG pin is to allow external gain
adjustment for the RxO pin. If RxG is left open. then the output
signal at RxO will be inverted and output at RxO. Thus the
push-pull gain to a load from RxO to Fii(O is two times the
output level at RxO. If external resistors are applied from RxO
to RxG (RI) and from RxG to RxO (RG). the gain of RxO can
be set differently from inverting unity. These resistors should
be in the range of 10 kn. The RxO output level is unchanged
by the resistors and the RxO gain is approximately equal to
minus RG/RI. The actual gain is determined by taking into
account the internal resistors which will be in parallel to these
extemal resistors. The internal resistors have a large
tolerance. but they match each other very closely. This

MOTOROLA COMMUNICATIONS DEVICE DATA

matching tends to minimize the effects of their tolerance on
external gain configurations. The circuit for RxG and RxO is
shown in the block diagram.

VSS
Most Negative Power Supply
VSS is typically 10 to 12 V negative of VDD.
For a ±5 V dual-supply system, the typical power supply
configuration is VDD + 5 V, VSS
5 V, VLS 0 V (digital
ground accommodating TTL logic levels), and VAG = 0 V
being tied to system analog ground.
For single-supply applications, typical power supply
configurations include:
VDD = 10 V to 12 V
VSS = 0 V
VAG generates a mid supply voltage for referencing all
analog signals.
VLS controls the logic levels. This pin should be connected
to VDD for CMOS logic levels from VSS to VDD. This pin
should be connected to digital ground for true TTL logic levels
referenced to VLS.

Txl
Transmit Analog Input
Txl is the input to the transmit filter. It is also the output of
the transmit gain amplifiers of the MC145501/02103/05. The
input impedance is greater than 100 kn to VAG in the
MC145500. The Txl input has an internal gain of 1.0, such
that a +3 dBmO signal at Txl corresponds to the peak
converter reference voltage as described in the Vref and RSI
pin descriptions. For 3.15 V reference, the +3 dBmO input
should be 6.3 V peak-to-peak.

=

+Tx/-Tx
Positive Tx Amplifier Input (MC145502103/05 Only) I
Negative Tx Amplifier Input (MC145501/02103/05 Only)
The Txl pin is the input to the transmit band-pass filter. If
+Tx or - Tx is available, then there is an internal amplifier
preceding the filter whose pins are +Tx, - Tx, and Txl. These
pins allow access to the amplifier terminals to tailor the input
gain with external resistors. The resistors should be in the
range of 10 kU If +Tx is not available, it is internally tied to
VAG. If - Tx and +Tx are not available, the Txl is a unity gain
high-impedance input.

VDD
Most Positive Power Supply
VDD is typically 5 to 12 V.
MC145503
6000
Rx

5kO
Tx
<

VOO

2 RxO

ROO

+ Tx
4 Txl
5
- Tx

I

681

VAG

o----!

10kO

,i

-=
0.1 IlF

I

MulA

~

POI
8 VSS

1

=

TESTING CONSIDERATIONS (MC145500/01/02 ONLy)
An analog test mode is activated by connecting MSI and
CCI to 128 kHz. In this mode, the input of the AID (the output
of the Tx filter) is available at the PDI pin. This input is direct
coupled to the AID side of the codec. The AID is a differential
design. This results in the gain of this input being effectively
attenuated by half. If monitored with a high-impedance buffer,
the output of the Tx low-pass filter can also be measured at
the PDI pin. This test mode allows independent evaluation
of the transmit low-pass filter and AID side of the codec. The
transmit and receive channels of these devices are tested with
the codec-filter fully functional.

POWER SUPPLIES

...--...!.

=-

RCE
ROC

fO.l

51 kO"

16
15
14

5V

IlF

ENABL E

13

CLOCK

rE U

TOC
TOO 11
10
TOE

VLS~n

*To define RDO when TOO is high Z.

-b

-5V

Figure 1. Test Circuit

Table 1. Options Available by Pin Selection
RSI*
Pin Level

V,e"
Pin Level

VOO

VSS

7.56 Vpp

VOO

VAG + VEXT

(3.02 x VEXT) Vpp

Peak-to-Peak Overload Voltage (Txl, RxO)

VAG

VSS

5Vpp

VAG

VAG +VEXT

(2 x VEXT) Vpp

VSS

VSS

6.3 Vpp

VSS

VAG + VEXT

(2.52 x VEXT) Vpp

*On MC145500/03/05, RSI and V,ef tied internally to VSS. On MC145501, V,ef tied internally to VSS.

MOTOROLA COMMUNICATIONS DEVICE DATA

MC145500.MC145501.MC145502.MC145503.MC145505
2-863

.

Table 2. Summary of Operation Conditions User Programmed Through Pins VDD. VAG and VSS

~
Programmed

Logic
Level

MulA

RSI
Peak Overload
Voltage

VLS

VDD

Mu·Law Companding Curve and D3/D4
Digital Formats with Zero Code Suppress

3.78

CMOS
Logic Levels

VAG

Mu-Law Companding Curve and Sign
Magnitude Data Format

2.50

TTL Levels
VAG Up

VSS

A-Law Companding Curve and CCITT
Digital Format

3.15

TTL Levels
VSSUp

TOE

TOC

"Data output during this time will vary depending on TDC rate and TDE timing.

Figure 2. Transmit Timing Diagram

RCE

Figure 3. Receive Timing Diagram

MSI

CCI

Figure 4. MSIICCI Timing Diagram

MC145500.MC145501.MC145502.MC145503.MC145505
2-864

MOTOROLA COMMUNICATIONS DEVICE DATA

1.00
0.80

r----------------..,
VOO=+5V

1.00 . . . . . - - - - - - - - - - - - - - - . . . ,
VOO=+SV
Vss=-SV
2048 kHz CLOCK
0.60
0.80

VSS=-5V
2048 kHz CLOCK

0.60
GUARANTEEO
PERFORMANCE

CD 0.40

~ 0.20
~
a:
0

_

~

~

0.40

020

ffi

w

-0.20

z -0.20

"-0.40

-0.40

~

~

-0.60

-0.60

-0.80
_ 1.00 '--...L......L.---'-----l'--.L-...L......L.--I..----l_.L-...L......L....J
-60
-so
-40
-30
-20
-10
o
INPUT LEVEL AT 1.02 kHz

-0.80
_ 1.00 '--...L......L.--I..----l_.L-...I-...L.--I..----l_.L-...I-...L....J
-so
-40
-30
-20
-10
-60
INPUT LEVEL AT 1.02 kHz

Figure 6. MC145502 Gain vs Level Mu-Law Receive

Figure 5. MC145502 Gain vs Level Mu-Law Transmit

4S.0

r-----------------.

~ 40.0

15

3S.0

~c

30.0

~

z

a

I

~.O.-----------------,

CD 40.0

:s-

15

~
Iii

VOO=+SV
VSS=-5V
2048 kHz CLOCK

2S.0
20.0

30.0

is

15

I

GUARANTEEO
PERFORMANCE

1S.0

3S.0

2S.0
20.0

o 15.0

10.0 '--...I-...L....L----l_.L-...I-...L.--I..----l_.L-...L.......L.......I
-60
-SO
-40
-30
-20
-10
o
INPUTLEVELAT 1.02 kHz

~

0.2

o

O.B . - - - - - - - - - - - - - - - - . . . . . ,
VOO = +5 V
0.6
VSS=-5V
2048 kHz CLOCK
0.4

CD
a:

:B.

TYPICAL PEFORMANCE

~

zffi -0.2
~ -0.4

ffi

GUARANTEEO
-0.6
PERFORMANCE
-0.8 '--_ _.L-_ _...I-_ _...J...._ _....L.._ _.....J
-60

-SO

-40

-30

-20

-10

INPUT LEVEL PSEUDO NOISE (dBmO)

Figure 9. MC145502 Gain vs Level A-Law Transmit

MOTOROLA COMMUNICATIONS DEVICE DATA

GUARANTEEO
PERFORMANCE

Figure 8. MC145502 Quantization
Distortion Mu-Law Receive

0.8.------------------,
VOO=+SV
0.6
VSs=-5V
2048 kHz CLOCK
0.4

aa:

VOO=+5V
VSS =-5 V
2048 kHz CLOCK

10.0 '--...I-....L.....L--1_'--...I-....L..--I..----l_.L...-...L...-L.......I
-20
-10
-30
-60
-SO
-40
o
INPUT LEVEL AT 1.02 kHz

Figure 7. MC145502 Quantization
Distortion Mu-Law Transmit

a:

GUARANTEEO
PERFORMANCE

~

0.2

o

TYPICAL PEFORMANCE

-0.2
-0.4
-0.6
-o.8'------...I-------'-----.....J------.L...-----...J
-50
-40
-30
-20
-10
-60
INPUT LEVEL PSEUOO NOISE (dBmO)

Figure 10. MC145502 Gain vs Level A-Law Receive

MC145500.MC145501.MC145502.MC145503.MC145505
2-865

m

40.0

:E!.

z

a
~

I:!
en
i5

25.0

~

20.0

§

15.0

1=

40.0

z

35.0

~

GUARANTEED
PERFORMANCE

30.0

z

a

m
:E!.

35.0

~

30.0

z

25.0

~

20.0

i5

PSOPHOMETRIC
WEIGHTED

GUARANTEED
PERFORMANCE

PSOPHOMETRIC
WEIGHTED

Q

1=

~
:::> 15.0

0

0

10.0
-60

-50

-40

-30

-20

-10

10.0
-60

0

-50'

INPUT LEVEL PSEUDO NOISE (dBmO)

Figure 11. MC145502 Quantization Distortion
A-Law Transmit

m

70

z

60

t3w

50

:E!.

a

~

Il.
Il.

:::>
en

c:

~

Il.

TYPICAL PERFORMANCE

m

70

z

60

u
w
jjj

50

40

c:

30

Il.
Il.

~

:::>
en

c:

20

~

10

Il.

0

ro

20

~

40

~

M

ro

40

20
10

00

~

0

ro

20

~

FREQUENCY (kHz)

m

70

z

60
50

c:

40

~

:::>

en
c:
w

~

Il.

m

70

z

60

:E!.

jjj

Il.
Il.

~

M

ro

M

00

~

Figure 14. MC145502 Power Supply Rejection
Ratio Negative Transmit VAC =250 mVrms,
C-Message Weighted

TYPICAL PERFORMANCE

~

40

FREQUENCY (kHz)

Figure 13. MC145502 Power Supply Rejection
Ratio Positive Transmit VAC =250 mVrms,
C-Message Weighted

:E!.

-10

30

0
M

-20

TYPICAL PERFORMANCE

:E!.

~

0

-30

Figure 12. MC145502 Quantization Distortion
A-Law Receive

jjj

c:

-40

INPUT LEVEL PSEUDO NOISE (dBmO)

§w

50

c:

40

TYPICAL PERFORMANCE

jjj

~

Il.
Il.

30

:::>
en
c:
w

20

~

Il.

10
10

20

30

40

~

60

70

80

90

100

FREQUENCY (kHz)

Figure 15. MC145502 Power Supply Rejection
Ratio Positive Receive VAC =250 mVrms,
C-Message Weighted

MC145500.MC145501.MC145502.MC145503.MC145505

2-866

30
20
10
10

.20

30

40

50

60

70

80

90

100

FREQUENCY (kHz)

Figure 16. MC145502 Power Supply Rejection
Ratio Negative Receive VAC =250 mVrms,
C-Message Weighted

MOTOROLA COMMUNICATIONS DEVICE DATA

0.2

2.0 . - - - - - - - - - - - - - - - - ,

-0.1 iii -0.2 :20.1

---'

01===::::::;.....

~

-2.0

PERFORMANCE
GUARANTEED
PERFORMANCE

z -0.3 ;;;:
Cl -0.4 '-

-4.0
iii -6.0
:2-

z -B.O

~-10.0

-0.5

;-

-12.0

-0.6

;-

-14.0

-0.7 i-O.B

o

I
0.4

I
O.B

I
1.2

I
1.6

I
2.0

I
2.4

I
2.B

I
3.2

GUARANTEED
PERFORMANCE
-16.0
-IB.O '---'--'-_'--..1--'---'_......-'---'.......................---1
3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.B 3.9 4.0 4.1 4.2
FREQUENCY (kHz)

3.6

FREQUENCY (kHz)

Figure 17. MC145502 Pass-Band
Filter Response Transmit

Figure 18. MC145502 Low-Pass Filter
Response Transmit

2.0.----..-------------.

0.2
0.1

-2.0

r-=================~===I

o

-6.0

-0.1

TYPICAL
PERFORMANCE

iii - 0.2

~--------~~~------~
GUARANTEED

z-14.0

~ - 0.3

PERFORMANCE

1B.0

-0.4

iii- l 0.0
:2-

;;:

Cl-

~

-22.0 F---......II/

-0.5
-0.6

-26.0

-0.7

:30.0 '---'--'--'-''---'--'---'_..............--'_.............---1
o
0.04
0.08
0.12
0.16
0.20
024
FREQUENCY (kHz)

-O.B 1..---'_-'-_-'-_'----'_........_-'-4-.................
0
0.4
O.B 1.2 1.6
2.0 2.4 2.B
3.2 3.6
FREQUENCY (kHz)

Figure 19. MC145502 High-Pass Filter
Response Transmit

Figure 20. MC145502 Pass-Band
Filter Response Receive

2.0.-----------------.

01--------.
-2.0

GUARANTEED
PERFORMANCE

-4.0

i
z

~

-6.0
-B.O
-10.0
-12.0
-14.0
-16.0
-IB.O '---'--'---''--..L--'---'_......-'---'_.a..-'---'
3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.B 3.9 4.0 4.1 4.2
FREQUENCY (kHz)

Figure 21. MC145502 Low-Pass Filter Response Receive

MOTOROLA COMMUNICATIONS DEVICE DATA

MC145500.MC145501.MC145502.MC145503.MC145505
2-867

3000,.--_ _ _ _ _ _ _ 2.048 MHz
(TOC, ROC, cel)

+5V

OSC

OSC

OSC

IN

OUT 1

OUT 2

8kHz
(TOE, ACE, MSI)

MC74HC4060
Q4

Q

Q

112
MC74HC73
K

R

Q

+5V

255

256

2

3

4

5

6

7

9

10

2.048 MHz

8kHz

Figure 22. Simple Clock Circuit for Driving MC145500/01/02l03l05 Codec-Filters

MC145500.MC145501.MC145502.MC145503.MC145505

2·868

MOTOROLA COMMUNICATIONS DEVICE DATA

~

[~
=:3
-48V

VAG

VOO

RxO

ROD

+ Tx

RCE

Txl

ROC

-Tx

TOC

MulA

TOO

POI

TOE

VSS

VLS

10kn

N=1

MCI45503
23A. Simplified Transformer Hybrid Using MC145503

R3

':'

RS
R6

':'

VAG

VOO

RxO

ROD

+Tx

RCE

Txl

ROC

-Tx

TOC

MulA

TOO

POI

TOE

VSS

VLS

Rl

R2

RO=R3I1R411(R2+Rl)=R311 R4
PI
_
Roll R4II(R2+ Rl)
"lout - R3+ RO II R4 II(R2 + Rl)

AV'

RoIIR4
= R3+ROIIR4

_.::B!
R2

MCl45503

In -

NOTE: Hybrid Balance by RS and R6 to equate the RxO signal gain at Txl through the Inverting
and non-Inverting signal paths.

23b. Universal Transformer Hybrid Using MC14SS03

Figure 23. Hybrid Interfaces to the MC145503 PCM Codec-Fllter Mono-Circuit

MOTOROLA COMMUNICATIONS DEVICE DATA

MC145500.MC145501.MC145502.MC145503.MC145505

2-869

VSS

+Vref

RSI

VAG

VOO

RxO

ROD

RxG

RCE

RiO

ROC

+Tx

TOC

Txl

CCI

-Tx

TOO

MulA

TOE

POI

MSI

Vss

VLS

R4
R3

R2

Rl

RS RS

NOTE: Balance by
and
to equate the TxI gains through the Inverting
and non-Inverting Input signal paths, respectively, Is given by:

2:~20

-::)= (1

+

:~) [RS:SRS - :: (RS:5R~J

Tx Gain = R11R2
Rx Gain = 1+ R3IR4
RS, R6= 10kQ
Adjust Rx Gain wiIh R3
Adjust Tx Gain willi Rl

MC145502

248. Universal Transformer Hybrid Using MCl45502
RO 600

I
.J

10kQ
N=2

.f.
-

I

V~s

'A

20kn

+Vref

:SI

VAG

VOO

RxO

I

RxG

RO

RxO
+Tx

-'>.A

I

RO=900

1°
-

ROD
RCE
ROC
TOC

Txl
CCI

20kQ
-Tx

10kQ

TOO
MulA

TOE

POI

MSI

VSS

VLS

MC145502
24b. Single-Ended Hybrid Using MCI45502

Figure 24. Hybrid Interfaces to the MC145502 PCM Codec-Fllter Mono-Circuit

MC145500.MC145501.MC145502.MC145503.MC145505
2-870

MOTOROLA COMMUNICATIONS DEVICE DATA

:;:
0
-f
0

:Il

0

r»
()

0

!!

IC
C

(jl

:;:
:;:

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en

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~

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m

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C;

m

0

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0

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![
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-48V--,

~
()

::J'
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TIP --4t--'I/II\i

UI
0

~

s::

0
....
....
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UI
0
CAl

3:
0....

N ....
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(l)UI
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.... UI

•

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en
r-

(AO)

-=

RS
126kn

-=

TSI

POI

CC

HSO

RSI

TSO 13

(At)

0.0047 ::;:

..........

0.0047

T
47k

C;

SN

RSO 12

EN

HST
Vas

VEE

:s

s:
~
....
U1
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0
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s:
0
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c

;:;:

-=

lkn

lN4002

rr-t

-48V

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1Ol1F
+sov

AxO

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+Tx

RCE 14

Txl

ROC 113

4

TOC r2
TOO 11

7 _
POI

It
10

~R7

270kn

..l..

-SV

0.1

VOO

-Tx

+5V

16

VAG

6 MulA

DI

a.

2

tOkn
tOkn

s:
ID

0.47

3

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RING

()

::

I

19.6kn

III

S·

R1
30.1 kn

,~

TxO
'

+SV

MCl45503

19.6kn

c::

IC

[2:

Rxl

:s
;:;:

3:
0
....
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UI
0
....
3:
0
....
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VAG

DI

!!.

UI
UI
0
0

I Vcc

17 -

c::

s::

MC3419-1L

,

"D

:s
:s

0
....
....

,

en

:i"
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~

1\):5:

&00
.........

+SV

t

1\)"",

til
til

o

o

1 V

~

...o
"'"

til
til

SPEAKER

~

~

...o

SW1: CLOSED = ON·HOOK
OPEN = OFF·HOOK

"'"

til
til

~
~
~

"'"

til
til

8

~
~

"'"
8l
fil

VDD 9
OSC 2

iil

I\)

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;::

!1

~

~

iii
::r
0
:s

"C

r:t ~

C1>

~

@

3
!!!.

R3,

o·

:0

o

R4

R2

';
o

Rl

o

~
~

c

z

o
~

a
z

(fl

o
m
<

o

m

o
:!:j

»

-=

~ RS

::r

S
Tx: iliA
Txl
VDD
3 RxO

a
1~

1 Tx+
9 VAG
VLS

r~'I

I

i

I CST

IL HANDSET
I
_ _ _ .l

;::

!1

III
8

C4

-=

C1

~Rll

POI
TOC
RDC
RCE
RDD

7

I

I

~

r1£-,

~
~

I

-SV

1

SYNC TO
POWER SUPPLY

-:....
-

~
~

Cl0...

C9

L

I

C7

~ XlgR16~ C~
~
~
3
r--

18 Tx
Rx '" LB 21
19
LOI 3
TREEI
LI S
+SV'-VD'::"
Vss
Vref 2

T RIO 1

+5V

-0-0-0-0-0-0-0-0-0-0-

~
22
I 8" S02
VDD 16
------ SI2
X2
SOl
PO
17 Sil ;:: XI 10
13 CLK
iliA
14 TEl
L02 4

I

113 1
14
IS

TOD 11
10
TOE 8
VSS

-=

~ ~ RxS ~ BR2 ~
,-----;;;RST co BR3
r---_-"IS'-( DCLK BCLK
18 DCO
CM
13 DC[
VSS 10

OPL 17

~C2

C1>
(fl

n

I

OH r1c::.2_ _ _; -_ _ _ _t-___---'

TSO

RS

R3S;\\

vssf":------<.-......---+......--~

DTMF OUT

Rx2r.st==2~;::=:t:

Tx2(..:
Txl ~
Rxl
GND 9

VDD
TxS
DOE BRCLK 4
D[E
DL
TxD
SB
'--_--'171
1 RxD ~ BRI

10
MS I-:l:::-l---~
M0 6
SW2

..

+sv

LED..L

R36

C4 NcD
oscS
X2

't!

ca·0

16

CC 7
Tx3 f.!6------,
Rx3 (.!'..----+-J.;
4

-SV

+SV

"e:
ca·

V

10 DD
r----"II'-iD[3
D03;::
13
0
12 D02 ~
D[2 ~
14 D[l '"
15 DOl
VSS

I""l

'
CTIP

J

*
T

I

Cll

......,

i

~

V

. TO POWER
CSUPPLYVin

R[NG

~

Refer 10 AN968 for more information.

Table 3. Mu-Law Encode-Decode Characteristics

Chord
Number

Number
of Steps

Step
Size

Normalized
Encode
Decision
Levels

Digital Code

1
Sign

I

I
I Chord I Chord I Chord I Step I
2

I

3

I

4

I

5

I
Step I
6

7
Step

I
I

Step

Normalized
Decode
Levels

8

8159
1

0

0

0

0

0

0

0

8031

1

0

0

0

1

1

1

1

4191

1

0

0

1

1

1

1

1

2079

1

0

1

0

1

1

1

1

1023

1

0

1

1

1

1

1

1

495

1

1

0

0

1

1

1

1

231

1

1

0

1

1

1

1

1

99

1

1

1

0

1

1

1

1

33

1

1

1

1

1

1

1

0

2

1

1

1

1

1

1

1

1

0

7903
8

16

256
4319
4063

7

16

128

2143
2015

6

16

64

1055
991

5

16

32

511
479

4

16

16

239
223

3

16

8

103
95

2

16

4

35
31

1

15

2

3
1

1

1
0

NOTES:
1. Characteristics are symmetrical about analog zero with sign bit = 0 for negative analog values.
2. Digital code includes inverison of all magnitude bits.

MOTOROLA COMMUNICATIONS DEVICE DATA

MC145500.MC145501.MC145502.MC145503.MC145505
2-873

Table 4. A-Law Encode-Decode Characteristics

Chord
Number

Number: Step
of Steps
Size

Normalized
Encode
Decision
Levels

Digital Code

1
Sign

I
I

2
Chord

I

3

I

4

I

I Chord I Chord I

5
Step

6

I

7

Step

I

Step

I
I

I
I

Step

Normalized
Decode
Levels

8

4096
1

0

1

0

1

0

1

0

4032

1

0

1

0

0

1

0

1

2112

1

0

1

1

0

1

0

1

1056

1

0

0

0

0

1

0

1

528

1

0

0

1

0

1

0

1

264

1

1

1

0

0

1

0

1

132

1

1

1

1

0

1

0

1

66

1

1

0

1

0

1

0

1

1

3968
7

16

128
2176
2048

6

16

64

1088
1024

5

16

32

544
512

4

16

16

272
256

3

16

8

136
128

2

16

4

68
64

1

32

2

2
0

NOTES:
1. Characteristics are symmetrical about analog zero with sign bit 0 for negative analog values.
2. Digital code includes alternate bit inverison, as specified by CCITT.

=

MC145500.MC145501.MC145502.MC145503.MC145505
2-874

MOTOROLA COMMUNICATIONS DEVICE DATA

MOTOROLA

-

SEMICONDUCTOR
TECHNICAL DATA

MC145532
Advance Information

ADPCM Transcoder

DWSUFFIX

SOG
CASE 751G

Conforms to G.721-1988 and T1.301-1987
The MC145532 Adaptive Differential Pulse Code Modulation (ADPCM)
Transcoder provides a low-cost, full-duplex, single-channel transcoder to (from)
a 64 kbps PCM channel from (to) either a 16 kbps, 24 kbps, 32 kbps, or 64 kbps
channel.
•
•
•
•
•
•
•
•
•
•

Complies with CCITT Recommendation G.721-1988
Complies with the American National Standard (T1.301-1987)
Full-Duplex, Single-Channel Operation
Il-Law or A-Law Coding is Pin Selectable
Synchronous or Asynchronous Operation
Easily Interfaces with Any Member of Motorola's PCM Codec-Filter
Mono-Circuit Family or Other Industry Standard Codec
Serial PCM and ADPCM Data Transfer Rate from 64 kbps to 5.12 Mbps
Power Down Capability for Low Current Consumption
The Reset State, an Option Specified in the Standards, is Automatically Initiated
When the RESET Pin is Released
Simple Time Slot Assignment Timing for Transcoder Applications

-

LSUFFIX

CERAMIC
CASE 620

1

• Single 5 V Power Supply
• 16-Pin Package
• The MC145536EVK is the evaluation platform for the MC145532 and also
includes the MC145480 5 V PCM Codec-Filter

PIN ASSIGNMENT

MODE [ 1·

16

VDD

DDO[ 2

15

EDO

DOE [ 3

14

EOE

DOC [ 4

13

EDC

DDI[ 5

12

EDI

PEIE
PSPC
9 PAPD

DIE[ 6

11

RESET [ 7

10

VSS[ 8

BLOCK DIAGRAM
000

EDO

DOE

EDE

DOC

EDC

001

EDI

DIGITAL
SIGNAL
PROCESSOR

DIE

MODE

APD

-----------.j

VSS ----~~

EIE

1+----------14----------

RESET
SPC

~4---VDD

This dOCllment contains Information on a new product under development. Motorola reserves the right to change or discontinue this product without notice.

MOTOROLA COMMUNICATIONS DEVICE DATA

MC145532
2-875

DEVICE DESCRIPTION
An Adaptive Differential PCM (ADPCM) transcoder is used
to reduce the data rate required to transmit a PCM encoded
voice signal while maintaining the voice fidelity and intelligibility of the PCM signal.
The transcoder is used on 64 kbps data streams which
represent either voice or voice band data signals that have
been digitized by a codec (e.g., MC145557). The transcoder
uses a filter to attempt to predict the next PCM input value
based on previous PCM input values. The error between the
predicted and the true PCM input value is the information that
is sent to the other end of the line. Hence the word differential,
since the ADPCM data stream is the difference between the
true PCM input value and the predicted value. The term
"adaptive" applies to the filter that is performing the prediction.
It is adaptive in that its transfer function changes based on
the PCM input data. That is, it adapts to the statistics of the
signals presented to it.

PIN DESCRIPTION
ENCODER INPUT
EDI
Encoder Data Input (Pin 12)
PCM data to be encoded are applied to this input pin which
operates synchronously with EDC and EIE to enter the data
in a serial format.
EDC
Encoder Data Clock (Pin 13)
Data applied to· EDI are latched into the transcoder on a
falling edge of EDC and data are output from EDO on a rising
edge of this input pin. The frequency of EDC may be as low
as 64 kHz or as high as 5.12 MHz.
EIE
Encoder Input Enable (Pin 11)
The beginning of a new PCM word is indicated to the
transcoder by a rising edge applied to this input. The frequency
of EIE may not exceed 8 kHz.
ENCODER OUTPUT
EDO
Encoder Data Output (Pin 15)
ADPCM data are available in a serial formatfrom this output,
which operates synchronously with EDC and EOE. EDO is
a three-state output which remains in a high-impedance state,
except when presenting data.
EOE
Encoder Output Enable (Pin 14)
Each ADPCM word is requested by a rising edge on this
input, which causes the EDO pin to provide the data when
clocked by EDC. One EOE must occur for each EIE.
DECODER INPUT
DDI
Decoder Data Input (Pin 5)
ADPCM data to be decoded are applied to this input pin,
which operates in conjunction with DOC and DIE to enter the
data in a serial format.

MC145532
2-876

DOC
Decoder Data Clock (Pin 4)
Data applied to 001 are latched into the transcoder on the
falling edge of DOC and data are outputfrom 000 on the rising
edge of DOC. The frequency of DOC may be as low as 64 kHz
or as high as 5.12 MHz.
DIE
Decoder Input Enable (Pin 6)
The beginning of a new ADPCM word is indicated by a rising
edge applied to this input. Data are serially clocked into 001
on the subsequent falling edges of DOC following the DIE
rising edge. The frequency of DIE may not exceed 8 kHz.
DECODER OUTPUT

000
Decoder Data Output (Pin 2)
PCM data are available in a serial format from this output,
which operates in conjunction with DOC and DOE. 000 is
a three-state output that remains at a high-impedance state
except when presenting data.
DOE
Decoder Output Enable (Pin 3)
Each ADPCM word is requested by a rising edge on this
input which causes the 000 pin to provide the data when
clocked by DOC. One DOE must occur for each DIE.
CONTEXT
MODE
Mode Select (Pin 1)
A logic 0 applied to this input makes the transcoder
compatible with 1!-255 companding and 03 data format. A
logic 1 applied to this pin makes the transcoder compatible
with A-law companding with even bit inversion data format.
SPC
Signal Processor Clock (Pin 10)
This input is typically clocked with a 20.48 MHz clock signal
which is used as the digital signal processor master clock.
This pin has a CMOS compatible input.
RESET
Reset (Pin 7)
A logic 0 applied to this input forces the transcoder into a
low power dissipation mode. A rising edge on this pin causes
power to be restored and the optional transcoder RESET state
(specified in the standards) to be forced. Valid data is available
at the output pins four input enables after a rising edge on
this pin. This pin has ~,~MOS compatible input.
APD
Absolute Power Down (Pin 9)
A logic 1 applied to this input forces the transcoder into a
power saving mode. This pin has a CMOS compatible input.
POWER SUPPLY
VDD
Positive Power Supply (Pin 16)
The most positive power supply pin, normally 5 V.
VSS
Negative Power Supply (Pin 8)
The most negative power supply pin, normally 0 V.

MOTOROLA COMMUNICATIONS DEVICE DATA

FUNCTIONAL DESCRIPTION
ENCODING/DECODING RATES
The MC145532 allows for the encoding and decoding of
data at one of four rates on a sample by sample basis. Each
data sample that is provided to the part is accompanied by
an indication of the rate at which it is to be encoded ordecoded.
The width of the enable pulse determines the encoding/decoding rate chosen for each sample.
The 64 kbps rate allows for PCM data to be passed directly
through the part. The 32 kbps rate is either the G.721 or the
T1.301-1987 standard, depending on the state of the mode
pin. The 24 kbps encoding rate is compliant with CCITT G. 723
and G.726. The 16 kbps rate is a modified quantizerfrom the
32 kbps technique and is not a standard.
TIMING
Figures 1 through 8 show the timing of the input and output
pins. The MC145532 determines the mode of the timing
signals, either short or long frame, for each enable,
independent of the mode of any previous enables. A transition
from short frame to long frame mode or vice versa will cause
at least one frame of data to be destroyed. Each of the four
sets of I/O pins determines its mode independent of the other
sets. Thus the encoder input could be operating with long
frame timing and the output could be operating with short
frame timing. Note that the short frame timing on the input
enables can only be used with the 32 kbps transcoding rate.
The number of data clock falling edges enclosed by the input
enable line (EIE or DIE) determines both the short frame or
long frame mode and the transcoding rate. The mode of the
input or output is determined each frame. In all modes, the
data is captured by the MC145532 on the falling edge of either
EDC or DDC.
ENCODER INPUT - SHORT FRAME
Figure 1 shows the timing of the encoder data clock (EDC),
the encoder input enable (EIE), and the encoder data input
(ED I) pins in short frame operation.
The determination of short frame mode is made by the
MC145532 based on one falling EDC edge while EIE is high.
Note that only a 32 kbps encoding rate can be specified when
using short frame mode on the encoder input.
ENCODER INPUT - LONG FRAME
Figure 2 shows the clock, enable, and data signals for the
encoder input in long frame mode. In this mode, the data is
captured by the MC145532 on the falling edge of EDC.
The determination of the encoding rate is made based on
the number of falling EDC edges seen by the MC145532 while
EIE is high. Four edges implies a 32 kbps encoding rate, three
edges implies a 24 kbps encoding rate, two edges implies a
16 kbps rate, and from five to eight inclusive imply a 64 kbps
rate. The encoding rate may be changed on a frame by frame
basis. The encoded word is available at EDO (via EOE and
EDC) from 250 Jls to 375 JlS after it is requested.
ENCODER OUTPUT - SHORT FRAME
Figure 3 shows the timing of the encoder output in short
frame mode. The length of the LSB is always one half of an
EDC cycle.

MOTOROLA COMMUNICATIONS DEVICE DATA

The EDO will provide the correct number of bits for the
encoding rate that was selected for this frame of data on the
encoder input pins. The data is loaded into the MC145532
during one frame, encoded on the next frame, and read during
the third frame.
ENCODER OUTPUT - LONG FRAME
Figure 4 shows the timing of the encoder output in long
frame mode. The enable must be wider than two falling edges
of the EDC to be in long frame mode. If the enable falls before
the correct number of bits have been presented to the output
(EDO), the transcoder will complete the presentation of the
bits to the output with the LSB being one half of an EDC period
wide. If the enable falls after the one half EDC period of the
LSB, then the LSB will be extended up to the full EDC clock
period and the subsequent data will be a recirculation of the
previous data, which repeats until the enable pin falls. This
is shown on the second enable for the 16 kbps encoding rate
example in Figure 4.
DECODER INPUT - SHORT FRAME
Figure 5 shows the timing of the decoder data clock, the
decoder input enable, and the decoder data input pins in short
frame operation. Note that in this mode only a 32 kbps
decoding rate can be selected.
DECODER INPUT - LONG FRAME
Figure 6 shows the clock, enable, and data signals for the
decoder input in long frame mode.
The determination of the decoding rate is made based on
the number of falling DDC edges seen by the MC145532while
DIE is high. Four edges implies a 32 kbps decoding rate, three
edges implies a 24 kbps decoding rate, two edges implies a
16 kbps rate, and from five to eight edges inclusive imply a
64 kbps rate. The decoding rate may be changed on a frame
by frame basis.
DECODER OUTPUT - SHORT FRAME
Figure 7 shows the timing of the decoder output in short
frame mode.
The DDO will provide the 8-bit PCM word for the decoding
rate that was selected for this frame of data on the decoder
input pins. The data is loaded into the MC145532 during one
frame, decoded on the next frame, and read during the third
frame.
DECODER OUTPUT - LONG FRAME
Figure 8 shows the timing of the decoder output in long
frame mode. Note that at least eight bits are presented to the
output, provided that at least two falling edges of DDC are
seen while DOE is high. The enable can be used to extend
the LSB to a full DDC period and/or cause the eight bits of
data to be recirculated to the output pin until the enable falls.
STANDARDS INFORMATION
The following standards apply to the MC145532:
T1.301-1987-32 kbps APDCM
T1.303-1988-24 kbps ADPCM.
CCITT G.721 , G.723, and G.726-32 kpbs and 24 kpbs
CCITT documents may be obtained by contacting Omnicom
in the USA at (703) 281-1135.

MC145532
2-877

ABSOLUTE MAXIMUM RATINGS (Voltages Referenced to VSS)
Rating
OC Supply Voltage

Symbol

Value

Unit
V

VOO

- 0.5 to+ 7.0

Voltage, Any Pin to VSS

V

- 0.5 to VOO + 0.5

V

DC Current, Any Pin

lin

±IO

rnA

Operating Temperature

TA

-40to+85

°C

Tstg

-85to+150

°C

Storage Temperature

This device contains circuitry to protect
against damage due to high static voltages or
electric fields; however, it is advised that
normal precautions be taken to avoid
application of any voltage higher than.
maximum rated voltages to this high
impedance circuit. For proper operation it is
recommendedthatVlnandVoutbeconstrained
to the range VSS ~ (Vin or Voutl ~ VOO.
Unused inputs must always be tied to an
appropriate logic voltage level (e.g., eltherVSS
orVOO)·

RECOMMENDED OPERATING CONDITIONS (TA = - 40 to + 85°C)
~ymbol

Min

Max

OC Supply Voltage

VOO

4.50

5.50

V

Power Oissipation

Po

-

0.28

W

Unit

Parameter

Unit

DIGITAL CHARACTERISTICS (VOO = 5.0 V, TA = - 40 to + 85°C)
Symbol

Min

Max

High Level Input Voltage

Mode, OOE, ~OC, 001, OlE, EIE, EOI, EOC, EOE

VIH

2.0

-

V

Low Level Input Voltage

Mode, OOE, ~OC, 001, OlE, EIE, EOI, EOC, EOE

VIL

-

0.8

V

High Level Input Voltage

RESET, APO, SPC

VIH

0.7VOO

-

V

Low Level Input Voltage

RESET, APO, SPC

VIL

Parameter

"

lin
Cin

-

10

pF

High Level Output Voltage (IOH = -2.0 rnA)

000, EOO

VOH

4.6

-

V·;

Low Level Output Voltage (IOL = 2.0 MA)

OOO,EOO

VOL

V

OOO,EOO

Ilkg

-

0.4

Output Leakage Current (VOO = 5.5 V)

±5.0

I1A

Input Current
Input Capacitance

0.3VOO

V

±I.O

j1A

SWITCHING CHARACTERISTICS (VOO =5.0 V, TA =- 40 to + 85°C)
Min

Max

Unit

SPC Frequency

19.990

23

MHz

SPC Outy Cycle

45

55

%

Parameter

MC145532

2-878

MOTOROLA COMMUNICATIONS DEVICE DATA

ENCODER INPUT -

SHORT FRAME (VDD

=5.0 V, TA =- 40 to + 85°C)
Symbol

Min

Max

Unit

Enable Low Setup Time

tsu(EIE)L

15

th(EIE)H

30

Enable Valid Time

tv(EIE)

15

-

ns

Enable Low Hold Time

Parameter

th(EIE)

15

Data Valid Time

tY(EDI)

15

Data Hold Time

th(EDI)

15

Enable Hold Time

ns
ns
ns
ns
ns

EDC

EIE

---Jn. .___________

~I...-.._ _ _ _ _ _ _ _

LSB

LSB

EDI

EDC
1+---Iot-tsu(EIE)L
EIE

EDI
tv(EDI)

fI__ ~
M-;:IB;-.__

Ih(EDI)

Figure 1. Encoder Input Tlmlng-Short Frame

MOTOROLA COMMUNICATIONS DEVICE DATA

MC145532

2-879

ENCODER INPUT -

LONG FRAME (VDD

=5.0 V, TA =- 40 to + 85°C)
. Symbol

Min

Iti(EIE)L

30

Enable Valid lime

tv(EIE)

15

Data Valid lime

tv(EDI)

15

Data Hold lime

th(EDI)

15

Parameter
Enable Low Hold lime

Max

Unit

-

ns
ns
ns
ns

EDC

EIE32kbps

~

EIE24 kbps

~

EIE16kbps

~

EIE64kbps

~

1111111111

111111111
LSB

LSB

EDI

EDC

EIE

EDI

Figure 2. Encoder Input Timing-Long Frame

MC145532
2-880

MOTOROLA COMMUNICATIONS DEVICE DATA

ENCODER OUTPUT -

SHORT FRAME (VDD = 5.0 V, TA = - 40 to + 85°C)
Parameter

Enable Low Hold lime
Enable Valid lime
Enable Hold lime
Data Valid lime
Data Three-State lime (with 150 pF Load)

Unit

Symbol

Min

th(EOE)L

30

tv(EOE)

15

th(EOE)

15

-

tv(EDO)

-

40

ns

tz(EDO)

1

30

ns

Max

ns
ns
ns

EDC

EOE

nL-----______

n

---J~'--_ _ _ _ _ _ _

LSB

LSB

EDO----{
·32 kbps transcoding rate selected for this frame at EIE

@

64 kbps trans coding rate selected for this frame at EI E

EDC

EOE
tx(EDO)
tV(EDO)-+--+tIr-_ _ _ _ _"'.,...._ _--.
EDO

------------------<1

MSB

LSB

Figure 3_ Encoder Output Timing-Short Frame

MOTOROLA COMMUNICATIONS DEVICE DATA

MC145532
2-881

ENCODER OUTPUT -

LONG FRAME (VDD = 5.0 V, TA = - 40 to + 85°C)
Parameter

Enable Low Hold TIme
Enable Valid TIme
Enable to Data TIme (Whichever Edge Occurs Last)

Symbol

Min

th(EOE)L

30

tv(EOE)

15

tEOE-EDO

Clock to Data TIme (Whichever Edge Occurs Last)

tEDC-EDO

-

Max

Unit

-

ns

40

ns

45

ns

ns

EDC

EOE~

*1.-1_ _ __

32 kbps

EDO

EOE~

~

24kbps

EDO

EOE~

@L-I_ __

16 kbps

EDO

EOE~

u

U

64kbps

EDO

*EDO Driver is controlled by EOE
#EDO completes the presentation of data
@Data recirculates

EDC

EOE

EDO ------------4--~

Figure 4. Encoder Output Timing-long Frame

MC145532
2-882

MOTOROLA COMMUNICATIONS DEVICE DATA

DECODER INPUT - SHORT FRAME (VDD =5.0 V, TA =- 40 10 + 85°C)
Parameter
Enable Low Selup Time 10 Falling DOC
Enable Low Hold Time from Falling DOC
Enable Valid Time 10 Falling DOC
Enable Hold Time from Falling DOC
Data Valid Time Before Falling DOC
Data Hold Time from Falling DOC

Symbol

Min

Isu(DIE)L

15

Ih(DIE)H

30

Iv(DIE)

15

Ih(DIE)

15

Iv(DDI)

15

IJ1(DDI)

15

Max

Unit

-

ns
ns
ns
ns
ns
ns'

DOC

DIE

--,nL.._________

~,---_ _ _ _ _ _ _ _

DDI-----{

DOC
-+r--th(DIE)---i+DIE

001

Figure 5. Decoder Input Timlng-Short Frame

MOTOROLA COMMUNICATIONS DEVICE DATA

MC145532
2-883

DECODER INPUT - LONG FRAME (VDD = 5.0 V, TA = - 40 to + 85°C)
Symbol

Min

Max

Unit

.Enable Hold Time from Falling DOC

th(DIE)

30

ns

Enable Valid Time to Falling DOC

tv(DIE)

15

Data Valid Time to Falling DOC

tv(DDI)

15

Data Hold Time from Falling DOC

th(DDI)

15

-

Parameter

ns
ns
ns

DOC

DIE~
32 kbps
DOl

DIE~
24 kbps

DOl

DIE~
16 kbps

DDI~------------------------~----------------------DIE

---.J

u

~\\\~ I

64 kbps
DOl

DOC

DIE

001

________.....;[""" .1. ,sa

''''---r

Figure 6. Decoder Input Timing-Long Frame

MC145532
2-884

MOTOROLA COMMUNICATIONS DEVICE DATA

DECODER OUTPUT -

SHORT FRAME (VDD = S.O V, TA = - 40 to + BSDC)
Symbol

Min

Max

Unit

Enable Low Hold Time

Parameter

th(DOE)L

30

ns

Enable Valid Time

tv(DOE)

15

Enable Hold Time

th(DOE)

15

-

Rising Edge of DOC to Valid 000

tv(DDO)

40

ns

Delay Time from Bth DOC Low to 000 Output Disabled

tz(DDO)

30

ns

-

ns
ns

DOC

DOE

n

~

n

I~------------~

~

_______________

LSB
000-----(

o
LSB

DOC

DOE

000

------------------<1
Figure 7. Decoder Output TIming-Short Frame

MOTOROLA COMMUNICATIONS DEVICE DATA

MC145532
2-885

DECODER OUTPUT -

LONG FRAME (VDD = 5.0 V, TA = - 40 10 + 85·C)
Symbol

Min

Enable Low Hold Time

Ih(DOE)L

30

-

ns

Enable Valid Time

Iv(DOE)

15

-

ns

Parameter

Max

Unit

Rising Edge of DOE 10 Valid 000 (when DOC Is High)

lODE-DOD

-

40

ns

Rising Edge of DOC 10 Valid 000 (when DOE is High)

IDDC-DDO

-

45

ns

Iz(DDO)

0

30

ns

Delay Time from 81h DOC Low or DOE Low 10 000 Outpul Disabled

DOC

ooE~

~\\\\\\\\\~

L

I

000

DOC

DOE

000 ------------~--~

Figure 8. Decoder Output Timing-Long Frame

MC145532

2-886

MOTOROLA COMMUNICATIONS DEVICE DATA

MC145532
PCMYBUSOUT
TS1
ADPCM Z BUS IN
TS3

~

.--.f;"

1.544 MHz

PCMXBUSOUT
TS3

MODE
000
DOE
DOC
001
DIE
RESET
VSS

VDD -+5V
EDO
EOE
EDC
EDI
EIE
SPC

ADPCM ZBUS OUT
TS 1
PCMYBUS IN
TS3

-

APD~

MC145532

f'

TS4
POWER DOWN

.f;"

MODE
000
DOE
DOC

001
DIE
RESET
VSS

VDD -+5V
EDO
EOE
EDC

TS2

EDI

PCMX BUS IN

EIE
SPC

TS1
20.48 MHz

APD~

1.544 MHz

TS1

J

TS2
TS3

L

TS4

PCM BUS OUT

000 Y
DDOx------------------~

PCM BUS IN

EDly

-------------------<

EDlx
ADPCM BUS OUT EDOzy

~>--------------------------

EDOZX------------~>------------------ADPCMBUS IN

DDlzy

------------------<~----------

DDlzx

-------------------------~
Figure 9. ADPCM Transcoder Application

MOTOROLA COMMUNICATIONS DEVICE DATA

MC145532

2-887

MC145503
VAG
':'
ANALOG OUT --";;;"'-1 RxO
ANALOG IN

+Tx
Txl

AOPCMIN
VOO
+5V
':'
ROD 1-----1--=--1
RCE
TSm1 TSm
ROC 1--1--_-1---11-1

-Tx
TOC 1-+--"
+5 V - - - - I MulA
TOO
POI
TOE
-5V I-V...::S~S_ _ _V.:::LS::.J

MC145532
MODE
000
DOE

VOO
EDO
EOE

DOC
001

EOC
EOI

DIE
RESET
VSS

EIE
SPC
APO

+5V
AOPCMOUT
TSm
1.544 MHz

20.4BMHz
':'

POWER DOWN
1.544 MHz = ROC = DOC
=TOE= EOC

L

TSml = RCE = TOE
EOI=TOO
TSm = EIE = EOE
= DIE = DOE
AOPCM OUT = EOO

ODO=ROO

AOPCM IN = 001

Figure 10. ADPCM Transcoder/Codec Application

MC145532

2-888

--~-~~-------~~~~

MOTOROLA COMMUNICATIONS DEVICE DATA

MC145557

-5V

VBB
GNDA
VFRO

f

ANALOG OUT

+5V

ff

VFXI+
VFXIGSX
TSX
FSX

~

,...
J

VCC
FSR
DR
Ox
BClKR
BClKXlMClKR MClKX

MC145532
+5 V- MODE
VDD -+5V
000
EDO
EOE
DOE
EDC
DOC

ANALOG IN
TxTIMESlOT

8 kHz

ADPCMOUT

-

2.048 MHz
ADPCM IN

001
DIE
RESET

POWER DOWN

~ VSS

EDI
EIE
SPC
APD

20.48 MHz

--:;!;.

2.048 MHz = MClKR = BClKR = DOC
= MClKX = BClKX = EDC
8kHz= DOE = DIE= FSR
= EOE = EIE = FSX

J

EDI = DX------<"'-_ _J

~ _ _J

,"_ _oJ ' -_ _J

~ _ _J

",- _ _J

'- _ _J

~ _ _J

' - _ _J

~ _ _J

",- _ _J

'- _ _J

ADPCM OUT = E D O - - - - - - (

'---_-I

000= DR------<"'-_ _J

'- _ _J

ADPCM IN = 0 0 1 - - - - - - <

Figure 11. ADPCM Transcoder/Codec Application (A-Law)

MOTOROLA COMMUNICATIONS DEVICE DATA

MC145532

2-889

MOTOROLA

-

SEMICONDUCTOR
TECHNICAL DATA

MC145540
Technical Summary

ADPCM Codec
This technical summary provides a brief description of the MC145540 ADPCM
Codec. A complete data book for the MC145540 is available and can be ordered
from your local Motorola sales office. The data book number is MC145540/D.
The MC145540 ADPCM Codec is a single chip implementation of a PCM
codec-filter and an ADPCM encoder/decoder, and therefore provides an efficient
solution for applications requiring the digitization and compression of voiceband
signals. This device is designed to operate over a wide voltage range, 2.7 to 5.25 V
and, as such, is ideal for battery powered as well as ac powered applications.
The MC145540 ADPCM Codec also includes a serial control port and internal
control and status registers that permit a microcomputer to exercise many built-in
features.
The ADPCM Codec is designed to meet the 32 kbps ADPCM conformance
requirements of CCITT Recommendation G.721 and ANSI Tl.301. It also meets
ANSI Tl.303 and CCITT Recommendation G.723 for 24 kbps ADPCM operation,
and the 16 kbps ADPCM standard, CCITT Recommendation G.726. This device
also meets the PCM conformance specification of the CCITT G.714 Recommendation.
•
•
•
•
•
•
•
•
•
•
•
•
•
•

Single 2.7 to 5.25 V Power Supply
Typical 3 V Power Dissipation of 60 mW, Power Down of 151lW
Differential Analog Circuit Design for Lowest Noise
Complete Mu-Law and A-Law Companding PCM Codec-Filter
ADPCM Transcoder for 64, 32, 24, and 16 kbps data rates
Universal Programmable Dual Tone Generator
Programmable Transmit Gain, Receive Gain, and Sidetone Gain
Low Noise, High Gain, Three Terminal Input Operational Amplifier for
Microphone Interface
Push-Pull, 300 n Power Drivers with External Gain Adjust for Receiver
Interface
Push-Pull, 300 n Auxiliary Output Drivers for Ringer Interface
Voltage Regulated Charge Pump to Power the Analog Circuitry in Low Voltage
Applications
Receive Noise Burst Detect Algorithm
Order Complete Document as MC145540/D
Device Supported by MC145537EVK ADPCM Codec Evaluation Kit

PSUFFIX
PLASTIC DIP
CASE 710

DWSUFFIX
28

SOG
CASE 751F

ORDERING INFORMATION
MCI45540

SUFFIX DENOTES

E :w

Plastic DIP
SOG Package

PIN ASSIGNMENT

~

TG

I

TI-

r2

27 ~ FSR

TI+

l 3

26

VAG

r 4

1-

RO l 5

28

VDD

P BClKR

25 ~ DR

24 ~ Cl+

AXO-

6

23

AXO+

7

22

~

Cl-

VOSP

8

P VSS
21 P SPC

VEXT

9

20

PI

10

19

PO-

II

18

FST

PO+

12

17

SCP Rx

POI/RESET

13

16

SCP Tx

SCPEN

14

15

SCPClK

~
~

OT
BClKT

This document contains inlonnation on a product under development. Motorola reserves the right to change or discontinue this product without notice.

MC145540

2-890

MOTOROLA COMMUNICATIONS DEVICE DATA

BLOCK DIAGRAM

PO+

CODEC·FllTER

.-1-1---<

DR
DSP

POPI . - H - - - - - '
RO

ADPCM
TRANSCODER,
RECEIVE GAIN
AND
DUAL TONE
GENERATOR

FSR
BClKR
BClKT
FST

AXO- .-1-+---;;'1
DT

,-<:>+-O-....J

AXO+

TG

VDSP

.-1-1----,

TITI+

VDD

SEQUENCE!
CONTROL

SPC

VSS

PIN DESCRIPTIONS
POWER SUPPLY PINS
VSS
Negative Power Supply (Pin 22)
This is the most negative power supply and is typically
connected to 0 V.
VEXT
External Power Supply Input (Pin 9)
This pOl'@r supply input pin must be between 2.70 and
5.25 V. Internally, it is connected to the input of the VDSP
voltage regulator, the 5 V regulated charge pump, and all
digital 1/0 including the Serial Control Port and the ADPCM
Serial Data Port. This pin is also connected to the analog
output drivers (PO+, PO-, AXO+, and AXO-). This pin
should be decoupled to VSS with a 0.1 ~F ceramic capacitor.
This pin is internally connected to the VDD and VDSP pins
when the device is powered down.
VOSP
Oigital Signal Processor Power Supply Output (Pin 8)
This pin is connected to the output of the on·chip VDSP
voltage regulator which supplies the positive voltage to the
DSP circuitry and to the other digital blocks of the ADPCM
Codec. This pin should be decoupled to VSS with a 0.1 ~F
ceramic capacitor. This pin cannot be used for powering
external loads. This pin is internally connected to the VEXT
pin during power down to retain memory.

MOTOROLA COMMUNICATIONS DEVICE DATA

VOO
Positive Power Supply Input/Output (Pin 28)
This is the positive output of the on-Chip voltage regulated
charge pump and the positive power supply input to the analog
sections of the device. Depending on the supply voltage
available, this pin can function in one of two different operating
modes:
1. When VEXT is supplied from a regulated 5 V (±5%) power
supply, VDD is an input and should be externally connected to VEXT. Charge pump capacitor C1 should not
be used and the charge pump should be disabled in BRO
(b2). In this case VEXT and VDD can share the same
0.1 ~F ceramic decoupling capacitor to VSS.
2. When VEXT is supplied from 2.70 to 5.25 V, such as battery powered applications, the charge pump should be
used. In this case, VDD is the output of the on-chip voltage
regulated charge pump and must not be connected to
VEXT. VDD should be decoupled to VSS with a 1.0 IlF
ceramic capacitor. This pin cannot be used for powering
external loads in this operating mode. This pin is internally
connected to the VEXT pin when the charge pump is
turned off or the device is powered down.
VAG
Analog Ground Output (Pin 4)
This output pin provides a mid-supply analog ground
regulated to 2.4 V. All analog signal processing within this
device is referenced to this pin. This pin should be decoupled

MC145540
2-891

to VSS with a 0.01 to 0.1 ~F ceramic capacitor. If the audio
signals to be processed are referenced to VSS, then special
precautions must be utilized to avoid noise between VSS and
the VAG pin. Refer to .the applications information in this
document for more information. The VAG pin becomes high
impedance when in analog power-down mode.
C1-,C1+
Charge Pump Capacitor Pins (Pin 23 And 24)
These are the capacitor connections to the internal voltage
regulated charge pump that generates the VDD supply
voltage. A 0.1 ~F capacitor should be placed between these
pins. Note that if an external VDD is supplied, this capacitor
should not be in the circuit.
ANALOG INTERFACE PINS
TG
Transmit Gain (Pin 1)
This is the output of the transmit gain setting operational
amplifier and the input to the transmit band-pass filter. This
op amp is capable of driving a 2 kO load to the VAG pin.
When TI- and TI+ are connected to VDD, the TG op amp
is powered down and the TG pin becomes a high-impedance
input to the transmit filter. All signals at this pin are referenced
to the VAG pin. This pin is high impedance when the device
is in the analog power-down mode. This op amp is powered
by the VDD pin.
TITransmit Analog Input (Inverting) (Pin 2)
This is the inverting input of the transmit gain setting
operational amplifier. Gain setting resistors are usually
connected from this pin to TG and from this pin to the analog
signal source. The common mode range of the TI + and TIpins is from 1.0 V, to VDD - 2 V. Connecting this pin and TI +
(Pin 3) to VDD will place this amplifier's output (TG) in a
high-impedance state, thus allowing the TG pin to serve as
a high-impedance input to the transmit filter.
TI+
Transmit Analog Input (Non-inverting; Pin 3)
This is the non-inverting input of the transmit input gain
setting operational amplifier. This pin accommodates a differential to single-ended circuit for the input gain setting op amp.
This allows input signals that are referenced to the VSS pin
to be level shifted to the VAG pin with minimum noise. This
pin may be connected to the VAG pin for an inverting amplifier
configuration if the input signal is already referenced to the
VAG pin. The common mode range of the TI + and TI- pins
is from 1.0 V to VDD - 2 V. Connecting this pin and TI- (Pin
2) to VDD will place this amplifier's output (TG) in a highimpedance state, thus allowing the TG pin to serve as a
high-impedance input to the transmit filter.
RO
Receive Analog Output (Pin 5)
This is the non-inverting output of the receive smoothing
filter from the digital-to-analog converter. This output is
capable of driving a 2 kO load to 1.575 V peak referenced
to the VAG pin. This pin may be dc referenced to either the
VAG pin or a voltage of half of VEXT by BR2 (b7). This pin
is high impedance when the device is in the analog
power-down mode. This pin is high impedance except when
it is enabled for analog signal output.

MC145540
2-892

AXOAuxiliary Audio Power Output (Inverting) (Pin 6)
This is the inverting output of the auxiliary power output
drivers. The Auxiliary Power Driver is capable of differentially
driving a 300 0 load. This power amplifier is powered from
VEXT and its output can swing to within 0.5 VofVSS andVEXT.
This pin may be dc referenced to either the VAG pin or a
voltage of half of VEXT by BR2 (b7). This pin is high
impedance in power down. This pin is high impedance except
when it is enabled for analog signal output.
AXO+
Auxiliary Audio Power Output (Non-inverting; Pin 7)
This is the non-inverting output of the auxiliary power
output drivers. The Auxiliary Power Driver is capable of
differentially driving a 300 0 load. This power amplifier is
powered from VEXT and its output can swing to within 0.5
V of VSS and VEXT. This pin may be dc referenced to either
the VAG pin or a voltage of half of VEXT by BR2 (b7). This
pin is high impedance in power down. This pin is high
impedance except when it is enabled for analog signal output.
PI
Power Amplifier Input (Pin 10)
This is the inverting input to the PO- amplifier. The
non-inverting input to the PO- amplifier may be dc
referenced to either the VAG pin or a voltage of half of VEXT
by BR2 (b7). The PI and PO- pins are used with external
resistors in an inverting op amp gain circuit to set the gain
of the PO+ and PO- push-pull power amplifier outputs.
Connecting PI to VDD will power down these amplifiers and
the PO+ and PO- outputs will be high impedance.
POPower Amplifier Output (Inverting) (Pin 11)
This is the inverting power amplifier output that is used to
provide a feedback signal to the PI pin to set the gain of the
push-pull power amplifier outputs. This power amplifier is
powered from VEXT and its output can swing to within 0.5
V of VSS and VEXT. This should be noted when setting the
gain of this amplifier. This pin is capable of driving a 300 0
load to PO+ independent of supply voltage. The PO+ and
PO - outputs are differential (push-pull) and capable of
driving a 300 0 load to 3.15 V peak, which is 6.3-V
peak-to-peak when a nominal 5 V power supply is used for
VEXT. The bias voltage and Signal reference for this pin may
be dc referenced to either the VAG pin or a voltage of half
of VEXT by BR2 (b7). Lowimpedance loads must be between
PO+ and PO-. This pin is high impedance when the device
is in the analog power-down mode. This pin is high
impedance except when it is enabled for analog signal output.
PO+
Power Amplifier Output (Non-inverting) (Pin 12)
This is the non-inverting power amplifier output that is an
inverted version of the signal at PO-. This power amplifier
is powered from VEXT and its output can swing to within 0.5
V of VSS and VEXT. This pin is capable of driving a 300 0
load to PO-. This pin may be dc referenced to either the VAG
pin or a voltage of half of VEXT by BR2 (b7). This pin is high
impedance when the device is in the analog power-down
mode. See PI and PO- for more information. This pin is high
impedance except when it is enabled for analog signal output.

MOTOROLA COMMUNICATIONS DEVICE DATA

ADPCMlPCM SERIAL INTERFACE PINS

SERIAL CONTROL PORT INTERFACE PINS

FST
Frame Sync, Transmit (Pin 18)
When used in the Long Frame Sync or Short Frame Sync
mode, this pin accepts an 8 kHz clock that synchronizes the
output of the serial ADPCM data at the DT pin.

POI/RESET
Power-Down Input/Reset (Pin 13)
A logic 0 applied to this input forces the device into a
low-power dissipation mode. A rising edge on this pin causes
power to be restored and the ADPCM Reset state (specified
in the standards) to be forced.

BCLKT
Bit Clock, Transmit (Pin 19)
When used in the Long Frame Sync or Short Frame Sync
mode, this pin accepts any bit clock frequency from 64 to 5120
kHz.
DT
Data, Transmit (Pin 20)
This pin is controlled by FST and BCLKT and is high
impedance except when outputting data.
SPC
Signal Processor Clock (Pin 21)
This input requires a 20.48 or 20.736 MHz clock signal that
is used as the DSP engine master clock. Internally the device
divides down this clockto generate the 256 kHz clock required
by the PCM Codec. (This clock may be optionally specified
for higher frequencies; contact the factory for more information.)
DR
Data, Receive (Pin 25)
ADPCM data to be decoded are applied to this input, which
operates synchronously with FSR and BCLKR to enter the
data in a serial format.
BCLKR
Bit Clock, Receive (Pin 26)
When used in the Long Frame Sync or Short Frame Sync
mode, this pin accepts any bit clock frequency from 64 to
5120 kHz. This pin may be used for applying an external
256 kHz clock for sequencing the analog signal processing
functions of this device. This is selected by the SCP port at
BRO (b7).
FSR
Frame Sync, Receive (Pin 27)
When used in the Long Frame Sync or Short Frame Sync
mode, this pin accepts an 8 kHz clock that synchronizes the
input of the serial ADPCM data at the DR pin. FSR can
operate asynchronous to FST in the Long Frame Sync or
Short Frame Sync mode.

MOTOROLA COMMUNICATIONS DEVICE DATA

SCPEN
Serial Control Port Enable Input (Pin 14)
This pin, when held low, selects the Serial Control Port
(SCP) for the transfer of control and status information into
and out of the MC145540 ADPCM Codec. This pin should
be held low for a total of 16 periods of the SCPCLK signal
in order for information to be transferred into or out of the
MC145540 ADPCM Codec. The timing relationship between
SCPEN and SCPCLK is shown in Figures 6 through 9.
SCPCLK
Serial Control Port Clock Input (Pin 15)
This input to the device is used for controlling the rate of
transfer of data into and out of the SCP Interface. Data are
clocked into the MC145540 ADPCM Codec from SCP Rx on
rising edges of SCPCLK. Data are shifted out of the device
on SCP Tx on falling edges of SCPCLK. SCPCLK can be
any frequency from 0 to 4.096 MHz. An SCP transaction
takes place when SCPEN is brought low. Note that SCPCLK
is ignored when SCPEN is high ( i.e., it may be continuous
or it can operate in a burst mode).
SCP Tx
Serial Control Port Transmit Output (Pin 16)
SCP Tx is used to output control and status information
from the MC145540 ADPCM Codec. Data are shifted out of
SCP Tx on the falling edges of SCPCLK, most significant
bit first.
SCP Rx
Serial Control Port Receive Input (Pin 17)
SCP Rx is used to input control and status information to
the MC145540 ADPCM Codec. Data are shifted into the
device on rising edges of SCPCLK. SCP Rx is ignored when
data are being shifted out of SCP Tx or when SCPEN is high.

MC145540

2-893

ADPCM/PCM SERIAL INTERFACE TIMING DIAGRAMS

FST(FSR)
BCLKT (BCLKR)

DT
DR

I

DON'T CARE

I I 1 I 1 1-1- - - - - - - - - I I I I I I I I

11 12 3 14

5

6

7

11

5

6

7

2

3

4

8

DON'T CARE

8

Figure 1. Long Frame Sync (64 kbps PCM Data Timing)

FST(FSR)
BCLKT (BCLKR)

DR

I
I I I I I

1 21 314t-1- - - - - - - - - - - - - - -

DT

I

DON'T CARE

2

3

4

DCN'TCARE

Figure 2. Long Frame Sync (32 kbps ADPCM Data Timing)

FST (FSR)
BCLKT (BCLKR)

2131-1- - - - - - - - - - - - - - - - -

DT
DR

I

DON'T CAREl 1

2

I I
3

DON'T CARE

Figure 3. Long Frame Sync (24 kbps ADPCM Data Timing)

FST (FSR)

--~~~---------------------------

BCLKT (BCLKR)

DT

------~~r------------------------------------------------

DR

I

DON'T CAREl 1

I I
2

DON'T CARE

Figure 4. Long Frame Sync (16 kbps ADPCM Data Timing)

MC145540

2-894

MOTOROLA COMMUNICATIONS DEVICE DATA

FST(FSR)
BClKT (BClKR)

OT

----111

OR

I

213 1411-- - - - - - - - - - - - - -

OON'T CARElli 2

I I I
3

OON'TCARE

4

Figure 5. Short Frame Sync (32 kbps ADPCM Data Timing)

SCPEN

~~_ _ _ _ _~~~~_ _ _ _ _ _ _~~

SCPClK

I I I I

SCPRx
SCPTx

A3

A2

Al

AO

~\~\C~ 071 061

osl

I ®

04 1 03 1 02 1 01

00

-------------HIGHIMPEOANCE - - - - - - - - - - - - - - -

Figure 6. SCP Byte Register Write Operation Using Double 8-Bit Transfer

~L-_ _ _ _- - . I

55
L...--_ _ _ _ _ _ _ _

----'~

SCPClK
SCPRx
SCPTx

RIW
- - - - HIGH IMPEOANCE - - - - - - 1 1 071 061

osl

041 031 021 01

I

00

~

Figure 7. SCP Byte Register Read Operation Using Double 8-Bit Transfer

SCPEN

~~_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _..J
.......,.......~~......~,...........

SCPClK

SCP Rx
SCPTx

I

A31 A21 Al

I I
AO

071 061

osl

041 031 021 01

I

00

~~~~

- - - - - - - - - - - HIGHIMPEOANCE - - - - - - - - - - - - - - - - - -

Figure 8. SCP Byte Register Write Operation Using Single 16-Bit Transft.

MOTOROLA COMMUNICATIONS DEVICE DATA

MC145540
2-895

SCPEN

----,~__________________________________________~

SCPCLK
SCPRx
SCPTx

RIW

- - - HIGH IMPEDANCE - - - - - - I I D71 061 DSI D41 D31 D21 D1 I DO 1-1- - - - Figure 9. SCP Byte Register Read Operation Using Single 16-Bit Transfer

SERIAL CONTROL PORT (SCP) INTERFACE
The MC145540 is equipped with an industry standard Serial
Control Port (SCP) Interface. The SCP is used by an extemal
controller, such as an M68HC05 family microcontroller, to
communicate with the MC145540 ADPCM Codec.
The SCP is a full·duplex, four·wire interface used to pass
control and status information to and from the ADPCM Codec.
The SCP Interface consists of a transmit output, a receive
input, a data clOCk, and an enable signal. These device pins
are known as SCP Tx, SCP Rx, SCPCLK, and SCPEN,
respectively. The SCPCLK determines the rate of exchange
of data in both the transmit and receive directions, and the
SCPEN signal governs when this exchange is to take place.
The operation and configuration of the ADPCM Codec is
controlled by setting the state of the control and status
registers within the MC145540 and then monitoring these
control and status registers. The control and status registers
reside in sixteen 8·bit wide Byte Registers, BRO-BR15. A
complete register map can be found in the Serial Control Port
Registers section.
BYTE REGISTER OPERATIONS
The sixteen Byte Registers are addressed by addressing
a four·bit byte register address (A3:AO) as shown in Figures
6 and 7. A second 8·bit operation transfers the. data word
(D7:DO). Alternatively, these registers can be accessed with
a Single 16·bit operation as shown in Figures 8 and 9.

ADPCM CODEC DEVICE DESCRIPTION
The MCl45540 is a single channel MU-Law or A·Law
companding PCM codec·filter with an ADPCM encoder/decoder operating on a single voltage power supply from 2.7
to 5.25 V.
The MC145540 ADPCM Codec is a complete solution for
digitizing and reconstructing voice in compliance with cCln
G.714, G.721, G.723, G.726 and ANSI T1.301 and Tl.303
for 64,32,24, and 16 kbps. This device satisfies the need
for high quality, low power, low data rate voice transmission,
and storage applications and is offered in 28·pin Plastic Dip
and SOG packages.
Referring to Figure 10, the main functional blocks of the

MC145540
2-896

MC145540 are the switched capacitor technology PCM
codec-filter, the DSP based ADPCM encoder/decoder, and
the voltage regulated charge pump. As an introduction to the
functionality olthe ADPCM Codec, a basic description ofthese
functional blocks follows.
PCM CODEC-FILTER BLOCK DESCRIPTION
A PCM codec·filter is a device used for digitizing and
reconstructing the human voice. These devices were
developed primarily for the telephone network to facilitate
voice switching and transmission. Once the voice is digitized,
it may be switched by digital switching methods or transmitted
long distance (Tl, microwave, fiber optics, satellites, etc.)
without degradation. The name codec is an acronym from
·COder" for the analog-to·dig~al converter (ADC) used to
digitize voice, and "DECoder" for the digital·to-analog
converter (DAC) used for reconstructing voice. A codec is a
single device that does both the ADC and DAC conversions.
To digitize voice intelligibly requires a signal to distortion
of about 30 dB for a dynamic range of about 40 dB. This may
be accomplished with a linear 13·bit ADC and DAC, but will
far exceed the required signal to distortion at amplitudes
greater than 40 dB below the peak amplitude. This excess
performance is at the expense of bits of data per sample. Two
methods of data reduction are implemented by compressing
the 13-bit linear scheme to companded 8·bit schemes. These
companding schemes follow a segmented or "piecewise·
linear" curve formatted as sign bit, three chord bits, and four
step bits. For a given chord, all 16 of the steps have the same
voltage weighting.· As the voltage of the analog input
increases, the four step bits increment and carry to the three
chord bits, which increment. When the chord bits increment,
the step bits double their voltage weighting. This results in an
effective resolution of six bits (sign + chord + four step bits)
across a 42·dB dynamic range (seven chords above 0, by 6
dB per chord). There are two companding schemes used:
Mu·255 Law specifically in North America and A·Law
specifically in Europe. These companding schemes are
accepted world wide.

MOTOROLA COMMUNICATIONS DEVICE DATA

s:

@
:0

o

s;:

()

o

s:
s:

ANALOG INTERFACE
AND
CODEC·FILTER

PO+

c

z

o
~

o
z

»~

DR

INPUT SHIFT
REGISTER

FSR

PI

m

o

ADPCM SERIAL
DATA PORT

PO-

en
o

<
om

DIGITAL SIGNAL PROCESSOR

DAC

RO

ca·e"11

AXO-

...p(;

AXO+

»
c

VAG

()

5:

TG

o

8.

TI-

III

TI+

1

I"

,I

FSRLENGTH
CIRCUITRY

I.. BCLKR

~

rl

2.4·V
REFERENCE

-a

UNIVERSAL L - . .
DUAL TONE ,--------.GENERATOR

I..BCLKT
FSTLENGTH
CIRCUITRY

SIDETOI
GAIN

~~

til

COMPANDED
TO LINEAR

OUTPUT SHIFT
REGISTER

~

III

DT •

6"

n

~

c
mea
iil
3

POWER SUPPLY MANAGEMENT
SUBSYSTEM
VDD

5V
REGULATED
CHARGE PUMP
FOR CODEC·FILTER
ANALOG
PROCESSING

I-

3V
REGULATOR FOR
DIGITAL SIGNAL
PROCESSOR

SEQUENCE
AND
CONTROL

SERIAL CONTROL PORT

~

I I i i
:s::

...o

N~

,01

m~

..... 0

Cl +

Cl-

VSS

VEXT

~

i

i

i

~

VDSP

SCPEN

SCPCLK

SCP Ax

SCP Tx

i
PDI/RESET

~

In a sampling environment, Nyquist theory says that to
properly sample a continuous signal, it must be sampled at
a frequency higher than twice the signal's highest frequency
component. Voice contains spectral energy above 3 kHz, but
its absence is not detrimental to intelligibility. To reduce the
digital data rate, which is proportional to the sampling rate,
a sample rate of 8 kHz was adopted, consistent with a
bandwidth of 3 kHz. This sampling requires a low-pass filter
to limit the high frequency energy above 3 kHz from distorting
the inband signal. The telephone line is also subject to 50/60
Hz power line coupling, which must be attenuated from the
signal by a high-pass filter before the analog-to-digital
converter.
The digital-to-analog conversion process reconstructs a
staircase version of the desired inband signal which has
spectral images of the inband signal modulated about the
sample frequency and its harmonics. These spectral Images
are called aliasing components which need to be attenuated
to obtain the desired signal. The low-pass filter used to
attenuate these aliasing components is typically called a
reconstruction or smoothing filter.
The MC145540 ADPCM Codec incorporates this codec
function as one of its main functional blocks.
ADPCM TRANSCODER BLOCK DESCRIPTION
An Adaptive Differential PCM (ADPCM) transcoder is used
to reduce the data rate required to transmit a PCM encoded
voice signal while maintaining the voice fidelity and intelligibility of the PCM signal.
The ADPCM transcoder is used on both Mu-Law and A-Law
64 kbps data streams which represent either voice or voice
band data signals that have been digitized by a PCM
codec-filter. The PCM to ADPCM encoder section of this
transcoder has a type of linear predicting digital filter which
is trying to predict the next PCM sample based on the previous
history of the PCM samples. The ADPCM to PCM decoder
section implements an identical linear predicting digital filter.
The error or difference between the predicted and the true
PCM input value is the information that is sent from the
encoder to the decoder as an ADPCM word. The characteristics ofthis ADPCM word include the number of quantized steps
(this determines the number of bits per ADPCM word) and
the actual meaning of this word is a function of the predictor's
output value, the error signal and the statistics of the history
of PCM words. The term "adaptive" applies to the transfer
function of the filter that generates the ADPCM word which
adapts to the statistics of the signals presented to it. This
means that an ADPCM word "3" does not have the same
absolute error voltage weighting for the analog signal when
the channel is quiet as it does when the channel is processing
a speech signal. The ADPCM to PCM decoder section has
a reciprocating filter function which interprets the ADPCM
word for proper reconstruction of the PCM sample.
The adaptive characteristics of the ADPCM algorithm make
it difficult to analyze and quantify the performance of the
ADPCM code sequence. The 32 kbps algorithm was
optimized for both voice and moderate speed modems
( s 4800 baud). This optimization includes that the algorithm
supports the voice frequency band of 300-3400 Hz with
minimal degradation for signal-to-distortion, gain-versus-Ievel, idle channel noise; and other analog transmission
performance. This algorithm has also been subjected to
audibility testing with many languages for Mean Opinion Score
(MOS) ratings and performed well when compared to 64.kbps
PCM .. The standards committees have specified multiple

MC145540
2-898

16000 word test vectors for the encoder and for the decoder
to verify compliance. To run these test vectors, the device must
be initialized to the reference state by resetting the device.
In contrast to 64-kbps PCM, the ADPCM words appear as
random bit activity on an oscilloscope display whether the
audio channel is processing speech or a typical PCM idle
channel with nominal bit activity. The ADPCM algorithm does
not support dc signals with the exception of digital quiet, which
will result in all ones in the ADPCM channel. All digital
processing is performed on 13-bit linearizations of the 8-bit
PCM companded words, whether the words are Mu-Law or
A-Law. This allows an ADPCM channel to be intelligibly
decoded into a Mu-Law PCM sequence or an A-Law PCM
sequence irrespective of whether it was originally digitized as
Mu-Law or A-Law. There will be additional quantizing
degradation if the companding scheme is changed because
the ADPCM algorithm is trying to reconstruct the original 13-bit
linear codes, which included companding quantization.
CHARGE PUMP
The charge pump is the functional block that allows the
analog signal processing circuitry olthe MC145540 to operate
with a power supply voltage as low as 2.7 V. This analog signal
processing circuitry includes the PCM codec-filter function,
the transmit trim gain, the receive trim gain, the sidetone gain
control, and the transmit input operational amplifier. This
circuitry does not dissipate much current but it does require
a nominal voltage of 5 V for the VDD power supply.
The charge pump block is a regulated voltage doubler which
takes twice the current it supplies from the voltage applied
to the VEXT power supply pin which may range from 2.7 to
5.25 V and generates the required 5 VVDD supply. Thecharge
pump block receives as inputs the VEXT supply voltage, the
same 256 kHz clock that sequences the analog signal
processing circuitry, and the Charge Pump Enable signal from
the SCP block. It also makes use of the capacitor connected
to the C1 + and C1- pins and the decoupling capaCitor
connected to the VDD pin.

FUNCTIONAL DESCRIPTION
POWER SUPPLY CONFIGURATION
Analog Signal Processing Power Supply
All analog signal processing is powered by the VDD pin
at 5 V. This voltage may be applied directly to the VDD pin
or 5 V may be obtained by the on-chip 5 V regulated charge
pump which is powered from the VEXT pin. The VEXT pin is
the main positive power supply pin for this device.
For applications that are not 5 V regulated, the on-chip 5 V
regulated charge pump may be turned on and C1 will be
required. VDD will require a 1.0 IlF decoupling capacitor to
filter the voltage spikes of the charge pump. This allows the
VEXT power supply to be from 2.7 to 5.25 V. This mode of
operation is intended for hand held applications where three
NiCad cells or three dry cells would be the power supply.
The on-chip 5 V regulated charge pump is a single stage
charge pump that effectively series regulates the amount of
voltage it generates and internally applies this regulated
voltage to the VDD pin. This 5 V voltage is developed by
connecting the external 0.1 IlF capacitor (C1) between the
VEXT power supply pin and the power supply ground pin,
VSS. This puts a charge of as much as 2.7 V on C1. The
charge pump circuitry then connects the negative lead of C1
to the VEXT, pin which sums the voltage of C1 with the voltage
at VEXT for a minimum potential voltage of 5.4 V. The charge

MOTOROLA COMMUNICATIONS DEVICE DATA

voltage on C1 is regulated such that the summing of voltages
is regulated to 5 V. This limits all of the voltages on the device
to safe levels for this IC fabrication technology. This charge
pumped voltage is then stored on the 1.0 I1F capacitor
connected at VDD and VSS, which filters and serves as a
reservoir for power. The clock period for this charge pump
is the same 256 kHz as the analog sequencing clock,
minimizing noise problems.
For applications with a regulated 5 V (±5%) power supply,
the VDD pin and the VEXT pin are connected to the 5 V power
supply. These pins may share one decoupling capacitor in
this configuration as a function of extemal noise on the power
supply. The on-chip, 5 V regulated charge pump should be
turned off via the SCP port at register O. The external
capacitor (C1) should not be populated for these applications.
Digital Signal Processing Power Supply
This device has an on-chip series regulator which limits
the voltage of the Digital Signal Processing (DSP) circuitry
to about 3 V. This reduces the maximum power dissipation
of this circuitry. From the VEXT power supply pin, the DSP
circuitry appears as a constant current load instead of a
resistive (CV2/2) load for a constant clock frequency. This
series regulator is designed to have a low drop-out voltage,
which allows the DSP circuitry to work when the VEXTvoltage
is as low as 2.7 V. The output of this regulator is brought out
to the VDSP pin for a 0.1 I1F decoupling capacitor. This
regulator is not designed to power any loads external to the
device.
ANALOG INTERFACE AND SIGNAL PATH
Transmit Analog
The transmit analog portion of this device includes a lownoise, three terminal operational amplifier capable of driving
a 2 kQ load. This op amp has inputs of TI + and TI- and its
output is TG. This op amp is intended to be configured in an
inverting gain circuil. The analog signal may be applied directly to the TG pin if this transmit op amp is independently
powered down. Power down may be achieved by connecting
both the TI+ and TI- inputs to the VDD pin. The TG pin becomes high impedance when the transmit op amp is powered
down. The TG pin is internally connected to a time continuous
three-pole anti-aliasing pre-filter. This pre-filter incorporates
a two-pole Butterworth active low-pass filter, followed by a
single passive pole. This pre-filter is followed by a singleended to differential converter that is clocked at 512 kHz. All
subsequent analog processing utilizes fully differential circuitry. The output of the differential converter is followed by the
transmit trim gain stage. This stage is intended to compensate for gain tolerances of external components such as
microphones. The amount of gain control is 0-7 dB in 1 dB
steps. This stage only accommodates positive gain because
the maximum signal levels of the output of the input op amp
are the same as the transmit filter and ADC, which should
nominally be next to the clip levels of this device's circuitry.
Any requirement for attenuation of the output of the input op
amp would mean that it is being overdriven. The gain is programmed via the SCP port in BR1 (b2:bO). The next section
is a fully-differential, 5-pole switched-capacitor low-pass filter
with a 3.4 kHz frequency cutoff. After this filter is a 3-pole
switched-capacitor high-pass filter having a cutoff frequency
of about 200 Hz. This high-pass stage has a transmission
zero at dc that eliminates any dc coming from the analog input
or from accumulated op amp offsets in the preceding filter
stages. (This high-pass filter may be removed from the signal

MOTOROLA COMMUNICATIONS DEVICE DATA

path under control of the SCP port BRS (b4).) The last stage
of the high-pass filter is an autozeroed sample and hold
amplifier.
One bandgap voltage reference generator and digital-toanalog converter (DAC) are shared by the transmit and
receive sections. The autozeroed, switched-capacitor bandgap reference generates precise positive and negative
reference voltages that are virtually independent of temperature and power supply voltage. A binary-weighted capacitor
array (CDAC) forms the chords of the companding structure,
while a resistor string (RDAC) implements the linear steps
within each chord. The encode process uses the DAC, the
voltage reference, and a frame-by-frame autozeroed comparator to implement a successive-approximation analog-todigital conversion (ADC) algorithm. All of the analog circuitry
involved in the data conversion (the voltage reference, RDAC,
CDAC, and comparator) are implemented with a differential
architecture.
The nonlinear companded Mu-Law transfer curve of the
ADC may be changed to S-bit linear by BRS (b5).
The input to the ADC is normally connected to the output
of the transmit filter section, but may be switched to measure
the voltage at the VEXT pin for battery voltage monitoring.
This is selected by the I/O Mode in BRO (b4:b3). In this mode,
the ADC is programmed to output a linear S-bit PCM word
for the voltage at VEXT which is intended to be read in BR9
(b7:bO). The data formattor the ADC output is a "Don't Care"
for the sign bit and seven magnitude bits. The scaling for
the ADC is for 6.3 V at VEXT equals full scale (BIN X111
1111). The ADPCM algorithm does not support dc signals.
Transmit Digital
The Digital Signal Processor (DSP) section of this device
is a custom designed, interrupt driven, microcoded machine
optimized for implementing the ADPCM algorithms. In the full
duplex speech mode, the DSP services one encode interrupt
and one decode interruptperframe (125 I1s). Theencode algorithm (i.e., 16 kbps, 24 kbps, or 32 kbps ADPCM, or 64 kbps
PCM) is determined by the length of the transmit output enable
at the FST pin. The length of the FST enable measured in
transmit data clock (BCLKT) cycles tells the device which encoding rate to use. This enable length information is used by
the encoder each frame. The transmit ADPCM word corresponding to this request will be computed during the next
frame and will be available a total of two frames after being
requested. This transmit enable length information can be
delayed by the device an additional fourframes corresponding
to a total of six frames. These six frames of delay allow the
device to be clocked with the same clocks for both transmit
(encode) and receive (decode), and to be frame aligned for
applications that require every sixth frame signaling. It is important to note that the enable length information is delayed
and not the actual ADPCM (PCM) sample word. The amount
of delay for the FST enable length is controlled in BR7 (b5).
If the FST enable goes low before the falling edge of BCLKT
during the last bit of the ADPCM word, the digital data output
circuitry counts BCLKT cycles to keep the data output (DT
pin) low impedance for the duration of the ADPCM data word
(2,3,4, or S BCLKT cycles) minus one half of a BCLKT cycle.
Receive
Receive Digital
The receive digital section of this device accepts serial
ADPCM (PCM) words at the DR pin under the control of the
BCLKR and FSR pins. The FSR enable duration, measured
in BCLKR cycles, tells the device which decode algorithm (i.e.,

MC145540
2-899

16 kbps, 24 kbps, or 32 kbps ADPCM, or 64 kbps PCM) the
DSP machine should use for the word that is being received
at the DR pin. This algorithm may be changed on a frame by
frame basis.
The DSP machine receives an interrupt when an ADPCM
word has been received and is waiting to be decoded into
a PCM word. The DSP machine performs a decode and an
encode every frame when the device is operating in its full
duplex conversation mode. The DSP machine decodes the
ADPCM word according to CCITT G.726 for 32 kbps, 24
kbps, and 16 kbps. This decoding includes the correction for
the CCITT/ANSI Sync function, except when the receive
digital gain is used. The receive digital gain is anticipated to
be user adjustable gain control in handset applications where
as much as 12 dB of gain or more than 12 dB of attenuation
may be desirable. The receive digital gain is a linear multiply
performed on the 13-bit linear data before it is converted to
Mu-Law or A-Law, and is programmed via the SCP port in
BR3 (b7:bO). The decoded PCM word may be read via the
SCP port in BR10 (b7:bO).

Receive Analog Signal Processing
The receive analog signal processing section includes the
DAC described above, a sample and hold amplifier, a trim gain
stage, a 5-pole, 3400 Hz switched capacitor low-pass filter
with sinXlX correction, and a 2-pole active smoothing filter to
reduce the spectral components of the switched capacitor
filter. (The receive low-pass smoothing filter may be removed
from the signal path for the additional spectral components
for applications using the on-chip tone. generator function
described below. This low-pass filter performs the sinXlX
compensation. The receive filter is removed from the circuit
via the SCP in BR2 (b4).) The input to the smoothing filter
is the output to the receive trim gain stage. This stage is
intended to compensate for gain tolerances of external
components such as handset receivers. This stage is capable
of 0 to 7 dB of attenuation in 1-dB steps. This stage only
accommodates attenuation because the nominal signal levels
of the DAC should be next to the clip levels of this device's
circuitry and any positive gain would overdrive the outputs.
The gain is programmed via the SCP port in BR2 (b2:bO).The
output of the 2-pole active smoothing filter is buffered by an
amplifier which is output at the RO pin. This output is capable
of driving a 2 kn load to the VAG pin.
Receive Analog Output Drivers and Power Supply
The high current analog output circuitry (PO+, PO-, PI,
AXO+, AXO-) is powered by the VEXT power supply pin.
Due to the wide range of VEXT operating voltages for this
device, this Circuitry and the RO pin have a programmable
reference point of either VAG (2.4 V) or VEXT/2. In
applications where this device is powered with 5 V, it is
recommended that the dc reference for this circuitry be
programmed to VAG. This allows maximum output signals
for driving high power telephone line transformer interfaces
and loud speaker/ringers. For applications that are battery
powered, VAG pin will still be 2.4 V, but the receive analog
output circuitry will be powered from as low as 2.7 V. To
optimize the output power, this circuitry should be referenced
to one half of the battery voltage, VEXT/2. The RO pin is
powered by the. VDD pin, but its dc reference point is
programmed the same as the high current analog output
circuitry.
This device has two pairs of power amplifiers that are
connected in a push-pull configuration. These push-pull

MC145540

2-900

power driver pairs have similar drive capabilities, but have
different circuit configurations and different intended uses.
The PO+ and PO- power drivers are intended to
accommodate large gain ranges with precise adjustment by
two external resistors for applications such as driving a
telephone line or a handset receiver. The PI pin is the
inverting input to the PO- power amplifier. The non-inverting
input is internally tied to the same reference as the RO output.
This allows this amplifier to be used in an inverting gain circuit
with two external resistors. The PO + amplifier has a gain of
-1, and is internally connected to the PO- output. This
complete power amplifier circuit is a differential (push-pull)
amplifier with adjustable gain which is capable of driving a
300 Q load to +12 dBm when VEXT is 5 V. The PO+ and POoutputs are intended to drive loads differentially and not to
VSS or VAG. The PO+ and PO- power amplifiers may be
powered down independently of the rest of the chip by
connecting the PI pin to VDD or in BR2 (b5).
The other paired power driver outputs are the AXO+ and
AXO- Auxiliary outputs. These push-pull output amplifiers are
intended to drive a ringer or loud speaker with impedance as
low as 300 Q to +12 dBm when VEXT is 5 V. The AXO+
and A'X.O- outputs are intended to drive loads differentially
and nollo VSS orVAG. The AXO + and AXO-poweramplifiers
may be powered down independently of the rest of the chip
via the SCP port in BR2 (b6).
SIDETONE
The Sidetone function of this device allows a controlled
amount of the output from the transmit filter to be summed
with the output of the DAC at the input to the receive low-pass
filter. The sidetone component has gains of -8.5 dB, -10.5
dB, -12.0 dB, -13.5 dB, -15.0 dB, -18.0 dB, -21.5 dB, and
,;; -70 dB. The sidetone function is controlled by the SCP port
in BR1 (b6:b4).
UNIVERSAL TONE GENERATOR
The Universal Dual Tone Generator function supports both
the transmit and the receive sides of this device. When the
tone generator is being used, the decoder function of the DSP
circuit is disabled. The output of the tone generator is made
available to the input of the receive digital gain function for
use at the receive analog outputs. In handset applications,
this could be used for generating DTMF, distinctive ringing or
call progress feedback signals. In telephone line interface
applications, this tone generator could be used for signaling
on the line. The tone generator output is also available for the
input tothe encoder function of the DSP machine foroutputting
at the DT pin. This function is useful in handset applications
for non-network signaling such as information services,
answering machine control, etc. At the network interface side
of a cordless telephone application, this function could be used
for dialing feedback or call progress to the handset. The tone
generator function is controlled by the SCP port in BR4, BR5,
and BR7. The tone generator does not work when the device
is operated in 64 kbps mode, except when analog loopback
is enabled at BRO (b5).
POWER DOWN AND RESET
There are two methods of putting all of this device into a
low power consumption mode that makes the device
nonfunctional and consumes virtually no power. PDI/RESET
is the power down input and reset pin which, when taken low,
powers down the device. Another way to power the device
down is by the SCP port at BRO. BRO allows the analog section

MOTOROLA COMMUNICATIONS DEVICE DATA

of this device to be powered down individually andlorthe digital
section of this device to be powered down individually. When
the chip is powered down, the VAG, TG, RO, PO+, PO-,
AXO+, AXO-, DT and SCP Tx outputs are high impedance
. To return the chip to the power up state,POi/RESET must
be high and the SPC clock and the FST or the FSR frame
sync pulses must be present. The ADPCM algorithm is reset
to the CCITT initial state following the reset transition from
low to high logic states. The DT output will remain in a high
impedance state for at least two FST pulses after power up.
This device is functional after being reset for full-duplex voice
coding with the charge pump active.
SIGNAL PROCESSING CLOCK (SPC)
This is the clock that sequences the DSP circuit. This clock
may be asynchronous to all other functions of this device.
Clock frequencies of 20.48 MHz or 20.736 MHz are
recommended. This clock is also used to drive a digitally phase
locked prescaler that is referenced to FST (8 kHz) and
automatically determines the proper divide ratio to use for
achieving the required 256 kHz internal sequencing clock for
all analog signal processing, including analog-to-digital
conversion, digital-to-analog conversion, transmit filtering,
receive filtering and analog gain functions of this device and
the charge pump.
The analog sequencing function of the SPC clock may be
eliminated by reprogramming the device to use the BCLKR
pin as the direct input for the required 256 kHz analog
sequencing clock. The 256 kHz clock applied at BCLKR must
be an integer 32 times the FST 8 kHz clock and be
approximately rising edge aligned with the FST rising edge.
This mode requires that the transmit and receive ADPCM
transfers be controlled by the BCLKT pin. This is reprogrammed via the SCP port in BRO(b7).
DIGITALVO
The MC145540 is programmable for Mu-Law or A-Law. The
timing for the PCM data transfer is independent of the
companding scheme selected. Table 1 shows the 8-bit data
word format for positive and negative zero and full scale for
both 64 kbps companding schemes (see Figures 1 through
5 for asummary and comparison olthe five PCM data interface
modes of this device).
Long Frame Sync
Long Frame Sync is the industry name for one type of
clocking format which controls the transfer of the ADPCM or
PCM data words (see Figures 1 through 4). The "Frame Sync"
or "Enable" is used for two specific synchronizing functions.
The first is to synchronize the PCM data word transfer, and
the second is to control the internal analog-to-digital and
digital-to-analog conversions. The term "Sync" refers to the
function of synchronizing the PCM data word onto or off of

the multiplexed serial PCM data bus, also known as a PCM
highway. The term "Long" comes from the duration olthe frame
sync measured in PCM data clock cycles. Long Frame Sync
timing occurs when the frame sync is used directly as the PCM
data output driver enable. This results in the PCM output going
low impedance with the rising edge of the transmit frame sync,
and remaining low impedance for the duration of the transmit
frame sync.
The implementation of Long Frame Sync for this device has
maintained industry compatibility and been optimized for external clocking simplicity. The PCM data output goes low
impedance with the rising edge of the FST pin but the MSB
olthe data is clocked out due to the logical AND olthe transmit
frame sync (FST pin) with the transmit data clock (BCLKT pin).
This allows either the rising edge of the FST enable or the
rising edge of the BCLKT data clock to be first. This implementation includes the PCM data output remaining low
impedance until the middle of the LSB (seven and a half data
clock cycles for 64 kbps PCM, three and a half data clock
cycles for 32 kbps ADPCM, etc.). This allows the frame sync
to be approximately rising edge aligned with the initiation of
the PCM data word transfer but the frame sync does not have
a precise timing requirement forthe end of the PCM data word
transfer. This prevents bus contention between similar devices on a common bus. The device recognizes Long Frame
Sync clocking when the frame sync is held high fortwo consecutive falling edges of the transmit data clock.
In the full duplex speech mode, the DSP services one
encode interrupt and one decode interrupt per frame (1251-15).
The encode algorithm (i.e., 16 kbps, 24 kbps, or 32 kbps
ADPCM or 64 kbps PCM) is determined by the length of the
transmit output enable at the FST pin. The length of the FST
enable measured in transmit data clock (BCLKT) cycles tells
the device which encoding rate to use. This enable length
information is used by the encoder each frame. The transmit
ADPCM word corresponding to this request will be computed
during the next frame and be available a total of two frames
after being requested. This transmit enable length information
can be delayed by the device an additional four frames
corresponding to a total of six frames. This six frames of delay
allows the device to be clocked with the same clocks for both
transmit (encode) and receive (decode), and to be frame
aligned for applications that require every sixth frame
signaling. It is important to note that the enable length
information is delayed and not the actual ADPCM (PCM)
sample word. The amount of delay for the FST enable length
is controlled by the SCP port at BR7 (b5). The digital data
output circuitry counts BCLKT cycles to keep the data output
(DT pin) low impedance for the duration of the ADPCM data
word (2, 3, 4, or 8 BCLKT cycles) minus one half of a BCLKT
cycle.

Table 1. PCM Full Scale and Zero Words
A-Law

Mu-Law

Chord Bits

Sign Bit

Chord Bits

Step Bits

Sign Bit

+ Full Scale
+ Zero

1

000

o 000

1

o1

1

111

1111

1

1 0 1

-Zero

0

1 1 1

1111

0

1 0 1

o1
o1

- Full Scale

0

000

o 000

0

o1

101 0

Level

MOTOROLA COMMUNICATIONS DEVICE DATA

0

0

Step Bits

1 0 1 0
0 1
0 1

MC145540
2-901

The length of the FST enable tells the DSP what encoding
algorithm to use. The transmit logic decides on each frame
sync whether it should interpret the next frame sync pulse as
a long or a Short Frame Sync. The device is designed to
prevent PCM bus contention by not allowing the PCM data
output to go low impedance for at least two frame sync cycles
aiter power is applied or when coming out of the power-down
mode.
The receive side of the device is designed to accept the
same frame sync and data clock as the transmit side and to
be able to latch its own transmit PCM data word. Thus the
PCM digital switch only needs to be able to generate one type
of frame sync for use by both transmit or receive sections of
the device.
The logical AND of the receive frame sync with the receive
data clock tells the device to start latching the serial word into
the receive data input on the falling edges of the receive data
clock. The intemal receive logic counts the receive data clock
falling edges while the FSR enable is high and transfers the
enable length and the PCM data word into intemal registers
for access by the DSP machine which also sets the DSP's
decoder interrupt.
The receive digital section of this device accepts serial
ADPCM (PCM) words at the DR pin under the control of the
BClKR and FSR pins. The FSR enable duration measured
in BClKR cycles, tells the device which decode algorithm (i.e.,
16 kbps, 24 kbps, or 32 kbps ADPCM, or 64 kbps PCM) the
DSP machine should use for the word that is being received
at the DR pin. This algorithm may be changed on a frame by
frame basis.
When the device is programmed to be in the PCM Codec
mode by BRO (4:3), the device will output and input the
complete a-bit PCM words using the long frame sync clocking
format as though the FST and FSR pulses were held high for
a data clock cycles.
The DSP machine receives an interrupt when an ADPCM
word has been received and is waiting to be decoded into a
PCM word. The DSP machine performs a decode and an
encode every frame when the device is operating in its full
duplex conversation mode. The DSP machine decodes the
ADPCM word according to CCITT G. 726 for 32 kbps, 24 kbps,
and 16 kbps.
Short Frame Sync
Short Frame Sync is the industry name for this type of
clocking format which controls the transfer of the ADPCM data
words (see Figure 5). This device uses short frame sync timing
for 32 kbps ADPCM only. The "Frame Sync" or "Enable" is
used for two specific synchronizing functions. The first is to

MC145540
2-902

synchronize the ADPCM data word transfer, and the second
is to control the internal analog to digital and digital to analog
conversions. The term "Sync" refers to the function of
synchronizing the ADPCM data word onto or off of the
multiplexed serial ADPCM data bus, also known as a PCM
highway. The term "Short" comes from the duration of the
frame sync measured in PCM data clock cycles. Short Frame
Sync timing occurs when the frame sync is used as a
"pre-synchronization" pulse that is used to tell the intemallogic
to clock out the ADPCM data word under complete control
of the data clock. The Short Frame Sync is held high for,one
falling data clock edge. The device outputs the ADPCM data
word beginning with the following rising edge of the data clock.
This results in the ADPCM output going low impedance with
the rising edge of the transmit data clock, and remaining low
impedance until the middle of the'lSB (three and a half PCM
data clock cycles).
The device recognizes Short Frame Sync clocking when
the frame sync is held high for one and only one falling edge
of the transmit data clock. The transmit logic decides on each
frame sync whether it should interpret the next frame sync
pulse as a long or a Short Frame Sync. It is not recommended
to switch between long Frame Sync and Short Frame Sync
clocking without going through a power down cycle due to bus
contention problems. The device is designed to prevent PCM
bus contention by not allowing the ADPCM data output to go
low impedance for at least two frame sync cycles after power
is applied or when coming out of a powered down mode.
The receive side of the device is designed to accept the
same frame sync and data clock as the transmit side and to
be able to latch its own transmit ADPCM data word. Thus the
PCM digital switch only needs to be able to generate one type
of frame sync for use by both transmH or receive sections'of
the device.
The falling edge of the receive data clock (BClKR) latching
a high logic level at the receive frame sync (FSR) input tells
the device to start latching the 4-bit ADPCM serial word into
the receive data input on the following four falling edges of
the receive data clock. The internal receive logic counts the
receive data clock cycles and transfers the ADPCM data word
to a register for access by the DSP.
When the device is programmed to be in the PCM Codec
mode by BRO (4:3), the device will output the complete a-bit
PCM word using the short frame sync clocking format. The
a-bit PCM word will be clocked out (or in) the same way that
the 4-bit ADPCM word would be, except that the fourth bit will
be valid for the full BClKT period and the eighth bit will be
valid for only one half of the BClKT period.

MOTOROLA COMMUNICATIONS DEVICE DATA

SERIAL CONTROL PORT REGISTER MAP
The SCP register map consists of 16 byte registers. Registers BRO-BR5 and BR7 -BRl 0 provide external control of and status
olthe part. Register BR15 holds the value olthe mask number for the particular MC145540. BR6 and BRll-BR14 are not defined
and as such are presently reserved.
Table 2. Byte Register Map
Byte

b7

b6

b5

b4

b3

b2

bl

bO

BRO

Ext
256 kHz
Clk

MUlA Law
Select

Analog
Loopback

I/O Mode
(1)

I/O Mode
(0)

Charge
Pump
Disable

Analog
Power
Down

Digital
Power
Down

BR1

Reserved

Sidetone
Gain (2)

Sidetone
Gain (1)

Sidetone
Gain (0)

Transmit
Mute

Transmit
Gain (2)

Transmit
Gain (1)

Transmit
Gain (0)

BR2

RO
Reference
Select

AXO
Enable

PO
Disable

Receive
Filter
Disable

ROMute

Analog
Receive
Gain (2)

Analog
Receive
Gain (1)

Analog
Receive
Gain (0)

BR3

Digital Rx
Gain
Enable

Digital Rx
Gain (6)

Digital Rx
Gain (5)

Digital Rx
Gain (4)

Digital Rx
Gain (3)

Digital Rx
Gain (2)

Digital Rx
Gain (1)

Digital Rx
Gain (0)

BR4

N.B. Time
I Tone
Paramo
(7)

N.B. Time
I Tone
Paramo
(6)

N.B. Time
I Tone
Paramo
(5)

N.B. Time
I Tone
Paramo
(4)

N.B.Time
I Tone
Paramo
(3)

N.B. Time
I Tone
Paramo
(2)

N.B. Time
I Tone
Paramo
(1)

N.B. Time
I Tone
Paramo
(0)

BRS

N.B.
Threshold
(7)1
Address
Paramo
(1)

N.B.
Threshold
(6)1
Address
Paramo
(0)

N.B.
Threshold
(5) I
Don't
Care

N.B.
Threshold

N.B.
Threshold
(3) I
Tone
Paramo
(11)

N.B.
Threshold
(2)1
Tone
Paramo
(10)

N.B.
Threshold
(1) I
Tone
Paramo
(9)

N.B.
Threshold

BR6

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

BR7

Tone
Paramo
Status

N.B.
Detect
Enable

216
Delay

G.7261
Motorola
16 kbps

Tone
Enable

Reserved

Tone 1
Enable

Tone 2
Enable

BRS

Software
Encoder
Reset

Software
Decoder
Reset

Linear
Cadec
Mode

Highpass
Disable

Reserved

Reserved

Reserved

Reserved

BR9

Encoder
PCM(7)

Encoder
PCM(6)

Encoder
PCM(5)

Encoder
PCM(4)

Encoder
PCM(3)

Encoder
PCM(2)

Encoder
PCM(l)

Encoder
PCM(O)

BR10

D/APCM
(7)

D/APCM
(6)

D/APCM
(5)

D/APCM
(4)

D/A PCM
(3)

D/A PCM
(2)

D/A PCM
(1)

D/A PCM
(0)

(4) I
Don't
Care

(0) I
Tone
Paramo
(8)

BR11

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

BR12

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

BR13

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

BR14

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

BR15

Reserved

Reserved

Reserved

Reserved

Mask (3)

Mask (2)

Mask (1)

Mask (0)

Note: "Setting" a bit corresponds to writing a 1 to the register and "clearing" a bit corresponds to writing a 0 to the register.

MOTOROLA COMMUNICATIONS DEVICE DATA

MC145540

2-903

APPLICATION CIRCUITS

+3V

Hn

Hn

I

681lF

-=

20kn

l.°IlF

1 kQ

HI

MIC

Hn

II

-=-

TG

1

l

l.°IlF

20kn

150n
RINGER
20kn
+3V

0.1IlF~
3kn

150Q

~

26 hBCLKR

r

25 h OR

4

RO r 5
AXO- r 6

24 b C1+
h
23 C1-

AXO+ r 7

22

r

21

8

VEXT r 9

PI r 10
PO-

RE CEIVER

28il VOO

TI+ r 3

VOSP
0.1IlF~

1·

27 h FSR

VAG

0.1IlF~

r

TI- r 2

r

11

AOPCMIN

=F O.1IlF

h VSS
h SPC

~

20.736 MHz

20 hOT

AOPCMOUT

19 h BCLKT

2.048 MHz

18 h FST

8kHz

PO+ [ 12

17b SCPRx

POI/RESET r 13

16 h SCP Tx

SCPEN

I

r

15 h SCPCLK

14
MC145540

TOMI CROCONTROLLER
SERI AL PERIPHERAL
INTER FACE PORT ANO
RESETCIRCUIT

Figure 11. MC145540 Handset Application

MC145540
2-904

MOTOROLA COMMUNICATIONS DEVICE DATA

10kQ

2B I

VDD

2

27 I

FSR

3

26

4

25 I

5

24

NC~

6

23 tl Cl-

NC~

7

22 h VSS

B

21 tl SPC

9

20 tl DT

ADPCMOUT

10

19 tl BCLKT

2.04B MHz

11

lB h FST

BkHz

12

17 tl SCP Rx

13

16 tl SCP Tx

14

15

TG.L 1·

1

10kQ

r
r
r
r

TITI+

I

O.l/lFi

VAG
RO

20kQ
O.l/lF:;;;:
+5V

RO = 600 Q

PO-

r

PO+

r
r
r

VEXT

O.l/lF~
3kQ

150=

TIP

[311 ~

PI

r
r
r

VDSP

N=0.5

PDI/RESET

I

SCPEN

RING

I

h
b

i

BCLKR
DR

O

ADPCM IN

Cl+

NC
NC
~

20.4BMHz

rr SCPCLK

MC145540

TO MICRO CO NTROLLER
SERIAL PERIP HERAL
INTERFACE PORTAND
RESETCIRCU IT

Figure 12. MC145540 Transformer Application

10kQ

TG

10kQ

O.l/lF~

2

27h FSR

3

26h BCLKR

VAG

4

25h DR

RO

r

5

24tl Cl +

AXO-

r

6

23h Cl-

AXO+

r

7

22h VSS

VDSP

r

B

21h SPC

VEXT

r

9

20h DT

PI

r

10

19h BCLKT

2.04BMHz

PO-

r

11

lBh FST

B kHz

PO+

r
r

12

17tl SCP Rx

PDI/RESET

13

16 -, SCP Tx

SCPEN

r

I

O.l/lF:;;;:

20kQ
600Q

[3 II ~
RING

N=l

T

I

±

r

r
r

O.l/lF~

RO=600Q TIP

2Bh VDD

TI+

150Q

+SV

1·

TI-

SPEA KER

20kQ

r

I

O.

ADPCM IN
NC
NC
~

lSI SCPCLK

14
MC145540

20 .736 MHz
ADPCMOUT

TOMICROCONTROLLER
SERIALP ERIPHERAL
INTERFAC E PORT AND
RESETCI RCUIT

Figure 13. MC145540 Transformer + Speaker Application

MOTOROLA COMMUNICATIONS DEVICE DATA

MC145540
2-905

MOTOROLA

-

SEMICONDUCTOR
TECHNICAL DATA

MC145542
Product Preview

CT2 Speech and Framing IC
This specification describes a device to be used in a CT2 CAl handset or a
single or multi-line base station. It provides three key functions of a CT2 system:
voice conversion from analog-to-digital, ADPCM encoding of the voice data, and
bit framing for the radio (RF) interface.
The CT2 Speech and Framing circuit (CT2SF) core is a combination of the
MC145540 ADPCM/Codec and lime Division Duplex (TDD) bit framing logic.
More details of the architecture of the ADPCM/Codec can be found in the
MC145540'data sheet.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•

Intended for both fixed and portable applications
Single 2.7 to 5.25 V Power Supply
Typical 3 V Power Dissipation of 85 mW, Power Down of 1.2 mW
Differential Analog Circuit Design for Lowest Noise
Complete Mu-Law and A-Law Companding PCM Codec-Filter
ADPCM Transcoder for 64,32,24, and 16 kbps Data Rates
Universal Programmable Dual Tone Generator
Programmable Transmit Gain, Receive Gain, and Sidetone Gain
Low Noise, High Gain, Three Terminal Input Op Amp for Microphone Interface
Push-Pull 300 n Power Drivers with External Gain Adjust for Receiver Interface
Push-Pull 300 n Auxiliary Output Drivers for Ringer Interface
Voltage Regulated Charge Pump to Power the Analog Circuitry in Low Voltage
Applications
Receive Side Noise Burst Detect Algorithm
Implements TransmiVReceive Bit Framing and D Channel Handler as Defined in
CAl spec MPT1375
Includes D Channel Handler (Parity, CRC, SYNCD, Preamble, ... )
8 Bits Parallel Control Port PCP for MCU access of Internal Registers
Timing Recovery Digital Phase-Locked Loop
FSK Switched Capacitor Filter with Programmable Attenuation
External Data Interface Enables Multiplexing of Speech and Data
64-Pin PQFP Package

This document contains Information on a product under development. Motorola reserves the right to change or dlsoontlnue this product without notice.

MC145542
2-906

REV. 1

MOTOROLA COMMUNICATIONS DEVICE DATA

MOTOROLA

-

SEMICONDUCTOR
TECHNICAL DATA

MC145554
MC145557
MC145564
MC145567

PCM Codec-Filter
The MC145554, MC145557, MC145564, and MC145567 are all per channel
PCM codec-filters. These devices perform the voice digitization and reconstruction as well as the band limiting and smoothing required for PCM systems. They
are designed to operate in both synchronous and asynchronous applications and
contain an on-chip precision voltage reference. The MC145554 (Mu-Law) and
MC145557 (A-Law) are general purpose devices that are offered in 16-pin packages. The MC145564 (Mu-Law) and MC145567 (A-Law), offered in 20-pin
packages, add the capability of analog loop-back and push-pull power amplifiers
with adjustable gain.
These devices have an input operational amplifier whose output is the input
to the encoder section. The encoder section immediately low-pass filters the analog signal with an active R-C filter to eliminate very-high-frequency noise from
being modulated down to the pass band by the switched capacitor filler. From
the active R-C filler, the analog signal is converted to a differential signal. From
this point, all analog signal processing is done differentially. This allows processing of an analog signal that is twice the amplitude allowed by a single-ended
design, which reduces the significance of noise to both the inverted and noninverted signal paths. Another advantage of this differential design is that noise
injected via the power supplies is a common-mode signal that is cancelled when
the inverted and non-inverted signals are recombined. This dramatically improves the power supply rejection ratio.
After the differential converter, a differential switched capacitor filter band
passes the analog signal from 200 Hz to 3400 Hz before the signal is digitized
by the differential compressing AID converter.
The decoder accepts PCM data and expands it using a differential D/A converter. The output of the D/A is low-pass filtered at 3400 Hz and sinXlX compensated
by a differential switched capacitor filter. The signal is then filtered by an active
R-C filter to eliminate the out of band energy of the switched capacitor filter.
These PCM codec-fillers accept both long-frame and short-frame industry
standard clock formats. They also maintain compatibility with Motorola's family
of TSACs and MC3419/MC34120 SLiC products.
The MCl45554/57/64/67 family of PCM codec-fiIters utilizes CMOS due to its
reliable low-power performance and proven capability for complex analog/digital
VLSI functions.

MC145564
and
MC145567

MC145554
and
MC145557

.• P SUFFIX
PLASTIC
CASE 648

1

1

P SUFFIX
PLASTIC
CASE 738

~~

16rl~DU 2~HDD
1

LSUFFIX
CERAMIC
CASE 620

LSUFFIX
CERAMIC
CASE 732

16.
1

DWSUFFIX

DWSUFFIX

SOG

SOG

CASE 751G

CASE 7510

MC145554157 (16-Pin Package)
•
•
•
•
•
•
•
•

Fully Differential Analog Circuit Design for Lowest Noise
Performance Specified for Extended Temperature Range of - 40 to + 85"C
Transmit Band-Pass and Receive Low-Pass Filters On-Chip
Active R-C Pre-Filtering and Post-Filtering
Mu-Law Companding MC145554
A-Law Companding MC145557
On-Chip Precision Voltage Reference (2.5 V)
Typical Power DiSSipation of 40 mW, Power Down of 1.0 mW at ± 5 V

MC145564167 (20-Pin Package)
All of the Features of the MC145554/57 Plus:
• Mu-Law Companding MC145564
• A-Law Companding MC145567
• Push-Pull Power Drivers with External Gain Adjust
• Analog Loop-Back

MOTOROLA COMMUNICATIONS DEVICE DATA

MC145554.MC145557.MC145564.MC145567
2-907

PIN ASSIGNMENTS

MC145554, MC145557

MC145564, MC145567

VBB

VFXI+

VPO+

1-

20

VBB

GNDA

VFXI-

GNDA

2

19

VFXI+

VFRO

GSX

VPO-

3

18

VFXI-

VCC

TSX

VPI

4

17

GSX

FSR

FSX

VFRO

16

ANLB

DR

DX

VCC

6

15

TSX

BCLKR! CLKSEL

BCLKX

FSR

7

14

FSX

MCLKR!PDN

MCLKX

DR

13

DX

BCLKRi CLKSEL

12

BCLKX

11

MCLKX

MCLKRiPDN

10

FUNCTIONAL BLOCK DIAGRAM

GSx

ANLB*

VCC

r

iii

VFXI-

GNDA VBB

VPO+*

FSx

FSR MCLKX BCLKX

MCLKR! BCLKR!
PDN
CLKSEL

SAR
REG

TRANSMIT
SHIFT
REG

RECEIVE
LATCH

RECEIVE
SHIFT
REG

DX

VPO-*

VPI* _ - - - - - - - '

*MC145564 and MC145567 only.

MC145554.MC145557.MC145564.MC145567
2-908

MOTOROLA COMMUNICATIONS DEVICE DATA

DEVICE DESCRIPTION
A codec-filter is used for digitizing and reconstructing the
human voice. These devices were developed primarily for the
telephone network to facilitate voice switching and transmission. Once the voice is digitized, it may be switched by digital
switching methods or transmitted long distance (T1, microwave, satellites, etc.) without degradation. The name codec
is an acronym from "COder" (for the AID used to digitize voice)
and "DECoder" (for the D/A used for reconstructing voice).
A codec is a single device that does both the AID and D/A
conversions.
To digitize intelligible voice requires a signal-to-distortion
ratio of about 30 dB over a dynamic range of about 40 dB.
This can be accomplished with a linear 13-bit AID and D/A,
but will far exceed the required signal-to-distortion ratio at
amplitudes greater than 40 dB below the peak amplitude. This
excess performance is at the expense of data per sample.
Methods of data reduction are implemented by compressing
the 13-bit linear scheme to companded 8-bit schemes. There
are two companding schemes used: Mu-255 Law specifically
in North America, and A-Law specifically in Europe. These
companding schemes are accepted world wide. These
companding schemes follow a segmented or "piecewise-linear" curve formatted as sign bit, three chord bits, and four step
bits. For a given chord, all sixteen of the steps have the same
voltage weighting. As the voltage of the analog input
increases, the four step bits increment and carry to the three
chord bits which increment. When the chord bits increment,
the step bits double their voltage weighting. This results in an
effective resolution of six bits (sign + chord + four step bits)
across a 42 dB dynamic range (seven chords above zero, by
6 dB per chord). Tables 3 and 4 show the linear quantization
levels to PCM words for the two companding schemes.
In a sampling environment, Nyquist theory says that to
properly sample a continuous signal, it must be sampled at
a frequency higher than twice the signal's highest frequency
component. Voice contains spectral energy above 3 kHz, but
its absence is not detrimental to intelligibility. To reduce the
digital data rate, which is proportional to the sampling rate,
a sample rate of 8 kHz was adopted, consistent with a
bandwidth of 3 kHz. This sampling requires a low-pass filter
to limit the high frequency energy above 3 kHz from distorting
the in-band signal. The telephone line is also subject to 50/60
Hz power line coupling, which must be attenuated from the
Signal by a high-pass filter before the AID converter.
The D/A process reconstructs a staircase version of the
desired in-band signal, which has spectral images of the inband signal modulated about the sample frequency and its
harmonics. These spectral images, called aliasing components, need to be attenuated to obtain the desired Signal. The
low-pass filter used to attenuate these aliasing components
is typically called a reconstruction or smoothing filter.
The MC145554/57/64/67 PCM codec-filters have the
codec, both presampling and reconstruction filters, and a
preCision voltage reference on chip, and require no external
components.

PIN DESCRIPTION
DIGITAL
FSR
Receive Frame Sync
This is an 8 kHz enable that must be synchronous with
BCLKR. Following a rising FSR edge, a serial PCM word at
DR Is clocked by BCLKR into the receive data register. FSR
MOTOROLA COMMUNICATIONS DEVICE DATA

also initiates a decode on the previous PCM word. In the
absence of FSX, the length of the FSR pulse is used to
determine whether the 1/0 conforms to the short frame sync
or long frame sync convention.
DR
Receive Digital Data Input
BCLKR/CLKSEL
Receive Data Clock and Master Clock Frequency
Selector
If this input is a clock, it must be between 128 kHz and 4.096
MHz, and synchronous with FSR.ln synchronous applications
this pin may be held at a constant level; then BCLKX is used
as the data clock for both the transmit and receive sides, and
this pin selects the assumed frequency of the master clock
(see Table 1 in Functional Description).
MCLKR/PDN
Receive Master Clock and Power Down Control
Because of the shared DAC architecture used on these
devices, only one master clock is needed. Whenever FSX is
clocking, MCLKX is used to derive all internal clocks, and the
MCLKR/PDN pin merely serves as a power-down control. If
MCLKR/PDN pin is held low or is clocked (and at least one
of the frame syncs is present), the part is powered up. If this
pin is held high, the part is powered down. If FSX is absent
but FSR is still clocking, the device goes into receive
half-channel mode, and MCLKR (if clocking) generates the
internal clocks.
MCLKX
Transmit Master Clock
This clock is used to derive the internal sequencing clocks;
it must be 1.536 MHz, 1.544 MHz, or 2.048 MHz.
BCLKX
Transmit Data Clock
BCLKX may be any frequency between 128 kHz and 4.096
MHz, but it should be synchronous with MCLKX.

Ox

Transmit Digital Data Output
This output is controlled by FSX and BCLKX to output the
PCM data word; otherwise this pin is in a high-impedance
state.

FSx
Transmit Frame Sync
This is an 8 kHz enable that must be synChronous with
BCLKX. A rising FSX edge initiates the transmission of a serial PCM word, clocked by BCLKX, out of DX. If the FSX pulse
is high for more than eight BCLKX periods, the DX and TSX
outputs will remain in a low-impedance state until FSX is
brought low. The length of the FSX pulse is used to determine
whether the transmit and receive digital 1/0 conforms to the
short frame sync or to the long frame sync convention.
TSX
Transmit Time Slot Indicator
This is an open-drain output that goes low whenever the
DX output is in a low-impedance state (i.e., during the transmit
time slot when the PCM word is being output) for enabling
a PCM bus driver.
ANLB
Analog Loop-Back Control Input (MC145564/67 Only)
When held high, this pin causes the input of the transmit
RC active filter to be disconnected from GSX and connected

MC145554.MC145557.MC145564.MC145567
2-909

to VPO+ for analog loop-back testing. This pin is held low in
normal operation.
ANALOG
GSX
Gain-Setting Transmit
This output of the transmit gain-adjust operational amplifier
is internally connected to the encoder section of the device.
It must be used in conjunction with VFXI- and VFXI+ to set
the transmit gain for a maximum signal amplitude of 2.5 V
peak. This output can drive a 600 n load to 2.5 V peak.
VFXIVoice-Frequency Transmit Input (Inverting)
This is the inverting input of the transmit gain-adjust
operational amplifier.
VFXI+
Voice-Frequency Transmit Input
(Non-Inverting)
This is the non-inverting input of the transmit gain-adjust
operational amplifier.
VFRO
Voice-Frequency Receive Output
This receive analog output is capable of driving a 600
load to 2.5 V peak.

n

VPI
Voltage Power Input (MC145564167 Only)
This is the inverting input to the first receive power amplifier.
Both of the receive power amplifiers can be powered down
by connecting this input to VBB.
VPOVoltage Power Output (Inverted) (MC145564/67 Only)
This inverted output of the receive push-pull power
amplifiers can drive 300 n to 3.3 V peak.
VPO+
Voltage Power Output (Non-Inverted)
(MC145554167 Only)
This non-inverted output of the receive push-pull power
amplifier pair can drive 300 n to 3.3 V peak.
POWER SUPPLY
GNDA
Analog Ground
This terminal is the reference level for all signals, both
analog and digital. It is a V.
VCC
Positive Power Supply
VCC is typically 5 V.
VBe
Negative Power Supply
VBB is typically - 5 V.

FUNCTIONAL DESCRIPTION
ANALOG INTERFACE AND SIGNAL PATH
The transmit portion of these codec/filters includes a lownoise gain selting amplifier capable of driving a 600 11 load.
Its output is fed to a three-pole anti-aliasing pre-filter. This
pre-filter incorporates a two-pole Butterworth active low-pass

MC145554.MC145557.MC145564.MC145567
2-910

filter, and a single passive pole. This pre-filter is followed by
a single ended-to-differential converter that is clocked at 256
kHz. All subsequent analog processing utilizes fully differential
circuitry. The next section is a fully-differential, five-pole
switched capacitor low-pass filter with a 3.4 kHz passband.
After this filter is a 3-pole switched-capacitor high-pass filter
having a cutoff frequency of about 200 Hz. This high-pass
stage has a transmission zero at dc that eliminates any dc
coming from the analog input or from accumulated operational
amplifier offsets in the preceding filter stages. The last stage
of the high-pass filter is an autozeroed sample and hold
amplifier.
One bandgap voltage reference generator and digital-toanalog converter (DAe) are shared by the transmit and receive sections. The autozeroed, switched-capacitor bandgap reference generates precise positive and negative reference voltages that are independent of temperature and
power supply voltage. A binary-weighted capacitor array
(CDAC) forms the chords of the companding structure, while
a resistor string (RDAC) implements the linear steps within
each chord. The encode process uses the DAC, the voltage
reference, and a frame-by-frame autozeroed comparator to
implement a successive-approximation conversion algorithm. All of the analog circuitry involved in the data
conversion-the voltage reference, RDAC, CDAC, and
comparator-are implemented with a differential architecture.
The receive section includes the DAC described above, a
sample and hold amplifier, a five-pole 3400 Hz switched capacitor low-pass filter with sinXlX correction, and a two-pole
active smoothing filter to reduce the spectral components of
the switched capacitor filter. The output of the smoothing filter
is a power amplifier that is capable of driving a 600 n load.
The MC145564 and MC145567 add a pair of power amplifiers
that are connected in a push-pull configuration; two external
resistors set the gain of both of the complementary outputs.
The output of the second amplifier may be internally connected to the input of the transmit anti-aliasing filter by
bringing the ANLB pin high. The power amplifiers can drive
unbalanced 300 n loads or a balanced 600 n load; they may
be powered down independent of the rest of the chip by tying
the VPI pin to VBB.
MASTER CLOCKS
Since the codec-filter design has a single DAC architecture, only one master clock is used. In normal operation (both
frame syncs clocking), the MCLKX is used as the master
clock, regardless of whether the MCLKR/ PDN pin is clocking
or low. The same is true if the part is in transmit half-channel
mode (FSX clocking, FSR held low). But if the codec-filter is
in the receive half-channel mode, with FSR clocking and FSX
held low, MCLKR is used for the internal master clock if it is
clocking; if MCLKR is low, then MCLKX is still used for the
internal master clock. Since only one of the master clocks is
used at any given time, they need not be synchronous.
The !paster clock frequency must be 1.536 MHz, 1.544
MHz, or 2.048 MHz. The frequency that the codec-filter expects depends upon whether the part is a Mu-Iaw or an A-law
part, and on the state of the BCLKR/CLKSEL pin. The allowable options are shown In Table 1. When a level (rather than
a clock) is provided for BCLKR/CLKSEL, BCLKX is used as
the bit clock for both transmit and receive.

MOTOROLA COMMUNICATIONS DEVICE DATA

ing an FSR rising edge, the receive sign bit is clocked into
DR. The next seven BClKR falling edges clock in the remaining seven bits of the receive peM word.
Table 2 shows the coding format of the transmit and receive
PCM words.

Table 1. Master Clock Frequency Determination
Master Clock Frequency Expected
BCLKR/CLKSEL

MC145554/64

MC145557/67

Clocked, 1, or Open

1.536 MHz
1.544 MHz

2.04BMHz

0

2.04BMHz

1.536 MHz
1.544 MHz

FRAME SYNCS AND DIGITAL VO
These codec·filters can accommodate both of the industry
standard timing formats. The long frame sync mode is used
by Motorola's MC145500 family of codec-filters and the UDlT
family of digital loop transceivers. The short frame sync mode
is compatible with the IDl (Interchip Digital Link) serial format
used in Motorola's ISDN family and by other companies in
their telecommunication devices. These codec·filters use the
length of the transmit frame sync (FSX) to determine the timing
format for both transmit and receive unless the part is
operating in the receive half·channel mode.
In the long frame sync mode, the. frame sync pulses must
be at least three bit clock periods long. The DX and TSX out·
puts are enabled by the logical ANDing of FSX and BClKX;
when both are high, the sign bit appears at the DX output.
The next seven rising edges of BClKX clock out the remain·
ing seven bits of the PCM word. The DX and TSX outputs
return to a high impedance state on the falling edge of the
eighth bit clock or the falling edge of FSX, whichever comes
later. The receive PCM word is clocked into DR on the eight
falling BClKR edges following an FSR rising edge.
For short frame sync operation, the frame sync pulses
must be one bit clock period long. On the first BClKX rising
edge after the falling edge of BClKX has latched FSX high,
the DX and TSX outputs are enabled and the sign bit is presented on DX. The next seven rising edges of BClKX clock
out the remaining seven bits of the PCM word; on the eighth
BClKX falling edge, the DX and TSX outputs return to a high
impedance state. On the second falling BClKR edge follow·

HALF-CHANNEL MODES
In addition to the normal full duplex operating mode, these
codec·filters can operate in both transmit and receive halfchannel modes. Transmit half·channel mode is entered by
holding FSR low. The VFRO output goes to analog ground
but remains in a low impedance state (to facilitate a hybrid
interface); PCM data at DR is ignored. Holding FSX low while
clocking FSR puts these devices in the receive half·channel
mode. In this state, the transmit input operational aniplifier
continues to operate, but the rest of the transmit circuitry is
disabled; the DX and TSX outputs remain in a high imped·
ance state. MClKR is used as the internal master clock if it
is clocking. If MClKR is not clocking, then MClKX is used
for the internal master clock, but in that case it should be syn·
chronous with FSR. If BClKR Is not clocking, BClKX will be
used for the receive data, just as in the full channel operating
mode. In receive half·channel mode only, the length of the
FSR pulse is used to determine whether short frame sync or
long frame sync timing is used at DR.
POWER DOWN
Holding both FSX and FSR low causes the part to go into
the power down state. Power down occurs approximately 2
ms after the last frame sync pulse is received. An altemative
way to put these devices In power down is to hold the
MClKR/ PDN pin high. When the chip is powered down, the
OX, TSX, and GSX outputs are high impedance, the VFRO,
VPO-, and VPO+ operational amplifiers are biased with a
trickle current so that their respective outputs remain stable
at analog ground. To retum the chip to the power up state,
MClKR/PDN must be low or clocking and at least one of the
frame sync pulses must be present. The Ox and TSX outputs
will remain in a high-impedance state until the second FSX
pulse after power up.

Table 2. PCM Data Format
Mu·Law (MC145554164)

A-Law (MC145557167)

Level

Sign Bit

Chord Bits

Step Bits

Sign Bit

Chord Bits

+ Full Scala

1

000

0000

1

010

Step Bits
1010

+ Zero

1

11 1

1111

1

101

0101

-Zero

0

111

111 1

0

101

0101

-Full Scale

0

000

0000

0

010

1010

MOTOROLA COMMUNICATIONS DEVICE DATA

MC145554.MC145557.MC145564.MC145567
2-911

This device contains circuitry to protect against damage due to high static
voltages or electric fields; however, it is
advised that normal precautions be taken to avoid application of any voltage
higher than maximum rated voltages to
this high impedance circuit. For proper
operation it is recommended that Vin
and Vout be constrained to the range
VSS S (Vin or Vout) S VDD.

MAXIMUM RATINGS (Voltage Referenced to GNDA)
Rating

Value

Unit

-0.5 to +13
-0.3 to +7.0
-7.0 to +0.3

V

Voltage on Any Analog Input or Output Pin

Vee- 0.3to
VCC+ 0.3

V

Voltage on Any Digital Input or Output Pin

GNDA-0.3to
VCC+ 0.3

V

DC Supply Voltage

Symbol
VcctoVee
VCCtoGNDA
VeetoGNDA

Operating Temperature Range

TA

-40 to +85

·C

Storage Temperature Range

Tstg

-85to+150

·C

Unused inputs must always be tied to
an appropriate logic voltage level (e.g.,
VSS, GNDA, or VCC).

POWER SUPPLY (TA = - 40 to + 85·C)
Characteristic
DC Supply Voltage

VCC
Vee

Active Power Dissipation (No Load)

MC145554/57
MC145564/67
MC145564167, VPI = Vee

Power Down Dissipation (No Load)

MC145554/57
MC145564/67
MC145564167, VPI = Vee

Min

Typ

Max

Unit

4.75
-4.75

5.0
-5.0

5.25
-5.25

V

-

-

40
45
40

60
70
60

mW

1.0
2.0
1.0

3.0
5.0
3.0

mW

DIGITAL LEVELS (VCC = 5 V ± 5%, Vee = - 5 V ± 5%, GNDA = 0 V, TA = - 40 to + 85·C)
Symbol

Min

Max

Unit

Input Low Voltage

VIL

-

0.6

V

Input High Voltage

VIH

2.2

-

V

0.4

V

Characteristic

Output Low Voltage

Ox or TSX, IOL = 3.2 mA

VOL

-

Output High Voltage

OX, IOH = - 3.2 mA
IOH=-1.6mA

VOH

2.4
VCC-0.5

-

V

Input Low Current

GNDA S Vln S VCC

IlL

-10

+10

Input High Current

GNDA S Vin S VCC

IIH

-10

+10

Output Current in High Impedance State

GNDA S Ox S VCC

IOZ

-10

+10

I1A
I1A
I1A

MC145554.MC145557.MC145564.MC145567
2-912

MOTOROLA COMMUNICATIONS DEVICE DATA

ANALOG ELECTRICAL CHARACTERISTICS
(VCC = + 5 V± 5%, VBB = -5 V± 5%, VFxl-Connected to GSX, TA =-40to + 65°C)
Min

Characteristic

Typ

Max

±0.05

±0.2

Unit

Input Current (- 2.5 $ Yin $ + 2.5 V)

VFXI+, VFXI-

-

AC Input Impedance to GNDA (1 kHz)

VFXI+, VFXI-

10

20

Input Capacitance

VFXI+, VFXI-

-

-

10

pF

Input Offset Voltage of GSX Op Amp

VFXI+, VFXI-

-

-

±25

mV

Input Common Mode Voltage Range

VFXI+, VFXI-

-2.5

-

2.5

V

Input Common Mode Rejection Ratio

VFXI+, VFXI-

-

65

dB

Unity Gain Bandwidth of GSX Op Amp (Rload ~ 10 kQ)

-

1000

-

DC Open Loop Gain of GSX Op Amp (Rload ~ 10 kQ)

75

-

-

dB

Equivalent Input Noise (C-Mess) Between VFXI+ and VFXI- at GSX

-

-20

-

dBrnCO

IJA
MQ

kHz

0

-

100

pF

Rload = 10 kQ to GNDA
Rload = 600 Q to GNDA

-3.5
-2.6

-

-

+3.5
+2.6

V

GSX, VFRO

±5.0

-

Output Load Capacitance for GSX Op Amp
Output Voltage Range for GSX

-

Output Current (- 2.8 V $ Vout $ + 2.6 V)

-

Output Impedance VFRO (0 to 3.4 kHz)
Output Load Capacitance for VFRO

0

1

-

-

rnA

500

pF

VFRO Output DC Offset Voltage Referenced to GNDA

-

Transmit Power Supply Rejection

Positive, 0 to 100 kHz, C-Message
Negative, 0 to 100 kHz, C-Message

45
45

Positive, 0 to 100 kHz, C-Message
Positive, 4 kHz to 25 kHz
Positive, 25 kHz to 50 kHz
Negative, 0 to 100 kHz, C-Message
Negative, 4 kHz to 25 kHz
Negative, 25 kHz to 50 kHz

50
50
43
50
45
36

-

-

Receive Power Supply Rejection

-

±0.5

-

±100

Q

mV

-

dBC

-

dBC
dB
dB
dBC
dB
dB

MC145564/67 Power Drivers
Input Current (- 1 V $ VPI $ + 1 V)

VPI

-

±0.05

Input Resistance (- 1 V $ VPI $ + 1 V)

VPI

5

10

VPI

-

-

±50

VPO+orVPO-

1

-

Q

VPO-

-

400

-

kHz

Input Offset Voltage (VPI Connected to VPO-)
Output Resistance, Inverted Unity Gain
Unity Gain Bandwidth, Open Loop

-

I'A
MQ
mV

0

-

Gain from VPO-to VPO+ (Rload = 300 Q, VPO + to GNDA Level at VPO= 1.77 Vrms, +3 dBmO)

-

-1

-

VN

Maximum 0 dBmO Level for Better than ± 0.1 dB Linearity Over the
Rload= 600Q
Range -10 dBmO to +3 dBmO (For Rload between VPO+ and VPO-) Rload = 1200 Q
Rload = 10 kQ

3.3
3.5
4.0

-

-

Vrms

to 4 kHz
4to 50 kHz

55
35

-

-

Differential Power Supply Rejectkm of VCC or VBB (VPO- Connected to VPI)
VPO+ to VPO-, 0 to 50 kHz

50

-

-

Load Capacitance (00 Q ~ Rload ~ 300 Q)

VPO+ orVPO-to GNDA

Power Supply Rejection of Vec or VBB (VPO- Connected to VPI)
VPO + or VPO- to GNDA

MOTOROLA COMMUNICATIONS DEVICE DATA

o

-

1000

pF

dB
dB

MC145554.MC145557.MC145564.MC145567
2-913

ANALOG TRANSMISSION PERFORMANCE
(VCC = +5 V ± 5%, VBB = -5 V ± 5%, GNDA = 0 V, 0 dBmO = 1.2276 Vrms = +4 dBm @ 600 n, FSx = FSR = 8 kHz,
BCLKx = MCLKX = 2.048 MHz Synchronous Operation, VFXI- Connected to GSX, TA = - 40 to + 85°C Unless Otherwise Noted)

AID

End-to-End
Characteristic
Absolute Gain (OdBmO @ 1.02 kHz, TA= 25°C, VCC = 5 V, VBB =-5 V)
Absolute Gain Variation with Temperature

Oto 70°C
-40to+ 85°C

Absolute Gain Variation with Power Supply (VCC = 5 V, ± 5%,
VBB =-5 V, ±5%)

Max

Min

Max

Min

Max

Unit

-

-

-0.25

+0.25

-0.25

+0.25

dB

±0.03
±0.06

dB

-

-

±0.02

dB

+0.4
+0.8
+1.6

Gain vs Level Tone (Relative to - 10 dBmO, 1.02 kHz)

+3to-40 dBmO
-401o-50dBmO
-5010-55 dBmO

-0.4
-0.8
-1.6

Gain vs Level Pseudo Noise CCITT G.712
(MC145557/67 A-Law Relative to - 10 dBmO)

-10to-40 dBmO
-40to-50 dBmO
-50 to-55 dBmO

-

Total Distortion, 1.02 kHz Tone (C-Message)

Total Distortion With Pseudo Noise CCITT G.714
(MC145557/67 A-Law)

+3dBmO
Oto-30 dBmO
-40dBmO
-45dBmO
-55dBmO
-3dBmO
- 6to- 27 dBmO
-34dBmO
-40 dBmO
-55dBmO

Idle Channel Noise (For End-End and AID, Note 1)
(MC145554164 Mu-Law, C-Message Weighted)
(MC145557/67 A-Law, Psophometric Weighted)
Frequency Response (Relative to 1.02 kHz @ 0 dBmO)

In-Band Spurious
(1.02 kHz @ 0 dBmO, Transmit and Receive)

15Hz
50Hz
60Hz
200Hz
300 to 3000 Hz
3300 Hz
3400 Hz
4000 Hz
4600 Hz
300 to 3000 Hz

Out-of-Band Spurious at VFRO (300-3400 Hz @ 0 dBmO In)
4600 10 7600 Hz
7600 to 8400 Hz
8400 to 100,000 Hz
Idle Channel Noise Selective (8 kHz, Input = GNDA, 30 Hz Bandwidth)
Absolute Delay (1600 Hz)
Group Delay Referenced to 1600 Hz

500 to 600 Hz
600 to 800 Hz
800 to 1000 Hz
100010 1.600 Hz
1600 10 2600 Hz
2600 10 2800 Hz
2800 10 3000 Hz

Crosstalk of 1020 Hz @ 0 dBmO from AID or D/A (Note 2)
Intermodulation Distortion of Two Frequencies of Amplitudes
-410-21 dBmO from the Range 300 to 3400 Hz

D/A

Min

33
35
29
24
15
27.5
35
33.1
28.2
13.2

-

-0.3
-0.70
-1.6

-

-

-

-

15
-70
-40
-30
-26

-

+0.3
+0.3
0
-28
-60
-48

-30
-40
-30

±0.02

-

-0.2
-0.4
-0.8

+0.2
+0.4
+0.8

-0.2
-0.4
-0.8

+0.2
+0.4
+0.8

dB

-0.25
-0.30
-0.45

.+0.25
+0.30
+0.45

-0.25
-0.30
-0.45

+0.25
+0.30
+0.45

dB

33
36
30
25
15

-

33
36
30
25
15

-

dBC

-

-

28.5
36
34.2
30
15

-

-

dB

15
-70

-

7
-83

dBmCO
dBmOp

0
0
0
0
+0.15
+0.15
0
-14
-30

dB

-48

dBmO

28
35.5
33.5
28.5
13.5

-

-

-1.0
-0.15
-0.35
-0.8

-

-

-

-41

-

-70

±0.03
±0.06

-

-40
-30
-26
-0.4
+0.15
+0.15
0
-14
-32
-48

315
220
145
75
40
75
105
155

-0.15
-0.15
-0.15
-0.15
-0.15
-0.35
-0.8

-

-

dB

-

-40
-40
-40
-30

-30
-40
-30
-70

dBmO

215

liS

-

I1S

-

-

90
125
175

-75

-

-75

dB

-41

-

-41

dB

NOTES:
1. Extrapolated from a 1020 Hz @ -50 dBmO distortion measurement to correct for encoder enhancement.
2. Selectively measured while the AID is stimulated with 2667 Hz @ -50 dBmO.

MC145554.MC145557.MC145564.MC145567
2-914

MOTOROLA COMMUNICATIONS DEVICE DATA

DIGITAL SWITCHING CHARACTERISTICS
VCC =5 V ± 5%, VBB =- 5 V ± 5%, GNDA =0 V, All Signals Referenced to GNDA;TA =- 40 to + 85°C, Cload =150 pF Unless Otherwise Noted
Characteristic

Symbol

Min

Typ

Max

Unit

-

1.536
1.544
2.048

MHz

tw(M)

100

tw(B)

50

tw(Fl)

50

-

50

ns

Master Clock Frequency

MClKX or MClKR

fM

Minimum Pulse Width High or low

MClKX or MClKR

Minimum Pulse Width High or low

BClKX or BClKR
FSxor FSR

Minimum Pulse Width low
Rise Time for all Digital Signals

tr

Fall Time for all Digital Signals

tf

-

fB

128

Bit Clock Data Rate

BClKX or BClKR

Setup Time from BClKX low to MClKR High

tsu(BRM)

50

Setup Time from MClKX High to BCLKX Low

tsu(MFB)

20

ih(BF)

20

Hold Time from BCLKx (BCLKR) Low to FSx (FSR) High
Setup Time for FSX (FSR) High to BCLKX (BCLKR) Low for Long Frame

ns
ns
ns

50

ns

4096

kHz

-

ns

ns

ns
ns

tsu(FB)

80

Delay Time from BClKX High to Ox Data Valid

id(BD)

20

60

140

ns

Delay Time from BCLKX High to TSX Low

id(BTS)

20

50

140

ns

Delay Time from the 8th BCLKX low of FSX Low to Ox Output Disabled

id(ZC)

50

70

140

ns

Delay Time to Valid Data from FSx or BClKX, Whichever Is Later

id(ZF)

20

60

140

ns

Setup Time from DR Valid to BCLKX Low

lsu(DB)

0

-

-

ns

Hold Time from BCLKR Low to DR Invalid

th(BD)

50

Setup Time from FSX (FSR) High to BCLKX (BCLKR) Low In Short Frame

lsu(F)

50

Hold Time from BCLKX (BCLKR) Low to FSx (FSR) Low in Short Frame

th(F)

50

Hold Time from 2nd Period of BClKX (BClKR) low to FSX (FSR) Low In
Long Frame

th(BFI)

50

MOTOROLA COMMUNICATIONS DEVICE DATA

ns
ns
ns
ns

MC145554.MC145557.MC145564.MC145567
2-915

MCLKX
MCLKR

BCLKX

FSx
----'

DX-------{

DR-------<

Figure 1. Short Frame Sync Timing

MC145554.MC145557.MC145564.MC145567
2-916

MOTOROLA COMMUNICATIONS DEVICE DATA

MCLKX
MCLKR

BCLKX

FSx

_ _ _ _ _J

Ox

DR

Figure 2. Long Frame Sync Timing
-5V
2
ANALOG OUT

':'

3
4

+5V

5
6

VBB

VFXI+

GNDA

VFxlGSx

VFRO
VCC

MCl45554157

TSx
FSx

FSR

16
ANALOG IN
TXTIMESLOT
12

11
Ox
10
BCLKX
MCLKX

DR
BCLKRi CLKSEL
MCLKRiPDN

8kHz
2
3
1.544MHzI
2.04BMHz

4
5

ADCPMIN

MODE

VDD

000

EDO

DOE

EOE

DOC
001
DIE

7

POWER DOWN

PO/RESET
VSS

':'

MCl45532

16+ 5V
15
14

13
EDC
12
EDI
11
EIE
10
SPC
9
ADP

ADPCMOUT

20.48 MHz
':'

Figure 3. ADPCM Transcoder Application

MOTOROLA COMMUNICATIONS DEVICE DATA

MC145554.MC145557.MC145564.MC145567
2-917

20
19
18

MC33120
15
Vec
VOO
EP PDI/ST2 12
13
ST1
BP
14
VOG

+5V
+

51lF,16V

lN4002
VAG
1k

17

9.1 k 16
RING

9.1 k

5

1k

4

9

-=

CP
TSI

+5V
MCI4555417
48.5 k

RXI
4.7k

RSI
CN

RFO
IIlF

O.OO5IlF
50V

TXO
3

BN

CF

EN

vaB

VEE

11
7
6

Vce
12
FSx
FSR
10
BCLKX
7
BCLKR
8
MCLKR
9
MCLKx
15
11
VFXIOx
14
GSx
OR
49.0k 16
13
VFXI+
TSx
3

1+ 1.0IlF,50V

E 101lF,50V

VFRO

GNOA

-=

8 kHz SYNC
OATACLOCK
MC145554=
1.544 MHZ
MCI45557=
2.048 MHz
TO PCMHWY

VBB
-5V

NOTE: Six resistors and two capacitors can be 5% tolerance.

Figure 4. A Complete Single Party Channel Unit Using MC145554157 PCM CodeC/Filter and MC33120 SLIC

MC145554.MC145557.MC145564.MC145567
2·918

MOTOROLA COMMUNICATIONS DEVICE DATA

'5' TRANSCEIVER
+5V

MC145474P

17

TEIN'i'

VOO

33k
+5V

ISET

SINTERFACE

':'

SYNC

Hl

21

TX+

CLK

+5V
7n

RX

7n

TX

20

TX-

OREO

LAP·OIlAP·B CONTROLLER
4

+5V +5V

8
9
10
11
7

OGRT

SEL

RX+

CLK

+5V
lkn

AX

lkn

TX
IRO
RESET
EXTAL

RXVSS
XTAL

':'

0
':'

MCl45554P
500n
VFRO

VCC
FSX, FSR

soon
+MIC (RED)
-RCVR
(WHITE)
-MIC(BLK)

13
12

30pF

':'

+5V

14

15.36 MHz

I
HANDSET
RJ·l1
+ RCVR
(WHITE)

15

19

30pF

MC145488

DO
01
02
60,44
SYNC 0, 1 03
04
59,45
CLKO, 1
05
55,49
06
TXO,l
07
56,48
08
RXO,l
47
09
OREOl
010
46
011
OGNTl
012
013
50 SCPE 1
014
53
015
SCPEO
Al
57
A2
SCPCLK
A3
54
SCPTXO
A4
58
AS
SCPRXO
A6
A7
A8
A9
Al0
All
A12
A13
A14
A15
OWNO
OWNl
MCLK

':'

lkn

52,2,9

~

VOO

LOS
UOS
RST
lACK
IRO
OTACK
BERR

12,5
10,7,8,9

COOECIFILTER

64
63
62
61
42
43
27
28
29
31
32

33

34
36
37
38
BR 39
BG 40
BGACK 41

VFXI-

O.lI1F

22
23
24
25
26
8
7
6
5 MPU
4 BUS
3
1
68
67
66
65

CS
RiW
AS 30

+5V
4

MCLK,BCLK
11
Ox
6
GSx
DR
13
VFXI+
TSX 1
VBB
GNOA

10kn

10
11
12
13
14
15
16
17
18
19
20

-5V

51,36,21

VSS

':'

Figure 5. ISDN Voice/Data Terminal

MOTOROLA COMMUNICATIONS DEVICE DATA

MC145554.MC145557.MC145564.MC145567
2-919

Table 3. Mu-Law Encode-Decode Characteristics

Chord
Number

Number
of Steps

Step
Size

Normalized
Encode
Decision
Levels

Digital Code

1
Sign

I
I

I 3 I 4 I
Chord I Chord I Chord I
2

5
Step

I
I

6
Step

I
I

7
Step

I
I

Step

Normalized
Decode
Levels

8

8159
1

0

0

0

0

0

0

0

8031

1

0

0

0

1

1

1

1

4191

1

0

0

1

1

1

1

1

2079

1

0

1

0

1

1

1

1

1023

1

0

1

1

1

1

1

1

495

1

1

0

0

1

1

1

1

231

1

1

0

1

1

1

1

1

99

1

1

1

0

1

1

1

1

33

1

1

1

1

1

1

1

0

2

1

1

1

1

1

1

1

1

0

7903
8

16

256
4319
4063

7

16

128

2143
2015

6

16

64

1055
991

5

16

32

511
479

4

16

16

239
223

3

16

8

103
95

2

16

4

35
31

1

15

2

1

1

3
1
0

NOTES:
1. Characteristics are symmetrical about analog zero with sign bit = 0 for negative analog values.
2. Digital code includes inverison of all magnitude bits.

MC145554.MC145557.MC145564.MC145567

2-920

MOTOROLA COMMUNICATIONS DEVICE DATA

Table 4. A-Law. Encode-Decode Characteristics

Chord
Number

Number
of Steps

Step
Size

Normalized
Encode
Decision
Levels

Digital Code

1
Sign

I
I

I 3 I 4 I
Chord I Chord I Chord I
2

5
Step

I
I

I
Step I
6

7
Step

I
I

Step

Normalized
Decode
Levels

8

4096
1

0

1

0

1

0

1

0

4032

1

0

1

0

0

1

0

1

2112

1

0

1

1

0

1

0

1

1056

1

0

0

0

0

1

0

1

528

1

0

0

1

0

1

0

1

264

1

1

1

0

0

1

0

1

132

1

1

1

1

0

1

0

1

66

1

1

0

1

0

1

0

1

1

3968
7

16

128
2176
2048

6

16

64

1088
1024

5

16

32

544
512

4

16

16

272
256

3

16

8

136
128

2

16

4

68
64

1

32

2

2
0

NOTES:
1. Characteristics are symmetrical about analog zero with sign bit 0 for negative analog values.
2. Digital code includes alternate bit inversion, as specified by cCln.

=

MOTOROLA COMMUNICATIONS DEVICE DATA

MC145554.MC145557.MC145564.MC145567
2-921

MOTOROLA

-

SEMICONDUCTOR
TECHNICAL DATA

MC145572
Product Preview

ISDN U·lnterface Transceiver II
The MC145572 is a second generation Integrated Services Digital Network
U-Interface Basic Access Transceiver. The MC145572 is an enhancement of
the MC1454721MC14LC5472 with low power consumption, fewer pins, fewer
extemal components, and increased digital interface functionality. It provides
144 kbps full duplex data transmission on twisted pair loops up to 18,000 feet
or 5.5 km in length.
• Single Chip 2B 1Q, Echo Cancelling, Adaptively Equalized Transceiver
• Conforms to the ANSI T1.601, "... ISDN Basic Access Interface for Application
for Use on Metallic Loops for Application on the Network Side of the NT
(Layer 1 Specification)" and to ETSI Standards
• Extended Maintenance Functions Provided Through Control Interface
• Automatic Embedded Operations Channel Mode
• All Maintenance Functions are Provided on Chip
• Pin Selectable LT/NT Mode of Operation
• Low Power CMOS
• Maximum 300 mW Power Consumption When Activated
• 44-Lead Surface Mount Package
• Selectable Between IDL and GCllnterfaces
• Six Programmable Timeslot Assigners
• 8-kHz Reference Clock Input
• Serial or Parallel Control Interfaces
• Optional D Channel Interface
• Optional Access to D Channel Through Control Interface
• Software Compatible with MC1454721MC14LC5472
• IDL Data Alignable to U-Interface Superframe for Transmit and Receive
• Fewer External Components in Line Interface Circuit
• Voltage Controlled Crystal Oscillator only Requires an External Crystal

Tl1ls document contains Information on a product under development. Motorola reserves the rlght to change or discontinue this product without notice.

MC145572
2-922

MOTOROLA COMMUNICATIONS DEVICE DATA

MC145572 BLOCK DIAGRAM

INTERFACE

ill
z

ill
z

o
:::E

C

~ 0~

CONTROL
INTERFACE-

~~====~

MOTOROLA COMMUNICATIONS DEVICE DATA

MC145572
2-923

MOTOROLA

-

SEMICONDUCTOR
TECHNICAL DATA

MC145574
Product Preview

ISDN SIT Interface
Transceiver II
The MC145574 is the Motorola second generation ISDN SfT Interface Transceiver. The MC145574 provides an economical VLSI Layer 1 interface for the
transportation of two 64 kpbs B channels and one 16 kbps D channel between
the network termination (NT) and terminal equipment (TE) applications. The
MC145574 conforms to CCITT 1.430 and ANSI T1.605 specifications.
The MC145574 provides the modulation line drive and demodulation/line receive functions required of the interface. In addition, the MC145574 provides
the activation/deactivation, error monitoring, framing, bit, and octet timing. The
MC145574 provides the control signals for the interface to the Layer 2 devices.
Complete multiframe capability is provided.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•

Backwards compatible with the MC145475
Conforms to CCITT 1.430 and ANSI T1.605 Specifications
Detects Far-End Code Violations (FECVs) in the NT Mode
Pin Selectable NT or TE Modes of Operation
Industry Standard Microprocessor SCP Interface
Incorporates IDL and IDL2 Interfaces
Supports 1:2.5 Transformers for Transmit and Receive
IDL2 Interface has Time Slot Assignment Capability
GCI Compatible (General Circuit Interface)
Supports Full Range of SfT and IDL Loopbacks
Enhanced S&Q Multiframing Capability
Reduced Power Consumption
NT1 Star Mode of Operation
Incorporates all the Features of the MC145474
Supports TE Slave/Slave Mode for PBX Applications
Supports NT Terminal Mode for NT1fTA Applications

PIN ASSIGNMENT

ISET
RxN
RxP
TEiNU
MASTERISLAVE_L
TFSC/TCLKlDSTBIFIX
VSS
GCLSGlDGRANT/ANDout
DREQ/ANDin
CLASSJDJN/ECHOJN
IDL..FSC/IDL_FSRlGCLFSC
IDL_DCUGCLDCL
IDL..DinlGCLDin
IDL_Dout/GCLDout

4
6
7
8
9
10
11
12
13
14

28
27
26
25
24
23
22
21
20
19
18
17
16
15

RESET_L
TxP
TxN
XTAL
EXTAL
3V REG_OUTPUT
OUTPUT_DRIVER_VDD
VDD
SCPJRQ.L
TSEN/IDL_FST/GCLBCL
SCP_EN_UGCLEN_L
SCP_CLKlGCLS2IGCLM2
SCP_RxlGCI_Sl/GCLMI
SCP_TxlGCLSOIGCLMO

This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.

MC145574
2-924

MOTOROLA COMMUNICATIONS DEVICE DATA

MC145574 BLOCK DIAGRAM

TxP TxN

DGRANT

DREQ

RxP RxN

ISET

EXTALout
XTALin

!oIf':....;;;;;t--

VDD

CONTROL & DATA INTERFACE SIGNALS

MOTOROLA COMMUNICATIONS DEVICE DATA

MC145574
2-925

MOTOROLA

-

SEMICONDUCTOR
TECHNICAL DATA

MC145583
Product Preview

3.3·Yolt.Only
Driver/Receiver With an
Integrated Standby Mode

DWSUFFIX

SOG
CASE 751F

EIA-232E and CCITT V.28
The MC145583 is a CMOS transceiver composed of three drivers and five
receivers that fulfills the electrical specifications of EIA-232E, EIA-562, and CCITI
V.28 while operating from a single +3.3 or +5.0 V power supply. This transceiver
is a high· performance, low-power consumption device that is equipped with a
Standby function.
A voltage tripler and inverter converts the +3.3 Vto±8.8 V, or a voltage doubler
and inverter converts the + 5.0 V to ±8.8 V. This is accomplished through an onboard 40 kHz oscillator and five inexpensive external electrolytic capacitors.

PIN ASSIGNMENTS

cs+

C2+

GNO

VCC

cs-

C2-

RIMON

Cl +

Receivers:
• ±25 V Input Range
• 3 to 7 kn Input Impedance
• 0.8 V Hysteresis for Enhanced Noise Immunity
• Three-State Outputs During Standby Mode

VSS

Cl-

STS

VOO

Rxl

001

Charge Pumps:
• +3.3 V to ±8.8 V Triple Charge Pump Architecture or + 5.0 V to ±8.8 V
Doubler Charge Pump Architecture
• Requires Five Inexpensive Electrolytic Capacitors
• On-Chip 40 kHz Oscillators

Rx2

002

Rx3

003

Txl

011

Rx4

004

Tx2

012

RxS

005

Tx3

013

Drivers:
• ±6.0 Output Swing at 3.3 or 5.0 V power supply
• 300 n, Power-Off Impedance
• Output Cu,rrent Limiting
• Three-State Outputs During Standby Mode

Ring Monitor Circuit:
• Invert the Input Level on Rx1 to Logic Output Level on RIMON al Standby
Mode

This document contains infonnation on a product under development. Motorola reserves the right to change or discontinue this product without notice.

MC145583

2-926

MOTOROLA COMMUNICATIONS DEVICE DATA

MOTOROLA

-

SEMICONDUCTOR
TECHNICAL DATA

MC145601
Product Preview

Time Slot Interchange
Circuit

PSUFFIX
PLASTIC
CASE 711

The MC145601 time slot interchange circuit (TSIC) is a CMOS IC designed
for switching pulse code modulation 9PCM) voice or data, under microprocessor
control, in a digital exchange or central office. It connects any of 256 incoming
PCM channels to any of 256 outgoing PCM channels.
•
•
•
•
•
•
•
•
•
•
•
•

5 V Supply
8 x 32 Channel Input
8 x 32 Channel Output
256 Port Non-blocking Digital Switching Matrix
Building Block for Digital PABX
Expandable to Larger Capacity Block
32 Serial Channels Per Frame
Typical Bit Rate: 2.048 Mbps
Typical Synchronization Rate: 8 kHz
Interface to MC88XXX Family Microprocessors
8 Instructions Available
40-Pin Dual-In-Line Package

PIN ASSIGNMENT
OC4

RESET
ClK

OC2

SYNC

OCl

Tx7
Tx6
TxS

Rx6
RxS

Tx4
VOO
Tx3

N

MMENDED
R NEW DESIGN

Vss

Tx2

Rx3

Txl

Rx2

TxO

Rxl

07

RxO

06

REAOY

05

OTACK

04

RS1

03

RSO

02

RiW

01

cs

00

This document contains Information on a new product under development. Motorola reserves the right to change or discontinue this product without notice.

MOTOROLA COMMUNICATIONS DEVICE DATA

MC145601

2·927

MOTOROLA

-

SEMICONDUCTOR
TECHNICAL DATA

MC145611
Product Preview

PCM Conference Circuit
The MC145611 PCM conference circuit is an HCMOS device designed for
voice conference in a digital (PCM) telephone switch such as a TDM PABX. The
device is capable of providing mixing of up to eight channels (parties) such that
every party can hear when one or more parties speak at the same time.
The technique of level priority coding is used. It provides a low cost means
of mixing of PCM voice codes for voice conference application.
• 20-Pin Dual-In-Line Package
• Single +5 V Power Supply
• Support Standard Mu-Law or A-Law PCM Codes
• Directly Off the PCM Highways
• 4.096 MHz Clock, 8 kHz Frame Sync, and Serial PCM Data Comply with
Codec Timing Used in the PABX System
• One-Frame Delay to PCM Data
• Built-In Time Slot Assignment Circuit
• Serial Data with MCU Interface
• 8 Parties Conference in Single Group or Split into Two Groups
• Intrusion Party Channel Time Slot Assignment Provided
• Built-In Maskable Tone Signalling. Tone Level and Frequency External
Adjustable

PSUFFIX
PLASTIC

CASE73B

PIN ASSIGNMENT
OCI [ 1-

20

FS [ 2

19

PCMin [ 3
PCMout [ 4

17

PCMEN[ 5

16

MulA [ 6

15

CTS [ 7

cst

8

ON [ 9
VSS [ 10

P VOO

PNC
18 PTSAO

PTE2

pm

PTL3
14 pTl2
13 P TL1
12 P TF
11 P OCLK

NC = NO CONNECTION

NOT RECOMMEND D
FOR NEW D
GN

This document contains information on a new product under development. Motorola reserves the right to change or discontinue this product without notice.

MC145611
2-928

MOTOROLA COMMUNICATIONS DEVICE DATA

MOTOROLA

-

SEMICONDUCTOR
TECHNICAL DATA

MC145705
MC145706
MC145707

Product Preview

5-Yolt-Only Driver/Receiver With
an Integrated Standby Mode
EIA-232-E and CCITT V.28
The MC145705/06/07 are a series of silicon-gate CMOS transceiver ICs that
fulfill the electrical.specifications of EIA-232-E and CCITT V.28 while operating
from a single +5 V power supply. These transceiver series are high performance
and low power consumption devices that are equipped with standby and output
enable function.
A voltage doubler and inverter convert the +5 V to ±10 V. This is accomplished
through an on-board 20 kHz oscillator and four inexpensive external electrolytic
capacitors.
The MC145705 is composed of two drivers and three receivers, the MC145706
has three drivers and two receivers, and the MC145707 has three drivers and
three receivers. These drivers and receivers are virtually identical to those of
the MC145407.

-

PSUFFIX
PLASTIC
CASE 738

DWSUFFIX

SOG
CASE 751D

Available Driver/Receiver Combinations
Drivers

Receivers

No_ of Pins

MC145705

2

3

20

MC145706

3

2

20

MC145707

3

3

24

Device

Drivers:
• ±7.5 Output Swing
• 300 Q Power-Off Impedance
• Output Current Limiting
• TTL and CMOS Compatible Inputs
• Three-State Outputs During Standby Mode
• Hold Output OFF (MARK) State by TxEN Pin
Receivers:
• ±25 V Input Range
• 3 to 7 kQ Input Impedance
• 0.8 V Hysteresis for Enhanced Noise Immunity
• Three-State Outputs During Standby Mode

_

PSUFFIX
PLASTIC
CASE 724

I

24

DWSUFFIX

SOG
CASE 751E

ORDERING INFORMATION
MC145705P
MC145706P
MC145707P
MC145705DW
MC145706DW
MCl45707DW

}
}

PLASTIC

SOG

Charge Pumps:
• +5 to ±10 V Dual Charge Pump Architecture
• Supply Outputs Capable of Driving Three Drivers on
the MC145403106 Simultaneously
• Requires Four Inexpensive Electrolytic Capacitors
• On-Chip 20 kHz Oscillators

This document contains Inlonnation on a product under development. Motorola reserves the right to change or discontinue this product without notice.

MOTOROLA COMMUNICATIONS DEVICE DATA

MC145705.MC145706.MC145707

2-929

PIN ASSIGNMENTS

MC145706
3 Drlvers12 Receivers

MC145705
2 Drlvers/3 Receivers
C2+

Cl+

02+

Ycc

VCC
02-

Cl+

Cl-

C2-

ClVoo

VOO
STB

TxEN

STB

TxEN

Axl

DOl

Txl

011

Rx2

002

Rxl

DOl

Txl

011

Tx2

012

Rx3

003

Rx2

D02

Tx2

012

Tx3

013

MC145707
3 Drivers13 Receivers
Cl+

C2+

VCC
C2-

Cl-

VSS
TxEN
NC

NC

Axl

DOl

Txl

011

Rx2

002

Tx2

012

Rx3

D03

Tx3

013

NC = NO CONNECTION

MC145705.MC145706.MC145707

2-930

MOTOROLA COMMUNICATIONS DEVICE DATA

FUNCTION DIAGRAM

CHARGE PUMPS

OSC

GND
+
C4

C3

Vss

VDD

RECEIVER
VDD

VDD

STS
DO

-=

-=

VSS
1.0V

'---1<:>1--- 1.8 V

'Protection Circuit

DRIVER
VDD

STS

TxEN
VCC

300Q
Tx

o--'VI/Ir-<.---+

LEVEL
SHIFT

I - -......--DI
1-----1.4V

VSS

MOTOROLA COMMUNICATIONS DEVICE DATA

MC145705.MC145706.MC145707
2-931

MAXIMUM RATINGS (Voltage Polarities Referenced to GNO)
Rating

Symbol

Value

Unit

DC Supply Voltage

VCC

-0.5 to +6.0

V

Input Voltage
Rx1-3 Inputs
011-3 Inputs

VIR

VSS-15 to VOO+15
-0.5 to VCC+0.5

V
mA

I

±100

Power Dissipation

Po

1

W

Operating Temperature Range

TA

-40 to +85

°c

Tsta

-85 to +150

°c

DC Current Per Pin

Storage Temperature Range

This device contains protection circuitry
to guard against damage due to high static
voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum
rated voltages to this high-impedance circuit. For proper operation, it is recommended that the voltage at the 01 and DO
pins be constrained to the range
GNO S VOl S VOOandGNOSVOOS VCC.
Also, the voltage at the Rx pin should be
constrained to (V SS- 15 V) S V Rx1-Rx3 S
(VOO+ 15 V), and Tx should be constrained
to VSS S VTx1-Tx3 S VOO.
Unused inputs must always be tied to
an appropriate logic voltage level (e.g.,
GNO or VCC for 01, and GNO for Rx).

RECOMMENDED OPERATING LIMITS
Parameter
Power Supply
Operating Temperature Range

Symbol

Min

Typ

Max

VCC

4.5

5

5.5

Unit
V

TA

-40

-

85

°c

DC ELECTRICAL CHARACTERISTICS (Voltage polarities referenced to GNO = 0 V; C1-C4 = 10 ItF; TA = -40 to +85°C)
Symbol

Min

Typ

Max

DC Power Supply

Parameter

VCC

4.5

5

5.5

V

Quiescent Supply Current (Output Unloaded, Input Low)

ICC

-

1.7

3.5

mA

<10

20

itA

0.5

V

ICC(STB)

-

Control Signal Input Voltage (STB, TxEN)
Logic Low
Logic High

VIL
VIH

VCc-O· 5

Control Signal Input Current
Logic High (STB)

IlL
IIH

-

Quiescent Supply Current (Stand-By Mode) (Output Unloaded, Input Open)

Logic Low (TxEN)

Charge Pumps Output Voltage (C1, C2, C3, C4 = 10 ItF)
Output Voltage (VOO)
Iload= 0 mA
Iload =5 mA
Iload = 10 mA
Output Voltage (VSS)
Iload =5 mA
Iload = 10 mA

Iload= 0 mA

-

-

-

Unit

-10
10

itA
V

VOO

VSS

8.5
7.5
6.0

10.0
9.5
9.0

-8.5
-7.5
-6.0

-10.0
-9.2
-8.6

11

-11

-

-

RECEIVER ELECTRICAL SPECIFICATIONS
(Voltage polarities referenced to GNO = 0 V; VCC = +5 V ±10%; C1-C4 = 10 ItF; TA = -40 to +85°C)
Parameter

Symbol

Min

Typ

Max

Unit

Input Turn-On Threshold (V001-003 = VOL)
Rx1-Rx3

Von

1.35

1.8

2.35

V

Input Turn-Oil Threshold (V001-003 = VOH)
Rx1-Rx3

Voll

0.75

1

1.25

V

Input Threshold Hysteresis (Von = VolI)
Rx1-Rx3

Vhys

0.6

0.8

Input Resistance

Rin

3

High-Level Output Voltage (001-003)
lout =-20 itA
VRx1-Rx3 = -3 to -25 V
lout=-1 mA

VOH

VCc-O·1
VCc-O· 7

Low-Level Output Voltage (001-003)
lout = +20 itA
V Rx1-Rx3 = +3 to +25 V
lout = + 1.6 mA

VOL

MC145705.MC145706.MC145707
2-932

-

-

V

5.4

7

kQ

-

-

V

4.3

-

0.01
0.5

0.1
0.7

V

MOTOROLA COMMUNICATIONS DEVICE DATA

DRIVER ELECTRICAL SPECIFICATIONS
(Voltage polarities referenced to GNO = 0 V; VCC = +5 V ±10%; C1-C4 = 10 IlF; TA = -40 to +85°C)
Parameter

Symbol

Min

Typ

-

-

Max

Oigitallnput Voltage 011-013
Logic Low
Logic High

VIL
VIH

Input Current
VOI=GNO
VOl = VCC

IlL
IIH

-

-

±1.0

Output High VoltageTx1-Tx3
(VOI1-013 = Logic Low, RL = 3 kn)
Tx1-Tx6*

VOH

6
5

7.5
6.5

-

Output Low Voltage Tx1-Tx3
(V0I1-013 = Logic High, RL = 3 kO)
Tx1..,Tx6*

VOL

~

-7.5

-5

~.5

2

011-013

Off Source Impedance

Tx1-Tx3

-

300

loff

Output Short Circuit Current (VCC = 5.5 V)
Tx1-Tx3 Shorted to GNO**
Tx1-Tx3 Shorted to ±15 V***

7

ISC

-

..

-

Unit
V

0.8

-

-

-

I1A
V

V

il
mA

±60
±100

*Speclficatlons for a MC14570X powenng a MC145406 or MC145403 With three additional drivers/receivers.
**Specification is for one Tx output to be shorted at a time. Should all three driver outputs be shorted simultaneously, device power dissipation
limits could be exceeded.
***This condition could exceed package limitations.

SWITCHING CHARACTERISTICS (VCC = +5 V, ±10%; C1-C4 = 10 IlF; TA = -40 to +85°C)

I

I

Parameter

Symbol

I

Typ

Min

Max

Unit

Drivers
Propagation Oelay Time
Tx1-Tx3
Low·to-High
(RL = 3 kil, CL = 50 pF or 2500 pF)

tpLH

High-to-Low
(RL = 3 kil, CL = 50 pF or 2500 pF)

tpHL

I1S

-

0.5

1

0.5

1

±6

±ao
-

Output Olsable Time

tOAZ

-

4

10

I1S

Output Enable Time

tOZA

-

25

50

ms

-

1

250

400

40

100

ns

4

10

I1S

25

50

ms

Output Slew Rate Tx1-Tx3
Minimum Load (RL = 7 kn, CL = 0 pF)

SR

Maximum Load (RL = 3 kn, CL = 2500 pF)

V/IlS

±5

Receivers
Propagation Oelay Time
LoW-lo-High

001-003
tPHL

-

Output Rise Time

001-003

1r

-

Output Fall Time

001-003

tf

tpLH

High-to-Low

Output Oisable Time

tRAZ

Output Enable Time

tR7A

TRUTH TABLE
Drivers

-

I1S
1
ns

Receivers

01

TxEN

STB

Tx

Rx

STB

DO

X

X

H

Z*

X

H

Z*

X

L

L

L

H

L

L

H

H

L

L

L

L

H

L

H

L

H

*GNO SVOO S VCCX = Oon~ Care

*VSS SVTx S VOO X = Oon't Care

MOTOROLA COMMUNICATIONS DEVICE DATA

MC145705.MC145706.MC145707

2-933

PIN DESCRIPTIONS
VCC
Digitill Power Supply
This digital supply pin is connected to the logic powersupply.
This pin should have a 0.33 j.lF capacitor to ground.
GND
Ground
Ground return pin is typically connected to the signal ground
pin of the EIA-232D connector (Pin 7) as well as to the logic
power supply ground.
VDD
Positive Power Supply
This is the positive output of the on-chip voltage doubler
and the positive power supply input of the driver/receiver
sections of the device. This pin requires an extemal storage
capacHor to filter the 50% duty cycle voltage generated by the
charge pump.
VSS
Negative Power Supply
This is the negative output of the on-chip voltage
doublerlinverter and the negative power supply input of the
driver/receiver sections of the device. This pin requires an
extemal storage capacitor to filter the 50% duty cycle voltage
generated by the charge pump.
TxEN
Output Enable
This is the driver output enable pin. When this pin is in logic
low level, the condition of the driver outputs (Tx1-Tx3) are
in keep OFF (mark) state.
STB
Stand-By
The device enters the stand-by mode while this pin is
connected to the logic high level. During the stand-by mode,
driver and receiver output pins become high-impedance state.
In this condition, supply current ICC is below 10 l!A(Typ) and
can be operated with low current consumption.

C2+, C2-, C1+,C1Voltage Doubler And Inverter
These are the connections to the internal voltage doubler
and inverter, which generate the VDD and VSS voltages.
Rx1, Rx2 (Rx3)
Receive Data Input
These are the EIA-232-E receive signal inputs. A voltage
between +3 and +25 V is decoded as a space, and causes
the corresponding DO pin to swing to ground (0 V). A voltage
between -3 and -25 V is decoded as a mark,and causes the
DO pin to swing up to Vcc.
001, 002 (003)
Data Output
These are the receiver digital output pins, which swing from
VCC to GND. Each output pin is capable of driving one LSTTL
Input load.
Output level of these pins is high-impedance while In
standby mode.
011, 012 (013)
Data Input
These are the high-impedance digital input pins to the
drivers. Input voltage levels on these pins must be between
VCC and GND.
The level of these input pins are TTUCMOS compatible.
Tx1, Tx2 (Tx3)
Transmit Data Omput
These are the EIA-232-E transmit signal output pins, which
swing toward VDD and VSS. A logic 1 at a DI input causes the
corresponding Tx output to swing toward VSS. The actual
levels and slew rate achieved will depend on the output loading
(RUCL).
The minimum output impedance is 300 n when tumed off.

SWITCHING CHARACTERISTICS
Driver

- +3V

Driver

f

STB(INPUT)

1

+1.5V

- +5V

+1.5V
OV

OV
+5V

VOH
Txl-3 (OUTPUT)

Txl-3 (OUTPUT)

VOH

HIGHZ

- VOL
IOAZ

Receiver
Rxl-3

,---------.,

}

(INP~ 50%

- +3V
OV

IOZA

Receiver

f

STB(INPUT)

VOH

+1.5V

1

- +5V

+1.5V
OV
VOH

001-3 (OUTPUT)
- VOL
If

001-3 (OUTPUT)

Ir
lRAZ

MC145705.MC145706.MC145707
2-934

MOTOROLA COMMUNICATIONS DEVICE DATA

MOTOROLA

-

SEMICONDUCTOR
TECHNICAL DATA

TCA3385

Advance Information

Telephone Ring Signal Converter

,.,

The TCA3385 is a high efficiency telephone ring si'gnal converter designed for
use with the TCA3386 (it can also be used stand-alone). These devices, together
with a microprocessor, form the basis for a high-performance feature telephone
set.
The circuit includes a switching regulator which converts the ring signal from the
telephone line into a DC supply signal suitable for powering the other devices in
the telephone, e.g. TCA3386 and the MPU, during the ringing phase.

DP SUFFIX
PLASTIC PACKAGE
CASE 626

• High efficiency step-down DC/DC converter with linear input impedance
• Power derived from rectified AC ring signal or DC voltage
• Drive output for external PNP transistor
• System supply voltage determined by external transistor, coils and diodes
FPSUFFIX
PLASTIC PACKAGE
CASE 751G

• Two modes of operation: fixed internal or programmable ring detectthreshold
(7 to 35V)
• Programmable input impedance between 3K and 15Kohms
• Ring detect output for microprocessor

ORDERING INFORMATION

• Lightning and mains protection
• Applications: telephone set, answering machine, home appliance, etc ...

TCA3385-DP Plastic DIP
TCA3385-FP SO package

BLOCK DIAGRAM AND TYPICAL APPLICATION CIRCUIT

ToMPU

MOTOROLA COMMUNICATIONS DEVICE DATA

TCA3385
2-935

~-----~

-----~-------

TCA3385 PIN DESCRIPTIONS

Pin 1 GND, GROUND
This is the reference ground for the overall system.

Pin 7 MS, MODE SELECT
An external resistor RL connected between this pin
and ground sets the value ofthe ri~g detectthreshold.

Pin 2 Vee' POWER SUPPLY
The output is a current which will establish a voltage
defined by the load circuit and the voltage regulator
(typically 5-6 volts for telephone application).

If RL = 0, Mode 1 is selected and a fixed 12 volt level
is automatically chosen by the internal level sensor
circuitry.

Pin 3 DRV, DRIVE OUTPUT
This output directly drives the base of the PNP transistor of the switch mode power supply system.

Otherwise Mode 2 is selected and RL determines the
value of the ring detect threshold. In Mode 2 RL also
affects the input impedance of the circuit.

Pin 4 CO, CURRENT OUTPUT
This pin provides constant current output for charging
the external capacitor Cosc '

Pin 8 ROO, RING DETECT OUTPUT
This is a digital output for a microprocessor which
indicates that a ring signal has been detected. This pin
will shift from low to high each time the input voltage
passes the preset threshold voltage.

Pin 5 L1, LINE INPUT
This pin can be driven either by a DC voltage or a non
filtered rectified AC voltage. In a typical telephone
application, it is connected to the positive side of a
diode bridge before the twisted pair cable.

Depending on its load (resistive or capacitive), the
signal at this pin can either remain high during the ring
time, or be a square wave at twice the ringing signal
frequency.

Pin 6 Rin
An external resistor Rin connected between this pin
and LI sets the input impedance of the circuit.

GND
Vee
DRV
CO

•

8

ROO

7

MS

3

6

Rin

4

5

1
2

OlL8 pins

TCA3385

2-936

LI

•

16

ROO

2

15

N.C.

Vee

3

14

MS

N.C.

4

13

N.C.

DRV

5

12

Rln

N.C.

6

11

N.C.

CO

7

10

LI

N.C.

8

9

N.C.

GNO

1

N.C.

SOIC wide 16 pins

MOTOROLA COMMUNICATIONS DEVICE DATA

ABSOLUTE MAXIMUM RATINGS
Parameter

Line Voltage
Input Impedance
Maximum Peak Current (crowbar on)
Storage Temperature Range
Operating Junction Temperature

Value

Unit

120

Vrms

3K to 15K

Ohms

500

mA

-65 to +150

°C

150

°C

Devices should not be operated at or outside these values, Actual device operation should be restricted
to within the "Recommended Operating Limits",
RECOMMENDED OPERATING LIMITS
Parameter

Symbol

Operating Ambient Temperature Range
Line Voltage

Ta

Min

Typ

0

. Vin

Line Source Impedance

Zs

Max

Unit

70

°C

90

Vrms
Ohms

500

THERMAL DATA
Parameter

Thermal Resistance Junction-Ambient
Plastic Package Case 626
SO Package Case 751 G

MOTOROLA COMMUNICATIONS DEVICE DATA

Value

Unit

°cm
90
110

TCA3385

2·937

ELECTRICAL CHARACTERISTICS

Parameter

Symbol

Min

Typ

Max

Ring Detect Output Voltage High

Voh

Vee
-0.93

Vee
-0.7

Vee
-0.57

Ring detect Output Voltage Low

Vol

11

20

mV

Turn-on Threshold Input Voltage

Vd1

12

13.0

V

11.2

Unit

V

(Mode 1, RL =0, ILoad=O)
Threshold Temperature Drift

DVd1

-5

mVrC

(Mode 1, RL =0)
On/Off Threshold Hysteresis

Hys1

1.2

Vd2

8

1.8

2.4

V

35

V

(Mode 1, RL =0, ILoad=O)
Turn-on Threshold Input Voltage
(Mode 2, limit fixed by ext res RL)
Threshold Temperature Drift

D Vd2

-20

mVrC

(Mode 2)
On/Off Threshold Hysteresis

Hys2

0.5

7

V

Id up

0.5

1.5

2.5

mA

Low State (V RDO < Vee /2)

60

100

140

High State (V RDO > Vee /2)

10

20

26

3.1

3.45

V

1..8

2.3

V

.(Mode 2)
Ring Detect Output Pull-up Current
(V in = 15V)
Ring Detect Output Pull-down Current

Vee Level (Ring Detector Enabled)

IIA

Id down

Vee on

2.75

@ Vee max = 5.5V

Vcc Level (Ring Detector Disabled)

Vee off

1.40

@ Vee max = 5.5V

Ring Detect Output Rise Time

tr

1

lIS

!t

4

lIS

Vdrip

0.25

(no capacitor)
Ring Detect Output Fall Time
(no capacitor)
Ring Detect Output Ripple

0.5

Vpp

(Crd = 0.47~F, f = 50Hz, no load)

TCA3385
2-938

MOTOROLA COMMUNICATIONS DEVICE DATA

SWITCHMODE POWER SUPPLY
Parameter

Symbol

= 36mA)
Output Power (Vin = 90V rms, f = 50Hz)

Vee Output Voltage (lioad

Min

Typ

Max

Unit

Fixed by Zener diode

Vee

600

Pout

mW

%

Power Supply Efficiency

Eff

50

55

Switching Frequency

Fs

25

35

45

KHz

0.5

0.7

Vpp

(Vin

= 40v, Rin = 500Kn)

Output Voltage Ripple
(lioad

Vee rip

= 36mA, Cload = 220IJ.F, Vin = 90V rms)

Cose Charge Current
(Vin = 20V, Rin = 500Kn, RL
Cose Discharge Current
(Vin

leharge

3.1

3.5

4.1

mA

Idiseh.

11

18

25

mA

= 0)

= 20V, Rin = 500Kn, RL = 0)

LINE INPUT AND PROTECTION
Symbol

Parameter
Input Impedance

Min

Typ

25

50

3

~

Max

Kohm

Zin

Off-state (Vin = 4.5V, Rin = 500Kn, RL
On-state (Vin > 25V, Mode 1, RL = 0)
Fixed by external resistance Rin

= 0)

15

100

On-state (Vin > 25V, Mode 2)

3

Rin+ 2R L 15

~

Fixed by external resistance Rin and RL
Non-linearity @ 35 !

ffi

~

~

g

-

f- 0.2

-

f-O.l
0.0§...

0.1

E
~ 0.07
a'i 0.05
in

0.Q3

0.5

~

-

- - -""""'"

~ --+-R9JClti

;;;...- i""'"

= rlt) 6JC --t--+- R6JC = 10"C!W MAX--r:: D CURVES APPLY FOR PO'!"ER·::
: PULSE TRAIN SHOWN
:
- READ TIME AT 11

P(pk)
I

_._1

~0.02

:-

0.01
o(SINGLE PULSE)

11

1---

I

=

.12 -_,

DUTY CYCLE, D = 11n2

I

0.02

0.01
0,02

I I I II
0.05

0,1

TJ(pk) - TC

I
0.2

0.5

i

~~J

I
10

= P(pk) 6JC(I)-

11
20

50

100

200

I, TIME (m,)

Figure 3. Thermal Response

MJD243.MJD253
2-948

MOTOROLA COMMUNICATIONS DEVICE DATA

500
TJ = 15O'C

'"i'5

100
70
50

c

30
20

a:
a:
::>
u
u

~

=

1"2V-

VCE
VCE

--

ts::

125'C

z
;;;:
I-

r-;::'it

55'C

,

+2.5

So

0.2

0.1

0.4

0.6

~
8

o

o. 2

~

- 1

-D
~

= 10 I:P'
1I1~_15

1/ III
IIIII

IdlB

~II

IIIII

Figure 4. DC Current Gain

Figure 5. "On" Voltages

'APPLIES FOR IC/IB .. hFEI3

+30V
~ VCC

./

25'CIIO~ f-"'"

'lIvc FOR VCElsa11

.....-:;

55'C 10 25'C

II'

~

- 2 6VB FORVBE

-2.5W+ttff""'
0.04 0.06
0.1

0.2

-J
f/

IC. COLLECTOR CURRENT IAMPI

:;; -1.5

~

i---

0.2
0.4 O.S
1
IC. COLLECTOR CURRENT IAMPI

~ -0.5



0.4

I::;:?'"

= 10

+2

+1
o +0.5

:>

;>

§!

1

~

~

,/
_.

0.6 VBE@VCE = 1 V

"I

I- r VCElsa11
0
0.1
0.04 O.OS

g +1.5

It!

IIII
IIII
IIII

'"~
~

0.04 0.06

r-

0.8 VBElsa11 @ IC/IB

""if,."';:

5

TJ

~
~
~

......

//

= 25'C

r1.2

I~

10
7

cr

-

1.4

300 200

0.4

0.6

/

RC

o-~---,\RNB\----?-_t-C
f'i) ~OPE

j;

~

V

/

Ir• If" 10 ns
DUTY CYCLE = 1%

~
- 55'C 10 25'C

II

~II' 01

51

-4V
RB and RC VARIED TO OBTAIN DESIRED CURRENT LEVELS
01 MUST BE FAST RECOVERY TYPE. eg:
MBD5300 USED ABOVE IB = 100 mA
FOR PNP TEST CIRCUIT.
MSDS100 USED BELOW IB = 100 mA
REVERSE ALL POLARITIES

- f--

1

IC. COLLECTOR CURRENT IAMPI

Figure 7. Switching Time Test Circuit

Figure 6. Temperature Coefficients

500
TJ
VCC
IC/IB

300
200
100
I 70
~ 50
t= 30

25'C
= 30V
= 10

2000

-

r-.

..... 1.....

20
10
7
5
0.04 0.06

.....

Id @ VBEloffl

..,".Q J
0.1

0.2

0.4

Ir -

0.6

1

IC. COLLECTOR CURRENT IAMPI

Figure 8. Turn-On Time

MOTOROLA COMMUNICATIONS DEVICE DATA

= 5 V-

~

~

TJ = 25'C
VCC - 30V
IC/IB
10
IBI
IB2

1000t700
500

.-

Is

]: 300
~ 200
t=

-

=

=
=

......

.>

-

100
70
50
30
20
0.04 O.OS

If

I":!..

I
0.1

0.2

0.4

O.S

1

IC. COLLECTOR CURRENT IAMPI

Figure 9. Turn-Off Time

MJD243.MJD253
2-949

200

- r- -

100

~ 70
z~

~

~

()

TJ 1= J50CI-

50

Cib

-

30

c.3

......

20

10

1

1. . . . .

Cob

i+_

II

10

r-20

30

50

70 100

VR. REVERSE VOLTAGE {VOLTSI

Figure 10. Capacitance
Voo 15

+5 VOLTS

STl

Six resistors and two capacitors on two wire side can have 5% tolerance.

Component values shown lor a Soon: system.

P-r::--=--'Vv---r---.-AECEIVE IN (VAX)
RB
30K RTX230.9K

I-'-'-----!---'Vv-'-"~J::~. ~[ TRANSMIT OUT
~(VTX)
V

Figure 11. Application Circuit

MJD243.MJD253
2·950

MOTOROLA COMMUNICATIONS DEVICE DATA

NPN

MOTOROLA

-

MJE270

SEMICONDUCTOR
TECHNICAL DATA

PNP

MJE271
2.0 AMPERE

COMPLEMENTARY SILICON
POWER TRANSISTORS

COMPLEMENTARY
POWER DARLINGTON
TRANSISTORS

... designed specifically for use with the MC3419 Solid-State Subscriber Loop Interface Circuit (SUC).

100 VOLTS
15 WATTS

•

High Safe Operating Area
ISIB @40V, 1.0 s = 0.375 A -

TO-126

• Collector-Emitter Sustaining Voltage
VCEO(sus) = 100 Vdc (Min)
•

High DC Current Gain
hFE @ 120 mA. 10 V = 1500 (Min)

STYLE 3:
PIN 1. BASE
2 COLLECTOR
3. EMITIER

MAXIMUM RATINGS
Rating

Symbol

Value

Unit

VCEO

100

Vdc

Collector-Base Voltage

VCB

100

Vdc

Emitter-Base Voltage

VEB

5.0

Vdc

IC

2.0
4.0

Adc

Base Current

IB

0.1

Adc

Total Power Dissipation @ TC = 25°C
Derate above 25°C

Po

15
0.12

Watts
W/oC

Total Power Dissipation @ TA = 25°C
Derate above 25°C

Po

1.5
0.012

Watts
W/oC

TJ, Tstg

-65 to +150

°C

Collector-Emitter Voltage

Collector Current -

-

Continuous

Peak

Operating and Storage Junction
Temperature Range

THERMAL CHARACTERISTICS
Characteristic
Thermal Resistance, Junction to Case

Symbol

Max

Unit

ROJC

8.33

°C/W

83.3

°C/W

Thermal Resistance, Junction to Ambient

NOTES:
1. DIMENSIONING AND TOlERANCING PER ANSI

Y14.5M,1982.
2. CONTROLLING DIMENSION: INCH.
3. 077-01 THRU·06 OBSOLETE, NEW STANDARD

077-07.
INCHES
MAX
M'N
0.425 0.435
0.295 0.305
0.095 0.105

"M
A
B
C
0
F
G
H

M'N
10.80
7.50
2.42
0.51

J

0.39
14.61
3"
3.76
1.15

4.01
1.39

0.64

088

3.69
1.02

3.93

K
M
Q

R
S
U
V

0.020

0.026

2.93
2.39

0.115 0.130
0.094 BSC

1.27

0.050 0.095
0.D15 0.025
0.575 0.655
3°TYP
0.148 0.158
0.045 0.055
0.025 0.035
0.145 0.155
0.040

CASE 77-07

TO-225AA TYPE

MOTOROLA COMMUNICATIONS DEVICE DATA

MJ E270.MJE271
2-951

ELECTRICAL CHARACTERISTICS (TC = 25°C unless otherwise noted)

I

Symbol

Min

Max

Unit

VCEO(sus)

100

-

Vde

Collector Cutoff Current
(VCE =100 Vde. IB =0)

ICEO

-

1.0

mAde

Collector Cutoff Current
(VCB =100 Vde. IE =0)

ICBO

-

0.3

mAde

Emitter Cutoff Current
(VBE =5.0 Vde. IC =0)

lEBO

-

0.1

mAde

500
1500

-

-

2.0
3.0

-

2.0

Characteristic
OFF CHARACTERISTICS
Collector-Emitter Sustaining Voltage (1)
(IC =10 mAde. IB =0)

SECOND BREAKDOWN
Second Breakdown Collector Current with Base Forward Biased
(VCE = 40 Vde. t = 1.0 s. non-repetitive)
ON CHARACTERISTICS (1)
DC Current Gain
(lc =20 mAde. VCE =3.0 Vde)
(lC =120 mAde. VCE =10 Vde)

-

hFE

Collector-Emitter Saturation Voltage
(lC =20 mAde. IB =0.2 mAde)
(lC =120 mAde. IB =1.2 mAde)

VCE(sat)

Base-Emitter On Voltage
(lc =120 mAde. VCE =10 Vde)

VBE(on)

Vde

Vde

DYNAMIC CHARACTERISTICS
Current Gain - Bandwidth Product (2)
(lc =0.05 Ade. VCE =5.0 Vde. f test =1.0 MHz)
NOTES:
(1) Pulse Test: Pulse Width
12) fT = I hfe I. f test

~

300 IJ.S. Duty Cvcle

~

2.0%.

FIGURE 2 - SAFE OPERATING AREA

FIGURE 1 - DC CURRENT GAIN
10.000
7000
5000

""
«
'"

3000

150°C

~-

ffi

1000
700
'-'
c
500

a

300

;;;

~

,..

::.

1\.."

,/

0:
0:

;

25)oC

VCE = 3.0 V

r--

-55°C

I-

~

0:
0:

1\

:I

1.0

de ~

0.5

'-'

MJE270/MJE271

0:

C

t;
~

./

\

/

100
0.015

8
E

:\.

0.03

0.05 007 0.1

0.3

IC. COLLECTOR CURRENT (AMPS)

MJE270.MJE271
2-952

0.5 0.7

1.0

1.5

0.1
"0.05

;= - .Bonding Wire Limit

r- - - - - Therma) Limit @ TC = 25°C
(Singl. PU)'.1

r-

~--- Second Breakdown Limit
0.01 '-....L....L--:":-J........l....l...::l:-l-~---L---L-7::-...L-.L...J.-:!;:-'~.
1.0
3.0
1.0 10
30
10 100
VCE. COLLECTOR·EMITTER VOLTAGE (VOLTS)

MOTOROLA COMMUNICATIONS DEVICE DATA

MOTOROLA

-

SEMICONDUCTOR
TECHNICAL DATA

MPS6717
MAXIMUM RATINGS
Rating

Symbol

Value

Unit

Collector-Emitter Voltage

VCEO

80

Vde

Collector-Base Voltage

VCBO

80

Vde

Emitter-Base Voltage

VEBO

5.0

Vde

IC

500

mAde

Total Device Dissipation @TA = 25°C
Derate above 25°C

Po

1.0
8.0

Watt
mWrC

Total Device Dissipation @TC = 25°C
Derate above 25°C

Po

2.5
20

Watts
mWrC

TJ, Tstg

-55to +150

°c

Characteristic

Symbol

Max

Unit

Thermal Resistance, Junction to Ambient

ROJA

125

0c/w

Thermal Resistance, Junction to Case

ROJC

50

°CIW

Collector Current -

Continuous

Operating and Storage Junction
Temperature Range

CASE 29·05, STYLE 1
TO·92 (TO·226AE)

THERMAL CHARACTERISTICS

ONE WATT
AMPLIFIER TRANSISTOR
NPN SILICON
Refer to MPSW05 for graphs.

I

ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted.)
Characteristic

Symbol

Min

Max

Unit

Collector-Emitter Breakdown Voltage(l)
(lc = 1.0 mAde, IB = 0)

V(BR)CEO

80

-

Vde

Collector-Base Breakdown Voltage
(lc = 100 /LAde, IE = 0)

V(BR)CBO

80

-

Vde

Emitter-Base Breakdown Voltage
(IE = 10/LAde, IC = 0)

V(BR)EBO

5.0

-

Vde

OFF CHARACTERISTICS

Collector Cutoff Current
(VCB = 60 Vdc, IE = 0)

ICBO

-

0.1

/LAde

Emitter Cutoff Current
(VEB = 5.0 Vde, IC = 0)

lEBO

-

10

/LAde

ON CHARACTERISTICS
DC Current Gain
(lc = 50 mAde, VCE = 1.0 Vde)
(lC = 250 mAde, VCE = 1.0 Vde)

hFE

Collector-Emitter Saturation Voltage
(lC = 250 mAde, IB = 10 mAde)
Base-Emitter On Voltage
(lc = 250 mAde, VCE = 1.0 Vde)

-

80
50

250

VCE(sat)

-

0.5

Vde

VBE(on)

-

1.2

Vde

Ceb

-

30

pF

hfe

2.5

25

-

SMAll-SIGNAL CHARACTERISTICS
Collector-Base Capacitance
(VCB = 10 Vde, IE = 0, f

=

1.0 MHz)

Small-Signal Current Gain
(lC = 200 mAde, VCE = 5.0 Vde, f

=

20 MHz)

(1) Pulse Test: Pulse Width", 300 ,... Duty Cycle'" 2.0%.

MOTOROLA COMMUNICATIONS DEVICE DATA

MPS6717

2·953

MOTOROLA

-

SEMICONDUCTOR
TECHNICAL DATA

4N35
4N36
4N37

6-Pin DIP Optoisolators
Transistor Output
These devices consist of a gallium arsenide infrared emitting diode optically coupled
to a monolithic silicon phototransistor detector.
•
•
•
•
•
•

Convenient Plastic Dual-In-Line Package
High Current Transfer Ratio - 100% Minimum at Spec Conditions
Guaranteed Switching Speeds
High Input-Output Isolation Guaranteed - 7500 Volts Peak
UL Recognized. File Number E54915
VDE approved per standard 0884/8.87 (Certificate number 62054), with additional
approval to DIN IEC380NDE0806, IEC435NDE0805, IEC65NDE0860, VDEOll0b,
covering all other standards llliith equal or less stringent requirements, including
IEC204NDEOl13, VDE0160, VDE0832, VDE0833, etc.
• Meets or Exceeds All JEDEC Registered Specifications
884
• Special lead form available (add suffix "T" to part number) which satisfies VDE08831
6.80 requirement for 8 mm minimum creepage distance between input and output
solder pads.
• Various lead form options available. Consult "Optoisolator Lead Form Options" data
sheet for details.

6-PIN DIP
OPTOISOLATORS
TRANSISTOR
OUTPUT

%

®

MAXIMUM RATINGS (TA

I

=

CASE 730A
PLASTIC

25°C unless otherwise noted)

I

Rating

Symbol

Value

Unit
Volts

SCHEMATIC

INPUT LED
Reverse Voltage

VR

6

Forward Current - Continuous

IF

60

mA

LED Power Dissipation (C, TA = 25°C
with Negligible Power in Output Detector
Derate above 25°C

Po

120

mW

1.41

mwrc

OUTPUT TRANSISTOR
Coliector·Emitter Voltage

VCEO

30

Volts

Emitter-Base Voltage

VEBO

7

Volts

Coliector·Base Voltage

Volts

VCBO

70

Collector Current - Continuous

IC

150

mA

Detector Power Dissipation (a TA = 25°C
with Negligible Power in Input LED
Derate above 25°C

Po

150

mW

1.76

mwrc
1. LED ANODE

TOTAL DEVICE
Isolation Source Voltage (1)
(Peak ac Voltage, 60 Hz, 1 sec Duration)
Total Device Power Dissipation
Derate above 25°C

30--

(a

TA

=

25°C

Ambient Operating Temperature Range
Storage Temperature Range
Soldering Temperature (10 seconds, 1/16" from case)

VISO

7500

Vac

Po

250
2.94

mW
mWrC
°c

TA

-55to +100

Tstg

-55to +150

°c

-

260

°c

2. LED CATHODE
3. N.C.
4. EMITTER
5. COLLECTOR
6. BASE

(1) Isolation surge voltage is an internal device dielectric breakdown rating.
For this test, Pins 1 and 2 are common, and Pins 4, 5 and 6 are common.

4N35.4N36.4N37
2-954

MOTOROLA COMMUNICATIONS DEVICE DATA

ELECTRICAL CHARACTERISTICS (TA

I

= 25°C unless otherwise noted)

I

Characteristic

Symbol

Min

Typ

Max

Unit

VF

0.8
0.9
0.7

1.15
1.3
1.05

1.5
1.7
1.4

V

-

-

10

I'A

18

-

pF

INPUT LED

=

Forward Voltage (IF

10 rnA)

Reverse Leakage Current (VR

,

Capacitance (V

=

0 V, f

=

TA
TA
TA

=

=
=
=

25°C
-55°C
100°C

6 V)

IR

1 MHz)

CJ

OUTPUT TRANSISTOR

Collector-Emitter Dark Current (VCE
(VCE
Collector-Base Dark Current (VCB

=

=
=

10 V, TA
30 V, TA

10 V)

Collector-Base Breakdown Voltage (lC
Emitter-Base Breakdown Voltage (IE
DC Current Gain (lC

=

2 rnA, VCE

=

Collector-Emitter Capacitance (f
Collector-Base Capacitance (f

=

Emitter-Base Capacitance (f

=

=

=

=

TA
TA

=

Collector-Emitter Breakdown Voltage (lC

=
=

25°C)
100°C)

=
=

25°C
100°C

1 rnA)

lOOI'A)

1001'A)

-

0.2
100

-

50
500

nA
I'A

20

nA
V

V(BR)CEO

30

45

70

100

V(BR)EBO

7

7.8

-

400

-

= 0)
= 0)

=

ICBO

1

-

V(BR)CBO

1 MHz, VCE

1 MHz, VEB

-

-

5 V)

1 MHz, VCB

ICEO

0)

hFE

-

CCE

-

7

CCB

-

19

CEB

-

9

V
V

pF
pF
pF

COUPLED

Output Collector Current
(IF = 10 rnA, VCE = 10 V)

TA
TA
TA

Collector-Emitter Saturation Voltage (lC

=

0.5 rnA. IF

=

=
=
=

30

VCE(sat)

-

0.14

0.3

V

ton

-

7.5

10

I's

-

3.2

-

4.7

IC

10 rnA)

Turn-On Time
Turn-Off Time

toff

(IC = 2 rnA, VCC = 10 V,
RL = 100 n, Figure 11)

Rise Time

tr

Fall Time

tf

Isolation Voltage (f

=

60 Hz, t

=

1 sec)

4N35
4N36
4N37

-

1150

-

-

1011

RISO

-

CISO

-

5.7

7500

VISO

'--.

= 3550 Vpk)
= 2500 Vpk)
= 1500 Vpk)
Isolation Resistance (V = 500 V)
Isolation Capacitance (V = 0 V, f = 1 MHz)
Isolation Current (VI-O
(VI-O
(VI-O

-

10
4
4

25°C
-55°C
100°C

10

-

-

-

8

100
100
100

-

-

0.2

rnA

-

Vac(pk)
I'A

n

2

pF

TYPICAL CHARACTERISTICS
2

-

5

~~ ~_ '-! jUIL~~ ON~Y I.

I

~ 1.8 - - - - PULSE OR DC

,/

1.6

V

~

"

I

-TA = -SsoC

~

;i- 1.2

o

I':.t

1--1"1

8:t
2SOC
. H-

100°C

.......

,,'

i

cc

§
~

8

"/""

o. 1

!;

t-.

_.

13o

u

1000

Figure 1. LED Forward Voltage versus Forward Current

MOTOROLA COMMUNICATIONS DeViCe DATA

/

1

::::>
u

I

10
100
IF. LED FORWARD CURRENT (mAl

I--

~

l-

I

1.4

TO:
f= ~ NORMALIZED
IF - 10 rnA

cc

Cl

~

10

~

,

I '
I '
I

I

~

~
':::;
g

~

I

- 0.01

O.S

1
2
S
10
IF. LED INPUT CURRENT (mAl

20

so

Figure 2. Output Current versus Input Current

4N35.4N36.4N37
2-955

28
24

«

~

V"

,-

20

z

-

I-+-

w
g§ 16

aa:

/'
/

~ 12

~

~=10~A-

o

o

NORMALIZED TO TA = 25°C -

a:

~

V

a:

5mA-

a

1

~

0.7

~

0.5

8

I /
IJ
II.

9

I
~

I-'"

/

8

V

10

2mA_
lmA10

2345678
VCE. COLLECTOR·EMITTER VOLTAGE (VOLTSI

~

0.2

o

9 0.1

Figure 3. Collector Current versus
Collector-Emitter Voltage

- 60

-40 -20
0
20
40
60
TA. AMBIENT TEMPERATURE (OCI

80

100

Figure 4. Output Current versus Ambient Temperature

100
50

VCC

10V

20

~

RL

~ 10

If

1000

1=

-40
60
TA. AMBIENT TEMPERATURE (OCI

80

1
0.1

100

RL

0.2

Figure 5. Dark Current versus Ambient Temperature

100
70
50

~

VCC

1=

15

10

Z

7
5

~
j

~
~

10

"I'

"~

0.5 0.7 1
2
5 7 10
20
IF. LED INPUT CURRENT (mAl

Figure 7. Turn-On Switching Times

4N35.4N36.4N37
2-956

'\.

H

[\

1
2
5
10
IF. LED INPUT CURRENT (mAl

50

100

10V

V
-...!L =

7

lOPO

V

100

5

~

50 70100

20

VCC

~ 20
~
1=
I±: 10

100

0.2

I,

~

Figure 6. Rise and Fall Times

10V

~
1
0.1

0.5

-

100
70
50

~1

20

~

100l

'1 0
1
0.1

0.2

0.5 0.7 1
2
5 7 10
IF. LED INPUT CURRENT (mAl

20

50 70100

Figure 8. Turn-Off Switching Times

MOTOROLA COMMUNICATIONS DEVICE DATA

0
IF

0

IS

/
1/

7/iA

lB

6/iA

6

CL~D

CCB'

~ 14

..-

5/iA

~

z

~

L'i

3/iA

I

B

u

CCE

o

0.05

0.2

0.1

Figure 9. DC Current Gain (Detector Only)

f':

I

.

1
2
5
V, VOLTAGE (VOLTSI

10

20

50

WAVEFORMS
=

INPUT PULSE

l-

-.JI

10 V

~10011

I

I
,
10%~-

,,:1:: ~'"

90%

I
I

____ I_Z: ___ -

--:.1-, ______ :_ ,-l-___
: II

~: I'+- tr

=

INPUT CURRENT ADJUSTED
TO ACHIEVE IC = 2 rnA.

0.5

Figure 10. Capacitances versus Voltage

TEST CIRCUIT

VCC

!;;::.

1

f--

20

r-

i

1 flA

lB

i'

CES

2/i A

10
12
14
16
VCE, COLLECTOR·EMITTER VOLTAGE (VOLTS)

r-r--

1

12

;::10

4/iA

= 1 MHz

f

~

I

ton~

I

~

I r
~
I

OUTPUT PULSE

I

:lr ""OM' ~LG

+

LINEAR TO
COMPANDED

DAC

2.4 VOLT ./
REFERENCE

rrr

DIGITAL SIGNAL PROCESSOR

ANALOG INTERFACE
AND
CODEC·FILTER

SCPEN

SCPCLK

SCP Rx

SCP Tx

PDI/RESET

~

Telecom

..

Application Notes and Technical Articles

AN872
AN893
ARTICLE 1
AN943
AN949
AN968
AR239
AN933
AN937
AN940
AN957
AN958
AN959
AN960
AN1002
AN1003
AN1004
AN1006
EBl12
ARTICLE 4
AN1077
AN1081
AN946
AN948
EB111
ARTICLE 5
ARTICLE 6
AN1510

MCl4402 Mono-Circuit Applications Information ........................................... .
Understanding Telephone Key Systems ................................................... .
Telephone Quality CVSD Codecs Using New Bipolar Linear/12L I.C. . ......................... .
UDLT Evaluation Board ................................................................. .
A Voice/Data Modem Using the MC145422126, MC145428, and MCl4403 ..................... .
A Digital Voice/Data Telephone Set ....................................................... .
Implementing Integrated Office Communications ........................................... .
A Variety of Uses for the MC34012 and MC34017 Tone Ringers .............................. .
A Telephone Ringer Which Complies with FCC and EIA Impedance Standards ................. .
Telephone Dialing Techniques using the MC6805 ........................................... .
Interfacing the Speakerphone to the MC34010/11/13 Speech Networks ....................... .
Transmit Gain Adjustments for the MC34014 Speech Network ............................... .
A Speakerphone with Receive Idle Mode .................................................. .
Equalization of DTMF Signals Using the MC34014 ......................................... .
A Handsfree Featurephone Design Using the MC34114 Speech Network
and the MC34018 Speakerphone ICs ................................................. .
A Featurephone Design, with Tone Ringer and Dialer, Using the MC34118 Speakerphone ICs .... .
A Handsfree Featurephone Design Using the MC34114 Speech Network
and the MC34118 Speakerphone ICs ................................................. .
Linearize the Volume Control of the MC34118 Speakerphone ................................ .
The Application of a Telephone Tone Ringer as a Ring Detector .............................. .
LSI for Telecommunications ............................................................. .
Adding Digital Volume Control to Speakerphone Circuits .................................... .
Minimize "Pop· in the MC34119 Low Power Audio Amplifier .................................. .
Limited Distance Modem ................................................................ .
Data Multiplexing ...................................................................... .
The Application of a Duplexer ........................................................... .
IC Trio Simplifies Speech Synthesis ...................................................... .
Turn I/O Data Port Into Speech Port ...................................................... .
A Mode Indicator for the MC34118 Speakerphone Circuit .................................... .

MOTOROLA COMMUNICATIONS DEVICE DATA

4-3
4-8
4-15
4-21
4-31
4-37
4-44
4-49
4-58
4-65
4-83
4-95
4-97
4-99
4-101
4-119
4-132
4-150
4-151
4-152
4-156
4-160
4-163
4-173
4-183
4-185
4-189
4-190

4-1

..

4-2

MOTOROLA COMMUNICATIONS DEVICE DATA

MOTOROLA

-

SEMICONDUCTOR
APPLICATION NOTE

AN·872
Application Note

MC14402 MONO·CIRCUIT
APPLICATIONS INFORMATION
by
Richard L. Hall and Michael D. Floyd
Telecom Systems Engineering

This application note is intended to ease customer evaluation of the Motorola MCI4402 PCM mono-circuit, particularly when using the Motorola Mono-circuit Evaluation
Board. Schematics and artwork of this board are given as
well as layout guidelines for designing the mono-circuit into a
custom PC board. Analog testing considerations are mentioned to help sidestep some of the troublesome aspects of
codeclfilter evaluations.
EVALUATION BOARD DESCRIPTION
The Motorola Mono-circuit Evaluation Board is a small
PC board that contains all necessary clock circuitry for
operating the MCI4402. Coaxial connectors allow access to
the analog input/ output ports and the only other connections required are to the three power terminals-VDD, VSS
,and VAG. The schematic for this board is shown in Figure I
"while the artwork is given in Figure 2.
The clock circuitry uses a 2.048 Mhz crystal to produce the
2.048 Mhz data clock as well as the 8 kHz sync signal. The
8 kHz sync is an 8-data-c1ock-wide pulse that is connected to
the RCE, TDE and MSI inputs of the mono-circuit. RCE
and TDE are the receive and transmit enables respectively,
while MSI is the 8 kHz reference input. The 8 kHz sync is
generated by the MCI4417 TSAC (Time Slot Assigner Circuit).
Options are available to help evaluate different channel
parameters. These include:
• 600 or 900 ohm channel impedance
• RSI peak overload voltage of 3.15 or 3.78 volts
• TTL or CMOS logic levels
• Transmit and Receive gain adjustment (RxO gain only)
• A or MU-Iaw coding
• Power-down capability

MOTOROLA COMMUNICATIONS DEVICE DATA

These options are selected by solderable wire straps (SI-S6)
as described in the Strapping Information Chart. The straps
can be replaced by DIP switches if desired and can be obtained from:
Grayhill Inc.
561 Hillgrove Avenue
La Grange, Illinois 60525
PIN
78J05
78J02
78JOI

Name
SI
S2,S3
S4-S6

Qty
I
2

3

Figure 3 shows the physical location of the strap points as
well as the component layout. The solid lines indicate the
normal strap positions as shipped from the factory which
select Mu-Iaw, 900 ohm, CMOS, 3.78 volts peak operation.
The straps EI-EIO allow reprogramming of the clock lines to
provide different clock schemes. Refer to the schematic in
Figure I for changing these straps.
TEST CONSIDERATIONS
Input/Output Levels
Obtaining valid test data is highly dependent upon establishing the proper input/output voltage levels. However, this
can be a somewhat confusing task since the mono-circuit can
use three different peak overload voltages-2.5, 3.1 and 3.8
volts. The evaluation board permits selection of either 3.1 or
3.8 volts. For 3.1 volts, the proper input/output level for a 0
dBmO test signal is + 6 dBml600 ohms (1.5455 volts rms).
For 3.8 volts, 0 dBmO corresponds to +6 dBml900 ohms
(1.893 volts rms). Usually, measurement levels are referenced

AN872
4-3

CMOS
S5

VSS---a
VOO

VSS

VOO

C9

V

50QPF

R-ICN
I,,"Law)
S4
0

VSS

21

R2
10k

~

3.78V
S6

RS
51 k

RxO

Digital
Ground

4
TOO
RxG

EB

E9

ROC

Data Clock

TOC
CCI
Txl

RCE
TOE

Tx

MSI

>-~~----~----~~~~~-Tx
+Tx
Vag
MCI4402
Mono-circuit

VOO
TOE TOO TOC ROC

RED

---I....- c

)>-----.....

Mono-circuit Asynchronous/32 Channel Synchronous Clock Circuit

O.I.F
C5

VOO

r-------------------,
,
I

IVAGI
Analog
Ground

)>----6----t~_(

RCE

VOO

GRN

BlK

RO~

l
I
I

VSS

I
I SI

: lSB

I

I

I

lL.

I
___________________ ..JI

2.048 MHz

o

YI

04

18

02

03

DO

01

TxE

VOO
I
12 VCC

20M

RI ....-'V'''''-..

VOO

Till

MCI4069
13
10

14

lE

Enable

16

RxE 15 NC

UI
MCI4417

NC

DC
II

CI r30PF

E2
YOut

Yin

VOO

02
C2
14

01

13
01

11
CI

-::"' Ground

NC
128 kHz

------------

8kHz

03
...LOigital

02
U2
MCI4013

8kHz

E3

E4

15
MSI
Out

r1-,Analog

V

Ground

MSI
In

10

-=
FIGURE 1 - MC14402 Switch Programmable Evaluation Board PIN 618-1030

AN872
4-4

MOTOROLACOMMUNICATIONS DEVICE DATA

distortion and gain tracking should be avoided since these
parameters involve very low voltage levels that require a
selective voltmeter function for accurate results. Also, attention should be given to correct selection of input/output
parameters on programmable test gear such as the HewlettPackard 3779 PMA and others.

to 0 dBmO to avoid possible confusion over absolute levels.
For example, an absolute idle noise measurement of 21
dBrnC becomes 15 dBrnCO when referenced to 0 dBmO
(where 0 dBmO= +6 dBm in our system).
Noise
Special care has been taken in the layout of the evaluation
board to minimize noise corruption. The analog and digital
sections are isolated from each other and bypassing is present
to reduce high frequency noise. The use of shielded cable for
analog test lines is recommended to prevent extraneous environmental noise pickup as well as the use of a power supply
reasonably free of high frequency noise. A 500 pF capacitor
has been put on the RxO output to bypass any radiated asynchronous noise that might be picked up at this node.

LAYOUT GUIDELINES FOR PC BOARDS
• Bypassing of both VOO and VSS to VAG with 0.1
microfarad ceramic capacitors (or any other capacitors
with good high frequency behavior) as close to the part
as possible.
• Isolate analog lines from digital sections. The monocircuit pinout facilitates this by keeping digital and
analog pins on opposite sides of the chip.
• Use gain-setting resistors in the range of 50 kO > R > 5
kO to avoid high impedance nodes in the analog section.

Test Equipment

• If VLS is tied to VAG for TTL level selection, then this
connection should be a short, direct, low inductance
trace.
• In a dual supply environment, VOO and VSS should be
connected before VAG (ground).

There are many different pieces of telecommunications
test gear on the market and most will be more than adequate
for testing codec/filter parameters. However, the use of
wideband measurement devices for such tests as quantizing

MONOCKT ASYNC I 32 CHAN SYNC

CLOCK

CKT

r
V55

618- 1029

V55

voo

EN

\ ld~:di
-=
::r~
-

YIN

YOUT

•

•

voo

V55

NOTE: Drawings are not actual size.
FIGURE 2 -

MOTOROLA COMMUNICATIONS DEVICE DATA

• • •

Evaluation Board Artwork

AN872

4·5

S6

S5

3.78113.15
Rx
Analog Out

R8~~r
1
~ 0:. •

C5C:>
C9

~R3:~2

CMOS 1 ITTL

E5

l

U5

•

S2A

11MU

600

C6C)
S2B
S3A
• TT

Tx

E~

.~,

E1~

~~

• --=--R6
--=--R7

~ ~It~I

........

Digital GND
Digital Supply

S4

Time Slot
1.
• MSB

•

--

•

Data Clock

- - - - - -...

...

E8 - - E7

•

:.-...: S1

•-...•

Enable

•

•

1~MI~NIUP
1

S3B

•

•

•

Analog I n .

•

.~~
•
VAG

VSS

• • •

R9

•••

~

@@

VDD

MSIOut

LUQUUOw

•

~~~~~~

~.~
~

•

Access

NOTE: Solid line indicates normal strapping as shipped from factory; dashed lines indicate opiional straps as described below in the
Strapping Information Chart.
Reference Voltage

Reference Impedance

(56)

(S2A)

+6/+6
+6/0
010
010
+6/+6
+6/0
010
010

6000

3.15 V

~O

3.78 V

~O

6000

* Rout is located

InputlOutput Levels
(dBm)

R2

R3

-

-

16.6 k

10 k

-

-

-

-

12.5 k

10 k

-

-

R4
10k
10 k
20 k
16.6 k
10 k
10 k
20 k
25 k

R5
10 k
10 k
10 k
10 k
10 k
10 k
10 k
10 k

Rout*
Jumper

6000
6000
Jumper
Jumper

9000
9000
6000

between Rx analog out and RxO output underneath the board.

NOTE: Drawings are not actual size.

FIGURE 3 - Component Layout

Strapping Information Chart
Sl

S2A
S2B
S3A
S3B
S4

AN872
4-6

S5

These straps select via VI (MCI4417 TSAC) one
of 32 possible time slots in the 8 kHz frame.
When used in conjunction with another board,
performance in different time slots can be
evaluated. (that is TDE
RCE).
Selects 600 or 900 ohm input impedance.
Selects A or Mu-law coding.
Selects either TTL(TT) or CMOS(CM) logic
levels. The TTL levels swing from VDD and
VAG; CMOS levels swing from VDD to VSS.
Powers device up or down. DN = Powered down
and VP = Powered up.
Normally loops RDD to TDD. When R-ICN is
strapped, Mu-law receive idle channel noise can
be measured (RDD= 1 111 1111).

'*

S6

Rl,R3
R4,RS

Rout

Controls digital ground of clock logic. When
CMOS is strapped, digital ground=Vss; when
TIL is strapped, digital ground = VAG. Note
that this strap must agree with the selection on
S3A.
Selects either 3.78 or 3.15 volts peak overload
voltage.
Adjusts RxO output level where gain = - R3/R2
(optional).
Adjusts Tx Analog In level where gain=
-R4/RS.
A I kilohm pullup resistor is needed when VAG
output is used by itself to provide ground return
for RxO or RxO. If VAG is tied to system power
ground, this resistor can be deleted.
Determines output impedance.

MOTOROLA COMMUNICATIONS DEVICE DATA

APPENDIX

o --

A DB By Any Other Name •••
The following is a brief discussion of decibels and how
they are used in the telephone industry in an attempt to lessen
the notorious confusion this term can create.
Engineers are very familiar with the equation definition of
a decibel which is:

Decibels = dB = 20 log V2
VI

(1)

or its corollary:
dB = IOlog~f.

(2)

The use of the logarithmic function eases the use of the large
range of voltage numbers encountered in the telephone industry. A decibel is only a relative term; it defines the difference between two absolute voltage levels.
Which now brings us to the absolute decibel-the dBm
(decibel milliwatt). A dBm is equivalent to a milliwatt of
power delivered into a reference impedance-usually 600
ohms. An equation commonly used to calculate dBm levels
can be derived from equation (2):

dBm

= 10 log (P2/P ref)
10 log (P2/0.001 W)
10 log 1000 (P2)
10 10 1000 (Vrms2)
g 6OO0hm

where reference impedance =600 ohms.

For example, to caiculate the peak-ta-peak voltage of a
o dBm sinusoidal signal:

MOTOROLA COMMUNICATIONS DEVICE DATA

10 log 1000 (Vrms2)
600
100 = (5/3)Vrms2
Vrms2 = 0.6
Vrms = 0.7746
Vp-p = 2(2)II2Vrms
= 2.191 volts peak-ta-peak.
In order to understand the proper level at a certain point in
a system, the term dBmO is used for reference. A dBmO
defines the nominal signal level at a test point node. Absolute
levels can then be referred to in dBmO for comparison to the
nominal level. For example, suppose that at' a certain point in
a system 0 dBmO = + 6 dBml600 ohms. Then a - 20 dBm
signal would be equal to - 20 - ( + 6) = - 26 dBmO. Therefore, a - 20 dBm signal would be 26 dB down from the
nominal level.
Noise measurements require a different decibel unit as they
usually involve some bandwidth or filtering constraint. One
such unit commonly used (especially in North America) is
dBm or decibels above reference noise. The reference noise
level is defined as one picowatt into 600 ohms or - 90 dBm.
Telephone measurements typically refer to dBmC which is
the noise level measured through a C-message weighting filter
(a filter that simulates the response of the human ear). Eurapean systems use a related term called dBmp which is the
dBm level noise measured through a psophometric filter.
Both dBmC and dBmp can be referenced to 0 dBmO by adding a zero-dBmCO and dBmOp. Two examples are shown
below to illustrate the use of these units:
1) 0 dBmO = + 6 dBml600 ohms
Noise measurement = 20 dBmC
= 14 dBmCO
2) 0 dBmO = +9 dBml600 ohms
Noise measurement = - 70 dBmp
= -79 dBmOp.
Understanding these units should help avoid any possible
correlation problems between measurements and published
specifications.

AN872

4-7

_

MOTOROLA

SEMICONDUCTOR
APPLICATION NOTE

AN893
Application Note

UNDERSTANDING
TELEPHONE
KEY SYSTEMS
Prepared By:
Steve Bramblett
Telecom Applications
Austin, Texas

INTRODUCTION
This application note is intended to give an understanding
of key sysiems and how they differ. A theoretical architecture based loosely on many of the 16 station key systems now
in existence Will be presented. Possible variations and the impact on overall design will also be discussed.
WHAT IS A KEY SYSTEM?
A key system is a telephone system that can be used behind
a PBX of central office. Generally, key systems are designed
to support as many as lOll telephones, and provide service to
these phones With up to 50 percent trunking (a trunk may be
either a PBX or central office line co~ecting the key system
to the rest of the world). The telephone
has several push
buttons that are not generally found on a KSOO-type desk set.
These push buttons allow direct access to several trunks,
intercom lines and system features such as hold and do-notdisturb. The major difference between a key system and a
PBX is that a key system allows the user full control over individual .trunks, while a PBX assigns whatever trunk is
available whe,n requested (usually this is done by dialing a
"9").

set

HOW DOES "SQUARENESS" AFFECT THE SIZE?
There are two basic architectural types of key systems, one
known as a "square" system, and the other a "non-square"
system. In a square system, every subset has control over
every trunk so there can be no special reserved lines. Some
designs go one step further by forcing a button appearance
for each station. The most obvious size limiting factor in a
square system is the number of buttons on the phone. In a
non-square system, each phone is provided With a subset of
the available trunks. While this makes the non-square system
design appear more attractive, one must understand the complexity involved. In a square system, only one set of tip and
ring Wire pair must be routed to the phone, and since each
phone looks identical, bookkeeping by the CPU is held to a
minimum. In a non-square system there must either be a
separate voice pair for each trunk and intercom link; as in

AN893
4-8

IA2 system, or there must be a· way to program the
telephone's "profile" into the CPU so it can control the station accesses. This presents real problems as there must be
some input and display device associated With the CPU plus
some form of non-volatile data storage. This storage can be
anything as simple as several dip sWitches, or as complicated
as an intelligent controller that hooks into the system With a
CRT terminal and programs several EEPROMs.
WHAT IS A tAl SYSTEM?
The IA2 key system is an older system that relied on
electro-mechanical devices to accomplish the tasks now
replaced by modem integrated circuit technology. These
systems generally included several pairs of tip and ring
signals which led to each station, where complicated
mechanical sWitches selected the desired pair. The connections to the outside world were metallic, and therefore were
of the non-protected variety. The biggest expense was cabling
and installation labor, because the system required a' 25-pair
cable for each phone.
WHAT IS MEANT BY "PROTECI10N"?
A protected key system is designed in such a way to prevent stressful voltages reaching the trunk under any circumstances. Generally, this is accomplished by transformer
coupling the trunk to the system at the interface and adding
overvoltage protection. This Will prevent any accidents from
causing problems With the trunk, such as 11 0 Vac getting to
the trunk from an improperly installed telephone. When a
key system is not protected, it must be installed by a
registered agent of the manufacturing company. Both
distributor and manufacturer are burdened by expensive
agency agreements if a system is not protected.
KEY SYSTEM ARCHITECfURE
A l6-station square system with protection is outlined in
Figure ·1. The trunk interfaces provide the necessary protection to pass the FCC requirements, plus the circuitry to condition the voice and signaling information to make them
MOTOROLA COMMUNICATIONS DEVICE DATA

Central /,---.,\1
Office
Lines

Trunk
Interfaces

Subscriber
Apparatus

Call

Voice
Matrix'

Progress

Station
Apparatus
Interfaces

CPU

Tones

FIGURE 1 - Key System Unit

easier for the system to handle. The voice information is
passed to a voice matrix, where the information can be
routed to the proper destinations, and the signaling goes to
the CPU to indicate what is happening at the interface. The
station apparatus interfaces provide the voice arid data interfaces to the phones. The progress tones are for internal
supervisory signaling within the switch. The CPU is charged
with the supervisory and monitoring tasks for all other parts
of the system.
A much more detailed look at the voice matrix is provided
in Figure 2. The voice matrix is an analog crosspoint variety
which may be composed of relays or CMOS switches. Relays
are a good voice switch medium for systems with eight or less
stations, but the newer crosspoint ICs, such as the MC142100
and MC142101, are much more cost effective. There is some
loss associated with the switches (about 100 ohms) that does
not occur in the relays. In our example we will consider a
4 x 4 x 2 crosspoint and the dotted lines outlining the three
chips needed for the matrix. The music-on-Jiold (MOH)
music and the tones are separated to help alleviate crosstalk
within the switch structure. The design includes the ability to
handle 3 trunks and 1 internal conversion. This appears to be
a standard that was implemented through the years. Most
systems allow expansion to either 2 more trunks or a trunk
and an intercom link by adding to the matrix. Bridging more
than one trunk or station can be easily accomplished by setting multiple contact points.
The loss the switch introduces into the system is the major
drawback to using the CMOS crosspoint switch. The FCC requires that the electrical-to-acousticalloss of the system from
the trunk to the station must not exceed 2.S dB. A look at
Figure 3A shows that a typical trunk-to-station loop has loss
in two areas. The two crosspoint switches represent a typical
200 ohm resistance when they are in an on state which creates
about 2.S dB of loss in a 600 ohm system. Each transformer
also introduces some loss so the electrical-to-electrical loss
exceeds 2.S dB. Changing the internal resistance of the loop

MOTOROLA COMMUNICATIONS DEVICE DATA

minimizes the switch resistance but the transformer efficiency is greatly decreased so no advantage is found here. The
loop could be amplified, but this is costly and leads to
unstable circuitry so the phone must be designed to operate
on different levels from a standard phone. The FCC allows
another 2.S dB of loss for a station-to-station talk path as
shown in Figure 3B so the extra switches in the loop are not
a problem .
. Figure 4A is a block diagram of the trunk circuit. When
.the trunk is idle, the tip and ring are bridged by the loop relay
across the ring detect circuit. This circuit signals the CPU
when a call is ringing in from the central office or PBX.
When the trunk is accessed by the system the loop relay connects tip and ring to. the transformer. The protect circuit
helps prevent surge and static damage. The battery reversal
detector is an optional circuit thai alerts the CPU when the
tip and ring polarity has been reversed. This usually happens
momentarily when a central office toll circuit has been accessed, so this is for toll restriction. The loop detect circuit is
needed to indicate when the connection has been terminated
by the outside caller. This prevents the hold function from
locking up a trunk. If pulse dialing is to be provided a relay
circuit similar to the one in Figure 4B must be added to the
loop. The CPU must read the pulses from the station and
transfer them to the trunk. Another possible optional circuit
is a ground loop detector. This is needed to detect grounds
on a groundstart trunk. These trunks use a ground to start
where loopstart trunks (the most common kind) use loop
continuity to start.
The station interface in Figu~.. S is a four-wire design. The
first pair (tip and ring) are used to provide voice communications while the second pair (D + and D - ) provide data communications. The two resistors in the voice circuit provide a
current limiting function to prevent catastrophic system
failures should tip and ring get shorted together. The protect
circuit functions in a manner similar to the trunk protect circuit and the loop detect is used to detect the making and

AN893
4-9

r----.., r-----, r----:-l r----..,
COl

I

,I

I.

C02

I

.1

I

C03 I

.1

I

I

.1

I

~

L

Intercom

L

Stations

-

-

-

2

3

4

"

,I

I
I

5

-

I- -

6

7

"
01

I
I

...J

L - I-

8

9"

A

I

,I

I

1,1

01

I

:1

.1

I

,I

- ..J L

B

C

D

-

I- -

E

- ~

10

MOH TONE

FIGURE 2 - Voice Matrix

breaking of the loop to pass pulse dialing signaling to the
trunk. The resistors in the data interface do the same job in
the voice circuit as does the protect circuit. The differential
mode transmitter and receiver provide a serial data stream interface for the data communications. The data is generally in
a half-duplex ping-pong arrangement, where the outgoing
data tells the station which lamps should be on, whether the
ringer is to ring, and whether the call announcer should be
energized. The incoming data gives the status of the phone's
hookswitch and the buttons on the keypad.
Another name for the station apparatus is the keyphone or
the subset. Figure 6 is a block diagram of the subset. Tip and
ring come into the subset through the hookswitch. When the
handset is on-hook, the tip and ring are directed to the
handsfreelcall announcer circuit. This circuit is similar to a
speakerphone circuit. When the handset is removed from its
cradle, the tip and ring is routed to the speech network for
normal telephone operation. Each voice network is powered
by the battery voltage on tip and ring. The data circuit is
powered by its own battery feed to help prevent crosstalk between voice and data. The data is brought into the control
logic to activate the lamps, ringer, and in some cases, the
handsfreel call announcer.
There are several variations on the voice and data links to
the subset.' Some systems impress the data, which generally
has a rate well above the voice channel, onto the tip and ring
for a single pair run. Extra filtering is needed to separate
voice and data. Another variation connects tip and ring to
the speech network causing the handsfreelcall announcer to
receive voice over the same wire pair as the data. This allows
"off-hook call announcing" where the user can be paged via
the call announcer while off-hook talking. Generally the output level of the call announcer is greatly attenuated when the
handset is not in the cradle.
Another interesting variation to the architecture deals with
how the dialing is controlled by the system. In this arrangement all DTMF tones or dial pulses originate at the subset
and are passed through the system as though it is transparent. This is known as end-to-end signaling. An alternative
is to place the pulse or tone dialer on the trunk interface and
read the dial by the control logic so the dialing information is
passed through the CPU to be interpreted at the trunk. The
major drawback here is that there must be extra circuitry in
the subset to produce aural feedback. In a normal phone the
DTMF encoder mutes the speech network. Since the encoder
is not here the mute is lost. The levels needed at the trunk

AN893
4-10

may be uncomfortable, so they must not reach the user,
therefore some feedback must be generated to indicate dialing has taken place.
Adaptation of this system into a non-square system requires several major system modifications. Since a nonsquare system allows only a portion of the trunks and
available features to be represented as buttons on the subset,
some scheme of accessing other non-appearing trunks and
features must be employed. This is usually done by dial access. In a dial access system, every subset must have a dial intercom button. When this button is accessed the system must
provide a dial tone and a dialing register. The dialing register
must be capable of countilig dial pulses and decoding DTMF
data. Since DTMF decoders alone are in the $20-$30 price
range the number of registers are generally restricted. This
. can cause bottlenecking problems when there is a need for
more dial accesses than the number of registers available.
There is generally a tone associated with this overload (the
overload is called blocking) that indicates to the user that all
circuits are busy. If all intercom links are busy when access is
needed, then blocking also occurs. Now that the buttons
must have some flexible assignments a data base of the subset
"profiles" must be retained by the CPU. In addition to this
data base duty, new software overheads are necessary for the
CPU to allow dial and button accesses, as well as the addition of new, extended features such as dial intercom that are
generally included in the non-square system.
There are several alternatives in operation during a power
failure. One solution is called powerfail cutthrough. In this
scheme certain trunks are metalically connected to certain
phones. Our subset design does not support this arrangement
since ringing would be impossible and the call announcer
would be bridged across tip and ring when the subset is
on-hook. The system can be designed so that ringing occurs
in a normal manner, but a ringing generator is necessary. The
ringing generator is a specialized ac power source. An alternative is battery back-up, and since most systems have a
master power supply of 24-48 Vdc, this can be easily accomplished. The major advantage to this that no calls are
lost on the power loss as in cut-through, and unless a
sophisticated cut-through system is employed, calls are lost
. on the return to power which again is not a problem in a battery backed-up system. The system must be a low-power
design or the battery back -up system may become prohibitively expensive.

MOTOROLA COMMUNICATIONS DEVICE DATA

"oJ

• Tip

~

-r

::::c:
::::c:

-L

~ Talk

F

Ring.

FIGURE 3A -

Trunk-to~Station

• Ring

Loop

I"'F----------;·..

TiP ...O(E---------""\~
Talk

Battery

'11'1'.--+ Gnd

·TiP

__:::L=....J-

'--:::L-r--~Talk

Gnd~~-=r=~~3

~,..---::c-'---'II\I'vo-+Gnd

Battery~....-

Battery

'------------'l.~Ring

Ring ...o ( E - - - - - - - - - - ' -

T

T

FIGURE 3B - Station-ta-Station Loop

r------I~

Tip

Tip_--+------....
Loop
Detect

To
Central
Office

To
Matrix

'-------I. Ring

Ring.-.....- -.....---I.",

V 111

1
1

~
~
3 ~ Detect
:,.3. __1....___-_-_~_ _ _ _ _ _ _ _ _ _ _: CPU

FIGURE 4A - Trunk Interfaca IWithout Pulse Dialing)

To
Hookswitch ..
Relay

~ I-I--l----!-=t.,,.-l
'-----'
(Digital
Input)
Analog
Output

1N914

1k

4 f - ¥ t - -......--L~Vsyl.
200k

600

R1

C1

6

8

600 0.05~F
RC 13k

FIGURE 5 - TELEPHONE QUALITY DELTA MODULATOR CODER
Both Double Integration and Active Companding Control Are Used to Obtain Improved CVSD Performance.
Laser Trimming of the Integrated Circuit Provides Reliable Idle Channel and Step Size Range Characteristics.

resistor. The required integrator current for a given change in
voltage now becomes
Vout
R2C2 RICI
.6.Vout+
Iin=Rij+
+ Rij+CI

Ro

TT""

R2C2CI + RIC1R2C2 .6.Vout 2

Ro
.6.T2
The calculation of desired gain resistor Rx then proceeds
exactly as previously described using this current equation.
SUBSCRIBER CARRIER TELEPHONE QUALITY
CODEC USING MC3418
Two specifications of the integrated circuit are specifically
intended to meet the performance requirements of commercial telephone systems. First, slope polarity switch current
matching is laser trimmed to guarantee proper idle channel
performance with 5 mV minimum step size and a typical 1Of.
current match from 10 ~ TO = p./1. Thus a 300 to 1 range of
step size variation is possible. Second, the MC3418 provides
the four bit algorithm currently used in subscriber loop
telephone systems.
With these specifications and the circuit of Figure 5, a
telephone quality codec can be mass produced.

MOTOROLA COMMUNICATIONS DEVICE DATA

The circuit in Figure 5 provides a 30 dB SINc ratio over 50
dB of dynamic range for a 1 kHz test tone at a 37.7 kilobit
rate: At 37.7 kilobits, 40 voice channels may be multiplexed
on a standard 1.544 megabit TI facility. This codec has also
been tested for 10-7 error rates with asynchronous and synchronous data up to 2400 baud and for reliable performance
with DTMF signaling. Thus, the design is applicable in
telephone quality subscriber loop carrier systems, subscriber
loop concentrators and small P ABX instaIlations.
THE ACTIVE COMPANDING NETWORK
The unique feature of the codec in Figure 5 is the step size
control circuit which uses a companding ratio reference, the
present step size, and the present syllabic filter output to
establish the optimum companding ratios and step sizes for
any given input level. The companding ratio of a CVSD
codec is defined as the duty cycle of the coincidence output.
It is the parameter measured by the syllabic filter and is the
voltage across Cs divided by the voltage swing of the coincidence output. In Figure 5, the voltage swing of pin 11 is 6
volts. The operating companding ratio is analoged by the
voltage between pin IO and 4 by means of the virtual short
across pin 3 and 4 of the V to I op amp within the integrated
circuit. Thus, the instantaneous companding ratio of the
codec is always available at the negative input of AI.

ARTICLE 1
4-19

The diode DI and the gain of Al and A2 provide a companding ratio reference for any input level. If the output of
A2 is more than 0.7 volts below VCCI2, then the positive input of Al is (VCCI2-0.7).
The on diode drop at the input of Al represents a 12"1.
companding ratio (12% = 0.7 V/6 V).
The preseut step size of the operating codec is directly
related to the voltage across Rx which established the integrator current. In Figure 5, the voltage across Rx in a direction which reduces the difference between the companding
reference and the operating ratio by changing the step size.
The ratio of R4 and R3 determines how closely the voltage at
pin 4 will be forced to 12%. The selection of R3 and R4 is initially experimental. However, the resulting companding
control is dependent on Rx, R3, R4, and the full diode drop
DI. These values are easy to reproduce from codec to codec.
For small input levels, the companding ratio reference
becomes the output of A2 rather than the diode drop. The
operating companding ratio on pin 4 is then compared to a
companding ratio smaller than 12% which is determined by
the voltage drop across Rx and the gain of A2 and AI. The
gain of A2 is also experimentally determined but once determined, the circuitry is easily repeated.
With no input signal, the companding ratio at pin 4 goes to
zero and the voltage across Rx goes to zero. The voltage at
the output of A2 becomes zero since there is no drop across

SIGNAL TO N.OISE PERFORMANCE OF
TELEPHONY QUALITY DELTAMODULATOR

Rx. With no signal input, the actively controlled step size

vanished.
The minimum step size is established by the 500 k resistor
between Vee and Vcc12 and is, therefore, independently
selectable.
The signal to noise results of the active companding network are shown in Figure 6. A smooth 2 dB drop is realized
from + 12 dBm to - 24 under the control of AI. At - 24
dbm, A2 begins to degenerate the companding reference and
the resulting step size is reduced so as to extend the dynamic
range of the codec by 20 dBm. The slope overload characteristic is also shown. The active companding network produces
improved performance with frequency. The 0 dBm slope
overload point is raised to 4.8 kHz because of the gain
available in controlling the voltage across Rx. The curves
demonstrate that the level linearity has been maintained or
improved.
The codec in Figure 5 is designed specifically for 37.7
kilobit systems. However, the benefits of the active companding network are not limited to high bit rate systems. By
modifying the crossover region (changing the gain of A2),
the active technique may be used to improve the performance
of lower bit rate systems.
The performance and repeatability of the codec in Figure 5
represents a significant step forward in the art and cost of
CVSD codec designs.

FREQUENCY RESPONSE VS INPUT LEVEL
(SLOPE OVERLOAD CHARACTERISTIC)

35

m

"C

~w30t------Jr=========S~S=========~1
50dB

(/)

5

4 BIT ALGORITHM
37.7 Kilobit.
1 kHz TEST TONE
C MESSAGE WEIGHT

z

a

>~25+---+-----------------------------1

z

<.!l
Cij

-48

-36
-24
o
-12
INPUT LEVEL INdBmO

E
m
"C

z

0
-10

:::; -20
w

j;j

...J

!;
a.
!;
a

-30
-40
-50

4 BIT ALGORITHM
37.7 Kilobit.

-60

2 kHz 4 kHz 6 kHz 8 kHz 10 kHz
INPUT FREQUENCY IN Hz

12

DELTAMOD SYSTEM PERFORMANCE

FIGURE 6 - SIGNAL TO NOISE PERFORMANCE AND FREQUENCY RESPONSE
Data Document the Improvement Realized with the Circuit in Figure S.

ARTICLE 1
4-20

MOTOROLA COMMUNICATIONS DEVICE DATA

MOTOROLA

-

SEMICONDUCTOR
APPLICATION NOTE

AN943
UDLT Evaluation Board
INTRODUCTION
To help meet the demands for a cost effective solution to
the ever growing voice/ data world within the digital telephone
and PBX realm, Motorola has created the Universal Digital
Loop Transceiver (UDLT) voice/data circuit family. The purpose of this application note is to render an understanding of
the UDLT voice/data family and show a typical application for
these CMOS parts. This is an evaluation of the application and
performance of the MC145422/26 UDLT demonstration board,
which was designed and built for customer evaluation.

ping-pong with the master at an eight kilohertz rate. The PD
pin can be left floating as an output, in which case the slave
will pull PD high until the slave stops receiving bursts from the
master then it will take PD low and stop bursting until PD is
brought high or the master· bursts again. A three state control
can be used on this pin if the designer wants to send data to
the master during a power down. The slave also has a Tone
Enable input pin (TE) which when held high generates a 500
hertz ·square wave tone at approximately - 20 dBmO which
can be used in the digital telset to provide audio feedback.

FUNCTION OF PARTS
UDLT's

MONO-CIRCUITS

The UDLT master (MC145422) and slave (MC145426) are
transceivers that provide 80 kilobit-per-second full duplex synchronous voice and data communication to distances of two
kilometers on 26 AWG twisted pair and further on heavier
gauge pairs. The modulation technique used is a 256 kilobaud
Modified Differential Phase Shift Keying (MDPSK) type burst.
The MDPSK triangular waveform used in this modulation
technique reduces radiation, EMI, and ·crosstalk due to its
compact frequency spectrum.
The master which is used at the telephone switch linecard
bursts ten bits to the slave, consisting of eight bits of
voice/ data and two signaling bits. The slave, which is used at
the terminal or digital telephone, receives the burst from the
master and upon demodulation of the burst synchronizes its
clocks, and bursts ten bits back to the master. This "pingpong" technique occurs within a 125 microsecond frame
period and allows end to end full duplex, synchronous operation. This full duplex operation between the master, at the
digital linecard and the slave/ mono-circuit, at the digital
telephone, enables each set to have high speed access to the
PABX switching facility.
At the linecard a microprocessor has complete control of
the master. The Signal Enable input (SE) is a three state controller pin which if held high enables the power down, loopback and the two signaling bits, thus allowing these signals to
be bussed to the microprocessor. The master can be programmed via the Signal Insert Enable (SIE) pin to insert signaling bit
two into the LSB of the PCM word at Tx. This allows
simultaneous voice and data transmission through the PABX
without the need of changing existing hardware and software.
Both the master and the slave have power down and loopback
features for system power conservation and testing. The
power down pin on the slave is a bidirectional pin. It can be
used as an input to initiate a call. When the PD pin is pulled
high, the slave will continue to burst every other frame (once
every 250 microseconds) until the master responds by
bursting. Once the master responds, the slave synchronizes to

Motorola's family of Pulse Code Modulation (PCM) monocircuits incorporate a codec, filter and voltage reference into a
single IC. The general block diagram for Motorola's monocircuits is shown in Figure 1. These devices perform the
digitizing and recovery, as well as the band-limiting and
reconstruction filtering necessary for voice digitization in
telephone systems. The mono-circuits are tailored for a variety
of telephone switch architectures. The family consists of five
different device types. The MC14400, MC14403, and MC14405
16 pin devices,the MC14401 18 pin device and the MC14402
22 pin device allow designers to optimize for minimal configurations or select a full set of features. The MC14403, for
example, can be used where minimal space is desired for the
digital phone design whereas the MC14402 is available for
maximum flexibility. The mono-circuit incorporates the bandpass filter required for antialiasing and 60 hertz rejection, the
A/D, the D/A, both for either U.S. Mu-Law or European
A-Law companding formats, the lowpass filter required for
reconstruction smoothing, on-board precision voltage
reference and does not require any external components.
In this demonstration board, the full featured 22 pin
MC14402 mono-circuit is used in the slave circuit showing its
ability to adjust the receive gain while maintaining a low impedance output using the RxO, RxG, and RxO pins, The
MC14403 is used on the master board showing a simple 16 pin
solution for the telephone handset interface.

MOTOROLA COMMUNICATIONS DEVICE DATA

DATA SET INTERFACE (DSI)
The MC145428 Data Set Interface (DSI) provides the asynchronous to synchronous and synchronous to asynchronous
data conversion. This low power five volt CMOS device is
ideally suited to interface between the RS-232 compatible data
port of any voice/ data digital telset or terminal and the synchronous data channel of the UDLT. A block diagram of the
Data Set Interface is shown in Figure 2.
There are two .basic modes of operation for the synchronous channel interface. In the first mode the DSI inter-

AN943

4-21

Tx_--------......_'_-+1
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---------------j

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MCI488
VEE U6 VCC
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101
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DC

VSS -5 V

VCC

MCI489
IA U5 VCC 14
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4
18
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RESET 19
DL
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DOE 17
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Figure 5. Master UDLT Demo Board

TIP
RING

17

MASTER UDLT DEMO BOARD
PARTS LIST
PART

QUANTITY
(PART NUMBER)

MCl45422
MCl46428
MCl4403
MCl45406
MCl489
MCl488
MCl4069UB
MC74HC74
MC74HC393
LEPCO P-l358A
DB25
RJll
GRAYHILL (SPOT 78J05)
CUTLER-HAMMER B8500W/PZ81R
GRAYHILL (SPOT 78J02)
BANANA JACKS

l-Ul
l-U2
l-U3
l-U4
l-U5
l-U6
l-U7
l-U8
l-U9

20 pF
0.1 JtF
10 JtF
10M
5K
33011
1.6 K
3.6 K
56K
10 K
1K
22011
10 K
1011
CRYSTAL
JUMPERS
DIODES lN914
LED (T1)
2N2907

l-Tl
1
1
l-Sl
l-S2
l-S3
6
2-Cl & C2
12-C3-C14
2-C15, C16
l-Rl
l-R2
l-R3
l-R5
l-R6
l-R7
l-R8
l-R9
2-Rl0, Rll
2-R12, R4
2-R13, R14
1-4.096 M
10
2-01,02
1

1

SOLDER TAIL SOCKETS
14
16
20
22

AN943

4-26

PIN
PIN
PIN
PIN

5
2
1
1

MOTOROLA COMMUNICATIONS DEVICE DATA

S2 - This switch is optional and is hardwired to signaling
channel one for demonstration using LEOs. The footprint for
this switch is included on the board.
This switch can be obtained from:
Cutler-Hammer
PIN B8500W/P281R
S3 - These straps select Mu or A laws and power down on
the MCl4403 Mono-circuit and MCl45422 master UDLT.
SWl - (PO) This strap when high, powers both the monocircuit and master UDLT. When low, both parts are
powered down.
SW2 - (Mu/ A) Selects Mu or A law cOding.
Loopback and Valid Data on the master can be accessed via
pads.
STRAPPING ON THE SLAVE
Sl - Same as Sl on the master; selects asynchronous data
format and bit rate.
S2 - These straps select Tone Enable, Power Down, Mu/ A,
and Loopback features of the slave (MCl45426) as well as
Mu/ A and Power Down on the MCl4402 Mono-circuit.
SWI - (TE) A high enables a 500 hertz tone.
SW2 - (PO) Powers both the slave and mono-circuit up or
down. High = powered up, and Low = powered down.
SW3 - (Mu/ A) Selects Mu or A law coding for the monocircuit.
SW4 - (Mu/ A) Selects Mu or A law coding for the slave
UDLT.

SW5 - (LB) When low, the 64 kilobits-per-second of information coming from the master will loop through the slave
and return to the master. The signaling bits are unaffected.
S3 -

Same as the S2 switch on the master.

POWER SUPPLY CONSIDERATIONS/LAYOUT
GUIDELINES
The power supply requirements for these boards are VDD at
+ 5 volts, VSS at - 5 volts and VCC which is the RS-232 driver
positive voltage of + 7 to 12 volts for the MCl488. VCC may
be as low as +5 volts with the MCl45406 Driver/Receiver
chip. The power supply current required by each of these
voltages is less than 30 milliamperes. This results in a total
slave board power consumption of less than 400 milliwatts.
This amount of power may be supplied by the loop using a
linear supply. To isolate the RS-232 port with respect to earth
ground. a switching regulator powered by the loop or an external power supply will be required. If a switching regulator is
used, it should be synchronized to the eight kilohertz and 128
kilohertz clocks of the slave UDLT to reduce the affects of
aliasing noise into the analog circuitry of either the UDLT or
audio voice channel. This function will be supported by the
MC34129 Digital Telephone. Switching Power Supply Controller chip. This device has the capability to power-up and
regulate on its internal oscillator. After regulation is established it can synchronize to an external clock such as the slave's
128 kilohertz clock.

+

SLAVE UDLT DEMO BOARD
PARTS LIST
PART

QUANTITY
(PART NUMBER)

PART

QUANTITY
(PART NUMBER)

MCl45426
MCl45428
MCl4402
MC145406
MCl489
MCl488
LEPCO P-1358A
DB25
RJ11
GRAYHILL (SPOT 78J05)
CUTLER-HAMMER B8500W/P281R
BANANA JACKS
20 pF CAPS
O.l,.,F CAPS
10,.,F CAPS
10 M
5K
3300
5K

l-Ul
1-U2
1-U3
l-U4
1-U5
1-U6
l-Tl

5000
10 K

l-R6
1-R7
l-R8
2-R9, Rl0
3-Rll, R13, R2
1-R12
2-R14, R15
12
1-4.096 M

1
1
2-S1 & S2
l-S3
6
2-Cl & C2
10-C3-Cl1, C14
2-C12, C13
1-Rl
1-R3
l-R4
1-R5

MOTOROLA COMMUNICATIONS DEVICE DATA

56K
2200
10 K
1K
100
JUMPERS
CRYSTAL
LED (Tl)
DIODES lN914
2N2907

1
2-01,02

1

SOLDER TAIL SOCKETS
14 PIN
16 PIN
20 PIN
22 PIN

2
1
1

2

AN943
4-27

;t~

mID

~

~~~r+frf{~
0~25 2 TxO "

D
=

VCC
+12 V
C7

O.II'F

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VSS -5 V
7 GNO

IIII +~~CV
VOO
+5 V

MC1488
U6
1
VCC
2 VEE
101
3 IA
OA
102 11
4 lBl
00
5 lB2
lCl
lC2
OB
OC
GNO

VOO
+5 VC14

MC145406
U4
VOO
VCC
Rxl
001
Txl
011
Rx2
002
Tx2
012
Rx3
003
Tx3
013
VSS GNO

~

I

16
15
14
13
12
11
10
9

s::

@

I

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I

S2·112
13
14
15
16
17
18
19
20

l

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s::

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z
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~

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en
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=

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=

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MC145426
Ul PO 11 S2·2
TE
MUlA 10 S2·4
TEl
TX
502 9
Xl
512
X2
SOl
Clk
SI1
Rx
~ 14
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lio';
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=

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+SPK

2
3
SI·5
NC 4
5
S1-4 6
SI·3 7
SI·28
SI·1 9
10

=

VSS -5 V
-MIC
IBLACKI
-SPK

NC

MC145428
O.II'F U2
20
TxS ~ 19
TxO RESET
OL
OCO 1.I.lI.-----,
BRClk OOE 17
BC
CM WI11.......-_--..
BRI
OC 1
BR2
OlE 14 VOO
BR3
OCt t.!1.:<.3_ _+-....
SB
R,S 12 NC
VSS
R,O 11

VSS
-5 V
R3
5k

VOO
'

r;!/'
R4
330
Tl
_
PINS2&3TIEO TOGETHER
~IN4
TIP

E
N-l

~VSS-5V

~VOO

+5V

220 RIO

'These optional resistors provide additional
power supply noise isolation and are utiliz·

ed bV cutting the trace that jumpers across
them.
Figure 6. Slave UDLT Demo Board

220 R9

PIN 1

RING

MOTOROLA COMMUNICATIONS DEVICE DATA

AN943
4-29

"

II

_.

,,'

u

=1,~

.....

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cci

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ao

it

AN943

4-30

MOTOROLA COMMUNICATIONS DEVICE DATA

MOTOROLA

-

SEMICONDUCTOR
APPLICATION NOTE

AN949

A Voice/Data Modem
Using the MC145422/26,
MC145428 and MC14403
GENERAL APPLICATIONS
This voice/data application allows an analog telephone system to support simultaneous voice and data across a single
twisted-wire pair: Figure 1 shows how this system is implemented. To use the voice/data modem, the analog telephone
line must be intercepted at the telephone system by one modem (the PBX-CPU Interface). The analog signals are then
converted to digital signals, combined with data and transmitted down the remaining line as a digital loop. The second
modem (the Telset-Terminal Interface) terminates the digital
loop, reconstructs the analog signals and sends this information to the telephone that is plugged into the modem. The
digital data is removed from the digital loop information and
routed to the endpoint terminal. Any signalling information
(hookswitch status and ringing) is handled by a second data
channel, and it too is combined with the data and digitized
voice for transmission on the digital loop.
ANALOG CODING AND DECODING
Analog signal digitization and reconstruction on both modems are done by the MCl4403 Mono-circuit. The monocircuit band limits incoming analog signals to prevent aliasing
and then samples them with a sample and hold amplifier. This
information is then digitized by an on-board analog-to-digital
converter. This converter creates an eight bit 'companded'
word for each sample by converting the signal to a pseudologarithmic form known as Mu-Law companding (A-Law companding is also available). In this manner approximately 78 dB
of dynamic range can be represented by compromising the
signal-to-distortion specifications. The mono-circuit is also capable of performing the reverse digital-to-analog conversion
for this 'companding' technique. There is a reconstruction filter
to convert the resultant stepped waveforms into a continuous
waveform that very closely approximates the original analog
input.
THE DIGITAL LOOP TRANSMISSION
The MC145422 master Universal Digital Loop Transceiver
(UDLT) and MC145426 slave UDLT are used to transmit the
digital information between the modems. In addition, the slave
UDLT must be capable of- determining and maintaining synchronization with the master UDLT so that word boundaries
may be defined. The UDLT transmits a 10 bit, 256 kilobaud
burst of information at an 8 kHz rate. By controlling the frequency of the burst from the master, the slave can sense and
generate syncs. In this 10 bit word is the 8 bit voice sample
along with one signalling bit and one data bit. Since each burst
carries one digital "voice" word, the UDLT must create bursts

MOTOROLA COMMUNICATIONS DEVICE DATA

at a rate of 8 kHz. This obviously means that both the data
channel and the signalling channel operate at an 8 kbps speed.
ASYNCHRONOUS TO SYNCHRONOUS DATA
CONVERSION
Since data is transferred at an 8 kbps rate in a synchronous
mode, the MC145428 Data Set Interface (DSI) is used to convert an asynchronous data stream into the 8 kbps synchronous
stream. The DSI can take data at speeds up to 9600 baud on
the asynchronous channel and convert it to 8 kbps synchronous. The DSI is capable of supporting asynchronous speeds
well in excess of 9600 baud, however, with an 8 kbps synchronous channel, dynamic handshaking on the asynchronous
channel would be required. The DSI is also capable of converting the received synchronous data back into asynchronous
data at the same time.
THE PBX-CPU INTERFACE
Figure 2 shows the block diagram of the PBX-CPU Interface.
This circuit contains an analog interface that mimics the telephone electrical characteristics with respect to the PBX. This
makes the voice/data modem transparent to the telephone
system. The RS-232-C terminal interface is a 9600 baud asynchronous interface that appears to be a modem (data set
equipment) to the data device (data terminal equipment). The
digital loop is a specially devised transmission scheme that
uses the UDLT to its fullest advantage. The digital loop is
capable of excellent data performance (better than 8 x 10 - 8
bit-error-rate in 95% of the installations) on twisted pair up to
2 kilometers in length (26 gauge wire worst case).
The analog loop as shown in Figure 3 must be able to provide
all the necessary interface considerations to simulate a telephone. The interface must be able to control the loop like a
phone and it must be able to interface the voice signals, i.e.,
provide a 2-to-4 wire hybrid. In an idle condition (the handset
is in the cradle or "on-hook"), the telephone appears as a high
dc impedance. The relay provides this by "breaking" the loop
and preventing dc current flow. When the phone goes offhook, the dc impedance is drastically reduced. In a normal
environment the phone must draw a minimum 20 mA of loop
current, and since 48 volts is supplied to the loop at all times,
this can be accomplished with resistor R6 or R7. This would
energize a "ring-trip" relay coil which would disconnect any
ring signals in the telephone system. At the same time an
analog voice path would be established. The ac impedance of
the telephone is typically held to 600 ohms to maintain transmission line balance and to minimize 60 Hz noise.

AN949

4·31

When the phone is on hook, it must be capable of detecting
a ring signal. Ringing is typically a 100 volt RMS 20 Hz signal
impressed on the 48 volt dc level. In this scheme ringing is
detected with the MC34012 (U9) bipolar ringer chip. The 2to-4 wire hybrid not only preserves the 600 ohm ac impedance,
but it also converts a 4-wire system (separate transmit and
receive) into a 2-wire current loop environment. In this design
this is done with a duplexer circuit made up from the monocircuit op-amps and resistors R12 through R16. Diodes 4 and
5 prevent excessive voltage transients from damaging the
mono-circuit (U7). Engineering Bulletin EBlll provides a detailed analysis of the duplexer design.
TIMING SIGNAL GENERATION
The timing signals that drive the mono-circuit, UDLT (U4)
and DSI (U5) are derived from Ul, U2 and U3. U1A is a
standard CMOS crystal oscillator topology designed for ATcut parallel resonant crystals. Ul B buffers the master clock
signal (4.096 MHz) and then sends it to the DSI and U2A.
U2A is a flip-flop that divides the signal by 2 to get the monocircuit and UDLT master (CCI) and data clocks (2.048 MHz).
U3 and U2B are a divider network that creates the 8 kHz master
sync signal from the 2.048 MHz clock. This 8 kHz signal is
also used as the enable signals for data communication between the UDLT and mono-circuit, and the DSI and UDLT.
Voice data is clocked out of both the UDLTand mono-circuit
in 8 bit packets. These packets are defined by the 8 kHz sync
positive-going level. This level is eight 2.048 MHz clocks long
so the 2.048 MHz clock is the transport clock. The information
is clocked out on leading edges. The information is clocked
in on falling edges of the same 2.048 MHz clock and is likewise
controlled by the positive portion of the 8 kHz signal.
Digital data and signalling information is directly controlled
by the 8 kHz sync. The data is clocked into and out of the
UDLT on the leading edge of the 8 kHz signal, and into and
out of the DSI on the falling edge of the 8 kHz signal. This
scheme is guaranteed on the UDLT but must be set up by
tying the CM pin Iowan the DSI. Data out of the DSI can be
three-stated through the DCO pin, but in this application this
is not necessary. The UDLT data-channel output can also be
put into a high impedance mode by the SE pin, and again,
this is not necessary in this application.
The asynchronous output and input of the DSI is an NRZ
(Non-Return to Zero) 5-volt CMOS signal that requires level
conversion to be RS-232-C compatible. The MC145406 CMOS
RS-232-C Driver-Receiver chip (U6) performs this function
quite nicely.

AN949
4-32

THE DIGITAL LOOP INTERFACE
The UDLT provides the needed signals for digital loop transmission. The interface circuit shown is a typical circuit designed
to utilize the UDLT features to the fullest. For a detailed description of the digital loop, consult application note AN-943.

THE TELSET-TERMINAL INTERFACE
Figure 4 is the block diagram of the Telset-Terminal Interface. In a telephone system this unit must look like a line card
to the telephone. The data communications port is once again
intended to look like a modem. This portion of the design is
the same as the digital loop interface. The only other variable
part of the design is clock generation.
Clock generation is the sale responsibility of the slave
UDLT. The UDLT has an on-board crystal oscillator that uses
a 4.096 MHz crystal to generate a master clock. From this
clock an 8 kHz sync similar to the one used in the PBX-CPU
Interface is generated. This sync is now called TEl and is used
like MSI except for communication from the mono-circuit. A
sync that is basically the inverse of TEl, called REI, is used to
enable the mono-circuit to output digital voice, and for the
UDLT to receive this voice. The data clock that is generated
(128 kHz) is used to clock the data with respect to TEl and
REI. The DSI will use TEl to clock data to and from the UDLT,
and it will get a master 4.096 MHz clock by tapping off the
crystal oscillator output (X2).
The analog loop interface (see the schematic in Figure 5)
uses the same duplexer circuit for regeneration of the 2-wire
loop, but it must provide the complimentary signalling functions. It must first supply power to the telephone at all times
and be able to tell when the phone is off-hook. Power is
supplied by feeding the ± 5 volt supplies over the loop through
current limiting resistors (R13 + R14). Current flow is detected
through the opto-coupler (U5) when the phone is off-hook,
and then hook status is passed to the loop relay on the PBXCPU interface. Ringing is handled within the modem as opposed to generating the ring voltage and sending it to the
phone. The output of the UDLT signalling channel toggles at
the typical 34012 rate when the PBX is ringing out, so this
output is used to drive a transistor which in turn drives a piezo
speaker. An alternate solution would be to drive a small PMtype speaker that has a capacitor filter to eliminate harsh harmonics from the square waves.

MOTOROLA COMMUNICATIONS DEVICE DATA

Figure 1. Typical Voice/Data Modem Implementation

ANALOG LOOP
TO TELEPHONE
SYSTEM

MC14403
MONO·CIRCUIT

2·TO·4 WIRE
HYBRID

64 kbps

B kbps
SIGNALLING

VOICE

MC145422
MASTER UDLT

CLOCK GENERATOR
DATA

DIGITAL LOOP TO
TELSET·TERMINAL
INTERFACE

8 kbps
RS·232·C LINK
TO TERMINAL

MC145406
RS·232

MC145428
DSI

Figure 2. PBX-CPU Interface Block Diagram

MOTOROLA COMMUNICATIONS DEVICE DATA

AN949

4·33

t~
~!
U3

4.096
MHz

CI4
U5

+5V
I

SWI·5

+5V

RIO
OIl

...

.~

'WI

Iub_o-"-~RECEIVE
~TRANSMIT

OCD

+5V

E:

o

CTS

d
~

>

RTS

8E:
E:

c

R6'-t--......- J

Z

TIP_'

?:j

RING~

o

oz

R7

•

I.............

• 1
9

-5V
)

•

en

o
~

om
o

»~

+5V
Figure 3. PBX-CPU Interface

PBX-CPU Interface Parts List

Rl- 10 MO
R2- 2200
R3- 2200
R4- 1 kO
R5- 10 kO
R6- ff71/2 W
R7- 671/2 W
RS- 560 0
R9- 4.7 kO
Rl0-4.7 kO
Rll-270 kO
R12-10 kO
R13-20 kO
R14-600 0
R15-10 kO
R16-20 kO
R17-1.SkO
R1S-1S0 kO
R19-330 0

Cl- 20 pF
C2- 20 pF
C3- 0.1 p.F
C4- 0.1 p.F
C5- 0.005 p.F 1 kV
C6- 0.47 p.F
C7- 2p.F
CS- 10p.F
C9- 0.1 p.F
Cl0-l0 p.F
Cll-0.l p.F
C12-0.1 p.F
C13-0.1 p.F
Cl4-0.1 p.F
C15-0.1 p.F
Cl6-0.1 p.F
C17-4.7 p.F
C1S-l000 pF

01- lN914
02- lN914
03- lN4001
04- lN4683
05- lN4683
XTAL-4.096 MHz
Ul- 74HCU04
U2- 74HC74
U3- 74HC393
U4- MC145422
U5- MC145428
U6- MC145406
U7- MCl4403
US- 4N26 Optocoupler
U9- MC34012
Ql- 2N2222

n- Lepco P-135S-A
T2- 600 0:600 0
SWl-5:SPOT

Telset Terminal Interface Parts List

Rl- 10MO
R2- 1 kO
R3- 2200
R4- 2200
R5- 1 kO
R6- 10 kO
R7- 270 kO
RS- 10 kO
R9- 20 kO
Rl0-600 0
Rl1-10 kO
R12-20 kO
R13-92 1/2 W
Rl4-92 1/2 W

ClC2C3C4-

20 pF
20 pF
0.1 p.F
0.1 p.F
C5- 47 p.F
C6- 0.1 p.F
C7- 10 p.F
C8- 10 p.F
C9- 0.1 p.F
Cl0-0.l p.F
Cll-l p.F
C12-0.1 p.F
C13-0.1 p.F

ANALOG LOOP
TO TELEPHONE

01- lN914
02- lN914
03- lN4683
04- lN4683
Ql- 2N2222
02- 2N2907
XTAL-4.096 MHz
Ul- MCl45426
U2- MCl45428
U3- MCl4403
U4- MC145406
U5- 4N26 Optocoupler

2·T0-4 WIRE
HYBRIO

Tl- Lepco P-1358-A
T2- 600 0:600 0
SWl-5:SPOT

MC14403
MONO·CIRCUIT

B kbps

RINGER
VOICE

OIGITAL LOOP
TO PBX·CPU
INTERFACE

DATA

RS·232·C LINK
TO TERMINAL

MC1454DB
RS·232

Figure 4. Telset-Terminallnterface Block Diagram

MOTOROLA COMMUNICATIONS DEVICE DATA

AN949
4-35

t~

CTI1
4.096 MHz

OI~

Ii!,
15
R2

R3

OT3:(

XI
SOl

7

+5V
T1

R4

R5

1
LI

Vr.t

VO
+5V

~

1

PO
V
22
00

Iii

BC

RxO

RECEIVE

BRCLK

TxO

TRANSMIT

OCO

_11

'01L02

"" :"II{' ,'" f :l
-5 V-

16
X2
SI2

S02
MCI45426 TE 112
UI
VSS
211 Lol
MulA

~

I

U4=MC145406

RI

OCO

DCI

+5V

•

•

TxS
MCI45428 DL
.·-IVoo
U2
SB
DOE
DIE

-

BRI

~RESET

BR2

10 VSS

+5V

BR3

~
CM

15 DC

4

REI 19
18
Rx
TEl 13
14
Tx

.... III II II P
SWII

r-I U5

I,-

s::

~

:II

o

-

VAG

RI3

+Tx

8
s::
z

IIIII

+5V

I'~U~GTS

ROO

GI3

RGE

..fCi2

MCI4403 TOO 11
U3
10
TOE

TIP ...._ - - - - - - - '

C5
~

~

en
o
~
C5
m
o
»~

SW41

TOC
ROC

+5V~

>

s::
c

SW31

+5V

I

RING II

SW21

1

RxO

MU/A~

-Tx

VOO

Txl
-5 V •

SW5

11

CLK 17

2

1
1

-!

-IVss

16

PiiT
~

Figure 5. Telset-Terminallnterface

-5V
+5V

VLS

h

::IE

.....::. VLS

C4

7
6
17
13
14
18

.!!..,
131
14
15
11

TOE 10
VSS 8

C5T'"
-=

7

l R1O'l

-5 V

+5V
1
SYNC TO

Cl0

1T

POWER SUPPLY

Figure 3. Digital Telephone Schematic

SOl
SI1
CLK
TEl
T
I
RI

19 REI
,ll. TE

~ Vss

-=-

~

~

~
~

-<>'-0--<>'-0- -<

1

9
6
7

"'-

-0 '0- -<
-0'-0- -<
-0'-0--<

8
5

t*1

-

C7

X2 16

PO.!!........

<>

::IE

XI

CJRI6~

T"

Vre' 2

C9 :::

~

C6

~

XI 15
-To'
idA.!!L.......
L021"2::..0-I--I'I.""",-,"""r--<"I1
LB L...
-<
21
-<
LOI
U 3
VO iCll

':...
-

+5 V

VOO 22

~
~

FEMALE
OB-25

+5V
R37-R41.'
~
. SW3-SW7
~
-

~8
VSS ~

~S12
POI
TOC
ROC
RCE
ROO
TOO

:

::

1

17 00
TIS
14 OOE
8RCLK
DIE
OL
L......-1. TIO '" SB
II:;!
12 RIO ~ 8Rl
.:.::. RlS u BR2
RST ::IE BR3
-=OC
BC
,......!! OCO
CM

R12

-!:
LI= #1
:!
L...

9

-~V

T T

~

I

~
1-

~

C14 ...lf12

R13

R14

'I

~

~
~

-=

~ VAG

.-I

"I...L IC1

...

~
~

R5

: TI
R3
R4 ........--,I--.....::..tidA
r'lllIIt1Io---+---+---:'4='lTII
R2
16 VOO
~v.-_-+_-+_..::.j2 RIO
3
RI
.....::. TI +

I
I

R35

~

05

OPL 17

~C2

c3 L
s

1

MO~

rl

~

CDC»

fi

,LEO T

3
. - - - - ' 44C1C1
..---"""":"IiCC22

~
~

CIt:R2';1

-4-

o

»
i"ii
WOI

Yin 1
CO 3
FCI 2
FC2 f-J.!:13

~

+5V

o
m

R25

~

~

r

SW1:CLOSEO=ON HOOK
OPEN=OFF HOOK

(IJ

T

R23

L.!.

~

-=

~

~

L:

..3

T2

TIP
TO POWER
SUPPLY Yin

RING
SEE FIGURE 5

+5V-----------1~~~~
GND------~--_1~--~~
-5V-------r--~~~~-J

SYNC IN

DR1

FIgure 4. Switching Power Supply

PARTS LIST FOR FIGURES 3, 4, AND 5
,Resistors

Capacitors

Diodes

Rl
R2
R3
R4
R5
R6
R7
RB
R9-Rl0
Rll-R13
R14-R15
R16
R17
RIB
RI9-R22
R23
R24-R25
R26
R27

Cl-C3
C4-C5
C6-C7

01
02-011
BRI

22 kl:'
3.3 kll
7.5 kll
47 kll
22 kll
10 kll
62011
1 kll
1011
10 kll
100 kll
10 Mil
10 kll
5 kll
11011
75 kll
100 kll
10 kll
3 kll
R28
9.1 kll
R29
1.3 kll
R30
22 kll
R31
2.2 kll
R32
220kll
R33
1011
R34
100 kll
R35
56011
R36-R41 10 kll

O.I,.F
10,.F
20 pF
CB-C9
O.I,.F
Cl0
10,.F
Cll-C15 O.I,.F
C16
0.005 ,.F
C17
O.I,.F
CIB
0.005 ,.F
100 pF
C19
C20
O.OI,.F
330 pF
C21
C22
loo,.F (50 VI
C23-C24 loo,.F (16 VI
C25
10,.F (16 VI
C26
O.I,.F
C27
510 pF
C28
O.I,.F
10,.F (16 VI
C29
C30
O.OI,.F
Transformers
Tl: Power Transformer
Coilcraft G6808-A
T2: Line Transformer
Coilcraft G6320-0 or
Lepco P-I358-A

lN5819
lN4148
3N248 Bridge Rectifier

Integrated Circuits
MCI4513
MCI4403
MCI45428
MCI45426
MCI45406
MC34119
MC34129

Dialer
Mono-circuit
Data Set Interface
Slave UOLT
RS-232 Transceiver
Speaker Driver
Power Supply Controller

Optocoupler
MOC5007 High-speed Optocoupler
Transistors
Ql-Q2 2N3904
2N5551 160 V NPN
MTP2N2O Power MOSFET
Q5
2N3904

Q3
Q4

Switches
SWI
SPST Hookswitch
SW2-SW7 DIP Switches

Inductor
Ll

AN968

4-40

80 ,.H each winding on a common core

MOTOROLA COMMUNICATIONS DEVICE DATA

(every 125 /LS), so the transceivers effectively exchange 80
kbps of full-duplex synchronous data. The data is arranged
into three channels, a 64 kbps full-duplex voice channel and
two 8 kbps full-duplex data channels.
The slave UDlT generates all timing signals used by the
digital telephone. Timing is synchronized to the received bursts
from the master UDlT. A 4.096 MHz on-chip crystal oscillator
is the basis for all clocks. A 128 kHz clock (ClK), which drives
the mono-circuit's 0/ A and A/D circuits and synchronizes the
power supply, is produced. An 8 kHz clock (TE1 and RE1) is
also produced. Any timing slip from master to slave UDlTs is
corrected every 125 /LS, keeping the master and slave devices
in perfect synchronism. The baud rate generator in the data
set interface is driven by the 4.096 MHz clock on the slave
UDlT.
The burst received from the master's transmission is input
on the slave's line input (ll) pin. The burst is demodulated,
separated into the three channels, then output on the digital
side of the slave every 125 /LS. Eight voice bits are output
serially from the transmit data output (Tx) on the rising edges
of ClK while TE1 is high. One signalling bit is output on
signalling output 1 (501) on the rising edge of TE1. The outbound signalling channel one provides the ringing signal for
the speaker amplifier (MC34119). The other signalling bit is
output on signalling output 2 (502) to the data set interface
(MC145428), also on the rising edge of TE1. This channel,
both inbound and outbound, carries the data between the
attached terminal and the data switch or computer at the
voice/data multiplexer or PBX.
After the slave receives a burst from the master, it transmits
a 10-bit burst of its own back to the master. The slave outputs
this burst on its line driver outputs (l01, l02) which are pushpull drivers configured as a balanced bridge. These outputs
directly drive the line transformer through a resistor loading
and protection network (see Figure 5). The 10 bits of data
which are transmitted to the master are input every 125 /LS.
Eight bits of voice data are input serially on the receive data
input (Rx) on the falling edges of ClK while receive data enable
(RE1) is high. A signalling bit which carries the digital telephone's hookswitch status back to the voice/ data multiplexer
is input on signalling input 1 (511) on the rising edge of TE1.
Data from the attached terminal or PC is input on signalling
input 2 (512), also on the rising edge of TE1.
Transformer T2 interfaces the twisted pair wire to the
UDlT's l01, l02. and LI pins. It performs the functions of
impedance matching, bandwidth limiting, and gain adjustment

Voo

R20

,...,.-'V\I\r+--+-I-Nl.,,""",. TO LOI
R22

......,."""tv-+-+--+...AJ'w-....

TO L02

DID

,..."""tv-+-+.......I,Jw-_ TO LI
R17

'-'---+--1-+---- To Vrel
Figure 5. Line Interface and Protection

MOTOROLA COMMUNICATIONS DEVICE DATA

for the receive signals. At the frequencies of interest (128 kHz
and 256 kHz), ordinary telephone wire has a characteristic
impedance of about 110 ohms. The loading resistors R19-R22
between l01, l02 and the Tx winding of the transformer are
set to 110 ohms. The series combination of these resistors is
significantly higher than the 20-0hm output impedance of the
l01 and l02 drivers causing the resistance presented to the
transformer to be set primarily by the resistors alone. Clamp
diodes 06-09 protect the l01 and l02 outputs from transient
signals on the twisted pair. Line settling between data bursts
is improved by selecting a bandwidth of 20 to 512 kHz for the
transformer interface. The lower corner frequency is set by
adjusting the inductance of the transformer's Tx winding to
1.75 mHo The upper corner frequency is determined by the
design of the transformer winding technique.
The impedance matching network on the transmit side of
the transformer attenuates the transmitted signal by 12 dB.
This loss is recovered in the receive side of the transformer.
A step-up of 4:1 directly compensates for the 12 dB loss. As
with the transmit side, a protection network is required. 010
and 011 clamp the received signal to a safe level but are
sufficiently isolated by R17 so that they do not load the transformer when they are conducting. At 192 kHz (the spectral
peak of MDPSK), 26 AWG wire attenuates signals about 17
dB/km. The receiver in the UDlTs has sufficient input dynamic
range to operate on loops as long as 2 km. Transformers which
are designed for the UDlT system may be obtained from:
Coilcraft, Inc.
1102 Silver Lake Rd.
Cary, Illinois 60013
Part Number: G6320-D
leonard Electric Products Company
85 Industrial Drive
Brownsville, Texas 78521
Part Number: P-1358-A
The transformer from Coilcraft is similar to the leonard
Electric device, except it has a Faraday shield between the Rx
and Tx windings and the line windings. The shield helps reduce
the spurious radiation from the digital circuitry onto the twisted
pair.

CODEC/FllTER
The MC14403 codec/filter is a PCM codec-filter which performs 0/ A, A/D, band-limiting, and reconstruction filtering
for the voice signals in the digital telephone. Analog voice
signals in the 300 Hz to 3400 Hz frequency band are sampled
at an 8 kHz rate. The samples are converted into a pseudologarithmic code known as PCM and passed to the UDlT for
transmission to the voice/data multiplexer or PBX. Received
digital signals are reconstructed at an 8 kHz rate back into
analog voice signals.
Three signals are available for use on the analog input amplifier. They are Tx + (noninverting input), Tx - (inverting
input), and Txl (filter input). Sidetone (feedback from the
handset microphone to earpiece) and gain balance are controlled with external components around the Tx and Rx operational amplifiers in the codec/filter. Tx + is tied to ground
and a gain setting resistor is placed between Tx - and Txl.

AN968

4-41

The microphone output from the handset and the OTMF output from the dialer are both ac coupled to the Tx - input. The
output of this amplifier is digitized and output to the UOLT on
TOO on the eight rising edges of TOC when TOE is high.
~igital data is input from the UOLT on ROD on the first eight,
falling edges of ROC after the rising edge of RCE. This data
is reconstructed and output on the analog output pin (RxO).
This signal is summed with TSO from the dialer and Txl and
applied to the speaker in the handset.
A decoupling RC filter is used to attenuate any power supply
noise seen at VCC and VSS of the codec/filter. This filter
consists of 10-ohm resiStors in series with the power feed to
VCC and VSS with 10 "F capacitors from VCC and VSS to
ground. Also, to reduce noise in the ground paths, a stargrounding scheme is used where all ground pins of the circuits
are connected to the power supply's central isolated ground.

DATA SET INTERFACE
The MCl45428 data set interface (OSI) is an interface between an asynchronous data terminal and the synchronous 8
kbps full-duplex data channel of the UOLT. The OSI performs
basic UART functions of start-bit and stop-bit detection of the
asynchronous data. It also detects and transports break signals
over the synchronous link. Start and stop bits are stripped
from the data which is then loaded into a FIFO. The data is
then sent to the UOLT for transmission to the far end of the
digital link. On the receive side, the reverse of these actions
is performed. Special synchronization characters (transparent
to the user) are exchanged between OSls to maintain synchronization. The OSI has an internal clock generator which
produces the most commonly used baud rates. The OSI is
capable of operating at data rates up to 128 kbps, however
this application uses 9600 baud.
On the synchronous side of the OSI, data is output to the
UOLT on the data channel output (OCO) on the falling edge
of data clock (DC) while the data output enable (DOE) is high.
Data from the OSI is input and output by the UOLT on SI2
and S02 respectively. DC is connected to TEl of the UOLT.
DIE and DOE are connected to VOO, permanently enabling
the synchronous inputs and outputs. RESET is connected to
the hookswitch, clearing the FIFOs and resetting the device
when the digital telephone is not in use.

RS-232 DRIVER/RECEIVER
The RS-232 interface is connected as follows. Asynchronous
serial data from the attached data terminal (Tx DATA, RS-232
pin 2) is through a receiver on the MCl45406 RS-232 driver/
receiver and connected to the transmit data input (TxO) of the
OSI. Asynchronous serial data from the OSI is output on the
receive data output (RxO) and fed through a driver on the
MCl45406 to the data terminal (Rx DATA, RS-232 pin 3).
Another output of the OSI, transmit data status (TxS), is used
to generate a clear-to-send signal for local flow control
(CLEAR-TO-SENO, RS-232 pin 5). TxS goes low when there
are two words in the OSI's transmit FIFO and must be inverted
to provide the'CTS function. TxS is applied to a receiver of
the MC145406 for inversion and then fed through a driver to
convert the signal to RS-232 levels. The MCl45406 threshold
for the RS-232 receivers is 1.8 volt so it may be used as an
inverter for ordinary digital signals. The receive data status

AN968
4-42

(RxS) pin of the OSI may be used as a carrier detector. Since
it goes high when synchronization with the far-end OSI is
established, it must also be inverted before conversion to RS232 levels. As with the TxS signal, an RS-232 receiver is used
an an inverter. The inverted signal is then converted to RS232 levels by a transmitter and applied to RECEIVED LINE
SIGNAL DETECT, RS-232 pin 8. The baud rate, word length,
and number of stop bits used on the asynchronous side of the
OSI are controlled by five pins: BR1-BR3, OL, SB. These
inputs are controlled by a DIP switch. Table 1 shows the switch
settings to configure the asynchronous data port.

DIALER
The pulse tone repertory dialer (MCl45413) converts keyboard inputs to either pulses or dual tone multiple frequency
(OTMF) or Touch-Tone outputs for use in telephone dialing.
This device also provides last number redial and a nine number
repertory memory. The digital telephone in this application
uses a 3 x 4 class A single contact keyboard, although a 4 x 4
keyboard could have been used for enhanced features. The
MCl45413 operates in pulse mode at either 10 or 20 pulses
per second, or tone dialing modes. These modes are determined by the mode select (MS) pin.
When the pulse dialing mode is used in this telephone,
dialing information is output at 20 pulses per second. Note:
The PBX used with this telephone is capable of accepting
dialing pulses at this rate. Other applications may require the
pulses at 10 pulses per second, in which case the wiring of
the DIP switch would have to be modified appropriately. The
pulse output OPL, is an N-channel open-drain transistor which
is wire-ORed with the hookswitch. This point is sampled 8000
times each second by the UOLT, and the status is passed to
the loop monitoring circuitry in the voice/ data multiplexer on
signalling channell. In the tone dialing mode, dialing informatiCm is output as tones corresponding to the row and column
pressed. This signal is output on the OTMF OUT pin of the
dialer and is coupled to the analog input of the codec/filter.
The analog OTMF signal is thus carried to the PBX in digital
form on the 64 kbps voice channel.
Table 1. DIP Switch Settings
Pin
Name

Low

Baud

BR3

BR2

9600

0

1

1

9 bits

4800

1

0

0

High

BRt

DL

8 bits

SB
MS

One

Two

2400

1

0

1

Tone

Pulse

1200

1

1

0

300

1

1

1

SWITCHING POWER SUPPLY
Figure 4 shows the schematic of the switching power supply
for the digital telephone. This power supply has the capability
of supplying about 900 mW of power at ± 5 V when the length
of the loop is 2 km. As the loop length is increased, the power
available at the phone is reduced. To maintain stability of the
power supply, the maximum power consumed by the phone
(including the efficiency losses in the power supply) must be

MOTOROLA COMMUNICATIONS DEVICE DATA

less than 90% of the maximum power available (MPA) at the
maximum loop length.
MPA = Vsource2 /(4. Rloop)
Example:

(pin 13) and power is supplied by the + 10 V output. This
start-up sequence allows the power supply to reliably start in
the presence of high source resistance seen at the end of a
long twisted pair wire. Efficiency of this power supply is approximately 80%.

Rloop for 2 km of 26 AWG wire = 576 0
APPENDIX
MPA=4s2/(4.576 0)=1 Watt

The ± 5 V outputs are isolated from the twisted pair so that
a local ground reference may be established with the terminal
attached to the RS-232 port.
The switching power supply operates by repetitively storing
and releasing energy in a transformer. The energy is stored in
the primary winding of transformer Tl for part of the switching
cycle and discharged into the load through the secondary
during the remaining part of the cycle. The controller for this
power supply is the MC34129 high-performance current-mode
power-supply controller. The MC34129 controls the current
(energy) in the primary winding by varying the duty cycle of
the power switch (Q4). As the duty cycle is changed, more
or less energy is stored under control of the MC34129 to maintain regulation of the output voltage. The switching frequency
of the power supply is synchronized to the 128 kHz clock signal
used by the codec/filter by bringing ClK from the UDlT
through an opto-isolator (MOC5007) into the sync input (pin
4) of the MC34129. Synchronization improves the idle-channel
noise performance of the codec/filter and minimizes the filter
requirements on the output of the power supply.
The input voltage for the power supply is taken from the
48 V available on the twisted pair. A 0.1 ,..f capacitor is placed
between the two line windings of transformer T2. The dc
voltage across the capacitor is then routed through a balanced
three-pole elliptical lowpass lC filter (ll and C16-C18) and a
full-wave rectifier before being applied to the input ofthe power
supply.
The power supply is regulated by two methods. Current in
the primary winding is sensed as a voltage across resistor R30.
Also, the + 10 V nonisolated output is sensed by being fed
back to the voltage divider formed by resistors R25 and R26.
The controller maintains the voltage across R26 at 1.25 V by
varying the switching duty cycle. This forces the output voltage
to be 10 V. Regulation of the +5 V isolated outputs is maintained by the magnetic coupling from the 10 V winding to the
+ 5 V windings. Because the primary current is sensed by the
MC34129, pulse-by-pulse overcurrent limiting is automatically
achieved. The power supply is thus fully protected against
short circuits on the outputs. If an overload occurs, the
MC34129 will shut the power supply down and attempt to
restart. When the overload is removed, the power supply will
again begin normal operation.
During normal operation, the MC34129 is powered by the
+ 10 V output. However, since there is no voltage atthis output
when the circuit is first started-up, provisions must be made
to power the circuit from another source until the outputs are
stable. Transistor Q3 and the Start/Run output perform this
task. During start-up, Q3 is biased on and power for the
MC34129 is taken from the 48 V on the twisted pair through
R28. After the power supply has completed the soft-start cycle
and stabilized, transistor Q3 is turned off by the Start/Run pin

MOTOROLA COMMUNICATIONS DEVICE DATA

On the printed circuit board there are three connections
available for the hookswitch (SW1). These are +5 V, GND,
and Sil. The following is a list of several implementations of
the hookswitch.
1. Mechanical SPST switch (normally open) - In this
configuration the lED, R32, R31, and Q5 are not needed
unless an lED signal is desired.

.------II'

00_-+-__ H.S.
H.S. GND

\ ..

h ,
t _____

2. Mechanical SPOT switch (normal position
shown) - In addition to the components listed in the
above implementation, R14 and Q2 are not needed.

i

H.S. GND

00--;1-- H.S.

----f-o..-..
I
,

OO~If-1______
,

02 CDLLECTDR

3. Reed relay in handset (magnet in telephone case) The figure below shows how to modify the handset for
this application.

,._-------------I

MIC

I

:

WHITE

I
I

I

RED

'----+---+-- SPK
.------,
BLACK
,
'
H.S. GND
•
I:' \0b
WHITE
'-__C>_-_~_,t---.;.;;;..-+-H.S.
4. Hall Effect Device in telephone case (magnet in
handset) - For this and the previous application, a mechanical SPST switch can be used in parallel for on-hook
operation.
VOUI
HED

GND
VCC

H.S.
H.S. GND
H.S. VCC

AN968
4-43

MOTOROLA

-

SEMICONDUCTOR
TECHNICAL DATA
AR239

IMPLEMENTING INTEGRATED OFFICE
COMMUNICATIONS
By Tanya Tussing
Telecom Applications Engineer
Motorola, Inc.
Austin, Texas
INTRODUCTION
ISDN has gotten a lot of attention during the course of
the last year, and rightfully s. flows
through Da and Ra setting the inverting input of the
comparator at 1.5 volts below Rs (pin 6). The majority
of the input current, however, flows through R3, and
the waveform across it is filtered by C3 and the internal
50 k resistor before being applied to the non-inverting
input of the comparator. When the input voltage is
increased sufficiently so that the current through R3
causes the voltage at the non-inverting input to be more
than 1.5 volts below R s , the comparator's output
changes to a low state, allowing the oscillator's signal
to reach the piezo transducer. Additionally the value of
Ia is reduced by 20% in order to provide hysteresis to the
comparator.
The 22 volts zener diode provides regulation for the
internal circuitry, and C4 filters noise and ripple from
this voltage. The input current must be at least 0.5 rnA
for the regulation and bias circuits to function properly.

The MC34012 and MC34017 electronic tone ringers
were developed to replace the bulky electromechanical
bell assembly of a telephone, while providing the same
basic function. When used in conjunction with a piezo
ceramic transducer, these circuits will output a warbling sound in response to the applied ringing voltage.
With some imagination, however, the circuits can be
used in a variety of ways, including non-telephone
applications, - wherever an alerting sound or indication is required. Applications include appliance
buzzers, burglar alarms, safety alerting functions,
special sound effects, visual ringing indicators, and
others. The circuits in this application note show how a
variety of effects can be obtained.

HOW THE MC34012 WORKS
A block diagram is shown in Figure 1. An AC
voltage is applied to the input terminals, and the
current is rectified by the full wave bridge. The six
C1

~(2)
/
Input VAC

r-----------------------,
I

\

I
I Rs(S)

~

AC1 1
I
(3) 1-::-

AC2

& Clamp

(8) I

C2

R21
I

Oscillator
&
Dividers

:
L _____ - -

--r

Buffer

,

-=-

Rg(1)-- - - - - - =-N':;-m~ers in parenlheses

-

are pin numbers.

FIGURE 1 - MC34012 Block Diagram

MOTOROLA COMMUNICATIONS DEVICE DATA

AN933
4-49

The oscillator is a relaxation type, with the frequency determined by the values of R2 and C2. The
base frequency (f = (0.6711R2C2) + 200 Hz) is divided
down to produce two output frequencies (fl4 and f/5)
which are outputted alternately at a warble rate deter·
mined by the base frequency, and the specific tone
ringer model used. The MC34012-1 produces a warble
rate of f/320, the MC34012-2 produces a warble rate of
f/640, and the MC34012-3 produces a warble rate of
f/160. The base frequency (f) should be selected to be
between 1500 Hz and 10 kHz.
The output buffer is a totem· pole configuration with
a25 rnA source-sink capability, and is intended to drive
a piezo ceramic transducer. The output waveform is a
20 V p.p square wave.

HOW THE MC34017 WORKS
A block diagram is shown in Figure 2. The external
components are labeled the same as in Figure 1.
Operation is very similar to the MC34012 with the
following differences:
a) The output to the piezo transducer is a push· pull
configuration, rather than single ended, providing 40
Volts pop.
b) The comparator's inputs are referenced to ground
rather than to the supply voltage. V r is 1.2 volts when
the comparator's output is off (low), and 0.9 volts when
the output is on.
c) The configuration consisting ofthe comparator, R3,
and C3 sense the incoming current to determine the
turn-on and turn'offtrip points. When the voltage atRs
exceeds 1.2 volts, the comparator changes state to turn
on the output.

SAMPLE CIRCUITS
The circuits of Figures 3 & 4 provide ON-DELAY, ie.,
Rl

Cl

~(1)
/
Input VAC
\

after applying voltage to the input terminals, sound is
not produced until a delay period has elapsed. The
output sound is continuous after that. The delay is
primarily determined by C3 in the Figures, although
R3 and R1 also affect the timing. The circuit may be
controlled by turning on and off the voltage to the input
terminals, or by leaving the input voltage applied
continuously, and using a normally closed switch
across C3 (open switch to start timing). Power consumption is typically less than 3/4 watt. Applications
include time out circits for burglar alarms, dark room
equipment, and others.
The circuits of Figures 5 and 6 provide OFF-DELAY,
i.e., sound is produced immediately upon applying an
input voltage, but then turns itself off after a delay. The
delay time is determined by Ct. The circuits (as shown)
have a long reset time (time for Ct to discharge after
removing the input voltage) and so the user may want
to consider providing a quick discharge path for Ct
whenever the input voltage is removed (such as an
extra set of contacts on the on-off switch). The particular application will determine the need for this. Applications include warning buzzers in washing machines,
microwave ovens, alarm clocks, and other appliances.
The circuits of Figures 7 and 8 cause the sound
output to be cycled on and off at a rate determined by
Ct. The duty cycle can be varied by changing Rd. The
LM393A dual comparator (configured as an oscillator)
needs only 1 rnA of power supply current, and so it is
powered directly from the tone ringer's RI pin. Several
cycle times are listed in the Figures, and can be used to
indicate different conditions, such as "WARNING"
(slow cycle), and "EMERGENCY" (fast cycle). Applications include appliances, alarm clocks, emergency
indicators on hot water heaters (overtemperature) and
furnaces, smoke detectors, and any place where an
attention getting'sound is required.

r------------------------,

,I

2...

ACl I
I

I RI(4)

(8) 1-=

C2

I Ro 2(3)
I

-

------ ---"j:"R;;i7j------ - =-N:;-m~ers in parentheses
-=

are pin numbers.

FIGURE 2 - MC34017 Block Diagram

AN933

4·50

MOTOROLA COMMUNICATIONS DEVICE DATA

Rl

r----------------------,
I
I

(2)

ACl I
I

/
\

Input VAC

(3) I

~

I Rs(6)

=-

-l

Optional

Q (See Text)

~--r--------¢~~~-J

MC34012

C2
680pF

Input
VAC

Rl

R3

C3

On
Oelay

24

100

1600

100"F

30 Sec

120

16 k

750

1000"F

30 Sec

120

16k

750

100"F

10Sec

are pin numbers.

FIGURE 3 - On Oelay Timer Using MC34012

Rl

(1)

r-----------------------i

ACl I
I

/

Input VAC

\

(8) I

~

I RI(4)

-=

C2
loo0pF

MC34017
I Ro2(3)

-

I

---------jtRa)----------~

-=

g

On
Delay

Input
VAC

Rl

R3

C3

24

1.0k

15k

500/iF

15 Sec

24

1.0k

15k

2200 "F

75 Sec

120

33 k

15k

500"F

8 Sec

120

33k

15k

2200 "F

40 Sec

- Numbers in parentheses
are pin numbers.

FIGURE 4 - On OelayTimer Using MC34017

MOTOROLA COMMUNICATIONS DEVICE DATA

AN933

4-51

R1
/

16k

120VAC

\

~------A~C~2~-+~

MC34012

C2
680 pF

-=
are pin numbers.

- Delay is 5 seconds.
FIGURE 5 - Off Delay Timer Using MC34012

- Numbers in parentheses
are pin numbers.

Off

Ct

Delay

20"F

17 Sec

10"F

7 Sec

5.0"F

4 Sec
FIGURE 6 - Off Delay Timer Using MC34017

AN933

4-52

MOTOROLA COMMUNICATIONS DEVICE DATA

Rl

4700

MC34012

(8) I

C2
680pF

R21
200k

Oscillator
&
Dividers

:

-=

Buffer

L _____ - - -

-=
On/Off
Cycle Time

16 k

lOOI'F

.2 Sec/.2 Sec

500l'F

3 Sec/3 Sec

lOOOI'F

8 Sec/8 Sec

,

-=

-y Rg(1)----=-Numbiirsiil pa~ntheses
are pin numbers.

lN914

I

O. 1

75k
27k

36k

LM393A
FIGURE 7 - On/Off Timer Using MC34012

6200

Rl

/
1.0k
24VAC

\

MC34017
I Ro 2(3)
-

I

---- - - - - -~ Rg (7)" - - -=-Nu;;;be~;;:; pa-;;'~heses
-=-

are pin numbers.

47

FIGURE 8 - On/Off Timer Using MC34017

MOTOROLA COMMUNICATIONS DEVICE DATA

AN933
4-53

The circuits of Figures 9 and 10 provide a special
effects sound by varying the frequency of the base
oscillator. The 2N3904 transistor is slowly turned on
(as Cs charges up) thus varying the equivalent resistance at the Rc pin. This causes the frequency of the
base oscillator to vary from low to high over a period of
several seconds. C s determines the rate at which the
audio frequency is swept, and Ct determines how often
the sweep cycle is repeated. The sound effects produced
by this circuit are similar to those heard in many video
games (home and arcade type), and in children's games
and toys with sound effects. The two sweep circuits are
different as they produce different effects. The circuit of
Figure 9 uses feedback (via the51 k resistor and the two
portions of Cs ) to generate a different linearity sweep
curve than the simpler circuit of Figure 10. Either
circuit can be used with the MC34012 or the MC34017
by making appropriate connections at RI and Rc.
The circuits of Figure 11 & 12 are Ring Detector
Circuits. Designed for use on the telephone line, they
provide an output voltage level to indicate the presence

of a ringing signal. (The 1.0 I'F capacitor at terminal
AC1 is necessary to meet FCC impedance requirements.) The output, at Vout, is high (+12 V) as long as
anAC voltage is present on the Tip and Ring terminals.
The optocoupler provides isolation from the circuit to
be controlled, since telephone lines cannot be referenced to earth ground. The 1.0 k and 100 k resistors, and
theO.1l'F capacitor, filter the square wave output of the
integrated circuit to provide a steady voltage at Vout.
The output can be used to turn on a light, activate an
answering machine, alert a computer that data is to be
sent to it, and for many other uses. The circuit shown is
not limited to telephones, however. By changing the
value ofRl to 15 kohms for 120 VAC, or to 100 ohms for
24 VAC and deleting the 1.0 I'F capacitor (as in the
previous examples), the output will indicate the
presence of an input voltage while providing isolation.
Isolation can be used to prevent unwanted ground
loops, or for safety reasons such as to meet UL
requirements (the 4N25A and 4N35 optocouplers are
UL listed).

Rl

12000

MC34012

150k

C2
2oo0pF

10M

47
3Sk

3900

- Numbers in parentheses
are pin numbers.
Ct:::r:
151'F

-=

10k

FIGURE 9 - Audio Frequency Sweeper Using MC34012

AN933
4-54

MOTOROLA COMMUNICATIONS DEVICE DATA

- Numbers in parentheses
are pin numbers.

FIGURE 10 - Audio Frequencv Sweeper Using MC34017

MOTOROLA COMMUNICATIONS DEVICE DATA

AN933

4-55

r------ - ---------- ------,
I
I
-.!..
I R (6)

1.0 1'F" (2)
Tip~
Rl
ACl I
6800
I

s

(3) I ':"

Ring

1800

0-----:-':=<1--4---'

MC34012

C2
680pF

"The capacitor must be rated 250 V min.
and be non-polarized. It is necessary
to meet FCC requirements.

- Numbers in parentheses
are pin numbers.

FIGURE 11 - Ring Detector Circuit Using MC34012

r------------------ ------,

1.01'F*(1)
Tip~
Rl
ACl I
6800
I

I

I
I RI(4)

2....

(8) I ':"

Ring

D----:-':~--4---'

C2
1000pF

MC34017

"The capacitor must be rated 250 V min.
and be non-polarized. k is necessary
to meet FCC requirements.

- Numbers in parentheses
are pin numbers.

FIGURE 12 - Ring Detector Circuit Using MC34017

AN933

4-56

MOTOROLA COMMUNICATIONS DEVICE DATA

The circuit of Figure 13 will count the number of
times the ringing voltage is sent to the telephone, and
will not allow the piezo transducer to sound until a
certain number of ring cycles (selected by SI) have
passed. The circuit values are based on a typical ringing cadence of2 seconds on, 4 seconds off. The outputs
ofthe MC14017 counter (QI-Q9) become active sequentially with each cycle of the ringing signal. When the
selected output becomes active, the MC14013 flip-flop
changes state, and the piezo transducer sounds. The Q
output of the MC14013 can be used to activate other
circuitry such as an answering machine. After the

ringing signal stops due to answering the phone, or the
caller hangs up, the counters and the flip-flop are reset.
Note the two separate grounds - the telephone line
must be kept separate from the circuit ground.
As a final note, many applications will be enhanced
by the addition of a volume control. Simply connect a
10 k potentiometer in series with the piezo sound trans·
ducer. The sound output level will then be controllable
over a substantial range. Additionally, if the particular
transducer being used has a high frequency shrill in its
sound, the series resistance can remove the high
frequencies, and produce a more pleasant sound.

1800

1.0 !IF'
TIp

~

Ring

MC34012

4

38

680pF

200k

Piezo
Sound
Transducer

1000pF
'The 1.0 !IF capacitor must be rated 250 V min.
and be non·polarized. It is necessary
to meet FCC requirements.

:

Jt;:

I
I

FIGURE 13 - Ring Signal Counter

MOTOROLA COMMUNICATIONS DEVICE DATA

AN933

4-57

MOTOROLA

-

SEMICONDUCTOR
APPLICATION NOTE

AN937

Application Note

A TELEPHONE RINGER WHICH COMPLIES
WITH FCC AND EIA IMPEDANCE STANDARDS
Prepared by
Dennis Morgan

INTRODUCTION
The MC34012 and MC34017 Tone Ringers are designed to replace the bulky bell assembly of a telephone, while providing the same function and performan~e under a variety of conditions. The operational
requirements spelled out by the FCC and the EIA,
simply stated, are that a ringer circuit MUST function
when a ringing signal is provided, and MUST NOT
ring when other signals (speech, dialing signals, noise)
are on the line. This application note discusses how the
IC's operate, the specific operational requirements to
be met, and how they are met. Only "on-hook" requirements are discussed since off-hook operation is not
applicable.

ON HOOK IMPEDANCE REQUIREMENTS
The FCC Rules & Regulations, Part 68, define the
on-hook impedance (while ringing) requirements, as
well as the ringing voltages and frequencies. EIA
Standard RS-470 expands upon the requirements to
include minimum impedance during the non-ringing
(quiescent) state. The FCC requirements were promulgated so that any newly designed equipment, meant for
connection to the Tip and Ring lines, be Compatible
with the already existing Bell Telephone network and
central office equipment. The measured impedance, in
all cases, is defined as the quotient ofthe applied rms ac
voltage divided by the true rms measured current.
For the quiescent state, EIA Standard RS-470 provides the minimum impedance requirements at low
voltages «10 Vrms ) in the 5-3200 Hz range to provide
for the loading presented by an on-hook extension
phone's ringer circuit to the dialing and speech signals
coming from a parallel off-hook phone. Table 1 and
Figures 1 & 2 indicate the minimum values. The dc
resistance limits of Table 1 keep the telephone from
consuming significant power when idle since most
phones are on-hook the majority of the time. The lower
frequency range of the ac resistance limits includes all
of the standard ringing frequencies, and so has a
higher applied voltage limit than the upper frequency
range, which covers the speech and DTMF signals.
In the ringing state, the limitations for ringer
impedance are based on the REN (Ringer Equivalence
Number), which is an indication of the power consumed
by the ringer circuit during ringing. The FCC regulations state that the total REN for any individual
AN937
4-58

telephone line cannot exceed 5.0, where the total REN
is the sum of the REN of each device connected to the
line (answering machine, protection devices, as well as
each telephone). The specific impedance values listed
in the FCC Regulations (Section 68.312, paragraphs b
& c, and Table 1) correspond to a REN of 5.0, and are
therefore the minimum allowable system impedances.
EIA Standard RS-470 provides the same information
for the on-hook dc and ac resistance (while ringing),
except that the listed values differ by a factor of5 from
those listed in the FCC Rules. The EIA information is,
therefore, not a set of limits, but rather a definition of a
1.0 REN. (Originally the 1.0 REN was defined as the
load presented by the electromechanical type ringer of
a standard Bell Telephone Co. 2500 series telephone.)
TABLE 1

QUIESCENT STATE LIMITS
DC RESISTANCE (between Tip and Ring)
>50 Mohms for 0-100VDC
> 150 kohms for 100-200 VDC
AC RESISTANCE (between Tip and Ring)
For 5 Hz 4 x Z at 10 Vrms

The specifications of Table 2 includes not only the
ringing impedance guidelines of RS-470, but also the
voltages and frequencies at which the ringer circuit
MUST ring. When testing a circuit to the conditions of
Table 2, the minimum measured impedance within
each voltage and frequency range is divided into the
impedance listed for that range. The largest number
obtained over the full set of ranges for a ringing type is
the REN for that circuit. In addition to the specifications of Table 2, RS-470 and the FCC Rules require that
the ac ringing impedance of an individual device be
less than 40 kohms, unless that requirement is already
provided for by some other parallel device.
In addition to the above ac specifications, the dc
requirements impose an upper limit of 0.6 dc rnA when
any ofthe Table 2 ringing signals are applied.
MOTOROLA COMMUNICATIONS DEVICE DATA

(NOTE: The type A ringers mentioned in Table 2
refer to the inherently, frequency selective electromechanical type ringers used for decades in the typical
single-line (non-party line) telephone_ Type Bringer
specifications cover a wider frequency range, and were
deVeloped with the advent of electronic ringers which
are generally not frequency selective_ Ringer types C
through Q, listed in the FCC and EIA specifications,
are selective to specific frequency ranges for the
purpose of party line applications, and are not discussed here_)
TABLE 2

RINGING CHARACTERISTICS
Ringing Type

Frequency
(Hzl

A
A, B
A
A
A
A
B

Voltage
(Vrmsl
40-130
55
40-130
40
40-130
40-130
40-150

17
17
20
20
23
27-33
15.3-68

100

80

e

w

u

70
60

z

50

0..

40

2iw
~

\

0-105
0-105
0-105
0-105
0-105
0-52.5
0-105

7
10
7
8
6
5
8

I

Impedan~e (k!ll

5
15
20
30
50

50
11
7
5
3
3

2f

\

\

30

Acceptable

\

20

Unacceptable
10
0

Impedance
(kohmsl

Frequency (Hzl

90

~

Bias
(Vdcl

4.05.0

'"

10

r-20

100

40

200

FREQUENCY (Hzl

FIGURE 1 - Quiescent State Minimum Impedance (1-10 Vrmsl
(EIA Standard RS-4701
140
Acceptable Region
120
(697,10011

e

100

u

w

80

2iw

60

~

40

~

z

0..

20
0

/v

/

/

(1633,1001

-~ange- I"
DTMF

1

1
Unacceptable Region

-(200,301

I
200

300

500

1000

'"

(3200,601

2000 3200

FREQUENCY (Hzl
FIGURE 2 - Quiescent State Minimum Impedance (0-3 Vrmsl
(EIA Standard RS-4701

MOTOROLA COMMUNICATIONS DEVICE DATA

CIRCUIT DESCRIPTION - MC34012
A block diagram is shown in Figure 3 (R1-R3, C1-C4,
and the piezo transducer are external). A ringing signal
(From Table 2) is applied to the Tip and Ring terminals,
and the current is rectifed by the full wave bridge. The
string of six diodes following the bridge provide the
high impedance required at low voltage (non-ringing)
levels (see Figures 1 & 2). When the voltage across
AC1-AC2 exceeds approximately 5.6 volts (8 diode
drops) current will flow (several microamps), primarily
through R3 and into the Bias Circuit block (Ia is
relatively small). As the current reaches approximately
0.5 mA, the internal biasing becomes well established,
and so further increases in voltage result in little
increase in current. When the voltage at pin RI reaches
22 volts, the zener diode conducts and the current
increases rapidly with voltage.
The two inputs of the comparator are referenced to
pin Rs (the output of the diodes), rather than to ground.
The inverting input is kept at 1.5 volts below Rs by la,
R a , and Da. The voltage at the non-inverting input
depends on the current through R3. When the voltage
at this input is more than 1.5 volts below Rs the output
of the comparator changes state, allowing the oscillator's signals to reach the piezo transducer. On-Off
hysteresis of the comparator is provided for in two
ways: 1) the comparator's output (when low) reduces
the value ofIa, thus reducing the voltage across D a and
Ra to 1.2 volts; and 2) The load current (ILl passes
through R3, increasing the voltage across it. When the
current through R3 is reduced sufficiently to turn off
the comparator, Ia is returned to the higher value, and
the flip-flop is reset, turning off the output.
Capacitor C3 filters the waveform across R3 so that
the comparator does not turn on & off with every cycle
of the applied ringing signal. In effect, the comparator
responds to the AVERAGE voltage across R3. C3 also
filters out transient voltages and noise to prevent false
ringing. C3 should be large enough (typically 1.0 JLF) to
reject dialing transients, as well as to ensure the
comparator stays on at the lowest ringing voltage and
frequency listed in Table 2 (40 Vrms , 15.3 Hz). Values
larger than 3.0 JLF will significantly affect the response
time of the circuit.
C4 is a filter for the internal 22 volt supply. With a
5.0 JLF capacitor, a ripple of about 3 volts p-p (at15.3 Hz)
results at theRI pin, which shows up on the output pin.
With a 2.0 JLF capacitor, the ripple increases to 6 volts
p-p, with a slight reduction in output sound level of the
piezo transducer, since the output's average value is
lowered. Valuesless than 2.0 JLF are not recommended.
Neither C3 nor C4 affect the impedance of the overall
circuit during ringing.
The values of C3 and R3 determine the turn-on trip
point of the circuit, while the turn-off trip point is
determined by R3, C3, and the load (piezo transducer)
since the load current (ILl passes through R3. (The line
input resistor and capacitor, R1 and C1, also affect the
on-off trip points, and will be discussed later). 1800
ohms is the recommended value for R3_ A higher value
will lower the trip points, but will make the circuit more
susceptible to noise. Additionally, ifR3 is too large, it is
possible the comparator may turn oli the output before
the internal circuitry is fully biased, resulting in erratic
operation. R3 must therefore be selected to pass sufficient current to supply the bias current, AND some
AN937

4-59

through the 22 volt zener diode, BEFORE the comparator switches the output on_ On the other hand, a lower
value of R3 will increase the circuit's noise rejection,
while raising the on-off trip voltages_

C1

Components R2 and C2 set the base frequency of the
oscillator, and have no effect on the on-off trip points,
or circuit impedance. Refer to the data sheet for proper
component values_

r-----------------------,
I
I
AC1 I
-!...
I Rs(6)

~(2)
/
InputVAC
\

I
(3) I ':"

C2

- Numbers in parentheses
are pin numbers.

FIGURE 3 - MC34012 Block Diagram

CIRCUIT DESCRIPTION - MC34017
A block diagram is shown in Figure 4_ The external
components are labeled the same as in Figure 3_ The
following provides a functional comparison of the
MC34017 with that of the MC34012:
- The output to the piezo transducer is a pushpull configuration, rather than single ended,
providing 40 volts p-p_
- The comparator~s inputs are referenced to
ground rather than to the supply voltage_ V r is
1.2 volts when the comparator's output is off
(low), and 0_9 volts when the output is on.
- The configuration consisting of the comparator, R3,· and C3 sense the incoming current
(Is) to determine the turn-on and turn-off trip
points. Since Is contains the load current (10,
the same hysteresis effect that exists in the
MC34012 is provided for in this circuit.
- Five diodes are shown in series with the input
bridge rather than six. The Current Mirror
block provides an effective sixth diode, providing the same high impedance at low voltage as
provided for by the MC34012.
- Typical values for R3 and C3 are 15 kohms
and 2.2 I'F, respectively.
AN937
4-60

MC34012/34017
IMPEDANCE CHARACTERISTICS
The circuit of Figure 5 was used to determine the dc
characteristics, and the results are shown in Figure 6.
The component values (R2, R3, C2-C4) are typical
recommended values, and the 0.047 I'F capacitor and
390 ohms resistor simulate a typical piezo transducer.
The circuit is obviously very non-linear, resembling, in
effect, a 29 volt zener diode in series with a 450 ohm
resistor (for Yin > 29 volts).

QUIESCENT STATE IMPEDANCE
The very high dc impedance requirements, and the
fairly high ac impedance requirements (particularly at
the lowest frequencies) of Table I, require the use of a
capacitor in series with the input to the Ic. A series
resistor is not practical because of the values involved.
Figure 7 depicts the circuit configuration. The maximum capacitor value (for Cl), which results in the
circuit exceeding the EIA requirements, was experimentally determined. Figures 8 & 9 indicate the
impedance curves of the resulting circuit. Figure 8
shows the results at 10 Vrms only since any lower input
voltage results in a higher circuit impedance.
Typically, mylar, polycarbonate, and Teflon capacitors are best suited to meet the dc impedance
requirements.
MOTOROLA COMMUNICATIONS DEVICE DATA

R1

/
Input VAC
\

r-----------------------.,
I
I

C1

D--'WI--l

(1)
AC1 I
I

2-

I R114)

(8) I-=-

I Ro 2(3)
-

I

---------j[Rga)----------~
-

Numbers in parentheses
are pin numbers.

FIGURE 4 - MC34017 Block Diagram

,...------,

DC
Power

i 0.047

+

Supply -

2

4

390

: Load

IL ______ ...lI

1-------1

1.0 "F

DC
Power

Supply

+
-

1-------1 8
5

C2
1000pF

2.2"F
FIGURE 5 - DC Test Circuit

MOTOROLA COMMUNICATIONS DEVICE DATA

AN937
4-61

DCR (ohms)

10k
40
35

'"
!:l

.....

V
i'

Dutput
Switched Dn

25

'"
~

20

'"'

15

1) 7200 ohms is the maximum value which will
allow the circuit to tum on at 40 Vrms , 15.3 Hz.
2) 7800 ohms is the maximum value which will
allow the circuit to turn on at 40 Vrms, 17 Hz.
3) 2000 ohms is the minimum value which will
result in a REN of 1.0 for a type A ringer.
4) 5500 ohms is the minimum value which will
result in a REN of 1.0 for a type Bringer.
5) WithR1 chosen within the abovementioned
range of values, the highest measured circuit
impedance was approximately 23 kohms, well
below the maximum allowable of 40 kohms.
Choosing a value of 6200 or 6800 ohms (2
watts) for R1 will then result in a circuit which
is functional at all of the voltages and frequencies listed in Table 2, but also provides a
REN of less than 1.0 for both type A and B
ringers.

10M

..-

""'I"-

30

~

1 DM

lDD k

10k

:>

lin

I(

10

5.0

f-

D.01

DIC~

~
0.1

11

1.0

lD

100

lin (rnA)

FIGURE 6 - DC Characteristics

RINGING STATE
Considering (temporarily) the impedance values of
Table 2 as minimums in order to guarantee aREN of1.0
or less, reasoning will indicate that the circuit ofFigure
7 will not provide the necessary impedance since: 1) the
impedance of the ringer Ic drops off quickly at the
higher voltages (Figure 6); and 2) the impedance ofthe
capacitor (C1) drops off at the higher frequencies. (The
capacitor's impedance can be roughly estimated using
1/2rrfC, but this is a VERY rough estimate since the
current through the capacitor is anything but sinusodia!.) A series resistor (R1) is therefore added (Figure
10) to provide the additional impedance. The limits on
the value ofR1 are that it must be low enough to allow
the circuit to operate (output on) at the lowest voltage
AND frequency of Table 2, and yet high enough to
provide sufficient impedance at the highest voltage
AND frequency. Since an optimum value for R1 is
difficult to calculate, different values were tested experi·
mentally with the following results:

The allowable values for C1 are fairly narrow.
Reducing C1 will increase the circuit impedance and
lower the REN, but testing indicated that 0.61'F is the
lowest value which will allow the circuit to turn on at 40
Vrms and 17Hz. It was previously determined (see
Figure 8) that C1' s value could not be much higher than
1.0l'F and still meet the quiescent state impedance
requirements. The voltage rating for C1 must be at
least 250 volts, and must be non·polarized.
The load (represented in Figure 10 by the 0.0471'F
capacitor and the 390 ohm resistor) affects the overall
circuit impedance when ringing since the load current
must be supplied on the Tip and Ring lines, and so the
actual sound transducer must be installed when
making the impedance measurements of a production
circuit.
Variations in performance over temperature (-20° C
to +60°C) are minor, and generally do not present a
problem in most applications. Variations inR1, C1, R3,
and C3 will affect input impedance, and the on-off trip
points, if they drift with temperature.
0.047 390

Signal
Generator

390
Signal
Generator

C2
Note: Cl is Non·polarized

FIGURE 7

AN937
4-62

MOTOROLA COMMUNICATIONS DEVICE DATA

lOOk

10M

-....;:::

~

:-........

"
l-

1.0 k

"-

M~34012

r-<:::::
1.0 M

ie.
~

u

z

«
c

Requirements

~

II
S.O

10

MC34D12

~

J'

Rs - 470 Minimum k-!'

I-

MC34017

S.OM

MC34D17

L

20

SO

100

200

OTMF
Range

'"

-l

100 k

400

FREQUENCY IHzl
R, - 470 Minimum

/'

_1~'1uir~ments

FIGURE 8 - AC Impedance at 10 Vrms
10 k
100

II ill

200

SOD

2.0 k

1.0 k
FREOUENCY

S.O k

10 k

IHzl

FIGURE 9 - AC Impedance at 3.0 Vrms

0.047

1---'lN'<---H---i 2

.------------'---1 3

390

4
MC34012 81----_._---,

C2

High
Voltage
Amplifier

1000pF

1.0,.F

1800

390

2

.---------'----18

MC34017 3
61---~---,

5

High
Voltage
Amplifier

C2
1000 pF

2.2,.F
Note: Cl is Non-polarized

FIGURE 10 - Ringing State Test Circuits

MOTOROLA COMMUNICATIONS DEVICE DATA

AN937
4-63

SUMMARY
The MC34012 and MC34017 provide a simple and
inexpensive means to construct a telephone ringer
which meets the FCC and EIA impedance and operational requirements. The output frequencies to the
sound transducer are selectable over a 6.5:1 range, and
three different warble rates are available by appropriate suffix choice (-I, -2, or -3). The circuits are
designed for use with piezo sound transducers, rather
than a bulky speaker/transformer arrangement. Only
3 resistors and 4 capacitors (all standard values) are
required to make the circuit operational
A REN ofl.O is easily obtained for a type B ringer, as
is a REN of 0.5 for a type A ringer.

ACKNOWLEDGEMENT
Figures 1 and 2 were taken from RS Standard 470
with permission of the Electronic Industries Association, 2001 Eye St. NW, Washington, DC 20006.
(202-457-4900).

BIBLIOGRAPHY
Electronic Industries Standard RS-470, "Telephone
Instruments With Loop Signaling For Voiceband
Applications", (Issue I), January 1981.
Federal Communications Commission Rules andRegulations, Part 68 "Connection ofTerminal Equipment
to the Telephone Network", October 1982.
MC34012 Data Sheet, Motorola Inc., 1983.
MC34017 Data Sheet, Motorola Inc., 1984.

AN937

4-64

DEFINITION OF TERMS
RINGER CIRCUIT The bell, or other alerting device (circuit) in a
telephone.
ON-HOOKThe circuit condition of a telephone when it is not
in use (handset is on-hook).
OFF-HOOKThe circuit condition of a ,telephone when it is in
use (handset is off-hook).
DTMFDual Tone MultiFrequency - The dialing system
where (somewhat musical) tones are produced by a
pushbutton telephone.
RENRinger Equivalence Number - see text.

TIP, RlNGThe connection points whereby an individual telephone is connected to a switching network. Ring is
traditionally negative with respect to Tip.
TURN-ON TRIP POINT The voltage (at Tip & Ring) at which the ringer
circuit switches on.
TURN-OFF TRIP POINT The voltage (at Tip & Ring) at which the ringer
circuit switches off.

MOTOROLA COMMUNICATIONS DEVICE DATA

MOTOROLA

-

SEMICONDUCTOR
APPLICATION NOTE

AN940
Application Note

TELEPHONE DIALING TECHNIQUES
USING THE MC680S
Prepared by
Robert Fischer
Downsview, Ontario, Canada

INTRODUCTION
Telephones and associated ancillary equipment providing
intelligent features are fast becoming commonplace. Often,
it is necessary for the microprocessor providing the intelligence to also dial a telephone number.
The M6805 Family microcomputers (MCV) , with their
proven hardware/software versatility, are ideal candidates
for such applications. Illustrated here are two cost-effective
methods of telephone dialing. Hardware and software is
given for both Dual Tone Multi-Frequence (DTMF) and
rotary-pulse type dialing.
DEMONSTRATION BOARD DESCRIPTION
Figure 1 shows the schematic of the demonstration board
designed around a MC68705P3 single-chip MCV. This board
is capable of pulse or DTMF dialing. The type of dialing is
selected by switch S 1. A 12-contact keyboard is used for
input. While this is an extravagant use of I/O, it is acceptable
for the purposes of a demonstration board.
Pulse dialing requires a direct connection to the telephone
line. Interface to the line is made by a 600-ohm, 1: 1 line
transformer and a relay that provides on/off hook capability. An indicator light (LED #1) shows the current hook
status.
After a power-on reset, the board is in an on-hook state
(LED #1 off). The pressing of any key will result in an offhook state without the digit being dialed. Subsequent key
presses will result in the dialing of the corresponding digit.
Pressing of the cancel button (S2) returns the board to the
on-hook state.
The hardware and software to accomplish either form of
dialing is readily applicable to any number of the M6805
Family.
ROTARY PULSE DIALING
From both a hardware and software viewpoint, pulse dialing is by far the simplest form of dialing to implement.
Pulse dialing requires that the telephone line circuit receive
a make/break sequence at a 100pulse-per-second (PPS) rate
(see Figure 2). The dialing of the digit 3, for example, requires three make/break sequences. The lO-PPS rate requires the use of either a transistor or high speed relay for
line looping. Note that if a low current reed relay is used,
port B may be capable of driving the relay directly
(eliminating the 2N3904 driver).
MOTOROLA COMMUNICATIONS DEVICE DATA

Subroutine PDIAL provides the proper timing sequences
for pulse dialing. The routine is called with the digit to be
dialed resident in the accumulator. Because the timing is not
particularly critical, interrupts that can be quickly serviced
are permissible.
DTMF DIALING
Dual tone multi-frequency tone dialing is considerably
more complex in terms of ROM usage and external hardware. The M6805 MCV is required to generate two
simultaneous sine waves of different frequencies. Table 1
shows the key pad digit and the frequencies of the corresponding tone pairs. Note that the tones fall into two groups:
Group

Frequency (Hz)
697, 770, 852, 941
1209, 1336, 1477, 1633

Low Tones
High Tones

TABLE 1 -

Keypad Digit and Frequencies for Tone Pairs

Keypad Digit

DTONE Entry

0
1
2
3
4
5

$0
$1
$2
$3
$4
$5
$6
$7
$8
$9
$A
$8
$C
$D
$E
$F

6
7
8
9
A
8
C
D

*
#

Tone Pair (Hz)
941
697
697
697
770
770
770
852
852
852
697
770
852
941
941
941

1336
1209
1336
1477
1209
1336
1477
1209
1336
1477
1633
1633
1633
1633
1209
1477

Also note that if the seldom used keys A, B, C, and D are not
required, it is not necessary to generate a 1633-Hz tone.
The method used to generate the tones uses a series of 3-bit
look-up tables. Consider a sine wave that has been sampled

AN940

4-65

t~

QlCO

=
0.1 k

1
Sl

=

INT
VCC

PA7

EXTAL

PA6

XTAL

PA5

Vpp

PA4

TIMER

PA3

PCO

PA2

~4.~'k I PCl

PAB

"I"

Open=DTMF Dialing
Closed = Pulse Dialing

I

RESET

VSS

+5V

8

~

"'=

1I

4.7 k

S2-L
0

0

Cancel
+5V
240 k

.@L!:.
60k

PAl

PC2

PB7

PC3

PB6

PBO

PB5

PBl

PB4

PB2

PB3

I

12x4.7 k

MC6B705P3

30k
4x4.7 k

A, B, C= 14 LM324
Low Pass Filter

Hi Pass Filter

~ II~
RXTestPoint

!i:

+lI'F. 470

~

el

>
~
!i:

=

=

10k

=

1:1

150

~ ~iP
I

+5V

LED 1
(Hook Statusl

+5V

c

z

Reed
Relay

o
~

az
en

c
~

o

m

c
~
>

Ring

+5V

=
FIGURE 1 - Demonstration Board Schematic

2Nl6004

at a constant interval, starting at the positive peak (see
Figure 3). Sampling is continued until the next positive peak
is encountered. There is, of course, some quantization error
associated with this next found peak. If this group of samples
were to be continuously cycled, a frequency error would
result.

1 Pulse

Digit Dialed = 3

FIGURE 2 - Timing for Rotary Pulse Dialing

To cure this, continue sampling until the next peak is encountered and determine if the resultant frequency error falls
within acceptable limits. Figure 3 is actually the output of a
program written in BASIC for the EXORciser. This listing is
included at the end of this application note. This program is
used to design the look-up table for incorporation into the
M6805 program according to the error rates acceptable in the
end equipment.
This program prompts the user for the sample interval and
the frequency of the tone which is to be generated. Sampling
of the tone is thus automated and after a peak is encountered, the cumulative frequency error is calculated and
displayed along with the sample count. If the user is satisfied
with the percentage error, a table of the samples is generated.
If the error is still unacceptable, the program continues
sampling until the next peak is encountered. Note that the
samples have all been "dc shifted".
This program was used to generate the look-up tables for
all the tones given in Table 1 with a criteria of 1% maximum
frequency error.
The subroutine OTONE actually operates on these tables
to generate the OTMF tone pairs. The routine is entered with

the OTMF digit (see Table 1) is resident in the accumulator.
Note that interrupts cannot be tolerated by this routine.
The first task of this routine is to convert the digit into the
table start addresses for the high and low tones. This routine
requires that the tables be resident in page 0 ROM to allow
use of indexed addressing with 0 offset. The structure chosen
for the tables puts the high group tones in the right nibble
and the low group tones in the left nibble. Because the tables
are all of different lengths, the table end is marked by an entry of $F. In defiance of Murphy's Law, the OTMF tables fit
exactly into page 0 ROM.
Generation of the tones involves cycling around a loop
which plucks a 3-bit low tone sample and adds it to the 3-bit
high tone sample. The 4-bit sum is then output to a 01 A converter. If the end of the table marker is encountered for
either sample, the pointer must be reset to the table start.
This loop also keeps track of the duration of the tone burst
by counting loops in TIMEH and TIMEL.
Notice that every program path through the loop takes a
constant time (122 microseconds). The actual sequence of
program development was to first write the loop, determine
the execution time, and then, with the sample interval defined, generate the tone tables.
The 4-bit 01 A converter is economically implemented with
standard 5% resistors (60 kilohms =30 kilohms + 30
kilohms). Port B was used because of its slightly superior
high output voltage drive. It is still necessary to supplement
the high drive with pull-up resistors.
One unfortunate by-product of this tone generation technique is the production of subharmonics (and, of course,
harmonics). This necessitates the use of an active bandpass
filter. This filter consists of separate high pass and low pass
sections. The filter response is shown in Figure 4.
The output level to the telephone line is adjusted with a
470-0hm resistor in series with the line transformer primary.
This also provides the RX point, where received audio can be
obtained for duplex communication.
Using the BASIC software at the end of this application
note, the generation of custom tone groups is readily accomplished. Single tone generation is also possible by using
the table entry TNOFF at the end of the given OTMF tables.
This allows the muting of either the high or low
group tones.

EXORciser is a registered trademark of Motorola Inc.

MOTOROLA COMMUNICATIONS DEVICE DATA

AN940
4-67

7 :*'
6
5

*'

*'

4
3
2
1

*'

121, :

*'*'

*'
*'

*'

*'

*'
*'

*'

*'

*' *'
*'*

*'*'

*'*'

*'
*'

*'

*'
*'

*'

*'

*'

: : : : : : : : : ,: : : : : : : : : : : : : : : : : : : : **'
:: :: :::: :: :::: : : : :::: :

FREQUENCY
ERROR
NO. SAMPLES
NO. CYCLES
SAMPLE 1
SAMPLE 3
SAMPLE 5
SAMPLE 7
SAMPLE 9
SAMPLE 11
SAMPLE 13
SAMPLE 15
SAMPLE 17
SAMPLE 19
SAMPLE 21
SAMPLE 23
SAMPLE 25
SAMPLE 27
SAMPLE 29
SAMPLE 31
SAMPLE 33
SAMPLE 35

HORIZONTAL
Hz

= 122.~~~

uSEC

697.~121~
~.8121~
35.~11l121
3.~~121

"

SAMPLE 2
SAMPLE 4
SAMPLE 6
SAMPLE 8
SAMPLE 1~
SAMPLE 12
SAMPLE 14
SAMPLE 16
SAMPLE 18
SAMPLE 2~
SAMPLE 22
SAMPLE 24
. SAMPLE 26
SAMPLE 28
SAMPLE 3121
SAMPLE 32
SAMPLE 34

7

3.
121
1
4
7
6
3
~

1
4
7
6
3
121
1
5
7

FIGURE 3

-

5
2
121
2

=6

7
5
1
~

2
6
7
4
1
~

3
6

Sine Wave Sampling

+2
0

;'

..........

-2
-4
-6

iIi
~

illc

-8

-12

ill
a:

-14

CJ.

-16
-18

'\.
'\.

I

-10

0

I,

I
Low Tone Group
High Tone Group

\

I
I
I

"
~

\

I

-20

l~

-22
-24

\

-26
100

1000

10,000

Frequency IHzl
FIGURE 4 - Cumulative High-Pass, Low-Pass, and line Transformer Response
AN940
4-68

MOTOROLA COMMUNICATIONS DEVICE DATA

"AGE

t1I01

• SA::.

DEt"O

- MC6871215P3 SOURCe: FOR DIALER DE!"IO

DEMO

DEMO
_. I":C687t!15P3 SOURCE FOR
ABS,ORE

l1lIZI!Zlt'lJ.

001111212
fIII1lli11213

2101211215
12I1i112l11l6
012)1211217
12l12l11l12l8
012)12l1219

***:**:t:***************~:~r:***************;"'~:.-t:****

012l12l11
11l12111l12
121011113

17.111117.11.5
11I12l016
111121121::'7
12112l11l18r-l l?J784
12111112119~~ 111784

*'
*'
*'
5F

SET I"IOR

R

012)12121
0012122

*'
*'

i1l7J11l25
012112126
0(2)12127
00028
0121029
11)(1!030
1110031

flll2l00
I2l~GL

121'502
t!l12i04
001215

011l11l6
11l011l8
11lf2!1ZI9

r.J~fZ)32

ORO
FCB

$784
1.11)112111;, il.

PORT OEFI:-i-:**************

I1II1II2l 1 III

01Z11ilt.~lA

D~RL.ER

MOTOROLA COMMUNICATIONS DEVICE DATA

RMB
RMB
RMS
"MEl

'~EG

):S-i":::R

$£~(/l

·...{j:\.E

1.

,
1
:(

TIl"iE (riS)

TONE ;IME (LS)

:"iI TOi\:E TA8,_,'O S-··ART
LO TON::: TABLE S,AR"f
hI TO,,"E CLRR:;::I\'-,- PDINT~R
LO TONE: CU,!QEN7 POIyr:::q
-:'Ei"IPORARY SCRATC~!
LRST DIALED DIGIT USED

AN940
4-69

PAGE

01212

• SA: 1

DEMO

1il1Zl12l47
0012148
01Z11Zl49
000512lA 12l101Z1
1Zl0051
00052
eilZl1Zl53
11I00511·
01Zl12l55A Q) 1 (21(11 3F 0!2!
00056A ~102 3F 01

DEl"lO

- MC68705P3 SOURCE FOR

MAIN

*'

RO~

>I<

ORG

$11Z10

COL.D START.
INITIALIZE PORTS.

*'
A START
A

CLR
CLR
CU~

:"ORi"A
PORTB
PORTe
",1-000011 11

010£1· 3F "2

A

012!058A
00059A
012l060A
00fl16H\
2l0!2l62
1210063
(ZIIZl064
00065A
00fl166A
00067
01Zl1Z168A
01Z1069A
0012l70A
0(2)(1171
1Zl!211il72
11I1Z1073
(1l!1!1Zl74
11I12l075

0106
0108
010A
0i0C

0F

A

:"DA

1215

A

8TA

;:>O~TBD

04
06

A
A

LOA

.,1-01110011)1 00
;:>OR",CD
SST

010E CD 0185
25 1117

0111

DEMO

>I<

(2]~m57A

A6
B7
A6
B7

DXA~ER

STA

*' CHECK fAG1::

003

• SA: 1

DEt'iO

DEl"IO

1ZI1ZI12I94
0121095
12112!12196
1Z11ZI1ZI97
012!12198

*'*'***'***'*'**'*'*'*'*'**'*'**'*'*'*''''****''''*'****'*'*'*'*'**'*'
*'
*'
SUBROUTINES
*'
*

*

*

*'*'*'**'**************'**'*************'*'*'*'**"'''

00100
1110101
01Zl102
00::'1ZI3

*'
*'

WAITi"'lS
WAITS THE NUMBER OF mSECS GIVEI\, r.:-.: ACC.
BOTh ACC AND X ARE DESTROYED.

*

*'
*'

!2I010t~

1Z1132 AE 7C
IZIIZli06A 121134 5A
01Z1107A 12)135 26 :=D
111121:08A 0137 4A
1Z1IZI109A 0).38 26 F8
1110110A 013A 81
0011215~;

00112
i1IIZl113
0121114
01Zl115
00116
01Zl117
1Z10118
0121119
(ll1ZlJ.20
ZI2I121A 12113B
iZlf211.22A 0:'.3D
0121:23A 013::
0012M,12I1'3F
1Z1I2I125A 121142
001261=1 0144
1Z1I2I127A 0146
001281=1 0149
IZ1I2Ii29A 12114B
00130
00131

- MC68705P3 SOURCE =0" DIALER DEl"iO

A4
97
58
D6
B7
B7
06
B7
B7

0F
0l.95
42
44
0196
43
45

A6 <=D

0121:'.34A 0:i.4= B7 1':0
!?l!Zi:.35A 121151 A6 'EC
1Z112I~.36A 0153 B7 41
01i.')137
0121138
1ZI\2!:39
00140
012l14:l A 0155 3C 41
00j.4:2A 0157 26 08
!2I121143A 0159 3C 40
IIlIZl:l44A 015B 26 07

A WAITMS LDX
WAITl DECX
ENE
0134
DECA
ENE
1Z1132
RiS

\*124
WAITi
~JArr!'",S

*'
DTO"iE
*'
GEt-ERATES :2 TONE BURS'- 0;= 65 MSEC
*'
FO:"'LOWED BY A FORCED 25 MSEC S):LEr.· T
*'
PERIOD FOR DTMF DIALr~G.
*'
DTMF DrGIT ($I2I-$F) IS GIVEN IN ACC.
*'
*'
INTERRUPTS t'iUST BE MASKED BEFORE ENTRY.
*'
*
A DYONE AND
TAX
LSLX
LDA

A
A
A
A
A
A

A
A
A
A

S~A

SiA
LDA
STA
STA

*'*'
*'

LDA
STA
:"DA
STA

'"

A TDNEL? II\IC

A

121164 CONT

i1!17.l1!. ?

MOTOROLA COMMUNICATIONS DEVICE DATA

*'

*'

:"0 TONE S-~A'I7 POII'!T,::R
LO TON:::: CURRSNT PO!NTER

~$FD

TIMEH

MS

*~$EC

TIMEL

LS

TONE GENERATION ~OOP.
CONSTANT LOOP TIME OF

0161

<'HZ! :~45

HI TONE START POINTER
HI TONE CURRENT POIi\;TER

SET TO\iE TI ME COUNTER

*'
*'
*'

00:46

TTAB,X
STARTH
iONC::H
TTAB+l,X
STARTL
TONEL

AL~

BNE
INC
BNE

~22

uSECS.

TIMEL
NCARRY
TIMEH
GETLO

DO~::

'"

AN940
4-71

P~GE

11I1Zl4

DEMO

111111 148A 111150 A5 19
f1I121149A 01.5F 2111 D1.

A
121132

I1If1I15\Z!
0015j.A
~(!lJ.52A

f1I0153
111111154
f1I121155
01O:56A
i2li2l157A
f1Il1l:i.58
12)121159
0121100A
0111 161A
11l11l162A
f1I0J.6:5P'

0161- 90
0162 20 F7

*'NCARRY
121158

*'
*'
0~5l~ BE 45
111166 F6

01.67
0169
01.6A
0:6B

28 04
9D
90
20 1113

*'

111160

*'
*'

iZ!~1l93

0f11~96A 0~86 BE 42
1Zl0:;'97A 0188 F6
00198
0121199A 0189 5C
0~12111111A 018A BF iJ.4
00201.
i?lilJ211l2
00203
00204A (2)18C BS 46
00205

AN940
4-72

j*25
WArn'IS

I\:OP
BRA

CONT

NO CA,HY- BURN 6 uSECS

LOX
TONEL
,X
LOA
LO ""ONES ARE IN LEFT
SEE IF TABLE ENO 01S
GETNL.O
BM:
NOP
NOP
BRA
SHFLO

LO TO~IE CURRENT POINTER
GET ByTE
NIBBLE
BIT =1)
FILL FOR COI\;STANT TIME

TABLE END- RESET TO TABLE START
LOX
LOA

STARTL
,X

*'
*' SWAP NIBBLES
*'
ShFL.O
LSRA

A

*'
*'

A

*'

0~:L8~;

0eJ!.94
2)f1I195

LOA
BRA

GET LO TONE

A *'GETNL.O

11!1?l169

00184.A 0179 B::: 44
0121::.8$\ !1lHa F5
f1Iii118<;
QHIJ:!.87A iiH7C All· 0F
00188A lZli7E A;. i21F
0~JJ.89A 0181Zi 27 1214
0~1.91ZiA 0182 9D
Zll11i.9j. i::; (Z!183 90
00192~l 0i84 20 03

*'
*'

f1I ,. 7111

~e)165

111111170
0111171.
11l11l172A 11117111 44
IIll1lj.T$A 0~.71 44
11I12I:,.74A 111172 44
f1If1I~75A 0173 44
I1IIiH76
f1Iii'l:l77A 0174 B7 45
I.lli0 ,t'

K::Y

f<:::VS

PORTA

GST

GOT'<:'::V

KEV C,_OGED?

:t\iCA

I2IF 01 I2IF 1211;:3
4C
IIlD 1211 IIlB (2)lF3
A6 0 c
A
0B 01 06 lIllF3
4C
09 01 02 1Il1F3

~0:~:10A 12l1Fl. 98
i1llll3i ~A 0~.F2 81
00312
el03::::::
11l1Zl3:4
11I11l315A 12I1F3 99

AN940
4-74

l~7

DE~'O

*$P

LOA
.TSR

~·\EY42

27 FA

DIf.h_ER

~I·XE

F::RST

P

*'

FO~

i..Sn<;::v

L.DA
C!YIP
8EQ

A
01D6
linCE

98
81

SOURCE

~:C68711l5P3

NO f<:EV .:lRESSED.
):F FI~S'" TIi"IE, WAIT OUT DSBO'J;-':CE.

0iCC

~;.:

01C8
2l:d273 A \IllCR
11l1'l27M~ 01CC
iZ'0275(.1 01CD
00275
11l17.l2T7
00278
111(2)279
11l11l280A I2I1CE
fIllZ);;:81.A 1211. Dill
0~282A (21).02
'l0283A 01D4
el028M) 0105

12!121285
00287
eliZl288
1210289
il0290
1110291
11I0292A
00293A
1110294A
00295A
00295A
00297A

'*
*
*'

A

~0271
12!0272(:~

-

DEi"iO

• SA: 1

~O

C;vP
;;'S
lo::nc

j-f.Sl
l-.jqITMS

*'

WAITMS
SCRTC,",
PDIA,-2
BNE
WAI," 212!12l MSEC INTER-DIGIT
#2121121
LDA
JMP
WAITMS

AN940
4-75

PAGE

12l1Zl8

.SA:).

DE!"IO

DEMO

00341
0121342
00343

12l0345A
00346A
11l0347A
00348A
00349A
01lJ:550A
00351A
1Z112l352A
Ztl):353A

lZIeJ354A
2l0355A
0lin56A
fi10:S57 A
012l358A
2!!ll359A
'111lJ360A
1/i0361 A
!2l0362A
00363A
Ii3Ii.n64A
iileJ365A
!2l0~;66A

,ll1ZrS67 A
1Z)0358A
01ZJ:::69A
!2lLl):S70A
02l371A
00372A
12l0373A
12lf1l374A
!2]1ZJ375A
1Zl0376A
0fzr377A
0IZ):578A
0!ll379A
1Z117.l381Z1A
00381A
01i.'r582A
QHll.383A
00384A
1Il0385A
eJIZ)386A
021387A
00388A
12l12l389A
012l390A
2I0391A
012l392A
QlfZl393A
00394A
1Il0395A
00396A

AN940
4-76

*'

*'
*'
0080
0080
0081
0082
0083
0084
0eJ85
0086
0087
0088
0089
008A
008B
008C
01Z)8D
QU218E
008F
0090
0091
0092
1m'l93
0094
0095
0096
0097
0098
0099
009A
009B
009C
009D
009:::
01Zl9F
00A0
17.l0Al
00A2
00A3
00A4
01ZlA5
00A6
1Zl0A7
00A8
f2J0A9
00AA
I2II2IAB
1210AC
I2lI2lAD
1210AE
1Zl0AF
12l0BI2I
!Z)IZ)B1
00B2

77
76
53

3eJ
21
03
06
17
25
4·~
~.

60
71
74
67
57
34
H
~0

02
15
27
46
54

n

70
52
45
3F

17
05
02
lIZ)
31
55
67
F5
72

60
51
34
17
1216
1213
2121
41
54
77
76
63
40
20

-

t':C68705P3 SOURC::: FOR DIALER DE"'O

TOUCH TO!\:E GENC:RATOR TABLE

A TI\!697
A
A

ORG
FCB
FCB
FCB

A

~"'CB

A
A
A

FCB
FCB
FCB
A
FeB
A
FCB
A
F'CB
FCB
A
A
rCB
A
""CB
A
FeB
A
FCB
A
FeB
FeB
A
A
FeB
(4
FCB
A
FCB
A
FeB
FeB
A
FeB
A
FeB
A
FeB
A
A
FeB
A
FeB
A
FeB
A TN1335 FeB
A
FeB
A
FeB
A
FeB
FCB
A
A
FCB
FeB
A
A
FCB
A TN770 FCB
A
FCB
A
FCB
A
FeB
A
FCB
FeB
A
A
FeB
A
FCB
FeB
A
A
FCB
A
FCB
A
FeB
A
FeB
A
FCB
A
FCB

$80
$77
$76
$53
$30
$21
$03
$05
$::7

$25

$42
$6f2l
$7:
$74
$67
$57
$34
$:tl
~;00

$02
$15
$27
$46
$54
$71

$70
$52
$45
.....

~·T;::
)
,

$17
$05
$02
$10
$3i.
$55
$67
$F5
$72
$50
$51
$34
$17
$06
$03
,.20
$41$54
$77
$76
$53
$40
$20

MOTOROLA COMMUNICATIONS DEVICE DATA

PAGE

0Q)9

J!2l397A Ii'lli'lB3
'lllZl 398 A ~J!1)Blt
'll'll~;99A 0085
fll2i411lZA i2ll'lB5
Ql!i'l401 A Ii'll2lB7
iill2l411l2A ~%.'lB8
12!!i'l4Ql3A 012199
Zli'llt04·A Ii'l!2lBA
Ii'll2ll.05A Ii'lI2lBB
(/}0lt11l5A iIl0BC
!i'l0(~12l7A 01i'lBD
~JQl408A "J0BE
I1lli'llt09A I2lI2lB'"
iIl(1Jlt10A I2l(1JC0
004:i.1A 00Cj.
Ql(l)4J.2A Cll2lC2
00lt13A IlJlZ)C3
i1U/14l4A !i'l0C4
00415A I2lQJC5
01l141.6(::,

~~Q)C5

'2l1Zl417A
1lI1ZlLL18A
01Zlt.t19A
00420A
210421 A
lleJ422A
0042314
iZi042M1
IZ1l2ll,25A

0ZC7
(2)0C8
012lC9
00CA
I2l!llCB
;1i1lCC
t<%lCD
12i0CE
i2l0CF
0!1lD0
0001
1i'l0D2
00D3
l10D4
11I>1D5
0iZlD5
00D7
2)0D8

~e142SA
00(~27A

Q')l21428P
121121429A
itJ0431ZlA
012llt31A
ZiZl432A
lZI!Zlt.:.33A
Q:iZJLL3ltR
iZI0lt35A 02)D9
iHZI 0 1. 09 0111:L~9 0111258 11033: 00334 00339

0080 ~t,,597
00R4 TN7711l
iZliZlC5 T!\852
m'lE3 T!\i941.

AN940
4·80

MOTOROLA COMMUNICATIONS DEVICE DATA

?AGE 001
~H00

0101
0102
IlL. 10
0J.20
0:;,21
12l,,22
0123
0:].24
0125
0J.25

01:;'21

TONCAL

.SA:l

T(00)
H=1,
P=122E-6
,C=0
W=f"*l.E5
PRINT IIPEF~IOD == .. ;W; iluSECS (Y/\!) 11 ~
Il\PUT A$
IF" (~$="Y" T'-iE:-" [3OTO ',30
IF A$ (> IIj\l1l THE!\! GO:-O :L2l
INPUT "PEfEOD (uSEC;::S)=", FJ
P=P'+'lE-5
PRIi\iT IITOh!E FREQ=II;
II\PU-c F
X=2*3.141593*F*P
FOR N=l TO 100
T(N)=:NTC3.5*CDS(N*X)+4)
GOSUB 8000
IF T(,,')(7 THE.·~ GDTD 370
REM GOT A CREST- CALCULATE CU~ULATIVE
DI~I

0140
0150
0150
0170
!ZJ :i. 71
CH90
0200
0220
Q==r\!*P
E= (C/F:'-Q) *100/Q
21230
0240 GOSUB 7000
~250 PRI~IT "ERROR

ERRO~

0270 PRINT nSRMPLE COU:\T=",N
~275 j:JRINT IIFR~QUENCY
=1I;l=;IIHzlI
0280 ?FlINT "CONTINUE (YIN)";
0290 I~:PU-:- (.:?j$
21::;00 IF f"$="Y" THEN GOTD 370
0311Z; IF (-1$ 0 "N" THEN GOTO 280

~32~

R~M

DONE- PRINT SAMPLE LIST

liJ::,30 GOSUB 9~l00
Q)::"·32 (30TO !. !,12l
(lfS7e: r"~::XT N
21:::.80 PRJ::\'T "SA.vIPLE COU~IT
03':';D '::I~D
7000 REM PLOT SUBROUTINE
7iZlIi:11"RINT CH;~$(27); "q"
7002 FOR I=~ TO 50
712l(21::) I\!",:n I
72(2)5 FJt~I ;\IT

:,00"

., "
7006 PRINT "
7010 FOR I = 1 TO 8
7020

_=8-1

70;:'2'1 PRINT

L~

II

i!!;

7040 REM PRINT THIS LINE
7050 FOR J=l TO N
7050 IF 7(J)=L THEN GO TO 7090
7070 ,"RINT "

";

7080 GO-:O 7i00
7tZl9Ql
7H'l0

NE':X~-

7110

i~RJ:i\iT

PF~I:\IT

1I:+:1I

1

J'

7120 I'I,EXT I
·7~.:;e;
:iRI\i"T
7~40 ~OR 1=1 TO 70
7:.5Ql PR~j\l: ":II~i
715(2) ,\IEXT :
7155
W=P*lE5
II

MOTOROLA COMMUNICATIONS DEVICE DATA

,

AN940
4-81

PelGS 0(7)2

TONCAl

• SA: 1

717(7)
71.80
7:,90
7200
8!ZH110
8010
8i1l2i1l
8030
8040
8050

HORIZO~~P~ =";W;"USEC"
i':'lIi'F ..
PRINT
PRINT
RETURN
I~Ei'" CREST COUNT ROUTINE- '-.00', FOR 1'1 ZERO CROSSr;"G
I", T(N) )3 -'-HE" GOTO 8040
H=0
RETURN
:::F H=0 ,HE\I C=C+:
1-1=1

(:;060

'~ETURN

9(7)(7)(7)
9011
9012
9(7) :'. :;';

REM PRIN~ER OUTPU~ SUBROUTINE
FOR J=l TO 4
PRINT *,,2
N:::xr J

9~22)

:~')R

I NT :1t.2

912)30 P::,INT ~i=21 II
904i1l ~OR 1=1 TO

• II

8

9fl.)50

L==8-I
PRI NT :!-1:2, L;II ~ II ~
9070 :=OR 3=1 TO N
9080 :'. F Tt: J) =L -:HEN
9090 .~ R I NT t~2," .. ~
~3Il!50

mr-o

9:'.10

9J.00 Go-,-e 9120
9;:.).0 P~:(1\iT ~*2jil*lI;
9).20 NEXT J'
9::.~3e:

prxI:\.;T

g\t.L~

l\l~XT

~).2

I

9~50PRINTtf27U

111

9160 FOR 1=1 TO 70
~J:i. 70 ?RIi\iT :f~2, ": ";
9 J. 8el NE::XT I
Si90
W=P*1E6
9:,',3:. DlG;:TS= :::
~~l92 PRr.t\'T l*2
9200 :'RI,\IT l*2, ..
921111 PRINT lQ
922111 PRINT #2
9230 PR I!\iT ~*2," FRt::QUE\:CY
~j24i1l PR;:NT #2, "ERROR
9250 "'RINT li'2, "NO. SAM"Li:S
926el P::xI:\lT ~*2, H!\!O. CYCLES
927111 PRINT 'Fi2
9271 DIGITS= i2l
928fZl !:3RINT :l:l:2
929111 FOR ';~l. TO N STEc.! 2
~r~::0Q)

?;~IN'r

~:j:2,I1SA~oL~

II;J;II

II; W;"

II

F;

II

E;H ':f..11

II

C

/I

uSEe II

HZII

II;-'-(J);

8=J"+1
932173 IF B) t-.: TL!EN GO""O '33/1.111
9:::;~5el PRINT ~~:::, II
SAtviPLE 11;8;11
934.111 i'Rlt\!T ,1*2
':B512l NEXT J
~)310

9370

AN940
4-82

11;-:-(8);

i,ETUI~N

MOTOROLA COMMUNICATIONS DEVICE DATA

_

MOTOROLA

SEMICONDUCTOR

APPLICATION NOTE

AN957

Interfacing The Speakerphone To The
MC34010/11/13 Speech Networks
Prepared by
Dennis Morgan
Bipolar Analog IC Division

INTRODUCTION
Interfacing the MC34018 speakerphone circuit to the
MC34010 series of telephone circuits is described in this
application note. The series includes the MC34010,
MC34011, MC34013, and the newer "A" version of each
of those. The interface is applicable to existing designs,
as well as to new designs.

FUNCTIONAL REQUIREMENTS
Figure 1 shows the basic MC34010 telephone circuit as
described in the data sheet. It is a completely functional
telephone meant for use with a handset, and provides
the additional function of a microprocessor interface for
the DTMF dialing function. The MC34011 does not have
the microprocessor interface, but otherwise is identical,
including the pin numbers. The MC34013 has the same
speech network, dialer, and line interface circuit as the
MC34010, but does not have the microprocessor interface
or the tone ringer. Except for a minor difference between
the speech networks of the "A" version parts and the
"non-A" parts, the interface to the speakerphone circuit
is virtually the same for all 6 parts.
Figure 2 shows the basic MC34018 speakerphone circuit as described in the data sheet. It is NOT a complete
telephone, but provides only the speakerphone functions.
It requires a speech network, such as the MC34010, to
transfer the speech signals tolfrom the Tip & Ring lines,
and to provide the required supply voltage. The four external connections - transmit output, receive input, dc
line input, and chip select - are the points which must
be interfaced to the speech network.
In the following text, only the MC34010 interface will
be described. The interface to the other parts is the same
except where noted.
When combining a speech network which operates a
handset, with a speakerphone circuit, certain changes are
required in the circuit operation when switching between
the handset mode and the speakerphone mode, and additionally when the dialing mode is in effect. The four
modes to be considered are: 1) using the handset for
speech, 2) using the speakerphone for speech, 3) dialing
in the handset mode, and 4) dialing in the speakerphone

MOTOROLA COMMUNICATIONS DEVICE DATA

mode. The requirements are summarized in the following
table:

Mode

MC34018

Vir

Handset
Mike

Handset-Speech
Spkrphone Speech
Handset-Dialing
Spkrphone Dialing

Unpowered
Powered
Unpowered
Powered

Low
High
Low
High

Live
Dead
Dead
Dead

Speakerphone
Mike

N/A
Live
N/A
Dead

Since the entire circuit is to be powered by the phone
line, the speakerphone circuit is powered up only when
it is to be used since it uses a portion of the loop current,
(a significant portion on long loops). The MC34010, however, must be powered all the time since it is the interface
to the phone line. The Vir voltage mentioned in the table
is the voltage across the resistor at the LR pin of the
MC34010, which sets the dc characteristics of the circuit.
By increasing that resistor, the dc supply voltage (and the
voltage at Tip & Ring) will be increased in the speakerphone modes, where additional power is required.
The handset mike is to be functional only in the handset-speech mode. If it were functional in the speakerphone-speech mode, system oscillations andlor additional echoes could occur. Disabling the microphone is
accomplished by activating the MM (Mike Mute) pin on
the MC34010. On the MC34010A, activating the MM pin
results in disabling the transmit amplifier, so in that case,
a transistor is added to the microphone circuit as the
means to disable it. In both dialing modes, muting is automatic whenever the dialer is activated, so the DTMF
tones are not distorted by sounds entering the
microphone.
The speakerphone mike is listed as NIA in the handset
modes since the MC34018 circuit is unpowered, effectively disabling the mike. In the speakerphone dialing
mode it must be non-functional for the same reason as
mentioned above. That is accomplished by the fact that
the MC34010 (and MC34010A) transmit amplifier is inoperative when its DTMF dialer is activated.

AN957

4-83

TIP
TO
TONE RINGER
CIRCUIT

C7

R5

CS

R7

R6
RECEIVER

RING

RXI

RM

RXO

RS

STA

a.6V
MT

V+
MIKE

T C12

Rla
Cll

r7

lC

TXO

C5
Rl2

MT

L-------¢MM
MT

Rl

a

#

C3

DIALER
LOGIC
&
DTMF
GENERATOR

MICROPROCESSOR
INTERFACE

...

MC340la TYPE
SPEECH NElWORK

KEYPAD

\ ••••• I

V-

!,P INTERFACE
MC340la{A) ONLY

Figure 1. Basic MC34010 Type Telephone

AN957

4·84

MOTOROLA COMMUNICATIONS DEVICE DATA

s:

@
:Il

o

~

o

o
s:
s:
c

TRANSMIT
OUTPUT

Vee

z

o
:!:i

o

z
en
o
m
<

om

::;o»

Figure 2. MC34018 Speakerphone Circuit

:I>
""'Z
.<0
0)(11
(11 .....

CIRCUIT DESCRIPTION

since 51 B is open, the MC3401S's CS pin (Chip Select) is
taken high through R33, disabling the IC.
Anytime the handset is on-hook, and S2 is on (both
poles closed), power is applied to both the MC34010 and
the MC3401S. Since SlB is closed, C5 is taken low, enabling the speakerphone circuit. Anytime the handset is
taken off-hook the circuit will revert back to the handset
mode.
The 1.0 Henry inductor isolates the speech signals at
Tip & Ring from the V + pin of the MC3401S, preventing
an oscillatory loop from forming. The diode bridge, B2,
is added for the tone ringer circuit of the MC34010(A), or
MC34011 (A), to keep the switches 51 and S2 from requiring 3 poles each.

SWITCHING ARRANGEMENT
Figure 3 indicates the switching arrangement for going
off-hook in either the handset mode or speakerphone
mode, and for switching between them. 51 (a two pole
switch) is the normal hook switch activated by lifting the
handset. S2 (a two pole switch) is a manually operated
switch which activates the speakerphone.
Whenever the handset is off-hook, and 52 is in the off
position, power from Tip & Ring is applied to the
MC34010 through the diode bridge and 51A. SlB's position is of no consequence in this mode. Should S2 be
switched on while the handset is off-hook, power is then
applied to the speakerphone IC through 52B. However,

TO
TONE RINGER
CIRCUIT
R5
r---'Vw-.... TO RECEIVE CIRCUIT

TlPo-+----~

V+

ZI
RING

-=

O-~----'

MC3401D,A
SERIES
SPEECH NElWORK

V-

-=

Note:
51 ~ Hookswitch
(Shown On·Hook)
52 ~ Speakerphone On/Off
Switch

R33
47k

MC34018

..........,.v:v.::r'-.....-t-----......-;V7":"i+ SPEAKERPHONE
-=

V-

-=

Figure 3. Handset/Speakerphone Power Switching

AN957

4-86

MOTOROLA COMMUNICATIONS DEVICE DATA

20
18
16

13
§;

HANDSET MODE . / , /

14

~ 12
ir

~ 10

SPEAKERJHONE

8/""

6/
./
y
4
20

MODE~

.&---;."/
/'

4D

60

--

Y

-

80
100
LOOP CURRENT ImAI

./
f-

120

Figure 5. Tip-Ring Voltage versus Loop Current
MOTOROLA COMMUNICATIONS DEVICE DATA

AN957

4-87

MICROPHONE CONTROLS

In Figure 6, when the handset mode is in effect, S1B
takes the MM pin low, enabling the handset microphone
by turning on the MIC pin (to ground). When the speakerphone mode is in effect, MM is taken high through R32,
disabling the handset microphone (MIC pin is open).

To mute the handset microphone when the speakerphone speech mode is in effect, the circuit of Figure 6 is
used for the MC34010 (MC34011, MC34013), and the circuit of Figure 7 is used for the MC34010A (MC34011A,
MC34013A).

TO
TONE RINGER
CIRCUIT
R5

llP

TO RECEIVE CIRCUIT

V+
Zl

-=

RING
T1

TO OTHER
CIRCUITRY
PER FIGURE 1

BP
VR
LR

1k

MC34010
SERIES
SPEECH NETWORK

1,5k

Note:
Sl
Hookswitch
(Shown On·Hook)
S2
Speakerphone
On/Off Switch

=
=

-=
MIKE
TO TRANSMIT AMPLIFIER

MIC
MM
V-

-=

SlB

cs,-----j
R33
47k

MC3401B

L...4l-fvvY\.....+---'r__---4-......--,V7'"+' SPEAKERPHONE

-=
Figure 6. Microphone Muting -

AN957
4-88

V-

-=
MC34010 Series

MOTOROLA COMMUNICATIONS DEVICE DATA

In Figure 7, in the handset mode, S1 B is open, T3 is on,
and the microphone bias current flows through the MIC
pin. In the speakerphone mode, S1 B is closed, turning off
T3, disabling the microphone. T3 is required for disabling
the microphone with the "A" series speech networks
since the transmit amplifier is disabled when the MM pin
is taken high.
In both the "non-A" and the "A" version circuits, the
handset microphones are muted during dialing due to
the fact that the MIC pin is opened by the dialer circuit.
SPEECH SIGNALS
Referring to the complete schematics (Figures 8, 9, 10,

and 11) the receive signals coming in on Tip & Ring are
sent to the handset receiver (at RXO) and to the speakerphone circuit's "receive input" path by the MC34010's
hybrid function. It is not necessary to mute the handset
receiver during speakerphone operation.
The transmit signals from the handset microphone are
put onto the Tip & Ring lines through the MC34010's hybrid function, with a gain determined by resistors
R27-R30. In the speakerphone mode, the transmit output
signals (at TXO of the MC34018) are attenuated by R35
before being applied to the MC3401 O's transmit amplifier.
The level of the speakerphone transmit signals at Tip &
Ring can be adjusted by varying R35.

TO
TONE RINGER
CIRCUIT
R5

TIP

TO RECEIVE CIRCUIT

v+
ZI

=

RING
TI

TO OTHER
CIRCUITRY
PER FIGURE I

BP

VR
'R
3k

MC340IO
SERIES
SPEECH
NETWORK

IK

=

Note:
SI = Hookswitch
(Shown On-Hook)
S2 = Speakerphone
On/Off Switch

MIKE
MIC
3K
R36

=

47k

v-

R33

.......,...."""1P---------;v:-:-l+

'-4....r:.!:~

MC34018
SPEAKERPHONE

v-

=
Figure 7. Microphone Muting -

MOTOROLA COMMUNICATIONS DEVICE DATA

MC34010A Series

AN957
4-89

KEYPAD
Rl
R2
R3
R4

• 0 #

;:.. l

DI'

TO
MS

, ~

rt-_r_---lCRl
R5 Cl9
RU
CIS
RXI

V+

r:1

R32

CP2

CS

SKG

RRX

C9
SKO

GNO

R35

MC34010/11 and MC34018
COMPONENT VALUES
Rl
R2
R3
R4
R5
R6
R7
R8

-30 k
-SI k
-3.3k
-1 M
-4.7 k
-1 M

-100 k
-4.7 k

R9 -4.3k

Rl0-200 k
RI'-24 k
R12-20k
R13-18 k
R14-2 k
RI5-1.8k
R16- 200 k
R17-1 k
R18-100
R1S-3S0
R20- 200 k
R21-56k
R22-150k
R23-56 k
R24-1.5 k
R25 -"' 1.5 k
R26-6.8 k
R27-270
R28- 200 k
R2S-4.7k
R30-4.7 k
R31-1.5k
R32-51 k
R33-47k
R34-36
R35-33k

Cl "-0.1
C2 -0.068
C3 -2.2p.F
C4 -2.2p.F
C5 -0.1
C6 -47p.F
C7 -4.7p.F
C8 -0.068
CS -47p.F
Cl0-lp.F
C"-0.05
C12 -47p.F
CI3-47p.F
CI4-4.7p.F
CI5-4.7p.F
CI6-0.05
CI7-0.01
CI8-0.05
C1S-0.l
C20-1000 p.F
C21-1p.F
C22-4.7p.F
C23-620 pF
C24-0.01
C25-0.D1p.F
C26- 2.2p.F
C27 - 0.1
C28-0.05
C2S-0.05
C30-1p.F, NP
C31-0.1
C32-0.1
C33-100 pF
C34-100 pF
C35-1p.F
C36-0.1

L1 -

1 Hry, < 10011

ZI-IBV
Z2-4.7V
Z3-30V
Z4-7V
Dl,D2-1N4001
Tl-2N4126
T2-2N2222A
Bl -IN4004's
B2-1N4004's
51 - DPDT (Hookswitch)
52 - DPST (Speakerphone switch)
Handset R'cvr - 300 11
Handset Mike - Electret
Spkr'phone Speaker - 25 11, 0.3 W
Spkr'phone Mike - Electret

Figure 8. HandsetlHandsfree System Using the MC34010/11 and MC34018

AN957
4·90

MOTOROLA COMMUNICATIONS DEVICE DATA

KEYPAD

Rl
9
•

R2
R3

0 #

l

DP

iii
MS

.;.'~" ~
,",,~--iCRl

CR2

R5 CI9

MC340IOAIllA

RU
CI6
RXI
C/

V+

CP2

CS

SKG

RRX

C9
SKO

GND

R35

MC34010AlllA and MC34018
COMPONENT VALUES

Rl -30 k
R2 -91 k
R3 -3.3 k
R4 - I M
R5 -4.7 k
R6 - I M
R7 -IDOk
R8 -4.7 k
R9 -4.3k
RIO-200 k
R11-24k
R12-20 k
R\3-18 k
R14-2 k
R15-1.8k
R16-200 k
R17-3 k
R18-100
R19-390
R20-200 k
R21..,..56k
R22-1S0 k
R23-56 k
R24-1.S k
R25-1.S k
R26-6.8 k
R27 -270
R28-20D k
R29-4.7 k
R30-4.7 k
R31-1 k
R33-47k
R34-36
R35-33 k
R36-3k

Cl -0.1
C2 -0.068
C3 -2.2I'F
C4 -2.2I'F
C5 -0.1
C6 -471'F
C7 -4.7I'F
C8 - 0.068
C9 -471'F
Cl0-l1'F
Cll-0.05
C12-471'F
C13-471'F
C14-4.7I'F
C1S-4.7I'F
C16-0.0S
C17-0.D1
C18-0.0S
C19-0.1
C20-1000 I'F
C21-11'F
C22-4.7I'F
C23- 620 pF
C24-0.1
C25- 2.21'F
C26-0.01
C27-0.1
C28-0.0S
C29-0.0S
C30-1I'F, NP
C31-0.1
C32-0.1
C33-100 pF
C34-100 pF
C35-11'F
C36-0.1

Ll-1Hry,<100n
Zl-18V
Z2-4.7V
Z3-30V
Z4-7V
01, 02 - 1N4001
Tl-2N4126
T2, T3 - 2N2222A
Bl - 1N4004's
B2 -lN4004's
Sl S2 -

OPOT (Hookswitch)
OPST (Speakerphone switch)

Handset R'cvr - 300 n
Handset Mike - Electret
Spkr'phone Speaker - 2S n, 0.3 W
Spkr'phone Mike - Electret

Figure 9. HandsetlHandsfree System Using the MC34010Al11A and MC34018

MOTOROLA COMMUNICATIONS DEVICE DATA

AN957

4·91

TIP
KEYPAD
Rl
R2
R3
R4
Cl
C2
C3

Rll
•

0 #

FB
V+
BP

lR
lC
VMC34013
VR
RXO

SOOkHz
RESONATOR

RXI
CRI
RM
CR2
CAl
STA

r:7

V+

R32

CP2

CS

SKG

C35

MM
MIC
AGC

TXO
TXI

RRX

C9

SKO

TXl
GND

R35

MC34013 and MC3401a
COMPONENT VALUES
Rl -30 k
R2 -91 k
R3 -3.3 k
R4 - I M
RS -4.7 k
R6 - I M
R7 - 100 k
RS -4.7 k
. R9 -4.3k
Rl0-200 k
Rll -24 k
R12-20 k
R13- IS k
R14-2 k
R17-1 k
R1S- 100
R19-390
R20-56k
R21 -200 k
R22- ISO k
R23-S6k
R24- 1.S k
R2S-1.5 k
R27- 270
R2S-200 k
R29-4.7 k
R30-4.7 k
R31-1.Sk
R32- S1 k
R33-47 k
R34-36
R3S-33 k

Cl -0.1
C2 -0.068
C3 -2.2 p.F
C4 -2.2 p.F
CS -0.1
CS -47 p.F
C7 -4.7 p.F
CS -0.068
C9 -47 p.F
Cl0-l p.F
Cll -O.OS
C12 -47 p.F
C13 -47 p.F
C14-4.7 p.F
C15-4.7 p.F
C1S-0.05
C17-0.01
C1S-0.05
C19-0.1
C20- 1000 p.F
C24-0.1
C25- 2.2 p.F
C26-0.01
C27-0.1
C2S-0.05
C29-0.05
C31-0.1
C32-0.1
C33- 100 pF
C34- 100 pF
C35-1p.F
C36-0.1

L1 -

I Hry, < 100 n

Z1 -1SV
Z4-7V
01,02-1N4001
Tl -2N4126
T2- 2N2222A
B2 -

lN4004's

S1 - OPOT (Hookswitch)
S2 - OPST (Speakerphone switch)
Handset R'cvr - 300 n
Handset Mike - Electret
Spkr'phone Speaker - 25 n, 0.3 W
Spkr'phone Mike - Electret

Figure 10. HandsetlHandsfree System Using the MC34013 and MC34018

AN957
4-92

MOTOROLA COMMUNICATIONS DEVICE DATA

TIP
KEYPAD
2 3
5 6
7 8 9

Rn

• 0 #

RI
R2
R3

FB
V+
BP

R4
CI
C2
C3

LA
LC
VVR
MC34013A
RXO

500 kHz
RESONATOR

RXI
CRI
RM
CAl

CAL
MM

C7

V+

HANDSET

STA
TXO

CP2

CS

SKG

TXI
RRX

C9
SKO

TXl

GNO

S2B

R35

MC34013A and MC34018
COMPONENT VALUES
Rl -3~ k
R2 -SI k
R3 -3.3 k
R4 - I M
R5 -4.7 k
R6 - I M
R7 - 100 k
RS -4.7 k
RS -4.3 k
RIO-200 k
R11-24k
R12-20 k
R13-1S k
R14-2 k
R17-3 k
R1S- 100
R1S-3S0
R20-56k
R21- 200 k
R22-150k
R23-56k
R24-1.5 k
R25-1.5 k
R27-270
R2S-200 k
R2S-4.7 k
R30-4.7 k
R31-1 k
R33-4.7 k
R34-36
R35- 33 k
R36-3k

Cl -0.1
C2 -0.06S
C3 -2.2J.'F
C4 -2.2J.'F
C5 -0.1
C6 -47 J.'F
C7 -4.7 J.'F
CS -0.06S
CS -47 J.'F
Cl0-1 J.'F
Cll-0.05
C12-47 J.'F
C13-47 J.'F
CI4-4.7 J.'F
CI5-4.7 J.'F
CI6-0.05
CI7-0.01
C1S-0.05
C1S-0.l
C20 -1000 J.'F
C24-0.1
C25-2.2 J.'F
C26-0.01
C27-0.1
C2S-0.05
C2S-0.05
C31-0.1
C32-0.1
C33-100 pF
C34-IOO pF
C35-1 J.'F
C36-0.1

L1 -

I Hry, < 100 n

ZI-1SV
Z4-7V
01,02 - lN4001
T1- 2N4126

T2, T3 - 2N2222A
B2 - 1N4004's
51 52 -

OPOT (Hookswitch)
OP5T (Speakerphone switch)

Handset R'cvr - 300 n
Handset Mike - Electret
Spkr'phone Speaker - 25 n, 0.3 W
Spkr'phone Mike - Electret

Figure 11. HandsetiHandsfree System Using the MC34013A and MC34018

MOTOROLA COMMUNICATIONS DEVICE DATA

AN957
4-93

CONCLUSION
Interfacing the MC34018 speakerphone circuit to the
MC34010 series of speech networks has been shown to
be simple and straightforward. The interface requires the
addition of 2 diodes, 5 resistors, either 1 or 2 transistors
(depending on the speech network), and one diode bridge
for the tone ringer circuit in the MC34010(A) and the
MC34011(A). Any existing MC34010 type circuit can be
easily modified to accept the speakerphone circuit.

AN957

4-94

REFERENCES
MC34010 Data Sheet, Dec. 1983, Motorola, Inc.
MC34010A Data Sheet, May, 1985, Motorola, Inc.
MC34013 Data Sheet, Nov. 1983, Motorola, Inc.
MC34013A Data Sheet, Feb. 1985, Motorola, Inc.
MC34018 Data Sheet, Apr. 1985, Motorola, Inc.

MOTOROLA COMMUNICATIONS DEVICE DATA

MOTOROLA

-

SEMICONDUCTOR
APPLICATION NOTE

AN958

Transmit Gain Adjustments
For The MC34014 Speech Network
By
Scott Bader and Dennis Morgan
Bipolar Analog IC Division

INTRODUCTION
The MC34014 telephone speech network provides for
direct connection to an electret microphone and to Tip
and Ring. In between, the circuit provides gain, drive capability, and determination of the ac impedance for compatability with the telephone lines. Since different microphones have different sensitivity levels, different gain
levels are required from the microphone to the Tip and
Ring lines. This application note will discuss how to
change the gain level to suit a particular microphone
while not affecting the other circuit parameters.

CIRCUIT DESCRIPTION
Refer to Figure 1. The microphone is assumed to be an
electret type, characterized by a high dynamic impedance.lt is therefore considered to be an ac current source
rather than a voltage source. If the microphone used has
a dynamic impedance which is not high (compared to
Ra), then the microphone must be modeled as a current
source paralleled by its dynamic impedance. That impedance value must then be considered to be in parallel with
Ra in the following equations. The Tx amplifier has a fixed
gain of - 20, and the EO amplifier gain varies from' 0.25
to 0.75, depending on the loop current. ZL is the line
impedance. The transmit gain is defined as V+/lmic and
is equal to:
V+
Imic

RS x ZL x ATX
(1 + RstRA)Rg + (ATX) (AEO) (ZLl

where ATX = gain of the transmit amplifier (20 VN)
AEO = gain of the equalization amp. (0.25 to
0.75 VN)
RA = Rall10 kO (10 k!l. = input impedance
ofTx amp.)
The ac impedance of the circuit is defined as:
Zac = Rg (1 + RstRA)
(ATX) (AEQ)
The receive gain (see data sheet for the equivalent circuit) is defined as:
Grx

=

R4 + (Xd/ R2) (AEO) (ATXO) (ASTA) x R4
R1
((XCI/R2) + R3) (1 + RstRA) x R2

As can be seen from the above equations, changing RS
while maintaining the RstRA ratio constant will result in
a transmit gain change (proportional to RS) but will not
affect the other parameters. For example, increasing Ra
and RS by a factor of 3 will increase the transmit gain by
=10 dB.
Using the above procedure to increase the transmit
gain results in increasing Ra, which supplies the bias current to the microphone. If the higher value of Ra results
in insufficient bias voltage at the microphone, then the
alternate biasing scheme of Figure 2 should be used.

v+
10 k

R6

10 k

0.05
.....-~o---i~--¢TXI

MC34014

L-------¢MIC

Figure 1. MC34014 Transmit Section

MOTOROLA COMMUNICATIONS DEVICE DATA

Figure 2. Alternate Biasing Scheme for
Higher Voltage Microphones

AN958
4-95

TEST RESULTS

CONCLUSION
Although the designs of the various parameters (transmit gain, receive gain, ac impedance, etc.) ofthe MC34014
speech network are not mutually exclusive due to the
commonality of various components, it is possible to adjust the transmit gain independently to suit a particular
microphone.
For further information on the MC34014 speech network, refer to the data sheet.

Tests were conducted with a Primo EM-95A microphone, having a sensitivity of -53 dB ±3 dB (0 dB = 1
V/ftbar), and a Hosiden KUC2123 microphone which has
a sensitivity of -60 dB ±3 dB. The test circuit is shown
in Figure 3. The tests consisted of applying a constant
sound level to the microphones, and measuring the output at VeQ, while simulating line lengths of 0-21 Kfeet.
The outputs of the two circuits were nearly identical at
all line lengths.

200

MIKE
RS

47

TXO

LR

0.05

0.2

TXI

LC

RS

MC34014
EQ

150 k
V+

2.4 k

LOOP
CURRENT

V+

MIC
VR

~

2 p.F

2.4 k

VR

STA

~

30 p.F
VDD

RXI

RXO

Mf
RMT

V-

MS
TI

~

!

DIALER
INTERFACE

':"

For Primo EM-95A microphone RS = 500 n, R6 = 10 k
For Hosiden KUC2123 microphone RS = 1.5 k, R6 = 30 k

Figure 3. Microphone Gain Test Circuit

AN958
4-96

MOTOROLA COMMUNICATIONS DEVICE DATA

MOTOROLA

-

SEMICONDUCTOR
APPLICATION NOTE

AN959

A Speakerphone
With Receive Idle Mode
By
Dennis Welty and Dennis Morgan'
Bipolar Analog IC Division

CIRCUIT DESCRIPTION
The additional circuitry is shown in Figure 1. The receive signal normally applied to RXI also drives XDI
through a 2.7 kn resistor and a 0.1 JLF capacitor. XDC is
connected to VLC through the NPN and PNP emitter followers. When voice signals in the receive channel exceed
the background noise by 4.6 dB, XDC switches high and
turns off the PNP transistor (the 4.6 dB threshold is built
into the MC34018). The voltage at VLC is then determined
by the volume control potentiometer. When voice signals
are no longer present, XDC decays to 0.5 VB and turns
on the emitter followers. The voltage at VLC is now determined by the voltage at XDC. By decreasing the VLC
voltage with the emitter followers the transmit and receive gains are adjusted to produce a receive-idle mode.
A peak detector using an external voltage comparator
and diode is required to hold the receive attenuator fully
on (out of the idle mode) when constant level signals,
such as dial tone, are intentionally presented to the re-

INTRODUCTION
The MC34018 speakerphone system operates on the
principle of comparing the transmit and receive signals
to determine which is stronger, and then switching the
circuit into that mode. Under conditions where noise
from the telephone line (in the receive path) exceeds
the background noise in the transmit path, the speakerphone wi" switch easily, or even lock, into the receive
mode. Under these conditions the conversation wi"
sound "dead" to the party at the far-end. It wi" also be
more difficult for the near-end party to activate the
transmit channel since the transmit detection is at the
output of the transmit attenuator, which wi" be at maximum attenuation during this time. The addition of a
receive idle mode can alleviate this problem by ensuring that the transmit and receive gains will be approximately equal when no voice signals are present. This
allows the far-end party to hear ambient noises, and
also increases the sensitivity to transmit signals.

MC34018

MCO

XDI

10

XDC

13

VLC

23

VB

24

2.7k
2.7k

10 k

200
k

~

...........

1M

91k

*

~~Pt
1

+
10

16

200

51 k

Jl000

~J

-=

"

470 k
20 k

10 k
1

r

lN4150
24 k

k

-= -= ~

27
DC
SUPPLY

51 k
VOLUME
CONTROL

V

0.1 ;;

20

~ ~

0.1 "F'

RXI

V+

VCC

21

-=

112
LM393'
OR
EQUIV.

8~
+ 2k
4

>--

0.1

3
47k

~

RECEIVE
SIGNAL

"="

lO"

'SEE LM193 DATA SHEET.

Figure 1. Receive-Idle Circuit

MOTOROLA COMMUNICATIONS DEVICE DATA

AN959
4-97

ceive channel. When the receive signal at the receive input exceeds the threshold on the comparator (typically
20 mV) the peak detector charges the capacitor at XDC
which prevents the speakerphone from relaxing to the
idle mode. The PNP transistor is turned off and the voltage at VLC is then determined by the volume control
potentiometer. Under these conditions the speakerphone
will be in the receive mode.
The sensitivity threshold of the voice detector circuitry
can be changed by applying a dc current to XDI. The
threshold current (nominally 250 nA) also prevents XDC
from switching sporadically in quiet signal conditions.
The threshold current is determined by the 1 Megohm
resistor between XDI and the 10 k0/91 kG divider refer-

AN959
4-98

enced to VB. Whenever receive signal currents exceed
the threshold current by 4.6 dB, the voice detector will
respond and allow XDC to switch high.

CONCLUSION
The receive-idle mode is simple to implement, and improves the performance of the speakerphone system by
allowing noise rejection in both the receive and transmit
channels. The voice-switching function operates only on
valid speech, and ignores background noises.

REFERENCES
MC34018 data sheet, Motorola, 1985
LM193 data sheet, Motorola

MOTOROLA COMMUNICATIONS DEVICE DATA

MOTOROLA

-

SEMICONDUCTOR
APPLICATION NOTE

AN960

Equalization of DTMF Signals
Using the MC34014
by
Scott Bader and Dennis Morgan
Bipolar Analog IC Division

INTRODUCTION
This application note will describe howto obtain equalization (line length compensation) of the DTMF dialing
tones using the MC34014 speech network. While the
MC34014 does not have an internal dialer, it has the interface for a dialer so as to provide the means for putting
the DTMF tones onto the Tip & Ring lines. The Equalization amplifier, whose gain varies with loop current, was
meant primarily to equalize the speech signals. However,
by adding one resistor, it can be used to equalize the
DTMF signals as well.

CIRCUIT DESCRIPTION
Referring to Figure 1, the gain of the equalization amplifier varies with loop current as it is a function of the
voltage at the LR pin (Pin 13). The gain varies from a
minimum of -12 dB at low loop currents (long line), to
- 2.5 dB at high loop currents (short line). The output at
EO (Pin 6) is in phase with the signals going out onto Tip
& Ring, but is out of phase with the DTMF input signals
from the dialer at R7 (see Figure 2). Because of the outof-phase relationship, the signal at EO can be used to
partially cancel the signals at the Tone Input (Pin 16). The
addition of resistor Rl0 provides the path for this function, with the result that the DTMF gain increases as loop
cu rrent decreases.
-2.0
-3.0

I
I
II

-4.0
-5.0
@-6.0

::?+ -7.0

Because the addition of Rl0 cancels some ofthe signal
going into Pin 16, resistor R7 must be decreased in order
to restore the overall gain from the dialer to Tip & Ring.
The DTMF gain values indicated in Figures 3 and 4 is
the gain from the tone dialer (input at R7) to the Tip &
Ring lines terminated with a 600 ohm resistor. Figure 3
indicates the gain CHANGE (as the loop current is varied
from 60 to 20 mAl versus different values of Rl0. The
gain change is a function of Rl0, and independent of R7.
Figure 4 indicates the DTMF gain versus R7 for different
values of Rl0 at a loop current of 20 mAo
Because the typical telephone line is not purely resistive, there will be a phase shift of other than 180 from
the DTMF dialer to Tip & Ring in most applications. For
this reason, the values of Rl0 and R7 will have to be
adjusted slightly from those in the graphs to compensate
for the phase shift.
0

The MC34014 data sheet mentions that a dc bias current of 20-50 /LA is required into Pin 16 in order to bias
the DTMF amplifier. The addition of Rl0 will provide the
bias current from the EO output for most applications,
in which case it may be desirable to ac couple the dialer
to R7 with a 0.5 /LF capacitor. Excessive bias current will
result in clipping of the signals at Tip & Ring. If just the
addition of Rl0 results in excessive bias current, then
the EO output should be ac coupled to Rl0 with a 0.5
/LF capacitor, and the bias current supplied either from
the dialer or from an additional resistor as shown in
Figure 5.
For further information on the MC34014, refer to its'
data sheet.

J

;;-80

I
II

~-9.0
!?5 -10
-11
-12

J
0.2

0.6

1.0

1.4

1.8

2.2

2.6

VLR IVOLTSI

Figure 1. Equalization Amplifier Gain

MOTOROLA COMMUNICATIONS DEVICE DATA

AN960
4-99

14

5

I-4"'"

2

I-

.........

I--

.........

........
2

0

st--..

'--

'" ..........

~
6~
........

I--

4

I- ILOOP VARIED FROM

10

1-1--

60 TO 20 rnA
15

20

25

30

Rl0 =

ex>

~ I---

> 300

Rl0-kO

r--

~ t:::::---r--

V

1-1--

o

r---.....

b:r:::::::: ~ ~

Rl0 = 12k/.. ~ ~
2
-...........
= 15~/
= 20k
0
= 3Ok'
ILOOP = 20 rnA
I
2
14
16
10
12
R7-kO

1-1--

1

""" t-.....

Figure 3. Gain Change

~

lS

--

~

20

22

Figure 4. DTMF Gain

75 k
DTMF
0.5
R7
INPUT >----1'!--.ANr--.....-n-O

MC34014

Rl0
0.5
EQ

Figure 5. Alternate Biasing

AN960
4-100

MOTOROLA COMMUNICATIONS DEVICE DATA

MOTOROLA

-

SEMICONDUCTOR
APPLICATION NOTE

AN1002
A Handsfree Featurephone Design
Using the MC34114 Speech Network
and the MC34018 Speakerphone ICs
Prepared by
Dennis Morgan
Bipolar Analog Ie Division

INTRODUCTION
This application note describes the procedure for combining the MC34114 speech network with the MC34018
speakerphone circuit into a featurephone which includes
the following functions: ten number memory pulse/tone
dialer. tone ringer. a "Privacy" (Mike Mute) function. and
line length compensation for both handset and speakerphone operation.

TIP

Three circuits are developed in this discussion: a linepowered featurephone. a line-powered featurephone
with a booster (for using the speakerphone on long lines).
and one powered from a power supply. The circuits are
nearly identical. except for the Tip/Ring interface. Their
performance. however. differs noticeably. particularly in
the low loop current range. Initially. the discussion will
focus on the line-powered circuit.

Rll
RB

Rl

RECEIVER

R4

MIKE

R5

NOlE: PIN NUMBERS IN PARENTHESES
ARE FOR TliE SOIC PACKAGE.

Figure 1. MC34114 Block Diagram

MOTOROLA COMMUNICATIONS DEVICE DATA

AN1002
4-101

MC34018 Speakerphone
The MC34018 speakerphone IC (see Figure 2) provides
all of the necessary functions for a complete speakerphone circuit in a single integrated circuit. Included are
the transmit and receive attenuators, which operate in a
complementary manner, to provide the necessary halfduplex function. The two level detectors, in conjunction
with the background noise monitor and control algorithm, provide a two point sensing and decision making
system to control the attenuators based on the levels and
timing of the transmit and receive signals. Additional
functions include the microphone amplifier, speaker
amplifier, volume control for the receive path, and a chip
select pin. The gain of the speaker amplifier, normally
+34 dB, is reduced by the AGC circuit in the presence of
strong signals to prevent clipping at SKO. The component
values shown are typical.
Connections to the speakerphone circuit are made to
the four points at the right end of Figure 2 (Receive Input,
DC Supply, Chip Select, & Transmit Output).
The DC supply requires 4 to 11 volts dc, and it must
be well filtered to prevent oscillations when the speaker
amp is operating. In a typical line powered circuit, an
inductor (1H) is used, in conjunction with the 1000 p.F
capacitor shown, to filter the voltage derived from the
loop current.
The Receive Input of Figure 2 is derived from the 4-wire
side of the speech network. The gain from RXI to the
speaker is +40 dB when in the receive mode at maximum
volume (+6 dB in the attenuator, +34 dB in the speaker
amp). At minimum volume, the attenuator's gain reduces
by =30 dB, for an overall gain of + 10 dB. In the transmit
mode, the receive gain is '" - 4 dB.
The transmit gain, from the microphone to Transmit
Output, is +40 dB (+34 dB in the mike amp, +6 dB in
the attenuator), and does not vary with the volume control. 'In the receive mode, the transmit gain is = -4 dB.
The Transmit Output will connect to the 4-wire side of
the speech network.

DESCRIPTION OF THE BUILDING BLOCKS
NOTE: Several pins on the ICs used in this application
note have identical nomenclature (VCC, VB, TXI, MS, VDD
and RXI). They provide separate functions, and are not
to be connected together, unless so noted.
MC34114 Speech Network
The MC34114 is a speech network which interfaces with
Tip & Ring and provides the 2-to-4 wire conversion (see
Figure 1). The transmit gain is determined by the microphone amplifier (fixed gain of 30 dB), R6, C5, the internal
current gains of A 1, A2, the AGC, and the line impedance
in parallel with R1. The receive gain is determined by ZB,
the internal current gains of A4 and AGC, C8 and R8. The
sidetone cancellation is determined by A3 and the ZB
network. The AGC points have a current gain of 1 at low
loop current, and decrease to 0.5 (- 6 dB) at higher loop
currents, thus providing line length compensation. R1
(typically 600 0) sets the circuit's terminating impedance
for ac (return loss) purposes.
The MUTE input (when low) disables the microphone
amplifier, and partially mutes the receive amplifier (with
an internal 1 k feedback resistor), when dialing. DTMF
dialing signals are injected at TXI through R7 and C6. The
Mode Select (MS) input (when low, and MT is low) provides a voltage boost at VCC to ensure adequate voltage
during DTMF dialing at low loop currents. The 3.3 volt
regulated output (VDD) powers the dialer, and the 1.7
volt regulated output (VR) is used to bias the microphone.
The dc characteristics at Tip & Ring are determined by
the diode bridge (1.4 volts), a level shift of approximately
2.9 volts from VCC to LR, and the voltage across R2 + R3
(typically 43 nand 13 0). All the loop current, minus
"'10 mA, flows through those two resistors. The level
shift (VCC- LR) increases to "'3.9 volts when both MUTE
and MS are low (tone dialing mode). The voltage at
RAGC, when within the range of 0.5 to 1 volt, controls
the internal AGC as a function of loop current.

21

BACKGROUNO
NOISE
MONITOR

CHIP
SELECT •
VB

MIKE

RTX

RR

RRX

TXI

1"'

RLO

28
200k
4.1

0.1

91k

,.

TRANSMIT
OUTPUT

:;j

30k 18k

-= -=

-=

VOLUME
CONTROL

24k

":"

Figure 2. MC34018 Block Diagram
AN1002
4·102

MOTOROLA COMMUNICATIONS DEVICE DATA

The overall speakerphone's transmit and receive gains
to/from Tip & Ring will be adjusted at the interface from
Figure 2 to the speech network.
Chip Select enables the MC34018 when at a logic low.
The MC34018's supply current is normally ==5 mAo When
CS is taken higher than 1.6 volts, the IC is disabled, and
the supply current drops to ==500 pA.
VCC (Pin 20) is a regulated 5.4 volt output, and VB (Pin
21) is a regulated 2.9 volt output. VB is typically used to
bias the microphone.
MC145412 Dialer
The dialer is a pulse/tone dialer with 10 number memory, including last number redial (Figure 3). The pulse
and tone functions are selectable by Pin 10 (MS). The
circuit uses a standard 3.58 MHz crystal, and a standard
3x4 or 4x4 keypad.
The NPN transistor at Pin 12 indicates the on-hookloffhook status to the IC. Power for the dialer is the
MC34114's VDD (3.3 volts), diode connected with a memory sustaining battery. The DTMF output goes to C6/R7
of Figure 1, which sets the gain.
The OPL (OUTPULSING) pin is used to interrupt the
loop current when pulse dialing. The pin is active low,
open drain. TSO (Tone Signal Output) provides a pacifier
tone during pulse dialing. The tone is a 500 Hz square
wave, which swing from VDD to VSS.
The Mute Output (MO) is active low, open drain, and
pulls to ground while dialing. It is used to mute the speech
paths during dialing.

VSS
":;"

MC145412
DIALER

KEYPAD

I

2 3

A

4

5

B

7 8

6

7 _ _ _--. TO PULSE
Qii[ ,",1c:...
OIALCKT.

16

Rl

(-'=-_+-,....... g~~~UT

Table 1.
HANDSET SPEAKERPHONE
Mike

Speaker

Handset Speech
Handset Dialing
Handset Mike Mute

On
Off
Off

On
Mute
On

Off
Off
Off

Off
Off
Off

Speakerphone Speech
Speakerphone Dialing
Speakerphone Mike Mute

Off
Off
Off

Off
Off
Off

On
Off
Off

On
Mute
On

Function

Mike R'cvr

In Table 1, "ON" means fully functional, "OFF" means
non-functional, and "MUTE" means partially muted (10
to 20 dB). To apply Table 1 to the specific ICs described
above, the requirements are expanded as follows:
Table 2.
MC34114
Function

MC34018
CS

Loop
Current

MC145412
MS

X

Hi

Thru MC34114

X

Hi

Hi

Thru MC34114

Open

Lo"

Hi

Thru MC34114

Gnd

X

Hi

Thru MC34114

X

Lo

X

Lo

To MC34018

X

Lo

Hi

Lo

To MC34018

Open

Lo

Lo

Lo

To MC34018

Gnd

Lo

X

Lo

To MC34018

X

MT MS

Handset
Hi
Speech
Handset Pulse Lo
Dialing
Handset Tone Lo
Dialing
Handset Mike Lo
Mute
Speakerphone
Speech
Speakerphone
Pulse Dialing
Speakerphone
Tone Dialing
Speakerphone
Mike Mute
X = Don·' Care

15
14
13

fROM

VOO 1-'-~*".-4-<
I
MC34114
VOO

MUTE
r--4----1~ OUTPUT

1-'-_ _ _---1~ ~~~:'ER

A summary of Table 2 is:
a) The MC34114 speech network is put into the Mute
mode (MT = Lo) not only for dialing, but also to mute
the microphone and receiver for the Privacy function
(Mike Mute), and when in the speakerphone mode.
b) The MC34018 is disabled for all the handset functions,
and enabled for all the speakerphone functions.
c) The loop current, which normally flows through the
LR pin of the MC34114 (see Figure 1), is directed
instead to the MC34018 in the speakerphone mode so
as to make the power available to the speaker.
d) The MS pins of the dialer, and of the MC34114, are
significant only during dialing.

Figure 3. PulseITone Dialer

SWITCHING THE CIRCUIT AROUND
The logic functions involve: a) switching the circuit
from handset mode to/from speakerphone mode,
b) switching in and out of either dialing mode while in
either handset or speakerphone mode, and c) muting the
two microphones for the "Privacy" function. Table 1 tabulates the fundamental requirements applicable to any
featurephone:

MOTOROLA COMMUNICATIONS DEVICE DATA

PUTTING IT ALL TOGETHER
Switching Between Handset and Speakerphone Modes
To switch between m"odes, two actions are necessary:
1) Divert the excess loop current, which normally flows
through the MC34114, to the MC34018 during speakerphone mode, and 2) enable and disable the speech network and speakerphone circuits appropriately. The circuit
of Figure 4 fullfills those requirements:

AN1002
4-103

LOOP
CURRENT

I

43,1 W
VCC-------LR
RAGC

MC34114

MT

GND

RING
V+

]:1000
_
82k

MC34018
GND

-=
1M

CS
13
1/4W

Q4

~

2N2222A, DIODES

~

lN4001, OR EQUIVALENT

Figure 4. Switching Between Modes

HS (3 poles) is the hookswitch operated by lifting the
handset. SS (1 pole) activates the speakerphone when
the handset is on-hook. The switches are shown on-hook
in Figure 4.
If the handset is lifted (HS transfers), the MC34114 consumes =10 mA internally, and the excess loop current
flows out of the LR pin and through the 43 il and 13 il
resistors. The voltage across the 13 il resistor controls
the AGC function. The configuration in this position is
similar to that of Figure 1. Additionally, 04 is off, allowing
CS to be pulled high, disabling the MC3401B.
If the handset is on-hook, and switch SS is closed, the
MC34114 still consumes =10 mA internally, but the
excess loop current now flows through the 1 Henry
choke, the zener diode, and the 13 il resistor. The voltage
across the 13 il resistor still controls the AGC function
of the MC34114. The MC3401B's CS is held low by 04,
enabling the speakerphone, and the MC34114's MT is
low, muting its microphone and receive amplifiers. Ifthe
handset is lifted while the speakerphone is in operation,
the circuit reverts to the handset mode.
It may appear that CS and MT could be connected
together and to HS3 to provide the same functions,
thereby eliminating 04. The fact, however, that other
parts of the circuit will be connected to MT in subsequent
sections of this application note negates that possibility.
Joining the Receive Paths
Refering to Figure 1, receive signals arriving at Tip &
Ring generate a current through the lB network, into Pin
15. That current is modified by A4, the AGC, made available (as a current) at RXA, and coupled to RXI, where it
is converted to a voltage by the receive amplifiers and
RB. The lB network is typically 12 kil, and RB is typically
3.9 kil. The receive gain to the handset receiver is therefore nominally -10 dB at low loop currents.
To feed the receive signals to the speakerphone, the
circuit of Figure 5 is used.
The current out of RXA is now split (by the 1 kil resistors) so that approximately half goes to RXI (of the

AN1002
4-104

MC34114) via CB, and the other half is converted to a
voltage (by the op amp) for the speakerphone's Receive
Input (Figure 2). The MC33171 was chosen for its very
low supply current (typically lBO /LA). The op amp is powered from the MC3401B's VCC output (5.4 volts), and
biased by the MC3401B's VB (2.9 volts). The receive gain
for the speakerphone is determined by the following
equation:

= 20 I (RRSP x A4 x AGC x 0.5)
40 dB
G
RX
09
lB+500 il
+
The terms A4, lB, and AGC (from Figure 1) are set at
0.5, 12 kil, and 1 respectively for low loop currents. The
0.5 in the above equation is due to the current splitting
of Figure 5, and the + 40 dB is the gain ofthe MC3401B's
receive attenuator and speaker amp. For a nominal
overall gain of +30 dB, RRSP calculates to =1B kil. At
higher loop currents, the overall gain will be = +24 dB.
The above equation assumes the volume control is set
to maximum.
To compensate for the reduced current going to the
MC34114's receive amplifiers, RB (Figure 1) is increased
to B,2 kil.

~""--l..

TO RECEIVE
INPUT
(FIGURE 21

Figure 5. Joining the Receive Paths

MOTOROLA COMMUNICATIONS DEVICE DATA

MC34018

Figure 6. Joining the Transmit Paths
Joining the Transmit Paths
In the transmit path of Figure 1, the microphone signals
are gained up by 30 dB by the mike amplifier. The output
at MCO creates a current into TXI through R6 and C5.
That current is gained up by 100 by A1 and A2 (assume
AGC = 1), and A2's output current then acts on the parallel combination of R1 and the line's ac impedance. Typical values are: R6 = 15 kn, R1 = 600 n, and 600 n for
the line's impedance. Neglecting the slight loading of R7,
R12, and ZB, the overall handset transmit gain is =+36
dB at low loop currents.
The transmit output (voltage signals) from the speakerphone circuit (Figure 2) is applied to the speech network
at TXI (a current input) in Figure 1, through a resistor
(RTSP) and a coupling capacitor (see Figure 6). For a
nominal gain of +44 dB (from the microphone to the
MC34114's VCC), RTSP calculates to be =18 kn. The coupling capacitor (nominally 0.1 JLF) can be varied to set
the low freq uency rolloff.
Fitting in the Dialer and Another Switch
The Mute Output of Figure 3 must mute three items:
1) The MC34114 by pulling its MT pin low, 2)the
MC34018's transmit path, and 3) the MC34018's receive
path. This is accomplished with the circuit of Figure 7:

During dialing, 01-03 are turned on by the dialer. 01
mutes the MC34114, which shuts off its microphone
amplifier, and mutes the receive amplifier by =27 dB. To
mute the speakerphone's transmit path, RTSP (of Figure
6) is divided into two resistors, and the junction pulled
low by 02, providing =35 dB muting of TXO's signal.
Since the MC34018 will switch to the receive mode during
DTMF dialing, the transmit attenuator will provide an
additional muting of 44 dB, for a total of =79 dB. The
speakerphone's receive path is muted by reducing the
effective resistance at RRX (MC34018's Pin 28) from 18
kn to =3.7 kn with 03. From Figure 3 of the MC34018's
data sheet, the receive attenuator's gain is reduced by
=23 dB. The 1 JLF capacitor on 03 softens any "pops" in
the speaker when switching out of muting.
The DTMF output in Figure 3 is simply connected to
C6/R7 of Figure 1 (or Figure 6) to get the DTMF signals
to Tip & Ring. Using 24 kn for R7, and 0.1 JLF for C6,
DTMF levels of = - 3.8 dBm will result at Tip & Ring.
For pulse dialing, Pin 17 of the MC145412 dialer (OPL)
is connected to a standard two transistor network to interrupt the loop current (Figure 8). The 12 volt zener diode
protects the circuitry from voltage spikes during pulse
dialing, and whenever a hook switch is opened.
The TSO output (pacifier tone), which is generated only
when a keypad button is depressed in the pulse dialing
mode, is injected to the MC34114's ZB pin so as to make
it available to both the handset receiver and the speakerphone. This tone is not generated during DTMF dialing.
To select between pulse and tone dialing modes, the
switch on the dialer's Pin 10 (Figure 3) is connected to
the MC34114's MS pin (Pin 16). Since the MC34114's MS
pin requires a pull-up resistor for a logic high, a diode
must be added (Figure 8) so the dialer's MS pin is open
when the switch is in the pulse position.
Switching in Some Privacy
The Privacy function (Mike Mute of Tables 1 and 2)
requires only a 2 pole switch. One pole mutes the
MC34114 to disable its microphone amplifier. The other
pole is wired directly across the speakerphone's
microphone.

MC34018
28

0.1

18k

FROM
Voo 1-:-~4-1r-......<34114
Voo

L------

TRANSMIT
OUTFUT

'---"N'~""'-'\o",,"--l,--------- ITO MC34114
TXI-PIN 101

MC145412

NPNs ARE
2N2222A

Figure 7. Muting Circuit

MOTOROLA COMMUNICATIONS DEVICE DATA

AN1002
4-105

MS

1-';.:.°+f-'l~-;T;;;ON7;:"E------"l\'S~~~4~~i
~
PULSE
-=

Figure 8. Pulse Dialing Circuit
Adding the Tone Ringer
The MC34017 tone ringer circuit, shown in Figure 9, is
added tothe circuit bysimply connecting it directly across
Tip & Ring. It is not necessary to disconnect the tone
ringer when off-hook. This circuit will provide a ringer
with an REN of =0.5, and meet all the EIA-470 and Bell
system requirements for impedance, ilnti-bell tapping,
and turn-on/off thresholds.
Finally, the Complete 'Circuit
The complete line-powered featurephone is shown in
Figure 10. The performance curves for this circuit are
shown in Figures 11-16. The "Speaker Amp Max Output
Swing" is the maximum rms voltage available at the
speaker amp output (Pin 15) of the MC34018 (its internal
AGC circuit limits the maximum output to prevent clipping). The transmit gain tests involved replacing each
microphone with a signal generator, and adjusting for a
level of approximately -11 dBm at Tip & Ring into a
600 n resistive load. The receive tests involve applying

approximately -27 dBm to Tip & Ring, and measuring
the gain to the receiver or speaker.
As can be seen in Figure 12, the maximum available
speaker power is a function of the loop current since
all of the speaker current must come from the loop.
Consequently, the receive gain for the speakerphone
(Figure 15) shows a marked decrease at low loop currents. It must be remembered that in a line powered
speakerphone, as the 'speaker draws current in
response to a receive signal, the voltage at Tip & Ring
decreases quickly. As the MC34018's V + falls with the
Tip & Ring voltage, the speaker amp's output capability
is reduced. Consequently, a 25 n speaker is recommended for a line powered speakerphone as this makes
the best use of the power available from the phone line.
A lower impedance speaker will require more current,
causing V + to sag further for a given signal level. A
higher impedance speaker draws less current, but produces less sound power.

TIP
6.Bk.1/2W

RING

S~~g~ES

?

11'F. NPO

MC34017

TONE RINGER
ACl

ROl

RI

------

TO TELEPHONE
CIRCUIT
PlEZO SOUNOER

Figure 9. Tone Ringer Circuit

AN1002
4-106

MOTOROLA COMMUNICATIONS DEVICE DATA

s::

HSI

a
o

TO PULSE!
TONE SWITCH

JJ

~

43,lW

"E,Cllnrn

i'i
m III

lN4742
12V

s;:

li'go 'gos,:e

820

s::
c

VB

z

HANDSET
MIKE

o
o
z

GNO

MUlE

OPL

:!i

OIAlER

en
o

Rl

~

...L

I rlllh

o

VOOr

o
»~

Mii

!!!.3

3°0-

l~k! I

.J

~z
lk
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II

16 III

s:a.
n ttl
w:E
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c» ~

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_.......

I'" '"I I·v:::it I"
..."

- ..-

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V+116,

.,'

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s:: ~cc
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CD:::I' ~
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......._._--

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OTMF
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"CI

NETWORK

lOOk

;g.;
: ;: °

t 0£I' 8.
'go 5'
CD°:E
0.
.:::1-'
ttI:::I'
oCIJ:::I

MC34114
SPEECH

MC145412

::I 0

CD

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r"'I"I::::J ....... CD
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=

13,1I4W
RTX I RR

10~j...:.J

iii'

2S

cE•

=:

1) All capacitors in p,F except

where noted.

:J>

.....

oI>oZ
.... 0

~IG

a;

~j;!

MUlE~
~MU1E
100 k

Figure 10, PulselTone Featurephone w/Memory -

:E
3 ~
::::r I::
=S" ~
CD rn :E

_y

9:~,::J'
m
..... -·

oo

::::J:l"'_.

0..

to

:E
::r
Line Powered

8.
-.J -, If
m c.""

a.'ttlCDy

RRX

Notes:
2) H5 ~ Handset operated hookswitch - 3 poles.
55 ~ Speakerphone on/off switch - 1 pole.
Switches shown in on-hook position.
3) All diodes 1N4002,
4) These resistors depend on the specific microphones.

CD

CD
::::J

s·

=:°CD

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~

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mc.::J
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Q.

;

MC34114/MC34018 Line Powered Featurephone
4

J.

HANDSET MODE (TONE DIALlNGI~
21--- SPEAKERPHONE MODE
I--ISPEECH/PULSE DIALINGI
./
ITONE DIALINGI
\,./'"
0
,..(
/'
~

~

..& .......

V

a

40

V

~

SPEAKER AMP. MAX.
OUTPUT SWING

1.2

~~

,;;:; ~

en

:;;
a:

~O.8
§;
0.6

~ANDSET MODE

(SPEECH MODEl
(PUL~E DIALINGI

P"

20

---

..........

......:: ~

~ P' ~r-

...........A
4

V

V>

,-

1.4

NO SIGNAL AT SPEAKER IN SPEAKERPHONE MODE

V
I

100

120

/
20

j

//

3S _

'"

~ 36
"'34

""

HANDSET MODE........

40

20

100

120

I

+30

iL

'/
/
/

.............

_ ~ANDSET MODE
ILOOP = 30 mA

V

:s

'---

~ 34

'"

2

""'"

60
so
LOOP CURRENT (mAl

100

30
100

120

300

1k
FREQUENCY (Hz!

4k

Figure 14. Transmit Gain versus Frequency

'THIS REGION NOT RECOMMENDED FOR SPEAKERPHONE USE

+30

"" '\
\

r--

+26
~EAKERPHONE

"'"

SPEAKERPHONE MODE
ILOOP = 40 mA .......

MODE ~+22
z - 4"

I'
~

..........

-

«

~

'"

V

6

-...;.
100

Figure 15. Receive Gain versus Loop Current

......- ....-

' - - ~ANDSET MODE
ILOOP = 30 mA

~JMODi

-10 f = 1kHz
-12 GAIN IS FROM TIP/RING TO RECV'R/SPKR.
60
SO
20
40
LOOP CURRENT (mAl

AN1002
4-108

S~EAK~RPHOINE ~OdE
v'

Figure 13. Transmit Gain versus Loop Current

-6
-S

60
SO
LOOP CURRENT ImAI

6

I

f=1kHz I
GAIN IS FROM MIKE TO TIP/RING

30

~+lS

r--

in

..........

32

~+20

40

ILOOP = 40 mA

~EAKERPHONE MODE - -

'"

«

in

LEVEL AT TIP/RING -

40

z

+22

~TMF

Figure 12. Speaker Amplifier Output and DTMF Level
versus Loop Current

/

S

+26

"

'THIS REGION NOT RECOMMENOED FOR SPEAKERPHONE USE

0

+24

V

V

0.2

Figure 11. Tip to Ring DC Voltage
versus Loop Current

+2S

,.....

-I'-- ./

/

0.4

60
SO
LOOP CURRENT (mAl

--

/'

V

V

120

S
9
100

lL1

300

lK
FREQUENCY (HzI

4K

Figure 16. Receive Gain versus Frequency

MOTOROLA COMMUNICATIONS DEVICE DATA

BOOSTING THE SPEAKERPHONE AT
LOW LOOP CURRENTS
Adding a Booster
To improve the performance of the speakerphone at
low loop currents (below 30 mAl, a minimal cost
approach is to add an optional booster to the power
supply portion of the MC34018. The approach in this
application note is to use a wall mount transformer,
similarto calculator chargers. A 9 volt ac Adapter, Radio
Shack model #273-1455A, which contains the diode
bridge and filter capacitor, was used to minimize the
additional circuitry within the speakerphone itself.

Since this particular ac adapter is specified for use with
Radio Shack's speakerphones (model Duofone 102), it
is this author's assumption that it complies with applicable FCC specifications, although that is not so stated
on the transformer.
This application does not require a regulated voltage
from the ac adapter, which further simplifies the design.
The circuit of Figure 17 adds the ac adapter to the circuit
of Figure 10:

FROM
TIP & RING

IOOO
::t
=

MC34018

1N4734
5.6V

82k

~------~lR

CSI-1c:;.8_ _..

02

MC34114

.-.....+ - - - - - - 1 RAGe
47

13,

1I4W

20 k

OIOOES ~ 1N4002
05 ~ 2N2222A

Figure 17. Adding a Speakerphone Booster

The circuit is the same as in Figure 10, but with the
addition of 05, the 20 k and 47 n resistors, 2 diodes, the
1000 /-LF capacitor, and the power supply connector for
the ac adapter. The zener diode is changed to 5.6 volts
to provide slightly more voltage to the MC34018 when
the ac adapter is not used (at higher loop currents). The
47 n resistor provides short circuit protection for the
ac adapter, and also aids in filtering 60 Hz ripple from
the MC34018.
At low loop currents, and with the adapter plugged in,
and the circuit in the speakerphone mode (HS2 as shown
in Figure 17), Dl is reverse biased by the adapter's higher
voltage. All of the speakerphone's current is now supplied by the ac adapter. 05 is on, allowing the excess
loop current to flow through the MC34114's LR pin, The
dc characteristics at Tip & Ring are similar for the handset
mode and the speakerphone mode.
At higher loop currents, the dc characteristics of the
two modes will differ slightly as some of the MC34018's
current may be supplied by the loop.

MOTOROLA COMMUNICATIONS DEVICE DATA

Without the adapter plugged in, the circuit will act the
same as that of Figure 10. Diode D2 prevents 05 from
being turned on.
In the handset mode, the circuit operates the same as
that in Figure 10 when it is in the handset mode.
The Complete Circuit with the Booster
The complete circuit is shown in Figure 18. A quick
comparison shows it is identical to that of Figure 10,
except for the booster section in the lower right hand
corner. The performance curves for this circuit are
shown in Figures 19-24. As can be seen in Figures 20
and 23, the speakerphone's performance does not
degrade below 30 mA as had happened in Figures 12
and 15. The muting specs for this circuit are the same
as for Figure 10.

AN1002
4-109

HSI

~l>

':'Z
......

..

00

g

~

N4742
12V

lR

~33

1R*

1 Vcc

43,IW

~

RAGC

820

lWiT'

VSS

• 1

r

MC145412

~

lOOk

OIALER

KEYPAD

16. Rl
15
14

OTMF I..

Vool.

==:J

1-!'

VB
22

SPEECH
NETWORK

J11

3.9NFI

i, (

0.111

1M

GNO

MC34114

c:.:::TOQ4

..

~ 14, 1

I

HANDSET
MIKE
MUTE

3.9 k
,.

ZB

141 RXA

n

RXI

Mca

L_

1-

~

MC33171 Lj~

47nF

.= 1 1

~~.

1~:.

-- I

1--

L·..

_.~~ 'M",'-

,;:. 1

... X·

.:, 1

1::..

lH
14211)
116
V+ I ,

1°00

;s:

"

I , 14

T

lN4734
III

~6V

@

~

HS2

13,
114W

8;s:

47
RTXIRRI

;s:

c

z

o
:!'.j
o
z
en

o
m

o!'l
MUTE

>----vvv--f"

~MUTE

lOOk

Figure 18. PulsefTone Featurephone w/Memory -

Line Powered w/Booster

MC34114/MC34018 Line Powered (w/Booster) Featurephone

14

2. 2

I
I

./
HANDSET MODE (TONE DIALING)
HANDSET MODE
(SPEECH, PULSE DIALING)
'\

-

,
V

;;..-

.,..-

",..-

--

V

~~ / '

/

./""

V

.........

~

~

V

~1.

'-...

/

~

,,!SPEECH/PULSE DIALING)
(TOlE DIAliNG)

o
>

40

60
80
LOOP CURRENT (rnA)

.....

38

.'\.
SPEAKERPHONE MODE

36

--

i'..

"

_ILOOP
32

"

T--.

SPEAKERPHONE MODE

+24
_+22

120

-

r--

V

100

300

lK
FREQUENCY (Hz)

4K

r--

+22t--r-+--t-+-rti;+t~+-~~~r+-rrr~

! -lll---t-t--+-+-rt++++-~--I--I---r_-++H-+-H

~+1 8

~

.........

-

61--~~-t-t-++t~~+-+--+-+~~+-H

HANDSET MODE

~
-1 o f = 1 kHz
-1 2 GAIN IS FROM TIP/RING TO RECV'R/SPKR.
40
60
80
20
LOOP CURRENT (rnA)

V

Figure 22. Transmit Gain versus Frequency

'"

8

= 30 rnA

30
100

~+20

...........

V

1/

Figure 21. Transmit Gain versus Loop Current

r---.....J.

= 40 rnA

~ 34 -HANDSET MODE

f = l\Hz I.
........
30 GAIN IS FROM MIKE TO TIPIRING
20
40
60
80
LOOP CURRENT (rnA)

6

120

100

z

...... 1--.

~,

SpJKER~HONJ M6DE
ILOOP

~ 36

.......

HANDSET MODE

+26

I

60
60
LOOP CURRENT (rnA)

40

40

38

+28

--r-

Figure 20. Max. Speaker Amplifier Output and DTMF
Level versus Loop Current

40

+30

DTMF LEVEL AT TIP/RING

I

20

Figure 19. Tip to Ring DC Voltage versus Loop Current

32

"""'--

o. 2

120

100

"

o.4

4
20

~

o. 6

I

./

I

SPEAKER AMP. MAX.
OUTPUT SWING

1.8

~

",..-

"--' --s.: ~ VI\. SPEAKERPHONE MODE

V

2

I
I

-

100

Figure 23. Receive Gain versus Loop Current

MOTOROLA COMMUNICATIONS DEVICE DATA

_~ANDSET MODEHio"'t-++++---t-+--t~-+-t-l1-+-H
ILOOP = 30 rnA ;/
120

100

300

lK
FREQUENCY (Hz)

4K

Figure 24. Receive Gain versus Frequency

AN1002
4-111

USING A POWER SUPPLY INSTEAD OF
LINE POWER
Using A Transformer
For those cases where it is desireable to power the
featurephone from a regulated power supply, rather than
from loop current, a transformer is required to provide
the isolation needed between the phone line and any ac
power and earth ground. The primary change to the circuit of Figure 10 is in the area of the Tip & Ring interface,
as shown in Figure 25. It must be remembered· that loop
length compensation is not possible in this circuit since
the loop current is not monitored. The MC34114's RAGC
pin is grounded in this circuit, setting the transmit and
receive gains to maximum.

~~~RING

Figure 25. Tip/Ring Interface with a Power Supply
The +9 volt supply powers the MC34114 through the
transformer winding. In this manner the speech signals
are coupled between the MC34114 and TIp/Ring. The two
diodes provide transient clamping; as does the 12 volt
zener diode. The MC34018 is powered directly from the
+9 volt supply, eliminating the need for the 1H choke.

The SS switch (speakerphone on/off) requires one more
pole now, as shown in Figure 25. (Note: Although a +9
volt supply' is shown, a lower voltage supply could be
used as well.)
Changes in the Dialer and Logic Circuit
To reduce the parts count of the logic portion of the
previous circuits, Q1-Q3 were replaced with logic gates.
A triple 3-input AND gate, with open collector outputs
(74LS15), 'fulfills the requirements of Tables.1 and 2. (The
use of an LSTTL logic gate was not feasible in the previous two circuits due to the current consumption of the
LS device.) The 5 volt power for the gates is derived from
the +9 volt supply using a 1N4733 zener diode. Since
the dialer's mute output drives the gate inputs, it is necessary to power the dialer from the same + 5 volt supply,
rather than the MC34114's VDD supply. The resulting
logic circuit is shown in Figure 26.
The use of the logic gate also simplifies the selection
of handset versus speakerphone mode of operation. The
diversion of the excess loop current is not an issue in this
circuit, so the switching of that current is eliminated,
along with Q4. The Mike Mute function can now be provided from a single pole switch, rather than the two pole
switch of the previous circuits.
With this circ,uit, the handset operated switch (HS)
remains a 3-pole switch.
Because of the isolation requirement, the MC145412
dialer requires a relay to break the loop current during
pulse dialing. Figure 27 depicts this circuit.
The relay is normally off, and energized only for the
pulse dialing function. The 1 p,F capacitor (rated 250 volts
min., NPO) helps absorb the transients generated during
pulse dialing.

+9V

Rrsp

TRANSMIT

L--~;;;:';;;:::;::;:w--lr-- ITg~:~'4
0.1

MC145412

TXI-PIN 101

10k

11

Mli 1--4--MiJrESiGN;ijL----;=!:::=~t::r}_-------I~

v ,"_ _--I

TO MC34114
MT-PIN11

HS3 SHOWN ON·HOOK

Figure 26. Switching Modes Using Logic Gates

AN1002
4-112

MOTOROLA COMMUNICATIONS DEVICE DATA

~j~~~____~+~9V
TO MC34114

RING

Vee (PIN 11

MC145412

100k

OPL 17

Figure 27. Pulse Dialer Circuit

The Complete Circuit with the Power Supply
The complete circuit is shown in Figure 28. The performance curves are shown in Figures 29-34. The Tip to

MOTOROLA COMMUNICATIONS DEVICE DATA

Ring dc voltage (Figure 29), determined solely by the dc
resistance ofthe transformer winding, is somewhat lower
than in the previous circuits. Figures 30, 31, and 33 show
the performance is fairly constant with loop current,
except for a slight reduction in gain at the higher currents.
This is due to the characteristics of the transformer used
in developing this circuit (model #TTPC-13 from Stancor,
Inc.). Also noticeable in the curves, compared to Figures
11-16 and 19-24, is the lack of loop length compensation
- a natural consequence of this type of circuit.
The muting specifications for this circuit are the same
as for the line powered circuit. The current required from
the +9 volt power supply is as follows:
a) Handset mode: =32 mA.
b) Speakerphone mode (no sound at the speaker):
=41 mA.
c) Speakerphone mode (max. volume at the speaker):

=82 mAo
Although Figure 28 indicates the use of a 25 ohm
speaker, any impedance speaker within the range of 16
to 40 n can be used, since this circuit is not line powered.
The receive gain may have to be adjusted, however, if a
different speaker is used.

AN1002
4-113

"'"l>
......
.!.z
","0

fG

HSI

Rl1

TIP

RINGV--+-.-------'·
RAGC
VR

VB

MC34114
GNO

SPEECH
NETWORK

MCI
KEYPAD

112

OTMFL
VOO I.'

I,

INPUT

+

I"

MC2

~ TOOTMF
ZB

<+5

RXA

10k

'~MO

MOI"
1M

Me33171

s::
o

Va

d

el

>

8
s::
s::
c
z

5

~

5z

en

c
~
5m
c
~
l>

24k

Notes:
1) All capacitors in f'F except
where noted.
2) HS = Handset operated hookswitch - 3 poles.
55 = Speakerphone on/off switch - 2 poles.
Switches shown in on-hook position.
3) All diodes in 1N4002.
4) These resistors depend on the specific microphones.

Figure 28. Pulserrone Featurephone w/Memory -

11k

+5

Powered From a Power Supply

0.1

MC34114/MC34018 Featurephone w/Power Supply

2.6

10

en

".

!:;

V

0

>

u

,,- V

ew

'"~

/

'"a:z

/

~

/'

~

V
o
20

40

2

!5.

~

o
> 0.6

".

THIS GRAPH APPLIES
TO ALL MODES OF
OPERATION
TRAINSFOR~ER =1 STAN~OR n~C.13

60
80
LOOP CURRENT (mAl

100

DTMF LEVEL AT TIP/RING

0.4

I

0.2

120

20

60
SO
LOOP CURRENT (mAl

40

40

120

100

40

38

SPEAKERPHONE MODE
38 i-ILOOP 40 rnA

SPEAKERPHONE MODE

36

I

as 36
:E

z

z

~34

~ 34

20

40

60
80
LOOP CURRENT (mAl

100

120

30
100

Figure 31. Transmit Gain versus Loop Current

+30

II

V
300

lK
FREQUENCY (HzI

+30
+26 _

SPEAKERPHONE MODE -

S~EAK~RPHdNE ~OJE
ILOOP = 40 rnA

.+24

r--...

'"

/

+22

~+20
~+18
-6
-8

4K

Figure 32. Transmit Gain versus Frequency

+28
+26

~

1/
32 I- ~ANDSET MODE
ILOOP = 30 rnA

f = 1kHz
GAIN IS FROM MIKE TO TIP/RING

30

/

HANDSET MODE

32

'"

I
I

Figure 30. Max. Speaker Amplifier Output and DTMF
Level versus Loop Current

Figure 29. Tip to Ring DC Voltage versus Loop Current

~

SPEAKER AMP. MAX.
OUTPUT SWING

2.2

en'
:=;;

/

0

>

I

2.4

-10 f = 1 kHz
-12 GAIN IS FROM TIP/RING TO RCV'R/SPKR.
60
SO
20
40
LOOP CURRENT (mAl

100

Figure 33. Receive Gain versus Loop Current

MOTOROLA COMMUNICATIONS DEVICE DATA

-

HANDSET MODE
-10 -ILOOP = 30 rnA
".
I I
V

HANDSET MODE- -

120

-14
100

300

lK
FREQUENCY (HzI

4K

Figure 34. Receive Gain versus Frequency

AN1002
4-115

CONSTRUCTION HINTS
Board Layout
The filter capacitor for the MC34018 speakerphone IC
(typically 1000 p.F) must be physically adjacent to Pin 16
of the IC, within 1". This is particularly important in the
line-powered versions, where VCC can vary with the
speech intensity. Since most of the current is used in the
speaker amplifier, the PC board track leading to Pin 16 of
the MC34018 should be laid out with care, preferably
close to the zener diode, or the power supply connector.
The ground tracks should be as wide as possible, and
laid out with care.
EMI Susceptibility
Potential EMI susceptibility problems should be
addressed early in the electrical and mechanical design
of the speakerphone. EMI may enter the circuit through
Tip & Ring, through the microphone wiring to the amplifiers, or through any of the PC board traces. The most
sensitive pins on the MC34108 are the inputs to the level
detectors (RLI, TLI), since, when there is no speech present, the inputs are high impedance and these op amps
are in a near open loop condition. These board traces
should be kept short, and the resistor and capacitor for
each input should be physically close to the pins. Other
high impedance input pins (MCI; VLC) should be considered sensitive to EMI signals.
The microphone wires within the handset cord can act
as an antenna, and pick up nearby radio stations. If this
is a problem in the final design, adding RF filters (consisting of ferrite beads and small (0.001 p.F) ceramic
capacitors) to the PC board where the wires attach to the
board can generally reduce the problem.
Acoustics
a) In the design of any speakerphone, acoustics are
extremely important, and must be considered from the
very beginning. Building a breadboard with the microphone and speaker "hanging out in mid air" simply will
not workl!! One of the most common problems in a
speakerphone design is acoustic feedback (the speaker
is closely coupled to the microphone) which results either
in oscillations (2-10 kHz) or "motor-boating" (1-10 Hz
switching). A properly designed enclosure for the finished product should provide at least 50 dB of acoustic
loss (speaker drive voltage to microphone output voltage). The physical location ofthe microphone, along with
the characteristics of the microphone, will playa large
role in the quality of the transmitted sound. The microphone and speaker vendors can usually provide additional information on the use of their products.
b) The quality of the speaker, and the acoustic cavity
in which it resides, have a major impact on the quality
of the sound. A little time spent here can go a long way
towards improving the sound of the finished speakerphone. As a general rule, good electronics cannot compensate for poor acoustics and/or low speaker quality.
In the Final Analysis ...
In the final analysis, the circuits shown in this application note will have to be "fined tuned" to match the

AN1002
4-116

acoustics of the enclosure, and the specific microphone
and speaker selected. The component values shown in
this application note should be considered as starting
points only. The gains of the transmit and receive paths
are easily adjusted at key points in the circuits (see appropriate text). The switching responseofthe speakerphone
can then be fine tuned by varying (in small steps) the
components at the level detector inputs until satisfactory
operation is obtained for both long and short lines. The
references can be consulted for additional speakerphone
design theory.

GLOSSARY
Attenuation - A decrease in magnitude of a communication signal, usually expressed in dB.
Bandwidth - The range of information carrying frequencies of a communication system.
C-Message Filter - A frequency weighting which evaluates the effects of noise on a typical subscriber's system.
Central Office - Abbreivated CO, it is a main telephone
office, usually within a few miles of its subscribers, that
houses switching gear for interconnection within its
exchange area, and to the rest of the telephone system.
A typical CO can handle up to 10,000 subscriber numbers.
dB - A power or voltage measurement unit, referred to
another power or voltage. It is generally computed as:
10 x log (P11P2) for power measurements, and
20 x log (V1N2) for voltage measurements.
dBm-An indication of signal power. 1 mW across 600 n,
or 0.775 volts rms, is defined as 0 dBm. Any other voltage
level is converted to dBm by:
dBm = 20 x log (Vrms/0.775), or
dBm = [20 x log (Vrms)] + 2.22.
dBmp - Indicates dBm measurement using a psophometric weighting filter.
dBrn - Indicates a dBm measurement relative to 1 pW
power level into 600 n. Generally used for noise measurements,O dBrn = -90 dBm.
dBrnC - Indicates a dBrn measurement using a Cmessage weighting filter.
dBrnCD - Noise measured in dBrnC referred to zero
transmission level.
DTMF - Dual Tone Multi-Frequency. It is the "tone dialing" system based on outputting two non-harmonic
related frequencies simultaneously to identify the number dialed. Eight frequencies have been assigned to the
four rows and four columns of a typical keypad.
Four Wire Circuit- The portion of a telephone, or central
office, which operates on two pairs of wires. One pair is
for the Transmit path (generally from the microphone),
and one pair is for the Receive path (generally to the
receiver).
Full Duplex -A transmission system which permits communication in both directions simultaneously. The standard handset telephone is full duplex.

MOTOROLA COMMUNICATIONS DEVICE DATA

Gain - The change in signal amplitude (increase or
decrease) after passing through an amplifier, or other
circuit stage. Usually expressed in dB, an increase is a
positive number, and a decrease is a negative number.
Half Duplex - A transmission system which permits
communication in one direction at a time. CB radios, with
"push-to-talk" switches, and voice activated speakerphones, are half duplex.
Hookswitch - A switch which connects the telephone
circuit to the subscriber loop. The name derives from old
telephones where the switch was activated by lifting the
receiver off and onto a hook on the side of the phone.
Line Length Compensation - Also referred to as loop
compensation, it involves changing the gain of the transmit and receive paths, within a telephone, to compensate
for different signal levels at the end of different line
lengths. A short line (close to the CO) will attenuate signals less, and therefore less gain is needed. Compensation circuits generally use the loop current as an indication of the line length.
Loop - The loop formed by the two subcriber wires (Tip
and Ring) connected to the telephone at one end, and
the central office (or PBX) at the other end. Generally it
is a floating system, not referred to ground, or ac power.
Loop Current - The dc current which flows through the
subscriber loop. Typically provided by the central office
or PBX, it ranges from 20 to 120 mA.
Off Hook - The condition when the telephone is connected to the phone system, permitting the loop current
to flow. The central office detects the dc current as an
indication that the phone is busy.
On Hook - The condition when the telephone is disconnected from the phone system, and no dc loop current
flows. The central office regards an on-hook phone as
available for ringing.
PABX - Private Automatic Branch Exchange. In effect, a
miniature central office, it is a customer owned switching
system servicing the phones within a facility, such as an
office building. A portion of the PABX connects to the
Bell (or other local) telephone system.
Pulse Dialing - A dialing system whereby the loop
current is interrupted a number of times in quick
succession. The number of interruptions corresponds
to the number dialed, and the interruption rate is typically 10 times per second. The old rotary phones, and
many new pushbutton phones, use pulse dialing.

REN - Ringer Equivalence Number. An indication of the
impedance, or loading factor, of a telephone bell or ringer
circuit. An REN of 1 equals =8 k ohms. The Bell system
typically permits a maximum of 5 REN (1.6 kO) on an
individual subscriber line. A minimum REN of 0.2 (40 kO)
is required by the Bell system.
Ring - One of the two wires connecting the central office
to a telephone. The name derives from the ring portion
of the plugs used by operators (in older equipment) to
make the connection. Ririg is traditionally negative with
respect to Tip.
Sidetone- The sound fed back to the receiver as a result
of speaking into the microphone. It is a natural consequence of the 2-to-4 wire conversion system. Widetone
was recognized by Alexander Graham Bell as necessary
for a person to be able to speak properly while using a
handset.
Speech Network - A circuit which provides 2-to-4 wire
conversion, i.e. connects the microphone and receiver
(or the transmit and receive paths) to the Tip and Ring
phone lines. Additionally it provides sidetone control,
and in many cases, the dc loop current interface.
Subscriber Line - The system consisting of the user's
telephone, the interconnecting wires, and the central
office equipment dedicated to that subscriber (also
referred to as a loop).
Tip - One of the two wires connecting to the central
office to a telephone. The name derives from the tip of
the plugs used by operators (in older equipment) to make
the connection. Tip is traditionally positive with respect
to Ring.
Tone Ringer - The modern solid state equivalent of the
old electromechanical bell. It provides the sound when
the central office alerts the subscriber that someone is
calling. Ringing voltage is typically 80-90 Vrms, 20 Hz.
Two-Wire Circuit - Refers to the two wires connecting
the central office to the subscriber's telephone. Commonly referred to as Tip and Ring, the two wires carry
both transmit and receive signals in a differential manner.
Voiceband - That portion of the audio frequency range
used for transmission across the telephone system. Typically it is 300-3400 Hz.

REFERENCES
MC34018 Data Sheet, March, 1988, Motorola Inc.
MC34017 Data Sheet, January, 1984, Motorola Inc.
MC34114 Product Preview Data Sheet, Sept. 1987,
Motorola Inc.
MC33171 Data Sheet, February, 1988, Motorola Inc.
MC145412 Data Sheet, February, 1987, Motorola Inc.
Busala, A., Fundamental Considerations in the Design
of a Voice Switched Speakerphone, B.S.T.J., 39,
1960, p. 265.

MOTOROLA COMMUNICATIONS DEVICE DATA

AN1002
4-117

SUGGESTED VENDORS

Microphones
Primo Microphones Inc.
Bensenville, III. 60106
312-595-1022
Model EM-60

MURA Corp.
Westbury, N.Y. 11590
516-935-3640
Model EC-983-7

Hosiden America Corp.
Elk Grove Village, III. 60007
312-981-1144
Model KUC2123

25 n Speakers
Panasonic Industrial Co.
Seacaucus, N.J. 07094
201-348-5233
Model EAS-45P19S

Telecom Transformers
Microtran Co., Inc.
Valley Stream, N.Y. 11528
516-561-6050
Various models - ask for
catalog and Applications
Bulletin F232
PREM Magnetics, Inc.
McHenry, III. 60050
815-385-2700
Various models - ask
for catalog

Stancor Products
Logansport, IN 46947
219-722-2244
Various models - ask
for catalog

Onan Power/Electronics
Minneapolis, MN 55437
612-921-5600
Model TC 38-6

Motorola Inc. does not endorse or warrant the
suppliers referenced.
Compliance with FCC or other regulatory agencies of
the circuits described herein is not implied or
guaranteed by Motorola Inc.

AN1002
4-118

MOTOROLA COMMUNICATIONS DEVICE DATA

MOTOROLA

-

SEMICONDUCTOR
APPLICATION NOTE

AN1003

A Featurephone Design, with Tone Ringer and
Dialer, Using the MC34118 Speakerphone IC
Prepared by
Dennis Morgan
Bipolar Analog Ie Division

INTRODUCTION
This application note describes how to add a handset,
dialer and tone ringer to the MC34118 speakerphone circuit. Although anyone of several speech networks could
be used as an interface between the MC34118 and the
phone line (those possibilities are discussed in separate
application notes) this application note covers the case
where simplicity and low cost are paramount. A "Privacy" (Mike Mute) function is included, but not pulse
dialing, nor line length compensation.
Two circuits are developed in this discussion: a linepowered featurephone and one powered from a power
supply. The circuits are nearly identical, except for the
Tip and Ring interface. Their parameters however, differ
noticeably, particularly in the low loop current range.

MC34118 DESCRIPTION
The MC34118 speakerphone IC provides all of the necessary functions for a complete speakerphone circuit,

except for the speaker amplifier, in a single integrated
circuit. Included are the transmit and receive attenuators,
which operate in a complementary manner, to provide
the half-duplex function. The four level detectors, in conjunction with the background noise monitors and the control algorithm, provide a four point sensing and decision
making system to control the attenuators based on the
levels and timing of the transmit and receive signals. A
filter, user selectable to be high pass, low pass, or bandpass, is included for filtering either the transmit or receive
signals. Additional functions include volume control for
the receive path, a Mute input for the microphone amplifier and a chip disable pin. A simplified block diagram is
shown in Figure 1.
Unlike many other speakerphone ICs, the MC34118
includes the hybrid amplifiers for the two-to-four wire
conversion when used in conjunction with a transformer.
Figure 2 depicts a basic line powered speakerphone using
the MC34119 speaker amplifier. When used in parallel
with any standard telephone, all of the necessary telephone functions are then provided.

TIP

MIKE

(

RING

r - -..........J\~VCC

CHIP
DISABLE

Figure 1. Simplified Block Diagram

MOTOROLA COMMUNICATIONS DEVICE DATA

AN1003
4-119

"":I>
':'Z

Vee

1\)'"

00

8

lk

20/LF

r

INot.1J<

VB

620
43k

TXO
8

MIKE

Vee

Tx

RING

AffiNUATOR
MUTE}

Vee

12
MUT

5/LF~U·~14
120 k

s::

~

VB

1\

220 /L F

_

RlI2120

RXO

I. .

_v. 1.. _ I,"

.,,_1_..

,

+
56k

::0

o

s;:

8
s::
s::
c
z

f)

~
(5
z
en
o

Notes:
1. These two resistors depend on the specific microphone selected.
2. BNM = Background Noise Monitor; OTO :::: Dial Tone Detector
3. All capacitors in p.F unless otherwise noted.

~

f)

m

o

»~

Figure 2. Basic Line-Powered Speakerphone

Figure 4, to drive it. The MC33171 was chosen due to its
low supply current (typically 180 p.A). It is biased from
VB and set for a gain of =0.43 (-7.3 dB). Low frequency
roll-off is provided by the 0.047 p.F input capacitor, as
well as by the filter. High frequency roll-off is not provided
since the presence of high frequencies generally make
the sound "crisper" and therefore easier to understand.
If roll-off is desired, simply add a capacitor across the
4.3 k feedback resistor.
The addition of the op amp facilitates providing sidetone control, which is obtained by sampling the transmit
signal at HTO - (Pin 6) and using that to cancel part of
the sidetone signal. The 20 k resistor and 0.02 p.F capacitor provide a phase shift to compensate for the signal's
phase shift at FO relative to HTO -, caused by the ~rans­
former and the line's complex impedance. The c'ombination of the phase shift and the 10 k resistor (RS) determine the amount of sidetone cancellation.
Since the op amp is driving an inductive receiver at the
end of a 2 to 3 foot cord, the 0.01 p.F capacitors at the
inputs are necessary for stability.
The diode provides a simple means for disabling this
circuit during speakerphone operation. With "Shutoff" at
ground, the amplifier is disabled.

LINE-POWERED FEATUREPHONE
DC Characteristics
The DC characteristics of the circuit (Figure 2) are
determined by the resistance of the transformer winding (Stancor TTPC-13 in this circuit development), the
diode bridge and the zener diode. Using a 3.9 volt zener
diode (to power the speakerphone and the various parts
of the circuit) the voltage at Tip and Ring is within the
EIA,470 guidelines.
With a VCC of 3.9 volts, the MC34118 provides a VB
voltage (Pin 15) of =1.6 volts. The VB voltage is used as
an AC ground for the entire circuit.
Adding the Handset Microphone
The microphone used in developing this circuit was the
Primo EM-95 which operates with a bias current of 500 pA
to 1 mA. The bias current is obtained from the VCC supply
voltage, but the bias resistor is composed of two resistors, with the center tap AC coupled to VB, as shown in
Figure 3. The AC output level of the microphone is determined by the 3.9 kO resistor, while the DC bias level is
determined by the sum of the 3.9 k and 3 k resistors, and
VCC. The 0.047 p.F capacitor provides high frequency rolloff. The AC output of the above circuit goes to Pin 7 (HTIl
of the MC34118, which is the summing junction of the
first hybrid amplifier. The 1 k resistor, in conjunction with
the 100 k feedback resistor on the amplifier (Figure 3),
sets the gain. In this way, the microphone signals are fed
to Tip and Ring. The gain of this circuit can be adjusted
by varying the 1 k or the 3.9 k resistor, or both. Different
microphone models generally have different biasing
requirements for optimum output levels.
The transistor, activated by an active high Mute signal, will shut off the microphone when it is to be inoperative, such as during dialing and during speakerphone operation.

VCC
3k

0.047 p.F
TO MC34118
PIN 7

MUTE >--'III~-r

Adding the Handset Receiver
Although the receive signals are available at the filter's
output (FO, Pin 1), the low impedance of a typical receiver
(100-150 0) requires a separate amplifier, depicted in

Figure 3. Handset Microphone Circuit

FROM HTOIPIN 6)

INPUT FROM
FO IPIN 1)

r

0.047
p.F

RS

}
'~l-'
*
0.02

10 k

p.F
10 p.F

-

SHUTOFF
VB

SIDETONE
CANCELLATION

4.3 k

MC3317t1

HANDSET
RECEIVER

-=
Figure 4. Handset Receiver Circuit

MOTOROLA COMMUNICATIONS DEVICE DATA

AN1003
4-121

Adding the Dialer
The dialer is the MC145412 pulse/tone dialer with 10
number memory. Since the pulse dialing function is not
used, the MS pin is grounded and the OPL (Outpulsing)
and TSO (Pacifier tone) outputs are not used. The circuit
uses a standard 3.58 MHz crystal and standard 3 x 4 or
4 x 4 keypads.

To provide the logic functions and with the intent of
keeping the number of mechanical switches to a minimum and simplicity at an optimum, an MC14023 triple
3-input CMOS NAND gate was used. See Figure 6.
TO RECEIVE
PATH MUTE
VCC

MC145412
DIALER
OH

R1

VDD

TO lOGIC
CIRCUIT

Mli

15
14
13

DTMF
VCC

KEYPAD
16

1 2 3 A

MO (FROM
DIALER)

TO HANDSET
MICROPHONE
MUTE INPUT

>-......-1--1

TO SPEAKERPHONE
MIKE MUTE
(MC34118 PIN 12)

4 5 6
7 8 9

VCC

• 0 #

!

MIKE MUTE
(PRIVACY)

HANDSET
~-= MODE SELECT
SWITCH
SPEAKERPHONE

Figure 5. Dialer Circuit

TO SPEAKER AMP ENABLE
AND HANDSET RECEIVER SHUTOFF

Referring to Figure 5, the NPN transistor at Pin 12
indicates the on-hookloff-hook status to the IC. Power
for the dialer is VCC, diode connected with a memory
sustaining battery. The DTMF output goes to Pin 7 (HTI)
of the MC34118, which is the summing junction of the
first hybrid amplifier. The 82 k resistor, in conjunction
with the 100 k feedback resistor on the amplifier, determines the gain. With the values shown, the DTMF output at Tip and Ring is approximately 550 mVrms
(- 3 dBm). To change the output level, vary the 82 k
resistor appropriately.
The Mute Output (MO) is active low, open drain and'
pulls to ground while dialing. It is used to mute the speech
paths during dialing.
Switching the Circuit Around
The logic functions involve: a) switching the circuit
from handset mode to/from speakerphone mode,
b) switching in and out ofthe dialing mode while in either
handset or speakerphone mode and c) muting the two
microphones for the "Privacy" function. Table 1 tabulates
the requirements:

Figure 6. Logic Circuit
The inputs are the Mute Output (MO) from the dialer
(described above), the Mike, Mute switch and the Mode
Select switch. The outputs are:
1. An active low output which enables the MC34119
speaker amplifier (at its Pin 1) and disables the handset receiver;
2. An active high output which disables the speakerphone microphone atthe MC34118's Pin 12 (MUT);
3. An active high output which disables the handset
microphone;
4. An active high output which partially mutes the
receive path during dialing. The circuit which does
the partial muting is shown in Figure 7.

FROM
TRANSFORMER

Table 1.
Handset
Function

Speakerphone

Mike

R'cvr

Mike

Speaker

Handset Speech
Handset Dialing
Handset Mike Mute

On
Off
Off

On
Mute
On

Off
Off
Off

Off
Off
Off

Speakerphone Speech
Speakerphone Dialing
Speakerphone Mike Mute

Off
Off
Off

Off
Off
Off

On
Off
Off

On
Mute
On

In Table 1, "ON" means fully functional, "OFF" means
non-functional and "MUTE" means partially muted (10
to 20 dB).

AN1003
4-122

FROM
LOGIC
CIRCUIT

Figure 7. Receive Path Muting

MOTOROLA COMMUNICATIONS DEVICE DATA

The muting circuit, consisting of the transistor and the
3 k and 10k resistors, is inserted in the line from the
transformer to the filter. Normally the transistor is off and
the 10 k resistor has little effect on the circuit due to the
high input impedance of the filter (>200 kn @ 1 kHz).
When Mute is asserted, the signal to the filter is muted
by =12.7 dB.
The MC34118's Disable pin (Pin 3) is hard wired to
ground since the MC34118 must be functional for both
the speakerphone and handset modes.
Adding the Tone Ringer
The MC34017 tone ringer circuit, shown in Figure 8, is
added to the circuit by simply connecting it across Tip
and Ring. It is not necessary to disconnect the tone ringer
when off-hook. This circuit will provide a ringer with an
REN of =1 and meet all the EIA-470 and Bell System
requirements for impedance, anti-bell tapping and tumon/off thresholds.
Finally, the Complete Circuit
The complete line-powered featurephone is shown in
Figure 9. HS1 and HS2 are the two poles of the hookswitch activated by lifting the handset off-hook (HS2 is
the Mode Select Switch of Figure 6). SS1 is a single pole
switch which, when closed (and the handset is on-hook),
powers up the circuit into the speakerphone mode.
Should the handset be taken off-hook, the circuit reverts
to the handset mode.
The performance curves for the circuit are shown in
Figures 10-15. The "Speaker Amp Max Output Swing"
is the maximum rms voltage available across pins 5 and
8 of the MC34119 without noticeable clipping. The transmit gain tests involved replacing each microphone with
a signal generator and adjusting for a level of approximately -11 dBm at Tip and Ring into a 600 n resistive
load. The receive tests involve applying approximately
- 27 dBm to Tip and Ring, and measuring the gain to the
receiver or speaker.

As can be seen in Figure 11, the maximum available
speaker power is a function of the loop current since all
of the speaker current must come from the loop. Consequently, the receive gain for the speakerphone
(Figure 14) shows a marked decrease at low loop currents. It must be remembered that in a line powered
speakerphone, as the speaker draws current in response
to a receive signal, the voltage at Tip and Ring decreases
quickly. As VCC falls with the Tip and Ring voltage, not
only is the speaker amp's output capability reduced, but
the MC34118's AGC circuit automatically reduces the
receive gain as Vce falls below 3.5 volts. This feature
prevents slow oscillations (motor-boating) due to the
speaker's current demands. A 25 n speaker is recommended as this makes the best use of the power available
from the phone line. A lower impedance speaker will
require more current, causing Vec to sag further for a
given signal level. A higher impedance speaker draws
less current, but produces less sound power.
The slight degradation of DTMF levels in Figure 11 and
in the transmit levels in Figure 12, at higher loop currents
is a function of the transformer's performance at those
current levels.
Additionally, the following muting specs apply:
1. Handset microphone: =37 dB while dialing, in
speakerphone mode, or when Mike mute switch is
closed.
2. Speakerphone microphone: >60 dB while dialing
or due to Mike Mute switch, plus an additional 52 dB
due to the MC34118 switching to the receive mode.
>60 dB while in the handset mode.
3. Handset receiver: =12.7 dB while dialing, =45 dB
when in the speakerphone mode.
4. Speaker: =12.7 dB while dialing, >100 dB when in
handset mode.

TIP
RG

RING

RC

MC34017

TONE RINGER

TO TELEPHONE
CIRCUIT
PIEZO

Figure 8. Tone Ringer Circuit

MOTOROLA COMMUNICATIONS DEVICE DATA

AN1003
4-123

!~

KEYPAD

N~§

Rl~

MO

14

VCC

13

51'F

s:1
Sl

~I

*
I VCC

VB
RlI2120

221
RXO

VLC 1'3

211 261RlIi
RXI

t=

0
0

-,u.u"'

0.11

s:
s:
c
z

TO

4700PU ~
~.~~ ~~

F~'•

S;
()

A

1§.

_"""T'"-

,.,-,HTO-

-

20k

.......

10

HANDSET
RECEIVER

(')

?:j

5z

Notes:

0

!;l!

1.
2.
3.
4.
5.

(')

6. See Figures 10-15.

en
m

0

~

l>

These resistors depend on the specific microphone selected.
These capacitors must be physically adjacent to the power supply pins.
Recommended transformer: Stancor TTPC·13. Microtran T5115.
HS = Handset Operated Hookswitch (2 poles), 55 = Speakerphone Switch (1 pole). Switches shown on-hook.
All capaCitors in JLF unless otherwise noted.

Figure 9. Line-Powered Featurephone

~MO

MC34118 Line Powered Featurephone
4

1.8

,/
,/

2
0

V

V

/

1.6

'"

u; 1.2

/

::;;

en

/

!:;

~ O.B

./

/

0.6

6/
40

60
80
LOOP CURRENT IrnAI

1

/
O. 2

4

20

DTMF LEVEL AT TIP/RING

/

0.4

_ APPLIES TO BOTH HANDSET AND SPEAKERPHONE MODES
f--- INO SIGNAL AT SPEAKEm

~AX / '

AMP
OUTPUT SWING

$.

",/

8

S~EAKE~

_

-

1.4

100

20

120

40

60
80
LOOP CURRENT IrnAI

100

120

Figure 11. Speaker Amp. Output and DTMF Level
versus Loop Current

Figure 10. Tip to Ring DC Voltage versus Loop Current

2

2

40

SPEAKERPHONE MODE

0

38

38

m 34

SPEAKERPHONE MODE

I-- ILOOP = 40 rnA '"

I"

6

m
:!<

:!<

«

«

z 32

z

HANDSET MODE

'" 24
22

r-f = 1 kHz

I

I

GAIN IS FROM MIKE TO TIP/RING

20
20

40

60
80
LOOP CURRENT IrnAI

---

'" 30
8
24
100

120

+30

4EAKER~HONEIMODE

+26

V

+24

/

m +22

f = 1 kHz
GAIN IS FROM TIP/RING TO RECV'R/SPKR.

/

:!<

z +20

«

= 40 rnA

V

m +22

:!<

z

6

~ -8

'" +18
-6

-1 O -

-

-8
-10
-12
20

HANDSET MODE
40

60
80
LOOP CURRENT IrnAI

100

Figure 14. Receive Gain versus Loop Current

MOTOROLA COMMUNICATIONS DEVICE DATA

4k

1k
FREQUENCY IHzl

~pJKERP~ON~ M~JE

+26 _ILOOP

1

'f

300

Figure 13. Transmit Gain versus Frequency

'THIS REGION NOT RECOMMENDED FOR SPEAKERPHONE USE

+28

r-

22

100

Figure 12. Transmit Gain versus Loop Current

+30

HANDSET MODE
ILOOP = 30 rnA

26

120

-12 -14
-1 6
100

.......

r- HANDSET MODE

......-

r- ILOOP = 30 rnA

1-

I 1Y

lA
300

1k

4k

FREQUENCY IHzl

Figure 15. Receive Gain versus Frequency

AN1003
4-125

USING A POWER SUPPLY INSTEAD OF
LINE POWER

Figure 16 shows the circuit of Figure 9 modified for use
with a +5 volt power supply. The only changes are at
the Tip and Ring interface where the zener diode and
bridge have been eliminated, but the two hook switches
(HS and SS) require one more pole each. The transformer
is used to pass the speech signals and to provide the
required isolation.
Current required from the +5 volt power supply is as
follows:
1. Handset speech mode: 6 rnA.
2. Handset dialing mode: 11 rnA
3. Speakerphone speech mode (no speech signals):
9 rnA.
4. Speakerphone receive mode, - 27 dBm at Tip and
Ring: 51 rnA.
5. Speakerphone receive mode, -9 dBm at Tip and
Ring: 100 rnA.
6. Speakerphone dialing mode: 19 rnA.
Items 4, 5 and 6 above were measured with a 25 0
speaker and the volume control set to maximum.

AN1003
4-126

The performance characteristics are shown in Figures
17-22. The Tip and Ring DC voltage (Figure 17) is now a
function only of the transformer winding resistance and
so is somewhat lower than in the previous circuit.
The speakerphone performance (Figures 18 and 21) is
now constant with respect to loop current since VCC is
fixed. Performance at 20 rnA is similar to that at higher
loop currents, unlike the previous circuit. Although the
speaker can be 25 n as in the previous circuit, it need not
be since the available power is not limited as before. The
recommended range for speaker impedance is 8-32 o.
For different speaker impedances, however, the gain of
the speaker amplifier may have to be changed to compensate for the different power level.
The slight degradation in the transmit curves at high
loop currents is evident in Figures 18 and 19, as was in
the previous circuit.
The muting specs of the transmit and receive paths are
the same for this circuit as for the previous one.

MOTOROLA COMMUNICATIONS DEVICE DATA

s:

KEYPAD

~

DIALER

MO

JJ

o

!i
14

Vcc

~

RI ~

~

7T8T9lC

()

o
s:
s:
c

MCl4023

Vcc

z

o
~

(5

z
en
o
~

om

RING

o
»~

MIKE
MUTE

HS3

1.

.

ceo

=~II

I

..
SS2

100 k

VB ..

t=k:~1

R1I2120

22Ih~- _

RXO

... 1 Ul_h

1

"JI I'

FI

Vcc

I .un=r

Notes:
1.
2.
3.
4.
5.

~

These resistors depend on the specific microphone selected.
These capacitors must be physically adjacent to the power supply pins.
Recommended transformer: StanCQr TTPC-13, Microtran T5115.
HS '" Handset Operated Hookswitch (3 poles), 55 '" Speakerphone Switch (2 poles), Switches shown on-hook.
All capacitors in ~F unless otherwise noted.
6. See Figures 17-22.

.... Z

"'0

1\)0

"",W

e
~

51'F

....

:J

Figure 16. Featurephone With Power Supply

5VDLT
POWER
SUPPLY
INPUT

MC34118 Featurephone With Power Supply

10

2.6

./'

V

6

..,/

-

o
20

/

2.2

./"

V
..,/

/'

V

0.6

f-- APPLIES TO BOTH HANDSET AND SPEAKERPHONE MODES

0.4

I
40

SPEAKER AMP MAX
OUTPUT SWING

2.4

I

I

I

I

I

80

60

I

I

100

DTMF LEVEL AT TIP/RING

I

O. 2
20

120

40

60

I

100

120

Figure 18. Speaker Amp. Output and DTMF Level
versus Loop Current

Figure 17. Tip to Ring DC Voltage versus Loop Current

+42

80

LOOP CURRENT ImAI

LOOP CURRENT ImAI

I

+40

-...

42
SPEAKERPHONE MODE
40 r- ILOOP = 40 mA i'"

-

SPEAKERPHONE MODE

....-

38

'"

36
~ +38

~

z

«

tAND1ET MODE

+22

z

30

'"

28

«

'" +24

34

HANDSET MODE
ILOOP = 30 mA

26
24

f = 1 kHz
1
1
r- GAIN IS FROM MIKE TO TIP/RING

+20
20

40

60
80
LOOP CURRENT ImAI

!--

22
100

20
100

120

Figure 19. Transmit Gain versus Loop Current

+32

ILOOP = 40 mA

+30

+28

~ +26
6
z

f = 1 kHz
GAIN IS FROM TIP/RING TO RCV·R/SPKR.

«

+20

'"

-6
-8

-8
-10

r- -

HANDSET MOOE
ILOOP 1= 30 mA

-12

-10

-14

HANDSET MODE

-12
20

40

60
80
LOOP CURRENT ImAI

100

Figure 21. Receive Gain versus Loop Current

AN1003

4-128

r-

V

+26

~ +22

4k

SpJAK~R~H6~~ ~ODE I

SPEAKERPHONE MODE

~+24

1k
FREQUENCY IHzl

300

Figure 20. Transmit Gain versus Frequency

+32
+30

....,/'

120

-16
100

300

1k
FREQUENCY IHzl

4k

Figure 22. Receive Gain versus Frequency

MOTOROLA COMMUNICATIONS DEVICE DATA

CONSTRUCTION HINTS

Board Layout
The filter capacitors for the speakerphone IC and the
speaker amplifier IC (100 ,.,.F and 1000 ,.,.F respectively)
must be physically adjacent to the pins of the ICs, within
1". This is especially important in the line-powered version, where VCC varies with the speech intensity. Since
most of the current is used in the speaker amp, the PC
board track leading to Pin 6 of the MC34119 should be
laid out with care, preferrably close to the zener diode,
orthe power supply connector. The ground tracks should
be as wide as possible, and laid out with care.
RFI Interference
Potential radio frequency interference problems should
be addressed early in the electrical and mechanical
design of the speakerphone. RFI may enter the circuit
through Tip and Ring, through the microphone wiring to
the amplifiers, or through any ofthe PC board traces. The
most sensitive pins on the MC34118 are the inputs to the
level detectors (RLll, RLl2, TLil and TLl2) since, when
there is no speech present, the inputs are high impedance
and these op amps are in a near open loop condition.
These board traces should be kept short and the resistor
and capacitor for each input should be physically close
to the pins. Other high impedance input pins (MCI, HTI,
FI and VLC) should be considered sensitive to RFI signals.
The microphone wires within the handset cord can act
as an antenna and pick up nearby radio stations. If this
is a problem in the final design, adding RF filters (consisting of ferrite beads and small (0.001 ,.,.F) ceramic
capacitors) to the PC board where the wires attach to the
board can generally reduce the problem.
Acoustics
a. In the design of any speakerphone, acoustics are
extremely important and must be considered from the
very beginning. Building a breadboard and having the
microphone and speaker "hanging out in mid air" simply
will not work! One of the most difficult problems in a
speakerphone design is acoustic feedback (the speaker
talks to the microphone) which results either in oscillations (2-10 kHz) or "motor-boating" (1-10 Hz switching).
A properly designed enclosure for the finished product
should provide at least 50 dB of acoustic loss (speaker
voltage to microphone output voltage). The physicallocation of the microphone, along with the characteristics of
the microphone, will playa large role in the quality of
the transmitted sound. The microphone and speaker vendors can usually provide additional information on the
use of their products.
b. The quality of the speaker and the acoustic cavity
in which it resides, have a major impact on the quality
of the sound. A little time spent here can improve the
sound of the finished speakerphone. As a general rule,
good electronics cannot compensate for poor acoustics
and/or low speaker quality.

MOTOROLA COMMUNICATIONS DEVICE DATA

In The Final Analysis ...
In the final analysis, the circuits shown in this application note will have to be "fine tuned" to match the
acoustics of the enclosure and the specific microphone
and speaker selected. The component values shown in
this application note should be considered as starting
points only. The gains of the transmit and receive paths
are easily adjusted at the microphones and speakerl
receiver amplifiers, respectively. The switching response
of the speakerphone can then be fine tuned by varying
(in small steps) the components at the level detector
inputs until satisfactory operation is obtained for both
long and short lines. The MC34118 data sheet should be
consulted for additional speakerphone design theory.

GLOSSARY
Attenuation - A decrease in magnitude of a communication signal, usually expressed in dB.
Bandwidth - The range of information carrying frequencies of a communication system.
C-Message filter - A frequency weighting which evaluates the effects of noise on a typical subscriber's system.
Central Office - Abbreviated CO, it is a main telephone
office, usually within of a few miles of its subscribers,
that houses switching gear for interconnection within its
exchange area and to the rest of the telephone system.
A typical CO can handle up to 10,000 subscriber numbers.
dB - A power or voltage measurement unit, referred to
another power or voltage. It is generally computed as:
10 x log (Pl/P2) for power measurements and
20 x log (V1N2) for voltage measurements.
dBm-An indication of signal power. 1 mWacross 600 n,
or 0.775 volts rms, is defined as 0 dBm. Any other voltage
level is converted to dBm by:
dBm = 20 x log (Vrms/0.775), or
dBm = [20 x log (Vrms)] + 2.22.
dBmp - Indicates dBm measurement using a psophometric weighting filter.
dBrn - Indicates a dBm measurement relative to 1 pW
power level into 600 n. Generally used for noise measurements, 0 dBrn = -90 dBm.
dBrnC - Indicates a dBrn measurement using a Cmessage weighting filter.
dBrnCO - Noise measured in dBrnC referred to zero
transmission level.
DTMF - Dual Tone MultiFrequency. It is the "tone dialing" system based on outputting two non-harmonic
related frequencies simultaneously to identify the number dialed. Eight frequencies have been assigned to the
four rows and four columns of a typical keypad.

AN1003

4-129

Four wire circuit - The portion of a telephone, or central
office, which operates on two pairs of wires. One pair is
for the Transmit path (generally from the microphone)
and one pair is for the Receive path (generally to the
receiver).
Full duplex - A transmission system which permits communication in both directions simultaneously. The standard handset telephone is full duplex.
Gain - The change in signal amplitude (increase or
decrease) after passing through an amplifier or other circuit stage. Usually expressed in dB, an increase is a positive number and a decrease is a negative number.
Half duplex -,.A transmission system which permits communication in one direction at a time. CB radios, with
"push-to-talk" switches and voice activated speakerphones, are half duplex.
Hookswitch - A switch which connects the telephone
circuit to the subscriber loop. The name derives from old
telephones where the switch was activated by lifting the
receiver off and onto a hook on the side of the phone.
Line length compensation - This is also referred to as
loop compensation. It involves changing the gain of the
transmit and receive paths, within a telephone, to compensate for different signal levels at the end of different
line lengths. A short line (close to the CO) will attenuate
signals less and therefore less gain is needed. Compensation circuits generally use the loop current as an indication of the line length.
Loop - The loop formed by the two subscriber wires
(Tip and Ring) connected to the telephone at one end and
the central office (or PBX) at the other end. Generally it
is a floating system, not referred to ground, or ac power.
Loop Current - The dc current which flows through the
subscriber loop. Typically provided by the central office
or PBX, it ranges from 20 to 120 mAo
Off hook - The condition when the telephone is connected to the phone system, permitting the loop current
to flow. The central office detects the dc current as an
indication that the phone is busy.
On hook - The condition when the telephone is disconnected from the phone system and no dc loop current
flows. The central office regards an on-hook phone as
available for ringing.
PABX - Private Automatic Branch Exchange. This is a
customer owned switching system servicing the phones
within a facility. It is in effect, a miniature central office.
A portion of the PABX connects to the Bell (or other local)
telephone system.

Pulse dialing - A dialing system whereby the loop current is interrupted a number of times in quick succession.
The number of interruptions corresponds to the number
dialed and the interruption rate is typically 10 times per
second. The old rotary phones and many new pushbutton
phones, use pulse dialing.
REN - Ringer Equivalence Number. This is an indication
of the impedance, or loading factor, of a telephone bell
or ringer circuit. A REN of 1 equals =8 k ohms. The Bell
system typically permits a maximum of 5 REN (1.6 kO)
on an individual subscriber line. A minimum REN of 0.2
(40 kO) is required by the Bell system.
Ring - This is one ofthe two wires connecting the central
office to a telephone. The name derives from the ring
portion of the plugs used by operators (in older equipment) to make the connection. Ring is traditionally negative with respect to Tip.
Sidetone - The sound fed back to the receiver as a result
of speaking into the microphone. It is a natural consequence of the 2-to-4 wire conversion system. Sidetone
was recognized by Alexander Graham Bell as being necessary for a person to be able to speak properly while
using a handset.
Speech network - A circuit which provides 2-to-4 wire
conversion, i.e. connects the microphone and receiver
(or the transmit and receive paths) to the Tip and Ring
phone lines. Additionally it provides sidetone control and
in many cases, the dc loop current interface.
Subscriber Line - This is the system consisting of the
user's telephone, the interconnecting wires and the central office equipment dedicated to that subscriber. It is
also referred to as a loop.
Tip - One of the two wires connecting the central office
to a telephone. The name derives from the tip ofthe plugs
used by operators (in older equipment) to make the connection. Tip is traditionally positive with respect to Ring.
Tone Ringer - The modern solid state equivalent of the
old electromechanical bell. It provides the sound when
the central office alerts the subscriber that someone is
calling. Ringing voltage is typically 80-90 Vrms, 20 Hz.
Two wire circuit - Refers to the two wires connecting
the central office to the subscriber's telephone. Commonly referred to as Tip and Ring, the two wires carry
both transmit and receive signals in a differential manner.
Voiceband - That portion of the audio frequency range
used for transmission across the telephone system. Typically it is 300-3400 Hz.

REFERENCES
MC34118 Data Sheet, April, 1987, Motorola Inc.
MC34119 Data Sheet, October, 1986, Motorola Inc.
MC33171 Data Sheet, July, 1985, Motorola Inc.
MC145412 Data Sheet, February, 1987, Motorola Inc.
Busala, A., Fundamental Considerations in the Design
of a Voice Switched Speakerphone, B.S.T.J., 39,
1960, p. 265.

AN1003
4-130

MOTOROLA COMMUNICATIONS DEVICE DATA

SUGGESTED VENDORS

Microphones
Primo Microphones Inc.
Bensenville, III. 60106
312-595-1022
Model EM-60

Hosiden America Corp.
Elk Grove Village, III. 60007
312-981-1144
Model KUC2123

MURA Corp.
Westbury, N.Y. 11590
516-935-3640
Model EC-983-7

25 n Speakers
Panasonic Industrial Co.
Sea caucus, N.J. 07094
201-348-5233
Model EAS-45P19S

Telecom Transformers
Microtran Co., Inc.
Valley Stream, N.Y. 11528
516-561-6050
Various models - ask for
catalog and applications
Bulletin F232

Stancor Products
Logansport, IN 46947
219-722-2244
Various models - ask
for catalog

PREM Magnetics, Inc.
McHenry, III. 60050
815-385-2700
Various models - ask for
catalog

On an Power/Electronics
Minneapolis, MN 55437
612-921-5600
Model TC 38-6

Motorola Inc. does not endorse or warrant the suppliers referenced.
Compliance with FCC or other regulatory agencies of the circuits
described herein is not implied or guaranteed by Motorola.

MOTOROLA COMMUNICATIONS DEVICE DATA

AN1003
4·131

MOTOROLA

-

SEMICONDUCTOR
APPLICATION NOTE

AN1004

A Handsfree Featurephone Design
Using the MC34114 Speech Network
and the MC34118 Speakerphone ICs
Prepared by
Dennis Morgan
Bipolar Analog IC Division

INTRODUCTION
This application note describes the procedure for combining the MC34114 speech network with the MC34118
speakerphone circuit into a featurephone which includes
the following functions: ten number memory pulse/tone
dialer, tone ringer, a "Privacy" (Mike Mute) function and
line length compensation for both handset and speakerphone operation.

Three circuits are developed in this discussion: a linepowered featurephone, a line-powered featurephone
with a booster (for using the speakerphone on long lines),
and one powered from a power supply. The circuits are
nearly identical, except for the Tip and Ring interface.
Their performance however, differs noticeably, particularly in the low loop current range. Initially, the discussion
will focus on the line-powered circuit.

TIP
RS

RING
R1

RECEIVER

R4

MIKE

R5

NOTE: PIN NUMBERS IN PARENTHESES
ARE FOR THE SOIC PACKAGE.

Figure 1. MC34114 Block Diagram

AN1004
4-132

MOTOROLA COMMUNICATIONS DEVICE DATA

The dc characteristics at Tip and Ring are determined
by the diode bridge (1.4 volts), a level shift of approximately 2.9 volts from VCC to LR, and the voltage across
R2 + R3 (typically 43 0 and 13 0). All the loop current,
minus =10 mA, flows through those two resistors. The
level shift (VCC - LR) increases to =3.9 volts when both
MUTE and MS are low (tone dialing mode). The voltage
at RAGC, when within the range of 0.5 to 1 volt, controls
the internal AGC as a function of loop current.

DESCRIPTION OF THE BUILDING BLOCKS
NOTE: Several pins on the ICs used in this application
note have identical nomenclature (VCC, VB, TXI, MS, VDD
and RXI). They provide separate functions, and are not
to be connected together unless so noted.
MC34114 Speech Network
The MC34114 is a speech network which interfaces with
Tip and Ring, and provides the 2-to-4 wire conversion
(see Figure 1). The transmit gain is determined by the
microphone amplifier (fixed gain of 30 dB), R6, C5, the
internal current gains of A1, A2, the AGC, and the line
impedance in parallel with R1. The receive gain is determined by ZB, the internal current gains of A4 and the
AGC, C8 and R8. The sidetone cancellation is determined
by A3 and the ZB network. The AGC points have a current
gain of 1 at low loop current, and decrease to 0.5 (- 6
dB) at higher loop currents, thus providing line length
compensation. R1 (typically 600 n) sets the circuit's terminating impedance for ac (return loss) purposes.
The MUTE input (when low) disables the microphone
amplifier, and partially mutes the receive amplifier (with
an internal 1 k feedback resistor), when dialing. DTMF
dialing signals are injected at TXI through R7 and C6. The
Mode Select (MS) input (when low, and MT is low) provides a voltage boost at VCC to ensure adequate voltage
during DTMF dialing at low loop currents. The 3.3 volt
regulated output (VDD) powers the dialer, and the 1.7
volt regulated output (VR) is used to bias the microphone.

MC34118 Speakerphone
The MC34118 speakerphone Ie (see Figure 2) provides
all the necessary functions for a complete speakerphone
circuit in a single integrated circuit. Included are the transmit and receive attenuators, which operate in a complementary manner, to provide the necessary half-duplex
function. The four level detectors, in conjunction with the
two background noise monitors and control algorithm,
provide a four point sensing and decision making system
to control the attenuators based on the levels and timing
of the transmit and receive signals. Additional functions
include the microphone amplifier, a Mute input for the
microphone amplifier, volume control for the receive
path, a filter, and a Chip Disable pin. The gain of the
receive attenuator, normally + 6 dB at max. volume, is
reduced by the AGC circuit as VCC falls below 3.5 volts
to control the amount of voltage sag in a line powered
application. The component values shown are typical.
Connections to the MC34118 circuit are made to several
points around the circuit as follows:

0----------------_ T~~~~~+T
.-,--_ _ _ _ _ _ } SEE
HTI
6 HTOTEXT
~~~--~+-~~~~--------~~~~-+~~~~----~
VCC

~~~i r-----t-...,
CHIP
DISABLE

CT

14
51'F

120 k

VB

15~~~~--~--~~------_+_4~----~+_~~~1r~
TL02
lB

RL02
19

TO
SPEAKER . - - - - - - - - - '
AMP

VOLUME
CONTROL

-=

Figure 2. MC34118 Block Diagram

MOTOROLA COMMUNICATIONS DEVICE DATA

AN1004

4-133

The TRANSMIT OUTPUT (upper right) connects to the
4 wire side of the speech network. The transmit gain,
from the microphone to TRANSMIT OUTPUT, is + 37 dB
(+ 31 dB in the mike amp, + 6 dB in the Tx attenuator),
and does not vary with the volume control. In the receive
mode, the transmit gain is = -15 dB.
The RECEIVE INPUT (lower right) is derived from the
4 wire side of the speech network. The gain from RXI to
RXO is +6 dB when in the receive mode at maximum
volume. At minimum volume, the attenuator's gain
reduces by =46 dB, for an overall gain of - 40 dB. In the
transmit mode, the gain is = -46 dB. Pins 22 (Receive
out) and 20 (Receive level detector input) connect to the
external speaker amplifier (MC34119).
The overall speakerphone's transmit and receive gains
to and from Tip and Ring are adjusted at the mike and
speaker amplifier and at the 4-wire interface.
The MIKE MUTE input disables the mike amplifier when
at a logic high. Chip Disable disables the MC34118 when
at a logic high, reducing the MC34118's supply current
from a normal =5.5 mA to =600 /LA.
The two op amps (pins 5, 6, 7) are available for a variety
of uses. Figure 23 of the MC34118 data sheet, for example, indicates their use with a transformer to form a standalone speakerphone. Later in this application note however, they will be used with the MC34114 as part of the
receive path.
VCC (Pin 4) is the power supply input, requiring 3 6.5 volts @ =5.5 mAo The 100 /LF capacitor must be physically adjacent to pin 4 in the board layout to prevent
oscillations.
VB is the ac ground for the IC, and must be well filtered,
as shown.
MC34119 Speaker Amplifier
The MC34119 (Figure 3) is a 400 mW speaker amplifier,
capable of 500 mW peaks. With a supply voltage range
down to 2 volts, it is well suited for speakerphone applications. The gain is adjustable from less than 0 dB (it is
unity gain stable) to a maximum of =46 dB to cover the
voiceband. It provides a differential output to the speaker,
eliminating the bulky series capacitor normally needed
with single-ended outputs. Additionally, the device has
a Chip Disable pin which, when taken high, sets the outputs to a high impedance state.
RI
6 VCC

125 k
50 k

MC34119
'OPTIONAL - FOR IMPROVEO POWER SUPPLY REJECTION
OIFFERENTIAL GAIN

~

2x~

Figure 3. Speaker Amplifier

AN1004
4-134

The dc supply at VCC must be well filtered to prevent
oscillations when the speaker amplifier is operating. In a
typical line powered circuit, an inductor (1 H) is used, in
conjunction with a 1000 /LF capacitor at VCC, to filter the
voltage derived from the loop current. Capacitors Cl and
C2 shown in Figure 3 are not used in this application.
Instead, bias is provided to Pin 3 from the MC3411S's VB
pin.
MC145412 Dialer
The dialer is a pulse/tone dialer with 10 number memory, including last number redial (Figure 4). The pulse/
tone functions are selectable at Pin 10 (MS). The circuit
uses a standard 3.58 MHz crystal, and a standard 3x4 or
4x4 keypad.

VSS

17

TO PULSE
DIAL CKT.

MC145412
DIALER

KEYPAO

2

3

4

5

6

B

7

8

9

C

1

5P[

A

16

R1

OTMF

DTMF
OUTPUT

VOO

FROM
MC34114
VDO

15
14

M6
C4
OSC1

11

MUTE
OUTPUT
PACIFIER
TONE

TSO

4.7M

FROM
TIP'RING

Figure 4. PulselTone Dialer
The NPN transistor at Pin 12 indicates the on-hookloffhook status to the IC. Power for the dialer is the
MC34114's VDD (3.3 volts), diode connected with a memory sustaining battery. The DTMF output goes to C6/R7
of Figure 1.
The OPL ("O"U'"T"'P"U"L"S"'IN'"G"') pin is used to interrupt the
loop current when pulse dialing. The pin is an active low
open drain. TSO (Tone Signal Output) provides a 500 Hz
pacifier tone during pulse dialing. The tone is a square
wave, which swing from VDD to VSS.
The Mute Output (MO) is active low, open drain and
pulls to ground while dialing. It is used to mute the speech
paths during dialing.

SWITCHING THE CIRCUIT AROUND
The logic functions involve: a) switching the circuit
from handset mode to and from speakerphone mode,
b) switching in and out of either dialing mode while in
either handset or speakerphone mode, and c) muting the
two microphones for the "Privacy" function. Table 1 tabulates the fundamental requirements applicable to any
featurephone:

MOTOROLA COMMUNICATIONS DEVICE DATA

Table 1.
HANDSET SPEAKERPHONE
Function

Mike R'cvr

Mike

Speaker

Handset Speech
Handset Dialing
Handset Mike Mute

On
Off
Off

On
Mute
On

Off
Off
Off

Off
Off
Off

Speakerphone Speech
Speakerphone Dialing
Speakerphone Mike Mute

Off
Off
Off

Off
Off
Off

On
Off
Off

On
Mute
On

In Table 1, "ON" means fully functional, "OFF" means
non-functional, and "MUTE" means partially muted (10
to 20 dB). To apply Table 1 to the specific ICs described
previously, the requirements are expanded in Table 2:

Table 2.
MC34114
Function
Handset
Handset
Handset
Handset

Speech
Pulse Dialing
Tone Dialing
Mike Mute

Speakerphone
Speakerphone
Speakerphone
Speakerphone

x=

Speech
Pulse Dialing
Tone Dialing
Mike Mute

MC3411S

Loop
Current

MT

MS

CD

MUT

MC34119
CD

Hi
Lo
Lo
Lo

X
Hi
Lo
X

Hi
Hi
Hi
Hi

X
X
X
X

Hi
Hi
Hi
Hi

Thru
Thru
Thru
Thru

Lo
Lo
Lo
Lo

X
Hi
Lo
X

Lo
Lo
Lo
Lo

Lo
Hi
Hi
Hi

Lo
Lo
Lo
Lo

To
To
To
To

MC34114
MC34114
MC34114
MC34114

MC34119
MC34119
MC34119
MC34119

MC145412
MS

X
Open
Gnd
X
X
Open
Gnd
X

Don't Care

A summary of Table 2 is:
a) The MC34114 speech network is put into the Mute
mode (MT = Lo) not only for dialing, but also to mute
the microphone and receiver for the Privacy function
(Mike Mute). and when in the speakerphone mode.
b) The MC34118 and MC34119 are disabled for all the
handset functions, and enabled for all the speaker·
phone fu nctions.
c) The MC34118's Mike Mute function is activated for
dialing and for the Privacy function.
d) The loop current, which normally flows through the
LR pin of the MC34114 (see Figure 1), is directed
instead to the MC34119 in the speakerphone mode so
as to make the power available to the speaker.
d) The M5 pins of the dialer and of the MC34114, are
significant only during dialing.

PUTTING IT ALL TOGETHER
Switching Between Handset and Speakerphone Modes
To switch between modes, two actions are necessary:
1) Divert the excess loop current, which normally flows
through the MC34114, to the MC34119 during speakerphone mode, and 2) enable and disable the speech network and speakerphone circuits appropriately. The circuit
of Figure 5 fullfills those requirements:
H5 (3 poles) is the hookswitch operated by lifting the
handset. 55 (1 pole) activates the speakerphone when
the handset is on-hook. The switches are shown on-hook
in Figure 5.

43, I W
RAGC 1-----,
VDD

IH

RING

,-----------..-t---1r---I----. lN4733
5.1 V

V+

MC34119
GND

DIODES

~

CD

I N4002, OR EQUIVALENT

Figure 5. Switching Between Modes
MOTOROLA COMMUNICATIONS DEVICE DATA

AN1004
4-135

If the handset is on-hook, and switch SSl is closed
(speakerphone mode), the MC34114 uses =10 mA internally, but the excess loop current flows through the 1
Henry choke, the zener diode and the 130 resistor. The
voltage across the 13 0 resistor controls the line length
compensation function of the MC34114. The MC3411S
and MC34119's CD pins are held low by HS3, enabling
the speakerphone circuit. The MC34114's MT is low, muting its microphone and receive amplifiers. If the handset
is lifted while the speakerphone is in operation, the circuit
automatically switches to the handset mode.
When the handset is lifted (HS transfers), the MC34114
consumes =10 mA internally, but the excess loop current
now flows through the MC34114, out of the LR pin and
through the 43 0 and 130 resistors. The voltage across
the 13 0 resistor still controls the line length compensation. This configuration is similar to that of Figure 1.
Since the MC3411S and MC34119 are disabled (their CD
pins are pulled high); their current consumption is
reduced to <1 mAo
Joining the Receive Paths
Referring to Figure 1, receive signals arriving at Tip and
Ring generate a currerit through the ZB network, into pin
15. That current is modified by A4 and the AGC, made
available (as a current) at RXA, and coupled to RXI, where
it is converted to a voltage by the receive amplifiers and
RS. The ZB network is typically 12 kO, and RS is typically
3.9 kO. The receive gain to the handset receiver is therefore nominally -10 dB at low loop currents.
To feed the receive signals to the speakerphone, the
circuit of Figure 6 is used.

G
= 20 I
(RRSPXA4XAGCXO.5)
6 dB
RX
og
ZB+500 0
+
+ 20

I~g (2 ~iRf)

The terms A4, ZB, and AGC (from Figure 1) are set at
0.5, 12 kO, and 1 respectively for low loop currents. The
0.5 in the first term is due to the current splitting of
Figure 6. The +6 dB isthegain ofthe MC3411S's receive
attenuator at maximum volume. The third term is the
gain of the speaker amplifier.
It is desirable to have as much gain as possible early
in the receive path to minimize the effects of noise generated or picked up by the circuit. Since the maximum
allowable input at RXI is 350 mVrms, a gain of 3.5
(10.9 dB) was chosen for the first term above, in order
to accommodate receive signals of 100 mVrms
(-17.S dBm) at Tip and Ring. RRSP calculates to
approximately 160 kO. For an overall gain of =+30 dB,
Rf/Ri must be =2.2. At higher loop currents, the overall
gain will be = + 24 dB, due to the line length compensation function.
Joining the Transmit Paths
In the transmit path of Figure 1, the microphone signals
are gained up by 30 dB by the mike amplifier. The output
at MCO creates a current into TXI through R6 and C5.
That current is gained up by 100 by Al and A2 (assume
AGC = 1), and A2's output current then acts on the parallel combination of Rl and the line's ac impedance. Typical values are: R6 = 15 kO, Rl = 6000, and 6000 for
the line's impedance. Neglecting the slight loading of R7,
R12, and ZB, the overall handset transmit gain is
=+36 dB at low loop currents.
MC34018

MCO
TO RECEIVE
INPUT
(FIGURE 2)

~----~----~----~

MC34114

'--'V'>/Ir--U----e--JTXI
RTSP

Figure 7. Joining the Transmit Paths
MC34118

HTO+

Figure 6. Joining the Receive Paths
The cu rrent out of RXA is now split by the 1 kO resistors
so that approximately half goes to RXI (of the MC34114)
via CS, and the other half is converted to a voltage (by
the op amp) for the speakerphone's Receive Input (Figure
2). The second op-amp (at HTO +) is unused in this application. The receive gain for the speakerphone (from Tip/
Ring to the speaker) is determined by the following
equation:

AN1004

4-136

The transmit output from the speakerphone circuit
(Figure 2) is applied to the speech· network at TXI in
Figure 1, through a resistor (RTSP) and a coupling
capacitor (see Figure 7). For a nominal gain +40 dB
(from the microphone to the MC34114's Vce), RTSP
calculates to be =11 kO. The coupling capacitor (typically 0.1 /LF) can be adjusted to set the low frequency
rolloff.
Fitting in the Dialer
The DTMF output in Figure 4 is simply connected to
C6 and R7 of Figure 1 to get the DTMF signals to Tip and
Ring. Using 20 kO for R7, and 0.1 /LF for C6, DTMF levels
of = - 2.2 dBm will result at Tip and Ring at low loop
currents.
MOTOROLA COMMUNICATIONS DEVICE DATA

MS

t-l_°-.t---<~-T;;O"'NE'-----------lI~ ~s~~~4;ii

'\--_--1

~

PULSE

-=-

Figure 8. Pulse Dialing Circuit

For pulse dialing, Pin 17 of the MC145412 dialer (OPL)
is connected to a standard two transistor network to interrupt the loop current (Figure 8). The 12 volt zener diode
protects the circuitry from voltage spikes during pulse
dialing (and whenever a hook switch is opened).
The TSO output (pacifier tone), which is generated only
when a keypad button is depressed in the pulse dialing
mode, is injected to the MC34114's ZB pin so as to make
it available to both the handset receiver and the speakerphone. This tone is not generated during DTMF dialing.
To select between pulse and tone dialing modes, the
switch on the dialer's Pin 10 (Figure 4) is connected to
the MC34114's MS pin (Pin 16). Since the MC34114's MS
pin requires a pull-up resistor for a logic high, a diode
must be added (Figure 8) so the dialer's MS pin is open
when the switch is in the pulse position.

TO SPEAKERPHONE
RECEIVE PATH MUTE
VDD
MO(FROM
DIALERI

Muting and Privacy
The Mute Output of Figure 4 must mute (by at least
45 dB) both microphone paths, and partially mute
(10-20 dB) both receive paths during dialing. The privacy (Mike Mute) function requires muting the microphones only by at least 55 dB. This is accomplished
with the circuit of Figure 9 using an MC14023 CMOS
triple NAND gate. The inputs to the logic circuit are the
Mute Output (MO) from the dialer, the Mike Mute (Privacy) switch and the speakerphone/handset mode
select switch HS3 (same as that of Figure 5). The outputs are to the speakerphone's receive path, the
MC34114's Mute (which mutes both its transmit and
receive paths), the speakerphone's microphone, and to
the speakerphone and speaker amp's CD pins. The
MC14023 is powered by the MC34114's VDD output.
The circuit of Figure 9 will:
a) Mute the receiver and speaker and disable both
microphones during dialing;
b) Disable both microphones when the Privacy switch
is closed;
c) Enable either the MC34114 or the MC34118/
MC34119 combination in response to the Mode Select

>---+---.

VDD

FROM
HTO - (PIN 61

100 k
FROM
LOGIC
CIRCUIT

MODE SELECT
SWITCH (HS31
TO MC34118 AND MC34119
CD PINS

Figure 9. Muting Circuit

MOTOROLA COMMUNICATIONS DEVICE DATA

Figure 10. Receive Path Muting

AN1004

4-137

TIP
6.8 k. 112 W

RING
II'F. NPO

S~g2~ESL

MC34017
TONE RINGER
ACI

ROI

R02

RI

TO TElEPHONE
CIRCUIT
PIEZO SOUNDER

Figure 11. Tone Ringer Circuit
Switch. HS3 is shown on-hook in Figure 9, which enables
the speakerphone when SS1 of Figure 5 is closed. (Note:
In Figure 5, HS3 is shown controlling the MC34114's MT
pin directly. In Figure 9 the same function is achieved
through the NAND gate).
Muting of the speakerphone's receive path (from the
above circuit) is accomplished with the circuit of Figure
10. The muting is inserted in the speakerphone's
receive path leading to the filter. Normally, the transistor is off and the 10 k resistor has little effect on the
circuit due to the filter's high input impedance (>200
kn @ 1 kHz). When Mute is asserted, the signal to the
filter is muted by =20 dB.
Adding the Tone Ringer
The MC34017 tone ringer circuit, shown in Figure 11,
is simply connected directly across Tip and Ring. It is not
necessary to disconnect the tone ringer when off-hook.
This circuit will provide a ringer with an REN of =0.5, and
meet all the EIA-470-A and Bell system requirements for
impedance, anti-bell tapping and turn-on/off thresholds.
Finally, the Complete Circuit
The complete line-powered featurephone is shown in
Figure 12. Some notes concerning this circuit:
a) The resistor and capacitor (R6/C5 shown in Figure
1) between MCO and TXI of the MC34114 was replaced
with the network of Figure 12 to provide high frequency
roll off.
b) The 13 n resistor normally spec'd for R3 of the
MC34114 (and shown in Figure 5) was increased to 18 n
to decrease the point at which line length compensation
begins.
c) A 470 /-LF capacitor was added across the 18 n resistor to suppress interaction which occurs between the line
length compensation function of the MC34114 and the
AGC function of the MC34118.
d) The dc resistance of the 1 Henry inductor must be
kept below 50 n to keep the dc voltage at Tip and Ring
and at the MC34114's VCC pin within safe bounds at both
low and high loop current values.

AN1004

4-138

The performance curves for this circuit are shown in
Figures 13-18. The "Speaker Amp Max Output Swing"
is the maximum rms voltage available at the speaker
terminals. The transmit gain tests involved replacing
each microphone with a signal generator and adjusting
for a level of approximately -11 dBm at Tip and Ring
into a 600 n resistive load. The receive tests involve
applying approximately -27 dB to Tip and Ring, and
measuring the gain to the receiver or speaker.
As can be seen in Figure 14, the maximum available
speaker power is a function of the loop current since all
of the speaker current must come from the loop. Consequently, the receive gain for the speakerphone (Figure
17) shows a marked decrease at low loop currents. It must
be remembered.that in a line powered speakerphone, as
the speaker draws current in response to a receive signal,
the voltage at Tipand Ring decreases quickly. As the VCC
at the MC34119 falls with the Tip and Ring voltage, the
speaker amp's output capability is reduced. Consequently, a 25 n speaker is recommended for a line powered speakerphone as this makes the best use of the
power available from the phone line. A lower impedance
speaker will require more current, causing V + to sag
further for a given signal level. A higher impedance
speaker. draws less current, but produces less sound
power.
Additionally, the following muting specs apply:
1) Handset microphone: >70 dB while dialing, or
when Mike mute switch is closed. 80 dB in speakerphone mode.
2) Speakerphone microphone: >90 dB while dialing,
in the handset mode, or when the Mike mute switch
is closed.
3) Handset receiver: =17 dB while dialing, or when in
the speakerphone mode.
4) Speaker: =20 dB while dialing, >100 dB when in
handset mode.

MOTOROLA COMMUNICATIONS DEVICE DATA

~

HSl

TlP~

d
~

>

RING( )

VR

I ,

L .. _l

nn;J

T ".....
..,••

8.lk~

VB

8s::

GND

s::
c

o
~

Vss

~

en
c

KEYPAD

~
A

m
<
om

SPEECH
NElWORK

MCl
MCl

FROM
150

z

MC34114

15

ZB

OPL

MC145412
DIALER

16 Rl
15 •
14 :

DTMF

I

18

~"I

~l00k

~.13k

VDD

c

lH
141il
SEE

»~

TEXT)
lN4733

Notes:
11 HS
SS

~
~

Handset operated switch - 3 poles.
Speakerphone on/off switch - 1 pole.

Switches shown in on·hook position.
2) Microphone biasing resistor values
depend on the specific microphone.

31 All diodes 1N4002.
5.1k.

15 •

TLOl I RLOl
_18 1..19
Il/L F 1 /L F

-=

....>-

""z
"'0

fg2

I-=

lOOk
VOLUME
CONTROL

Figure 12. PulselTone Featurephone w/Memory -

Line Powered

MC34114/MC34118 Line Powered Featurephone

1.6

13
SPEAKERPHONE MODE
(NO RECEIVE SIGNA~

r-- -

...............

---

'if"'"

-:: ~

?

..---

--- ---........-

L,. "\

..-/

...........

V

./

V :...--

/
Y

/

1

HANDSET MODE
(SPEECH, PULSE DIALINGI

/
/
0.6

HANDSET MODE
ONE ~IALlNGI

"",(,

100

/

'"'"'i---J

/

O. 2
20

120

........ ~~TMF L~VEL A~ TIPIRI~G- -

/

0.4

60
80
LOOP CURRENT (mAl

40

,/

I

SPEAKER AMP. MAX,
OUTPUT SWING

1.2

(r

3
20

I

1.4

I

I
60
80
LOOP CURRENT (mAl

40

I
100

120

F.igure 13. Tip to Ring DC Voltage versus Loop Current

Figure 14. Speaker Amplifier Output and DTMF Level
versus Loop Current

41

42
I

.......

I

39

'/

37

........ SPEAKERPHONE MODE

-

~ 35
z
~ 33

40

........

I

34

.........

29

........ HANDSET MODE- l -

/

0
8

6

i

/"

~

IV

/~130dBm

I I
I II I
I 1-26dBm

9
-1 1
-1 3
W

-

.r-to."

-40 dBm

+20

~

ILOOP = 40 mA
- 26 dBm AT TIP/RING

,.,.

E+l 6
z

~

~

-~
-1 0

r-.......

't-40

- f..--

Figure 17. Receive Gain versus Loop Current
and Input Signal

4k

SPEAKER~HONJ MohE

iii

SPEAIKERPHONE MODE---;

80
80
~
LOOP CURRENT (mAl
'THIS REGION NOT RECOMMENDED FOR SPEAKERPHONE USE
f = 1 kHz, GAIN IS FROM np/RING TO RCV'RISPKR

AN1004
4-140

+24

26dBm
.......
30dBm-

HANDSET MODE

lk
FREQUENCY (Hzl

Figure 16. Transmit Gain versus Frequency

,/

............

HANDSET MODE
'\. ILOOP = 30 mA

"

300

V-15dBm

/'

.........

V

30

Figure 15. Transmit Gain versus Loop Current

+22

\

/

32

f = 1 kHz
1'--..l
I -t-I
27 GAIN IS FROM MIKE TO TIP/RING
40
100
120
20
80
60
LOOP CURRENT (mAl
'THIS REGION NOT RECOMMENDED FOR SPEAKERPHONE USE

'/

"-

/

........
........

+24

.......

.........

31

+2 8
+2 6 -40 JBm'

JPEAKJRPH~N~ M'o6E'
ILOOP = 40 mA

V

38

.......

-

120

HANDSET MODE
-ILOOP = 30 mA
I
I
-1 4
-1 6
100

r

300

/

----

lK
FREQUENCY (Hz)

4K

Figure 18. Receive Gain versus Frequency

MOTOROLA COMMUNICATIONS DEVICE DATA

BOOSTING THE SPEAKERPHONE AT
LOW LOOP CURRENTS
Adding a Booster
To improve the performance of the speakerphone at
low loop currents (below 40 mAl, a minimal cost
approach is to add an optional booster to the power
supply portion of the MC34119. The approach in this
application note is to use a wall mount transformer,
similarto calculator chargers. A 6 volt ac Adapter, Radio
Shack model #273-1454A, which contains the diode
bridge and filter capacitor, was used to minimize the
additional circuitry within the speakerphone itself.
Since this particular ac adapter is specified for use with
Radio Shack's speakerphones, it is this author's
assumption that it complies with applicable FCC specifications, although that is not so stated on the
transformer.

Rf

Vee FROM
ZENER DIODE

Figure 19. Adding a Speakerphone Booster

MOTOROLA COMMUNICATIONS DEVICE DATA

This application does not require a regulated voltage
from the ac adapter, which further simplifies the design.
The circuit of Figure 19 adds the ac adapter to the circuit
of Figure 12.
The power supply connector is added to the MC34119
VCC pin, and diode connected to the system's 5.1 volt
zener diode of Figure 12. Pin 3 of the MC34119, which
previously had been connected to the VB bias line of the
MC34118, now is biased from an internal circuit. The 1 JLF
capacitors on pins 2 and 3 provide power supply noise
and ripple rejection.
On long lines, where the system VCC tends to sag easily
in the presence of receive signals, the booster provides
the current to the speaker amplifier. The system VCC, in
turn, does not sag, but remains at a stable and consistent
level over all values of loop current.
Without the adapter plugged in, the circuit will act similar to that of Figure 12. In the handset mode, the circuit
characteristics are the same as that of Figure 12 when it
is in the handset mode.
The Complete Circuit with the Booster
The complete circuit is shown in Figure 20. A quick
comparison shows it is identical to that of Figure 12,
except for the booster section in the lower left hand
corner. The performance curves for this circuit are
shown in Figures 21-26. As can be seen in Figures 22,
23 and 25, the speakerphone's performance does not
degrade below 40 mA as had happened in Figures 14,
15 and 17. The muting specs for this circuit are the same
as for Figure 12.
The current required from the booster varies from
=3 mA (no receive signal) to =120 mAwith a -15 dBm
signal at Tip and Ring.

AN1004
4-141

!~
....

HSI

Ni
~

TIP
VR

1'VCC

RING

B20

B.2k <;

22
FROM
TSO

-~
16
15
14
13

3.9 NF

3.9k

MC34114
SPEECH
NETWORK

15 ZB

QP[

VSS

A

1M

3 VB
5 GND

MC145412
DIALER
Rl
:
:
•

DTMF 118

lOOk

13·k

VDD

Notes:
1) HS
SS

s::

a
o

~

~

Handset operated switch - 3 poles.
Speakerphone onloff switch - 1 pole.

Switches· shown in on-hook position.
2) Microphone biasing resistor values
depend on the specific microphone.

3) All diodes 1N4002.

:II

s;:

o
o
s::
s::
c
z

o

:!:j

oz

en

o

~
om
o
~
:I>'

20

CT

14

]
15

r

n02
L02
_1819

221

RXO

~..

1f r;CL ·
-.

J;21'F121'F

lOOk
VOLUME
CONTROL

Figure 20. PulsefTone Featurephone w/Memory -

Line Powered w/Booster

"

=r

MC34114/MC34118 Line Powered (w/Booster) Featurephone

13

3

./'"

V
".........

--- ..----~NDSETMODE
/

~k

/'
,/

V

V

...- ~SETMODE
---

2. 6

-

4

::F

(SPEECH, PULSE DIALING I

::

6

(TONE DIALINGI

..........

DTMF LEVEL AT TIP/RING

~

o.4

3

r--,...

-

O. 2
20

40

60
80
LOOP CURRENT (mAl

100

120

20

60
80
LOOP CURRENT (mAl

40

I-120

100

Figure 21. Tip to Ring DC Voltage versus Loop Current

Figure 22. Speaker Amplifier Output and DTMF Level
versus Loop Current

41

40

-.....

If

39

........

r--

~ 35

r--- HANDSET MODE'
......
.......

27

20

40

V

~

«
c.:> 34

I
29 f = j kHz I
GAINIIS FRO~ MIKEl TO TIPIRING

60
80
LOOP CURRENT (mAl

-100

HANDSET MODE
-ILOOP = 30 my

+28

f""'o."..

..........

+24

120

-.......

:9.+20
z
~+1 8

Figure 24. Transmit Gain versus Frequency

-1 1
-13
20

1/

~+20
z -

«

:::

I"'40

HANDSET MODE

"i--

60
eo
LOOP CURRENT (mAl

-

100

Figure 25. Receive Gain versus Loop Current

MOTOROLA COMMUNICATIONS DEVICE DATA

-.......

SPEAKERPHONE MODE
+24 '--ILOOP = 40 mA

-- -

..........

4K

lK
FREQUENCY (Hzl

+2 8

7
9

\
300

SPEAKERPHONE MODE

+2 2

" '\

/

30

f = 1 kHz, GAIN IS FROM TIP/RING TO RECV'R/SPKR.

+26

I--

32

Figure 23. Transmit Gain versus Loop Current

+30

\

_ 36

.......

z

31

'\

SPEAKERPHONE MODE

-.......

.......

'"

~ 33

.........

SPEAKERPHONE MODE
38 r-ILOOP = 40 mA

"-

37

m

SPEAKER AMP. MAX.
OUTPUT SWING

2.

V

".........

I

8r-

SPEAKERPHONE MODE...........

'"

i

-1 o_
-1 4

-1 6
120

/
HANDSET MODE
ILOOP = 30 mA

r
300

/

---

A
lK
FREQUENCY (Hzl

4K

Figure 26. Receive Gain versus Frequency

AN1004
4-143

USING A POWER SUPPLY INSTEAD OF
LINE POWER
Using A Transformer
For those cases where it is desirable to power the featurephone from a regulated power supply, rather than
from loop current, a transformer is required at Tip and
Ring to provide the isolation needed between the phone
line and any ac power and earth ground. The primary
change to the circuit of Figure 12 is in the area ofthe Tip
and Ring interface, as shown in Figure 27. It must be
remembered that loop length compensation is not possible in this circuit since the loop current is not monitored.
The MC34114's RAGC pin is grounded in this circuit, setting the transmit and receive gains to maximum.

~~~-+ H~S~2
_____

RING

MC145412

100 k

QP[ 17

~!~-

Figure 28. Pulse Dialer Circuit

RING

Figure 27. Tip/Ring Interface with a Power Supply
The +6 volt supply powers the MC34114through the
transformer winding. In this manner the speech signals
are coupled between the MC34114 and Tip and Ring.
The two diodes provide transient clamping, as does the
12 volt zener diode. The MC34118 and MC34119 are
powered directly from the +6 volt supply, eliminating
the need for the 1H choke. The SS switch (speakerphone
on/off) requires one more pole, as shown in Figure 27.
The tolerance on the + 6 volt supply is ± 0.5 volt.
Changes in the Switching and the Dialer
The use of a power supply simplifies the selection of
handset versus speakerphone mode of operation. The
diversion of the excess loop current is not an issue in this
circuit, so the switching of that current is eliminated,
along with 5.1 volt zener diode.
Because of the isolation requirement, the MC145412
dialer requires a relay to break the loop current during
pulse dialing. Figure 28 depicts this circuit.
The relay is normally off, and energized only for the
pulse dialing function. The 1 /LF capacitor (rated 250 volts
min., NPO) helps absorb the transients generated during
pulse dialing.

AN1004
4-144

The Complete Circuit with the Power Supply
The complete circuit is shown in Figure 29. The performance curves are shown in Figures 30-35. The Tip to
Ring dc voltage (Figure 30), determined solely by the dc
resistance of the transformer winding, is somewhat lower
than in the previous circuits at low loop currents. Figures
31, 32, and 34 show the performance is fairly constant
with loop current, except for a slight reduction in gain at
the higher currents. This is due to the characteristics of
the transformer used in developing this circiJit (model
#TTPC-13 from Stancor, Inc.). Also noticeable in the
curves, compared to Figures 13-18 and 21-26, is the lack
of loop length compensation - a natural consequence
of this type of circuit.
The muting specifications for this circuit are the same
as for the line powered circuit. The current required from
the +6 volt powe"r supply is as follows:
a) Handset mode: ""13 mAo
b) Speakerphone mode (no sound at the speaker):
""24 mA.
c) Speakerphone mode (max. volume at the speaker):
""144 mAo
Although Figure 29 indicates the use of a 25 ohm
speaker, any impedance speaker within the range of 8 to
50 n can be used, since this circuit is not line powered.
The receive gain may have to be adjusted, however, if a
different speaker is used.

MOTOROLA COMMUNICATIONS DEVICE DATA

s::

HSl

@

TIP

RLl

~~

VCC

Jl

o
s;:
()
o
s::
s::
c

RING ( )

r

1 ,

~~1

•....

0.0'

1 •

1

T

lN4742
12 V

VB
GND
3.9 Nf

MC34114
SPEECH
NElWORK

ZB

1M

z

(5

5P[

~

TSO
MC145412
DIALER

oz

KEYPAD

rn

o
m
<
(5

m

~
A
B

16 Rl
15 :
14 •

DTMf

:t 100 k

LI

118

~13k

VDD.
1 T100

o
~
»

MOl"

= I'f,

't:

~

TO CO
MC34"9

Va

Notes:
1) HS = Handset operated hookswitch - 3 poles.
55 = Speakerphone onloff switch - 2 poles.
Switches shown in on-hook position.
2) Microphone biasing resistor values
depend on the specific microphone

3) All diodes 1 N4002.

15

TL02 I RL02
.18 J... 19
121'fI21'f

-=-

-=

22
RXO
100 k
VOLUME
CONTROL

»

....

""z
"'0
""0

<11""

Figure 29. PulseiTone Featurephone w/Memory -

Powered From a Power Supply

MC34114/MC34118 Featurephone w/Power Supply

14

3. 2

/'
/"

r-- -

/'

:;;

V

~

~

V>

~ 0. 8
!::i

§;
O. 6

/'
/
2 /'
20

DTMF LEVEL AT TIP/RING

o.4
o.2
80
60
LOOP CURRENT (mAl

40

100

120

0

~ 37
z
10 Mil) and low bias current (+0.2 flA for the
MC34018, - 60 nA for the MC34118). Additionally, they
both function similarly in that the volume control operation is based on the ratio of the voltage at VLC to the
internally generated reference voltage (VB shown in Figure 1). The ratio is 1.0 (VLC = VB) for maximum volume,
and less than 1 for reduced volume. The minimum recommended setting is 0.55 VB for the MC34018, and 0.3
VB for the MC34118.

VB

I

VOLTAGE
REGULATOR

To achieve the same voltage range at VLC with a digital
circuit, a binarily weighted resistor network is employed
(see Figure 2).

TO
VLC
2R

4R

8R

Figure 2. Digital Volume Control Resistor Network

With all switches open, VLC equals VB (maximum volume). The minimum setting occurs when all switches are
closed, and the RB in Figure 1 is represented by the parallel combination of the four lower resistors (0.533R). The
exact value of the resistors will be determined later.

USING UP/DOWN SWITCHES
VLch
t > - r TO
~
ATTENUATOR
i-CONTROL
I
BLOCK

I
I

I
EXTERNAL ---i_INTERNAL

Figure 1. Analog Volume Control Interface

AN1077
4-156

Controlling the resistor network of Figure 2 is done with
the circuit of Figure 3. The four switches of Figure 2 are
replaced with the four outputs of the MC14516 Up/Down
binary counter and 1N914 diodes. Each of the resistors
is "on" when the corresponding output is low, and disconnected (by means of the diode) when the output is
high, providing 16 volume levels for the speakerphone.
The circuit may be used in a line-powered speakerphone,
or one which is powered from a power supply.

MOTOROLA COMMUNICATIONS DEVICE DATA

5-15 Vdc

....,.----...,-.---'r--,------,
16 VDD

»()-Q+"'13'--_ _ _ _...;.10"1 Uli)

5
9

MC14516

8

11
21
31
41

ALL DIODES lN914 OR EQUIVALENT.
ALL RESISTORS 118 W.
BYPASS CAPACITORS REQUIRED AT EACH IC.
GOOD CIRCUIT LAYOUT REQUIRED DUE TO HIGH
SPEED CAPABILITIES OF THE ICs.

Figure 3. Up/Down Free Standing Digital
Volume Control
The circuit works as follows:
• When one of the switches is closed, pin 13 of the
MC14044 RS flip-flop is set either high (for UP) or low
(for DOWN), and this sets the U/O input of the counter.
• Upon closing the switch, the 1.0 /IF capacitor is discharged (the 24 II resistor limits the current during
discharge), and pin 9 ofthe MC14044, and the counter's
ClK input are taken low (assuming the CO output of
the counter is high).
• Upon releasing the closed switch, the 1.0 /IF capacitor
will charge up slowly, and the ClK input of the counter
will switch high approximately 80 milliseconds later,
incrementing or decrementing the counter. The time
delay provides for switch de-bounce.
• When maximum count is reached while up-counting,
the CO output (Pin 7) switches low, preventing any
more clock pulses from reaching the counter. The CO
output returns to high when the U/O input changes
state (by pressing the DOWN switch). allowing the
counter to count down. A similar sequence occurs
when minimum count is reached while down-counting.
• The Preset Enable (PE) input receives an active high
pulse during power up, thus presetting the outputs to
1011 (in this example). In this way the speakerphone's
volume is set to a known state each time the phone is
taken off-hook. The preset level may be any of the 16
states by appropriately wiring P3-PO.
As the counter is sequenced up or down, the voltage
at VlC will vary between a maximum of VB and a minimum determined by the resistors (RA, R1-R4). The 5.0
/IF capacitor at VlC smooths the transition to the new
level, preventing clicks or pops from being heard in the
speaker. The power supply voltage can be obtained from
the Vce pin of the MC34118 (Pin 4). or from the VCC
output pin of the MC34018 (Pin 20). The circuit of Figure

3 requires less than 1.0 /lA of supply current when idle,
and typically less than 200 /lA during a transition.

CALCULATING THE RESISTOR NETWORK
The resistor network values will be calculated for each
of the three following situations:
1) The MC34018 speakerphone circuit, which has a fixed
VB of 2.9 Volts, and requires a minimum VlC of 0.55
VB (1.59 Volts).
2) The MC34118 speakerphone circuit with a fixed supply
voltage, resulting in a fixed VB equal to = (VCC 0.7)/2, and requiring a minimum VlC of 0.3 VB.
3) The MC34118 speakerphone circuit with a variable
supply voltage (such as in a line powered phone),
resulting in a VB voltage which can range from 1.3 to
2.8 V, and requiring a minimum VlC of 0.3 VB.
The reason for the differentiation between #2 and #3
above is due to the voltage drop of the 1N914 diodes
(=0.5 V), which is a significant part of VB. The voltage
drop of the counter's outputs, when a logic "0," is typically <10 mV, and is considered negligible. The resistor
network for situations 1 and 2 is shown in Figure 4. Situation 3 will require a slightly different circuit.
VB

r--"--+--t"'-;--

TO
VLC

lN914s
Ql

QO

Figure 4. Network for Constant Voltage VB Circuits

MOTOROLA COMMUNICATIONS DEVICE DATA

AN1077
4-157

Situation 1
For the MC34018, RA is selected to be 20 kfl, as that
is the same as the potentiometer's value shown in its
data sheet. The voltage at VLC is equals:
VLC = (VB - 0.5) x RB
20 k + RB

Q:rQo

05V

a
1
2
3
4
5

'"On'"
Resistors
Rl
Rl
Rl
Rl
Rl
Rl

A

VLC VLCNB

dB Gain Comments

R3 R4 1.57
1.61
R3
1.66
R4
1.71
1.75
R4
1.81

0.542
0.556
0.571
0.588
0.604
0.624

0.014
0.Q15
0.017
0.016
0.020

-25.5
-24.6
-23.5
-22.4
-21.3
-19.9

R4

1.87
1.94
2.02
2,11
2.21

0.645
0.669
0.698
0,728
0.761

0.021
0.024
0,029
0,030
0,033

-18.5
-16.8
-14,8
-12,7
-10,5

2,31
2,42
2,55
2,71
2.9

0,798
0,834
0,881
0,936
1,0

0,037
0.Q36
0.047
0,055
0,064

-7.9
-5,4
-2,2
+1,6
+6,0

Rl
Rl
R2
R2
R2

11
12
13
14
15

R2
R3 R4
R3
R4
None

R3 R4
R3
R4

VLCNB

A

dB Gain

1
2
3
4
5

0.296
0,306
0,313
0,322
0.332
0,347

0,010
0,007
0,009
0,010
0.Q15

-33,0
-29,4
-26,1
-23,1
-20,1
-17,0

6
7
8
9
10

0,740
0,783
0,796
0,856
0,915

0,361
0,375
0,389
0,417
0.446

0,014
0,014
0,014
0,028
0,029

-14,0
-11,0
-8.5
-5.6
-2,9

11
12
13
14
15

1,01
1,10
1,28
1,52
2,05

0,489
0,536
0,624
0.741
1.00

0,043
0,047
0,088
0,117
0,259

-0,4
+1.6
+3.6
+5,0
+5,8

a

R2
R2
R2
R2
R3
R3

6
7
8
9
10

VLC
0,607
0,628
0.643
0,669
0,680
0,712

+.

where RB is the parallel combination of the "on" resistors. To achieve a minimum VLC of 0.55 VB, RB calculates
to be 16.8 kfl. The "R" value for Figure 2 is then 16.8 kl
0.533, or 31.5 kfl. The next lower standard resistor value
of 30 kfl is then chosen for "R," which is R1 in Figures
3 and 4. Using standard values for the other resistors
yields R2 = 62 kn, R3 = 120 k!l, and R4 = 240 kn. The
resulting performance of this network is shown in the
following tabulation:

Q:rOo

Min
Volume

In this case, the fact that the step sizes are smaller at
the minimum volume end is particularly advantageous
since the MC34118 has a non-linear relationship between
the VLCIVB ratio and the amount of signal attenuation
(see Figure 5).

+10
Max
Volume

,

-10

The t. column indicates the difference in the VLCIVB
ratio as the count is increased. The steps are larger at
the high volume end compared to the low volume end.
It is believed that this is not objectionable in most applications, and in fact, some users consider it desirable. The
"dB Gain" column indicates the gain of the receive attenuator derived from Figure 5 of the data sheet.

~
2:

-20

'"

-30

«

-40
-50

Situation 2
For the MC34118 with a fixed supply voltage, the value
of the resistors will depend on the specific voltage used
for VCC. Since the minimum VLC is 0.3 VB, RA was raised
and the equivalent RB lowered (from the values of situation 1) to achieve the lower ratio. The values for the five
resistors can be found from the following chart:
VCC

VB

RA

Rl

R2

R3

~

MinVLCNB

6,5
6,0
5,5
5,0
4.5
4,0

2.8
2,54
2,29
2,04
1,79
1.54

39K
43K
47K
56K
39K
51K

15K
15K
15K
15K
7.5K
7,5K

30K
30K
30K
30K
15K
15K

62K
62K
62K
62K
30K
30K

120K
120K
120K
120K
62K
62K

0.298
0.298
0.303
0,296
0,296
0.301

AN1077
4-158

5,0 V yielded the

Testing of the circuit with VCC
following results:

I

.....

./

/"

-

L

"r

CIR~UIT IN R~CEIVE MIODE-

~~ MINIMiM RECOIMMENDiD LEVEL
~

I

0,2

0.4

0,6
VLC VB

0,8

1,0

Figure 5. Receive Attenuator versus Volume
Control- MC34118
As can be seen from the "dB" column (which is the
MC34118's receive attenuator gain setting), the step size,
in terms of the dB attenuation, is fairly constant throughout most of the range.

MOTOROLA COMMUNICATIONS DEVICE DATA

Situation 3
For the case where the MC34118 is used in a line powered speakerphone, VCC can vary from 3.5 to 6.5 V, with
a range for VB of 1.3 to 2.8 V. If the circuit of Figure 4 is
used, and set to provide a minimum VLCIVB ratio of 0.3
when VB = 2.8 V, the minimum ratio will be considerably
higher (=0.43) when VB is reduced to 1.3 V. From the
graph of Figure 5, it can be seen that the minimum gain
will then be -10 dB rather than - 33 dB. The problem
stems from the =0.5 V drop of the diodes, which is a
significant part of VB. To reduce the effects of this voltage
drop, the diodes are replaced with NPN transistors which
have a saturation voltage of only =0.05 V (see Figure 6).
The outputs of the MC14516 counter drive the 2N2222A
transistors through the 100 kll base resistors. Because of
the logic inversion of the transistors, the function of the
UP and DOWN switches of Figure 3 is reversed. Additionally, because of the inversion, the preset inputs
(P3-PO) must be changed to 0100 to achieve the same
power-up setting as that of Figure 3.
With the circuit of Figure 6, the minimum VLCIVB ratio
ranges from a low of 0.298 (VCC = 6.5 V) to a high 0.312
(VCC = 3.5 V). The tested performance of this circuit,
with VCC = 5.0 V, is as follows:

Qa-Clo

VLC

VLCNB

.1

dB Gain

0
1
2
3
4
5

0.615
0.645
0.674
0.709
0.755
0.800

0.300
0.314
0.329
0.346
0.368
0.390

0.014
0.015
0.017
0.022
0.022

-30
-26.5
-23.3
-20.4
-17.4
-15.1

6
7
8
9
10

0.847
0.904
0.970
1.04
1.13

0.413
0.441
0.473
0.507
0.551

0.023
0.028
0.032
0.034
0.044

-13.1
-11.1
-9.1
-7.2
-5.4

11
12
13
14
15

1.24
1.39
1.56
1.77
2.05

0.605
0.678
0.761
0.863
1.00

0.054
0.073
0.083
0.102
0.137

-3.5
-1.6
+0.7
+3.3
+5.9

IF YOU HAVE A MICROPROCESSOR . ..
If a microprocessor is included in the speakerphone
design, the above circuit can be simplified by letting the
processor do the switch de-bouncing, the up/down counting, and the off-hook preset. The critical part of Figure
3's circuit is the resistor network, and it can be controlled
from a port through a CMOS latch (see Figure 7).

MOTOROLA COMMUNICATIONS DEVICE DATA

r-------VB

,...-------t_-+-----l1-'VII"v-"V~,·no--+--I
Ci

sili

VOl

·~_~3

FCl

SPEAKER

C'l}'JLF FC2
=

V02

CD
CHIP
I-D--C DISABLE
1<0.8 VI

=

Pins 4, 5, and 8 are at the same DC voltage as Pin 3.

=

Figure 1. Normal Operation

AN1081
4-160

MOTOROLA COMMUNICATIONS DEVICE DATA

==u

r-_ _ _ _ _ _ _..::.6C,V..:C:;;:C_ _ _ _ _ _----,
AUDIO
INPUT

0.1

LEAKAGE
CURRENT

Ri

>1 !--'V\fIr-+-V,.-<'nJ
Ci

~_~3r-J1-1

FCI

Clt}I-'F

SPEAKER

=

MC34119

50 k

FC2
125 k
50 k

=

CD
CHIP
J-o-=---C DI SABLE
1>2.0 VI

=

Ci discharges through Ri, Rt, and RLK; the voltage at Pins 4, 5, and 8 droops.

Figure 2. Disabled Mode

Upon re-enabling the MC34119, bias is returned to the
op amps immediately, and op amp #1 finds the voltage
at Pin 4 somewhat lower than that at Pin 3. Its output (Pin
5) is therefore driven near the upper rail (VCC), and this
causes op amp #2 output (Pin 8) to be driven near the
lower rail (Gnd). The result is a large sudden voltage
change across the speaker, hence the "pop." The outputs
will then stay at these levels as Ci is recharged (by Pin 5
through Rf and Ri) until the voltage at Pin 4 is equal to
that at Pin 3, bringing op amp #1 back into its linear
operating region. Then the circuit is once again considered turned on. Figure 3 is a scope photo of the transient
across the speaker (Val - V02) when the circuit is enabled. For this photo, VCC = 6 volts, Rf = 270 k, Ri = 24 k,
Ci = 0.1 I-'F, and RLK = 5 MlL

THE SOLUTION? -

ONE RESISTOR

The solution involves keeping Ci from discharging in
the first place. By placing a resistor from Pin 3 to 4, Pin
3 will supply the leakage current, relieving Ci of that duty
(see Figure 4). Due to the voltage divider effect of Rx , Rf,
and RLK, Ci does discharge a sma!1 amount however, and
upon re-enabling, requires a small amount of recharge.
So the "pop" is not eliminated, but is considerably
reduced. Figure 5 is a scope photo of the same circuit
used for Figure 3, but with a 10 kll resistor added between
Pins 3 and 4. The combination of reduced amplitude and
pulse width means the transient energy has been reduced
by a factor of almost 12, thereby considerably reducing
the sound level of the "pop."
Experimentation has shown that values of 10 kll to
40 kll for Rx reduce the "pop" a very significant amount
(Note: quantifying the amount of improvement is difficult, and could have been done by using an SPL meter.
The real issue is what is an acceptable "pop," and what
is objectionable - a purely sUbjective matter). Values
greater than 40 kll have a progressively lower effect on
the transient amplitude. Values less than 10 kll can actually increase the transient, and can also interfere with the
normal operation of the amplifiers in the voiceband, most
notably distortion.

CONCLUSION

Figure 3. Output Transient Due To Leakage

MOTOROLA COMMUNICATIONS DEVICE DATA

Because of the possibility of contaminants on the PC
board, the "pop" can occur even if a "perfect" IC is used.
This solution will considerably reduce the problem, but
will not completely eliminate it. This is due to the voltage
divider effect of Rx , Rf, and RLK which allows Ci to discharge slightly during the disable mode. Most applications should, however, find this solution a sufficient
improvement to consider the problem resolved.

AN1081
4-161

Rt
.-------"WI.--s-V-C-C---------'==u, LEAKAGE
CURRENT
AUDIO
0.1
Ri
INPUT >-11--'VI1'v-..............O
Ci
Vin
SPEAKER
MC34119

50 k

C11)1J.lF

FC2
125 k
50 k

CD
CHIP
1-0-"---':: DISABLE
(>2.0 VI

The voltage at Pin 4 changes only slightly when disabled.

Figure 4. Disabled Mode With Resistor Solution

Figure 5. Output Transient With Resistor Fix

AN1081
4-162

MOTOROLA COMMUNICATIONS DEVICE DATA

MOTOROLA

-

SEMICONDUCTOR
APPLICATION NOTE

AN946

Limited Distance Modem
Using the
Universal Digital Loop Transceiver Chip Family
OVERVIEW
The introduction of the Universal Digital Loop Transceiver
(UDLT) family of integrated circuits aids the design of a high
speed Limited Distance Modem (LDM). With an external clock,
the LDM will transmit asynchronous data at rates up to 80
kbps. As shown here with an internal clock, the LDM can send
as much as 38.4 kbps of asynchronous full duplex data up to
two kilometers on 26 AWG twisted pair wire. The data
transfer is controlled by the following RS-232C handshake
signals: Request to Send (RTS), Clear to Send (CTS), Data Set
Ready (DSR) and Carrier Detect (CD). If the data link is
operating, CTS goes active in response to RTS going active.
DSR is active if the LDM is powered up. If synchronization is
lost, the CD signal goes inactive. Figure 1 shows a block
diagram of the LDM. Figure 10 is a photostat of the LDM
Demonstration Board - front, and Figure 11 is a photostat of
the LDM Demonstration Board - back. Table 1 is a parts list for
the slave and master LDM.

Differential Phase Shift Keyed (MDPSK) data burst is transmitted from the masterto the slave. Then after a slight delay, a
burst is transmitted from the slave to the master. Since an
eight kHz clock is typically applied to the Master Sync Input
(MSI) pin, and ten bits are sent to the master and the slave
every MSI period (every 1251's), the transceiver is effectively
transmitting 80 kbps of full duplex synchronous data.
The burst's ten bits of digital data are input on three
different pins of the UDLT master. The first eight bits are
serially received from the Receive Data Input (Rx) pin. The
ninth bit is from the Signaling Bit Input (SI1) and the tenth bit
is from the SI2 pin. These ten bits are formatted together and
shipped out from the chip on the LOl and the L02 pins (Line
Driver Outputs). After being transmitted across the line and
received on the LI pin of the slave UDLT, "eight bits of data are
serially output through the slave's Transmit Data Output (Tx)
pin, one bit on the SOl and one bit on the S02 (Signaling Bit
Output). Then the slave UDLT sends a similar burst to the
master UDLT.

UNIVERSAL DIGITAL LOOP TRANSCEIVER
The heart of the LDM is the UDLT master/slave chip set.
This chip set transmits data at a 256 kbps burst rate using a
"ping pong" approach. As shown in Figure 2, a Modified

DLTVS. UDLT
Since the MC145418/19 Digital Loop Transceiver (DLT)
chip set is very similar to the UDLT, it is not difficult to adapt

VOO

VOO

~300

t-.

OSR
MC145406

MC145422

S1
S1

OSR

S2
22
22

Figure 1, Limited Distance Modem Block Diagram

MOTOROLA COMMUNICATIONS DEVICE DATA

AN946
4-163

I-

MASTER
MSI

-.l

-I

125 p..
TRANSMIT

RECEIVE

r-

TRANSMIT

'--

@DLT

@UDLT

-I

SLAVE
@DLT

~TURN
I--l.D.

@UDLT

TEl

1

I-

RECEIVE
125

-I

p.S

LD. ; LINE DELAY

Figure 2. 80 kbps MDPSK Timing Diagram

ABB3S

10·BIT TRANSMIT BUFFER

SIGNAL BIT INPUT 1
SIGNAL BIT INPUT 2
r - - - - RECEIVE DATA

r--.-'--~~--r-.--'-~~

~----- RECEIVE DATA CLOCK

L-~~

__~-L__~-L~__~-,

' - - - - - RECEIVE ENABLE

RECEIVE REGISTER
TRANSMIT REGISTER

r - - - - TRANSMIT ENABLE

.-.--.--.--.--r--r-.--__~

~-----

TRANSMIT DATA CLOCK

' - - - - , . TRANSMIT DATA
_ - - - SIGNAL BIT ENABLE
' - - - - - - - - - -..... SIGNAL BIT OUT 1
' - - - - - - - - - - -.... SIGNAL BIT OUT 2

lO-BIT RECEIVE BUFFER

Figure 3. UDLT Receive and Transmit Registers

AN946
4-164

AA8929-1

MOTOROLA COMMUNICATIONS DEVICE DATA

this LDM to use the DLT. There are three main differences
between the UDLT and the DLT chips. The most important
difference between the chips is that the UDLT automatically
adjusts the thresholds on the receive circuitry. This allows the
UDLTto optimize its reception to a particular line's attenuation
level. The DLTs threshold is externally set, so typically this
receive optimization will not be achieved, unless some rather
complex circuitry is implemented. Also, the DLT requires
external drivers and transmits square waves instead of
triangular waves. In conclusion, the UDLT has on board driver
and threshold adjust circuitry, but the DLTs basic approach
allows driver and threshold design flexibility.
SIGNALING PINS FOR RTS/CTS HANDSHAKE
This LDM uses the S11, S12, S01 and S02 pins of the
master and slave for a RTS/CTS handshake. To perform this
task, the signaling channels are used for transmitting the
RTS/CTS handshake. The input at SI1 of the master UDLT is
the RTS signal. This information is transmitted to the S01 of
the slave UDLT chip. At this point, the signal is looped around
into SI1 of the slave UDLT, and it is transmitted to SO 1 ofthe
master UDLT. This signal at S01 is the master's CTS signal. A
similar configuration is used for the slave's RTS/CTS handshake on the SI2/S02 channel. This allows the RTS/CTS
handshake to verify that the communication link is operating.
DATA SET INTERFACE
Since most data from a terminal is an asynchronous format.
the Data Set Interface (DSI) is needed to convert data from an

asynchronous to a synchronous format and vice versa. At TxD
of the DSI, the asynchronous signal should begin with a start
bit (logic 0). After following with an eight or nine bit data word,
the format ends with one or more stop bits (logic 1). The rate
that the data is loaded into the DSI is determined by the
internal bit rate generator, whose rate, if 38.4 kbps or less, is
selected by BR1, BR2 and 8R3 (Baud Rate Select Pins). An
external bit rate generator can be used for data rates higher
than 38.4 kbps.
Once in the DSI, the data is stripped of its start and stop bits
and loaded in a register. Next, the data is checked for a break
condition, and one of three types of words is sent, under the
timing control ofthe DC, CM and DOE pins. If a break condition
is recognized, the break flag (1111111 0) is transmitted. If data
is in the register, it is dispatched. Finally, if no data is in the
register, a synchronizing flag (01111110) is sent. However,
regardless of data being in the transmit register, a synchronizing flag is also transmitted on a regular basis to verify that
synchronization is intact. Furthermore, the transmit circuitry
inserts a binary 0 after five continuous 1's of data, so neither
pattern, (11111110) or (01111110), can be sent as data.
At DCI, DC, CM and DIE control the synchronous data's
receive loading into the DSI. Once loaded, the DSl's receiver
determines if the data is break or synchronizing information. If
it is a break or synchronizing flag, the appropriate action is
taken. If it is not. the data is loaded into a receive register.
From this register, data words aretaken, start and stop bits are
added and the asynchronous word is output on RxD (Receive
Data) at the baud rate selected by BR 1, BR2 and BR3. Figure 4
is a block diagram of the DSI.

MC145428
DATA SET INTERFACE
Tx STATUS

Tx DATA
DATA STRIPPER

SYNCHRONOUS
CHANNEl

DATA OUTPUT

OATA/LENGTH

}""""'~

BAUD {
RATE
SElECT

DATA CLOCK

XI6 CLOCK

CONTROL

CLOCK OUT

RESET

STOP BITS
DATA INPUT
RECEIVER

Rx DATA

Rx STATUS
ASYNCHRONOUS 1/0

SYNCHRONOUS liD

Figure 4. DSI Block Diagram

MOTOROLA COMMUNICATIONS DEVICE DATA

AA9544·1

AN946
4-165

!~

m!

C12

7

Ul

~ NC- 9 *MC1489
13
NC- 8
4
NC- 10
1
NC- 2

VOO

R5

OSR 6

14

VCC

12 I--- NC
11
6

2.048 MHz

4 5
VCC+- 14 1 U4
MC74HC74 ~ f---

~

3
5 f-- NC

VCC

f---

8 I-- NC
9 I-- NC
10 I-- NC
11 I--NC

7

NC- 12

13

3

N1C

I

C3=f

1..5
6
VOo,r

Tx
RTS

2
4

CO
CTS
Rx

8
5
3

SG

7~

-

:II

o

o
s::
s::
c
z

C'i

16
15
13

In
~C14

~!

--1

12
10

en

o

~
C'i
m
o

~
»

5

1 f--NC
19 I--- s1'
18
17
15
14

J-

J---

1:
11 14

NC- 13
7
VSST 1

13
16
20

~10

2
3
U3
6 *MC1488 4 ----,.
8
5 ---.J
NC- 12

NC
VOO

I

9

Cl0
*MC14B9 and MC14BB used when MC145406 not used
**CB is optional filtering.
***TR 1 should be cut when C7 is used

J-

"IT'd

14

I

C

5

13

8

13
14
U7
11
MC74HC393
10
2
7
9
12
6

L

Rl

Xl

\ ....J
3

12 10 13 11

t=

Cl

l'

U6
MC14069UB

1

C2 _

128 kHz
8 kHz

Y

II

Nry

11 16
9
8 5 4
18
19
21
U8
2017
MC145422
14
R2
R3
12
C8**
15 7 6 3 10 22
2
1 13

1~~
.T

.... VCC

II

II

VCC

~~

~~ 01

~i

R~

11

8

~

-

9
12~

7

i

T1

R4

-

6

.4~ 02
!IT-!ITRAP

---I

C

4

4.096 MHz

U5
MC145428

11

!I:i

o
z

2
ST- 3
NC- 4

1

~

I

12

VCC

ST-6
ST-7
ST- 8
ST- 9

a
()

U2
9
MC145406

Cl:I8
VSS
2
4
'--6
3
5
7

s::

s;:

1

H4

Nt jC
8
[" 4

r--

OB·25

I I

N1C

T I

VCC = 5 V
GNO = 0 V
VOO AND VSS ARE DISCUSSED IN THE RS·232 SECTION

Figure 5. Master Limited Distance Modem

L

345

10

I

I

NC

NC

C7***
G

~

Cll

~

!;

8s::

1

z

(')

U1

14

-l- VCC

5z

R5

(J)

11

NC- 8
4
NC- 10
1
NC- 2

VOO

~

o
<
(')

7

~ NC- ~3 *MC1489
12 -NC

s::
c

~i

6
3
5-NC

U4
MC145428

m
OSR

»~

08·25

6

f--

o

Tx
RTS
CO
CTS
Rx
SG

Vo~r
2
4
8
5
3

1

U2
9
MC145406

C:1- 8
VSS
2
4
'--- 6
3
5
7

16
15
13

!np:ciO
VCC

11~
14
12
10

STSTSTST-

6
7
8
9

3

2
U3
6 *MC1488 4 ----,.
8
5 ----'"
N e - 12

22
U5
2
10 MC145426

C~

1

18
19

17

17

15
14
13

13
14

1:

~ VSST

20
16r--VCC ~ 12
51--

11
20

-

b8,
-=-

R3

ST- 11
ST- 4
NC- 5
16

Vcc

1

I

CIt-

21
8
9
15

°A~

R1

=:l-

14 TVOO

C8

ST - STRAP
NC - NO CONNECTION

VOO AND VSS ARE DISCUSSED IN THE RS·232 SECTION

*MC1489 and MC1488 used when MC145406 not used
**C3 is optional filtering.
***TRI should be cut when C6 is used

...., Z
>
-CD
gjit

Figure 6. Slave Limited Distance Modem

IC2

7

O;=- R4

-=-

11 -NC

1

*

I

VCC

102
R2

-

NC- 13
7

~

3

2
ST- 3
NC- 4

10
7!.1

-

1 r-- NC
19 r-- ST
18

12

m

I-

VCC

1
2

6
NC- 10
NC 5
9

::1:

Tc3**

T1

C6***
3
4

8

RS-232C DRIVER/RECEIVER

TRANSFORMER INTERFACE

The last integrated circuit discussed is the RS-232C interface. Either the MC 145406 or the MC 1488/MC 1489 Driver /
Receiver, which both fulfill the electrical specifications of EIA
Standard RS-232C and CCITT Recommendation V. 28, can be
used. The receivers invert the signal and convert the RS-232
signals to standard five volt logic levels, and the drivers invert
the signal and convert five volt logic levels to RS-232 voltage
levels.
The MC145406 is a CMOS RS-232 chip with three drivers
and three receivers. This chip operates with a five volt supply
and ±5 to ±12 volt supplies. Although the MC145406 chip will
work with ±5 volt supplies in most systems, the voltage
supplies should be at least ±7 volts to meet the RS-232 driver
specification. For full RS-232 compliance, the driver's output
must be between 5 volts and 15 volts for a logical 0, and it
must be between -5 volts to -15 volts for a logical 1.
The MC1488 is a quad line driver. For the MC1488 to
comply with the RS-232 driver requirements, a minimum
power supply of ±8 volts must be used. However, the chip will
operate effectively in most systems with the positive supply
voltage varying from +7to +15 volts. The MC1489 is a five volt
quad line receiver.

The transformer interface greatly affects the UOLTs capabilities. It performs the functions of impedance matching,
bandwidth limiting, increasing receive voltages to required
threshold levels and input protection. At 256 kHz, 26 AWG
wire's characteristic impedance is 110 ohms. The source
resistors from the L01 and L02 pins are chosen to be 220
ohms. With a transformer turns ratio of 2:1, the line side's
characteristic impedance is 110 ohms. This configuration
impedance matches the twisted pair.
The UOLTs minimum output voltage from the L01 and the
L02 pins is 2.25 volts peak. Half of the voltage is lost across
the 220 ohm source resistor. That voltage of 1.12 volt peak is
halved again by the 2:1 turns ratio of the transformer to 0.56
volts peak. At 256 kHz, 26 AWG wire attenuates a signal level
of 18 decibels-per-kilometer. After traveling a distance of two
kilometers the signal will have attenuated 36 deciDels. At the
line side of the transformer, the minimum signal level is 8.9
millivolts peak. A turns 'ratio of 1:4 in the transformer
windings brings the signal level up to 35.6 millivolt peak. This
voltage is divided between a resistor from the transformer to
the LI pin and an internal resistance. At worst case, 29
millivolt peak are at the LI pin - within the 25 millivolts peak
minimum allowed signal.
The UDLTs maximum voltage output is 3.0 volts peak.
Because of the voltage being halved by the source resistors
and the transformer windings, the transmit signal level althe
line side is 0.75 volt peak. With a short loop, the signal level
drop is negligible, so the signal level at the receiving transformer is about 0.75 volts peak. With the 1:4 turns ratio at the
receiving transformer, the signal level at LI will be 3.0 volts
peak, which exceeds the 2.5 volt peak maximum input at LI. A
signal level greater than 2.5 volts peak will inject current into
the UOLTs substrate. This action will distort the modulator's
output, thus creating bit errors. Consequently, protection
diodes and resistors are needed to clamp the input at LI. The
demonstration board's transformer configuration is shown in
Figure 8. The LI pin's protection includes a 1 kilohm resistor
between the LI pin and the diodes. This resistor is not on the

RS-232C CONTROL AND SIGNALS
As seen in Figure 5, the master LOM schematic, and Figure
6, the slave LDM schematic, asynchronous control and data
signals enter the LDM at RS-232 voltage levels through a
DB-25connector. Figure 7 shows a OB-25 connector which is
the standard computer terminal connector. Pins 2,3,4,5,6,7,8
transmit the following information:
Pin
Pin
Pin
Pin
Pin
Pin
Pin

2:
3:
4:
5:
6:
7:
8:

Transmit Data (Tx)
Receive Data (Rx)
Request to Send (RTS)
Clear to Send (CTS)
Data Set Ready (DSR)
Signal Ground (GNO)
Carrier Detect (CD)

The Tx and RTS signals are fed into the receivers, and the Rx,
CTS and CD signals are outputs of the driver. For the CD
signal, oQe of the receivers inverts the signal from the RxS pin
of the OSI. When the OSI is in asynchronous status, this
inversion gives the CD a logic O. The output of that receiver is
then put into a driverto obtain RS-232 voltage levels. The DSR
pin is connected to the RS-232 positive power supply through
a 300 ohm resistor. Therefore, DSR will go active whenever
the power supply is on. The GND pin is connected to the
system's ground. The remaining pins used of the DB-25
connector are routed to the RS-232 Driver/Receiver.

R2

L01

n=2

------~~----~_.

n = 0.5
,..---------- TIP

L02

------~~----.....--'

II

---v~--,-~vv----,

L =1.75 mH

1k

13 12

11

10

9

8

7

6

5

4

3

2

1

0000000000000

L-_________

RING

n = 0.5

000000000000
25 24 23 22 21 20 19 18 17 16 15 14
Vref - - - - - - - - - - - '

Figure 7. D8-25 Connector

AN946
4-168

Figure 8, Transformer Configuration Used in
LDM Schematic

MOTOROLA COMMUNICATIONS DEVICE DATA

demonstration board. Typically, the external diodes will turn
on before the chip's internal diodes, so the external diodes will
shunt most of the current. However, the 1 kilohm resistor will
further ensure that the external diodes turn on first.
The maximum power bandwidth of the UDLT is 8 to 512
kHz, but to improve line settling, it is desirable to use a 20 to
512 kHz bandwidth. To make the lower corner of the bandwidth 20 kHz, the inductance of the transformer windings is
chosen to be 1.75 millihenries. To make the upper corner of
the bandwidth 512 kHz, a 0.001 microfarad capacitor is placed
in parallel with thetransmittap.lfbatteryfeed is used, further
input protection is advised. Figure 9 shows a more durable
transformer configuration. Transformers fulfilling these specification can be obtained from:
Leonard Electric Products Company
85 Industrial Drive
Brownsville, Texas 78521
Part Number: PIN P-1358-A
+5 V

110
PIN 21 -'I/VI,,-.....-'VV'..-.--,

lOi
...-_ _ _ _... TWISTED
PAIR
110
PIN 20 -"""'~+--,\N'v___...J
l02

TO SAmRY

lk
PIN 3 -J'I/VI~+--,\N'v---,
11

LDM BOARD OPTIONS
A picture of the LDM demonstration board is shown in
Figure 10 and 11. Many of the UDLT and DSI features are
made available on the demonstration board using straps.
These UDLT features include:
LB: In the master, a low disconnects the LI pin from the
internal circuitry, drives L01, L02 to Vref and internally ties
the modulator to the demodulator. In the slave, a Iowan the
LB pin makes the incoming demodulated data going to Tx
repiace the incoming data on Rx.
PO: A low powers down the UDLT, except for the receive
circuitry.
The DSI features that can be controlled using the straps
include:
SB: A low selects outputting one stop bit per data word, and
a high selects outputting two stop bits.
DL: A low selects operating with eight bit data words, and a
high selects operating with nine bit data words.
Reset: A low clears the internal FIFO, disables TxD, and
forces TxS and RxS low.
BR1, BR2, BR3: These pins select the asynchronous data
rate.
For more information, refer to the individual data sheets. The
top of the LDM board shows suggested straps for these
functions. These straps select one stop bit, an eight data word,
an inactive Reset, a 9600 baud asynchronous data rate, an
inactive loop-back and an inactive power-down.
For battery feed applications, C6 of the slave LDM and C7 of
the master LDM can be inserted, and the trace between these
pins should be broken. This capacitor allows ac signals to pass
through the transformer, but keeps dc power across the
capacitor to be fed into the system's power supply. C3 of the
slave LDM and C8 of master LDM provide filtering for the
upper corner of the bandwidth. If this filtering is not desired,
these capacitors may be omitted, but their insertion is
recommended.
CONNECTORS

L-_ _ _ _. . .

PIN 2 _ _ _ _ _-+-_--'

V,ef

TWISTED
PAIR

l = 1.75 mH
C = 0.001 I'F

Figure 9, Battery Feed Transformer Configuration

MOTOROLA COMMUNICATIONS DEVICE DATA

On the demonstration board, VSS and VDD are only used to
power the RS-232 circuitry. VSS is the most negative power
supply, and VDD is the most positive power supply. The
RS-232C DriverIReceiver section explains the appropriate
voltage ranges for using either the MC145406 or the
MC1488/MC1489. VCC is the board's five volt supply, and
GND is the board's digital ground. Tip and Ring are the
connections for the twisted pair wire. The 25 pins on the left
side of both the slave and'the master board is for the DB-25
connector.

AN946
4-169

-5V
VCC

VOO

VSS

GNO

Ul

~

ItC11

0
0I
-0
_
~

Cglt

~I

U2

I .
.
Ii'
.
.'"
!l!

U3

- Q;~~
::

~

~

c
Ii'

C8

RING

U5

U'

T,O

-

0

it

C2

I

,!
w

=

9~ ~Ii'~

C7

It

III
Reset

PO

C5

~c ~
a:

*~ 9~

n

C6
Tl

0

C3'

LB
TIP

MOTOROLA

Slave

UCLT

Limited

Distance

VSS

Modem

Demo

-5V
VCC

VOO

0" 0
~0
0 -~

I

Cl'

U6

)

C13t1

;

5"

,i~1i' - 0

'"'"

N

U8

~

U3

c

Limited

Distance

"

TIP

T1

=~
):30
c.

02

~
~
~

.'"

m

tOl~

~8

U5

~

Il
:11

~
~

RTS

~

I

Po

U7

illS

UDLT

.

r

04

Master

GNO

C12

Ul

MOTOROLA

618-1065

Board

n
128K

...c=R2

U
0

nil

-c=R3

co

Modem

0
RING

Demo

Board

e18-1066

NOTE: Drawings are not actual size.
Figure 10. Photostat of LDM Demonstration Board - Front

AN946

4·170

MOTOROLA COMMUNICATIONS DEVICE DATA

*External to the demonstration board-back. pin 6 of the MC74HC74 should be connected to pin 16 of the MC145422

NOTE: Drawings are not actual size.

Figure 11. Photostat of LDM Demonstration Board - Back

MOTOROLA COMMUNICATIONS DEVICE DATA

AN946
4-171

Table 1. Limited Distance Modem Parts List

Master LOM

Slave lOM

Rl: 10Mn
R2: 220n
R3: 220 n

R4: 10kn
R5: 300 n

Rl: 10Mn
R2: 220 n
R3: 220n

Cl:
C2:
C3:
C4:
C5:
C6:
C7:

C8: 1000 pF
C9: O.lI'F
Cl0: 0.1 I'F
Cll: O.lI'F
C12: O.II'F
C13: 0.1 I'F
C14: O.II'F

Cl:
C2:
C3:
C4:
C5:
C6:

D2: lN914

01: lN914

20pF
20 pF
O.lI'F
O.lI'F
O.lI'F
0.1 I'F
1.01'F

01: lN914
Xl: 4.096 MHz

Xl: 4.096 MHz

Ul:
U2:
U3:
U4:
U5:
U6:
U7:
U8:

Ul:
U2:
U3:
U4:
U5:

MC1489
MC145406
MC1488
MC74HC74
MC145428
MC14069U8
MC74HC393
MC145422

T1: lepeD PIN P-1358-A

AN946
4-172

20 pF
20 pF
0.001 I'F
O.lI'F
O..lI'F
1.01'F

R4: 10 kn
R5: 300 n
C7: 0.1 I'F
C8: O.lI'F
C9: O.II'F
Cl0: 0.1 I'F
Cll:0.lI'F

D2: lN914

MC1489
MC145406
MC1488
MC145428
MC145426

T1: lepeD PIN P-1358-A

MOTOROLA COMMUNICATIONS DEVICE DATA

_

MOTOROLA

SEMICONDUCTOR

APPLICATION NOTE

AN948

Data Multiplexing
Using the
Universal Digital Loop Transceiver and the Data Set Interface
INTRODUCTION
Data multiplexers find applications where clusters of terminals are connected to a central computer and in systems
where modems are pooled at a common location. Combining
the signals from the various terminals onto one multiplexed
data link simplifies wiring and reduces expenses. Sharing the
cost of the multiplexer among the several terminals results in
a lower net cost compared to installing and maintaining
individual cables for each terminal. While present day multiplexers are economical, new ICs from Motorola make possible
enhanced performance multiplexers for a fraction of the cost
of existing devices.
This Application Note will describe the design of a shorthaul multiplexer for asynchronous data at rates up to 9600
baud. The mux combines eight full-duplex data channels
along with eight end-to-end RS-232 control signals onto a
single pair of telephone wire for distances up to 2 km.
Motorola's Universal Digital Loop Transceivers (MC1454221
26 UDLTs) master Islave high-speed synchronous data transceivers and Data Set Interface (MC145428 DSI) full-duplex
asynchronous to synchronous converter form the heart of this
multiplexer. A few MSI CMOS ICs complete the design.
Figure 1 illustrates a typical system with the terminals in a
departmental situation multiplexed onto one high-speed data
link. RS-232 control signals are passed transparently through

the multiplexer so the terminals have direct access to the
controls of the modems. This multiplexer system transports
one control signal bidirectionally for each data channel. As
will be described below, other configurations may easily be
constructed with simple wiring changes.

CHARACTERISTICS OF THE UDLTs
The UDLTs are synchronous data transceivers capable of
transporting 80 kbps of full-duplex data over ordinary twisted
pair 26 to 19 gauge telephone wire at distances of up to 2 km.
These devices utilize a 256 kilobaud MDPSK ping-pong burst
modulation technique for transmission. Three logical data
channels, one of 64 kbps and two of 8 kbps each are
exchanged in bursts of 10 bits every 1251-'s frame. MDPSK
timing is shown in Figure 2. The master initiates a ping-pong
frame by bursting 10 bits of data tothe slave beginning on the
riSing edge of an externally generated Master Sync Input
(MSI). The modulator'S analog output signal (L01, L02) is
shown referenced to MSI. Upon receiving the last bit from the
master, the slave responds with a 10 bit burst of its own after a
four baud delay. The slave's modulator output (LO 1, L02) is
shown referenced to its own Transmit Enable 1 (TEl).
Depending on the transmission line characteristics and
length, the actual time of arrival of the slave's return burst at
the master will vary due to the propagation time of the signal

TERMINAL

o

•

MODEM
7

•
•

•
•
•
•

•
•

TERMINAL
7
MULTIPLEXER

Figure 1. Typical Multiplexer Application

MOTOROLA COMMUNICATIONS DEVICE DATA

AN948

4-173

I~~--------------------------125~S--------------------------~~~1

MASTER

MSI

~

TRANSMIT

I

RECEIVE

RECEIVE

~_

_-----,Ir---

MODULATOR
OUTPUT
(LOI. L02)

SLAVE

MODULATOR
OUTPUT
(L01. L021

TEl

TRANSMIT

L

Figure 2. UDLT Timing

between UDLTs. On excessively long lines. propagation time
down the transmission line results in collisions between the
master and slave bursts so maximum line length is limited to
2 km with 26 gauge wire. The slave's TEl is generated
internally upon completion of demodulation of the burst from
the master. TEl remains high for eight data clock (128 kHz)
periods and returns low until another burst is received. This
process is repeated every 125 p.s. Since both master and slave
devices exchange data every frame in a half-duplex manner at
a 256 kilobaud rate. an effective fUll-duplex rate of 80kilobaud
is accessible to the user.
The bursts of data on the transmission line use Modified
DPSK signals to reduce EMI and susceptibility to crosstalk
from other signals in telephone cables. The frequency spectrum consists of peaks at 128 kHz and 256 kHz and their odd
harmonics. Only a small amount of energy is present in the
frequency bands used by analog telephone service. so UDLT
signals may be placed on adjacent pairs in cables with
ordinary telephone sig'nals with no degradation of performance. The power spectral density at 76 kHz is approximately
18 dBm and at 28 kHz the level is less than -30 dBm. Because
there is no signal energy at very low frequencies. dc energy
may be transported on the transmission line to power the
remote multiplexer unit. Details of this feature will be
described later.
The UDLTs have internal buffers to store and prepare
synchronous data for transmission. Eight bits for the 64 kbps
channel are serially input and output every 125 p's frame. The
two 8 kbps channels each have one bit input and output every
frame. The master and slave UDLTs synchronous timing is
shown in Figures 3 and 4 respectively. Both figures illustrate
the transmit and receive timing for the eight bit words on Tx

AN948
4-174

and Rx, and the timing for the two signalling bits, both inputs
(SI1, S12) and outputs (SOl, S02).
The master UDLT timing shown in Figure 3 requires
external timing signals of 8 kHz for MSI, TEl, RE1, and 64kHz
up to 2.56 MHz may be used for the TDC/RDC pin. This
application uses 128 kHz. Eight bits of the 64 kbps data
channel received from the slave are output on the Tx pin on
the first eight rising edges of TDC/RDC while TEl is high.
Data to be sent to the slave is input on the Rx pin on the first
eight falling edges of TDC/RDC while REl is high. In this
application TEl and REl are connected together so data is
input and output simultaneously. Data on the 8 kHzsignalling
channels are input on Sil and SI2 pins and output on SOl and
S02 pins on MSI's rising edge.
The slave UDLTtiming (shown in Figure 4) is similar to the
master except that the slave synchronizes to the master's
bursts and generates its own clocks and enables. The eight
bits of the 64 kbps data channel received from the master are
presented on the Txpin on the rising edges of CLK while TEl is
high. Data to be transmitted to the master is loaded in on the
Rx pin on the falling edges of CLK while REl is high. Signalling
bits onthe 8 kbps channels to and from the master are input at
S11, SI2 and output at SOl, S02 on TEl's rising edge.
The master UDLT has pin controlled Power-Down (PO) and
Loop-Back (LB) features which can be used for system testing.
Also available on the master is Signal Insert Enable (SIE)
which enables the insertion and extraction of an 8 kbps
channel into the LSB of the 64 kbps channel. In this
application SIE is unused and held low. The signal enable pin
(SE) is a three-state control pin which when held high enables
PO, LB, and the two signalling bits (SOl and S02) allowing
these signals to be bussed to a microprocessor.

MOTOROLA COMMUNICATIONS DEVICE DATA

1~~~--------------------------------125~S--------------------------------~·1
MSI

J

r-

~--------------~I

TOC/ROC

THREE· STATE

Tx

TEL REl

Rx

J

~

______________~r_

~_______________O_ON_'T_C_A_RE______________~X

S11, SI2

VALID

SOl,S02 ==x~

X'--________________________O_O_N'T_C_A_RE____________________-----'~

_____________________________________

~~

Figure 3, Master Timing

~---------------------------------125~S--------------------------------~·1
I~
TEl

~

J

________________~r_

ClK
THREE·STATE

Tx

REl

Rx

S11, SI2

SOL S02

l

X

~ON'T CARE

=

L

~--------------~

VALID

X'--_________________O_O_N'_T_CA_R_E__________________~

-:J..~---------------------------------------------~
Figure 4, Slave Timing

MOTOROLA COMMUNICATIONS DEVICE DATA

AN948
4-175

i">
.... z

GI!

+12V

+5V

Voo

VCC

MC1454D6
RS-232
DRIVER/RECEIVER

OSlO
+5V

Voo
CM

+5 V

MC145422
MASTER UoLT

110n

~LDI

110n

~LD2

VSS

CHO EN

J
128 kHz

[8

~
~
~

~

Rx DATA

oTR
CHANNEL 0
oSR

RxS

ers

i=~~~~1 111-+-1- :-------': :
f-----I--H

+5V
+5V

VS8

CH7 EN

+5·V

-12 V
+12 V +5 V

BRCLK

oCI
IDlE
ODE
OCO
BC
'-----I. DC
Vss

5B
oL
BR3
BR2
BRI
TxS
Rx5

III,

'-+------ll

~~I-I----'

Tx DATA

II II

z

CHANNEL 7
oSR

ers

Tl: Lepco PIN P·1358·A

o
~

~
en

c

~

om
c
?i»

Rx DATA

oTR

3:

c:

MC145406
RS-232
DRIVER/RECEIVER

MC145428
Voo

~~

SEQUENCING AND
SlGNAWNG
(FIGURE 7)

GNo

.-----r-

oSI7

-=+5V

I

CHO

802

PO

------,I

1--1

rl-t-I I - I
I I!H- .- - - - lfM~ ~

~l ~

5kn

BRCLK
Txo

4.096 MHz

Tx
Rx
TOC/RoC

~u

Tx DATA

MC145428

-12 V

Figure 5. Master Unit Interconnect

s::

~
~

>

<12 V <5 V

(")

o

s::
s::
c

DSIO

'~

z

o
~
o
z
en
o
~

om
o

~

+5 V

MC145426
SLAVE UDLT

+5 V

I-----i

VDD
,-,--'VI."r-+-----'\'VV---1 L01

CHO OOE t-J
CHO DIE f--

Tx

»

Rxl--~

CLK
TE
Mu/A
TEl

L02

·~1

u

SI1
SI2
S02 1 - - - - - - 1
PO
+5 V
iii
+5V

In

4.096 MHz

~Olt
q 2 2 PF

Tl: Lepco PIN P-135B-A

-=-

Tx DATA

MC145428
VDD
CM
RST
DCI
DIE
DDE
DCD
BC
DC

BRClI(
TxD
RxD
SB
DL
BR3
BR2
BRl
TxS
RxS

VSS

RX DATA
DTR
CHANNEl 0
DSR

CTS

128 kHz
CHO SIG IN
CHO SIG OUT
:
•

1-1----IIH-I-+1...:11--------------

••

•

I III I

CH7 SIG IN
CH7 SIG OUT 1 - - - I - + - l H - - - - - - - - - - - - - ,
CH7DOE
CH7 DIE

t--

h

SEIlUENCING AND
SIGNAlliNG
(FIGURE 81

-12 V
<12 V +5 V

DSI7
+5 V

X2
10M

V~D vJc I

'-------i

-f1

MC145428
BRCLK
TxD
RxD
SB
DL
BR3
BR2
BRl
TxS
RxS
VSS

Rx DATA
DTR
CHANNEl 7
DSR

VSS
-12 V

Figure 6_ Slave Unit Interconnect

.co.:!>
,Z

::It

MC145406
RS-232
DRIVER/RECEIVER
Tx DATA

VDD
CM
RST
DCI
DIE
DOE
DCD
BC
DC

GND

~

"'CD

MC145406
RS-232
DRIVER/RECEIVER

TRANSFORMER INTERFACE
The duplexer function, separating transmit and receive
bursts on a single twisted pair wire is automatic with UDLTs.
The receiver input is blanked while the transmitter is active so
the transmitted signal is ignored by the demodulator circuits.
The receiver unblanks when the transmitter finishes its burst
to search for the return burst from the other end. Automatic
duplexer action allows a simple transformer to be used for the
interface between the transmission media and UDLTs shown
in Figures 5 and 6. The transformer Tx winding and the
associated padding network match the transmitter output to
the impedance olthe transmission line. The Rx winding steps
up the signal from the far end to compensate forthe loss in the
matching network. The characteristic impedance of twisted
pair telephone wire in the frequency range used by the UDLTs
is approximately 1100hms. Matching this impedance requires
resistors of 220 ohms in each leg of the Tx winding. The
impedance of 440 ohms when transformed through a 2:1
turns ratio results in a match to 1100hms. 12 dB of loss is also
introduced. The 12 dB is made up in the Rx winding which has
a 4:1 step-up from line to receiver input.
Protection of the UDLTs against transients induced onto the
transmission line is accomplished by adding clamp diodes to
the padding networks. It is convenient to split the 220 ohm
resistors into two 110 ohm resistors and place the clamps at
the junction of the resistors. The same technique is used at
the receiver inputs.
CHARACTERISTICS OF THE OSI
The DSI is a device which provides full-duplex asynchronous to synchronous conversion. It allows the user to
select asynchronous data formats and baud rates. The
synchronous port has selectable timing for easy interfacing to
a variety of systems. The asynchronous port characteristics
are controlled by the Stop Bit select (SB), Data Length select
(DL), Baud Rate select (BR1-BR3) pins. Synchronous data is
under the control of the Data Output Enable (DOE), Data Input
Enable (DIE), Data Clock (DC), and Clock Mode (CM) pins.
Asynchronous data is sampled at 16 times the selected baud
rate. Logic circuits search the asynchronous data for a start
bit, eight or nine data bits and one or two stop bits. When valid
start and stop bits are found, they are removed from the
character and the remaining eight or nine data bits are loaded
into the transmit FIFO for transmission on the synchronous
port. The Tx Status pin goes low when the transmit FIFO is
more than half full. This signal may be used for a local ClearTo-Send indication to the data device on the asynchronous
port. Special characters are generated and transmitted on the
synchronous port to synchronize the receiver of the remote
DSI to the ch"racter boundaries. At the remote DSI synchronous data is reassembled into eight or nine bit characters,
start and stop bits are added and the data is transmitted out on
the asynchronous port.
Since start and stop bits are removed from the asynchronous data before transmission on the synchronous port,
some data compression is achieved. For example, asynchronous data at 9600 baud with eight data bits and one stop
bit is compressed to 7680 baud on the synchronous channel.
This makes possible the use of an 8 kbps synchronous
channel to transport 9600 baud data. However, since sync
and break characters consisting of data patterns 01111110
and 11111110 respectively are exchanged between DSls

AN948
4-178

every so often, the effective data compression is somewhat
reduced. Zero bit insertion on the synchronous data between
DSls is used to eliminate the possibility of data imitating either
of these characters (the inserted zeros are removed by the
synchronous receiver). The multiplexer allocates the UDLTs
64 kbps synchronous channel to each DSI for one 125 J1.S
ping-pong frame out of every 1 ms data frame. This results in
an 8 kbps synchronous channel for each DSI. Under certain
circumstances, with binary data, zero insertion may cause the
transmit FIFO to overrun. If hex 'FF' characters are input to the
DSI on the asynchronous port at 9600 baud with minimum
time between characters, inserted zeros and sync characters
cause the effective data rate to increase from 7680 baud to
approximately 9400 baud. Since the synchronous channel
supports only 8 kilobaud, an overrun of the Tx FIFO will
occur. The TxS pin will go low approximately 5 ms before an
overrun occurs and this indication may be used to stop the
flow of new asynchronous data until the FIFO clears out.
When ASCII data is used, only 6 characters (>(3E hex),
?(3F hex), 1(7C hex), -(7E hex), DEL(7F hex), and Blank(7D hex))
generate stuffed zeros. Fortunately, it is unlikely that these
characters will be sent in large enough groups to cause FIFO
overruns. In applications where ASCII data is transported,
eight 9600 baud channels may be multiplexed onto this
system's 64 kbps synchronous channel. If binary data is
transported, a 16 kbps synchronous channel must be allocated
for each DSI, resulting in a four channel multiplexer. This
guarantees that even with maximum zero insertions, FIFO
overruns will not occur.

OCTAL MULTIPLEXER SYSTEM DESCRIPTION
This multiplexer system fully exploits the DSI chips and the
UDLTtransceiver pair. The UDLTs 64kbps channel transports
the synchronous data from the DSls. One of the UDLTs 8 kbps
channels is used to synchronize the multiplexing of the eight
data channels, and the other 8kbps channel is used to
transport eight RS-232 control signals.
The multiplexer system consists of two units, a master and
a slave. Figure 5 illustrates the interconnection of the various
devices within the master unit. The transformer interface to
the twisted pair is shown with the previously described
impedance matching and protection circuitry. The master
UDLT is shown with the Tx, Rx lines along with the 128 kHz
and the 4.096 MHz clocks bussed to the eight DSls. The data
channel enables and signalling lines are shown connecting
the DSls and the RS-232 driver Ireceivers to the sequencing
and signalling block. Each DSI is shown configured for 9600
baud with eight bit character lengths and one stop bit which
may be made switch selectable, if desired.
Figure 6 shows the complementing slave unit. Protection
circuitry and the transformer interface are the same as the
master unit. The slave UDLT generates its own clocks derived
from an on-chip crystal oscillator circuit. An inverter is used to
drive the eight clock inputs to the DSls. Also shown is the
sequencing and signalling interconnect to the DSls and the
RS-232 driver Ireceivers.
Circuitry in the sequencing and signalling blocks is shown
in Figures 7 and 8 for the master and slave units respectively.
All pertinent timing of the multiplexer system is shown in
Figure 9. Master timing is shown in the top section, master
and slave bursts on the twisted pair are shown on the line

MOTOROLA COMMUNICATIONS DEVICE DATA

labeled 'Transmission Line'. Slave timing is illustrated on the
bottom half of the figure.
Clocks for the master UDLT are created by a 12-stage ripple
counter (MC74HC4040) which is driven by a 4.096 MHz
crystal oscillator. Taps at aI, 05, and 09 create the 2.048
MHz (CCI), 128 kHz (TOC/RDC) and 8 kHz (MSI,TE1,RE1)
clocks respectively. Inverters are needed on each line so the
rising edges coincide. A pulse which synchronizes the master
and slave data channel sequencing circuitry is generated
when a count of 0 is reached by 010, all, and 012 of the
ripple counter. This pulse is shifted through the enable shift
register (MC14015B) to create eight non-overlapping enables
forthe DSls. A latch (MC14013B) is used to delay the pulse so
that it can be properly input into Sil of the UDLT on the next
rising edge of MSI. The delayed pulse on Sil and the data
channel enables (CHO-CH7 DOE, DIE) are shown on the
timing diagram. RS-232 control data is routed to a latch by an
addressable data selector (MC14051B). RS-232 control data
received from the slave unit is written into an addressable
latch (MC14051 a). Notice thatthe first 00 ofthe shift register
is the enable tothe DSI of data channell. Since the sync pulse
arrives at the input of the shift register slightly after the clock,

a one-channel offset is used to address the proper channel.
This offset is transparent to the system.
Data input on the Rx pin of the UDLT is buffered until the
next rising edge of MSI, when it is burst out on the
transmission line. Data on Sil and SI2 are latched in on the
rising edge of MSI and transmitted in the burst which was
initiated by that MSI edge. The bursts from the master (boxes
with M) and the return bursts from the slave (boxes with S) on
the twisted pair wire are illustrated on the 'Transmission
Line'. The numbers indicate which channel's data is transported in that burst.
The system sync pulse arrives at the slave unit on the SOl
pin of the UDLT (Figure 8). It is shifted through a shift register
(MC14015B) which is clocked by the REI pin. The a's from
this shift register enable the transmission of data from the
DSls to the UDLT. The sync pulse is delayed and shifted
through another shift register clocked by TEl. The a's from
this shift register enable the DSls to accept data from the
UDLT. RS-232 control data is handled in the slave unit in a
similar manner as the master with a data selector and an
addressable latch. Simply offsetting the connections to the
RS-232 driver/receivers realigns the data to the proper

4.096 MHz

----iOI--

MC140l5B

4.096 MHz CLOCK
GENERATOR

MC74HC4040

_
CCI
TOC/RDC
MSt TEl, REl

-

2.048 MHz

-----<><

110 I--111 I - 112 I - 113 I- .--

-0

r - RST
=L...-_l1rl__l1r5_I1,9_'l1rl0-,I1,l1_I1,l_2- '

~- ---001- 111 I- 112 I- 113 I- -

-I>

I

DIE
DIE
DIE
DIE
DIE
OlE
DIE
DIE

AND
AND
AND
AND
AND
AND
AND
AND

DOE
DOE
ODE
ODE
ODE
ODE
ODE
ODE

CHANNEl 1
CHANNEl 2
CHANNEl 3
CHANNEl 4
CHANNEl 5
CHANNEl 6
CHANNEl 7
CHANNEl 0

128 kHz

---_----+----

RST

I-

~LC_E_________11~4~>O--------------l
soi - - - - - - - - - - - - - - - - - - - - - - - - - - - 1

C
B
A
WD
y

XO
Xl
X2
X3
X4
X5
X6
X7

-

CHANNEl 0
CHANNEL 1

- . CHANNEL 2
-

CHANNEL 3
CHANNEL 4
CHANNEL 5
CHANNEL 6
- ' CHANNEL 7

SIGNAL OUT TO
RS·232 DRIVER

Figure 7, Master Sequencing and Signalling

MOTOROLA COMMUNICATIONS DEVICE DATA

AN948
4-179

channels eliminating any superfluous circuitry. Offsetting the
connections to the data selector (MCl4051 B) similarly aligns
the channels so that the data arrives at the master in the
correct time slot. Following the channels on the timing
diagram illustrates the concept.

This multiplexer, because it is all CMOS, consumes only
about 175 mW per unit. One of the units may be powered by
dc energy transported on the transmission line itself eliminating a power cord. The line interface transformer is designed to
pass dc energy by separating the two line windings and
installing a 1 p.F capacito'r between pins 2 and 3. Now, dc
current may be passed to the twisted pair. A switching power
supply may be installed in the remote unit to convert the line
power to voltage levels useable by the digital circuitry. Recall
thatthe dc resistance of 2 km of 26AWG wire is approximately
575 ohms. This necessitates a relatively high voltage on the
sending side to keep the 12R losses in the twisted pair to a
tolerable level. Usually 36to 40 volts is satisfactory to furnish
enough voltage to the remote unit. Since the transmission
line is balanced, there is no ground reference between master
and slave units. dc power to the twisted pair must be fed from
an isolated winding on the mains transformer, so that a
ground reference may be established at the remote unit.
Connecting the ground references of the two units through
the ~wisted pair will result in poor 'data performance due to
longitudinal currents in the line.

ADDITIONAL CONSIDERATIONS
This multiplexer design is quite modular. If RS-232 control
signalling is not desired then the circuitry can be simplified by
removing the write pulse generator (MC14022B), addressable
latches (MC14099B) and data selectors (MC14051B) from
both units. The address generator (MC14163B) on the slave
unit may also be removed. In applications where data rates of
less than 9600 baud are used, the Baud Rate select pins on
the OSls need simply be reconfigured. A DIP switch can be
conveniently used to set the Baud Rate, Data Length and Stop
Bit pins on the DSls. Note that the DSls must not be set for
19.2 or 38.4 kilobaud when eight channels are multiplexed. If
data rates higher than 9600 baud are desired, the individual
data channels must be serviced more often by the UDLT.
Because the high-speed synchronous channel between
UDLTs is 64 kbps, the total bandwidth required by all of the
channels must be at or below 64 kbps. The multiplexer may
also be converted into a single channel limited-distance
modem where data rates of up to 56 kbps can be attained.

MC14163B

Motorola Telecommunications Device Data Book DL136, 1984.

..

, ~'

L~

MC14099B

~~

ClK --C CE

- .-

SIGNAL OUT
TO
RS·232
ORIVER
t- CHI
f.- CH2
t- CH3
t- CH4
f.- CH5
-CH6
t- CH7
f.- CHO

MC14022B

RST

..- A

~ f- B

C
WO

112MC14013B

0

a

y

XO
Xl
X2
X3
X4
X5
X6
X7

OlE ENABLES TO OSls

-

~ ____O!

-

>C

.- I>C

RST 02 01 00

+5 V

S02

MC14015B

PE
TE

TEl

REI

References

-0

00
01
02

00
01
02
03

CHANNEL 1
CHANNEL 2
CHANNEL 3
~r CHANNEL 4
- t- CHANNEL 5
- t- CHANNEL 6
- - CHANNEL 7
- - CHANNEL 0

Q

CONNECTIONS TO
SLAVE UOLT

112MC14013B

SOl

0

a
Q

MC14051B
L-

L--

L--

SI2

A
B
C

y

MC14015B
0OE ENABLES TO OSls
SIGNAL IN
FROM
RS·232
03 I CHANNEL 2
-0
02 j---Jf- CHANNEL 1
RECEIVER
01 l -t- CHANNEL 0
t- CH4
00 l-f- CHANNEL 7
I- CH5 r - - I> C
I- CH6
03 ~ CHANNEL 6
-0
CHANNEL 5
f.- CH7
02 CHANNEL 4
t- CHO
01 - I>C
CHANNEL 3
I- CHI
00 I- CH2
I- CH3

-

XO
Xl
X2
X3
X4
X5
X6
X7

------

Figure S. Slave Sequencing and Signalling

AN948

4-180

MOTOROLA COMMUNICATIONS DEVICE DATA

Tx & Rx

X

CH7

X

CHO

X

CHI

X

CH2

X

CH3

X

CH4

X

CH5

X

CH6

X

CH7

X

CHO DOE, DIE
CHI DOE, OlE

••

•

CH7 ODE, OlE

S12~

CH7

X

CHO

X

CHI

X

CH2

X

CH3

X

CH4

X

X

CH2

X

CH3

X

X

CH5

CH6

X

CH7

'C

X

CH6

C

SII
MS1. TEl. REI
TRANSMISSION LINE
SLAVE TEl
SLAVE REI
SLAVE SOl

SLAVE Tx & S02

~

CH6

X

SLAVE Rx & SI2

X
CHI

CH7

X

X
CH2

X

CHO

X

CH3

CHI

X

CH4

X

CH5

X

CH6

X

CH4

X

CH7

CH5

X

CHO

X

CHI

CH7 ODE
CH2 OlE

CH600E

••
•

~

CHI OlE

0

BURST FROM MASTER

0

BURST FROM SLAVE

Figure 9, System Timing

MOTOROLA COMMUNICATIONS DEVICE DATA

AN948
4-181

MAINS
TRANSFORMER
RECTIFIER/
FILTER

SWITCHING
POWER
SUPPLY

RECTIFIER/
REGULATOR

T1

RS·232
CONNECTIONS

SLAVE
MUlTIPLEXER
CIRCUITRY

MASTER
MUlTIPLEXER
CIRCUITRY

RS·232
CONNECTIONS

TWISTED PAIR
WIRE

Figure 10. Powering Slave Unit From the Twisted Pair

AN948
4-182

MOTOROLA COMMUNICATIONS DEVICE DATA

MOTOROLA

-

SEMICONDUCTOR
TECHNICAL DATA

EB111

'-i""';-;~'

Vince Deems

:-1' Telecommunication Applications

. ~ L
i I'

Austin, Texas

THE APPLICATION OF A DUPLEXER

The purpose of this document is to explain the application
and operation of a duplexer circuit, to show how to balance a
duplexer, and to discuss the duplexer's operation analysis
when used with two different transformers and with variable
components.
The duplexer circuit shown in Figure I is a fundamental
circuit that is used to help reject the transmit energy from the
receive signal. The circuit in Figure I is set up for a standard
600 ohm system.
This circuit eliminates the transmit signal from the receiving point by sending a combination of both signals into the
inputs of a differential amplifier. This tends to cancel out the
transmit signal leaving only the receive signal. A signal is
transmitted into Pin 3, the noninverting input, while a signal
is being received across Pins 5 and 8 of the transformer, from
the same line. There is a 600 ohm impedance when looking
into Pins 1 and 4 of the transformer. With RI tweaked to approximately 600 ohms, a voltage divider network is established with the 600 ohm impedance of the transformer. Thus,
the signal at the noninverting input, Pin 5, is Rx + (Tx/2).
The signal at the inverting input, Pin 6, is Tx/2 due to the
virtual ground concept. When these inputs are added
together, the transmit signal cancels leaving Rx, the receive
signal, at the output Pin 7.
There are- several ways of balancing or tuning duplexers
but only one technique will be explained for this application.
The transmit Pin 3 is grounded while a 600 ohm signal source
with a predetermined level and frequency is connected to
Pins 5 and 8 of the transformer. A signal with a level of
- 10 dBm (0.6938 Vp-p) and a frequency of 1700 Hz was
used in this circuit. RI is then tweaked such that the voltage
across Pins 5 and 8 of the transformer is half the signal
voltage or until there is exactly a 6 dB loss across Pins 5 and
8, (i.e., - 16 dBm at Pins 5 and 8). Next, the 600 ohm signal
source set at the same level and frequency is connected to Tx
(Pin 3) across a 10 kilohm resistor. A 600 ohm resistor is connected to Pins 5 and 8 of the transformer. Then, R2 is
tweaked until there is a minimum signal at Rx. Next, several
different values of capacitance are tried for Cl until the

MOTOROLA COMMUNICATIONS DEVICE DATA

smallest null is found at Rx. Once the best value of
capacitance has been found, the duplexer has been balanced
for that particular input signal and the best possible rejection
of the transmission signal to the receive signal has been
found. This is called the Transhybrid Rejection and is shown
with different values of capacitance in Figure 2.
There are several noisy signals that this duplexer can not
eliminate at the receive Pin 7. For instance, deflection of the
transmit signal off of the transformer returns out of phase
and tends to leak through onto the receive signal. For this
particular circuit, curve I shows the best rejection over the
spectrum.
It is worth noting the difference in performance of this
duplexer with respect to the type of transformer used. The rejection versus frequency plot shown in Figure 2 was the result
obtained when the Midcom 671-0018 was incorporated. This
transformer has winding resistances of 14 ohms on the
primary coil and 18 ohms on the secondary. The same test
was run with a different transformer (Midcom 671-09(5) and
the results are shown in Figure 3. This transformer has winding resistances of 178 ohms on the primary coil and 67 ohms
on the secondary coil giving it a much larger insertion loss
than the Midcom 671-0018. This difference is displayed in
Figure 3 as there is not as much rejection with the Midcom
671-0915 over the spectrum as with the Midcom 671-0018
(Figure 2).
It can be seen from Figures 2 and 3 that changing the
capacitance changes the amount of rejection. This is due to
the fact that the coil (Pins I and 4) not only has a resistance
but also has an inductive reactance. If there is not a proper
sized capacitance in parallel with this inductance, then the
overall impedance of the coil increases. This impedance
changes the voltage divider with RI which in turn allows a
larger Tx at Pin 5 which is slightly out of phase with the
Rx + Tx/2 at Pin 6. This allows more leakage of the transmission onto the receive signal thus decreasing the rejection.
This difference between the size of the capacitance and the
type of transformer to use is a tradeoff which is left to the
designer's judgement.

EB111
4-183

VDD
Tx _ _+-_ _..:3~
Tl

10 k

5

>-----+--..J\IY~ ~:

2

600

= - 1 01700
§B
Hz m
,...,

'----+------0

VSS
4

8

VDD= +5V
VSS= -5 V
VAG=GND (Analogi
Signal = - 10 dBm
11700 Hz)
Ul - MC143403
Tl - Midcom 671-0018

FIGURE 1 - Duplexer Circuit

o

Or--.-.-,~srTTTnr-'-'-~~~7rrn

-6
_ -12

-6
_ - 12 1--+-+-+--t-+-t-NrH-~-!:,£-I
/---,A-+~-t-;::.C.;:=~OH
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I

r--H--r-T~i'~mtr-~~/:±z1~l/rTptflJJfIl

~

m

::! -18 ~
c:

.g -24

-

Curve -(=0

I"' ~ ~

t7'L.--

'~-30

a:
:2 -36
 buffers
the signal and band-limits the input to -2.9 kHz. U 6,
an MC3417 linear CVSD modulator/demodulator,
encodes the CVSD word and creates a bit stream at
-12k bps. This serial bit stream loads into U" where
the ",p reads it in parallel.
For decoding and outputting speech, the iJ.P loads
the MC14014 8-bit shift register (U,) with parallel
data. U, shifts the data to Us for CVSD decoding. Us
performs low-pass filtering and buffers the resultant
voice waveform.
CMOS ICs U to U, and Us clock the filter and CVSD
chips, and U 7 drives a loudspeaker. Four control
lines connect with the iJ.P to control data direction
and synchronize data clocking.
EDN

90kHz
O.ODSp.F

NOTES:
ENCODE MODE: DATA CAN BE
READ FROM SHIFT REGISTER
AFTER NEGATIVE CLOCK EDGE,
ONLY STABLE FOR JOIISEC
DECODE MODE: DATA SHOULD BE
LOADED INTO PIA AFTER POSITIVE
CLOCK EDGE AND BE STABLE

BEFORE NEGATIVE CLOCK EDGE
U,=MC14069
U2 =MC14040
U3 =MC14538
U4 =MC14034
Us =MC3417
U.=MC145414
RESISTORS = 'I~W.5%

12V'o--------+---+.--t-\---+--H---------,
CLOCKlSVNC

3.3k

5Vo--~-,

ALL
3.3k

PB,o-_......:;=t
PB,
PB,
PB,o-_""""",
PB.o-_,.......'"
PB.o-_,........!j
PB,
PB, 0-_1'-1"1
GNO'o--~::t:j:::::::::~-_

O"~
_JL-_1___l_1_l~-_L_-_l_J

This 8-blt speech circuit encodes and decodes analog waveforms. Adjust the data-c/ock rate to trade off between voice quality
and memory overhead.

"Reprinted from EDN. May 26. 1982. Copyright 1982; Cahners Publishing Company"

MOTOROLA COMMUNICATIONS DEVICE DATA

ARTICLES
4-189

MOTOROLA

-

SEMICONDUCTOR
APPLICATION NOTE

AN1510

A Mode Indicator for the
MC34118 Speakerphone Circuit
Prepared by: Dennis Morgan
Introduction
In most applications involving a normal conversation, the
operating mode (receive, transmit, idle) of the MC34118
speakerphone IC is obvious to the users of the
speakerphone. There are some applications, however,
where it is beneficial to have an indication of the operating
mode. This indication may have to be visual, or logic levels to
a microprocessor or other circuitry. This application note
describes how to create a mode indicator for use with the
MC34118 speakerphone circuit.
Concept
Within the MC34118 are two comparators driven by the
level detectors which are sensing the speech signals (see
MC34118/D Data Sheet, Figure 24). The comparators'
outputs drive the attenuator control block which sets the
operating mode. The circuit described below parallels the
internal comparators with external ones.
Circuit
Figure 1 shows the additional circuitry. The two
comparators parallel the two which are inside the IC, located
at the outputs of the level detectors. Output A will be high
when the level detectors on the left side sense a transmit
condition, and low when they sense a receive condition.
Output B has the opposite polarity.
Figure 1. Mode Indicator Circuit

Vee
4

Vee
TL01 24
RL01
25

TL02
RL02

A
1.5M

Vee

MC34118
1.5M

The two 1.5 Mn resistors create a slight offset by draining
a trickle current out of Pins 19 and 24 in order to well define
the idle state. This is necessary due to the fact that when in an
idle state (no signal on either side) TL02 and RL02 will be
very similar in voltage (within a few millivolts of each other).
The same is true of TL01 and RL01. This, coupled with the
normal offset which exists at the cornparator inputs, would
make it difficult to predict the state of the A and B outputs
during idle.
Table 1 defines the comparator outputs. The fast idle
rnode is uncommon, occurring rarely. Only the slow idle
mode is of concern here.
Table 1
Output
Mode

A

B

Transmit

High

Low

Receive

Low

High

Slow Idle

High

High

Fast Idle

Low

Low

Circuit Variations
The outputs (A and B) in Figure 1 can be connected to
additional circuitry in a variety of ways. Figures 2 to 4 provide
a few suggestions. In Figure 2, the A and B outputs are simply
directed to a microprocessorior decoding. In Figure 3, LED A
will be ON in the receive mode, and LED B will be ON in the
transmit mode. In Figure 4, the outputs are decoded to
provide an idle/non-idle indication, and a Transmit/Receive
indication. Another alternative is to drive LEOs frorn the
decoded outputs of this circuit.
The value of the pull-up resistors at the comparator
outputs depends on the circuit which follows the
comparators. When driving CMOS logic, for example, 43 kn
resistors are adequate.

28

AN1510
4-190

MOTOROLA COMMUNICATIONS DEVICE DATA

When driving LEOs, they must generally be under
1.0 kO, depending on the specific LEOs which must be
illuminated. If the circuit is phone-line powered, the pull-up
resistors must be as high a value as possible to minimize
the drain on the loop current.
The LM393 comparator was chosen due to its low input
bias current, as well as its low supply current and input offset.

The low bias current Is very necessary so as to not upset the
level detector outputs any more than absolutely necessary.
The resistors at the level detector inputs (Pins 17, 20, 23, 26)
will generally have to be readjusted slightly after adding the
Figure 1 circuit to compensate for the slight offset which has
been added to the system. In most cases, it will be necessary
only to slightly increase the resistor at TL12 (Pin 17).

Figure 3

Figure 2

VC:Jl_

VCC_T*:-..
YU--'

A

-v-tr

VCCTI

To
Microprocessor

~
Figure 4

--.J:: Non-Idle
Idle

MOTOROLA COMMUNICATIONS DEVICE DATA

AN1510
4-191

4-192

MOTOROLA COMMUNICATIONS DEVICE DATA

Phase-Locked Loop

..

Application Notes and Technical Articles

AN535
AN827
AN969
AN980
AN1207
AN254#1
AN254#2
AN254#3
AN254-4

Phase-Locked Loop Design Fundamentals _.•••.••..•........••.••....•••••••.....•........
The Technique of Direct Programming by Using a Two-Modulus Prescaler •.....••......•.......
Operation of the MC145159 PLL Frequency Synthesizer with Analog Phase Detector ..•.•••.•..•
VHF Narrowband FM Receiver Using the MC3362 and MC3363 Dual
Conversion Receivers (MC145152) •..•••.......................•.........•••..........
MC145170 in Basic HF and VHF Oscillators .•...•.......•....••.•.••••.•.•....•..•••.••••••
Analyze, Don't Estimate, Phase-Lock Loop .••••..••.•••...•••............••.....•.•........
Optimize Phase-Lock Loops To Meet Your Needs ...
Suppress Phase-Lock Loop Sidebands Without Introducing Instability ...............•..•......•
Programmable Calculator Computes PLL Noise, Stability ...................•.•......••......•

MOTOROLA COMMUNICATIONS DEVICE DATA

4-195
4-206
4-211
4-222
4-236
4-242
4-245
4-249
4-252

4-193

..

4-194

MOTOROLA COMMUNICATIONS DEVICE DATA

MOTOROLA

-

SEMICONDUCTOR
APPLICATION NOTE

AN-535
Application Note

PHASE-LOCKED LOOP DESIGN FUNDAMENTALS

INTRODUCTION

The purpose of this application note is to provide the
electronic system designer with the necessary tools to
design and evaluate Phase Locked Loops (PLL) configured
with integrated circuits. The majority of all PLL design
problems can be approached using the Laplace transform
technique. Therefore, a brief review of Laplace is included
to establish a common reference with the reader. Since
the scope of this article is practical in nature all theoretical
derivations have been omitted hoping to simplify and
clarify the content. A bibliography is included for those
who desire to pursue the theoretical aspect.

OJ(S)

6j(s)

Phase input

0e(5)

Phase error

8 0 (5) Output phase

PARAMETER DEFINITION

G(s)

Product of the individual feed
forward transfer functions

H{s)

Product of the individual feedback transfer functions

FIGURE 1 - Feedback System

The Laplace Transform permits the representation of
the time response f(t) of a system in the complex domain
F(s). This response is twofold in nature in that it contains
both the transient and steady state solutions. Thus, all
operating conditions are considered and evaluated. The
Laplace transform is valid only for positive real time linear
parameters; thus, its use must be justified for the PLL which
includes both linear and nonlinear functions. This justification is presented in Chapter Three of Phase Lock
Techniques by Gardner.l
The parameters in Figure 1 are defined and will be used
throughout the text.

Using servo theory, the following relationships can be
obtained.2
1
(I)
(}e(s) ; 1 + G(s) H(s) (}i(S)
G(s)
{} (s) _
o - 1 + G(s) H(s) (}i(S)

(2)

These parameters relate to the functions of a PLL as
shown in Figure 2.

fj

FIGURE 2 - Phase Locked Loop

MOTOROLA COMMUNICATIONS DEVICE DATA

AN535
4-195

The phase detector produces a voltage proportional to
the phase difference between the signals /I i and /I o/N. TItis
voltage upon filtering is used as the control signal for the
VCO!VCM (VCM - Voltage Controlled Multivibrator).
Since the VCO!VCM produces a frequency proportional
to its input voltage, any time variant signal appearing on
the control signal will frequency modulate the VCO!VCM.
The output frequency is

(3)
during phase lock. The phase detector, filter, and VCO/
VCM compose the feed forward path with the feedback
path containing the programmable divider. Removal of
the programmable counter produces unity gain in the feedback path (N = 1). .As a result, the output frequency is
then equal to that of the input.
Various types and orders of loops can be constructed
depending upon the configuration of the overall loop
transfer function. Identification and examples of these
loops are contained in the following two sections.

Various inputs can be applied to a system. Typically
these include step position, velocity, and acceleration. The
response of type 1, 2, and 3 systems will be examined with
the various inputs.
/le{s) represents the phase error that exists in the phase
detector between the incoming reference signal /li{S) and
the feedback /lo{s)/N. In evaluating a system, /le{s) must
be examined in order to determine if the steady state and
transient characteristics are optimum and/or satisfactory.
The transient response is a function of loop stability and is
covered in the next section. The steady state evaluation
can be simplified with the use of the final value theorem
associated with Laplace. This theorem permits fmding the
steady state system error /le{s) resulting from the input
/li{S) without transforming back to the time domain}
Simply stated
Lim [/I{t)] = Lim [s/le{s)]
t-+oo

(10)

s-+o

Where

TYPE-ORDER
These two terms are used somewhat indiscriminately
in published literature, and to date there has not been an
established standard. However, the most common usage
will be identified and used in this article.
The type of a system refers to the number of poles of
the loop transfer function G{s) H{s) located at the origin.
Example:
10
G(s) H{s) = - s{s + 10)

let

ERROR CONSTANTS

(4)

This is a type one system since there is only one pole at
the origin.
The order of a system refers to the highest degree of
the polynomial expression

1
/le{s) = 1 + G{s) H{s) /li(S)

(II)

The input signal 9i{S) is characterized as follows:
Step position:

9i{t) = Cp t

~

0

C

(13)

Or, in Laplace notation: /li(S) =..l
s

where Cp is the magnitude of the phase step in radians.
This corresponds to shifting the phase of the incoming
reference signal by Cp radians:
Step velocity:

9i(t) = Cvt t

~

0

C

1 +G{s)H{s)=O~C.E.

(5)

which is termed the Characteristic Equation (C.E.). The
roots of the characteristic equation become the closed loop
poles of the overall transfer function.
Example:
10
G(s) H{s) = s{s + 10)

Or, in Laplace notation: /li(S)=~
s2

s3

(7)

(8)
(9)

which is a second order polynomial. Thus, for the given
G(s) H(s), we obtain a type 1 second order system.
AN535
4-196

/li(t) = Ca t 2 t ~ 0

2C a
Or, in Laplace notation: /li(S)=--

therefore
C.E. = s(s + 10) + 10

(IS)

where Cv is the magnitude of the rate of change of phase
in radians per second. This corresponds to inputing a frequency that is different than the feedback portion of the
VCO frequency. Thus, Cv is the frequency difference
in radians per second seen at the phase detector.
Step acceleration:

C.E.=s2+10s+10

(14)

(6)

then
10
I + G{s) H{s) = 1 + - - =0
s{s + 10)

(12)

(16)
(l7)

Ca is the magnitude of the frequency rate of change in
radians per second per second. This is characterized by a
time variant frequency input.
Typical loop G{s) H{s) transfer functions for types I,
2, and 3 are:

K
Type 1 G(s)H(s)=-{s s + a)

(18)

MOTOROLA COMMUNICATIONS DEVICE DATA

Type 2 G(s) H(s)

K(s + a)

=-s2-

K(s+a)(s+b)
Type 3 G(s) H(s) =----'-------'---'---"s3

(19)

(20)

The final value of the phase error for a type 1 system
with a step phase input is found by using Equations 11
and 13.
lIe(s) = (

~)
(s + a)Cp

Rule 1 - The root locus begins at the poles of G(s) H(s)
(K = 0) and ends at the zeroes of G(s) H(s)
(K =00). Where K is loop gain.
Rule 2 - The number of root loci branches is equal to
the number of poles or number of zeroes,
whichever is greater. The number of zeroes at
infinity is the difference between the number
of finite poles and finite zeroes of G(s) H(s).

1+-s(s + a)

(s2 + as + K)

istic equation) vary with loop gain. For stability all poles
must lie in the left half of the s-plane. The relationship of
the system poles and zeroes then determine the degree of
stability. The root locus contour can be determined by
using the following guidelines)

(21)

Rule 3 - The root locus contour is bounded by asymptotes whose angular position is given by
(2n + 1)
#P-#Z 1T; n=0,1,2, ...

(22)
Where
Thus the final value of the phase error is zero when a
step position (phase) is applied.
Similarly applying the three inputs into type 1, 2 and
3 systems and utilizing the final value theorem, the following table can be constructed showing the respective steady
state phase errors.

TABLE I - Steady State Phase Errors for Various System Types

(23)

uP (#Z) is the number of poles (zeroes).

Rule 4 - The intersection of the asymptotes is positioned
at the center of gravity C. G.
~P-~Z

C.G.=

uP-

#Z

(24)

Where :i;p (~Z) denotes the summation of the
poles (zeroes).
Rule 5 - On a given section of the real axis, root loci
may be found in the section only if the uP + #Z
to the right is odd.
Rule 6 - Breakaway points from negative real axis is
given by:
dK

-=0
ds

A zero phase error identifies phase coherence between
the two input signals at the phase detector.
A constant phase error identifies a phase differential
between the two input signals at the phase detector. The
magnitude of this differential phase error is proportional to
the loop gain and the magnitude of the input step.
A continually increasing phase error identifies a time
rate change of phase. This is an unlocked condition for
the phase loop.
Using Table I the system type can be determined for
specific inputs. For instanc~, if it is desired for a PLL to
track a reference frequency (step velocity) with zero phase
error, a minimum of type 2 is required.

Again where K is the loop gain variable factored from
the characteristic equation.
Example:
The root locus for a typical loop transfer function
is found as follows:

K
G(s) H(s) = - ( s s + 4)

MOTOROLA COMMUNICATIONS DEVICE DATA

(26)

The root locus has two branches (Rule 2) which begin
at s = 0 and s = -4 and ends at the two zeroes located at
infinity (Rule 1). The asymptotes can be found according
to Rule 3. Since there are two poles and no zeroes the
equation becomes:

STABILITY
The root locus technique of determining the position of
system poles and zeroes in the s-plane is often used to
graphically visualize the system stability. The graph or plot
illustrates how the closed loop poles (roots of the character-

(25)

2n + 1

--1T=

2

g

forn = 0
(27)

for n = 1

AN535
4-197

The position of the intersection according to the Rule
4 is:
~p

~Z

-

(-4 -0) - (0)

s = #P _ #Z

=

2- 0

s = -2

(28)

The response of this type 1, second order system to
a step input is shown in Figure 4. These curves represent
the phase response to a step position (phase) input for
various damping ratios. The output frequency response
as a function of time to a step velocity (frequency) input is
also characterized by the same set of figures.

The breakaway point as defined by Rule 6 can be found
by first writing the characteristic equation.
C.E. = I

+ G(s) R(s) = 0

K
= I +--=s2+4s+K=0
s(s + 4)

(29)
w

(f)

z

o0-

Now solving for K yields

(f)

W

K=-s2 -4s

(30)

Taking the derivative with respect to s and setting it
equal to zero then determines the breakaway point.

a:

I:::J
0-

I:::J

o
o

w

d
- (-s2-4s)
ds

dK
ds

N

(31)

:i

«

:>
a:

o
z

dK
- =-2s-4=0
ds

(32)

or
s =-2

(33)

is the point of departure. Using this information, the root
locus can be plotted as in Figure 3.
This second order characteristic equation given by
Equation 29 has been normalized to a standard form 2
(34)

FIGURE 4 - Type 1 Second Order Step Response

where the damping ratio I = Cos if! (0 0 ';; if! .;; 90 0 ) and Wn
is the natural frequency as shown in Figure 3.

jw

Asymptote

=

The overshoot and stability as a function of the damp·
ing ratio I is illustrated by the various plots. Each response
is plotted as a function of the normalized time wnt. For a
given I and a lock-up time t, the Wn required to achieve the
desired results can be determined. Example:

rr/2

Assume

Center of gravity

a
-4

K~O

Breakaway point

From I = 0.5 curve the error is less than 10% of final
value for all time greater than wnt = 4.5. The required
wn can then be found by:

3"
Asymptote

=

1=0.5
error < 10%
for t > 1 ms

wnt = 4.5

(35)

Wn = 4.5 = ....±2... = 4 5 k rad/s
t
0.001
.

(36)

"2

or
K-+oo

FIGURE 3 - Tvpe 1 Second Order Root Locus Contour

AN535
4-198

MOTOROLA COMMUNICATIONS DEVICE DATA

1

t is typically selected between 0.5 and 1 to yield optimum overshoot and noise performance.
Example:
Another common loop transfer function takes the form

.71--

(37)

This is a type 2 second order system. A zero is added
to provide stability. (Without the zero the poles would
move along the jw axis as a function of gain and the system
would at all times be oscillatory in nature.) The root locus
shown in Figure 5 has two branches beginning at the origin
with one asymptote located at 180 degrees. The center of
gravity is s = a; however, with only one asymptote there is
no intersection at this point. The root locus lies on a circle
centered at s = -a and continues on all portions of the negative real axis to left of the zero. The breakaway point
is s = -2a.

If ~ .... 0.
'r P\1 /' ;;;::

,
>
()

(s + a)k
G(s) H(s) = - s2

=.:;"o·j. .o.

z

1

:::l

1

w

oW
II:

U.

..

I:::l
I:::l

:::--- 10:

1.2

1
n

w

n

p:B.

I.~

0 ..

:;:

n

II:

o
Z

n

JIJIIII

n

:11111

/ \

1// r-,
:,.....- I - ~

.\

1,,-- ........2.~0

N

«

I

.L~l

I

:;

,,0. 1

//u.

~~

1.1

o
o

r- [)(\ V

./

,"-. =

/L
/

\

"1\ /1/

J

\.~i

\
\ L

.1

I!
I":

rff

n

W
0.1

o'i.
1.0 2.03.04.05.06.07.0 B.O 9.0 10 11

jw

12 13 14

s-plane

FIGURE 6 - Type 2 Second Order Step Response
u

K=O

to these design constraints is now illustrated. It is desired
for the system to have the following specifications:

FIGURE 5 - Type 2 Second Order Root Locus Contour

The respective phase or output frequency response of
this type 2 second order system to a step position (phase)
or velocity (frequency) input is shown in Figure 6. As
illustrated in the previous example the required wn can
be determined by the use of the graph when t and the lock
up time are given.
BANDWIDTH
The -3 dB bandwidth of the PLL is given by

w-3 dB =: Wn ( l-2t2 +.J2 -4 t 2 +4 t 4 )

~

(38)

~

(39)

for a type 1 second order4 system, and by

w-3 dB =Wn

(1

+2t 2 +.J2+4t2+4t4 )

for a type 2 second order I system.
PHASE-LOCKED LOOP DESIGN EXAMPLE
The design of a PLL typically involves determining the
type of loop required, selecting the proper bandwidth, and
establishing the desired stability. A fundamental approach
MOTOROLA COMMUNICATIONS DEVICE DATA

Output frequency
Frequency steps
Phase coherent frequency
output
Lock-up time between
channels
Overshoot

2.0 MHz to 3.0 MHz
100kHz

I ms

<20%

NOTE: These specifications characterize a system
function similar to a variable time base generator or a
frequency synthesizer.
From the given specifications the circuit parameters
shown in Figure 7 can now be determined.
The devices used to configure the PLL are:
Frequency-Phase Detector
MC4044/4344
Voltage Controlled
Multivibrator (VCM)

MC4024/4324

Programmable Counter

MC4016/4316

The forward and feedback transfer functions are given
by:
G(s) = Kp Kf Ko
where

Kil

=I/N

H(s) =--xn

(40)
(41)
AN535

4·199

FIGURE 7 - Phase Lacked Loop Circuit Parameters

The programmable counter divide ratio Kn can be found
from Equation 3.
fo min fo min
2 MHz
Nmin=--=-- = - - = 2 0
100 kHz
fi
fstep

(42)

3 MHz
fomax
Nmax = - - = - - = 30
100 kHz
fstep

(43)

I

Kn

=20

The transfer function of the VCM is given by
Kv
Ko=s

Where Kv is the sensitivity in radians per second per
volt. From the curve in Figure 8, Kv is found by taking the
reciprocal of the slope.

"I
to 30

Kv =

(44)

A type 2 system is required to produce a phase coherent
output relative to the input (see Table I). The root locus
contour is shown in Figure 5 and the system step response
is illustrated by Figure 6.
The operating range of the MC4024/4324 VCM must
cover 2 MHz to 3 MHz. Selecting the VCM control capacitor
according to the rules contained on the data sheet yields
C = 100 pF. The desired operating range is then centered
within the total range of the device. The input voltage
versus output frequency is shown in Figure 8.

(45)

4 MHz -1.5 MHz
5V-3.6V

21T rad/s/V

Kv = 11.2 X 106 rad/s/V

(46)

Thus

Ko =

11.2 X 106

rad/s/V

(47)

The s in the denominator converts the frequency characteristics of the VCM to phase, i.e., phase is the integral
of frequency.
The gain constant for the MC4044/4344 phase detector
is found by 5

Kp

DF High - UF Low
2 (21T)

2.3 V -0.9 V
41T
0.111 V/rad (48)

~oJ
o

"~

Since a type 2 system is required (phase coherent
output) the loop transfer function must take the form of
Equation 19. The parameters thus far determined include Kp, Ko, Kn leaving only Kf as the variable for
design. Writing the loop transfer function and relating
it to Equation 19

w

C!l

«

!:io

>

..z

I-

::>

c

;;

G(s) H(s) = Kp Kv Kn Kf = K(s + a)
s
s2

o

Thus Kf must take the form
1.0

2.0

3.0

4.0

5.0

f out • OUTPUT FREQUENCY (MHz)

FIGURE 8 - MC4324 Input Voltage versus Output
Frequency (100 pF Feedback Capacitor)

AN535
4-200

(49)

6.0

s+a
Kf=-

s

(50)

in order to provide all the necessary poles and zeroes for
MOTOROLA COMMUNICATIONS DEVICE DATA

the required G(s) H(s). The circuit shown in Figure 9 yields
the desired results.
Kf is expressed by

c

R2CS+ 1

Kf = ~ for large A

(51)

where A is voltage gain of the amplifier.
R1, R2, and C are then the variables used to establish
the overall loop characteristics.
The MC4044/4344 provides the active circuitry required
to configure the filter Kf. An additional low current high
(j buffering device or FET can be used to boost the input
impedance thus minimizing the leakage current from the
capacitor C between sample updates. As a result longer
sample periods are achievable.
Since the gain of the active fIlter circuitry in the
MC4044/4344 is not infinite, a gain correction factor Kc
must be applied to Kf in order to properly characterize the
function. Kc is found experimentally to be Kc = 0.5.
R2CS+ 1)
Kfc = Kf Kc = 0.5 ( - - RICS

FIGURE 9 - Active Filter Design

0.5 KpKvR2
R1N
=2~wn

and

(58)

With the use of an active fIlter whose open loop gain (A)
(Kc = 1), Equations 57 and 58 become

is large

(52)

(59)
( For large gain, Equation 51 applies. )
The PLL circuit diagram is shown in Figure 10 and its
Laplace representation in Figure 11.
The loop transfer function is
G(s) H(s) = Kp Kfc

Ko Kn

(53)

+ 1) (KV)
1)
R1 CS
-; ( N
G(s) H(s) = Kp(0.5) ( R2CS

(54)

(60)
The percent overshoot and settling time are now used
to determine Wn. From Figure 6 it is seen that a damping
ratio ~ = 0.8 will produce a peak overshoot less than 20%
and will settle to within 5% at wnt = 4.5. The required
lock-up time is 1 ms.

The characteristic equation takes the form
Rewriting Equation 57

C.E. = 1 + G(s) H(s) = 0
0.5 Kp Kv R2
0.5 Kp Kv
= s2 +
s + --::::--::::-:-R1N
R1CN

(55)
(0.5)(0.111)(11.2 X 106)

Relating Equation 55 to the standard form given by
Equation 34

(4500)2 (30)
RIC = 0.00102

0.5 Kp Kv R2
s2 +
R1N

S

+

0.5 Kp Kv

(Maximum overshoot occurs at Nmax which is minimum
loop gain)

R1CN

(56)
Equating like coefficients yields
0.5 Kp Kv _
2
R1 CN - Wn
MOTOROLA COMMUNICATIONS DEVICE DATA

(57)

Let

C =0.5/lF
0.00102

Then

R1 =

Use

R1 =2kU

0.5 X 10-6

= 2.04 kU

AN535

4-201

Vee

Vee

Ii

• Denotes parts external to the MC4344.

+

FIGURE 10 - Circuit Diagram of Type 2 Pha.. Locked Loop

FIGURE 11 - Laplaca Reprasentation of Diagram in Figure 10

AN535

4-202

MOTOROLA COMMUNICATIONS DEVICE DATA

Rl is typically selected greater than I kn.
Solving for R2 in Equation 58

(63)

2(0.8)

(0.5 X 10-6)(4.5 k)
=711

use R2

n

= 680 n

All circuit parameters have now been determined and
the PLL can be properly configured.
Since the loop gain is a function of the divide ratio
Kn, the closed loop poles will vary is position as Kn
varies. The root locus shown in Figure 12 illustrates the
closed loop pole variation.
The loop was designed for the programmable counter
N = 30. The system response for N = 20 exhibits a wider
bandwidth and larger damping factor, thus reducing both
lock·up time and percent overshoot (see Figure 14).

quency change as the programmable counter is stepped
from 21 to 20.
Since the output frequency is proportional to the VCM
control voltage, the PLLfrequency response can be observed
with an oscilloscope by monitoring pin 2 of the VCM. The
average frequency response as calculated by the Laplace
method is found experimentally by smoothing this voltage
at pin 2 with a simple RC filter whose time constant is
long compared to the phase detector sampling rate but
short compared to the PLL response time. With the
programmable counter set at 29 the quiescent control voltage at pin 2 is approximately 4.37 volts. Upon changing
the counter divide ratio to 30 the control voltage increases
to 4.43 volts as shown in Figure 14. A similar transient
occurs when stepping the programmable counter from 21
to 20. Figure 14 illustrates that the experimental results
obtained from the configured system follows the predicted
results shown in Figure 13. Linearity is maintained for
phase errors less than 211, i.e. there is no cycle slippage at
the phase detector.

N

1:

~

>z

u

w

:;)

N = 30
wn :::: 4.61 k rad/s

N
wn

\

= 20
=

5.64 k rad/s

r = 0.961

r = 0.785
-.. ,

,
I

a:

11.

I-

---- ,

I

ow

:;)
0-

I:;)

o

\

\

__ - - - - - - - ....."O-----""I~-\
-2.94 k
I
\

"'*----

I
TIME (ms)

///1

FIGURE 13 - Frequency·Time Response

FIGURE 12 - Root Locus Variation

NOTE: The type 2 second order loop was illustrated
as a design example because it provides excellent performance for both type 1 and 2 applications. Even in systems
that do not require phase coherency a type 2 loop still
offers an optimum design.
EXPERIMENTAL RESULTS
Figure 13 shows the theoretical transient frequency
response of the previously designed system. The curve
N =30 illustrates the frequency response when the programmable counter is stepped from 29 to 30 thus producing a
change in the output frequency from 2.9 MHz to 3.0 MHz.
An overshoot of 18% is obtained and the output frequency
is within 5 kHz of the final value one millisecond after the
applied step. The curve N = 20 illustrates the output freMOTOROLA COMMUNICATIONS DEVICE DATA

11111

4.43 V

4.37 V

3.89 V

3.83 V

V
H

= 0.05 V/cm
= 0.5 ms/cm

FIGURE 14 - VCM Control Voltage (Frequency) Transient

AN535
4-203

I. .....•........ 1. .............. I ............... 1. .............. 1............... 1. .............. 1

1 ............... 1 ............... 1 ............... 1. .............. 1. .............. 1 ............... 1
0.02

0.04

0.06

0.08

VCM CONTROL SIGNAL (VOLTS)

FIGURE 15 - VCM Control Signal Transient

AN535
4-204

MOTOROLA COMMUNICATIONS DEVICE DATA

Figure 15 is a theoretical plot of the VCM control voltage transient as calculated by a computer program. The
computer program is written with the parameters of Equations 58 and 59 (type 2) as the input variables and is valid
for all damping ratios of ~ .;;; 1.0. The program prints or
plots the control voltage transient versus time for desired
settings of the programmable counter. The lock-up time
can then be readily determined as the various parameters
are varied. (If stepping from a higher divide ratio to a lower
one the transient will be negative.) Figures 14 and 15 also
exhibit a close correlation between the experimental and
analytical results.

SUMMARY

This application note describes the basic control system
techniques required for phase-locked loop design. Criteria
for the selection of the optimum type of loop and methods
for establishing the desired performance characteristics are
presented. A design example is illustrated in a step-by-

MOTOROLA COMMUNICATIONS DEVICE DATA

step approach along with the comparison of the experimental and analytical results.

BIBLIOGRAPHY
1. Topic: Type Two System Analysis
Gardner, F. M., Phase Lock Techniques, Wiley, New
York, Second Edition, 1967
2. Topic: Root Locus Techniques
Kuo, B. C., Automatic Control Systems, Prentice-Hall,
Inc., New Jersey, 1962
3. Topic: Laplace Techniques
McCollum, P. and Brown, B., Laplace Transform Tables
and Theorems, Holt, New York, 1965
4. Topic: Type One System Analysis
Truxal, J .G., Automatic Feedback Control System Synthesis, McGraw-Hill, New York, 1955
5. Topic: Phase Detector Gain Constant
DeLaune, Jon, MTTL and MECL Avionics Digital Frequency Synthesizer, AN532

AN535
4-205

MOTOROLA

-

SEMICONDUCTOR
APPLICATION NOTE

AN·827

Application Note

THE TECHNIQUE OF DIRECT PROGRAMMING
BY USING A TWO·MODULUS PRESCALER
Prepared by
PLL Applications

INTRODUCTION

DESIGN CONSIDERATIONS

The MC12009, MC12011, or MC12013 can be used as
part of a variable modulus (divisor) prescaling subsystem
used in certain Digital Phase-Locked Loops (PLL).
More often than not, the feedback loop of any PLL contains a counter-divider. Many methods are available for
building a divider, but not all are simple, economical, or
convenient in a particular application.
The technique and system described here offer a new
approach tothe construction of a phase-locked loop divider.
In addition to using either the MC12009, MC12011, or
the MC12013 variable modulus prescaler, this system
requires an MC12014 Counter Control Logic Function,
together with suitable programmable counters (e.g.,
MC4016s or SN74LS716s). Data sheets for these additional devices should be consulted for their particular
functional descriptions.

The disadvantage of using a fixed modulus (+ P)forfrequencydivision in high-frequency phase-locked loops (PLL)
is that it requires dividing the desired reference frequency
by P also (desired reference frequency equals channel
spacing).
The MC12009/11/13 are especially designed for use
with a technique called "variable modulus prescaling".
This technique allows a simple MECL two-modulus
prescaler to be controlled by a relatively slow MTTL programmer counter. The use of this technique permits
direct high-frequency prescaling without any sacrifice in
resolution since it is no longer necessary to divide the
reference frequency by the modulus of the high-frequency
prescaler.

AN827
4-206

MOTOROLA COMMUNICATIONS DEVICE DATA

The theory of "variable modulus prescaling" may be
explained by considering the system shown in Figure 1.
For the loop shown:
fout

~

N. p. fref

to multiply by a fractional number, equation 4 must be
synthesized by some other means.
Taking equation 3 and adding ±AP to the coefficient
of fref, the equation becomes:

(1)

fout
FIGURE 1 - FREQUENCY SYNTHESIS BY PRESCALING

~

(Np • P + A + A. P - A. P) fref.

Collecting terms and factoring gives:
f out ~ [(Np - A) P +A (P + 1)] fref

R e f e , e n case
e @ -Fh(5)B - -

Frequency ___

(f,ef)

(5)

(6)

veo

Oet.

From equation 6 it becomes apparent that the fractional part of N can be synthesized by using a two-modulus counter (P and P + 1) and dividing by the upper modulus, A times, and the lower modulus (Np - A) times.
This equation (6) suggests the circuit configuration in
Figure 3. The A counter shown must be the type that
where P is fixed and N is variable. For a change of 1 in N,
the output frequency changes by P • fref. If fref equals
the desired channel spacing, then only every P channel
may be programmed using this method. A problem remains: how to program intermediate channels.
One solution to this problem is shown in Figure 2.

FIGURE 3 - FREQUENCY SYNTHESIS BY TWO
MODULUS PRESCALING

Reference
Frequency

(f,ef)
FIGURE 2 - FREQUENCY SYNTHESIS BY PRESCALING

N~Np.P+A

A -;- P is placed in series with the desired channel spacing
(frequency) to give a new reference frequency: channel
spacing/Po
Another solution is found by considering the defining
equation (1) for fout of Figure 1. From the equation it
may be seen that only every P channel can be programmed
simply, because N is always an integer. To obtain intermediate channels, P must be multiplied by an integer plus
a fraction. This fraction would be of the form: AlP. If
N is defined to be an integer number, Np, plus a fraction,
A/P, N may be expressed as:
N ~ Np + A/P.
Substituting this expression for N in equation 1 gives:

or:

fout ~ (Np + A/P) • P • fref

(2)

fout ~ (Np P + A) • fref

(3)

fout

~

Np • p. fref + A • fref.

counts from the programmed state (A) to the enable state,
and remains in th is state until divide by Np is completed
in the programmable counter.
In operation, the prescaler divides by P + 1, A times.
For every P + 1 pulse into the prescaler, both the A counter and Np counter are decremented by 1. The prescaler
divides by P + 1 until the A counter reaches the zero state.
At the end of (P + 1) • A pulses, the state of the Np
counter aquals (Np - A). The modulus of the prescaler
then changes to P. The variable modulus counter divides
by P until the remaining count, (Np - A) in the Np counter,
is decremented to zero. Finally, when this is completed,
the A and Np counters are reset and the cycle repeats.
To further understand this prescaling technique, consider the case with P ~ 10. Equation 6 becomes:
fout

~

(A + 10 Np) • fref

(7)

If Np consists of 2 decades of counters then:
(4)

Np ~ 10 NPl + NPO
Equation 4 shows that all channels can be obtained directly
if N can take on fractional values. Since it is difficult
MOTOROLA COMMUNICATIONS DEVICE DATA

(Npl is the most significant digit).
and equation 7 becomes:

AN827
4-207

FIGURE 4 - DIRECT PROGRAMMING UTILIZING
TWO-MODULUS PRESCALER

ZO
ZI

Eo

Z2

-E

,-

MC12013
MTTL out

Z3

®

-®

fin

MC12014

PO

Cl

PI

f out

P2

@
----fR, then FSO pulses low. The FSO pulse
width is approximately equal to the period of time between
two fV pulses if tv>fR, or two fR pulses if fR>tv. FSOs
repetition rate is equal to the difference frequency between
fR and fV. When tv = fR over a 211' window with respect to
fR, then the FSO remains in a high-impedance state and phase
lock is maintained by the analog phase detector output. (See
Figure 6.1 By combining APDout and FSO, the required lownoise VCO control voltage is provided by APDo·ut while the
FSO provides a coarse error signal to achieve fast frequency
lock.
The ramp clamp approach to phase detector design, which
is implemented on the MC145159, offers significant advantages over the traditional method of sample-and-hold phase
comparators. In traditional sample-and-hold detectors, ramp
slewing during the sample window causes rippling on the hold
capacitor. Therefore, a second hold capacitor and sampling
switch may be needed. The ramp clamp technique however,
alleviates the need for a second hold capacitor and all of its
related circuitry. This becomes very significant in the production of monolithic integrated circuits due to the savings in chip
area that result.
Another benefit of ramp clamping is that the ramp amplitude
is not allowed to go beyond the value reached when sampling
occurs. The traditional method permits the ramp capacitor to
charge all the way up to the positive supply voltage value; in
most cases well after sampling has occurred. This extends the
ramp amplitude beyond that allowed with the ramp clamp
approach. A lower ramp pulse results in less ripple in the output
error signal caused by parasitic ramp feed-through. With ramp
clamping, the ramp amplitude is limited to only that value
necessary to keep the loop locked and, more importantly, it
provides a constant voltage to the hold capacitor during the
entire sample window.

THEORY
The MC145159 uses a new, patented design approach for
sample-and-hold phase deteCtors called ramp clamping, which
results in improved performance over the traditional approach.
Ramp clamping minimizes the need for a second hold capacitor, and in most applications only one hold capacitor is needed.
When the loop is in frequency lock, the rising edge of fR
(divided-down OSCin signal) activates a constant current
source to initiate charging of the ramp capacitor. (See Figures
4 and 5. I The slope of this ramp waveform is also known as
the phase detector gain. The ramp voltage continues to build,
at a rate determined by RR, CR, and VDD' , until the rising
edge of tv (divided-down VCO signal) terminates the charge
signal, thereby establishing a constant voltage on CR. After
a predetermined delay (equal to two clock cycles of finl this
ramp voltage is sampled onto the hold capacitor during a
sample window lasting four periods of fin. CH is then isolated
from CR and, after a delay of two clock cycles of fin, CR is
discharged. This cycle repeats every fR period. The tv edge
relative to the fR edge in time therefore determines how long
the ramp charges before being clamped and sampled onto CH.
This establishes the hold voltage necessary to maintain loop
lock. The voltage on CH feeds an N-channel source follower,
the output of which (APDoutl controls an external VCO.
When the loop is out of frequency lock, that is when fR
and tv are not in a one-to-one relationship over a 211' window
with respect to fR, the Frequency Steering Output (FSOI becomes active. As a general rule, fR and tv must differ by 2%
for the FSO to become active. However, as the reference
frequency decreases, the frequency steering sensitivity increases. If the divided-down VCO frequency, tv, is lower than
the divided-down oscillator frequency, fR, (tvIRI

IL _ _--'

-l
FSO
(0.98 IR

~ 2. 0:--'"
I'...
g

.

fR
(INTERNAL)

(lNTERN:~

JlL-_______--Jn

L _ __

(b) fR=fV= 10 kHz

Figure 7. Determining the Gain
of the Analog Phase Detector

MOTOROLA COMMUNICATIONS DEVICE DATA

~ 1. 0

~

~

"'" ....

i"""--.

r-Voo' - 5 V

I

10

r-..

I'

I
20

30

50

70

100

200 300

500 700 1000

RO • .oUTPUT RESISTANCE Ik[J)

Figure 9. APDout Bias Current
versus Output Resistance

AN969

4-215

METHOO OF PROGRAMMING THE COUNTERS

Action

The MC145159 contains three fully-programmable counters.
The R, N, and A counters are programmed by a serial data
bit stream. (See Figure 10.) Perusing the logic diagram of the
device gives insight as to how the counters are loaded with
data. (See Figure 1.)
First, the desired values for R, N, and A must be converted
to binary form with the proper amount of bit positions. Note
that the R counter is 14 bits long, the N counter 10 bits long,
and the A counter 7 bits long. To load the data the Enable
pin must be taken low to isolate the counters fr~m changes
that occur in the shift registers. With Enable low, data is then
loaded into the shift registers on the rising edge of the clock
input. Care must be taken to ensure that Olita, Clock, and
Enable voltage levels and rise, fall, setup, hold, and recovery
times are not violated. The divide-by-R word is loaded first
with its most-significant bit as the first bit entered. The divideby-N word follows immediately, again with its most-significant
bit as the first bit entered. Next is word A, similarly with its
most-significant bit entering first. The last bit of the string is
the control bit. A logic one for the control bit allows all the
counters to be loaded with shift register information when
Enable is taken high. A logic zero entered as the control bit
inhibits a reference counter latch load. Therefore, only the N
and A counters are loaded when Enable is taken high.
Finally, after all the data is properly loaded into the shift
registers and the control bit is at the desired logic state, Enable
is taken high to program the counters. After satisfying the
minimum input pulse width for Enable, that pin must then be
taken low to isolate the counters from outside disturbances.
For example, suppose system requirements dictate that the
R, N, and A counters be programmed with 40, 200, and 72,
respectively. The steps to load the counters are outlined below.
R=40 (14 bits)
0 0
MSB

0

0

0

0

0

0

0

0

0

0

A=72 (7 bits)
0

0

MSB

0

0
LSB

Isolate the counters

1. Take Enable low
«0.3 VOO)
2. Shift in eight Os
3. Shift in one 1
4. Shift in one 0
5. Shift in one 1
6. Shift in five Os

Start loading R word

R word entered; start
loading N word

Shift in two 1s
Shift in two Os
Shift in one 1
Shift in three Os
Shift in one 1
Shift in two Os
Shift in one 1
Shift in three Os
Sh.ift in one 1
Take Enable high
(>0.7 VOO)
17. Take Enable low
«0.3 VOO)

7.
8.
9.
10.
11.
12.
13.
14.
15.
16.

N word entered
Start loading A word

A word entered
Control bit high
Load the three counters
Isolate the counters

Now that the counters are loaded with the correct information and the system is working properly, changing the output frequency is desired. New values of N and A are chosen
while keeping R the same. (R is only used in this case to set
up the system resolution.) The same method can be used to
program the N and A counters while simply ignoring the R
counter. Take Enable low, shift in the appropriate binary data
for N and A, shift in a control bit of logic zero to isolate the
R counter form the Enable line, and pulse high the Enable
input.
For example, suppose the new values for N and A are 178
and 13, respectively. The steps to load the counters are outlined below.

N = 178 (10 bits)

N =200 (10 bits)
0 0
MSB

0

Comment

0

0
LSB

o

o

0

o

MSB

0

o
LSB

A = 13 (7 bits)
0

0

0
LSB

o

0

0

MSB

o

1
LSB

LATCHED WHEN CONTROL BIT = 1
SHIFT
REGISTER
OUT

DATA IN

Figure 10. Data Entry Format

AN969
4-216

MOTOROLA COMMUNICATIONS DEVICE DATA

Action
1.
2.
3.
4.

5.
6.
7.
8.

tiA=~50CI

Take Enable low
Shift in two Os
Shift in one 1
Shift in one 0
Shift in two Is
Shift in two Os
Shift in one 1
Shift in four Os

Shift in one 0
Shift in one 1
Shift in one 0
Take Enable high
Take Enable low

I

8

N word entered; start
loading A word

I
I

I
I

1 kllsRRSl Mil
500 pFsCR sO.l1'F
10 CH s CR
10 kll s RO s 1 Mil

MOTOROLA COMMUNICATIONS DEVICE DATA

./

_ .... f"'"

GUARANTEED

....-

I:'

-

RECDMMENDED DPERATING REGION
I
I . 1 I" 1 -

_-t.- -

J

MAX

4

A word entered
Control bit low
Load the two counters
Isolate the counters

Although not stated on the data sheet, the fin and OSCin
limits for the MCl45159 are about the same as the rest of the
silicon-gate MCl451XX family of frequency synthesizers. (See
Figures 11 and 12.) One limit is 15 MHz for a supply voltage
of 5 V and a divide value of six or greater for the Nand R
counters. Refer to the graphs for frequency limits of the
MCl45159 counters at other supply voltages.
The analog phase detector component values playa small
role in determining the input frequency limits at the input to
the phase detector. For high reference frequencies, a large
value of Icharge is most likely required. Make certain that
component values are in specified ranges. For best results,
the following limits are recommended. (Low-leakage polystyrene or Mylar capacitors are recommended for CR and CH.)

f"'"

/

... " ./'"
L...::.J::-fo'"

L

fin, OSCin LIMITS

I

'" /

-T~PICA~*

As is evident, the two prior routines are serial in nature. A
microprocessor is therefore best suited to program the
counters. Also, note that the counter outputs are not available
on the MCl45159 for checking correct counter operation.
However, a shift register output, SRout, is available. (See
Figure 1.) Therefore, the same microprocessor that programs
the counters can also be used to verify the contents of the
shift registers to ensure that the correct data has been loaded.
Enable must be held low while verifying shift register contents
to avoid affecting the counters.
Although the MCl45159 has on-chip logic for control of an
external dual modulus prescaler, the device is capable of performing in a single modulus mode simply by leaving the modulus control output unconnected. In this case, the 10-bit divideby-N counter performs the loop divide-by-N function. The A
counter must still be loaded with data, but that data is a don't
care. However, loading the A counter with all Os is strongly
recommended. In that way, the modulus control output is
stuck high and cannot cause any possible interference by
switching periodically.

I

J
2

9. Shift in two Is
10.
11.
12.
13.
14.

I

SQUARE WAVE. VDD - VSS
TSINE WAVE, 5DO mVp.p y

Isolate the counters
Start loading N word

TOTAL DIVIDE VALUE
(a) VDD=3V

;l!

~
>-

...15
=>

ffi

fE

'"

:z

~

~

C>

::;;
=>
::;;

x

'"::;;

j

TA=25°C
28 r-_ SQUARE WAVE, VDD - VSS
26 r-_ - SINE WAVE. 500 mVp•p _
~
24
/
1
1
22
/
1 1
V
20
TYPICAL* / '
18
/
16
..:'.14
V
12
GUARANTEED
10
I-.::t:: -f-- RECOMMENDED DPERATING REGION

"

----

1

"

---"

1
MAX

4

TDTAL DIVIDE VALUE
(b) VDD=5 V

6 TYJICAL1*
........ ~
2

.... f-

--- -

TA=25°C
SQUARE WAVE. VDD - VSS '
- -SINE WAVE. 500 mVp.p

0
8

L J

GUARANTEED
2

r-l-

-f-'

I

-

I

i

-r
J J J J
'
RElOMM1ENDE1D OPfRAT1ING ~EGIOIN- J--

4

5

MAX

TOTAL DIVIDE VALUE
(e) VDD=9 V

*Data labelled "Typical" is not to be used for design purposes, but
is intended as an indication of the IC's potential performance.

Figure 11. OSCin and fin Maximum
Frequency versus TotBI Divide Value
(Rmln 3, Nmin 16)

=

=

AN969

4-217

1.1 2

~
~ _

1.09 3 V 1.0 6 5V

53 3
ff::iS

- ---

9V

-

--'.

~

1'-0..
~

~

"r-.. ,

1

0.79

1.063 3 V
1.05 6
1.049
1.042
1.0355 V•
9V
1.028
1.02 1
1.014
1.007
1.000
0.993

R COUNTER ONLY

~

5V
3V
r>..9V

40

-20

20

40

60

80

.•
•.
1',
\

Rmin=3
Nmin=16

,

K.

-40

'"

r-..... ".

3V
5V
9V

r=:: .....
20

-20

40

TEMPERATURE 1°C)

TEMPERATURE 1°C)

la) TOTAL DlVIOE VALUE = 3. 4. OR 5

Ib) TOTAL OIVIOE VALUE", 6

80

80

. Figure 12. OSCin and fin Maximum Frequency versus Temperature for Sine and Square Wave Inputs
DUAL-MODULUS PRESCALING CONSTRAINTS
The MC145159 contains all the necessary logic for control
of an external dual-modulus prescaler. Dual-modulus prescaling is a solution to some of the shortcomings associated
with single-modulus prescaling. Inherent in the design of
synthesizers using, single-modulus prescaling is the fact that
the value of the reference frequency into the phase detector
is multiplied by the prescale value P, as well as by the counter
value, N. (See Figure 13.) This results in a loss of system
resolution because any unitary change of N results in the
output frequency of the VCO changing by the reference frequency times P, which may be undesired.
Dual-modulus prescaling is a solution to this problem. It
allows VCO step sizes equal to the value of the phase detector
reference frequency to be obtained. This technique utilizes an
additional A counter and a special prescaler which divides by
anyone of two values, depending upon the state of its control
line. (See Figure 14.) In dual-modulus prescaling, the lower
speed counters are uniquely configured. Special control logic
is necessary to select the divide value, P or P + 1, in the prescaler for the required amount of time.
The modulus control signal is low at the beginning of a
count cycle, enabling the prescaler to divide by P + 1, until the
A counter has counted down to zero. At this time, modulus
control goes high, enabling the prescaler to divide by P, until

CRYSTAL
OSCILLATOR

1----+

+ R COUNTER

fref

PHASE
OETECTOR

"'ref

IK~1

1---+

the N counter counts down the rest of the way to zero; N
minus A additional counts.
Ntot= (P+1)A+P(N-A)
= NP+A
Modulus Control is then set back low, the counters preset to
their respective programmed values, and the sequence is
repeated.
This provides for a total programmable divide value of (N
times P) + A. To have a range of total divide values in sequence,
the A counter is programmed from zero through P - 1 for a
particular value N in the N counter. N is then incremented by
1 and the A counter is sequenced from zero to P -1 again.
Certain constraints apply when using dual-modulus prescaling: 1) N is greater than or equal to A always applies; 2)
the value of P must be large enough so that the maximum
frequency of the VCO divided by P must not exceed the frequency capability of the N and A counters; also, 3) P times
the period of the maximum VCO frequency must be greater
than the sum of the prop delay through the dual-modulus
prescaler plus the prescaler setup or release time relative to
its control signal plus the propagation delay of frequency in'
(fin) to Modulus Control.

Ve

f----+

LOW·PASS
FILTER
IKFI

Vc

1----+

VOLTAGE·
CONTROLLEO
OSCILLATOR
IKOI

fo

iiP
Ntot=NP

fo
+ N COUNTER
IKNI

I..P

+P
PRESCALER
IKpl

-

Figure 13. Single-Modulus Prescaling

AN969

4-218

MOTOROLA COMMUNICATIONS DEVICE DATA

CRYSTAL
OSCILLATOR

PHASE
DETECTOR
IK >R2

r

lal

Cl

r

C2

Ibl

APDout

----.l\AIV--...-'V'oIV--i If-----,

r

>----"""'_.-.. TO VCO

lei

r

Figure 16. Possible Methods for Combining Analog Phase Detector Output and Frequency Steering Output

CONCLUSION
This application note discussed the open-loop characteristics of the MC145159 PLL frequency synthesizer with analog
phase detector. The MC145159 uses an improved method over
the traditional sample-and-hold technique while providing an
alternative to digital phase detectors in frequency synthesis
applications. The Frequency Steering Output together with
the Analog Phase Detector Output combine to produce an
error signal without the introduction of excessive noise. In
fact, this phase detector scheme minimizes filtering requirements, reduces VCO modulation sidebands, and allows for
wider loop bandwidths than are normally possible with digital
phase detector outputs.
An additional application note is planned to cover the closedloop application of the MC145159, especially the methods for
combining the two phase detector outputs.

MOTOROLA COMMUNICATIONS DEVICE DATA

REFERENCES AND ACKNOWLEDGMENTS

1. CMOS/NMOS Special Functions Data, Motorola Inc.
2. Manassewitsch, Vadim, Frequency Synthesizers- Theory
and Design, Wiley and Sons, 1980, pp. 401-407.
3. Sample and Hold Phase Detectors/Comparators, Motorola
internal memo, signed by John Hatchett and Roy Jones,
10/3179.
4. Sample and Hold Phase Detector Timing, Motorola internal
memo, Andy Olesin and John Hatchett, 10/23/79.

AN969
4-221

MOTOROLA

-

SEMICONDUCTOR
APPLICATION NOTE

AN980

VHF Narrowband FM Receiver Design
Using the MC3362 and the MC3363
Dual Conversion Receivers
Prepared by: Bipolar Analog Applications

Motorola has developed a series of low power narrowband FM dual conversion receivers in monolithic silicon
integrated circuits. The MC3362 and the MC3363 are manufactured in Motorola's MOSAIC process technology.
This process develops NPN transistors with fT = 4 +
GHz, which allows the MC3362 and the MC3363 to have
excellent very high frequency (VHF) operation with low
power drain. They are ideal for application in cordless
phones, narrowband voice and data receivers, CB and
amateur band radios, radio frequency (RF) security
devices and other applications through 200 MHz.
Features of the MC3362/3 Receiver ICs:
• Broadband RF input frequency capability (to 200 MHz
using internal oscillator, over 450 MHz using external
oscillator)
• Single supply operation from VCC = 2 to 7 Vdc
• Low power consumption (Icc = 3 mA typical at VCC
= 2 Vdc)
• Internally biased NPN RF transistor amplifier (MC3363)
• Complete dual conversion circuitry - first mixer and
oscillator included
• First local oscillator (La) includes buffered output and
varactor diode to allow phase locked-loop (PLL) frequency synthesis for multichannel operation.
• Buffered second local oscillator output available for
PLL reference input (MC3362)
• Multistage limiter and quadrature detection circuitry
included
• RSSI (Received Signal Strength Indicator) with Carrier
Detect logic included
• BUilt-in data slicing comparator detects zero crossings
of FSK data transmission
• Inverting operational amplifier included for audio muting or active filtering (MC3363)

SCOPE
This application note contains functional descriptions
and applications information pertaining to the various
functional blocks of the MC3362/3 receiver circuits. Four
receiver application circuits are shown. A single channel
receiver and a 10 channel frequency synthesized receiver

designed for the 49 MHz cordless telephone band are
shown. A 256 channel "2 Meter" (144-148 MHz) amateur
band receiver is also shown, including an appropriate PLL
frequency synthesizer design to control the receiver's
local oscillator. Finally, a low cost application featuring
the MC3362 as a single chip manually tunable 162 MHz
weatherband receiver is shown. A directory of external
component manufacturers is included as an appendix.

COMPARISON OF THE MC3362 AND THE MC3363
Figures 1A and 1B show the system block diagrams of
MC3362 and MC3363, respectively. The MC3362 and the
MC3363 are made from the same die, but a final metal
mask difference allows different features to be made
available on each. Data pertaining to the common functional blocks are identical on both circuits.
The MC3363 is a complete VHF dual conversion FM
receiver including RF amplifier, two mixers and oscillators, limiting IF amplifier and quadrature detection circuitry, received signal strength indicator (RSS!) circuitry,
squelch circuitry and a data shaping comparator for
detecting FM frequency shift keyed (FSK) data transmissions. Receivers using the MC3363 alone can achieve
better than 0.3 /LV input sensitivity for 12 dB SINAD, from
a 50 n source. The MC3363 comes in a 28-lead plastic
wide SOIC package only.
The MC3362 is optimized for cordless telephone applications and as such does not contain the RF preamplifier
or squelch circuitry. In addition, the second local oscillator contains a buffered output so that it can serve as
the system frequency reference in applications where a
10.240 MHz or 10.245 MHz reference is needed. In general, the MC3362 can be substituted for the MC3363
where:
• A receiver with sensitivity of 0.7 /LV at the input for
12 dB SINAD is adequate.
• An external RF preamplifier with AGC is desired (such
as MOSFET's 3N211 and MPF211).
• Receiver squelch is not needed.
• Surface mount technology cannot be used. The
MC3362 is available in two 24-lead plastic packages
(DIP and wide SOIC surface mount).

MOSAIC is a trademark of Motorola, Inc.

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4-222

MOTOROLA COMMUNICATIONS DEVICE DATA

1ST MIXER

2ND MIXER

OSC
OUT

10.24 ~
T
MHZ~

PHASE
I
LOCKED- VCO INPUT
LOOP
SYSTEM SYSTEM FREQUENCY INPUT

CARRIER
DETECT

DEEMPHASIS

I

T

AUDIO

I-- OUTPUT

DATA
OUTPUT

FSK COMPARATOR

Figure 1A_MC3362 Internal Block Diagram

MOTOROLA COMMUNICATIONS DEVICE DATA

AN9ao
4-223

1ST MIXER

2ND MIXER

AMP

PHASE 1------'
LOCKED· VCO INPUT
I
LOOP
SYSTEM SYSTEM FREOUENCY INPUT

CARRIER
DETECT

MUTE

...-o--.. .-ll- AUDIO

OUTPUT

DEEMPHASIS

I
DATA
OUTPUT

LIMITER

I
FSK COMPARATOR

Figure 1B. MC3363 Internal Block Diagram

AN9aD
4-224

MOTOROLA COMMUNICATIONS DEVICE DATA

FEDERAL REGULATIONS.
RECOMMENDED STANDARDS
Radios built for certain VHF and UHF bands may qualify
under the FCC Code of Federal Regulations Title 47. Part
15, for use by unlicensed operators. It is important to
know the federal regulations concerning a particular frequency channel or band of channels before a receiver or
transmitter circuit is designed. Contact the FCC/Government Printing Office to order a copy of the Code of Federal Regulations, Title 47, Parts 0-20 which contains Part
15. before designing a radio receiver or transmitter for
unlicensed utility applications.
Professional (land mobile) radios come under another
part (Part 90) of the Title 47 code. There are a set of
standards, published by the Electronic Industries Association, which dictate recommended operating specifications for two way communication equipment. These
standards provide useful information about radio performance, terminology and measurement techniques
and are useful even if professional radios are not a
designer's primary goal. Contact the EIA at
(202) 457-4900 to order the standards listed below. The
FCC/GPO can be reached at (202) 275-2054 or
(213) 894-5841. The pertinent documents are:
Number
Description
Parts Referenced
Radio Frequency
FCC Title 47, Code of Federal
Regulations
Devices
Part 15
FCC Title 47, Code of Federal
Landmobile Radios
Part 90
Regulations
RS-204-C
EIA Recommended FM/PM Receiver
Standards
Standard
EIA Recommended FM/PM Transmitter
EIA-152-B
Standard
Standards
EIA-316-B
EIA Recommended Test Conditions,
Standard
Radio Standards

REFERENCE LITERATURE
The following Motorola literature may be useful when
designing with the MC3362/3 receivers:
Parts Referenced
Number
Description
DL128, Rev. 2 Linear and
MC3362, MC3363,
Interface Device MC34119, MC2831A,
Data
MC2833, MC13060,
MC33171
DL130
CMOS/NMOS
MC1451XX CMOS
PLL's
Special
Functions Data
DL122
MECL Device
MC12XXX ECL
Data
Prescalers
DL126
Small Signal
3N211, MPF211
Transistor Data

COMPANION DEVICES
• The MC2831A and the MC2833 low power FM transmitter ICs provide all essential functions for cordless
telephone and general transmitter and oscillator applications through 60 MHz (MC2831A) and 200 MHz
(MC2833, using internal very high frequency [VHF]
transistors as frequency multipliers).
• The MC34119 low power audio amplifier with differential outputs provides efficient power transfer and
MOTOROLA COMMUNICATIONS DEVICE DATA

•
•
•

•
•
•

•

eliminates the need for the typical large audio coupling
capacitor.
The MC13060 Mini-Watt audio amplifier (for higher
powered audio output).
The MC33171 low power single suppJy operational
amplifier for use as an RSSI buffer or active integrator.
The MC14516X series of dual PLL frequency synthesizers for development of 10 channel cordless telephone
band transceivers.
The MC12XXX series of ECL prescalers and
MC1451XX series of CMOS Frequency Synthesizers for
development of VHF "high band" radios to 200 MHz
The MC145442/3 single chip 300 baud modems which
allow audio frequency shift keyed (AFSK) RF modem
design for very reliable data transmission.
The 3N211 and MPF211 dual gate MOSFET's for
MC3362 RF preamplification with AGC capability.

BLOCK DESCRIPTION
RF Amplifier (MC3363 only)
The MC3363 contains an internal NPN bipolar RF amplifier transistor. The base of the transistor is biased internally to approximately 0.8 Vdc, which simplifies
common-emitter amplifier design. Grounding the emitter
yields an emitter current IE = 1.5 rnA and voltage gain
AV = 20 dB with a collector load RL = 1 kn.
Emitter degeneration resistors can be added to lower
current drain, with RE decoupling used to preserve the
gain. With the emitter grounded the input at Pin 2 looks
like 180 n in parallel with 20 pF at 50 MHz. The noise
figure at 50 MHz and unity gain frequency (fr) of the NPN
transistor are approximately 2 dB and 3 GHz, respectively,
at IE = 1.5 rnA. The collector load can be resistive, as
shown in Figure 10, or tuned as shown in Figure 14. When
both input and output are tuned and/or impedance
matched care must be taken to prevent unwanted oscillations - this is why the 2 kn resistor is included in the
collector load of Figure 14.
First Mixer
The first mixer is a doubly balanced multiplier, driven
directly from the RF input and from the first local oscillator via a cascode amplifier. It is used to convert the RF
input frequency down to the first IF of 10.7 MHz. The
input admittance seen at either RF input pin is 670 ohms
in parallel with 7 pF at 50 MHz; that is, Rp = 670 nand
Cp = 7 pF. The series equivalent impedance at 50 MHz
is Rs = 210 nand Cs = 10.2 pF. The first mixer:s input
is differential, but can be driven single-ended with no
loss in system gain. If a single·ended input is used, be
sure to AC ground the unused pin. This can be done with
a bypass capacitor to the negative rail (VEE) or by connecting the pin directly to the VCC supply.
The isolation of the mixer is shown in Table 1, and of
particular value in many applications will be the strong
attenuation (41 dB) of the local oscillator at the mixer
input. The isolation is due to the fully balanced mixer
configuration used and helps to reduce LO radiation at
the receiver's antenna.
Table 1. First Mixer Isolation Level (in dB) at:
Signal
LO Tank Mixer Out (IF)
Mixer In (RF)
LO
0
-17
-41
RF
-16
-9
0
IF
-29
0
<-40

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Initial Alignment of LC Tank

Final Configuration

VARACTOR

VARACTOR

1STLOTANK

1ST LO TANK
VCC

1ST LO TANK
1ST LO OUT

VCC
lSTLO TANK

R1
BUFFERED OUTPUT
3 k!l
(OPTIONAL!

I-~--o

1STLO OUT

3 k!l

NOTES:
1. The varactor control pin controls the net capacitance across the
local oscillator tank pins. The net capacitance will be approximately
20-25 pF when this pin is left open and 10-15 pF when connected
to Vee, depending upon strays and the Vee value used. If the Vee
supply is regulated, connect the varactor control pin to Vee;
otherwise. bypass via a 0.01 p.F capacitor to ground.

2. Connect the oscillator as shown in the left hand drawing (Initial
Alignment) and adjust L1 so that the tank resonates approximately
2-3 MHz below the crystal frequency. The frequency should be
checked by examining the buffered output using a high impedance
probe or by some sort of inductive pickup which will not push the
oscillator off frequency. The frequency should be:
fLO

=

1
217 V(L1 + [2) Cvaractor
3. Break the Ll-L2 connection and add Xl and R2. Verify that the LO
operates at the desired frequency by applying an RF input of

I-~--o

o

BUFFERED OUTPUT
(OPTIONAL!

10.7 MHz above or below the crystal frequency and checking for
receiver quieting. Make sure that there is proper LO amplitude. Also
there should be approximately 200 mVpp seen at either LO tank pin.
The buffered LO output should yield 200-600 mVpp depending on
the Vee value used.
4. The R2 resistor must be included or else the oscillator will latch.
5. This method has been proven effective up to 65 MHz using 3rd
overtone crystals, but has proven unreliable at higher frequencies
(usually using 5th and 7th overtone types!. For higher frequency
operation on a single channel, a signal can be injected into the local
oscillator port. (See the "First Mixer and Oscillator" section.)
6. Component values: The R1 resistors should be 10 to 50 kO and are
included in order to add some current and gain to the local
oscillator. L1 should equal L2 in nominal value and a fixed value
might be used but startup with different crystals might be degraded.
R2 should be 300 to 1500 n. Xl should be 3rd overtone, series
mode resonant (no load capacitance specified).

Figure 2. Running the MC336213 First Local Oscillator
on a Single Channel Under Crystal Control

The open circuit conversion voltage gain of the first
mixer is typically 24 dB, flat to 7 MHz. Internal rolloff is
provided above 7 MHz to suppress RF and LO signals
and spurious products sent on to the second mixer. The
gain at 10.7 MHz is typically 18 dB. The output circuit is
an emitter follower which is impedance-matched to 330
ohms to drive 10.7 MHz ceramic filters which typically
have 330 ohm input and output impedances. For applications which require a high impedance crystal filters,
impedance matching will likely need to be added at the
first mixer's output to preserve the filter's response.
First Local Oscillator and Varactor Diodes
Associated with the first mixer is the first local oscillator
(LO). It is a complete voltage controlled oscillator and
only requires an external LC tank circuit (no external varactor diode). For multichannel applications, the oscillator
includes varactor tuning and a buffered output suitable
for interfacing to a PLL frequency synthesizer. This is the
approach used in the receivers of Figures 10 and 11. The
maximum oscillation frequency obtained has been
approximately 190 MHz, achieved by injecting extra current into the oscillator. To inject current into the local
oscillator, connect pull-up resistors of 10-50 kG from VCC
to each LO tank pin. The LO buffered output varies from
400 mVpp to 1100 mVpp with supply voltage and the
output waveform appears best with Rpd = 3 kG, as
shown in Figure 3.
There are internal varactor diodes which have capacitance which appears across the local oscillator tank pins.
The internal capacitance can ra~ge from 10 to 25 pF

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depending on the control voltage applied to the varactor
control pin (MC3362 Pin 23, MC3363 Pin 27). The capacitance is maximum when the voltage applied is at the
minimum (0.7 V) value. Applying voltages greater than
VCC and lower than 0.7 V to the varactor control pin can
cause the oscillator to stop.
The first local oscillator can be crystal controlled to run
on a single channel. The procedure of Figure 2 shows
how to do this for applications through 65 MHz. The
receiver of Figure 10 uses this approach.

Figure 3, First Local Oscillator Buffered Output

MOTOROLA COMMUNICATIONS DEVICE DATA

A third application of the local oscillator is to drive it
from an external source. This is recommended for applications from 75 MHz to 200 MHz and beyond which do
not require PLL frequency synthesis. The inputs are differential and they must be driven using a wideband RF
transformer or balun. The input voltage seen at either
tank pin should be roughly 100 mVrms to ensure proper
operation of the mixer and care should be taken so that
any inductance present at the LO tank pins does not resonate with the internal varactor capacitance (a small valued resistor of 50-100 n should ensure this does not
occur). Using this approach, no loss in mixer gain is seen
until the RF and LO inputs are taken over 450 MHz. The
RF and LO inputs should be run with a 10.7 MHz difference in frequency to accommodate the first IF bandwidth,
so image frequency considerations (preselector filter
quality) may limit the maximum RF input frequency to
less than 450 MHz.
Second Mixer and Second Local Oscillator
After the 10.7 MHz IF signal is filtered using a ceramic
filter, it is applied to the second mixer input. The second
mixer is also doubly balanced to reduce spurious
responses and typically is used to convert the 10.7 MHz
IF down to 455 kHz for application to the limiting amplifier
and detection circuitry. In the typical low cost application,
the mixer is driven single-endedly from a ceramic filter,
with one ofthe mixer inputs bypassed directly to the VCC
supply. The open circuit conversion voltage gain is typically 25 dB. For applications which require a high impedance crystal filter, impedance matching will likely need
to be added at the second mixer input to preserve the
filter response. The second mixer output is rolled off
above 500 kHz, to reduce spurious response and idle
noise.
The second local oscillator is a Colpitts type which is
typically run under crystal control. The crystal used is
specified for fundamental mode operation, calibrated for
parallel resonance with a load capacitance of 30-40 pF.
The typical waveform seen at the base is shown in Figure
4. The oscillator can be run at 10.240 MHz or 10.245 MHz,
depending on the first local oscillator frequency desired.

Figure 4. Second Local Oscillator Waveform

MOTOROLA COMMUNICATIONS DEVICE DATA

The MC3362 second local oscillator has a buffered output
available which can be used to drive the reference frequency input of a PLL synthesizer or a prescaler. An external local oscillator signal can be injected into the local
oscillator's base, with the emitter pin left open. The signal
should be sinusoidal and should be approximately 300
mVpp to 500 mVpp in level.
The output admittance of the second mixer at 500 kHz
is 1500 n in parallel with 50 pF; that is, Rp = 1500 nand
Cp = 50 pF. The series equivalent impedance is Rs =
1420 nand Cs = 1065 pF. This impedance matches the
typical input impedance of standard 455 kHz ceramic filters, which have 1500-2000 n typical input and output
impedances.
Limiting IF Amplifier and Quadrature Detector
The 455 kHz IF signal is applied to the limiting IF amplifier, where it is amplified and limited before application
to the quadrature detection circuitry. The limiting IF
amplifier input has an input impedance of approximately
1.5 kn, which provides good power transfer from 1.5 kn
ceramic filters. The limiting IF circuitry has 10 p.V input
sensitivity for - 3 dB limiting, flat to 1 MHz. In order to
preserve overall power supply current drain, the limiting
IF and the receiver in general are not designed for wideband applications.
The coupling capacitor from limiter output to quadrature tank and detector input is provided internally and its
value is 5 pF. The 455 kHz oscillator circuit is typically
built around an LC tank circuit, with Cp = 180 pF, Lp =
680 p.H. Typical ceramic resonators can not be driven
from the quadrature tank pin. A waveform like that of
Figure 5 should appear at the quadrature tank pin during
periods of full receiver quieting and no modulation.
Meter Drive (RSSI)
The amplitude of the RF input signal at the appropriate
frequency is monitored by meter drive circuitry. This circuitry detects the amount of limiting in the limiting IF
amplifier and produces a linear change in current (nominally 0.1 p.A) at the meter drive pin for each decibel of
change in the RF input. The meter drive circuitry is fairly

Figure 5. Quadrature Tank Pin Waveform Under
Strong Received Signal Condition

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linear for input signal levels over a 60 dB range. This
output can be used as a meter drive or Received Signal
Strength Indicator (RSSI) and needs to be bufffered. In
order to provide a linear, wide ranging RSSI output voltage, three things must be accomplished:

Vee2

Vee1

1. The Meter Drive pin (MC3362 Pin 10, MC3363 Pin 12)
should be clamped to within VBE/2 (approximately 300
mV) of the MC3362/3 supply voltage, or loading of the
Meter Drive's current source will occur. The carrier
detect output is disabled (high output) when the
Meter Drive pin is clamped in this manner. There are'
diodes present at the Meter Drive pin which can interfere with the Meter Drive. (See Figure 6 for a schematic
representation.) With these diodes present the voltage
swing possible at the Meter Drive pin is limited to a
diode drop above and below the VCC supply.
2. Some type of current to voltage conversion must take
place. The RSSI output is typically 4 to 12 pA
3. Negative feedback must be provided in the output
buffer to counteract buffer amplifier gain variations.
Some method of output level adjustment may be
desirable.

Vee

METER
ESD
DIODE

DRIVE

Figure 6. Schematic Representation of Meter Drive
"Parasitic Circuits"
Carrier Detect
Another configuration for the meter drive and carrier
detect circuitry, is to program the carrier detect output
using a resistor from the meter drive pin to the VCC supply. The carrier detect pin is an open collector output so
a pull-up resistor is required. The carrier detect is active
low, meaning that an RF input above the programmed
trip level will yield a low output «0.1 V) at the carrier
detect pin. When the RF input is below the trip level (or
is detuned) the carrier detect pin will be at the supply
voltage. The trip level is set by the resistor value used
between the meter drive pin and supply. A resistor of
130 kfl sets the trip level to approximately - 110 dBm at
the first mixer's input, which is roughly the 12 dB SINAD
point of the receivers with no external RF amplification.
It should be noted that the meter drive current will not
have the .same linear 0.1 JLA/dB current-input level relationship as when the meter drive is buffered as discussed
above, so an analog RSSI output is not really achievable
when Carrier Detect is .used.

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RSSIOUTPUT

Figure 7. Sample RSSI Buffer
• Recommend MC33171 as the operational amplifier.
The MC33171 is a low-power single supply single op
amp with offset adjustment capability.
• VCCl = MC3363 supply (2 V to 7 V)
• VOUT = VCCl + Imeter (Rf)
• VCC2 = Op amp supply. Make this high enough to stay
within the op amp's common mode input range equal to VCCl + 2.2 V for the MC33171. This voltage
also must be high enough to provide the maximum
VOUT desired.
• Rls can be added to level shift the output, and is
optional. The output voltage will be adjusted downward by a factor of (VCCl - VCC2)(Rf/Rls)'
• Compensation capacitor Cc is added to ensure stability
and will limit the circuit's response time.
• This circuit is not recommended for general purpose
AM detection.

Muting (MC3363 only)
Audio muting can be provided in two ways. The carrier
detect output can be DC coupled to the MC3363 muting
op amp input (Pin 15) and the op amp output can serve
to mute the audio. That is, the op amp output (Pin 19)
serves as a switch to ground in the audio signal path.
When the carrier level decreases below the carrier detect
trip point, the carrier detect pin will go to VCC and the
op amp output will go into saturation, muting the audio.
This yields a simple squelch with minimum external components and is shown in Figures 10 and 14.
Another way to mute the audio on MC3363 is to use
the op amp as an active filter for detecting noise above
the audio passband. The recovered audio is fed through
the active filter, rectified, integrated and compared to a
reference level. When the level rises above the reference,
a squelch gate is triggered. The data slicing comparator
on the MC3363 might be used as a squelch gate. This
noise triggered squelch would be executed similarly to
the squelch in MC3357/59/61 FM IF applications. (See the
MC3359 data sheet for details.) This type of squelch frees
the Meter Drive circuit to provide a linear output as noted
under "Meter Drive (RSS!)" above.

MOTOROLA COMMUNICATIONS DEVICE DATA

Data Recovery
Both receivers contain a data slicing comparator which
provides data shaping and limiting of frequency-shift
keyed (FSK) serial data transmissions. The data slicer is
a non-inverting type, with the negative input terminal
biased internally to VCC/2. Typically the data slicer is AC
coupled to the recovered audio pin via a 0.01 /LF to 0.1 /LF
capacitor. Larger coupling capacitors can cause distortion
of the detected output and this is seen as negative slew
rate limiting in Figures Band 9. A pull down resistor from
the detector output pin to VEE will reduce this effect if
objectionable. The comparator output is an open collector so a pull-up resistor is required.
Comparator hysteresis is available by connecting the
comparator output and input using a high-valued resistor. This helps maintain data integrity as the recovered
audio becomes noisy, or for long bit strings of one polarity. Resistor values below 120 kn are not recommended
as the comparator input signal will not be able to overcome the large hysteresis induced. Figure BA shows data
jitter resulting from noisy demodulated data signal. The
improvement seen when hysteresis was added is shown
in Figure BB.

The maximum usable FSK data rate for any narrowband FM system is typically 1200 baud subject to IF and
quadrature bandwidth and adjacent channel spacing limitations. The approximate bandwidth required to generate or receive a frequency modulated signal is:
BW = 2 (fmod + fdev) kHz, where fmod is the modulating frequency and fdev is the frequency deviation.
This is known as Carson's Rule and is fairly accurate.
Any modulating signal which exceeds the available IF
bandwidth will be attenuated and/or distorted. For proper
recovery of square waves including the leading and trailing edges approximately the 7th harmonic should be
present. For a 1200 baud (600 Hz) square wave with fdev
= 3 kHz, fmod = 4.2 kHz (7th harmonic of 600 Hz square
wave), the bandwidth niieded is: BW = 2(4.2 + 3) kHz
= 14.4 kHz = ±7.2 kHz, which is acceptable in narrowband FM channels. Figures 9A and 9B show the effect of
trying to pass a 9600 baud modulated carrier through a
narrowband channel, with resulting degradation of
recovered data.

Figure SA. Noisy Recovered Data Signal
Causes Data Jitter

Figure SB. Improvement in Data Jitter
Through Addition of Hysteresis

Figure 9A. FSK Data Recovery at 1200 Baud

Figure 9B. Distortion of Recovered Audio
with 9600 Baud Modulation

MOTOROLA COMMUNICATIONS DEVICE DATA

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For narrowband RF modems where 300 baud is adequate, an audio frequency shift keyed (AFSK) approach
is recommended. In this application two audio tones (for
Logic "0" and Logic "1 ") are modulated onto an RF carrier
and transmitted to the receiver, which reproduces the
audio tone sequence. The audio tones can be generated
at the transm itter and decoded after the receiver by the
MC145442/3 single chip 300 baud modems.

receiver sensitivity and noise quieting will suffer, and
oscillations can occur.

APPLICATIONS CIRCUITS

Single Channel VHF FM Narrowband Receiver
The first application shown is of a complete single
channel VHF receiver operating at 49.67 MHz. This application includes a suitable circuit for running the first local
oscillator under crystal control on a single channel, which
is particularly useful for dedicated remote control links
and low cost two-way radios through 75 MHz. The circuit
contains a simple carrier level based squelch circuit and
audio amplification.
The 49.67 MHz receiver frequency is within the 49 MHz
USA cordless telephone band. Radios built for this band
may qualify under FCC Code of Federal Regulations Title
47, Part 15, for use by unlicensed operators. It is important to know the federal regulations concerning a particular frequency channel or band of channels before a
receiver circuit is design (see the notes on FEDERAL REGULATIONS, RECOMMENDED STANDARDS above).
Figure 10 shows the complete receiver schematic. The
LC network shown is used to match the input impedance

BREADBOARDING
Do not attempt to build a high frequency radio circuit
using a wirewrap or plug-in prototype board. While the
MC3362 and the MC3363 are "tame" as high gain receivers go, high frequency layout techniques are critical to
obtaining optimal receiver performance. This means
(typically) a one- or two-sided copper clad board with
adequate ground plane connected to VEE potential. It is
also important that all VCC interconnections are made
using copper traces on the board. Do not use "free floating" point to point wiring for the VCC interconnections!
In general, keep all lead lengths as short as possible, with
an emphasis on minimizing the highest frequency pathlengths. Decoupling capacitors should be placed close to
the IC. If these techniques are not followed then the

RF INPUT
49.67 MHz

50.n

W9Po~1-t--{:J

MC3363DW

0.D1 J.t

28

1000p

(

r---CJ-rYY"'Or,--+-_-""~10

k

·~{J~~--~-~~~10k

TEST
POINT

100 k

+

1~
LEGEND:
Xl ~ 10.245 MHz, fundamental mode. load capacity 32 pF.
Fl ~ 455 kHz ceramic filter, Rin '" Rout ~ 1.5 kO to 2 kO.
Part numbers are muRata CFU455X or CFW455X - suffix

denotes bandwidth.
lC1 = 455 kHz quadrature tank circuit. Part numbers are Toko
RMC2A6597 HM or 5SVLC-0637BGT (smallerl. Ceramic
discriminators cannot be used with the MC3362/3, as their input
impedance is too low.

Pl
F2

~

X2

=

~

10 kO, audio taper.
10.7 MHz ceramic filter, Rin ~ Rout ~ 330 O.
Part numbers are muRata SFE10.7MJ-A, SFA10.7MF5, or
SFE10.7MS2-A.
38.97 MHz, 3rd overtone, series mode
(no load capacity specifiedl.

All capacitors in microfarads, inductors in Henries and resistors in
Ohms unless otherwise specified.

Figure 10. Single Channel FM VHF Receiver at 49.67 MHz

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MOTOROLA COMMUNICATIONS DEVICE DATA

of the RF amplifier to 50 n at this frequency. The amplifier
collector load is a single resistor for simplicity and in
order to enhance stability. The method of Figure 2 was
used to develop the crystal controlled oscillator circuit at
38.97 MHz. The RC integrator rolls off the audio above 2
kHz in order to minimize unwanted noise output. This
enhances receiver sensitivity and provides proper audio
deemphasis. The receiver, without the audio amplifier,
has 6.2 mA current drain at VCC = 5 V for a total dissipation of 31 mW. Using a 455 kHz filter with a 6 dB
bandwidth of ± 10 kHz the receiver has a 12 dB SINAD
point of 0.28/.N, modulation acceptance of 10.4 kHz and
distortion below 1.2% with fmod = 1 kHz and modulation
deviation fdev = 3 kHz. The maximum (S + N)/N ratio
obtained is 60 dB.
The MC34119 audio amplifier adds 3 mA quiescent current drain at 5 V, can deliver 250 mW into an 8 n speaker

Vcc

17

and has differential outputs which eliminate the need for
the typical large audio coupling capacitor. It also has a
chip disable input which provides muting and power
conservation.
Ten Channel Frequency Synthesized
Cordless Telephone Receiver
A demonstration receiver circuit has been built featuring the MC3362 and the MC145160 dual phase locked
loop (DPLL). This receiver features frequency synthesis
to cover the ten channels allocated in the USA for cordless telephone (CT) receivers in the 46 MHz (handset) and
49 MHz (base station) frequency ranges. The MC14516X
series DPLL's feature two complete loops which control
both the transmitter output and receiver first LO
frequencies.

9B7654
11 P

OSC IN

DPLL MC14S160

18i--=-'c::...;,:,'-----l1-------~

13

V+

27 k

TaKa
291GCS·5Bl0N

DATA

.---------~-'::'--<>OUTPUT

Vcc
"""'VIA_-o AUDIO
OUTPUT

560

50 rT~-l::::

~
_

~

I

22~

_ _ --1

-=

-=-=
TaKa

291 GCS·5Bl ON

Figure 11. Ten Channel Frequency Synthesized Receiver
MOTOROLA COMMUNICATIONS DEVICE DATA

AN980

4-231

I

:Et
'
fl

MC3362

T1
0.8 JLH

50ll

~

-=-

24

2

4

I
I

I

6

-=-: -=-

T1 and T2 wound on

Taka Type 7KM
7 mm Shielded Cores.

12 P

Figure 12. Information on T1 and T2 of Figure 11

1ST LO

BUFFER
OUTPUT

r---I MC3362
I

1ST

LOCAL
OSC

FIN·R
MC14516X
PO·R

3.3 k

Figure 13. Simple Interface of MC3362/3
To DPLL MC14516X
Figure 11 shows the complete schematic diagram. A
simple RF transistor amplifier is included to overcome
antenna and RF preselector losses. The output of the VCO
buffer is amplified by an external transistor amplifier so
that the VCO signal strength is large enough to drive the
receiver input pin (Fin-R) of the DPLL properly. Gain of
the VCO is set at approximately 400 kHz using the LC
values shown. The SB (Pin 3) of the MC145160 is
grounded to disable the transmit loop to simplify development of the circuit and reduce power consumption.
The DC voltage at the varactor control input of the
MC3362 (Pin 23) is adjusted to VCC/2. The system reference frequency of 10.240 MHz is generated in the
MC3362 second LO and fed into the Osc-In (Pin 18) of the
MC145160.
With a supply voltage of VCC = 3 V and modulating
signal fmod = 1 kHz, fdev = 3 kHz the receiver yields
an input sensitivity of 0.6 pV for 20 dB noise quieting
and 0.2 pV for 12 dB SINAD from a 500 source. The

AN980
4-232

audio distortion is less than 3 percent. The minimum
noise floor is less than 80 /LV and the maximum (S + N)I
N ratio is 53 dB.
There is a simpler way to interface the MC3362/3 to the
MC145160 DPLL as shown in Figure 13. The VCO signal
(about 400 mVpp with Vec = 3 V using a pull-down
resistor of 3 kO from the MC3362 Pin 20 to VEE) is fed
directly into the Fin-R input (Pin 16) of the MC145160.
With this configuration, the noise floor is raised to 245 /LV,
10 dB higher than the circuit of Figure 11.

256 Channel Frequency Synthesized
Two Meter Amateur Band Receiver
A more traditional PLL frequency synthesizer approach
is needed to provide frequency flexibility and to allow
the MC3362/3 receivers to operate in the VHF "high band"
(130 MHz to 172 MHz). A receiver is shown which covers
the entire Two Meter (referring to radio wavelength) amateur radio band from 144 MHz to 148 MHz in 256 channels
spaced at 20 kHz. The complete receiver and PLL frequency synthesizer are shown in Figures 14 and 15. The
receiver achieved the same specifications as the
49.67 MHz MC3363 receiver discussed above~
The MC3363 receiver was chosen because squelch and
good sensitivity with minimum component count were
desired. To obtain good operation of MC3363 VCO above
75 MHz, the first local oscillator must be running well. To
ensure this, the VCC supply voltage is kept above 3 V
which increases the current in the local oscillator circuitry. Extra current is also injected into the local oscillator
via pull-up resistors of 10 kO from each of the local oscillator tank pins to the VCC supply. With the components
of Figure 14, the receiver VCO had an average gain of
1.5 MHzN.
The VCO output is amplified and fed into an MC12017
dual modulus prescaler which drives the input of the PLL
frequency synthesizer. The MC145152-2 PLL frequency
synthesizer was chosen for its ease of use and parallel
input format. The MC33171 bipolar operational amplifier
was chosen as the active integrator (loop filter) because
of its low power drain, offset adjustment capability and
ability to operate from a single supply voltage. The design
equations and assumptions used to determine loop filter
components are shown below. The MC145152-2 data
sheet and other sources go into much more detail on PLL
theory and performance.

Calculations of Loop Filter For VCO PLL
Frequency Synthesis
Assumptions:
fo = 135.3 MHz (local oscillator center frequency)
fs = 20 kHz (channel spacing)
fb = 0.01 fs (loop bandwidth)
f rc = 20 fb (filter cutoff frequency)
§ = 0.707 (loop damping factor)
VDD = 5 V (PLL supply voltage)
KVCO = 9.4 x 106 radN (VCO gain, measured on
MC3363 receiver)
Cl = 0.1 /LF (active integrator component)

MOTOROLA COMMUNICATIONS DEVICE DATA

Table 2. PLL Frequency Synthesizer Switch
Settings and Frequencies

Results:
fb = 0.Q1 fs = 0.01 (20 kHz) = 200 Hz
f rc = 20 fb = 20 (200) = 4 kHz
Kill = VDD 1 2'IT = 0.796 (phase detector gain)
wn = 2'ITfb
{2§2 + 1 + ((2§2 + 1)2

+

1I O•5}0.5

Switches

C257)
2.06 = 610 rad/sec

00000000
00000001
01000000
01111111
10000000
10001101
10011100
11010001
11111111

Nt = fo 1 fs = 135.3 MHz 120 kHz = 6765
Rl = Kill KVCO 1 (Cl wn 2 Nt) = 29.7 kG == 30 kG
R2 = 2 § -;- (wn Cl) = 23.2 kG == 24 kG
Cc = 4 -;- (2 Rlfrcl == 0.017 /LF
With an 8 bit parallel input format several possible
switch settings and resultant counter values and receiver
frequencies are shown in Table 2 below (Note: Nt = NP
+ A, where P = 64 for the MC12017).

RF INPUT
144-148 MHz
50n

\L7 22 P

N

P

A

~

104
104
105
105
106
106
106
107
107

64
64
64
64
64
64
64
64
64

0
1
0
63
0
13
28
17
63

6656
6657
6720
6783
6784
6797
6812
6865
6911

f rx (MHz)

'vee
(MHz)
= Ntfs
133.12
133.32
134.40
135.66
135.68
135.94
136.24
137.30
138.22

= fvee +
10.7 MHz
143.82
143.84
145.10
146.36
146.38
146.64
146.94
148.00
148.92

MC3363DW
rr------------~28

0.05 p.

y(~

39 P

*

veo
0,01

r---n-~------_f-

I

TUNING VOLTAGE
ISEE FIGURE 15)
39 p

)-t:J-....L~4-____--'II'10""k4 ~2.2 k

Vee

10k

=

5V.
REGULATEO

3k

0.22 p.

veo OUTPUT

4+---~-

1 Vpp
ISEE FIGURE 151

20 P

MC34119D
LOW POWER
AUDIO AMPLIFIER

1

8

0.1

100 k

LEGEND:
Xl
= 10.245 MHz. fundamental mode. load capacity 32 pF.
Fl
= 455 kHz ceramic Ii Iter. Rin = Rout = 1.5 kn to 2 kn.
Part numbers are muRata CFU455X or CFW455X - suffix
denotes bandwidth.
LC1
= 455 kHz quadrature tank circuit. Part numbers are Toka
7MC-8128Z or 5SVLC-0637BGT Ismallerl. Ceramic
discriminators cannot be used with the MC336213. as their
input impedance is too low.

Pl
F2

= 10 kn. audio taper.
= 10.7 MHz ceramic filter. Rin = Rout = 330 n. Part numbers
are muRata SFE10.7MJ-A. SFA10.7MF5. or SFE10.7MS2-A.
= 3 Turns #18 AWG. 0.25" diam .• 0.125" spacing. air wound.

L1
VCC2 = 2-12 V. must be well decoupled Irom the VCC source for the
MC3363.
All capacitors in microfarads. inductors in Henries and resistors in
Ohms unless otherwise specified.

Figure 14. 2 Meter Frequency Synthesized FM Receiver

Single Chip Weatherband Receiver
An application of the MC3362 as a simple receiver
tuned to the NOAA Weatherband (162.4 MHz to
162.55 MHz) is shown in Figure 16. The RF input is
applied directly to the mixer input, using a simple "L
network" to provide impedance matching of the mixer

MOTOROLA COMMUNICATIONS DEVICE DATA

input to 50 G. The system sensitivity for 12 dB SINAD
is 0.67 /LV at the input from a 50 G source in this application, which is as good as most inexpensive weather
cubes and the dual conversion design allows for excellent image protection to be provided.

AN980
4-233

MC145152-2
Fin

LD
OSCin tJ-~=:--1I

VSS
VDD

OSCout

RAO

A4

RAI

A3

NOTES:
1. The values of Al, R2, Cl and Cc are very important in determining
the loop characteristics. Those values calculated in the text gave
fairly "clean" veo Control Voltage and veo Buffered Output
signals.
2. Switches 51-58 can be mini-DIP or hexadecirnally coded
thumbwheel switches. S1 is the MSB, 58 is the LSB.
3. VCC3 :=: 7.2 V minimum, to ensure that the MC33171's input
common mode range is not exceeded. An acceptable way of

RA2
~R
~V

Al

configuring the entire receiver's power is:

MC

Vee. Voo

0.1 Jl- 5 V, REGULATED
y-.L..--t--~

A5
NO

Nl
N2

R112

R112
10 k

N3
R112

VCO TUNING VOLTAGE
ISEE FIGURE 141

J. 0,01 fJ-

Figure 15. 256 Channel VCO Control Using PLL Frequency Synthesizer

t

FINPUT 1162.40-162,55 MHz, 50 01

5P

MC3362

50 p

1-.--1----11------1

VCC

0,1
+--_--"V\"v--..-l12 t--"""'>-±'~"'"
O-..J'PN">-01

1

I

: TOKO RMC
:
L-_~~r...._J

Lp = 680fJCp = 180 P

NOTES:

1. Make Vee connections along a substantial portion of copper plane.
Do NOT use point to point wiring for Vee interconnections!
2, Vcc (MC3362) ~ 2 V to 7 V, regulated, First local oscillator will drift
if this supply is not regulated!
3, VCC2 (MC34119) ~ 2 V to 12 V, must be well decoupled from the
VCC source for the MC3363.

4. L 1 = 3 turns #18 AWG, .2" dia., .05" spacing, air wound.
5. Pins 1 and 24 are differential RF input, and are unmatched and used
single-ended in this circuit. If single-ended input is used, be sure to
bypass the unused pin.
6. All capacitors in microfarads, inductors in Henries and resistors in
Ohms, unless otherwise specified.

Figure 16. MC3362 Application as a Tunable Weather Band Receiver

AN980
4-234

MOTOROLA COMMUNICATIONS DEVICE DATA

The first local oscillator is free-running in this application and the receiver is manually tunable over a range
of ± 1 MHz. The oscillator's frequency and tuning range
are determined by the external tank circuit values chosen.
Keep in mind that the internal varactor diodes add
10-25 pF of capacity across the tank pins, depending on
the varactor control voltage applied.
This circuit is easily built to vefify receiver characteristics on the lab bench, but as shown is not suited for
mass production. The local oscillator temperature stability is not nearly adequate in this free-running configuration and microphonic pickup is difficult to avoid.
Before a narrowband receiver is production-ready, the
first local oscillator must be stable to within approxi-

APPENDIX -

mately ± 100 Hz. The "First Mixer and Oscillator" section
provides notes on driving the first mixer using an external
oscillator signal above 50 MHz. The MC2833 FM transmitter IC might serve as the local oscillator source up to
200 MHz.

SUMMARY

The high degree of integration and MOSAIC process
used in the MC3362/3 receivers give the radio designer
new levels of space and power economy, while providing
high performance and considerable design flexibility. The
receivers shown and alternate configurations discussed
should interest designers of cordless phones, VHF two
way radios, remote control receivers, wireless data links
and home security systems.

DIRECTORY OF COMPONENT MANUFACTURERS

muRata-Erie
2200 Lake Park Drive
Smyrna, GA 30080

(404) 436-1300
ceramic filters

Toko America Inc.
1250 Feehanville Drive
Mount Prospect, IL 60056
Distributor - Digikey
Distributor - Inductor Supply

(708) 297-0070
quadrature coils
coils, transformers
(800) 344-4539
(800) 854-1881
(800) 472-8421 (California)

Coilcraft
1102 Silver Lake Road
Cary, IL 60013

(708) 639-6400
coils

California Crystal Laboratories

(800) 333-9825
crystals

Fox Electronics

(813) 693-0099
crystals

International Crystals

(405) 236-3741
crystals

Standard Crystal Corporation

(818) 443-2121
crystals

Note: Design-in kits including printed circuit boards are available from analog marketing. Call (602) 897-3820

Motorola does not endorse the vendors listed.
This is a partial vendor list and no liability is assumed
for omissions or errors in address, product line or other information.

MOTOROLA COMMUNICATIONS DEVICE DATA

AN980
4-235

MOTOROLA

-

SEMICONDUCTOR
TECHNICAL DATA

AN1207
The MC145170 in Basic HF and VHF Oscillators
Prepared by: David Babin and Mark Clark

Phase-locked loop (PLL) frequency synthesizers are commonly found in communication gear today. The carrier
oscillator in a transmitter and local oscillator (LO) in a receiver
are where PLL frequency synthesizers are utilized. In some
cellular phones, a synthesizer can also be used to generate
90 MHz for an offset loop. In addition, synthesizers can be
used in computers and other digital systems to create different
clocks which are synchronized to a master clock.
The MC145170 is available to address some ofthese applications. The frequency capability of the MC145170 is very broad
- from a few hertz to 160 MHz.

ADVANTAGES
Frequency synthesizers, such as the MC145170, use digital
dividers which can be placed under MCU control. Usually, all
that is required to change frequencies is to change the divide
ratio of the N Counter. Tuning in less than a millisecond is
achievable.
The MC145170 can generate many frequencies based on the
accuracy of a single reference source. For example, the reference can be a low-cost basic crystal oscillator or a
temperature-compensated crystal oscillator (TCXO). Therefore, high tuning accuracies can be achieved. Boosting of the
reference frequency by 100x or more is achievable.

ELEMENTS IN THE LOOP
The components used in the PLL frequency synthesizer ·of
Figure 1 are the MC145170 PLL chip, low-pass filter, and
voltage-controlled oscillator (VCO). Sometimes a voltagecontrolled multivibrator (VCM) is used in place of the VCO.
The output of a VCM is a square wave and is usually integrated before being fed to other sections of the radio. The
VCM output can be directly used in computers and other digi-

tal equipment. The output of a VCO or VCM is typically
buffered, as shown.
As shown in Figure 2, the MC145170contains a reference oscillator, reference counter (R Counter), VCONCM counter (N
Counter), and phase detector. A more detailed block diagram
is shown in the data sheet.

HF SYNTHESIZER
The basic information required for designing a stable high-frequency PLL frequency synthesizer is the frequencies
required, tuning resolution, lock time, and overshoot. For the
example design of Figure 3, the frequencies needed are
9.20 MHz to 12.19 MHz. The resolution (usually the same as
the frequency steps or channel spacing) is 230 kHz. The lock
time is 8 ms and a maximum overshoot of approximately 15%
is targeted. For purposes of this example, lock is considered
to be when the frequency is within about 1% of the final value.

HF SYNTHESIZER LOW-PASS FILTER
In this deSign, assume a square wave output is acceptable. To
generate a square wave, a MC1658 VCM chip is chosen. Per
the transfer characteristic given in the data sheet, the MC1658
transfer function, KVCM, is approximately 1 x 108 radians!
second/volt. The loading presented by the MC1658 control
input is large; the maximum input current is 350 ~A. Therefore,
an active low-pass filter is used so that loading does not affect
the filter's response. See Figure 3. In the filter, a 2N7002 FET
is chosen because it has very high transconductance (80
mmhos) and low input leakage (100 nA).

DIVIDE VALUE

REFERENCE
OSCILLATOR

REFERENCE
OSCILLATOR
TO
LOW-PASS
FILTER
FROM

VCONCM

MULTIPLYING VALUE
Figure I. PLL Frequency Synthesizer

AN1207
4-236

Figure 2. Detail of the MC145170

MOTOROLA COMMUNICATIONS DEVICE DATA

+5V

+5V

+5V
1.5kn
BIAS

PLL
FREQUENCY
SYNTHESIZER

LOW·PASS
FILTER

VCM
16

16

47pF
O.OIIlF

Rl
DATA IN
ENABLE
CLOCK

MC145170
':'

8

.~

MC1658
0.01
IlF

9

8

lMQ

lMQ

':'

O.OIIlF

O.OIIlF

OUTPUT
PULLDOWN

510Q

LOW-PASS FILTER

BUFFER/FILTER
':'

Figure 3. HF Synthesizer

In order to calculate the average divide value for the N Counter, follow this procedure. First, determine the average
frequency; this is (12.19 + 9.2)/2 = 10.695 MHz or approximately 10.7 MHz. Next, divide this frequency by the resolution:
10.7 MHzl230 kHz = about 47.

1.8

Next, reference application note AN535 (see book DL130/D
Rev 1). The active filter chosen takes the form shown in Figure
9 of the application note. This filter is used with the single-ended phase detector output of the MC145170, PDout. The
phasedetectorassociatedwithPDouthasagainKm = VDoI411.
For a supply of 5 V, this is 5/411 = 0.398 Vlrad. The system's
step response is shown in Figure 4. To achieve about 15%
overshoot, a damping factor of 0.8 is used. This causes frequency to settle to within 1% at wnt = 5.5.

1.4

The Information up to this point is as follows.
fref = 230 kHz
ivCM = 9.2 to 12.19 MHz; the average is 10.7 MHz,
average N = 47
power supply = 5 V for the phase detector
KVCM = 1 x 108 radls/V
overshoot = approximately 15%, yields a damping
factor = 0.8
lock time t = 8 ms settling to within 1%, wnt = 5.5
K41 or Kp = 0.398 Vlrad.
From the application note, equation 61, wn = 5.5/t = 5.5/0.008
= 687.5 radls.
Equation 59 is R1C

~=0.1

1.7

I 1\ V 0.2
~ V 0.3

1.6

'r

1.5

~ 1.3

ill
::>

@

~~

1.2

I-

1.0

50

0.9

c..

cw

0.8

::1i
a:

0.7

~

/\

0.7

/

~~
1 ~l

a:
u. 1.1

::>

0.4

~ /0.5
H i'l? V 0.6
'/"",<

-h

0

z 0.6
8 00.5

r- 0.8

/

'In

1.0
2.0

- .\

'/:: ""'" ~

I"- ./VI

\\ )11

V7

i'..

II

\

J

\

\ I

a>

0.4
0.3
0.2
0.1

o0

1.0 2.0 3.04.0 5.0 6.0 7.0 8.0 9.0 10
IIlnt

11 12 13 14

= (Kp Kv)/wn 2 N

= (0.398 x 1 x 108)/687.52 x 47
= 1.79
Equallon 59 Is used because of the high-galn FET.

Next, the capacitor C is picked to be 1 1lF. Therefore,
R1 = 1.79/C which is 1.79 MO. The standard value of 1.8 MO
is used for R1.
Equation 63 is R2= (2~)/C wn
= (2 x 0.8)/(1 x 10-6 x 687.5)

MOTOROLA COMMUNICATIONS DEVICE DATA

Figure 4. Type 2 Second Order Step Response

=2.33 kn.
A standard value for R2 of 2.4 kn is utilized.

HF SYNTHESIZER PROGRAMMING

Programming the MC145170 is straightforward. The three
registers may be programmed in a byte-oriented fashion. The
registers retain their values as long as power is applied. Thus,

AN1207
4-237

usually both the C and R Registers are programmed just once,
right after power up.
The C Register, which configures the device, is programmed
with $CO (1 byte). This sets the phase detector to the proper
polarity and activates PDout. This also turns off the unused
outputs. The phase detector polarity is determined by the filter
and the VCM. For this example, the MC1658 data sheet
shows that a higher voltage level is needed if speed is to be
increased. However, the low-pass filter inverts the signal from
the phase detector (due to the active element configuration).
Therefore, the programming of the polarity for the phase detector means that the POL bit must be a "1."
The R Register is programmed for a divide value that results
in the proper frequency at the phase detector reference input.
In this case, 230 kHz is needed. Therefore, with the 4.6 MHz
source shown in Figure 3, the R Register needs a value of
$000014 (3 bytes, 20 in decimal).

VHF SYNTHESIZER
The MC145170 may be used in VHF designs, also. The range
forthis next example is 140to 160 MHz in 100 kHz increments.
VHF SYNTHESIZER LOW-PASS FILTER
To illustrate design with the doubled-ended phase detector,
the --~---o

L-a-J

To=1/27rlo T2 =Rz (C 1 +C ..l

T, :.; R,C,

£(-w) = £(w).

Therefore, to convert £(w) data to "straight" S.(w)
data, add 3 dB to the £(w) data and take the antilog.
An HP-19C program (see "Noise in a 5th-order
PLL") calculates this single-sideband noise, where
G(w)H(w) is the open-loop gain of the PLL.' The feedback path, H(w), is simply liN; and G(w) equals

(KpKvlwT,) (jwT, + 1)

+

1

S.(w)REF

supplied phase-noise data, designated £(w), and also
measured in dBc, are for single-sideband noise. (The
dBc designation is defined as 10 log,o of the ratio
between the output from a spectrum analyzer with
a I-Hz bandwidth and the signal's carrier level.)
Accordingly,
£(w) = 10 log,o(V2)S.(w) (per rad'),
assuming that

T)= R"C ..

A" 0:: op-amp de gain: fo = frequency at -3-d8 gain

Optimized for functional performance, the following
circuit constants are used for a typical PLL (Fig. 3):
Ao
To

Tv
T,
T2
T,

Kp
Kv
N

320,000
7.96 X 10-' s
= 1.59 X 10-' s
= 2.408 X 10-' s
;= 2.491 X 10-6 s
= 4.700 X 10-' s
= 314 X 10' VIrad
= 0.16 rad/V
=20.
=
=

The single-sideband phase noise, when calculated
by the program for a range of so-called Fourier
frequencies (offsets from a carrier, f = wI2,,), can
be plotted as in Fig. 4 (dotted line). Although this
output phase noise can be reduced by varying circuit
constants to illcrease the loop's bandwidth, proceed
with caution, because other desirable operating characteristics (such as circuit stability or speed of
response) could be compromised. The program, however, offers an easy way to determine how systematic
changes in the parameters affect noise.
Oscillator noise should be low

Phase
computation

[K,]

3. For a filth·order PLL, four of the time constants are
determined by the integrator/filler circuit, and the fifth Is
determined by the veo.

MOTOROLA COMMUNICATIONS DEVICE DATA

In addition to the calculated PLL noise, Fig. 4
shows a plot of the SSB-noise characteristics of the
circuit's VCO and crystal-reference oscillator. The
oscillators are the main source of phase noise in a
PLL. The information for plotting their noise can
be obtained from the manufacturers of the oscillators, or from measurements made by the user.
Where noise reduction is of prime importance,
select oscillators that generate minimum noise and
have noise spectral densities that complement each
other (as in Fig. 5). The point at which the two curves
AN254 #4
4-253

Noise In 5th order PLL

AN254#4
4-254

MOTOROLA COMMUNICATIONS DEVICE DATA

PLL noise and stability
crosB is called the crossover frequency (f,). This
frequency is an important parameter for optimizing
a PLL's noise characteristics.
In Fig. 5, the VCO noise-distribution plot is divided
into three characteristic regions. High-quality oscillators generally exhibit this spectral-density relationship. In region I, S,,(O is typically proportional
to 1If", so-called flicker-frequency noise; in region
II, S"(O is proportional to 11£2, so-called white-frequency noise; and in region III, S,,(e) is constant, socalled white-phase noise. Beyond region III, the
bandwidth limitation of the circuit at~enuates the

noise to negligible levels.
Region I noise stems from fluctuations in
oscillatorccircuit frequency-control components; region II, from thermal noise in the oscillator's gain
element; and region III, from additive thermal noise
from other elements of the circuit (including the gain
element).
A plot of the optimum phase-noise characteristic
of a PLL would coincide with the lower parts of the
two oscillator curves (heavy lines in Fig. 5).
The type-2, second-order PLLcircuit in Fig. 6 helps
to illustrate how closely this' condition can be approached. This circuit can be generalized by relating
the integrator's time constants (T, and T.) and the
VCO's and phase comparator's transfer coefficients
(K. and Kp) with a damping factor (d), and with the
reference and VCO crossover frequency (f, =
w,/2'11-), as follows:
d

T.
T,

= (T/2) .jKpK.lTl;
= 4d'lw,
=

d»l

T.KpK.lw,.

When these circuit parameters are considered
together with the circuit's open-loop gain (note:
Ill'·

~ouriert!8quenoy (HZ) .

H(w) = 1),

ill'

4. A PLL·ls optimized for performance characteristics, such
as stability, response time, and sideband levels; but the noise
characteristics generally fall where they may, as exemplified
In this plot of a fifth-order PLL.

G(w)H(w)

= KpK. (-jwT.-1),
T,w'

and substituted in the phase-noise equation for
S(w)O, the PLL's spectral density becomes

110
115

J1
1
s

l'

i

S(W)RE{

~ 130

w·

(2d) ( ~ ~
(1

w·

+(

~) +
4d'w'

~)

•]

(We)
w

REF

150

veo

155
III

10',

101
10' ,:'
Fourterfrequency (Hz)

10"

10'

5. The "optimum" PLL output-noise characteristic Is the one
that coincides most closely with the PLL's Intersecting
reference crystal oscillator and VeO-osclllator noise
characteristics (heavy lines). A high damping-factor value
(such as d = 10) makes the best correspondence with this
criterion.

MOTOROLA COMMUNICATIONS DEVICE DATA

The "Optimizing PLL Phase Noise" program with
its subroutine 0, solves this equation for any F~urier
frequency (f = wI2'11"). In Fig. 5, solutions are shown
for damping-factor values (d) of 0.5, 1.0, and 10.
The largest damping.factor (d = 10) causes the
noise curve to approach the "optimum" noise characteristic most closely-when it lies completely between the VCO/reference-oscillator lines and as
closely as possible to the lower lines. To satisfy this
criterion, the curve generally passes through the
frequency crossover point previously mentioned.
Larger damping values than 10 will provide little
further improvement. In fact, a larger damping value
would slow response more than it would lower the
noise output. Special cases may require low damping
AN254#4
4-255

Subroutine 0 must be performed before the
time constants can be calculated with subroutine 1

AN254#4
4-256

MOTOROLA COMMUNICATIONS DEVICE DATA

PLL noise and stability
factors-a value of 1 or even 0.5-to get a faster
response or the special noise-distribution shapes that
these lower damping factors produce.
After the phase-noise characteristics (based on the
fc of the oscillators and a selected damping factor)
have been calculated, a second part of the optimizing
program (subroutine 1) can then be used to calculate
the time constants T, and T, for the given Kp and
Kv of a type-2 second-order PLL.
Determining a PLL's short-term frequency stability requires integration of the spectral density of the
phase fluctuations to obtain the so-called Allan
variance (a dimensionless measure of stability,
where u,' is ..If!f in a short sample period). Thus
u,'(T,fh)

Whlte~
~

phase

noise
S¢(f)

""I Y :,,"1

~

"I

~

f

Whlte~
~>

frequ,ency
nOise

S¢(f)

FIiCkerll
f

frequ,ency

~"">

nOise

""

S¢(f)

fiT

~I

:

""1

fiT

'~I ~ :~"I
I.

f

f
Frequency
Time
domain I domain

"I
T

= __2_ f'jS.(f) sin' (1I'fT)df,
(TV1I')'

0

where T is the sampling time (in seconds), v is the
long-term average frequency (in Hz), and fh is the
bandwidth, or maximum excursion of the offset from
the carrier (the maximum Fourier frequency).
Figure 7 (top) shows the relationship between
frequency or phase and the frequency spectral-noise
densities, along with the resultant short-term frequency stabilities, for several distinct types of phase
or frequency noise. A typical complex signal source
(such as a PLL) could have a combined short-term
frequency;stability as in Fig. 7 (bottom). But such
noise types generally do not obey simple integerpower curves and, therefore, pose a problem: The
Allan equation dges not have a closed-form solution
for fractional powers, so it cannot be used directly.
Nevertheless, very accurate answers can be obtained
with Simpson's Rule and a programmable calculator.
Although the Allan equation requires integration
over the Fourier frequency range of 0 to fh' the lowfrequency limit of 0 Hz cannot be used in a log-log
Simpson's Rule integration. Fortunately, frequen-

G(W) =

~::

T2=4d2Jwc.

(-JwT2-1)

(log)

1

U~'l

White·phase
nOise region

I
I

t~~j~:r;~;i~~~
I

:

r'Os ____

fr~~~~~y

,..,~T-I.0_--('

Flicker- r
I noise region I frequency I
I
: noise region:
I

"Long-term"

fret~~~~~~rifl
temperature

effects, aging)

(log)

7. The distribution olthe dlfferenllypes offrequency and
phase noise can be expressed as line segments that
represent powers of frequency or tlme(top), and the overall
distribution of a system can be shown by combining
appropriate segments (bottom).

cies below (211'Th)-', where Th is the longest sampling
time, do not contribute appreciably to the value of
the Allan variance. The longest sampling time for
short-term effects is generally 1 s; therefore, for a
measuring-system bandwidth of 1000 Hz, just the
Fourier frequencies between about 0.16 and an fh of
1000 Hz need be considered. (Since the manufacturer
did not supply data below 2 Hz for the reference
oscillator and veo used in Fig. 5; a new oscillator
with data to 0.1 Hz was substituted in Fig. 8, top.)
As shown in Fig. 7 (bottom) and Fig. 8 (top), the
phase-noise curves can be approximated with
straight-line segments. The segments are plotted on
semilog paper with S.1f) measured in dBc on the
vertical axis. Therefore, the segments,
y = ax b ,
can be established from the end points on their phasenoise curves-where S.(f,) and S.(f.) correspond to the
low-frequency (f,) and the high-frequency (f,) end
points, as follows:

Tl=T2Kp K,I w c

6. The phase-output noise in this type-2 second-order PLL
can be optimized by adjusting the damping factor(d) in
relation to the oscillator-noise crossover frequency (fel.

MOTOROLA COMMUNICATIONS DEVICE DATA

b =

and

10 (log f, - log f,)

AN254#4
4-257

Allan variance calculations
Keys

Output
Data/Units

5504
4541 05
5505
1300
1306
2513
·251405
03
5500

'1407

14.00

2523
45.06

2563

55&~

51
1642
2553
2553
5506
5507
1654

AN254 #4
4-258

MOTOROLA COMMUNICATIONS DEVICE DATA

PLL noise and stability
S.(£,I - 10 h log f,1 )

(

10

a = 10

-so
•

-60

With coefficients a and b established for each line
segment, the contributions of each segment to the
overall Allan variance d,' can be calculated with the
approximate Allan equation,

-70

veo

i-aD
e

/

o

~-90

§
~
~ -100

....

";

by. a modified Simpson's Rule program supplied by
Hewlett-Packard (HP-19C/29C Applications' Book,
1977). The Simpson's Rule is incorporated into the

u: -110

.~~ -120
1l

~ -130

~

Ca.lculated short-term stability
Device

Reference
oscillator

Voltage·
controlled
oscillator

PLL

output

'"

.~

Segment I

f,

= 0.1 Hz,

I,

~-150

= 10 Hz

'i!

a = 1.26 x 10-". b = -1.40
T/nI0.001/l0
10.01/10
10.1120
111100
uy'l1.1o x 10-21 11.05 x 10-2514.80 x 10-2511.76 x 10-"
f,

1-160+-------~--------~------~~------.,
0.1

10

1.0

100

1000

Fourier frequency (Hz)

= 0.1 Hz, f, = 10 Hz

a = 5.01 x 10-", b = -3.90
T/n10.001110
10.01/10
J 0.1120
111100
uy'14.49 x 10-2114.39 x 10-2511.34 x 10-2318.10 x 10-23
I,

= 0.1 Hz,

I,

= 100 Hz

a = 4.64 x 10-", b = -1.83
j 0.1/100
Tin I0.00111 0
10.01/20
J 1/1000
uy'12.43 x 10-" 11.46 x 10-23 11.19 x 10-" 18.21 x 10-"
Segment II

DevIce
Reference

'5 -140

I,

= 10 Hz,

I,

= 100 Hz

oscillator
a = 1.26 x 10-", b = -0.40
T/nI0.001l10
10.01/20
I 0.11100
1111000
uy'13.27 x 10-2318.22 x 10'''17.56 x 10-"17.56 x 10- 21
Voltage·
controlled
oscillator

PLL

output

Device
Reference

oscillator

Voltage·
controlled
oscillator

I,

= 10 Hz,

I,

= 100 Hz

/',

a = 6.31 x 10-", b = -2.00
T/nI0.001/l0
I 0.01120
10.1/100
1111000
uy'j1.59 x 10 "11.06 x 10-2311.63 x 10 2511.27 X 10-21
f,

= 100 Hz,

I,

Output

= 1000 Hz

a = 2.51 x 10-", b = -0.70
jO.l/1000
T/nI0.001/20
10.Q11100
11/10,000
uy'll.04 x 10 21 11.00 x 10 2311.01 x 10 "11.01 x 10

21

Segment III

+ _____.,._______.,.________...

0.001

0.01

0.1

1.0

Sampling time, T (s) - -_ _..,__

I, = 100 Hz, I, = 1000 Hz

a = 2.00 x 10-", b = 0.00
I 0.011100
10.1/1000
11110,000
T/nI0.001l20
uy'16.08 x to'" 15.47 x 10-" 15.47 x 10-" 15.47 X 10-"
I, = 100 Hz, f, = 1000 Hz

a = 6.31 x 10-", b = -0.50
I 0/01/100
10.111000
T/nI0.001l20
uy' 18.88 x 10-" 18.27 x 10-" 18.28 x 10

10.13

11/10,000

"I

MOTOROLA COMMUNICATIONS DEVICE DATA

Short-term frequency stability

8. The phase-noise characteristics ofthe reference oscillator
and the veo can be expressed with three straight-line
segments (I,ll, and III); and the PLL output, by two (top).
The short-term stability In terms of the Allan variance can
then be calculated by keying the required coefficients as
determined from the coordinates ofthese line-segment ends
Into the calculator (see Table)and plotting the results
(bottom).

AN254 #4
4-259

complete program for an HP-19C calculator-"Allan
Variance Calculations." With a, b, v, and T established, the only decision remaining is the number
of intervals, n, into which the segments must be
divided. The more intervals chosen, the more accurate the calculation, but the longer the calculation
takes. A good choice for a minimum n value (which
must be an even number) is
n ~ 10 [T(f, - f,)].
The calculation time, then, is 0.056 n + 0.15 min.
To illustrate an application of the Allan variance
calculations, the (a and b) program coefficients for
the straight-line segments making up the VCO,
reference oscillator, and overall output noise were
determined from Fig. 8 (top). The coefficients are
listed in the "Calculated Short-term Stability" table.
Sample times of 1, 10, 100, and 1000 ms and end
frequencies of 0.1, 10, and 1000 Hz were employed.
With these inputs, u/ was determined with the
Allan variance program. The frequency stability,
Uy(T) = v2:u/(T,fh),

was calculated, after summing the individual u/
contributions of each segment. A plot of uy VB
sampling time for the VCO, reference, and output
is shown in Fig. 8 (bottom).D

AN254#4
4-260

Acknowledgments

The author wishes to thank Dr. D. Halford and Dr. Fred·L.
Walls of the National Bureau of Standards, whose constructive
discussions contributed to a more insightful understanding of the
problems involved in working with PLL noise and short-term
frequency stability.
References
1. Przedpelski, A.B., "Phase Lock Loops," R.F. Design,
Sept./Oct., 1979, p. 24.
2. Halford, D., et ai, "Spectra'l Density Analysis: Frequenc~
Domain Specification and Measurement of Signal Stability,'
Proceedings of the 27th A nnaal Symposium on Frequeucy Control, U.S. Army Electronics Command, Fort Monmouth, NJ, June,
1973, p. 421.
3, Barnes, J.A" et ai, "Characterization of Frequency Stability," IEEE Transactions ofIn.truments and Measurements, 1971,
p. 105.
4. Lance, A.L., et aI., "Phase Noise Characteristics of Frequency
Standards," Ninth Annual Precise Time and Time Interval Applica.lions and Planning Meeting, NASA-GSFC, Greenbelt, MD,
1977.
5. Walls, F.L., and Stein, S.R.,"A Frequency-Lock System for
Improved Quartz Crystal Oscillator Performance," IEEE Transuelions qf lnstrumenis nnd Mea.,urements, 1978, p. 249.
6. Stein, S.R., et ai, "A Systems Approach to High-Performance
Oscillators," NBS Technical Note, Boulder, CO.
7. Stein, S.R., and Walls, F.L., "Composite Oscillator Systems
for Meeting User Needs for Time and Frequency," NBS Technical
Note, Boulder, CO.
8. Cutler, L.S., and Searle, C.L., "Some Aspects of the Theory
and Measurement of Frequency Fluctuations in Frequency Standards," Proceedin.qs of the IEEE, February, 1966, p. 136.

MOTOROLA COMMUNICATIONS DEVICE DATA

Remote Control

Application Notes and Technical Articles

AN806A

Operation of the MC14469 ...............................................................

4-263

AN1016

Infrared Sensing and Data Transmission Fundamentals .....•.•......••..................•..

4-270

AN1126

Evaluation systems for Remote Control Devices on an Infrared Link •.................•.......•

4-275

AN1203

Software Method for Decoding Output from MC14497/MC3373 Combination.. . . . .. . . . . . . . . . . . . .

4-285

AR255

Simplified Remote Control Circuits (MC145030) .............................................

4-290

MOTOROLA COMMUNICATIONS DEVICE DATA

4·261

III

4-262

MOTOROLA COMMUNICATIONS DEVICE DATA

MOTOROLA

-

SEMICONDUCTOR
APPLICATION NOTE

AN806A
Application Note

OPERATION OF THE MC14469
Prepared By:
Len Bogle and Bill Cravy
Logic and Special Functions Applications
Austin, Texas

The MC14469 is an addressable asynchronous receiver transmitter that finds applications in control of remote devices, transfer of data to and from remote locations
on a shared wire and as an interface from remote sensors to a central processor.

OPERATION OF THE MCl4469
The MCl4469 is an asynchronous receiver/transmitter
fabricated in metal-gate CMOS technology. The asynchronous data format consists of a serial stream of data bits,
preceded by a start bit and followed by one or more stop bits.
The asynchronous data format is used to eliminate the need
to transmit the system clock along with the data bit stream.
The fact that the MCl4469 is made in CMOS technology
means that it offers the high noise immunity and low power
consumption characteristic of this technology.
The MCl4469 can receive one or two eleven-bit words in a
serial data stream. The first received word contains a sevenbit address and if it matches the programmed address of the
receiver. the transmitter can be enabled to transmit its two
data words. The 7 bits of the received address word must correlate bit by bit with the 7 address pins of the MCI4469. A
second word may optionally be received for data or control
use. This word will contain seven data bits which will be
latched onto the command data outputs if it has a valid command format. With 7 address lines, 27 or 128 separate units
may be interconnected for simplex or full duplex data
transmission. The MCI4469 is capable of operation at data
rates in excess of 30,000 baud controlled by an on chip
oscillator. Applications include transmitting data from
remote A/D converters, temperature sensors, or remote
digital transducers as well as single line control of remote
devices such as motors, lights or security devices.
DEVICE OPERATION
As shown in the block diagram of Figure I, the MCI4469
consists of three different sections: the receiver, the transmitter, and the oscillator. The receiver must receive (at least) a
valid address on its receive data input (pin 19) in order to set
up the necessary internal conditions to allow the transmitter
to transmit its two data words. The address word consists of
MOTOROLA COMMUNICATIONS DEVICE DATA

a start bit, seven address bits, the address identifier, an even
parity bit and a stop bit. The address will be valid only if: a)
the seven address bits match the address that is programmed
on input pins AD through A6, b) if the address identifier is
high, and c) if the state of the parity bit causes the total
number of ones in the address word, including the address
identifier and parity bit, to be even. After reception of a valid
address, the MCI4469 can optionally receive a command
word. Similar to the address word, the command consists of
a start bit, seven data bits, a command identifier, an even
parity bit and a stop bit. The command will be valid if the
command identifier is low and the total number of ones, including the parity bit, is even. The reception of either a valid
address or both valid address and a valid command can be
used to set up the necessary internal conditions for transmission. The format of address and command words is shown in
Figure 2.
Upon receipt of a valid address data stream, the MCI4469
generates a valid address pulse (V AP) which in turn sets the
internal valid address latch (VAL) and the internal send
enable latch (SEL). See Figure 3 for a timing diagram. SEL
remains high for eight data bit times or until the send input
(pin 30) is taken high. If SEL is allowed to time out and a
valid command word is subsequently received, a command
strobe (CS) is generated which sets SEL high again. It again
remains high for eight data bit times after being set.
However, once the valid address latch (VAL) is set high, it
will remain high until SEND goes high and resets it.
In order for the MCl4469 to transmit its two data words,
SEND must receive a rising edge while the valid address latch
and send enable latch are both set high. Therefore, a send input must occur within eight bit times after the generation of
either a valid address pulse or a command strobe, depending
on the system configuration. After eight bit times. SEL will
time out and transmission will be inhibited.

AN806A
4-263

Figure lAo MCl4469 Block Diagram
Transmit

Receive
lAO-AS}

(CO-eel

Address

Command Data

100-107

150-$71

Receive

D'ta
Strobe

Data Rate Clock

OSC1

Receive Data Strobe

OSC2

Receive Data Strobe Enable

1-86

Figure lB. Pin Assignments
Oscl

VOO

Osc2
RESET
AO 4
Al 5
A2 6

SEND going high resets VAL and SEL, and initiates the
transmission of the data defined by input pins 11-18 and the
status word defined by input pins 22-29. The transmitted
words each contain a start bit, eight data bits, an even parity
bit and a stop bit, all in UART compatible format. The
transmitted data has the format shown in Figure 3. Note that
the transmitted data must be inverted before being presented
to the receiving device. This is usually accomplished by the
line driver or transistor used to drive the common transmit
wire.

A3
A

8

A5 9

CS

A6 10
100 11
101 12
102 13
103 14
104 15
10

16

54

106 17
107 18

56

RI 19
VSS 20

AN806A
4-264

TRO

OSCILLATOR OPERATION
The oscillator can be controlled by a ceramic resonator, a
crystal or by an externally generated clock, and will typically
operate at frequencies up to 2 MHz at a VDD of 12 V. The
oscillator frequency is divided by 64 to derive the receive data
strobe and the data rate clock. Thus, the data bit period is 64
times the oscillator period. To allow for maximum phase jitter, the receive data strobe is centered at the middle of each
data bit. The receipt of a start bit initiates the receive data
strobe and synchronizes the strobe to the receive data bit
stream.
Since data is sent asynchronously, the transmit oscillator
and receive oscillator must be the same frequency to ensure
that the receive data strobe occurs at the middle of the bit
period. The maximum permissible variation in oscillator frequency between a transmitting unit and a receiving unit can
be such that over the entire receive data word time the total
error is plus or minus one-half data bit period.

MOTOROLA COMMUNICATIONS DEVICE DATA

Figure lAo Data Format
,0(

Address

------~15T'
MC14469
Pin Number
Pin Designation

.,0(

TIT TTl

J"'"

I:.:J _ 1_.1.. L- .J.. .1...L.J "'L

S

.,0(

Command

.,

T T l T'~rpJTs::-:p:---"'~STr
t.:2.i. .1.' T
...1 ...L .J. .J...J. ~

"'

. " Address
Identifier

4 5 6 7 8 9 10
AO A1 A2A3 A4A5A6

MC6B50
ACIA Pin Number
Pin Designation

f

.-rP~

39 3B 37 36 35 34 33
CO C1 C2 C3 C4 C5 C6

22 21 20 19 18 17 16
DO 01 02 03 04 05 06

Command
Identifier

22 21 20 19 18 17 16
DO 01 02 03 04 05 06

'"'IO(~----Input Oata------i.~'0(~-----5tatus-----i.-t,

T",

r:::;rT T"T

T T

T:"'1~nr;:;r

T , T ' " T"'T "T T '
.J. .J.. .J. P.......
5_P_ _ _ _ __

..L. J.. P ~ 5T L..J. .J. ..L ..J. .J.

_ _ _ _-'1 5T L .J. .l. ..L .J. ..J.. ..L
MC14469
Pin Numbers
Pin Designation

11 12 13 14 15 16 17 18
100101102103104105106107

29 28 27 26 25 24 23 22
50 51 52 53 54 55 56 57

MC6B50
ACIA Pin Number
Pin Designation

22 21 20 19 18 17 16 15
DO 01 02 03 04 05 06 07

22 21 20 19 18 17 16 15
DO 01 02 03 04 05 06 07

1-87

Note: Pin numbers apply to plastic DIP only.

Figure 2B. Example Data Words

I
t::
l!!
f/)

RECEIVE DATA

Address Word
(0100000)

.,0(

0

iii

~

'"

M

...

nsu
'"

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