1993_Motorola_Linear_Interface_ICs_Vol_2 1993 Motorola Linear Interface ICs Vol 2

User Manual: 1993_Motorola_Linear_Interface_ICs_Vol_2
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Volumes
II
I
I

Index and Cross Reference
Amplifiers and Comparators

I

Power Supply Circuits _ _

I

Power/Motor Control Circuits _ _

II

Voltage References

II

Data Conversion

II

Interface Circuits

II

Communication Circuits

II

Consumer Electronic Circuits

II

Automotive Electronic Circuits

II

Other Linear Circuits

II

I

Surface Mount Technology

II

I

Packaging Information

II

Quality and Reliability Assurance

II

Applications and Product Literature

What's Different
New Additions
CHAPTER 2
MC33076
MC33201/2/4
MC33304
MC33102
ADDENDUM
CHAPTER 3
LP2950/51
MC33267
MC33269
MC34023
MC34025
MC34065-H,-L
MC34067
MC34152
MC34161
MC34165
MC34167
MC34261
MC34268
MC34360
MC34361
UC3842B,43B
UC3844B,45B
HB206 MANUAL
CHAPTER 4
UAA2016

CHAPTER 5
TL431,A,B
CHAPTER 6
MC10322
MC10324
CHAPTER 7
MC14C88B
MC14C89B,AB
MC34055
MC34142
MC75172B/174B
CHAPTERS
MC13135/136
MC13155
MC13156
MC13173
MC13175
MC3371/72
• MC33110
• MC33121
• MC33218
ADDENDUM

*See Telecommunications Device Datal (OL 136)

CHAPTER 9
MC1388
MC13007
MC13017
MC13025
MC13077
MC44001
MC44011
MC44144
MC44145
MC44301
MC44302
MC44615A
MC44802A
MC44807/817B
CHAPTER 10
MC3392
MC33091
MC33092
MC33192
MC33293
MC33295
MC33298
MCCF33093
MCCF33094
MCCF33096
MCCF79076

Deletions
LF355,B
LM 108,A1208,A1308,A
LM 109/209/309
LM148
LM193,A
MC1382
MC1383
MC1384
MC1414/1514
MC1439/1539
MC1454G/1554G
MC1456/1556
MC1458S/1558S
MC1466L
MC1590G

MC1709,A,C
MC1741S,SC
MC3357
MC3397T
MC3440Al41 A
MC3446A
MC10318P
MC10320/20-1
MC13010
MC13023
MC13041
MC33034
MC33153/34153
MC34013A
MC34063/33063/35063

MC35181/182/184
MC44802
MC75125/127
MC75128/129
MC8T28
MC8T95
MC8T96
NE5921SE592
OP-27
SG1525A127A;2525A127 A
TDA1524A
TDA3330
TDA4601
TL061
ULN2074B

New Product Literature (Referenced)
AN1046
AN1077

AN1122
AN1203

AN1510

M01'OROLA

LINEAR/INTERFACE
ICs DEVICE DATA
This publication presents technical information for the broad line of Linear and Interface Integrated Circuit
products. Complete device specifications are provided in the form of Data Sheets which are categorized by product
type into ten chapters for easy reference. Selector Guides by product family are provided in the beginning of each
Chapter to enable quick comparisons of performance characteristics. A Cross Reference chapter lists Motorola
nearest replacement and functional equivalent part numbers for other industry products.
A chapter is provided to illustrate Package Outline and includes information on Surface Mount Devices (SMD).
Additionally, chapters are provided with information on Quality program concepts, high-reliability processing,
and abstracts of available Technical Literature.
The information in this book has been carefully checked and is believed to be accurate; however, no responsibility
is assumed for inaccuracies.
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no
warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does
Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims
any and all liability, including without limitation consequential or incidental damages. "Typical" parameters can and
do vary in different applications. All operating parkmeters, including "Typicals" must be validated for each customer
application by customer's technical experts. MotOrola does not convey any license under its patent rights nor the
rights of others. Motorola products are not designed, intended, or authorized for use as components in systems
intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other
application in which the failure of the Motorola product could create a situation where personal injury or death may
occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer
shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless
against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly,
any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges
that Motorola was negligent regarding the design or manufacture of the part. Motorola and ® are registered
trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.

Series H
First Printing
© MOTOROLA INC., 1993
Previous Edition © 1990
"All Rights Reserved"
Printed in U.S.A.

New Product Literature
Chapter 2 has an addendum providing applications information on operational
amplifiers.
The applications information which formerly appeared in the Motorola
LinearlSwitchmode Voltage Regulator Handbook (HB20S) is now included as an
addendum to Chapter 3.
.
An addendum covering RF applications information has been added to Chapter 8.
The Surface Mount Technology in Chapter 12 has been expanded to include
Multiple Package Quantity (MPQ) information for surface mount and TO-92
packages shipped in Tape and Reel or Ammo Pack Styles. Mechanical Polarization
drawings for the TO-92 (TO-22SAA) in tape and reel plus the ammo pack styles
have also been added to Chapter 12.

Data Classification
Product Preview
This heading on a data sheet indicates that the device is in the formative stages or
in design (under development). The disclaimer at the bottom of the first page reads:
"This document contains information on a product under development. Motorola
reserves the right to change or discontinue this product without notice."

Advance 'nformation
This heading on a data sheet indicates that the device is in sampling,
pre-production, or first production stages. The disclaimer at the bottom of the first
page reads: "This document contains information on a new product. Specifications
and information herein are subject to change without notice."

Fully Released
A fully released data sheet contains neither a classification heading nor a disclaimer
at the bottom of the first page. This document contains information on a product in
full production. Guaranteed limits will not be changed without written notice to your
local Motorola Semiconductor Sales Office.

C-QUAM®, Designer's, MDTL, MECL, MECL 10,000, MONOMAX, MOSAIC®, MRTL,
MTTL, MOSFET, SENSEFET, SLEEP-MODE, SMARTMOS, Switch mode, and
ZIP-R-TRIM® are trademarks of Motorola Inc.

Index and Cross Reference

In Brief . ..
Motorola linear and interface integrated circuits cover a
much broader range of products than the traditional op
amps, regulators and consumer-image associated with
linear suppliers. Linear circuit technology currently
influences the design and architecture of equipment for all
major markets. As with other integrated circuit technologies,
linear circuit design techniques and processes have been
continually refined and updated to meet the needs of these
diversified markets.
Operational amplifiers have utilized JFET inputs for
improved performance, plus innovative design and trimming
concepts have evolved for improved high performance and
precision characteristics. In linear power ICs, basic voltage
regulators have been refined to include higher current levels
and more precise three-terminal fixed and adjustable
voltages. The power area continues to expand intoswitching
regulators, power supply control and supervisory circuits,
and motor controllers.
Linear designs also offer a wide array of line drivers,
receivers and transceivers for many of the EIA, European,
IEEE and IBM interface standards. Peripheral drivers for a
variety of devices are also offered. In addition to these key
interface functions, a variety of magnetic and semiconductor
memory read, write, sense and RAM control circuits are also
available.
In data conversion, the original A-O and O-A converters
have been augmented with high performance video speed
and multiplying designs. Linear circuit technology has also
provided precision low voltage references for use in data
conversion and other low temperature drift applications.
A host of special purpose linear devices have also been
developed. These circuits find applications in telecommications, radio, television, automotive, RF communications,
and data transmission. These products have reduced the
cost of RF communications, and have provided capabilities
in telecommunications which make the telephone line
convenient for both voice and data communications. Linear
developments have also reduced the many discrete
components formerly required for consumer functions to a
few IC packages, and have made significant contributions
to the rapidly growing market for electronics in automotive
applications.
The table of contents provides a perspective of the many
markets served by linearlinterface ICs and of Motorola's
involvement in .these areas.

Alphanumeric Index
~~~~~~~~~

AM26lS32
CA3054
CA3059
CA3079
CA3146
DAC-08

Dual Differential/Quad Single-Ended Line Drivers
Quad Line Driver with NAND Enabled
Three-State Outputs
Quad EIA-422/423 Line Receiver
Dual Differential Amplifier
Zero Voltage Swhches
Zero Voltage Switches
I-Differentially Connected and 3-lsolated
Transistor Arrays
High Speed 8-Bh MuRiplying
D-to-A Converter

7-25
9-27
4-10
4-10
9-28

6-6

LF347

LM124
LM139,A
lM158
LM201A
lM211

LM323,A
lM324,A
LM337
lM337M

Quad Single Supply Operational Amplifier
Quad Three-State Bus Transceiver
Hex Three-State Buffer/Inverter
Hex Three-State Buffer/Inverter
Low-Level Video Detector

High Penormance Voltage Comparator
Quad, Low Power Operational Ampltliers
Quad, Single-Supply Comparators
Dual Low Power Operational Amplifiers
Operational Amplifier
High Performance Voltage Comparator
Quad Power Operational Amplifiers
Quad, Single-Supply Comparators
Quad MC1741
I

3-l9rminal
Vonage Regulator
Positive VoRage Regulators
Quad, Low Power Operational Amplifiers
3-Terminal Adjustable Output Negative
Voltage Regulator
3-Terminal Adjustable Output Negative
Voltage Regulator
Quad, Single-Supply Comparators
3-Terminal PosRlve Voltage RegUlator
Quad MC1741 Operational Amplifier

2-56
2-60
2-40
2-41

2-44
7-28
7-33
7-33
9-30
9-36

Peripheral Driver Arrays
High Voltage, Internally Compensated
Operational Amplifiers
Wideband Amplifiers
Timing Circuit
Dual Operational Amplifiers
Dual ± 15 von Tracking Regulator
Dual Peripheral Poshive NAND Driver
Quad MDTl Line Driver

2-95
11-5
2-101
3-99
7-41
7-44

Dual Operational Amplifier
Dual ± 15 Volt Regulator
Four-Quadrant Multiplier
Four-Quadrant Multiplier
Balanced Modulator/Demodulator
Voltage Regulators
Differential Video Wideband Amplifiers
High Penormance Operational Amplifiers
Dual MC1741 Operational Amplifiers

11-12
11-26
8-32
3-105
2-114
2-122
2-127

2-50
3-42
3-81

2-56

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

1-2

Alphanumeric Index (continued)
Device
Number

Function

Device
Number

Page

MCI748C
MC1776,C
MC26S10
MC2B30
MC2831A
MC2833
MC3301
MC3302
MC3303
MC3325
MC3334
MC3335
MC3340
MC3346
MC3356
MC3357
MC3358
MC3359
MC3361B
MC3362
MC3363
MC3367
MC3371
MC3372
MC3373
MC3391
MC3392
MC339g
MC3401
MC3403
MC3405
MC3417

High Pertormance Operational Amplifiers
2·131
Micropower Programmable Operational Amplifiers
2·135
7-66
Quad Open·Coliector Bus Transceiver
Voice Activaled Switch
8-42
Low Power FM Transmitter Syslem
8-46
Low Power FM Transmitter System
8-49
2-144
Quad Operational Amplifier
Quad, Single-Supply Comparator
2-56
Quad Low Power Operational Amplifiers
2-154
Automotive Voltage Regulator
10-8
High Energy IgnHion CircuH
10-11
Low Power Narrowband FM Receiver
8-55
Electronic Attenuator
9-100
General-Purpose Transistor Array
9-103
Wideband FSK Receiver
8-659
Low Power FM IF
8-65
Dual, Low Power Operational Amplifier
2-175
Low Power Narrowband FM IF
8-69
Low Voltage Narrowband FM IF
8·75
Low Power Dual Conversion FM Receiver
8-82
Low Power Dual Conversion FM Receiver
8-89
Low Voltage Single Conversion FM Receiver
8-97
Low Power FM IF
8-106
Low Power FM IF
8-106
Remote Control Amplifier/Detector
9-106
Low Side Protected SwHch
10-15
Low Side Protected SwHch
10-24
Automotive High Side Driver SwHch
.10-33.
l'i144
Quad Operational Amplifier
Quad Low Power Operational Amplifiers .
2·154
Dual Operational Amplifier plus Dual Comparator
2-159
Continuously-Variable-Slope Delta
!. .'
.'
Modulator/Demodulator
MC3418
Continuously-Variable-Slope Delta
Modulator/Dernodulator
>';'::.. "
Telephone Line-Feed CircuH
:' *
MC3419-1L
, :~ . 3·111
OVervoitage Crowbar Sensing CircuH
MC3423
MC3425
Power Supply Supervisory/OVer, Under·
3-117
voltage Protection Circuit
MC3430
High Speed Quad Comparator
2-167
2-167 .
MC3431
High Speed Quad Comparator
MC3432
High Speed Quad Comparator
2·167
MC3433
High Speed Quad Comparator
2-167
Hex Unified Bus Receiver
7-69
MC3437
MC3447
Bidirectionallnstrumenlalion Bus Transceiver
7·72
MC3448A
Quad Three-State Bus Transceiver
7-78
MC3450
Quad Une Receiver
7·63
MC3452
Quad Une Receiver
7-83
MC3453
Quad Une Driver
7-90
MC3456
Dual Timing Circuit
11-41
2-175
MC3458
Dual, Low Power Ope~nal Amplifier
MC3467 .
7-94
Triple Preamplifier
MC:i469:i ...,:, floppy. Disk W,ite. Controller
1-99
7-109
MC94?O,: ......... fiop!,}: Disk. ~~adAmplifier System
MC3470A.
Floppy .DiS!< Read Amplifier System
'. 1,109
MC3471 :,
floppy Disk Wrile Controller/Head Driver
7.-123
2:181
Low'Cost Programrn8ble OperatiOnal Amplifier
MC3476 : ,..
MCa479 .,
Steppe! MotOr Driver .
.
4-15
Mc3481"
Quad, Si~gle:Ended Line Driver' ."
:7~134

.

..

.

MC3484S2
MC3484S4
MC3485
MC3486
MC3487
MC3488A
MC3503
MC3505
MC3517
MC3518
MC3523
MC3558
MC4558,AC,C
MC4741,C
MC6875,A
MC7800
Series
MC78LOOA
Series
MC78MOO
Series
MC7900
MC79LOO,A
Series
MC79MOO
Series
MC10319
MC10321
MC10322
MC10324
MCI3001XP
MCI3007XP
MC13017
MC13020
MC13022
MC13024
MC13025
MC78TOO
Series
MC13055
MCI3060
MC13077 .
MC13t04 ' ''''i
MC13135
MCI3136:
MC13155 ,.
MC1317.3
MC13175
.MC33023 i

Function
Integrated Solenoid Driver
Integrated Solenoid Driver
Quad, Single-Ended Une Driver
Quad EIA-422/3 Une Receiver
Quad EIA-422 Une Driver With Three-State
Output
Dual EIA-423/EIA 232D Driver
Quad low Poer Operational Amplifiers
Dual Operational Amplifier piUS Dual
Comparator. ' .
DeHa
DeHa
r
Overvoltage C!ll~ Sensing Circuit
Dual, Low Power Operational Amplifier
Dual Wide Bandwidth Operational Amplifiers
Quad MC1741 Operational Amplifiers
MC6800 Clock Generator
Three-Terminal Positive VoHage Regulators
Three-Terminal Low Current Positive
Voltage Regulators
Three-Terminal Medium Current Positive
Voltage Regulators

MC33033'" .:
MC33035
MC33039

3-11
2·175
2-185
2-189
7-150
3-125
3-137
3-144

3-175
Hig~ Speed8-BH ND Flash Converter
High5Pe.d7-BH ND FI~hConverter
8Bil Vidiio DAC wHh
.
8'B~V~e~.i),l,C wHh
Moriamax BlaCk·and-'
Monomax Black-andNTSC/PAL Chroma 10 Color TB and
Timebase Processor
C-QUAM® AM Stereo Decoder
Advanced Medium Voltage AM Stereo Decoder
Low Voltage Motorola C-QUAM®
AM Slereo Receiver
Electronically Tuned Radio Front End
Three-Ampere Positive VoHage Regulators

Wideband FSK Receiver
Min~Watt Audio Output
·'~variced .~LJNTSC Encoder·
·LNNMixerNCQ

1

:.
:M9torCOn!roU~(/nrilter
Brushless DC Motor ControUer
Brushless DC Motor ControUer
Closed-Loop Brushless Motor Adapter

·See Telecommunication Device Data (DL (36)

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

1-3

7-146
2-154
2-159

3-161
3-170

!'

MC33025 '
MC3303il'

Page
10-36
10-36
7-134
7-139
7·142

6-27
6-45
6-63
6-68
9-110
9:110'
9-119
9-121
9·126
9-130
9-134
3-152
8-123
9-137
9·141
8-130
8-131
8-131
.. 8-143
8-159
8-160
3-187
3·203
4-23
4-36
4-57
4-79

.. Page

MC33063A
MC33064
MC33065-H, l
MC33066
MC33067
MC3307t
MC33072
MC33074
MC33076

Undervoltage Sensing Circu"
High Performance Dual Channel Current
Mode Controller
High Performance Resonant Mode ControUer
High Performance Resonant Mode Controller
High Performance Single-Supply
Operational Amplifier
Dual, High Performance Single-Supply
Operational Amplifier
Quad, High Penormance Single-Supply
Operational Amplifier
Dual High Output Curren~ Low Power,
Operational Amplifier

JFET Operational Amplifier
Quad Low Side Driver
Quad Low Side Driver
Octal OutpUt Driver. .. .•
Rai~to-Rail, Sleepmode Two-State .
Operational Amplifier .. ..

3-243
3-252
3-257
3-270
3-278
2-284

.!
t-1C34oo2 !ii . ,
MC34oo4.,
MC34010,+.

2-284

~~~l~~·

2-284

Series
MC34013A
MC34014

2-194

MC34017
MC34018
MC34023
MC34025
MC34050
MC34051

MC33161
MC33163
MC33164
MC33166
MC33167
MC33171
MC33172

Microprocessor Voltage Regulator and
Supervisory Cireun
Universal Voltage Monnor
Power SwHching Regulator
Micropower Undervoltage Sensing Ciroon
Power SwHching Regulator
Power Switching Regulator
Low Power, Single Supply Operational Amplifier
Low Power, Single Supply Operational Amplifier
Low Power,

3-329
3-343
3-342
3-362
3-375
2-234

M(;34071
MC34072
MC34074
MC34080
MC34085

MC33272
MC33274
MC33282

Lowe Dropout Regulator
Low Dropout Postive Voltage Regulator Series
Low Power, Single Supply Operational
Amplifiers
Low Power, Single Supply Operational
Amplifiers
JFET

JFET-lnpirtOperationai Amplifier
JFET-Input Operational Arl1p1~er.!
JFET-Inpirt Operational Anlplifie!
Bectronic Telaphone Ciroon
Bectronic Telaphone Ciroon
Telephone Tone Ringer
Speech Network and Tone Dialer
Telephone Speech Network with Dialer
Intertace
Telephone Tone Ringer
Voice Switched Speakerphone Cireuit
High Speed Single-Ended PWM Controller
High Speed Double-Ended PWM Controller
Dual EIA-422/423 Transceiver
Dual EIA-422/423 Transceiver
ISO 88-2-3(IEEE 802.3]10Base-TTransceiver
.SwltphmOde Pulse Width MOduliliion
Control Clroolt,,· .
, . !.
Precelsion Switchmode Pulse Width
i MOdulation Control Clroon· .
DC-to-DC Convertor Controle!rcun
UndelVOltage Sensing eireun !.
.,
'High Penormance Dual Channel Current
Mode Controller!
..! ,.
. .
!H~llpertonnanceReSon~11t !ModeCcfulroDel.
~igh Perto~nce Resorarit Mode cOntroller
High Performance Single-Supply
Operational AmpHtier
Dual, High Performance Single-Supply
Operational Amprrfier
Quad, High Penormance Single-Supply
Operational Amprlfier
High Speed Decompensated (AVCl" 2)
JFET Input Operational Amplifier
Quad, High Speed Decompensated
(AVCl" 2) JFET Input Operational Amplifier
Telephone Speech Network with Diater Intenace
Continuously Variable Slope Delta
Modulator/Demodulator

2-259
2-268

'See Telecommunication Device Data (DL136)

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
1-4

2-268

3-187
3-203
7-161
7-161

s-tn
3-219 .

2-284
2-284
2-284
2-300
2-300

Alphanumeric Index (continued)
DevIce
Number
MC34181
MC34182
MC34184
MC34261
MC34262
MC34268
MC34360
MC34361
MC35060A
MC35063A
MC35071
MC35072
MC35074
MC35080
MC35085
MC35171
MC35172
MC35174
MC44oo1
MC44011
MC44144
MC44145
MC44301
MC44302
MC44602
MC44615A
MC44802A
MC44807/17
MC44610
MC75107
MC75108
MC75S11 0
MC75172B
MC75174B
MCC3334
MCCF3334
MCCF33093
MCCF33094
MCCF33095
MCCF33096
MCCF79076
SAAl042,A

S<33525A
SG3526
SG3527A
,SN75173

Function

Low Power JFET Inpul Operational Amplifier
Dual, Low Power JFET Input Operational

2-311
2-311

Amplifier
Quad, low Power JFET Input Operational
Amplifier
Power Factor Conlmllers
Power Factor Conlmllers
SCSI-2 Three-Tenninal Voltage Regulalor
High Voltage Swi1ching Integrated Conteroller
High Voltage Switching Integrated Conteroller
Swi1chmode Pulse Width Modulation
Conkol Clrcutt
DC-to-DC Converter Control Circuit
High Performance Single-Supply
Operational Amplifier
Dual, High Perfonnance Single-Supply
Operational Amplifier
Quad, High Performance Single-Supply
Operational Amplifier
High Speed Decompensated
(AVCL" 2) JFET Input Operational Amplifier
Quad, High Speed Decompensated
(AVCL" 2) JFET Input Operational Amplifier
Low Power, Single Supply Operational Amplifier
Low Power, Single Supply Operational Amplifier
Low Power, Single Supply Operational Amplifier
Chroma 4 Multistandard Video Processor
Buss Controlled Multistandard Video Processor
Subcarrier Reference
Sync Separator/Pixel Clock Generator
High Perfonnance Color TV IF
Advanced Multistandard TV Video/Sound IF
High Perfo~ce CUlrent Mode Controller
Convergence Ymelorm Generator IC for
Projection TV, ';:
PLL lUnlng'CiiCtiit witt, 1.3 GHz Prescalel '
PLL Tuning Circuit with 3:Wir~ Bus,
PLL Tuning Clicunwith1.3 GHz, Prescaler
andD/ASection' , , ' ,
Dual Une Receiver
Dual Une Receiver
DuaiUneDriver
Quad EIA-485 Une Drivers wHh Three-S1ate
Outputs
Quad EIA-485 Une Drivers wtth Three-Sfate
Outputs
High Energy Ignition Circutt
High Energy Ignition Circutt
Ignition Conkol Chip
Ignition Conlml Chip
Integrat Mernator Regulator
Darlington Drive Flip-Chip
Ignition Conlml Chip
Stepper Motor Driver
Pulse Width Modulator Control Circuit
Pulse
Modulator COntrol Clrcutt
Putse Width Modulator Control CircUH
Qued EIA-485 Un. Receivers

W.dth

Device
Number

Page

SN75174
SN75175
TCA0372
TOO6oo

2-311
3-388
3-399
3-414
3-417
3-418
3-231

TCF5600
TCF6000
TDA1085A
TDA1085C
TDAII85A
TDA3190
TDA3301B
TL062

3-243
2-284
2-284

TL064

2-284
2-300

Function
Quad EIA-485 Une Driver wHh Three-State
Output
Quad EIA-485 Une Receivers
Dual Power Operational Amplifier
Universal Microprocessor Power Supply/
Controller
Universal Microprocessor Power Supply/
Controller
Peripheral Clamping lVIay
Universal Motor Speed Controller
Universal Motor Speed Controller
Triac Phase Angle Controller
TV Sound System
TV Color Processor
Dual, Low
Amplifier
Quad, Low
Ampflfier

,"

10-11
10-11
10-62
10-63
10-&4
10-73
10-99
4-84
3-435
3441

<,

,i.'"

3-435
~i

2-337 '
2-337
2-337
5-17
Switchmode Pulse Width Modulation
Control CircuH
Precision Switchmode Pulse Width
Modulation Control Circutt
Three-Terminal Posnive Voltage Regulator
Zero Voltage Controller
Autcmotlve Direction Indicator
Zero Voltage Controller
High Perfonnance Current Mode Conkoller
High Performance Current Mode Controller
High Perfonnance Current Mode Controller
High

Quad 1.5 A Darlington Swnch
Octal Peripheral Driver lVIay
Octal Peripheral Driver lVIay
Octal Peripheral Driver Array
Octal Peripheral Driver lVIay
Universal Switching Regulator Subsystem

7-193:

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
1-5

2-324

TL072

TL780
UAAl016B
UAA1041
UAA2016
UC2842A
UC2843A
UC2844
UC2844B
UC2845
UC2845B
UC3842A
UC3842B
UC3843A
UC3843B
UC3844
UC3844B
UC3845'
UC3845B
ULN2068B
ULN2801
ULN2802
ULN2803
ULN2804
1lA78S40

7-182

10-100
4-89
4-96
4-106
9-297
9-300
2-324

2-331

TL594

7-172
7-172
7-1n
7-182

3-449

2-331
'i;:'<"
, 2-331

TL081
TL082
TL084
TL431,A,B
Series
TL494

9-275
9-282
9-289

7-193
2-320
3-449

TL071

2-300
2-234
2-234
2-234
9-166
9-182
9-230
9-234
9-237
9-255
3-419
9-258

Page
7-193

3-460

3-471
3-482
4-115
10-104
4-121
3-488
3-488
3-515
3-528
3-515
3-528
3-488
3-501
3-488
3-501
3-515
4-528
3-515
3-528
7-198
7-202
7-202
7-202
7-202
3-508

Cross Reference
The following table represents a cross reference guide for all of Analog devices which are manufactured by Motorola. Where
the Motorola part number differs from the industry part number, the Motorola device is a "form, fit and function" replacement for
the industry part number. However, some differences in characteristics andlor specifications may exist.
Indust~

Part Hum er
55110DM
75107ADC
75107APC
75107BDC
75107BPC
75108ADC
75108APC
75108BDC
75108BPC
75110DC
75110PC
75207DC
75207PC
75208DC
75208PC
8216
9614DC
9614DM
9615DC
9616CDC
9616DM
90616EDC
9617DC
9620DC
9620DM
9621DC
9627DC
9627DM
9636AT
9637T
9638T
9640DC
9640PC
9665DC
9665PC
9666DC
9666PC
9667DC
9667PC
9668DC
9668PC
AD1403AN
AD1508-8D
AD530
AD531
AD532L
AD580J
AD580K
AD580M
AD580S
AD580T
AD589J
AD589K
AD589L
AD589M
ADDAC-08CQ
ADDAC-08ED

Motorola
Nearest
Replacement

Motoria
Similar
Replacement

Indust~

Part Num er

MC75S110L

ADDAC-08HD
AM107
AM201AD
AM201D
AM26LS30D
AM26LS30L
AM26ALS30P
AM26LS31CJ
AM26LS31CN
AM26LS31DS
AM26LS31P
AM26LS32ACJ
AM26LS32ACN
AM26LS32PC
AM26LS32P
AM26LS33DC
AM26LS33PC
AM26S10DC
AM301AD
AM301D
AM311D
AM723DC
AM723DM
AM723P
AM741DC
AM741DM
AM747DC
AM747DM
AN5150
AN5151
CA081AE
CA081AS
CA081CS
CA081E
CA081S
CA082AE
CA082AS
CA082CS
CA082E
CA082S
CA084AE
CA084E
CA084S
CA1391E
CA139AG
CA139G
CA1458S
CA1558S
CA239AE
CA239AG
CA239E
CA239G
CA3026
CA3045F
CA3045
CA3046
CA3048

MC75107L
MC75107P
MC75107L
MC75107P
MC75108L
MC75108P
MC75108L
MC75108P
MC75S110L
MC75S110P
MC75107L
MC75108P
MC75108L
MC75108P
MC8T26AL
MC75S110L
MC75S110L
MC75108L
MC1488L
MC1488L
MC1488L
MC1489AL
MC75S110L
MC75S110L
MC75108L
MC1489AL
MC1489AL
MC3488AP
MC3486P
MC3487P
MC26S10L
MC26S10P
MC1411L
MC1411P
MC1412L
MC1412P
MC1413L
MC1413P
MC1416L
MC1416P
MC1403AU
MC1508L8
MC1595L
MC1595L
MC1595L
MC1403U
MC1403P1
MC1403AP1
MC1503U
MC1503AU
LM385Z-1.2
LM385Z-1.2
LM385Z-1.2
LM385BZ-1.2
DAC-08CQ
DAC-08EQ

Motorola
Nearest
Replacement
DAC-08HQ
LM111J

LM201AN
LM201AN
AM26LS30D
AM26LS30L
AM26LS30P
AM26LS31PC
AM26LS31PC
AM26LS31DS
AM26LS31P
AM26LS32D
AM26LS32APC
AM26LS32PC
AM26LS32PC
MC3486L
MC3486P
MC26S10L
LM301AJ
LM301AJ
LM311J-8
MC1723CL
MC1723L
MC1723CP
MC1741CU
MC1741U
MC1747CL
MC1747L
MC34129P
MC13001P
TL081ACP
TL081 ACJG
TL081CJG
TL081CP
TL081MJG
TL082ACP
TL082ACJG
TL082CJG
TL082CP
TL082MJG
TL084ACN
TL084CN
TL084MJ
MC1391P
LM139AJ
LM139J
MC1458CP1
MC1558U
LM239AN
LM239AJ
LM239N
LM239J
CA3054
MC3346P
MC3346P
MC3346P

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

1-6

Motoria
Similar
Replacement

MC3301P

Cross Reference (continued)
Indu.~

PartNum

r

CA3052
CA3054
CA305B
CA3059
CA3079
CA30B5AF
CA30B6F
CA308AS
CA30910
CA3136A
CA3146D
CA3146
CA3201E
CA3210E
CA3217E
CA3302E
CA339AE
CA339AG
CA339E
CA339G
CA3401E
CA723CE
CA723E
CA741CS
CA741S
CA747CE
CA747CF
CA747E
CA747F
CA74BCS
CS2B42AD
CS2843AD
CS2B44D
CS2B45D
CS3471
CS3842AD
CS3B43AD
CS3844D
CS3B45D
DB216
DB226
DAC-OBCD
DAC-08CN
DAC-OBCP
DACOBCO
DAC-OBED
DAC-OBEN
DAC-OBEP
DAC-OBEO
DAC-OBHN
DAC-OBHP
DAC-OBHO
DACOBOOLCJ
DACOBOOLCN
DAC0801LCJ
DACOB01LCN
DACOB02LCJ
DACOB02LCN
DACOBOBLCJ
DACOBOBLCN
DACOBOBLD

Motorola
Nearest
Replacement

Motoria
Similar
Replacement

Indu:te
PartNum r

MC3301P

DM7B22J
DM7B37J
DMBB22J
DMBB22N
DMB837N
DSl48BJ
DSl48BN
DSl489AJ
DSl489AN
DSl489J
DS14B9N
DS26LS31N
OS26LS32N
OS26S10CJ
OS26S10CN
DS3486J
0S34B6N
OS3487J
OS3487N
DS3612H
OS3612N
DS3632H
OS3632J
OS3632N
DS3650J
0S3650N
DS3651J
DS3651N
0S3652.1
DS3652N
0S3653J
DS3653N
0S55107W
DS5511OJ
DS75107J
OS75107N
DS7510BJ
DS75108N
DS7511OJ
DS7511ON
DS75207J
·OS75207N
OS7520BJ
OS7520BN
DS7837J
OS7837W
.DSB834J
0S8834N
OS8B35J
Dsaa35N
DSB837J
OSB837N
DS8922A
DS8923A
DS9636AcN
ICL741CLNPA
ICL741CLNTY.
IC18001CTZ
IC18001MTZ
ICL8008CPA
IC1880BCTY

CA3054
CA3059
CA3059
CA3079
MC1723L
MC3346P
LM30BN
MC1594L
MC3346P
CA3146D
MC3346P
TDA3301B
MC13001P
TDA3301B
MC3302N
LM339AN
LM339AJ
LM339N
LM339J
MC3401P
MC1723CP
MC1723L
MC1741CP1
MC1741U
MC1747CL
MC1747CL
MC1747L
MC1747L
MC1748CP1
UC2B42BD1
UC2843BD1
UC2844BD1
UC2845BD1
MC3471P
UC3842BD1
UC3B43DB1
UC3844BD1
UC3845BD1
MCBT26AL
MCBT26L
DAC-OBCD
DAC-oBCP
DAC-OBCP
DAC-08CO
DAC-08ED
DAC-OBEP
DAC-OBEP
DAC-OBEQ
DAC-OBHP
DAC-OBHP
DAC-OBHO
DAC-OBEO
DAe-OBEP
DAC-OBCO
DAC-OBCP
DAC-OBHO
DAC-08HP
MC140B18
MC140BP8
MCl50818

Motorola
Naarest
Replacement

MC14B9AL
MC3437L
MC14B9AL
MCl489AP
MC3437P
MCl488L
MCl48BP
MC14B9AL
MCl489AP
MCl489L
MC14B9P
AM26LS31P
AM26LS32P
MC26S10L
MC26S10P
MC34B6L
MC3486P
MC3487L
MC34B7P
MC1472U
MC1472P1
MC1472U
MC1472U
MC1472P1
MC3450L
MC3450P
MC3430L
MC3430P
MC3452L
MC3452P
MC3432L
MC3432P
MC75107L
MC75S110L
MC75107L
MC75107P
MC7510BL
MC7510BP
MC75S110L
MC758110P
MC75107L
MC75107P
MC7510BL
MC74108P
MC3437L
MC3437L
MCBT26AL
MC8T26AP
MCBT26AL
MCBT26AP
MC3437L
MC3437P
MC34051P
MC34050P
MC3488AP1

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

1-7

Motoria
Similar
Replacement

MC1741CP1
MC1741CP1
LM111J
LM111J
LM301AN
LM301AN·

Cross Reference
p~~d~~~1;er
ICL8013A
ICL80138
ICL8013C
ICL8017CTW
ICL8017MTW
ICL8069CCZR
ICL8069DCZR
IP33063N
IP34060AN
IP34063N
IP35063J
IP3525AJ
IP3525AN
IP3526J
IP3526N
IP3527AJ
IP3527AN
IP494ACJ
IP494ACN
IP494AJ
ITI371 0
ITI652
ITI654
ITI656
L144AP
L201
L202
L203
L387
L583
LF347BN
LF347N
LF351AN
LF351BN
LF351N
LF352D
LF353AN
LF353BN
LF353D
LF353N
LF3568J
LF356BN
LF356JG
LF356J
LF356N
LF356P
LF357BJ
LD357BN
LD357JG
LF357J
LF357N
LF357P
LF411CD
LF411CH
LF412CD
LF412CH
LF441CD
LF441CN
LF442CD
LF442CN

(continued)

Motorola
Nearest
Replacement

Motoria
Similar
Replacement

Indust~
Part Num er

MC1594L
MC1594L
MC1594L
LM301AN
LM301AN
LM3848Z-1.2
LM3858Z-1 ,2

LF444CD
LF444CN
LF351AN
LM101AJ-14
LM101AJG
LM101AJ
LM101D
LM101J-14
LM1035
LM107L
LM111J-8
LM111JG
LM11CLN
LM11CN
LM124AD
LM124AJ
LM124J
LM124N
LM139AJ
LM139J
LM139N
LM1408JB
LM140BNB
LM14B9AN
LM14B9J
LM14B9N
LM1496J
LM1496N
LM149J
LM15BJG
LM15BJ
LM155BJ
LM1596J
LM163J
LM1B49A
LM1BB9
LM1900D
LM19B1
LM201AD
LM201AJ-14
LM201AJG
LM201AJ
LM201AN
LM201AP
LM201J-14
LM201J
LM211D
LM211J-B
LM211JG
LM211M
LM212H
LM224AF
LM224AJ
LM224D
LM224J
LM224M
LM224N
LM239AJ
LM239AN
LM239D

MC33063AP1
MC34060AP
MC34063AP1
MC35063AU
SG3525AJ
SG3525AN
SG3526J
SG3526N
SG3527AJ
SG3527AN
TL5941N
TL594CN
TL594MJ
MC1391P
MC1411P
MC1412P
MC1413P
LM324N
MC1411P
MC1412P
MC1413P
MC33267
MC3484S2
LF347BN
LF347N
MC34001AP
MC340018P
LF351N
LF355J
MC34002AP
MC34002BP
LF353D
LF353N
LF3568J
LF356J
LF356J
LF356J
LF356J
LF356J
LF3578J
LF3578J
LF357J
LF357J
LF357J
LF357J
LF411CD
MC34001AG
LF411CD
MC34002AG
LF441CD
LF441CN
LF442CD
LF442CN

Motorola
Nearest
Replacement
LF444CD
LF444CN

MC34001AP
LM101AJ
LM101AJ
LM101AJ
LM101AJ
LM101AJ
TCA5550
MC1741L
LM111J-8
LM111J-8
LM11CLN
LM11CN
LM124J
LM124J
LM124J
LM124N
LM139AJ
LM139J
MC1391P
MC140BL8
MC140BPB
MC14B9AP
MC14B9L
MC14B9P
MC1496L
MC1496P
MC4741L
LM15BJ
LM158J
MC155BU
MC1596L
MC3450L
MC34B4S2
MC1374P
MC3301P
MC13020P
LM201AD
LM201AJ
LM201AJ
LM201AJ
LM201AN
LM201AN
LM201AJ
LM201AJ
LM211D
LM211J-8
LM211J-B
LM211D
MC1456U
LM224J
LM224J
LM224D
LM224J
LM224D
LM224N
LM239AJ
LM239AN
LM239D

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

1-8

Motoria
Similar
Replacement

Cross Reference
Indust~

PartNum

r

LM239J
LM239M
LM239N
LM240LAZ-12
LM240LAZ-1S
LM240LAZ-1S
LM240LAZ-24
LM240LAZ-S.0
LM204LAZ-6.0
LM240LAZ-S.0
LM248J
LM24SN
LM249J
LM249N
LM25SD
LM258J
LM25SM
LM25SN
LM2S5Z-1.2
LM2S5Z-2.5
LM2900N
LM2901D
LM2901M
LM2901N
LM2902D
LM2902J
LM2902M
LM2902N
LM2903D
LM2903M
LM2903N
LM2903P
LM2904J
LM2904M
LM2904N
LM290SN
LM2931 ACT
LM2931 AD-5.0
LM2931AT-5.0
LM2931 AZ-S.O
LM2931CD
LM2931CM
LM2931CT
LM2931 D-5.0
LM2931D
LM2931T-5.0
LM2931 Z-5.0
LM2935T
LM293D
LM301AD
LM301AJG
LM301AJ
LM301AM
LM301AN
LM301AP
LM3026
LM3045
LM3046N
LM3054
LM307N
LM307P

(continued)

Motorola
Nearest
Replacement

Motoria
Similar
Replacement

Indust~

PartNum er

LM239J
LM239D
LM239N

LM30S9
LM3llD
LM3llJ-S
LM331JG
LM3llM
LM3llN-14
LM3llN
LM3llP
LM3l46A
LM3l46
LM3l7KC
LM3l7KD
LM3l7LD
LM3l7LZ
LM3l7MP
LM3l7P
LM3l7T
LM31S9
LM320LZ-12
LM320LZ-15
LM320LZ-5.0
LM320MP-12
LM320MP-15
LM320MP-1S
LM320MP-24
LM320MP-5.0
LM320MP-5.2
LM320MP-6.0
LM320MP-S.0
LM320T-12
LM320T-15
LM320T-5.0
LM320T-5.2
LM322N
LM323AT
LM323T
LM324AD
LM324AJ
LM324AN
LM324D
LM324J
LM324M
LM324N
LM325AN
LM325N
LM326N
LM328AN
LM32SN
LM3301N
LM3302J
LM3302N
LM337MP
LM337MT
LM337T
LM339AD
LM339AJ
LM339AM
LM339AN
LM339D
LM339J
LM339N

MC78L12ACP
MC78L1SACP
MC7SL1SACP
MC7SL24ACP
MC7SL05ACP
MC7SL05ACP
MC7SLOSACP
LM24SJ
LM24SN
MC4741L
MC4741P
LM25SD
LM25SJ
LM25SD
LM25SN
LM25SZ-l.2
LM25SZ-2.5
LM2900N
LM2901D
LM2901D
LM2901N
LM2902D
LM2902J
LM2902D
LM2902N
LM2903D
LM2903D
LM2903N
LM2903N
LM2904J
LM2904D
LM2904N
MCl455Pl
LM2931ACT
LM2931AD-5.0
LM2931AT-5.0
LM2931 AZ -5.0
LM2931CD
LM2931CD
LM2931CT
LM2931 D-5.0
LM2931D
LM2931T-5.0
LM2931Z-5.0
MC2935T
LM293D
LM301AD
LM301AJ
LM301AJ
LM301AD
LM301AN
lM301AN
CA3054
MC3346P
MC3346P
CA3054
LM307N
LM307N

Motorola
Nearest
Replacement

MC3356P
LM3llO
LM3llJ-S
LM3llJ-S
LM3llO
LM3llJ-S
LM3llN
LM3llN
MC3346P
MC3346P
LM3l7T
LM3l7T
LM3l7LD
LM3l7LZ
LM3l7MT
LM3l7T
LM3l7T
MC3356P
MC79L12ACP
MC79L15ACP
MC79L05ACP
MC79l2CT
MC79l5CT
MC791SCT
MC7924CT
MC7905CT
MC790S.2CT
MC7906CT
MC790SCT
MC79l2CT
MC79l5CT
MC790SCT
MC790S.2CT
MC145SPl
LM323AT
LM323T
LM324AD
LM324J
LM324AN
LM324D
LM324J
LM324D
LM324N
MCl468L
MC146SL
MC146SL
MCl46SL
MC146SL
MC3301L
MC3302L
MC3302P
LM337MT
LM337MT
LM337T
LM339AD
LM339AJ
LM339AD
LM339AN
LM339D
LM339J
LM339N

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
1-9

Motoria
Similar
Replacement

Cross Reference (continued)
Mol.Orola
:;:,I~: MOtorIa
Similar· ..
i~~~~~I~r::=,~~,",::~":' i. RlIJIIacenMtrit:
I

I

•.
• ••. .:. I

l:

LM339P
LM3401N
LM340AT-12
LM340AT-15
LM340AT-5.0
LM340KC-12
LM340KC-15
LM340LAZ-12
LM340LAZ-18
.LM340LAZ-24
LM340LAZ-5.0
LM340LAZ-8.0
LM340T-12
LM340T-15
LM340T-18
LM340T-24
LM340T-5.0
LM340T-S.O
LM340T-8.0
LM341P-12
LM341P-15
LM341P-18
LM341P-24
LM341P-5.0
LM341P-S.0
LM341P-8,0
LM342P-12
LM342P-15

LM339N

LM3900N
LM3905N
LM393AN
LM393D
LM393JG
LM393M
LM393N
LM4250CN
LM55109J
LM5511OJ
LM555CN
LM556CD
LM556CJ
LM556CN
LM556L
LM703LN
LM723CD
LM723CJ
LM723CN
LM723J
LM741CD
LM741CJ-14
LM741EJ
. LM741EN
LM747CD
LM748CN
LM75107AN
LM7510sAJ
LM75108AN
LM75.11OJ
LM7511ON
LM75207L
LM75207N
LM7520BJ
LM75208N
LM7805CT
- LM7812CT
LM781sCT
LM78L05ACZ
LM78L05CZ
LM78L08ACZ
LM78L08CZ
LM78L12ACZ
LM78L12CZ
LM78L15ACZ
LM78L15CZ
LM78L18ACZ
LM78L18CZ
LM78L24ACZ
LM78L24CZ
LM78M06CP
LM78M12CP
LM78M15CP
LM7905CT
LM7912CT
LM7915CT
LM79L05ACZ
LM79L12ACZ
LM79L15ACZ
LM79M05CP
LM79M12CP

MC3401P
LM340AT-12
LM340AT-15
LM340AT-5.0
LM340T-12
LM340T-15.
MC78L12ACP
MC78L18ACP
MC78L24ACP
MC78LOSACP
MC78L08ACP
LM340T-12
LM340T-15
LM340T-18
LM340T-24
LM340T-5.0
LM340T-6.0
LM340T-8.0
MC78M12CT
MC78M15CT
MC78M18CT
MC78M24CT
MC78M05CT
MC78M06CT
MC78M08CT
MC78M12CT
MC78M15CT
MC78M18CT
MC78M24CT
MC78M05CT
MC78M06CT

LM342P~18

LM342P-24 .
LM342P-5,0
LM342P-S.O
LM342P-8.0 .
LM348D·LM348J
LM348M
LM348N
LM349J
LM349N
LM350T
LM35BAN
LM358D
LM35BJG
LM35BJ
LM358M
LM358N
LM363AJ
LM363AN
LM363J
LM363N
LM3858Z-1.2
LM3858Z-2.5
LM385D-1.2
LM385D·2.5
LM385M-1.2
LM385M-2.5
LM385Z-1.2
LM385Z-2.5
LM386N
LM3900D
LM3900J

,nd···'>";··

."'rt.~~.

:

MC78~08CT

:

LM348D
LM348J
LM348D
LM348N
MC4741CL
MC4741CP
LM350T
LM358N
LM358D
LM358J
LM358J
LM358D
·LM358N
MC3450L
MC3450P
MC3450L
MC3450P
LM3858Z-1.2
LM3858Z-2.5
LM385D-1.2
LM385D-2.5
LM385D-1.2
LM385D-2.5
LM385Z-1.2
LM385Z-2.5
MC34119P
LM3900D
LM3900J

LM3900N
MC1455P1
LM393AN
LM393D
LM393N
LM393D
LM393N
MC1776CP1
MC75S110L
MC75S110L
MC1455P1
MC3456L
MC3456L
MC345SP
MC3456L
MC1350P
MC1723CL
MC1723CL
MC1723CP
MC1723L
MC1741CL
MC1741CL
MC1741CU
MC1741CP1
MC1747CL
MC1748CP1
MC75107P
MC75108L
MC75108P
MC75S110L
MC758110P
MC75107L
MC75107P
MC75108L
MC75108P
MC7805CT
MC7812CT
MC7815CT
MC78LOSACP
MC78L05CP
MC78LOBACP
MC78L08CP
-MC78L12ACP
MC78L12CP
MC78L15ACP
MC78L15CP
MC78L18ACP
MC78L18CP
MC78L24ACP
MC78L24CP
MC78M05CT
MC78M12CT
MC78M15CT
MC7905CT
MC7912CT
MC7915CT
MC79LOSACP
MC79L12ACP
MC78L15ACP

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
1-10

MC79MOSCT
MC79M12CT

Cross Reference (continued)
Indust~
PartNum r

LM79M15CP
LM833D
LM833N
LM833P
LM837N
LMC6482D
LMC6482P
LMC6484D
LMC6484P
LT1083
MB3759
MP5531CP
MP5531DP
MP5532CP
MP5532DP
N5558F
N555BV
N5595A
N5595F
N5596A
N5723A
N5741 A
N5741 V
N5747A
N5747F
NBT15A
NBT15F
NBT16A
NBT26AB
NBT26AE
NBT26AJ
NBT26AN
NBT26B
NBT26J
N8T26N
NBT37A
NBT97B
NBT97F
NBT97N
NBT98B
NBT9BF
N8T9BN
NE550A
NE555JG
NE555D
NE555V
NE556D
NE556F
NE5561FE
NE5561N
NE5234D
NE5234P
OP-01P
PWM125CK
RC145BDN
RC1488DC
RC14B9ADC
RC14B9DC
RC3302DB
RC4136DP
RC4136D

Motorola
Nearest
Replacement

Motoria
Similar
Replacement

p~~d3';;~~er

MC79M15CT

RC4136J
RC4136N
RC4194DC
RC4195NB
RC455BON
RC455BJG
RC4458P
RC7230B
RC723DC
RC723D
RC741DN
RC747D
RC75107AOP
RC75107AD
RC7510BAOP
RC7510BAD
RC75109DP
RC751 090
RC75110DP
RC75110D
REF-01CJ
REF-01CP
REF-01CZ
REF-01OJ
REF-01DP
REF-01DZ
REF-02CJ
REF-02CP
REF-02CZ
REF-02DJ
REF-02DP
REF-02OZ
RM41360
RM4136J
RM4194DC
RM455BD
RM4558JG
RM723DC
RM723D
RM741DP
RM747D
RV3301DB
S555BE
S5596F
SA555N
SAA1042A
SAA1042
SG107J
SG107T
SG111D
SG124J
SG1402N
SG1402T
SG1436M
SG145BM
SG1468J
SG1468N
SG1495D
SG1495N
SG1496D
SG1496N

LM833D
LM833N
LM833N
MC33079P
MC33202D
MC33202P
MC33204D
MC33204P
MC34268
TL494CN
MC1404U5
MC1404U5
MC1404U10
MC1404U10
MC1458U
MC145BP1
MC1495L
MC1495L
MC1496L
MC1723CP
MC1741CP1
MC1741CP1
MC1747CL
MC1747CL
MC148BL
MC14BBL
MC1489L
MC8T26AP
MCBT26AL
MCBT26AL
MCBT26AP
MC8T26AP
MCBT26AL
MC8T26AP
MC3437P
MCBT97P
MCBT97L
MCBT97P
MC8T98P
MCBT98L
MCBT9BP
MC1723CP
MC1455U
MC1455D
MC1455P1
NE5560
MC3456L
MC34060AL
MC34060P
MC33204D
MC33204P
MC1436P1
SG3525AJ
MC145BP1
MC14BBL
MC14B9AL
MC14B9L
MC3302P
MC3403P
MC3403L

Motorola
Nearest
Replacement

MC3403L
MC3403P
MC146BL
MC146BL
MC455BCP1
MC455BCU
MC455BCP1
MC1723CP
MC1723CL
MC1723CL
MC1741CP1
MC1747CL
MC75107P
MC75107L
MC7510BP
MC7510BL
MC75S110P
MC75S110L
MC75S110P
MC75S110L
MC1404U10
MC1404U10
MC1404U10
MC1404U10
MC1404U10
MC1404U10
MC1404U5
MC1404U5
MC1404U5
MC1404U5
MC1404U5
MC1404U5
MC3503L
MC3503L
MC156BL
MC4558U
MC455BU
MC1723L
MC1723L
MC1741L
MC1747L
MC3301P
MC155BU
MC1596L
MC1455BP1
SAA1042AV
SAA1042V
MC1741L
MC1741L
LM111J
LM124J
MC1594L
MC1594L
MC1436U
MC1458P1
MC146BL
MC146BL
MC1495L
MC1495L
MC1496L
MC1496P

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
1-11

Motoria
Similar
Replacement

Cross Reference (continued)
,: ";'.d:,~, ,
""
'"dusi~ ,
"Part Num, r
SG1501AD
SG1501AJ
SG1501AJ
SG1502D
SG1502J
SG1502N
SG1503T
SG1503Y
SG1524J
SG1568J
SG1595D
SG1596D
SG201AM
SG201AN
SG201M
SG201N
SG211D
SG211M
SG224J
SG224N
SG2402N
SG2402T
SG2501AD
SG2501D
SG2501J
SG2501N
SG2502J
SG2502N
SG2503M
SG2503T
SG2503Y
SG300N
SG301AM
SG301AN
SG307J
SG307M
SG307N
SG308AM
SG311D
SG311M
SG317P
SG317R
SG324J
SG324N
SG337P
SG337R
SG3402N
SG3402T
SG3423M
SG3423Y
SG3501AD
SG3501AJ
SG3501AN
SG3501D
SG3501J
SG3501N
SG3502D
SG3502J
SG3502N
SG3503M
SG3503T

"

Ii,

11:

"'

, Motorola'
Nearelltl:' '"

~lIep"'c8ii18nr'

'", , '

Motoria
Similar'
Replacement

" ',,': , '"dUst~
,PartNum .'

MC1568L
MC1568L

SG3503Y
SG3523Y
SG3524J
SG3525AJ
SG3525AN
SG3526J
SG3526N
SG3527AJ
SG3527AN
SG3561
SG4194CJ
SG4194J
SG4250CM
SG4501D
SG4501J
SG4501N
SG555CM
SG556CJ
SG556CN
SG556J
SG723CD
SG723CJ
SG723CN
SG723D
SG723J
SG741CM
SG747CJ
SG747CN
SG747J
SG748CD
SG748CM
SG748CN
SGn7CN
SG7805ACP
SG7805ACR
SG7805ACT
SG7805CP
SG7806ACP
SG7806ACR
SG7806ACT
SG7806CP
SG7806CR
SG7808ACP
SG7808ACT
SG7808CP
SG7808CR
SG7812ACP
SG7812ACR
SG7812ACT
SG7812CP
SG7812CR
SG7815ACP
SG7815ACR
SG7815ACT
SG7815CP
SG7815CR
SG7815CT
SG7818ACP
SG7818ACR
SG7818ACT
SG7818CP

MC1568L
MC1568L
MC1568L
MC1568L
MC1503U
MC1503U
TL494MJ
MC1568L
MC1595L
MC1596L
LM201AN
LM201AN
LM201AN
LM201AN
LM211J-8
LM211J-8
LM224J
LM224N
MC1494L
MC1494L
MC1468L
MC1468L
MC1468L
MC1468L
MC1468L
MC1468L
MC1403AU
MC1403AU
MC1403AU
MC1723CP
LM301AN
LM301AN
LM307N
LM307N
LM307N
LM308AN
LM311J
LM311N
LM317T
LM317T
LM324J
LM324N
LM337T
LM337T
MC1494L
MC1494L
MC3423P1
MC3423U
MC1468L
MC1468L
MC1468L
MC1468L
MC1468L
MC1468L
MC1468L
MC1468L
MC1468L
MC1403U
MC1403U

'"Motorola
, ",,.:,'Neareal
,

:'<'Repl~~e"1

"', ,Molortl,'C':"
' ,':'':'Slmllar "!"r,:
," ",' "RI!P'Ilc:ei'iient,'':''

MC1403U
MC3523U
TL494CJ
SG3525AJ
SG3525AN
SG3526J
SG3526N
SG3527AJ
SG3527AN
MC34261
MC1468L
MC1568L
MC1775CP1
MC1468L
MC1468L
MC1468L
MC1455P1
MC3456L
MC3456P
MC3456L
MC1723CL
MC1723CL
MC1723CP
MC1723L
MC1723L
MC1741CP1
MC1747CL
MC1747CP2
MC1747L
MC1748CP1
MC1748CP1
MC1748CP1
LM308AN
MC7805ACT
MC7805ACT
MC7805ACT
MC7805CT
MC7806ACT
MC7806ACT
MC7806ACT
MC7806CT
MC7806CT
MC7808ACT
MC780BACT
MC7808CT
MC7808CT
MC7812ACT
MC7812ACT
. MC7812ACT
MC7812CT
MC7812CT
MC7815ACT
MC7815ACT
MC7815ACT
MC7815CT
MC7815CT
MC7815CT
MC7818ACT
MC7818ACT
MC7818ACT
MC7818CT

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

1-12

,

Cross Reference (continued)
Indust~

PartNum

SG7818CR
SG7824ACP
SG7824ACR
SG7824ACT
SG7824CP
SG7824CR
SG7905.2CP
SG7905.2CR
SG7905.2CT
SG7905ACP
SG7905ACR
SG7905ACT
SG7905CP
SG7905CR
SG7905CT
SG7908CP
SG7908CR
SG7908CT
SG7912ACP
SG7912ACR
SG7912ACT
SG7912CP
SG7912CR
SG7912CT
SG7915ACP
SG7915ACR
SG7915ACT
SG7915CP
SG7915CR
SG7915CT
SG7918CP
SH8090FM
SN75107AJ
SN75107AN
SN75107BJ
SN75107BN
SN75108AJ
SN75108AN
SN75108BJ
SN75108BN
SN75110AJ
SN75110AN
SN75121J
SN75121N
SN75125N
SN75126J
SN75126N
SN75150J
SN75150N
SN75154J
SN75154N
SN75160J
SN75160N
SN75172N
SN75173J
SN75173N
SN75174N
SN75175J
SN75175N
SN75188J
SN75188N

r

Motorola
Nearest
Replacement

Motoria
Similar
Replacement

P~~'W~~1:er
SN75189AJ
SN75189AN
SN75189J
SN75189N
SN75207J
SN75207N
SN75208J
SN75208N
SN75251N
SN75466J
SN75466N
SN75467J
SN75467N
SN75468J
SN75468N
SN75475JG
SN75475P
SN76514N
SN76591P
SN76600P
SSS140BA-8Z
SSS150BA-8Z
SSS201AP
SSS301AP
SSS747BP
SSS747CP
SSS747GP
SSS747P
TA7179P
TA7504P
TA7506P
TA75071P
TA75072P
TA75074F
TA75339F
TA75339P
TA75358CF
TA75358CP
TA75393F
TA75393P
TA75458F
TA75458P
TA75558P
TA7555F
TA7555P
TA75902F
TA76494P
TA78005AP
TA78006AP
TA78008AP
TA78012AP
TA78015AP
TA78018AP
TA78024AP
TA78LOO5AP
TA78LOO5P
TA78LOO8AP
TA78LOO8P
TA78L012AP
TA78L012P
TA78L015AP

MC7818CT
MC7824ACT
MC7824ACT
MC7824ACT
MC7824CT
MC7824CT
MC7905.2CT
MC7905.2CT
MC7905.2CT
MC7905ACT
MC7905ACT
MC7905ACT
MC7905CT
MC7905CT
MC7905CT
MC7908CT
MC7908CT
MC7908CT
MC7912ACT
MC7912ACT
MC7912ACT
MC7912CT
MC7912CT
MC7912CT
MC7915ACT
MC7915ACT
MC7915ACT
MC7915CT
MC7915CT
MC7915CT
MC7918CT
MC1508L8
MC75107L
MC75107P
MC75107L
MC75107P
MC75108L
MC75108P
MC75108L
MC75108P
MC75S110L
MC75S110P
MC3481/5L
MC3481/5P
MC3481/5L
MC3481/5L
MC3481/5P
MC1488L
MC1488P
MC1489L
MC1489P
MC3447L
MC3447P/P3
MC75172BP
SN75173J
SN75173N
MC75174BP
SN75175J
SN75175N
MC1488L
MC1488P

Motorola
Nearest
Replacement
MC1489AL
MC1489AP
MC1489L
MC1489P

MC75107L
MC75107P
MC75108L
MC75108P
MC3471P
MC1411L
MC1411P
MC1412L
MC1412P
MC1413L
MC1413P
MC1472U
MC1472P1
MC1496P
MC1391P
MC1350P
MC1408L8
MC1508L8
LM201AN
LM301AN
MC1747L
MC1747CL
MC1747L
MC1747L
MC1468L
MC1741CP1
LM301AN
MC34001P
MC34002P
MC34004P
LM339D
LM339N
LM358D
LM358N
LM393D
LM393N
MC1458D
MC1458CP1
MC4558CP1
MC1455D
MC1455P1
LM324D
TL4941N
MC7805CT
MC7806CT
MC7808CT
MC7812CT
MC7815CT
MC7818CT
MC7824CT

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
1-13

Motoria
Similar
Replacement

MC78L05ACP
MC78L05CP
MC78L08ACP
MC78L08CP
MC78L12ACP
MC78L12CP
MC78L15ACP

Cross Reference

P~~~~~ter
TA78L015P
TA78L018AP
TA78L018P
TA78L024AP
TA78L024P
TA78M05P
TA78M06P
TA78M08P
TA78M12P
TA78M18P
TA78M20P
TA78M24P
TA79005P
TA79006P
TA79008P
TA79012P
TA79015P
TA79018P
TA79024P
TA79LOO5P
TA79L012P
TA79L015P
TA79L018P
TA79L024P
TB920
TBA920S
TCA5600
TCF5600
TD62001 P/AP
TD62002P/AP
TD62003P/AP
TD62477P
TD62479P
TDA1085A
TDA1085C
TDA1085
TDAl185A
TDA3301B
TDA4817
TDC1048
TLC2272D
TLC2272P
TLC2274D
TLC2274P
TL022CJG
TL022CP
TL022MJG
TL044CJ
TL044MJ
TL062ACP
TL062CD
TL062CP
TL062MJG
TL062VP
TL064ACD
TL064ACN
TL064CD
TL064CN
TL064MJ
TL064VN
TL071ACD

(continued)

Motorola
Nearest
Replacement

Motoria
Similar
Replacement

Industry
Part Number

MC78L15CP
MC78L18ACP
MC78L18CP
MC78L24ACP
MC78L24CP

TL071ACJG
TL071ACP
TL071CD
TL071CJG
TL071CP
TL071MJG
TL072ACD
TL072ACJG
TL072ACP
TL072CD
TL072CJG
TL072CP
TL072MJG
TL074ACJ
TL074ACN
TL074CJ
TL074CN
TL074MJ
TL081ACD
TL081 ACJG
TL081ACP
TL081CD
TL081CJG
TL081CP
TL081MJG
TL082ACJG
TL082ACP
TL082CD
TL082CJG
TL082CP
TL082MJG
TL084ACJ
TL084ACN
TL084CJ
TL084CN
TL084MJ
TL1431
TL431CD
TL431CJG
TL431CLP
TL431CP
TL4311JG
TL4311LP
TL4311P
TL431MJG
TL494CJ
TL494CN
TL4941J
TL4941N
TL494MJ
TL497CJ
TL497CN
TL497MJ
TL594CN
TL5941N
TL594MJ
TL780-05CKC
TL780-12CKC
TL780-15CKC
TL7805ACKC
IlA0802DC-l

MC78M05CT
MC78M06CT
MC78M08CT
MC78M12CT
MC78M18CT
MC78M20CT
MC78M24CT
MC7905CT
MC7906CT
MC7908CT
MC7912CT
MC7915CT
MC7918CT
MC7924CT
MC79L05CP
MC79L12P
MC79L15P
MC79L18P
MC79L24P
MC1391P
MC1391P
TCA5600
TCF5600
MC1411P
MC1412P
MC1413P
MC1472P
MC1374P
TDA1085A
TDA1085C
TDA1085C
TDAl185A
TDA3301B
MC34261
MC10319P
MC33202D
MC33202P
MC33204D
MC33204P
LM358J
LM358N
LM158J
LM324N
LM124J
TL062ACP
TL062CD
TL062CP
TL062MJG
TL062VP
TL064ACD
TL064ACN
TL064CD
TL064CN
TL064MJ
TL064VN
TL071ACD

Motorola
Nearest
Replacement
TL071 ACJG
TL071ACP
TL071CD
TL071CJG
TL071CP
TL071MJG
TL072ACD
TL072ACJG
TL072ACP
TL072CD
TL072CJG
TL072CP
TL072MJG
TL074ACJ
TL074ACN
TL074CJ
TL074CN
TL074MJ
TL081ACD
TL081 ACJG
TL081ACP
TL081CD
TL081CJG
TL081CP
TL081MJG
TL082ACJG
TL082ACP
TL082CD
TL082CJG
TL082CP
TL082MJG
TL084ACJ
TL084ACN
TL084CJ
TL084CN
TL084MJ

TL431
TL431CD
TL431CJG
TL431CLP
TL431CP
TL4311JG
TL4311LP
TL4311P
TL431MJG
TL494CJ
TL494CN
TL4941J
TL4941N
TL494MJ
MC34063AU
MC34063APl
MC35063AU
TL594CN
TL5941N
TL594MJ
TL780-05CKC
TL780-12CKC
TL780-15CKC
MC7805ACT
MC1408L8

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

1-14

Motoria
Similar
Replacement

Cross Reference (continued)
Industry
Part Number

IIAOB02DC-2
IIAOB02DC-3
IIAOB02DM-1
IIAOB02PC-1
flAOB02PC-2
flAOB02PC-3
flA101AD
1IA101AF
1IA101D
flA101F
flA1391PC
flA145BCP
flA145BCRC
flA145BCTC
flA145BP
flA145BRC
1IA145BTC
flA201AD
flA201AF
1IA201D
1IA201F
1IA2240DC
1IA2240PC
1IA301AD
1IA301AT
1IA3026HM
1IA3045
1IA3046DC
1IA3054DC
1IA307T
1IA311T
1IA317UC
1IA3301P
1IA3302P
1IA3303P
1IA3401 P
1IA3403D
1IA3403P
1IA4136DC
1IA4136DM
1IA4136PC
1IA431AWC
1IA455BTC
1IA494DC
1IA494DM
1IA494PC
1IA555TC
1IA556DC
1IA556PC
1IA723CF
1IA723CJ
1IA723CN
1IA723DC
1IA723DM
1IA723F
1IA723MJ
1IA723PC
1IA734DC
1IA734DM
1IA741 ADM
1IA741CJG

Molorola
Nearest
Replacement

Motoria
Similar
Replacement

Industry
Part Number

MC140BLB
MC140BLB
MC150BLB
MC140BPB
MC140BPB
MC140BPB

flA741CP
flA741MJG
1IA741RC
flA741RM
1IA742DC
1IA747ADM
flA747CN
1IA747DC
1IA747DM
1IA747EDC
1IA747MJ
1IA747PC
1IA74BCP
1IA74BTC
1IA757DC
1IA757DM
1IA775DC
1IA775DM
1IA775PC
flA776TC
flA7B05CKC
1IA7B05UC
1IA7B05UV
1IA7B06CKC
1IA7806UC
1IA7806UV
flA7B08CKC
flA7B08UC
1IA7808UV
1IA7812CKC
1IA7B12UC
1IA7812UV
flA7815CKC
flA7815UC
1IA7815UV
flA7818CKC
flA7818UC
1IA7818UV
flA7B24CKC
flA7824UC
1IA7824UV
flA78GU1C
1IA78GUC
1IA78L05ACLP
1IA78L05AWC
1IA78L05CLP
flA7BL05WC
flA78L08ACLP
IIA78L08AWC
flA78L08CLP
1IA78L12ACLP
1IA78L12AWC
1IA78L12CLP
1IA78L12WC
1IA78L15ACLP
1IA78L15AWC
1IA78L15CLP
1IA78L15WC
1IA78L18AWC
1IA78L24AWC
1IA78M05CKC

LM101AJ
LM101AJ
LM101AJ
LM101AJ
MC1391P
MC145BCP1
MC145BCU
MC145BCP1
MC145BP1
MC145BU
MC145BP1
LM201AJ
LM201AJ
LM201AJ
LM201AJ
MC1455U
MC1455P1
LM301AJ
LM301AN
CA3054
MC3346P
MC3346P
CA3054P
LM307N
LM311N
LM317T
MC3301P
MC3302P
MC3303P
MC3401P
MC3403L
MC3403P
MC4741CL
MC4741L
MC4741CP
TL431CP
MC455BCP1
TL494CJ
TL494MJ
TL494CN
MC1455P1
MC3456L
MC3456P
MC1723CL
MC1723CL
MC1723CP
MC1723CL
MC1723L
MC1723L
MC1723L
MC1723CP
LM311J
LM311J
MC1741L
MC1741CU

Motorola
Nearest
Replacement

MC1741CP1
MC1741U
MC1741CU
MC1741U
CA3059
MC1747L
MC1747CP2
MC1747CL
MC1747L
MC1747CL
MC1747L
MC1747CP2
MC174BCP1
MC174BCP1
MC1350P
MC1350P
LM339J
LM339J
LM339N
MC1776CP1
MC7B05CT
MC7B05CT
MC7B05BT
MC7806CT
MC7B06CT
MC7806BT
MC7808CT
MC7808CT
MC7808BT
MC7812CT
MC7812CT
MC7B12BT
MC7815CT
MC7815CT
MC7815BT
MC7818CT
MC7818CT
MC7818BT
MC7B24CT
MC7824CT
MC7B24BT
LM317T
LM317T
MC78L05ACP
MC78L05ACP
MC78L05CP
MC78L05CP
MC78LOBACP
MC7BL08ACP
MC78LOBCP
MC78L12ACP
MC78L12ACP
MC78L12CP
MC78L12CP
MC78L15ACP
MC78L15ACP
MC78L15CP
MC78L15CP
MC7BL18ACP
MC78L24ACP
M78M05CT

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

1-15

Motoria
Similar
Replacement

Cross Reference (continued)
,c

"

Indu81~ ,(
PartNum r
pA78MOSCKD
pA78M05UC
pA78M06CKC
pA78M06CKD
pA78M06UC
pA78M08CKC
pA78M08CKD
pA78M08UC
pA78M12CKC
pA78M12CKD
pA78M12UC
pA78M15CKC
pA78M15CKD
pA78M15UC
pA78M18UC
pA78M20CKC
pA78M20CKD
pA78M20UC
pA78M24CKC
pA78M24CKD
pA78M24UC
pA78MGT2C
pA78MGU1C
pA78MGUC
pA78S40DC
pA78S40DM
pA78S40PC
pA78S40PV
pA7905.2CKC
pA7905CKC
pA7905UC
pA7906CKC
pA7906UC
pA7908CKC
pA7912CKC
pA7912UC
pA7915CKC
pA7915UC
pA791BCKC
pA7918UC
pA7924CKC
pA7924UC
pA7960C
pA796DM
pA798RC
pA798RM
pA798TC
pA79LOSAWC
pA79L05WC
pA79L12AWC
pA79L12WC
pA79L1SAWC
pA79L15WC
pA79M05AUC
pA79MOSCKC
pA79M06AUC
pA79M06CKC
pA79M06UC
pA79M08AUC
pA79M06CKC

pA79M12AUC
pA79M12CKC
pA79M18AUC
pA79M18UC
pA79M24AUC
pA79M24CKC
pA79M24UC
pA9636ATC
UAA1016B
UC2842AD
UC2842AJ
UC2842AN
UC2842BD
UC2842BN
UC2842D
UC2842N
UC2843AD
UC2843AJ
UC2843AN
UC2843BD
UC2843BN
UC2843D
UC2843N
UC2844BD
UC2844BN
UC2844D
UC2844J
UC2844N
UC2845BD
UC2845BN
UC2845D
UC2845J
UC2845N
UC317T
UC337T
UC3525AJ
UC3525AN
UC3526J
UC3526N
UC3527AJ
UC3527AN
UC3823
UC3825
UC3842AD
UC3842AN
UC3842BD
UC3842BN
UC3842D
UC3842N
UC3843AD
UC3843AN
UC3843BD
UC3843BN
UC3843D
UC3843N
UC3844BD
UC3844BN
UC3844D
UC3844J
UC3844N
UC3845BD

MC78MOSCT
MC78M06CT
MC78M06CT
MC78M06CT
MC78M08CT
MC78M08CT
MC78M08CT
MC78M12CT
MC78M12CT
MC78M12CT
MC78M15CT
MC78M15CT
MC78M15CT
MC78M18CT
MC78M20CT
MC78M20CT
MC78M20CT
MC78M24CT
MC78M24CT
MC78M24CT
LM317T
LM317T
LM317MT
pA78S40DC
pA78S40DM
pA78S40PC
pA78S40PV
MC7905.2CT
MC790SCT
MC790SCT
MC7906CT
MC7906CT
MC7908CT
MC7912CT
MC7912CT
MC791SCT
MC791SCT
MC7918CT
MC781BCT
MC7924CT
MC7924CT
MC1496L
MC1596L
MC3458U
MC3558U
MC3458Pl
MC79LOSACP
MC79LOSCP
MC79L12ACP
MC79L12CP
MC79L15ACP
MC79L1SCP
MC79MOSCT
MC79M05CT
MC7906CT
MC7906CT
MC7906CT
MC790BCT
MC790BCT
MC790BCT

,Moto.:bia'
Naare81" ,
RIIJII,aC!'",enl

'

Motoria" P
Similar" ,,'
Replacement '

MC79M12CT
MC79M12CT
MC7918CT
MC7918CT
MC7924CT
MC7924CT
MC7924CT
, MC3488API
UAA1016B
UC2842AD
UC2842AJ
UC2842AN
UC2842BD
UC2842BN
UC2842AD
UC2842AN
UC2843AD
UC2843AJ
UC2843AN
UC2843BD
UC2843BN
UC2843AD
UC2843AN
UC2844BD
UC2844BN
UC2844D
UC2844J
UC2844N
UC2845BD
UC2845BN
UC2845D
UC2845J
UC2845N
LM317T
LM337T
SG3525AJ
SG3525AN
SG3526J
SG3526N
SG3527AJ
SG3527AN
MC34023
MC34025
UC3842AD
UC3842AN
UC3842BD
UC3842BN
UC3842AD
UC3842AN
UC3843AD
UC3843AN
UC3843BD
UC3843BN
UC3843AD
UC3843AN
UC3844BD
UC3844BN
UC3844D
UC3844J
UC3844N
UC3845BD

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

1-16

,

Cross Reference (continued)
Industry
Part Number

UC3845BN
UC3845D
UC3845N
UC494ACN
UC494AJ
UC494CN
UC494J
UCN5816A
UDN5712M
ULN2068BB
ULN2068NE
ULN2151 H
ULN2151M
ULN2747A
ULN2801A
ULN2802A
ULN2803A
ULN2804A

--

Motorola
Nearest
Replacement

Motoria
Similar
Replacement

p~~d~~,~'ber

UC3845BN
UC3845D
UC3845N

ULNB126A
ULN8126R
ULQ8126R
ULS2151M
ULS2157A
ULS2157H
ULX8161M
UPC1373
UPD6950C
UVC3101
XR082CN
XR082CP
XR082M
XR084CN
XR084CP
XR084M
XR3470A

TL594CN
TL594MJ
TL494CN
TL494MJ
MC34142
MC1472P1
ULN2068B
ULN2068B
MC1741CP1
MC1741CP1
MC1747CL
ULN2801A
ULN2802A
ULN2803A
ULN2804A

Motorola
Nearest
Replacement

SG3526N
SG3526J
SC3526J
MC1741CP1
MC1558U
MC1558U
MC34060P
MC3373P
MC10319P
MC10319P
TL082CJG
TL082CP
TL082MJG
TL084CJ
TL084CN
TL084MJ
MC3470AP

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
1-17

Motoria
Similar
Replacement

MOTOROLA LlNEARIiNTERFACE ICs DEVICE DATA
1-18

Voltage References

In Brief ...
Page

Motorola's line of precIsion voltage references is
designed for applications requiring high initial accuracy, low
temperature drift, and long term stability. Initial accuracies of
± 1.0%, and± 2.0% mean production line adjustments can
be eliminated. Temperature coefficients of 25 ppm;oC
maximum (typically, 10 ppm;oC) provide excellent stability.
Uses for the references include OIA converters, NO
converters, precision power supplies, voltmeter systems,
temperature monitors, and many others.

Precision Low Voltage References . . . . . . . . . . . . . . . . .. 5-2
Index ........................................... 5-3
Data Sheets ..................................... 5-4

Precision Low Voltage References
A family of precision low voltage bandgap reference
devices designed for applications requiring low temperature
drift.

1.235±12mV
1.235±25 mV

20

80Typ

2.5±38 mV
2.5±75 mV
2.5±25 mV

LM385BZ-l.2
LM385Z-1.2

LM285Z-1.2
(-40' 10 +85'C)

LM385BZ-2.5
LM385Z-2.5

(-40' 10 +85'C)

(Nolel)

LM285Z-2.5

(Note 4)

10
(Note 6)

6.0
(NoteS)

5.0±50 mV

Zl29

2.0
(Nole3)

3.0/4.5

10

1.0
(Note 2)

U/693,01751

U/693

6.2S±60 mV

10±100mV

2.51037

100

50Typ

TL431C, AC, BC

TL4311, AI, BI
(-40' to +8S'C)

Shunt Reference
Dynamic Impedance
(z)SO.SO

NOles: I. Micropower Reference Diode Dynamic Impedance (z) S 1.0 n al IR =100 IIA
2.10IlASIRsl.0mA
3. 20 IIA S IR S 1.0 mA
4.4.5 VsVin S 15 V/15 VsVin S40V
5. (Voul + 2.5 V) S Vin S 40V
6.0mAs1LS10mA

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

5-2

LPI29, P/626
JGl693, 01751

Voltage References
Page

Device

Function

LM285, LM385
MC1403,A, MC1503
MC1404,A, MC1504

Micropower Voltage Reference Diodes .............................. 5-4
Precision Low Voltage Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-8
Precision Low Drift Voltage References ............................. 5-12
Programmable Precision References .............................. 5-17

TL431 , A, B Series

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

5-3

MOTOROLA

-

LM285
LM385

SEMICONDUCTOR - - - - - -

TECHNICAL DATA

MICROPOWER VOLTAGE REFERENCE DIODES
The LM285/LM385 series are micropower two-terminal bandgap voltage regulator diodes. Designed to operate over a wide
current range of 10 }LA to 20 mA. these devices feature exceptionally low dynamic impedance, low noise and stable operation
over time and temperature. Tight voltage tolerances are achieved
, by on-chip trimming. The large dynamic operating range enables
these devices to be used in applications with widely varying supplies with excellent regulation. Extremely low operating current
make these devices ideal for micropower circuitry like portable
instrumentation, regulators and other analog circuitry where
extended battery life is required.
The LM285/LM385 series are packaged in a low cost TO-226AA
plastic case and are available in two voltage versions of 1.235 and
2.500 volts as denoted by the device suffix (see ordering information table). The LM285 is specified over a - 40"C to + 85"C
temperature range while the LM385 is rated from O"C to +70"C.
The LM385 is also available in a surface mount plastic package
in voltages of 1.235 and 2.500 volts.

MICROPOWER VOLTAGE
REFERENCE DIODES
SILICON MONOLITHIC
INTEGRATED CIRCUIT

Z SUFFIX
PLASTIC PACKAGE
CASE 29
(Bottom View)

N.C. 3
CATHODE 2
ANODE 1

D SUFFIX
PLASTIC PACKAGE
CASE 751
(SO-8)

• Operating Current from 10 }LA to 20 mA
• 1.0%,1.5%,2.0% and 3.0% Initial Tolerance Grades
• Low Temperature Coefficient
• 1.0

n Dynamic Impedance

STANDARD APPLICATION

• Surface Mount Package Available
1.5 V
Battery

i-

+
3.3 k

1.235 V

EQUIVALENT CIRCUIT SCHEMATIC

LM385-1.2

CATHODE

10 k

360 k

Open
for 1.235 V

ORDERING INFORMATION

600 k

Temp.
Device

LM285D-l.2
LM285Z-1.2
LM285D-2.5
LM285Z-2.5

600 k

Range
-40'C
to +85"C

LM385BD-1.2
LM385BZ- 1.2
600 k

500 !l

LM385D-l.2
LM385Z-1.2
LM385BD-2.5
LM385BZ-2.5
LM385D-2.5
LM385Z-2.5

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
5-4

O'Cto
+70'C

Reverse
Breakdown
Voltage

Tolerance

1.235
Volts

±1.0%

2.500
Volts

±1.5%

1.235
Volts

±1,Q%

1.235
Volts

±2.0%

2.500
Volts

±1.5%

2.500
Volts

±3.Q%

LM285, LM385
MAXIMUM RATINGS (TA ~ + 25°C unless otherwise noted)
Rating

Symbol

Value

Unit

Reverse Current

IR

30

rnA

Forward Current

IF

10

rnA

Operating Ambient Temperature Range
LM285
LM385

TA

Operating Junction Temperature
Storage Temperature Range

°c
-40 to +85
o to +70

TJ

+150

°C

Tsta

-65 to + 150

°C

ELECTRICAL CHARACTERISTICS (TA ~ 25°C unless otherwise noted)
LM285-1.2
Characteristic

Reverse Breakdown Voltage

Symbol

Min

Typ

LM385-1.21LM385B-l.2
Max

Min

Typ

Max

IRmin '" IR '" 20 rnA
LM285-1.2/LM385B-l.2
TA ~ Tlow to Thigh (Note 1)
LM385-1.2
TA ~ Tlow to Thigh (Note 1)

1.223
1.200

Minimum Operating Current
TA ~ 25°C
TA ~ Tlow to Thigh (Note 1)

1.235

-

-

-

8.0

1.247
1.270

-

1.223
1.210
1.205
1.192

1.235

-

8.0

-

15
20

-

1.0
1.5
20
25

0.6

-

n

1.235

-

1.247
1.260
1.260
1.273
p.A

IRmin

Reverse Breakdown Voltage Change with Current
IRmin '" IR '" 1.0 rnA. TA ~ +25°C
TA ~ Tlow to Thigh (Note 1)
1.0 rnA '" IR '" 20 rnA. TA ~ +25°C
TA ~ Tlow to Thioh (Note 1)

Unit
V

V(BR)R

-

-

-

-

10
20

-

mV

toV(BR)R

-

Z

-

1.0
1.5
10
20

0.6

-

-

toV(BR)/toT

-

80

-

-

80

-

ppmrC

Wide band Noise (RMS)
IR ~ 100 p.A. 10 Hz '" f '" 10 kHz

n

-

60

-

-

60

-

p.V

Long Term Stability
IR ~ 100 p.A. TA ~ +25°C ± O.l°C

S

-

20

-

-

20

-

ppm/
kHR

Reverse Dynamic Impedance

IR

~

100 p.A. TA

~

-

+ 25°C .

Average Temperature Coefficient
10 p.A '" IR '" 20 rnA. TA ~ Tlow to Thigh (Note 1)

ELECTRICAL CHARACTERISTICS (T A ~ 25°C unless otherwise noted)
LM38S-2.S/LM38SB-2.S

LM285-2.S
Characteristic

Symbol

Reverse Breakdown Voltage
IRmin '" IR '" 20 rnA
LM285-2.5/LM385B-2.5
TA ~ Tlow to Thigh (Note 1)
LM385-2.5
TA ~ Tlow to Thigh (Note 1)

V(BR)R

Minimum Operating Current
TA ~ 25°C
TA ~ Tlow to Thigh (Note 1)

IRmin

Min

Typ

Max

Min

Typ

Max

2.462
2.415

2.5

2.538
2.585

2.5

-

2.462
2.436
2.425
2.400

2.538
2.564
2.575
2.600

V

-

-

-

20
30

-

-

1.0
1.5
10
20

Z

-

0.6

-

-

toV(BR)/toT

-

80

-

-

Wideband Noise (RMS)
IR ~ 100 p.A. 10 Hz '" f '" 10 kHz

n

-

120

-

Long Term Stability
IR ~ 100 p.A. TA ~ +25°C ± O.l°C

S

-

20

-

-

IR

~

100 p.A. TA

~

-

13

13

20
30

-

-

2.0
2.5
20
25

0.6

-

n

80

-

ppmrC

-

mV

toV(BR)R

Reverse Dynamic Impedance

-

2.5

p.A

-

Reverse Breakdown Voltage Change with Current
IRmin '" IR '" 1.0 rnA. TA ~ +25°C
TA ~ Tlow to Thigh (Note 1)
1.0 rnA '" IR '" 20 rnA. TA ~ +25°C
TA ~ Tlow to Thioh (Note 1)

Unit

+25°C

Average Temperature Coefficient

20 p.A '" IR '" 20 rnA. TA ~ Tlow to Thigh (Note 1)

Note: t. Tlow = - 4DoC for LM285-1.2. LM285-2.5
= DOC for LM385-1.2. LM385B-l.2. LM385-2.5. LM385B-2.5

20

-

p.V
ppm/
kHR

Thigh = + 85°C for LM285-1.2. LM285-2.5
= + 70°C for LM385-1.2. LM385B-l.2. LM385-2_5. LM385B-2.5

MOTOROLA LlNEARIiNTERFACE ICs DEVICE DATA
5-5

120

LM285, LM385
TYPICAL PERFORMANCE CURVES FOR LM285-1.2/385-1.2/3858-1.2

FIGURE 1 -

FIGURE 2 -

REVERSE CHARACTERISTICS

REVERSE CHARACTERISTICS

100

>'

E

10

w

1 10

'"

~

i3'"

Z

~w

>-

i3

'"
'"

~

1.0

=

E

=-i'A

V

40°C

TA

/

0.8 _

TA

0.6

:. 0.4

l0.2

4.0

~

2.0

'"

r--- -

ffi
;;;:-

1.2

0.1

-

750

~ 625

~

+25°c

I/J

~""

TA

1.0
IR. REVERSE CURRENT 1m AI

500

~

375

~

250

z

-40°C

10

100

?

--

0

>

'"
'"w

1.230

~

f(

'"

TA

~

~

100,.LA

1.240

'"
i3

----

I'--

~ 1.220

+85°C

1.210

1.0
10
IF, FORWARD CURRENT ImAI

-50

100

-25

0
25
50
75
TA, AMBIENT TEMPERATURE lOCI

FIGURE 6 -

NOISE VOLTAGE

1.50
1.25

--- r--i'

2: 1.00
>-

~ 0.75

100

125

RESPONSE TIME

0-:-

/'-..

Inpul

/

100 k

./

>-

:::>

~

~

TEMPERATURE DRIFT

IR

w

vV'

FIGURE 5 -

875

0.1

FIGURE 4 -

2:

"I;,

-

~

1.250

L~1114~jl

~

+85°c

II
0.01

FORWARD CHARACTERISTICS

~ +25°C

~

- 2.0

IIIIIII
0.01

0

1.4

IIIIIII

~ 1.0

w

'"'"

0.4
0.6
0.8
1.0
VIBRI. REVERSE VOLTAGE IVI

1.2

o

--

TA

>

'

>

,/

TA
6.0

0

;;".

If'

o

FIGURE 3 -

~~
'"
~

.......-

+ 25°C
A'

TA
0.1

+ 85°C

8.0

00.50

\

0.25

o

DUT~

~PUI

=

r--

1\

'\

2: 10

125

>-

o
10

100

1.0 K
f, FREQUENCY IHzl

10 K

lOOk

~

5.0

;;;

0

0.1

0.2

0.3

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

5-6

0.6
0.7
I, TIME Im'l

0.8

0.9

1.0

1.1

LM285, LM385
TYPICAL PERFORMANCE CURVES FOR LM285·2.5/385·2.51385B·2.5

FIGURE 7 - REVERSE CHARACTERISTICS

FIGURE 8 - REVERSE CHARACTERISTICS

100

>

.E 10
w

'"~

1

1

8.0

:I:

U

10

TA = +85'C

W

'"i:§

=>

u

w

-

ffi

4.0
::l
a:

. / ./

+ 25'C

0.1

o

~

40'C

TA

~~

0

0.5

1.0
1.5
2.0
2.5
VI8R). REVERSE VOLTAGE IV)

0.01

3.0

0.1

2.520

>
;:;;

~

~ 1.0

TA

~
~

0.4

t-'"

I-"

r"'

I--f--

I--

=

l0.2

TA

o

0.01

~

=

t-

~ 2.490
!!;!
~ 2.480

+B5'C

= l00pA

-- I"'-

>



=

0.8

c

III

1.0
10
IR, REVERSE CURRENT ImA)

FIGURE 10 - TEMPERATURE DRIFT

1.2

g

TAI1~

:f-2.0

FIGURE 9 - FORWARD CHARACTERISTICS

!:;

V

TA = +25'C ....

~
a: 2.0


0

c- -

;;;; 4.0

.
w

1°

IJ5 0 C_

I

'":z

3.0

~ 2.0

-

S

>°1.0
'""

75°C

---

S.O

'"

olc- -

......-

>

S 9.0

.sw

25°C

-------

0
> -I
;;;;
w
-2

10

I

-

+1

------ /'

-55°C

I--

75°C

I--

.....-

V

~

---=

o

OOC- I--

I-- I--

1.0

2.0

25°C

3.0
4.0
5.0
6.0
7.0
lout. OUTPUT CURRENT (rnA)

S.O

r-9.0

10

FIGURE 6 - CHANGE IN V out versus TEMPERATURE
(NORMALIZED TO Vout /iii Vin = 15 V)

1.2 5
I. Vin = 5.0 V _
1.20

§

~ 1.1 0

ffi~ 1.05
ff3

--

...

1.00

.s

lout=2mA

>
;;;; -2.0

....-:;

........

~ -4.0

;2

...........

u

'"

.....

::::::-.. 2

~ .......

l#

w

..............

~

-6.0 / '

",,'

>'g -8.0

'5

30.95

-1

-10

0.9 0
0
-75

2. Vin'" 15 V

s

.s< 1.1 5

-12
-50

-25

~

~

~

I~

100

I~

-14
-75

I~

-50

~

-25

TA. TEMPERATURE (OC)

FIGURE 7 - CHANGE IN Vout versus TEMPERATURE
(NORMALIZED TO TA = 10. Vin = 15 V. lout = 0 rnA)

4.0
2.0

s

.s

•

>0 -2. 0

;;;;
~

z

~

-4.0

-6.0

J -~.

~~
~

~~

~~
~

"
~

\'

0

 ±6%

• Wide Input Voltage Range: Vref

+ 2.5 V to 40 V

• Low Quiescent Current: 1.25 mA Typical
• Temperature Coefficient: 10 ppmrC Typical
• Low Output Noise: 12 /LV p-p Typical
• Excellent Ripple Rejection: > 80 dB Typical
U SUFFIX
CERAMIC PACKAGE
CASE 693

TYPICAL APPLICATIONS
• Voltage Reference for 8 - 12 Bit D/A Converters
• Low TC Zener Replacement
• High Stability Current Reference

PIN ASSIGNMENTS

• MPU D/A and AID Applications

FIGURE 1 - VOLTAGE OUTPUT 8-BIT DAC USING MC1404Ul0

+5.0
1J
14

MSB

5.0 k
MC1404U10

MC1408

15

0.05

ORDERING INFORMATION

S.Ck

PACKAGE Ceramic DIP

":"

Device

:CMOS
or TTL

Temperature Range

5.0 Volts

Inputs

MC1504U5
MC1404U5
MC1404AU5

10

11

- 55°C to + 125°C
O°C to +70°C
O°C to +70°C

6.25 Volts
0<0
+10Volts

16

12
LSB

MC1504U6
MC1404U6
MC1404AU6

- 55°C to + 125°C
O°C to +70°C
O°C to + 70°C

10 Volts
-15

MC1504Ul0
MC1404Ul0
MC1404AU10

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

5-12

- 55°C to + 125°C
O°C to +70°C
O°C to + 70°C

MC1404,A, MC1504
MAXIMUM RATINGS
Symbol

Value

Input Voltage

Rating

Vin

40

Unit
V

Storage Temperature

TstQ

-65 to +150

°C

Junction Temperature

TJ

+175

Operating Ambient Temperature Range
MC1504
MC1404,A

TA

°C
°C

-55to +125
o to +70

ELECTRICAL CHARACTERISTICS (Vin = 15 Volts TA = 25°C and Trim Terminal not connected unless otherwise noted)
MC1404,A
Symbol

Characteristic
Output Voltage
(10 = 0 mAl

MC1504

Min

Typ

Max

Min

Typ

Max

4.95
6.19
9.9

5.0
6.25
10

5.05
6.31
10.1

4.95
6.19
9.9

5.0
6.25
10

5.05
6.31
10.1

MC1404U5, AU5/MC1504U5
MC1404U6, AU6/MC1504U6
MC1404Ul0, AU10/MC1504Ul0

-

Output Voltage Tolerance

±0.1

±1.0

±0.1

±1.0

-

-

-

Output Trim Range (Figure 10)
(Rp = 100 kO)

AVTRIM

Output Voltage Temperature Coefficient,
Over Full Temperature Range
MC1404, MC1504
MC1404A

AVO/AT

Maximum Output Voltage Change
Over Temperature Range
MC1404U5, MC1504U5
MC1404AU5
MC1404U6, MC1504U6
MC1404AU6
MC1404Ul0, MC1504Ul0
MC1404AU10

AVO

±6.0

-

-

-

10
10

-

-

-

-

-

-

-

-

-

50

%
%

55
mV

-

Regline

2.0

Re910ad

-

Quiescent Current
(10 = 0 mAl

IQ

Short Circuit Current

Isc

Long Term Stability
Note 1: Includes thermal effects.

-

-

-

-

62

-

-

99
-

6.0

-

2.0

6.0

mV

-

10

-

-

10

mV

-

1.2

1.5

-

1.2

1.5

mA

-

20

45

-

45

-

-

-

25

25

-

-

-

-

= 0 mAl

Load Regulation (1)
(0'" 10'" 10 mAl

DYNAMIC CHARACTERISTICS (Vin

mA
ppm/l000 hrs

= 15 V, TA = 25°C all voltage ranges unless otherwise noted)
MCI404,A
Symbol

Min

Typ

MCI504
Max

Min

-

-

Unit
/LS

12

-

/LV

-

-

-

0.15
0.2

-

70

80

-

-

50

Output Noise Voltage - P to P
(Bandwidth 0.1 to 10Hz)

Vn

-

12

Small-Signal Output Impedance
120 Hz
500 Hz

ro

-

0.15
0.2

-

70

80

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
5-13

Max

-

ts

PSRR

Typ
50

Turn-On Settling Time
(to ±0.01%)

Power Supply Rejection Ratio

-

40
25

-

Characteristic

-

±6.0

ppm/oC

14
9.0
17.5
11
28
18

Line Regulation (1)
(Vin = Vout + 2.5 V to 40 V, lout

Unit
Volt

Vo

n
dB

MC1404,A, MC1504

TYPICAL CHARACTERISTICS

FIGURE 3 - LINE REGULATION versus TEMPERATURE

FIGURE 2 - SIMPLIFIED DEVICE DIAGRAM

2.5

'> 2.0
oS

V out

z

"

~

R

5.0 k

1.5

~

TRIM

w

.

":::;
R

Vo

3.75 k
6.0 k
8.75 k

5.0V

V

1.0

/'

-'"

~

Vi" = Vref + 2.5VI040V
10UI = OmA

"'\

~ 0,5

6.25 V

1.25 k

10 V

o
-75

FIGURE 4 - OUTPUT VOLTAGE versus TEMPERATURE
MC1404Ul0

-50

-25
+25
+50
+75
TA. AMBIENT TEMPERATURE I'CI

+100

+125

FIGURE 5 - LOAD REGULATION versus TEMPERATURE
0.010

10.04

~
~

~

"~>
....
~

;(

.!'! 0.008
;;';

10,02

10.00

i'--.

,/
9.98
,I

9.9 6

"">=

i

"-

c

"g

::: 9.94

0.006

0.002

I

o
-75

-75 -50 -25
0 +25 +50 +75 +100 +125
TA. AMBIENT TEMPERATURE I'CI

FIGURE 6 - POWER SUPPLY REJECTION RATIO
versus FREQUENCY

-

Load Change 0 to 10 rnA

-

0.004

:?
o

;.7

,/

-50

-25
0
+25
+50
+75
TA. AMBIENT TEMPERATURE I'CI

1.6
1.4

0

;(

oS 1.2

0

I--

~

:: 1.0
0

=>

r

~~~~
-.

HP209A
3VRMS

""

1k

01-

12

OUT

SltN~eto 4
ftil ':'

0.1

~~

r-.

¥'l.3V
-0:' 1111 20VoitsAver

0

-- -

~ 0.8

500jlf

1.0

Vin = 15V

0.6

lout=OmA

:;

~O.4

,~
HP34DDA

10

O. 2

100

+125

FIGURE 7 - QUIESCENT CURRENT versus TEMPERATURE

90

0

+100

o

1000

-75

f. FREQUENCY IkHzl

-50 -25
+25 +50 +75 +100 +125
TA. AMBIENT TEMPERATURE I'CI

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

5-14

MC1404,A, MC1504

FIGURE 9 - VTEMP OUTPUT versus TEMPERATURE

FIGURE 8 - SHORT CIRCUIT CURRENT versus TEMPERATURE
1.0

40

-

~ 35

.s

ffi

~

25

~

20

_b:

....
....

-

- -

O.B

~

r-- r--

U 15

~

~

30
Vin'" 15 V

-

~

0

w
~

0.6

-f--

~

g

r-- r- I--

~

0.4

~

IVTEMP 010 nA

0:.

10

f----

I

~ 0.2

....

L

>

5. 0

o
-75

-75

-50 -25
0 +25 +50 +75 +100 +125
T A. AMBIENT TEMPERATURE lOCI

FIGURE 10 - OUTPUT TRIM CONFIGURATION

-50

-25
+25
+50
+75
T A. AMBIENT TEMPERATURE lOCI

+125

FIGURE 11 - PRECISION SUPPLY USING MC1404

r------------t---0V+

+15 V

12

330

Vin

6

Output

Va
MC1404

Rp
100 k

5
TRIM

0.01 J..tF

5.0.6.25.

Gnd
V in

I

-b

+100

6

Va

10

v

@

1/2 Amp

f-------+---o

MC1404

Output Adjustment

Output Power Boosting
Gnd

The MC14Q4 trim terminal can be used to adjust the output

4

voltage over a ± 6% range. For example, the output can be set to
10.000 V or to 10.240 V for binary applications. For trimming,
Bourns type 3059, 100 kS1 or 200

kn

trimpet is recommended,

The addition of a power transistor, a resistor, and a capacitor
converts the MC1404 into a precision supply with one ampere
current capability. At V+ = 15 V, the MC1404 can carry in excess
of 14 mA of load current with good regulation. If the power
transistor current gain exceeds 75, a one ampere supply can
be realized.

Although Figure 10 illustrates a wide trim range, temperature
coefficients may become unpredictable for trim> ±6.0%.

FIGURE 12 - ULTRA STABLE REFERENCE FOR MC1723 VOLTAGE REGULATOR
Supply

81121

71111

MC1723G
(MC1723L or P)

315)
2141

'-+--......"V'h-,..--o V out
V out =5.0V (
lomax

JO.OOl J.tF

4.7 k

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

5-15

~

°R6scV

R a +4.7k)
~

MC1404,A, MC1504

FIGURE 13 - 5.0 V, 6.0 AMP, 25 kHz SWITCHING REGULATOR WITH SEPARATE ULTRA-STABLE REFERENCE

+10to +30 In

120l'H

+5.0 Out

r-~p-rv--Y-Y"\--t--:~
(R)

(Top View)
Cathode
(I<)

JG SUFFIX
CERAMIC PACKAGE
CASE 693

Anode
(A)

INTERNAL SCHEMATIC
Component values are nominal

[]B

Cathode
Anode{

Cathode (I<)

~

~

N.C. 4

8

r•1~1111
t

Reference
}

Anode

5 N.C.
[li V· )
op lew

_

8~,

0 SUFFIX
PLASTIC PACKAGE
CASE 751
(SOP-S)

ORDERING INFORMATION
Device
TL431 CLP ACLP BCLP
TL431CP, ACP. BCP
TL43tCD ACD BCD
TL431CJG
TL4311LP AILP BILP
TL4311P. AlP. BIP
TL4311D AID BID
TL4311JG
TL431MJG

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

5-17

Temperature
Range

0 0 to + 70°C

Package
TO-92
Plastic
SOP-S

Ceramic
-40' to + S5'C

TO·92
Plastic
SOP-S
Ceramic

to + 125'C

Ceramic

_55'

TL431 , A, B Series
MAXIMUM RATINGS (Full operating ambient temperature range applies unless otherwise noted)
Rating

Symbol

Value

VKA

37

V

Cathode Current Range, Continuous

IK

-100to+150

rnA

Relerence Input Curent Range, Continuous

Irel
TJ

-0.05 to +10

rnA

Cathode to Anode Voltage

Operating Junction Temperature
Operating Ambient Temperature Range
TL431M
TL431I, TL431AI, TL431BI
TL431C, TL431AC, TL431BC

TA

Storage Temperature Range

Tsta
Po

Unit

150

°C
°C

-55 to +125
-40 to +85
to +70

o

Total Power Dissipation @ TA = 25°C
Derate above 25°C Ambient Temperature
0, LP Suffix Plastic Package
P Suffix Plastic Package
JG Suffix Ceramic Package

-65 to +150

°C

W
0.70
1.10
1.25

Total Power Dissipation @ TC = 25°C
Derate above 25°C Case Temperature
0, LP Suffix Plastic Package
P Suffix Plastic Package
JG Suffix Ceramic Package

W

Po
1.5
3.0
3.3

RECOMMENDED OPERATING CONDITIONS
CondltionNalue
Cathode to Anode Voltage
Cathode Current
THERMAL CHARACTERISTICS
Symbol

0, LP Suffix
Package

PSufflx
Package

JGSuffix
Package

Thermal Resistance, Junction to Ambient

RaJA

178

114

100

Thermal Resistance, Junction to Case

ROJC

83

41

38

Characteristics

Unit

°CIW
°CIW

ELECTRICAL CHARACTERISTICS (Ambient temperature at 25°C, unless otherwise noted.)
TL431 I

TL431M
Characteristics

Symbol

Relerence Input Voltage (Figure 1)
VKA = Vrel, IK = 10 rnA
TA = +25°C
TA = Tlowto Thiah (Note 1)
Reference Input Voltage Deviation Over
Temperature Range (Figure I, Notes 1,2,4)
VKA = Vrel,IK = 10 rnA
Ratio of Change in Relerence Input Voltage
to Change in Cathode to Anode Voltage
IK = lOrnA (Figure 2), ~ VKA = 10 V to Vref
~VKA=36Vto 10V

Vrel

Reference Input Current (Figure 2)
IK=10mA, Rl =10k,R2=~
TA = +25°C
TA = Tlowto Thiah (Note 1)
Relerence Input Current Deviation Over
Temperature Range (Figure 2, Note I, 4)
IK = 10 rnA, Rl = 10 k, R2 = ~

~Vrel

TL431C

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

2.44
2.396

2.495

2.55
2.594

2.44
2.41

2.495

2.55
2.58

2.44
2.423

2.495

2.55
2.567

-

15

44

30

-

V

-

-

7.0

3.0

17

~Vref
~VKA

Unit

mV

mVN

-

-

-1.4
-1.0

-2.7
-2.0

-

-

-1.4
-1.0

-2.7
-2.0

-

1.8

-

4.0
7.0

1.0

3.0

-

-

-

-1.4
-1.0

-2.7
-2.0

-

1.8

-

4.0
6.5

-

1.8

-

-

4.0
5.2

0.8

2.5

-

0.4

1.2

JlA

flA

Iref

~Iref

-

Minimum Cathode Current For Regulation
VKA = Vref (Figure 1)

Imin

-

0.5

1.0

-

0.5

1.0

-

0.5

1.0

rnA

Off-State Cathode Current (Figure 3)
VKA = 36 V, Vref = 0 V

loff

-

2.6

1000

-

2.6

1000

-

2.6

1000

nA

Dynamic Impedance (Figure I, Note 3)
VKA = Vref, ~IK = 1.0 rnA to 100 rnA
I,; 1.0 kHz

t1:kal

-

0.22

0.5

-

0.22

0.5

-

0.22

0.5

Q

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

5-18

TL431 , A, B Series
ELEC"fRICAL CHARACTERISTICS (Ambient temperature at 25°C, unless otherwise noted.)
TL431AI
Characteristics

Symbol

Reference Input Vollage (Figure 1)
VKA = Vref, IK = 10 mA
TA = +25'C
TA = Tlow to ThiQh
Reference Input Voltage Deviation Over
Temperature Range (Figure 1, Notes 1,2,4)
VKA = Vref, IK = 10 mA
Ratio of Change in Reference Input Voltage
to Change in Cathode to Anode Voltage
IK = 10 mA (Figure 2), t.VKA = 10 V to Vref
t.VKA = 36 V to 10 V
Reference Input Current (Figure 2)
IK=10 mA, Rl = 10 k, R2 ==
TA = +25'C
TA = Tlow to Thigh (Note 1)

Min

Typ

TL431AC
Max

Min

TL431B

Typ

Max

Min

Typ

Max

Unit
V

Vref

t.Vref

2.47
2.44

2.495

-

7.0

-

2.52
2.55

2.47
2.453

2.495

-

-

30

-

-

-

2.52
2.537

2.475

2.495

2.515

17

-

3

17

3.0

mVN

t.Vref
t.VKA

mV

-

-1.4
-1.0

-2.7
-2.0

I.B

-

4.0
6.5

O.B

2.5

-

-

-

-

-1.4
-1.0

-2.7
-2.0

-

-1.4
-1.0

-2.7
-2.0

-

I.B

-

3.0
4.0

0.4

1.2

-

1.6

-

4.0
5.2

0.4

1.2

flA

flA

Iref

Reference Input Current Deviation Over
Temperature Range (Figure 2, Note 1)
IK=10mA,Rl =10k,R2==

t.lref

-

Minimum Cathode Current For Regulation
VKA = Vref (Figure 1)

'min

-

0.5

1.0

-

0.5

1.0

-

0.5

1.0

mA

Off-State Cathode Current (Figure 3)
VKA = 36 V, Vref = 0 V

loff

-

2.6

1000

-

2.6

1000

-

0.23

0.5

nA

IZkal

-

0.22

0.5

-

0.22

0.5

-

0.14

0.3

Q

Dynamic Impedance (Figure 1, Note 3)
VKA = Vref, t.IK = 1.0 mA to 100 mA
f,; 1.0 kHz
Note 1:
Tlow

-55'C for TL431 MG
-40'C for TL431 AlP TL431AILP, TL4311P, TL431ILP,
TL4311JG
O'C for TL431 ACP, TL431 ACLP, TL431 CP, TL431 CLP,
TL431CJG, TL431 CD, TL431ACD

+ 125'C for TL431 MJG
+85'C for TL431 AlP, TL431AILP, TL43I1P, TL431ILP,
TL4311JG
+70'C for TL431 ACP, TL431 ACLP, TL431 CP,
TL431CLP, TL431CJG, TL431 CD, TL431ACD

Note 2:
The deviation parameter t. Vref is defined as the difference between
the maximum and minimum values obtained overthefull operating ambient temperature range that applies.

"··r71

Figure

1. Test Circuit for

a

Vref

!

T2

Ambient Temperature

The average temperature coefficient of the reference inputvoltage,
Vref, is defined as:
(
ppm

t.Vref,) xl06
Vref@25 C

t. TA

"Vref --;;c=

=Vref

I n p U t W~V
IK K A

.6..Vref =Vref max

V'efm,"~
TI

VKA

ijf
Figure

p
In U: l

t. Vref x 106
- t. TA (V,ef@ 25'C)

a Vrefcan be positive or negative depending on whetherVrefMin or
Vref Max occurs at the lower ambient temeperature. (Refer to
Figure 6.)
Example: t. Vref = 8.0 mV and slope is positive,

lref

2.

=

Test Circuit for VKA > Vref

t

IK

VKA

R2
vKA = Vref (1
Vref

t

~)

=

Vref@ 25'C o.~O~9~ ~og TA = 70'C

a Vref = 70 (2.495) - 45.8 ppm/'C
Note 3:
t. V
The dynamic impedance Zka is defined a\;Zkal =-----'SA
t.IK
When the device is programmed with two external reSistors, Rl and
R2, (refer to Figure 2) the total dynamic impedance of the circuit is defined as:

1 'I
Zka

=

1 1(
Zka

Figure 3. Test Circuit for loff
,npUI7VKA

~~

~\

I+R2 J

MOTOROLA LlNEARIiNTERFACE ICs DEVICE DATA

5-19

t

Iref. Rl

TL431 , A, B Series
Figure 4. Cathode Current versus
Cathode Voltage
150

1
!z
w
a:
a:

~

Figure 5. Cathode Current versus
Cathode Voltage
800

VKA=Vref
TA=25°C

Input~VKA

100

"'-J I - I
/

!z
w

a: 400
a:
:::>
<>
w
c

50

0

3

0

/
-50

3

I
-1.0

II'

200

./
./

~

/.

-100
-2.0

0
1.0
VKA. CATHODE VOLTAGE M

2.0

V
-200
-1.0

3.0

Figure 6. Reference Input Voltage versus
Ambient Temperature

I

InputW VKA
11K VKA=Vref
Vref
IK=10rnA

~

a:
a:
<>
!:;
a..
;;;

I

:::>

I

VrefTyp = 2495 mV

2.5

..............

2.0

I

2460

I

Vi . !
V
-r--:.:!
Min = ~440 m

2440
2420
2400

-25

0
25
50
75
TA. AMBIENT TEMPERATURE (OC)

100

1.0

a:

0.5

~

10k

o

Figure 8. Change In Reference Input
Voltage versus Cathode Voltage

"-

"

...........

""i'M
Rl

R2

IK

Vref

10

'!!!

-25

K

0
25
50
75
TA. AMBIENT TEMPERATURE (OC)

:[

1k

~
a:

100

8

10

<>

1.0

t5
~

O.

.,/

~

r---.....

~
~

~

"

20
30
VKA. CATHODE VOLTAGE M

100

125

Figure 9. Off-5tate Cathode Current
versus Ambient Temperature

IK=10rnA
TA=25°C

.......

r-- '-

Input~VKA

-55

125

r-...

IK=10mA

<>
zw
a:

w
u.
w

r--

I

-55

3.0

1.5

w

2480

1.0
2.0
VKA. CATHODE VOLTAGE M

<" 3.0
.a.

I

I

o

Figure 7. Reference Input Current versus
Ambient Temperature

Vref Max = 2550 mV

y';--

j

IMin

~ 600 Input~VKA

w
c

~

VKA =Vref
TA=25°C

<"

j
40

~~

./

IV

0.01
-55

-25

./

.,/

.. .
VKA=36V
Vref=OV

~

0
25
50
75
TA. AMBIENT TEMPERATURE rC)

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
5-20

/

,

100

125

TL431 , A, B Series
Figure 10. Dynamic Impedance
versus Frequency

Figure 11. Dynamic Impedance
versus Ambient Temperature

100

0.320

w

TA 25'C
61K 1.0mAlol00mA
loOk

z
«
0

~OUIPUI

g
u

w

10 =('V

0..

'"
'"

50

w
u
z

0.300

w

0.280

n.
~

Gnd

u

-

0.260

'"

1.0
0

>-

~

'"

10k

lOOk
t, FREQUENCY (MHz)

loOM

0.200
-55

10M

-25

Figure 12. Open-Loop Voltage Gain
versus Frequency
iii'

60

z

50

w

C!l

40

0

30

~

1\

>

'"

20

0..

10

Z
w

0

OUlpul

r

B.25k

_,;.

~

230

I'

+

Gnd

V

'" -

0
25
50
75
TA, AMBIENT TEMPERATURE (0G)

-

60

§.

Gnd

w

C!l

0..

0

9

f~~M~'K
9.0 F

/'

_

100

125

Figure '13. Spectral Noise Density

j

C!l

50

80

IK = 10 mA TA = 25°C

3



l.u

~

Input ~E--o Output
jlK


u

OJ
Z

~
en
w

1.0

w
0

OJ

0

100

A VI

12

16

60

I\Slable
A

A
B

B
C

1

40

I
I

20

o

20

100 pF

(~s)

~III

Siable

:c

8.0
1, TIME

100 k

Figure 15. Stability Boundary Conditions

3.0

~

10k

1000 pF

0.01 ~F

O. 1 ~F

CL, LOAD CAPACITANCE

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
5-21

1.0~F

TL431 , A, B Series
Figure 16. Test Circuit for Curve A
of Stability Boundary Conditions

Figure 17. Test Circuit for Curves B, C, and D
of Stability Boundary Conditions

150

150

"f]!}',

V+

TYPICAL APPLICATIONS
Figure 18. Shunt Regulator
V+cr-vvv·-_

Figure 19. High Current Shunt Regulator

___.-___.--c Vout
Al

I

A2

J..
T
I

V+·o---"VVv-_-.__..---o Vout

Al

A2

Vout= (1

Figure 20. Output Control for a
Three-Terminal Fixed Regulator

V+

+~)

Vre!

Figure 21. Series Pass Regulator

f--._-QVout

A2
A2

Vout=

(1 + ~) Vref

Vout=

(1 +~) Vre!

YOU! min = Vre! +Vb.

Vout min = Vre! +5.0 V

Figure 22. Constant Current Source

Figure 23. Constant Current Sink
V+

Isink

I
IS' k = Vref
In
AS

AS

MOTOROLA LlNEARIiNTERFACE ICs DEVICE DATA

5·22

TL431 , A, B Series
Figure 25. SCR Crowbar

Figure 24. TRIAC Crowbar

<>-.--.---..---.--.---{) Vout

V+

Rl

Rl

R2
R2
Vout(trip) = (1 +

-m) Vref
Vout(trip) = ( 1 +

-m) Vref

Figure 27. Single-Supply Comparator with
Temperature-Compensated Threshold

Figure 26. Voltage Monitor

V+

Vout

R4

R2

o---.---~~--o

Vlh = Vref

L.E.D. indicator is 'on' when V+ is betwean the
upper and lower limils.

Vin

Vout
V+

< Vref

Lower Umit = (1 +
UpperUmil=

-m) Vref

(1+~)

> Vref

2.0V

Vref

Figure 29. Simple 400 mW Phono Amplifier

Figure 28. Linear Ohmmeter

38V
330

TI = 330 to B.O n
5.0k
1%

Rj

50k
1%
10kn

B.on

v
1.0kn

v

Vout

Rx
Rx = Vout·

'Thermalloy
THM 6024
Heatsink on LP
Package

n

II Range

56k

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

5-23

TL431 , A, B Series
Figure 30. High Efficiency Step-Down
Switching Converter
150"H@2.OA

Vin = 10VIo2OV

+

TIPI15r--_+-_---1I--JTlTL-._--_-o Vout =5.OV
lou1= I.OA

lOOk

22oo"F

+

4.7k

51k

10

Test
Line Regulation
Load Regulation

Conditions

Results

Vin=IOV to20V,IO=I.OA

53mV

(1.1%)
(0.5%)

Vln=15V,IO=OA tol.OA

25mV

Output Ripple

Vln = 10 V,IO = I.OA

50 mVp_p P.A.R.D.

Output Ripple

Vin=20V,IO=I.0A

100 mVp_p P.A.R.D.

Efficiency

Vin=15V,IO=I.OA

82%

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

5-24

Data Conversion

In Brief ...
Page

Motorola's line of digital-to-analog and analog-to-digital
converters includes several well established industry
standards, and many are available in various linearity
grades so as to suit most any application.
The AID converters have 7 and 8-bit flash converters
suitable for NTSC and PAL systems, CMOS has 8-bit to
10-bit converters, as well as other high speed digitizing
applications.
The DIA converters have 6 and 8-bit devices, video
speed (for NTSC and PAL) devices, and triple video DAC
with on-board color palette for color graphics applications.

A-D Converters
CMOS ....................................... 6-2
Bipolar ....................................... 6-2
D-A Converters
CMOS ....................................... 6-3
Bipolar ....................................... 6-3
A-D/D-A Converters
CMOS - For Telecommunications. . . . . . . . . . . . . .. 6-3
Package Overview ............................... 6-4
Index ........................................... 6-5
Data Sheets ..................................... 6-6

Data Conversion
The line of data conversion products which Motorola offers
spans a wide spectrum of speed and resolution/accuracy.
Features, including bus compatibility, minimize external parts
count and provide easy interface to microprocessor systems.
Various technologies, such as Bipolar and CMOS, are utilized

to achieve functional capability, accuracy and production
repeatability. Bipolar technology generally results in higher
speed, while CMOS devices offer greatly reduced power
consumption.

A·D Converters

CMOS
8

MC145040

±1/2LSB

MCl45041

lOllS

OtoVDD

-40to +85
(Suffix 2 devices)

P1738
FN1775

Requires external
clock, ll-Ch MUX

-40to+125
(Suffix 1 devices)

DW1751D

Includes intemal
clock, ll-Ch MUX

-40to+85

PI710
FN1776

liP compatible
ll-Ch MUX S.A.R.

+3.010 +18

-5510+125
-4010+85

U620
P/648

Compatible wHh
MC1408 S.A.R.
8-blt D-A Converter

FNI7n

+5.0±10%

20 lIS

MCl4442
MC14549B1
MC14559B

Successive Approximation
Registers

Triple
8-Bit

MC44250

aSB

15MHz

1.6t04.6V

+5.0± 10%

Oto+70

10

MCI45050

±1 LSB

21 lIS

OtoVDD

+5.0±10%

-4010+125

MCI45051

P1738
Requires exlemal
DW1751D clock, l1-Ch MUX
Includes Intemal
clock, ll-Ch MUX

44 lIS

MCI45053

P/646

D1751 A

±0.5%
Full Scale

300 lIS

Variable
w/Supply

+5.0 to +18

MCI4433

±0.05%
± 1 Count

40ms

±2.0V
±200mV

+5.0 to +8.0
-2.8to-8.0

7

MC10321

± 112 LSB

40ns

010 2.0Vpp +5.0 and
Max
-3.010-8.0

8

MC10319

±1 LSB

8-10

MCI44431

MCI4447
3-112 Dlgil

3 separate video
channels

-40 to +85

Includes Inlemal
clock, 5·Ch MUX

P/648
liP compalible,
DW1751G single slope,
6-ChMUX

P1709
Dual slope
DW1751E

Bipolar
Oto +70

P1738
Video speed, Gray
DW1751D code, TIL outputs
U623
Video speed flash
P1709
converter, intemal
DW1751F Gray code,
Die Form TIL Outputs

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

6-2

D-A Converters
Max
AccurIIcy

FIetIolutlon
(BIte)

@25'C
Device

Me.

MCl44110

-

Temperature

Settling

Range

(±1I2LS8)

SUpplies
(V)

-

+5.0 to +15

o to +85

TIme ..

('C)

Suffix!
Package

<

»'

,

Comments

CMOS
6

Pfl07

Serial input, hex DAC,
6 outputs

DWfl51D

P/646

MCl44111

Serial input, quad DAC,
4 outputs

DWfl51G
Bipolar
8

DAC-08

±1 LSB

150ns

±4.5to±18

oto +70

EO, H0I620
CP, HP, EP/648
CD, EDfl51B

High speed multiplying

Multiplying

±1/2LSB

MC1408

± 1/4LSB

135ns

± 112 LSB

300 ns Typ

MC1508
4x3

MC10320

+5.0,

Oto +75

L8I620, P8I648

-5.0to-15

-55 to +125

L8/620

±1/4LSB

3.0ns

+5.00r±5.0

Oto +70

U733

± 112 LSB

5.0ns

+5.0,-5.2

-40to +85

P/649

MC10320-1
8

MC10322

125 MHz color
graphics triple DAC
90 MHz Color

MC10324

TIL 40 MHz minimum
ECl 40 MHz minimum

-5.2

A-D/D-A Converters

CMOS - For Telecommunications
13

MC145402

13

62.5 liS

±3.28 V
peak

±5.0to 6.0

-40 to +85

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
6-3

Ll620

Digital signal
processing (e.g.,
echo cancelling,
high speed modems,
phone systems
with conferencing)

Data Conversion Package Overview

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

6-4

A-D Converters
Device

Function

MC10319
MC10321

High Speed 8-Bit Analog-to-Digital Flash Converter .................. 6-27
High Speed 7-Bit Analog-to- Digital Flash Converter ................. 6-45

Page

D-A Converters
DAC-Da
MC140a
MC150a
MC10322
MC10324

High Speed 8-Bit Multiplying D-to-A Converter ....................... 6-6
Eight-Bit Multiplying Digital-to-Analog Converter ..................... 6-15
Eight-Bit Multiplying Digital-to-Analog Converter ..................... 6-15
8-Bit Video DAC with ECL Inputs .................................. 6-63
8-Bit Video DAC with ECLInputs .................................. 6-78

RELATED APPLICATION NOTES
App Note

Title

Related Device

EB-51

Successive Approximation BCD A-to-D Converter ................. MC1408, MC1508

AN702

High Speed Digital-to-Analog and Analog-to-Digital
Techniques ................................................ General Information

AN926

Techniques for Improving the Steeling Time of a DAC and
Op Amp Combination ....................................... Various

MOTOROLA LINEAR/INTERFAcE ICs DEVICE DATA
6-5

MOTOROLA

-

DAC-OS

SEMICONDUCTOR - - - - - -

TECHNICAL DATA

HIGH SPEED 8·BIT MULTIPLYING D·TO·A CONVERTER
The DAC·08 series is a monolithic 8-bit high speed multiplying digital-toanalog converter, capable of settling to within 112 LSB (0.19%) in 85 ns.
Monotonic multiplying performance is retained over a wide 40-to-1 reference
current range. Full scale and reference currents are matched to within 1 LSB,
therefore eliminating the need for full scale trim in most applications.
Dual complementry current outputs with high voltage compliance provide
added versatility and allow differential mode of operation to effectively double the peak-to-peak output swing. In many applications, output current-tovoltage conversion can be accomplished without requiring an external op
amp. Noise-immune inputs permit direct interface with TTL and DTL levels
when the logic threshold control, VLC, (Pin 1) is grounded. All other logic
family thresholds are attainable by adjusting the voltage level of Pin 1. Performance characteristics are virtually unchanged over the entire ±4.S V to
± 18 V power supply range. Power consumption is typically 33 mW with
± 5.0 V supplies.
The DAC-08 is available in several versions, with nonlinearity as tight as
± 0.1% (± 1/4 LSB) over temperature. All versions are guaranteed monotonic
over 8 bits. For an extra margin of performance, Motorola utilizes thin-film
resistors permitting very accurate resistive values which are extremely stable
over temperature.
High performance characteristics along with low cost, make the DAC-08
an excellent selection for applications such as CRT displays, waveform generation, high speed modems, and high speed analog-to-digital converters.
•
•
•
•
•
•
•

Fast Settling Time - 85 ns
Full Scale Current Pre matched to ± 1 LSB
Nonlinearity Over Temperature to ±0.1% Max
Differential Current Outputs
High Voltage Compliance Outputs - 10 V to + 18 V
Wide Range Multiplying Capability
Inputs Compatable With TTL, OTL, CMOS, PMOS, ECL, HTL

•
•
•
•

Low Full Scale Current Drift
Wide Power Supply Range ;;4.5 V to ± 18 V
Low Power Consumption
Thin-Film Resistors

HIGH SPEED
a-BIT MULTIPLYING D-TO-A
CONVERTER
SILICON MONOLITHIC
INTEGRATED CIRCUIT

P SUFFIX
PLASTIC PACKAGE
CASE 648

QSUFFIX
CERAMIC PACKAGE
CASE 620

Threshold Control
IVLe!

1

16

lout

2

15

VREFI-)

"

VREF(+)

12

B8ILSB)

Compensation

"
VREFI+)

B8ILSB)

2

VREF(-)

J

Campen.

4

• Low Cost

- ,_ _ _.........
' B1 IMSB)

V+

D SUFFIX
PLASTIC PACKAGE
CASE 751B
(SO-1S)

EQUIVALENT CIRCUIT
(MSBI
(LSB)
VLC B1 B2 B3 B4 B5 B6 B7 B8

(Top View)

1

4
"'-'out

Device

1S
Compensation

V-

DAC-OBHO

±O.l%

Ceramic

OAC-OBEO

±O.19%

I Ceramic

DAC-OBCD

±O.39%

DAC-08ED

±O.19%

DAC-OBHP

±D.1%

DAC-OBEP

±O.19%

DAC-08CP

±D39%

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
6-6

ORDERING INFORMATION
Temperature
Range
Nonlinearity
Package

DOC to +70"C

~
~
I Plastic

I
I

Plastic
Plastic

OAt-Os
MAXIMUM RATINGS (TA = 25'C unless otherwise noted)
Symbol

Value

Unit

V+ Supply to V- Supply

Vs

36

V

Logic Inputs

-

V- to V- Plus 36

V

Rating

Logic Threshold Control

VLC

V-to V+

V

Analog Current Outputs

'out

See Figure 7

mA
V

Reference Input (V14, V15)

Vref

V-to V+

VrellOI

± 18

V

Reference Input CUrrent (114)

'ref

5.0

mA

Operating Temperature Range

TA
Tstg

Oto,70

'C

Storage Temperate

-65to+150

'C

Power Dissipation
Derate above 100°C

Po
RaJA

500
10

mW
mWfC

Reference Input Differential Voltage (V14 to V15)

ELECTRICAL CHARACTERISTICS (Vs = ±15 V, Iref = 2.0 mA, TA = O'C to 70°C, unless otherwise noted)
DAC-OSH

Characteristic

DAC-oae

DAC-08C

Symbol

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

Unit

8

8

8

8

8

8

8

8

8

Bits

Monotonicity

-

B

B

B

8

B

8

8

8

Bits

Nonlinearity, TA = DOG to 700 e

NL

%FS

ts

-

±a.39

Settling Time to ± 1/2 LSB
(All Bits Switched On or Off
TA = 25'CI Figure 241Note 11

-

-

8

85

-

35
35

--

±10

-

Resolution

Propagation Delay, TA = 25°C (Note 1)
Each Bit
All Bits Switched

tPLH
tpHL

Full Scale Tampco

TCIFS

-

Output Voltage Compliance
Full Scale Current Change
< 1/2 LSB,
Rout> 20 MQ Typ.

VOC

-10

Full Range Current
IVrel = 10.000 V;
Rt4, R15 = 5.000 kfl
TA = 25'C

IFR4

1.9B4

Full Range Symmetry IIFR4 -IFR21

IFRS

Zero Scale Current

IZS

-

Output Current Range
V-:-5.0V
V-=-B.OVto-1BV

IOR1
IOR2

0
0

Logic Input Levels IVLC = 0 VI
Logic "0"
Logic "1"

VIL
VIH

2.0

Logic Input Levels IVLC = 0 VI
Logic "0"
IVin = -10 V to +O.B VI
Logic "1"
(Vin '" +2.0 V to + 18 VI

-

-

±a.1

B5

-

35
35

-

1.99

2.04

1.94

1.94

±a.5

±4.0

±8.0

1.0

-

±1.0

0.1

0.2

2.0

-

-

2.1
4.2

0
0

-

2.1
4.2

-

0.8

-

-

-

0.8

2.0

-

-10

-

-2.0

-10

ns

ns

-

ppmfC

+18

V

1.99

2.04

mA

±2.0

±16.0

0.2

4.0

I1A
I1A

0
0

-

2.1
4.2

-

-

O.B

2.0

-

-2.0

-10

0.002

-

mA

V

-

I1A

VTHR

-10

Reference Bias Current

115
di/dt

IS

-

2.000

Logic Threshold Range, Vs '" ± 15 V

Note 1. Parameter

-10

1.992

0.002

Power Dissipation
VS=±5.0V, Irel= 1.0 mA
Vs = ±5.0 V, - 15 V, Irel = 2.0 rnA
Vs = ± 15 V, Iref: 2.0 mA

±10

+18

-10

-

VS: ± 15 V,lrel= 2.0 mA

-

-

-10

VS: i5.0 V, - 15 V, Ire!: 2.0 rnA

35
35

-

-

+1B

IH
VIS

Power Supply Current
Vs = ±5.0 V,lrel = 1.0 mA

-

-

-2.0

Power Supply Sensitivity
IIrel= 1.0 mA
V-=-4.5Vto 18V
V- = - 4.5 V to -lB V

85

±10

-

Reference Input Slew Rate
Figure 19 (Note 11

-

-

IlL

Logic Input Swing, V- '" -15 V

-

-

±a.1g

10

-

0.002

10

+1B

-10

-

-

-

+18

-10

+13.5

-10

-

+13.5

-10

-

+13.5

V

-

-1.0

-3.0

-1.0

-3.0

-3.0

I1A

-

8.0

-

-

-1.0

B.O

-

8.0

-

mAi\lS

PSSIFS+
PSSFS-

-

±a.0003
±a.002

±a.01
±a.01

-

iO.0003
±a.002

±a.01
±a.01

-

±a.0003
±a.002

±a.o1
±a.Ol

1+
11+
11+
1-

-

2.3
-4.3
2.4
-5.4
2.5
-6.5

3.8
-5.B
3.8
-7.8
3.B
-7.8

-

2.3
-4.3
2.4
-6.4
2.5
-6.5

3.8
-25.8
3.8
-7.8
3.8
-7.8

-

2.3
-4.3
2.4
-6.4
2.5
-6.5

3.B
-5.8
3.B
-7.8
3.8
-7.8

-

33
10B
135

4B

33

4B

108
135

136
174

33
108
135

136
174

-

10
+18

V

%/%

Po

136
174

---

not 100% tested; guaranteed by design.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
6-7

-

-

--

mA

mA

4B

DAC-08

TYPICAL PERFORMANCE CURVES
FIGURE 1 - FULL SCALE CURRENT versus
REFERENCE CURRENT

FIGURE 2 - REFERENCE AMP
COMMON MODE RANGE
3.2

5.0

AliiSits "On.!

f--:

2.8

E.

....

I

3.0

:=

2.0

....
=>

/"

V

5

~

/'

1.0

o /'
o

TA_t Tmin to Tmax

.A

4.0 I - - TA=tmintolTmax
;;t
All Bit' "On"

;;t 2.4

/' \

E.

....

limit tor
V-=-ISV

/'

!

V- = -5.0 V

V+=+ISV

I

I

IREF = 2.0 mA

1.6

~

/" l"limitfor
~- = -SiO V

V-=-IISV
2.0

1.2

0

0.8

V

IREF

I

~ 11.0 mA

-

I

0.4

-

IREF ~ 1.2 mA

o
1.0

2.0
3.0
IREF' REFERENCE CURRENT (mA)

4.0

-14

5.0

-10

-6.0

-2.0

2.0

6.0

10

14

18

VIS, REFERENCE COMMON MOOE VOlTAGE (V)
NOTE: Positive Common Mode Range is Always (V+l-l.5 V

FIGURE 3 - REFERENCE INPUT FREQUENCY RESPONSE
6.0
4.0
2.0

-

6

-4.0

~

-6.0

..

k~
V

400

\

" I"

VR1S=OV

~ -2.0

....

Rlt RIIS = \
RL.;;;soon
AII 18it' "~n"

FIGURE 4 -.LSa PROPAGATION DelAY versus IFS
500

>-

1\

~ 300

o

\2

z

o

>=

1\.1

\

~ -8.0

1\

-10

C1i 200

\

i

f\

~

I LSS - 61 nA

l"-

100

I LSB = 7.8

-12

o

-14
0.1

0.2

0.5

1.0

2.0

5.0

0.005 om

10

0.02

f, FREQUENCY (MHz)
Curve 1 Curve 2 -

~A

II 11
1
0.05 0.1
0.2
0.5 1.0
2,0
IFS, OUTPUT FULL SCALE CURRENT (mA)

5.0

10

Cc = 15 pF. Vin = 2.0 V pop Centered at +1.0 V (large-Signal)
Cc = 15 pF. Vin = 50 mV pop Centered at +200 mV (Small-Signal)

FIGURE 5 - LOGIC INPUT CURRENT versus
INPUT VOLTAGE

FIGURE 6 - VTH - VLC versus TEMPERATURE

8.0

2.0
1.8

;;t

....3

Itl
....

~
;;;

;;;
~

0

9

~
%

G

to

o

1.4
1.2

==- 1.0

4.0

u

:--

1.6

6.0

:!;'

I

-12

I
-4.0

r--

0.8
0.6
0.4
0.2

I

-8.0

---

4.0

8.0

12

16

20

-SO

LOGIC INPUT VOLTAGE (V)

-25

25
SO
TEMPERATURE (DC)

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

6-8

75

100

125

DAC-08

TYPICAL PERFORMANCE CURVES
FIGURE 7 - OUTPUT CURRENT versus
OUTPUT VOLTAGE
(Output Voltage Compliance)
3.2

«
g

2.4

i

2.0

~

g

All

r--- -

2.8

TA

=Tmin to Tmax

1

I

I

I

16
12

~

g

4.0

....
=>
....=>
'"

-4.0

«

I
lR!F = 1.0 ~A_
I

I

co

8.0

~

1

1.2
0.8

I

IR[F = 2.0 rnA

V-=-5.0V

I

1.6

OUTPUT VOLTAGE COMPLIANCE
versus TEMPERATURE

20

6~ts "On" I

V-=-15V

FIGURE 8 -

>

~

I

IREF = 0.2 rnA - -

0.4

-8.0
-12

-10

-14

-6.0

FIGURE 9 1.4

i
....=>
....=>
'"

10

14

18

-50

81TTRANSFER CHARACTERISTICS

-25

FIGURE 10 -

25
50
TEMPERATURE (OCI

75

100

125

POWER SUPPLY CURRENT versus V+

80

I
t-

1.2

«g

-2.0
2.0
6.0
OUTPUT VOLTAGE IVI

IREF = 2.0 rnA
61

1.0

7.0

«
.s
....

6.0

~

50

-

All

slts "Hi9Ih" or ,.low"

1-

z

0.8

~ 4.0
0.6

62

~

U)

3,0

1+

a:

0.4
V

0.2

15 V

YI

~

63
V -

1.0

64

5.0 V

~

If'

2.0

o

65
-12-10-8.0-6.0-4.0-2.00 2.04.06.08.0 10 12 14 16 18
LOGIC INPUT VOLTAGE (VI

o

2.0

4.0

6.0
8.0
10
12
14
V+. POSITIVE POWER SUPPLY IVdcl

16

18

20

NOTE: 81-88 have identical transfer characteristics. Bits are fully switched
with less than 1/2LSBerror,atiess than ±10Q mV from actual
threshold. These switching points are guaranteed to lie between
0.8 V and 2.0 V over operating temperature range (VLC 0 VI.

=

FIGURE 11 -

FIGURE 12 - POWER SUPPLY CURRENT
versus TEMPERATURE

POWER SUPPLY CURRENT versus V-

8.0

8.0

All Bits "High" or ''low

Bits May Be "High" or "low"

«
g
....

~

7.0
6.0
5.0

~

4.0

=>
a:

'"

3.0

~

2.0

;;

n--

1- with IREF = 2.0 mA

I.

1

«
g
....
z

6.0

a:
a:

5.0

~

4.0

a

1- with IREF = 1.0 rnA

I

1- with IREF - 0.2 mA_

5l

3.0

~

2.0

a:

'1+

1.0

-2.0

-4.0

-6.0 -8.0 -10 -12 -14 -16
V-. NEGATIVE POWER SUPPLY (Vdc)

-18

7.0

IREF - 2.0 mA

V-=-15V

V+-+15V

1-

1+

1.0

-20

-50

-25

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

6-9

25
50
75
TEMPERATURE (0C)

100

125

DAC-08

BASIC CIRCUIT CONFIGURATIONS
FIGURE 13 - RECOMMENDED FULL SCALE
ADJUSTMENT CIRCUIT

FIGURE 14 - POSITIVE LOW IMPEDANCE
OUTPUT OPERATION

Low T.C.
4.5 k

+10V

14
DAC-08

39 k
10k
Pot

IFR = 255 IREF
256
~·1.0V

If complementry output {Negative Logic DACI operation IS
desIred, connect inverting Input of ap amp 10
(Pm 2) and
ground 10 (Pm 4)

iQ

FIGURE 15 - NEGATIVE LOW IMPEDANCE
OUTPUT OPERATION

FIGURE 16 - BASIC POSITIVE REFERENCE
OPERATION
.
MSB
B2

84

B6

LSB
B8

10

DAC-OB

IFR=~IREF

R15 VREF'-;:.-.:.r-+-TJ - -

256

H

If complementry output (Negative LoQ!p OAC) is desired, connect noninverting input of op amp to 10 (Pin 2) and ground 10
(Pin 4)

0.1
IO+iQ= IFRlor
all logic states

FIGURE 17 - BASIC NEGATIVE REFERENCE
OPERATION
MSB
B2

B4

B6

VLS

~Fl

R15

I O.l~F

For fixed reference. TIL operation. tvpical values are
VREF=+10.oo0V
Cc =O.Ol.F
RREF = 5.000 k
VLC = 0 V (Groundl
R!5 RREF

LSB
B8

=

2 __ Ii)

L -_ _ _---f

I

V+

+VREF
255
IFR=--x - RREF
256

10

DAC-08

V-

I

255
IFR= -VREF
- - x-RREF
256
NOTE: RREF sets full scale current 'FR: R15 is for bias current

cancellation.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
6-10

iQ

DAC-08

BASIC CIRCUIT CONFIGURATIONS

FIGURE 18 -

ACCOMMODATING BIPOLAR REFERENCES

+VREF
+VREF

IREF.

14

RREF
RREF

Vin

~

IREF

~

-r

Rin

14

V,n~

DAc·oa

DAC·Oa
15

R15

(Opt1onan

15
RREF~

R15

+VREF must be above peak positive swing of Vin

Peak Negative Swing of lin

FIGURE 19 -

PULSED REFERENCE OPERATION

+VREF
Optional Resistor
for Offset Inputs
ovJL

9
~

Eo-U

RREF
I

14

.Req =

Rin

Rp

OAC.O,=-

~

15

1

10 4

Typical Values: Rin 5.0 k, +Vin::: 10 V

)

10 2

16

RL

T

RL

6

-=

FIGURE 20 -

-=

EQ.sL

b

No cap .

8ASIC UNIPOLAR NEGATIVE OPERATION

>-

EO 5.000 k
104.,,)-o---,\/V'v-'

IREF 0--_----::---114
2.000 rnA

DAC-OB_

EO

5.000 k

10 2~-o-"Nv--"

al 82 83 84 85 86 B7 BB lornA lornA
Full Range
Half Scale + LSB
Half Scale

Half Scale - LSa
Zero Scale
Zero Scale

+ LSB

1
1
1
0
0
0

1
0
0
1
0
0

1
0
0
1
0
0

1
0
0
1
0
0

1
0
0
1
0
0

1
0
0
1
0
0

1
0
0
1
0
0

1
1
0
1
1
0

1.992
1.008
1.000
0.992
0.008
0.000

0.000
0.984
0.992
1.000
1.984
1.992

EO

EO

-9.960
-5.040
- 5.000
-4.960
-0.040
0.000

-0.000
-4.920
-4.960
-5.000
-9.920
-9.960

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

6-11

OAt-os

BASIC CIRCUIT CONFIGURATIONS

FIGURE 21 -

BASIC BIPOLAR OUTPUT OPERATION

EO
IREF

o--_--~

10 4")--O-~VVIr-"

14

2.000 mA

DAC-OB
_

_ 10.000 k
EO

10 2,L--o-'VV'Ir--'
10.000 k

'10.000 V

, , , , , , ,
,, , , , , , , ,
,
, , , , , , ,
,

B1
PaS Full Range
Pas Full Range -LSB

Zero Scale +lSB
Zero Scale
Zero Scale -LSB
Neg Full Scale tlSB
Neg Full Scale

B2

B3

B4

B5

B6

B7

B8

1

0

0
0

0

0
0

0
0

0
0

0

0

0
0

0
0

0

0
0

0
0

0
0

0
0

0
0

0
0

0

EO
EO
-9.920 +10.000
-9.840 • 9.920
-0080 +0.160
0.000 -0_080
+0,080
0.000
+9.920 - 9.840
-10000 -9.920

FIGURE 22 - OFFSET BINARY OPERATION

10k

+15 V

5.0k

LSB

MSB

,,5 V

2

5.000 k
• 10 V i-:=--~I--'VII\r--1
MC1404UlO 6
5.0 k

DAC-OB

V,

"5V

Pos Full Range
Zero Scale
Neg Full Scale -1 LSB
Neg Full Scale

EO

V-

-15V

, , , , , , , ,
,

B'

B2

B3

B4

B5

B6

1
0
0

0
0
0

0
0

0

0
0

0
0
0

0

a a a

B7

B8

0
0

0

a a

EO
-4.960
0.000
-4.960
-5000

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

6-12

DAC-08

FIGURE 23 - INTERFACING WITH VARIOUS LOGIC FAMILIES

TTL, DTl
VTH = +1.4 V

15 V CMOS. HTL. HNll
VTH = 7.6 V

R

To

+15 V

+10V

9.1 k

6.2 k

6.2 k

5.0 V CMOS
VTH = 2.B V

0.1 "F

3.6 k

0.1 "F

PMOS
VTH = OV

lN414B

VLC

10 V CMOS
VTH = 5.0 V

10K ECl
VTH = -1.29V

1.3k

lN4148

lN414B
1N414B

10k

-5.0 V to - 1 0 V

10 k

3.9 k

'--------*--0-5.2 V
NOTE. Do not el(ceed negative logic input range of OAe
VTH::: VLC + 1.4 V

MOTOROLA LlNEARIINTERFACE ICs DEVICE DATA

6·13

OAt-os

FIGURE 24 - SETTLING TIME MEASUREMENT CIRCUIT

For Turn "On", VL = 2.7 V VL
For Turn "Off", VL =0.7 V

+5.0 V

I

Minimum
Capacitance

Q2

MBD501
Schottky Diodes

2N2222A

~
VLC
0.7 V o-~I--.

Vout
1)( Probe

15kll
RREF
14

+VREF

4

DAC-OB
(OUT)

15
R15

-15V
13

-::-

16

O.Ol"F

O.l"F

Waveforms

I

atVout

~ L+~':
? r OV

_.L--O.4 V
+15V

-15V

NOTE: Oscilloscope bandWidth for settling time measurement
~

V

50 MHz

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

6-14

(Turn "On")
(Turn "Off")

MOTOROLA

-

MC1408
MC1508

SEMICONDUCTOR - - - -__

TECHNICAL DATA

EIGHT-BIT MULTIPLYING
OIGITAL-TO-ANALOG CONVERTER

EIGHT-BIT MULTIPLYING
01 GI TAL-TO-ANALOG
CONVERTER

· .. designed for use where the output current is a linear product
of an eight-bit digital word and an analog input voltage.

SILICON MONOLITHIC
INTEGRATED CIRCUIT

•

Eight-Bit Accuracy Available in Both Temperature Ranges
Relative Accuracy: ±0.19% Error maximum
(MC140BLB, MC140BPB, MC150BLB)

• Seven and Six-Bit Accuracy Available with MC140B Designated
by 7 or 6 Suffix after Package Suffix
• Fast Settling Time - 300 ns typical
•

Noninverting Digital Inputs are MTTL and
CMOS Compatible

.1

• Output Voltage Swing - +0.4 V to -5.0 V
High·Speed Multiplying Input
Slew Rate 4.0 mAIlls

•

L SUFFIX
CERAMIC PACKAGE
CASE 620

• Standard Supply Voltages: +5.0 V and
-5.0 V to -15 V

P SUFFIX
PLASTIC PACKAGE
CASE 648

1

ORDERING INFORMATION

Device

Temperature Ranga

MC140BPB

Oto+75°C

MC140BLB
MC150BLB

FIGURE 1 - D-to-A TRANSFER CHARACTERISTICS

-55 to +1255°C

FIGURE 2 - BLOCK DIAGRAM

";(

.E
IZ

w

a:
a:
::>

01
I-

.

::>

I-

::>

o

.100000000)

1""'".11
INPUT DIGITAL WORD

NPN Current
Source Pair

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
6-15

Package

Plastic
Ceramic
Ceramic

MC1408, MC1508
MAXIMUM RATINGS ITA
Rating

=

+25 0 C unless otherwise noted. I
Symbol

Power Supply Voltage

VCC
Vee

Digital Input Voltage

Value

Unit

+5.5
-16.5

Vdc

V5 thru V12

o to +5.5

Vdc

Applied Output Voltage

Vo

+0.5,-5.2

Vdc

Reference Current

114

5.0

mA

V14,V15

Vcc,Vee

Vdc

Reference Amplifier Inputs

Operating Temperature Range

TA

MC1508
MC140S Series
Storage Temperature Range

°c
-55 to +125
o to +75

Tstg

-65 to +150

°c

..Ym.

ELECTRICAL CHARACTERISTICSWCC = +5.0 Vdc, VEE = -15 Vdc, R14 = 2.0 rnA, MC150BLB: TA
MC140BL Series: TA = Oto + 75°C unless otherwise noted. All digital inputs at high logic level.)
Characteristics
Relative Accuracy IError relative to full scale 101
MC150SLS, MC140SLS, MC140BPB

Figure
4

Settling TIme to with ±1/2 LSB lincludes tPLHJ(TA - + 25°C) (Note 2)
Propagation Delay TIme
TA=+25°C
Output Full Scale Current Drift
Digital Input Logic Levels (MSB)
High Level, Logic ·1"
Low Level, Logic ·0"
Digital Input Current IMSB)
High Level, VIH = 5.0 V
Low Level, VIL = O.S V
Reference Input Bias Current IPin 15)
Output Current Range
VEE = -5.0 V
VEE = - 15 V, TA = 25°C
Output Current
VREF = 2.000 V, R14= 1000 Q
Output Current
(All Bits Low)
Output Voltage Compliance IEr'; 0.19% at TA = + 25°C)
Pin 1 Grounded
Pin 1 Open, VEE below - 10 V
Reference Current Slew Rate
Output Current Power Supply Sensitivity
Power Supply Current
IAII Bits Low)

5
5

Min

Typ

Max

-

-

-

±0.19
±0.39
±0.7S

-

300
30

100

-

-20

-

VIH
VIL

2.0

-

IIH
IlL
115
lOR

Er

ts
tPHL,
tpHL
TCIO

3

3

3
3

3

10lmin)

3

Vo

3
3
3

-

SR Iref
PSRRH
ICC
lEE
VCCR
VEER
PD

All Bits High
VEE = - 5.0 Vdc
VEE =-15 Vdc

-

-

O.B

-

0
-0.4
-1.0

0.04
-O.B
-5.0

0
0

2.0
2.0

2.1
4.2

1.9

1.99

2.1

-

0

4.0

-

-

ns
ns
PPMI"C
Vdc

rnA

IlA
rnA

rnA

-

+4.5
-4.5

IlA
Vdc

4.0
0.5
+ 13.5
-7.5
+5.0
-15

-0.55, +0.4
-5.0, +0.4

-

mNlis

2.7
+22
-13

IlNV

+5.5
-16.5

Vdc

rnA

mW

-

105
190

170
305

-

90
160

-

-

Notes: 1. All current sWitches are tested to guarantee at least 50% of rated output current.
2. All bits switched.
.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
6-16

Unit
%

10

3

6

Power Supply Voltage Range
ITA = + 25°C)
Power Dissipation
All Bits Low
VEE = - 5.0 Vdc
VEE =-15 Vdc

Symbol

=-55°C to +125°C.

-

MC1408, MC1508
TEST CIRCUITS
FIGURE 3 - NOTATION DEFINITIONS TEST CIRCUIT

Typical Values:

"4
14~

R14" R1S" 1 k
Vref = +2.0 V
C = 15 pF

V I and II apply to inputs A 1
thru AS

R14
l-'-o--'W'~....._Vref(+1

A'
A2

The resistor tied to pin 15 is to temperatura compensate the
bias current and may not be necessary for all applications.

A3
Digital
Inputs

A4
A5

-

A6

~

10 ::: K {

Vo

I-'-o----.....___ Output

A7

AS

'0

c

where K

+

~

+

~

+

~:

+

~

+

~

+

:is

+

::s }

== V ref
R'4

RL

=

and AN
"1" if AN is at high level
AN ::: "0" if AN is at low level

FIGURE 4 - RELATIVE ACCURACY TEST CIRCUIT
MSB
r-----~-iA'

,------o-jA2
12·Bit
D·ta-A

,-----o--jA3
r----<>---iA4

Converter

Error (1 v'" 1%)

8-Blt Counter

f-o------+H+-O,,'-l
'0

MC1408 Series

MC1s0B

"

FIGURE 5 - TRANSIENT RESPONSE and SETTLING TIME

·'n

2.4 V

1.4 V
0.4

+2.0 Vdc

VF=r-----::--:F==
tPHL" tpLH C:;;'O n.

0.7 V
SETTLING TIME
• 0 for Figure 6

-Internel

Clamp L.evel

bO-~--~"eo ~-:':::!~:n~~me

ts· 300 nl typical

to.t.1I2LSB

(All bits switched
low~ high)
TRANSIENT 0

+--kl-------+II""R-L.. 60 n

RESPONSE
-100
mV

Vee

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
6-17

UN RL to GNC for
turnoff

me••urement (s •• textl •

pin 4 to GN 0

MC1408, MC1508

TEST CIRCUITS (continued)
FIGURE 6 - REFERENCE CURRENT SLEW
RATE MEASUREMENT
Vee

VEE
dl

I

dt

dV

RL dt

1~90% / 0

-l tt=-'---

2.0 rnA

Slewing

Time

FIGURE 7 - POSITIVE Vret
Vee
.-,;..:1-,,3--,

A 14

== A 15

A1

A2
A3

A4
AS

A6
A7
AS

FIGURE 8 - NEGATIVE V,.t
Vee
13

R14==R15

A1

A2
A3

14

R14

f-"""50>---_~

_ _ _ C-l

Vref

A4
A5
A6
A7
AS

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
6-18

MC1408, MC1508

FIGURE 9 - MC1408, MC1508 SERIES EQUIVALENT
CIRCUIT SCHEMATIC
DIGITAL INPUTS

16
COMPENSATION

15
Vref(-)

3
Vee

OUTPUT

2
GND

RANGE
CONTROL

CIRCUIT DESCRIPTION

The MC1408 consists of a reference current amplifier. an
R·2R ladder, and eight high-speed current switches. For many
applications, only a reference resistor and reference voltage need
be added.
The switches are noninverting in operation, therefore a high
state on the input turns on the specified output current component.
The switch uses current steering for high speed, and a termination
amplifier consisting of an active load gain stage with unity gain
feedback. The termination amplifier holds the parasitic capacitance
of the ladder at a constant voltage during switching, and provides

a low impedance termination of equal voltage for all legs of
the ladder.
The R-2R ladder divides the reference amplifier current into
binarily-related components, which are fed to the switches. Note
that there is always a remainder current which is equal to the
least significant bit. This current is shunted to ground, and the
maximum output current is 255/256 of the reference amplifier
current, or 1.992 rnA for a 2.0 mA reference amplifier current
if the NPN current source pair is perfectly matched.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

6-19

MC1408, MC1508

GENERAL INFORMATION

Reference Amplifier Drive and Compensation

The reference amplifier provides a voltage at pin 14 for converting the reference voltage to a current, and a turn-around circuit

Refer to the subsequent text section on Settling Time for more
details on output loading.
If a power supply value between -5.0 V and -10 V is desired,
a voltage of between 0 and -5.0 V may be applied to pin 1. The
value of this voltage will be the maximum allowable negative output swing.

or current mirror for feeding the ladder. The reference amplifier
input current, 114. must always flow into pin 14 regardless of the

setup method or reference voltage polarity.
Connections for a positive reference voltage arB shown in Figure
7. The reference voltage source supplies the full current 114. For
bipolar reference signals. as in the multiplying mode, R15 can be

Output Current Range

tied to a negative voltage corresponding to the minimum input

The output current maximum rating of 4.2 rnA may be used
only for negative supply voltages typically more negative than
-B.O volts, due to the increased voltage drop across the 350-ohm
resistors in the reference current amplifier.

level. It is possible to eliminate R15 with only a small sacrifice
in accuracy and temperature drift. Another method for bipolar
inputs is shown in Figure 25.
The compensation capacitor value must be increased with increases in R14 to maintain proper phase margin; for R14 values
of 1.0, 2.5 and 5.0 kilohms, minimum capacitor values are 15,
37, and 75 pF. The capacitor "should be"tied to VEE as this increases negative supply rejection.
A negative reference voltage may be used if R14 is grounded
and the reference voltage is applied to R15 as shown in Figure 8.
A high input impedance is the main advantage of this method.
Compensation involves a capacitor to VEE on pin 16, using the
values of the previous paragraph. The negative reference voltage
must be at least 3.0-volts above the VEE supply. Bipolar input
signals may be handled by connecting R 14 to a positive reference
voltage equal to the peak positive input level at pin 15.
When a dc reference voltage is used, capacitive bypass to ground
is recommended. The 5.O-V logic supply is not recommended as
a reference voltage. If a well regulated 5.O-V supply which drives
logic is to be used as the reference, R14 should be decoupled by
connecting it to +5.0 V through another resistor and bypassing
the junction of the two resistors with 0.1 #'F to ground. For
reference voltages greater than 5.0 V, a clamp diode is recommended betvveen pin 14 and ground.
If pin 14 is driven by a high impedance such as a transistor
current source, none of the above compensation methods apply
and the amplifier must be heavily compensated, decreasing the
overall bandwidth.

Accuracy

Absolute accuracy is the measure of each output current level
with respect to its intended value, and is dependent upon relative
accuracy and full scale current drift. Relative accuracy is the
measure of each output current level as a fraction of the full scale
current. The relative accuracy of the MC1408 is essentially
constant with temperature due to the excellent temperature track·
ing of the monolithic resistor ladder. The reference current may
drift with temperature, causing a change in the absolute accuracy
of output current. However, the MC1408 has a very low full
scale current drift with temperature.
The MC140S/MC150S Series is guaranteed accurate to within ± 1/2 LSB at +250 C at a full scale output current of 1.992 rnA.
This corresponds to a reference amplifier output current drive to
the ladder network of 2.0 rnA, with the loss of one LSB =S.O jlA
which is the ladder remainder shunted to ground. The input current
to pin 14 has a guaranteed value of between 1.9 and 2.1 rnA,
allowing some mismatch in the NPN current source pair. The
accuracy test circuit is shown in Figure 4. The 12-bit converter
is calibrated for a full scale output current of 1.992 mAo This is
an optional step since the MC1408 accuracy is essentially the
same between 1.5 and 2.5 rnA. Than the MC140S ·circuits' full
scale current is trimmed to the same value with R 14 so that a zero
value appears at the error ampl ifier output. The counter is activated
and the error band may be displayed on an oscilloscope, detected
by comparators, or stored in a peak detector.
Two 8-bit D-to-A converters may not be used to construct a
16-bit accurate D-to-A converter. 16-bit accuracy implies a total
error of ±1/2 of one part in 65, 536, or ±0.OOO76%, which is much
more accurate than the ±'o.19% specification provided bV the
MCI408xS.

Output Voltage Range
The voltaae on pin 4 is restricted to a range of -0.55 to +0.4
volts at +25 C, due to the current switching methods employed
in the MC1408. When a current switch Is turned "off". the positive voltage on the output terminal can turn "on" the output
diode and increase the output current level. When a current switch
is turned "on", the negative output voltage range is restricted.
The base of the termination circuit Darlington transistor is one
diode voltage below ground when pin 1 is grounded, so a negative
voltage below the specified safe level will drive the low current
device of the Darlington into saturation, decreasing the output
current level.
The negative output voltage compliance of the MC140B may
be extended to -5.0 V volts by opening the circuit at pin 1. The
negative supply voltage must be more negative than -10 volts.
Using a full scale current of 1.992 mA and" load resistor of 2.5
kilohms betvveen pin 4 and ground will yield a voltage output
of 256 levels between 0 and -4.9S0 volts. Floating pin 1 does
not affect the converter speed or power dissipation. However, the
value of the load resistor determines the switching time due to
increased voltage swing. Values of RL up to 500 ohms do not significantly affect performance, but a 2.5-kilohm load increases
"worst case" settling time to 1.2#'s (when all bits are switched on).

Multiplying Accuracy
The MC1408 may be used in the multiplying mode with
eight-bit accuracy when the reference current is varied over a range
of 256:1. The major source of error is the bias current of the
termination amplifier. Under "worst case" conditions, these eight
amplifiers can contribute a total of 1.6 #'A extra current at the
output terminal. If the reference current in the multiplying mode
ranges from 16 SLA to 4.0 mA, the 1.6 IlA contributes an error
of 0.1 LS8. This is well within eight-bit accuracy referenced to
4.0mA.
A monotonic converter is one which supplies an increase in
current for each increment in the binary word. Typically, the
MC1408 is monotonic for all values of reference current above
0.5 mAo The recommended range for operation with a dc reference
current is 0.5 to 4.0 mAo

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

6-20

MC1408, MC1508

GENERAL INFORMATION

IContinued)

Settling Time
The "worst case" switching condition occurs when all bits are
switched "on", which corresponds to a low-ta-high transition for
all bits. This time is typically 300 ns for settling to within ±1/2
LSB, for S-bit accuracy, and 200 ns to 1/2 LSB for 7 and 6-bit
accuracy. The turn off is typically under 100 ns. These times
apply when RL ~ 500 ohms and

The test circuit of Figure 5 requires a smaller voltage swing for
the current switches due to internal voltage clamping in the MC·
1408. A 1.0-kilohm load resistor from pin 4 to ground gives
a typical settling time of 400 ns. Thus, it is voltage swing and not
the output RC time constant that determines settling time for
most appl ications.
Extra care must be taken in board layout since this is usually
the dominant factor in satisfactory test results when measuring
settling time. Short leads, 100 j.LF supply bypassing for low frequencies, and minimum scope lead length are all mandatory.

Co :::;:; 25 pF.

The slowest single switch is the least significant bit, which turns
"on" and settles in 250 ns and turns "off" in 80 ns. In applications where the O-to-A converter functions in a positive-going
ramp mode, the "worst case" switching condition does not occur,
and a settling time of less than 300 ns may be realized. Bit A 7
turns "on" in 200 ns and "off" in 80 ns, while bit A6 turns "on"
in 150 ns and "off" in 80 ns.

TYPICAL CHARACTERISTICS
(VCC = +5.0 V, VEE = -15 V, TA
FIGURE 10 - LOGIC INPUT CURRENT versus INPUT VOL TAGE

=

+25 0 C unless otherwise noted.l
FIGURE 11- TRANSFER CHARACTERISTIC versus TEMPERATURE
(A5 thru AS thresholds lie within range for Al thru A4l

1. 0

~+250C_ t----55 0 C

o. S

r'115 0 C'

'\

o
6

.\

o.1 k
0

A1A1

\

~

" II

\

Mt- ~

0
1.0

~

9

~

High L:"I
A2-A8@ low level
A1

Sf----

3.0

4.0

5.0

Va

~~ +0.6
+0.4~~:~??~??;f???~??~~~~~~~=~=~

R~nge

w-

~ +0.21------;f-c:75f-c:771777%'77::M75~75_517777t_-__t-~

0
-7.0

-6.0

-5.0

~

,,,
(

pin 1 open
VEE ~ -10 Vdc

/

o. 1
-4.0

-3.0

5.0

+1.0,--,--,---,---,--,-----,---,-,---,---;

Accuracy

o. 4

4.0

FIGURE 13 - OUTPUT VOLTAGE versus TEMPERATURE
(Negative range with pin 1 open is -5.0 Vdc over full temperilture rangel

for S·bit

-

3.0

." 'O.S f---+--+--+--+--+---j-----j------t----t--'

1

0
O. 6

1.0

VI. LOGIC INPUT VOLTAGE IVric)

I

4

S

A4

II I
1.0

6

1. 0

A3

o. 1

FIGURE 12 - OUTPUT CURRENT versus OUTPUT VOLTAGE
(See text for pin 1 restrictions)

1. 0

A1

4

VI, LOGIC INPUT VOLTAGE IVdc)

-

Al

6

"-

1.0

~B

/

S

4"

'.s"

"

1 \

if

-1.0

/

>

~

~

pin 1 grounded

~

J
-1.0

I

+1.0

-0.2 t---+t:T7'.'D5-»
-0.4 t--'rWWl7"m+77'7+77'7't77771777Zf:::""""t-----t----j

-0.6 t---7f7Wl7"ij,;~"...+"=T-----t----j-----j------t----j

-O.sl----"I=----+-+-+-+--I---+--+-+-1
-1.0 L--_:'-:55L.-L.--':------'----+-:-50::------'---:+-::10;;;0----'----:+--;t5~0;------'

+1.0 +3.0

VO, OUTPUT VOLTAGE, PIN 4lVdc)

T, TEMPERATURE IOC)

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

6-21

MC1408, MC1508

TYPICAL CHARACTERISTICS (continued)
(VCC

= +5.0 V, VEE =-15 V, TA =+25 0 C unless otherwise noted.)
FIGURE 15 - TYPICAL POWER SUPPLY CURRENT
versus TEMPERATURE (all bits low)

FIGURE 14 - REFERENCE INPUT FREQUENCY RESPONSE
+8.0

20

+6. 0
+4, 0

=

...

~ +2. 0

~

L

5
~

8

6

~
~

0

~ -2. 0

>

1'-

VI\

!

4

r-- r--

2

-

t--

A

-4. 0

~~

-6. 0

I I

0

ICC

0

-8. 0

lEE

1\

-I 0

6. 0

1\

-I 2
0,1

4. 0

1.0

10

+50

-55

+100

+150

T, TEMPERATURE (OC)

f, FREQUENCY (MHz)

FIGURE 16 - TYPICAL POWER SUPPLY CURRENT

versus Vee {all bits lowl

Unless otherwise specified:

20

R14" R15" 1.0kU
C " 15 pF, pin 16 to VEE
RL =50 n,pin 4 (0 GNO

Curve A:

Curve B:

;{ 18
~
...

large Signal Bandwidth
Method of Figure 7
Vref" 2.0 Vlp·pl offset 1.0 Vahove OND
Small Signal Bandwidth
Method of Figure 7 Rl" 250 n
Vref:: 50 mV(p·p) offset 200 mV above GND

Curve C:

large and Small Signal Bandwidth
Method of Figure 2S Ina op·ampl, RL" 50
RS"5011
V re f"2,OV

.

16

§~

14

::

~~

12

10

~

8. 0

rn

ICC

lEE

6. 0
4,0

VS:: 100 mV(p·p) centered at 0 V

o

-2,0

-4,0

-6,0

-8.0

-10

-12

-14

-16

-18

-20

VEE, NEGATIVE POWER SUPPLY (Vdcl

APPLICATIONS INFORMATION
FIGURE 17 - OUTPUT CURRENT TO VOLTAGE CONVERSION
V rei
R14
RO

Vcc
13

Theoretical
14

MSB Al

= 2.0 Vdc
= R15 '" 1.0 kU
= 5.0 Idl
Vref

A2

Vo

15

A3

Vo

R14

=

V I
[AI
-IlL (RO) R14
2

+ -A2
+ -A3
+ -A4
+ -A5
+ -A6 + -A7 + -A8]
4
8
16
32
64
128
256

Adjust Vref, R14 or RO so that
level is equal to 9.961 volts.

A6

Vo
4

Vo

= -2V
(5 k) ~- + -1 + -1 + -1 + -1
1k
2
4
8
16
32
= 10 V [255 = 9.961
256

V

or Equiv.
VEE

MOTOROLA LlNEARIINTERFACE ICs DEVICE DATA
6-22

Vo with all digital inputs at high
+ -1 + - 1 + - 1
64

128

256

]

MC1408, MC1508

APPLICATIONS INFORMATION (continued)

Voltage outputs of a larger magnitude are obtainable with this
circuit which uses an external operational amplifier as a current
to voltage converter. This configuration automatically keeps the
output of the MC1408 at ground potential and the operational
amplifier can generate a positive voltage limited only by its positive
supply voltage. Frequency response and settling time are primarily
determined by the characteristics of the operational amplifier. In

The positive voltage range may be extended by cascading the
output with a high beta common base transistor, Q 1, as shown.

FIGURE 20 - EXTENDING POSITIVE
VOLTAGE RANGE

addition, the operational amplifier must be compensated for unity
gain, and in some cases overcompensation may be desirable.
Note that this configuration results in a positive output voltage
only, the magnitude of which is dependent on the digital input.
The following circuit shows how the MLM301AG can be used
in a feedforward mode resulting in a full scale settling time on
the order of 2.0 ,,",S.

Vee
5 k
(Resistor and
diode optional.

see toxt)
Go

FIGURE 18
65 pF

5.1 k.

(To pin 4
of MC15D8LBI

The output voltage range for this circuit is 0 volts to BVCBO
of the transistor. If pin 1 is left open, the transistor base may be
grounded, eliminating both the resistor and the diode. Variations
in betil must be considered for wide temperature range applications. An inverted output waveform may be obtained by using a
load resistor from a positive reference voltage to the collector of
the transistor. Also, high-speed operation is possible with a large
output voltage swing, because pin 4 is held at a constant voltage.
The resistor (RI to VEE maintains the transistor emitter voltage
when all bits are "off" and insures fast turn-on of the least
significant bit.

--o--+.--oVQ

An alternative method is to use the MC1539G and input compensation. Response of this circuit is also on the order of 2.0 ,,",S.
See Motorola Application Note AN-459 for more details on this
concept.

Combined Output Amplifier and Voltage Reference
For many of its applications the MC1408 requires a reference
voltage and an operational amplifier. Normally the operational
amplifier is used as a current to voltage converter and its output
need only go positive. With the popular MC1723G voltage regulator both of these functions are provided in a single package with
the added bonus of up to 150 mA of output current. See Figure
21. The MC1723G uses both a positive and negative power supply.
The reference voltage of the MC1723G is then developed with
respect to the negative voltage and appears as a common-mode
signal to the reference amplifier in the D-to-A converter. This
allows use of its output amplifier as a classic current-to-voltage
converter with the non-inverting input grounded.
Since ±15 V and +5.0 V arc normally available in a combination digital-to-analog system, only the -5.0 V need be developed.
A resistor divider is sufficiently accurate since' the allowable range
on pin 5 is from -2.0 to -8.0 volts. The 5.0 kilohm pull down
resistor on the ampl ifier output is necessary for fast negative
transitions.
Full scale output may be increased to as much as 32 volts by
increasing RO and raising the +15 V supply voltage to 35 V maximum. The resistor divider should be altered to comply with the
maximum limit of 40 volts across the MC1723G. Co may be
decreased to maintain the same RaCa product if maximum speed
is desired.

FIGURE 19

+15 V

35 pF

5 k

10 k

-15 V

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

6-23

MC1408, MC1508

APPLICATIONS INFORMATION (continued)

Programmable Power Supply

FIGURE 22 - BIPOLAR OR NEGATIVE OUTPUT
VOLTAGE ~IRCUIT

The circuit of Figure 21 can be used as a digitally programmed
power supply by the addition of thumbwheel switches and a BCD~
to-binary converter. The output voltage can be scaled in several

ways. including 0 to +25.5 volts in a.l-volt increments. ±O.05 volt;
or 0 to 5.1 volts in 20mV increments,±10mV.
Aa

FIGURE 21 - COMBINED OUTPUT AMPLIFIER and
VOLTAGE REFERENCE CIRCUIT

Va
RO 5 k
Co 25 pF

Vee +5 V

'5 V

Vee

Vo

A5
A6

-15
VEE

Vref

= - - fRO)

R14

RB=2 Rt4
R15 = R14

V

[A1

A2

A3

A4 A5

A6 A7

4

S

16

64 128 256

AS]

-+-+-+-+-+ -+- + 2

32

Vref

- -

RB

(RO)

+15 V

7

A7

I

15

AS
LSB

1
1
1
3.6 k

17.1

v

1

5
1.6 k

Vee -15

I
I

0.01 SlF I

L ___

FIGURE 23 - BIPOLAR OR INVERTED NEGATIVE
OUTPUT VOL TAGE CIRCUIT

:

I
I

A

1

--.l

V

Vo" Vref - :~ {A}
Settling time for a 10-volt $tep §g' 1.0 ~s

F or A = 00000000
bit configuration
A14

A15

VO=-Vref
For a ±.5.0 volt output range:

Vee ":'
Vee -15 V
'5 V

Bi....... or Negative Output Voltage
The circuit of Figure 22 is a variation from the standard voltage output circuit and will produce bipolar output signals. A
positive current may be sourced into the summing node to offset
the output voltage in the negative direction. For example, if
approximately '.0 mA is used a bipolar output signal results which
may be described as a a-bit ""s" complement offset binary. Vref
may be used as this auxiliary reference. Note that RO has been
doubled to 10 kilohm. because of the anticipated 20 VIp-pI
output range.

-Vref

Vref = -5.00 volts
R14 = Rt5 = 2.5kO
= 37 pF (minI
RO = 6 k{l

e

'Decrease RO to 2.5 kSl for a D to -S.D·volt outPut range.
This application provides somewhat lower speed, as previously
discussed in the Output Voltage Range section of the General
Information.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

6-24

MC1408, MC1508

APPLICATIONS INFORMATION (continuedl

Polarity Switching Circuit, a·Bit Magnitude
Plus Sign D-to-A Converter

Panel Meter Readout

Bipolar outputs may also be obtained by using a polarity switching circuit. The circuit of Figure 24 gives 8·bit magnitude plus
a sign bit. In this configuration the operational amplifier is switched
between a gain of +1.0 and -1.0. Although another operational

The MC1408 can be used to read out the status of BCD or
binary registers or counters in a digital control system. The current
output can be used to drive directly an analog panel meter. Ex·
ternal meter shunts may be necessary if a meter of less than 2.0
mA full scale is used. Full scale calibration can be done by adjusting R14 or Vref

amplifier is required, no more space is taken when a dual operational
amplifier such as the MC1558G is used. The transistor should be

selected for a very low saturation voltage and resistance.
FIGURE 26 - PANEL METER REAOOUT CIRCUIT
FIGURE 24 - POLARITY SWITCHING CIRCUIT
(8·Bit Magnitude Plus Sign D-to-A Converted

Digital Word From Counter or Register

MSB~LSB

'4V---o"14'-j
V ref ...--"R",
R15

MC1408 Series
MC1508
15

Observe internal meter
resistance (for pin 4

Programmable Gain Amplifier or Digital Attenuatar

FIGURE 27 - OC COUPLEO OIGITAL ATTENUATOR
and OIGITAL SUBTRACTION

When used in the multiplying mode the MC1408 can be
applied as a digital attenuator. See Figure 25. One advantage of
this technique is that if RS '" 50 ohms, no compensation capacitor
is needed. The small and large signal bandwidths are now identic(]l
and are shown in Figure 14.
The best frequency response is obtained by not allowing 114
to reach zero. However, the high impedance node, pin 16, is
clamped to prevent saturation and insure fast recovery when the
current through R14 goes to zero. RS can be set for a ±1.0 mA
variation in relation to 114' 114 can never be negative.
The output current is always unipolar. The quiescent dc output
current level changes with the digital word which makes ac coupl 1ng
necessary.
FIGURE 25 - PROGRAMMABLE GAIN AMPLIFIER OR
OIGITAL ATTENUATOR CIRCUIT
Vs
RS
R14

j"4

Vref
When Vs = 0, 114 = 2.0 mA

102 = -16
18 I 10 ~ 10 1

Digital Subtraction:

V re f l
Lo< - -

V re f2

R141

R142

Programmable Amplifier
Connect Digital Inputs so A = B

V - { } [V,efl
0'-

A

--

R14,

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

6-25

V,ef']

-~-

R142

MC1408, MC1508

APPLICATIONS INFORMATION (continued)
FIGURE 36 - TWO·DIGIT BCD CONVERSION

Vo

Vee

Two B·bit, D-to-A converters can be used to build a two digit
BCD D-to-A or A-to-D converter. If both outputs feed the virtual
ground of an operational amplifier, 10:1 current scaling can be
achieved with a resistive current divider. If current output is desired, the units may be operated at full scale current levels of

4.0 mA and 0.4 rnA with the outputs connected to sum the currents.
The error of the D-to-A converter handling the least significant
bits will be scaled down by a factor of ten and thus an MC140BL6
may be used for the least significant word.

FIGURE 37 - DIGITAL QUOTIENT OF TWO ANALOG VARIABLES
or ANALOG·TO·DIGITAL CONVERSION

Clock

Reset

RO
Vref

4
12
11
10

R14
Vref

R15

VEE

14

13

MC140S Series

9

Me15Q8

8

6
5

LSB

The circuit shown is a simple counter-

ramp-converter. An UP/DOWN counter
and dual threshold comparator can be
used to provide faster operation and continuous conversion.

MSB

'---v-----'
C

c

=

Vln/RO
Vref/R14

MOTOROLA LlNEARIINTERFACE ICs DEVICE DATA

6-26

MOTOROLA

-

SEMICONDUCTOR - - - - - -

MC10319

HIGH SPEED
8-BIT ANALOG-TO-DIGITAL CONVERTER

HIGH SPEED
8-BIT ANALOG-TO-DIGITAL
FLASH CONVERTER

TECHNICAL DATA

SIUCON MONOUTHIC
INTEGRATED CIRCUIT

The MC10319 is an 8·bit high speed parallel flash AID converter.
The device employs an internal Gray Code structure to eliminate
large output errors on fast slewing input signals. It is fully TTL
compatible, requiring a + 5.0 V supply and a wide tolerance neg·
ative supply of - 3.0 to - 6.0 V. Three·state TTL outputs allow
direct drive of a data bus or common I/O memory.
The MC10319 contains 256 parallel comparators across a precision input reference network. The comparator outputs are fed
to latches and then to an encoder network, to produce an 8-bit
data byte plus an overrange bit. The data is latched and converted
to 3-state LS-TTL outputs. The overrange bit is always active to
allow for either sensing of the overrange condition or ease of
interconnecting a pair of devices to produce a 9-bit AID converter.
Applications include Video Display and Radar processing, high
speed instrumentation and TV Broadcast encoding.

~

LSUFFIX
CERAMIC PACKAGE
CASE 623

24

1

PSUFFIX

PLASTIC PACKAGE
CASE 709

• Internal Gray Code for Speed and Accuracy, Binary Outputs

~
~

Jr6IS\!
24

• 8·Bit Resolution/9-Bit Typical Accuracy

28#

• Easily Interconnected for 9-Bit Conversion
• 3·State LS-TTL Outputs with True and Complement Enable
Inputs
• 25 MHz Sampling Rate
• Wide Input Range: 1.0-2.0 Vp _p Between ±2.0 V
• Low Input Capacitance: 50 pF
• Low Power Dissipation: 618 mW

DWSUFFIX
PLASTIC PACKAGE
CASE 751F
SO·28L

PIN DIAGRAM
IL and P only)

• No Sample/Hold Required for Video Bandwidth Signals
• Single Clock Cycle Conversion

BLOCK DIAGRAM
Logic
Analog
Input

VCC(O)
(11.17)

VEE
(13)

Vin
(14)

1
:Sia-;
I
L ___ J

MC10319
VRT
(24)

.----,
I
I

I

GNO
(2.12.
16.22)

j----,

I

I

I

I

Over·
Range
(31
07 (4)
06 (51
05 (6)

VRM
(1)

04 (7)
03 (8)
02 (9)
01 (10)
DO (211

VRB
(23)

ORDERING INFORMATION
Device
MC10319DW
MC10319L
MC10319P

Clock
(18)

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

6-27

Temperature Range

Package

0' to +70'C

SO·28L
Ceramic
Plastic

MC10319
ABSOLUTE MAXIMUM RATINGS
Parameter
Supply Voltage
Positive Supply Voltage Differential

Symbol

Value

Unit

VCC(A),(D)
VEE

+7.0
-7.0

Vdc

VCC(D)VCC(A)

-0.3 to +0.3

Vdc

Digital Input Voltage (Pins 18-20)

VI(D)

-0.5 to +7.0

Vdc

Analog Input Voltage (Pins 1, 14,23,24)

VI(A)

-2.5 to +2.5

Vdc

Reference Voltage Span (Pin 24-Pin 23)

-

2.3

Vdc

Applied Output Voltage (Pins 4-10, 21 in 3-State)

-

-0.3 to +7.0

Vdc

Junction Temperature

TJ

+150

°c

Storage Temperature

Tstg

-65 to +150

°c

Devices should not be operated at these values. The "Recommended Operatmg Limits " provide gUidelines for actual
device operation.

RECOMMENDED OPERATING LIMITS
Parameter

Power Supply Voltage (Pin 15)
(Pins 11, 17)

Symbol

Min

Typ

Max

Unit

VCC(A)
VCC(D)

+4.5

+5.0

+5.5

Vdc

avCC

-0.1

0

+0.1

Vdc

Power Supply Voltage (Pin 13)

VEE

-6.0

-5.0

-3.0

Vdc

Digital Input Voltages (Pins 18-20)

VI(D)

0

+5.0

Vdc

Analog Input (Pin 14)

VI (A)

-2.1

+2.1

Vdc

Voltage @ VRT (Pin 24)

VRT

-1.0

+2.1

Vdc

Voltage @ VRB (Pin 23)

VRB

-2.1

VRT - VRB

aVR

+1.0

VRB - VEE

-

1.3

Applied Output Voltage (Pins 4-10, 21 in 3-State)

Vo

0

-

tCKH
tCKL

5.0
15

20
20

fCLK

0

TA

0

-

VCC(D) - VCC(A)

Clock Pulse Width -

High
Low

Clock Frequency
Operating Ambient Temperature

-

+1.0

Vdc

+2.1

Vdc

-

Vdc

5.5

Vdc

-

ns

25

MHz

+70

°c

ELECTRICAL CHARACTERISTICS (0° < TA < 70°C, VCC = 5.0 V, VEE = -5.2 V, VRT = + 1.0 V, VRB = -1.0 V, except
where noted.)
Parameter

Symbol

Min

N

-

Typ

Max

Unit

-

8.0

Bits

±1.0

LSB

TRANSFER CHARACTERISTICS (fCKL - 25 MHz)
Resolution

MON

Monotonicity
Integral Nonlinearity

INL

-

±1/4

Differential Nonlinearity

DNL
DP

-

1.0

DG

-

1.0

Differential Phase (See Figure 16)
Differential Gain (See Figure 16)

-

-

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
6-28

±1.0

-

LSB
Deg.
%

LSBN

PSRR

Power Supply Rejection Ratio
(4.5 V < VCC < 5.5 V, VEE = -5.2 V)
(-6.0 V < VEE < -3.0 V, VCC = +5.0 V)

Bits

Guaranteed

0.1
0

-

ELECTRICAL CHARACTERISTICS -

continued (0' < TA < 70'C. VCC = 5.0 V. VEE =
VRS = -1.0 V. except where noted.)

- 5.2 V. VRT =

+ 1.0 V.

ANALOG INPUT (PIN 14)

= VRS (See Figure 5)
= VRT (See Figure 5)
Input Capacitance (VRT - VRS = 2.0 V. See Figure 4)
Input Capacitance (VRT - VRS = 1.0 V. See Figure 4)
Input Current @ Vin

IINL

Input Current @ Vin

IINH

VOS

-

Rref

104

TC
Cref

-

Cin
Cin

Bipolar Offset Error

-100

0

-

p.A

60

150

p.A

36

pF

0.1

-

130

156

+0.29
25

-

-

-

V

0.8

V

55

pF
LSS

REFERENCE
Ladder Resistance (VRT to VRS. TA

= 25'C)

Temperature Coefficient
Ladder Capacitance (Pin 1 open)

ENABLE INPUTS (VCC

=

n
%/DC

pF

55 V) (See Figure 6)

Input Voltage -

High (Pins 19-20)

VIHE

2.0

Input Voltage -

Low (Pins 19-20)

VILE

-

Input Current @ 2.7 V

IIHE

20

p.A

Input Current @ 0.4 V @ EN (0 < EN < 5.0 V)

IILI

-400

-100

-

p.A

IIL2

-400

-100

-

p.A

IIL3

-20

-2.0

p.A

VIKE

-1.5

-1.3

-

Input Voltage High

VIHC

2.0

Input Voltage Low

VILC

-

Input Current @ 004 V (See Figure 7)

IILC

Input Current @ 2.7 V (See Figure 7)

Input Current @ 004 V @ EN (EN
Input Current @ 004 V @ EN (EN
Input Clamp Voltage (11K

CLOCK INPUT (VCC

=

= 0 V)
= 2.0 V)

-18 mAl

0

V

= 5.5 V)

-

-

Vdc

0.8

Vdc

-400

-80

-

p.A

IIHC

-100

-20

-

p.A

-18 mAl

VIKC

-1.5

-1.3

-

Vdc

High Output Voltage (lOH

= -400 p.A. VCC = 4.5 V. See Figure 8)
= 4.0 mAo See Figure 9)
Output Short Circuit Current" (VCC = 5.5 V)

VOH

2.4

3.0

-

V

Low Output Voltage (lOL

VOL

-

0.35

0.4

V

-

rnA

Input Clamp Voltage (11K

=

DIGITAL OUTPUTS

ISC

35

-50

-

Cout

-

9.0

VCC(A) Current (4.5 V < VCC(A) < 5.5 V) (Outputs unloaded)

ICC(A)

10

VCC(O) Current (4.5 V < VCC(D) < 5.5 V) (Outputs unloaded)

ICC(O)

50

lEE

-14

-10

-6.0

mA

618

995

mW

Output Leakage Current (004 < Vo < 204 V. See Figure 3.
VCC = 5.5 V. 00-07 in 3-State Mode)

ILK

Output Capacitance (00-07 in 3-State Mode)
*Only one output IS to be shorted at a time, not to exceed 1 second.

+50

p.A

-

pF

17

25

mA

90

133

mA

POWER SUPPLIES

VEE Current (-6.0 V < VEE < -3.0 V)
Power Oissipation (VRT - VRB

= 2.0 V)

(Outputs unloaded)

Po

-

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
6-29

MC10319
TIMING CHARACTERISTICS (TA = 25°C, VCC = +5.0 V, VEE = -5.2 V, VRT = +1.0 V, VRB = -1.0 V,
See System Timing Diagram.)
Symbol

Parameter

Min

Typ

Max

Unit

INPUTS
Min Clock Pulse Width -

High

tCKH

-

ns

Low

tCKL

-

5.0

Min Clock Pulse Width -

15

-

ns

Max Clock Rise, Fall Time

tR,F

-

100

-

Clock Frequency

fCLK

0

30

25

ns
MHz

OUTPUTS
New Data Valid from Clock Low

tCKDV

-

19

tAD

4.0

-

-

ns

Data High to 3-State from Enable Low'

tEHZ

Data Low to 3-State from Enable Low'

tELZ

Data High to 3·State from Enable High'

tEHZ

-

Data Low to 3-State from Enable High'

tELZ

-

18

-

Valid Data from Enable High (Pin 20 = 0 V)'

tEDV

-

15

-

ns

Valid Data from Enable Low (Pin 19 = 5.0 V)'

tEDV

-

16

-

ns

8.0

-

ns

Aperture Delay
Hold Time

tH

Output Transition Time' (10%-90%)

ttr

*See FIgure 2 for output loadtng.

PIN DESCRIPTIONS
Symbol

Pin
L,P Suffix

OW Suffix

VRM

1

1

The midpoint of the reference resistor ladder. Bypassing can
be done at this point to improve performance at high
frequencies.

GND

2,12
16,22

2,13,17
18,25,26

Digital ground. The pins should be connected directly together,
and through a low impedance path to the power supply.

OVR

3

3

Overrange output. Indicates Vin is more positive than VRT 112
LSB. This output does not have 3-state capability.

D7-DIIl

4-10,21

4-10,24

Digital Outputs. 07 (Pin 4) is the MSB. Dill (Pin 21 or 24) is the
LSB. LSTTL compatible with 3·state capability.

VCC(D)

11,17

11,12
19,20

Power supply for the digital section. +5.0 V, ± 10% required.
Reference to digital ground.

VEE

13

14

Negative Power supply. Nominally - 5.2 V, it can range from
-3.0to -6.0 V, and must be more negative than VRB by >1.3 V.
Reference to analog gnd.

Vin

14

15

Signal voltage input. This voltage is compared to the reference
to generate a digital equivalent. Input impedance is nominally
16-33K in parallel with 36 pF.

VCC(A)

15

16

Power supply for the analog section. + 5.0 V, ± 10% required.
Reference to analog ground.

CLK

18

21

Clock input. TTL compatible.

EN

19

22

Enable input. TTL compatible, a logic 1 (and EN at a logic 0)
enables the data outputs. A logic 0 puts the outputs in a 3-state
mode.

EN

20

23

Enable input. TTL compatible, a logic 0 (and EN at a logic 1)
enables the data outputs. A logic 1 puts the outputs in a 3-state
mode.

VRB

23

27

The bottom (most negative point) of the internal reference
resistor ladder.

VRT

24

28

The top (most positive point) of the internal reference resistor
ladder.

Description

MOTOROLA L1NEARIINTERFACE ICs DEVICE DATA
6-30

6.0
27
18
32

-

ns
ns
ns
ns
ns
ns

MC10319
FIGURE 1 -

SYSTEM TIMING DIAGRAM

tCKH---II"I-"I----tCKL---_

,-----__,.·-3.0 V
Clock

~

__~__________~ 1.5V

1.5

Vl"------------

tCKDV and tH measured at output levels of 0.8 and 2.4 volts.

------ --- -- --- --- --- --- --- --- --- --- --- --- --- --- --- --- -----EN

High Data
Output

Low Data
Output

-.3_State------~----_OutPuts----I~
Active

FIGURE 2 -

DATA OUTPUT TEST CIRCUIT

FIGURE 3 -

OUTPUT 3-STATE LEAKAGE CURRENT

200
VCC

1.0 kO

00-07

'>--..--.-*---1
C1-T'

3.0 kO

n'7
Diodes

=

lN914 or equivalent, Cl = 15 pF

100

1

50

Ia
~

-50

~

-100

-200
-1.0

)

If
II

I

Pin 19

1.0

= 0V

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
6-31

OOG < TA < 70'G

2.0
3.0
4.0
APPLIED VOLTAGE [VOLTS[

5.0

S:~.

7.0

MC10319

FIGURE 4 -

FIGURE 5 -

INPUT CAPACITANCE @ VIN (PIN 14)

100

INPUT CURRENT @ VIN (PIN 14)

0

,
I
I

25°C_
DoC

I

~.
t':l

:
\:

z

;:0
<:3

0

I

80

60

;t

I--



i'..

u
~

"

20°
40°
60
TA. AMBIENT TEMPERATURE lOCI

!!5
'"

"""

-9

-8

70°

VEE = -5.2 V

o

20°
40°
TA. AMBIENT TEMPERATURE

60"

70"

lOCI

FIGURE 13 - INTEGRAL LINEARITY ERROR

FIGURE 12 - DIFFERENTIAL LINEARITY ERROR

1/2

lSB

h. ~ ~ ~ ~

~~'Ir\ ~
-1/2

LSB

~ 11'1 ~ ~

~JJ ~.l

.1~11

-r l r'I'f'l

"

I

VRT = 2.0V. VRB = OV
F'I = 215 M~z I I

32

64

96

128

160

192

224

FIGURE 15 - INTEGRAL LINEARITY ERROR

FIGURE 14 - DIFFERENTIAL LINEARITY ERROR

1/2
lSB

~ l.A ~. 1\.1 ~ jj

~ W1jP\ ~

~

I"

-112

.1
'1Ij\

11 ..

~r ~ In r1
~

lSB
VRT = 2.0 V. VRB = OV
F'I =

lr5~Hz I
32

64

I

96

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
6-33

128

160

192

224

~

MC10319

DESIGN GUIDELINES
INTRODUCTION
The MC10319 is a high-speed, 8-bit, parallel ("Flash")
type analog-to-digital converter containing 256 comparators at the front end. See Figure 17 for a block diagram. The comparators are arranged such that one input of each is referenced to evenly spaced voltages,
derived from the reference resistor ladder. The other
input of the comparators is connected to the input signal
(Vin)' Some of the comparator's differential outputs will
be "true," while other comparators will have "not true"
outputs, depending on their relative position. Their outputs are then latched, and converted to an 8-bit Grey
code by the Differential Latch Array. The Grey code ensures any input errors due to cross talk, feed-thru, or
timing disparaties, result in glitches at the output of only
a few LSBs, rather than the more traditional 1/2 scale
and 1/4 scale glitches.
The Grey code is then translated to an 8-bit binary
code, and the differential levels are translated to TTL
levels before being applied to the output latches. ENABLE inputs at this final stage permit the TIL outputs
(except Overrange) to be put into a high impedance
(3-state) condition.

REFERENCE
The reference resistor ladder is composed of a string
of equal value resistors so as to provide 256 equally
spaced voltages for the comparators (see Figure 17 for
the actual configuration). The voltage difference between adjacent comparators corresponds to 1 LSB of
the input range. The first comparator (closest to VRB)
is referenced 1/2 LSB above VRB, and the 256th comparator (for the overrange) is referenced 1/2 LSB below
VRT. The total resistance of the ladder is nominally 130
fl, ±20%, requiring 15.4 mA@ 2.0 volts, and 7.7 mA@
1.0 volt. There is a nominal warm-up change of = +9.0%
in the ladder resistance due to the + 0.29%I"C temperature coefficient.
The minimum recommended span [VRT - VRBl is
1.0 volt. A lower span will allow offsets and nonlinearities to become significant. The maximum recommended span is 2.1 volts due to power limitations of
the resistor ladder. The span may be anywhere within
the range of - 2.1 to + 2.1 volts with respect to ground,
and VRB must be at least 1.3 volts more positive than
VEE. The reference voltages must be stable and free of
noise and spikes, since the accuracy of a conversion is
directly related to the quality of the reference.
In most applications, the reference voltages will remain fixed. In applications involving a varying reference
for modulation or signal scrambling, the modulating
signal may be applied to VRT, or VRB, or both. The output will vary inversly with the reference signal, introducing a nonlinearity into the transfer function. The addition of the modulating signal and the dc level applied
to the reference must be such that the absolute voltage
at VRT and VRB are maintained within the values listed
in the Recommended Operating Limits. The RMS value
of the span must be maintained ..2.1 volts.
VRM (Pin 1) is the midpoint of the resistor ladder,
excluding the Overrange comparator. The voltage at
VRM is:
VRT + VRB _ 1/2 LSB
2.0
In most applications, bypassing this pin to ground (0.1
p.F) is sufficient to maintain accuracy. In applications
involving very high frequencies, and where linearity is
critical, it may be necessary to trim the voltage at the
midpoint. A means for accomplishing this is indicated
in Figure 18.

ANALOG SECTION
SIGNAL INPUT
The signal voltage to be digitized (Vin) is applied
simultaneously to one input of each of the 256 comparators through Pin 14. The other inputs of the comparators are connected to 256 evenly spaced voltages
derived from the reference ladder. The output code depends on the relative position of the input signal and
the reference voltages. The comparators have a
bandwidth of >50 MHz, which is more than sufficient
for the allowable (Nyquist theory) input frequency of
12.5 MHz.
The current into Pin 14 varies linearly from 0 (when
Vin = VRB) to =60 p.A (when Vin = VRT). If Vin is taken
below VRB or above VRT, the input current will remain
at the value corresponding to VRB and VRT respectively
(see Figure 5). However, Vin must be maintained within
the absolute range of ± 2.5 volts (with respect to
ground) - otherwise excessive currents will result at
Pin 14, due to internal clamps.
The input capacitance at Pin 14 is typically 36 pF if
[VRT - VRBl is 2.0 volts, and increases to 55 pF if [VRT
- VRBl is reduced to 1.0 volt (see Figure 4). The capacitance is constant as Vin varies from VRT down to
=0.1 volt above VRB. Taking Vin to VRB will show an
increase in the capacitance of =50%. If Vin is taken
above VRT, or below VRB, the capacitance will stay at
the values corresponding to VRT and VRB, respectively.
The source impedance of the signal voltage should
be maintained below 100 0. (at the frequencies of interest) in order to avoid sampling errors.

POWER SUPPLIES
VCC(A) is the positive power supply for the comparators, and VCC(D) is the positive power supply for the
digital portion. Both are to be + 5.0 volts, ± 10%, and
the two are to be within 100 millivolts of each other.
There is indirect internal coupling between VCC(D) and
VCC(A)' If they are powered separately, and one supply
fails, there will be current flow through the MC10319 to
the failed supply.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
6-34

MC10319
The comparator output latches provide the circuit
with an effective sample-and-hold function, eliminating
the need for an external sample-and-hold.

ICC(A) is nominally 17 mA, and does not vary with
clock frequency or with Vin. It does vary linearly with
VCC(A)' ICC(O) is nominally 90 mA, and is independent
of clock frequency. It does vary, however, by 6-7 mA
as Vin is changed, with the lowest current occuring
when Vin = VRT It varies linearly with VCC(O).
VEE is the negative power supply for the comparators,
and is to be within the range - 3.0 to - 6.0 volts. Additionally, VEE must be at least 1.3 volts more negative
than VRB. lEE is a nominal -10 mA, and is independent
of clock frequency, Vin, and VEE.
For proper operation, the supplies must be bypassed
at the IC. A 10 JLF tantalum, in parallel with a 0.1 JLF
ceramic is recommended for each supply to ground.

ENABLE INPUTS
The two Enable inputs are TTL compatible, and are
used to change the data outputs (07-00) from active to
3-state. This capability allows cascading two MC10319s
into a 9-bit configuration, flip-flopping two MC10319s
into a 50 MHz configuration, connecting the outputs
directly to a data bus, multiplexing mUltiple converters,
etc. See the Applications Information section for more
details. For the outputs to be active, Pin 19 must be a
Logic "1," and Pin 20 must be a Logic "0." Changing
either input will putthe outputs into the high impedance
mode. The Enable inputs affect only the state of the
outputs - they do not inhibit a conversion. The input
current into Pins 19 and 20 is shown in Figure 6, and
the input - output timing is shown in Figure 1 and 20.
Leaving either pin open is equivalent to a Logic "1,"
although good design practice dictates that an input
should never be left open.
The Overrange output (Pin 3) is not affected by the
Enable inputs as it does not have 3-state capability.

DIGITAL SECTION
CLOCK
The Clock input is TTL compatible with a typical frequency range of 0 to 30 MHz. There is no duty cycle
limitations, but the minimum low and high times must
be adhered to. See Figure 7 for the input current
requirements.
The conversion sequence is shown in Figure 19, and
is as follows:
• On the rising edge, the data output latches are latched
with old data, and the comparator output latches are
released to follow the input signal (Vin).

OUTPUTS
The data outputs are TTL level outputs with high
impedance capabilility. Pin 4 is the MSB (07), and Pin
21 is the LSB (DO). The eight outputs are active as long
as the Enable inputs are true (Pin 19 = high, Pin 20 =
low). The timing of the outputs relative to the Clock
input and the Enable inputs is shown in Figures 1 and
20. Figures 8 and 9 indicate the output voltage versus
load current, while Figure 3 indicates the leakage current when in the high impedance mode.
The output code is natural binary, depicted inthe table
below.
The Overrange output (Pin 3) goes high when the input, Vin, is more positive than VRT - 112 LSB. This
output is always active - it does not have high impedance capability. Besides being used to indicate an input
overrange, it is additionally used for cascading two
MC10319s to form a 9-bit AID converter (see Figure 27).

• During the high time, the comparators track the input
signal. The data output latches retain the old data.
• On the falling edge, the comparator outputs are
latched with the data immediately prior to this edge.
The conversion to digital occurs within the device,
and the data output latches are released to indicate
the new data within 20 ns.
• During the clock low time, the comparator outputs
remain latched, and the data output latches remain
transparent.
A summary of the sequence is that data present at
Vin just prior to the Clock falling edge is digitized and
available at the data outputs immediately after that
same falling edge.

VRT, VRB Ivolts)

Input
>VRT - 1/2 LSB
VRT - 1/2 LSB
VRT - 1 LSB
VRT - 1-1/2 LSB
Midpoint
VRB + 1/2 LSB
2.044 V
2.044 V
2.040 V

>0.9961 V
0.9961 V
0.992 V

>0.9980 V
0.9980 V
0.9961 V
0.9941 V
0.5000 V
1.95 mV
<0 V

FFH
FFH
FFH
FEH - FFH
80H
OOH - 01H
DOH

2.036 V
1.024 V
4.0 mV
<0 V

0.988 V

0.000 V
-0.9961 V
<-1.0V

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
6-35

Overrange

1
0-1
0
0
0

0
0

MC10319
APPLICATIONS INFORMATION
POWER SUPPLIES. GROUNDING
The PC board layout. and the quality of the power
supplies and the ground system at the IC are very important in order to obtain proper operation. Noise. from
any source. coming into the device on VCC. VEE. or
ground can cause an incorrect output code due to interaction with the analog portion of the circuit. At the
same time. noise generated within the MC10319 can
cause incorrect operation if that noise does not have a
clear path to ac ground.
Both the VCC and VEE power supplies must be
decoupled to ground at the IC (within 1" max) with a 10
/-tF tantalum and a 0.1 /-tF ceramic. Tantalum capacitors
are recommended since electrolytic capacitors simply
have too much inductance at the frequencies of interest.
The quality of the VCC and VEE supplies should then
be checked at the IC with a high frequency scope. Noise
spikes (always present when digital circuits are present)
can easily exceed 400 mV peak. and if they get into the
analog portion of the IC. the operation can be disrupted.
Noise can be reduced by inserting resistors and/or inductors between the supplies and the IC.
If switching power supplies are used. there will usually be spikes of 0.5 volts or greater at frequencies of
50-200 kHz. These spikes are generally more difficult to
reduce because of their greater energy content. In extreme cases. 3-terminal regulators (MC78L05ACP.
MC7905.2CT). with appropriate high frequency filtering.
should be used and dedicated to the MC10319.
The ripple content of the supplies should not allow
their magnitude to exceed the values in the Recommended Operating Limits.
The PC board tracks supplying VCC and VEE to the
MC10319 should preferably not be at the tail end of the
bus distribution. after passing through a maze of digital
circuitry. The MC10319 should be close to the power
supply. or the connector where the supply voltages enter the board. If the VCC and VEE lines are supplying
considerable current to other parts of the boards. then
it is preferable to have dedicated lines from the supply
or connector directly to the MC10319.

do not drift more than this amount once set. Over the
temperature range of 0 to 70'C. a maximum temperature coefficient of 28 ppml'C is required.
The voltage supplies used for digital circuits should
preferably not be used as a source for generating VRT
and VRB. due to the noise spikes (50-400 mV) present
on the supplies and on their ground lines. Generally
± 15volts. or ± 12 volts. are available for analog circuits.
and are usually clean compared to supplies used for
digital circuits. although ripple may be present in varying amounts. Ripple is easier to filter out than spikes.
however. and so these supplies are preferred.
Figure 21 depicts a circuit which can provide an
extremely stable voltage to VRT at the current required
(the maximum reference current is 19.2 mA@2.0volts).
The MC1403 series of reference sources has very low
temperature coefficients. good noise rejection. and a
high initial accuracy. allowing the circuit to be built without an adjustment pot if the VRT voltage is to remain
fixed at one value. Using 0.1 % wirewound resistors for
the divider provides sufficient accuracy and stability in
many cases. Alternately. resistor networks provide high
ratio accuracies. and close temperature tracking. If the
application requires VRTto be changed periodically. the
two resistors can be replaced with a 20 turn. cermet
potentiometer. Wirewound potentiometers should not
be used for this type of application since the pot's slider
jumps from winding to winding. and an exact setting
can be difficult to obtain. Cermet pots allow for a
smooth continuous adjustment.
In Figure 21. R1 reduces the power dissipation in the
transistor. and can be carbon composition. The 0.1 /-tF
capacitor in the feedback path provides stability in the
unity gain configuration. Recommended op amps are:
LM358. MC34001 series. LM30BA. LM324. and LM11C.
Offset drift is the key parameter to consider in choosing
an op amp. and the LM308A has the lowest drift of those
mentioned. Bypass capacitors are not shown in Figure
21. but should always be provided at the input to the
2.5 volt reference. and at the power supply pins of the
op amp.
Figure 22 shows a simpler and more economical circuit. using the LM317LZ regulator. but with lower initial
accuracy and temperature stability. The op amp/current
booster is not needed since the LM317LZ can supply the
current directly. In a well controlled environment. this
circuit will suffice for many applications. Because of the
lower initial accuracy. an adjustment pot is a necessity.
Figure 23 shows two circuits for providing the voltage
to VRB. The circuits are similar to those of Figures 21
and 22. and have similar accuracy and stability. The
output transistor is a PNP in this case since the circuit
must sink the reference current.

The four ground pins (2. 12. 16. 22) must be connected
directly together. Any long path beween them can cause
stability problems due to the inductance (@25 MHz) of
the PC tracks. The ground return for the signal source
must be noise free.
REFERENCE VOLTAGE CIRCUITS
Since the accuracy ofthe conversion is directly related
to the quality of the references. it is imperative that accurate and stable voltages be provided to VRTand VRB.
If the reference span is 2 volts. then 1/2 LSB is only 3.9
millivolts. and it is desireable that VRT and VRB be accurate to within this amount. and furthermore. that they

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
6-36

MC10319
VIDEO APPUCATIONS

conversion. If the references are to be symmetrical
about ground (e.g., :!: 1.0 volt), the adjustment can be
eliminated, and the midpoint connected to ground.
The use of latches on the outputs is optional, depending on the application.

The MC10319 is suitable for digitizing video signals
directly without signal conditioning, although the standard 1 volt Pop video signal can be amplified to a 2_0
volt Pop signal for slightly better accuracy. Figure 24
shows the input (top trace) and reconstructed output of
a standard NTSC test signal, sampled at 25 MSPS, consisting of a sync pulse, 3.58 MHz color burst, a 3.58 MHz
signal in a Sin 2x envelope, a pulse, a white level signal,
and a black level signal. Figure 25 shows a Sin 2x pulse
that has been digitized and reconstructed at 25 MSPS.
The width of the pulse is =450 ns at the base. Figure 26
shows an application circuit for digitizing video.

50 MHz, 8-BIT AID CONVERTER
Figure 28 shows how two MC10319s can be connected together in a flip-flop arrangement in order to
have an effective conversion speed of 50 MHz. The
74F74 Ootype flip-flop provides a 25 MHz clock to each
converter, and at the same time, controls the ENABLES
so as to alternately enable and disable the outputs. The
Overranges do not have 3-state capability, and so cannot be paralleled. Instead they are OR'd together. The
use of latches is optional, and depends on the application. Data should be latched, or written to RAM (in
a OMA operation), on the high-to-Iow transition of the
50 MHz clock.

9-BIT AID CONVERTER
Figure 27 shows how two MC10319s can be connected to form a 9-bit converter. In this configuration,
the outputs (07-00) of the two 8-bit converters are paralleled. The outputs of one device are active, while the
outputs of other are in the 3-state mode. The selection
is made by the Overrange output ofthe lower MCI 0319,
which controls Enable inputs on the two devices. Additionally, this output provides the 9th bit.
The reference ladders are connected in series, providing the 512 steps required for 9 bits. The input voltage range is determined by VRT of the upper MC10319,
and VRB of the lower device. A minimum of 1.0 volt is
required across each converter. The 500 !l pot (20 turn
cermet) allows for adjustment of the midpoint since the
reference resistors of the two MC10319s may not be
identical in value. Without the adjustment, a non-equal
voltage division would occur, resulting in a nonlinear

FIGURE 16 -

Video
Signal
(See Below)

NEGATIVE VOLTAGE REGULATOR
In the cases where a negative power supply is not
available - neither the - 3.0 to - 6.0 volts, nor a higher
negative voltage from which to derive it - the circuit
of Figure 29 can be used to generate - 5.0 volts from
the + 5.0 volts supply. The PC board space required is
small (=2.0 in 2), and it can be located physically close
to the MC10319. The MC34063 is a switching regulator,
and in Figure 29 is configured in an inverting mode of
operation. The regulator operating specifications are
also given.

DIFFERENTIAL PHASE AND GAIN TEST

HDS-1250
12-Bil D/A

MC10319
OUT

1.024
Vp _p

to
Analyzer

Clock----....- - - - - - - -.....

---------------------------------------------L-VRB

Video Input Signal
-Input waveform: 571.4 mV p•p sine wave (fv 3.579545 MHz. de
levels as shown above.
- MC10319 clock at 14.31818 MHz (4x) asynchronous to input.
- Differential gain: p-p output (jp each IRE level compared to
that at 0 IRE.
- Differential phase: Phase @ each IRE level compared to that
(w 0 IRE.

MOTOROLA LlNEARIiNTERFACE ICs DEVICE DATA
6-37

MC10319

FIGURE 17 -

MC10319
VCC(D) (+5.0 V)

11,17

-------

ECl-to-TTl
Converter

and
latches

3

------

D
I

F
F

13

E
R
E
N
T
I

S

4
5

T
A
T
Gray
Code
to
Binary
Converter

A
l
l

6
7

E

A
T
C
H

L

8

C
I
R
C
U
I
T

9
10
21

A
R
R

A
Y

Reference
Resistor
ladder
130 n
R
256
0.508 n

2,12,16,22

18

19

20

Enable
Clock (0-25 MHz)

Enable

>-------1

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

6-38

OR

07
06
05
D4
D3
D2
01
00

TTL
Outputs

MC10319
FIGURE 18 -

ADJUSTING VRM FOR IMPROVED LINEARITY

FIGURE 21 -

PRECISION VRT VOLTAGE SOURCE

+ 5.0 V 0---"--4---'----,
R1

25 MHz
Clock
VRT
500

n

ClK

OR

VRT

D7

100
620

n for

n for

+5.0 V
+ 15 V

• Data
• } 0","",
•
• •
DO
•
•
•

VRM
0.1;;t:

VRB

=

to
VRT

VRB
Input
Signal

Vin

VEE

GND

-5.2 V
10 /LF
2.5 V References

FIGURE 19 -

CONVERSION SEQUENCE

MC1403U MC1403AU

line Regulation

0.5 mV

TC (ppmrC) max

40

25

to Vout for 0-70'C

7.0 mV

4.4mV

::tl%

±1%

Initial Accuracy

0.5 mV

~

~rator

Outputs latched
(Valid data available after tCKDV)

FIGURE 22 -

latches Comparator Outputs,
Opens Data Output latches

VRT, VOLTAGE SOURCE

+5.0 to 0--1~--l
L"...,...
1._2_5_tO......
2_.0_0_V_ _ to VRT
+40 V
In lM317lZ 'but
Adj.

Data Outputs latched, Releases
Comparator Latches

240

510

200

FIGURE 20 -

ENABLE TO OUTPUT CRITICAL TIMING

LM317LZ
Line Regulation

EN~
-1121-

l1.0/LF

-1211;;

DO-D7~

60

toVout for 0-70'C

8.4 mV

Initial Accuracy

Timing (li,' 07-00 measured where waveform starts to change.
Indicated time values are typical @.J 25°C, and are in ns.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

6-39

1.0 mV

TC (ppm/'C) max

±4%

MC10319
FIGURE 23 -

VRB VOLTAGE SOURCES

0.1

I -5.0to
I -40V

I

R2
- 5.0 to -40 V

~O.I

Line Regulation

R2 = 620 n for -5.0 V
3.0 kG for -15 V

I'O/LF . .

I
I
I
I
I
I

0----------------'

RI = 100 n for -5.0 V
620 n for -15 V

In r-L-M-3-37-M-T-'Out - 1.25 to- 2.00 V to
VRB
120
A_d_j._ _~

100

I
MCI400G2

LM337MT

1.0mV

1.0mV

TC (ppmI"C) max

25

48

<1Vout for 0-70°C

4.4mV

6.7mV

Initial Accuracy

±0.2%

±4%

FIGURE 24 - COMPOSITE VIDEO WAVEFORM

FIGURE 25 - SIN2 X WAVEFORM

INPUT

OUTPUT

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

6-40

I'·O/LF

270

MC10319

FIGURE 26 - APPLICATION CIRCUIT FOR DIGITIZING VIDEO

+ 5.0 V o - - - - - - - - - < J - - . _ - -.....- - - - .
14.3 MHz Clock ; r - - - - - ,

MC10319

Output
Data

GND

1.5 kll
620 II
3.0

kll

0.1~

-2.5 V

1/2W

-15VO-~--~-----~---"

3.0 pF
1.0

Video Input
(1 Volt pop)

~

/L F

NOTES: 1) MC34080's powered from ± 15 V
supplies. MC34083 (Dual) may be used.
2) Bypass capacitors required at
power supply pins of ALL IC's.
3) Ground plane required over all
parts of circuit board.
4) Care in layout around MC34080's
necessary for good frequency
response.

kll

25 II

,----,1---""""--._.,

51 A 1

~

MC34002.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
6-41

MC10319

FIGURE 27 -

9-BIT AID CONVERTER

GNO

-=-

0-25 MHz
Clock
+2.0V

r

EN

OR

CLK

07

VRT

0.1

MC10319

••
•

•

VRM

DO

VRB

EN

Yin VEE VCC(O) VCC(A)
0.1

500 !l

~
ClK

-2.0 V

t

0.1

VEE VCC(O) VCC(A)
VRT
VRM
VRB

08

07

07

•
•
••

Yin
+5.0 V

OR

OR
MC10319

ClK

Yin

EN

DO

EN
GNO

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
6-42

DO
latches
(Optional)

MC10319
FIGURE 28 - 50 MHz 8-BIT AID CONVERTER

50 MHz
Clock

~
CK
o

Q

74F74'5~

GNO

EN

EN

OR
D7

ClK
+1.0V
0.1

.,rf-

•
•
••
DO

MC10319
(#1)

VRT

h

VRM
VRB

+5.0V
Vin VEE VCC(O)' VCC(A)

1$"'
$"'

5.2 V

EN VEE VCC(OI'VCC(A)

-

VRT

-fci~
-1.0V

VRM

OR

OR
VRB

,--

MC10319
(#2)

ClK

Vin

74F32

07

::

•
•
•
•
DO

Vin
+5.0 V 0 - - - EN

=

----

GNO

--L

07

•
•
•
••
DO

trtches

(Optional)

50 MHz Clock

r--

Q~
,

I

00-07 #l-T-{valid

I

I

~

00-07 #2

oata)---~---~
I

@%B>----~

FIGURE 29 -

-5.0 VOLT REGULATOR

Vin
(+4.5 to + 5.5 V)
100/LF

1

2.2

6 7

n

8

2

MC34063

4.5 V < Vin < 5.5 V.
lout = 10 rnA

0.16%

load Regulation

Vin = 5.0 V. 8.0 rnA <
lout < 20 rnA

0.4%

Output Ripple

Vin

Short Circuit lout Vin
11540/LH

3.0

Line Regulation

Efficiency

Vin

5.0 V. lout = 20 rnA
= 5.0 V. Rl = 0.1 n
= 5.0 V. lout = 50 rnA

=

kn
Vout
~--r..,......n...-<""'-"'-5.0

470 /L F

J

J

V/20 rnA

470 /LF

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
6-43

2 rnV p _p
140 rnA
52%

MC10319
GLOSSARY
LOAD REGULATION - The ability of a voltage regulator
to maintain a certain output voltage as the load current
is varied. The error is typically expressed as a percent
of the nominal output voltage.

APERTURE DELAY - The time difference between the
sampling signal (typically a clock edge) and the actual
analog signal converted. The actual signal converted
may occur before or after the sampling signal, depending on the internal configuration of the converter.

MONOTONICITY - The characteristic of the transfer
function whereby increasing the input code (of a DAC),
orthe inputsignal (ofan A-D), results in the output never
decreasing.

BIPOLAR INPUT - A mode of operation whereby the
analog input (of an A-D), or output (of a DAC), includes
both negative and positive values. Examples are -1.0
to + 1.0 V, -5.0 to +5.0 V, -2.0 to +8.0 V, etc.

MSB - Most Significant Bit. It is the highest order bit
of a binary code.

BIPOLAR OFFSET ERROR - The difference between the
actual and ideal locations of the OOH to 01 H transition,
where the ideal location is 1/2 LSB above the most negative reference voltage.

NATURAL BINARY CODE - A binary code defined by:
N = An2n + ... + A323 + A222 + A121 + A020
where each UAU coefficient has a value of 1 or O. Typically, all zeroes correspond to a zero input voltage of
an A-D, and all ones correspond to the most positive
input voltage.

BIPOLAR ZERO ERROR - The error (usually expressed
in LSBs) of the input voltage location (of an A-D) of the
SOH t081H transition. The ideal location is 1/2 LSB above
zero volts in the case of an A-D setup for a symmetrical
bipolar input (e.g., -1.0 to + 1.0 V).

NYQUIST THEORY DIFFERENTIAL NONLINEARITY - The maximum. deviation in the actual step size (one transition level to
another) from the ideal step size. The ideal step size is
defined as the Full Scale Range divided by 2n (n = number of bits). This error must be within ± 1 LSB for proper
operation.
ECL -

See Sampling Theorem.

OFFSET BINARY CODE - Applicable only to bipolar input (or output) data converters, it is the same as Natural
Binary, except that all zeroes correspond to the most
negative input voltage (of an A-D), while all ones correspond to the most positive input.
POWER SUPPLY SENSITIVITY - The change in a data
converter's performance with changes in the power
supply voltage(s). This parameter is usually expressed
in percent of full scale versus t!N.

Emitter coupled logic.

FULL SCALE RANGE (ACTUAL) - The difference between· the actual minimum and maximum end points
of the analog input (of an A-D).

QUANTITIZATION ERROR - Also known as digitization
error or uncertainty. It is the inherent error involved in
digitizing an analog signal due to the finite number of
steps at the digital output versus the infinite number of
values at the analog input. This error is a minimum of
±1/2 LSB.

FULL SCALE RANGE (IDEAL) - The difference between
the actual minimum and maximum end points of the
analog input (of an A-D), plus one LSB.
GAIN ERROR - The difference between the actual and
expected gain (end point to end point), with respect to
the reference, of a data converter. The gain error is usually expressed in LSBs.

RESOLUTION - The smallest change which can be discerned by an A-D converter, or produced by a DAC. It
is usually expressed as the number of bits, n, where the
converter has 2n possible states.

GREY CODE - Also known as reflected binary code, it
is a digital code such that each code differs from adjacent codes by only one bit. Since more than one bit is
never changed at each transition, race condition errors
are eliminated.

SAMPLING THEOREM - Also known as the Nyquist
Theorem. It states that the sampling frequency of an
A-D must be no less than 2x the highest frequency (of
interest) of the analog signal to be digitized in order to
preserve the information of that analog signal.

INTEGRAL NONLINEARITY - The maximum error of
an A-D, or DAC, transfer function from the ideal straight
line connecting the analog end points. This parameter
is sensitive to dynamics, and test conditions must be
speCified in order to be meaningfull. This parameter is
the best overall indicator of the device's performance.

UNIPOLAR INPUT - A mode of operation whereby the
analog input range (of an A-D), or output range (of a
DAC), includes values of a signal polarity. Examples are
o to +2.0 V, 0 to -5.0 V, +2.0 to +8.0 V, etc.

LSB - Least Significant Bit. It is the lowest order bit of
a binary code.

UNIPOLAR OFFSET ERROR - The difference between
the actual and ideal locations of the OOH to 01 H transition, where the ideal location is 1/2 LSB above the
most negative input voltage.

UNE REGULATION - The ability of a voltage regulator
to maintain a certain output voltage as the input to the
regulator is varied. The error is typically expressed as
a percent of the nominal output voltage.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
6-44

-

MOTOROLA

SEMICONDUCTOR - -_ _ __

MC10321

TECHNICAL DATA

HIGH SPEED 7·BIT ANALOG·TO·DIGITAL
FLASH CONVERTER

HIGH SPEED
7·BIT ANALOG·TO·DIGITAL
FLASH CONVERTER
SILICON MONOLITHIC
INTEGRATED CIRCUIT

The MC10321 is a 7·bit high speed parallel flash AID converter,
which employs an internal Grey Code structure to eliminate large
output errors on fast slewing input signals. It is fully TTL com·
patible, requiring a + 5.0 volt supply, and a negative supply
between - 3.0 and - 6.0 volts. Three-state TTL outputs allow
direct connection to a data bus or common 110 memory.
The MC10321 contains 128 parallel comparators wired along a
precision input reference network. The comparator outputs are
fed to latches, and then to an encoder network which produces
a 7-bit data byte, plus an overrange bit. The data is latched and
converted to three-state LSTTL levels. Enable inputs permit setting the outputs to a three-state condition. The overrange bit is
always active to allow for sensing of the overrange condition, and
to ease the interconnection of two MCl 0321 s into an 8-bit
configuration.
The MC10321 is available in a 20-pin standard plastic and SOIC
packages.
'
Applications include Video displays (digital TV, picture-inpicture, special effects), radar processing, high speed instrumentation, and TV broadcast.

P SUFFIX
PLASTIC PACKAGE
CASE 738

OW SUFFIX
PLASTIC PACKAGE
CASE 7510
150-20)

PIN CONNECTIONS

• Internal Grey Code for Speed and Accuracy

ITop View)

• 25 MHz Sampling Rate
• 7-Bit Resolution with 8-Bit Accuracy
• Easily Cascadable into an 8-Bit System

02

• Three-State LSTTL Outputs with True and Complement
Enable Inputs

D1

• Low Input Capacitance: 25 pF

DO

• No Clock Kick-Out Currents on Input or Reference

Gnd

• Wide Input Range: 1.0-2.1 Volts within a ±2.1 Volt Range
• No Sample and Hold Required for Video Applications
• Edge Triggered Conversion -

VCC(D)

No Pipeline Delay

Clock

• True and Complement Enable Inputs for Three-State Control
• Standard DIP and Surface Mount Packages Available
• Operating Temperature Range: -40' to +85'C

EN

Over
Range
VCC(D)

Gnd

ORDERING INFORMATION

Device

MC10321P
MC10321DW

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
6-45

Temperature
Range
- 40' to

+ 85'C

Package
Plastic DIP
50-20

MC10321

BLOCK DIAGRAM
VCC(O)

(Analog In) Yin

Gnd

o--J=:::;--"jt:t------::t::1t"---------,

VRT

[.!!ias..,J

..----r---I..--,
I

I
I

~

r--~u~:--l

)

I

I
I

I
I

_ >

I

.!!!

~I ~1 I~I

E

li
is .!l

I
I
I

_oJ

..

MC10321

I Il g

I

Over
Range

latches
and
ECl-TIl
Converters

06
05
D4

03

Cll-

I

I

I

02

I

I

II
I

DO

L ___ .l

01

Enable

Clock

ABSOLUTE MAXIMUM RATINGS
Parameter

Symbol

Value

Units

Supply Voltage

VCC(A), VCC(O)
VEE

+7.0
-7.0

Vdc

Positive Supply Voltage Differential

VCC(O)~VCC(A)

-0.3, +0.3

Vdc

Digital Input Voltage (Pins 13-15)

VI(Oj

-0.5, +7.0

Vdc

Analog Input Voltage (Pins 5, 6, 7)

VI(AI

-2.5, +2.5

Vdc

+2.3

Vdc

Applied Output Voltage (00-06 in 3-State)

-

-0.3, +7.0

Vdc

Junction Temperature

TJ

+150

·C

Storage Temperature

TstR

-65, +150

·C

Reference Voltage Span (Pin 7-Pin 5)

Devices should not be operated at these values. The "Recommended Operating Limits" provide guidelines for actual

device operation.

RECOMMENDED OPERATING UMITS
Parameter

Symbol

Min

Typ

Max

Units

VCC(A)
VCC(O)
Il.VCC

+4.5
+4.5
-0.1

+5.0
+5.0
0

+5.5
+5.5
+0.1

Vdc

-5.0

Power Supply Voltage (Pin 9)
Power Supply Voltage (Pins 10, 16)
VCCIDI-VCCIA)
Power Supply Voltage (Pin 8)

VEE

-6.0

Digital Input Voltages (Pins 13-15)

-:-

0

Analog Input (Pin 6)

Yin

-2.1

Voltage @ VRT (Pin 7)
@VRB(Pin5)
VRT-VRB
VRB-VEE

VRT
VRB
Il.VR

-

-1.0
-2.1
+1.0
1.3

Applied Output Voltage (Pins 00-06 in 3-State)

Vo

0

Clock Pulse Width - High
-low

tCKH
tCKl

5.0
15

Clock Frequency

fClK

0

TA

-40

Operating Ambient Temperature
All

limits are not necessarily functional concurrentlv.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
6-46

-

-

-3.0

Vdc

VCC(O)

Vdc

+2.1

Vdc

+2.1
+1.0
+2.1

Vdc

VCC(OI

Vdc

-

ns

25

MHz

+85

"C

-

MC10321

ELECTRICAL CHARACTERISTICS (TA = + 25°C, VCC = 5.0 V, VEE
except where noted)

= - 5.2 V, VRT =

+ 1.0 V, VRB

=-

1.0 V,

Characteristic
TRANSFER CHARACTERISTICS (!CKL = 25 MHz)
Resolution

N

-

-

7.0

Bits

±1.0
±1.0

LSB

Monotonicity

MON

Integral Nonlinearity
Differential Nonlinearity

INL
DNL

-

±1/4

Differential Phase (See Figure 11)
Differential Gain (See Figure 11)

DP
DG

-

-

2.0
2.0

-

-

0.02
0

-

+1.0
+60

+5.0
+150

Cin

-

22

VOS

-

0.1

-

Ladder Resistance (VRT to VRB, TA = 25°C)

Rre!

100

140

175

Temperature Coefficient

TC

-

+0.29

-

%fC

Cre!

-

5.0

-

pF

Input Voltage - High
-Low

VIHE
VILE

2.0

-

-

V

-

0.8

Input Current @ 2.4 Volts (See Figure 5)
@ 0.4 Volts (See Figure 5)

IIHE
IILE

-200

+0.2
-120

Input Clamp Voltage (11K

VIKE

-1.5

-1.3

Input Voltage - High
-Low

VIHC
VILC

2.0
-

Input Current @ 0.4 V (See Figure 6)
@ 2.7 V (See Figure 6)

IILC
IIHC

-150
-80

-80
-40

Input Clamp Voltage (11K

VIKC

-1.5

High Output Voltage (lOH = -400 p.A @ 06-00, OR,
VCC = 4.5 V, See Figure 7)

VOH

Low Output Voltage (lOL = 4.0 rnA @ 06-00, OR,
VCC = 4.5 V, See Figure 8)

VOL

Power Supply Rejection Ratio
(4.5 V < VCC < 5.5 V, VEE = - 5.2 V)
(-6.0 V < VEE < -3.0 V, VCC = +5.0 V)

PSRR

Guaranteed

-

Bits

-

Deg.
%
LSBN

ANALOG INPUT (Pin 6)
Input Current @ Vin
@ Vin

= VRB
= VRT

Input Capacitance (1.0 V

- 0.1 V (See Figure 4)
+ 0.1 V (See Figure 4)

IINL
IINH

< (VRT - VRB) < 2.0 V)

Bipolar Offset Error

p.A
pF
LSB

REFERENCE

Ladder Capacitance (Pin 1 Open)
ENABLE INPUTS (VCC

n

= 55 V)

=

-18 rnA)

-

2.0

p.A

-

V

-

Vdc

CLOCK INPUT (VCC = 55 V)

=

-18 rnA)

-

0.8

-1.3

-

Vdc

2.4

3.0

-

V

-

0.3

0.4

V

-

-35

p.A

DIGITAL OUTPUTS

Output Short Circuit Current' (06-00, OR, VCC

=

5.5 V)

ISC

Output Leakage Current (0.4 < Vo < 2.4 V,
See Figure 3, VCC = 5.5 V, 00-06 in 3-State Mode)

ILK

Output Capacitance (00-06 in 3-State Mode)

Cout

-10

-

5.0

+10

-

rnA
p.A
pF

*Only one output to be shorted at a time, not to exceed 1 second.

POWER SUPPLIES
VCC(A) Current (4.5 V < VCC(A) < 5.5 V, Outputs Unloaded)
VCC(D) Current (4.5 V < VCC(D) < 5.5 V, Outputs Unloaded)
VEE Current (-6.0 V < VEE < -3.0 V)

ICC(A)
ICC(D)
lEE

Power Dissipation (VRT - VRB = 2.0 V, Outputs Unloaded)

Po

10
40
-16

-

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

6-47

13
60
-13

16
80
-8.0

rnA

459

668

mW

MC10321
TIMING CHARACTERISTICS (TA = 25'C, VCC = + 5.0 V, VEE
See System Timing Diagram)
Parameter

= - 5.2 V, VRT =
Symbol

+ 1.0 V, VRB

=

-1.0 V,

Min

Typ

-

5.0
15

Max

Units

INPUTS

Max Clock Rise, Fall Time

tR F

-

100

-

Clock Frequency

fCLK

0

30

25

MHz

22

-

ns

Min Clock Pulse Width - High
-Low

tCKH
tcKL

ns
ns

OUTPUTS
New Data Valid from Clock Low

-

tCKDV

Aperture Delay

-

tAD

Hold Time

tH

Data High to 3-State from Enable Low"

tEHZ

Data Low to 3-State from Enable Low"

tELZ

Data High to 3-State from ENABLE High"

tE'HZ

Data Low to 3-State from ENABLE High"

tE'LZ

Valid Data from Enable High (Pin 14 = 0 V)"

tEDV

Valid Data from ENABLE Low (Pin 13 = 5.0 V)"

tE'DV

Output Transition Time (10%-90%)"

ttr

-

ns
ns

27

-

19

-

ns

3.0
6.0
22

17

20

-

6.0

-

13

ns
ns
ns
ns
ns
ns

·See Figure 2 for output loading.

TEMPERATURE CHARACTERISTICS
Parameter

Typical Value
@25"C

Typical Change
- 40 to + 85"C

73mA
-13mA
1400
0.3 V
3.0 V

-100 !LAI"C
+ 7.0 !LAI"C
+0.29%1'C
+8.0/LVrC
2.1 mVrC
- 0.0008 LSBrC
-0.001 LSBrC

ICC (+5.0 V Supply Current)
lEE (-5.2 V Supply Current)
Ladder Resistance
VOL (Output Low Voltage @ 4.0 mAl
VOH (Output High Voltage @ -400,.A)
Differential Nonlinearity
Integral Nonlinearity

0.25 LSB
PIN DESCRIPTIONS

PIN DESCRIPTIONS
Symbol

Pin

Symbol

Description

Pin

Description

VCC(A)

9

Power supply for the analog section.
+ 5.0 V, ± 10% required.

CLK

15

Overrange output. Indicates Yin is more
positive than VRT-1/2 LSB. This output
does not have 3-state capability, and therefore is always active.

Clock input, TTL compatible, and can
range from dc to 25 MHz. Conversion
occurs on the negative edge of the clock.

EN

13

D6-DO

1-4, Digital Outputs. 06 (Pin 4) is the MSB, DO
16-20 (Pin 18) is the LSB. LSTTL compatible with
3-state capability.

Enable input. TTL compatible, a Logic "1"
(and Pin 14 a Logic "0") enables the data
outputs. A Logic "0" sets the outputs
(except Overrange) to a 3-state mode.

Eli!

14

EIiIAm

VCC(D)

10,16 Power supply for the digital section.
+5.0 V, ± 10% required.

VEE

8

Negative Power supply. Nominally - 5.2 V,
it can range from - 3.0 to - 6.0 V, and must
be more negative than VRB by >1.3 V.

VRB

5

The bottom (most negative point) of the
internal reference resistor ladder. The ladder resistance is typically 140 0 to VRT.

Yin

6

Signal voltage input. This voltage is compared to the reference to generate a digital
equivalent. Input impedance is nominally
16-33 kfl (See Figure 4) in parallel with 22
pF.

VRT

7

The top (most positive point) of the internal reference resistor ladder.

GND

OR

11,17 Power supply ground. The two pins should
be connected directly together, and
through a low impedance path to the
power supply.
12

input. TTL compatible, a Logic
"0" (and Pin 13 a Logic "1") enables the
data outputs. A Logic "1" sets the outputs
(except Overrange) to a 3-state mode.

Pin assignments are the 88me for the standard DIP package and the
surface mount package.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

6-48

MC10321

FIGURE 1 -

!-tCKH-----!'
Clock

tCKL-.j

~I

1/-

SYSTEM TIMING DIAGRAM

1/~-------,\----3.ov

-T
_ _ _ _ _---J+ 1.5 V
1,-_1._5V

...:J 1.5 V

-T
'__
1.5_V_ _ _ __
1

tCKDV and tH measured at output levels of 0.8 and 2.4 volts.

---yEN

1.2 V

3.0V

-\--~_;,...-------::Ij--l-1.2 V

tEHZ
High Data
Output

tELZ
Low Data
Output

FIGURE 2 -

DATA OUTPUT TEST CIRCUIT

VCCo----,
1.0 k

00-07

>--..--...

Diodes

~

1N914 or equivalent, C1 = 15 pF

MOTOROLA LlNEARIiNTERFACE ICs DEVICE DATA

6-49

MC10321

FIGURE 3 - OUTPUT 3-STATE LEAKAGE CURRENT
200

I

100

1
!Z

,

FIGURE 4 - INPUT CURRENT @ Vin
80

1

J

60

./

I-

50

i'5

40

~

!!1

a

:::>
u

L

~ -50

/'

l-

ii'

20

;;;
~

~ -100

V

V
(

I

-200
-1.0

1.0

2.0

3.0

4.0

5.0

6.0

- 2.5

7.0

VRB

APPLIED VOLTAGE (VOLTS)

I

~

-70

-110
-130

I

-

I
I
L

I?--

~

l-

LPin 13 (EN = 0)
Pin 114 (0"1 EN 
u

I

I/'"

V

I-

II

I

-50

;;;
-90
~

./'
./

.5 -20

/

I-

z

,..../

II
;<;

1 -30
~
a:
:::>
u

+20

./

Pin 13
(EN = +5.0 V)

+ 2.5

FIGURE 6 - CLOCK INPUT CURRENT

FIGURE 5 - INPUT CURRENT AT ENABLE, ENABLE
10
0
-10

VRT
Vin.INPUT VOLTAGE (VOLTS)

>

~

- I--

~

V

00.1
~

~

o
o

-100

-200
-300
IOH. OUTPUT CURRENT (!LA)

-400

°o

2.0

4.0
IOL. OUTPUT CURRENT (rnA)

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
6-50

6.0

8.0

MC10321

FIGURE 9 - INTEGRAL LINEARITY ERROR IN LSBs
versus CODE

FIGURE 10 - DIFFERENTIAL LINEARITY ERROR
IN LSBs versus LOWER CODE

1.0

1.0

0.6

0.6

o. 2

m

I\..

o
25

I"-'\.

-0. 2

A.

V

W

V

i- o.

-1.0

-1.0
16

32

48

64

80

96

112

V·'"

.M

V."\

A.l

~""

...

'

.IL

~

A

roy

v

V

' .... V'

-0.6

'eLK ~ 25 MSPS

o

.. f\.

2

ffi

-0.6

0.2

'"

1\.

128

fCLK ~ 25 MSPS

o

16

32

48

CODE

64

80

96

112

128

CODE

DESIGN GUIDELINES
(see Figure 4). However, Vin must be maintained within
the absolute range of ± 2.5 volts (with respect to
ground) - otherwise excessive currents will result at
Pin 6.
The input capacitance at Pin 6 is typically 22 pF, and
is constant as Vin varies from VRT to VRB·
The source impedance of the signal voltage should
be maintained below 100 n (at the frequencies of interest) in order to avoid sampling errors.

INTRODUCTION
The MC10321 is a high speed, 7-bit parallel ("Flash")
type Analog-to-Digital converter containing 128 comparators at the front end. See Figure 12 for a block diagram. The comparators are arranged such that one
input of each is referenced to evenly spaced voltages,
derived from the reference resistor ladder. The other
input of each of the comparators is connected to the
input signal (Vin). Some of the comparator's differential
outputs will be "true," while other comparators will
have "not true" outputs, depending on their relative
position. Their outputs are then latched, and converted
to a 7-bit Grey code by the Differential Latch Array. The
Grey code ensures that errors caused at the input stage,
due to cross talk, feed-thru, or timing disparaties, result
in glitches at the output of only a few LSBs, rather than
the more traditional 1/2 scale and 1/4 scale glitches.
The Grey code is then translated to a 7-bit binary code,
and the differential levels are translated to TTL levels
before being applied to the output latches. ENABLE
inputs (EN and EN) at this final stage permit the TTL
outputs (except Over range) to be put into a high impedance (3-state) condition.

REFERENCE
The reference resistor ladder is composed of a
string of equal value resistors so as to provide 128
equally spaced voltages for the comparators (see Figure 12 for the actual configuration). The voltage difference between adjacent comparators corresponds
to 1 LSB ofthe input range. The first comparator (closest to VRB) is referenced 1/2 LSB above VRB, and the
128th comparator (for the overrange) is referenced 1/
2 LSB below VRT. The total resistance of the ladder is
nominally 140 n, ±25%, requiring 14.3 mA@2.0volts
and 7.14 mA@ 1.0 volt. There is a nominal warm up
change of = + 8.0% in the ladder resistance due to the
+ 0.29%rC temperature coefficient.
The minimum recommended span [VRT - VRBI is 1.0
volt. A lower span will allow offsets and nonlinearities
to become significant. The maximum recommended
span is 2.1 volts due to power limitations of the resistor
ladder. The span may be anywhere within the range of
-2.1 to +2.1 volts with respect to ground, and VRB
must be at least 1.3 volts more positive than VEE. The
reference voltages must be stable and free of noise and
spikes, since the accuracy of a conversion is directly
related to the quality of the reference.
In most applications, the reference voltages will
remain fixed. In applications inVOlving a varying reference for modulation or signal scrambling, the modulating signal may be applied to VRT, or VRB, or both.
The output will vary inversely with the reference signal,
introducing a nonlinearity into the transfer function. The
addition of the modulating signal and the dc level

ANALOG SECTION

SIGNAL INPUT
The signal voltage to be digitized (Vin) is applied
simultaneously to one input of each of the 128 comparators through Pin 6. The other inputs of the comparators are connected to 128 evenly spaced voltages
derived from the reference ladder. The output code
depends on the relative position of the input signal to
the reference voltages. The comparators havE1 a
bandwidth of >50 MHz, which is more than sufficient
for the allowable (Nyquist theory) input frequency of
12.5 MHz.
The current into Pin 6 varies linearly from 0 (when
Vin = VRB) to =60 p.A (when Vin = VRT). If Vin is taken
below VRB or above VRT, the input current will remain
at the value corresponding to VRB and VRT respectively

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
6-51

MC10321
applied to the reference must be such that the absolute
voltage at VRT and VRB are maintained within the values listed in the Recommended Operating Limits. The
RMS value of the span must be maintained ,;;;2.1 volts.

A summary of the sequence is that data present at
Vin just prior to the Clock falling edge is digitized and
available at the data outputs immediately after that
same falling edge. The minimum amount of time the
data must be present prior to the clock falling edge
(aperture delay) is 2.0-6.0 ns, typically 3.0 ns.
The comparator output latches provide the circuit
with an effective sample-and-hold function, eliminating
the need for an external sample·and-hold.

POWER SUPPLIES

VCC(A) (Pin 9) is the positive power supply for the
comparators, and VCC(D) (Pins 10, 16) is the positive
power supply forthe digital portion. Both are to be + 5.0
volts, ± 10%, and the two are to be within 100 millivolts
of each other. There is indirect internal coupling
between VCC(D) and VCC(A). If they are powered separately, and one supply fails, there will be current flow
through the MC10321 to the failed supply.
ICC(A) is nominally 13 mA, and does not vary with
clock frequency or with Vin' but does vary slightly with
VCC(A). ICC(D) is nominally 60 mA, and is independent
of clock frequency. It does vary, however, by 4-5 mA
as Vin is varied from VRT to VRB, and varies directly
with VCC(D).
VEE is the negative power supply forthe comparators,
and is to be within the range - 3.0 to - 6.0 volts. Additionally, VEE must be at least 1.3 volts more negative
than VRB. lEE is a nominal - 13 mA, and is independent
of clock frequency, Vin and VEE.
For proper operation, the supplies must be bypassed
at the IC. A 10 /LF tantalum, in parallel with a 0.1 /LF
ceramic is recommended for each supply to ground.

ENABLE INPUTS
The two Enable inputs (Pins 13, 14) are TTL compatible, and are used to change the data outputs (D6-DO)
from active to 3-state. This capability allows cascading
two MC10321s into an 8-bit configuration, connecting
the outputs directly to a data bus, multiplexing multiple
converters, etc. See the Applications Information section for more details. For the outputs to be active, Pin
13 must be Logic "1," and Pin 14 must be a Logic "0."
Changing either input will put the outputs into the high
impedance mode. The Enable inputs affect only the
state of the outputs - they do not inhibit a conversion.
Both pins have a nominal threshold of =1.2 volts, their
input currents are shown in Figure 5, and their inputoutput timing is shown in Figure 1 and 14. Leaving
either pin open is equivalent to a Logic "1," although
good design practice dictates that an input should never
be left open.
The Overrange output (Pin 12) is not affected by the
Enable inputs as it does not have 3-state capability.

DIGITAL SECTION
CLOCK
The Clock input (Pin 15) is TTL compatible with a
typical frequency range of 0 to 30 MHz. There is no duty
cycle limitation, but the minimum low and high times
must be adhered to. See Figure 6 for the input current
requirements.
The conversion sequence is shown in Figure 13, and
is as follows:

OUTPUTS
The data outputs (Pins 1-4, 12, 18-20) are TTL level
outputs with high impedance capability (except Overrange). Pin 4 is the MSB (D6), and Pin 18 is the LSB (DO).
The seven outputs are active as long as the Enable
inputs are true (EN = high, EN = low). The timing of
the outputs relative to the Clock input and the Enable
inputs is shown in Figures 1 and 14. Figures 7 and 8
indicate the output voltage versus load current, while
Figure 3 indicates the leakage current when in the high
impedance mode.
The output code is natural binary, depicted in Table 1.

- On the rising edge, the data output latches are
latched with old data, and the comparator output
latches are released to follow the input signal (Vin).
- During the high time, the comparators track the
input signal. The data output latches retain the old data.
- On the falling edge, the comparator outputs are
latched with the data immediately prior to this edge.
The conversion to digital occurs within the device, and
the data output latches are released to indicate the new
data in =22 ns.
- During the clock low time, the comparator outputs
remain latched, and the data output latches remain
transparent.

The Overrange output (Pin 12) goes high when the
input, Vin, is more positive than VRT - 112 LSB. This
output is always active - it does not have high impedance capability. Besides used to indicate an input
overrange, it is additionally used for cascading two
MC10321s to form an 8-bit A/D converter (see Figure
21 ).
TABLE I

VRT, VRB (Volts)
Input
>VRT - 1/2 LSB
VRT - 1/2 LSB
VRT - 1 LSB
VRT - 1 1/2 LSB
Midpoint
VRB + 1/2 LSB
< VRB + 1/2 LSB

2.048,0

+1.0 V, -I.OV

+1.0 V, 0 V

Output
Code

Overrange

>2.040 V
2.040 V
2.032 V
2.024 V
1.024 V
8.0 mV
<8.0 mV

>0.9922 V
0.9922 V
0.9844 V
0.9766 V
0.000 V
-0.9922 V
<-0.9922 V

>0.9961 V
0.9961 V
0.9922 V
0.9883 V
0.5000 V
3.9mV
<3.9 mV

7FH
7FH
7FH
7EH - 7FH
40H
DOH - 01H
OOH

1
0-1
0
0
0
0
0

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

6-52

MC10321
APPLICATIONS INFORMATION
POWER SUPPLIES, GROUNDING
The PC board layout, and the quality of the power
supplies and the ground system at the IC are very
important in order to obtain proper operation. Noise,
from any source, coming into the device on VCC, VEE,
or ground can cause an incorrect output code due to
interaction with the analog portion of the circuit. At the
same time, noise generated within the MC10321 can
cause incorrect operation if that noise does not have a
clear path to ac ground.
Both the VCC and VEE power supplies must be decou·
pled to ground at the IC (within 1" max) with a 10 /LF
tantalum and a 0.1 /LF ceramic. Tantalum capacitors are
recommended since electrolytic capacitors simply have
too much inductance at the frequencies of interest. The
quality of the VCC and VEE supplies should then be
checked at the IC with a high frequency scope. Noise
spikes (always present when digital circuits are present)
can easily exceed 400 mV peak, and if they get into the
analog portion of the IC, the operation can be disrupted.
Noise can be reduced by inserting resistors and/or
inductors between the supplies and the IC.
If switching power supplies are used, there will usu·
ally be spikes of 0.5 volts or greater at frequencies of
50-200 kHz. These spikes are generally more difficult to
reduce because of their greater energy content. In
extreme cases, 3·terminal regulators (MC7SL05ACP,
MC7905.2CT), with appropriate high frequency filtering,
should be used and dedicated to the MC10321.
The ripple content of the supplies should not allow
their magnitude to exceed the values in the Recommended Operating Limits.
The PC board tracks supplying VCC and VEE to the
MC10321 should preferably not be at the tail end of the
bus distribution, after passing through a maze of digital
circuitry. The MC10321 should be close to the power
supply, or the connector where the supply voltages
enter the board. If the VCC and VEE lines are supplying
considerable current to other parts of the boards, then
it is preferable to have dedicated lines from the supply
or connector directly to the MC10321.
The two ground pins (11, 17) must be connected
directly together. Any long path between them can
cause stability problems due to the inductance (@ 25
MHz) of the PC tracks. The ground return for the signal
source must be noise free.

the temperature range of - 40 to + S5'C, a maximum
temperature coefficient of 31 ppm/'C is required.
The voltage supplies used for digital circuits should
preferably not be used as a source for generating VRT
and VRB, due to the noise spikes (up to 500 mV) present
on the supplies and on their ground lines. Generally
± 15 volts, or ± 12 volts, are available for analog circuits,
and are usually clean compared to supplies used for
digital circuits, although ripple may be present in varying amounts. Ripple is easier to filter out than spikes,
however, and so these supplies are preferred.
Figure 15 depicts a circuit which can provide an
extremely stable voltage to VRT at the current required
(the maximum reference current is 20 mA @ 2.0 volts).
The MC1403 series of references have very low temperature coefficients, good noise rejection, and a high
initial accuracy, allowing the circuit to be built without
an adjustment pot if the VRT voltage is to remain fixed
at one value. Using 0.1% wirewound resistors for the
divider provides sufficient accuracy and stability in
many cases. Alternately, resistor networks provide high
ratio accuracies, and close temperature tracking. If the
application requires VRT to be changed periodically, the
two resistors can be replaced with a 20 turn, cermet
potentiometer. Wirewound potentiometers should not
be used for this type of application since the pot's slider
jumps from winding to winding, and an exact setting
can be difficult to obtain. Cermet pots allow for a
smooth continuous adjustment.
In Figure 15, R1 reduces the power dissipation in the
transistor, and can be carbon composition. The 0.1 /LF
capacitor in the feedback path provides stability in the
unity gain configuration. Recommended op amps are:
LM35S, MC34001 series, LM30SA, LM324, and LM11C.
Offset drift is the key parameter to consider in choosing
an op amp, and the LM30SA has the lowest drift of those
mentioned. Bypass capacitors are not shown in Figure
15, but should always be provided at the input to the
2.5 volt reference, and at the power supply pins of the
op amp.
Figure 16 shows a simpler and more economical circuit, using the LM317LZ regulator, but with lower initial
accuracy and temperature stability. The op amp/current
booster is not needed since the LM317LZ can supply
the current directly. In a well controlled environment,
this circuit will suffice for many applications. Because
of the lower initial accuracy, an adjustment pot is a
necessity.
Figure 17 shows two circuits for providing the voltage
to VRB. The circuits are similar to those of Figures 15
and 16, and have similar accuracy and stability. The
MC1403 reference is used in conjunction with an op amp
configured as an inverter, providing the negative voltage. The output transistor is a PNP in this case since
the circuit must sink the reference current.

REFERENCE VOLTAGE CIRCUITS
Since the accuracy of the conversion is directly related
to the quality of the references, it is imperative that
accurate and stable voltages be provided to· VRT and
VRB. If the reference span is 2.0 volts, then 1/2 LSB is
only 7.S millivolts, and it is desireable that VRT and VRB
be accurate to within this amount, and furthermore, that
they do not drift more than this amount once set. Over

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

6-53

MC10321

VIDEO APPLICATIONS
The MC10321 is suitable for digitizing video signals
directly without signal conditioning, although the standard 1.0 volt p-p video signal can be amplified to a 2.0
volt p-p signal for slightly better accuracy. Figure 18
shows the input (top trace) and reconstructed output of
a standard NTSC test signal, sampled at 25 MSPS, consisting of a sync pulse, 3.58 MHz color burst, a 3.58 MHz
signal in a Sin 2x envelope, a pulse, a white level signal,
and a black level signal. Figure 19 shows a Sin 2x pulse
that has been digitized and reconstructed at 25 MSPS.
The width of the pulse is =225 ns at the base. Figure
20 shows an application circuit for digitizing video.

voltage division could occur, resulting in a nonlinear
conversion. If the references are to be symmetrical
about ground (e.g., ± 1.0 volt or ±2.0 volts), the adjustment can be eliminated, and the midpoint connected to
ground.
The use of latches on the outputs is optional, depending on the application. If latches are required,
SN74LS173As are recommended.
50 MHz, 7 BIT AID CONVERTER
Figure 22 shows how two MC10321s can be connected together in a flip-flop arrangement in order to
have an effective conversion speed of 50 MHz. The
74F74D-type flip-flop provides a 25 MHz clock to each
converter, and at the same time, controls the SELECT
input to the MC74F257 multiplexers to alternately select
the outputs of the two converters. A brief timing diagram is shown in the figure.

8-BIT AID CONVERTER
Figure 21 shows how two MC10321s can be connected to form an 8-bit converter. In this configuration,
the outputs (06-00) of the two 7-bit converters are paralleled. The outputs of one device are active, while the
outputs of other are in the 3-state mode. The selection
is made by the OVERRANGE output of the lower
MC10321, which controls Enable inputs on the two
devices. Additionally, this output provides the 8th bit.
The reference ladders are connected in series, providing the 256 steps required for 8 bits. The input voltage range is determined by VRT of the upper MC10321,
and VRB of the lower device. A minimum of 1.0 volt is
required across each converter. The 500 0 pot (20 turn
cermet) allows for adjustment of the midpoint since the
reference resistors of the two MC10321s may not be
identical in value. Without the adjustment, a nonequal

NEGATIVE VOLTAGE REGULATOR
In the cases where a negative power supply is not
available - neither the - 3.0 to - 6.0 volts, nor a higher
negative voltage from which to derive it - the circuit
of Figure 23 can be used to generate - 5.0 volts from
the + 5.0 volts supply. The PC board space required is
small (=2.0 in 2), and it can be located physically close
to the MC10321. The MC34063 is a switching regulator,
and in Figure 23 is configured in an inverting mode of
operation. The regulator operating specifications are
given in the figure.

GLOSSARY
another) from the ideal step size. The ideal step size is
defined as the Full Scale Range divided by 2 n (n =
number of bits). This error must be within ± 1 LSB for
proper operation.

APERTURE DELAY - The time difference between the
sampling signal (typically a clock edge) and the actual
analog signal converted. The actual signal converted
may occur before or after the sampling signal, depending on the internal configuration of the converter.

FULL SCALE RANGE (ACTUAL) - The difference
between the actual minimum and maximum end points
of the analog input (of an A-D).

BIPOLAR INPUT - A mode of operation whereby the
analog input (of an A-D), or output (of a DAC), includes
both negative and positive values. Examples are -1.0
to + 1.0 V, -5.0 to +5.0 V, -2.0 to +8.0 V, etc.

FULL SCALE RANGE (IDEAL) - The difference between
the actual minimum and maximum end points of the
analog input (of an A-D), plus one LSB.

BIPOLAR OFFSET ERROR - The difference between the
actual and ideal locations of the OOH to 01 H transition,
where the ideal location is 1/2 LSB above the most negative reference voltage.

GAIN ERROR - The difference between the actual and
expected gain (end point to end point), with respect to
the reference of a data converter. The gain error is usually expressed in LSBs.

BIPOLAR ZERO ERROR - The error (usually expressed
in LSBs) of the input voltage location (of a 7-bit AID) of
the 40H to 41 H transition. The ideal location is 1/2 LSB
above zero volts in the case of an AID set up for a
symmetrical bipolar input (e.g., -1.0 to + 1.0 V).

GREY CODE - Also known as reflected binary code, it
is a digital code such that each code differs from adjacent codes by only one bit. Since more than one bit is
never changed at each transition, race condition errors
are eliminated.

DIFFERENTIAL NONLINEARITY - The maximum deviation in the actual step size (one transition level to

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
6-54

MC10321

INTEGRAL NONLINEARITY - The maximum error of
an AID, or DAC, transfer function from the ideal straight
line connecting the analog end points. This parameter
is sensitive to dynamics, and test conditions must be
specified in order to be meaningfull. This parameter is
the best overall indicator of the device's performance.

OFFSET BINARY CODE - Applicable only to bipolar
input (or output) data converters, it is the same as Natural Binary, except that all zeroes corresponds to the
most negative input voltage (of an AID), while all ones
corresponds to the most positive input.
POWER SUPPLY SENSITIVITY - The change in a data
converters performance with changes in the power supply voltage(s). This parameter is usually expressed in
percent of full scale versus !lV.

LSB - Least Significant Bit. It is the lowest order bit of
a binary code.
LINE REGULATION - The ability of a voltage regulator
to maintain a certain output voltage as the input to the
regulator is varied. The error is typically expressed as
a percent of the nominal output voltage.

QUANTITIZAnON ERROR - Also known as digitization
error or uncertainty. It is the inherent error involved in
digitizing an analog signal due to the finite number of
steps at the digital output versus the infinite number of
values at the analog input. This error is a minimum of
:to 1/2 LSB.

LOAD REGULATION - The ability of a voltage regulator
to maintain a certain output voltage as the load current
is varied. The error is typically expressed as a percent
of the nominal output voltage.

RESOLUTION - The smallest change which can be discerned by an AID converter, or produced by a DAC. It
is usually expressed as the number of bits, n, where the
converter has 2n possible states.

MONOTONICITY - The characteristic of the transfer
function whereby increasing the input code (of a DAC),
orthe input signal (of an AID), results in the output never
decreasing.

SAMPLING THEOREM - Also known as the Nyquist
Theorem. It states that the sampling frequency of an
AID must be no less than 2x the highest frequency (of
interest) of the analog signal to be digitized in order to
preserve the information of that analog signal.

MSB - Most Significant Bit. It is the highest order bit
of a binary code.
NATURAL BINARY CODE N = An2n

A binary code defined by:

UNIPOLAR INPUT - A mode of operation whereby the
analog input range (of an AID), or output range (of a
DAC), includes values of a single polarity. Examples are
o to + 2.0 V, 0 to - 5.0 V, + 2.0 to + 8.0 V, etc.

+ ... + A323 + A222 + A121 + A020

where each "Au coefficient has a value of 1 or O. Typically, all zeroes corresponds to a zero input voltage of
an AID, and all ones corresponds to the most positive
input voltage.
NYQUIST THEORY -

UNIPOLAR OFFSET ERROR - The difference between
the actual and ideal locations of the DOH to 01 H transition, where the ideal location is 1/2 LSB above the
most negative input voltage.

See Sampling Theorem.

FIGURE " - DIFFERENTIAL PHASE AND GAIN TEST
HDS-1250
12 Bit D/A
D4

Video
Signal
(See Below)

••

DO

Clock

1.024
Vp_p
to
Analyzer

=='---fr-

VRT

2.0 V

----'-1..

- Input waveform: 571.4 mV
pop sine wave @ 3.579545
MHz, de levels as shown.
- MC10321 clock at 14.31818
MHz (4x) asynchronous to
input.
- Differential gain: pop output
@ each IRE level
compared to that at 0 IRE.
- Differential phase: Phase @
each IRE level compared
to that @ 0 IRE.

VIDEO INPUT SIGNAL

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

6-55

FIGURE12~

VRT
VRB

50 V)

MC10321

fVCC(O)(+ .

~4::============11:===========~----~
~ R/2~}- __1
5

_ 10, 16

R

R

~
a~
~
o

~m~

!>r

~ ~~~

VRT~

Converter

'"

,...

..

r-

iT

TIL

I,

0.,"'"

I,

';0'", ,

",

A

o

I"
L
i'

"

m
oQ
m
<

"
A

"""'

,

o

~

I I I"
I

Reference
Resistor
ladder-I

,~",~

"c- '.M' n

~
Ul, ] . .

.,

,-

VEE (-30
. to -6.0 Vaits)

H

';

~ ,,,ctM""
11

10_"

113

15

'0' '"

~

s:

... !,
I,

and

';0

m

m

~,
"'~
~
'oo~rt"! ~

--~OR

Eel to TTL

114
_._

''''''

~~

C>

MC10321

FIGURE 13 -

CONVERSION SEQUENCE

Clock

,~------~v~------~/

L

~

Comparator Outputs Latched
(Valid Data Available After tCKDV)

Latches Comparator Outputs,
Opens Data Output Latches

Data Outputs Latched, Releases Comparator Latches

FIGURE 14 -

ENABLE TO OUTPUT CRITICAL TIMING

FIGURE 15 -

PRECISION VRT VOLTAGE SOURCE

+5.0 to +40 V

Rl

I.
-=-

3-State

0.1

= 91

0 for + 5.0 V
560 Ofor +15V

Rl

r--111.5 k

I

:

I
1.0 kl

I

__

+

I
I

r-!-~L. . . . or /~ _ J
f-

I

2.0k:

iL. __ I
.1

DO-D6---~

Timing @ 06-00 measured where waveform starts
to change. Indicated time values are typical
@ 25'C, and are in ns.

2.5 V References

MC1403U

MC1403AU

Line Regulation

0.5 mV

0.5mV

TC (ppmI'C) max

40

25

AVaut for 0-70'C

7.0 mV

4.4 mV

Initial Accuracy

±1.0%

±1.0%

FIGURE 16 - VRT VOLTAGE SOURCE

+5.0 to +40 V

C

1

.J

l

1.25 to 2.0 V
LM317LZ

f

10 JLF

...----.....2_4-'0

200

p

±

To
VRT

1.0 JLF

510

LM317LZ
Line Regulation

60

AVaut for 0-70'C

8.4 mV

Initial Accuracy

± 4.0%

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

6-57

1.0 mV

TC (ppm/'C) max

MC10321

FIGURE 17 - VRB VOLTAGE SOURCES
+5.0 to +40 V

R1
R1

~

91 n for - 5.0 V
560 n for -15 V
-5.0 to -15 V
MC1403U

MC1403AU

LM337MT

0.5mV

0.5 mV

1.0 mV

TC (ppmI'C) max

40

25

48

aVout for 0-70'C

7.0 mV

4.4 mV

6.7 mV

Initial Accuracy

±1.0%

::t::1.0%

±4.0%

Reference

Line Regulation

FIGURE 18

Input

Output

FIGURE 19

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

6-58

MC10321

FIGURE 20 -

APPLICATION CIRCUIT FOR DIGITIZING VIDEO

+5.0 V
10,16
13

+5.0 V

14

-=

+1.0V

-

15

VCC(D)
EN
EN
ClK

OR

MC10321

06

•
•
••
DO

VRT

Iref

0.1

12
4

••
18

•
•

l

Output
Data

-1.0 V
VRB

7.5 k
6

Vin
VEE

Gnd

8

1', 17
0.1

-6.0
-5.2 V

1.0 I'F '---"YVv-~>-l
Video Input ~ t----'IM.-......-l
(1.0 Volt pop)

ro

-

NOTES: 1) Bypass capacitors required at
power supply pins of ALL IC's.
2) Ground plane required over all
parts of circuit board.
3) A 1 = MC34002.
4) These resistors can be changed
to match signal source impedance.

50n

MOTOROLA LlNEARIiNTERFACE ICs DEVICE DATA

6-59

MC10321

FIGURE 21 -

8·BIT AID CONVERTER

Gnd
EN

0-25 MHz
Clock

OR
elK

06

VRT

•
•
•
•
DO

MC10321

+2.0 V

EN

VRB

+5.0 V
500 n
(Optional
See Text)

Vin
VEE

VCe(D)

VCC(A)

qO.1
10J.LF

.:r. 0.1

-5.2 V

-=

VCe(D)

9°·1

VCC(A)

VRT

-2.0 V
VRB

EN

OR

OR

07

06

06

•
•
•
•
DO

elK
Vin
+5.0 V

Clock

10 J.LF

VEE

Vin

=

EN

DO
3X 74lS173A
latches
(Optional)

Gnd

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

6·60

MC10321

FIGURE 22 - 50 MHz 7 BIT AID CONVERTER

IT

SO MHz Clock

?

~CK
Q
o 74F74 ~

Gnd
EN
CLK

+S.OVo- EN

OR
06
OS
04
03
02
01
00

MC10321
(#1)

~

VRT

+ 1.0 V
~

VRB

-1:0 V

Vin
+S;!!, V

O'~QJ
_

VEE

VCC(O)

MC74F2S7

I----

-

10c
10d
11a
11b
11c
11d

10ILF

In

10ILF

0.1:t:-=r

VEE

VCCIO)

-

S

'--

MC10321
(#2)

OR c-06 !-OS I - 04
03 ~

-

f-

-

CLK

02
01
00

Vin
() Vin

lOa
lOb
10c
10d
11a
11b
11c
11d

~
Q
74F74

I

I

I

Q

--.J

I
I

00-06 #1

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

6-61

OS "

&.

r - - 03 ;

r-- 02 0
r- 01
00

S
Za
Zb
Zc
Zd

MC74F2S7
Gnd

OR
06

'---- 04

T

VRB

~

r--

I

VCC(A)

VRT

+S.OVo-- EN
EN

r----

Za
Zb I - - Zc I - Zd

VCC(A)

-S.2~ -

~

lOa

' - - - - lOb

--

i--

i-i--

r-----

MC10321

FIGURE 23 -

Vin

1

(+4.5 to +5.5 V)

-5.0 VOLT REGULATOR

100
/t F

2.2 n

tTl
8
1

6

7

MC34063
5

J..

3

1
3.0 kn

1.0

4

I

1

"

470'pF

540/tH
2-'1

JI

..

1N5819

k{}

470/tFt

--

1

1.0/tH

= 10 rnA
= 5.0 V. 8.0 rnA < lout < 20 rnA
= 5.0 V. lout = 20 rnA
= 5.0 V. RL = 0.1 n
= 5.0 V. lout = 50 rnA

Line Regulation

4.5 V < Vin < 5.5 V. lout

Load Regulation

Vin

Output Ripple

Vin

Short Circuit lout

Vin

Efficiency

Vin

vout

:f=.

-5.0 V/20 rnA
470 /t F

0.16%
0.4%
2.0 rnV p-p
140 rnA
52%

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

6-62

MOTOROLA

SEMICONCUCTOR _ _ _ __

MC10322

TECHNICAL DATA

Advance Information

a-Bit Video CAC with TTL Inputs
8-BIT VIDEO DAC
with TTL INPUTS

The MC10322 is a 40 MegaSample Per Second (MSPS) 8-bit
Video DAC capable of directly driving a 75 n cable, with appropriate
terminations, to EIA-170 and EIA-343-A video levels. The logic inputs
(data and controls) are TTL compatible. Input registers negate the need
for eX1ernal latches unless the transparent mode is selected.
Video controls (Force High, Blank, Bright, and Sync) permit an easy
interface to standard video systems. The Clock (Convert) inputs can be
differential or single-ended. Complementary outputs are provided for
custom displays or special effects.
The MC10322 is fabricated with Motorola's MOSAICT" process
which provides high speed with low power consumption. The MC10322
is available in a 24 pin plastic DIP package.

SILICON MONOLITHIC
INTEGRATED CIRCUIT

• 40 MSPS Minimum Conversion Rate
• TTL Compatible Inputs
• 8-Bit Linearity
• latched Data and Video Control Inputs, or Transparent Mode
• Video Controls: Force High, Blank, Bright, Sync
PSUFFIX
PLASTIC PACKAGE
CASE 649

• Each Differential Current Outputs Can Swing 2.0 V
• Modulation Capability (Multiplying Mode)
• PSRR >60dB
• Operates from + 5.0 and - 5.2 V Power Supplies
• Power Dissipation: Typically 344 rflW
• Available in 24 Pin Plastic DIP Package
• Available with ECl Inputs (MC10324)

PIN CONNECTIONS

Simplified Block Diagram

04
05

1------------------,

Sync
ConY

r-----__..-L._ Out -

'-.-.--'" '-r-r----r./V"II-

OGnd

VEE

Out +
~VCC
OGnd

Conv

+AGnd
,VEE

~

AGnd

VCC

Comp

Out+

-r--

_-1-:"'::=====---..1

Cony --~------------~

••

~ --~--------------~

Ref +
RefComp

07

I

00-07

FH
BLK
BRT

06

01

L__________________
VEE

I
I
I
I
I

Out-

FH

Ref+

Blank

Ref-

BRT

Sync

~

(Top View)

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

6-63

MC10322
PIN FUNCTION DESCRIPTION
Symbol

Pin

Description

00-07

1-4,
21-24

Data inputs. DO is the LSB and 07 is the MSB. Inputs are TTL compatible. Maximum update
rate is typically 60 MHz. The eight bits control the Gray Scale amplitude only, and do not
involve the Sync or Blank levels.

DGnd

5

Connect to system digital ground. This pin must be within 100 mV of AGnd (Pin 17).

Conv

6

Convert input. The rising edge latches data and controls if FT = O. May be used single-ended
(with Pin 7 at a fixed voltage), or differentially with Pin 7.

Conv

7

Convert input. The falling edge latches data and controls if FT = O. May be used
single-ended (with Pin 6 at a fixed voltage), or differentially with Pin 6.

FT

8

Feedthrough. When high, the internal latches are transparent, and Pins 6 and 7 are unused.
When low, data and controls are latched by Pins 6 and 7.

VCC

9

Connect to + 5.0 V, ± 10%. This pin powers the digital portion of the IC.

FH

10

Force High. A logic high internally sets data inputs = I, overriding external data inputs.

Blank

11

A logic high overrides data inputs, sets the outputs to the video blanking level.

BRT

12

Bright. A logic high increases the Gray Scale output level by =11 %, providing an enhanced
display. Does not affect Sync or Blank.

Sync

13

A logic high overrides all other inputs, and sets the output to video sync level.

Ref-

14

Inverting Reference input. A high impedance input, normally set to a negative DC voltage in
the range of - 0.8 to -1.7 V. Can be used to modulate the output.

Ref +

15

Noninverting Reference input. A virtual ground, current supplied to this pin (between 0.5 and
1.7 mAl sets the maximum output current.

Comp

16

Compensation. A capacitor between this pin and Pin 20 stabilizes the reference amplifier.

AGnd

17

Connect to system analog ground. This pin must be within 100 mVof DGnd (Pin 5).

Out-

18

A high impedance current output. Video voltage levels are produced when connected to a
75 Q cable with appropriate terminations. This output provides a "sync down" waveform. If
unused, connect to Pin 17.

Out +

19

Complementary output provides a "sync up" waveform. If unused, connect to Pin 17.

VEE

20

Connect to - 5.2 V, ± 10%. This supply should be referenced to analog ground.

Figure 1. Test Circuit

I
I
I

37.50

O.U.T.

07

0.4V
or
2.4V

FT
FH

BRT
BLK

Vout-

Out-

00

Vout+

Out +
37.50

Re!-

MC10322
Ref +

Vre!
_1.115mA
1.0k

Sync

Comp
Vee

0.01

JlSl
40MHz

0.1

AGnd

Conv

Ne

-5.2V

VEE

OGnd

Conv

MOTOROLA LINEAR/iNTERFACE les DEVICE DATA
6-64

MC10322
MAXIMUM RATINGS
Characteristics

Value

VCC (with respect to DGnd and AGnd)

Unit

+ 7.0, -0.5

Vdc

DGnd (with respect to AGnd)

-1.0 to + 0.5

Vdc

VEE (with respect to AGnd)

-7.0, + 0.5

Vdc

logic Input Voltage (with respect to DGnd)

-0.5

Vdc

logic Input Voltage (with respect to VCC)

+0.5

Vdc

+ 0.5, VEE

Vdc

Voltage at Reference Amp inputs
Current Into Ref +
Voltage Applied to Out +, Out - (Normal Operation)
Voltage Applied to Out +, Out - (VCC, VEE = 0)
Junction Temperature

+6.0,0

mA

+ 0.5,-2.0

Vdc

+0.5,-1.2

Vdc

-65to+150

°c

..

Devices should not be operated at these values. The ~Recommended Operating Conditions" table provides
conditions for actual device operation.

RECOMMENDED OPERATING CONDITIONS
Symbol

Min

Typ

Max

Unit

Vcc-DGnd
DGnd-AGnd
VEE-AGnd

4.5
-0.1
-5.72

5.0
0
-5.2

5.5
+0.1
-4.68

Vdc

DGnd

-

VCC

Vdc

-

-

rnA

1.7
Vdc

Characteristic
Supply Voltage

logic Input Voltage

Yin

Reference Current (for Video Standard Output)
(for ail other applications)

Iref

Voltage at Ref -

Vref

-1.7

-

-0.8

Output load Impedance

Rl

0

37.5

-

g

Vo

-1.7

-

+ 0.3

Vdc

fs

0
0

60
60

40
40

MHz

VCM

DGnd +1.3

Vdc

-40

-

VCC-2.0

TA

+85

°c

-

1.115

0.5

Output Compliance (with respect to AGnd)
Convert Frequency (FT = 0)
Data Update Frequency (FT = 1)
Convert, Convert Common Mode Range
Operating Ambient Temperature

..

All hmlts are not necessanly functional concurrently.

ELECTRICAL CHARACTERISTICS (TA = 25°C, Iref = 1.115 mA, load =37.5 gto AGnd, VCC = + 5.0 V, VEE =-5.2V, see Figure 1.)

I

I

Characteristic

Symbol

I

Min

I

Typ

I

Max

I

Unit

REFERENCE AMPUFIER
Input Offset (Ref + to Ref-)

VOS

Bias Current Into Ref-

IBR

Bandwidth (CC = 250 pF, Vref - = 10 mVp·p)

BW

-15

-

±5.0

+15

1.4

5.0

mV

j1A

3.0

-

MHz

-

0.8

Vdc

VCC

Vdc

DIGITAL INPUTS
Low Voltage

VIL

0

High Voltage

VIH

2.0

Low Current (Data, Controls @ 0.4 V)

ill

High Current (Data, Controls @ 2.4 V)

10

25

j1A

IIH

-

65

110

j1A

Low Current (Conv, Conv @ 0.4 V)

IlL

-200

-144

-

j1A

High Current (Conv, Conv @ 2.4 V)

IIH

100

140

j1A

Input Capacitance

Cin

3.0

-

pF

..

..

-

NOTES: 1. Current Into a pin IS deSignated as pOSItiVe, current out of a pin as negative •
2. Controls = FH, BRT, BlK, Sync, and FT.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
6-65

MC10322
ELECTRICAL CHARACTERISTICS (TA = 25'C, Iref = 1.115 mA, load =37.5010 AGnd, VCC = + 5.0 V, VEE =-5.2V, see Figure 1.)

I

I

Characteristic

Symbol

I

Min

I

'iYP

I

Max

I

Unit

TRANSFER CHARACTERISTICS
Resolution

Res

8.0

8.0

8.0

BHs

Integral Nonlinearity

INl

-1/2

0

+1/2

lSB

Differen1ial Nonlinearity

DNl

-1/2

0

+1/2

lSB

Monotonicity

-

Differential Gain

DG

-

1.0

-

%

Differen1ial Phase

DP

-

0.5

-

Deg

Output Current at Out - (Control Inputs = 0 Except as Noted)
Enhanced White (FH = BRT = 1)
Normal White (FH = 1 or DO - 07 = 1)
Normal Black (DO - 07 = 0) Referred to Normal White
Blank Referred to Normal Black (BlK = 1)
Sync Referred to Blank (SYNC = 1)

IEHINWINBIBlNISYNC-

0
1.75
16.6
1.32
7.1

18
1.94
17.7
1.43
7.7

100
2.13
18.7
1.54
8.3

Output Voltage at Out - (Control Inputs = 0 Except as Noted)
Enhanced White (FH.= BRT = 1)
Normal White (FH = 1 or DO - 07 = 1)
Normal Black (DO - 07 = 0) Referred to Normal White
Blank Referred to Normal Black (BlK = 1)
Sync Referred to Blank (SYNC = 1)

VEHVNWVNBVBlNVSYNC-

0
-67.8
-626
-SO.6
-270

-0.67
-73
-663
-53.6
-288

-3.75
-77.6
-694
-56.6
-308

Output Current at Out + (Control Inputs = 0 Except as Noted)
Enhanced White (FH = BRT = 1)
Normal White (FH = 1 or DO - 07 = 1)
Normal Black (DO - 07 = 0) Referred to Normal White
Blank Referred to Normal Black (BlK = 1)
Sync Referred to Blank (SYNC = 1)

IEH+
INW+
INB+
IBlN+
ISYNC+

26.8
25
-16.6
-1.32
-7.1

28.8
26.8
-17.7
-1.43
-7.7

30.6
28.5
-18.7
-1.54
-8.3

Output Voltage at Out + (Control Inputs = 0 Except as Noted)
Enhanced White (FH = BRT = 1)
Normal White (FH = 1 or DO - 07 = 1)
Normal Black (DO - 07 = 0) Referred to Normal White
Blank Referred to Normal Black (BlK = 1)
Sync Referred to Blank (SYNC = 1)

VEH+
VNW+
VNB+
VBlN+
VSYNC+

-1016
-949
626
50.6
270

-1080
-1005
663
53.6
288

-1132
-1057
694
56.6
308

IFSER

-50

0

+50

GER

-50

0

+5.0

%

Output Impedance (Gray Scale, -1.7 V < Vo < 0.3 V)

Zo

25

100

-

kO

Output CapaCitance

Co

16

-

Guaranteed'

OUTPUTS

I1A
mA

mV

mA

mV

Output Matching ( IINB + I -IINB -I )
Gain Error (Gray Scale at Out -)

-

Glitch Energy (Clocked Mode)
At Midscale Transition (DO - 07 = ,27...,28)
Due to Clock Feedthrough (DO - 07 = Constant)
Due to Data Feedthrough (Clock = Constant)

EGM
EGC
EGO

Peak Glitch Current (Clocked Mode)
At Midscale Transition (DO - 07 = ,27...,28)
Due to Clock Feedthrough (DO - 07 = Constant)
Due to Data Feedthrough (Clock = Constant)

IGM
IGC
IGD

-

Supply Current
(VCC = + 5.5 V)
(VEE =-5.72 V,lref= 1.115 mAl

ICC
lEE

-55

22
-45

-

Power Dissipation

Po

-

344

469

-

18
2.0
25

-

0.2
55
0.5

-

I1A

pF
pV-sec

-

mA

-

rnA

I1A

POWER SUPPUES

Power Supply Sensitivity at Outputs
(VEE =-5.2 V, 4.5< VCC < 5.5 V)
(VCC = + 5.0 V,-5.72", To Next
~------, Stage

40k

DGnd - .....- - - - - - - - - - - - '

OAC - Video Controls
The four video controls (Sync, BLK, FH, and BRT) are
logic level inputs, TTL compatible, which permit selting the
outputs to standard video levels. All four are active high.
The Truth Table on page 7 indicates their priority.
The Force High input (FH) overrides the data inputs
(DO - D7), selting the DAC inputs to all ls (FFH). In most
applications, this is equivalent to the normal wMe level. FH
can be used with the BRT input to create an enhanced
white, but is overridden by Sync or BLK.
The Bright input (BRT) shifts the Gray Scale by =11% in
the high (white) direction. Typically this function is used to
provide an enhanced, or brighter display so as to highlight
certain portions of the screen. A highlighted cursor is a
typical example.

Vee

--<_. . .

---------1>-----,

1.7V
~--+-------" To Next

10k

+--------1 Stage

Conv~~+---+_~-L_

COrW-~~--~--------~------~

DGnd

--<-.. . . ------------'

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

6-70

MC10322
Convert Inputs
The Convert inputs (Pins 6 and 7) are used to clock in
data and the video controls to the internal registers only if
FT (Pin 8) is low. The input stage for these pins is shown
in Figure 5. The pins are internally biased at = +1.6 V
with a nominal input impedance of 10 kO. The inputs may
be driven from complementary TIL clock signals with the
clocking action occurring on the rising edge of Conv and
the falling edge of Conv as the signals cross each other
in Voltage.
A single-ended clock source may be used by connecting
either Pin 6 or 7 to a fixed voltage to set the threshold and
applying the clock signal to the other pin. If done this way,
the fixed voltage must be within the range of + 1.3 V to VCC

_ 2.0 V. Figure 6 shows three positive edge triggered
examples. Interchanging Pins 6 and 7 provides negative
edge triggered operation.
The input current required at each pin is shown in Figure 9,
and is independent of the clocking mode used.
If FT is high, the Convert pins are nonfunctional, and must
be connected to different voltages (e.g., VCC and DGnd).
Leaving the pins open can result in high frequency
oscillations or spurious noise.
Conv and Conv must be kept within the range of VCC and
DGnd. If taken more than 0.5 V above VCC or below Gnd
excessive currents will flow, and the DAC output waveform
will be distorted.

Figure 6. Single-Ended Clock Input

!l
.3k

tl
VCC

VCC

,-------

71 Conv

I
I
I
MC10322
I
I
I
Clock~Conv
L ______ _

3.3k

i ------I
Conv

I
I
I
I

MC10322

Clock~conv
L ______ _

Reference Amplifier
The reference amplifier (Pins 14 to 16) is used to accept
the externally supplied reference current for the DAC current
switches (see Figure 7).
Ref + (Pin 15) is a low impedance (virtual ground) input
into which the reference current flows (current cannot flow
out of this pin). Due to the op amp's internal feedback, the
voltage at Ref + is the same as that set at Ref -, with a typical
input offset of ± 5.0 mV. The current into Ref + should be
within the range of 0.5 rnA to 1.7 rnA to maintain 8-bit linearity
and accuracy. A reference current of 1.115 rnA is
recommended to obtain EIA-170 and EIA-343-A voltage
levels at the outputs if they are terminated with 37.5 0
(double 75 0 terminations).
Ref - is a high impedance input (>10 MO) which must be
set to a voltage within the range of - 0.8 to -1.7 V. A
nominal bias current of =1.4 ~A will flow into this pin. In
Figure 7, Iref = Vref/Rref·

,------71-

0.01r iI

conv

Figure 7. Reference Amplifier

Ra " Rrel
0.01
0.5 < Irel < 1.7 rnA
-1.7V < Vrel < -O.B V

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
6-71

MC10322

I
I
I
Clock~LConv
______ _

MC10322
Power Supplies
The MC10322 requires both a + 5.0 V and a - 5.2 V
supply, both ± 10%. Nominal current requirements are 22 mA
and 45 mA, respectively, (including a total output current of
29 mAl. The supply current required at VEE is dependent on
the IOtal output current (Pin 18 + Pin19). The + 5.0 V supply
powers only the digital portion of the IC (control logic and
latches), and should be referenced to Digital Ground (Pin 5).
The - 5.2 V supply powers the analog portion of the IC
(reference amplifier and the DAC's current sources), and
should be referenced to Analog Ground (Pin 17). See the
Applications Section for add~ional information on power
supplies, bypassing and PC board layout.

(andlor Convert) inputs. I! the clock signal is single-ended,
the data and control latching occurs on the rising edge of
Convert, or the falling edge of Convert. I! a differential clock is
used, latching occurs at the cross-over point of the two
signals. The hold time for the data and controls is 0, but the
setup times must be observed. The clock duty cycle is not
important as long as the minimum pulse widths are observed.
Figure 3 is for the transparent (non-clocked) mode. The
output responds to the application of new data or control
inputs without the need for a clocking edge. The propagation
delay to the output is different for each of the data and control
signals. To prevent large glitches at the outputs. it is
imperative that the data bits (DO - 07) arrive at the MC10322
simultaneously with minimum skew. I! the synchronism of the
8-bits cannot be guaranteed. either an 8-bitlatch should be
used (F373 or F374 type). or the MC10322 should be used in
the clocked mode.

Timing
Figures 2 and 3 are the timing diagrams for the MC1 0322.
Figure 2 is for the clocked mode where data and control
inputs are latched into the input registers by the Convert

Figure 8. Input Current, Data and Controls
160

soo

/

./

Vcc=+S.OV

./

~300

10'

I'
-1.0

/

~

/"

.:..5

2.0

3.0

4.0

./

S.o

-300
-1.0

6.0

/

100

~
-- -100

V
1.0

t..-,I

/"

VCC=+S.OV

ffi

,/

",

Figure 9. Input Current, Convert Inputs

/'"

,

)~

V

Yin, INPUT VOLTAGE M

2.0

1.0

3.0

4.0

S.o

6.0

Vln.INPUT VOLTAGE M

APPLICATIONS INFORMATION
Power Supplies, Grounding
The PC board layout and the quality of the power supplies
and the ground system at the IC are very important in order
to obtain proper operation. Noise from any source coming
into the device on VCC. VEE. or ground can cause an
incorrect output code due to interaction with the analog
portion of the circuit. At the same time. noise generated
within the MC10322 can cause incorrect operation If that
noise does not have a clear path to AC ground.
Both the VCC and VEE power supplies must be decoupled
to the appropriate ground at the IC (within 1" max) with a 10
j1F tantalum and a 0.1 j1F ceramic. Tantalum capacitors are
recommended since electrolytic capaCitors simply have too
much inductance at the frequencies of interest. The quality of
the VCC and VEE supplies should then be checked at the IC
with a high frequency scope. Noise spikes (whenever digital

circuits are present) can easily exceed 400 mV peak. and if
they get into the analog portion of the IC. the operation can
be disrupted. Noise can be reduced by inserting resistors
and/or inductors between the supplies and the IC.
I! switching power supplies are used. there will usually
be spikes of 0.5 V or greater at frequencies of 50 kHz to
1.0 MHz. These spikes are generally more difficult to
reduce because of their greater energy content. In extreme
cases
three
terminal
regulators
(MC78L05ACP.
MC7905.2CT). w~h appropriate high frequency filtering
should be used and dedicated 10 the MC10322.
The ripple content of the supplies should not allow their
magnitude to exceed the values in the Recommended
Operating Conditions.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

6-72

MC10322
line theory. Otherwise reflections back to the signal sources
can occur, disrupting their operation. Additionally, the
overshoots and undershoots which will occur at the
MC10322's input pins can cause its operation to be
disrupted, resulting in a noisy or incorrect output.
Additional information regarding the transmission
characteristics of PC board tracks can be found in Motorola's
MECL System Design Handbook (HB205).

The PC board tracks supplying VCC and VEE to the
MC10322 should preferably not be at the tail end of the
bus distribution after passing through a maze of digital
circuitry. The MC10322 should be close to the power
supply, or the connector where the supply voltages enter
the board. If the VCC and VEE lines are supplying
considerable current to other parts of the board, then it is
preferable to have dedicated lines from the supply or
connector directly to the MC10322.
The two ground pins (DGnd and AGnd) must eventually be
connected together, usually near the power supply, although
the specific board layout may dictate a different "best point",
VCC must be referenced to DGnd, and VEE must be
referenced to AGnd.

Reference Circuits
Since the accuracy of the outputs are directly related to the
accuracy and quality of the reference current and voltage, it
is imperative that accurate and stable references be used at
Pins 14 and 15. The voltage supply used for the digital
circuitry should preferably not be used as a source for either
the reference current or voltage due to the noise spikes and
ripple present on the supply and its ground lines.
Figure 10 indicates a method for generating the reference
signals from a positive supply. The MC1403 reference is a
stable 2.5 V bandgap regulator (± 1%), with a maximum
temperature coefficient of 40 ppm/"C, and good ripple and
high frequency noise rejection. In the figure, the circuit
supplies -1.48 V to Pin 14, and a current of 1.113 mA to Pin
15. If the outputs olthe MC10322 are terminated with 37.5 0,
the voltage levels will be well within the allowable range
specified by EIA-170 and EIA-343-A.

PC Board Layout
Due to the high frequencies involved, and in particular, the
fast edges of the various digital signals, proper PC board
layout is imperative. A solid ground plane is strongly
recommended in order to have known transmission
characteristics, and also to minimize coupling of the digital
signals into the analog section. Use of wire wrapped boards
should definitely be avoided.
Each PC track should be considered a transmission line,
and if they are of any considerable length (more than a few
inches), they should be terminated according to transmission

Figure 10. Reference Supply

r---------,

1

1

MCI0322

1

4.5Vlo 40V
Inpul

MC1.403

1

Iref
1
~~----~------'~
______~15TI~

ro.

1
I
1
1

3570
1

141

2.0k

1.1Bk

3570

1

1

1

1

1
IAGnd

L_____ ___ n
1

...I

1

20

_

-

VEE

Figure 11. Reference Supply
If the analog - 5.2 V supply is fairly clean and free of
digital noise the circuit of Figure 11 may be used. The
TL431 is a stable 2.5 V bandgap reference (± 1%) with an
effective temperature coefficient of 50 ppm/"C. The 5 k pot
allows adjustment for precise output levels, or it may be
replaced with a precision resistor which provides the correct
voltage at Pin 14.

Iref
I.Ok

r---------,

-

1
1
1

MCI0322

I

0.1
TL431

5.0k ~--~"+----I

1
1

2.4k

1

I.Ok

'- _ _ _ _ _ _ _

20

VEE

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

6-73

.J~

MC10322
Figure 15. Applying a Modulating Current

Figure 12 indicates another reference circuit using the
LM385-1.2 reference diode. Rref is chosen to provide the
desired reference current to Pin 15 knowing that it is set at
-1 .235 V. The LM385 is a bandgap type reference with a
± 2% initial accuracy. The 20 k resistor biases the diode at
approximately 200 IlA for minimum temperature variations.
The 0.2 IlF capacitor, with the 20 k resistor, filters out noise
above ~ 40 Hz.
Figure 12. Reference Supply

r--------,

Rref

Iref

I

Mel 0322

r--+----'\Mr-------.,.=-'o

LM385-1.2

20k

IL. _ _ _ _ _ _
20

I
I
I
I
I
I
I

Ra = Rre!
(-I.7V < Vret < - 0.8V]

~
_.J 17 ...L

In all three examples the DC reference current is Vref/Rref.
In Figure 13 the AC signal source is referenced to a negative
voltage source (Vref). In Figures 13 and 14 the AC reference
current is equal to VAC divided by Rref. In Figure 15 the AC
reference current is equal to VAC divided by Rb. The AC
signal at Out - and Out + is determined by the following
equations:

Digitally Modulating an Analog Signal
The MC10322 may be used to digitally modulate (or
attenuate) an analog signal by applying the analog signal to
the reference amplifier. Three methods of doing this are
shown in Figures 13 to 15.

VO-(AC)

Iref(AC) x (255-A) x RL
16
Iref(AC) x A x RL

VO+(AC)-

16

Figure 13. Applying an Analog Signal Directly
where "A" is the value of the digital word at DO - 07 (0 to 255).
When implementing any of the above schemes, or any
other method of feeding an AC signal to the reference
amplifier, the following operating limits must be observed:
1) The peak values of the reference current
(AC + DC) must be within the range of 0.5 mA
to 1.7 mA into Pin 15;
2) The peak values of the voltage at Ref + and Refmust be within the range of - 0.8 V to -1.7 V;
3) The peak values of the voltage at Out - and Out +
must be within the range of -1.7 V to + 0.3 v.
The maximum frequency which can be handled by the
reference amplifier is dependent on the compensation
capacitor (CC) at Pin 16, and the signal amplitude according
to the following equation:

Ra = Rre!
(-1.7V < Vref < - 0.8V]

Figure 14. CapaCitor Coupling the AC Voltage

1.59x 10- 8
fmax=

Cc x Ipk

where Ipk is the peak value of the AC reference current (112 of
the peak-to-peak value). The small signal bandwidth of the
reference amplifier is ~ 3.0 MHz.
Components associated with the reference amplifier (Pins
14 - 16) should be physically close to the pins. The board
layout should be neat, preventing unwanted stray capacitive
coupling between the outputs and the reference amplifier. If
Cc is smaller than 5000 pF a ground plane is strongly
recommended. Cc should not be smaller than 250 pF.

Ra = Rref
(-1.7V < Vret < - 0.8V]

MOTOROLA LlNEAR/(NTERFACE ICs DEVICE DATA
6-74

MC10322
Negative Voltage Regulator
In the case where a negative power supply is not
available, neither the - 5.2 V, nor a higher negative voltage
from which to derive it, the circuit of Figure 16 can be used to
generate - 5.2 V from the + 5.0 V supply. The PC board
space required is small (= 2.0 in2), and it can be located
Vin >----.....-...,
(04.5 \0 0 5.5V)

physically close to the MC10322. The MC34063A is a
switching regulator, and in Figure 16 is configured in an
inverting mode of operation. The regulator operating
specifications are given in Figure 16.

Figure 16. - 5.2 V Regulator
0.470

6 7

- 5.2V/l00mA
1 r~o--,--o Vout

Line Regulation

4.5 V < Vin < 5.5 V,
lout = 50 rnA

0.04%

Load Regulation

Yin = 5.0 V,
15 rnA < IOUI<85 rnA

1.5%

Output Ripple

Vin = 5.0 V, loul =85 rnA

Short Circuit lout

Vln =5.0 V, RL = 1.0 0

Efficiency

Yin = 5.0 V, loul =50 rnA

4.0 rnVp-p
620 rnA
48%

TYPICAL APPLICATION CIRCUITS
Figure 17 shows a typical video application circuit using
the MC10322 in the clocked mode. The clock is
Single-ended, and the circuit updates the output on the rising
edge of the clock. The Out - pin feeds a standard 75 Q

monitor through a 75 Q cable, which is terminated at both
ends. The reference voltage is supplied by an LM385-1.2
regulator.

Figure 17. Clocked Mode

" Vcc

Clock /

,

6 ConY
7 COnY

18

3.3k ,

.)
175

~
5

o 5.011, ± 10%

Out-

FT

Out 0

OGnd

Ref 0

101lF+ O.lt 9

19 15

37.5

75DC8bIe

}o

L

*
J-

Uk I ..

Video
Monitor

Vee

Digital Supply

~-I
Digital
Inputs

4
3
2
1
24
23

DO
01
02
D3
D4
05

2206
21 07

Video
Controls

t

10
FH
12
BRT
11 BLI<
13 Sync

MC10322

Ref-

14

0 2 r " LM385-1.2

20k
Comp
VEE

16

17
AGnd

°i~1
11

20

±f
1000F _

-5.2Y,±10%
Analog Supply
0.1

J.

NOTES: 1. Gray Scale Inputs, video controls, and clock are \0 be referenced to digital ground.
2. Outputs and reference circuitry are to be referenced to analog ground.
3. PC board layout to be such that digital noise does not get Into the analog side clrcuRry.
4. Analog and digital grounds to be connected together. location of this connedlon Is board
layout dependent,and is to be such that digital ground noise does not show up In the analog signals.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
6-75

000

MC10322
Figure 18 shows a circuit similar to that of Figure 17,
except the MC10322 is used in the transparent mode. The
source of the data bits must provide the 8-bits
simultaneously, with minimum skew, to keep output glitches

to a minimum. If latches, or other antiskew circuitry, are not
available within the microprocessor circuitry, a set of 8-bit
latches between it and the MCl 0322 is recommended, or the
MC10322 should be used in the clocked mode.

Figure 18. Transparent Mode

L....1

Vcc

18

Cony

Oul-

8 FT

7~conv

n7]

,4,

i

Oul + 19 -

75£1 Cable
7S

7S

r

Ls

Video
Monilor

Ref + I-'I",S_~1.VllkIV1_%_.....

OGnd

_0._~T+--,9, VCC

,----4'-100
(
3 01
----'2,02
----1'-103
24 04
23 05
22 06
(
2t 07

000

37.5

+ 5.0\1, ± 10% ,>-_10_f1_F.......
Oigital Supply

I l
I a
It
I ~
I e

LJ O

0.2
MC10322

Ref- 14

ft--

LM38S -1.2

20k
Comp ,...1_6_ _~"itl_l_ _",
VEE ..,2",0~_ _~_......_-< -S.2V,±10%

f1P
Syslem

17

0 FH
-;1--_ _ _ _ _-'1"-1
2 BRT
o t-_ _ _ _ _-'1=-t
1 BlK
1--_ _ _ _ _-'1-'-1

AGnd

++
IOflF

Analog Supply

0.1

J,

13 Sync

NOTES: 1. Gray Scale inputs and video controls are to be referenced to digital ground.
2. Outputs and reference circuitry are to be referenced to analog ground.
3. PC board layout to be such that digital noise does not get into the analog side circuitry.
4. Analog and digital grounds to be connected together. Location of this connection is board
layout dependent, and is to be such that digital ground noise does not show up in the analog signals.

GLOSSARY
Bandgap Reference - A voltage reference circuit based on
the predictable base-emitter voltage of a transistor. The
silicon bandgap voltage of ~1.2 V is the basis for generating
other voltages which are stable with time and temperature.
Bipolar Input - A mode of operation whereby the analog
input (of an A-D), or output (of a DAC), includes both negative
and positive values. Examples are: - 5.0 V to + 5.0 V, - 2.0
V to + 8.0 V, etc.
DAC Current Gain - The internal gain the DAC applies to
the reference current to determine the full scale output
current. The actual maximum current out of a DAC is one
LSB less than the full scale current.

Differential Nonlinearity - The maximum deviation in the
actual step size (one transition level to another) from the ideal
step size. The ideal step size is defined as the Full Scale
Range divided by 2n. This error must be within ± 1 LSB for
proper operation.
Differential Phase - In video systems, differential phase is
the change in the phase modulation of the chrominance as
a function of the luminance level. The hue in a color picture
will be distorted if the differential phase is not zero.
Full Scale Range - The difference between the minimum
and maximum end points of the analog input (of an ND),
or output (of a DAC), plus one LSB.

Differential Gain - In video systems, differential gain is a
component's change in gain as a function of luminance level.
In a color picture, contrast will be affected if the differential
gain is not zero.

Gain Error - The difference between the actual and
expected gain (end point to end point), with respect to the
reference, of a data converter. The gain error is usually
expressed in LSBs, or percent.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
6-76

MC10322
Output Compliance - The maximum voltage range to which
the DAC outputs can be subjected, and still meet all
specifications.

Glitch Area - The energy content of a glitch, specifically
In volt-seconds. It is the area under the curve of the glitch
waveform. For a symmetrical glitch, the area and the energy
can be zero.

Power Supply Rejection Ratio - The ability of a device
to reject noise andlor ripple on the power supply pins from
appearing at the outputs. An AC measurement, this
parameter is usually expressed in dB rejection.

Gray Code - Also known as reflected binary code, it is a
digital code such that each code differs from adjacent codes
by only one bit. Since more than one bit is never changed
at each transition, race condition errors are eliminated.
Integral Nonlinearity - The maximum error of an ND or
DAC, transfer function from the ideal straight line connecting
the analog end points. This parameter is sensitive to
dynamics, and test conditions must be specified in order to
be meaningful. This parameter is the best overall indicator
of the device's performance.
LSB - Least Significant Bit. It is the lowest order bit of a
binary code.

Power Supply Sensitivity - The change in a data
converter's performance with changes in the power supply
voltage(s). This parameter is usually expressed in percent
of full scale versus t.v.
'Propagation Delay - For a DAC, the time from when the
clock input crosses its threshold to when the DAC output(s)
changes.

Line Regulation - The ability of a voltage regulator to
maintain a certain output voltage as the input to the regulator
is varied. The error is typically expressed as a percent of
the nominal output voltage.

Quantltlzatlon Error - Also known as digitization error or
uncertainty. It is the inherent error involved in digitizing an
analog signal due to the finite number of steps at the digital
output versus the infinite number of values at the analog
input. This error is a minimum of ± 1/2 LSB.

Load Regulation - The ability of a voltage regulator to
maintain a certain output voltage as the load current is varied.
The error is typically expressed as a percent of the nominal
output voltage.

Resolution - The smallest change which can be discerned
by an ND converter, or produced by a DAC. It is usually
expressed as the number of bits (n), where the converter
has 2n possible states.

Monotonlclty - The characteristic of the transfer function
whereby increasing the input code (of a DAC), or the input
Signal (of and ND), results in the output never decreasing.
Nonmonotonicity occurs if the differential nonlinearity
exceeds ± 1 LSB.

Sampling Theorem - Also known as the Nyquist Theorem.
It states that the sampling frequency of an ND must be no
less than 2x the highest frequency (of interest) of the analog
signal to be digitized in order to preserve the information of
that analog signal.

MSB - Most Significant Bit. It is the highest order bit of a
binary code.

Settling Time - For a DAC, the time required for the output
to change (and settle in) from an initial ±1/2 LSB error band
to the final ± 112 LSB error band.

Natural Binary Code - A binary code defined by:
N = An2n + ... + Aa23 + A222 + A121 + A020
where each "A" coefficient has a value of 1 or O. Typically,
all zeros correspond to a zero input voltage of an ND, and
all ones correspond to the most positive Input voltage.

TTL - Transistor-transistor logic,
Two's Complement Code - A binary code applicable to
bipolar operation, in which the positive and negative codes
of the same analog magnitude sum to all zeros, plus a carry.
It is the same as offset binary code, with the MSB inverted.

Nyquist Theory - See Sampling Theorem.
Offset Binary Code - Applicable only to bipolar input (or
output) data converters, it is the same as Natural Binary
code, except that all zeros correspond to the most negative
output signal (of a D/A), while all ones correspond to the
most positive output.
.

Unipolar Input - A mode of operation whereby the analog
input range (of an ND), or output range (of a D/A), includes
values of a single polarity. Examples are:
o to +10 V, 0 to -5.0 V, +2.0 V to + 8.0 V, etc.

Acldltlonallnfonnatlon regarding the trensmlsslon characteristics 01 PC board treeks can be found In
Motorola's MECL System Daslgn Handbook (HB205).

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

6-77

MOTOROLA

SEMICONDUCTOR _ _ _ __

MC10324

TECHNICAL DATA

Advance Information
a-Bit Video DAC with ECllnputs
a-BIT VIDEO DAC
with ECl INPUTS

The MCt 0324 is a 40 MegaSample Per Second (MSPS) 8-bit
Video DAC capable of directly driving a 75 Q cable, with appropriate
terminations, to EIA-t70 and EIA-343-A video levels. The logic inputs
(data and controls) are ECl compatible. Input registers negate the need
for external latches unless the transparent mode is selected.
Video controls (Force High, Blank, Bright, and Sync) permit an easy
interface to standard video systems. The Clock (Convert) inputs can be
differential or single-ended. Complementary outputs are provided for
custom displays or special effects.
The MCt 0324 is fabricated with Motorola's MOSAICTM process
which provides high speed with low power consumption. The MCt 0324
is available in a 24 pin plastic DIP package.

SILICON MONOLITHIC
INTEGRATED CIRCUIT

• 40 MSPS Minimum Conversion Rate
• ECl Compatible Inputs
• 8-Bit Linearity
• latched Data and Video Control Inputs, or Transparent Mode
• Video Controls: Force High, Blank, Bright, Sync
P SUFFIX
PLASTIC PACKAGE
CASE 649

• Each Differential Current Outputs Can Swing 2.0 V
• Modulation Capability (Multiplying Mode)
• PSRR > 60 dB
• Standard Power Supply: - 5.2 V
• Power Dissipation: Typically 338 mW
• Pin Compatible with TRW's TDCt Ot8
• Available with TTL Inputs (MCt 0322)

PIN CONNECTIONS

Simplified Block Diagram

D4
D5

,------------------1
I

DO-D7

FH

BLK

Reft
RefComp

, - - - - -_____.-L_ Out-

VEEIA)

'-,-,-----rv lOut t

Outt

-r- DGnd

BRT
Sync
Cony
Cony
FT

D6

Dl

--i-.:::..':::===--J
---'~-------'
---!~--------'

-J-

VEEID)

...L

AGnd

+
I
I
I
I
I

L ________________ -.!~I~

OutAGnd

VEEIA)

Comp
FH

Reft

BRT

Sync

Ref-

(Top View)

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

6-78

MC10324
PIN FUNCTION DESCRIPTION
Symbol

Pin

Description

DO-D7

1-4,
21-24

Data inputs. DO is the lSB and D7 is the MSB. Inputs are ECl compatible. Maximum update
rate is typically 60 MHz. The eight bits control the Gray Scale amplitude only, and do not
involve the Sync or Blank levels.

VEE(D)

5

Connect to - 5.2 V, ± 10%. This supply should be referenced to digital ground.

Conv

6

Convert input. The rising edge latches data and controls if FT = O. May be used single-ended
(with Pin 7 at a fixed voltage), or differentially with Pin 7.

Conv

7

Convert input. The falling edge latches data and controls if FT = O. May be used
single-ended (with Pin 6 at a fixed voltage), or differentially with Pin 6.

FT

8

Feedthrough. When high, the internal latches are transparent, and Pins 6 and 7 are unused.
When low, data and controls are latched by Pins 6 and 7.

DGnd

9

Connect to system digital ground. This pin must be within 100 mV of AGnd (Pin 17).

FH

10

Force High. A logic high internally sets data inputs = 1, overriding external data inputs.

Blank

11

A logic high overrides data inputs, sets the outputs to the video blanking level.

BRT

12

Bright. A logic high increases the Gray Scale output level by = 11%, providing an enhanced
display. Does not affect Sync or Blank.

Sync

13

A logic high overrides all other inputs, and sets the output to video sync level.

Ref-

14

Inverting Reference input. A high impedance input, normally set to a negative DC voltage in
the range of-0.8 to-1.7 V. Can be used to modulate the output.

Ref +

15

Noninverting reference input. A virtual ground, current supplied to this pin sets the maximum
output current.

Comp

16

Compensation. A capaCitor between this pin and Pin 20 stabilizes the reference amp.

AGnd

17

Connect to system analog ground. This pin must be within 100 mV of DGnd (Pin 9).

Out-

18

A high impedance current output. Video voltage levels are produced when connected to a
75 n cable with appropriate terminations. This output provides a "sync down" waveform. If
unulied, connect to Pin 17.

Out +

19

Complementary output provides a "sync up" waveform. If unused, connect to Pin 17.

VEE(A)

20

Connect to - 5.2 V, ± 10%. This supply should be referenced to analog ground.

Figure 1. Test Circuit

DuI-

DO

I
I
I

37.50

FT
FH
BRT
BU<
Sync

VOul-

VOuit

Quit

D7

-1.95V
or
-O.B1V

37.m

RefMC10324

Vref
_1.115mA

Reft
1.0k

Comp
0.01

DGnd
VEE(D)

nIL
40MHz

0.1
AGnd

Cony
NC

-5.2V

VEE(A)

Conv

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
6-79

MC10324
MAXIMUM RATINGS
Characteristics

Value

Unit

VEE(D) (with respect to DGnd)

-7.0, + 0.5

Vdc

DGnd (with respect to AGnd)

-1.0, + 0.5

Vdc

VEE(A) (with respect to AGnd)

-7.0, + 0.5

Vdc

Logic Input Voltage (with respect to DGnd)

+ 0.5

Vdc

Logic Input Voltage (with respect to VEE(D))

-0.5

Vdc

+ 0.5, VEE(A)

Vdc

Voltage at Reference Amp Inputs
Current Into Ref +
Voltage Applied to Out +, Out - (Normal Operation)
Voltage Applied to Out +, Out - (VEE(D), VEE (A)

= 0)

Junction Temperature

+ 6.0, 0

mA

+ 0.5, -2.0

Vdc

+ 0.5, -1.2

Vdc

-65 to +150

°C

Devices should not be operated at these values. The "Recommended Operating Conditions' table provides
conditions for actual device operation.

RECOMMENDED OPERATING CONDITIONS
Characteristic

Symbol

Min

Typ

Max

Unit

VEE(D) - DGnd
DGnd-AGnd
VEE (A) - AGnd

-5.72
-0.1
-5.72

-5.2
0
-5.2

-4.68
+ 0.1
-4.68

Vdc

Logic Input Voltage

Vin

VEE(D)

-

DGnd

Vdc

Reference Current (for Video Standard Output)
(for all other applications)

Iref

-

-

mA

Supply Voltage

1.115

Vref-

-1.7

-

Output Load Impedance

RL

0

37.5

Output Compliance (with respect to AGnd)

Va

-1.7

fs

0
0

VCM
TA

0.5

Voltage at Ref-

Convert Frequency (FT = 0)
Data Update Frequency (FT

= 1)

Convert, Convert Common Mode Range
Operating Ambient Temperature

1.7
-0.8

Vdc

-

-

11

+0.3

Vdc

60
60

40
40

MHz

VEE(D)+1.3

-

DGnd
-0.3

Vdc

-40

-

+85

°C

Allllmrts are not necessarily functional concurrently.

ELECTRICAL CHARACTERISTICS (TA

I

= 25°C, Iref = 1.115 mA. Load = 37.5 11 to AGnd, VCC = VEE = -5.2 V, see Figure 1.)

Characteristic

I

Symbol

I

Min

I

Typ

I

Max

I

Unit

REFERENCE AMPLIFfER
Input Offset (Ref + to Ref-)

Vas

-15

±5.0

+15

Bias Current Into Ref-

IBR

-

1.4

5.0

j.tA

BW

-

3.0

-

MHz

Bandwidth (CC

= 250 pF, Vref - = 10 mVp-p)

mV

DIGITAL INPUTS
Low Voltage

VIL

-1.95

High Voltage

VIH

-1.13

Low Current (Data, Controls @ -1 .95 V)

IlL

High Current (Data, Controls @-0.81)

IIH

-

Low Current (Conv, Can v @ -1.95)

IlL

High Current (Conv, Conv@-0.81)

IIH

Input Capacitance

Cin

-1.6

Vdc

-0.81

Vdc

90

150

IlA

120

200

IlA

-150

-60

-

j.tA

-

80

150

j.tA

5.0

-

pF

NOTES: 1. Current mto a pin IS deSignated as positive, current out of a pin as negative.
2. Controls = FH, BRT, BLK, Sync, and FT.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

6-80

-

MC10324
ELECTRICAL CHARACTERISTICS (TA = 25'C, Iref = 1.115 mA, load = 37.5!lto AGnd, VCC = VEE =-5.2 V, see Figure 1.)

I

Characteristic

I

Symbol

I

Min

I

I

Typ

Max

I

Unit

TRANSFER CHARACTERISTICS
Resolution

Res

8.0

8.0

8.0

Bits

Integral Nonlinearity

INl

-1/2

0

+1/2

lSB

Differential Nonlinearity

DNl

-1/2

0

+1/2

lSB

Monotonicity

-

Differential Gain

DG

Differential Phase

DP

Guaranteed·

-

1.0

-

%

0.5

-

Deg

*Guaranteed by linearity tests.

OUTPUTS
Output Current at Out - (Control Inputs = 0 Except as Noted)
Enhanced White (FH = BRT = 1)
Normal White (FH = 1 or DO - D7 = 1)
Normal Black (DO - D7 = 0) Referred to Normal White
Blank Referred to Normal Black (BlK = 1)
Sync Relerred to Blank (SYNC = 1)

IEHINWINBIBlNISYNC-

0
1.75
16.6
1.32
7.1

18
1.94
17.7
1.43
7.7

100
2.13
18.7
1.54
8.3

Output Voltage at Out - (Control Inputs = 0 Except as Noted)
Enhanced White (FH = BRT = 1)
Normal White (FH = 1 or DO - D7 = 1)
Normal Black (DO - D7 = 0) Referred to Normal White
Blank Relerred to Normal Black (BlK = 1)
Sync Referred to Blank (SYNC = 1)

VEHVNWVNBVBlNVSYNC-

0
-67.8
-626
-50.6
-270

-0.67
-73
-663
-53.6
-288

-3.75
-77.6
-694
-56.6
-308

Output Current at Out + (Control Inputs = 0 Except as Noted)
Enhanced White (FH = BRT = 1)
Normal White (FH = 1 or DO - D7 = 1)
Normal Black (DO - D7 = 0) Referred to Normal White
Blank Referred to Normal Black (BlK = 1)
Sync Referred to Blank (SYNC = 1)

IEH+
INW+
INB+
IBlN+
ISYNC+

26.8
25
-16.6
-1.32
-7.1

28.8
26.8
-17.7
-1.43
-7.7

30.6
28.5
-18.7
-1.54
-8.3

Output Voltage at Out + (Control Inputs = 0 Except as Noted)
Enhanced White (FH = BRT = 1)
Normal White (FH = 1 or DO - D7 = 1)
Normal Black (DO - 07 = 0) Referred to Normal White
Blank Referred to Normal Black (BlK = 1)
Sync Referred to Blank (SYNC = t)

VEH+
VNW+
VNB+
VBlN+
VSYNC+

-1016
-949
626
50.6
270

-1080
-1005
663
53.6
288

-1132
-1057
694
56.6
308

IFSER

-50

0

+50

GER

-50

0

+5.0

Output Impedance (Gray Scale, -1.7 V < Vo < 0.3 V)

Zo

25

100

-

Output CapaCitance

Co

-

16

-

IIA
mA

mV

mA

mV

Output Matching ( IINB + I -IINB -I )
Gain Error (Gray Scale at Out-)

Glitch Energy (Clocked Mode)
At Midscale Transition (00-07 = 127... 128)
Due to Clock Feedthrough (DO - 07 = Constant)
Due to Data Feedthrough (Clock = Constant)

EGM
EGC
EGD

Peak Glitch Current (Clocked Mode)
At Midscale Transition (00- 07 = 127... 128)
Due to Clock Feedthrough (DO - 07 = Constant)
Due to Data Feedthrough (Clock = Constant)

IGM
IGC
IGO

-

-

IIA
%

kn
pF
pV-sec

18
2.0
25

-

-

0.2
55
0.5

-

IEE(O)

-80

-65

-

mA

PD

-

338

458

mW

-100

20

+100

-

-

-

mA

IIA
mA

POWER SUPPLIES
Supply Current VEE(O) = VEE(A) = - 5.72 V
Power Dissipation
Power Supply Sensitivity at Outputs
(- 5.72 < VEE(O), VEE(A) < - 4.68 V)

IIAIV

PSSO

VEE (D) Supply Rejection (VEE(O) = VEE (A) = - 5.2 V, f = 10kHz)

PSRRO

-

100

VEE(A) Supply Rejection (VEE(D) = VEE(A) = - 5.2 V, I = 10kHz)

PSRRA

-

60

-

dB
dB
(continued)

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
6-81

MC10324
TIMING CHARACTERISTICS (TA=2S"C, Iref= 1.11SmA, load=37.SQ//1SpF, VCC= VEE=- S.2V, see Figures 2,3.)
Symbol

Min

Typ

FS

40

60

-

tcaD
tSD
tSFS
tSB
tH
tpw

-

10
B.O
5.0
4.0
0
6.0

-

Transparent Mode (FT = 1)
Data to Output Delay
Sync to Output Delay
BlK to Output Delay
FH to Output Delay
BRT to Output Delay

tDO
tso
tBO
tFO
tRO

-

16
13
14
16
12

-

Output Rise/Fall Time - 10 to 90% of Gray Scale
Enhanced White to Sync level

tRFG
tRFF

-

2.0
3.0

-

ns

-

Output Settling Time

tSET

-

4.0

-

ns

Characteristic
Maximum Conversion or Update Rate
Clocked Mode (FT = 0)
Clock to Output Delay (Data, Controls)
Setup lime - Data to Cony Rising Edge
FH, Sync to Cony Rising Edge
BRT, BlK to Cony Rising Edge
Hold lime - All Inputs (After Cony Rising Edge)
Minimum Clock Width (High or low)

Max

Unit
MHz
ns

-

ns

-

-

FUNCTIONAL DESCRIPTION
Introduction
The MC10324 is an 8-bit DAC intended for video
applications, employing ECl inputs for the data (natural
binary code) and video controls, and outputs capable of
directly driving a standard 50 Q or 75 Q monitor. Its use is not
limited to video, however, any application requiring a high
speed DAC (typically 60 MHz) or a DAC with high output
current capability (up to 44 mA) can use the MC10324. The
input data and controls may be clocked into the internal
registers, or the MC10324 may be used in the transparent
mode eliminating the need for the clock.
The MC10324 may be used in the multiplying mode by
varying the reference current along with the digital inputs
producing the product of the two at the outputs. The reference
current can be varied over a range of 0.5 to 1.7 mA. The
MC10324 requires - 5.2 V, ± 10% for both the analog and
digital supply pins. Power consumption is nominally 338 mW.

DAC Outputs
The outputs of the MCI 0324 are high impedance constant
current sinks whose values depends on the reference current
(I ref) , the binary value of the digital word at DO - D7, and the
status of the video controls (Sync, BlK, FH, and BRT).
Complementary outputs are provided allowing an increased
output swing (when used differentially), or for creation of
special effects required by the application. For a given
reference current, the sum of the two output currents is a
constant equal to:

(10 -) + (10 +) = Iref x 25.86
The Out - output provides a "sync down" waveform, while
the Out + output provides a "sync up" waveform (see Table 1).
Current flow is into4 each of the outputs. Each output's
impedance is typically 100 kQ over the compliance range of
-1.7 to + 0.3 V, and the output capacitance is typically 16 pF.
An unused output cannot be left open - both outputs must be
connected to a voltage within the compliance range. Both
outputs should be equally loaded for best accuracy.

Table 1. Output Levels
BRT= 0
Out-

mV
0
-100
-200
-300
-400
-500
-600
-700
-800
-900
-1000
-1100

BRT= 1
Out +
Sync-

-

-

Normal White-

i

GrayScale

~

-

- Normal Black--Blank--

-

--Sync--

--Blank-- Normal Black-

i

Gray Scale
-

~

Normal White-

Out-

e- Enhanced White -

i

Out+
-Sync-

Enhanced
GrayScale

--Blank--

~

- Enhanced Black-

--Sync--

- Enhanced White-

t

- Enhanced Black--Blank--

Enhanced
Gray Scale

Iref= 1.115 mAo RL = 37.5 n.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
6-82

+

MC10324

Figure 2. Timing Diagram, Clocked Mode
(FT=O)

Cony

00-07

-+______- J

BRT _ _

FH---+-----------J

tSBlrtH1-

Blli----r--------------

J

~-,,-~~--'

s~c----4---------------------------------J

OmV
1/21.5B

Out-

-ll00mV----------------------------------------------------------~~::::~~------------/.
~~~ - - - - - - - - - - - -....-1/...- Blank
~c
Blank
~~~

+ +

NOTES: 1.
2.
3.
4.

Single-ended clock used in production testing.
If differential clock is used, timing would be determined from the crossover point of the two clock signals.
If Convert is used in single-ended mode, timing would be measured from its falling edge.
liming to output from data and controls is from Convert rising edge (threshold) to where the output
has changed to 50% of final value.
5. Reference current = 1.115 mAo Output load = 37.5 U
6. Waveform at Out + is inverted from that shown above.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

6-83

-1

MC10324

Figure 3. Timing Diagram, Transparent Mode
(FT 1)

=

00-07

BRT

FH
tFO
BLK

Sync

OmV

50%
50%

Out-

-tl00mV------------------------------------------------------~~::::~~-------------

1-

l....- Normal

,.

Gray
Scale

White

+

Normal
Black

+

+-I

Enhanced
Black

Blank

+

Sync

-+-

----I

Blank -,

Gray
Scale

NOTES: 1. Reference current = 1.115 rnA. Output load = 37.5 .Q.
2. Waveform at Out + is inverted from that shown above.

3. Timing from DO - 07 and Controls is to where output has changed to 50% of final value.

TRUTH TABLE
Inputs

Outputs

Controls

Out-

Data

Out+

Sync

Blank

Force High

Bright

07-00

(mA)

(mV)

(mA)

(mV)

1
0
0
0
0
0
0
0

X

X
X

X
X

X
X

2B.B

-lOBO

0
0
1
0
0
1

0
1
0
0
1
1

000 ..
000 ..

21.1
19.6
17.7
1.94
1.94
0
0

-790
-736
-663
-73
-73
0
0

0
7.7
9.1
11.1
26.8
26.8
28.8
28.8

0
-289
-341
-416
-1005
-1005
-1080
-1080

1
0
0
0
0

0
0

X
111..
111..

X

NOTES: 1. Current flow IS Into the output pins.

2. Output voltage measured across a 37.5 Q resistor to AGnd.
3. Waveform at Out + is inverted from that at Out-,
4. Reference Current = 1.115 rnA.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

6-84

Condition
Sync
Blank
Normal Black
Enhanced Black
Normal White
Normal White
Enhanced White
Enhanced White

MC10324
DAC Gray Scale (DO - 07)
Within the Gray Scale (all 4 video controls = 0), the current
at Out - is controlled by the data inputs (00 - 07) according
to the following equation:
10 - (GS) =

The current change at each output is equal to:
t>IO(BRT) = Iref x 1.74
The current at 10 _ decreases in magnitUde, while the
current at 10 + increases, when BRT is asserted. BRT is
ineffective when Sync or BlK are asserted, but can be used
at any point within the Gray Scale.
The Blank input (BlK) sets the output currents to the
blanking level used during horizontal and vertical retrace.
The current at Out - is:

Iref x (255-A)
16
+ (lref x 1.74)

The current at Out + in the Gray Scale is determined by:
10+ (GS)

IrefX A

-...:..::..c1-6 - - + (Iref x 8.18)

10 - (BlK)
for the test value of Iref = 1.115 mA, 10 _ varies from 19.6 mA
to 1 .94 mA as the digital inputs (A) vary from D to 255 (DOH to
FFH), and 10 + will vary from 9.12 mA to 26.8 mAo The data
inputs are overridden by Sync, BlK, or FH.
Figure 4 depicts a typical input stage configuration, and
Figure 8 indicates the typical input current. The threshold is
= -1.4 V, independent of VEE(O). An open input is
equivalent to a logic low, but good design practices dictate
that inputs should never be left open. The inputs must be
kept within the range of VEE(O) and OGnd. If an input is
taken more than 0.5 V above Gnd or below VEE(O)
excessive currents will flow, and the OAC output waveform
will be distorted.

= Iref x 18.96

The current at Out + is:
10 + (BlK)

= Iref x 6.9

The BlK input will override the data inputs, FH and BRT,
but is overridden by Sync. Therefore, the BlK input may be
left asserted during the sync time.
The Synchronizing input (Sync) sets the output currents
to the sync level used for normal horizontal and vertical
picture synchronization.
The current at Out - is:
10 - (Sync) = Iref x 25.86
The current at Out + will be leakage current only, typically
< 20 !lA. The Sync input will override all other control inputs

Figure 4. Typical Input Stage

as well as data inputs.
Feedthrough (FT) Input
With FT low, the internal registers are active, and the data
and video controls are clocked through to the OAC on the rising
edgeof Pin 6 (Conv), oronthefalling edgeof Pin 7.ln this mode
the data bits (07 - 00) which may appear asynchronously to
the MC10324 are then presented synchronously to the OAC,
reducing output glitches and noise. This mode is also useful
for synchronizing control functions with other events. While
hold times are typically D ns for all inputs, the setup times prior
to the clock edge must be observed.
With FT high, the registers are transparent and the data
and video controls feed through directly to the DAC. This
mode may be used if the data is presented to the MC10324
from external latches, which ensure minimum skew among
the data bits. In this mode Pins 6 and 7 are not used.

DGnd--~~--------~-----,

+------+----------"\,

+-------(

To Next

Stage

Figure 5. Convert Input Stage

DAC - Video Controls
The four video controls (Sync, BlK, FH, and BRT) are
logic level inputs, ECl compatible, which permit setting the
outputs to standard video levels. All four are active high. The
Truth Table on page 7 indicates their priority.
The Force High input (FHf overrides the data inputs
(DO - 07), setting the DAC inputs to all 1s (FFH). In
most applications, this is equivalent to the normal white
level. FH can be used with the BRT input to create an
enhanced white, but is overridden by Sync or BlK.
The Bright input (BRT) shifts the Gray Scale by =11 % in
the high (white) direction. Typically this function is used to
provide an enhanced, or brighter display so as to highlight
certain portions of the screen. A highlighted cursor is a
typical example.

DGnd~~~----------~---,

-1.3V

+----+---------'10k

Cony ~+-+--__+----_L.
Conv--~~---*--------+--------~

VEE(Dj--<>-----------'

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

6-85

To Next

+-------1 Stage

MC10324
Convert Inputs
The Convert inputs (Pins 6 and 7) are used to clock in
data and the video controls to the internal registers only if
FT (Pin 8) is low. The input stage for these pins is shown
in Figure 5. The pins are internally biased at ~ -1.5 V
with a nominal input impedance of 10 kQ. The inputs may
be driven from complementary ECl clock signals with the
clocking action occurring on the rising edge of Conv and
the falling edge of Canvas the signals cross each other
in voltage.
A single-ended clock source may be used by connecting
either Pin 6 or 7 to a fixed voltage to set the threshold and
applying the clock signal to the other pin. If done this way,
the fixed voltage must be within the range of - 0.3 V to
VEE(D) + 1.3 V. Figure 6 shows three positive edge triggered
examples. Interchanging Pins 6 and 7 provides negative
edge triggered operation. Alternately the VBB reference of
another ECl circuit may be used to set the MC10324's
clock reference.

out of this pin). Due to the op amp's internal feedback, the
voltage at Ref + is the same as that set at Ref -, with a typical
input offset of ± 5.0 mY. The current into Ref + should be
within the range of 0.5 mA to 1.7 mA to maintain 8-bit linearity
and accuracy. A reference current of 1.115 mA is
recommended to obtain EIA-170 and EIA-343-A voltage
levels at the outputs if they are terminated with 37.5 a
(double 75 a terminations).
Ref - is a high impedance input (>10 Ma) which must be
set to a voltage within the range of -0.8 to -1.7 V. A
nominal bias current of ~1.4 j.tA will flow into this pin. In
Figure 7, Iref = Vref/Rref.
Figure 7. Reference Amplifier

Figure 6. Single-Ended Clock Input

620

1-----

3.9k
VEE (D)

i
i
I
I

1----71_

71 Conv

~conv

lo.OI i
MC10324

Clock~Conv
L ____ _

I
I
I

Ra = Rrel
0.5 < Irel < 1.7 rnA
-1.7 V z
w

0:
0:

=>
>=>
D..

I

.~

I
./

VEE(D) = - 5.2 V

140

./"

V

-6.0

-5.0

-4.0

V

u

D..

Z

-:-" - 400

/'
-3.0

-2.0

-1.0

- 600

r

/

(

-u

+1.0

/'

~

!::;

V

V

... V

""

/"

20

/'

!z
w
0:
!5 - 200

/'

60

!

«

,/

;:

I

I--- VEE (D) = - 5.2 V

/'

100

U

~

Figure 9. Input Current, Convert Inputs
200

-u

Vin, INPUT VDLTAGE M

-u

-u

-u

~n

+1.0

Vin, INPUT VOLTAGE M

APPLICATIONS INFORMATION
Power Supplies, Grounding
The PC board layout and the quality of the power supplies
and the ground system at the IC are very important in order
to obtain proper operation. Noise from any source coming
into the device on the VEE supply pins, or ground can cause
an incorrect output code due to interaction with the analog
portion of the circuit. At the same time, noise generated
within the MC10324 can cause incorrect operation if that
noise does not have a clear path to AC ground.
Both the analog and digital power supplies must be
decoupled to the appropriate ground at the IC (within 1"
max) with a 10 ~F tantalum and a 0.1 ~F ceramic. Tantalum
capacitors are recommended since electrolytic capacitors
simply have too much inductance at the frequencies of
interest. The quality of the supplies should then be checked
at the IC with a high frequency scope. Noise spikes (always
present when digital circuits are present) can easily exceed
400 mV peak, and if they get into the analog portion of the IC,
the operation can be disrupted. Noise can be reduced by
inserting resistors and/or inductors between the supplies and
the IC.
If switching power supplies are used, there will usually
be spikes of 0.5 V or greater at frequencies of 50 kHz to
1.0 MHz. These spikes are generally more difficult to
reduce because of their greater energy content. In extreme
cases three terminal regulators (MC7905.2CT), with
appropriate high frequency filtering should be used and
dedicated to the MC10324.
The ripple content of the supplies should not allow their
magnitude to exceed the values in the Recommended
Operating Conditions.

The PC board tracks supplying - 5.2 V to the MC10324
should preferably not be at the tail end of the bus
distribution after passing through a maze of digital circuitry.
The MC10324 should be close to the power supply, or the
connector where the supply voltages enter the board. If the
supply lines are supplying considerable current to other
parts of the board, then it is preferable to have dedicated
lines from the supply or connector directly to the MC10324.
The two ground pins (DGnd and AGnd) must eventually be
connected together, usually near the power supply, although
the specific board layout may dictate a different "best point."
VEE (D) must be referenced to DGnd, and VEE(A) must be
referenced to AGnd.
PC Board Layout
Due to the high frequencies involved, and in particular, the
fast edges of the various digital signals, proper PC board
layout is imperative. A solid ground plane is strongly
recommended in order to have known transmission
characteristics, and also to minimize coupling of the digital
signals into the analog section. Use of wire wrapped boards
should definitely be avoided.
Each PC track should be considered a transmission line,
and if they are of any considerable length (more than a few
inches), they should be terminated according to transmission
line theory. Otherwise reflections back to the signal sources
can occur, disrupting their operation. Additionally, the
overshoots and undershoots which will occur at the
MC10324's input pins can cause its operation to be
disrupted, resulting in a noisy or incorrect output.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

6-87

MC10324
Figure 10. Reference Supply

r---------,

1
Ire!

4.5Vlo40V

MCl403

Input

1

MC10324

1
1

1
1

~~____~___---'~~____~15TI~~.

rO.1

1
1
1

3570

141
1
1

2.0k
1.18k

3570

1
1
1

L_____ ___ f17l

1
1

IAGnd

.J

_

20

-

VEE(A)

Reference Circuits
Since the accuracy of the outputs are directly related to the
accuracy and quality of the reference current and voltage, it
is imperative that accurate and stable references be used at
Pins 14 and 15. The voltage supply used for the digital
circuitry should preferably not be used as a source for either
the reference current or voltage due to the noise spikes and
ripple present on the supply and its ground lines.
Figure 10 indicates a method for generating the reference
signals from a positive supply. The MC1403 reference is a
stable 2.5 V bandgap regulator (± 1%), with a maximum
temperature coefficient of 40 ppm?C, and good ripple and
high frequency noise rejection. In the figure the circuit
supplies -1.48 V to Pin 14, and a current of 1.113 mA to Pin
15.lfthe outputs ofthe MC10324 are terminated with 37.5 n,
the voltage levels will be well within the allowable range
specified by EIA-170 and EIA-343-A.

If the analog - 5.2 V supply (VEE(A)) is fairly clean and
free of digital noise the circuit of Figure 11 may be used.
The TL431 is a stable 2.5 V bandgap reference (± 1%) with
an effective temperatute coefficient of 50 ppm?C. The 5 k
pot allows adjustment for preCise output levels, or it may be
replaced with a precision resistor which provides the correct
voltage at Pin 14.
Figure 12 indicates another reference circuit using the
LM385-1.2 reference diode. Rref is chosen to provide the
desired reference current to Pin 15 knowing that it is set at
-1.235 V. The LM385 is a bandgap type reference with a
± 2% initial accuracy. The 20 k resistor biases the diode at
approximately 200 !1A for minimum temperature variations.
The 0.2 ~F capacitor, with the 20 k resistor, filters out noise
above ~ 40 Hz.

Figure 11. Reference Supply

Figure 12. Reference Supply

-

Iret

1.0k

5.0k ~-......!.",+---i
TL431

2.4k
1.0k

r--------,

r--------,
MCt0324
1

Rre!

1
1
1
1
1
1

~ 1

I

MC10324

1

1
1
1
1

LM385-1.2

1

~
..L

20k

_ .J 17

1L. _ _ _ _ _ _

VEE(A)

VEE(A)

MOTOROLA LlNEARIiNTERFACE ICs DEVICE DATA

6-88

~..L

_.J 17

20
VEE(A)

MC10324
Digitally Modulating an Analog Signal
The MC10324 may be used to digitally modulate (or
attenuate) an analog signal by applying the analog signal to
the reference amplifier. Three methods of doing this are
shown in Figures 13 to 15.

In all three examples the DC reference current is Vref/Rref.
In Figure 13 the AC signal source is referenced to a negative
voltage source (Vref). In Figures 13 and 14 the AC reference
current is equal to VAC divided by Rref. In Figure 15 the AC
reference current is equal to VAC divided by Rb. The AC
signal at Out - and Out + is determined by the following
equations:

Figure 13. Applying an Analog Signal Directly

VO-(AC)

Iref(AC) x (255-A) x RL
16
Iref(AC) x A x RL

Va + (AC)

16

where "A" is the value of the digital word at DO - D7 (0 to 255).
When implementing any of the above schemes, or any
other method of feeding an AC signal to the reference
amplifier, the following operating limits must be observed:
1) The peak values of the reference current
(AC + DC) must be within the range of 0.5 rnA
to 1.7 rnA into Pin 15;
2) The peak values of the voltage at Ref + and Ref must be within the range of - 0.8 V to -1.7 V;
3) The peak values of the voltage at Out - and Out +
must be within the range of -1.7 V to + 0.3 V.
The maximum frequency which can be handled by the
reference amplifier is dependent on the compensation
capacitor (CC) at Pin 16, and the signal amplitude according
to the following equation:

Ra = R,e!
1-1.7V < V,e! < - O.8V]

Figure 14. Capacitor Coupling the AC Voltage

Ra

1.59 x 10- 8
fmax =
Ra = R,e!
1-1.7V < V,e! < - O.8V]

Cc x Ipk

where Ipk is the peak value of the AC reference current (1/2 of
the peak-to-peak value). The small signal bandwidth of the
reference amplifier is = 3.0 MHz.
Components associated with the reference amplifier (Pins
14 - 16) should be physically close to the pins. The board
layout should be neat, preventing unwanted stray capacitive
coupling between the outputs and the reference amplifier. If
Cc is smaller than 5000 pF a ground plane is strongly
recommended. Cc should not be smaller than 250 pF.

Figure 15. Applying a Modulating Current

Ra =R,e!
1-1.7V < V,e! < - O.8V]

TYPICAL APPLICATION CIRCUITS
Figure 16 shows a typical video application circuit
using the MC10324 in the clocked mode. The clock is
single-ended, and the circuit updates the output on the
rising edge of the clock. The Out - pin feeds a standard
75 n monitor through a 75 n cable, which is terminated
at both ends. The reference voltage is supplied by an
LM385-1.2 regulator.

Figure 17 shows a circuit similar to that of Figure 16,
except the MC10324 is used in the transparent mode. The
source of the data bits must provide the 8-bits
simultaneously, with minimum skew, to keep output glitches
to a minimum. If latches, or other anti skew circuitry, are not
available within the microprocessor circuitry, a set of 8-bit
latches between it and the MCI 0324 is recommended, or the
MC10324 should be used in the clocked mode.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

6-89

MC10324
Figure 16. Clocked Mode
6 Cony
7
Cony

Clock
VEE(O)

3.9k

10~F+

Oigital
Inputs

OUlt
OGnd
Reft

0.1+ 5

La.

~~·t

4
3
2
1
24
23
22
21

VEE(O)
FT
00
01
02
03
04
05
06
07

MC10324

f

Ref-

75QCabie

~

19

37.5

15

1.1kl%

'--

000

J.

0.2f.

14

~·o
Video
Mon~or

l.M385 -1.2

20k
Comp
VEE(A)
AGnd

FH
12 BRT
11 BLK
13 Sync

°i?1

16
20
17

10
Video
Controls

.)

18
]75

620
9

-5.2V,± 10% "
OigitaiS upply"

OUl-

"

+10~F +

-5.2V,±10%
" Analog Supply

0.1

J

NOTES: 1. Gray Scale inputs, video controls, and clock are to be referenced to digital ground.
2. Outputs and reference circuitry are to be referenced to analog ground.
3. PC board layout to be such that digital noise does not get into the analog side circuitry.
4. Analog and digital grounds to be connected together. Location of this connection is board
layout dependent,and is to be such that digital ground noise does not show up in the analog signals.
5. EeL termination required at all inputs per Eel system requirements.

Figure 17. Transparent Mode

Out-Pl!8-r----~c=~~~~==)__+_r~
75

OUlt

- 5.2V, ± 10%
Oigital Supply

Reft

,ECl
~p

s

y
S

T
E
M

I l
I
I
I
I
I S
L

24
23
22
21

00
01
02
03
04
05
06
07

19

37.5

15

1.1kl%

000
Video

Mon~or

0.2
MC10324

Ref-

l.M385 -1.2

14
20k

Comp

16

0.01
-5.2V,±10%
Analog Supply

VEE(A)
0.1

to
FH
12
BRT
11
BlK
13
Sync

AGnd

MOTOROLA LlNEARflNTERFACE ICs DEVICE DATA

6-90

0

MC10324
GLOSSARY
Bandgap Reference - A voltage reference circuit based on
the predictable base-emitter voltage of a transistor. The
silicon bandgap voltage of ~1 .2 V is the basis for generating
other voltages which are stable with time and temperature.
Bipolar Input - A mode of operation whereby the analog
input (of an A-D), or output (of a DAC), includes both negative
and positive values. Examples are: - 5.0 V to + 5.0 V, - 2.0 V
to + 8.0 V, etc.
DAC Current Gain - The internal gain the DAC applies to
the reference current to determine the full scale output
current. The actual maximum current out of a DAC is one
lSB less than the full scale current.
Differential Gain - In video systems, differential gain is a
component's change in gain as a function of luminance level.
In a color picture, contrast will be affected if the differential
gain is not zero.
Differential Nonlinearity - The maximum deviation in the
actual step size (one transition level to another) from the ideal
step size. The ideal step size is defined as the Full Scale
Range divided by 2n. This error must be within ± 1 lSB for
proper operation.
Differential Phase - In video systems, differential phase is
the change in the phase modulation of the chrominance as a
function of the luminance level. The hue in a color picture will
be distorted if the differential phase is not zero.
ECl - Emitter coupled logic.
Full Scale Range - The difference between the minimum
and maximum end points of the analog input (of an AID), or
output (of a DAC), plus one lSB.
Gain Error - The difference between the actual and
expected gain (end point to end point), with respect to the
reference, of a data converter. The gain error is usually
expressed in lSBs, or percent.
Glitch Area - The energy content of a glitch, specifically in
volt-seconds. It is the area under the curve of the glitch
waveform. For a symmetrical glitch, the area and the energy
can be zero.
Gray Code - Also known as reflected binary code, is a digital
code such that each code differs from adjacent codes by only
one bit. Since more than one bit is never changed at each
transition, race condition errors are eliminated.
Integral Nonlinearity - The maximum error of an AID or
DAC, transfer function from the ideal straight line connecting
the analog end points. This parameter is sensitive to
dynamics, and test conditions must be specified in order to
be meaningful. This parameter is the best overall indicator of
the device's performance.
lSB - least Significant Bit. It is the lowest order bit of a
binary code.
line Regulation - The ability of a voltage regulator to
maintain a certain output voltage as the input to the regulator
is varied. The error is typically expressed as a percent of the
nominal output voltage.
load Regulation - The ability of a voltage regulator to
maintain a certain output voltage as the load current is varied.
The error is typically expressed as a percent of the nominal
output voltage.

Monotonicity - The characteristic of the transfer function
whereby increasing the input code (of a DAC), or the input
signal (of and AID), results in the output never decreasing.
Nonmonotonicity occurs if the differential nonlinearity
exceeds ± 1 lSB.
MSB - Most Significant Bit. It is the highest order bit of a
binary code.
Natural Binary Code - A binary code defined by:
N ~ An2n + ... + A323 + A222 + A121 + A02 0
where each "A" coefficient has a value of 1 or O. Typically, all
zeros correspond to a zero input voltage of an AID, and all
ones correspond to the most positive input voltage.
Nyquist Theory - See Sampling Theorem.
Offset Binary Code - Applicable only to bipolar input (or
output) data converters, it is the same as Natural Binary
code, except that all zeros correspond to the most negative
output signal (of a D/A), while all ones correspond to the most
positive output.
Output Compliance - The maximum voltage range to
which the DAC outputs can be subjected, and still meet
all specifications.
Power Supply Rejection Ratio - The ability of a device to
reject noise andlor ripple on the power supply pins from
appearing at the outputs. An AC measurement, this
parameter is usually expressed in dB rejection.
Power Supply Sensitivity - The change in a data
converter's performance with changes in the power supply
voltage(s). This parameter is usually expressed in percent of
full scale versus tN.
Propagation Delay - For a DAC, the time from when the clock
input crosses its threshold to when the DAC output( s) changes.
Quantization Error - Also known as digitization error or
uncertainty. It is the inherent error involved in digitizing an
analog signal due to the finite number of steps at the digital
output versus the infinite number of values at the analog
input. This error is a minimum of ± 1/2 lSB.
Resolution - The smallest change which can be discerned
by an AID converter, or produced by a DAC. It is usually
expressed as the number of bits (n), where the converter has
2n possible states.
Sampling Theorem - Also known as the Nyquist Theorem.
It states that the sampling frequency of an AID must be no
less than 2x the highest frequency (of interest) of the analog
signal to be digitized in order to preserve the information of
that analog signal.
Settling Time - For a DAC, the time required for the output to
change (and settle in) from an initial ±1/2 lSB error band to
the final ± 1/2 lSB error band.
Two's Complement Code - A binary code applicable to
bipolar operation, in which the positive and negative codes of
the same analog magnitude sum to all zeros, plus a carry. It
is the same as offset binary code, with the MSB inverted.
Unipolar Input - A mode of operation whereby the analog
input range (of an AID), or output range (of a D/A), includes
values of a single polarity. Examples are:
oto +10 V, 0 to - 5.0 V, + 2.0 V to + 8.0 V, etc.

Additional Information regarding the transmission characteristics of PC board tracks can be found in
Motorola's MECL System Design Handbook (HB2D5).

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
6-91

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

6-92

Interface Circuits

In Brief ...
Page

Described in this section is Motorola's line of interface
circuits, which provide the means for interfacing
microprocessor or digital systems to the external world, or
to other systems.
Also included are devices which allow a micro- processor
to communicate with its own array of memory and peripheral
I/O circuits.
The line drivers, receivers, and transceivers permit
communications between systems over cables of several
thousand feet in length, and at data rates of up to several
megahertz. The common EIA data transmission standards,
several European standards, IEEE-488, and IBM 360/370
are addressed by these devices.
The peripheral drivers are designed to handle high
current loads such as relay coils, lamps, stepper motors, and
others. Input levels to these drivers can be TTL, CMOS, high
voltage MOS, or other user defined levels. The display
drivers are designed for LCD or LED displays, and provide
various forms of decoding.

Enhanced Ethernet Serial Transceiver (EEST)

7-2

High Performance Decoder Driver/Sink Driver ........ 7-3
ISO 8802-3[IEEE 802.3] ........................... 7-3
Microprocessor Bus Interface
Address and Control Bus Extenders .............. 7-4
Microprocessor Data Bus Extenders. . . . . . . . . . . . .. 7-4
Magnetic Read/Write ..... . . . . . . . . . . . . . . . . . . . . .. 7-4
Single-Ended Bus Transceivers ....................
For Instrumentation Bus ........................
For High-Current Party-Line Bus ................
Line Receivers
General Purpose . . . . . . . . . . . . . . . . . . . . . . . . . . ..
EIA Standard ...............................
Line Drivers
General Purpose ............................
360/370 I/O Interface ........................
EIA Standard ...............................
Line Transceivers ..............................
EIA-232-DN.28 CMOS Drivers/Receivers .........
Peripheral Drivers .............................
IEEE 802.3 Transceivers .......................

7-5
7-5
7-5
7-5
7-5
7-6
7-6
7-6
7-6
7-7
7-7
7-7

CMOS Display Drivers
Display Drivers ................................ 7-8
Functions ..................................... 7-8
Package Overview ............................... 7-9
Index .......................................... 7-10
Data Sheets .................................... 7-11

Enhanced Ethernet Serial Transceiver (EEST)
MC68l60P
TA = 00 to +70°C, Case 848D
Connection to the twisted pair media is accomplished with
common 1OBASE-Tlilters and transformers. The AUI requires
standard transformers. (The EEST is packaged in a 52-pin
Thin Quad Flat Pack.)

The MC68160 is a BiCMOS integrated circuit for use in
ethernet applications. The IC integrates the Attachment Unit
Interface (AUI), the 10BASE-T interface and the
communications controller interface. The communications
interface Is compatible with Motorola, AMD, Intel, National
Semiconductor, Fujitsu, Western Digital controllers and is set
by the bias of external pins.

D-Connector
toAUI Drop
Cable

;;;

~

B

j
~
E
B
"'!

To tOBase·T
Twisted Pair
Interlace

ill

Communication Controller Selection
CSO

CS1

1

1
1

0

1
0

0
0

1

1

CS2
0
0
0
0
1

802.3 Communication Controller
Motorola M068360, AMD 7990 & 790900
Intel 8256, 82590, 82593, 82596
Fujitsu M886950, M886960
National 8390, 830690, 839328
Standby Low Ourrent Mode

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

7-2

High Performance Decoder Driver/Sink Driver
MC34142DW, FN
TA = 0° to +70°C, Case 751 F, 776

m

0-------,

Output
Enable

The MC34142 is a high performance 4 to 16 multiplexed
driver. This integrated circuit features a 4 to 16 decoder,
16 open drain N-channel MOS output devices with clamp
diodes. The outputs are controlled by 4 address inputs, an
output enable, and a chip enable.
Typical applications include solenoid drivers, LED drivers,
lamp drivers, and relay drivers.

-=

fl

Chip
Enable
A

Output 1
--0 Output 2
-oOutpu13
Kt
-0 Outpul 4
-0 Oulput 5
-0 Output 6
-0 Output 7
Output B

K2

ISO 8802-3[IEEE 802.3] 1OBASE-T Transceiver
MC34055DW, P

TTL, CMOS, and raised ECL compatible, and the interface
to the Twisted Pair (TP) media is supported through
standard 10BASE-T filters and transformers. Differential
data intended for the TP media is provided a 50 ns
pre-emphasis and data at the TP receiver, is screened by
Smart Squelch circuitry for specific threshold, pulse width,
and sequence requirements.

TA = 0° to +70°C, Case 751 E, 724
The Motorola 10BASE-T transceiver, designed to
comply with the ISO 8802-3[IEEE 802.3] 10BASE-T
specification, will support a Medium Dependent Interface
(MDI) in an embedded Media Attachment Unit (MAU). The
interface supporting the Data Terminal Equipment (DTE) is

5.0 V

Balun

r ___________________

Loop Back

5.0V

Test Select

l~~~~lC~D~~)_,
I

2 TXDataA
3 TXDataB

4

TXENH

B AXDataA

9 AXDataB
10 AXENH

SIA
14

CTLH

13

JABB H

15

I
I

Duplex Mode
Selec1

FU-L-L~DiDl1--li.-~~~J
17

I
LNKFLH I
V
CC

121

TTIJCMOS

t2kO I

LEDPartf L _ _

_

7}

mA
Gnd

-=

UnkBeatl-_ _--'
Conlrol

I19 IS
_

-=
PWA
Gnd

22 SQEENL

_______

-=

DIG
Gnd

24

Clk+·
20pF

ftf

_

23

Clk20pF

oul

10MHz

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
7-3

Duplex
ModeSelec1

Microprocessor Bus Interface
features, such as hysteresis, short circuit protection, clamp
diode protection, or special control functions.

Motorola offers a spectrum of line drivers and receivers
which provide interfaces to many industry standard
specifications. Many of the devices add key operational

Address and Control Bus Extenders
These devices are designed to extend the drive capabilities of today's standard microprocessors. All devices are fabricated
with Schottky TTL technology for high speed.

0.5

2.4

13

6

11

Hex 3-State Buffers/Inverters
TA = 0° to +75°C

MC8T971
MC6887

Noninverting

MC8T981
MC6888

Inverting

Vee

Enable 4

The noninverting MC8T97/MC6887 and inverting
MC8T98/ MC6888 provide two Enable inputs, one controlling
four buffers and the other controlling the remaining two buffers.

Input A

Enable 2

Output A

Input F
Output F

MC8T97/MC6887(1) - Noninverting
MCST98/MC6888(1) -Inverting

Input E

Output B

(1 )These devices may be ordered by either of the paired numbers.

Output E

Input C
Output C

Input 0

Gnd

Output 0
'Add Inverter for
MC6888/MCBT98.

Microprocessor Data Bus Extenders

Magnetic ReadlWrite
~~~

MC3471

Tunnel/Straddle Erase Controller. Provides entire interface between floppy disk heads and
the head control and write data signals for straddle erase heads.

MC3470,A

Floppy Disk Read Amplifier System. A monolithic read amplifier system for reading
differential AC signals from the magnetic head and converting to a digital output.

MC34167

Magnetic Tape Sense Amplifier. Trace independent preamplifiers with individual gain
control. Optimized for use with 9·track magnetic tape memory systems.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

7-4

P1738

oto + 70

P1707

Single-Ended Bus Transceivers
For Instrumentation Bus, Meets GPIBIIEEE Standard 488
Driver Characteristics

Receiver Characteristics

Output
Current
(rnA)

Propagation
Delay
Max (ns)

Propagation
Delay
Max (ns)

Transceivers
Per Package

48

30

50

8

Suffix!
Package

Device
MC3447

Comments
Input hysteresis, open collector,
3-state outputs with terminations

P3/724

U623
P/649

17

25

MC3448A

4

Input hysteresis, open collector,
3-state outputs with terminations

P/648
D/7518

U620

For High Current Party-Line Bus for Industrial and Data Communications
Driver Characteristics

Receiver Characteristics

Output
Current
(rnA)

Propagation
Delay
Max (ns)

Propagation
Delay
Max (ns)

Transceivers
Per Package

100

15

15

4

Sufflxl
Package

Device
MC26S10

Comments
Open collector, outputs, common
enable

P/648
D/7518

U620

Line Receivers
General Purpose
S = Single
Ended
D = Differential
D

Type (1)
of
Output

TP

~rop

elay
Time
Max (ns)

Party
Line
Operation

Strobe
or
Enable

Power
Supplies
(V)

25

V

V

±5.0

V

V

OC

OC

(1 lac

TP

MC3450
MC3452

Suffix!
Package

Receivers
Per
Package

D/7518
P/648

Companion
Drivers

4

MC3453

2

MC75S110

Comments
Quad version of
MC751 07/1 08

U620

TP
S

Device

V

30

V

+ 5.0

Strobe
or
Enable

Power
Supplies
(V)

MC75107
MC75108

P/646

MC3437

P/648

U632

Dual version of
MC3450/2

Input hysteresis

6

U620

= Open Collector, TP = Totem-pole output

EIA Standard
S= Single
Ended
D Differential

Output

tprop
Delay
Time
Max (ns)

S

TP

4000

-

-

S

R(2)

85

-

-

=

Type

01

Party
Line
Operation

+ 5.0

Device

Suffix!
Package

MC14C898
MC14C898

P/646
D/751 A

MC1489
MC1489A

0/751A

Receivers
Per
Package

Companion
Drivers

4

MC14C888

EIA-232-DI
EIA-562

MC1488

EIA-232-0

AM26LS31
MC3487

EIA-422/423

MC751728
MC751748

EIA-422/4231
485

Comments

P/646

U632
S,D

TP

30

V

V

AM26LS32
MC3486

P/648
D/7518

35

V

V

SN75173
SN75175

N/648
0/7518

U620

(2lR = Res,stor Pull-up, TP = Totem-pole output

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

7-5

Line Drivers

15

o

15

±5.0

MC3453

P/648
U620

4

MC3450
MC3452

Quad version of
MC75S110

MC75S110

P/646
U632

2

MC75107
MC75108

Dual version of
MC3453

MC3481

P/648
U620

4

MC3485

P/648

MC75172B
MC75174B

N!648

3601370 1/0 Interface
60

45

S

V

V

V

V

+5.0

Short circuit
Fault flag

EIA Standard

85
48

35

+5.0

20

SN75173
SN75175

EfA-485

J/620
P/648

MC3486

EIA-422
with 3-state
outputs

V

V

MC3487

V

V

AM26LS31

PC/648
DC/620

±12

MC3488A
(IIA9636A)

PI 1626
D!751B

±7.0to
±12

MC14C88B

±9.0to
±12

MCI488

4

D!751B

U620

20

S

AM26LS32

2

MC3486
AM26L532

EIA-4231232-D

4

MC14C89B
MCI4C89B

EIA-232-DI
EIA-562

MCI489
MCI489A

EIA-232-D

AM26LS32
MC3486

EIA-422
EIA-423

U/693
15
10

3500
350

P/646
D!75IA

P/646
D!751 A

U632
60

SID

300

42211'
423 -

±5.0

AM26LS30

PC/648

2(422)
4(423)

Switchable

Line Transceivers

20

30

DE,RE

+ 5.0

DE

MC34050

D!751B
P/648

MC34051

D!751B

P/648

MOTOROLA LlNEARIINTERFACE ICs DEVICE DATA
7-6

2

2

EIA-422

EIA·232·D/V.28 CMOS Drivers/Receivers
Device

Sufflx/Packege

Pins

Drivers

Receivers

Power Supplies (V)

MC145403

PJ738
DW/751D

20

3

5

± 5.0 to ± 12

MC145404

PJ738
DWJ751D

4

4

5

3

MC145405
MC145406

P/648
DWJ751G

16

MC145407

PJ738
DWJ751D

20

MC145408

PJ724
DWJ751E

24

5

5

±5.0to± 12

MC145705

PJ738
DWJ751D

20

2

3

+5.0

MC145706

PJ738
DWJ751D

3

2

MC145707

PJ724
DWJ751E

Perino~''''''''''1

Features

3
+5.0

24

Charge Pump

Charge Pump, Power Down

3

Drivers

14Vt025V
PMOS

50

TTl,CMOS
PMOS
14 Vto 25
PMOS

7

P/648

16

FNJ776
DWJ751F

1 of 16 Power
Decoder

4

B/648C

Invert

v

TTL, 5.0 V
CMOS
8.0Vto 18
MOS

1500

v

TTl,5.0V
CMOS

0.15

35

TTl,5.0V
CMOS

1.0

50

UlN2068B

IEEE 802.3 Transceivers
MC34055

+ 5.0 Vdc

Transmit and
Receive over
4 Pins

Raised
ECl,
CMOS

802.3 Type
10BaseT

Transceiver with non-return to zero (NRZ)
interface. Intended for but not restricted to
concentrators and repeator applications.

MC68160

+ 5.0 Vdc

Transmit and
Receive over
4 Pins

TTL,
CMOS

802.3 Type
10BaseT/
AUIINRZ

Interfaces gluelessly to Motorola's MC68360
communications controller.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

7-7

DWJ751 E
PJ724
P/648

CMOS Display Drivers
These CMOS devices include digit as well as matrix drivers
for LEDs, LCDs, and VFDs. They find applications over a wide

range of end equipment such as instruments, automotive
dash boards, home computers, appliances, radios and clocks.

Display Drivers
. . . ~[. . r . il·,~,~~,li I;:. . :l.:j~~~~;~~~~'i
LCD
(Direct Drive)

Muxed LCD
(1/4 Mux)

LED,
Incandescent,
Fluorescent(1 )

Muxed LED
(1/4 Mux)
(1/5 Mux)

•.'.;.,.

Parallel BCD

I)rl~~ CaRa~II!,1Y
~er. P~ckage

PI1~Cl!lp
Latch

7 Segments

V

i'~;i~,:~6~n~~l;";.";
,d"i.i Ii...
~
"··.'""-:~urrent·;~?
•. "", ...
~1.0mA

Blank

MC14543B
MC14544B

Blank, Ripple Blank
20~A

MC145453

Serial Binary
[Compatible with the
Serial Peripheral
Interface (SPI) on
CMOS MCUs]

33 Segments
or Dots
48 Segments
or Dots

~200 ~A

MC145000

Parallel BCD

7 Segments

44 Segments
or Dots

MC145001
Blank, Lamp Test

25mA

Serial Binary
[Compatible with the
Serial Peripheral
Interface (SPI) on
CMOS MCUsj

4 Digits +
Decimals

LED
(Direct Drive)

Parallel Hex

7 Segments +
A thru F Indicator

(Interfaces to
Display Drivers)

Parallel BCD

7 Segments

(1)Absolute maximum working voltage
(2) On-chip current·limiting resistor

=:

Blank

65mA

MC14547B

Oscillator
(Scanner)

50 mA
(Peak)

MC14499

Oscillator (Scanner),
Low·Power Mode,
Dimming

Ot035mA
(Peak)
Adjustable

MC14489

10mA(2)

MC14495.1

V

5 Characters +
Decimals or 25
Lamps

MC14511B
MC14513B

Blank, Ripple Blank,
Lamp Test

Ripple Blank,
Enable

MC14558B

18 V

Functions

I. . . . .:... ·Devlee '.... '. r. ..n.:····,'....,I:',·. '. . <".'" '.'JI" .... ,..., '.'." •. ',i~L1nctlon·. ".' '.,...... 'J,!) "'.'" .,.'..... '.'

,

..

![.... .... ,.... ".~ac:kage·, ,.".

MC14489

Multi-Character LED Display/Lamp Driver

738,7510

MC14495.1

Hexadecimal-to-7 Segment Latch/Decoder ROMlDriver

648,751G

MC14499

4-Digit 7 -Segment LED Display Decoder/Driver with Serial Interface

707,7510

MC14511B

BCD-to-7 -Segment Latch/Decoder/Driver

620,648

MC14513B

BCD-to-7-Segment Latch/Decoder/Driver with Ripple Blanking

726,707

MC14543B

BCD-to-7-Segment Latch/Decoder/Driver for Liquid Crystals

620,648

MC14544B

BCD-to-7-Segment Latch/Decoder/Driver with Ripple Blanking

726,707
620,648

MC14547B

High-Current BCD-to-7-Segment Decoder/Driver

MC14558B

BCD-to-7-Segment Decoder

620,648

MC145000

48-Segment Serial Input Multiplexed LCD Driver (Master)

709,776

MC145001

44-Segment Serial Input Multiplexed LCD Driver (Slave)

707,776

MC145453

33-Segment, Non-Multiplexed LCD Driver with Serial Interface

711,777

• Replace + with package identifier (see product data),

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

7-8

Interface Package Overview

CASE 620
CERAMIC
D, DC, J, L SUFFIX

•

CASE 646
PLASTIC
PSUFFIX

CASE 623
CERAMIC
LSUFFIX

CASE 626
PLASTIC
P1 SUFFIX

CASE 648, 646C
PLASTIC
B, N, P, PC SUFFIX

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
7-9

CASE 632
C:"'!~NlI.C
L:SUFFIX

Interface Circuits
Device

Function

Page

AM26LS30
AM26LS31
AM26LS32
MC1411,B, MC1412,B,
MC1413,B, MC1416,B
MC1472
MC1488
MC1489,A
MC14C88B
MC14C89B, MC14C89AB
MC26S10
MC3437
MC3447
MC3448A
MC3450, MC3452
MC3453
MC3467
MC3469
MC3470, MC3470A
MC3471
MC3481, MC3485
MC3486
MC3487
MC3488A
MC6875, MC6875A
MC8T26A
MC8T97, MC8T98
MC751 07, MC75108
MC34050, MC34051
MC34142
MC75172B
MC75174B
MC75S110
SN75173, SN75175
ULN2068B
ULN2801, ULN2802,
ULN2803, ULN2804

Dual Differential/Quad Single-Ended Line Drivers ....................
Quad Line Driver with NAND Enabled Three-State Outputs ...........
Quad EIA-422/423 Line Receiver ..................................
High Voltage, High Current Darlington Transistor Arrays ..............

7-11
7-22
7-25
7-37

Dual Peripheral-High-Voltage Positive "Nand" Driver .................
Quad Line Driver ................................................
Quad Line Receivers .............................................
Quad Low Power Line Driver ......................................
Quad Low Power Line Receiver ...................................
Ouad Open-Collector Bus Transceiver .............................
Hex Bex Receiver with Input Hysteresis ............................
Bidirectional Instrumentation Bus (GPID) Transceiver ................
Bidirectional Instrumentation Bus (GPIB) Transceiver ................
Quad MTTL Compatible Line Receivers ............................
MTTL Compatible Qud Line Driver .................................
Triple Wideband Preamplifier with Electronic Gain Control (EGC) ......
Floppy Disk Write Controller ......................................
Floppy Disk Read Amplifier .......................................
Floppy Disk Write Controller/Head Driver ...........................
Quad Single-Ended Line Driver ....................................
Quad EIA-422/423 Line Receiver ..................................
Quad Line Driver with Three-State Outputs .........................
Dual EIA-423/EIA-232D Line Driver ................................
MC6800 Clock Generator .........................................
Quad Three-State Bus Transceiver ................................
Hex Three-State Buffer Inverters ..................................
Dual Line Receivers .............................................
Dual EIA-422/423 Transceiver ....................................
High Performance Decoder/Sink Driver .............................
Quad EIA-485 Line Drivers with Three-State Outputs ................
Quad EIA-485 Line Drivers with Three-State Outputs ................
Monolithic Dual Line Drivers ......................................
Quad EIA-485 Line Receivers ..... , ...............................
Quad 1.5 A Sinking High Current Switch ............................
Octal High Voltage, High Current Darlington Transistor Arrays .........

7-41
7-44
7-50
7-55
7-61
7-66
7-69
7-72
7-78
7-83
7-90
7-94
7-99
7-109
7-123
7-134
7-139
7-142
7-146
7-150
7-28
7-33
7-172
7-161
7-168
7-182
7-182
7-177
7-193
7-198
7-202

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
7-10

MOTOROLA

AM26LS30

SEMICONDUCTOR-----TECHNICAL DATA

Advance Information

Dual Differential (EIA-422-A)/
Quad Single-Ended (EIA-423-A)
Line Drivers
The AM26LS30 is a low power Schottky set of line drivers which can be
configured as two differential drivers which comply with EIA-422-A standards, or
as four single-ended drivers which comply with EIA-423-A standards. A mode
select pin and appropriate choice of power supplies determine the mode. Each
driver can source and sink currents in excess of 50 mAo
In the differential mode (EIA-422-A), the drivers can be used up to 10 Mbaud.
A disable pin for each driver permits setting the outputs into a high impedance
mode within a ±1 0 V common mode range.
In the single-ended mode (EIA-423-A) each driver has a slew rate control pin
which permits setting the slew rate of the output signal so as to comply with
EIA-423-A and FCC requirements and to reduce crosstalk. When operated from
symmetrical supplies (±5.0 V), the outputs exhibit zero imbalance.
The AM26LS30 is available in a 16-pin plastiC DIP and surface mount package.
Ambient operating temperature range is -40° to +85°C.
• Operates as Two Differential EIA-422-A Drivers, or Four Single-Ended
EIA-423-A Drivers
• High Impedance Outputs in Differential Mode
• Short Circuit Limit In Both Source and Sink Modes
• ± 10 V Common Mode Range on High Impedance Outputs
• ± 15 V Range on Inputs
• Low Current PNP Inputs Compatible with TTL, CMOS, and MOS Outputs
• Individual Output Slew Rate Control in Single-Ended Mode
• Replacement for the AMD AM25LS30 and National Semiconductor DS3691

DUAL DIFFERENTIAU
QUAD SINGLE-ENDED
LINE DRIVERS
SILICON MONOLITHIC
INTEGRATED CIRCUIT

PC SUFFIX
PLASTIC PACKAGE
CASE 648

DSUFFIX
PLASTIC PACKAGE
CASE 751B
(So-I6)

PIN CONNECTIONS

SR·A
Input A 2

Output A

~
EnableAB

OutputB

Mode
BLOCK DIAGRAMS

SINGLE-ENDED MODE
EIA-423-A
16

DIFFERENTIAL MODE
EIA-422-A

SR,C

~
Enable CD
Input 0

OutputC
Output 0

VEE

~15 OulA

SR-A

SR-O
(Top View)

.
2
Input A

13

SR·B

Gnd

3
14
~
InputB
OulB

6

SR.B

~SR-C

Input C

--v--;-

Input 0

7
10
~
Out 0

OuI C
SR.O

ORDERING INFORMATION
___ 6

Part No.

Ambient
Temperature
Range

Package
Type

AM26LS30PC
MC26LS30D

-400 10 +85°C

Plastic DIP
So-16

Enable CD

VCC- 1
VEE-8

Gnd-5

Mode-4

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
7-11

AM26LS30
MAXIMUM OPERATING CONDITIONS
Rating
Power Supply Voltage

Symbol

Value

Unit

Vee
VEE

-{).5. +7.0
-7.0, +0.5

Vdc

Input Voltage (All Inputs)

Vin

-{).5, +20

Vdc

Applied Output Voltage when in High Impedance Mode
(Vce = 5.0 V, Pin 4 = Logic 0, Pins 3, 6 = Logic 1)

Vza

±t5

Vdc

Output Voltage with Vee, VEE = 0 V

Vzb

±15

Output Current

10

Self limiting

-

Junction Temperature

T

-B5, +150

°e

Devices should not be operated at these limits. The "Recommended Operating Conditions" table provides
conditions for actual device operation.

RECOMMENDED OPERATING CONDITIONS
Rating

Symbol

Min

Typ

Max

Unit

Power Supply Voltage (Differential Mode)

Vee
VEE

+4.75
-{).5

5.0
0

+5.25
+0.3

Vdc

Power Supply Voltage (Single-Ended Mode)

Vee
VEE

+4.75
-5.25

+5.0
-5.0

+5.25
-4.75

-

+15

Input Voltage (All Inputs)

Vin

0

Applied Output Voltage (when in High Impedance Mode)

Vza

-10

Applied Output Voltage, Vee = 0

Vzb

-10

Output Current

10

-B5

Operating Ambient Temperature (See text)

TA

-40

Vdc

+10
+10
+65

rnA

+85

°e

All limits are not necessarily functional concurrently.

ELECTRICAL CHARACTERISTICS (EIA-422-A differential mode, Pin 4:> 0.8 V, -40 o e < TA < +85°e, +4.75 V 5 Vee 5 +5.25 V,
VEE = Gnd unless otherwise noted)
Characteristic
Output Voltage (see Figure 1)
Differential, RL = ~, Vee = 5.25 V
Differential, RL = 100 n, VCC = 4.75 V
Change in Differential Voltage, RL = 100 n (Note 4)
Offset Voltage, RL = 100 n
Change in Offset Voltage', RL = 100 n
Output Current (each output)
Power Off Leakage, VCC = 0, -10 V 5 Vo 5 +10 V
High Impedance Mode, VCC = 5.25 V, -10 V 5 VO:> +to V
Short Circuit Current (Note 2)
High Output Shorted to Pin 5 (TA = 25°C)
High Output Shorted to Pin 5 (-40°C < TA < +85°C)
Low Output Shorted to +6.0 V (TA = 25°C)
Low Output Shorted to +6.0 V (-40°C < TA < +85°C)
Inputs
Low Level Voltage
High Level Voltage
Current @ Vin = 2.4 V
Current @ Vin = 15 V
Current@Vin = 0.4 V
Current, 0:> Vin 515 V, VCC = 0
Clamp Voltage (lin = -12 rnA)

Symbol

Min

Typ

Unit

Unit

IVODll
IVOD21

-

ILl.VOD21
VOS
ILl.Vosl

-

4.2
2.6
10
2.5
10

6.0

2.0

400
3.0
400

Vdc
Vdc
mVdc
Vdc
mVdc

10LK
102

-100
-100

0
0

+100
+100

J.lA

ISCISCISC+
ISC+

-150
-150
60
50

-95

-BO
-50
150
150

rnA

0.8

Vdc
Vdc

VIL
VIH
IIH
IIHH
IlL
IIX
VIK

Power Supply Current (VCC = +5.25 V, Outputs Open)
(0,;; Enable 5 Vcc)

ICC

-

2.0

-

-

-200

-1.5

75

-

0
0
-8.0
0

40
100

-

-

16

30

~A

Vdc
rnA

-

NOTES: 1. All voltages measured with respect to Pm 5.

2. Only one output shorted at a time, for not more than 1 second.
3. Typical values established at +25°C, Vee = +5.0 V, VEE = -5.0 V.
4. Vin switched from O.S to 2.0 V.
5. Imbalance is the difference between IV02) with Vin < 0.8 V and IV021 with Vin > 2.0 V.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

7-12

-

-

AM26LS30
TIMING CHARACTERISTICS (EIA-422-A differential mode, Pin 4,; O.B V, TA = +25"C, VCC

= +5.0 V, VEE = Gnd,

unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

Differential Output Rise Time (Figure 3)

tr

-

70

200

ns

Differential Output Fall Time (Figure 3)

tl

Propagation Delay Time - Input to Differential Output
Input Low to High (Figure 3)
Input High to Low (Figure 3)

tpDH
tpDL

-

90
90

200
200

Skew Timing (Figure 3)
ItpDH to tpDLI for Each Driver
Max to Min tpDH Within a Package
Max to Min tpDL Within a Package

tSKt
tSK2
tSK3

-

-

9.0
2.0
2.0

-

Enable Timing (Figure 4)
Enable to Active High Differential Output
Enable to Active Low Differential Output
Enable to 3-State Output From Active High
Enable to 3-State Output From Active Low

tPZH
tpZL
tPHZ
tpLZ

-

150
190
BO
110

300
350
350
300

ns

-

ns

ns

ELECTRICAL CHARACTERISTICS (EIA-423-A single-ended mode, Pin 4" 2.0 V, -40"C < TA < +B5"C, +4.75 V ,;IVccl,
IVEEI < 5 25 V unless otherwise noted)
Characteristic

Unit

Symbol

Min

Typ

Max

Output Voltage (VCC = IVEEI = 4.75 V)
Single-Ended Voltage, RL = = (Figure 2)
Single-Ended Voltage, RL = 450 n (Figure 2)
Voltage Imbalance (Note 5), RL = 450 n

IV011
IV021
16V 021

4.0
3.6

6.0
6.0
0.4

Slew Control Current (Pins 16, 13, 12, 9)

ISLEW

-

4.2
3.95
0.05
±120

-

J.LA

IOLK

-100

0

+100

fiA

ISC+
ISC+
ISCISC-

60
50
-150
-150

-

BO

150
150
-60
-50

mA

-

O.B

-

-

Vdc
Vdc

-

0
0

40
100

-200

-B.O

Vdc

Output Current (Each Output)
Power Off Leakage, VCC = VEE = 0, -6.0 V,; VO'; +6.0 V
Short Circuit Current (Output Short to Ground, Note 2)
Yin ,; O.B V (TA = 25"C)
Yin ,; O.B V (-40"C < TA < +B5"C)
Yin " 2.0 V (TA = 25"C)
Yin " 2.0 V (-40"C < TA < +B5"C)
Inputs
Low Level Voltage
High Level Voltage
Current @ Yin = 2.4 V
Current @ Yin = 15 V
Current @ Yin = 0.4 V
Current, 0,; Vin'; 15 V, VCC = 0
Clamp Voltage (lin = -12 mAl

VIL
VIH
IIH
IIHH
IlL
IIX
VIK

Power Supply Current (Outputs Open)
VCC = +5.25 V, VEE = -5.25 V, Yin = 0.4 V

ICC
lEE

2.0

-

-1.5

-

-22

-95

J.LA

-

-

-

Vdc

17

30

mA

0

-B.O

-

TIMING CHARACTERISTICS (EiA-423-A single-ended mode, Pin 4" 2.0 V, TA = 25"C, VCC = +5.0 V, VEE = -5.0 V,
unless otherwise noted)
Characteristic

Symbol

Output Timing (Figure 5)
Output Rise Time, Cc = 0
Output Fall Time, Cc = 0
Output Rise Time, Cc = 50 pF
Output Fall Time, Cc = 50 pF

tr
tf
tr
tf

Rise Time Coefficient (Figure 16)

Min

-

Crt

-

Propagation Delay Time, Input to Single Ended Output (Figure 5)
Input Low to High, Cc = 0
Input High to Low, Cc = 0

tpDH
tpDL

Skew Timing, Cc = 0 (Figure 5)
ItpDH to tPDLI for Each Driver
Max to Min tpDH Within a Package
Max to Min tPDL Within a Package

tSK4
tSK5
tSK6

Typ

Max

Unit

65
65
3.0
3.0

300
300

ns

-

0.06

-

-

-

100
100

300
300

-

15
2.0
5.0

fiS
fiS/pF
ns

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
7-13

-

-

ns

AM26LS30
Table 1
Inputs

Outputs

Vee

VEE

Mode

A

B

e

D

A

B

e

D

Differential
(EIA-422-A)

+5.0

Gnd

0
0
0
0
0
0

0
1
X
1
0
1

0
0
1
0
0
0

0
0
0
0
0
1

0
1
1
0
1
X

0
1
Z
1
0
1

1
0
Z
0
1
0

1
0
0
1
0
Z

0
1
1
0
1
Z

Single-Ended
(EIA-423-A)

+5.0

-5.0

1
1
1
1
1

0
1
0
0
0

0
0
1
0
0

0
0
0
1
0

0
0
0
0
1

0
1
0
0
0

0
0
1
0
0

0
0
0
1
0

0
0
0
0
1

X

0

X

X

X

X

X

X

Z

Z

Z

Z

Operation

x =Don't Care
Z = High Impedance (Off)

Figure 1_ Differential Output Test

Figure 2_ Single-Ended Output Test

RtJ2

Vin
(0.8 or 2.0 V)
RtJ2

Mode =0

t

r-

Vas
-'-

..1

Va

-=

Figure 3_ Differential Mode Rise/Fail Time and Data Propagation Delay

100

500 pF

t

Vao

I

NOTES:

~: ~~1 :ert~~~~t~~~~~; :~~h ~~~:r~ 50%; Ir. tf, ::; 10 ns.
3. tSK2 computed by subtracting the shortest tpDH from the longest tpDH of the 2 drivers within a package.
4. tSK3 computed by subtracting the shortest tpDl from the longest tpDL of the 2 drivers within a package.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

7-14

AM26LS30
Figure 4. Differential Mode Enable Timing
r -_ _ _ _ _ _ _ _ _ _ _ _ _ _--..+3.OV

1.5V

1.5 V

t

OV

RL VSS

I
(Vin = Hi)

Output
Current

(Vin = 1..0)
NOTES:
1. S.G. set to: f :s; 1.0 MHz; duty

cycle" 50%; tr, tf, S 10 ns.

2. Above tests conducted by momtoring output current levels.

Figure 5. Single-Ended Mode Rise/Fall Time and Data Propagation Delay
, -_ _ _ _ _ _ _ _ _ _ _--. +2.5 V

Vee

FT

500 P

J.-

NOTES:

r,

ns.

~: ~~4 :eft~~~~t~ogS~~r; ~~~ &~~r~ 50%; t tf, S 10
3. tSK5 computed by subtracting the shortest tpDH from the longest tpDH of the 4 drivers within a package.
4. tSK6 computed by subtracting the shortest tpOL from the longest tpOL of the 4 drivers within a package.

MOTOROLA LlNEARIINTERFACE ICs DEVICE DATA

7-15

AM26LS30
Figure 6. Differential Output Voltage
versus Load Current

Figure 7. Internal Bias Current
versus Load Current
40

5.0
~ 4.0
w

'"
1:3

g

-

..........

r-

3.0

>::::>
D..

r-

~ 2.0 Differential Mode
_ , Mode=O, VCC=5.0V
ci

-

l

?

1.0 _ro.80r~T
~V
+101,0
10

a:
a:

::::>

r--_

a

20
30
40
10, OUTPUT CURRENT (rnA)

30

!Z
w

-

....

Differential Mode
Mode=O
I-- Supply Current = Bias Current + load Current

u

en

S

'"o:l

50

20
VCC=5.25V

20

60

Figure 8. Short Circuit Current
versus Output Voltage

100

120

Figure 9. Input Current versus
Input Voltage

+100

+5.0

.1

I

VCC=O

l>-

LL

+60

/

iii
a:

+20

t::
::::>
u

a:

C3 -20

J

~

"

/

en_ -60
u

./

.!!J

-100 0

1.0

f-

::::>

/

~z

Normally High Oulpul

::t:

~

-5.0
a:
a:
u -10

/

b:
a

0

2-

Normally low Oulpul

V

a:

5

5.0

Pins 2 to 4, 6, 7
-5.0V
>::::>
D..

-

>-

::::>

:z:

3.5 , -

r--

?

11

13

15

-3.25

......

'"1:3

5.0
7.0
9.0
Vin, INPUT VOLTAGE (V)

Figure 11. Output Voltage versus
Output Sink Current

4.5

a

40
60
80
TOTAL LOAD CURRENT (rnA)

!--

w

'"t§

~

~~

Single·Ended Mode
Mode = 1
VCC = 5.0 V, VEE = -5.0 V
Vin= 1

T

g

........

.....

~

,., V

a

-I -4.25

?

/

I I I I

3.0
-10

-3.75

-20

-30

-40

-50

-4.75

-60

o

V

10

-

_.......

I

I

.......

.......

---

Single-Ended Mode
Mode = 1
VCC = 5.0 V, VEE = -5.0 V
Vin=O

20

30

L
40

10l, OUTPUT CURRENT (mA)

10H, OUTPUT CURRENT (rnA)

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

7-16

50

-

60

AM26LS30
Figure 12. Internal Positive Bias Current
versus Load Current

Figure 13. Internal Negative Bias Current
versus Load Current
0

26

I- Single Ended Mode

1

Mode = 1
I- VCC = 5.0 V. VEE = -5.0 V
22
Supply Current = Bias Current +IOH

!Z
w
a:
a:
::::>
u

-

/

1-5.0
!Z

r-- .........

-

:$

14

10240

I

a -1 0
~

'".-

/

IE -1

5~
I--

Vin=lo Vln=Hi

160

80

""'0....---

IOl

+r- I -"'-r0

-t60
-240
IOH - - -....1
TOTAL LOAD CURRENT (rnA)

Figure 14. Short Circuit Current
versus Output Voltage
100

110

~
~

I

60

a:

a

!:

~

-20

1

Normally low Output

rn

70

Single-Ended Mode

I

' - Vee = 5.0 V, VEE = -5.0 V
-100
-6.0

II
-4.0

I

1

--

I
r-

I

Normally low Output

I--J.
J
I
I

-40

6.0

o
20
40
60
TA. AMBIENT TEMPERATURE (OC)

Single-Ended Mode
Mode = 1
VCC = 5.0 V, VEE = -5.0 V

/'

~ 100

:l
if

ffi

a:

V

10

1.0
10

,/
100
1.0k
CC. CAPACITANCE (pF)

10 k

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

7-17

--

J

J

-20

Figure 16. Rise/Fall TIme versus Capacitance

a

r--

I

1.0 k

..

-

NJrmallY Hi9hlOutput to Ground

-90

b -100

4.0

T

Figure 15. Short Circuit Current
versus Temperature

!!! -110

-2.0
2.0
Vza. APPUED OUTPUT VOLTAGE M

I

Single·Ended Mode
Mode = 1
VCC = 5.0 V, VEE = -5.0 V
Supply Current = Bias Current +IOl

50

Normally High Output

~ -60 f- Mode=1

T

Single or Differential Mode
VCC = 5.0 V. VEE = -5.0 V or Gnd

IF

/
/

'"

90

+

u

/

~
(3

I

V

20

Vin= lo Vi" -Hi

-20
240
160
80
-80
-160
-240
1""•.-.---IOl
.. ,.
IOH - - -.....1
TOTAL LOAD CURRENT (rnA)

-80

.'0

-

ll!
a:

......... V

18

'"
'"IE..,

I

85

AM26LS30
APPLICATIONS INFORMATION
Description
The AM26LS30 is a dual function line driver - it can be
configured as two differential output drivers which comply with
EIA-422-A Standard, or as four single-ended drivers which
comply with EIA-423-A Standard. The mode of operation is
selected with the Mode pin (Pin 4) and appropriate power
supplies (see Table 1). Each of the four outputs is capable of
sourcing and sinking 60 to 70 mA while providing sufficient
voltage to ensure proper data transmission.
As differential drivers, data rates to 10 Mbaud can be
transmitted over a twisted pair for a distance determined by the
cable characteristics. EIA-422-A Standard provides
guidelines for cable length versus data rate. The advantage of
a differential (balanced) system over a single-ended system is
greater noise immunity, common mode rejection, and higher
data rates.
Where extraneous noise sources are not a problem, the
AM26LS30 may be configured as single-ended drivers
transmitting data rates to 100 Kbaud. Crosstalk among wires
within a cable is controlled by the use of the slew rate control
pins on the AM26LS30.
Mode Selection
(Differential Mode)
In this mode (Pins 4 and 8 at ground), only a +5.0 V supply
±5% is required at VCC. Pins 2 and 7 are the driver inputs,
while Pins 10, 11, 14 and 15 are the outputs (see Block
Diagram on page 1). The two outputs of a driver are always
complementary and the differential voltage available at each
pair of outputs is shown in Figure 6 for VCC = 5.0 V. The
differential output voltage will vary directly with VCC. A "high"
output can only source current, while a "low" output can only
sink current (except for short circuit current - see Figure 8).
The two outputs will be in a high impedance mode when the
respective Enable input (Pin 3 or 6) is high, or if VCC $ 1.1 V.
Output leakage current over a common mode range of ±1 0 V
is typically less than 1.0 /lAo
The outputs have short circuit current limiting, typically, less
than 100 mA over a voltage range of 0 to +6.0 V (see Figure
8). Short circuits should not be allowed to last indefinitely as
the IC may be damaged.
Pins 9, 12, 13, and 16 are normally not used when in this
mode, and should be left open.
(Single-Ended Mode)
In this mode (Pin 4 ~ 2.0 V) VCC requires +5.0 V, and VEE
requires -5.0 V, both ±5%. Pins 2, 3, 6, and 7 are inputs forthe
four drivers, and Pins 15, 14, 11, and 10 (respectively) are the
outputs. The four drivers are independent of each other, and
each output will be at a positive or a negative voltage
depending on its input state, the load current, and the supply
voltage. Figures 10 & 11 indicate the high and low output
voltagesforVcc =5.0V, and VEE =-5.0 V. The graph of Figure
10 will vary directly with VCC, and the graph of Figure 11 will
vary directly with VEE. A "high" output can only source current,
while a "low" output can only sink current (except short circuit
current-see Figure 14).

The outputs will be in a high impedance mode only if VCC
$1.1 V. Changing VEE to 0 V does notsetthe outputs to a high
impedance mode. Leakage current over a common mode
range of ±1 0 V is typically less than 1.0 J.lA.
The outputs have short circuit current limiting, typically, less
than 100 mA over a voltage range of ±G.O V (see Figure 14).
Short circuits should not be allowed to last indefinitely as the
IC may be damaged.
Capacitors connected between Pins 9, 12, 13, and 16 and
their respective outputs will provide slew rate limiting of the
output transition. Figure 16 indicates the required capacitor
value to obtain a desired rise or fall time (measured between
the 10% and 90% points). The positive and negative transition
times will be within = ±5% of each other. Each output may be
set to a different slew rate if desired.

Inputs
The five inputs determine the state of the outputs in
accordance with Table 1. All inputs (regardless of the
operating mode) have a nominal threshold of + 1.3 V, and their
voltage must be kept within the range of 0 Vto + 15 V for proper
operation. If an input is taken more than 0.3 V below ground,
excessive currents will flow, and the proper operation of the
drivers will be affected. An open pin is equivalent to a logic
high, but good design practices dictate that inputs should
never be left open. Unused inputs should be connected to
ground. The characteristics of the inputs are shown in Figure

9.

Power Supplies
VCC requires +5.0 V, ±5%, regardless of the mode of
operation. The supply current is determined by the IC's
internal bias requirements, and the total load current. The
internally required current is a function of the load current and
is shown in Figure 7 for the differential mode.
In the single-ended mode, VEE must be-5.0 V, ±5% in order
to comply with EIA-423-A StandardS. Figures 12 and 13
indicate the internally required bias currents as a function of
total load current (the sum of the four output loads). The
discontinuity at 0 load current exists due to a change in bias
current when the inputs are switched. The supply currents
vary=±2.0 mAas VccandVEE are varied from 14.75 VI to 15.25
VI·
Sequencing of the supplies during power-up/power-down is
not required.
Bypass capacitors (0.1 J.lF minimum on each supply pin) are
recommended to ensure proper operation. Capacitors reduce
noise induced onto the supply lines by the switching action of
the drivers, particularly where long P.C. board tracks are
involved. Additionally, the capacitors help absorb transients
induced onto the drivers' outputs from the external cable (from
ESD, motor noise, nearby computers, etc.).

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

7-18

AM26L530
Operating Temperature Range
The maximum ambient operating temperature, listed as
+85°C, is actually a function of the system use (I.e., specifically
how many drivers within a package are used) and at what
current levels they are operating. The maximum power which
may be dissipated within the package is determined by:
PDmax=

The junction temperature calculates to:
TJ = 85°C + (0.454 W • 67°CIW) = 115°C for the
DIP package,
TJ = 85°C + (0.454 W • 120°CIW) = 139°C for the
SOIC package.
Since the maximum allowable junction temperature is not
exceeded in any of the above cases, either package can be
used in this application.

TJmax-TA
RaJA

2) Single-Ended Mode Power Dissipation
For the single-ended mode, the power dissipated within the
package is calculated from:

where RaJA = package thermal resistance which is typically:
67°CIW for the DIP (PC) package,
120°CIW for the SOIC (D) package,
TJmax = max. allowable junction temperature (150°C)
TA = ambient air temperature near the IC package.

PD = (18+ • VCC) + (Is-. VEE) +
[(10 • (VCC - VOH)](each driver)
The above equation assumes 10 has the same magnitude
for both output states, and makes use of the fact that the
absolute value of the graphs of Figures 10 and 11 are nearly
identical. 18+ and Is-are obtained from the right half of Figures
12and 13, and (VCC-VOH) can be obtained from Figure 10.
Note that the term (VCC - VOH) is constantfor agiven value of
10 and does not vary with VCC. Foran application involving the
following conditions:
TA=+85°C,10=-60mA(eachdriver), VCC=5.25V, VEE =
-5.25 V, the suitability of the package types is calculated as
follows.
The power dissipated is:
PD = (24 rnA • 5.25 V) + (-3.0 rnA • -5.25 V) +
[60 rnA • 1.45 V • 4.0]
PD=490mW
The junction temperature calculates to:
TJ = 85°C + (0.490 W. 67°CIW) = 118°C for the
DIP package,
TJ = 85°C + (0.490 W • 120°CIW) = 144°C for the
SOIC package.
Since the maximum allowable junction temperature is not
exceeded in any of the above cases, either package can be
used in this application.

1) Differential Mode Power Dissipation
For the differential mode, the power dissipated within the
package is calculated from:
PD = [(VCC - VOD) • 10](each driver) + (VCC· 18)
where: VCC = the supply voltage
VOD = is taken from Figure 6 for the known
value of 10
18 = the internal bias current (Figure 7)
As indicated in the equation, the first term (in brackets) must
be calculated and summed for each of the two drivers, while
the last term is common to the entire package. Note that the
term (VCC- VOD) is constantfor a given value of 10 and does
not vary with VCC. For an application involving the following
conditions:
TA = +85°C, 10 = -60 rnA (each driver), VCC = 5.25 V,
the suitability of the package types is calculated as follows.
The power dissipated is:
PD = [3.0 V. 60 rnA. 2] + (5.25 V • 18 rnA)
PD =454 mW

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
7-19

AM26LS30
SYSTEM EXAMPLES
Differential System
An example of a typical EIA-422-A system is shown in
Figure 17. Although EIA-422-A does not specifically address
multiple driver situations, the AM26LS30 can be used in this
manner since the outputs can be put into a high impedance
mode. It is, however, the system designer's responsibility to
ensure the Enable pins are properly controlled so as to prevent
two drivers on the same cable from being "on" at the same
time.
The limit on the number of receivers and drivers which may
be connected on one system is determined by the input
current of each receiver, the maximum leakage current of each
"off" driver, and the DC current through each terminating
resistor. The sum of these currents must not exceed the
capability of the "on" driver (~60 mAl. If the cable is of any
significant length, with receivers at various points along its
length, the common mode voltage may vary along its length,
and this parameter must be considered when calculating the
maximum driver current.
The cable requirements are defined not only by the AC
characteristics and the data rate, but also by the DC
resistance. The maximum resistance must be such that the
minimum voltage across any receiver inputs is never less than
200mV.
The ground terminals of each driver and receiver in Figure
17 must be connected together by a dedicated wire (or the
shield) in the cable so as to provide a common reference.
Chassis grounds or power line grounds should not be relied on
for this common connection as they may generate significant
common mode differences. Additionally, they usually do not
provide a sufficiently low impedance at the frequencies of
interest.
Single-Ended System
An example of a typical EIA-423-A system is shown in
Figure 18. Multiple drivers on a single data line are not possible
since the drivers cannot be put into a high impedance mode.
Although each driver is shown connected to a single receiver,
multiple receivers can be driven from a single driver as long
as the total load current of the receivers and the terminating
resistor does not exceed the capability of the driver (~60 mAl.
I! the cable is of any significant length, with receivers at various
points along its length, the common mode voltage may vary
along its length, and this parameter must be considered when
calculating the maximum driver current.
The cable requirements are defined not only by the AC
characteristics and the data rate, but also by the DC
resistance. The maximum resistance must be such that the

minimum voltage across any receiver inputs is never less than
200mV.
The ground terminals of each driver and receiver in Figure
18 must be connected together by a dedicated wire (or the
shield) in the cable so as to provide a common reference.
Chassis grounds or power line grounds should not be relied on
for this common connection as they may generate significant
common mode differences. Additionally, they usually do not
provide a sufficiently low impedance at the frequencies of
interest.
Additional Modes of Operation
If compliance with EIA-422-A or EIA-423-A Standard is not
required in a particular application, the AM26LS30 can be
operated in two other modes.
1) The device may be operated in the differential mode (Pin
4 = 0) with VEE connected to any voltage between ground and
-5.25 V. Outputs in the low state will be referenced to VEE,
resutting in a differential output voltage greater than that
shown in Figure 6. The Enable pins will operate the same as
previously described.
2) The device may be operated in the single-ended mode
(Pin 4= 1) with VEE connected to any voltage between ground
and -5.25 V. Outputs in the high state will be at a voltage as
shown in Figure 10, while outputs in a low state will be
referenced to VEE.
Termination Resistors
Transmission line theory states that, in order to preserve the
shape and integrity of a waveform traveling along a cable, the
cable must be terminated in an Impedance equal to its
characteristic impedance. In a system such as that depicted
in Figure 17, in which data can travel in both directions, both
physical ends of the cable must be terminated. Stubs leading
to each receiver and driver should be as short as possible.
In a system such as that depicted in Figure 18, in which data
normally travels in one direction only, a terminator is
theoretically required only at the receiving end of the cable.
However, if the cable is in a location where noise spikes of
several volts can be induced onto it, then a terminator
(preferably a series resistor) should be placed at the driver end
to prevent damage to the driver.
Leaving off the terminations will generally result in
reflections which can have amplitudes of several votts above
VCC or several volts below ground or VEE. These
overshoots/undershoots can disrupt the driver and/or
receiver, create false data, and in some cases, damage
components on the bus.

MOTOROLA LlNEARIINTERFACE ICs DEVICE DATA

7-20

AM26LS30
Figure 17. EIA·422·A Example

TTL

TTL

TIL

TIL

TTL

TIL

TTL
Twisted

Pair

TTL

NOTES:

1.
2.
3.
4.

Terminating resistors Rr should be located at the physical ends of the cable.
Stubs should be as short as possible.
Receivers = AM26LS32, MC3486, MC7S173 or MC7S17S.
Circuit grounds must be connected together through a dedicated wire.

Figure 18. EIA-423·A Example

TTL

TTL

TTL

TTL

AM26LS30

AM26LS32, MC3486, MC75173, or MC75175

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

7-21

MOTOROLA

-

AM26LS31

SEMICONDUCTOR - - - - - -

TECHNICAL DATA

QUAD LINE DRIVER WITH NAND ENABLED
THREE-STATE OUTPUTS

QUAD EIA-422 LINE DRIVER
WITH THREE-STATE OUTPUTS
SILICON MONOLITHIC
INTEGRATED CIRCUIT

The Motorola AM26LS31 is a quad differential line driver
intended for digital data transmission over balanced lines. It meets
all the requirements of EIA-422 Standard and Federal Standard
1020.
The AM26LS31 provides an enable/disable function common
to all four drivers as opposed to the split enables on the MC3487
EIA-422 driver.
The high impedance output state is assured during power
down.

DC SUFFIX
CERAMIC PACKAGE
CASE 620

• Full EIA-422 Standard Compliance
• Single

+ 5.0 V Supply

• Meets Full Vo = 6.0 V, VCC = 0 V, 10 < 100 /LA Requirement
• Output Short Circuit Protection
• Complementary Outputs for Balanced Line Operation

D SUFFIX
PLASTIC PACKAGE
CASE 751B
ISO-16)

• High Output Drive Capability
• Advanced LS Processing
• PNP Inputs for MOS Compatibility

PC SUFFIX
PLASTIC PACKAGE
CASE G48

PIN CONNECTIONS
DRIVER BLOCK DIAGRAM

Input

Outputs

Inverting
Enable
Output

Controls

TRUTH TABLE
Control

Input

Inputs

Non-Inverting
Output

Inverting
Output

H
L
Z

L
H
Z

ORDERING INFORMATION

(E/E)
H
L
X

H/L
HIL
LIH

Temperature

Device
AM26LS31PC

L = Low Logic State

X

H = High Logic State

Z = Third-State (High Impedance)

=:

Range

Irrelevant

MC26LS31D*

*Note that the surface mount MC26LS31 D devices use the same die as in the ceramic and plastic
DIP AM26LS31 DC devices, but with an Me prefix to prevent confusion with the package suffixes.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

7-22

Package
Ceramic DIP

AM26LS31DC

o to 70°C

Plastic DIP
SO-16

AM26LS31

MAXIMUM RATINGS
Rating

Symbol

Value

Unit

VCC

8.0

Vdc

Input Voltage

VI

5.5

Vdc

Operating Ambient Temperature Range

TA

o to +70

'c

Operating Junction Temperature Range
Ceramic Package
Plastic Package

TJ

Power Supply Voltage

Storage Temperature Range

'C
175
150

Tst 2.7 VI
IIQ = 8.0 mAo VOL'" 0.45 VI

-

Input Bias Current

IVCC

-

0.2
-0.2
mA

IIBIDI

= 0 V or 5.251 10ther Inputs at
Vin = + 15 V
Vin = -15 V

Input Aesistance f

V

VTHIDI

- 15 V .; Vin .; + 15VI

-

15V.; Vin .; + 15 VI

Rin

6.0 K

VOH
VOL
10Z

2.7

-

-

2.3
-2.8

-

Input Balance and Output Level

1-7.0V '" VIC'; 7.0V. VIH = 2.OV.
See Note 31
110 =-0.4 mA, V ID =0.4 VI
110 =8.0 mAo VID =-0.4 VI

Output Third State leakage Current
IVIIDI = + 3.0 V, VIL = 0.8 V. Vo
IVIIDI

= - 3.0 V. Vll = 0.8 V, Vo

Output Short Circuit Current
(VIIDI = 3.0 V. VIH = 2.0 V. Vo
See Note 41

-

= 0.4 VI
= 2.4 VI

-

-

-

0.45
-20
20
-85

mA

"A

"A

lOS

-15

-

III

-

-

-360

-

-

20
100

-

Ohms
V

= 0 V.

Input Current - Low Logic State

IThree·State Control)
IVll =0.4 V)

Input Current
High logic State
(Three' State Control)
IVIH = 2.7 VI
IVIH = 5.5 VI
Input Clamp Diode Voltage
(Three-State Control)

IIH

IIIC = -18mAI
Power Supply Current
IVll = 0 VI IAlllnputs Groundedl

"A

VIK

-

-

-1.5

ICC

-

-

70

V

mA

NOTES:
1. All currents into device pins are shown as positive. out of device pins are negative. All voltages referenced to ground unless otherwise noted.
2. Differential input threshold voltage and guaranteed output levels are done simultaneously for worst case.
3. Refer to EIA·422/3 for exact conditions. Input balance and guaranteed output levels are done simultaneously for worst case.
4. Only one output at a time should be shorted.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

7-26

AM26LS32

SWITCHING CHARACTERISTICS IUnless otherwise noted, VCC = 5.0 V and TA = 25°CI
Symbol

Characteristic
Propagation Delay Time -

Typ

Min

Unit

Max

ns

Differential

Inputs to Output
10utput High to Lowl
10utput Low to Highl
Propagation Delay Time - Three-State

-

tpHLIDI
tpLHIDI

-

30
30

-

ns

Control to Output
(Output Low to Third State)

tPL2

!Output High to Third State)
(Output Third State to High)

tPHZ
tpZH

(Output Third State to Low)

tpZL

-

-

35
35
30
30

-

SWITCHING TEST CIRCUIT AND WAVE FOR
FIGURE 1 - PROPAGATION DELAY DIFFERENTIAL INPUT TO OUTPUT
To Scope

To Scope

ilnpuO

(Output)

t

J
Gene,ato~

M"

+2.5Vln~F\ov

tP2L:~DI~~J.
--"-:~--. ~~J-~- tpHLIDI
CL

15 pF

VOH

!Includes Probe
and Stray

"'

2.0 V

j

-

t;

13V
1.3 V
OV-----------

Capacitance}

OV

-

VOL Output

Input Pulse Characteristics

3-State Control

tTLH

tTHL

PRR

1.0 MHz, 50% Duty Cycle

6.0 ns (10% to 90%)

FIGURE 2 - PROPAGATION DELAY THREE-STATE CONTROL INPUT TO OUTPUT
To Scope

Input Pulse Charactenstics

tTLH
PRR

(Inpull

tTHL
6.0 ns 110% to 90%)
1.0 MHz, 5O ult) Duty Cycle

3 State
Control

To Scope
(Output!

Pulse
Generator

SWI

2.0 k

+ 5.0 V

+ 1,5 V for tpHZ and tpZH
1.5 V for tpLZ and tpZL
Inputs

CL

15 pF

(Includes

I

All Diodes 1 N916 or
Equivalent

5.0 k

Probe and Stray -=Capacitance)

YSW2

(nput

3'0v~tPHZ

3'0v~tPLZ
o V--·

1.5 V

- r

-1.5 V

Input

tpLZ

oV

SWI Closed
SW2 Closed

OutPu~ lV30~ ~

VOH

OutP~tl.3 V

---1- -----

30V
oV

tpZH

5V

~
~tP~:2

3.0 V
I

SW10pen

- -

---,J-L 0.5 V r-_____
~
tpZL

~5V
SW1CIosed

nput 0 V _ _ .

Closed

SW2 Open

PZL

~

=5.0V - V B E - -

VOH
Output

SW2 Closed
tpHZ

---------OV

0V

Input

r;-

SWl Closed

Output

15 V

1.5 V

VOL

OV - - -

--------OV

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

7-27

MOTOROLA

-

MC8T26A

SEMICONDUCTOR - - - - - -

(MC6880A)

TECHNICAL DATA

QUAD THREE-STATE
BUS TRANSCEIVER

QUAD THREE-STATE BUS TRANSCEIVER
This quad three-state bus transceiver features both excellent MOS
or MPU compatibility, due to its high impedance PNP transistor
input, and high-speed operation made possible by the use of Schottky
diode clamping. Both the -48 rnA driver and -20 rnA receiver outputs are short-circuit protected and employ three-state enabling inputs.
The device is useful as a bus extender in systems employing the
M6800 family or other comparable MPU devices. The max imum
input current of 200 IlA at any of the device input pins assures
proper operation despite the limited drive capability of the MPU
chip. The inputs are also protected with Schottky-barrier diode
clamps to suppress excessive undershoot voltages.
The MC8T26A is identical to the NE8T26A and it operates from
a single +5 V supply.
•

High Impedance Inputs

•

Single Power Supply

•

High Speed Schottky Technology

•

Three-State Orivers and Receivers

•

Compatible with M6800 Family Microprocessor

MONOLITHIC SCHOTTKY
INTEGRATED CIRCUITS

L SUFFIX

CERAMIC PACKAGE
CASE 620

,

P SUFFIX

PLASTIC PACKAGE
CASE 648

PIN CONNECTIONS -

MICROPROCESSOR BUS EXTENDER APPLICATION
(Clock)
GND +5 $1 $2

MC8T26A
(MC6880A)

Receiver
Enable
Input

Vee

Receiver

,

Output

Driver
Enable
Input

2

14 Receiver
Output

4
8us 4
Driver
Input

4
Receiver
Output

3
Bus 3

Gnd

ORDERING INFORMATION
Temperature

Device

Alternate

MC8T26AL MC6880AL
MC8T26AP MC6880AP

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
7-28

Range

o to

+75°C

Package

Ceramic DIP
Plastic DIP

MC8T26A

MAXIMUM RATINGS ITA

= 25°C unless otherwise noted.)

Symbol

Value

Unit

Vcc

B.O

Vdc

Input Voltage

VI

5.5

Vdc

Junction Temperature

TJ

Rating
Power Supply Voltage

Ceramic Package
Plastic Package

°c
175
150

Operating Ambient Temperature Range

TA

o to +75

Storage Temperature Range

T stg

-65 to+150

°c
C

ELECTRICAL CHARACTERISTICS 14.75 V .; VCC';; 5.25 V and OOC .. TA .;; 75 0 C unless otherwise noted.)
Characteristic

Symbol

Min

Typ

IIL!REI
IILlDE)
IILlDI
IILlBI

-

-

-

Max

Unit

-200
-200
-200

"A

-

-

-

-200

-

-

-25

"A

IIHlRE)
IIHIDEI
IIHID)
IIHIB)

-

-

25
25
25

"A

100

(Driver Enable Input
(Driver Input)

VILlRE)
VILIDEI
VILIDI

-

-

0.85
0.85
0.85

(Receiver Input)

VI LIB)

-

-

0.85

VIHlREI
VIHIDEI
VIHID)
VIHIB)

2.0
2.0
2.0
2.0

-

-

vOLlB)
VOLIRI

-

-

0.5
0.5

V

VOHIBI
VOHIR)

2.4
2.4
3.5

3.1
3.1

V

-

-

IOHLIBI
IOHLIRI

-

-

100
100

pA

IOLLlB)
IOLL(RI

-

-

-

-100
-100

"A

-

VICIDEI
VICIRE}
VICID)

-

-

-1.0
-1.0
-1.0

V

10SIB)
IOSIR)

-50
-30

-150
-75

mA

ICC

-

87

rnA

Input Current

~

Low Logic State

(Receiver Enable Input, VIL(REI '" 0.4 V)

IDriver Enable Input. VI LIDE) = 0.4 VI
(Driver Input, VIL(O)

= 0.4

V)

(Bus (Receiver) Input, VIL(S)

=

0.4 V)

Input Disabled Current - Low Logic State

-

IILlD) DIS

IDriver Input. VILlD) = 0.4 V)
Input Current-High Logic State
(Receiver Enable Input, VIH(RE) = 5.25 V)
(Driver Enable Input, VI H(DE).'" 5.25 V)

IDriver Input. VIHID) = 5.25 V)
IReceiver Input. VIHIB) = 5.25 V)
Input Voltage - Low Logic State
(Receiver Enable Input)

Input Voltage - High Logic State
(Receiver Enable Input)
(Driver Enable Input)
(Driver Input)
(Receiver Input)

V

V

-

Output Voltage - Low Logic State

IBus Driver! Output, 'OL(B) = 48 rnA)
IReceiver Output. IOLIR) = 20 mAl
Output Voltage - High Logic State

IBus IDriver! Output, IOHIB) = -10 rnA)
IReceiver Output. IOHIR) = -2.0 mAl
IReceiver Output. IOHIR) = -100 "A, VCC = 5.0 V)
Output Disabled Leakage Current - High Logic State

IBus Driver! Output, VOHIB) = 2.4 V)
IReceiver Dutput. VOHIR) = 2.4 V)
Output Disabled Leakage Current - Low Logic State

IBus Output, VOL(B) = 0.5 V)
(Receiver Output. VOL(R) = 0.5 V)
Input Clamp Voltage
(Driver Enable Input IID(OE) = -12 mAl
IReceiver Enable Input IICIRE) = +12 mAl
IDriver Input IIC(D) = -12 rnA)

Output Short Circuit Current. VCC
(Bus (Driver) Output)
(Receiver Output)

~

-

5.25 V, Note 1

Power Supply Current

(VCC = 5.25 V)
Note 1. Only one output may be short-Circuited at a time.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

7-29

-

MC8T26A

SWITCHING CHARACTERISTICS (Unless otherwise noted, specifications apply at T A = 25°C and VCC = 5.0 V)
Symbol

Figure

Min

Max

Unit

Propagation Delay Time from Receiver (Bus) Input to
High Logic State Receiver Output

tPLH(R)

1

-

14

ns

Propagation Delay Time from Receiver (Bus) Input to
Low Logic State Receiver Output

tPHL(R)

1

14

ns

Propagation Delay Time from Driver Input to

tPLH(O)

2

-

14

ns

tPHL(O)

2

-

14

ns

Propagation Delay Time from Receiver Enable Input to
High Impedance (Open) Logic State Receiver Output

tpLZ(RE)

3

-

15

ns

Propagation Delay Time from Receiver Enable Input to
Low Logic Level Receiver Output

tPZL(RE)

3

-

20

ns

Propagation Oelay Time from Driver Enable Input to
High Impedance Logic State Driver (8us) Output

tPLZ(DE)

4

-

20

ns

Propagation Delay Time from Driver Enable Input to
Low Logic State Driver (Bus) Output

tPZL(OE)

4

-

25

ns

Characteristic

High Logic State Driver (Bus) Output
Propagation Delay Time from Driver Input to
Low Logic State Driver (Bus) Output

FIGURE 1 - TEST CIRCUIT AND WAVEFORMS FOR PROPAGATION DELAY FROM
BUS (RECEIVER) INPUT TO RECEIVER OUTPUT, tpLH(R) AND tpHL(R)

tTl.H

~

5.0 ns

tTHL'" 5.0 ns

Input

ov--'-="'"

Input Pulse Frequency = 10 MHz
Duty eye Ie = 50"4

tpHL(Rl
VOH---Output
VOL----------·~--------J

To Scope
(Input)

~r

2.6 V

To Scope
( Input)

En;bi;
Input

92
Receiver

1N916

Output

or Equiv.

Driver
Input
Pulse

Generator

51

1.3 k

30 pF

Driver
Enable
Input

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
7-30

MC8T26A
FIGURE 2 - TEST CIRCUIT AND WAVEFORMS FOR PROPAGATION DELAY TIME FROM
DRIVER INPUT TO BUS (DRIVERI OUTPUT. tpLH(DI AND 'PHL(DI

tTHL

<

B.O nl

2.6 v-----I.,j==----~=i.
Input

OV----'-''"''-'''l

Input Pull8 Frequency ... 10 MHz
Duty Cycle - 50%

'PHL(O)
VOH----Output

VOL-----------~-------J

2.6 V

To Scope

Driver
Input

2.6 V

To Scope

Driver
Enable
Input

(lnpu')

(Output)

30

Driver
(Bus)

lN916

Output

or Equiv.

Receiver

Output

51

300pF

260

fi'8c8iV8r
Enable
Input

FIGURE 3 - TEST CIRCUIT AND WAVEFORMS FOR PROPAGATION DELAY TIME FROM
RECEIVER ENABLE INPUT TO RECEIVER OUTPUT.IPLZ(REI AND 'PZL(REI

tTLH

< 5.0"s

tTHL'" 5.0 ns

2.6 V ---h~::::-----::::::;-:oL.
Input

OV

r-

'PLZ(RE)
"'3.5 V -----t--::,.-------~.

'PZL(M)

1.5 V

Output

Input Pul. Frequency = 5.0 MHz
Duty Cycle = 50%

VOL-----......;J

To Scope
(Input)

2.6 V

To Scope
(Outpu')

R"8Cii'V8r "Enable
Input

5.0 V

2.4 k

Receiver

240

Output

Pul.

51

Generator

lN916
5.0 k

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
7-31

30pF

or Equlv.

MC8T26A

FIGURE 4 - TEST CIRCUIT AND WAVEFORMS FOR PROPAGATION DELAY TIMES FROM
DRIVER ENABLE INPUT TO DRIVER (BUS) OUTPUT:tPLZ(DE) AND tpZL(DE)

tTLH

<:

5.0

2.6 V

tTHL:SO; 5.0 ns

n$

---+-fi:;;;;:-----........

Input

Input Pulse Frequency;:: 5.0 MHz
Duty Cycle = 50%

OV----,,"I

tpZL(DE)
~3.5V-----

Output

VOL------'-------~

+2.6 V

To Scope
Driver Enable

5.0 V

(Output)

Input

2.4 k

Driver
Input

Pulse

51

Generator

70

Driver (Bus)
Output

Receiver
Output

300pF

5.0 k

~

lN916
or Equiv.

Enaiiie
Input

FIGURE 5 - BIDIRECTIONAL BUS APPLICATIONS

Receiver
Outputs

Receiver

Outputs

Orlver
Inputs

Driver
Inputs

To Other
Drivers/Receivers

Driver
Enable

Receiver

E'Nibie

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
7-32

MOTOROLA

SEMICONDUCTOR-----TECHNICAL DATA

HEX THREE-STATE BUFFER INVERTERS
This series of devices combines three features usually found desirable in
bus-oriented systems: 1) High impedance logic inputs insure that these
devices do not seriously load the bus; 2) Three-state logic configuration
allows buffers not being utilized to be effectively removed from the bus; 3)
Schottky technology allows high-speed operation.
The noninverting MC8T97/MC6887 and inverting MC&t98/MC6888
provide two Enable inputs - one controlling four buffers and the other
controlling the remaining two buffers.
The units are well-suited for Address buffers on the MC6800 or similar
microprocessor application.
• High Speed - 8.0 ns (Typ)
• Three-State Logic Configuration
• Single +5 V Power Supply Requirement
• Compatible with 74LS Logic or MC6800 Microprocessor Systems
• High Impedance PNP Inputs Assure Minimal Loading of the Bus

MC8T97
MC8T98

(MC6SS7)
(MC6SSS)

HEX THREE-STATE
BUFFER/INVERTERS
MONOLITH SCHOTTSKV
INTEGRATED CIRCUITS

LSUFFIX

PSUFFIX

CERAMIC PACKAGE
CASE 620

PLASTIC PACKAGE
CASE 648

INPUT EaUIVALENT CIRCUIT
VCC

MICROPROCESSOR BUS EXTENDER APPLICATION
IClock)
GND +5 .pI .p2

OUTPUT EaUIVALENT CIRCUIT

ORDERING INFORMATION

(Temperature Range = 0 to + 7S"C)
Device
MC8T97L
MC8T9BL
MC8T97P
MC8T98P

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
7-33

Alternate
MC6887L
MC6888L
MC6887P
MC6688P

Package
Ceramic DIP
Ceramic DIP
Plastic DIP
Plastic DIP

MC8T97, MC8T98

MAXIMUM RATINGS (TA = 25°C unless otherwise noted)
Rating
Symbol
Power Supply Voltage
Vrr
Input Voltage

VI

Operating Ambient Temperature Range

TA
T sto

Storage Temperature Range
Operating Junction Temperature
Plastic Package
Ceramic Package

Value

Unit

8.0
5.5
o to +75
-65 to +150

Vdc
Vdc

°c
°c
°c

TJ

150
175

MC8T981MC6888

MC8T97/MC6887

Vee

Eri'8bi8 4

Output A

Enable 2

Input A

Input F

Output A

Output F

Input E

OutPut B

Output E

Input C

Input 0

Output C

Output 0

Gnd

Enable
L
L

H

Input

Output

L

L

H
X

H
Z

L "" Low LogIc State
H = HIgh Logic State
Z .,. Third (High Impedance) State
X

= Irrelevant

Enable

Output

L

H

H

L
Z

H

X

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
7-34

Input

L
L

MC8T97, MC8T98
ELECTRICAL CHARACTERISTICS (Unless otherwise noted, ooe S TA S 75°e and 4.75 V S Vee S 5.25 V)
Characteristics

Symbol

Min

VIH
VIL

2.0

Input CurrentHigh Logic State (VCC = 5.25 V, VIH = 2.4 V)
_
Low Logic State (VCC = 5.25 V, VIL = 0.5 V, VIL(E) = O.~ V)
High Impedance State (VCC = 5.25 V, VIL = 0.5 V, VIH(E) = 2.0 V)

IIH
IlL
IIH(E)

-

Output Voltage
High Logic State (VCC = 4.75 V, 10H = -5.2 mAl
Low Logic State (lOL = 48 mAl

VOH
VOL

2.4

Input Voltage
High Logic State (VCC = 4.75 V, TA = 25°C)
Low Logic State (VCC = 4.75 V, TA = 25°C)

Output Voltage - High Impedance State
(VCC = 5.25 V, VOH = 2.4 V)
(VCC = 5.25 V, VOL = 0.5 V)

10Z

Output Short Circuit Current
(VCC = 5.25 V, Vo = 0, only one output can be shorted at a time)

lOS

Power Supply Current
MC8T97, MC6887
(Vce = 5.25 V)
MC8T98, MC6888

ICC

Input Clamp Voltage
(VCC = 4.75 V, IIC = -12 mAl

VIC

-

-

Output Gnd Clamp Voltage
(VCC = 0, 10C = 12 rnA)

VOC

0.8
40
-400
-40

-

0.5

-

40
-40

-80

-115

65
59

98
89

V

I1A

V

-

I1A

V

5.5
VOC

-

Unit

mA

-

VI

Output VCC Clamp Voltage
(VCC = 0, 10C = 12 rnA)

Max

mA
-40

Input Voltage
(11= 1.0 rnA)

Typ

-

-

-

-1.5

-

-

V
V

1.5
-1.5

SWITCHING CHARACTERISTICS (Vee = 5.0 V, TA = 25°e unless otherwise noted.)
MC8T97
MC6887
Characteristic
Propagation Delay TIme (CL= 50 pF)
(CL= 250 pF)
(CL = 375 pF)
(CL= 500 pF)

High-to-Low State

Propagation Delay TIme (CL= 50 pF)
(CL= 250 pF)
(CL = 375 pF)
(CL= 500 pF)

Low-to-High State

Symbol

Min

Typ

Max

Min

3.0

-

12

4.0

-

16
20
23

3.0

-25

tpHL

-

tPLH

-

--

Transition TIme (CL = 250 pF)
(CL= 375 pF)
(CL= 500 pF)

High-to-Low State

Transition TIme (CL = 250 pF)
(CL =375 pF)
(CL = 500 pF)

Low-to-High State

lTHL

lTLH

Propagation Delay TIme (CL = 5.0 pF)

High State-to-Third State

Propagation Delay TIme (CL = 5.0 pF)

Low State-to-Third State

tPLZ(E)

Propagation Delay TIme - Third State-to-High State
(CL = 50 pF)

tPZH(E)

Propagation Delay TIme - Third State-to-Low State
(CL = 50 pF)

tPZL(E)

tpHZ(E)

MCBT98
MC6888

33
42

-

10
11
14

--

-

-

--

13

3.0

--

15
18
22

-22

-

--

-

-

10
13
15

28
35

Max

Unit
ns

11

-

ns
10

--

ns

-

--

32
42
60

--

-

-

28
38
53

--

-

-

10

-

-

10

-

-

12

-

-

16

25

-

-

22

-

-

25

-

-

24

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
7-35

Typ

ns

ns

ns

MC8T97, MC8T98

FIGURE 2 - WAVEFORMS FOR PROPAGATION DELAY
TIMES INPUT TO OUTPUT

FIGURE 1 - TEST CIRCUIT FOR SWITCHING CHARACTERISTICS

,..----""----- 3 V

To Scope

To Scope (Input)

Output

Open for

Input or

tpZH(e) Test Only

'----OV

+5 V

Enable

~

200

Output

MCBT9B or MC6BBB

'N3064

50

or Equivalent
Output

MCBT97 or MC6BB7
Open for
CL Includes Probe and

Input Pulse Conditions

tPZLfE) Test Only

tTH L = tTLH "
f = 1.O"MHz

Jig Capacitance

FIGURE 3 - WAVEFORMS FOR PROPAGATION DELAY TIMES -

3.0 V

~V
tpZL(E)

tPHZIE)iL

f·sv

Enable

0

3.0 V

tPLZ(E)

Output

VOL

L

H"" High-Logic State, L.

0

X,·5V

'''/~:::"
~

VOL

---l I

0

0.5V

Output

Enable

\:.5V

<;'.5 V

Enable

E1iIAm:E TO OUTPUT

~

VOH
Output

10 ns

3.0 V

tpZH(E)

---I

1/=
!,.5V

= Low-Logic State. Z

"" High Impedance State

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
7-36

Enable

\1.5 V
0

VOH
Output

MC1411,B
MC1412,B
MC1413,B
MC1416,B

MOTOROLA

_ SEMICONDUCTOR - - - - - TECHNICAL DATA

HIGH VOLTAGE, HIGH CURRENT
DARLINGTON TRANSISTOR ARRAYS

PERIPHERAL
DRIVER ARRAYS

The seven NPN Darlington connected transistors in these arrays
are well suited for driving lamps, relays, or printer hammers in a
variety of industrial and consumer applications. Their high breakdown voltage and internal suppression diodes insure freedom
from problems associated with inductive loads. Peak inrush currents to 600 mA permit them to drive incandescent lamps.
The MC1411,B device is a general purpose array for use with
DTl, TTL, PMOS, or CMOS logic. The MC1412,B contains a zener
diode and resistor in series with the input to limit input current
for use with 14 to 25 Volt PMOS logic. The MC1413,B with a 2.7
kO series input resistor is well suited for systems utilizing a 5 Volt
TTL or CMOS logic. The MC1416,B uses a series 10.5 kO resistor
and is useful in 8 to 18 Volt MOS systems.

SIUCON MONOUTHIC
INTEGRATED CIRCUITS

,,ryrn
¥¥~ ~

P SUFFIX

PLASTIC PACKAGE
CASE 648

MAXIMUM RATINGS (TA ~ 25'C and rating apply to anyone device in the
package unless otherwise noted.)
Rating

Symbol

Value

Unit
V

Output Voltage

Va

50

Input Voltage (Except MC1411)

VI

30

V

Collector Current - Continuous

IC

500

mA

IB

25

mA

Base Current -

Continuous

Operating Ambient Temperature Range
MC1411-16
MC1411B-16B

'c

TA
-20 to +85
-40 to +85
Tst!l

-55 to +150

Junction Temperature

TJ

150

Thermal Resistance - Junction-to-Ambient
Case 648, P Suffix
Case 751B, D Suffix

8JA

Storage Temperature Range

PIN CONNECTIONS

'c
'c
'C/W

67
100

ORDERING INFORMATION
Plastic DIP

SOIC

D SUFFIX
PLASTIC PACKAGE
CASE 751B
(50-16)

Ambient
Temperature Range

MC1411P (ULN2001A)
MC1412P (ULN2002A)
MC1413P (ULN2003A)
MC1416P (ULN2004A)

MC1411D
MC1412D
MC1413D
MC1416D

- 20' to + 85'C

MC1411BP
MC1412BP
MC1413BP
MC1416BP

MC1411BD
MC1412BD
MC1413BD
MC1416BD

_40' to +85'C

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
7-37

MC1411,8, MC1412,8, MC1413,B,'MC1416,8

ELECTRICAL CHARACTERISTICS (TA ~ 25'C unless otherwise noted)
Symbol

Characteristic
Output Leakage Current
(VO ~ 50 V, TA ~ +85'C)
(VO ~ 50 V, TA ~ + 25'C)
(VO ~ 50 V, TA ~ + 85'C, VI ~ 6.0 V)
(VO ~ 50 V, TA ~ + 85'C, VI ~ 1.0 V)

All Types
All Types
MC1412,B
MC1416,B

Collector-Emitter Saturation Voltage
(lc ~ 350 rnA, IB ~ 500 /LA)
(lc ~ 200 rnA, IB ~ 350 /LA)
(lC ~ 100 rnA, IB ~ 250/LA)

All Types
All Types
All Types

ICEX

VCE(sat)

Input Current - On Condition
(VI ~ 17 V)
(VI ~ 3.85 V)
(VI ~ 5.0 V)
(VI ~ 12V)

MC1412,B
MC1413,B
MC1416,B
MC1416,B

Input Voltage
(VCE ~ 2.0
(VCE ~ 2.0
(VCE ~ 2.0
(VCE ~ 2.0
(VCE ~ 2.0
(VCE ~ 2.0
(VCE ~ 2.0
(VCE ~ 2.0

MC1412,B
MC1413,B
MC1413,B
MC1413,B
MC1416,B
MC1416,B
MC1416,B
MC1416,B

V,
V,
V,
V,
V,
V,
V,
V,

-

-

100
50
500
500

-

1.1
0.95
0.85

1.6
1.3
1.1

-

0.85
0.93
0.35
1.0

1.3
1.35
0.5
1.45

V

mA

Vllon)

Unit
/LA

-

-

V

-

-

-

Input Current - Off Condition
(lc ~ 500 /LA, TA ~ + 85'C)

All Types

II(off)

50

100

-

/LA

DC Current Gain
(VCE ~ 2.0 V, IC ~ 350 rnA)

MC1411,B

hFE

1000

-

-

-

-

-

13
2.4
2.7
3.0
5.0
6.0
7.0
8.0

CI

-

15

30

pF

Turn-On Delay Time
(50% EI to 50% EO)

ton

-

0.25

1.0

/Ls

Turn-Off Delay Time
(50% EI to 50% EO)

toff

-

0.25

1.0

/Ls

IR

-

-

50
100

/LA

1.5

2.0

V

Input Capacitance

Clamp Diode Leakage Current
(VR ~ 50 V)

TA
TA

~

~

+25'C
+ 85'C

Clamp Diode Forward Voltage
(IF ~ 350 rnA)

VF

TYPICAL PERFORMANCE CURVES FIGURE 1 -

]: 300

I

MC1413,B

/

MC141S,B

«

I
II

.s

MC1412,B

200

= 25'C
OUTPUT CURRENT versus INPUT CURRENT

400

I

I

I

MC1411,B

TA

FIGURE 2 -

OUTPUT CURRENT versus INPUT VOLTAGE

400

!z
~
gs
u

Max

Ilion)

On Condition
IC ~ 300 rnA)
IC ~ 200 rnA)
IC ~ 250 rnA)
IC ~ 300 rnA)
IC ~ 125 rnA)
IC ~ 200 rnA)
IC ~ 275 rnA)
IC ~ 350 rnA)

Typ

Min

I

300

~

I
All Types

II

f-

~
gs
u

I

200

f-

~

5

I

0. 100

o
o

1.0

2.0

3.0

J

4.0

1=
0. 100

L

~

/

I

9

5.0

8.0

9.0

J

10

9

11

o
o

12

VI, INPUT VOLTAGE (VOLTS)

50

I
J 150
100

200

250

II, INPUT CURRENT (/LA)

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

7-38

300

350

400

MC1411,8, MC1412,8, MC1413,8, MC1416,8

TYPICAL CHARACTERISTIC CURVES - TA
FIGURE 3 -

TYPICAL OUTPUT CHARACTERISTICS

FIGURE 4 -

BOO

:;r:
..§.

!;;;

g§

=>
u

,II

500

2.0

./

y)f

PIN 10 __

1 Oulpul Conducting at a Time

./

/- ~PIN1S

a: 400

ti

Maximum

!ff

~ 300
u

.y 200

/'
,/

ff

100

All Types

0.2

0.4

O.S

o

O.B

1.0

1.2

1.4

I.S

o

14

12

VCE(sal}, SATURATION VOLTAGE (VOLTS}

FIGURE 5 -

INPUT CHARACTERISTICS -

MC1413,B

/

Maximum

:;r:
..§.

15

/

1.5

=>
U
l-

~

to

~

-

/

0.5

FIGURE 6 -

./

/

2.0

I-

~

/ 1/
V/
V

-

t-

~

INPUT CHARACTERISTICS -

1.5

1.0

7.0

6.0

-

Max~

...-

0.5

J.--

B.O

5.0

6.0

7.0

-

~

-...........

~ 500

f3
~

8

.y

MAXIMUM COLLECTOR CURRENT
versus DUTY CYCLE
(AND NUMBER OF DRIVERS IN USE)

.......

...........

~

a:
=>
u
a:

300

.......

........

---

r--..

...........

-...........

r--

..............

-...........

~

20 a

r-

........
....... :---.

......."

r-..... ........... ........ r-..
"r--....::
r--- r-..
~ ::::-- i"--.. ....... . . . . r-..
..............

.............. :::::r-..

100
10

B.O

1

9.0

VI, INPUT VOLTAGE (VOLTS}

FIGURE 7 -

700

V--

---rypIcal

f-- r-

VI, INPUT VOLTAGE (VOLTS}

1000

26

MC1416,B

20

30

50

70

100

% DUTY CYCLE

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

7-39

---

I--'

~

5.0

24

2.0

Typical

4.0

22

..§.

=>
U

3.0

20

:;r:

/'

1.0

lB

2.5

/

/'

g§

V

/'

16

V

.... f-"""

VI, INPUT VOLTAGE (VOLTS}

2.5

2.0

~Iical

V

V

....

0.5

~."

o

/'

/'~

A~

a

I-

MC1412,B

PIN 13-

sao

a

INPUT CHARACTERISTICS -

2.5

I

700

=2S 0C (continued)

10

~

11

12

MC1411,8, MC1412,8, MC1413,8, MC1416,8

RGURE 8 - REPRESENTATIVE CIRCUIT SCHEMATICS

In

In

MC1411,B

MCI41~,B

~-ItI--ir--o Pin 9

...
I

•
I

I

- _.J
I _'-----4---.J\N'v--+
L
______ _

In MC1413,B

In MC1416,B
~-IM-----,c-O Pin 9

~-IM-----,r--o Pin 9

I

I

1

L---14------ --

MOTOROLA LlNEARIINTERFACE ICs DEVICE DATA

7-40

MOTOROLA

-

SEMICONDUCTOR - - - -_ _

MC1472

TECHNICAL DATA

DUAL PERIPHERAL
POSITIVE "NAND" DRIVER

DUAL PERIPHERAL-HIGH-VOL TAGE
POSITIVE "NAND" DRIVER

SILICON MONOLITHIC
INTEGRATED CIRCUITS

The dual driver consists of a pair of PNP buffered AND gates
connected to the bases of a pair of high voltage NPN transistors.
They are similarto the MC75452 drivers but with the added advantages of: 1) 70 Volt capability 2) output suppression diodes and
3) PNP buffered inputs for MOS compatibility. These features
make the MC1472 ideal for mating MOS logic or microprocessors
to lamps, relays, printer hammers and incandescent displays.

•

300 mA Output Capability (each transistor)

•

70 Vdc Breakdown Voltage

•

Internal Output Clamp Diodes

•

Low Input Loading for MOS Compatibility (PNP buffered)

P1 SUFFIX
PLASTIC PACKAGE
CASE 626

PIN CONNECTIONS
MAXIMUM RATINGS (TA = 25°C)
Rating

Symbol

Value

Unit

Supply Voltage
Input Voltage
Output Voltage
Clamp Voltage
Output Current (Continuous)
Operating Junction Temperature

Vec
Vin
Vout
Vc

7.0
5.5
80
80

Storage Temperature Range

Tstg

10

399

V
V
V
V
mA

TJ

+ 150
-65to+ 150

°c
°c

RECOMMENDED OPERATING CONDITIONS
Rating
Supply Voltage

Symbol

Min

Max

Unit

VCC

4.5

5.5

Volts

Operating Ambient Temperature

TA

0

70

°c

Output Voltage

Vo

VCC

70

Volts

Clamp Voltage

Vc

Vo

70

Volts

Positive Logic: V=AB·

TRUTH TABLE
ORDERING INFORMATION

A

B

L
H

Device

Temperature Range

Package

L
L

MC1472P1

o to + 70°C

Plastic DIP

H

L

H

H

H = Logic One
L = Logic Zero

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
7-41

Y
H ("OFF" STATE)

L ("ON" STATE)

MC1472

ELECTRICAL CHARACTERISTICS (Unless otherwise noted minimax limits apply across the O°C to 70°C temperature range
with 4.5 V '" VCC '" 5.5 V. All typical values are for TA
Characteristic

= 25°C, VCC = 5.0 Volts.)

Symbol

Min

Typ

Max

Unit

5.5

Vdc

0.8

Vdc

Input Voltage -

High Logic State

VIH

2.0

Input Voltage -

Low Logic State

VIL

0

-

Input Current - Low Logic State
(VIL = 0.4 V)
A Input
B Input

IlL

-

-

-0.3
-0.15

Input Current - High Logic State
(VIH = 2.4 V)
A Input
B Input
(VIH = 5.5 V)
A Input
B Input

IIH

-

-

40
20

-

-

200
100

Input Clamp Voltage
(Icc = -12 mAl

VIK

-

-

-1.5

Output Leakage Current - High Logic State
(VO = 70 V, See Test Figure)

IOH

-

100

Output Voltage - Low Logic State
(lQL = 100 mAl
(lQL = 300 mAl

VOL

-

-

0.4
0.7

Output Clamp Diode Leakage Current
(VC = 70 V, See Test Figure)

IOC

-

-

100

Output Clamp Forward Voltage
(lFC = 300 mA, See Test Figure)

VFC

-

-

1.7

Power Supply Current
(All Inputs at VIH)
(All Inputs at VIL)

ICC

-

-

70
15

mA

pA

V

pA
V

V
V
mA

-

NOTE: All currents into device pins are shown as positive, out of device pins as negative. All voltages referenced to ground unless otherwise
noted.

SWITCHING CHARACTERISTICS Vee

=

5.0V, TA

=

25 0 e
Symbol

Min

Typ

Max

Unit

Output High to Low
Output Low to High

tpHL
tpLH

-

-

1.0
0.75

/.IS

-

Output Transition Time
Output High to Low
Output Low to High

tTHL
tTLH

0.1
0.1

/.IS

Characteristic
Propagation Delay Time

-

-

-

-

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

7-42

MC1472

TEST CI RCUITS

B
VIH & VIL

Per Truth Table

B

f

vee

VOH
IOH

--

3

4

4

Ve

8

I VOL I
8

Vee

8

Vee

VIH (

3

4

SWITCHING TEST CIRCUIT AND WAVEFORM
+50 V

To Scope

(Output)

To
100

....--o--+-'V\/V--.

I

Pulse
Generator

3.0V

INPUT

"

30pF
Includes Probe

and Stray

v-f

~

OV

+ 30 V

tL---·
5V

~PHL

VOH
OUTPUT

J

90%

90%
50%

tTHL

~'0~%~,_ _ _ _ _ _ _ _~

~

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
7-43

-

MOTOROLA

SEMICONDUCTOR - -_ _ __

MC1488

TECHNICAL DATA
QUAD LINE DRIVER
The MC1488 is a monolithic quad line driver designed to interface data terminal equipment with data communications equipment in conformance with the specifications of EIA Standard No.
EIA-2320.
Features:
•

Current Limited Output
±10 rnA typ

•

Power·Off Source Impedance
300 Ohms min

•

Simple Slew Rate Control with External Capacitor

•

Flexible Operating Supply Range

•

Compatible with All Motorola MOTl and MTTl logic Families

QUAD MDTL LINE DRIVER
EIA-232D
SILICON MONOLITHIC
INTEGRATED CIRCUIT

L SUFFIX
CERAMIC PACKAGE
CASE 632

P SUFFIX
PLASTIC PACKAGE
CASE 646

ORDERING INFORMATION
Device

Temperature Range

Package

Oto + 75'C

Plastic
SO-14

MC1488P
MC1488D
MC1488L

o SUFFIX
PLASTIC PACKAGE ~
CASE 751A
14 ......·
(SO-14)
1

Ceramic
PIN CONNECTIONS

TYPICAL APPLICATION
INTERCONNECTING
CABLE

LINE DRIVER
MCI488

LINE RECEIVER
MC14B9

...r--, "'--I"L- _ _ "

l

INTERCONNECTING

Mon LOGIC INPUT ~r---

CABLE

I

~ MOTL lOGIC OUTPUT

CIRCUIT SCHEMATIC
(1/4 OF CIRCUIT SHOWN)
Vee 14

F--K

B.2k
PINS 4,9, 120R 2
INPUT
INPUT
PINS 5,10,13

10

'00

)----=""
GN01~

10'

VEE 1

T:
I

1k

10

MOTOROLA LlNEARIINTERFACE ICs DEVICE DATA
7-44

OUTPUT
PI NS6,8,11 OR 3

MC1488
MAXIMUM RATINGS (TA

= + 25'C unless otherwise noted.)

Rating

Symbol

Value

Unit

Power Supply Voltage

VCC
VEE

+15
-15

Vdc

Input Voltage Range

VIR

-15'" VIR '"
7.0

Vdc

Output Signal Voltage

Va

±15

Vdc

Po
1/R8JA

1000
6.7

mW
mWrC

TA

o to +75

'c

Tsta

-65 to + 175

'c

Power Derating (Package Limitation, Ceramic
and Plastic Dual-In-Line Package)
Derate above TA = + 25'C
Operating Ambient Temperature Range
Storage Temperature Range

ELECTRICAL CHARACTERISTICS (VCC = +9.0 ±1% Vdc, VEE = -9.0 ±1% Vdc, TA = 0 to 75'C unless otherwise noted.)
Characteristic
Input Current Input Current -

= 0)
High Logic State (VIH = 5.0 V)
Low Logic State (VIL

Output Voltage - High Logic State
(VIL = 0.8 Vdc, RL = 3.0 kO, VCC
(VIL = 0.8 Vdc, RL = 3.0 kO, VCC
Output Voltage - Low Logic State
(VIH = 1.9 Vdc, RL = 3.0 kO, VCC
(VIH = 1.9 Vdc, RL = 3.0 kO, VCC

=
=

Figure

Symbol

Min

Typ

Max

Unit

1

IlL

-

1.0

1.6

rnA

1

IIH

-

-

10

2

VOH

+9.0 Vdc, VEE = -9.0 Vdc)
+ 13.2 Vdc, VEE = -13.2 Vdc)
2

=
=

+9.0 Vdc, VEE = -9.0 Vdc)
+ 13.2 Vdc, VEE = -13.2 Vdc)

-

+6.0
+9.0

+7.0
+10.5

-6.0
-9.0

-7.0
-10.5

-

VOL

-

3

10S+

+6.0

+10

+12

Negative Output Short-Circuit Current, Note 1

3

10S-

-6.0

-10

-12

= VEE = 0, IVai =
Positive Supply Current (RI = 00)
(VIH = 1.9 Vdc, VCC = +9.0 Vdc)
(VIL = 0.8 Vdc, VCC = + 9.0 Vdc)
(VIH = 1.9 Vdc, VCC = +12 Vdc)
(VIL = 0.8 Vdc, VCC = + 12 Vdc)
(VIH = 1.9 Vdc, VCC = + 15 Vdc)
(VIL = 0.8 Vdc, VCC = + 15 Vdc)
Negative Supply Current (RL = 00)
(VIH = 1.9 Vdc, VEE = - 9.0 Vdc)
(VIL = 0.8 Vdc, VEE = -9.0 Vdc)
(VIH = 1.9 Vdc, VEE = -12 Vdc)
(VIL = 0.8 Vdc, VEE = -12 Vdc)
(VIH = 1.9 Vdc, VEE = -15 Vdc)
(VIL = 0.8 Vdc, VEE = -' 15 Vdc)

4

ro

300

-

5

ICC

±2.0 V)

-

5

lEE

Power Consumption
(VCC = 9.0 Vdc, VEE = - 9.0 Vdc)
(VCC = 12 Vdc, VEE = -12 Vdc)

-

-

-

-13

-

-

rnA
rnA
Ohms
rnA

+15
+4.5
+19
+5.5

-

-

Vdc

-

Positive Output Short-Circuit Current, Note 1

Output Resistance (VCC

pA
Vdc

-

-18

-

+20
+6.0
+25
+7.0
+34
+12
-17
-500
-23
-500
-34
-2.5

rnA
p,A
rnA
pA
rnA
rnA

-

-

-

-

-

333
576

275

350

45

75

ns

110

175

ns

55

100

ns

mW

Pc

-

SWITCHING CHARACTERISTICS (VCC = +90 -"'1% Vdc VEE = -90 -"'1% Vdc TA = + 25'C )
Propagation Delay Time (ll
Fall Time

(ll

Propagation Delay Time (ll
Rise Time

(ll

= 3.0 k and 15 pF)
= 3.0 k and 15 pF)
= 3.0 k and 15 pF)
= 3.0 k and 15 pF)

6

tpLH

6

trHL

6

tpHL

-

6

trLH

-

Note 1. MaXimum Pa~kage Power DISSipation may be exceeded If all outputs are shorted simultaneously.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
7-45

ns

MC1488

CHARACTERISTIC DEFINITIONS

FIGURE 1 - INPUT CURRENT
+9 V

FIGURE 2 - OUTPUT VOLTAGE
+9 V

-9 V

FIGURE 3 - OUTPUT SHORT-CIRCUIT CURRENT

-9 V

FIGURE 4 - OUTPUT RESISTANCE IPOWER-OFF)

+1.9 V

105+

I

Vo
±2 Vdc

e

±S.S rnA Max

105-

+0.8 V

FIGURE 6 - SWITCHING RESPONSE

FIGURE 5 - POWER·SUPPLY CURRENTS

Vee

ein--D~r-=3k---I-eva
11~PF

+3 V ,--_ _--.

~
I.~V

VIL
ein

---------0 V

'PHL

Vo-----,.

+0.8 V

'THL--._ _ _ _r--'TLH
tTH Land tTLH Measured 10% to 90%

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
7-46

MC1488

TYPICAL CHARACTERISTICS
(T A = +2SoC unless otherwise noted.)
FIGURE 7 -

FIGURE 8 -

TRANSFER CHARACTERISTICS

versus POWER-SUPPLY VOLTAGE
+12
VCC !VEE}t 12V
+9.0
~

VE~ =,9

vJc -

t-

5 +6.0

t

~ +3.0

~
:::>

~
~



o

>

I

I

:~
•

VI

t-

~

-3.0

O.B V

;:;

-::-

I

-9.0

+3.0

o

3k

~ -6.0
~
-9.0

I

I

0.6
O.B
1.0
1.2
1.4
Vin.INPUT VOLTAGE IVOLTS)

0.4

I.B

1.6

2.0

-55

+20
+16

-;;;-

:0:
.5

100

+12
+8.0

"-'\

t-

~ +4.0

0

2:
~

'\.

~ -4.0

~CL

5

-8.0

1.9 V

52

-12

VI

10

100

1.000

"

- -

lOS

O.B V, Vee

-20
-16

10.000

- ~-

•

-16

11111111

r--- r-. ~

I\.

:::>
u
t-

g~o
II 11111

i---

'"

-

w
t-

1.0
1.0

-12

=VEE =,9 V
-B.O

-4.0

FIGURE 11 -

MAXIMUM OPERATING TEMPERATURE

versus POWER-SUPPLY VOLTAGE
16

~

-......

14

2:
w

12

to


~ B.O

!l:

iil

-

Vee

.............

I
14
3

-

:B
>
ti
>

~

8 3k
11 3 k

I-f-7

2.0

...................

6 3k

I-f--

6.0 I-f---

'"~

~ 4.0

..........

3k

I-f---55

-=

1

I VEE I
o

I
+25
+75
T. TEMPERATURE IOC)

+125

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

7-47

1

3 k!!

~~

LOA~ LINE

-

/
--'

"'\

,

r\

.~

~tvo
+4.0

Va. OUTPUT VOLTAGE IVOLTS)

CL. CAPACITANCE IpF)

0

+125

+25
+75
T. TEMPERATURE IOC)

FIGURE 10 - OUTPUT VOLTAGE
AND CURRENT-LIMITING CHARACTERISTICS

1000

10

-

10S-

FIGURE 9 - OUTPUT SLEW RATE
versus LOAD CAPACITANCE

~

-::-

-12
. 0.2

:;

VEE = 9 V

M

-12

.g

-

105+
+6.0

t:::>

~LD-F

-3.0

~

+12
+9.0

~

~ee - VEE =, 6V

2:

"<
;

SHORT-CIRCUIT OUTPUT CURRENT
versus TEMPERATURE

+8.0

+12

+16

MC1488

APPLICATIONS INFORMATION

-..

The Electronic Industries Association EIA-232D specification
detail the requirements for the interface between data processing equipment and data communications equipment. This
standard specifies not only the number and type of interface
leads, but also the voltage levels to be used. The MCl488 quad
driver and its companion circuit, the MC1489 quad receiver,
provide a complete interface system between DTl or TTL logic
levels and the EIA-232D defined levels. The EIA-232D require·
ments as applied to drivers are discussed herein.
The required driver voltages are defined as between 5 and
15·volts in magnitude and are positive for a logic "0" and
negative for a logic "1." These voltages are so defined when
the drivers are terminated with a 3000 to 7000-ohm resistor.
The MC1488 meets this voltage requirement by converting a
DTUTTl logic level into EIA-232D levels with one stage of

VCC

FIGURE 13 - POWER-SUPPLY PROTECTION
TO MEET POWER-OFF FAULT CONDITIONS

--.------.... - -- - - - - - --.- ---914

r-MC1~8-~
1

0-

r·· .... , :

:-1 . _. . 'o--r-o

o-~-,-- -"',
I'

C>'T ;. ___ ... '

I

1

:
.00J--o
I

l--r7~

FIGURE 12 - SLEW RATE versus CAPACITANCE
FOR ISC = 10 mA

I

oJ

~1

-L __ _

would be excessive. Therefore, if the system is designed to
permit low impedances to ground at the power-supplies of the
drivers, a diode should be placed in each power-supply lead
to prevent overheating in this fault condition. These two
diodes, as shown in Figure 13, could be used to decouple all
the driver packages in a system. (These same diodes will allow
the MCl488 to withstand momentary shorts to the ±25 volt
limits specified in the earlier Standard EIA-232B.) The addition
of the diodes also permits the MCI488 to withstand faults with
power-supplies of less than the 9.0 volts stated above.
The maximum short-circuit current allowable under fault
conditions is more than guaranteed by the previously mentioned 10 mA output current limiting.

1000

t:: I vi",

~
w

...

:'i

~

___ ,

I

V.E>-E-+ot-_ _+-_______ --------~-:

~

o-J--o
I

o-~-.f--"'"
~"1-..f.

The EIA-232D specification further requires that during transitions, the driver output slew rate must not exceed 30 volts

~ 100

I
I

0-,-1. ___ -'

inversion.

0

I

o-i-.1---'\

I!

:

0-+-0

I

10

·per microsecond. The inherent slew rate olthe MC1488 is much
too fast for this requirement. The current limited output of the
device can be used to control this slew rate by connecting a
capacitor to each driver output. The required capacitor can be
easily determined by using the relationship C = lOS x IH/AV
from which Figure 12 is derived. Accordingly, a 330 pF capacitor on each output will guarantee a worst case slew rate of
30 volts per microsecond.
The interface driver is also required to withstand an accidental shortto any other conductor in an interconnecting cable.
The worst possible signal on any conductor would be another
driver using a plus or minus 15 volt, 500 mA source. The
MCI488 is designed to Indefinitely withstand such a short to
all four outputs in a package as long as the power-supply voltages are greater than 9.0 volts (i.e., VCC" 9.0V; VEE'; -9.0 V).
In some power-supply designs, a loss of system power causes
a low impedance on the power-supply outputs. When this
occurs, a low impedance to ground would exist at the power
inputs to the MCl488 effectively shorting the 300 ohm output
resistors to ground. If all four outputs were then shorted to

Other Applications
The MCI488 is an extremely versatile line driver with a myriad of possible applications. Several features of the drivers
enhance this versatility:
1. Output Current Limiting -this enables the circuit designer
to define the output voltage levels independent of powersupplies and can be accomplished by diode clamping of the
output pins. Figure 14 shows the MC1488 used as a DTl to
MOS translator where the high level voltage output is clamped
one diode above ground. The resistor divider shown is used
to reduce the output voltage below the 300 mV above ground
MOS input level limit.
2. Power Supply Range - as can be seen from the schematic
drawing of the drivers, the positive and negative driving elements of the device are essentially independent and do not
require matching power-supplies. In fact, the positive supply
can vary from a minimum seven volts (required for driving the
negative pulldown section) to the maximum specified 15 volts.
The negative supply can vary from approximately -2.5 volts
to the minimum specified -15 volts. The MC1488 will drive
the output to within 2 volts of the positive or negative supplies
as long as the current output limits are not exceeded. The
combination of the current-limiting and supply-voltage features allow a wide combination of possible outputs within the
same quad package. Thus if only a portion of the four drivers
are used for driving EIA-232D lines, the remainder could be
used for DTl to MOS or even DTl to DTl translation. Figure

plus or minus 15 volts, the power dissipation in these resistors

15 shows one such combination.

IF

mill

1.0
1.0

10

100

1000

10.000

C. CAPACITANCE (pfl

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
7-48

MC1488

FIGURE 14 - MDTLlMTTL·TO·MOSTRANSLATOR

FIGURE 15 - LOGIC TRANSLATOR APPLICATIONS

+12V
MOTL
INPUT

MDn

Mm

INPUT

-12V

MOTl ~-'--r--...
MHTl
P-+-<>----=--.....
INPUT 010-t-L-/

MHTl OUTPUT
10 to V

-=---..... -0.7 V

-12V

12
MOTl

~N~~~

,,---,-.r--...

P-+-<>-1>--'W'.r--...----13

10k

-12V

+12V

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

7-49

MOS OUTPUT
-10 V to 0 V

MOTOROLA

-

MC1489
MC1489A

SEMICONDUCTOR - - - - - TECHNICAL DATA
QUAD LINE RECEIVERS

QUAD MDTL

The MC1489 monolithic quad line receivers are designed to
interface data terminal equipment with data communications
equipment in conformance with the specifications of EIA Standard
No. EIA-232D.

•

Input Resistance - 3.0 k to 7.0 kilohms

•

Input Signal Range - ±.30 Volts

•

Input Threshold Hysteresis Built In

•

Response Control
a) Logic Threshold Shifting
b) Input Noise Filtering

LINE RECEIVERS
EIA·232D
SILICON MONOLITHIC
INTEGRATED CIRCUIT

ORDERING INFORMATION
Temperature Range

Device

LSUFFIX
CERAMIC PACKAGE
CASE 632

Package

MC1489p,AP

Plastic
Oto + 75°C

MC1489D,AD

50-14
Ceramic

MC1489L,AL

D SUFFIX
PLASTIC PACKAGE
CASE 751A
(50-14)

P SUFFIX
PLASTIC PACKAGE
CASE 646

14.,.
1

TYPICAL APPLICATION
Input A

LINE RECEIVER
MC1489

LINE DRIVER
MC1488

1

Response 2

I--,'

Control A

-i
-t. __ /

12 Response
Control D

I

Response 5
Control 8

I
- f - - MOll lOGIC OUTPUT

INTERCONNECTING

MOll lOGIC INPUT ~

CABLE

I

9 Response
Control C

I
Ground 7

EQUIVALENT CIRCUIT SCHEMATIC 11/4 OF CIRCUIT SHOWN)
14

Vec
9k

1.7k

5'

RF
3 OUTPUT

RESPONSE CONTROL 2

3.Sk
INPUT 1

~
10k

II

MCI489
,RF: 8.7m

I

MCI489A

1.6kO

'"

r--..

I

1 GROUND

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
7-50

MC1489, MC1489A

MAXIMUM RATINGS (TA - + 25'C unless otherwise noted)
Symbol

Value

Unit

Power Supply Voltage

VCC

10

Vdc

Input Voltage Range

VIR

±30

Vdc

Output Load Current

IL

20

rnA

Po
1I0JA

1000
6.7

mWrC

TA

o to +75

'c

Tstg

-65to +175

'c

Rating

Power Dissipation (Package Limitation, Ceramic
and Plastic Dual In-Line Package)
Derate above TA = + 25'C
Operating Ambient Temperature Range

Storage Temperature Range
ELECTRICAL CHARACTERISTICS (Response control pin is open.) (VCC
otherwise noted)

Characteristics
Positive Input Current

(VIH
(VIH

Negative Input Current

(VIL
(VIL

Input Turn-On Threshold Voltage
(TA = + 25'C, VOL ~ 0.45 V)

= + 25 Vdc)
= +3.0 Vdc)
= - 25 Vdc)
= - 3.0 Vdc)

=

+5.0 Vdc ±10%, TA
Min

Typ

Max

Unit

3.6
0.43

8.3

rnA

IlL

-3.6
-0.43

-

-8.3

rnA

(VIL

= 3.0 V,

IL

=

10 rnA)

Output Short-Circuit Current

0.75
0.75

0.8

1.25
1.25

VOH

2.5
2.5

4.0
4.0

5.0
5.0

Vdc

VOL

-

Power Supply Current (All Gates "on," lout

ICC

Power Consumption

Pc

SWITCHING CHARACTERISTICS (VCC
Propagation Delay Time
Rise TIme
Propagation Delay Time
Fall TIme

1.95

1.5
2.25
Vdc

lOS

= 0 rnA, VIH = + 5.0 Vdc)
(VIH = + 5.0 Vdc)
= 5.0 Vdc +1%,
TA = + 25'C,
(RL = 3.9 kill
(RL = 3.9 kill
(RL = 390 kill
(RL = 390 kill

Vdc

MC1489
MC1489A

Output Voltage Low

-

1.0
1.75
VIL

(VIH = 0.75 V, IL = -0.5 rnA)
(Input Open Circuit, IL = - 0.5 rnA)

+ 75'C unless

IIH

VIH

Output Voltage High

= 0 to

Symbol

MC1489
MC1489A

Input Turn-Off Threshold Voltage
(TA = + 25'C, VOH '" 2.5 V, IL = -0.5 rnA)

mW

-

0.2

0.45

Vdc

-3.0

-4.0

rnA

16

26

rnA

80

130

mW

ns

See Figure 1.)

tTHL

-

FIGURE 2 -

RESPONSE CONTROL NODE

tpLH
tTLH
tpHL

25

85

120

175

ns

25

50

ns

10

20

ns

TEST CIRCUITS
FIGURE 1 -

SWITCHING RESPONSE
+5 Vc1c

or equiv
P-------~--------~----

__

Eo

c~
1/4

MCl489A

tTLH and tTHL

RESPONSE NOOE

p..------.vo

measured

to% - 90%

tTHL

C, capacitor Ii lor none filtering.
R. resistor IS for threshold shlfling.

1.5 V

CL = 15 pF = total parasitic capacitance, which includes
probe and wiring capacitances

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
7-51

MC1489, MC1489A

(Vee

TYPICAL CHARACTERISTICS
= 5.0 Vdc. T A = +250 e unless otherwise nOfedl

FIGURE 3 - INPUT CURRENT

RGURE 4 - MC1489 INPUT THRESHOLD
VOLTAGE ADJUSTMENT
6. 0

+10
+8.0
_

.....

+6.0

....:g +40.

/'

z

~ +2.0

'"
U

....

:g

V

~

V

-2.0

~ -4.0
-6.0

./

V

~

r-RT
r-'"~ 3. o r-.5 k I -

-8.0

I

-10
-25

·20

-15

-10

+5.0

-5.0

r- V'h
o
>
.... 2. o +5 V
~
....
g 1. 0

Y

VI

I-

r--

'-

0

I

I

I

+15

+20

+25

-3.0

-2.0

1.4
1.1
~

4.0
RT

'":;""

3.0

5k

....>
~
....

2.0

-5 V

0

1.0

0

".,;

-

RT

RT
11k
V,h
·5 V

-

~

V'h

-

>

-3.0

I

I

~

'?
RT

.L

'-

.f--.

-

V1h

-1.0

+1.0

~
w

'"
~
0

+3.0

2.0

·1.0

+ 1,0

::

r--- r--

18

0

1.1

"........'"

08

'"

0.1

~

-

1.0

-

0
-60

+4.0

~

0

VIH MCl489
VIL MCl489
VIL MCl489A

"........'"

.,

~

o
3.0

_

-

-=-V'h_

-:!-

+3.0

j

I

MCl489A VIH

4.0

5.0

6.0

VCC. POWER SUPPLY VOLTAGE (VOLTS)

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
7-52

-

r~

I
I

t- MC1~9A VIL I
I
I

'60

w

-

-

T. TEMPERATURE 10C)

'"
~
1.0

+2.0

:
I

VIH MCl489A

>

RT-

MCl489 VIL

FIGURE 7 - INPUT THRESHOLD versus
POWER-SUPPLY VOLTAGE

::
~

-

MCl489VIH

~ 06
04

VI. INPUT VOLTAGE (VOLTS)

1.0

-

-

-

I
1

16

> 1.4

~ :>

+2.0

11k
V,h
-5 V

..'--

.,

r-- ....

VILH -VIHL

-2.0

~

I--

FIGURE 6 - INPUT THRESHOLD VOLTAGE
versus TEMPERATURE

6.0

~

I - - RT

00

VI. INPUT VOLTAGE (VOLTS)

FIGURE 5 - MC1489A INPUT THRESHOLD
VOLTAGE ADJUSTMENT

w

RT

VILH VIHL

Vin. INPUT VOLTAGE IVOLTS)

5.0

RT
13 k
V,h
+5 V

.,;

>

+10

y=

4. 0

w

./

:0

a:z

1/

5.0

-

.110

MC1489, MC1489A
APPLICATIONS INFORMATION

The MC1489 interface receivers have internal feedback
from the second stage to the input stage providing input

hysteresis for noise rejection. The MC1489 input has
typical turn-on voltage of 1.25 volts and turn-off of 1.0
volt for a typical hysteresis of 250 mV. The MC1489A
has typical turn-on of 1.95 volts and turn-off of 0.8 volt
for typically 1.15 volts of hysteresis.
Each receiver section has an external response control node in addition to the input and output pins,
thereby allowing the designer to vary the input threshold voltage levels. A resistor can be connected between
this node and an external power supply. Figures 2, 4
and 5 illustrate the input threshold voltage shift possible
through this technique.
This response node can also be used for the filtering
of high-frequency, high energy noise pulses. Figures 8
and 9 show typical noise-pulse rejection for external
capacitors of various sizes.
These two operations on the response node can be
combined or used individually for many combinations
of interfacing applications. The MC1489 circuits are particularly useful for interfacing between MaS circuits and
MDTL/MTTL logic systems. In this application, the input
threshold voltages are adjusted (with the appropriate
supply and resistor values) to fall in the center of the
MaS voltage logic levels. (See Figure 10)
The response node may also be used as the receiver
input as long as the designer realizes that he may not
drive this node with a low impedance source to a voltage greater than one diode above ground or less than
one diode below ground. This feature is demonstrated
in Figure 11 where two receivers are slaved to the same
line that must still meet the EIA-232D impedance
requirement.

FIGURE 8 - TYPICAL TURN-ON THRESHOLD versus
CAPACITANCE FROM RESPONSE CONTROL PIN TO GND

FIGURE 9 - TYPICAL TURN-ON THRESHOLD versus
CAPACITANCE FROM RESPONSE CONTROL PIN TO GND

General Information
The Electronic Industries Association (EIA) has released
the EIA-232D specification detailing the requirements
for the interface between data processing equipment
and data communications equipment. This standard
specifies not only the number and type of interface
leads, but also the voltage levels to be used. The
MC1488 quad driver and its companion circuit, the
MC1489 quad receiver, provide a complete interface
system between DTL or TTL logic levels and the EIA232D defined levels. The EIA-232D requirements as
applied to receivers are discussed herein.
The required input impedance is defined as between
3000 ohms and 7000 ohms for input voltages between
3.0 and 25 volts in magnitude; and any voltage on the
receiver input in an open circuit condition must be less
than 2.0 volts in magnitude. The MC1489 circuits meet
these requirements with a maximum open circuit voltage of one VSE.
The receiver shall detect a voltage between -3.0 and
- 25 volts as a Logic "1" and inputs between + 3.0 and
+ 25 volts as a Logic "0." On some interchange leads,
an open circuit of power "OFF" condition (300 ohms or
more to ground) shall be decoded as an "OFF" condition
or LogiC "1." For this reason, the input hysteresis
thresholds of the MC1489 circuits are all above ground.
Thus an open or grounded input will cause the same
output as a negative or Logic "1" input.
Device Characteristics

I~--------~~--------~----------~
10

100

1000

PW, INPUT PULSE WIDTH Insl

PW. INPUT PULSE WIDTH Insl

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
7-53

10,000

MC1489, MC1489A

FIGURE 10 - TYPICAL TRANSLATOR APPLICATION MOS TO OTl OR TTL
+S Vdc
i

--..,

-

... ,

l.. __ ,

,

OTL", TTL

r- -,
__ ..J
:
'5VdCl.t

FIGURE 11 - TYPICAL PARAllELING OF TWO MC1489.A RECEIVERS TO MEET EIA-2320
VCC

RESPONSE CONTROL PIN

r-----------------,
111 MCI489
OUTPUT

INPUT

8k

VCCO-~----------------~

OUTPUT

INPUT

L __~8~k~_9_+----------..._1f_v,~~,.............--lo-..

RESPONSE·CONTROL PIN

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
7-54

MOTOROLA

MC14C888

SEMICONDUCTOR-----TECHNICAL DATA

Advance Information
Quad low Power line Driver

QUAD LOW POWER
LINE DRIVER

The MC14C88B is a low power monolithic quad line driver, using BiMOS
technology, which conforms to EIA-232-D, EIA-562, and CCITT V.28. The
inputs feature TTL and CMOS compatibility with minimal loading. The outputs
feature internally controlled slew rate limiting, eliminating the need for external
capacitors. Power off output impedance exceeds 300 n, and current limiting
protects the outputs in the event of short circuits.
Power supply current is less than 160 I1A over the supply voltage range of
±4.5 to ±15 V. EIA-232-D performance is guaranteed with a minimum supply
voltage of ±6.5 V.
The MC14C88B is pin compatible with the MC1488, SN75188, SN75C188,
DS1488, and DS14C88. This device is available in 14 pin plastic DIP, and
surface mount packaging.
Features:
• BiMOS Technology for Low Power Operation «5.0 mW)
• Meets Requirements of EIA-232-D, EIA-562, and CCITT V.28
• Quiescent Current Less Than 160 !LA
• TTUCMOS Compatible Inputs
• Minimum 300 n Output Impedance when Powered Off
• Supply Voltage Range: ±4.5 to ±15 V
• Pin Equivalent to MC1488
• Current Limited Output: 10 rnA Minimum
• Operating Ambient Temperature: -40° to 85°C

SILICON MONOLITHIC
INTEGRATED CIRCUIT

...

f'

,.

PSUFFIX

PLASTIC PACKAGE
CASE 646

DSUFFIX
PLASTIC PACKAGE
CASE 751A
(50-14)

PIN CONNECTIONS

Simplified Block Diagram
(Each Driver)

InpulA

•

OutputA

3

InputB1

4

InputB2

5

OutputB
Gnd

11

OutpulD

6

9

InpulC2

7

8

OutputC

Vee

(Top View)
Input'

o-+-....-Ir

ORDERING INFORMATION

39

Device
MC14C88BP
MC14C88BD

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

7-55

Temperature
Range
-40° 10 +85°C

Package
Plaslic DIP
50-14

MC14C88B
MAXIMUM RATINGS (TA = +25°C, unless otherwise noted.)
Rating
Power Supply Voltage
Vee (max)
VEE(min}
(Vee - VEE}max

Symbol

Value

Vee
VEE
Vee-VEE

+17
-17
34

Unit
Vdc

Input Voltage (All Inputs)

Yin

VEE-Q.3, VEE+39

Vdc

Applied Output Voltage, when Vee=VEE"O V
Applied Output Voltage, when Vee=VEE=O V

Vx

VEE-6.0 V, Vee+6.O V
±15

Vdc

Output Current

10

Self Limiting

rnA

Operating Junction Temperature

TJ

-65, +150

°e

Devices should not be operated at thesa limits. The "Recommended Operating Conditions" table provides for actual

device operation.

RECOMMENDED OPERATING CONDITIONS
Characteristic
Power Supply Voltage

Symbol

Min

Typ

Max

Unit

Vee
VEE

+4.5
-15

-

-

+15
-4.5

Vdc

Input Voltage (All Inputs)

Yin

0

-

Vee

Vdc

Applied Output Voltage (Vee=VEE=O V)

Vo

-2.0

0

+2.0

Vdc

Output DC Load

RL

3.0

-

7.0

kQ

Operating Ambient Temperature Range

TA

-40

-

+85

°e

Max

Unit

All limits are not necessarily functional concurrently.

ELECTRICAL CHARACTERISTICS (-40°C:S; TA:S; +85°C, unless otherwise noted.),
Characteristic

Symbol

Min

ICC (OH)
ICC (OL)

-

Typ

I1A

Supply Current (lout = 0, see Figure 2)
lee@4.75V,;Vee,-VEE'; 15 V
Outputs High
Outputs Low
lEE
Outputs High
Outputs Low

lEE (OH)
lEE (OL)

-160
-160

Output Voltage - High, Yin ,; 0.8 V (RL = 3.0 kn. see Figure 3)
Vee = +4.75 V, VEE = -4.75 V
Vee = +5.0 V, VEE = -5.0 V
Vee = +6.5 V, VEE = -6.5 V
Vee = +12 V, VEE =-12 V
Vec= +13.2 V, VEE =-13.2V (RL = =)
Output Voltage - Low, Yin ~ 2.0 V
Vee = +4.75 V, VEE = -4.75 V
Vee = +5.0 V, VEE = -0.0 V
Vee = +6.5 V, VEE = -6.5 V
Vee = +12 V, VEE =-12 V
Vee = +13.2 V, VEE =-13.2V (RL = =)

VOH

Output Short Circuit Current" (see Figure 4) (Vee = IVEEI = 15 V)
Normally High Output, shorted to ground
Normally Low Output, shorted to ground

lOS

Output Source Resistance
(Vee = VEE = 0 V, -2.0 V,; Vout'; +2.0 V)

RO

300

VIL
VIH

0
2.0

-

-13.2

Input Voltage
Low Level
High Level

-35
+10

• TYPical. reflect performance@TA=2S'C

" .. Only one output shorted at a time, for not more than 1 second.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
7-56

160
160

-

-

-

-

Vdc
3.7
4.0
5.0
10

VOL

-

3.8
4.3
6.1
10.5
13.2
-3.8
-4.2
-6.0
-10.5
-13.2

-

-

-

13.2
-3.7
-4.0
-5.0
-10

rnA
-10
+35

0.8
Vee

Q

Vdc

MC14C88B
ELECTRICAL CHARACTERISTICS CONTINUED (-40'C ~ TA ~ +85'C, unless otherwise noted.)*
Characteristic

Symbol

Input Current
Vin = 0 V, VCC = IVEEI = 4.75 V
Vin = 0 V, VCC = IVEEI = 15 V
Vin = 4.5 V, VCC = IVEEI = 4.75 V
Vin = 4.5 V, VCC = IVEEI = 15 V

Min

Typ

Max

-10
-10
0
0

-0.1
-0.1
+0.1
+0.1

0
0
+10
+10

Min

Typ

Max

Unit

!lA

lin

TIMING CHARACTERISTICS (-40'C ~ TA ~ +85'C, unless otherwise noted.)'
Characteristic

Symbol

Output Rise Time
VCC = 4.75 V, VEE = -4.75 V
-3.3 V ~ Vo ~ 3.3 V
CL = 15 pF
CL = 1000 pF
-3.0 V ~ Vo ~ 3.0 V
CL=15pF
CL = 1000 pF
VCC= 12.0 V, VEE=-12.0V
-3.0 V ~ Vo ~ 3.0 V
CL=15pF
CL = 2500 pF

!,S

tRl
0.22
0.22

0.66
1.52

2.1
2.1

0.20
0.20

0.51
1.16

1.5
1.5

0.20
0.20

0.62
0.82

1.5
1.5

0.53

1041

3.2

tR2

10%~VO~90%

tR3

CL = 15 pF
Output Fall Time
VCC = 4.75 V, VEE = -4.75 V
3.3 V $VO $-3.3 V
CL=15pF
CL = 1000 pF
3.0 V $VO ~-3.0 V
CL = 15 pF
CL = 1000 pF
VCC = 12.0 V, VEE = -12.0 V
3.0 V$ VO$-3.0 V
CL=15pF
CL= 2500 pF
90%$VO$10%
CL= 15pF

!,S

tFl
0.22
0.22

0.93
1.28

2.1
2.1

0.20
0.20

0.72
1.01

1.5
1.5

0.20
0.20

0.70
0.94

1.5
1.5

0.53

1.71

3.2

4.0

-

30

tF2

tF3

Output Slew Rate, 3.0 k!l < RL < 7.0 kQ, 15 pF < CL < 2500 pF

SR

Propagation Delay A (CL = 15 pF, see Figure 1)
VCC = 12.0 V, VEE = -12.0 V
Input to Output - Low to High
Input to Output - High to Low
Propagation Delay B (CL = 15 pF, see Figure 1)
VCC = 4.75 V, VEE = -4.75 V
Input to Output - Low to High
Input to Output - High to Low
* TYPlcals reflect performance @TA

Unit

V/!'s
!,S

tPLH
tPHL

tpLH
tpHL

-

-

-

= 25°C

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
7-57

0.9
2.3

3.0
3.5

004
1.5

2.0
2.5

MC14C88B
Figure 1. Timing Diagram

J-r-

S.G.
OV

VOUT

1.5V

tPHl

NOTES: S.G. set to: I =20 kHz lor Propagation Delay

A

~---VOH

~-_+------

90% -------1--->-/

\«-+------ 3.3 V -------1:-1
\ ' < i - - - - - 3.0V - - - - - - + /

and I =64 kHz lor Propagation Delay B; D~
Cycle = 50%; tR, tF ,;; 5.0 ns
out

---r-H~-----------~tr-r------OV

-----VOL

STANDARDS COMPLIANCE
The MC14C88 is designed to comply with EIA-232-D
(formerly RS-232), the newer EIA-562 (which is a higher
speed version 01 the EIA-232), and CCln's V.28. EIA-562
was written around modern integrated circuit technology,
whereas EIA-232 retains many of the specs written around

the electro-mechanical circuitry in use at the time of its
creation. Yet the user will find enough similarities to allow
a certain amount 01 compatibility among equipment built to
the two standards. Following is a summary of the key
specifications relating to the systems and the drivers.

EIA-232-0

Parameter
Maximum Data Rate

20 kbaud

EIA-562
38.4 kbaud Asynchronous
64 kbaud Synchronous

Maximum Cable Length

50leet

Based on cable capacitance/data rate

Maximum Slew Rate

,;; 30 V/Jls anywhere on the wavelorm

,; 30 VIJlS anywhere on the wavelorm
~ 4.0 V/JlS between +3.0 and -3.0 V

Transition Region

-J.O to +3.0 V

-3.3 to +3.3 V

Transition Time

For UI ;, 25 ms, tR ,; 1.0 ms
For 25 ms > UI > 125 JlS, tR';; 4% UI
For UI < 125 JlS, tR';; 5.0 Jls

For UI ~ 50 JlS, 220 ns < tR ';3.1 Jls
For UI < 50 JlS, 220 ns < tR';; 2.1 JlS
(within the transition region)

MARK (one, off)

More negative than -J.O V

More negative than -J.3 V

Space (zero, on)

More positive than +3.0 V

More positive than +3.3 V

Short Circuit Proof?

Yes, to ground

Short Circuit Current

any system voltage
,; 500 mA to any system voltage

,; 60 mA to ground

Open Circuit Voltage

IVocl,;25V

IVocl < 13.2 V

Loaded Output Voltage

5.0 v,;; IVai';; 15 V for loads between 3.0 kO
and 7.0 kO

IVai

~

~

Yes, to

Power Off Input Source Impedance

..

300 0 for IVai,;; 2.0 V

~

3.7 V for a load of 3.0 kO

300 0 for IVai,; 2.0 V

NOTE: UI = Umt Interval, or bit time .
V.28 standard has the same specifications as EIA·232. with the exception of transition time which is listed as "less than 1.0 ms,
or 3% of the UI, whichever is less".

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

7-58

MC14C88B
Figure 2. Typical Supply Current
versus Supply Voltage

Figure 3. Typical Output Voltage
versus Supply Voltage

110

«
w

55

a:
a:
=>
~

it

8.0

~

4.0

~

0

-::..-~t
(0.8 or 2.0 V)

!:;

=>
en

~ -55

~

-110

~~J

o -8.0
IEE(OH)

8.0

10

12

14

4.0

16

Vee AND -VEE. M

Ise

1

20

~

10

ffi

=>
'-'
t:::
=>

Ii:
ili

~

r-

~
13

o

............

-10

~ -20

-30
4.0

I

Vin
(0.8 or 2.0 V)

----6.0

8.0

-=-

-I

6.0

~32

8.0

10

aw

I

!:i'"

16

I

I
VOL@Vee=-VEE=4.5V

5 -5.0

VOL@vce~ -VEE = 12 V

o

-10

I

-15
14

14

M

VOH@Vee=-VEE=4.5V

5.0

~
!:;

1

12

12

VOH@vee=-VEE=12V
10

:se NOrrnal~ High OutP~
10

3-RL=~

15

ii~
I

I

2-RL=7.0kil

Figure 5. Typical Output Voltage
versus Temperature

Normall~ Low outpul

Vee

I
Vou!

t-- l-RL=3.0kQ

Vee AND -VEE.

Figure 4. Typical Short Circuit Current
versus Supply Voltage
30

2- RL = 7.0 kil
3- RL = 3.0 kil

r

-16

6.0

l-RL=~

V6L

-12

IEE(O~

4.0

RL

VEE

5 -4.0

W

~

VOH

a
!:i

'-'

~~2

I

12
lee(OH)

~

!Z

16

lee(o~

16

Vee AND -VEE. M

-40

+22
TA. AMBIENT TEMPERATURE (Oe)

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
7-59

RL = 3.0 kil
+85

MC14C88B
APPLICATIONS INFORMATION
Description
The MC14C88 was designed to be a direct replacement
for the MC1488 in that it meets all EIA-232 specifications.
However, use is extended as the MC14C88 also meets the
faster EIA-562 and CCITT V.28 specifications. Slew rate
limited outputs conform to the mentioned specifications and
eliminate the need for external output capacitors. Low power
consumption is made possible by SiMaS technology. Power
supply current is limited to less than 160 /lA, plus load
currents over the supply voltage range of ±4.5 V to ±t5 V
(see Figure 2).

input voltage drop below VEE by more than 0.3 V or rise
above VEE by more than 39 V, excessive currents will flow
at the input pin. Open input pins are equivalent to logic high,
but good design practices dictate that inputs should never
be left open.
Operating Temperature Range
The ambient operating temperature range is listed as -40°
to +85°C and meets EIA-232-D, EIA-562 and CCITT V.28
specifications over this temperature range. The maximum
ambient temperature is listed as +85°C. However, a lower
ambient may be required depending on system use, i.e. specifically how many drivers within a package are used, and
at what current levels they are operating. The maximum power which may be dissipated within the package is determined
by:

Outputs
The output low or high voltage depends on the state of
the inputs, the load current, and the supply voltage (see
Table 1 and Figure 3). The graphs apply to each driver regardless of how many other drivers within the package are
supplying load current.

Po

Table 1. Function Tables

- T,lmax - TA
maxijJJA

where: RaJA = the package thermal resistance (typically,
100°CIW for the DIP package, 125°C/W for the
SOIC package);
TJmax = the maximum operating junction
temperature (150°C); and
TA = the ambient temperature.

Drivert

Drivers 2 through 4
Input *1

Input *2

Output*

H
L
X

H
X
L

L
H
H

Po = { [ (VCC - VOH) • IIOHII or [ (VOL - VEE) •
IIOLII leach driver + (VCC • ICC) + (VEE' lEE)
where: VCC and VEE are the positive and negative
supply voltages;
VOH and VOL are measured or estimated from
Figure 3;
ICC and lEE are the quiescent supply currents
measured or estimated from Figure 2.

H =HlQh level, L = Low level, X "" Don t care.

Driver Inputs
The driver inputs determine the state of the outputs in accordance with Table 1. The nominal threshold voltage for the
inputs is 1.4 Vdc, and for proper operation, the input voltages
should be restricted to the range Gnd to VCC. Should the

As indicated, the first term (in brackets) must be calculated
and summed for each of the four drivers, while the last terms
are common to the entire package.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

7-60

MOTOROLA

SEMICONDUCTOR-----TECHNICAL DATA

MC14C89B
MC14C89AB

Advance Information

Quad Low Power Line Receiver

QUAD LOW POWER
LINE RECEIVER

The MC14C89B and MC14C89AB are low power monolithic quad line
receivers, using bipolar technology, which conform to the EIA-232-E, EIA-562 and
CCITT V.28 Recommendations. The outputs feature LSTTL and CMOS
compatibility for easy interface to +5.0 V digital systems. Internal time-domain
filtering eliminates the need for external filter capacitors in most cases.
The MC14C89B has an input hysteresis of 0.35 V, while the MC14C89AB
hysteresis is 0.95 V. The response control pins allow adjustment of the threshold
level if desired. Additionally, an external capacitor may be added for additional
noise filtering.
The MC14C89B and MC14C89AB are each available in a 14 pin dual-in-Iine
plastic DIP and SOIC package.
Features:

PSUFFIX
PLASTIC PACKAGE
CASE 646

• Low Power Consumption

"#

• Meets EIA-232-E, EIA-562, and CCITT V.28 Recommendations
• TTUCMOS Compatible Outputs

DSUFFIX
PLASTIC PACKAGE
CASE 751 A
(SO-14)

• Standard Power Supply: + 5.0 V ± 10%
• Pin Equivalent to MC1489, MC1489A, TI's SN75CI89/A, SN75189/A and
National Semiconductor's DSI4C89/A
• External Filtering Not Required in Most Cases
• Threshold Level Externally Adjustable

PIN CONNECTIONS

• Hysteresis: 0.35 V for MCI4C89B, 0.95 V for MC14C89AB
• Available in Plastic DIP, and Surface Mount Packaging

Input A

• Operating Ambient Temperature: -40° to +85°C

VCC

Response
Control A

Input D
Response
ControlD

Output A
Simplified Block Diagram
(Each Receiver)

DutputD
Response
ControiB

VCC

Input
C
Response
ControlC

OutputB

Input ot---- 0
!:;
D..

!5
a

-9

-

VOH(IO~ = -20 IIA)

MC1.kB9A 8
MCt4C89B
TA=25°C _

4.0 V/!!S between +3.0 V and -3.0 V

IVol ~ 3.7 V for a load of 3.0 kn

5.

o

VOH(lout=- 01lA)

w

4.
0

VOH(lout=- ,2 rnA)

g

3.
0

2:

'"E§

I-

MCI4C89AB
MCI4C898
VCC=5V

::::>

D..

2.
0

!:; 2
a 0

-9

1.
0
VOL(loU! = 3,2 rnA)

o

4,5

4,7

4.9
5.1
VCC, SUPPLY VOLTAGE M

1
0
VOL(lout = 3.2 rnA)

5,3

5,5

o-40

-7.5
25
57.5
TA, AMBIENT TEMPERATURE (OC)

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
7-63

85

MC14C89B, MC14C89AB
Figure 4. Typical Short Circuit Current
versus Temperature

Figure 5. Typical Threshold Voltage
versus Temperature

15

llO
!z

~
~
u

2
0

~

w

Normally Low OU1pU1 Shorted 10 VCC

'"~

MC14C89A
B
MC14C89B
VCC =5.5 V

5
0

t:::

~

0

>

9
0

:I:

en
w
a:
:I:
>>:::J

~ -5.0

a:

o:I:
en -10
-15
-40

0-



9

4
0

\ \

3
0

0

VIH

:I:

en

w
a:

~

!:i
0-

:::J

::J
0-

4.
5

-t----j--+--t--

MC14C89B
Pulse Rate = 300 kHz
RC Pin Open

4.
0

::;;

« 3.
w

~

5

:::J

0-

3.
c
W 0
2.
5

1.6

1.8

2.0

2.2

2.4

2.6

PW, INPUT PULSE WIDTH (!ts)

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
7-64

-

4.5 V < VCC < 5.5 V
20kn

30kn

BIAS RESISTANCE (RRC)

5.
0

C

+ RRC

.:I; Vbat

I
25

85

Figure 7. Typical Effect of Response
Control Pin Bias

MC14C89B
4.5 V 2.5V
H = High Logic State
L = Low Logic State

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
7-69

MC3437
ELECTRICAL CHARACTERISTICS (Unless otherwise noted, specifications apply for 0 ";TA"; 700 e and 4.75 V"; Vee";5 25 V )
Characteristic
Receiver Input Threshold Voltage - High Logic State

(VI L(DA)

(VIH(DA)
(VIH(DA)

1.30

1.55

V

-

15
1.0

50
50

VIH(DA)

2.0

-

-

V

VIL(DA)

-

-

O.B

V

VOH

2.4

-

-

V

VOL

-

0.25

0.4

V

-

BO
2.0

I'A
mA

-3.2

mA

I'A

IIH(DAl

= 2.4 V)
= 5.5 V)

IIL(DA)

-

-

lOS

-lB

-

-55

mA

lee

-

45

65

mA

VI

-

-1.0

-1.5

V

-

Disable Input Current - Low Logic State

= 4.0 V, VIL(DAl = 0.4 V)

Output Short Circuit Current

= 0.5 V, VIL(DA) = OV, Vee = 5.25 V)

Power Supply Current

= 0.5 V, VIL(DA) = 0 V)

Input Clamp Diode Voltage

OI(R)

1.05

= -400I'A)

Disable Input Current - High Logic State

(VI(R)

VIHL(R)

= 0.5 V, VOH ;;>2.4 V, 10H = -400I'A)

Output Voltage - Low Logic State
(VI(R) = 4.0 V, VIL(DA) = O.B V, 10L = 16 mAl

(VI(RI

V

= 0.5 V, VOL ";0.4 V, 10L = 16 mAl

Output Voltage - High Logic State
(VI(R) = 0.5 V, VIL(DA) = O.B V, 10H

(VI(R)

Unit

II(R)

Disable Input Voltage - Low Logic State

(VI(R)

Max
2.50

= 4.0 V, Vee = 5.25 V)
= 4.0V, Vee = 0 V)

Disable Input Voltage - High Logic State

(VI(R)

TVp

2.25

= O.B V, 10H = -400I'A, VOH ;;>2.4 V)

Receiver Input Current

(VI(R)
(VI(R)

Min

I.BO

= O.B V, 10L = 16 mA, VOL"; 0.4 V)

Receiver Input Threshold Voltage - Low Logic State

(VIL(DA)

Symbol
VILH(R)

= -12 mA, II(DA) = -12 mA,

SWITCHING CHARACTERISTICS (TA = 25 0 e Vee = 50 V unless otherwise noted.)
Characteristic
Propagation Delay Time from Receiver Input to

Symbol

Min

Typ

Max

Unit

tPLH(R)

-

20

30

ns

tPHL(R)

-

lB

30

ns

tpLH(DA)

-

9.0

15

ns

tpHL(DAI

-

4.0

15

ns

High Logic State Output
Propagation Delay Time from Receiver I "put to
Low Logic State Output

Propagation Delay Time from Disable Input to

High Logic State Output
Propagation Delay Time from Disable Input to
Low Logic State Output

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
7-70

MC3437
FIGURE 2 - SWITCHING TIMES TEST CIRCUIT AND WAVEFORMS
+5.0 V

To Scope

3.0 V

390

(Input)

----.r----,.
2.3 V

Input

1.3 V
1N916 or

OV3.0 V - - - + - - - - + - - - - - - · , - - - ,

Equiv

Disable
(DA)

To Scope

OV-----+--------+--------~

(Output)

Output
Pulse
Generator

1.5 V

51

1.5 V

1,5 V

1.5 V

VOL----~~---~

To Scope
(Disable)

FIGURE 3 - TYPICAL HYSTERESIS
5.0 , - - - - , - - - , - - . - - - - , - - , - - . - - - - , - - - ,

~ 4.01---+--f--+--j--+--j--+----l
o

~
w

~ 3.0
o

>
~

f--+---+
2.0f--+--

!:;

o

~

1.01---+--

VI(A). INPUT VOLTAGE (VOLTS)

FIGURE 4 -

REPRESENTATIVE CIRCUIT SCHEMATIC
(1/6 Shown)

r---~-~-~-~._-------~~-~._---~--_f-_oVcc

Rl

R4

R3

RIO

R13

--1---+,

Input 0-....

Output

Dl

'--+....--<0 Disable

~~--_e--~~--~--~_e-----~-~-------e_~-OGround

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
7-71

MOTOROLA

-

MC3447

SEMICONDUCTOR - - - - - -

TECHNICAL DATA

OCTAL BIDIRECTIONAL
BUS TRANSCEIVER
WITH
TERMINATION NETWORKS

B.IDIRECTIONAL INSTRUMENTATION
BUS (GPIB) TRANSCEIVER
This bidirectional bus transceiver is intended as the interface
between TTL or MOS logic and the IEEE Standard Instrumentation
Bus (488-1978, often referred to as GPIB). The required bus termination is internally provided.
Low power consumption has been achieved by trading a minimum of speed for low current drain on non-critical channels. A
fast channel is provided for critical ATN and EOI paths.
Each driver/receiver pair forms the complete interface between
the bus and an instrument. Either the driver or the receiver of
each channel is enabled by a Send/Receive input with the disabled
output of the pair forced to a high impedance state. The receivers
have input hysteresis to improve noise margin, arid their input
loading follows the bus standard specifications.

SILICON MONOLITHIC
INTEGRATED CIRCUIT

LSUFFIX
CERAMIC PACKAGE
CASE 623

• Low PowerAverage Power Supply Current = 30 mA Listening
75 mA Talking
• Eight Driver/Receiver Pairs
• Three-State Outputs
• High Impedance Inputs
• Receiver Hysteresis - 600 mV (Typ)
• Fast Propagation Times - 15-20 ns (Typ)
• TTL Compatible Receiver Outputs
• Single + 5 Volt Supply
• Open Collector Driver Output with Terminations
• Power Up/Power Down Protection
(No Invalid Information Transmitted to Bus)
• No Bus Loading When Power is Removed From Device
• Terminations Provided: Termination Removed When Device is
Unpowered

P SUFFIX
PLASTIC PACKAGE
CASE 649

P3 SUFFIX
PLASTIC PACKAGE
CASE 724

PIN CONNECTIONS

TYPICAL MEASUREMENT
SYSTEM APPLICATION

I

Instrument
A
(With GPIB)

I

.

--- ",

'.

" ,"
Instrument
B
(With GPIB)

.

.

I

Programmable
Calculator
(With GPIB)

I

.' ..
---16 Line. T ot81

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

7-72

MC3447
MAXIMUM RATINGS IT A

=

25°C unless otherwise noted I
Symbol

Value

Unit

VCC

7.0

Vdc

VI

5.5

Vdc

Driver Output Current

10101

150

rnA

Junction Temperature

TJ

150

°c

Operating Ambient Temperature Range

TA

Rating
Power Supply Voltage
Input Voltage

Storage Temperature Range

o to

T stg

+70

°c

-65 to +150

°c

ELECTRICAL CHARACTERISTICS

Vee <. 5 50 V and 0 < TA
Characteristic - Note 1

(Unless otherwise noted 4.50 V<

~ 70 c C' typical values are at TA

'=

25°C

Vee:::: 5

0 VI

Symbol

Min

Typ

Max

IBus Pin Open)(VIIS/AI = 0.8 VI
IIIBus) = -12 rnA)

VIBus)
VICIBus)

2.5

-

3.7
-1.5

Bus Current
15.0 V .;; V IBus) .;; 5.5 V)
IVIBus) = 0.5 V)
IVcc = 0 V, 0 V.;; VIBus)';; 2.75 V)

IIBus)

-

-

2.5
-3.2
+0.04

400

600

-

-

2.0

Bus Voltage

Unit

V

-

rnA
0.7
-1.3

-

Receiver Input Hysteresis

rnV

IVIIS/R) = 0.8 V)
Receiver Input Threshold

IVIIS/A)

V

= 0.8 V)

Low to High
High to Low

VILHIR)
VIHLIR)

0.8

1.6
1.0

Receiver Output Voltage - High Logic State
(VIIS/A) = 0.8 V, 10H(RI = -200 ~A, VIBus) = 2.0 V)

VOHIRI

2.4

-

-

V

Receiver Output Voltage - Low Logic State
(VIIS/A) = 0.8 V, 10LlR) = 4.0 rnA, (V (Bus)
Receiver Output Short Circuit Current
(V I ISiR) = 0.8 V, V IBusl = 2.0 V)

VOLlR)

-

-

0.5

V

10S(R)

-4.0

-

-20

rnA

Driver Input Voltage - High Logic State
IVIIS/AI = 2.0 VI

VIHIO)

2.0

-

-

V

Driver Input Voltage - Low Logic State

VILID)

-

-

0.8

V

(VI(SiRl

-

= 0.8 V

= 2.0 VI

Driver Input Current - Data Pins

~A

(VI ISlA) = 2.0 V)
10.5';; VIIO)';; 2.7 VI
(VIID) = 5.5 V)

IIID)
IIB(DI

-100

-

-

-

Input Current - Send/Receive
(0.5';; VI(S/RI';; 2.7 V)
IVI(S/RI = 5.5 V)

IIIS/R)
IIB(S/A)

-250

Driver Input Clamp Voltage

VIC(DI

-

-

-1.5

V

VOHIO)

2.5

-

-

V

VOLIDI

-

-

0.5

V

ICCL
ICCH

-

30
75

45
95

-

7.0
16

15
30
50
30
30
22

(VIIS/R)

= 2.0 V,IICIDI

40
200
~A

-

20
100

= -18 rnA)

Driver Output Voltage

High Logic State
IV ISlA) = 2.0 V, VIHIOI = 2.0 V)
Driver Output Voltage - Low Logic State (Note 2)
(VI(S/R) ~ 2.0 V, VIL(D) ~ 0.8 V, 10LID) ~ 48 rnA)
Power Supply Current
(Listening Mode - All Receivers On)
(Talking Mode - All Drivers On)

SWITCHING CHARACTERISTICS (VCC

rnA

=5 0 V

TA

= 25°C unless otherwise noted)

Propagation Delay of Driver
(Output Low to High)
(Output High to Low)

tpLH(D)
tPHLIDI

Propagation Delay of Receiver (Channels 0 to 5, 7)
(Output Low to High)
(Output High to Low)

tPLH(R)
tPHLIRI

-

28
15

Propagation Delay of Receiver (Channel 6, Note 3)
(Output Low to High)
(Output High to Low)

tpLH(R)
tpHLIRI

-

17
12

ns

-

ns

-

ns

NOTES: 1. Specified test conditions for Vl(siR) are 0.8 V (Low) and 2.0 V (High). Where VI(S/A) is specified as a test condition, VI(S/R) uses the
opposite logic levels.
2. The IEEE 488·1979 Bus Standard changes VOl(D) from 0.4 to 0.5 V maximum to permit the use of Schottky technology.
3. !n order to meet the IEEE 488-1978 Standard for total system delay on the ATN and EOI channels, a fast receiver has been provided on
Channel 6 (Pins 9 and 16).

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

7-73

MC3447

SWITCHING CHARACTERISTICS (continued) (VCC = 5 0 V TA = 25 0 C unless otherwi,e noted)
Symbol

Characteristic

Min

Typ

Max

-

15
15
15
10

30
30
25
25

13
30

25
50

Unit

n,

Propagation Delay Time - Send/Receiver to Data
Logic High to Third State

tPHZ(R)
tPZH(R)
tpLZ(R)
tPZL(R)

Third State to Logic High
Logic Low to Third State
Third State to Logic Low

Propagation Delay Time - Send/Receiver to Bus
Logic Low to Third State
Third State to Logic Low

tpLZ(D)
tpZL(D)

-

-

n,

-

-

PROPAGATION DELAY TEST CIRCUITS AND WAVEFORMS
FIGURE 1 - BUS INPUT TO DATA OUTPUT (RECEIVER)

,---------..,
Input

\

+5.0 V

3.0 V
1.5 V

To Scope
(Input)

-l~L~R~

tpLHiRI

To Scope
(Output)

1 k
)ata

,.-------~- - - - V O H
Output

lN916

1.5 V

or Equiv.

tTLH = tTHL 0;;;. 5.0 ns (10-90)
Duty Cycle = 50%

Send/

Pulse
Generator

-Includes Jig
and Probe Capacitance

FIGURE 2 - DATA INPUT TO BUS OUTPUT (DRIVER)
3.0 V
To Scope
(Output) 3.0 V

Sendl

Driver Input
or Enable

1.5 V

51
Bu,

Pulse

Output
C L '130PF
f = 1.0 MHz

-Includes Jig
and Probe Capacitance

tTLH = tTHL:S;;; 5.0 ns (10-90)
Dutv Cycle = 50%

FIGURE 3 - SEND/RECEIVE INPUT TO BUS OUTPUT (DRIVER)
To Scope
(Output)

Bus
Input

Output
Low to Open

51
Pulse

51

3.0V

f= 1.0MHz

CL "" 30 pF (Includes Jig and
Probe Capacitance

tTLH "" tTHL "" :s;;; 5.0 ns (10-90)
Duty Cycle"" 50%

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
7-74

MC3447
FIGURE 4 - SEND/RECEIVE INPUT TO DATA OUTPUT (RECEIVER)
; - - - - - - - - - , , - - - - - 3.0 V
Input

5.0 V

OV

To Scope
(Output)

1.2 k
Output
High to Opon

r

z~
Pulse

51

Output
Low to Open

600

CL = 15 pF (Includes Jig
and Probo Capilcitance)

f'" 1.0 MHz

tTLH '" tTHL '" ~ 5.0 ns (10-90)
Duty Cycle'" 50%

. FIGURE 5 - TYPICAL RECEIVER HYSTERESIS
CHARACTERISTICS

FIGURE 6 - TYPICAL BUS LOAD LINE

5.0 ,.----,---,-----,~--.---,----,---,___,

g

Vee=255.0
V
4 . 0 - - TA
0C
0

6. 0
4.0

-1---t==:J=:"::=I=l==l===j
..s

2:
w

~

>-

~

3.01----+---+---+--+----1--++-+---j

~ -4.0

o

~

~ -6.0

2.01----+--+---+---+----\--++-f---1

f

---

-

-10 1 -

1.01----+--+---+---+----\--++-f---1

Non·ShadedArea
f--Conforms to
Paragraph 3·5.3 of - f - IEEE Standard
f--488·1978

Vee " 5,0 VI

-11

0~0--~--0~.~5-~--~1.70---L--~1~.5--L--~1.0·

l

-14
-4.0

1.0

-2.0

4.0

VBUS, BUS VO LT AGE (Va LTS)

VI, INPUT VOLTAGE (VOLTS)

FIGURE 7 - SUGGESTED PRINTED CIRCUIT BOARD LAYOUT USING MC3447s AND MC68488

10

MC68488

0

o
o

0
0

2 MC3447s

,---------"--------,
~

VCC

~

T~"'{""~,J ! =1fi

0
0
0
0
0

:~'!...

0
0

: 0....... -.'

0

I 0'

0

IB7

0

T/R1

0
0

DAV
DAC
RFD 0-_ _ _---'

:::: \
SRQ~

0

REN

0

Fe

~

0--1

0--------/,r--O

0--

4

0

0---0108

5

a

2

I

0

a

/

:

o---~~~

/

S/R(5)OS/R(1-4)~

~~SI:(6}--O---------O----D:=~{~
W 1
Gnd

Gnd

Gnd

C>-----{)

I

::;:IP::;e~;1 second

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

7-75

I

~

-

~-8.0

~

o

~

I

I

-2.0 f-..

~

>::;
>

- --

1.0
~

o

I

Gnd

1-6.0

MC3447

FIGURE 8 - SIMPLE SYSTEM CONFIGURATION
+5 V

080

T/R1

r------...,
I
i

Data

T/R 2
087

2 MC3447s

I
OAV

00

I
I

OAV

0101

180

0103

iB2

0105

184

0107

186

07

R/Vii

R/W

RS0

A0

RS2

Address

MC6802
or
MC6800
MPU

A15

IRO

IRO

NDAC

OAC

EOI

EOI

IFe

iFC
MC68488
GPIA
SRO

0102

iB1

0104

183

0106

185

0108

187

NRFD

RFO

ATN

ATN

NOTE 1: Although the MC3447 transceivers are
noninverting, the 488-1978 bus callouts appear

inverted with respect to the MC68488 pin
designations. This is because the 488-1978

REN

REN

L ______ ...JI

Standard is defined for negative logic, while all
M6S0a MPU components make use of positive

Trig

logic format.

IEEE 488-1978 BUS

-=

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
7-76

MC3447

FIGURE 9 - SUGGESTED PIN DESIGNATIONS FOR USE WITH MC68488

MC68488

MC684BB

Connections
A

Connections

MC3447 Pin Designations

A

B

~

T/R 2

Vee

SIR (0)

DAV

SRQ

Data

IB0

fi31

Data 1

3

IB2

IB3

Data 2

4

IB4

IB5

Data 3

5

Is6

IB7

Data 4

6

a0

2

vee

vee

vee

Bus 0

DAV

SRO

22

Bus 1

0101

0102

21

Bus 2

0103

0104

20

Bus 3

0105

0106

19

Bus 4

0107

0108

23

Octal
GPIB

B

DAe

RFD

Data 5

7

Transceiver 18

Bus 5

NOAC

NRFD

TIft 2

T/'R 2

SIR

8

17

SIR (1-4)

T/R 2

T/R 2
ATN

(5)

Ec5T

ATN

Data 6

9

16

Bus 6

EOI

iFC

REN

Data 7

10

15

Bus 7

IFe

REN

T/R 1

Gnd

SIR (6)

11

14

siR (7)

Gnd

Gnd

Gnd

Gnd

Logic Gnd

12

13

Bus Gnd

Gnd

Gnd

GPIB
Bus

GPIA

Instrument

MC3447
(2)

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

7-77

MOTOROLA

MC3448A

_ SEMICONDUCTOR - - - - - TECHNICAL DATA

BIDIRECTIONAL INSTRUMENTATION
BUS (GPIB) TRANSCEIVER
This bidirectional bus transceiver is intended as the interface
between TTL or MOS logic and the IEEE Standard Instrumentation
Bus (488-1978, often referred to as GPIB). The required bus termination is internally provided.
Each driver/receiver pair forms the complete interface between
the bus and an instrument. Either the driver or the receiver of
each channel is enabled by its corresponding Send/Receive input
with the disabled output of the pair forced to a high impedance
state. An additional option allows the driver outputs to be operated in an open collector(1) or active pull-up configuration. The
receivers have input hysteresis to improve noise margin, and their
input loading follows the bus standard specifications.

QUAD THREE-STATE
BUS TRANSCEIVER WITH
TERMINATION NETWORKS
SILICON MONOLITHIC
INTEGRATED CIRCUIT

•
•
•
•
•
•
•
•
•

Four Independent Driver/Receiver Pairs
Three-State Outputs
High Impedance Inputs
Receiver Hysteresis - 600 mV (Typ)
Fast Propagation Times - 15-20 ns (Typ)
TTL Compatible Receiver Outputs
Single + 5 Volt Supply
Open Collector Driver Output Option(1)
Power Up/Power Down Protection
(No Invalid Information Transmitted to Bus)
• No Bus Loading When Power Is Removed From Device
o Terminations Provided: Termination Removed When Device
is Unpowered

L SUFFIX
CERAMIC PACKAGE
CASE 620

o SUFFIX
PLASTIC PACKAGE
CASE 7518

(50-161

(1) Selection of the "Open Collector" configuration, in fact, selects an open collector device with a
passive pull·up load/termination which conforms to Figure 7, IEEE 488-1978 Bus Standard.

P SUFFIX

TRUTH TABLE
Send/Rec. Enable

x-

Info. Flow

PLASTIC PACKAGE
CASE 648

Comments

-

0

X

Bus -

Data

1

1

Data -

Bus

Active Pull·Up

1

0

Data -

Bus

Open Col.

Don t Care

PIN CONNECTIONS
TYPICAL MEASUREMENT
SYSTEM APPLICATION

Send/Rec.
Input A

15 Send/Rec.
Input 0

Data A

Instrument

A
(With GPIB)

I

.

--

Calculator

Pull-Up
Enable
Input A-B

'"

Pull-Up

Bus B

-~

Programmable

Bus A

--- -

l

,

,

,

~~-

,

,

B
(With GPIB)

Input CoD
11 Bus C

Data B

I nstrumant

I

12 Enable

I

Send/Rec.
Input B
Send/Rec.
Input C

Gnd

,

(With GPIB)

- T-

----

=

Bus Termination

VCC~-=
1.7 k

16 Lines Total

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

7-78

3.9 k

MC3448A
MAXIMUM RATINGS ITA" 25 0 C unless otherwise noted)
Rating

Symbol

Value

VCC

7.0
5.5
150
150
o to +70
-65 to +150

Power Supply Voltage
Input Voltage

VI

Driver Output Current

IOIO}

Junction Temperature

TJ

Operating Ambient Temperature Range

TA

Storage Temperature Range

T stg

Unit
Vdc
Vdc
mA
°c
°c
°c

ELECTRICAL CHARACTERISTICS
(Unless otherwise noted 4.75 V ~

Vee

0;;;;

5.25 V and

a .;;

TAO;;;; 70De; typical values are at TA

Characteristic

=2Soc, Vee = 5.0 V)

Symbol

Min

Typ

Max

VIBUS)
VICIBUS)

2.75

-

3.7
-1.5

0.7
-1.3

-

-

2.5
-3.2
+0.04

400

600

-

-

1.6
1.0

1.8

Unit
V

Bus Voltage
IBus Pin Open)IVIIS/R) "0.8 V)
(lIBUS)" -12 mAl
Bus Current
15.0 V <; VIBUS) <; 5.5 V)
IVIBUS)" 0.5 V)
IVcc~OV.OV <; VIBUS) <; 2.75 V)

-

mA

IIBUS)

-

Receiver Input Hysteresis

mV

IVIIS/R)" 0.8 V)
V

Receiver Input Threshold

IVIIS/R) "0.8 V. Low to High)
IVIIS/R) ~ 0.8 V. High to Low)

VILHIR)
VIHLlR)

Receiver Output Voltage - High Logic State
IVIIS/R) "0.8 V. IOHIR)" -800 ~A. VIBUS}" 2.0 V)
Receiver Output Voltage - Low Logic State
IVIIS/R)" 0.8 v. 10LlR) " 16 mAo VI BUS) "0.8 V)
Receiver Output Short Circuit Current

-

-

V

-

-

0.5

V

10SIR)

-15

-

-75

mA

VIHID)

2.0

-

-

V

VILlD)

-

-

0.8

V

VOHIR)

0.8
2.7

VOLlR)

IVIIS/R) "0.8 V. V IBUS) "2.0 V)

Driver Input Voltage - High Logic State
IVIIS/R)" 2.0 V)
Driver Input Voltage - Low Logic State
IVIIS/R)" 2.0 V)

IJA

Driver Input Current - Data Pins

IVIIS/R)" VilE) ~ 2.0 V)
10.5 <; VIID) <; 2.7 V)
IVIID) "5.5 V)

-

40
200

-

20
100

-

-

20
100
-1.5

V

VOHID)

2.5

-

-

V

VaLID)

-

-

0.5

V

10SID)

-30

-120

mA

ICCL
ICCH

-

11(0)
IIB(D)

-200

-100

IVIIS/R)" 5.5 V)

IIiS/R)
IIBIS/R)

Input Current
Enable
10.5 <; VilE) <; 2.7 V)
IVIIE) "5.5 V)

IIIE)
IIBIE)

-200

Driver Input Clamp Voltage

VIC(D)

-

IJA

Input Current - Send/Receive
10.5';; VIIS/R)';; 2.7 V)

-

IJA

IVIIS/R) ~ 2.0 V. IICID)" -18 mAl
Driver Output Voltage - High Logic State

IVI(S/R) " 2.0 V. VIHID) ~ 2.0 V. VIHIE)" 2.0 V. 10H" -5.2 mAl
Driver Output Voltage - Low Logic State (Note 1)

IVIIS/R)" 2.0 V. 10LID) ~ 48 mAl
Output Short Circuit Current

IVIIS/R)" 2.0 V. VIHID)" 2.0 V. VIHIE)" 2.0 V)
mA

Power Supply Current
(Ustening Mode - All Receivers On)
(Talking Mode - All Drivers On)

-

63
106

85
125

SWITCHING CHARACTERISTICS (VCC "5.0 V. TA " 25 0 C unless otherwise noted)
ns

Propagation Delay of Driver
(Output Low to High)
(Output High to Low)

tpLHID)
tPHLlD)

-

-

-

15
17

Propagation Delay of Receiver
(Output Low to High)
(Output High to Low)

tPLH(R)
tPHLlR)

-

-

25
23

ns

-

NOTE 1. A modification of the IEEE 488-1978 Bus Standard changes VOL (D) from 0.4 to 0.5 V maximum to permit the use of
Schottky technology.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
7-79

MC3448A
SWITCHING CHARACTERISTICS (continued I (Vcc = 5.0 V, TA = 25°C unless otherwise noted)
Characteristic
Propagation Delay Time - Send/Receive to Data
Logic High to Third State
Third State to Logic High
Logic Low to Third State
Third State to Logic Low

Symbol

Min

Typ

Max

tPHZ(R)
tpZH(R)
tPLZ(R)
tpZL(R)

-

-

30
30
30
30

Propagation Delay Time - Send/Receive to Bus
Logic High to Third State
Third State ~o Logic High
Logic Low to Third State
Third State to Logic Low

tPHZ(D)
tPZH(D)
tpLZ(D)
tpzLlol

-

tPOFF(E)
tPON(E)

-

Unit
ns

-

-

ns

-

30
30
30
30

-

-

Turn-On Time - Enable to Bus

ns

Pull-Up Enable to Open Collector
Open Collector to Pull-Up Enable

-

30
20

-

PROPAGATION DELAY TEST CIRCUITS AND WAVEFORMS
FIGURE 1 - BUS INPUT TO DATA OUTPUT (RECEIVER)

Js:

Input

r--------.:-

Output

+5.0 V

3.0V

1.5 V

To Scope

tPHL~:'

tpLH(RI

To Scope
(Output)

240

(Input)

---VOH
1.5 V

1N916
or Equiv.

f= 1.0 MHz

= tTHL"

tTLH

Duty Cycle

::=

5.0 ns (10-90)

50%
Pulse

Generator

Send!
Rec

tlncludes Jig and
Probe Capacitance

FIGURE 2 - DATA INPUT TO BUS OUTPUT (DRIVER)
3.0 V

To Scope
(Input)

To Scope
(Output) 2.3 V
Send!

L--..-f--o-~ Rec

Driver Input
or Enable

38.3

1.5 V

Bus

Pulse

Output
C L '130PF

fo::: 1.0 MHz

• Includes Jig
and Probe Capacitance

Pull-Up Enable

tTLH

0:::

tTHL

<.

5.0 ns (10-90)

Duty Cycle;::: 50%

3.0 V

FIGURE 3 - SEND/RECEIVE INPUT TO BUS OUTPUT (DRIVER)
To Scope
(Output)

Bus

~13.5

o'r~ 1

To Scope
(Input)
Pulse
Generator

Input

ZL

51
CL

c

Output
High to Open

Output
Low to Open

15 pF (includes Jig and
Probe Capacitance

f=1.0MHz

tTLH

= 'THL = ... 5.0 ns (10-901

Duty Cycle;::: 50%

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
7-80

MC3448A

FIGURE 4 - SEND/RECEIVE INPUT TO DATA OUTPUT (RECEIVER)

r-------___- - - - 3 . 0 V
Input

5.0 V

OV

To Scope

3.0 V

(Output)

VOH
Output
High to Open
Output

Low to Open

51

CL

=

15 pF (Includes Jig
and Probe Capacitance)

f = 1.0 MHz

tTLH = tTHL

==,;;; 5.0 ns (10-90)

Duty Cycle = 50%

FIGURE 5 - ENABLE INPUT TO BUS OUTPUT (DRIVER)
To Scope

3.0 V

(Output)

Enable'np~t
1.5 V
1.5V
3.0V

Data

tpON(E)
To Scope

480

ctPOF~~E~

~ ~o V

Output

(Input)

OV

t=

Send/Ree

90%

- - - - ' ~ 1.0 V

Pulse

Generator

1"1.

51

VOC

f= 1.0MHz

CL == 15 pF (Includes Jig

tTLH == tTHL

and Probe Capacitance

=.;;;; 5.0 ns (10-90)

Duty Cycle = 50%

FIGURE G - TYPICAL RECEIVER HYSTERESIS
CHARACTE R ISTICS

FIGURE 7 - TYPICAL BUS LOAD LINE

5.0

6.0
.

-

~ 4.0

-

Vee- 5.OV
TA - 25 0 e

2.0
.§
f-

~ 3.0

..........

,

".

~ -2.0

'"

~

.......

~ -8.0

~

~ 1.0

-10

o

0.5

....

1.0

1.5

•
-14
-4.0

2.0

."

Conforms to
Paragraph 3·5.3 of

•••

.

48B·1978
vc.C' 5.0 V

>-1

I

, .....

2.0

-2.0

MOTOROLA LlNEARIiNTERFACE ICs DEVICE DATA
7-81

Area

~ii:iE Sta'ndafd

VBUS, BUS VOLTAGE (VOLTS)

VI, INPUT VOLTAGE (VOLTS)

r .....

,~tH'·Shaded

•••••••

-12

o

.........

I

~ -6.0 I.·.·

2.0

- ---.1

I

.....

G -4.0

'">
~

."

.....

....

~

'"

~

'

................

4.0

·'1
4.0

1
J

;::::..
•

••

.

~
~

.. ~
~r6.0

MC3448A

FIGURE 8 - SIMPLE SYSTEM CONFIGURATION
+5 V

DBp

T/R 1

D¢
Data

T/R 2

EOI

EDT

SRO

SRO

REN

REN

IFC

IFC

ATN

ATN

DB7

07

R/W

R/W

RSP

A0

MC6802

OR
Me68QO

RS2

MPU

Address

0

,
•

i.

A15

0

OJ:;;

IRO

IRO

DAC
RFD

DAV
MC68488
GPIA

iEijj

IB1
iB2

..

IB3

o

184

IB5

NOTE 1: Although the MC3448A transceivers

are non-inverting, the 488-1978 bus ca!louts
appear inverted with respect to the MC68488

pin designations. This is because the 488-1978
186

IB7

t-----t-----.---~

Trig ....

Standard is defined for negative logic, while
all M6800 MPU components make use of
positive logic format.
NOTE 2: Unless proper considerations are
provided, it is recommended that the pull-up
enable pins on the MC3448As be groundod,

selecting the open-collector mode.

IEEE 488-1975 BUS

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
7-82

MC3450
MC3452

MOTOROLA

• SEMICONDUCTOR
TECHNICAL DATA

QUAD LINE RECEIVERS
WITH COMMON THREE·STATE
STROBE INPUT

QUAD MTTL COMPATIBLE
LINE RECEIVERS
The MC3450 features four MC75107 type active pullup line
with the addition of a common three-state strobe input.
When the strobe input is at a logic zero, each receiver output state is
determined by the differential voltage across its respective inputs.
With the strobe high, the receiver outputs are in the high impedance
state.
The MC3452 is the same as the MC3450 except that the outputs
are open collector which permits the implied "AND" function.
The strobe input on both devices is buffered to present a strobe
loading factor of only one for all four receivers and inverted to
provide best compatability with standard decoder devices.

SILICON MONOLITHIC
INTEGRATED CIRCUITS

receivers

•

!I _

16

Receiver Performance Identical to the Popular
MC75107/MC75108 Series

•
•

Four Independent Receivers with Common Strobe Input
Implied "AND" Capability with Open Collector Outputs

•

Useful as a Quad 1103 type Memory Sense Amplifier

1

LSUFFIX
CERAMIC PACKAGE
CASE 620

-

PSUFFIX

_

PLASTIC PACKAGE
CASE 648
16
1

D SUFFIX
PLASTIC PACKAGE
CASE 7518

16

(50·161

.
~
...
....

PIN CONNECTIONS

Inputs
A
Inputs

B

FIGURE 1 - A TYPICAL MOS MEMORY SENSING APPLICATION FOR A
4 k WORD BY 4·BIT MEMORY ARRANGEMENT EMPLOYING
1103 TYPE MEMORY DEVICES

Strobe
Output C
Output 0

Inputs
C

Inputs

D
Gnd

TRUTH TABLE
Output
Input

Strobe

MC3450

MC3452

VID ;e
+25 mV

L

H

Off

H

Z

Off

-25 mV '"
VID '" + 25 mV

L

I

I

H

Z

Off

VIO '"
-25 mV

L

L

L

H

Z

Off

l '-' Low Logic State
H - High Logic State
Z =- Third (High Impedance} State
I '" Indeterminate State

Only four MC3450 devices are required for
a 4 k word by 16·bit memory system.

MOTOROLA LlNEAR/INTERFACE ICs DEVICE DATA

7·83

MC3450, MC3452
MAXIMUM RATINGS ITA = 0 to +700C unless otherwise noted)
Rating

Symbol

Value

Unit

VCC.VEE

±7.0

Vdc

Differential Mode I nput Signal Voltage Range

VIDR

±6.0

Vdc

Common Mode Input Voltage Range

VICR

±5.0

Vdc

Strobe Input Voltage

VIIS)

5.5

Vdc

1000
6.6

mW
mWf'C

1000
6.6

mW
mW/oC

Power Supply Voltages

Power Dissipation (Package Limitation)
Ceramic Dual In-Line Package

Po

Derate above T A = +250 C
Plastic Duall n-Line Package

Derate above T A = +25 0 C
Operating Temperature Range

TA

o to +70

°c

Storage Temperature Range

T stg

-65to+150

°c

RECOMMENDED OPERATING CONDITIONS IT A = 0 to +700C unless otherwise noted)
Characteristic
Power Supply Voltages

Symbol

Min

Typ

Max

Unit

VCC
VEE

+4.75
-4.75

+5.0
-5.0

+5.25
-5.25

Vdc

-

mA

-5.0

-

16

VIDR

+5.0

Vdc

Common Mode Input Voltage Range

VICR

-3.0

-

+3.0

Vdc

Input Voltage Range (any input to Ground)

VIR

-5.0

+3.0

Vdc

Output Load Current

10l

Differential Mode Input Voltage Range

ELECTRICAL CHARACTERISTICS IVcc

= +5 0 Vdc VEE = -50 Vdc TA = 0 to +700 C unless otherwise noted)

MC3450

MC3452

Symbol

Fig.

Min

Typ

Max

Min

Typ

Max

Unit

High Level Input Current to Receiver Input

IIHII)

7

-

75

75

pA

IlllI)

8

-

-10

-

-

Low Level I nput Current to Receiver Input

-

-

-10

pA

High Level Input Current to Strobe Input

IIHIS)

5

-

40
1.0

-

40
1.0

pA
mA

-1.6

-

-1.6

mA

-

-

Vdc

-

250

pA

0.5

-

0.5

Vdc

-70

-

-

mA

Characteristic

-

VIHIS) ~ + 2.4 V
VIHIS) ~ + 5.25 V
Low Level I nput Current to Strobe Input

VILIS)

IlllSI

5

2.4

+0.4 V

High Level Output Voltage

VOH

3

High Level Output Leakage Current

ICEX

3

Low Level Output Voltage

Val

3

-

-

Short-Circuit Output Current

lOS

6

-18

-

loll

9

-

-

40

--

-

-

pA

High Logic Level Supply Current from Vce

ICCH

4

-

45

60

-

45

60

mA

High Logic Level Supply Current from VEE

IEEH

4

-

-17

-30

-

-17

-30

mA

Output Disable Leakage Current

SWITCHING CHARACTERISTICS IVCC

= +5 0 Vdc

VEE" -5 0 Vdc TA

=

+25 0

C unless otherwise noted)

MC3450

MC3452

Symbol

Fig.

Min

Typ

Max

Min

Typ

Max

Unit

High to Low Logic Level Propagation Delay
Time (Differential Inputs)

tpHllD)

10

-

-

25

-

-

25

ns

Low to High Logic Level Propagation Delay
Time (Differential Inputs)

tplHID)

10

-

-

25

-

-

25

ns

Open State to High Logic Level Propagation
Delay Time (Strobel

tPZHIS)

11

-

-

21

-

-

-

ns

High Logic Level to Open State Propagation
Delay Ti me (Strobel

tpHZIS)

11

-

-

18

-

-

-

ns

Open State to Low Logic Level Propagation
Delay Time (Strobel

tPZlIS)

11

-

-

27

-

-

-

ns

Low Logic Level to Open State Propagation
Delay Time (Strobel

tPlZIS)

11

-

-

29

-

-

-

ns

High Logic to Low Logic Level Propagation
Delay Time (Strobe)

tpHllS)

12

-

-

-

-

-

25

ns

Low Logic to High Logic Level Propagation
Delay Time (Strobel

tPlHIS)

12

-

-

-

-

-

25

ns

Characteristic

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
7-84

MC3450, MC3452

FIGURE 2 - CIRCUIT SCHEMATIC
(114 Circuit Shown)
Vcco---~--~------~----~--------~----------~----~--------~--,

650

4k

850

1.6 k

~+------1

1--<"-"----<1+4.75 V

V2 --------::<>---1
+O.B V

TEST TABLE

-+-----"<>-1
1--<>-=-+-+-41 -4.75 V

MC3450 MC3452 MC3450 MC3452 MC3450 MC34S2 MC3450 MCJ452

V3-4-~---"-<>--l
V4_++--~--'-<>---1

(MC3452)

+5.25 V

---0----0

Channel A Ihown under tUt. Olher CMDnnel, erllll1lted limilarly

ICEX

III
(MC3450)

FIGURE 5 - IIHIS) AND IILIS)

FIGURE 4 - ICCH AND IEEH
+3.0 V _

.....- - - - - - - - - - - - - - - - - - ,

H>--...... +5.25

V

H>-............ +3.0 V

+5.25 V

~>-I-I---1H..... -5.25

+3.0 V

V

V

_+--+--o-!,-(
Fo-H---_e +5.25

V,

V, - 2.0 V_+-......=---0-:'-<

BHH_e+3.0V

8>--_e +5.25

V

Pe>-f-+-e -S.25

V

+3.DV_-"'--o-!-l

8>---e+5.25

V

R:>-I-J._e -5.25

V

V,_+...=----o-::-<
+2.0 V ......~--I-+-o-!!l

+3.0 V_+-+-<>-'~

Channel AI-) shown under test, other channels are tested
slmllarlv. Devices are tested with V1 from +3.0 V to -3.0 V.

Output of Channel A shown under test, other outputs are

tested similarly for V1 = 0.4 V and +2.4 V.

FIGURE 10 - RECEIVER PROPAGATION DELAY tpLH(OI AND tpHL(OI
+5.0 V

+100 mV _--~--o..!...j

200mVT:h---Ein

50%

OV

t:~~I~-~----tpHLIO)
EO

1.5 V

VOL
Eln waveform characteristics:

Output of Channal B shown under test, other channels are tested similarlv.
51 at
51 at
CL =
CL '"

tTLH and tTHL~ 10 ns measured 10% to 90%
PRR" 1.0 MHz
Duty Cvcle '" 500 ns

"A" for MC3452
"B" for MC3450
15 pF total for MC3452
50 pF total for MC3450

MOTOROLA LlNEARIINTERFACE ICs DEVICE DATA
7-86

MC3450, MC3452

TEST CIRCUITS (continued)

FIGURE 11 - STROBE PROPAGATION OELAY TIMES tPLZ(S): tpZL(S) tpHZ(S) and tPZH(S)

+5.0 V

V2
GND
GND

51

S2

Closed

Closed

15 pF

Closed

Open

50 pF

100 mV

Closed

Closed

15 pF

lQOmV

Open

Closed

50 pF

V1
tPLZ(SI

100 mV

tpZL{S)

100mV

tpHZtS)

GND
GND

tpZH(S)

CL

CL includes Jig and probe capacitance.
Ein waveform characteristics:
tTLH and tTH L ~ 1 0 ns measured 10% to 90%.
PRR

~

1.0 MHz

Duty Cycle = 50%
Output of Channel B shown under test,
other channels are tested similarlV.

tPLZ(SJ E;n

3.::-----

tpHZ(S) {.," ' :
__---~1.5V

VOH

tEO

tPZL(S)j E;n

"c"

:_mn

EO

3'::~

E;n

EO

EO

1.5 V

,

-

{

VOL--------"----

::l:::: 1.5 V

3'OV~
50%
oV

tPZH(S)

5.0V-VO,

VOH-O.5 V

.

-tpZH(S)

VOH~----I1.5 V
"'OV

FIGURE 12 - STROBE PROPAGATION OELAY tpLH{S) AND tpHL(S)

+5.0 V
Ein

.100 mV.._---..---<>-'-!

+3'OV~----50%
OV

~~L:~(~____
tpHUS)

390

~~-+---t-.EO

8>-1H...... -5.0 V

EO

1.5 V

VOL
15 pF

I(Tot811
Ein waveform characteristics;
tTLH and tTHLEQ; 10 nl m.asured '0% to 90%
PAR "'.OMHz
Duty Cycle" 500 nl
Output of Channel B shown under tast, other channels are tested similarly,

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
7-87

MC3450, MC3452

APPLICATIONS INFORMATION
FIGURE 13 -IMPLIED "AND" GATING

FIGURE 14 - BIDIRECTIONAL DATA TRANSMISSION

Vref

500

t

+5.0 V

}--I-o-....""'- +5.0 V

-+-o-+-l

ADDRESS #1 ....

1BO
COMPUTER _

BUS

-+-0-+-1

MEMORY

BUS

3BO

ADDRESS #2 __

STROBE

1/41MCJ4501
CIRCUIT

+-<>-...--1

ADDRESS #3 ___

The three·state capability of the MCJ450 permits
bidirectional data transmission as illustrated.

)-t-ro.....- .. OUTPUT

--o-..L-1

A DO R E SS #4 ....

The MC3452 can be used for address decodiny as illustrated
above, All outputs of the MC3452 er. tied together through 8
cammon resistor to +5.0 volts. In this configuration the MC3452
provides the "ANO" function. All addresses have to be true

before the output will go high. This scheme eliminates the need
for en "AND" gate and enhances speed throughput for address
decoding.

FIGURE 15 - SINGLE·ENDED UNI·BUS· LINE RECEIVER
APPLICATION FOR MINICOMPUTERS

FIGURE 16 - WIRED "OR" DATA SELECTION USING
THREE·STATE LOGIC
STROBE

lN914

9
'50 v

MCJ450

2N2222 or .quiv
+5.0 V

r-------,I

I
I

'so

STROBE

I

DATA

DATA B U S _ - + - - _ - + - o - + - l

OATA
LINES

'5.0 V

MCJ450

'so

AODRESS

ADDRESS BUS - - - - + - - + - 0 - + - - 1

STROBE

9

CONTROL

I

390

MC34501=

I

_---_-+-<>+-:--I

~

}--o-<

390

CONTROL BUS - - + - - - - + - 0 - + - 1

STROBE

DATA
OUTPUT

MCJ450

390

'so

+5.0 V

~

¢

I

DATA BUS_---+_-+-o-+--I

390

I-<>--

MC3450

I

MC3452

I

:

L _______

.J

"T"deml.k 01 Ollliul
EqUIpment Corp.

d.

TO ADDITIONAL
RECEIVERS

The MCJ450/J452 can be used for single.ended as well as
differential line receiving. For slngle·ended line receiver appli·
cations, such as are encountered In minicomputers, the con·
figuration shown In Figure 15 can be used. The voltage lOurce,
which generates Vref. should be designed so that the Vr.f
voltage Is halfway between VOHlmlnl and VOLlmaxl. The
maximum input overdrive required to guarantee a given logic
state is extremely small, 25 mV maximum. This low·input over·
drive enhances differential noise immunity. Also the high·input
impedance of the line receiver permits many receivers to be
placed on a single line with minimum load effects.

01 ·02 OJ 04

X
A1

A2

V

1/2 MC4001
CIRCUIT

I

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
7-88

MC3450, MC3452

APPLICATIONS INFORMATION {continued I

FIGURE 17 - PARTY·LINE DATA TRANSMISSION SYSTEM
WITH MULTIPLEX DECODING

~R()B!

DATA
INPUTS

-+--0-1
MCJ4!jJ~ r---_-+__

OUTPUTS

~

OUTPUTS

OUTPUTS

OA

rA

INPUTS

_++I-o-j

Me3"'3

-

I?~
02

2'3

--O-MC/404
~ CIRCUIT

~

-<>---

l)UTPUTS

-

-01 '2
)(
-0- MC4001K:>-_ _- - .
-0- CIRCUIT - 0 - -

~

y

•

.2

.2

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
7-89

MOTOROLA

-

MC3453

SEMICONDUCTOR - - - - - -

TECHNICAL DATA

QUAD LINE DRIVER WITH
COMMON INHIBIT INPUT

MTTL COMPATIBLE QUAD LINE DRIVER

SILICON MONOLITHIC
INTEGRATED CIRCUIT

The MC3453 features four SN75110 type line drivers with a
common inhibit input. When the inhibit input is high, a constant
output current is switched between each pair of output terminals
in response to the logic level at that channel's input. When the
inhibit is low, all channel outputs are nonconductive (transistors
biased to cut-off). This minimizes loading in party-line systems
where a large number of drivers share the same line.
• Four Independent Drivers with Common Inhibit Input
• -3.0 Volts Output Common-Mode Voltage Over Entire
Operating Range

L SUFFIX

• Improved Driver Design Exceeds Performance of
Popular SN7511 0

CERAMIC PACKAGE
CASE 620

P SUFFIX
PLASTIC PACKAGE
CASE 648

FIGURE 1. - PARTY·LlNE DATA TRANSMISSION SYSTEM WITH
MULTIPLEX DECODING

PIN CONNECTIONS

DATA
'NPUTS

vcc
INPUT B

Y

OUTPUT A

OA1A.
INPUTS

Y

Z

OUTPUTB
Z

OUTPUT

Z

c·

z

Y

OUTPUT 0
Y

DATA

INPUTS

DATA
INPUTS

TRUTH TABLE
(positive logic)
Inhibit
Input

Z

Y

H

H

On

Off

L

H

Off

On

H

L

Off

Off

L

L

Off

Off

L = Low LogIc Level
H

= High

Logic Level

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

7-90

Output
Current

Logic
Input

MC3453
MAXIMUM RATINGS (TA = 0 to +700 e unless otherwise noted I
Symbol

Value

Unit

Vee
VEE

+7.0
-7.0
5.5
-5.0 to +12

Volts

1000
6.6
Oto +70
-65 to +150

mW
mW/oe
ue

Power Supply Voltage
Logic and Inhibitor Input Voltages

Vin

Common-Mode Output Voltage Range

VOeR

Volts
Volts

Po

Power Dissipation (Package Limitation)
Plastic and Ceramic Dual In-Line Packages

Derate above T A = +25 0 e

Operating Ambient Temperature Range

TA

Storage Temperature Range

T stg

°e

Plastic and Ceramic Dual In-Line Packages
RECOMMENDED OPERATING CONDITIONS (See Notes 1 and 2)

Characteristic

Symbol

Min

Nom

Max

Unit

Vee
VEE

+4.75
-4.75

+5.0
-5.0

+5.25
-5.25

Volts

0
0

-

+10
-3.0

Power Supply Voltages
Common-Mode Output Voltage Range

Volts

VOeR

Positive

Negative

Notes: 1. These voltage values are in respect to the ground terminal.
2. When not using all four channels, unused outputs must be grounded.

DEFINITIONS OF INPUT LOGIC LEVELS*
Characteristic

High-Level Input Voltage (at any input)
Low-Level Input Voltage (at any input)
·The algebraic convention, where the most positive limit is designated maximum, is used with Logic Level Input Voltage Levels only.

ELECTRICAL CHARACTERISTICS (TA = 0 to +700 C unless otherwise noted I
Symbol

Characteristic##

High-Level Input Current (Logic Inputs)
(Vee = Max, VEE = Max, VIHL = 2.4 VI
(Vee = Max, VEE = Max, VI HL = Vee Max)

IIHL

Low-Level Input Current (Logic Inputs)
(Vee= Max, VEE = Max, VILL = 0.4 V)

IILL

High·Levellnput Current (Inhibit Input)
(Vee = Max, VEE = Max, VIHI = 2.4 V)
(Vee = Max, VEE = Max, VIH = Vee Max)

IIHI

Low-Level Input Current (Inhibit Input)

IILI

Min

Typ#

Max

Unit

-

-

40
1.0
-1.6

rnA

-

p.A
rnA

-

-

-

-

-

100

p.A

40
1.0
-1.6

p.A
mA
rnA

(Vee = Max, VEE = Max, VI LI = 0.4 V)
Output Current ("on" state)

mA

10(on)

(Vee = Max, VEE = Max)
(Vee = Min, VEE = Mini
10(0ff)

-

11
11
5.0

lee(onl

-

35

50

mA

IEE(on)

-

65

90

rnA

Supply Current from Vee (with driver inhibited)
IVI LL = 0.4 V, VI LI = 0.4 V)

lee(off)

-

35

50

rnA

Supply Current from Vee (with driver inhibited)

IEE(off)

-

25

40

rnA

6.5

Output Current ("off" state)

15

-

(Vee = Min, VEE = Min)
Supply Current from Vce (with driver enabled)

(VI LL = 0.4 V, VI HI = 2.0 V)
Supply Current fr~m Vee (with driver enabled)

(VI LL = 0.4 V, VI HI = 2.0 V)

(VI LL = 0.4 V, VI LI = 0.4 V)
#AII tvPical values are at Vee = +5.0 V, VEE = -5.0 V, TA = +250 e.
##For conditions shown as Min or Max, use the appropriate value specified under recommended operating
conditions for the applicable device type.
Ground unused inputs and outputs.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
7-91

MC3453·
SWITCHING CHARACTERISTICS (VCC

=+5.0 V, VEE = -5.0 V, TA =+250 C.1
Symbol
tPLHL
tPHLL
tPLHI
tPHLI

Characteristic
Propagation Delay Time from Logic Input to

Output Y or Z (RL

= 50 ohms, CL =40 pFI

Propagation Delay Time from Inhibit Input

to Output Y or Z (RL

= 50 ohms, CL =40 pFI

Min

Typ

Max

Unit

-

9.0
9.0

ns

16

17
17
25

20

25

ns

FIGURE 3 - INHIBIT INPUT TO OUTPUTS PROPAGATION
DELAY TIME WAVEFORMS

FIGURE 2 - LOGIC INPUT TO OUTPUTS PROPAGATION
DELAY TIME WAVEFORMS

3.0 V
INHIBIT
INPUT

OV

OUTPUT
y

50%

50%

OUTPUT Z

OV

TEST CIRCUITS
FIGURE 5 -INHIBIT INPUT TO OUTPUT PROPAGATION
DELAY TIME TEST CIR.CUIT

FIGURE 4 - LOGIC INPUT TO OUTPUT PROPAGATION
DELAY TIME TEST CIRCUIT
Vcc

Ern to Scope

= +5.0 V

Vcc = +5.0 V

Output

to

50
3
50

y

SCOPT --+_~!.....-,

2

40 pF
(total)

4

I

Z ~-""'~>-(J,.j

~

MC3453

tTHL

"'10n:-f Y
Output

to
Scope

Z
50
8

9

VEE
=-5.0

V
1k
Channel A shown under test, the other
channels are tested similarly.

Channel A shown under test, the other

channels are tested sim ilarlv.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
7-92

MC3453

FIGURE 6 - CIRCUIT SCHEMATIC

1114 Circuit Shown)

--------------------1----------------------------------I

I

Vee

Vee

I
I
I

I
I
I

I
I
I
I

I
I
COMMON

INHIBIT

I

COMMON
LEVEL SET

I
I

I
I

VEE
o----+-----------------+-----+-----+--~--~

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
7-93

MOTOROLA

-

MC3467

SEMICONDUCTOR - - - - - -

TECHNICAL DATA

TRIPLE MAGNETIC TAPE
MEMORY PREAMPLIFIER

TRIPLE WIDEBAND PREAMPLIFIER
WITH ELECTRONIC GAIN CONTROL (EGC)

SILICON MONOLITHIC
INTEGRATED CIRCUIT

The MC3467 provides three independent preamplifiers with in·
dividual electronic gain control in a single lB·pin package. Each pre·
amplifier has differential inputs and outputs allowing operation in
completely balanced systems. The device is optimized for use in 9·
track magnetic tape memory systems where low no ise and low dis·
tortion are paramount objectives.
The electronic gain control allows each amplifier's gain to be set
anywhere from essentially zero to a maximum of approximately
100V/V.
• Wide Bandwidth -15 MHz (Typ)
• Individual Electronic Gain Control
• Differential Input/Output

P SUFFIX
PLASTIC PACKAGE
CASE 707

PIN CONNECTIONS

TYPICAL APPLICATION
HIGH PERFORMANCE 9-TRACK OPEN REEL
TAPE SYSTEM
NRZI!4>
VI(EGC)

Select
Active
Differentiator
Input {

4

Input {

7

T
A

P
E

Formatter
MC8500
MC8501
MC8502
MC8520

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
7-94

MC3467

MAXIMUM RATINGS (T A = 25°C unless otherwise noted.l
Rating

Symbol

V.lue

Negative Supply Voltage

VCC
VEE

6.0
-9.0

EGC Voltages (Pins 1,6 and 13)

Power Supply Voltages
Positive Supply Voltage

Unit
V

VIIEGC}

-5.0 toVCC

V

Input Differential Voltage

VIO

±5.0

V

Input Common-Mode Voltage

VIC

±5.0

V

Amplifier Output Short Circuit
Duration ho Ground)

tse

10

s
°c

Operating Ambient Temperature Range

TA

o to +70

Storage Temperature Range

T stg

-65 to +150

aC

TJ

+150

°c

Junction Temperature

ELECTRICAL CHARACTERISTICS (VCC ~ 5.0 V, VEE = -6.0 V, f = 100 kHz, TA
Characteristic

=0 to +700 C unless otherwise noted.)

Symbol

Min

Typ

Max

Unit

VCCR
VEER
VIIEGCI

4.75
-5.5
0

5.0
-6.0

-

5.25
-7.0
VCC

V
V
V

AVO

B5

100

120

V/V

AVO

-

0.6

2.0

V/V

VIOR

0.2

-

-

Vpp

VOR

6.0

B.O

-

Vpp

Power Supply Voltage Range
Positive Supply Voltage

Negative Supply Voltage
Operating EGC Voltage
Differential Voltage Gain (Balanced)

(V IIEGC)

=0, ei =25 mVp-p}

(See Figure 1)

Differential Voltage Gain

(VIIEGC)

= VCC}

Maximum Input Differential Voltage

(Balanced) (T A

=25°C)

Output Voltage Swing (Balanced) (Figur. 1)
(ei =200 mVp·p)
Input Common-Mode Range
Differential Output Offset Voltage

(TA

=25°C)

Common-Mode Output Offset Voltage

(TA

=25°C I

Common Mode Rejection Ratio (Figure 2)

VIIEGC} = 0, VCM
(f = 100 kHz)
(t = 1.0 MHz)

VICR

±1.S

'2.0

VOOO

-

500

-

mV

VOOC

-

500

-

mV

60
40

100
100

10

15

-

CMRR

V

dB

= 1.0 Vpp

Small-Signal Bandwidth (Figure 11
(-3.0 dB, ei = 1.0 mVp-p, T A = 25°C)

BW

MHz

Input Bias Current

liB

-

5.0

15

"A

Output Sink Current (Figure 5)

lOS

1.0

1.4

mA

en

-

3.5

-

"VRMS

Positive Power Supply Current (Figure 4)

ICC

40

mA

lEE

-

30

Negative Power Supply Current (Figure 4)

-30

-40

mA

ri

12

25

kn

Ci

-

2.0

-

Differential Noise Voltage Referred to Input (Figure 3)

(VIIEGC)

=0, RS =50 n, BW = 10 Hz to 1.0 MHz, TA =25°C}

Input Aesistance
Input Capacitance

= 250 CI
ITA = 250 Cl

(TA

Output Resistance (Unbalanced)

(TA

ro

=25°C)

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

7-95

30

pF
Ohm.

MC3467

FIGURE 1 - DIFFERENTIAL VOLTAGE GAIN,
BANDWIDTH AND OUTPUT VOLTAGE SWING
TEST CIRCUIT
(Channel A under test, other channell tested limilarly.

FIGURE 2 - COMMON-MODE REJECTION RATIO
(Channel A under tost, other amplifiers tostod Ilmllarly)

5.0 V

5.0 V
18

18

17

17

"I

16

t-l_6o-_.... VOO

"2

= 81

80

MC3467

CMRR
-

82

MC3467

13

~

20 log 1100
AV VI

13
"".20 log

=
10

10

-6.0V

-6.0 V

FIGURE 3 - DIFFERENTIAL NOISE VOLTAGE
REFERRED TO THE INPUT

FIGURE 4 - POWER SUPPLY CURRENT TEST CIRCUIT

vcc
5.0 V

KrohnHlta
3202
Filter

51

51
hp
3400A

Low Pass
Assume Uncorrelated Noise Sources
en (Differential Noise at Input) '"

80

-6.0 V

Filter With
BW" 1.0 MHz

v'2/100

FIGURE 6 - TOTAL HARMONIC DISTORTION
TEST CIRCUIT
(Channel A under test, other channels tested similarly)

FIGURE 5 - OUTPUT SINK CURRENT TEST CIRCUIT
(Channel A under test, other channels tested similarly)
+5.0 V

+2.0 V

5.0 V

-6.0 V

-6.0 V

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

7-96

Voo

100 VI

MC3467

TYPICAL CHARACTERISTICS
(VCC = 5.0 V. VEE = -6.0 V. TA = 25 0 unless otherwise noted)
FIGURE 7 - TOTAL HARMONIC DISTORTION (THO)
versus INPUT VOL TAGE

FIGURE 8 - NORMALIZED VOLTAGE GAIN
versus FREQUENCY

p

.s,p

l

z

ffi

8, U

Q

~
t;;

o

6.0

u

Z

Q

4,0

"

~

g...

2,0

~.

...

0
50

-

~

-5,0

Z
Z

-1 0

'"w

-1 51--

....... r--

/

V

L

lL

~

Q

1
..l

200

250

I 1111111

-2

5

~: ~t~Hil-

1 1 1lllili'l

'"

50

111111/

1111111

-3 0
0,1

tt1:""
Jill

1.0

10

100

t, FREaUENCY IMHz)

VI, INPUT VOLTAGE ImVp.p)

FIGURE 9 - NORMALIZED VOLTAGE GAIN
versus AMBIENT TEMPERATURE

~

Vi= 1.0mV pp

-2 01- Av Inom,l = 20 log A

>

150

1'\

;;:

'"

f-"""
100

I'

Q

(See Figure 6)

~
..

l"-

N

::;
Av" 30
VIIEGC) = 1.8 V
II = 100 kHz

Q

FIGURE 10 - NORMALIZED POSITIVE POWER SUPPLY
CURRENT yersus POSITIVE POWER SUPPLY VOLTAGE

1.

1.04

ffi
N

VEE = -6,0 V

..

::; 1.02'1---+--+--1- VI = 10 mV R
II = 100 kHz

~

~
z

;;:

0

'"w
'"

.

VEE - 6,OV
TA=250C
_
ICC If)
n = ICC 125°C) - t - -

r--

~

Q

>

8

1

T~ST CIRlCUIT ={'GUR~ 4

.[

0,9 6
4.75

4,8

...

i

~-

4,95

5,0

5,05

5,1

5,15

5,2

FIGURE 12 - NORMALIZED POWER SUPPLY CURRENTS
versus AMBIENT TEMPERATURE

1.04

1.0 2

1.02

"'w
"'N

~~

4,9

FIGURE 11- NORMALIZED NEGATIVE POWER SUPPLY
CURRENT yersus NEGATIVE POWER SUPPLY VOLTAGE

~c

~~

4,85

1.00

~~
~ 0.9 8
ffi

----

l-- V

z

;
0,96
-5,0

-5,5

-6,0

V r-

-

1

V
/"

0

VCC=5,OV
fA = 25°C
lEE If)
n = lEE 1250C)

LLJ

TEST CIRCUIT = FIGURE 4

u
u

-6,5

5,25

VCC, POSITIVE POWER SUPPLY VOLTAGE IVdc)

TA,AMBIENT TEMPERATURE 10C)

V

-7,5

VCC = 5,0 V
VEP -6,0 V
ICC If)
lEE IT)
n = ICC 1250C) = lEE 125'Cj-

/"

SEE FIGUIRE 4 _
FOt TEST CIIRCUIT

0.9
9/

0,9 8
7,0

L-- t---

o

10

20

30

40

50

TA,AMBIENT TEMPERATURE lOCI

VEE, NEGATIVE POWER SUPPLY VOLTAGE IVdc)

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

7-97

60

70

80

MC3467

FIGURE 14 - COMMON-MODE REJECTION RATIO
(CMRRlversu. FREQUENCY

FIGURE 13 - DIFFERENTIAL VOLTAGE GAIN .,.,..u.
ELECTRONIC GAIN CONTROL VOLTAGE (VUEGCII
100

c

\

0

5
iilw

.
.

g

\

0

'\

"-

c

>

o

0.5

1.0

t--

§
1\

o

1.5

2.0

z
c

--

8

~~

Vo
_ CMRR = 20 log AV VICM
AV=100VN=40dB
TEST CIRCUIT' FIGURE 2

VICM = 1.0 Vp•p

-40

1!i

3.0

2.5

VCC =5.0 V
VEE = -S.O V

-6 Of-- TA = 250C

3.5

4.0

f. FREQUENCY (MHz)

FIGURE 16 - TYPICAL EGC INPUT CURRENT versu.
EGC INPUT VOLTAGE

FIGURE 15 - PHASE SHIFT versus FREQUENCY

4.0

-r-.

;(

-4 0
~

w

.g
....

I\.

~ -80

~

'\

ffl
c

t"-12 0

~ -16 0
~
'"<> -20 0

3.0

V
./

a

~

\

;;;

~--

U

~

-240

10

1.0

/

,/

o

o

100

../

VCC = 5.0 V
VEE = -S.OVTA = 25°C

2.0

3.0

VI(EGCI. EGC INPUT VOLTAGE (Vdcl

REPRESENTATIVE CIRCUIT SCHEMATIC
1/3 MC3467

I"putt

Dl
RI

Input

D2

VEE

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
7-98

f---

./

1.0

f. FREQUENCY (MHzl

EGC

~-.

.,/

u

EL..

v

/'

2.0

'"w

1.0

100

10

1.0

0.1

VlfEGC). ELECTRONIC GAIN CONTROL VOLTAGE (VOLTSI

-300
0.1

I"-

~ -80

\

0

.

........

~-10 0

"-1\

4.0

5.0

MOTOROLA

-

MC3469

SEMICONDUCTOR - - - - - -

TECHNICAL DATA

FLOPPY DISK WRITE CONTROLLER

FLOPPY DISK

WRITE CONTROLLER
The MC3469 is a monolithic WRITE Current Controller designed
to provide the entire interface between floppy disk heads and the
head control and write data signals for stradle-erase heads.
Provisions are made for selecting a range of accurately controlled write currents and for head selection during both read
and write operation. Additionally, provisions are included for
externallY'adjusting degauss period and inner/outer track
compensation.
I»

SILICON MONOLITHIC
INTEGRATED CIRCUIT

Head Selection - Current Steering Through Write Head and
Erase Coil in Write Mode

• Provides High Impedance (Read Data Enable) During Read
Mode

-

• Head Current (Write) Guaranteed Using Laser Trimmed Internal
Resistor (3.0 mA using Rext = 10 kO)
• IRW Select Input Provides for Inner/Outer Track Compensation

1

• Degauss Period Externally Adjustable
• Specified With ± 10% Logic Supply and Head Supply (VBB)
from 10,8 V to 26.4 V

P SUFFIX
PLASTIC PACKAGE
CASE 648

• Minimizes External Components
• See Application Note AN917 for Further Information

PIN CONNECTIONS

BLOCK DIAGRAM

R WI R W2

Center

Vref

16

Tap 1

6

Iref
Toggle
Select

WD

4

13
11

Select

IRWS

8

Enable

Current
Select

14
16

WG
Eij
E1

CT0

cn

9

Vref

I,ef

15

VBB

Gnd

3

14

Center
Tap 55

Write
Gate

4

13

Erase 55

5

12

Coil
Gnd

R/W2

6

11

&aSe1

R/W1

7

10

VCC

IRW
Select

8

9

Head
Select

Write

Data

HS

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

7-99

2

MC3469

MAXIMUM RATINGS (TA = 25°C)
Symbol

Value

Unit

Power Supply Voltage (Pin 101

Vee

7.0

Vdc

Power Supply Voltage (Pin 151

VBB

30

Vdc

VI

5.75

Vdc

Tstg

-55 to +150

°e

TJ

150

°e

Rating

Input Voltage (Pins 4, 5, 8, 91
Storage Temperature
Operating Junction Temperature

RECOMMENDED OPERATING CONDITIONS
Rating

Symbol

Value

Unit

Power Supply Voltage (Pin 101

Vee

+4.5 to +5.5

Vdc

Power Supply Voltage (Pin 151

VBB

+10.8 to +26.4

Vdc

TA

o to +70

De

Operating Ambient Temperature Range

ELECTRICAL CHARACTERISTICS (TA=Oto+70oe, Vee= 4.5 to 5.5 V, VBB= 10.8 to 26.4 V unless otherwise noted. Typicalsgiven
for Vee = 5.0 V, VBB = 12 V and TA = 25°e unless otherwise noted.1
Characteristics

DIGITAL INPUT VOLTAGES
Power Supply eurrent - Vee
VBB

lee
IBB

-

22
15

50
30

mA

High Level Input Voltage
(Vee = 4.5 VI

4,8,9

VIH

2.0

-

-

V

Low Level Input Voltage

4,8,9

VIL

-

-

0.8

V

4,5,8,9

VIK

-

-0.87

-1.5

V

5

VT(+I

1.5

1.75

2.0

V

5

VT(_I

0.7

0.98

1.3

V

0.2
0.4

-

-

0.76

-

-

0.1

40

-

-

-1.6

0.36
0.76
0.46
0.39

-

(Vee = 5.5 VI
Input elamp Voltage
(lIK=-12 mAl
Positive Threshold

(Vee = 5.01
Negative Threshold
(Vee = 5.01
Hysteresis (VT(+I- VT(-II
TA = ooe to +70 oe
TA = 25°e

V

VHTS

DIGITAL INPUT CURRENTS
High Level Input Current

4,5,8,9

IIH

4,5,8,9

IlL

p.A

(Vee = 5.5 V, VBB = 26.4 V, VI = 2.4 VI
Low Level Input Current

(Vee = 5.5 V, VBB = 26.4 V, TA = 25°e unless
noted belowl
VBB = 12 V
V8B = 24 V
Vee = 5.0 V
Vee= 5.0V

4
4
5
8,9

mA

-

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

7-100

-

-

MC3469

ELECTRICAL CHARACTERISTICS (continued) (T A = 0 to+70oe, Vee = 4.5 to 5.5 V, VBB = 10.8 to 26.4 V unless otherwise noted.
Typicals given for

Vee;;

5.0 V. VBB;;; 12 V and TA;:' 25°C unless otherwise noted.)

Characteristics

Symbol

CENTER-TAP and ERASE OUTPUTS
Output High Voltage (See Figure 91
(lOH = -100 rnA. Vee =4.5 VI
VBB = 10.8 to 26.4 V

14,16

VOH

Output Low Voltage (See Figure 9)

14,16

VOL

V
VBB-l.5

(IOl = 1 .0 mAl
VBB= 12V
VBB = 24 V
I 1,13

IOH

11,13

VOL

mV

-

Output High Leakage

VBB-l.0

-

70
70

150
150

-

0.Q1

100

-

0.27
0.27

0.60
0.60

I'A

(VOH = 24 V, Vee = 4.5 V, VBB = 24 VI
Output low Voltage (See Figure 101
(IOl = 90 rnA, Vee = 4.5 VI
VBB = 12 V
VBB = 24 V

V

CURRENT SOURCE
Reference Voltage

1

Vref

-

5.7

-

V

Degauss Voltage (See Text)

I

VOEG

-

1.0

-

V

(Voltage Pin 1 - Voltage Pin 21
Bias Voltage
Write Current Off Leakage

-

2

VF

-

0.7

6,7

IOH

-

0.03

15

I'A

6,7

Vsat

-

0.85

2.7

V

6,7

LlIIRW2, 1

-

15

40

I'A

2.91
2.84

3.0

3.09
3.16

5.64
5.51

5.89

-

6.14
6.28

31.3
30.3

33.3
33.3

35.5
36.6

V

(VOH = 35 V)
Saturation Voltage

(VBB = 12 VI
Current Sink Compliance

(For V6, 7 = 4.0 V to 24 V, VWG = 0.8 VI
6,7

Average Value Write Current

(IPin 6 + IPin 71
(
2
for VBB = 10.8 to 26.4 VI
@ IR/W = ILOW, R = 10k

rnA

IR/W(ll

TA= 25°e
TA = 0 to +70 oe
@ IR/W = ILOW, R = 5.0 k
TA = 25°e
TA = 0 to +70 oe
@ IR/W= IHI, R = 10 k (lHI = ILOW+ % IlOwl
TA = 25°e
TA = 0 to +70 oe

-

%

-lIR/W(HI

6,7

Difference in Write Current

(1lPin 6 -IPin 71
@ IR/W = IlOW, VBB = 10.8 V to 26.4 VI
R= 10k
TA = 25°e
TA= 0 to +70 oe
R = 5.0 k
TA = 25°e
TA = 0 to +70 oe

IR/W-l

rnA

-

0.003

-

-

0.015
0.023

-

-

0.030
0.046

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
7-101

MC3469
AC SWITCHING CHARACTERISTICS (VCC= 5.0V. TA = 25°C. Vee= 24 V.IRWS = 0.4 and IR/W= 3.0 mA unless otherwise noted
- refer to Figure 2 and Figure 11.)
C~(Notel)

fin (Note 3)

Min

Typ

Ma.

Unit

1. Delay from Head Select going low through 0.8 V to CTO
going high through 20 V.

HS. Pin 9

-

1.6

4.0

"s

cn

HS. Pin 9

-

2.1

4.0

",

3. Delay from Head Select going high through 2.4 V to CTO
going low through 1.0 V.

HS. Pin 9

-

1.7

4.0

"s

cn

HS. Pin 9

-

1.4

4.0

"s

5. Delay from WG going low through 0.8 V to CTO
going low through 1.0 V.

WG. Pin4

-

1.3

4.0

"s

cn

WG. Pin4

-

0.8

4.0

"s

7. Delay from WG going low through 0.8 V to CTO
going high through 20 V.

WG. Pin4

-

0.75

4.0

"s

WG. Pin4

-

1.2

4.0

"s

WG. Pin4

20

750

-

ns

10. After
goes high. delay from R/Wl turning off
through 10% to cn going low through 1.0 V.

WG. Pin4

20

1200

-

ns

11. After WG goes high. delay from R/W2turning off
through 10% to CTO going low through 1.0 V.

WG. Pin4

20

1200

-

ns

12. After WG goes high. delay from R/W2turning off
through 10% to cn going high through 20 V.

WG. Pin4

20

600

-

ns

13. Delay from WG going low through 0.8 V to EO
going low through 1.0 V.

WG. Pin4

-

0.085

4.0

"s

14. Delay from WG going low through 0.8 V to El
going low through 1.0 V.

WG. Pin4

-

0.085

4.0

"s

15. Delay from WG going high through 2.0 V to EO
going high through 23 V.

WG. Pin4

-

0.7

4.0

"s

16. Delay from WG going high through 2.0 Vto El
going high through 23 V.

WG. Pin4

-

0.7

4.0

"s

17. AfterWG goes low. delay from CTOgoing low through
1.0 V to R/Wl turning on through 10%.

WG. Pin4

20

750

-

ns

18. After WG goes low. delay from cn going low through
1.0 V to R/W2 turning on through 10%.

WG. Pin4

20

750

-

ns

2. Delay from Head Select going low through 0.8 V to
going low through 1.0 V.

4. Delay from Head Select going high through 2.4 V to
going high through 20 V.

6. Deley from WG going low through 0.8 V to
going high through 20 V.

8. Delay from iN(; going low through 0.8 V to
going low through 1.0 V.

cn

9. After iN(; goes high. delay from R/Wl turning off
through 10% to CTO going high through 20 V.

m

19. After WG goes low. faUtime (10% to 90%) of R/Wl.

WG. Pin4

200

WG. Pin4

-

5.0

20. After WG goes low. faUtime (10% to 90%) of R/W2.

5.0

200

ns

21. Setup time. Head Select going low before
iNG going low.

WG. Pin4

4.0

-

-

"s

22. Write Data low Hold Time

WD. Pin5

200

23. Write Data high Hold Time

WD. Pin5

500

-

-

24. Delay from WG going high through 2.0 V
to R/W 1 turning off through 10% of on value.

WG. Pin4

-

3.9

-

Notes 1. Test numbers refer to encircled numbers In Agure 2.
2. AC teat waveforms applied to the designated pins as follows:
Pin

fJn

Amplitude

Duty Cycle

HS. PinS
WG.Pln4
Wii. Pin 6

50kHz
50kHz
1.0 MHz

0.4to2.4V
0.4 to 2.4V
0.2to2.4V

50%
50%
60%

3. Test numbers refer to encircled numbers in Figure 4.
lin = 1.0 MHz, 50% Duty Cycle and AmplHude of 0.2 V to 2.4 V.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

7-102

ns

ns
ns
"s

MC3469
AC SWITCHING CHARACTERISTICS (continued)
(VCC = 5.0 V, TA = 25°C, Vaa = 24 V, WG = 0.4 unless otherwise noted - refer to Figure 3 and Figure 11.)
Min

Typ

Max

Unit

-

85

-

ns

2. Delay skew, difference of R/WI turning off and R/W2
turning on through 50% after Write Data going low
through 0.9 V.

-

1.0

±40

ns

3. Delay from Write Data going low through 0.9 V to R/WI
turning off through 50%.

-

80

-

ns

4. Delay skew, difference of R/WI turning on and R/W2
turning off 50% after Write Data going low
through 0.9 V.

-

1.0

±40

ns

5. Rise time, 10% to 90%, of R/WI

-

1.7

200

ns

6. Rise time, 10% to 90%, of R/W2

-

1.7

200

ns

12

200

ns

12

200

ns

Characteristics (Note 3)

1. Delay from Write Data going low through 0.9 V to R/WI
turning on through 50%.

7. Fall time, 90% to 10%, of R/WI
8. Fall time, 90% to 10%, of R/W2

PIN DESCRIPTION TABLE
Symbol

Pin

Description

Head Select

HS

9

Head Select input selects between the head 1/0 pins: center-tap, erase, and read/write. A HIGH
selects Head 0 and a LOW selects Head 1.

Write Gate

WG

4

Write Gate input selects the mode of operation. HIGH selects the read mode, while LOW selects
the Write Control mode and forces the write current.

Write Data

WD

5

Write Data input controls the turn on/off of the write current. The internal divide·by·twoflip-flop
toggles on the negative going edge of this input to direct the current alternately to the two
halves of the head coils.

IRWSelect

IRWS

8

IRW Select input selects the amount of write current to be used. When LOW, the current equals
the value found in Figure 5, according tathe external resistor. When HIGH, the current equals
the low current + 33%.

Vref
Iref

Vref
Iref

1
2

A resistor between these pins sets the write current. Laser trimming reliably produces 3 rnA of
current for a 10 k resistor. A capacitor from Vref to Gnd will adjust the Degauss period.

Center-tap 0

CTO

14

Center-tapOoutput is connected to the center tap of HeadO.lt will be pulled to Gnd orVaa (+12 or

EO

13

Erase 0 will be LOW for writing on Head 0, and floating for other conditions.

CT1

16

Center-tap 1 output isconnectedtothe center tap of Head 1. It will be pulled to Gnd orVBB (+12 or
+24) depending on mode and head selection.

Name

+24) depending on mode and head selection.
Erase 0
Center-tap 1

E1

11

Erase 1 will be LOW for writing on Head I, and floating for other conditions.

R/W2

R/W2

6

R/W2 input is one of the differential inputs that sinks current during writing, being the opposite
phase of R/WI. It will be connected to one side of the heads.

R/WI

R/WI

7

R/W1 input is one of the differential inputs that sinks current during writing, being the opposite
phase of R/W2. It will be connected to one side of the heads.

VCC

10

+5 V Power

Vaa

15

+12 Vor+ 24 V Power

Gnd

12

Coil grounds

Gnd

3

Reference and logic ground

Erase 1

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
7-103

MC3469
FIGURE 1 - LOGIC OIAGRAM

Write

VBB

VCC

15

10

3

12

1 1 th

~

Data

Write

Gate 4

)--=.:=--_ _ E0'
-"'.rt-"~

t----J

./

13

)..:C'----_~Ef
11

'>--I-__~ 1;---Q--,---o ~~1
CT0

14

Head

select·9--?--------------------4------------------------------~

"""External Component

oc - open collector

FIGURE 2 -

AC TIMING OIAGRAM

Head 9

Select

2.0V

Write 4 - - " = =
Gate

2.0V
O.BV

~~~5---r---+---=~1

eTiI

en
Eil13-------+-+---------------+--------~~4_~------~~h

R/Wl

7

-----=-'-':1

R/W2 6 _ _ _ _

~"-..u.

__'"'

10%

Vref
(5.0V Nom.)

~:~~ ~~It~~~n 0~ _____-1-0.85 V Nom.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

7-104

MC3469

R/W1 AND R/W2 RELATIONSHIP

FIGURE 3 Write Data

5
2.4 V
0.9V _ _ _ _
0.2 V

R/W1

7

r

6
10%
50%

---l::@

:!I-®

90%

~(i)

f®



50 0

'"

40 0
5
~ 30 0

Pin 2

;j

VP2 = 0.7 V

/

20
10

/
/

0/

~l/

20

10

DEGAUSS PERIOD

FIGURE 8 - TURN-ON WRITE PROTECTION

Rextr:r=:l
1

2700PF~
I
5.0%

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

7-106

30
(~sl

MC3469

TEST FIGURES
FIGURE S - CENTER TAP OUTPUT VOLTAGE
(PINS 14 AND 161
CONDITIONS
Measure

Sot

VT

Sij, S2
VT

4.5 V

51

52

53

V4"

VS"

VOH (P141

On

Off

P14

O.B
2.0

O.B

VOH (P16)

On

Off

P16

VOL (P14)

Off

On

P14

2.0
O.B

~

100 rnA

=-

1.0 rnA

VOL(P16)

Off

On

P16

2.0
2.0
O.B

O.B
2.0

O.B

2.0

O.B
2.0

O.B

2.0

"Va Its

FIGURE 10 - ERASE OUTPUT LOW VOLTAGE
(PINS 11 AND 131

CONDITIONS
Sot

Measure

VT
VOL(Pll)

51
Pl1

VB.S
O.BV

VOL(P131

P13

2.0V

FIGURE 11 - TIMING TEST CIRCUIT
+5.0 V ±5%

+24 V ±5%

100

24 k

24 k

O.lT T 10
I'F

= = I'F

240
2.0W
AC
Inputs

2702.0W

1-<'--+----""'(1,-- +24 V
50

See Specification
Table and Note 3.

50

Notes:
Diodes Type 1 N4934.
Resistors (unless otherwise noted) are 114 W. 5%.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

7-107

MC3469

ERASE CURRENT
Erase timing is provided internally and is active during
Write Gate low for the selected head.

The value of RE, the erase current set resistor, is found
by referring to Figure 12 and selecting the desired erase
current.
Looking atthe simplified erase current path in Figure 12,
when writing, CTOwili be high (VOH(minl= 21 VI and EO
will be low(VOL(maxl=0.6 VI. If the erase coil resistance
is 100 and 40 rnA of erase current is desired, then:

FIGURE 12 - ERASE CURRENT
(RE Selection I

(RE + 1001 x 40 mA= (21 -0.61 V

RE

13

EO
or
RE
PD

=

20.4 V
0.0"4 A - 10 0

"

MC3469

=500 0

CTO
14

=(0.041 (20.41 =0.816 Wor 1.0 W

This gives the minimum value REforworstcase VOH/VOL
conditions. It is also recommended that a diode be used as
required for inductive back emf suppression.

FIGURE 13 - TYPICAL DUAL HEAD FLOPPY DISK SYSTEM USING
FET GATE READ CHANNEL SELECTION AND MC3469/MC3470
MC3470

:

0:

r--------....,

..~~--.,...---i:-1l'" - - :

Read Data

I

(out)

L________ J
Read Amp
See Data Sheet

r------,
I

I
From
Head Select :
I
Logic
IL _____
..-II
I

HI

t

VBB
RD

I

I

VCC

I
I
I
I
I

RD

I

R/W2

I

l ___{

R/Wl

VBB
HS

CTO
CTI

TrackComp

EO
TI

Write Data (inl

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

7-108

Digital

f'

~
~

Erase

Coil

MOTOROLA

-

MC3470
MC3470A

SEMICONDUCTOR - - - - - -

TECHNICAL DATA

FLOPPY DISK
READ AMPLIFIER SYSTEM

FLOPPY DISK READ AMPLIFIER
The MC3470 is a monolithic READ Amplifier System for obtaining digital information from floppy disk storage. It is designed to
accept the differential ac signal produced by the magnetic head
and produce a digital output pulse that corresponds to each peak
of the input signal. The gain stage amplifies the input waveform
and applies it to an external filter network, enabling the active
differentiator and time domain filter to produce the desired
output.

SILICON MONOLITHIC
INTEGRATED CIRCUIT

• Combines All the Active Circuitry To Perform the Floppy Disk
Read Amplifier Function in One Circuit
• Guaranteed Maximum Peak Shift of 2.0% -

MC3470A

-

• Improved (Positive) Gain Te and Tolerance
• Improved Input Common Mode
• See Application Note AN917 for Further Information

1

P SUFFIX

PLASTIC PACKAGE
CASE 707

TYPICAL APPLICATION
Filter Network

Active
Oifferentiator

PIN CONNECTION

Amplifier

Inputs

Offset
Decoupling

Gnd

One-Shot
Components
Mono #1

8

Analog Inputs

Geln Select

Mono #1

Mono #2

One-Shot
{
Components
Mono #2
9

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
7-109

Data
Output

MC3470, MC3470A
MAXIMUM RATINGS (TA=25°C)
Symbol

Value

Unit

Power Supply Voltage (Pin 11)

Rating

VCCI

7.0

Vdc

Power Supply Voltage (Pin 18)

VCC2

16

Vdc

Input Voltage (Pins 1 and 2)

VI

-0.2 to +7.0

Vdc

Output Voltage (Pin 10)

Vo

-0.2 to +7.0

Vdc

Operating Ambient Temperature

TA

Oto +70

°c

Tstg

-65 to +150

°c

TJ

150

°c

Symbol

Valua

Unit

VCC

VCCI + 4.75 to +5.25
VCC2 +10 to +14

Vdc

TA

Oto +70

°c

Storage Temperature
Operating Junction Temperature

Plastic Package

RECOMMENDED OPERATING CONDITIONS
Rating
Power Supply Voltage
Operating Ambient Temperature Range

ELECTRICAL CHARACTERISTICS (TA = Oto +70oC, VCCI = 4.75 to 5.25 V, VCC2 = 10to 14 V unlass otherwise noted)
Characteristic

Differential Voltage Gain
(f = 200 kHz, ViD = 5.0 mV(RMS)

MC3470
MC3470A

Figure

Symbol

Min

Typ

Max

Unit

2

AVO

80
100

100
110

130
130

V/V

118

-

-10

-25

p.A

viCM

-0.1

-

1.5

V

viD

-

-

25

mVp-p

vciD

3.0

4.0

-

8.0

-

Vp-p

10
lOS

2.8

4.0

mA

Small Signal Input Resistance (TA = 25°C)

r;

100

250

-

Small Signal Output Resistance, Singla-Ended
(TA = 25°C, VCCI = 5.0 V, VCC2 = 12 V)

ro

-

15

-

11

2,17

BW

10

-

-

MHz

5

CMRR

50

-

-

dB

VCCI Supply Rejection Ratio (TA = 25°C, VCC2 = 12 V,
4.75';;; VCCI .;;; 5.25 V, AVO = 40 dB)

-

50

-

-

dB

VCC2 Supply Rejection Ratio (TA = 25°C, VCCI = 5.0 V,
10 V.;;; VCC2';;; 14 V, AVO = 40 dB)

-

60

-

-

dB

Diffarential Output Offset (TA = 25°C, viD = Yin = 0 V)

VDO

0.4

V

VCO

-

-

Common Mode Output Offset (ViD = Yin = 0 V,
Differential and Common Mode)

3.0

-

V

en

-

15

-

I'V(RMS)

ICCI
ICC2

-

40
4.8

-

3

Input Bias Current
Input Common Mode Range Linear Operation

(5% max THO)
Differential Input Voltaga Linear Operation
(5% max THO)
Output Voltage Swing Differential

2

Output Source Current, Toggled
Output Sink Current, Pins 16 and 17

Bandwidth,.-3.0 dB (Vi 0 = 2.0 mV(RMS), TA = 25°C
VCCI = 5.0 V, VCC2 = 12 V)
Common Moda Rejection Ratio (TA = 25°C, f = 100 kHz,
AVO =40 dB, Yin = 200 mVp-p, VCCI = 5.0 V,
VCC2 = 12 V)

Diffarential Noise Voltage Referred to Input
(BW = 10Hz to 1.0 MHz, TA = 25°C)
Supply Currents
(VCCI = 5.25 V, SI to Pin 12 or Pin 13)
(VCC2 = 14 V)

4

22
1

-

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
7-110

mA

kll

mA

MC3470, MC3470A

ELECTRICAL CHARACTERISTICS (continued) (TA = Oto+70oC, VCC1 =4.75to 5.25 V, VCC2 = 10to 14 Vunless otherwise noted)
Characteristic

Typ

ACTIVE DIFFERENTIATOR SECTION
Differentiator Output Sink Current, Pins 12 and 13

6

IOD

7,8

PS

1.0

1.4

-

rnA

(VOD = VCC1)
Peak Shift (f = 250 kHz, vi D = 1.0 Vp-p, icap = 500 ~A,
where PS= 112 tPS1- t PS2 x 100%,
tps, + tpS2

MC3470

VeC1 = 5.0 V, VCC2 = 12 V)

MC3470A

%

-

-

5.0
2.0

Differentiator Input Resistance. Differential

riD

-

30

-

kfl

Differentiator Output Resistance, Differential

roD

-

40

-

fl

(TA = 25°C)
DIGITAL SECTION
Output Voltage High Logic Level, Pin 10 (Vee1 = 4.75 V,
VCC2 = 12 V, IOH = -0.4 rnA)

9

VOH

2.7

-

-

V

Output Voltage Low Logic Level. Pin 10 (VCC1 = 4.75 V,
VeC2 = 12 V, IOL = 8.0 rnA)

10

VOL

-

-

0.5

V

Output Rise Time, Pin 10

, 1. 12

tTLH

-

-

20

ns

Output Fall Time, Pin 10

11. 12

tTHL

-

-

25

ns

13

t1A, B

500

-

4000

ns

12,13

Et 1

85

-

115

%

Timing Range Mono #1 (t1A and t1 B)
Timing Accuracy Mono #1

(t1 = 1.0 ~s = 0.625 R 1C1 + 200 ns)
(R1 = 6.4 kfl, C1 = 200 pF)
Accuracy guaranteed for R1 in the range

1.5 kfl":; R1 ,,:; 10 kfl and C1 in the range
150pF":; C1":; 6BOpF.
Note: To minimize current transients, C1 should
be kept as small as is convenient.
Timing Range Mono #2

11,12

t2

150

-

1000

ns

Timing Accuracy Mono #2

12,13

Et 2

85

-

115

%

(t2 = 200 ns = 0.625 R2C2)
(R2 = 1.6 kfl, C2 = 200 pF)

Accuracy guaranteed for 1.5 kfl
100 pF ,,:; C2 ,,:; BOO pF

~

R2 ~ 10 kil.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

7-111

MC3470, MC3470A
MC3470 CIRCUIT SCHEMATIC

Gain
Stage

16

' -.....-+--017

4

30-------------'

40 k

4k

1.33 k

1.33 k
Active
Differentiator
and
Peak
Detector

15 k

15 k

14o-~--~------_t======~====~--__l
15O-~~--------_L

13

o--------------f--.......

12 O'---------j----ir--------+

6

9

10

Digital
Section

Q Cr-----------------~
'-----/0

0

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

7-112

MC3470, MC3470A

FIGURE 1 - POWER SUPPL V CURRENTS.
ICCI AND ICC2

-

18

FIGURE 2 - VOLTAGE GAIN. BANDWIDTH.
OUTPUT VOLTAGE SWING

18

VCC2

2

17

vo17
vo16

VCC2

2

17

3

16

3

16

4

15

4

15

5

14

ICC2

AV

13

12

8

11

9

10

-

Vee,
pF

ICC1

8

11

9

10

1.6 k

1.6 k

6.4 k

6.4 k

18

18
17

17
3

16

3

4

15

4

15

14

5

14

6

13

13

16

200 pF

12

12

8

11 t---t--<>VCCI

9

10

Vee1

FIGURE 4 - AMPLIFIER OUTPUT SINK CURRENT.
PINS 16 AND 17

FIGURE 3 - AMPLIFIER INPUT BIAS CURRENT. liB

7

vin

13

6

5,

12

6

vo16 - vo17
c

14

8

11

pF

10

1.6 k

1.6 k

6.4 k

6.4 k

MOTOROLA LINEAR/INTERFACE IC5 DEVICE DATA
7-113

---lOS

MC3470, MC3470A

FIGURE 5 - AMPLIFIER COMMON MODE
REJECTION RATlO,CMRR

FIGURE 6 - DIFFERENTIATOR OUTPUT SINK CURRENT,
PINS 12 AND 13

18

18

VCC2

2

17

vo17

2

3

16

Yo16

3

16

4

15

vin

-= -=

4

15

5

14

6

13

CMRR = 20 10910

vo16 - vo17
100 vin

17

14

f= 100kHz

13

6

vin = 200 mVpp

200pF
12

12

pF

8

11

9

10

VCCI

8

11

9

10

1.6 k

1.6 k

6.4 k

6.4 k

NOTE: Measurements may be made with vector voltmeter hp
8405A or equivalent 8t 1.0 MHz to guarantae 100 kHz
performance.

FIGURE 7 - PEAK SHIFT, PS

FIGURE B - PEAK SHIFT, PS

See Figure 8 for Output Waveform

VI"

= 1.0 Vpp

f

= 250 kHz

Test schematic on Figure 7
18

VCC2

17
3

16

4

15

V out
Pin 10

14
13
12
11

9

10

m

250 kHz

~ "~'."
1 k

8

t Jl

1.5V
f

6

51

VCCI

-= -=

R2
1.6 k

2.4 k

Rl
6.4k
5V

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
7-114

VCC2

MC34701, MC3470A

FIGURE 9 - DATA OUTPUT VOLTAGE HIGH. PIN 10

18

FIGURE 10 - DATA OUTPUT VOLTAGE LOW. PIN 10

VCC2

18

17

2

17

3

16

3

16

4

16

4

15

5

14

6

14

6

13

':"

':"

6

13
200 pF

200pF
12
8

11

9

10

Vee1

7

12

8

11

9

10 r-r-------~--_oVout

200 pF

200 pF
V out

~400"A
1.6 k

1.6 k

':"

6.4 k

6.4 k

FIGURE 11 - DATA OUTPUT RISE TIME. tTLH
DATA OUTPUT FALL TIME. tTHL
TIMING ACCURACY MONO IR.. Et2

FIGURE 12 - TIMING ACCURACY. Et1 AND Et2
DATA OUTPUT RISE AND FALL TIMES. tTLH AND tTHL
Vin shown on Figure 13

Vin 1. same as shown on Figure 13. test schematic on Figure 12

18
2.7 V -----~r_
V out
Pin 10

I--- '2 --

20

30

40

50

r-....

60

N

c
w
:::;

1.00

c

0.98

.il:i
.
z

....- ~
.............
~

Z

:;.

0.96

10

..... i---"""'"
.....--r""

c

70

0.96
10

80

20

30

40

50

60

TA, AMBIENT TEMPERATURE (DC)

TA, AMBIENT TEMPERATURE (DC)

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
7-116

70

80

MC3470 MC3470A
1
"

FIGURE 17 - PHASE AND NORMALIZED VOLTAGE
GAIN versus FREQUENCY

II

z

;;:

'"w~
~
o

-

1. 0

~

,. 1.04

Gain

~c

r-- t-... ...... I-t

>

N

O.9

1/

I"-

PhasB

"

\'

z

Q

?;; o.7

fil

N

ffi

60

~ 1.00

e

::E

:;

~

80
100

1.0 2

;::

m

40

~

~ 0, 8

o

w
::E

20

:::l

~

FIGURE 18 - NORMALIZED TIME DELAY
tl versus TEMPE RATU R E

"s:,;

r-

z

r§ 0.9 B

~
~

0.96

0.8
200 kHz

1.0 MHz
f, FREQUENCY

10MHz

10

80

See Figure 14 Switch Position R

:z:

z

61.04

f=!50kHZ

1.04

;;:

3:
w

w

~

1.02

~

I

AVA = 2V~~t IR)

'"

~

Rext '" 500 n

1.02

o

~

>

fil

:::l

:::l

~
~ 0.9 8

fil

01.00

1.0 0

N

"

N

~

70

FIGURE 20 - NORMALIZED VOLTAGE GAIN,
AVR/AVR 25 0 C

FIGURE 19 - NORMALIZED OUTPUT PULSE WIDTH,
t2/t2 25 0 C

iE

50
60
20
30
40
TA, AMBIENT TEMPERATURE IOC)

0.9 8

o

-"

~O.9 8

" 0.9 8

z

z

-=>
10

20
30
50
80
40
TA, AMBIENT TEMPERATU RE IOC)

70

10

80

20

30

40

50

80

70

80

TA, AMBIENT TEMPERATURE IOC)

FIGURE 21 - EFFECTIVE EMITTER RESISTANCE
DISTRIBUTION, PINS 3 AND 4

FIGURE 22 - DIFFERENTIAL NOISE VOLTAGE
VCC2

0

I--S~' Figure 114

18

Pin 3 or4
0

3.3 k

O~

W W

17
3.3 k

'/

Krohn-Hita
3202 Filter

~ W ~W

0.01
I'F

0

16
4

15

Low Pass
Filter with
f2"" 1.0 MHz

14
5.0V

-=6

13

0
12

10

40
50
80
20
30
TA, AMBIENT TEMPERATURE IOC)

70

80

6.4 k
8

11

9

10

1---0---- V CCI

NOTE: Assume uncorrelated noise sources
an (differential noise at input) = ao~2/' 00

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
7-117

hp 3400A
RMS
Voltmeter

MC3470, MC3470A

APPLICATION INFORMATION
The MC3470 is designed to accept a differential ac
input from the magnetic head of a floppy disk drive and
produce a digital output pulse that corresponds to each
peak of the ac input. The gain stage amplifies the input
waveform and applies it to a filter network (Figure 23a),
FIGURE 23. - BLOCKING CAPACITORS USED TO
ISOLATE THE DIFFERENTIATOR
16

C

14
MC3470

Filter

Oifferentiator

2
C'

15

enabling the active differentiator and time domain filter
to produce the desired output.
FILTER CONSIDERATIONS
The filter is used to reduce any high frequency noise
present on the desired signal. Its characteristics are dic·
tated by the floppy disk system parameters as well as the
coupling requirements of the MC3470. The filter design
parameters are affected by the read head characteristics,
maximum and minimum slew rates, system transient
response, system delay distortion, filter center frequency,
and other system parameters. This design criteria varies
between manufacturers; consequently, the filter con·
figuration also varies. The coupling requirements of the
MC3470 are a result of the output structure of the gain
stage and the input structure of the differentiator, and
must be adhered to regardless of the filter configuration.
The differentiator has an internal biasing network on
each input. Therefore, any dc voltage applied to these
inputs will perturbate the bias level. Disturbing the bias
level does not affect the waveform at the differentiator
inputs, but it does cause peak shifting in the digital output
(Pin 10). Since the output of the gain stage has an associ·
ated dc voltage level, it, as well as any biasing introduced
in the filter, must be isolated from the differentiator via
series blocking capacitors. The transient response is mini'
mized if the blocking capacitors C and C' are placed
before the filter as shown in Figure 23a. The charging and
discharging of C and C' is controlled by the filter termina·
tion resistor instead of the high input impedance of the
differentiator.
The filter design must also include the current·sinking
capacity of the amplifier output. The current source in
the output structure (see circuit schematic -Pins 16
and 17) is guaranteed to sink a current of 2.8 mAo If the
current requirement of the filter exceeds 2.8 rnA, the cu~
rent source will saturate, the output waveform will be
distorted, and inaccurate peak detection will occur in
the differentiator. Therefore, the total impedance of the

filter must be greater than Zmin as calculated from
Zmin =

(EpAVD) max
2.8mA

where Ep is the peak differential input voltage to the
MC3470.
TRANSIENT RESPONSE
The worst-case transient response of the read channel
occurs when dc switching at the amplifier input causes its
output to be toggled. The dc voltage changes are a consequence of diode switching that takes place when control
is transferred from the write channel to the read channel.
If the diode network is balanced, the dc change is a
common mode input voltage to the amplifier. The switching of an unbalanced diode network creates a differential
input voltage and a corresponding amplified swing in the
outputs. The output swing will charge the blocking
capacitor resulting in peak shifting in the digital output
until the transient has decayed. Eliminating the differential
dc changes at the amplifier input by matching the diode
network or by coupling the read head to the amplifier via
FET switches, as shown in Figure 23b, will minimize the
filter transient response.
FIGURE 23b - FET SWITCHES USED TO COUPLE THE R/W
HEAD TO THE MC3470
Power
2N5460
.....--.--+--,
r--.-_

R/W
Head

Write

Two of the advantages FET switches have over diode
switching are:
1. They isolate the read channel from dc voltage
changes in the system; therefore, the transient
response of the filter does not influence the system
transient response.
2. The low voltage drop across the FETs keeps the
input signal below the amplifier's internal clamp
voltage; whereas, the voltage dropped across a diode
switching network adds a dc bias to the input signal
which may exceed the clamp voltage.
AMPLIFIER GAIN
For some floppy systems, it may become necessary
to either reduce the gain of the amplifier or reduce the

See Application Note AN917 for further information.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
7-118

MC3470, MC3470A

signal at the input to avoid exceeding the output swing
capability of the amplifier. The voltage gain of the ampli·
fier can be reduced by putting a resistor in series with
the capacitor between Pins 3 and 4 (Figure 14). The
relationship between the gain and the external resistor is
given by
2 (re+ Re)
AVR = AVO ": 2 (re + Re) + Rext

crossing detection of the current waveform. Since the
capacitor shifts the current 90 0 from the input voltage,
the comparator performs peak detection of the input
voltage.
The following terms will be used in determining the
value of C to be used in the differentiator:
Ep ~ peak differential voltage applied to MC3470
amplifier input.
Ep sin wt ~ voltage waveform applied to MC3470
amplifier input (for purposes of discussion,
assume a sine wave).

where AVO ~ voltage gain with the external resistor = 0,
AVR ~ voltage gain with the external resistor in,
Rext ~ the external resistor, and
re + Re ~ the resistance looking into Pin 3 or Pin 4.

AVO ~ differential voltage gain of input amplifier.
Vin(t) ~ differential voltage waveform applied to the
differentiator inputs.

Thus,

= EpAvosin wt (Note: The filter is assumed to

Rext = 2 ('!'VO - 1) (re + Re).
\AVR

be lossless.!
ic!t) ~ current through capacitor CD.

A plot of (re + Re) versus temperature is shown in
Figure 21. Figure 20 shows the normalized voltage gain
versus temperature with the external resistor equal to
500 ohms.

RO fl output resistance of 01 (02) at Pin 12 (13).
If Vin(t) = EpAVDsin wt, then the current through the
capacitor Co is given by
ic(t)

ACTIVE OIFFERENTIATOR
The active differentiator in the MC3470 (simplified
circuit shown in Figure 24), is implemented by coupling

and VO(t)

-

The MC3470 current·sourcing capacity will determine
the maximum value ic; therefore, CD must be chosen such
that the maximum ic occurs at the maximum AVOEpw
product.
1 mA
Co = _
icmax
(AVDEpw)max (120)(E pw)max

13

ic(t)

If the peak value specified for ic is exceeded, the
current source (10 in Figure 24) will saturate and distort
the waveform at Pins 12 and 13. Consequently, the
differentiator will not accurately locate the peaks and
peak shifting will occur in the digital output.
The effective output resistance RO of 01 (02) will
create a pole (as shown in Figure 25) at 1/2 ROCO. If
this pole is ten times greater than the maximum operating
frequency (wmax), the phase shift approaches 84 0 .
Locating the pole at a frequency much greater than
10 wmax needlessly extends the noise bandwidth thus:

the emitters of a differential amplifier with a capacitor
resulting in a collector current that will be the derivative
of the input voltage,

1= Cdv/dt
If the output voltage is taken across a resistor through
which the collector current is flowing, the resulting volt·
age will be the derivative of the input voltage.

2RO

dv' (t)
dt
Va is applied to a comparator which will provide zero
Va

= 2RCCDAVDEpwcoswt.

Accurate zero crossing detection of Volt) [peak
detection of vin(t)] occurs when the current waveform
ic!t) crosses through zero in a minimum amount of time.
This condition is satisfied by maximizing current slew
rate. For a given value of w, the maximum slew rate
occurs for the maximum value of ic or coswt = 1. There·
fore,

FIGURE 24 - ACTIVE DIFFERENTIATOR NETWORK

12

= CDAVDEpwcoswt

= 2Ric = 2RC-In-

=

1
.
Co 10 wmax

If RO is not large enough to satisfy this condition, a series

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
7-119

MC3470, MC3470A
Using this value for L gives:

FIGURE 25 - RESPONSE OF DIFFERENTIATOR
USING ONLY CD

RCD
6 = _-::-2-~J~C~D==
1.0

CD(wmaxl2

Solving for R gives:

R = ::-:---=-6__
5CD W max
The total resistance (R I is the effective output resis·
tance (ROI plus the resistor added in the differentiator
(RD). Values of 6 from .0.3 to 1 produce satisfactory
results.
1

W max 2R Co

PEAK SHIFT CONSIDERATIONS
Peak shift, resulting from current imbalance in the
differentiator, offset voltage in the comparator, etc., can
be eliminated by nulling the current in the emitters of
the differentiator with a potentiometer as shown in
Figure 27.

resistor can be added so that
R = 2RO + R D =

1
.
CD 1.0 wmax

To further reduce the noise bandwidth, a second pole
can be added (as shown in Figure 261 by putting an

FIGURE 27 - PEAK SHIFT COMPENSATION

FIGURE 26 - COMPLETE RESPONSE OF DIFFERENTIATOR

20 k to 50 k

10 k

The potentiometer across the differentiator components
is adjusted until a symmetrical digital output cycle is
obtained at Pin 1.0 for a sinusoidal input with the minimum anticipated Epw product.

1

w max "'LOCo

inductor in series with the resistor and the capacitor.
The values of Rand L are determined by choosing the
center frequency (wol and the damping ratio (6 I to meet
the systems requirements where

DESIGN EQUATIONS FOR ONE·SHOTS
As shown in Figure 28, the MC347D input waveform
may have distortion at zero crossing, which can result in
false triggering of the digital output. The time domain
filter in the MC347D can be used to eliminate the distor·
tion by properly setting the period (q I of the one·shot
timing elements on Pins 6 and 7. The following equation
will optimize immunity to this signal distortion at zero
crossing of the read head signal.
The timing equation for the time domain filter's one·
shot is:
q = R1C1Kl +To

wo=_I-

v'LCo

6 = RCD

2v'LCD
Wo= 1Dwmax=_I-

v'LCo

where CD is chosen for maximum ic as shown previously.
Solving for L gives:
L=

where K1 = .0.625, To = 2.0.0 ns.
Actual time will be within ±15% of tl due to variations
in the MC347D.
If .t.T is the maximum period of distortion (see Figure

.

1
IDa CD(w max l 2

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

7-12.0

MC3470, MC3470A

FIGURE 28 - WAVEFORMS THROUGH THE REAO CIRCUIT

~:~!I~\·:nal -LC\
__-1~\_ _a~TIL.IC\_~\Jr-_--;.-=£\<------''---_
Vo (Differential
Output Voltage

T

=='

~

/\\

r\

~

r-J

--~~--~ITI~\--~
/~'T'~~

aT
I I
I I
I I
I I
I

I

'--..-/

aT

Ii

I I
I I
I I
I

I

Comparator
Output

Output of

One-Shot (t,)

Time Domain

Filter Ouput

Digital
Output

28), then choose !1 such that

the manufacturer, the coupling of signals or noise between
external wires is under the control of the end·user who
designs the integrated circuit into a piece of equipment.
The designer should be familiar with the following layout
procedures which will optimize the performance of the
device. See Figure 29.

l1T-----------1

WD

>-------1

IRWS

>-----+--+---1

RD

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

7·129

MC3471
APPLICATION INFORMATION
The MC34 71 P serves as a complete interface between
the Write Control functional signals (Head Select. Write
Data. Write Gate and inner track compensation. IRWSI

Figure 7. Degauss Period shows the relationship
between COG and Degauss Period for Rext = 10 kn. This
period is equal tothe exponential delay time for the voltage

and the head itself. A typical configuration is shown in
Figure 4. LE's are erase coils.

as mentioned pius internal delay times.
FIGURE 6 - SIMPLIFIED DEGAUSS CIRCUIT

WRITE CURRENT SELECTION

vBB

Although the MC3471 P has been specified for 3.0 mA
write current (with a 10 kfl external resistor I. a range of
write current values can be chosen by varying Rext using
the plot in Figure 5. This current can also be derived using

the relationship IWrite (mAl = __3_0__
Rext(kfll

to Internal
Logic

'Ref' the current flowing in Rext (required only for dissipation calculations) can be worst case using the fact
that the differential voltage between Pins 1 and 2 (VRef)
shown in Figure 3 never exceeds 5.0 volts. With a low
value of Rext = 1.0 kn, PD = 25 mW.

Pin 2
Vp2=0.7V

FIGURE 5 - WRITE CURRENT versus Rext

0"
0

I~

IRWS low

FIGURE 7 - DEGAUSS PERIOD versus
CAPACITANCE (CDGI

100 0

.0

~

K

5. 0

1"-

0

~

0

1. 0

V

I"-

2.0

3.0

co

/

c

'" ~

7.0
10
5.0
EXTERNAL SET RESISTOfI - Rext Ikill

20

..
ti
w

'-'
z

50 0
40 0

II

« 30 0

30

j

20 0
10 0

Referring to Figure 4. resistors RD are used to dampen
any ringing that results from applying the relatively fast
risetime write current pulse to the inductive head load.
Values chosen will be a funciton of head characteristics
and the desired damping. Rp serves as a common pullup
resistor to the head supply VBB.

10

20

30

OEGAUSS PERIOD (psi

POWER-UP WRITE CURRENT CONTROL
During power-up, under certain conditions (VBB
comes up first while WG is low), there can be a write
current transient on Pins 6 and 7 (R!W1 and R!W2) of
sufficient magnitude to cause writing to occur if the
head is loaded.
This transient can be eliminated by placing a capacitor
from Pin 2 to ground. This also delays the write current
when WG goes low and this delay must be accounted
for when the capacitor on Pin 2 is used. The delay is 3.0
p..s for a 2700 pF capacitor, and Rext = 10 kn. Values
up to 7000 pF may be used.

DEGAUSS PERIOD
Degauss of the read/write head can be accomplished at
the end of each write operation by attaching a capacitor
from Pin 1 to ground. The time relationship that results is
shown in Figure 7. A simplified diagram of this function is
shown in Figure 6.
While WG is low. the selected write current flows into
Pin 6 or Pin 7 (R/Wl or R/W21 and is mirrored through the
external resistor. Rext. The degauss capacitor. COG. will
be chargedto approximately 5.7volts. After WG goes high.
the voltage on COG begins to decay toward 0.7 V. When
the voltage reaches the comparator threshold of 1.7 V. the

1

Rext~L-

comparator output triggers the internal logic to completely

turn off the write current. At this point. the pulse amplitude
on the R/Wl and R/W2 pinS has returned to 10% of its
maximum value.

I

1

011

WRITE CURRENT DAMPING

I
Rex!:;: 10 k!l I - - -

I

r---

-

I

2700 pF
5.0%

~

I

See Application Note AN917 for further information.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

7-130

________M
__
C_34_7_1________

~

MC3471

ERASE DELAY
The MC3471 P can be used with both straddle and
tunnel erase heads. When using the tunnel erase heads,
it is necessary to delay the erase current in time with
respect to WG due to the physical placement of the
erase gap behind the RIW gap on the heads. The amount
of delay required depends upon the disk rotation velocity, recording density and format. Turn-on delay and
turn-off delay must also be independent to guarantee
erase is on for the entire block.
Nominal delays of 500 /LS turn-on; and 1.0 ms turnoff are available by adjusting the value of Rl, R2 and
Cl, C2 shown in Figure 4_ These delays are adjustable
over a broad range as shown in Figure 9 to achieve any
practical delay required_ By using 5% capacitors and 1%
resistors, total timing accuracy is better than ± 15% over
temperature and supply. Timing is shown in Figure 10.
In applications using logic or microprocessor controlled delays, the 01 and 02 inputs can be used directly
to turn-on and turn-off the erase current. (Controlling
outputs should be Open-collector wll0 k pullup)_ Figure
11 shows the relative timing involved for the microprocessor and logic controlled applications.
In straddle erase systems, the erase delays can be
eliminated by pulling 01 and 02 high thru a 10 kO pullup
resistor to + 5_0 V.

This gives the minimum value RE for worst case VOH'
VOL conditions. It is also recommended that a diode be
used as indicated for inductive back emf suppression.
FIGURE 10 - DELAY INPUT FUNCTION/TIMING
WITH RC ELEMENTS
WG - - - ,
,'I....-._ _ _

I

---!

01

_

Turn-On

Delay

-

02
Turn-Off_
Delay

Eil or

_(Erase)

E1

FIGURE 11 - DELAY INPUT FUNCTION/TIMING
WITH LOGIC CONTROL

-

FIGURE 9 - TYPICAL WG TO Ee, 1 DELAY versus RC
2.0
1.5

f--

td = kRC ±O.09RC

01

. / '"

1.2
k=I

V

0.5

02

V
O. 2
0

-

-

_

Turn-On
Delay

Turn-Off_
Delay

Eil or

3DkOO<;RO<;300kO

0.5

1.2

1.0

1.5

2.0

-

0.63 Vee

V
0.2

1\

0.63 Vce

_(Erase)_

E1

td

ERASE CURRENT
The value of RE, the erase current set resistor, is found
by referring to Figure 12 and selecting the desired erase
current.
Looking at the simplified erase current path in Figure
12, when writing, CT0 will be high (VOH(min) =
22.5 V) and E0 will be low (VOL(max) = 0.6 V). If the
erase coil resistance is 100 and 40 mA of erase current
is desired then:

FIGURE 12 - ERASE CURRENT
IRE Selection I

19
VBS

+24V
17

RE

Erase
Coil

MC3471

(RE + 100) x 40 mA = (22.5 -0_6) V
or
eT0~--o------------O------J

R = 21.9V - 100 = 5370
E
0.04A

Po

18

= (537) (0.04)2 = 0.86 W

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
7-131

MC3471

FIGURE 13 - TYPICAL DUAL HEAD FLOPPY DISK SYSTEM USING
FET GATE READ CHANNEL SELECTION AND MC3471/MC3470A

:

D:

MC3470A

r------ --,

:
1

HO

- - -

I

L________ J
Read Amp
See Data Sheet

Hl

t

VSS
RO
VCC
RD
R/W1VSS

HS

---{

CTO

Write Gate

CT1

IRW

EO
E1

TrackComp

Write Data lin)
Erase

MC3471

02
VRel IRel

Delays

Inhibit

-=
Function
Write 0
Write 1
Read 0
Read 1

CT.

CTl

E8

El

Vee
OV
OV
Vee

OV
Ves
Vee
OV

On
Off
Off
Off

Off
On
Off
Off

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
7-132

Digital

~ Read Data
(out)

MC3471

TEST FIGURES
FIGURE 14 - CENTER TAP OUTPUT VOLTAGE
(PINS 1 BAND 20)

10k

CONDITIONS
Measure

Set

VT

30 k
111--'v'.1y-....
30 k

51

52

53

VOH (P18)

On

Off

P 18

VOH (P20)

On

Off

P20

VOL (P18)

Off

On

PIB

VOL (P20)

Off

On

P 20

10 k

--L 3

18

0.8V~4

17

2.0 V 0--- 5

16

2.0 V 0

12 V

2.0
O.B

O.B

0.8

2.0

2.0

2.0

0.8

O.B

2.0

Set
51

V13

VOL (P15)

P15

0.8V

VOL (P17)

P17

2.0 V

VT

14

8

13

9

12 r--'VW-~---0 Driver Output

20k
(Diodes are MM07000 or eqUivalent)

50 pF'

• Load Capacitance shown includes
Fixture and Probe Capacitance

Driver Application

Table

1/0

1

Select-Out

VOH

3.11 V

3.9 V

Input Frequencv

5MHz

1 MHz

100 ns

500 ns

o V to 4 V

o V to 4 V

Input Pulse Width
Input Amplitude
Input tTLH

~6

ns

~

Input tTHL

~6

ns

';6 ns

50

Load Resistance (RLl

tTLH

6 ns

90

tTHL

4.0V
90%

Input

13V
10%

OV

90%
PW.

1.3V
10%
Normal
Operation

tpLHID)
tpLHIDS)
Driver Output

tPLHIF)
tPLHIF-S)

1

Driver
Short
Circuit
Operation

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
7-137

MC3481, MC3485

FIGURE 2 -

MC3485 AC TEST CIRCUIT AND WAVEFORMS

+5.0 V
RL

~

2.0 k

(All Diodes are MMD7000 or equivalent)

Table
P--~r---'----1---o

Driver Application

2

Driver Output

+5.0 V

1/0
3.11 V

3.9 V

Input Frequency

5 MHz

1 MHz

Input Pulse Width

CL

~

50 pF*

2.0 k

Input Amplitude

1-----

x>----------i-<>

J: CL

* Load Capacitance shown includes

Fault Flag Output
~ 50 pF*

Fixture and Probe Capacitance

'TLH

100 ns

500 ns

o V 10 4 V

o V 10 4 V

Input tTLH

~6

ns

-:;;6 ns

Inpu"THL

<;;;6 ns

-.:;6 ns

50

90

Load Resistance (RLl

*See Table 2

ITHL

4.0V----Input

o V _ _ _ _---JI
IpLH(DI
'pLH(DSI
Normal
Operation

Driver Output

IpHL(Bsl-t-~---l

'pHL(DI

Driver Output

l

Drtver
Short
Circuit
Operation

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

7-138

Select· Out

VOH

-

MOTOROLA

SEMICONDUCTOR -

_ _ _ __

MC3486

TECHNICAL DATA

QUAD EIA-422/423 LINE RECEIVER
Motorola's Quad EIA-422/3 Receiver features four independent
receiver chains which comply with EIA Standards for the Electrical
Characteristics of Balanced/Unbalanced Voltage Digital Interface
Circuits. Receiver outputs are 74LS compatible, three-state structures which are forced to a high impedance state when the appropriate output control pin reaches a logic zero condition. A PNP
device buffers each output control pin to assure minimum loading
for either logic one or logic zero inputs. In addition, each receiver
chain has internal hysteresis circuitry to improve noise margin
and discourage output instability for slowly changing input waveforms. A summary of MC3486 features include:
• Four Independent Receiver Chains
• Three-State Outputs
• High Impedance Output Control Inputs
(PIA Compatible)
• Internal Hysteresis - 30 mV (Typ) @ Zero Volts Common Mode

QUAD EIA-422/3 LINE RECEIVER
WITH THREE-STATE
OUTPUTS
SILICON MONOLITHIC
INTEGRATED CIRCUIT

LSUFFIX
CERAMIC PACKAGE
CASE 620

D SUFFIX
PLASTIC PACKAGE
CASE 7518
(SO·16)

• Fast Propagation Times - 25 ns (Typ)
• TTL Compatible
• Single 5.0 V Supply Voltage

P SUFFIX
PLASTIC PACKAGE
CASE 648

• DS 3486 Provides Second Source

PIN CONNECTIONS
RECEIVER CHAIN BLOCK DIAGRAM

Inputs
A

Three-State
Differential

Control

Inputs

Input

Output

Output

Inputs
B

A
3-5t8t8
Control

Output

Ale

B

3-8t8t8

Output

e
Inputl

e
Inputs
D

ORDERING INFORMATION
Device

Temperature Range

MC3486P
MC3486D

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

7-139

Package
Ceramic DIP

MC3486L
Oto +70'C

Plastic DIP
SO-16

MC3486
MAXIMUM RATINGS
Symbol

Rating
Power Supply Voltaga

VCC
VICM
VID
VI

Input Common Mode Voltage
Input Differential Voltaga
Three·Stata Control Input Voltage
Output Sink Current

10
T stg
TJ

Storage Temperature
Operating Junction Temperature

Value
8.0
±15
±25
8.0
50
-65 to +150

Unit
Vdc
Vdc
Vdc
Vdc
rnA

°c
°c

+175
+150

Ceramic Package

Plastic Package

RECOMMENDED OPERATING CONDITIONS
Symbol

Value

Unit

Input Common Mode Voltage Range
Input Differential Voltage Range

VICR
VIDR

4.75 to 5.25
o to +70
-7.0 to +7.0
6.0

Vdc

Operating Ambient Temperature

VCC
TA

Rating
Power Supply Voltage

°c
Vdc
Vdc

ELECTRICAL CHARACTERISTICS (Unless otherwise noted minimum and maximum limits apply over recommended temperature
and power supply voltage ranges. Typical values are for TA = 25°C, VCC = 5.0 V and VIK = 0 V.
See Note 1 )
Symbol

Min

Input Voltage - High Logic State
(Three·State Control)

Characteristic

VIH

2.0

Input Voltage - Low Logic State
(Three·State Control)

VIL

-

Differential Input Threshold Voltage, Note 2
(-7.0 V", VIC'" 7.0 '.J, VIH = 2.0 V)
(10 = -0.4 rnA, VOH '" 2.7 V)
(10 = 8.0 rnA, VOL'" 0.5 V)

VTH(D)

Input Bias Current
(VCC = 0 V or 5.25) (Other Inputs at 0 V)
(VI = -10V)
(VI = -3.0 V)
(VI = +3.0 V)
(VI = +10V)

IIB(D)

Output Third State Leakage Current
(VUD) = +3.0 V, VIL = 0.8 V, VOL
(VUD) = -3.0 V, VIL = 0.8 V, VOH
Output Short·Circuit Current
(VUD) = 3.0 V, VIH = 2.0 V, Vo

V

0.8

V

-

0.2
-0.2

-

-3.25
-1.50
+1.50
+3.25

--

V

-

-

VOH
VOL

2.7

-

-

0.5

10Z

-

-

-40
40

-

-100

rnA

-

-

-100

pA

-

--

lOS

-15

Note 4)

Input Current - Low Logic State (Three·State Control)
(VIL = 0.5 V)

IlL

Input Current - High Logic State (Three·State Control)
(VIH = 2.7 V)
(VIH = 5.25 V)

IIH

Input Clamp Diode Voltage (Three·State Control)
(11K = -10 rnA)

VIK

-

ICC

-

Power Supply Current
(VIL = 2.0 V)
NOlES:
1.
2.
3.
4.

Unit

-

rnA

---

= 0.5 V)
= 2.7 V)

= 0 V,

Max

-

V

--

Input Balance and Output Level
(-7.0 V '" VIC'" 7.0 V, VIH = 2.0 V, Note 3)
(10 = -0.4 rnA, VID = 0.4 V)
(10 = 8.0 rnA, VID = -0.4 V)

Typ

pA

pA
20
100
-1.5

V

85

rnA

All currents into device pins are shown as positive, out of device pins are negative. All voltages referenced to ground unless otherwise noted.
Differential input threshold voltage and guaranteed output levels are done simultaneously for worst case.
Refer to EIA-42213 for exact conditions. Input balance and guaranteed output levels are done simultaneously for worst case.
Only one output at a time should be shorted.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

7-140

MC3486

SWITCHING CHARACTERISTICS (Unless otherwise noted VCC = 5 0 Vend TA = 25 0 C )
Characteristic

Symbol

Min

Typ

tpHUD)
tpLH(D)

-

-

-

35
30

tpLZ
tPHZ
tpZH
tpZL

-

-

35
35
30
30

Max

Unit

Propagation Deley Time - Differential

ns

Inputs to Output

(Output High to Low)
(Output Low to High)

Propagation Delay time - Three-State

ns

Control to Output

(Output
(Output
(Output
(Output

Low to Third State)
High to Third State)
Third State to High)
Third State to Low)

FIGURE 1 - SWITCHING TEST CIRCUIT AND WAVEFORMS
Propagation Delay Differential Input to Output

To Scope

To Scope

(Input)

(Output)

3.00v~n~1.5V
tPLHCO;=r

Inputs

vOH

51

V
and Stray
Capacitance)

-~-

-J-;:

tpLHCO)

--+,---.

Output

OL

OV----------Input Pulse Characteristics
= tTH L = 6,0 ns (10% to 90%)
PRR::::I 1.0 MHz, 50% DutY Cycle

tTLH

+1.5V

+2.0V

FIGURE 2 - PROPAGATION DELAY THREE-STATE CONTROL INPUT TO OUTPUT
To Scope
(I nput) 3-State

Input Pulse Characteristics
tTLH:; tTHL = 6.0 ns (10% to 90%)
PRR"" 1.0 MHz, 50% Duty Cycle

To Scope
(Output)

Pulse
Generator

SWI

2.0 k

+5.0 V

~~~--~~----~--~--4r--~~--r-~

+1.5 V for t PHZ and tpZH
-1.5 V for tPLZ and tpZL

CL=15pF
(Includes

I

Probe and Stray

=

All Diodes 1 N916 or
Equivalent

5.0 k

Capacitance)

tpLZ
Input

3.0 V

3'OV~
1.5 V
1.5 V
av - -

--., r-

Eln

oV

SW1 Closed
tpLZ

SW2 Closed

--

0.5V
-l-;p~;

VOH
E out
~1.3V

- --0 V

3'OV~
Input
1.5 V .1.5 V SW1

1.5 VI SW1 Closed
SW2 Closed

~
lIo:::
~
Z

"".3V~

Output

VOL

- -

-

----- - - - - - ---OV
tpZL

3.0 V
Input

Open

OV~--tp~~2CIOS.d

PZL

~

"'6.0 V - VSE---

VOH

Output

1.6 V

1.6 V

VOL

OV---

--------OV

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

7-141

MOTOROLA

-

MC3487

SEMICONDUCTOR - - - - - -

TECHNICAL DATA

QUAD EIA-422 LINE DRIVER
WITH THREE-STATE
OUTPUTS

QUAD LINE DRIVER WITH
THREE-STATE OUTPUTS

SILICON MONOLITHIC
INTEGRATED CIRCUIT

Motorola's Quad EIA-422 Driver features four independent
driver chains which comply with EIA Standards for the Electrical
Characteristics of Balanced Voltage Digital Interface Circuits. The
outputs are three-state structures which are forced to a high
impedance state when the appropriate output control pin reaches
a logic zero condition. All input pins are PNP buffered to minimize
input loading for either logic one or logic zero inputs. In addition,
internal circuitry assures a high impedance output state during
the transition between power up and power down. A summary
of MC3487 features include:

L SUFFIX

CERAMIC PACKAGE
CASE 620

D SUFFIX

PLASTIC PACKAGE
CASE 751B
ISO-16)

• Four Independent Driver Chains
• Three-State Outputs
• PNP High Impedance Inputs (PIA Compatible)
• Fast Propagation Times (Typ 15 ns)

P SUFFIX

PLASTIC PACKAGE
CASE 648

• TTL Compatible
• Single 5 V Supply Voltage
• Output Rise and Fall Times Less Than 20 ns
• DS 3487 Provides Second Source

PIN CONNECTIONS

Input A

Outputs

DRIVER BLOCK DIAGRAM

I.

1

15

A{~

vcc
Input D

::} Outputs 0

AlB Control 4

12 C/D Control

Outputs B {:
::} Outputs C

Input B 7

9

Gnd 8

Input

Input C

Outputs

TRUTH TABLE
Inverting

Control

Non-Inverting

Inverting

Input

Input

Output

Output

H

H

H

L

L

H

L

H

L

Z

Z

X

L = Low Logic State

= High Logic State
= Irrelevant
Z = Third·State (High
H

X

MOTOROLA LlNEARIiNTERFACE ICs DEVICE DATA

7-142

Impedance)

MC3487

MAXIMUM RATINGS
Roting
Power Supply Voltage

Symbol

Value

Unit

Vee

8.0

Vdc

Input Voltage

VI

5.5

Vdc

Operating Ambient Temperature Range
Operating Junction Temperature Range
Ceramic Package
Plastic Package
Storage Temperature Range

TA

o to +70

°e
°e

TJ
175
150
-65 to +150

T otg

°e

ELECTRICAL CHARACTERISTICS IUnless otherwise noted specifications apply 4.75 V .. Vee" 5.25 V and oOe .. TA .. 700 e.
Typical values measured at Vee = 5.0 V, and T A : : : 2So C.J

Characteristic
Low Logic State

Input Voltage

Symbol

Input Voltage - High Logic State

VIH

Input Current

IlL

Low Logic State

Min

TVD

Mox
0.8

Unit

2.0

-

-

Vdc

-400

"A

VIL

Vdc

IVIL = 0.5 VI

Input Current - High Logic State

IIH

IVIH = 2.7 VI
IVIH = 5.5 VI

Input Clamp Voltage
0IK=-18 mAl

Output Voltage - Low LogiC State

-

-

-

+50
+100

VIK

-

-1.5

V

VOL

-

-

0.5

V

VOH

2.5

-

-

V

lOS

-40

-

-140

rnA

-

-

-

.100
.100

-

-

+100
-100

-

.0.4

-

.0.4

(lOL =48mAI
Output Voltage - High Logic State
(lOH = -20 mAl

Output Short-Circuit Current
(VIH

= 2.0 V, Note 11

Output Leakage Current - Hi·Z State

10L(ZI

(VIL = 0.5 V, VILIZI = 0.8 VI
(VIH = 2.7 V, VILIZI = 0.8 VI

Output Leakage Current - Power OFF

10LIoffl

IVOH = 6.0 V, Vee = 0 VI
IVOL = -0.25 V, Vee = 0 VI
Output Offset Voltage Difference INote 21
Output Differential Voltage (Note 2)
Output Differential Voltage Difference (Note 2)

"A

-

VOS-vOS

"A

-

-

VOO

2.0

IdVODI

-

"A

V
V
V

Power SupplV Current
(eontrol Pins
(Control Pins

mA

= Gnd, Note 3)
= 2.0 V)

leex

-

-

105

ICC

-

-

85

Notes: 1. Only one output may be shorted at a tima.
2. See EIA Specification EIA-422 for exact test conditions.
3. Circuit in three·state condition.

SWITCHING CHARACTERISTICSIVee = 5 0 V TA = 25°C unless otherwise noted)

Characteristic
Propagation Delay Times
High to Low Output
Low to High Output
Output Transition Times - Differential
High to Low Output
Low to High Output
Propagation Delay ContrOl to Output

Symbol

Min

Typ

Max

tpHL
tPLH

-

-

20
20

tTHL
tTLH

-

-

20
20

-

-

25
25
30
30

Unit
ns

ns

ns

(RL = 200 n, CL = 50 pF)
IRL = 200 n, CL = 50 pFI
IRL coo, eL = 50 pFI
IRL - 200 n, eL 50 pF)

tPHZ(E)
tl'LZIEI
tPZH(EI
tPZLIEi

C

-

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
7-143

MC3487
FIGURE 1 - THREE-IITATE ENABLE TEST CIRCUIT
AND WAVEFORMS
To Scope (I "put)

3,0 V or Gnd
Input

To Scope
Output

Iny

Pulse generator characteristics
Zo· 60

Output

Open for tPZH(E) Test Only

n
~+5V

PAR = 1.0 MHz

Non-Inv
Output

50% Duty Cycle
~TLH. tTH L <; 5

ns
Pulse
Generator

I1.

200

l~~

Control

50

IN3064

pF

or Equivalent

1.0 k

1

CL Includes Probe and
Jig Capacitance

----""'·-------3.o V

Open for

tpzLiE') Test Only

__- - - - - 3.0 V

--------/~------------O

'------VOL

-----+--+-----0 V
~----VOH

==========~--------OV

FIGURE 2 - PROPAGATION DELAY TIMES INPUT TO
OUTPUT WAVEFORMS AND TEST CIRCUIT
Scope
(Output)

5.0 V

Iny
Output

Pulse
Generator

Non·lnv
1N914or
Equivalent

Output

Pu Ise generator characteristics
Zo = 50
PAR

c

n

Control

3.0V

1.0 MHz

50% Duty Cycle

tTLH. t-rHL

<

, - - - - , - - - - - - 3.0 V

5 ns

CL includes probe
and jig capacitance

Input

Output

'----+-'+-----

VOL

--+--+---+-+--'-- 0V
Output

VOL
OV

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

7-144

MC3487

FIGURE 3 - OUTPUT TRANSITION TIMES TEST CIRCUIT AND WAVEFORMS
Scope
Input

Input
Scope
Output
(Differential)

1\-3.0
--.!
Lov

V

Tel

3.0 V

-=-

Output
( DifferentIal)

CL includes probe
and jig capacitance

Pulse generator characteristics

n

Zo::' 50
PRR = 1.0 MHz
50% Duty Cycle

tTLH. tTHL"';; 5 ns

FIGURE 4 - OUTPUT CURRENT versus OUTPUT VOL TAGE

FIGURE 5 - OUTPUT SINK CURRENT versus OUTPUT VOL TAGE

0

80

0

=>
~

/

0

.0
0

10 f - - -

o
o

4.0

VOH. OUTPUT VOLTAGE (VOLTSI

-/

100

/

/
V

100

300

400

500

600

VOL. OUTPUT VOLTAGE-LOW ImVI

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
7-145

f---

I

700

800

MOTOROLA

-

MC3488A

SEMICONDUCTOR - - - - - -

TECHNICAL DATA

DUAL
EIA-423/EIA-232D
DRIVER
DUAL EIA-423/EIA-232D LINE DRIVER
The MC3488A dual single-ended line driver has been designed
to satisfy the requirements of EIA standards EIA-423 and
EIA-232D. as well as CCITT X.26. X.28 and Federal Standard
FIDS1030. It is suitable for use where signal wave shaping is
desired and the output load resistance is greater than 450 ohms.
Output slew rates are adjustable from 1.0 IlS to 100 IlS by a single
external resistor. Output level and slew rate are insensitive to
power supply variations. Input undershoot diodes limit transients
below ground and output current limiting is provided in both
output states.
The MC3488A has a standard 1.5 V input logic threshold for
TTL or NMOS compatibility.

SILICON MONOLITHIC
INTEGRATED CIRCUIT

.~

PI SUFFIX
PLASTIC PACKAGE
CASE 626

1

D SUFFIX
PLASTIC PACKAGE
CASE 751

• PNP Buffered Inputs to Minimize Input Loading
• Short Circuit Protection

(50·8)

• Adjustable Slew Rate Limiting
• MC3488A Equivalent to 9636A
• Output Levels and Slew Rates are Insensitive to Power
Supply Voltages
• No External Blocking Diode Required for VEE Supply
• Second Source IlA9636A

PIN CONNECTIONS

Wave
Shape

VCC

Input A

Output A

Input B

Output B

Gnd

VEE

TYPICAL APPLICATION

Wave Shape
Control

~

MC3488A Driver

TIL Logic

MC3486
Three-State Receiver
RS-423 Interface

~

1 ~

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

7-146

MC3488A
MAXIMUM RATINGS (Note 1)
Rating

Symbol

Value

Unit

VCC
VEE

+15
-15

V

10.
10-

+150
-150

Power Supply Voltages

Output Current

rnA

Source
Sink
Operating Ambient Temperature

TA

Junction Temperature Range
Ceramic Package
Plastic Package

TJ

Storage Temperature Range

Tste

o to

+ 70

"C
"C

175
150
-65to +150

"C

RECOMMENDED OPERATING CONDITIONS
Characteristic

Symbol

Min

Typ

Max

Unit

VCC
VEE

10.8
-13.2

12
-12

13.2
-10.8

V

Power Supply Voltages
Operating Temperature Range
Wave Shaping Resistor

TA

0

25

RWS

10

-

70

"C

1000

k!l

TARGET ELECTRICAL CHARACTERISTICS (Unless otherwise noted specifications apply over recommended operating
conditions)
Symbol

Min

Typ

Max

Unit

Input Voltage -

Low Logic State

VIL

-

0.8

V

Input Voltage -

High Logic State

VIH

2.0

Input Current - Low Logic State
(VIL = 0.4 VI

IlL

-80

-

-

p.A

10
100

-1.5

-

-6.0
-6.0
-6.0

-

-5.0
-5.0
-4.0

5.0
5.0
4.0

-

6.0
6.0
6.0

-

25

50

-

-15
+ 150
100

p.A

-

+18

mA

Characteristic

Input Current - High Logic State
(VIH = 2.4 VI
(VIH = 5.5 VI

V

p.A

IIHI
IIH2

Input Clamp Diode Voltage
(11K = -15 mAl

VIK

Output Voltage - Low Logic State
EIA·423
"-I
IRL
(RL
3.0 k!!1 EIA·232D
IRL - 450 HI EIA·423

VOL

Output Voltage - High Logic State
EIA·423
IRL
'·1
IRL - 3.0 kHl EIA-232D
450 HI EIA-423
IRL

VOH

Output Resistance

RO

-

-

V
V

V

!I

(RL" 450 ill
Output Short-Circuit Current (Note 21
(Vin = V out = 0 VI
(Vin = VIH(Minl' Vout = 0 VI
Output Leakage Current INote 31
(VCC = VEE = 0 V. - 6.0 V '" Vo '" 6.0 VI
Power Supply Currents
(RW = 100 k!l. RL = x. VIL '" Vin '" VIHI

..

laSH
10SL

-150
+15

lox

-100

ICC
lEE

-18

..

-

rnA

-

Note 1: DeVices should not be operated at these values. The Electrical Characteristics provide conditions for actual deVice operation .
2: One output shorted at a time.
3: No VeE diode required.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

7-147

MC3488A
~ 30 pF, f ~ 1.0 kHz, VCC ~ -VEE ~ 12.0 V :t 10%, TA ~ 25°C, RL ~ 450
measured 10% to 90% and 90% to 10%)

TRANSITION TIMES (Unless otherwise noted, CL

n. Transition times

Symbol

Characteristic
Transition Time, Low-to-High State Output
(RW ~ 10 kfll
(RW ~ 100 kfll
(RW ~ 500kfll
(RW ~ 1000 kfll

tTLH

Transition Time, High-to-Low State Output
(RW ~ 10 kfll
(RW ~ 100 kfll
(RW ~ 500 klll
(RW ~ 1000 klll

tTHL

Min

Typ

Max

I'S

-

0.8
8.0
40
80

1.4
14
70
140

-

I'S

-

0.8
8.0
40
80

1.4
14
70
140

-

-

FIGURE 1 - TEST CIRCUIT AND WAVEFORMS
FOR TRANSITION TIMES
To
Scope
(Input!

f

To
Scope
(Outputl

VCC

50

Pulse
Generator

RWS

~

1.0 kHz
Pw ~ 500 l's

'---+---_0--+______....__-'

CL
(Includes
Probe and Jig
Capacitancel

=
{

Note: Input Rise
and Fall Times

,:,:~ --!r------------;~-' < " " '
VOH----""""\I
90%

oV

90%

- - - - . - - - ---

outP:~L _______ J_[\-1;.:0__%~___________1..:.00.:.:V0'__'l
tTHL

---.~

f--- tTLH

r--

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

7-148

Unit

MC3488A
FIGURE 2 - OUTPUT TRANSISTION TIMES
versus WAVE SHAPE RESISTOR VALUE

11

FIGURE 3 -

t.:

I!lllIm

itW:;iiI':";

1,1'_]I,'ll1!

i
I ..i
.,.,....;: ;: '.

6.0

~

i 1O~+t~_;-M t111~j it:
~

-r

0.1

10

10

100

~~~J~~too~c~-~~tI~~~~~~

r--- --

I

---

lOor



~ -10
~

::>

O.OB

-20

I

] -40

.s

0.04

~No

>-

~

0.02

::>

12.0
10.0

Vin

8.0

j

6.0
~ 4.0
2.0
~
0
~ -2.0
~ -4.0
j: - 6.0
--B.O
-10.0
-12.0

6.0

B.O

10

·0.10
- 10

6.0 - 4.0 - 2.0
0
2.0 4.0
Vout • OUTPUT VOLTAGE iVOLTSI

·B.O

FIGURE 6 -

6.0

B.O

10

RISE/FALL TIME versus RWS

100

~ 0 V, V:n = VIIH

'VCC'
f=
r-- VEE -

ICC

Vce ~ 12 V
VEE = -12V
RwS = 100 kll, RL

a

--

-0.06

- O.OB

I

I

!Z

0.02

SUPPLY CURRENT versus
TEMPERATURE

I

0V

at VEE Pin.1

<=
::> . 0.04

I

FIGURE 5 -

=

diode required

0

I

Vin - OV

- 50
-10 - 8.0 ,,6.0 -- 4.0 - 2.0
0
2.0 4.0
Vout, OUTPUT VOLTAGE IVOLTSI

1

VCC = VEE = Vin
TA = 25°C

u
>-

I
I

I

2.0

::>

I

I

I

"'. -30

0.06

 - 6.0 t--- - RLl. 450 ~
':;--2.0

TRANSITION TIMES, tTLH,tTHLil'sl

FIGURE 4 -

I

I

4.0

!3

JLl!l HP

1.0 L.LL.LLLlllll:-'-'-...LLll"J-";llill,

-:.=T.•. -r---

i ': ~-=- -Lf~-_·-·"-ft---ItHt-t---t'~=

~1 'tt

!ll

~ r---:~

INPUT/OUTPUT CHARACTERISTICS
versus TEMPERATURE

r--

CL

I

I!O'

I

bt'"

TA = O°C, 70'C

t--

="

=

12V
12 V
30 pF

~

IP'

TA - 25'C
OV

Yin

"...

lEE

I

b?'"
<2':..

Vin I VIH
10

W

W

~

~

~

ro

1bt'"
10 k

~

TA, AMBIENT TEMPERATURE lOCI

100 k
RWS. WAVE SHAPING RESISTANCE 1111

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
7-149

tM

MOTOROLA

MC6875
MC6875A

- TECHNICAL
SEMICONDUCTOR
-----DATA

M6800 TWO·PHASE
CLOCK GENERATOR/DRIVER
M6800 CLOCK GENERATOR

SCHOTTKY MONOLITHIC
INTEGRATED CIRCUIT

Intended to supply the non'overlapping 1/>1 and 1/>2 clock signals
required by the microprocessor, this clock generator is compatible
with 1.0, 1.6, and 2.0 MHz versions of the MC6S00. Soth the
oscillator and high capacitance driver elements are included along
with numerous other logic accessory functions for easy system
expansion.
Schottky technology is employed for high speed and PNP·buffered
inputs are employed for NMOS compatibility. A single +5 V power
supply, and a crystal or RC network for frequency determination
are required.

Typical MPU System with Bus Extenders
L SUFFIX
CERAMIC PACKAGE
CASE 620

GND +5 V

c:::J 4 x fo MPU

~

PIN CONNECTIONS

Xl

Vee

X2

MPUoj>l

Ext In

Aeset Output

4 x fo

MPU oj>2

2 x fo
Memory
Ready

Power-On Reset
DMA/Ref Grant

BustP2

DMAfRef Aaq

Ground

Memory Clock

ORDERING INFORMATION
Device
Temperature Range
Package
MC6875L
o to +70·C
Ceramic
DIP
MC6875AL
- 55 to + 125·C

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

7·150

MC6875. MC6875A
MAXIMUM RATINGS

(Unle•• otherwise noted TA ~ 250 C.1

Roting

Symbol

Volu.

VCC

+7.0

Vdc

Input Voltage

VI

+5.5

Vdc

Operating Ambient Temperature Range
MCSB75L
MC6875AL

TA

Storage Temperature Range

T stg

-65 to +150

TJ

175

Power Supply Voltage

Unit

°c
Oto +70
·55 to +125

NOTE:
Operation of Ihe MC6B75AL over the full military
temperature range (to maximum TAl will resuilin

°c

excessive operating junction temperature.

Operating Junction Temperature

The use of a clip on 16 pin heatsink similar to AAVID
Engineering, Inc., Model 5007 (R6CA = llrCJWlls
recommended above TA .... 9SoC.

°c

RECOMMENDED OPERATING CONDITIONS

Conlact AAVID Engineering, Inc.
30 Cook Court
laconia, New Hampshire 03246
Tel. (6031 524-4443

Roting
Power Supply VO,ltage

ELECTRICAL CHARACTERISTICS
(Unless otherwise noted specifications apply over recommended power supplV and temperature ranges.
Typical values measured at Vee = 5.0 V and T A'" 2SoC.t
Characteristic
OUlput Voltage - High Logic State
MPU ¢ 1 and 1/>2 Outputs
(VCC = 4.75 V, IOHM = -200 "AI
(Vce = 5.25 V, IOHMK = +5.0 mAl
Bus 1/>2 Output
IVec ~ 4.75 V, IOHB = -10 mAl
IVCC = 5.25 V, IOHBK = +5.0 mAl

Symbol

Min

Typ

Max

VOHM
VOHMK

Vec -0.6

-

VCC + 1.0

VOHB
VOHBK

2.4

VOH4X
VOH

2.4
2.4

VOHR

2.4

-

-

VOLM
VOLMK

-

-

0.4
-1.0

VOLB
VOLBK

-

-

0.5
-1.0

VOL4X
VOL

-

-

0.5
0.5

V

0.5

V

V

-

-

4:1e fa Output
(VCC = 4.75 V, VIH = 2.0 V,IOH4X = -500 "AI
2 ~ fa, DMA/Refresh Grant and Memory Clock Outputs
~CC = 4.75 V, IOH = -500 "AI
Reset Output
(Vce = 4.75 V, VIH = 3.3 V, IOHA = -100 "AI
Output Voltage - Low Logic State
MPU 1/>1 and 1/>2 Outputs
(Vec=4.75V,IOLM = +200 "AI
(Vec = 4.75 V,IOLMK = -5.0 mAl
Bus 1/>2 Output
(Vee = 4.75 V, IOLB = +4B mAl
(VCC = 4.75 V, IOLBK ~ -5.0 mAl
4 x fo Output
(VCC = 4.75 V, VIL =0.8 V,IOL4X = 16mAI
2 x fo, DMA/Refresh Grant and Memory Clock Outputs
~CC =4.75 V,IOL = 16mAI
Reset Output
(VCC = 4.75 V, VIL = O.B V, IOLR = 3.2 mAl

-

-

-

V
V
V

V

V

V

VOLR

VIH

2.0

-

-

Input Voltage - Low Logic State
Ext. In, Memory Ready and DMA/Refresh Request Inputs

VIL

-

-

DB
3.6

V
V

Input Thresholds Power·On Reset Input (See Figure 21
Output Low to High
Output High to Low

=

V

Vce+ 1•O

Input Voltage - High Logic State
Ext. In, Memory Ready and DMA/Refresh Request Inputs

Input Clamp Voltage
(VCC 4.75 V, IIC = -5.0 mAl

Unit

MCSB75L
MCSB75AL

Input Current High Logic State
Ext. In, Mamory Ready and DMA/Refresh Request Inputs
(Vce =4.75 V, VIH = 5.0 VI
Power.()n Reset
(VCC = 5.0 V, VIHA = 5.0 VI
Input Current - Low Logic State
Ext. In, Memory Ready and DMA/Refresh Reque.t Inputs
(VCC = 5.25 V, VIL = 0.5 VI
Power.()n R_lnput'
(VCC· 5.25 V, VIL 0.5 VI

=

O.B

2.B
1.4

VIK

-

-

IIH

-

V

-

-1.0
-1.5

-

-

25

"A

IIHR

-

-

50

"A

IlL

-

-

-250

"A

IILR

-

-

-250

"A

-

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
7-151

V

VILH
VIHL

MC6875, MC6875A
I

OPERATING DYNAMIC POWER SUPPLY CURRENT
Characteristic

Symbol

Min

Typ

Max

Unit

ICCN

-

-

150

mA

ICCMR

-

-

135

mA

ICCDR

-

-

135

mA

Power Supply Currents

(VCC = 5.25 V, fose = 8.0 MHz, VIL = 0 V, VIH = 3.0 V)
Normal Operation
(Memory Ready and OMA/Refresh Request Inputs at
High Logic State)
Memory Ready Stretch Operation
(Memory Ready Input at Low Logic State;
DMA/Aefresh Request Input at High Logic State)
DMA/Refresh Request Stretch Operation
(Memory Ready Input at High Logic State;
DMA/Refresh Request Input at Low Logic State)

SWITCHING CHARACTERISTICS
(These specifications apply whether the Internal Oscillator (see Figure 9) or an External Oscillator is used (see Figure 10).

Typical values measured at

Vee

==

5.0 V, T A

== 25°C, fo == 1.0 MHz (see Figure 8).

Characteristic

Symbol

Min

Typ

Max

Unit

to
tpWM

500

-

-

ns
ns

400
230
180

-

-

900

-

-

600
440

-

-

0

-

-

ns

-

-

85
70

ns
ns
ns
ns

MPU 1>1 AND 1>2 CHARACTERISTICS
Output Period (Figure 3)

Pulse Width (Figure 3)
(fa = 1.0 MHz)
(fo = 1.5 MHz)
(fa = 2.0 MHz)
Total Up Time (Figure 3)
(fo=1.0MHz)
(fa = 1.5 MHz)
(fa = 2.0 MHz)

ns

tUPM

Delay Time Referenced to Output Complement (Figure 3)
Output High to Low State (Clock Overlap at 1.0 V)

tpLHM

Delay Times Referenced to 2 x fa (Figure 4 MPU 1>2 only)
Output Low to High Logic State
Output High to Low Logic State

tpLHM2X
tPHLM2X

-

-

-

-

25
25

Transition Times (Figure 3)
Output Low to High Logic State
Output High to Low Logic State

tTLHM
tTHLM

-

BUS 1>2 CHARACTERISTICS
Pulse Width - Law Logic State (Figure 4)

ns

tpWLB

430
280

-

-

-

-

210

-

-

450
295
235

-

-

480

-

320
240

-

-

-

-

25
20

tpLHBM2
tpHLBM2

-30
0

-

+25
+40

ns
ns

tTLHB
tTHLB

-

-

--

20
20

ns
ns

(fa = 1.0 MHz)
(fa = 1.5 MHz)
(fa = 2.0 MHz)
Pulse Width - High Logic State

ns

tpWHB

(fo = 1 .0 MHz)
(fo = 1.5 MHz)
(fa = 2.0 MHz)
Delay Times - (Referenced to MPU <1>1) (Figure 4)
Output Low to High Logic State

Output High to Low Logic State

tPHL8M1

(CL = 300 pF)
(CL = 100 pF)
Delay Times (Referenced to MPU ¢21 (Figure 4)
Output Low to High Logic State
Output High to Low Logic State
Transition Times (Figure 4)
Output Low to High Logic State
Output High to Low Logic State

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
7-152

ns

tpLHBMl

(fa = 1.0 MHz)
(fo = 1.5 MHz)
(fo = 2.0 MHz)

-

-

MC6875, MC6875A
SWITCHING CHARACTERISTICS (continued)
Characteristic

Symbol

Min

Typ

Max

Unit

tPLHCM
tpHLCM

-50
0

-

+25
+40

ns
ns

tpLHC2X
tPHLC2X

-

-

65
85

ns
ns

-

-

25
25

ns
ns

-

-

50
65

ns
ns

365
220

-

-

-

-

25
25

ns
ns

-

-

50
30

ns
ns

tTLH4X
tTHL4X

-

-

25
25

ns
ns

tSMRL
tSMRH

55
75

-

-

ns
ns

tHMRL

10

-

-

ns

Low Input Logic State
High Input Logic State

tSDRL
tSDRH

65
75

-

-

-

ns
ns

Hold Time (Figure 6)
Low Input Logic State

tHDRL

10

-

-

ns

Delay Time Referenced to Memory Clock (Figure 6)
Output Low to High Logic State
Output High to Low Logic State

tpLHG
tpHLG

-15
-25

-

+25
+15

ns
ns

Transition Times (Figure 6)
Output Low to High Logic State
Output High to Low Logic State

tTLHG
tTHLG

-

-

25
25

ns
ns

tPLHR
tpHLR

-

-

-

1000
250

ns
ns

tTLHR
tTHLR

-

-

-

100
50

ns
ns

MEMORY CLOCK CHARACTERISTICS
Delay Times (Referenced to MPU <1>2) (Figure 4)
Output Low to High Logic State

Output High to Low Logic State
Delay Times (Referenced to 2 x fa) (Figure 4)

Output Low to High Logic State

Output High to Low Logic State
Transition Times (Figure 4)

Output Low to High State
Output High to Low State

tTLHC
tTHLC

2 x fo CHARACTERISTICS
Delay Times (Referenced to 4 x fa) (Figure 4)
Output Low to High Logic State

tPLH2X
tPHL2X

Output High to Low Logic State
Delay Time (Referenced to MPU <1>1) (Figure 4)
Output High to Low Logic State
(fa = 1.0 MHz)
(fo = 1.5 MHz)

ns

tpHL2XM1

Transition Times (Figure 4)

Output Low to High Logic State
Output High to Low Logic State

tTLH2X
tTHL2X

4 x fo CHARACTERISTICS
Delay Times (Referenced to Ext. In) (Figure 4)

Output Low to High Logic State
Output High to Low Logic State
Transition Time (Figure 4)
Output Low to High Logic State
Output High to· Low Logic State

tPLH4X
tpHL4X

MEMORY READY CHARACTERISTICS
Set-Up Times (Figure 5)

Low Input Logic State
High Input Logic State
Hold Time (Figure 5)

Low Input Logic .State
DMA/REFRESH REQUEST CHARACTERISTICS
Set-Up Times (Figure 6)

DMAi.REFRESH GRANT CHARACTERISTICS

RESET CHARACTERISTICS

Delay Time Referenced to Power-On Reset (Figure 1)
Output Low to High Logic State
Output High to Low Logic State
Transition Times (Figure 1)
Output Low to High Logic State
Output High to Low Logic State

DESCRIPTION OF PIN FUNCTIONS
.4 x fo

• BUS 1/.12
- An output nominally in phase with MPU 1/.12 having
MC8T26A type drive capability.
• MEMORY CLOCK - An output nominally in phase with MPU tjJ2 which free runs
during a refresh request cycle.
• POWER-ON RESET A Schmitt trigger input which controls "Rti"S8i. A capacitor
to ground is required to set the desired time constant. Internal 50 k resistor to VCC. See General Design Suggestions
for Manual Reset Operation.

-

A free running oscillator at four times the MPU clock rate
useful for a system sync signal.
.2 x fo
- A free running oscillator at two times the MPU clock rate.
• DMAfREF REO
- An asynchronous input used to freeze the MPU clocks in
the 1/.11 high. tjJ2 low state for dynamic memory refresh or
cycle steal DMA (Direct Memory Access).
• REF GRANT
- A synchronous output used to synchronize the refresh or
DMA operation to the MPU.
• MEMORY READY - An asynchronous input used to freele the MPU clocks in
the tjJ1 low. tjJ2 high state for slow memory interlace.
• MPU ~1
- Capable of driving the 1/.11 and tjJ2 inputs on two MC6800s.
MPU ¢2

• "RESET
• X1, X2
• EXT IN

- An output to the MPU and 110 devices.
- Provision to attach a series resonant crystal or RC network.
- Allows driving by an external TIL signal to synchronous
the MPU to an external system.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

7-153

MC6875, MC6875A

FIGURE 1 - BLOCK DIAGRAM

Xl
X2

In

BUS ¢2

+-____-I

Mem 0 ry Aead y o-:(S;cl'--__

~D~M~A~/~A~e7fr-e~'h(o'0_1+-__-+____~
Request

Pin 16 - +5.0 Volts

PinS

FIGURE 2 - TYPICAL HYSTERESIS CHARACTERISTIC
OF RESET FUNCTION

-Gnd

FIGURE 3 - TIMING DIAGRAM FOR
MPU1 AND2

5. 0

__ Vee

0

5.0 V

TA '" 25 0 C

g

4. 0
tTLHM1

'"
20
w

'"0:
'='

'">
~

MPU <1>1
3. 0

2. 0

~

6 1. 0

>

0
4.0
2.0
3.0
1.0
VI, INPUT VOLTAGE (VOLTS!. POWER-ON RESET PIN

5.0

Vov

=

1.0 V

=

Clock Overlap

measurement point

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

7-154

MC6875, MC6875A

FIGURE 4 - TIMING DIAGRAM FOR NON-8TRETCHED OPERATION
(Memory Ready and DMA/Refresh Request held high continuously)
Ext. In Input Voltage: 0 V to 3.0 V, f =B.O MHz, Duty Cycle =50%, 'TLHEX ='THLEX

=5.0 ns

2.0V

Ext. In

tpLH4X

4 x fo

2 x fo

MPU \1>1

MPU \1>2

tTHLB
2.0 V

Busr$l2
0.8V

tTLHC

tTHLC

tpLHCM
2.0V

Memory Clock
0.8 V

0.8 V

0.8V

DMA/Refresh_G_'a_"_'_ _ _ _ _ _(;.;:L:...O_w.;.I_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

7-155

MC6875, MC6875A
FIGURE 5 - TIMING DIAGRAM FOR MEMORY READY STRETCH OPERATION
(Minimum Stretch Shown)

Input Voltage: 3.0 to 0 V. tTHLMR = tTLHMR = 5.0 ns

Memory Ready
0.8 V

~

DMA/Aefresh Request

tpWMR:=:

OM AI Refresh Grant

Irrelevant

1

fu

(Low)

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
7-156

MC6875, MC6875A
FIGURE 6 - TIMING DIAGRAM FOR DMA/REFRESH REQUEST STRETCH OPERATION
(Minimum Stretch Shown)
Input Voltage: 3.0 to 0 V. tTHLDR = tTLHDR a 5.0 ns

Memory Ready

~

Irrelevant

DMA/Refresh Request

tTLHOA

-+----tPwDMA.

~~5

MPU 1

2.0V

2.0 V

DMA/Rafrelh Grant
0.8 V

0.8 V

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
7-157

MC6875, MC6875A
FIGURE 7 - POWER ON RESET
Input Voltage: 0 to 5.0 V. f =100 kHz - Puis. Width =1.0 jlS, tTLH

='THL =25 ns

'TLH

5.0 V

---.,---t---t,-----------------""'

Power-On Reset

OV------"

2.OV

0.8 V

0.8 V

FIGURE 8 - LOAO CIRCUITS
For MPU

For Bus tfJ2

and MPU 2

~,1

+5.0 V

+5.0 V
RLL
58

RLL= 18k

t-_-i"IIt---;

To output'"-JR""D>tv-+-_........

Pin

r

To

RLH
20 k

~~~put\4__+-_-1>-_-i'III---;
RLH
240

All diodes are 1 N916
or equivalent

MPU 1 CL = 35 pF, RD = 20
MPU 2 CL = 70 pF, RD = 15

All diodes are 1N916
or equivalent

n
n

For 4 )( fa, 2 x fa, Memory Clock and DMA/Refresh Grant

For Reset Output

+5.0 Volts

+5.0 V

ALL=240

RLL- 1.2k

o ~~~put\4--t----1>---i'IIt--......
CL'
100pF

I

RLH

RLH=24k

4.7 k
All diodes are 1N916
or equivalent

• Load capacitance includes fixture and probe capacitance

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

7-158

All diodes are 1 N916
or equivalent

MC6875, MC6875A
APPLICATIONS INFORMATION
FIGURE 9 - TYPICAL RC FREQUENCY versus VOLTAGE
+8.0

~

+£.0

'"z
~

v

V

w

V

+4.0

~
~

/'

=> +2.0

V
10~1.0MHz _
@VCC"5.0V'
TA~25'C
-

/'
./

'1

~
~

I

V
-2.0
4.5

5.0

5.5
6.0
VCC, SUPPLY VOLTAG E IVO LTS)

6.5

7.0

FIGURE 10 - TYPICAL RC FREQUENCY
versus TEMPERATURE
/

+1.0

/

~ +O.B

1/

w

'"~
>-

ffi

~.6

/

1/
/

+0.4

1/

=>
d
~ +0.2

10

/
/

~

V

---

-10

10

20

1.0MHz._

~

1

./

-0.2

~

~:SC2~~r- f----

30
40
50
60
TA, TEMPERATURE 1'C)

70

80

90

FIGURE 11 - TYPICAL FREQUENCY versus
RESISTANCE FOR C VARIABLE
200

100
80

~

"'I'..

"........

"
"20

I

'""
~ ~

""-

"-

"'-

,,-'"

"-

" "'"

1

"-

"-

"-

I'\.

l"-."

'\

3k

CT

IVC~"510)TA" 25°C -

ITrlm)

\

2k

_lL'

n=

~ ".. "'\ ~
~ ",-" i'.. '\ 1\

'"

OSCILLATOR
A tank circuit tuned to the desired crystal frequency
connected between terminals Xl and X2 as shown in
Figure 12, is recommended to prevent the oscillator from
starting at other than the desired frequency. The 1kn
resistor reduces the 0 sufficiently to maintain stable
crystal control. Crystal manufacturers may recommend a
capacitance (CU to be used in series with the crystal for
optimum performance at series resonance.
See Figures 9 and 10 for typical oscillator temperature
and VCC supply dependence for R-C operation.
FIGURE 12 - OSCILLATOR-CRYSTAL OPERATION

NOTE: RC Operation not recommended above
4Xlo "2.0MHz ,-

Ri 5k 4ki

10

I I I I I

GENERAL
The MC6875 Clock Generator/Driver should be located
on the same board and within two inches of the MC6800
MPU, Series damping resistors of 10·30 ohms may be
utilized between the MC6B75 and the MC6800 on the 4>1
and 4>2 clocks to suppress overshoot and reflections.
The VCC pin (pin 16) of the MC6875 should be
bypassed to the ground pin (pin 8) at the package with a
0.1 j.LF capacitor. Because of the high peak currents
associated with driving highly capacitive loads, an ade·
quately large ground strip to pin 8 should be used on the
MC6875. Grounds should be carefully routed to minimize
coupling of noise to the sensitive oscillator inputs, Unnec·
essary grounds or ground planes should be avoided near
pin 2 or the frequency determining components. These
components should be located as near as possible to the
respective pins of the MC6875. Stray capacitance near
pin 2 or the crystal, can affect the frequency. The can of
the crystal should not be grounded. The ground side
of the crystal or the C of the R·C oscillator should be con·
nected as directly as possible to pin 8.
Unused inputs should be connected to VCC or ground.
Memory Ready, DMA/Refresh Request and Power·On
Reset should be connected to VCC when not used.
The External Input should be connected to ground
when not used.

\

1k

l__ -

-I=

•
cL

XTAL

• Required by some

7

8 9 10

Crystal manufacturers

4 X 1o, FREQUENCY IMHz)

MOTOROLA LlNEAR/INTERFACE ICs DEVICE DATA

7-159

13)

Ext In

I

O'i k

MC6875

_
-

4 X fo"" Crystal frequency
4 X fo =\ _ _
1 __

2 "/LTCT
2.5 I'H .. LT .. 22 I'H
75 pF .. CT .. 200 pF

RT

~

1>11

MC6875, MC6875A
TABLE 1 - OSCILLATOR COMPONENTS
TANK CIRCUIT
PARAMETERS

CTS KNIGHTS
400 REIMANN AVE.
SANOWICH,IL

APPROXIMATE
CRYSTAL PARAMETERS

60548

(815) 786-8411

10

~H

CT
pF

RS
Ohms

Co
pF

C1
mpF

MHz

10

150

15-75

3·6

12

4.0

MP.()4A
* 390pF

113-31

4.7

82

11-45

23

8.0

MP.(J80
• 47 pF

113-32

LT

4·7

TYCO CRYSTAL PROOUCTS
3940 W. MONTECITO
PHOENIX,AZ
85019
(602) 272·7945

McCOY ELECT. CO.
WATTS & CHESTNUTS STS.
MT. HOLLY SPRING, PA
17065
(717) 486.:1411

150-3260
150-3270

Inductors may be obtained from: Collcraft, Cary, IL 60013 (312) 639·2361

FIGURE 13
RC OPERATION

(1).------,
r - - - - - - 1 Xl
EXTERNAL INPUT

R

(I)

(2)

+-----i x2

Open

Me6S75

(2)

(3)

Ext In

MC5S75
(3)

r - - -....---l Ext In

51
External Pulse
Generator

To precisely time a crystal to desired frequency, a
variable trimmer capacitor in the range of 7 to 40 pF
would typically be used. Note it is not a recommended
practice to tune the crystal with a parallel load capaci·
tance.
The table above shows typical values for CT and LT,
typical crystal characteristics, and manufacturers' part
numbers for 4.0 and 8.0 megahertz operation.
The MC6875 will function as an R·C oscillator when
connected as shown in Figure 13. The desired output
frequency (M4>1) is approximately:
Formula

320

4 x to "" C (R+ .27) + 23
(See Figure 11)

a solid VOL output level until VCC has reached 3.5 to
4.0 V. During this time transients may appear on the
clock outputs as the oscillator begins to start. This
happens at approximately VCC = 3 V. At some VCC level
above that, where Reset Output goes low, all the clock
outputs will begin functioning normally. This phenom·
enon of the start-up sequence should not cause any
problems except possibly in systems with battery back·up
memory. The transients on the clock lines during the
time the Reset Output is high impedance could initiate
the system in some unknown mode and possibly write
into the backup memory system. Therefore in battery
backup systems, more elaborate reset circuitry will
be required.
Please note that the Power·On Reset input pin of the
MC6875 is not suitable for use with a manual MPU reset
switch if the DMA/Ref Req or Memory Ready inputs are
going to be used. The power on reset circuitry is used to
initialize the internal control logic and whenever the
input is switched low, the MC6875 is irresponsive to
the DMA/Ref Req or Memory Ready inputs. This may
result in the loss of dynamic memory and/or possibly
a byte of slow static memory. The circuit of Figure 14
is recommended for applications which do not utilize the
DMA/Ref Req or Memory Ready inputs. The circuit of
Figure 15 is recommended for those applications that do.
FIGURE 14 - MANUAL RESET FOR APPLICATIONS NOT USING
DMA/REFRESH REQUEST OR MEMORY READV INPUTS
Vce

C in picofarads
R in K ohms
4 x fo in Megahertz
C

It would be desirable to select a capacitor greater than
15 pF to minimize the effects of stray capacitance. It is
also desirable to keep the resistor in the 1 to 5 k n
range. There is a nominal 270 n resistor internally at
X 1 which is in series with the external R. By keeping
the external R as large as possible, the effects due to
process variations of the internal resistor on the frequency
will be reduced. There will, however, still be some
variation in frequency in a production lot both from
the resistance variations, external and internal, and
process variations of the input switching thresholds.
Therefore, in a production system, it is recommended
a potentiometer be placed in series with a fixed R
between X 1 and X2.
POWER-ON RESET
As the power to the MC6875 comes up, the Reset
Output will be in a high impedance state and will not give

T~,12 ~
4
\a~u'l

14

40

l'l

-=

g
l'l

Raset Switch :!

FIGURE 15 - MANUAL RESET FOR SYSTEMS USING
DYNAMIC· RAM OR SLOW STATIC RAM IN CONJUNCTION
WITH MEMORY READY OR DMA/REFRESH REQUEST INPUTS
Vec
1/474LSOS
47 k

III

CIJ;:

....

B
.:!

14

~

..t

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

7-160

Manual Reset

Switch

MOTOROLA

MC34050
MC34051

SEMICONDUCTOR-----TECHNICAL DATA

DUAL EIA-422/423 TRANSCEIVER

DUAL EIA-422/423
TRANSCEIVER

The MC34050/51 are dual transceivers which comply with EIA Standards
EIA-422 (Balanced line) and EIA-423 (Unbalanced line). Each device contains
two drivers and two receivers.
The MC34050 has a DRIVER ENABLE (for both drivers) and a RECEIVER
ENABLE (for both receivers). Connecting the two ENABLES together
provides Driver-to-Receiver switching from a single line.
The MC34051 has a DRIVER ENABLE for each driver. The two receivers are
permanently enabled.
The Driver inputs, Receiver outputs, and Enable inputs are 74LS TTL
compatible.

SILICON MONOLITHIC
INTEGRATED CIRCUIT

DSUFFIX
PLASTIC PACKAGE
CASE 7518
(SO·16)

• Two Independent Drivers and Receivers Per Package

PSUFFIX
PLASTIC PACKAGE
CASE 648

• 3-State Outputs
• Single 5.0 V Supply
• Internal Hysteresis (50 mV Typical) on Receivers
• Receivers Provide Fail-Safe Function. Output Stays High if Inputs are
Open, Shorted (floating), or Terminated (floating)

PIN CONNECTIONS

• Receivers May Be Used in EIA-422 or 423 Systems
• Drivers Meet Full EIA-422 Standards

REel In-

Vee
DRlin

REel In+

RECEIVER BLOCK DIAGRAM

REel Out

DRl Out

REeEN

DR10ut

REe2 Out

OR EN

REe2 In+

DR2 Out

REe2 In-

DR20ut

GND

DR21n
(MC34050)

REel In-

DRIVER BLOCK DIAGRAM

::: {Lg'l

~'-"
":~.

Nonmvertlng

REel In+

Vee
DRlin

REel Out

DR10ut

REeEN

DRl Out

REe2 Out

OR EN

REe2 In+

DR2 Out

REe2 In-

DR2 Out

GND

Driver Enableo-Q---J

(MC34051)

Driver

Data

EN

L

H
H

H
X

L

Receiver

Inv. Out Noninv. Out
H

L

L
Z

H

Z

DR21n

ORDERING INFORMATION

Input

EN

Output

> + 0.2 V Ditt.
< - 0.2 V Ditt.
X

L
L
H

H

L
Z

Device
MC34050D
MC34050P
MC34051P

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

7-161

Temperature Range

0° to + 70°C

Package
SO-16
Plastic DIP
Plastic DIP

MC34050, MC34051
MAXIMUM RATINGS
Value

Units

Power Supply Voltage (VCC)

7.0

Vdc

Input Common Mode Voltage (Receivers)

±25

Vdc

Input Differential Voltage (Receivers)

±25

Vdc

Parameter

Output Sink Current (Receivers)

50

rnA

Enable Input Voltage (Drivers and Receivers)

5.5

Vdc

Input Voltage (Drivers)

5.5

Vdc

Applied Output Voltage (3-State mode) -

Receivers

-1.0to +7.0

Vdc

Applied Output Voltage (3-State mode) -

Drivers

-1.0to +7.0

Vdc

Junction Temperature

-65 to + 150

·C

Storage Temperature

-65to +150

·C

Devices should not be operated at these values.
The "Recommended Operating limits'" provide for actual device operation.

RECOMMENDED OPERATING LIMITS
Parameter

Min

Typ

Max

Power Supply Voltage

+4.75

+5.0

+5.25

Vdc

Input Common Mode Voltage (Receivers)

-7.0

+7.0

Vdc

Input Differential Voltage (Receivers)

-6.0

+6.0

Vdc

+5.25

Vdc

+5.25

Vdc

Enable Input Voltage (Drivers and Receivers)

0

Input Voltage (Drivers)

0

Ambient Temperature Range

0

-

Units

·C

+70

ELECTRICAL CHARACTERISTICS (Unless otherwise noted specifications apply for 4.75 < VCC < 5.25 volts,
and o· < TA < 70·C).
Symbol

Parameter

Min

Typ

Max

Units

DRIVERS
Input Voltage -

Low

VILD

-

-

0.8

Vdc

Input Voltage -

High

VIHD

2.0
-360

-

Vdc

IILD
IIHD

-

-

+20
+100

p.A

-

Vdc

0.5

Vdc

-

Vdc

+0.4

Vdc

= 0.4 V
Input Current @ VIH = 2.7 V
VIH = 5.25 V
Input Clamp Voltage (11K = -18 rnA)
Output Voltage - Low (lOL = 20 rnA)
Output Voltage - High (lOH = - 20 rnA)

VIKD

-1.5

VOLD

-

VOHD

2.5

Output Offset Voltage Difference (Note 1)

VOSD

-0.4

Input Current @ VIL

Output Differential Voltage (Note 1)

-

VT

2.0

Output Differential Voltage Difference (Note 1)

VTD

-0.4

Short Circuit Current (VCC = 5.25 V)
(From High Output, Note 2)

10SD

-150

Output Leakage Current - Hi-Z State
(Vout = 0.5 V, DR EN = 0.8 V)
(Vout = 2.7 V, DR EN = 0.8 V)

10ZD

Output Leakage - Power Off
(Vout = -0.25 V, VCC = 0 V)
(Vout = 6.0 V, VCC = 0 V)

-

Vdc

+0.4

Vdc

-30

rnA
p.A

-100
-100

-

-

+100
+100

-100

-

-

-

-

+100

10(off)

Notes: 1) See EIA Standard EIA-422 and Figure 1 for exact test conditions.
2) Only one output in a package should be shorted at a time, for no longer than 1 second.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

7-162

p.A

p.A

MC34050, MC34051
ELECTRICAL CHARACTERISTICS (Unless otherwise noted specifications apply for 4.75 < VCC < 5.25 volts,

I

and 0"

< TA < 70"C).
Parameter

Symbol

Min

Typ

Max

-

-

+0.2

-

-

-

+2.3

Units

RECEIVERS
Differential Input Threshold Voltage (Note 3)
(-7.0 V < VICM < + 7.0, Vout '" 2.7 V)
(-7.0 V < VICM < +7.0, Vout '" 0.45 V)
Input Bias Current
(0'" VCC '" 5.25 V, Vin
(0'" VCC '" 5.25 V, Vin

=
=

VTHR

-0.2

rnA

IIBR
+15 V)
-15 V)

Output Leakage Current - 3-State (Pin 4
(VID = +3.0 V, Vo = 0.4 V)
(VID = -3.0 V, Vo = 2.4 V)

-2.8

Input Balance and Output Level
(-7.0'" VICM '" +7.0 V)
(VID = +0.4 V, 10 = -400/LA)
(VID = -0.4 V,IO = 8.0 rnA)

Vdc

-

Vdc

2.7

VOHR
VOLR

= 2.0 V,

MC34050 only)

Output Short Circuit Current (Note 2, VCC = 5.25 V)
(VID = +3.0 V, MC34050 Pin 4 = 0.4 V, Vo = 0 V)

-

-

-

-

-100
-100

-

+100
+100

10SR

-85

-

-15

-

10ZR

0.45
pA

rnA

ENABLES
Input Voltage -

Low

VILE

-

Input Voltage -

High

VIHE

2.0

IlLER
IILED

-100
-360

IIHE

-

VIKE

-1.5

Input Current @ VIL

= 0.4 V (Receiver EN)
(Driver EN)

= 2.7 V
= 5.25 V
Input Clamp Voltage (11K = -18 rnA)
Input Current @ VIH
VIH

-

0.8

Vdc

-

Vdc

-

pA

+20
+100

pA

-

Vdc

80

rnA

-

POWER SUPPLY
Power Supply Current @ VCC = 5.25 V
Notes: 1)
2}
3}
4)

55

ICC

See EtA Standard EIA-422 and Figure 1 for exact test conditions.
Only one output in a package should be shorted at a time, for no longer than 1 second.
Differential input threshold voltage and guaranteed output levels are done simultaneously for worst case.
All currents into a device pin are positive. those out of a pin are negative. Voltages are referenced to ground. Algebraic convention rather
than magnitude is used to define limits.

DRIVER SWITCHING CHARACTERISTICS (VCC

= 50 V TA = 25"C See Figure 2)

Symbol

ParaMeter
Propagation Delay
Data Input to Output High-to-Low
Data Input to Output Low-to-High
Output Skew ([tpHL - tpLHI each driver)
Enable Input to Output
CL = 10 pF, RL = 75 {l to Gnd
CL = 10 pF, RL = 180 {l to VCC
CL = 30 pF, RL = 75 {l to Gnd
CL = 30 pF, RL = 180 {l to VCC
Maximum Data Input Transition Time (10-90%)

RECEIVER SWITCHING CHARACTERISTICS (VCC

Enable Input Enable Input Enable Input Enable Input -

Max

-

-

20
20
8

tpHZD
tpLZD
tPZHD
tpZLD

-

-

30
35
40
45

-

50

-

Min

Typ

Max

-

-

30
30
35
35
30
30

-

-

Units
ns

tpHLD
tPLHD
tSKD

trRD

Symbol

High-to-Low
Low-to-High

Output Low to 3-State }
Output High to 3-State
Output 3-State to High
Output 3-State to Low

Typ

ns

= 5.0 V TA = 25"C Figure 3)

Parameter
Propagation Delay
Differential Input to Output Differential Input to Output -

Min

tpHLR
tpLHR
tpLZR
tPHZR
tPZHR
tpZLR.

MC34050 Only

-

-

°MC340SO Only.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
7-163

Units
ns

-

-

-

-

MC34050, MC34051
FIGURE 1 - DRIVER OUTPUT TEST CIRCUIT

I

50 Il, 1%
Yin = 3.0 V
Yin' = OV

l

501l,1%
V05

±=

V05D

I V05 -

VODD

IIVTi -

V05'1:
IVT'II

Circuit per EIA·422-A, Dec. 1978

FIGURE 2 - DRIVER SWITCHING TEST CIRCUITS

+3.0V-r-------,
Input

0 J,+1.3V

-I
I

tpHLD

r=

~~~~
-I tpHLD 1- --I tpLHD If-:-:-:-::L
VOH
B
'\+1.3V
VOL-'-.
_ _ _ _ _ _ r+I.3V

A

751l

"\+1.3V

~ tpLHD I;::

1801l

Output

I -f+1.3V

....J_

Input

+3.0~V+1.3V
+1.3V

L

o

180 Il +5.0 V

0.5 V

~V

tPZHDr,:::

+1.3 V

OH
tpHZD

Output
tPLZD } / - -

'-_____..JT- 0.5 V
5G: 1.0 MHz, 50% duty cvcle, tA, tF = 6.0 ns (10-90%)
AL = 751l to GND for tpZHD and tpHZD, 180 II to Vee for tpZLD and tPLZD:
CL = 10 pF for tpHZD and tpLZD, 30 pF for tpZHD and tpZLD.

FIGURE 3 - RECEIVER SWITCHING TEST CIRCUITS

InpUt

+3.0 V- r --:-:----"""\
J,+1.5V

I

o __
Output

tpLHA

\+1.5V

....I

1;=

tpHLA

_ _ _...J_f+I.3V

51
Input

2.0 k

5.0 k
Va

Output
IN916's
or
equivalent

52

MC34050 Only

5G: 1.0 MHz, 50% duty cycle, tA, tF = 6.0 ns (10-90%)
V. = + 1.5 V for 'pHZ, tpZH: Va = -1.5 V for tPLZ, 'PZL.
51,52 closad for tpHZ, tpLZ: 51 open, 52 clooed for 'PZH: 51 closed, 52 open for 'pZL.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
7-164

1--::_ VOH
\+1.3V
' -_ _ _ VOL

MC34050, MC34051

FIGURE 4 - DRIVER INPUT CHARACTERISTICS

FIGURE 5 -

3.8

+30
in

!:; 3.4

~

-30

I

1 -60
f.5 -so

;;J, 2.6

V

~ 2.2

c
I--

1.4

2.0
3.0
INPUT VOLTAGE IVOLTS)

4.0

5.0

I

o

400

-

~

9

"...-

........

V

~

./

10

20

.:-....

f-Vee = 4.77v'

-.......'- 0-.......~

20
30
LOAD CURRENT

r- -......
r----- -...
r-.
r--

r-..
...........

o

-10

....... ",Vee

~
Vee =

-20

IOLD ImA)

AGURE 8 - RECEIVER OUTPUT VOLTAGE.

"-

IOHD

Typical (II) 25°C
2.0

'<

+~-VOHD

~I

5.25 v

Vee

-... -.......-""'"

D

50

40

DRIVER OUTPUT VOLTAGE

-

f--

+~IOLO -VOLDI Typical @ 25oe,~
4.75 V'" Vee'" 5.25 V
30
40
50

100

o
o

!).... "'1--............

I
10

FIGURE 7 -

4.0

:f2 200

K.."k

r-.....

f--~v..r---,T

5.25 ~
I

Jee;= 5.0V- -

I"--.. I'.
--~ r-.....
I

FIGURE 6 - DRIVER OUTPUT VOLTAGE

500

~300

~

~1.8 Ct-TYPical @ 25°C

Typical @ 25°C

4.71 V'" vice'" j.25 V
1.0

Vee
./

F

V

o

3.0

:E

/

5

~ -150

~

I--

r-.....

§!

V

ll§

a -120
-210

~

---

r---....
r---... -... t---

!:;

/

I-

-180

w

DRIVER DIFFERENTIAL OUTPUT CHARACTERISTICS

-30
IOHDlmAI

5.0 V

"- r........

I4.7 "~ I"..
V

'" I".."

-40

-50

FIGURE 9 - RECEIVER OUTPUT VOLTAGE

5.0

400

300

-- -

4.5

~

V
100
o

o

--

Vf..--

2.0

I\,

""'-

-I---

3.5

4.0
lOLA ImAI

Typical @ 25°C
Vee = 5.0V
I
6.0

r--

I--3.0
8.0

o

Typical@ 25°C
Vee = 5.0V

r

I
-100

MOTOROLA L1NEARIINTERFACE ICs DEVICE DATA
7-165

-200
IOHR IpA)

-300

-400

--

MC34050, MC34051

FIGURE 11 - ENABLE INPUT CHARACTERISTICS

FIGURE 10 - RECEIVER INPUT CHARACTERISTICS
0.8

&

I

I-o. 4fI-

I I I

=

I

I

o

-2.0

U

A

I!P

~

Vec

.&J~

-1.2 ~
-7.0
- 5.0

\[.....--'"
~

".-

5.25 V

V-

Typical @ 25°C
- 3.0
-1.0
+ 1.0
+ 3.0
INPUT VOLTAGE (VOLTS)

FIGURE 12 0.8

-

1=

TA
-0.8

~

-26

+ 7.0

~~

~

-5.0

~

O°C

-

~

-' i-"""

~

I

V~HD~ ~20~~

/'

./

5.0 V
+5.0

o

o

+7.0

-

...... V
f-10°

0.4 V

i..-20°
30°
40°
50°
AMBIENT TEMPERATURE re)

/
".-

"2

+50

i

70°

60"

f
~ -1.0

70

~1.7Jvc~~ ~V,T.d

17- l-

Va ~ 0.4 V, VCC ~ 5.0V/ / ' /

I-Vr tr'
o

10

ViC

~I 0.0

I

20
30
40
50
AMBIENT TEMPERATURE lOCI

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
7-166

,J

o
-IVa ~ 6.0 V, Vce ~ O.OV

V; ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~

VOLO@ +20 mA_ -

60

~

K"

FIGURE 15 - DRIVER OUTPUT LEAKAGE

/

20
30
40
50
AMBIENT TEMPERATURE lOCI

Va

./

+100

-2.0
10

7
va ~ 2.4 V V

V

o

MC34050 only
Pin 4 ~ 2.0 V

50

V
-120

5.0

/'

I

...-

4.0

2.0
3.0
INPUT VOLTAGE (VOLTS)

/

FIGURE 14 - DRIVER OUTPUT VOLTAGE

./

I
1.0

V

-1.0
+1.0
+3.0
INPUT VOLTAGE iVOLTS)

+120

Typical @25°C_ I - Vec ~ 5.0V - f---

o

~
~
10" TA ~1700e

TA

Vcc
-3.0

/

FIGURE 13 - RECEIVER OUTPUT LEAKAGE

-1.2 ~ V
-7.0

V

Driver Enable

7

250

=

25°C

~~

+5.0

-22

RECEIVER INPUT CHARACTERISTICS

~'

-

-

1/

I - - Receiver
Enable

Vee ~ 5.0V~~ ~

=

~

0

-I-Vee:~4175~ ~ !P'

l#~

-0.8

0.4

+2.0

I¢¢'

........

"-

60

"
70

MC34050, MC34051

FIGURE 16 -

EIA·422 APPLICATION

TTL

FIGURE 17 -

EIA·422 APPLICATION

--

I

Notes: 1) RT must equal characteristic impedance of the cable.
2) Individual receivers may be MC34050, MC34051, MC3486, or AM26LS32.
3) System ground may be made through cable shield as shown, or through chassis ground. Common mode differences and signal quality
must be considered when choosing a ground path.

MOTOROLA LlNEARIiNTERFACE ICs DEVICE DATA

7-167

MOTOROLA

MC34142

SEMICONDUCTOR-----TECHNICAL DATA

Advance Information

High Performance Decoder!
Sink Driver
The MC34142 is a high performance 4 to 16 multiplexed driver. This
integrated circuit features a 4 to 16 decoder, 16 open drain N-channel MOS
output devices with clamp diodes. The outputs are controlled by 4 address
inputs, an output enable, and a chip enable.
Typical applications include solenoid drivers, LED drivers, lamp drivers,
and relay drivers.
This device is offered in a PLCC and a wide body surface mount package.
•
•
•
•
•
•
•
•
•

FNSUFRX
PLASTIC PACKAGE
CASEnS

DWSUFRX
PLASTIC PACKAGE
CASE 751F
(SO-2BL)

SMARTMOSTM Technology
35 V Maximum Output Off-State Voltage
500 mA Maximum Output Sink Current
Regulated Output Saturation Voltage
16 Open Drain MOS Outputs
4 Input CMOS Decoder
Chip Select and Output Enable Input Pins
Internal Freewheel Diodes
Functional Equivalent to the UCN5816A

PIN CONNECTIONS
1

o
(Top View)

Pin 1. Chip Enable

2. N.C.
3.
4.
5.
6.
7.
8.
9.
10.

Simplified Block Diagram

Vee
OU1pU1 Enable
Kl
0U1pU11
0U1pU12
0U1pU13
0U1pU14
0U1pU15

11.0U1pU16
12. 0u1put7
13.0U1pu16
14. Ground
15. Ground
16.0u1put9
17.0U1pU110
18.0U1pu111
19.0u1put12

2O.0ulput13
21. 0u1put14

22. 0u1put15
23.0u1put16
24. K2

2S.lnpu1A
26.lnpU1B
~.lnpu1C

28.Inpu1D

Output Enable 0 - 1 - - - - - - - - - ,

Chip Enable

A
B

C

i

1--+--;"" Output 9
I

+0

Output 10
Output 11

+0 Output 12

D

-to Output 13

(Top View)

1"" Output 14

Oulput 15
I----!I"" Outpul16

IL _____________ _ __ I
~

ORDERING INFORMATION
Temperature

~

Device

Range

MC34142FN
MC34142DW

0'10 + 70'C

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
7-168

Package
PLCC
SO-2BL

MC34142
MAXIMUM RATING
Rating

Symbol

Value

Unit

VCC

7.0

V

Output Voltage

Vo

35

Drive Output Sink Current (Note t)

10

Power Supply Voltage

Continuous
Pulsed (10 ~s)

V
mA

500
1000

Power Dissipation and Thermal Characteristics
FN Suffix, Plastic Package, Case 776
TA = 25°C
Thermal Resistance, Junction to Air
OW Suffix, Plastic Package, Case 751 F
TA = 25°C
Thermal Resistance, Junction to Air

Po
RSJA

1.9
66

°crw

W

Po
RSJA

1.5
80

°crw

Operating Junction Temperature

TJ

+150

Operating Ambient Temperature
MC34142

TA

Storage Temperature

Tstg

W

°c
°c

o to + 70
-55 to +150

°c

ELECTRICAL CHARACTERISTICS (VCC = 5.0 V, for typical values TA = 25'C, for min/max values TA= 0' to + 70°C.)

I

I

Characteristic

Symbol

I

Min

I

Typ

I

Max

Unit

POWER SUPPLY SECTION
Logic Supply Voltage

VCC

Supply Current
Outputs Off
Outputs On

ICC

4.75

5.0

5.25

V
mA

-

-

-

-

0.5
4.0

LOGIC INPUT SECTION
Input Threshold Voltage -

High State Logic 1
Low State Logic 0

VIH
VIL

Input Current (Vin = 5.0 V)

liN

2.2

-

-

V

-

-

0.8

-

20

1.1
1.2

-

1.3
1.4

-

-

100

~A

-

100

~A

0.8

-

1.1

-

1.2
1.6

~A

OUTPUT SECTION
Output Saturation Voltage
ISink = 100 mA
ISink = 400 mA

VSat

Output Leakage Current (VO = 35)

ILeak

Clamp Diode Leakage Gurrent (VR = 35 V)

IR

Clamp Diode Forward Voltage
Iforward = 100 mA
Iforward = 400 mA

VF

SWITCHING CHARACTERISTICS (TA

V

V

=25°C)

Output Rise Time

tr

-

40

-

ns

Output Fall Time

tf

-

40

-

ns

Propagation Delay Time
Output Enable Low to Output Low
Output Enable High to Output High

tpl\
tphh

50
50

-

150
150

Setup Time, Data to Output Enable

tsu

40

ns

Hold Time, Output Enable to Data

th

40

ns

ns

MOTOROLA LlNEARIINTERFACE ICs DEVICE DATA

7-169

-

MC34142
APPLICATION CIRCUIT INFORMATION
500 mAo The outputs have been uniquely designed to control
the "on-resistance" of the power MOSFET. The voltage drop
across the MOSFET is regulated and temperature
compensated to give a consistent saturation voltage
characteristic over load and temperature. Figure 2 shows
a curve of the Output Saturation Voltage versus Sink Current.
Each output also has a flyback diode clamp to protect the
device from inductive load kickbacks. Special care should
be taken when laying out the printed circuit board to use
these clamp diodes effectively. A capacitor should be placed
close to the K1 and K2 clamp outputs.

The MC34142 is a high performance 4 x 16 multiplexed
driver. This integrated circuit features a 4 x 16 decoder, 16
open-drain output devices with clamp diodes, an output
enable, and a chip enable. Typical applications include
solenoid drivers, LED drivers, lamp drivers, and relay drivers.
The inputs to this device are TTUCMOS compatible,
making them ideal to be driven from a microcomputer.
Table 1 Is a truth table for the Input logic versus the
appropriate activated output. Notice, for a specific input,
only one output can be activated.
The outputs on the MC34142 are open drain DMOS power
MOSFETs. Each output is capable of sinking in excess of

Figure 1. Typical Application
Vcc= 5.0V

Voo

T

I

I

1:
-=-

d~
Kl,K2

A

311

~

B
Solenoid

C

MC34142

Microcomputer

~~
-<>

LEO

0
Chip Enable

Lamp

OU1pUl Enable

r[
Relay

.L

.L

Figure 2. Output Saturation Voltage
versus Load Current

:E

3.0

!!l
!:5

2.5

VCC=5.0V
80 lIS Pulsed Load
120 Hz Ra1e
TA = 25°C

§!
;

2.0

~

1.5

!

Figure 3. Propagation Delay

1.0
0.5

>1 o

o

0.1

0.2
0.3
10, OUTPUT CURRENT (A)

0.4

0.5

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
7-170

50nsJDIV

-<>

MC34142
Figure 5. Output "Turn-Off" Time

Figure 4. Output "Turn-On" Time

90%

90%

10%

10%

10 n,/DIV

10 n,/DIV

Table 1. Truth Table
Data Inputs
D

C

B

A

Selected Output
Active Low

1

0

0

0

0

Output 1

1

0

0

0

1

Output 2

0

1

0

0

1

0

Output 3

0

1

0

0

1

1

Output 4

0

1

0

1

0

0

Output 5

0

1

0

1

0

1

Output 6

0

1

0

1

1

0

Output 7

0

1

0

1

1

1

OutputS

0

1

1

0

0

0

Output 9

0

1

1

0

0

1

Output 10

0

1

1

0

1

0

Output 11

0

1

1

0

1

1

Output 12

0

1

1

1

0

0

Output 13

0

1

1

1

0

1

Output 14

0

1

1

1

1

0

Output 15

0

1

1

1

1

1

Output 16

x

0

x

x

x

x

1

x

x

x

x

x

All Outputs
High

Output Enable

Chip Enable

0
0

MOTOROLA LlNEARIiNTERFACE ICs DEVICE DATA

7-171

MOTOROLA

MC75107
MC75108

- TECHNICAL
SEMICONDUCTOR
-----DATA
DUAL LINE RECEIVERS
The MC75107 and MC75108 are MTTL compatible dual line
receivers featuring independent channels with common voltage supply
and ground terminals. The MC75107 circuit features an active pull·up
(totem·pole) output. The MC75108 circuit features an open-collector
output configuration that permits the Wired-OR logic connection with
similar outputs (such as the MC5401/MC7401 MTTL gate or additional
MC75108 receivers). Thus a level of logic is implemented without
extra delay.
The MC75107 and MC75108 circuits are designed to detect input
signals of greater than 25 millivolts amplitude and convert the polarity
of the signal into appropriate MTTL compatible output logic levels.
•
•
•
•
•

High Common-Mode Rejection Ratio
High Input Impedance
High I nput Sensitivity
Differential Input Common-Mode Voltage Range of ±3.0 V
Differential Input Common-Mode Voltage of More Than ± 15 V
Using External Attenuator
• Strobe Inputs for Receiver Selection
• Gate Inputs for Logic Versatility
• MTTL or MDTL Drive Capability
• High DC Noise Margins
• MC55107 Available as JM38510/10401

DUAL LINE RECEIVERS
SILICON MONOLITHIC
INTEGRATED CIRCUITS

.'.
1

CIRCUIT SCHEMATIC
Vcco-~~---'--~------'-----~~------~---'
14

186

2.5 k

4 k

P SUFFIX
PLASTIC PACKAGE
CASE 646

L SUFFIX
CERAMIC PACKAGE
CASE 632

PIN CONNECTIONS

1.6 k

Vee

OUTPUT STROBE
2'1
20

VeE

2.5 k
INPUTS

OUTPUT STROBE STROBE

1 Y

IS

13

10

S

VEE~+---~----~----~-+--~------------~

mUTHTABLE
Differential
Inputs
A-B

11
28 0-+----+----,
INPUTS
2A \>+

VIO'" 25mV

12

-25 mV < VIO
< 25mV

850 850

186

4k

VIO" -25 mV

Components shown with dashed lines ara applicable to the MC75107 only.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
7-172

Strobes
G

S

LorH Lor H

Output
y
H

LorH

L

H

L

Lor H

H
Indeterminate

H

H

LorH

L

H

L

Lor H

H

H

H

L

MC75107, MC75108
MAXIMUM RATINGS ITA ~ O'C to + 70'C unless otherwise noted)
Rating

Symbol

Value

Unit

VCC
VEE

+7.0
-7.0

Vdc

Power Supply Voltages

VID

±6.0

Vdc

Common-Mode Input Voltage Range

Differential-Mode Input Signal Voltage Range

VICR

±5.0

Vdc

Strobe Input Voltage

VIIS)

5.5

Vdc

625
3.85

mW
mWrC

Power Dissipation (Package Limitation)

PD

Plastic and Ceramic Dual-In-Line Packages
Derate above TA ~ + 25'C
Operating Ambient Temperature Range

o to

TA

Tst~

Storage Temperature Range

+ 70

-65 to + 150

'c
'c

RECOMMENDED OPERATING CONDITIONS

Characteristic
Power Supply Voltages

Symbol

Min

Typ

Max

Unit

VCC
VEE

+4.75
-4.75

+5.0
-5.0

+5.25
-5.25

Vdc

-

-

-16

rnA

Differential-Mode Input Voltage Range

VI DR

-5.0

-

+5.0

Vdc

Output Sink Current

lOS

Common-Mode Input Voltage Range

VICR

-3.0

Vdc

VIR

-5.0

-

+3.0

Input Voltage Range, any differential
input to ground

+3.0

Vdc

Operating Temperature Range

TA

0

-

+70

'c

DEFINITIONS OF INPUT LOGIC LEVELS
Symbol

Test Fig.

Min

Max

Unit

High-Level Input Voltage (between differential inputs)

VIDH

1

0.025

5.0

Vdc

Low-Level Input Voltage Ibetween differential inputs)

VIDL

1

-5.0t

-0.025

Vdc

High-Level Input Voltage lat strobe inputs)

VI HIS)

3

2.0

5.5

Vdc

Low-Level Input Voltage lat strobe inputs)

VILIS)

3

0

0.8

Vdc

Characteristic

tThe algebraic convention, where the most positive limit is designated maximum, is used with Low-Level Input Voltage Level (VIOL)

ELECTRICAL CHARACTERISTICS ITA ~ O'C to + 70'C unless otherwise noted)
Symbol

Test Fig.

Min

Typ #

Max

Unit

High-Level Input Current to lA or 2A Input
IVCC ~ Max, VEE ~ Max, VID ~ 0.5 V, VIC = -3.0 V
to +3.0 V) 11)

IIH

2

-

30

75

/LA

Low-Level Input Current to lA or 2A Input
IVCC ~ Max, VEE ~ Max, VID ~ - 2.0 V, VIC ~ -3.0 V
to +3.0 V) 11)

IlL

2

-

-

-10

/LA

High-Leve! Input Current to 1G or 2G Input
IVCC ~ Max, VEE ~ Max, VI HIS) ~ 2.4 V) 11)
IVcc ~ Max, VEE ~ Max, VI HIS) ~ VCC Max) 11)

IIH

4

-

-

40
1.0

/LA
rnA

Low-Level Input Current to lG or 2G Input
IVCC ~ Max, VEE ~ Max, VILIS) ~ 0.4 V) 11)

IlL

4

-

-

-1.6

mA

High-Level Input Current to S Input
IVcc ~ Max, VEE ~ Max, VI HIS) ~ 2.4 V) 11)
(VCC ~ Max, VEE ~ Max, VIHIS) ~ VCC Max) (1)

IIH

4

-

-

80
2.0

/LA
rnA

Low-Level Input Current to S Input
IVCC ~ Max, VEE ~ Max, VILIS) = 0.4 V) 11)

IlL

4

-

-

-3.2

mA

High-Level Outut Voltage
IVcc ~ Min, VEE ~ Min, Iload ~ -400/LA,
VIC ~ -3.0 V to +3.0 V) 11)

VOH

3

-

-

-

V

Low-Level Output Voltage
IVee ~ Min, VEE ~ Min, Isink ~ 16 rnA,
VIC ~ -3.0 V to +3.0 V) 11)

VOL

3

-

-

0.4

V

High-Level Leakage Current
IVCC ~ Min, VEE ~ Min, VOH ~ VCC Max) 11)

ICEX

3

-

-

250

/LA

10SC

5

-

-

-

mA

High Logic Level Supply Current from VCC
(Vce ~ Max, VEE ~ Max, VID ~ 25 mV, TA ~ +25'C) (1)

ICCH+

6

-

18

30

mA

High Logic Level Supply Current from VEE
IVCC ~ Max, VEE = Max, VID ~ 25 mV, TA ~ + 25'C) 11)

ICCH-

6

8.4

-15

rnA

Characteristic

-

Short-Circuit Output Current 13)
IVcc ~ Max, VEE ~ Max) 11)

0

NOTES:
1. For conditions shown as Min or Max, use the appropriate value specified under recommended operating conditions for the applicable device type.
2. All typical values are at Vee = +5.0 V, VEE = -5.0 V, TA = + 25°e.
3. Not more than one output should be shorted at a time.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

7-173

MC75107, MC75108

SWITCHING CHARACTERISTICS

(Vcc

=+5.0 V. VEE =-5.0 V. TA = +250 CI

Characteristic
Propagation Delay Time, low-to-high level from

Svmbol

Test Fig.

tpLH(OI

7

differential inputs A and B to output
(RL = 390 n. CL = 50pFI
(RL =390 n. CL = 15 pFI
Propagation Oelav Time. high·t... low level from
differential inputs A and 8 to output
(RL' 390 n. CL = 50pFI
(RL =390 n. CL = 15 pFI

tPHL(OI

Propagation Oelav Time, low-to-high level, from strobe
input G or S to output

tPLH(SI

(RL
(RL

Min

TVp

Max

-

-

-

19

25

ns

-

ns

7

-

-

-

19

25
ns

7

=390 n. CL = 50 pFI
=390 n. CL = 15 pFI

Propagation Delay Time, high-ta-Iow level. from strobe
input G or S to output
IRL =390 n. CL = 50 pFI
IRL = 390 n. CL = 15 pFI

Unit

-

-

-

13

15

-

-

-

13

20

ns

7

tpHL(SI

-

15

TEST CIRCUITS
FIGURE 1 - VIDH and VIDL

FIGURE 2 - IIH Ind IlL

VCC 2G

veL.

~Not.
281

VIC

1
1

2V

I OPEN

L ___ .__~.;;.,.-;; __ ....J

.t

281

I

L-----¥GNO---l
NOTE: Each pair of diff.rentlal Inputs Is tasted
separately, The inputs of the other pair
.r. grounded

NOTE: When testlnl ana channel. the Inputs of
the other channel are grounded.

FIGURE 3 - VIH(SI. VILISI. VOH. VOL. and IOH

VIH(SI

~

VIL(SI

lG

~:,

S

Tabl. \-=-2G=-_ _ _ _--.
TEST TABLE

-

MC75t07

1,lnk' 'CEX

..,
VD-r T_

Tabla

I
I
I

I
I

-

Ilink. ICEX
2V_

I lood
VIC

-i

MC75t08

.1 STROBE 1G or 2G ISTROBE S
APPLY

ICEX
ICEX
ICEX

VOL

+25mV
-26mV
-25mV
-25mV

VIH(S)
VIL(S)
VIH(S)
VIHIS)

VIH S)
VIHIS)
VILIS)
VIHIS)

NOTES: 1. VIC"'-3.0Vto+3.0V.
2. When testing one channel. the inputs of the other channel
should be grounded.

1

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
7-174

VIO

TEST

VOH
VOH
VOH
VOL

Vo

I

MC75107, MC75108

TEST CI RCUITS Icontinued)
FIGURE 4 - IIHIG). IlLIG). IIHIS). and IILIS)

VIHIS)J

lG

5 ••

S

Test

-

Table

2G

VILIS)

I ILIS)

t

VIO

!

I

I

OPEN

I

S ••
Test

I
I

Table

12y
OPEN

TEST

INPUT lA

INPUT 2A

STROBE lG

STROBE S

'IH at Strobe 1G

+25 mV

Gnd

VIHIS)

Gnd

Gnd

IIH at Strobe 2G

Gnd

+25 mV

Gnd

Gnd

VIHIS)

STROBE 2G

+25 mV

+25 mV

Gnd

25 mV

Gnd

VILIS)

VIHIS)
4.5 V

Gnd

IlL at Strobe lG
I'L at Strobe 2G

Gnd

-25 mV

Gnd

4.5 V

-25 mV

-25 mV

4.5 V

VILIS)

VILIS)
4.5 V

'[ H at Strobe S

'I L at Strobe S

FIGURE 6 - ICC and lEE

FIGURE 5 - lOS

Vee

VEE

l_l_2~"':' ~ __ 1_--,
I
°1

lA

Gnd

I

VIO
25 mV

NOTES: 1. Each channel is tested separately.
2. Not more than one output should be tested at one time.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

7-175

MC75107, MC75108

TEST CI RCUITS (continued)
FIGURE 7 - PROPAGATION OELAY TIME TEST CIRCUIT
ANO WAVEFORMS

OUTPUT
MC75107

50 pF

See Note 3

See Note 4

1G

s

2G

1lse.

5 PF
Note 3

STROBE
INPUT e-------~~---J~~--_,

See Note 2

__________ •

INPUT~
A

100 mV

100 mV

I

I

I

t-- tp1---1

I

I

O"~"'

~

3V
1.5 V

I

I--

-------I

I

I
I

I

tp2

I
I

I

I
I

tpLH(D) ...,

I--

I

I

OV

'r-----~

I
I

I

STROBE
INPUT
G or S

200mV

I

I--tPHL(D)

I

I

'-------~.-+----

I

OV

k:-i ..:'"' '--< ;r1.-5-V-------------l---,f.~HVL~~

~

.. - -

~~J------J'

~

VOL

NOTES: 1. The pulse generators have the following characteristics: Zo = 50 n, t r '" tf = 10 ±5 ns, tpl = 500 ns, PRR = 1 MHz
tp2 ::: 1 }J.S, PR A '" 500 kHz.
2. Strobe input pulse is applied to Strobe 1 G when Inputs lA-18 are being tested, to Strobe S when Inputs lA-l B or 2A-2B
are being tested, and to Strobe 2G when inputs 2A-2B are being tested.
3. CL includes probe and jig capacitance.

4. All diodes are 1 N916 or equivalent.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

7-176

MOTOROLA

-

MC755110

SEMICONDUCTOR - - - - - -

TECHNICAL DATA

MONOLITHIC DUAL LINE DRIVERS
The MC75S110 dual line driver features independent channels
with common voltage supply and ground terminals. Each driver
circuit provides a constant output current that switches to either
of two output terminals subject to the appropriate logic levels at
the inpuUerminals. Output current can be switched "off" (inhibited) by appropriate logic levels at the inhibit inputs. Output current is nominally twelve milliamperes.
The inhibit feature permits use in party-line or data-bus applications. A strobe or inhibitor, common to both drivers, is included
to increase driver-logic versatility. With output current in the inhibited mode, IO(off) is specified so that minimum line loading
occurs when the driver is used in a party-line system with other
drivers. Output impedance of the driver in inhibited mode is very
high (the output impedance of a transistor biased to cutoff).
All driver outputs have a common-mode voltage range of -3.0
volts to +3.0 volts, allowing common-mode voltage on the line
without affecting driver performance.

DUAL LINE DRIVERS
SILICON MONOUTHIC
INTEGRATED CIRCUIT

LSUFFIX

CERAMIC PACKAGE
CASE 632

• Insensitive to Supply Variations Ov.er the Entire Operating
Range
•
•
•
•

".

MTTL Input Compatibility
Current-Mode Output (12 mA Typical)
High Output Impedance
Common-Mode Output Voltage Range
(-3.0 V to +3.0 V)

P SUFFIX

PLASTIC PACKAGE
CASE 646

• Inhibitor Available for Driver Selection

PIN CONNECTIONS
INHIBIT
OUTPUTS
IN~TS OUTPUTS
VCC 1Y 1Z VEE
D
2Z
2Y

TRUTH TABLE
LOGIC INPUTS

INHIBITOR
INPUTS

B

C

D

Y

Z

Lor H
Lor H
L
Lor H
H

Lor H
Lor H
Lor H
L
H

L
Lor H
H
H
H

Lor H
L
H
H
H

H
H
L
L
H

H
H
H
H
L

Low output represents the "on" state.
High output represents the "off" state.

6

4
1A

1B

LOGIC
INPUTS

1C
2C
INHIBIT
INPUT

2A

2B
LOGIC
INPUTS

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
7-177

OUTPUTS

A

MC75S110

MAXIMUM RATINGS (TA

~ 0 to + 70'C unless otherwise noted)

Ratings

Symbol

Value

Unit

Power Supply Voltages
(See Note 1)

VCC
VEE

+7.0
-7.0

Volts

Logic and Inhibitor Input Voltages
(See Note 1)

Vin

5.5

Volts

VOCR

-5.0 to + 7.0

Volts

1000
3.85

mWrC

Common-Mode Output Voltage Range
(See Note 1)
Power Dissipation (Package Limitation)
Plastic and Ceramic Dual In-Line Packages
Derate above TA ~ + 25'C
Operating Temperature Range

Po

TA

Storage Temperature Range

Tstg

o to

mW

+70

-65to +150

'C
'C

NOTE 1. These voltage values are with respect to the ground terminal.

RECOMMENDED OPERATING CONDITIONS (See Notes 1 and 2.)
Characteristic

Symbol

Min

Nom

Max

Unit

VCC
VEE

+4.75
-4.75

+5.0
-5.0

+5.25
-5.25

Volts

VOCR

-3.0

+3.0

Volts

Power Supply Voltages
Common-Mode Output Voltage Range

-

NOTE 2. When uSing only one channel of the Ime drivers, the other channel should be inhibited and/or Its outputs grounded.

DEFINITIONS OF INPUT LOGIC LEVELS'
Symbol

Test Figure

Min

Max

Unit

High-Level Input Voltage (at any input)

VIH

1,2

2.0

5.25

Volts

Low-Level Input Voltage (at any input)

VIL

1,2

0

0.8

Volts

Characteristic

* The algebraic conventioii, where the most positive limit is designated maximum, is used with Logic Level Input Voltage Levels only.

ages and supply currents at the worst case operating
condition.

THERMAL INFORMATION
The maximum power consumption an integrated circuit can tolerate at a given operating ambient temperature, can be found from the equation:
PD(TA)

=

TJ(max)

= Maximum Operating Junction Tempera-

ture as listed in the Maximum Ratings
Section
TA = Maximum Desired Operating Ambient
Temperature
ROJA (Typ) = Typical Thermal Resistance Junction to
Ambient

TJ(max) - TA
ROJA (Typ)

Where: PD(TA) = Power Dissipation allowable at a
given operating ambient temperature. This must be
greater than the sum of the products of the supply volt-

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

7-178

MC75S110

ELECTRICAL CHARACTERISTICS (TA

= 0 to

+ 70°C unless otherwise noted.)
Symbol

Test Figure

High-Level Input Current to lA, 1B, 2A or 2B
(VCC = Max, VEE = Max, VIHL = 2.4 V)"
(VCC = Max, VEE = Max, VIHL = VCC Max)

IIHL

1

Low-Level Input Current to lA, lB, 2A or 2B
(VCC = Max, VEE = Max, VILL = 0.4 V)

IILL

1

High-Level Input Current into lC or 2C
(VCC = Max, VEE = Max, VIHI = 2.4 V)
(VCC = Max, VEE = Max, VIHI = VCC Max)

II HI

1

Low-Level Input Current into lC or 2C
(VCC = Max, VEE = Max, VILI = 0.4 V)

IILI

1

High-Level Input Current into D
(VCC = Max, VEE = Max, VIHI
(VCC = Max, VEE = Max, VIHI

II HI

1

= 2.4 V)
= VCC Max)

Low-Level Input Current into D
(VCC = Max, VEE = Max, VILI

= 0.4 V)

Characteristic**

Min

Typ·

Max

Unit

-

-

-

-

40
1.0

p.A
mA

-

-

-3.0

mA

-

-

40
1.0

p.A
mA

-

-

-3.0

mA

-

80
2.0

p.A
mA

-

-

-6.0

mA

-

12

15

6.5

-

-

-

-

-

-

IILI

1

Output Current ("on" state)
(VCC = Max, VEE = Max)
(VCC = Min, VEE = Min)

10(on)

2

Output Current ("off" state)
(VCC = Max, VEE = Max)
(VCC = Min, VEE = Min)

10(off)

Supply Current from VCC (with driver enabled)
(VILL = 0.4 V, VIHI = 2.0 V)

ICC(on)

3

-

Supply Current from VEE (with driver enabled)
(VILL = 0.4 V, VIHI = 2.0 V)

IEE(on)

3

-

Supply Current from VCC (with driver inhibited)
(VILL = 0.4 V, VILI = 0.4 V)

ICC(off)

3

Supply Current from VEE (with driver inhibited)
(VILL = 0.4 V, VILI = 0.4 V)

IEE(off)

3

2

mA

p.A
100
100
35

mA

-

-50

rnA

-

-

35

rnA

-

-

-50

rnA

·AII typical values are at Vee = + 5.0 V, VEE = - 5.0 V.
**For conditions shown as Min or Max, use the appropriate value specified under recommended operating conditions,

SWITCHING CHARACTERISTICS (VCC = + 5.0 V, VEE = - 50 V, TA = + 25°C)
Symbol

Test Figure

Min

Typ

Max

Unit

Propagation Delay Time from Logic Input A or B to
Output Y or Z (RL = 50 ohms, CL = 40 pF)

tpLHL
tPHLL

4

9.0
9.0

15
15

ns

Propagation Delay Time from Inhibitor Input C or D
to Output Y or Z (RL = 50 ohms, CL = 40 pF)

tpLHI
tPHLI

4

-

16
13

25
25

ns

Characteristic

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

7-179

MC75S110
TEST CIRCUITS
FIGURE 1 Vee

IIH. IlL

VEE

,J----l,1Y

IIH

"~See

TEST TABLE

e-F'-lTable r"<>-t--L.-.-/
IlL

~IH

TEST AT
ANVINPUT

See

~ Table

ADJACENT INPUTS
NOT UNDER TEST

IIH

GND

IlL

4.5 V

.J-=c::..o-+--L~

~
IIH

See
_
Table
IlL

r='-O-t--L~

FIGURE 2 -

10(on) and 10(off)

Vce

VEE

,J----l,1Y

VIH--f See
VIL ....--l.Table I-""'O-f---L~

VIH

JT~~~e
.1-'=<>+-L..-/

VIL

VIH~See

VIL ~Table 1--"'''-o-f----1

L __ ~ ___ -.J

2Z

l
-=

GND

Arrows indicate actual direction
of current flow.

TEST TABLE
TEST
Ground all output pins
not under test.

1010n)

at output
IV or 2V

LOGIC INPUTS
1A or 2A

1B or 2B

VIL

VIL

VIL

VIH

VIH

VIL

INHIBITOR INPUTS
1C or 2C

D

VIH

VIH

10(on)

at output
IZ or 2Z

VIH

VIH

VIH

VIH

10(011)

at output
IY or 2Y

VIH

VIH

VIH

VIH

VIL

VIL

10(off)

at output
IZ or 2Z

VIL

VIH

VIH

VIH

VIH

VIL

Either

Either

state

state

10(011)

at output
IY. 2Y. lZ. or 2Z

VIL

VIL

VIL

VIH

VIH

VIL

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

7-180

MC75S110
TEST CIRCUITS Icontinued!
FIGURE 3 - ICC and lEE

TEST TABLE
TEST

ALL LOGIC
INPUTS

ALL INHIBITOR
INPUTS

Icclon!

Driver enabled

VIL

VIH

IEElon!

Driver enabled

VIL

VIH

ICCloff!

Driver inhibited

VIL

VIL

IEEloffi

Driver inhibited

VIL

VIL

FIGURE 4 - PROPAGATION DELAY TIMES TEST CIRCUIT AND WAVEFORMS
VCC

VEE

~~ro~~__~__-.-e°UTPUT
Y

I

I

'--___<>----_.. OUTPUT
Z

I
I

I

TO OTHER

lJ CHANNEL

-G~DI--

I
-.J

LOGIC
INPUT
A or B
INHIBIT
INPUT
Cor D

-----3.0 V
'-------- 0 V
t p2 - - -

------1------+--

r - - - - 3.OV

'-------J+---o

V
tPHLIIN!

OUTPUT
y
on
r-~r-----------------------off

OUTPUT
Z

I-----------------------on

20 = 50 n, tr "" tf = 10
PRR = 500 kHz.
2. CL includes probe and jig capacitance.
3. For simplicity. only one channel and the inhibitor connections are shown.

NOTES: 1. The pulse generators have the following characteristics:

:::!::

5.0 ns tp1 = 500 ns, PRR ::: 1.0 MHz. tp2 = 1,0 ms,

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

7-181

MOTOROLA

MC75172B
MC75174B

SEMICONDUCTOR-----TECHNICAL DATA

Advance Information

Quad EIA-485 Line Drivers with
Three-State Outputs

QUAD EIA-485 LINE DRIVERS
SILICON MONOLITHIC
INTEGRATED CIRCUIT

The Motorola MC75172B/174B Quad Line drivers are differential high speed
drivers designed to comply with the EIA-485 Standard. Features include
three-state outputs, thermal shutdown, and output current limiting in both
directions. These devices also comply with EIA-422-A, and CCID
Recommendations V.11 and X.27.
The MC75172B/174B are optimized for balanced multipoint bus
transmission at rates in excess of 10 MBPS. The outputs feature wide common
mode voltage range, making them suitable for party line applications in noisy
environments. The current limit and thermal shutdown features protect the
devices from line fault conditions. These devices offer optimum performance
when used with the MC75173 and MC75175 line receivers.
Both devices are available in 16-pin plastic DIP and 20-pin wide body surface
mount packages.

PSUFFIX
PLASTIC PACKAGE
CASE 648

o

SUFFIX
PLASTIC PACKAGE
CASE 751 D
(SO-20L)

• Meets EIA-485 Standard for Party Line Operation
• Meets EIA-422-A and CCID Recommendations V.11 and X.27
• Operating Ambient Temperature: -40°C to +85°C
• High Impedance Outputs

ORDERING INFORMATION

• Common Mode Output Voltage Range: -7 to + 12 V
• Positive and Negative Current Limiting

Device

• Transmission Rates in Excess of 10 MBPS

MC75172BDW

• Thermal Shutdown at 150°C Junction Temperature, (±20°C)

MC75172BP

• Single +5.0 V Supply

Temperature
Range

Package
SO-20L

- 40° to +85°C

Plastic DIP

MC75174BDW

• Pin Compatible with TI SN7517214 and NS !1A9617214
• Interchangeable with MC3487 and AM26LS31 for EIA-422-A Applications

MC75174BP

SO-20L
Plastic DIP

SIMPLIFIED BLOCK DIAGRAM
MC75172B

MC75174B

P Package

OW Package

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
7-182

MC751728, MC751748
MAXIMUM RATINGS
Rating

Symbol

Value

Unit
Vde
Vde

Power Supply Voltage

VCC

-0.5, +7.0

Input Voltage (Data, Enable)

Yin

+7.0

Input Current (Data, Enable)

lin

-24

mA

Applied Output Voltage, when in 3-State Condition (VCC
=5.0V)

V za

-10, +14

Vde

Applied Output Voltage, when VCC = a V

Vzb

±14

10

Self-Limiting

TstQ

-B5, +150

Output Current
Storage Temperature

"C

DeVices should not be operated at these limits. The "Recommended Operating Conditions table provides for
actual device operation.

RECOMMENDED OPERATING CONDITIONS
Characteristic

Symbol

Min

Typ

Max

Unit

VCC

+4.75

+5.0

+5.25

Vde

Vin

a

-

VCC

Vde

Vem

-7.0

+12

Vde

Output Current (Normal data transmission)

10

-B5

-

+65

mA

Operating Ambient Temperature (see text)
EIA-485
EIA-422

TA
-40

-

+85
+85

Power Supply Voltage
Input Voltage (All Inputs)
Output Voltage in 3-State Condition, or when VCC =

aV

"C

a

-

All limits are not necessarily functional concurrently.

ELECTRICAL CHARACTERISTICS (-40"e" TA" +85°e, +4.75 V" Vee" +5.25 V, unless otherwise noted.)
Characteristic
Output Voltage
Single-Ended Voltage
10=0
High @ 10 = -33 mA
Low @ 10 = +33 mA
Differential Voltage
Open Circuit (10 = 0)
RL = 54 Q (Figure 1)

Symbol

Min

Typ

Max

Vo
VOH
VOL

a

-

6.0

-

4.0
1.6

-

lVODll
IVOD2l

1.5
1.5

3.4
2.3

6.0
5.0

It.VOD2 l
lVOD2Al

-

5.0
2.2
5.0

200

IVOD3l

1.5

-

~VOD3l

-

5.0
2.9
5.0

Unit

Vde

Change in Differential', RL = 54 Q (Figure 1)
Differential Voltage, RL = 100 Q (Figure 1)
Change in Differential', RL = 100 Q (Figure 1)
Differential Voltage, -7.0 V,; Vem '; +12 V (Figure 2)
Change in Differential', -7.0 V,; Vem '; + 12 V (Figure 2)
Offset Voltage, RL = 54 Q (Figure t)
Change in Offset', RL = 54 Q (Figure 1)

~VOD2AI

VOS

~vosl

Output Current (Each Output)
Power Off Leakage, VCC = 0, -7.0 V,; VO'; +12 V
Leakage in 3-State Mode, -7.0 V,; VO'; + 12 V
Short Circuit Current to Ground
Short Circuit Current, -7.0 V,; VO'; +12 V

-

-

200
5.0
200

200

mVde
Vde
mVde
Vde
mVde
Vde
mVde

10(off)
10Z

-50
-50

a
a

+50
+50

~A

10SR
lOS

-150
-250

-

+150
+250

mA

·Vin sWitched from 0.8 to 2.0 V.
Typical values determined at +25°C ambient and +5.0 V supply.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

7-183

-

MC751728, MC751748
ELECTRICAL CHARACTERISTICS (--40 o e $ TA$ +85°e, +4,75 V $ Vee $ +5.25 V, unless otherwise noted.)
Characteristics
Inputs
Low Level Voltage (Pins 4 & 12, MC75174B only)
Low Level Voltage (All Other Pins)
High Level Voltage (All Inputs)

= 2.7 V (All Inputs)
= 0.5 V (All Inputs)
Clamp Voltage (All Inputs, lin =-18 rnA)
Thermal Shutdown Junction Temperature

TIMING CHARACTERISTICS (TA

Min

VIL(A)
VIL(B)
VIH

0
0
2.0

Typ

Max

Unit
Vdc

Current @ Vin
Current @ Vin

Power Supply Current (Outputs Open, VCC
Outputs Enable
Outputs Disabled

Symbol

-100

VIK

-1.5

Tjts

= +5.25 V)

-

IIH
IlL

ICC

-

-

0.7
0.8

-

VCC

0.2
-15

-

20

-

-

+150

-

IlA
Vdc

°c
rnA

-

60
30

70
40

Typ

Max

= +25°e, Vee = +5.0 V)

Characteristics

Symbol

Propagation Delay - Input to Single-ended Output (Figure 3)
Output Low-to-High
Output High-to-Low

Min

Unit
ns

tpLH
tpHL

-

23
18

30
30

tPLH(D)
tPHL(D)

-

15
17

25
25

Differential Output Transition Time (Figure 4)

tdr, idf

-

19

25

Skew Timing
ItPLHD - tPHLD I for Each Driver
Max - Min tPLHD Within a Package
Max - Min tpHLD Within a Package

tSK1
tSK2
tSK3

-

0.2
1.5
1.5

-

Propagation Delay -Input to Differential Output (Figure 4)
Input Low-to-High
Input High-to-Low

ns

ns
ns

Enable Timing
Single-ended Outputs (Figure 5)
Enable to Active High Output
Enable to Active Low Output
Active High to Disable (using Enable)
Active Low to Disable (using Enable)
Enable to Active High Output (MC75172B only)
Enable to Active Low Output (MC75172B only)
Active High to Disable (using Enable, MC75172B only)
Active Low to Disable (using Enable, MC75172B only)

-

ns

tPZH(E)
tPZL(E)
tPHZ(E)
tPLZ(E)
tPZH(E)
tPZL(E)
tPHZ(E)
tPLZ(E)

Differential Outputs (Figure 6)
Enable to Active Output
Enable to Active Output (MC75172B only)
Enable to 3-State Output
Enable to 3-State Output (MC75172B only)

-

-

-

-

48
20
35
30
58
28
38
36

60
30
45
50
70
35
50
50

47
56
32
40

-

ns
tpZD(e)
tPZD(E)
tPDZ(E)
tPDZ(E)

-

-

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

7-184

-

-

MC75172B, MC75174B

Figure 2. Common Mode Test

Figure 1. VDD Measurement

t

Vin
(O.B or 2.0 V)

Vin
(0.8 or 2.0 V)

VOD3

I

375

58
375

Figure 3. Propagation Delay, Single-Ended Outputs

Vee

2.3V

2Hl
Output

r

3.0V

15PF

3.0 V

Figure 4. Propagation Delay, Differential Outputs

NOTES:
1)
2)
3)
4)

S.G. set to: f S 1.0 MHz; duty cycle =50%; to tf, S 5.0 ns.
tsKI = I tpLHD - tPHLDI for each driver.
tSK2 computed by subtracting the shortest tpLHD from the longest tPLHD of the 4 drivers within a package.
tsK3 computed by subtracting the shortest tPHLD from the longest tpHLD of the 4 drivers within a package.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

7-185

I

MC751728, MC751748

Figure 5. Enable Timing, Single-Ended Outputs

~+3'~'~V

Vee
V,-

.A?if-o-.-0111-

Vout

1100

j1.SV

~ I~:J.
1PZH(E).

ov

~~.

....------------.

~ut

Vee

UV

r------------.:+3.OV
1.SV
1.SV
'----OV
tpLZ(E)

2.3V

Figure 6. Enable TIming, Differential Outputs

r - - - - - - - - - - - - , +3.0 V
SOpF

1.SV

1.SV

t

tPZD(E)

VOD

I
1.SV

VOD
Disabled

Active

NOTES:
1) S.G. set to: f s 1.0 MHz; duty cycle = 50%; tr• If. S 5.0 ns.
2) Vin is inverted for Enable measurements.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

7-186

VOH

MV

MC75172B, MC75174B
Figure 7. Single-Ended Output Voltage
versus Output Sink Current

Figure 8. Single-Ended Output Voltage
versus Temperature

2.0

2.0

- --

~1.5

./
13
(!J

~
!::; 1.0

10L - 27.8 rnA

- r---

10L = 20.0 rnA

!3o
.OJ

090.5
4.75V~VCC~5.25V

4.75 V ~ VCC

_

~

5.25 V

TA = 25°C

o
o

10

20

30
40
50
10L, OUTPUT CURRENT (rnA)

1.0
-40

70

60

-20

Figure 9. Single-Ended Output Voltage
versus Output Source Current
5.

~

w

(!J

o~

4.0

R- VCC 5.00 V

~

f--

~

-

13

w

(!J

VCC = 4.75 V

!:§

3.75

!3o

3.5

I

~ 3. 0

!3

-

10H - 27.8 rnA

±

09

TA = 25°C

VCC = 4.75 V

3.25
-10

-20
-30
-40
-50
10H, OUTPUT CURRENT (rnA)

-60

-40

-70

-20

~
w

w

85

4.0

1§

3.0f-"..-""

!::;

!3 2.01---"'-'-+---+-

0
-'

3.0
10

0..

t-

0.0 rnA

::>

~

,;;

~

10-2.8mA

2.0

tZ
W

il'!

a:

tt 1.01-----1---+--+--+---+---+---1
~

60

(!J

!::;

~

40

Figure 12. Output Differential Voltage
versus Temperature

(!J

1§

20

TA, AMBIENT TEMPERATURE (OC)

Figure 11. Output Differential Voltage
versus Load Current

~

85

I-

10H - 20.0 rnA

~
!::;

o
±
::;9 2. 0

1. 0

60

Figure 10. Single-Ended Output
Voltage versus Temperature

VCC ~ 5.25 V

~
4.0

0
20
40
TA, AMBIENT TEMPERATURE (0C)

1

~~~~o
oL-__ __- L__
o
10
20
~

Voo

~

~
is
u..

TA=25°C

____L -__

~

30
40
50
10, OUTPUT CURRENT (rnA)

__- L__

60

6
~

~

70

1.0

f--

o

-40

0.8or~0
2.0V
I

-20

Iv

I

I

20
40
TA, AMBIENT TEMPERATURE (OC)

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

7-187

00

Vce = 4.75 V

I

60

85

MC75172B, MC75174B
Figure 13. Output Leakage Current
versus Output Voltage

Figure 14. Output Leakage Current
versus Temperature

2.0

20

.6 1.0

:<" 15
.3!z 10

:<"

!z

!l!

~

~ 5.0

::;,

'-'
w

~

~

rJA

where:

RaJA = package thermal resistance (typ.
70°C/W for the DIP package, 85°C/W for
SOIC package);
TJmax = max. operating junction
temperature, and
TA = ambient temperature.
Since the thermal shutdown feature has a trip point of
+ 150°C, ± 20°C, TJmax is selected to be + 130°C. The power
dissipated within the package is calculated from:
PD
= {[(VCC - VOH) • IOHI + VOL· loll} each driver
+ (VCC • ICC)
where:
VCC = the supply voltage;
VOH, VOL are measured or estimated from
Figures 7 to 10;
ICC = the quiescent power supply current
(typ. 60 rnA).
As indicated in the equation, the first term (in brackets) must
be calculated and summed for each of the four drivers, while
the last term is common to the entire package.
Example 1:TA = +25°C, IOl = IOH = 55 rnA for each driver,
VCC= 5.0 V, DIP package. How many drivers per package can
be used?
Maximum allowable power dissipation is:

Figure 17. Unit load Definition

Reprinted from BA-4B5. Electronic Industries Association,
Washington,DC.

PDmax=
Since the power supply current of 60 rnA dissipates 300
mW, that leaves 1.2 W (1 .5 W - 0.3 W) for the drivers. From
Figures 7 and 9, VOL =1.75 V, and VOH =3.85 V. The power
dissipated in each driver is:
{(5.0 - 3.85) • 0.055} + (1.75 • 0.055) = 160 mW.
Since each driver dissipates 160 mW, the four drivers per
package could be used in this application
Example 2:TA = +85°C, IOl = 27.8 rnA, IOH = 20 rnA for
each driver, VCC = 5.0 V, SOIC package. How many drivers
per package can be used?
Maximum allowable power dissipation is:
PDmax=
Since the power supply current of 60 rnA dissipates 300
mW, that leaves 230 mW (530 mW - 300 mW) for the drivers.
From Figures 8 and 10 (adjusted for VCC =5.0V), VOl=I.38
V, and VOH =4.27 V. The power dissipated in each driver is:
{(5.0 - 4.27) • 0.020} + (1.38 • 0.0278) = 53 mW
Since each driver dissipates 53 mW, the use of all four
drivers in a package would be marginal. Options include
reducing the load current, reducing the ambient temperature,
and/or providing a heat sink.

A load current within the shaded regions represents an
impedance of less than one U.L., while a load current of a
magnitude outside the shaded area is greater than one U.L. A
system's total load is the sum of the unit load equivalents of
each receiver's input current, and each disabled driver's
output leakage current. The 60Q termination resistance
mentioned above allows for two 120Q terminating resistors.
Using the EIA·485 requirements (worst case limits), and
the graphs of Figures 7 and 9, it can be determined that the
maximum current an MC75172B or (MC75174B) driver will
source or sink is =65 rnA.
System Example
An example of a typical EIA·485 system is shown in
Figure 18. In this example, it is assumed each receiver'S input
characteristics correspond to 1.0 U.L. as defined in Figure 17.
Each "off' driver, with a maximum leakage of ±50 I1A over the
common mode range, presents a load of =0.06 U.L. The total
load for the active driver is therefore 8.3 unit loads, plus the
parallel combination of the two terminating resistors (60Q). It
is up to the system software to control the driver Enable pins
to ensure that only one driver is active at any time.
Termination Resistors
Transmission line theory states that, in order to preserve
the shape and integrity of a waveform traveling along a cable,
the cable must be terminated in an impedance equal to its
characteristic impedance. In a system such as that depicted
in Figure 18, in which data can travel in both directions, both
physical ends of the cable must be terminated. Stubs, leading
to each receiver and driver, should be as short as possible.
leaving off the terminations will generally result in
reflections which can have amplitudes of several volts above
Vccorbelowground. These overshoots and undershoots can
disrupt the driver and/or receiver operation, create false data,
and in some cases damage components on the bus.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
7-190

MC75172B, MC75174B

Figure 18. Typical EIA-485 System

TTL

TTL

TTL
120Q
Twisted
Pair

5 "off" drivers (@0.06 U.L each),
+8 receivers (@ 1.0 U.L each) = 8.3 Unit Loads
RT = 120 Q at each end of the cable.

TTL
TTL

TTL

TTL
TTL

TTL

TTL

TTL

NOTES:
1) Terminating resistors RT must be located at the physical ends of the cable.
2) Stubs should be as short as possible.
3) Circuit ground of all drivers and receivers must be connected via a dedicated wire within the cable.
Do not rely on chassis ground or power line ground.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
7-191

MC75172B, MC75174B
Comparing System Requirements

I

EIA-485

Symbol

EIA-422-A

V.11

and X.27

GENERATOR (Driver)
Output Impedance (Note 1)
Open Circuit Voltage
Differential
Single·Ended

Zout
VOCD
VOCS

loaded Differential Voltage

VOD

Differential Voltage Balance

dVOD

Output Common Mode Range
Offset Voltage
Offset Voltage Balance
Short Circuit Current

Not Specified

< loon

50tol00n

1.5 to 6.0 V
<6.0V

56.0 V
56.0 V

56.0 V. w/3.9 kn. load
56.0 V. w/3.9 kn. load

1.5 to 5.0 V. w/54 n load

;, 2.0 V or;, 0.5 VOCD.
wlloon load

;, 2.0 V or;, 0.5 VOCD.
wllOO n load

<200 mV

5400 mV

< 400 mV

VCM

-7.0 to +12 V

Not Specified

Not Specified

VOS

-1.0 < VOS < 3.0 V

53.0 V

53.0V

< 200 mV

5400 mV

< 400 mV

5250 mA from -7.0 to
+12V

5 150 mA to ground

5 150 mA to ground

dVOS
lOS

leakage Current (VCC = 0)

10lK

Not Specified

:5 100 f1A to -{).25 V thru
+6.0V

:5100

f1A to ± 0.25 V

Output Rise/Fall Time (Note 2)

tr.tf

:5 0.3 TB. w/54 Q//1150 pF
load

:50.1 TBor520ns.
wllOO n load

:50.1 TB or:5 20 ns.
wllOO n load

Vth

±200 mV

± 200 mV

±300 mV

:53.0 V

:53.0V

RECEIVER
Input Sensitivity
Input Bias Voltage

Vbias

:53.0 V

Input Common Mode Range

Vcm

-7.0 to +12 V

-7.0 to +7.0 V

-7.0 to +7.0 V

Dynamic Input Impedance

Rin

Spec number of U.L.

;,4kn

;,4kn

NOTES:
1) Compliance with V.11 and X.27 (Blue book) output impedance requires external resistors in series with the outputs of the MC75172B and MC75174B.
2) TB =Bit time.

Additional Information
Copies of the EIA Recommendations (EIA-485 and EIA-422-A) can be obtained from the Electronics Industries Association.
Washington. D.C. (202-457-4966). Copies of the CCID Recommendations (V.11 and X.27) can be obtained from the United States
Department of Commerce. Springfield. VA (703-487·4600).

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
7-192

SN75173
SN75175

MOTOROLA

-

SEMICONDUCTOR

'~,'

•

' ):'

•

'oil

~.

,"'"

4'"

TECHNICAL DATA

QUAD EIA-485 LINE RECEIVERS

QUAD EIA-485
LINE RECEIVERS WITH
THREE-STATE OUTPUTS

The Motorola SN75173/175 are monolithic quad differential line
receivers with three-state outputs. They are designed specifically
to meet the requirements of EIA-485, EIA-422A123A Standards and
CCITT recommendations.
The devices are optimized for balanced multipoint bus transmission at rates up to 10 megabits per second. They also feature
high input impedance, input hysteresis for increased noise immunity, and input sensitivity of:!: 200 millivolts over a common mode
input voltage range of -12 volts to 12 volts. The SN75173/175
are designed for optimum performance when used with the
SN75172 or SN75174 quad differential line drivers.

SILICON MONOLITHIC
INTEGRATED CIRCUITS

J SUFFIX
CERAMIC PACKAGE
CASE 620

• Meets EIA Standards EIA-422A and EIA-423A, EIA-485
• Meets CCITT Recommendations V.l 0, V.ll, X.26, and X.27
• Designed for Multipoint Transmission on Long Bus Lines in
Noisy Environments
D SUFFIX
PLASTIC PACKAGE
CASE 7518
(SO-16)

• 3-State Outputs
o Common-Mode Input Voltage Range ... -12 V to 12 V
" Input Sensitivity ... :!: 200 mV

16

• Input Hysteresis ... 50 mV Typ
• High Input Impedance ... 1 EIA-485 Unit Load
N SUFFIX
PLASTIC PACKAGE
CASE 648

• Operates from Single 5.0 V Supply
• Low Power Requirements
o Plug-In Replacement for MC3486 (SN75175)
AM26LS32 (SN75173)

PIN CONNECTIONS
SN75173

SN75175

Vee

Vee
Output

Output

A

A

3-5tate

3-5tate

Control

Output
B

Control

Output

3-5tate

Output

Control

e

e

Inputs
B

Output
8

Ale

3-5tate
Control

BID
Output

Output
D

Inputs

D

Inputs

e

e
Inputs
D

Inputs

D

Gnd

Gnd

ORDERING INFORMATION

ORDERING INFORMATION
Device

Temperature

Package

Device

Temperature

Package

SN75173J

o to +70°C
o to +70°C

Ceramic DIP

SN75175J

Ceramic DIP

Plastic DIP

SN75175N

o to +70°C
o to +70 o C

SN75173N

MOTOROLA LlNEARIiNTERFACE ICs DEVICE DATA

7-193

Plastic DIP

SN75173, SN75175
MAXIMUM RATINGS
Rating
Power Supply Voltage
Input Common Mode Voltage
Input Differential Voltage

Symbol

Value

VCC

7.0

Vdc

VICM

±25

Vdc

Unit

VID

±25

Vdc

Three-State Control Input Voltage

VI

7.0

Vdc

Output Sink Current

10

50

rnA

Storage Temperature

Tstg

-65 to +150

°c

TJ

+175
+150

°C

Symbol

Value

Unit

VCC

4.75 to 5.25

Vdc

TA

o to +70

°c

Input Common Mode Voltage Range

VICM

-12to+12

Vdc

Input Differential Voltage Range

VIDR

-12 to +12

Vdc

Operating Junction Temperature -

Ceramic Package
Plastic Package

RECOMMENDED OPERATING CONDITIONS
Rating
Power Supply Voltage
Operating Ambient Temperature

ELECTRICAL CHARACTERISTICS (Unless otherwise noted. minimum and maximum limits apply over recommended
temperature and power supply voltage ranges. Typical values are for TA =25°C, Vee = 5 0 V and VICM =0 V) (Note 1)
Characteristic
Dillerential Input Threshold Voltage (Note 21
(-12 V';; VICM';; 12 V. VIH = 2.0 VI
(10 = -0.4 rnA. VOH;;' 2.7 VI
(10 = 16 rnA. VOL';; 0.5 VI
Input Hysteresis

Symbol

Min

Typ

Max

VT+ - VT_

Input line Current (Dillerential Inputsl
(Unmeasured Input at 0 V - Note 31
(VI = +12 VI
(VI = -7.0 VI

II

Input Resistance (Note 41

ri

Unit
V

VTH(DI

-

-

0.2
-0.2

-

50

-

mV
rnA

-

-

1.0
-0.8

1 Unit

-

-

-

Load
Input Balance and Output level (Note 31
(-12V';;VICM';; 12 v. VIH=2.0VI
(10 = -0.4 rnA. VID = 0.2 VI
(10 = 8.0 rnA. VID = -0.2 VI
(10 = 16 rnA. VID = -0.2 VI

V
VOH
VOL
VOL

2.7

-

-

0.45
0.5

High Logic State (Three-State Control)

VIH

2.0

-

-

Input Voltage -

Low Logic State (Three-State Control)

VIL

-

-

0.8

Input Current (VIH = 2.7 VI
(VIH = 5.5 VI

High Logic State (Three-State Control)

IIH

Input Current (VIL = 0.4 VI

Low Logic State (Three-State Control)

Input Voltage

~

-

V
V
pA

-

-

20
100

IlL

-

-

-100

pA

Input Clamp Diode Voltage (Three-State Control)
(11K = -18 mAl

VIK

-

-

-1.5

V

Output Third State Leakage Current
(VI(DI = 3.0 V. VIL = O.B V. Vo = 0.4 VI
(VI(D) = -3.0 V. VIL = 0.8 V. Vo = 2.4 VI

10Z

-

-

-20
20

Output Short-Circuit Current (Note 51
(VI(DI = 3.0 V. VIH = 2.0 V. Vo = 0 VI

lOS

-15

-

-85

rnA

Power Supply Current
(VIL = 0 VI (All Inputs Groundedl

ICC

-

-

70

rnA

pA

NOTES:
4. Input resistance should be derived from input line current specifications and is shown for reference only. See EIA-485 and input
line current specifications for more specific input resistance information.
5. Only one output at a time should be shorted.

1. All currents into device pins are shown as positive, out of device
pins are negative. All voltages referenced to ground unless otherwise noted.
2. Differential input threshold voltage and guaranteed output levels
are done simultaneously for worst case.
3. Refer to EIA-485 for exact conditions. Input balance and guaranteed output levels are done simultaneously for worst case.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

7-194

SN75173, SN75175
SWITCHING CHARACTERISTICS (Unless otherwise noted VCC" 5 0 V and TA" 25'C)

Characteristic
Propagmion Delay Time (Output High to Low)
(Output Low to High)

SN75173

Symbol

Min

SN75175

Typ

Max

25
25

35
35

-

20
20
16
16

40

--

Min

Unit

Typ

Max

25
25

35
35

16
19
11
11

35
35
30
30

Differential Inputs to Output

ns
tpHL(DI
tPLH(D)

-

tpLZ
tpHZ
tpZH
tpZL

-

Propagation Delay Time - Three-State Control to Output
(Output Low to Third State)
(Output High to Third State)
(Output Ttlird State to High)
(Output Third State to Low)

-

-

---- - - -

ns

-

-

30
22
25

-

SN75173

SN75175

FUNCTION TABLE (EACH RECEIVER)

FUNCTION TABLE (EACH RECEIVER)

--

3-5tate
Differential Inputs

VID;;' 0.2 V
-0.2 V< VID< 0.2 V
VIDS; -0.2 V

X

3-5tate

Differential Inputs

Control

4

12

H

X

X

L

H

X

X

L

H

X

Output
Y

Control

Output
Y
H

VID;;' 0.2 V

H

H
H

-0.2 V < VID < 0.2 V

H

,

VIDS; -0.2 V

H

L

,?

X

L

Z

X

L

L
L

L

H

Z

H:: high level
L :: low level
X:: irrelevant

---

( ::: indeterminate
Z :: high-impedance (off)

--

SWITCHING TEST CIRCUIT AND WAVEFORMS
FIGURE 1 -

PROPAGATION DELAY, DIFFERENTIAL INPUT TO OUTPUT

To Scope

To Scope

(Input(

(Output)

I

51

CL" 15 pF
(Includes Probe

":'"

and Stray

'" ~::1'" ~'

tPL~(~)

--- -

tpHL(D)

VOH-----t-r-----___

Capacitance)

+1.5 V
Input Pulse Characteristics tTLH:;; tTHL:;; 6.0 ns (10% to 90%)
PRR:;; 1.0 MHz, 50% Duty Cycle

+2.0 V
3-5tate Control

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

7-195

SN75173, SN75175
SWITCHING TEST CIRCUIT AND WAVEFORMS (continued)
FIGURE 2 -

PROPAGATION DELAY. THREE·STATE CONTROL INPUT TO OUTPUT

Input Pulse Characteristics -

To Scope

tTLH ~ tTHL ~ 6.0 ns (10% to 90%)
PRR ~ 1.0 MHz. 50% Duty Cycle

(Input)

~

n.:..:.:rl
!,,
:,,
I

I

r--+--<>-\

To Scope
(Output)

I

Pulse
Generator

SWI

2.0 k
--+-1--.--'11'.,...-____
____. +5.0 V

>--41---.....- -....

+1.5 V for tpHZ and tPZH
-1.5 V for tPLZ and tpZL

Differential
Inputs

CL ~ 15 pF
(Includes Probe
and Stray
Capacitance)

I

All Diodes 1N916
or Equivalent

5.0 k

":'"

tpLZ

tpHZ

3.0V
Input

3.0V

0 V ___

-l
=1.3 V
Output
VOL

1.5 V

r-tPLZ

Ein

SWI Closed

-tJ----\
--1'iLv L

o V ---VOH-

-I

-

=1.3 V

0V

===---------.0 V

3.0V
Input

SWI Open
SW2 Closed

o V ____

~

SWI Closed
SW2 Open

Output
~ ~
VOL ______________ 0 V

TYPICAL CHARACTERISTICS
(Both Device Types, Unless Otherwise Noted)

FIGURE 3 - OUTPUT VOLTAGE versus
DIFFERENTIAL INPUT VOLTAGE

Vce
TA

4.0

1.5 V

_~ltPZL

=5.0V-VSE

OV ____ L J 1 . 5 V

5.0

SWI Closed
SW2 Closed

~IT~P::
~-

VOH

3.0V
1.5 V

----

Eout

-----=t--------

Input

1.5 V

oV

SW2 Closed

~

~

5.0 V
25°e

VeM~-12V

VCM

~

+12 V

o
-140-120-100-80 -60 -40 -20

0

20 40 60 80 100 120 140

VID. DIfFERENTIAL INPUT VDLTAGE (mV)

MOTOROLA LlNEARIiNTERFACE ICs DEVICE DATA

7-196

SN75173, SN75175
TYPICAL CHARACTERISTICS (continued)
FIGURE 5 - OUTPUT VOLTAGE versus (INVERTED)
3-STATE CONTROL VOLTAGE - SN75173

FIGURE 4 - OUTPUT VOLTAGE versus
3-STATE CONTROL VOLTAGE
5.0

;;;4.0

~

-

2:-

Vee

5.0

I
Vee J5.25 V

15.0 V

4.0

§

f
I

I
o

o

0.5

~

I

1.0
1.5
2.0
2.5
3.0
VI. 3-STATE CONTROL VOLTAGE (VOLTS)

I
3.5

2.0

5
~
01.0

?
o

o

4.0

FIGURE 6 - HIGH LEVEL OUTPUT VOLTAGE
versus OUTPUT CURRENT

VID = +0.2 V
TA =25°e

~ 4.0

~

w

to

~
:>

;o~

I'-.'\.'\.

""

2.0

w

i!i

,r,

§?

0

~Vee

~'\.

Vee = 4.75 V~

~ 1.0

"

g
o

r--

o

-5.0

0.5

/

«
!:o

o

:>

~
5

= 5.0 V

/

~ 0.2

-35

-40

0

-

5.0

10
15
20
25
30
10L. LOW LEVEL OUTPUT CURRENT (rnA)

35

40

FIGURE 9 - LOW LEVEL OUTPUT VOLTAGE
versus TEMPERATURE
0.5

~

~ 3.5

«

~

~
:>

!:o

§; 3.0

...

~

~ 2.5
=>

1.5

Vee =5.0 V_
TA =25°C

0

-10
-15
-20
-25
-30
10H. HIGH LEVEL OUTPUT CURRENT (rnA)

5.0

~

V

L

~ o.1 /

f\-I'-I'-.
.

~4.5
2:- 4.0

2.0

4.0

/

i!i

~

""':-,.

3.5

/

0.3

FIGURE B - HIGH LEVEL OUTPUT VOLTAGE
versus TEMPERATURE

~

1.0
1.5
2.0
2.5
3.0
VI. 3-STATE CONTROL VOLTAGE (VOLTS)

~ 0.4

~ ~ee = 5.25 V

3.0

0.5

FIGURE 7 - LOW LEVEL OUTPUT VOLTAGE
versus OUTPUT CURR ENT

5.0

~

VIO = to.2 V I
Load = 8.0 kO to Gnd
TA = 25°C

«

!:o

SN75173 VI to Pin 4. Pin 12 = 2.0 V
SN75175 VI to Pin 4 or 12

~1.0

Vee = 5.0 V -

Vjlo IPin 12.
Pin 4 = 0 V

to

VIO = +0.2 V
Load = 8.0 kO to Gnd
TA = 25°C

~ 2.0

5.25 V

2:- 3.0 r- Vee = 4.75 V

I

~

:>

1

~

Vee = 4.75 V

~ 3.0

r-vee

;;;

SN751~3

50

Vee = 5.0 V
10H = 400 I'A- f--

0.4

0.3
Vee = 5. 0 V
10L = 16 rnA

0.2

i!i
3:

~ 1.0

9 0.1

" 0.50

..;.

~

§?

0

:>

o

10

20

30
40
50
60
70
80
TA. FREE AIR TEMPERATURE (0C)

90

100

U

10

20

HO
30
40
50
70
80
IA. FREE AIR TEMPERATURE (0C)

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
7-197

90

100

MOTOROLA

-

ULN2068B

SEMICONDUCTOR - - - - - -

TECHNICAL DATA

QUAD 1.5 A SINKING HIGH CURRENT SWITCH

QUAD 1.5A
DARLINGTON SWITCH

The ULN2068B is a high-voltage, high-current quad Darlington
switch array designed for high current loads, both resistive and
reactive, up to 300 watts.
It is intended for interfacing between low level (TTL, DTL, LS
and 5.0 V CMOS) logic families and peripheral loads such as
relays, solenoids, dc and stepping motors, multiplexer LED and
incandescent displays, heaters, or other high voltage, high
current loads.
The Motorola ULN2068B is specified with minimum guaranteed
breakdown of 50 V and is 100% tested for safe area using an
inductive load. It includes integral transient suppression diodes.
Use of a predriver stage reduces input current while still allowing
the device to switch 1.5 Amps.
It is supplied in an improved 16-Pin plastic DIP package with
heat sink contact tabs (Pins 4, 5 and 12, 13). A copper alloy lead
frame allows maximum power dissipation using standard cooling
techniques. The use of the contact tab lead frame facilitates attachment of a DIP heat sink while permitting the use of standard layout
and mounting practices.

SIUCON MONOUTHIC
INTEGRATED CIRCUIT

B SUFFIX
PLASTIC PACKAGE
CASE 648C

• TTL, DTL, LS, CMOS Compatible Inputs
• 1.5 Amp Maximum Output Current
• Low Input Current
PIN CONNECTIONS

• Internal Freewheeling Clamp Diodes
• 100% Inductive Load Tested
• Heat Tab Copper Alloy Lead Frame for Increased Dissipation
K

MAXIMUM RATINGS ITA = 25"C and ratings apply to anyone device in the
package unless otherwise noted)
Rating

C

Symbol

Value

Unit

Output Voltage

Vo

50

V

Input Voltage INote 1)

VI

15

V

Supply Voltage

Vs

10

V

IC

1.75

A

25

mA

Collector Current INote 2)
Input Current INote 3)

II

Operating Ambient Temperature Range
Storage Temperature Range
Junction Temperature

TA

o to

+70

·C

Tstg

-55 to +150

·C

TJ

150

·C

B

Gnd
Gnd

Gnd

B

B

NC

CW.......r..--UU

Notes:
1. Input voltage referenced to ground.
2. Allowable output conditions shown in Figures 11 and 12.
3. May ba IImilBd by max input vollBga.

Vs PARTIAL SCHEMATIC

ORDERING INFORMATION*

r--~--"""o()C
H~---j--<) K

Device

ULN2068B

II

Temperature
Range
O'C to +70"C

II

Package
Plastic DIP

'Othar options of this ULN2060/2070 series ara
available for volume applications. Contact your

local Motorola Sales Representative.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

7-198

ULN2068B

ELECTRICAL CHARACTERISTICS (TA = 25'C unless otherwise noted.1
Fig.

Ch.racterlstlc
Output Leakage Current
(VCE = 50 VI
(VCE = 50 V, TA = 70'CI

Min

Typ

ICEX

-

-

-

-

6.0

-

1.0

I

I

Collector-Emiller Saturation Voltage
(lC = 500mA
(lC = 750mA
(lC=I.0A
(lC = 1.25 A

Symbol

VCE(satl
2

V' = 24VI
,n
•

Input Current- On Condition
(VI = 2.4 VI
(VI = 3.75 VI

4

Input Voltage - On Condition
(VCE = 2.0 V, IC = 1.5 AI

5

Inductive Load Test
(VS = 5.5 V, VCC = 24.5 V,
tpw = 4.0msl

3

SupplV Current
(lC = 500 mA, Yin = 2.4 V, Vs = 5.5 VI

8

IS

-

tpHL

IUonl

VUonl
<1Vout

Turn-On Delav TIme
(50% Elto 50% EOI
Turn-Off Delav Time
(50% EI to 50% EOI
Clamp Diode Leakage Current
(VR = 50 VI
(VR = 50 V, TA = 70'CI

6

Clamp Diode Forward Voltage
(IF = 1.0 AI
(IF = 1.5 AI

7

tpLH
IR

VF

j.

0---<_-0 Open

FIGURE 6

FIGURE 5
Open

FIGURE 7

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

7-204

ULN2801, ULN2802, ULN2803, ULN2804
TYPICAL CHARACTERISTIC CURVES - TA = 25°C
(unless otherwise noted)
OUTPUT CHARACTERISTICS
FIGURE 9 - OUTPUT CURRENT versus
INPUT CURRENT

FIGURE 8 - OUTPUT CURRENT versus
SATURATION VOLTAGE

I

:::>
u

~

~

.§. 600

/

I-

~

/
V

All Types
400

~

8

.

/

1600

200

-

...<=

~5

/

!;j
=!

8

~

V

o
o

400

c

/

/

V

All Types

:::>

1~

1~

L

200

,/

o
o

2.0

./

V

200

400

600

800

liN. INPUT CURRENT ("A!

VCE( ••t!. SATURATION VOLTAGE (VOLTS!

INPUT CHARACTERISTICS
FIGURE 11 - ULN2803 INPUT CURRENT
versus INPUT VOLTAGE

FIGURE 10- ULN2802 INPUT CURRENT
versus INPUT VOLTAGE

2.0

2.0

.. 1.5

I
~

/""

~

~ 0.5

.§.

V

~

~

,/'

./

~0.5

/'

,../

/

<=

B 1.0

./

o
12

/'

i

V

B 1.0

/

.. 1.5

,/'

.§.

./

./

o
14

16

18

20

22

24

26

2.0

2.5

3.0

VIN. INPUT VOLTAGE (VOLTS!

3.5

FIGURE 12 - ULN2804 INPUT CURRENT
versus INPUT VOLTAGE

2.0

.. 1.5
.§.

i

B 1.0

I-

~
~

~ 0.5

"........

o
5.0

4.0

4.5

VIN. INPUT VOLTAGE (VOLTS!

6.0

-7.0

- f..--

I-""'"

8.0

9.0

10

11

12

VIN. INPUT VOLTAGE (VOLTS!

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
7-205

5.0

5.5

6.0

ULN2801, ULN2802, ULN2803, ULN2804

REPRESENTATIVE CIRCUIT SCHEMATICS

1/8 ULN2802

1/8 ULN2801

7.0V
NOM.

+----1M----1t-O Pin 10
I
I

*

'--_ _

I
I

*
I

I

~_+--J

I _______ _
L

+---Ii----1t-O Pin 10

I

1... _ _ _ _ _

* ____ _
1/8 ULN2804

1/8 ULN2803

+----1M---,;--o

+----1M----1r-O Pin 10

I

I

I

I

I

L __

* ______ _

:

L ___

* ______ _ *

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
7-206

3.0 k

__ .JI

Pin 10

Communication Circuits

In Brief ...
Page
RF
Radio communication has greatly expanded its scope in
the past several years. Once dominated by public safety
radio, the 30 to 1000 MHz spectrum is now packed with
personal and low cost business radio systems. The vast
majority of this equipment uses FM or FSK modulation and
is targeted at short range applications. From mobile phones
and VHF marine radios to garage door openers and radio
control/ed toys, these new systems have become a part of
our lifestyle. Motorola Linear has focused on this technology,
adding a wide array of new products including complete
receivers processed in our exclusive 3.0 GHz MOSAIC® 1.5
process. New surface mount packages for high density
assembly are available for all of these products, as is a
growing family of supporting applications notes and
development kits.

Telephone & Voice/Data
Traditionally, an office environment has utilized two
distinctly separate wired communications systems Telecommunications and Data communications. Each had
its individual hardware components complement, and each
required its own independent transmission line system:
twisted wire pairs for Telecom and relatively high priced
coaxial cable for Datacom. But times have changed. Today,
Telecom and Datacom coexist comfortably on inexpensive
twisted wire pairs and use a significant number of
components in common. This has led to the development
and enhancement of PBX (Private Branch Exchanges) to
the point where the long heralded "office of the future, " with
simultaneous voice and data communications capability at
each station, is no longer of the future at all. The capability
is here today!
Motorola Semiconductor serves a wide range of
requirements for the voice/data marketplace. We offer both
CMOS and Linear technologies, each to its best advantage,
to upgrade the conventional analog voice systems and
establish new capabilities in digital communications. Early
products, such as the solid-state single-chip crosspoint
switch; the more recent monolithic Subscriber Loop
Interface Circuit (SLlC); a single-chip CodeC/Filter
(Mono-Circuit); the Universal Digital Loop Transceivers
(UDLT); basic rate ISDN (Integrated Services Digital
Network), and single-chip telephone circuits are just a few
examples of Motorola leadership in the voice/data area.

RF Communications .............................. 8-2
Telecommunications ............................. 8-26
PBX Architecture (Analog Transmission) . . . . . . . . . . . .. 8-8
ISDN Voice/Data Circuits .. . . . . . . . . . . . . . . . . . . . . . .. 8-12
Voice/Data Communication (Digital Transmission) ... 8-15
Complete Electronic Telephone Circuit ............. 8-17
Tone Ringers ................................... 8-18
Speech Networks ............................... 8-19
Speakerphones ................................. 8-20
Telephone Accessory Circuits ..................... 8-22
Phase-Locked Loop Components. . . . . . . . . . . . . . . . .. 8-28
Index .......................................... 8-30
Data Sheets .................................... 8-32
Addendum .................................... 8-179

RF Communications
Wideband (FM/FSK) IFs

Wideband Single Conversion Receivers -

VHF

Narrowband Single Conversion Receivers -

MC3359

4-8 V

5.0 rnA

5.0~V

4-9 V

7.0 rnA

2.0~V

45 MHz

VHF

455 kHz

>4.8kb

Ceramic Quad
Detector/Resonator
Scan output option

P/648

P/707

DWI751D
MC33618

2-8 V

6.0mA

Lowest cost receiver

60 MHz

P648
D17518

MC3367

1-5V

1.0 rnA

MC3371

2-8 V

6.0mA

1.0~V

75 MHz

1.2 kb

V

60 MHz

>4.8kb

MC3372

1 Cell Operation
RSSI

DW/751F
P/648
D17518

RSSI, Ceramic Quad
Detector/Resonator

Narrowband Dual Conversion Receivers -

MC3362

MC3363

2.0V
to
7.0V

3.0 rnA

0.71lV

4.0 rnA

O.4IlV

10.7
MHz

VHF

V

455 kHz

>4.8
kb

V

0.7~V

MC3335
MC13135

180
MHz

FM/FSK -

3.5mA

200
MHz

> 50 kb

MC13136

Includes buffered
VCO output

P/724
DW/751E

Includes RF
amp/mute

DW1751F

Low cost version

DW/751D

Voltage buffered
RSSI

DW/751E

High level IF
resonator drive

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
8-2

RF Communications (continued)

Transmitters -

AM/FM/FSK

Device

VCC

ICC

Pout

MaxRF
Freq
Out

MC2831A

3.0 V
to
8.0V

5.0 rnA

-30 dBm

50 MHz

lOrnA

-30 dBm
to
+10 dBm

150 MHz

2.0V
to
5.0V

40 rnA

8.0 dBm

500 MHz

MC2833

MC13175
MC13176

Max
Mod
Freq
50kHz

Notes
FM transmitter. Includes low battery checker,
tone oscillator

Suffix/
Case
P/648
0/751B

FM transmitter. Includes two frequency
multiplier/amplifier transistors
5.0 MHz

1.0 GHz

AM/FM transmitter. Single frequency PLL
fout = 8 x fref

01751B

fout = 32 x fref

Balanced Modulator/Demodulator
Device

VCC

ICC

MC1596
MC1496

5.0V
to
30V

lOrnA

Function
Carrier Balance >50 dB

General purpose balanced modulator/
demodulator for AM, SSB, FM detection

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

8-3

Suffix!
Case

U632
P/646
01751 A

Wideband FM IF
MC13155D TA = 40° to +85°C, Case 648, 751B

The MC13155D is a complete wideband FM detector
designed for satellite TV and other wideband data and
analog FM applications. Devices may be cascaded for higher
IF gain and extended Receive Signal Strength Indicator
(RSSI) range.

•
•
•
•
•
•

12 MHz Video/Baseband Demodulator
Ideal for Wide band Data and Analog FM Systems
Limiter Output for Cascade Operation
Low Drain Current: 7.0 rnA
Low Supply Voltage: 3.0 to 6.0 V
Operates to 300 MHz

10 k

lOOn
Detector o---1l-~,----'VV'v---I

Ouputo---jf--_-'VV\~--I
100 n

t-:-~;;c:_------~;--_c VEE2

560
20p

r

-

- -

- - ,

,~,L
L -_ _"
~_ _~

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

8-4

Wideband FM IF System
MC13156DW TA = -40° to +85°C, Case 751 E

The MC13156 is a wideband FM IF subsystem targeted at
high performance data and analog applications. Excellent
high frequency performance is achieved, with low cost,
through use of Motorola's MOSAIC 1.5™ RF bipolar process.
The MC13156 has an onboard Colpitts VCO for PLL
controlled multichannel operation. The mixer is useful to
beyond 200 MHz and may be used in a differential, balanced,
or single-ended configuration. The IF amplifier is split to
accommodate two low cost cascaded filters. RSSI output is
derived by summing the output of both IF sections. A precision
data shaper has a hold function to preset the shaper for fast
recovery of new data.

Applications forthe MC13156 include CT-2, wide band data
links, and other radio systems utilizing GMSK, FSK or FM
modulation.
•
•
•
•

2.0 to 6.0 Vdc Operation
Typical Sensitivity of 6.0 ~V for 12 dB SINAD
RSSI Range of Greater than 70 dB
High Performance Data Shaper for Enhanced CT-2
Operation
• Internal 300 nand 1.4 kQ Terminations for 10.7 MHz and
455 kHz Filters
• Split IF for Improved Filtering and Extended RSSI Range

0.146~

1.0 f1

£

144.455 MHz

IF

I-~r---,.---I--o RSSI
OUlput

Dala
f - - - - - - - + - - O Slicer
Hold
10 k

Dala

"--------+--OOUlPut

Vee

680p

lOOk

Vee
-.J

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

8-5

Narrowband FM Receiver
MC131351136P,

ow

TA = -40' to +85'C,
Case 724, 751 E

Vcc

l' 0.1

The MC13135 is a full dual conversion
receiver with oscillators, mixers, Limiting IF
Amplifier, Quadrature Discriminator, and RSSI
circuitry. It is designed for use in security systems,
cordless phones, and VHF mobile and portable
radios. Its wide operating supply voltage range
and low current make it ideal for battery
applications. The Received Signal Strength
Indicator (RSSI) has 65 dB of dynamic range with
a voltage output, and an operational amplifier is
included for a DC buffered output. Also, an
improved mixer third order intercept enables the
MC13135 to accommodate larger input signal
levels.

360
Audio
Qulpu

RSSI
Qulpu
I

•
•
•
•
•

Complete Dual Conversion Circuitry
Low Voltage: 2.0 to 6.0 Vdc
RSSI with Op Amp: 65 dB Range
Low Drain Current: 3.5 rnA Typical
Improved First and Second Mixer 3rd Order
Intercept
• Detector Output Impedance: 25 n Typically

455kHz
Quad Coil

Toka
7MC·8128Z

UHF, FM/AM Transmitter
MC1317511760 TA

AM Modulator
1.3k

= 0' to +70'C. Case 751 B

S2

The MC13175 and MC13176 are one chip
FMIAM transmitter subsystems designed for
AMIFM communication systems operating in the
260 to 470 MHz band covered by FCC Title 47;
Part 15. They include a Colpitts crystal reference
oscillator, UHF oscillator, +8 (MCI3175) or +32
(MCI3176) prescaler, and phase detector
forming a versatile PLL system. Another
application is as a local oscillator in a UHF or 900
MHz receiver. MC131751176 offer the following
features:

1-,-.;--"" 150p RFoul

~C

SI

n

• Power Down Feature
• UHF Current Controlled Oscillator
P f --;p-+-----1E---o:;;;;
• Use Easily Available 3rd Overtone or
MC13176 1 MC131751
Fundamental Crystals for Reference
VCC
~
0.82~
• Low Number of External Parts Required
MC13175
Crystal
lk
=
• Low Operating Supply Voltage (1.8-5.0 Vdc)
3RD Overtone
~
T.
• Low Supply Drain Currents
40.0000MHz
• Power Output Adjustable (Up to +10 dBm)
• ASK Modulated by Switching Output On and Off
• Differential Output for Loop Antenna or Balun Transformer Networks
• MC13175 - fo = 8 x fref
• MC13176 -fo = 32 x fref

-+

l00

t

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

8-6

MCl317s:l Cryslal
=

I

Vcc

Fundamental
10MHz

Subscriber Loop Interface Circuits (SLlC)
MC3419-1L TA = 0° to +70°C, Case 726
transmission. These include the provision of DC power to the
telephone (Battery); Overvoltage protection; Ring trip
detection; Supervisory features such as hook status and dial
pulsing; 2-to-4 wire conversion, suppression of longitudinal
signals (Hybrid).

The replacement of two-to-four wire conversion hybrid
transformers in Central Office, PBX, and Subscriber Carrier
equipment with the SLiC has resulted in major improvement
in telephone equipment. The SLiC family performs this task,
along with most other BORSHT functions required by signal

Vee

• All Key Parameters Externally Programmable
• Current Sensing Outputs Monitor Status of both
Tip and Ring Leads
• On-Hook Power Below 5.0 mW
• Digital Hook Status Output
• Power Down Input
• Ground Fault Protection
• Size and Weight Reduction over Conventional
Approaches
• The sale of this product is licensed under
Patent No. 4,004,109. All royalties related to
this patent are included in the unit price.

MC33120/1 P, FN TA

= -40° to +85°C, Case 738,

776

VEE

With a guaranteed minimum longitudinal balance of 58 dB,
the MC33120/1 is ideally suited for Central Office applications,
as well as PBXs, and other related equipment. Protection and
sensing components on the two-wire side can be non-precision while achieving required system performance. Most
BORSHT functions are provided while maintaining low power
consumption, and a cost effective design. Size and weight
reduction over conventional transformer designs permit a
higher density system.

•
•
•
•
•
•
•
•

• All key parameters externally programmable with resistors:
• Transmit and Receive Gains
• T ranshybrid Loss

MC33122 TA

VOB

• Return Loss
• DC Loop Current Limit and Battery Feed Resistance
• Longitudinal Impedance
Single and Double Fault Sensing and Protection
Minimum 58 dB Longitudinal Balance (2-wire and 4-wire)
Guaranteed
Digital Hook Status and Fault Outputs
Power Down Input
Loop Start or Ground Start Operation
Size & Weight Reduction Over Conventional Approaches
Available in 20 Pin DIP and 28 Pin PLCC Packages
Battery Voltage: -42 V to -58 V (for MC33120),
-21.6 V to -42 V (for MC33121)

= -40° to +85°C, Case 'TBD

The MC33122 is designed to provide the interface between
the four-wire side of a Central Office or remote terminal and the
two-wire subscriber line. Interface functions include battery
feed, proper loop termination AC impedance, adjustable
transmit, receive and transhybrid gains, hookswitch and ring
trip detection. Additionally, the MC33122 provides a minimum
of 58 dB of longitudinal balance.
The transmit and receive signals are referenced to analog
ground (VAG), easing the interface to Codecs, filters, etc. The
logic interface is TTL and CMOS compatible.
Internal loop current power transistors sink and source
current attip and ring. Thermal shutdown is provided to protect
against line faults. A switching regulator is used to reduce
power dissipation and enhance reliability, and a clock input
allows synchronization to minimize noise.
The MC33122 will be fabricated on a standard high voltage
(90 V) BiMOS process to increase protection during lightning
surges. It will be available in a 52 pin PLCC and 64 pin QFP
package.

• Designed in Accordance with TR·000057 and TA-000909
Bellcore Objectives
• Suitable for CO, Digital Loop Carrier Systems (DLCS),
and PBX
• Full On-Hook Transmission Capability
• On-Chip Loop Current Power Transistors
• Reduced Power Dissipation with Switching Regulator
• Minimum 58 dB Longitudinal Balance
• Externally Adjustable Impedance, Tx, Rx and Transhybrid
Gains
• Current Limit Externally Adjustable to 50 mA
• Hook Switch Detection and Ring Tip Capability,
Adjustable
o Polarity Reversal and Power Down Capability
• Ground Start Sequence Controls
• Two Relay Drivers

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

8-7

PBX Architecture (Analog Transmission)
PCM Mono-Circuits Codec-Filters
(CMOS LSI)
MC14SS00 Series Case 620, 64B, 70B, 726, 736, 751, 776

The Mono-circuits perform the digitizing and restoration of
the analog signals. In addition to these important functions,
Motorola's family of pulse-code modulation mono-circuits also
provides the band-limiting filter functions - all on a single
monolithic CMOS chip with extremely low power dissipation.
The Mono-circuits require no external components. They
incorporate the bandpass filter required for antialiasing and 60
Hz rejection, the AlD-D/A conversion functions for either U.S.
Mu-Law or European A-Law companding formats, the lowpass filter required for reconstruction smoothing, an on-board
precision voltage reference, and a variety of options that lend
flexibility to circuit implementations. Unique features of
Motorola's Mono-circuit family include wide power supply
range (6 to 13 V) selectable on-board voltage reference (2.5,
3.1, or 3.B V), and TTL or CMOS I/O interface.
Motorola supplies five versions in this series. The
MC145500, MC145503 and MC145505 are general-purpose
devices in 16 pin packages designed to operate in digital
telephone or line card applications. The MC145501 is the
same device (in an 1B pin package) that offers the capability
of selecting from three peak overload voltages (2.5, 3.15 and
3.7B V). The MC145502 is the full-feature device that presents
all olthe options available on the chip. This device is packaged
in a 22 pin DIP and 2B pin chip carrier package.

Txl_-----,

TOC
- Tx
+Tx

TOE
TOO

VAG

CCI
MSI
RSI

Vrer
RxG---....
ROD

RxO

RCE
ROC

VSS-

Voo-

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

8-8

_ _ POI

- - MulA
- - VIS

PCM Mono-Circuits Codec-Filters
MC145554/57/64/67 Case 620, 648, 732, 738, 7510, 751G

MC145480 Case 738, 7510

These per channel PCM Codec-fiIters perform the voice
digitization and reconstruction as well as the band limiting and
smoothing required for PCM systems. They are designed to
operate in both synchronous and asynchronous applications
and contain an on-chip precision voltage reference. The
MC145554 (Mu-Law) and MC145557 (A-Law) are general
purpose devices that are offered in 16 pin packages. The
MC145564 (Mu-Law) and MC145567 (A-Law), offered in 20
pin packages, add the capability of analog loop-back and
push-pull power amplifiers with adjustable gain.
All four devices include the transmit bandpass and receive
lowpass filters on-chip, as well as active RC pre-filtering and
post-filtering. Fully differential analog circuit design assures
lowest noise. Performance is specified over the extended
temperature range of -40° to +85°C.
These PCM Codec-filters accept both industry standard
clock formats. They also maintain compatibility with Motorola'S
family of MC3419/MC33120 SLiC products.

This 5.0 V, general purpose per channel PCM Codec-fiIter
offers selectable Mu-Law or A-Law companding in 20 pin DIP
and SOG packages. It performs the voice digitization and
reconstruction as well as the band limiting and smoothing
required for PCM systems. It is designed to operate in both
synchronous and asynchronous applications and contains an
on-chip precision reference voltage (1.575 V).
The transmit bandpass and receive lowpass filters, and the
active RC pre-filtering and post-filtering are incorporated, as
well as fully differential analog circuit design for lowest noise.
Push-pull 300 n power drivers with external gain adjust are
also included.
The MC145480 PCM Codec-filter accepts a variety of clock
formats, including short-frame sync, long-frame sync, IDL,
and GCI timing environments. This device also maintains
compatibility with Motorola's family of Telecom products,
including the MC145472 U Interface Transceiver,
MC145474175 SIT Interface Transceiver, MC145532 ADPCM
Transcoder, MC145422126 UDLT-I, MC145421/25 UDLT-II,
and MC3419/MC33120 SLiC.

Also Available - Filters:
MC145414

MC145432

Dual Tuneable Low-Pass Sampled Data Filter

2600 Hz Tone Signalling Filter

Crosspoint Switches
Crosspoint switches implemented with semiconductor
technology take the place of the huge banks of mechanical
relay matrices once utilized in Central Offices and PBXs.
Motorola's crosspoint switches have latches to control the
state of any particular switch in order to route analog or digital
Signals. These ICs find applications in PBXs, key systems,
and test equipment.

MC 1421 00

4 x 4 x 1 Analog Switch
• 4.2 to 18 V operation
• Low on-state resistance

MC145100

4 x 4 x 1 Analog Switch
• 4.2 to 18 V operation
• Low on-state resistance
• Power-on reset

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
8-9

CU620
CP/648

DW1751G
CP/648

PBX Architecture (continued)

Codec-Filter/ADPCM Transcoder Evaluation Kits
MC145536EVK

MC145537EVK

The MC145536EVK is the primary tool for evaluation and
demonstration of the MC145480 Single +5.0 V supply PCM
Codec-Filter and the MC145532 ADPCM Transcoder (see
"Telephone Accessory Circuits"). The MC145536EVK
provides the necessary hardware needed to evaluate the
many separate operating modes under which the MC145480
and MC145532 are intended to operate.

The MC145537EVK is the primary tool for evaluation and
demonstration of the MC145540 ADPCM Codec. It provides
the necessary hardware and software interface to access the
many features and operational modes of the MC145540
ADPCM Codec.
• Provides Stand Alone Evaluation on Single Board
• The kit provides Analog-to-Analog, Analog-to-Digital or
Digital-to-Analog connections - with Digital connections
being 64 kbps PCM; 32 or 24 kbps ADPCM; 16 kbps
CCITT G.726 or Motorola Proprietary ADPCM
• +5.0 V only Power Supply, or 5.0 V plus 2.7 to 5.25 V
Supply
• Easily Interfaced to test EqUipment, Customer System,
Second MC145537EVK or MC145536EVK (5.0 V only)
for Full Duplex Operation
• Convenient Access to Key Signals
• Piezo Loudspeaker
• EIA-232 Serial Computer Terminal Interface for Control of
the MC145540 ADPCM Codec Features
• Compatible Handset Provided
• Schematics, Data Sheets, and User's Manual Included

• Provides Stand Alone Evaluation on a Single Board
• Easily Interfaced to test Equipment, Customer System, or
second MC145536EVK
• Convenient access to Key Signals
• Generous wire-wrap area for Application Development
• The kit provides Analog-to-Analog, Analog-to-Digital, or
Digital-to-Analog connections - with Digital connections
being 64 kbps PCM; 32, 24, or 16 kbps Motorola.
Proprietary ADPCM
• Compatible Handset included
• Schematics, Data Sheets, and User's Manual included.

r-------------

I
I
I
I

+S.OV Gnd +3.0V

Clocks

r------T5~1~r-----l
I
I
I
I
I

Digital

Analog
Inlerface

Interface

I
I
_________ _
MCI4553&EVK
IL _

Dual Tone Multiple
Frequency Receiver
MC145436 Case 646, 751
This device contains the filter and decoder for detection of
a pair of tones conforming to the DTMF standard with outputs
in hexadecimal. Switched capacitor filter technology is used
together with digital circuitry for the timing control and output
circuits. The MC145436 provides excellent power-line noise
and dial tone rejection.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
8-10

PBX Architecture (continued)

ADPCM Codec
MC145540 Case 710, 751 F
The MC145540 ADPCM Codec is a single chip
implementation of a PCM codec-filter and an ADPCM
encoder/decoder, and therefore provides an efficient solution
for applications requiring the digitization and compression of
voiceband signals. This device is designed to operate over a
wide voltage range, 2.7 V to 5.25 V, and as such is ideal for
battery powered as well as AC powered applications. The
MC 145540 ADPCM Codec also includes a serial control port
and internal control and status registers that permit a
microcomputer to exercise many built-in features.

The ADPCM Codec is designed to meet the 32 kbps
ADPCM conformance requirements of CCID Recommendation G.721 and ANSI T1.301. It also meets ANSI T1.303 and
CCID Recommendation G.723 for 24 kbps ADPCM
operation, and the 16 kbps ADPCM standard, CCITT
Recommendation G.726. This device also meets the PCM
conformance
specification
of the
CCID G.714
Recommendation.

Block Diagram

Serial Control Port

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
8-11

ISDN Voice/Data Circuits
Integrated Services Digital Network
ISDN is the revolutionary concept of converting the present
analog telephone networks to an end-to-end global digital
network. ISDN standards make possible a wide variety of
services and capabilities that are revolutionizing communications in virtually every industry.
Motorola's ISDN product family includes: the MC145472
U-Interface Transceiver; the MC145474175 SIT-Interface
Transceivers; MC145488 Dual Data Link Controller; and the
MC68302 Integrated Multi-Protocol Processor. These are
supported by a host of related devices including: the
MC145480 +5.0 V PCM Codec-Fllter; MC145532 ADPCM
Transcoder; MC145540 ADPCM Codec; MC145500 family of
single-chip Codec/filters; MC145436 DTMF Decoder;
MC33120 Subscriber Loop Interface Circuit; MC34129
Switching Power Supply Controller; MC145611 PCM
Conference Circuit; and the MC145406/07 CMOS EIA 232-0
Driverl Receiver family.

Motorola'S key ISDN devices fit into four ISDN network
applications: a digital subscriber line card, an NT1 network
termination, an ISDN terminal adapter, and an ISDN terminal.
Digital subscriber line cards are used in central offices, remote
concentrators, channel banks, T1 multiplexers, and other
swHching equipment. The NT1 network termination block
illustrates the Simplicity of remote U to SIT-interface
conversion. The ISDN terminal adapter and ISDN terminal
block show how Motorola ICs are used to combine voice and
data in PC compatible boards, digital telephones, and other
terminal equipment. Expanded applications such as a PBX
may include these and other Motorola ISDN circuits. Many
"non-ISDN" uses, such as pairgain applications, are
appropriate for Motorola'S ISDN devices as well.

NTI
1-----------,

I

MC14LC5472

c

•

I

o

,--:-:-----=::.:.--:,-

f
f
I

I
I
I
I
I
I
I
I
IL_________ _

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
8-12

ISDN Voice/Data Circuits

(continued)

U-Interface Transceivers

U-Interface Transceiver
Evaluation Kit

MC145472 Case 847B
MC14LC5472 Case 847B, 847
The MC145472/MC14LC5472 fully conforms to ANSI
T1.601-1991, the North American standard for ISDN Basic
Access on a single twisted-wire pair. The transceiver achieves
a remarkable 10-7 bit error rate performance on all ANSI
specified test loops with worst-case impairments present. The
state-of-the-art 1.2 micron single-chip solution uses advanced
design techniques to combine precision analog signal
processing elements with three digital signal coprocessors to
build an adaptively equalized echo cancelling receiver.
Two modes of handling U-interface maintenance functions
are provided on the MC145472/MC14LC5472. In the
automatic maintenance mode the U-interface transceiver
handles all ANSI specified maintenance and channel
procedures internally to minimize your software development
effort. Automatic procedures include generating and
monitoring the cyclic redundancy check, reporting and
counting far end block errors (near end block errors too),
handling the ACT and DEA bits, as well as monitoring and
appropriately responding to embedded operations channel
messages.
The optional manual maintenance mode lets you choose
an inexpensive microcontroller, such as a member of
Motorola's MC68HC05 family, to control and augment the
standard maintenance channel functions. This flexible feature
also allows for easy implementation of proprietary
maintenance functions.

MC14LC5494EVK
This kit provides the hardware and software to evaluate the
many configurations under which the MC14LC5472 is able to
operate. Used as a whole, it operates as both ends of the
two-wire U-Interface that extends from the customer premises
(NT1) to the switch line card (LT). The two halves of the board
can be physically and functionally separated, providing
independent NT1 and LT evaluation capability.
The kit provides the ability to interactively manipulate
status registers in the MC14LC5472 U-Interface Transceiver
or in the MC145474/75 SIT-Interface Transceiver with the aid
of an external terminal. The device can also be controlled
using the MC68302 Integrated Multiprotocol Processor
application development system to complete a total Basic
Rate ISDN evaluation solution.
A generous wire-wrap area is available to assist application
development.

2Bl Q U-Interface

NT1 Side

SIT

LT Side

tnterface

,.IDL

-t---t----t:==~----7--;::=!=:::lI------'--____j

SCP . . .

L:::..::l~::::::"'-I-+

MC14LC5494EVK

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

8-13

SCP

ISDN Voice/Data Circuits

(continued)

Dual Data Link Controller

SIT-Interface Transceivers

MC145488 Case 779

MC145474 Case 736A
MC145475 Case 710, 751 F

The MC1454BB features two full-duplex serial HDLC
channels wHh an on-chip Direct Memory Access (DMA)
controller. The DMA controller minimizes the number of
microprocessor interrupts from the communications
channels, freeing the microprocessor's resources for other
tasks. The DMA controller can access up to 64 k bytes of
memory, and transfers either B-bit bytes or 16-bit words to or
from memory. The MCI454BB DDLC is compatible with
Motorola's MC6BOOO and other microprocessors.
In a typical ISDN terminal application, one DDLC
communications channel supports the D-channel (LAPD)
while the other supports the B-channel (LAPB). While the
DDLC is ideally suited for ISDN applications, it can support
many other HDLC protocol applications as well.
Some of the powerful extras found on the DDLC include
automatic abort and retransmit of D-channel collisions in
SfT-interface applications, address recognition, automatic
recovery mechanisms for faulty frame correction, and several
system test modes. Address recognition provides a reduction
in the host microprocessor load by filtering data frames not
addressed to the host. The DDLC can compare either SAPI or
TEl fields of LAPD frames. For LAPD (0.921) applications,
both A and B addresses may be checked.

The MC145474175 SfT-lnterface Transceivers provide a
CCITT 1.430 compatible interface for use in line card, network
termination, and ISDN terminal equipment applications.
Manufactured with Motorola's advanced 1.5 micron CMOS
mixed analog and digital process technology, the
MC145474175 is a physical layer device capable of operating
in point-to-point or point-to-multipoint passive bus
arrangements. In addition, the MC145475 can implement the
optional NT! Star topology.
This
device
features
outstanding
transmission
performance. It reliably transmits over 2.5 kilometers in a
point-to-point application with specifications of 1 kilometer.
Comparable performance is achieved in all other topologies
as well. Other features include pin selectable terminal or
network operating modes, industry standard microprocessor
serial control port, full support of the multiframing Sand 0
channels, a full range of loopbacks, and low power CMOS
operation.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

8-14

Voice/Data Communication (Digital Transmission)
2-Wire Universal Digital Loop Transceiver (UDLT)
MC145422 Master Station Case 708, 736, 751 E
MC145426 Slave Station Case 708, 736, 751 E
The UDLT family of transceivers allows the use of existing
twisted-pair telephone lines (between conventional
telephones and a PBX) for the transmission of digital data.
With the UDLT, every voice-only telephone station in a PBX
system can be upgraded to a digital telephone station that
handles the complex voice/data communications with no
increase in cabling costs.
In implementing a UDLT-based system the ND to D/A
conversion function associated with each tel set is relocated
from the PBX directly to the telset. The SLiC (or its equivalent
circuit) is eliminated since its Signaling information is
transmitted digitally between two UDLTs.
The UDLT master-slave system incorporates the
modulation/demodulation functions that permit data
communications over a distance up to 2 kilometers. It also
provides the sequence control that governs the exchange of
information between master and slave. Specifically, the
master resides on the PBX line card where it transmits and
receives data over the wire pair to the telset. The slave is
located in the telset and interfaces the mono-circuit to the wire
pair. Data transfer occurs in 1O-bit bursts (8 bits of data and 2
Signaling bits), with the master transmitting first, and the slave
responding in a synchronized half-duplex transmission
format.
UDLTs utilize a 256 kilobaud Modified Differential Phase
Shift Keyed (MDPSK) burst modulation technique for
transmission to minimize radio frequency, electromagnetic,
and crosstalk interference. Implementation through CMOS
technology takes advantage of
low-power operation,
increased reliability, and the proven capabilities to perform
complex telecommunications functions.

Functional Features
• Provides Synchronous Duplex 64 kbits/Second
Voice/Data Channel and Two 8 kbits/Second Signaling
Data Channels Over One 26 AWG Wire Pair Up to 2 km.
• Compatible with Existing and Evolving Telephone Switch
Architectures and Call Signaling Schemes
• Automatic Detection Threshold Adjustment for Optimum
Performance Over Varying Signal Attenuations
• Protocol Independent
• Single 5.0 V to 8.0 V Power Supply
MC145422 Master UDLT
• 2.048 MHz Master Clock
• Pin Controlled Power-Down and Loop-Back Features
• Variable Data Clock - 64 kHz to 2.56 MHz
• Pin Controlled Insertion/Extraction of 8 kbits/Seconds
Channel into LSB of 64 kbits/Second Channel for
Simultaneous Routing of Voice and Data Through PCM
Voice Path of Telephone Switch
MC145426 Slave UDLT
• Compatible with MC145500 Series and Later PCM
Mono-Circuits
• Automatic Power-Up/Down Feature
• On-Chip Data Clock Recovery and Generation
• Pin Controlled 500 Hz D3 or CCITT Format PCM Tone
Generator for Audible Feedback Applications

UDLT
, - - - - - - - - - - -.... Signaling Input 1

,----------0-

Signaling Input 2

Une
Driver
Output

f-----..........
1 - - -..........
1------0.....

f--------o.....

r

Power Down
T/R Oala Clock

Conv.rtCIOCk - - Master Sync
Signal Insert Enable

Master
Only

f - - - - - o I f - Signal Enable

. . j-----4-MuLaw---: ; , f - - - - - Tone Enable

Slave

Only

Transmit Enable
Transmit Data
Signal Output 1
Signal Output 2

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

8-15

Voice/Data Communication (Digital Transmission)

(continued)

2-Wire ISDN Universal Digital Loop Transceiver II
(UDLT II)
MC145421 Master Case 623, 709, 751 E
MC145425 Slave Case 623, 709, 751 E
Similar to the MCI45422126 UOLT, but provide 160 kbps in
two 64 kbps and two 16 kbps (2B + 20) format.

Data Set Interface Circuit (DSI)
MC145428 TA =-40° to + 85°C, Case 738, 7510
This new CMOS LSI circuit provides asynchronous-to-synchronous data conversion. It is particularly well-suited for use
in conjunction with a UOLT-based integrated voice/data
system. The MC145428 OSI provides EIA-232-to-time slot
data conversion that permits direct interface between existing
data equipment and the UOLTwithout modifications. With this
interactive component, digitized voice information from the
PCM Mono-Circuit and asynchronous data from computers or
terminals can be transmitted simultaneously through a
synchronous switching network.
OSI circuits are also suited for data multiplexers,
concentrators and deconcentrators, data rate changers,
data-only switching, and PBX-based local area networks.

• Up to 128 kbps asynchronous data rate operation
• 0 up to 2.1 Mbps synchronous data rate operation
• On-board bit rate clock generator with pin selectable
bit rates of 300, 1200, 2400, 4800, 9600, 19200,
and 38400 bps or an externally supplied 16 times
bit rate clock may be used
• Accepts asynchronous data words of 8 or 9 bits
• False start detection provided
• Automatic sync insertion and checking

Data Set Interface Circuit

TxS

-4-----------.,

TxD

i---DCO

OL

~"""""~---DOE

BRI-BR3

:''',,'''!'i/;'';\I*--- DIE

BC
BRCLK

l4---DC
.J:li±~~~-- CM
' - - - - - RESET

AxD

,,14----

SB

RxS + - - - - - - - - - - - '

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
8-16

DCI

Complete Electronic Telephone Circuit
MC34010P, FN TA = -20° to +60°C, Case 711, 777
Piezo
Sound
Element

Hook Switch
/-~

Ceramic
Resonator

------,

r-

A

c
• 0

I
I
Tone
Ringer

DTMF

D

Une
Voltage
Regulator

Keypad

MPU

MPU
Interlace

III
I

I
I
I
I
I

~
Tip

Ring

Speech
Network

L _______ _

Receiver
MC34010

Electret
Microphone

The conventional transformer-driven telephone handset is
undergoing major innovations. The bulky transformer is
disappearing. So are many of its discrete components,
including the familiar telephone bell. They are being replaced
with integrated circuits that perform all the major handset
functions simply, reliably and inexpensively ... functions such
as 2-to-4 wire conversion, DTMF dialing, tone ringing, and a
variety of related activities.
The culmination of these capabilities is the Electronic
Telephone Circuit, the MC34010. These ICs place all of the
above mentioned functions on a single monolithic chip.
These telephone circuits utilize advanced bipolar linear
(12L) technology and provide all the necessary elements of a
modern tone-dialing telephone. The MC34010 even
incorporates an MPU interface circuit for the inclusion of
automatic dialing in the final system.

• Provides all basic telephone functions, including DTMF
dialer, tone ringer, speech network and line voltage
regulator.
• DTMF generator uses low cost ceramic resonator with
accurate frequency synthesis technique.
• Tone ringer drives piezoelectric transducer and satisfies
EIA-470 requirements
• Speech network provides 2-to-4 wire conversion with
adjustable sidetone utilizing an electret transmitter
• On-chip regulator insures stable operation over wide
range of loop lengths
• 12L technology provides low I .4 V operation and high
static discharge immunity
• Microprocessor interface port for automatic dialing
features

Also Available
A broad line of additional telephone components for customizing systems design.

Audio Control Circuit

Dial Circuits

MC145429

MC145412113116

Telset audio interface circuit for MPU-controlled independent adjustment of ear piece, speaker and ringer volume.

Integrated TonelPulse 10-number Repertory Dialer.
MC145512113
Integrated TonelPulse 10-number Repertory Dialer.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

8-17

Tone Ringers
The MC34012, MC34017, and MC34117 Tone Ringers are
designed to replace the bulky bell assembly of a telephone,
while providing the same function and performance under a
variety of conditions. The operational requirements spelled
out by the FCC and EIA-470, simply stated, are that a ringer

circuit MUST function when a ringing signal is provided, and
MUST NOT ring when other signals (speech, dialing, noise)
are on the line. The tone ringers described below were
designed to meet those requirements with a minimum of
external components.
C3

MC34012P, D
TA = -20° to +60°C, Case 626, 751

•
•
•
•
•
•
•

Complete Telephone Bell Replacement
On-Chip Diode Bridge and Transient Protection
Single-Ended Output to Piezo Transducer
Input Impedance Signature Meets Bell and EIA Standards
Rejects Rotary Dial and Hook Switch Transients
Adjustable Base Frequencies
Output Frequency to Warble Ratio - MC34012-1 :80
MC34012-2:160
MC34012-3:40

Ring

C2

MC34017P, D
TA = -20° to +60°C, Case 626, 751

•
•
•
•
•
•

Complete Telephone Bell Replacement
On-Chip Diode Bridge and Transient Protection
Differential Output to Piezo Transducer for Louder Sound
Input Impedance Signature Meets Bell and EIA Standards
Rejects Rotary Dial and Hook Switch Transients
Output Frequency to Warble Ratio - MC34017-1 :80
MC34017-2:160
MC34017-3:40

MC34217P, D
TA = -20° to +60°C, Case 626, 751

•
•
•
•
•
•
•

Complete Telephone Bell Replacement
On-Chip Diode Bridge
Internal Transient Protection
TIp
Differential Output to Piezo Transducer ior Louder Sound
Input Impedance Signature Meets Bell and EIA Standards R;"9
Rejects Rotary Dial and Hook Switch Transients
Base Frequency and Warble Frequencies are
Independently Adjustable
• Adjustable Base Frequency
• Reduced Number of Externals

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

8-18

Speech Networks
Speech Network with Dialer Interface
MC34014P,

ow TA = -20

0

to +600 C, Case 707, 7510

The MC34014 is a Telephone Speech Network integrated
circuit which incorporates adjustable transmit, receive, and
sidetone functions, line interface circuit, dialer interface, and
a regulated output voltage for a dialer circuit. It includes an
equalization circuit to compensate for various line lengths and
the conversion from 2-to-4 wire is accomplished with supply
voltages as low as 1.5 V.

T~

Rirg

• Transmit, Receive, and Sidetone Gains Set by External
Resistors
• Loop Length Equalization for Transmit, Receive, and
Sidetone Functions
• Operates Down to 1.5 V (V +J in Speech Mode
• Provides Regulated Voltage for CMOS Dialer
• Speech Amplifiers Muted During Pulse and Tone Dialing
• DTMF Output Level Adjustable with a Single Resistor
• Compatible with 2-Terminal Electret Microphones
• Operates with Receiver Impedances of 150 0 and Higher

Telephone Speech Network with Dialer Interface
MC34114P,

ow TA =-20° to +70

0

C, Case 707, 7510

• Operation Down to 1.2 V
• Adjustable Transmit, Receive, and Sidetone Gains by
External Resistors
• Differential Microphone Amplifier Input Minimizes RFI
• Transmit, Receive, and Sidetone Equalization on both
Voice and DTMF Signals
• Regulated 1.7 V Output for Biasing Microphone
• Regulated 3.3 V Output for Powering External Dialer
• Microphone and Receive Amplifiers Muted During Dialing
• Differential Receive Amplifier Output Eliminates Coupling
Capacitor
• Operates with Receiver Impedances of 150 0 and Higher

Ti>

Rirg

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

8-19

Speakerphone
Voice Switched Speakerphone Circuit
ow

MC34018P,
TA = -20' to +60'C, Case 710, 751 F
The MC34018 Speakerphone integrated circuit incorporates the necessary amplifiers, attenuators, and control
functions to produce a high quality hands-free speakerphone
system. Included are a microphone amplifier, a power audio
amplifier for the speaker, transmit and receive attenuators, a
monitoring system for background sound level, and an
attenuation control system which responds to the relative
transmit and receive levels as well as the background level.
Also included are all necessary regulated voltages for both
internal and external circuitry, allowing line-powered operation
(no additional power supplies required). A Chip Select pin
allows the chip to be powered down when not in use. A volume
control function may be implemented with an external

potentiometer. MC34018 applications include speakerphones for household and business uses, intercom systems,
automotive telephones, and others.
• All Necessary Level Detection and Attenuation Controls
for a Hands-Free Telephone in a Single Integrated Circuit
• Background Noise Level Monitoring with Long Time
Constant
• Wide Operating Dynamic Range Through Signal
Compression
• On-Chip Supply and Reference Voltage Regulation
• Typical 100 mW Output Power (into 25 Q) with Peak
Limiting to Minimize Distortion
• Chip Select Pin for Active/Standby Operation
• Linear Volume Control Function

Electret
Microphone

Speaker

~~

Receive Volume Control

Voice Switched Speakerphone with f.lProcessor Interface
• Microphone Amplifier Gain Set by External Resistors,
MC33218P, ow TA = -40' to +85'C, Case 724, 751 E
Mute Function Included
• Dial Tone Detector to Inhibit Receive Idle Mode During
Dial Tone Presence
• Microprocessor port for controlling:
• Receive Volume Level (16 Steps)
• Attenuator Range (26 or 52 dB, Selectable)
• Microphone Mute
• Force to Transmit, Receive, Idle or Normal Voice
Switched Operation
• Compatible with MC34119 Speaker Amplifier

The MC33218 Voice Switched Speakerphone circuit
incorporates the necessary amplifiers, attenuators, level
detectors, and control algorithm to form the heart of a high
quality hands-free speakerphone system. Included are a
microphone amplifier with adjustable gain, and mute control,
transmit and receive attenuators which operate in a complementary manner, and level detectors and background noise
monitors for both paths. A dial tone detector prevents dial tone
from being attenuated by the receive background noise
monitor. A Chip Disable pin permits powering down the entire
circuit to conserve power.
Also included is an 8-bit serial /lprocessor port for
controlling the receive volume, microphone mute, attenuator
gain, and operation mode (force to transmit, force to receive,
etc.). Data rate can be up to 1.0 MHz. The MC33218 can be
operated from a power supply, or from the telephone line,
requiring typically 3.8 rnA. It can also be used in intercoms and
other voice-activated applications.
• Low Voltage Operation: 2.5 to 6.0 V
• 2-Point Sensing, Background Noise Monitor in Each Path
• Chip Disable Pin for Active/Standby Operation

r.,-· ....... .,- ...... ----.,...."":."'l
T,

r+£+.TxOutput

RXlnput

Vee
Chip Disable

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
8-20

Voice Switched Speakerphone Circuit
MC34118P,

ow TA = -20° to +60°C, Case 710, 751F

The MC34118 Voice .Switched Speakerphone circuit
incorporates the necessary amplifiers, attenuators, level
detectors, and control algorithm to form the heart of a high
quality hands-free speakerphone system. Included are a
microphone amplifier with adjustable gain and mute control,
Transmit and Receive attenuators which operate in a
complementary manner, level detectors at input and output of
both attenuators,and background noise monitors for both the
transmit and receive channels. A dial tone detector prevents
the dial tone from being attenuated by the Receive
background noise monitor circuit. Also included are two line
driver amplifiers which can be used to form a hybrid network
in conjunction with an external coupling transformer. A
high-pass filter can be used to filter out 60 Hz noise in the
receive channel, or for other filtering functions. A Chip Disable
pin permits powering down the entire circuit to conserve power
on long loops where loop current is at a minimum.
The MC34118 may be operated from a power supply, or it
can be powered from the telephone line, requiring typically

5.0 mAo The MC34118 can be interfaced directly to Tip and
Ring (through a coupling transformer) for stand-alone
operation, or it can be used in conjunction with a handset
speech network and/or other features of a featurephone.
• Improved Attenuator Gain Range: 52 dB between
Transmit and Receive
• Low Voltage Operation for Line-Powered Applications
(3.0 to 6.5 V)
• 4-Point Signal Sensing for Improved Sensitivity
• Background Noise Monitors for both Transmit and
Receive Paths
• Microphone Amplifier Gain set by External Resistors,
Mute Function included.
• Chip Disable for Active/Standby Operation
• On Board Filter Pinned-Out for User Defined Function
• Dial Tone Detector Inhibits Receive Idle Mode during
Dial Tone presence
• Compatible with MC34119 Speaker Amplifier

Motorola Family of Speakerphone Integrated Circuits
MC3401S

MC3411S

Two point senSing with slow idle, background noise
monitor in Tx path only

Four point sensing with both fast and slow idle
modes, background noise monitors in both Rx and
Tx paths

..

MC3321S

Two poInt sensing with slow idle, background noise
monitors in both Rx and Tx paths

No dial tone detector in receive path

Receive path has dial tone detector

Receive path has dial tone detector

Attenuator Characteristics:
• Range: 44 dB
• Tolerance: ±4 dB
• Gain tracking not specified
• White noise is constant

Attenuator Characteristics:
• Range: 52 dB
• Tolerance: ±2 dB
• Gain Tracking: <1 dB
• White noise reduces with volume

Attenuator Characteristics:
• Range: 52 or 26 dB (selectable)
• Tolerance: ±3 dB
• Gain Tracking: <1 dB
• White noise reduces with volume

External hybrid required

Hybrid amplifiers on board

External hybrid required

Speaker amplifier is on board (34 dB, 100 mW)

External speaker amplifier required (MC34119)

External speaker amplifier required (MC34119)

Filtering is external

Configurable filter on board

Filtering is external

Microphone amplifier has fixed gain and no muting

Microphone amplifier has adjustable gain and mute
input

Microphone amplifier has adjustable gain, and can
be muted through ~p port

Supply Voltage: 2.8 v to 6.5 V

Supply Voltage: 2.5 V to 6.5 v

Supply Voltage: 4.0 V to 11

v

Supply Current: 6.5 rnA typ., 9.0 rnA max

Supply Current: 5.5 rnA typ., 8.0 rnA max

Supply Current: 4.0 rnA typ., 5.0 rnA max

Speaker amplifier reduces gain to prevent clipping

Receive gain is reduced as supply voltage falls to
prevent clipping

Receive gain is reduced as supply voltage falls to
prevent clipping

Volume control is linear. Cannot override voice
switched operation except through additional
circuitry. Attenuator gain is fixed at 44 dB (slightly
variable). No microphone mute.

Volume control is linear, and microphone mute has
separate pin. Cannot override voice switched
operation except through additional circuitry.
Attenuator gain is fixed at 52 dB.

8-bit ~P serial port controls:
• Volume control (16 steps)
• Microphone mute
• Range selection (26 dB or 52 dB)
• Force to transmit, idle, receive, or normal
voice switched operation

28 Pin DIP and SOIC packages

2S Pin DIP and SOIC packages

24 Pin narrow DIP and SOIC packages

External Required:
• 12 Resistors
.11 Capacitors (::;1.0 IlF)
• 8 Capacitors (> 1.0 IlF)

External Required:
• 14 Resistors
• 12 Capacitors (::;1.0 IlF)
• 9 Capacitors (> 1.0 IlF)

External Required:
• 12 Resistors
.11 Capacitors (::;1.0 IlF)
• 4 Capacitors (>1.0 J.lF)

Temperature Range: _20 0 to +60 °C

Temperature Range: -20 0 to +60 °C

Temperature Range: -40 0 to +85 °C

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
8-21

Telephone Accessory Circuits
Audio Amplifier

el
0.1

MC34119P, 0 TA

= 0° to +70°C, Case 626, 751

~~~~~ )---1

Differential Gain =2 x

Ri

A low power audio amplifier circuit intended (primarily) for
telephone applications, such as speakerphones, Provides
differential speaker outputs to maximize output swing at low
supply voltages (2.0 V min.). Coupling capacitors to the
speaker, and snubbers, are not required. Overall gain is
externally adjustable from 0 to 46 dB. A Chip Disable pin
permits powering-down to mute the audio signal and reduce
power consumption.

5k

:~

Rt
25 k

Vee

•
•
•
•

Drives a Wide Range of Speaker Loads (16 to 100 0)
Output Power Exceeds 250 mW with 32 0 Speaker
Low Distortion (THO = 0.4% Typical)
Wide Operating Supply Voltage (2.0 V to 16 V) - Allows
Telephone Line Powered Applications.
Low Quiescent Supply Current (2.5 mA Typical)
• Low Power-Down Quiescent Current (60 IlA Typical)

Current Mode Switching Regulator
MC34129P, 0 TA
MC33129P, 0 TA

= 0° to +70°C, Case 646, 751A
= 0° to +70°C, Case 646, 751A

r:-----·-----c.---,
1
1

High performance current mode switching regulator for
low-power digital telephones. Unique internal fault timer
provides automatic restart for overload recovery. A starVrun
comparator is included to implement bootstrapped operation
ofVCC·
Although primarily intended for digital telephone systems,
these devices can be used cost effectively in many other
applications. On-chip functions and features include:
•
•
•
•
•
•
•

eSoft·Start 112

Current Mode Operation to 300 kHz
Automatic Feed Forward Compensation
Latching PWM for Cycle-By-Cycle Current Limiting
Latched-Off or Continuous Retry after Fault Timeout
Soft-Start with Maximum Peak Switch Current Clamp
Internally Trimmed 2% Bandgap Reference
Input Undervoltage Lockout

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

8-22

131 Start/Run
Qulput

t41 Vee

Telephone Accessory Circuits

(continued)

300 Baud FSK Modems

ADPCM Transcoder

MC145442 Modem (CCITT V.21) Case 738,7510
MC145443 Modem (8eIl103) Case 738, 7510

MC145532 Case 620, 751G

This powerful modem combines a complete FSK
modulator/demodulator and an accompanying transmiVre·
ceive filter system on a single silicon chip. Designed for
bidirectional transmission over the telephone network, the
modem operates at 300 baud and can be obtained for
compatibility with CCITT V.21 and Bell 103 specifications.
The modem contains an on·board carrier-detect circuit that
allows direct operation on a telephone line (through a simple
transformer), providing simplex, half-duplex, and full-duplex
data communications. A built-in power amplifier is capable of
driving -9.0 dBm onto a 600 n line in the transmit mode.
CMOS processing keeps power dissipation to a very low
45 mW, with a power-down dissipation of only 1.0 mW . " from
a single 5.0 V power supply. Available in a 20 pin dual-in-Iine
P suffix, and a wide body surface mount OW suffix.

C
II

Tip

Ring

The MC145532 Adaptive Differential Pulse Code
Modulation (ADPCM) Transcoder provides a low cost,
full-duplex, single-channel transcoder to (from) a 64 kbps
PCM channel from (to) either a 16 kbps, 24 kbps, 32 kbps, or
64 kbps channel.
• Complies with CCITT Recommendation G.721
(Geneva 1986)
• Complies with the American National Standard
(T1.301-1987)
• Full-Duplex, Single-Channel Operation
• Mu-Law or A-Law Coding is Pin Selectable
• Synchronous or Asynchronous Operation
• Easily Interfaces with any Member of Motorola's PCM
Codec-Filter Mono-Circuit Family or Other Industry
Standard Codecs
• Serial PCM and ADPCM Data Transfer Rate from 64 kbps
to 5.12 Mbps
• Power Down Capability for Low Cost Consumption
• The Reset State is Automatically Initiated when the
Reset Pin is Released.
• Simple Time Slot Assignment Timing for Transcoder
Applications
• Single 5.0 V Power Supply
• Evaluation Kit MC145536 EVK Supports the MC145532
as well as the MC145480 PCM Godec-Filter. (See PBX
Architecture Pages for More Information.)

3.579545 MHz

MC145444 (CCITT V.21) Case 804,7510
This device includes the DTMF generator and call progress
tone detector (CPTD) as well as the other circuitry needed for
full-duplex, half-duplex, or simplex 300 baud data communication over a pair of telephone lines. It is intended for use
with telemeter system or remote control system applications.
The differential line driver is capable of driving 0 dBm into
a 600 n load. The transmit altenuator is programmable in 1
dB steps.

Vss-

-VDD

Bit Rate Generators
MC14411 Case 709, 623

MC145411 Case 648

Internal (crystal controlled) 1.843 MHz oscillator and
subsequent divider networks provide 16 different output
clocks rates ranging from 75 Hz to 1.843 MHz for data
communications equipment such as teleprinters, printers,
CRT terminals and microprocessor systems.

Similar to the MC14411, this device utilizes a 1.843 MHz
or 3.6864 MHz crystal frequency input divided to provide
nine different output clock rates from 150 Hz to 1.843 MHz,
or 300 Hz to 3.6864 MHz, respectively.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

8-23

Telephone Accessory Circuits (continued)

Calling Line Identification (CUD)
Receiver with Ring Detector
MC145447 Case 648, 751G

The MC145447 is designed to demodulate Bell 202
1200 baud FSK asynchronous data. Its primary application is
in products that will be used to receive and display the calling
number, or the message waiting indicator sent to subscribers
from participating central office facilities of the public switched
network. The device also contains a carrier detect circuit and
telephone ring detector which may be used to power up the
device.
Applications include adjunct boxes, answering machines,
feature phones, fax machines, and computer interface
products.

lip
Ring

r---"

RawData

out

Cooked
Data out

•
•
•
•
•

Ring Detector On-Chip
Ring Detect Output for MCU Interrupt
Power-Down Mode less than 1.0 IJ.A
Single Supply: 3.5 V to 6.0 V
Pin Selectable Clock Frequencies: 3.68 MHz, 3.58 MHz,
or 455 kHz
• Two-Stage Power-Up for Power Management Control

ClockSelocl
3.58 MHz, 3.68 MHz,
or 455 kHz

--0

VSS

Calling Line 10 Receiver
MC145460EVK Evaluation Kit

The MC145460EVK is a low cost evaluation platform for
the MCI45447. The MC145460EVK facilitates development
and testing of products that support the Bellcore customer
premises equipment (CPE) data interface, which enables
services such as Calling Number Delivery (CND). The
MC145447 can be easily incorporated into any telephone,
FAX, PBX, key system, answering machine, CND adjunct box
or other telephone equipment with the help of the
MC145460EVK development kit.

• Easy Clip-On Access to Key MCI45447 Signals
• Generous Prototype Area
• Configurable for MC145447 Automatic or External Power
Up Control
• EIA-232 and Logic Level Ports for Connection to any PC
or MCU Development Platform
• Carrier Detect, Ring Detect and Data Status LEDs
• Optional Tip and Ring Input Protection Network
• MCI45460EVK User Guide, MC145447 Data Sheet, and
additional MCI45447 Sample included.

EIA-232 Level
output

CD,RD,DATA
Logic Level
output

CD, RD,DATA

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
8-24

Telephone Accessory Circuits

(continued)

Continuously Variable Slope Delta (CVSD)
Modulator/Demodulator
MC34115P TA = 0° to +70°C. Case 648
MC3417/18L TA = 0° to +70°C. Case 620
MC3517/18L TA =-55° to +125°C. Case 620

Provides the AlD-D/ A function of voice communications by
digital transmission.
The MC3517/18 series of CVSDs is designed for military
secure communications and commercial telephone applications. A single IC provides both encoding and decoding
functions in a 16 pin package.

Encode
Decode

• Encode and Decode Functions on the same Chip with a
Digital Input for Selection
• CMOS Compatible Digital Output
• Digital Input Threshold Selectable (VCC/2 Reference
provided On-Chip)
• MC3417/MC3517/MC34115 have a 3-Bit Algorithm
(General Communications)
• MC3418/MC3518 have a 4-Bit Algorithm
(Commercial Telephone)

Clock

Analog Input O-+"'--j
Analog Feedback o-,,-\---j
Digital Data 0-:.1=-3f---j
Input
Digital Threshold

~1",2+-~~_ _- l

Digital Output o-"'+"'----=--'---';t>-'-++~-'--~-'-¥c+-I

I--C"'-+lf"-o

Syllablic Filter

f-:-'Hf-'-O Gain Control

VCC/2 Reference 0-:1.:,0t-,..,.,--j

Analog
Output

Reference
Input

Filter
Input

1+)

H

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

8-25

Telecommunications

SLiCs
L726

MC3419-1

Central Office, Remote Terminals, PBX All gains externally programmable, most BORSHT functions,
Applications
current limit adjustable to 50 mA, 58 dB Longitudinal Balance,
-21.6 V to -42 V.

P/738
FNm6

MC33121

Central Office, Remote Terminals, PBX All gains externally programmable, most BORSHT functions,
Applications
current limit adjustable to 50 mA, 58 dB Longitudinal Balance,-42
V to-58 V.

P/738
FN/776

MC33120

Central Office, Remote Terminals, PBX All gains externally programmable, most BORSHT functions,
Applications
current limit adjustable to 50 mA, 58 dB Longitudinal Balance,
-21.6 V to -58 V, ring trip, on-hook transmission, polarity reversal.

TBD(1)

MC33122

PBX Applications

All gains externally programmable, most BORSHT functions,
current limit adjustable to 100 mAo

Complete Telephone Circuit
POTS Circuit + MPU Dialing

Speech network, tone ringer, DC loop current interface, DTMF
dialer with serial port control.

Tone Ringers
Adjustable Tone Ringer

Single-ended output, meets FCC requirements, adjustable REN,
different warble rates.

P/626
D751

MC34012-1,
2,3

Adjustable To~e Ringer

Differential output, meets FCC requirements, adjustable REN,
different warble rates.

P/626
D751

MC34017-1,
2,3

Adjustable Tone Ringer

Differential output, meets FCC requirements, adjustable REN,
single warble rates.

P/626
D751

MC34217

Speech Networks
Basic Phone Line Interface

Loop current interface, speech network, line length compensation,
speech/dialing modes, Bell System compliant.

P/707
DW1751D

MC34014

Basic Phone Line Interface

Loop current interface, speech network, line length compensation,
speech/dialing modes, Bell System and foreign countries.

P/707
DW1751D

MC34114

Complete Speaker Phone with
Speaker Amplifier

All level detection (2 pt.), attenuators, and switching controls, mike
and speaker amp.

PI710
DW751F

MC34018

Complete Speaker Phone with Hybrid,
Filter

All level detection (4 pt.), attenuators, and switching controls, mike
amp with mute, hybrid, and filter.

PI710
DW751F

MC34118

Complete Speaker Phone with MPU
Interface

All level detection, attenuators, and switching controls, mike amp,
MPU interface for: volume control, mode selection, mike mute.

P1724
DW751E

MC33218

Speakerphone Circuits

Audio Amplifiers
1 Watt Audio Amp

1.0 W output power into 16 Q, 35 V maximum.

D1751

MC13060

Low Voltage Audio Amp

400 mW, 8.0 0 to 100 Q, 2.0 V to 16 V, differential outputs,
chip-disable input pin.

P/626
D751

MC34119

Companders
Basic Compander

2.1 Vto 7.0 V, no precision externals, 80 dB range,-40'to +85°C,
independent compressor and expander.

P/646
D1751 A

MC33110

Compander with Features

3.0 V to 7.0 V, no precision externals, 80 dB range, -40° to +85°C,
independent compressor and expander, pass through and mute
functions, two op amps.

P/648
D/751B

MC33111

(1) To Be Determined

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
8-26

Summary of Bipolar Telecom Circuits (continued)

I

I

Functlon

Suffix!
Case

Features

Device

Switching Regulator
Current Mode Regulator

For phone line power applications, soft-start, current limiting,
2% accuracy.

Voice Encoder/Decoders
Continuously Variable Slope
Modulator/Demodulator (CVSD)

Telephone quality voice encoding/decoding, variable clock rate,
3-bit coding, for secure communications, voice storage/retrieval,
answering machines, 0' to 70'C.

PJ738
DWJ751G

MC34115

Same as above except 4-bit coding.

PJ738
DW751G

MC3418

Same as MC34115, -55' to 125'C temperature range.

U620

MC3517

Same as MC3418, -55' to 125'C temperature range.

U620

MC3518

Motorola Family of Bipolar Handset Telecom Integrated Circuits
MC34018

MC34010

MC34014

Speakerphone
w/Speaker Amp

MC34114

Speech

Speech

Network

Network

Dialer
Interface

Dialer
Interface

MC34012

MC34017

Tone Ringer
(Single-Ended
Output)

Tone Ringer
(Push-Pull
Output)

MC34118
Speakerphone
w/Hybrid Amps

MC33218
Speakerphone
w/MPUlnterface

MC34119
400mW
Speaker
Amplifier

MC33110

MC33111

LowVohage
Compander
(Basic Compander)

Low Voltage
Compander
(w/Mute&
Passthrough,
OpAmps)

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

8-27

Tone Ringer
(Push-Pull
Output)

Phase-Locked Loop Components
power consumption and bipolar for high speed operation.
Typical applications include TV, CATV, radios, scanners,
cordless telephones plus home and personal computers.

Motorola offers a choice of phase-locked loop components
ranging from complete functional frequency synthesizers for
dedicated applications to a wide selection of general purpose
PLL circuit elements. Technologies include CMOS for lowest

PLL Frequency Synthesizers
Divider
Programming
Format., •
Serial

Single-Ended
, (3-State)
External" . Phase
Prescaler
' Detector
Output'
,M~dul.us

I,,,

Single
Dual

Parallel

4-Bit Bus

V
V
VV(1)
V
V

Dual

Frequency
Detector

Not
Required

VV(1)
Vv(1)
VV(1)
V
V
V

Single

Double-Ended
Phase
Detector
Output
V
V
V
V
Analog
Detector

-

V
V
V

-

V
V

V

f max
(MHz)

Functional
Supply,
Range.
(V)

20
20

3.0 to 9.0
3.0 to 9.0

MC145155-2
MC145157-2

P/707, DW/751 D, FN/775
P/648, DWI751D, FN1775

15
20
20

3.0 to 9.0
3.0 to 9.0
3.0 to 9.0

MC145149
MC145156-2
MC145158-2

P/738, DW/751 D
P/738, DW/751 D, FN1775
P/648, DWI751D, FN1775

15

3.0 to 9.0

MC145159-1

P/738, DWI751D, FN1775

60
60
60

2.5to
2.5 to
2.5 to
2.5 to
4.5 to
2.7 to

MC145161
MC145167
MC145169
MC145170
MC145191
MC145192

P/648, DW/751 G
P/648, DW1751 G
P/648, DW/751 G
P/648, D/751 B
F/751J
F1751J

160(2)
1100
1100

5.5
5.5
5.5

6.0
5.5

5.0

Suffix/.
Case.

Device

4.0
20

3.0 to 9.0

MC145106
MC145151-2

P/707, DW/751D, FN1775
P/71 0, FN1776, DW/751 F

4.5 to 12

Dual

-

20

3.0 to 9.0

MC145152-2

P/71 0, FN1776, DW1751 F

Not
Required

Vv(1)
VV(1)
Vv(1)

-

60
60
60

2.5 to 5.5
2.5 to 5.5
2.5 to 5.5

MC145160
MC145166
MC145168

P/707, DW/751 D
P/648, DW/751G
P/648, DW/751G

Single

V

V

20

3.0 to 9.0

MC145145-2

P/707, DW/751D

Dual

V

V

20

3.0 to 9.0

MC145146-2

P/738, DW/751D

V

(1 )Accommodates two loops per package.
(2h 80 MHz version available, see data sheet.

Intended Applications
o"

General Purpose

Cordless Phones

MC145106
MC145145-2
MC145146-2
MC145149
MC145151-2
MC145152-2
MC145155-2
MC145156-2
MC145157-2
MC145158-2
MC145159-1
MC145170
MC145191
MC145192

MC145160
MC145161
MC145166
MC145167
MC145168
MC145169

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

8-28

Phase-Locked Loop Components (continued)

Additional Phase-Locked Loop Functions
Devices
Function

(O'to70'C)

Suffix/Case

Oscillators
Crystal Oscillator

MECL

MC12061

Voltage-Controller Oscillator

MECL

MCI64S(3)

P/64S, U620
P/646, U632, F/607

Voltage-Controlled Multivibrator

MECL

MCI65S(3)

P/64S, U620

Dual Voltage-Controlled Multivibrator

TTL

MC40241
MC4324(1)

P/64S, U632, F/607

Voltage-Controller Oscillators

TTULS

SN74LS724

P.626, U693

Digital Mixer

MECL

MC12000

P/646, U632

Phase-Frequency Detector

MECL

MC12040

Phase-Frequency Detector

TTL

MC4044
MC4344(1)

P/646, U632, F/607

Analog Mixer, Double Balanced

MECL

MCI2002(3)

P/646, U632

Modulator/Demodulator

Linear

MCI496(2)1
MCI596(1)

P/646, U632

MECL

MC12014

P/64S, U620

Phase Detectors

Control Functions

I

Counter-Control Logic

Prescalers/Counters
MECL

MCI690(3)

F/650, U620

2-Modulus + 51 + 6, 600 MHz

MECL

MCI2009(3)

P/64S, U620

2-Modulus + SI + 9, 600 MHz

MECL

MCI2011(3)

2-Modulus + 101 + 11, 600 MHz

MECL

MCI2013(3)

Low Power 2-Modulus + 32/ + 33, 225 MHz

MECL

MCI2015(4)

Low Power 2-Modulus + 401 + 41,225 MHz

MECL

MCI2016(4)

Low Power 2-Modulus + 641 + 65, 225 MHz

MECL

MCI2017(4)

Low Power 2-Modulus + 12S1 + 129, 520 MHz

MECL

MCI201S(4)

Low Power 2-Modulus + 201 + 21 , 225 MHz

MECL

MCI2019(4)

Low Power 2-Modulus + 641 + 65, + 12S1 + 129 Pas. Edge 1.1 GHz

MECL

MC12022A(4)

Low Power 2-Modulus + 641 + 65, + 128/ + 129 Neg. Edge 1.1 GHz

MECL

MCI2022B(4)

Low Power + 64 Prescaler, 225 MHz 3.2 to 5.5 VCC

MECL

MC12023

Low Power + 64 Prescaler, 1.1 GHz

MECL

MC12073

Low Power + 256 Prescaler, 1.1 GHz

MECL

MC12074

UHF + 2 Prescaler, 750 MHz

MECL

MC12090

P/64S, U620, F/650

Programmable + N Decade

TTL

MC43161
MC4316(1)

P/64S, U620, F/650

UHF -

2,500 MHz

(1)TA = -5S· to +12S'C
(3)TA = -30' to +8S·C
(2lTA = o· to 70'C
(4)TA = -40' to +8S'C
Plastic packages available for commercial temperature range only.
NOTE: For more information see SG366/0

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

8-29

P/626, D/751

RF Communications
Device

Function

Page

MC1496, MC1596
MC2830
MC2831A
MC2833
MC3335
MC3356
MC3357
MC3359
MC33618
MC3362
MC3363
MC3367
MC3371, MC3372
MC13055
MC13104
MC13135, MC13136
MC13155
MC13156
MC13173
MC13175, MC13176
MC34055

Balanced Modulator/Demodulator
Voice Activated Switch .......................................... .
Low Power FM Transmitter System ............................... .
Low Power FM Transmitter System ............................... .
Low Power Dual Conversion FM Receiver ......................... .
Wideband FSK Receiver ........................................ .
Low Power FM IF ............................................... .
High Gain Low Power FM IF ..................................... .
Low Power FM IF . .............................................. .
Low-Power Dual Conversion FM Receiver, .........................
Low Power Dual Conversion FM Receiver ..........................
Low Voltage Single Conversion FM Receiver. . . . . . . . . . . . . . . . . . . . . . ..
Low Power FM IF ................................................
Wideband FSK Receiver .........................................
1.0 GHz Receiver LNAlMixerlVCO .................................
FM Communication Receivers ....................................
Wideband FM IF System .........................................
Wide band FM IF System .........................................
Intrared Integrated Transceiver System .............................
UHF FM/AM Transmitter .........................................
ISO 7702-3[IEEE 802.3]1 OBase-T Transceiver ......................

8-32
8-42
8-46
8-49
8-55
8-59
8-65
8-69
8-75
8-82
8-89
8-97
8-106
8-123
8-130
8-131
8-143
8-158
8-159
8-160
8-177

Device

Function

Page

MC3417,3517
MC3418,3518
MC3419·IL
MC33110
MC33120
MC33121
MC33129, MC34129
MC33218
MC34010
MC34011A
MC34012-1,-2,-3
MC34014
MC34017
MC34018
MC34114
MC34115
MC34117
MC34118
MC34119
MC34129

Continuously Variable Slope Delta Modulator/Demodulator ............ .
Continuously Variable Slope Delta Modulator/Demodulator ............ .
Telephone Line-Feed Circuit ........................................•
Low Voltage Compander ........................................... •
Subscriber Loop Interface Circuit ....................................•
Low Voltage Subscriber Loop Interface Circuit .........................•
High Performance Current Mode Controller ............. See Chapter 3, •
Voice Switched Speakerphone with Microprocessor Interface ...........•
Electronic Telephone Circuit ........................................•
Electronic Telephone Circuit ........................................•
Telephone Tone Ringer .............................................•
Telephone Speech Network with Dialer Interface ......................•
Telephone Tone Ringer .............................................•
Voice Switched Speakerphone Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . •
Telephone Speech Network with Dialer Interface ......................•
Continuously Variable Slope Delta Modulator/Demodulator .............•
Telephone Tone Ringer .............................................•
Voice Switched Speakerphone Circuit ................................•
Low Power Audio Amplifier ............................. See Chapter 9
High Performance Current Mode Controller ............. See Chapter 3, •

Telecommunications

'See Telecommunications Device Data (DL 136)

MOTOROLA LlNEARIINTERFACE ICs DEVICE DATA
8-30

RELATED APPLICATION NOTES
App Note

Title

Related Device

AN531

MC1596 Balanced Modulator ................................. MC1596

AN933

A Variety of Usese for the MC34012/MC34017
Tone Ringers ............................................. MC34012-1,-2,-3
MC34017

AN937

A Telephone Ringer which Complies with FCC and EIA
Impedance Standards ..................................... MC34012, MC34017

AN957

Interfacing the Speakerphone to the MC3401 0/11 /13
Speech Networks ......................................... MC34010, MC34011A

AN958

Transmit Gain Adjustments for the MC34014 Speech
Network ................................................. MC34014

AN959

A Speakerphone with Receive Idle Mode ....................... MC34018

AN960

Equalization of DTMF Signals Using the MC34014 .............. MC34014

AN976

A New High Performance Current Mode Controller Teams
Up with Current Sensing Power MOSFETs ................... MC34129

AN980

Low Power FM Dual Conversion Receivers ..................... MC3362, MC3363

AN1002

A Handsfree Featurephone Design Using the MC34114 Speech
Network and the MC34018 Speakerphone ICs ............... MC34018
MC34114

AN1003

A Featurephone Design, with Tone Ringer and Dialer,
Using the MC34118 Speakerphone IC ....................... MC34118, MC34017,
MC145412, MC34119

AN1004

A Handsfree Featurephone Design Using the MC34114 Speech
Network and the MC34118 Speakerphone ICs ................ MC34114, MC34118,
MC34119, MC3417,
MC145412

AN1006

Linearize the Volume Control of the MC34118 Speakerphone ..... MC34118

AN1077

Adding Digital Volume Control to Speakerphone Circuits ......... MC34018, MC34118

AN1081

Minimize the "Pop" in the MC34119 Power Audio
Amplifiers

MC34119

AN1510

A Mode Indicator forthe MC34118 Speakerphone Circuit ......... MC34118

DL136

Telecommunications Device Data

SG98

Linear Telecom Cross Reference

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
8-31

MOTOROLA

-

MC1496
MC1596·

SEMICONDUCTOR - - - - - -

TECHNICAL DATA

BALANCED
BALANCED MODULATORI DEMODULATOR

MODULATO~DEMODULATOR

These devices were designed for use where the output voltage
is a product of an input voltage (signal) and a switching function
(carrier). Typical applications include suppressed carrier and
amplitude modulation, synchronous detection, FM detection,
phase detection, and chopper applications. See Motorola
Application Note AN531 for additional design information.

LSUFFIX
CERAMIC PACKAGE
CASE 632

• Excellent Carrier Suppression - 65 dB typ @ 0.5 MHz
- 50 dBtyp@ 10 MHz
• Adjustable Gain and Signal Handling
• Balanced Inputs and Outputs
• High Common Mode Rejection - 85 dB typ

D SUFFIX
PLASTIC PACKAGE
CASE 751A
(SO-14)

-

P SUFFIX
PLASTIC PACKAGE
CASE 646

1

FIGURE 1SUPPRESSED CARRIER
OUTPUT WAVEFORM

PIN ASSIGNMENTS

VEE

Signal Input
Gain Adjust

NC

Gain Adjust
Signal Input

Output

NC
Carrier Input

Bias

NC

Output

NC

Input Carrier

ORDERING INFORMATION
FIGURE 2SUPPRESSED CARRIER
SPECTRUM

Device

Temperature Range

Package

O'C to +70'C

Ceramic DIP

-55'C to + 125'C

Ceramic DIP

SO-14

MC1496D
MC1496L
MC1496P
MC1596L

Plastic DIP

FIGURE 4 - AMPLITUDE·MODULATION SPECTRUM

FIGURE 3AMPLITUDE MODULATION
OUTPUT WAVEFORM

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
8-32

MC1496, MC1596
MAXIMUM RATINGS· ITA = +25°C unless otherwise noted)

Rating
Applied Voltage
(V6-Va. V1O-V1. V12 -Va. V12- V 10. Va- V 4.
Va-V1. V10-V4. V6-V1O. V2-V5. V3- V 5)
Differential Input Signal

Maximum Bias Current
Thermal Resistance, Junction to Air
Ceramic Dual In-Line Package
Plastic Dual In-Line Package

Symbol

Value

Unit

I1V

30

Vde

Va- V 1O
V4- V 1

+5.0
±(5+15Re)

Vde

15

10

mA

0c/w

RBJA
100
100
160

Metal Package
Operating Temperature Range

°c

TA
010 +70
-5510+125

MCI496
MC1596
Storage Temperature Range

-65to +150

Tstg

ELECTRICAL CHARACTERISTICS (VCC

~

+12 Vde. VEE

~

-B.O Vde.15

~

1.0 mAde. RL

°c
~

3.9 kfl. Re

~

1.0 kfl. TA

~

+ 25°C.

all input and output characteristics are single-ended, unless otherwise noted.)

MCI596

Characteristic
Carrier Feedthrough
Vc = 60 mV(rms) sine wave and
offset adjusted to zero

IC
IC

~
~

Fig.

Note

Symbol

5

1

VCFT

1.0 kHz
10 MHz

Min

-

Typ

IC ~ 1.0 kHz
IC ~ 1.0 kHz

offset adjusted to zero

Carrier Suppression

5

2

-

-

-

40
140

-

-

0.04
20

0.2
100

-

0.04
20

0.4
200

BW3dB

IVei ~ 0.5 Vde

Signal Gain

10

3

6

-

-

AVS

mV(rms)

65
50

-

40

65

-

50

~

5.0 MHz

Parallel Input Resistance
Parallel Input capacitance
Single·Ended OUlput Impedance. I

r,p
eip
~

10 MHz

6

-

Parallel Output Resistance
Parallel Output Capacitance

rop
coo
7

Input Bias Current
IbS

~

11 ; 14; IbC

~ la ~110

-

k
MHz

-

300

-

-

300

BO

-

-

80

-

2.5

3.5

-

2.5

3.5

-

VN

200
2.0

-

-

-

200
2.0

-

kn

-

-

40
5.0

-

kn

Vs ~ 100 mV(rms). I ~ 1.0 kHz; IVei ~ 0.5 Vde
Single-Ended Inpullmpedanee. Signal Port. I

Unit
/LV(rms)

dB

50

8

Max

40
140

8

Typ

VCS

IS ~ 10 kHz. 300 mV(rms)
IC ~ 500 kHz. 60 mV(rms) sine wave
fC = 10 MHz, 60 mV(rms) sine wave

Transadmittance Bandwidth (Magnitude) (RL = 50 ohms)
Carrier Input Port, Vc = 60 mV(rms) sine wave
fS = 1.0 kHz. 300 mV(rms) sine wave
Signal Input Port. Vs = 300 mV(rms) sine wave

Min

-

Vc = 300 rnVp-p square wave:

offset not adjusted

MCI496
Max

-

-

-

40
5.0

-

-

pF

pF
p.A

IbS
IbC

-

12
12

25
25

-

-

12
12

30
30

Iliosl
lioel

-

-

0.7
0.7

5.0
5.0

-

0.7
0.7

7.0
7.0

-

Input Offset Current
liaS ~ 11-14; (ioC ~ 1a-110

7

Average Temperature Coefficient of Input Offset Current

7

-

ITCliol

-

2.0

-

-

2.0

-

nArC

7

-

11001

-

14

50

-

14

BO

p.A

7

-

ITctool

-

90

-

-

90

-

nArC

-

5.0

-

-

5.0

-

Vp·p

-85

-85

-

8.0

-

-'

-

-

8.0

8.0

8.0

-

(TA

~

p.A

-55°C to +125"<:)

Output Offset Current
(lS- 19)

Average Temperature Coefficient of Output Offset Current
(TA

~

-.

-55°C to + 125°C)

Common-Mode Input Swing, Signal Port. fS

= 1.0 kHz

Common-Mode Gain. Signal Port. fS = 1.0 kHz.

9

4

CMV

9

-

ACM

IVei ~ 0.5 Vde

Common-Mode Quiescent Output Vottage (Pin 6 or Pin 9)

10

-

Vout

Oifferenlial Output Voltage Swing Capability

10

-

Vout

Power Supply Current

7

6

16+ 112
114

DC Power Dissipation

ICC
lEE
7

5

Po

-

8-33

Vp-p
Vp-p
mAde

2.0
3.0

3.0
4.0

-

2.0
3.0

4.0
5.0

33

-

-

33

-

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

dB

mW

MC1496, MC1596
GENERAL OPERATING INFORMATION
Carrier Feedthrough

Power Dissipation

Carrier feedthrough is defined as the output voltage
at carrier frequency with only the carrier applied (signal
voltage = 0).
Carrier null is achieved by balancing the currents in
the differential amplifier by means of a bias trim potentiometer (Rl of Figure 5).

Power dissipation, PO, within the integrated circuit
package should be calculated as the summation of the
voltage-current products at each port, i.e. assuming V12
= VS, 15 = IS = 112 and ignoring base current, Po = 215 (V6
- V14) + 15) V5 - V14 where subscripts refer to pin
nur:nbers.

Carrier Suppression

Design Equations

Carrier suppression is defined as the ratio of each
sideband output to carrier output for the carrier and
signal voltage levels specified.
Carrier suppression is very dependent on carrier input
level, as shown in Figure 22. A low value of the carrier
does not fully switch the upper switching devices, and
results in lower signal gain, hence lower carrier
suppression. A higher than optimum carrier level
results in unnecessary device and circuit carrier feedthrough, which again degenerates the suppression figure. The MC1596 has been characterized with a 60
mV(rms) sinewave carrier input signal. This level provides optimum carrier suppression at carrier frequencies in the vicinity of 500 kHz, and is generally recommended for balanced modulator applications.
Carrier feedthrough is independent of signal level, VS.
Thus carrier suppression can be maximized by operating
with large signal levels. However, a linear operating mode
must be maintained in the signal-input transistor pair or harmonics of the modulating signal will be generated
and appear in the device output as spurious sidebands
of the suppressed carrier. This requirement places an
upper limit on input-signal amplitude (see Figure 20). Note
also that an optimum carrier level is recommended in
Figure 22 for good carrier suppression and minimum spurious sideband generation.
At higher frequencies circuit layout is very important
in orderto minimize carrier feedthrough. Shielding may
be necessary in order to prevent capacitive coupling
between the carrier input leads and the output leads.

The following is a partial list of design equations
needed to operate the circuit with other supply voltages
and input conditions.
A. Operating Current
The internal bias currents are set by the conditions at
pin 5. Assume:
15 = IS = 112,
IB«IC for all transistors
then:
R5 = V - 15

B. Common-Mode Quiescent Output Voltage

Biasing
The MC1596 requires three dc bias voltage levels
which must be set externally. Guidelines for setting up
these three levels include maintaining at least 2 volts
collector-base bias on all transistors while not exceeding the voltages given in the absolute maximum rating
table;
30 Vdc ~ [(VS, V12) - (Va, VlO)] ~ 2 Vdc
30 Vdc ~ [(Va, Vl0) - (Vl, V4)] ~ 2.7 Vdc
30 Vdc ~ [(Vl, V 4) - (V5)] ~ 2.7 Vdc
The foregoing conditions are based on the following
approximations:
VS=V12, Va = VlO, Vl =V4

Signal gain (single-ended) at low frequencies is
defined as the voltage gain,
Vo

RL

= Vs = Re+ 2r e where re =

where: R5 is the resistor between
pin 5 and ground
cf> = 0.75 Vat TA = +25°C

The MC159S has been characterized for the condition
15 = 1.0 mA and is the generally recommended value.

Signal Gain and Maximum Input Level

AVS

p _ 500 n

Bias currents flowing into pins 1, 4, a, and 10 are
transistor base currents and can normally be neglected
if external bias dividers are designed to carry 1.0 mA or
more.

26mV
15 (mA)

A constant dc potential is applied to the carrier input
terminals to fully switch two of the upper transistors
"on" and two transistors "off" (VC = 0.5 Vdc). This in
effect forms a cascode differential amplifier.
Linear operation requires that the signal input be
below a critical value determined by RE and the bias
current 15.

Transadmittance Bandwidth
Carrier transadmittance bandwidth is the 3 dB
bandwidth of the device forward transadmittance as
defined by:

= io (each sideband) I V = 0
'Y21C

Vs '" 15 RE (Volts peak)
Note that in the test circuit of Figure 10, Vs corresponds
to a maximum value of 1 volt peak.

Vs (signal)

0

Signal transadmittance bandwidth is the 3 dB
bandwidth of the device forward transadmittance as
defined by:

Common Mode Swing
'Y21S

The common-mode swing is the voltage which may
be applied to both bases of the signal differential amplifier, without saturating the current sources or without
saturating the differential amplifier itself by swinging it
into the upper switching devices. This swing is variable
depending on the particular circuit and biasing conditions chosen.

io (signal) I
= Vs
(.signa I) Vc = 0.5 Vdc, Vo = 0

MOTOROLA LlNEARIlNTERFACE ICs DEVICE DATA
8-34

MC1496, MC1596

Coupling and Bypass Capacitors

Signal Port Stability

Capacitors Cl and C2 (Figure 5) should be selected for
a reactance of less than 5.011 at the carrier frequency.

Under certain values of driving source impedance.
oscillation may occur. In this event. an RC suppression
network should be connected directly to each input
using short leads. This will reduce the Q of the sourcetuned circuits that cause the oscillation.

Output Signal
The output signal is taken from Pins 6 and 12 either
balanced or single-ended. Figure 11 shows the output
levels of each of the two output sidebands resulting
from variations in both the carrier and modulating signal
inputs with a single-ended output connection.
Negative Supply

An alternate method for low-frequency applications is
to insert a 1.0 k11 resistor in series with the input (Pins 1.
4). In this case input current drift may cause serious
degradation of carrier suppression.

VEE should be dc only. The insertion of an RF choke in
series with VEE can enhance the stability of the internal
current sources.

TEST CIRCUITS
FIGURE 5 - CARRIER REJECTION AND SUPPRESSION

FIGURE 6 - INPUT·OUTPUT IMPEDANCE

Vcc
Ik

+12 Vdc

Ik

Re = 1 k
RL
3.9 k

c2
CARRIER O.l"F
INPUTVc --1}--"------""""
VS~_~--~---~
MODULATING
SIGNAL
INPUT
10 k

}--o----e +Vo

f-::o......:....:f-.+V o

-Zout

f-O--..... -V o

12

Zin-

nJro-'L.---,-)12

-Vo

14
6.8 k
-8 Vdc

-8 Vdc

VEE

NOTE: Shielding of input and output leads may be needed
to properly perform these tests.
FIGURE 7 - BIAS AND OFFSET CURRENTS

FIGURE 8 - TRANSCONDUCTANCE BANDWIDTH

VCC
+12 Vdc

Vcc

lk

lk

Re

CARRIER O.l"F
INPUT VC--1f--'--------<>:':l

VS~---.,---__t_--<810

MOOU LATING
SIGNAL
INPUT
10 k

MC1496
MC1596

f-,o-.......--e-Vo

r-t:-:-~71--.-...,--,J

!

12

6.8k

-8 Vdc
VEE

-8 Vdc
VEE

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

8-35

MC1496, MC1596

FIGURE 9 - COMMON MODE GAIN

FIGURE 10 - SIGNAL GAIN AND OUTPUT SWING

Ik
0.5 V

j-,<....-t-... +V,

j-,<....-t-... +Vo

\--o-~_-Vu

Vs

'--,_ _.--' 12
6.8 k
ACM = 20 log IVol

Vs

-8 Vdc
VEE

-8 Vdc
VEE

TYPICAL CHARACTERISTICS
Typical characteristics were obtained with circuit shown in Figure 5, fC '" 500 kHz (sine wave),
VC'" 60 mV(rms). f8 '" 1 kHz,

Vs = 300 mV(rms), TA = +2SoC unless otherwise noted.
FIGURE 12 - SIGNAL.pORT PARALLEL·EIlUIVALENT
INPUT RESISTANCE .ersus FREQUENCY

FIGURE 11 - SIDEBAND OUTPUT .ersus CARRIER LEVELS

~

1.0 M
;;;
,. 500

2.0

?:
'"z

ffi

5

+rjp

=<
w

1.6

<.>

'"
in

SIGNAL INPUT = 600 mV

%

~ 1.2
w

g

.... ~
1/

~

V f..I::::- ~

'"~ 0.4
5
'"

0

~

~

40Lv

50

0

~

0

\

I-""'

-rip

'\.

I-

~

300mV

ro-

100

~

/

0.8

z

w

~

200 mV

5.0

~

:i

100mV

'\

0

~

;t

.g.

100
150
. VC. CARRIER LEVEL (mVlrmsl)

200

1.0
1.0

FIGURE 13 - SIGNAL·PORT PARALLEL·EQUIVALENT
INPUT CAPACITANCE .ersus FREQUENCY

50

5.0
10
I. FREQUENCY (MHz)

FIGURE 14 - SINGLE·ENDED OUTPUT
IMPEDANCE .ersus FREQUENCY

en

5.0

;;:

,g

1

140

u:

%120

~4.0
;!:

12~

w
<.>

z

~
~
5

~ 3.0
~

.... 1-""

~ 2. 0

~
:i

~ 1.0

~

40

a.

if!

2.0

5.0
10
20
I. FREQUENCY (MHz)

50

100

~

6.O~

Cop

~

4.0~

"- .......

20

0

o

.0:;:i

2

o
1.0
I. FREQUENCY (MHz)

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

8-36

~

8.O~

rop

80
60

if

o

z

1O;!:

100

~

:i

-91.0

100

10

100

a.

8

MC1496, MC1596

TYPICAL CHARACTERISTICS (continued)
Typical characteristics were obtained with circuit shown in Figure 5,fC = 500 kHz (sine wiNe),
Vc == 60 mV(rms). fS = 1 kHz, Vs = 300 mV(rms), T A = +25 0 C unless otherwise noted.

FIGURE 15 - SIDEBAND AND SIGNAL PDRT
TRANSADMITTANCES versus FREQUENCY

r--lTTr
r--

1.0
0.9

~

.sw

0.6

t-

0.5

ill
~

II

0.7

z

«
t-

"'-

SllGnMi RT

0.8

"\

r-- f-SIOEBANO~

I

SIGNAL PORT
TRANSADMITTANCE

t-

0.2
>

lout I

0.1

Y21 I°VPI

o

I

1\

I 11111111

~ 0.3

'"

SIDEBAND
TRANSADMITT ANCE

= I_~ACH SIDEBAND)
Y21
Vin (SIGNAL)

0.1

10

-z

l"-

11111

0.4

FIGURE 16 - CARRIER SUPPRESSION
versus TEMPE RATUR E

'I~OI":I;O

1.0

"'-

I vout-0

~

=

i

w

~MC1496-1

30

(+70 0 C)

40

~

~

~

11111

;3

II II

50

""'"

~

>

IVel" 0.5 V(le

I 111111
100

10

MC1596

20

60
10
-75

1000

-50

~

'='
'"
>
'"
z'"
w

r-- -10

w

~

'"u;z

i1 ~lll

'"
-30
D.01

Rl °
Re ° 2

IIIIIII

Re'" 1 k

IIIIIII
0.1

+75

+100

+125

+150 +175

/

kl

IVClo 0.5 Vdc
1111111

«>

TestICi',"it)

Rlo500n

-20

+50

FIGURE 18 - CARRIER SUPPRESSION versus FREQUENCY

~k-

RL = 3.9 k (Standard

Rel

+25

"-

!

'"«

\. /

TA, AMBIENT TEMPERATURE (OC)

FIGURE 17 - SIGNAL·PORT FREQUENCY RESPDNSE
+ 20
Rlo3.9k,i
Re = 500nI
+10

w

'"

[)

·25

IC, CARRIER FREQUENCY (MHzl

~

V

21C'

f..---"

V

V-

/'
IC

Av~~'1
I I ~"I+I ii'll
1.0

10

100

f-

!------'
0.5

0.1

31C

f-"

e--- f-

1.0

5.0

10

50

IC, CARRIER FREQUENCY (MHz)

I, FREQUENCY (MHz)

FIGURE 20 - SIDEBAND HARMDNIC SUPPRESSION
versus INPUT SIGNAL LEVEL

FIGURE 19 - CARRIER FEEDTHROUGH versus FREQUENCY

IC±3IS........0

0

I2fS
l---- - fC±

~

200
fe, CARRIER FREQUENCY (MHz)

400

/

V

.--- V
600

VS. INPUT SIGNAL AMPLITUDE (mV[rms])

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

8-37

800

MC1496, MC1596

FIGURE 21 - SUPPRESSION OF CARRIER HARMONIC
SIDEBANDS verlUs CARRIER FREQUENCY

FIGURE 22 - CARRIER SUPPRESSION
versus CARRIER INPUT LEVEL

IIIII

0

3fC±fS

0

nor-IIIII

fC' 10MHz- r -

0
0

2fC±fS

-or

_
1

-70
0.05

2fC±21~

0.5
1.0
5.0
fC. CARRIER FREQUENCY IMHz}

"-

..-'--"":

0,
70

0.1

.........

0

10

50

o

100

--

./

L

200

fC' 500 kHz

300

400

500

VC. CARRIER INPUT LEVEL (mV[rmsll

OPERATIONS INFORMATION
The MC1596/MC1496. a monolithic balanced modulator circuit, is shown in Figure 23.

FIGURE 23 - CIRCUIT SCHEMATIC
1-)12

This circuit consists of an upper quad differential amplifier

driven by a standard differential amplifier with dual current
sources. The output collectors are cross-coupled so that full-wave
balanced multiplication of the two input voltages occurs. That is,
the output signal is a constant times the product of the two input
signals.
Mathematical analysis of linear ac signal multiplication indicates that the output spectrum will consist of only the sum and
difference of the two input frequencies. Thus, the device may be
used as a balanced modulator, doubly balanced mixer, product
detector, frequency doubler, and other applications requiring
these particular output signal characteristics.
The lower differential amplifier has its emitters connected to
the package pins so that an external emitter resistance may be
used. Also, external load resistors are employed at the device
output.

r---1====~=t====~VD'
OUTPUT
(t)6

4(.)

INPUT
SIGNAL

vs~----1======~=~~=i
I It)

GAIN ADJUST

3
BIAS

so---,--t-------\.
'OD

VEE 1 4 . 0 - - - - 4 - - - 4 - - - - - - - - '

Signal Levels

FIGURE 24 - TYPICAL MODULATOR CIRCUIT

The upper quad differential amplifier maY,be operated either
in a linear or a saturated mode. The lower differential amplifier
is operated in-a linear mode for most applications.
For low-level operation at both input ports, the output signal
will contain sum and difference frequency components and have
an amplitude which is a function of the product of the input signal
amplitudes.
For high-level operation at the carrier input port and linear
operation at the modulating signal port, the output signal will
contain sum and difference frequency components of the modulating signal frequency and the fundamental and odd harmonics of
the carrier frequency. The output amplitude will be a constant
times the modulating Signal amplitude. Any amplitude variations
in the carrier signal will not appear in the output.

f-O---..... -v,

CARRIER NULL

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

8-38

MC1496, MC1596

The gain from the modulating signal input port to the output is

The linear signal handling capabilities of a differential amplifier

With no emitter degeneration, the maximum

the MC1596/MC1496 gain parameter which is most often of interest

input voltage for linear operation is approximately 25 mV peak.

to the d,esigner. This gain has significance only when the lovver
differential amplifier is operated in a linear mode, but this includes

are well defined.

Since the upper differential amplifier has its emitters internally
connectcd, this voltage applies to the carrier input port for all

most applications of the device.
As previously mentioned, the upper quad differential amplifier
may be operated either in a linear or a saturated mode. Approxi·
mate gain expressions have been developed for the MC15961
MC1496 for a low-level modulating signal input and the following
carrier input conditions:

conditions,

Since the lower differential amplifier has provisions for an
external emitter resistance, its linear signal handling range may be
adjusted by the user. The maximum input voltage for linear operation may be approximated from the following expression:

V =-(15)

1) Low-level dc

(RE)VOItS peak.

21 High-level de

3) Low-level ac
4) High-level ac

This expression may be used to compute the minimum value of
RE for a given input voltage amplitude.

These gains are summarized in Table 1, along with the frequency components contained in the output signal.
FIGURE 25 - TABLE 1
VOLTAGE GAIN AND OUTPUT FREQUENCIES

Carrier I"put

Approximate

Output Signal

Signal (Vcl

VolmgeGain

Frequencyls)

Low-level de

High-level de

RL Vc
2(RE + 2'el(~T)

~
RE + 2re

NOTES:

1. Low-level Modulating Signal, VM, assumed in all cases.
Vc is Carrier ,"nput Voltage.
2. When the output signa' contains multiple frequencies,
the gain expression given is for the output amplitude of
each of the two desired outputs, fC + fM and fC - fM·
3. All gain expressions are for a single-ended output. For
a differential output connection, multiply each expression by two.
4. AL = Load resistance.
5. RE = Emitter resistance between pins 2 and 3.
6. re = Transistor dynamic emitter resistance, at +2SoC;

1M

1M

RL Vc(,msl
LOW-level ae

High-level ae

2J2(~T)(RE + 2'el

IC±fM

0.637 RL
RE + 2re

IC±IM. 3IC±IM.
SIC±fM • . . .

26 mV
'e"" 15 (mAl

7. K = Boltzmann's Constant, T = temperature in degrees
Kelvin, q = the charge on an electron.

.!S!
~ 26 mV at room temperature
q

APPLICATIONS INFORMATION
This produ~t detector has a sensitivity of 3.0 microvolts and a
dynamic range of 90 dB when operating at an intermediate frequency of 9 MHz.
The detector is broadband for the entire high frequency range.
For operation at very low intermediate frequencies down to 50
kHz the 0.1 JlF capacitors on pins 8 and 10 should be increased to
1.0 JlF. Also, the output filter at pin 12 can be tailored to a
specific intermediate frequency and audio amplifier input impedance.
As in all applications of the MC159S/MC1496, the emitter
resistance between pins 2 and 3 may be increased or decreased to
adjust circuit gain, sensitivity, and dynamic range.
This circuit may also be used as an AM detector by introclucing
carrier signal at the carrier input and an AM signal at the SSB
input.
The carrier signal may be derived from the intermediate frequency signal or generated locally. The carrier signal may be introduced with or without modulation, provided its level is
sufficiently high to saturate the upper quad differential amplifiet.
If the carrier signal is modulated, a 300 mV(rms) input level is
recommended.

Double sideband suppressed carrier modulation is the basic
application of the MC1596/MC149S. The suggested circuit for
this application is shown on the front page of this data sheet.
In some applications, it may be necessary to operate the
MC1596/MC1496 with a single de supply voltage instead of dual
supplies. Figure 26 shows a balanced modulator designed for
operation with a single +12 Vdc supply. Performance of this circuit is similar to that of the dual supply modulator.
AM Modulator
The circuit shown in Figure 27 may be used as an amplitude
modulator with a minor modification.
All that is required to shift from suppressed carrier to AM
operation is to adjust the carrier null potentiometer for the proper
amount of carrier insertion in the output signal.
However, the suppressed carrier null circuitry as shown in
Figure 27 does not have sufficient adjustment range. Therefore.
the modulator may be modified for AM operation by changing
two resistor values in the null circuit as shown in Figure 28.
Product Detector
The MC159S/MC149S makes an excellent SSB product detector (see Figure 291.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

8-39

MC1496, MC1596

Doubly Balanced Mixer

Phase Detection and FM Detection

The MC15961MC1496 may be used as a doubly balanced
mixer with either broadband or tuned narrow band input and

The MC15961MC1496 will function as a phase detector. Highlevel input signals are introduced at both inputs. When both inputs
are at the same frequency the MC1596/MC1496 will deliver an

output networks.
The local oscillator signal is introduced at the carrier input

output which is a function of the phase difference between the
two input signals.
An FM detector mav be constructed bV using the phase detector principle. A tuned circuit is added at one of the inputs to
cause the two input signals to vary in phase as a function of fre-

port with a recommended amplitude of 100 mV(rms).
Figure 30 shows a mixer with.a broadband input and a tuned

output.
Frequency Doubler

quency. The MC15961MCI496 will then provide an output which

is a function of the input signal frequency.

The MC15961MC1496 will operate as a frequency doubler by

introducing the same frequency at both input ports.
Figures 31 and 32 show a broadband frequency doubler and a
tuned output .very high fre~uency (VHF) doubler, respectively.

TYPICAL APPLICATIONS
FIGURE 26 - BALANCED MODULATOR
1+12 VdcSINGLE SUPPLY)

FIGURE 27 - BALANCEO MODULATOR·DEMODULATOR

Vee
1k

81"

+12Vdc

Uk

Rl
3k

3k
0.1 "F

3.9k
O~E

b>-6-f-'+vo

OUTPUT

:>--.e. -v,

""I=<2

MODULATING
SIGNAL
INPUT

MDDULATI~ +

14

~IGNAL INPUT 10 jJF
:roOmV(rms)
15V

25pF

ISV

6.Bk

10k

CARRIER

,-'Wrlf-'

NULL

10k

50'

100

CARRIER NULL

100

L.J~:::t-+---'

~IGURE

FIGURE 29 - PRODUCT DETECTOR
(+12 VdcSINGLE SUPPLY)

28 - AM MODULATOR CIRCUIT

vee
81"
Rl

1k

3.9k

,y,

V,

MC1496
MC1596

12

MODULATING
SIGNAL
INPUT

-v,

6.ak

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
8-40

I.lk

+12Vdc

MC1496, MC1596

FIGURE 30 - DOUBLY BALANCED MIXER
(BROADBAND INPUTS, 9.0 MHz TUNED OUTPUT)

FIGURE 31 - LOW·FREQUENCY DOUBLER

Vee

·n

1k

R,e

lDD .. H

12

RF INPUT

OD '"

9.5,..H
L1

5-80pF
68 k

OUTPUT

MC159GI
MC14961

9.0MHI
OUTPUT
RL ~ 5011

1Z

90-480pf

-=

-=

14

'DO

'-"'==:::..:..~_~EJdr.-=

t

II "44 TURNSAWG NO. 28 ENAMELED WIRE, WOUND
ON MICROMETAlS TYPE 44.6 TORDlD CORE

VEE

S.ak

'5

-8Vdc

FIGURE 32 - 150 to 300 MHz DOUBLER

Vee
1k

1I

lBnH

...

r..L--....Ll-!~.l-p'i'--

300",HZ
OUTPUT
I-lOpf Rl =son
l-lOpF

L1=lTURNAWG
NQ.18WIRE,7132"1O

t

w

Q

....=>

~
«

'"

:E?

-'
~~
,FREOUENCY

-----t... BALANCEO MODULATOR SPECTRUM
DEFINITIONS

IC
CARRIER FUNDAMENTAL
IS
MODULATING SIGNAL
IC' IS FUNDAMENTAL CARRIER SIDEBANDS

IC' nls FUNDAMENTAL CARRIER SIDEBAND HARMONICS
nlc
CARRIER HARMONICS
nlc' nls CARRIER HARMONIC SIDEBANDS

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
8-41

MOTOROLA

-

MC2830

SEMICONDUCTOR - - - - - -

TECHNICAL DATA

Product Preview
VOICE ACTIVATED
SWITCH

VOICE ACTIVATED SWITCH
The MC2830 circuit incorporates a microphone amplifier (MIC
AMPI, automatic level control (ALCI and a voice activated switch.
The voice activated switch circuit has the ability to distinguish a
voice from the background noise and trigger the switch output
circuit by the voice signal. Therefore, the switching operation is
highly reliable in noisy environments. The ALC range ofthe microphone amplifier is over 50 dB and can be adjusted by an external
resistor. This device is particularly suitable for applications such
as radio transceivers, car radios, message storage recorders, and
voice controlled toys.

SILICON MONOLITHIC
INTEGRATED CIRCUIT

• Microphone Amplifier with External Feedback
• External Resistor Adjust ALC Over 50 dB
• Voice Activated Switch with Externally Controlled Sensitivity
P SUFFIX
PLASTIC PACKAGE
CASE 626

• Low Voltage Operation from 1.8 to 8.0 V

s.
1

D SUFFIX
PLASTIC PACKAGE
CASE 751
(SO-81

FIGURE 1 NF

FUNCTIONAL BLOCK DIAGRAM
Mic Out

ALe

Nse

PIN CONNECTIONS

Mic In

16

I

I
I
I

Reference

VCC

NF

NSC

Mic Out

II

14-----1a - - - '
Gnd

Vee

This document contains information on a product under development. Motorola reserves the right
to change or discontinue this product without notice.

(Top Viewl

ORDERING INFORMATION
Device

MC2830D
MC2830P

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

8-42

SWO
ALC

Gnd

I
I

I

I ~mm
I
L-----

Mic In

Temperature
Range

o to

+70°C

Package
SO-8
Plastic DIP

MC2830
MAXIMUM RATINGS
Rating

Symbol

Value

VCC

10

V

TA

o to +70

°c

Storage Temperature Range

Tstg

-65 to + 150

°C

Loading Current: Pin 3
Pin 6

10
ISWO

200
2.0

/LA
mA

Supply Voltage
Operation Temperature Range

Unit

ELECTRICAL CHARACTERISTICS (VCC = 50 V Input Frequency = 10kHz Loading Resistor = 50 kOhm, TA = 25°CI
Pin

Symbol

Min

Typ

Max

Supply Voltage

8

VCC

1.8

-

8.0

V

Quiescent Current

8

ID

-

2.0

mA

80

-

dB

Characteristic

MIC AMP Open Loop Gain

AVOL

Total Harmonic Distortion of MIC AMP
(VO = 0.1 Vrmsl

3

Maximum MIC AMP Output Swing
ALC Range (-6.0 dB, R1

= 33 k, Vin =

1.0 VI

Ripple Rejection

THD

-

1.0

3

Vo

-

0.16

3

ALC

40

50

3

RR

-

55

Voice Trigger Level Above Noise

Vsln

Switch Output Current

6

ISWO

Switch Output Voltage
High
(lSWO = 2.0 mAl
Low

6

VSWO

4.6

-

3.0

-

-

2.0

-

Unit

%

Vrms
dB
dB
dB
mA
V

0.4

PIN FUNCTION DESCRIPTION
Pin No.

Description

Function

1

MICIN

Input of the microphone amplifier. The gain of the amplifier is set by the external components of
the Rf, R2, and C2 (See formula 21.

2

NF

This is the negative feedback input pin of the microphone amplifier.

3

MIC OUT

Output of the microphone amplifier. It is designed to drive a maximum load current of 200 pA.

4

GND

The ground pin.

5

ALC

This pin is for the ALC level detector filter. An RC is connected to this pin.

6

SWO

This is the output pin of the voice activated switch. A resistor at this pin sets the voice trigger
level above the noise level. The current drain of this pin is around 20 pA typical with a switch
"off" state. The maximum output voltage level is VCC-VCES with a maximum output current of
2.0 mA. As shown in Figure 3, this output is used to connect a switch time delay circuit to unify
the "on" time. In Figure 3, C5 is the time delay capacitor which controls the "on" time of TR1.

7

NSC

The Noise Storing Capacitor at this pin sets the rise time and decay time. The rise time is
determined by the constant of the R5C4.

8

VCC

This pin has a low voltage operation from 1.8 to 8.0 Volts.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
8-43

MC2830
FIGURE 2 - TEST CIRCUIT

Mic
C1
Mic Int* o----- SWO
ALC 5

4 Gnd
=Gnd

R41.0M
Mic Out 0 - - - - - - '

FIGURE 3 - TYPICAL APPLICATION CIRCUIT
Mic Sensitivity Control

~-=:ir·O_/L~F_~r-___________________--'
F~ov;'

R3 5.6 k

C1

R1

10/LF

33 k

Mic

NF
Rf 100 k
3

=
R2

~~---------~VCC

Mic In

Switch Output

NSC r 7'--_----t
01

Mic Out

SWO

1-'6'-----;_----VlIIr---J~.......-L

1.0 k

R615 k
4

5

Gnd

C32.2/LF

Mic Out

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

8-44

MC2830
Voice Detection and Switching
A traditional voice activated circuit design is unable
to distinguish between voice and noise in the incoming
signal. In a noisy environment, the switch is often mistriggered by noise, or the activation sensitivity must be
reduced. The MC2830 voice activated circuit has overcome this weakness in traditional designs. The switch
is activated by voice level above the noise and is not
affected by the background noise level. This is accomplished by utilizing the differences in voice and noise
waveforms. Voice waveforms generally have a wide
range of variation in amplitude, whereas noise waveforms are more stable. With this in mind, the NOISE
MONITOR in Figure 1 was designed to have an output
characteristic which has a slow attack time but a fast
decay time. When the envelope of incoming signal,
which consists of voice and noise, is passing through
it, the voice will not be stable during the long time constant of RC (approx. 45 seconds) and it is therefore
degraded. Whereas the noise content of incoming signal is delayed at the rising edge of its envelope, as in
Figure B. Meanwhile, the envelope of the incoming signal is passing through the DC SHIFTER path, which does
not introduce any time constant or amplification, but
gives the incoming signal envelope a dc offset set by
resistor RB.
By comparing the two signals from the output of the
DC SHIFTER and the NOISE MONITOR, as in Figure B,
the voice is distinguished from the incoming Signal and
activates the switch circuit. The sensitivity of voice activation depends on the value of RB. The voice activation
sensitivity is reduced from 3.0 dB to 8.0 dB above the
noise if RB changes from 14 k to 7.0 k.

FUNCTIONAL DESCRIPTION
As shown in the block diagram, the features provided
by the MC2830 are the microphone amplifier with ALC
and voice switch circuit. The detailed functional circuitry
is described below.
Microphone Amplifier
The MIC AMP is a non inverting amplifier as shown
in Figure 4. An ALC controlled resistance is connected
to the input pin of the MIC AMP to accomplish ALC
function. The voltage gain and ALC attenuation ratio are
given in formulas (1) and (2):
Voltage Gain = 1

+ R2

=

R~/wC2

(1)

ALC = 20 log (Rl + Ral c)
(2)
Ralc
Replacing Rf by a Zf network can be formed as a band
pass, low pass or high pass network for various
applications.

FIGURE 4 - MIC AMPLIFIER WITH ALC

Pin 3

ALC Control

FIGURE 6 - WAVEFORMS OF VOICE DETECTION
AND SWITCHING

Incoming Signal
Pin 1

A typical application circuit is shown in Figure 3, the
ALC performance of the microphone amplifier is shown
in Figure 5.

RGURE 5 - ALC CHARACTERISTICS

I

I

Level DetectOutPut~
Pin 5
~I

-10

/

I

L

I

I

Noise Level Detection

61J=:==:,t

Noise Monitor Output
DC Shifter Output ~

/

:

:

:::

DC Level Detection

comparatoroutPut~

-50
-60
0.1 mV

r -

1.DmV

lDmV
D.1V
MIC INPUT LEVEL

1.0 V

10 V

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
8-45

MOTOROLA

-

MC2831A

SEMICONDUCTOR - - - - - -

TECHNICAL DATA

LOW POWER FM TRANSMITTER SYSTEM
The MC2B31A is a one-chip FM transmitter subsystem designed
for cordless telephone and FM communication equipment. It
includes a Microphone Amplifier, Pilot Tone Oscillator, Voltage
Controlled Oscillator and Battery Monitor.
• Wide Range of Operating Supply Voltage (3.0 V-B.O V)

LOW POWER
FM TRANSMITTER SYSTEM

• Low Drain Current (4.0 mA Typ Full Operation at
VCC = 4.0 V)

SILICON MONOLITHIC
INTEGRATED CIRCUIT

• Battery Check!? (290 /-LA Typ at VCC = 4.0 V)
• Low Number .of External Parts Required
• Users Must Comply with Local Regulations on R.F.
Transmission (FCC, DOT, P.T.T., etc)

FUNCTIONAL BLOCK DIAGRAM
P SUFFIX
PLASTIC PACKAGE
CASE 648
16

~.

16'~ro'

2

15

1

o SUFFIX
PLASTIC PACKAGE
CASE 7518
(50-16)

14

PIN ASSIGNMENTS

40--..-_

13

Variable
Reactance
Output

12

Decoupling
Modulator
Input

6Q-_~--'

11
MicAmp
Input 5

7

10

MicAmp 6
Output
Tone 7
Switch

Tone
8

Output

1---~9

ORDERING INFORMATION
Device
MC2831AD
MC2831AP

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

8-46

Temperature
Range
- 30°C to

+ 75°C

Package
SO-16
Plastic DIP

MC2831A

MAXIMUM RATINGS (TA ~ 25'C unless otherwise noted)
Rating

Symbol

Value

Power Supply Voltage

VCC

10

Unit
Vdc

Operating Supply Voltage Range

VCC

3.0 to 8.0

Vdc

Battery Checker Output Sink Current

ILED

25

rnA

Junction Temperature

TJ

+150

Operating Ambient Temperature Range

TA

-30 to +75

Tstq

-65 to + 150

'c
'c
'c

Storage Temperature Range

ELECTRICAL CHARACTERISTICS (VCCl ~ 4.0 Vdc, VCC2 ~ 4.0 Vdc, TA ~ 25'C, unless otherwise noted)
Symbol

Pin

Min

Typ

Max

Drain Current

ICCl

12

150

290

420

,.,.A

Drain Current

ICC2

4

2.2

3.6

6.5

rnA

Characteristic

Unit

BATTERY CHECKER
Threshold Voltage (LED Off

~

On)

VTB

11

1.0

1.2

1.4

Vdc

VOSAT

10

-

0.15

0.5

Vdc

AV

5,6

27

30

33

dB

Output DC Voltage

VOdc

6

1.1

1.4

1.7

Vdc

Output Swing (Vin ~ 30 mV rms , fin ~ 1.0 kHz)

VOP-P

6

0.8

1.2

1.6

Vp-p

THO

6

-

0.7

-

%

Output Saturation Voltage
(Pin 11 ~ 0 V, Pin 10 Sink Current

~

5.0 rnA)

MIC AMPLIFIER
Voltage Gain, Closed Loop
(Vin ~ 1.0 mV rms, fin ~ 1.0 kHz)

Total Harmonic Distortion
(VO ~ 31 mV rms , fin ~ 1.0 kHz)
PILOT TONE OSCILLATOR (250

n

LOADING)
VAFO

8

-

50

-

mV rms

Output DC Voltage

VOdc

8

-

1.4

-

Vdc

Total Harmonic Distortion
(fo ~ 5.0 kHz, VAF ~ 150 mV rms )

THO

8

-

1.8

5.0

%

-

7

1.1

1.4

1.7

Vdc

Output AF Voltage (fo

~

5.0 kHz)

Tone Switch Threshold
FM MODULATOR (120

n

LOADING)
VRFO

14

-

40

-

Output DC Voltage

VOdc

14

-

1.3

-

MOdulation Sensitivity (Note 1)
(Vin ~ 1.0 V ± 0.2 V)

SEN

3,14

6.0

10

18

Hz/mVdc

Maximum Deviation (Note 1)
(Vin ~ 0 V to +2.0 V)

Fdev

3,14

=2.5

"5.0

" 12.5

kHz

-

14

60

MHz

Output RF Voltage (fa

~

16.6 MHz)

RF Frequency Range

..

I

-

-

Note 1. Modulation sensitivity and maximum deviation are measured at 49.815 MHz. which IS the third harmoniC of the crystal frequency .

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
8-47

mV rms

Vdc

MC2831A
FIGURE 1 -

TEST CIRCUIT

-~vv-,.---1D

4.7 p.H

16.605 MHz

Mod Out

16

0.0047
15

Mod In

14

RF Out
(16.605 MHz)

12

VCC1

MC2831A

Battery

11

Checker In

LED

10

L1

0.047

Toke America
7PA Type
126AN - 6708X

<>-I-jf--+-o VCC2
20 mH
Ose Coil

FIGURE 2 -

SINGLE CHIP FM VHF TRANSMITTER AT 49.7 MHz

4.7 f..tH

------to 16.5667 MHz
~------101---~

~

-

51 pF
100pF

( J"
~

i1
J

5.0pF

0

I~ 15 pF

39 pF

~;j;: 30 pF

RF Output
49.7 MHz
- 30 dBm

0.47,uH

NOTES:
$1 is a normally closed push button type switch.

Battery checker circuit (Pins 10, 11) is not used in this application.

The crystal used is fundamental mode, calibrated for paraliel resonance
with a 32 pF load. The 49.7 MHz output is generated in the output buffer,
which generates useful harmonics to 60 MHz.

All capacitors in microfarads, inductors in Henries and resistors in
Ohms, unless otherwise specified.

The network on the output at Pin 14 provides output tuning and impedance matching to 50 n at 49.7 MHz. Harmonics are suppressed by more
than 25 dB.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

8-48

MOTOROLA

-

SEMICONDUCTOR

Me2833

TECHNICAL DATA

LOW POWER
FM TRANSMITTER
SYSTEM

LOW POWER FM TRANSMITTER SYSTEM
MC2833 is a one-chip FM transmitter subsystem designed for
cordless telephone and FM communication equipment. It includes
a microphone amplifier, voltage controlled oscillator and two auxiliary transistors.
• Wide Range of Operating Supply Voltage (2.8-9.0 V)
• Low Drain Current (ICC = 2.9 mA Typ)
• Low Number of External Parts Required
• -30 d8m Power Output to 60 MHz Using Direct RF Output

• + 10 dBm Power Output Attainable Using On-Chip Transistor
Amplifiers

,.

16#
I

I

• Users Must Comply with Local Regulations on R.F.
Transmission (FCC, DOT, P.T.T., etc)

PSUFAX
PLASTIC PACKAGE
CASE 648

D SUFFIX
PLASTIC PACKAGE
CASE 751B
(50-16)

FUNCTIONAL BLOCK DIAGRAM

16

PIN ASSIGNMENTS
Variable

15

2

Reactance
Output
Oecoupling

3

14
Mic
Amp

4

13

12

5

J,
6

11

Modulator
Input

10

8

9

Tr 2
Base

MicAmp
Input

Tr2
Emitter

Gnd
Tr 1
Emitter

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
8-49

RF
Output

MicAmp
Output 4

Trl
Base

7

} RF
Osc

Tr2
Collector
VCC
Trl
Collector

MC2833

MAXIMUM RATINGS
Ratings

Unit

Symbol

Value

Power Supply Voltage

VCC

10 (max)

V

Operating Supply Voltage Range

VCC

2.8-9.0

V
·C

Junction Temperature

TJ

+150

Operating Ambient Temperature

TA

-30to +75

·C

Tstg

-65 to + 150

·C

Storage Temperature Range

ELECTRICAL CHARACTERISTICS (VCC = 4.0 V, TA = 25·C, unless otherwise noted)
Characteristics

Drain Current (No input signal)
FM MODULATOR

=

Vout RF

14

60

90

130

Output DC Voltage (No input signal)

Vdc

14

2.2

2.5

2.8

V

Modulation Sensitivity (fa = 16.6 MHz)
(Vin = 0.8 V to 1.2 V)

SEN

3.0
14

7.0

10

15

HzlmVdc

-

-

-

Maximum Deviation (fa = 16.6 MHz)
(Vin = 0 V to 2.0 V)

Fdev

3.0
14

3.0

5.0

-

-

10

kHz

Av

4.0
5.0

33

dB

Output RF Voltage (fa

16.6 MHz)

-

mVrms

MIC AMPLIFIER
Closed loop Voltage Gain (Vin = 3.0 mVrms)
(fin = 1.0 kHz)

27

30

-

-

-

Output DC Voltage (No input signal)

Vout de

4.0

1.1

1.4

1.7

V

Output Swing Voltage (Vin = 30 mVrms)
(fin = 1.0 kHz)

Vout p-p

4.0

O.B

1.2

1.6

Vp-p

THO

4.0

-

0.15

2.0

%

Max

Unit

Total Harmonic Distortion (Vin = 3.0 mVrms)
(fin = 1.0 kHz)
AUXILIARY TRANSISTOR STATIC CHARACTERISTICS
Characteristics

= 5.0 !LA)
Collector Emitter Breakdown Voltage (lC = 200 !LA)
Collector Substrate Breakdown Voltage (lC = 50 !LA)
Emitter Base Breakdown Voltage (IE = 50 !LA)
Collector Base Cut Off Current (VCB = 10 V)
(IE = 0)
DC Current Gain (lC = 3.0 rnA)
(VCE = 3.0 V)
Collector Base Breakdown Voltage (lC

Symbol

Min

Typ

V(BR)CBO

15

45

V(BR)CEO

10

15

V(BR)CSO

-

70

-

6.2

-

-

200

nA

hFE

40

150

-

-

tr

-

500

-

MHz

2.0

-

pF

3.3

-

pF

V(BR)EBO
ICBO

V
V
V
V

AUXILIARY TRANSISTOR DYNAMIC CHARACTERISTICS
Current Gain Bandwidth Product (VCE = 3.0 V)
(lc = 3.0 rnA)
Collector Base Capacitance (VCE = 3.0 V)
(lc = 0)

CCB

Collector Substrate Capacitance (VCS = 3.0 V)
(lC = 0)

CCS

-

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
8-50

MC2833

FIGURE 1 -

TEST CIRCUIT

Crystal: fo = 16.605 MHz
Cl = 30 pF
Co = 6.1 pF
RS -= 10!! Max

RF Out

Base 2

Emitter 2

Collector 2

Emitter 1

Base 1

FIGURE 2 -

SINGLE CHIP VHF NARROWBAND FM TRANSMITTER
______ Lt

Xl

r----,

390 k

AUdiO>

Dynamic

Input

Mike

I

>rt--rl
-

I

I~ 1.0k

I
I

Electret

I

~Ii~~~npa~~~e

:

and biasing

t~
~:

I--t--t-~----:

I

RFOutPut

+5.0 to + 10 dBm
(see Note 4)

Ce2

Rbl

IL ___ +--_ _ _ _ _ _---..._ _ _ _ _ _ _ _----i>-,

NOTES:

VCC

~

9.0 Vde

J

1.0 MF
tantalum

1. Components versus output frequency:

Rel
Rbl
Cel
Ce2
Cl
C2
C3
C4
C5
LlII'H) l2II'HI
33 p
220 p
390 k
33 p
33 P
470 P
33 p
47 p
0.22
330
0.22
68 p
68 p
470 p
20 p
120 p
150
300 k
12 P
10 P
0.22
0.22
47 p
10 p
68 p
1000 p
18 p
12 p
33 p
150
220 k
0.10
0.15
2. Crystal Xl is fundamental mode, calibrated for parallel resonance with a 32 pF load. The final output frequency is generated by frequency
multiplication within the MC28331C. The RF output buffer (Pin 14) and Q2 transistor are used as a frequencytripler and doubler, respectively. in the
76 and 144 MHz transmitters. The Q1 output transistor is a linear amplifier in the 49.7 MHz and 76 MHz transmitters, and a frequency doubler
in the 144 MHz transmitter.
Output RF
50 MHz
76 MHz
144 MHz

Xl IMHz)
16.6667
12.6000
12

Lt II'H)
3.3-4.7
5.1
5.6

3. All coils used are 7 mm shielded inductors,CoilCraft series Ml175A, M1282A-M1289A, M1312A or equivalent
4. Power output is F:;j + 10 dBm for 50 MHz and 76 MHz transmitters, and
drops with lower Vee.

F:;j

+ 5.0 dBm for the 144 MHz transmitter at Vce = 8.0 V. Power output

5. All capacitors in microfarads, inductors in Henries and resistors in Ohms unless otherwise specified.
6. Other frequency combinations may be set-up by simple scaling of the 3 examples shown.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

8-51

MC2833

FIGURE 3 - BUFFER/MULTIPLIER (X3. PIN 14)
(16 MHz FUNDAMENTAL)

FIGURE 4 - INPUT TO DOUBLER (PIN 13)
(50 MHZ x 3 COMPONENT)

FIGURE 5 - DOUBLER OUTPUT 76 MHz (PIN 11)

FIGURE 6 - SPECTRUM

FIGURE 7 - OUTPUT SPECTRUM (50 MHz)

FIGURE 8 - MODULATION SPECTRUM
(1.0 kHz SHOWING CARRIER NULL)

-43 dB

MOTOROLA LlNEARIiNTERFACE ICs DEVICE DATA
8-52

MC2833

FIGURE 9 -

144 MHzlX12 MULTIPLIER

FIGURE 10 -

FIGURE 11 -

CIRCUIT SIDE VIEW

GROUND PLANE ON COMPONENT SIDE

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

8-53

MC2833

FIGURE 12 - COMPONENT VIEW

'""'11(1----------2.0"----------,l..~1

1.5"

NOTES,
• Positive artwork povided.
• Drill holes must be plated to ensure making all groung (VEE)

connectionsl
• Resistors labelled
if used.

11-

are used for biasing of electret microphone

• Capacitors labelled "SM" are silver mica.

• Final board size is 1.5" x 2.0".

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

8-54

-

MOTOROLA

SEMICONDUCTOR _ _ _ _ __

MC3335

TECHNICAL DATA

LOW POWER NARROWBAND FM RECEIVER
· .. includes dual FM conversion with Oscillators, Mixers, Quadrature Discriminator, and Meter Drive/Carrier Detect Circuitry. The
MC3335 also has a comparator circuit for FSK detection.

LOW POWER
DUAL CONVERSION
FM RECEIVER
SILICON MONOLITHIC
INTEGRATED CIRCUIT

• Complete Dual Conversion Circuitry
• Low Voltage: VCC = 2.0 to 6.0 Vdc
• Low Drain Current (Typical 3.6 mA with VCC
• Excellent Sensitivity: - 3.0 dB Input Limiting

= 3.0 Vdc)
= 0.7 /LV

• Externally Adjustable Carrier Detect Function
• Separate Data Shaping Output Circuitry
• Data Rate Up to 35000 Baud Detectable
• 60 dB RSSI Range

P SUFFIX
PLASTIC PACKAGE
CASE 738

• Low Number of External Parts Required
• Manufactured in Motorola's MOSAIC Process Technology
• MC13135 is Preferred for New Designs

20#1

OW SUFFIX
PLASTIC PACKAGE
CASE751D
(SO-20L)

TYPICAL APPLICATION AS A FIXED RECEIVER

PIN CONNECTION AND
FUNCTIONAL BLOCK DIAGRAM

1st Mixer Input

1 <---~..-:-7lo------'

2nd La Emitter 2
2nd La Base 3

17 1st Mixer Output

2nd Mixer Output 4

limiter Decoupling 7

14 Comparator Output

Limiter Oecouptiog 8

13 Comparator Input

11 Quadrature Coil

To Carrier
Detect Indicator

ORDERING INFORMATION
Device
MC33350W
MOSAIC is a trademark of Motorola, Inc.

MC3335P

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

8-55

Temperature
Range
- 40° to

+ 85°C

Package
SO-20
Plastic OIP

MC3335
MAXIMUM RATINGS (TA

= 25·C unless otherwise noted)

Pin

Symbol

Value

Unit

Power Supply Voltage

5

VCC(max)

7.0

Vdc

Operating Supply Voltage Range
(Recommended)

5

VCC

2.0 to 6.0

Vdc

1,20

Vl-20

Rating

> 5.0 Vdc)

1.0

Vrms

TJ

150

·C

Operating Ambient Temperature Range

-

TA

-40 to +85

·C

Storage Temperature Range

-

Tstg

-65 to +150

·C

Input Voltage (VCC

Junction Temperature

ELECTRICAL CHARACTERISTICS (VCC

= 5.0 Vdc, fo = 49.7 MHz, Deviation = 3.0 kHz, TA = 25·C, test circuit of Figure 2,
unless otherwise noted I

Pin

Min

Typ

Max

Unit

Drain Current

5

-

4.5

7.0

mAde

Input for - 3.0 dB Limiting

-

2.0

12

250

Noise Output (RF Signal Level = 0 mY)

12

-

0.7

Recovered Audio (RF Signal Level = 1.0 mY)

Carrier Detect Threshold (below VCC)

9

Meter Drive Slope

9

Input for 20 dB (S+ N/N)
First Mixer 3rd Order Intercept (Input)

-

First Mixer Input Resistance (Rp)

-

First Mixer Input Capacitance (C p )

-

Characteristic

Second Mixer Conversion Voltage Gain

-

Detector Output Resistance

12

First Mixer Conversion Voltage Gain

FIGURE 1 -

-

250

-

0.64

-

-

100

-

1.3

7.2

-

pF

18

-

dB

-

21
1.4

II

VCC
20 k

HM.....- -... RA

--..,

tl

L __ ...J -::-

Lp = 660 ",H
Cp = 180 pF

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
8-56

",Vrms
dBm

RF Input : r - - l : J 2 . 6
49.7 MHz
0.01

I

Vdc
",AldB

690

TEST CIRCUIT

To Carrier
Detect Indicator

mVrms

-

-20

-

10 k

",Vrms
mVrms

n
dB

kn

MC3335
FIGURE 2 -

12
11 f10
9.0

1

L'

I

~ ~C3335

7.0

./

./

ICC. Carr. Det. High (RF in = 0 mV)

/'

.s

1l

./

6.0

5.0

:;;:

./

I----

FIGURE 4 -

-50

o
2.0

3.0

FIGURE 5 -

4.0
VCC IV)

5.0

6.0

7.0

8.0

(S + N)/N versus INPUT

+1 0
S+N

rs::

~ -20
~ -30

""-

z
; -40
-50

-1 0

"'"

r-.....

I"-

1""-

~-30

l'...

"'"

-50

N

.112 7.5 k
-60 MC3335
-70
-50

/

10

FIGURE 7 -

//

-20

/

V

Desired Producty

-40
-50

-60

/

V

/

- -.....\

I""'"'"

\ '-r--

N

/3rd Order Intermod._
Products

:>

V
/

DETECTOR OUTPUT versus FREQUENCY

~ 2.0

/

/

-100 -90 -80 -70

3.0

1-/

/

*,
t.D1

4.0

/'"

~/

o
-10

1.0

/

-60 -50 -40
RF INPUT (dBm)

-30

~20

N

-80
-130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30
RF INPUT (dBm)

-40 -30

1ST MIXER 3RD ORDER INTERMODULATION

20

~ -30

~

;-40

-70
-80
-130 -120 -110 -100 -90 -80 -70 -60
RF INPUT (dBm)

FIGURE 6 -

S+N

-...

0

~-20

-60

-SO

100

J)

+20

+10

-70

200

II

I.U

o

-10

-40

-30

--

-20
-10
10
20
RELATIVE INPUT FREQUENCY 1kHz)

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
8-57

4
3

/d

(S + N). N OF 2ND MIXER

+20

-10

3.0

o
o

-40 -30

_I>- 5

,

k:::::::; ~~ 'Recovered Audio

1.0

3.0
2.0
-130 -120 -110 -100 -90 -80 -70 -60
RF INPUT IdBm)

600

"

----~~

4.0

2.0

4.0

700

ICC. Carr. Det. Low IRF in = 10 mV)

6.0

./

1 7.0
5.0

800

8.0

Vc~

8.0

E>

FIGURE 3 - DRAIN CURRENT. RECOVERED
AUDIO versus SUPPLY

Imeter versus INPUT

I--

30

40

MC3335
CIRCUIT DESCRIPTION
Following the first mixer, a 10.7 MHz ceramic bandpass filter is recommended. The 10.7 MHz filtered signal
is then fed into one second mixer input pin, the other
input pin being connected to VCC. Pin 5 (VCC) is treated
as a common point for emitter-driven signals.
The 455 kHz IF is typically filtered using a ceramic
bandpass filter, then fed into the limiter input pin. The
limiter has 10 IlV sensitivity for - 3.0 dB limiting, flat to
1.0 MHz.
The output of the limiter is internally connected to
the quadrature detector, including a quadrature capacitor. A parallel LC tank is needed externally from Pin 11
to Vcc. A 39 Idl shunt resistance is included which
determines the peak separation ofthe quadrature detector; a smaller value will increase the spacing and linearity but decrease recovered audio and sensitivity.
A data shaping circuit is available and can be coupled
to the recovered audio output of Pin 12. The circuit is
a comparator which is designed to detect zero crossings
of FSK modulation. Data rates of up to 35000 baud are
detectable using the typical application. Hysteresis is
available by connecting a high-valued resistor from
Pin 13 to Pin 14. Values below 120 Idl are not
recommended as the input signal cannot overcome the
hysteresis.
The meter drive circuitry detects input signal level by
monitoring the limiting of the limiting amplifier stages.
Figure 2 shows the unloaded current at Pin 9 versus
input power. The meter drive current can be used
directly (RSSI) or can be used to trip the carrier detect
circuit at a specified input power. To do this, pick an RF
trip level in dBm. Read the corresponding current from
Figure 2 and pick a resistor such that:
R9 = 0.64 Vdc /19
Hysteresis is available by connecting a high-valued
resistor RH between Pin 9 and 10. The formula is:
Hysteresis = VCC/(RH x 10- 7 ) dB

The MC3335 is a complete FM narrowband receiver
from antenna input to audio preamp output. The low
voltage dual conversion design yields low power drain,
excellent sensitivity and good image rejection in narrowband voice and data link applications.
In the typical application diagram, the first mixer
amplifies the signal and converts the RF input to 10.7
MHz. This IF signal is filtered externally and fed into the
second mixer, which further amplifies the signal and
converts it to a 455 kHz IF signal. After external bandpass filtering, the low IF is fed into the limiting amplifier
and detection circuitry. The audio is recovered using a
conventional quadrature detector. Twice-IF filtering is
provided internally.
The input signal level is monitored by meter drive
circuitry which detects the amount .of limiting in the
limiting amplifier. The voltage at the meter drive pin
determines the state of the carrier detect output which
is active low.

APPLICATION
The first local oscillator can be run using a free running LC tank, as a VCO using PLL synthesis, or driven
from an external crystal oscillator. At higher VCC values
(6.0-7.0 V), it has been run to 170 MHz. The second local
oscillator is a common base Colpitts type which is typically run at 10.245 MHz under crystal control.
The mixers are doubly balanced to reduce spurious
responses. The first and second mixers have conversion
gains of 18 dB and 22 dB (typical), respectively. Mixer
gain is stable with respect to supply voltage. For both
conversions, the mixer impedances and pin layout are
designed to allow the user to employ low cost, readily
available ceramic filters. Overall sensitivity is shown in
Figure 5. The input level for 20 dB (S + N)/N is 1.3 /LV
using the two-pole post-detection filter is demonstrated.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

8-58

-

MOTOROLA

SEMICONDUCTOR _ _ _ _ __

MC3356

TECHNICAL DATA

WIDEBAND
FSK
RECEIVER
WIDEBAND FSK RECEIVER
SILICON MONOLITHIC
INTEGRATED CIRCUIT

· .. includes Oscillator, Mixer, Limiting IF Amplifier, Quadrature
Detector, Audio Buffer, Squelch, Meter Drive, Squelch Status output, and Data Shaper comparator. The MC3356 is designed for
use in digital data communications equipment.
• Data Rates up to 500 kilobaud
• Excellent Sensitivity: - 3 dB Limiting Sensitivity
30 ILVrms @ 100 MHz
• Highly versatile, full function device, yet few external parts
are required

~

20

• Down Converter Can be Used Independently - Similar
to NE602

1

PSUFFIX
PLASTIC PACKAGE
CASE 738

DWSUFFIX
PLASTIC PACKAGE
CASE 751D
(SO-20LJ

FIGURE 1 -

FUNCTIONAL BLOCK DIAGRAM

FIGURE 2 -

PIN CONNECTIONS

RF

vee

RF
Ground

1

Ceramic

+ Comparator

Filter

- Comparator

Squelch Status

Squelch Control
Buffered Output

10
Limiter Bias
Quadrature Detector
Tank

r-=.=.;:--,
vee

I

I

I
I

I
I

Demodulator
Filter
Quad Input

Il.. _____ -lI

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

8-59

MC3356

MAXIMUM RATINGS
Rating
Power Supply Voltage

Symbol

Value

Unit

VCClmax)

15

Vdc

VCC

3.0 to 9.0

Vdc

RFVCC

3.0 to 12.0

Vdc

Operating Power Supply Voltage Range (Pins 6, 10)
Operating RF Supply Voltage Range (Pin 4)
Junction Temperature

TJ

150

"C

Operating Ambient Temperature Range

TA

-40 to +85

·C

Tstg

-65 to +150

·C

Po

1.25

W

Storage Temperature Range
Power Dissipation. Package Rating

ELECTRICAL CHARACTERISTICS
.

(VCC = 5.0 Vdc, 10 = 100 MHz, losc = 110.7 MHz,I11 = :t75 kHz, Imod
source TA = 25·C test circuit 01 Figure 3 unless otherwise noted)

Characteristics

Min

-

Drain Current Total, RF VCC and VCC
Input lor - 3 dB limiting
Input for 50.dB quieting (S

~ N)

2.5

-

Mixer/Oscillator Frequency Range (Note 1)
IF/Quadrature Detector Frequency Range (Note 1)

Max

Unit

25

mAdc

0.2 to 150
0.2 to 50

Meter Drive

7.0

Squelch Threshold

-

0.8

Demodulator Output, Pin 13

-

5.0

-

AM Rejection (30% AM, RF Yin = 1.0 mVrms)

-

260

-

Mixer Input Capacitance, 100 MHz

50
0.5

-

Note 1: Not taken in Test Circuit of Figure 3; new component values required.

FIGURE 3 - TEST CIRCUIT
Oemod

Squelch
Status

Data Output

47 k

47 k

Out

'30 k
,8 k

100 MHz

RF I

~_o_. ,

'0 k

np~U' ~r1__1"_0:IO:'~~~~-=~~~~~-L~~~~3'_3~k~~\~i~~~~~~I"~_~

(;4
y__

__

5,

'7

,6

,5

'4

Compl + I Camp! - I Squelch Squelch Demod
Status Control
Out

Filter

Ll-ll0.7 MHz, 0.4 ",H
7T #22,
Form
w/slug & can
L2-10.7 MHz, 1.5 ",H
20T #30,
Form
w/slug & can
T1-muRata
SFE10.7 MA5-Z
or
KYOCERA
KBF10.7MN-MA

'II,.

'II,.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
8-60

n

20
60

Mixer Input Resistance, 100 MHz

1.0 kHz, 50

Typ

30

Mixer Voltage Gain, Pin 20 to Pin 5

=

Input

____,______'

",Vrms
",Vrms

n
pF
MHz
MHz
dB
Vrms
tLAldB
Vdc

MC3356

FIGURE 4 - OUTPUT COMPONENTS OF SIGNAL, NOISE,
AND DISTORTION
10

1

II

s + IN J
-10
a;

5I!=

10

5- 30
!!;!

~-40
-50

I'

FIGURE 5 - METER CURRENT versus SIGNAL INPUT

10 = IIOOIM~Z I
1m = 1.0 kHz
III = ± 75kHz

V
/

-r---

:z

rrrrTTTI'I'lrrrrnlTTTT'TT'TTTTIlTrrT1'TnTIIrTTTTnnTI

600

H-H-ttttftt-t-t-Htttttt-t+-t++tttH-H+H:IIII-'Ft-H-ttR1t

0::

400 H-H-t+ftttI+H-++ttltl-++:.r1'Httll-t+++t+HlH+t+tftHll

g§

300 f-+H-++Hltt+f-++J,IIllI--H-H+It+tt-++++-++HlH+H-IH1fIl

!i

a

N+ 0

700

I-'

~ 100H-~H+~~r+~~-+++~ffir++-++t#m-t+++H+m

..... ,

::E

N

100 H:;Io"'f+t1itttt-H-+1+1tItt-l+H+ttttI-+1H-t+t1Ift1-t+-Httttti

0.1

1.0

~.OLI.J.O.L...L.llJJ.l0Jl..I...LJ....l.J.llI.UL1.0...l.J...l.J.llI.lllI0'"".U,...L1J.J.lllIOl..O.J..L..LLJ.lIllllOOO·

10

INPUT ImVrmsl

PIN 10 INPUT ImVrmsl

GENERAL DESCRIPTION
trol of hysteresis. Good positive action can be obtained
for IF input signals of above 30 .,.Vrms. The 130 kfl
resistor shown in the test circuit provides a small
amount of hysteresis. Its connection between the 3.3 k
resistor to ground and the 3.0 k pot, permits adjustment
of squelch level without changing the amount of
hysteresis.
The squelch is internally connected to both the quadrature detector and the data shapero The quadrature
detector output, when squelched, goes to a dc level
approximately equal to the zero signal level, unsquelched. The squelch causes the data shaper to produce a high (VCC) output.
The data shaper is.a complete "floating" comparator,
with back to back diodes across its inputs. The output
of the quadrature detector can be fed directly to either
input of this amplifier to produce an output that is either
at VCC or VEE, depending upon the received frequency.
The impedance of the biasing can be varied to produce
an amplifier which "follows" frequency detuning to
some degree, to prevent data pulse width changes.
When the data shaper is driven directly from the demodulator output, Pin 13, there may be distortion at Pin
13 due to the diodes, but this is not important in the
data application. A useful note in relating highllow input
frequency to logic state: low IF frequency corresponds
to low demodulator output. If the oscillator is above the
incoming RF frequency, then high RF frequency will
produce a logic low. (Input to (+ )input of Data Shaper
as shown in figures 1 and 3_)

This device is intended for single and double conversion VHF receiver systems, primarily for FSK data
transmission up to 500 K baud (250 kHz). It contains an
oscillator, mixer, limiting IF, quadrature detector, signal
strength meter drive, and data shaping amplifier.
The oscillator is a common base Colpitts type which
can be crystal controlled, as shown in Figure 1, or L-C
controlled as shown in the other figures. At higher Vce,
it has been operated as high as 200 MHz_ A mixer/
oscillator voltage gain of 2 up to approximately 150
MHz, is readily achievable.
The mixer functions well from an input signal of 10
.,.Vrms, below which the squelch is unpredictable, up
to about 10 mVrms, before any evidence of overload.
Operation up to 1.0 Vrms input is permitted, but nonlinearity of the meter output is incurred, and some oscillator pulling is suspected. The AM rejection above 10
mVrms is degraded.
The limiting IF is a high frequency type, capable of
being operated up to 50 MHz. It is expected to be used
at 10.7 MHz in most cases, due to the availability of
standard ceramic resonators. The quadrature detector
is internally coupled to the IF, and a 5.0 pF quadrature
capacitor is internally provided. The - 3dB limiting sensitivity of the IF itself is approximately 50 .,.V (at Pin 7),
and the IF can accept signals up to 1.0 Vrms without
distortion or change of detector quiescent dc level.
The IF is unusual in that each of the last 5 stages of
the 6 state limiter contains a signal strength sensitive,
current sinking device_ These are parallel connected and
buffered to produce a signal strength meter drive which
is fairly linear for IF input signals of 10.,.V to 100 mVrms.
(See Figure 5.)
A simple squelch arrangement is provided whereby
the meter current flowing through the meter load resistance flips a comparator at about 0_8 Vdc above
ground_ The signal strength at which this occurs can be
adjusted by changing the meter load resistor. The comparator( +) input and output are available to permit con-

APPLICATION NOTES
The MC3356 is a high frequency/high gain receiver
that requires following certain layout techniques in designing a stable circuit configuration. The objective is
to minimize or eliminate, if possible, any unwanted
feedback.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
8-61

MC3356

FIGURE 6 -

APPLICATION WITH FIXED BIAS ON DATA SHAPER

Data Oul
~

Car. Del. Oul
5.0 V

lB k

15 k
RF In
-'-2-1

~
";"

I
I
I

001

I
I
I

~~-r-~J~~~~~19~~~I~B~~1~7~~~-f~~~~~~~~~~17'__'
Data

Compl. I Comp!

Output

Filter

Input

MC33S6

RF

osc

osc

Gnd

EM.

COL

RF

Mixer

Vee

Out

Limiter limiter

Quad
Bias

10

Bead

+5.010 +-12V

B2

APPLICATION NOTES (continued)
Shielding, which includes the placement of input and
output components, is important in minimizing electrostatic or electromagnetic coupling. The MC3356 has its
pin connections such that the circuit designer can place
the critical input and output circuits on opposite ends
of the chip. Shielding is normally required for inductors
in tuned circuits.
The MC3356 has a separate VCC and ground for the
RF and IF sections which allows good external circuit
isolation by minimizing common ground paths.
Note that the circuits of Figures 1 and 3 have RF,
Oscillator, and IF circuits predominantly referenced to
the plus supply rails. Figure 6, on the other hand, shows
a suitable means of ground referencing. The two methods produce identical results when carefully executed.
It is importantto treat Pin 19 as a ground node for either
approach. The RF input should be "grounded" to Pin 1
and then the input and the mixer/oscillator grounds (or
RF VCC bypasses) should be connected by a low inductance path to Pin 19. IF and detector sections should also

have their bypasses returned by a separate path to Pin
19. VCC and RF VCC can be decoupled to minimize feedback, although the configuration of Figure 3 shows a
successful implementation on a common 5.0 V supply.
Once again, the message is: define a supply node and
a ground node and return each section to those nodes
by separate, low impedance paths.
The test circuit of Figure 3 has a 3 db limiting level
of 30 fLV which can be lowered 6 db by a 1:2 untuned
transformer at the input as shown in figures 6 and 7.
For applications that require additional sensitivity, an
RF amplifier can be added, but with no greater than 20
db gain. This will give a 2.0 to 2.5 fLV sensitivity and any
additional gain will reduce receiver dynamic range without improving its sensitivity. Although the test circuit
operates at + 5.0 V, the mixer/oscillator optimum performance is at +8.0 V to 12 V. A minimum of +8.0 V
is recommended in high frequency applications (above
150 MHz), or in PLL applications where the oscillator
drives a prescaler.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
8-62

MC3356
FIGURE 7 Data

APPLICATION WITH SELF·ADJUSTING BIAS ON DATA SHAPER

+5.0 V

Car. Del. Out

Oul
OVor4.0V
130 k
3.3 k

f '" 10.7

150 pF

MC3356

APPLICATION NOTES (continued)
changed to a circuit configuralion as shown in Figure
7. In Figure 7 the reference voltage for the comparator
is derived from the demodulalor outpul through a low
pass circuit where T is much lower than the lowest frequency data rate. This and similar circuits will compensate for small tuning changes (or drift) in the quadrature
detector.

Depending on the external circuit, inverted or non·
inverted data is available at Pin lB. Inverted data makes
the higher frequency in the FSK signal a 'one' when Ihe
local oscillator is above the incoming RF. Figure 6 sche·
matic shows the comparalor wilh hysteresis. In this cir·
cuit the dc reference voltage at Pin 17 is about the same
as the demodulated output voltage (Pin 13) when no
signal is present. This type circuit is preferred for sys·
tems where the data rates can drop to zero. Some sys·
tems have a low frequency limit on the data rate, such
as syslems using the MC3B50 ACIA that has a start or
stop bit. This defines the low frequency limit that can
appear in the data stream. Figure 6 circuit can then be

Squelch status (Pin 15) goes high (squelch off) when
the input signal becomes greater than some preset level
set by the resistance between Pin 14 and ground. Hys·
teresis is added to the circuit externally by the resistance
from Pin 14 to Pin 15.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
8-63

I
RGURE 8 -INTERNAL SCHEMATIC

s::
o

d

~
S;

.....

z

~

~

s:

~
, m

(")

~
m

U'I

(XI

~ ~

()

(')

'"o

~

(')

m

o
»~

fA)
fA)

0)

-

MOTOROLA

SEMICONDUCTOR _ _ _ _ __

MC3357

TECHNICAL DATA

LOW POWER NARROWBAND FM IF
LOW POWER
FM IF

· .. includes Oscillator, Mixer, Limiting Amplifier, Quadrature
Discriminator, Active Filter, Squelch, Scan Control, and Mute
Switch. The MC3357 is designed for use in FM dual conversion
communications equipment.

= 6.0

•

Low Drain Current (3.0 mA (Tvp) @ VCC

•

Excellent Sensitivity: Input Limiting Voltage (-3.0 dB) = 5.0 pV (Typ)

•

Low Number of External Parts Required

SILICON MONOLITHIC
INTEGRATED CIRCUIT

Vdc)

-

16

1

• Recommend MC3372 for Replacement/Upgrade

P SUFFIX

PLASTIC PACKAGE
CASE 648

FIGURE 1 - FUNCTIONAL BLOCK DIAGRAM
D SUFFIX

Vee

PLASTIC PACKAGE
CASE 7516
(SO-16)

PIN CONNECTIONS

Crystal

j

Osc. ~
Mixer

Output

vcc
Limiter
Input
Decoupling

Limiter
Output
Quad
Input

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

8-65

MC3357

MAXIMUM RATINGS

(T A = 25 0e, unless otherwise noted)

Rating

Power Supply Voltage
Operating Supply Voltage Range
Detector I nput Voltage

Pin

Svmbol

Value

Unit

4

Vee(max)

12

Vdc

4

Vee

4 to8

Vdc

8

-

1.0

Vp-p

Input Voltage (Vee;' 6.0 Volts)

16

V16

1.0

VRMS

Mute Function

14

V14

-0.5 to 5.0

VDk

Junction Temperature
Operating Ambient Temperature Range

-

TJ

150

°e

TA

-30 to +70

°e

Storage Temperature Range

-

T sto

-65 to +150

°e

ELECTRICAL CHARACTERISTICS (Vee =6.0 Vdc, 10 = 10.7 MHz, AI = ± 3.0 kHz, Imod = 1.0 kHz, T A = 25°C unless otherwise noted.)
Pin

Characteristic
Drain Current
Squelch Off

Min

TVp

Max

-

2.0
3.0

5.0

Unit
mA

4

Squelch On

-

Input Limiting Voltage
(-3 dB Limiting)

16

-

5.0

10

~V

Detector Output Voltage

9
9

-

3.0

Vdc

-

400

200

350

-

mVrms

Filter Gain (10 kHz)
(V in = 5 mV)

-

40

46

-

dB

Detector Output Impedance
Recovered Audio Output Voltage
(Vin

n

= 10 mV)

Filter Output Voltage

11

1.8

2.0

2.5

Vdc

Trigger Hysteresis

-

-

100

-

mV

Mute Function Low

14

-

15

50

12

Mute Function High

14

1.0

10

-

Mn

Scan Function Low (Mute Off)
(V12 = 2 Vdc)

13

-

0

0.5

Vdc

Scan Function High (Mute On)
(V12 = Gnd)

13

5.0

-

-

Vdc

Mixer Conversion Gain

3

-

dB

16

3.3

16

--

kn

Mixer Input Capacitance

-

20

Mixer I nput Resistance

Vc.c

=

6.0 Vdc

2.2

FIGURE 2 - TEST ClReUIT

Input
10.7 MHz

14

f--------o

13

f--+-""'~--,

. muRata

10 k

CFU
4550

I-~------o Op Amp Output

390k

1.0~F·

1.0 k +

f----o

Filter In

1---"""'-1>--0 Audio

:;J;: 0.01 IlF
rI
I

Lp= 1.0mH
Cpc 'OOpF

Rp= 100kn

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
8-66

Out

pF

MC3357

CIRCUIT DESCRIPTION
The MC3357 is a low power FM IF circuit designed
primarily for use in voice communication scanning
receivers.
The mixer-oscillator combination converts the input
frequency (e.g., 10.7 MHz) down to 455 kHz, where, after
external bandpass filtering, most of the amplification
is done. The audio is recovered using a conventional
quadrature FM detector. The absence of an input signal
is indicated by the presence of noise above the desired
audio frequencies. This "noise band" is monitored by
an active filter and a detector. A squelch trigger circuit
indicates the presence of noise (or a tone) by an output
which can be used to control scanning. At the same
time, an internal switch is operated which can be used
to mute the audio.
The oscillator is an internally-biased Colpitts type with
the collector, base, and emitter connections at Pins 4,
1, and 2 respectively. A crystal can be used in place of
the usual coil.
The mixer is doubly-balanced to reduce spurious responses. The input impedance at Pin 16 is set by a 3.0
kG internal biasing resistor and has low capacitance,
allowing the circuit to be preceded by a crystal filter.
The collector output at Pin 3 must be dc connected to
B +, below which it can swing 0.5 V.
After suitable bandpass filtering (ceramic or LC) the
signal goes to the input of a five-stage limiter at Pin 5.
The output of the limiter at Pin 7 drives a multiplier,

both internally directly, and externally through a quadrature coil, to detect the FM. The output at Pin 7 is also
used to supply dc feedback to Pin 5. The other side of
the first limiter stage is decoupled at Pin 6.
The recovered audio is partially filtered, then buffered
giving an impedance of around 400 G at Pin 9. The
signal still requires de-emphasis, volume control and
further amplification before driving a loudspeaker.
A simple inverting op amp is provided with an output
at Pin 11 providing dc bias (externally) to the input at
Pin 10 which is referred internally to 2.0 V. A filter can
be made with external impedance elements to discriminate between frequencies. With an external AM detector the filtered audio signal can be checked for the presence of noise above the normal audio band, or a tone
signal. This information is applied to Pin 12.
An external positive bias to Pin 12 sets up the squelch
trigger circuit such that Pin 13 is low at an impedance
level of around 60 kG, and the audio mute (Pin 14) is
open circuit. If Pin 12 is pulled down to 0.7 V by the
noise or tone detector, Pin 13 will rise to approximately
0.5 Vdc below supply where it can support a load current
of around 500 pA and Pin 14 is internally short-circuited
to ground. There is 100 mV of hysteresis at Pin 12 to
prevent jitter. Audio muting is accomplished by connecting Pin 14 to a high-impedance ground-reference
point in the audio path between Pin 9 and the audio
amplifier.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
8-67

FIGURE 3 -CIRCUIT SCHEMATIC

3

4

~
10k

5k

s:
o

~

d

~
r
Z
~

3.0 k

t....

Vg

,

&l

11~

2O

~

V,6

'"

20k

17

30 k

100 k

30 k

~
m

30 k

5.0 k

)l;!
om

§
!;g

o
m
o
»~

:.t

10k

~

i-i

S
n
w

50 k

15

4~
10 k

10 k

10 k

10 •

10k

10 •

10 •

10 •

35

36

37~40

41

",53

~

'1

~~l

10'
44

~7-

-ii2

~3
42

4~

J6

50 •

6.2 •

33 •

6

33 k

33 •

33 •

10 •

10
k

120 •

l
urr

56

50 k

J4

100.:;

.....

60

9

~~

100 k

C2

57r

'-I

7

'-.I

58~

w

U'I

?8

30~r

31~'

22 k

470

29 ,.

5

12

50 k

Cl

28
10 Ok

~4
14

G=-d,

o

10k

15 k

220 k

~9

r

k8

15 k

:II

13

-----t:::

J
1~

~5

15 k

~

)- rK:kJ

t....

:II

20 k

L

V
1

30k

10 k

59

MOTOROLA

-

Me33S9

SEMICONDUCTOR

TECHNICAL DATA

HIGH GAIN
LOW POWER

FMIF

LOW POWER NARROWBAND FM IF
· .. includes oscillator, mixer, limiting amplifier, AFC, quadrature
discriminator, op/amp, squelch, scan control, and mute switch.
The MC3359 is designed to detect narrowband FM signals using
a 455 kHz ceramic filter for use in FM dual conversion communications equipment. The MC3359 is similar to the MC3357 except
that the MC3359 has an additional limiting IF stage, an AFC output,
and an opposite polarity Broadcast Detector. The MC3359 also
requires fewer external parts. For low cost applications requiring
VCC below 6.0 V, the MC3361 BP,BD are recommended. For applications requiring a fixed, tuned, ceramic quadrature resonator,
use the MC3357. For applications requiring dual conversion and
RSSI, refer to these devices; MC3335, MC3362 and MC3363.
• Low Drain Current: 3.6 mA (Typ)

«/. VCC

=

SILICON MONOLITHIC
INTEGRATED CIRCUIT

P SUFFIX
PLASTIC PACKAGE
CASE 707

DW SUFFIX
PLASTIC PACKAGE
CASE 7510

ISO-20l)

6.0 Vdc

• Excellent Sensitivity: Input Limiting Voltage - 3.0 dB = 2.0 pV (Typ)

20.
,

FIGURE 2 - PIN CONNECTIONS AND
FUNCTIONAL BLOCK DIAGRAM

• Low Number of External Parts Required
• For Low Voltage and RSSI, use the Me3371

crvstal.{
0"

I
2

Limiter

Input

FIGURE 1 - TYPICAL APPLICATION IN A SCANNER RECEIVER

Oecouplmg

6

Decouplmg

7r+:'Y"'~--'

Quadrature

11 Demod

Inpul

Output

to

Demodulator
Filter

Vee = 6.01lde

O.IIo'F

10.7 MHz
Input

CASE 707

Vee ~ 6.0 Vde

NC-

•

i-

2

51k

15

Crystal

Scan Control

1

Osc. ~

MC3359

13

Output

12

,. ---:

I Quad I

L_~o.!!_J
Toka
Type

10

1\

7MC.8128Z,:,

4

17

r~~~~O

VCC- 5

16

r- ~~~7ro'

'5

r- ~~Uu~ICh

Decoupling -

7

14 :-

Decoupling -

B

13

r

12

rg~~~~

u~~~~_

IN4148

18k
Recovered Audio

r--"'==="'-.....~7".5...k ---r--il---,

Quadrature
Input

100 pF

Demodulator
Filter

10

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

~~~;ut
r~~~~

11 r :~~~~ered

CASE 7510

8-69

RF
Input

19

6

-SquelCh

Sensitivity

(Filter)
Input

I

o~:~~~-

I~471-'F _~
-

Inverting
Op Amp

20 rNC

18 rGnd

r,,~~Sq~"'~I'~h~I"P~"~I________~__~~~350k
120 k

Recovered
AudiO

MC3359
MAXIMUM RATINGS (TA

= 25°e,

unless otherwise noted)

Pin

Symbol

Value

Unit

Power Supply Voltage

4

Veel max )

12

Vdc

Operating Supply Voltage Range

4

Vee

6 to 9

Vdc

Input Voltage (Vee'" 6.0 Volts)

18

V18

1.0

Vrms

Mute Function

16

V16

-0.7 to 12

Vpk

Junction Temperature

-

TJ

150

°e

TA

-30 to +70

°e

Tsto

-65 to + 150

°e

Rating

Operating Ambient Temperature Range
Storage Temperature Range

ELECTRICAL CHARACTERISTICS (Vee = 6.0 Vdc, 10 = 10.7 MHz, M = ±3.0 kHz, Imod = 1.0 kHz, 50!1 source,
TA = 25°C test circuit 01 Figure 3 unless otherwise noted)

Characteristics
Drain Current (Pins 4 and 8)

Squelch Off
Squelch On

Min

Typ

Max

Units

-

3.6
5.4

6.0
7.0

mA

-

46

-

Mixer Third Order Intercept, 50 !1 Input

-

-1.0

Mixer Input Resistance

-

3.6

Mixer Input Capacitance

-

2.2

Recovered Audio, Pin 10
(Input Signal 1.0 mVrms)

450

700

-

mVrms

Detector Center Frequency Slope, Pin 10

-

0.3

-

VlkHz

AFe eenter Slope, Pin 11, Unloaded

12

-

VlkHz

Filter Gain Itest circuit 01 Figure 3)

40

51

Squelch Threshold, Through 10K to Pin 14

-

0.62

-

Vdc

-

0.01
2.4

Input lor 20 dB Quieting
Input lor -3.0 dB Limiting
Mixer Voltage Gain (Pin 18 to Pin 3, Open)

Scan Control Current, Pin 15

Pin 14 - High
-Low

Mute Switch Impedance
Pin 16 to Ground

Pin 14 - High
-Low

FIGURE 3 -

2.0

-

8.0

-

/-LVrms

2.0

-

jJVrms

1.0

-

5.0
1.5

10

-

TEST CIRCUIT
0.1 ~F

Ceramic
Filter

Input
10.7 MHz

2.4 k

16

muRata
CFU455D

15

0'

Kyocera
KBF455P-20A

Audio Gen.
0.7 Vp-p

~
Squelch Input

"

10 k

13

Op Amp Output

1.0 M

12
1.0

~

Op Amp Input

~F

AFC Output

11

10
75 k -

f

Audio Output

0.0:' "F

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

8-70

dBm
k!1
pF

dB

J"A
mA
!1
M!1

MC3359
FIGURE 4 -

MIXER VOLTAGE GAIN

FIGURE 5 -

LIMITING I.F. FREQUENCY RESPONSE

40 0
10.7 MHz
INPUT /0
OUTPUT /0 ~ 455 kHz
OUTPUT TAKEN AT
PIN 3 WITH FILTER
REMOVED IOPEN}

10 0

§

§

100

Vee - 9.0V lA11l111

V

/

H1i1ill

6.0V= t=

Vee

II

-10

R~SpJN~E ~AU~ ~N

\--- TERMINALS NOT
AVAILABLE ON
STANDARD DEVICE.

0

/ )/

0

iF IINiUITI

6. 0
4.0
0.1

1.0
INPUT, 50 n ImVrms}

10

FIGURE 6 - MIXER THIRD ORDER
INTERMODULATION PERFORMANCE

1 J

; -20

...,

/

DESIRED PRODUCTS//"

~ -30

£

0 _ 40

/

/
-80

-70

-60

-50 -40 -30
INPUT, 50 U}dBml

FIGURE 8 -

/

-20

;;
~

I

~

0.1

-

-10

RELATIVE MIXER GAIN

VDETECTOR OUTPUT PIN 10

V

-8

-6

-4
-2
2.0
RELATIVE FREQUENCY 1kHz}

S+N

10

.1~r~F(

25'e I
- - - 75'e _

:= -20

o=>

~

8.0

llllllllllllill

F'l

'::;

DERIVED USING
OPTIMUM UC
OSCILLATOR VALUES
AND HOLDING
IF FREOUENCY AT
455 kHz

6.0

4.0

OVERALL GAIN, NOISE, AND A.M. REJECTION

10

~-10

.....-

/

FIGURE 9 -

Vec

-30

~

6.0 Vdc

S+ ~ I I :jri!~IA~}1

~ -40

N

-so

-50
-60

/"

o

10

_

/

1.0

-1 0

-40 - -

~

4.0

0

-3 o~

AF~ OUTP~T PIN 111

V

2.0

-10

6.0 Vdc

63.0

0

~ -20

~

u 5.0

lRDIORDER 1M PRODUCTS

/

-50
-60
-90

1/

100

DETECTOR AND AFC RESPONSES

6.0

il

//

VCC

7.0

L/j

r---

10

8.0

/

OUTPUTTAKEN AT
PIN 3 WITH FILTER
REMOVED
E
Vec ~ 6.0 Vdc
~ -10 i----

/

-till

1.0
FREQUENCY IMHz}

FIGURE 7 -

20
10

1 11111

100,)

-70
0.1

40

¥'

WR - 3i BLlIMIU

-60

0.04

V

HIIIII

/

0

~

\

\--- A SPECIAL PROTOTYPE.

0

~

r-..

IF OUTPUT

IIIIII

1.0

10

-60
0.001

100

FREQUENCY 1M Hz}

I
0.01

0.1
1.0
INPUT ImVrms}

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
8-71

10

100

MC3359
FIGURE 10 - OUTPUT COMPONENTS OF
SIGNAL. NOISE, AND DISTORTION

+1 0

FIGURE 11 - AUDIO OUTPUT AND TOTAL
CURRENT DRAIN versus SUPPLY VOLTAGE

B.O

,

Isll~I~ID I

1111111

II

,

111111 I I . ~.I I
iii

= 10.7 MHz
fm = 1 kHz
!J.f = ±3.0kHz

-10

~ -20

~

~

~

t
z

TEST CIRCUIT Of
fiGURE 3.

~

u
~

-40

~

W

3.0

om

Ie'

10

0.1

1.0
INPUT ImVrms

4.0

"'r-...

10.700

>-

~ 10.698

~

"-.........

10.694

PHASE

r-....'" ~CC
TEMP
f"'" ~

10.692

FIGURE 14 -

60

40
50
AMBIENT TEMPERATURE lOCI

500

~

..... k--

I
O.8

'J

1.0

~
5

0.7
0.5 ~

" r.......

0.3
0.2
0.1

7.0

10

20
lO
OSCILLATOR fREOUENCY IMHzI

50

70

AND PHASE (SOLID LINES)

100

GIVENfo
Alto'

I--if 0.61-~
.... I-5 0.4
o

'"

I

lO

100 K
fREQUENCY IHzI

11

I I I II

CENTER fREQUENCY
GAINATCENTERFREDUENCY

RJ'"

I

I

10M

I

V,n

I I I

OOO,~\~

::~~ ,:~ lo"~'

TT

_

13

+

V'o'
_

"

Rl=~

R1R3
R2=~

\

\
2.0

5.0

::-.,

10
20
fREOUENCY IkHzI

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

8-72

1.0M

,F "
150 V'ef

-----L.
f~ Cl

.2

0
1.0

60

THE OP AMP AS A BANDPASS FILTER

I
=
=

90~

r:::'

J

.0

2.0 ~

~

0

5.0

FOR OPEN lOOP GAIN

~

o
1-[lllilll
10 K
1.0K

1
7.0
5.0
4.0
3.0

1

.

USE CIRCUIT ABOVE

I

Of FIGURE 3

or- Vcc~ '6.0rVd~'

FIGURE 15 -

C4

C5

~

180

Il

Vref

~

~~

ot-- WITH CIRCUIT VALUES

70

.~

L
C5 .........

GAIN

~

12

oomo CURVES WKEN

UC OSCILLATOR RECOMMENDED
COMPONENT VALUES

1000
700

9.0

8.0

0-:0

ill

0

""- ~

lO

o

OP AMP GAIN AND PHASE RESPONSE

,::s

50

10.696

I-

6.0
7.0
Vce. SUPPLY VOLTAGE IVde)

0

-t-- r-.

20

5.0

0

10.702

10

o

5

::>

62

~

10.704

:=::>

0.1

FIGURE 13 -

Vee. SUPPLY VOLTAGE IVdel
59
60
61

!:i

0.2 ..

o

III!

58

10.706

lOO

0.4

~

~

O.lo

2.0

FIGURE 12 - UC OSCILLATOR, TEMPERATURE
AND POWER SUPPLY SENSITIVITY

10.690

0.5

1.0

0.001

fE

---+--tICC. MUTE OFF

0.7
0.6

-- -

~.MLrEO~

~ 4.0

N+D

-60

~

::::r-

5.0

::>

-30

-50

1

~

AUDld OUTP0T

u 6.0
~

fo

"'....

0.B

7.0

50

100

,W

r----------------------------------r---------,----------I
3?!_ '~? _ _ ~3?i ?"
4
Q77

HS7k

Q1

h.,

1.8 i<

Q2

15'

Q3

Q4

s::

@

18

Q~

JJ

o

>

,J

"I.

L. I a"

...

~

r

Z
m

»

3,.

~3
Q12
Q13

3Jk~ 33 k

3.5 k

~

CX>

~

cj ~
~

15 k

062 1

7k

50 k S 2 5 k

OSCILLATOR -

MIXER

750 II

so,

s:

I

I
:

OP AMP

n
Co)

IBROADCAST DETECTOR

~--------------------------------~----------~---------I
I

LIMITING IF AMPLIFIER

()

m

~
'7

6Ch
o

m

<
6
m
o
»~

061h

Q14
33 k ~ 33 k

Co)

C1I

DETECTOR AND AFC

CD

~

Q22
~.~--~.~.~--~,~~.---.-.,-.,----~.~,~--~~

018
100 k I 10 k

Q19

~
17

L _________________________________
6
I _____________________
~

FIGURE 16 -

CIRCUIT SCHEMATIC

~

MC3359
CIRCUIT DESCRIPTION

has an internal 1.8 k resistor. The IF has a 3 dB limiting sen~
sitivity of approximately 100 /LV at Pin 5 and a useful frequency
range of about 5 MHz as shown in Figure 5. The frequency
limitation is due to the high resistance values in the IF, which
were necessary to meet the low power requirement. The out~
put of the limiter is internally connected to the quadrature detector, including the 10 pF quadrature capacitor. Only a parallel
lIC is needed externally from Pin 8 to Vce. A shunt resistance
can be added to widen the peak separation of the quadrature
detector.
The detector output is amplified and buffered to the audio
output, Pin 10, which has an output impedance of approximatley 300 n. Pin 9 provides a high impedance (50 k) point in
the output amplifier for application of a filter or de-emphasis
capacitor. Pin 11 is the AFC output, with high gain and high
output impedance (1 M). If not needed, it should be grounded,
or it can be connected to Pin 9 to double the recovered audio.
The detector and AFC responses are shown in Figure 7.
Overall performance of the MC3359 from mixer input to audio output is shown in Figure 9 and 10. The MC3359 can also
be operated in "single conversion" equipment; i.e., the mixer
can be used as a 455 kHz amplifier. The oscillator is disabled
by connecting Pin 1 to Pin 2. In this mode the overall performance is identical to the 10.7 MHz results of Figure 9.
A simple inverting op amp is provided with an output at Pin
13 providing dc bias (externally) to the input at Pin 12, which
is referred internally to 2.0 V. A filter can be made with external
impedance elements to discriminate between frequencies.
With an external AM detector, the filtered audio signal can be
checked for the presence of either noise above the normal
audio, or a tone signal.
The open loop response of this op amp is given in Figure
13. Bandpass filter design information is provided in Figure 15.
A low bias to Pin 14 sets up the squelch-trigger circuit such
that Pin 15 is high, a source of at least 2.0 mA. and the audio
mute (Pin 16) is open-circuit. If Pin 14 is raised to 0.7 V by the
noise or tone detector, Pin 15 becomes open circuit and Pin
16 is internally short circuited to ground. There is no hysteresis.
Audio muting is accomplished by connecting Pin 16 to a highimpedance ground-reference point in the audio path between
Pin 10 and the audio amplifier. No dc voltage is needed, in fact
it is not desirable because audio "thump" would result during
the muting function. Signal swing greater than 0.7 V below
ground on Pin 16 should be avoided.

The MC3359 is a low-power FM IF circuit designed primarily
for use in voice-communicatiop scanning receivers. It is also
finding a place in narrowband data links.
In the typical application (Figure 1), the mixer-oscillator combination converts the input frequency (10.7 MHz) down to 455
kHz, where, after external bandpass filtering, most of the amplification is done. The audio is recovered using a conventional
quadrature FM detector. The absence of an input signal is indicated by the presence of noise above the desired audio frequencies. This "noise band" is monitored by an active filter
and a detector. A squelch-trigger circuit indicates the presence
of noise (or a tone) by an output which can be used to control
scanning. At the same time, an internal switch is operated
which can be used to mute the audio.

APPLICATION
The oscillator is an internally biased Colpitts type with the
collector, base, and emitter connections at Pin 4, 1, and 2, re~
spectively. The crystal is used in fundamental mode, calibrated
for parallel resonance at 32 pF load capacitance. In theory this
means that the two capacitors in series should be 32 pF, but
in fact much larger values do not significantly affect the os~
cillator frequency, and provide higher oscillator output.
The oscillator can also be used in the conventional lie eol~
pitts configuration without loss of mixer conversion gain. This
oscillator is, of course, much more sensitive to voltage and
temperature as shown in Figure 12. Guidelines for choosing L
and e values are given in Figure 14.
The mixer is doubly balanced to reduce spurious responses.
The mixer measurements of Figure 4 and 6 were made using
an external 50 n source and the internal 1.8 k at Pin 3. Voltage
gain curves at several Vce voltages are shown in Figure 4. The
Third Order Intercept curves of Figure 6 are shown using the
conventional dBm scales. Measured power gain (with the 50
n input) is approximately 18 dB but the useful gain is much
higher because the mixer input impedance is over 3 kil. Most
applications will use a 330 n 10.7 MHz crystal filter ahead of
the mixer. For higher frequencies, the relative mixer gain is
given in Figure 8.
Following the mixer, a ceramic bandpass filter is recom~
mended. The 455 kHz types come in bandwidths from", 2 kHz
to ± 15 kHz and have input and output impedances of 1.5 k to
2.0 k. For this reason, the Pin 5 input to the 6 stage limiting IF

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

8-74

MOTOROLA

-

MC3361B

SEMICONDUCTOR - - - - - -

TECHNICAL DATA

Advance Information
LOW POWER

FM IF

LOW POWER NARROWBAND FM IF

SILICON MONOLITHIC
INTEGRATED CIRCUIT

The MC3361B includes an Oscillator, Mixer, Limiting Amplifier,
Quadrature Discriminator, Active Filter, Squelch, Scan Control,
and Mute Switch. This device is designed for use in FM dual
conversion communications equipment.
• Operates From 2.0 V to 8.0 V Supply
• Low Drain Current 3.9 rnA Typ @.o VCC = 4.0 Vdc
• Excellent Sensitivity: Input Limiting Voltage -3.0 dB = 2.6 p.V Typ
• Low Number of External Parts Required
• Operating Frequency Up to 60 MHz

P SUFFIX
PLASTIC PACKAGE
CASE 648

DSUFFIX
PLASTIC PACKAGE
CASE 7518
(50-161

FIGURE 1 Mixer
Input

Gnd

FUNCTIONAL BLOCK DIAGRAM

PIN CONNECTIONS

Scan Squelch Filter Filter Recovered
In·
Output Input Audio
Mute Control

crvstall
Osc.
Mixer Output

3

11 Filter Output

9 Demodulator

Output

Crystal
Osc

Oecoupling

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

8-75

MC3361B
MAXIMUM RATINGS (TA = 25°C unless otherwise noted)
Pin

Symbol

Value

Unit

Power Supply Voltage

4

Vee(max)

10

Vdc

Operating Supply Voltage Range

4

Vee

2.0 to 8.0

Vdc

Detector Input Voltage

8

-

1.0

Vp-p

Input Voltage (Vee'" 4.0 Volts)

16

V16

1.0

VRMS

Mute Function

14

V14

-0.5to +5.0

Vok

Junction Temperature

TJ

150

°e

Operating Ambient Temperature Range

-

TA

-30to +70

°e

Storage Temperature Range

-

Tstg

-65to +150

Rating

ELECTRICAL CHARACTERISTICS (Vee = 4.0 Vdc, 10 = 10.7 MHz, M
unless otherwise noted.)

=

°e
±3.0 kHz, Imod
Pin

Characteristic
Drain Current (No Signal)

=

1.0 kHz, TA

= 25°C,

Min

Typ

Max

2.9
4.4

3.9
5.4

4.9
6.4

4
Squelch Off
Squelch On

Recovered Audio Output Voltage (Vin

=

10 mVRMS)

Unit
mA

9

130

160

200

mVRMS

Input Limiting Voltage (-3.0 dB Limiting)

16

-

2.6

6.0

fLV

Total Harmonic Distortion

9

-

0.86

-

Recovered ·Output Voltage (No Input Signal)

9

60

120

250

9

-3.0

-0.6

Drop Voltage AF Gain Loss

-

dB

50

-

dB

1.0

1.3

1.6

Vdc

-

30

50

II

1.0

11

-

Mil

-

40

Filter Output Voltage

11

Mute Function Low

14

Mute Function High

14

Detector Output Impedance
Filter Gain (10 kHz) (Vin

= 0.3 mVRMS)

= 1.0 Vdc)
= Gnd)

%

mVRMS

450

II

13

-

0

0.4

Vdc

13

3.0

3.5

Vdc

Trigger Hysteresis

-

-

-

45

100

mV

Mixer Conversion Gain

3

-

28

-

dB

Mixer Input Resistance

16

3.3

-

kll

Mixer Input Capacitance

16

-

2.2

-

pF

Scan Function Low (Mute Off) (V12
Scan Function High (Mute On) (V12

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

8-76

MC33618
FIGURE 2 - TEST CIRCUIT

0.01
1--_-l~--....----__oMixer Input
10.7 MHz

10.245 MHz
VCC o-..----l

0I--..---l

1 - - - - - - - - - - - - - 0 Audio Mute

muRata
CFU455D2

1 - - - - - - - - -....- - 0 Scan

Control

10 k

=

0.1

1-----<1.......- - 1 1 - - - - - - 0 Filter Amp Out
0.1

1-----~ 150

,..-

250 C

-

Audio Output

-

8.0

240

7.0_

220

it.
6.0~

~

5.0~

is

: :I

i5

~14O

Q

:::>

""130

2.0

Distortion

120

1.0

g

-

-Vcc

!

200



1-

~

b::::::::: f----

1.0

J
II
-70 -60 -50 -40
RF INPUT IdBml

........

FIGURE 9 - DETECTOR OUTPUT versus FREQUENCY

.-1

V

10 k

4.0

v'-"

-20
~

I 13 10 k

S+N30%AM

.........

001+0£=9 001
-7 0
-80
-130 -120 -110 -100 -90 -80 -70
RF INPUT IdBml

.-

I

0

~

'" -5 0 MC3362
-60

~V

....--::;:V

0

8.0

-

I~

-40

FIGURE 8 - 1ST MIXER 3RD ORDER INTERMODULATION

-1 0

7.0

~

~ -30

~ ~RF Input to Transformer

90
80 -70
RF INPUT IdBml

o

S+N

-1 O~

j...--

Second Mixer Output I'-.
First Mixer Output ~

a:

6.0

5.0

0

-20

300

Recovered Audio -

FIGURE 7 - S + N, N, AMR versus INPUT

FIGURE 6 - SIGNAL LEVELS

-1 0

500

~- ~ 400

VCC IVI

0

0

~

600

100

RF INPUT IdBml

E

P-,

-

1/

1.0

3.0

IRFlin~l~

rlcc, Carr. Det.IHigh

700

= 10 ~V!..:::,.

o

-10

-40

-30

-20

-10

10

20

RELATIVE INPUT FREQUENCY IkHzl

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

8-84

30

40

!.s..,
:>

MC3362
FIGURE 10 - PC BOARD TEST CIRCUIT
(LC Oscillator Configuration Used in PLL Synthesized Receiver)

RF Input
49.67
50

n

VCC

18 p

1000 P

MHZ~p:

-:r:

•

-=

Varactor Control

10.47 p.

1-..---< (keep 0.7 V '" V23 '" VCC)

= 2.0 to 7.0 Vdc -=

(This network must be tuned to exactly
10.7 MHz above or below the incoming
RF signal. NOTE: The IF is rolled off
above 10.7 MHz to reduce L.a. feedthrough.)
I-~_"" First Local Oscillator

to VCC

CRFl = muRata CFU 455X - the X
suffix denotes 6.0 dB bandwidth.
Rin = Rout = 1.5 to 2.0 kn.
CRF2 = muRata SFA10.7 MF5 or
SFE10.7 or equivalent. Rin = Rout
= 330 n. Crystal filters can be
used but impedance matching will
need to be added to ensure proper

0.1
0.1

filter characteristics are realized.

Carrier
Detect

-+-------'

455 kHz

r
I

LC Resonator ~ _ _ _ _ -'~

FIGURE lOA - CRYSTAL OSCILLATOR CONFIGURATION FOR SINGLE CHANNEL APPLICATION

Crystal used is series mode resonant

(no load capacity specified). 3rd overtone.
This method has not proven adequate for
fundamental mode, 5th or 7th overtone crystals.
The inductor and capaCitor will need to be
changed for other frequency crystals. See
AN980 for further information.

20.k

300

VCC

20 k
I

38.97 MHz

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

8-85

MC3362
FIGURE 11 - COMPONENT PLACEMENT VIEW
SHOWING CRYSTAL OSCILLATOR CIRCUIT

FIGURE 11A - LC OSCILLATOR COMPONENT VIEW

NOTES:
1. Recovered Audio components may be deleted when using data

5. Meter Drive cannot be used simultaneously with Carrier Detect out·
put. For analog meter drive, remove components labelled "2" and
measure meter current (4-12/LA) through ammeter to VCC'
6. Either type of oscillator circuit may be used with any output circuit
configuration.
7. LC Oscillator Coil: Coilcraft UNI 10/42 10.5 turns, 0.41 ~H Crystal
Oscillator circuit: trim coil, 0.68 J.lH. Coilcraft M1287-A.
8. 0.47 H, Coilcraft M1286-A.lnput LC network used to match first
mixer input impedance to 50 n.

output.
2. Carrier Detect components must be deleted in order to obtain linear
Meter Drive output. With these components in place the Meter Drive
outputs serve only to trip the Carrier Detect indicator.
3. Data Output components should be deleted in applications where
only audio modulation is used. For combined audio/data applica-

tions, the 0.047 ,uF coupling capacitor will add distortion to the audio,
so a pull-down resistor at pin 13 may be required.
4. Use Toka 7MC81282 Quadrature coil.

CIRCUIT DESCRIPTION
The MC3362 is a complete FM narrowband receiver
from antenna input to audio preamp output. The low
voltage dual conversion desigr{ yields low power drain,
excellent sensitivity and good image rejection in narrowband voice and data link applications.
In the typical application (Figure 1), the first mixer
amplifies the signal and converts the RF input to 10.7
MHz. This IF signal is filtered externally and fed into the
second mixer, which further amplifies the signal and
converts it to a 455 kHz IF signal. After external bandpass filtering, the low IF is fed into the limiting amplifier
and detection circuitry. The audio is recovered using a
conventional quadrature detector. Twice-IF filtering is
provided internally.
The input signal level is monitored by meter drive
circuitry which detects the amount of limiting in the
limiting amplifier. The voltage at the meter drive pin
determines the state of the carrier detect output, which
is active low.

APPLICATION
The first local oscillator can be run using a freerunning LC tank, as a VCO using PLL synthesis, or
driven from an external crystal oscillator. It has been
run to 190 MHz." A buffered output is available at Pin
20. The second local oscillator is a common base Colpitts type which is typically run at 10.245 MHz under
crystal control. A buffered output is available at Pin
2. Pins 2 and 3 are interchangeable.
The mixers are doubly balanced to reduce spurious
responses. The first and second mixers have conversion gains of 18 dB and 22 dB (typical), respectively,
as seen in Figure 6. Mixer gain is stable with respect
to supply voltage. For both conversions, the mixer
impedances and pin layout are designed to allow the
user to employ low cost, readily available ceramic filters. Overall sensitivity and AM rejection are shown
in Figure 7. The input level for 20 dB (S+N)/N is 0.7
,.,.V using the two-pole post-detection filter pictured.
*If the first local oscillator (Pins 21 and/or 22) is driven from a
strong external source (100 mVrms), the mixer can be used
to over 450 MHz.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
8-86

MC3362
crossings of FSK modulation. Data rates are typically
limited to 1200 baud to ensure data integrity and avoid
adjacent channel "splatter." Hysteresis is available by
connecting a high valued resistor from Pin 15 to Pin
14. Values below 120 k!1 are not recommended as the
input signal cannot overcome the hysteresis.
The meter drive circuitry detects input signal level
by monitoring the limiting amplifier stages. Figure 4
shows the unloaded current at Pin 10 versus input
power. The meter drive current can be used directly
IRSSl) or can be used to trip the carrier detect circuit
at a specified input power. To do this, pick an RF trip
level in dBm. Read the corresponding current from
Figure 4 and pick a resistor such that:

Following the first mixer, a 10.7 MHz ceramic bandpass filter is recommended. The 10.7 MHz filtered signal is then fed into one second mixer input pin, the
other input pin being connected to Vee. Pin 6 IVee)
is treated as a common point for emitter-driven
signals.
The 455 kHz IF is typically filtered using a ceramic
bandpass filter then fed into the limiter input pin. The
limiter has 10 /-LV sensitivity for -3.0 dB limiting, flat
to 1.0 MHz.
The output of the limiter is internally connected to
the quadrature detector, including a quadrature
capacitor. A parallel Le tank is needed externally from
Pin 12 to Vee. A 39 kn shunt resistance is included
which determines the peak separation of the quadrature detector; a smaller value will increase tile spacing and linearity but decrease recovered audio and
sensitivity.
A data shaping circuit is available and can be coupled to the recovered audio output of Pin 13. The circuit is a comparator which is designed to detect zero

FIGURE 12 -

RlO = 0.64 Vdc 1110
Hysteresis is available by connecting a high valued
resistor RH between Pins 10 and 11. The formula is:
Hysteresis

=

Vee/lRH x 10 - 7) dB

CIRCUIT SIDE VIEW

-----4"------.1-1

1.
+
.
-1

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

8-87

FIGURE 13 -

23

~

CIRCUIT SCHEMATIC

t
~5

s::

o

o
:D

o
~

II $

,,-+

c
z
m
OJ

0,
OJ

~
~
m

:D

~
()

m

~

'"]J) I'W. .U ! ~ I I

""

,

mIT"

o

!;2
C'i
o
»~

""Al

m

14

13

~

e

$

~

+

I

$$$

~

bias

~

$ $

$

Q

Y

16

i

VEE

3:

n
Co)

Co)

en

N

MOTOROLA

-

MC3363

SEMICONDUCTOR - - - - - -

TECHNICAL DATA

LOW POWER
DUAL CONVERSION
FM RECEIVER

LOW POWER DUAL CONVERSION FM RECEIVER
The MC3363 is a single chip narrowband VHF FM radio receiver.
It is a dual conversion receiver with RF amplifier transistor, oscillators, mixers, quadrature detector, meter drive/carrier detect and
mute circuitry. The MC3363 also has a buffered first local oscillator
output for use with frequency synthesizers, and a data slicing
comparator for FSK detection.

SILICON MONOLITHIC
INTEGRATED CIRCUIT

• Wide Input Bandwidth - 200 MHz Using Internal Local Oscillator
- 450 MHz Using External Local Oscillator
• RF Amplifier Transistor
• Muting Operational Amplifier
• Complete Dual Conversion
• Low Voltage: VCC

= 2.0 V to 6.0 Vdc

• Low Drain Current: ICC = 3.6 mA (Typ) at VCC = 3.0 V,
Excluding RF Amplifier Transistor
• Excellent Sensitivity: Input 0.3 p.V (Typ) for 12 dB SINAD
Using Internal RF Amplifier Transistor
DWSUFFIX
PLASTIC PACKAGE
CASE 751F
(SO-28LI

• Data Shaping Comparator
• Received Signal Strength Indicator (RSSI) with 60 dB
Dynamic Range
• Low Number of External Parts Required
• Manufactured in Motorola's MOSAIC Process Technology

FIGURE 1 -

PIN CONNECTIONS AND FUNCTIONAL
BLOCK DIAGRAM

1st Mixer Input 1

Emitter

3

Collector

4

28

1st Mixer Input

27

Varicap Control

1st LO Tank
1st LO Output

2nd LO Emitter 5
2nd LO Base

6

1st Mixer Output

2nd Mixer Output

7

2nd Mixer Input
21

Limiter Input

VEE

9

Mute Dutput

Limiter Decoupling
Limiter Decoupling

2nd Mixer Input

18

11

Comparator Output

17 Comparator Input

Meter Drive (RSSII 12

Recovered Audio

Carrier Detect
Quadrature Coil

15

Mute .Input

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

8-89

MC3363

MAXIMUM RATINGS (TA ~ 25'C unless otherwise noted)
Pin

Symbol

Value

Unit

Power Supply Voltage

8

VCC(max)

7.0

Vdc

Operating Supply Voltage Range
(Recommended)

8

VCC

2.0 to 6.0

Vdc

Rating

=

1,28

V1-28

1.0

Vrms

Mute Output Voltage

19

V19

-0.7 to 8.0

Vpk

Junction Temperature

TJ

150

'c

Operating Ambient Temperature Range

-

TA

-40 to +85

'C

Storage Temperature Range

-

Tsto

-65 to +150

'c

Input Voltage (VCC

5.0 Vdc)

ELECTRICAL CHARACTERISTICS (VCC ~ 5.0 Vdc, fa ~ 49.7 MHz, Deviation ~ 003.0 kHz, TA = 25'C, Mod 1.0 kHz,
test circuit of Figure 2 unless otherwise noted)
Pin

Min

Typ

Max

8

-

4.5

8.0

mA

-

0.7

2.0

~Vrms

Input For 12 dB SINAD

-

0.3

-

20 dB SIN Sensitivity (RF Amplifier Not Used)

1.0

1,28

-

690

-

Q

1,28

-

7.2

-

pF
dB

Characteristic

Drain Current (Carrier Detect Low)
-3.0 dB Limiting Sensitivity (RF Amplifier Not Used)

1st Mister Input Resistance (Parallel -

Rp)

1st Mixer Input Capacitance (Parallel- Cp)
1st Mixer Conversion Voltage Gain (Ave 1, Open Circuit)

-

18

2nd Mixer Conversion Voltage Gain )Avc 2, Open Circuit)

-

21

2nd Mixer Input Sensitivity (20 dB SIN) (10.7 MHz i/p)

21

-

10

-

Limiter Input Sensitivity (20 dB SIN) (455 kHz i/p)

9

-

100

-

Units

~Vrms

RF Transistor DC Current Drain

4

1.0

1.5

2.5

mAdc

Noise Output Level (RF Signal = 0 mV)

16

-

70

mVrms

Q

Recovered Audio (RF Signal Level = 1.0 mV)

16

120

200

THO of Recovered Aduio (RF Signal = 1.0 mV)

16

2%

Detector Output Impedance

16

400

-

Series Equivalent Input Impedence

1

-

-

450j350

-

Data (Comparator) Output Voltage -

High
Low

18

-

-

0.1

0.1

VCC

-

mVrms

%

Vdc

Data (Comparator) Threshold Voltage Difference

17

70

110

150

mV

Meter Drive Slope

12

70

100

135

nNdB

Carrier Detect Threshold (Below VCC)

12

0.53

0.64

0.77

Vdc

Mute Output Impedance -

19

High
Low

-

-

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

8-90

10
25

-

-

Mn

FIGURE 2 -- TEST CIRCUIT
VCC

=

5.0 Vdc

Ferronics 12-345-K Core

1st Mixer Input
50 MHz

s::

o

bJJ

,~.

CRF 1: muRata SFE 10.7 rnA

~I'

~.

or Equivalent

CRF 2: muRata CFU 455D
or Equivalent

L1 0.41 JLH

:411

..

""

.-----,

Ll: Coilcraft UNll0/142 lOY, Turns
LC1: Toko lMC8128Z

o

~
Z

r

From PLL Phase Detector

~

~
00

.

~

~m

To PLL Phase Detector

~

-m.

()

m

fj

~

r-----liiI

m

4lID

o

~
»

, '

w

10JLF

0

Mute Output

0

Comparator Output

390 k

') I

IiID

10 k

5.0 k
'W\

'W\
5.0 k

1.0 k

0

Recovered Audio
Output

L~-n----o Comparator Test Input
0.01

L....-.....-() Carrier Detect Output

L---------O

W

en

=

10 k

'"o

fj

I

l

()

w

+

JJ

s

Mute Input

MC3363
CIRCUIT DESCRIPTION

The output of the limiter is internally connected to
the quadrature detector, including a quadrature capacitor. A parallel lC tank is needed externally from Pin 14
to VCC. A 68 kOhm shunt resistance is included which
determines the peak separation ofthe quadrature detector; a smaller value will lower the Q and expand the
deviation range and linearity, but decrease recovered
audio and sensitivity.
A data shaping circuit is available and can be coupled
to the recovered audio output of Pin 16. The circuit is
a comparator which is designed to detect zero crossings
of FSK modulation. Data rates of up to 35000 baud are
detectable using the comparator. Best sensitivity is
obtained when data rates are limited to 1200 baud
maximum. Hysteresis is available by connecting a highvalued resistor from Pin 17 to Pin 18. Values below 120
kOhm are not recommended as the input signal cannot
overcome the hysteresis.
The meter drive circuitry detects input signal level by
monitoring the limiting of the limiting amplifier stages.
Figure 5 shows the unloaded current at Pin 12 versus
input power. The meter drive current can be used
directly (RSSI) or can be used to trip the carrier detect
circuit at a specified input power.
A muting op amp is provided and can be triggered
by the carrier detect output (Pin 13). This provides a
carrier level triggered squelch circuit which is activated
when the RF input at the desired input frequency falls
below a preset level. The level at which this occurs is
determined by the resistor placed between the meter
drive output (Pin 12) and VCC. Values between 80-130
kOhms are recommended. This type of squelch is pictured in Figures 3 and 4.
Hysteresis is available by connecting a high-valued
resistor Rh between Pins 12 and 13. The formula is:

The MC3363 is a complete FM narrowband receiver
from RF amplifier to audio preamp output. The low voltage dual conversion design yields low power drain,
excellent sensitivity and good image rejection in narrowband voice and data link applications.
In the typical application, the input RF signal is amplified by the RF transistor and then the first mixer amplifies the signal and converts the RF input to 10.7 MHz.
This IF signal is filtered externally and fed into the second mixer, which further amplifies the signal and converts it to a 455 kHz IF signal. After external bandpass
filtering, the low IF is fed into the limiting amplifier and
detection circuitry. The audio is recovered using a conventional quadrature detector. Twice-IF filtering is provided internally.
The input signal level is monitored by meter drive
circuitry which detects the amount of limiting in the
limiting amplifier. The voltage at the meter drive pin
determines the state of the carrier detect output, which
is active low.

APPLICATION
The first local oscillator is designed to serve as the
VCO in a Pll frequency synthesized receiver. The
MC3363 can operate together with the MC14516617 to
provide a two-chip ten channel frequency synthesized
receiver in the 46/49 cordless telephone band. The
MC3363 can also be used with the MC14515X series of
CMOS Pll synthesizers and MC120XX series of ECl
prescalers in VHF frequency synthesized applications to
200 MHz.
For single channel applications the first local oscillator can be crystal controlled. The circuit of Figure 4
has been used successfully up to 60 MHz. For higher
frequencies an external oscillator signal can be injected
into Pins 25 and/or 26 - a level of approximately 100
mVrms is recommended. The first mixer's transfer characteristic is essentially flat to 450 MHz when this
approach is used (keeping a constant 10.7 MHz IF frequency). The second local oscillator is a Colpitts type
which is typically run at 10.245 MHz under crystal
control.
The mixers are doubly balanced to reduce spurious
responses. The first and second mixers have conversion
gains of 18 dB and 21 dB (typical), respectively. Mixer
gain is stable with respect to supply voltage. For both
conversions, the mixer impedances and pin layout are
designed to allow the user to employ low cost, readily
available ceramic filters.
Following the first mixer, a 10.7 MHz ceramic bandpass filter is recommended. The 10.7 MHz filtered signal
is then fed into the second mixer inpu~ Pin 21, the other
input Pin 22 being connected to VCC.
The 455 kHz IF is filtered by a ceramic narrow bandpass filter then fed into the limiter input Pin 9. The limiter
has 10 I'V sensitivity for - 3.0 dB limiting, flat to 1.0
MHz.

Hyst = VCC/ (Rh x 10- 7 ) dB
The meter drive can also be used directly to drive a
meter or to provide AGC. A current to voltage converter
or other linear buffer will be needed for this application.
A second possible application of the op amp would
be in a noise triggered squelch circuit, similiar to that
used with the MC3357/MC3359/MC3361 B FM IFs. In this
case the op amp would serve as an active noise filter,
the output of which would be rectified and compared
to a reference on a squelch gate. The MC3363 does not
have a dedicated squelch gate, but the NPN RF input
stage or data shaping comparator might be used to
provide this function if available. The op amp is a basic
type with the inverting input and the output available.
This application frees the meter drive to allow it to be
used as a linear signal strength monitor.
The circuit of Figure 4 is a complete 50 MHz receiver
from antenna input to audio preamp output. It uses few
components and has good performance. The receiver
operates on a single channel and has input sensitivity
of <0.3 /LV for 12 dB SINAD.

NOTE: For further application and design information, refer to AN9ao.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

8-92

FIGURE 3 - TYPICAL APPLICATION IN A PLL FREQUENCY SYNTHESIZED RECEIVER
VCC

= 5.0 Vdc

CRF1: muRata SFE 10.7M
CRF2: muRata CFU 455D
LC1: Toko 7MCB12BZ

;s:
0

d
:0

RF Input
49.670 to
49.970 MHz

....-,1

0.01

m---L

0

L - - - - - - - - - - I - - -..
_

~
Z

From PLL Phase Detector

r

~

~
00

z--I

To
MC145166f7
Dual PLL

CRl

+

10.245 M

m


Mute
Control

I

Cr

T
100 k

LCl
L
C

= 680 "H
= 180 pF

I-

~(
1.0 "H

~

Recovered Audio
Output

I Pin 26
L

I.... 25
Din

=

0.08"H

('

fosc: 200 MHz

fpjn 24

Note: Pull Up resistor is
used to run the oscillator above 50 MHz.

II
FIGURE 4 RF Input
.67 MHz
50n

SINGLE CHANNEL NARROWBAND FM RECEIVER AT 49.67 MHz

MC3363DW

(

0.01

;!Jj'::,
"::"

20k

o~ Ii':'6k

E:q'

20k

s::
o

.fm=.U-~'~

23~

d
:0

~

r

Z
~

~
00

,

'f

Squelch
Adjust

L.a. Out
"(oPtional)

,

4.7/LH

4.7/LH

3,3/LH

10/LH

8.0

n Spkr

_.. )~

,

•

s:

oen

z

-I

m

Co)

:0

J!
()

Co)

m

~

o

m

<

39k

~

50k

o

»~

Fl - 455 kHz.ceramic filter, Rin
RLED

F2 -

=

Rout

= 1.5 kn to 2.0 kn

MuRata CFU455X or CFW455X, suffix denotes bandwidth
10.7 MHz ceramic filter. Ain = Rout = 330 n

MuRata SFE10.7MJ·A. SFA10.7MF5. or SFE10.7MS2A.
F2X -

Carrier

23

Detect

F2

~Indicator

----c::::L..

p22

.....-

I

21

VCC

~1.0/LF
LCl -

455 kHz quadrature tank circuit; Toka 7MC8128Z

Pl - Volume control. miniature potentiometer, logarithmic
taper.
Xll -10.245 MHz fundamental mode crystal. load capacity
32 pF.
X2 -

Standard 10.7 MHz Filter

10.7 MHz crystal filter. FOX 10M20A or equivalent.

Crystal filters improve adjacent channel and second
image (unwanted 48.76 MHz) rejection. Sensitivity is
degraded very slightly with this cirellit.

+

38.97 MHz, 3rd overtone crystal, series mode.

0.68 ~H adjustable coil; Coilcraft M1287-A
O.221lH adjustable coil; Coilcraft M1175-A
Vee - VLED
RLED is used to adjust LED current: 'LED =
RLED

FIGURE 5 -

CIRCUIT SCHEMATIC

27

6
8

7

23

6~

s:

5

0

<1
:0
0

..

r

»

r

Bias

Z

m

»

~

~
cp m
to
c.n

:0

~

~~~
2~"'Bias

120

r r

,

s

13

(')

W
15

14

19

0

m

0
Ul
0

m

<

0

m
0

~
»

11

16

17
20

1

18

w
en
w

MC3363

FIGURE 6 - PC BOARD COMPONENT VIEW
WITH HIGH PERFORMANCE CRYSTAL FILTER

FIGURE 8 -

FIGURE 7 - PC BOARD CIRCUIT SIDE VIEW

PC BOARD COMPONENT SIDE GROUND PLANE

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
8-96

MOTOROLA

MC3367

• SEMICONDUCTOR - - -_ __
TECHNICAL DATA

LOW VOLTAGE FM NARROWBAND RECEIVER
· .. with single conversion circuitry including oscillator, mixer, IF
amplifiers, limiting IF circuitry, and quadrature discriminator. The
MC3367 is perfect for narrowband audio and data applications up
to 75 MHz which require extremely low power consumption. Battery powered applications down to VCC = 1.1 V are possible. The
MC3367 also includes an on-board voltage regulator, low battery
detection circuitry, a receiver enable allowing a power down
"sleep mode," two undedicated buffer amplifiers to allow simultaneous audio and data reception, and a comparator for enhancing FSK (Frequency Shift Keyedl data reception to 1200 baud.
• Low Supply Voltage: VCC = 1.1 to 3.0 Vdc
• Low Power Consumption: PD = 1.5 to 5.0 mW
• Input Bandwidth 75 MHz

LOW VOLTAGE
SINGLE CONVERSION
FM RECEIVER
SILICON MONOLITHIC
INTEGRATED CIRCUIT

28~
~III'~~~~Y
1

• Excellent Sensitivity: Input Limiting Voltage for 12 dB
Sinad = 0.5 p.Vrms from Conjugated Matched Source

OW SUFFIX
PLASTIC PACKAGE
CASE 751F
(SO-2BLI

• Voltage Regulator Available (Source Capability 3.0 mAl
• Receiver Enable to Allow Active/Standby Operation
• Low Battery Detection Circuitry
• Self Biasing Audio Buffer with Nominal Gain AV

4.0

• Data Buffer with Nominal Gain AV = 3.2
• FSK Data Shaping Comparator Included

PIN CONNECTIONS

• Standard 28-Lead Surface Mount (SOICI Package

Mixer Out

FIGURE 1 -

Data Buffer Out

BLOCK DIAGRAM
Mixer In

Data Buffer In
1st IF Amp Out

Osc. Base

Osc. Emit.

Rec. Audio
Quad Tank

Quad Tank
Demod. Gnd

Comparator lIP

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

8-97

MC3367

MAXIMUM RATINGS (Voltages with respect to Pins 8 and 13· TA
Rating

~ 25°C)

Pin

Value

Unit

Supply Voltage

18

5.0

Vdc

RF Input Signal

3

1.0

Vrms

Audio Buffer Input

21

1.0

Vrms

Data Buffer Input

26

1.0

Vrms

Comparator Input

14

1.0

Vrms

Junction Temperature

-

150

°c

-65to +150

°c

Storage Temperature

Devices should not be operated at or outside these values. The "Recommended
Operating Limits" provide for actual
device operation.

RECOMMENDED OPERATING CONDITIONS
Pin

Value

Unit

Supply Voltage

18

1.1 to 3.0

Vdc

Receiver Enable Voltage

16

o or VCC

Vdc

1.2 V Select Voltage

19

Open or VCC

Vdc

RF Input Signal Level

3

0.001 to 100

mVrms

o to 75

MHz

Parameter

RF Input Frequency

3

Intermediate Frequency (IF)

-

455

kHz

Audio Buffer Input

21

mVrms

Data Buffer Input

26

o to 75
o to 75

Comparator Input

14

10 to 300

mVrms

Ambient Temperature

-

o to 70

°c

ELECTRICAL CHARACTERISTICS (VCC

mVrms

~ 1.3 V, fa ~ 10.7 MHz, fmod ~ 1.0 kHz, Deviation ~ 3.0 kHz, TA ~ 25°C,

Test Circuit of Figure 2 unless otherwise noted)
Characteristic

I

Pin

I

Min

TVp

Max

Units

1.4
0.5

3.0

mA
/LA

-

OVERALL MC3367 PERFORMANCE
Drain Current -

Pin 15
Pin 15

~
~

VCC
0 Vdc

Recovered Audio IRF Input ~ 10 mY)
Noise Output (RF Input

~

0 mY)

Input for -3.0 dB Limiting

-

-

10

-

13

10

-

4.5

3

-

0.2

-

-

mVrms
mVrms

p,Vrms

MIXER
Mixer Input Resistance IRp)
Mixer Input Capacitance (Cp)
FIRST IF AMPLIFIER

I First IF Amp Voltage Gain

25

dB

AUDIO BUFFER
4.0

-

125

-

kll

21

-

70

-

mVrms

MaXimum Output Swing

22

-

800

-

mVpp

Output Resistance

22

-

680

-

II

Voltage Gain

-

-

3.2

-

VN

Input Resistance

26

8.0.

-

Mil

Maximum Input for Undistorted Output 1< 3% THO)

26

70

-

mVrms

Maximum Output Swing

27

600

-

mVpp

Output Resistance

27

-

1.5

-

Voltage Gain

-

Input Resistance

21

Maximum Input for Undistorted Output

VN

DATA BUFFER

kll
(continued)

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

8-98

MC3367
ELECTRICAL CHARACTERISTICS -

continued IVee
TA

~

Characteristic

~ 1.3

V, fa ~ 10.7 MHz, fmod ~ 1.0 kHz, Deviation ~ 3.0 kHz,
25°C, Test Circuit of Figure 2 unless otherwise noted)

I

I

Pin

Min

I

Typ

I

Max

Units

COMPARATOR
Minimum Input for Triggering
Maximum Input Frequency IRL
Rise Time 110-90%; RL

~

~

100 kn)

100 kn)

Fall Time 190-10%; RL ~ 100 kfl)

14

-

7.0

-

mVrms

14

-

25

-

kHZ

15

-

5.0

p.s

15

-

0.4

-

p.s

LOW BATTERY DETECTOR
Low Battery Trip Point
Low Battery Output - Vec

~

0.9 V

-Vcc

~

1.3V

VOLTAGE REGULATOR
Regulated Output Isee Figure 6)
Source Capability
FIGURE 2 -

EVALUATION CIRCUIT
VCc 2

MC34119D
Low Power
Audio Amplifier

0.01

39 k

3.3 k

0.22

330

I

:J.022

I

I

~

Rl ~ 8.0 n
to 32 n
Audio

100

Output
1300 to
3000 Hzl

:JrO

~r+~~------------~--+-+--{)VREG

:J 1.0

Enable

~ble

~-+-+--oVCC

100 k
L-----------t-----------------------------------t============~+_~Data
Output
10 to 60 Hzl
4.7

NOTES:
1. FL 1 and FL2 are 455 kHz ceramic bandpass filters, which should have
input and output impedances of 1.5 kD to 2.0 kn. Suggested part
numbers are muRata CFU455X or CFW455X -the "X" suffix denotes
bandwidth.
2. LCl is a 455 kHz resonator. Recommended part number are Toka
America 7M8128Z. The evaluation board layout shown provides for

4. Ccl and Cc3 are RF coupling capacitors and should have ~ 20 n
impedance at the desired input and oscillator frequencies.
5. Cc2 provides "light coupling" of the oscillator signal into the mixer,
and should have a = 3.0 kO to 5.0 kD impedance at the desired local
oscillator frequency.
6. Capacitors labelled Cs are bypass capacitors and should have ~ 20 n
impedance at the desired RF and local oscillator frequencies.
7. The network of Ll, Cl and C2 provides impedance matching of the
mixer input (nominally 3.0 kD shunted by 9.0 pF) to 50 0 at the
desired RF/IF input frequency. This will allow for bench testing of
the receiver from typical RF signal generators or radio service monitors, but additional or different matching will be required to maximize receiver sensitivity when used in conjunction with an antenna,
RF preamplifier or mixer.

use of either resonator. Ceramic discriminator elements cannot be
used with the MC3367 due to their low input impedance. The
damping resistor value can be raised to increase the recovered audio
or lowered to increase the quadrature detector's bandwidth and
linearity- practical limits are approximately 27 k.O: to 75 kQ. Typically
the quadrature detector's bandwidth should match the low IF filter's
bandwidth
3. The data buffer is set up as a low-pass filter with a corner frequency
of approximately 200 Hz. The audio buffer is a bandpass filter with
corner frequencies of 300 Hz and 3.0 kHz. The audio amplifier provides bass suppression.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
8-99

Me3367

RECOVERED AUDIO versus SUPPLY

FIGURE 3 -

80

1400

~1.0~

60

/'

1200

22

V22

50

I

1000

(

40

DRAIN versus SUPPLY

1600

~

70

~E

FIGURE 4 -

I
I

~

-'>
u

800

.Y

30

600

20

400

V9

10

I

200

o

o

0.5

1.5

1.0

FIGURE 5 -

2.0
VCC IVI

2.5

3.0

3.5

o
o

4.0

900

+10

800
S+N

:>

"-

-20

-60

2.5

3.0

3.5

4.0

VREG versus SUPPLY

700

-10 r=:::-

-50

2.0
VCC IVI

1000

+20

-40

1.5

1.0

FIGURE 6 -

S + N. N versus INPUT

+30

-30

0.5

500

>

400

~

R

~~
6
27

0.1

C:::!;:

r-RL

7330

RL

~ 990

300

N

R ~ 56k!1

RL

~ 00

200

~ C~1000pF
22

600

.s

100

Output

-70.130-120-110-100 -90 -80

-70 -60 -50

-40 -30

00

'h
0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

VcCIVI

FIGURE 7 -

REGULATED OUTPUT AND RECOVERED AUDIO
versus TEMPERATURE

1150

~

~ 3.0 mlAI /

1130 V17IILOAJ
1110

'"\

""-X V

E

;:: 1090
::>

~ 1070

i :~:~

t-=--

/

~

1\
i'-.

f-VIO /

::>

~ 1010
~ 990

........

\

-25

0
+25
+50
+75
TA. AMBIENTTEMPERATURE I"CI

3.95
3.94

2

~3.93

2

~

""3.92 r----~

1

'"
ffi

3.9 1

~
§

-

3.6

I
~b

3.9

3.4

"

3.89

+100

1

:3.88

1

.; 3.87

1

3.86
3.85
-55

13
+125

3

""

2
2

~

~ r--Avab
1\

2
2
2

\Avdb

1.8
1.6

-25

0
+25
+50
+75
TA. AMBIENT TEMPERATURE (OCI

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

8-100

3

-..........::: :::-..

::>

970
950
-55

2

1

\
' - --\

BUFFER AMPLIFIER GAINS versus
TEMPERATURE

2

1

I

>

FIGURE 8 -

+100

+125

MC3367
FIGURE 9 -

3.0

--

2. 9
2.8

~

"" 2.7
~
~ 2.6

CURRENT DRAIN versus TEMPERATURE

ITOTAL ~ 19 + 118 + 124

-..........
.............

...........

C>

i

>-

2. 5

:::>

2. 4

u

............

;::: 2. 3
~ 2. 2

2. 1

2.0
-55

-25

FIGURE 10 -

0
+25
+50
+75
TA, AMBIENT TEMPERATURE lOCI

+100

+125

MC3367DW DEMONSTRATION RECEIVER

Alternate input circuit
for 72 MHz receiver.
In. Freq.

L1

L2

C1

C2

C3

C4

Ce1

Ce2

CB

RO

10.7 MHz

6.8 "H

Short

2-82 pF

10 pF

120 pF

50 pF

1.0 k pF

5.0 pF

0.1 "F

Open

45 MHz

0.68 "H

1.2 "H

5-25 pF

Open

30 pF

5.0 pF

1.0 k pF

1.0 pF

1.0 k pF

1.0 k

72 MHz

0.22 "H 0.22 "H 5-25 pF

Open

18 pF

3.0 pF

470 pF

1.0 pF

470 pF

1.0 k

Volume Control: CRL 812503SL

VCC1: 1.1 Vt03.0V
VCC2: 2.0 V to 16 V
Speaker: 8.0 n to 32 n
Jl: Jumper - install for 1.2 V operation. Leave open for 2,4 V operation.
les mount on circuit side (back) of PC board.
C3, C4 must be 5% silver mica

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

8-101

MC3367

'FIGURE 11- BOTTOM (CIRCUIT) SIDE

1·~------------~3o/~------------~·~1

FIGURE 12 -

TOP (COMPONENT/GROUND PLANE) SIDE

'""1---------------

3%"

---------------!·~I

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

8-102

FIGURE 13 - CIRCUIT SCHEMATIC
11
2

;s::

I

1.:n •.

~I

3

~I

4

t 1.511

I rrb II
24

23
2.0 k

~

25 28

9

t

! I

12

17

~.7k

0

,>
Z

~I

6

~

~
0

c.>

3:

o

Z

--l

m

JJ

~

0

m

6U>

7

Co)

1~~ l
180

0)
~

I

1100 k ~

!

~1kOO

0

m

<
6

m
01

»~

91 k

f1k

19

20 16

14

15

-

26

27

21

22

MC3367
CIRCUIT DESCRIPTION

The audio buffer is a noninverting amplifier with a
nominal voltage gain of 4.0 VN. This buffer is selfbiasing so its input should be ac coupled. The two
buffers, when applied as active filters, can be used
together to allow simultaneous audio and very low
speed data reception. Another possible configuration
is to receive audio only and include a noise-triggered
squelch.
The comparator is a non inverting type with an open
collector output. Typically, the pull-up resistor used
between Pin 15 and VCC is 100 kfl. With RL = 100 kfl
the comparator is capable of operation up to 25 kHz.
This circuit is self-biasing, so its input should be ac
coupled.
The regulator is a 0.95 V reference capable of sourcing
3.0 mAo This pin (Pin 17) needs to be decoupled using
a 1.0-10 /LF capacitor to maintain stability of the
MC3367.
All three Vccs on the MC3367 (VCC, VCC2, VCC3) run
on the same supply voltage. VCC is typically decoupled
using capacitors only. VCC2 and VCC3 should be
bypassed using the RC bypasses shown in Figure 2.
Eliminating the resistors on the VCC2 and VCC3
bypasses may be possible in some applications, but a
reduction in sensitivity and quieting will likely occur.
The low battery detection circuit gives an NPN open
collector output at Pin 20 which drops low when the
MC3367 supply voltage drops below 1.1 V. Typically it
would be pulled up via a 100 kfl resistor to supply.
The 1.2 V Select pin, when connected to the MC3367
supply, programs the low battery detector to trip at VCC
< 1.1 V. Leaving this pin open raises the trip voltage on
the low battery detector.
Pin 16 is a receiver enable which is connected to VCC
for normal operation. Connecting this pin to ground
shuts off receiver and reduces current drain to ICC <
0.5/LA.

The MC3367 is an FM narrowband receiver capable
of operation to 75 MHz. The low voltage design yields
low power drain and excellent sensitivity in narrowband
voice and data link applications. In the typical application the mixer amplifies the incoming RF or IF signal
and converts this frequency to 455 kHz. The signal is
then filtered by a 455 kHz ceramic filter and applied to
the first intermediate frequency (IF) amplifier input,
before passing through a second ceramic filter. The
modulated IF signal is then applied to the limiting IF
amplifier and detector circuitry. Modulation is
recovered by a conventional quadrature detector. The
typical modulation bandwidth available is 3.0 to 5.0 kHz.
Features available include buffers for audio/data
amplification and active filtering, on board voltage regulator, low battery detection circuitry with programmable level, and receiver disable circuitry. The MC3367
is an FM utility receiver to be used for voice and/or
narrowband data reception. It is especially suitable
where extremely low power consumption and high
design flexibility are required.

APPLICATION
The MC3367 can be used as a high performance FM
IF for use in low power dual conversion receivers.
Because of the MC3367's extremely good sensitivity
(0.6 /LV for 20 dB (S + N)/N, see Figure 5), it can also
be used as a stand alone single conversion narrowband receiver to 75 MHz for applications not sensitive
to image frequency interference. An RF preamplifier
will likely be needed to overcome preselector losses.
The oscillator is a Colpitts type which must be run
under crystal control. For fundamental mode crystals
choose resonators, parallel resonant, for a 32 pF load.
For higher frequencies, use a 3rd overtone series
mode type. The coil (L2) and RD resistor are needed
to ensure proper operation.
The best adjacent channel and sensitivity response
occur when two 455 kHz ceramic filters are used, as
shown in Figure 2. Either can be replaced by a 0.1 /LF
coupling capacitor to reduce cost, but some degradation in sensitivity and/or stability is suspected.
The detector is a quadrature type, with the connection from the limiter output to the detector input provided internally as with the MC3359 and the MC3361.
A 455 kHz LC tank circuit must be provided externally.
One of the tank pins (Pin 11) must be decoupled using
a 0.1 /LF capacitor. The 56 kfl damping resistor (see
Figure 2), determines the peak separation olthe detector (and thus its bandwidth). Smaller values will
increase the separation and bandwidth but decrease
recovered audio and sensitivity.
The data buffer is a noninverting amplifier with a
nominal voltage gain of 3.2 VN. This buffer needs its
dc bias (approx. 250 mY) provided externally or else
debiasing will occur. A single-pole RC filter, as shown
in Figure 5, connecting the recovered audio output to
the data buffer input provides the necessary dc bias and
some post detection filtering. The buffer can also be
used as an active filter.

APPENDIX
Design of 2nd Order Sallen-Key Low Pass Filters
Input ~

~+
Cl
Low Pass Output

L\I\II
R2 ..L::r: C2

-=-

_
Bias

_

0 to fa Hz

Avo - K

The audio and data buffers can easily be configured as
active low pass filters using the circuit configuration
shown above. The circuit has a center frequency (fo)
and quality factor (Q) given by the following:

1
fo = 21T VR1R2C1C2
Q

=
R2C2
j R1C1

+

1
jR1C2
R2C1

+ (1 -K)

jR1C1
R2C2

If possible, let R1 = R2 or C1 = C2 to simplify the above
equations. Be sure to avoid a negative Q value to prevent instability. Setting Q = 1/\12 = 0.707 yields a maximally flat filter response.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
8-104

MC3367

Data Buffer Design
The data buffer is designed as follows:
fo = 200 Hz
Cl = C2 = 0.Q1 J.LF
Q = 0.707 (target)
K = 3.2 (data buffer open loop voltage gain)
Setting Cl

Audio Buffer Design
The audio buffer is designed as follows:
fo = 3000 Hz
R1 = R2 = 8.2 kfl
Q = 0.707 (target)
K = 4.0 (audio buffer open loop voltage gain)

= C2 yields:

Setting Rl = R2 yields:

1

1

fo

fo = 27TRl v<::lC2

= 2nC1VR1R2

1
Q

= JR2

1
JRl
Rl +(2-K) R2

Iteration yields C2 = 2.65 (Cl) to make Q = 0.707.
Substitution into the equation for fo yields:
Cl = 3900 pF
C2 = 2.65 (Cl) = 0.01 J.LF
R1 = R2 = 8.2 kfl

Iteration yields R2 = 4.2 (Rl) to make Q = 0.707.
Substitution into the equation for fo yields:
Rl = 38 kfl (use 39 kfl)
R2 = 4.2 (Rl) = 180 kfl
Cl = C2 = 0.01 J.LF

MOTOROLA LlNEARIiNTERFACE ICs DEVICE DATA
8-105

MC3371
MC3372

MOTOROLA

_ SEMICONDUCTOR - - - - - TECHNICAL DATA

Advance Information

Low Power
Narrowband FM IF

LOW POWER

FMIF

The MC3371 and MC3372 perform single conversion FM reception and
consist of an oscillator, mixer, limiting IF amplifier, quadrature discriminator, active filter, squelch switch, and meter drive circuitry. These devices
are designed for use in FM dual conversion communication equipment.
The MC3371/MC3372 are similar to the MC3361/MC3357 FM IFs, except
that a signal strength indicator replaces the scan function controlling driver
which is in the MC3361/MC3357. The MC3371 is designed for the use of
parallel LC components, while the MC3372 is designed for use with either
a 455 kHz ceramic discriminator, or parallel LC components.
These devices also require fewer external parts than earlier products.
The MC3371 and MC3372 are available in dual-in-line and surface mount
packaging.
•
•
•
•
•
•
•

Wide Operating Supply Voltage Range: VCC = 2.0 to 9.0 V
Input Limiting Voltage Sensitivity of - 3.0 dB
Low Drain Current: ICC = 3.2 rnA, @ VCC = 4.0 V, Squelch Off
Minimal Drain Current Increase When Squelched
Signal Strength Indicator: 60 dB Dynamic Range
Mixer Operating Frequency Up to 100 MHz
Fewer External Parts Required than Earlier Devices

SILICON MONOLITHIC
INTEGRATED CIRCUIT

P SUFFIX
PLASTIC PACKAGE
CASE 648

o SUFFIX
PLASTIC PACKAGE
CASE 7518
(SO-16)

PIN CONNECTIONS
Cfvstal{ 1

Osc.

MAXIMUM RATINGS
Pin

Symbol

Power Supply Voltage

4

Vcc(maxl

10

Vdc

RF Input Voltage (VCC '" 4.0 Vdcl

16

V16

1.0

Vrms

Rating

Value

Unit

Detector Input Voltage

8

V8

1.0

V p_p

Squelch Input Voltage (VCC '" 4.0 Vdcl

12

V12

6.0

Vdc

Mute Function

14

V14

-0.7to 10

Vpk
mA

Mute Sink Current

14

114

50

Junction Temperature

-

TJ

150

'C

Storage Temperature Range

-

Tstg

-65to +150

'c

DevIces should not be operated at these values. The "Recommended Operating Conditions" table
provides conditions for actual device operation.

Mixer Output

3

limiter Input

5

DeCOUPlin g{

11 FilterOutpul

6

Recovered
Audio

crvstal{ 1
Osc.

Mixer Output

3

limiter Input

5

RECOMMENDED OPERATING CONDITIONS
Rating
Supply Voltage

Pin

Symbol

Value

Unit

4

VCC

2.0 to 9.0
2.4 to 9.0

Vdc

RF Input Voltage

16

Vrf

0.0005 to 10

mVrms

RF Input Frequency

16

Irf

0.1 to 100

MHz

Oscillator Input Voltage

1

Vlocal

80 to 400

mVrms

Intermediate Frequency

-

Iii

455

kHz

(@TA = 25'CI
(-30'C" TA" +75'C)

Decoupling 6
LimiterOulput

7
Recovered

AudiO

ORDERING INFORMATION
Temperature

Limiter Amp Input Voltage

5

Vii

o to 400

mVrms

Filter Amp Input Voltage

10

Via

0.1 to 300

mVrms

MC3371D

SO-16

Squelch Input Voltage

12

VSQ

o or 2

Vdc

MC3371P

Plastic DIP

Mute Sink Current

14

ISQ

0.1 to 30

rnA

MC3372D

Ambient Temperature Range

-

TA

-30 to +70

'C

MC3372P

Device

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

8-106

Range

- 30' to + 70'C

Package

SO·16
Plastic DIP

MC3371, MC3372
AC ELECTRICAL CHARACTERISTICS (VCC ~ 4.0 Vdc, fa ~ 5S.1125 MHz, df ~ ±3.0 kHz, fmod ~ 1.0 kHz, 50 n source, flocal
~ 576575 MHz Vlocal ~ 0 dBm TA ~ 25'C unless otherwise noted)

Pin

Characteristic

Symbol

Input for 12 dB SINAD
Matched Input - (See Figures 10, 11 & 12)
Unmatched Input - (See Figures 7A & 7B)

-

Input for 20 dB NQS

-

VNQS

Recovered Audio Drop Voltage Loss
Vrf ~ -30 dBm, VCC ~ 4.0 V to 2.0 V

-

AFloss

Meter Drive Output Voltage (No Modulation)
Vrf ~ -100 dBm
Vrf ~ -70 dBm
Vrf ~ -40 dBm

13

Filter Amp Gain
Rs ~ 600 n, fs

-

Recovered Audio Output Voltage
Vrf ~ -30 dBm

~

10 kHz, Vfa

~

~

-40 dBm, RL

-

Signal to Noise Ratio
Vrf ~ -30 dBm

-

Total Harmonic Distortion
Vrf ~ -30 dBm, BW ~ 400 Hz to 30 kHz

-

-

15

120

200

320

-S.O

-1.5

-

Zo
DVO

Meter Drive
Vrf ~ -100 to -40 dBm

13

MO

Meter Drive Dynamic Range
RFln
IFln (455 kHz)

13

Mixer Third Order Input Intercept Point
fl ~ 5S.125 MHz
f2 ~ 5S.1375 MHz

-

Mixer Input Resistance

16

Rin

Mixer Input Capacitance

16

Cin

JLVrms

dB
Vdc

1.1
2.0

0.3
1.5
2.5

0.5
1.9
3.1

47

50

-

14

20

-

36

67

-

-

0.6

3.4

450

-

dB
dB
dB

THD

9

%

n
Vdc

-

1.45

-

-

O.S

-

-

60
SO

-

JLA/dB

MVD

dB

-

~

3.5

sin

9

4.0 Vdc, T A

-

AV(Mix)

Detector Output Voltage INa Modulationl
Vrf ~ -30 dBm

Unit

mVrms

MDrv
MVl
MV2
MV3

Detector Output Impedance

~

1.0
5.0

AFO

1.S kn

DC ELECTRICAL CHARACTERISTICS IVcc

Max

AV(Amp)

~

Typ

JLVrms

1.0 mVrms

Mixer Conversion Gain

Vrf

Min

VSIN

dBm

lTOMix

-

-

-22

Min

Typ

Max

-

3.2
3.6
1.0

4.2
4.S
2.0

0.9

1.6

2.3

Vl1
dVll

1.5
2.0

2.5
5.0

3.5
S.O

Hys

34

57

SO

3.3

-

kn

2.2

-

pF

25'C, unless otherwise noted I

Characteristic

Pin

Drain Current (No Input Signal)
Squelch Off, Vsq ~ 2.0 Vdc
Squelch On, Vsq ~ 0 Vdc
Squelch Off, VCC ~ 2.0 to 9.0 V

4

Detector Output (No Input Signal)
DC Voltage, VS ~ VCC

9

Filter Output (No Input Signal)
DC Voltage
Voltage Change, VCC ~ 2.0 to 9.0 V

11

Trigger Hysteresis

-

Symbol

rnA
Iccl
Icc2
dlccl

Vdc

V9

Vdc

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

8·107

Unit

mV

•

MC3371, MC3372
TYPICAL CURVES (UNMATCHED INPUT)

FIGURE 1 -

TOTAL HARMONIC DISTORTION
versus TEMPERATURE

RSS' versus RF INPUT

FIGURE 2 -

0

5.0

1

.1

TA

Vcc = 4.0 Vdc
RF Input = - 30 dBm r fa = 10.7 MHz

0

0
0

0

~

0

0

\l/ 1\

0
0
-55

V I--

-15

FIGURE 3 -

r/

0

5.0
25
45
65
TA, AMBIENT TEMPERATURE I'CI

85

105

0
-140

125

-100

60
54

VCC = 4.0Vdc_
fa = 10.7 MHz

2
6

~-20
~ -30

70 dBm

/

:=
5-40
'"
~

0

I---

B

i/

-60

/

-110 dBm
-35

-15

5.0
25
45
65
TA, AMBIENT TEMPERATURE I'CI

85

105

-70
-70

125

FIGURE 6 -

MIXER GAIN versus SUPPLY VOLTAGE

FIGURE 5 -

0

I

7

-60

-50

./

--- -

-40

/

5

t

:=
=>

15

~

2

o

I

I-

8

-30
-20
RF INPUT IdBml

-10

30'C

I-JA

)4.0Iv~rr

vcJ
TA = +27'C
RFin = -40 dlBm

+ 25'C

111

-10 dB\;;-

0

-15 dB:nfa = 10.7 MHz- r--RFin - 40 dBm _
f-1.8 1kfl Loa,d

6. 0

3.0
1.0

2.0

3.0 4.0
5.0
6.0
7.0
VCC, SUPPLY VOLTAGE IVI

8.0

9.0

- 20 dB,;;-

0

0

10

1.0

1\

~\

f\\

5.0 dBm

1\\

-5.0 dBm

I\\' 01~
10

100
f, FREQUENCY IMHzl·

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
8-108

10

MIXER GAIN versus FREQUENCY

0

.~

9. 0

0

TA

= 4.0 Vdc _
= 27'CI

VCC
T~

4

1

-

/

0

TAI~- t =

20

hoMHZ
_
II 3rd Order Products

'" -50

0
-55

-20

MIXER OUTPUT versus RF INPUT

2
6. 0

-60
-40
RF INPUT IdBml

100lMHZ
Desired prod7

-10

l

48

4

-80

I

30 dBm

i

.lS~TA = -30'C

-120

FIGURE 4 -

RSSI OUTPUT versus TEMPERATURE

VCC = 4.0Vdc_
fa 10.7 M~Z

J

OTA=+75'C

\/

-35

~ T~~30'C-

TA - +25'C~ ~

0

./

~ +75'~,

1000

MC3371, MC3372

FIGURE 7A -

MC3371 FUNCTIONAL BLOCK DIAGRAM AND TEST FIXTURE SCHEMATIC

RSSIOutpul

RF Input

VCC

= 4.0 Vdc

Filter In
0.1

51k

SQ In

it

Filter Out

Cl

o.ot

51
11

16

15

001

510 k

Mute

13

AF Oul
to Audio
Power Amp

470

8.2 k

1

12

51 k

53 k

r----,
0.1

0.1

I
20 k

I

i

Quad Coil TOKO

I 2A6597 HK (10 mml
lor

I
I 7MC·8128Z (7 mml
L ___ --1
muRata
CFU455D2

Units:

or

R:

equivalent

n, C: J.LF

Unless otherwise noted,
capacitors marked "sm"

are silver mica.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

8-109

MC3371, MC3372

FIGURE 7B -

MC3372 FUNCTIONAL BLOCK DIAGRAM AND TEST FIXTURE SCHEMATIC

RSSIOutput

RF Input

VCC

= 4.0 Vdc

Filter In
51 k

CI
0.01

SO In

I,

51

470

r----~_o

SID k

Mute

16

I,

Filter Out

8.2 k

O.OIJ

AFOut
to Audio
Power Amp

IS

•

51k

53k

CI4
27p
Rlt

51k

o

RI2
4.3 k

Ceramic
Resonator
muRata

CDB455CI6
muRata

CIS

CFU455D2
or

JO.I

equivalent

Units:

R: fl.C: p.F
Unless othelWise noted.
capacitors marked "8m"
are silver mica.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
8-110

MC3371, MC3372
PIN DESCRIPTION
OPERATING CONDITIONS vcc = 4.0 Vdc, RFln = 100 p.V, fmad = 1.0 kHz, fdev = 3.0 kHz. MC3371 at fRF = 10.7 MHz
(see Figure 10).
Internal Equivalent

Circuit

Pin

The base of the Colpitts oscillator. Use
a high impedance and low capacitance
probe or a "sniffer" to view the waveform without altering the frequency.
Typical level is 450 mVp-p.
VCC

15 k
OSCI .......---'3~N.-2

OSC2

3

MXOut

The emitter of the Colpitts oscillator.
Typical signal level is 200 mVp-p. Note
that the signal is somewhat distorted
compared to that on pin 1.

OSC2

Output of the Mixer. Riding on the
455 kHz is the RF carrier component.
The typical level is approximately
60 mVp-p.

3

VCC

Y'~~'
1.5 k

4

5

100
p.A

VCC

Supply Voltage operating range.
ground.

2.0 to 9.0 Vdc is the

Vee is decoupled to

Input to the IF amplifier after passing
through the 455 kHz ceramic filter. The
signal is attenuated by the filter. The
typical level is approximately
50 mVp-p.

IFln

IFln

DECI
DEC2
6
7

DECl
DEC2

IF Decoupling. External 0.1 p.F capacitors connected to Vcc.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

8-111

MC3371, MC3372
PIN DESCRIPTION
~ 4.0 Vdc, RFln ~ 100 p.V, fmod ~ 1.0 kHz, fdev ~ 3.0 kHz. MC3371 at fRF ~ 10.7 MHz

OPERATING CONDITIONS VCC
(see

Pin

10).
Symbol

Internal Equivalent
Circuit

Description

Squelch Input. See discussion in
application text.

13

RSSI Output. Referred to as the
Received Signal Strength Indicator or
RSSI. The chip sources up to 60 p.A
over the linear 60 dB range. This pin
may be used many ways, such as:
AGe, meter drive and carrier triggered

RSSI

Vee

:t

squelch circuit.

Bias

13

14

RSSIOUI

Mute Output. See discussion in
application text.

MUTE

tf~::
40 k
"::'

15

"::'

GND

GND

*
16

Ground. The ground area should be
continuous and unbroken. In a twosided layout, the component side has
the ground plane. In a one-sided layout, the ground plane fills around the
traces on the circuit side of the board
and is not interrupted.

15

•

MIXln

Vee

Mixeqn

~
3.3k

Mixer InputSeries Input Impedance:
@ 10 MHz: 309 -j33 n
@45 MHz: 200 -j13

n

10 k

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
8-112

MC3371, MC3372
PIN DESCRIPTION
OPERATING CONDITIONS VCC = 4.0 Vdc, RFln = 100 p.V, fmod = 1.0 kHz, fdev = 3.0 kHz. MC3371 at fRF = 10.7 MHz
(see
10).
Pin

Symbol

8

Quad
Coil

Internal Equivalent
Circuit

B

~
T 10p

9

auadCoil
VCC

Description
Quadrature Tuning Coil. Composite
(not yet demodulated) 455 kHz IF
signal is present. The typical level is
500 mVp-p.

50 p.A

RA

Recovered Audio. This is a composite
FM demodulated output having signal
and carrier component. The typical
level is 1.4 Vp-p.

VCC

The filtered recovered audio has the
carrier component removed and is

typically 800 mVp-p.

10

11

Filter Amplifier Input

Filter Amplifier Output. The typical
signal level is 400 mVp-p.

FilOut

~
VCC240P.A

11

Filte'Out

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
8-113

MC3371, MC3372
PIN DESCRIPTION
OPERATING CONDITIONS vcc = 4.0 Vdc, RFln = 100 p.V, fmod

1.0 kHz, fdev

=

= 3.0 kHz. MC3372 at fRF = 45 MHz

(see Figure 121.

Internal Equivalent
Pin

Circuit

IF Amplifier Input

6

DECl

IFln~
6

53 k

DEC

IF Decoupling. External 0.1 I'F capacitors connected to

Vee.

60 l'A

7

IFOut

Vi
vee

IF Amplifier Output Signal level is
typically 300 mVp·p.

7 IFOut

50 p.A

l20l'A

7

8

Quadrature Detector Input. Signal

Quadl n

B

~

level is typically 150 mVp-p.
Quad In

Vee

50l'A

9

Recovered Audio. This is a composite
FM demodulated output having signal
and carrier components. Typical level

RA

is 800 mVp-p.

Vee

RAOul

The filtered recovered audio has the
carrier signal removed and is typically

500 mVp·p.

*Other pins are the same as pins in MC3371.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
8-114

MC3371, MC3372
FIGURE 8 -

MC3371 CIRCUIT SCHEMATIC

Mixer OUI
3

Vee

ose1+--~"",,"~

OSe2

r-

~

15
GND

RAOul

FIGURE 9 -

MC3372 CIRCUIT SCHEMATIC

Vee

ose1+--~"""~

OSe2

r-

~

Vee

15
GND

4

RAOul
6

53 k

DEe+--~-~----~~---------------r~'---~

7
IF Oul +-----::l:-----------------+---:i---±-.J

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
8-115

MC3371, MC3372
CIRCUIT DESCRIPTION
The MC3371 and MC3372 are low power narrowband
FM receivers with an operating frequency of up to
60 MHz. Its low voltage design provides low power drain,
excellent sensitivity, and good image rejection in narrowband voice and data link applications.
This part combines a mixer, an IF (intermediate frequency) limiter with a logarithmic response signal
strength indicator, a quadrature detector, an active filter
and a squelch trigger circuit. In a typical application, the
mixer amplifier converts an RF input signal to a 455 kHz
IF signal. Passing through an external bandpass filter, the
IF signal is fed into a limiting amplifier and detection
circuit where the audio signal is recovered. A conventional quadrature detector is used.
The absence of an input signal is indicated by the presence of noise above the desired audio frequencies. This
"noise band" is monitored by an active filter and a detector. A squelch switch is used to mute the audio when
noise or a tone is present. The input signal level is monitored by a meter drive circuit which detects the amount
of IF signal in the limiting amplifier.

APPLICATION
The oscillator is an internally biased Colpitts type with
the collector, base, and emitter connections at Pins 4, 1
and 2 respectively. This oscillator can be run under crystal
control. For fundamental mode crystals use crystal characterized parallel resonant for 32 pF load. For higher frequencies, use 3rd overtone series mode type crystals.
The coil (L2) and resistor RD (R13) are needed to ensure
proper and stable operation at the LO frequency (see
Figure 12,45 MHz application circuit).
The mixer is doubly balanced to reduce spurious radiation. Conversion gain stated in the AC Electrical Characteristics table is typically 20 dB. This power gain measurement was made under stable conditions using a 50 !1
source at the input and an external load provided by a
455 kHz ceramic filter at the mixer output which is connected to the VCC (Pin 4) and IF input (Pin 5). The filter
impedance closely matches the 1.8 k!1 internal load resistance at Pin 3 (mixer output). Since the input impedance
at Pin 16 is strongly influenced by a 3.3 k!1 internal biasing
resistor and has a low capacitance, the useful gain is
actually much higher than shown by the standard power
gain measurement. The Smith Chart plot in Figure 16
shows the measured mixer input impedance versus input
frequency with the mixer input matched to a 50!1 source
impedance at the given frequencies. In order to assure
stable operation under matched conditions, it is necessary to provide a shunt resistor to ground. Figures 10, 11
and 12 show the input networks used to derive the mixer
input impedance data.
Following the mixer, a ceramic bandpass filter is recommended for IF filtering (i.e. 455 kHz types having a
bandwidth of ± 2.0 kHz to ± 15 kHz with an input and
output impedance from 1.5 k!1 to 2.0 k!1). The 6 stage
limiting IF amplifier has approximately 92 dB of gain. The
MC3371 and MC3372 are different in the limiter and quadrature detector circuits. The MC3371 has a 1.8 k!l and a
51 k!1 resistor providing internal DC biasing and the out-

put of the limiter is internally connected, both directly
and through a 10 pF capacitor to the quadrature detector;
whereas, in the MC3372 these components are not provided internally. Thus, in the MC3371, no external components are necessary to match the 455 kHz ceramic filter,
while in the MC3372, external 1.8 k!1 and 51 k!1 biasing
resistors are needed between Pins 5 and 7, respectively
(see Figures 11 and 12).
In the MC3371, a parallel LCR quadrature tank circuit
is connected externally from Pin 8 to VCC (similar to the
MC3361). In the MC3372, a quadrature capacitor is
needed externally from Pin 7 to Pin 8 and a parallel LC
or a ceramic discriminator with a damping resistor is also
needed from Pin 8 to VCC (similar to the MC3357). The
above external quadrature circuitry provides 90 0 phase
shift at the IF center frequency and enables recovered
audio.
The damping resistor determines the peak separation
of the detector and is somewhat critical. As the resistor
is decreased, the separation and the bandwidth is
increased but the recovered audio is decreased. Receiver
sensitivity is dependent on the value of this resistor and
the bandwidth of the 455 kHz ceramic filter.
On the chip the composite recovered audio, consisting
of carrier component and modulating signal, is passed
through a low pass filter amplifier to reduce the carrier
component and then is fed to Pin 9 which has an output
impedance of 450 n. The signal still requires further filtering to eliminate the carrier component, deemphasis,
volume control, and further amplification before driving
a loudspeaker. The relative level of the composite
recovered audio signal at Pin 9 should be considered for
proper interaction with an audio post amplifier and a
given load element. The MC13060 is recommended as a
low power audio amplifier.
The meter output indicates the strength of the IF level
and the output current is proportional to the logarithm
of the IF input signal amplitude. A maximum source current of 60 fJ-A is available and can be used to drive a
meter and to detect a carrier presence. This is referred
to as a Received Strength Signal Indicator (RSSI). The
output at Pin 13 provides a current source. Thus, a resistor to ground yields a voltage proportional to the input
carrier signal level. The value of this resistor is estimated
by (VCC(Vdc) - 1.0 V)/60 fJ-A; so for VCC = 4.0 Vdc, the
resistor is approximately 50 k!1 and provides a maximum
voltage swing of about 3.0 V.
A simple inverting op amp has an output at Pin 11 and
the inverting input at Pin 10. The noninverting input is
connected to 2.5 V. The op amp may be used as a noise
triggered squelch or as an active noise filter. The bandpass filter is designed with external impedance elements
to discriminate between frequencies. With an external
AM detector, the filtered audio signal is checked for a
tone signal or for the presence of noise above the normal
audio band. This information is applied to Pin 12.
An external positive bias to Pin 12 sets up the squelch
trigger circuit such that the audio mute (Pin 14) is open
or connected to ground. If Pin 12 is pulled down to 0.9 V
or below by the noise or tone detector, Pin 14 is internally
shorted to ground. There is about 57 mV of hyteresis at
Pin 12 to prevent jitter. Audio muting is accomplished by
connecting Pin 14 to the appropriate point in the audio

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

8-116

MC3371, MC3372
path between Pin 9 and an audio amplifier. The voltage
at Pin 14 should not be lower than -0.7 V; this can be
assured by connecting Pin 14 to the point that has no dc
component.
Another possible application ofthe squelch switch may
be as a carrier level triggered squelch circuit, similar to

FIGURE 10 -

Vcc

= 4.0Vdc

the MC3362/MC3363 FM receivers. In this case the meter
output can be used directly to trigger the squelch switch
when the RF input at the input frequency falls below the
desired level. The level at which this occurs is determined
by the resistor placed between the meter drive output
(Pin 13) and ground (Pin 15).

TYPICAL APPLICATION FOR MC3371 AT 10.7 MHz

ASSIOutput
A2
10 k

+ C9
JIO

1st IF 10.7 MHz
from Input
Front End

Units:
A: n, C: /LF
Unless otherwise noted
capacitors marked "5m"
are silver mica.

A3
100 k

CIS!
91p

....._-'\....
A5,.,...._~VAIISquelch Control I
10 k

AFOut
VA2 ~f--""-o to Audio
10 k
Power Amp

t

- - - - , T2: Toko

L ______..:.........._ ......------.L~---......muAata
CFU455D2
or
equivalent

......-~:-='------jl::':-!:'::-=-:--=.J
CI4

~O.I

MOTOROLA LlNEARIINTERFACE ICs DEVICE DATA

8-117

I 2A6597 HK 110 mml
I or
7MC·8128Z (7 mml

MC3371, MC3372

FIGURE 11 -

VCC

~

4.0 Vdc

TYPICAL APPLICATION FOR MC3372 AT 10.7 MHz

RSSIOutput
R2

10 k
1st If 10.7 MHz

Units:
R: n, C: I'f
Unless otherwise noted

R3
100 k

from Input
Front End

capacitors marked "sm"
are silver mica.

C16!
91p

~_~VlR51'r-_"" VRI

(Squelch Cantrall

10 k

Af Out

;.....c-~-Oto Audio

YR2

10 k

Power Amp

CI4
27p

muRala
CfU45502
or

RI2
4.3 k
CI5

~Ol

equivalent

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
8-118

muRala
DCOB455CI6

MC3371, MC3372
FIGURE 12 -

TYPICAL APPLICATION FOR MC3372 AT 45 MHz

RSSIOutput
to Meter (Triplett -100 kV)

Vcc = 4.0 Vdo

R2
12k
Units:
R: n, C: I'F
Unless otherwise noted
capacitors marked "sm"
are silver mica.

R3
100 k

R5

VRI (Squelch Control)
10 k

AF Out
VR2 ~i--__-oto Audio
10 k
Power Amp

C14
27p
R12
muRata
4.3 k Cl CDB455C16

C15

muRata
CFU455D2
or
equivalent

AGURE 13 -

::f 0.1

RSSI OUTPUT versus RF INPUT

FIGURE 14 -

3. 5
3. 0
u

2. 5

~

./

~

./

1.0

fRF = 10.7 MHz
VCC = 4.0 Vdc
Reference Figure 10

/'

/'
-100

./

2.5

./
./

2.0

5
o 1.5

V
./

gj

0
-120

u

./

~

O. 5

3.0

r---

>=> 2.0
1=
=>
0
1. 5

'"

RSSI OUTPUT versus RF INPUT

3.5

~

I---

r----

./

1.0

/

I--0.5

-80
-60
RF INPUT (dBm)

-40

o

-20

......

-120

fRF = 45 MHz
VCC = 4.0 Vdc
Reference Figure 12

I---

r----

I---

/'
-100

-80
-60
RF INPUT (dBm)

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
8-119

V

-40

-20·

MC3371, MC3372
FIGURE 15 -

S+N, N, AMR versus INPUT

0

I
S+N

O....-!:

~

~-1 0

1""-

~-2 0

«
Z

~

"1"'-'\ l '

z~-3 0

+

U)

.~

-40

-130

S+N30%AM

1"0.

I

~

-50

-60

fRF = 10.1 MHzVCC = 4.0 V TA = 25'C
-

~

"'-110

-90

N

-10
-50
RF INPUT IdBm)

30

'REFERENCE FIGURES 10, 11 & 12

FIGURE 16 -

MIXER INPUT IMPEDANCE versus FREQUENCY

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

8-120

10

MC3371, MC3372
FIGURE 17 -

MC3371P PC BOARD COMPONENT VIEW WITH MATCHED INPUT AT 10.7 MHz

COMPONENT SIDE

~~MD20Cll

J3 Dvcc
C140 C13C12

Af OUT

@
O
BN(

T2D~

o
J2

MC3371
If 1B.7 MHZ
fRONT END

INPUT If
1B.7 MHZ

;:::'===;1

R1B
[]VR2

MC3371

MHZ
6
15

8

~B~ ~9 O~2~

@
0

*O~
DJ4~CUT
~R5 ~R4 n ~ ~
VR1 ~ V

-AJ

FIGURE 18 -

CUil

CD

V

c'fI VR1

BNC

ETER
OUT

-£-

cc

MC3371P PC BOARD CIRCUIT OR SOLDER SIDE AS VIEWED THRU COMPONENT SIDE

Above PC Board is laid out for the circuit in Figure 10.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

8·121

MC3371, MC3372
FIGURE 19 -

MC3372P PC BOARD COMPONENT VIEW WITH MATCHED INPUT AT 10.7 MHz

COMPONENT SIDE
~

VCC GNO

~DCh

'tg'+

~

J3 VCC

C15~ ~ ~RO~ C12

AF OUT

o

(Q)

4:=-CFU45502

INPUT IF

XTAL
i~~Q nil10 ~111I1111.245
1111.7 MHZ
~
MHZJI(Q)
J2
14 12
MC3372
7 0

o

BNC

0

DVR2 n

~By n n~3 C2 L2~n
LO

MC3372
IF 1111.7 MHZ
FRONT END

0C16

t7 RZY 5 Y 8CJ ~R13 L1
+40~61
DJ4~
R5 n., n n ~
VRI D
yn4 t6 yRI METER
R2

~

~Rcc

FIGURE 20 -

Om

BNC

OUT

MC3372P PC BOARD CIRCUIT OR SOLDER SIDE AS VIEWED THRU COMPONENT SIDE

Above PC Board is laid out for the circuit in Figure 11.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

8-122

MOTOROLA

MC13055

SEMICONDUCTOR-----TECHNICAL DATA

Advance Information
Wideband FSK Receiver

WIDEBAND
FSK
RECEIVER

The MC13055 is intended fo RF data link systems using carrier frequencies up
to 40 MHz and FSK (frequency shift keying) data rates up to 2.0 M Baud
(1.0 MHz). This design is similar to the MC3356, except that it does not include
the oscillator/mixer. The IF bandwidth has been increased and the detector output
has been revised to a balanced configuration. The received signal strength
metering circuit has been retained, as has the versatile data slicer/comparator.
• Input Sensitivity 20 ~V @ 40 MHz
• Signal Strength Indicator Linear Over 3 Decades
• Available in Surface Mount Package
• Easy Application, Few Peripheral Components

MONOLITHIC SILICON
INTEGRATED CIRCUIT

...

P SUFFIX
PLASTIC PACKAGE
CASE 648

1

o

SUFFIX
PLASTIC PACKAGE
CASE 7518
(SO-16)

Figure 1. Block Diagram and Application Circuit

PIN CONNECTIONS
Squelch
Adjust
(meter)

Comparator Gnd

1

Comparator VCC

2

IF Ground 3
IFVCC

4

Input

5

Umiter Bias {

6

Um~er

Quad Bias
L2

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
8-123

8

12

Meter Drive

11 }
10

Detector
Out

9

Quad Input

MC13055
MAXIMUM RATINGS
Rating
Power Supply Voltage
Operating Supply Voltage Range

Symbol

Value

VCC(max)
V2, V4

15

Unit
Vdc

3.0 to 12

Vdc
·C

Junction Temperature

TJ

150

Operating Ambient Temperature Range

TA

-40 to +85

·C

Storage Temperature Range

Tstg

-65 to +150

·C

Power Dissipation, Package Rating

Po

1.25

W

ELECTRICAL CHARACTERISTICS (VCC = 5.0 Vdc, fo = 40 MHz,lmod = 1.0 MHz, ,M = ±1.0 MHz, TA = 25·C, test circuit of Figure 2.)
Characteristics

Measure

Min

Typ

Max

Unit

12+ 14

20

25

rnA

10

-

rnA

7.0

9.0

IlAIdB

Data Comparator Pull-Down Current

116

-

Meter Drive Slope versus Input

112

4.5

Carrier Detect Pull-Down Current

113

-

1.3

113

-

500

-

rnA

Carrier Detect Pull-Up Current
Carrier Detect Threshold Voltage

V12

700

800

900

mV

DC Output Current

110,111

Recovered Signal

Vl0-Vll

-

350

Total Drain Current

VIN

-

20

Vl0-Vll

-

30

Sensitivity for 20 dB S + NIN, BW = 5.0 MHz
S + NIN at Vin = 50 I1V
Input Impedance @ 40 MHz

Pin 5, Ground

Rin
Cin

Quadrature Coil Loading

Pin9t08

Rin

430

Cin

4.2
4.5
7.6
5.2

-

(1A
(1A
mVrms
I1Vrms
dB

lin
pF

lin
pF

Figure 2. Test Circuit

l00pF

14

r---.,

1-1-<:3>--+___t-----+---t---
u
a: 300
w

./

z

I
I
I

:l
rE

39.4 Cl
39.3
39.2

"0

1200

~

;t-" ~O:lll

~ 1000

e

f1,l

20

z

w
a:
a:
::>
u
a:
0

I-

t-"

800
600

u
w

t;;

0

400

+

200

.....

...:
>:>

o
o

15

1/
1.0

-:;:]4

-

.....

50 !z
w
a:
a:
40B
~

Il.

30~

'"a:

20~
o
Il.

10~

1/
3.0

5.0
7.0
9.0
11
Vee, SUPPLY VOLTAGE (Vdc)

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
8-125

~

-_

60 '[

13

15

o '"

MC13055
Figure 9. Recovered Audio versus Temperature

Figure 10. carrier Detect Threshold versus Temperature

>" 1000

i

§.

5

:I 900

4.0
2.0
0
Q -2.0

§
Q

ii!

-4.0

~ -6.0
~ -8.0

'"

-'

-~

--

,.-

~

!

700

:::>

u
II:
w 300

Iii
::;;

~ 200

.........

.......

....

5
N

-40

-20

0
20
40 60
80 100
TA. AMBIENT TEMPERATURE 1°C)

120

140

:>

500
-60

Figure 11. Meter Current versus Temperature

400

.............

ffi

600

II:
II:

........

800

ir 600

-60

soo

..........

~

~ -10
:> -12

...zw~

........

InpU10.
-10 J--..

~
~

V

-30-

-

V

----

100
-60 -40

-20

~

-40
-50
-60

,

20 40
60 80 100
TA. AMBIENT TEMPERATURE l°e)

120 140

~

:!!. -50

-~

~

~

"" r-..

~en

~-

I'-... ~

"""

-20

Figure 12. Input Limiting versus Temperature

B.'!l

........

-40

..........

"
1'-.::.. . .....

~I!o

....... "

...... r..... ........;: .......

-20 0
20 40
60 80
TA. AMBIENTTEMPERATURE 1°C)

....

100

120

-

'" -70

~,

......

-60

~

::;;
:::J

~

-80

t-_

,.......

'-

~

:Z -90

->

-60 -40 -20

140

0
20 40
60 80 100
TA. AMBIENT TEMPERATURE 1°C)

Figure 13. Input Impedance, Pin 5

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
8-126

-'

" ... '"

120

140

MC13055

Figure 14. Test Fixture
(Component Layout)

1+-1' - - - - ---------1·1
4"

(Circuit Side View)

4"

1+-1·-----4"-------1·1
MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

8-127

Figure 15. Internal Schematic
.....,2

16

s::

0

JiIDJ

d

67

J)

~g

M

70

12~

0

r
»
r

Z

m

»

~

Z

~ -I
m
J)
N
CD

46
65

~

()

m

0
(J)

0

m

<
0

m

s

15

~lllc'

Q9

Q8

13J

L

IS

(")
...a
Co)

o

U1
U1

"6

I I

26

HHHHH~·n~ I~

0

»~
~

'" 58
,..J

'157

'156

~

~

'155

;:::<

'154

~2

['l;a

~

~

~

I

11

48

47

~1

7750

49

MC13055
GENERAL DESCRIPTION
The MC13055 is an extended frequency range FM IF,
quadrature detector, signal strength detector and data shapero
It is intended primarily for FSK data systems. The design is
very similar to MC3356 except that the oscillator/mixer has
been removed, and the frequency capability of the IF has been
raised about 2:1. The detector output configuration has been
changed to a balanced, open-collector type to permit
symmetrical drive of the data shaper (comparator). Meterdrive
and squelch features have been retained.
The limiting IF is a high frequency type, capable of being
operated up to 100 MHz. It is expected to be used at 40 MHz
in most cases. The quadrature detector Is internally coupled
to the IF, and a 2.0 pF quadrature capacitor is internally
provided. The 20 dB quieting sensitivity is approximately
20 ILV, tuned input, and the IF can accept signals up to
220 mVrms without distortion or change of detector quiescent
DC level.
The IF is unusual in that each of the last 5 stages of the 6
stage limiter contains a signal strength sensitive, current
sinking device. These are parallel connected and buffered to

produce a signal strength meter drive which is fairly linear for
IF input signals of 20 ILV to 20 mVrms. (See Figure 4.)
A simple squelch arrangement is provided whereby the
meter current flowing through the meter load resistance flips
a comparator at about 0.8 Vdc above ground. The signal
strength at which this occurs can be adjusted by changing the
meter load resistor. The comparator (+) input and output are
available to permit control of hysteresis. Good positive action
can be obtained for IF input signals of above 20 ILVrms. A
resistor (R) from Pin 13 to Pin 12 will provide VCdR of
feedback current. This current can be correlated to an amount
of signal strength hysteresis by using Figure 4.
The squelch is internally connected to the data shapero
Squelch causes the data shaper to produce a high (VCC)
output.
The data shaper is a complete "floating" comparator, with
diodes across its inputs. The outputs of the quadrature
detector can be fed directly to either or preferably both inputs
of the comparator to produce a squared output swinging from
VCC to ground in inverted or noninverted form.

MOTOROLA LlNEARIiNTERFACE ICs DEVICE DATA
8-129

MOTOROLA

MC13104
MC13105

SEMICONDUCTOR-----TECHNICAL DATA

Product Preview
1.0 GHz Receiver LNA/MixerNCO

1.0 GHz RECEIVER
LNAIMIXERNCO

The MC13104/13105 are fully integrated UHF down converters intended
for use in receivers operating in the 800 MHz to 1.0 GHz frequency range.
The design utilizes Motorola's advanced Mosaic® 3 RF bipolar process to
yield high gain, low noise, low current drain in a cost effective monolithic device. The basic receiver functions of low noise amplifier, mixer and AGC are
included in both devices, while the MC13104 also includes a VCO with two
buffered outputs which permit simple interfacing to multichannel PLUprescaler frequency synthesized systems. Ap~!:cations for the MC131 04/131 05
include CT-2 cordless telephones, security monitor receivers, remote control,
video and audio short range links, field disturbance receivers, and low cost
cellular radios. A power down control to minimize current drain with minimum
recoverylturn-on time.
• Low Cost Silicon Bipolar Design
• Internal VCO
• VCO Buffer to Drive Prescalar
• Low Drain Current: Nominal 10 mA Current Drain (ON)
• Power Down Current: Nominal 10 IlA
• LNA Has AGC Input with Nominal ~ 20 dB Range
• Performance Optimized for CT-2 and Similar Systems
• Target Noise Figure of 5.0 dB Overall at 1.0 GHz
• Input Impedance: Nominal 50 n

SILICON MONOLITHIC
INTEGRATED CIRCUIT

DSUFFIX
PLASTIC PACKAGE
CASE 751B
(50-16)

ORDERING INFORMATION
Temperature
Range

Device
MC13104D
MC13105D

Package
50-16

- 20' to +70'C

50-16

PIN CONNECTIONS AND BLOCK DIAGRAMS
(MCI3104)
Prescalar
Drive
ExcRer
Drive
OSCGnd

f

OSCTunlng
2

,,-:1

(MCI3105)
Power
Down

Gain
Switch

Gain Switch

Lo Input
Gnd

RFBias
(Gnd)

RF Input
(Base)

Lo Input

RF Input
(Base)

Power
Down

RF Input Gnd
(Emitter)
RF Bias
Gnd
Gnd

RFBias
Gnd

Vcc

Gnd

Image FiRer

Image
Rller

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
8-130

Vee

MOTOROLA

MC13135
MC13136

SEMICONDUCTOR-----TECHNICAL DATA

Advance Information
FM Communications Receivers

DUAL CONVERSION
NARROWBAND
FM RECEIVERS

The MC13135/MC13136 are the second generation of single chip, dual
conversion FM communications receivers developed by Motorola. Major
improvements in signal handling, RSSI and first oscillator operation have
been made. In addition, recovered audio distortion and audio drive have
improved. Using Motorola's MOSAICTM 1.5 process, these receivers offer
low noise, high gain and stability over a wide operating voltage range.
Both the MC13135 and MC13136 include a Colpitts oscillator, VCO
tuning diode, low noise first and second mixer and LO, high gain limiting
IF, and RSSI. The MC13135 is designed for use with an LC quadrature
detector and has an uncommitted op amp that can be used either for an
RSSI buffer or as a data comparator. The MC13136 can be used with
either a ceramic discriminator or an LC quad coil and the op amp is
internally connected for a voltage buffered RSSI output.
These devices can be used as stand-alone VH F receivers or as the
lower IF of a triple conversion system. Applications include cordless
telephones, short range data links, walkie-talkies, low cost land mobile,
amateur radio receivers, baby monitors and scanners.
• Complete Dual Conversion FM Receiver - Antenna Input to
Audio Output
• Voltage Buffered RSSI with 70 dB of Usable Range

SILICON MONOLITHIC
INTEGRATED CIRCUIT

P SUFFIX
PLASTIC PACKAGE
CASE 724

DWSUFFIX
PLASTIC PACKAGE
CASE 751 E
(SO-24L)

ORDERING INFORMATION

• Low Voltage Operation - 2.0 to 6.0 Vdc (2 Cell NiCad Supply)
• Low Current Drain - 3.5 mA Typ
• Low Impedance Audio Output < 25

Temperature
Range

Device

Q

• VHF Colpitts First LO for Crystal or VCO Operation

MC13135P

.. Isolated Tuning Diode

MC13135DW

• Buffered First LO Output to Drive CMOS PLL Synthesizer

MC13136P

Package
PlaS1ic DIP
SO-24L

- 40 0 to +85°C
Plastic DIP

MC13136DW

SO-24L

PIN CONNECTIONS
MC13136

MC13135

1st LO Base

Varicap C

1st LO Base

Varicap C

1st LO Emitter

VaricapA

lsI LO Emitter

Varicap A

lstLOOut

1sl Mixer In 1

1sl Mixer In 2

VCC1

1sl Mixer In 2

1sl Mixer Out

2nd LO Emitter

1st LO Out

151 Mixer In 1

VCC1
2nd LO Emitter
2nd LO Base
2nd Mixer Out

VEE

VCC2

2nd lO Base
2nd Mixer Out

2nd Mixer In
Audio Out

VEE

Umiterln

OpAmp Ou1

limiter In

Decouple 1

Op Amp In-

Decouple 1

2nd Mixer In
Audio Out
Buffered RSSI Output

OpAmp In-

limiter Output

Op Amp In +

RSSI

1st Mixer Out

VCC2

RSSI

Quad Coil

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
8-131

Quad Input

MC13135, MC13136
MAXIMUM RATINGS
Rating

Pin

Symbol

Value

4,19

Vcc(max)

6.5

Vdc

RF Input Voltage

22

RFin

1.0

Vrms

Junction Temperature

-

TJ

+150

°c

Tstg

-65to+150

°c

Symbol

Value

Unit

VCC

2.0 to 6.0

Vdc

flF1

21

MHz

flF2

3.0

MHz

TA

-40to+85

°c

Power Supply Voltage

Storage Temperature Range

Unit

RECOMMENDED OPERATING CONDITIONS
Rating

Pin

Power Supply Voltage

4,19

-

Maximum 1st IF
Maximum 2nd IF
Ambient Temperature Range

ELECTRICAL CHARACTERISTICS (TA =25°C, VCC=4.0Vdc, fo=49. 7MHz, iMOD= 1.0 kHz, Deviation =±3.0kHz,1j stLO =39MHz, f2nd
LO = 10 245 MHz IF1 = 10 7 MHz IF2 = 455 kHz unless otherwise noted All measurements performed in the test circuit of Figure 1 )
Condition

Symbol

Total Drain Current

No Input Signal

ICC

Sensitivity (Input for 12 dB SINAD)

Matched Input

VSIN

Recovered Audio
MC13135
MC13136

VRF= 1.0 mV

AFO

Characteristic

Limiter Output Level
(Pin 14, MC13136)

Min

-

1st Mixer Conversion Gain

VRF= -40 dBm

MXgain1

VRF =-40 dBm

MXgain2

-

First LO Buffered Output
Total Harmonic Distortion

VLO

VRF =-30 dBm

Demodulator Bandwidth

-

RSSI Dynamic Range

-

First Mixer 3rd Order Intercept
(Input)

Unft

6.0

mAdc

1.0

-

THD
BW
RSSI

Matched
Unmatched
Matched
Input

170
215

220
265

270
315

-

130

-

100

-

1.2

3.0

12
13

50
70

%
kHz
dB

-

-

-27

-

-

-

pF

-

ill

1.8

-

ill

25

-

Q

dBm

First LO Buffer Output Resistance

-

RLO

-

R

First Mixer Parallel Input Capacitance

-

C

First Mixer Output Impedance

-

ZO

Second Mixer Input Impedance

-

ZI

-

MOTOROLA LlNEARIINTERFACE ICs DEVICE DATA
8-132

mVrms

-17
-11

First Mixer Parallel Input Resistance

ZO

dB
dB

TOIMix2

ZO

-

mVrms

dBm

-

-

!lVrms
mVrms

TOIMix1

Second Mixer 3rd Order
Intercept (RF Input)

Detector Output Impedance

Max

4.0

VUM

2nd Mixer Conversion Gain

Second Mixer Output Impedance

Typ

722
3.3
330
40

Q
Q

Q

MC13135, MC13136
TEST CIRCUIT INFORMATION
the signal level to the mixer, the third order intercept (Tal)
Although the MC13136 can be operated with a ceramic
point is better with an unmatched input (50 0 from Pin 21 to
discriminator, the recovered audio measurements for both
Pin 22). Typical values for both have been included in the
the MC13135 and MC13136 are made with an LC quadrature
detector. The typical recovered audio will depend on the
Electrical Characterization Table. Tal measurements were
taken at the pins with a high impedance probe/spectrum
external circuit; either the Q of the quad coil, or the RC
analyzer system. The first mixer input impedance was
matching network for the ceramic discriminator. On the
MC13136, an external capacitor between Pins 13 and 14 can
measured at the pin with a network analyzer.
be used with a quad coil for slightly higher recovered audio.
See Figures 10 through 13 for additional information.
Since adding a matching circuit to the RF input increases
Figure la. MC13135 Test Circuit

,-----"""-;------,

Vcc

I

241

11

:J 0.1

varicaP-LI

~

0.001

I-------=::..;---I~ 62pF

0.2~H

:;&:0.01

= =

L------=-i------, Ceramic
Rller
10.7MHz

360

10

Umiter

39k

14

12

0.1 :;&:

13

L ___ -=-_________ .J

Figure 1b. MC13136 Quad Detector Test Circuit

0.1~

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
8-133

RF

~Input

MC13135, MC13136
Figure 2. Supply Current versus Supply Voltage

Figure 3. RSSI Output versus RF Input

6.0

~

1400

--

5.0

!;;; 4.0
w

~

Q,
Q,

::::>

~

r-

.....-

0::
0::

::::>

u

3.0
2.0

u

E 1.0

o
o

/

/

1.0

I

RFin = 49.7 MHz
'MOD = 1.0 kHz
ioEV = ± 3.0 kHz
'1
I

2.0

3.0

4.0

5.0

~ 1200

I----

6.0

.5
Q,

~

s.

1600

t---

Zlo::-

7.0

Vee=4.0V
1000 t-- RFin = 49.67 MHz
'MOD = 1.0 kHz
ioEV = ± 3.0 kHz
BOO

400

V

r--

200
-140

B.O

V

-120

-100

Vee. SUPPLY VOLTAGE M

J

K-

~
RJ=50MHl- B.O

6.0
4.0

if

::::>

~

u..

2.0 ~

1.5

2.0

R~I=

150 MHz

3.0

3.5

2.5

47.5

~

I~

C~~=50MHi

1.0

-60

-40

-20

Figure 5. Oscillator Frequency
versus Varactor Bias

.1

-

-88

48.0

10 [

"" ..........

V

RF INPUT (dBm)

Figure 4. Varactor Capacitance, Resistance
versus Bias Voltage
I'-...C~I=150MHz

-

V

o

4.0

§
Ii.
0::

¥

47.0

~

46.5

O!.
w

~

46.0
45.5

",---

/'

/

/

1

~~l~~ ~
1

27p

-

O.61~H

'l'~

2'
Yark:ap:}

2

1.0MIl

:.t O.2~F

Va

-

5.0p~

45.0
1.0

2.0

3.0

4.0

5.0

VB. VARACTOR BIAS VOLTAGE. VPin24 to VPin 23 (Vdc)

VB. VARACTOR BIAS VOLTAGE (Vdc)

Figure 6. Signal Levels versus RF Input

Figure 7. Signal + Noise, Noise, and
AM ReJeclion versus Input Power

6.0

10
S+N
10r---r---r-~r-~---1---1---+---1

;[
~

iii" -10

~-20

-101--+--+--+--+-+7""'b"""":;J..~~

...........
~

'"

!-30
~
2- 40

~-50 r-60 r-

-20

-70
RFin. RF INPUT (dBm)

-70

-130

~

Vee = 4.0Vdc
RFin = 49.67 MHz
'Moo = 1.0 kHz
ioEV = ± 3.0 kHz

-110

-90

S+N30%AM

"'-

I'....N

-70

RFin. RF INPUT (dBm)

MOTOROLA LlNEAR/INTERFACE ICs DEVICE DATA

8-134

-50

-30

MC13135, MC13136
Figure 9. First Mixer Third Order Intermodulation
(Unmatched Input)

Figure 8. Op Amp Gain and Phase
versus Frequency

so

80

r-

30
iii'

:E

z

;jj
:>
«

120

~

10

Phase

J"'....

0
-10

\

OJ

Eo _

=>


1\
- SO
10 k

ffl
w
a:

1\

r-

20

B.O
7.0

;::

.s lS00
o

a:

0

f-

5
~

6.0

-+~w...-..------I'--_ Recovered
10
0.1

:;j;:

0.1

Audio

Umiter

10k

11
RSSI
'---"'I-~-------+-~ Output
14

12
0.1~

13
455 kHz
Quad Coil
Taka
7MC-BI2BZ

Figure 17b. PC Board Component View

NOTES: 1. 0.21tH tunable (unshielded) inductor
2. 39 MHz Series mode resonant
3rd Overtone Crystal
3. 1.51tH tunable (shielded) inductor
4. 10.245 MHz Fundamental mode crystal,
32 pF load
5. 455 kHz ceramic filter, rnuRata CFU 4558
or equivalent
6. Quadrature coil, Taka 7MC-BI2BZ (7mm)
or Taka RMC-2A6597HM (1 Omm)
7. 10.7 MHz ceramic filter, muRata SFE1 O. 7MJ·A
or equivalent

Figure 17c. Optional Data Slicer Circuit
(Using Internal Op Amp)

Vce

tOM

M6TOROLA LINEAR/INTERFACE ICs DEVICE DATA
8-138

MC13135, MC13136

Figure 18. PC Board Solder Side View

(Circuit Side View)

Figure 19. PC Board Component View

NOTES: 1. 0.2 ~H tunable (unshielded) inductor
2. 39 MHz Series mode resonant
3rd Overtone Crystal
3. 1.5 ~H tunable (shielded) inductor
4. 10.245 MHz Fundamental mode crystal,
32 pF load
5. 455 kHz ceramic filter, muRala CFU 4558
or equivalent

6. Ceramic discriminator, muRala FX2577
or equivalent
7. 10.7 MHz ceramic filter, muRala SFE10.7MJ~A
or equivalent

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
8-139

MC13135, MC13136
Figure 20a. Single Channel Narrowband FM Receiver at 49.7 MHz

MC13136
24
0.1

=!=

23
22

Buffered LO: __-+-------lf-----:-:-:-.._-t--------"
OutpU1

ri1

0.001

'--_ _ _
21-+-__

I

0.21lH

0.01:J

62PF ( RFlnput
150pF
50nSaurce

-=--=-

Ceramic
Filter
10.7 MHz

360

10
0.1

Recovered
Audio
Umiter
10k

11
RSSI
OutpU1
12

0.1 :J
muRata
455 kHz
Resonator
FX2577

Figure 20b. Optional Audio Amplifier Circuit

Speaker
Recovered ----Jf-~\JV'y--H
Audio ---.
0.01

27k

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
8-140

Figure 21. MC13135 Internal Schematic
Vcc1 I
"
15k

I

S::I

§

I

5p

:II

0

r

>
r

VEE

First Mixer

FirstLO

Z

Second LO

Second Mixer

m

>

~

16

Z

VCC2

~ m
--I

~

i:

Vcc2

~UI

:II

~

i:

(')

m

12

0
CJl
0

VEE

VEE

m

<

13

0

m

Vcc2

Vcc2

0

»~

0
.....
(0)
.....
(0)

I

go--2k ~
10
11

T

1~'----T-''----T-''-----9''-''-----9''-''-----=f-'

~

I I

I II

I :;

:;

*

1 I ... I

I I

UmHlng IF Amplifier

Detector and Audio Amplifier

I I

~17

~

0
.....
(0)
.....

(0)

en

Figure 22. MC13136 Internal Schematic
Vcc1

~i;~;t~~~];~:l______~~~~;:~~f"Jl__~~~~f:~J:-'~__~'-____~~~~~____ j[~ "~ ~I_~I:; - ;:

s::

o

dJJ
o

S;
Z

r

II II

I I

-~

First Mixer

FirstLO

Second LO

-1__

~

oj>.
J\)

:s:::

Vcc2

l------ll----t---<> 16

~

00
~

SecondMlxar

z
-l

Vcc2

..I.

Co)
..I.

Co)

m

9'
i:

JJ
~

om

(")

~12

..I.

Co)

S?

VEE

VEE

o
~

om

(")

II

Vcc2

o
»~

I, II II II

I

I

13

"I

Vcc2

~17

2k

:~:

!

I I~ J II II II I II "
I

II

VEE

Limiting IF Amplifier

14

II

Detector and Audio Amplifier

VEE

..I.

Co)
0')

MOTOROLA

MC13155

SEMICONDUCTOR-----TECHNICAL DATA

Advance Information
Wideband FM IF

WIDEBAND FM IF

The MC13155 is a complete wideband FM detector designed for
satellite TV and other wideband data and analog FM applications. This
device may be cascaded for higher IF gain and extended Receive Signal
Strength Indicator (RSSI) range.

SILICON MONOLITHIC
INTEGRATED CIRCUIT

• 12 MHz Video/Baseband Demodulator
• Ideal for Wideband Data and Analog FM Systems
• Limiter Output for Cascade Operation
• Low Drain Current: 7.0 rnA
• Low Supply Voltage: 3.0 to 6.0 V
• Operates to 300 MHz

DSUFFIX
PLASTIC PACKAGE
CASE 7518
(SO-16)

MAXIMUM RATINGS
Pin

Symbol

Value

Power Supply Voltage

Rating

11,14

VEE (max)

6.5

Unit
Vdc

Input Voltage

1,16

Vin

1.0

Vrms

Junction Temperature

-

TJ

+150

°C

Storage Temperature Range

-

Tstg

- 65 to +150

°C

NOTE: Devices should not be operated at or outside these values. The "Recommended Operating
Conditions" provide for actual device operation.

PIN CONNECTIONS

Simplified Block Diagram
Input

Input
Decouple
Buffe,ed
RSSI
Decouple
15

RSSI
Output

Urn"e,
Output
10

Decouple
VEEI

VCCI

RSSI Buffe,

16
Inpul >--0--'-'; .--------'-,

Output

RSSI

VCC2

VEE2

Urnite,Qut
Input >--0-+-';

Urn"e,Out

Quad Coil

L _ _ _...J

(Top View)

Decouple

Balanced
Outputs

Urnite,
Output

ORDERING INFORMATION
Device

Temperature
Range

Package

- 40° to + 85°C

SO-16

NOTE: This device requires careful layout and decoupling to ensure stable operation.

MC13155D

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

8-143

MC13155
RECOMMENDED OPERATING CONDITIONS
Rating

Pin

Symbol

Value

Unit

Power Supply Voltage (TA= 25°C)
-40°C:s; TA:S; 85°C

11,14
3,6

VEE
VCC

-3.0to-6.0
Grounded

Vdc

Maximum Input Frequency

1,16

fin

300

MHz

TJ

-40to+85

°C

-

Ambient Temperature Range

DC ELECTRICAL CHARACTERISTICS (TA = 25°C, no input signal.)
Characteristic
Drain Current
(VEE = - 5.0 Vdc)
(VEE =-5.0 Vdc)
Drain Current Total (see Figure 3)
(VEE = - 5.0 Vdc)
(VEE = - 6.0 Vdc)
(VEE = - 3.0 Vdc)

Pin

Symbol

Min

Typ

Max

Unit

11
14
14

111
114
114

2.0
3.0
3.0

2.8
4.3
4.3

4.0
6.0
6.0

mA

11,14

ITotal

5.0
5.0
5.0
4.7

7.1
7.5
7.5
6.6

10
10.5
10.5
9.5

mA

AC ELECTRICAL CHARACTERISTICS (TA = 25°C flF = 70 MHz VEE = - 5 0 Vdc Figure 2 unless otherwise noted)
Characteristic

Pin

Min

Typ

Max

Unit

Input for - 3 dB Limiting Sensitivity

1,16

-

1.0

2.0

mVrms

Differential Detector Output Voltage (Vin = 10 mVrms)
(fdev = ± 3.0 MHz) (VEE = - 6.0 Vdc)
(VEE = - 5.0 Vdc)
(VEE =-3.0 Vdc)

4,5
470
450
380

590
570
500

700
680
620

Detector DC Offset Voltage

mVp-p

4,5

-250

-

250

mVdc

RSSI Slope

13

1.4

2.1

2.8

IlAIdB

RSSI Dynamic Range

13

31

35

39

RSSIOutput
(Vin = 100 ~Vrms)
(Vin = 1.0 mVrms)
(Vin = 10 mVrms)
(Vin = 100 mVrms)
(Vin = 500 mVrms)

12

-

2.1
2.4
24
65
75

-

2.3

16

-

RSSI Buffer Maximum Output Current

13

(Vin = 10 mVrms)

Differential Limiter Output
(Vin = 1.0 mVrms)
(Vin = 10 mVrms)

7,10

Demodulator Video 3~0 dB Bandwidth

4,5

Input Impedance (Figure 14)
@70MHz Rp (VEE = - 5.0 Vdc)
Cp (C2=CI5 = 100 p)

1,16

Differential IF Power Gain

1,7,10,16

..

100

-

140
180

-

12

-

450
4.8

-

46

NOTE: POSitive currents are out of the pins of the device.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
8-144

-

dB

IIA

36

-

-

-

mAdc
mVrms

MHz
Q

-

pF

-

dB

MC13155
CIRCUIT DESCRIPTION
The MC13155 consists of a wideband three-stage limiting
amplifier, a wide band quadrature detector which may be
operated up to 200 MHz, and a received signal strength

indicator (RSSI) circuit which provides a current output
linearly proportional to the IF input signal level for
approximately 35 dB range of input level.

Figure 2. Test Circuit
Vin )

21
9.9

LOn
IOn
DECI

27

~

VCCI

VEE

DETOI

Video
Output

DET02

VEE

VCC2

VEE

Output
~~'}:
1.0n
330

~umiter2

LOn

Output

330

QUAD 1

499
20p
11 - Coileraft part number 146-09J08S

260n

APPLICATION INFORMATION
Evaluation PC Board
The evaluation PCB shown in Figures 19 and 20 is very
versatile and is designed to cascade two ICs. The center
section of the board provides an area for attaching all surface
mount components to the circuit side and radial leaded
components to the component ground side of the PCB (see
Figures 17 and 18). Additionally, the peripheral area
surrounding the RF core provides pads to add supporting
and interface circuitry as a particular application dictates.
This evaluation board will be discussed and referenced in
this section.
Limiting Amplifier
Differential input and output ports interfacing the three
stage limiting amplifier provide a differential power gain of
typically 46 dB and useable frequency range of 300 MHz.

The IF gain flatness may be controlled by decoupling of the
internal feedback network at Pins 2 and 15.
Scattering parameter (S-parameter) characterization of the
IF as a two port linear amplifier is useful to implement
maximum stable power gain, input matching, and stability over
a desired bandpass response and to ensure stable operation
outside the bandpass as well. The MC 13155 is unconditionally
stable over most of its useful operating frequency range;
however, it can be made unconditionally stable over its entire
operating range with the proper decoupling of Pins 2 and 15.
Relatively small decoupling capacitors of about 100 pF have
a significant effect on the wideband response and stability.
This is shown in the scattering parameter tables where
S-parameters are shown for various values of C2 and C15 and
at VEE of - 3.0 and - 5.0 Vdc.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
8-145

MC13155
TYPICAL PERFORMANCE AT TEMPERATURE
(See Figure 2. Test Circuit)

I

100

10 - TA=1 o
25 C

I

~ 8.0

~

~

r

I
I

4.0

po

R

0.0
0.0

I-

z

1.0

a: 40

~
20

3.0

4.0

5.0

6.0

7.0

8.0

10

t=70MHz
5.0 I- VEE = - 5.0 Vdc

VEE = - 6.0 Vdy i-'"""".-5.0Vdc

...

~

~V /

.....' i / "

./ ~

./

a:

a:

G

~ 3.5

V3.0VdC

c

:

...,./

'; 2.5

-10
10
30
50
70
TA, AMBIENT TEMPERATURE (OC)

/

.:!, 24.0

/

!:i

22.5
22.0
21.5
-50

,

""r--.
1000

90

2.0
-50

110

.....

,...--1-""

"..,.......

-- -I,.....-

-30

r-

jJ.. ~

-10
10
30
50
70
TA, AMBIENTTEMPERATURE (OC)

90

110

Figure 8. RSSI Output versus Input Signal Voltage
(Vin at Temperature)
100.--,.-,-"-rnr.-.--rnTTTrr----'-TTTTT1rrr--r-,-,.,.".,,,

i.---

<"

~

3.0

2!

./
-30

4.0

z

......-

24.5

1l!

.....

,...-- ~

~ 4.5

25.0

en 23.0

.......

5.5

1

Figure 7. RSSI Output versus Ambient
Temperature and Supply Voltage

§ 23.5

.......

Figure 6. Detector Drain Current and Limiter Drain
Current versus Ambient Temperature

-'

5.0
-50

--

Figure 5. Total Drain Current versus Ambient
Temperature and Supply Voltage

'-' 7.5
z
~
c 7.0

2! 5.5

....... ......
...... ,r\

VEE, SUPPLY VOLTAGE (·Vdc)

::::>

.§: 6.0

_40IdB~

o

.........

100
t, FREQUENCY (MHz)

w
a: 8.0
a:

:="'

en
en

9.0

j! 6.5

_ 20 d Bj

'/

2.0

l
_ 30 ldBJ

0

114

8.5

~

60

::::>

/I

2.0

~

i

::::>

D-

--

-10IdB~

~

II-

VEE = - 5.0Vdc

oldBl

<" 80

If

j;j

~

-

IToUlI = 114 till

a:

aa:z 6.0

U"

Figure 4. RSSI Output versus Frequency and
Input Signal Level

Figure 3. Drain Current versus Supply Voltage

~

/

/'"

L
.........-

/'

/

-30

V

-

~~IJ~~50~

VEE = - 6.0 Vdc

60

~50

..-::"40 0 C

~~ 40r-~~H*r-1-~~~~~~A~~H__+~~m
20r-~~H*r-1-~~~~~~H__+~~m

I
90

~

o

~J
V~E=-3rdCI

80~~~~~~~+»~~++H+~~~+H~

~

"" I
~J

VEE=-5.0Vdc 'j
I

-10
10
30
50
70
TA, AMBIENT TEMPERATURE (OC)

<"

o~~~~llW~~~-LUll~

110

0.1

1.0

10
100
Vin, INPUT VOLTAGE (mVrms)

MOTOROLA LlNEARIiNTERFACE ICs DEVICE DATA
8-146

1000

MC13155

Figure 9. Differential Detector Output Voltage versus
Ambient Temperature and Supply Voltage

Ul

~

750

~

700

VE5; - 6.0 Vdc

5_ 650
~jl:600

t~ 550
Ul.,

~:
..... ,5

~~
z

w

500
450

;..-

~

ItC

350
- 50

./

~>

v;::V ./"

~~

V

V

V

./

140

It
10

30

50

70

90

110

./

I..---

V

120
- 50

-30

-10

TA, AMBIENT TEMPERATURE (0G)

~~1600~V~in-=-_-3"'0~d~B~m-----------'---'---'---'---'

Q. 2400

E

1400 VEE = - 5.0 Vdc
fc = 70 MHz
~
1200 fmod = 1.0 MHz
(Figure 16 no external capacitors
o 1000 between Pins 7, 8 and 9, 10)
....>&£...+..~+'=T'-"---1
a:

5

~ 800~--~--~--+"~~~~---b~~~~~~
600 f--t----,j...s,...q7"'~=""'f=-_+=..,

~ 400~--~~F-~~~~~~--~--~--~--~
a:

200f--t~~~~~~--~~_+---+--~--~
O~~

1.5

__J -__

2.0

2.5

~~

3.0

__

3.5

~

__

4.0

L-~

4.5

__

5.0

J-~

5.5

>c.

wC!J

!:i

5o

t

1200

c..

~

~

8001---~~~~+-_~=-4_--~~..

~

40°r---C;~t-~I=::~~~--_r--1

~

5~

__'----1

oL-__L-__L-__~__~__~___L___L___L__~
1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

Q OF QUADRATURE LC TANK

Figure 13. - S+N, N versus IF Input
10

VEE = - 5.0 Vdc
Ic = 70 MHz

SlN

4.0 (See Figure 14)

-10

Capac"ively coupled interstage:
3.0 no attenuation

i'C -20

1.0 ~----__+7"'-----~71''-----~-----'-------~

z

:of
(Jl

-30

-50
-60
-1.0 ' -___-'-____'--___-'-_ _ _'--____...J
-40

-20

-70
-90

20

"-

"

-40

(Jl

a:

./

.....<.

:s!.

Cii

- 60

90

~--~--~----o.l""""'+-_"""'=--~~"

co

r---~--~----'----'-----'

- 80

70

a:

6.0

~ 2.0 f------+------.".-F------l-::~--_+------~
~

50

Vin = - 30 dBm
VEE = - 5.0 Vdc
2000 Ie = 70 MHz
fmod = 1.0 MHz
1600 (Figure 16 no external capacitors ,...t!::..~""'~Ibetween Pins 7, 8 and 9,10)

i;

Figure 12. RSSI Output Voltage versus IF Input

~

30

0.;----::-;:-;;;---------,---,...---,----,----,

Q OF QUADRATURE LC TANK

5.0

Vin = 1.0 mVrms

Figure 11 B. Differential Detector Output Voltage
versus Q of Quadrature LC Tank

.5.

Itc

10

-----

TA, AMBIENT TEMPERATURE (0G)

Figure 11 A. Differential Detector Output Voltage
versus Q of Quadrature LC Tank

co

f.-'"

V
/'

~~
i3

V

. . . Vi-'"

180

j.~ 160

a:

-10

Vin = 10 mv':!-

200

SEr'

./'
- 30

f=70MHz
VEE = - 5.0 Vdc

c..E

0.5.

......... V

400

a:

~

~u;-

,-

220

!:io

. /V -5.0Vdc
l./::: V . / -3.0Vdc

~

til

Figure 10. Differential Limiter Output Voltage versus
Ambient Temperature (Vin = 1 and 10 mVrms)

Ic = 70 MHz
frnod = 1.0 MHz
Idev = ± 5.0 MHz
VEE = - 5.0 Vdc
-70

...............
~N

-50

IF INPUT, (dBm)

-30

IF INPUT (dBm)

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
8-147

-10

10

MC13155
In the 5-parameters measurements, the IF is treated as a
two-port linear class A amplifier. The IF amplifier is measured
with a single-ended input and output configuration in which
the Pins 16 and 7 are terminated in the series combination of
a 47 Q resistor and a 10 nF capacitor to VCC ground (see
Figure 11- 5-Parameter Test Circuit).
The 5-parameters are in polar form as the magnitude
(MAG) and angle (ANG). Also listed in the tables are the
calculated values for the stability factor (K) and the Maximum

Available Gain (MAG). These terms are related in the
following equations:
K=(1-1511 12_152212+lilI2)/(21512521 I)
where: I ill = I 511 522 - 512 521 I.
MAG = 10 log I 521 III 512 I + 10 log I K - ( K2 - 1) 1/2 I
where: K > 1. The necessary and sufficient conditions for
unconditional stability are given as K > 1:
Bl = 1 + I 511 12 -152212 -I ill 2 > 0

Figure 14. 5-Parameter Test Circuit

IF
Input

SMA

)

£

:q

tOn

I

INt

VEE

SMA

r--f--£-+--<

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
8-148

~utput

MC13155
S-Parameters (VEE =-5.0 Vdc, TA = 25°C, C2 and C15 = 0 pF)
K

MAG

MHz

MAG

ANG

MAG

ANG

MAG

ANG

MAG

ANG

MAG

dB

1.0

0.94

-13

8.2

143

0.001

7.0

0.87

-22

2.2

32

2.0

0.78

-23

23.5

109

0.001

-40

0.64

-31

4.2

33.5

5.0

0.48

1.0

39.2

51

0.001

-97

0.34

-17

8.7

33.7

7.0

0.59

15

40.3

34

0.001

-41

0.33

-13

10.6

34.6

10

0.75

17

40.9

19

0.001

-82

0.41

-1.0

5.7

36.7

20

0.95

7.0

42.9

-6.0

0.001

-42

0.45

0

1.05

46.4

50

0.98

-10

42.2

-48

0.001

-9.0

0.52

-3.0

0.29

-

70

0.95

-16

39.8

-68

0.001

112

0.54

-16

1.05

46.4

100

0.93

-23

44.2

-93

0.001

80

0.53

-22

0.76

150

0.91

-34

39.5

-139

0.001

106

0.50

-34

0.94

-

Frequency

InputS11

ForwardS21

OutputS22

RevS12

200

0.87

-47

34.9

-179

0.002

77

0.42

-44

0.97

500

0.89

-103

11.1

-58

0.022

57

0.40

-117

0.75

700

0.61

-156

3.5

-164

0.03

0

0.52

179

2.6

900

0.56

162

1.2

92

0.048

-44

0.47

112

4.7

4.5

1000

0.54

131

0.8

42

0.072

-48

0.44

76

5.1

0.4

K

MAG

13.7

S-Parameters (VEE =-5 0 Vdc TA = 25°C C2 and C15 = 100 pF)
Frequency

InputS11

ForwardS21

RevS12

OutputS22

MHz

MAG

ANG

MAG

ANG

MAG

ANG

MAG

ANG

MAG

dB

1.0

0.98

-15

11.7

174

0.001

-14

0.84

-27

1.2

37.4

2.0

0.50

-2.0

39.2

85.5

0.001

-108

0.62

-35

6.0

35.5

5.0

0.87

8.0

39.9

19

0.001

100

0.47

-9.0

4.2

39.2

7.0

0.90

5.0

40.4

9.0

0.001

-40

0.45

-8.0

3.1

40.3

10

0.92

3.0

41

1.0

0.001

-40

0.44

-5.0

2.4

41.8

20

0.92

-2.0

42.4

-14

0.001

-87

0.49

-6.0

2.4

41.9

50

0.91

-8.0

41.2

-45

0.001

85

0.50

-5.0

2.3

42

70

0.91

-11

39.1

-63

0.001

76

0.52

-4.0

2.2

41.6
43.6

100

0.91

-15

43.4

-84

0.001

85

0.50

-11

1.3

150

0.90

-22

38.2

-126

0.001

96

0.43

-22

1.4

41.8

200

0.86

-33

35.5

-160

0.002

78

0.43

-21

1.3

39.4

500

0.80

-66

8.3

-9.0

0.012

75

0.57

-63

1.7

23.5

700

0.62

-96

2.9

-95

0.013

50

0.49

-111

6.3

12.5

900

0.56

-120

1.0

-171

0.020

53

0.44

-150

13.3

2.8

1000

0.54

-136

0.69

154

0.034

65

0.44

-179

12.5

-0.8

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
8-149

--

MC13155
S-Parameters (VEE = - 5 0 Vdc TA = 25°C C2 and C15 = 680 pF)
K

MAG

MHz

MAG

ANG

MAG

ANG

MAG

ANG

MAG

ANG

MAG

dB

1.0

0.74

4.0

53.6

110

0.001

101

0.97

-35

0.58

-

2.0

0.90

3.0

70.8

55

0.001

60

0.68

-34

1.4

45.6

5.0

0.91

0

87.1

21

0.001

-121

0.33

-60

1.1

49

7.0

0.91

0

90.3

11

0.001

-18

0.25

-67

1.2

48.4

Frequency

Input 511

Output 522

Rev 512

Forward 521

10

0.91

-2.0

92.4

2.0

0.001

33

0.14

-67

1.5

47.5

20

0.91

-4.0

95.5

-16

0.001

63

0.12

-15

1.3

48.2

50

0.90

-8.0

89.7

-50

0.001

-43

0.24

26

1.8

46.5

70

0.90

-10

82.6

-70

0.001

92

0.33

21

1.4

47.4

100

0.91

-14

77.12

-93

0.001

23

0.42

-1.0

1.05

49

150

0.94

-20

62.0

-122

0.001

96

0.42

-22

0.54
0.75

-

200

0.95

-33

56.9

-148

0.003

146

0.33

-62

500

0.82

-63

12.3

-12

0.007

79

0.44

-67

1.8

26.9

700

0.66

-98

3.8

-107

0.014

84

0.40

-115

4.8

14.6

900

0.56

-122

1.3

177

0.028

78

0.39

-166

8.0

4.7

1000

0.54

-139

0.87

141

0.048

76

0.41

165

7.4

0.96

K

MAG

S-Parameters (VEE = - 3.0 Vdc, TA = 25°C, C2 and C15 = 0 pF)
Frequency

Input 511

Rev 512

Forward 521

Output 522

MHz

MAG

ANG

MAG

ANG

MAG

ANG

MAG

ANG

MAG

dB

1.0

0.89

-14

9.3

136

0.001

2.0

0.84

-27

3.2

30.7

2.0

0.76

-22

24.2

105

0.001

-90

0.67

-37

3.5

34.3

5.0

0.52

5.0

35.7

46

0.001

-32

0.40

-13

10.6

33.3

7.0

0.59

12

38.1

34

0.001

-41

0.40

-10

9.1

34.6

10

0.78

15

37.2

16

0.001

-92

0.40

-1.0

5.7

36.3

20

0.95

5.0

38.2

-9.0

0.001

47

0.51

-4.0

0.94

-

50

0.96

-11

39.1

-50

0.001

-103

0.48

-6.0

1.4

43.7

70

0.93

-17

36.8

-71

0.001

-76

0.52

-13

2.2

41.4

100

0.91

-25

34.7

-99

0.001

-152

0.51

-19

3.0

39.0

150

0.86

-37

33.8

-143

0.001

53

0.49

-34

1.7

39.1

200

0.81

-49

27.8

86

0.003

76

0.55

-56

2.4

35.1

500

0.70

-93

6.2

-41

0.015

93

0.40

-110

2.4

19.5

700

0.62

-144

1.9

-133

0.049

56

0.40

-150

3.0

8.25

900

0.39

-176

0.72

125

0.11

-18

0.25

163

5.1

-1.9

1000

0.44

166

0.49

80

0.10

-52

0.33

127

7.5

-4.8

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
8-150

MC13155
S-Parameters (VEE = - 3.0 Vdc, TA = 25'C, C2 and C15 = 100 pF)
Frequency

Input 511

Forward 521

Rev 512

Output 522

K

MAG

MHz

MAG

ANG

MAG

ANG

MAG

ANG

MAG

ANG

MAG

dB

1.0

0.97

-15

11.7

171

0.001

-4.0

0.84

-27

1.4

3S.8

2.0

0.53

2.0

37.1

80

0.001

-91

0.57

-31

S.O

34.8

5.0

0.88

7.0

37.7

18

0.001

-9.0

0.48

-7.0

3.4

39.7

7.0

0.90

5.0

37.7

8.0

0.001

-11

0.49

-7.0

2.3

41

10

0.92

2.0

38.3

1.0

0.001

-59

0.51

-9.0

2.0

41.8
42.5

20

0.92

-2.0

39.6

-15

0.001

29

0.48

-3.0

1.9

50

0.91

-8.0

38.5

-4S

0.001

-21

0.51

-7.0

2.3

41.4

70

0.91

-11

36.1

-64

0.001

49

0.50

-8.0

2.3

40.8
37.8

100

0.91

-15

39.6

-85

0.001

114

0.52

-13

1.7

150

0.89

-22

34.4

-128

0.001

120

0.48

-23

1.6

40.1

200

0.8S

-33

32

-163

0.002

8S

0.40

-26

1.7

37.8

500

0.78

-S4

7.6

-12

0.013

94

0.46

-71

1.9

22.1

700

0.64

-98

2.3

-102

0.027

58

0.42

-109

4.1

10.1

900

0.54

-122

0.78

179

0.040

38.6

0.35

-147

10.0

-0.14

1000

0.53

-136

0.47

144

0.043

23

0.38

-171

15.4

-4.52

K

MAG

S-Parameters (VEE =-3 0 Vdc TA = 25'C C2 and C15 = 680 pF)
Frequency

Input 511

Rev 512

Forward 521

OutputS22

MHz

MAG

ANG

MAG

ANG

MAG

ANG

MAG

ANG

MAG

dB

1.0

0.81

3.0

37

101

0.001

-19

0.90

-32

1.1

43.5

-

2.0

0.90

2.0

47.8

52.7

0.001

-82

0.66

-39

0.72

5.0

0.91

0

58.9

20

0.001

104

0.37

-56

2.3

44

7.0

0.90

-1

60.3

11

0.001

-76

0.26

-55

2.04

44

10

0.91

-2.0

61.8

3.0

0.001

105

0.18

-52

2.2

43.9

20

0.91

-4.0

63.8

-15

0.001

59

0.11

-13

2.0

44.1

50

0.90

-8.0

60.0

-48

0.001

96

0.22

33

2.3

43.7

70

0.90

-11

56.5

-67

0.001

113

0.29

15

2.3

43.2

100

0.91

-14

52.7

-91

0.001

177

0.36

5.0

2.0

43

150

0.93

-21

44.5

-126

0.001

155

0.35

-17

1.8

42.7
34.1

200

0.90

-43

41.2

-162

0.003

144

0.17

-31

1.6

500

0.79

-65

7.3

-13

0.008

80

0.44

-75

3.0

22

700

0.65

-97

2.3

-107

0.016

86

0.38

-124

7.1

10.2

900

0.56

-122

0.80

174

0.031

73

0.38

-174

12

0.37

1000

0.55

-139

0.52

137

0.50

71

0.41

157

11.3

-3.4

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
8-151

MC13155
DC Biasing Considerations
The DC biasing scheme utilizes two VCC connections
(Pins 3 and 6) and two VEE connections (Pins 14 and 11).
VEE1 (Pin 14) is connected internally to the IF and RSSI
circuits' negative supply bus while VEE2 (Pin 11) is connected
internally to the quadrature detector's negative bus. Under
positive ground operation, this unique configuration offers the
ability to bias the RSSI and IF separately from the quadrature
detector. When two ICs are cascaded as shown in the 70
MHz application circuit and provided by the PCB (see Figures
17 and 18), the first MC13155 is used without biasing its
quadrature detector, thereby saving approximately 3.0 mAo A
total current of 7.0 mA is used to fully bias each IC, thus the
total current in the application circuit is approximately 11 mAo
Both VCC pins are biased by the same supply. VCC1 (Pin 3) is
connected internally to the positive bus of the first half of the
IF limiting amplifier, while VCC2 is internally connected to the
positive bus of the RSSI, the quadrature detector circuit, and
the second half of the IF limiting amplifier (see Figure 15).
This distribution of the VCC enhances the stability of the IC.
RSSI Circuitry
The RSSI circuitry provides typically 35 dB of linear
dynamic range and its output voltage swing is adjusted by
selection of the resistor from pin 12 to VEE. The RSSI slope is

typically 2.1 !1AIdB ; thus, for a dynamic range of 35 dB, the
current output is approximately 74 IJA. A 47 k resistor will
yield a RSSI output voltage swing of 3.5 Vdc. The RSSI buffer
output at Pin 13 is an emitter-follower and needs an external
emitter resistor of 10k to VEE.
in a cascaded configuration (see circuit application in
Figure 16), only one of the RSSI Buffer outputs (Pin 13) is
used; the RSSI outputs (Pin 12 of each IC) are tied together
and the one closest to the VEE supply trace is decoupled
to VCC ground. The two pins are connected to VEE through
a 47 k resistor. This resistor sources a RSSI current which
is proportional to the signal level at the IF input; typically,
1.0 mVrms (-47 dBm) is required to place the MC13155
into limiting. The measured RSSI output voltage response
of the application circuit is shown in Figure 12. Since the
RSSI current output is dependent upon the input signal level
at the IF input, a careful accounting of filter losses, matching
and other losses and gains must be made in the entire
receiver system. In the block diagram of the application
circuit shown below, an accounting of the signal levels at
points throughout the system shows how the RSSI
response in Figure 12 is justified.

Block Diagram of 70 MHz Video Receiver Application Circuit
Input

- 57 dB
31611Vms

Level:

- B2dBm
lBI1Vms

-72dBm
56 11Vms

Inp~~fT

J--L:y!:~~

:r:
-

-25dB
(Insertion Loss)

Transformer
10 dB

- 32dBm
5.611Vms

- 47 dBm 1.0 mVms

Minimum Inputto Acquire
Umiting in MC13155

10 t-..,.-'W'.,....,--JH 16

16
MC13155

'---4"""0"""dB:-G:-81""·n-----'

Cascading Stages
The limiting IF output is pinned-out differentially,
cascading is easily achieved by AC coupling stage to
stage. In the evaluation PCB, AC coupling is shown,
however, interstage filtering may be desirable in some
applications. In which case, the S-parameters provide a
means to implement a low loss interstage match and better
receiver sensitivity.
Where a linear response of the RSSI output is desired
when cascading the ICs, it is necessary to provide at least
10 dB of interstage loss. Figure 12 shows the RSSI response
with and without interstage loss. A 15 dB resistive attenuator
is an inexpensive way to linearize the RSSI response. This
has its drawbacks since it is a wideband noise source that is
dependent upon the source and load impedance and the
amount of attenuation that it provides. A better, although
more costly, solution would be a bandpass filter designed to
the desired center frequency and bandpass response while

MC13155

-15dB
(Attenualor)

carefully selecting the insertion loss. A network topology
shown below may be used to provide a bandpass response
with the desired insertion loss.
Network Topology

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
8-152

40 dB Gain

tOn

tOn

MC13155
Quadrature Detector
The quadrature detector is coupled to the IF with internal
2.0 pF capacitors between Pins 7 and 8 and Pins 9 and 10.
For wide band data applications, such as FM video and
satellite receivers, the drive to the detector can be increased
with additional external capacitors between these pins, thus,
the recovered video signal level output is increased for a
given bandwidth (see Figure 11 A and Figure 11 B).
The wide band performance of the detector is controlled by
the loaded Q of the LC tank circuit. The following equation
defines the components which set the detector circuit's
bandwidth:
Q = RT/XL
(1)
where: RT is the equivalent shunt resistance across the LC
Tank and XL is the reactance of the quadrature inductor at the
IF frequency (XL = 21tfL).
The inductor and capacitor are chosen to form a resonant
LC Tank with the PCB and parasitic device capacitance at the
desired IF center frequency as predicted by:
fc = (21t --i(LC p)) -1
(2)
where: L is the parallel tank inductor and Cp is the equivalent
parallel capacitance of the parallel resonant tank circuit.
The following is a design example for a wide band
detector at 70 MHz and a loaded Q of 5. The loaded Q of
the quadrature detector is chosen somewhat less than the
Q of the IF bandpass. For an IF frequency of 70 MHz and
an IF bandpass of 10.9 MHz, the IF bandpass Q is
approximately 6.4.
Example:
Let the external Cext = 20 pF. (The minimum value here
should be greater than 15 pF making it greater than the
internal device and PCB parasitic capacitance, Cint = 3.0 pF).
C p = Cint + Cext = 23 pF
Rewrite Equation 2 and solve for L:
L = (0.159)2 /(Cp fc 2)
L = 198 nH, thus, a standard value is chosen.
L = 0.22 IJ.H (tunable shielded inductor).

The value of the total damping resistor to obtain the
required loaded Q of 5 can be calculated by rearranging
Equation 1:
RT= Q(21tfL)
RT = 5 (21t)(70)(0.22) = 483.8 Q.
The internal resistance, Rint between the quadrature tank
Pins 8 and 9 is approximately 3200 Q and is considered in
determining the external resistance, Rext which is
calculated from:
Rext = ((RT)(Rint))/ (Rint - RT)
Rext = 570, thus, choose the standard value.
Rext =560 Q.
SAW Filter
In wide band video data applications, the IF occupied
bandwidth may be several MHz wide. A good rule of thumb is
to choose the IF frequency about 10 or more times greater
than the IF occupied bandwidth. The IF bandpass filter is a
SAW filter in video data applications where a very selective
response is needed (i.e., very sharp bandpass response).
The evaluation PCB is laid out to accommodate two SAW
filter package types: 1) A five-leaded plastic SIP package.
Recommended part numbers are Siemens X6950M which
operates at 70 MHz; 10.4 MHz 3 dB passband, X6951 M
(X252.8) which operates at 70 MHz; 9.2 MHz 3 dB passband;
and X6958M which operates at 70 MHz, 6.3 MHz 3 dB
passband, and 2) A four-leaded TO-39 metal can package.
Typical insertion loss in a wide bandpass SAW filter is 25 dB.
The above SAW filters require source and load
impedances of 50 Q to assure stable operation. On the PC
board layout, space is provided to add a matching network,
such as a 1:4 surface mount transformer between the SAW
filter output and the input to the MC 13155. A 1 :4 transformer,
made by Coilcraft and Mini Circuits, provides a suitable
interface (see Figures 16, 17 and 18). In the circuit and
layout, the SAW filter and the MC13155 are differentially
configured with interconnect traces which are equal in length
and symmetrical. This balanced feed enhances RF stability,
phase linearity, and noise performance.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

8-153

Figure 15. Simplified Internal Circuit Schematic

~~

J

r"'

Decouple

s::

~

~

~

2

13

o

J

r

Z
m

>

....

~

Z

-I

~

lOp

.:.. m
:II
~

r--zn

m

<

a
m

UMOul

Vce

7

6

B

...

J ~ ~ >-

J
~4

B.Ok

om

a
'"o

9

D,

>

01
..,.

~

RSS RSSI
I

:II

0>

Quad Coil

UMOul
10

VCCl
3

12

B.Ok
1.0k

1.0k

~>

o
~
:l>

~~ ~~

~

Input

Input

0 j

~$

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~

~~

~

~~

1
VEEl

2.0p

2.0p

"

"

~f3

i:

o

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l
~~

~
.2i~

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-

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L Del

r

>---

K>

~~3

~

~

~

~

VEE2

) Out

~

Co)
~

U1
U1

MC13155
Figure 16. 70 MHz Video Receiver Application Circuit

If Input

SAW Filter is Siemens
Part Number X6950M

RSSI
Output

10k

47k

~ lOOn

lOOn

Detector
Output

t~~__~~__3_3P~lN·Ok~ ~
__

1OOn

~ 33p

1.0k

1--__._-----------..-oVEE2
10/!¥

560
20p

i:'=I L

-=--_---1

,..J..

' - -_ _-1.- ,

1

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L ___ ..,J

L- Coilcraft part number 146-OBJ08S

0.22/!

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

8-155

MC13155
Figure 17. Component Placement (Circuit Side)

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Figure 18. Component Placement (Ground Side)

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
8-156

MC13155
Figure 19. Circuit Side View

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4.0"

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4.0"

Figure 20. Ground Side View

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

8-157

-I

MOTOROLA

SEMICONDUCTOR _ _ _ __

MC13156

TECHNICAL DATA

Product Preview
Wideband FM IF System
The MC13156 is a wideband FM IF subsystem targeted at high
performance data and analog applications. Excellent high frequency
performance is achieved, with low cost, through use of Motorola's
MOSAIC 1.5™ RF bipolar process. The MC13156 has an onboard
Colpitts VCO for PLL controlled multichannel operation. The mixer is
useful to beyond 200 MHz and may be used in a differential, balanced,
or single-ended configuration. The IF amplifier is split to accommodate
two low cost cascaded filters. RSSI output is derived by summing the
output of both IF sections. A precision data shaper has a hold function
to preset the shaper for fast recovery of new data.
Applications for the MC13156 include CT-2, wideband data links,
and other radio systems utilizing GMSK, FSK or FM modulation.

WIDEBAND FM IF SYSTEM
for DIGITAL and
ANALOG APPLICATIONS
SILICON MONOLITHIC
INTEGRATED CIRCUIT

• 3.0 to 6.0 Vdc Operation

DWSUFFIX
PLASTIC PACKAGE
CASE 751E
(SO-24L)

• Typical Sensitivity at 200 MHz of 6.0 flV for 12 dB SINAD
• RSSI Range 01>70 dB
• High Performance Data Shaper for Enhanced CT-2 Operation
• Internal 330 Q Termination for 10.7 MHz Filters
• Split IF for Improved Filtering and Extended RSSI Range

ORDERING INFORMATION

• 3rd Order Intercept (Input) Target of -1 0 dBm

Pin Connections and Block Diagram
LO

Emit

CAR
Del

OS
Gnd

RSSI

OS
In

Demod

5.0pF

MOTOROLA LlNEARIiNTERFACE ICs DEVICE DATA
8-158

MOTOROLA

MC13173

SEMICONDUCTOR----TECHNICAL DATA

Product Preview
Infrared Integrated
Transceiver System

INFRARED INTEGRATED
TRANSCEIVER SYSTEM

The MCt3173 is a low power integrated infrared (IR) transceiver
system. It is a unique blend of a split IF wideband FM receiver and a
specialized infrared LED transmitter. This device was designed to
provide communications between portable computers via a half-duplex
infrared link. It is capable of data rates over 40 kbps.
The receiver includes a mixer, IF amplifier and limiter, and data slicer.
The IF amplifier is split to accommodate two low cost cascaded filters.
The RSSI output is derived by summing the output of both IF sections.
The transmitter section includes a frequency synthesizer, FSK
modulator, harmonic low-pass filter and an IR LED driver.

StLiCON MONOLITHIC
INTEGRATED CIRCUIT

• Transmitter Operates in Two Modes:
On/Off Pulsing for Remote Control
FSK Modulation at 1.4 MHz for Data Communications
• Over 70 dB of RSSI Range

FUSUFFtX

• Split IF for Improved Filtering and Extended RSSI Range

PLASTIC OFP PACKAGE
CASE 873

• Digitally Controlled Via a Six Line Interface Bus
• Individual Circuit Blocks can be Powered Down when not
in Use for Power Conservation

ORDERING INFORMATION
Temperature
Range

Package

- 40' 10 + 85'C

32 Pin OFP

Device
MC13173FU

MC13173 Pin Out/Simplified Block Diagram
Ma
PLL

Tx 14MHz
PLL Ref

T

E

IR LED
Driver

LED Driver
Feedback

12M
VEEI

VEE3

R

Data Out

RFlnl

VEE2

RFln2

Dala
Slicer In

Mixer
Out

Dernod

VCCI

Quad Coil
Carrier
Detect

IF In

IF
Decl

IF VCC2
Out

Urn
In

Urn Urn RSSI
Decl Dec2

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

8-159

MOTOROLA

MC13175
MC13176

SEMICONDUCTOR-----TECHNICAL DATA

Advance Information
UHF FM/AM
TRANSMITIER

UHF FMIAM Transmitter
The MC13175 and MC13176 are one chip FMfAM transmitter subsystems
designed for AMfFM communication systems. They include a Colpitts crystal
reference oscillator, UHF oscillator, + 8 (MCI3175) or + 32 (MCI3176)
prescaler and phase detector forming a versatile PLL system. Targeted
applications are in the 260 to 470 MHz band and 902 to 928 MHz band covered
by FCC ntle 47; Part 15. Other applications include local oscillator sources in
UHF and 900 MHz receivers, UHF and 900 MHz video transmitters, RF Local
Area Networks (LANs), and high frequency clock drivers. The MC13175f76
offer the following features:

SILICON MONOLITHIC
INTEGRATED CIRCUIT

• UHF Current Controlled Oscillator
• Uses Easily Available 3rd Overtone or Fundamental Crystals for
Reference
• Fewer External Parts Required
• Low Operating Supply Voltage (1.8 to 5.0 Vdc)
• Low Supply Drain Currents
• Power Output Adjustable (Up to + 10 dBm)

o SUFFIX
PLASTIC PACKAGE
CASE 751B
(50-16)

• Differential Output for Loop Antenna or Balun Transformer Networks
• Power Down Feature
• ASK Modulated by Switching Output On and Off
• (MCI3175) fo

= 8 x fref; (MCI3176) fo = 32 x fref

Figure 1. Typical Application as 320 MHz AM Transmitter
AM Modulator

1.3k

PIN CONNECTIONS

s,
Coilcrafl
150-0SJ08

Osc
1

Imod
Out

N

e
N
e
s,

Gnd

Out 2

Ose
4

Out 1

VEE

Vee
Enable

MCI3175-30p
MCI3176-1BOp
e~S1al

NOTES: 1. 50

~t

0.82"
MC13175

3rdOvertone
40.0000 MHz

1.0k~

1

Oo;;;--I

(3)

Me13176

e"",~

PDout

Reg.
Gnd

Xtale

Xtalb

I

..L

Fundamental_
10MHz

•

Vee

coaxial balun, 1/10 wavelength at 320 MHz equals 1.5 inches.
2. Pins 5,10 & 15 are ground and connected to VEE which islhe component/DC ground plane side of
PCB. These pins must be decoupled to Vee: decoupling capacitors should be placed as close as

ORDERING INFORMATION

Q

possible to the pins.

3. The crystal oscillator circuit may be adjusted for frequency with the variable inductor (MC1317S);
recommended source is Coilcraft ~slot seven" 7mm tuneable inductor, Part #7M3-821. 1.0k resistor.
Shunting the crystal prevents it from oscillating in the fundamental mode.

Device
MC13175D
MC13176D

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
8-160

Temperature
Range

- 40' to +85'C

Package
50-16
50-16

MC13175, MC13176
MAXIMUM RATINGS (TA = 25°C, unless otherwise noted.)
Symbol

Value

Unit

Power Supply Voltage

VCC

7.0 (max)

Vdc

Operating Supply Voltage Range

VCC

1.8 to 5.0

Vdc

Junction Temperature

TJ

+150

°c

Operating Ambient Temperature

TA

-40 to + 85

°c

Tstg

- 65 to +150

°c

Rating

Storage Temperature

ELECTRICAL CHARACTERISTICS (Figure 2; VEE = - 3.0 Vdc, TA = 25°C, unless otherwise noted.)"
Characteristic
Supply Current (Power down: 111 & 116=0)

Ptn

Symbol

Min

Typ

-

IEEl

-0.5

-

IEE2

-18

-14

IEE3

-39

-34

-

Supply Current (Enable [Pin 11] to VCC thru 30 k, 116 = 0)
Total Supply Current (Transmit Mode)
(Imod = 2.0 mA; 10 = 320 MHz)
Differential Output Power (fa = 320 MHz; Vref [Pin 9]
= 500 mVp _p ; fa = N x fref)
Imod = 2.0 mA (see Figure 7, 8)
Imod =0 mA

13 & 14

Hold-in Range (± dfref x N)
MC13175 (see Figure 7)
MC13176 (see Figure 8)

13 & 14

7

-

+4.7
-45

3.5
4.0

6.5
8.0

20
22

25
27

-

4.0

±MH

tenable
BWAM

Spurious Outputs (Imod = 2.0 mAl
Spurious Outputs (Imod = 0 mAl

13& 14
13& 14

Pson
Psoff

-

Maximum Divider Input Frequency
Maximum Output Frequency

13 & 14

fdiv
fa

-

* For testing purposes,

-

25
-50
-50

-

950
950

RFoutl
VEE
(1)

r--+V""'" I,eg. enable

0.01;- - - -

~l'+

082

. ~
1.0k~

3
()

10MHz

NOTES: 1. Vee is ground; while VEE is negative with respect to ground.
2. Pins 5, 10 and 15 are brought to the circuit side of the PCB via plated through holes. They are
connected together with a trace on the PCB and each Pin is decoupled to Vee (ground).
3, Recommended source is Coilcraft "slot seven" inductor, part number 7M3·821.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

8-161

"l

MC13176 I
Crystal
~
Fundamental VCC

-

-

Figure 2. 320 MHz Test Circuit

MC13175
Crystal
3rd Overtone
40 MHz

rnA

MHz

-

Vee is ground (see Figure 2).

MC13175-30p
MC13176-33p

~A

rnA

-

'error

16

Amplitude Modulation Bandwidth (see Figure 24)

Unit

dBm

11,8

Oscillator Enable Time (see Figure 22b)

-

Pout
2.0

Phase Detector Output Error Current
MC13175
MC13176

Max

-

~

ms
MHz
dBc
MHz

MC13175, MC13176
PIN DESCRIPTIONS
Pin

Symbol

1&4

Osc 1,
Osc4

Internal Equivalent
Circuit

~e

J'"

10k
1
Osc 1

10k
4
Osc 4

~
~

~
+

5

Description/External
Circuit Requirements

VEE

CCOlnputs
The oscillator is a current controlled type. An external oscillator
coil is connected to Pins 1 and 4 which forms a parallel resonance
LC tank circuit with the internal capacitance of the
IC and with parasitic capacitance of the PC board. Three
base-emitter capacitances in series configuration form the
capacitance for the parallel tank. These are the base-emitters
at Pins 1 and 4 and the base-emitter of the differential amplifier.
The equivalent series capacitance in the differential amplifier is
varied by the modulating current from the frequency control circuit
(see Pin 6, internal circuit). A more thorough discussion
is found in the Applications Information section.

Supply Ground (VEE)
In the PCB layout, the ground pins (also applies to Pins 10 and
IS) should be connected directly to chassis ground. Decoupling
capacitors to VCC should be placed directly at
the ground returns.

VEE
5

,,;l- ~
VEE ~

6

ICont

Frequency Control
For VCC =3.0 Vdc, the voltage at Pin 6 is approximately 1.55 Vdc.
The oscillator is current controlled by the error current from the
phase detector. This current is amplified to drive the current
source in the oscillator section which controls the frequency of the
oscillator. Figures 9 and 10 show the Mosc versus ICont, Figure 5
shows the "fosc versus ICont at- 40'C, + 25'C and + 85'C for320
MHz. The CCO may be FM modulated as shown in Figure 17,
MC13176 320 MHz FM Transmitter. A detailed discussion is found
in the Applications Information section.

Vee

T
Reg

6

-- R
leont

~

7

PDout

Phase Detector Output
The phase detector provides ± 30 ~A to keep the CCO locked at
the desired carrier frequency. The output impedance of the phase
detector is approximately 53 kQ. Under closed loop conditions
there is a DC voltage which is dependent upon the free running
oscillator and the reference oscillator frequencies. Tha circuitry
between Pins 7 and 6 should be selected for adequate loop filtering necessary to stabilize and filter the loop response. Low pass
filtering between Pin 7 and 6 is needed so that the corner frequen·
cy is well below the sum of the divider and the reference oscillator
frequencies, but high enough to allow for fast response to keep
the loop locked. Refer to the Applications Information section regarding loop filtering and FM modulation.

Vee

.or

iTf
r

PDout

7

~

+

8

Vee

Xtale

LK

~
9
8

Xtalb
"

Xtale

8.0krif!

i 1'\
~

-

~t

~

4.0k

~"
~

t

Crystal Oscillator Inputs
The internal reference oscillator is configured as a common
emitter Colpitts. It may be operated with either a fundamental
or overtone crystal depending on the carrier frequency and the
internal prescaler. Crystal oscillator circuits and specifications
of crystals are discussed in detail in the applications section.
With VCC = 3.0 Vdc, the voltage at Pin 8 is approximately 1.8 Vdc
and at Pin 9 is approximately 2.3 Vdc. 500 to 1000 mVp-p should
be present at Pin 9. The Colpitts is biased at 200 ~A; additional
drive may be acquired by increasing the bias to approximately 500
flA. Use 6.2 k from Pin 8 to ground.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

8-162

MC13175, MC13176
PIN DESCRIPTIONS
Internal Equivalent
Circuit

Description/External
Circuit Requirements

Pin

Symbol

9

Xtalb

Vee

Crystal Oscillator Inputs
The internal reference oscillator is configured as a common
emitter Colpitts. It may be operated with either a fundamental
or overtone crystal depending on the carrier frequency and the
internal prescaler. Crystal oscillator circuits and specifications
of crystals are discussed in detail in the applications section.
With VCC = 3.0 Vdc, the voltage at Pin 8 is approximately 1.8 Vdc
and at Pin 9 is approximately 2.3 Vdc. 500 to 1000 mVp-p should
be present at Pin 9. The Colpitts is biased at 200 !lA; additional
drive may be acquired by increasing the bias to approximately 500
!lA. Use 6.2 k from Pin 8 to ground.

10

Reg. Gnd

Vee

Regulator Ground
An additional ground pin is provided to enhance the stability of the
system. Decoupling to the VCC (RF ground) is essential; it should
be done at the ground return for Pin 10.
Reg

11

Device Enable
The potential at Pin 11 is approximately 1.25 Vdc. When Pin 11
is open, the transmitter is disabled in a power down mode and
draws less than 1.0 IlA ICC if the MOD at Pin 16 is also open (i.e.,
it has no current driving it). To enable the transmitter a current
source of 10 IlA to 90 !lA is provided. Figures 3 and 4 show the
relationship between ICC, VCC and lreg. enable. Note that ICC is flat
at approximately 10 mA for Ireg . enable = 5.0 to 100 IlA (Imod = 0).

Enable

Supply Voltage (V CC)
The operating supply voltage range is from 1.8 Vdc to 5.0 Vdc. In
the PCB layout, the VCC trace must be kept as wide as possible to
minimize inductive reactances along the trace; it is best to have it
completely fill around the surface mount components and traces
on the circuit side of the PCB.
Differential Output
The output is configured differentially to easily drive a loop
antenna. By using a transformer or balun, as shown in the
application schematic, the device may then drive an unbalanced
low impedance load. Figure 6 shows how much the Output Power
and Free-Running Oscillator Frequency change with temperature
at 3.0 Vdc; lmod = 2.0 mAo
Output Ground
This additional ground pin provides direct access for the output
ground to the circuit board VEE.

16

AM Modulation/Power Output Level
The DC voltage at this pin is 0.8 Vdc with the current source active. An external resistor is chosen to provide a source current of
1.0 to 3.0 mA, depending on the desired output power level at a
given VCC. Figure 23 shows the relationship of Power Output to
Modulation Current, Imod. At VCC = 3.0 Vdc, 3.5 dBm power output
can be acquired with about 35 mA ICC.
For FM modulation, Pin 16 is used to set the desired output power
level as described above.
For AM modulation, the modulation signal must ride on a positive
DC bias offset which sets a static (modulation off) modulation
current. External Circuitry for various schemes is further discussed
in the Applications Information section.

Imod

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
8-163

MC13175, MC13176
Figure 3. Supply Current
versus Supply Voltage

,.....r-

10

:;;:

.s

I

I

I:z 8.0
w
a:
a:
::>
u 6.0

Figure 4. Supply Current versus
Regulator Enable Current

-

100

:;;:

.s

Ireg. enable = 90 rlA
Imod = 0

I-

:z
w
a:
::>
u
10

~

0..
0..

::>

en

~

0..
0..

4.0

::>

en

U

u

!:? 2.0

!:?

I

./

o
o

1.0

2.0
3.0
VCC, SUPPLY VOLTAGE (Vde)

4.0

1.0
0.1

5.0

Figure 5. Change Oscillator Frequency
versus Oscillator Control Current
;;§..

~+5.0

w

::>

ow

fE

a:

o
t<'
::i - 5
o

VCC= 3.0Vdc
Imod = 2.0 rnA
f = 320 MHz (ICont = 0; TA = 25°C)
~ee.Running Oscillator

""0-::"
.....

0

U -10

~ ..............
........
1'....1'....
........,
............

.9


o

Figure 8. MC13176 Reference Oscillator
Frequency versus Phase Detector Current

"N

I
~

_

:I:

r

-10
0
10
20
17, PHASE DETECTOR CURRENT (rlA)

1000

5.5
Ilfose

+1.0

~C3
u

Closed Loop Response:
VCC = 3.0Vdc
fa = 8.0 x fref
Vref = 500 mVp-p

\1\

::>
0

.p -3.0

- 20
40
60
20
ICont, OSC!LLATOR CONTROL CURRENT (rlA)

\\

+ 3.0

:z
w + 2.0

en

25°C

Figure 7. MC13175 Reference Oscillator
Frequency versus Phase Detector Current

"N

:I:

>u

0

- 40
°C

........

1.0
10
100
Ireg . enable, REGULATOR ENABLE CURRENT (rlA)

"N + 4.0

:I:

;;§..

w
c:
u.
a:

............

......

I

Figure 6. Change in Oscillator Frequency and
Output Power versus Ambient Temperature

N +10

:I:

~

VCC = 3.0Vdc
Imod =0

c:

rP

MC13175, MC13176

Figure 10. Change in Oscillator Frequency
versus Oscillator Control Current

Figure 9. Change in Oscillator Frequency
versus Oscillator Control Current
~
~

20

~

10

z

w

::>

~

u..

~

-10

~
13

-20

'"o
&l - 30

o


r---

ow

..i

\

\.

a:

u..

-

~ -10

~

i'-..

13 -20

I--t---

VCC=3.0Vde
Imod = 2.0 rnA
TA=25'C
fose (ICont @ 0) 450 MHz

'"o

0-30

en

~

r---

r--

o


~
w

<>

....

9.8

i'ii

i'

~ 9.6
w
a:
.;. 9.4

_E -150

~oo

-W

0

W

100

16, OSCILLATOR CONTROL CURRENT (~)

Lock-in Range/Capture Range
If a signal is applied to the loop not equal to free running
frequency, ff, then the loop will capture or lock-in the signal
by making fs = fo (i.e. if the initial frequency difference is
not too great). The lock-in range can be expressed as ,lOll
- ± 2()Oln

FM Modulation
Noise external to the loop (phase detector input) is
minimized by narrowing the bandwidth. This noise is minimal
in a Pll system since the reference frequency is usually
derived from a crystal oscillator. FM can be achieved by
applying a modulation current superimposed on the control
current of the CCO. The loop bandwidth must be narrow
enough to prevent the loop from responding to the
modulation frequency components, thus, allowing the CCO
to deviate in frequency. The loop bandwidth is related to the
natural frequency Oln. In the lag-lead design example where
the natural frequency, Oln = 5.0 krad/sec and a damping
factor, () = 0.707, the loop bandwidth = 1.64 kHz.
Characterization data of the closed loop responses for both
the MC13175 and MC13176 at 320 MHz (Figures 7 and 8,
respectively) show satisfactory performance using only a
simple low-pass loop filter network. The loop filter response
is strongly influenced by the high output impedance of the
push-pull current output of the phase detector.

fc

=

0.159/RC;

For R = 1.0 k + R7 (R7 = 53 k) and C = 390 pF
fc

= 7.55 kHz or OlC = 47 krad/sec

The application example in Figure 17a of a 320 MHz FM
transmitter demonstrates the FM capabilities of the IC. A high
value series resistor (100 k) to Pin 6 sets up the current
source to drive the modulation section of the chip. Its value is
dependent on the peak to peak level of the encoding data
and the maximum desired frequency deviation. The data
input is AC coupled with a large coupling capacitor which is
selected for the modulating frequency. The component
placements on the circuit side and ground side of the PC
board are shown in Figures 28 and 29, respectively. Figure
18a illustrates the input data of a 10kHz modulating signal at
1.6 Vp-p. Figures 18b and 18c depict the deviation and
resulting modulation spectrum showing the carrier null at - 40
dBc. Figure 18d shows the unmodulated carrier power output
at 3.5 dBm for VCC = 3.0 Vdc.
For voice applications using a dynamic or an electret
microphone, an op amp is used to amplify the microphone's
low level output. The microphone amplifier circuit is shown
in Figure 19. Figure 17b shows an application example for
NBFM audio or direct FSK in which the reference crystal
oscillator is modulated.
Figure 19. Microphone Amplifier

VCC

lOOk

Voice>
Input
10k
Electrel
Microphone

Local Oscillator Application
To reduce internal loop noise, a relatively wide loop
bandwidth is needed so that the loop tracks out or cancels
the noise. This is emphasized to reduce inherent CCO and
divider noise or noise produced by mechanical shock and
environmental vibrations. In a local oscillator application the
CCO and divider noise should be reduced by proper
selection of the natural frequency of the loop. Additional low
pass filtering of the output will likely be necessary to reduce
the crystal sideband spurs to a minimal level.

MOTOROLA LlNEAR/INTERFACE ICs DEVICE DATA

8-168

MC13175, MC13176

Figure 17a. 320 MHz MC13176D FM Transmitter
RF Level Adjust

Coilcraft
146-04J08
SM

~RFOulpul

~-"-_ _ _ _-.. 510P.:t

i----'VV'v--\ Vee
130k

Dalalnpul
(1.6Vp-p)

51p

~220P

~51P

~6.8(4)
Crystal
Fundamental (5)1'
10MHz

NOTES: 1.50 Q coaxial balun, 2 inches long.
2. Pins 5, 10 and 15 are grounds and connnected to VEE which is the component's side ground plane. These
pins must be decoupled to Vee; decoupling capacitors should be placed as close as possible to the pins.
3. RFCl is 180 nH Coileraft surface mount inductor or 190 nH Coilcraft 146-05JOa.
4. Recommended source is a Coilcraft "slot seven" 7.0 mm tuneable inductor, part #7M3-682.
5. The crystal is a parallel resonant, fundamental mode calibrated with 32 pF load capacitance.

Figure 17b. 320 MHz NBFM Transmitter

NOTES: 1.50 0 coaxial balun, 2 inches long.

2. Pins 5,10 and 15 are grounds and connnected to VEE which is the component's side ground plane. These
pins must be decoupled to Vce; decoupling capacitors should be placed as close as possible to the pins.
3. RFC1 is 180 nH Coilcraft surface mount inductor.
4. RFC2 and RFC3 are high impedance crystal frequency of 10 MHz; 8.211H molded inductor gives XL > 10000...
5. A single varactor like the MV2105 may be used whereby RFC2 is not needed.
6. The crystal is a parallel resonant, fundamental mode calibrated with 32 pF load capacitance.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

8-169

"' to Antenna

MC13175, MC13176
Figure 18a.lnput Data Waveform

Figure 18b. Frequency Deviation

Figure 18c. Modulation Spectrum

Figure 18d. Unmodulated Carrier

Reference Crystal Oscillator (Pins 8 and 9)
Selection of Proper Crystal: A crystal can operate in a
number of mechanical modes. The lowest resonant
frequency mode is its fundamental while higher order modes
are called overtones. At each mechanical resonance, a
crystal behaves like a RLC series·tuned circuit having a large
inductor and a high Q. The inductor Ls is series resonance
with a dynamic capacitor, Cs determined by the elasticity of
the crystal lattice and a series resistance Rs , which accounts
for the power dissipated in heating the crystal. This series
RLC circuit is in parallel with a static capacitance. C p which
is created by the crystal block and by the metal plates and
leads that make contact with it.
Figure 20 is the equivalent circuit for a crystal in a single
resonant mode. It is assumed that other modes of resonance
are so far off frequency that their effects are negligible.

Figure 20. Crystal Equivalent Circuit

the frequency separation at resonance is given by;

~f =fp-fs

=fs[1 -

(I + CslCp) I 12]

Usuallyfp is less than I % higherthan fs, and acrystal exhibits an
extremely wide variation of the reactance with frequency between fp and fs . A crystal oscillator circuit is very stable with frequency. This high rate of change of impedance with frequency
stabilizes the oscillator, because any significant change in oscillatorfrequency will cause a large phase shift in the feedback
loop keeping the oscillator on frequency.

Series resonant frequency, fs is given by;
fs =1/21t(LsCs )1/2
and parallel resonant frequency, fp is given by;
fp = fs(1 + CslCp) I 12

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

8-170

MC13175, MC13176
Manufacturers specify crystal for either series or parallel
resonant operation. The frequency for the parallel mode is
calibrated with a specified shunt capacitance called a "load
capacitance". The most common value is 30 to 32 pF. If the
load capacitance is placed in series with the crystal, the
equivalent circuit will be series resonance at the specified
parallel-resonant frequency. Frequencies up to 20 MHz use
parallel resonant crystal operating in the fundamental mode,
while above 20 MHz to about 60 MHz, a series resonant
crystal specified and calibrated for operation in the overtone
mode is used.
Application Examples
Two types of crystal oscillator circuits are used in the
applications circuits: 1) Fundamental mode common emitter
Colpitts (Figures 1, 17a, 17b, and 21). 2) Third overtone
impedance inversion Colpitts (also Figures 1 and 21).
The fundamental mode common emitter Colpitts uses a
parallel resonant crystal calibrated with a 32 pf load
capacitance. The capacitance values are chosen to provide
excellent frequency stability and output power of > 500
mVp-p at Pin 9. In Figures 1 and 21, the fundamental mode
reference oscillator is fixed tuned relying on the repeatability
of the crystal and passive network to maintain the frequency,
while in the circuit shown in Figure 17, the oscillator
frequency can be adjusted with the variable inductor for the
precise operating frequency.
The third overtone impedance inversion Colpitts uses
a series resonance crystal with a 25 ppm tolerance. In
the application examples (Figures 1 and 21). the
reference oscillator operates with the third overtone
crystal at 40.0000 MHz. Thus, the MC13175 is operated
at 320 MHz (f0l8 = crystal; 320/8 = 40.0000 MHz. The
resistor across the crystal ensures that the crystal will
operate in the series resonant mode. A tuneable inductor
is used to adjust the oscillation frequency; it forms a
parallel resonant circuit with the series and parallel
combination of the external capacitors forming the divider
and feedback network and the base·emitter capacitance
of the device. If the crystal is shorted, the reference
oscillator should free-run at the frequency dictated by the
parallel resonant LC network.
The reference oscillator can be operated as high as 60
MHz with a third overtone crystal. Therefore, it is
possible to use the MC13175 up to at least 480 MHz and
the MC13176 up to 950 MHz (based on the maximum
capability of the divider network).
Enable (Pin 11)
The enabling resistor at Pin 11 is calculated by:
Rreg. enable = VCC - 1.0 Vdc/l reg . enable

From Figure 4, Ireg. enable is chosen to be 75 flA. So, for a
VCC = 3.0 Vdc Rreg. enable = 26.6 kQ, a standard value 27
kQ resistor is adequate.
Layout Considerations
Supply (Pin 12): In the PCB layout, the VCC trace must
be kept as wide as possible to minimize inductive reactance
along the trace; it is best that VCC (RF ground) completely
fills around the surface mounted components and
interconnect traces on the circuit side of the board. This
technique is demonstrated in the evaluation PC board.
Battery/Selection/Lithium Types
The device may be operated from a 3.0 V lithium battery.
Selection of a suitable battery is important. Because one of
the major problems for long life battery powered equipment
is oxidation of the battery terminals, a battery mounted in a
clip-in socket is not advised. The battery leads or contact
post should be isolated from the air to eliminate oxide
build-up. The battery should have PC board mounting tabs
which can be soldered to the PCB. Consideration should be
given for the peak current capability of the battery. Lithium
batteries have current handling capabilities based on the
composition of the lithium compound, construction and the
battery size. A 1300 mAlhr rating can be achieved in the
cylindrical cell battery. The Rayovac CR2/3A
lithium-manganese dioxide battery is a crimp sealed, spiral
wound 3.0 Vdc, 1300 mAlhr cylindrical cell with PC board
mounting tabs. It is an excellent choice based on capacity
and size (1.358" long by 0.665" in diameter).
Differential Output (Pins 13, 14)
The availability of micro-coaxial cable and small baluns
in surface mount and radial-leaded components allows for
simple interface to the output ports. A loop antenna may be
directly connected with bias via RFC or 50 Q resistors.
Antenna configuration will vary depending on the space
available and the frequency of operation.
AM Modulation (Pin 16)
Amplitude Shift Key: The MC13175 and MC13176 are
designed to accommodate Amplitude Shift Keying (ASK).
ASK modulation is a form of digital modulation corresponding
to AM. The amplitude of the carrier is switched between two
or more values in response to the PCM code. For the binary
case, the usual choice is On-Off Keying (often abbreviated
OOK). The resultant amplitude modulated waveform consists
of RF pulses called marks, representing binary 1 and spaces
representing binary O.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
8-171

MC13175, MC13176
Figure 21. ASK 320 MHz Application Circuit
Rmod
3.3k

~ Input
)

On·Off

mLeve 10kHz
Collcraft
150-05J08

SM
tt- 5.0

o

II:

,I

-10

~... -15
,p
-20

VCC= 3.0Vdc
1= 320 MHz

V
/'"
I"

-25
0.1

1.0
Imod, MODULATION CURRENT (rnA)

10

Analog AM
In analog AM applications, the output amplifier's linearity
must be carefully considered. Figure 23 is a plot of Power
Output versus Modulation Current at 320 MHz, 3.0 Vdc. In
order to achieve a linear encoding of the modulating
sinusoidal waveform on the carrier, the modulating signal
must amplitude modulate the carrier in the linear portion of
its power output response. When using a sinewave
modulating signal, the signal rides on a positive DC offset
called Vmod which sets a static (modulation off) modulation
current, Imod. Imod controls the power output of the IC. As
the modulating signal moves around this static bias point the
modulating current varies causing power output to vary or
to be AM modulated. When the IC is operated at modulation
current levels greater than 2.0 mAdc the differential output
stage starts to saturate.

MOTOROLA LlNEARIiNTERFACE ICs DEVICE DATA
8-173

MC13175, MC13176
In the design example, shown in Figure 24, the operating
point is selected as a tradeoff between average power output
and quality of the AM.
ForVcc =3.0 Vdc; ICC =18.5 mAand Imod =0.5 mAdcand
a static DC offset of 1.04 Vdc, the circuit shown in Figure 24
completes the design. Figures 25a, 25b and 25c show the results of- 6.9 dBm output power and 100% modulation by the
10kHz and 1.0 MHz modulating sinewave signals. The amplitude of the input signals is approximately 800 mVp-p.
Where Rmod = {VCC - 1.04 Vdc)/0.5 mA = 3.92 k, use
a standard value resistor of 3.9 k.

Figure 24. Analog AM Transmitter

1----

~
Vee t--'V';y---...,.--vvv- 16
3.9k

l.04Vdc 560

3.0Vdc Rmod
Data "---------' +
Input~

SOOmVp-p

6.Sft

O.SVdc

I
I
I

Figure 25a. Power Output of Un modulated Carrier

Figure 25c. Input Signal and AM Modulated
Carrier for fmod = 1.0 MHz

Figure 25b. Input Signal and AM Modulated
Carrier for fmod = 10kHz

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

8-174

MC13175, MC13176
Figure 26. Circuit Side View of MC1317XD

. ···1

••••••••••••••••••••••••••••••••••••••
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..........................
......... ,'

••••••••••••••••••••••••••
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••••••••••••••••••••••••

::::::::
•••••••••
•••••••••
•••••••••
•••••••••

.1

.1

:::1
•••••••

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1-·- - - - --------1-1
4"

Figure 27. Ground Side View

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
8-175

4"

MC13175, MC13176
Figure 28. Surface Mounted Components Placement
(on Circuit Side)

Figure 29. Radial Leaded Components Placement
(on Ground Side)

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
8-176

MOTOROLA

SEMICONDUCTOR-----

MC34055

TECHNICAL DATA

Product Preview
ISO 8802-3[IEEE 802.3]

10BASE-T
TRANSCEIVER

1OBASE-T Transceiver
The Motorola 10BASE-T transceiver, designed to comply with the ISO
8802-3 [IEEE 802.3] 10BASE-T specification, will support a Medium
Dependent Interface(MDI) in an embedded Media Attachment Unit(MAU)*.
The interface supporting the Data Terminal Equipment(DTE) is TTL, CMOS,
and raised ECl compatible, and the interface to the Twisted Pair(TP) media is
supported through standard 1OBASE-T filters and transformers. Differential
data intended for the TP media is provided. A 50 ns pre-emphasis and data at
the TP receiver is screened by Smart Squelch circuitry for specific threshold,
pulse width, and sequence requirements.
Other features of the MC34055 include: Collision and Jabber detection
status outputs, select mode pins for forcing loop Back and Full-Duplex
operation, a Signal Quality Error pin for testing the collision detect circuitry
without affecting the TP output, and a lED driver for Link Integrity status. An
on-chip oscillator, capable of receiving a clock input or operating under crystal
control, is also provided for internal timing and driving a buffered clock output.

DWSUFFIX
PLASTIC PACKAGE
CASE 751E

(SO-24l)

PSUFFIX
PLASTIC PACKAGE
CASE 724

_
24

PIN CONNECTIONS

• BiCMOS technology for low Power Operation
• Standard 5.0 V, ± 5% Power Supply
• Smart Squelch Enforcement of Threshold, Pulse Width, and
Sequence Requirements
• Driver Pre-Emphasis for Output Data
• TTL, CMOS and Raised ECl Compatible
• Interfaces to TP Media with Standard 1OBASE-T Filters and Transformers
• Status Outputs for Collision and Jabber Detection
• Directly Driven or Crystal Controlled Clock Oscillator

Clk+

ClkOut

Clk-

SQEEnl

lXPwrGnd

Vee (Di!I'Ana)

Pwrvcc
FullDL
Alb

• Selectable Full-Duplex Operation
• Signal Quality Error Test Pin
• Selectable loop Back

AXEnH

AXCTlH

LNKFLH

JabbH

.. The sale and use of this product Is licensed under technology covered by one or more Digital Equipment Corporation patents.

Simplified Block Diagram

Balun

Pw'Vee

VCCIDigJAn.)

lX.r--------------------o---O-----i
I
TX Data A
lXDaIa.
TXEnH
RXDalaA
RXDataB
AXEnH

CTlH

JabbH

SQEEnL

I

L--o--o--o------Ana
Pwr
Dig
elk +
Gnd

Gnd

Gnd

I

10MHz .;;:.

MOTOROLA LINEAR/INTERFACE ICs DEVICE- DATA
8-177

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
8-178

Addendum
An Introduction to Motorola
RF Communications IC Applications

In Brief ...

Page

The RF devices described in the following chapter are
targeted for the consumer communications market. In
addition, most of these parts are capable of superior
performance in professional and industrial applications.
These devices represent the latest technology in cost
effective RF and audio subsystems for cordless
telephones (CT-I), RF LANs, land mobile radio,
scanners, cellular telephones, remote control spread
spectrum, and amateur radio. The purpose of this
introduction is to help the user explore all the
opportunities presented by this growing family of wireless
communications ICs from Motorola Analog.

Regulatory Issues ............................. 8-180
Industry Standards ........................... . 8-180
Communications Systems ..................... . 8-181
Passive Components

8-181

Component Suppliers

8-182

Breadboarding ................................ 8-182
Test Equipment ............................... 8-183

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
8-179

REGULATORY ISSUES
Each country has its own specific set of regulations regarding radio frequency systems and equipment built
and sold within their jurisdiction. These regulations are strongly applicable to transmitting devices. The
rules are based on both local needs and international treaties. The regulations are established to provide
maximum utilization of the limited available radio spectrum. Motorola strongly recommends that you, the
user of these communication ICs, obtain the applicable regulations and abide by them.
In the United States, the regulations of the Federal Communications Commission are published in the
Code of Federal Regulations (CFR), Title 47, Parts 0 through 99. In the U.S.A. most of the consumer
applications fall under CFR 47, Part 15, covering non licensed intentional radiators, or Part 68 which covers
public network interconnections. CFR 47 may be obtained at most libraries (in the reference section) or
from the U.S. Government Printing Office. You may call their office at (213) 894-5841 , or (202) 274-2054 for
prices and availability. In addition, private contractors such as the Rules Service Company, (301) 424-9402
can provide both the CFR data and an automatic update service. In the U.S.A., further information is
available from the FCC field organization.
For the address and telephone number of the nearest office, contact the FCC at:
FCC CONSUMER OFFICE AND SMALL BUSINESS DIVISION
1919 M STREET WEST
WASHINGTON, D.C. 20554
(202) 632-7000
In other countries, the Ministry of Posts or Telecommunications should be contacted. Motorola
Semiconductor does not warrant that the applications shown in this data book meet all the conditions
prescribed by government regulations.

INDUSTRY STANDARDS
Throughout the world the telecommunications industry has established working standards committees to
ensure equipment compatibility by setting minimum standards. These standards also help make the best
use of the available radio spectrum. In the U.S.A., the Electronic Industries Association (E.I.A.) has
developed a series of these recommended standards which have become the defacto global guidelines.
The following standards apply to Frequency Modulation (FM) systems.
EIAlTIA-204C

EIA STANDARD

FM/PM RECEIVER STANDARDS

EIAlTIA-152B

EIA STANDARD

FM/PM TRANSMITTER STANDARDS

EIAlTIA-316B

EIA STANDARD

TEST CONDITIONS, PORTABLE PERSONAL RADIO

For additional information and priCing, contact the E.I.A. at the following address:
ELECTRONIC INDUSTRIES ASSOCIATION
ENGINEERING DEPARTMENT
2001 EYE STREET N.W.
WASHINGTON, D.C. 20006
(202) 457-4900

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

8-180

COMMUNICATIONS SYSTEMS
For the most part, the devices described in Chapter 8 use frequency modulation (FM ) for both analog
voice and data. FM is generally considered the simplest and most cost efficient modulation type today. FM
offers excellent: noise rejection; good sensitivity; reduction of interference due to the FM capture effect;
simple circuitry; and an array of test equipment, most of which has spun-off the land mobile market. Direct
digital transmission may also be accomplished using Frequency Shift Keying (FSK) or Amplitude Shift
Keying (ASK).
The devices shown in this chapter are designed to operate at frequencies below 1.0 GHz (1000 MHz).
Today, that frequency range offers the best compromise among performance, complexity and cost. Over
the next decade there will be an increasing movement to 1 .0 to 3.0 GHz, as the demand for more complex
personal communications systems comes on-line. Motorola will add products to its line-up as these
microwave applications become better defined.
Several reference books on Communications Theory and Design are listed below. These books are
generally available at major public and university libraries.
THE RADIO AMATEUR'S HANDBOOK, American Radio Relay League, Newington, CT.
MICROWAVE THEORY AND APPLICATIONS, Steven F. Adam, Hewlett Packard, Prentice Hall.
SOLID STATE RADIO ENGINEERING, Herbert L. Krauss, Charles W. Bosdan, F.H. Raab, Wiley 1980.
RF CIRCUIT DESIGN, Chris Bowick, Howard Sams & Co., 1982.
INTRODUCTION TO COMMUNICATIONS SYSTEMS, Ferrel Stremler, Addison Wesley.
ARRL ANTENNA HANDBOOK, American Radio Relay League, Newington, CT.
STANDARD RADIO COMMUNICATIONS MANUAL, R.H. Kinley, CET, Prentice Hall, 1985.
In addition, you may find very timely design and component information in the following magazines:

R.F. DESIGN, Cardiff Publishing (708) 647-0756.
MICROWAVES AND RF, Penton Publishing (216) 696-7000.

PASSIVE COMPONENTS
The availability of passive components - coils, filters, crystals, capacitors, resonators, resistors, etc. - is
often a larger problem than finding the RF or analog IC to meet your needs. The Motorola applications
engineering team considers this a key issue when developing the circuits shown in our data sheets. Analog
Applications has worked with many suppliers to develop practical and reasonably priced passive
component selections. Suppliers who have a global support structure and can supply both prototype and
production quantities are listed. The following table lists a number of suppliers which have been used in
recent applications. You will also need information on the performance of the component as a function of
temperature, frequency, solderability and reliability. Most of these suppliers have applications-engineering
support who can provide a wealth of specific technical information. Motorola, however, cannot warrant
these suppliers' quality, availability, or prices. Motorola suggests contacting these suppliers directly to
obtain technical information and competitive quotes.
In many cases, recommendations have been made to use readily available sources such as "Radio Shack"
for small parts and construction material. The user is encouraged to develop a core of dependable and
local, if possible, suppliers for his or her passive components. Please note that many data sheets have
specific passive components which have been used to develop and characterize the integrated circuit.
Constructing a "benchmark" circuit with these components is an excellent starting point in the development
of a new design.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

8-181

COMPONENT SUPPLIERS
QUARTZ CRYSTALS - FREQUENCY CONTROL:
California Crystal Laboratories
Fox Electronics
International Crystals
Standard Crystal Corporation

(800)
(813)
(405)
(818)

333-9825
693-0099
236-3741
443-2121

GENERAL COMPONENTS - PROTOTYPE QUANTITIES PC BOARD MATERIAL:
Digi-Key Corporation
Radio Shack Division,
Tandy Corporation

ASSEMBLY MATERIAL -

(800) 344-4539
(See local telephone directory)

INDUCTORS, COILS, RF TRANSFORMERS, FIXED AND VARIABLE:
CoilCraft

(800) 322-COIL
(708) 639-6400
(708) 297-0070

Toko America, Inc.

CERAMIC FILTERS AND RESONATORS, IF FILTERS - AM AND FM TYPES:
muRata Erie
TDK Corporation of America
Toko America, Inc.

(404) 436-1300
(708) 803-6100
(708) 297-0070

(Todd Brown, Harry Moore)

BREADBOARDING
Breadboarding RF or other high speed analog circuits can be a very frustrating process for the newcomer
or even an experienced digital deSigner. Most of these circuits deal with very high gain (100+ dB), very
small signals (less than a few microvolts), or with very high frequencies where a wavelength may be a
fraction of a meter. Once "friendly" 0.1 IlF capacitors may now be inductors due to their parasitic
inductance, and conventional construction methods may yield only circuits that oscillate.

What to avoid (never use these):
-

Wire wrap for RF or high frequency breadboards.
Conventional push-in prototype boards.
Digital printed protoboards with ground and power supply bus lines.

What to use:
-

Carefully laid-out double-sided groundplane PC boards.
Grid boards with a background plane.
Single-sided PC layouts with continuous full ground fill.
High frequency qualified components.
Adequate decoupling.

You will find recommended PC layouts for most of the communications circuits in this chapter. These
layouts are strongly recommended as starting points for new designs. They will allow you to develop your
own benchmark standard circuit to be used as a standard of comparison during further design iterations.
Many Motorola communications ICs have supporting development kits which include a PC board. These
boards are meant to provide performance equivalent to the data sheets specifications and are easy to
modify for other uses but these boards, however, are not optimized or intended for production applications.
Contact your Motorola sales office or Motorola distributor for information on the availability of these
development kits.

MOTOROLA LlNEARIiNTERFACE ICs DEVICE DATA
8-182

In addition, there are many PC and Macintosh-based CAD programs available today. In general, these
programs work well for digital and low frequency analog circuits, but are of very limited value in RF
applications. SPICE models are not currently available for the communications circuits. Several circuits do
show S-Parameter data or admittance plane information which may be used to optimize input or output
matching for gain or noise. The most useful method of utilizing the applications circuits at different
frequencies is simple linear scaling of the tuning and reactive elements. This method is generally
applicable over a 2:1 frequency range lower than the documented application.
Many communications applications include some digital signaling, data conversion, or microcontroller
interface. The RF designer must take great caution to avoid interference with the low level analog circuits
in these mixed-mode systems. The receivers are particularly susceptible to noise as they respond to
signals of only a few microvolts. Make sure the clock frequency is not a sub-multiple of the receiver input
or IF frequencies. Keep the DC supply lines for the digital and analog circuitry separate. Avoid ground
paths carrying common digital and analog currents. As much common sense as analytical skill goes
into a successful RF design. A good consultant may well save many times their fee in material, lost time,
and rework.

TEST EQUIPMENT
Establishing a new RF communications lab can be a very costly investment. The normal DVMs and
regulated power supplies are generally acceptable if they do not generate spurious RF, and are not
sensitive to RF voltages. You should pick an oscilloscope with a frequency response three or more times
higher than your operating frequency. In addition, a low capacitance probe - FET probe - would be
useful. Remember, while conventional probes have very high input resistance, their capacitive reactance
decreases with frequency and becomes a limiting factor above 30 MHz. For most transmitter work, a basic
spectrum analyzer is a must. It will help confirm power output, spurious output levels, stability, and
modulation characteristics.
Rental and used equipment are often a good source of test equipment. Recently, Communications System
Analyzers have become available at very moderate prices. The Motorola R2600, for example, combines 16
different instruments into one portable package. The signal generator, receiver, counter, oscilloscope and a
"best-in-class" modulation meter make this package a very attractive design and production test tool.
Further information, including a demonstration, are available from your local Motorola Communications
and Electronics sales office.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

8-183

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

8-184

Consumer Electronic Circuits

In Brief ...
Page

These integrated circuits reflect Motorola's continuing
commitment to semiconductor products necessary for
consumer system designs. This tabulation is arranged to
simplify selection of consumer integrated circuit devices that
satisfy the primary functions for home entertainment
products, including television, hi-fi audio and AMIFM radio.

Entertainment Radio Receiver Circuits

9-2

Video Circuits . . .. . . . .. . . . . . . .. . . . . . . . . . . . . . . . . . .. 9-3
Composite Video Overlay Synchronizer ........... 9-7
Advanced PAUNTSC Encoder .................. 9-8
Multistandard Videommebase Processor ......... 9-9
Digitally Controlled Video Processor ............. 9-10
TV Stereo Decoder for NICAM and
German System ............................ 9-11
Digital Chroma Delay Line ..................... 9-12
Subcarrier Reference.. . . . . .. . . . . . . . . . . . . . . . . .. 9-13
Pixel Clock Generator and Sync Separator .. . . . .. 9-14
Triple 8-Bit D/A Converter ...................... 9-14
Triple 8-Bit ND Converter ...................... 9-15
Multistandard Video IF ......................... 9-16
1.3 GHz Tuner PLL with 12C Control . . . . . . . . . . . .. 9-17
1.3 GHz Tuner PLL with 3-Wire Control .......... 9-18
PLL Tuning Circuit with DACs .................. 9-19
Closed-Caption Decoder. . . . . . . . . . . . . . . . . . . . . .. 9-20
Advanced NTSC Comb Filter. . . . . . . . . . . . . . . . . .. 9-21
Advanced PAUNTSC Comb Filter. . . . . . . . . . . . . .. 9-22
Dual Video Amplifiers ......................... 9-23
Remote Control Circuits ....................... 9-25
Index .......................................... 9-26
Data Sheets .................................... 9-27

Entertainment Radio Receiver Circuits
Entertainment Receiver RFIIF

C-Quam® AM Stereo Decoders

Audio Amplifiers

Audio Attenuator

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

9-2

Video Circuits
Video Circuits
Function

Features

Suffix!
Case

Device

Encoders
RGB to PAUNTSC Encoder

RGB and Sync inputs, Composite Video out; PAUNTSC selectable.

Advanced RGB to PAUNTSC
Encoder

RGB and Sync inputs, Composite Video and S-VHS out;
PAUNTSC selectable; subcarrier from crystal or external source.

P1738
DWI751D

MC1377

P/738

MC13077

DWI751D

Decoders
TV Color Processor

PAUNTSC input, RGB outputs; also RGB inputs, Fast blanking, ideal for
text, graphics, overlay.

PI711

TV Color Processor

PAUNTSC input, RGB outputs

P1724

TDA3330

Chroma 10 Timebase and Color
NTSC/PAL Decoder

PAUNTSC input, RGB outputs; horizontal and vertical timing processors.

PI711

MC13017

Chroma 4 Multistandard Decoder
(TV set)

PAUNTSC/S-VHS input, RGB outputs; horizontal and vertical timing
outputs; all digital internal filters, no external tank; liP and crystal
controlled.

PI711

MC44001

Chroma 4 Multistandard Decoder
(Multimedia)

PAUNTSC/S-VHS input, RGBIYUV outputs; horizontal and vertical
timing outputs; all digital internal filters, no external tanks; liP and
crystal controlled.

FNI777

MC44011

Chroma 4 Multistandard Decoder
(Multimedia)

PAUNTSC/S-VHS input, RGBIYUV outputs; horizontal and vertical
timing outputs; all digital internal filters, no external tanks; liP and
crystal controlled.

FN/777

MC44011

PAL Digital Delay Line

For PAL applications olthe MC44011 and MC44001.

P/648
D1751

MC44140

TDA3301B

Video Capture Chip Set

Pixel Clock PLUSync Sep.

PAUNTSC sync separator, 6-40 MHz pixel clock PLL.

D1751

MC44145

Triple 8-Bit Video DAC

TIL inputs, 75 n drive outputs.

FB/824

MC44200

Triple 8-Bit Video AID

Video clamps for RGBIYUV, 15 MHz, TIL outputs.

FNI777

MC44250

Video clamps for RGBIYUV, 18 MHz, High Z TIL outputs.

FN/777

MC44251

Advanced NTSC Comb Filter

Composite Video input; YC outputs in digital and analog form;
all digital internal filters.

FB/898

MC141621

Advanced PAUNTSC Comb Filter

Composite Video input; YC outputs in digital and analog form;
all digital internal filters.

FB/898

MC141625

Horizontal Processor

Linear balanced phase detector, oscillator and predriver, adjustable
DC loop gain and duty cycle.

P/626

MC1391

Waveform Generator for Monitors

Provides geometry correction by generating 10 waveforms to modulate
deflection circuitry. Supports multifrequency operation.

P/711

MC1388

Line Deflection Transistor Driver

Provides optimum drive control of the power transistor, peak current
limiting, overvoltage and thermal protection.

P/648

MC44614

Waveform Generator for Projection
TV Convergence Function

Provides geometry correction by generating 18 waveforms to modulate
deflection circuitry. Supports multifrequency operation.

PI711

MC44615A

Deflection

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
9-3

Comb Filters
Enhanced Comb Filter

Fast 8-bit ND converter, two 8-Bit D/A Converters, two line-delay
memories, utilizes NTSC subcarrier frequency clock, CMOS technology

FB/898

MC141620

Advanced NTSC Comb Filter

Composite Video input; YC outputs in digital and analog form;
all digital internal filters.

FB/898

MC141621

Advanced PAUNTSC Comb Filter

Composite Video input; YC outputs in digital and analog form; all digital
internal filters.

FB/898

MC141625

P/724
DW1751F

MC44301

IF Circuits
Advanced Video IF

Complete video/audio IF system for high performance analog TV
receivers.

Video Detector

3rd IF, video detector, video buffer and AFC buffer.

P/626

MC1330A

IF Amplifier

1st and 2nd video IF amplifiers, 50 dB gain at 45 MHz, 60 dB AGC range.

D/751
P/626

MC1350

1.3 GHz, 20 mV sensitivity, selectable prescaler, op amp, 7 band buffers,
12C interface.

P/707

MC44802A

P/648

D1751

MC44807
MC44817

1.3 GHz, 10 mV sensitivity, selectable prescaler, op amp, 7 band buffers,
12C interface, 3 DACs.

P1738

MC44810

1.3 GHz, 20 mV sensitivity, prescaler, 3 band buffers, 12C interface,
replacement for Siemens MPG3002.

D1751

MC44824

1.3 GHz, 5.0 mV sensitivity, prescaler, op amp, 4 band buffers, 12C
interface, lock detect.

D1751

MC44818

Tuner PLL Circuits
Pll Tuning Circuits

1 .3 GHz, 5.0 mV sensitivity, selectable prescaler, op amp, 4 band
buffers, SPI interface, lock detect.

Modulators
Color TV Modulator

RF Oscillator and Modulator.

Color TV Modulator with Sound

RF Oscillator/Modulator, and FM Sound Oscillator/Modulator.

Video Data Converters
Single Channel7-Bit ND

7-Bit, 25 MHz, 2.0 V input range, ± 5.0 V supplies, TTL output, no
pipeline delay.

P/738
DW1751D

MC10321

Single Channel 7-Bit ND

8-Bit, 25 MHz, 2.0 V input range, ± 5.0 V supplies, TTL output, no
pipeline delay.

P/709
DW/751E

MC10319

Video clamps for RGBIYUV, 15 MHz conversion.

FN/777

MC44250

Video clamps for RGBIYUV, 18 MHz conversion, high Z outputs.

FN/777

MC44251

Triple 8-Bit Video ND

Single Channel 8-Bit Video DAC

Triple 8·Bit Video DAC

40 MSPS, video controls ± 5.0 V, TTL inputs.

P/649

MC10322

40 MSPS, video controls - 5.0 V, ECl inputs.

P/649

MC10324

FB/824

MC44200

TTL inputs, 75 Q drive outputs.

Television Subsystems
Monomax Black and White TV
Subsystem

IF, Video processor, horizontal and vertical timing, for NTSC applications,
525 line systems.

P!710

MC13001X

Monomax Black and White TV
Subsystem

IF, Video processor, horizontal and vertical timing, for PAL applications,
625 line systems.

P!710

MC13007X

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
9-4

Video Circuits (continued)
>::; :~;i~:>

-"; ;::tlfu,~ctlon,','
Multimode Color Monitor Processor

Triple video amplifiers, horizontal PLLs and deflection timing, vertical
ramp generator, 30 to 57 kHz.

Sound
Sound IF Detector

Interchangeable with ULN2111 A.

P/646

MC1357

Sound IF with Preamp

Sound IF, Low Pass Filter, FM Detector, DC Volume Control,
Preamplifier, 100 I1V sensitivity, 4.0 W output into 16 n.

P/648C

TDA3190

Video Overlay Synchronizer

Complete Color TV Video Overlay Synchronizer, remote or local system
control.

PI711
FNI777

MC1378

Subcarrier Reference Generator

Provides continuous subcarrier sine wave and 4x subcarrier, locked to
incoming burst.

P/626
01751

MC44144

Closed Caption Decoder

Conforms to FCC, NTSC standards, underline and italics control.

P1707

MC144143

Sync Separator/Pixel Clock PLL

PAUNTSC sync separator with vertical and composite sync output,
6.0 to 40 MHz pixel clock PLL.

01751

MC44145

Dual Video Amplifiers

Gain @ 4.43 MHz = 6 dB ±1 dB, fixed gain, internally compensated,
CMOS technology.

P/626
F/904

MC14576B

Gain @ 5.0 MHz = 10 dB maximum, 10 MHz = 6 dB maximum,
adjustable gain, internally compensated, CMOS technology.

P/626
F/904

MC14577B

Transistor Array

One differential pair and 3 isolated transistors, 30 V, 50 mAo

01751

CA3146

Transistor Array

One differential pair and 3 isolated transistors, 15 V, 50 mAo

P/626
01751

MC3346

Miscellaneous

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
9-5

Video Circuits

(continued)

zoomed, windowed, overlayed. or process enhanced in ways
never before possible.
Also included in this selector guide you will find products for
TV and other TV related functions that will allow you to
produce advanced TV products. These products span the
range of applications including tuner control, video decoding,
closed-captioning, stereo sound decoding and video
encoding and synchronizing.

Bringing video into the personal computer allows a
multitude of multimedia application dreams to become
possible. Old applications can be done in new ways. Totally
new applications, before impossible, become reality.
Moving beyond text and graphics to real images is what
Motorola can bring to the user. Utilizing Motorola integrated
circuits, video can be captured, processed and brought onto
the screen where the video image can be scaled, clipped,

Video Input Processing

Video lin

Comb Filter
MC141625

TripieADC
MC44251
Pixel Clock

Video 21n

Video Output Processing

Digital
RGB/YUV ' - - - - - , /

Analog
RGB/yUV

Triple DAC
MC44200

CompVideo
Encoder
MC13077

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

9-6

S-Luma
S-Chroma

Video Circuits (continued)

Composite Video Overlay Synchronizer
MC1378P, FN Case 711, 777
•
•
•
•
•
•
•

The MC1378 contains a complete encoder function, i.e.
quadrature color modulators, RGB matrix, and blanking level
clamps, plus a complete complement of synchronizers to lock
a microcomputer based video source to any remote video
source. The MC1378 can be used as a local system timing and
encoding source, but it is most valuable when used to lock the
microcomputer source to a remotely originated video signal.

Contains All Needed Reference Oscillators
Can Be Operated in PAL or NTSC Mode, 625 or 525 Line
Wide band, Full Fidelity Color Encoding
Local or Remote Modes of Operation
Minimal External Components
Single 5.0 V Supply
Works with Non-Standard Video

Burst Gate Out

5

----------------~r,
28

I
I
I

I----~wv_="= 4 MHz

*

Cer

Res

1----<)--0 HSync In
Comp

>--",:::()--OSync Out

I
I
I
I
I1... _ _ _

17

-Yout

Video VCC
Out

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

9-7

Video Circuits

(continued)

Advanced PALINTSC Encoder
MC130np, ow Case 738,7510
The MC13077 is an economical, high quality, RGB encoder
for PAL or NTSC applications. It accepts red, green, blue and
composite sync inputs and delivers either composite PAL or
NTSC video, and S-Video Chroma and Luma outputs. The
MC13077 is manufactured using Motorola's high density,
bipolar MOSAIC® process.

•
•
•
•
•
•
•
•

• Single 5.0 V Supply
• Composite Output

S-Video Outputs
PAUNTSC Switchable
PAL Squarewave Output
PAL Sequence Resettable
Internal/External Burst Flag
Modulator Angles Accurate to 90°
Burst Position/Duration Determined Digitally
Subcarrier Reference from a Crystal or External Source

Vcc

Gnd

i----~----------------------~-----l
Divide by Four Ring
Counter

45"

Divide by 256

0"

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
9-8

3.58/
4.43 MHz
Latch

I
I
I
I
I
I
I

Video Circuits

(continued)

Multistandard Video/Timebase Processor
MC44001P Case 711
The MC44001 is a highly advanced circuit which performs
most of the basic functions required for a color TV. All of its
advanced features are under processor control via an 12C bus,
enabling potentiometer controls to be removed completely. In
this way the component count may be reduced dramatically,
allowing significant cost savings together with the possibility
of implementing sophisticated automatic test routines. Using
the MC44001, TV manufacturers will be able to build a
standard chassis for anywhere in the world.

• Filters Automatically Commutate with Change
of Standard
.
• Chroma Delay Line is Realized with Companion
Device (MC44140)
• RGB Drives Incorporate Contrast and Brightness
Controls and Auto Gray Scale
• Switched RGB Inputs with Separate
Saturation Control
• Auxiliary Y, R-Y, B-Y Inputs
• Line Timebase Featuring H-Phase Control and
Switchable Phase Detector Gain and Time Constant
• Vertical Timebase Incorporating the Vertical
Geometry Corrections
• E-W Parabola Drive Incorporating the Horizontal
Geometry Corrections
• Beam Current Monitor with Breathing Compensation

• Operation from a Single +5.0 V Supply; Typical Current
Consumption only 100 rnA
• Full PAUSECAM/NTSC Capability
• Dual Composite Video or S-VHS Inputs
• All ChromalLuma Channel Filtering, and Luma Delay
Line are Integrated using Sampled Data Filters requiring
no External Components

R-Y

R
G

B

Drive

.s.ov

Anode
Current

.s.ov

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
9-9

Video Circuits

(continued)

Digitally Controlled Video Processor
for Multimedia Applications
MC44011FN Case 777

The MC44011, a member of the MC44000 Chroma 4
family, is designed to provide RGB or YUV outputs from a
variety of inputs. The inputs may be either PAL or NTSC
composite video (two inputs), S-VHS, RGB, and color
difference (R-Y, B-Y).
The MC44011 provides a sampling clock output for use
by a subsequent analog to digital converter. The sampling
clock (6.0 to 40 MHz) is phase-locked to the horizontal
frequency. Additional outputs include composite sync,
vertical sync, field identification, luminance, burst gate, and
horizontal frequency.
Control of the MC44011, and reading of status flags is
accomplished via an 12C bus.

• Multistandard Decoder, Accepts NTSC and PAL
Composite Video
• Dual Composite Video or S-VHS Inputs
• All Chroma and Luma Channel Filtering, and Luma Delay
Line are Integrated using Sampled Data Filters requiring
no External components
• Digitally Controlled via 12C Bus
• Auxiliary Y, R-Y, B-Y Inputs
• Switched RGB Inputs with Separate Saturation Control
• Line-Locked Sampling Clock for Digitizing Video Signals
• Burst Gate Pulse Output for External Clamping
• Vertical Sync and Field Ident Outputs
• Software Selectable YUV or RGB Outputs able to Drive
AID Converters

MC44011 Block Diagram

~_~lnR.uts

Outputs
VCC1GND1

~

R-Y

r------ff----

B-Y

, Fast
Y2 R G B Comm.

CompVideo 1

R/Y }
G/Y Outputs

Sound Trap/Luma Filter/Luma Delay/
Chroma Filter/Pal & Ntsc Decoder/
Hue & Saturation Control

CompVideo2

B/U

1------OVCC3
~-~~~-~-~-~~~~~~--------~GND3

Burst
Gate
....n...

16Fh/ Fitter
CSYNC Switch

H
Filter

Quiet
Gnd

Fh
Ref.

15k
Ret.

PLL
Filter

Clock

.IUU""

Frequency
Divider

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

9-10

To NO Converters

Video Circuits

(continued)

TV Stereo Decoder for NICAM
and German System
MC44131P Case 710

The MC44131 combines all of the functions necessary for
the decoding and sound control in accordance with the NICAM
and German Standard transmission systems. It is controlled
via a microprocessor and 12C bus.

• Direct Balance Adjustment via Software
• 12C Bus Controlled Routing of the Basebandl
Monaurai/SCART Inputs to Loudspeaker/Headphonel
Hi Fi/Scart Outputs
• Loudspeaker Output Control of Tone, Special Effects,
Independent Left-Right Volume Control
• Headphone Output Control of Independent Left-Right
Volume Control

• Pilot Tone Decoding
• Baseband Stereo Signal Decoding
• Signal De-emphasis

AnaVss
AnaGnd

Ana
Gnd

K2

TCl

Kl

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
9-11

TCR

Video Circuits

(continued)

Digital Chroma Delay Line
MC44140P,

ow Case 648, 751G

The MC44140 is a monolithic 64 J.LS delay line, intended for
color TV applications. It may be used as a baseband chroma
correction circuit (with PAL), or as a chroma delay line (with
SECAM). The device has been designed for use with the
MC44000 as part of Chroma 4, or with the MC44011 , but may
also be used as a general purpose delay line for other
applications.

R-Yln

Analog

Analog

VDD

Vss

•
•
•
•
•
•
•
•

Part of SYSTEM 4 Concept
Works with Baseband Color Difference Signals
PAL (4.43 MHz)/SECAM/NTSC Capability
Uses 17.734475 MHz Clock with PAUSECAM Signals
8-Bit Sampling at 1/6 Clock Frequency
External Inputs (Satellite ...)
Minimum Number of External Components
Low Current (35 mAl, +5.0 V Supply

Digital
VDD

Digital

ETR

ETR

VSS

R-Y

R-Y

--l
I-R-YOul

R-Yln

--l

B-Yln

--l
I- B-YOut

B-Yln

--l

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
9-12

Video Circuits

(continued)

Subcarrier Reference
MC44144P, D Case 626, 751
The MC44144 is a phase-locked-loop for video
applications that provides the subcarrier frequency, and 4
times subcarrier frequency locked to the color burst. It
contains, on a single chip, a phase detector, voltage controlled
oscillator, divide-by-four, and video clamp.

The MC44144 is manufactured using Motorola's high
density, bipolar MOSAIC® process.
• Provides 4x Frequency Locked to Color Burst
• Provides Regenerated Subcarrier Output
• 5.0 V Operation

Burst
Gale

Subcarrier

Crystal

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
9-13

Video Circuits

(continued)

Pixel Clock Generator and Sync Separator
MC44145D Case 751A
The MC44145 Pixel Clock Generator is a component of the
M44000 family. This device contains a sync separator with
horizontal and vertical outputs, and clock generation circuitry
for the digitization of any video signal, along with the
necessary circuitry for clock generation such as a phase
comparator and a + 2 to provide a 50% duty cycle.

•
•
•
•

Stand Alone PLL Circuit
Switchable Divider for 50% Duty Cycle
Integrated Sync Separator
Integrated Buffer Amplifier

Sync

vee
Video In

r='c;I

Sync Sop

Out
B

Sync Amp

Out

+2EN

hr-,,.,-,,.,-lll

I
I
I
I
I

I:

I
Ii

r\""==~,

L
I:;
WJ:I:
Gain

Triple a-Bit 01A Converter
MC44200FB Case 824A
The MC44200 is a monolithic digital to analog converter for
three independent channels fabricated in CMOS technology.
The part is specifically designed for video applications.
Differential outputs are provided, allowing for a large output
voltage range.
•
•
•
•
•
•
•
•

r-------------,
VOOG

OG

G~

~':':'>---VOO

8-Bit Resolution
Differential Outputs
80 msps Conversion Speed
Large Output Voltage Range
Low Current Mode
Single 5.0 V Power Supply
TTL Compatible Inputs
Integrated Reference Voltage

r--oL_,,",

vOOR

~-+-~~
OR
"'--,~--uOii

Rln

r::--n---O VOOB
H--+--r-I
OB

Bin

"'--,,-I"--u00

+---+-0---If--o
Clk o-----<~-'

VOO
VSS

CCAS

6-!.
~

VOOR 0 - - - - - - - - - - ' "

Rlref

I-O--l~

I
I

VSSR 0
-_
-_
-_
-_
-_
--_
' _ .J
L. _
____

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

9-14

CVre!

Video Circuits

(continued)

Triple a-Bit AID Converter
MC44250/51 FN Case 777
The MC44250 and MC44251 contain three independent
parallel analog to digital converters. Each ADC consists of 256
latching comparators and an encoder. Input clamps allow for
AC coupling of the input signals, and DC coupling is also
allowed. For video processing performance enhancements, a
dither generator with subsequent digital correction is provided
to each ADC. The outputs of the MC44251 can be set to a high
impedance state.

These AIDs are especially suitable as front end converters
in TV picture processing.
•
•
•
•

15 MHz Maximum Conversion Speed (MC44250)
18 MHz Maximum Conversion Speed (MC44251)
Input Clamps suitable for RGB and YUV applications
Built-in Dither Generator with Subsequent
Digital Correction
• Single 5.0 V Power Supply

Simplified Diagram of One of the ADCs
Vrel

Rtop

Rmid

8
Data
Outputs
Clock

Analog Input

HZ

VTN
Mode

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
9-15

Video Circuits

(continued)

Multistandard Video IF
MC44301 P,

ow Case 724, 751 F

The MC44301 is a single channel TV IF and PLL detector
system for all standard transmission systems. This device
enables the designer to produce a high quality IF system with
white spot inversion, AFT and AGC. The MC44301 was
designed with an emphasis on linearity to minimize
sound/picture intermodulation.

•
•
•
•
•
•
•
•

Single Coil Adjustment for AFT and PLL
VCO at 1/2 IF for Minimum Beats
Simple Circuitry for Low System Cost
White Spot Inversion
Symmetrical ± 2.0 MHz AFT Pull-In
Demodulates Positive or Negative Modulation
Auxiliary AM Detector for AM Sound
Simple Alignment Procedure

Video

Output

4

Mode SWitch

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

9-16

Video Circuits

(continued)

1.3 GHz Tuner PLL with 12C Control
MC44802AP Case 707
The MC44802A is a tuning circuit for TV applications. It
contains, on one chip, all the functions required for PLL control
of a VCO. This integrated circuit also contains a high frequency
prescaler (which can be bypassed by software control) and
thus handle frequencies up to 1.3 GHz.

•
•
•
•
•

Programmable Reference Divider
Tri-State Phase/Frequency Comparator
Op Amp for Direct Tuning Voltage Output: 30 V
Seven High Current Buffers: 10 mA, 12 V
Output Options for 62.5 kHz, Reference Frequency
and the Programmable Divider
• Software Compatible with the MC4481 0
• 12C Interface

• Complete Single Chip System for MPU Control (12C Bus)
• Selectable -;. 8 Prescaler Accepts Frequencies Up
to 1.3 GHz

18

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

9-17

Video Circuits

(continued)

1.3 GHz Tuner PLL with 3-Wire Control
MC44807P/17D Case 648, 751 B
The MC44807/17 is a tuning circuit for TV applications. It
contains, on one chip, all the functions required for PLL control
of a VCO. This integrated circuit also contains a high frequency
prescaler (which can be bypassed by software control) and
thus handle frequencies up to 1.3 GHz.

• Tri-State Phase/Frequency Comparator with Lock
Detect Output
• Op Amp for Direct Tuning Voltage Output: 30 V
• Four Integrated Band Buffers for 40 mA (VCC1
to 14.4 V)
• Output Options for Reference Frequency and
Programmable Divider
• Bus Protocol for 18 or 19-Bit Transmission
• High Input Sensitivity

• Complete Single Chip System for MPU Control
(3-Wire Bus)
• + 8 Prescaler Accepts Frequencies Up to 1.3 GHz
• 15-Bit Programmable Reference Divider Accepts
Frequencies Up to 165 MHz

Bands Out
30mA
~

Vtun

Amp In

Gnd
Lock

EN
Data
Clock

Xtal

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
9-18

Video Circuits

(continued)

PLL Tuning Circuit with DACs for Tuner Alignment
MC44810P Case 738
The MC44810 is a tuning circuit for TV applications. It
contains a PLL section and a DAC section and is MPU
controlled through the 12C bus.
The PLL section contains all the functions required to
control the VCO of a TV tuner. It generates the tuning voltage
and the additional control signals. The PLL section is
functionally equivalent to the MC44802A.
The DAC section generates three varactor voltages in
order to feed all of the tuner varactors with their individually
optimized control voltages (automatic tuner adjustment).

• Selectable .;- 8 Prescaler accepts Frequencies up
to 1.3 GHz
• 15-Bit Programmable Reference Divider accepts
Frequencies up to 165 MHz
• Op Amp for Direct Tuning Voltage Output: 30 V
• Seven High Current Buffers: 10 mA, 12 V
• Output Options for 62.5 kHz, Reference Frequency
and Programmable Divider
• Software Compatible with the MC44802A
• Three 6-Bit DACs for Automatic Tuner Adjustment
Allowing use of Non-Matched Varactors
• 2-Chip Addresses for the PLL Section and
2 Different Chip Addresses for the DAC Section

• Complete Single Chip System for MPU Control (12C Bus)
• Tri-State Phase/Frequency Comparator

VCC233 V

r-"-t----.,..=-t---H

----po--l
AMP

19
Amp In

Gnd

Clock
Data

HFln

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

9-19

Video Circuits

(continued)

Closed-Caption Decoder
MC144143P Case 707

The MC144143 is a Line 21 closed-caption decoder for use
in television receivers or set top decoders conforming to the
NTSC broadcast standard. Capability for processing and
displaying all of the latest standard Line 21 closed-caption
format transmissions is included. The device requires a
closed-caption encoded composite video signal, a horizontal
sync signal, and an external keyerto produce captioned video.
RGB outputs are provided, along with a luminance and a box
signal, allowing simple interface to both color and black and
white receivers.

• Conforms to the SCC Report and Order as Amended by
the Petition for Reconsideration on Gen. Doc. 91-1
• Supports Four Different Data Channels, Time Multiplexed
within the Line 21 Data Stream: Captions Utilizing
Languages 1 & 2, Plus Text Utilizing Languages 1 & 2
• Output Logic Provides Hardware Underline Control and
Italics Slant Generation
• Single Supply Operating Voltage Range: 4.75 to 5.25 V
• Composite Video Input Range: 0.7 to 1.4 Vp-p
• Horizontal Sync Input Polarity can be either Positive
or Negative
• Internal Timing/Sync Signals Derived from
On-Chip VCO

Data Modulator &
Transfer Buffer

Video
In

Slice
Level

Character
ROM

R
G

Output
Logic

B
luma

Hsync

Box

Reset

Filter

Config
Enable

Decoder
Control

CT/SData
Lang/SClk

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
9-20

Video Circuits

(continued)

Advanced NTSC Comb Filter
MC141621FB Case 898
The MC141621 is an advanced NTSC comb filter for VCR
and TV applications. It separates the luminance (Y) and chrominance (C) signals from the NTSC composite video signal
by using digital signal processing techniques. This filter allows a video signal input of an extended frequency bandwidth
by using a 4.0 FSC clock. In addition, the filter minimizes dot
crawl and cross color effects. The built-in NO and O/A converters allow easy connections to analog video circuits.

•
•
•
•
•
•
•

Built-in High Speed 8-Bit NO Converter
Two line Memories (1820 Bytes)
Advanced Combing Process
Two 8-Bit O/A Converters
Built-in Clamp Circuit
On-Chip Reference Voltage Regulator for AOC
Oigitallnterface Mode

CO C1 C2 C3 C4 C5 C6 C7

RTP
28

RTPS
27
Self
Bias

Ibias

39

23

22
AOC

Ibias

RBTS

RBT

21
Vin
Yout
REF(OA)

20

Control
Logic

Clout

Cout

Clamp

18

17

16

CLC

TE1

TEO
Mode 1

VCC(AO) =PIN 25
VCC(O) =PIN 11
VCCIOA) =PIN 42
GNO AD) =PIN 26
GNO(O) =PINS 9, 19
GNO(OA) =PIN 43

Mode 0

DO 01 02 03 04 05 06 07

13
BW

Clk

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
9-21

Video Circuits

(continued)

Advanced PAL/NTSC Comb Filter
MC141625AFB, FB Case 898
The MC 141625 is an advanced PAUNTSC comb filter for
VCR and TV applications. It separates the luminance (Y) and
chrominance (C) signals from the PAL or NTSC composite
video signal by using digital signal processing techniques.
This filter allows a video signal input of an extended frequency
bandwidth and minimizes dot crawl and cross color effects.
The built-in AID and D/A converters allow easy connections to
analog video circuits.

•
•
•
•
•
•
•
•

DO 01 02 03 04 05 06 07

Fast 8-Bit AID Converter
Four Line Memories (4540 Bytes)
Advanced Combing Process
Two 8-Bit D/A Converters
Built-in Clamp Circuit
On-Chip Reference Voltage Regulator for ADC
Digital Interface Mode
PAUNTSC Mode
CO Cl C2 C3 C4

C5 C6

C7

TEl
TEO
Model
Mode 0

~Clk(AO)

Control
Logic

17

ComblBPF 46

Vin
Clout
CLC

BW 48

RBT
Control
Logic
Bypass

47
RTP

Clk~ CLK BUF I
VCC(AD) =PIN 12
VCC(O) =PINS 2, 44
VCC(OA) =PIN 7
GNO(AO) =PIN 11
GNO(O) =PINS 1, 19, 43
GNO(OA) =PtN 6

OAC OAC

10

4
Yout

Cout

Ibias

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

9-22

Video Circuits

(continued)

Dual Video Amplifiers
MC14576B177BF, P Case 626, 904

The MC14576B!77B devices each contain two amplifiers
manufactured in CMOS process. Each amplifier also employs
two lateral NPN bipolar transistors.
The MC14576B contains two internally compensated
operational amplifiers. On-chip gain setting resistors result in
a noninverting voltage gain of 6.0 dB, ±1.0 dB at 4.43 MHz for
each amp. Each noninverting input of the MC14576B appears
as mostly a capacitive load of approximately 10 pF.

The MC14577B also contains two internally compensated
operational amplifiers. However, the gain for each amplifier is
adjustable with external components. All inputs of the
MC14577B appear mostly as capacitive loads of
approximately 10 pF.
• Direct Drive of 150 Q Loads
• May Be Used with Single or Dual Supplies
• Guaranteed Bandwidth of 10 MHz

MC145768

MC145778

5>J
5000.

5000.
2
Input A- (J----/\./V'v
3
______ +
Input A+ 0 - -

2
Input A - :3
r > - +> - - - - - -o OutputA
Input A + )-------1

t
>-~>_--O OutputA

[i>J
5000.

6
5000.
Input B- Q-------A.JVv.5_
Input B+

c:..--

~

-+

6

?

Input B - :5
. .r > - +> - - - - -0 Output B
InputB+ - - Pin 4 =VSS
Pin 8= VDD

o OutputB
Pin 4 = VSS
Pin 8 ~ VDD

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

9-23

Video Circuits (continued)
Chroma 4 Family Block Diagram

MCM44182
2 kbit EEPROM

Remote Control
MCl44105
MC44106
MC68HC04Rl
MLED81

I

I
I
I
I
I
I
I
I
I
I

f
MRD821
RC Receiver

._r--1
I

, -_ _ _ _ _ _....,video
MC44301
Video IF

I
I
I

I

MC44140
Chroma Delay Une

From SateliHe

12C BUS

I
I
I__ - ~~~~~~~-Q~~
1

I
Demodulator

Stereoton Decoder
and Audio Processor

I
I
I
I
I
I
I
I
I
I
._1

Video/RGB Switch

tR rtl
G B FC
Hi-Fi

0000
0000
0000
0000

+12V
+5.0V

SCART Connector

MC44602
SMPS Controller

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

9-24

Remote Control Circuits
MC3373P Amplifier/Detector (Bipolar) Case 626
MC14497 Transmitter (CMOS) Case 707
The MC3373 remote control receiver is specifically
designed for infrared link systems where high sensitivity and
good noise immunity are critical. The MC3373 incorporates a
high gain detector diode preamp driving an envelope detector
and data wave shaper for accurate data recovery. Provision
is also made to use an external L-G tank circuit at the carrier
frequency, normally 30 to 60 kHz, for extended range low

noise systems. Applications include TV remote control, short
range data links (up to several hundred feet), door openers
and security systems. The MG14497 is an ideal companion
transmitter, where a simple DTMF like key-pad control is
desired. The Motorola Discrete Opto Division also has several
high sensitivity detectors and emitters which match up well to
the MG3373 system.

Remote Control Application
40 kHz Carrier
+9.0Vdc
lN4001
1500

'"

MLED81

"'-wr-wv-",
'"

-+--1++-117
-+--1++-12
-+--1++-116
-+--1++-114
-+--1++-111
4
56 7

Infrared
Emitting
.Diodes

'"
'"

lN914
('See Fig. 4)

CMOS Remote Control Functions

<.

.'

Number of

..'

Functio/1

".

Addre~J..iI1E!$

MaldmumNumbef iNt.101~rof
of Address Codes .'. Data Bits .

1}.····S'·•.··.·.2'i.····· E·:e:'.·
·~· ·• ·.· ~.t~J1;Q,>· ~.· · ·"· · · ·
I:
ice

Addressable UART

7

128

7/8

Full-Duplex

MCl4469

Transmitter

0

0

6

Simplex

MC14497

P1707

Encoder

Depends on
Decoder(1)

Depends on
Decoder(1)

Depends on
Decoder(1)

Simplex

MC145026

P/648, D1751 B

Decoder

5

243

4

Simplex

MC145027

P/648, DW1751G

9

19,683

0

Simplex

MC145028

9

512

0

Half-Duplex

MC145030

P1738, DW1751 D

15

32,768

0

Half-Duplex

MC145033

DW1751F

Encoder

13 or 17

131,072

4

Simplex

MC145034

Decoder

13 or 17

131,072

4

Simplex

MC145035

Encoder/Decoder

(l)See MC145027, MC145028

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

9-25

PI711, FNI777

CONSUMER ELECTRONIC CIRCUITS
Entertainment Radio Receiver Circuits
Device

Function

Page

MC3340
MC13020
MC13022
MC13024
MC13060
MC34119

Electronic Attenuator ....................................................
Motorola C-QUAM AM Stereo Decoder ....................................
Advanced, Medium Voltage AM Stereo Decoder ............................
Low Voltage Motorola C-QUAM AM Stereo Receiver ........................
Mini-Watt Audio Output ..................................................
Low Power Audio Amplifier ...............................................

9-100
9-121
9-126
9-130
9-137
9-153

Device

Function

Page

CA3054
CA3146
MC1330A
MC1350
MC1357
MC1373
MC1374
MC1377
MC1378
MC1388
MC1391
MC3346

Dual Independent Differential Amplifier ....................................
General Purpose Transistor Array ....................................... "
Low-Level Video Detector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Monolithic If Amplifier ...................................................
TV Sound If or FM If Amplifier with Quadrature Detector .....................
TV Video Modulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
TV Modulator Circuit ....................................................
Color Television RGB to PAUNTSC Encoder ...... . . . . . . . . . . . . . . . . . . . . . . . ..
Color Television Composite Video Overlay Synchronizer .....................
Geometry Correction Waveform Generator .................................
TV Horizontal Processor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
General Purpose Transistor Array One Differentially Connected Pair
and Three Isolated Transistor Arrays ....................................
Monomax Black and White TV Subsystem .................................
Monomax Black and White TV Subsystem .................................
NTSC/PAL Chroma 10 Color TV and Timebase Processor ...................
Electronically Tuned Radio Front End .....................................
Advanced PAUNTSC Encoder ...........................................
Chroma 4 Multistandard Video Processor ..................................
Bus Controlled Multistandard Video Processor .............................
Subcarrier Reference ...................................................
Sync Separator/Pixel Clock Generator .....................................
High Performance Color TV IF ...........................................
Advanced Multistandard TV Video/Sound IF ...............................
Convergence Waveform Generator IC for Projection TV .....................
PLL Tuning Circuit with 1.3 GHz Prescaler .................................
PLL Tuning Circuit with 3-Wire Bus .......................................
PLL Tuning Circuit with 1.3 GHz, Prescaler and D/A Section .................
TV Sound System ......................................................
TV Color Processor .....................................................

9-27
9-28
9-30
9-36
9-40
9-46
9-49
9-57
9-73
9-77
9-96

Video Circuits

MC13001XP
MC13007XP
MC13017
MC13025
MC13077
MC44001
MC44011
MC44144
MC44145
MC44301
MC44302
MC44615A
MC44802A
MC44807/17
MC44810
TDA3190
TDA3301B

9-103
9-110
9-110
9-119
9-134
9-141
9-166
9-182
9-230
9-234
9-237
9-255
9-258
9-275
9-282
9-289
9-297
9-300

Remote Control Circuit
Device

Function

MC3373

Remote Control Wideband Amplifier with Detector .......................... 9-106

Page

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
9-26

CA3054

MOTOROLA

SEMICONDUCTOR-----TECHNICAL DATA

DUAL DIFFERENTIAL
AMPLIFIER

Dual Independent Differential
Amplifier
The CA3054 consists of two independent differential amplifiers with associated
constant-current transistors on a common monolithic substrate. The six NPN
transistors which comprise the amplifiers are general purpose devices useful from
DC to 120 MHz.
The monolithic construction of the CA3054 provides close electrical and
thermal matching of the amplifiers which makes this device particularly useful in
dual channel applications where matched performance of the two channels is
required.
• Two Differential Amplifiers on a Common Substrate

".

PSUFFIX
PLASTIC PACKAGE
CASE 646

,

PIN CONNECTIONS

• Independently Accessible Inputs and Outputs
• Maximum Input Offset Voltage: ±5.0 mV
MAXIMUM RATINGS
Rating

Symbol

Value

Unit

Collector-Emitter Voltage
Collector-Base Voltage
Emitter-Base Voltage

VCEO
VCBO
VEBO

15
20
5.0

Vdc

Collector-Substrate Voltage

VCIO
IC

20

Vdc

50

mAdc

Collector Current - Continuous
Junction Temperature

TJ

150

'C

Operating Ambient Temperature Range
Storage Temperature Range

TA

-40 to +85
-65 to +150

'c

Tstg

Pin 5 is connected to substrate and must
remain at the lowest circuit potential

'C

ELECTRICAL CHARACTERICISTICS (TA = 25°C. unless otherwise noted.)

I

Symbol

Characteristics

Min

Typ

Max

Unit

STATIC CHARACTERISTICS (For Each Differential Amplifier)
Input Offset Voltage
(VCB = 3.0 Vdc)

VIO

-

-

5.0

mV

Input Offset Current
(VCB = 3.0 Vdc)

110

-

-

2.0

JJA

Input Bias Current
(VCB = 3.0 Vdc)

liB

-

-

24

JJA

-

0.70
0.80
0.85
0.90

-

-

V(BR)CEO

15

V(BR)CBO

STATIC CHARACTERISTICS (For Each Transistor)
Base-Emitter Voltage
(VCB = 3.0 Vdc. IC = 50 JJA)
(VCB = 3.0 Vdc. IC = 1.0 rnA)
(VCB = 3.0 Vdc. IC = 3.0 rnA)
(VCB = 3.0 Vdc. IC = 10 rnA)

VBE

Collector Cutoff Current
(VCB = 10 Vdc. IE = 0)
Collector-Emitter Breakdown Voltage
(lc = 1.0 rnA)
Collector-Base Breakdown Voltage
(lc = 10 pA)
Collector-Substrate Breakdown Voltage
(IC = 10 pA)
Emitter-Base Breakdown Voltage
(IE = 10 JJA)

ICBO

Vdc

-

100

nA

-

-

Vdc

20

-

-

V(BR)CIO

20

-

-

V(BR)EBO

5.0

-

-

MOTOROLA LlNEARIINTERFACE ICs DEVICE DATA
9-27

MOTOROLA

CA3146

SEMICONDUCTOR-----TECHNICAL DATA

General Purpose Transistor Array

GENERAL PURPOSE
TRANSISTOR ARRAY

One Differentially Connected Pair and
Three Isolated Transistor Arrays

SILICON MONOLITHIC
INTEGRATED CIRCUIT

The CA3146 is designed for general purpose, low power applications in the
DC through VHF range.
• Guaranteed Base-Emitter Voltage Matching
• Operating Current Range Specified: 10 IlA to 10 rnA

".

• Five General Purpose Transistors in One Package

PSUFFIX
PLASTIC PACKAGE
CASE 646

1

MAXIMUM RATINGS
Symbol

Value

Unit

Collector-Emitter Voltage

VCEO

130

Vdc

Collector-Base Voltage

VCBO

20

Vdc

Collector-Substrate Voltage

VCIO

20

Vdc

VEBO

5.0

Vdc

Collector Current

IC

50

mAde

Operating Temperature Range

TA

-40 to +85

°c

Tstg

-65 to +150

°C

Rating

Emitter-Base Voltage

DSUFFIX
PLASTIC PACKAGE
CASE 751A
(SO-14)

ORDERING INFORMATION
Temperature Range

Storage Temperature Range

PIN CONNECTIONS

Pin 13 is connected to substrate and must remain at the lowest circuit potential.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

9-28

CA3146
ELECTRICAL CHARACTERICISTICS

I

Characteristics

Symbol

Min

Typ

Max

Unit

Collector-Base Breakdown Voltage
(IC = 10 !lAdc)

V(BR)CBO

40

89

-

Vdc

Collector-Emitter Breakdown Voltage
(IC = 1.0 mAdc)

V(BR)CEO

35

45

-

Vdc

Collector-Substrate Breakdown Voltage
(ICI = 10 !lA)

V(BR)CIO

40

85

-

Vdc

Emitter-Base Breakdown Voltage
(IE= IO !lA)

V(BR)EBO

5.0

-

-

Vdc
nAdc

STATIC CHARACTERISTICS

-

0.68

40

-

171
188

-

VBE

-

0.7

-

Vdc

VCE(sat)

-

0.28

0.5

Vdc

110

-

0.03

2.0

!lAdc

IVlol

-

0.13

2.0

mVdc

Low Frequency Noise Figure
(VCE = 5.0 Vdc, IC = 100 !lAdc, RS = 1.0 kn, 1= 1.0 kHz)

NF

-

3.25

-

dB

Forward Current Transler Ratio
(VCE = 5.0 Vdc, IC = 1.0 mAdc, I = 1.0 kHz)

hie

-

201.5

-

-

Short Circuit Input Impedance
(VCE = 5.0 Vdc, IC = 1.0 mAdc, I = 1.0 kHz)

hie

-

6.7

-

kn

Open Circuit Output Impedance
(VCE = 5.0 Vdc, IC = 1.0 mAdc, I = 1.0 kHz)

hoe

-

15.6

-

!lmho

Reverse Voltage Transler Ratio
(VCE = 5.0 Vdc, IC = 1.0 mAdc, I = 1.0 kHz)

hre

-

3.5

-

XI 0-4

Input Admittance
(VCE = 5.0 Vdc, IC = 1.0 mAdc, I = 1.0 kHz)

Vie

-

0.14+
jO.16

-

mmho

Forward Transler Admittance
(VCE = 5.0 Vdc, IC = 1.0 mAdc, I = 1.0 kHz)

Vie

-

34.6jO.63

-

mmho

Reverse Transler Admittance
(VCE = 5.0 Vdc, IC = 1.0 mAdc, I = 1.0 kHz)

Vre

-

62.0j59.4

-

!lmho

Output Admittance
(VCE = 5.0 Vdc, IC = 1.0 mAdc, I = 1.0 kHz)

Voe

-

0.16+
jO.14

-

mmho

300

500

-

MHz

Collector-Base Cutoff Current
(VCB = 10 Vdc, IE = 0)

ICBO

DC Current Gain
(IC = 10 mAdc, VCE = 5.0 Vdc)
(IC = 1.0 mAdc, VCE = 5.0 Vdc)

hFE

Base-Emitter Voltage
(VCE = 5.0 Vdc, IE = 1.0 mAdc)
Collector-Emitter Saturation Voltage
(IC = 10 rnA, IB = 0.4 rnA)
Magnitude 01 Input Offset Current 11101 - 11021
(VCE = 5.0 Vdc, ICI = IC2 = 1.0 mAdc)
Magnitude 01 Input Offset Voltage IVBEI = VBE21
(VCE = 5.0 Vdc, IE = 1.0 mAdc)

-

DYNAMIC CHARACTERICISTICS

Current-Gain - Bandwidth Product
(VCE = 5.0 Vdc, IC = 3.0 mAdc)

IT

Emitter-Base Capacitance
(VEB = 5.0 Vdc, IE = 0 mAdc)

CEB

-

1.17

-

pF

Collector-Base Capacitance
(VCB = 5.0 Vdc, IE = 0 mAdc)

CCB

-

0.68

-

pF

Collector-Substrate Capacitance
(VCS = 5.0 Vdc, IC = 0 mAdc)

CCI

-

1.92

-

pF

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

9-29

MOTOROLA

MC1330A

SEMICONDUCTOR-----TECHNICAL DATA

Low-Level Video Detector

LOW·LEVEL VIDEO
DETECTOR

The MC1330A is an integrated circuit featuring very linear video
characteristics and wide bandwidth. Designed for color and monochrome
television receivers, replacing the third IF, detector, video buffer and AFC buffer.

SILICON MONOLITHIC
INTEGRATED CIRCUIT

• Conversion Gain: 33 dB (Typ)
• Excellent Differential Phase and Gain
• High Rejection of IF Carrier Feedthrough
• High Video Output: 8.0 V(p-p)
• Fully Balanced Detector
• Output Temperature Compensated
• Improved Version of the MC1330
MAXIMUM RATINGS
Value

Rating

Unit

Power Supply Voltage

24

Vdc

DC Video Output Current
DC AFT Output Current

5.0
2.0

mAdc

Junction Temperature

150

°C

Oto 75

°C

-65 to +150

°C

Operating Ambient Temperature Range
Storage Temperature Range

PSUFFIX
PLASTIC PACKAGE
CASE 626

Figure 1. Circuit Schematic
Rl
4.8k

3

Tuned Circun

2

6

r-~~~--~~--------~~--~~~~--~~~--~--~----~~~--------~-oVCC

R7
2.2k

R8
2.2k

R9

RIO

6.95
k

6.4k

Rl1
4.35k

1

'''''''''-------+--0 AFT

R2
3.6k

Buffer

Output

IF 07-t--__+

____-,

Input

R3
2k

Primary

Video

R15
150
R27
12k
R18
5k

lk
R22

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

9-30

3pF

I

4 Output
R28
10.75k

MC1330A
ELECTRICAL CHARACTERICISTICS (VCC = +20 Vdc, Q = 40, fc = 45.75 MHz, TA = +25°C, unless otherwise noted.)
Characteristics

Zero Signal DC Output Voltage
Supply Current

Pin

Min

4

7.0

5,6

11

Typ

-

Max

Unit

8.7

Vdc

17.5

24

rnA

0

0.5

Vdc

-

Maximum Signal DC Output Voltage

4

Conversion Gain for 1.0 Vp-p Output (30% Modulation)

7

25

36

65

mVrms

AFT Buffer Output at Carrier Frequency

1

300

475

650

mVp-p

Pin

Typ

Unit

7
7

4.9
1.5

kn
pF

Internal Resistance (Across Tuned Circuit)
Internal Capacitance (Across Tuned Circuit)

2,3
2,3

4.4
1.0

kn
pF

Negative Video Output Bandwidth (Figurel0)
Positive Video Output Bandwidth (Figurel0)

4
5

10.8
2.2

MHz
MHz

Differential Phase @ 3.58 MHz, 100% Modulated
Staircase, 3.0 Vp-p Detected Video Pin 5 Tied to Pin 6
Differential Gain @3.58 MHz, 100% Modulated
Staircase, 3.0 Vp-p Detected Video Pin 5 Tied to Pin 6

4

7.0

Degrees

4

4.0

%

Differential Phase @ 3.58 MHz, 100% Modulated
Staircase, 3.0 Vp-p Detected Video, R Pin 5 = 4.3 kn
Differential Gain @ 3.58 MHz, 100% Modulated
Staircase, 3.0 Vp-p Detected Video, R Pin 5 = 4.3 kn

4

8.0

Degrees

4

6.0

%

920 kHz Beat Output (dB Below 100% Modulated Video, see Figure 11)
45.75 MHz = Reference
42.17 MHz = -6.0 dB
41.25 MHz = -20 dB

4

-38

dB

DESIGN CHARACTERISTICS (VCC = +20 Vdc, Q = 40, fc = 45.75 MHz, TA = +25°C, unless otherwise noted.)
Characteristics

Input Resistance
Input Capacitance

Video Output Resistance @ 1.0 MHz, 2.0 rnA
Input Overload (Carrier Level at Input to Pin 4, Primary
Output to go Positive 0.1 Vdc from Ground.)

VCC
VCC
VCC
VCC

= 12 Vdc
= 15 Vdc
= 20Vdc
=24 Vdc

Power Supply Voltage Range

4

94

Q

7

2.0
2.6
3.6
4.6

V

5

10 to 24

V

Figure 2. Test Fixture Circuit

vcc
Carrier
Input

>--_---1
50

O.OOl~F

4.3k
Auxiliary Output

20V[~J
MC1330AP

AFT Output

10V

-----

Primary Output
Cl

LI, Cl: See Generallnformaijon Number 3, page 5 of this specification.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
9-31

MC1330A
Figure 4. Video Detector Output Resistance

Figure 3. Input Admittance
1.0

0.8

550

1

Vc 12Vdc

0.6

ii:

W 400

gIl

1/

-~ 1000.

co

0.2

<.>

1il 300

Vqc =20 Vdc
V<;c= 20Vdc

VCC=12VdC'111

3.0

5.0
10
FREQUENCY (MHz)

30

50

\

I-

~III

bll ~

\
\

;l! 350

~

E 0.4

1.0

~.
rJ

II

.§.

o

9. 500
;; 450

COILa "'40

100

ll!
~
I-

250
200

"

is

150
@ 100

" ....,

r--

c

>

50
0.1

0.3
0.5
1
3
VIDEO OUTPUT CURRENT, PIN 4 (mAde)

10

CIRCUIT DESCRIPTION
The MC1330A video detector is a fully balanced multiplier
detector circuit that has linear amplitude and phase characteristics. The signal is divided into two channels, one a linear
amplifier and the other a limiting amplifier that provides the
switching carrier for the detector.
The switching carrier has a buffered output for use in
providing the AFT function.

The video amplifier output is an improved design that
reduces the differential gain and phase distortion associated
with previous video output systems. The output is wideband,
> 8.0 MHz, with normal negative polarity.
A separate narrow bandwidth, positive video output is
also provided.

Figure 5. Differential Phase and Gain Test Set Up

RF'i--------i

1

50

-=

75nlO
50n
= 6.7 dB

100mVInlO
load
Boonton 910

Modulation
Adjustment
= -11 V for 100%
Video
Demodulator
Test
FIXture
Rload = 3k Typ
low Capacitance Resistor
Probe Divider H.P. 10020A

Six Step
Modulated

Staircase

Generator
Tektronix
144NTSC

Vector Scope
Preamplifier

Subcarrier

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

9-32

MC1330A
Figure 7. Output Voltage Transfer Function

Figure 6. Output Voltage Transfer Function
8
7.9
"

7.8

:2.
..,. 7.7
~ 7.6

~

7.5

13 74
~.

7.3

f-

t

r\

~

~ f-- See Figure 6
~
I"---..
..,.
z
~
ii: 5
7

Positive
Offs t

,~

1'.......,. ~

1=

-. I'-...

!:i
o
...... 1--.

a

4
6
8
10
12
CARRIER INPUT VOLTAGE (mVrms)

14

a

20

Output Voltage
( arrier Input =.2-

:2.8
..,.

--- --

z 7

ii:

....-

ui6

(!)

13

5

~ 4
f-

./

f-

is

2

a

-.;'

..,.

./

~

........

~

. / Output Voltage
Carrier Input = 50 mVrms

/supply Current
Carrier Input =

8

V

-'"

~

~ 3

...........

_

26

12

c:I

24
22 ""0
20

g

18

gj

~
.§.. 500
z 300
ii: 200
~

=>
0-

13

f-

16 0
14 ~

=>

4

iii'

:s.

2

0

z

a

~
=>
zw

~
w

I-- Pin 4 - Negative Video
RPin5=0

a:

12 ~
10 en

a:
a:

w

50

t3

30

f-

20

«

""" ,

./'

........

-2
-4

>

........

"

3 -10-8 I - - _po

1

~-;;

~

-14

~

o

a

50

100

~
f-

w-20~--+---4---~~-+---4----.J---+---~

~

G-30~~+--=~~~---+--~~=-.J---+---~

=>

8-40~~~~~~~~~~-4----.J---~~~

'\

1\
\

0 I - - - . J - - 45.75 MHz Input = 25 mVrms
42.17 MHZ Input = 12.5 mVrms
-101--=;""':::-- 41.25 MHz Input = Relative to 45.75 MHz Input

z

~
~
~

~

flPin 5 = 4.3 kQ

-12

5
10
20 30
CARRIER INPUT (mVrms)

Figure 11. Video Output Products

r\

If"\.

In 5, oSltl~e I eo I

-

10

24

I'"\.

./

160

~ 10r---'---~R~e~re-re-nc~e-=~3~.58~M~H~z~O~ut~pu-t--r---.---,

Pin 5=(3 kQ

'"

-6

J

/

140

./

100

Figure 10. Video Output Response
6

r-:;: ::---......

0

a
22

.;'

i-"

u.

14
16
18
20
SUPPLY VOLTAGE (Vdc)

......

1000

6
10

i'.....

~ r....... '-..

Figure 9. AFT Limiting

..,..

,,9

.........

40
60
80
100
120
CARRIER INPUT VOLTAGE (mVrms)

Figure 8. Output Voltage, Supply Current
10

..............

VCC = 10Vd;'

a

16

~ ...........~

VCC = 15 Vdc

=>
0-

~

VCC =20Vdc

...........

f-

=>
07.1

7

.............

~
4
'-'
~ 3

......i::

Transfer
7.2 I-- FUTtion

=>

""""" ""r---.::::
" ::::.......

ui

Actual Ti ansfer Function

............
r- Ideal ~
......~ ~
r- Unear

a:
~-501-~~--~~~-=~~~--~~~+---~

I~

4
6
8
10
12
VIDEO OUTPUT RESPONSE (MHz)

2:

r\\

j-601---~--4--=~---+~-4~~~--~~~

w

~
14

a:_70~__~~~-=~~~~~

-10

16

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
9-33

__

~~~~

-20
-30
-40
RELATIVE 41.25 MHz INPUT LEVEL (dB)

__

~

MC1330A
GENERAL INFORMATION
The MC1330A offers the designer a new approach to an old
problem. Now linear detection can be performed at much
lower power Signal levels than possible with a detector diode.
Offering a number of distinct advantages, its easy implementation should meet with ready acceptance for television
designs. Some specific features and information on systems
design with this device are given below:
1. The device provides excellent linearity of output versus
input, as shown in Figures 6 and 7. These graphs also
show that video peak-to-peak amplitude (AC) does not
change with supply voltage variation. (Slopes are parallel.
Visualize a given variation of input CW and use the figure as
a transfer function.)
2. The DC output level does change linearly with supply
voltage shown if Figure 8. This can be accommodated by
regulating the supply or by referencing the subsequent video
amplifier to the same power supply.
3. The choice of for the tuned circuit of Pin 2 and 3 is not
critical. The higher the a, the better the rejection of 920 kHz
products by the more critical the tuning accuracy required (see

a

a

Figure 11). Values of from 20 to 50 are recommended. (Note
the internal reSistance.)
4. A video output with positive-going sync is available at
Pin 5 if required. This signal has a higher output impedance
than Pin 4 so it must be handled with greater care. If not used,
Pin 5 may be connected directly to the supply voltage (Pin 6).
The video response will be altered somewhat (see Figure 10).
5. An AFT output (Pin 1) provides 460 mV of IF carrier
output, sufficient voltage to drive an AFT ratio detector, with
only one additional stage.
6. AGC lockout can occur if the input signal presented in the
MC1330A is greater than that shown in the input overload
section of the design characteristics shown on Page 3. If these
values are exceeded, the turns ratio between the primary and
secondary of T 1 should be increased. Another solution to the
problem is to use an input clamp diode D1 shown if Figure 14.
7. The totall.F. noise figure at high gain reductions can be
improved by reflecting = 1.0 k source impedance to the input
of the MC1330A. This will cause some loss in overall IF
voltage gain.

TV·IF AMPLIFIER INFORMATION
A very compact high performance IF amplifier constructed
as shown in Figure 14 minimizes the number of overall
components and alignment adjustments. It can be readily
combined with normal tuners and input tuning-trapping
circuitry to provide the performance demanded of high quality
receivers. This configuration will provide approximately 93 dB
voltage gain and can accommodate the usual low impedance
input network or, if desired, can take advantage of an
impedance step-up from tuner to MC1350 input.
The burden of selectivity, formerly found between the third
IF and detector, must now be placed at the interstage.
The nominal 3.0 V peak-to-peak output can be varied from 0
V to 7.0 V with excellent linearity and freedom from spurious
output products.
Alignment is most easily accomplished with an AM generator, set at a carrier frequency of 45.75 MHz, modulated with a
video frequency sweep. This provides the proper realistic

conditions necessary to operate to lOW-level detector (LLD).
The detector tank is first adjusted for maximum detected DC
(with a CW input). Next, the video sweep modulation is applied
and the interstage and input circuits aligned, step by step, as
in a standard IF amplifier.
Note: A normal IF sweep generator, essentially an FM
generator, will not serve properly without modification. The
LLD tank attempts to "follow" the sweep input frequency, and
results in variations of switching amplitude in the detector.
Hence, the apparent overall response becomes modified by
the response of the LLD tank, which a real signal doesn't do.
This effect can be prevented by reSistively adding a
45.75 MHz CW signal to the output of the sweep generator
approximately 3.0 dB greater than the sweep amplitude. See
Figures 12 and 13 below. For a more detailed description of
the MC1330A see application note AN545A.

Figure 12. Band Pass Displayed by
Conventional Sweep

Figure 13. Band Pass Display with the Addition
of Carrier Injection

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
9-34

MC1330A
Figure 14. Typical Application of MC1350P Video if Amplifier
and MC1330A Low-Level Video Detector Circuit
C6

R3
470

0.002~F

R4
220

+1 BVdc
Auxiliary Video 1BV [
Output

tOV

-l
J
--- ;:-

-J Ivvvu

Primary Video
and Sound Output

~ik7.7:[VJ

MC1330A

C10
12pF
R2

...----+.. AFT Output
3.9k
R6

T1

= AGC

LJ~··p~,.
Turn~urns

3"

M~

Irrnl~
10 I
-3"

'4

All windings #30 AWG tinned nylon acetate
wire tuned with Carbonyl E or J slugs.

Figure 15. Printed Circuit Board (Parts Layout)

Turns

Figure 16. Printed Circuit (Board Layout)

AGC

INPUT

C1~

R2

n

~~
•

•

16

L1 wound with #26 AWG tinned nylon
acetate wire tuned by distorting winding.

C3

COPPER SIDE UP

COPPER SIDE UP

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
9-35

MOTOROLA

MC1350

SEMICONDUCTOR-----TECHNICAL DATA

IF AMPLIFIER

Monolithic IF Amplifier

SILICON MONOLITHIC
INTEGRATED CIRCUIT

The MC1350 is an integrated circuit featuring wide range AGC for use as an
IF amplifier in radio and TV over an operating temperature range of 0° to +75°C.
• Power Gain: 50 dB Typ at 45 MHZ
50 dB Typ at 58 MHZ

.~

• AGC Range: 60 dB Min. DC to 45 MHz
• Nearly Constant Input & Output Admittance over the Entire AGC Range
• Y21 Constant ( -3.0 dB) to 90 MHz
• Low Reverse Transfer Admittance: < < 1.0 IJ.mho Typ

1

PSUFFIX
PLASTIC PACKAGE
CASE 626

• 12 V Operation. Single-Polarity Power Supply
MAXIMUM RATINGS (TA = +25°C. unless otherwise noted.)
Symbol

Value

Unit

Power Supply Voltage

Rating

V+

+18

Vdc

Output Supply Voltage

VI. V8

+18

Vdc

AGC Supply Voltage

VAGC

V+

Vdc

Differential Input Voltage

Vin

5.0

Vdc

Power Dissipation (Package Limitation)
Plastic Package
Derate above 25°C

Po
625
5.0

mW
mW/oC

Operating Temperature Range

TA

Oto+75

°C

DSUFFIX
PLASTIC PACKAGE
CASE 751
(S0-8)

Operating Temperature

Figure 1. Typical MC1350 Video IF Amplifier and MC1330 Low-Level Video Detector Circuit
+1 BVdc
3.3k

]

Auxi~~~deo lBV[~
10V

---

Primary Video
and Sound Output

3.9k7·~r r ]

MC1330AP

t---t-e AFT Output
3.9k

-=

T1
AGC

L]d-rJ.p~,.
Turn~urns

3N

M~

!;It.. 3

N

'4

All windings #30 AWG tinned nylon acetate
wire tuned with Carbonyl E Dr J slugs.

Turns

LI wound with 1126 AWG tinned nylon
acetate wire tuned by distorting winding.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
9-36

16

MC1350
ELECTRICAL CHARACTERICISTICS (V+ = +12 Vdc, TA = +25°C, unless otherwise noted.)
Symbol

Characteristics

Min

Typ

60

68

-

48
50
58
62

-

AGC Range, 45 MHz (5.0 V to 7.0 V) (Figure 1)
Power Gain (Pin 5 grounded via a 5.1 k.Q resistor)
See Figure 6(a)
f = 58 MHz, BW = 4.5 MHz
See Figure 6(a), (b)
f = 45 MHz, BW = 4.5 MHz
f = 10.7 MHz, BW = 350 kHz
See Figure 7
f = 455 kHz, BW = 20 kHz

Ap

Maximum Differential Voltage Swing
OdBAGC
-30 dB AGC

Vo

Output Stage Current (Pins 1 and 8)

11 + 18

-

Total Supply Current (Pins 1, 2 and 8)

IS

Power Dissipation

PD

-

Unit
dB
dB

46
-

Max

-

VH
20
8.0

-

5.6

-

14

17

mAdc

168

204

mW

rnA

DESIGN PARAMETERS, Typical Values (V+ = +12 Vdc, TA = +25°C, unless otherwise noted.)
Frequency
Parameter
Single· Ended Input Admittance

Symbol

455 kHz

10.7 MHz

45 MHz

58 MHz

Unit

gIl
bll

0.31
0.022

0.36
0.50

0.39
2.30

0.5
2.75

mmho

~911
~bll

Input Admittance Variations with AGC
(0 dB to 60 dB)
Differential Output Admittance

922
b22

-

-

4.0
3.0

4.4
110

30
390

60
510

Ilmho

-

-

4.0
90

-

Ilmho

-

60
0

Ilmho

-

Output Admittance Variations with AGC
(0 dB to 60 dB)

~g22

Reverse Transfer Admittance (Magnitude)

IY121

< < 1.0

< < 1.0

< < 1.0

< < 1.0

Ilmho

Forward Transfer Admittance
Magnitude
Angle (0 dB AGC)
Angle (-30 dB AGC)

IY211
< Y21

160
-20
-18

200
-80
-69

180
-105
-90

mmho
Degrees
Degrees

~b22

< Y21

160
-5.0
-3.0

Single·Ended Input Capacitance

Cin

7.2

7.2

7.4

7.6

pF

Differential Output Capacitance

Co

1.2

1.2

1.3

1.6

pF

Figure 3. Noise Figure versus Gain Reduction

Figure 2. Typical Gain Reduction

o
ar

~ 20

IAGC=~ -...........

~
"

o
;::

g
c

40

;;!;

60

w
a:

(§

(~igures 6 an~ 7)

80
4.0

22
20
~ 18
ti! 16
14
~ 12
~ 10
z 8.0

a

""-rnA'---

IAGC = 0j2

5.0
6.0
VAGC, SUPPLY VOLTAGE M

58MHlz~ lL
I-"'"

7.0

6.0

~

~ i-"""
45 MHz
~ I-""

(Figure6)

-

.."., , /

I

V"'""
a

10

20
GAIN REDUCTION (dB)

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

9-37

/

/

30

I
40

MC1350
GENERAL OPERATING INFORMATION
The input amplifiers (01 and 02) operate at constant emitter
currents so that input impedance remains independent of
AGC action. Input signals may be applied single-ended or
differentially (for AC) with identical results. Terminals 4 and 6
may be driven from a transformer, but a DC path from either
terminal to ground is not permitted.

AGC action occurs as a result of an increasing voltage on
the base of 04 and 05 causing these transistors to conduct
more heavily thereby shunting signal current from the
interstage amplifiers 03 and 06. The output amplifiers are
supplied from an active current source to maintain constant
quiescent bias thereby holding output admittance nearly
constant. Collector voltage for the output amplifier must be
supplied through a center-tapped tuning coil to Pins 1 and 8.
The 12 V supply (V+) at Pin 2 may be used forthis purpose, but
output admittance remains more nearly constant if a separate
15 V supply (V+ +) is used, because the base voltage on the
output amplifier varies with AGC bias.

Figure 4. Circuit Schematic
AGe Amplifier Section

Figure 5. Frequency Response Curve
(45 MHz and 58 MHz)

, / ..........

-

7

V

Input Amplifier Section

Bias Supplies

V

-

t"\.

" ."
~

Scale:l.0MHzJcm

-

Output Amplifier Section

Figure 6. Power Gain, AGC and Noise Figure Test Circuits
(a) 45 MHz and 58 MHz

(b) Alternate 45 MHz

5.1k

O.OOl~F

O.OOl~F

·Connect to ground for maximum power gain test.
All power supply chokes (Lp), are self-resonant at input frequency. Lp ;0, 20 kD.
See Figure 5 for Frequency Response Curve.
L1 @ 45 MHz = 7 1/4 Turns on a 1/4" coil form
@58 MHz = 6 Turns on a 1/4" coil form
TI Primary Winding = 18 Turns on a 1/4" coil form, center-tapped, #25 AWG
Secondary Winding = 2 Turns centered over Primary Winding @ 45 MHz
= I Turn@58MHz
Slug = Carbonyl E or J

LI
Tl
Cl
C2

45 MHz
Q~ 100
0.4 ~H
I
1.3 ~H to 3.4 ~H I Q ~ 100 @ 2.0 ~H
50 pF to160 pF
8.0 pF to 60 pF

LI

Ferrite Core
14 Turns 28 S.W.G

CI
C2
C3

5-25 pF
5-25 pF
5-25pF

58 MHz
Q~ 100
I
1.2 ~H to 3.8 ~H I Q ~ 100@ 2.0 ~H
8.0 pF to 60 pF
3.0 pF to 35 pF

0.3~H

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
9-38

~

---

MC1350

Figure 7. Power Gain and AGC Test Circuit
(455 kHz and 10.7 MHz)

Input
RS= 500

Ll

12V

Output
RS =500

VAGC·

Frequency
455 kHz
10.7 MHz
81l-4S0 pF
5.O-80pF
O.OSIlF
O.OOIIlF
O.OSIlF
O.OSIlF
36pF
O.OOIIlF
O.OSIlF
O.OSIlF
O.OSIlF
O.OSIlF
4.61lF
Note 1
Note 2

Component
Cl
C2
C3
C4
CS
C6
C7
Ll
Tl

NOTES: 1. Primary: 120 ~H (conler·lapped)
au = 140 al455 kHz
Primary: Secondary turns ratio"" 13

_--VVlr-+-'"

'Grounded for
maximum power gain.

2. Primary: 6.0 ~H
Primary winding = 24 turns #36 AWG
(close-wound on 1/4'" dia. form)

Core = Carbonyl E or J
Secondary winding = 1·1/2 turns #36 AWG, 1/411 dia.
(wound over center-tap)

Figure 8. Single-Ended Input Admittance
S.O

.§.

SOO

J
/

4.0

IE

Figure 9. Forward Transfer Admittance

bl1

V

1.0

o

10

- ----

20

/

IE

gil
40

~

.....

SO

...,.."

_V

1.0

2.0

f- (Sin~le~nded o~put
admittance exhibHs
0.8 r- twice th se valu 5.)

"§

b22

.§. 0.6

V

~

V

V

~

w 7.0

/

- 0.4

~

0.2

o

10

--

-

20

922

---

30
40 SO
f, FREQUENCY (MHz)

i-""'

V

70

!:3

6.0

!5

S.O

1=
g

4.0

~

3.0

~

1..;' .....

........ i-"""

-120 N

~

>-

'J

-160

30

-200
100

SO

I\.

(!l

..;

.<>

'"

8.0

1/

'S

ffi

Figure 11. Differential Output Voltage

Figure 10. Differential Output Admittance
1.0

3.0 S.O
10
20
f, FREQUENCY (MHz)

V

""- ..............
"- .............,..

II\.

V++ =14V

"'""""
V++ =12V

~ 2.0
~
~ 1.0

o
o

100

10

20

30
40
SO
GAIN REDUCTION (dB)

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
9-39

m~
e.

Y21

o

100

70

-80

I'

100

o
-40

~

300

~ 200

....... i-""'
30

,,~

.§.

. / V"

f, FREQUENCY (MHz)

L Y21 (-30 dB gain)

L Y21 (max gain) "

1/"

.i[ 2.0

I

400

/

3.0

III

60

70

80

MOTOROLA

MC1357

SEMICONDUCTOR-----TECHNICAL DATA

TV Sound IF or FM IF Amplifier
with Quadrature Detector

IF AMPLIFIER
WITH QUADRATURE
DETECTOR
SILICON MONOLITHIC
INTEGRATED CIRCUIT

• A Direct Replacement for the ULN211 A
• Greatly Simplified FM Demodulator Alignment

...

• Excellent Performance at Vee = B.O Vdc

1

PSUFFIX
PLASTIC PACKAGE
CASE 646

Figure 1. TV Typical Application Circuit

+22V

820

+

0

Cl

~

11

O.I~F

~

5.0~F

4

O.I~F

-=

J

+

0.1

3.0pF
100~F

Rl
13

2

MC13060
12

160

4

Inpul

3
MC1357

51
330
6.8

Typical Performance
2.0WOutput
2% Distortion
250 ~V Sensitivity (3 dB Urn.)

Cl =120pF
11

= 14 ~H

Rl =20 kO
Q =30

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

9-40

MC1357
MAXIMUM RATINGS (TA = +25°C, unless otherwise noted.)
Value

Unit

Power Supply Voltage

Rating

16

Vdc

Input Voltage (Pin 4)

3.5
625
5.0

Vp
mW
mW/oC

Power Dissipation (Package Limitation)
Plastic Package Derate above TA = +25°C

oto +70

°c

-65 to +150

°c

Operating Temperature Range (Ambient)
Storage Temperature Range

ELECTRICAL CHARACTERICISTICS (VCC = 12 Vdc, TA = +25°C, unless otherwise noted.)
Characteristics
Drain Current

VCC =8.0V
VCC=12V

Pin

Min

Typ

Max

Unit

13

10

12
15

19
21

mA

Amplifier Input Reference Voltage

6

Detector Input Reference Voltage

2

-

Amplifier High Level Output Voltage
Amplifier Low Level Output Voltage

10

1.25

Detector Output Voltage

9
1

VCC =8.0V
VCC=12V

-

Vdc

3.65
1.45

1.65

Vdc

1.45

Vdc

-

0.145

0.2

Vdc

--

3.7
5.4

-

Vdc
k.Q

Amplifier Input Resistance

4

-

5.0

-

Amplifier Input Capacitance

4

-

11

-

pF

Detector Input Resistance

-

70
2.7

-

k.Q

-

pF

Detector Input Capacitance

12
12

Amplifier Output Resistance

10

-

Detector Output Resistance

1

-

200

De-Emphasis Resistance

14

-

8.8

60

n
n
k.Q

DYNAMIC CHARACTERICISTICS FM Modulation Frequency = 1.0 kHz, Source Resistance = 50 n, TA = +25°C for all tests.
(VCC 12 Vdc, fo 4.5 MHz, Af ±25 kHz, Peak Separation 150 kHz)

=

=

=

=

Characteristics

·Pin

Min

Typ

Max

Unit

Amplifier Voltage Gain (Vin S 50 I1V[rms])

10

-

60

-

AM Rejection· (Vin = 10 mV[rms])

1

-

36

-

dB

Input Limiting Threshold Voltage

4

-

250

I1Vnm S
Vrms

dB

Recovered Audio Output Voltage (Vin = 10 mV[rms])

1

-

0.72

-

Output Distortion (Vin = 10 mV[rms])

1

-

3.0

-

%

dB

=

=

=

(VCC 12 Vdc, fo 5.5 MHz, AI ±SO kHz, Peak Separation
Amplifier Voltage Gain (Vin S 50 I1V[rms])

=260 kHz)
10

-

60

-

AM Rejection· (Vin = 10 mV[rms])

1

-

40

-

dB

Input Limiting Threshold Voltage

-

-

250
1.2

-

Recovered Audio Output Voltage (Vin = 10 mV[rms])

4
1

-

I1Vnms
Vrms

Output Distortion (Vin = 10 mV[rms])

1

-

5.0

-

%

dB

=

=

=

(VCC 8.0 Vdc, fo 10.7 MHz, AI ±75 kHz, Peak Separation
Amplifier Voltage Gain (Vin S 50 I1V[rms])

=550 kHz)
10

-

53

-

AM Rejection· (Vin = 10 mV[rms])
Input Limiting Threshold Voltage

1
4

-

-

dB

-

37
600

-

Recovered Audio Output Voltage (Vin = 10 mV[rms])

1

-

0.3

Output Distortion (Vin = 10 mV[rms])

1

-

-

I1Vrm S
Vrms

1.4

-

%

-

dB

(VCC

=12 Vdc, fo =10.7 MHz, AI =±75 kHz, Peak Separation =550 kHz)

Amplifier Voltage Gain (Vin S 50 I1V[rms])
AM Rejection· (Vin = 10 mV[rms])

10

-

53

1

-

45

Input Limiting Threshold Voltage

4

-

600

-

Recovered Audio Output Voltage (Vin = 10 mV[rms])

1

-

0.48

Output Distortion (Vin = 10 mV[rms])

1

-

1.4

-

NOTE: ·100% FM, 30% AM Modulation

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
9-41

dB
I1Vrms
Vrms
%

MC1357
TYPICAL CHARACTERISITICS
(VCC = 12 V, TA = +25°C, unless otherwise noted.)
(Use Test Circuit of Figure 13)

Figure 2. AM Rejection
60

IIII
I I I
(10 =4.S MHz)

so

is

40

~

30

~
~

20
10
O.OS

~

V

t'

V

60

II IIII
ReI. Signal Input
Pin 10
~

'-

\.

Figure 3. AM Rejection

""'

-

is

40

~

30

~

Input (Pin 9

0.2

O.S 1.0
2.0
S.O
INPUT VOLTAGE (mVrms)

"-

10

V

10
O.OS

so

Figure 4. Detected Audio Output

~ 0.8

~

0.6

5

0.S

....

ReI. Signal Input (Pin 9)

Rei. Signal
Input (Pin 9

100% FM, 30% AM
(10 = S.S MHz)

IIIIII
IIIIII
0.1

0.2

O.S 1.0
2.0
S.O
INPUT VOLTAGE (mVrms)

1.1

g

1.0

....

10

so

20

5

/
±2S kHz Deviation

IIIIIII

I

0.04 0.1

0.4
1.0
4.0
INPUT VOLTAGE (mVrms)

10

0.8

/

/
±SO kHz Deviation _

JI IHIIII

If

<.)

Iii 0.4

II IIII

0

I

~ 0.7
~ 0.6
c
I!:! O.S

/

II"

/

~ 0.9

I

Iii 0.1
c

V

ReI. Signal Input (Pin 9)

~

'-'

~ 0.4

~ 0.3
c
~ 0.2

,r

11.3
w 1.2

w 0.9

(!)

0.7

......

Figure 5. Detected Audio Output

11.0

g

-

"- ........

~

V

20

20

ReI. Signal Input
(Pin 10)

V"

~

100% FM, 30% A
(10 =4.S MHz)

II III
0.1

~

so

V
/"ReI. Signal

-

"ll~ = s.sIMH~) I

II IIII

c 0.3
40

0.02

Figure 6. Detector Transfer Characteristic

0.1

0.2
1.0 2.0
INPUT VOLTAGE (mVrms)

Figure 7. Detector Transfer Characteristic

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

9-42

10

20

MC1357
TYPICAL CHARACTERISITICS (continued)
(fa

= 10.7 MHz, TA = +25°C, unless otherwise noted.)
(Use Test Circuit of Figure 13)

Figure 8. AM Rejection

Figure 9. AFC Voltage Drift
1600
§. 400

50
40

is

-.-

'".

J

A'
,

30

~

(!)

1"1

~ 20

!:§

200

!5
c..
!5

100

g

8' ~
1

J.I't'!"

w

l

, C =J2t

g

FM, O%AM

a

~

1I

~ 20

o

0.5

1.0

2.0

5.0
10
20
50 100 200
Vin, INPUT VOLTAGE (mVrms)

500

6.0
0.01 0.02 0.05 0.1 0.2 0.5 1.0 2.0 5.0 10 20
Vin, INPUT SIGNAL VOLTAGE (mVrms)

,. ~

~

V
,/

z

t!j 0.98

!:§

0.97

o

/

~
rn

~
DC level = 5.36 V @+25°C
Input Carrier = 1.0 mV
V+ = 12Vdc

I

I

I

-

I

-10

10

30
50 70
90 110 130
TA, AMBIENT TEMPERATURE (OC)

60

VCC= 12V

az

640

~-

~

~ 20

o
> 0.96

0.95
-30

Llt = 25 kHz
I - - Mod
f= 1.0 kHz

;::;

/1"'"

1.00
[§ 0.99

II 1111
II 1111

~80

",/

:0

50 100

Figure 11. Signal-to-Noise Ratio

1.04

1.01

niIIl

c

100

~ 1.02

m Inntlimr@

II

10

Figure 10. Limiting

gj
+ 1.03

.lllt J

±75 kHz Deviation
I I III

1111111

;

1.05

'"w

8.0

60
40

10

P

IlJll""

VCC = 12V

150

8.0V

/. ~

o~

170

I-.:::

0.01

0.02

0.05

0.1 0.2
0.5 1.0 2.0
Vin, INPUT SIGNAL VOLTAGE (mV)

10

Figure 13. Test Circuit
Figure 12. Detector Transfer Characteristic
Cl

1.5

2:
w

C2 is connected to Pin 9
unless otherwise noted.

1.0

(!)

!:3

0.5

g
!5
o~

-0.5
Out

-1.0

.

-1.5
10.45 10.5 10.55 10.6 10.65 10.7 10.75 10.8 10.85 10.9

10.95

t, FREQUENCY (MHz)

COMPONENT VALUES
f

Ll

Cl

Rl

MHz

~H

pF

kn

4.5
5.5
10.7

14
8.0
2.0

120
100
120

20
20
3.9

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

9·43

Q(Rl,Ll)

30
30
20

C2

C3

pF

~F

3.0
3.0
4.7

0.003
0.003
0.01

MC1357
Figure 14. FM Radio Typical Application Circuit

2
AGe In

o--~VVI.--(}-j

Audio
Output

560
4.7pF

120pF

son

2k

Input
0.05
llF

Figure 15. Output Distortion
5

~

Note 1:
Information shown in Figures IS, 16, and 17 was obtained using the
circuit of Figure 14.

z

0

i=
a:

4

0

t;;

Note 2:
Optional input to the quadrature coil may be from either Pin 9 or
Pin 1Ointheapplicationshown. Pin9hascommonlybeen used on this
type of part to avoid overload with various tuning techniques. For this
reason, Pin 9 is used in tests on the preceding pages (except as
noted). However, a significant improvement of limiting sensitivity can
be obtainea using Pin 10, see Figure 17, and no overload problems
have been incurred with this tuned circuit configuration.

Ci
<.:>

~"""'
Input
(Pin 10

~w

,.,.

C/)

50

~

~ 40

..!I

;li

~

...... ~

/'

,/

r\

V

'30
100
300
INPUT SIGNAL VOLTAGE (llVrms)

1000

Figure 17. Recovered Audio Output

g

700

~

600

~

o
o

/

Ci

500
400

~

300

~

200

-

~ 100
to

..........

;:!:
~

!:§

Ref Signal Input (Pin 9)

30
20

Ref Signal
Input
(Pin 9)

1000
§. 900
w
C!l
800

II II

o

\

-'

I

Ref Signal Input (Pin 10)

~60

~

\

«
:J:

10

Figure 16. Signal-to-Noise Ratio

'-

\

Z

0

::;;
a:

o

70

II II
1\ II II

30
100
300
Vin,lNPUT SIGNAL VOLTAGE (llVrms)

1000

&l

a:

0
10

......

,.,.

Ref Signal Input (Pin 10)

...... ~
i-"

30
100
300
Vin, INPUT SIGNAL VOLTAGE (llVrms)

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

9-44

Ref Signal Input (Pin 9) -

1000

MC1357
Figure 18. Circuit Schematic
Input Signal Voltage (mV)

2

l
~

1.0k

1.0k

.-(

H

irK>
6

.
.
..

ltf-(~

j/

2k

500

2.5k

y
t-..
.. 450
2k

..

500

50

n

2.5k

~

(

6

7

10

9

11

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
9-45

J..

1200

t-..

4.0k
500

200
200

Kr1 ~'4

5

S.Sk

t---

1.0k

13

J

3.0k

~

~~

12

14

~
~

1
I---()

S.Ok

5.0k

MOTOROLA

MC1373

SEMICONDUCTOR-----TECHNICAL DATA

TV VIDEO
MODULATOR CIRCUIT

TV Video Modulator
The MC1373 is an RF oscillator and dual-input modulator to generate a TV
signal from baseband video inputs.
Applications include video games, home computer display, video tape
recorders, and test equipment.
The very low level of intermodulation products, compact package and small
external component count make this device superior to simple discrete circuits.
• Single 5.0 Vdc Supply
• Channel 3 or 4 Operation
• Excellent Oscillator Stability to 100 MHz
• Color and Sound Compatibility
• Dual Input Modulator for Ease of Signal Handling
• Low Intermodulation (-50 dB, 920 kHz Beat)
• Overmodulation Protection

SILICON MONOLITHIC
INTEGRATED CIRCUIT

"~
PSUFFIX
PLASTIC PACKAGE
CASE 626
PIN CONNECTIONS

MAXIMUM RATINGS (TA = 25°C, unless otherwise noted.)
Rating
Value
Supply Voltage
8.0
Operating Ambient Temperature Range
oto +70
Storage Temperature Range
-65 to +150
Junction Temperature
150
Power Dissipation Package
1.25
Derate above 25°C
10

RFTank

Unit
Vdc
°C
°C
°C
W
mWfOC

NC

RFTank
Gnd
Video Input

4 L..-_ _- - '

Figure 1. Block Diagram and Application Circuit
R2
240

56PF~ i ~
I

1

I

O.II!H

2

-:!:-

R3
240
1.0 V 0.35 V
OV-

r-""l-l
L

-.J

3

-1

~

4 -ComposHa 0

Vidao Input
Soundl ----J
Chroma ~
Input
O.II!F

5

R4 Io.oOII!F
240 -=

6

RF
Oscilal1or

vccJ:.

~

1

RI
75
7

RF
Modulator

RF
Output

l

o.001 1!F

I

I

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
9-46

VSB
Riter

Sound/Chroma
Input

MC1373
RECOMMENDED OPERATING CONDITIONS
Supply Voltage

5.0

Vdc

Luma Input Voltage - Sync Tip
Peak White

1.0
0.35

Vdc

ELECTRICAL CHARACTERICISTICS (VCC = +5 Vdc, TA = 25'C, Test Circuit 1 unless otherwise noted.)
Characteristics
Operating Supply Voltage

Min

Typ

Max

4.75

5.0

5.25

-

Supply Current

12

-

Unit
V
rnA

RF MODULATOR

-

1.5

-

15

-

mVrms

Luma Conversion Gain
(I1V71I'N4, V4 = 0.1 Vdc to 1.0 Vdc) (See Figure 3)

-

0.8

-

VN

Chroma Conversion Gain
(I1V71I1V5; V5 = 1.5 Vp-p;V4 = 1.0 Vdc) (See Figure 3)

-

0.95

-

Chroma Linearity
(Pin 7, V5 = 1.5 Vp-p) (See Figure 3)

-

1.0

-

%

Luma Linearity
(Pin 7, V4 = a Vdc to 1.5 Vdc) (See Figure 3)

-

2.0

-

%

Luma Input Dynamic Range (Pin 4, see Figure 3)

a

RF Output Voltage
(f = 67.25 MHz, V4 = 1.0 V)

V

VN

Input Current (Pin 4)

-

-

-20

Input Resistance (Pin 5)

-

800

-

I1A
n

Input Resistance (Pin 4)

100

kn

-

-

-

Input Capacitance (Pins 4, 5)

5.0

pF

Residual 920 kHz (Measure at Pin 7) (Note 1)

-

60

dB

Output Current (Pin 7, V4 = a V) (See Figure 3)

-

1.5

-

rnA

TEMPERATURE CHARACTERISTICS (VCC = 5.0 V, TA = 0' to 70'C, IC only)
RF Oscillator Deviation
(fo = 67.25 MHz)
NOTES: 1. RF Reference Level = 6.0 mV @ Pin 7. Load Impedance = 75 n
RF + 4.5 MHz = -13 dB.
RF + 3.58 Mhz = -20 dB.

Figure 2. Test Circuit 1

-

240

240

o. OII1F

Figure 3. Test Circuit 2

l

+7.0V

.

O.II1H

56pF

240

RFOutput

lN4001

Q

1

8 NC

2

7

2.0k
VideoOu!put
V7
+S.OV

u

8 NC
2

V4

7

3

6

4

5

~

75
+5.0V

3

6

V4D-- 4

5
360

Vc
90

90

f:-----o VS
O.II1F

I

+

I

1Ol1F

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

9·47

IOI1F

MC1373
Figure 4. Schematic Diagram
Luma
Input
4

6

Chrominanca
Input
5

RF Modulator
Output
7

RF
Tank

I

VCCO-~--"------~+---~~------~4-----'---~r-~--~--'

RI
1.5k
R1S
3.4k
01

RS
500

500

R4
R2
3.4k

Ground

R12

3

RI3

R14

R16

o--+---+--~'----+----'------'----'--'------'

SCHEMATIC DESCRIPTION
The RF oscillator consists of differential amplifier 013 and
014 cross-coupled through emitter followers all and 012.
The oscillator will operate at the parallel resonant frequency of
the network connected between Pins 1 and 2. The oscillator
output is used to switch the doubly balanced RF modulator, 04
through 01 O. Transistors 02 and 03 provide level shifting and
a high input impedance to the luminance input Pin 4. The
bases of transistors 04 and
are both biased through
resistors R4 and R5, respectively, to the same DC reference
voltage at 01 emitter. The base voltage at
may only be
offset in a negative direction by luminance signal current
source 03. This design insures that overmodulation due to the
luminance signal will never occur. The chrominance signal is
externally AC coupled to Pin 5 where it is reduced by resistor
dividers R7 and R4, and added to the luminance signal in 04.
The resultant differential composite video currents are
switched at the appropriate RF frequency in 07 through 010.
The output signal current is presented at Pin 7.
Transistors 015, 016 and resistors R15, R16 provide
a highly stable voltage reference for biasing the current
source 06.

as

as

OPERATIONAL DESCRIPTION
Pins 1 and 2 - RF Tank. A tuned circuit connected
between these pins determines the RF oscillator frequency.
The tuned circuit must provide a low DC resistance shunt.
Applying a DC offset voltage between these pins results in
baseband composite video at the RF Modulator Output.
Pin 3 - Ground.
Pin 4- Luminance Input. Input to RF modulator. This pin
accepts a DC coupled luminance and sync signal. The
amplitude of the RF signal output increases with positive
voltage applied to the pin, and ground potential results in zero
output (I.e., 100% modulation). A signal with positive-going
sync should be used.
Pin 5 - Chrominance/Sound Input. Input to the RF
modulator. This pin accepts an AC coupled chrominance

signal. The signal is reduced by and internal resistor divider
before being applied to the RF modulator. The resistor divider
consists of a 300 n series resistor and a 500 n shunt resistor.
A 4.5 MHz FM audio signal may be added to the input by
selecting an appropriate series input resistor to provide the
correct Luminance:Sound ratio.
Pin 6 - VCC. Positive supply Voltage.
Pin 7 - RF Modulator Output. Common collector of
output modulator stage. Output impedance and stage gain
may be selected by choice of resistor connected between this
pin and DC supply.
Pin 8 - No Connection.
APPLICATIONS INFORMATION
RF Modulator and Oscillator
The coil and capacitor connected between Pins 1 and 2
should be selected to have a parallel resonance at the carrier
frequency of the desired TV channel. The values of 56 pF and
0.1 /lH shown in Figure 1 were chosen for a Channel 4 carrier
frequency of 67.25 MHz. For Channel 3 operation, the
resonant frequency should be 61.25 MHz (C = 75 pF, L =
O.I/lH). Resistors R2 and R3 are chosen to provide an
adequate amplitude of switching voltage, whereas R4 is used
to lower the maximum DC level of switching voltage below
VCC, thus preventing saturation within the IC.
Composite Luminance and Sync should be DC coupled to
Luminance Input, Pin 4. This signal must be within the Luma
Input Dynamic Range to insure linearity. Since an increase in
DC voltage applied to Pin 4 results in an increase in RF output,
the input signal should have positive-going sync to generate
an NTSC compatible signal. As long as the input signal is
positive, overmodulation is prevented by the integrated circuit.
Chrominance information should be AC coupled to Chrominance Input, Pin 5. This pin is internally connected to a resistor
divider consisting of a series 300 n and a shunt 500 n resistor.
The input impedance is thus 800 n, and a coupling capacitor
should be appropriately chosen.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

9-48

MOTOROLA

MC1374

SEMICONDUCTOR-----TECHNICAL DATA

TV MODULATOR CIRCUIT

TV Modulator Circuit
SILICON MONOLITHIC
INTEGRATED CIRCUIT

The MC1374 includes an FM audio modulator, sound carrier oscillator, RF
oscillator, and RF dual input modulator. It is designed to generate a TV signal
from audio and video inputs. The MC1374's wide dynamic range and low
distortion audio make it particularly well suited for applications such as video
tape recorders, video disc players, T.V. games and subscription decoders.
• Single Supply, 5 V to 12 V
• Channel 3 or 4 Operation
• Variable Gain RF Modulator
II Wide Dynamic Range
•
•
•
•

Low Intermodulation Distortion
Positive or Negative Sync
Low Audio Distortion
Few External Components

PSUFFIX
PLASTIC PACKAGE
CASE 646

Figure 1. Typical Application

v
+Vcc = 12V

4

- - - - - - - - - - VPinl

3

"1 .1'-"1 .1
__][ ____If__

VPln 11

C9
0.001

:J

Rl

470

T

• t

R7
750

R9
560

+

Rll

220
R4

6.ak

' - - - - - - - < J Video In

14
R5
3.3k

R6
2.2k
Shaded Parts Optional

--~ f-(- - - - 0 Audio In
C6
ll1F

L1 - 4 Turns #22, 1/4" Dia.
l2 - 40 Turns, #36, 3/16" Dia

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

9-49

MC1374
MAXIMUM RATINGS (TA = 25°C, unless otherwise noted.)
Rating
Supply Voltage
Operating Ambient Temperature Range
Storage Temperature Range
Junction Temperature
Power Dissipation Package
Derate above 25°C

ELECTRICAL CHARACTERICISTICS (VCC

I

Value

Unit

14

Vdc

oto +70

°c

-65 to +150

°c

150

°C

1.25
10 mW;oC

W

= 12 Vdc, TA = 25°C, fc = 67.25 MHz, Figure 4 circuit, unless otherwise noted.)
I Min I Typ I Max I

Characteristics

Unit

AM OSCILLATOR/MODULATOR
Operating Supply Voltage

12

5.0
-

Supply Current (Figure 1)

0.25

Video Input Dynamic Range (Sync Amplitude)

12

13

-

1.0

1.0

V
mA
V Pk

RF Output (Pin 9, R7 = 75 Q, No External Load)

-

170

Carrier Suppression

36

40

-

Linearity (75% to 12.5% Carrier, 15 kHz to 3.58 MHz)

-

-

2.0

Differential Gain Distortion (IRE Test Signal)

5.0

7.0

10

%

Differential Phase Distortion (3.58 MHz IRE Test Signal)

-

1.5

2.0

Degrees

920 kHz Beat (3.58 MHz @ 30%, 4.5 MHz @ 25%)

-

-57

-

dB

Video Bandwidth (75 Q Input Source)

30

-

-

MHz

Oscillator Frequency Range

-

105

-

MHz

1.8
4.0

-

kQ
pF

Internal Resistance across Tank (Pin 6 to Pin 7)
Internal Capacitance across Tank (Pin 6 to Pin 7)

ELECTRICAL CHARACTERICISTICS (TA

I

-

mVpp
dB
%

-

= 25°C, VCC = 12 Vdc, 4.5 MHz, Test circuit of Figure 11, unless otherwise noted.)

Characteristics

I

Min

I

Typ

I

Max

I

Unit

FM OSCILLATOR/MODULATOR
Frequency Range of Modulator
Frequency Shift versus Temperature (Pin 14 open)
Frequency Shift versus VCC (Pin 14 open)
Output Amplitude (Pin 3 not loaded)
Output Harmonics, Unmodulated

-

14

Modulation Sensitivity

1.7MHz
4.5 MHz
10.7 MHz

-

Audio Distortion (±25 kHz Deviation, Optimized Bias Pin 14)
Audio Distortion (±25 kHz Deviation, Pin 14 self biased)
Incidental AM (±25 kHz FM)

-

Audio Input Resistance (Pin 14 to ground)
Audio Input Capacitance (Pin 14 to ground)

-

Stray Tuning Capacitance (Pin 3 to ground)
Effective Oscillator Source Impedance (Pin 3 to load)

-

-

4.5
0.2

900

0.20
0.24
0.80

-

-

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

9-50

14
0.3
4.0

-40

-

MHz
kHz/DC
kHz/V
mVp-p
dB
MHZ/V

-

0.6
1.4
2.0

1.0

6.0
5.0

-

5.0
2.0

-

%

-

-

-

kQ
pF
pF
kQ

MC1374
Figure 2. TV Modulator

Bias
Section

FM Oscillator/Modulator
Sound Carrier
OSC B+

4

14,?

Rll

RIO

n

3

R12

AM Oscillator

VCC

RFOut

S~

9

RFTank

7

O~
ii

t-P7

01
R13
325

~
R17

"025

~024

"

6

J
~~Jr*~ ~~

R16

6.0k

AM Modulator

Sound Carrier
Oscillator

Audio In

,.....022

C~

~ ~3r

R14

h03

V-

--~4

R15

~026

o23

V 027

h

f....

~

I

OS

f....

~
Rl

R2

R3

R4

50

R5
1

Gnd

Sound Carrier
In

"
or

+13

~

~

:

~

Dl

i"'"' 016 i"'"' 017
~1 S
......
......

~

R6
12
Gain

"
or

~
R7

+
11

RS

"

~ R9

+

Video In

GENERAL INFORMATION
The MC1374 contains an RF oscillator, RF modulator, and
a phase-shift type FM modulator, arranged to permit good
printed circuit layout of a complete T.V. modulation system.
The RF oscillator is similar to the one used in MC1373, and is
coupled internally in the same way. It's frequency is controlled
by and external tank on Pins 6 and 7, or by a crystal circuit, and
will operate to approximately 105 MHz. The video modulator
is a balanced type as used in the well known MC1496.
Modulated sound carrier and composite video information can
be put in separately on Pins 1 and 11 to minimize unwanted
crosstalk. A single resistor on Pins 12 and 13 is selected to set
the modulator gain. The RF output at Pin 9 is a current source
which drives a load connected from Pin 9 to VCC.
The FM system was designed specifically for the T.V.
intercarrier function. For circuit economy, one phase shift
circuit was built into the ship. Still, it will operate from 1.4 MHz
to 14 MHz, low enough to be used in a cordless telephone

base station (1.76 MHz), and high enough to be used as an FM
IF test signal source (10.7 MHz). AT 4.5 MHz, a deviation of
±25 kHz can be achieved with 0.6% distortion (typical).
In the circuit above devices 01 through 07 are active in the
oscillator function. Differential amplifier 03, 04, 05, and 06
acts as a gain stage, sinking current from input section 01 , 02
and the phase shift network R17, C1. Input amplifier 01, 02
can vary the amount of "in phase" 04 current to be combined
with phase shifter current in load resistor R16. The R16
voltage is applied to emitter follower 07 which drives an
external L-C circuit. Feedback from the center olthe L-C circuit
back to the base of 06 closes the loop. As audio input is
applied which would off-set the stable oscillatory phase, the
frequency changes to counteract. The input to Pin 14 can
include a DC feedback current for AFC over a limited range.
The modulated FM signal from Pin 3 is coupled to Pin 1 of
the RF modulator and is then modulated onto the AM carrier.

MOTOROLA LlNEARIiNTERFACE ICs DEVICE DATA
9-51

MC1374
AM Section
The AM modulator transfer function in Figure 3 shows that
the video input can be of either polarity (and can be applied at
either input). When the voltages on Pin 1 and Pin 11 are equal,
the RF output is theoretically zero. As the difference between
VPin 11 and VPin 1 increase, the RF output increases linearly
until all of the current from both 11 current sources (08 and 09)
is flowing in one side of the modulator. This occurs when
±(VPin11-VPin1) = 11 RG, where 11 is typically 1.15 mAo The
peak-to-peak RF output is the 211 RL. Usually the value of RL
is chosen to be 75 n to ease the design of the output filter and
match into T.V. distribution systems. The theoretical range of
input voltage and RG is quite wide, but noise and available
sound level limit the useful video (sync tip) amplitude to
between 0.25 Vpk and 1.0 Vpk. It is recommended that the
value of RG be chosen so that only about half of the dynamic
range will be used at sync tip level.
The operating window of Figure 5 shows a cross-hatched
area where Pin 1 and Pin 11 voltages must always be in order
to avoid saturation in any part of the modulator. The letter 
represents one diode drop, or about 0.75 V. The oscillator Pins
6and7mustbebiasedtoaievelofVcc -  - 211 RL(orlower)
and the input Pins 1 and 11 must always be at least 2<1> below
that. It is permissible to operate down to 1.6 V, saturating the
current sources, but whenever pOSSible, the minimum should
be 3<1> above ground.
The oscillator will operate dependably up to about 105 MHz
with a broad range of tank circuit components values. It is
desirable to use a small L and a large C to minimize the
dependence on IC internal capacitance. An operating 0
between 10 and 20 is recommended. Thevalues of R1, R2 and
R3 are chosen to produce the desired 0 and to set the Pin 6
and 7 DC voltage as discussed above. Unbalanced operation;
i.e., Pin 6 or 7 bypassed to ground, is not recommended.
Although the oscillator will still run, and the modulator will
produce a useable signal, this mode causes substantial
base-band video feedthrough. Bandswitching, as Figure 1
shows, can still be accomplished economically without using
the unbalanced method.
The oscillator frequency with respect to temperature in the
test circuit shows less than ±20 kHz total shift from 0° to 50°C
as shown in Figure 7. At higher temperatures the slope
approaches 2.0 kHz/oC. Improvement in this region would
require a temperature compensating tuning capacitor of the
N75 family.
Crystal control is feasible using the circuit shown in Figure
21. The crystal is a 3rd overtone series type, used in series
resonance. The L 1, C2 resonance is adjusted well below the
crystal frequency and is suffiCiently tolerant to permit fixed
values. A frequency shift versus temperature of less than
1.0 Hz/oC can be expected from this approach. The resistors
Ra and Rb are to suppress parasitic resonances.
Coupling of output RF to wiring and components on Pins 1
and 11 can cause as much as 300 kHz shift in carrier (at 67
MHz) over the video input range. A careful layout can keep this
shift below 10kHz. Oscillator may also be inadvertently
coupled to the RF output, with the undesired effect of
preventing a good null when V11 = V1. Reasonable care will
yield carrier rejection ratios of 36 dB to 40 dB below sync tip
level carrier.
.

In television, one of the most serious concerns is the
prevention of the intermodulation of color (3.58 MHz) and
sound (4.5 MHz) frequencies, which causes a 920 kHz signal
to appear in the spectrum. Very little (3rd order) nonlinearity is
needed to cause this problem. The results in Figure 6 are
unsatisfactory, and demonstrate that too much of the available
dynamic range of the MC1374 has been used. Figures 8 and
10 show that by either reducing standard signal level, or
reducing gain, acceptable results may be obtained.
At VHF frequencies, small imbalances within the device
introduce substantial amounts of 2nd harmonic in the RF
output. At 67 MHz, the 2nd harmonic is only 6 dB to 8 dB below
the maximum fundamental. For this reason a double pi low
pass filter is shown in the test circuit of Figure 3 and works well
for Channel 3 and 4 lab work. For a fully commercial
application, a vestigial sideband filter will be required. The
general form and approximate values are shown in Figure 19.
It must be exactly aligned to the particular channel.

Figure 3. AM Modulator Transfer Function

"5

.e--o::
"
I
as

"->
a:

Differen1iallnput, Vll-Vl (V)

Figure 4. AM Test Circuit
R2
470

L1
C2 56
Rl
470
6

7

8

10l!F
o--j

VCC
RL
75

11

Video
Input
22

t.Ok

12

13 5

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

9-52

I

RF

MC1374

;

Figure 6. 920 kHz Beat

Figure 5. The Operating Window

~

12~-='----r----r---'----r----r-~

~ 11
~ 10

;;:; 9.0
o..

!ll 8.0 "'V""CC:---;;3~$_-;2;;'ll""RLd---=IPs.-~---:::l..r977'&7'~
!:3 7.0 3
~

6.01-"::""..!:111'''''''''''''''::---l;;.o1'77''¥7o
!3 5.0
~ 4.0 F----::k.-?;~6<:h':~h':7¥.

~3.0~~~~w.~~~
~

<

ur

Q

E
....I

!:i

~ g:

-60

g

-70

+1

o~--~--~----~--~--~----~~

5.0

6.0

7.0

8.0

9.0

11

10

-80

12

Vcc. SUPPLY VOLTAGE (Vde)

'"
o 0.1

b

~

¥

C5.

1'77; b--..

-10

0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4

>- -30

~

fil
ff

25

~

50

5

'"

lL

Sl :c. -60

-80

100

o 0.1

w

53

~
-20

ff

-30

Q

~
~

o

:z

~

~~

~ 11; ~ V~ 'l; lj loY
'II Ij, Vi VI 1/
-40
(I; 'II I/~ V
-50
I~ I/; rP
-60
'/) /"
-70
5.0

6.0

7.0

-

VI ~ ~

0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4

Figure 10. 920 kHz Beat

8.0

-10

rz ~

EO'
:!:.

~

i=
:::J w
o.. Q
~ i=
'N~

:li1
TA= 25°C
le l= 61 125 ~HZ

9.0

10

Vcc. SUPPLY VOLTAGE M

~

~V

DIFFERENTIAL INPUT (VII - VI) (Vde)

o

~ -10

.........

a

~

-70

:c.

10

:z

I

b

;-.,........ r--....

"U"

+I
<>

75

Ir1'

I

I

-40

:li1 ~ -50

TA. AMBIENT TEMPERATURE (0C)

0

I

o.. :::>

Figure 9. RF Oscillator Frequency
versus Supply Voltage

f

I

'No..

~

o

-20

5 ~ -30

" '< f?.

-60

Iii'
w:!:.

I~

-50

I .1

InHial Video = 0.5 Vde
Chroma (3.58 MHz) = 150 mVp-p
Sound (4.5 Mhz) a) = 125 mVp-p
b) = 250 mVp-p
Gain Resislor RG = 1.0 kQ

-10
Q

l))..

-40

-70

~~z

I'e~

:;:
en
u
:z

~

Figure 8. 920 kHz Beat

o

"'< l'>..

Ii: -20

r-. cv:

lI/

DIFFERENTIAL INPUT (VII - VI) [Vde)

Ie 61.25
__
V C=12Vde

~~

I"'-.

a

Figure 7. RF Oscillator Frequency
versus Temperature
10

~

Q

o.. :::>
~
-40
'No..

:li1 ~ -50

S2.0e::
~ 1.0

o

InHial Video = 1.0 Vde
-10 f-Chroma (3.58 MHz) = 300 mVp-p
Sound (4.5 Mhz) a) = 250 mVp·p
-20 fb) = 500 mVp-p
Gain Resistor R = 1.0 kQ
w -30

Iii'

11

--

-20
-30

In~ial

-40

~ -50

~ ;g: -60

..........

+I

g

-70
-80

12

1.~

I I
Jideo 1= Vde l
Chroma (3.58 MHz) = 300 mVp-p
Sound (4.5 Mhz) A) = 250 mVp-p
b) = 500 mVp-p
Gain Resislor (Real = 2.2 kQ

o 0.2

....

-

L.""

~V

b

a

-"'t': ~ 'I'
v

0.4 0.6 0.8 1.0 1.2 1.4 1.5 1.6 1.8 2.0 2.2 2.4 2.8
DIFFERENTIAL INPUT (V11 - VI) [Vde)

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

9-53

MC1374

FM Section
The oscillator center is approximately the resonance of the
inductor L2 from Pin 2 to Pin 3 and the effective capacitance
C3 from Pin 3 to ground. For overall oscillator stability, it is best
to keep XL in the range of 300 Q to 1.0 kQ.
The modulator transfer characteristic at 4.5 MHz is shown
in Figure 15. Transfer curves at other frequencies have a very
similar shape, but differ in deviation per input volt, as shown in
Figures 13 and 17.
Most applications will not require DC connection to the
audio input, Pin 14. However, some improvements can be
achieved by the addition of biasing circuitry. The unaided
device will establish its own Pin 14 bias at 4 e, or about 3.0 V.
This bias is a little too high for optimum modulation linearity.
Figure 14 shows better than 2 to 1 improvement in distortion
between the unaided device and pulling Pin 14 down to 2.6 V
to 2.7 V. This can be accomplished by a simple divider, if the
supply voltage is relatively constant.
The impedance of the divider has a bearing on the
frequency versus temperature stability of the FM system. A
divider of 180 kQ and 30 kQ (for VCC = 12 V) will give good
temperature stabilization results. However, as Figure 18
shows, a divider is not a good method if the supply voltage
varies. The designer must make the decisions here, based on
considerations of economy, distortion and temperature
requirements and power supply capability. If the distortion
requirements are not stringent, then no bias components are
needed. If, in this case, the temperature compensation needs
to be improved in the high ambient area, the tuning capacitor
from Pin 3 to ground can be selected from N75 or N150
temperature compensation types.
Another reason for DC input to Pin 14 is the possibility of
automatic frequency control. Where high accuracy of intercarrier frequency is required, it may be desirable to feed back
the DC output of an AFC or phase detector for nominal carrier
frequency control. Only limited control range could be used
without adversely affecting the distortion performance, but
very little frequency compensation will be needed.
One added convenience in the FM section is the separate
Pin "oscillator B+" which permits disabling of the sound system
during alignment of the AM section. Usually it can be hard
wired to the VCC source without decoupling.
Standard practice in television is to provide pre-emphasis of
higher audio frequencies at the transmitter and a matching
de-emphasis in the TV receiver audio amplifier. The purpose
of this is to counteract the fact that less energy is usually
present in the higher frequencies, and also that fewer
modulation sidebands are within the deviation window. Both
factors degrade signal to noise ration. Pre-emphasis of 75 ~s
is standard practice. Forcases where it has not been provided,
a suitable pre-emphasis network is covered in Figure 20.
It would seem natural to take the FM system output from
Pin 2, the emitter follower output, but this output is high in
harmonic content. Taking the output from Pin 3 sacrifices
somewhat in source impedance but results in a clean output
fundamental, with all harmonics more than 40 dB down. This
choice removes the need for additional filtering components.
The source impedance of Pin 3 is approximately 2.0 kQ, and

the open circuit amplitude is about 900 mV pop for the test
circuit shown in Figure 11.
The application circuit of Figure 1 shows the recommended
approach to coupling the FM output from Pin 3 to the AM
modulator input, Pin 1. The input impedance at Pin 1 is very
high, so the intercarrier level is determined by the source
impedance of Pin 3 driving through C4 into the video bias
circuit impedance of R4 and R5, about 2.2 k. This provides an
intercarrier level of 500 mV pop, which is correct for the 1.0 V
peak video level chosen in this design. Resistor R6 and the
input capacitance of Pin 1 provide some decoupling of stray
pickup of RF oscillator or AM output which may be coupled to
the sound circuitry.

Figure 11. FM Test Circuit
C3 L2
10
(MHz) (pF) (jlH)
10.7

VCC

10

12

4.5

120

10

1.76

200

40
C14
O.OljlF

Interearrier
Sound Output
(Use FET Probe)

07

810-

06

910

05

100

--04

110

I
L2
10jlH

'1 [) 4

5 3

Ig~FI

He 2

~

'~b,

120

"ltr

R12 C6

13 0

Optional Bias R
(See Text)

~

Audio
13 Input
_ R

Figure 12. Modulator Sensitivity
2.0

b

1.8

I

:z

~ ~1.6

~ ~

1.4

!Z



@ 4.6

ff
a:
o

~
~

4.5

.,.

~

4.3

4.1

1.0

I

N'

Vee = 5.0 V, 9.0 V

:J:

~

~

1.1

z
w

=>

C

w

a:

~

~ 11.2
z
11.0

c=>
w 10.8
a:
a: 10.6

"-

0

~
G

10.4

0

10.0

en

1 9.8
9.6 0

,.

IJ
).

10.2

r\

.J.

[) ~
1.0

Pin14Vto2~6L

4.52

6.0

- r-- -. ---

./

4.50

~

~

~~

1==

I"'--

25
50
75
TA, AMBIENTTEMPERATURE (Oe)

12V
9.0 V Vee
5.0V

4.49
N'

4.48

~

4.47

:J:

~

z
w

4.46

cw

4.45

a:

"-

"
7.0

Pin 14102.6 V Source

--

4.44

4.43 L
6.0

100

Figure 18. FM System Frequency versus Vee
4.50

=>

2.0
3.0
4.0
5.0
De INPUT VOLTAGE, PIN 14 M

180 k}30 k Divider

Pin 14 Open
I

4.47 0

7.0

........

/'

./

4.51

4.48

TA=25°e
:;; 11.4
I--- (10.7 MHz)
05w

~

4.49

11.6

100

75

.I

I

"-

2.0
3.0
4.0
5.0
De INPUT VOLTAGE, PIN 14 M

-

..l~ ~

50
DEVIATION (kHz)

4.53

Figure 17. Modulator Transfer Function
N'

L

--r

4.54 t - Vee=12V

~ IV

o

i

25

4.55

Jee!12~

L..4 ~

$ 4.2

IL

Figure 16. FM System Frequency
versus Temperature

~r

4.4

/

o

Figure 15. Modulator Transfer Function

05- 4.8 I -

L

V
LO~timum Bias (2.6-2.7 V)

~ 2.0
Q

o

1.3

I-'

~
z 3.0 I - - - Self B:as (2.9-3.0 V)
o
I
./

"'--:: ~

~ 1.5

./

Vee=12V
TA=25°e
fc =4.5MHz

4.0 -

~,

o
~ 1.6

I

_

I
Vee=12V
-

4.42
4.0

~

-d-::::I--"
Pin 14 Open

/'

. / V"

L

"Pinl4 -180 k/ 30 k Divider

L
TA=25°e

5.0

6.0
7.0
8.0
9.0
10
Vee, SUPPLY VOLTAGE (Vdc)

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
9-55

V
,,/'

11

12

MC1374

Figure 19. A Channel 4 Vestigial Sideband Filter

VCC

Both transformer windings
4T#23AWG
close wound on 1/4" 10
on common axis, 3/8" spacing.

8.2pF

ij
24Q
3PF

33pF

2.~

~ -30
~ -40

ffi

~~07~h~

=

~. 33pF

i

=

=

-10

:z- -20

'"~

= 8T#23AWG

I
I

![

-50

~ -60

100Q

65
69
73
f, FREQUENCY (MHz)

close wound on 1/8" 10,
knife tuned to trap Ch. 3
61.25 MHz.

..J

Figure 20. Audio Pre-Emphasis Circuit
CD 25

21t RC

~

I=0

c.

z

C=0.001211F

CC=O.~
"Flaf'
Audio

0--=-1

r = 56kQ

20

Audio
Input

15
is
=0
C.

--

I=0

a

R
6.OkQ

w

5

5a:

-5

>

Inp~

w

5 :>Gnd

10

210
2100
21k
f, FREQUENCY (MHz)

21

Pre-emphasis = 7511s = rC = 21t (2;00 Hz)

Figure 21. Crystal Controlled RF Oscillator
for Channel 3,61.25 MHz
VCC
Rl

Cl
O.OOIJ

R2

470

470

Rb

MC1374

18

I

I
NOTE: See Application Note AN829 for further information.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
9-56

MOTOROLA

MC1377

SEMICONDUCTOR-----TECHNICAL DATA

COLOR TELEVISION
RGB to PALINTSC ENCODER

Color Television RGB to
PAL/NTSC Encoder
The MC1377 will generate a composite video from baseband red, blue, green
and sync inputs. On board features include: a color subcarrier oscillator; voltage
controlled 90° phase shifter; two double sideband suppressed carrier (DSBSC)
chroma modulators; and RGB input matrices with blanking level clamps. Such
features permit system design with few external components and accordingly,
system performance comparable to studio equipment with external components
common in receiver systems.

P SUFFIX
PLASTIC PACKAGE
CASE 738

DWSUFFIX
PLASTIC PACKAGE
CASE 751D
(SO·20L)

• Self-contained or Externally Driven Reference Oscillator
• Chroma Axes, Nominally 90° (±5°), are Optionally Trimable
• PAUNTSC Compatible
• Internal 8.2 V Regulator

ORDERING INFORMATION
Temperature
Range

Device
MC1377DW

Package
SO-20L

0° to +70°C

Plastic DIP

MCI377P

Figure 1. Simplified Block Diagram
VCC
0'14

'0

•

~-

Oscillator
Buffer

t_

~

Voltage
Controlled
90°

!

VB
0 16

1 i

... X+

PAL
Switch
0/180°

8.2V
Regulator

900~

I H/2

~-

2
NTSC/PAL
Select

PAl./NTSC
Control

I--

i
Gnd

i

Latching
Ramp
Generator

~

1

Burst
Pulse
Driver

I---<>

I

f

u 1
Trise

I

+
u 2
Composite
Sync Input

°l

t
1 R·Y

~

I B·Y

~-Y

t

t

t

I
u

I
u

u 5

R

G

B

B-Y
Clamp

I

11

R-Y
Clamp

I

12

Output Amp/
Clamp

I

9 Composite
Video Output
Video Clamp
7

H

H

I

,---- V - - - )

,
f

6
-Yout

Inputs

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
9-57

Chroma Out

-';} aChroma In

f

Color Difference and
Luminance Matrix

3

Amp

1

-AA
l
r

Dual
Comparator

t

t

---,

,.~~

u 8
-Yin

I

I

B-YClamp

R-YClamp

MC1377
MAXIMUM OPERATING CONDITIONS
Rating

Symbol

Value

Unit

VCC

15

Vdc

'c

Supply Voltage
Storage Temperature

Tstg

-65 to +150

Power Dissipation Package
Derate above 25'C

Po

1.25
10

W
mW/'C

Operating Temperature

TA

oto +70

'C

RECOMMENDED OPERATING CONDITIONS
Characteristics

Min

Typ

Max

Unit

Supply Voltage

10

12

14

Vdc

IB Current (Pin 16)

0

-

-10

rnA

1.7
-0.5
2.5

0
-

8.2
0.9
5.2

Vdc

Sync, Blanking Level (DC level between pulses, see Figure ge)
Sync -np Level (see Figure ge)
Sync Pulse Width (see Figure ge)
R, G, B Input (Amplitude)
R, G, B Peak Levels for DC Coupled Inputs, with Respect to Ground

!is

-

1.0

-

2.2

-

4.4

V(p_p)
V

Chrominance Bandwidth (Non-comb Filtered Applications), (6 dB)

0.5

1.5

2.0

MHz

Ext. Subscarrier Input (to Pin 17) if On-Chip Oscillator is not used.

0.5

0.7

1.0

V(p_p)

-

rnA

ELECTRICAL CHARACTERICISTICS (VCC = 12 Vdc, TA = 25'C, circuit of Figure 7, unless otherwise noted.)
Characteristics

Typ

SUPPLY CURRENT
Supply Current into VCC, No Load, on Pin 9.
Circuit Figure 7

VCC= 10V
VCC=11V
VCC=12V
VCC=13V
VCC= 14 V

14

ICC

20

-

33
34
35
36
37

40

-

VOLTAGE REGULATOR
VB Voltage (IB = -10 rnA, VCC = 12 V, Figure 7)
Load Regulation (0 < IB ,; 10 rnA, VCC = 12 V)
Line Regulation (lB = 0 rnA, 10 V < VCC < 14 V)

16

VB
Regload
Regline

7.7
-20

-

8.2
120
4.5

-

Vdc
mV
mVIV

Osc

-

Rosc

-

0.6

-

V(p_p)

-

kQ

-

Cosc

-

5.0
4.0
2.0

-

pF

19
19

0m
A0m
V19

-

±5
0.25
6.4

-

-

Deg
Deg/!iA
Vdc

10

Yin

-

4.0
0.7

-

Vdc
V(p_p)

Rin
Cin

-

10
2.0

-

kQ
pF

Vout

8.9

-

10
1.0

Rout

-

BWLuma

-

8.7
+30

OSCILLATOR AND MODULATION
Oscillator Amplitude with 3.58 MHzl4.43 MHz crystal

17

Subcarrier Input: Resistance at 3.58 MHz
4.43 MHz

17

Capacitance

-

Modulation Angle (R-Y) to (B-Y)
Angle Adjustment (R-Y)
DC Bias Voltage
CHROMINANCE AND LUMINANCE9
Chroma Input DC Level
Chroma Input Level for 100% Saturation
Chroma Input: Resistance
Capacitance
Chroma DC Output Level
Chroma Output Level at 100% Saturation

13

Chroma Output Resistance
Luminance Bandwidth (-3.0 dB), Less Delay Line

9

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

9-58

10.9

-

Vdc
V(p_p)

50

-

Q

8.0

-

MHz

MC1377
ELECTRICAL CHARACTERICISTICS (VCC = 12 Vdc, TA = 25'C, circuit of Figure 7, unless otherwise noted.)
Characteristics

typ

VIDEO INPUT
R, G, B Input DC Levels

3,4,5

RGB

R, G, B Input: Resistance
Capacitance

3.3

3.8

-

1.0

-

8.0

-

10
2.0

-

kQ
pF

10

-

kQ

0.6
1.4
1.7
0.6

-

V(p_p)

-

Rvideo

-

50

-

!l

Vlk

-

20

-

mV(p_p)

RRGB
CRGB

Sync Input Resistance (1.7 V < Input < 8.2)

Vdc

2.8

R, G, B Input for 100% Color Saturation

2

Sync

-

9

CVout

-

V(p_p)

17

COMPOSITE VIDEO OUTPUT

}{

Composite Output,
100% Saturation
(see Figure 8d)

Sync
Luminance
Chroma
Burst

Output Impedance (Note 1)
Subcarrier Leakage in Output (Note 2)

NOTES: 1. Output Impedance can be reduced to less than 10 Q by uSing a 150 Q output load from Pin 9 to ground. Power supply current will
increase to about 60 mAo
2. Subcarrier leakage can be reduced to less than 10 mV with optional circuitry, (see Figure 12).

PIN DESCRIPTIONS
Symbol

Pin Number'

Description

tr

1

External components at this pin set the rise time of the internal ramp function generator. See Figure 10.

Sync

2

Composite sync input. Presents 10 kQ resistance to input.

R

3

Red signal input. Presents 10 kQ impedance to input. 1.0 V (p_p) required for 100% saturation.

G

4

Green signal input. Presents 10 kQ impedance to input. 1.0 V(p_p) required for 100% saturation.
Blue signal Input. Presents 10 kQ impedance to input. 1.0 V (p-p) required for 100% saturation.

B

5

-Yout

6

Luma (-Y) output. Allows external setting of luma delay time.

Vclamp

7

Video Clamp pin. Typical connection is a 0.01 !iF capacitor to ground.

-Yin

8

Luma (-Y) input. Presents 10 kQ input impedance.

CVout

9

Composite Video output. 50 Q output impedance.

Chromaln

10

Chroma input. Presents 10 kQ input impedance.

B-Ycl arnp

11

B-Y clamp. Clamps B-Y during blanking with a 0.1 !iF capacitor to ground.
Also used with R-Y clamp to null residual color subcarrier in output.

R-Yclamp

12

R-Y clamp. Clamps R-Y during blanking with a 0.1 !iF capacitor to ground.
Also used with B-Y clamp to null residual color subcarrier in output.

ChromaOut

13

Chroma output. 50 Q output impedance.

VCC

14

Power supply pin for the IC. +12, ± 2.0 V, required at 35 mA (typical).

Gnd

15

Ground pin.

VB

16

+8.2 V reference from an internal regulator capable of delivering lamA to external circuitry.

OS Cin

17

Oscillator input. A transistor base presents 5 kQ to an external subcarrier input, or is available for
constructing a Colpitts oscillator. (See Figure 4)

OS Cout

18

Oscillator output. The emitter of the transistor, with base access at pin 17, is accessible for completing the
Colpitts oscillator. See Figure 4.

0m

19

Quad decoupler. With external circuitry, R-Y to B-Y relative angle errors can be corrected. Typically,
requires a 0.01 !iF capacitor to ground.

NTSC/PAL
Select

20

NTSC/PAL switch. When grounded the MC1377 is in the NTSC mode; if unconnected, in the PAL mode.

'Pin designations apply to both the DIP and the SOIC package.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

9-59

MC1377
FUNCTIONAL DESCRIPTION
Figure 2. Power Supply and VB

Power Supply and VB (8.2 V Regulator)
The MC1377 pin for power supply connection is Pin 14.
From the supply voltage applied to this pin, the IC biases
internal output stages and is used to power the 8.2 V internal
regulator (VB at Pin 1S) which biases the majority of internal
circuitry. The regulator will provide a nominal 8.2 V and is
capable of 10 mA before degradation of performance. An
equivalent circuit of the supply and regulator is shown in
Figure 2.
R, G, B Inputs
The RGB inputs are internally biased to 3.3 V and provide
10 kQ of input impedance. Figure 3 shows representative
input circuitry at Pins 3, 4, and 5.
The input coupling capacitors of 15 llF are used to prevent
tilt during the SO/SO Hz vertical period. However, if it is desired
to avoid the use of the capacitors, then inputs to Pins 3, 4, and
5 can be DC coupled provided that the signal levels are always
between 2.2 V and 4.4 V.
After input, the separate RGB information is introduced to
the matrix circuitry which outputs the R-Y, B-Y, and -Y signals.
The -Y information is routed out at Pin S to an external delay
line (typically 400 ns).

Figure 3. RGB Input Circuitry
R·Y

.y

B·Y

DSBSC Modulators and 3.58 MHz Oscillator

3

I

6

151!F
-Y

R
Figure 4. Chroma Section
_ Oscillator

Quad
Oecoup

________ ~1~7~--~~~~1~9

B·Y

R·Y

The R-Y and B-Y outputs (see (B-Y)/(R-Y) Axes versus I/O
Axes, Figure 22) from the matrix circuitry are amplitude
modulated onto the 3.58/4.43 MHz subcarrier. These signals
are added and color burst is included to produce composite
chroma available at Pin 13. These functions plus others,
depending on whether NTSC or PAL operation is chosen, are
performed in the chroma section. Figure 4 shows a block
diagram of the chroma section.
The MC1377 has two double balanced mixers and
regardless of which mode is chosen (NTSC or PAL), the
mixers always perform the same operation. The B-Y mixer
modulates the color subcarrier directly, the R-Y mixer receives
a 90° phase shifted color subcarrier before being modulated
by the R-Y baseband information. Additional operations are
then performed on these two signals to make them NTSC or
PAL compatible.
In the NTSC mode, the NTSC/PALcontrol circuitry allows an
inverted burst of 3.58 MHz to be added only to the B-Y signal.
A gating pulse or "burst flag" from the timing section permits
color burst to be added to the B-Y signal. This color burst is
180 0 from the B-Y signal and 90° away from the R-Y signal
(see Figure 22) and permits decoding of the color information.
These signals are then added and amplified before being
output, at Pin 13, to be bandpassed and then reintroduced to
the IC at Pin 10.
In the PAL mode, NTSC/PAL control circuitry allows an
inverted 4.43 MHz burst to be added to both R-Y and B-Y
equally to produce the characteristic PAL 225°/135 burst
phase. Also, the R-Y information is switched alternately from
180° to 0° of its original position and added to the B-Y
information to be amplified and output.

MOTOROLA LlNEARIiNTERFACE ICs DEVICE DATA

9-60

MC1377
Timing Circuitry

Figure 5. Timing Circuitry

The composite sync input at Pin 2 performs three important
functions: it provides the timing (but not the amplitude) for the
sync in the final output; it drives the black level clamps in the
modulators and output amplifier; and it triggers the ramp
generator at Pin 1, which produces burst envelope and PAL
switching. A representative block diagram of the timing
circuitry is shown in Figure 5.
In order to produce a color burst, a burst envelope must be
generated which "gates" a color subcarrier into the R-Yand
B-Y modulators. This is done with the ramp generator at
Pin 1.
The ramp generator at Pin 1 is an R-C type in which the pin
is held low until the arrival of the leading edge of sync. The
rising ramp function, with time constant R-C, passes through
two level sensors-the first one starts the gating pulse and the
second stops it (see Figure 10). Since the 'early' part of the
exponential is used, the timing provided is relatively accurate
from chip-to-chip and assembly-to-assembly. Fixed components are usually adequate. The ramp continues to rise for
more than half of the line interval, thereby inhibiting burst
generation on 'half interval' pulses on vertical front and back
porches. The ramp method will produce burst on the vertical
front and back 'porches' at full line intervals.
R-V, B-V Clamps and Output Clamp/Amplifier

H/2

PAll
NTSC

R

Figure 6. R-V, B-V and Output Amplifier Clamps
, Chroma
10

B-Y
11

O.~

R-Y

The sync Signal, shown in the block diagram of Figure 6,
drives the R-Y and B-Y clamps which clamp the R-Y and B-Y
signals to reference black during the blanking periods. The
output amplifierfclamp provides this same function plus
combines and amplifies the chroma and luma components for
composite video output.

12

O.~

t-_-p9--l~composite
7
Video

Sync

~__~~t---~~o.~

Application Circuit
Figure 7 illustrates the block diagram olthe MC1377 and the
external circuitry required for typical operation.
Figure 7. Block Diagram and Application Circuit

TOKO 166NNF
-10264AG

0.1

0.1
9

L~~L..J--f;-;:i~::-t
7 0.01
+-----'w.-.... VB
56k

• Refers to the choice NTSC/PAL
(3.58 MHzl4.43 MHz).

1.0k

Composite
Sync
Input

R, G, B Inputs

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

9-61

Composite
Video Output

MC1377
Figure 8.
17

""'"

18

-.
"'"

19

OSCOul

14

"'"

~

'"

2.0k

..."

"""

'""

~

oro

~~I
I

-tft-

,ro
'"

m

, F

...,....

~CF

~"
"
SpF

~
f<'"

®.,'"

P I
G~

~, m
-;J ,"...
J:::::=::::
17

"T8

S.lk

""

~o

RI6

~

'"

~7

PAlJNTSC

r

~7

20

,.

AF>

A"
",

'","

"

G.Ble

!.Ok

.-r!9 A23
~

".
~r

"'
r

,.'"

"~3r-= ,......
~ me; "'

RO •

~

'"

'.0

~r.

r

R25

R26

'"

~7

'"

A~

~7

~':~

,.

.~

An

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MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

9-62

MC1377
Internal Schematic

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MC1377
APPLICATION INFORMATION
Figure 9. Signal Voltages
(Circuit Values of Figure 7)
(a)

R, G, B Input Levels

4.4V
Umits
tor DC
Coupled
In puis

1oOV(p_p)

100%
Green
Input
(Pin 4)

2.2V
(b)

100%
Red
Input
(Pin 3)

1.0V(p_p)

(c)

100%
Blue
Input
(PinS)

1.0V(p_p)

The signal levels into Pins 3, 4, 5 should be 1.0 V(p_p) for fully
saturated, standard composite video output levels as shown
in Figure 9(d). The inputs require 1.0 V(p_p) since the internally
generated sync pulse and color burst are at fixed and
predetermined amplitudes.
Further, it is essential that the portion of each input which
occurs during the sync interval represent black for that input
since that level will be clamped to reference black in the color
modulators and output stage. This implies that a refinement,
such as a difference between black and blanking levels, must
be incorporated in the RGB input signals.
If Y, R-Y, B-Y and burst flag components are available and
the MC1377 is operating in NTSC, inputs may be as follows:
the Y component can be coupled through a 15 pF capacitor to
Pins 3,4 and 5 tied together; the (-[R-Y]) component can be
coupled to Pin 12 through a 0.1 /IF capacitor, and the (-[B- Y])
and burstflag components can be coupled to Pin 11 in a similar
manner.
Sync Input

(d)

5.0
Compos~e

4.0

Output
(Pin 9)

3.0
(e)

S.2Max
107 Min
0.9 Max

II

0 II
-0.5 Min LJ
(ij

Sync
Input
(Pin 2)

11LJ

10.5
Chroma
Output
(Pin 13)

10.0
9.5
(g)

4.35
Chroma
Input
(Pin 10)

4.0
3.65
(h)

5.2

Luminance
Oulput
(Pin 6)

4.3
(i)

M~

2.1

Luminance
Input
(PinS)

As shown in Figure 9(e), the sync input amplitude can be
varied over a wide latitude, but will require bias pull-up from
most sync sources. The important requirements are:
1) The voltage level between sync pulses must be between
1.7 V and 8.2 V, see Figure 9(e).
2)The voltage level for the sync tips must be between
+0.9 V and - 0.5 V, to prevent substrate leakage in the IC,
see Figure 9(e).
3)The width of the sync pulse should be no longer than
5.2 J.lS and no shorter than 2.5 Ils.
For PAL operation, correctly serrated vertical sync is
necessary to properly trigger the PAL divider. In NTSC mode,
simplified 'block' vertical sync can be used but the loss of
proper horizontal timing may cause 'top hook' or 'flag waving'
in some monitors. An interesting note is that composite video
can be used directly as a sync signal, provided that it meets the
sync input criteria.
Latching Ramp (Burst Flag) Generator
The recommended application is to connect a close
tolerance (5%) 0.001 IlF capacitor from Pin 1 to ground and a
resistor of 51 kQ or 56 kQ from Pin 1 to VB (Pin 16). This will
produce a burst pulse of 2.5 Ils to 3.5 Ils in duration, as shown
in Figure 10. As the ramp on Pin 1 rises toward the charging
voltage of 8.2 V, it passes first through a burst 'start threshold'
at 1.0 V, then a 'stop threshold' at 1.3 V, and finally a ramp reset
threshold at 5.0 V. If the resistor is reduced to 43 kQ, the ramp
will rise more quickly, producing a narrower and earlier burst
pulse (starting approx. 0.4 /lS after sync and about 0.6 /ls
wide). The burst will be wider and later if the resistor is raised
to 62 kQ, but more importantly, the 5.0 V reset point may not
be reached in one full line interval, resulting in loss of alternate
burst pulses.
As mentioned earlier, the ramp method does produce burst
at full line intervals on the 'vertical porches.' If this is not
desired, and the MC1377 is operating in the NTSC mode,
burst flag may be applied to Pin 1 provided that the tip of the

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

9-64

MC1377
pulse is between 1.0 Vdc and 1.3 Vdc. In PAL mode this
method is not suitable, since the ramp isn't available to drive
the PAL flip-flop. Another means of inhibiting the burst pulse is
to set Pin 1 either above 1.3 Vdc or below 1.0 Vdc for the
duration that burst is not desired.

Also, it is possible to do both; i.e., let the oscillator "free run"
on its own crystal and override with an external source. An
extra coupling capacitor of 50 pF from the external source to
Pin 17 was adequate with the experimentation attempted.

Color Reference Oscillator/Buffer

The oscillator drives the (B-Y) modulator and a voltage
controlled phase shifter which produces an oscillator phase of
90° ± 5° at the (R-Y) modulator. In most situations, the result
of an error of 5° is very subtle to all but the most expert eye.
However, if it is necessary to adjust the angle to better
accuracy, the circuit shown in Figure 11 can be used.
Pulling Pin 19 up will increase the (R-Y) to (B-Y) angle by
about 0.25°/flA. Pulling Pin 19 down reduces the angle by the
same sensitivity. The nominal Pin 19 voltage is about 6.3 V, so
even though it is unregulated, the 12 V supply is best for good
control. For effective adjustment, the simplest approach is to
apply RGB color bar inputs and use a vectorscope. A simple
bar generator giving R, G, and B outputs is shown in
Figure 26.

Voltage Controlled 90°

As stated earlier in the general description, there is an
on-board common collector Colpitts color reference oscillator
with the transistor base at Pin 17 and the emitter at Pin 18.
When used with a common low-cost tv crystal and capacitive
divider, about 0.6 V{p_p) will be developed at Pin 17. The
frequency adjustmenl can be done with a series 30 pF trimmer
capacitor over a total range of about 1.0 kHz. Oscillator
frequency should be adjusted for each unit, keeping in mind
that most monitors and receivers can pull-in 1200 Hz.
If an external color reference is to be used exclusively, it
must be continuous. The components on Pins 17 and 18 can
be removed, and the external source capacitively coupled into
Pin 17. The input at Pin 17 should be a sine wave with
amplitude between 0.5 V(p_p) and 1.0 V(p_p).

Figure 10. Ramp/Burst Gate Generator
5.0

a:<=

1.3

1.0

BUTst Start,

Ync: I
~
(Pin 21

L

: :

, ,
, ,

Time (J.ls)

5.58.5

Residual Feedthrough Components
As shown in Figure 9(d), the composite output at Pin 9
for fully saturated color bars is about 2.6 V (p_p), output with full
chroma on the largest bars (cyan and red) being 1.7 V{p_p).
The typical device, due to imperfections in gain, matnxing,
and modulator balance, will exhibit about 20 mV(p'_p) residual
color subcarrier in both white and black. Both residuals can be
reduced to less than 10 mV (p-p) for the more exacting
applications.
The subcarrier feedthrough in black is due primarily to
imbalance in the modulators and can be nulled by sinking or
sourcing small currents into clamp Pins 11 and 12 as shown
in Figure 12. The nominal voltage on these pins is about
4.0 Vdc, so the 8.2 V regulator is capable of supplying a pull
up source. Pulling Pin 11 down is in the 0° direction, pulling it
up is towards 180°. Pulling Pin 12 down is in the 90° direction,
pulling it up is towards 270°. Any direction of correction may
be required from part to part.
White carrier imbalance at the output can only be corrected
by juggling the relative levels of R, G, and B inputs for perfect

50

balance. Standard devices are tested to be within 5% of
balance at full saturation. Black balance should be adjusted
first, because it affects all levels of gray scale equally. There
is also usually some residual baseband video at the chroma
output (Pin 13), which is most easily observed by disabling the
color oscillator. Typical devices show 0.4 V{p_p) of residual
luminance for saturated color bar inputs. ThiS is not a major
problem since Pin 13 is always coupled to Pin 10 through a
bandpass or a high pass filter, but it serves as a warning to pay
proper attention to the coupling network.
Figure 11. Adjusting Modulator Angle
+12Vdc
19

220k

p-----~--~v'v-~~

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
9-65

63.5

10k

MC1377
Figure 12. Nulling Residual Color in Black
VB
470k

12

11

10k

~

then a monitor or receiver with frequency response shown in
Figure 14(b), which is fairly typical of non-comb filtered
monitors and receivers, will detect an incorrect luma sideband
at X' .This will result in cross-talk in the form of chroma
information in the luma channel. To avoid this situation, a
simpler bandpass circuit as shown in Figure 15(a), can be
used.

-=

10k

Figure 14. MC1377 Output with
Low Resolution RGB Inputs

470k

VB

X X

Figure 13. Delay of Chroma Information

I

X

(!)

Lum~

II

X

"1---,,
'n;
1.0

2.0

3.0 3.584.0

5.0

(a) Encoder Output with Low Resolution Inputs
and No Bandpass Transformer

I

~

The Chroma Coupling Circuits

With the exception of S-VHS equipped monitors and
receivers, it is generally true that most monitors and receivers
have color IF 6.0 dB bandwidths limited to approximately
±a.5 MHz. It is therefore recommended that the encoder
circuit should also limit the chroma bandwidth to approximately ±0.5 MHz through insertion of a bandpass circuit between
Pin 13 and Pin 10. However, if S-VHS operation is desired, a
coupling circuit which outputs the composite chroma directly
for connection to a S-VHS terminal is given in the S-VHS
application (see Figure 19).
For proper color level in the video output, a ±0.5 MHz
bandwidth and a midband insertion loss of 3.0 dB is desired.
The bandpass circuit shown in Figure 7, using the TaKa fixed
tuned transformer, couples Pin 10 to Pin 13 and gives this
result. However, this circuit introduces about 350 ns of delay
to the chroma information (see Figure 13). This must be
accounted for in the luminance path.
A 350 ns delay results in a visible displacement of the color
and black and white information on the final display. The
solution is to place a delay line in the luminance path from Pins
6 to 8, to realign the two components. A normal tv receiver
delay line can be used. These delay lines are usually of 1.0 kQ
to 1.5 kf.! characteristic impedance, and the resistors at Pins
6 and 8 should be selected accordingly. A very compact,
lumped constant delay line is available from TDK (see Figure
25 for specifications). Some types of delay lines have very low
impedances (approx. 100 Q) and should not be used, due to
drive and power dissipation requirements.
In the event of very low resolution RGB, the transformer and
the delay line may be omitted from the circuit. Very low
resolution for the MC 1377 can be considered RGB information
of less than 1.5 MHz. However, in this situation, a bandwidth
reduction scheme is still recommended due to the response
of most receivers.
Figure 14(a) shows the output of the MC1377 with low
resolution RGB inputs. If no bandwidth reduction is employed

1.0

2.0

3.0 3.58 4.0

5.0

(b) Standard Receiver Response

A final option is shown in Figure 15(b). This circuit provides
very little bandwidth reduction, but enough to remove the
chroma to luma feedthrough, and essentially no delay. There
is, however, about a 9 dB insertion loss from this network.
It will be left to the designer to decide which, if any,
compromises are acceptable. Color bars viewed on a good
monitor can be used to judge acceptability of step luminance!
chrominance alignment and step edge transients, but signals
containing the finest detail to be encountered in the system
must also be examined before settling on a compromise.
The Output Stage
The output amplifier normally produces about 2.0 V(p_p) and
is intended to be loaded with 150 Qas shown in Figure 16. This
provides about 1.0 V (p_p) into 75 Q, an industry standard level
(RS-343). In some cases, the input to the monitor may be
through a large coupling capacitor. If so, it is necessary to
connect a 150 Q resistor from Pin 9 to ground to provide a low
impedance path to discharge the capacitor. The nominal
average voltage at Pin 9 is over 4.0 V. The 150 Q DC load
causes the current supply to rise another 30 mA (to approximately 60 mA total into Pin 14). Under this (normal) condition
the total device dissipation is about 600 mW. The calculated
worst case die temperature rise is 60°C, but the typical device
in a test socket is only slightly warm to the touch at room
temperature. The solid copper 20-pin lead frame in a printed
circuit board will be even more effectively cooled.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
9-66

MC1377
regulator is convenient for a tracking DC reference for DC
coupling the outputto an RF modulator. Typical turn-on drift for
the regulator is approximately -30 mV over 1 to 2 minutes in
otherwise stable ambient conditions.

Figure 15. Optional Chroma Coupling Circuits
0.001

1.0k

0.001

~~--~~--~--~~~

13

10
39pF

Figure 16. Output Termination

a) Insertion Loss: 3.0 dB
Bandwidth: ± 1.0 MHz
Delay: ~ 100 ns
~F
1~
~m
~r---~~--~--~--~~

13

10

27pF

4.7k
b) Insertion Loss: 9.0 dB
Bandwidth: ± 2.0 MHz
Delay: 0

SUMMARY

Power Supplies
The MCI377 is designed to operate from an unregulated
10 v to 14 V DC power supply. Device current into Pin 14 with
open output is typically 35 mAo To provide a stable reference
for the ramp generator and the video output, a high quality
8.2 V regulator can supply up to lamA for external uses, with
an effective source impedance of less than 1.0 Q. This

The preceding information was intended to detail the
application and basis of circuit choices for the MCI377. A
complete MCI377 application with the MC1374 VHF modulator is illustrated in Figure 17. The internal schematic diagram
of the MCI377 is provided in Figure 8. If further assistance is
needed, contact Motorola Linear Applications Engineering.

Figure 17. Application with VHF Modulator
470
47k

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11 12 19 15

0.1

.01

1.2k

®

+-+---f14

Video
Oul

7

,

10

JLO
Audio
In

.01

+12Vdc

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

9-67

0.33~H

r

~F
Oul
122

MC1377
APPLICATIONS INFORMATION
S-VHS
In full RGB systems (Figure 18), three information channels
are provided from the signal source to the display to permit
unimpaired image resolution. The detail reproduction of the
system is limited only by the signal bandwidth and the capability of the color display device. Also, higher than normal sweep
rates may be employed to add more lines within a vertical
period and three separate projection picture tubes can be
used to eliminate the 'shadow mask' limitations of a conventional color CRT.
Figure 21 shows the 'baseband' components of a studio
NTSC signal. As in the previous example, energy is concentrated at multiples of the horizontal sweep frequency. The
system is further refined by precisely locating the color
subcarrier midway between luminance spectral components.
This places all color spectra between luminance spectra and
can be accomplished in the MC1377 only if 'full interlaced'

external color reference and sync are applied. The individual
components of luminance and color can then be separated by
the use of a comb filter in the monitor or receiver. This
technique has not been widely used in consumer products,
due to cost, but it is rapidly becoming less expensive and more
common. Another technique which is gaining popularity is
S-VHS (Super VHS).
In S-VHS, the chroma and luma information are contained
on separate channels. This allows the bandwidth of both the
chroma and luma channels to be as wide as the monitors
ability to reproduce the extra high frequency information. An
output coupling circuit for the composite chroma using the
TOKO transformer is shown in Figure 19. It is composed of the
bandpass transformer and an output buffer and has the
frequency performance shown in Figure 20. The composite
output (Pin 9) then produces the luma information as well as
composite sync and blanking.

Figure 18. Spectra of a Full RGB System

Figure 20. Frequency Response of
Chroma Coupling Circuit

Red

G,~ ~l IlIlI lInt'"

I

~

I

..,

~1I1I""1111111
1.0

J.

L

I

4-8

t, FREQUENCY (MHz)

Figure 19. S-VHS Output Buffer
+12Vdc

100/62pF*

':,~If*--+-_~---'-~----l

Composite
Chroma

t, MHz
2.7

Out

O.IJlF

·Refers to different component values used for NTSC/PAL (3.58 MHzl4.43 MHz).
"Toko 166NNF-I 026AG

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

9-68

3.66

4.5

MC1377
I/O System versus (R-Y)/(8-Y) System
The NTSC standard calls for unequal bandwidths for I and
Q (Figure 21). The MC1377 has no means of processing the
unequal bandwidths because the I and Q axes are not used

(Figure 22) and because the outputs of the (R-Y) and the (B-Y)
modulators are added before being output at Pin 13. Therefore, any bandwidth reduction intended for the chroma
information must be performed on the composite chroma
information. This is generally not a problem, however, since
most monitors compromise the standard quite a bit.

Figure 23 shows the typical response of most monitors and
receivers. This figure shows that some crosstalk between
luma and chroma information is always present. The acceptability of the situation is enhanced by the limited ability of the
CRT to display information above 2.5 MHz. If the signal from
the MC1377 is to be used primarily to drive conventional
non-comb filtered monitors or receivers, it would be best to
reduce the bandwidth at the MC1377 to that of Figure 23 to
lessen crosstalk.

Figure 22. Color Vector Relationship
(Showing Standard Colors)

Figure 21. NTSC Standard Spectral Content

Purgle
(61 )

Q (33')

Yellow
(168')

/'

y

1.0

2.0

3.0

/'/'

/'

/'

/'

""
(B·Y) 0°

4.0
Blue
(348°)

f, FREQUENCY (MHz)

Green
(241°)

Figure 23. Frequency Response of
Typical MonitorlTV
Chroma
Channel
Gain t-------..."
Luminance
Channel

1.0

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

9-69

Cyan
(284°)

MC1377
Figure 24. A Prototype Chroma Bandpass Transformer
Toko Sample Number 166NNF-10264AG

-.-

7±0.2mm

£
(Drawing Provided By:
Toko America, Skokie, IL)

Connection Diagram
Bottom View

Unloaded Q (Pins 1-3): 15@2.5MHz
Inductance: 30 ~H ± 10% @ 2.5 MHz
Turns: 60 (each winding)
Wire: #38 AWG (0.1 m/m)

Figure 25. A Prototype Delay Line
TDK Sample Number DL122301D-1533

I

1.26M~

I

H

·Markin

0.35M~

9.0

0.93 M~
23.5

[•

!
0.026 ± 0.002
0.65 ± 0.33

0.2 ± 0.04
5.0± 1.0

0.788±0.08
20.0±2.0

0.8 Radius M~
2.0

Item
'Marking: Part Number, Manufacturer's Identification,
Date Code and Lead Number.
Skokie, IL (TDK Corporation of America)

TIme Delay

Specifications
400 nsf 10%

Impedance

1200 Q ± 10%

Resistance

Less Than 15 Q

Transient Response with 20 ns
Rise TIme Input Pulse

Overshoot: 10% Max

Attenuation

3 dB Max at 6.0 MHz

Pres hoot: 10% Max
Rise Time: 120 ns Max

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

9-70

MC1377
Figure 26. RGB Pulse Generator

-,Llr

4.7~F

BNC

Q

10k

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Composite
Blanking

2.2k

10k
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MC74LSl12A

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Output

470

r~

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RGB Pulse Generator Timing Diagram for NTSC

LJ

~1~~---------------------64~5

Composite
Blanking
Input

154 kHz
Clock
Black
Blue
Output

Red
Output

-------'

Green
Output

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
9-71

~

0.1

0.1

470

. ~:~ ~
rf-

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2N4401

Green
Output

MC1377
Figure 27. Printed Circuit Boards for the MC1377

o
RF

ou'

(COMPONENT SIZE)

(CIRCUIT SIDE)

Figure 28. Color TV Encoder -

Modulator
470

47k
470
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20

18

16

8.2Vdc

75

O.33~H

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+

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120

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t

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mica

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11

5.1k

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14
13
1.2k
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11 12 19 15
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13

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400n5
1.21<

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®

Video
Out

Audio
In

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Vee
(,12V)

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

9-72

0.001

E--o

54k

R--i ,

0.33~H

RF
Out

MOTOROLA

MC1378

SEMICONDUCTOR-----TECHNICAL DATA

COLOR TELEVISION
COMPOSITE VIDEO OVERLAY
SYNCHRONIZER

Advance Information

Color Television Composite Video
Overlay Synchronizer
The MC1378 is a bipolar composite video overlay encoder and microcomputer
synchronizer. The MC1378 contains the complete encoder function of
the MC1377, i.e. quadrature color modulators, RGB matrix, and blanking
level clamps, plus a complete complement of synchronizers to lock a
microcomputer-based video source to any remote video source. The NC1378 is
especially tailored to work with the Motorola RMS (Raster Memory System), but
it can be applied to other controllable video sources. It can be used as a local
system timing and encoding source, but it is most valuable when used to lock the
microcomputer source to a remotely originated video signal.
• Contains All Needed Reference Oscillators
• Can Be Operated in PAL or NTSC Mode, 625 or 525 Line

PSUFFIX
PLASTIC PACKAGE

C~E;'

FN SUFFIX
PLASTIC PACKAGE
CASE 777
(PLCC-44)

• Wideband, Full-Fidelity Color Encoding
o Local or Remote Modes of Operation

•

PIN CONNECTIONS

• Minimal External Components
Local/Rem.

• Designed to Operate from 5.0 V supply

H. PLLFiHer

• Will Work with Non-standard Video

H.VCO{

Clock PLL FiHer

5(5)

ClockVCC

6 (7)

Clock Output

Ground

7 (8)

Clock Ground

3.58/4.43 In

8(9)
9 (10)

}CIOCkVCO

10(11)

Killer FiHer

11 (12)

Quad. Loop FiHer

R·YClamp

12 (13)

PAL Indent Cap

H Sync

B·YClamp

13(14)

VCC

R Input

14(15)

Compo Vid. Out

Glnput

15 (16)

Ground
Overlay Enable

14-

Vert/Comp Sync
Red

Remote
Video

MC1378

Green
Composite

r--- Overplayed

Blue

Video

Video Enable
Local/Remote

i

V. Out/Sync In

4(4)

36MHz Master Clock

3.58/4.43MHz

525/60
625/50

3(3)

Burst Gate Out

chromavco{

RMS

Compo Sync Out

PALJNTSC Mode

Chroma PLL Filter

Figure 1. Block Diagram Typical Application

H. Sync In
2 (2)

B Input

16 (18)

-Y Output

17(19)

Rem. Vid.ln

Chroma Out

18 (20)

ACCFiHer

Loc. Vid. Clamp

19 (21)

-Y Input

Chroma In

20 (22)

Rem. Vid. Clamp

• ( ) PLCC Pin Assignments

ORDERING INFORMATION

i

Device

PALJ
NTSC

MC1378P
MC1378FN

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
9-73

Temperature
Range
0° to +70°C

Package
Plastic DIP
PLCC·44

MC1378
MAXIMUM RATINGS
Rating

Symbol

Value

Unit

VCC

6.0

Vdc

TA

o to +70

°C

Storage Temperature

Tstg

-65 to +150

°C

Junction Temperature

TJ(max)

150

°C

PD

1.25
10

W
mW/"C

Pin No.

Value

Unit

28,36

5.4 ± 0.25

Vdc

14,15,16

1.0

Vp-p

Color Oscillator Input Level

8

0.5

Vp-p

Video Input, Positive

24

1.0

Vp-p

Supply Voltage
Operating Temperature

Power Dissipation, Package
Derate above 25°C

RECOMMENDED OPERATING CONDITIONS
Condition
Supply Voltage
RGB Input for 100% Saturation

ELECTRICAL CHARACTERISTICS (VCC = 5.0 V, TA = 25°C, circuit of Figure 4 or 5)
Pin No.

Min

Typ

28,36

-

100

-

Video Output, Open Circuit, Positive

27

-

2.0

9.4

Vp-p

Modulation Angle (R - Y) to (B - Y)

-

87

90

93

Degrees

-

kU

-

Vp-p

-

Vp-p

Characteristics
Supply Current

RGB Input Impedance
Local/Remote Switch (TIL)

High
Low

Horizontal Sync Input, Negative Going

(TIL)

14,15,16

-

10

1

-

Remote
Local

40

-

4.3

38

-

4.3

(TIL)

39
5

-

4.3

(TIL)

Vertical Sync Output, Negative Going,
Remote Mode

(TIL)

Composite Sync Output, Negative Going
Burst Gate Output, Positive Going

Description of Operation -

PD1 -

PD2 PD3 PD4 PD5 -

locks the internally counted-down 4 MHz horizontal VCO
to the incoming horiiontal sync. It is fast acting, to follow
VCR source fluctuations.
locks the 36 MHz clock VCO, which is divided down by
the RMS, to the divided down horizontal VCO.
is a gated phase detector which locks the 14 MHz crystal
oscillator, divided by 4, to the incoming color burst.
controls an internal phase shifter to assure that the
outgoing color burst is the same phase as incoming burst
atPD3.
not used in REMOTE MODE

Vertical lock is obtained by continuously resetting the sync
generator in the RMS with separated vertical sync from the
MC1378, Pin 38. This signal is TIL level vertical block sync,
negative going. The horizontal sync from the RMS to Pin 40 is
also TTL level with sync negative going. The local/remote switch,
Pin 1, is in local mode when grounded, remote mode when taken
to 5.0 V. The overlay control, Pin 25, has an analog characteristic,
centered about 1.0 V, which allows fading from local to remote.

Unit
mAdc

-

Vp-p

Vp-p

Refer to Figures 3, 4
Local Mode

Remote Mode
The incoming remote video signal (Pin 24) supplies all
synchronizing information. A discussion of the function of the
phase detectors helps to clarify the lockup method:

4.3

Max

The MC1378 and RMS combine to provide a fully synchronized
standard signal source. In this case, composite sync must be
supplied by the RMS or other time base system. In the MC1378
the phase detectors operate as follows:
PD1 - locks the internally counted-down 4 MHz horizontal VCO
to a Horizontal Sync signal (at Pin 40) from the RMS
(counted down from 36 MHz)
PD2 - not used in LOCAL MODE.
PD3 - not used in LOCAL MODE.
PD4 - active, but providing an arbitrary phase shift setting
between the color oscillator and the output burst phase.
PD5 - locks the 36 MHz clock VCO (which is divided down by
the RMS) to the 14 MHz (crystal) color oscillator. The
14 MHz is, therefore, the system standard in LOCAL MODE,
and is not DC controlled.
COMPOSITE VIDEO GENERATION
The color encoding at the RGB signals is done exactly as in
the MC1377. Composite chroma is looped out at Pins 18 and 20
to allow the designer to choose band shaping. Luminance is
similarly brought out (Pins 17 and 22) to permit installation of
the appropriate delay.
Composite sync output, Pin 39, and burst gate output, Pin 5,
are provided for convenience only.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

9-74

Figure 2. MC13781nlernai Block Diagram
Clock

"1 i

Burst Gate Out

Clock

-----------------------~~,I

1=

Vcc

36-

CIockD
Gnd

35.8/

~

5

.,

34

~.--5~

'"

"""J

I

4MH1

35.5

L-__v_VU~-1-----.4r-----~v~~~

MHz

s:::

~

I

~

:II

*

0
r

»
r

Z

m

s::

»

o

~

Z
(0

~

(J1

~I

...&.

W

PAll

~

NTSC

~
(")

m

0
(J)

0

m

<
0

m
0

~

»

~GB

0---1
~~
l~~0---1
15

16

Luma

Matrix

I

Vert. Out

R- Y

I
I
I
I
I
I

L-----..1!t
-Y
Out

~l

I I

I

II------~i-J
V~eoln
dl

--22
-Y
In

SyncSep

I Comp. Sync In
I
I
I
I
I
I

0ve!Iay
Enable

Remote

Video
Out

=

VCC

MC1378
Figure 3. Remote Mode
Overlay Enable

Remote
Video
In

+ 5 Video
Vee Out

Master Clock 35.8/35.5MHz

1-

33

32

31

30

25

24

TDK

RMS

SDL·4301

orolher
Local
Video
Source

Figure 4. Local Mode
Overlay Enable

+5 Video
Vee Out

Master Clock 35.8/35.5MHz

470k

75
0.1

34

33

32

31

30

29

28

27

26

25

24

TDK
SD~4301

~
+8

RMS

or other
Local
Video
Source

MOTOROLA LINEAR/INTERFACE DEVICES

9-76

MC1388

MOTOROLA

SEMICONDUCTOR-----TECHNICAL DATA

Advance Information

WAVEFORM GENERATOR
Ie FOR MONITOR
APPLICATIONS

Geometry Correction Waveform
Generator
The MC1388 is a bipolar integrated circuit designed to be used with the control
circuitry for geometry correction in monitors and HDTV receivers. The function of the
integrated circuit is to generate the required voltage waveforms that will be applied
to the control circuitry. The control circuitry will apply them in the proper amplitude and
combination for use in modulating the horizontal and vertical scan currents.

Features:
• Multistandard Operation Capable (10 kHz ~ tH ~ 63 kHz)(45 ~ tv ~ 120 Hz)
• Constant Amplitude Outputs, Independent of Frequency
• Complementary Output Waveforms (Horizontal Parabola, Horizontal Cubic,
Vertical Ramp, Vertical Parabola and Sine Functions)
• Three Input Multiplier
• Minimum of External Components Necessary

PSUFFIX
PLASTIC PACKAGE
CASE 711

• Standard Supplies (±5 Vdc)

PIN CONNECTIONS

Functions (Ten Waveforms):

(Top View)

• Horizontal Ramp and Vertical Ramp
• Horizontal Parabola and Vertical Parabola
• Horizontal Cube and Cube with Accessible Inputs (H'in, V'in)
•
•
•
•

±
±
±
±

Sine
Sine
Sine
Sine

H
2H
V
2V

SIMPLIFIED BLOCK DIAGRAM

H'V'

out

+V2

SineH
Drive

Sine V
Drive

Sine2H
Drive

Sine2V
Drive

_v2
tV Ramp
-V Ramp
+SineV
-Sine V
tSine2V

+ Sine2V

-Sine2V

+SineH
HYout

-SineH

+Sine2H
-Sina2H

+H Ramp

+H2
_H2
+H3

ORDERING INFORMATION

_H3

Device
MC1388P

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
9-77

Temperature
Range

Package
Plastic DIP

MC1388
Figure 1. Test Circuit of the MC1388
VCC

Blanking
Reference
Insertion

Vertical
Oscillator

H' V' Amplitude
Drive**

H' V' Clamp O.002211F
L-~~~--122
V'in
V'in Drive**
'-----------\21

HI'

Polystyrene
The three input multiplier was tested by applying a DC voltage to two of the inputs while applying a 1.25 Vp-p ramp input to the third.
The inputs applied to the Sine Drive Inputs is a voltage ramped from -850 mV to +850 mV in 10 mV steps.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

9-78

MC1388
MAXIMUM OPERATING CONDITIONS
Rating
Power Supply Voltage
Input Voltage
Maximum
Minimum

Symbol

Value

Unit

Vee
VEE

+6.0
-6.0

Vdc
Vdc

Vin. Hin. H'in.

V'in,H'V'
Amplitude

Vee +0.5
VEE-O·5

Storage Temperature

Tstg

-65 to +150

°e

Junction Temperature

TJ

+150

°e

RECOMMENDED OPERATING CONDITIONS
Pins(s)

Characteristics

Symbol

Value

Unit

+4.5 to +5.5
-5.5to-4.5

Vdc

Power Supply Voltage

1
40

Vee
VEE

Horizontal Sync Frequency (see Figure 8)
Maximum
Minimum
Pulse Width: Maximum
Minimum
Pulse Amplitude: Maximum Voltage (Tip)
Minimum Voltage (Baseline)
Minimum Threshold: Tip
Baseline

2

Hin

Vertical Sync Frequency (see Figure 8)
Maximum
Minimum
Pulse Width: Maximum
Minimum
Pulse Amplitude: Maximum Voltage (Tip)
Minimum Voltage (Baseline)
Minimum Threshold: Tip
Baseline

39

Sine H Drive
Sine 2H Drive
Sine V Drive
Sine 2V Drive

11
14
30
27

Sine H Drive
Sine 2H Drive
Sine V Drive
Sine 2V Drive

-0.85 to +0.85

Vdc

H'in
V'in
H'in V'in Amplitude

20
21
24

H'in
V'in
H'in V'in
Amplitude

-1.25 to +1.25

Vdc

6.7.8.12.
13.15.16
17.18.23.
25.26.28
29.33.34
35.36

IL

5.0

mA

TA

oto +70

°e

kHz
63
10
<1 .0/(2,OfH)
2.0
Vee
VEE +0.5
Vect2.0 +0.2
Vect2.0 +0.2

Ambient Temperature

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

9-79

Vdc

Hz

Vin
120
45
<1.0/(2,OfV)
2.0
Vce
VEE +0.5
Vee/2.O +0.2
Vect2.0 +0.2

Peak Load eurrent

I1s

115
Vdc

MC1388
ELECTRICAL CHARACTERISTICS (VCC = +5.0 V, VEE = -5.0 V, RL = 2.5!2~

-

VEE
21

V'in

(See Pin 20)

V' Input. Dynamic input impedance in excess of
1.0 MQ. Valid input voltage range is between VEE
and VCC.

22

H'V'
Clamp

(See Pin 9)

H'in, V'in and H' V' Amplitude Product Clamping pin.
An external capacitor works to cancel DC offset.
Typically coupled to ground with a 0.047 IlF capacitor.

23

H'V' out

(See Pin 6)

H' V' Output Pin. The product of H'in, V'in, H' V' amplitude must be less than 1.9 Vp-p.

24

H'V'
Amplitude

(See Pin 20)

H' V' Amplitude. Dynamic input impedance in excess of
1.0 MQ. Valid input voltage range is between VEE
andVcc·

25

+Sine 2V

(See Pin 6)

+Sine 2V output. The sine wave output developed from
the input at Pin 27.

26

-Sine 2V

27

Sine 2V
Drive

(See Pin 11)

Sine 2V Drive. A ramp waveform input here will produce
a sine wave output (at Pins 25 and 26) with frequency
varying with input ramp amplitude, and phase varying
with ramp DC offset. Input impedance is nominally
greater than 1.0 MQ.

28

+Sine V

(See Pin 6)

+Sine V output. The sine wave output developed from
the input at Pin 30.

29

-Sine V

30

Sine V
Drive

-Sine 2V output. A 1800 phase shifted version of
+Sine 2V.

-Sine V output. A 1800 phase shifted version of
+Sine V.
(See Pin 11)

Sine V Drive. A ramp waveform input here will produce a
sine wave output (at Pins 28 and 29) with frequency
varying with input ramp amplitude, and phase varying
with ramp DC offset. Input impedance is nominally
greater than 1.0 MQ.

MOTOROLA LlNEARIINTERFACE ICs DEVICE DATA

9-83

MC1388
PIN DESCRIPTIONS
Internal Equivalent
Circuit

Pin

Symbol

31

Gnd

32

V2clamp

(See Pin 9)

Vertical Parabola Clamp pin. An extemal capacHor
works to cancel DC offset. Typically coupled to ground
with a 0.047 IlF capacitor.

33

+V2

(See Pin 6)

Vertical Parabola.

34

-V2

35

+V

Vertical Ramp.

36

-V

Complement Vertical Ramp.

37

IVset

Description
Ground conneclion.

Complement Vertical Parabola.

Vertical Charge Current Set. An internally regulated 1.25
Vdc, and the external resistance (RVsetl at this pin determines the charging current for the capacitor, CV, connected to Pin 38.

Vee

~~
-Y

37

VEE

':'

38

+
~ 1.25V

101lA~

RVset

Iv

Vertical Ramp Generator Capacitor (CV). The charge
and discharge rate of the capacitor at this pin determines
the vertical ramp rate.

Vee
20k

J

20k

evt}}-=
GJ
aOOIlA $

j151lA

VEE
39

Vin

Positive Vertical Flyback input pin. Presents 10 k.Q to
input waveform. (See Figure 3). Threshold is at VCC/2.

Vee
25k
20k
39

20k

lOki
':'

':'

VEE
40

Negative Supply pin. Requires 43 mA at -5.5 < Vdc
<-4.5.

VEE

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
9-84

MC1388
FUNCTIONAL DESCRIPTION
Introduction
The MC1388 is a multi-frequency capable integrated
circuit used for geometry correction in monitors and HDTV
receivers. With a few inputs the MC1388 will provide ten
functions, eight with complements, as output waveforms.
These waveforms can then be used by the control circuitry
in any combination to modulate the horizontal and vertical
deflection currents for geometry correction.
The MC1388 accomplishes multi-frequency operation by
allowing external components to determine the nominal
frequency of operation. This is done by choosing
resistor-capacitor pairs for the desired horizontal and vertical
oscillator frequencies. The horizontal and vertical sync
inputs then provide the timing reference to which the output
waveforms of the MC1388 adhere.
Horizontal Timing
To ensure proper horizontal timing, the MC1388 uses a
phase-locked-loop to provide a reliable time base. The loop
is externally accessible at the current controlled oscillator
(ICO), Pins 3, 4, and at the output of the phase detector,
Pin 5. Figure 2 shows relevant internal circuitry and pin
connections. This allows the system designer to tailor the
timing and performance of the MC1388.
The ICO is an RC type in which the horizontal frequency
is determined by the charge and discharge rate of the
capacitor at Pin 3. During charging, the voltage on the
capacitor (CH) is increased until it reaches an internally
determined trip level. At this trip level the direction of the
current at Pin 3 is reversed and the discharge process
begins. During discharge, circuitry diverts the current
available at Pin 3 internally and the capacitor discharges
quickly to the bottom trip level where control circuitry switches
the direction of Pin 3 current and the cycle begins again.

The charging current at Pin 3 is determined by the
current out of Pin 4, which is mirrored at Pin 3. The
current out of Pin 4 is set by a nominal 1.25 V stable
reference and the external resistance at this node (RHset).
This also provides a means of modulating the charging
current at Pin 3 by injecting the error current from the
phase detector (Pin 5).
At Pin 5(HpLLl are the filter components of the horizontal
phase-locked-loop. These components were chosen to
ensure fast tracking over the possible horizontal operating
frequencies and a capture range equal to the lock range over
these operating frequencies. (Refer to application notes
AN553 and AN535 for information regarding design of the
filter). The feedback resistor RF, and the frequency setting
capacitor CH, are also components of the the horizontal
phase-locked-loop. RF serves two purposes, it provides the
feedback path for the error current to Pin 4, and is a factor
in the phase detector sensitivity which sets the amount of
feedback. CH influences the characteristics of the loop by
being a factor in the oscillator sensitivity.
The error current from the phase detector is determined
by the static phase error between the free running frequency
and the frequency of the horizontal input at Pin 2, and the
value of feedback resistance (RF) between Pins 4 and 5. The
output of the phase detector, Pin 5, will develop a voltage
as a result of the phase detector error current acting on the
HPLL filter. This voltage difference will appear between Pins
5 and 4 and produce the error current provided to the
horizontal oscillator. This error current is:
IERROR = (V5 - V4)
RF

Figure 2. Horizontal Timing

I
I
I
I
I
I

_ _ .J

L _ _ _ _ _ _ _ _ :J

* Polyslyrene

4

R

- - - - ----,
I 10kQ
Hpll I
I 11lF ::f---J'
Filler I
- ___
0.01
I
IL _ _ _
_ _ _ ...l

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
9-85

MC1388
geometry errors. The ramp amplitude affects the number of
sine wave cycles and the ramp offset affects the phase.
By doubling the peak-to-peak amplitude of an input ramp
which created one complete period, a sine wave of two
complete periods is produced. By adding DC offset to
the input ramp, phase advance or delay is produced. Input
ramps to the sine wave generators, which should be DC
coupled to provide bias current, are presented to transistor
bases with high dynamic impedances in excess of 1.0 Mr.!.
A means of applying an adjustable ramp is shown in the
application section.

The average voltage difference (V5 - V4) is capable of
approximately ±2.5 V. The changing current is then
defined by:
1.25 V
-IERROR
RHset
Vertical Timing
Vertical timing for the MC1388 is determined by the frequency of the input at Pin 39 and the charging rate of the
capacitor at Pin 38. Representative circuitry for relevant pins
is shown in Figure 3. The vertical timing is set by an injection
oscillator, with the frequency of the generated ramp being
determined by the current drawn out of Pin 37.That current
is also set with a stable 1.25 Vdc reference and the resistance (RVset) at this pin. At the beginning of a vertical cycle,
the current sourced by Pin 37 is mirrored out of Pin 38 charging the capacitor at Pin 38 with a constant current resulting
in a linear ramp. The charging current of the capacitor (eV)
must be set so the +V output (Pin 35) reaches 2.5 V just
before the next vertical sync pulse arrives to trigger the discharge of the capacitor. The current sourced by Pin 37 is
then again provided to the capacitor and the cycle repeats.

Figure 4. Sine Wave Generator
16

16

16

16

Ramp
Input

WAVEFORMS
Figure 5. Sine Wave Adjustments

Sine Waveforms
The MC1388 has on board circuitry which is capable of
producing sine wave like waveforms. Relevant circuitry is
shown in Figure 4. A total of four subcircuits are available
and each has a 00 and 1800 phase shifted output.The sine
wave generators require a ramp input which can be provided
by the horizontal and vertical ramp outputs of the MC1388.
By modifying the input ramp, the output sine wave can
be tailored to meet particular requirements for geometry
correction. Figure 5 illustrates an example of geometry errors
and the waveforms needed to correct the top to bottom

,

~

Sine2V
(2nd Harmonic) ./

Waveform

Figure 3. Vertical Timing

Vee

39 1 10k
1
1
1
1

1
1
1

L _____ ~~ ________ _
* Polystyrene

/

I

37

38

I

ev* -=-

RVset

-=-

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

9-86

/

,
,
,
,

I

,

,
,
,

Screen Pattern

MC1388
Three Input Multiplier (H'in. V'in and H' V' Amplitude)
Pins 20, 21 and 24, are the inputs to a multiplier with the
output at Pin 23. All three inputs, although named differently,
are the same internally and can be combined in any means
to provide the desired output. However, the product of the
three inputs is restricted to less than 1.9 Vp-p or the output
waveform will experience current limiting. Input bias current
must be provide and therefore the input waveforms require
DC coupling. The output is clamped and blanked during the
appropriate intervals.
Internally Generated Waveforms
Within the MC13BB, operations are performed on the
horizontal and vertical ramps to produce several waveforms
before being provided as outputs through buffers.
Of the internally generated waveforms resulting from
operations on the horizontal ramp are a blanked version of
the horizontal ramp (+H, Pin 6). A blanked, clamped and
squared version of the horizontal ramp (±H2, Pins 7 and B),
and a blanked, clamped and cubed version of the horizontal
ramp(±H3, Pins 17 and 1B).
The vertical ramp is blanked and provided at Pins 35 and
36 (±V). Also, a squared, clamped, and blanked version of
the vertical ramp is provided at Pins 33 and 34 (±V2).
Blanking of the waveforms occurs once every vertical
retrace. Clamping occurs during this blanked interval.
Outputs Buffers and Clamps
The 1B output waveforms are buffered and made available
at the output pins. The output buffers are capable of
supplying 5.0 mA. A simplified schematic of the output stage
is shown in Figure 6.

output (H' V'out). Clamping occurs after the leading edge of
a vertical sync pulse. Blanking logic zeros the outputs for
the time spanned by the first two horizontal pulses during
the vertical sync period (see Figure 7B). Clamping circuitry
works for the line period between the first two horizontal
blanking intervals. Clamping is done by storing a voltage on
the clamp capacitor that is proportional to the current required
to force the output voltage of the buffer to zero. This provides
a sustained current for the next vertical period that is capable
of cancelling the DC offset in the waveform. Internal circuitry
present at the clamp pins is shown in Figure 7A, and a
diagram showing relative timing is shown in Figure 7B.
Figure 7A. Clamp Circuitry for Output Waveforms

I
I
I
I
9,19, I

Vcc

22,32

I
I
I
-= I
I
I
I
I
I
I

Figure 6. Output Circuitry
Figure 7B. Blanking and Clamping Diagram

VertiCalsj

6,7,8,12,
13,15,16,17,
18, 23, 25, 26,
28,29,33,
34,35,36

Horizontal
Ryback

L -___________

~

Clamp Time

Although all outputs are blanked once each vertical period,
not all of them are clamped. Clamping is performed only on
the horizontal and vertical parabola outputs (±H2, ±V2), the
horizontal cubic outputs (±H3), and the three-input multiplier

Blank Pulse

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
9-87

~----------~

MC1388
APPLICATION INFORMATION
The following information is provided to assist designing in
the MC1388.

Horizontal and Vertical Flyback Inputs
Waveforms to the horizontal and vertical flyback inputs
(Pins 2 and 39) must meet similar requirements except for
the frequencies involved. The requirements can be described
as follows:
1) VCC/2.0 + 0.2 V < Yin Peak < VCC
2) VEE + 0.5 < Yin Baseline $ VCC/2 - 0.2 V
3) 2.0 its $ Pulse Width < 1/(2 fH) (Horizontal Input)
2.0 fls $ Pulse Width < 1/(2 fv) (Vertical Input)
and the allowable frequencies of operation are:
A) 10kHz $ fH $ 63 kHz
B) 45 Hz $ tv $ 120 Hz
Figure 8 shows the restrictions on the voltage levels for the
flyback inputs.
Figure 8. Valid Input Levels for Both the Horizontal
(Pin 2) and the Vertical (Pin 39) Inputs.
Vee

n

I I

If CH is chosen to meet the requirements of retrace time
and, trace time » retrace time, then tcharge » tdischarge.
Icharge
1
then fhorizontal = -t-h-- or, fhorizontal = CH t.V
c arge
pop
By choosing CH and determining Icharge the horizontal
frequency can be set, since t.Vp-p is known. Referring to
Figure 2, the current out of Pin 4 is the current Icharge and
is composed of,
I
1.25
I
charge = RHset - ERROR
where IERROR is the current from the phase detector when
the loop is locked and was determined in the FUNCTIONAL
DESCRIPTION to be,
IERROR

=

(V5 - V4)
RF
The horizontal frequency is now defined and is,
{1.25
(V5- V4)}(
1
)
RHset ±
RF
CH t.Vp_p or,

.
fhonzontal

=

fhorizontal

= ffree

vecl2 + 0.2 V Min
Vecl2 - 0.2 V Max

Since the input pins are equipped with ESD diodes, voltages
on these pins should never exceed VCC or VEE by more than

0.5 V.
Horizontal Oscillator and Phase-Locked-Loop
Since the charge and discharge of the capacitor at Pin 3
(CH) is done with constant currents, the voltage waveform
of the capacitor voltage is:

±lJ.V= ± ~
C
,where t.t is the trace or retrace time.
The horizontal frequency is then the inverse of the sum
of the charge time and the discharge time,
fhorizontal

=

1
(tcharge + tdischarge)
where, !charge = trace time andtdischarge = retrace time. This
relates the trace and retrace time to element values, internal
quantities and a design variable, Icharge. So,
tcharge

=

CH t.Vp-p
Icharge

and tdischarge

=

run ± t.j,

where t.f is the frequency difference between the horizontal
free run frequency and the frequency of the input signal,
RHset is the resistance from Pin 4 to ground, RF is the resistor
between Pins 4 and 5, and CH is the capacitor from Pin 3
to ground. It is to be emphasized that this equation holds
true only when the loop is locked.
The phase detector sensitivity, KpD, is determined from
the slope of the curve which describes the average current
output from the phase detector and the phase error related
to that current. It is defined by,
KPD

=

2 IPDmax
900. 10-6
SW 2nf H (A/rad) or, SW 2nf H (A/rad).

IPDmax is the maximum currentthat can be sourced or sinked
from the phase detector and SW is the width of the horizontal
flyback input pulse in seconds. fH is the frequency of the
horizontal flyback input.
The oscillator sensitivity, KO, defined by dfH/dl is,

1
KO = 2.5 CH (Hz/ A)
Since the maximum average voltage difference between Pins
4 and 5 is capable of about ±2.5 V, the maximum error current
transfer from Pin 5 to Pin 4 is,
IERRORmax ,,; ±

~.~

V.

CH t.Vp-p
Idischarge

And also redefines the phase detector sensitivity as,
KpD' -

t. Vp-p and Idischarge are fixed (Idischarge is typically 1.0
mA and t.Vp-p is = 2.5 t.Vp-p). If CH is chosen to meet
the requirements of retrace time and,

2.5 V
RF n SWfH

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

9-88

MC1388
The product of the phase detector sensitivity, the oscillator
sensitivity and the maximum phase error then defines
maximum possible deviation from the free run frequency.
The maximum possible phase error is the phase error
corresponding to one half the width of the horizontal flyback
input pulse or, (SWf2), 2ltfH, so the maximum deviation from
the free run frequency is one half the lock range and is,

±

fFlock = _1_
2
CH RF·

(The value of fFlock should be kept small enough to
prevent loop lock on harmonics. A general rule of thumb
is flock < 10% of the desired horizontal frequency.) Then
IERROR is less than 10% of Icharge, and the horizontal
frequency is almost entirely determined by,

so this becomes, fhorizontal = 2 R 1 C '
Hset H
which is also the horizontal free run frequency. The horizontal
free run frequency should be set at or very near the desired
horizontal frequency since the lock range is centered about
this frequency.
Calculating the external components is then based on the
following requirements:
1) The value of CH satisfies the requirements for retrace time,
or CH ~ 5.6 • 10-4 tdischarge.
2) The value of the resistance from Pin 5 to ground is
given by,
1
.
2 fhorizontal CH

(The value of the resistor calculated for RHset should be
considered approximate. The 5.0 kQ pot shown in the
application circuit of Figure 12 is recommended for
optimization).
3) The resistor RF is such that the lock range is a reasonable
choice (fHfl0) given by,
RF

=

± I:!..Y

=

±!.A!

Cy'
describes the capacitor voltage for the charge and
discharge currents made available at Pin 38. Further, if
tretrace « ttrace then,
fvertical = tv = _1_ = _ _1__
I:!..ttrace
!J.tcharge

fh·
t I
1.25
I:!.. Y
25
p-p=. ,
onzon a = RHset CH I:!..Y p_p'

RHset =

Yertical Timing
To set the vertical timing a capacitor-resistor pair must be
chosen (refer to Figure 3). The vertical timing section is
similar to the horizontal section in that the frequency is
determined by the charge and discharge rate of a capacitor
at Pin 38. However, the vertical ramp oscillator is an
injection type and the proper peak-to-peak voltage must be
set with RYset.
The basic equation,

2
CH (± ~ock)·

For 15,625 Hz, recommended values are, CH = 0.001 IlF,
RHset =30 kil + 5.0 kil variable, and RF ~ 620 kil. For 31 ,250
Hz, recommended values are, CH = 0.001 IlF, RHset = 13
kQ + 5.0 kil variable, and RF ~ 300 kQ.

and the vertical frequency is determined by the charging
current, I:!..Y and the capacitor value.
The reference voltage for developing the charging current
is present at Pin 37 and is nominally 1.25 Y. The charging
current is then defined by the resistance at this node,
1.25
Icharge = - - - RYset
The resistance required can be determined for a particular
frequency and capacitor combination. The capacitor voltage,
I:!.. V. must be nominally 2.5 Vp-p for the specified full scale
vertical outputs. Using this value, the proper combination
RYset and Cy, can be calculated.
The current available to discharge Cy is approximately
800!lA. So, a practical Cy value is described by, Cy :5 3.2
• 10-4 I:!..t, where I:!..t is required retrace time.
This value of Cy is next used to calculate the value RYset
considering the vertical frequency desired,
Icharge

1.25 = Cy I:!..Y = Cy I:!..Y tv or,
RYset
I:!..t

R
1.25
Yset = Cy I:!..Y

_

fv -

_

fv -

1
2 Cy

fv

(The equation given for RVset is approximate and should be
used only as a starting point. The 25 kQ pot in the
applications circuit of Figure 12 is used to optimize this
value.)

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

9-89

1.25
Cy 2.5

MC1388
Sine Wave Generation
Shown in Figure 9 and 10 are two circuits which can be
used to provide drive to the sine generator circuits. These
circuits DC couple to the sine drive inputs providing the
necessary base drive. The circuit in Figure 9 will provide

adequate ramp amplitude for a single cycle of a sine wave
at the horizontal or vertical frequency and the circuit in Figure
10 will provide adequate ramp amplitude for two cycles of
a sine wave.
Figure 10. Sine 2H or 2V Driver

Figure 9. Sine H or V Driver

I

Vee

H orVRamp,
From Pin 6 or 35

5.1k to 6.2k
24k

lOOk

HorV Ramp,
From Pin 6 or 35

Phase
Adjustment

VEE

Sine Frequency
Adjustment

Sine Frequency
Adjustment
510

Sine (H or V) Drive,
to Pin 11 or30

..._------....J

Figure 11. Phase versus DC Offset
180

rn
w
w
w

90

e.
w
rn

""

:I:
Il..
W

~

~
w

a:

-9
0
-180
-0.5

/ '"
-0.25

/

500

Phase

lOOk Adjustment

VEE

Sine (2H or 2V) Drive,
to Pin 14 or 27 ..._------....J

The phase of the output sine wave is a function of the input
ramp DC offset. Figure 11 shows the relationship between
the phase and the offset.
If a phase change is desired, it should be remembered that
the input windows for the sine generators are between
-850 mV and +850 mV centered about zero, therefore, a DC
offset will reduce the allowable input ramp peak-to-peak
amplitude.

<.!l

4.3k

2k

An approximate relation between the number of cycles
and peak-to-peak input voltage is,
V
number of cycles + 0.2
1.25
inp-p =

a:

I

Vee

L
o

/v
0.25

Multiplier Circuit
The multiplier is made up of three inputs, H'in, V'in and
H'V' Amplitude (Pins 20, 21 and 24 respectively), which
are internally equivalent. The voltage output on Pin 23 is
the product of the voltage on the input pins and is
restricted to a maximum output voltage of 1.9 Vp-p, or
current limiting will occur. Any combination of the three
inputs can be used, provided that the product of all the
inputs is less than 5.0 Vp-p.
Application Circuit
Figure 12 shows an application circuit with component
values applicable for,
fhorizontal = 31.25 kHz
fvertical = 60 Hz
±flock = 2.3 kHz
±fpull-in = 2.3 kHz
Figure 13 shows the timing of all the vertical waveforms
for the application circuit. Figure 14 shows the timing of all
the horizontal waveforms for the application circuit.

0.5

De OFFSET

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

9-90

MC1388

Figure 12. Application Circuit of the MC13BB

VCC

Blanking
And
Clamping
Logic

5k RHset13k

Blanking
Reference
Insertion

Blanking
Reference
Insertion

Vertical
Oscillator

II~
430k

Blanking

It'ri
IIIl..:)

Vertical
Ramp

+---....+

O.Ot

c.

E

a:
'"

5l

1

3

DC.

E

0

:z:

c3

11,",\I·'I\'~\I\I\~J\I\·I\r-'

H'in
Drive
• Polystyrene

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
9-91

II

MC1388
Figure 13. Vertical TIming

114'----- Illv -----+1"1

J

Yin
Pin 39

~
I

II

Vertical oscillator triggers off the leading

~ edge oftheflyback input pulse.

~--------------~

t

+2.5V--

Iv

Pin 38
OV-~~~---------~~~-----------

Icharge

+V
Pin 35

+2.5 V -

-~

OV
-2.5V--

\

!discharge

----1

~ ~ Blanking Interval ~
~

:

-~

._v~v--~

\::::::=?""

I
I
I
I

~

i~

"~~:--

~

~

~~:--~

A

~.

I

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
9-92

MC1388
Figure 13. Vertical Timing (continued)

+2.0 V

+ Sine V
Pin 28

-2.0 V

+2.0V

- Sine V
Pin 29

-2.0 V

+2.0 V

+ Sine 2 V
Pin 25

-2.0 V

-Sine2V
Pin 26

-2.0 V

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

9-93

MC1388
Figure 14. Horizontal Timing

I~"---- 11fH

", nI

-----.1"1

n -,----

~ _. -...
I tL

~.J

~
fH

3.4 V

t

-+-,

:

Pin 3
1

MV-

1

OV

"
1 1

1

1 I"

"I 1

1charge

:

~

1

11

+2.5V +H
Pin 6

1
Idischarge

1

1 1
OV -r-----::;;..-""-----.J..-.1.------c::7""=------..
1

1 1

-2.5V -

f+------1charge

-----+1"1 1

~

Idischarge

+2.6 V
+H2
Pin 8
OV
OV
-H2
Pin 7

-2.6V +2.5 V +H3
Pin 17

OV

--I..------:::;;oa--=----.l-I-Y\-----=---""'=--------

,1

-2.5 V -

-H3
Pin 18

1

m-~

!!~

OV

-2.5V-

-

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

9-94

MC1388
Figure 14. Horizontal Timing (continued)

+2.0 V

+ Sine H
Pin 12

-2.0 V

+2.0 V

- Sine H
Pin 13

-2.0 V

+2.0 V

+ Sine 2H
Pin 15

-2.0 V

+2.0 V

+Sine2H
Pin 16

-2.0 V

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
9-95

MOTOROLA

MC1391

SEMICONDUCTOR-----TECHNICAL DATA

TV HORIZONTAL
PROCESSOR

TV HORIZONTAL PROCESSOR

SILICON MONOLITHIC
INTEGRATED CIRCUIT

The MC1391 provides low-level horizontal sections including phase
detector, oscillator and pre-driver. This device was designed for use in all types
of television receivers.
• Internal Shunt Regulator
• Preset Hold Control Capability
• ±300 Hz Typical Pull-In
• Linear Balanced Phase Detector
• Variable Output Duty Cycle for Driving Tube or Transistor
• Low Thermal Frequency Drift
• Small Static Phase Error
• Adjustable DC Loop Gain
• Positive Flyback Inputs

Figure 1. Typical Application Circuit

Vnonr.t!ll
+30V
RA

RB

470 1470
CA
l00IlF

PSUFFIX
PLASTIC PACKAGE
CASE 626

r

+ Ro
2.7k

~{,

+lS0V

~3k

Hold

,..........,

Ry

0.0068

lSOk

III

RE
2.4k

r

~

o.oosJ
IIF

CB
7

8

2.2k

6

4k
lOW

Rx
3.3k

12k

J

Cc~

J

S

Rzt
82k

1 :>

MJl0S or Equiv

~II

0.001
IIF

~S.3:1

10.1I1F

39k

r-----

f?
~

3~

2~

IQ'

S.OIlF;;;::; 1.S

y

MRD
1140
or
Equiv

~.~
or Equiv

O.OO3
IIF
-=-

f

-.

-20VSync

f°.1 I1F

t RZ - 6.8 k per 100 V of flyback amplitude.

This circuit has an oscillator pull-in range of ±300 Hz. a noise bandwidth of 320 Hz. and a damping factor of 0.8.

MOTOROLA liNEAR/INTERFACE ICs DEVICE DATA

9-96

High
Voltage
-=-TriPler

JL

ll1F

15k
MCl391P

...
::1

0
K
E

;::;0.01
IIF

;:r 0.2
IIF

MC1391
MAXIMUM RATINGS (TA = +25°C, unless otherwise noted.)
Value

Unit

Supply Current

Rating

40

mAdc

Output Voltage

40

Vdc

Output Current

30

mAdc

Sync Input Voltage (Pin 3)

5.0

V(p_p)

Flyback Input Voltage (Pin 4)

5.0

V(p_p)

Power Dissipation (Package limitation)
Plastic Package
Derate above TA = +25°C

625
5.0

mW
mW/oC

oto +70

°C

--65 to +150

°C

Operating Temperature Range (Ambient)
Storage Temperature Range

ELECTRICAL CHARACTERISTICS (TA = +25°C, unless otherwise noted. See Test Circuit 01 Figure 2, all switches in position 1.)
Min

Typ

Max

Regulated Voltage (Pin 6)

8.0

8.6

9.4

Vdc

Supply Current (Pin 6)

-

20

-

mAdc

Collector-Emitter Saturation Voltage (Output Transistor Ql in Figure 6)
(lc = 20 rnA, Pin 1 ) Vdc .

-

0.15

0.25

Voltage (Pin 4)

-

2.0

Oscillator Pull-in Range (Adjust RH in Figure 2)
Oscillator Hold-in Range (Adjust RH in Figure 2)

-

Static Phase Error
(AI = 300 Hz)

Characteristics

Unit

Vdc

-

Vdc

±300

-

Hz

±900

-

Hz

-

0.5

-

Free-running Frequency Supply Dependance
(Sl in position 2)

-

±3.0

-

Phase Detector Leakage (Pin 5)
(All switches in position 2)

-

-

±1.0

Sync Input Voltage (Pin 3)

2.0

-

5.0

V(p-p)

Sawtooth Input Voltage (Pin 4)

1.0

-

3.0

V(p-p)

/I

-=

33k

~1-;-Sl

6

6800PF f

I

8

.VM
4
Vee +30V (See Figure 5)

Output
Pulse
+30V
1

loOk

-4:-

39k

2

7

T
-=

3
MC1391P

150k

/3.0k
loOk

~1~

5

O.lIo1F

+4.0V

~-

lolA

2

1

2

12k

Hz/Vdc

Figure 2. Test Circuit

r' .
O.lIo1F

JI

S2

2

JH~
0.003 1
IoIF

Pulse Generator
Output =+50 V
1210lS

2.0k

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
9-97

loiS

Pulse Generator
Sync Pulse =
-20V,5.01olS,
10 =15.750 Hz

MC1391
TYPICAL CHARACTERISTICS
Figure 4. Frequency Drift versus Warm-Up Time

Figure 3. Frequency versus Temperature
40

30
20

- ,

10

........

¥

;:- -10
()

iIi

-20

-30
cr:
u.. -40

N'

'£ 30

I:i:

./

a:
c

r---....

~

~

Reference Frequency
= 15.750 Hz

>-

()

1'-....

S3 in Position 2

z

w

/

20

/
I

~

~

0

w

cr:
u..

i'

-50

.,.:

V

10

Reference Frequency
= 15.750Hz



.j

/

3.5

/

3.25

/

3.0
2.75

:/

o

/
10

20
30
POSITIVE PULSE WIDTH (I1S)

40

50

Figure 6. Circuit Schematic

3
Sync Input

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

9-98

90

120

MC1391
CIRCUIT OPERATION
The MC1391 P contains the oscillator, phase detector and
predriver sections needed for a television horizontal APC loop.
The oscillator is an RC type with one pin (Pin 7) used to
control the timing. The basic operation can be explained
easily. I! it is assumed that 07 is initially off, then the capacitor
connected from Pin 7 to ground will be charged by an external
resistor (RC) connected to Pin 6. As soon as the voltage at
Pin 7 exceeds the potential set at the base of 08 by resistors
R8 and R10, 07 will turn on and 06 will supply base current
to 05 will discharge the capacitor through R4 until the base
bias of 07 falls below that of 08, at which time 07 will turn off
and the cycle repeats.
The sawtooth generated at the base of 04 will appear
across R3 and turn off 03 whenever it exceeds the bias
set on Pin 8. Sy adjusting the potential at Pin 8, the duty
cycle (MSR) at the predriver output pin (Pin 1) can be
changed to accommodate either tube or transistor horizontal
output stages.

The phase detector is isolated from the remainder of the
circuit by R14 and Z2. The phase detector consists of the
comparator 015, 016 and the gated current source 017.
Negative going sync pulses at Pin 3 turn off 012 and the
current division between 015 and 016 will be determined by
the phase relationship of the sync and the sawtooth waveform
at Pin 4, which is derived from the horizontal flyback pulse. I!
there is no phase difference between the sync and sawtooth,
equal currents will flow in the collectors of 015 and 016 each
of hal! the sync pulse period. The current in 015 is turned
around by 018 so that there is no net output current at Pin 5
for balanced conditions. When a phase offset occurs, current
will flow either in or out of Pin 5. This pin is connected via an
external low-pass filter to Pin 7, thus controlling the oscillator.
Shunt regulation for the circuit is obtained with a zero
temperature coefficient from the series combination of 01, 02
and Z1.

APPLICATION INFORMATION
Although it is an integrated circuit, the MC1391 P has all the
flexibility of a conventional discrete component horizontal
APC loop. The internal temperature compensated voltage
regulator allows a wide supply voltage variation to be
tolerated, enabling operation from nonregulated power
supplies. A minimum value for supply current into Pin 6 to
maintain zener regulation is about 18 mA. Allowing 2.0 mA for
the external dividers
RA + RS = Vno~~e;(1~ina-8·8
Components RA, RS and CA are used for ripple rejection. I!
the supply voltage ripple is expected to be less than 100 mV
(for a 30 V supply) then RA and RS can be combined and
CA omitted.
The output pulse width can be varied from 6.0 J.ls to 48 J.lS
by changing the voltage at Pin 8 (see Figure 5). However, care
should be taken to keep the lead lengths to Pin 8 as short as
possible at Pin 1. The parallel impedance of RD and RE should
be close to 1.0 kn to ensure stable pulse widths.
For 15 mA drive at saturation
Vnonreg -0.3
RF
15x1Q=3
The oscillator free-running frequency is set by RC and Cs
connected to Pin 7.' For values of RC ~ Rdischarge (R4 in
Figure 6), a useful approximation for the free-running
frequency is

Increasing RC will raise the DC loop gain and reduce the
static phase error (S.P.E.) for a given frequency offset.
Secondary effects are to increase the natural resonant
frequency of the loop (wn) and give a wider pull-in range from
an out-of-Iock condition. The loop will also tend to be
underdamped with fast pull-in times, producing good airplane
flutter performance. However, as the loop becomes more
underdamped impulse noise can cause shock excitation of
the loop. Unlimited increase in the DC loop gain will also raise
the noise bandwidth excessively causing horizontal jitter with
thermal noise. Once the DC loop gain has been selected for
adequate SPE performance, the loop filter can be used to
produce the balance between other desirable characteristics.
Damping of the loop is achieved most directly by changing the
resistor RX with respect to Ry which modifies the AC/DC gain
ration (m) of the loop. Lowering this ratio will reduce the pull-in
range and noise bandwidth (fnn). (Note: very large values of
Ry will limit the control capability of the phase detector with a
corresponding reduction in hold-in range.)
Static phasing can be adjusted simply by adding a small
resistor between the flyback pulse integrating capacitor and
ground. The sync coupling capacitor should not be too small
or it can charge during the vertical pulse and this may result in
picture bends at the top of the CRT.
Note: In adjusting the loop parameters, the following
equations may prove useful:

1
fO=0.6 RCCS

fnn =

Proper choice of RC and Cs will give a wide range of
oscillator frequencies - operation at 31.5 kHz for countdown
circuits is possible for example. As long as the product RCCS
'" 10-4 many combinations of values of RC and Cs will satisfy
.the free-running frequency requirement of 15.734 kHz.
However, the sensitivity of the oscillator (~) to control-current
from the phase detector is directly dependent on the
magnitude of RC, and this provides a convenient method of
adjusting the DC loop gain (fc).
For a given phase detector sensitivity (J.l) = 1.60 x 10-4 Nrad
fc= J.l~and~=3.15xRC Hz/mA

wn

1 xX2TwC
4 T

X

=)(1 :~)T

wC= 27tfc
T=RyCC

X2T-WC
K=
4
where: K = loop damping coeffecient

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

9-99

X = RX
Ry

MOTOROLA

MC3340

SEMICONDUCTOR-----TECHNICAL DATA

ELECTRONIC ATTENUATOR

ELECTRONIC ATTENUATOR
The MC3340 is a simple but very effective electronic attenuator. This device
offers up to 80 dB of attenuation control for frequencies to 1.0 MHz. THD
(distortion) is less than 1% - up to 15 dB attenuation and less than 3% - up
to 40 dB.
Typical uses include instrumentation control, remote control audio amplifiers,
electronic games, and CATV (cable TV) set-top converter audio control.

SILICON MONOLITHIC
INTEGRATED CIRCUIT

• Designed for use in:
DC Operated Volume Control
Compression and ExpanSion Amplifier Applications

1
PSUFFIX
PLASTIC PACKAGE
CASE 626

• Controlled by DC Voltage or External Variable Resistor
• Economical 8-Pin Dual-In-Line Package

PIN CONNECTIONS

MAXIMUM RATINGS (TA = +25'C, unless otherwise noted.)
Rating

Symbol

Value

Unit

VCC

20

Vdc

Power Dissipation@TA= 25'C
Derate above TA = 25'C

PD

1.2
10

W
mWI'C

Operating Ambient Temperature Range

TA

oto +75

'c

Power Supply Voltage

Vin08VCC
Control 2
7 Vo

Figure 1. Typical DC Remote Volume Control

Vee
1. 0llF

1

1----6--

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

9-100

Gnd 3

NC 4

6 Ro"off

5 NC

MC3340

ELECTRICAL CHARACTERISTICS (ein ~ lOa mVrms, f ~ 1.0 kHz, VCC
Circuit

~ 16 Vdc, TA ~ +25°C, unless otherwise noted.)

Characteristics

Min

Typ

Max

Unit

18

Vdc

Control Terminal Sink Current, Pin 2
(ein ~ 0)

2.0

mAde

Maximum Input Voltage

0.5

Vrms

0.8

Operating Power Supply Voltage

Voltage Gain

II

13

dB

Attenuation Range from Maximum Gain
(V2 ~ 6.5 Vdc)

70

80

dB

Total Harmonic Distortion (Pin 2 Gnd)
(ein ~ 100 mVrms, eo ~ Av • ein)

0.6

Figure 2. Circuit Schematic

~

5.lk

1

750

4.7k

h..,.

Output

5.lk

N 1-2~

CJ- =

3.9k

~

2

ControI

5.lk

5.lk

=
Input

=

I

I

....l

I-...
20k

510

-

1.3k

-

1.5k
-

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
9-101

Roll-off

7

200

750

=

=

5.lk
6

6.2k

5.lk

510

-

1.0

%

MC3340
Figure 3. Attenuation versus
DC Control Voltage

o

I,

~

"

20

Vcc=
8.0Vdc _

~

10

.""

~ 40
o
~
~ 60

....
~
\~

....
"~
\,"\

w

~

Vcc=
K,12VdC

80

~~

\'

2',

"
,
.'\:'.
"

20
VCC=

2.5

-

~ 16Vdc

:::!.

,

z

40

~z

60

w

"' ..'-..:
l',

5.5

o dB Reference = 13 dB Gain
f=1.0kHz

80

6.0

4.0

Figure 5. Frequency Response

:::!. 10

z

r-

Input voltage (ein) = 10 mV
Pin 6 uncompensaled

6.

z

~

w

.",..

6.0

.--

1,/

C!)

"

..... .....

~

30

.....
40

-

-

i""""

1:5

~ 4.0

~O_

.jJ 4.0
2.0
100

8.0

C!)

,

6.0

o

"

...,

8.0
10
15
20
RC, CONTROL RESISTOR (kO)

'E:
~

~

C!)

~

,~

Figure 6. Output Voltage Swing

,

12

1:5

r-...'..

10

10

~ 8.0

' '"

RC, is from Pin 2 to ground ' ....

100

6.5

14

:;;:

~~

~~

~

"

" "

3.5
4.5
V2, CONTROL VOLTAGE M

",

0

'1:\,

r\..' ....

r-....

10

~

"

100
1.5

-

0

I,

Figure 4. Attenuation versus
Control Resistor

2.0

o
1.0k

10k

lOOk
1.0M
f, FREQUENCY (Hz)

10M

8.0

100M

9.0

10

11

12

Figure 7. Total Harmonic Distortion

g

4.0

z

o

>=

~ 3.0

~

/

o
o

i§

/

2.0

I

~

~ 1.0
~
d'

i=

0

/

V

odB Reference = 13 dB Gain
f=1.0kHz
eo = 2.5Vnns

I

_r"'"

o

13

14

15

Vcc, SUPPLY VOLTAGE M

10

20

30
40
50
ATTENUATION (dB)

60

70

80

MOTOROLA LlNEARIINTERFACE ICs DEVICE DATA
9-102

16

17

18

MOTOROLA

MC3346

SEMICONDUCTOR-----TECHNICAL DATA

GENERAL PURPOSE
TRANSISTOR ARRAY

General Purpose Transistor Array
One Differentially Connected Pair and
Three Isolated Transistor Arrays

SILICON MONOLITHIC
INTEGRATED CIRCUIT

The MC3346 is designed for general purpose, low power applications for consumer and industrial designs,
• Guaranteed Base-Emitter Voltage Matching
• Operating Current Range Specified: 10 I1A to 10 mA
• Five General Purpose Transistors in One Package
PSUFFIX
PLASTIC PACKAGE
CASE 646

MAXIMUM RATINGS
Rating

Symbol

Value

Unit

Collector-Emitter Voltage

VCEO

15

Vdc

Collector-Base Voltage

VCBO

20

Vdc

Emitter-Base Voltage

VEB

5.0

Vdc

Collector-Substrate Voltage

DSUFFIX
PLASTIC PACKAGE
CASE 751A
(SO-14)

VCIO

20

Vdc

Collector Current - Continuous

IC

50

mAdc

Total Power Dissipation @ TA = 25°C
Derate above 25°C
Derate Each Transistor @ 25°C

PD

1.2
10
300

W
mW/oC
mW/oC

Device

Operating Temperature Range
Storage Temperature Range

ORDERING INFORMATION

TA

-40 to +85

°C

MC3346D

Tstg

-65 to +150

°C

MC3356P

PIN CONNECTIONS

Pin 13 is connected 10 subslrate and must remain at the lowest circuil potential.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

9-103

Temperature Range
-40° to +85°C

Package
SO-14
Plastic DIP

MC3346
ELECTRICAL CHARACTERISTICS (TA = +25°C, unless otherwise noted.)

I

I

Symbol

Min

Typ

Max

Unit

Collector-Base Breakdown Voltage
(IC = 10 IlAdc)

V(BR)CBO

20

60

-

Vdc

Collector-Emitter Breakdown Voltage
(IC = 1.0 mAdc)

V(BR)CEO

15

-

-

Vdc

Collector-Substrate Breakdown Voltage
(IC = 10 1lA)

V(BR)CIO

20

60

-

Vdc

Emitter-Base Breakdown Voltage
(IE = 10 IlAdc)

V(BR)EBO

5.0

7.0

-

Vdc

Collector-Base Cutoff Current
(VCB = 10 Vdc, IE = 0)

ICBO

-

-

40

nAdc

DC Current Gain
(IC = 10 mAdc, VCE = 3.0 Vdc)
(IC = 1.0 mAdc, VCE = 3.0 Vdc)
(IC = 10 IlAde, VCE = 3.0 Vde)

hFE

-

140
130
60

-

Base-Emitter Voltage
(VCE = 3.0 Vdc, IE = 1.0 mAdc)
(VCE = 3.0 Vdc, IE = 10 mAdc)

VBE

0.72
0.8

-

-

0.3

2.0

IlAdc

Characteristics

STATIC CHARACTERISTICS

40

-

Input Offset Current for Matched Pair 01 and 02
(VCE = 3.0 Vdc, IC = 1.0 mAdc)
Magnitude of Input Offset Voltage
(VCE = 3.0 Vdc, IC = 1.0 mAdc)

-

Vdc

-

11101- 11021

-

-

-

0.5

5.0

mVdc

-

-1.9

-

mV/oC

Temperature Coefficient of Base-Emitter Voltage
(VCE = 3.0 Vdc, IC = 1.0 mAdc)

aVBE
dT

Temperature Coefficient

laVIOI
dT

-

1.0

-

JlV/oC

Collector-Emitter Cutoff Current
(VCE = 10 Vdc, IB = 0)

ICEO

-

-

0.5

IlAdc

Low Frequency Noise Figure
(VCE = 3.0 Vdc, IC = 100 JlAdc, RS = 1.0 kn, f = 1.0 kHz)

NF

-

3.25

-

dB

Forward Current Transfer Ratio
(VCE = 3.0 Vdc, IC = 1.0 mAde, f = 1.0 kHz)

hFE

-

110

-

Short Circuit In~ut Impedance
(VCE = 3.0 dc, IC = 1.0 mAdc)

hie

-

3.5

-

Open Circuit Output Impedance
(VCE = 3.0 Vdc, IC = 1.0 mAdc)

hoe

-

15.6

-

Jlmhos

Reverse Voltage Transfer Ratio
(VCE = 3.0 Vdc, IC = 1.0 mAdc)

hre

-

1.8

-

x10-4

Forward Transfer Admittance
(VCE = 3.0 Vdc, IC = 1.0 mAdc, f = 1.0 MHz)

Yfe

31-j1.5

-

Input Admittance
(VCE = 3.0 Vdc, IC = 1.0 mAdc, f = 1.0 MHz)

Yie

0.3 + jO.04

-

out~ut

Yoe

-

0.001 + jO.03

-

-

IT

300

550

MHz

DYNAMIC CHARACTERISTICS

Admittance
VCE = 3.0 Vdc, IC = 1.0 mAdc, f = 1.0 MHz)

kn

Emitter-Base CapaCitance
(VEB = 3.0 Vdc, IE = 0)

Ceb

-

0.6

-

Collector-Base Capacitance
(VCB = 3.0 Vdc, IC = 0)

Ccb

-

0.58

-

pF

Collector-Substrate Capacitance
(VCS = 3.0 Vdc, IC = 0)

CCI

-

2.8

-

pF

Current-Gain - Bandwidth Product
(VCE = 3.0 Vdc, IC = 3.0 mAdc)

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

9-104

pF

MC3346
Figure 1. Collector Cutoff Current
versus Temperature (Each Transistor)
//

I- IB=O

./
./

VCE=10V

,
......

Figure 2. Collector Cutoff Current
versus Temprature (Each Transistor)

./

Lh

/

r--

L VCE=5.0V

f--

VCB=15V~

.....-: ......
/

./

25

50

75

100

125

25

TA, AMBIENT TEMPERATURE (OC)

Figure 3. Input Offset Characteristics
for Q1 and Q2

.a.
ffi
~

i3

w
t!l

0.3

~

!:3

",

0.03

g 0.02

50
75
100
TA, AMBIENTTEMPERATURE (OC)

5.0

0.8

4.0

"0-

a: 0.7

~
~

./

-

0.01
0.01

V

VBE

i

_f-

0.6

2.0 O

~

If 0.5

>
0.1

0.2

0.3

0.5 0.7 1.0

0.01

0.05

IC, COLLECTOR CURRENT (mAde)

0.1

0.5

Figure 5. DC Current Gain
140

!z
ll:!
a:

3.0
2.5

./
hFE

110

~

/"

=>

o

~

z

2.0

~

1.5

15

1.0

§

(.)

90
70

3.5

/--

(.)

g

0.95

;

I hFE11
l!ml
hFE2 or hFEl

./

50
0.01

1.0

IE, EMITTER CURRENT (mAde)

z
~ 130

IIII
0.05

0.1

0.5

1.0

I I II r
5.0

g

iii

0.9
0.85 ~
0.8 ~
0.75 .c
10

IE, EMITTER CURRENT (mAde)

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
9-105

1.0

5.0

~

:e:
o

IVlfl

0.4
0.05

~

III
!:3

3.0 ~

1-----

~

0.02 0.03

125

0.9

~

0.2

~

!:;

VCB=10V

Figure 4. Base-Emitter and Input Offset
Voltage Characteristics

1.0
0.7
0.5

0.1
u.. 0.07
o 0.05

~'VCB=5.0V

".~

/'"

:[

'"

o ->
10

MOTOROLA

MC3373

SEMICONDUCTOR-----TECHNICAL DATA

Remote Control Amplifier/Detector
The MC3373 is intended for application in infrared remote controls. It provides
the high gain and pulse shaping needed to couple the signal from an IR receiver
diode to the tuning control system logic.
• High Gain Pre-Amp
• Envelope Detector for PCM Demodulation
• Simple Interface to Microcomputer Remote Control Decoder
• Use with Tuned Circuit for Narrow Bandwidth, Lower Noise Operation
• Minimum External Components
• Wide Operating Supply Voltage Range
•
•
•
•
•

REMOTE CONTROL WIDEBAND
AMPLIFIER WITH
DETECTOR

PSUFFIX
PLASTIC PACKAGE
CASE 626

Low Current Drain
Improved Retrofit for NEC Part No. IlPC1373
MC14497 Recommended IR Transmitter
MLED81 Complementary Emitter
MRD821 Complementary Detector Diode

o SUFFIX
PLASTIC PACKAGE
CASE 751
(SO-8)

PIN CONNECTIONS
MAXIMUM RATINGS
Rating

Symbol

Value

Unit

VCC

15

Vdc

Operating Temperature Range

TA

Ot075

DC

Storage Temperature Range

Tstg

-55 to +125

DC

TJ

150

DC

PD
1/8JA

1.25
10

W
mW/DC

Supply Voltage

Junction Temperature
Power DisSipation, Package Rating
Derate above 25 DC

Output
Filter

Tank
Peak Hold

Figure 1. Remote Control Application
40 kHz Carrier
+9.0Vdc

1500111'

To
Keyboard
17

16
14
11

18

MC14497
(3)
MLED71
Inkared
Emitting
Diodes

4
5
6

1N914

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

9-106

Was this redrawn
for LSG-

MC3373
RECOMMENDED OPERATING CONDITIONS
Symbol

Min

Power Supply Voltage (25°C)

Characteristics

VCC

4.75

-

15

Vdc

Power Supply Voltage (O°C)

VCC

5.0

-

15

Vdc

fin

30

40

80

kHz

Input Frequency

Typ

Max

Unit

ELECTRICAL CHARACTERISTICS (TA = 25°C, VCC = 5.0 V, fin = 40 kHz, Test circuit of Figure 2)
Characteristics

Symbol

Min

Typ

Max

Unit

Power Supply Current

ICC

1.5

2.5

3.5

mAdc

2.4

2.8

3.0

Vdc
ItVp,p

Input Terminal Voltage

V(Pin 7)

Input Voltage Threshold

Vin

-

50

100

Input Amplifier Voltage Gain
(V[Pin 3] = 500 mVp·p)

AV

-

60

-

dB

Input Impedance

rin

Output Voltage, Vin

= 1.0 mVp-p

Output Leakage, VCC

= VOH = 15 Vdc

Output Voltage, Input Open

40

60

80

kQ

VOL

-

-

0.5

V

IOH

-

-

2.0

itA

VOH

-

-

5.0

Vdc

NOTE: See AN1 016 for IR System Information.

Figure 2. Test Circuit
VCC~

100k
10ltF
+

0.033

h

-=- 5.0mH

5.0Vdc

Output
COil:
TOKOINC.
CANS·4612Z

51
22

(Bottowm View)

Figure 3. Block Diagram

VCC
8

Tuned
Circuit and VCC

Detector
Threshold (Fig. 5)

3
Output
Output
Decoupling

Input from
Detector

Ground

Gain Adjust
(Fig. 4)

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

9-107

MC3373
Figure 4. Input Amplifier Gain

Figure 5. Detector Threshold
1.0
~

1= Vee=

~

r-

~

""'r-.

10Vdc

~

" I'\.

0.1

I\..

I - Vee = 8.5 Vdc

z
..,

I

z

ii:

~ 0
10
100
RpIN6, PIN 6 RESISTOR (0)

\

'\

~

~w
1.0

Vee = 12Vdc

1\

\

::i!

r---

~

~"'"
........

"

,......"

~

I

50

100

150

-

200

250

RplN4, PIN 4 RESISTOR (kO)

APPLICATIONS INFORMATION
The MC3373 is a specialized high gain amplifier/signal
processor bipolar analog IC designed to be the core of infrared
carrier signaling systems. The amplifier section has an
Automatic Bias Level Control (ABLe) for simplified direct
connection to an IR detector diode. Generally, it is operated
AC coupled, utilizing an input high-pass filter to eliminate
power line related noise, particularly that from florescent and
gas vapor lamps. The use of a high frequency carrier is
strongly recommended as opposed to simply detecting "DC"
bursts of IR energy. In the carrier mode setup the MC3373 acts
like an AM receiver subsystem, amplifying the incoming
signal, demodulating it, and providing some basic wave
shaping of the demodulated envelope. The tuned circuit at
Pin 3 provides the main system selectivity reducing random
noise interference and permitting multichannel operation in
the same physical area without falsing. In the multichannel
case the carriers must not be harmonically related. The
bandwidth is determined primarily by the "Q" of the coil.
Bandwidth may be increased by loading, shunting, the coil
with a resistor.
Since this is a very high gain system operating at relatively
high frequencies, care must be taken in the circuit layout and
construction. Do not use wire wrap or non-ground plane
protoboard. A simple single sided PCB with ground fill o! a
two-sided board with a solid groundplane and top Side
point-to-point will provide consistent high performance. There
is a wide array of IR emitter/detectors available. The Motorola
MLED81 and MRD821 are an excellent low cost combination
to use with the MC3373. Multiple emitters are recommended
for extended range. Application note ANl 016 is must reading
as it covers basic IR systems and specific applications.

........

I

I

o

1000

I

Figure 6. Typical Signal Waveforms
Pin 7
Input
50IlVP.P(min)

~2.8V

Pin 3
Amplifier
Output
= 500mVp.p

~Vee

Pin 1
Output

+-l I-- 512msburslof30-80kHz

~

r-I
I.!.wd
_

r--Vee
___ 0.5 V

---------0

The input amplifier gain is approximately equal to the load
impedance at Pin 3, divided by the resistor from Pin 6
to ground. Again, the low frequency gain can be reduced
by using a small coupling capacitor in series with the
Pin 6 resistor.
The load may be reSistive, with only, or tuned, as in the test
circuit. The amplifier output is limited by back-to-back
clamping diodes, level shifted, buffered and fed to a negative
peak detector. The detector threshold is s~t by the e~ternal
resistor on Pin 4, and an internal 6.B k.Q resistor and diode to
VCC. The capacitor from VCC to Pin 4 quickly charges during
the negative peaks and then settles toward the set-up voltage
between signal bursts at a rate roughly determined by the
value of the capacitor and the 6.B k resistor. The external
capacitor at Pin 2 filters the ultrasonic carrier from the pulses.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
9-108

MC3373
CIRCUIT DESCRIPTION
01 to 04 set the bias on the amplifier input at approximately
2.8 V. 06 to 010 form the input amplifier, which has a gain of
about 80 dB when R(Pin 6) = 0, 05 sinks input current from
the photo diode and keeps the amplifier properly biased.

018 to 020 level shift and buffer the signal to the negative
peak detector, 022 and 023. Output devices 026 and 027
conduct during peaks and pull the output (Pin 1) low. The
capacitor on Pin 2 filters out the carrier.

Figure 7. Internal Schematic

Vee
r-----~--~-.--~~~~------~~~+_--~----~~--------~r_~

8

R23
15k

Rl
56k

Input

Output

1

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
9-109

MOTOROLA

SEMICONDUCTOR-----TECHNICAL DATA

Monomax Black and White
TV Subsystem
The MONOMAX is a single-chip IC that will perform the electronic functions
of a monochrome TV receiver, with the exception of the tuner, sound channel,
and power output stages. The MC13001XP and MC13007XP will function as
a drop-in replacementfor the MC13001 P and MC13007P, but some external IF
components can be removed for maximum benefit. IF AGC range has been
increased, video output impedance lowered, and horizontal driver output
current capability increased.

MC13001XP
MC13007XP

MONOMAX
BLACK AND WHITE TV
SUBSYSTEM
SILICON MONOLITHIC
INTEGRATED CIRCUITS

• Full Performance Monochrome Receiver with Noise and Video Processing
(Black Level Clamp, DC Contrast, Beam Limiter)
• Video IF Detection On-Chip (No Coils, No Pins, except Inputs)
• Noise Filtering On-Chip (Minimum Pins and Externals)
• Oscillator Components On-Chip (No Precision Capacitors Required)
• MC13001 XP for 525 Line NTSC and MC13007XP for 625 Line CCIR
• Low Dissipation in All Circuit Sections
• High Performance Vertical Countdown

PSUFFIX
PLASTIC PACKAGE
CASE 710

• 2-Loop Horizontal System with Low Power Start-Up Mode
• Noise Protected Sync and Gated AGC System
• Designed to work with TDA1190P or TDA3190P Sound IF and Audio
Output Devices
Figure 1. Basic Elements of the System
VIF IF Decoupling
4 2
6

Sound
IF
28

Black
Clamp
Contrast
Beam Umit
26 25 27

,--"'024 Video Out

IFln
IFln

8 AGC Filter
RFAGC 11
RF AGC Delay 10

r--------I-----~023

Vertical Sync

AGC 9a.-t--=-:-';::-:'---,----'
Flyback

15O-~---1

Honzontal Sync O.--I-------+...J
Separator 7

, - I -....Q22 Vertical Out

2t Vertical
Feedback
VCC 18
20 Vertical Size
+8.0V Out 19

17 Honzontal Out

13
Horizontal Phase
Detector 1

12
Honzontal Frequency

14
Horizontal Phase
Detector 2

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
9-110

MC13001 XP, MC13007XP
MAXIMUM RATINGS (TA = 25"C, unless otherwise noted.)
Rating
Power Supply Voltage -

Pin 18

Symbol

Value

Unit
Vdc

VCC

+16

Power Dissipation

Po

1.0

W

Horizontal Driver Current- Pin 17

Ihor

-20

rnA

IRFAGC

20

rnA

IVID

5.0

rnA

Ivert

5.0

rnA

Ireg

35

rnA

RBJC

60

"CIW
"C

RF AGC Current -

Pin 11

Video Detector Current -

Pin 24

Vertical Driver Current -

Pin 22

Auxiliary Regulator Current -

Pin 19

Thermal Resistance Junction-to-Case
Maximum Junction Temperature

TJ

150

Tstg

-65 to + 150

"C

TA

0" to + 70

"C

Symbol

Value

Unit

Ihor

,,10

rnA

RF AGC Current

IRFAGC

,,10

rnA

Regulator Current

Ireq

,,20

rnA

Storage Temperature Range
Operating Temperature Range

RECOMMENDED OPERATING CONDITIONS
Rating
Horizontal Output Drive Current

ELECTRICAL CHARACTERISTICS (VCC = 11.3 V, TA = 25"C)
Symbol

Min

Typ

Max

Power Supply Current

Characteristics
Pins 18, 19

ICC

44

-

76

rnA

Regulator Voltage

Pin 19

Vreg

7.2

8.2

8.8

Vdc

Pin 12

thor(NOM)

Unit

HORIZONTAL SPECIFICATIONS
Oscillator Frequency (Nominal)
Oscillator Sensitivity
Start-Up Frequency (118

= 4.0 rnA)

thor

13

-

19

-

230

-

-

+10

-10

Oscillator Temperature Stability (0 "TA" 75"C)

-

Phase Detector 1 (Charge/Discharge Current)
(Non-Standard Frame)
(Standard Frame)

1<\>1

Phase Detector 2
(Charge/Discharge Current)

V<\>2

-

Phase Detector 1
(Output Voltage Limits)

V<\>1

-

7.5 (max)
2.5 (min)

Phase Detector 2
(Output Voltage Limits)

V<\>1

-

7.7 (max)
1.5 (min)

Phase Detector 1
(Leakage Current)

-

-

2.0

Phase Detector 2
(Leakage Current)

-

-

3.0

Horizontal Delay Range
(Sync to Flyback)

-

Horizontal Output Saturation Voltage
(117 = 15 rnA)

VI7(sat)

Phase-Detector 1 (Gain Constant)
(Out-ot-Lock)
(In-Lock)

-

50

-

±900
±400

-

Hz

-

~A

-

rnA

-

Vdc

-

-

0.3

-

5.0
10

-

±500

±750

-

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
9-111

18 (max)
5.0 (min)

%

-

-

-

Horizontal Pull-In Range

+1.0
-0.6

kHz
HzJ~A

~A

~s

Vdc
~N~s

Hz

MC13001 XP, MC13007XP
VERTICAL SPECIFICATIONS
Characteristics

Symbol

Min
-0.6

Typ

Max

Unit

Output Current

Pin 22

122

-

-

Feedback Leakage Current

Pin 21

121

-

-

6.0

~A

V21

-

5.1

-

Vdc

120

500

-

gOO

~A

-

-

0.3

~

-

7.5

-

Vdc

-

6.0

-

kn

2.0

-

pF

-

80

-

~Vrms

-

75

-

MHz

Feedback Maximum Voltage
Ramp Retrace Current

Pin 20

Ramp Leakage Current

Pin 20

mA

IF SPECIFICATIONS
Regulator Voltage

V4

Input Bias Voltage

V2,6

Input Resistance

Rin

Input Capacitance (VAGC Pin 8 = 4.0 V)

Cin

Sensitivity
(V8 = 0 V, 400 Hz 30% MOD, V28 = 0.8 Vpp)
Bandwidth

BW

4.2

VIDEO SPECIFICATIONS
Zero Carrier Voltage (See Figure 5)

Pin 28

-

7.0

-

Vdc

Output Voltage (See Figure 6)
White to Back Porch

Pin 24

-

1.4

-

V

-

6

-

%
Degrees
~A

Differential Gain
Differential Phase (IRE Test Method)

4
126

-

10

-

V27

-

14:1
1.0

-

Vdc

RF (Turner AGC Output Current (V 11 = 5.5 V)

111

5.0

-

-

mA

AGC Delay Bias Current

110

-

-10

-

~A

Ig

-

1.0

-

mA

Contrast Bias Current

Pin 26

Contrast Control Range
Pin 27

Beam Limiting Voltage

AGC & SYNC

AGC Feedforward Current
AGC Threshold (Sync Tip at Pin 28)

4.7

-

5.1

Vdc

V7

-

4.2

-

Vdc

17

-

5.0

-

mA

V28

Sync Separator Operating Point
Sync Separator Charge Current

Figure 2. Monomax AGC Characteristics

o
iil
B

~

"-

-to

z

to

=>

'"w~

-20

I
(Pin 9)

\.
\

-30
-40

-so

",'

.~

.... '

-- ,.,

o

'"
1.0

'"

-~

I.....

~

4.0

z'"

c::

ci
3.0 a:

~

a:
0

2.0 "w
w

","

~

!!,

,
I'\.

"\

Q

Figure 3. Video Output Response
5.0

\.

t.O

.........
2.0
3.0
AGC VOLTAGE, PIN 8 M

4.0

B

I-'-

z

0

~
=>
zw 0
I=; -t
eo::

~ -2

--

Video Out (Pin 24) w~h Max Contrast

'""- 5 -3
w
<..>
C!)



:z -20

~

-30

Q

-40

I..........

.... ..........
....
r--..... r--....

r--.....

a:

~~

~

2.66 MHz

5:::>
0

"- -50

5w

-60

a:

-10

~

45~74 M~z =25lmVrm~

42.17 MHz = 12.5 mVrms
41.25 MHz = Relative to
45.75 MHz
I

I

, r--.... ,i"~

~~z
~

~

r---..... .....
-20
-30
-40
-50
RELATIVE 41.25 MHz INPUT LEVEL (dB)

-----------r~

Figure 5. Pin 28 Sound Output

7.0V

-

I

5.1 V 3.6 V

Back Porch

-AGCThreshold
Noise Threshold

Figure 6. Pin 24 Video Output
-

3.BV

1.7V

Max. Contrast

Min. Contrast
Back Porch

2.4V
- - -

- - - - - - -

-

Max. Blanking Level

integratng capacitor is at Pin 25 and is normally at a voltage of
3.3 V. The frequency response of the video at Pin 24 is shown
in Figure 3 and it is blanked to within 0.5 V of ground.
The AGC loop is a gated system, and for all normal
variations olthe IF input signal maintains the sync tip of a noise
filtered video signal at a reference voltage (5.1 V Pin 28). The
strobe for the AGC error amplifier is formed by gating together
the flyback pulse with the separated sync pulse. Integration of
the error signal is performed by the capacitor at Pin 8, which
forms the dominant AGC time constant. Improved noise
performance is obtained by the use of a gated AGC system,
noise protected by a DC coupled noise canceling circuit. The
false AGC lock conditions, which can result from this
combination, are prevented by an anti lockout circuit
connected to the sync separator at Pin 7. AGC lockout
conditions, which occur due to large rapid changes of signal
level are detected at Pin 7 and recovery is ensured under
these conditions by changing the AGC into a mean level
system. The voltage at Pin 10 sets the point at which tuner
AGC takeover occurs and positive going tuner control,
suitable for an NPN RF transistor, is available at Pin 11. The
maximum output is 5.5 V at 5.0 mAo A feed-forward output is
provided at Pin 9. This enables the AGC control voltage to be
AC coupled into the tuner takeover control at Pin 10. The
coupling allows additional IF gain reduction during signal
transient conditions, thus compensating for variations of AGC
loop gain at the tuner AGC takeover point. In this way the AGC
system stability and response are not degraded.
The previously mentioned noise protection is effected by
detecting negative-going noise spikes at the video detector

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
9-113

25%

Zero Carrier

•

MC13001 XP, MC13007XP
output. A DC coupled detector is used which turns on when a
noise spike exceeds the video sync tip by 1.4 V. This pulse is
then stretched and used to cancel the noise present on the
delayed video at the input to the sync separator. Cancellation
is performed by blanking the video to ground. Complete
cancellation ofthe noise spike results from the stretching ofthe
blanking pulse and the delay of the noise spike at the input to
the sync separator. Protection of both the horizontal PLL and
the AGC stems from the fact that both circuits use the noise
cancelled sync for gating.
The composite sync is stripped from a delayed and filtered
video in a peak detecting type of sync separator. The
components connected to Pin 7 determine the slice and tilt
levels of the sync separator. For ideal horizontal sync
separation and to ensure correct operating of AGC antilockup circuit, a relatively short time constant is required at
Pin 7. this time constant is less than optimum for good noise
free vertical separation, giving rise to a vertical slice level near
sync tip. An additional, longer, time-constant is therefore
coupled to the first via a diode. With the correct choice of time
constants, the diode is non conducting during the horizontal
sync period, but conducts during the longer vertical period.
This connects the longer time constant to the sync separator
for the vertical period and stops the slice level from moving up
the sync tip. The separated composite sync is integrated
internally, and the time constant is such that only the longer
period vertical pulses produce a significant output pulse. The
output is then fed to the vertical sync separator, which further
processes the vertical pulse and provides increased noise
protection. The selection of the external components
connected to the vertical separator at Pin 23 permits a wide
range of performance options. A simple resistor divider from
the 8.2 V regulated supply gives adequate performance for
most conditions. The addition of an RC network will make the
slice level adapt to varying sync amplitude and give improved
weak signal performance. A resistor to the AGC voltage on
Pin 9 enables the sync slice level to be changed as a function
of signal level. This further improves the low signal level
separation while at the same time giving increased impulse
noise protection on strong signals.

Horizontal Oscillator
The horizontal PLL (see Figure 7) is a 2-loop system using
a 31.5 kHz oscillator which after a divider stage is locked to the
sync pulse using Phase Detector 1. The control signal derived
from this phase detector on Pin 13 is fed via a high-value
resistor to the frequency-control point on Pin 12. The same
divided oscillator frequency is also fed to Phase Detector 2,
where the flyback pulse is compared with it and the resulting
error used to change a variable slice level on the oscillator
ramp waveform. This therefore changes the timing of the
output square wave from the slicer and hence the timing of the
buffered horizontal output on Pin 17 (see Figure 8). The error
on Phase Detector 2 is reduced until the phasing of the flyback
pulse is correct with respectto the divided oscillatorwaveform,
and hence with respect to the sync pulse.
Figure 8. Horizontal Waveforms

y ____--::;20:.:.0.;;;mV;J:p!l!/p_ _ _-.lrt- 4.5 V ([)
-AI

V

A~ 6.0V

V

50mVp/p

'-1'(1')
~I

J

OV

+0.9V@

OV
-0.7 V

To improve the pull-in and noise characteristics of the first
PLL, the phase detector current is increased when the vertical
lock indicator signals an unlocked condition and is decreased
when locked. This increases the loop bandwidth and pull-in
range when out of lock and decreases the loop bandwidth
when in lock, thus improving the noise performance.
In addition, the phase detector current during the vertical
period is reduced in order to minimize the disturbance to
the horizontal caused by the longer period vertical phase
detector pulses.

Figure 7. Horizontal Oscillator Systems

12

®

I
I

13

i=:l
~I
Ryback

Deflection

L _ _ _- - '

Sync

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
9-114

MC13001 XP, MC13007XP
. !he oscillator itself is a novel design using an on-chip 50 pF
silicon mtnde capacitor which has a temperature drift of only
70 ppm/oC and negligible long term drift. This, in conjunction
with an external resistor, gives a drift of horizontal frequency
of less than 1.0 Hz;oC - i.e., less than 100 Hz over the full
operating temperature range of the chip. The pull-in range of
the PLL is about±750 Hz, so normally this would eliminate the
need for any customer adjustment of the frequency.
The second significant feature of this design is the use of a
virtual ground at the frequency control point which floats at a
potential derived from a divider across the power supply and
this is the same divider which determines the end-points of the
oscillator ramp. The frequency adjustment which is necessary
to take up tolerances in the on-chip capacitor is fed in as a
current to this virtual ground and when this adjustment current
is derived from an external potentiometer across the same
supply there is no frequency variation with supply voltage.
Moreover, using the voltage from a potentiometer for the
adjustment instead of the simple variable resistor normally
used in RC oscillators make the frequency independent of the
value of the potentiometer and hence its temperature
coefficient. The frequency control current from the first
phase detector is fed into this same virtual ground and
as the sensitivity of the control is about 230 Hz/llA a high
value resistor can be used (680 kQ) and this can be
directly connected to the phase detector filter without
significant loading.
This oscillator operates with almost constant frequency
to below 4.0 V and as the total PLL system consumes
less than 4.0 mA at this voltage, this gives an ideal
start-up characteristic for receivers using deflection-derived
power supplies.

The flyback gating input is on Pin 15 which is internally
clamped to 0.7 V in both directions and requires a negative
input current of 0.6 mA to operate the gate circuit. This input
can be a raw flyback pulse simply fed via a suitable resistor.
Vertical System
An output switching signal is taken from the 31.5 kHz
oscillator to clock the vertical counter which is used in place of
a conventional vertical oscillator circuit. The counter is reset by
the vertical sync pulse but the period during which it is
permitted to reset is controlled by the window control.
Normally, when the counter is running synchronously, the
window is narrow to give some protection against spurious
noise pulses in the sync signal. If the counter output is not
'coincident with sync however, after a short period the window
opens to five reset over a much wider count range, leading to
a fast picture roll towards lock. At weak signal, i.e., less than
20011V IF input, the vertical system is forced to narrow mode
to give a steadier picture for commonly occurring types of
noise. The vertical sync, gated by the counter, then resets a
ramp gener~tor on Pin 20 and the 1.5 Vp _p ramp is
buffered to Pin 22 by the vertical preamplifier. A differential
input to the preamp on Pin 21 compares the signal generated
across the resistor in series with the deflection coils with the
generated ramp and thus controls shape and amplitude of the
coil current.
The basic block diagram of the countdown system is shown
in Figure 9. The 31.5 kHz (2FH) clock from the horizontal
oscillator drives a 10-stage counter circuit which is normally
reset by the vertical sync pulse via the sync gate, "OR" gate
and D flip-flop. This D input is also used to initiate discharge
of the ramp capacitor and hence causes picture flybacl{.

Figure 9. Monomax Vertical Countdown

f - - - - - Blanking
Pulse

Clock

Counter Reset

10 Stage Counter
514-526

"Narrow"

384-544

"Wide"

Vertical
Sync
Clock

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
9-115

MC13001 XP, MC13007XP
The period during which sync can reset the counter and
cause flyback is determined by the window control which
defines a count range during which the gate is open. One of
two ranges is selected according to the condition of the signal.
The normal "narrow" range is 514 to 526 counts for a 525 line
system and is selected after the coincidence detector
indicates that the reset is coincident, twice in succession, with
the 525 count from the counter. When the detector indicates
non-coincidence 8 times in succession, then the window
control switches to the "wide" mode (384 to 544 counts) to
achieve rapid re-synchronization. For the 625 line version the
counts are 614 to 626 for narrow mode and 484 to 644 for wide
mode. Note that the OR gate after the sync gate is used to
terminate the count at the end of the respective window if a
sync pulse has not appeared.
This method accepts non-standard signals almost in the
same way as a conventional triggered RC oscillator and has
a similar fast lock-in time. However, the use of a window control
on the counter reset ensures that when locked with a normal
standard broadcast signal the counter will reject most spurious
noise pulse.
The blanking output is provided from a latch which is set by
the counter reset pulse and terminated by count 20 from the
counter chain.

Figure 10. Vertical Waveforms

-2.SV
2.0V

®
OV

@,
-4.0 V

Power Supply
The power supply regulator, although of simple design,
provides two independent power supplies - one for the
horizontal PLL section and the other for the remainder of the
chip. The supplies share the same reference voltage but
the design of the main regulator is such that it can be switched
on independently to give minimum loading on the "bleed"
voltage source during start-up phase of a defection-derived
supply system.

Figure 11. Power Supply Circuit

Main
12 V Supply

VBl -B
RBl= 4x10-3

+ VBl

IEXT

----"v'o/v-_~.J4_-____---AoI\J\---_----+

B.2Vl0
External
Circuits

19

B.2Vto
Horizontal
System

®

__--'V'v\r-__~~---_

RS

IEXT (mA)

RS (0)

<5.0

150

20

82

35

S8

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
9-116

B.2Vto
All Monomax
Circutls Except
Horizontal

MC13001 XP, MC13007XP
Figure 12. Test Circuit Diagram

CS) o-----------~~

f--------'WIr---{) Vreg

JII
f---~---'WIr---{)

®

o-----------~~

6

Vreg

Same as Pin 2

470k

220

.------0 V21
f----e---Cr--\;V\r---{) 12V

f---._---'WIr---{) 12V

Vreg Source
f--.---O------r,::;---=O 8_2V

o

~_I-----12V
t----.----vv~_o

120V

330
17 I--::=::-------vvlr---{) 5.0V

82k

~.-.~~--~--~

C9

91k

1
f---------vvlr---{) Flyback Pulse

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

9-117

MC13001 XP, MC13007XP
Figure 13. Typical Application

Video
Out
+8.2V
+8.2V
39k

Vert
Feedback

High Voltage
Winding

+24V

+t2V

+t20V

+t20V +120V

t~

Ryback
RFB 1J}Pk
RFB=."PI< kQ

2

+8.2V
Vert
Drive
24

23

22

Vreg
21

20

VCC
18

19

15

17

MCI3001X MONOMAX
10

12

11
RF
AGC

1.0~F

680
O.lnF

1:

rn'l

t4
HOfiz
Phase
Det. 1

8.2V

RF
AGC
Delay

Video IF In

13
Horiz
Freq
680k

+8.2V

Horiz
Phase
Det.2

J

~

~.tHori:
~IiI~I
-= Frf,,= -= - -= '" -=

10nF

2% Metal Film
or Metal Oxide

+8.2V

470k

2.7M
Sync Separator Components

.--.....-'W\_-. Pin 9

r-----.,

I
I
I

1.8M

2.2k
L_-_ _

23

t Vertical Sync. optional components
for extra performance with low signal strength.

I
I
I
Tuner I
I
I
I

-=-_...l

See Application Note AN879 for further information.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
9-118

10nF

MC13017

MOTOROLA

SEMICONDUCTOR-----TECHNICAL DATA

NTSC/PAL CHROMA 10
COLOR TV and
TIMEBASE PROCESSOR

Product Preview
NTSC/PAL Chroma 10 Color TV
and Timebase Processor
The MC13017 consists of all the necessary circuits for TV NTSC/PAL decoding
and timebase processing. It forms a kit set with the MC44301 VIF and the
TDA3190 Sound IF and Power for a low cost, high performance CTV system.
• On-Chip Sync Separator
• Dual Loop Horizontal Timebase
" Direct Locked Vertical Counter
• X-Ray Protection

P SUFFIX
PLASTIC PACKAGE
CASE 711

• Noise Blanking on Sync Separator
• NTSC/PAL Color Decoding
" Direct Interface with SECAM TDA3030B
I)
I)

4.43/3.579 MHz Crystal Reference
Three DC High Impedance Control Outputs for Contrast, Brightness, and
Saturation

• 12 V Supply
Vertical Ramp Buffer Output

VCC3~VCC2

I)

• Sandcastle Output
• Hue Control

MAXIMUM RATINGS (TA = 25°C, unless otherwise noted.)
Rating
Power Supply Voltages

PIN CONNECTIONS

Symbol

Value

Unit

VCC1, VCC3
VCC2

15
10

V

Operating Temperature Range

TA

o to +70

°C

Storage Temperature Range

Tstg

-55 to +125

°C

Horizontal Output Voltage
Vertical Output Voltage

VOH
VOV

8.0

V

4.0

V.Gnd
V. Feedback
V. Out
Buffer Ramp
Ramp Cap
V. Height
Sync Sep Cap
Sync liP
LumallP
VCC1+ 12V
Hue
Chroma liP
ACC
DLE
DLC
Sat
ID
V liP
U lIP

39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21

4

10
11
12
13
14
15
16
17

18
19
20

H.Gnd
H. O/P
PD2
H. Flyback
PDl
H. Freq
X·Ray
Contrast
Brightness
Sandcastle
Pulse
RO/P
GO/P
BO/P
DC Ref&BL
Gnd
XtalFB
Xtal Drive
VCOFLT
90°'FLT

[fop View)

ORDERING INFORMATION
Device

Temperature
Range

Package

MC13017P

0° to + 70 c C

Plastic DIP

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

9-119

MC13077
PIN FUNCTION DESCRIPTION
Pin

Function

Description

+12 V supply for V CC2 power regulator.

1

VCC3

2

Vert Gnd

3

Vert Feedback

4

Vert Out

5

Buffer Ramp

6

Ramp Cap

The external cap is charged by a current controlled through vertical height control
Pin 7 to produce a vertical ramp. The discharge of the cap is controlled internally by
the vertical counter.
Current input for vertical height control.

Vertical output analog ground.
The Ramp on Pin 6 is internally inverted, level shifted and subtracted from the input
to Pin 3. The result appears as an output on an open collector at Pin 4.
Vertical ramp output to external vertical power drive.
The vertical buffer ramp output of Pin 6.

7

Vert Height

8,9

Sync Sep Cap,
Sync liP

11

VCC1

12

Hue

This is Hue control for NTSC system. It should be connected to VCC1 at PAL system.
When voltage at Pin 12 is smaller than 8.0 V, NTSC mode is selected.

15

OLE

Delay line drive open emitter terminal.

16

DLC

Delay line drive open collector terminal.

Sync separator input is a NPN transistor stage with the signal presented at its base
with a peak level of about 4.0 V. The emitter is brought out to Pin 8 through a 200 n
resistor so that a capacitor with a series resistor may be connected. The circuit
behaves as a peak detector with a slicing level controlled by the choice of charge
and discharge resistors. An additional time constant is connected through a diode to
prevent the slice level from riding up on the field sync.

+12 V supply for chroma.

An external filter cap is connected at this pin for 10 circuit.

18

10 Filter

19,20

V, U

21

90 0 Filter

22

VCO Filter

23
24

Xtal2
Xtal1

30

Sandcastle
Pulse Output

35

PD1

36

Horiz Flyback

37

PD2

38

Horiz Out

This is a saturated NPN transistor with a 2.0 kQ internal load to regulate
supply VCC2.

39

Horiz Gnd

Horizontal analog output grounding should be connected nearby the external
horizontal output stage.

40

VCC2

V, U inputs after delay line to detectors.
90 0 phase shifter filter.
Color reference VCO filter.
A 4.43 MHz (PAL), or 3.579 MHz (NTSC) crystal is connected to the internal VCO for
color subcarrier reference frequency.
The Sandcastle Pulse Output is delivered through 200 n from an emitter-follower
with 10 kn pull-down. The blanking duration is determined by the applied flyback
pulse. The burst gate determined by the second half of the flyback levels are:
Blanking (4.0 V), Burst Gate (11 V).
Horizontal phase detector current output. The PLL 1 is locked to the sync input
with 2H oscillator.
Horizontal flyback, a positive input pulse exceeded threshold of 1.0 V is required,
input impedance is between 600 and 2.0 kQ so that a minimum of 0.5 mA current
is needed to exceed the threshold voltage. The recommended peak current is
2.0 mA.
Second horizontal phase detector current output. The function of PLL 2 is to adjust
the horizontal drive in order to maintain the flyback in phase with the osciilator.

Regulated supply to horizontal timebase section. A diode is in series with 270 n
from VCC3 + 12 V to block the high voltage start-up supply of 10 mA for
horizontal oscillator.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
9-120

MOTOROLA

MC13020

SEMICONDUCTOR-----TECHNICAL DATA

MOTOROLA c-aUAM®
AM STEREO DECODER

Motorola C-QUAM®
AM Stereo Decoder

SILICON MONOLITHIC
INTEGRATED CIRCUIT

This circuit is a complete one ship, full feature AM stereo decoding and pilot
detection system. It employs full-wave envelope signal detection at all times for
the L + R signal, and decodes L - R signals only in the presence of valid stereo
transmission.

.-

• No Adjustments, No Coils
• Few Peripheral Components
• True Full-Wave Envelope Detection for L + R
• PLL Detection for L - R

1

• 25 Hz Pilot Presence Required to Receive L - R

PSUFFIX
PLASTIC PACKAGE
CASE 738

• Pilot Acquisition Time 300 ms for Strong Signals, Time Extended for
Noise Conditions to Prevent "Falsing"
• Internal Level Detector can be used as AGC Source

+8.0Vdc
.0033

1

Figure 1. Typical Application

t

r~

0.0033
1
2

IF Input

3

0-------1
0.01

OptionaI Tuner
AGCSo urce

4

,~,J too,

5

o----!
7

Au dio {
Outputs

8

I Detector

o Detector

Envelope
Detector

Phase Detector
Osc. Feedback

IF Input

Osc.lnput

Level
Detector

Ground

Error
Amplifier
VCC

-

0.0033

4~~F

19

~~D
17

51pF
16

-To.Q1

15

Stereo Lamp
Pilot Detector
Input

14

Pilot Filter
Input

13

)

10

'T'

1"0.0033

Stereo
Indicator

~
+

I

r

O~.r,

220k

Right Output

+Ir

"

0.47
56k

9

G0LED

3.3k

Left Output

lOOk
Auto Monaural

220

20

Forced
Monaural
Lock

2.21lF f

Co·Channel
Input

12

AGC'dO
Output

11

1.5k _, -±--=

4.7k
910
1.5k

10llF J+
12.21lF

430

4. 71lF

l+

'muRata Ceramic Resonator - CSA3.60MGF10l
The purchase of the Motorola C·QUAM@ AM Stereo Decoder does not carry with such purchase any license by implication, estoppel or otherwise, under
any patent rights of Motorola or others covering any combination of this decoder with other elements including use in a radio receiver. Upon application by
an interested party, licenses are available from Motorola on its patents applicable to AM Stereo radio receivers.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
9-121

MC13020
MAXIMUM RATINGS
Rating

Symbol

Value

Unit

VCC

14

Vdc

50

mAdc

Operating Temperature

TA

-40 to +85

°c

Storage Temperature

Tstg

-65 to +150

°c

TJ(max)

150

°C

Po

1.25
10

W
mW/oC

Supply Voltage
Pilot Lamp Current, Pin 15

Junction Temperature
Power Dissipation
Derate above 25°C

ELECTRICAL CHARACTERISTICS (VCC = 8.0 Vdc, TA = 25°C, Input Signal = 200 mVrms. Unmodulated carrier, circuit ot Figure I,
unless otherwise noted.)
Characteristics

Min

Typ

Max

Unit

20

30

40

mAdc

Supply Line Current Drain, Pin 6

112

200

357

mVrms

160
80

220
110

280
140

mVrms

-

-

±1.0

dB

-

-

-

%

-

0.5
1.0
1.0

Channel Separation, L only or R only, 50% Modulation

23

30

-

dB

Input Impedance

20

-

27
6.0

-

-

kQ
pF

-

100

150

Q

-

280

300

ms
sec

Input Signal Level, Unmodulated, Pin 3, tor Full Operation
Audio Output Level, 50% Modulation

L only or R only
Monaural

Channel Balance, 50% Modulation, Monaural
Output THO, 50% Modulation

Monaural
Stereo
Monaural

Output THO, 90% Modulation

-

Rin
Cin

Output Impedance
Pilot Acquisition Time
VCO locked (after release of forced monaural)
Bad Signal Condition
Lock Detector Filter Voltage, Pin 10

2.5
0.15
3.5
<0.001

3.7
1.0

Vdc
j.LA

-

-

v' (I+L+R)2 + (L-R)2 = Envelope

Average
Carrier
....- - ' L - _. .

L-R

j.tA

1.0

Pull-Up for Automatic Mode

I+L+1!..

Vdc

8.0
0.8

-

2.0

Figure

1.0

7.7

In Lock
Outot Lock

2_ Basic Quadrature AM (QUAM)

Vdc

-

Force to Monaural, Pin 9
Pull·Down for Monaural Mode

Figure

-

1.48

3_ Motorola C·QUAM@

(I+L+R)cosO I+L+R

.JJ

Envelope amplitude
is not a correct
sum signal tor
envelope detection.

-

a

~A~erage
Carrier

,

(L-R)cosO

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
9-122

Envelope is
compatible
with existing
monaural
receivers.

MC13020
Figure 4. Block Diagram
VCC

10l1F

0.01
IF Input o-l

6

2

~

Env
DEl

l+L+R
1/cos9

t

I

3

1

I

I

Phase
DEl

•
r- H I
I

J

r---

I

(1-

-- -

19

18

Cl

+0
Crysta'=

-

SeeTeld
I
and Figures I R2 C2
5,6and7 L-:

Divide
by8

VCO

I

.--

~

-- --'

0.0:

r

IL-R

II

Q

AGC
400

16

11
43Q

I
I
I
I
CSI

4.711F

_.J

t
Pilot
Decode

r-"t>
13

220k

0.47 .f
4.7k

+ 1.5k +
2.211F

Matrix

I

7
8

220
LED ,

J Switch ~ ~
b--1
9

f

51ereo
Ind icalor

Force to
Monaural

~

,-'VII\,

14
56k

L Audio
R Outputs
(Note 1)
VCC

r<>

I

loci<

0-

I

+

I

.1

D?

-,

17

I

l+L+R

90·

~

Level
DEl

Q

Optional
AGC
To Tuner

lQ

•
I

O·

r

L

IDEl

i
I
I

+

4

Error
Amp

-'

I

Var
Gain

20

5

-!.-

2.211F

+

0.0033

0.001

0.0033

0.0033

-

2.0k v 47k
12

+0.47
1.5k
+IEro;F
910

.L-

Note 1• Output polarity is defined
for receiver front end withLO
above signal frequen cy.

MOTOROLA C·QUAM® - COMPATIBLE QUADRATURE AM STEREO

o·

Introduction
In C-QUAM®, conventional quadrature amplitude
modulation has been modified by multiplying -each axis by
cos9 as shown in Figures 2 and 3. The resulting carrier
envelope is 1 + L + R, i.e., a correct sum signal for monaural
receivers and for stereo receivers operating in monaural
mode. A 25 Hz pilot signal is added to the L - R information at
a 4% modulation level.
Decoder
The MC13020P takes the output of the AM IF amplifier and
performs the complete C-QUAM® decoding function. In the
absence of a good stereo signal, it produces an undegraded
monaural output. Note in Figure 4 that the L + R information
delivered to the output always comes from the envelope
detector (Env DET).
The MC13020P decodes the stereo information by first
converting the C-QUAM® signal to QUAM, and then detecting
QUAM. The conversion is accomplished by comparing the
output of the Env DET and the I DET in the Err AMP. This
provides 1/cos9 correction factor, which is then multiplied by
the C-QUAM® incoming signal in the Var Gain block. Thus,
the output of the Var Gain block is a QUAM signal, which can
then be synchronously detected by conventional means. The

I and Q detectors are held at and 90· relative demodulation
angles by reference signals from the phase-locked,
divided-down vce. The output of the I DET is 1 + L + R, with
the added benefit (over the Env DET) of being able to produce
a negative output on strong co-channel or noise interference.
This is used to tell the Lock circuit to go to monaural operation.
The output of the Q DET is the L - R and pilot information.

veo
The vce operates at 8 times the IF input frequency, which
ensures that it is out-of-band, even when a 260 kHz IF
frequency is used. Typically, a 450 kHz IF frequency is used
with synthesized front ends. This places the vce at 3.6 MHz,
which permits economic crystal and ceramic resonators. A
crystal vce is very stable, but cannot be pulled very far to
follow front-end mis-tuning. Pull-in capability of ±100 Hz at
450 kHz is typical, and de-Q-ing wHh a resistor (see Figure 7)
can increase the range only slightly. Therefore, the crystal
approach can only be used with very accurate, stable
front-ends. By comparison, ceramic and L - e vce circuits
offer pull-in range in the order of ±2.5 kHz (at 450 kHz).
Ceramic devices accurate enough to avoid trimming
adjustment can be obtained with a matched capacitor for Cs
(see Figure 1 and 5).

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
9-123

MC13020
In the PLL filter circuit on Pin 19, Cl is the primary factor in
setting a loop corner frequency of 8.0 to 10Hz, in-lock. An
internally controlled fast pull-in is provided. R2 is selected to
slightly overdamp the control loop, and C2 prevents high
frequency instability.
The Level DET block senses carrier level and provides an
optional tuner AGC source. It also operates on the Q AGC
block to provide a constant amplitude of 25 Hz pilot at Pin 11,
and it delivers inforrnation to the pilot decoder regarding
signal strength.
Pilot and Co-Channel Filters
The Q AGC output drives a low pass filter, made up of 400 Q
internal and 430 Q and 511F external. From this point, an active
25 Hz band-pass filter is coupled to the Pilot Decoder, Pin 14,
and another low-pass filter is connected to the Co-channel
Input, Pin 12. A 2:1 reduction of 25 Hz pilot level to the Pilot
Decode circuit will cause the system to go monaural, with the
components shown. Refer to Figure 8 for the formulas
governing the active band-pass filter. The co-channel input
signal contains any low frequency intercarrier beat notes, and,
at the selected level, prevents the Pilot Decode circuit from
going into stereo. The co-channel input, Pin 12, gain can be
adjusted by changing the external 1.5 k resistor. The values
shown set the "trip" level at about 7% modulation. The 25 Hz
pilot signal at the output of the active filter is opposite in phase
to the pilot signal coming from the second low-pass filter. The
56 k resistor from Pin 14 to Pin 12 causes the pilot to be
cancelled at the co-channel input. This allows a more sensitive
setting of the co-channel trip level.

the decoder in monaural. In stereo, the co-channel input is
disabled, and co-channel or other noise is detected by
negative excursions of the I DET, as mentioned earlier. When
these excursions reach a level caused by approximately 20%
modulation of co-channel, the lock detector puts the system in
monaural, even though the PLL may still actually be locked.
This higher level of co-channel tolerance provides the
hysteresis to prevent chattering in and out of stereo on a
marginal signal.
When all inputs to the Pilot Decode block are correct, and
it has completed its count, it turns on the Switch, sending the
L - R to the Matrix, and switches the pilot lamp pin to a low
impedance to ground.
Summary
It should be noted that in C-QUAM®, with both channels AM
modulated, the noise increase in stereo is a maximum of
3.0 dB, less on program material. Therefore, this is not the
major concern in the choice of monaural to stereo switching
point as it was in FM, and blend is not needed.

PIN FUNCTION DESCRIPTION
Pin No.

Description

1,2

Detector Filters, Rout = 4.3 k, recommend 0.003311F to
VCC to filter 450 kHz components.

3

IF Signal Input

4

Level Detector filter pin, Rout = 8.2 k, 10 llF to ground
sets the AGC time constant. High impedance output,
needs buffer.

5

Error Amp compensation to stabilize the Var Gain
feedback loop

6

VCC, 6.0 to 10 Vdc, suitable for low Vbat automotive
operation, but must be protected from "high line"
condition.

Pilot Decoder
The Pilot Decoder has two modes of operation. When signal
conditions are good, the decoder will switch to stereo after 7
consecutive cycles of the 25 Hz pilot tone. When signal
conditions are bad, the detected interference changes the
pilot counter so as to require 37 consecutive cycles of pilot to
go to stereo. In a frequency synthesized radio. the logic that
mutes the audio when tuning can be connected to Pin 9. When
this pin is held low it holds the decoder in monaural mode and
switches it to the short count. This pin should be held low until
the synthesizer and decoder have both locked onto a new
station. A 300 ms delay should be sufficient. If the synthesizer
logic does not provide sufficient delay, the circuit shown in
Figure 9 may be added. Once Pin 9 goes high, the Pilot
Decoder starts counting. If no pilot is detected for seven
consecutive counts, it is assumed to be a good monaural
station and the decoder is switched to the long count. This
reduces the possibility of false stereo triggering due to signal
level fluctuation or noise. If the PLL goes out of lock, or
interference is detected by the co-channel protection circuit
before seven cycles are counted, the decoder goes into the
long count mode. Each disturbance will reset the counter to
zero. The Level Detector will keep the decoder from going into
stereo if the IF input level drops 10 dB, but will not change the
operation of the pilot counter.
Once the decoder has gone into the stereo mode, it will go
instantly back to monaural if either the lock detector on Pin 10
goes low, or if the carrier level drops below the present
threshold. Seven consecutive counts of no pilot will also put

7,8

Left and Right Outputs, NPN emitter-followers

9

Forced Monaural, MOS or TTL controllable

10

Lock detector filter, Rout = 27 k, recommend 2.2 llF
to ground

11

AGC'd Q output, NPN emitter-follower with 400 n from
emitter to Pin 11

12

Co-channel input, 2.0 k series in and 47 k feedback

13

Pilot Filter input to op amp, see Figure 8.

14

Pilot Decode Input (op amp output) emitter-follower,
Rout = 100 n

15

Stereo Lamp, open-collector of an NPN common emitter
stage, can sink 50 rnA, Vsat = 0.3 V at 5.0 rnA.

16

Ground

17

Oscillator input, Rin = 10k, do not DC connect to Pin 18
or ground.

18

Oscillator feedback, NPN emitter, Rout = 100 n

19

Phase Detector output, current source to filter.

20

Detector Filter, Rout = 4.3 k, recommend 0.0033 llF to
VCC to filter 450 kHz.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

9-124

MC13020
Figure 6. L-C VCO

Figure 5. Ceramic VCO
5.5

2:

-120

~

2:
w

:z 5.0

4.5

c::

(!)

!:3
~
~

!:3

~flt?~

4.5 560

0.0033 30

447

448

452
449
450
451
VCO -;- 8 FREQUENCY (kHz)

./

~

./

0

§; 3.5

I
446

454

453

1120

18

17,

/

:J;
rr .6.
~
MHz

5.0

:z

19

W
(!) 4.5

;:!i
:...J
0

> 4.0
I-

S

~

:::>

a.
~

448 449 450 451 452
VCO -;- 8 FREQUENCY (kHz)

453

454

nLO~~~___~~90 MCI3020
Bus

./

/
",...

./."

III

/

3.5
3.0

0.111f
1.2k
24T

447

I

/'

2.211F

c::

/

Figure 8. Forced Monaural
Optional Delay Circuit

Figure 7. Crystal VCO
5.5

/

/'

a. 4.0

3.0

0

22

:::>

3.51--Y"----,,j£-+-l--+--+--+---+----1

§;

I
f

I-

c::

~

I
I

17

~

4.0

:z

2:

18

100

W

(!)

19

I
449.90

I

449.95
450.00
450.05
VCO -;- 8 FREQUENCY (kHz)

450.10

Figure 9. Active Bandpass Filter
R -~
c-ltfOC
Rc
Ra=2Ao
RaRc
Rb = 4Q2Ra-Rc

C±5%

Ra±5%

Rb±1%

Rc ±1%

0.47J.lF

4.7k

910

220 k

0.33J.lF

8.2 k

1.3 k

330 k

Note: Capacitor C should be a good grade. low ESA.

Where in this application: fa = center frequency = 25 Hz
Ao = gain at fa S 25
Qsl0
Choose values for fa.

Ao. Q. and conveinent C. solve for resistors.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
9-125

MOTOROLA

MC13022

SEMICONDUCTOR-----TECHNICAL DATA

Advance Information
Advanced, Medium Voltage AM
Stereo Decoder
The MC13022 is designed for home, portable, and automotive AM stereo
radio applications. The circuits and functions included in the design allow
implementation of a full-featured C-QUAM® AM stereo radio with relatively few,
inexpensive external parts. It is available in either 28-lead DIP or EIAJ
compatible wide-bodied 28-lead SOIC.
o Operation from 4.0 V to 10 V Supply with Current Drain of 18 mA Typ
• IF Amplifier with Two Speed AGC
• Post Detection Filters with 10kHz Notch that Allow User or Automatic
Adjustable Audio Bandwidth Control
• Signal Quality Controlled Stereo Blend and Noise Reduction

C-QUAM®
ADVANCED, MEDIUM VOLTAGE
AM STEREO DECODER
SILICON MONOLITHIC
INTEGRATED CIRCUIT

~PSU'AX

PLASTIC PACKAGE
CASE 710

• Noise and Co-Channel Discriminating Stop-an-Station
• Signal Strength Indicator Output for RF AGC and/or Meter Drive
• Signal Strength Controlled IF Bandwidth
• Noise Immune Pilot Detector Needs no Precision Filter Components
• MC13023 Complementary Tuning System IC

OW SUFFIX
PLASTIC PACKAGE
CASE 751F
(SO-28L)

Figure 1. Basic Elements of the System

450 kHz
Low-Level

Left Audio
Right Audio

IF

Pilot Lamp

Stop-Sensei
RF AGCIMeter Drive
Fast AGC Control

The purchase of the Motorola C-QUAM® AM Stereo Decoder does not carry with such purchase any license by implication, estoppel or otherwise, under
any patent rights of Motorola or others covering any combination of this decoder with other elements including use in a radio receiver. Upon application by
an inlerested party, licenses are available from Motorola on its patents applicable to AM Stereo radio receivers.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

9-126

MC13022
MAXIMUM RATINGS
Rating

Symbol

Value

VCC

12

Vdc

30

mAdc
DC

Supply Voltage
Stereo Indicator lamp Current, Pin 21

Unit

Operating Temperature

TA

-40 to +65

Storage Temperature

Tstg

-65 to +150

°c

Junction Temperature

TJ(max)

150

°c

Power Dissipation
Derate above 25°C

Po

1.25
10

W
mW/oC

ELECTRICAL CHARACTERISTICS (VCC = 6.0 V, TA = 25DC)
Min

Typ

Max

Power Supply Operating Range

4.0

6.0

10

Vdc

Supply line Current Drain, Pin 25

11

16

22

mAdc

Characteristics

Minimum Input Signal level, Unmodulated, Pin 5, for Full Operation
Audio Output level, 50% Modulation, l only or R only

Stereo

Unit

-

5.0

-

mVrms

100

140

160

mVrms

Audio Output level, 50% Modulation

Monaural

50

70

90

mVrms

Output THO, 50% Modulation

Monaural
Stereo

-

0.3
0.5

0.5
2.0

%

22

35

-

dB

-

-

600

ms

300

-

Stereo Indicator lamp Pin
Saturation Voltage at 3.0 rnA load Current - Vsat Pin 21

-

-

200

mVdc

Stereo Indicator lamp Pin
leakage Current Pin 21

-

-

1.0

!lAdc

Channel Separation, l only or R only, 50% Modulation

Stereo

Pilot Acquisition Time Following BLEND Reset to 0.3 Vdc
Audio Output Impedance at 1.0 kHz, Pin 7, 14

(1

(See Figure 3)

Notch Filter Control Pin 15
Response versus Voltage

EXPLANATION OF FEATURES
Blend and Noise Reduction
Although AM stereo does not have the extreme difference
in SIN between mono and stereo that FM does (typically less
than 3.0 dB versus greater than 20 dB for FM), sudden
switching between mono and stereo is quite apparent. Some
forms of interference such as co-channel have a large L - R
component that makes them more annoying than would
ordinarily be expected for the measured level. The MC13022
measures the interference level and reduces L - R as
interference increases, blending smoothly to mono. The pilot
indicator remains on as long as a pilot signal is detected,
even when interference is severe, to minimize annoying pilot
light flickering.
RF AGC/Meter Drive
A DC voltage proportional to be log of signal strength is
provided at Pin 6. This can be used for RF AGe, signal
strength indication, and/or control of the post detection filter.
Normal operation is above 2.2 V as shown is Figure 4.
Stop Sense
Multiplexed with the signal strength information is the
stop sense signal. The stop sense is activated when scanning
by externally pulling the blend capacitor on Pin 23 below
0.5 V. This would typically be done from the mute line in a
frequency synthesizer.
If at any time Pin 23 is low and there is either no signal in the
IF or a noisy signal of a predetermined interference level,

Pin 6 will go low. This low can be used to tell the frequency
synthesizer to immediately scan to the next channel. The
interference detection prevents stopping on many
un listenable stations, a feature particularly useful at night
when many frequencies may have strong signals from
multiple co-channel stations.
IF Bandwidth Control
IF AGC attenuates the signal by shunting the signal at
the IF input. This widens the IF bandwidth by decreasing
the loaded Q of the input coupling coil as signal
strength increases.
Post Detection Filtering
With weak, noisy signals, high frequency rolloff greatly
improves the sound. Conventional tone controls do not
attenuate the highs sufficiently to control noise without also
significantly affecting the mid-range. Also, notch filters are
necessary with any wide-band AM radio to eliminate the
10 kHz whistle from adjacent stations.
By using a twin-Tfilterwith variable feedback to the normally
grounded center leg, a variable Q notch filter is formed that
provides both the 10kHz notch and variable high frequency
rolloff functions. Typical range of response is shown in
Figure 3. Response is controlled by the DC voltage on Pin 15.
Pin 15 could interface with a DC operated tone control such
as the TDA 1524, or could be tied to Pin 6 for automatic audio
bandwidth control as a function of signal strength.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

9-127

MC13022
Figure 2. Test Circuit

Vee
2.2k

2.2k

0.001;:

rl·

0.001

OOl
,~

l
~

IDel

l-R
De1

Q
OUl

28

27

26

~~711F

201lF

+
Loop +
Blend
FiR
24
23

VCC
25

LED

*"

"~

r1af-+~:

Gnd

Stereo
Lamp

Osc
Fbk

Osc
In

22

21

20

19

'-

-

2
Decoder

1npU11~

4
AGC

5

.., 101lF +

I
I
1T2-1r
[.2 _ _ _

I..,.

7

6

9

1

i-

-~ t

....

I

1.5

I

I

2.0

3.0

12

13

14

r1

740
T.43k

43k

21.5k

370

"

370

FiRered
Rih1
O:WPul

370

Tl -Ceramic Resonalor muRa1a
CSA 3.60 MGFl 01
T2 - Broad Resonance @ 450 kHz
Effec1ive Rp of 8.0 K 10 12 K
(Part No. 10 be De1ermined)

RF AGC,

Figure 4. RF AGC/Slgnal Strength Output
versus Input Signal

I

Signal
5
InpU1 ~tl
'1ok1.01

.., 5.0

....

R: !'....'"

Response at
Pins 10 and 11 Due
to IF Selectivity
Total Response at
Output Pins 7 and 14

[l O~

~fo

Figure 3. Overall Selectivity of a Typical Receiver
versus Filter Control Voltage

-

_I

[2J-rkJ

11
R
Oul

43k

SSMe1er

10
VAT Pin 15 = 3.5 VdC::>'"'
w
-20
U)
I
2.5Vdc""""/ IA"
is
-30
II..
1.5Vdc
1

10

21.5k

Filtered
I.ef1
OU1pul

..,. S1opSense,

1-60
0-70
-60

15

I

740

43k

,,1

~.

Filter
Ccn1rol

lOOk
0.01

..I

Ma1rix

-I

8

0 01
10k.

IF
InpU1

101lF l

.1

c<}{5j

""'--

3
Ref

+

ffi-40
~ -50

16!

Pilo1
De1ec1or

RFAGC

~/AGC ...

...J

J

17!

I

Envelope l +R

Z:'

3.rN

o

18

Pilo1
Q

Gain-Con1rolled l-R

IFOUl

0.001 ~

:j 0'4~ !

VCO

Decoder

1
Env
De1

ll.0l1F

10l1
Pilol
I

PilolDe1
InpUl

J

Signal
Quali1y
De1ec1or

+

*0.22

~
CD
z

'" ,
I" ",.......
.c::;:.:'\

1"\

m

~

::!i

g
<

Ltjt:!]

L_:.J

6

./

3.0

I

RF AGC
lOOk:E SS Me1er
..,. 0.01

1'1-'

,,/

Zo =12k

li: 4.0

,~

23

1- . to.

~

~

I I
4.0 5.0 6.0 8.0 10
15
AUDIO FREQUENCY (kHz)

20

2.0

30

~

1.0

i--'"
3.0

10
30
100 300
SIGNALINPUT, 10k n TO PIN 5 (mVrms)

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
9-128

tOk

MC13022
Figure 5. High Performance Home Type AM Stereo Receiver

Vcc

TOKO Part No. MF292BC·1349Z

27

~~~

26

O~

25

VCC

Pilo1
MC13022
L.eftNotch
In
FBK
8
9

Unfiltered

Loul
10

Roul
11

FBK Rightl~otch Out
12
13
14

r

To
Signal
Strength
Meter

See
MC13023
Da1a Sheet
for
Alternate
Approach

I
I
I
I
IL

YI---+--l
_ _ _ _ _ _ _ _ _ _ _ _ ...l
TOKO Part No. THB·l22

Tuning Uno
From Synthesizer

~II

8-/1

.9.,.

.

L ____

.,.
~~

_

_ ._

_______

_ __

1
I
1
I

. - . 1

~~~_~

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

9-129

MOTOROLA

MC13024

SEMICONDUCTOR-----TECHNICAL DATA

Advance Information
Low Voltage Motorola C-QUAM®
AM Stereo Receiver

LOW VOLTAGE

MOTOROLA C-QUAM®
AM STEREO RECEIVER

The MC13024 is intended to serve the manually tuned portable and pocket
radio mass market. This part includes all receiver and stereo decoding
functions, from antenna to left and Right audio outputs.
• Full Operation from 1.8 V to 8.0 Vdc Supply
• low Power, Current Drain (typ) 5.0 rnA
• Typical Distortion <1 % at 90% l + R or 50% Single Channel
• Typical Channel Separation >25 dB
• Pilot Tone Detector
• Combined Two level Tuning and Stereo Indicator
•
•
•
•
•

SILICON MONOLITHIC
INTEGRATED CIRCUIT

~
PSUFFIX
!'lfj1nlT
III1 PLASTIC PACKAGE
1

"Blend On" Stereo Mode
High Accuracy, Fast locking VClO
Controlled Return to Monaural Under Adverse Conditions
Minimized ''Tweets and Birdies"
Minimized Tuning Transients

CASE 724

DWSUFFIX
PLASTIC PACKAGE
CASE 751E

(SO-24L)

Figure 1. Functional Block Diagram

19

r

~r-~----------------------~--~.

I
I
I
.I +--'v-'v-lt--.....

I
I
~
I
_Filters
________ I
IL _ _ _ _ _ _Pilot
~

The purchase of the Motorola C-QUAM® AM Stereo Decoder does not carry with such purchase any license by implication, estoppel or otherwise, under
any patent rights of Motorola or others covering any combination of this decoder with other elements including use in a radio receiver. Upon application by
an interested party, licenses are available from Motorola on its patents applicable to AM Stereo radio receivers.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
9-130

MC13024
MAXIMUM RATINGS
Rating
Supply Voltage
Operating Temperature
Storage Temperature

Symbol

Value

Unit

VCC

12

Vdc

TA

oto +70

°c

Tstg

-65 to +150

°C

ELECTRICAL CHARACTERISTICS (VCC = 2.2 Vdc, TA = 25°C, TA = Input RF signal = 40 dBIlV at 1.0 MHz directly fed to the receiver,
Modulating signal = 1.0 kHz sine wave at 30% modulation, unless otherwise noted.)
Min

Typ

Max

Unit

Power Supply Voltage

Characteristics

-

1.8 to 8.0

-

Vdc

Supply Current, Excluding Current LEDs
No Signal
Monaural
Stereo

4.0
5.0
5.0

5.4
6.0
6.0

6.5
6.8
6.8

LED Driving Current
Monaural
Stereo

0.8
2.5

1.2
4.0

Sensitivity, Monaural
Maximum
20dBS/N

-

5.0
8.0

-

30
28

38
34

-

-

dB

17
17

25
25

-

dB

rnA

SIN Ratio
Channel Separation

Monaural
Stereo
LtoR
Rto L

Recovered Audio (L or R)

9.0

Stereo Channel Balance

-

Distortion

Monaural
Stereo

-

1.8
5.5

rnA

IlV

13

16

mVrms

--32

-

dB

0.9
1.1

1.3
2.5

%

NOTE: 1. A 200 Hz high-pass filter IS reqUired at the recovered audio output to filter out the reSidual 25 Hz pilot frequency.

GENERAL DESCRIPTION
The MC 13024 is a complete C-QUAM® AM stereo receiver,
from the antenna to low level audio. All that is needed to make
a complete AM stereo radio is the addition of the appropriate
audio output amplifier. The MC13024 is intended for use in
most types of manually tuned receivers: pocket portables,
"boom boxes", table radios, etc. It will operate from 1.8 Vdc to
8.0 Vdc and requires typically 5.0 mA (not including LED). This
broad supply voltage tolerance and low power consumption
makes it ideal for portables using as few as 2 battery cells.
The radios which can be built using this part can be quite
low in cost, while still benefiting from a high degree of
functional sophistication.

Features
The MC13024 contains a wide dynamic range mixer, IF,
AGC, AFC, C-QUAM® decoder, stereo pilotlone detector, and
a signal quality detector. The stereo decoding and pilot
detection are similar to the well-established MC13020, except
for reduced peripheral components, and the phase-locked
loop used forthe L-R detection now is looped around the entire
receiver. In other words, the PLL controls the tuner local
oscillator (VCLO) rather than a detector loop after the IF. The
advantage of this, in manually tuned AM stereo, is significant,
because it assures that the signal will always be properly
centered in the IF bandpass, which is critical to good channel
separation. this architecture also gives the radio an AFC
tuning behavior which makes it easy to tune. The PLL has two
speeds, provided by current ratios of 50:1, which give fast lock
and low distortion, respectively.
A signal quality detector circuit monitors lock condition,
excess in-phase modulation due to interference, pilot
presence and amplitude, and the movement of the tuning

element by the user. A proper level of pilot must be present for
several cycles before stereo mode will be enabled. When all
conditions are correct, the transition from monaural to stereo
is done gradually to prevent a transient "pop." Under aberrated
conditions, the audio may either blend to mono or make an
immediate change to mono, depending on the detected
condition. The LED pin drives a dual purpose indicator: low
current for PLL lock, and full current for stereo mode. Again,
the switching is done "softly" to prevent transient loading of a
weak battery.
The IF gain and the mixer RF gain are each reduced, in turn,
as signal strength increases, to optimize SIN and prevent
overload. The receiver is capable of 20 dB SIN at
2.5!iV/50 Q input. At weak signals, the reference oscillator
and quadrature divider are shut off to minimize '1weets
and birdies."

Radio Construction
Layout is not much more critical than any high performance
AM receiver. Care must be taken to provide a good ground
plane and short leads on Signal paths. Take special care to
keep the reference oscillator components close to Pin 22 and
protected from coupling from the pilot bandpass output,
Pin 24. Also take care with the ever present threat of RF
radiation from the audio output back into the antenna. This can
be controlled by proper component location and good (close)
RF bypass on the amplifier VCC and good snubbers on the
audio outputs. Keeping in mind that this is a phase-detecting
receiver, it is important to mount coils securely and avoid
movable wires in tuned circuits. A lot of individual preference
will go into each implementation; the components shown here
are only intended to provide a good working start.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
9-131

Figure 2. MC13024 Test Circuit Schematic

Pin 15

Pin 15

50

1.0k
5.1k

0.1~

---I

TP1 0

s::

0
0
::D
0
r
»
r

-l

Ground

-"I;f

,

Vee=2.2V ...

200k

m

If---<

Out

~~~ - . . . . - - - - - -

Pilolln

.~

L"ut

Vee=2.2V

Lowpass

Out

~

~

0.1!!

Bandpass ~

LED

»

I\J

SW1b

LED

Z

w

Bandpass
In

SW1a

470k

Z

Lowpass
In

-l

s:
o

Rout

...a.

m

W

::D

~

o

Vee

N
oI::to

0

m

10

0en

Fitter

T

CJ

m

<
0

m
CJ

~

»

Pll

22!!
100k

0.01!!

~~Di'L-I

Pilol
Oul

i6ll....---iIT08

veLD

--+-+------f

-

-=-

Mixer
Part Numbers for Tuning Componenls:

Out

2.7k

-=•

Tanlalum Capacilor

T1 -Inpul Transformer
T2 - Local Oscillalor
T3 - Mixer Oulpul
T4-IF Inpul (Ceramic)
T5-IFOulpul
T6 - Reference Oscilialor

A7BRS-1 0952X-TOKO
A7BRS-T1342AIX-TOKO
7MCS-T1464X-TOKO
ALFC-450El
ACMF-450STI
NTK RLF-B 12-450
7MCS-T1463BS-TOKO
MF291 ACS-3688VL-TOKO

Figure 3. Application Circuit, Manually Tuned Headphone Radio

+

22~F~

Two "AA/(
Batteries
or Larger

O.33~

~

s:

~

0
--I
0
::D
0
r
»
r

pj

'"'
Tuning &stereol
Indicator
•

Z

In t

11
~I I

NFt

LED

is:

m

»

o......

~

'P
~

(..)
(..)

Z

In 2

--I

m

::D

NF 2

)!;!
()
m

0C/l
m

o

tOO~

22~

0

m

<
0

CN

2.m
Out 21 6 i-----+-"-I {-'

tOOk
loop
Antenna

0

~

»

Part Numbers for Tuning Components:
T1
T2
T3
T4

Input Transformer
Local Oscillator
Mixer Output
IF Input (Ceramic)

T5
T6

IF Output
Reference Oscillator

A7BRS-10952X-TOKO
A7BRS-T1342AIX-TOKO
7MCS-T1464X-TOKO
AlFC-450E!
ACMF-450STI
NTK RlF-B12-450
7MCS-T1463BS-TOKO
MF291 ACS-3688VL-TOKO

C1

Tuning Capacitor

HU22124-NOOO-O

I\)

.I:a

MOTOROLA

MC13025

SEMICONDUCTOR-----TECHNICAL DATA

ETR® FRONT END for
C-QUAM® AM STEREO

Product Preview
Electronically Tuned Radio
Front End

SILICON MONOLITHIC
INTEGRATED CIRCUIT

The MC13025 is the complementary ETR® Electronically Tuned Radio
front-end for the second generation MC13022 C-QUAM® AM stereo
IF/decoder. The MC13025 provides a high dynarnic range mixer, voltage
controlled oscillator, and first IF that with the MC13022 and synthesizer form a
complete digitally controlled AM stereo tuner system. This system in turn may
drive a dual channel audio processor and high power amplifiers for car radio or
home stereo applications. Other applications include portable radio "boom
boxes", table radios and component stereo systems. The MC13025 is
designed to be a simple upgrade or replacement for the older MC13023 Front
EndlTuner in ETR applications.
• Replaces the MC13023
• Operates Over a Wide Range of Supply Voltages: 6.0 VCC to 10 VCC
• Wideband AGC Voltage to RF Amp for Extended Dynamic Range
• Buffered VCO Output to Frequency Synthesizer
• No External RF Amp Needed for Most Home Stereo and
Portable Radios
• IF Drive Output Matches the MC13022 for Optimum Performance
• VCO Operates at Four Times Local Oscillator Injection Frequency

PSUFFIX
PLASTIC PACKAGE
CASE 648

DSUFFIX
PLASTIC PACKAGE
CASE 751B
(50-16)

PIN CONNECTIONS
vee 1
Wideband 2
AGel"

ORDERING INFORMATION
Temperature
Range

Device
MC13025P

- 40° to + 85°C

MC13025D

Package
Plastic DIP
[Top View)

50-16

Simplified Block Diagram

l--

I

RFAmplifier
Varactor
Tuned
CircuH

m,---------------11-tMixer

IF Amplifier

l !I I '

rH

I
'---t--t------' I
I
'----+-----+-1
I

I

Wideband
AGC

+4

Buffer

•

~

Pin Attn.
Driver

I

I

Voltage
Controlled
Oscillator

I

I
I
I
I
I
I
I
I

L~~~~ ____ J------J

I

Frequency
Synthesizer

II-________

Varactor
Tuned
Circuit

--=====~

Right Channel

MCI3022
Variable Bandwidth IF
Amplifier wHh Notch Filter
and C-QUAM® AM
Stereo Decoder

*4

Stereo Indicator

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

9-134

Audio Out

r---Left Channel

MC13025
MAXIMUM RATINGS
Rating

Symbol

Value

Unit

VCC

4.0 to 10

Vdc

Supply Voltage
Ambient Operating Temperature

TA

-40to+85

°c

Storage Temperature

Tstg

- 65 to +150

°C

Junction Temperature

TJ

150

°C

Power Dissipation
Derate above 25°C

PD

1.25
10

W
mW/oC

ELECTRICAL CHARACTERISTICS ( 25°C, 8.0 VCC test circuit as shown in Figure 2.)
Pin

Min

Typ

Max

Unit

Supply Current

1

7.0

8.2

10

mAde

Characteristics

Regulator Current

7

-50

7.0

90

IlAdc

IF Out DC Current

8

0.9

1.05

1.2

mAde

Mixer DC Current Output

4

0.70

0.77

0.82

mAde

IF Output Amplitude, RF Input
@ 1.7 MHz, 31.6 mV

8

270

317

350

mVrms

Local Oscillator Output

10

160

181

210

mVrms

Wideband AGC Pull-Down Current

16

0.5

1.0

1.5

mAde

PNP Darlington Collector Current

13

-5.0

-4.7

-4.5

mAde

1000

2500

5000

-0.13

-0.06

PNP Darlington (DC Beta @ 5.0 mA IE)
PNP Darlington Collector Leakage

13

!lAde

Figure 1. MC13025 Test Circuit

VCC

Wideband
AGCOui
0.01

WBln

-

~
50

2.2k
j--.......__------+--------oWBOui

Wideband
AGCln

PNP
Base

1 - - - - - - - - - - + - - - - - - - - o P N P Base

Mixer In

PNP
Emit

f----------+---~r_--o

Mixer Out

PNP
Coli

f - - - - - - - - - - + - - - - i - - r - o P N P Collector

Gnd

Gnd

IFln

VCLO

~

3.0V 0 - - - -.......--j----"--'-+-1

Refl n

LO

IFOui

NC

~

(1

At 19ANS·10287RS
t

r:

2.2k

~

PNP Load
200

~4~
!

MVAMt25

-=-

PNP Emitter

I

Osc
Tune

O.t

-=LO

IFOui

LOLo~
110k 1100

MOTOROLA LlNEARIINTERFACE ICs DEVICE DATA
9-135

Figure 2. Cascode RF ETR Application
(NRSC - Notch Filters - Optional Pilot High Pass)

~-------------r-:~'~ ':~---------------r~~~-.~
+
C17
0.01

3.0V
In

LOOu1

"*

A16
4.7k

.----I

s:

Blend

@

MC13025

A21
lOOk

A14

MIxerOu114

JJ

A43
Interstation
VVV---- Mu18
lOOk

1.Bk

0

Mixer In

):
r

Z

WBAGC

I

C14

S!erao

m

»

~

~
(.0)
0)

LEDVCC

Z

-I

LED

A6

m

~

(')

~I

0

0.22

csH
J.

3.3iJF

A44
./IA

22k

l.Ok

m
('5

0 1

C7

);'1

0.01

»

J

0.1

8.2k

l.eIIAud~

Tuning
VOltage

Forca

-Stereo

Con1rDl

C9

A12
1.0k

Antenna

-'- C44
~ Ull·F

-

VCC

<

m

W
0

N
UI

JJ

~

i:

0...I.

A17

Signal Slrenglh and
Stop Sense

A40<

< A42

39k:?

:? 680

R~h1Audio

MOTOROLA

SEMICONDUCTOR------

MC13060

Mini-Watt Audio Output

MINI-WATT
AUDIO OUTPUT

TECHNICAL DATA

This device is a rugged and versatile power amplifier in a remarkable
plastic power package.
• Supply Voltages from 6.0 Vdc to 35 Vdc

SILICON MONOLITHIC
INTEGRATED CIRCUIT

• 2.0 W Output @ 70°C Ambient on PC Board with Good
Copper Ground Plane
• Self Protecting Thermal Shutdown
• Easy to Apply, Few Components
• Gain Externally Determined
• Output is Independent of Supply Voltage Over a Wide Range
DSUFFIX
PLASTIC PACKAGE
CASE 751

(SOP-S)

Figure 1. Typical Application
PIN CONNECTIONS

Vee = 6.0V to 35V
1.0jLF
Audio 0---1 + 5

Power Type
Lead Frame

Speaker

Input

16/32ll

6.8

Output

1

8

Feedback

Gnd {

2

7

}

(Top View)

Figure 2. Thermal Resistance & Maximum Power Dissipation
versus PC Board Copper

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
9-137

Gnd

MC13060
MAXIMUM RATINGS
Rating
Power Supply Voltage

Symbol

Value

VCC

35

V

1.0

Vp_p

160

°CfW

Audio Input, Pin 5
Thermal Resistance, Junction to Air

RBJA

Thermal Resistance, Junction to Case

Unit

RBJC

25

°CfW

Junction Temperature

TJ

150

°C

Operating Ambient Temperature Range

TA

-40 to +85

°C

Tstg

-65 to +150

°C

Storage Temperature Range

ELECTRICAL CHARACTERISTICS (TA = 25°C, circuit of Figure 3, unless otherwise noted.)
Characteristics

AUDIO SECTION
ICC

-

13

-

mAdc

Ao

-

50

-

VN

Distortion at 62.5 mW Output, 1.0 kHz

THD

-

0.2

1.0

Distortion at 900 mW Output, 1.0 kHz

THD

-

0.5

3.0

%

Quiescent Output Voltage, No Signal

VPin 1

B.4

-

Vdc

Rin, Pin 5

-

28

-

Vout

-

0.5

4.0

Power Supply Current, No Signal
Gain

Input Bias

VPiin5, VPin 8

Input Resistance
Output Noise (50 Hz to 15 kHz) Input 50 n

0.7

%

Vdc
kn

mVrms

GENERAL DESCRIPTION
can best be described as a voltage source with about 1.0 Ap_p
capability. On a good heatsink, it can deliver over 2.0 W at
70°C ambient.
The MC13060 will automatically go into shutdown at a die
temperature of about 150°C, effectively protecting itself, even
on fairly stiff power supplies. This eliminates the need for
decoupling the power supply, which degrades performance
and requires extra components.
Input Pins 5 and 8 are internally biased at 0.7 Vdc and
should not be driven below ground.

The MC13060 is a quasi-complementary audio power
amplifier, mounted in the SOP 8 (power SOIC package). It is
well suited to a variety of 1.0 Wand 2.0 W applications in radio,
TV, intercom, and other speaker driving tasks. It requires the
usual external components for high frequency stability and for
gain adjustment.
The output signal voltage and the power supply drain
current are very linearly related, as shown in Figure 5. Both are
quite constant over wide variation of the power supply voltage
(above minimum VCC for clipping, of course). The amplifier

Figure 3. Test Circuit

Audiolnput

1.0llF
+

~

501

5

8

l00IlF

~----~--~+~r----~-------'
6,7

3.0

16n
Load

330

::t. 0.1
6.8

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

9-138

MC13060
All Curves Taken in the Test Circuit of Figure 3, Unless Otherwise Noted.
Figure 4. Quiescent Supply Current and Output Voltage
versus Supply Voltage

Figure 5. Supply Current versus Output

20

200
Signal = 0

" " 18
~ ~ 16

--

gj ~ 14

1:3
~
Oct:
~

12

13

10

~ ~ 8.0
=>0.
~ 175 6.0
C!l

~

-

ICC

..;.;- -;?

r-

......::

./

/

180

/

"
.s

---

"0

160

f-

140

zw

a::
a::

=>

./

()

80
60

0
()

40
20

/'

2.0

o

o

10
20
30
Vee, SUPPLY VOLTAGE (Vdc)

2.0

'"

1.8

i""
o

~

1.6

B

1.2

00

4.0

~2.0
z
~ 1.8
@5 1.6 f_
1!l1.4

2.0

LO

()

1ii"
:8.

z
~

-1.0 ~

~ 0.8

-2.0 ~

:; 0.6

-3.0 ~
-4.0

~

-5.0

~ 0.2

::;;

1\

THO

J..K'

~- 0.2

II I

010

1.0k
t, FREQUENCY (Hz)

100

320 Load

V

~

z

/"

0

~

/ ' fo-

(J)

is 1.0
ct:

w

:;::

0

0.

0

0.

V

/

en

I V//
Ih V

~ io""""

20V

....-

.......

---

,..-

10k

cl

8.0

_I 16IV/161

I!

ri

~24V/160

24 V/32 0

I II

Ij

1 1 I II

-

I

--I

32 V/32 0

Ii

'I

-

~

-..

0.1

10

1.0
2.0
PO, POWER OUTPUT (W)

Figure 9. Dissipation versus Output Power

-

160 Load

y

~

-:> .'"

~

/

en
-

1!l 1.0

16V

/,

0.

III.
'ff/

o

0.

'/

j/

ct:

~

"

Vee = 24 V

/"

z
o

/;

1.0

7.0

h

0.4

2.0

1%
~/
2::....... r-- THO -

V
RL = =, Vee = 32 V

II

II

o

II

28V

...-

2.0
3.0
4.0
5.0
6.0
SINE WAVE OUTPUT VOLTAGE (Vrms)

400Hz Signal _

~ 0.8
~ 0.6

-6.0

Vee=32V -

1.0

7

.,/'

a::

Figure 8. Dissipation versus Output Power
2.0

/'

~ 1.2
~ 1.0

~ 1.0

~
~ 0.4

RL = 320
Vee = 32':,....

./

/: ~

40

3.0

.1 Jai~

.....

/

v

/

Figure 7. Distortion versus Power Output

II~e~ ~ 1JJ, k~I~I\6 hlo.~ Jvl
I I I

~ 1.4

1/

/

Figure 6. Distortion and Gain versus Frequency
_

RL = 16 0
Vee = 24 V

100 -

=>

(J)

-

120

~

0.
0.

Vo (DC)

./

15 4.0


I>
11~
11~g

Description

Expected Waveforms

Supply Voltage

+ 5.0 Vdc ±1 0%.

Composite Video output. The external
75 Q series resistor determines the
impedance of the output. The output will
drive a 75 Q load through a 75 Q coax.

1.0 Vp-p (75% Color Saturation),
1.23 Vp-p (100% Color Saturation) at
the 75 Q load.

Luminance S-Video output. The external
75 Q series resistor determines the
impedance of the output. The output will
drive a 75 Q load through a 75 Q coax.

1.0 Vp-p with sync (100% output) at the
75Qload.

Chrominance S-Video output. The
external 75 Q series resistor determines
the impedance of the output. The output
will drive a 75 Q load through a 75 Q coax.

885 mVp-p (100% output) when at the
75Qload.

Luminance Output Clamp storage
capacitor. A 0.01 !IF capacitor should be
connected from this pin to ground.

3.4 Vdc.

Luminance input from the delay line. The
delayed Luma from Pin 10 is applied at
this pin.

500 mVp-p of Composite Luma when
100% saturated RGB inputs are applied.

CompoSite Sync input. Negative going
sync should be applied at this pin. The
input has a threshold of 1.4 V.

The peak voltage may not exceed VCC.
Minimum voltage should not be less than
oV. See Figure 2 for input requirements.

Four times Subcarrier Frequency Crystal
Oscillator pin. This pin provides for the
connection of the oscillator resonant
element. Pin may also be driven directly
with a 4x subcarrier signal.

300 Vp-p to 600 Vp-p 4x subcarrier input
if the pin is being externally driven.
Approximately 40 mVp-p, if a crystal is
being used.

1-

3

Luma
S-Vldeo

Zo=75Q
7 5 Q r 75Q

1-:-

4

Chroma
S-Video

Zo=75Q
75Q
7001

J>
11~g
1-:-

5

Luma
Clamp

6

Yin

1

K
+

~
1

-

I
I

7

Sync In!
SyncSep

-=

1.4V +

.~.w

1
1
1
1 10k

~

~f

11
8

4xfsc Xtai
14xfsc In

I~;~
1400
1

-

:r:

+

-= Vref

:r:
":"

12.0k

9

3.58/
4.43 MHz
In!PLLOff

1

fF>
1 -:-

External Subcarrier Input. This pin
0.10 Vp-p to 3.0 Vp-p (AC coupled) of
provides an input to a Phase Detector and subcarrier to phase-lock 4x oscillator or
PLL and allows phase-lock of the 4x
grounded to disable the PLL. .
oscillator to an external subcarrier
reference. To disable the PLL, this pin
should be grounded. 400 Hz of pull-in and
lock-in range is possible with a crystal.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

9-144

MC13077
PIN DESCRIPTIONS
Pin
10

Internal Equivalent
Schematic

Symbol
YOut

~
I
I

11

Gnd

12

Redl n

Expected Waveforms

Description

Luminance Delay Line Drive Output. A
1.0 Vp-p with sync
delay should be inserted between this pin (100% saturated Color Bar output).
and Pin 6 to match the delay incurred by
the Chroma.

+ 1.4V

I
I

~

Ground

Ground

Red Video input.

0.7 Vp-p AC coupled (100% Color Bars).

I POk

Yv

I

ref

13

Greenln

See Pin 12

Green Video input.

0.7 Vp-p AC coupled (100% Color Bars).

14

Blueln

See Pin 12

Blue Video input.

0.7 Vp-p AC coupled (100% Color Bars).

15

B-Y
Clamp

B-Y Clamp storage capacitor. A 0.01 !IF
capacitor should be connected from this
pin to ground, unless the pin is used as
an input.

If not used as an input the pin is clamped
during sync to 2.4 Vdc. Can be used as a
B-Y input (AC coupled, 350 mVp-p, 100%
color saturation). Burst Flag, if disabled
at Pin 18, must be inserted here with the
following signal levels; -170 mV (NTSC),
-121 mV (PAL).

16

R-Y
Clamp

R-Y Clamp storage capacilor. A 0.01 !IF
capacitor should be connected from this
pin to ground, unless the pin is used as
an input.

If not used as an input the pin is clamped
during sync to 2.4 Vdc. Can be used as a
R-Y input (AC coupled, 490 mVp-p, 100%
color saturation). Burst Flag, if disabled
at Pin 18, must be inserted here with the
following signal level; + 121 mV for PAL.

17

Chroma
Out

Chroma Bandpass Drive Output.

2.8 Vp-p (100% Color Bars).

18

Burst Flag
Oul/Force
Burst Flag

K
K

H
I
IlntemaJ

Burst

I
I
19

PAL
Squarewave
Oul/Force
NTSC

,.~:~

-

Flag +

Vee

W'"

Burst Flag Output Disable and Force pin. 1.8 Vp-p burstflag pulses if unconnected.
If left unconnected, internally generated
color burst will appear at Pins 2 and 4.
Burst Flag will appear at this pin (18). If
grounded, the Burst Flag will be disabled.
If externally driven from another source of
burst flag, the internal flags will be
overriden.
PALINTSC system switch. If grounded,
the MC13077 will encode NTSC, and if
left open, PAL.

In PAL mode, a PAL squarewave appears
at this pin, the phase of which can be
reset by momentarily forcing the pin to
ground during the high state of
the squarewave.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
9-145

MC13077
PIN DESCRIPTIONS

Pin

Symbol

20

Chroma In

Internal Equivalent
Schematic

I

Description

10k

I
~

Expected Waveforms

Chroma Bandpass input. Output from
1.4 Vp-p (100% Color Bars) with
chroma bandpass filter should be applied bandpass filter and 1.0 k.Q matching
at this pin.
resistors.

2.0V +

Composite Sync Input
Other than the component video inputs to be encoded,
only Composite Sync is required for encoding the
components into a composite signal compatible with either
the NTSC or PAL standard. The Composite Sync input is
used internally for determining which standard to encode to,
for driving the black level clamps, and to set the timing of the
composite sync in the outputs.
The Composite Sync/Sync Separator input was designed
to accept AC or DC coupled inputs making it possible to drive
the sync input from a variety of sources. An interesting note is
that composite video can also be used for sync input. The
threshold of the sync input is 1.4 Vdc. Figure 2 shows the
requirements for sync input.
Figure 2. Sync Input Amplitude Requirements

n

Baseline Voltage

Sync Tip

i

Luma and Color Difference Clamps
Clamping for the MC13077 occurs once every horizontal
line during sync. The absence of color creates a color
difference component voltage of zero, this null is used to
generate a reference voltage for black in the video outputs.
The clamp capacitors at Pins 5, 15 and 16 are used to store
the reference voltage during the line period.
RGB Inputs
To encode RGB, the component video inputs (Pins 12,
13, 14) are applied to the Luma (Y) and color difference
(R-Y, B-Y) matrix. The color difference signals are
then conditioned by Sallen-key low pass filters (f-3 dB =
4.0 MHz). The inputs are designed so that 700 mVp-p RGB
provides 100% color saturation.
The first color difference component (R-Y) is created by
matrixing the RGB components with the following weights:

Vee

R-Y = 0.70R - 0.59G -O.IIB

, s y n c Input

B-Y = 0.89R - 0.59G - 0.30B

VOltag~- tj - - - I.4V
__
L -_ _ _ _ _ Gnd

Both serrated and block vertical sync can be used for
NTSC applications. PAL applications require a serrated
vertical sync. The serrations at the horizontal rate trigger the
PAL flip-flop to generate the swinging burst.
Even though the sync input olthe MC13077 is well suited
for TTL interface, some functions of the IC are susceptible to
the high energy present in such signals and may be
disturbed. This disturbance may take the form of a noise
spike in the video outputs and/or a disturbance of the 4x
oscillator resulting in an incorrect encoding of the chroma
information. Therefore, it is recommended that if TTL or other
fast-edged inputs are going to be used for the sync input,
then either the amplitude and/or the edge speed of the sync
input pulse should be reduced. 300 mVp-p of sync without a
reduction of edge speed has to be shown to produce
disturbance free operation. Also, a sync input of 4.0 Vp·p and
edge rates of 225 ns have been shown to produce similar
results. Figure 3 shows a recommended coupling circuit for
TTL type composite sync.
Figure 3. TTL Sync Input Circuit

1

5.1k

0.1J.L

71

nLSynC_~f----C1
240

1

1

(1)

The second color difference signal (B-Y) is created in a
similar fashion by the equation:
(2)

These two components then receive burst flag before being
modulated by the color subcarrierto create composite chroma.
The luma is also the result of a weighted matrixing of the
RGB components. The components and corresponding
weights are:
Y = 0.30R + 0.59G + O.IIB

(3)

Composite sync is then added to the result of Equation 3 to
create composite luma.
The luma information thus created must be eventually
recombined with the chroma information. However, since the
chroma information created by Equations 1 and 2 is filtered
internally before being modulated then bandlimited
externally, the resultant encoded chroma experiences a
group delay that is the sum of the delay imposed by the
internal and external filtering. So, the composite luma is
output at Pin 10 so that an external delay can be inserted in
the path to match the delay incurred by the composite
chroma. The delayed composite luma is then input back into
the MC13077 at Pin 6.
Color Difference Inputs
If the MC13077 is intended to encode color difference
signals (YUV or Y, R-Y, B-Y), it becomes necessary to bypass
the color difference and luma matrix circuitry. This can be
accomplished by inputing directly to the color modulators the
color difference signals. 491 mVp-p and 349 mVp-p should
be input to the R-Y and B-Y Clamp pins (Pin 16 and Pin 15)
respectively, to achieve 100% color saturation in the
composite video output. The luma information can be input in

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

9-146

MC13077
two ways. The luma can be input directly into the RGB inputs
(700 mVp-p without sync), or through the delay line (1.0 Vp-p
with sync, sync tip-to-peak white) in which case the RGB
inputs should be cap-coupled to ground. In either case,
composite sync still needs to be input to the MC13077 at Pin 7
(see Figures 11,12 and 13).

If the R-Yand B-Y inputs also have burst flag, it can also
be input along with the color difference signals at these pins.
Of course, now since the color difference modulator
pre-filtering is circumvented, the delay for the luma
information should be matched only to the delay of the
bandpass filter.

Figure 4. Versatility of the 4x fsc Oscillator
4xfsc

~i~tal
8
_
Oscillator Free
- 5-25pF

-=

9

MC13077

Run with Crystal

..L

-=

5-25pF
1000pF MC13077
fsc
.)
9
Subcarrier Reference
Input (Pull-in Range
of~±400 Hz)

MC13077

Oscillator Phase Lock
with Crystal to
Subcarrier Reference

MC13077

4X Subcarrier Oscillator
To encode the color difference components, an accurate
and reliable subcarrier source is required. The MC130n has
an on-chip single pin oscillator that will free-run with a 4x fsc
crystal, phase-lock to an external subcarrier reference with a
4x fsc crystal or resonator, or be driven externally from a 4x fsc
source. If the 4x fsc oscillator is going to be free run, the
subcarrier input (Pin 9) should be grounded. If the 4x fsc
oscillator is going to be phase-locked to an external
subcarrier source, the external reference should be
capacitor-coupled to Pin 9. If the 4x fsc oscillator is going to be
driven externally, Pin 8 should be driven from a network that
increases the impedance of the source at frequencies
capable of producing off-frequency oscillations. The 4x fsc
subcarrier source, thus being defined, makes it possible to
produce accurate quadrature subcarriers for the modulators.
The 4x source is internally divided by a ring counter to
produce the quadrature subcarrier signals. These signals in
turn are provided to the color difference modulators to
produce the modulated chroma. The oscillator was designed
so that if a crystal is chosen as the resonant element of the 4x
oscillator, the crystal specifications would be common.
Crystal specifications for an adequate crystal are shown in
Table 1.
Table 1. Crystal Specifications
Frequency: 14.31818 MHz (NTSC)
17.734475 MHz (PAL)
Mode: Fundamental
Frequency Tolerance (@25°C), 40 ppm
Frequency Tolerance df/dfo (0° - 70°C), 40 ppm
Load Capacitance: 20 pF
ESR: 50n
Cl(lnternal Series Capacitance), 15 mpF
..
ThiS crystal IS a common variety and IS specified as a parallel resonant.

Oscillator Phase Lock
with Resonator to
Subcarrier Reference

Burst Flag Decoding
In order to encode to either NTSC or PAL compatibility, the
MC13077 must first determine which is the intended
standard. The MC13077 accomplishes this with an internal
decode using the sync input and the output of the divide by 4
ring counter. Internally, the Sync separator circuitry provides
an output that is sampled by the subcarrier signal from the
ring counter. The result is an internal sync representative of
externally input sync but synchronized to the internal
subcarrier signal. This signal provides a reset for an internal
9-bit counter that provides divisions of the subcarrier signal
from the ring counter at powers of2 (Le. 2 1,22,23 ,... 29 = 512).
The eighth bit of the counter gives the output, fsc + 256. The
decision to provide burst gate timing for PAL or NTSC is
based upon the state of this output after one period of the
horizontal sync. Figure 5 shows the relationship between the
clock and the eighth bit of the counter.
Triggering of the burst PAL flip-flop due to equalizing
pulses is also inhibited by the decode circuitry. This is done
by counting out beyond a half line interval before generating
burst flag.
If the MC130n is encoding 525/60 component video to
NTSC and the MC13077 is generating the burst flag, the start
of burst will occur 18 counts after the leading edge of sync
has been sampled, and will continue until nine cycles of burst
have occurred. Since the reset pulse of the 9-bit counter has
a resolution of 1.0/fsc , this implies that the start of burst will
occur 5.17 ± 0.1397 I1s after the leading edge of sync and
also that the start (and end) of burst may differ by as much as
279.4 ns from line-to-line. If the MC13077 is encoding 625/50
to PAL, the subcarrier frequency will be 4.43361875 MHz and
that implies a resolution of 225.5 ns for the burst position. For
PAL encoding, 24 counts of the subcarrier are necessary
before burst is initiated. So ten cycles of subcarrier will occur
5.53 ± 0.1128 I1s after the leading edge of sync. After the
timing of the burst gate is selected, the burst gate envelope is
added to the color difference components.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
9-147

Direct Drive of
Oscillator with
4x fse Source

MC13077
Another alternative to the internal determination of burst
flag is the external input of burst flag. This allows the user to
externally define the exact timing and duration of color burst.
If external burst flag is available, it can be inserted at Pin 18.
The threshold level is nominally Vee/2 and the input should
not exceed Vee. Burst will begin when the leading edge of the
burst flag input exceeds Vee/2 and will stop when it falls
below Vee/2. If it is desired to disable the burst flag, Pin 18
can be pulled low. It is also possible to insert burst flag with
the R-Y and B-Y components. This is done at the clamp pins
with the respective color difference inputs with the internal
burst flag generation disabled (Pin 18 grounded).
Chroma Band Limiting and Luma Delay
Once the color difference and burst flag envelopes have
been modulated, the two components are internally
summed and applied to an output buffer that will drive the
external bandpass circuitry before entering the chip again at

Pin 20. The sum of the color difference modulators
produces an output that is high in harmonic content. For this
reason, and to reduce the possibility of cross color, a
chroma bandpass transformer is used to band-limit the
chroma. Suggested bandpass filters and specifications for
NTSe and PAL are shown in Figure 6a and 6b. For each of
these filters, approximately 300 ns of group delay is
experienced by the filtered chroma. There is also an internal
delay on the order of 100 ns due to internal filtering that
must be considered. Thus a 400 ns luma delay line is used
to equalize the timing of the luma and the chroma. Suitable
400 ns delay lines are the TOKO H321 LNP-1436PBAB and
the TDK DL122401D-1533. The delay of the luma channel
is inserted between Pins 10 and 6. Pin lOis the buffered
output of the luma from the RGB matrix. This output is
capable of driving the external passive delay line with no
external gain or buffering required.

Figure 6a. Group Delay and Magnitude Response of the
TOKO Bandpass Filter Intended for NTSC Applications

Figure 6b. Group Delay and Magnitude Response of the
TOKO Bandpass Filter Intended for PAL Applications

vr

I I I

iO 10

:s

z

"'6

0

~
::J
z
w

S
w
c

~

"-

::J

w

>
~
...J

0.4

1E
(!)

z

0

20

~
::J
Z

w 30

I

"...

17

~

PAL Bandpass Riter
lk

I
I

w

;:: 40
!;;:

0.2

2.0

3.0

4.0

5.0

6.0

7.0

8.0

9.0

4.~

6 4

lk

c

I
I

"-

::J

0

0.4 a:

(!)

w
a: 50
60

1.0

"'6
S
w

I

1 3

=

...J

w
a:

I

I"l"'..

Y I I"l. I
HH-+-;/--TOKO H286BAIS'4963D~""'........++-+-H
Attenuation

v

T\
I
J I\.. Group Delay

/

0.2

t!:::tlI--""2tt1~t111=rl:::E±:±~u

o

1.0

2.0

FREQUENCY (MHz)

3.0

4.0

5.0

6.0

7.0

8.0

9.0

FREQUENCY (MHz)

Characteristics of TOKO Bandpass Filter
(H286BAIS - 4963DAD)

Characteristics of TOKO Bandpass Filter
(H286BAIS - 6276DAD)
Frequency (MHz)

Attenuation (dB)

Group Delay (IlS)

Frequency (MHz)

Attenuation (dB)

Group Delay (IlS)

2.0

8.0 (min)

0.12

2.50

10 (min)

0.075

2.8

3.0 ± 3.0

0.25

3.73

3.0 ± 3.0

0.24

3.58

Ins. Loss 3.5 (max)

0.290 ± 0.030

4.43

Ins Loss 2.0 (max)

0.295 ± 0.035

4.3

3.0 ± 3.0

0.24

5.13

3.0 ± 3.0

0.24

6.2

15 (min)

0.05

6.50

12 (min)

0.05

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
9-148

MC13077
Chroma Encoding
Modulation of the color difference components is
performed by two double-balanced mixers that are driven
from quadrature signals provided by an internal ring counter.
The quadrature signals are derived from a ring counter that is
driven by the 4x oscillator, and which makes highly accurate
quadrature angles possible.
If PAL encoding is selected, negative burst flag envelope is
provided to both B-Y and R-Y components equally, then the
R-Y envelope phase is switched positive and negative from
line-to-line to provide the PAL alternating burst phase
characteristic. An internal flip-flop that provides the internal
fH/2 switching is enabled by opening the connection at Pin
19. If enabled, the pin will exhibit the internally generated half
line frequency squarewave. If it is desired to reverse the
sense of the PAL swinging burst, it can be done at this pin by
pulling Pin 19 low when the squarewave is high. The
component envelopes with the proper PAL burst phase are
then modulated to produce the composite chroma.
If the MC13077 is encoding to NTSC, only the B-Y color
difference component is provided a negative burst flag. This
envelope when modulated results in the characteristic -180°
phase difference between the color burst and the subcarrier
for the B-Y component. Pin 19 should be grounded for NTSC
operation to disable the PAL flip-flop.

Video Outputs
After being filtered, the composite chroma is recombined
with the composite luma information for the Composite Video
output. The composite chroma and composite luma
components are also kept separate and buffered for the
chroma S-Video and luma S-Video outputs. The video
outputs are provided with low impedance emitter-follower
stages and, therefore, require an external 75 n impedance
determining series resistor (see Figure 7). The outputs are
designed to drive a 75 n load through the external 75 n
series resistor.
The Composite Video output will provide 1.23 Vp-p of video
(sync tip-to-peak chroma) for 100% saturated video at the
75 n load. Luma S-Video will be 1.0 Vp-p (sync tip-to-peak
white) at the 75 n load and the Chroma S-Video output will
provide 885 mVp-p at the 75 n load.
Figure 7. Composite S-Luma and
S-Chroma Video Outputs

750

I
I
___"':.......1

750

APPLICATIONS INFORMATION
Figures 8 through 13 are application examples showing
the versatility of the MC13077.
Figure 8. Standard Encoder Application with RGB Inputs and Phase-Locked Subcarrler

MC13077

+5.0V
2

3

4

5

6

7

8

9

10

1.2k

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
9-149

MC13077
Figure 9. Encoder with RGB Inputs and Unlocked Subcarrier

1.1k
(J

as

4.7n ~

'"
u::

~

if.

¥i
'"

E

(J

20

1k

as

§

18

19

17

15

16

14

13

12

11

MC13077

+5.0V
2

4

.,

as

0

'0

:>
ci.
E

E

75 .:l
ch

75

a.
E

E
.c

e

75

(J

ch

0

10

5

as

.5

.5
u
c

as

c3

E

(Ji

.:l

17.73

jlon

(J

:f'

'5
o
as

14.32/ _

.§

1.2k

20p

1.2k

Figure 10. Encoder with RGB Inputs and 4x Subcarrier Drive

1.1k
(J

4.7n ~

'"
~

:J

"§

z

:>

if.

20

1k

'"
19

18

17

16

15

14

13

11

12

MC13077

+5.0V
3

.,
'0
0

:>

ci.
E

0
(J

4

as

E

75 .:l
ch

5

as

75

E
.c

e
~

a.
E

75

7
.5

.5

E

~

.~
.c

as

c3

u

.:l

jlon

ffi

:>

; 11.0n

1.2k

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
9-150

10

8

.5

8as
.§

1.2k

MC13077
Figure 11. Encoder with Luma and Color Difference Inputs
Using Phase-Locked Subcarrier
R·Y, B·Y Source
Impedance
<500n

MC13077

+5.0V
2

4

Q)

E

'C

:;

Q.

E

75 .3
ch

ci.
E

75

0

u

7

6

as

as

0

e

75

~

.E

~

8

as
E

0

Ii;

'lij~1.0n.3~
~

1n

.3

10

9
5

.E
u
c

jIon

1.2k

Figure 12. Encoder with Composite Luma and Color Difference Inputs
Using Phase-Locked Subcarrler
R·Y, B·Y Source
Impedance
<500n

u
4.7n ~

lk

~

i'f.
20

17

18

19

15

16

14

13

12

11

8

9

10

MC13077

+5.0V
2

3

Q)

'C

:;
ci.
E
0

u

as

E

75

~

5

4

as

0

75

E
.r:

e

u

ch

Q.

E

75 ~

7

6
.E

.E

E

~

as

.3

u

jIon

1.2k

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
9-151

1.2k Composite
Y-Input

MC13077
Figure 13. Encoder with Composite Luma and Color Difference Inputs
Using the Sync Separator and Having Phase-Locked Subcarrier
R·Y, B·Y Source
Impedance
<500Q
1.1k

'-'

'"

E

OJ>

4.7n ~

Ei:

'"

E

ct

tIl

'-'

§

~

'-'
20

'"

~

19

~

18

17

16

15

14

13

12

11

MC13077

+5.0V
3

al
'C
:>

'"E

75 .3

ci.

E

rh

4

6

7

10

'"E

75 ~

'-?
46 dB for Voice Band
• Requires Few External Components

SILICON MONOLITHIC
INTEGRATED CIRCUIT

.~
1

PSUFFIX
PLASTIC PACKAGE
CASE 626

DSUFFIX
PLASTIC PACKAGE
CASE 751
(SO-8)

MAXIMUM RATINGS
Rating
Supply Voltage
Maximum Output Current at VOl, V02
Maximum Voltage @ Vin, FC1, FC2, CD
Applied Output Voltage to VOl, V02 when disabled
Junction Temperature

Value

Unit

-1.0to+18

Vdc

±250

mA

-1.0, VCC + 1.0
-1.0, VCC + 1.0

Vdc

-55, + 140

°C

PIN CONNECTIONS

Vcc

FCl

Block Diagram and Typical Application Circuit

VOl
RI
10k

(Top View)

6 Vcc

~1

Audio '-.J

-----,

I
sl VOl

Ri
2.0k

Input / I f--'WIr-+-"O-"--t--l
Cl

1.01lFp2'
S.OIlF

I
I
I2

FC2 1

-=

Differential Gian = 2 x

Disable

7

Device
Gnd

• = Optional

ORDERING INFORMATION

Chip

SOk

I
IL. _-=_ _MC34119
___

Temperature
Range

~:

MC34119D

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

9-153

Package
Plastic DIP

MC34119P
-20° to +70°C

SO-8

MC34119
RECOMMENDED OPERATING LIMITS
Characteristics

Symbol

Min

Max

Unit

VCC
VCD

+2.0
0

+16
VCC

Vdc

Load Impedance

RL

8.0

Peak Load Current

IL

-

Supply Voltage
Voltage @ CD (Pin 1)

Differential Gain (5.0 kHz Bandwidth)
Ambient Temperature

100

Q

±200

mA

AVD

0

46

dB

TA

-20

+ 70

°c

ELECTRICAL CHARACTERISTICS (TA = 25°C, unless otherwise noted.)

I

Characteristics

Symbol

I

Min

Typ

Max

I

Unit

Amplifiers (AC Characteristics)
q

AC Input Resistance (@ Vln)
Open-Loop Gain (Amplifier # 1, f < 100 Hz)

-

AVOL1

80

Closed-Loop Gain (Amplifier # 2, VCC = 6.0 V, f = 1.0 kHz, RL = 32 Q)

AV2

-0.35

Gain Bandwidth Product

GBW

Output Power;
VCC = 3.0 V, RL = 16Q, THD" 10%
VCC = 6.0 V, RL = 32 Q, THD" 10%
VCC = 12 V, RL = 100 Q, THD" 10%

POut3
POut6
POut12

Total Harmonic Distortion (f = 1.0 kHz)
(VCC = 6.0 V, RL = 32 Q, Pout = 125 mW)
(VCC '" 3.0 V, RL = 8.0 Q, Pout = 20 mW)
(VCC'" 12 V, RL = 32 Q, Pout = 200 mW)

THD

Power Supply Rejection (VCC = 6.0 V, AVCC = 3.0 V)
(C1 =~, C2 = 0.01 IIF)
(C1 = 0.1 IIF, C2 = 0, f = 1.0 kHz)
(C1 = 1.0 IIF, C2 = 5.0 IIF, f = 1.0 kHz)

PSRR

Muting (VCC = 6.0 V, 1.0 kHz" f" 20 kHz, CD = 2.0 V)

GMT

>30

0

-

MQ

-

dB

+0.35

-

1.5

-

55
250
400

-

-

-

-

dB
MHz
mW

%
0.5
0.5
0.6

1.0

50

-

-

-

12
52

-

-

>70

1.0

-

1.15
2.65
5.65

-

VCC-1.0
0.16

-

-30

0

+30

-

-100

-200

-

dB

-

-

dB

Amplifiers (DC Characteristics)
Output DC Level@V01, V02, VCC = 3.0 V, RL = 16 Q
(Rf = 75 k)
VCC =6.0V
VCC = 12 V

VO(3)
VO(6)
VO(12)

Output Level
(lout = -75 mA, 2.0 V" VCC" 16 V)
(lout = 75 mA, 2.0 V" VCC " 16 V)

1.25

Vdc

Vdc

High
Low

VOH
VOL

Output DC Offset Voltage (V01-V02)
(VCC = 6.0 V, Rf = 75 kQ, RL = 32 Q)

AVO

Input Bias Current@ Yin (VCC = 6.0 V)

liB

Equivalent Resistance
@ FC1 (VCC = 6.0 V)
@ FC2 (VCC = 6.0 V)

-

mV
nA
kQ

RFC1
RFC2

100
18

150
25

220
40

VIL
VIH

-

-

0.8

2.0

-

-

RCD

50

90

175

kQ

ICC3
ICC16
ICCD

-

2.7
3.3
65

4.0
5.0
100

mA
mA
IIA

Chip Disable (Pin 1)
Input Voltage

Low
High

Input Resistance (VCC = VCD = 16 V)

Vdc

Power SUpJlIY
Power Supply Current
(VCC = 3.0 V, RL =~, CD = 0.8 V)
(VCC= 16 V, RL =~, CD = 0.8 V)
(VCC = 3.0 V, RL =~, CD = 2.0 V)

..

Note: Currents Into a pin are positive, currents out of a pin are negative.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
9-154

I

MC34119
PIN FUNCTION DESCRIPTION
Symbol

Pin

CD

1

Chip Disable- Digital input. A Logic "0" «0.8 V) sets normal operation. A logic "1" (2!2.0 V) sets the powerdown mode.
Input impedance is nominally 90 k.Q .

Description

FC2

2

A capacitor at this pin increases power supply rejection, and affects turn-on time. This pin can be left open if the
capacitor at FC 1 is sufficient.

FC1

3

Analog ground for the ampli!iers. A 1.0 IlF capacitor.at this pin (with a 5.0 IlF capacitor at Pin 2) provides (typically)
52 dB of power supply reJectIOn. Turn-on time ofthe CirCUit IS affected by the capacitor on this pin. This pin can be used
as an alternate input.

Yin

4

Amplifier input. The input capacitor and resistor set low frequency rolloff and input impedance. The feedback resistor
is connected to this pin and V01.
Amplifier Output #1. The DC level is ~ (VCC - 0.7 V)/2.

V01

5

VCC
GND

6

DC supply voltage (+ 2.0 V to + 16 V) is applied to this pin.

7

Ground pin for the entire circuit.

V02

8

Amplifier Output #2. This signal is equal in amplitude, but 180° out-of-phase with that at V01.
The DC level is ~ (VCC - 0.7 V)/2.

TYPICAL TEMPERATURE PERFORMANCE (-20° C< TA < + 70°C)
Function
Input Bias Current (@ Yin)
Total Harmonic Distortion
(VCC = 6.0 V, RL = 32 n. Pout = 125 mW, f = 1.0 kHz)
Power Supply Current
(VCC = 3.0 V, RL ==, CD
(VCC = 3.0 V, RL ==, CD

Typical Change

Units

+40

pA/oC

+ 0.003

%/oC
llA/oC

= 0 V)
= 2.0 V)

-2.5
-0.03

DESIGN GUIDELINES
General
The MC34119 is a low power audio amplifier capable of low
voltage operation (VCC = 2.0 V minimum) such as that
encountered in line-powered speakerphones. The circuit
provides a differential output (V01-V02) to the speaker to
maximize the available voltage swing at low voltages. The
differential gain is set by two external resistors. Pins FC1 and
FC2 allow controlling the amount of power supply and noise
rejection, as well as providing alternate inputs tothe amplifiers.
The CD pin permits powering down the IC for muting purposes
and to conserve power.
Amplifiers
Referring to the block diagram, the internal configuration
consists of two identical operational amplifiers. Amplifier #1
has an open-loop gain of ~80 dB (at f $ 100 Hz), and the
cloS~~-lo?p gain is. set by external resistor Rf and Rj. The
amplifier IS unity gain stable, and has a unity gain frequency
of approximately 1.5 MHz. In order to adequately cover the
telephone voice band (300 Hz to 3400 Hz), a maximum
closed-loop gain of 46 is recommended. Amplifier #2 is
internally set to a gain of - 1.0 (0 dB).
The outputs of both amplifiers are capable of sourcing and
sinking a peak current of 200 mAo The outputs can typically
swing to within ~0.4 V above ground, and to within ~1.3 V
below VCC, at the maximum current. See Figures 18 and 19
for VOH and VOL curves.
The output DC offset voltage (V01-V02) is primarily a
function of the feedback resistor (Rf), and secondarily due to
the amplifiers' input offset voltages. The input offset voltage of

the two amplifiers will generally be similar for a particular IC,
and therefore nearly cancel each other at the outputs.
Amplifier #1's bias current, however, flows out of Yin (Pin 4)
and through Rf, forcing V01 to shift negative by an amount
equal to [RfX IIBI. V02 is shifted positive an equal amount. The
output offset voltage, specified in the Electrical
Characteristics, is measured with the feedback resistor shown
in the Typical Application Circuit, and therefore takes into
account the bias current as well as internal offset voltages of
the amplifiers. The bias current is constant with respect to VCC.
FC1 and FC2
Power supply rejection is provided by the capacitors (C1
and C2 in the Typical Application Circuit) at FC1 and FC2. C2
is somewhat dominant at low frequencies, while C1 is
dominant at high frequencies, as shown in the graphs of
Figures 4 to 7. The required values of C1 and C2 depend on
the conditions of each application. A line powered
speakerphone, for example, will require more filtering than a
circuit powered by a well regulated power supply. The amount
of rejection is a function of the capacitors, and the equivalent
impedance looking into FC1 and FC2 (listed in the Electrical
Characteristics as RFC1 and RFC).
In addition to providing filtering, C1 and C2 also affect the
turn-on time of the circuit at power-up, since the two capacitors
must charge up through the internal 50 k and 125 k.Q resistors.
The graph of Figure 1 indicates the turn-on time upon
application of VCC of + 6.0 V. The turn-on time is ~60% longer
for VCC =3.0 V, and ~20% less for VCC =9.0 V. Turn-off time
is <10 Ils upon removal of VCC.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
9-155

MC34119
Figure 1. TUrn-On TIme versus C1, C2 at Power-On

Power Dissipation

360

Figures 8 to 10 indicate the device dissipation (within the IC)
for various combinations of VCC, RL, and load power. The
maximum power which can safely be dissipated within the
MC34119 is found from the following equation:

l.,.....--i"'"

soo

!

::;

240 I-- I- Cl =5.011/

F
:z 180

~
i=

-

V

V

l"......--

Po = (140·C - TA)/9JA

./

./

60

o
o

where TA is the ambient temperature; and 9JA is the package
thermal resistance (100·CIW for the standard DIP package,
and 180·CIW for the surface mount package.)
The power dissipated within the MC34119, in a given
application, is found from the following equation:

/
l..,...oo'"

,..."

120

l"......--

Cl = LOIlF

I

VCC switching from
OVtot6.0V

I

2.0

4.0
6.0
C2, CAPACITANCE (J1F)

8.0

Po = VCC x ICC) + (IRMS x VCC) - (RL x IRMS2)
10

where ICC is obtained from Figure 15; and IRMS is the RMS
current at the load; and RL is the load resistance.
Figures 8 to 10, along with Figures 11 to 13 (distortion
curves), and a peak working load current of ±200 mA, define
the operating range for the MC34119. The operating range is
further defined in terms of allowable load power in Figure 14
for loads of 8.0 0, 160, and 32 O. The left (ascending) portion
of each of the three curves is defined by the power level at
which 10% distortion occurs. The center flat portion of each
curve is defined by the maximum output current capability of
the MC34119. The right (descending) portion of each curve is
defined by the maximum internal power dissipation of the IC
at 25·C. At higher ambient temperatures, the maximum load
power must be reduced according to the above equations.
Operating the device beyond the current and junction
temperature limits will degrade long term reliability.

Chip Disable

The Chip Disable (Pin 1) can be used to power down the IC
to conserve power, or for muting, or both. When at a Logic "0"
(0 V to O.B V), the MC34119 is enabled for normal operation.
When Pin 1 isata Logic "1 "(2.0 VtoVCC V), the ICisdisabled.
If Pin 1 is open, that is equivalent to a Logic "0," although good
design practice dictates that an input should never be left
open. Input impedance at Pin 1 is a nominal 90 kn. The
power supply current (when disabled) is shown in Figure 15.
Muting, defined as the change in differential gain from
normal operation to muted operation, is in excess of 70 dB.
The turn-off time ofthe audio output, from the application ofthe
CO signal, is <2.0 JIS, and turn on-time is 12 ms-15 ms. Both
times are independent of C1, C2, and VCC.
When the MC34119 is disabled, the voltages at FC1 and
FC2 do not change as they are powered from VCC. The
outputs, V01 and V02, change to a high impedance condition,
removing the signal from the speaker. If signals from other
sources are to be applied to the outputs (while disabled), they
must be within the range of VCC and Ground.

Layout Considerations

Normally a snubber is not needed at the output of the
MC34119, unlike many other audio amplifiers. However, the
PC board layout, stray capacitances, and the manner In which
the speaker wires are configured, may dictate otherwise.
Generally, the speaker wires should be twisted tightly, and not
more than a few inches in length.

Figure 2. Amplifier #1 Open-Loop Gain and Phase

100
80

5'60

:!5
~

I

r--...

36
!i5'
72 ~
108 fa

Ph~el

.........

I......

Rf

IL

"
loOk

Rf = 11501k'IRli = 6.0 k

...-fJ.11l111
~ ~~f~-m~i=iok

180 ~

Gain

20

36 _

144~

......... 1"-

40

Figure 3. Differential Gain versus Frequency

o

10k
f, FREQUENCY (Hz)

O.I~

113

~

"
lOOk

Input)-!

o

100M

100

-,

VOl }

RI~VO

1.Ok
10k
f, FREQUENCY (Hz)

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

9-156

.

20k

MC34119

Figure 4. Power Supply Rejection versus Frequency
(C2 10 1lF)

Figure 5. Power Supply Rejection versus Frequency

=

EO 60

:&

:&

:z

o 50

~

f-

~

8::

8::

1

..............

a::
a:

10k

50

200

8::

iil

-

~

1
a::
a:

I

30 I- C1=O.lIlF

10

~ 0

~

,

20
_

....

:z

I I I
I I I

~

Cl =5.0IlF
I I L

:&

o 50
~ 40

a..~
::::l
en

~

30

Cl =1.0IlF

I

1

..............

a::

if
1.0k
f, FREQUENCY (Hz)

10k

20k

I I

I I I

[

10

:z

800

V

0

~

c;;

I
II

BOO

~
w

~

,,- i"""

J

400

I

c

./

J......-

--

III
oV
o

~

-

VCC =6.0V

§.

I--

c

:z

~

c;;

800

BO
90
LOAD POWER (mW)

120

,

~

400

fJ

200

f/

150

./

I /
I
'f
/I

!!2
c
w

-~

/

/

600

(>

VCC-3.0V _

Vr.r.=16V

1000

c

30

~

"
10k

20k

Figure 9. Device Dissipation

I

200

."

~

1.0k
f, FREQUENCY (Hz)

1200

VCC=12V

20k

nl

o
200

/'
./[

"'" "

Cl =O.lIlF
J J.J;

Figure 8. Device Dissipation, 8.0 n Load
1000

--

--- --

I--"'T I

I.-I-t'

20

I

200

10k

(C2=O)

Cl=O

I

1.0k
f, FREQUENCY (Hz)

Figure 7. Power Supply Rejection versus Frequency

-

10"1
VI

..............

iii' 60

Cl =1.01lF...-"

~ 40
~

<:! = 5.0 J.lF

I"--

0

20k

=

~

Cl=O

10

~
1.0k
f, FREQUENCY (Hz)

I-

-

30
20

Figure 6. Power Supply Rejection versus Frequency
(C2 1.0 1lF)
:&

Cl=O.lIlF

en

~ 0

iii' 60

-

L
_

~

::::l

10

200

=5.0 IlF)

f - !:1.0 IlF

50

~ 40

I--

w 20 f- Cl =0

~

~

-

30

a:

a::
a:

i!5

-

~01~FJ

~ 40

iil

(C2
iii' 60

f- ;1;?;1.0 IlF

/

o Vo

-

160 Load

VCC-~V _

r---

r-

-'"

~=3y

I
100

200
LOAD POWER (mW)

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
9-157

.J

VVCC=12V

300

400

MC34119
Figure 11. Distortion versus Power
Figure 10. Device Dissipation, 32 n Load
1200

!

I.
Vee=16V

-

I 1000

/

:z
Q

!fen
UJ

a

800
600

w

t)

il:ic

.......

-I'-"'"

...-

Z

o

liz

Vee=6.0V _

..,

~

Vee=3.0V

~

o

100

I

I

I

I

200
300
LOAD POWER (mW)

is 2

f2
e

400

rr

/

i!= 0 /...
o

500

I

I

I

I I

-'

I

!
!i!

9

RL=32Q

400

I

1/
/
1/

300
200

I"

100

o
o

I

I

\

I

RL=16Q

I

t

RL=8.0Q

!z
~

\

"-.....

2

4

6
8
10
12
Vee, SUPPLY VOLTAGE M

14

-

I\

I

1-.

200
300
400
POut, OUTPUT POWER (m\AJ)

----

3.0

i3
~

!t
iil

~~

....... ....
I .......
............
I

TA = 25°C-Derate at higher temperatures

"

500

RL= 00

a:

"- ........

I

Figure 15. Power Supply Current

1

1\

I

Vee = 6.0 II,
Vee = 12 V,
RL=16QUmH _ RL=32Q

\
100

4.0

\

I

~ I

RL-320"'"

\

Figure 14. Maximum Allowable Load Power

RL=32Q

II

Vee = t611,

l-

o

I Vee = 6.0 V,

I

e

i!= 0

= 12 dB)

Vee=3.0V,
RL=8.0Q

I
I
II

g2

Vee =6.011, RL = 16 Q
Vee = 1211, RL=32Q
100
200
300
400
500
POut, OUTPUT POWER (mW)

500

500

I
I

I

Z

/

V.

I

~ 6

II
V

I '1

200
300
400
POut, OUTPUT POWER (mW)

I

o
~ 4
~

/

II I

I

~

I

Vee = 3.0 II,
8 RL=16Q

f2UJ

/vee = 6.011,
RL=32Q

Vee = 1611,
RL=32Q

I I

~

I

I

ll
Vee
= 1211,
.
RL=32Q

'l./

(f = I, 3.0 kHz, AVO

_10

I

Vee = 3.011,
RL=8.0Q

f·

Figure 13. Distortion versus Power

=3.0 kHz, AVO =34 dB)
I I
I

Vee = 3.011,
RL= 16Q

I \1

100

Figure 12. Distortion versus Power
(f

I RL=32Q
I I I

I I I I I
I I Vee = 1611, Vee = 6.011,
I II RL=~2Q RL= 16Q

~
-'

i--

I Vee = 6.0 V,

Vee = 3.011,
RL=8.0Q

6

t)

:::; 4

'/

200

I
:z
Q 8 Vee = 3.011,
RL=16Q

~a

IV'

400

o

i.---"""

/
V V
1/

- -

g

Vee=12V -

V

=1.0 kHz, AVO =34 dB)

(f

10

~
16

2.0

eD=O
~

1.0
eo = Vee

o
o

J
2.0

4.0

6.0
8.0
10
12
Vee, SUPPLY VOLTAGE M

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
9-158

14

16

MC34119
Figure 16. Small Signal Response

Figure 17. Large Signal Response
rJiII

.~

~

3

I

I:

20IlS/DIV

20 Ils/DiV

Figure 18. VCC-VOH @ V01, V02 versus Load Current

Figure 19. VOL @ V01, V02 versus Load Current

1.5

1.4

1.4

~ 1.2

f-- TA = 25°C

1.3

/'

~

/'

6 1.2

/'

::r

/'

1.0

"2.0';;VCC';;16V -

r--

40

80

120

0.6

:?

0.8 / '

o

~

160

200

ILDAD, LOAD CURRENT (rnA)

Figure 20. Input Characteristics @ CD (Pin 1)

0.2

/

V
./

'-

I
40

80

120

160

....... ~

~

./
~.1 3.0k

/'

5

~ 80

o
-"

40

/"

-'"

o

/'"

/"

200

Figure 21. Audio Amplifier with High Input Impedance

.......

:;: 120

I

ILOAD, LOAD CURRENT (rnA)

75k

9

o

VCC=3.0V

I. ..-rVCC>6.0V

200

§ 160

/

/

c:, 0.4

TA=25°C -

/'

0.8

V

1.0

:::J

/'
/

0.9

e:i
~

a:

/'

~1.1

:?

VCC=2.0V -.

--'
UJ

0.1
1
Input >-I j---J

k-'"

r

Valid for VCD';; VCC
I
I
~o
M
12
16
VCD, CHIP DISABLE VDLTAGE M

':'

I

5.01lF 1

21
I
MC34119
I
L______
_ ___ .JI
7 Gnd

Differential Gain = 34 dB
Frequency Response: See Figure 3
Input Impedance = 125 kn
PSRR = 50dB

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
9-159

MC34119
Figure 22. Audio Amplifier with Bass Suppression

Figure 23. Frequency Response of Figure 22

75k

tr,. L-'(J--1~-=-~----+----'
0.05 0.05

0.1

36
10 32

s

~
;;!

~ 16

tt

5.01lF 21

r :
I

24

~

>=
z

I

Input >---l

'/

z

./

is
ci 8.0

~

50k

=

,/

MC34119

o

L _ _ _ _ _ ...1

100

1.0k
10k
f. FREQUENCY (Hz)

20k

Figure 25. Frequency Response of Figure 24

Figure 24. Audio Amplifier with Bandpass
1000pF
36

~ 32
z

~
..J

~w

24

cr 16

tt

is

g8.0
«

I
5.01lF

r

I

v
~

"

;'

o

100

2:

I

1.0k
10k
f. FREQUENCY (Hz)

50k

=

"

-.

20k

MC34119

L _ _ _ _ _ ...1

Figure 26. Split Supply Operation

At 75k
~CJ:!: ~V~ ;a.0V)

Cj Ri
0.1 3.0k

Audio Input

I

>---l ~Mr"""'''':::'''-O-:+---l

51 VOl

20k

t--,..-'W\----< Chip Disable

20k

NOTE: HVCC and VEE are not symmetrical about ground then FC1 must be
connected through a capacitor to ground as shown on lhe front page.

VEE

MOTOROLA LlNEARIINTERFACE ICs DEVICE DATA

9-160

MOTOROLA

MC44001

SEMICONDUCTOR-----TECHNICAL DATA

Chroma 4

Product Preview

VIDEO PROCESSOR

Chroma 4 Multistandard
Video Processor

SILICON MONOLITHIC
INTEGRATED CIRCUIT

'The MC44001 is a highly advanced circuit which performs most of the basic
functions required for a color TV. All of its advanced features are under processor
control via an 12C bus, enabling potentiometer controls to be removed completely.
In this way the component count may be reduced dramatically, allowing significant
cost savings together with the possibility of implementing sophisticated automatic
test routines. Using the MC44001, TV manufacturers will be able to build a
standard chassis for anywhere in the world.
• Operation from a Single + 5.0 V Supply; Typical Current Consumption
Only 120 mA
• Full PAUSECAM/NTSC capability
• Dual Composite Video or S-VHS Inputs
• All ChromaiLuma Channel Filtering, and Luma Delay Line Are Integrated
Using Sampled Data Filters Requiring No External Components
• Filters Automatically Commutate with Change of Standard
• Chroma Delay Line is Realized with a 16 Pin Companion Device, the
MC44140
• RGB Drives Incorporate Contrast and Brightness Controls and Auto Gray
Scale
• Switched RGB Inputs with Separate Saturation Control
• Auxiliary Y, R-Y, B-Y Inputs
• Line Timebase Featuring H-Phase Control, Time Constant and
Switchable Phase Detector Gain
• Vertical Timebase Incorporating Vertical Geometry Corrections
• E~W Parabola Drive Incorporating Horizontal Geometry Corrections
• Beam Current Monitor with Breathing Compensation

PSUFFIX
PLASTIC PACKAGE
CASE 711

PIN CONNECTIONS

ACC

Video lin

Video 2
12C

r

I

Iref

Clock
Data

Outputs

V-Ramp
V-Drive

Gnd
(17.7 MHz)

EWDrive

Crys(14.3 MHz) tals
SandcasUe

IAnode
D/AOutput

System Select

SECAM Cal. Loop
H·Drive

VI Output
VI Clamp

Pin

Symbol

Value

Unit

Supply Voltage

Ratings

35

Vcc

6.0

Vdc

Operating Ambient Temperature

35

TA

oto + 70

°C

Storage Temperature

-

Tstg

-65to+150

°C

Junction Temperature

-

TJ

+150

°C

Drive Output Sink Current

12

112

2.0

Applied Voltage Range:
E-WDrive
Feedback
Anode Current
All Other Pins

9

-

Va
V20
Vg
Vi

Oto+ 7.0
oto + 7.0
-2.0 to VCC
OtoVCC

Feedback

JlR~

Inputs

Fast Commutate
[Top View)

ORDERING INFORMATION
Device

Temperature
Range

Package

MC44001P

0° to + 70°C

Plastic DIP

• (Based on C26K. C32K. C63K and CSSK geometries charactenzatlons)

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
9-161

Inputs

rnA
Vdc

a
20

l::~

)v2

MAXIMUM RATINGS (TA = 25°C, unless otherwise noted.)·

MC44001
ELECTRICAL CHARACTERISTICS (VCC = 5.0 Vdc, 13 = 70 ~, TA = 25°C, unless otherwise noted.)
Pin

Min

l\'p

Max

Supply Voltage

35

4.75

5.0

5.12

V

Operating Current

35

90

120

180

rnA

Reference Current, Input Voltage

3

1.0

1.30

1.60

V

01A Output Offset
O/A Output Register Set to 00

10
-5.0

0

+5.0

O/A Output Range
O/A Output Register Varying from 00 to 63

10
100

300

500

Characteristic

NOTES: ComposHe Video Input Signal Level = 1.0 Vpp
Black-la-White = 0.7 Vpp, Syn-to-Black = 0.3 Vpp
PALJNTSC = 75% color bars; Burst = 300 mVpp
SECAM = 75% color bars

Unit

~
~

Horizontallimebase started (subaddress 00)
Vertical Breathing control set to 00; V9 = 0 V
All other analog controls set to midrange 32
Video Peaking 'Pl, P2, P3" bits high

Simplified Block Diagram
R-Y

B-Y

Y-t

Red

Green
Blue

II

~ I~~

12

r HDrive
+5.0V

H FIybeck
Pulse

+5.0V

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

9-162

MC44001
GENERAL DESCRIPTION OF THE CHROMA 4 SYSTEM
Figure 1 shows a simplified block diagram representation
of the basic system using the MC44001 and its companion
device the MC44140 chroma delay line. The Chroma 4 has
been designed to carry out all the processing of video
signals, display controls and timebase functions. There are
two video inputs which can be used for normal composite
video or separate Y and C inputs. In either case, the inputs
are interchangeable and selection is made via the 12C bus.
The video is decoded within the MC44001 which involves

separation, filtering and delay of the luminance part of the
signal, and demodulation of the chroma into color difference
signals. The luminance (called Y1) together with the
demodulated R-Y and 8-Y are all then brought out from the
IC. The color difference signals then enter the MC44140
which performs color correction in PAL and the delay line
function in SECAM. Corrected color difference signals then
re-enter the MC44001.

Figure 1. Connection to TV Chassis

H.T.

+5.0V

Compo Video {

Video 1

or
S·VHS

Video 2
Y10ut
R·YOut

H·Scan
Coils

Ext R·Y o-j

Unerarity

ExtB.Yo-j
+26V

V·Scan
Coils
V·Drive

DIA

VO/P
Stage

EHT
G1 G2 G3

R·O/P
Fast Commutate 0----+1

G·O/P
B·O/P
Feedback

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
9-163

MC44001
The next stage is called the color difference stage where a
number of control functions are carried out together with
matrixing of the components to derive RGB signals. At this
point a number of auxiliary signals may also be switched in,
again all under MCU control. External RGB (text) and Fast
Commutate enter here; also an external luminance (V2) may
be used instead of VI. External R-V and B-V are switched in
via the delay line circuit to save pins on the main device. The
V2 and External R-V, B-V will obviously be of considerable
benefit from the system point of view for use with either
feature boxes MAC or CTI.
The final stage of video processing is the RGB outputs
which drive the high voltage amplifiers connected to the
tube cathodes. These outputs are controlled by a
sophisticated digital servo-loop which is maintained and
stabilized by a sequentially sampled beam current feedback
system. Automatic gray scale control is featured as a part of
this system.
Both horizontal and vertical timebases are incorporated
into the MC44001 and control is via the 12C bus. The
horizontaltimebase employs a dual loop system of a PLL and
variable phase shifter, and the vertical uses a countdown
system. For the vertical, a field rate sawtooth is available
which is used to drive an external power amplifier with flyback
generator (usually a single IC). The line output consists of a
pulse which drives a conventional line output stage in the
normal way. The line flyback pulse is sensed and used by the
second loop for horizontal phase shift.
Where E-W correction is required, a parabola waveform is
available for this which, with the addition of a power amplifier,
can be used with a diode modulator type line output stage for
dynamic width and E-W control. The bottom of the EHT
overwinding is returned to the MC44001 and is used for
anode current monitoring and'anti-breathing correction.
A much more detailed description of each stage of the
MC44001 will be found in the next section. Information on the
delay line is to be found in this data sheet.

Introduction
The following information describes the basic operation of
the MC44001 IC together with the MC44140 chroma delay

line. The MC44001 is a highly advanced circuit which
performs all the video processing, timebase and display
functions needed for a modern color TV. The device employs
analog circuitry but with the difference that all its advanced
features are under processor control, enabling external
filtering and potentiometer adjustments to be removed
completely. Sophisticated feedback control techniques have
been used throughout the design to ensure stable operating
conditions and the absence of drift with age.
The IC described herein is one of a new generation of TV
circuits, which make use of a serial data bus to carry out
control functions. Its revolutionary design concept permits a
level of integration and degree of flexibility never achieved
before. The Chroma 4 consists of a single bipolar VLSI chip
which uses a high density, high frequency, low voltage
process called MOSAIC 1.5. Contained within this single 40
pin package is all the circuitry needed for the video signal
processing, horizontal and vertical timebases and CRT
display control for today's color TV. Furthermore, all the user
controls and manufacturer's set-up adjustments are under
the control of the processor 12C bus, eliminating the need for
potentiometer controls. Chroma 4 offers an enormous variety
of different options configurable in software, to cater to
virtually any video standard or circumstance commonly met.
The decoder section offers full multistandard capability, able
to handle PAL, SECAM and NTSC standards. Practically all
the filtering is carried out onboard the IC by means of
sampled data filters, and requires no external components or
adjustment.
Digital Interface
One of the most important features of Chroma 4 is the use
of processor control to replace external potentiometer and
filter adjustments. Great flexibility is possible using processor
control, as each user can configure the software to suit their
individual application. The circuit operates on a bidirectional
serial data bus, based on the well known 12C bus. This
system is rapidly becoming a world standard for the control of
consumer equipment.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
9-164

MC44001
12C Bus
It is not within the scope of this data sheet to describe in
detail the functioning of the 12C bus. Basically, the 12C bus is a
two-wire bidirectional system consisting of a clock and a
serial data stream. The write cycle consists of 3 bytes of data
and 3 acknowledge bits. The first byte is the Chip Address,
the second the Sub-address to identify the location in the
memory, and the third byte is the data. When the address'
Read/Write bit is high, the second and third bytes are used to
transmit status flags back to the MCU.
Figure 2 shows a block diagram of the MC44001 Bus
Interface/Decoder. To begin with, the start bit is recognized by
means of the data going low during ClK high. This causes
the Counter and all the latches to be reset. For a write
operation, the Write address ($88) is read into the Shift
Register. If the correct address is identified, the Chip Address
Latch is set and at ClK 9 an acknowledge is sent.
The second byte is now read into the Shift Register and is
used to select the Sub-address. At ClK 18 a Sub-address
Enable is sent to the memory to allow the Data in the register
to be changed. Also at ClK 18 another acknowledge is sent.
The third byte is now read into the Shift Register and the
Data bussed into the memory. The Data in the Sub-address
location already selected is then altered. A third acknowledge
is sent at ClK 27 to complete the cycle.

A Read address ($89) indicates that the MCU wants to
read the Chroma 4 status flags. In this instance, the
Read/Write latch is set, causing the Memory Enable and
Subaddress Enable to be inhibited, and the flags to be
written onto the data line. Two of the status flags are
permanently wired one-high and one-low (O.K. and Fault),
to provide a check on the communication medium between
the MC44001 and the MCU.
At start-up the Counter is automatically reset and the Data
for each Sub-address is read in. Only after the entire memory
contents has been transmitted, is Data 00 sent to start the
Horizontal Drive.
It must be noted that Chroma 4 does not fully conform to
the 12C bus specification. The protocol of the Chroma 4 bus
differs from that of the 12C bus in the following respect:
When the device is in the Read mode, it starts with the
Chip Address as always, but detects the Read bit high and
sends an acknowledge (SDA pulled low). The first byte of
data is transmitted to the MCU and an acknowledge is also
given. The second byte is transmitted, again followed by
an acknowledge. These two acknowledges are always
transmitted, both in the Read and Write mode. In the 12C
bus specification, it is normally the receiver device which
provides the acknowledge, in order to indicate the validity
of the transmission.

Figure 2. 12C Bus Interface and Decoder

Reset

I

III

4

Clock

I

Read/Write
Latch

Chip-Address
Latch
Memory &
Sub-Address
Decoding

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
9-165

Sub-Address
Latches

MC44001
Memory
Figure 3 shows a diagram of the MC44001 Memory Map. It
has 18 bytes of memory which are located at hex
sub-addresses 77 to 88. Sub-address 77 is used to set up the
vertical timebase mode of the IC and for S-VHS switching,
and consists of 8 separate data bits. The remaining 17 bytes

use the least significant 6-bits as an analog control register.
The contents of each are D/A converted, providing an analog
control current which is distributed to the appropriate part of
the circuit. Bits 6 and 7 are used singularly for switching
control functions.

Figure 3. MC44001 Memory Map

Bits 6,7

Bits 6,7

-------

...... JIl
...= ·1.,

..
...

~

i! '"
0

...
...= I.,

-------

1!... t

.
... ""..

i:'en

i:'en

Bits 6,7

..i! ~

~

ID

~

"'a:
~~
.. c

:s<

'"....

l:l
Ii! .ID

= .,
"'a:
0.2

E '"
..
c

:s<

Ii!

Bits
6,7

Bits 6,7

.

CD
CD

ID

~

.a...

~

.~

ID

1= I.,en

~

'"~ a:en

-------

..

E ~
:s ~

"'a:

i:'en
0

..

0

E 1iI
:s ~

-------

Chroma Decoder
The main function of this section is to decode the incoming
composite video, which may be in any of the PAL, NTSC or
SECAM Standards, and to retrieve the luminance and color
difference signals. In addition the signal filtering and luma
delay line functions are carried out in this section by means of
sampled data filters.
The entire decoder section operates in sampled data mode
using clocks generated by external crystals. The oscillator,
which is phase-locked in the usual way for PAUNTSC modes,
provides the clock function for the whole circuit. The crystals
are selected by the MCU by means of a control bit. Only
crystals appropriate to the standards which are going to be
received need to be fitted. A 17.7 MHz crystal (4x PAL
subcarrier) is used for PAL and SECAM systems (50 Hz, 625
lines); and 14.3 MHz (4x NTSC subcarrier) for the NTSC
system (60 Hz, 525 lines). Nearly all the filters, together with
the luma delay line and peaking, have been integrated,
requiring no external components or any adjustment. The
filter characteristics are entirely determined by the clocks and
by capacitor ratios, and are thus completely independent of
variations in the manufacturing process. The PAUNTSC
subcarrier PLL and ACC loop filters have not been integrated
in order to facilitate testing. These filters consist of fixed
external components.
Figure 4 is a block diagram of the main features of the
chroma decoder. Selection is first made between the V1 and
V2 inputs. These may be either normal composite video or
separate luma and chroma which may enter the IC at either

pin. Commands from the MCU are used to route the signals
through the appropriate delay and filter sections. A composite
video signal first passes through the sound trap filter which is
of recursive design. With the 17.7 MHz crystal selected the
following trap frequencies may be set by an MCU control
word: 5.5 MHz, 6.0 MHz, 6.5 MHz. Next, the video enters the
luma delay line and SECAM cloche filter. The PAL or NTSC
chroma signal is separated out by a transversal filter
receiving inputs from taps along the luma delay line, arranged
in such a way that group delays in PAL and SECAM are
nominally equalized. A second set of taps feeds another
transversal filter whose function is to provide a chroma trap
combined with luma channel peaking. In SECAM mode the
trap frequency is dynamically steered to follow the
instantaneous frequency of the chroma.
The high frequency luma may be peaked in 1 dB steps, up
to a maximum of + 6 dB, by a control word from the MCU.
Another control word is used to trim the delay in the luma
channel. Five steps of 56 ns are possible, giving a total
programmable delay of 280 ns. The resulting processed luma
signal then proceeds to the color difference section. The luma
output (Y1) is also made available at Pin 29, for use with
frame store or other auxiliary function.
As all the delay and filter responses are determined by the
Clock, they automatically commute to the new standard when
the crystal is changed over. Thus, when the 14.3 MHz clock is
being used the chroma trap moves to 3.58 MHz, and the
sound traps move to 4.5 MHz.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

9-166

MC44001
The demodulated color difference signals now enter the
The filtered PAUNTSC and SECAM chroma signals are
Saturation/Hue control section, where selection is made
decoded by their respective circuits. The PAUNTSC decoder
between PAUNTSC and SECAM outputs. The Saturation
employs a conventional design, using ACC action for gain
and Hue control is simply realized by altering the amplitudes
control and the common double balanced multipliers to
of both color difference signals together. Hue control is only a
retrieve the color difference signals. The SECAM decoder is
requirement in NTSC mode and would not normally be used
discussed in a separate subsection.
for other standards. The function is usually carried out prior to
The identification signals from the PAL and SECAM
demodulation of the chroma by shifting the phase of the
decoders are set in opposition to each other, this being done
subcarrier reference, causing decoding to take place along
as the best way to prevent misidentification between the two.
different axes. In Chroma 4, Hue control is performed on the
The actual decision as to a signal's identity is made by the
already demodulated color difference signals. A proportion of
MCU based on data provided by 3 flags returned to it,
the R-Y signal is added or subtracted to the B-Y signal and
namely: ACC Active, PAL Identified, and SECAM Identified.
vice-versa. This has the same effect as altering the reference
This allows a maximum of flexibility, since the software
phase. If desired, Chroma 4 can apply the Hue control to
may be written to accomodate many different sets of
circumstances. For example, channel information could be
simple PAL signals.
After manipulation by the Saturation and Hue controls the
taken into account if certain channels always carry signals in
color difference signals are finally filtered to reduce any
the same standard. Alternatively, if one standard is never
remaining subcarrier and multiplier products. Before leaving
going to be received, the software can be adapted to this
the chip at Pins 36 and 37, the signals are blanked during line
circumstance. If none of the flags are on, color killing will be
and frame intervals. The 64 Ils chroma delay line is carried
implemented by the MCU. This occurs if the net Ident Signal
out by a companion device, the MC44140.
is too low, or if the ACC circuit is inactive due to too Iowa
signal level.
Figure 4. Chroma Decoder

Video 1 -.;:

X

To Color
Difference
Stage

Video 2 ---.L

4.418.8MHz

Crystal
Select

SECAM
Cal.
Loop

SECAM Decoder
The SECAM signal from the high-pass filter enters tightly
controlled AGC amplifiers wrapped around a cloche filter
which is a sampled recursive type, with the AGC derived
from a signal squarer. Next, the signal is blanked during the
calibration gate period and a reference 4.43 MHz is inserted
during this time. The SECAM signal is then passed through
a limiter.
The frequency demodulator function is carried out by a
frequency-locked-loop (F.L.L.). This consists of three
components: a tracking filter, a phase detector and a loop
filter. The center frequency of the tracking filter depends on

three factors: internal R-C product, ADJUST voltage,
TUNING voltage. The tracking filter is dynamically tuned by
the TUNING feedback from the loop-filter forming the F.L.L.
The ADJUST control calibrates the F.L.L. and compensates
for variations in the R-C product. After the F.L.L. the color
difference Signals are passed to another block where several
functions are carried out. The signals are de-emphasized and
outputs are provided to the IDENT section. Another function
of this section is to generate the ICOMP signal used for
calibrating the F.L.L. This signal is blanked during the H-IG
period to ensure that (R-Y) and (B-Y) output signals have a
clean DC level for clamping purposes.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

9-167

MC44001
In addition, components are added to compensate for the
R-C product, and tuning offsets are introduced during the
active lines for FOR/FOB.
Calibration of the F.L.L. takes place during every field
blanking interval, starting from field retrace and ending just
before the SECAM vertical ident. sequence (bottles). The
calibration current ICAl is derived from ICOMP during the
calibration gate (CAL) and integrated by an external capacitor
on Pin 11. The resulting voltage VEXT is then transformed to
generate the ADJUST control voltage removing from the loop
range most of the variations due to internal RC products and
temperature.
Color Difference Stages
This stage accepts luminance and color difference signals,
together with external R,G,B and Fast Commutation inputs
and carries out various functions on them, including
clamping, blanking, switching and matrixing. The outputs,
consisting of processed R,G,B signals, are then passed to
the Auto Gray Scale section.
A block diagram of this stage is shown in Figure 6. The Y2,
R-Y, B-Y together with R, G and B are all external inputs to the
chip. The Y1 signal comes from the decoder section. Each of
the signals is back-porch clamped and then blanked. The Y2
and R,G,B inputs have their own simple sync separators, the
output from which may be used as the primary
synchronization for the chip by means of commands from the
MCU.

The Fast Commutation is an active high input used to drive
a high speed switch; for switching between the Y and color
difference inputs and the R,G,B (text) inputs.
After blanking, the Y1 and Y2 channels go to the luma
Selector which is controlled by means of 2-bits from the MCU.
From here the selected luma signal goes to the RGB matrix.
The two color difference signals pass through a second
saturation control, whose main function is described later.
From here they go to a matrix in which G-Y is generated from
the R-Y and B-Y, and lastly, to another matrix where Y is
added to the three color difference signals to derive R,G,B.
The R,G,B inputs may take one of two different paths.
They may either go straight to the output without further
processing, or via a separate matrix and the second
saturation control. The path taken is controlled in software.
When the latter route is selected, the R,G,B signals undergo
a matrix operation to derive Y. From this R-Y and B-Y are
easily derived by subtraction from Rand B; the derived color
difference signals are then subjected to saturation control.
The second saturation control may be disabled by the MCU if
desired. This extra circuitry allows another feature to be
added to the TV set, namely the ability to adjust the color
saturation of the RGB inputs. This is not possible on present
day receivers. After the saturation control the derived signals
are processed as before.

Figure 5. SECAM Decoder
Squarer

AGC

FLL Demodulator

L _______ _

•

VAt Adjust I

I

Ident
Out
RC·T
Compensation

PHIG
De·emphasis
Tuning Offsets
Output Interface

ICOMP

SECAM Out
Timing Signals
(R·Y/B-Y Sequen.)

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
9-168

MC44001
Figure 6_ Color Difference Stages

,-----F/C
Fast
Commutation

Sync.
Separator

YXEN

Blanking

B
G

Bypass

R

Burst Gate

YMatrix

Blanking

Blanking/Fast
Commutation
Logic

)---*-+--t-_+I R

f----+-j---< G
R-Y)-----t--.----.j

)-----_+1

B

Outputs
B-Y )------t----.--~
Blanking

Y2

Y1 ------t----.--~

Y1

Luma
Selector

Y1, Y2 Select

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

9-169

MC44001
Auto Gray Scale Control Loops
This section supplies current drives to the RGB cathode
amplifiers and receives a signal feedback from them,
proportional to the combined cathode currents. The current
feedback is used to establish a set of feedback loops to
control the DC and gain of the RGB drives. There are three
loops to control the dark currents and another three to control
the gains. During the field blanking period the video outputs
are switched off and a set of references are inserted on three
consecutive lines to control the R, G, and B outputs
respectively. The white current reference pulses are sent first,
followed by the black current reference pulses. Drives whose
outputs are not being monitored are rendered nonconducting
during this time.
A block diagram of the complete system is illustrated in
Figure 7. Data words from the MCU which represent the RGB
color temperatures selected at the factory, are stored in
Latches 1,2,3 and D/A converted by DAC1 ,2,3 to reference
currents. During, e.g., the red dark current set-up period, the
reference current from DAC1 is selected and compared with
the feedback current. The currents must match each other. If
not, a current will flow in resistor R producing an error voltage.
This is then buffered into comparators Comp1, 2 and is
compared with voltage references Vref1 and Vref2. If the error
voltage is greater than Vref1, Comp1 causes the counter to
count up. If the error voltage is less than Vref2, Comp2 sends
a count-down command. In this way a "deadband" is set up to
prevent the outputs from continuously changing.
During Load the contents of the counter are loaded into
Latch 6 (for red DC) and then D/A converted by DAC6. The
resulting DC current is then applied as an offset to the red
output amplifier, completing the loop. For white current set-up
the same color temperature data is used but multiplied by a
common factor. A common pulse representing a white level is
applied to the RGB cathode amplifiers. The feedback loop
adjusts the gains to establish a set of cathode currents scaled
by a common factor to a set of black currents. Therefore, the
image color will always be adjusted to match the black level
color; i.e. gray scale tracking is ensured.
The Load/Backload sequencer is used to control which
latch is being addressed at any given time by means of the
timing signals input to it. The backload command sends the
data from the appropriate latch to the Up/Down Counter,
ready to be modified if necessary.
The Brightness control is affected by simply changing the
DC pedestal of all three drives by the same amount, and does
notfarm part of the feedback loop_ The Contrast is adjusted to
a set of values dependent on the level of the input pulse
applied during the calibration time. This level is set by a
control word from the MCU. Once the loops have stabilized
under normal working conditions, they may be deactivated by
means of a control bit from the MCU. When, however, any
change is made to either contrast or brightness, the loops
must be reactivated.
An extra loop has been included via Latch 4 and DAC 4,
which operates during the field flyback time to compensate
for offsets within the loop. This has the effect of counteracting
any input offset from the Buffer/Amp and will also
compensate for cathode leakage should this be needed.
A second output of the reference currents from DAC6, 8
and 10 are used to compare with preset limits, to ensure that

the loops are working within their range of control. Should the
limits be exceeded in either direction, flags are returned to the
MCU to request that the G2 control be adjusted up or down as
appropriate.
Horizontal Timebase
The horizontal timebase consists of a PLL which locks up
to the incoming horizontal sync, and a phase detector and
shifter whose purpose is to maintain the H-Drive in phase with
the line flyback pulse.
Because of on-chip component tolerances, the
free-running oscillator frequency cannot be set more
accurately than ± 40%; whereas ± 5% would be a more
appropriate figure for the sake of the line output stage. For
this reason the free-running frequency is calibrated
periodically by other means. Continuously during start-up
and thence during two lines every field, the phase detector is
disconnected from the VCO. A block diagram of the line
timebase is given in Figure 8. The calibration loop consists of
a frequency comparator driving an Up/Down Counter. The
count is D/A converted to give a DC bias which is used to
correct a 1.0 MHz VCO. The 1.0 MHz is divided by 64 to give
line frequency and this is returned to the frequency
comparator. This compares Fh from the VCO with a
reference derived from dividing down the subcarrier
frequency. Any difference in frequency will result in an output
from the comparator, causing the counter to count up or
down; and thus closing the loop.
A Coincidence Detector looks at the PLL Fh and compares
it with the incoming H-sync. If they are not in lock, a flag is
returned to the MCU. To allow for use with VCRs, the gain of
the phase detector and the loop time constant may be
switched by means of commands from the MCU.
Twice line frequency is output from the PLL which may be
divided by either 1 or 2 depending on the command of the
MCU. The x2 Fh will be used with Frame Store TV in the
future. The phase of the Fh and fiyback pulses are compared
in a phase detector, whose output drives a phase shifter. A
6-bit control word and D/A converter are used to apply an
offset to Ihe phase detector giving a horizontal phase shift
control. Also the phase of the horizontal drive may be shifted
by 180 degrees with a control bit set by the MCU.
The presence of the horizontal flyback pulse is detected; if
it is missing a warning flag is sent back to the MCU which can
take appropriate action.

Vertical Timebase
The vertical timebase consists of two sections; a digital
section which includes a vertical sync separator and
standard recognition; and an analog section which generates
a vertical ramp which may be modified under MCU control to
allow for geometrical adjustments. A parabola is also
generated and may be used for pin-cushion (E-W) correction
and width control (see Figure 9).
The MC44001 uses a video sync separator which works
using feedback, such that the threshold level of a comparator
(slice level) is always maintained at the center of the sync
pulse. Sync from any of the auxiliary inputs may also be used.
The composite sync is fed to a vertical sync separator, where
vertical sync is derived. This consists of a comparator,

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

9-170

MC44001
up/down counter and decoder.The counter counts up when
sync is high, and down when sync is low. The output of the
decoder is compared with a threshold level, the threshold
only being reached with a high count during the broad pulses
in the field interval.
Initially the vertical timebase operates in Injection Lock
mode, until a standard signal is recognized (525, 625), then it
is switched to a Countdown mode. A standard recognition
circuit is employed, which looks for a count of more or less
than 576; the standard recognized is then indicated to the
MCU. Commands from the processor may be used to force
the timebase to operate only in Countdown mode at 525 or
625 lines, or stay in Injection Locked mode.
An adjustable current source is used to charge an external
capacitor at Pin 6 to generate a vertical ramp. The amplitude
of the ramp is varied according to the current source (Height),
and is automatically adapted when the 525 standard is
recognized by multiplying by 1.2. The Linearity control is
achieved by squaring the ramp and either adding or
subtracting a portion of it to the main linear current.
The final ramp with corrections added is then passed to a
driver/amplifier and is output at Pin 7. The vertical ramp can
be used to drive a separate vertical deflection power circuit
with local feedback control. Vertical "S" Correction will then be
made using fixed components within the feedback loop of the
power op amp.
The reference ramp is squared to provide a pin-cushion
correction parabola, developed across an external resistor at
Pin 8. The parabola amplitude may be varied from zero to a
maximum level set by the external resistor. The parabola
itself is squared, giving and independent fourth order term
(Corner Correction) whose level can also be varied; this is
then added as a further modifying term to the E-W output.
This latter correction is used for obtaining good corner
geometry with flat-square tubes. A variable DC current is
added to the parabola to effect a width control. Using a
suitable power amplifier and a diode-modulator in the line
output stage, the parabola may be used for E-W correction
and dynamic width control. A further control is provided to
shift the center point of the parabola up and down the screen
(Parabola Tilt), to accommodate different CRTs. As with the
vertical ramp output, an EHT correction is applied.
All of the vertical and horizontal signals are adjustable via
6-bit words from the MCU, and stored in latches. The
adjustment controls available are:
Vertical Amplitude/Linearity/Breathing Correction
Parabola (E-W) Amplitude/Horizontal Amplitude/
Corner Correction, and Parabola Tilt
The Anode Current Sense at Pin 9 is also used as a beam
current monitor. Two thresholds may be set, by the
manufacturer, using external components. The first threshold
sets a flag to the processor if beam current becomes
excessive. The MCU could e.g. reduce brightness and/or
contrast to alleviate the condition. The second threshold sets
a flag warning of an overload condition where the CRT
phosphor could be damaged. If such a condition were to
arise, the processor would be programmed to shut down
the PSU.
The vertical blanking period may be selected by means
of a bit from the MCU to either 22 or 11 lines. The interlace
may also be suppressed again under the control of
the processor.

Vertical Countdown System
The MC44001 uses a countdown system to implement
the vertical timebase function. Initially, the vertical timebase
should reset to the Injection mode. This means that the
timebase locks immediately to the first signal received, in
exactly the same way as an old type injection locked
timebase. A Coincidence Detector looks for counts of the
right number (e.g., 625) and causes a 4-bit counter to count
up. When there are 8 consecutive coincidences the vertical
countdown is engaged, and the MSB of the counter is
brought out to the set flag. Then the Auto Coundown mode
should be set. Similarly, non-coincidences which will occur if
synchronizing pulses are missing or in the wrong place, or if
there is noise on the signals, cause the counter to count
down. When the count goes back to zero, after 8
non-coincidences, the timebase automatically reverts to
Injection Lock mode.
If it is known that lock will be lost (e.g., channel change), it
is possible to jump straight into Injection Lock mode and not
have to wait for the 8 consecutive non-coincidences. In this
way the new channel will be captured rapidly. Once locked on
to the new channel, "auto countdown" is then reselected by
the MCU.
Under some conditions such as some VCRs in Search
mode, it is possible to get signals having an incorrect number
of lines, meaning that the countdown flag will go off because
of successive non-coincidences. In these circumstances, if
"auto countdown" is selected, the timebase will automatically
lock to the signal in the Injection Lock mode. The fact that the
flag is effectively saying that the vertical timebase is out of
lock need not be a cause for major concern, since the
horizontal timebase will still be locked to the signal, and has
its own flag - "Horizontal out of lock". The vertical
countdown and horizontal lock flags both perform an
independent test for the presence of a valid signal. A logical
OR function can be performed on the two flags, such that if
either are present then by definition a valid signal is present.
The vertical oscillator has end-stops set at two line-count
decodes as given below:
50 x 625/672 = 46.5 Hz (min)
50 x 625/512 = 61.0 Hz (max)
These figures assume that the horizontal timebase is
running at 15,625 Hz. When the vertical timebase is in
Injection Lock mode the line counter reset is inhibited so that
it ignores any sync pulses before a count of 512 is reached.
This prevents any possible attempted synchronization in the
middle of the picture. If the count reaches 672 lines then there
is an automatic reset which effectively sets the lower
frequency limit. The choice of these limits is a compromise
between a wide window for rapid signal capture and a narrow
window for good noise immunity.
It is also possible to run the timebase in 2V mode as there
are decodes for 100 Hz (2 x 50 Hz) operation with upper and
lower limits in proportion. This is, of course, intended to be
used in conjunction with field and frame memory stores. The
similar decodes which would be necessary to allow 120 Hz (2
x 60 Hz) operation have not, for the present, been
implemented. Finally, the timebase can be forced into a count
of either 625 or 525 by commands from the MCU; in this
mode the input signal, if present, is ignored completely. If
there is no signal present save for noise, then this feature can
be used to obtain a stable raster.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

9-171

MC44001
Figure 7. Auto Gray Scale Control Loops
Feedback

2.5V

Color Temperature
Data from MPU

ToMPU
~

Up
Down
Request Request

ROC
GoC
BoC

Offset
Compensation

Up/Oown
Counter

Clock oebounce

1+---- Vertical
Clock

Vertical
RED Une
GREEN Une

~§

BLUE Une

C'

"
'"

TIming
Signals

CI)

'C

t

Backload

~
.9

Load

III

Bright
Dark

PIN FUNCTION AND EXTERNAL CIRCUIT REQUIREMENTS
The following section describes the purpose and function
of each of the 40 pins on the MC44001. There is also an
explanation of the external circuit component requirements
for a practical application; a diagram of the small signal circuit
will be found in Figure 10. One of the primary design aims for
the MC44001 was to use the minimum number of external
components, and where these are necessary to employ low
cost and easily obtainable standard types. Thus for example,
as all the video signal filtering is carried out on the IC there
are no coils required whatsoever. The most common
requirement is for AC coupling capacitors which are far too

big to be integrated onto the chip. The time constants on
certain pins are deliberately left as external components to
facilitate testing and for fine tuning the performance.
ACC (Pin 1) - External filter used by ACC section. Normally a
single 100 nF capacitor.
Video Inputs 1, 2 (Pin 2, 40) - Video inputs intended for a
nominal 1.0 Vp-p input level of composite video. Separate
Luma and Chroma components may also be used with
these input pins. The external circuit requirement is for a
series 100 nF and 1.0 kn. The input selection and
adaptation for Y and C is carried out in software.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

9-172

MC44001
Figure 8. Horizontal Timebase
IS.625kHz!
18kHz

Coincidence (MPU)

~

15

12 Drive Out
Flyback In
(MPU)

(MPU)

14

~

Figure 9. Vertical Timebase
2Fh
Clock

EHT
Height

Unearity

Correction

Composite
Sync

Vertical
Ramp

6

9
Vertical Anode Current
Output
Sense

E·W
Drive

+S.OV

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

9-173

MC44001
Reference Current (Pin 3) - Master reference current used
throughout the IC. This is programmed by means of an
external pull-up resistor, as onboard resistors are not
sufficiently accurate. The designated current is 70 !LA. This pin
should be very well decoupled to ground to avoid picking up
interference from the nearby 12C bus inputs.

there is no separate ground pin available which may be
connected near the line O/P stage; noise could be injected into
the signal ground on the IC. Therefore, with a transformer
driven line output stage, this output has been designed to be
used with an extra external transistor inverter between the IC
and the line driver.

12C Clock (Pin 4) -12C bus clock input. This input can be taken
straight into the IC, but in a real TV application it may be
prudent to fit a series current limiting resistor nearby the pin in
case of flashover.

H-Flyback Input (Pin 13) - Flyback sensing input taken from
the line output transformer. These pulses are used by the 2nd
horizontal loop for H-phase control. A positive going pulse
from 0 V to + 5.0 V amplitude is needed for correct operation.
The internal impedance of the pin is about 50 kQ. An external
attenuating series resistor will also be needed.

12C Data (Pin 5) -12C data input. The comment above for Pin 4
also applies to this pin.
Vertical Ramp (Pin 6) -A current is used to charge an external
capacitor connected to this pin, developing a voltage sawtooth
with a field period.
Vertical Drive (Pin 7) - The sawtooth derived on Pin 6 is used
to drive an external power amplifier vertical output stage. The
amplitude and linearity of the output ramp are adjustable via
the MCU.
Parabola (E-W) Drive (Pin 8) - A parabolic waveform derived
by squaring the vertical ramp is used to drive an external
power amplifier. In sets fitted with a diode modulator type line
output stage, this provides Width Control and Pin Cushion
Correction. The parabola is squared again to give a fourth
order correction term required for flat square tubes. The E-W
amplitude, DC level, Tilt and Corner Correction are all
adjustable by means of the MCU. This is a current output
and requires an external pull-up resistor to develop the
voltage waveform.
Anode Current (Pin 9) - Used as an anode current monitor
whose purpose it is to: provide EHT compensation
(antibreathing); and also warn of excessive and overload
beam current conditions.
This pin is connected via 560 k series resistor to the bottom
of the EHT overwinding. Thus increasing beam current will
pull the voltage on this pin more negative. This change is
sensed within the chip and used to apply a correction to the
ramp and parabola amplitudes. With large beam currents,
thresholds at + 1 Vbe and - 2 Vbe set off warning flags to the
MCU, which then has to take the appropriate action. The
anode current levels at which these thresholds are reached
are set up using fixed external resistors.
Grid 2 Control (Pin 10) - This consists of one ofthe MC44001
control registers which has been D/A converted and brought
out from the IC as a current source. The current may be varied
from o!LA to 300 !LA, and may be used for a number of auxiliary
tasks, such as for Grid 2 control.
SECAM Calibration Loop (Pin 11) - A 100 nF capacitor on
this pin is used for the SECAM Calibration Loop.
H-Drive (Pin 12) - Horizontal drive pulses having an
approximately even mark-to-space ratio emerge from this pin.
This is an open-collector output which can sink up to 10 mAo
However, taking this much current is not recommended since

H-Loop 2 Filter (Pin 14) - A simple external filter consisting of
a 100 nF capacitor for the 2nd horizontal loop.
H-Loop 1 Filter (Pin 15) - Horizontal PLL loop time constant.
The value of RC time constant is selected with external
components to give a smooth recovery after the field
interval disturbance.
Signal Ground (Pin 16)
R,G,B Outputs (Pin 17, 18, 19)-The R,G,Bdrives are current
rather than voltage due to the limited headroom available with
the 5.0 V supply line. The outputs themselves consist of
open-collector transistors and these are used to drive the
virtual ground point of the high voltage cathode amplifiers.
Feedback (Pin 20) - Current feedback sense derived from the
video output amplifiers. The currents from all three guns are
summed together as each is driven sequentially with known
current pulses during the field interval. This feedback is then
compared with internally set-up references. A low value
ceramic capacitor to ground may be fitted close to this pin to
help stabilize the control loops.
A secondary function of this pin is for peak beam current
limiting. When the feedback voltage during picture time
becomes too great (i.e., too high beam current), a threshold
at VCC + 2 Vbe is exceeded at which time a flag is sent to the
MCU. The MCU then has to carry out the function of peak
beam limiter by e.g. reducing contrast until the flag goes off.
The threshold current is set externally with a fixed resistor
value.
Fast Commutate (Pin 21) - A very fast active high switch
(transition time IOns). Used with text on the R,G,B inputs, for
overlaying text on picture. This hardware switch may be
enabled and disabled in software.
R,G,B Inputs (Pins 22, 23, 24) - These external input signals
are AC coupled into the IC via 100 nF capacitors and are
clamped. The inputs have a 1.0 kQ impedance and should be
driven with 700 mVp-p signal levels.
Y2 Input (Pin 25) - Auxiliary external input to the MC44001.
The pin has a 1.0 kQ impedance and should be driven with
700 mVp-p of luminance signal. The signal must be AC
coupled via an external 100 nF coupling capacitor, and is
clamped internally.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

9-174

MC44001
B-Y and R-Y Inputs (Pin 26, 27) - Corrected color difference
inputs from the MC44140. The signals are AC coupled to the
MC44001 color difference section and are clamped. The input
impedance is of the order of 1.0 kil.
Y1 Clamp (Pin 28) - External capacitor used by the circuit
which clamps the Yl signal output on Pin 29.
Y1 Output (Pin 29) - The luminance, after passing through
the filter and delay line/peaking sections, is made available on
this pin.
System Select (Pin 30) - A DC level output controlled in
software. Used by the MC44140 for system selection.
Sandcastle (Pin 31) - A special timing pulse derived in the
MC44001 for use by the MC44140.
Crystal (Pin 32, 33) - A 14.3 MHz crystal is required at Pin 32
for NTSC decoding, and a 17.7 MHz crystal is required at Pin
33 for PAL and SECAM decoding. Either crystal may be
omitted if the application does not involve the associated
signals. The appropriate crystal is selected by the MCU.
The crystals are parallel-driven, and require an external
load capacitor of 20 pF to 30 pF. Only crystals intended for
VCO operation should be used. The selected crystal's
frequency is made available to the MC44140 by means of the
external capacitor divider.

+ 5.0 V Supply (Pin 35) - Supply line, nominally + 5.0 V
requiring about 120 mAo The actual voltage should be in the
range of 4.75 V to 5.25 V for usable results. It is recommended
to decouple the supply line using a small ceramic capacitor
mounted close to the supply and ground pins.

Ground (Pin 34)
B-Y and R-Y Outputs (Pin 36, 37) - Demodulated color
difference outputs. These signals are AC coupled to the
MC44140 for correction and delay with PAL and SECAM,
respectively. Signal levels up to a maximum of 1.0 Vp-p may
be expected.
Ident (Pin 38) - External filter used by R-Y indent circuit. The
filter normally consists of a single capacitor (47 nF) whose
value is a compromise between rapid identification and noise
rejection.
OSC Loop Filter (Pin 39) - External time constant for chroma
PLL. The crystal reference oscillator is phase-locked to the
incoming burst in PAL and NTSC. A low value ceramic
capacitor, for good noise immunity, is normally placed in
parallel with a much longer RC time constant. The PLL pull-in
range is reduced when the time constant on the pin is made
bigger; allowing this function to be optimized by the user.

CONTROL FUNCTIONS
General Description
As already related in the circuit description, the MC44001
has a memory of 18 bytes. All, except Sub-address 77 and
7F, use the 6 least significant bits (64 steps) as an analog
control register with D/A converters within the memory
section. The remaining bits are controlled individually for
switching of numerous functions. Table 1 gives a listing of all
the memory registers and control bits. An explanation of the
function of the 16 analog control registers is given below.

D/A Output - A variable DC current output which may be used
to drive auxiliary external circuitry under 12C bus control.

Vertical Amplitude - Changes the amplitude of the vertical
ramp available on Pin 7.

Horizontal Phase Control- Applies a variable phase offset to
the horizontal drive pulse at Pin 15 providing for a picture
centering control.

Vertical Breathing Correction - A correction is applied to the
vertical ramp amplitude in a sense opposite to the picture
expansion and contraction produced by changes in beam
current. This register alters the sensitivity of the beam current
sensing and hence the size of correction applied for a given
change in beam current.
Parabola Amplitude - Changes the amplitude of the E-W
output parabola developed across an external pull-up resistor
at Pin 8.
Parabola Tilt - Shifts the point of inflection of the E-W
parabola from side to side along the time axis. Also known as
keystone correction.
Vertical linearity - The vertical ramp is multiplied by itself to
give a squared term, a part of which is either added or
subtracted to the linear ramp as determined by this register.

Corner Correction - An independent 4th order term which is
subtracted from the E-W parabola to achieve correct geometry
with flat square tubes.
Horizontal Amplitude - A variable DC offset applied to the
E-W output parabola on Pin 8.

B, G, R Temperature - These controls set up the current
reference pulses used when sampling the beam current
during field interval. The data is fixed by the TV manufacturer
when setting up the CRT for correct Gray Scale tracking.
(All the above registers are for use during the test and
setting up pmcedures; the remaining 4 registers are also user
controls.)
Contrast - During bright sample time during the field interval
this control varies the level of the current pulses injected into
the R,G,B channels, so altering the picture contrast.
Brightness - A variable current pedestal which is added to
the three drives during active picture time.
Slituratlon - A variable gain control for the two color
difference signals (0 to 140%). There are two such controls
within the MC44001, and this control acts on them both.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

9-175

MC44001
Hue - Achieved by mixing a proportion of one color difference
signal into the other.

the new channel and hence no picture roll. If there is no valid
signal being received the display can be stabilized by forcing
the timebase into 525 or 625 lines.

Individually Adjustable Control Bits - These consist of all
Sub-address 77 and bits 6 and 7 of Sub-addresses 78 to 88.
Some of these are used individually to control single functions
requiring just on/off switching; and some are arranged into 2 or
3-bit words (e.g., luma peaking). A list of control words and
truth tables for these may be found in Table 2.

IC1, IF1 - These bits are used to suppress the field interlace,
which can be scanned in the nearest even or odd half line.
H1, V1 - Selects the type of SECAM ident when operating in
this mode. Either vertical ident bursts or back porch ident can
be selected individually, or ident can be taken from a
combination of the two.

CA1, CB1 - Used to change the mode of operation of the
vertical timebase to either injection lock or auto countdown, or
to force it into 525 or 625 lines. Just prior to changing channel,
the vertical timebase can be switched to injection lock mode
and when a new channel is captured, the time base is switched
back to auto mode. In this way there is no delay in locking onto

SSA, SSB, SSC - Used to set the DC level of the System
Select output from the MC44001, Pin 30. This output is used
by the MC44140 delay line in turn for changing between PAL,
NTSC, SECAM and external modes of operation. In effect the
MC44140 is being controlled by the 12C bus via the MC44001.

Figure 10. Basic Small Signal Circuit
Video 2

+5.0V

Video 1

~i

+5.0V 100i-t 75100h75

52k

Clk

1.0k~

11.0k
_

Gnd

_

+5.0V
Data

+ 5.0V
+5.0V

3.9k

E·W

68k

Driv.

Vertical
Driv.

16

Anod.
Currenl
220

+ 5.0V
30

D/A()4-

Yl0ut

29

11

28

10

27
26
H·Drive

0------4
BC337
120k
22k

16

25

17

24

18

23

19

22

20

21
+ 5.0
390

~
H.flyback

1

~F/B

100

F/C
~

Outputs

B

G

R

~

Y2 R·Y B·Y
/

Inputs

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
9-176

IOn

MC44001
Table 1. Control Data
HEX Sub-address

MSB

77

S·VHS Y

S·VHSC

78

INTSEL

CALKILL

Vertical Amplitude

Data Byte
FSI

I

I

BAI

LSB
ICI

I

I

IFI

CBI

79

HI

VI

Vertical Breathing Correction

7A

XS

SSD

Parabola Amplitude

7B

T1

T2

Parabola Tilt

7C

SSC

SSA

Vertical Linearity

7D

P1

SSB

Corner Correction

7E

P3

P2

Horizontal Amplitude

7F

D3

D1

Reserved

80

DEN

D2

D/AOutput
Horizontal Phase Control

81

Y2 EN

Y1 EN

82

TEST

YXEN

Blue Temperature

83

Not Used

VCR

Green Temperature

84

FILT

NORM

Red Temperature

85

BRIEN

2x Fh

Contrast

86

SSE

HEN

Brightness

87

SS1

SAT2 EN

Saturation

88

V11V2

SS2

I

CAl

Hue

00

Dummy - If H EN, then starts H timebase

FF

Dummy - Resets peak beam limit flag

Camp. Video/S·VHS Switching
(0 = normal; 1 = S·VHS)
50 Hz/I 00 Hz Field Rate

ICI IFI

x
HI VI
0 0
0 1
1 0
1 1

Nurn berafBI anked Unes
(Either 22 or 11)

SECAMldenl
H+V
Honl
V only
None

I
Tl 12

Trap (4.4S/C)

0
0
1

0
1
0

6.5 MHz
Not Used
6.0 MHz

1

1

5.5 MHz

Reduce Vertical
Time Constanl Crystal Select -

tuma Peaking (dB)

INTSEL

1
1

0
1

Field Scan
Intertaced
Even 1/2 Une
Odd 1/2 Une

VI

XS

SSD

11

T2

SSC

SSA

PI

SSB
P2

03

01

Disable RGB Input -

DEN

02
Yl EN

I- Enable tuma from Filters

TEST

YXEN

I- Enable tuma Matrix

NotUsed -

DELAY

VCR

FILT

NORM

I- Select 625/50Hz

BRIEN

2XFH

I- Double Fh

Select Video Input -

V\N2

SSC

SSA

SSB

Col. Dill. Source

0
0
0
0
1

0
0
1
1
X

0
1
0
1
X

SECAM
PAL
NTSC
None
External

SSE
0
0

SSI

0
0

1
1

SS2
0
1
0
1

1

X

X

Sync Source
None
RGB
Y2
N01 Used
Camp. Video

tuma Delay in Muniples of 56 ns

Y2EN

SSI

Force 625
Force 525
In'ecllock
Auto Count.

Ovende SECAM Mode

Enable Y21nput -

SSE

1
0
1

I- Select in Delay Une

For Production Test -

Enable Bright Sample -

0
1
1

CALKILL I- Disable Calibration loop

HI

P3

Change PLL Time Constant -

CAl CBI Verlical Mode

I- Select High P.O. Gain

HEN ,- Enable H·Drive
SAT2EN - Disable 2nd Sat. Control
SS2

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
9-177

0
0

MC44001
Table 2. Control Bit Truth Tables
CAl

CBI

Sync Mode

ICI

IFI

a
a

a

Force 625

0

X

Field Scan
Interlaced

1

Force 525

1

a

Even Up 1/2 Line

1

1

Odd Up 112 Line

1

a

Injection Lock

1

1

Auto Countdown

HI

VI

SECAM Ident.

Tl

T2

Trap'

a
a

a

H+V

0

0

6.5 MHz

1

H only

a

1

Not Used

1

a

Vonly

1

a

6.0 MHz

1

1

None

1

1

5.5 MHz

SSC

SSA

SSB

Col. Dill. Source

SSE

SSI

SS2

Sync Source

a
a
a
a

a
a

a

SECAM

None

PAL

a
a

a

1

a
a

1

RGB

1

a

NTSC

0

1

a

Y2

1

1

None

a

1

1

Not Used

1

X

X

External

1

X

X

Compo Video

P2

P1

P3

Luma Peak (dB)
@3.0MHz'

01

02

03

Approx. Luma
Delay (ns)'

a
a
a
a

0

0

8.5

0

0

0

525

0

1

8.0

a

0

1

581

1

0

7.2

0

1

0

637

1

1

6.3

0

1

1

693

1

0

0

5.4

1

0

0

749

1

0

1

3.8

1

0

1

805

1

1

0

2.3

1

1

0

749

1

1

0.0

1

1

1

805

1

'Values given with 17.7 MHz crystal selected. Frequencies and delay step size change proportionately
when the 14.3 MHz crystal is selected.

SSE, SSI, SS2 - These 3 bits select the signal input from
which tl:!e timebase synchronization is taken. The composite
video input has a high quality sync separator which has been
designed to cope with noise and interference on the video; the
RGB and Y2 inputs have simple single sync separators which
may also be used for synchronization.
Tl, T2 - To select the center frequency of the sound trap.
Either 5.5 MHz, 6.0 MHz, or 6.5 MHz center frequencies
are available.
PI, P2, P3 - These 3 bits are used to adjust the luma
peaking value.
Dl, D2, D3 - These 3 bits are used to adjust the luma
delay value.
The remaining control bits are used Singularly and are
listed as follows:
S-VHS Y - Selects between luminance from chroma
trap/peaking section, and separate luminance which
bypasses this filter section.

S-VHS C -In one mode selects chrominance from the takeoff
filter which forms part of the luma delay line. The other mode
accepts separate chrominance directly for the input.
FSI- Selects either 50 Hz or 100 Hz field rate. When bit is low
50 Hz operation is selected. Not usable with NTSC.
BAI - Either 22 or 11 lines may be blanked using this bit.
INTSEl - The vertical sync separator operates by starting a
counter counting up at the beginning of each sync pulse, a
field pulse being recognized only if the counter counts up to a
sufficiently high value. The control bit INTSEL is used in taking
the decision as to when a vertical sync pulse has been
detected. When low, the pulse is detected after 8.0 /-1S; when
high after 24 /-1s. This may find application with anti-copy
techniques used with some VCRs, which rely on a modified or
corrupted field sync to allow a TV with a short time constant to
display a stable picture. However, a VCR having a longer time
constant will be unable to lock to the vertical.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

9-178

MC44001
CALKILL - Enables or disables the horizontal calibration
loop. The loop may be disabled so long as the horizontal
time base is locked to an incoming signal.

FILT - Controls the time constant of the horizontal PLL. The
long time constant is useful for VCR or other non-broadcast
quality signals.

XS - Is used to change between the two external crystal
positions (Pins 32 and 33).

Norm - Alters the division ratio for the reference frequency
used by the horizontal calibration loop. Always used when
changing between 14.3 MHz and 17.7 MHz crystals.

SSD- Can be used to override SECAM mode in the delay line.
When low, SECAM mode is enabled.
DEN - Enables or disables the RGB Fast Commutation switch
for the RGB inputs. When low, RGB inputs are enabled.
Y1 EN - Switches Y1 through to the color difference stage.
Y2 EN - Switches Y2 through to the color difference stage.
Test - When bit is low, enables continuous sampling by the
RGB output control loops throughout the entire field period.
Used only for testing the IC.
YX EN - Enables the luma matrix when the 2nd saturation
control is selected. Used in conjunction with SAT2 EN.
VCR - Is used to change the gain of the horizontal phase
detector, e.g., when locking onto a new channel and operation
with VCR.

BRI EN - Used to switch on or off the "bright" sampling pulses
used by the RGB output loops. This feature was originally
introduced to prevent any backscatter from these three bright
lines in the field interval from getting into the picture. Must be
enabled when adjusting to any of Contrast or Red, Green and
Blue color temperatures.
2x Fh - Line drive output is either standard 15.625 kHz
(15.750 kHz) or at double this rate.
H EN - Control bit enables horizontal drive pulse. This is
normally done automatically after the values stored in the
MCU nonvolatile memory have been read into the MC44001
memory.
SAT2 EN - When low enables operation of 2nd saturation
control. Used in conjunction with YX EN.

V11V2 - To select between Video Inputs 1 and 2.

Table 3. Control Bit Functions
Bits
V11V2

Bit High

Bit Low
Video liP 2 Selected

Video liP 1 Selected

Second SAT Control Enabled

Second SAT Control Disabled

HEN

H-Drive Enabled

H-Drive Disabled

2x FH

H-Drive: 1X Fh

H-Drive: 2x Fh

SAT2 EN

"Bright" Sample Switched Off

"Bright" Sample Switched On

625/50 Hz

525/60 Hz

FILT

H Phase Detector Short lime Constant

H Phase Detector Long lime Constant

VCR

Low H Phase Detector Gain

High H Phase Detector Gain

BRI EN
Norm

YXEN

Disable Luma Matrix (2nd SAT Control)

Enable Luma Matrix (2nd SAT Control)

Video OIPs Sampled Continuously

Video OIPs Sampled Once Per Field

Y1 EN

Luma From Filters Switched Off

Luma From Filters Switched On

Y2 EN

EXT Luma Input Switched Off

EXT Luma Input Switched On

DEN

RGB Inputs Enabled

RGB Inputs Disabled

SSD

SECAM Mode Select Enabled

SECAM Mode Select Disabled

Pin 33 Crystal Selected

Pin 32 Crystal Selected

H Calibration Loop Enabled

H Calibration Loop Disabled

Fast Vertical lime Constant Selected

Slow Vertical lime Constant Selected

22 Blanked Lines Selected

11 Blanked Lines Selected

Test

XS
CALK ILL
INTSEL
BAI

50 Hz Field Rate Selected

100 Hz Field Rate Selected

S-VHSC

Chroma From Take Off Filter Selected

Direct Chroma From liP Selected

S-VHS Y

Luma From NotchlPeak Delay Selected

Luma By Passing NotchlPeak Delay

FSI

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

9-179

MC44001
FLAGS RETURNED BY THE MC44001
When the Address Read/Write bit is high the last two bytes
of 12C data are read by the MCU as status flags; a listing of
these may be found in Table 4. The MC44001 is designed to
be part of a closed-loop system with the MCU; these flags are
the feedback mechanism which allow the MCU to interact
with the MC44001.
A brief description of each of the flags, its significance and
possible uses are given below.
Table 4. Flags Returned
Clock #

Flag (Bit High)

10

Horizontal Flyback Present

11

Horizontal Drive Enabled

12

Horizontal Out Of Lock

13

Excess Average Beam Current

14

Less Than 576 Lines

15

Vertical Countdown Engaged

16

Overload Average Beam Current

17

Reserved

18

(Acknowledge)

19

Grid 2 Voltage Up Request

20

Grid 2 Voltage Down Request

21

OK

22

Fault

23

ACC Active

24

PAL Identified

25

SECAM Identified

26

Excess Peak Beam Current

27

(Acknowledge)

Horizontal Flyback Present - A sense of the horizontal
flyback is taken via a current limiting series resistor from one of
the flyback transformer secondaries to Pin 13. This is used for
the H-phase shift control, but the presence of the pulse is also
flagged to the MCU. Should the flag be missing after the
chassis has been started up then the MCU would have to shut
down the set immediately.
Horizontal Drive Enabled -Indicates that the horizontal drive
pulse output at Pin 15 has been enabled. This occurs after the
stored values in the nonvolatile memory have been
transferred to the MC44001 memory.
Horizontal Out of Lock - This flag is high when no valid
signal is being received by the MC44001. Possible action in
this case would be to change the phase detector gain and
time constant bits to ensure rapid capture and locking to a
new signal.
Excess Average Beam Current - Is one of two conditions
whose threshold levels are determined by an external

component network connected to beam current sensing Pin 9.
This condition indicates an excess beam current as compared
tothe manufacturer's set maximum level during normal usage.
A typical response to this warning indicator would be for the
MCU to reduce the brightness and/or contrast.
Less Than 576 Lines - Output from the line counter in the
vertical timebase. If there is a count of less than 576 this is
indicative of a 525 line system being received. If the flag is low
then a 625 line system is being received. This information can
be used as a part of an automatic system selection software.
Vertical Countdown Engaged - The vertical time base is
based on a countdown system. The timebase starts in
Injection Lock mode and when vertical retrace is initiated a
4-bit counter is set to zero. A coincidence detector looks for
counts of 625 lines. In Auto mode each coincidence causes
the counter to count up. When eight consecutive coincidences
are detected the countdown is engaged. The MSB of the
counter is used to set this flag to the processor.
Overload Average Beam Current - This is the second
threshold level which is set by the external component network
on Pin 9. The flag warns of an overload in anode current which
could damage the CRT if allowed to continue. Appropriate
action in this case is therefore to shut down the set.
Grid 2 Voltage Up/Down Requests - These flags indicate
when the RGB output loops are about to go out of the control
range necessary for correct gray scale tracking.
OK and Fault- These two flags are included as a check on the
communication line between the MCU and MC44001. The OK
flag is permanently wired high and Fault is permanently wired
low. The MCU can use these flags to verify that the data
received is valid.
ACC Active- This flag is high when there is a sufficient level of
burst present in PAL and NTSC modes during the video back
porch period. The flag goes low when the level of burst falls
below a set threshold or if the signal becomes too noisy. The
flag is used to implement a software color killer in PAL and
NTSC and is also available for system identification purposes.
Since in SECAM there is line carrier present during the gating
period, it is quite likely that the ACC will be on, or will flicker on
and off in this mode.
• PAL Identified - Recognizes the line-by-line swinging phase
characteristic of the PAL burst. When this flag is on together
with the ACC flag, this is positive identification for a PAL Signal.
• SECAM Identified - Senses the changing line-by-line
reference frequencies (F01 and F02) present during the back
porch period of the SECAM signal. This flag alone provides
identification that SECAM is being received.
• These two flags are set in opposition to one another such that they can never
both be on at the same time. This has been done to try to prevent
misidentification from occurring. Often it is very difficult to distinguish between
PAL and SECAM especially when broadcast material has been transcoded,
sometimes badly. leaving e.g. large amounts of SECAM carrier in a transcoded
PAL signal (also often with noise). With this method the strongest influence will
win out making a misidentification much less likely.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
9-180

MC44001
picture. This flag together with the excess average beam flag
already described perform the function of beam limiting. The
exact way in which this is handled is left to the discretion of the
user who will have their own requirements, which may be
incorporated by the way in which the software is written.

Excess Peak Beam Current - A voltage threshold is set on
the beam current feedback on Pin 20, which is also used for
the RGB output loops for current sampling. When the
threshold is reached the flag is set, indicating too high a peak
beam current which may be in only a part of the screen. The
response of the MCU might be to reduce the contrast of the

READING AND WRITING TO THE MC44001
Flag reading may be done at any time during a field.
However, writing to the MC44001 must be restricted to
certain times. If writing of new data is done during the
middle of a field, a disturbance will be seen on the screen,
particularly for the four user controls. While writing during
the vertical interval may appear to be the obvious solution
for this, there is a limited time available due to the contrast
control function which is carried out with RGB sampling

loops during this interval. Writing during this particular time
can cause the sampling loops to become unstable.
The time available for writing new data is approximately
1.2 ms from the beginning of the field flyback pulse to the
beginning of the RGB sampling. It is only the third by1e
(data byte) which is restricted to this time interval. The first
two bytes may be sent previous to this, or also during
this time.

Table 5. System Identification
Flags From Chroma 4

<576

Standard Selected
By MCU

Lines

ACCOn

PAL

SECAM

Crystal
(MHz)

0

0

0

0

17.7

Kill

0

0

0

1

17.7

SECAM

0

0

1

0

17.7

Kill

0

0

1

1

17.7

12C Bus Error

0

1

0

0

17.7

Kill

0

1

0

1

17.7

SECAM

0

1

1

0

17.7

PAL

0

1

1

1

17.7

12C Bus Error

1

0

0

0

14.3

Kill

1

0

0

1

14.3

Kill

1

0

1

0

14.3

Kill

1

0

1

1

14.3

12C Bus Error

1

1

0

0

14.3

NTSC

1

1

0

1

14.3

NTSC

1

1

1

0

14.3

NTSC

1

1

1

1

14.3

12C Bus Error

NOTES: 1. The table above can be used for color standard selection between the normal PAL (I. 8G). SECAM (L. 8G)
and NTSC (3.58 MHz - M) Standards. To detect the hybrid VCR standard (525 lines with 4.4 MHz
chrominance) would entail switching back to the 17.7 MHz crystal in the event of there being no flags
present with the 14.3 MHz crystal.
2. Chroma 4 could also be used for the PAL M & N Standards that are used in some parts of South
America, but because the subcarrier frequencies used differ by some kHz from the normal, crystals
with a different center frequency would be required.

Table 6. Mode Definitions
Control Bits
Mode
Selected

XS·

NORM'

SSA

SSB

SSC

Kill (17.7 MHz)

0

0

1

1

0

Kill (14.3 MHz)

1

1

1

1

0

PAL (I, BG)

0

0

0

1

0

SECAM

0

0

0

0

0

NTSC(M)

1

1

1

0

0

'Control bits XS and NORM are always changed together.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
9-181

MC44011

MOTOROLA

SEMICONDUCTOR-----TECHNICAL DATA

Advance Information
Bus Controlled Multistandard
Video Processor

BUS CONTROLLED
MULTISTANDARD
VIDEO PROCESSOR

The Motorola MC44011, a member of the MC44000 Chroma 4 family, is
designed to provide RGB or YUV outputs from a variety of inputs. The inputs can
be composite video (two inputs), S-VHS, RGB, and color difference (R- Y, B-Y). The
composite video can be PAL and/or NTSC as the MC44011 is capable of decoding
both systems. Additionally, R-Yand B-Y outputs and inputs are provided for use
with a delay line where needed. Sync separators are provided at all video inputs.
In addition, the MC44011 provides a sampling clock output for use by a
subsequenttriple AID converter system which digitizes the RGBIYUV outputs. The
sampling clock (6.0 to 40 MHz) is phase-locked to the horizontal frequency.
Additional outputs include composite sync, vertical sync, field identification,
luma, burst gate, and horizontal frequency.
Control of the MC44011, and reading of status flags, is via an 12C bus.
• Accepts NTSC and PAL Composite Video, S-VHS, RGB, and R-Y, B-Y
• Includes Luma and Chroma Filters, Luma Delay Lines, and Sound Traps
• Digitally Controlled via 12C Bus
• R-Y, B-Y Inputs for Alternate Signal Source
• Line-Locked Sampling Clock for AID Converters
• Burst Gate, Composite Sync, Vertical Sync and Field Identification Outputs
• RGBIYUV Outputs can provide 3.0 Vp_p for AID Inputs
• Overlay Capability
• Single Power Supply: + 5.0 V, ± 5%, 550 mW (Typical)
• 44 Pin PLCC Package

SILICON MONOLITHIC
INTEGRATED CIRCUIT

FNSUFFIX
PLASTIC PACKAGE
CASE 777
(PLCC)

ORDERING INFORMATION
Device

Temperature
Range

Package

MC44011FN

0° to + 70°C

PLCC-44

Simplified Block Diagram
Outputs
VCC1

GND1

r------1r-~----o

Comp
Video 1
Comp
Video 2

Inputs

~
Y1
R·Y B-Y

,,,..--~""'---~,

R-Y

- -

1
Sound Trap/Luma
Filter/Luma
Delay/
Chroma
RHer/PAL and
NTSC Decoder/

B-Y

Y2

Fast

R G B Comm.

-I
1

~~M.~r-'-~~-T""'1J==~ ~B/u/Y}

Lr-._ _~Hu~e~a~nd~S~m~um~ti~on~~~m~ro~1-------"

Outputs

1

IS~I-+--+------r

SDL} TOI1P
SCL

i+----------Q VCC3
f----------¢ GND3

......,,='-+- To ND Converters
MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

9-182

Figure 1. MC44011 Block Diagram
Inputs

s:

0
--I
0
JJ

0
r
»
r

Z

»

PALJNTSCI5-VHS Decoder
r
------------------I
;----------,
Adaptive Sync
I

Z

Separator &
Selector

m
~

~

--+-20-k-r..
47PFI

~

=

tOM

I

IL _______
?)--- _

,---------

2

I

~--

I

0.1

~

Video Input 1 & 2 - Video 1 (Pin 1) and Video 2 (Pin 3) are
composite video inputs. Either can be NTSC or PAL. Input
impedance is high, termination must be external. Also used
for the luma and chroma components of an S-VHS signal.
Selection of these inputs is done by software. External
components protect against ESD
and noise.

ACC Filter - A 0.1 flF capacitor at this pin filters the
feedback loop of the chroma automatic gain control
amplifier. Input chroma burst amplitude can be between
30 and 600 mV p_p.

2

i 'if
L

4

_+----4-4----

+5.~10k
____ _

~

Vertical s9nc

Vertical Sync Output -An open collector output requiring
an external pull-up. Output is an active low pulse, 500 flS
wide, occurring each field. Timing of this pulse depends
on Bit $78-7.

___ _

I

_
L_-=-__
_

5
From MCU

, lOOk
11---L~

SCl - Clock for the 12C bus interface. See Appendix C for
specifications. Maximum frequency is 100 kHz.

____ _

,----;;;;-

6

SOL - Bidirectional data line for the 12C bus interface. As
an output, it is an open collector. (Write Address $8A,
Read Address $8B)

TO/FromMcu~--

i l:----)---

L_=_____ _

I~OOk

7

Field I.D.

~

Field 10- TIL level output indicating Field 1 or Field 2.
Polarity depends on state of Bit $78-7 (Vert. Sync Delay).
See Table 11 and Figure 33 and 34.

--

I

12k

I

L__

_

_

8

Burst Gate - TIL level output used for external clamps,
as well as internally. Pulse is active high, = 3.5 fls wide,
with the rising edge = 3.0 flS after center of selected
incoming sync pulse.

(Same as Pin 7)

+ 5.0

9

110k
2.2flF II
0.01

I

,--------r-I

9

I
I
I

,

~

fa.Ok

l'
20k

1

Reference Current Input - Current supplied to this pin,
typically 32 flA from + 5.0 V through a 11 0 kQ resistor,
is the reference current for the calibration circuit. Noise
filtering should be done at the pin. Voltage at this pin is
typically 1.2 V.

L

10

(See power distribution diagram at the end of this section.)

Quiet Ground - Ground for the horizontal PLL filter
(PLL#l) at Pin 11.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

9-190

MC44011
PIN FUNCTION DESCRIPTION
PinNa.

Description

Representative Circuitry

r----------

11

I
I

H Filter - Components at this pin filter the output
of the phase detector of PLL #1. This PLL becomes
phase-locked to the selected incoming horizontal sync.
External' component values are valid for NTSC and
PAL systems.

0.1

H Filter Switch - An internal switch-to-ground which permits altering the filtering action of the components
at Pin 11.

12
12
470pF T

r--+~~-..,

J..,

L--...L.1!J

L_~

_____ _

(Same as Pin 7)

16 Fh/CSync - A TTL level output from PLL #1 .
This pin provides either a square wave equal to Fh x 16
(~ 250 kHz), or composite sync, depending on the
setting of Bit $85-6.

(Same as Pin 7)

Fh Reference - A TTL square wave output which is
phase-locked to the selected incoming horizontal sync.
The rising edge occurs ~ 1.3 !is after sync center.

13

14

r---------

15

I

I
15kHz
Return

10k

15

20k

I

I

15 kHz Return - This TTL input receives the output
of an external frequency divider which is part of PLL #2
(Pixel Clock PLL). This signal will be phase and
frequency-locked to the Fh signal at Pin 14. If PLL #2
is not used, this pin should be connected to
a + 5.0 V supply,

6.0k

IL ________ _

16

r-------------I
I
I

17

(See power distribution diagram at the end of this section.)

r---------

18

I

Pixel
Clock
Output

200

I

I
I
18
I
I
IL ________ _

19
(See power distribution diagram at the end of this section.)

PLL #2 Filter - Components at this pin filter the
output of the phase detector of PLL 2. This PLL becomes
phase-locked to the Fh signal at Pin 14. Recommended
values for filter components are shown. External
components should be connected to ground at Pin 17.
I! PLL #2 is not used, this pin should be grounded.

GND 3 - Ground for the high frequency PLL #2. Signals at
Pins 15 to 19 should be referenced to this ground.
Pixel Clock Output - Sampling clock output (TTL) for
external AID converters, and for the external frequency
divider. Frequency range at this pin is 6.0 to 40 MHz.

VCC3 - A + 5.0 V supply (± 5%), for the high frequency
PLL #2. Decoupling must be provided from this pin to
Pin 17. Ripple on this pin will affect pixel clock jitter.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

9-191

MC44011
PIN FUNCTION DESCRIPTION
Pin No.

Description

Representative Circuitry

20

Color

-,

+5.0V

&~~
Brightness

+

20

-

I

Output

__________ :::--.J
21
22
23
24

RN Output - Red (in RGB mode), or R-Y (in YUV mode),
output from the color difference stage. A pull-up (390 il) to
+ 5.0 V is required. Blank level is = + 1.4 Vdc. Maximum
amplitude is = 3.0 Vp-p, black-to-white.

(Same as Pin 20)

GtV Output - Green (in RGB mode), or Y (in YUV mode),
output from the color difference stage (same as Pin 20).

(Same as Pin 20)

BtU Output - Blue (in RGB mode), or B-Y (in YUV mode),
output from the color difference stage (same as Pin 20).

(See power distribution diagram at the end of this section.)

VCC2-A + 5.0 V supply (± 5%). forthecolordifference
stage. Decoupling must be provided from this pin to Pin 24.

(See power distribution diagram at the end of this section.)

GND 2 - Ground for the color difference stage. Signals at
Pins 20 to 31 should be referenced to this pin.

~
r

25

FC - Fast Commutate switch. Taking this pin high (TTL
level) connects the RGB inputs (Pins 26 to 28) to the RGB
outputs (Pins 20 to 22), permitting an overlay function. The
switch can be disabled in software (Bit $80-7).

25

L _____

26,27,28

R,G,B
Inputs

>--l

r

29

V2
Input

>--l

J

~~~
IL ___________
~-- 1~~~kI
I

V2 Input - Luma #2!Composite sync input. This luma input to the color difference stage is used in conjunction with
auxiliary color difference inputs, and/or as a sync input.
Clamp and sync separator are provided.

J

~~r~f

I
I

29

IL ___________
lr;'-- )~O~~

r-----------

30,31

R-Y, B-Y

>--l

Inputs

Blue (26), Green (27), Red (28) Inputs - Inputs to
the color difference stage. Designed to accept standard
analog video levels, these input pins have a clamp and
sync separator. They are selected with Pin 25 or in
software (Bit $80-7).

~Vref
--

II

J

~~--

II

B-V (30), R-V (31) Inputs -Inputs to the color difference
stage. Designed for standard color difference levels, these
inputs can be capacitor coupled from the color difference
outputs, from a delay line, or an auxiliary
signal source. Input clamp is provided.

lOOk
L ___________

32

~
I

0.47

33

~

VI Clamp - A 0.47 IlF capacitor at this pin provides
clamping for the Luma #1 output.

--

32

I

-L _______

~
~

VI Output - Luma #1 output. This output from the PAU
NTSCtS-VHS decoder is the luma component of the
decoded composite video at Pin 1 or 3. It is internally directed to the color difference stage.

I

VI
Out ut
p

33

I

---

L_ _ __

34

I

System
Select

34

I

L

System Select - A multi-level DC output which indicates
the color decoding system to which the PAUNTSC
detector is set by the software. This output is used by the
MC44140 chroma delay line.

__

+

_

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

9-192

MC44011
PIN FUNCTION DESCRIPTION
Pin No.

Representative Circuitry

35

r

Description

~
t

Sandcas~e

__

Sandcastle Pulse - A multi·level timing pulse output used
by the MC44140 chroma delay line. This pulse
encompasses the horizontal sync and burst time.

35

I

Pulse

L

1-------14.3 MHz I
20~

36.38

¢

~I

~

17.7MHz

~

l

;1----

I

Xtal 2 (36), Xtal1 (38) - Designed for connection of 4x
subcarrier color crystals. Selection is done in software.
The selected frequency is used by the PAUNTSC
detector; system identifier; all notches and traps; delay
lines; and the horizontal calibration circuit.
The crystal frequency should be:
14.3 MHz at Pin 36 for NTSC,
17.7 MHz at Pin 38 for PAL.

--

R

L _______ _

R = 400 Q at Pin 38
R = 300 Q at Pin 36

(See Table 18 for crystal specs.)
No Connect - This pin is to be left open.

37
39
40

(See power distribution diagram at the end of this section.)

Ground 1 - Ground for all sections except PLL #2 and the
color difference stage.

(See power distribution diagram at the end of this section.)

VCC1 - A + 5.0 V (± 5%), supply to all sections except PLL
#2 and the color difference stage.

r

41

B-V ---1

41

I
I
I

L

42

8-Y Output - Output from the PAUNTSC decoder, it is
typically capacitor-coupled to a delay line or to the 8-Y
input. This pin is clamped, and filtered at the color
subcarrier frequency, 2x, and ax that frequency.

6-

I

-

F-

R-Y Output - Output from the PAUNTSC decoder.

(Same as Pin 41)

1---------

43

>t---

I

0.1

P

Ident Filter - A 0.1 ~F capacitor filters the system
identification circuit in the NTSC/PAL decoder.

I

h--- -

43 f-+~f---+--{V

!

L ________ _

Crystal PLL Filter - Components at this pin filter the PLL
for the crystal chroma oscillator circuit.

44

~.1
-=10,17,
19,23,
24,39,
40

2200pF

If If

VCCl
7
. 0 V U (40) 7.0V
(39,10)
----

VCC2
(24) 7.0V

(23)---

VCC3
(19)

(17)

Power Distribution - The three V CC pins must be
externally connected to + 5.0 V (± 5%) supply. The four
grounds must be externally tied together, preferably to a
ground plane.

(Dashed lines indicate substrate connection.)

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
9-193

MC44011
Luma Frequency Response (14.3 MHz) Crystal, (4.5 MHz) Sound Trap
Figure 2. Compo Video Mode

-

10

~

0

@
~
~

~F

@

""

~

"'

-10

5w -20

"
"
rl.

a:

:;::

!cc

-30

«(!)

-40

z

Figure 3. S-VHS Mode
10

'~ 000
010
r~ ,111

>- Peaking

I--

/I

0

~
~

\
\

:;::

II

!cc
z

Sound Trap = 1,1 I - -

Dl

'C

-

'"'"

-10

5~ -20

\

-30

,

\I

«

~ -40

ound rap=l,l
~II Pea~ing S~ngs

"C

1

-50

0.1

1.0

3.0

1

- 50

10

7.0

5.0

0.1

1.0

3.0

f, FREQUENCY (MHz)

1

10

7.0

5.0

f, FREQUENCY (MHz)

Luma Frequency Response (17.7 MHz) Crystal, (5.5 MHz) Sound Trap
Figure 4. Compo Video Mode
10

@
c

Figure 5. S-VHS Mode

-~

~~

""

0

r-...'\

:;:

:;:

"

~ -10

~S

-20
~
:;:: -30

- oo}-r---

~ ::"'010 .f~
111

0

"

~ -10

~
S

-20
w
a:
:;:: -30

r--

1

!cc

!cc
z

U

~ -40

Soun~ Trap 1'1,1

Dl

'C

-50
0.1

10

1.0

3.0

r---

z

~II pea~ing seVings

Dl

'C

1

- 50

10

5.0
7.0
f, FREQUENCY (MHz)

ound Trap = 1,1

\I

~ -40
0.1

1.0

3.0

1

5.0
7.0
f, FREQUENCY (MHz)

10

Luma Frequency Response (17.7 MHz) Crystal, (5.5/5.75 MHz) Sound Trap
Figure 6. Compo Video Mode
10

~

:;:

-

0

........

~,

~ -10

~
S
w

Figure 7. S-VHS Mode
10

-20

""

V"~

" OO~J-r---

~.,\V. './""" :::- 010
1111

,"

a:
:;:: -30

0

~

-10

:;:

IJ ~\

v

. Peaking

Il

~

~
S

"

-20
w
a:
:;:: -30

z

I

~ -40

sounr Trap ,1,1

z

r------

V

~ -40
~

Dl

'C

- 50
0.1

1

1.0

3.0

5.0
7.0
f, FREQUENCY (MHz)

0.1

1.0

3.0

ound rap = 0,1
~I pearing s~nings

5.0
7.0
f, FREQUENCY (MHz)

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

9-194

.......

I

-50

10

,r

I
II

!cc

!cc

1\
\

I
10

MC44011
Luma Frequency Response (17.7 MHz) Crystal, (6.0 MHz) Sound Trap
Figure 8. Compo Video Mode

~
:>

10

a:

~

'\.

~ -10

,....
11/

;:

Peaking
~'l-~
,,010
111

.

."

-50
0.1

3.0

5.0
7.0
t, FREQUENCY (MHz)

-10

:5~

-20

\

,.

\
\

I

I
II

:z

~

'"

1

-50
0.1

10

"

Sound Trap = 1,0 _
All Peaking Settings

-40

."

1
1.0

~

!;;: -30

soun~ Trap = 1,0

40

0

;:

1
1

If

:z

'"

~

/I

!;;: -30

«

,-:

'"\

-20

C!l -

-

@

...... I"\."\.
"\.'

0

~

:5w

Figure 9. S-VHS Mode

--

10

~

1.0

3.0

10

5.0
7.0
t, FREQUENCY (MHz)

Luma Frequency Response (17.7 MHz) Crystal, (6.5 MHz) Sound Trap
Figure 10. Compo Video Mode

-

10

@

0

Q

"\.

......

:>

"'-'

~

[\.

1'"'\
r\.

'\.

~ -10
~
20
~
;: -30
!;;:

!5 -

-==

JL

:sw~

'1~r-

DID . Peaking

\

1\ I
\I

a:
;: -30

"

!;;:

V

~ -40

Sound Trap ~ 0 0

'"

1

1.0

3.0

5.0
7.0
t, FREQUENCY (MHz)

10

-50
0.1

Figure 12. (3.58 MHz) Chroma Notch

:>

20

........

3.0

I

5.0
7.0
t, FREQUENCY (MHz)

10

Figure 13. (4.43 MHz) Chroma Notch

"-

r-

!;;:

:z

~ -35
."

-40
3.0

soundlTrap =11,1
14.3 MHz Crystal

.........

101
010
011
110
111

/. II'//"

~

:>

,.

/,

"\., ''/r-

-Gain at
~ -25
a:
I - - _ Peaking = 000
001
;: -30
100

'"

I
1.0

-10

-15

I- _

~

ound rap = 0,0
All Peaking Settings

."

- 50
0.1

-10

o

\

-20

:z

."

~

-,

0

:>
~ -10

111

:z
~ -40

'"

Figure 11. S-VHS Mode
10

r--...

~

ISound Trap =11,1
17.7 MHz Crystal

I"-..
............

w -20

~

/

~

'/fi ?Sf/"
'I'//" :/\. /
'1'// /
'/
'/

3.5
t, FREQUENCY (MHz)

-15

a:

E
« -30

I-Peaking = MlO

:z

~ -35

'"

."

4.0

\

-25 r-Gain at

-40
4.0

001
100
101
010
011
110
111

-%::

./

:c-

~
~
f'l'~ r~
~
~

II

V/,

V

V. . . .

/

I

"V

~

4.5

t, FREQUENCY (MHz)

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
9-195

5.0

MC44011
(4.5 MHz) Sound Trap
Figure 14. Camp. Video Mode

-

-15
~

o

UJ

e
>

-20

UJ

-25

~

;:::

5
UJ

c::

-

V

.......

"" \.

\

>=

I

t;: -35

;;:

-40

!g

~ound

Irap = 1,1

/

I

~

-20

S

-

c::

'"

'\
\

25

;;:

5.0

/

\
\ /
\/

t;: - 30

4.5

./

\

>=

V

-

.......

z

\ /

-45
4.0

~ -15

UJ

1\ /

r- Peaking = 111
r- 14'13 MHzlCrysta:

"'-

oUJ
~

./

\

30

z

C)

~

~

Figure 15. S-VHS Mode
-10

~ound lrap - 1,1
~ -35 - Peaking = 111
'C
- 14.~ MHz prystall
-40
4.0

II

v

5.0

4.5

t, FREQUENCY (MHz)

t, FREQUENCY (MHz)

(5.5 MHz) Sound Trap
Figure 16. Camp. Video Mode
- 5.0

-15
~

~

@ -20
c
:>

o

r-- r-......
.............

1\
\

c::

>= - 35
~ -40

'"

/'

...........

5w
z

1/

~

UJ

>

;;:

1\ /

C)

'"

v

5.0

.............. :-..,

"'-'\

20

'C

6.0

5.5

,/'

\

c::

>=

~

- 45

-

-

S
-25
w

L

\

r- Sound Trap =1,1
r- Peaking =111

:> -15

/

I- 17{ MHZrrystai

'C

c

/

~ -25
UJ
;:::
-30

t;:

-10

UJ

Figure 17. S-VHS Mode

-30

-35 - Sound Trap = 1,1
Peaking = 111
-40
MHz ~rystall

\

- 17I

~

V

1/
[\/

-45

5.0

6.0

5.5

t, FREQUENCY (MHz)

t, FREQUENCY (MHz)

(5.5 + 5.75 MHz) Sound Trap
Figure 18. Camp. Video Mode

Figure 19. S-VHS Mode

-10

- 5.0
~

~

o

@ -10

:>
o

:> -15

~ -15

.... -20 I - -

~

~ -25
c::

E
-30
-.:

c

~

"\

'C

- 40
5.0

\

I
/
I
I

Sound Trap = 0,1
Peaking = 111
17.7 MHz Crystal

.I
5.4

~

-25

>=

-30

c::

\

~ -35

;:;

./

:\.
\

z

'"

~ -20

V

...........

I
5.8

6.2

j

t;:

-

'"

~

'\

./~

\

/

\

\/

~ -35

/
Sound Trap = 0,1 Peaking = 111
17.7 MHz Crystal -

C)

'"
- 40
'C

-

- 45
5.0

6.6

I
5.4

5.8

t, FREQUENCY (MHz)

t, FREQUENCY (MHz)

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
9-196

6.2

i

6.6

MC44011
(6.0 MHz) Sound Trap

-fil

Figure 20. Camp. Video Mode

Figure 21. S-VHS Mode

-10

-5.0

~ -15

~ -10
:>

~

~ -20

.............

5w-25

--

r-....

a:

""

:;:
!;;: -30
z
:;;:
(!) -35

\.

,

~

/

/

I
1/

k--'"

........

,

r-....

5~ -25

\

:;: -30

!;;:
~ -35

Sound Trap = 1,0
Peaking = 111
17.7 MHz Crystal

~

./

,

/

/

6.0
f, FREQUENCY (MHz)

f, FREQUENCY (MHz)

--

Sound Trap =1,0
Peaking =111
17.7 MHz Crystal

~L

-40
-45
5.5

6.5

6.0

~

w
2: -20

I

-40
5.5

oI- -15

6.5

(6.5 MHz) Sound Trap
Figure

2~.

Camp. Video Mode

Figure 23. S-VHS Mode

-15

~

-20

-15

,

.........
:>
I'\.
~ -25

~

:5
w

-30
a:
:;: -35

./

1\

/'

\.
\.

!;;:

z

~ -40

'"

\

\

I
I
I

--

6.5

I"'....

-20

i'..

"I\..

:>
~ -25

..".,

,

\.

~

:5
w

-30
a:
:;: -35

Sound Trap = 0,0
Peaking = 111
17.7 MHz Crystal

~ -40

'"

-45
6.0

6.5
f, FREQUENCY (MHz)

Figure 24. FC Input Current

o
./

<" -20
~

~ -40

....V

(..')

!5
a.

-60

~

.:.,5 -80
-100

."

V

./

~

a:

V

./

./

V'
VCC = 5.0 \I

o

1.0

/

\ II

f, FREQUENCY (MHz)

::J

I

'C

7.0

2.0

3.0

4.0

5.0

PIN 25 VOLTAGE (V)

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

9-197

-

/'

1\

!;;:
z

Sound Trap = 0,0
Peaking = 111
17.7 MHz Crystal

'C

-45
6.0

~

7.0

MC44011
Figure 25. Horizontal PLL 1 Timing/Composite Video Inputs

Video Input
(@ Pins 1 or 3)

Burst Gate
(Pin 8)

I.- 3.1~s +- 3.5~s-l
!

1 1-

----~I----~·

+4.5V

~.--------------------------------

i
I

FhRef
(Pin 14)

1.3~s --: I..

1/2Fh

:~

----------.J-I

+4.5V

'-------

+4.5V

16 Fh Out
(Pin 13)

I-----.j
1/16Fh
, . . - - - - - - - - - - - - - - - - - - - - - - - - - +4.5V

Compo Sync
Out
(Pin 13)

(l.4~s

during vertical interval)

I

~

Sandcaslle Out
(Pin 35)

J ---L1-""
f.o--

II
I
I

5.9,~

5.0~s

1-----------------------------------------W
+30V

+1.55V

--I

I
NOTE:

In above waveforms, all timing is referenced to the center of the incoming Sync Pulse at Pin 1 or 3.
Above timings based on a 4.6 ~s wide sync pulse.
Lower two levels of Sandcastle output alternate, based on video system in effect.
All timings are nominal, and apply to both PAL and NTSC Signals.

Figure 26. Horizontal PLL 1 Noise Gate and Filter Pin

Video Input
(@ Pins 1 or 3)

NOise Gate
Charge Pump Current
(Pin 11)
Voltage Waveform
(Pin 11)

----~---------------~ - - - - - - - - - . { 700 mVp-p with High Gain

-----"

~

=----..t

250 mVp-p with Low Gain

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

9-198

MC44011
Figure 27. Horizontal PLL1 Timing/R, G, Band Y2 Inputs

Video Inpul
(@Pins26to
29)

1..2.5~S-+- 3.5~s-.j
I

(PinS)

+4.5V

~I________________

--~i~1

Bursl Gale

I
I

Fh ReI
(Pin 14)

650ns

4

----------+l-IL-______
+4.5V

1
.....- - - - - -

1/2Fh

i~

-

+4.5V

16Fh Oul
(Pin 13)

I----+l
1/16Fh

Compo

r-------------------------

Sync
Oul

(1.4~s

(Pin 13)

+4.5V

during vertical interval)

I

~

J -L1-""
II
I
I

Sandcaslle Oul
(Pin 35)

t-- 5.9.~s

5.0~s

-

+30V

C---------------------------------------

--I

I
I
I
I
I
I
I

R, G, B Oulpuls
(@ Pins 20 10 22)

NOTE:

In above waveforms, all timing is referenced to the center of the incoming Sync Pulse at Pin 26 to 28, or 29.
Above timings based on a 4.6 ~s wide sync pulse.
Lower two levels of Sandcastle output alternate, based on video system in effect.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
9-199

+1.55V

OV

MC44011
Figure 28. System TiminglVideo Inputs to RGB Outputs

Video Input
(@ Pins 1 or 3)

R·Y, B·Y Outputs
(@Pins41,42)

R, G, B, Outputs
(@ Pins 20 to 22)

Figure 29. Fast Commutate Timing

~o"

Input @Pin 25

90ns

R, G, B, Outputs
(@ Pins 20 to 22)
50%

Color Differ·
ence
Inputs Enabled

RGB Inputs
Enabled

Color Difference
Inputs Enabled

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
9·200

MC44011
Figure 30. Horizontal Outputs versus Fields (NTSC System)

Field 2

Field 1

Composite Input
(@ Pins 1, 3, 26 to 29)

FhRel
(Pin 14)

Burst Gate
(PinS)
1
1
1

Composite Sync
(Pin 13)

--, r---l

U

~Ir

U

m
1
1

1 ______________________________ _
____________ L

Field 1 : Field 2
ComposHe Input
(@ Pins 1, 3, 26 to 29)

.1

FhRel
(Pin 14)
Burst Gate
(PinS)

Composite Sync
(Pin 13)

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
9-201

MC44011
Figure 31. Horizontal Outputs versus Fields (PAL System)

Unel

Composite Input
(@ Pins 1, 3, 26 to 29)

.

Field 214

I
I
I
I

Field 1/3

Fh Ref
(Pin 14)

Burst Gate
(Pin 8)

Composite Sync
(Pin 13)

IL---_JL_--',_" '-----'
I
I
I

L_'U

---------------~---------------------... Field 1/3 i Field 2/4 •
Composite Input

I

(@ Pins 1, 3, 26 to 29)

Fh Ref
(Pin 14)

Burst Gate
(Pin 8)

Composite Sync
(Pin 13)

Figure 32. Horizontal PLL2 Timing

Determined by
t - - - - External Circu~ - - - - t
(Must be > 200ns)

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

9-202

MC44011
Figure 33_ Vertical Timing (NTSC System)

A) Bit $78-7 = 0

Une 1

Video Input
Vert_ Sync Out
(Pin 4)
Field 2

Field Ident Out
(Pin 7)

I

Field 1

I--- 500!lS - - l

----1----.
I
I
I
I
I

----------1----------------------I

Video Input

--J 36!lSi--

I
Vert_ Sync Out
(Pin 4)

Field 1

I

----I
I
Field Ident Out
(Pin 7)

Field 2

I.

:

..

:

:

I

--l

I.

I--- 500!lS ---I

I
I

68115

I
I--

-----------~---------------------------------------------------------Une 1
B) Bft $78-7 = 1

Video Input

Vert_ Sync Out
(Pin 4)

_-F-ie-ld-2 : _Fi_eld_l_ _
..

Field Ident. Out
(Pin 7)

I
I
I
I
I

:

I

r--

I-- 500!lS --l

I
I
I
I

----------1----------------------I

Video Input
Vert_ Sync Out
(Pin 4)
Field Ident. Out
(Pin 7)

..

Field 1

Field 2

:r--

l44lls

--iI~----------

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

9-203

MC44011
Figure 34. Vertical Timing (PAL System)
Unel
I
I

A) Bit $78-7 = 0

Video Input

I

Vert. Sync Out
(Pin 4)

---'

36115~

I

, - I_ _ _ _- - '

I - - 500115 --I

I

..

Field 2/4

Field Ident.
Out
(Pin 7)

I Field 1/3

•

I
I
1- 110115-1
I

--------------------r-------------I

Video Input

--J

Vert. Sync Out
(Pin 4)

36115~

I I
I

..
Field Ident.
Out
(Pin 7)

Field 1/3

I

I - - 500115 --I

I Field 2/4
I
I

..

1- 68115+1
I

===================================
Unel

B) Bit $78·7 = 1

Video Input
Vert. Sync Out
(Pin 4)

I

..

I

~

I

I--- 500115--1

..

Field 2/4 I Field 1/3

I --1I
I
--------------------1-------------I

Field Ident. Out
(Pin 7)

/","- 100115

Video Input

Vert. Sync Out
(Pin 4)

Field Ident. Out
(Pin 7)

I

..

I

Field 1/3 I Field 2/4

I

I

I

I--- 500115---+\

..

~I_________

I-- 144115----1

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
9-204

MC44011
FUNCTIONAL DESCRIPTION
Introduction
The MC44011, a member of the MC44000 Chroma 4
family, is a composite video decoder which has been tailored
for applications involving multimedia, picture-in-picture, and
frame storage (although not limited to those applications).
The first stage of the MC44011 provides color difference
signals (R-Y, B-Y, and Y) from one of two (selectable)
composite video inputs, which are designed to receive PAL,
NTSC, and S-VHS (Y,C) signals. The second stage provides
either RGB or YUV outputs from the first stage's signals, or
from a separate (internally selectable) set of RGB inputs,
permitting an overlay function to be performed. Adjustments
can be made to saturation; hue; brightness; contrast;
brightness balance; contrast balance; U and V bias;
subcarrier phase; and color difference gain ratio.
The above mentioned video decoding sections provide
the necessary luma/delay function, as well as all necessary
filters for sound traps, luma/chroma separation, luma
peaking, and subcarrier rejection. External tank circuits and
luma delay lines are not needed. For PAL applications, the
MC44140 chroma delay line provides the necessary
line-by-line corrections to the color difference signals
required by that system.
The MC44011 provides a pixel clock to set the sampling
rate of external AID converters. This pixel clock, and other
horizontal frequency related output signals, are phase-locked

to the incoming sync. The VCO's gain is adjustable for
optimum performance. The MC44011 also provides vertical
sync and field identification (Field 1, Field 2) outputs.
Selection of the various inputs, outputs, and functions, as
well as the adjustments, is done by means of a two-wire 12C
interface. The basic procedure requires the microprocessor
system to read the internal flags of the MC44011, and then
set the internal registers appropriately. This 12C interface
eliminates the need for manual controls (potentiometers) and
external switches. All of the external components for the
MC44011, except for the two crystals, are standard value
resistors and capacitors, and can be non-precision.
(The DACs mentioned in the following description are 6-bits wide.
The settings mentioned for them are given in decimal values of 00 to
63. These are not hex values.)

PAUNTSC/S-VHS Decoder
A block diagram of this decoder section is shown in
Figure 35. This section's function is to take the incoming
composite video (at Pins 1 or 3), separate it into luma and
chroma information, determine if the signal is PAL or NTSC
(for the flags), and then provide color difference and luma
signals at the outputs. If the input is S-VHS, the
luma/chroma separation is bypassed, but the other functions
are still in effect.

Figure 35. PAUNTSC/S-YHS Decoder Block Diagram

Camp.
Video 1
Camp.
Video 2
Ident

R-YOut
Saturation ($87-510)
Hue ($88-510)
Color Balance ($78-5/0)
Blanking

Crystal Select

IS7A-7)

B-YOut

3.617.2/28.6/4.4/
8.8/35.4 MHz
Notch

Switches shown with control bits = o.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
9-205

MC44011
Inputs
The inputs at Pins 1 and 3 are high impedance inputs
designed to accept standard 1.0 Vp-p positive video
signals (with negative going sync). The inputs are to be
capacitor-coupled so as not to upset the internal DC bias.
When normal composite video is applied, the desired
input is selected by Bit $88-7. Bits $77-6 and $77-7 must
be set to 0 so that their switches are as shown in Figure
3S. The selected signal passes through the sound trap,
and is then separated by the chroma trap and the chroma
(high pass) filter.
When S-VHS signals (Y,C) are applied to the two inputs, Bit
$88-7 is used to direct the luma information to the sound trap,
and the chroma information to the ACC circuit (Bit $77-6 must
be set to a Logic 1). Bit $77-7 is normally set to a Logic 1 in
this mode to bypass the first luma delay line and the chroma
trap, but it can be left 0 if the additional delay is desired.
Sound Trap
The sound trap will filter out any residual sound subcarrier
at the frequency selected by control bits T1 and T2 according
to Table 3. The accuracy of the notch frequency is directly
related to the selected crystal frequency.
Table 3. Sound Trap Frequency
Crystal
Frequency

T1
($7B-7)

T1
($7B-6)

17.73 MHZ

0

0

6.5 MHz

17.73 MHZ

0

1

5.5 + 5.75 MHz

1

0

6.0 MHz

1

1

5.5 MHz

14.32 MHz

0

0

5.25 MHz

14.32 MHz

0

1

4.44 + 4.64 MHz

1

0

4.B4MHz

1

1

4.44 MHz

17.73 MHZ

14.32 MHz

Notch
Frequency

Code 01 (for T1, T2) is used to widen the band rejection
where stereo is in use. Typical rejection is 30 dB.
ACC and PAL/NTSC Decoder
The chroma filter bandpass characteristics (3.S8 or
4.43 MHz) is determined by the selected crystal. The output
of the chroma filter is sent to the ACC circuit which detects the
burst signal, and provides automatic gain control once the
crystal oscillator has achieved phase lock-up to the burst.
The DC voltage at Pin 2 is ~1.S to 2.0 V. This will occur if the
burst amplitude exceeds 30 mVp-p, and if the correct crystal
is selected (Bit $7A-7). A 17.734472 MHz crystal is required
for PAL, and a 14.31818 MHz crystal is required for NTSC.
When Flag 23 is high, it indicates that the crystal's PLL has
locked up, and the ACC circuit is active, providing automatic
gain control. A small amount of phase adjustment (~ ± SO) of
the crystal PLL, for color correction, can be made with control
DAC $79-S/0. Pin 2 is the filter for the ACC loop, and Pin 44 is
the filter for the crystal oscillator PLL.

The PAUNTSC decoder then determines if the signal is
PAL or NTSC by looking for the alternating phase
characteristic of the PAL burst. When Flag 24 is high, PAL
has been detected. Bits SSA, SSB, SSC, and SSD (Table 4)
must then be sent to the decoder to set the appropriate
decoding method.
Table 4. Color System Select
SSA
($7C-6)

SSB
($70-6)

SSC
($7C-7)

SSO
($7A-6)

Color
System

0

0

0

0

Not Used

0

1

0

0

PAL

1

0

0

0

NTSC

1

1

0

0

Color Kill

X

X

1

0

Extemal

Upon receiving the SSA to SSD bits, the decoder provides
the correct color difference signals, and with the Identification
Circuit, provides the correct level at the System Select output
(Pin 34). This output is used by the MC44140 delay line.
The color kill setting (SSA = SSB = 1) should be used
when the ACC flag is 0, when the color system cannot be
properly determined, or when it is desired to have a
black-and-white output (the ACC circuit and flag will still
function if the input signal has a burst signal). The "External"
setting (SSC = 1) is used when an external (alternate)
source of color difference signals are applied to the
MC44140 delay line. (See Miscellaneous Applications
Information for more details.)
Color Difference Controls and Outputs
The color difference Signals (R-Y, B-Y) from the PAUNTSC
decoder are directed to the saturation, hue and color balance
controls, and then through a series of notch filters before
being output at Pins 41 and 42. Blanking and clamping are
applied to these outputs.
The saturation control DAC($87-S/0) varies the amplitude
of the two signals from 0 Vp-p (DAC setting = 00), to a
maximum of ~1.8 Vp-p (at a DAC setting of 63). The
maximum amplitude (without clipping) is ~1.S Vp-p, but a
nominal setting is ~1.3 Vp-p at a DAC setting of 1S.
The hue control ($88-S/0) varies the relative amplitude of
the two signals to provide a hue adjustment. The nominal
setting for this DAC is 32.
The color balance control ($78-S/0) provides a fine
adjustment of the relative amplitude of the two outputs. This
provides for a more accurate color setting, particularly when
NTSC Signals are decoded. The nominal setting for this
DAC is 32, and should be adjusted before the hue control
is adjusted.
The notch filters provide filtering at the color burst
frequency, and at 2x and 8x that frequency. Additionally,
blanking and clamping (derived from the horizontal PLL) are
applied to the signals at this stage. The nominal output DC
level is ~ 2.0 to 2.S Vdc, and the load applied to these outputs
should be > 10 kf.!. Sync is not present on these outputs.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

9-206

MC44011
Luma Peaking, Delay Line, and Y1 Output
When composite video is applied, the luma information
extracted in the chroma trap is then applied to a stage which
allows peaking at z 3.0 MHz with the 17.7 MHz crystal (z 2.2
MHz with the 14.3 MHz crystal). The amount of peaking at
Y1 is with respect to the gain at the minimum peaking value
(P1, P2, P3 = 111), and is adjustable with Bits $70-7, and
$7E-7,6 according to Table 5.
The luma delay lines allow for adjustment of that delay so
as to correspond to the chroma delay through this section.
Table 6 indicates the amount of delay using the 01-03 bits
($7F-7,6, and $80-6). The delay indicated is the total delay
from Pin 1 or 3 to the Y1 output at Pin 33. The amount of
delay depends on whether Composite Video is applied, or YC
signals (S-VHS) are applied.
The output impedance at Y1 is z 300 0, and the black level
clamp is at z + 1.1 V. Sync is present on this output. Y1 is also
internally routed to the color difference stage.

Table 5. Luma Peaking
P1
($70-7)

P2
($7E-6)

P3
($7E-7)

Y1
Peaking

0

0

0

+ 9.5 dB

0

0

1

+ 8.5

1

0

0

+ 7.7

1

0

1

+6.5

0

1

0

+ 5.3

0

1

1

+3.8

1

1

0

+2.2

1

1

1

0

17.7 MHz Crystal. 6.5 MHz Sound Trap. Comp. Video Mode

Table 6. Luma Delay
14.3 MHz Crystal
01
($7F-6)

02

17.7 MHz Crystal

($80-6)

03
($7F-7)

Camp. Video
($77-7 = 0)

S-VHS
($77-7= 1)

Camp. Video
($77-7=0)

S-VHS
($77-7= 1)

0

0

0

690 ns

395ns

594 ns

350 ns

0

0

1

760

465

650

406

0

1

0

830

535

707

463

0

1

1

900

605

763

519

1

0

0

970

675

819

575

1

0

1

1040

745

876

632

1

1

0

970

675

819

575

1

1

1

1040

745

876

632

Color Difference Stage and RGB/YUV Outputs
A block diagram of this section is shown in Figure 36. This
section's function is to take the color difference input signals
(Pins 30,31), or the RGB inputs (Pins 26 to 28), and output
the information at Pins 20 to 22 as either RGB or YUV.
The inputs (on the left side of Figure 36) are analog RGB,
or color difference signals (R-Y and B-Y) with Y1 or Y2 as the
luma component. Pin 25 (Fast Commutate) is a logic level

input, used in conjunction with RGB EN (Bit $80-7), to select
the RGB inputs or the color difference inputs. The outputs
(Pins 20 to 22) are either RGB or YUV, selected with
Bit $82-7. The bit numbers adjacent to the various switches
and gates indicate the bits used to control those functions.
Table 7 indicates the modes of operation.

Table 7. Color Difference Input/Output Selection
FC

RGBEN
$80-7

YXEN
$82-6

YUVEN
$82-7

1

0

0

0

RGB inputs, RGB outputs, no saturation control

1

0

1

0

RGB inputs, RGB outputs, with saturation control

1

0

1

1

RGB inputs, YUV outputs, with saturation control

1

0

0

1

Not usable

FC Low and/or
RGB EN Hi

X

0

R-Y, B-Y inputs, RGB outputs. Yl or V2 must be selected

FC Low and/or
RGB EN Hi

X

1

R· V, B-V inputs, VUV outputs. VI or V2 must be selected

Function

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

9-207

-

MC44011
In addition to Table 7, the following guidelines apply:
a) To select the RGB inputs, both FC must be high and
RGB EN must be low. Therefore, the RGB inputs can
be selected either by the 12C bus by leaving FC
permanently high, or by the FC input by leaving
Bit $80-7 permanently low. For overlay functions,
where high speed, well controlled switching is
necessary, the FC pin must be the controlling input.
b) When the R-Y, B-Y inputs are selected, either Y1 or Y2
must be selected, and the other must be deselected.
The YX input is automatically disabled in this mode.
c) In applications where the color difference inputs are

obtained from the NTSC/PAL decoder (from a
composite video signal), Y1 is used. The Y2 input is
normally used where alternately sourced color
difference signals are applied, either through the
MC44140 delay line, or through other external
switching to Pins 30 and 31.
In Figure 36, the bit numbers followed by "- 0/5" indicate
DAC operated controls (contrast, brightness, etc.), which are
controlled by the 12C bus. The DACs have 6-bit resolution,
allowing 64 adjustment steps. Table 8 provides guidelines on
the DAC operation.

Table 8. DAC Operation - Color Difference Section

=0)

=1)

Function

Bits

Brightness

$84-0/5

Affects DC black and maximum levels of the three
outputs, but not the clamp level, nor the amplitude.

Affects DC black and white levels of the Y output
only, but not the clamp level, nor the amplitude.

d DC- Red
dOC-Blue

$85-0/5
$83-0/5

Fine tune the Red and Blue brightness levels.

Allows a small amount of color tint control (not to be
confused with hue).

Contrast

$81-0/5

Provides gain adjustment (black-to-white) of the
three outputs.

Provides gain adjustment of the three outputs.

dGain-Red
dGain-Blue

$82-0/5
$80-0/5

Fine tune the Red and Blue contrast levels.

Fine tune of the U and V gain levels.

VDC
U DC

$7E-0/5
$70-0/5

Must be set to 00.

Should nominally be set to 32. This sets the DC
level of the U and V outputs at = mid-scale.

Main Saturation

$86-0/5

Affects color saturation, except when the RGB inputs bypass this section (YX EN = 0).

Affects color saturation levels of the UV outputs.
Does not affect the Y output.

RGB Outputs ($82-7

YUV Outputs ($82-7

Figure 36. Color Difference Stage and Outputs

Inputs

Contrast

{:~
B~
I
I
I

$81·0/5

Brightness

$82-0/5

B-Y

+5.0

Main Saturation

Matrix
Decoder

YX

$84·0/5
$82·7

$86-0/5
R-Y

I
I
I

R-Y

Outputs

$
I

B-Y
Y2

Y

FIC

NOTES: 1. []] = Clamp Circuit
2. Switches controlled by
12C Interface - See Text.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

9-208

MC44011
The RGB and Y2 inputs are designed to accept standard
1.0 Vp-p analog video signals. They are not designed for TIL
level signals. The color difference inputs are designed to
accept signals ranging up to 1.8 Vp-p. All signals are to be
capacitor-coupled as clamping is provided internally. Input
impedance at these six pins is high.
For applications involving externally supplied color
difference signals, sync can be supplied on the luma input
(Y2), or it can be supplied separately at the RGB inputs.
Where the color difference signals are obtained from the
NTSC/PAL decoder, sync is provided to this section on the
internal Yl signal. See Sync Separator section for more
details on injecting sync into the MC44011.
Sync is present on all three outputs in the RGB mode, and
on the Y output only (Pin 21) in the YUV mode.
The Fast Commutate input (FC, Pin 25) is a logic level
input with a threshold at z 0.5 V. Input impedance is
z 67 kil, and the graph of Figure 24 shows the input current
requirements. Propagation delay from the FC pin to the
RGBIYUV outputs is z 50 ns when enabling the RGB inputs,
and z 90 ns when disabling the inputs. (See Figure 29 Fast
Commutate Timing diagram.) If Pin 25 is open, that is
equivalent to a Logic 1, although good design practices
dictate that inputs should never be left open. The voltage on
this pin should not be allowed to go more the 0.5 V above
VCC2 or below ground.
The three outputs (Pins 20 to 22) are open-collector,
requiring an external pUll-Up. A representative schematic is
shown in Figure 37.
The output amplitude can be varied from 100 mVp-p to
3.0 Vp-p by use of the contrast and saturation controls. Any
output load to ground should be kept larger than 1.0 kil. In
the RGB mode, OACs $70 and $7E should be set to 00,
which results in clamping levels of z + 1.4 Vdc. In the YUV
mode, OACs $70 and $7E should be set to 00, which results

Figure 37. Output Stage
Coler or
ColorDiff
Contrast
dGain

390
L-_-""'~--1>--(J-<>--_

in clamping levels of z + 1.4 Vdc. In the YUV mode, the OACs
should be set to 32 to bias the U and V outputs to z +2.3 V.
The Y output clamp will remain at z + 1.4 V in the YUV mode.
Horizontal PLL (PLL1)
PLL 1 (shown in Figure 38) provides several outputs which
are phase-locked to the incoming horizontal sync. In normal
operation, the two switches at the left side of Figure 38 are as
shown, and (usually) the transistor at Pin 12 is off.
The phase detector compares the incoming sync (from the
sync separator) to the frequency from the + 64 block. The
phase detector's output, filtered at Pin 11, controls the VCO
to set the correct frequency (zl.0 MHz) so that the output of
the + 64 is equal to the incoming horizontal frequency.
The line-locked outputs are:
1) Fh Ref (Pin 14) - A square wave, TIL levels, at the
horizontal frequency, and phase-locked to the sync
source according to the timing diagram of Figures 25
and 27.
2) Burst Gate (Pin 8) - This is a positive going pulse, TIL
levels, coincident with the burst signal. See the timing
diagram of Figures 25 and 27.

Figure 38. Horizontal PLL (PLL1)

fot-_ _ _ _+--.-'H'-'-_ _ _ _ _ _ To PLL #2
Heriz. Sync
from Sync
Separator

L1 Gain

$83·6

Ref
Switch

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

9-209

Output

MC44011
3) Sandcastle Output (Pin 35) - This is a multilevel
output, at the horizontal frequency, used by the
MC44140 delay line. See the timing diagram of Figures
25 and 27.
4) 16Fh/CSync (Pin 13) - This is a dual purpose output,
TTL levels, user selectable. When Bit $85-6 is set to 0,
Pin 13 is a square wave at 16x the horizontal frequency
(250 kHz for PAL, = 252 kHz for NTSC). When
Bit $85-6 is set to 1, Pin 13 is negative composite sync,
derived from the internal sync separator. See the timing
diagram of Figures 25 and 27.
The first three outputs mentioned above, and Pin 13 when
set to 16 Fh, are consistent, and do not change duty cycle or
wave shape during the vertical sync interval. These four
outputs will also be present regardless of the presence of a
video signal at the selected input.
When Pin 13 is set to CS ync output, it follows the incoming
composite sync format. If there is no video signal present at
the selected input, this output will be a steady logic high.
Loading on these pins should not be less than 2.0 k.Q to
either ground or + 5.0 V.
Pin 11 is the filter for the PLL, and requires the components
shown in Figure 38, and with the values shown in the
application circuit of Figure 42. Pin 12 is a switch which allows
the filtering characteristics at Pin 11 to be changed. Switching
in the additional components (set $84-7 =1) increases the
filter time constant, permitting better performance in the
presence of noisy signals.
The gain of the phase detector may be set high or low,
depending on the jitter content of the incoming horizontal
frequency, by using Bit $83-6. Broadcast signals usually
have a very stable horizontal frequency, in which case the
low gain setting ($83-6 = 0) should be used. When the video
source is, for example, a VCR, the high gain setting may be
preferable to minimize instability artifacts which may show
up on the screen.
The gating function ($77-2) provides additional control
where the stability of the incoming horizontal frequency is in
question. With this bit set to 0, gating is in effect, causing the
phase detector to not respond to the incoming sync pulses
during the vertical interval. This reduces disturbances in this
PLL due to the half-line pulses and their change in polarity.
The gating may be disabled by setting this bit to 1 where the
timing of the incoming sync is known to be stable. The gating
cannot be enabled if the phase detector gain is set high
($83-6 = 1).

the D-to-A converter to drive the VCO through switch Sc. The
resulting frequency at the output of the divide-by-64 block is
then fed to the frequency comparator to complete the loop.
When a sync signal is not present at Phase Detector #1,
and at the Coincidence Detector, as indicated by the
coincidence detector's output (Flag 12), Bit $78-6 should be
set to o. This will cause the switch (Sc) to transfer to the
D-to-A converter for two lines (lines 4, 5) in each vertical field,
and will maintain the PLL 1 at a frequency near the standard
horizontal frequency (between 14 to 16 kHz). When lock to an
incoming sync is established, Bit $78-6 may be set to 1,
disabling the periodic recalibration function, or it may be left
settoO.
If a more accurate horizontal frequency is desired in the
absence of an input signal, Bit $86-6. can be set to 1 (and
Bit $84-6 set according to Table 9). This holds the horizontal
frequency to = 15.7 kHz. In this mode, Flag 12 will stay 0, as
the PLL will not be able to lock-up to a newly applied external
signal. To reset the system, set $86-6 to 0, write $00 to
register $00, and then check Flag 12 to determine when the
loop locks to an incoming signal.
Table 9. Calibration Loop
Crystal

Set Bit $84-6 to

14.3 MHz

1

17.7 MHz

0

On initial power up, Bit $86-6 (PLL 1 EN) is automatically
set to 1, engaging the calibration loop continuously. This
condition will remain until this bit is set to 0, and $00 is written
to register $00, as part of the initialization routine.
Pixel Clock PLL (PLL2)
The second PLL, depicted in Figure 39, generates a high
frequency clock which is phase-locked to the horizontal
frequency.
Figure 39. Pixel Clock PLL (PLL2)
Flag 19 (Veo HI)
L....;=T=--~-Flag 20 (VCO LO)

Calibration Loop
The calibration loop (upper left portion of Figure 38)
maintains a near correct frequency of this PLL in the absence
of incoming sync signals. This feature minimizes
re-adjustment and lock time when sync signals are
re-applied. The calibration loop is similar to the PLL function,
receiving one frequency from the crystal (either 4.43 MHz or
3.58 MHz) divided down to a frequency similar to the
standard horizontal frequency. Bit $84-6 is used to set the
frequency divider to the correct ratio, depending on which
crystal is selected (see Table 9). The output of the frequency
comparator operates an up/down counter, which in turn sets

15625Hzor
15750Hz

MOTOROLA·LlNEAR/INTERFACE ICs DEVICE DATA

9-210

MC44011
The phase and frequency comparator receive inputs from
PLL 1 (fH, the horizontal frequency). and the frequency
returned from the external divider. Any difference between
these two signals causes the Up or Down output to change
the charge pump's timing. The charge pump output is
composed of two equal current sources which alternately
source and sink current to the filter at Pin 16. The voltage at
Pin 16 (which is the input to the VCO) is therefore determined
by the relative timing of those two current sources, and the
filter characteristics. A coarse control of the loop gain is set
with Bit $83-7. Low gain is obtained by setting this bit to ai,
which sets the charge pump's output current sources to
~ ± 20 ~A. Setting this bit to 0 sets the current sources to
~ ± 50 ~A, or high gain.
Depending on the output frequency desired, and whether
or not a 50-50 square wave is needed at the pixel clock, the
+2 may be engaged (Bit $85-7). Generally, the + 2 should not
be engaged for high frequencies, and should be engaged for
low frequencies, so as to keep the VCO's input voltage in a
comfortable range (between 1.7 and 3.3 V). If the input
voltage is outside this range, Flag 19 or 20 will switch high,
indicating the need to fine tune the VCO's gain (control DAC
$7F). The usable adjustment range for this DAC is 00 to ~ 50.
Settings of 51 to 62 will generally produce non-square wave
outputs, and can be unstable. A setting of 63 will shut off the
VCO, which should be done if the pixel clock is not used.
When not used, Pin 18 will be at a constant low level.
The pixel clock frequency is equal to the horizontal
frequency (fH) x the frequency divider ratio. The frequency
divider can be made up of programmable counters (e.g.
MC74F161 A Applications Information), or it can be integrated
into another device (e.g., an ASIC). The returned signal to Pin
15 must be TTUCMOS logic levels, and must have a low time
of> 200 ns. The phase comparator will phase-lock the falling
edge of the returned signal with the rising edge of the fH
signal at Pin 14 (see Figure 32).
Vertical Decoder
The vertical decoder section, depicted in Figure 40,
provides a vertical sync pulse and a field identification signal,
as well as flags which indicate if vertical lockup has occurred,
and if the number of horizontal lines per frame is greater or
less than 576.
Inputs to this section consists of the composite sync from
the sync separator, and horizontal related signals from the
horizontal PLL (PLL 1).
Figure 40. Vertical Decoder

L -_ _ _

2Fh

r--7:""7-;;---,--_ Compo
Sync
L--=<=,,---~-16Fh

The sync output (Pin 4) is an active low signal which starts
after the horizontal half-line sync pulses change polarity (see
Figures 33 and 34). The pulse width is nominally 500 ~s for
both PAL and NTSC signals. The position of this sync pulse's
leading edge can be altered slightly with Bit $78-7, but this
does not change the pulse width. Since the pulse width is
generated digitally by counters, it will not vary with
temperature, supply voltage, or manufacturing distribution.
The sync output is an open-collector NPN output, requiring
an external pull-up resistor. Minimum value for the pull-up is
1.0 kQ, with 10 kQ recommended for most applications.
Flag 14 « 576 lines) is derived from the counter which
compares the number of horizontal lines in each frame with a
preset value of 576. This flag can be used externally to help
determine whether PAL or NTSC signals are being provided
to the MC44011. Flag 15 (Vertical countdown engaged)
indicates that the vertical decoder has locked-up to the
incoming composite sync information for eight consecutive
fields (CB1, CAl = 11).
The operation of the vertical decoder is controlled by Bits
$77-0 and $77-1, according to Table 10.
Table 10. Vertical Decoder Mode
CB1 ($77-1)

CA1 ($77·0)

Vertical Sync Mode

0

0

Force 625

1

0

Force 525

0

1

Injection Lock

1

1

Auto-Count

The Injection Lock mode has a quicker response time, but
less noise immunity, than the Auto-Count mode, and is
normally used when attempting to lock-up to a new signal
(such as when changing video input selection). Flag 15 will
not switch high when in this mode. The Auto-Count mode,
having a higher noise immunity, should be set once the
horizontal PLL is locked-up (by reading Flag 12), and then
Flag 15 should be checked after 8 fields for vertical lock-up.
The modes designated Force 525 and Force 625 can be
used for those cases where it is desired to force the vertical
sync pulse to occur twice every 525 or 625 lines, regardless
of the incoming signal. In either of these modes, the
MC44011 's vertical section will not lock-up to the vertical sync
information contained in the incoming composite video
signal. If there is no incoming video signal, the vertical sync
will still occur every 525 or 625 lines generated by the
horizontal PLL. Flag 14 will indicate the number of lines
selected, and Flag 15 will be a steady high.
Bit $77-5 (FSI) is used only in the PAL mode to select the
vertical sync output rate. With this bit set to 0, the vertical sync
pulses will be synchronized with the composite vertical sync
input (every 20 ms). With this bit set to 1, the MC44011 will
add a second vertical output sync pulse 10 ms after the
one occurring at the vertical interval, giving a vertical sync
rate of 100 Hz.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

9-211

MC44011
The Field ID output (Pin 7) indicates which field is being
processed when interlaced signals are applied, but the
polarity depends on Bit $78-7. Table 11 indicates Pin 7
output. When non-interlaced signals are being processed,
Pin 7 will be a constant high level when $78-7 is set to 1 , and
will be a constant low level when $78-7 is set to a O. Loading
on Pin 7 should not be less than 2.0 kQ to either ground or
+ 5.0 V. Figures 33 and 34 indicate the timing.

Table 12. Sync Source
VinSync
($86-7)

Y2Sync
($87-7)

RGBSync
($88-6)

0

0

0

0

0

1

RGB (Pins 26 - 28)

0

1

0

Y2 (Pin 29)

1

X

X

Camp. Video (Pins 1, 3)

Sync Source
None

Table 11. Field 10 Output
Field

FieldlD
(Pin 7)

1

1

High

1

2

Low

36/68115
($78-7)

0

1

Low

0

2

High

Setting Bit $86-7 to a 1 overrides the other bits, thereby
deriving the sync from the composite video input (either Pin 1
or 3) selected by Bit $88-7.
When RGB is selected, sync information on Pins 26 to 28
is used. Sync may be applied to all three inputs, or to anyone
with the other two AC grounded. If RGB signals are applied to
these pins, sync may be present on anyone or all three.
When Y2 is selected, sync information on Pin 29 is used.
The sync amplitude applied to any of the above pins must be
greater than 100 mY, and it must be capacitor coupled.
This system allows a certain amount of flexibility in using
the MC44011, in that if the sync information is not present as
part of the applied video signals, sync may be applied to
another input. In other words, the input selected for the sync
information need not be the same as the input selected for
the video information.

Sync Separator
The sync separator block provides composite sync
information to the horizontal PLL, and to various other blocks
within the MC44011 from one of several sources. It also
provides composite sync output at Pin 13 when Bit $85-6 = 1.
The sync source is selectable via the 12C bus according to
Table 12.

SOFTWARE CONTROL OF THE MC44011
12C Interface
Communication to and from the MC44011 follows the 12C
interface arrangement and protocol defined by Phillips
Corporation. In simple terms, 12C is a two line, multimaster
bidirectional bus for data transfer. See Appendix C for a

description of the 12C requirements and operation. Although
an 12C system can be multimaster, the MC44011 never
functions as a master.

Figure 41. 12C Bus Interface and Decoder

Clock
Chip
Address
Latch

Data

Readl
Write
Latch

Sub-Address
Latches

19 Registers

Flag Data

The MC44011 has a write address of $8A, and a flag read
address of $88. It requires that an external microprocessor
read the internal flags, and then set the appropriate registers.
The MC44011 does not do any automatic internal switching
when applied video Signals are changed. A block diagram of

the 12C interface is shown in Figure 41. Since writing to the
MC44011 's registers can momentarily create jitter and other
undesirable artifacts on the screen, writing should be done
only during vertical retrace (before line 20). Reading of flags,
however, can be done anytime.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

9-212

MC44011
Write to Control Registers
Writing should be done only during vertical retrace. A write
cycle consists of three bytes (with three acknowledge bits);
1. The first byte is always the write address for the
MC44011 ($8A).
2. The second byte defines the sub-address register
(within the MC44011) to be operated on ($77 through
$88, and $00).
3. The third byte is the data for that register.

generated by the MC44011, which tells the master to continue
the communication. The second byte is then entered,
followed by an acknowledge. The third byte is the operative
data which is directed to the designated register, followed by
a third acknowledge.
Sub-Address Registers
The sub-addresses of the 19 registers are at $77 through
$88, and $00. 14 of the registers use Bits 0-5 to operate
DACs which provide the analog adjustments. Most of the
other bits are used to set/reset functions, and to select
appropriate inputs/outputs. Table 13 indicates the
assignments of the registers.

Communication begins when a start bit (data taken low
while clock is high), initiated by the master, is detected,
generating an internal reset. The first byte is then entered,
and if the address is correct ($8A) , an acknowledge is

Table 13. Sub-Address Register Assignments
Sub
Address

7

6

5

$77

S-VHS Y

S-VHS C

FSI

$78

36/38 !is

Cal Kill

(R-Y)/(B-Y) adjust DAC

$79

HI

VI

Subcarrier balance DAC

$7A

Xtal

SSD

I
I

4
L2GATE

I
I

$7B

T1

T2

$7C

SSC

SSA

$7D

P1

SSB

Blue bias for YUV operation DAC

$7E

P3

P2

Red bias for YUV operation DAC
Pixel Clock VCO Gain adjust DAC

3
BLCP

I
I

$7F

D3

D1

$80

RGB EN

D2

$81

Y2 EN

Y1 EN

Main Contrast DAC

$82

YUV EN

YXEN

Red Contrast trim DAC

$83

L2 Gain

L1 Gain

Blue Brightness trim DAC

$84

H Switch

525/625

Main Brightness DAC

$85

PClkl2

C Sync

Red Brightness trim DAC

$86

Vin Sync

PLL1 En

Main Saturation DAC (Color Difference section)

$87

Y2 Sync

0

$88

V21V1

RGB Sync

$00

2
L1 GATE

I
I

1
CBI

I
I

0
CAl

Blue Contrast trim DAC

IJI

I

(R-Y)/(B-Y) Saturation balance DAC (Decoder section)
Hue DAC
Set to $00 to start Horizontal Loop if $88-6

Table 14 is a brief explanation of the individual control bits.
A more detailed explanation of the functions is found in the
block diagram description of the text (within the Functional
Description section). Table 15 provides an explanation of the

=0

DACs. Each DAC is 6 bits wide, allowing 64 adjustment
steps. The proper sequence and control of the bits and
DACs, to achieve various system functions, is described in
the Applications Information section.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

9-213

MC44011
Table 14. Control Bit Description
Control Bit

Name

Description

$77-7

S·VHS·V

Set to 0 for normal Composite Video inputs at V1 and/or V2 (Pins 1,3). Set to 1 for S·VHS (VC)
operation. When 1, the V·input at the selected video input (V1 or V2, selected by Bit $88·7)
bypasses the initial luma delay line, and associated lumalchroma filters and peaking. The signal
passes through the second luma delay, adjustable with Bits D1·D3. Luma is output at Pin 33.

$77-6

SNHS·C

Set to 0 for normal Composite Video inputs at V1 and/or V2 (Pins 1,3). Set to 1 for S·VHS (VC)
operation. When 1, the chroma input at the non·selected video input (V1 or V2 by Bit $88·7) is di·
rected to the ACC loop and PAUNTSC detector. Color difference signals are then output at
Pins 41 and 42.

$77·S

FSI

Set to 0 for a Vertical Sync output rate of SO Hz. Set to 1 for 100 Hz. Useable in PAL systems only.

$77-4

L2GATE

When set to 0, the pixel clock charge pump (PLL2) operation is inhibited during the Vertical Retrace
to minimize momentary instabilities. When set to 1, PLL2 operation is not inhibited.

$77-3

BLCPGATE

$77-2

L1 GATE

$77·1,0

CB1,CA1

Sets the Vertical Timebase operating method according to Table 10.

$78·7

36/681ls

When 0, the time delay from the sync polarity reversal within the Composite Sync to the leading
edge of the Vertical Sync output (Pin 4) is 361ls. When 1, the time delay is 68 Ils.
(See Figure 33 and 34).

$78·6

CalKiII

$79·7

HI

This bit is not used in the MC44011 , and must be set to 1.

$79·6

VI

This bit is not used in the MC44011, and must be set to 1.

$7A-7

Xtal

When 0, the crystal at Pin 38 (17.7 MHz) is selected. When 1, the crystal at Pin 36 (14.3 MHz)
is selected.
This bit is not used in the MC44011, and must be set to O.

When 0, Vertical Gating of the black level clamp pulse during the Vertical Retrace occurs to
minimize momentary instabilities. The Vertical Gating can be inhibited by setting this bit to 1.
When set to 0, the horizontal PLL's phase detector (PLL1) operation is inhibited during the Vertical
Retrace to minimize momentary instabilities. When set to 1, the phase detector is not inhibited. If
PLL 1 gain is high (Bit $83·6 = 1), gating cannot be enabled.

When 0, the Horizontal Calibration Loop is enabled for two lines (lines 4 and S) in each field.
When 1, the Calibration Loop is not engaged. Upon power·up, this bit is ineffective (Calibration Loop
is enabled) until bit $86·6 is set to 0, and register $00 is set to $00.

$7A·6

SSD

$7B·7,6

T1, T2

Used to set the Sound Trap Notch filter frequency according to Table 3.

$7C·7, 6 $7D·6

SSC,SSA,SSB

Sets the NTSC/PAL decoder to the correct system according to Table 4.

$7D-7 $7E·7, 6

P1,P2,P3

Sets the Luma Peaking in the decoder section according to Table S. (See text).

$7F·7, 6 $80·6

D3,D1,D2

Sets the Luma Delay in the decoder section according to Table 6. (See text).

$80·7

RGB EN

$81·7

V2EN

When 1, the V2 Luma input (Pin 29) is selected. When 0, it is deselected.

$81·6

V1 EN

When 1, the V1 Luma Signal (provided by the decoder section to the color difference section) is
selected. When 0, it is deselected.

$82·7

VUVEN

$82·6

YXEN

$83·7

L2Gain

When 0, the gain of the pixel clock VCO (PLL2) is high (SO I!A). When 1, the gain is low (20 I!A).

$83·6

L1 Gain

When 0, the Horizontal Phase Detector Gain (PLL1) is low. When 1, the gain is high.

$84-7

H Switch

When 0, Pin 12 is open. When 1, Pin 12 is internally switched to ground, allowing the PLL1 filter
operation to be adjusted for noisy signals.

When 0, permits the RGB inputs (Pins 26 to 28) to be selected with the Fast Commutate (FC) input
(Pin 2S). When 1, the FC input is disabled, preventing the RGB inputs from being selected. When
the RGB inputs are selected, the Color Difference inputs (Pins 30, 31) are deselected.

When 0, Pins 20 to 22 provide RGB output signals. When 1, those pins provide VUV
output signals.
Effective only when the RGB inputs are selected. When 0, the RGB inputs (Pins 26 to 28) are
directed to the RGB outputs (Pins 20 to 22) via the Contrast and Brightness controls. When 1, the
RGB inputs are directed through the Color Difference Matrix, allowing Saturation control in
addition to the Brightness and Contrast controls. See Figure 36.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

9-214

MC44011
Table 14. Control Bit Description (continued)
Control Bit

Name

$84-6

525/625

$85-7

PClkl2

When 0, the PLL2 VCO provides the Pixel Clock at Pin 18 directly. When 1, the VCO output is directed through a + 2 stage, and then to Pin 18.

$85-6

C Sync

When 0, Pin 13 will provide a square wave of ~ 250 kHz (16 x Fh). When 1, Pin 13 provides a negative composite sync signal. See Figures 25, 27, 30, 31.

$86-7

Yin Sync

$86-6

f'LL1 Enable

$87-7

Y2 Sync

$87-6

0

$88-7

V2IV1

$88-6

RGB Sync

Description
This bit sets the division ratio from the crystal for the reference frequency for the Horizontal
Calibration Loop. For NTSC systems, set to 1. For PAL systems, set to O.

When 1, Composite Sync at the selected Video input (Pin 1 or 3) is used for all internal timing.
When 0, the Sync source is selected by Bits $87-7 and $88-6. See Table 12.
After power up, this bit must be set to 0, and then register $00 set to $00, to enable the Horizontal Loop
(PLL 1). Setting this bit to a 1 will disable the Horizontal Loop, and engages the Calibration Loop.
When 1, and $86-7 = $88-6 = 0, Composite Sync at the Y2 input (Pin 29) is used for all internal
timing. When 0, the Sync source is selected by Bits $86-7 or $88-6. See Table 12.
This bit must always be set to

o.

When Composite Video is applied, and this bit is 0, the Video 2 input (Pin 3) is directed to the Sound
Trap. When 1, the Video 1 input (Pin 1) is selected. In S-VHS applications, when 0, Pin 3 is the Y
(Iuma) input, and Pin 1 is the chroma input. When this bit is 1, Pin 1 is the luma input, and Pin 3 is
the chroma input.
When 1, and $86-7 = $87-7 = 0, Composite Sync at any or all of the RGB inputs (Pin 26 to 28) is
used for all internal timing. When 0, the sync source is selected by Bits $86-7 or $87-7.
See Table 12.
Table 15. Control DAC Description

Control Bits

Description

$78-5/0

This DAC allows for a relative gain adjustment of the R-Y and B-Y outputs (Pins 41,42) as a means of adjusting the
color decoding accuracy. Nominal setting is 32.

$79-5/0

Used to balance out reference errors of the color subcarrier, primarily for NTSC. Nominal setting is 32.
Adjustment range is ~ ± 5°.

$70-5/0

Used to set the U (Pin 22) DC bias level. When in the YUV mode ($82-7 = 1), this setting should nominally be 32. When
in RGB mode, set to 00.

$7E-5/0

Used to set the V (Pin 22) DC bias level. When in the YUV mode ($82-7 = 1), this setting should nominally be 32. When
in RGB mode, set to 00.

$7F-5/0

Used to fine tune the gain of the Pixel Clock VCO to obtain optimum performance without instabilities. A setting of 63 will
shut off the VCO. Setting 50 to 62 provide non-square wave outputs, and can be unstable. As the setting is increased
from 00 to 49, the gain is increased. Changing this register does not change the Pixel Clock frequency.

$80-5/0

Used to fine tune the contrast of the Blue output when in RGB mode. In YUV mode this provides a fine tuning of the
color, similar to, but not to be confused with, hue.

$81-5/0

Used to adjust the gain of the three outputs. In RGB mode this is the Contrast control.

$82-5/0

Used to fine tune the contrast of the Red output when in RGB mode. In YUV mode this provides a fine tuning of the color,
similar to, but not to be confused with, hue.

$83-5/0

Used to fine tune the brightness of the Blue output when in RGB mode. In YUV mode this provides a fine tuning of the
color, similar to, but not to be confused with, hue.

,

$84-5/0

Used to adjust the brightness of the three RGB outputs. In YUV mode this DAC affects only Y output (Pin 21).

$85-5/0

Used to fine tune the b~ightness of the Red output when in RGB mode. In YUV mode this provides a fine tuning of the
color, similar to, but not to be confused with, hue.

$86-5/0

Used to adjust the saturation of the RGBIYUV outputs of the Color Difference section.

$87-5/0

Used to adjust the saturation of the R-Y, B-Y outputs (Pins 41,42) of the Decoder section.

$88-5/0

Used to adjust the hue of the R-Y, B-Y outputs (Pins 41,42). Nominal setting is 32.

$00-7/0

This register must be set to 00, after Bit $86-6 is set to 0, to enable the Horizontal Loop (PLL 1) after power up, or
anytime when Bit $86-6 is set to 0 after having been a 1.

The above DACs are 6-bits wide. The settings mentioned above, and in subsequent paragraphs are given in decimal values of 00 to 63. These are not hex values.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

9-215

MC44011
Reading Flags
A read cycle need not be restricted to the vertical interval,
but may be done anytime. A flag read cycle consists of three
bytes (with three acknowledge bits):
• The first byte is always the Read address for the
MC44011 ($88).
• The second and third bytes are the flag data.
Communication begins when a start bit (data taken low
while clock is high), initiated by the master (nolthe MC44011),
is detected, generating an internal reset. The first byte
(address) is then entered, and if correct, an acknowledge is

generated by the MC44011. The flag bits will then exit the
MC44011 as two 8 bit bytes at clock cycles 10-17 and 19-26.
The master (receiving the data) is expected to generate the
acknowledge bits at clocks 18 and 27. The master must then
generate the stop bit.
The MC44011 flags must be read on a regular basis to
determine the status of the various circuit blocks. The
MC44011 does not generate interrupts. It is recommended
the flags be read once per field or frame. See Table 16 for a
description of the flags.

Table 16. Flag Description
Clock No.

Description (When Flag

= 1)

10

Internally set to a Logic 1.

1t

Horizontal Loop (PLL 1) enabled, indicating the loop can be driven by the incoming sync. This bit will be low upon power up, and will change to a 1 after initialization of control Bit $86·6 and register $00.

12

Horizontal Loop (PLL 1) not locked. Lack of incoming sync, or wrong sync source selection, or the wrong horizontal
frequency, will cause the Coincidence Detector to indicate a "not locked" condition.

13

Internally set to Logic O.

14

Less than 576 horizontal lines counted per frame. This flag helps determine the applied video system. When high, a
525 line system (NTSC) is indicated. When low, a 625 line system (PAL) is indicated.

15

Vertical Countdown engaged. When high, this flag indicates the Vertical Countdown section has successfully
maintained lock for 8 consecutive fields, indicating therefor a successful vertical lock-up. This flag is low in the
Injection Lock mode.

16

Internally set to a Logic 1.

17

Internally set to a Logic 1.

18

(Acknowledge pulse).

19

Pixel clock VCO control voltage too low « 1.7 V at Pin 16). This indicates the VCO may not function correctly as the
control voltage is near one end of its range. The DAC setting at register $7F-5/0 must be increased, and/or the + 2
block must be selected (set $85-7 = 1), to clear this flag.

20

Pixel clock VCO control voltage too high (> 3.3 V at Pin 16). This indicates the VCO may not function correctly as the
control voltage is near one end of its range. The DAC setting at register $7F-5/0 must be reduced, and/or the + 2 block
must be deselected (set $85-7 = 0) to clear this flag. This flag will be high if the VCO is off (DAC $7F = 63).

21

Internally set to a Logic 1.

22

Internally set to a Logic O.

23

ACC Loop is active, indicating it is locked up to the color burst signal. The Color Burst amplitude must exceed
30 mVp _p , and the correct crystal selected, for lock-up to occur.

24

PAL system identified by the decoder, indicating the decoder recognizes the line-by-line change in the burst phase.
When NTSC is applied, this flag is O.

25

Not used.

26

Internally set to a Logic O.

27

(Acknowledge pulse).

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

9-216

MC44011
APPLICATIONS INFORMATION
Design Procedure and PC Board Layout
The external components required by the MC44011 are
shown in Figure 42. Except for the crystals, all the
components are standard value resistors and capacitors, and

can be non-precision. Table 17 describes the external
components for each pin.

Figure 42. Basic Functional Circuit
Video 2 ___--'V47V10~
Output

VSync Out __- - - ,
12C{SCL

--1~~======:;=1l

Bus SOL ......
Field 10 Out - - - - - - - - - ,
Burst Gate Out - - - - - - - - - - - ,

1.0
1.0

+5.0

(If necessary - see text)

Gnd
Xtall
NtC
Xtal2
PLL 1Rlt
'-'\i'o/'v----=:::-::1I--,,12"-j PLL 1Filt SW
12k 4700pF
16Fh/Csynutc __----'''''----'.:..::..:;0.:.---'.:'-1
16Fh/CSVNC
o
.---------"''-1 FH Ref
.---------;.:'-1 15k Ret
I-,--~;.J PLL FiR
~--=~o-----'-'--I

G~

Pixel
Clock ----+-+-5-.0---------,

MNOC~~------~

SysSell-":----------'
V1Out ~~----:-=-------,
47
VI Clmp
1 0.

MC44011

*

R~Vp~---~~-+_-~

B·V VP ~------_+_-__::...,-'
V2 In
220 0.22
VI Luma Out
I~ • V2 Luma Input
gee

5

E

5 ~ '0
0 (.) c (.) .5 - U>a:C!JDl>C!Ju..Dla:C!J

55
o~ 8
(,)00

220~0'22
-: 75
Red In

220

0.22

'--_ _ _ _--'V22Vy0

0.22

'-----...JV\/'v

Red Out ---H-+-----,
Green Out ---1--+----,
Blue Out __--<0-------, L _ _ _ _ _ _----'

Fast
Commutate
Crystal Specifications and Operation
The crystals used with the MC44011 should comply with
Table 18 specifications.
Table 18. Crystal Specifications
Frequency:
(4 x Subcarrier)

NTSC (14.31818 MHz)
PAL (17.734472 MHz)
PAL-M (14.30244 MHz)

Pull-in range:

± 1600 Hz

Tolerance:

30 ppm (with fixed load capacitor)

Temperature Coefficient:

50 ppm (with fixed load capacitor)

Operating Mode:

Fundamental series resonance

(with respect to crystal frequency)

Load Capacitance:

Nominally 20 pF

Motional Capacitance:

10 to 30 fF

Series Resistance:

< 30 0 (nominally 10 0)

75Ea

The oscillator output resistance at Pin 36 is nominally 300 n
for NTSC mode, and 400 n at Pin 38 for PAL mode. It is
recommended that a stray capacitance (p.c board, package
pins, etc.) of 4.0 to 5.0 pF be included when selecting a crystal.
The above values for tolerance and temperature
coefficent can be increased if a trimmer capacitor is used for
the load capacitor.
The crystal PLL filter (Pin 44) voltage is between 1.8 and
3.8 V in normal operation. If the color output of the MC44011
is incorrect, or non-existent (ACC flag off), this voltage should
be checked. If it is beyond either of the above limits, the
capacitor in series with the crystal should be changed so as
to allow the PLL to pull-in the crystal. The capacitor is
generally specified by the crystal manufacturer, but should
also comply with Table 18 specifications. If no burst is
present, Pin 44 voltage will be =1.3 V.
The selected crystal frequency can be checked by using a
scope at the non-selected crystal pin. The signal amplitude is
nominally 200 to 400 mVp-p. In this way the selected crystal's
frequency is not affected by the scope probe.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
9-217

Green In
Blue In

MC44011
Table 17. External Components
PinNa.

Name

Function

1,
3

Video 1,
Video 2

Input signals must be capacitor-coupled. The 470 Q resistors protect the pins from ESD and RFI. The 75
Q resistors are not required by the MC44011, but depend on the signal source. The 47 pF capacitors filter
high frequency noise.

2

ACC Filter

The 0.1 I1F ceramic capacitor filters the Automatic Gain circuit.

4

Vert. Sync

The pull-up resistor is required for this open-collector output.

5,
6

SCL,
SDL

Pull-up resistors are required on each 12C line since outputs are open-collector. They are typically located
at the master device.

7

Field ID

No external components required.

8

Burst Gate

No external components required.

9

Iref

The 110 kQ resistor provides = 3211A from the + 5.0 V source. This pin must be well filtered to the Quiet
Ground (Pin 10).

10

QuietGND

This is the Reference Ground for Pin 9 and the PLL1 Filter.

11

PLL1 Filter

The 100 kQ resistor, and the 0.1 I1F and 68 pF capacitors are the filter network for this PLL.
Connect to Pin 10 ground.

12

PLL1 Filt.SW

The 12 kQ resistor and 470 pF capacitor give the filter a longer time constant when Pin 12 is switched in.

13

16 Fh/CSync

No external components required.

14

Fh Ref

No external components required.

15

15 k Return

TIL Return signal from external frequency divider.

16

PLL2 Filter

The 10 kQ resistor and 47 nF and 4.7 nF capacitors are the filter network for this PLL. Connect to Pin 17
ground.

17

Ground

Ground for the Pixel Clock circuit.

18

ClkOut

Pixel Clock output to external frequency divider and triple ND converter.

19

VCC3
R,G, BOut

+ 5.0 V supply for the Pixel Clock circuit.

VCC2
Ground

+ 5.0 V supply for the Color Difference section.

24
25

FastComm.

No external components required. This input should not be left open.

B,G, R In

Input signals must be capacitor-coupled. The 220 Q resistors protect the pins from ESD and RFI.

29

Y21nput

Input signals must be capacitor-coupled. The 220 Q resistor protects the pin from ESD and RFI. The 75
Q resistor is not required by the MC44011 , but depends on the signal source.

30,
31

B-Y,
R-Yln

Input signals must be capacitor-coupled. The MC44140 is required if PAL signals are processed
(see text).

32

Y1 Clamp

The 0.1 I1F ceramic capacitor provides clamping for the Y1 output.

33

Y10ut

No external components required. This pin cannot drive 75 Q directly. If required to do so, see text for
suggested buffer.

34,
35

SystemSel.,
Sandcastle

For use by the MC44140 delay line. No other external components required.

36,
38

Xtal2,
Xtal1

A 17.7 MHz crystal is required (at Pin 38) for PAL signals, and a 14.3 MHz crystal is required (at Pin 36)
for NTSC signals. If only one crystal is required, leave the other pin open. The series capacitor depends
on the crystal manufacturer. (See Table 18 for crystal specs.)

20,21,22

23

26,27,28

The 390 Q pull-up resistors are required for these open-collector outputs. The pull-ups should go to a
clean, well filtered + 5.0 V supply. These pins cannot drive 75 Q directly. If required to do so, see text for
suggested buffer.
Ground for the Color Difference section.

37

N/C

No external components required.

39

Ground

Ground for Color Decoder section.

40
41,
42

VCC1
B-Y,
R-YOut

+ 5.0 V supply for the Color Decoder section.

43

Indent. Filter

The 0.1 I1F ceramic capacitor provides filtering for the Identification circuit.

44

4FSC PLL

The 47 kQ resistor, and O.II1F and 2.2 nF capacitors are the filter network for the crystal PLL. Connect to
Pin 39 ground.

The MC44140 is required if PAL signals are processed. Otherwise, capacitor-couple to Pins 30, 31
(see text).

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
9-218

MC44011
Power Supplies and Ground
There are three VCC pins (Pins 19, 23, and 40) which must
be connected to a source of +5.0 V, ± 5%. Since the three pins
are internally connected by diodes, none can be left open,
even if a particular section (such as the Pixel Clock
Generator) is to be unused. Total current required is ~135 mA
(including the RGB output load current). There are
four ground pins (Pins 10, 17, 24, and 39) which
must be connected together, and preferably connected to a
ground plane.
Pins 19 and 17 are the VCC and ground for the Pixel
Clock Generator, and the circuitry associated with the Pixel
Clock should be referenced to those two pins.
Pins 23 and 24 are the VCC and ground for the Color
Difference section, which includes the RGB outputs. The
output pull-up resistors should be connected to the VCC at
Pin 23.
Pins 40 and 39 are the VCC and ground for the Color
Decoder, Sync Separator, Horizontal PLL and the Vertical
Decoder. Pin lOis the Quiet Ground for the horizontal PLL's
VCO and filter, and therefore, the components on Pins 9 and
11 should be connected as close as possible to Pin 10.
Bypassing of the power supplies must be done as close as
possible to each VCC pin, and at the output pull-up resistors.
Recommended bypassing components are a 10 IlF tantalum
capacitor in parallel with a O.OlIlF ceramic.
Input Signals
The various video inputs, Video 1 and 2, Red In, Green In,
Blue In, R-V, B-V, and V2 inputs, are designed to accept
standard level analog video waveforms. They are not
designed for digital signals. The input impedance of the
above pins is high. The need for 75 il terminations for those
video signals depends on the video source itself. All of the
above signals must be capacitor-coupled as clamping is
provided internally.
The 12C inputs (SCL, SOL) are designed according to the
12C specifications, which define VOL as between 0 and 1.5 V,
and VOH as between 3.0 V to VCC. See Appendix C.
The 15 k Return and Fast Commutate (Pins 15 and 25,
respectively) are designed for TTL level signals. If unused,
they should not be left open, but connected to + 5.0 V, or
ground, as appropriate.
Output Signals
The RGBIYUV outputs are open-collector, and require
pull-up resistors (typically 390 il) to a clean + 5.0 V (VCC2).
The output impedance is such that the load impedance (to
ground) should be > 1.5 kil. If it is desired to drive a 75 n load
(e.g., a monitor) from these outputs, a simple buffer (see
Figure 43) can be added.
Figure 43_ Output Buffer

The Vl output (Pin 33) has an output impedance of
300 n, and can be used as a monitoring point, or to drive
the input of the MC44145 sync separator, or other high
impedance loads (minimum load forVl is 1.0 kn). If it is to be
used to drive a 75 n load, the buffer shown in Figure 43 can
be used, except the 390 n resistor must be deleted.
The Vertical Sync output (Pin 4) is an open-collector logic
level output, and requires a pull-up resistor to + 5.0 V. 10 kn
is recommended, but it can be as low as 1.0 kn. The 12C data
line (SOL, Pin 6) is also open-collector when it is an output,
and can sink a maximum of 3.0 mA. Only one pull-up resistor
is required on the SOL line (regardless of the number of
devices on that line). and it is typically near the master device.
The Field 10, Burst Gate, 16 Fh/CS ync , Fh Ref, and Pixel
Clock outputs are logic level totem-pole outputs.
~

PC Board
The PC board layout should be neat and compact, and
should preferably have a ground plane. If feasible, a second
plane should be provided for the + 5.0 V supply, but this is not
mandatory. The components at Pins 9 and 11 should be
connected to the same ground track which goes to Pin 10.
The VCC and ground should be connected as directly as
possible to the power supply, and not routed through a maze
of digital circuitry before arriving at the MC44011. Since the
MC44011 is intended to be used with AID converters and
high speed digital signals, it is expected digital circuitry will be
on the same board. Care should be taken in the layout to
prevent digital noise from entering the analog portions of the
MC44011. The most sensitive pins are Pins 1,2, 3, 9, 10, 11,
12, 16, and 44, and should be protected from noise.
Initialization and Programming Information
Upon powering up the MC44011, initialization consists of
first filling the registers with initial values to set a known
condition. Table 19 provides recommended values for the
initial settings, although these may be tailored for each
application (with the exception of Bits $79-6,7, $7A-6, $86-6,
and $87-6). Table 19 settings will set up the MC44011 to the
following conditions:
• CompOSite video input at Video 1 (Pin 1), NTSC, using
the crystal at Xtal 2 (Pin 36).
• Vl enabled, RG outputs enabled, and Composite
Sync at Pin 13
'
• RGB inputs not enabled (R-V, B-V inputs are enabled)
• The Sound Trap at 4.5 MHz
• The Luma Peaking at 0 dB
• The Luma Delay at minimum
• High gain and high noise rejection for the horizontal PLL
o Vertical decoder set to Injection Lock mode
• The Pixel Clock VCO is off
After the registers are initialized, then set Bit $86-6 to 0,
and load register $00 with $00. This will enable the horizontal
PLL, permitting normal operation.

R,G,B,
orYIOut

To Monitor

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

9-219

MC44011
Table 19. Recommended Initial Settings
Sub
Address

7

6

5

S·VHSC=O

FSI = a

$78

a
36/681's = a

$79

HI = 1

VI= 1

$7A

Xtal =1

SSD=O

$77

S·VHS Y=

Calkill =

a

4

a

BLCP

T1 =1

T2= 1

SSC=O

SSA= 1

$7D

P1 =1

SSB = a

Blue Bias = 00

$7E

P3 = 1

P2 = 1

Red Bias = 00

$7F

D3 =0

D1 = 0

Pixel Clock VCO Gain Adjust = 63

$80

RGB EN = 1

$81

Y2 EN =0

Main Contrast = 47
Red Contrast Trim = 32

$82

YUV EN = a

YX EN =0

$83

L2 Gain = 1

L1 Gain = 1

Blue Brightness Trim = 32

$84

H Switch = 1

525/625 = 1

Main Brightness = 30
Red Brightness Trim

PCIk/2 = 1

CS ync = 1

$86

Vin Sync = 1

PLL1 EN = 1

$87

Y2 Sync = a

0

$88

V2N1 = 1

RGBSync = 0

L1 Gain = a

1
CBI

0
=

a

CAl = 1

Blue Contrast Trim = 32

Y1 EN = 1

$85

a

Subcarrier Balance DAC = 32

$7B

a

=

(R-Y)/(B-Y) Adjust DAC = 32

$7C

D2=

2

3

L2 Gain =

=

32

Main Saturation (Color Difference section) = 32
(R-Y)/(B-Y) Saturation Balance (Decoder section) = 15
Hue = 32

These settings are for power-up initialization only. Refer to the text, and Appendix B, for subsequent modifications based on the application.

Then, after selecting the desired input(s) (from Pins 1, 3, or
26 to 31), and based on the applied signals at those inputs,
and by reading the flags, the registers are adjusted for the
desired and proper mode of operation. A suggested routine
for setting modes is given in Appendix B. The "initial values"
in the Control DACs table of Appendix B are those in Table
19. The remainder of the flow chart is a recommendation only,
and should be tailored for each application.
The monitoring of flags should be done on a regular basis,
and it is recommended it be done once per field. See Table 16
(in the Functional Description section) for a summary of the
flags. Should any flags change, the following procedures are
recommended:
Flag 11 (Horizontal Enabled) - Once enabled by setting
Bit $86-6 = 0, this flag should always remain a 1. Should it
change to 0, reset $86-6 to 0, and write $00 to register $00
again. If the flag does not return to a 1, this indicates a possible device malfunction.
Flag 12 (Horizontal Out-ot-lock) - When 1, this indicates:
a) the wrong input is selected (Bits $88-7, $81-7,
$80-7, and $77-7,6), or;
b)the wrong sync source is selected (Bits $86-7, $87-7,
and $88-6), or;
c) the incoming signal is somewhat unstable, as from a
VCR tape (change Bit $83-6), and/or;
d)the incoming signal is noisy (change Bit $84-7), or;
e) a loss of the incoming signal with sync.
(It is possible for this flag to flicker when the video signal is
from a poor quality tape, or other poor quality source.)

Flag 14 (less than 576Iines)- This flag, from the vertical decoder, is used to help determine if the signal is PAL or NTSC.
Should it change, this indicates the incoming signal has
changed format, or possibly one of the items listed under Flag
12 above.
Flag 15 (Vertical Countdown Engaged) - Bits 77-0 and 1
must be set to 1 (after Flag 12 reads 0) for this flag to indicate
correctly. Then this flag will change to a 1 after 8 fields of successful synchronization of the internal counters with the incoming signal. To change to a 0 requires 8 consecutive fields
of non-synchronization. If this flag changes to 0, this indicates
a loss of signal, a change of signal format, or instability in the
horizontal PLL.
Flags 19, 20 (VCO Control Voltage low/High) - These flags
are meaningful only if the Pixel Clock Generator is used. If Flag
19 is a 1 , the gain of the pixel clock VCO needs to be increased
by increasing the value of register$7F, and/or set Bit $85-7 =1.
If Flag 20 is a 1, the value of the register must be decreased,
and/or set Bit $85-7 = o. If the VCO is turned off ($7F = 63), Flag
19 will be 0, and Flag 20 will be 1.
Flag 23 (ACC Active) - If this flag is a 0, it indicates the ACC
loop is not active. This will happen if the burst signal is less
than 30 mVp-p, if the incorrect crystal is selected ($7A-7), ilthe
crystal PLL is not locked, or if the horizontal PLL is not locked.
Flag 24 (PAlldentitied) - This flag is a 1 when PAL signals
are applied, and a 0 when NTSC signals are applied, or when
no burst is present.
It is recommended that the Color Decoder section, and
crystal, should be set according to the state of Flags 14, 23,
and 24 according to Table 20.

MOTOROLA LlNEARIINTERFACE ICs DEVICE DATA

9-220

MC44011
Table 20. Color Standard Selection Table
Flags

Bit Settings

#14

#23

#24

<576 Lines

ACCActive

PAL Signal

X

0

X

0

1

0

0

1

1

Crystal

SSA
($7C·6)

SSB
($70·6)

SSC
($7C-7)

System

Either

1

1

0

Color Kill

Either

1

1

0

Color Kill

17.7 MHz

0

1

0

PAL

1

1

0

14.3 MHz

1

0

0

NTSC

1

1

1

(Note 1)

0

1

0

PAL·M

NOTES: 1. PAL·M, used in Brazil and other Soulh American countries, can be decoded by the MC44011, but requires a 14.3024 MHz crystal.
2. SSO ($7A·6) is always set to O.

MISCELLANEOUS APPLICATIONS INFORMATION
Use of the MC44140 Delay Line
The MC44140 delay line is generally required if PAL
signals are to be decoded, so as to average out the
line-by·line color information associated with PAL color
decoding. If the same single PAL video source is always used
in a particular application, the delay line can be eliminated,
and any slight phase errors can be corrected with the DAC of
register $79-5/0. If, however, various video sources can be
used, and/or if the video signal is less than broadcast quality,
it is recommended the MC44140 delay line be included.
The MC44140 acts on the color difference signals before
they enter the color difference stage of the MC44011. It will,
however, pass NTSC signals through without modifications.
The MC44011 uses the System Select output (Pin 34) to
indicate to the delay line which signals are being processed.
The System Select voltage is set when the color decoder is

set with Bits SSA, SSB, SSC, SSD. The Sandcastle output
(Pin 35) provides the horizontal timing signals to the delay
line. In addition, the MC44140 uses the crystal frequency for
the internal counters.
The MC44140 is inserted into the circuit between the Color
Difference outputs and inputs of the MC44011. In addition,
the MC44140 provides pins (Pins B,9) for inserting an
alternate source of color difference signals to the MC44011
by setting the System Select to external (Bit $7C-7 = 1). See
Figure 44 for a suggested circuit.
If only NTSC signals are to be processed by the MC44011,
the MC44140 is not needed. In this case, connect Pin 42 to
Pin 31 with a 0.111F capacitor, and similarly connect Pin 41 to
Pin 30.

Figure 44. Incorporating the MC44140 Delay Line

--MC44011l

+5.0

12,OpF

10

Gnd $±1~---'

Xtall

Xtal2

47

I .".
22pF
~II---II---+t---+-t
I 17.7MHz
I
22pF

I3sl-iII---l
114.3MHz

SandC

I

MC44140
5

SandC

SysSel

f - - - - - - - ' .....---t~ R·Y In

r---~-l
7 R·YOU!

r

~.

0.1

SysSel

B·Y In

B·Y 0: h-J.Ol

B.YOU! 41 f - - - - - - - + - - - , _

O.t

L- __

,I----

@t.)

~~ 14.32
one::

~~

!5

5
o
x....~

~

14.32
14.31
14.31
-1.0

~
o

~

~
KONTSC

I('

~e

1.0

17.74

¥
;;:!

Table 1. Crystal Specifications
Frequency

17.74

Mode

17.73

Frequency Tolerance
@25°C
df/dfo 0' - 70'C
Load Capacitance

17.73

ESR

gain must be estimated from the
17.72
operating point. KOpAL is the gain for
PAL applications and KONTSC is the
gain for NTSC applications.
17.72
2.0
3.0
4.0
5.0
6.0

Cl (Internal Series CapaCitance)

~

VCO, CONTROL VOLTAGE (PIN 3 VOLTAGE) M

MOTOROLA LlNEARIINTERFACE ICs DEVICE DATA
9-231

14.31818 MHz (NTSC)
17.734475 MHz (PAL)
Fundamental
40 ppm
20pF
50Q
15fF(mpF)

MC44144
Figure 2. Test Schematic
4X
+5.0

Voltage

Reference
2.6V

Video Clamp

4XRef
Out
Divideby4

Subcarrier
Output

FUNCTIONAL DESCRIPTION
The MC44144 is designed to implement the color sync
function in a video system. When provided NTSC/PAL
composite video or composite chroma and burst gate inputs,
the IC will phase-lock a Voltage Controlled Crystal Oscillator
(VCXO) to the color burst. Both 4X and 1X subcarrier
frequency outputs are provided by the IC. The VCXO
operates off of a 4X subcarrier crystal and is typically
± 350 Hz of pull-in.
In addition to providing the gate pulse for the MC44144
phase detector, the Burst Gate input also initiates a clamp
pulse that sets up the level of the composite video at the input
to the Phase Detector. The start and duration of the Gate
Pulse should be timed so that the pulse envelopes the color
burst of the video signal, but not so wide as to gate sync or
video into the Phase Detector.
The Phase Detector is enabled when the voltage at
the Burst Gate input (Pin 7) is above the nominal 2.2 V threshold. While this makes possible the ability to lock to a color
burst, it does not exclude the possibility of lock to a constant
reference. If a constant source is to be the reference, the
Phase Detector can be permanently enabled by holding the
voltage on the Phase Detector input pin higher than the
threshold voltage.
The phase detector gain must be specified in two ways, for
a constant reference and for a burst-locked application. The

gain in a constant reference application is specified by the
maximum current output with the maximum phase error. For
a maximum phase error of 7tl2 radians the maximum current
available is approximately 200 flA. So the phase detector
gain is defined as,
KPD = 200/(7tl2)(flAIrad/sec)
For a burst-locked application, the Phase Detector is active for only the duration of the color burst. Therefore the
phase detector gain must be specified as an average gain
over a line period. In this case the phase detector gain for
NTSC and for PAL applications is,
KPDNTSC = (S/(7tl2))(jlNrad/sec) and,
KPDpAL = (7/(7tl2))(flAIrad/sec)
A suitable filter for both types of applications is shown in
the test schematic Figure 2. This same filter also works for
both NTSC and PAL applications.
The 4X subcarrier Voltage Controlled Crystal Oscillator
(VCXO) was designed to work with a parallel resonant crystal. A suitable crystal would meet the specifications found in
Table 1.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
9-232

MC44144
PIN FUNCTION DESCRIPTION
Name
Subcarrier
Output

Pin

Representative Circuitry

Ground

2

Circuit Ground

Phase
Detector
Output

3

The error current from the
phase detector is output at
this pin. A filter circuit should
be connected at this pin.

~
1.0M

2. 5V.i.

I

-=-

4XSubXtai

4

4X Subcarrier
Output (or
Black Burst)

5

Composite
Video Input
(Black Burst,
Continuous
Wave, or
Composite
Chroma
can also be
applied)

6

Vee

*+
; ~
%

Expected Waveforms

Description
Subcarrier Output. A
phase-locked reference of
the PAL or NTSC color burst
is output at this pin.

A 300 mVp-p square wave is
output. Some high frequency
content is present.

A beat waveform, showing both
horizontal period and half the
subcarrier period, is present.
~1/2 Subcarrier PeriOd~
\\\\\\\,

,\\\\\\\

!---UnePeriod-.j Vlcck

Crystal Oscillator Pin. A 4X
subcarrier parallel resonant
crystal, in series with a
5.0 pF to 25 pF trimmer
capacitor provides the
resonant element for the
Voltage Controlled Crystal
Oscillator (VCXO).

Approximately 40 mVp-p. A
scope probe will disturb the
frequency of oscillation.

Buffered output from the 4X
voltage controlled oscillator.

The sinusoidal 4Xfsc oscillator
output is available at this pin.
The output is nominally:
610 mVp-p for NTSC,
450 mVp-p for PAL.

Composite Video Input.
Color burst from the video
present at this pin is used as
a reference to phase lock
the VCXO. Positive or
negative video may be
used.

Composite video should be
applied at this pin. The color
burst amplitude of the input
video should be at least 50 mV,
but no more than 1000 mV. The
waveform at this pin should not
exceed ground or VCC.
- - - - - - - - Vee

I

2.1W
- - - - - - - - GND

Burst Gate
Input

7
Vee

Input for the phase detector
gate pulse. TTL compatible.
The threshold is nominally
2.2V.

A positive going gate pulse
should be applied at this pin. The
Burst Gate input should envelope the color burst.

22k
22k

Pin 6
Pin 7-=.R - - - - -

VCC

8

Power Supply Pin. 5.0 Vdc
should be applied at this pin.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
9-233

2.2V

MOTOROLA

MC44145

SEMICONDUCTOR-----TECHNICAL DATA

SYNC SEPARATOR/
PIXEL CLOCK GENERATOR

Product Preview

Sync Separator/
Pixel Clock Generator

SILICON MONOLITHIC
INTEGRATED CIRCUIT

The MC44145 Pixel Clock Generator is a component of the MC44000 family,
and a spin-off of the PLL2 function of the MC44011 , Digital Multistandard Video
Processor.
The MC44145 contains a sync separator with horizontal and vertical outputs,
and clock generation circuitry for the digitalization of any video signal along with
the necessary circuitry for clock generation, such as a phase comparator and
a divide-by-2 to provide a 50% duty cycle.
The MC44145 is available in a 14 pin package and is fabricated using
Motorola's high density, low voltage, bipolar MOSAIC 1.5® process.

DSUFFIX
PLASTIC PACKAGE
CASE 751A
(50-14)

Simplified Block Diagram
VCC
Sync Sep
1

Sync Out

Sync Amp

~

r---.A---l

'-w-' ,

BC

In

Out

PIN CONNECTIONS

Div 2
EN

NPDGain

1

PLL Loop Filter
NBACK
Video In

Sync Amp In

4
Sync Amp Oul

Clock 7
Out
(Top View)

Clock Out

Gnd

ORDERING INFORMATION
Device

Temperature
Range

Package

MC44145D

0° 10 +70°C

50-14

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
9-234

MC44145
CIRCUIT DESCRIPTION
Composite Sync Separator
The composite sync separation section comprises two
blocks, a sync slicer and a sync amplifier, that can be used to
extract the vertical sync information from a video signal.
The sync separator is an adaptive slicer in which the video
signal is slightly integrated and then sliced at a ratio of 4.7 to
64 which corresponds to the sync to horizontal ratio. Two
outputs are given, one of high impedance and the other low
impedance.
A slicing sync inverting amplifier is also on-chip, allowing
one output to be used for composite sync and the other
output to be integrated and then sliced using the slicing
amplifier to extract the vertical sync information.
Clock Generation
The clock generation is made up of a wide ranging
emitter-coupled VCO followed by a switchable .,. 2 to provide
a 50% duty cycle wherever required, or twice the set
frequency if an external divider is used. The clock generation
is a PLL subsection. Its function is the generation of a high
frequency, line-locked clock that is used for video sampling
and digitizing.

The clock is output by a LSTTL-like buffer which has a
limited drive capability of two LSTTL loads.
The VCO is driven from a charge pump circuit, with
selectable current. The charge pump is driven from the phase
comparator. The phase comparator is a type IV "phase and
frequency comparator" sequential circuit.
The clock generator, the heart of a PLL, is to be closed by
means of an external divider, thus setting the synthesized
frequency. This divider could be implemented in discrete logic
or be a part of an ASIC subsystem.
Phase and Frequency Comparator
The phase comparator is fed from two input buffers (Fref)
which expects a reference frequency at line rate and that is
rising-edge sensitive, and NBACK which comes from the
external divider and is falling-edge sensitive.
Charge pump current and output divider action are
controlled by applying suitable voltage on the appropriate
pins, respectively, NPD Gain and Div 2 EN.

PIN FUNCTION DESCRIPTION
Pin

Function

Description

1

NPD Gain

This pin sets the gain of the phase frequency detector by changing the current of the
charge pump output (40 /.LA or 80 /.LA). Low current with this pin> 2.0 V, high current
for < 0.5 V.
Ground connection common to the PLL and sync separator sections.

2

Ground

3

Sync B

High impedance sync output.

4

Sync Amp In

Sync amplifier input.

5

SyncC

Low impedance sync output.

6

VCC

Power connection to the PLL section.

7

Clock Out

VCO clock output. Capable of limited LSTTL drive. It should not be used to drive high
capacitive loads, such as long PCB traces or coaxial lines.

8

Div 2 EN

The divider is switched-in with this pin> 2.0 V; switched-out for < 0.5 V.

9

Fref

Reference frequency input to the phase and frequency comparator. Typically, this will
be a 15625 (15475) Hz signal. It is rising-edge sensitive. Due to the nature of the phase
and frequency comparator, no missing pulse is tolerable on this input. In a typical
setup, this signal can be provided by the MC44011.

10

Sync Amp Out

Sync amplifier output.

11

VCC2

Power connection to the sync separator and amplifier.

12

Video In

Video signal input to the sync separator.

13

NBACK

Fed by the external clock divider. Sets the multiplication ratio of the loop in multiples of
the Fref frequency. Negative-edge sensitive.

14

PLL Loop Filter

Values for the loop filter components should be the same as for the MC44011.

NOTE: The two vee pins are not independent. as they are internally in relationship by means of the input protection diodes.
They must always be connected to a suitable Vee line.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
9-235

MC44145
CIRCUIT OPERATION
Composite Sync Separator
The sync separator is an adaptive slicer. It will output "raw"
sync data. Two outputs are given, thus allowing one output to
be used for composite sync and the other output to be
integrated and then sliced using the inverting slicing amplifier
provided. As the input of the slicing amplifier is external, the
amplifier may be driven from either sync output, although
normally the high output impedance (Sync B) would be
recommended.
The positive video input signal required is nominally 1.0 V
sync-to-white, but the circuit supports signals above and
below this level and also is resistant to a degree of reflections
on the signal. Coupling to the sync separator may be
achieved by a simple capacitor of 100 nF, but better results
may be obtained with a higher value in series with a
resistance of 1.0 kQ.

structure makes up a noise insensitive frequency (and
phase) locked loop.
The phase and frequency comparator provides two logical
outputs, mutually exclusive - up or down - that are used to
source or sink current to and from the loop filter. This current
can be user-selected to be 40 !LA or 80 !LA (typical), thus
providing some degree of loop gain control.
The VCO is an emitter-coupled multivibrator type, with an
on-chip timing capacitor, and has been designed for low
phase noise.
The divide-by-2 is included at the output of the VCO,
thus allowing for a precise 50% duty cycle, hence the VCO
is operating at twice the required frequency. The divider can
be bypassed, bringing the VCO output directly to the output
buffer.
The external divider must provide a feedback pulse to
close the loop. The falling edge of this pulse will be aligned
(when the loop is in lock) with the rising edge of the pulse
applied to the Fref input. Operation of the phase comparator is
insensitive to the duty cycle of both its inputs. The feedback
pulse should have a minimum width of 500 ns. This can be
guaranteed if it has a length of at least 16 output clock cycles
(highest output frequency with the divider disabled).

Clock Generator
The system is best put to use in a dual loop configuration.
The first loop locks to line frequency by means of a type I
phase detector (multiplier type) which is insensitive to
missing pulses. This PLL is then followed by a second loop
using the MC44145, performing frequency multiplication. The
phase comparator of the MC44145 is frequency and phase
sensitive. It is a type IV (sequential type) phase detector,
which does not tolerate missing pulses. The dual loop

APPLICATION INFORMATION
The frame store contains the memory, the necessary logic
for the memory addressing, as well as the counter to set the
frequency multiplication ratio of the line-locked clock
generator (H. Count).

Analog video signals out of the MC44011 are sampled and
converted to 8-bit digital in the AID converter (MC44250) by
means of the pixel clock generator, provided by the
MC44145 (see Figure 1).

Figure 1_

RM
Digital
Multistandard
Decoder

Video
--<~

G(U)

RM
ND

Frame Store

Converter

8M
MC44011

G(U)

8M
MC44250

Pixel Clock
H.Count

Pixel Clock
Generator

Vertical Sync
MC44145

MOTOROLA LlNEARIINTERFACE ICs DEVICE DATA
9-236

MOTOROLA

SEMICONDUCTOR-----TECHNICAL DATA

MC44301

Advance Information
High Performance Color TV IF

_
.

The MC44301 is a single channel TV IF and PLL detector system for all
standard transmission systems. This device enables the designer to produce a
high quality IF system with white spot inversion, AFT and AGC. The MC44301
was designed with an emphasis on linearity to minimize sound/picture
intermodulation.

PSUFFIX
PLASTIC PACKAGE
CASE 724

24

DWSUFFIX
PLASTIC PACKAGE
CASE 751F
(SO-28L)

• Single Coil Adjustment for AFT and PLL
• VCO at 1/2 IF for Minimum Beats
• Simple Circuitry for Low System Cost
• White Spot Inversion
• Symmetrical ± 2.0 MHz Pull-in

ORDERING INFORMATION

• User Selectable Positive or Negative Modulation
• Auxiliary AM Detector for AM Sound

Temperature
Range

Device

• Simple Alignment Procedure

MC44301P

0° to 70°C

MC44301DW

SO-28L

Figure 1. Block Diagram

AFT

9 Switch

--------.,

,, , . . . . - - - - - ,
~Mr-t--o

VCC

,18
L _ _ .,

,
,
,
,
,I 24

Sound

~~--+-~------------~iJf~
I

L_
RFAGC
Filter

11

1

PLL
Lock

-----<>-------20

15

1

Ground

4
Mode Switch

Note: Pin numbers shown are for DIP package only. Refer to Table 1 for pin assignments.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

9-237

Package
Plastic DIP

MC44301
MAXIMUM OPERATING CONDITIONS
Characteristics
Power Supply Voltage - Pin 22

Symbol

Rating

VCC

7.0

V

±500

I!Apk

-

Gating Pulse Amplitude

Unit

Ambient Operating Temperature (Note 1)

TA

oto +70

°c

Storage Temperature

Tstg

-65 to +150

°e

Junction Temperature

TJmax

150

°C

Power Dissipation
Derate above 25°C

PD

1.25
10

W
mW/oe

ELECTRICAL CHARACTERISTICS (VCC

= 5.0 Vdc, TA = 25°e, unless noted.)
Pin (DIP)

Pin (SOIC)

Min

Typ

Max

Unit

Operating Supply Voltage Range
Supply Current

22

27

4.5

-

5.5

70

-

Vdc
mAdc

Differential Input Sensitivity for Full Output

6,7

30

-

I!Vrms

-

dB

Characteristics

Bandwidth
Video Bandwidth

-

7,8

2,3

2,3

-

120
8.0

-

AGe Range
Noise Figure (RS = 300 0)

80
7.0

MHz

Video Amplitude (100% mod depth)

2,3

2,3

-

Tuner AGC Current (10 Vdc; Rpullup = 10k)

10

12

0.6

0.95

-

Differential Gain Distortion
Differential Phase Distortion
(Uncorrected - refer to text description)

2

2

-

2.0
1.0

5.0
5.0

Sound Subcarrier Output

24

28

-

0.1

-

Vrms

AGC Gate Pulse (Rpin = 5.0 k)

13

15

-

±0.3

mApk

6,7

7,8

-

3.4
3.0

-

Lock-up Time

Differential Input Impedance

Rin
Cin

..

..

5.0
2.2

-

Vp-p
mAdc

ms

%
Degrees

kQ
pF

-

NOTE: 1. At Q'C the deVice only tolerates a 5% change In minimum supply voltage (I.e. 4.75 Vdc IS the minimum supply voltage at which the deVice Will function).

Figure 2. Test Circuit
t

Positive
WhHeSpot
Inverted
Negative
AFT
Output

2 } Video
3 Out

/c

*

NC

Mode
4 SwHch

0.047~

Sound
Output

24
NC 23

O.Ot

22
NC 21

0.01

Ground

VCC

+
50

3.0kf
27

6

330

220
7

220

27
17
AFT
SwHch

RF
AGC

VCC
AGC
Adjust

~ 0.1

16

10

15

11 AGC
Fitter

14

12

13

I
1I
I

:t

Connection
for AM
Modulated
Sound
Subcarrier

I
I
I
I
To.l I
I

0.1
~ Lock Detector Filter
3.0k

Envelope Detector Output
AGC Gate Pulse

Note: Capacitors in I!F and inductors in I!H, unless otherwise noted.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

9-238

Envelope
Detector
Input

MC44301
TYPICAL CURVES
Figure 3. AFT Open-Loop Error versus
Closed-Loop Error
2.5
'N'

:I:

1.5

a:
a:
a:
w
c..

0.5

9

-0.5

~

~

0

Tradit!Onal "

0

Z
w

c..

0

-1.5

Table 1. Package/Pin Assignments

\

Description

'"" "
MC44301

-2.5
-300

-200

\

I

"

200

300

Figure 4. AGC Voltage versus
Antenna Input Signal
2.5

III

'U

~ 2.25 Iw

t!I

~

0

>
a:
w
!:i

11111111

IFAGC

1\

IIIII

W

TunerAGC
Region

t!I

I'
0.1

1

1

2

2

Negative Video Output

3

3
4

§;
3.0 ~
a:
w
z

2.0 ~

\

1.0
10
100
ANTENNA INPUT SIGNAL (mVrms)

4

AFT Output

5

6

IF Input (Pos)

6

7

IF Input (Neg)

7

8

Digital AFT Output

8

9

AFT Switch

9

10
11

RFAGC

10

12

AGC Filter

11

13

AGC Adjust or Delay

12

14

AGC Gate Pulse

13

15

Envelope Detector Out

14

16

Lock Detector Filter

15

17

1.0
1000

No Connection

18

Envelope Detector In

16

19

PLL Filter

17

20

VCO

18

21

veo

19

22

Ground

20

23

No Connection

21

Figure S. IF Noise Figure versus IF Input
25

;;;-

w

22

No Connection

23

Sound Output

24

VCC= 5.0Vdc
IIF = 45.75 MHz
RS=300n

:::>

t!I

u::

Vce

20

w

a:

15

sa
0
z
!!:

10

5.0
0.01

V
0.1

1.0
10
IF INPUT SIGNAL (mVrms)

100

1000

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
9-239

24
25,26

No Connection

:E-

5

Mode Switch

t!I

4.0 ~

(.)

VCC =5.0Vdc
IIF = 45.75 MHz
AGC Gate Pulse =
400!lA (4.7 IJ.S)
AGC I~elay = 1.9 V~,~

(.)

1.25
0.01

5.0 ~

i--"'

..:

1.5

6.0

II

TunerAGC

IIIII

2.0

No Connection

No Connection

IFAGC
Region

u:: 1.75

!!:

1111111

28 Pin
(SOIC)

Positive Video Output

No Connection

r-.....

-100
0
100
CLOSED-LOOP ERROR (kHz)

24 Pin
(DIP)

27

28

MC44301
Figure 6. Typical 5.0 V Color TV Application

_~i~!.=-.@.e~~ ~ ____________

I

_

I

Quadrature Phase Correction (Nyquist)

1

~a

1

1

1
1

1

To Pin 17

1
1

1
1

1
500k
82k
0.1
1
1
1_ _ _ _ ~.~a~~r.::'i~ _ _ _ _ _ _ _ _ _ _ _ _ -.J

NC

2

Video Output

Pas Video Out
(Whtte Spot Inv.)
Neg Video Out

AFT Output

AFT Out

". . :u;;;-- I~,"

}"'"

I . 11

68

5.0V--' 1

...

5.0V (VCC)

C4
0.01

C5
5011F

Gnd

(')

C2
27

0:2-

""
:E
U

"'0 {

C3
27
C12

DigttalAFT
Out

PLL Filter

AFT Switch

Env
Detln

~.,...-..=:.j

R17

!-Jv'\II.---::L

0.1

220

~

R18
Cl0
16 1----'VVIr--1f-<>
1.0k
0.1

Lock Det
Filter
Env
DetOut

AGe
Adjust

R14
7.2k

23

0

AGC
Filter

1.0
C15 ~

NC

NJC

RFAGC
TunerAGC

24

VCC

Mode Switch

1) SAW

Sound
Out

AGC
Gate Pulse

R19
13 1---'III.I'v----Q Flyback Pulse
3.0k

5.0V
R15
1.0k

R16
4.7k
NOTES:
1) IF input assumes 75 Q outputfrom tuner. The SAW filter should be low loss «20 dB) with good triple transit response. The Murata SOZ series resin mold SIP
type filter has low loss and good TT response. The PCB enclosed in the evaluation kit accommodates these filters and SAF45MASOZ and Siemens M1963.
The Zenith SAW filter is packaged in a metal can filter.
2) Optional circuitry to improve sound performance by providing additional quadrature and in-phase corrections.
3) The VCO coil is a shielded 10 mm center-tapped inductor. bifiliar wound. See detials in Figure 17.
4) See Figure 17 for coil details.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

9-240

MC44301
CIRCUIT DESCRIPTION
IF Amplifier and AGe
The IF amplifier is a four stage AC coupled amplifier having
a sensitivity of 30 ltV, thus removing the need for a SAW
preamplifier when used with a suitable SAW filter and tuner.
The first three stages are gain controlled, giving an extended
AGC range of 80 dB with improved signal handling. The AGC
to the first stage is delayed as normal so as to preserve the
amplifier's noise figure. Reverse AGC is supplied to the tuner
and provision is made for the usual tuner RF delay adjustment.
The AGC system is gated with a positive or negative pulse.
Flyback gating is used for negative modulation and the video
is maintained constant by the sync tip being kept equal to an
internal voltage reference. When positive modulation is
selected, via the mode switch, back porch sampling pulse is
used and the internal reference is altered such that the video
amplitude remains unchanged. Both polarities of video are
provided, and the same sense is kept at the video outputs by
means of the video switches.

PLL and Demodulation
Following the IF amplifier and preceding the PLL phase
detector is a two stage limiter with a gain of 100 and overall DC
feedback. This contrasts with the usual single stage of limiting
with no DC feedback and diodes with possibly a tuned circuit
at its output. With two stages of limiting, the minimum gain
required to remove amplitude modulation can be designed-in
without the large voltage swings of a single stage with the

same gain. Large voltage swings lead to poor differential
phase performance, hence the need for diodes and a tuned
circuit as used in previous designs. The DC feedback
removes the effects of input offsets which are another source
of differential phase. The combination of low swing per stage
and DC feedback removes the need for having a tuned circuit
atthe limiter output and reduces the danger of IF instability and
radiation. The only problem in using this technique is the
potential for extra static phase shift with resultant errors in the
demodulating angles at the video and sound demodulators.
However, by putting a similar two stage limiter, with a matching
phase shift on the oscillator side of the phase detector, the
demodulating angles can be restored to the correct phases
(0°,90°). Phase errors and hence quadrature video distortion
can also be caused by DC errors in the phase detector and
AFT amplifier (Figure 1). Most of the DC offsets are caused by
mismatches in the current mirrors of the push-pull output stage
(see simplified stage Figure 7). Switches SI, S2 and S3 are
driven by an accurate 1:1 mark/space ratio 1.0 MHz square
wave. Switches SI and S2 maintain the same sense of error
signal, while S2 ensures errors due to the top PNP current
mirrors average to zero on the external loop filter capacitor. In
a similar way, S3 by interchanging 03 and 04 cancels errors
due to the bottom NPN mirror. With phase errors reduced to a
minimum, there is no need for external phase adjustments.
The output of the phase detector is filtered and controls the
VCO to lock at 90°C phase to the incoming IF signal. The VCO,

Figure 7. Phase Detector

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
9-241

MC44301
as shown in Figure 8, is a reactance tuned oscillator at "half IF".
The frequency is doubled by a balanced multiplier, and signals
to the multiplier's input ports are at 90° to each other.
Reactance tuning enables a higher Q to be used in the
oscillator tank circuit as opposed to a phase shift type of
oscillator with the same tuning range. The oscillator being at
"half IF" means that radiation from the external
frequency-determining components will be at half frequency
and so will not desensitize the system even if picked up by the
amplifier input leads (PLL push-off). Running the oscil!ator ~t
twice IF and dividing down, which is another way of solving this
problem, has several disadvantages. First and foremost,
radiation into the antenna at twice IF produces channel 6
problems in the U.S.A. and possibly channel 8 due to
harmonics. It is also much more difficult to produce a stable
oscillator at twice the IF frequency than at one-half IF
frequency. After attaining phase lock, demodulation of the
video is achieved by multiplying the 90° phase shifted signal
(nonlimited) with the regenerated vision carrier (VeO) in a
double balanced multiplier. The sound FM intercarrier signal
is recovered in a similar way by multiplication, but in this case,
the phase relationship of signal and veo is 90° and not 0° as
for the video.

Figure 8.

Differential Phase Suppression
Even with all the care taken in this design, some residual
differential phase still remains. Although low, it would degrade
stereo sound performance. In addition, there is the quadrature
differential phase produced by the IF filter to be considered.
Both produce currents in the output of the phase detector
which in turn phase modulates the veo. This phase
modulation is transferred to the sound intercarrier and hence
produces video related sound interference. With th~ ~orrect
phase of demodulated video, these currents can be eliminated
at the output of the phase detector, as shown in Figure 6, by
the network connected to the PLL filter. The phase detector
current, due to the in-phase differential gain, is cancelled by
the resistor current, while the capacitive current cancels the
quadrature component induced by the IF filter. This technique
enables the level of performance to be taken to the point where
the use of the parallel sound IF is now unnecessary. Here it
should be pointed out that in many cases the improved sound
quality of a parallel sound system has proved to be illusive.
The gain in quality accrued by removing IF filter phase
modulation is often more than offset by imperfections in the
regeneration of the vision carrier (VeO).

veo and Frequency Doubler

Vee

Reactance Stage

Oscillator

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

9-242

Frequency Doubler

MC44301
Video Demodulator and Amplifier
The video demodulator and amplifier are shown in simplified
form in Figure 9. The 90° phase shift of the signal is obtained
by replacing the usual emitter resistors in the differential
amplifier feeding the demodulator by capacitors. The output
currents are 90° with respect to the input voltage over a wide
range of frequencies and small phase errors, caused by
transistor small signal emitter resistances, are corrected by
the cross coupled resistors. This arrangement leads to a
simpler design, the ability to adjust the demodulation angle,
and lower distortion than is normal at the IF
amplifier/demodulator interface. The dynamic emitter
resistances are now in quadrature with the capacitive
reactance and therefore contribute very little to the resultant
output. Although the current outputs of the demodulator are in
antiphase, the voltages at A and B are forced by the feedback
loop to be in phase. Level shifting from the top supply to the
bottom rail is within the feedback loop, and RF components
are filtered internally. The advantages of this configuration are
improved linearity with lower sound/chroma beat products;
differential to single-ended conversion of the demodulator
output; accurate control of the peak white video level, and low
levels of high frequencies at the video outputs. The positive
video output is intended to be used as the actual video and is
acted upon by a white spot noise inverter. This effectively
removes the "whiter than white" noise produced by a true
synchronous demodulator and prevents the CRT from being

overdriven and defocused. The negative video output is not
acted upon by a white spot noise inverter and, of course, the
noise output from a synchronous detector does not contain a
DC component. Hence, this drive should be used as the sync
separator drive because a simple preseparator low pass noise
filter will give optimum sync performance.

Sound Output
A separate quadrature demodulator is used to recover the
intercarrier sound signal. The IF signal and VCO have a 90°
phase relationship at the detector's input ports instead of the
0° required at the video demodulator. This ensures that the
only video components appearing at the output will be high
frequency components. A consequence of the quadrature
relationship of the demodulator signals is that the low
distortion capacitive input stage used in the video
demodulator cannot be used. Instead, a new linear wideband
differential stage has been designed where the distortion in
the output currents, caused by emitter/base diode
nonlinearities, is cancelled by the current through the R2
resistor. A reduction in THD of 20 dB is obtained, compared to
a simple differential amplifier even at 120 MHz. The
combination of a linear input stage and a post demodulation
feedback amplifier results in quadrature intercarrier sound
demodulation having lower video interference than sound
recovered in the normal way from the video channel.

Figure 9. Video Demodulator and Amplifier

Video Outputs
A~--------~--~~~~--~~--~----~--------~-

OSC

-VIF

IR

Vector Diagram

I
-0

Impedance Diagram

(rell + rel21 ,

Xc
-=:::::::::::::
Zr

Zr = j Xc2 + (rell + rel21 2
MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

9-243

MC44301
Figure 10. Sound Demodulator

osc

Vref
VIF--+---t

I----Ji---- -VIF

AFT
The AFT portion of the circuit is the most unconventional in
form. Essentially, AFT is derived by amplifying the error Signal
and applying this to the local oscillator in the tuner, thus
eliminating a coil and a potential IF instability problem. After
acquisition (phase lock) when the circuit has reached its
steady state condition, due to the much higher gain in the La
loop, the veo will have moved a small amount (D.fv) from its
nominal frequency, and almost all the original IF error (D.fe) will
have been corrected by a change in the La frequency (D.fl). In
this way, provided the local veo loop can initially be phase
locked to the incoming IF signal, the veo can be used as the
frequency reference for the AFT system. It follows from the
above, therefore, because the system is phase locked, that
D.fe = (D.fl +D.fv). The combination of local veo loop and the
loop produced by feedback to the local oscillator forms a
double-loop PLL. Analysis shows that overall system stability
can be assured by treating the veo as a stand alone PLL,
provided the bandwidth is much wider than the La loop. The
veo loop therefore is a low gain wideband loop which
guarantees initial capture, while the La loop is basically a high
gain De loop used to keep frequency and phase offsets to a
minimum.
The AFT system is designed to acquire the vision carrier,
without false locking to the sound or adjacent sound carriers,
with an initial error of ±2.0 MHz being reduced to 10kHz to
20 kHz when locked (U.S.A.). This contrasts with the
discriminator type of AFT which has highly asymmetric lock
characteristics (-2.0 MHz + 1.0 MHz), because of the effects

of the IF filter, and large closed-loop errors caused by limited
loop gain (see Figure 3). To achieve this level of performance
without encountering the normal AFT problems associated
with high loop gain (large De offsets, etc.), a novel approach
has been taken to locking up the PLL. In the absence of an IF
signal, the acquisition circuitry examines the state of the video
(I) and sound (Q) demodulators and detects the lack of a
signal. The filtered output of the lock detector then sits at
approximately 2.7 V. Under these circumstances the La drive
is clamped to a reference voltage and an offset applied to the
yeo. This is done in such a way that the IF signal (should a
signal appear) and the veo are sitting in the center of the IF
filter passband. Therefore, even if the La drifts high by as
much as 2.0 MHz, the signal will not be significantly attenuated
by the filter. On the arrival of a signal, beat notes appear at the
outputs of the demodulators, the output of the lock detector
goes low and a sweep generator is switched on. The
generator immediately sweeps the veo an additional -2.0
MHz from its out of lock mid-band nominal frequency. During
this negative sweep, the PLL phase detector is switched off so
phase lock cannot be obtained. The veo is then swept
positive from -2.0 MHz to +2.0 MHz of the nominal out of lock
frequency with the phase detector switched on. The PLL will
therefore lock to the first carrier it encounters. This in fact must
be the vision carrier because the sound carrier is more than
2.0 MHz below the nominal frequency and the adjacent sound
carrier is higher than the vision carrier. On achieving lock, the
lock detector output goes high. When this happens, the AFT

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

9-244

MC44301
clamp is released, the veo offset is slowly removed, the
sweep generator is inhibited and the phase detector remains
permanently enabled. With the AFT clamp removed, a large
error voltage appears at the AFT output, driving the system
back to the correct frequency. Since the La loop is slow and
the veo loop is fast, the IF changes slowly and the veo tracks
it, maintaining phase lock until the final static conditions are
reached. For large frequency errors during this period, the
slew rate of the La loop is increased but not to the extent
where it would cause any veo tracking problems. This
technique allows the acquisition time of the circuit to be
considerably shortened while still using a larger than normal

time constant in the La loop. In this way, any possibility of
phase modulating the La with video is removed. Figure 11
illustrates the AFT system in action.
To accommodate all types of tuners the Las, positive or
negative La drive can be selected externally by operation of
the AFT switch. The AFT switch also has a third position which
disconnects the drive to the tuner. Under this condition,
the TV set can be tuned in the normal manner and so appears
to have a conventional type of AFT. Other PLL systems cannot
be tuned manually in this way, having an abrupt
capture characteristic, and because of this, have not gained
general acceptance.

Figure 11. The AFT System In Action

Typical IF Input
Filter Response

IF Bandpass

Properly Tuned Channel

8J

Adjacent

I
I
I
I

t tS

AP

t

t t
S

P

AS

I

I
I

I
I
I

I
I
I

ttl

Desired

AP

p

AS
Desired

Adjacent

Initial nominal offset of VCO and LO (AF1). When a beat note is
detected, AFT bias is held and VCO is swept another 2.0 MHz low with
phase detector inhibHed, then the VCO is swept high wnh the phase
detector active. Upon phase lock, the AFT clamp is removed and the
initial veo offset is slowly removed. capture of desired picture carrier is
assured even Hmistuned ±2.0 MHz.

I

t

t t
P

Nominal Channel with Initial 2.0 MHz Offset

-2.0 MHz Mistuning with Initial 2.0 MHz Offset
+2.0 MHz Mistuning with Initial 2.0 MHz Offset

AS

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

9-245

MC44301
APPLICATIONS INFORMATION
Alignment
The alignment of the MC44301 is very simple and
inexpensive compared to other IF amplifier circuits, especially
those using PLL demodulators. With a CW input signal of
correct picture carrier frequency, the LO side of the B.2 kQ
resistor in series with the loop is connected to a DC supply of
approximately 2.5 V. The DC supply is adjusted until the output
of the tuner is 45.75 MHz. The VCO coil is adjusted until lock
is obtained and the voltage across the B.2 kQ resistor is zero.
The DC supply is then removed (refer to Figure 12).
Component Selection
The IF input assumes 75 Q output from the tuner. A SAW
bandpass filter is used which has a low insertion loss while
maintaining good triple transit response. Recommended
sources forthis filter include Murata BOZ series, SAF45MA80Z
and Siemens M1963, which are packaged in a 5-pin SIP
plastic package. Pinouts are identical, but the interface
matching to IF will need to be modified for best performance.
The evaluation PC board is laid out to accept either the SIP or
a more expensive metal can filter.
The
coil is a bifiliar wound, center-tapped, 10 mm size
shielded inductor, Figure 17 shows the construction details.
Recommended sources for the (45.75 MHz IF) coil are TOKO
TKANAS-T1390ADP, and Coilcraft M1300-A. For a higher IF
frequency, the coil inductance must be decreased. In this
case, the coil may be a custom having windings similar to the
specified coil in Figure 17. Note that this coil has the same
number of turns on both sides of the center-tap.

veo

Evaluation PC Board
The evaluation PC board schematic in Figure 13 and the
layout in Figures 14, 15, and 16 show a double sided board
which is designed to accommodate additional external
components and circuitry intended for use in 12 V systems
and various tuner systems and applications. An optional sync
separator circuit is recommended where a flyback pulse is not
available, such as in set-top converters. Other optional
circuitry is shown which helps to further improve the sound
performance through additional quadrature and phase
corrections. This is shown in the schematic for the Rev B
evaluation PC board (Figure 13).
PCB Layout Considerations
The typical 5.0 V application circuit shown in Figure 6 uses
a single sided PC board with very few external components.
To maintain optimum performance, the placement and
interconnection of some components such as the SAW filter
and VCO tank are critical. These components are placed
close to the IC 10 enable short trace lengths which are
symmetrically placed and equal in length to avoid differential
offsets and noise. In a single sided PC board layout the ground
should flow around the device, and around the Vce trace and
other circuit traces as a continuous "sea of ground". Since the
IF is very stable and immune to radiation, the device can be
mounted on a single sided PC board without the customary
and necessary shielding required in other IF systems.
However, do not use prototype and wire wrap
construction techniques.

Figure 12. Alignment Configuration

CW
Picture 0---+--1
Carrier

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

9-246

MC44301
Table 2. Pin Function Desription
24 Pin
(DIP)

28 Pin
(SOIC)

1,21,

23

1,4,11,
18,24,
25,26

2

2

Functional Descrlptlonl
External Circuit Requirements

Equivalent Internal Circuit

No Connection.

Positive Video Output
With White Spot Noise Inversion
In the evaluation PCB a discrete external buffer (2N4402)
is used to provide interface - this is not needed in the
actual application.

Vee

Positive

60

+--'WIo---o Video

Output

2.7k

3

3

Negative Video Output
Without White Spot Noise Inversion
Intended for sync separator use.

Vee

Negative

60

+-_........- - 0 Video

Output

1.6k

4

5

Mode Switch
Selects positive or negative modulation. The pin is open
for negative going video and grounded for positive
going video.

1.0k
3.4k

Mode
Switch

1.8k

5.6k

5

6

Vee

.4.._+---0

AFT

Output

AFT Output
High output impedance push-pull current drive. Intended
to give high AFT loop gain when used with high load
impedances (i.e. direct connection to the tuner varactor
diode). Drive is greatly increased for large frequency error
to minimize pull-in time and clamped when PLL is not
locked. External circuitry is provided in the evaluation PCB
to allow adjustment of the drive to the tuner. This will not be
needed in the actual application where the tuner is
compatible with the IC. Polarity is controlled externally by
the AFT switch.

(continued)

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
9-247

MC44301
Table 2. Pin Function Description
24 Pin
(DIP)

28 Pin
(SOIC)

6, 7

7,8

Functional Description!
External Circuit Requirements

Equivalent Internal Circuit
IF Inputs

Input leads should be kept short and symmetrical to avoid
instability problems. The performance of the IF is greatly
dependent upon the characteristics of the IFfilterand upon
the proper matching of the filter to the IF input. Refer to the
evaluation circuit for recommended filters.

8

9

Digital AFT Output

Vee

This is a tristate output having a ±300 kHz dead zone.
Polarity is controlled externally by the AFT switch.

+---0

9

10

Digital AFT

Output

Vee
24k
1---t----1~VIr--o

S.lk

AFT
Switch

AFT SWitch
AFT is designed to accommodate all types of tuners and
Las. On the evaluation PCB, a jumper matrix provides
three positions: 1) AFT switch pin to VCC for positive
La drive, 2) AFT switch pin to ground for negative LOdrive
and 3) AFT switch pin to open which disconnects drive to
the tuner.

24k

10

12

RF AGC Output

Vee

The output is designed for a reverse AGC tuner and will
only sink about 0.8 rnA maximum. At 5.0 Vdc VCC, the
maximum voltage on this pin is 5.8 Vdc, due to an internal
clamping diode. In an application in which the tuner does
not have a pull-up resistor, one must be added to the
external circuit. With a tuner supply voltage at 8.0 Vdc, the
load resistor should be at least 10 kn or greater.

RFAGe

Output

(continued)

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

9-248

MC44301
Table 2. Pin Function Description
24 Pin
(DIP)

28 Pin
(SOle)

11

13

Equivalent Internal Circuit

Functional Description!
External Circuit Requirements
AGC Filter, AGC Control Voltage
Voltage level at this pin indicates AGe action by three gain
control ranges. Increasing voltage at this pin gain reduces
the tuner or IF.

oVdc to 2.5 Vdc is the IF initial control range,
2.5 Vdc to 4.0 Vdc is the nominal tuner RF control range,
4.0 Vdc to 5.0 Vdc further gain reduces the IF for very
large signal level at the antenna.

Fmer

12

14

13

15

RF Tuner AGe Delay Adjustment
Below the potential set at this pin, the IF AGe is active and
the tuner AGe is non-active. Above the potential set the IF
amplifier gain is held constant while the tuner is gain
reduced. The tunertakeover point normally corresponds to
a 1.0 mVrms to 2.0 mVrms signal into the antenna. Thus,
as the input increases beyond this level, the tuner AGe will
activate, clamping the input drive into the IF at the
associated 1.0 mVrms to 2.0 mVrms antenna threshold.
The external AGe adjust network shown in Figure 13
provides 2.0 Vdc ± 0.2 Vdc at the AGe Adjust pin.
This network may be modified for the desired range
and resolution.

Vee

22k

r--r~~~-+--+-~--~AGe
Gate

6.ak

AGe & Lock Gating Input
A 300 ).IA current pulse is required at this pin to gate on the
AGe and lock systems. In most TV applications where
negative modulation is used, theflyback pulse can be used
to gate the AGe through a resistor. In applications where
flyback is not available, the gate pulse can be acquired via
a sync separator from the video output at Pin 2. The circuit
shown in Figure 13 insures thatthe gate will be acquired in
the proper time and level from the sync pulse.

6.ak

(continued)

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

9-249

MC44301
Table 2. Pin Function Description
24 Pin
(DIP)

28 Pin
(SOIC)

14

16

Functional Description!
External Circuit Requirements

Equivalent Internal Circuit

Envelope Detector Output
Detector for AM sound modulation
descrambler signal).

Vee

(SECAM

or

Envelope
Deteclor

Output

15

17

PLL Lock Detector
With 5.0 Vdc Vcc. lock is indicated by approximately
4.3 Vdc and zero signal is indicated by approximately
2.7 Vdc on this pin.

Vee

t--'l1VY----t---o PLL Lock
Detector

16

19

Envelope Detector Input
AM sound subcarrier input.

Vee

Envelope
Detector

0--'1/1110--.....-1

Input

17

20

PLL Filter
The phasedetectoroutputaiterfiltering produces a voltage
which controls the frequency of the VCO. With 5.0 Vdc
VCC. there is approximately 3.2 Vdc present when VCO is
locked and 3.1 Vdc when unlocked.

(continued)

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

9-250

MC44301
Table 2. Pin Function Description
24 Pin
(DIP)

28 Pin
(SOIC)

18,19

21,22

Functional Descrlptlonl
External Circuit Requirements

Equivalent Internal Circuit

veo

VCOlnputs
Care should be taken in layout by placing the VCO tank
close to the IC pins with symmetrical traces to the shielded
inductor. A center-tapped, bifiliar wound coil, previously
defined, provides symmetrical tuning about the VCO
frequency. The external VCO operates at half the IF
frequency and is doubled on the IC chip.

r-

Inputs

4.7k

4.7k

rYYl
I

I

2D

23

Supply Ground
Care should be taken to provide a continuous sea of
ground or fill olthe ground around the part, and traces in a
single-sided PCB layout or a full ground plane on the
component side of a double-sided layout.

22

27

Supply Voltage (VCC)
Good RF decoupling must be provided close to this pin. At
25°C, maintain between 4.5 Vdc to 5.5 Vdc. At DOC do not
use less than 4.75 Vdc.

24

28

Sound Carrier Output
Due to quadrature demodulation, the video components
are suppressed at this output. However, with a vestigial
sideband signal, high frequency video components will
be present.

Vee

~
60

e

Sound
Carrier
Output

5k

,J;
Note: Most pins on the Ie have electrostatic protection diodes to vee and to ground. It is therefore imperative that no pin is taken below ground or above Vee by
more than one diode drop wijhout current limiting.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

9-251

MC44301
Figure 13. MC44301P Universal Evaluation Circuit Schematic
Rev8-PCB

_~i~~

r

________________ _

I

Ouadrature Phase Correction (Nyquist)

1

I
I
I

5p-25p

1

To Pin 17

1

1

I
R3

1

Video
Output
J7

I

1
500k
82k
0.111
1
1_ _ _ _ ~-~a~~r~i~ _ _ _ _ _ _ _ _ _ _

Output

JI
r-

J ,------,
Used In Evaluation PCB
12V

1

Sound
Out

NC

Neg Video Out

4

Mode Switch

I J14
I

1

R16
68

1

Pos Video Out
(White Spot Inv)
3

24 \-----0 J5

NC

23

1

I
1

1

1

I

VCC

1
1

01
J3

AFT Out

m.----

JlR13
IF
Input 68
J2

SAW
Filter

I

}"'"

r--=--=--=---..,
R12

1

ll.
,....
0
M

I L1
l.~IlH
I

Ll~ _ _ _ _
1
I~

""
~
==

Gnd

Digital AFT
Out

PLL Filter

Used In Evaluation PCB
Off.

AFT Switch

Env
Oetln

3 12

Env
Oet Out

AGC
Filter

C151

AGC
Adjust

R14
30k

~--~--+--t-o J13,

2)

R20

AGC
Gate Pulse

J15,
J16

C2
27
C3
27

C12
R17
1-------'::-'0."-1
1 ~
R18
CIO
16 1-----'V'VIr--;(-o
1.0k
0.1

Lock Oet
Filter

RFAGC
1.0

lN5231 I
___
J

~{

-1

Tuner
AGC
J4

I

NC

,---I
R21
1.5k

1

J9 r - - - - . J
I
01
I
2N4402

12V
R15
1.0k
J15
R23
5.6k

I
I
I
I
I
I
I
I
I

Sync
Separator
R22
1.1k

ToVideo Out
(Base of 02)

_In
_Evaluation
_ _ _PCB
_ _ _ _ ---1I
IL _
Used

NOTES:
1) See Figure 17 for coil details.
2) Capacitors should be close tolerance, high 0 components, such as silver mica - to insure dynamic frequency response and minimum bandwidth.

MOTOROLA LlNEARIINTERFACE ICs DEVICE DATA

9-252

MC44301
Figure 15. Component Placement
and Silk Screen View
HI

0

Figure 16. Component Side of PCB

o

H4

•

· =.0.
.00

••

•

_- 0

0

8
_._

•

•

0 ••0

••• g••
••••••
•

0

• • • •___•

.. io." ....
... .......0........ .
•••• •• •• • •
• .0.. 0
• :..

O.

0 •••••••••••• 0

•• :

•

.0.0

0
•

•

0 •••

o • • • •0

• ••• ••• g

o

I ••• • 0

•••••

••

•0

• 0

H3

•

0

Figure 17. Circuit Side of PCB

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
9-253

•

MC44301

Winding Instructions

windings at the "F" pin. Wind the wire in the same direction,
making sure it is wound tightly around the bobbin. The wire
must be tinned to obtain the necesary solder connections.
Application of solder directly to the enameled wire will remove
the enamel and adequately tin it.

Use 38 AWG enameled wire. Start at "ST" pin, go to the top
of the bobbin: wind 2-1/2 turns on the first tier; 3 turns on the
second tier; 2-3/4 turns on the third tier, then go to the center
tap ·CT" pin. From the CT wind 2-3/4, 3 and 2-1/2 turns on the
first, second and third tiers respectively, then finish the

Figure 18. Winding Details for the VCO Coli

Number of turns from ST to CT

2-1/2

3

2-3/4

000

000

000

1st
Tier

2nd
Tier

3rd
Tier

000

000

000

2-3/4

3

ST

CT

F

2-1/2

Number of turns from CT to F

Blfiliar Wound 16-1/2 Turns

CT

8-1/4 Turns

F

8-1/4 Turns

(Schematic)

(Bottom Vlerw)

(TaKa Type 10k Series or Coilcraft Slot 10 Series Bobbin. Recommended
sources for the coil are TaKa TKANAS-T1390ADP and the Coilcraft M1300-A)

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
9-254

MOTOROLA

MC44302

SEMICONDUCTOR-----TECHNICAL DATA

ADVANCED MULTISTANDARD
TV VIDEO/SOUND IF

Product Preview

Advanced Multistandard TV
Video/Sound IF

SILICON MONOLITHIC
INTEGRATED CIRCUIT

The MC44302 is a new multistandard single channel TV Video/Sound IF and
PLL detector system for all standard transmission systems. This device enables
the designer to produce a high quality IF system with white spot inversion, AFT
and AGC. The MC44302 was designed with an emphasis on linearity to minimize
sound/picture intermodulation.
Features:
• Single Coil Adjustment for AFT and PLL
• VCO at 112 IF for Minimum Beats
• Simple Circuitry for Low System Cost
• White Spot Inversion
• Symmetrical

PSUFFIX
PLASTIC PACKAGE
CASE 710

± 2.0 MHz Pull-In

• User Selectable Positive or Negative Modulation
• Simple Alignment Procedure
• AGC Gating Input Options
Sound Features:
• Self-Tuning, Low Distortion FM IF Demodulator
• AM Sound IF for SECAM
• Sound Muting

DWSUFFIX
PLASTIC PACKAGE
CASE 751F
(SO·2BL)

• Variable and Constant Audio Outputs
Added Features Will Include:
• FM IF Demodulator
• AM Sound IF for SECAM

ORDERING INFORMATION

• AGC Gating Input Options
• Mode Select Pin for Selecting M, B-G-I, Lor D2MAC

Device

• Sound Muting

MC44302DW
MC44302P

Temperature
Range
A' to + 70°C

Package
SO-2BL
Plastic DIP

PRODUCT DESCRIPTION
Advanced TV Video/Sound IF for PAL, NTSC, SECAM and AM D2MAC
The MC44302 is a new multistandard TV Video/Sound IF
SECAM (system L), NTSC (system M), and AM D2MAC.
that will have the present MC44301 as its basis. All present
Added features include self-contained AGC systems, AM and
FM demodulation, volume control, and circuitry designed to
features and performance (with the exception of the AM
meet Peri-TV socket requirements. PAL, NTSC and SECAM
detector) will be retained.
are selected via Pin 11 (voltage level) and AM D2MAC by
The circuit will demodulate the sound and video of all of the
world's major television systems, namely PAL (system B, G, I),
grounding Pin 16 (normally used as a PLL filter).

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

9-255

MC44302
Modes
PAL - In the PAL mode the AGC is self-gating via a horizontal PLL which is locked to the video. The gating pulse
samples the video level during the sync interval.
FM sound demodulation is active in the PAL mode. The
FM demodulator is self-tuning over the range of 5.5 MHz to
6.0 MHz. Other frequencies can be chosen by externally
switching a capacitor on Pin 3. The FM demodulator has low
distortion (approximately 0.1 %) with better than 70 dB signal
to noise ratio.
Two sound modes are possible in PAL; with and without
sound muting. The sound output also has constant and variable audio outputs which meet the requirements of the European Peri-TV socket.
External audio can be switched through to the variable output via Pin 3. The internal variable signal is inhibited, but the
internal constant audio still appears at Pin 24. This means
that the external audio signal can be used internal to the TV
chassis and its level adjusted via the volume control (Pin 1),
while the internal audio can be taken from the constant output
(Pin 24) via the Peri-TV socket to some external device such
as a VCR.
SECAM - An advanced form of back porch gated AGC is
used in SECAM mode. A long term peak white detector also
controls the video output level over a limited range, correcting
for any errors in the transmitted black level. In this way the
AGC system retains the accuracy of a peak detecting system

without the usual sacrifice of speed. The peak white detector
uses the FM AFT filter capacitor at Pin 7. Thus the need for
an extra pin and capacitor for this function is avoided.
The video switches maintain the same video sense as in
PAL at the video outputs. The FM demodulator circuitry is disabled and the AM demodulator is switched on. All other aspects of the sound system are similar to PAL with regards to
the audio switching.
NTSC - The AGC system is the same for NTSC as in PAL
mode. Both FM and AM demodulators are active when NTSC
mode is activated. The demodulator FM is routed to the variable audio output to be used as the TV chassis drive for the
loudspeaker. At the same time, the AM output is fed to the
constant output. This can be used for suppressed sync
scrambling systems, where the sync is on the sound carrier,
to recover the sync signal.
Grounding Pin 3 when in the NTSC mode inverts the output video polarities. This is useful in scrambling systems that
invert the video from line to line.
AM D2MAC - In this mode, the AGC system is a simple,
very long time constant peak detector. The FM AFT filter capacitor at Pin 7 is used for this time constant.
Both the FM and AM sound demodulators are switched off.
This is to prevent interference with the D2MAC digital sound
in the sync system.

Simplified Block Diagram
RF
AGC

IF
Input

Mode
VCC SW

AFT

AFT
SW

PLL

VCO FM AFT

IL

Audio Out
(VAR)

AGC
Riter

Volume
Control
Gnd

Flyback/
Video
Filter
Input DMAC Select

Sound
Out

Lock

'--'V---'

Video
Out

Audio In/
AudioSW

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
9-256

MC44302
Single-sided board with GND between pins. The boards
are to be single-sided, standard FR-4, with a tin-lead
finish. There are no plated-thru holes and no solder mask
is required.

PIN CONNECTIONS

R~~j.

~
-=-

SW3

10nF

A~
27k

TP3

-=-

ToA

Volume
Control

~F-TOB

Sound In (FM)

2.0k 1.0nF

Audio Out
(Variable)

Audioln~

r~
-=- SW4 100nF

Audio In !Video
Audio SW Invert

Quad
Coil

FM
De-Emphasis

VCC

Neg. Video
Output

Audio Out
(Constant)

Pos. Video
Output
To Pin 19

FM AFT Filter/
Peak White Filter

Gnd

22

IF Input

VCC
IF Input

IJI

I

Mode
Switch

AFT
Output

AFT
Switch

Flyback/
Video input

17

~ From C

20nF

VCC
2.7k

L......-

50nF

10k

13

~--L--'

H PLL Filter/
DMACSelect

RFAGC

16

rlh_

r
~

200nF 1.5k

T.P.l
AGC
Fmer

RFAGC
Adjust

-

15

.J~~

~VCC
-=- 4.3k 1.0k 6.2k

r'MNv-.,.-o AFT to Tuner
200

10nF

* Siemens M1963, Murata SAF45MA80Z

**

TOKO TKANAS-T1390ADP
COILCRAFT M1300-A

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
9-257

MC44615A

MOTOROLA

SEMICONDUCTOR-----TECHNICAL DATA

Advance Information
Convergence Waveform Generator
IC for Projection TV

WAVEFORM GENERATOR
IC FOR PROJECTION TV

The MC44615A is a bipolar integrated circuit designed to be used with the
control circuitry for projection television convergence systems. The function of
the integrated circuit is to generate the required voltage waveforms that will be
applied to the convergence control circuitry. This control circuitry will apply them
in the proper amplitude and combination for use in driving the convergence coils.
• Multistandard Operation Capable (10 kHz::; fH::; 63 kHz) (45::; Iv::; 120 Hz)
• Constant Amplitude Outputs, Independent of Frequency
PSUFFIX
PLASTIC PACKAGE
CASE 711

• Complementary Output Waveforms
• Blanking Control of Output Waveforms
• Horizontal Phase Advance
• Standard Supplies (±5.0 Vdc)
Functions (Nine Waveforms):
• Horizontal and Vertical Ramp

PIN CONNECTIONS

• Horizontal Parabola and Vertical Parabola

o

• Horizontal Ramp and Vertical Ramp Product
• Horizontal Parabola and Vertical Parabola Product

VEE
Yin

• Horizontal Ramp and Vertical Parabola Product

Iv

• Horizontal Parabola and Vertical Ramp Product

IVset

• Horizontal Cubic

-V
+v

Simplified Block Diagram

fv

fVset
37

V2clamp
_V2

Output Waveform Clamps
15,18,21,24,27,30,34

+v2
35

36

Hv2clamp

32

-HV2

33
28

+HV2

29

H2v2clamp
-H 2v2

25
26

+H2v2

22

H2Vclamp

23

-H2V

19

+H2v

20

11
12

(Top View)

13

14
16
17

ORDERING INFORMATION
Device

Temperature
Range

Package

MC44615AP

0° to +70°C

Plastic DIP

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
9-258

MC44615A
Figure 1. MC44615A Test Circuit

Vcc
Blanking and
Clamping Logic
VPin2 <2.5V
OulplJl=OV

401------.--~

100nF:f

10nF :f

f---o!--- Vin

Hin-----j

III

I

• Polystyrene

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
9-259

MC44615A
MAXIMUM RATINGS
Symbol

Value

Unit

Supply Voltage - Positive
-Negative

Rating

Vee
VEE

+6.0
-6.0

Vdc

Ambient Temperature
Storage Temperature

TA

01070

°e

Tstg

-6510+150

°e

Junction Temperature

TJ

150

°e

RECOMMENDED OPERATING CONDITIONS
Characteristics
Supply Voltage - Positive
-Negative
Horizontal Sync
Frequency - Max
-Min

Pln(s)

Symbol

Value

Unit

1

+4.5 to +5.5
-5.5to-4.5

Vdc

40

Vee
VEE

3

Hin

kHz
63
10

Pulse Width - Max
-Min
Pulse Amplitude - Max Voltage (Tip)
- Min Voltage (Baseline) (see Figure 2)
Vertical Sync
Frequency - Max
-Min

39

Vin

Pulse Width - Max
-Min

12
2.0

I1S

Vee
VEE +0.5

Vdc
Hz

120
45
12
5.0

Pulse Amplitude - Max Voltage (Tip)
- Min Voltage (Baseline) (see Figure 2)
Peak Output Load eurrent

11-14,

IL

Vee
VEE +0.5

Vdc

±2.5

rnA

16/17,19/20,
22123, 25/26,
28/29, 32133,

35/36

FUNCTIONAL DESCRIPTION
Introduction
The MC44615A will provide 9 pairs, a function and its
complement, of waveforms. These waveforms can then be
used by the projection control circuitry for convergence.
The inputs ofthe MC44615A are the horizontal and vertical
frequencies and an optional blanking input. Adapting this
device to these frequencies is made by choosing external
resistor - capacitor pairs. The enable input, a threshold sense
that trips nominally at 2.5 V, can be used to delay the
appearance of the waveforms and/or to tum off the waveforms
during the blanking interval (or at any other time).
Inputs
Waveforms to the horizontal and vertical inputs (Pins 3, 39)
must meet similar requirements except for the frequencies
involved. The requirements can be described as follows:
3.0 V < Yin Peak < 5.0 V;
-4.5 V < Yin Baseline :s; 2.0 V.
2.0 11S:s; Pulse Width < 1/(fH) (Horizontal Input);
2.0 11S:s; Pulse Width < 1/(fv) (Vertical Input);
and the allowable frequencies of operation are:
10 kHz:s; fH:S; 63 kHz,
50 Hz:s; fH:S; 120 Hz

Figure 2 shows these requirements.
Figure 2. Valid Input Levels for Both
Horizontal (Pin 3) and Vertical (Pin 39) Inputs
5.DVmax
3.DVmin
2.DVmax
-4.5 Vmin

•• - - - - -

The blanking input, Pin 2, presents at least 500 kn to
external signals and has a threshold of approximately
+2.5Vdc. At voltages greater than this threshold, the outputs
are present. This pin can be biased high to keep the
waveforms on, controlled by an external voltage to blank the
output waveforms when desired, or charged-up with an
external RC to delay the appearance of the output waveforms
during power-up. During blanking, the output voltages are
oVdc ±50 mV and power supply current remains unchanged.
Since the input pins are all equipped with ESD diodes,
voltages on these pins should never exceed VCC or VEE by
more than 0.5V.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
9-260

MC44615A
ELECTRICAL CHARACTERISTICS (VCC = +5.0 V, VEE = -5.0 V, RL = 2.5 kQ, TA = 25°C, fH = 31,250 Hz, fv = 31,250 Hz,
see Figure 1)
Characteristics
Supply Current
Output DC Offset (all outputs when Pin 2 ,;; 2.0 Vdc)
Horizontal Delay Output
Voltage Level - Low
-High

Pin
1
40

Symbol

7

Hadv

Timing (relative to Pin 3)
(@ +750 Hz offset from fHfree run)
(@ -750 Hz offset from fHfree run)
Ou~ut Waveform Phase, Advance (involving horizontal functions)
( adv = 1200 pF, Radv = 10 kQ)

ICC
lEE

Min
25
-50

Typ
33
-43

Max
40
-35

Unit
mA

-50

0

50

mV

-1.5
+0.7
-1.5
-1.1
-1.9

-1.1
+1.1
0
+0.4
-0.4

-0.7
+1.5
+1.5
+1.9

Vdc

7.0

7.6

8.2

±750

± 1300

4.4

4.9

-

-

!1S

+1.1
~s

tadv

kHz

Pull-in Range
(CH = 1.0 nF, RF = 750 kQ)
Horizontal Ramp - Amplitude
-Linearity

11,12

Horizontal Parabola - Amplitude
-Symmetry

13,14

Cubic - Amplitude
-Symmetry

16,17

Vertical Ramp - Amplitude
-Linearity

35,36

Vertical Parabola - Amplitude
-Symmetry

32,33

±H
±H2

5.4
2.0

Vp-p
%
Vp-p
%

2.7

-

-

3.3
12

4.1

4.9

-

5.9
12

Vp-p

±V

4.4

4.9

5.4
2.0

Vp-p

±V2

2.25

3.3
12

Vp-p

±H3

2.25

-

-

-

-

2.7

-

%
%
%

Vp-p

Horizontal Ramp,
Vertical Ramp Product
Vertical Parabola Product
Horizontal Parabola,
Vertical Ramp Product
Vertical Parabola Product
Waveform Output Resistances
All Outputs

19,20
28,29

±HV
±HV2

4.0
4.0

4.8
4.9

5.8
5.8

22,23
25,26
11,12,13,
14,16,17,
19,20,22,
23,25,26,
28,29,32,
33,35,36

±H2V
±H2V2

2.1
2.0

2.63
3.0
100

3.25
3.6

Vp-p

-

-

Q

Horizontal Timing
To insure proper horizontal timing, the MC44615A uses a
Phase-locked-Loop to provide a reliable time base. The loop
is externally accessible at the current controlled oscillator
(ICO) (Pin 4, 5) and at the output ofthe phase detector (Pin 6).
Figure 3 shows relevant internal circuitry and pin connections.
This allows the system designer to tailor the timing and
performance of the MC44615A.
The ICO is an RC type in which the horizontal frequency is
determined by the charge and discharge rate of the capacitor
at Pin 4. During charging, the voltage on the capacitor (CH) is
increased until it reaches an internally determined trip level.
At this trip level the direction of the current at Pin 4 is reversed
and the discharge process begins. During discharge, circuitry
diverts the current available at Pin 4 internally and the
capacitor discharges quickly to the bottom trip level where
control circuitry switches the direction of Pin 4 current and the
cycle begins again.
The charging current at Pin 4 is determined by the current
out of Pin 5, which is mirrored at Pin 4. The current out of
Pin 5 is set by a nominal 1.25 V stable reference and the
resistance at this node. This also provides a means of

modulating the charging current at Pin 4 by injecting the error
current from the phase detector at Pin 6 to Pin 5.
At Pin 6, and connected to Pin 5 by the· feedback resistor
(RF), are the filtercomponentsoflhe HpLL. Thesecomponents
were chosen to insure fast tracking over the possible
horizontal operating frequencies. (Refer to application notes
AN553 and AN921 for information regarding design of
the filter.) The effect of this filter and the other HpLL
components provides a capture range equal to the lock range
and a stable horizontal time base over the possible horizontal
operating frequencies.
The error current from the phase detector is determined by
the product of the pase detector sensitivity (~) and the phase
error (CPE) between the inputs Hin and at Pin 8. The voltage
difference between Pin 6 and Pin 5 will change to
accommodate the error current.
IERROR = 11 CPE,
where the phase detector sensitivity is,
11 = 191 E-6 Mad.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

9-261

MC44615A
input to the phase detector. Representative circuitry at Pins 7
and 8 is shown in Figure 4 and should be considered with
Figure 3 since Pin 6 links them.

The charging current is now defined and is,
1.25V
14 = 15 = - - -IERROR·
RHset
With the MC44615A there is also the possibility of phase
advancing the output waveforms to compensate for the
integration effects of the horizontal convergence coils. Phase
advance is done by an external RC combination at Pin 7,
where a square wave at the horizontal frequency is output, and
at Pin 8, the input to the horizontal phase detector, PD. The
square wave provides one input to the phase detector, the
input at Pin 3 is the other.
A delay to the square wave at the horizontal frequency
advances the output waveforms by delaying the square wave

Vertical Timing
Vertical timing for the MC44615A is determined by the
frequency of the input at Pin 39 and the charging rate of the
capacitor at Pin 38. Representative circuitry for relevant pins
is shown in Figure 5. The vertical timing is set by a ramp
generator, the frequency of the generated ramp being
determined by the current drawn out of Pin 37 (1.25/ RVsetl.
At the beginning of a vertical cycle, the current sourced by Pin
37 is mirrored out of Pin 38, charging the capacitor at Pin 38

Figure 3. Horizontal Frequency Control
1 ;
1

icC - - - -- - - - - - - - - - - ,

Vee

'

600

1 ,
'~
1 ,

~

1
1

'

41

'

1

'

1 '
1
1

'
'

1 '
1
1

600

'

1 '
1

'

I_'-=' ~ -=. -:.. .: ..:..-....: .::...--=..::...--=. ~ ~

5

________ 6___________ ,
~--~~--~---~--~
Hp~ ,
Fiher '
: 10kn

"Polystyrene
L

_________________

.:._~

Figure 4. Horizontal Input and Phase Advance

Vee

10k 1 3
1

1
1
1
1
1
1

VEE

a---------US--------------

7

Adelay

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
9-262

1

J

MC44615A
Figure 5. Frequency Control

39

1

I
I
I
I
I
I
I
I ____________
VEE
1_
38

Cv' I
with a constant current resulting in a linear ramp. The charging
current of the capacitor (ev) must be set so the capacitor voltage reaches 2.5 II, when the next vertical sync pulse arrives
to discharge the capacitor. The current, sourced by Pin 37, is
again provided to the capacitor and the cycle continues.

+

37
RVset

in Figure 7A, and a diagram showing relative timing is shown
in Figure 7B.

Figure 6. Internal Circuitry for
Output Waveforms

Outputs and Output Clamps
The various output waveforms are developed by internal
circuitry and are the result of operations on the internal vertical
and horizontal ramps. The waveforms and their complements
are then made available at the output pins and are capable of
supplying at least 2.5 mA per pin. A simplified schematic ofthe
output stage is shown in Figure 6. It is clear from the figure that
output voltages should never exceed VCC or V EE by more than
0.5 V or excessive currents will flow.
During vertical sync inteNals, circuitry blanks the outputs
while clamping circuitry works to cancel out DC offsets in the
waveforms. After the leading edge of a vertical sync pulse,
blanking logic blanks the outputs for the time spanned by the
first two horizontal pulses (see Figure7B). Clamping circuitry
works for the line period between the first two blanking
intervals. Internal circuitry present at the clamp pins is shown

Figure 7A. Clamp Circuitry for
Output Waveforms

Output
~-+--jp--. Waveform

Figure 7B. Blanking and Clamping Diagram

VCC

15,18,21,24
27,30,34
47n

Verticalsj

I
I
I
I

Horizontal
Flyback

II
-=-1

I
I
I
I
I
I

_

L--_ _ _ _

Horizonlal
and
Vertical Sync

~

Clamp Time

-,",,~~~~m~~

_B_la_nk_P_u_ls,-e

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

9-263

MC44615A
APPLICATION INFORMATION
The following information is provided to assist designing-in the
MC44615A.

The maximum phase error for which the loop is stable is
determined experimentally and is,

Horizontal Timing
Since the charge and discharge of the capacitor at Pin 4
(CH) is done with constant currents, the voltage waveform of
the capacitor voltage is,

±IN = ± ~

where, L'.t is the trace or retrace time.

ct>Emax = 0.124 rad.
The lock range then is defined by the product of this maximum
phase error and the loop gain (KV). The loop gain is the product
of the phase detector sensitivity (Il) and the oscillator
sensitivity (~).

C

Il = 191 E-S
~ = 1/2.5 CH

The horizontal frequency is then the inverse of the sum of the
charge time and the discharge time,

KV =

191E-S
2.5CH

1
fhorizontal =

(tcharge + tdischarge)

where,

flock

=

L'.fmax

=

±

191E-SO.124
9.5E-S
=±
2.5 CH
CH

tcharge = trace time, and tdischarge = retrace time.
This relates the trace and retrace time to element values,
internal quantities and a design variable, Icharge. 80,
!charge

=

CH L'.Vp-p
I
charge

CH L'.Vp-p
and

tdischarge

= Id·IsCharge

L'.Vp-p and Idischarge are fixed (ldischarge is typically 1.4 rnA
and L'.Vp-p is 2.5 Vp-p.). If CH is chosen to meet the
requirements of retrace time and,

(The value of flock should be kept small enough to prevent
loop-lock on harmonics. A general rule of thumb would be flock
< 10% of the desired horizontal frequency.) Then IERROR is
less than 10% of Icharge and so the horizontal frequency is
almost entirely determined by:

=

trace time » retrace time, then tcharge » tdischarge,

~

1.25
Icharge = -R-- - IERROR
Hset

The horizontal frequency is now defined as,

-Il ct>E

}(

1.25
L'.Vp-p =2.5,
C'V
H L> p-p

fhorizontal =

1
2 RHset CH

which is also the horizontal free-run frequency. The horizontal
free-run frequency should be set at or very near the desired
horizontal frequency since the lock range is centered about
this frequency.
80 a design would meet the following requirements:

or, required retrace time>

CH L'.Vp-p

,

Idischarge
where Idischarge is = 1.4 rnA and L'.Vp-p is = 2.5 Vp-p.

IERROR = Il ct>E

+

Hset

1) The value of CH satisfies the requirements for retrace time

where IERROR is the currentfrom the phase detector when the
loop is locked and was determined in the FUNCTIONAL
DESCRIPTION text to be,

.
{1.25
RHset
fhonzontal =

= R

so this becomes,

dCh~~e

,or fhorizontal =
p
'Charge
H
pDetermining the current Icharge then gives the horizontal
frequency, since CH and L'.Vp-p are known.
Refering to Figure 3, the current out of Pin 5 is the current
Icharge and is composed of,
then, fhorizontal =

f horizontal

2) The value of the resistance from Pin 5 to ground is given by

1
RHset

1
) , or
CH L'.Vp-p

fhorizontal = ffree run ± N,
where N is the frequency difference between the horizontal
free run frequency and the frequency ofthe input signal, RHset
is the resistance from Pin 5 to ground, CH is the capacitor at
Pin 4 and RF is the resistor between Pins 5 and S. It must be
emphasized that this equation holds true only when the loop
is locked.

2 fhorizontal CH

(The value of the resistor calculated for RHset should be
considered approximate. The 5.0 kQ pot, shown in the
Application Circuit of Figure 10, is recommended for
optimization.)
3) The capacitor CH is such thatthe lock range is a reasonable
choice given by,

flock = ± 9.5E-S
CH

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

9-264

MC44615A
Vertical Timing
To set the vertical timing a capacitor-resistor pair must be
chosen (refer to Figure 5). The vertical timing section is similar
to the horizontal section in that the frequency is determined by
the charge and discharge rate of a capacitor (at Pin 38). The
vertical ramp generator is an injection type, so a vertical input
must be present for vertical outputs to be present. The vertical
ramp generator is not free running.
I t.t
Again, ±AV = ± _
Cv
describes the capacitor voltage for the charge and discharge
currents made available at Pin 38. Further, iftretrace« ttrace,
then,

1

The amount of "advance" desired can be calculated by
considering the phase detector's treatment of the inputs. The
inputs to the phase detector, horizontal sync and signal,
injected at Pin 8, are phase-locked so that they appear as
shown in Figure 8. The center of the horizontal sync pulse is
phase-locked to the zero crossing of the internal oscillator that
is output at Pin 7.
Figure 8. Phase Detector, Horizontal Sync
and Signal Inputs

1

fvertical = fv =~t = ~h
race
c arge

and the vertical frequency is determined by the charging
current, the t.V and the capacitor value. The reference voltage
for developing the charging current is present at Pin 37 and is
nominally 1.25 V. The charging current is then defined by the
resistance at this node,
1.25
Icharge =

RVset

The resistance required can be determined for a particular
frequency and capacitor combination. The capacitor voltage
(t.V), must be nominally 2.5 Vp-pforthe specified full scale
vertical outputs. Using this value, the proper combination
RVset and Cv can be calculated. The current available to
discharge Cv is approximately 800 flA. So a practical Cv
value is described by,
CV:-:; 800 f1A t.t ,where t.t :-:; required retrace time.
t.v
This value of Cv is next used to calculate the value RVset
considering the vertical frequency desired,
1.25
Icharge= - RVset
R
Vset

1.25

= Cv IN fv

Cv t.V

~ = Cv t. V fV,

1.25
= Cv 2.5 fv

=

time base = 10 Ils/Div

So a delay of the oscillator zero crossing will force the loop
to lock the incoming horizontal sync input to a phase delayed
representation of the internal horizontal oscillator. The outputs
are not delayed, so as a result they are phase advanced.
Figure 9 shows the result of about 8.0 fls of delay placed on
the oscillator square wave output at Pin 7.

Figure 9. Oscillator Square Wave Output

or

1
2 Cv tv

(The equation given for RVset is approximate and should be
used only as a starting point. The 20 kQ pot in the applications
circuit of Figure 10 is used to optimize this value.)

Optional Horizontal Phase Advance
The MC44615A allows the output waveforms to be
"advanced" relative to the incoming horizontal input at Pin 3 by
delaying the internal oscillator input into the phase detector.
The delay is accomplished with an external RC combination
at Pins 7 and 8 (refer to Figure 6). The resistor, Rdelay, also
couples the two pins and provides the signal path to the phase
detector, PD. In any event, whether or not delay is desired,
the signal output at Pin 7 must be coupled to Pin 8. A
10 kQ resistor can be used to couple Pins 7 and 8, if no delay
is desired.

time base = 10 Ils/Div

The amount of delay or advance required is calculated
according to,
tadvance
Rdelay Cdelay = - - 0.69
The minimum impedance coupled to ground should be greater
than 4.0 kQ and a maximum of 20 kQ .

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
9-265

MC44615A
Optional Waveform Disable
Pin 2 on the MC44615A is provided for blanking the output
waveforms. When the voltage applied at this pin is less than
about 2.5 V, all outputs are blanked and within 50 mV of
ground. The impedance presented at this pin is> 500 kQ. The
outputs can be permanently enabled by a pull-up resistor from

Pin 2 to the positive supply, VCC. An external RC is
anotheroption. A resistor (1 a kQ to 100 kQ) coupled from Pin 2
to VCC and a capacitor coupled from Pin 2 to ground will delay
the appearance of the waveforms by an amount,
tdelay = RC (0.69)

PIN DESCRIPTION TABLE
Symbol

Pin

Internal Equivalent Circuit

Description
Positive rail voltage. Requires 33 mA at 4.5 < Vdc < 5.5.

VCC
Waveform
Blank

Output waveform blanking pin. An external RC may be used
to delay the appearance of the output waveforms.
Waveforms are present when Pin 2 voltage exceeds 2.5 V.
Input impedance is nominally 500 kQ.

2

lk

(See Note)
Positive horizontal flyback input. Input impedance is
nominally 10 kQ. (See Figure 2)

3

25k

25k

fH

4

Horizontal oscillator capacitor (CH). The charge and
discharge rate of this capacitor's voltage determines the
horizontal frequency. Charging current set predominantly
by RHset. (See Figure 3)

Nole: All pins (except Vee and VEE) have ESD diodes between Vee and VEE.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

9-266

MC44615A
Description

Symbol

Pin

iHset

5

Horizontal charge current set. An internally regulated
1.25 Vdc, and the external resistance (RHsetl at this pin
determines the horizontal free run charging current. Also, the
feedback current from the HpLL filter is input at this pin.

6

Horizontal Phase Detector output pin. An external filter
circuit between this pin and Pin 5 determines the selectivity
of the Phase Detector and provides the feedback path for
the Horizontal Phase-Locked-Loop.

7

Square wave output at the horizontal oscillator frequency.
An external RC added at this pin advances the phase of
the waveforms. External impedance to ground should be
> 4.0 fl, and < 20 ill

Hadvout

Internal Equivalent Circuit

10k

Hadv in

Horizontal phase detector input. The path between this
pin and Pin 7 can be used to delay the squared output
from the horizontal oscillator. This results in a phase
advance of the horizontal waveforms. Input impedance
is nominally 200 kQ .

8

8

Clamp Pulse

Clamp Pulse output. This pulse is initiated by the vertical
and horizontal flyback pulses to enable the clamp circuits.
The timing of the pulse is shown in Figure 9.

9

Note: All pins (except Vee and VEE) have ESO diodes between Vee and VEE·

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
9-267

MC44615A
Symbol

Pin

Gnd

10

+H

11

Internal Equivalent Circuit

Horizontal ramp output.

Vee
501lA

+

L
r

100

VEE
-H

12

+H2

13

-H2

14

H2Clamp

15

Description
Ground connection.

Output
Waveform

I
Complement horizontal ramp output.

(See Pin 11)

Horizontal parabola output. The squared result of the
positive horizontal ramp.
Complement horizontal parabola output.
Horizontal parabola clamping pin. An external capacitor
works to cancel DC offset. Typically, coupled to ground
with a 47 nF capacitor.

Vee

.

1.0~?-3S

eonnec:~~ ~
.

~
20k

~

+ 50~A
VEE
+H3

16

-H3

17

H3Clamp

18

+HV

19

-HV

20

HVClamp

21

Cubic output.
(See Pin 11)

Complement cubic output.

(See Pin 15)

Cubic clamping pin. An external capacitor works to cancel
DC offset. Typically, coupled to ground with a 47 nF
capacitor.
Horizontal and vertical ramps product.

(See Pin 11)
Complement horizontal and vertical ramps product.
Horizontal and vertical ramp product clamping pin. An
external capacitor works to cancel DC offset. Typically,
coupled to ground with a 47 nF capacitor.

(See Pin 15)
H2V

22

Positive product of horizontal parabola and vertical ramp.
(See Pin 11)

-H2V

23

H2VClamp

24

Complement horizontal parabola and vertical ramp product.
Horizontal parabola and vertical product clamping pin. An
external capacitor works to cancel DC offset. Typically,
coupled to ground with a 47 nF capacitor.

(See Pin 15)
+H2V2

25

-H2V2

26

H2V2Clamp

27

Horizontal parabola and vertical parabola product.
(See Pin 11)

Complement horizontal parabola and vertical parabola
product.
Horizontal parabola and vertical parabola product clamping
pin. An external capacitor works to cancel DC offset.
Typically, coupled to ground with a 47 nF capacitor.

(See Pin 15)
+HV2

28

-HV2

29

Horizontal ramp and vertical parabola product.
(See Pin 11)
Complement horizontal ramp and vertical parabola product.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
9-268

MC44615A
Symbol

Pin

HV2Clamp

30

Internal Equivalent Circuit

Description

Horizontal ramp and vertical parabola product clamping
pin. An external capacitor works to cancel DC offset.
Typically, coupled to ground with a 47 nF capacitor.

(See Pin 15)
Gnd

31

+V2

32

_V2

33

V2Clamp

34

Ground connection.
Vertical parabola.
(See Pin 11)

Complement vertical parabola.
Vertical parabola clamp pin. An external capacitor works to
cancel DC offset. Typically, coupled to ground with a 47 nF
capacitor.

(See Pin 15)
+V

35

-V

36

Ivset

37

Vertical ramp.

(See Pin 11)

Complement vertical ramp.
Vertical charge current set. An internally regulated
1.25 Vdc, and the external resistance at this pin
determines the charging current for the capacitor, CV,
connected to Pin 38.

Vee

~
-+

~ 1.25V

37
Iv

VEE

38

Vertical ramp generator capacitor (CV)' The charge and
discharge rate of this capacitor determines the vertical
ramp rate.

Vee
20k

20k

38

=
800~

r15~
+
VEE

Vin

39

Positive vertical flyback input pin, presents 10 kn to input
waveform. (See Figure 2)

Vee

39
10k

i\-§{-

i"
~

~

20k

20k

VEE
VEE

40

Negative supply pin. Requires 43 mAat -5.5

VCC3
B3

• High Sensitivity

(Top View)

• Fully ESD Protected

MAXIMUM RATINGS (TA = 25°C, unless otherwise noted.)
Value

Unit

3

7

6.0

V

Band Buffer OFF Voltage

6-9

10-13

15

V

Band Buffer ON Current

6-9

10-13

50

mA

Band Buffer - Short Circuit Duration (0
to VCC3) (Note 2)

6-9

10 -13

Continuous

sec

Rating
Power Supply Voltage (VCC1)

Pin(807)/(817)

2

Op Amp Short Circuit Duration
(0 to VCC2)

1

Power Supply Voltage (VCC3)

10

14

14.4

V

Storage Temperature

10

14

- 65 to +150

°C

-20 to + 80

°C

6
5

Operating Temperature Range

Op Amp Output Voltage

PIN CONNECTIONS
Oa

En
Lock

Xtal

Op Amp Power Supply Voltage
(VCC2)

Band Buffer Operation (Note 1) @ 50
mA each buffer. All buffers ON
simultaneously

DSUFFIX
PLASTIC PACKAGE
CASE 751B
(SO-16)

40
Continuous

V
sec

6-9

10 -13

10

sec

1

5

VCC2

V

NOTES: 1.A1VCC3 = VCC1 to 14.4 v, andTA =-20 to + eo°c.
2.AtVCC3 = VCC1 to 14.4 v, andTA = -20 to + eo°c, one buffer ON only.
0

0

B3

Vtun

B2

VCC2

B1

VCCI

BO

HFln

Gnd

ORDERING INFORMATION
Device
MC44807P
MC44817D

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

9-282

VCC3

Ampln

Temperature
Range
- 20° to + 80°C

Package
Plastic DIP
SO-16

MC44807/17
Figure 1. Ripple Rejection - Measurement Schematic (MC44807P)

16

100nF

(Max 2.8m Vpp)
50Hz

MC448D7
22k

47nF

VTuning
100nF

I
+33V

Loop is locked on any channel

1

500mVpp
F = 50Hz
5.0V

PIN FUNCTION DESCRIPTION
Pin

Function

Description

MC44B07P (see Block Diagram)
1

Out

2

VCC2

3

VCCI

Positive supply of the circuit (5.0 V)

4

HFln

HF inputs from local oscillator

5

Gnd

Ground

6,7,8,9

BO, Bl ... B3

Operational amplifier output which provides the tuning voltage
Operational amplifier positive supply (33 V)

Band buffer outputs can drive up to 30 rnA (40 rnA at 00 to 80 0 C)

10

VCC3

Positive supply for integrated band buffers (12 V)

11

LOCK

Lock detector output

12

En

Enable input (3·wire Bus)

13

DA

Data input (3-wire Bus)

14

CL

Clock input (supplied by the microprocessor via 3-wire Bus)

15

Xtal

Crystal input (typ: 3.2 MHz)

16

In

Negative operational amplifier input and charge pump

MC44817D
1

DA

Data input (3-wire Bus)

2

CL

Clock input (supplied by the microprocessor via 3-wire Bus)

3

Xtal

4

In

5

Out

Crystal oscillator (3.2 MHz)
Negative operational amplifier input and charge pump
Operational amplifier output which provides the tuning voltage

6

VCC2

7

VCCI

Positive supply of the circuit (5.0 V)

8

HFln

HF input from local oscillator
Ground

9

Gnd

10,11,12,13

BO, Bl ... B3

14

VCC3

15

LOCK

16

En

Operational amplifier positive supply (33 V)

Band buffer outputs can drive up to 30 rnA (40 rnA at 00 to 80 a C)
Positive supply for integrated band buffers (12 V)
Lock detector output
Enable input (3-wire Bus)

MOTOROLA LlNEARIINTERFACE ICs DEVICE DATA
9-283

MC44807/17

Figure 2. HF Sensitivity Test Circuit
Bus

VCC3= 12V

."""""""""""""""~

Bus Controller

I

12 13 14
VCCI =5.0V
-=--3

10

MC44807

B3

HF Generator
4
HFOut

= = 1.0nF

I-J

50n Cable

15

±

22pF

o

I-=-

Device is in Test mode: Sens~vity is level of
HF generator on 50 n load (w~hout MC44B07 load).

5

In

9

Counter

~

4.7k

3.2 MHz

~

-

Figure 3. Block Diagram MC44807P
(22n)

Vtun
(47n)

·--r---------3

I

I
I

(5.0V) VCCI

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
9-284

(47k)

MC44807/17
Figure 4. Typical Tuner Application
IF

External

UHF

Switching

VH~F

______________+-________--.

83

'-------:;:r=f.~r--~J-

I---~-H-

Clock
Data

'-'-!""-.J-----"""""'",.- En

I

12pF

= 3.2MHz

*
AGC

VTune

33V

22nF

NOTE: 1. This feature needs to be characterized on the final silicon. In the case that it degrades the

HF-sensilivity, it will be eliminated.
2. The 100 n resistor is not required any more, but does not disturb the performance.

FUNCTIONAL DESCRIPTION
A representative block diagram and a typical system
application are shown in Figures 4 and 5. A brief discussion of
the features and function of each of the internal blocks follows.

14-bit, its MSB (Bit N14) is internally reset. The reset pulse is
generated only if En goes negative after the 18th clock pulse
(signal Rl).

Data Format and Bus Receiver
The circuit is controlled by a 3-wire bus with Data (DA),
Clock (Cl), and Enable (En) inputs. The Data and Clock
inputs may also be shared with an 12C Bus (data changes
when clock is low) while the Enable is a separate signal. The
circuit is compatible with 18 and 19-bit data transmission and
also has a mode for 34-bit transmission for test and
additional features.
The 3-wire bus receiver receives data for the internal shift
register after the positive-going edge of the En signal. The
data is transmitted to the band buffers on the negative-going
edge of clock pulse 4 (signal DTB1).

34-Bit Data Transmission
(For Test and Additional Features) In the test mode, the
programmable divider receives 15-bit and the data is
transferred to latches A on the negative edge of clock pulse
19 (signal DTF). The information for test is received on clock
pulses 20 to 26 and transmitted to the latches on the negative
edge of pulse 34 (signal DTB2). These latches have a
power-on reset. The power-on reset sets the programmable
divider to a counting ratio of 256 or higher and resets the
corresponding latches to test bits TO to T6 (signal POR). The
bus receiver is not disturbed if the data format is wrong.
Useless bits are ignored. If, for example, the Enable signal
goes low after clock pulse 9, bits 1 to 4 are accepted as valid
buffer information and the other bits are ignored. If more than
34 bits are received, bit 35 and the following are ignored.
The lock Detector output is low in lock. The output goes
immediately high when an unlock condition is detected. The
output goes low again when the loop is in lock during a
complete period of the reference frequency.

18 and 19-Bit Data Transmission
The programmable divider may receive 14-bit (18-bit
transmission) or 15-bit (19-bit transmission). The data is
transmitted to the programmable divider (latches A) on the
negative-going edge of clock pulse 19 or on the negative
edge of the En signal if En goes down after the 18th clock
pulse (signal DTF). If the programmable divider receives

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

9-285

MC44807/17
BUS TIMING DIAGRAM
Standard Bus Protocol 18 or 19-Blt

Data

4

5

t8

t9

Clock

I

Frequency

Buffers

J

L--'--_Enable
__
Bus Protocol for Test and Features

t

4 5

t9 20

26 27

34

B3 B2 Bt BO Nt4 Nt3 Nt2 Ntt NtO N9 N8 N7 N6 N5 N4 N3 N2 Nt NO T6 T5 T4 T3 T2 Tt TO X7 X6 X5 X4 X3 X2 Xt

I

Frequency

Buffers

Test and Features

Random

J

L
DEFINITION OF BUS PROTOCOLS

Bus Protocol for 18-Blt
1 83

B2

Bt

Nt3

BO

Nt2

Ntt

NtO

N9

N8

N7

NS

N5

N4

N3

N2

Nt

NO

Nt

NO

Max counting ratio 16363
N14 is reset internally
Bus Protocol for 19-Blt

I B3

B2

Bt

BO

Nt4

Nt3

Nt2

Ntt

NtO

N9

N8

Max counting ratio 32767:
BO, Bl ... B3 = Control of band buffers
NO, Nl ... NI4 = Control of programmable divider

N7

NS

N5

N4

N3

N2

N14 = MSB; NO = LSB
Min, counting ratio always 17.
B3 = First shifted bit
NO = Last shifted bit

Bus Protocol for Test and Further Features (34-Blt)

I B3

xo

B2

Bt

BO

Nt4...NO

TS

T5

T4

T3

TO, Tl ...T3 = Control the phase comparator
T4 = Switches test signals to the buffer outputs
T5 = Division ratio of the reference divider
T6 = Bypasses the prescaler (see note Bit T6 table)
XO, Xl ... X7 = Are random

T2

Tt

TO

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
9-286

X7

B3 = First shifted bit
XO = Last shifted bit

XS ... Xt

XO

MC44807/17
DEFINITION OF THE BITS FOR TEST AND FEATURES

Bit TO Defines the Charge Pump Current
of the Phase Comparator
TO

Charge

Pump current 50 IJ.A (Typical)
Pump current 151J.A (Typical)

0
1

Bits T1 and T2 Define the Digital Function of the Phase Comparator
T2

T1

State

0
0
1
1

0
1
0
1

1
2
3
4

Output Function of Phase Comparator

Normal Operation
High Impedance (Tri-State)
Upper Source On, Lower Source Off
Lower Source On, Upper Source Off

NOTE: Statel The phase comparator pulls high If the Input frequency IS too high and It pulls low when the
input frequency is too low. (Inversion by op amp) The phase comparator generates a fixed
duration offset pulse for each comparison pulse (similar to the MC44802A). This guarantees
operation in the linear region. The offset pulse is a positive current pulse (upper source).

Bit T3 Defines the Offset Pulse
of the Phase Comparator
T3

Bit T5 Defines the Division Ratio
of the Reference Divider

Offset Pulse

a

Offset pulse short (200 ns), normal mode

1

Offset pulse long (350 ns)

T5

Bus Protocol

0

Division ratio 512

1

Division ratio 1024

.. .

..

The diVISion ratio of the Reference D,v,der can only be programmed In the
34 bit bus protocol. In the standard bus protocol the division ratio is 512.
(The power-up reset (POR) sets the division ratio to 512).

Bit T4 Switches the Internal Frequencies Fref and FBY2
to the Buffer Outputs (B2, B3)
T4

Buffer Outputs

0

Normal operation

1

FRet switched to buffer output B2
FBY2 switched to buffer output B3

Bit T6 Switches the Prescaler
T6

0
1

Operation

Normal operation, 1.3 GHz
Preamp 2 switched OFF
Lowfrequency operation, 165 MHz maximum.
The prescaler is bypassed and its power supply is

switched OFF. Input, 10 MHz min, 20 mVrms min.

Bits 82 and 83 = have to be one in thiS case

..

FRef =reference frequency
FBY2 =output frequency of the Programmable Divider, + 2

NOTE: ThiS feature needs to be characterized on the final slhcon. In the
case that it degrades the HF-sensitivity, it will be eliminated.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

9-287

MC44807/17
Figure 7. Equivalent Circuit of the Integrated Band
Buffers

Figure 8. Equivalent Circuit of the Lock Output
VCCI

,--------~~------o(5.0V)

(min. VCCI , max 14.4V)
VCC3
12V

200j.tA 1yp

0.15V1yp
0.3Vmax

25V
Protection

~-'VV'v--.---o

30mA (40mA
@OOtoBO°C)

Isub

lOOk

Lock

25V Protection

Out
Gnd

BO ... B3
Ib + Isub = B.O mA 1yp, 13 mA max
Ib = Base Current
Isub = Substrate Current of PNP

Programmable Divider
The programmable divider is a presettable down counter.
When it has counted to zero it takes its required division ratio
out of the Latches B. Latches B are loaded from Latches A by
means of signal TDI which is synchronous to the
programmable divider output signal.
Since Latches A receive the data asynchronously with the
programmable divider; this double latch scheme is needed
to assure correct data transfer to the counter.
The division ratio definition is given by:
N = 16384 x N14 + 8132 x N13+ ... + 4 x N2 + 2 x N1+
NO
maximum ratio 32767 (16363 in case of 18-bit protocol),
minimum ratio 17, where NO ... N14 are the different bits for
frequency information.
At power-on the whole bus receiver is reset and the
programmable divider is set to a counting ratio of N = 256
or higher.
Prescaler
The prescaler has a preamplifier which guarantees high
input sensitivity.

Phase Comparator
The phase comparator is phase and frequency sensitive
and has very low output leakage current in the high
impedance state.
Operational Amplifier
The operational amplifier is designed for very low noise,
low input bias current and high power supply rejection. The
positive input is biased internally. The op amp needs 28.5 V
supply (VCC2) as minimum voltage for a guaranteed
maximum tuning voltage of 28 V.
Figure 4 shows a possible filter arrangement. The
component values depend very much on the application
(tuner characteristic, reference frequency, etc.).
Oscillator
The oscillator uses a 3.2 MHz to 4.0 MHz crystal tied to
ground in series with a capacitor, used in the series
resonance mode. The voltage at Pin 15 (or Pin 3 in SOIC
package) "crystal", has low amplitude and low harmonic
distortion.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
9-288

MOTOROLA

MC44810

SEMICONOUCTOR-----TECHNICAL DATA

Product Preview
PLL Tuning Circuit with 1.3 GHz
Prescaler and OfA Section
The MC4481 0 is a tuning circuilforTV applications. It contains a PLL section
and a DAC section and is MPU controlled through the 12C Bus.
The PLL section contains all the functions required to control the VCO of a
TV tuner. It generates the tuning voltage and the additional control signals
(e.g. band switching voltages). The PLL section is functionally equivalent
to MC44802.
The D-to-A section generates three further varactorvoltages in order to feed
all of the varactors of the tuner with their individually optimized control voltages
(automatic tuner adjustment).
The MC44810 is manufactured on a single silicon chip using Motorola's
high density bipolar MOSAIC® process (Motorola Oxide Self Aligned
Implanted Circuits).
• Complete Single Chip System for MPU Control (12C Bus)
• Selectable + 8 Prescaler Accepts Frequencies Up to 1.3 GHz
• 15-Bit Programmable Divider Accepts Input Frequencies Up
to 165 MHz
• Programmable Reference Divider
• Tri-State Phase/Frequency Comparator
• Op Amp for Direct Tuning Voltage Output (30 V)
• Seven Output Buffers: 10 mA, 12 V
• Output Options for 62.5 kHz, Reference Frequency and the
Programmable Divider
• Software Compatible with MC44802A
• Three 6-Bit DACs for Automatic Tuner Adjustment Allowing Use of
Non-Matched Varactors
• Better Tuner Performances Through Optimum Filter Response
• Two Chip Addresses for the PLL Section and Two Different Chip
Addresses for the DAC Section

SYSTEM 4
PLL TUNING CIRCUIT with
1.3 GHz PREsCALER

_

PSUFFIX
PLASTIC PACKAGE
CASE 738

20

1

DWSUFFIX
PLASTIC PACKAGE
CASE 751D
(SO-20L)

PIN CONNECTIONS

VCC2
AmPln
PHO
Xtal
SOA

VCC1

SCL

HFln

B7

BO

MAXIMUM RATINGS (TA = 25 unless otherwise noted.)
0 ,

Ratings

Pin

Value

Unit

5

6.0

V

Band Buffer OFF Voltage

8to 14

15

V

Band Buffer ON Current

8to 14

15

rnA

Power Supply Voltage (VCC1)

Op Amp Power Supply Voltage (VCC2)
Op Amp Short Circuit Duration
(OtoVCC2)

20

36

V

1 t04

Continuous

sec

B5

B2

B4

-

- 65 to +150

DC

Operating Temperature Range

-

o to+ 70

DC

ORDERING INFORMATION

MC44810P
MC44810DW

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
9-289

"

(Top View)

Device

Storage Temperature

B6

B1

Temperature
Range

Package

00 to + 70°C

Plastic DIP
SO-20L

MC44810
Figure 1. Ripple Rejection - Measurement Schematic

22k

(Max 2.8mVpp)
50Hz

1

100nF

MC44810
22k

47nF

7

Vtuning -+---------'
100nF

I
Loop is locked on any channel
500mVpp
F = 50Hz
5.0V

+33V

1
Figure 2. HF Sensitivity Test Circuit
Bus

~

"""""""'"'~

Bus Controller

15

16

MC44810

HF Generator

6

==1.0nF

HFOut

LJ

";>

<,4.7k

VCC1 =5.0V
-""'-'---- 5

B5
7

1
-

500 Cable

17

12

In

±

Counter

22pF

14.oMHZ

Device is in Test mode: R2 =1, R3 =0 (~ee Bus section) sensitivity
is level of HF generator on 50 0 load (WIthout MC4481 0 load).

-=-

--=-

PIN FUNCTION DESCRIPTION
Pin

Function

1

Out

2,3,4

DA1, DA2, DA3

Description
Operational amplifier output which provides the tuning voltage

D/A output control voltages
Positive supply of the circuit (except op amp)

5

VCCI

6

HFln

HF inputs from local oscillator

7

Gnd

Ground

8,9,10,11
12, 13, 14

BO ... B2
B4 ... B7

Band buffer outputs can drive up to 10 mA

15

SCl

16

SDA

Clock input (supplied by the microprocessor via 12C bus)
Data input (12C bus)

17

Xtal

Crystal oscillator (typ: 4.0 MHz)

18

PHO

Phase comparator output

19

In

Negative operational amplifier input

20

VCC2

Operational amplifier positive supply

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

9-290

MC44810
Figure 3. Pin Circuit Schematic
22k
Tuning Voltage

100nF
47nF

1.0nF

=f

20
OpAmp
Section ----<:>+--VCC2 = 33V
360

OAI

10k

_--'\I\~>-----'---'\I\~"'-

360

VCCI
1.0k
1.0k

>----__--'\I\~...-

Xla1

OA3 _--'\I\rv-'<4
360

HFln

PHO

All Sections
Except OpAmp

-,,;<;>------

50

17

15 SCl

,--1------1

1

87 14

1

L ___ -.l

,---

:

8 BO

86 13

L _____ ...!
1

1

1

,---

1

1

1
9~
---~
~--~
1

L ___ -.l
10 B2

~--~I~

1

---~

1

1

L ___ -.l

j----i----- j

1

85 12
1

L ___ -.l

1

,---

1

1

B4 11

j----r----- L___ -.l

1

j

L ___ -.l

1

,----------1
1 Add Selection

1

I----.l-----I

180~CCll1

:

1

1

1

1

1

1

1

1

1

U

1

~4.0MHZ

SOA 16

-I f--'<6O---O---1I:::--L.
1.0nF

Gnd ,..----=-¢--...,

1

l

1.0nF

12pf

5

VCCI = 5.0V

10k

18

On/Off

L __ ~ ______ .J

Bl~
... B7
VCC1:

1

I__ ~ _______ .J

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

9-291

~

MC44810
FUNCTIONAL DESCRIPTION
A representative block diagram and a typical system
application are shown in Figures 4 and 5. A discussion of
the features and function of each of the internal blocks is
given below.
Automatic Tuner Alignment
The circuit generates the tuning voltage through the PLL
in the same way as the MC44802A. The output voltage of
the D/A converters are equal to the tuning voltage plus a
positive or negative offset of up to 31 steps. During the
automatic alignment the PLL first locks to the appropriate

frequency and then searches for the optimum values of the
other varactor voltages. The digital word for each voltage
value is stored in a nonvolatile memory (NVM). Hence, for
each frequency point to be adjusted, three times 6 bits of
information have to be stored (plus 2 bits for the DAC range).
The information stored in the NVM reflects the
characteristic of the individual tuner. For this reason the NVM
is preferably situated inside the tuner and is also controlled
by the 12C Bus. (The NVM is also needed to store the
program-channel allocation).

Figure 4. Block Diagram

fL_~

Controls Out

Vtun
DA2

DA3

OAt
(47n)

(390)

(390)

I-=

(I.On)

~
PHO

VCCt ~
5.0V I

I
I
I

~

Gnd ,.---,

I

11~15~-+____-+~~~~f---l-W~L.~l;h;ftRe:;~:----1

Clock t-

16
Data t---I-----L~~~.r.:;;_;_

........='--lo\_,__...!f_~---.J

I
I
I
I
I
I
I
16

HFln t-=------1H

I
I
I
II
I

Preamp 2

1_- ____ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - MOTOROLA LlNEARIiNTERFACE ICs DEVICE DATA

9-292

MC44810
Figure 5. TV Tuner for Automatic Alignment
12V

IF

VCC3
Swijch Buffers

Mixer

Antenna
FiHer

AGC

HFln

MC4481 0

VCC2

35V

VCCl

5.0V

Clock

SCL
12C Bus
SDA

Antenna
Data

rJ

Oscillator

I

D/A
Cony

DAl
______________________________________________~
DA3L-________________________________________________________~
D~L-

PLLSECTION
Data Format and Bus Receiver
The circuit receives the information for tuning and control
via the 12C Bus. The incoming information is treated in the
12C bus receiver.
Bus Protocol
1_STA
2_STA
3_STA
4_STA
STA
STO
CA1
CO
BA
FM
FL

=
=
=
=
=
=
=

CA1
CA1
CA1
CA1

Start
Stop
Chip
Data
Data
Data
Data

CO
FM
CO
FM

BA
FL
BA
FL

STO
STO
FM FL
CO BA

Figure 6. Definition of Bytes

CA1_Chip Address

0/1

0

ACK

CO_Control Information

STO
STO

BA_Band Information

Condition
Condition
Address Byte of PLL Section
Byte for Control Information
Byte for Band Information
Byte for Frequency Information (MSBs)
Byte for Frequency Information (LSBs)

Figure 6 shows the five bytes of information that are
needed for circuit operation: there is the chip address, two
bytes of control and band information and two bytes of
frequency information.
After the chip address, two or four data bytes may be
received. If three data bytes are received the third data byte
is ignored. If five or more data bytes are received the fifth
and following data bytes are ignored and the last
acknowledge pulse is sent at the end of the fourth data byte.
The first and third data bytes contain a function bit F. If
the function bit F=O, frequency information is acknowledged
and if F=1, control/band information is acknowledged.

~--------------------~

FMfreq Info (with MSB)

F=O N14 N13 N12 Nll Nl0 N9 N8 ACK

Fl_Freq Info (with LSB)

N7 N6 N5

N2 Nl

NO ACK

If the address is correct (signal AD1) the information is
loaded into latches.
A function bit in the first and third data byte is used to
pass this data either into the latches for the programmable
divider (signal DTF) or into the latches for band and control
information (signal DTB). The data transfer to the latches
(signals DTF and DTB) is initiated after the 2nd and 4th
data bytes.
A second string of latches is used for the data transfer
into the programmable divider to inhibit the transfer during
the preset operation (signal TDI, Signal AVA is an internal
"address valid" command).

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
9-293

N4 N3

MC44810
The control and band information bits have the following
functions:
Bit RO and R1 (See Table 1) Define the reference divider
division ratio. Four ratios are available.
Bit R2 and R3 (See Table 2) Are used to switch internal
signals to the buffer outputs. Pin 11 and 12.
Bit R2, R6 and T (See Table 3) Are used to control the
phase comparator output stage.
Bit P (See Table 6) Switches the prescaler in and out. At
Logic "1' the prescaler is bypassed and the power supply
of the prescaler is switched off.
Bits BO to B7 (See Table 7) Controls the buffers. At logic
"1" the buffers are active (low).
The circuit has two PLL chip addresses. The PLL chip
address is programmable by Pin 8. When Pin 8 is open or
normally used as a buffer the first PLL address is selected
as follows:
MSB
LSB
PLL Address 1: 1 1 a a a a 1 0= C2 (octal)
When Pin 8 is at ground the 2nd address is selected.
PLL Address 2: 1 1 a a a 1 1 a = C6 (octal)
Bit B4 must be "zero" when Pin 11 is used to output
62.5 kHz. Bits B4 and B5 have to be "zero" to output Fref
and FBY2. FBY2 is the programmable divider output
frequency divided by two.
The data transfer to the latches (signals OTF and OTB)
is initiated after the 2nd and 4th data bytes. The bus receiver
fulfills the standard 12C bus specifications.
The switching levels of Clock and Data (Pins 15 and 16)
are 0.5 x VCC1.
Table 1
Reference Divider
Division Ratio

Input Data
RO
R1
0
1
0
1

0
0
1
1

2048
1024
512
256

0
0
1
1

Test Outputs on Buffers
Pin 11
Pln12
62.5 kHz
FRet

0
1
0
1

-

-

FBY2

-

Table 3
R2

Input Data
R6

T

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

Programmable Divider - The programmable divider is
a presettable down counter. When it has counted to zero it
takes its required division ratio out of the Latches B. Latches
B are loaded from Latches A by means of signal TDI which
is synchronous to the programmable divider output signal.
Since Latches A receive the data asynchronously with the
programmable divider, this double latch scheme is needed
to assure correct data transfer to the counter.
The division ratio definition is given by:
N = 16384 x N14+8132 x N13 + ... + 4 x N2+2 x N1 + NO
Maximum ratio 32767, minimum ratio 1'7, where NO ... N14 are
the different bits for frequency information.
The counter may be used for any ratio between 17 and
32767 and reloads correctly as long as its output frequency
does not exceed 1.0 MHz.
The data transfer between Latches A and B (signal TOI)
is also initiated by any start condition on the 12C Bus.
At power-on the whole bus receiver is reset and the
programmable divider is set to a counting ratio of N=256
or higher.
Prescaler - The prescaler has a preamp and may be
bypassed (Bit Pl. The signal then passes through preamp
2. Table 6 shows the frequency ranges which may be
synthesized with and without prescaler.

Table 2
Input Data
R2
R3

Band Buffers - The band buffers are open collector
transistors and are active "low" at Bn = 1. They are designed
for 10 mA with a typical on-resistance of 70 Q. These buffers
are designed to withstand relative high output voltage in the
off-state. (16 V)
B2 and B3 buffers (Pins 11 and 12) may also be used
to output internal IC signals (reference frequency and
programmable divider output frequency + 2) for test purposes.
Buffer B2 may also be used to output a 62.5 kHz frequency
from an intermediate stage of the reference divider. The bit
B2 and/or B3 has to be zero if the buffers are used for these
additional functions.
Buffer BO, Pin 8, is also used to select the chip address.
This buffer has a higher on-voltage than the other buffers.

Output Slate
of the Phase Comparator
Normal Operation
Off (High Impedance)
High
Low
Normal Operation
Off
Normal Operation
Off

Phase Comparator - The phase comparator is phase
and frequency sensitive and has very low output leakage
current in the high impedance state.
Operational Amplifier - The operational amplifier for the
tuning voltage is designed for very low nOise, low input bias
current and high power supply rejection. The positive input
is biased internally. The op amp needs 32 V supply (VCC2)
as minimum voltage for a guaranteed maximum tuning voltage of 28 V.
Figure 4 shows a possible filter arrangement. The
component values depend very much on the application
(tuner characteristic, reference frequency, etc.).
As a starting point for optimization, the component values
in Figure 4 may be used for 7.8125 kHz reference frequency
in a multiband TV tuner.
Oscillator - The oscillator uses a 4.0 MHz crystal tied
to ground through a capacitor, used in the series resonance
mode. The voltage at Pin 17 "crystal" has low amplitude and
low harmonic distortion.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

9-294

MC44810

D/ASECTION
Basic Function
The D/A section has two separate chip addresses from
the PLL section. Three D-to-A converters that have a
resolution of 6 bits (5 bits plus sign) are on chip. The analog
output voltages are DC. The converters are buffered to the
analog outputs DA1, DA2 and DA3 by operational amplifiers
with an output voltage range that is equal to the tuning
voltage range (about 0 V to 30 V). The op amps are arranged
such that a positive or negative offset can be generated from
the tuning voltage.
Data Format
The D-to-A information consists of the D/A chip address
(CA2) and four data bytes. The first two bits of the data bytes
are used as the function address. Thus the bytes C1, C2
and C3 contain the address for the individual converter and
the 6 bits to be converted. Bit D5 is the sign (logic = 1 positive
offset, logic = 0 negative offset) and the bits DO to D4
determine the number of steps to be made as an offset from
the tuning voltage. The bits SO and S1 in the data byte RA
define the step size (Vstep) and the range of the converters
(see Table 4 and 5). The range is the same for all converters.
Bus Protocols
1_STA CA2
2_STA CA2
3_STA CA2
4_STA CA2
5_STA CA2
6_STA CA2
STA
STO
CA2
C1,C2,C3
RA

=
=
=
=
=

C1
C1
C1
C1
RA
C1
Start
Stop
Chip
Data
Data

STO
C2
C2
C2
C1
C1

STO
C3
C3
C2
C1

to the IC in random order with up to four in one sequence.
The same converter may be loaded up to four times as
shown in example 6 (see Bus Protocols).
Figure 7. Definition of Bytes

Cl_Converter 1

RA_Range Selection

The D/A section has two separate chip addresses. These
are programmable by Pin 8 as in the PLL section. When Pin
8 is open or normally used as a buffer, the first DIA address
is selected as follows:
MSB
LSB
D/AAddress1:11 0000 00= CO (octal)
When Pin 8 is at ground the second D/A address is selected.
D/A Address 2: 1 1 0 0 0 1 0 0 = C4 (octal)

STO
RA STO
C3 STO
C1
STO

Condition
Condition
Address Byte for D/A Section
Bytes for D/A Converters
Byte for Range

Table 4. Output Voltage
VOA

=Vtun ± Vstep (DO + 201 + 402 + 803 + 1604)

05 = "1" positive sign; 05 = "0" negative sign

The bus receiver accepts up to four data bytes in random
sequences. If more than four data bytes are received, the
fifth and following data bytes are ignored. The same data
byte may be sent up to four times as shown in example 6.
After the chip address (CA2) , up to four data bytes may
be received. If more than four bytes are received the fifth
and following bytes are ignored and the last acknowledged
pulse is sent after the fourth data byte. The data transfer to
the converters (signal DTC) is initiated each time a complete
data byte is received.
Figure 7 shows some examples of the permissible bus
protocols of the D-to-A section. The data bytes may be sent

Vtun: Tuning Voltage set by PLL
Vstep: Voltage STEP (LSB) of the O/A converters

Table 5. Range Selection

51

SO

Typ. Step Size
Vstep
(mV)

0
0
1
1

0
1
0
1

225
125
70
40

Input Data

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
9-295

Guaranteed Range
31 Steps
(V)
6.25
3.40
1.90
1.05

•

,

I

MC44810
D/A Converters - The D/A converters convert S-bit into
an analog current of which the polarity is switched by the
sixth bit. The reference voltage of the converters is
programmed by two bits (SO, Sl of the RA-byte) to
determine the scaling factor. The analog currents are then
converted into voltages by means of op amps 2, 3 and 4
and the voltages are added to the tuning voltage (Vtun, see
Figure 4) to generate the positive or negative offset.
If the data bits DO to DS are logic "0" the three D/A output
voltages on Pins 2, 3 and 4 are equal to the tuning voltage
(Pin 1) within the input offset voltages of the op amps
(maximum error O.S LSB).

The four amplifiers have the same output characteristics
with the maximum output voltage being 4.0 V lower than VCC2
in the worst case. The four analog outputs are short circuit
protected. At power-up the D/A outputs are undetermined.
The four op amp outputs require external resistors (390 0)
for stability.
The D/A converters are guaranteed to be monotonic with
a voltage step variation of ± O.S LSB. The temperature
stability is ± O.S LSB from 0° to 70°C.

Table 6

Table 7

Input Data
Prescaler Function
P
0

Active
Bypassed, Power Supply Off

1

Input Data

Band Buffers

BO ... B7

(Output Siale)

0
1

Off
On

Table 8. System Application (Using a 4.0 MHz Crystal)
With Inlernal Prescaler (P=O)
Input Data
R1

RO

Reference
Divider
Division Ratio

0
0
1
1

0
1
0
1

2048
1024
512
256

Reference
Frequency (1)
(Hz)
1953.125
3906.25
7812.5
15625.0

(1) With 4.0 MHz Crystal

.

Wilhout Internal Prescaler (P=l)

Frequency
Steps
(kHz)

Max Input
Frequency
(MHz)

Frequency
Steps
(kHz)

Max Input
Frequency
(MHz)

15.625
31.25
62.5
125

512
1024
1300 (2)
1300 (2)

1.953125
3.90625
7.8125
15.625

64
128
165(3)
165(3)

.

(2) limit of Prescaler

. .

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

9-296

..

(3) Limit of Programmable DIvider

MOTOROLA

TDA3190

SEMICONDUCTOR-----TECHNICAL DATA

4.2 WATT

TV Sound System

TV SOUND SYSTEM

The TDA3190 is a 4.2 W sound system designed for television and related
applications. Functions performed by this device includes: IF Limiting, IF
amplifier, low pass filter, FM detector, DC volume control, audio preamplifier, and
audio power amplifier.

SILICON MONOLITHIC
INTEGRATED CIRCUIT

• 4.2 W Output Power (VCC = 24 V, RL = 160)
• Linear Volume Control
• High AM Rejection
• Low Harmonic Distortion
• High Sensitivity

PSUFFIX
PLASTIC PACKAGE
CASE 648C

BLOCK DIAGRAM

15

14

9

PIN CONNECTIONS
11

'----010

IF Input 1

Deemphasis
5 Ripple Rejection
Supply Voltage

1 Output

2

o
3

8

6

16

DC Volume
Control

(TopViewj

up
4

5

12

13

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

9-297

Compensation
Gain

TDA3190
MAXIMUM RATINGS
Rating

Symbol

Value

Unit

VCC

9.0 to 28

V

10

2.0
1.5

A

Supply Voltage Range
Output Peak Current

lNonrepetitive)
Repetitive)

VI

1.0

V

Operating Temperature Range

Input Signal Voltage

TA

Oto+ 75

DC

Junction Temperature

TJ

150

DC

ELECTRICAL CHARACTERISTICS (VCC = 24 V, 10 = 4.5 MHz, al = ±25 kHz, TA = 25DC, unless otherwise noted.)
Symbol

Characteristics
Quiescent Output Voltage (Pin 11)
VCC=24V

Min

Typ

Max

11

12

13

Quiescent Drain Current
(Pl =22kn)VCC=24V

ID
11

22

35

Output Power
(d = 10%, fm = 400 Hz)
VCC=24V,RL=160
VCC= 12 V, RL =8.00
(d = 2%, fm = 400 Hz)
VCC=24V,RL=160
VCC= 12V, RL=8.00

Po

Input Limiting Threshold Volts (-3.0 dB) at Pin 1
af = ±7.5 kHz, fm = 400 Hz, set Pl for 2.0 Vrms on Pin 11

VI

mA
W

-

4.2
1.5

-

-

3.5
1.4

-

-

40

100

-

0.75

-

-

Distonion (PO = 50 mW, fm = 400 Hz, af = ± 7.5 kHz)
VCC=24V,RL=160
Frequency Response of Audio Amplifier (-3.0 dB)
(RL = 16 Q, C10 = 120 pF, C12 = 470 pF, Pl = 22 kn)
Rf=820
Rf=470

B

Recovered Audio Voltage (Pin 16)
(VI'" 1.0 mY, fm = 400 Hz, af = ± 7.5 kHz, Pl = 0)

Vo

Amplitude Modulation Rejection
(VI'" 1.0 mY, fm = 400 Hz, m = 30%)

AMR

Signal and Noise to Noise Ratio
(VI'" 1.0 mY, Vo = 4.0 V, fm = 400 Hz)

S+N
N

Input Resistance (Pin 1)
(VI = 1.0 mY)

q

Input Capacitance (Pin 1)
(VI = 1.0 mY)

Ci

DC Volume Control Attenuation
(Pl = 12 kn)

-

I1V
%

Hz

-

-

70 to 12k
70 to 7.0 k

-

-

120

-

-

55

-

50

65

-

-

30

-

-

5.0

-

-

90

-

mV
dB
dB
kn
pF

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
9-298

Unit
V

QO

dB

TDA3190
TEST CIRCUIT
Ll

--+
~

L= 10f!H
0 0 =60
fo =4.5MHz

~~F
6

C1
10OnF

C7
9.0pF

C6

C12
470pF

Cl0
120pF

C9,1
lOOnF ~

~
10

7

14

Input o----j
Rl
50n

R3
22kn

TDA3190

3

4,5,
12,
13

16

R2
4.7n

T

.

C3
47n F

R4
1.0

~

r-----Z>-

C2
7nF

Cll
l000f!F/16V

11

1

T T

8

~

15
Rf

Volume

PI
22kn
lin /

VCC
,1 C14
~ loof!F/35V

C5

',.i

50f!F/16V
C4
T50f!F/16V

'C8
7.5nF

C13
T220nF

RC-75flS

Vee

12

24

V

AL

8

16

Af

82

47

n
n

TYPICAL CIRCUIT CONFIGURATION
R3
C4

C5

Vo

r~-If----"V\I\Rf~

r-----------

15

9

----

~C14

14

--,

I

I
I
I
I
I
I
I
I

111

11

16

PI

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
9-299

MOTOROLA

TDA33018

SEMICONDUCTOR-----TECHNICAL DATA

TV COLOR PROCESSOR

TV COLOR PROCESSOR
This device will accept a PAL or NTSC composite video signal and output the
three color signals, needing only a simple driver amplifier to interface to the picture tube. The provision of high bandwidth on-screen display inputs makes it
suitable for text display, TV games, cameras, etc. The TDA3301 B has user controllaws, and also a phase shift control which operates in PAL, as well as NTSC.

SILICON MONOLITHIC
INTEGRATED CIRCUIT

• Automatic Black Level Setup
•

Beam Current Limiting

• Uses Inexpensive 4.43 MHz to 3.58 MHz Crystal
• No Oscillator Adjustment Required
• Three OSD Inputs Plus Fast Blanking Input
• Four DC, High Impedance User Controls

PSUFFIX
PLASTIC PACKAGE
CASE 711

• Interfaces with TDA33030B SECAM Adaptor
• Single 12 V Supply
• Low Dissipation, Typically 600 mW

PIN CONNECTIONS

Chroma Input

Hue Control/NTSC Switch

ACC Capacitor

+ t2V

Chroma DL Driver, Emitter

Ground

1.0 V Composite Video Input

Chroma DL Driver, Collector
Saturation Control

Delayed Luma input
Luma DL Drive and 3.0 Inverted Output

Identification Capacitor
V Input

Luma Emitter Load

U Input

Luma Collector Load

90° Loop Capacitor

Contrast Control

Oscillator Loop Filer

Black Level Clamp

Crystal Drive

Brightness Control

Drystal Feedback

Peak Beam Umit Adjust

Ground

Frame Pulse Input

Blue Output

Sandcastle Pulse Input

Blue Output Clamp Capacttor

OSD Input Green

Blue Output Feedback

OSD Input Red

Green Output

OSD Input Blue

Green Output Clamp Capacitor

OSD Input Fast Blanking

Green Output Feedback

Red Output Feedback

Red Output

Red Output Clamp Capacitor

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

9-300

TDA3301B
MAXIMUM RATINGS (TA =+ 25°C, unless otherwise noted.)
Rating
Supply Voltage (Pin 39)
Operating Temperature Range
Storage Temperature Range

Symbol

Value

Unit

VCC

14

Vdc

TA

Oto+ 70

°c

Tstg

-65 to +150

°c

ELECTRICAL CHARACTERICISTICS (TA = 25°C, VCC = 12 V)
Pin

Min

Typ

Max

Unit

Supply Voltage
Supply Current

39

10.8

12
45

13.2
60

V
mA

Composite Video Input
Video Input Resistance
Video Gain to Pin 35
Input Window

37

1.0
18
3.2
0.7-3.2

23
3.6

Chrome Input (Burst)
Input Resistance
ACC Effectiveness

1
1
4

Characteristics

-

13
2.7
0.8-3

OSD Input
OSD Drive Impedance
OSD Frequency Response (-3.0 dB)
OSD Max Gain
Gain Difference Between Any Two

24,25,26

Beam Current Ref. Threshold
Differential Voltage
Beam Current Ref. Input Current
Differential Current
Luminance Gain Between Pin 36 and Outputs (Depends on
R333 and R34)
Luminance Bandwidth (-3.0 dB)
Output Resistance
Residual Carrier (4.43 Mcls)
PAL Offset (H/2)
Difference in Gain Between Y Input and any RGB olp
U Input Sensitivity for 5.0 V Blue Output

10

-

-

200

-

100
5.0
1.2

0.5

0.7

1.0
180

9.0

-

-

-

-

-

3.0

Vp-p
kn
Vp-p
V
mVp-p
kn
dB
V

n

-

MHz

15

%

2.3
20
+1.51-0.5
1.0

V
mV
IlA

-

7.2

16,19,22

1.7

2.0

-

4.7

14,17,20

9.0
120

-

-

170
30

mVp-p

-

300
150
50

5.0

-

%

8

-

340

-

mVp-p

14,17,20

10

%

-

-

-

-

MHz

n

-

-

Oscillator Capture Range

350

-

-

U Ref. Phase Error

-

-

5.0

Degrees

Matrix Error

Hz

-

-

5.0

Degrees

Color Kill Attenuation

14,17,20

50

-

-

dB

Contrast Tracking OSD/LumaiChroma

14,17,20

-

-

-

dB

OSD Contrast Tracking

14,17,20

OSD Enable Slice Level

23

-

0.7

-

Sandcastle Slice Level
Burst Gate
Line Blanking
R Input V27 > 7.0 V
V27<7.0V

27
7.2
2.6
5.0
22

8.0
3.0

-

kn

Frame Slice Level
R Input

28

2

-

2.8
15

3.6

V
kn

3.4 x 129

4 x 129

4.6 x 129

V Ref. Phase Error

6.5
2.0

-

Peak Beam Limiter Threshold
(129 Min = 250 1lA)

-

±2.0

-

dB
V
V

,

Pin 29 Input Resistance

29

-

5.0

-

kn

Pin 29 Open Circuit Voltage

29

-

10.6

-

V

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
9-301

TDA33018
INPUT/OUTPUT FUNCTIONS
The brilliance control operates by adding a pedestal to the output
signals. The amplitude of the pedestal is controlled by Pin 30.

Figure 1. Brillance Control

During CRT beam current sampling a standard pedestal is
substituted, its value being equivalent to the value given by V30 Nom
Brightness at black level with V30 Nom is given by the sum ofthreegun
currents at the sampling level, i.e. 3x20 IlA with 100 k reference
resistors on Pins 16, 19, and 22.
During picture blanking the brilliance pedestal is zero; therefore, the
output voltage during blanking is always the minimum brilliance black
level (Note: Signal channels are also gain blanked).

I
I

1

I
I

I
I ....

~I!il

::= I ~
o

1~

ao

~o

4.0

BRIWANCE CONmOL M V30

Figure 3. Contrast Control

Figure 2. Saturation Control Voltage

o

VSM
1.0

2.0

3.0

4.0

5.0

o

1.0

2.0

V32M
3.0

4.0

5.0

2.0
-10

4.0
6.0

i-20

8.0

:z

o
~

ilo

:z
Q 12

~ -30

~

!;c
:::>

-40

ffi

14

~

16

18
-50

20
22

24
Note: Nominal 100% saturation point is given by choice of R2 which
sets ACC operating point.
Pin5isautomaticailypuiledtogroundwithamisidentifiedPALsignal.

Note: Pin 32 is pulled down bytheoperationofthepeakbeam limiter.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
9-302

TDA3301B
Figure 4. Block Diagram

t~

31

34

30

32

29

-----

6

Black
level
Clamp

r-

Brilliance
Control

I

Beam
Umijing

t

I
DC
Level
Shifter

33

3 Way
Splitter

I

I

r

39
+12V

I

I

Luma
Contrast

{>

Contrast
Controller

I

I

35

~

37

1

t
I

Blanking
Controller

!

-1

-1

Hue
Control

r=1

1

I

28

Filter

13

.J:

I

U
Ref
90° 
Shiller

I

~
6

7

8

1

+
U Del

r

H/2
Bistable

1

1 VDet
V
Ref

I 90° Det I
I

t

I

S:Ch

1
U

~~
I

I
9

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

9-303

1 FiRer

V

tu

I

1

I

J

DelayUne
Driver

5

t

b-

Ident
Det

~

4

27

Burst Gate

I

Color
Contrast &
Saturation

3

0

I

r'---i

14
17
20
23

X31

Timing
Logic
Counters A & B

Color Difference
Matrix & Color Killer

I
ACC
Del

40

Output
Amplifier

H
-i

t

2

}--

15
18
21

F
TDA3301B

Color
Kill Logic

ACC
Control

22

~
J-

~

16
19

CRT Beam
Current
Clamp
X3

J=:

38

i-

I

24
26
25

OSD
Black level
Clamp &
Contrast X3

H/2
Switch

!

I
I

4.33 MHz
VCO

ill

112

•

Burst
Det

H/2
Switch

~
10

I
I

TDA3301B
Figure 5. Hue Control
Burst
Leado (3.58 MHz)

The hue control acts only during burst gating to give a ± ~oC
phase shift between the burst and chrominance signal. On the
TDA3301 BNTSCselection is independenlofV40 and the control can
be operated in both NSTC and PAL

50

~i---------------~

en
ttl

a:

30
20

C!l

~ 10

~

I

1.0

5.0

2.0

V~

7.0

6.0

~ 10

a:

:::>

'" 20-

30~-

50 -

Burst
LagO

CIRCUIT OPERATION
Chromlnance Decoder
The chrominance decoder section of the TDA3301 B
consists of the following blocks:
Phase-locked reference oscillator; Figures 6, 7 and 8.
Phase-locked 90 degree servo loop; Figures 8 and 9.
U and V axis decoders
ACC detector and identification detector; Figure 10.
Identification circuits and PAL bistable; Figure 11.
Color difference filters and matrixes with fast blanking
circuits.
The major design considerations apart from optimum
performance were:
• A minimum number of factory adjustments,
• A minimum number of external components,
• Compatibility with SECAM adapter TDA3030B,
• Low dissipation,
• Use of a standard 4.433618 Mhz crystal rather
than a 2.0 fc crystal with a divider.

Figure 6. Voltage Controlled Osscillator (VCO)
+12V

Rl

=
12

Ql r--.--~-----tVF

I
Figure 7. Vector Diagram for VCO

Reference Regeneration
The crystal VCO is of the phase shift variety in which the
frequency is controlled by varying the phase of the feedback.
A great deal of care was taken to ensure that the oscillator loop
gain and the crystal loading impedance were held constant in
order to ensure that the circuit functions well with low grade
crystal (crystals having high magnitude spurious responses
can cause bad phase jitter). It is also necessary to ensure that
the gain at third harmonic is low enough to ensure absence of
oscillation at this frequency.

a=1

-------/7"
/

/
Ix

//

/
/

/

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
9-304

VF

TDA33018
By referring to Figures 6 and 7 it can be seen that the
necessary ± 45°C phase shift is obtained by variable addition
of two currents 11 and 12 which are then fed into the load
resistance of the crystal tuned circuit R1. Feedback is taken
from the crystal load capacitance which gives a voltage of VF
lagging the crystal current by 90 0 •
The RC network in the T1 collector causes 11 to lag the
collector current of T1 by 45 0 •
For SECAM operation, the currents 11 and 12 are added
together in a fixed ratio giving a frequency close to nominal.
When decoding PAL there are two departures from normal
chroma reference regeneration practice:
a) The loop is locked to the burst entering from the PAL
delay line matrix U channel and hence there is no
aHernating component. A small improvement in signal
noise ratio is gained but more important is that the loop

filter is not compromised by the 7.8 kHz component
normally required at this point for PAL identification
b) The H/2 switching of the oscillator phase is carried out
before the phase detector. This implies any error signal
from the phase detector is a signal at 7.8 kHz and not dc.
A commutator at the phase detector output also driven
from the PAL bistable coverts this ac signal to a dc prior
to the loop filter. The purpose of this is that constant
offsets in the phase detector are converted by the
commutator to a signal at 7.8 kHz which is integrated to
zero and does not give a phase error.
When used for decoding NTSC the bistable is inhibited, and
slightly less accurate phasing is achieved; however, as a hue
control is used on NTSC this cannot be considered to be a
serious disadvantage.

Figure 8. Block Diagram of Reference Section
UAxis

V Axis

III

U Signal
from PAL_---i

I

DelayUne

900 Reference Generation

To generate the U axis reference a variable all-pass network
is utilized in a servo loop. The output of the all-pass network
is compared with the oscillator output with a phase detector of
which the output is filtered and corrects the operating point of
the variable all-pass network (see Figure 9).
As with the reference loop the oscillator signal Is taken after
the H/2 phase switch and a commutator inserted before the
filter so that constant phase detector errors are cancelled.

For SECAM operation the loop filter is grounded causing
near zero phase shift so that the two synchronous detectors
work in phase and not in quadrature.
The use of a 4.4 MHz oscillator and a servo loop to generate
the required 90 0 reference signal allows the use of a standard,
high volume, low cost crystal and gives an extremely accurate
90 0 which may be easily switched to 00 for decodi(lg AM
SECAM generated by the TDA3030B adapter.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
9-305

TDA33018
Figure 9. Variable All-Pass Network

+12V

4.0k

RRer 9
C D-'I_----+---+---l

t---_90°
Control

DC

4.43MHz
from Osc

~----..

SECAM Switching

Figure 10. ACC and Identification Detectors
ToR·YRRer

To B·YRRer

7.0V

4.0k

4.0k

4.0k

4.0k

I--"'VIIV-_ +Burst

Gate

Ident
RRer

ACC
RHar

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
9-306

TDA3301B
ACC and Identification Detectors
During burst gate time the output components of the U and
also the V demodulators are steered into PNP emitters. One
collector current of each PNP pair is mirrored and balanced
against its twin giving push-pull current sources for driving the
ACC and the identification filter capacitors.
The identification detector is given an internal offset by
making the NPN current mirror emitter resistors unequal. The
resistors are offset by 5% such that the identification detector
pulls up on its filter capacitor with zero signal.
Identification
See Figure 11 for definitions.
Monochrome 11 > 12
PAL Ident. OK 11 < 12
PAL Ident. X
11 > 12
NTSC
13> 12

When Vref2 is exceeded by 0.7 V then Latch 2 is made to
conduct until C is completely discharged and the current drops
to a value insufficient to hold on Latch 2.
As Latch 2 turns on Latch 1 must turn off.
Latch 2 turning on gives extra trigger pulse to bistable to
correct identification.
The inhibit line on Latch 2 restricts its conduction to alternate
lines as controlled by the bistable. This function allows the
SECAM switching line to inhibit the bistable operation by firing
Latch 2 in the correct phase for SECAM. For NTSC, Latch 2
is fired by a current injected on Pin 6.
If the voltage on C is greater than 1.4 V, then the saturation
is held down. Only for SECAM/NTSC with Latch 2 on, or
correctly identified PAL, can the saturation control be
anywhere but minimum.
NTSC Switch

Only for correctly identified PAL signal is the capacitor
voltage held low since 12 is then greater than 11.
For monochrome and incorrectly identified PAL signals 11 >12
hence voltage Vc rises with each burst gate pulse.
When Vref1 is exceeded by 0.7 V Latch 1 is made to conduct
which increases the rate of voltage rise on C. Maximum
current is limited by Rl.

NTSC operation is selected when current (13) is injected into
Pin 6. On the TDA3301 B this current must be derived
externally by connecting Pin 6 to + 12 V via a 27 k resistor (as
on TDA3300B). For normal PAL operation Pin 40 should be
connected to + 12 V and Pin 6 to the filter capacitor.

Figure 11. Identification Circuit
NTSC
Switch
+12V

1----01 SECAM Switching
Une

III
I

R2
Vc 440

Vreft
+Trigger
Burst
Gate
latch 2
Inhibtt

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
9-307

TDA3301B
Color Difference Matrixing, Color Killing,
and Chroma Blanking
During picture time the two demodulators feed simple RC
filters with emitter follower outputs. Color killing and blanking
is performed by lifting these outputs to a voltage above the
maximum value that the color difference signal could supply.
The color difference matrixing is performed by two
differential amplifiers, each with one side split to give the
correct values of the -(B-Y) and -(R-Y) signals. These are
added to give the (G-Y) signal.

The three color difference signals are then taken to the
virtual grounds of the video output stages together with
luminance signal.

Sandcastle Selection
The TDA3301 B may be used with a two level sandcastle
and a separate frame pulse to Pin 28, or with only a three level
(super) sandcastle. In the latter case, a resistor of 1.0 Mil is
necessary from + 12 V to Pin 28 and a 470 pF capacitor from
Pin 28 to ground.

Figure 12. Color Difference Stages
Color Kill
&
Blanking

+

+

R

R
B-Y

R-Y

C

RC

R

.---_B-Y

R-Y ....- -.........

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
9-308

Figure 13. Timing Diagram

,-------------~I,r/--------------,
Frame Pulse F (V28)

s:

0
--I
0
JJ
0
r
»
r

)LJ\

Z

I

I

I
I
Sand castle L (V27)

!LsI

m

I

»
~

to

L--------il

Z

m
W
0
to

JJ

~

0

m
(5
en

I

U:I

:I U

I

~

C

l>

I

I

~II

m

<

U

_ _ _ _ _ _ _ _ _ ----.1
I
- I
I
Counter A Output

0

(5
m

I

I
I
Clock To A

--I

L

I
I

c..l
c..l

I

I
I

I
I

I
I

I
I

....

o

OJ

I~:--~:-------I
I

- - -_ _ _ _ _

I
Ie

Counter B Output

0

~

»

CRT
Sample
Time
S

I
.1

Insert Brilliance
Reference Pedestal
S+B

Ii

I"

7I

Gain Blank Ail Signals
F+L+B+A

·1

H

TDA3301B
Timing Counter for Sample Control

In order to control beam current sampling at the beginning
of each frame scan, two edge triggered flip-flops are used.
The output Aof the first flip-flop A is used to clock the second
flip-flop B. Clocking of Aby the burst gate is inhibited by a count
of A.B.
The count sequence can only be initiated by the trailing
edge of the frame pulse. In order to provide control signals for:

LumalChroma blanking
Beam current sampling
On-screen display blanking
Brilliance control
The appropriate flip-flop outputs ar matrixed with sandcastle
and frame signals by an emitter-follower matrix.

Figure 14. Timing Counter
+

Frame

Burst
Gate

_~oN---l

_-vvv--------......l--_~

On-8creen Display Inputs
Each section of the OSD stages consists of a common
emitter input stage feeding a diversion gate controlled by the
contrast control. During burst gate time a feedback loop is
activated which clamps the signal at the input coupling

capacitor. This ensures that the current in the diversion gate
is zero at black level and the OSD black level insensitive to
contrast control, also the inputs ignore signals below black,
e.g. sync, pulses.

Figure 15. OSD Stage
To Summing
Amp

Burst

+

Gate
Pulse

OS0-p

.. 1

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
9-310

TDA33018
Video Output Sections
Each video output stage consists of a feedback amplifier in
which the input signal is a current drive to the virtual earth from
the luminance, color difference and on-screen display stages.

A further drive current is used to control the DC operating
point; this is derived from the sample and hold stage which
samples the beam current after frame flyback.

Figure 16. Video Output Section

DC Control
Drive

r------:~

Output

+
Video
Blanking

Luminance
Drive

OSD
Drive

Color
Difference
Drive

Figure 17. Complete Video Output Sections

External
Video Output
CRT

Signals

r

Ref

R
Enable

Vref

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
9-311

TDA33018
Figure 18. Typical Video Output Stage

- - - - . - - - - - - - - - - - +250V
1.0nF

12k

loOk

12k

CRT
Cathode
22k

IN4148

22k
Gain
Video
BF789
Drive --'VVI.---W\r--f--=.:...:...:..:C-----+12-V- - - - - -

Spark
Gap

T

loOk

To Other
Stages

4.7k

1.5k
1.5k

F e e d b a c k . . - - - - - - - - - - _ - - - - - ' l N Y - - -....
3.3k

r

33pF

'RF is chosen to suit CRT characteristics, typically 120 k.

Figure 19. Class A Video Output Stage with Direct Feedback

+250V

10k
1.0k

.----Yvv------. CRT Cathode
Gain
Video _-----v'/Ar---....----j
Drive
2.0k
2.2k
180
Feedback . . - - - - - - - - - - - - '
t80

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
9-312

TDA33018
Figure 20. Typical PAL Application

~

4711F
Ilf-----ITT'L-

+ Video
1.0Vp·p
lOI1H

IIH~~~

J

~~
IIHf--lOOI1F

LOI1F

1~.1!!..

"~h

~f

'I
82

lOI1H

'I

1.8M

1.Ok

CD ~

r

11[------1

6

35

7

34

8

33

1.0nF

"H

"H~

LOI1F

U

10

~,\l~ J

TDA3301B

4.43~12

10nF

~

2.7k
220k

Conlrast

j,

,II

13

28

14

27

1.0k

~~nF
~nF

16

~onF
23

>-----1~
19

22

,.----'-"-

- Video
3.0Vp-p

Bril liance
1.0k

~HI

17

10nF

1

~h
.1ID"

--l~

1.0k

330

30

11

.£"'"'"

"H12pF

l·~

1.0k

32~dnF
f---jll

10~~9
11f-----1

II

II
II
II
II,

100M

Super
Sandcastle
75

J

75

J

75

J

75

J

G
R}

Data
I:puts

B

Fast
BIanking

~~

~

Blue
Blue
Drive Feedback

1+ 12V

~

36

V

390

38

5

rr- LOnF

~

3

11[------1
10nF

3-~;g

39

4
1.011F

l

2

T

>--rY'rn.
400

Saluration

~

Green Green
Drive Feedback

Red
Red
Drive Feedback
NOTE: When not using Super Sandcastle a
positive vertical blanking pulse must
be applied to Pin 28.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
9-313

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

9-314

Automotive Electronic Circuits

In Brief ...
Page

Motorola Linear has established itself as a global leader
in custom integrated circuits for the automotive market. With
multiple design centers located on four continents, global
process and assembly sites, and strategically located
supply centers, Motorola serves the global automotive
market needs. These products are key elements in the
rapidly growing engine control, body, navigation,
entertainment, and communication electronics portions of
modern automobiles. Though Motorola is most active in
supplying automotive custom designs, many of yesterday's
proprietary custom devices become standard products of
today available to the broad base manufactures who support
this industry. Today, based on new technologies, Motorola
offers a wide array of standard products ranging from rugged
high current "smart" fuel injector drivers which control and
protect the fuel management system, through rigors of the
underhood environment, to the latest SMARTMOS'M
switches and series transient protectors. Several devices
are targeted to support microprocessor housekeeping and
data line protection. A wide range of packaging is available
from die, flip-chip, and SOICs for high density layouts, to low
thermal resistance mUlti-pin, single-in-line types for high
power controllCs.

Voltage Regulators

10-2

Electronic Ignition

10-2

Special Functions

10-3

Index .......................................... 10-7
Data Sheets .................................... 10-8

l

•

,

ASE 29

CASE 314D
PLASTIC
S,.T, T-1 SUFFIX

PLASTIC
•..... ,SUffiX

• •
________
"

_CASEm

CASE 646
. PLASTIC

.....

CASE 626
PLASTIC
P.SUFFIX

CASE 369A
PLASTIC
DTSUFFIX

PLASTIC

PSUFFIX

..

~

'

~t_~_~_~_~_.

:_~_C_~_i_1~_~G_x ~~ ;_~_'~_;_·~_~~
__

____

__________________

~

___________ _

Voltage Regulators
.function

.....

f~1\'!lre!!'

----

SIJff!X!
.' ellS!'

Pev/t::'e

Low Dropout Voltage Regulator

Positive fixed and adjustable output voltage regulators which
maintain regulation with very low input to output voltage differential.

Z/29,
T/221A,
T/314D,
DT/369A

LM2931,C

Low Dropout Dual Regulator

Positive low voltage differential regulator which features dual 5.0 V
outputs, with currents in excess of 750 rnA (switched) and 10 rnA
standby, and quiescent current less than 3.0 rnA.

T/314D

LM2935

Automotive Voltage Regulator

Provides load response control, duty cycle limiting, under/overvoltage
and phase detection, high side MOSFET field control, voltage regulation
in 12 V alternator systems.

DW/751D

MC33092

Low Dropout Voltage Regulator

Positive 5.0 V, 500 rnA regulator having on-chip power-up-reset circuit
with programmable delay, current limit, and thermal shutdown.

T/314

MC33267

Electronic Ignition
$!Jftlx .

Fmiclio!l
Electronic Ignition Circuit

.':

f~A~ures

Used in high energy variable dwell electronic ignition systems with
variable reluctance sensors. Dwell and spark energy are externally
adjustable.

I

b~$I?:

tl~'JjC'"

P/626,

MC3334

D1751

Flip-Chip Electronic
Ignition Circuit

Same as MC3334 - Mirror image die for inverted "bumped"
mounting to substrate

Flip-Chip

MCCF3334

Flip-Chip Electronic Ignition
Control Chip

Used in high energy electronic ignition systems requiring differential Hall
Sensor control. "Bumped" die for inverted mounting to substrate.

Flip-Chip

MCCF33093

Flip-Chip Electronic Ignition
Control Circuit

Used in high energy electronic ignition systems requiring single Hall
Sensor control. "Bumped" die for inverted mounting to substrate.

Flip-Chip

MCCF33094

Flip-Chip Electronic Ignition
Control Circuit

Used in high energy electronic ignition systems requiring single Hall
Sensor control. Dwell feedback for coil variation. "Bumped" die for
inverted mounting to substrate.

Flip-Chip

MCCF79076

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

10-2

Special Functions
,

Function

"

Features

Low Side Protected Switch

Single automotive low side switch having CMOS compatible input, 1.0 A
maximum rating, with overcurrent, overvoltage, and thermal protection.

High Side Driver Switch

Sufllxi
Cese

Device

T/221 ,
T-1/314D,
DW1751G

MC3392

Drives loads from positive side of power supply and protects against
high voltage transients.

T/314D

MC3399

High Side TMOS Driver

Designed to drive and protect N-channel power MOSFETs used in high
side switching applications. Has internal charge pump, externally
programmed timer, and fault reporting.

P/626,
D1751

MC33091

Mi-Bus Interface Stepper Motor
Controller

High noise immunity serial communication using Mi-Bus protocol to
control relay drivers and motors in harsh environments. Four phase
signals drive two phase motors in either half or full-step modes.

DW/751G

MC33192

Quad Fuel Injector Driver

Four low side switches with parallel CMOS compatible input control,
:s 7.0 mA quiescent current, 0.25 Q rds(ON) at 25°C independent
outputs with 3.0 A current limiting and internal 65 V clamps.

T/821C-02

MC33293

Quad Fuel Injector Driver

Four low side switches with parallel CMOS compatible input control,
:s 5.0 mA quiescent current, 0.7 Q rds(ON) at 25°C independent outputs
with 3.0 A current limiting and internal 65 V clamps.

T/821C-02

MC33295

Octal Serial Output Switch

Eight low side switches having 8-bit serial CMOS compatible input
control, serial fault reporting, :S 4.0 mA quiescent current, independent
0.45 Q rds(ON) at 25°C outputs with 3.0 A minimum current limiting and
internal 55 V clamps.

P!738

MC33298

Integral Alternator Regulator

Control device used in conjunction with an MCCF33096 Darlington
companion device to monitor and control the field current in alternator
charging systems. "Bumped" die for inverted mounting to substrate.

Flip-Chip

MCCF33095

Darlington Drive Chip

Darlington companion device for MC33095 used to control the field
current in alternator charging systems. "Bumped" die for inverted
mounting to substrate.

Flip-Chip

MCCF33096

Peripheral Clamping Array

Protects up to six MPU 110 lines against voltage transients.

D1751

TCF6000

Automotive Direction Indicator

Detects defective lamps and protects against overvoltage and short
circuit hazards in automotive turn-signal applications. Replaces
UAA 1041 with improved noise immunity.

P/626,
D1751

UAA1041B

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
10-3

Quad Fuel Injector Driver
MC33293T TJ ~ -40° to +150°C, Case 821 C

The MC33293T is a monolithic quad low-side
switching device having CMOS logic, bipolar/
CMOS analog circuitry, and DMOS power FETs.
All inputs are CMOS compatible. Each independent output is internally clamped to 65 V, current
limited to 2: 3.0 A, and has an rds(on) of ,,; 0.25 Q
with VPWR 2: 9.0 V and may be paralleled to lower
rds(on). Fault output reports existence of open
loads (outputs On or Off), shorted loads, and over
temperature condition of outputs. A shorted load
condition will shut off only the specific output
involved while allowing other outputs to operate
normally. An overvoltage condition will shut off all
outputs for the overvoltage duration. A single/dual
mode select pin allows either independent inpuV
output operation or paired output operation.

~--'-:lo-t

5<..>

1.4

(3

1.3

~

IT:

ti:
a
V5

1.2

~

/

f-

:::J

5a 1.1
~ 1.0_5

v

1.3

!:ia

1.2

>
z
a

f-

I~

~0=800mA

./

1.1

:::J
a 1.0
C:

~ 0.9

0.8
-50

150

~

I

-- ---

o
50
100
TA, OPERATING AMBIENT TEMPERATURE (0G)

~

4.0

w

74

!:i

73

a
>

~ 3.0

0..

::E

(!)

«

VIH ....,.

~ 2.0

f-

:::J

~ 1.0

0_
<..>

+VS=5.0V -

...J

-I

>"
-50

71

50
100
TA, OPERATING AMBIENT TEMPERATURE (OC)

~

70
69

~ -9
3
-9

US

-9
5
-9

w
~

-9

g:;
~

IT:
IT:

co

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9-5

o

150

z
a 2.0
~
IT:
:::J

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0..

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7
-9
8

100

2.5

\

6

50

~

'" 1\

4

/

Figure 10. Fault Output Saturation
versus Sink Current

Transient Breakdown
Pulse Width = 1.0 ms

\.

!:i

/

TA, OPERATING AMBIENT TEMPERATURE (0G)

Figure 9. Reverse Breakdown Voltage
versus Temperature

tlJ

10= 100 rnA

/

o

150

/'

/

72

:::J
0..

VIL -'"

0

./

...J

<..>
f-

!3
0..

~

/'

(!)

!:i

52

150

75

5.0

J:

~

I
10 =400mA

Figure 8. Output Clamp Voltage
versus Temperature

(!)

~

1
Yin =4.0V

f-

Figure 7. Input Voltage
versus Temperature

~
9

/'

:::J
0..

+VS = 14 V
RL=O

o
50
100
TA, OPERATING AMBIENT TEMPERATURE (0G)

o

~
w

(!)

1.0

0.

...!..o=20mA

i

U)

0.5

Cl

>

50

100

4.0

150

TA, AMBIENT TEMPERATURE (OC)

6.0

8.0

Isink, SINK CURRENT (rnA)

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

10-19

12

MC3391
Figure 11. Turn-On Waveform

Figure 12. Turn-Off Waveform

10

Vout

Figure 13. Output Current versus
Supply Voltage

Figure 14. Maximum Load Inductance
versus Output Current
~ 0.5
w

1.5

g 1.25

ffi
8!

1.0

-

({

"" ~

Vin=4.0V
RL=O
_
TA=25°C

"50.75
5
o. 0.5
10

"

'"~

, e a t Sink

Infin~e Heal Si~

° 0.25

j$ 0.4

:::>

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:::>

~

~

'~

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0.3

"-

• 0.1 -

E
....I

50

0.2

60

~600

o

~ 4OO~----~------~~~~~--~r-----~

!:i

~ 300~-----r--~~~~~-r----~r_----~

700

.:!:
....I

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500

(!l

en

!:i
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if

400
300

w
~ 200

~ 200 ~----....".~~
if

~ .....

I I

0.4

0.6

if

i'

-r--

0.8
1.0
1.2
10. OUTPUT CURRENT (A)

"'

\\

\\
\\
\ r\

--

1.4

1.6

.~~d=2.5m~
-

0.52
0.68
10. OUTPUT CURRENT (A)

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

10-20

-

100
0.36

100

I

~=83mH--

\\.

'-load = 0.1 mH"'-.l

40
60
80
LLOAD. LOAD INDUCTANCE (mH)

-

Figure 16. Output Current versus
Open False Fault Time

.. 600

500~-----r----~~----~~£-~~--~

J.

External Clamp Needed

Safe Operating Region

~

I"..

20
30
40
+VS. SUPPLY VOLTAGE (VI

'1

~ 0.2
:;;

Figure 15. Load Inductance versus
Open False Fault Time
700r------.-----,r------.-----,------,

~

\

~

I

Emax= 60 mJ

0.84

1.0

MC3391
TECHNICAL DISCUSSION
Introduction
The MC3391 is a low side protected switch incorporating
many features making it ideal for use in harsh automotive
applications. The protection circuitry of the MC3391 protects
not only itself but also the associated load from destructive
high voltage transients attributed to load and field dump, as
well as, reverse and double battery conditions found in
automotive applications. The MC3391 is unique in that the
protection circuitry is internal and does not require additional
external protection components for its operation. This makes
the device very cost effective in that its application utilizes few
external components, thus reducing cost and space
requirements needed for the system. The MC3391 is
extremely effective when used to drive solenoids, as well as,
incandescent lamp loads. The following description of the
device's operation is in reference to the functional blocks of the
Representative Block Diagram shown in Figure 1.
CMOS Input
The input of the MC3391 is CMOS compatible. Input control
performs as true logic in that when the input (Vin) is less than
1.0 V, the MC3391 switch is in a high impedance or OFF state
and when Yin is greater than 4.0 V the MC3391 is in a low
impedance or ON state. The switching threshold of the input
is approximately 2.0 V and is graphed in Figure 7. With the
input at 4.0 V, the input sink current will be approximately
250 IlA. In the ON state, the internal protection circuitry is
activated and all of the protection features are available for
use. In the OFF state, however, it is importantto note that none
of the protection features are available, with the exception of
the internal inductive load clamp. The input pin is afforded a
minimum of 2000 V ESD protection (Human Body Model) by
virtue of the 7.2 V zener diode.
Over Temperature Shutdown
Internal Thermal Shutdown Circuitry is provided to protect
the MC3391 in the event the Operating Junction Temperature
(TJ) exceeds 150°C. Typically, Thermal Shutdown will occur at
160° to 170°C. The Thermal Shutdown sense element is
embedded within the output PNP (05) so as to afford very fast
thermal coupling of 05 to the sense element. Any rise in
temperature due to the ambient is translated directly to 05 and
the sense element. If the junction temperature rises
excessively above 150°C, the Thermal Shutdown circuit will
turn ON, quickly pulling the gate of 02 to ground, which pulls
the base of 05 to ground, turning it OFF. In addition, the
Thermal Shutdown circuit simultaneously turns 06 ON and
with a suitable pull-up resistor at the Fault pin reports the
presence of a fault (logic low). The output PN P will remain OFF
until the junction temperature decreases to within the
operating range at which time Thermal Shutdown turns OFF,
ceasing to hold the gate of 02 low, turning 05 back ON. This
process will repeat as long as the thermal over load exists.
This mode of operation is a nondestructive safety feature of
the device and will real time correct itself when the cause of
over temperature is removed. A continued over temperature
condition will thermally Pulse Width Modulate (PWM) the
output and Fault and may be incorrectly interpreted as an

oscillating load if one does not consider the simultaneous
performance of the Fault pin.
Current Limit
The MC3391 protects itself against Vout to +VS hard shorts
as well as any over current conditions by reducing the
magnitllde of output current (10) to that of the short circuit
current limit value (lSC). When the output current monitored by
03 tries to exceed ISC, the Current Limitcircuit lowers the gate
voltage of 02, lowering the base of 05, causing the load
current through 05 to diminish. Simultaneously, when the load
current exceeds ISC, 06 will turn ON reporting a fault condition.
If the output current is allowed to remain excessively high for
the degree of heat sinking incorporated, and the junction
temperature of the device is allowed to heat beyond 150°C,
the Thermal Shutdown circuit will activate and the output will
thermally PWM. Again, these modes of operation are safety
features of the MC3391 and are not destructive.
Overvoltage Detect
This circuitry protects the MC3391 from Vout voltages in
excess of 16 V by lowering the output current to a
nondestructive value. With increasingVoutvoltage (16 V < Vout
< 45 V) the load current is reduced to below that of ISC and
produces a fold back current effect. As Vout increases in
excess of 16 V, the output current decreases linearly until Vout
exceeds 45 V. With an infinite heatsink and Vout > 45 V, 10 will
be less than 100 mAo For the other extreme, no heatsink and
You!> 45 V, 10 can be expected to be less than about 400 mAo
This behavior of 10 in relation to Vout is shown in Figure 13.
For the infinite heatsink case, the output current initially
increases with increased voltage until Vout exceeds 16 V,
thereafter the behavior is expressed as,
10 = ISC [1-(Vout -16 V) 130 VI·
Beyond 45 V, 10 is limited to less than 100 mA. Anytime the
Overvoltage Detect circuit is activated, the gate of 06 is pulled
low causing 06 to turn ON to report the fault at the Fault pin.
Inductive Load Clamp
The MC3391 has an internal inductive load clamp for
protection against flyback voltages imposed on the output pin
in excess of 70 V. The incorporated zener clamp can quickly
dissipate up to 60 milli-Joules of inductive flyback energy.
Figure 14 shows the maximum inductive load versus load
currentthatthe clamp can handle safely. As an example (using
Figure 14), if operating the MC3391 to drive a 0.33 H inductor,
the maximum load current should be adjusted to 600 mA or
less. If the load current is too high for the inductor used, some
series resistance can be added to the load to limit the current.
If this is not possible, an external clamp must be used to
facilitate handling the higher energy. When using an external
clamp, the external clamp voltage must be less than 60 V so
as to override the internal clamp. The output clamp offers
protection for the output when the MC3391 is in the OFF state.
During the ON state, other protection features (Overvoltage,
Current, and Temperature) are available to protect the output.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
10-21

MC3391
Open Load Detect
This protection feature will set Fault logic low whenever 10,
monitored by 04, is less than 200 mAo When driving inductors,
voltage leads the current buildup and as a result a false Fault
will be reported during initial turn-on until the load current
attains at least 200 mAo The duration of the inductive false
Fault (tff) will be affected by the inductance of the load
(Figure 15) and also by the value of 10 (Figure 16). The data
for these graphs was taken in a laboratory setup in which each
inductive load was connected in series with a 10 n power
resistor to VS. The input was a 1.0 kHz, 5.0 V p-p square wave
with a 75% high duty cycle.
When driving incandescent lamp loads, in-rush current will
cause a false Faultfor the duration the in-rush current exceeds
ISC. When 200 mA < 10 < ISC, the false Fault will correct itself.
The timing of the false Fault can be seen in the timing diagram
of Figure 2.
During lab characterization it was noted the Fault output will
operate with Vs voltages below 4.0 V but fails to allow full
pull-up to the pull-up Voltage. This is due to insufficient internal
current available to fully turn 06 off. This is not thought to be
a problem since almost all applications use Vs voltages
greater than 4.0 V.

resistor to a +5.0 V supply is satisfactory. The Fault pin is
afforded a minimum of 2000 V ESD protection (Human Body
Model) by virtue of the 7.2 V zener diode. The Fault will report
a fault (logic low state) whenever the MC3391 experiences a
fault condition. Conditions producing a fault are: 10 < 200 mA
(open load); 10> 1.3 A (overcurrentlshorted load); TJ> 150°C
(over temperature); and Vout > 16 V (overvoltage).
If the device goes into Thermal Shutdown, caused by
environmental overheating (not resulting from another fault
condition), the Fault and Vout will thermally PWM as the
MC3391 repeatedly heats to shut off, cools, and again turns
on. If a current limit fault causes the device to go into Thermal
Shutdown, the output will oscillate while the Fault remains
pulled low. There is no designed-in thermal hysteresis to
control the PWM effect and this fault mode of operation is
not destructive.
Fast Turn-Off
This circuitry enhances the MC3391 turn-off performance.
Whenever Vin goes to a logic low state, Vout is held in an OFF
state for approximately 15 118. During fast turn-off, less than
30 mA of current is allowed to flow producing an abrupt
turn-off. This turn-off characteristic can be seen in Figure 12,
a photograph of the typical turn-off waveform.

Fault Logic
The Fault is comprised of an internal open drain FET
requiring an external pull-up resistor. Typically, a 5.0 k pull-up

APPLICATIONS
Solenoid Driver
The MC3391 can be used to drive a variety of solenoid
applications similar to that of Figure 17. For example; driving
a solenoid having an inductance of 73.8 mH and a resistance
of 95 n from a 12 V supply will cause 240 mA of sink current
to flow with the MC3391 in the ON state. The resulting current

value is within the normal load current operating region and will
not produce a fault. Load current is paramount in any design
using the MC3391 and must be less than ISC for acceptable
operation. If the load current is greater than ISC, a current limit
fault state will exist. Operation in this state is not destructive as

Figure 17. Solenoid Driver

fiP
1-

VinicMOSlnp;- -

+

5.0V

-=

I_
II
I
II

-=

-;:; -

-

-

-

-

-

-

-,

Turnoff

VOu!

-=

Detect

I

MC3391

L~ _________ ~-=-~
Gnd

Solenoid

Overvoltage

.£.
MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
10-22

Fault

+
.=.. 5.0V

l

MC3391
the device will turn off if the Junction Temperature (TJ) rises
above 150°C. When the Junction Temperature cools below
150°C the device will again turn-on, with a repeat of the cycle.
If the solenoid resistance is exceedingly large so as to cause
little load current (less than 200 mAl to flow when ON, an open
load fault state will exist. Careful design to acceptable load
current limits should be insured for satisfactory operation of an
application.
Instrument Panel Lamp Dimmer Control
The MC3391 can be used to control the dimming function
associated with instrument panel lamps. The brightness of
incandescent lamps can be varied by Pulse Width Modulating
the input of the MC3391. The modulating signal for the
MC3391 can be obtained directly from a microprocessor or, as
in Figure 18, from an MC1455 timer. The MC1455 timer is

configured as a free-running clock having both frequency and
duty cycle control. The typical timer frequency is
approximately 80 Hz when the frequency potentiometer is
adjusted to 1.0 k. This frequency was chosen so as to avoid
any perceptible lamp flicker. The duty cycle potentiometer
controls the duty cycle over a range of approximately 3% to
97%; when at 3% duty cycle, the lamps are essentially off;
when at 97% duty cycle, the lamps are essentially full lit. Six
incandescent lamps are shown in this application, drawing
720 mA total current. Similar applications can be used to drive
a variety of lamp loads. The total load current is the primary
factor of consideration when driving lamp loads. The total
value of 10 must be less than ISC.
Another convenient aspect of this application is the
LED. The LED can be used to denote the existence of a
system fault (overvoltage, open load, current limiting, or
thermal shutdown).

Figure 18. Instrument Panel Lamp Dimmer Control

r-~------------,+

l-

1.Ok

5.0V

Frequency

I
I
I
I
I
I
I

Instrument
Panel Lamps

J-

+

~

I

L_P=: _________ .:.:J
Gnd

r

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
10-23

5.0V

MOTOROLA

MC3392

SEMICONDUCTOR-----TECHNICAL DATA

Advance Information
Low Side Protected Switch

LOW SIDE
PROTECTED SWITCH

The MC3392 is a low side protected switch designed for use in harsh
automotive applications which require the capability of handling high voltages
attributed to load and field dump transients, in addition to reverse and double
battery conditions. The three terminal TO-220 is intended to replace power
Darlington transistors in new and existing switching applications when taking into
account the CMOS input levels required by the MC3392. It offers improved
functionality and ruggedness over power Darlingtons while retaining the same
package and pin configuration, and can be used as a replacement in many
applications using the industry standard TIP100/101 NPN power Darlington
transistor.
Thefive-terminal TO-220 has the added feature of having a Fault output (active
low) which will indicate the existence of an over temperature, over-voltage or
current limit condition, including an output short to ground.
When driving a moderate load, the MC3392 performs as an extremely high
gain, low saturation Darlington transistor having CMOS input levels. The primary
advantage of the MC3392 over a Darlington transistor is the additional protection
afforded the device and load when driving difficult or faulty loads. This device
incorporates unique internal current limit and thermal protection circuitry to
safeguard itself and the associated load from catastrophic failure.
The MC3392 is available in a three and five-lead TO-220 package; the
five-lead having the added diagnostic feature. The full featured MC3392 is also
available in a 16 pin wide body SOIC plastic power package.
• Designed for Automotive Applications
• Can Be Used as a Replacement for TIP1 00/1 01 NPN Power Darlingtons
• Drives Inductive Loads without External Clamp Circuitry
• Withstands Negative and Positive Transient Voltages
• Low ON Voltage
• CMOS Logic Compatible Input
• Over Current, Overvoltage, and Thermal Protection
• Extended Operating Temperature Range
• Fault Output

SILICON MONOLITHIC
INTEGRATED CIRCUIT

Pin 1. Input
2. Output
3. Ground
(Heatsink surface
connected to Pin 3)
TSUFFIX
PLASTIC PACKAGE
CASE 221A
(TO-220)

T-l SUFFIX
PLASTIC PACKAGE
CASE 3140
(TO-220)

Simplified Block Diagram

I--....--..--------

200

lin
TA=25°C

....I

a:
t-

150

z

0

(;I

t::>
a..
~

<"

-=
t-

100
50

.5

1.0

~

~

w

a:
a:

g.
U
VI

2.0
3.0
Yin. INPUT VOLTAGE M

3.5
3.0

Z

2.5

::>

lin
TA= -40°C

(;I

0

.---

lin
TA= 125°C

1~

~1

8!

300
250

I
I

I I
.1 ... I....J

Figure 3. Input Control Current
versus Input Voltage

~

I

I
I

I Ir----i

lrT1J

~

tw

I

I

c:s~

z

I

---t---- -

II
II

If

I

I
I
I
I

-I--I-t--t---t----- ----1--1

-+-1---+----+-

10

Faull t

--t-t- I I

II

<16V-

I
I
I
I

(;I

w

~

5

1=
::>
0

..:.

4.0

5.0

2.0

,

1.5
1.0
0.5

o

-50

./
o

50
100
150
TA. AMBIENT TEMPERATURE (OC)

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

10.. 27

II

+VS=28V

200

MC3392
Figure 6. Output On Voltage
versus Temperature

Figure 5. Output Short Circuit Current
versus Temperature

g

1.6

~

1.5

a:

1.4

v

B

5

1.4

/

~

C3

b:

1.3

o

ffi
!3

~
o

lil

1.2
1.1

/

1.0
-50

/

2:

~
~

§;

5

+VS= 14 V
RL=O

Yin = 4.0V

~ 1.0

o

.} 0.9

o
50
100
TA. OPERATING AMBIENT TEMPERATURE (oG)

O.B
-50

150

w

0-

::;;

VIH ...

:5
u

VIL ..../'

505

1.0

o.

+VS=5.0V -

0

o

-50

50

100

71
70

~ 69

-93

!:§ -94

§;

'"enw
a:

~
a:

-95
-96
- 97
- 9B

a:
> -99

'"

-50

,

./

6B
- 50

150

V

10 = 100 mA

/

o

50

150

100

TA. OPERATING AMBIENT TEMPERATURE (oG)

Figure 10. Fault Output Saturation
versus Sink Current

Figure 9. Reverse Breakdown Voltage
versus Temperature
2.5
Transient Breakdown
Pulse Width = 1.0 ms

"" '-

;'

/

72

u

-I

C!l

~

./

!:§ 73

3.0

w

150

",

74

TA. OPERATING AMBIENT TEMPERATURE (oG)

a:

o
50
100
TA. OPERATING AMBIENTTEMPERATURE (oG)

§;

..J

~

10 =400 mA

C!l

4.0

'$'

2:

r--

75

2:

0-

:j

-- -

Figure 8. Output Clamp Voltage
versus Temperature

5.0

§; 2.0
!;
~

10 = BOO mA

./

~ 1.1

:I:
C!l

~
C!l
!:§

/'
V

C!l

!:§ 1.2

Figure 7. Input Voltage
versus Temperature

2:

.",...,.

1.3

w

Yin = 5.0V Yin =5.0V Yin = 5.0V
TA= 125°C TA=25°C TA= -40°C

2:

z 2.0

0

~

=>
!;;: 1.5
en
=>
0- 1.0
=>

...
...

~

c:

10=20mA

WO.5
(if
0

>

o
50
100
TA. OPERATING AMBIENTTEMPERATURE (0C)

150

2.0

4.0
6.0
B.O
ISink. SINK GURRENT (mA)

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
10-28

10

12

MC3392
Figure 11. Turn-On Waveform

Figure 12. Turn-Oft Waveform

10

Vou!

Figure 13. Output Current versus
Supply Voltage

Figure 14. Maximum Load Inductance
versus Output Current

1.5

<;::- t.25

:z
w
a:

!§ 1.0
(.)

5

0.5

rr

1/

~ 0.75

o

6

0.5

~

~

o
o

10

-

is
(.)

'""""
Heatsi~

~

~ ........

I\,

20
30
40
+VS, SUPPLY VOLTAGE M

~

50

0.3

"-

0.2

i

0.1 I-- Safe Operating Region

~

60

'1

9

:::;;
=>
:::;;

~

Emax =60 mJ

\

:z

5

I

\

~
~ 0.4

~Heatsink

InfinRe

0.25

Vin =4.0V
RL=O
TA=25°C

...J

0
0.2

I

r

0.4

0.6

J

-

External Clamp Needed

~

I

-r--

0.8
1.0
1.2
10. OUTPUT CURRENT (A)

--

1.4

1.6

TECHNICAL DISCUSSION
Introduction
The MC3392 is a low side protected switch incorporating
many features making it ideal for use in harsh automotive
applications. The protection circuitry of the MC3392 protects
not only itself but also the associated load from destructive
voltage transients attributed to load and field dump, as well as,
reverse and double battery conditions found in automotive
applications. The MC3392 is unique in that the protection
circuitry is internal and does not require additional external
protection components for its operation. This makes the
device very cost effective in that its application utilizes few
external components, thus reducing cost and space requirements needed for the system. The MC3392 is extremely effective when used to drive solenoids, as well as, incandescent
lamp loads. The following description of the device's operation
is in reference to the functional blocks of the Representative
Block Diagram shown in Figure 1.

CMOS Input
The input of the MC3392 is CMOS compatible. Input control
performs as true logic in that when the input (Vin) is less than
1.0 V, the MC3392 switch is in a high impedance or OFF state
and when Vin is greater than 4.0 V the MC3392 is in a low
impedance or ON state. The switching threshold of the input
is approximately 2.0 V and is graphed in Figure 7. With the
input at 4.0 V, the input sink current will be approximately
250 IlA. In the ON state, the internal protection circuitry is
activated and all of the protection features are available for
use. In the OFF state, however, it is importantto note that none
of the protection features are available, with the exception of
the internal inductive load clamp. The input pin is afforded a
minimum of 2000 V ESD protection (Human Body Model) by
virtue of the 7.2 V zener diode.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

10-29

MC3392
Over Temperature Shutdown
Internal Thermal Shutdown Circuitry is provided to protect
the MC3392 in the event the Operating Junction Temperature
(TJ) exceeds 150°C. Typically, Thermal Shutdown will occur at
160° to 170°C. The Thermal Shutdown sense element is embedded within the output PNP (04) so as to afford very fast
thermal coupling of 04 to the sense element. Any rise in temperature due to the ambient is translated directly to 04 and the
sense element. II the junction temperature rises excessively
above 150°C, the Thermal Shutdown circuit will turn ON
quickly pulling the gate of 02 to ground, which pulls the bas~
of 04 to ground, turning it OFF. In addition, the Thermal Shutdown circuit simultaneously turns 05 ON and with a suitable
pull-up resistor at the Fault pin reports the presence of a fault
(logic low). The output PNP will remain OFF until the junction
t~mperature decreases to within the operating range at which
time Thermal Shutdown turns OFF, ceasing to hold the gate of
02 low, turning 04 back ON. This process will repeat as long
as the thermal over load exists. This mode of operation is a
nondestructive safety feature of the device and will real time
correct itself when the cause of over temperature is removed.
A continued over temperature condition will thermally Pulse
Width Modulate (PWM) the output and Fault and may be incorrectly interpreted as an oscillating load if one does not consider the simultaneous performance of the Fault pin.
Current Limit
The MC3392 protects itself against Vout to +VS hard
shorts as well as any over current conditions by reducing
the magnitude of output current (10) to that of the short
circuit current limit value (lSC). When the output current
monitored by 03 tries to exceed ISC, the Current Limit circuit
lowers the gate voltage of 02, lowering the base of 04
causing the load current through 04 to diminish. Simulta:
neously, when the load current exceeds ISC, 05 will turn ON
reporting a fault condition. If the output current is allowed to
remain excessively high for the degree of heat sinking incorporated, and the junction temperature of the device is allowed to heat beyond 150°C, the Thermal Shutdown circuit
will activate and the output will thermally PWM. Again, these
modes of operation are safety features of the MC3392 and
are not destructive.
Overvoltage Detect
This circuitry protects the MC3392 from Vout voltages in
excess of 16 V by lowering the output current to a nondestructive value. With increasing Vout voltage (16 V < Vout< 45 V) the
load current is reduced to below that of ISC and produces a fold
back current effect. As Vout increases in excess of 16 V, the
output current decreases linearly until Vout exceeds 45 V.
With an infinite heatsinkand Vout> 45 V, 10 will be less than 100
mAo Forthe other extreme, no heatsink and Vout > 45 V, 10 can
be expected to be less than about 400 mAo This behavior of
10 in relation to Vout is shown in Figure 13.

. For the in~init.e heatsink case, the output current initially
Increases with Increased voltage until Vout exceeds 16 V,
thereafter the behavior is expressed as,
10 = ISC [1-(Vout -16 V) 130 V]
Beyond 45 V, 10 is limited to less than 100 mAo Anytime the
Overvoltage Detect circuit is activated, the gate of 05 is pulled
low causing 05 to turn ON to report the fault at the Fault pin.
Inductive Load Clamp
The MC3392 has an internal inductive load clamp for protection against flyback voltages imposed on the output pin in
e~c~ss of 70 V. The incorporated zener clamp can quickly
d~sslpate up to 60 milli-Joules of inductive flyback energy.
Figure 14 shows the maximum inductive load versus load
c~rrent that.the cla~p can handle safely. As an example (using
Figure 14), If operating the MC3392 to drive a 0.33 H inductor,
the maximum load current should be adjusted to 600 mA or
less. If the load current is too high for the inductor used some
series resistance can be added to the load to limit the c~rrent.
If this is not possible, an external clamp must be used to facilitate handling the higher energy. When using an external
clamp, the external clamp voltage must be less than 60 V so
as to override the internal clamp. The output clamp offers
protection for the output when the MC3392 is in the OFF state.
During the ON state, other protection features (Overvoltage,
Current, and Temperature) are available to protect the output.
Fault Logic
. The Fault is comprised of an internal open drain FET requirIng. an external pull-up resistor. Typically, a 5.0 k pull-up
resistor to a +5.0 V supply is satisfactory. The Fault pin is
afforded a minimum of 2000 V ESD protection (Human Body
Model) by virtue of the 7.2 V zener diode. The Fault will report
a fault (logic low state) whenever the MC3392 experiences a
fault condition. Conditions producing a fault are: 10 > 1.3 A
(over currenVshorted load); TJ > 150°C (over temperature);
and Vout > 16 V (overvoltage).
II. the device goes into Thermal Shutdown, caused by
enVIronmental overheating (not resulting from another fault
condition), the Fault and Vout will thermally PWM as the
MC3392 repeatedly heats to shut off, cools, and again turns
on. II a current limit fault causes the device to go into Thermal Shutdown, the output will oscillate while the Fault re~ains pulled low. There is no designed-in thermal hystereSIS to control the PWM effect and this fault mode of
operation is not destructive.
Fast Turn-Off
This circuitry enhances the MC3392 turn-off performance.
Whenever Vin'goes to a logic low state, Vout is held in an OFF
state for approximately 15 lIS. During fast turn-off, less than
30 mA of current is allowed to flow producing an abrupt turnoff. This turn-off characteristic can be seen in Figure 12, a
photograph of the typical turn-off waveform.

MOTOROLA LlNEARIINTERFACE ICs DEVICE DATA
10-30

MC3392
APPLICATIONS INFORMATION
Solenoid Driver
The MC3392 can be used to drive a variety of solenoid
applications similar to that of Figure 15. For example; driving
a solenoid having an inductance of 73.8 mH and a resistance
of 95 from a 12 V supply will cause 240 mA of sink current
to flow with the MC3392 in the ON state. The resulting current
value is within the normal load current operating region and
will not produce a fault. Load current is paramount in any
design using the MC3392 and must be less than ISC for

acceptable operation. If the load current is greater than ISC, a
current limit fault state will exist. Operation in this state is not
destructive as the device will turn off if the Junction Temperature (TJ) rises above 150°C. When the Junction Temperature
cools below 150°C the device will again turn-on, with a repeat
of the cycle. Careful design to acceptable load current limits
should be insured for satisfactory operation of an application.

n

Figure 15. Solenoid Driver

fift
i-

VinIcMOSlnpu-t- - - - - : - -

-

-

5.0V

-=

-

-

Turnoff

-

-,

I
I
I
I
I
I Fault
9,.-=-~
VOu!

Over
Voltage
Oetect

...J..

+

-

I - -=
II
I
II MC3392

L_G _________
Gnd.5:-

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
10-31

Solenoid

+

-=-

-l-

5.0V

MC3392
Instrument Panel Lamp Dimmer Control
The MC3392 can be used to control the dimming function
associated with instrument panel lamps. The brightness of
incandescent lamps can be varied by Pulse Width Modulating
the input of the MC3392. The modulating signal for the
MC3392 can be obtained directly from a microprocessor or, as
in Figure 16, from an MC1455 timer. The MC1455 timer is
configured as a free-running clock having both frequency and
duty cycle control. The typical timer frequency is
approximately 80 Hz when the frequency potentiometer is
adjusted to 1.0 k. This frequency was chosen so as to avoid
any perceptible lamp flicker. The duty cycle potentiometer

controls the duty cycle over a range of approximately 3.0% to
97%; When at 3.0% duty cycle, the lamps are essentially off;
When at 97% duty cycle, the lamps are essentially full lit. Six
incandescent lamps are shown in this application drawing 720
rnA total current. Similar applications can be used to drive a
variety of lamp loads. The total load current is the primary
factor of consideration when driving lamp loads. The total
value of 10 must be less than ISC.
Another convenient aspect of this application is the LED.
The LED can be used to denote the existence of a system fault
(overvoltage, current limiting, or thermal shutdown).

Figure 16. Instrument Panel Lamp Dimmer Control

r-~------------,+

1.0k

-=- 5.0V

-t

Frequency

Over
Voltage
Detect

I
I
I
I
I
I
I

+

~

I

L_I1- _________ -=-:J
GndY

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
10-32

-=- 5.0V

-t

MOTOROLA

MC3399

SEMICONDUCTOR-----TECHNICAL DATA

Automotive High Side Driver Switch
The MC3399T is a High Side Driver Switch that is designed to drive loads from
the positive side of the power supply. The output is controlled by a TIL compatible
Enable pin. In the ON state, the device exhibits very low saturation voltages for
load currents in excess of 750 mAo The device also protects the load from positive
or negative going high voltage transients by becoming an open circuit and
isolating the transient for its duration from the load.
The MC3399T is fabricated on a power BIMOS process which combines the
best features of Bipolar and MaS technologies. The mixed technology provides
higher gain PNP output devices and results in Power Integrated Circuits with
reduced quiescent current.
The device operates over a wide power supply voltage range and can
withstand voltage transients (positive or negative) of ± 100 V. A rugged PNP
output stage along with active clamp circuitry, current limit and thermal shutdown
permits driving of all types of loads including inductive. The MC3399T is specified
over a wide junction temperature of -40° to + 125°C and is ideally suited for
industrial and automotive applications where harsh environments exist.
• Low Switch Voltage Drop

AUTOMOTIVE
HIGH SIDE DRIVER SWITCH
SILICON MONOLITHIC
INTEGRATED CIRCUIT

TSUFFIX
PLASTIC PACKAGE
CASE314D
Pin I.
2.
3.
4.
5.

Ignition
Output
Output
Ground
Input

• Load Currents in Excess of 750 mA

Heatsink surface
connected to Pin 2

Block Diagram

• Low Quiescent Current

MC3399T

• Transient Protection Up to ± 100 V

r

• TIL Compatible Enable Input
• On-Chip Current Limit and Thermal Shutdown Circuitry

Ignition I

I

-v

~.
Output
~T -v

:J

I I IS

;:::LL
0
A

In:J

Power
Supply

Gnd

D

'--T-

Timing Diagram

100V -

MAXIMUM RATINGS
Rating
Ignition Input Voltage-Continuous
Ignition Input Voltage-Transient
t = 100 ms
t= 1.0ms

Symbol

Value

Unit

VIGN

+25
-12

Vdc

VIGN

V
±60
±IOO

Yin

-0.3 to + 7.0

V

Output Current

10

Internally
Limited

A

PD
1I9JA
9JA
PD
9JA

2.0
16
65
25
200
5.0

TJ

-40 to +125

Operating Junction Temperature Range
Storage Temperature Range

1/9JA

Tstg

-65 to +150

12V=--

I I

W
mW/oC
°CIW

W
mW/oC
°CIW

°C
°C

-IOOV -

I
~

I

}.,

~

I I
1.0ms

~

"'}

I~

12VOV -

L..

I
I--

IF

~

5.0VJ
OV-

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
10-33

t

ov----J

Input Voltage

Power Dissipation and Thermal Characteristics
TA = + 25°C
Derate above TA = + 25°C
Thermal Resistance Junction to Ambient
TC = + 25°C
Derate above TC = + 25°C
Thermal Resistance Junction to Case

"'V-

~T~'~
1.0 ms

Input

Output
(load Voltage)

~

1

MC3399
ELECTRICAL CHARACTERICISTICS (VIGN

=+12 V, IL =150 mA, -40°C :s; TJ =+125°C, V Input ="1", unless otherwise noted.)'
Symbol

MIn

Typ

Max

UnIt

Operating Voltage

VIGN(min)

4.5

-

-

V

Switch Voltage Drop (Saturation)
VIGN =4.5 V 10 =150 mA TJ =25°C
10 =200 mA TJ =-40°C
10 =125 mA TJ =125°C
VIGN = 12 V 10 =425 mA TJ =25°C
10 =550 mA TJ =-40°C
VIGN = 16 V 10 =375 mA TJ =125°C

VIGN-VO

-

0.2
0.3
0.3
0.3
0.3
0.4

0.5
0.5
0.5
0.7
0.7
0.7

Quiescent Current
VIGN = 12 V 10 =150 mA TJ =25°C
10 =550 mA TJ =-40°C
10 =300 mA TJ =125°C

IGND

-

12
25
10

50
100
50

ISC

-

1.6

2.5

A

ILeak

-

10

150

IJA

2.0

-

-

Characteristics

Output Current Limit (VO = 0 V)
Output Leakage Current (VIGN

=12 V, Input ="0")

Input Voltage
High Logic State
Low Logic State

VIH
VIL

Input Current
High Logic State (VIH =5.5 V)
Low Logic State (VIL =0.4 V)

IIH
IlL

-

V

mA

V

0.8

Output Tum-On Delay lime
Input ="0" -+ "1", TJ =+25°C (Figures 1 and 2)

tDLY(on)

Output Tum-OIl Delay lime
Input ="1" -+ "0", TJ =+25°C (Figures 1 and 2)

tDLY(off)

-

5.0

-

lIS

Over Voltage Shutdown Threshold

Vin(OV)

26

31

36

V

tDLY

-

2.0

-

lIS

tRCVY

-

5.0

-

lIS

Output Turn-OIl Delay lime (TJ =+ 25°C) to Overvoltage Condition,
Vin stepped from 12 V to 40 V, V:s; o.g Vo (Figures 1 and 2)
Output Recovery Delay lime (TJ =+ 25°C)
VIGN stepped from 40 V to 12 V, V 2: 0.9 Vo (Figures 1 and 2)
'Typical Values Represent Characteristics of Operation at TJ =+ 25°C.

Figure 1. Transient Response Test Circuit

50n

NOTE:
"Depending on Load Current and Transient Duration, an Output Capacitor (CO) of
sufficient value may be used to hold up Output VoRage during the Transient, and
absorb Tum-off Delay Voltage Overshoot.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

10-34

120
20
50

-

IJA

-

lIS

MC3399
Figure 2. Response Time Diagram

n

40V-

Ignition
12V-

I
I
I
I

Inpul
5.0VOV31V-

I
I
I
I
I
I
I
I

Oulpul
Vo 12VOV-

r-I I

I I
I I
I
I
I
I
1+-+1

-.j
IOLY(OV)

IRCVY

Figure 3. Switch Voltage Drop
versus Load Current
800

,.. ..."
o

./

.,.,

./

,.. V

i-"""

80

200

II
VIGN=+24V
TJ = +25°C
Vin='I"

f-f--

V

1
!z
w

60

u
I:z
w
u

40

5

20

ffi

--

0

_0
400
600
It. LOAD CURRENT (mA)

800

r-f---

a:
a:

::>

V

o

toLY(on)

Figure 4. Quiescent Current
versus Load Current

II
VIGN = +24 V
TJ = +25°C
Vin='I"

toLT(off)

1000

o !-'"
o

200

400
600
It. LOAD CURRENT (mA)

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
10-35

800

V
1000

MC3484S2-2
MC3484S4-2

MOTOROLA

SEMICONDUCTOR-----TECHNICAL DATA

SOLENOID DRIVER

2.4A-S2
4.0A-S4

Integrated Solenoid Driver
The MC3484 is an integrated monolithic solenoid driver. Its typical function
is to apply full battery voltage to fuel injector(s) for rapid current rise, in order to
produce positive injector opening. When load current reaches a preset level
(4.0 A in MC3484S4 or 2.4 A in MC3484S2) the injector driver reduces the load
current by a 4-to-1 ratio and operates as a constant current supply. This
condition holds the injector open and reduces system dissipation. Other
solenoid or relay applications could be served by the MC3484. Two high
impedance inputs are provided which permit a variety of control options and can
be driven by TTL or CMOS logic.
• Microprocessor Compatible Inputs
• On-Chip Power Device
MC3484S2-2 2.4 A Peak 0.6 A Sustain
MC3484S4-2 4.0 A Peak 1.0 A Sustain
• Low Thermal Resistance to Grounded Tab-RaJC =2.5°C/W
• Overvoltage Protection Cutoff
• Low Saturation Voltage: VCE(sat) = 1.6 V Typ @ 4.0 A
• Uncompromised Performance - 40° to + 85°C Junction Temperature
• Fully Functional from Vbat = 4.0 V to 24 V
• High VCEO(sus) = 42 V min @ Isus
• Alternate Lead Forms are Available

SSUFFIX
PLASTIC PACKAGE
CASE 314D

PIN CONNECTIONS
Input

I!

Control
Ground

Output

+vcc

(Unformed Package)

ORDERING INFORMATION
Device
MC3484S2-2
MC3484S4-2

Tested Ambient
Temperature Range
-40° to +85°C

Peak
Current
2.4A
4.0A

Figure 1. Typical Application
Single Injector with Overvoltage Protection at 30 V (Vbatl

4000

5
r-----------I
r--r~
20kn

ILoad

I
I

11

OVP
In

1.0kn

I

~

Vref

L--------------

_~

s1

I lout
I
I
I
I
I
I
I

I

VSuppl V
4 Vdc 10 24"Vdc

10
lout (A)

5

4

Yin (V) 0

~;jiTat>t

2

o

lout
1.0mS/DIV

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
10-36

MC3484S2-2, MC3484S4-2
MAXIMUM RATINGS
Rating
Power Supply Voltage (Vbat)
Input (Pin 1)
Control (Pin 2)

Symbol

Value

Vbat

24

Unit
V

Vin
Vcont

-0.3 to +6.0
o to +5.0

V

Internal Regulator (Pin 5)

-

50

mA

Junction Temperature

TJ

150

Operating Temperature (Tab Temperature)

TA

-40 to +105

'c
'c

Storage Temperature

Tstg

-65 to + 150

°C

Thermal Resistance, Junction-to-Case

8JC

2.5

°CIW

ELECTRICAL CHARACTERICISTICS (Vbat = 12 Vdc, TC = -40' to +85°C, test circuit of Figure 2, unless otherwise noted.)
Characteristics
Output Peak Current

S4-2
S2-2

Output Sustaining Current

Symbol

Min

Typ

Max

Unit

Ipk(sense)

3.6
1.7

4.0
2.4

5.2
2.9

A

Isus

0.95
0.50

1.0
0.6

1.3
0.7

A

42

50

-

-

VCEO(sus) @ 2.0 A
Output Voltage in Saturated Mode
S2@1.5A
S4@3.0A

Vout

Internal Regulated Voltage (VCC, Figure 2)

V
V

-

1.2
1.6

-

Vreg

-

7.1

-

V

Input "On" Threshold Voltage

Von

-

1.4

2.0

V

Input "011" Threshold Voltage

Voll

0.7

1.3

-

Input "On" Current
@VI=2.0Vdc
@VI=5.0Vdc

-

V

j.iA

lin

-

50
220
1.5

VI Low

-

Input Turn on Delay

ti

-

0.5

Ipk sense to Is us delay

tp

-

60

-

Control Signal Delay

tt

-

15

-

IlS

Input Turn 011 from Saturated Mode Delay

ts

1.0

Id

0.2

-

IlS

Input Turn 011 from Sustain Mode Delay

-

Output Voltage Rise Time

tv

-

0.4

-

IlS

tf

-

0.3
0.6

-

IlS

Control "On" Threshold Voltage

Vcont

Control "On" Current

lin2

Control Pin Impedance

Output Current Fall Time

2.0A
4.0A

75
10

Figure 2, Test Circuit
,0.
400(1
2.0W

Overvoltage
Control

20k

f

VCC

1.2

RL

5
2
2.0mH

1.0k

MC3484
~

~~~~~p p -

Square
Wave

Ilniector
Load
I

51

Input

Output

4

1
3

0-5.0Vdc

1

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
10-37

~

=

40V/l0W
Zener

V

j.iA
kQ

IlS
IlS

IlS

MC3484S2-2, MC3484S4-2
GENERAL INFORMATION
Inductive actuators such as automotive electronic fuel
injectors, relays, solenoids and hammer drivers can be
powered more efficiently by providing a high current drive until
actuation (pull-in) occurs and then decreasing the drive
current to a level which will sustain actuation. Pull-in and
especially drop-out times of the actuators are also improved.
The fundamental output characteristic of the MC3484
provides a low impedance saturated power switch until the
load current reaches a predetermined high-current level and
then changes to a current source of lower magnitude until the
device is turned off. This output characteristic allows the
inductive load to control its actuation time during turn-on while
minimizing power and stored energy during the sustain period,
thereby promoting a fast turn-off time.

Automotive injectors at present come in two types. The
large throttle body injectors have an impedance of about
2.0 mH and 1.2 n and required the MC3484S4 driver. The
smaller type, popular world-wide, has an impedance of 4.0 mH
and 2.4 n and needs about a 2.0 A pulse for good results.
Some designs are planned which employ two of the smaller
types in parallel. The inductance of an injector is much larger
at low current, decreasing due to armature movement and
core saturation to the values above at rated current.
Operating frequencies range form 5.0 Hz to 250 Hz
depending on the injector location and engine type. Duty cycle
in some designs reaches 80%.

APPLICATIONS INFORMATION
Figure 3. Operating Waveforms
(Max Frequency 250 Hz, Pin 2 Grounded)

The MC3484 is provided with an input pin (Pin 1) which turns
the injector driver "on" and "off." This pin has a nominal trip
level of 1.4 V and an input impedance of 20 kil. It is internally
protected against negative voltages and is compatible with
TTL and most other logic.
There is also a control pin (Pin 2) which may be used as an
overvoltage, load dump, shutdown. When a nominal 1.5 V is
applied to Pin 2, via a 20: 1 voltage divider the driver and circuit
are set in a safe off state at 30 V (Vbat).
Figure 3 shows the operating waveforms for the simplest
mode; Le., with control Pin 2 grounded. When the driver is
turned on, the current ramps up to the peak current sense
level, where some overshoot occurs because of internal delay.
The MC3484 then reduces its outputto Isus. The fall time ofthe
device is very rapid (:;; 1.0 I1S), butthe decay ofthe load current
takes 150 I1S to 220 I1s, while dumping the load energy into the
protection zener clamp. It is essential thatthe zener voltage be
lowerthanthe VCEO(sus), butnotso lowastogreatlystretchthe
load current decay time. Without the zener, the discharge of
the load energy would be totally into the MC3484, which, for
the high current applications could cause the device to fail.
(See SOA, Figure 11.)
Also in Figure 3 is the graphically derived instantaneous
power dissipation of the MC3484. It shows that, for practical
purposes, the worst case dissipation is less than (lsus) (Vbat)
(duty cycle).
Provided in Figures 3 and 4 are definitions of the switching
intervals specified in the Electrical Characteristics. Figure 5
shows that the critical switching parameters stay under control
at elevated temperatures.

Output
Current

Output
Vohage
Vbat-Isus

Ipk
Ipk(sense)
Isus

Vz
vbal
RL

-]J

"3:='F--==.....=---.,.----~~

V5atV~ZPk

Power
Dissipation
VZls~---(Vbat"lsus RLlls~ _ -_ _
Vsat Ipk

Figure 4. Switching Waveforms
(Expanded Time Scale)

.C"
I

Figure 5. Switching Speed
versus Temperature
2.0
15(S2)

Ipk

90%

~

c

1.5

~
en

~

~ 1.0

10%

o

I

~

"

Iv(!~)

0.5

,

..; ~ Is(S4)

~

~

IIt/S4}

.......

1~(S4)

1f(l:i2)

Vz

o

-40

-20

0
20
40 60 80 100
TC, CASE TEMPERATURE (OC)

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
10-38

120 140

MC3484S2-2, MC3484S4-2
TYPICAL CHARACTERISTICS
(Unless otherwise noted, test circuit of Figure 2, Vbat = 12 Vdc, TC = -40' to +85'C, 250 Hz square wave input)

Figure 6. Output Current versus Temperature

g
::>

4.0

f-

0..

a
S0

2.0

I.

Dynamic Ipk

Ipk(sense) (S2)

1
Vbat= 12Vdc
-40

-20

100

1.4

a

1.2

TC=125'C ~ __
TC=25'C

k-:::='

_.

1.0

g

TC~25'C I

en.

~

4.0

/

W

a:
a:

::>

3.0

J

C,)

/ oK:.

f-

::>
0..

f-

2.0

'V

::>

a

'S
0

-

1.0

00

1.0
2.0
lout. OUTPUT CURRENT (A)

8.0

r-

Ipk(sense)

1

8.0

10

~ '7

6.0

~.

U

'0

Ipk (S2)

~

~

§?

3.0

!j
1

z

Isus (S4)

5.0

4.0 V/

w

12
14
16
Vbat (Vdc)

250 Hz

5.0 Hz

Pin 2 (Control Threshold)

1-1

~

20

22

o

4.0

24

Figure 10. Breakdown Voltage
versus Temperature

I

... 250 Hz
6.0

8.0

10

12

14
16
Vbat (Vdc)

High Umit

De~ice

22

24

g

10~

.......

f-

zw 3.0

DC'.

1

C,)

Typical Device
'j

f-

::>
0..

f-

::>

~

LO
0.7
0.5

I'-.

1

f= Bonding Wire LTD

f-- Thermally LTD
'S 0.3 f-- 2nd Breakdown
0
0.2 I - TC = 25'C, TJ(pk)'; 150'C

!

Law Umit. DeVlce
Ipk = 2.0 A
-20

20

lOOI1S

::>

-40

18

10
7.0
5.0

a: 2.0
a:

40

+-=-

Pin 1 (Input Thresholdl
I
I
TC = 25'C

Figure 11. Safe Operating Area

60

-

"-

V

c:::: 2.0

18

4.0

Pin 5 (VCC)

5.0 Hz

1.0 f"""
4.0 6.0

3.0

Figure 9. Operating Voltages

Isus (S2)

o

-

0.6

7.0

Ipk(sense)

-

J..~

~·Ivcc=i.o~

~ 0.2
140

10k (S4)

--

/

VCC=3.0V .....~

~ 0.4

/.

fZ

::;;0'

~ F---

Figure 8. Output Current
versus Supply Voltage
5.0

!....

---

!;;: 0.8

_

1
120

1.6

a

~
::>

Isus (S2)

0
20
40
60
80
TC, CASE TEMPERATURE ('C)


z

Is us (S4)
1.0

1.8 I---

t§

2)-

.1.1

2:
w

~

1

r-

::>
f-

I
I
Ipk(sense) (S4)
T'I

-

3.0

C,)

::>

2.0

Dyna~iC Ipk \S4)

fZ
W

a:
a:

Figure 7. Saturation Voltage

--- r-.l--rTs

5.0

0
20
40
60 80 100
TC. CASE TEMPERATURE (5C)

120

0.1
140

I-

o

I' I
2.0

I

T I II

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

10·39

II

3.04.05.0 7.0 10
20 30 40 50 70 100
Vout, OUTPUT VOLTAGE M

Figure 12. Internal Schematic

s:::

0

d

s::

::0

0

r
»
r

Z

0

ZI

W

6JIV
Pow

3:

3_ Gate Voltage versus Supply Voltage

>

20

C!)

15

w
!;;:

2.0 1--'----=::1_"""'---+-----+---::=---1

8 1.5 J--."c..---j---==-t,""",=---+-",,--,=c..::.-j

IG=O .A

>6 10

r

V

./

~/

'(/7'-.

TA=25°e

IG = 20 flA

fA
5.0

1.0 I---;.,..=-+----+-----j-----I
0.5 ' - - - - - ' - - - - - ' - - - - - ' - - - - - - - '
5.0
10
15
20
25
Vee, SUPPLY VOLTAGE (V)

o

5.0

IG=40~
10

15
20
Vee, SUPPLY VOLTAGE (V)

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

10-43

25

30

MC33091
Figure 5. Gate to Source Voltage
versus Source Voltage

Figure 4. Gate Voltage versus Gate Current
50

.1

45
~

..L"

40

Ambient Temperatures Shown (OC)
VCC=28V
125°C

w

35

!:!i
g

30

CC=14V"\.

25

,"

C!I

~
>f:J

-40° 125°

"lit' VCC=21 V

20 ~=7.0V
15
~
10
125° r-...
5.0

'"'

o
o

25

-40° "-

""'"
12~ :--

~Oo

75

---

~

~

...,40

-

0

-....:

100 125 150 175
IG. GATE CURRENT !IJA)

25°

".....
-' -

5°

~~

"

50

'" '2.

\ 25°'- ~

\.

r"..

......

200

225

~

14
13

!:!i
g

12

9
v,

10r-----~-----+~--~~r---+-----~

~

~

~

~

w

~
!:J

g
~
C!I

TI =125°~

30
25

15
10

o

II

I

TA=-40°C

J.

~
w

TA=-40°C -

0.5

1.0
1.5
2.0
VSRC. SOURCE VOLTAGE M

2.5

Figure 7. Gate Voltage versus Input Control Voltage
40

VCC=14V
Pin 1 (SRC) = Open
TA = 25°C

30

C!I

25

g
~
C!I

20

!:!i

/
I(

>f:J

IJ

o

35

~~

20

I

I
I
,III

9.0

250

~=J5OC

A~

Gate Unloaded

I

TA= 125°C

7.oE=:E:~f:::~:L_-L_J

..J

35

. , - - TA=25°C

II
I'!
II

llr-----~-----t-i----~~--+-----~

~ 8.0

Figure 6. Gate Voltage versus Supply Voltage
40

VCC=14V
FETLoadShOrlCharacterlistiC / '

I

•

15

t

I

>f:J 10
5.0

5.0

10

15

20

25

o

2.0

30

Vee. SUPPLY VOLTAGE M

Figure 8. Input Control Current
versus Input Control Voltage

2.2

2.4
2.6
2.8
Yin. INPUT CONTROL VOLTAGE M

3.0

Figure 9. Squaring Constant "K"
versus Supply Voltage
11.30 r - - - - - - - , r - - - - - - , - - - - - , - - - - - - ,

120

..:; 1.25

/'
VCC= 14 V
TA = 25°C

V

/

/
V

!z

V

j$ 1.20

g,l

8

r-------+-------+--=_=--I-------~

r-------+---::"""'''---+--------I-------~

~ 1.10 r----;;tO'-"+-------+-----::::;;;o..".""""'----~

~~

/"
1.0

1.15

RX=100k
VOS=2.0V

!z

1.05
1.00

r----:;o.....,.,.-1-='''--=:==---+-------~------~

~

0.95

h~----+_------+-------+_------~

(.')

2.0
3.0
4.0
Yin. INPUT CONTROL VOLTAGE M

5.0

6.0

>i 0.90 L-______" -______- ' -______- ' -______- I
5.0
10
15
20
25
VCC. SUPPLY VOLTAGE M

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
10-44

MC33091
Figure 10. Timer Current versus Drain to
Source Voltage Squared

~

ci

.....

Figure 11. Faiill Voltage versus Faiill Sink Current

1000 , - - - - - - , - - - - - - , - - - - - - , - - - - - - - ,
VCC= 14 V
TA = 25°C

1.4

100~---~----4~£--~~---~

aa:

~

1.0 I----+---~---+.~--j---~

~

0.8 1-----t----t--7'~+-----1_=____:_:::-::-__1
TA = 25°C
0.6 t-----t------,rt------::..r-""-----1---__1
TA = -40°C
0.4 t-----b~--:::ii"t=---=....r-=-----1---__1

I Ll~::

10~---~~L-~~----+----~

a:

UJ

::;;
j::

_g

1.2

~

i'a:iJ

I~

1.0

VCC=14V
VT=5.0V

~

>
0.2 ~~~7'"""""-1--1-1--1

O.II:....----...l...------L...-----I..----I
0.1
1.0
10
100
1000
VDS2, DRAIN TO SOURCE VOLTAGE SQUARED (V2)

O~----~------~----~----~------~

o

Figure 12. FET Comparison Gate Response

1.0

2.0
3.0
4.0
IFault, FAULT SINK CURRENT (rnA)

5.0

Figure 13. FET Comparison Gate Response

20,----,----,---,---,---,-----,

30

1 --;:'1=:::::;=1===6;=-1

~ 15~~~~::~~::j:::::~~M~T~P5:0N:0~6
~

~
~

Ciss = 3000 pF
10~-7~~--4-

UJ

!

MTP8NIO
Ciss =500 pF

!C!J 10

200

300

400

VCC = 24 V

(

C!J

~

UJ

/

~ 30
UJ

30

UJ

C!J

a
>

800

Figure 15. MTP25N06 Gate Response

40

~

600

I, TIMEtus)

10

o

V

o

./

/fVCC = 14 V

--

VCc=,'OV

100

200

300

I,TIME(~)

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
10-45

~

400
I,TIME{)!s)

MTP25N06
Ciss = 1000 pF
Inpul = 5.0 V Slep
TA = 25°C
500
600
700

800

..

MC33091
Figure 16. Timer Lower Threshold Voltage
versus Temperature

~

1.0

I

fa!

~

I

0.9

0.7
0.6

::E

F

i

E§

0.5
-50

---

TA= 125°C

§! 0.9

9
o

ili

V

/

I

(!l

J

0.8

F
ffi

:a
w 1.0 I -

I

5.5VSVCCS24V

9

~

Figure 17. Timer Lower Threshold Voltage
versus Supply Voltage

~

!

5.5VSVee S24V
0.8
TA = -40°C

F
ffi

0.7
0.6

TA=25°C

::E

F

150

o
50
100
TA. AMBIENT TEMPERATURE (OC)

~0.5

>

5.0

10

Figure 18. Timer Upper Threshold Voltage
versus Temperature

:a 4.44

fa!

fa!

w

4.42

ffi

~ 4.42 ">

Vee = 7.0 V

--.....

~

I

9

~ 4.40

~

1\

Vee=24V

4.38

~

VCC=l~ r\\

4.36

w

j!: 4.34

o

50

,

\

~ 4.36

150

100
TA. AMBIENT TEMPERATURE (OC)

-50

4.38

~

It
:::>

\

::E

F

>

j!:4.34

>

:a
2.50
w

,.. -

2.25
~ 2.00

>

~ 1.50
~

~

~

1.25
1.00

w

II""

Elenl

1.25

~

1.00

1"0.75
15

150.25

o

0.1

0.2

TA= 125°C
15
20
VCC. SUPPLY VOLTAGE (V)

0.3

0.4 0.5 0.6 0.7
IG. GATE CURRENT (mA)

0.8

0.9

25

TA = -40°C

2.00

L.

~ 1.50

TA= 125°C

0.75

0

"'-..
10

!:J
§! 1.75
~

TA= 25°C

t o.50

>

TA=-55°C

:a 2.25
fa!

,,-

TA=25°C

~

Figure 21. Gate Saturation Voltage
versus Gate Current (Expanded Scale)

TA=-4O°C

fa!

"

5.0

Figure 20. Gate Saturation Voltage
versus Gate Current

~ 1.75

25

w

~ 4.40

F

15
20
Vee. SUPPLY VOLTAGE (V)

Figure 19. Timer Upper Threshold Voltage
versus Supply Voltage

:a 4.44
~
9

1

TA = 85°C

1.0

> 0.50

V

I
TA = 25°C

Ar

1/

-

TA= 125°C

IJI

o W

"

~

~

40
50
00 m
IG. GATE CURRENT (jIA)

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
10-46

00

00

~

MC33091
Figure 22. Gate to Source Voltage
versus External RT Timer Resistor
~

w



w

7.0
6.0

0

a:

:::>

\

4.0

"\.

0

en
0

I-

3.0

Z

...........

""

~ 2.0

..............

..........
RX 150 k

.............

..........

~

100

w
::;;

;:: 10-1
w
en
z
0 10-2
cen
w
a: 10-3
a:

RX=100k

~:;5k-

w

r--

::;;

;:: 10-4
::;;
:::>
::;;

...-

V ...........
V V

V

Z 10-5

~ 1.0

en

>0

-

r---...

.........

0

1rl

VDS(min) = [(VTHRX2IQ) / RTll/2
VTH = 404 V
IQ = 100 IlA

\

5.0

Figure 23. Timer Response
versus VDS(min)Nbat Ratio

B

~

~

--

:E

I

0
100

-------

~

~

~

B

~

1~

~1O-6

_-

Rr. EXTERNAL TIMER RESISTOR (kQ)

0.05

~

-

RrCT = 1.:2.RrCL=O.l

-

l(min/ = -RIfT In[1
0.10

RrCT = 0.01_

I"""

I (VDS\min)Nb1atl2J

0.15 0.20 0.25 0.30 0.35 0040 0045
VDS(min)Nbat. DRAIN TO SOURCE VOLTAGE
TO BATIERY VOLTAGE RATIO

Figure 24. Descriptive Waveform Diagram
Vz' '.

+VCC
(Pin 5)

<30 V

J
.

OV
5.0V

Input~

(Pin 7)

...

OV
• VSRC+14V

Gate
(Pin 4)

OV

VT
(Pin 8)

,-_'_V..:.T:..L_ _ _ _ _ _ OV

,

,

,

~------~--------

Fault
(Pin 6) .

VPU
OV

SRC
(Pin 1)

DRN
(Pin 2)

VSRC
OV

Normal Operation

Shorted FET Load

Normal Operation

MOTOROLA L1NEAR/[NTERFACE ICs DEV[CE DATA

10-47

Overvoltage

0.50

MC33091
FUNCTIONAL DESCRIPTION
Introduction
The MC33091 is designed to drive a wide variety of
N-channel TMOS transistors in high side configured, low
frequency switching applications. The MC33091 has an
internal charge pump to fully enhance the on-state of the
TMOS device. The MC33091 protects the TMOS device from
shorts to ground and provides a Fault output to report the
presence of an over current condition. The few additional
external components required allow tailoring of the
application's protection level. The protection scheme of the
MC33091 uses an externally programmable, nonlinear timer
that disables the TMOS device in the event the drain to source
voltage exceeds a specified value for a specified duration.
Both the value and duration are externally programmable
allowing for ilexibility in applications.
Pin Description
Figure 1 shows a typical application as well as the internal
functional blocks of the MC33091. The discussion to follow
references this figure.
Input (Pin 7): The logic levels of the Input are compatible
with CMOS logic families. The Input enables the protection
and charge pump circuitry. With the Input in a logic low state
the MC33091 draws only leakage current of less than 3.0 ~A
and in this condition the associated TMOS device will be in the
off state. When the Input is in a logic high state, the Gate
voltage (Pin 4) rise is limited to a maximum of 14 V above SRC
(Pin 1), due to an internal clamp diode being used. Under this
condition the TMOS device is enhanced full on.
Fault (Pin 6): The Fault output is comprised of an open
collector NPN transistor capable of sinking at least 500 ~A
when the TMOS gate is disabled due to an over current
condition. When the TMOS device experiences an over
current condition the Fault pin is pulled low.
SRC (Pin 1): The SRC pin senses the TMOS source voltage
and is the input to the VOS buffer used in conjunction with the
ORN pin in monitoring the drain to source voltage developed
across the TMOS device. The purpose of the 1.0 k resistor
connected to this pin is to protect the SRC input from over
voltage as a result of flyback voltage produced when the
TMOS device is used to switch large inductive loads. This
resistor can be eliminated when switching noninductive loads.
DRN (Pin 2): The ORN is used in conjunction with the SRC
pin and together constitute a VOS monitor of the TMOS drain
to source voltage. Feedback from the SRC pin will maintain a
voltage across the resistor, (RX), equal to the VOS voltage
developed across the TMOS device. The series resistor, (RX),
connected between the drain of the TMOS device and ORN of
the MC33091 is used in conjunction with the feedback buffer
and associated PNP transistor to establish a current
proportional to the drain to source voltage, (VOS), of the TMOS
device. This proportional current, acted upon by the current
squaring circuit of the MC33091, is an important part of the
TMOS protection scheme.

VCC (Pin 5): The VCC pin supplies operational powerto the
MC33091. An internal 30 V zener clamp connects to this pin
provide over voltage protection of the MC33091. When the
zener is activated, the MC33091 disables the TMOS device
only for the duration of the overvoltage but the Fault output
(Pin 6) does not change logic states. The Fault pin does not go
to a logic low state during the over voltage duration since this
is not an MC33091 device fault, but an external system fault.
Gate (Pin 4): The Gate pin of the MC33091 is the output of
the internal charge pump which controls the TMOS device.
The charge pump is a voltage tripler and requires no additional
external components for operation. With the Input in a logic low
state the charge pump will be turned off. When the Input is
pulled to a logic high state, with no load fault existing, the
charge pump turns on and pumps the TMOS gate voltage to
at least8.0 V, typically 10Vto 14 V, above VCC overthe supply
voltage range. An internal zener clamp is incorporated so as
to limit the Gate to approximately 14 V above the source so as
to prevent rupture of the TMOS gate.
VT (Pin 8): The Timer Pin (VT) is both an input to the timer
window comparators and an output of the current squaring
circuit. An external resistor (RT) and capacitor (CT) are tied to
this node so as to afford programing the characteristics
necessary for protection of the TMOS device.
Over Current Protection Timer
The MC33091 protection scheme is based on the ability of
the MC33091 to constantly sense the voltage drop developed
across the TMOS device. A low voltage drop is indicative of
normal TMOS "on" operation while a large voltage drop
represents the existence of an over current condition. By
monitoring the TMOS drain to source voltage (VOS) the
MC33091 is able to detect a shorted load and react to disable
the TMOS device. The circuit protection scheme is essentially
based on a timer whose rate is dependent on the magnitude
of VOS. If the drain to source voltage is large (i.e. VOS = VCC),
the timer will disable the gate drive very quickly. If VOS is only
slightly above the normal operating level, the timer will take
much longer to disable the gate drive.
Since the power dissipated in the TMOS device is
proportional to VOS2, low VOS conditions can be tolerated for
a longer time than high VOS conditions. To enhance the
system application the timer time-out of the MC33091 is
inversely proportional to VOS2. This approach maximizes the
TMOS operating range. The timer parameters are completely
user programmable through the use of external components
affording application usage of a wide variety ofTMOS devices.
This is intended to model the generation and dissipation of
heat within the TMOS device.
The external components RX, RT, and CT determine the
timer characteristics. Once enabled, the MC33091 will source
a current, (ISO), from the timer pin that is proportional to VOS2
such that:
ISO = KVOS2
where: K

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
10-48

= 1/(RX210)

(1 )

MC33091
10 is an internal current source parameter of the MC33091
that has a nominal value of 100 ~A and RX is the external
resistor in series with the drain of the TMOS device
that establishes the value of the voltage to current
proportionality constant. Since the parallel combination of RT
and CT appear at the timer pin (VT), the timer pin voltage, VT,
can be written as:

ground resulting in the full battery voltage (Vbat) to appear
directly across the TMOS device. This condition causes
maximum ISO current to be produced by the current squaring
circuit. Under this condition the maximum ISO current
experienced is:

(2)

An expression for the minimum time-out is obtained by
substituting 10 of Equation 6 into Equation 3:

With the Input (Pin 7) in a logic high state and no over current
condition existing, the TMOS device will be in the "on" state.
lithe TMOS device experiences an over current condition, ISO
flowing through RT will increase causing CT to charge up, in
turn causing the timer voltage, (VT), to exceed the threshold,
(VTH), olthe upper comparator. This sets the latch causing the
output of the latch to go high (and the Q output to go low),
in turn causing the TMOS gate and Fault output (Pin 6) to be
pulled low, disabling the TMOS device. Both the current
squaring circuit (ISO) and the charge pump are disabled
whenever the output of the latch goes low. Using Equation
2, the fault time response for an over current condition can be
written as:

a

a

t = -RTCT In(1-VTH/ISORT)

= [(VTHRX210)/RT]1/2

= (VTH/KRT)1/2

= -RTCT

Under norma/operating steady state TMOS "on" conditions,
RX and RT should be chosen such that the upper comparator
threshold voltage is never reached. This insures the TMOS
device will always be in operation so long asthe VOS(min) is not
exceeded.
The minimum time required for the capacitor CT to charge
up to upper comparator threshold voltage occurs when the
TMOS device experiences maximum current (lmax). This will
occur when the load, and in turn the source, are shorted to

(7)

Figure 25. Theoretical Fault Time versus VDS
RX = 50 k
RT=300k
CT = 0.051lF
VTH =4.4 V

10-1
VDS(min) = [(VTHRX 10) / RTll/2

~

I"

I

.1

10-4

I
I

I
I

10=100~

Ilmax) = Select
I

~T In l - VTH Rx21 0 /VDs 2Rr

1

1

N-- r-o

lminj= -RrCT In (1 - VTH /1(maxlRT)
2.0
4.0
6.0
8.0
10
12
VDS, DRAIN TO SOURCE VOLTAGE (V)

14

16

When driving incandescent lamp loads the minimum timer
time-out (the time required for the VT voltage to reach VTH
threshold of the upper comparator) should be set long enough
so as to not allow the inrush current of incandescent lamp to
cause a false trigger, yet short enough to afford the TMOS
device survival protection against direct shorts under worst
case supply and temperature conditions.
TMOS Driver Power Dissipation
Under load short conditions, the MC33091 will duty cycle
the TMOS gate. The power dissipation in this mode can be
significant. For this reason proper heatsinking of the TMOS
device is essential as is the selection of compatible external
components so as to protect the TMOS device from
destruction. In most cases, the heatsink required to handle the
TMOS power diSSipation under normal operating conditions
will be adequate to insure the device survives a short circuitfor
an indefinite time under worst case conditions.
The MC33091 can protect the TMOS device under a direct
load short condition. If the source voltage is less than about
1.5 V above ground, which will normally be the case in the
event of a dead short, the MC33091 will clamp the gate to
source voltage at 7.0 V. This action wililimitthe TMOS current
and power diSSipated under a direct load short condition.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

10-49

In[1-VTH/(ISO(max)RT)]

100

(4)

(5)

(6)

Equation 4 is shown graphically along with the asymptotic
limits imposed by Equations 5 and 7 in Figure 25.

10-3

When the timer current (ISO) is disabled, the attained VTH
voltage at Pin 8 decays according to the RTCT time constant
until the VTL threshold of the lower comparator is reached.
At this point the latch is reset and the TMOS gate, charge
pump and the current squaring circuit are again enabled,
again turning on the TMOS device. The MC33091 will
repeatedly duty cycle the TMOS gate in this manner so long
as the over current condition exists and the input control Signal
remains in a high logic state. The Fault output (Pin 6) will
likewise duty cycle.
Considerthecasewhere in Equation 4 the term (VTHRX210)
I (VOS2RT) = 1 such that the time period is undefined. Solving
for VOS for this case yields the minimum drain to source
voltage necessary which will not allow VT to charge to the VTH
threshold of the upper comparator. In other words, the TMOS
on-time period is infinite which indicative of no TMOS over
current condition existing. This minimum drain to source
voltage for uninterrupted continuous TMOS operation is:
VOS(min)

t(min)

(3)

Using Equation 1 and substituting for ISO in Equation 3:
t = -RTCT In[1-(VTHRX210)/(VOS2RT)]

ISO(max) = KVbat2 = (Vbat/RX)2/10

MC33091
The data sheet for the particular TMOS device being used
will normally reveal the current value, I OS(max), to be expected
under a dead short condition. TMOS data sheets normally
depict graphs of drain current versus drain to source voltage
for various gate to source voltages from which the drain
current at 7.0 V VGS, IOS(max), can reasonably be
approximated. Using this information, the peak TMOS power
dissipation under a dead short condition is approximated to
be:
PO(peak) = Vbat(max)IOS(max)

PO(avg) = PO(peak)OC

Figure 26. MC33091 Duty Cycle
versus VDS 1 VDS(min)

~

\
8
7

6
~ 5

is

c5
Q

VTH =4.4 V
VTL=0.6V
~ = i0sNOS( in)

4

3

\
\
\

I
,-OC=

./

\.

,

1
I-In(VnJVTH)
1+
(VTH - ~2 VTH) I-In
(VTL - ~2 VTH) I--

-

I

"'-l.
1.0 2.0 3.0 4.0 5.0 6.0 7.0
VOsNOS(min)

8.0 9.0

10 11

12

As previously discussed, ISO is externally dependant on the
sensed VOS voltage developed across the TMOS device and
RX in accordance with Equations 1 and 2. At the onset of an
overload condition, the voltage across CT will be less than the
VTH threshold voltage of the upper comparator with the TMOS
device in an "on" state. ISO current will increase dramatically
and the timing capacitor CT charges toward VTH. When the
voltage on CT reaches the VTH threshold voltage of the upper
comparator, the upper comparator output goes high setting
the latch output (a) high, turning on the open collector NPN
transistor and pulling the Fault output low. At the same time,
ISO is switched off allowing CTto discharge through resistor RT

(10)

The discharge time (td) of CT can be shown as:
td = -RTCT In(VTLNTH)

(11)

The duty cycle is defined as charge time divided by the
charge plus discharge time and represented by:
OC = td(tc+ld)

(9)

As long as the average power, in Equation 9, is less than the
maximum power dissipation of the TMOS device under normal
conditions, the short circuit protection scheme of the
MC33091 will adequately protect the TMOS device. The duty
cycle at which the MC33091 controls the gate can be
determined by using Figure 26.

£:

tc = -RTCT In[1-(VTH-VTU/(ISORT-VTLll

(8)

The average power is equal to the peak power dissipation
multiplied by the duty cycle (OC):

10

to VTL, at which time the TMOS device is again switched on.
This action is repeated so long as the overload condition
exists. The VTL and VTH thresholds are internally set to
approximately 0.6 V and 4.4 V respectively. The charge time
(tel of CT can be shown as:

Substituting Equations 10 and 11 into 12:

(12)
(13)

OC = 1/1 +In(VTLNTH)lln{(VTH-1l 2VTH)I(VTL-1l 2 VTH))
where:

Il =

VOsNOS(min)

Notice the duty cycle is dependent on/yon the ratio of the
drain to source voltage, (VOS), of the TMOS device to the
minimum drain to source voltage (VOS(min)). allowing
uninterrupted continuous TMOS operation as calculated in
Equation 5. A graph of Equation 13 is shown in Figure 26 and
is valid for any ratio ofVOS to VOS(min). Knowing this ratio, the
duty cycle can be determined by using Figure 26 or Equation
13 and knowing the duty cycle, the average power dissipation
can be calculated by using Equation 9.
If the TMOS device experiences a hard load short to ground
a minimum duty cycle will be experienced which can be
calculated. When this condition exists, the TMOS device
experiences a VOS voltage of Vbat which is sensed by the
MC33091. The MC33091 very rapidly charges the timing
capacitor CT to VTH shutting down the TMOS device. This
condition produces the minimum duty cycle for the specific
system conditions. The minimum duty cycle can be calculated
for any valid Vbat voltage by substituting the value of Vbat used
for VOS in Equation 13 and solving for the duty cycle.
Knowing the duty cycle and peak power allows
determination of the average power as was pointed out in
Equation 9. TMOS data sheets specify the maximum
allowable junction temperature and thermal resistance,
junction to case, at which the device may be operated.
Knowing the average power and the device thermal
information, proper heatsinking of the TMOS device can
.
be determined.
The duty cycle graph (Figure 26) reveals lower values of
VOS(min)produceshorterdutycycles,foragivenVosvoltages.
The minimum duty cycle, being limited to the case where
VOS = Vbat, increases as higher values of Vbat are used.

APPLICATION
The following design approach will simplify application of
the MC33091 and will insure the components chosen to be
optimal for a specific application.
1. Characterize the load impedance and determine
the maximum load current possible for the load supply
voltage used.

2. Select a TMOS device capable of handling the maximum
load current. Though the MC33091 will equally drive our
competitors products, it is hoped you will select one of the
many TMOS devices listed in Motorola's TMOS Power

MOSFET Selector Guide/Cross Reference, (SG56/0).

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
10-50

MC33091
3. Oetermine the maximum steady state VOS voltage the
TMOS device will experience under normal operating
conditions. Typically, this is the maximum load current
multiplied by the specified rOS(on) of the TMOS device.
Junction temperature considerations should be taken into
account for the rOS(on) value since it is significantly
temperature dependent. Normally, TMOS data sheets depict
the affect of junction temperature on rOS(on) and an rOS(on)
value at some considered maximum junction temperature
should be used. Various graphs relating to rOS(on) are
depicted in Motorola TMOS data sheets. Though Motorola
TMOS devices typically specify a maximum allowable
junction temperature of 150°C, in a practical sense, the user
should strive to keep junction temperature as low as possible
so as to enhance the applications long term reliability. The
maximum steady state VOS voltage the TMOS device will
experience under normal operating conditions is thus:
VOS(norm) = IL(max)rOS(on)

(14)

4. Calculate the maximum power dissipation of the TMOS
device under normal operating conditions:
PO(max) = VOS(on)IL(max)

(15)

5. The calculated maximum power dissipation of the TMOS
device dictates the required thermal impedance for the
application. Knowing this, the selection of an appropriate
heatsink to maintain the junction temperature below the
maximum specified by the TMOS manufacture for operation
can be made. The required overall thermal impedance is:
TRJA = (TJ(max) - TA(max))/PO(max)

(16)

Where TJ(max), the maximum allowable junction
temperature, is found on the TMOS data sheet and TA(max),
the maximum ambient temperature, is dictated by the
application itself.
6. The thermal resistance (TRJA), represents the maximum
overall or total thermal resistance, from junction to the
surrounding ambient, allowable to insure the TMOS
manufactures maximum junction temperature will not be
exceeded. In general, this overall thermal resistance can be
considered as being made up of several separate minor
thermal resistance interfaces comprised of TRJC, TRCS, and
TRSA such that:
TAJA = TAJC + TACS + TASA

(17)

Where TRJC, TRCS, and TRSA represent the
junction-to-case, case-to-heatsink, and heatsink-to-ambient
thermal resistances respectively. TRCS and TRSA are the only
parameters the device user can influence.
The case-to-heatsink thermal resistance (TRCS) is material
dependent and can be expressed as:
TRCS = P • tlA

(18)

Where "p" is the thermal resistivity of the heatsink material
(expressed in °C/W unit thickness), ''I'' is the thickness of
heats ink material, and "A" is the contact area of the case to
heatsink. Heatsink manufactures specify the value ofTRCS for
standard heatsinks. For nonstandard heatsinks, the user is
required to calculate TRCS using some form of the basic
Equation 18.
The required heatsink-to-ambient thermal resistance
(TRSA) can easily be calculated once the terms of Equation 17
are known. Substituting TRJA of Equation 16 into Equation 17
and solving for TRSA produces:
TRSA = (TJ(max)-TA(max))/PO(maxHTRJC+TRCS) (19)
Consulting the heatsink manufactures catalog will provide
TRCS information for various heatsinks under various
mounting conditions so as to allow easy calculation of TRSA
in units of °C/W (or when multiplied by the power dissipation
produces the heatsink mounting surface temperature rise).
Furthermore, heatsink manufactures typically specify for
various heatsinks, heatsink efficiency in the form of mounting
surface temperature rise above the ambient conditions for
various power dissipation levels. The user should insure that
the heatsink selected will provide a surface temperature rise
somewhat less than the maximum capability ofthe heatsink so
as to insure the device junction temperature will not be
exceeded. The user should consult the heatsink
manufacturers catalog for this information.
7. Set the value of VOS(min) to something greater than the
normal operating drain to source voltage, VOS(norm), the
TMOS device will experience as calculated in Step 3 above
(Equation 14). From a practical standpoint, a value twice the
VOS(norm) expected under normal operation will prove to be
a good starting point for VOS(min)'
8. Select a value of RT less than 1.0 Mil for minimal timing
error whose value is compatible with RX, (RX will be selected
in Step 9 below). A recommended starting value to use for
RT would be 470 k. The consideration here is that the input
impedance of the threshold comparators are approximately
10 Mil and if RT values greater than 1.0 Mil are used,
significant timing errors may be experienced as a result of
input bias current variations of the threshold comparators.
9. Select a value of RX which is compatible with RT. The value
of RX should be between 50 k and 100 k. Recall in Equation
5 that VOS(min) was determined by the combined selection
of RX and RT. Low values of RX will give large values for
K (K = 4.0 IJAIV2 for RX = 50 k) causing Isa to be very
sensitive to VOS variations (see Equation 1). This is desirable
if a minimum VOS trip point is needed in the 1.0 V range since
small VOS values will generate measurable currents.
However, at high VOS values, TMOS device currents become
excessively large and the current squaring function begins
to deviate slightly from the predicted value due to high level
injection effects occurring in the output PNP of the current
squaring circuit. These effects can be seen when Isa
exceeds several hundred microamps.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
10-51

,

III

I

MC33091
10. Calculate the shorted load average power dissipation for
the application using Equations 8 and 9. This involves
determining the peak shorted load power dissipation of the
TMOS device and gate duty cycle. The duty cycle is based
on VDS(min), the value of VDS under shorted conditions (Le.
Vbat(max))·
11. The calculated shorted load average power dissipation
of Step 10 should be less than the maximum power
dissipation under normal operating conditions calculated in
Step 4. If this is not the case, there are two options.
Option one is to reduce the thermal resistance of the TMOS
device heatsink, in other words, use a larger or better heatsink.
This though, is not always practical to do particularly if
restricted by size.
Option two is to set VDS(min) to the lowest practical value.
If for instance VDS(min) is set to 4.0 V when only 2.0 V are
needed, the short circuit duty cycle will be over twice as large,
resulting in double the TMOS device power dissipated.
Keeping VDS(min) to a minimum, reduces the shorted load
average power.
12. Choose a value of CT. The value of CT can be determined
either by trial and error or by characterizing the VDS waveform
for the load and selecting a capacitor value that generates
a minimum fault time curve (see Equation 4) that
encompasses the VDS versus time waveform. The value of
CT has no effect on the duty cycle itself as was pointed out
earlier. See Figure 23 for a graphical selection of CT.
Inductive Loads
The TMOS device is turned off by pulling the gate to near
ground potential. Turning off an inductive load will cause
the source of the TMOS device to go below ground due to
flyback voltage to the point where the TMOS device may
become biased on again allowing the inductive energy to be
dissipated through the load. There is an internal 14 V zener
diode clamp from the gate to source pin which will limit how far
the source pin can be pulled below ground. For high inductive
loads, it may be necessary to have an external 10k current
limiting resistor in series with the source pin to limit the clamp
current in the event the source pin is pulled more than 14 V
below ground.
Transient Faults
The MC33091 is not able to withstand automotive voltage
transients directly. However, by correctly sizing resistor RS
and capacitor CS, the MC33091 can withstand load dump
and other automotive type transients. The VCC voltage is
clamped at approximately 30 V through the use of an internal
zener diode.
Under reverse battery conditions, the load will be energized
in reverse due to the parasitic body diode inherent in the
TMOS device. Under this condition, the drain is grounded and
the MC33091 clamps the gate at 0.7 V below the battery
potential. This turns the TMOS device on in reverse and

minimizes the voltage across the TMOS device resulting in
minimal power dissipation. Neither the MC33091 nor the
TMOS device will be damaged under such a condition. In
addition, if the load can tolerate a reverse polarity, the load will
not be damaged. Some sensitive applications may not tolerate
a reverse polarity load condition with reverse battery polarity.
There is no protection of the TMOS device during a reverse
battery condition if the load itself is already shorted to ground.
The MC33091 will not incur damage under this specialized
reverse battery condition but the TMOS device may be
damaged since there could be significant energy available
from the battery to be dissipated in the TMOS device.
The MC33091 will withstand a maximum VCC voltage of
28 V and with the proper TMOS device used, the system can
withstand a double battery condition.
Figure 32 depicts a method of protecting the FET from
positive transient voltages in excess of the rated FET
breakdown Voltage. The zener voltage, in this case, should be
less than the FET breakdown voltage. The diode D is
necessary where reverse battery protection is required to
protect the gate of the FET.

EMI Concern
The gate capacitance and thus the size of the TMOS device
used will determine the turn-on and turn-off times
experienced. In a practical sense, smaller TMOS devices
have smaller gate capacitances and give rise to higher slew
rates. By way of example, the slew rate of an MPT50N06
TMOS device might be of the order of 7.5115 while that of an
MPT8N10 is23 115 (see Figure 13). The slew rate, or speed of
turn-on or turn-off can be calculated by assuming the charge
pump to supply approximately 100 !!A over the time the gate
capacitance will transition a VGS voltage of 0 V to 10 V. In
reality, the VGS voltage will be greater than 10 V but the
additional increase in TMOS drain current will be minimal for
VGS voltages greater than 10 V.
Sizing of the charge pump current is such that slew rate
need not be of concern in all but the most critical of
applications. Where limiting of EMI is of concern, the charge
pump of the MC33091 may be slew rate limited by adding an
external feedback capacitor from the gate to source of the
TMOS device for slow down adjustment of both turn-on and
turn-off times (see Figure 29). Figures 27 through 31 depict
various methods of modifying the turn-on or turn-off times.
Figure 31 depicts a method of using only six external
components to decrease turn-off time and clamp the fiyback
voltage associated with inductive loads. VGS(th) used in the
critical component selection criteria refers to the gate to source
threshold voltage of the FET used in the application.
Caution should be exercised when slowing down the
switching transition time since doing 50 can greatly increase
the average power dissipation of the TMOS device. The
resulting increase in power dissipation should be taken into
account when selecting the RTCT time constant values
in order to protect the TMOS device from any over
current condition.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
10-52

MC33091
Figure 27. Slow Down FET Turn-On

Figure 28. Slow Down FET Turn-Off

Figure 29. Slow Down Turn-On and Turn-Off of FET

Figure 30. Independent Slow Down Adjustment
of FET Turn-On and Turn-Off

Figure 31. Decreased FET Turn-Off Time
With Inductive Flyback Voltage Clamp

Figure 32. Overvoltage Protection of FET

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
10-53

MOTOROLA

MC33092

SEMICONDUCTOR-----TECHNICAL DATA

Advance Information
Alternator Voltage Regulator
The MC33092 is specifically designed for voltage regulation and Load
Response Control (LRC) of diode rectified alternator charging systems, as
commonly found in automotive applications. The MC33092 provides load
response control of the alternator output current to eliminate engine speed
hunting and vibration due to sudden electrical loads which cause abrupt torque
loading of the engine at low RPM. Two load response rates are selectable using
Pin 11. The timing olthe response rates is dependent on the oscillator frequency.
In maintaining system voltage, the MC33092 monitors and compares the
system battery voltage to an externally programmed set point value and pulse
width modulates an N-channel MOSFET transistor to control the average
alternator field current.
• Forced Load Response Control (LRC) with Heavy Load Transitions
at Low RPM
• Capable of Regulating Voltage to ± 0.1 V @ 25°C
• Operating Frequency Selectable with One External Resistor
• < 0.1 V Variation over Speed Range of 2000 to 10,000 RPM
• < 0.4 V Variation over 10% to 95% of Maximum Alternator Output
• Maintains Regulation with External Loads as Low as 1.0 A
• Load Dump Protection of Lamp, Field Control Devices, and Loads
• Duty Cycle Limit Protection
• Provides High Side MOSFET Control of a Ground Referenced Field Winding
• Controlled MOSFET and Flyback Diode Recovery Characteristics for
Minimum RFI
• < 2.0 mA Standby Current from Battery @ 25°C
• < 3.0 mA Standby Current from Battery Over Temperature Range
• Optional 2.5 or 10 sec. LRC Rate Control (Osc. Freq. = 280 kHz)
• Undervoitage, Overvoltage and Phase Fault (Broken Belt) Detection

Simplified Block Diagram
FB UV

r - - - - - - - - -1
I
I
I
I

ALTERNATOR
REGULATOR
SILICON MONOLITHIC
INTEGRATED CIRCUIT

DWSUFFIX
PLASTIC PACKAGE
CASE751D
(SO-20L)

PIN CONNECTIONS

Filter Buffer
Remote Sense
Lamp Collector
Lamp Base

V,ef

19

MC33092
Gate

Vref
UndervoHage
Source
Gate
NC
Gnd
VCC1
VCC3
Supply
Regulation
Rate

Gnd {
Oscillator
Adjust
Vref0
Oscillator
Phase
(Top View)

ORDERING INFORMATION
Device

Temperature
Range

Package

MC33092DW

- 40° to +125°C

SO-20L

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
10-54

MC33092
MAXIMUM RATINGS
Rating
Power Supply Voltage
Load Dump Transient Voltage (Note 1)
Negative Voltage (Note 2)

Symbol

Value

Unit

Vbat
+Vmax
-Vmin

24
40
-2.5

V
V
V

Po
RBJA

867
75

mW
°CIW

Power Dissipation and Thermal Characteristics
Maximum Power Dissipation @ TA = 125°C
Thermal Resistance. Junction to Ambienl
Operating Junction Temperature

TJ

+150

°C

Operaling Ambient Temperature Range

TA

-40 to +125

°C

Tstg

-45to +150

°C

Storage Temperature Range

ELECTRICAL CHARACTERISTICS (External components per Figure 1. TA = 25°C unless otherwise noted)

I

Characteristic

I

Symbol

I

Min

I

Typ

Max

Unit

14.85

-

V

DC CHARACTERISTICS

-

Regulation Voltage
(Determined by external resistor divider)

VReg

Regulation Voltage Temperature Coefficient

TC

-13

-11

-9.0

mV/oC

Vbat

11.5

14.85

16.5

V

VPwr

0.5

1.2

2.0

V

lal
la2

-

-

1.3

2.0
3.0

rnA
rnA
V

Suggested Battery Voltage Operating Range
Power Up/Down Threshold Voltage (Pin 3)
Standby Current.
Vbat = 12.8 V. Ignition off. TA = 25°C
Vbat = 12.8 V. Ignition off. - 40°C::;TASI25°C
Zero Temperature Coefficient Reference Voltage. (Pin 8)

-

Vref 0

1.1

1.25

1.4

Band Gap Reference Voltage (Pin 20)

Vref

1.7

2.0

2.3

V

Band Gap Reference Temperature Coefficient

TC

-13

-11

-9.0

mV/oC
V

SLoss(th)

-

0.6

1.0

PTh

1.0

1.25

1.5

V

Phase Rotation Detection Frequency (Pin 10)

PRot

-

36

-

Hz

Undervoltage Threshold (Pin 19)

VUV

1.0

1.25

1.5

V

Overvoltage Threshold (Pin 2. or Pin 12 if Pin 2 is not used)

VOV

1.09(Vretl

1.12(Vref)

1.16(Vref)

V

Load Dump Threshold (Pin 2. or Pin 12 if Pin 2 is not used)

VLD

1.33(Vre tl

1.4(Vre tl

1.48(Vref)

V

Sense Loss Threshold (Pin 2)
Phase Detection Threshold Voltage (Pin 10)

SWITCHING CHARACTERISTICS
-

68

-

Hz

fosc

205

280

350

kHz

Duty Cycle. (Pin 17)
At Start-up
During Overvoltage Condition

StartDC
OVDC

27
3.5

29
4.7

31
5.5

%
%

Low/High RPM Transition Frequency. (Pin 10)

LRCFreq

247

273

309

Hz

LRCS

8.5

9.5

10.5

%/sec

LRCF

34

38

42

o/oisec

LRCH

409

455

501

o/oisec

Fundamental Regulation Output Frequency. (Pin 17)
(Clock oscillator frequency divided by 4096)

f

Suggested Clock Oscillator Frequency Range. (Pin 9)
(Determined by externai resistor. RT. see Figure 6)

LRC Duty Cycle Increase Rate
Low RPM Mode (LRCFreq < 247 Hz).
Pin 11 = Open (Slow Rate)
Low RPM Mode (LRCFreq < 247 Hz).
Pin 11 = Grounded (Fast Rate)
High RPM Mode (LRCFreq > 309 Hz).
Pin 11 = Don't Care (LRC Mode is disabled)
NOTES: 1. 125 ms wide square wave pulse.
2. Maximum time =2 minutes.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
10-55

Figure 1. MC33092 Typical Application Diagram
Sense

28k

!

s::

~

::Il

o

>
r

I

r

r-------------1
1
1
1

MC33092

1
1
21

~

0)

I Lamp

2.0k

~
......

I

250

Z
~

o
cJ,

Phase
0 B+ Supply

1.0k

45k
28k

r

J

s::

IgnHion
~

0

/

W
W

Z

--t
m

0

::Il

~

CO
N

BSP52T1 '
(Q2)

()

~

m

0----

(5

rn

1Lamp
1Base

(5

k

o
m
<

15

m

1Ground

o
~
»

10

1I
MR850

Ground
NOTES: Rl = R2 = 3.0 k 10 5.0 k
R3=10klo15k
RT=50klol00k

Battery

-=J:

MC33092
Figure 3. Turn-On Voltage versus Temperature

Figure 2. Standby Current versus Temperature
0.8

l

0.7

I-

:z
w

a:
a:

"'-

'"

0.6

:::J

u

Ili
Cl

:z
~
en

0.5
0.4

m

.!!' 0.3
0.2
-55

-~

ISB = Current fro~ VCC SJpply
VCC = 12.8 V (see Figure 8)
VCl = 0.5 V (Ignition OFF)
VPin 2 = VPin 12 = 1.5 V
VPin 1 = VPin 1 = VPin 19 =OV

"

............

~

0

w

C!l

~

2.1

e

1.6

g

~

1.5

:z

1.4

Z
a:

..........

1.3

:::J
I-

........... r-.....

~

100

~

~

~

>

......

............

2.0

'"

-~

rf

100

-~

i'......

~

~

0

~

100

~

............... .......

........

~

1.26

Vref 0 ~ Voltage ~ Pin 8 I
1.25 I- VCC = 12.8 V (see Figure 8)
VC2 = 6.0 V (51 Closed)
~
0
> 1.24 I- VPin2=VPinI2=1.5V =OV
w
VPin 1 = VPin 1 = VPin 1
u
:z
w 1.23
a:
w
~
u..
w
~~
a: 1.22
~
u
\;
~ 1.21
C!l

I'-.....

100

~

,

1~

1.20
-55

-~

70

~

2.5

:i!:
w

~

0

.......

>

"

m

~

I

a..

.::

~

~

~

I

2.0

I

1.96

I

I

Lo~d Du~p

Protection

-

I:::J

-,..
r"1-

1.95

f;

VCC = 14.8 V (see Figure 8)
VC2 = 6.0 V (51 Closed)
VPin 2 = VPin 10 = VPin 12 = VPin 19 = 1.5 V
VPinl1 =OV

"
~

~

100

~

125

Figure 7. Input Voltage versus Output Duty Cycle
3.0

C!l

" ......

~

0

TA. AMBIENT TEMPERATURE (OC)

r--...

80

./

..........V

e

>

R= Resista~ce from Pin 7 to Ground
f = Frequency at Pin 9

"- ........

125

w

Figure 6. Oscillator Frequency
versus Timing Resistor

90

60

~

0

:i!:

Vref = VOl1age at Pin 20
VCC = 12.8 V (see Figure 8)
VCl = 0.5 V (Ignition OFF)
VPin 2 =VPin 12 = 1.5 V
VPin 10=VPin 1 =VPin 1 =OV

1.9

~

en
w
a:

r-......

1.1
1.0
- 55

125

I

110

~
~

r--....

0

TA. AMBIENT TEMPERATURE (OC)

u

.........

:Z 1.2

Figure 5. OTC Reference Voltage
versus Temperature

1.8
-55

w

........... 1-0.

Figure 4. Reference Voltage versus Temperature

>

e

""

TA. AMBIENT TEMPERATURE (OC)

>

a:

w

C!l

VON = Vol1age a~Pin 3 I
VCC = 12.8 V (see Figure 8)
VPin 2 = VPin 12 = 1.5 V
VPin 1 = VPin 1 = VPin 1~ = OV

TA. AMBIENT TEMPERATURE (0C)

0

w
u
:z
w
a:
w
u..
w

1.7

:i!:

0

2.2

:i!:

1.8

§-

->

~

I"'
~

~

1.94
1.93

o

10

20

30

-t

Yin =' VOltag~ at Pi~ 2 or 1~
Duty Cycle taken at Pin 17
VCC = 14.8 V (see Figure 8)
VC2 = 6.0 V (51 Closed)
VPin 10 = 1.5 V@>309Hz
VPinl1 =OV;VPi 19=1.5V

-- -

40

50

~

60

DC. DUTY CYCLE (%)

f. FREQUENCY (kHz)

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
10-57

"""-

70

80

r--

90

10C

Figure 8. MC33092 Typical Test Circuit

Vcc

250
FB

:s::

1
1

~

1

Z
m

1

--Z

&.
(X)

--I

~
m

()

Undervoltage

1

21
SenseOi i
(Remote)
1

m

JJ

MC33092

1

r

0

~GQ!_---~

r--------------

0
--I
0
JJ
0

»
JJ

1.0k

UV

ow
w
o

1

121

3:

2.0k

II U

Supply Reg OYx~~
(Local)
.

CO

f4-r+O

II

LI

OVCl

0---0 VC2

I

Sl

(5
en
0

m

<
(5
m
0

::;»

1Ground
1
_ _ _ _ _ _ _ _ _ _ _::... _ _ J I
RT

Rate

11

~

Ground

6 and 15

I\)

MC33092
PIN FUNCTION DESCRIPTION
Pin No.

Function

Description

1

FB

This pin provides a filtered result of the Sense input (if the Sense input is used) or the
Supply Regulation input (if the Sense input is not used).

2

Sense

The Sense input is a remote (Kelvin), low current battery voltage reference input used to
give an accurate representation of the true battery voltage. This input is also used to
monitor overvoltage or load dump conditions.

3

Lamp Collector and
Power-Up/Down

This pin connects to the collector of the transistor (02) used to drive the fault lamp. It is
also used to sense a closed ignition switch (voltage sense) which then turns on power to
the IC.

4

Lamp Base

The Lamp Base pin provides base current to the fault lamp drive transistor (02).

5

Ground

Grounded to provide a ground return for the fault lamp control logic circuit.

6,15

Ground

IC ground reference pins.

7

Oscillator Adjust

A resistor to ground on this pin adjusts the internal oscillator frequency, see Figure 6.

8

• Vref0

This is a test point for the 1.1 V to 1.4 V reference voltage. It has a zero temperature coefficient. The reference is used internally for phase signal and undervoltage detection.

9

• Oscillator

Test point for checking the operation of the internal oscillator.

10

Phase

The Phase input detects the existence of a magnetic field rotating within the alternator.

11

Rate

The Rate pin is used to select a slow mode (floating) or fast mode (ground) Load
Response Control recovery rate.

12

Supply Regulation

The voltage on the Supply Regulation pin is used as a representation of the alternator
output voltage. This input also used to monitor overvoltage or load dump conditions.

13

VCC3

Positive supply for the internal Charge Pump.

VCC1

Positive supply for the entire IC except for the Charge Pump.

Ground

Ground reference for the IC.

14
15,6
16

N/C

No connection.

17

Gate

Controls the Gate of the MOSFET used to energize the field winding.

18

Source

Field winding control MOSFET source reference.

19

Undervoltage

If the voltage at this pin goes below 1.0 V, the fault lamp is guaranteed to turn on. The IC
will continue to function, but with limited performance.

20

• Vref

Test point for the 1.7 V to 2.3 V Bandgap reference Voltage. This voltage has a negative
temperature coefficient of approximately -11 mVlOCo

-NOTE: Pins 8, 9 and 20 are test pOints only.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
10-59

MC33092
APPLICATION CIRCUIT DESCRIPTION
Introduction
The MC33092, designed to operate in a 12 V system, is
intended to control the voltage in an automotive system that
uses a 3 phase alternator with a rotating field winding. The
system shown in Figure 1 includes an alternator with its
associated field coil, stator coils and rectifiers, a battery, a
lamp and an ignition switch. A tap is connected to one corner
of the stator windings and provides an AC signal for rotation
(phase) detection.
A unique feature of the MC33092 is the Load Response
Control (LRC) circuitry. The LRC circuitry is active when the
stator winding AC signal frequency (phase buffer input signal,
Pin 10) is lower than the Low/High RPM transition frequency.
When active, the LRC circuitry dominates the basic analog
control circuitry and slows the alternator response time to
sudden increases in load current. This prevents the alternator
from placing a sudden, high torque load on the automobile
engine when a high current accessory is switched on.
The LRC circuitry is inactive when the stator winding AC
signal frequency is higher than the Low/High RPM transition
frequency. When the LRC circuitry is inactive, the basic
analog control circuitry controls the alternator so it will supply
a constant voltage that is independent of the load current.
Both the LRC and analog control circuits control the
system voltage by switching ON and OFF the alternator field
current using Pulse Width Modulation (PWM). The PWM
approach controls the duty cycle and therefore the average
field current. The field current is switched ON and OFF at a
fixed frequency by a MOSFET (01 ) which is driven directly by
the IC. The MC33092 uses a charge pump to drive the
MOSFET in a high side configuration for alternators having a
grounded field winding.
A fault detector is featured which detects overvoltage,
undervoltage, slow rotation or non-rotation (broken alternator
belt) conditions and indicates them through a fault lamp drive
output (Pin 4).
A Load Dump protection circuit is included. During a load
dump condition, the MOSFET gate drive (Pin 17) and the fault
lamp drive output are disabled to protect the MOSFET, field
winding and lamp.
Power-Up/Down
Power is continuously applied to the MC33092 through
VCC1 and VCC3. A power-up/down condition is determined
by the voltage on the Lamp Collector pin (Pin 3). When this
voltage is below 0.5 V the IC is guaranteed to be in a low
current standby mode. When the voltage at Pin 3 is above
2.0 V, the IC is guaranteed to be fully operational. The
power-up voltage is applied to Pin 3 via the ignition switch
and fault lamp. In case the fault lamp opens, a 500 n bypass
resistor should be used to ensure regulator IC power-up.
A power-up reset circuit provides a reset or set condition
for all digital counter circuitry. There is also a built-in power-up
delay circuit that protects against erratic power-up signals.
BaHery and Alternator Output Voltage Sensing
The battery and the alternator output voltage are sensed
by the remote (Sense, Pin 2), and the local (Supply Reg.,
Pin 12) input buffer pins, respectively, by way of external

voltage dividers. The regulated system voltage is
determined by the voltage divider resistor values.
Normally the remote pin voltage determines the value at
which the battery voltage is regulated. In some cases the
remote pin is not used. When this condition (VPin 2 < 0.6 V
typically) exists, a sense loss function allows the local pin
voltage to determine the regulated battery voltage with no
attenuation of signal. If, however, when the remote pin is
used, and the voltage at this pin is approximately 25% less
than the voltage at the local sense pin (but greater than 0.6 V,
typically), the value at which the battery voltage is regulated is
switched to the local sense pin voltage (minus the 25%). The
signal combiner/switch controls this transfer function.
Low Pass Filter, DAC & Regulator Comparator
The output of the combiner/switch buffer feeds a low pass
filter block to remove high frequency system noise. The filter
output is buffered and compared by the regulator comparator
to a descending ramp waveform generated by an internal
DAC. When the two voltages are approximately equal, the
output of the regulator comparator changes state and the
gate of the MOSFET is pulled low (turned OFF) by the output
control logic for the duration of the output frequency clock
cycle. At the beginning of the next output clock cycle, the
DAC begins its descending ramp waveform and the
MOSFET is turned ON until the regulator comparator output
again changes state. This ongoing cycle constitutes the
PWM technique used to control the system voltage.
Oscillator
The oscillator block provides the clock pulses for the
prescaler-counter chain and the charge control for the charge
pump circuit. The oscillator frequency is set by an external
resistor from Pin 7 to ground as presented in Figure 6.
The prescaler-counter divides the oscillator frequency by
212 (4096) and feeds it to the output control logic and
divider-up/down counter chain. The output control logic uses
it as the fundamental regulation output frequency (Pin 17).
Load Response Control
The Load Response Control (LRC) circuit generates a
digital control of the regulation function and is active when the
stator output AC signal (Pin 10) frequency is lower than the
Low/High RPM transition frequency. The LRC circuit takes
the output signal of the prescaler-counter chain and with a
subsequent divider and up/down counter to provide delay,
controls the alternator response time to load increases on the
system. The response time is pin programmable to two rates.
Pin 11 programs the divider to divide by 12 or divide by 48. If
Pin 11 is grounded, the signal fed to the up/down counter is
divided by 12 and the response time is 12 times slower than
the basic analog response time. If Pin 11 is left floating, the
signal to the up/down counter is divided by 48 and the
response time is 48 times slower.
The basic analog (LRC not active) and digital duty cycle
control (LRC active) are OR'd such that either function will
terminate drive to the gate of the MOSFET device with the
shortest ON-time, i.e., lower duty cycle dominating.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
10-60

MC33092
The digital ON-time is determined by comparing the output
of the up/down counter to a continuous counter and decoding
when they are equal. This event will terminate drive to the
MOSFET. A count direction shift register requires three
consecutive clock pulses with a state change on the data
input of the register to result in an up/down count direction
change. The count will increase for increasing system load
up to 100% duty cycle and count down for decreased loading
to a minimum of 29% duty cycle. The analog control can
provide a minimum duty cycle of 4 to 5%. The initial power-up
duty cycle is 29% until the phase comparator input exceeds
its input threshold voltage. Also, the IC powers up with the
LRC circuit active, i.e., when the Lamp Collector pin exceeds
the power-up threshold voltage.
Fault Lamp Indicator
Pins 3 and 4 control the external Darlington transistor (Q2)
that drives the fault indicator lamp. A Ion resistor should be
placed in series with the transistor's emitter for current
limiting purposes. The fault lamp is energized during any of
the following fault conditions: 1) No Phase buffer (Pin 10)
input due to slow or no alternator rotation, shorted phase
winding, etc.; 2) Phase buffer input AC voltage less than the
phase detect threshold; 3) Overvoltage on Pin 2, or Pin 12 if
Pin 2 is not used, or 4) Undervoltage on Pin 19 with the
phase buffer input signal higher than the Low/High RPM
transition frequency.
Phase Buffer Input
A tap is normally connected to one corner of the
alternator's stator winding to provide an AC voltage for
rotation detection. This AC signal is fed into the phase
buffer input (Pin 10) through a voltage divider. If the frequency
of this signal is less than the phase rotation detect frequency
(36 Hz, typically), the fault lamp is lit indicating an insufficient
alternator rotation and the MOSFET drive (Pin 17) output

duty cycle is restricted to approximately 29% maximum.
Also, if the peak voltage of the AC signal is less than the
phase detect threshold, the fault lamp is lit indicating an
insufficient amount of field current and again the MOSFET
drive (Pin 17) output duty cycle is restricted to approximately
29% maximum.
Undervoltage, Overvoltage and Load Dump
The low pass filter output feeds an undervoltage
comparator through an external voltage divider. The voltage
divider can be used to adjust the undervoltage detection
level. During an undervoltage condition, the fault lamp will
light only if the phase buffer input signal frequency is higher
than the Low/High RPM transition frequency. This is to
ensure that the undervoltage condition is caused by a true
fault and not just by low alternator rotation. To help maintain
system voltage regulation during an undervoltage condition,
the output duty cycle is automatically increased to 100%.
Even though the fault lamp may be energized for an
undervoltage condition, the MC33092 will continue to operate
but with limited performance.
Through an internal voltage divider, the low pass filter
feeds an overvoltage comparator which monitors this output
for an overvoltage condition. If the overvoltage threshold is
exceeded, the fault lamp is lit and the MOSFET drive (Pin 17)
output duty cycle is restricted to approximately 4% maximum.
The internal voltage divider on the input to the load dump
comparator has a different ratio than the divider used on the
overvoltage comparator. This allows the load dump detect
threshold to be higher than the overvoltage threshold even
though both comparators are monitoring the same low pass
filter output. If the load dump detect threshold is exceeded,
the fault lamp and MOSFET drive outputs are disabled to
protect the MOSFET, field winding and lamp.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
10-61

MOTOROLA

MCCF33093

SEMICONDUCTOR-----TECHNICAL DATA

Product Preview

IGNITION CONTROL
FLIP-CHIP

Ignition Control Flip-Chip
Designed for automotive ignition applications. The MCCF33093 provides
outstanding control of the ignition coil when used with an appropriate Motorola
Power Darlington Transistor. Engine control systems utilizing the MCCF33093
exhibit exceptional fuel efficiency and low exhaust emissions. The MCCF33093
requires a differential Hall Sensor input for proper operation.
The MCCF33093 utilizes Flip-Chip Technology in which solder bumps, rather
than traditional wire bonds, are created to establish mechanical and electrical
contact to the chip. This process affords a unique device having improved
reliability at elevated operating temperatures.
• Solder Bumped for Flip-Chip Assembly
• External Capacitors to Set Device TIming
• Overvoltage Shutdown Protection
• Auto Start-Up Capability Once Overvoltage Condition Ceases
• Allows for Push Start-Up in Automotive Applications
• Ignition Coil Current Limiting
• Ignition Coil Voltage Limiting
• Bandgap Reference for Enhanced Stability Over Temperature
• Negative Edge Filter for Hall Sensor Input Transient Protection
• Hall Sensor Inputs for RPM and Position Sensing
• - 30°C S TA S +140°C Ambient Operating Temperature

SILICON MONOLITHIC
INTEGRATED CIRCUIT

FLIP-CHIP CONFIGURATION
14
13

0

12
11

0

0

2

0

0

3

0>

0

4

0

5

0

6

1

!

10

.J

9

.J

y

0

\..

!

y

0

\..

0

8
(Backside View)

0.116 inch x 0.091 inch
Backside orientation marking
indicated by arrow oriented as shown

Simplified Block Diagram
and Application Circuit

vee

o
BUMP CONNECTIONS
1.
2.
3.
4.

5.
6.
7.
8.
9.

10.
11.
12.
13.
14.

Ground
Master Bias
Adaptive Capacitor
Ramp Capacttor
Positive Hall Input
Negative Hall Input
Start
Supply
Distributor Signal
Coil
Output
Process Tast
Emitter of Darlington
Stall Capacttor

ORDERING INFORMATION
Device

Temperature
Range

Package

MCCF33093

- 30° to +140°C

Flip-Chip

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
10-62

MOTOROLA

MCCF33094

SEMICONDUCTOR-----TECHNICAL DATA

Product Preview

IGNITION CONTROL
FLIP-CHIP

Ignition Control Flip-Chip
Designed for automotive ignition applications. The MCCF33094 provides
outstanding control of the ignition coil when used with an appropriate Motorola
Power Darlington Transistor. Engine control systems utilizing the MCCF33094
exhibit exceptional fuel efficiency and low exhaust emissions. For proper
operation, the MCCF33094 requires a single Hall Sensor input signal, which is
compared to an accurate internal reference.
The MCCF33094 utilizes Flip-Chip Technology in which solder bumps, rather
than traditional wire bonds, are created to establish mechanical and electrical
contact to the chip. This process affords a unique device having improved
reliability at elevated operating temperatures.
• Solder Bumped for Flip-Chip Assembly
• External Capacitors to Set Device Timing

SILICON MONOLITHIC
INTEGRATED CIRCUIT

FLIP-CHIP CONFIGURATION
14
13

0

12

0

11

0

0

0

2

0

3

0

4

0

5

0

6

• Overvoltage Shutdown Protection
• Auto Start-Up Capability Once Overvoltage Condition Ceases
• Allows for Push Start-Up in Automotive Applications
• Ignition Coil Current limiting
• Ignition Coil Voltage Limiting
• Bandgap Reference for Enhanced Stability Over Ternperature

>

1

10

-'

0

L

y

• Negative Edge Filter for Hall Sensor Input Transient Protection

1
-'

• Hall Sensor Inputs for RPM and Position SenSing

0

L

y

• - 30°C::; TA ::; +140°C Arnbient Operating Temperature

1

0

7
8
(Backside View)

0.116 inch x 0.091 inch
Backside orientation marking
indicated by arrow oriented as shown

Simplified Block Diagram
and Application Circuit
D

vee

BUMP CONNECTIONS
1.
2.
3.
4.

Ground
Master Bias
Adaptive Capacnor
Ramp Capacnor
5. Positive Hall Input

In 1+) -'Wv-Oe;-,

6. N.C.
7. Start
8. Supply

9.
10.
11.
12.
13.
14.

sw~~~or----~~~~
loOk

Distributor Signal
Coil
Output
Process Test
Emitter of Darlington
Stall Capacnor

ORDERING INFORMATION
Device

Tel]1perature
Range

Package

MCCF33094

- 30° to +140°C

Flip-Chip

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
10-63

MCCF33095

MOTOROLA

SEMICONDUCTOR-----TECHNICAL DATA

Advance Information

INTEGRAL ALTERNATOR
REGULATOR

Integral Alternator Regulator
The MCCF33095 Flip-Chip is a regulator control integrated circuit designed
for use with the MCCF33096 Darlington Flip-Chip in automotive alternator
charging systems. Few external components are required for full system
implementation when the MCCF33095 is used with the MCCF33096. This chip
set combination provides control for a broad range of 12 V alternator systems
when used with the appropriate Motorola Power Darlington to control the field
current of the specific alternator.
The MCCF33095 is designed to work in harsh automotive environments.
Internal detection and protection features coupled with Flip-Chip Technology
make the MCCF33095 able to withstand severe vibration, thermal shock, and
extreme electrical variations with a high degree of reliability.

SILICON MONOLITHIC
INTEGRATED CIRCUIT

FLIP-CHIP CONFIGURATION

,"

--<+~

y

• Constant Frequency with Variable Duty Cycle Operation

-"

--<+~

'I'

-"

--<+~ 10

• Adjusts System Charging to Compensate for Changes
in Ambient Temperature

Y

A

• Slew Rate Control to Reduce EMI

-"
--<+~
y

• Lamp Pin to Indicate Abnormal Operating Conditions

,I,

-"

y

y

--<+~ --<+~

• Shorted Field Protection
• Resumes Normal Operation Once Fault Condition Ceases

6

• Thermal Operation from - 40° to 170°C

(Backside View)
Back marking is array oriented as shown

• Solder Bump Processed for Flip-Chip Assembly
• Minimal Space Required

BUMP CONNECTIONS

Simplified Block Diagram

1. VCC
2. Sense
Ignition ,,4-1-----"____

3. Stator

Load Dump
Detection and
Protection

4. Ignition
5. Lamp

g6ti-;=1~~~~;tc~_1---~~19 Darlington

Oscillator

6. Oscillator

Drive
7. RolI·Off
Sense 02-H...-t--t
8. Ground
9. Darlington Drive

to

Shortot-H---{~~..J

7

Circuit

10. Short Circuit
Roll-Off

Statoro3~----------1

ORDERING INFORMATION

Device

Temperature
Range

Package

MCCF33095

- 40' to +Il0'C

Flip-Chip

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
10-64

MCCF33095
MAXIMUM RATINGS (Note 1,3)
Rating

Symbol

Steady State VCC, VIGN, VSTA

Value

Unit

9.0 to 24

V

VCC and VIGN Transient

80

V

Bump Shear Strength

8.0

Grams/Bump

700
29

mW
°C/W

Power Dissipation and Thermal Characteristics
Maximum Power@ TA ~ 25°C
Thermal Resistance, Junction-to-Substrate

TJS

Operating Junction Temperature

TJ

+170

°C

Ambient Temperature Range

TA

- 40 to + 170

°C

ELECTRICAL CHARACTERISTICS (Limit values are given for- 40°C" TA" 150°C and typical values represent approximate mean value
at TA ~ 25°C. Pins 6, 7, 8, 1a ~ 0 V, and 12 V " Pins 1, 2, 3, 4 " 16 V, unless otherwise specified.)

I

Characteristics

Symbol

I

Min

I

Typ

I

Max

I

Unit

SUPPLY (Pin 1)
Supply Current
Disabled (Pin 4 ~ 0.5 V, Pin 3 ~ 5.0 V)
Enabled (Pin 1, 2 ~ 17 V, Pin 4 ~ 1.4 V)

ICC

Darlington Drive Overvoltage
Disable Threshold (pin 1, 4, 1a ~ 19 V to 29 V Ramp, Pin 3 ~ 10 V)
Hysteresis (Pins 1, 3, 4, 10 ~ 29 V to 19 V Ramp)

- 50
0

+ 0.2
3.9

+ 50
25

19

26
4.2

28
-

22.3
0.3

28
-

!I A
mA
V

VCODD
VCODDH

-

V

lamp Overvoltage
Disable Threshold (Pins 1, 3, 4, 10 ~ 19 V to 29 V Ramp)
Hysteresis

VCOl
VCOlH

19

-

SENSE (Pin 2)
Sense Current (Pin 6 ~ 2.0 V)
Calibration Voltage (50% Duty Cycle, Note 5)
lamp Comparator Detect Thresllold

Isense

-10

+ 0.6

+10

VR

12.25

14.6

16.4

lamp Comparator Reset Threshold
lamp Hysteresis

V

-

16.3

MV

50

187.4

350

VHV

15.4

15.9

16.4

V

Vhys

20

416.6

600

mV

6.0

59.4

600

6.0

8.8

10

-10

+ 1.5

+10

0
0

111.8
147.4

350
350

-50

+ 0.8

+ 50

VSCD

Proportional Control Range

!I A

-

V
mV

STATOR
Propagation Delay
lamp-to-High (Pin 3

ms

tSTA
~

15 V to 6.0 V)

Reset Threshold Voltage
lamp-to-low (Pin 3 ~ 5.0 V to 11 V)

VIH

Input Current
(Pin 2 ~ 18 V, Pin 6

ISTA
~

2.0 V)

V

!IA

lAMP (Pin 5)
Saturation Voltage
(Pin 5 ~ 14 mAl
(Pins 1, 2, 3, 4 ~ 30 V, Pin 5
leakage Current
(Pin 2 ~ 1.0 V, Pin 5

mV

VOll
~

20 mAl

~

IOHl
~

2.5 V)

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
10-65

I

MCCF33095
ELECTRICAL CHARACTERISTICS (Limit values are given for - 40°C,;; TA ,;; 150°C and typical values represent approximate
mean value atTA = 25°C. Pins 6, 7, 8,10 = 0 V, and 12 V,;; Pins 1, 2, 3, 4,;; 16 V, unless otherwise specified.)
Symbol

Characteristics

Min

Typ

Max

5.0

7.6

20

0

300.1

350

Unit

DARLINGTON DRIVE (Pin 9)
Source Current
Pins 1, 2, 4 = 9.0 V, Pin 9 = V Across Power Darlington)

IOHDD

Saturation Voltage
(Pin 2 = 18 V, Pin 6 = 2.0 V, Pin 9 =-100 /lA)

VOLDD

Minimum ON lime (Pin 2 = 18 V, Note 5)

rnA
mV

tDD

200

697.8

-

Frequency (Note 5)

FOSC

75

174.7

325

Minimum Duty Cycle (Pin 2 = 18 V, Note 5)

DCDD

j1S

Hz

-

12.2

13

%

tr
tf

10

21.4
23.7

50

I1S

Duty Cycle (Note 5)

DCSC

0.5

1.7

5.0

%

ON lime (Note 5)
(Short Circuit High, Pin 10 = 8.0 V)

PWSC
50

99

660

Rise lime (10% to 90%, Note 5)
Fall lime (90% to 10%, Note 5)
SHORT CIRCUIT

I1S

NOTES: 1. Inputs to Pin 1 applied through a 250 Cl resistor.
2. Inputs to Pin 2 applied through a 100 kCl and 50 kCl resistor divider to generate one-third Vbat.
3. Inputs to Pin 3 and Pin 4 are applied through a 20 kCl resistor.
4. Inputs to Pin 10 applied through a 30 kCl resistor.
5. Pin 6 connected in series with 0.0221LF capaCitor to ground.

MECHANICAL DIMENSIONS
cp
0

2
,--=------------==-------+'1
, L

o----~~:t;~------~~--~

1----....:.4+--<:t ;-

'[
+;'[

10

6

~;-

9

7

81

L~ t
0.559
0.483

-80

r. ., ,. .

1.905

:t:-----<:t;-

5

.--__,.-__1---,

+;

J

,L

Dia. 10 Places

0.140-

""'1">--3---- 2.032

0.185 - - -

~:~~~

0.025R of True PosHion

'"
00

I I
-----1-----1

~

d

NOTE:

D

1. Ali dimensions shown indicated in miiiimeters.
2.
Denotes basic dimension having zero
tolerance and describes the theoretical
exact location (true posHion) or contour.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

10-66

0.029

Maximum taper either
direction allowed, 4 edges.
Die sawed through.

MCCF33095
Figure 1. Pins 1, 3, and 4 Field Transient Decay

Figure 2. Pins 1 and 4 Load Dump Transient Decay

40

1\J

VFT = 14.5 V for 0" t" 0.38 sec
VFT = - 75 e1/0.038 for 0 s; t s; 0.38 sec
Refer to Notes 1 to 5 of Electrical Table
for Ci cuit Ho k·Up

20 r-114 .5V

13

~

g

~

w

u:: -20

!z
w

/

fQ - 40
O§

I-

.:- - 60
u..
>
- 75
- 20

/

",

--

2:

I

1"-

w

(!J

130

60

>

I- 40
z
w
u;
z

16.5

20

40

60
80
t, TIME (ms)

100

380

400

o

o

420

0::

14.5

1\J

14.0

ou..

2:

-- --- ---

i---.

;------- ----

135
.

>
1i; 13.0
.0

-40

I--

...

19 r - - r - - , - - - , - - , - - , - - - , - - - , . . . - - - - - ,

~

~

16r---+-~4r---+~~r-.r9----+----r-~

0::

:3

o

~ 15~--1-~~~~~--t---~---+----t---~

.... .....

120

17r---~---+--~~~~~~'-_+~~r_--~

l-

-- ------ -----

~

>

13

160

Figure 5. Field Current versus Cycle Time

gl.000
I-

Z

W

~ 0,075

:::>
(,)

g

~

u..

0.050

Ii.

0.025

/\

I

13.5
14
14.5
15
15.5
Vbat FOR A 50% DUTY CYCLE (V)

16

16.5

Figure 6. Field Current versus Time
2.0

Vbat = 14.4 V
Duty Cycle = 6.0%
TA = 25°C

It

400

~ 18r--r--+--+--+--~~-r~~-~
z
Z

i:?

1.025

300

o

...............

40
80
TA, TEMPERATURE (DC)

"

200
t, TIME (ms)

::;;

~cal

> 12.5

100

a.

Maximum

Minimum

13o

"'-

Figure 4. Vbat (50% Duty Cycle) versus
Vbat (Lamp ON)

1-___

(,) 16.0

~

.........

g 20

G

~ 15.0

~

>

~

~ 15.5
:::>

"""

0::
1-"

Figure 3. Temperature versus
Vbat for 50% Duty Cycle

2:

VLD = 80 e- 5t for 0 s; t s; 0.342 sec
VLD = 14.5 V for t " 0.342 sec
Refer to Notes 1 to 5 of Electrical
Table for Circu~ Hook·Up

«

/

0

80

g
!z
w

-

1.5

0::
0::

\.

"'"

B 1.0

g

'" --

w

u::
~0.5

Vbat = 14.4 V
Duty Cycle =86%
TA =25°C

............

1.4

~

2.8
SC, CYCLE TIME (ms)

4.2

5.6

o

o

1.4

2.8
SC, CYCLE TIME (ms)

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

10-67

4.2

5.6

MCCF33095
Figure 7. Integral Alternator Regulator System
r---~r---------~----------------------------------~~A

1°.

250(1

047

r-----~------------_r~Sr_+_--------~------~~~

1.0k

1°·1

tOOk

r-

1

Vee

1

18k

-------

Stator

3

Stator

se f-l;.:O__"W\.-____f--,

21

1

.----+----"-i SENSE

1

0 022
.

5Dk

.Ii

0.022

1=

19

MCCF33D95

1

DD j-'-------L.

Dse

1
L

D

----,

Field

1
IGN

4

LMP

A.D.

GND...J

Power Ground

-----5--i--~

FUNCTIONAL DESCRIPTION
Introduction
The MCCF33095 Flip-Chip circuit was originally designed
for use in alternator charging systems. The MCCF33095
consists of many protection features which are entailed in a
10-pin flip-chip package. Device operation and application
suggestions are given below.

cycle. A low voltage at the Sense pin will result in a long duty
cycle for the Darlington and a high voltage produces a short
duty cycle. Proportional control is used to determine the duty
cycle time. Proportional control is defined as the difference
between the alternator voltages required for 20% and 95%
output duty cycles.

Oscillator
The oscillator frequency is determined by the value of an
external capacitor from the oscillator pin to ground (see
Figure 7). The oscillator frequency in a typical application is
approximately 175 Hz, but a range of 50 Hz to 500 Hz can
reasonably be used. The waveform generated consists of a
positive linear slope followed by relatively fast negative fall
(sawtooth). The flip-flops are reset by the falling edge of the
sawtooth signal as shown in the Simplified Block Diagram.
The oscillator signal peaks at approximately 3.0 V and
provides the timing required for the device.

Lamp
The Lamp Output pin functions as a warning indicator
for overvoltage and stopped engine conditions existing in
the system.

Ignition
The Ignition input signal enables the device turn-on when
the Pin 4 voltage is greater than 1.4 V. This signal normally
originates from the ignition switch of automotive systems.

Power Supply, Vee
The VCC pin powers the entire device and disables all
outputs during any overvoltage condition.

Sense
The Sense pin functions as a voltage sensor. It
proportionally senses the battery voltage and determines the
amount of time the Darlington transistor is high over the next

Stator
The Stator pin senses the voltage from the Stator in the
application circuit, and keeps the device powered up while the
stator voltage is high. Furthermore, it acts as a sense for a
stopped engine condition. If this condition is detected, the
Stator turns ON the lamp.

Roll Off
The Roll Off pin provides thermal protection for the circuit.
This capability exists, but has not been characterized and is
not tested for at this time. Therefore, it is recommended that
this pin be connected to ground.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
10-68

MCCF33095
Darlington Drive
The Darlington Drive output pin exists to turn on a power
Darlington. The Sense pin voltage determines the duty
cycle of the Darlington. The oscillator is set to maintain a
minimum duty cycle, except during overvoltage and short
circuit conditions.
Short Circuit
The Short Circuit pin monitors the field voltage. When the
Darlington Drive and Short Circuit pins are simultaneously
high for a duration greater than the slew rate period, a short
circuit condition is noted. The detection time required prevents
the device from reacting to false shorts. As a result of short

circuit detection, the output is disabled. During a short circuit
condition the device automatically retries with a 2% duty cycle
(Darlington ON). Once the short circuit condition ceases,
normal device operation resumes.
Note
A capacitor should be used in parallel with the VCC pin
to filter out noise transients. Likewise, a capacitor should be
used in parallel with the Sense pin to create a dominant
closed-loop pole. Resistors connected to inputs, as
mentioned in Notes 1 through 5 of the Electrical Characteristic
table, should be used.

FLIP-CHIP APPLICATION INFORMATION
Introduction
Although the packaging technology known as "flip-chip" has
been available for some time, it has seen few applications
outside the automotive and computer industries. Present
microelectronic trends are demanding smaller chip sizes,
reduced manufacturing costs, and improved reliability.
Flip-chip technology satisfies all of these needs.
Conventional assembly techniques involve bonding wires
to metal pads to make electrical contact to the integrated
circuit. Flip-chip assembly requires further processing of the
integrated circuit after final nitride deposition to establish
robust solder bumps with which to make electrical contact to
the circuit. Aspatially identical solderable solder bump pattern,
normally formed on ceramic material, serves as a substrate
host for the flip-chip. The "bumped" flip-chip is aligned to, and
temporally held in place through the use of soldering paste.
The aligned flip-chip and substrate host are placed into an
oven and the solder reflowed to establish both electrical and
mechanical bonding of the flip-chip to the substrate circuit.
Use of solder paste not only holds the chip in temporary
placement for reflow but also enhances the reflow process to
produce highly reliable bonds.
Flip-Chip Benefits
Some of the benefits of flip-chip assembly are:
1) Higher circuit density resulting in approximately
one-tenth the footprint required of a conventional
plastic encapsulated device.
2) Improved reliability especially in high temperature
applications. This is due, in part, to the absence
of wires to corrode or fatigue from extensive
thermal cycling.
3) No bond wires are required that might possibly
become damaged during assembly.
4) Adaptable for simultaneous assembly of multiple
flip-chips, in a hybrid fashion, onto a single
ceramic substrate.
The following discussion covers the flip-chip process steps
performed by Motorola, and the assembly processing
required by the customer, in order to attach the flip-chip onto
a ceramic substrate.

MOTOROLA'S FLIP-CHIP PROCESS
Overview
The process steps to develop an integrated circuit flip-chip
are identical to that of conventional integrated circuits up to

and including the deposition of the final nitride paSSivation
layer on the front surface (circuit side). At this stage all device
metal interconnects are present.
The process sequence is as follows:
1) Passivation-nitride photo resist and etch
2) Bimetal sputter (titanium (Ti) and tungsten (W)
followed by copper (Cu))
3) Photo mask to define the bump area
4) Copper plate
5) Lead plate
6) Tin plate
7) Photoresist clean to remove all photo resist material
8) Bimetal etchback
9) Reflow for bump formation
10) Final inspection
The diagram below depicts the various layers involved in
the bump process.
Figure 8. Plated Bump Structure
and Process Flow

Solder Bump After Reflow
Plated Copper

Initially, photoresist techniques are used to create openings
in the nitride passivation layer exposing the metal pad vias.
TilW, followed by Cu, are sputtered across the entire wafer
surface. The surface is then photo patterned to define the
bump areas. The sputtered metals together constitute a base
metal for the next two metal depositions.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
10-69

MCCF33095
The TIIW layer provides excellent intermetallic adhesion
between the metal pads and the sputtered copper. In addition,
the TIm provides a highly reliable interface to absorb
mechanical shock and vibrations frequently encountered in
automotive applications. The sputtered copper layer creates
a platform onto which an electroplated copper layer can be
built-up. Layers of Cu, Pb, and Sn are applied by plating onto
the void areas of the photo resist material. The photo resist is
then removed and the earlier sputtered materials are etched
away. The flip-chip wafer is then put into an oven exposing it
to a specific ambient temperature which causes the lead and
tin to ball-up and form a solder alloy.

Ie Solder Bumps
The solder consists of approximately 93% lead and 7% tin.
The alloying of lead with tin provides a bump with good ductility
and joint adhesion properties. Precise amounts of tin are used
in conjunction with lead. Too much tin in relation to lead can
cause the solder joints to become brittle and subject to fatigue
failure. Motorola has established what it believes to be the
optimum material composition necessary in order to achieve
high bump reliability.
In the make-up of the flip-chip design, bumps are ideally
spaced evenly and symmetrically along each edge of the chip
allowing for stress experienced during thermal expansion and
vibration to be distributed evenly from bump to bump. The
bump dimensions and center-to-center spacing (pitch) are
specified by the chip layout and the specific application. The
nominal diameter of the bumps is 6.5 mils and the minimum
center-to-center pitch is roughly 8.0 mils.
Reflow
The reflow process creates a thermally induced amalgam of
the lead and tin. In the melting process the surface tension is
equalized causing the melted solder to uniformly ball up as
mentioned earlier.
The ideal reflow oven profile gradually ramps up in
temperature to an initial plateau. The purpose of the plateau
is to establish a near equilibrium temperature just below that
of the solder's melting temperature. Following the preheat, a
short time and higher temperature excursion is necessary.
This is to ensure adequate melting of the solder materials. The
temperature is then ramped down to room temperature.
An atmosphere of hydrogen is used during the reflow heat
cycle. The hydrogen provides a reducing atmosphere for the
removal of any surface oxides present. The formation or
presence of oxides can cause degradation in the bond
reliability of the product.
During the flip-chip attachment reflow onto the ceramic substrate host, the created surface tension of the molten solder
aids in the alignment of the chip onto the ceramic substrate.

ATIACHING FLIP-CHIPS ONTO
CERAMIC SUBSTRATES
Overview
The assembly or process of attaching the flip-chip onto a
ceramic substrate is performed by the module fabricator. Prior
to actual assembly the ceramic substrate should undergo
several process steps. Care should be exercised to properly
orient the flip-chip onto the substrate host in order to
accommodate the appropriate solder bumps. Ideally, the
flip-chip should be removed from the waffle pack with a pick
and place machine utilizing a vacuum pick-up to move the die
onto the ceramic substrate. Any other components to be
reflow soldered onto the substrate can be placed onto the
substrate in a similar manner. Flip-chip assembly onto a
ceramic substrate allows for some passive components such
as resistors to be formed directly into the ceramic substrate
circuit pattern itself. With all surface components to be
mounted in place on the ceramic substrate, the assembly is
moved into the furnace where it undergoes a specified
temperature variation to solder all the components onto the
ceramic substrate. This is accomplished by melting (reflowing)
the substrate solder bumps. The resulting assembly should,
after being cooled, be cleaned to remove any flux residues. If
the substrate assembly is to be mounted into a module, it is
recommended the cavity of the module be filled with an
appropriate silicone gel. The use of a gel coating helps to seal
the individual components on the substrate from external
moisture. A commonly used gel for this purpose is Dow
Corning 562. As a final module assembly step, a cover is
recommended to be placed over the ceramic assembly for
further protection of the circuit.
It should be pointed out that the commonly used ceramic
substrate material, though more expensive than other
substrate materials, offers significantly superior thermal
properties. By comparison, the use of ceramic material offers
33 times the thermal advantage of the second best material,
Ceracom. The common FR-4 epoxy material is 100 times less
thermally conductive than ceramic. For applications where
dielectric constants are important and/or heat dissipation is
not of real importance, other less costly materials can be used.
The basic concept of the process is identical for all flip-chip
substrates used.
Figure 9. Process Flow Diagram

Reliability
Motorola is determined to bring high quality and reliable
products to its customers. This is being brought about by
increased automation, in-line Statistical Process Control
(SPC), bump shear strength testing, thermocycling from
- 40° to +140°C, process improvements such as backside
laser marking of the silicon chip, and improved copper
plating techniques.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

10-70

MCCF33095
Ceramic Substrate Preparation
The recommended ceramic substrate is aluminum oxide.
These substrates come connected in what is referred to as a
card. This is identical to the concept of die or chips on a wafer.
Each card usually contains 8 to 16 substrates.
Initially the ceramic should be precleaned with isopropyl
alcohol, followed by freon. The bump pattern is then
transferred onto the substrate using a metal stencil technique
using a palladium silver conducting paste, such as DuPont
9476, through a #325 mesh. Once the pattern is applied, the
substrate is dried for ten minutes at 150°C and then fired for
60 minutes at a temperature increasing to a peak of 850°C for
ten additional minutes. Solder paste is then stenciled onto
the pads.
A metal etched stencil defining the contact areas is
recommended. The use of an etched stencil affords better
solder paste control than does a silk screen. The metal stencil
affords a deposition of a known amount of solder paste,
thereby preventing bridging caused by excess solder usage.
Solder Paste Content
It is recommended that the solder paste consist of 10% tin,
88% lead, and 2% silver alloy. However, 95/3/2 compositions
have had successful results.
A rosin based flux, such as RMA (Rosin Mildly Activated)
manufactured by Dupont and having spherical particles of 45
to 75 microns, should be used. The tackiness of the solder
paste at room temperature helps to hold the flip-chip in place
during the pick and place operation. The use of flux:
1) Prevents excess oxidation during reflow,
2) Optimizes the flow of liquid solder through the stencil,
3) Smooths the surface by reducing surface tension, and
4) Enhances the normalization of surface tension upon
reflow causing the flip-chip bumps to effectively
auto-align themselves to substrate bump pads.
A solder mask can be used for applications requiring high
precision and is shown in Figure 10.
Figure lOa. Before Reflow

Figure 11. Reflow OVen Profile

o~-~-~---:---:::-

---..

The oven temperature profile is established primarily to melt
the solder while minimizing the alloying of the materials and
keeping the flux from boiling away. It should be noted that
when the flip-chip is placed onto the substrate, the material is
stressed in one direction or another. The use of flux helps to
reduce any surface stresses present. A reduction in the
surface stress enhances solder wetting which in turn aids in
the alignment of the flip-chip to the substrate. Poor solder
wetting will produce misalignment as well as inferior bond
strengths and reliability.
It is recommended that an inert atmosphere such as
nitrogen be used during the reflow process to prevent
oxidation.
Final Cleaning
The final cleaning involves removing the remaining flux from
the flip-chip assembly. Three possible methods of removing
flux are: ultrasonic cleaner, Terpene solvent and 01 water, or
vapor degreaser. The flux manufacturer should be able to
recommend the proper type of vapor degreaser to be used.

Aip-Chip Bump
/
r>o,...:::><-c.=---'i

Oven Profile
After the flip-chip is placed onto the bumped substrate, the
substrate and flip-chip are ready for reflow.lnitially, the flip-chip
is heated to a peak temperature of around 300° to 350°C for
five minutes. It is to be noted that the flip-chip bumps have a
higher melting temperature than the bumps on the substrate.
During assembly reflow the substrate bumps melt and create
a substrate to flip-chip bump bond. After reflow the assembled
part is cooled to room temperature or to some intermediate
temperature point for annealing purposes.

Aaltened Pb/Sn

~~~~~;;s~i Solder Mask
Ceramic

Figure lOb. After Reflow
IC
Flip-Chip Bump
Pb/Sn
Reflow
~;L.;:-~~Ip...:-T>n;- Solder Mask

Ceramic

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
10-71

III
I

MCCF33095
Test and Reliability
Both visual inspection and shear strength testing should be
performed on packaged flip-chip assemblies.
Solder reflow results which exhibit a grainy and dull
appearance produce inferior bond shear strengths. Inferior
bond shear strengths are visually recognizable by:
1) The presence of old or badly oxidized solder paste,
2) Insufficient amount of solderable material,
3) The contamination of bond pads with grease, oil, etc.
It should be mentioned that many contaminants are
transparent and not easily detectable by visual means.
Shear strength testing should meet a 0.8 Newtons/Bump
criteria. Shear strength testing should follow thermocycling of
the chip from - 40° to +140°C to insure the stability of shear
strength over temperature. Figure 12 depicts a test set-up
which might possibly be used.

Figure 12. Shear Test Fixture
Substrate

Aside from physical contamination, flip-chips, like any other
chips, should not be handled directly due to the fact that
electrostatic discharges can cause permanent damage to the
electronic circuit. Flip-chips which do survive an electrostatic
discharge can be left in a weakened condition resulting in
reduced reliability of the end product. To avoid electrostatic
damage of the circuit, assembly personnel should make use
of a wrist strap or some other device to provide electrostatic
grounding of their body. For the same reason, machinery
used to assemble semiconductor circuits should be
electrostaticly grounded.
Flip-chips rely primarily on the thermal path established by
the bumps to remove heat from the chip as a result of internal
circuit operation. Standard Motorola flip-chips have a thermal
resistance of approximately 290°C/w/Bump. This figure can
be used to estimate the allowed maximum power dissipation
of the chip.

Cost and Equipment Manufacturers
The cost of implementing a flip-chip assembly process
depends on the specific production requirements and as a
result will vary over a broad range. It is possible to implement
a small volume laboratory set-up for a few hundred dollars
using manual operations. At the other end of the scale one
could spend millions setting up a fully automated line
incorporating pattern recognization, chip and substrate
orientation, reflow, cleaning, and test. The module fabricator
will have to make this assessment.
An assembly operator can manually accomplish the pick
and place operation using a vacuum probe to pick-up arid
orient the flip-chip onto the substrate. Furthermore, it is
possible to perform the ref low assembly operation using a
simple batch process oven fabricated from a laboratory hot
plate. However, the use of such process techniques will have
questionable impact on the final product's reliability and
quality. For this reason, it is highly recommended the module
fabricator seriously consider two major pieces of equipment;
a pick and place machine and an infrared solder reflow oven.
Both pieces of equipment can vary over a wide cost range
depending on the production requirements. A partial list of
manufacturers for this equipment is given below.
Pick and Place Machine:
Universal Instruments Corp
Dover Technologies, Inc.
Binghamton, NY 13902
(607) 772-7522
Seiko
Torrance, CA 90505
(310) 517-7850
Laurier Inc.
Hudson, NH 03051
(603) 889-8800
Infrared Reflow Oven:
BTU
Bellerica, MA 01862
(508) 667-4111
Vitronics
Newmarket, NH 03857
(603) 659-6550
Additional Applications
Completed ceramic flip-chip sub-assemblies can be
stacked one on top of another to produce an overall assembly
by making contact connections through bumps. This
technology is beginning to emerge in the computer industry
where physical module size is of significant importance.
Furthermore, this assembly technology, though more
complex, is undergoing serious consideration within the
automotive industry as well.
Applications requiring small size and high reliability at high
ambient temperatures can benefit considerably through the
implementation of flip-chip assembly techniques.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

10-72

MOTOROLA

MCCF33096

SEMICONDUCTOR-----TECHNICAL DATA

Advance Information

Darlington Drive Flip-Chip
The MCCF33096 is a Darlington Flip-Chip designed for use with the
MCCF33095 Flip-Chip as a lamp driver in automotive charging systems. The
MCCF33095 and MCCF33096, when used with an appropriate Motorola Power
Darlington Transistor, provide the necessary control for automotive alternator
regulator systems. The MCCF33096 is controlled by the Lamp pin output of the
MCCF33095 Flip-Chip for this application.
The MCCF33096 is made using Flip-Chip Technology and has solder bumps
attached. Flip-Chip Technology affords higher operating temperatures with
improved reliability. The Darlington Flip-Chip can be soldered directly to an
appropriate ceramic circuit board with substantial savings in space.
• High Reliability at Elevated Temperatures

DARLINGTON DRIVE
FLIP-CHIP
SILICON MONOLITHIC
INTEGRATED CIRCUIT

FLIP-CHIP CONFIGURATION

• Thermal Operation from -40° to + 170°C

Cl

B

,'.

-'.

y

y

• Solder Bumped for Flip-Chip Assembly

A

• Minimal Space Required

Mechanical Dimensions

1

... 0.131 Oia 4 Places
'I' 0.140
.
Cl

B

-+-1

C2

E

O.140
0.089

C!:

-t 1j

1.14 Square
1.19

'--'+-:~

r

I. .1

0.216
0.152
4 Edges

-'.

-'.

y

y

C2

E

(Backside View)
Back marking is array with arrow pointing
to side with Band Cl bumps

BUMP CONNECTIONS
Cl = 01 Collector

0.56
0.46

E = Emitter
B = Base

NOTE: All dimensions shown indicated in millimeters.

Block Diagram
C2

Simplified Block Diagram

rEt
l ___

Cl

0,

C2

r - - - - - - ---,

I
I ~O2
I
I
I
~
I
I ~
~ I
I
fR
I
I
IL _ _ _~
_ _ _ _ _ ..JI

Cl

I

~+B

I

B

J

ol

E

ORDERING INFORMATION

E
R= 200n±20%
NOTE: The emitter is connected to the substrate.

Device

Temperature
Range

Package

MCCF33096

-40° to +1lO°C

Flip-Chip

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
10-73

..
I

I

C2 = Q2 Collector

MCCF33096
MAXIMUM RATINGS
Symbol

Rating

Value

Unit

8.0

Grams/Bump

6.0
73

°CIW

Bump Shear Strength
Power Dissipation and Thermal Characteristics
Maximum Power @ TA = 25°C
Thermal Resistance, Junction-to-Substrate

TJS

W

Operating Junction Temperature

TJ

+170

°C

Ambient Temperature Range

TA

-40to+170

°C

ELECTRICAL CHARACTERISTICS (Limit values apply over - 40°C S TA S +150°C and typical values at TA = 25°C.)
Symbol

Min

Typ

Max

Unit

Saturation Voltage (IC2 = 350 rnA, IBI = 0.6 rnA)

VCE2(sat)

0

0.42

0.65

V

Breakdown Voltage (ICI = 1.0 rnA, VCl = VC2)

BVCER(sus)

80

-

-

V

Collector Cutoff Current (VCEI = 60 V = VCE2)

ICER

0.04

10

!lA

DC Current Gain
(VCEI = VCE2 = 1.0 V, IBI = 100 j.LA)
(IBI = 1.0 j.LA, VCE2 = 0 V, VCEI = 1.5 V)

HFEI
HFE2

1000
50

2100
61.3

3500
100

-

-

20

j.LS

toff

-

-

20

j.LS

VFDI
VFD2
VFD3

-1.5
-1.5
-1.5

-1.33
-1.33

-0.5
-0.5
-0.5

1.0

1.82

2.0

Characteristics

Turn ON Time

-10

ton

Turn OFF Time

-

V

Diode Forward Voltage
IDI =25mA
ID2 = 250 rnA
ID3=25 rnA
Emitter-Base ON Voltage (IC2 = 350 rnA, IBI = 0.6 rnA)

Figure

VBE(on)

V

1. Application Circuit (Integral Alternator Regulator System)

r---~----------~------------------------------~A

1

250n

0 047
.

r--~~----~S~------~------~+O

lOOk

I Vee1 - - - - -

3
Stator- -

0 022
.

I 9,
DDt----!:..

MCCF33095

~ OSC

50k

~~l-l!.:0,--'V30",k____-+----,

I

21

,----+--------"1 Sense
I

1

1.0k

18k

1. I

I
I
Gnd..JI

1 I 4----- --f-!

0.022

L

Ign

Lamp
5

~

A.O.

Power Ground

20k

Ion

1.0k

2.4k

Battery~

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

10-74

MOTOROLA

MC33192

SEMICONDUCTOR-----TECHNICAL DATA

Product Preview

MI-BUS INTERFACE
STEPPER MOTOR
CONTROLLER

MI-Bus Interface
Stepper Motor Controller

SILICON MONOLITHIC
INTEGRATED CIRCUIT

The MC33192 Stepper Motor Controller is intended to control loads in harsh
automotive environments using a serial communication bus. The MI-Bus can
provide satisfactory real time control of up to eight stepper motors. MI-Bus
technology offers a noise immune system solution for difficult applications
involving relay drivers, motor controllers, etc.
The MC33192 stepper motor controller provides four phase signals to drive two
phase motors in either half or full step modes. When used with an appropriate
Motorola HCMOS microprocessor it offers an economical solution for applications
requiring a minimum amount of wiring while allowing a versatile system. The
MC33192 is packaged in an economical 16 pin SOIC and specified at an
operating voltage of 12 V for - 40°C :,; TA :,; 100°C.
• Single Wire Open Bus Capability Up to 10 Meters in Length
• Programmable Address Bus System
• Fault Detection of Half-Bridge Drivers and Motor Windings
• Ceramic Resonator for Accurate and Reliable Transmission of Data

DWSUFFIX
PLASTIC PACKAGE
CASE 751G

• Sub-Multiple of Oscillator End-of-Frame Signal
• MI-Bus Signal Slew Rate Limited to 1.0 V/IlS for Minimum RFI

(SO-lSL)

• MI-Bus Error Diagnostics
• Non-Functioning Device Diagnostics
• Over Temperature Detection
• Address Programming Sequence Status
• Load and Double Battery (Jump Start) Protection

PIN CONNECTIONS

o

Ground
Ground

MI-Bus Stepper Motor Controller Application

Ground
Ground
+Vbat

Ground
Ground

Vee

A1

Ground

A2
MI
MC33192DW

To

Other
Devices

8

Ground

B1

[Top View)

B2
Xlal
Gnd
Ground

Ceramic
Resonator
MI·Bus

FromMCU
MI·Bus

ORDERING INFORMATION
Device

Temperature
Range

Package

MC33192DW

- 40° to +100°C

SO-lSL

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
10-75

MOTOROLA

MC33293

SEMICONDUCTOR-----TECHNICAL DATA

Product Preview

Quad Low Side Driver

QUAD LOW SIDE DRIVER

The MC33293 is a single monolithic integrated circuit specifically designed
for quad low side switching applications. This device was initially conceived as
a quad injector driver to operate in harsh automotive environments but is well
suited for many other applications. The MC33293 incorporates SMARTMOS'M
technology having CMOS logic, Bipolar/CMOS analog circuitry, and DMOS
power FETs. All of the device inputs are CMOS compatible. A Fault output is
provided to "flag" the existence of open loads (outputs ON or OFF), shorted
loads, and over temperature condition of any output. A shorted load fault
condition will shut off only the specific output involved while allowing the other
outputs to operate normally. An overvoltage (VPWR) condition will shut off all
outputs for the overvoltage duration. All outputs are independent in operation
and have internal clamp diode protection for switching inductive loads.
A Single/Dual Select pin is incorporated to allow either independent
input/output operation or output pair operation. The MC33293 is parametrically
specified over- 40°C ::;TA::; +125°C ambient temperature and 9.0 V ~ VPWR
::; 16 V supply.
• Designed to Operate with Supply Voltages of 5.5 V to 26.5 V
• CMOS Compatible Inputs with Active Internal Pull-Downs
• Maximum 7.0 mA Quiescent Current
• Output rDS(on) of 0.25 n Maximum with VPWR ::; 9.0 V
• Outputs Internally Clamped to 65 V for Driving Inductive Loads
• Output Current Limiting of 3.0 A to Accommodate Incandescent Lamp
Loads
• Output Fault Status with Interrogation Capability
• Open Load Detection (Output ON or OFF)
• Short Circuit Detection/Shutdown and Overvoltage Detection/Shutdown
• Short Fault Shutdown and Automatic Retry
• Reverse Battery Protection
• 2000 V Minimum ESD Protection (Human Body Model)

(rDS(on)

SILICON MONOLITHIC
INTEGRATED CIRCUIT

TSUFFIX
PLASTIC PACKAGE
CASE 821C
(15 Pin SIP)

PIN CONNECTIONS
PIN 1.
2.
3.
4.
5.
6.
7.

Output2
Output 1
Input 1
Input 2
Input 1 + 2
Single/Dual Select
VpWR
8. Ground
9. N.C.
10. Fault
11.lnput3+4
12. Input 4
13. Input 3
14. Output 3
15. Output 4

Simplified Block Diagram
+VPWR

<>-t---r-----------,

..-----1c-----1h

I 1 (Output 1)

I-" (Output 2)

1..1;

115 (Output 3)

I-" (Output4)
I
I
I
I
I
L ____________
__
_____ J
From_
Detectors
2,3,4

ORDERING INFORMATION
Device
MC33293T

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

10-76

= 0.25 n per Output)

Temperature
Range

Package
15 Pin SIP

MOTOROLA

MC33295

SEMICONDUCTOR-----TECHNICAL DATA

Product Preview
QUAD LOW SIDE DRIVER

Quad Low Side Driver
The MC33295 is a single monolithic integrated circuit specifically designed for
quad low side switching applications. This device was initially conceived as a
quad injector driver to operate in harsh automotive environments but is well suited
for many other applications. The MC33295 incorporates SMARTM05'M
technology having CMOS logic, Bipolar/CMOS analog circuitry, and DMOS
power FETs. All of the device inputs are CMOS compatible. A Fault output is
provided to '1Iag" the existence of open loads (outputs ON or OFF), shorted loads,
over temperature condition of any output, and overvoltage condition. Shorted
load or over temperature fault conditions will shut off only the specific outputs
involved while allowing the other outputs to operate normally. An overvoltage
(VPWR) fault condition will shut off all outputs for the overvoltage duration. All
outputs are independent in operation and have internal clamp diode protection for
switching inductive loads. A Single/Dual Select pin is incorporated to allow either
independent inpuVoutput operation or output pair operation. The MC33295 is
parametrically specified over - 40°C $ TA $ +125°C ambient temperature and
5.5 V $ VPWR $14.5 V supply.

(rDS(on) = 0.7 Q per Output)
SILICON MONOLITHIC
INTEGRATED CIRCUIT

• Designed to Operate with Supply Voltage of 5.5 V to 26.5 V
• CMOS Compatible Inputs with Active Internal Pull-Downs
• Maximum 5.0 mA Quiescent Current
• Output rDS(on) of 0.7 n Maximum with VpWR $ 9.0 V
• Outputs Internally Clamped to 65 V for Driving Inductive Loads
• Output Current Limiting of 3.0 A to Accommodate Incandescent Lamp Loads

TSUFFIX
PLASTIC PACKAGE
CASE 821C
(15 Pin SIP)

• Output Fault Status with Interrogation Capability
• Open Load Detection (Output ON or OFF)
• Over Temperature Detection and Shutdown
• Short Circuit Detection/Shutdown and Overvoltage Detection/Shutdown
• Short Fault Shutdown and Automatic Retry

PIN CONNECTIONS

• Reverse Battery Protection
• 2000 V Minimum ESD Protection (Human Body Model)

PIN 1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.

Simplified Block Diagram
tVpwR

"""T"-,----------.,

2

,------.----1>--,

1 1 (Outpu11)

I-" (Oulput2)
~4

115 (Oulput3)

I-" (Outpu14)

Output 2
Output 1
Input 1
Input 2
Input 1 + 2
Single/Dual Select
VpWR
Ground
N.C.
Fault
Input 3 +4
Input4
Input3
Output 3
Output4

1
1

1
1
1
1
From_
Detectors
2.3,4
L ____________
__
_____

~

ORDERING INFORMATION
Device
MC33295T

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

10-77

Temperature
Range

Package

-400 to +125°C

15 Pin SIP

MC33298

MOTOROLA

SEMICONDUCTOR-----TECHNICAL DATA

Advance Information

OCTAL SERIAL SWITCH
(SPI INPUT/OUTPUT)

Octal Serial Switch with
SPI Input/Output
The MC33298 is an eight output low side power switch with 8 bit serial input
control. The MC33298 is a versatile circuit designed for automotive applications,
but is well suited for other environments. The MC33298 incorporates
SMARTMOSTM technology, with CMOS logic, bipolarlMOS analog circuitry, and
DMOS power MOSFETs. The MC33298 interfaces directly with a microcontroller
to control various inductive or incandescent loads. The circuit's innovative
monitoring and protection features are: very low standby current, cascadable fault
reporting, internal 65 V clamp on each output, output specific diagnostics, and
independent shutdown of outputs. The MC33298 is parametrically specified over
a temperature range of - 40°C:;; TA :;; +125°C ambient temperature and 9.0 V :;;
VPWR $16 V supply. The economical 20 pin DIP and SO-24 wide body surface
mount plastic packages make the MC33298 very cost effective.
• Designed to Operate Over Wide Supply Voltages of 5.5 V to 26.5 V
• Interfaces Directly to Microprocessor Using SPI Protocol
• SPI Communication for Control and Fault Reporting
• 8-Bit Serial 1/0 is CMOS Compatible
• 3.0 A Peak Current Outputs with Maximum rDS(ON) of 0.45 n at 25°C
• Outputs are Current Limited to 3.0 A to 6.0 A for Driving Incandescent
Lamp Loads
• Output Voltages Clamped to 65 V During Inductive Switching
• Maximum Sleep Current (lPWR) of 50 IJA with VDD :;; 2.0 V
• Maximum of 4.0 mA IDD During Operation
• Maximum of 2.0 mA IpWR During Operation with All Outputs ON
• Open Load Detection (Outputs OFF)
• Overvoltage Detection and Shutdown
• Each Output has Independent Over Temperature Detection and Shutdown
• Output Mode Programmable for Sustained Current Limit or Shutdown
• Short Circuit Detect and Shutdown with Automatic Retry for Every
Write Cycle
• Serial Operation Guaranteed to 2.0 MHz

Simplified Application Schematic
SFPD

L~

CSB

Micro·
controller
wHh Bus

VpwR

VDD

SCLI<

51

-------

-::::l
Yo
Yl

CMOS
Inpul
logic

CMOS
Serial Shift
Registers
and
latches

PSUFFIX
PLASTIC PACKAGE
CASE 738
DIP (16+2+2)

PIN CONNECTIONS
DIP
2
3
4
5
6

7
8
9
10
11
12
13
14
15
16

17
18
19
20

Y2
Y3

Reset

DWSUFFIX
PLASTIC PACKAGE
CASE 751E
SOP (16+4+4)L

Function
Oulput7
Output 6
SCLK
SI
Ground
Ground
Ground
Ground
SO
CSB
Output 5
Output 4
Output 3
Output 2
SFPD
VDD
Ground
Ground
Ground
Ground
VpWR
Reset
Output 1
Output 0

SOP-24L
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

ORDERING INFORMATION

SO

Device
MC33298P
." Gnd

MC33298DW

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

10-78

Temperature
Range
- 40° to +125°C

Package
DIP
SOP-24L

MC33298
Figure 1. Simplified Block Diagram
VpWR

__

~-L==~--~~- -~------------------I

Bias
65V

VDDO!------i
SFPD o-t-~--t~

Gate
Gates
l ___-"""t----. To1-7

~
I
f.o
I

Outputs t -7

r<'

Fault
Timers

CSB

OulpulO

Lo
I
to

k

I

to

I
I

SCLK 0+---,-;---------'
Short
CircuH
Detect

SI <>+_._,-------'
Serial 0/0
SOot----j Une Driver

Over
Temperature
Detect

~ I
I
I
IL _____________________________________
From Detectors 1 to 7
I
~

FAULT OPERATION
SERIAL OUTPUT (SO) PIN REPORTS
Overvoltage

Overvoltage condition reported

Over Temperature

Fault reported by Serial Output (SO) pin

Over Current

SO pin reports short 10 battery/supply or over current condition

Output ON, Open Load Fault

Not reported

Output OFF, Open Load Fault

SO pin reports output OFF open load condition

DEVICE SHUTDOWNS
Overvoltage

Tolal device shutdown at VpWR = 28 V to 34 V. Re-operates when overvoltage is removed with
all outputs assuming an off state upon recovery from overvoltage. All device registers are
automatically reset (cleared) during shutdown.

Over Temperature

Only the output experiencing an over temperature shuts down.

Over Current

Only the output experiencing an over current condition shuts down at 3.0 A to 6.0 A after a
25!J.S to 100 !J.S delay, with SFPD pin grounded. All outputs will continue to operate in a current limit
mode, with no shutdown, if the SPFD pin is at 5.0 V.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

10-79

MC33298
MAXIMUM RATINGS (All voltages are with respect to ground, unless otherwise noted.)
Rating

Symbol

Value

Unit

Power Supply Voltage
Steady-State
Transient Conditions (Note1)

VPWR(sus)
VPWR(pk)

-1.5 to 26.5
-13 to 60

V
V

Logic Supply Voltage (Note 2)

VDD

-0.3 to 7.0

V

Yin

-0.3 to 7.0

V

Input Pin Voltage (Note 3)
Output Clamp Voltage (Note 4)
(lout = 2.0 mAl
(lout = 0.5 A)

V

Vout(off)
50 to 75
55 to 75

Output Self-Limit Current

10ut(UM)

3.0 to 6.0

A

Continuous Per Output Current (Note 5)

lout(cont)

0.5

A

VESD1
VESD2

2000
200

V
V

100
30

mJ
mJ

2.0
0.5

J
J

ESDVoltage
Human Body Model (Note 6)
Machine Model (Note 7)
Output Clamp Energy (Note 8)
Repetitive:
TJ = 25°C
TJ = 125°C
Non-Repetitive:
TJ = 25°C
TJ = 125°C

Eclamp

Recommended Frequency of SPI Operation (Note 9)

fSPI

2.0

MHz

Storage Temperature

Tstg

-55to+150

°c

Operating Case Temperature

TC

-40 to +105

°c

Operating Junction Temperature

TJ

-40 to +150

°c

Power Dissipation (TA = 25°C) (Note 10)

Po

3.0

W

Soldering Temperature (for 10 seconds)

Tsolder

260

°C

Thermal Resistance (Junction-to-Ambient) (Note 11)
Plastic Package, Case 738:
All Outputs ON (Note 12)
Single Output ON (Note 13)
SOP-24 Package, Case 751 E:
All Outputs ON (Note 12)
Single Output (Note 3)

°CIW

0J-A
31
37
34
40

NOTES: I. Transient capability with external I 00 0 resis10r connected in series with VpWR pin and supply.
2. Exceeding these limits may cause a malfunction or pennanent damage to the device.
3. Exceeding voltage limits on SCLK, SI, CSB, SFPD, or Reset pins may cause pennanent damage to
the device.
4. With output OFF.
5. Per output continuous rating wilh all outputs ON and equally conducting current (See Figure 21 and 22
for more details).
6. ESDI testing is performed in accordance with the Human Body Model (CZap = 100 pF, RZap= 15000).
ESDI voltage capability of VpWR pin is > 1000 V; All other device pins are as indicated.
7. ESD2 testing is perfonned in accordance wilh the Machine Model (CZap = 100 pF, RZap = 0 0).
8. Maximum output clamp energy capability at Indicated Junction Temperature using single pulse method.
See Figure 19 for more details.
9. Guaranteed and production tes1ed for 2.0 MHz SPI operation but has been demonstrated to operate to
8.5 MHz @ 25°C.
10. Maximum power dissipation at indicated junction temperature with no heat sink used. See Figures 20, 21,
and 22 for more details.
I!. See Figure 20 iorThermal Model.
12. Thermal resistance from Junction-ta-Ambient wilh all outputs ON and dissipating equal power.
13. Thermal resistance from Junction-ta-Ambient with a single output ON.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

10-80

MC33298
STATIC ELECTRICAL CHARACTERISTICS
Characteristic
POWER INPUT
Supply Voltage Range
Quasi-Functional (Note 1)
Full Operational

V
VPWR(QF)
VPWR(FO)

Supply Current (all Outputs ON, lout ~ 0.5 A) (Note 2)

IpWR(SS)

-

10ut(SS)

-

IpWR(ON)

Sleep State Supply Current (VDD ~ 0.5 V)
Sleep State Output Leakage Current (per Output, VDD ~ 0.5 V)

5.5
9.0

-

-

9.0
26.5

1.0

2.0

1.0

50

Il A

-

50

!lA

rnA

VOV

28

-

36

V

VOV(hys)

0.2

-

1.5

V

Logic Supply Voltage

VDD

4.75

-

5.25

V

Logic Supply Current (with any combination of Outputs ON)

IDD

-

-

4.0

rnA

VDD(UVLO)

2.0

-

4.5

V

-

-

Overvoltage Shutdown
Overvoltage Shutdown Hysteresis

Logic Supply Undervoltage Lockout Threshold (Note 3)
POWER OUTPUT
Drain-to-Source ON Resistance (lout ~ 0.5 A, TJ ~ 25°C)

rDS(ON)

VPWR~5.5V

-

VPWR~9.0V

VpWR ~ 13 V
Drain-to-Source ON Resistance (Iout~ 0.5 A, T J ~ 150°C)

rDS(ON)

VPWR~5.5V
VPWR~9.0V
VPWR~13V

Output Self-Limiting Current
Outputs Programmed ON, Vout ~ 0.6 VDD

Q

0.4
0.35

1.0
0.5
0.45
Q

-

0.75
0.65

1.8
0.9
0.8

3.0

4.0

6.0

0.6

0.7

0.8

30

50

100

50
55

65

75
75

-50

0

50

Il A

-

A

10ut(Um)

Output Fault Detect Threshold (Note 4)
Output Programmed OFF

VDD

VoutTH(F)

Output OFF Open Load Detect Current (Note 5)
Output Programmed OFF, Vout ~ 0.6 VDD

lOCO

Output Clamp Voltage
lout~2.0 rnA
lout~ 0.2 A

VOK

Output Leakage Current (VDD S 2.0 V) (Note 6)

10ut(LKG)

Over Temperature Shutdown (Outputs OFF) (Note 7)
Over Temperature Shutdown Hysteresis (Note 7)

!lA
V

-

I

TUm

155

170

185

°c

TUm(hys)

-

10

20

°c

NOTES: 1. SPI inputs and outputs operational; Fault reporting may not be fully operational within this voltage range.
2. Value reflects normal operation (no faults) with all outputs ON. Each ON output contributes approximately 20 IIA to IpWR. Each output experiencing
a "soft short" condition contributes approximately 0.5 rnA to IpWR. A "soft short" is defined as any load current causing the output source current to
self-limit. A "hard" output short is a very low impedance short to supply.
3. For VDD less than the Undervoltage Lockout Threshold voltage, all data registers are reset and all outputs are disabled.
4. Output fault detect threshold with outputs programmed OFF. Output fault detect thresholds are the same for output opens and shorts.
5. Output OFF Open Load Detect Current is the current required to flow through the load for the purpose of detecting the existence of an
open condition when the specific output is commanded to be OFF.
6. Output leakage current measured with output OFF and at 16 V.
7. This parameter is guaranteed by design but is not production tested.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
10-81

III

MC33298
STATIC ELECTRICAL CHARACTERISTICS

(Characteristics noted under conditions of 4.75 V:s; Voo :s; 5.25 V, 9.0 V:s; VpWR
:s; 16 V, - 40°C :s; TC :s; 125°C, unless otherwise noted.)

I

Charactarlstlc

Symbol

I

I

Min

Typ

Max

Unit

DIGITAL INTERFACE
Input logic High Voltage (Note 1)

VIH

0.7

0.5

1.0

VOO

Input logic low Voltage (Note 2)

Vll

0.0

0.5

0.2

VOO

VI(hys)

50

100

500

mV

lin

-10

0

10

IlA

Reset Pull-Up Current (Reset = 0.7 VOO)

IRSTB

10

22

50

SFPO Pull-Oown Current (SFPO = 0.2 VOO)

ISFPO

10

22

50

IlA
IlA

= 1.0 rnA)
SO low State Output Voltage (IOl =-1.6 rnA)
SO Tri-State leakage Current (CSB = 0.7 VOO, 0 V:s; VSo:S; VOO)

VSOH

VOO-l.0 V

VOO-0.6V

-

V

VSOl

-

0.2

0.4

V

ISOT

-10

0

10

IlA

Cin

-

-

12

pF

CSOT

-

-

20

pF

Input logic Voltage Hysteresis (Note 3)
Input logic Current (Note 4)

SO High State Output Voltage (IOH

Input Capacitance (0 V :s; VOO :s; 5.25 V) (Note 5)
SO Tri-State Capacitance (0 V :s; VOO :s; 5.25 V) (Note 6)
NOTES: 1.
2.
3.
4.
5.
6.

Upper logic threshold voltage range applies to SI, cse, SCLK, Reset, and SFPO Input signals.
Lower logic threshold voltage range applies to SI, cse, SCLK, Reset, and SFPO input signals.
Only the SFPO and Reset inputs have hysteresis. This parameter is guaranteed by design but is not production tested.
Input current 01 SCLK, SI, and cse logic control inputs.
Input capacitance 01 SI, cse, SCLK, Reset, and SFPO lor 0 V S VOO S 5.25 V. This parameter is guaranteed by deSign, but Is not production tested.
Tri-state capecitance 01 SO lor a V s VOO ,; 5.25 V. This parameter is guaranteed by design but is not production tested.

Figure 2_ Input Timing Switch Characteristics

RSTB
~

~---------------------------VIH

O.2VOO -

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Vll

I----+l

IIwRSTB I
------------,

O.2V~OO------------------------/
r-------

CSB

I

1

CI

O.7VOO~-

I~SClKI!l
I

1

1

SCLK

1

O.2VOO

tslSU

o_on_~_car_e

_S_I_ _ _ _ _

~

-~---------VIH
1
"--------Vll

I!
r

I1

twSCLKl

i-!I tsl(hold)

_:'~-~i~
O.2VOO

1

V
Il

1

1

-1-

1
~

______

~

------i-

VIH

-V< Oon~Gare >GX__oo_n_~car_e
,....----

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

10-82

VIH

__ Vll

MC33298

DYNAMIC ELECTRICAL CHARACTERISTICS

(Characteristics noted under conditions of 4.75 V S VDD S 5.25 V, 9.0 V S VpWR
S 16 V, -40°C STC S 125°C, unless otherwise noted.)

I

Characteristic

Symbol

I

Min

I

Typ

Max

Unit

POWER OUTPUT TIMING
Output Rise Time (VPWR =13 V, RL =26 0) (Note 1)
Output Fall Time (VpWR =13 V, RL =26 0) (Note 1)

tr

1.0

1.5

20

liS

2.5

20

liS
liS

tf

1.0

Output Turn ON Delay Time (VpWR =13 V, RL =26 0) (Note 2)

tDLY(ON)

1.0

5.0

15

Output Turn OFF Delay Time (VPWR =13 V, RL =26 0) (Note 3)

tDLY(ofl)

1.0

5.0

15

Output Short Fault Disable Report Delay (Note 4)
SFPD =0.2 x VDD

tDLY(sf)

Output OFF Fault Report Delay (Note 5)
SFPD =0.2 x VDD

tDLY(ofl)

liS

!IS
25

50

100

25

50

100

liS

NOTES: 1. Output Rise and Fall time respectively measured across a 26 n resistive load at 10% to 90% and 90% to 10% voltage points.
2. Output Turn ON Delay time measured from riSing edge of CSB to 50% of output OFF Vout voltage with Rl = 26 n resistive load
(see Figure 7 and 8).
3. Output Turn OFF Delay time measured from riSing edge of CSB to 50% of output OFF Vout voltage with Rl = 26 n resistive load
(see Figure 7 and 8).
4. Output Short Fault Disable Report Delay measured from rising edge of CSB to lout =2.0 A point with output ON, Vout =5.0 V,
and SFPD = 0.2 x VDD (see Figure 9 and 10).
5. Output OFF Fault Report Delay measured from 50% points of rising edge of CSB to rising edge of output (see Figure 8).

DYNAMIC ELECTRICAL CHARACTERISTICS

(Characteristics noted under conditions of 4.75 V S VDD S 5.25 V, 9.0 V S VPWR
S 16 V, -40°C STC S 125°C, unless otherwise noted.)

I

Characteristic

Symbol

I

Min

I

Typ

Max

Unit

ns

DIGITAL INTERFACE TIMING
tpSCLK

500

SCLK Clock High Time

twSCLKH

250

-

SCLK Clock Low Time

twSCLKL

250

-

-

IwRSTB

250

50

-

ns

tlead

250

50

-

ns

tlag

250

50

-

ns

SI to Falling Edge of SCLK (Required Setup Time)

tSISU

125

25

tSI(hold)

125

25

-

ns

Falling Edge of SCLK to SI (Required Hold Time)

SCLK Clock Period

Required Low State Duration for Reset (VIL S 0.2 VDD) (Note 1)
Falling Edge of CSB to Rising Edge of SCLK (Required Setup Time)
Falling Edge of SCLK to Rising Edge of CSB (Required Setup Time)

ns
ns

ns

SO Rise Time (CL = 120 pF)

trSO

-

25

50

ns

SO Fall Time (CL = 120 pF)

tfSO

-

25

50

ns

SI, CSB, SCLK Incoming Signal Rise Time (Note 2)

trSI

ns

tfSI

-

200

SI, CSB, SCLK Incoming Signal Fall Time (Note 2)

-

200

ns

1s0(en)
tSO(dis)

-

-

-

200
200

-

50

125

ns

Time from Falling Edge of CSB to SO
Low Impedance (Note 3)
High Impedance (Note 4)
Time from Rising Edge of SCLK to SO Data Valid (Note 5)
0.2 VDD S SO  3.0 V), the output being controlled will be high and turned OFF.

Figure 11. MC33298 SPI System Daisy Chain
SCLI(

MC68XX
Microcontroller
SPI

SCLI(

CSB

1;~1
IRQ

MOSI

so

SI

MC33298

I

I

1

Parallel Port

~

SCLI(

CSB

t------ so

SI I - -

MC33298

SCLI(

CSB

so

SII--

MC33298

I

I

CSB

SCLK

so

SI

MC3329B

J-

;.

;.

J-

8 Outputs

8 Outputs

8 Outputs

8 Outputs

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
10-86

t----

MC33298
One main advantage of the MC33298 is the serial port
which when coupled to an MCU, receives ONIOFF commands from the MCU and in return transmits the drain status
of the device's output switches. Many devices can be "daisychained" together to form a larger system (see Figure 11).
Note in this example that only one dedicated MCU parallel
port (aside from the required SPI) is needed for chip select to
control 32 possible loads.
Multiple MC33298 devices can also be controlled in a parallel input fashion using SPI (see Figure 13). This figure
shows a possible 24 loads being controlled by only three dedicated parallel MCU ports used for chip select.

SPI System Attributes
The SPI system is flexible enough to communicate directly
with numerous standard peripherals and MCUs available
from Motorola and other semiconductor manufacturers. SPI
reduces the number of pins necessary for input/output (1/0)
on the MC33298. It also offers an easy means of expanding
the 1/0 function using few MCU pins. The SPI system of communication consists of the MCU transmitting, and in return,
receiving one databit of information per clock cycle.
Databits of information are simultaneously transmitted by
one pin, Microcontroller Out Serial In (MOSI), and received by
another pin, Microcontroller In Serial Out (MISO), of the MCU.
Some features of SPI are:
• Full Duplex, Three-Wire Synchronous Data Transfer

Figure 13. Parallel Input SPI Control

• Each Microcontroller can be a Master or a Slave
• Provides Write Collision Flag Protection

MC33298

MOSI

• Provides End of Message Interrupt Flag

SI

SCLK

SCLK

~ 8 Outputs

The only drawbacks to SPI are that an MCU is required for
efficient operational control and, in contrast to parallel input
control, is slower at performing pulse width modulating
(PWM) functions.

CSB

MC68XX
Microconttoller
SPI

MC33298
~ SI

SCLK

r---A' f -

I Parallel B
I
Ports C
L ___---'"' r -

• Four 1I0s associated with SPI (MOSI, MISO, SCLK, SS)

~ 8 Outputs

Figure 14. Multiple MCU SPI Control

CSB

MC33298
~

SI
SCLK

f--" 8 Outputs

MC68XX
Microcontroller
SPI
(Master)

r--X

I Parallel B r---L Ports gr---r--

CSB

Figure 14 shows a basic method of controlling multiple
MC33298 devices using two MCUs. A system can have only
one master MCU at any given instant of time and one or more
slave MCUs. The master MCU supplies the system clock signal (top MCU designated the master); the lower MCU being
the slave. It is possible to have a system with more than one
master but not at the same time. Only when the master is not
communicating can a slave communicate. MCU master control is switched through the use of the slave select (SS) pin of
the MCUs. A master will become a slave when it detects a
logic low state on its SS pin.
These basic examples make the MC33298 very attractive
for applications where a large number of loads need be controlled efficiently. The popular Synchronous Serial Peripheral
Interface (SPI) protocol is incorporated, to this end, to communicate efficiently with the MCU.

-SCLK
8-Bit MISO

I~

~MOSI

ss rMC68XX
Microcontroller
SPI
(SlaveL_

Ir.:::
Parallel A ILPort
--,,=
8.B·t SCLK
~MISO

I~

MOSI
SS I--

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
10-87

MC33298
CSB

f-'. 8 Outputs

~gLK8_Bit
SI

1

MC33298
CSB

f-'. 8 Outputs

SCLK 8 B'

SO~_
SI~

I

MC33298
CSB
SCLK
SO 8-Bit

SI~

f-'. 8 Outputs

MC33298
PIN FUNCTION DESCRIPTION
CSB Pin
The system MCU selects the MC33298 to be
communicated with through the use of the CSB pin.
Whenever the pin is in a logic low state, data can be
transferred from the MCU to the MC33298 and vise versa.
Clocked-in data from the MCU is transferred from the
MC33298 shift register and latched into the power outputs on
the rising edge of the CSB Signal. On the falling edge of the
CSB signal, drain status information is transferred from the
power outputs and loaded into the device's shift register. The
CSB pin also controls the output driver of the serial output pin.
Whenever the CSB pin goes to a logic low state, the SO pin
output driver is enabled allowing information to be transferred
from the MC33298 to the MCU. To avoid any spurious data, it
is essential that the high-to-Iow transition of the CSB signal
occur only when SCLK is in a logic low state.
SCLKPin
The system clock pin (SCLK) clocks the internal shift
registers of the MC33298. The serial input pin (SI) accepts
data into the input shift register on the falling edge of the
SCLK signal while the serial output pin (SO) shifts data
information out of the shift register on the rising edge of the
SCLK signal. False clocking of the shift register must be
avoided to guarantee validity of data. It is essential that the
SCLK pin be in a logic low state whenever chip select bar pin
(CSB) makes any transition. For this reason, it is
recommended though not necessary, that the SCLK pin be
kept in a low logic state as long as the device is not accessed
(CSB in logic high state). When CSB is in a logic high state,
any Signal at the SCLK and SI pin is ignored and SO is
tristated (high impedance). See the Data Transfer Timing
diagram of Figure 16.
SI Pin
This pin is for the input of serial instruction data. SI
information is read in on the falling edge of SCLK. A logic high
state present on this pin when the SCLK signal rises will
program a specific output OFF, and in turn, tums OFF the
specific output on the rising edge of the CSB signal.
Conversely, a logic low state present on the SI pin will
program the output ON, and in turn, turns ON the specific
output on the rising edge of the CSB signal. To program the
eight outputs of the MC33298 ON or OFF, an eight bit serial
stream of data is required to be entered into the SI pin starting
with Output 7, followed by Output 6, Output 5, etc., to Output
O. For each rise of the SCLK signal, with CSB held in a logic
low state, a databit instruction (ON or OFF) is loaded into the
shift register per the databit SI state. The shift register is full
after eight bits of information have been entered. To preserve
data integrity, care should be taken to not transition SI as
SCLK transitions from a low to high logic state.
SO Pin
The serial output (SO) pin is the tri-stateable output from
the shift register. The SO pin remains in a high impedance
state until the CSB pin goes to a logic low state. The SO data
reports the drain status, either high or low. The SO pin
changes state on the rising edge of SCLK and reads out on
the falling edge of SCLK. When an output is OFF and not
faulted, the corresponding SO databit is a high state. When
an output is ON, and there is no fault, the corresponding
databit on the SO pin will be a low logic state. The SI/SO
shifting of data follows a first-in-first-out protocol with both
input and output words transferring the Most Significant Bit

(MSB) first. The SO pin is not affected by the status of the
Reset pin.
Reset Pin
The MC33298 Reset pin is active low and used to clear the
SPI shift register and in doing so sets all output switches OFF.
With the device in a system with an MCU; upon initial system
power up, the MCU holds the Reset pin of the device in a
logic low state ensuring all outputs to be OFF until both the
VDD and VPWR pin voltages are adequate for predictable
operation. After the MC33298 is reset, the MCU is ready to
assert system control with all output switches initially OFF. If
the VPWR pin of the MC33298 experiences a low voltage,
following normal operation, the MCU should pull the Reset
pin low so as to shutdown the outputs and clear the input data
register. The Reset pin is active low and has an internal
pull-up incorporated to ensure operational predictability
should the external pull-up of the MCU open circuit. The
internal pull-up is only 20 IlA to afford safe and easy
interfacing to the MCU. The Reset pin of the MC33298 should
be pulled to a logic low state for a duration of at least 250 ns
to ensure reliable reset.
A simple power ON reset delay of the system can be
programmed through the use of an RC network comprised of
a shunt capacitor from the Reset pin to Ground and a resistor
to VDD (See Figure 15). Care should be exercised to ensure
proper discharge of the capacitor so as to not adversely delay
the reset nor damage the MCU should the MCU pull the
Reset line low and yet accomplish initialization for turn ON
delay. It may be easier to incorporate delay into the software
program and use a parallel port pin of the MCU to control the
MC33298 Reset pin.
Figure 15. Power ON Reset

VOO

1-----"1
I +
I
I
I
I
I

1 ___ '
ROLY
I
201lA
I
II MCU IIC-O--+-----O-+Reset
Reset
I
I
1----'
.T
L___ .J
- COLY
I
I
MC33298 ~I
IL _____
SFPD Pin
The Short Fault Protect Disable (SFPD) pin is used to
disable the over current latch-OFF. This feature allows control
of incandescent loads where in-rush currents exceed the
device's analog current limits. Essentially the SFPD pin
determines whether the MC33298 output(s) will instantly shut
down upon sensing an output short or remain ON in a current
limiting mode of operation until the output short is removed or
thermal shutdown is reached. If the SFPD pin is tied to VDD =
5.0 V the MC33298 output(s) will remain ON in a current
limited mode of operation upon encountering a load short to
supply. If the SFPD pin is grounded, a short circuit will
immediately shut down only the output affected. Other
outputs not having a fault condition will operate normally. The
short circuit operation is addressed in more detail later.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
10-88

Figure 16. Data Transfer Timing

,
C5B

5CLK

s:

0
-t
0
:0
0

51

r
»
r

Z

s:
o

m

»

~

Z
0

OJ
CO

CtJ
CtJ

Output 7

-t

N

m

:0

~
m

()

Old Data '

New Data D07

Old Data ,

New Data DOO

OutpulO

(5
C/l

0

m

<

(5

m

0

~
»

NOTES:l.
2.
3.
4.
5.

Reset pin is in a logic high state during the above operation.
DO. Dl. D2 •...• and D15 relate to the ordered entry of program data into the MC33298 with DO/D8 bits (MSB) corresponding to Output 7 and D7/D15 corresponding to Output O.
DO". Dl". D2" •...• and D7" relate to the ordered data out of the MC33298 with DO' bit (MSB) corresponding to Output 7.
OD" corresponds to Old Databits.
For brevity. only D07 and DOO are shown which respectively correspond to Output 7 and Output O.

Data Transfer Timing (General)

CSB High-to-Low

SO pin is enabled. Output Status information transferred to Output Shift Register.

CSB Low-to-High

Data from the Shift Register is transferred to the Output Power Switches

SO

Will change state on the rising edge of the SCLK pin signal.

SI

Will accept data on the falling edge of the SCLK pin signal.

I

CD

CO

MC33298
Power Consumption
The MC33298P has extremely low power consumption in
both the operating and standby modes. In the standby or
"sleep" mode, with VDD ~ 2.0 V, the current consumed by the
VPWR pin is less than 50 1lA. In the operating mode, the
current drawn by the VDD pin is less than 4.0 rnA (1.0 rnA
typical) while the current drawn at the VPWR pin is 2.0 rnA
maximum (1.0 rnA typical). During normal operation, turning
outputs ON increases IpWR by only 20 IlA per output. Each
output experiencing a ·soft short" (overcurrent conditions just
under the current limit), adds 0.5 rnA to the IpWR current.
Paralleling of Outputs
Using MOSFETs as output switches allows the connection
of any combination of outputs together. MOSFETs have an
inherent positive temperature coefficient thermal feedback
which modulates rDS(ON) providing balanced current sharing
between outputs wIthout destructive operation (bipolar
outputs could not be paralleled in this fashion as thermal
run-away would likely occur). The device can even be
operated with all outputs tied together. This mode of
operation may be desirable in the event the application

requires lower power dissipation or the added capability of
switching higher currents. Performance of parallel operation
results in a corresponding decrease in rDS(ON) while the
Output Off Open Load Detect Currents and the Output
Current Limits increase correspondingly (by a factor of eight if
all outputs are paralleled). Less than 56 mQ rDSION) with
current limiting of 24 to 48 A will result if all outputs are
paralleled together. There will be no change in the
Overvoltage detect or the OFF Output Threshold Voltage
Range. The advantage of paralleling outputs within the same
MC33298 affords the existence of minimal rDS(ON) and output
clamp voltage variation between outputs. Typically, the
variation of rDS(ONl between outputs of the same device is
less than is 0.5%. The variation in clamp voltages (which
could affect dynamic current sharing) is less than 5%.
Paralleling outputs from two or more devices is possible but
not recommended. This is because there is no guarantee that
the rDS(ON) and clamp voltage of the two devices will match.
System level thermal design analYSis and verification should
be conducted whenever paralleling outputs.

FAULT LOGIC OPERATION
General
The MCU can perform a parity check of the fault logic
operation by comparing the command 8-bit word to the status
8-bit word. Assume that after system reset, the MCU first
sends an 8-bit command word, Command Word I, to the
MC33298. Each output that is to be turned ON will have its
corresponding databit low. Refer to the Data Transfer Timing
diagram of Figure 16. As this word, Command Word I, is
being written into the shift register of the MC33298, a status
word is being Simultaneously written out and received by the
MCU. However, the word being received by the MCU is the
status of the previous write word to the MC33298, Status
Word O. If the command word of the MCU is written a second
time (Command Word 2 = Command Word I), the word
received by the MCU, Status Word 2, is the status of
Command Word 1. The timing diagram shown in Figure 16
depicts this operation. Status Word 2 is then compared with
Command Word 1. The MCU will Exclusive or Status Word 2
with Command Word 1 to determine if the two words are
identical. If the two words are identical, no faults exist. The
timing between the two write words must be greater than
100 I1s to receive proper drain status. The system databus
integrity may be tested by writing two like words to the
MC33298 within a few microseconds of each other.
Initial System Setup Timing
The MCU can monitor two kinds of faults:
(1) Communication errors on the data bus and
(2) Actual faults of the output loads.
After initial system start up or reset, the MCU will write one
word to the MC33298. If the word is repeated within a few
microseconds (say 5) of the first word, the word received by
the MCU, at the end of the repeated word, serves as a
confirmation of data bus integrity (1). At startup, the MC33298
will take 25 to 100 I1S before a repeat of the first word can give
the actual status of the outputs. Therefore, the first word
should be repeated at least 100 I1s later to verify the status of
the outputs.
The SO of the MC33298 will indicate anyone of four faults.
The four possible faults are Over Temperature, Output Off

Open Fault, Short Fault (overcurrent), and VPWR Overvoltage
Fault. All of these faults, with the exception of the Overvoltage
Fault, are output specific. Over Temperature Detect, Output
Off Open Detect, and Output Short Detect are dedicated to
each output separately such that the outputs are
independent in operation. A VPWR Overvoltage Detect is of a
"global" nature causing all outputs to be turned OFF.
Over Temperature Fault
Patent pending Over Temperature Detect and shutdown
circuits are specifically incorporated for each individual
output. The shutdown that follows an Over Temperature
condition is independent of the system clock or any other
logic signal. Each independent output shuts down at 155°C
to 185°C. When an output shuts down due to an Over
Temperature Fault, no other outputs are affected. The MCU
recognizes the fault since the output was commanded to be
ON and the status word indicates that it is OFF. A maximum
hysteresis of 20°C ensures an adequate time delay between
output tum OFF and recovery. This avoids a very rapid turn
ON and turn OFF of the device around the Over Temperature
threshold. When the temperature falls below the recovery
level for the Over Temperature Fault, the device will turn ON
only if the Command Word during the next write cycle
indicates the output should be turned ON.
Overvoltage Fault
An Overvoltage condition on the VPWR pin will cause the
MC33298 to shut down all outputs until the overvoltage
condition is removed and the device is re-programmed by the
SPI. The overvoltage threshold on the VPWR pin is specified
as 28 V to 34 V with 1.0 V typical hysteresis. Following the
overvoltage condition, the next write cycle sends the SO pin
the hexadecimal word $FF (all ones) indicating all outputs are
turned OFF. In this way, potentially dangerous timing
problems are avoided and the MCU reset routine ensures an
orderly startup of the loads. The MC33298 does not detect an
overvoltage on the VDD pin. Other external circuitry, such as
the Motorola MC33161 Universal Voltage Monitor, is
necessary to accomplish this function.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
10-90

MC33298
Output Off Open Load Fault
An Output Off Open Load Fault is the detection and reporting of an "open" load when the corresponding output is disabled (input in a logic high state). To understand the operation of the Open Load Fault detect circuit, see Figure 17. The
Output Off Open Load Fault is detected by comparing the
drain voltage of the specific MOSFET output to an internally
generated reference. Each output has one dedicated
comparator for this purpose.
Figure 17. Output OFF Open Load Detect
VPWR

Output

An Output Off Open Load Fault is indicated when the output voltage is less than the Output Threshold Voltage (VThres)
of 0.6 to 0.8 x VDD. Since the MC33298 outputs function as
switches, during normal operation, each MOSFET output
should either be completely turned ON or OFF. By design the
threshold voltage was selected to be between the ON and
OFF voltage of the MOSFET. During normal operation, the
ON state VDS voltage of the MOSFET is less than the threshold voltage and the OFF state VDS voltage is greater than the
threshold voltage. This design approach affords using the
same threshold comparator for Output Open Load Detect in
the OFF state and Short Circuit Detect in the ON state. See
Figure 18 for an understanding of the Short Circuit Detect circuit. With VDD ~ 5.0 V, an OFF state output voltage of less
than 3.0 V will be detected as an Output Off Open Load Fault
while voltages greater than 4.0 V will not be detected as a
fault.
The MC33298 has an internal pull-down current source of
50 IlA, as shown in Figure 17, between the MOSFET drain
and ground. This prevents the output from floating up to
VPWR if there is an open load or internal wirebond failure. The
internal comparator compares the drain voltage with a reference voltage, VThres (0.6 to 0.8x VDD). If the output voltage is
less than this reference voltage, the MC33298 will declare the
condition to be an open load fault.
During steady-state operation, the minimum load resistance (RL) needed to prevent false fault reporting during normal operation can be found as follows:
VPWR ~ 9.0 V (min)
ILCO ~ 50 IlA
VThres (max) ~ (0.8 • 5.25)V

~

4.2 V

Therefore, the load resistance necessary to prevent false
open load fault reporting is (using Ohm's Law) equal to
96 kQ or less.

During output switching, especially with capacitive loads,
a false Output Off Open Load Fault may be triggered. To
prevent this false fault from being reported an internal fault
filter of 25 to 100 Ils is incorporated. The duration for which
a false fault may be reported is a function of the load impedance (RL, CL, LL), rDS(ON), and Cout of the MOSFET as well
as the supply voltage, VPWR. The rising edge of CSB triggers a built in fault delay timer which must time out (25
to 100 Ils) before the fault comparator is enabled to detect a
faulted threshold. The circuit automatically returns to normal
operation once the condition causing the Open Load Fault
is removed.
Shorted Load Fault
A shorted load (overcurrent) fault can be caused by any
output being shorted directly to supply, or an output experiencing a current greater than the current limit.
There are three safety circuits progressively in operation
during load short conditions which afford system protection:
1) The device's output current is monitored in an analog fashion using a SENSEFETTM approach and limited; 2) The device's output current limit threshold is sensed by monitoring
the MOSFET drain voltage; and 3) The device's output thermal limit is sensed and when attained causes only the specific faulted output to be latched OFF, allowing remaining outputs to operate normally. All three protection mechanisms are
incorporated in each output affording robust independent output operation.
The analog current limit circuit is always active and monitors the output drain current. An overcurrent condition causes
the gate control circuitry to reduce the gate to source voltage
imposed on the output MOSFET which re-establishes the
load current in compliance with current limit (3.0 to 6.0 A)
range. The time required for the current limit circuitry to act is
less than 20 Ils. Therefore, currents higher than 3.0 to 6.0 A
will never be seen for more than 20 Ils (a typical duration is 10
Ils). If the current of an output attempts to exceed the predetermined limit of 3.0 to 6.0 A (4.0 A nominal), the VDS voltage
will exceed the VThres voltage and the overcurrent comparator will be tripped as shown in Figure 18.
Figure 18. Short Circuit Delect and Analog
Current limiting Circuit

r ----------------i
MC33298
I

I

High = Fault

I
I

Output

I
I
I

I

I
I
I
I
I

RL

I

Vref

IL ________________ I

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

10-91

I

~

MC33298
The status of SFPD will determine whether the MC33298
will shut down or continue to operate in an analog current limited mode until either the short circuit is removed or thermal
shutdown is reached.
Grounding the SFPD pin will enable the short fault protection shutdown circuitry. Consider a load short (output short to
supply) occurring on an output before, during, and after output turn ON. When the CSB Signal rises to the high logic
state, the corresponding output is turned ON and a delay timer activated. The duration of the delay timer is 25 to 100 !J.s. If
the short circuit takes place before the output is turned ON,
the delay experienced is the entire 25 to 100 !J.s followed by
shutdown. If the short occurs during the delay time, the shutdown still occurs after the delay time has elapsed. If the short
circuit occurs after the delay time, shut- down is immediate
(within 20 !J.s after sensing). The purpose of the delay timer is
to prevent false faults from being reported when switching capacitive loads.
If the SFPD pin is at 5.0 V (or VDD), an output will not be
disabled when overcurrent is detected. The specific output
will, within 5.0 to 10 !J.s of encountering the short circuit, go
into an analog current limited mode. This feature is especially useful when switching incandescent lamp loads, where
high in-rush currents experienced during startup last for
10 to 20 ms.
Each output of the MC33298 has its own overcurrent shutdown circuitry. Over temperature faults and the overvoltage
faults are not affected by the SFPD pin.
Both load current sensing and output voltage sensing are
incorporated for Short Fault detection with actual detection
occurring slightly after the onset of current limit. The current
limit circuitry incorporates a SENSEFE"fTM approach to measure the total drain current. This calls for the current through
a small number of cells in the power MOSFET to be measured and the result multiplied by a constant to give the total
current. Whereas output shutdown circuitry measures the
drain to source voltage and shuts down if a threshold (VThres)
is exceeded.
Short Fault detection is accomplished by sensing the output voltage and comparing it to VThres. The lowest VThres requires a voltage of 0.6 times 4.75 V (the minimum VDD voltage) or 2.85 V to be sensed. For an enabled output, with VDD
= 5.0 ± 0.25 V, an output voltage in excess of 4.2 V will be detected as a "short" while voltages less than 2.85 V will not be
detected as "shorts."
Over Current Recovery
If the SFPD pin is in a high logic state, the circuit returns to
normal operation automatically after the short circuit is removed (unless thermal shutdown has occurred).
If the SFPD pin is grounded and overcurrent shutdown occurs; removal of the short circuit will result in the output remaining OFF until the next write cycle. If the short circuit is not
removed, the output will turn ON for the delay time (25 to 100
!J.s) and then turn OFF for every write cycle commanding a
turn ON.
SFPD Pin Voltage Selection
Since the voltage condition of the SFPD pin controls the
activation of the short fault protection (i.e. shutdown) mode
equally for all eight outputs, the load having the longest

duration of in-rush current determines what voltage (state)
the SFPD pin should be at. Usually if at least one load is, say
an incandescent lamp, the in-rush current on that input will be
milliseconds in duration. Therefore, setting SFPD at 5.0 V will
prevent shutdown of the output due to the in-rush current.
The system relies only on the Over Temperature Shutdown to
protect the outputs and the loads. The MC33298 was
designed to switch GE194 incandescent lamps with the
SFPD pin in a grounded state. Considerably larger lamps can
be switched with the SFPD pin held in a high logic state.
Sometimes both a delay period greater than 25 to 100 !J.s
(current limiting of the output) followed by an immediate over
current shutdown is necessary. This can be accomplished
by programming the SFPD pin to 5.0 V for the extended
delay period to afford the outputs to remain ON in a current
limited mode and then grounding it to accomplish the immediate shutdown after some period of time. Additional external circuitry is required to implement this type of function.
An MCU parallel output port can be devoted to controlling
the SFPD voltage during and after the delay period, is often
a much beller method. In either case, care should be taken
to execute the SFPD start-up routine every time start-up or
reset occurs.
Undervoltage Shutdown
An undervoltage VDD condition will result in the global
shutdown of all outputs. The undervoltage threshold is between 2.5 V and 4.5 V. When VDD goes below the threshold,
all outputs are turned OFF and the SO register is reset to indicate the same.
. An undervoltage condition at the VPWR pin will not cause
output shutdown and reset. When VPWR is between 5.5 V
and 9.0 V, the outputs will operate per the command word.
However, the status as reported by the serial output (SO) pin
may not be accurate. Proper operation at VPWR voltages below 5.5 V cannot be guaranteed.
Deciphering Fault Type
The MC33298 SO pin can be used to understand what
kind of system fault has occurred. With eight outputs having
open load, over current and over temperature faults, a total of
25 different faults are possible. The SO status word received
by the MCU will be compared with the word sent to the
MC33298 during the previous write cycle. If the two words are
not the same, then the MCU should be programmed to determine which output or outputs are indicating faults. If the command bit for any of the output switches indicating a fault is
high, the fault is an open load.
The eight open load faults are therefore the ones most
easily detected. Over current and over temperature faults are
often related. Turning the affected output switches OFF and
waiting for some time should make these faults go away.
Over current and over temperature faults can not be differentiated in normal application usage.
One advantage of the synchronous serial output is that
multiple faults can be detected with only one pin (SO) being
used for fault status indication.
If VPWR experiences an overvoltage condition, all outputs
will immediately be turned OFF and remain latched OFF. A
new command word is required to turn the outputs back ON
following an overvoltage condition.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

10-92

MC33298
Output Voltage Clamping
Each output of the MC3329B incorporates an internal
voltage clamp to provide fast turn-off and transient protection
of the output. Each clamp independently limits the drain to
source voltage to 65 V at drain currents of 0.5 A and keeps
the output transistors from avalanching by causing the
transient energy to be dissipated in the linear mode (see
Figure 19). The total energy (EJ) can be calculated by
multiplying the current area under the current curve (lA)
during the time the clamp is active and the clamp voltage

Figure 19. Output Voltage Clamping

Drain Voltage
Drain Current
(10 = O.SA) - - " " T h

(VcU·
Characterization of the output clamps, using a single pulse
repetitive method at 0.5 A, indicate the maximum energy to
be 100 mJ at 25°C and 25 mJ at 125°C per output. Using a
single pulse non-repetitive method at 0.5 A the clamps are
capable of 2.0 Joules at 25°C and 0.5 Joules at 125°C.

L--_ _ _

Drain·to·Source ON
Voltage (VDS(ON))
Gnd

==c...:.___

-"~

____

VpWR
TIme

THERMAL CHARACTERIZATION
Thermal Model
Logic functions take up a very small area of the die and
generate negligible power. In contrast, the output transistors
take up most of the die area and are the primary contributors
of power generation. The thermal model shown in Figure 20
was developed for the MC3329B mounted on a typical PC
board. The model is accurate for both steady state and
transient thermal conditions. The components RdO, Rdl,
Rd2, ... , and Rd7 represent the steady state thermal
resistance of the silicon die for transistor outputs 0, 1, 2, ... ,
and 7, while CdO, Cdl, Cd2, ... , and Cd7 represent the
corresponding thermal capacitance of the silicon die
transistor outputs and plastic. The device area and die
thickness determine the values of these specific
components.
The thermal impedance of the package from the internal
mounting flag to the outside environment is represented by
the terms Rllkg and Cpkg. The steady state thermal resistance
of leads and tile PC board make up the steady state package
thermal resistance, Rrkg . The thermal capacitance of the
package is made up 0 the combined capacitance of the flag
and the PC board. The mold compound was not modeled as
a specific component but is factored into the other overall
component values.
The battery voltage in the thermal model represents the
ambient temperature the device and PC board are subjected
to. The IPWR current source represents the total power
dissipation and is calculated by adding up the power
dissipation of each individual output transistor. This is easily
done by knowing rDS(ON) and load current of the individual
outputs.
Very satisfactory steady state and transient results have
been experienced with this thermal model. Tests indicate the
model accuracy to have less than 10% error. Output
interaction with an adjacent output is thought to be the main
contributor to the thermal inaccuracy. Tests indicate little or
no detectable thermal affects caused by distant output
transistors which are isolated by one or more other outputs.
Tests were conducted with the device mounted on a typical
PC board placed horizontally in a 33 cubic inch still air
enclosure. The PC board was made of FR4 material
measuring 2.5" by 2.5", having double-sided circuit traces of
1.0 oz. copper soldered to each device pin. The board
temperature was measured with thermal couple soldered to
the board surface one inch away from the center of the

device. The ambient temperature of the enclosure was
measured with a second thermal couple located over the
center and one inch distant from device.
Thermal Performance
Figure 20 shows the worst case thermal component
parameters values for the MC3329B in the 20 pin plastic
power DIP and the SOP-24 wide body surface mount
package. The power DIP package has Pins 5, 6,15, and 16
connected directly to the lead frame flag. The parameter
values indicated take into account adjacent output cell
thermal pulling effects as well as different output
combinations. The characterization was conducted over
power dissipation levels of 0.7 to 17 W. The
junction-to-ambient temperature thermal resistance was
found to be 37°CIW with a single output active (31 °CIW with
all outputs dissipating equal power) and in conjunction with
this, the thermal resistance from junction to PC board
(Rjunction-board) was foundto be 27°C/W (board temperature,
measured 1" from device center). In addition, the thermal
resistance from junction-to-heatsink lead was found to
approximate 10°C/W. Devoting additional PC board metal
around the heatsinking pins improved Rpkg from 30° to
2BoC/W.
The SOP-24 package has Pins 5,6,7, B, 17, lB, 19, and
20 01 the package connected directly to the lead frame flag.
Characterization was conducted in the same manner as for
the DIP package. The junction-to-ambient temperature
resistance was found to be 40°C/W with a single output active
(34°C/W with all outputs dissipating equal power) and the
thermalresistancefromjunction-to-PCboard(Rjunction_board)
to be 30°C/W (board temperature, measured 1" from device
center). The junction-to-heatsink lead resistance was found
again to approximate 10°CIW. Devoting additional PC board
metal around the heatsinking pins for this package improved
the Rpkg from 33° to 31 °CIW.
The total power dissipation available is dependent on the
number of outputs enabled at anyone time. At 25°C the
rDS(ON) is 450 ma with a coefficient of 6500 ppm/oC. For the
junction temperature to remain below 150°C, the maximum
available power dissipation must decrease as the ambient
temperature increases. Figures 21 and 22 depict the per
output limit of current at ambient temperatures necessary for
the plastic DIP and SOP packages respectively when one,
four, or eight outputs are enabled ON. Figure 23 depicts how
the rDS(ON) output value is affected by junction temperature.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

10-93

MC33298
Figure 20. Thermal Model (Electrical Equivalent)
Junction Temperature Node
VD=TD (OC)
(Volts represent Die Surface Temperature)
Output 1

Output 0

Output 2

Output 6

Cd2 - - - - - - - - -

•

IPWR (Steady State or Transient)
(1.0 A= 1.0 W01 Device Power Dissipation)

Cpkg = Coag + CpC Board

Rpkg = Rleads + Rpc Board

Rdx
(0)'

Cdx

Package

(F)'

Rpkg
(0)"

Cpkg
(F)'

20 Pin DIP

7.0

0.002

30

0.2

SOP-24L

7.0

0.002

33

0.15

•0

±

=°Cfw, F = W sl"C, IpWR = W, and VA =°c

5

Figure 21. Maximum DIP Package Steady State
Output Current versus Ambient Temperature
3.0 r----,---,-,--,---,-----,---,--,

!5O

2.5 ..........00;:::1----11----11---1-

ffi~

2.0

~

1.5

g

i

Ambient lilmperature Node
VA=TA(OC)
(1.0 V = 1°C Ambient Temperature)

1.0

! 0.:

rDS(ON) @ 150°C = 0.8 n
TJ = 150°C

1-t-;;;;;;;;t:::::E:::r;;;;;;::j:::::J-=:!I~=-1

-5~0--~--~0---25~--5~0--~~--~10-0--~--~15O

o

25
50
75
100
TA, AMBIENTlEMPERATURE (0C)

TA, AMBIENTTEMPERATURE (0C)

Figure 23. Maximum Output ON Resistance
versus Junction Temperature
0.9
~

0.8 -

~

0.7

V~R=I~V
VDD=5.0V
101 =0.5A

./

ffi

a: 0.6

V

is

~ 0.5

5

0.4

0.3
0.2
-50

./

V'
./

:F

j

./

"

./'"

-25

0

25

50

75

100

125

150

TJ, JUNCTION lEMPERATURE (OC)

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
10-94

125

150

MC33298
Latch-Up Immunity
Device latch-up caused by substrate injection has been
characterized. Latch-up immunity has both a DC and a
transient immunity component. DC latch-up immunity results
indicate the device to be capable of withstanding in excess of
four amps of reverse current out of any of the output
transistors while the control logic continues to function
normally. The logic control current (100) was found to
increase by only 0.6 mA with four amps of current being
pulled out of an output. Additionally, the IpWR current was
found to increase by only 0.15 mA under the same condition.
These increases are a result of minority carriers being
injected into substrate and subsequently being collected.
The following procedure has been developed to test for
transient latch-up immunity and has been applied to this
automotive circuit design. Results of transient testing indicate
the device to operate properly at output currents greater than
1.5 A. The procedure tests for the device's immunity to
intermittent load to battery current connection with the device
controlling an inductive load. Appropriately termed "the file
test," the battery is connected to a shop file while the lead to
the inductive load is dragged across the files surface causing
intermittent load opens producing lots of arcs, sparks, and
smoke, plus severe transients (see Figure 24). It is during
these severe transients that latch-up most likely could occur.
The battery voltage used for this test was 18 V and the
inductive load was 2.0 mHo These values were found to
produce severe transient stresses of the device outputs. All
outputs must maintain operation and input control during
transient generation to pass "the file test."

The device's input control currents were found to remain
stable and were not affected by DC or transient latch-up
immunity testing.
Figure 24. Transient Latch-Up Immunity File Test

II

I

OUlputO

~

1.0
1.0
l.o
I
I

Output
1-7

APPLICATIONS INFORMATION
SlOP Communication
Two common communication protocols used in Motorola's
microprocessors are the Serial Peripheral Interface (SPI) and
Synchronous Input Output Port (SlOP). SlOP is a subset of
the more flexible SPI and the simpler of the two protocols.
SlOP is used on many of the MC68HC05 family of
microcontrollers. Restrictions of the SlOP protocol include:
1) the SCLK frequency is fixed at one-fourth the internal clock
rate and 2) the polarity of the SCLK signal is fixed.
By way of example, the MC68HC05P9 utilizes SlOP protocol and is not directly compatible with the serial input requirements of the MC33298. Specifically, the MC33298 accepts
data on the falling edge of SCLK whereas its rising edge triggers data transfer in the SlOP protocol. SCLK is high during
SlOP transmissions, which is the opposite of what the
MC33298 requires.
Though designed specifically for SPI communication
protocol, the MC33298 can easily be adapted to
communicate with SlOP protocol through the use of software.
The amount of code required to implement SPI in software is
relatively small, so the only major drawback is a slower
transfer of data. The software routine shown in Table 1
completes a transfer in about 100 ~.

Cost
The bottom line relates to cost. The MC33298 is a very
cost effective octal output serial switch for applications
typically encountered in the automotive and industrial market
segments. To accomplish only the most basic serial switch
function the MC33298 offers, using a discrete semiconductor
approach, would require the use of at least eight logic level
power MOSFETs for the outputs and two shift registers for the
I/O plus other miscellaneous "glue" components. Additional
circuitry would have to be incorporated to accomplish the
protection features offered by the MC33298. Other
noteworthy advantages the MC33298 offers are
conservation of power and board space, requirement of
fewer application components, and enhanced application
reliability. The MC33298 is available at a fraction of the cost
required for discrete component implementation and
represents true value.
The MC33298 represents a cost effective device having
advanced performance and features and worthy of
consideration.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
10-95

MC33298
Table 1. Program to Exercise the MC33298 Using SPI (Having Only SlOP) Protocol
SET LABELS FOR OUTPUT REGISTERS
PORTA

EQU

$0000

;SPIPort
;DO (Data Out), SCLK, CS, RESET, X, FlTOUT, DI (Data In)
;Normally the SlOP Port. SlOP will be disabled

PORTB

EQU

$0001

PORTC

EQU

$0002

;A-D Converter Port

PORTO

EQU

$0003

;Timer Capture Port

DDRA

EQU

$0004

;Data Direction Register for SPI Port

DDRB

EQU

$0005

;Data Direction Register for SClK, SDI, SDO, 11111

DDRC

EQU

$0006

;Data Direction Register for A-D Converter Port

DDRD

EQU

$0007

;Data Direction Register for PORTD, Timer Capture

DTOUT

EQU

$0080

;Register for the SPI output data. This register will be used for a Serial-to-Parallel transformation.

DATAIN

EQU

$0081

;Input Register for SPI. Also used for a Serial-to-Parallel transformation.

VALUE

EQU

$0082

;Register to store the SPI. Also used for a Serial-to-Parallel transformation.

DATA1

EQU

$0083

;Miscellaneous data register

SCR

EQU

$OOOA

;label for SlOP control register, 0 SPE 0 MSTR 0 0 0 O.

SSR

EQU

$OOOB

;label for SlOP status register, SPIF DCOl 0 0 0 0 0 0, Read Only Register.

SDR

EQU

$OOOC

;label for SlOP data register.
;Program starts at first byte of User ROM.
;Reset Stack Pointer to $FF.

INITIALIZE THE DATA REGISTERS AND THEIR DATA DIRECTION BIT REGISTERS
;Configuration PortA as the SPI Port.
;AII but Bit 0 will be outputs.
LOA

#$FF

STA

DDRB

;Configure Register B as an output. SlOP is not used for the MC33298, but is available for
another peripheral.

STA

DDRC

;Configure Register C as an output

STA

DDRD

;Configure Register D as an output
;Initialize the SlOP Control Register.
;Disable SlOP by clearing Bit 6.

SELECT THE DESIRED OUTPUTS
TOP

lDA
STA

#$55
VALUE

Select outputs of MC33298 to be turned ON. This instruction is left inside the loop to include
changes while running the program. A set bit will cause the associated MC33298 output to be OFF.
The value register is uncorrupted by the serial-to-parallel conversion.

BSET

4,PORTA

;Reset the MC33298.

BClR

4,PORTA

;Also establishes a + or - trigger source

BSET

4,PORTA

;The MC33298 is reset with a logic low.
;Enable MC33298 by pulling CSB (chip select bar) low. Within the MC33298 the Fault Status is
transferred to the MC33298 Serial Register at a falling edge of CSB.

;Select outputs to be turned ON.
;Save Output Word (Value) to check for fault.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

10-96

MC33298
SPI TRANSFER LOOP

;Set the number of Read/Shift cycles.
ASL

DATAIN

;Shift a Zero into LSB of DATAIN and ASL other bits.

ASL

DTOUT

;Test value currently in MSB of DTOUT.

BCS

DOONE

BCLR

7,PORTA

JMP

GOON

DOONE

BSET

7,PORTA

;MSB was One, so set the DATA OUT bit.

GOON

BSET

6,PORTA

;Set the SCLK. Serial Output pin of the MC33298 changes state on the rising edge of the SCLK.
Read the next bit coming from the MC33298.

BRCLR

O,PORTA,
WZZERO

;Read the bit and branch if Zero. LSB of DATAIN is already cleared due to the ASL above.

BSET

O,DATAIN

;Bit was One. Set the next bit in DATAIN.

BCLR

6,PORTA

;Clear SCLK. Falling edge causes the MC33298 to read the next bit from the MCU.

LOOP

WZZERO

;

;MSB was Zero, so clear DATA OUT bit.

DECX
BPL

LOOP

;Continue to loop eight times until the SPI transfer is complete.
;Transfer control signal to output transistors.

ESTABLISH A BRIEF DELAY

LOA
PAUSE

#16

DECA

;3 Clock cycles
;3 Clock cycles

BNE

PAUSE

BCLR

5,PORTA

;Transfer output status to Serial Register.

JSR

FLTCHK

;Jump to Fault Check subroutine.

JSR

DLY

;Delay 11T msec

IDI

I

;Deselect the MC33298.
;Return to top of loop.
SUBROUTINE TO CHECK FOR FAULTS

FLTCHK

NOFLT

BCLR

1,PORTA

LDA

DATAIN

CMP

VALUE

BEQ

NOFLT

BSET

1,PORTA

;CLR the Fault pin.

;Check for Faults.
;If there is no Fault, continue.
;Activate Fault LED.

RTS

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

10-97

MC33298
DELAY SUBROUTINE
DLY

STA

DATA1

LDA

#$04

OUTLP

CLRX

INNRLP

DECX
BNE

;Save Accumulator in RAM.
;Do outer loop 4 times, roughly 4.0 ms.
;X used as Inner Loop Count
;O-FF, FF-FE, ... 1-0 256 loops.

INNRLP

DECA

;6CYC' 256' 1.0

~s/CYC

= 1.53 ms

;4-3.3-2,2-1,1-0
~s/CYC

BNE

OUTLP

;1545CYC' 4'1.0

LDA

DATA1

;Recover Accumulator value.

RTS

=6.18 ms

;Return from subroutine.

ORG

$1FF

FDB

INIT

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
10-98

MOTOROLA

MCCF79076

SEMICONDUCTOR-----TECHNICAL DATA

Product Preview

IGNITION CONTROL
FLIP-CHIP

Ignition Control Flip-Chip
The MCCF79076, in conjunction with an appropriate Motorola Power
Darlington Transistor, provides an economical solution for automotive ignition
applications. The MCCF79076 offers optimum performance by providing closed
loop operation of the Power Darlington in controlling the ignition coil current.
The MCCF79076 incorporates Flip-Chip Technology which involves the
formation of solder bumps, rather than traditional wire bonds, to establish
mechanical and electrical contact to the semiconductor chip. This process affords
a unique device having improved reliability at elevated operating temperatures.

SILICON MONOLITHIC
INTEGRATED CIRCUIT

FLlp·CHIP CONFIGURATION

• Solder Bumped for Flip-Chip Assembly
• Ignition Coil Voltage Internally Limited to 375 V
• Coil Current Limiting to 7.5 A
• Output On-Time (Dwell) Control

2

0

3

0
0

• Dwell Feedback Control to Sense Coil Variation
• Hall Sensor Input
• - 30°C ~ TA ~ +140°C Ambient Operating Temperature

4

0

1

5

oJ

6

oJ

y

\..

1

0 0

\..

y

7

0

13

0
0
0

12

10

0

9

11

8

Top View
(Bump Side)

-

Simplified Block Diagram
and Application Circuit

BUMP CONNECTIONS
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.

I
Hall

Sensor
Input

6

I
I

High Ground
Output Current UmH
Dwell Output
Supply
Low Ground
Reference Dwell Input
Advance Input
Bias Voltage
Estlnput
Reference Output
Bypass Input
900 RPM Detector
Dwell Control

II
-=-=- L - - - - - - - - - - - - -1
ORDERING INFORMATION

Device

Temperature
Range

Package

MCCF79076

- 30° to +125°C

Flip-Chip

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
10-99

I

MOTOROLA

TCF6000

SEMICONDUCTOR-----TECHNICAL DATA

Peripheral Clamping Array

PERIPHERAL CLAMPING ARRAY
SILICON MONOLITHIC
INTEGERATED CIRCUIT

The TCF6000 was designed to protect input/output lines of microprocessor
systems against voltage transients.
•
•
•
•
•

Optimized for HMOS System
Minimal Component Count
Low Board Space Requirement
No P.C.B. Track Crossovers Required
Applications Areas Include Automotive, Industrial,
Telecommunications and Consumer Goods

o SUFFIX
PLASTIC PACKAGE
CASE 751
(SO-8)

PIN CONNECTIONS

Gnd08

Clamp 2
Clamp 3

6 Clamp

Clamp 4

5 Clamp

Figure 1. Block Diagram and Typical Aplication

Each Cell

Digital

Inputs

{~vv\~-t+----I-H--l
Micro
Computer

Analog
Inputs

{~---l------I
Gnd

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
10-100

vcc

7 Clamp

TCF6000
MAXIMUM RATINGS (TA = 25°C, unless otherwise noted, Note 1.)
Rating

Symbol

Value

Supply Voltage

VCC

6.0

V

Supply Current

Ii

300

rnA

11K

±50

rnA

Clamping Current

Unit

Junction Temperature

TJ

150

°C

Power Dissipation (TA = + 85°C)

PD

400

m!W

Thermal Resistance (Junction-Ambient)

9JA

100

°CIW

Operating Ambient Temperature Range

TA

-40 to +85

°C

Tstg

-55to+150

°C

Storage Temperature Range
Note 1. Values beyond which damage may occur.

ELECTRICAL CHARACTERICISTICS (TA = 25°C, 4.5 <
- VCC <- 5.5 V; if not otherwise noted.)
Characteristics

Symbol

Max

Unit

-

VCC+l.0

V

IIK(P)

-

20

rnA

Negative Peak Clamping Voltage
(11K =-10 rnA, -40°C STA S + 85°C)

V(IK)

-{).3

-

V

Negative Peak Clamping Current

IIK(P)

-20

-

rnA

IL
ILT

--

1.0
5.0

AcT

100

-

d8

-

2.0

rnA

Positive Clamping Volta~ (Note 2)
(11K = lOrnA, -40°C S AS + B5°C)

V(IK)

Positive Peak Clamping Current

Output Leaka~ Current
(0 V S Yin S CC)
(0 V S Yin S VCC, -40°C S TA S + 85°C)
Channel Crosstalk (ACT = 20 log ILlIIK)
Quiescent Current (Package)

Min

18

J.IA

Note 2. The device might not give 100% protection in CMOS applications

CIRCUIT DESCRIPTION
To ensure the reliable operation of any integrated circuit
based electronics system, care has been taken that voltage
transients do not reach the device I/O pins. Most NMOS,
HMOS and Bipolar integrated circuits are particularly sensitive
to negative voltage peaks which can provoke latch-up or
otherwise disturb the normal functioning of the circuit, and in
extreme cases may destroy the device.
Generally the maximum rating for a negative voltage
transients on integral circuits is -0.3 V over the whole
temperature range. Classical protection units have consisted
of diode/resistor networks as shown in Figures 2a and 2b.
The arrangement in Figure 2a does not, in general, meet the
specification and is therefore inadequate.
The problem with the solution shown if Figure 2b lies mainly
with the high current drain through the biassing devices
Rl and 03. A second problem exists if the input line carries an
analog signal. When Vin is close to the ground potential,
currents arising from leakage and mismatch between 03
and D2 can be sourced into the input line, thus disturbing
the reading.

Figure 2_ Classical Protection Circuits

b

a
VCC
Rl
Vin

IIC

Rin

In,.1-

C.

01

Vin Rin

01

I

02

I

I

Gnd

IIC

02

c.In!
.103

Gnd

Figure 3 shows the clamping characteristics which
are common to each of the six cells in the Peripheral
Clamping Array.
As with the classical protection circuits, positive voltage
transients are clamped by means of a fast diode to the VCC
supply line.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
10-101

VCC

TCF6000
Figure 3. Clamping Characteristics
11K
+10mA - t - - - - - - - - - - i - - -

Vcc

APPLICATIONS INFORMATION
Figure 4 depicts a typical application in a microcomputer
based automotive ignition system.
The TCF6000 is being used not only to protect the
system's normal inputs but also the (bidirectional) serial
diagnostics port.
The value of the input resistors, Rin, is determined by the
clamping current and the anticipated value of the spikes.
Thus:

Vcc+

Rin =

0.75 VTyp

where:
So, taking,
-10mA

gives,

Hi h
Impedance

Impedance

Low
Impedance

V =
11K =
V =
11K =
Rin =

V

11K n

Peak Volts (V)
Clamping current (A)
300 V typically (SAE J1211)
10 mA (recommended)
30 k

Resistors of this value will not usually cause any problems
in MOS systems, but their presence needs to be taken into
account by the designer. Their effect will normally need to be
compensated for Bipolar systems.

Figure 4. Typical Automotive Application

Vee
~
Gnd

Vee
BO

Coil Drive

06

Coil Feedback

MC6805S2

Bl
B2
VSS
Gnd

Gnd

Serial Diagnostics

..

Car

Ignition Module

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

10-102

TCF6000
The use of Cin is not mandatory, and is not recommended
where the lines to be protected are used for output or for both
input and output. For digital input lines, the use of a small
capacitor in the range of 50 pF to 220 pF is recommended as
this will reduce the rate of rise of voltage seen by the TCF6000
and hence the possibility of overshoot.
In the case of the analog inputs, such as that from the
pressure sensor, the capacitor Cin is necessary for devices,
such as the MC6805S2 shown, which present a low
impedance during the sampling period. The maximum value
for Cin is determined by the accuracy required, the time taken
to sample the input and the input impedance during that time,
while the maximum value is determined by the required
frequency response and the value of Rin.
Thus for a resistive input AlO connector where:
Ts = Sample time (Seconds)
RO = Oevice input resistance (n)
Vin = Input voltage (V)
k

Thus:

but,
and,
so that,

and,

al = Cin Vin
al--Q2 = 10 - TS

10 TS
.

k - Cin-Vin
100

10-TS

Cin (min) = - Vk. Farad
In -

so,

.
100-TS
Cin (min) = k _ RO Farad

The calculation for a sample and hold type converter is
even simpler:
k = Required accuracy (%)
CH = Hold capacitor (Farad)
.
100 - CH
Cin (min) = - - k - - Farad

= Required accuracy (%)

al = Charge on capacitor before sampling

For the MC6805S2 this comes out at:

a2 = Charge on capacitor after sampling

C' (min) = 100.25 pF = 10 nF for 1/40/. accuracy
In
0.25
0

10 = Oevice input current (A)

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
10-103

MOTOROLA

UAA1041

SEMICONDUCTOR-----TECHNICAL DATA

Automotive Direction Indicator
This device was designed for use in conjunction with a relay in automotive
applications. It is also applicable for other warning lamps such as "handbrake
ON," etc.
•
•
•
•
•

AUTOMOTIVE DIRECTION
INDICATOR
SILICON MONOLITHIC
INTEGRATED CIRCUIT

Defective Lamp Detection
Overvoltage Protection
Short Circuit Detection and Relay Shutdown to Prevent Risk of Fire
Reverse Battey Connection Protection
Integrated Suppression Clamp Diode

.~
1

PSUFFIX

PLASTIC PACKAGE
CASE 626

Figure 1. Typical Automotive System

C2
-VCC

RS

8

2

UAA1041

7

3

6

4

5

+V

DSUFFIX

T
-.L

PLASTIC PACKAGE
CASE 751
(SO'B)

-v
R2

Rl
R3

0

PIN CONNECTIONS

-vee
+Vbat 2
RLY Out
Oscillator

8
7

Start
FauH Det

3

6

FauH Del On/Off

4

5

Oscillator

(Top View)
12

1.3

L4

L5

ORDERING INFORMATION

Ll: 1.2W, warning light handbrakeON
12, 1.3, L4, L5: 21 W, turn signals

Rl =75k
R2=3.3k
R3=2200

Rs=30mO
Cl =5.6I1F
C2=O.047I1F

Device

UAA1041D
UAA1041P

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
10-104

Ambient
Temperature Range

-40° to + 100°C

Package

50-8
Plastic DIP

UAA1041
MAXIMUM RATINGS
Rating
Current: Continuous/Pulse'

Pin

Value

Unit

1

+150/+500
-35/-500
+/-350/1900
+/-300/1400
+/-25/50

rnA

°C

2
3
8
Junction Temperature

TJ

150

Operating Ambient Temperature Range

TA

--40 to + 100

°C

Storage Temperature Range

Tstg

--65 to + 150

°C

, One pulse with an exponential decay and with a time constant of 500 ms.

ELECTRICAL CHARACTERICISTICS (Tl = 25°C)
Characteristics
Battery Voltage Range (normal operation)

Symbol

Min

VB

8.0

Typ
-

Max

Unit

18

V

Overvoltage Detector Threshold

(VPinZ-VPinl)

Dth(OV)

19

20.2

21.5

V

Clamping Voltage

(VPinZ-VPinl)

VIK

29

31.5

34

V

Short Circuit Detector Threshold

(VPinZ-VPin7)

Dth(SC)

0.63

0.7

0.77

V

Output Voltage (Irel ay

= -250 rnA)

(VPin2-VPin3)

Vo

-

= R2 + RLamp

Rst

-

Oscillator Constant (normal operation)

Kn

1.4

Temperature Coefficient of Kn

Kn

-

Duty Cycle (normal operation)

-

Starter Resistance Rst

Oscillator Constant -

(1 lamp defect of 21 W)

KF

Duty Cycle (1 lamp defect of 21 W)

-

Oscillator Constant

Kl
K2
K3

Current Consumption (relay off)
Pin 1; at VPin2 - VPinl = 8.0 V
= 13.5 V
= 18 V

ICC

1.5

V

3.6

kat

1.5

1.6

-1.5xl0--3

-

45

50

55

0.63

0.68

0.73

35

40

45

0.167
0.25
0.126

0.18
0.27
0.13

0.193
0.29
0.14

-

-0.9
-1.6
-2.2

79

-

t See Note 1 of Application Information

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

10-105

%

-

-1.0

rnA

-

VPinZ- VPin7
VPinZ- VPin7
VPin2-VPin7

%

-

-

-

= 8.0 V
= 13.5V
= 18 V

lrC

rnA

-2.5

Current Consumption (relay on)
Pin 1; at VPin2 - VPinl = 8.0 V
= 13.5 V
= 18 V
Defect Lamp Detector Threshold at VPin2 to VB
and R3 = 220 a

-

-3.8
-5.6
--6.9

-

68
85.3
100

-

91

-

mV

UAA1041
CIRCUIT DESCRIPTION
The circuit is designed to drive the direction indicator flasher
relay. Figure 2 shows the typical system configuration with the
external components. It consists of a network (R1, C1) to
determine the oscillator frequency, shunt resistor (RS) to
detect defective bulbs and short circuits in the system, and two
current limiting resistors (R2/R3) to protect the IC against load
dump transients. The circuit can be used either with or without
short circuit detection, and features overvoltage, defective
lamp and short circuit detection.
The lightbulbs L2, L3, L4, L5 are the turn signal indicators
with the dashboard-light L6. When switch S1 is closed, after a
time delay of t1 (in our example t1 = 75 ms), the relay will be
actuated. The corresponding lightbulbs (L2, L3 or L4, L5) will
flash at the oscillator frequency, independent of the battery
voltage of 8.0 V to 18 V. The flashing cycle stops and the circuit
is reset to the initial position when switch S1 is open.

Operation without Short Circuit Detection
Pin 6 has to be connected to Pin 2, and the use of capacitor
C2 is not necessary. The circuit can also be used for other
warning flashers. In this example, when the handbrake is
engaged, it is signaled by the light (L 1).
Figure 2. Typical System Configuration

Overvoltage Detection
Senses the battery voltage. When this voltage exceeds 20.2 V
(this is the case when two batteries are connected in series),
the relay will be turned off to protect the lightbulbs
Lightbulb Defect Detector
Senses the current through the shunt resistor RS. When one
ofthe lightbulbs is defective, the failure is indicated by doubling
the flashing frequency.
Short Circuit Detector

l2

Detects excessive current (Ish> 25 A) flowing in the shunt
resistor RS. The detection takes place after a time delay of t3
(t3 = 55 ms).ln this case, the relay will be turned off. The circuit
is reset by switching S1 to the off position.

l.3

L4

L.5

PARTS LIST
R1 = 75 kn
Relay-Coil Resistance
R2 = 3.3 kn
Range 60 n to 800 n
R3=220n
Note: Per text connect
RS=30mn
Wire Resistor
jumper JU-1 bypass
short circuit detector
C1 = 5.6 ~F
C2 may be deleted also.
C2 = 0.047 ~F

Operation with Short Circuit Detection
Pin 6 has to be left open and a capacitor C2 has to be
connected between Pin 1 and Pin 2.

APPLICATION INFORMATION
1. The flashing cycle is started by closing S1. The switch
position is sensed across resistor R2 and RLamp by
Input 8.
Rst = R2 + RLamp.
The condition for the start is: Rst < 3.6 kn.
For correct operation, leakage resistance from Pin 8 to
ground must be greater than 5.6 kn.

6

2. Flashing frequency: fn = R 1 1Kn
3. Flashing frequency in the case of one defective lightbulb
of 21 W:

4. t1: delay at the moment when S1 is closed and first flash
t1 =K1R1C
5. t2: defective lightbulb detection delay t2 = K2R1 C1
6. t3: short circuit detection delay t3 = K1 R1 C1
In the case of short circuit - it is assumed that the
voltage (VPin2-VPin1) ;;:: 8.0 V. The relay will be turned off
after delay t3. The circuit is reset by switching S1 to the off
position.
7. The capacitor C2 is not obligatory when the short circuit
detector is not used. In this case Pin 6 has to be connected
to Pin 2.
8. When overvoltage is sensed (VPin2 - VPin1) the relay is
turned off to protect the relay and the lightbulbs against
excessive currents.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

10-106

Other Linear Circuits

In Brief ...
Page

A variety of other analog circuits are provided for special
applications with both bipolar and CMOS technologies.
These circuits range from the industry standard analog timing circuits and multipliers to specialized CMOS smoke detectors. These products provide key functions in a wide
range of applications, including data transmission, commercial smoke detectors, and various industrial controls.

Timing Circuits
Singles . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 11-2
Duals ....................................... 11-2
Multipliers
Linear Four-Quadrant Multipliers .............. .. 11-2
Smoke Detectors(CMOS) ........................ 11-3
Index .......................................... 11-4
Data Sheets .................................... 11-5

Timing Circuits

Multipliers

These highly stable timers are capable of producing
accurate time delays or oscillation. In the time delay mode of
operation, the time is precisely controlled by one external
resistor and capacitor. For a stable operation as an oscillator,
the free-running frequency and the duty cycle are both
accurately controlled with two external resistors and one
capacitor. The output structure can source or sink up to 200
rnA or drive TTL circuits. TIming intervals from microseconds
through hours can be obtained. Additional terminals are
provided for triggering or resetting if desired.

Multipliers are designed for use where the output voltage
is a linear product of two input voltages. Typical applications
include: multiply, divide, square, root-mean-square, phase
detector, frequency doubler, balanced modulator/demodulator, electronic gain control.

Singles
MC1455P1 ,U,D TA = 0° to +70°C, Case 626, 693, 751
MC1455BP1 TA = --40° to +85°C, Case 626

Duals
MC3456L,P TA = 0° to +70°C, Case 632, 646

-4.0 -2.0 0
2.0 4.0
VX, INPUT VOLTAGE M

NE556A,N TA = 0° to +70°C, Case 646
NE556D TA = 0° to +70°C, Case 751

Linear Four-Quadrant Multipliers

Vee
8

MC1594L TA = -55° to +125°C, Case 620

Threshold

MC1494L TA = 0° to +70°C, Case 620

7
Discharge

Control
Voltage

Gnd

The MC1594/MC1494 is a variable transconductance
multiplier with internal level-shift circuitry and voltage
regulator. Scale factor, input offsets and output offset are
completely adjustable with the use of four external
potentiometers. Two complementary regulated voltages are
provided to simplify offset adjustment and improve power
supply rejection.

Reset

MC1595L TA = -55° to +125° C, Case 632
MC1495L TA = 0° to +70° C, Case 632

These devices are designed for uses where the output is
a linear product of two input voltages. Maximum versatility is
assured by allowing the user to select the level shift method.
Typical applications include: multiply, divide(1), square root(1),
mean square(1), phase detector, frequency doubler, balanced
modulator/demodulator, and electronic gain control.
(I}When used with an operational amplifier.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

11-2

Smoke Detectors (CMOS)
These smoke detector les require a minimum number of external components. When smoke is sensed, or a low battery
voltage is detected, an alarm is sounded via an external piezoelectric transducer. All devices are designed to comply with
UL specifications.

Smoke Detectors (CMOS)
Low
Battery
Detector

V

Piezoelectric
Horn Driver

Complies
with
UL217
and UL268

Device
Number

Suffix!
Case

V

V

MC14467-1

P1/626

MC14578

P/648

Recommended
Power Source

Unique
Feature

Ionization-Type
Smoke Detector

Battery

High Input Impedance
FET Comparator

Line

-

-

Ionization-Type
Smoke Detector
with Interconnect

Battery

V

V

V
V

MC14468

-

Photoelectric-Type
Smoke Detector
with Interconnect

Battery

V

V
V

V
V

MC145010

V

V

V

(1)

V

V

Function

Line
Photo Amplifier

Line
(1 )Low·supply detector

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
11-3

MC14470

MC145011

P/648
DW/751G

OTHER LINEAR CIRCUITS
Timing Circuits
Device

Function

MC1455
MC3456

Timing Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 11-5
Dual Timing Circuit ............... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 11-41

Page

Multipliers
Device

Function

MC1494
MC1495
MC1496
MC1594
MC1595
MC1596

Linear Four-Quadrant Multiplier ............................................... 11-12
Wide band Linear Four-Quadrant Multiplier ..................................... 11-26
Balanced Modulator/Demodulator Four-Quadrant Multiplier .............. (See Chapter 8)
Linear Four-Quadrant Multiplier ............................................... 11-12
Wideband Linear Four-Quadrant Multiplier ..................................... 11-26
Balanced Modulator/Demodulator Four-Quadrant Multiplier .............. (See Chapter 8)

Page

RELATED APPLICATION NOTES
Application
Note

Title

AN489

Analysis and Basic Operation of the MC1595 (Out of Print) .................... MC1595

AN531

MC1596 Balanced Modulator .............................................. MC1596

Related
Device

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
11-4

MOTOROLA

MC1455

SEMICONDUCTOR-----TECHNICAL DATA

TIMING CIRCUIT

Timing Circuit
The MC1455 monolithic timing circuit is a highly stable controller capable of
producing accurate time delays or oscillation. Additional terminals are provided
for triggering or resetting if desired. In the time delay mode, time is precisely
controlled by one external resistor and capacitor. For astable operation as an
oscillator, the free-running frequency and the duty cycle are both accurately
controlled with two external resistors and one capacitor. The circuit may be
triggered and reset on falling waveforms, and the output structure can source or
sink up to 200 mA or drive MTTL circuits.

SILICON MONOLITHIC
INTEGRATED CIRCUIT

~
1

• Direct Replacement for NE555 Timers

PI SUFFIX
PLASTIC PACKAGE
CA8E626

• Timing from Microseconds through Hours
• Operates in Both Astable and Monostable Modes

USUFFIX
CERAMIC PACKAGE
CASE 693

• Adjustable Duty Cycle
• High Current Output Can Source or Sink 200 mA
• Output Can Drive MTTL
• Temperature Stability of 0.005% per °C

DSUFFIX
PLASTIC PACKAGE
CASE 751

• Normally ON or Normally OFF Output

(SO-8)

Figure 1. 22 Second Solid State Time Delay Relay Circuit

ORDERING INFORMATION
Device
MC1455P1
MC1455D
MC1455U

10k

MC1455BD
MC1455BP1

t=1.1;RandC=22sec
Time delay (t) is variable by
changing A and C (see Figure 16).

lN4740

Temperature
Range
0° to +70°C

--40' to +85°C

Package
Plastic DIP
80-8
Ceramic DIP
80-8
Plastic DIP

Figure 3. General Test Circuit

Figure 2. Block Diagram
vcc
8

------------,
I7

Threshold ---{:l-+--1
Control Voltage

. .,----1(}--

Discharge

---{:l-+--1
Outpul

Trigger -(l-----t---i
L

Gnd

Reset

Test circuit for measuring De parameters (to set output and
measure parameters):
a) When Vs " 213 Vee. Va is low.
b) When Vs " 1/3 Vee, Va is high.
c) When Va is low, Pin 7 sinks current. To test for Reset, set Va,
high, apply Reset voltage, and test for current flowing into Pin
7. When Reset is not in use, it should be tied to Vee.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
11-5

III

MC1455
MAXIMUM RATINGS (TA = +25°C, unless otherwise noted.)
Rating
Power Supply Voltage
Discharge Current (Pin 7)
Power Dissipation (Package Limitation)
U Suffix, Ceramic Package
Derate above TA = +25°C
P1 Suffix, Plastic Package
Derate above TA = +25°C
D Suffix, Plastic Package
Derate above TA = +25°C
Operating Temperature Range (Ambient)
MC1455S
MC1455
Storage Temperature Range

Symbol

Value

Unit

VCC

+18

Vdc

17

200

rnA

PD

1000
6.6
625
5.0
625
160

mW
mW/oC
mW
mW/oC
mW
°C/W

PD
PD

°C

TA
-40 to +85
to +70

o

Tstg

-65 to +150

°C

ELECTRICAL CHARACTERISTICS (TA = +25°C, VCC = +5.0 V to + 15 V, unless otherwise noted.)
Symbol

Min

Operating Supply Voltage Range

Characteristics

VCC

4.5

Supply Current
Vce = 5.0 V, Rl = 00
Vce = 15 V, Rl = 00, low State (Note 1)

ICC

Timing Error (R = 1.0 kQ to 100 kn) (Note 2)
Initial Accuracy C = 0.1 j.lF
Drift with Temperature
Drift with Supply Voltage
Threshold Voltage/Supply Voltage

VthNCC

Trigger Voltage
Vce=15V
VCC = 5.0V

VT

Typ
-

Max
16

Unit
V
rnA

-

3.0
10

6.0
15

-

1.0
50
0.1

-

%

-

PPM/oC

2/3

-

5.0
1.67

-

%N
V

Trigger Current

IT

-

0.5

-

Reset Voltage

VR

0.4

0.7

1.0

Reset Current

IR

-

0.1

-

Threshold Current (Note 3)

Ith

-

0.1

0.25

j.lA

Idischg

-

-

100

nA

Discharge leakage Current (Pin 7)
Control Voltage level
Vce=15V
Vce =5.0 V

VCl

Output Voltage low
ISink = 10 rnA (VCC = 15 V)
ISink = 50 rnA (VCC = 15 V)
ISink = 100 rnA (VCC = 15 V)
ISink = 200 rnA (VCC = 15 V)
ISink = 8.0 rnA (VCC = 5.0 V)
ISink = 5.0 rnA (VCC = 5.0 V)

VOL

Output Voltage High
VCC = 15 V (lSource = 200 rnA)
VCC = 15 V (lSource = 100 rnA)
VCC = 5.0 V (ISource = 100 rnA)

VOH

10
3.33

11
4.0

0.1
0.4
2.0
2.5

0.25
0.75
2.5

V

-

-

-

0.25
12.5
13.3
3.3

0.35

-

tr

-

100

-

ns

tf

-

100

-

ns

NOTES:
1. Supply current when output is high is typically 1.0 rnA less.
2. Tested at VCC = 5.0 V and VCC = 15 V Monostable mode.
3. This will determine the maximum value of RA + RS for 15 V operation. The maximum total R = 20 mQ.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
11-6

V

12.75
2.75

Rise Time Differential Output

V
rnA

V
9.0
2.6

Fall Time Differential Output

j.lA

MC1455
Figure 4. Trigger Pulse Width

Figure 5. Supply Current

150

10

~ 125

:;(

~ 100

Z
W

75

-- -

ooe :...

50
25

o

o

0.1

6.0

u

::;

2:;;:..r:.. ....

b:::::= ~

"-

V
./

::J

...-I-"r-'

~

15:
;:

a:
a:

""::J

4.0

u

2.0

./

.O?

0.2

0.3

0.4

5.0

10
Vee, SUPPLY VOLTAGE (Vdc)

'2~O~

'"1:3

......

25°e

1.0

0

/

I-

>

"-

:s:
9

0.1

""

10

20

50

100

::J

0

V

:s:
9

1.015

1.015

w 1.010

~ 1.010

0



ISink, (mA)

:s

>

0.01
5.0

1.0

0

"-

0

0

Figure 9. Low Output Voltage

'"1:3

?

>
2.0

100

I-

..0

0.01
1.0

50

::J

0

0

20

2w

"-

>

10

I-

:::>

..0

5.0

."

I-

./'

2.0

10

::J

I-

1.0

ISource (mA)

I-

::J

~

5.0V$Vee$15V

o

15

I

~

w

0.1

0.6

@Vee=15Vdc

10

I

:::>

0.8

>

@Vee=10Vdc

0

1.0

b

u

Figure 8. Low Output Voltage

~

:s:
9

0

@ Vee = 5.0 Vdc

1.0

--

1.2

>

Figure 7. Low Output Voltage

w

0

b

0.2

10

>

~:r:

V

25 0

1.4

0.4

VT (min)' MINIMUM TRIGGER VOLTAGE
(x Vee =Vdc)

'"1:3

/

1.6

V

V

~

700 e

1.8

/

I-

b

~

~5oel / V

8.0

.§.

Figure 6. High Output Voltage
2.0

50

-

...2;£- ~ ~
~

~

J

V

-.;: rc- 25°e
- p:=. 70 e
0

I I

0.1
0.2
0.3
0.4
VT (min), MINIMUM TRIGGER VOLTAGE
(x Vee =Vdc)

MC1455
Figure 13. Representative Circuit Schematic
Control Voltage

1------11---1
I

II

Flip·Flop

Output

Vcc

I
I

Threshold

Output

Trigger 0------+--1--1

Reset

4.7k

Discharge
100

GENERAL OPERATION
The MC1455 is a monolithic timing circuit which uses as its
timing elements an external resistor - capacitor network. It
can be used in both the monostable (one-shot) and astable
modes with frequency and duty cycle controlled by the
capacitor and resistor values. While the timing is dependent
upon the external passive components, the monolithic circuit
provides the starting circuit, voltage comparison and other
functions needed for a complete timing circuit. Internal to the
integrated circuit are two comparators, one for the input signal
and the other for capacitor voltage; also a flip-flop and digital
output are included. The comparator reference voltages are
always a fixed ratio of the supply voltage thus providing output
timing independent of supply voltage.

input signal, it cannot be retriggered until the present timing
period has been completed. The time that the output is high is
given by the equation t = 1.1 RA C. Various combinations of R
and C and their associated times are shown in Figure 16. The
trigger pulse width must be less than the timing period.
A reset pin is provided to discharge the capacitor thus
interrupting the timing cycle. As long as the reset pin is low, the
capacitor discharge transistor is turned "on" and prevents the
capacitor from charging. While the reset voltage is applied the
digital output will remain the same. The reset pin should be tied
to the supply voltage when not in use.

Figure 14. Monostable Circuit

Monostable Mode
In the monostable mode, a capacitor and a single resistor
are used for the timing network. Both the threshold terminal
and the discharge transistor terminal are connected together
in this mode, refer to circuit Figure 14. When the input voltage
to the trigger comparator falls below 113 VCC the comparator
output triggers the flip-flop so that it's output sets low. This
turns the capacitor discharge transistor "off" and drives the
digital output to the high state. This condition allows the
capacitor to charge at an exponential rate which is set by the
RC time constant. When the capacitor voltage reaches 2/3
VCC the threshold comparator resets the flip-flop. This action
discharges the timing capacitor and returns the digital output
to the low state. Once the flip-flop has been triggered by an

+Vce (5.0V to 15V)

Reset
4
. - - - ' -_ _L

Output

~ RL

2
Trigger

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
11-8

Vee
8::....., Discharge
7

MC1455
Figure 15. Monostable Waveforms

Figure 16. Time Delay
100

1/

10
[L

"'-

~

z

j:!;

(3

8
5 O.OIIlF

r---t-

I

9.1k

4

8

1

=

Load

MOTOROLA

MC1494
MC1594

SEMICONDUCTOR-----TECHNICAL DATA

Linear Four-Quadrant Multiplier
The MC1494/1594 is designed for use where the output voltage is a linear
product of two input voltages. Typical applications include: multiply, divide,
square root, mean square, phase detector, frequency doubler, balanced
modulator/ demodulator, electronic gain control.
The MC1494/1594 is a variable transconductance multiplier with internal
level-shift circuitry and voltage regulator. Scale factor, input offsets and output
offset are completely adjustable with the use of four external potentiometers.
Two complementary regulated voltages are provided to simplify offset
adjustment and improve power supply rejection.
• Operates with ±15 V Supplies
• Excellent Linearity: Maximum Error (X or V): ±0.5% (MC1594)
±1.0% (MC1494)
• Wide Input Voltage Range: ±1 0 V
• Adjustable Scale Factor, K (0.1 nominal)
• Single-Ended Output Referenced to Ground
• Simplified Offset Adjust Circuitry
• Frequency Response (3 dB Small-Signal): 1.0 MHz
• Power Supply Sensitivity: 30 mVN typical

LINEAR FOUR·QUADRANT
MULTIPLIER INTEGRATED
CIRCUIT
SILICON MONOLITHIC
EPITAXIAL PASSIVATED

LSUFFIX
CERAMIC PACKAGE
CASE 620

Multiplier Transfer Characteristic
10
8.0

2:
w

~

6.0
4.0

"

I

I"...

.......... ~

~ 2.0
§!

!5

!5

"
.........

0

-2.0

0

c5 -4.0

......

> -6.0""'"

V

X

~

k=

KXY

-.!..
10

,

~~~
-.K~' :---::;

I~
l/': ...,....,'I'I~·I·

........ ~ b I-"'"
I?"" ~ ~

.,..., :/"
/

l/:::

+

X

Vy=+2.0'J
Vy=DV

.......... Vv=-i'OV

" "I""~

-8.0/
-10
-10 -8.0 -6.0 -4.0 -2.0 0 2.0 4.0
Vx, INPUT VOLTAGE M

~
'10",

6.0

8.0

10

LInearity Error versus Temperature

~ 1.00
a:

If
a:

~ 0.75

a:

15

~ 0.50

~
w

-

IS 0.25
~
w
0
-55

ORDERING INFORMATION

-25

25
75
0
50
TA, AMBIENT TEMPERATURE (DC)

100

125

Device

Ambient
Temperature Range

Package

MC1494L

0 to +70°C

Ceramic DIP

MC1495L

-55 to +125°C

Ceramic DIP

MOTOROLA LlNEARIiNTERFACE ICs DEVICE DATA
11-12

0

0

MC1494, MC1594
MAXIMUM RATINGS (TA = +25°C, unless otherwise noted.)
Rating
Power Supply Voltages
Differential Input Signal
Common Mode Input Voltage
VCMV = V9 = V6
VCMX = Vl0 = V13
Power Dissipation (Package Limitation)
TA = +25°C
Derate above TA = +25°C
Operating Temperature Range

Symbol

Value

Unit

±V

±18

Vg-V6
V1O-V13

±16 + 11 Rvl<30
±16 + 11 Rxl<30

Vdc
Vdc

VCMV
VCMX

±11.5
±11.5

PD
1/9JA

750
5.0

mW
mW/oC

TA

to +70
-55 to +125

°C

Tstg

-65 to +150

°C

Vdc

MC1494
MC1594

Storage Temperature Range

o

ELECTRICAL CHARACTERISTICS (±V = ±15 V, TA = +25°C, Rl = 16 kQ, RX = 30 ill, RV = 62 ill, RL = 47 ill, unless otherwise noted.)
Characteristics
Linearity
Output error in percent of full scale
-10 V -l

20k

e---~----+--" 50k
VX off

Figure 6. Common Mode

Figure 5. Frequency Response

CMVy

B

120HZ) :

47k

=

51

Figure 8. Burn-In

Figure 7. Power Supply Sensitivity

B.2k

H>--t-- -. Vo
47k

62k

-15V

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
11-14

MC1494, MC1594
Figure 9. Frequency Response of Y Input
versus Load Resistance

Figure 10. Frequency Response of X Input
versus Load Resistance
15
10
iii"
~

5.0

:z

~

0

w

~

~
w

a:

-5.0
-10
-15
-20
103

Figure 11. Linearity versus RX or Ry with K = 1

~ 0.4
a:
aa:
a:
w

~

0.3

a:

L5
:z
:::J

.;.
..If
0

~

w

0.2

"

Figure 12. Linearity versus RX or Ry with K = 1/10

~ 0.6
a:
aa:

RL Adjusted for K = 1 _
Vin = 2.0 Vp-p

a:
w

~

'""'-

......... t-....

0.1

-

105
f, FREQUENCY (Hz)

~

\

0.5

\

a:

L5

r-

I\.

:z

0.4

~

0.3

:::J

0

RL Adjusted for K = 1/10
Vin= 20Vp-p

1\

~

"'

~
w

0

0.2

........ r-

2.0

4.0

6.0

8.0

10 RX (kQ)

20

30

40

50

RX(kQ)

4.0

8.0

12

16

20 Ry (kQ)

40

60

60

100

Ry(kQ)

Figure 13. Large Signal Voltage versus Frequency

Figure 14. Scale Factor (K) versus Temperature
0.108

Ci:
Q.

(D

20

r--...

~
W

0

10

I-

:::l

~

~

o

100

CD
®

~

I'

With MC1456 Buffer Op Amp
No OpAmp, RL =47 kQ -

:.:

1.0k
10k
f, FREQUENCY (Hz)

~O.~

K Factor Adjusted for 1110 at 25°C)

'-

a
~ 0.102

u.:

IIIIIIII
I 1111111

6~

a: 0.104

!'!.i
~

!3
D-

0.10

1

.........

8

0.096

I

0.094

lOOk

-- ~

r

-55

-35

-15

5.0 25
45 65
85
105 125 145
TA, AMBIENT TEMPERATURE (OC)

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
11-15

r----.. ro-

MC1494, MC1594
CIRCUIT DESCRIPTION

Introduction

with the offset adjust circuits to virtually eliminate sensitivity of
the offset voltage nulls to changes in supply voltages.
As shown in Figure 15, the MC 1494 consists of a multiplier
proper and associated peripheral circuitry to provide
these features.

The MC1494 is a monolithic, four-quadrant multiplier that
operates on the principle of variable transconductance. It
features a signal-ended current output referenced to ground
and provides two complementary regulated voltages for use

Figure 15
(Recommended External Circuitry is Depicted within Dotted Lines)

1-----------------,
Block Diagram
Current and Voltage
Regulator

Vy

~

Differential
Current
Converter

Fourauadrant
Multiplier

12

_V65__________~------~+_----------~~~--~~----------~--------~
+vo-----~--._~----~_+--------~----------------------~----~----._----~

15

Simplified Circuit
Schematic

3

IA

+4.3V

tVR2

-,-

-VR

14
10

4 -4.3V

500

5
~O_----~~--~------~----~-----+----~------~----_r--------~

tVOH~.---~__~--_.--~--------_r----------------------~~------~~----~--_,

Complete Circuit
Schematic

15

5

-v O-----o-41..... vo

PI 20k

P3

50k

vo: -VXVy
10

'R is nol necessary ff inpuls are DC coupled.

MOTOROLA LlNEARIiNTERFACE ICs DEVICE DATA

11-17

-10V5VX,f+l0V
-10V5Vy5+10V

MC1494, MC1594
It should be pointed out that there is nothing magic about
setting the scale factor to 1/10. This is merely a convenient
factor to use if the Vx and Vy input voltages are expected to be
large, say ±1 0 V. Obviously with Vx = Vy = 10 V and a scale
factor of unity, the device could not hope to provide a 100 V
output, so the scale factor is set to 1/10 and provides an output
scaled down by a factor often. For many applications it may be
desirable to set K = 112 or K = 1 or even K = 100. This can be
accomplished by adjusting RX Ry and RL appropriately.
The selection of RL is arbitrary and can be chosen after
resistors RX and Ry are found. Note in Figure 16 that Ry is
62 kQ while RX is 30 kQ. The reason for this is that the "Y" side
of the multiplier exhibits a second order nonlinearity whereas
the "X" side exhibits a simple nonlinearity. By making the Ry
resistor approximately twice the value of the RX resistor, the
linearity on both the "X" and "Y" sides are made equal. The
selection of tile RX and Ry resistor values is dependent upon
the expected amplitude of Vx and Vy inputs. To maintain a
specified linearity, resistors RX and Ry should be selected
according to the following equations:
RX ~ 3 Vx (max) in kQ when Vx is in Volts,

Offset Adjustment
The noninverting input of the op amp provides a convenient
point to adjust the output offset Voltage. By connecting this
pointto the wiper arm of a potentiometer (P3), the output offset
voltage can be adjusted to zero (see Offset and Scale Factor
Adjustment Procedure).
The input offset adjustment potentiometers, PI and P2
will be necessary for most applications where it is desirable
to take advantage of the multiplier's excellent linearity
characteristics. Depending upon the particular application,
some of the potentiometers can be omitted (see Figures 17,
19,22,24 and 25).
Offset and Scale Factor Adjustment Procedure
The adjustment procedure for the circuit of Figure 16 is:
A.

B.

Ry ~ 6 \ly (max) in kQ when Vy is in Volts.
For example, if the maximum input on the "X" side is ±1.0 V,
resistor RX can be selected to be 3.0 kQ. If the maximum input
on the "Y" side is also ±1.0 V, then resistor Ry can be selected
to be 6.0 kQ (6.2 kQ nominal value). If ascale factor of K= 10 is
desired, the load resistor is found to be 47 kQ. In this example,
the multiplier provides a gain of 20 dB.
Operational Amplifier Selection
The operational amplifier connection in Figure 16 is a
simple but extremely accurate current-to-voltage converter.
The output current of the multiplier flows through the feedback
resistor RL to provide a low impedance output voltage from the
op amp. Since the offset current and bias currents of the op
amp will cause errors in the output voltage, particularly with
temperature, one with very low bias and offset currents is
recommended. The MC1456 or MC1741 are excellent
choices for this application.
Since the MC1494 is capable of operation at much higher
frequencies than the op amp, the frequency characteristics of
the circuit in Figure 16 will be primarily dependent upon the
operational amplifier.
Stability
The current-to-voltage converter mode is a most
demanding application for an operational amplifier. Loop gain
is at its maximum and the feedback resistor in conjunction with
stray or input capacitance at the multiplier output adds
additional phase shift. It may therefore be necessary to add
(particularly in the case of internally compensated op amps) a
small feedback capacitor to reduce loop gain at the higher
frequencies. A value of 10 pF in parallel with RL should be
adequate to insure stability over production and temperature
variations, etc.
An externally compensated op amp might be employed
using slightly heavier compensation than that recommended
for unity-gain operation.

C.

D.

E.

X Input Offset
1. Connect oscillator (1.0 kHz, 5.0 Vp-p sinewave)
to the "Y" input (Pin 9).
2. Connect "X" input (Pin 10) to ground.
3. Adjust X-offset potentiometer, P2 for an AC null
at the output.
Y Input Offset
1. Connect oscillator (1.0 kHz, 5.0 Vp-p sinewave)
to the "X" input (Pin 10).
2. Connect "Y" input (Pin 9) to ground.
3. Adjust V-offset potentiometer, P1 for an AC null
at the output.
Output Offset
1. Connect both "X" and "Y" inputs to ground.
2. Adjust output offset potentiometer, P3 until the
output voltage Vo is 0 Vdc.
Scale Factor
1. Apply +10 Vdc to both the "X" and "Y" inputs.
2. Adjust P4 to achieve -10 V at the output.
3. Apply -1 0 Vdc to both "X" and "Y" inputs and
check for Vo = -10 V.
Repeat steps A through D as necessary.

The ability to accurately adjust the MC1494 is dependent on
the offset adjust potentiometers. Potentiometers should be of
the "infinite" resolution type rather than wirewound. Fine
adjustments in balanced-modulator applications may require
two potentiometers to provide "coarse" and "fine" adjustment.
Potentiometers should have low temperature coefficients and
be free from backlash.
Temperature Stability
While the MC1494 provides excellent performance in itself,
overall performance depends to a large degree on the quality
of the external components. Previous discussion shows the
direct dependence on RX, Ry and RLand indirect dependence
on Rl (through 11). Any circuit subjected to temperature

variations should be evaluated with these effects in mind.
Bias Currents
The MC1494 multiplier, like most linear ICs, requires a DC
bias current into its input terminals. The device cannot be
capacitively coupled at the input without regard for this bias
current. If inputs Vx and Vy are able to supply the small bias
current (~0.5 ~A) resistors R can be omitted (see Figure 16). If
the MC1494 is used in an AC mode of operation and

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
11-18

MC1494, MC1594
capacitive coupling is used the value of resistor R can be any
reasonable value up to 100 kQ. For minimum noise and
optimum temperature performance, the value of resistor R
should be as low as practical.
Parasitic Oscillation
When long leads are used on the inputs, oscillation may
occur. In this event, an RC parasitic suppression network
similar to the ones shown in Figure 16 should be connected
directly to each input using short leads. The purpose of the
network is to reduce the "a" of the source-tuned circuits which
cause the oscillation.
Inability to adjust the circuit to within the specified accuracy
may be an indication of oscillation.
AC OPERATION

General
For AC operation, such as balanced modulation, frequency
doubler, AGC, etc., the op amp will usually be omitted as well
as the output offset adjust potentiometer. The output offset
adjust potentiometer is omitted since the output will normally
be AC coupled and the DC voltage at the output is of no
concern providing it is close enough to zero volts that it will not
cause clipping in the output waveform. Figure 17 shows a
typical AC multiplier circuit with a scale factor K=1. Again,
resistor RX and Ry are chosen as outlined in the previous
section, with RL chosen to provide the required scale factor.
Figure 17. Wideband Multiplier
3.0k

6.2k

+15V -15V

11

ey

I-C>--_ _-

........eo

R

-=

10

ex

R

13

..51k
20k

K=l

Ox (maxi =ey(max) =1.0 V

The offset voltage then existing althe output will be equal to
the offset current times the load resistance. The output offset
current of the MC1494 is typically 17!IA and 35 ~A maximum.
Thus, the maximum output offset would be about 160 mY.

Bandwidth
The bandwidth of the MC1494 is primarily determined by
two factors. First, the dominant pole with be determined by the
load resistor and the stray capacitance at the output terminal.
For the circuit shown in Figure 17, assuming a total output

capacitance (CO) of 10 pF, the 3.0 dB bandwidth would be
approximately 3.4 MHz. If the load resistor were 47 kn, the
bandwidth would be approximately 340 kHz.
Secondly, a "zero" is present in the frequency response
characteristic for both the "X" and "Y" inputs which causes the
output signal to rise in amplitude at a 6 dB/octave slope at
frequencies beyond the breakpoint of the "zero". The "zero" is
caused by the parasitic and substrate capacitance which is
related to resistors RX and Ry and the transistors associated
with them. The effect of these transmission "zeros" is seen in
Figures 9 and 10. The reason for this increase in gain is due to
the bypassing of RX and Ryat high frequencies. Since the Ry
resistor is approximately twice the value of the RX resistor, the
zero associated with the "Y" input will occur at approximately
one octave below the zero associated with "X" input. For RX =
30 kn and Ry = 62 kn, the zeros occur at 1.5 MHz for the "X"
input and 700 kHz for the "Y" input. These two measured
breakpoints correspond to a shunt capacitance of about
3.5 pF. Thus, for the circuit of Figure 17, the "X" input zero
and "Y" input zero will be at approximately 15 MHz and
7.0 MHz respectively.
It should be noted that the MC1494 multiplies in the time
domain, hence, its frequency response is found by means of
complex convolution in the frequency (Laplace) domain. This
means that if the "X" input does not involve a frequency, it is not
necessary to consider the "X" side frequency response in the
output product. Likewise, for the "Y" side. Thus, for
applications such as a wideband linear AGC amplifier which
has a DC voltage as one input, the multiplier frequency
response has one zero and one pole. For applications which
involve an AC voltage on both the "X" and "Y" side such as a
balanced modulator, the product voltage response will have
two zeros and one pole, hence, peaking may be present in
the output.
From this brief discussion, it is evident that for AC
applications; (1 ) the value of resistors RX, Ryand RL should be
kept as small as possible to achieve maximum frequency
response, and (2) it is possible to select a load resistor RL such
that the dominant pole (RL, CO) cancels the input zero (RX,
3.5 pF or Ry, 3.5 pF) to give a flat amplitude characteristic with
frequency. This is shown in Figures 9 and 10. Examination of
the frequency characteristics of the "X" and "Y" inputs will
demonstrate that for wide band amplifier applications, the best
tradeoff with frequency response and gain is achieved by
using the "Y" input for the AC signal.
For AC applications requiring bandwidths greater than
those specified for the MC1494, two other devices are
recommended. For modulator-demodulator applications, the
MC1496 may be used up to 100 MHz. For wideband multiplier
applications, the MC1495 (using small collector loads and AC
coupling) can be used.
Slew-Rate
The MC1494 multiplier is not slew-rate limited in the
ordinary sense that an op amp is. Since all the signals in the
multiplier are currents and not voltages, there is no charging
and discharging of stray capacitors and thus no limitations
beyond the normal device limitataions. However, it should be
noted that the quiescent current in the output transistors is

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
11-19

l1li

MC1494, MC1594
0.5 mA and thus the maximum rate of change of the output
voltage is limited by the output load capacitance by the
simple equation:

Figure 18. Phase Vector Error

Slew Rate I1VO= !Q
I1T
C
Thus, if Co is1 0 pF, the maximum slew rate would be:
I1VO = 0.5 x 10-3 = 50 V/Jls
I1T
10x10-12
This can be improved, if necessary, by the addition of an
emitter-follower or other type of buffer.
Phase Vector Error
All multipliers are subject to an error which is known as the
phase vector error. This error is a phase error only and does
not contribute an amplitude error per se. The phase vector
error is best explained by an example. If the "X" input is
described in vector notation as;
X

= A40°

and the "Y" input is described as;
Y

= B40°

then the output product would be expected to be;
VO= AB40° (see Figure 18)
However, due to a relative phase shift between the "X" and
"Y" channels, the output product will be given by:

meaningless. If phase of the output product is not important,
then neither is the phase vector error. If phase is important,
such as in the case of double sideband modulation or
demodulation, then a 1% phase vector error will represent a
1% amplitude error a the phase angle of interest.
Circuit Layout
If wideband operation is desired, careful circuit layout must
be observed. Stray capacitance across RX and Ry should be
avoided to minimize peaking (caused by a zero created by the
parallel RC circuit).
DC APPLICATIONS
Squaring Circuit
If the two inputs are connected together, the resultant
function is squaring:
VO= KV2
where K is the scale factor (see Figure 19).
However, a more careful look at the multiplier's defining
equation will provide some useful information. The output
voltage, without initial offset adjustments is given by:
Va = K(VX + Viox -VX off) (Vy + Vioy -Vy off) + VOO

Va = AB4~
Notice that the magnitude is correct but the phase angle of the
product is in error. The vector (V) associated with this error is
the "phase vector error". The startling fact about the phase
vector error is that it occurs and accumulates much more
rapidly than the amplitude error associated with frequency
response. In fact, a relative phase shift of only 0.57 0 will result
in a 1% phase vector error. For most applications, this error is

•

(Refer to "Definitions" section for an explanation of terms.)
With Vx = Vy = V (squaring) and defining;
EX = Viox - Vx (off)
Ey = Vioy - Vy (off)
The output voltage equation becomes:
Va = KVx2+ KVx (EX + Ey) + KEx Ey + VOO

Figure 19. MC1594 Squaring Circuit
30k

+15V -15V

62k

II
SDk

22k

V
10pF
MCI494
14

'~I
510

I 3 6
16k

13

4

51k

I"pm

Offset
P3
-15V

+15V

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
11-20

MC1494, MC1594
Figure 20 illustrates why this is so. For Vx > 0 the transfer
function through the multiplier is noninverting. Its output is fed
to the inverting input of the op amp Thus, operation is in the
negative feedback mode and the circuit is DC stable.

This shows that all error terms can be eliminated with only
three adjustment potentiometers, eliminating one of the input
offset adjustments. For instance, if the ·X" input offset
adjustment is eliminated, E x is determined by the internal
offset (Viox) but E y is adjustable to the extentthat the (E X + E y)
term can be zeroed. Then the output offset adjustment is used
to' adjust the Voo term and thus zero the remaining error terms.
An AC procedure for nulling with three adjustments is:
A.

Figure 20. Basic Divide Circuit Using Multiplier
Vx

AC Procedure:
1. Connect oscillator (1.0 kHz, 15 Vp-p) to input.
2. Monitor output at 2.0 kHz with tuned voltmeter and
adjust P4 for desired gain ( Be sure to peak
response of voltmeter).
3. Tune voltmeter to 1.0 kHz and adjust P1 for a minimum
output voltage.
4. Ground input and adjust P3 (output offset) for
Vdcout.
5. Repeat steps 1 through 4 as necessary.

IWXVy

Vz=-IWXVy

or
-Vz
Vo= IWx
Vz

>--.....--.vo

o

B.

Should Vx change polarity, the transfer function through
the multiplier becomes inverting, the amplifier has positive
feedback and latch-Up results. The problem resulting from Vx
being near zero is a result of the transfer through the multiplier
being near zero. The op amp is then operating with a very high
closed-loop gain and error voltages can thus become effective
in causing latch-Up.
The other mode of latch-up results from the output voltage
of the op amp exceeding the rated common mode input
voltage of the multiplier. The input stage of the multiplier
becomes saturated, phase reversal results, and the circuit is
latched up. The circuit of Figure 21 protects against this
happening by clamping the output swing of the op amp to
approximately ± 10.7 V. Five percent tolerance, 10 V zeners
are used to assure adequate output swing but still limit the
output voltage of the op amp from exceeding the common
mode input range of the MC1494.
Setting up the divide circuit for reasonably accurate
operation is somewhat different from the procedure for the
multiplier itself. One approach, however, is to break the
feedback loop, null out the multiplier circuit, and then close
the loop.

DC Procedure:
1. Set Vx = Vv = 0 V and adjust P3 (output offset
potentiometer) such that Vo = 0 Vdc.
2. Set Vx = Vv = 1.0 V and adjust P1 (V input offset
potentiometer) such that the output voltage is
-0.100 V.
3. Set Vx = Vv = 10 Vdc and adjust P4 (load resistor)
such that the output voltage is -10 V.
4. Set Vx = Vv = -10 Vdc and check that Vo = -10 V.
5. Repeat steps 1 through 4 as necessary.

Divide
Divide circuits warrant a special discussion as a result of
their special problems. Classic feedback theory teaches that if
a multiplier is used as a feedback element in an operational
amplifier circuit, the divide function results. Figure 20
illustrates the theoretical simplicity of such an approach and a
practical realization is shown in Figure 21.
The characteristic "failure" mode of the divide circuit is
latch-Up. One way it can occur is if Vx is allowed to go
negative, or in some cases, if Vx approaches zero.

Figure 21. Practical Divide Circuit

III

RL

~

3Dk

SDk

62k

22k

Vz

I

lDpF

lN5240A ,
(IDV)
or Equivalent
Vo

-IDVZ
Vo='Vj(

tl5V

-15V

O--.....-vo

Square Root
A special case of the divide circuit in which the two inputs to
the multiplier are connected together results in the square root
function as indicated in Figure 22. This circuit too may suffer

from latch-up problems similar to those of the divide circuit.
Note that only one polarity of input is allowed and diode
clamping (see Figure 23) protects against accidental latch-up.
This circuit too, may be adjusted in the closed-loop mode:
1. Set Vz = -0.01 Vdc and adjust P3 (output offset) for
Va = 0.316 Vdc.
2. Set Vz to -0.9 Vdc and adjust P2 ("X" adjust) for
Va = +3.0 Vdc.
3. Set Vz to -10 Vdc and adjust P4 (gain adjust) for
VO=+10Vdc.
4. Steps 1 through 3 may be repeated as necessary to
achieve desired accuracy.
Note: Operation near 0 V input may prove very inaccurate,
hence, it may not be possible to adjust Va to zero but
rather only to within 100 mV to 400 mV of zero.
AC APPLICATIONS
Wideband Amplifier with Linear AGC
If one input to the MC1494 is a DC voltage and a signal
voltage is applied to the other input, the amplitude of the output
signal can be controlled in a linear fashion by varying the DC
voltage. Hence, the multiplier can function as a DC coupled,
wide band amplifier with linear AGC control.
In addition to the advantage of linear AGC control, the
multiplier has three other distinct advantages over most other
types of AGC systems. First, the AGC dynamic range is
theoretically infinite. This stems from the basic fact that with
Vdc applied to the AGC, the output will be zero regardless of
the input. In practice, the dynamic range is limited by the ability
to adjust the input offset adjust potentiometers. By using
cermet multi-turn potentiometers, a dynamic range of 80 dB
can be obtained. The second advantage of the multiplier is that
variation of the AGC voltage has no effect on the signal
handling capability of the signal port, nor does it alter the input
impedance of the signal port. This feature is particularly
important in AGC systems which are phase sensitive. A third
advantage of the multiplier is that the output voltage swing
capability and output impedance are unchanged with
variations in AGC voltage.

o

Figure 23. Square Root Circuit
Vz

lN962B
(1 N5241 B)
(11V)
or Equivalent

1

10PF

510

-10V -10

<

1\
Vy

\

Vx

-20

l1li

-8.0 -6.0 -4.0 -2.0
0
2.0 4.0
VX, INPUT VOLTAGE M

6.0

8.0

-30
1.0

10

10

100

1000

f, FREQUENCY (MHz)

Figure 3. Circuit Schematic

.--r==;::=f=::=::::+:g 1~ Output (KXY)

1; X Input

Y Input:

;::=~=t=~~1110
13

ORDERING INFORMATION

Device

Ambient
Temperature Range

V-

MC1595D

500

MC1495L
MC1595L

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

11-26

Package
80-14

MC1495D
0° to +70°C

Ceramic DIP
-55° to +125°C

MC1495, MC1595
ELECTRICAL CHARACTERISTICS (+V = +32 V, -V = -15 V, TA = +25°C, 13 = 113 = 1.0 rnA, RX = Ry = 15 ka,
RL = 11 kQ, unless otherwise noted.)
Characteristics

Figure

Linearity (Output Error in percent of full scale)
TA = + 25°C
-10 < Vx < +10 (Vy = ±10 V)
-10 < Vy<+10 (VX = ±10 V)
TA = 0° to +70°C
-10 < Vx < +10 (Vy = ±10 V)
-10 < Vy< +10 (VX = ±10 V)

Min

±1.0
±0.5
±2.0
+1.0

±2.0
±1.0
±4.0
±2.0

ERX
ERY

-

±1.5
±3.0

--

ERX
ERY

-

-

±0.75
±1.5

-

ERX

MC1495

ERY

5

-

(K-~)
-13 RXRy
MC1495
MC1595
MC1495
MC1595

7

Differential Output Resistance (f = 20 Hz)

S

Input Bias Current

6
MC1495
MC1595
MC1495
MC1595

I _ (19 + 112)
(14 + IS)
bx - - - 2 - ' Iby = - - 2 -

Input Offset Current
119- 1121

%

-

±0.75
±O.5

-

±1.0
±0.75

-

0.1

-

-

30
35
20
35

-

RinY

-

-

RO

-

300

-

-

K
RinX

Ibx
Iby
6

MC1495
MC1595
MC1495
MC1595

114- lsl

Ilioxi
Ilioyl

Average Temperature Coefficient of Input Offset Current
(TA = 0° to + 70°C)
MC1495
MC1595
(TA =-55° to +125°C

6

Output Offset Current
MC1495
MC1595
1114- 121
Average Temperature Coefficient of Output Offset Current
(TA = 0° to + 70°C)
MC1495
(TA = -55° to + 125°C)
MC1595

6

11001

6

ITClool

Frequency Response
3.0 dB Bandwidth, RL = 11 kQ
3.0 dB Bandwidth, RL = 50 Q (Transconductance Bandwidth)
3° Relative Phase Shift Between Vx and Vy
1% Absolute Error Due to Input-Output Phase Shift

ITCliol

-

MQ

kQ
!!A

-

2.0
2.0
2.0
2.0

12
S.O
12
S.O

-

0.4
0.2
0.4
0.2

2.0
1.0
2.0
1.0

-

2.5
2.5

-

20
10

100
50

20
20

-

-

3.0
SO
750
30

-

MHz
MHz
kHz
kHz

±10.5
±11.5

±12
±13

Vdc

--40
-50

-50
-60

-

21
21

-

Vpk
mVIV

-

!!A

nAloC

!!A
nAloC

9,10

-

BW(3dB}

-

TB~&3dB}

Common Mode Input Swing
(Either Input)

MC1495
MC1595

11

f8
CMV

Common Mode Gain
(Either Input)

MC1495
MC1595

11

ACM

Common Mode Quiescent
Output Voltage

Unit

-

ESQ

-

MC1495
MC1595

Input Resistance
(f = 20 Hz)

Max

-

MC1495
MC1595
MC1495
MC1595

Square Mode Error (Accuracy in percent of full scale after
Offset and Scale Factor adjustment)
MC1495
TA = +25°C
MC1595
TA = 0° to +70°C
TA = -55° to + 125°C

Typ

%

MC1595

TA = -55° to + 125°C
-10 < Vx < +10 (Vy = ±10 V)
-10 < Vy < +10 (VX = ±10 V)

Scale Factor (Adjustable)

Symbol

5

12

VOl
V02

Differential Output Voltage Swing Capability

9

Power Supply Sensitivity

12

Vo
S+
S-

Power Supply Current

12

17

DC Power Dissipation

12

PD

-

,

-

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

11-27

±14
5.0
10

dB
Vdc

6.0

7.0

rnA

135

170

mW

MC1495, MC1595
MAXIMUM RATINGS (TA

=+25°C. unless otherwise noted.)
Symbol

Value

Unit

!:N

30

Vdc

Differential Input Signal

V1Z-V9
V4-V8

±(6+113 RX)
±(6+13 Ry)

Vdc

Maximum Bias Current

13
113

10
10

mA

PD

862
145
750
5.0

mW
mW/oC
mW
°CIW

Rating
Applied Voltage
(VZ-V1. V14-V1. V1-V9. V1-V12. V1-V4.
V1-Va.V1Z-V7.Vg-V7.VS-V7.V4-V7)

Power Dissipation (Package Limitation)
D Suffix. Plastic Package
Derate above TA = +25°C
J Suffix. Ceramic Package
Derate above TA = +25°C

PD

Operating Temperature Range

°C

TA
MC1495
MC1595

Oto +70
-55 to +125

Storage Temperature Range

Tstg

~5to+150

°C

Figure 4. linearity (Using Null Technique)
V+
+15V
3.0k

10k

40k

101e

10k
14
33k

Offset Adjust
See Figure 13 +-_ _ _-'

10k
Scale

Factor
Adjust

5k

OUlput
Offset
Adjust

4

V~--------~----~--------------~-------4
-15V
N01E:
Adjust
"Scale
Factor
Adjusr
lor
a
null
in
VE.
.:;!;.O.II1F
This schematic lor illustrative purposes only, not specified lor test conditions.

Figure 5. Linearity (Using

X-v Plotter Technique)
32V

Rl
1 9.1k

RLI = 11

Vz
Offset Adjust {
(See Figures 13 and 14)

2
14 RLI

V
X

=11k

~O

Plotter
"'Input

R13= 13.7k

-15V

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
11-28

X-V
Plotter

MC1495, MC1595
Figure 7. Input Resistance

Figure 6. input and Output Current
+32V

Ry= 15k RX= 15k

+32V

"I = 1.0 V (rms)
20Hz
tOM
tOM

2 11k
MC1495

5.6k

14 11k

-= 1.0M

7 13

tOM

12k

J.

5.0k

O.1IlF
-15V

Figure 9. Bandwidth (RL = 11 kO)

Figure 8. Output Resistance
+32V

Ry=15k RX=15k
111

+32V

9.1k

111 9.1k
2 11k

"2

RL = 11k

MC1495

MC1495
11k

14

"1
tOV(rms)
20Hz

12k

5.0k

~

11k

13

'V

13

14

1:. O.lIlF
-=

R13
13.7k
~O.lIlF

13.7k

O.lIlF
-15V

RO=RLI.:!..
"2

-15V

-21

Ry=510 Rx=510

+15V

111

+32V

15k

tOk

9.1k

50

"j

MC1495

14

+

R13
13.7k
~O.lIlF

11k

50
14

13

K=40

l1li

Figure 11. Common Mode Gain and
Common Mode Input Swing

Figure 10. Bandwidth (RL = 50 0)

1_ O.lIlF

i tOmA

"f "a
=;=

,

CL < 3.0pF

5.0k

.....
-15V

-15V

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
11-29

11k

Vo

ACM = 20 log

c~~y
Vo

or 20 log CMVX

MC1495, MC1595
Figure 13. Offset Adjust Circuit

Figure 12. Power Supply Sensitivity
+32V

Y'

.32V
15k

15k

R

...--.-

9.1k
11k

11k
6.2V

To Pin 8

PoUI

YOfIse1
Adjust

- - - 10k

2.0k

POU2 To Pin 12
10k.- XOffsel
Adjust

L..-J--

4.3k
2.0k
10k
-15V

s. = I~ (VOl - Yo211

2N2905A
or Equivalent

~Y.

22k

-15Y

-15V

s- =.'-1~....:(V-"O,,-1-_Y-"o",,211
~Y-

Figure 14. Offset Adjust Circuit (Alternate)
Y'
R

5.W
,~

-41--

To Pin 8
YOffset
Adjust

Pol #1
___ 10k

Pol #2 To Pin 12

10k ....... XOffset
Adjust

-41-"C

5.1Y
2k
-15V

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
11-30

MC1495, MC1595
Figure 15. Linearity versus Temperature
2.0

~

""

1.2

=;.. 1.0
cc

~

J

0.110

I\..

1.8
1.6

~
12 1.4

~

Figure 16. Scale Factor versus Temperature

cc 0.105

"""

.............

0.8

~

-

E~

............

0.6

./

ERY

..............

0.4

~

§
if

--

~ 0.100

(§

,.;:
0.095

-25

0
25
50
75
TA • AMBIENT TEMPERATURE (DC)

100

-55

125

-25

Figure 17. Error Contributed by
Input Differential Amplifier
~ 1.0

~
~

o

~

~

0.8

\

~ 0.4

~
cc-

100

1.0

en

0.8

::>
u..
u..

0.6

Vx = Vy =±5.0 V Max
13 = 113 = 1.0 mAde

IZ

w

~

ffi

o

10

\

0

~ 0.2

12

(,)

---

cc
w

0.4

r\

~

D..

cc0
cc
cc
w

f--

14
16
RXorRy(kQ)

18

0.2

..........

o

20

4.0

6.0

~ I--

8.0
10
RXorRy(kQ)

12

14

l1li

Figure 19. Maximum Allowable Input Voltage versus Voltage at Pin 1 or Pin 7
14

'i

12

:;
::>

10

~

8.0

?;

6.0

c:.

",,"

",,""
",,""

",,""

",,"""",

:;

:;

::;

~

125

...J
...J

\

~

0
25
50
75
TA • AMBIENT TEMPERATURE (DC)

Figure 18. Error Contributed by
Input Differential Amplifier

Vx = Vy= ± 10 V Max
13 = 113 = 1.0 mAde

0.6

'-..... r--

[

0_55

::I

"'"

!I<_ _ +10V
VxorVy

III

resistors RX and Ry must be chosen large enough so that
nonlinear base-emitter voltage variation can be ignored.
Figures 17 and 18 show the error expected from this source as
a function of the values of RX and Ry with an operating current
of 1.0 mA in each side of the differential amplifiers (Le., 13 = 113
= 1.0 mAl.
3 dB Bandwidth and Phase Shift
Sandwidth is primarily determined by the load resistors and
the stray multiplier output capacitance and/or the operational
amplifier used to level shift the output. If wide band operation is
desired, low value load resistors and/or a wideband
operational amplifier should be used. Stray output capacitance will depend to a large extent on circuit layout.
Phase shift in the multiplier circuit results from two sources:
phase shift common to both X and Y channels (due to the load
resistor-output capacitance pole mentioned above) and
relative phase shift between X and Y channels (due to
differences in transadmittance in the X and Y channels). If the
input to output phase shift is only 0.6°, the output product of
two sine waves will exhibit a vector error of 1%. A 3° relative
phase shift between Vx and Vy results in a vector error of 5%.
Maximum Input Voltage
VX(max), VY(max) input voltages must be such that:
VX(max) <113 Ry
Vy(max) <13 Ry
Exceeding this value will drive one side of the input amplifier to
"cutoff" and cause nonlinear operation.
Current 13 and 113 are chosen at a convenient value
(observing power dissipation limitation) between 0.5 mA and
2.0 mA, approximately 1.0 mAo Then RX and Ry can be
determined by considering the input signal handling
requirements.
For VX(max) = VY(max) = 10 V;
10 V
RX = Ry > 1.0 mA = 10 kQ.

For example, if the maximum deviation, VE(max), is
±100 mV and the full scale output is 10 v, then the percentage
error is:
ER = VE(max) .100 = 100.10-3 .100 = ±1.0%.
Vo(max)
10
Linearity error may be measured by either of the following
methods:
1. Using an X-V plotter with the circuit shown in Figure
5, obtain plots for X and Y similar to the one shown
above.
2. Use the circuit of Figure 4. This method nulls the level
shifted output of the multiplier with the original input.
The peak output of the null operational amplifier will
be equal to the error voltage, VE (max).
One source of linearity error can arise from large signal
nonlinearity in the X and Y input differential amplifiers. To avoid
introducing error from this source, the emitter degeneration

The equation IA - IS

=

is derived from IA - IS =

2VXVy
RX Ry 13
2VX Vy
(RX + 2kT ) (Ry + 2kT ) 13
ql13
q l3

with the assumption RX» 2kT and Ry» 2klT .
ql13
q3
At TA = +25°C and 113 = 13 = 1.0 mA,
2kT = 2kT = 52
ql13 ql3

n.

Therefore, with RX = Ry = 10 kQ the above assumption is
valid. Reference to Figure 19 will indicate limitations of
VX(max)orVY(max)dueto V 1andV7. Exceedingtheselimitswill
cause saturation or "cutoff" of the input transistors. See Step 4
of General Design Procedure for further details.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
11-32

MC1495, MC1595
If an operational amplifier is used for level shift, as shown in
Figure 21, the output swing (of the multiplier) is greatly
reduced. See Section 3 for further details.

Maximum Output Voltage Swing
The maximum output voltage swing is dependent upon the
factors mentioned below and upon the particular circuit being
considered.
For Figure 20 the maximum output swing is dependent
upon V+ for positive swing and upon the voltage at Pin 1 for
negative swing. The potential at Pin 1 determines the
quiescent level for transistors 05, aS, 07 and aS. This
potential should be related so that negative swing at Pins 2 or
14 does not saturate those transistors. See General Design
Procedure for further' information regarding selection of
these potentials.

GENERAL DESIGN PROCEDURE
Selection of component values is best demonstrated by the
following example. Assume resistive dividers are used at the X
and Y-inputs to limit the maximum multiplier input to ± 5.0 V
[VX = VY(max)J for a ± 10 V input [VX' = VY'(max)J
(see Figure 21). If an overall scale factor of 1110 is desired,
then V = VX' Vy' = (2VX) (2Vy) = 4/10 Vx Vy
,0
10
10
Therefore, K = 4/10 for the multiplier (excluding the divider
network).
Step 1. The fist step is to select current 13 and current 113.
There are no restrictions on the selection of either of these
currents except the power dissipation of the device. 13 and 113
will normally be 1.0 mA or 2.0 mAo Further, 13 does not have to
be equal to 113, and there is normally no need to make them
different. For this example, let

Figure 20. Basic Multiplier

10
Vx { _ _-;1:>-2-j

f-lo-4_______

1

Vo

MC1495

Vy{~

13

= 113 = 1.0 mAo

VO=KVXVy

3
R3

I

t 13

13

2RL
K--- RXRy l3

R13

V-

Figure 21. Multiplier with Operational Amplifier Level Shift
-15V

-15V

.-------_--~--_+_--+_e

Ry
10k

RX
10k

Rl
3.0k

RO
3.0k

+15V

RO
3.0k

10k

>-0-.-.

MC1741C
10k
14
VX' _""Vv\r-,,--o--I
Vx L , - - - - . - : - - - r - - r
10k
13
12
3
13
113
R13
RL {
12k
12k

t

t

R3 {

-IOV~VX~+IOV
-IOV~Vy~+IOV

Scale
Factor
Adiust

-=

P4
YOffset
Adiust
2.0k

+15V

PI

X Offset
Adiust

10k

RL

5.0k

5.0k
P3

20k

18k

Output
Offset
Adiust

-=
2.0k

_-V'-"'r---+------"""'-+-Y\O'v-----<>--+-.... Vy

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
11-36

MC1495, MC1595
Divide Circuit

In terms of percentage error,

Consider the circuit shown in Figure 24 in which the
multiplier is placed in the feedback path of an operational
amplifier. For this configuration, the operational amplifier will
maintain a ''virtual ground" at the inverting H input. Assuming
that the bias current of the operational amplifier is negligible,
then 11 = 12 and,
KVXVy
-VZ
--=
(1)
R1
R2
V _ -R1 ~
y- R2 K Vx

(2)

If R1=R2,

-VZ
Vy=KVX

(3)

If R1= KR2,

-VZ
Vy= Vx

(4)

Solving for Vy,

Percentage error = error x 100%
actual
or from Equation (5),

~
KVX

PEO -

(7)

Two things should be emphasized concerning Figure 25.
1. The input voltage (VX') must be greater than zero and
must be positive. This insures that the current out of Pin
2 of the multiplier will always be in a direction compatible
with the polarity of VZ.
2. Pin 2 and 14 of the multiplier have been interchanged in
respect to the operational amplifiers input terminals. In
this instance, Figure 25 differs from the circuit
connection shown in Figure 21; necessitated to insure
negative feedback around the loop.

(5)

-10VZ 10AE
Vx +vx-

[R2] AE
-1'1'1- Vz

-R2 K- Vx

A suggested adjustment procedure for the divide circuit.
1. Set Vz = 0 V and adjust the output offset potentiometer
(P4) until the output voltage (VO) remains at some (not
necessarily zero) constant value as VX' is varied
between +1.0 V and +10 V.
2. Keep Vz at 0 V, set VX' at + 10 V and adjust the y input
offset potentiometer (P1) until Vo = 0 V.
3. Let VX' = Vz and adjust the X-input offset potentiometer
(P2) until the output voltage remains at some (not
necessarily -10 V) constant value as Vz = VX' is varied
between +1.0 and + 10 V.
4. Keep VX' = Vz and adjust the scale factor potentiometer
(P3) until the average value ofVO is-1 0 Vas VZ= VX'is
varied between + 1.0 V and +10 V.
5. Repeat steps 1 through 4 as necessary to achieve
optimum performance.

where AE is the error voltage at the output of the multiplier.
From this equation, it is seen that divide accuracy is strongly
dependent upon the accuracy at which the multiplier can be
set, particularly at small values of Vy. For example, assume
that R1 = R2, and K = 1/10. For these conditions the output of
the divide circuit is given by:
Vy=

Vz =

From Equation 7, the percentage error is inversely related
to voltage Vz (i.e., for increasing values of VZ, the percentage
error decreases).
A circuit that performs the divide function is shown in
Figure 25.

Hence, the output voltage is the ratio of Vz to Vx and
provides a divide function. This analysis is, of course, the ideal
condition.lfthe multiplier error is taken into account, the output
voltage is found to be:
AE
[ R1 ] Vz
VY=-_R2K_ VX+ KVX

[~]

(6)

From Equation 6, it is seen that only when Vx = 10 V is the
error voltage of the divide circuit as low as the error of the
multiply circuit. For example, when Vx is small, (0.1 V) the
error voltage of the divide circuit can be expected to be a
hundred times the error of the basic multiplier circuit.

III

Figure 25. Divide Circuit
-15V

-15V

I

----.--t-... +15V

r--~O-----------......- Vo
1W02 =-VZ

or
VO=

II~I

Square Root
A special case of the divide circuit in which the two inputs to
the multiplier are connected together is the square root
function as indicated in Figure 26. This circuit may suffer from
latch-up problems similar to those of the divide circuit. Note
that only one polarity of input is allowed and diode clamping
(see Figure 27) protects against accidental latCh-Up.
This circuit also may be adjusted in the closed-loop mode
as follows:
1. Set Vz to -0.01 V and adjust P4 (output offset) for
Vo = +0.316 V, being careful to approach the output
from the positive side to preclude the effect of the
output diode clamping.
2. Set Vz to -0.9 V and adjust P2 (X adjust) for
VO= +3.0V.
3. Set Vz to -10 V and adjust P3 (scale factor adjust)
for Vo = +10 V.
4. Steps 1 through 3 may be repeated as necessary to
achieve desired accuracy.

AC APPLICATIONS
The applications that follow demonstrate the versatility of
the monolithic multiplier. If a potted multiplier is used for these
cases, the results generally would not be as good because the
potted units have circuits that, although they optimize DC
multiplication operation, can hinder AC applications.
Frequency doubling often is done with a diode where
the fundamental plus a series of harmonics are
generated. However, extensive filtering is required to obtain
the desired harmonic, and the second harmonic obtained
under this technique usually is small in magnitude and
requires amplification.
When a multiplier is used to double frequency the second
harmonic is obtained directly, except for a DC term, which can
be removed with AC coupling.
eo = KE2 cos 2 wt
KE2
eo =-2- (1 + cos 2wt).
A potted multiplier can be used to obtain the double
frequency component, but frequency would be limited by its
internal level-shift amplififer. In the monolithic units, the
amplifier is omitted.
In a typical doubler circuit, conventional ± 15 V supplies are
used. An input dynamic range of 5.0 V peak-to-peak is
allowed. The circuit generates wave-forms that are double
frequency; less than 1% distortion is encountered without
filtering. The configuration has been successfully used in
excess of 200 kHz; reducing the scale factor by decreasing
the load resistors can further expand the bandwidth.
Figure 29 represents an application for the monolithic
multiplier as a balanced modulator. Here, the audio input
signal is 1.6 kHz and the carrier is 40 kHz.

Figure 27. Square Root Circuit
-15V

-15V

III

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

11-38

MC1495, MC1595
The defining equation for balanced modulation is

Figure 28. Frequency Doubler
Ry
8.2k

K(Emcos comt) (Ec cos roct) =

RX
8.2k

VCC+15V

KEc Em [cos (coc + com)t + cos (coc - com) t]

2
Ecos col
1<5.0Vp.pl
Offset
Y
Adjust _ - - o - j

'Select
S.8k

1.0l1 F

r

CI'

E2

eO~20cos2cot

J

essbecarrier =

-15V

When two equal cosine waves are applied to X and Y, the result
is a wave shape of twice the input frequency. For this example
the input was a 10kHz signal, output was 20 kHz.

(A)
RX
8.2k

[cos (2roc + com)t + cos (roc) tl.

Amplitude Modulation
The multiplier performs amplitude modulation, similar to
balanced modulation. when a DC term is added to the
modulating signal with the V-offset adjust potentiometer (see
Figure 30).

+15V

ey = Ecos COmt
ex = E cos "
L.

1.2

0

-55'e

.J:

-

25'e

-

I

/

125'e _ _

-

1.0
0.8
0.6

5.0V S Vee S 15V

I

o

5.0

1.0

15

10
Vee. SUPPLY VOLTAGE (Vdc)

2.0

10

II

20

50

100

Figure 9. Low Output Voltage

(@Vee= 10 Vdc)
10

5.0

ISource (rnA)

Figure 8. Low Output Voltage

I

(@Vee= 15 Vdc)
10

II

II

-55'~

~55'e I

25'e

/25'e

1/125'e

.".

1.0

~

~

-

>0

f/

o.1

.".

125 cC

o

(@ Vee = 5.0 Vdc)

1.0

~

1.6

0.4

0.4

Figure 7. Low Output Voltage
0

~

~

Id: ~

V

-55'e

1.8

0.2

I

0.1
0.2
0.3
VT (min). MINIMUM TRIGGER VOLTAGE
(XVee· Vdc)

~

4.0

.B 2.0

70'e -

2.0

2~

~ 8.0

-55

Figure 6. High Output Voltage

~5\
~

r-

~

~

k:;~

1.0
25'e

~

>0

125'~

0.1

I
I ./

-55'e

~25'e

0.1

tIP

125'e

55'e

~

I"""

-55'C -

p-

0.0 1
1.0

2.0

5.0

10

20

0.01

50 100

I
1.0

2.0

5.0

IS~k.(mA)

Figure 10. Delay Time
versus Supply Voltage

50

1.0

100

2.0

5.0

10
20
ISink.(mA)

50

1.015

300

J

.",.

I

1.01 0
1.005

\
\

~

~
a: 1.005

-

I-- I--

~

0

z

w

"F

1.000

w

0.995

~

0

.s.

1.010

w

--

-- --

:5'

0.990

0.990

0.985

0.985
-75 -50 -25 0
25 50 75 100 125
TA. AMBIENT TEMPERATURE ('C)

o

5.0
10
15
Vee. SUPPLY VOLTAGE (Vdc)

20

"

250

F

I-

~

200

~

Q

150

a:

100

Jl.

50

1(1
f- -55'e

z

if
0
":

..... ~

O'C

I-- ~

V

~ ~5'e
~;70'e

1=

o

o

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
11-43

100

Figure 12. Propagation Delay
versus Trigger Voltage

Figure 11. Delay Time
versus Temperature

1.01 5

I I

0.01
10
20
ISink.(mA)

125'e
0.1

0.2

0.3

VT (min). MIN~~~~~V~ER VOLTAGE

0.4

MC3456
Figure 13.1/2 Representative Circuit Schematic
Control Voltage

---------- ,----

I

I I

Threshold
Comparator

r------, r----,

Trigger
Comparator

V~O-~~--~~--~--++~~--~~~-----4~~U--'--~

Threshold

Output

Trigger o---------+-+-l

Reset

100

GENERAL OPERATION
The MC3456 is a dual timing circuit which uses as its
timing elements an external resistor/capacitor network. It can
be used in both the monostable (one shot) and astable modes
with frequency and duty cycle, controlled by the capacitor and
resistor values. While the timing is dependent upon the
external passive components, the monolithic circuit provides
the starting circuit, voltage comparison and other functions
needed for a complete timing circuit. Internal to the integrated
circuit are two comparators, one for the input signal and the
other for capacitor voltage; also a flip-flop and digital output
are included. The comparator reference voltages are always
a fixed ratio of the supply voltage thus providing output timing
independent of supply voltage.
Monostable Mode
In the monostable mode, a capacitor and a single resistor
are used for the timing network. Both the threshold terminal
and the discharge transistor terminal are connected together
in this mode, refer to circuit Figure 15. When the input voltage
to the trigger comparator falls below 1/3 VCC the comparator
output triggers the flip-flop so that it's output sets low. This
turns the capacitor discharge transistor "off" and drives the
digital output to the high state. This condition allows the
capacitor to charge at an exponential rate which is set by the
RC time constant. When the capacitor voltage reaches 2/3
VCC the threshold comparator resets the flip-flop. This action
discharges the timing capacitor and returns the digital output
to the low state. Once the flip-flop has been triggered by an
input Signal, it cannot be retriggered until the present timing

period has been completed. The time that the output is high is
given by the equation t = 1.1 RA C. Various combinations of R
and C and their associated times are shown in Figure 14. The
trigger pulse width must be less than the timing period.
A reset pin is provided to discharge the capacitor thus
interrupting the timing cycle. As long as the reset pin is low, the
capacitor discharge transistor is turned "on" and prevents the
capacitor from charging. While the reset voltage is applied the
digital output will remain the same. The reset pin should be tied
to the supply voltage when not in use.
Figure 14. Time Delay
100
10

/
r1

t:i

Q>

-~~
....

0.01 /

/

V

1/

/

/

V

/
/

1/ 1/ 1/
0.001 /
10/1S 100 I1s 1.0 ms 10 ms 100 ms
!d, TIME DELAY (s)

11-44

./

/

/
~
/
/
~
/
/
L~Q>
.5)/ ~~~
/
/

1/
1/

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

/

./

./
./

./

<,~ ~~

1/ V
/

/

1.0

10

100

MC3456
Figure 16. Monostable Waveforms

Figure 15. Monostable Circuit
+Vee (5.0Vlo 15V)

=::::II
!np
Uut vo/U
t age 5.0 V/cm

Resel
Vee
14, Discharge
4,.,.(1",,0)c..L-_ _L..:...
1(13)
5 (9)
2(12)
Threshold

Oulpul
1/2

MC3456

6 (8)

U

Output

.

1_ e

1-0-3(,-11,-)_--,
L-_-.__...J Control
Gnd
Voltage 0.011'

Trigger

I

III
IIJ

VolI~g&

rill

csracitor"Vortag. o

20 V/cm

II .
5.0 V/cm

II

•

1= 50 I's/cm
(RA =10 kn, c =0.011'F. RL =1.0 kg, VCC =15 V)

Pin numbers in parenthesis ( ) indicate B-Channel

Figure 17. Astable Circuit

Figure 18. Astable Waveforms

+Vcc (5.0 10 15V)

~

RL

Resel
4(10)

RA

Vcc
14
1(13) Discharge

Oulpul
5(9)

Rs

~ RL
O.OII'F
~

I

C
1= 20 I's/cm
(RA =5.1 kn, C=0.0 11'F. RL =1.0 kn, RS =3.9 kn, VCC =15 V)

Astable Mode
In the astable mode the timer is connected so that it will
retrigger itself and cause the capacitor voltage to oscillate
between 1/3 Vee and 2/3 Vee (see Figure (7).
The external capacitor charges to 2/3 Vee through RA and
RB and discharges to 1/3 Vee through RB. By varying the ratio
of these resistors the duty cycle can be varied. The charge and
discharge times are independent of the supply voltage.
The charge time (output high) is given by:

current (Pin 7 current) within the maximum rating of the discharge transistor (200 rnA).
The minimum value of RA is given by:

> Vee (Vdc) > Vee (Vdc)
RA 0.2
17 (A)
Figure 19. Free Running Frequency

tl = 0.695 (RA+RB) C
The discharge time (output low) by:
t2 = 0.695 (RB) C
Thus the total period is given by:
T = tl + t2 = 0.695 (RA + 2RB) e
The frequency of oscillation is then: f =

+
=

(RA ~:~B) e

and may be easily found as shown in Figure 19.
The duty cycle is given by: DC =

R:~2RB

To obtain the maximum duty cycle RA must be as small as
possible; but it must also be large enough to limit the discharge

1.0

10
100
1.0 k
10 k
f, FREE RUNNING FREQUENCY (Hz)

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

11-45

lOOk

MC3456
APPLICATIONS INFORMATION

Dual Astable Multivibrator
This dual astable multivibrator provides versatility not
available with single timer circuits. The duty cycle can be
adjusted from 5% to 95%. The two outputs provide two phase
clock signals often required in digital systems. It can also be
inhibited by use of either reset terminal.

Tone Burst Generator
For a tone burst generator the first timer is used as a
monostable and determines the tone duration when triggered
by a positive pulse at Pin 6. The second timer is enabled by the
high output of the monostable. It is connected as an astable
and determines the frequency of the tone.

Figure 20. Tone Burst Generator
Rese;
Ar

! !
14

+15V

vee

6

Trigger

14

TriggeJ

Output

1/2
MC3456

Discharge
2

t

Threshold

7

CI-

3

~

Reset

RA
13 Discharge
RS

12 Threshold

1/2
MC3456

9

8 Trigger

o.;t

~ntrol

O.o1flF

Gnd

Jvcc

10

5

71

Gnd

o.OlmF'r

'

C2
Gnd

- -1.44
--

t=I.1 ArCI

Figure 21. Dual Astable Multivibrator
r-------~----~----~~--~--------------~--~~------~~--------_.--o

RI

Reset

14

IN914

10k

IN914

10k

10

Reset

+15V

R2
12

output
1/2
MC3456

Discharge

Output
0.001

Voltage

T

Discharge

Trigger

Trigger

eo':::ntr::;OI....---7,-G..J
nd

CI

1/2
MC3456

Control
Voltage

II

Output

C2

l'

I

I

L-------~----*-------------------------------------------~--------~__o Gnd

0.91
t= (RI+R2)C torCI=C2

Duty Cycle

R2

""Ri+R2

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
11-46

MC3456
Pulse Width Modulation
If the timer is triggered with a continuous pulse train in the
monostable mode of operation, the charge time of the
capacitor can be varied by changing the control voltage at
Pin 3. In this manner, the output pulse width can be modulated
by applying a modulating signal that controls the threshold
voltage.

Test Sequences
Several timers can be connected to drive each other for
sequential timing. An example is shown in Figure 24 where the
sequence is started by triggering the first timer which runs for
10 ms. The output then switches low momentarily and starts
the second timer which runs for 50 ms and so forth.

Figure 22. Pulse Width Modulation Circuit

Figure 23. Pulse Width Modulation Waveforms

+Vec(50Vto15Vj

4(1°1~

RL

RA

Reset

14

Vec

Discharge

Output
Output

1/2
MC3456

2 (12)
C,Qntrol

Togger
Clock
Input

3(11)

6 (8)
Gnd

t

1 (13)
Threshold

5 (9)

C

Modulatio
Input

7

t = 0.5 ms/cm

(RA

= 10 k!"!, C = 0.02 "F, vee = 15 V)

Figure 24. Sequential Timing Circuit
VCC(5 .OVto 15Vj

9.1k

27k

Threshold

9.1k

Reset

VCC

O.Ol"F

Discharge

"V'

Discharge

1/2
MC3456

Trigger

Output

Reset

VCC

O.Ol"F

Threshold

~1.

-<>--11

>----0--

~

112
MC3456

Trigger

Output

"

O.OOl"F
Togger

50k

O.Ol"F

Threshold

~1.

1/2
MC3456

27k
Reset

VCC

Gnd
1

':'

':'

Output

O.OOl"F

Gnd

11.0"F

Control

Gnd

5•o"F

1

5.o"F

':'

Load

':'

Load

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

11-47

Load

l1li

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
11-48

Surface Mount Technology

In Brief ...
Page
Surface Mount Technology is now being utilized to offer
answers to many problems that have been created in the
use of Insertion Technology. Limitations have been reached
with insertion packages and PC board technology. Surface
Mount Technology offers the opportunity to continue to
advance state-of-the-art designs that cannot be accomplished
with Insertion Technology.
Surface Mount packages allow more optimum device
performance with the smaller Surface Mount configuration.
Intemallead lengths, parasitic capacitance and inductance
that placed limitations on chip performance, have been
reduced. The lower profile of Surface Mount packages
allows more boards to be utilized in a given amount of space.
They are stacked closer together and utilize less total
volume than insertion populated PC boards.
Printed circuit costs are lowered with the reduction of the
number of board layers required. The elimination or
reduction of the number of plated-through-holes in the
board, contribute significantly to lower PC board prices.
Surface Mount assembly does not require the
preparation of components that are common on insertion
technology lines. Surface Mount components are set
directly to the assembly line, eliminating an intermediate
step. Automatic placement equipment is available that can
place Surface Mount components at the rate of a few
thousand per hour to hundreds of thousands of components
per hour.
Surface Mount Technology is cost effective, allowing the
manufacturer the opportunity to produce smaller units and
offer increased functions with the same size product.

Linear and Interface
Bipolar ...................................... 12-2
MOS Digital-Analog .................. . . . . . . . .. 12-6
Package Overview

12-8

Analog MPQ Table

12-9

Tape and Reel ................................. 12-10

..
I

Linear and Interface
Bipolar
All the major bipolar analog families are now represented in surface mount packaging. Standard SOIC and PLCC packages
are augmented by SOP-8 and DPAK for Linear regulators. In addition, tape and reel shipping to the updated EIA-481A is
now on line for the industry's largest array of operational amplifiers, regulators, interface, data conversion, consumer,
telecom and automotive Linear ICs.

·•.••••.•.·••.••·......· .•.. QI>"II;I>.·· . . ·· .•. '"

I>L< . . . · · . . . ••.••.••.. . . .•. . . ••.. . <..........

.-c.

-,«.··.·. ·. · · · .. >r . . . .···.·;

··.t.~·.···.···

.....;

".

CA3146D
DAC-08CD, ED
LF351 D
LF353D
LF411CD
LF412CD
LF441CD
LF442CD
LF444CD
LM201AD

Transistor Array
High-Speed 8-Bit Multiplying D-to-A Converter
Single JFET Operational Amplifier
Dual JFET Operational Amplifiers
Single/Dual JFET Operational Amplifier
Dual JFET Operational Amplifiers
Single JFET Low Power Operational Amplifier
Dual JFET Low Power Operational Amplifiers
Quad JFET Low Power Operational Amplifiers
General Purpose Adjustable Operational Amplifier

SO·14
SO-16
SO-8
SO-8
SO-8
SO-8
SO-8
SO-8
SO-14
SO-8

LM211D
LM224D
LM239D,AD
LM258D
LM285D-1.2
LM285D-2.5
LM293D
LM301AD

High Performance Voltage Comparator
Quad Low Power Operational Amplifiers
Quad Single Supply Comparators
Dual Low Power Operational Amplifiers
Micropower Voltage Reference Diode
Micropower Voltage Reference Diode
Dual Comparators
General Purpose Adjustable Operational Amplifier

SO-8
SO-14
SO-14
SO-8
SO-8
SO-8
SO-8
SO-8

LM311D
LM317LD
LM317MDT
LM324D,AD
LM339D,AD
LM348D
LM358D
LM385D-1.2
LM385D-2.5
LM393D

High Performance Voltage Comparator
Positive Adjustable 100 mA Voltage Regulator
Positive Adjustable 500 mA Voltage Regulator
Quad Low Power Operational Amplifiers
Quad Single Supply Comparators
Quad MC1741 Operational Amplifiers
Dual Low Power Operational Amplifiers
Micropower Voltage Reference Diode
Micropower Voltage Reference Diode
Dual Comparators

SO-8
SOP-8
DPAK
SO-14
SO-14
SO-14
SO-8
SO-8
SO-8
SO-8

LM833D
LM2901D
LM2902D
LM2903D
LM2904D
LM2931 AD-5.0,D-5.0
LM2931CD
LM3900D
MC1350D
MC1357D

Dual Audio Amplifiers
Quad Single Supply Comparators
Quad Low Power Operational Amplifiers
Dual Comparators
Dual Low Power Operational Amplifiers
Low Dropout Voltage Regulator
Adjustable Low Dropout Voltage Regulator
Quad Single Supply Operational Amplifiers
IF Amplifier
FM IC with Quadrature Detector

SO·8
SO-14
SO-14
SO-8
SO-8
SOP-8
SOP-8
SO-14
SO-8
SO-14

MC1377DW
MC1378FN
MC1382DW
MC1403D
MC1413D
MC1436D,CD
MC1455D
MC1458D,CD
MC14C88BD
MC1488D

Color Television RGB to PAUNTSC Encoder
Video Overlay Synchronizer
Multimode Monitor TTL To Analog Video
Precision Low Voltage Reference
Peripheral Driver Array
High Voltage Operational Amplifier
TIming Circuit
Dual Operational Amplifiers
Quad EIA-232-D/EIA-562 Drivers
Quad EIA-232-D Drivers

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

12-2

SO-20L
PLCC-44
SO-24L
SO-8
SO-16
SO-8
SO-8
SO-8
SO-14
SO-14

Bipolar (continued)
Device ....

......

.....

Function

Package
80-14
80-14
80-14
80-14
80-14
80-8
80-14
80-8
80-16
80-16
80-16
80-16
80-14

MC14C89ABD,BD
MC1489D
MC1495D
MC1496D
MC1723CD
MC1741CD
MC1747CD
MC1776CD
MC26L831D
MC26L832D
MC26810D
MC2831AD
MC3303D

Quad EIA-232-D/EIA-562 Receivers
Quad EIA-232-D Receivers
Four-Quadrant Multiplier
Balanced Modulator/Demodulator
Adjustable Positive or Negative Voltage Regulator
General Purpose Operational Amplifier
Dual MC1741 Operational Amplifiers
Programmable Operational Amplifier
Quad EIA-422/23 Drivers
Quad EIA-422 Receivers
Quad Bus Transceiver
FM Transmitter
Quad Differential-Input Operational Amplifier

MC3335DW
MC3346D
MC3356DW
MC3359DW
MC3361AD
MC3362DW
MC3363DW
MC3367DW
MC3371D
MC3372D
MC3391DW
MC3401D

Basic Dual Conversion Receiver
General Purpose Transistor Array
F8K Receiver
Low Power Narrowband FM IF Amplifier
Low Voltage Narrowband FM IF Amplifier
Dual Conversion Receivers
Dual Conversion Receivers
Low Voltage VHF Receiver
Low Voltage FM Receiver with R881, LC Quadrature Detector
Low Voltage FM Receiver with RS81, Ceramic Quadrature Detector
Low Side Protected Switch
Quad Operational Amplifiers

MC3403D
MC3418DW
MC3423D
MC3448AD
MC3450D
MC3452D
MC3456D
MC3458D
MC3486D
MC3487D
MC4558CD

Quad Differential-Input Operational Amplifier
CVSD
Overvoltage 8ensing Circuit
Quad GPIB Transceivers
Quad Line Receivers
Quad Line Receivers
Dual Timing Circuit
Dual Low Power Operational Amplifiers
Quad EIA-422/23 Receivers
Quad EIA-422 Drivers
Dual High Frequency Operational Amplifiers

80-14
80-16L
80-8
80-16
80-16
80-16
80-14
80-8
80-16
80-16
80-8

MC4741CD
MC78L05ACD
MC78L08ACD
MC78L12ACD
MC78L15ACD
MC78M05CDT
MC78M08CDT
MC78M12CDT
MC78M15CDT
MC79L05ACD

Quad MC1741 Operational Amplifiers
Positive Voltage Regulator, 5 V, 100 mA
Positive Voltage Regulator, 8 V, 100 mA
Positive Voltage Regulator, 12 V, 100 mA
Positive Voltage Regulator, 15 V, 100 mA
Positive Voltage Regulator, 5 V, 500 mA
Positive Voltage Regulator, 8 V, 500 mA
Positive Voltage Regulator, 12 V, 500 mA
Positive Voltage Regulator, 15 V, 500 mA
3-Terminal Negative Fixed Voltage Regulator, -5 V, 100 mA

80-14
80P-8
80P-8
80P-8
80P-8
DPAK
DPAK
DPAK
DPAK
80P-8

MC79L12ACD
MC79L15ACD
MC79M05CDT
MC79M12CDT
MC79M15CDT
MC10319DW
MC10321DW
MC13022DW(1 )

3-Terminal Negative Fixed Voltage Regulator, -12 V, 100 mA
3-Terminal Negative Fixed Voltage Regulator, -15 V, 100 mA
3-Terminal Negative Fixed Voltage Regulator, -5 V, 500 mA
3-Terminal Negative Fixed Voltage Regulator, -12 V, 500 mA
3-Terminal Negative Fixed Voltage Regulator, -15 V, 500 mA
8-Bit AID Flash Converter
7-Bit AID Flash Converter
Medium Voltage AM Stereo C-QUAM® Decoder

80P-8
80P-8
DPAK
DPAK
DPAK
80-24L
80-20L
80-28L

(1)To be Introduced.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
12-3

80-20L
80-14
80-20L
80-20L
80-16
80-28L
80-28L
80-28L
80-16
80-16
80P-8+8L
80-14

MC13024DW
MC13055D
MC13060D
MC33023DW,FN
MC33025DW,FN
MC33033DW
MC33035DW
MC33039D
MC33060AD
MC33064D-5
MC33065DW
MC33065DW-H
MC33065DW-L
MC33066DW
MC33067DW
MC33071 D,AD

Low Vol1age C-QUAM® Receiver
VHF LAN Receiver - FSK
1 Watt Audio Amplifier
High Speed (1.0 MHz) Single-Ended PWM Controller
High Speed (1.0 MHz) Double-Ended PWM Controller
Brushless DC Motor Controller
Brushless DC Motor Controller
Closed Loop Brushless Motor Adaptor (5 V ± 5% Supply)
Precision Switchmode Pulse Width Modulator
Undervoltage Sensing Circuit
Dual Current Mode PWM Controller
Dual Current Mode PWM Controller (Off-Line)
Dual Current Mode PWM Controller (DC-to-DC Converters)
Resonant Mode (ZCS) Controller
Resonant Mode (ZVS) Controller
Single, High Speed Single Supply Operational Amplifiers

MC33072D,AD
MC33074D,AD
MC33076D
MC33077D
MC33078D
MC33079D
MC33091D
MC33102D
MC33110D
MC33120FN
MC33121FN
MC33129D
MC33151D
MC33152D
MC33161D
MC33164D-3
MC33164D-5

Dual, High Speed Single Supply Operational Amplifiers
Quad, High Speed Single Supply Operational Amplifiers
Dual High Output Current Operational Amplifiers
Dual, Low Noise High Frequency Operational Amplifiers
Dual Audio, Low Noise Operational Amplifiers
Low Power, Single Supply Operational Amplifier
High Side TMOS Driver
Sleep-Mode™ 2-State, IlProcessor Operational Amplifier
Low Voltage Compander
SLiC II
Low Voltage Subscriber Loop Interface Circuit
High Performance Current Mode Controller
Dual Inverting MOSFET Drivers
Dual Noninverting MOSFET Drivers
Universal Voltage Monitor
Micropower Undervoltage Sensing Circuit (3 V ± 5% Supply)
Micropower Undervoltage Sensing Circuit (5 V ± 10% Supply)

MC33171D
MC33172D
MC33174D
MC33178D
MC33179D
MC33218DW
MC33261D
MC33272D
MC33274D
MC33282D
MC33284D

Single, Low Power, Single Supply Operational Amplifier
Dual, Low Power, Single Supply Operational Amplifiers
Quad, Low Power, Single Supply Operational Amplifiers
Dual Precision Operational Amplifiers
Quad Precision Operational Amplifiers
Voice-Switched Speakerphone with IlProcessor Interface
Power Factor Controller
Dual Precision Bipolar Operational Amplifiers
Quad Precision Bipolar Operational Amplifiers
Dual Precision Low Input JFET Operational Amplifiers (Trim-in-the-Package)
Quad Precision JFET Operational Amplifiers (Trim-in-the-Package)

MC34001D,BD
MC34002D,BD
MC34010FN
MC34012-1D
MC34012-2D
MC34012-3D
MC34014DW
MC34017-1 D
MC34017-2D
MC34017-3D
MC34018DW
MC34023DW,FN

Single JFET Input Operational Amplifier
Dual JFET Input Operational Amplifiers
Electronic Telephone Circuit
Telephone Tone Ringer
Telephone Tone Ringer
Telephone Tone Ringer
Telephone Speech Network with Dialer Interface
Telephone Tone Dialer
Telephone Tone Dialer
Telephone Tone Dialer
Voice Switched Speakerphone Circuit
High Speed (1.0 MHz) Single-Ended PWM Controller

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

12-4

SO-24L
SO-16
SOP-8
SO-16L, PLCC-20
SO-16L, PLCC-20
SO-20L
SO-24L
SO-8
SO-14
SO-8
SO-16L
SO-16L
SO-16L
SO-16L
SO-16L
SO-8
SO-8
SO-14
SO-8
SO-8
SO-8
SO-14
SO-8
SO-8
SO-14
PLCC-28
PLCC-28
SO-14
SO-8
SO-8
SO-8
SO-8
SO-8
SO-8
SO-8
SO-14
SO-8
SO-14
SO-24L
SO-8
SO-8
SO-14
SO-8
SO-14
SO-8
SO-8
PLCC-44
SO-8
SO-8
SO-8
SO-20L
SO-8
SO-8
SO-8
SO-28L
SO-16L, PLCC-20

Bipolar (continued)
Device

Function

Package

MC34025DW,FN
MC34050D
MC34051D
MC34060AD
MC34063AD
MC34064D-5
MC34065DW
MC34065DW-H
MC34065DW-L
MC34066DW
MC34067DW
MC34071 D,AD
MC34072D,AD
MC34074D,AD

High Speed (1.0 MHz) Double-Ended PWM Controller
EIA-422/23 Transceivers
EIA-422/23 Transceivers
Switchmode Pulse Width Modulation Control Circuit
Precision DC-to-DC Converter Control Circuit
UndervoJtage Sensing Circuit (5 V ± 5% Supply)
Dual Current Mode PWM Controller
Dual Current Mode PWM Controller (Off-Line)
Dual Current Mode PWM Controller (DC-to-DC Converter)
Resonant Mode (ZCS) Controller
Resonant Mode (ZVS) Controller
Single, High Speed, Single Supply Operational Amplifier
Dual, High Speed, Single Supply Operational Amplifiers
Quad, High Performance, Single Supply Operational Amplifiers

MC34080D
MC34081D
MC34084DW,ADW
MC34085DW,ADW
MC34114DW
MC34115DW
MC34118DW
MC34119D
MC34129D
MC34151D
MC34152D
MC34161D
MC34164D-3
MC34164D-5
MC34181D
MC34182D
MC34184D
MC34217D
MC34261D

High Speed Decompensated (AVCL ~ 2) JFET Input Operational Amplifier
High Speed JFET Input Operational Amplifier
Quad High Speed, JFET Operational Amplifier
Quad High Speed, JFET Operational Amplifier
Speech Network II
CVSD
Speakerphone II
Telephone Speaker Amplifier
Power Supply Controller
Dual Inverting MOSFET Drivers
Dual Noninverting MOSFET Drivers
Universal Voltage Monitor
Micropower Undervoltage Sensing Circuit (3 V ± 5% Supply)
Micropower UndervoJtage Sensing Circuit (5 V ± 10% Supply)
Single, Low Power, High Speed JFET Operational Amplifier
Dual, Low Power, High Speed JFET Operational Amplifiers
Quad, Low Power, High Speed JFET Operational Amplifiers
Adjustable Toner Ringer
Power Factor Controller

SO-8
SO-8
SO-16L
SO-16L
SO-18L
SO-16L
SO-28L
SO-8
SO-14
SO-8
SO-8
SO-8
SO-8
SO-8
SO-8
SO-8
SO-14
SO-8
SO-8

MC44301DW
MC75172BDW
MC75174BDW
NE556D
TL064CD
TL071CD,ACD
TL072CD,ACD
TL081 CD,ACD
TL082CD,ACD

High Performance Video IF
Quad EIA-485 Line Drivers w/3-State Outputs
Quad EIA-485 Line Drivers w/3-State Outputs
Dual Timing Circuit
Quad JFET Low Power Operational Amplifiers
Single, Low Noise JFET Input Operational Amplifier
Dual, Low Noise JFET Input Operational Amplifiers
Single, JFET Input Operational Amplifier
Dual, JFET Input Operational Amplifiers

SO-28L
SO-20L
SO-20L
SO-14
SO-14
SO-8
SO-8
SO-8
SO-8

TL431 ACD,AID,CD,ID
UAA1041BD
UC2842AD, BD, BDl
UC2843AD, BD, BDl
UC2844D, BD, BDl
UC2845D, BD, BDl
UC3842AD, BD, BDl
UC3843AD, BD, BDl
UC3844D, BD, BDl
UC3845D, BD, BDl

Programmable Precision Reference
Automotive Direction Indicator
Off-Line Current Mode PWM Controller
Current Mode PWM Controller
Off-Line Current Mode PWM Controller (DC'; 50%)
Current Mode PWM Controller (DC'; 50%)
Off-Line Current Mode PWM Controller
Current Mode PWM Controller
Off-Line Current Mode PWM Controller (DC'; 50%)
Current Mode PWM Controller (DC'; 50%)

SOP-8
SO-8
SO-14, SO-8
SO-14, SO-8
SO-14, SO-8
SO-14,SO-8
SO-14, SO-8
SO-14, SO-8
SO-14,SO-8
SO-14, SO-8

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
12-5

SO-16L, PLCC-20
SO-16
SO-16
SO-14
SO-8
SO-8
SO-16L
SO-16L
SO-16L
SO-16L
SO-16L
SO-8
SO-8
SO-14

IBI

I
I

MOS Digital-Analog

I

Device

I

Function

I .

Package

AID and DIA Converters
MC14433DW
MC14442FN
MC14443DW
MC14447DW
MC44250FN
MC144110DW
MC144111DW

3-1/2 Digit AID Converter
11-Channel 8-Bit AID Converter with Parallel Interface
6-Channel AID Converter Subsystem
6-Channel AID Converter Subsystem
Triple 8-Bit Video A/D Converter
Hex D/A Converter with Serial Interface
Quad D/A Converter with Serial Interface

SO-24L
PLCC-28
SO-16L
SO-16L
PLCC-44
SO-20L
SO-16L

MC 145040FN 1(2)
MC145040FN2(2)
MC145041FN1(2)
MC145041 FN2(2)
MC145050DW
MC145051DW
MC145053D

11-Channel,
11-Channel,
11-Channel,
11-Channel,
11-Channel,
11-Channel,
11-Channel,

PLCC-20
PLCC-20
PLCC-20
PLCC-20
SO-20L
SO-20L
SO-14

8-Bit AID Converter with Serial Interface
8-Bit AID Converter with Serial Interface
8-Bit AID Converter with Serial Interface
8-Bit AID Converter with Serial Interface
1O-Bit AID Converter with Serial Interface
1O-Bit AID Converter with Serial Interface
1O-Bit AID Converter with Serial Interface

Display Drivers
MC14489DW
MC14495DW1 (2)
MC14499DW
MC145000FN
MC145001FN
MC145453FN

Multi-Character LED Display/Lamp Driver
Hex-to-7 Segment Latch/Decoder ROM/Driver
7-Segment LED Display Decoder/Driver with Serial Interface
48-Segment Multiplexed LCD Driver (Master)
44-Segment Multiplexed LCD Driver (Slave)
33-Segment LCD Driver with Serial Interface

SO-20L
SO-16L
SO-20L
PLCC-28
PLCC-28
PLCC-44

Operational AmplifierslComparators
MC14573D
MC14574D
MC14575D
MC14576BF
IvlC14577BF
MC14578D

Quad Programmable Operational Amplifier
Quad Programmable Comparator
Dual Programmable Operational Amplifier and Dual Comparator
Dual Video Amplifier
Dual Video Amplifier
Micro-Power Comparator Plus Voltage Follower

SO-16
SO-16
SO-16
SO-8 (EIAJ)
SO-8(EIAJ)
SO-16

Phase-Locked Loop Frequency Synthesizers
MC145106FN
MC145145DW1
MC145146DW1
MC145149DW
MC145151DW2
MC145151FN2
MC145152DW2
MC145152FN2

PLL Frequency Synthesizer
4-Bit Data Bus Input PLL Frequency Synthesizer
4-Bit Data Bus Input PLL Frequency Synthesizer
Serial Input Dual PLL Frequency Synthesizer
Parallel Input PLL Frequency Synthesizer
Parallel Input PLL Frequency Synthesizer
Parallel Input PLL Frequency Synthesizer
Parallel Input PLL Frequency Synthesizer

PLCC-20
SO-20L
SO-20L
SO-20L
SO-28L
PLCC-28
SO-28L
PLCC-28

MC145155FN2
MC145155DW2
MC145156FN2
MC145156DW2
MC145157FN2
MC145157DW2

Serial
Serial
Serial
Serial
Serial
Serial

Synthesizer
Synthesizer
Synthesizer
Synthesizer
Synthesizer
Synthesizer

PLCC-20
SO-20L
PLCC-20
SO-20L
PLCC-20
SO-16L

MC145158FN2
MC145158DW2
MC145159DW1
MC145159FN(3)
MC145160DW
MC145161DW
MC145166DW
MC145167DW
MC145168DW
MC145170D

Serial Input PLL Frequency Synthesizer
Serial Input PLL Frequency Synthesizer
Serial Input PLL Frequency Synthesizer with Analog Phase Detector
Serial Input PLL Frequency Synthesizer with Analog Phase Detector
Dual PLL for Cordless Telephones
Dual PLL for Cordless Telephones
Dual PLL for Cordless Telephones
Dual PLL ior Cordless Telephones
Dual PLL ior Cordless Telephones
Serial Interface PLL Frequency Synthesizer

PLCC-20
SO-16L
SO-20L
PLCC-20
SO-20L
SO-16L
SO-16L
SO-16L
SO-16L
SO-16

Input PLL
Input PLL
Input PLL
Input PLL
Input PLL
Input PLL

Frequency
Frequency
Frequency
Frequency
Frequency
Frequency

(2)The digit 1 or 2 after the package designator is not a pari of the package definition, but describes the electrical capability of the device.
(3)Electrical variations may require a numerical suffix after the package suffix. Contact your Motorola representative for details.
(4)lntroduction of this device in surface mount packages is dependent on market demand.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

12-6

Remote Control Functions
MC14469FN
MC14497
MC145026D
MC145027DW
MC145028DW
MC145030DW
MC145033DW
MC145034DW
MC145035DW

Addressable Asynchronous ReceiverfTransmitter
PCM Remote Control Transmitter
Remote Control Encoder
Remote Control Decoder
Remote Control Decoder
Remote Control Encoder/Decoder
Remote Control Encoder/Decoder
Remote Control Encoder
Remote Control Decoder

PLCC-44
(3)
SO-16
SO-16L
SO-16L
SO-20
SO-28L
SO-28L
SO-28L

Smoke Detectors
MC14467
MC14468
MC145010DW
MC145011DW

Low-Cost Smoke Detector
Interconnectable Smoke Detector
Photoelectric Smoke Detector with I/O
Photoelectric Smoke Detector with I/O

(3)
(3)
SO-16L
SO-16L

Telecommunications Devices
MC14410DW
MC14411DW
MC142100DW
MC142103
MC143403D
MC145403DW
MC145404DW
MC145405DW
MC145406DW
MC145407DW

2-01-8 Tone Encoder
Bit Rate Generator
Crosspoint Switch with Control Memory (4 x 4 x 1)
Transcoder HDB31 AMI to NRZ
Quad Line Driver (Op Amp)
EIA-2321V.28 CMOS Driver/Receiver
EIA-2321V.28 CMOS Driver/Receiver
EIA-2321V.28 CMOS Driver/Receiver
EIA-232IV.28 CMOS Driver/Receiver
EIA-2321V.28 CMOS Driver/Receiver, 5.0 V Only

SO-16L
SO-24L
S0-16L
(3)
SO-14
SO-20L
SO-20L
SO-20L
SO-16L
S0-20L

MC145408DW
MC145412
MC145416DW
MC145421DW
MC145422DW
MC145425DW
MC145426DW
MC145428DW
MC145436DW
MC145439

EIA-2321V.28 CMOS Driver/Receiver
PulsefTone Repertory Dialer (Nine 18-Digit Memory)
PulsefTone Repertory Dialer (13 18-Digit Memory)
UDLT II Master
UDLTMaster
UDLT II Slave
UDLT Slave
Data Set Interface Circuit
DTMF Decoder
Transcoder B8ZS, B6ZS, HDB3 to NRZ

S0-20L
(3)
SO-20L
SO-24L
SO-24L
SO-24L
SO-24L
SO-20L
SO-16L
(3)

MC145442DW
MC145443DW
MC145447DW
MC145472FE
MC145472FU
MC145475DW
MC145480DW
MC145488
MC145502
MC145503DW
MC145505DW
MC145532DW

300-Baud CCITT V.21 Single-Chip Modem
300-Baud Bell 103 Single-Chip Modem
Calling Line 1.0. Receiver with Ring Detector
ISDN U-Interface Transceiver
ISDN U-Interface Transceiver
ISDN SfT Transceiver
+5.0 V PCM Codee/Filter
Dual Data Link Controller
PCM Codee/Filter
PCM Codee/Filter
PCM Codee/Filter
ADPCM Transcoder

MC145540DW
MC145554DW
MC145557DW
MC145564DW
MC145567DW
MC145705DW
MC145706DW
MC145707DW

ADPCM Codee
PCM Codee/Filter (TP3054 Compatible)
PCM Codee/Filter (TP3057 Compatible)
PCM Codee/Filter (TP3064 Compatible)
PCM Codee/Filter (TP3067 Compatible)
EIA-2321V.28 CMOS Driver/Receiver, 5.0 V Only
EIA-2321V.28 CMOS Driver/Receiver, 5.0 V Only
EIA-2321V.28 CMOS Driver/Receiver, 5.0 V Only

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

12-7

SO-20L
SO-20L
SO-16L
CQFP-68L
PQFP-68L
SO-28L
SO-20L
(3)
(3)
SO-16L
S0-16L
S0-16L
SO-28L
SO-16L
SO-16L
SO-20L
SO-20L
SO-20L
SO-20L
SO-20L

..

I

Surface Mount Technology Package Overview

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

12-8

Analog MPQ Table
Tape/Reel and Ammo Pack

I

Package Code

MPQ

0802
0804
0801
0805
0803
0806

1000/reel
500/reel
500/reel
450/reel
250/reel
250/reel

Case 751
Case 751A
Case 7518
Case 751G
Case 751C
Case 751D
Case 751E
Case 751F

0095
0096
0097
2003
2004
2005
2008
2009

2500/reel
2500/reel
2500/reel
1000/reel
1000/reel
1000/reel
1000/reel
1000/reel

Case 29
Case 29

0031
0031

2000/reel
2000/Ammo Pack

Package Type

PLCC
Case
Case
Case
Case
Case
Case

775
776
777
778
779
780

SOIC

TO-92

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

12-9

Tape and Reel
Logic and Analog Technologies,
and MOS Integrated Circuits
Motorola has now added the convenience of Tape and Reel
packaging for our growing family of standard Integrated Circuit
products. Three reel sizes are available, for all but the largest
types, to support the requirements of both first and second

generation pick-and-place equipment. The packaging fully
conforms to the latest EIA-481A specification. The antistatic
embossed tape provides a secure cavity, sealed with a
peel-back cover tape.

Mechanical Polarization
SOIC DEVICES

PLCC DEVICES
Typical

User Direction of Feed
User Direction of Feed

DPAK DEVICES
Typical

User Direction of Feed

so-s, sop-s
SO-14
SO-16

12
16
16

2,500
2,500
2,500

13
13
13

R2
R2
R2

SO-16L, SO-8+8L WIDE
SO-20LWIDE
SO-24LWIDE
SO-2SLWIDE
SO-28LWIDE

16
24
24
24
32

1,000
1,000
1,000
1,000
1,000

13
13
13
13
13

R2
R2
R2
R2
R3

PLCC-20
PLCC-28
PLCC-44

16
24
32

1,000
500
500

13
13
13

R2
R2
R2

PLCC-52
PLCC-68
PLCC-84

32
44
44

500
250
250

13
13
13

R2
R2
R2

TO-226AA (TO-92)(2)

18

2,000

13

RA, RB, RE, RM, or RP
(Ammo Pack) only

{I )Minimum order quantity is I reel. DistributOrs/OEM customers may break lots or reels at their option, however broken reels may not be returned.
(2)lntegrated circuits in TO-226AA packages are available in Styes A, Band E only, with optional '"Ammo Pack" (Suffix RM or RP).
For ordering information please contact your local Motorola Semiconductor Sales Office.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

12-10

Tape and Reel

(continued)

TO-92 Reel Styles
STYLE A

STYLE B

Carrier Strip

Feed

Adhesive Tape on Reverse Side

j

~-:7':"-----------'

Feed

Flat Side
Carrier Strip

~_-::>""";o~_o__o__o___

....J

Rounded Side of Transistor and Adhesive Tape Visible.

Flat Side of Transistor and Carrier Strip Visible
(Adhesive Tape on Reverse Side).
STYLE E

Flat Side

~ed~__~,,-______________-....J

Flat Side of Transistor and Adhesive Tape Visible.

TO-92 Ammo Pack Styles
STYLE M

STYLE P

Adhesive Tape on
Top Side

Adhesive Tape on
Top Side

Flat Side

Rounded Side

Carrier
Strip

Carrier
Strip

IEII
I

Label

Flat Side of Transistor and
Adhesive Tape Visible.

Label

Style M Ammo Pack Is Equivalent to Style E of Reel
Pack Dependent on Feed Orientation From Box.

Rounded Side of Transistor
and Adhesive Tape Visible.

Style P Ammo Pack Is Equivalent to Styles A and B of Reel Pack
Dependent on Feed Orientation From Box.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

12-11

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

12-12

Packaging Information

In Brief ...
The packaging availability for each device type is indicated
on the individual data sheets and the Selector Guide. All of the
outline dimensions for the packages are given in this section.
The maximum power consumption an integrated circuit
can tolerate at a given operating ambient temperature can be
found from the equation:

TJ(max)-TA
PD(TA) = -'------'--R9JA(Typ)

where:
PD(TA) = Power Dissipation allowable at a given

operating ambient temperature. This must
be greater than the sum of the products of
the supply voltages and supply currents at
the worst case operating condition.
TJ(max) = Maximum operating Junction Temperature
as listed in the Maximum Ratings Section.
See individual data sheets for TJ(max)
information.
TA = Maximum desired operating Ambient
Temperature
R9JA(Typ) = Typical Thermal Resistance Junction-toAmbient

Case Outline Dimensions

LP, P, Z SUFFIX
CASE 29-04

NOTES:
1. DIMENSIONING AND TOLEAANCING PER ANSI
YI4.5M,1982.
2. CONTROLLiNG DIMENSION: INCH.
3. CONTOUR OF PACKAGE BEYOND DIM R IS
UNCONTROLLED.
4. DIM F APPLiES BETWEEN P AND L DIM 0 AND
J APPLiES BETWEEN LAND K MINIMUM. LEAD
DIM IS UNCONTROLLED IN P AND BEYOND DIM
KMINIMUM.
5. 029-01 AND -02 OBSOLETE, NEW STANDARD
029-04.

Plastic Package
RaJA = 200°CIW
(TO-226AAlTO-92)

,/

DIM
A
B
C
0
F
G
H
J

3

K

SECTION

L
N
P
R

x-x

V

MILLIMETERS
MIN
MAX
4.45
5.20
4.32
5.33
3.18
4.19
0.41
0.55
0.41
0.48
1.15
1.39
2.42
2.66
0.39
0.50
12.70
6.35
2.04
2.66

2.54
2.93
3.43

-

INCHES
MIN
MAX
0.175 0.205
0.170 0.210
0.125 0.165
0.022
0.016 0.019
0.045 0.055
0.095 0.105
0.015 0.020
0.500
0.250
0.080 0.105
0.100
0.115
0.135

KC, TSUFFIX
CASE 221A-06

Plastic Package
RaJA = 65°C/W (Typ)
(TO-220AB)

~
T-

F

--C

T-rl

SEATING
PLANE

NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI YI4.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIM Z DEFINES AZONE WHERE ALL BODY
AND LEAD IRREGULARITIES ARE ALLOWED.

S

~

±R

vG-

---

-->oN

~I--

DIM

A

Q

MILLIMETERS
MIN
MAX

14.48

15.75

9.66
4.07
0.64
3.61
2.42
2.80
0.48
12.70
1.15

10.28
4.82
0.88
3.73
2.66
3.93
0.64

4.83
2.54

5.33

2.04
1.15
5.97
0.00

0.142

0.147

0.095

0.105

0.110
0.018

0.155
0.025

0.500
0.045
0.190

0.562
0.060
0.210

2.79

0.100
0.080

0.120
0.110

1.39

0.045

0.055

6.47

0.235

0.255

1.27

0.000
0.045
-

0.050

14.27
1.52
3.04

1.15

D

2.04

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

13-2

INCHES
MIN
MAX
0.570 0.620
0.380 0.405
0.160 0.190
0.025 0.035

0.080

NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI YI4.5M. 1982.
2. CONTROWNG DIMENSION: INCH.
3. DIMENSION D DDES NOT INCLUDE
INTERCONECT BAR (DAM BAR) PROTRUSION.
DIMENSION D INCLUDING PROTRUSION SHALL
NOT EXCEED 0.043 (1.092) MAXIMUM.
4. 314B·Ol. 314B·02AND 314B·03 OBSOlETE.
NEW STANDARD 314B·04.
5. STYLE lTHRU 4: OBSOlETE.

T, TV SUFFIX

CASE 3148-04
Plastic Package

1~
5

GATE
MIRROR
DRAIN
KELVIN
SOURCE

H i-G
05PL-!--

DIM
A
B
C
D
E
F
G
H
J
K
L
N

a

S
U
V
W

1+lc.lo(0.254)@ITI P@ I

MILLIMETERS
MIN
MAX
14.529 15.570
9.906 10.541
4.318 4.572

0.635 0.965
1.219 1.397
21.590 23.749
1.702BSC
4.216BSC
0.381
0.635
22.860 27.940
8.128 9.271
8.128BSC
3.556 3.886
15.748
11.888 12.627
18.669
2.286 2.794

INCHES
MAX

MIN
0.572
0.390
0.170
0.025
0.048

0.613
0,415

O.IBO
0.038
0.055
0.850 0.935
0.067BSC
0.166 BSC
0.015 0.025
0.900 1.100
0.320 0.365
0.320BSC
0.140 0.153
0.620
0.468 0.505
0.735
0.090 0.110

T, T1 SUFFIX

CASE 3140-03
Plastic Package
ReJA = 65"C/W (Typ)
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI YI4.5M, 1982.
2. CONTROWNG DIMENSION: INCH.

DIM
A
B
C
D
E

G
H
J
K
L

a
U
S

G

MILUMETERS
MIN
MAX
14.529 15.570
9.906 10.541
4.318
4.572
0.635
0.965
1.219
1.397
1.7Q2BSC
2.210
2.845
0.381
0.635
25.908 27.051
8.128
9.271
3.556
3.886
2.667
2.972
13.792 14.783

INCHES
MIN
MAX
0.572 0.613
0.390 0.415
0.170 0.180
0.025 0.038
0.048 0.055
0.067 BSC
0.087 0.112
0.015 0.025
1.020 1.065
0.320 0.365
0.140 0.153
0.105 0.117
0.543 0.582

H

05~

1+10.356 (0.014)@ I TI Q@ I

OT-1 SUFFIX

CASE 369-06
Plastic Package
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI YI4.5M, 1982.
2. CONTRDLUNG DIMENSION: INCH.
3. 369·01 THRU -05 OBSOLETE, NEW STANDARD
369-06.

DIM
A
B
C
D
E
F

"2 3

G

F

o 3PL
1+10.13(0.005) ® ITI

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

13-3

H
J
K
R
S
V

MILUMETERS
MIN
MAX
5.97
6.22
6.35
6.73
2.19
2.38
0.69
0.88
1.01
0.84
0.94
1.19
2.29 BSC
0.87
1.01
0.46
0.58
8.89
9.65
4.45
5.46
1.27
2.28
0.77
1.27

INCHES
MIN
MAX
0.235 0.245
0.250 0.265
0.086 0.094
0.027 0.035
0.033 0.040
0.037 0.047
0.090BSC
0.034 0.040
0.018 0.023
0.350 0.380
0.175 0.215
0.050 0.090
0.030 0.050

DTSUFFIX
CASE 369A-10
Plastic Package
DPAK

NOTES:
1. DIMENSIONING AND TOLERANCING
PERANSIYI4.5M, 198~
~ CONTROWNG DIMENSION: INCH.
3. 36QA.01 TIlRU.os OBSOLETE.
4. 369A.Q4 TIlRU.(19 OBSOLETE, NEW
STANDARD 369A·l0.

"i~~'W~M~IR~Stt~~~
~D:' ~~~ ~
~
B
C
D

3

E
F

G

H
J
K
L

J

R
S
U
Y
Z

D, J, L, N SUFFIX
CASE 620-10
Ceramic Package
RaJA = 1eeoc/W (Typ)

~~

~

2.19

U6

~

0.69

6~

0.68

~

0.84
1.01
~
0.94
1.19 ~0.047
4.58 BSC
BSC
0.87
1.01
0.040
0.48
0.58 0.016 0.023
2.60
~69
0.102 0.114
2.29 B~

4,45
0.51
0.51
0.77
3.51

5.48
1.27
127

0.090~C

0.175
0.020
0.020
0.030
0.136

0215
0.050
0.050

NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI YI4.5M, 1962.
2. CONTROWNG DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAO WHEN
FORMED PARALLEL
4. DIM F MAY NARROW TO 0.76 (0.0301 WHERE
TIlE LEAD ENTERS TIlE CERAMIC BODY.

,'11'---'111

II

II
u

jLh~
It I 0.25(0.010) @ITIB®I

DIM
A
B
C
D
E
F
G
J
K
L

M
N

MIWIIETERS
MIN --'lAX
19.05 19.93
6.10 7.49
5.08
0.39 0.50
I.27BSC
1.40 1.65
~54BSC

0.21
0.36
3.18 4.31
7.62BSC
D°
15"
0.51
1.01

INCHES
MIN
MAX
0.750 0.765
0.240 0.295
0.200
0.015 0.020
O.05OBSC
0.055 0.065
O.IDDBSC
0.008 0.015
0.125 0.170
O.3DDBSC
II"
15"
0.020 0.040

It I 0.25(0.010) @ITIA®I

LSUFFIX
CASE 623-G5
Ceramic Package
RaJA = 53°C/W (Typ)
13

1

~rT"TT'TTTT"TI"'TT'T'IrTT"T'I'TI'2
J
I..
.1
A

~~
NJJr.-L~\-

-JGk- -Jk-D

MOTOROLA L1NEARIINTERFACE ICs DEVICE DATA
13-4

NOTES:
1. DlM'~ TO CENTER OF LEADS WHEN
FORMED PARALLEL
2. LEADSWITHINO.13mm (0,0D5) RADIUS
OF TRUE POSITION /(f SEI!T1NG PLANE
/(f MAXIMUM Ml!TERIAL CONDmON.
(WHEN FORMED PARALLEL).

DIM
A
B
C
D
F
G
J
K
L

II

MIWIIETERS
MIN
MAX
31.24 3~77
12.70 1~49
4.06
5.59
0.41
0.51
1.27
1.52
~54BSC

0.20
3.16

0.30
4.06

I~BSC

II"

0.51

15°
1.27

INCHES
IIIN
MAX
1.230 1.290
0.500 0.610
0.160 0.220
0.016 0.020
0.050· 0.06D
O.IDDBSC
0.006 0.012
0.125 0.160
O.6DDBSC
II"
15°
0.020 0.050

DP1, N, P, P1 SUFFIX
CASE 626-05
Plaslic Package
RaJA ~ 1aaoclW (Typ)

.~

NOTES:
1. LEAD POSITIONAL TOLERANCE:

1"'I~o.13(0.005) @ITIA@IB @I
2. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL
3. PACKAGE CONTOUR OPTIONAL (ROUND
OR SQUARE CORNERS).
4. DIMENSIONS A ANO B ARE DATUMS.
5. DIMENSIONING AND TOLERANCING PER
ANSI YI4.5M, 1982.

DIM
A
B
C
D
F
G
H
J
K
L
M
N

NOTE.

1

(TO-116)

"I

f::::::: I~
14

m

DIM
A
B
C
D
F

C

II
.
14

1

G
J

4

s~~
F:Jt G
PLANE

INCHES
MIN
MAX
0.370 0.400
0.240 0.260
0.155 0.175
0.015
0.020
0.040 0.060
O.IOOBSC
0.030 0.050
0.008 0.012
0.115 0.135
0.300 BSC
1QO

0.030

0.040

NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI YI4.5M, 1982.
2. CONTROWNG DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL
4. DIM F MAY NARROW TO 0.76(0.030) WHERE
THE LEAD ENTERS THE CERAMIC BODY
5. 632.01 THRU ·07 OBSOLETE, NEW STANDARD
632·08.

J, F, L SUFFIX
CASE 632-08
Ceramic Package
RaJA ~ laaoclW (Typ)

MIWMETERS
MIN
MAX
9.40 10.16
6.10
6.60
3.94
4.45
0.51
0.38
1.02
1.52
2.54 BSC
0.76
1.27
0.20
0.30
2.92
3.43
7.62 BSC
100
0.76
1.01

II

K
L
M
N

D14PL

MIWMETERS
MIN
MAX
19.05 19.94
6.23
7.11
3.94
5.08
0.39
0.50
1.40
1.65
2.54 BSC
0.21
0.38
4.31
3.IB
7.62BSC
150
00
0.51
1.01

INCHES
MIN
MAX
0.750 0.785
0.245 0.2BO
0.155 0.200
0.015 0.020
0.055 0.065
0.100BSC
O.OOB 0.015
0.125 0.170
0.300 BSC
150
00
0.020 0.040

JLJ14PL

r.1tTl"'"'0.2'-5-(0,-01-'-0)-::::®"I::TTI-'A---;®:::-11

1,.:",'10-.2-5('--0.0-10-:-)®:=: M"TIT::TI--=B--::®"'I

N, P, N-14, P2 SUFFIX
CASE 646-06
Plaslic Package
RaJA ~ 1aaoclW (Typ)

NOTES:
1. LEADS WITHIN 0.13 mm (0.005) RADIUS
OF TRUE POSITION AT SEATING PLANE
AT MAXIMUM MATERIAL CONDITION.
2. DIMENSION"r TO CENTER OF LEADS
WHEN FORMED PARALLEL
3. DIMENSION "8" DOES NOT INCLUDE
MOLD FLASH.
4. ROUNDED CORNERS OPTIONAL

".

DIM
A
B
C
D
F
G
H

1

J

K

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
13-5

K
L
M
N

MILUMETERS
MAX
MIN
lB.16 19.56
6.10
6.60
4.69
3.89
0.53
0.38
1.02
1.7B
2.54BSC
1.32
2.41
0.20
0.3B
3.43
2.92
7.62 BSC
1QO
00
0.39
1.01

INCHES
MIN
MAX
0.715 o.no
0.240 0.260
0.145 0.165
0.015 0.021
0.040 0.070
0.100BSC
0.052 0.095
O.ooB 0.015
0.115 0.135
0.300BSC
1QO
00
0.015 0.039

DP2, N, P, PC SUFFIX
CASE 648-08
Plastic Package
RSJA = 67'C/W (Typ)

NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI YI4.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION"~ TO CENTER OF LEADS WHEN
FORMED PARALLEL
4. DIMENSION "B" DOES NOT INCLUDE MOLD
FLASH.
5. ROUNDED CORNERS OPTIONAL

DIM

A
B
C
D
F

G

1+10.25 (0.010)

H
J
K
L
M
S

® IT IA ® I

M1WMETERS
MIN
MAX
18.80 19.55
6.35
6.85
3.69
4.44
0.39
0.53
1.77
1.0'
2.54BSC
1.'7 BSC
0.21
0.38
2.80
3.30
7.50
7.74
0'
10'
0.51
1.01

INCHES
MIN
MAX
0.740 0.770
0.'50 0.270
0.145 0.175
0.015 0.021
0.040 0.070
0.100BSC
0.050BSC
0.008 0.015
0.110 0.130
0.295 0.305
0'
10
0.0'0 0.040

NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 198'.
,. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL
4. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
5. INTERNAL LEAD CONNECTION, BETWEEN
4 AND 5, 12 AND 13.

P, V SUFFIX
CASE 648C-03
Plastic Package
RSJA = 52'C/W

DIM

A
B
C
D
E
F

G

J
K
L
M
N

PSUFFIX
CASE 649-03
Plastic Package
RSJA = 90'C/W (Typ)

MILLIMETERS
MIN
MAX
18.80 21.34
6.10
6.60
3.69
4.69
0.38
0.53
l.'7BSC
1.78
1.0'
'.54 BSC
0.20
0.38
3.43
2.9'
7.62BSC
0'
10'
0.39
1.01

INCHES
MIN
MAX
0.740 0.840
0.240 0.'60
0.145 0.185
0.015 0.021
0.050BSC
0.040 0.070
0.100 BSC
0.008 0.015
0.115 0.135
0.300 BSC
10'
0'
0.015 0.040

NOTES:
1. LEADS WITHIN 0.13 mm (0.005) RADIUS OF
TRUE POSITION AT SEATING PLANE AT
MAXIMUM MATERIAL CONDITION.
2. DlMENSION"r TO CENTER OF LEADS WHEN
FORMED PARALLEL
3. 649-02 OBSOLETE, NEW STD 649-03 SEE
ISSUE 'C" FOR REFERENCE.

P

Q
DIM
A

B
C
D
F
G
H
J

24

K
L
M
N

P
Q

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

13-6

MILLIMETERS
MAX
MIN
31.50 32.13
13.21
13.72
5.21
4.70
0.38
0.51
1.02
1.5'
'.54BSC
2.16
1.85
0.20
0.30
2.92
3.43
14.99 15.49
10'
0.51
1.02
0.13
0.38
0.51
0.76

INCHES
MAX
MIN
1.'40 1.'85
0.520 0.540
0.185 O.,OS
0.015 0.020
0.040 0.060
0.100 BSC
0.065 0.085
0.008 0.012
0.115 0.135
0.590 0.610
10'
0.020 0.040
0.005 0.015
0.020 0.030

LSUFFIX

~:~"~=~~I

'9

E[__

__l ] ]

de Fl'

~ 1·F~ A
tLj
,,~... I H}U1)1HBM!~
JH~ JL.:: ~ i ~~J ~:I-

NOTES:
1. ·A· AND ·B· ARE DATUMS.
2. ·T-IS SEATING PLANE.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL
4. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5.1973.
5. 690-11 AND 690·12 OBSOLETE. NEW STANOARO
690-13.

DIM
A
B
C
D
F
G

H
J
K
L
M
N

MILUMETERS
MIN
MAX
2M7 20.57
7.11
7.74
2.67
4.19
0.38
0.53
0.76
1.52
2.54BSC
0.76
1.78
0.20
0.30
3.18
5.08
7.62BSC
10"
0.38
1.52

INCHES
MIN
MAX
0.790 0.810
0.280 0.305
0.105 0.165
0.015 0.021
0.030 0.060
0.100BSC
O.OSO 0.070
0.008 0.012
0.125 0.200
0.300BSC
10°
0.D15 0.060

I·Hpo.25(O.OI0)@ITI A@I B@I

J-B, J, JG, U, Z SUFFIX
CASE 693-03
Ceramic Package
RaJA = 100'CIW (Typ)

.~
1

03

IIlll1 ~=:fT
c

r;--r--QIJ1,

s~

PLANE

ffl1

~

IIU
E

,~

'I!I

f-

I--

G I---

f

OPTIONAL LEAD
CONFIGURATION

~

NOTES:
1. OIMENSIONING ANO TOLERANCING PER
ANSI Y14.5M. 1982.
2. CONTROLUNG DIMENSION: INCH.
3. OIMENSION L TO CENTER OF LEAD WHEN
FORMEO PARALLEL
4. OIMENSION F FOR FULL LEAOS. HALF LEADS
AT LEAD POSITIONS 1. 4. 5. ANO 8.
5. OIM F MAY NARROW TO 0.76 (0.030) WHERE
THE LEAD ENTERS THE CERAMIC BODY.
6. 693-01 AND.{)2 OBSOLETE. NEW STANDARD
693-OS.

I

i"
till'll
'~

JL -.
J

DIM
A
B

r\

C

o
E
F

M

BPL

G

I--~lt~I':"o.2-5"-(0.-01""-0)";::®:TI::1TI--::B:-;®~I
_ I--- 0 BPL
n
t l"'0.=25-=(0"'.01:'::0):-;®;:-r:1T:rl"'A'-'®"I

F-

L
M

"=:1

A, 8, N, P SUFFIX
CASE 707-02
Plastic Package
RaJA = 1oO'CIW (Typ)

MILUIiETERS
MIN
MAX
9.91
10.92
6.22
6.98
4~2
5.08
0.41
0.51
1.27BSC
1.27
1.65
2.54BSC
0.20
0.38
3.18
4.06
7.62BSC
00

150

0.51

1.02

INCHES
MIN
MAX
0.390 0.430
0.245 0.275
0.170 0.200
0.016 0.020
0.050BSC
0.050 0.065
0.100BSC
0.008 0.D15
0.125 0.160
0.300 BSC
0°
15°
0.020 0.040

NOTES:
1. POSITIONAL TOLERANCE OF LEADS (0).
SHALL BE WITHIN 0.25 mm (0.010) AT
MAXIMUM MATERIAL CONDITION. IN
RELATION TO SEATING PLANE AND EACH
OTHER.
2. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL
3. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.

DIM
A
D
F
G

H
J
K
L
M

N

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
13-7

IlILUIiETERS
MIN
MAX
22.22 23.24
6.10
6.60
3.56
4.57
0.36
0.56
1.27
1.78
2.54BSC
1.02
1.52
0.20
0.30
2.92
3.43
7.62BSC
0"
15°
051
1.02

INCHES
MIN
MAX
0.675 0.915
0.240 0.260
0.140 0.180
0.014 0.022
0.050 0.070
0.100 BSC
0.040 0.080
0.008 0.012
0.115 0.135
0.300BSC
0°
15'
0.020 0.040

I

--

PSUFFIX
CASE 71D-02
Plastic Package

J.-

NOTES;
1. POSITIONAL TOLERANCE OF LEADS (0).
SHALL BE WITHIN 0.25mm (0.010) AT
MAXIMUM MATERIAL CONDmON,lN
RELATION TO SEATING PLANE AND EACH
OTHER.
2. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL
3. DIMENSION B DOES NOT INCWDE MOLD
FLASH.
4. 710.(11 OBSOLETE, NEW STANDARD 710.Q2.

1

~::::::::::]J

B

~c
F

PSUFFIX
CASE 711-03
Plastic Package

D

SEATING
PLANE

~",

J
K
L
M
N

~::::::::::::::::: ]J

DIM
A
B
C
0
F
G
H

'I c~

~.'
A

F, P, P-3 SUFFIX
CASE 724-03
Plastic Package
RaJA = 100°CIW (Typ)

N_

I~:::::::::::I --,00
III
~. "III ~ UJ.-H
JGL
PLANE

J
K
L
M
N

MILUMETERS
MIN
MAX
51.69 5~45
13.72 14.22
3.94
5.08
0.36
0.56
1.02
1.52
2.54BSC
1.65
2.16
0.20
0.38
2.92
3.43
15.24BSC
IS"
0"
0.51
1.02

INCHES
MIN
MAX
2.035 2.065
0.540 0.560
0.155 0.200
0.014 0.022
0.040 0.060
0.100BSC
0.D65 0.085
0.008 0.015
0.115 0.135
O.600BSC
0"
IS"
0.020 0.040

NOTES:
1. CHAMFERRED CONTOUR OPTIONAL
2. DIM "no CENTER OF LEADS WHEN
FORMED PARALLEL
3. DIMENSIONS AND TOLERANCES PER
ANSI Y14.5M, 1982.
4. CONTROLUNG DIMENSION: INCH.

11

[!&]

INCHES
MIN
MAX
1.435 1.465
0.540 0.560
0.155 0.200
0.014 0.022
0.040 0.060
O.I00BSC
0.D65 0.085
0.008 0.015
0.115 0.135
0.600BSC
0"
W
0.020 0.040

PUN'

1

I-

MIWMETERS
IIIN
IlAX
36.45 37.21
13.72 14.22
3.94
5.08
0.56
0.36
1.02
1.52
2.54BSC
1.65
~16
0.20
0.38
2.92
3.43
15.24BSC
0"
W
0.51
1.02

NOTES:
1. POSITIONAL TOLERANCE OF LEADS (0),
SHALL BE WITHIN 0.25 mm (0.010) AT MAXIMUM
MATERIAL CONDmON,lN RELATION TO SEATING
PLANE ANO EACH OTHER.
2. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL
3. DIMENSION B DOES NOT INCLUDE MOLD FLASH.

1

I"

DIM
A
B
C
D
F
G
H

Fi~,

E--- F

-JLJ24PL

f-l!!!!.
~
J.+
~
D

M

1+lo.25!o.Olo1@J ITI B@JI

D24PL

Illo.25!O,OI01@JITI A@JI

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
13-8

E
F
G

J
K
L
M

T

I"r

32.13
6.85
4.44
0.51
1.27BSC
1.02
1.52
2.54BSC
0.18
0.30
2.60
3.55
7.62BSC
IS"
0"
0.51
1.01

INCHES
MIN
IIAX
1.230 1.265
0.250 0.270
0.145 0.175
0.015 0.020
O.05OBSC
0.040 0.060
O.I00BSC
0.007 0.012
0.110 0.140
O.300BSC
0"
IS"
0.020 0.040

J, LSUFFIX
CASE 726-04

NOTES:
1. LEADS, TRUE POSITIONED WITHIN 0.25 mm
(0.010) DlA. AT SEATING PLANE, AT MAXIMUM
MATERIAL CONDITION.
2. DIM"r TO CENTER OF LEADS WHEN FORMED
PARALLEL
3. DIM W & "B" INCLUDES MENISCUS.
4. "F" DIMENSION IS FOR FULL LEADS. "HALF"
LEADS ARE OPTIONAL AT LEAD POSITIONS
1,9,10, AND 18.

Ceramic Package
RaJA; 1OO"C/W (Typ)

OPTIOIW. LEAD
CONFIG. (1,9,10,18)

MILUMETERS
MIN
MAX
22.35 23.11
6.10
7.49
5.08
0.38
0.53
1.40
1.78
2.54 BSC
0.51
1.14
0.20
0.30

~~~~

DIM
A
B
C
D
F
G
H
J

K

3.18

SEATING

L
M
N

7.62 BSC
0"
15"
0.51
1.02

~~l~'-M

PlANE

4.32

INCHES
MIN
MAX
0.880 0.910
0.240 0.295
0.200
0.015 0.021
0.055 0.070
0.100 BSC
0.020 0.045
0.008 0.012
0.125 0.170
0.300 BSC
0"
15 "
0.020 0.040

LSUFFIX
CASE 732-03

Ceramic Package

NOTES:
1. LEADS WITHIN 0.25 mm (0.010) DIA.,
TRUE POSITION AT SEATING PLANE,
AT MAXIMUM MATERIAL CONDITION.
2. DIM L TO CENTER OF LEADS WHEN
FORMED PARALLEL
3. DIM A AND B INCLUDES MENISCUS.

RaJA; 75"C/W (Typ)

DIM
A
B
C
D
F

G
H
J

K
L
M
N

MILLIMETERS
MIN
MAX
23.88 25.15
6.60
7.49
3.81
5.08
0.38
0.56
1.40
1.65
2.54BSC
0.51
1.27
0.20
0.30
3.18
4.06
7.62BSC
0"
15"
0.25
1.02

INCHES
MIN
MAX
0.940
0.990
0.260
0.295
0.150 0.200
0.015 0.022
0.055
0.065
0.100 BSC
0.020 0.050
0.008
0.012
0.125 0.160
0.300 asc
0"
15"
0.010 0.040

LSUFFIX
CASE 733-04

Ceramic Package

[::::::::]J

NOTES:
1. DIM A AND B INCLUDES MENISCUS.
2. DIM -~ TO CENTER OF LEADS WHEN
FORMED PARALLEL
3. DIMENSIONING AND TOLERANCING PER
ANSI Y14.S, 1982.
4. CONTROLLING DIM: INCH.
5. 733-03 OBSOLETE, NEW STANDARD 733-04.

I

DIM
A
B
C
D
F

G
J

K
L
M
N

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

13-9

MILLIMETERS
I,IAX
1.1111
36.45 37.84
12.70 15.36
4.06
5.84
0.38
0.55
1.27
1.65
2.54 BSG
0.20
0.30
3.18
4.06
lS.24BSC
15"
0"
0.51
1.27

INCHES
MIN
MAX
1.435 1.490
0.500 0.605
0.160 0.230
0.015 0.022
0.050 0.065
O.lQOBSC
0.008 0.012
0.125 0.160
0.600BSC
15"
0"
0.020 0.050

DII

PSUFFIX
CASE 738-03
Plastic Package
ROJA = 75°CIW (Typ)

J'_
1

NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI YI4.5M, 1982.
2. CONTROLUNG DIMENSION: INCH.
3. DlMENSlON"r TO CENTER OF lEAD WHEN
FORMED PARALLEL
4. DIMENSION "8" DOES NOT INCWDE MOLD
FLASH.
5. 738-02 OBSOlETE, NEW STANDARD 738.()3.

~~

f~::::::::~1t

1H~

rC

~;

1:11111

~

B

IEIj~' ".J f

..... G--

I tI

F

1

.'

J~tLlt
G

1

C

~RX45O

Jet,

.~
7

J!lltl"-@I".I
7 PI.

Hj~tH_LLH.

1

C

~RX45O

~~~_~_CJ'p_CJJLt! :~NG tJ~
M
I t I 0.25(0.010) ® I TI B

®

IA

~54BSC

0.21
0.38
2.80
3.55
7.62BSC
15°
0°
0.51
1.01

INCHES
MIN
MAX
1.010 1.070
0.240 0.260
0.150 0.180
0.Q15 0.022
0.050BSC
0.050 0.070
O.IOOBSC
0.008 0.015
0.110 0.140
0.3OOBSC
0°
15"
0.020 0.040

Dill
A
B
C
D
F

G
J
K
II
P

MIWIIETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.18
0.25
0.10
0.25
0°
7°
5.80
6.20
0.25
0.50

INCHES
MIN
MAX
0.189 0.196
0.150 0.157
0.054 0.068
0.014 0.019
0.016 0.049
0.050BSC
0.007 0.009
0.004 0.009
0°
7°
0.229 0.244
0.010 0.019

NOTES:
1. DIMENSIONS A AND B ARE DATUMS AND
TIS A MTUM SURFACE.
2. DIMENSIONING AND TOLERANCING PER
ANSI YI4.5M. 1982.
3. CONTROWNG DIMENSION: MIWMETER.
4. DIMENSION A AND B DO NOT INCWDE MOLD
PROTRUSION.
5. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.

ifi-nftR-tJ
"
I,G)

N

R

I PI.

1

II

..".I"·1

OPL

ItI 0.25(0.010) ®I TI B ® IA ® I

14#

K
L

ETERS
MAX
27.17
6.60
4.57
0.39
0.55
1.27B5O
1.27
1.77

NOTES:
1. DIMENSIONS "II' AND 'Bo ARE DATUMS
AND"T" IS A DATUM SURFACE.
2. DIMENSIONING AND TOLERANCING PER
ANSI YI4.5M, 198~
3. CONTROWNG DIM: MIWMETER.
4. DIMENSION "II' AND "8" DO NOT INCLUDE
MOLD PROTRUSION.
5. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.

ITLb.<;32d=p'~ t~(
o SUFFIX
CASE 7S1A-02
Plastic Package
(50-14)

G
J

DIT
I l t I 0 ,25(0.010)@ITI B@I
0.25 (0.010)@ T A@

F%l
· '1j Itl~
G)

D
E
F

J20PL

o SUFFIX
CASE7S1'()3
Plastic Package
(50-8, SOP-8)

s.

~p.
r-"Ai-!
raIT

®I

h. .i
F.J l!J

DIM
A
B
C
D
F

G
J
K
M
P
R

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
13-10

IIIWMETERS
MIN
MAX
8.55
8.75
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
I.27BSC
0.19
0.25
0.10
0.25
7"
0°
5.80
6.20
0.25
0.50

INCHES
IIIN
MAX
0.337 0.344
0.150 0.157
0.054 0.068
0.014 0.019
0.016 0.049
O.05OBSC
0.009 0.009
0.004 0.009
0°
7°
0.229 0.244
0.010 0.019

o SUFFIX
CASE 7518-03

NOTES:
1. DIMENSIONS AAND B ARE DATUMS AND
T IS A DATUM SURFACE.
2. DIMENSIONING AND TOUERANCING PER
ANSI VI4.5M, 1982.
3. CONTROLLING DIMENSION: MIWMETER.
4. DIMENSION A AND B DO NOT INCLUDE MOLD
PROTRUSION.
5. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.

Plastic Package
(SO-16)

I;-RT~-n;@
16'
1

"

.~



0.25 (0.010®

ITI A®I

G

H
J
K
M
N

1+------1 -A f-------+f

Q

R
S
U
V

w

•

J
H
JL09PL

IF.t-T1

FNSUFFIX

<\>

0.25 (0,010®

-'-1T"TI-A-==®"I

•
YORK

B

1- 0

ITI c® I

""'0.2=5""-(0.""01""0®=M

:..::<\>

CASE 775-02
Plastic Package
(PLCC·20)
RaJA = 72°C/w(Typ)
(SkSQML)

ItI

ItI'.18(0.007) ®ITIN®-P®ll®-M®1
u ItI 018~007)

®ITI N®-P®ll®-M®1

NOTES:
1. DATUMS .~, ·M·, ·N·, AND .p. DETERMINED
WHERE TOP OF LEAD SHOULDER EXIT
PLASllC BODY AT MOLD PARTING LINE.
2. DIM GI, TRUE POSITION TO BE MEASURED AT
DATUM .T-, SEAllNG PLANE.
3. DIM RAND UDO NOT INCWDE MOLD
PROTRUSION. Au.oWABLE MOLD PROTRU·
SION IS 0.25 (0.010) PER SIDE.
4. DIMENSIONING AND TOLERANCING PER ANSI
YI4.5M,I982.
5. COt-lTROLUNG DIMENSION: INCH.

D1M
G1

A
B
C
E
F
G

H
J
K

DETAILS

6.60

3.45
3.65
0.40
0.55
9.35
9.60
1.40
1.60
2.54BSC
1.71
1.51
0.360 D.400
3.95
4.20
300 BAC
2.50
2.70
3.15
3.45
13.60 13.90
1.65
1.95
22.00 22.20
0.55 0.75
2.89BSC
0.65
0.75
2.70
2.80

INCHES
MIN
MAX
0.873 0.897
0.252 0.260
0.135 0.143
0.015 0.021
0.366 0.377
0.055 0.062
0.100BSC
0.059 0.067
0.014 0.D15
0.155 0.165
300 BAC
0.099 0.06
0.124 0.135
0.535 0.547
0.064 0.076
0.866 0.874
0.021 0.029
0.113BSC
0.025 0.029
0.106 0.110

DETAILS

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
13-13

R
U
V
W
X
Y
Z
Gl
Kl
ZI

MIWUETERS
MIN
MAX
9.78 10.03
9.78 10.03
4.20
4.57
2.29
2.79
0.33
0.48
1.27BSC
0.66
0.81
0.51
0.64
8.89
9.04
8.89
9.04
1.07
1.21
1.07
1.21
1.07
1.42
0.50
2°
10°
7.88
8.38

MIN
MAX
0.385 0.395
0.385 0.395
0.165 0.180
0.090 0.110
0.013 0.019
O.050BSC
0.026 0.032
0.020
0.025
0.350 0.356
0.350 0.356
0.042 0.048
0.042 0.048
0.042 0.056
0.020
2°
10°
0.310 0.330

1.02

0.040

2°

10 °

INCHES

2°

10°

I

III

I

FNSUFFIX

CASE 776-02
Plastic Package
(PLCC-28)
RaJA = 66°CIW(Typ)
(5kSQML)

•
B

YBRK

It IO.18~.D07) ®ITI N@.p.4

ec
@.t
CX)N'

'""'! '"'"
e.e.
~

:g

'" ci

+-1

V

::I:

@

co

'"'"
e.
'"ci'"

+
I---;;-':--t'~

r-~--~~
DETAIL A

1+10.20(0.008) ®

IHI A-B® I D ® I

BASE METAL

1+10.02(0.008) ®

lei A-B® I D ® I

SECTION B-B

DETAILC

NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI YI4.5M. 1982.
2. CONTROWNG DIMENSION: MILUMETER.
3. DATUM PLANE ·H·IS LOCATED AT BonOM
OF LEAD AND IS COINCIDENT WITH THE LEAD
WHERE THE LEAD EXITS THE PLASTIC BODY
AT THE BonOM OF THE PARTING UNE.
4. DATUMS ·A-. ·B· AND ·D· TO BE DETERMINED
AT DATUM PLANE ·H·.
5. DIMENSIONS S AND V TO BE DETERMINED AT
SEATING PLANE ·C·.
6. DIMENSIONS A AND B DO NOT INCWDE MOUD
PROTRUSION. ALLOWABLE PROTRUSION IS
0.25 (0.010) PER SIDE. DIMENSIONSAAND B DO
INCWDE MOLD MISMATCH AND ARE DETER·
MINED AT DATUM PLANE ·H·.
7. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAM BAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE D DIMENSION AT MAXIMUM
MATERIAL CONDITION. DAMBAR CANNOT BE
LOCATED ON THE LOWER RADIUS OR THE FOOT.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
13-16

DIM
A
B

C
D
E
F
G
H
J
K
L
M
N
Q

R
S
U
y

W

x

MILUMETERS
MIN
MAX
9.90 10.10
9.90 10.10
2.10
2.45
0.22
0.38
2.00
2.10
0.22
0.33
O.65BSC
0.25
0.13
0.23
0.65
0~5
7.80 REF
5'
10'
0.13
0.17
7'
0'
0.13
0.30
12.95 13.45
0.13
0'
12.95
13.45
0.35
0.45
1.6 REF

INCHES
MIN
MAX
0.390 0.398
0.390 0.398
0.083 0.096
0.009 0.Q15
0.079 0.083
0.009 0.013
0.026 BSC
0.010
0.005 0.009
0.026 0.037
0.307 REF
5'
10'
0.005 0.007
0'
7'
O.OOS 0.012
0.510 0.530
0.005
0'
0.510

0.530

0.014 0.018
0.063 REF

FUSUFFIX
CASE 873-01

Plastic Package
(32 Pin Flat Pack)
~------L------~

€)

€)

C

C

€)
ca

€)
ca

..(

..(

:I:
ca V
@..(
@

0

i~
dC!
~.e.

~~
0

+-1

~

~

!i!
0

+

s

Iflo.20(O.OO8)® IHI A-B® I D ®

I

t

C

L:ID

*

SEATING
PLANE

SECTIONB

c.=.d----f P
tt

~

DETAIL A

T

QIJ
DAiUU
PLANE

+1

R

~j~

NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI YI4.5M. 1982.
2. CONTROWNG DIMENSION: MILUMETER.
3. DATUM PLANE -H-IS LOCATED AT BOTIOM
OF lEAD AND IS COINCIDENT WITH THE lEAD
WHERE THE lEAD EXITS THE PLASTIC BODY
AT THE BOTTOM OF THE PARTING UNE.
4. DATUMS -A-, ·B- AND ·0· TO BE DETERMINED
AT DATUM PLANE ·H·.
5. DIMENSIONS S AND V TO BE DETERMINED AT
SEATING PLANE ·C·.
S. DIMENSIONS A AND B DO NOT INCLUDE MOlD
PROTRUSION. ALLOWABLE PROTRUSION IS
0.25 (0.010) PER SIDE. DIMENSIONS A AND B DO
INCWDE MOlD MISMATCH AND ARE DETER·
MINED AT DATUM PLANE ·H·.
7. DIMENSION 0 DOES NOT INCWDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.011 (0.0031 TOTAL IN
EXCESS OF THE 0 DIMENSION IiJ MAXIMUM
MliJERIAL CONDITION. DAMBAR CANNOT BE
LOCATED ON THE LOWER RADIUS OR THE FOOt

DETAILC

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
13-17

0111
A
B
C
0
E
F
G
H

J
K
L
II
N
P
Q

R
5

U
V
X

M1WME1ERS
IIIN
IIAX
6.95
7.10
7.10
6.95
1.40
1.60
0.273 0.373
1.30
1.50
0.273
O.90BSC
0.20
0.119 0.197
0.33
0.57
5.6 REF

60~

0.119
0.40
50
0.15
0.25
6.65
9.15
0.15
0.25
50
11 0
8.85
9.15
1.0 REF

INCHES
IIIN
IIAX
0.274 0.280
0.274 0.210
0.055 0.063
0.010 0.015
0.051 0.059
0.010
0.031 BSC
0.0011
0.005 0.0011
0.013 0.022
0.220 REF
60
60
0.005 0.005
0.016BSC
50
10"
0.006 0.010
0.348 0.360
0.006 0.00
50
11 0
0.346 0.360
0.039 REF

TSUFFIX
CASE 894·01
Plastic Package
(23-Pin ZIP)

NOTES:
1. OIMENSIONING AND TOLERANCEING PER
ANSI Y14.5M, 1982.
2, CONTROUNG DIMENSION INCH.
3. DIMENSION R OOES NOT INCLUDE MOUD
FLASH OR PROTRUSIONS.
4. DIMENSION B DOES NOT INCLUDE MOUD
FLASH OR PROTRUSIONS.
5. MOUD FLASH OR PROTRUSIONS SHALL NOT
EXCEED 0.250 (0.010).
6. OVERALL LEAD LENGTli DOES NOT INCWDE
LEAD FINISH.

I+t 0.152(0.006@ITI o® I N® I

DIM
A
B
C
D

E
F
G

H
J
K
L
M
N

23

P
Q

J

23 PL

S6AnNG
PLANE

1+10.610 (0.240)@ITI

FSUFFIX
CASE 904·01
Plastic Package

R
S
U
Y

W

MILUMETERS
MIN
MAX
17.374 17.627
30.048 30.302

4.445 4.547
0.660 0.787
1.473
1.574
4.191
4.445
1.270BSC
4.293BSC
0.356 0.508
15.875 16.231
19.558 20.066
4.039BSC
3.760 3.861
9.906 BSC
3.760 3.861
10.566 10.770
4.089 4.394
2.667 2.921
17.577 17.932
9.373 BSC

INCHES
MIN
MAX
0.684 0.694
1.183 1.193
0.175 0.179
0.026 0.031
0.058 0.062
0.165 0.175
0.050 BSC
0.169 BSC
0.014 0.020
0.625 0.839
0.770 0.790
0.159BSC
0.148 0.152
0.390 BSC
0.148 0.152
0.416 0.424
0.161
0.173
0.105 0.115
0.692 0.706
0.369 BSC

•
1

/VIEWA

IW~
S

1+[200 (.OOS'[Ml ITI z ® I y ® I

~ttt

NOTES:
1. OIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLUNG DIMENSION: MILUMETER.
3. DIMENSIONS AAND B DO NOT INCLUDE
MOUD PROTRUSION. MOUD PROTRUSION
SHALL NOT EXCEED .150 (.006) PER SIDE.

DIM
A
B
C
D
G
H
J
K
Q

S
X

1+[200 l.oos'[MlITI y®1 z®1
VIEW A

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

13·18

MILUMETERS
MIN
MAX
5.100 5.450
5.100 5.400
2.050
0.350 0.500
1.270 BASIC

0.050

0.200

0.180 0.270
0.500 0.850
00
100
7.400 8.200
1.260 REF

INCHES
MIN
MAX
0.201
0.214
0.201
0.216
0.080
0.014 0.001
0.050 BASIC
0.002 0.007
0.008 0.010
0.020 0.033
00
100
0.292 0.322
0.0496 REF

Quality and Reliability Assurance

In Brief ...
The word quality has been used to describe many
things, such as fitness for use, customer satisfaction,
customer enthusiasm, what the customer says quality is,
etc. These descriptions convey important truths, however.
quality should be described in a way that precipitates
immediate action. With that in mind, quality can be
described as reduction of variability around a target, so that
conformance to customer requirements and possibly
expectations can be achieved in a cost effective way. This
definition provides direction and potential for immediate
action for a person desiring to improve quality.
The definition of quality as described above can be
applied to a task, process or a whole company. If we are to
reap the benefits of quality and obtain a competitive
advantage, quality must be applied to the whole company.
Implementation of quality ideas company wide requires
a quality plan showing: a philosophy (belief) of operation,
measurable goals, training of individuals and methods
of communicating this philosophy of operation to the
whole organization.
Motorola, for example, believes that quality and
reliability are the responsibility of every person.
Participative Management is the process by which problem
solving and quality improvement are facilitated at all levels
of the organization through crossfunctional teams.
Continuous improvement for the individual is facilitated by
a broad educational program covering onsite, university
and college courses. Motorola University provides
leadership and administers this educational effort on a
company wide basis.
Another key belief is that quality excellence is accomplished by people doing things right the first time and
committed to never ending improvement. The Six Sigma
(6a) challenge is designed to convey and facilitate the idea
of continuous improvement at all levels.

Page

Quality Concepts ................................ 14-2
Reliability Concepts. . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Analog Reliability Audit Program ............. ....
Weekly Reliability Audit ............ , ...........
Quarterly Reliability Audit . . . . . . . . . . . . . . . . . . . . . ..

14-5
14-7
14-8
14-8

Quality Concepts
Quality improvement for a task or a process can be quickly
described in terms of the target, current status with respect to
target (variability), reduction of variability (commitment to
never ending improvement), customer requirements (who
receives output, what are a person's requirements/
expectations) and economics (cost of nonconformance, loss
function, etc.).
Application of quality to the whole company has come to be
known by such names as "Total Quality Control" (TQC);
"Company Wide Quality Control" (CWQC); "Total Quality
Excellence" or "Total Quality Engineering" (TQE); "Total
Quality Involvement" (TQI). These names attempt to convey
the idea that quality is a process (a way of acting continuously)
rather than a program (implying a beginning and an end).
Nevertheless for this process to be successful it must be able
to show measurable results.
"Six Sigma is the required capability level to approach the
standard. The standard is zero defects. Our goal is to be
Best-in-Class in product, sales and service." (For a more
detailed explanation, contact your Motorola Representative
for a pamphlet of the Six Sigma Challenge.)
Quick insight into six sigma is obtained if we realize that a
six sigma process has variability which is one half of the
variation allowed (tolerance, spread) by the customer
requirements (i.e. natural variation is one half of the customer
specification range for a given characteristic). When six sigma
is achieved, virtually zero defects are observed in the output
of a process/product even allowing for potential process shifts
(Figure 1).
Policies, objectives and five year plans are the mechanisms
for communicating the key beliefs and measurable goals to all
personnel and continuously keeping them in focus. This is
done at the corporate, sector, group, division, and department
levels.

The Analog Division, for example, evaluates performance
to the corporate goals of 10 fold improvement by 1989; 100
fold improvement by 1991 and achievement of six sigma
capability by 1992 by utilizing indices such as Outgoing
Electrical and Visual Mechanical Quality (AOQ) in terms of
PPM (parts per million or sometimes given in parts per billion);
% of devices with zero PPM ; product quality returns
(RMR); number of processes/products with specified capability indices (cp, cpk); six sigma capability roadmaps;
failure rates for various reliability tests (operating life,
temperature humidity bias, hast, temperature cycling, etc.);
on-time delivery; customer product evaluation and failure
analysis turnaround; cost of nonconformance; productivity improvement and personnel development.
Figure 2 shows the improvement in electrical outgoing
quality for analog products over recent years in a normalized
form. Figure 3 shows the number of parts with zero PPM over
a period of time.
Documentation control is an important part of statistical
process control. Process mapping (flow charting etc. ) with
documentation identified allows visualization and therefore
optimization of the process. Figure 4 shows a portion of a flow
chartforwaferfabrication. Control plans are an important part
of Statistical Process Control, these plans identify in detail
critical points where data for process control is taken,
parameters measured, frequency of measurements, type of
control device used, measuring equipment, responsibilities
and reaction plans. Figure 5 shows a portion of a control plan
for wafer fabrication. Six sigma progress is tracked by
roadmaps based on the six sigma process, a portion of which
is shown on Figure 6.
On-time delivery is of great importance, with the current
emphasis on just-in-time systems. Tracking is done on an
overall basis, and at the device levels.

Figure 1. A Six Sigma Process Has Virtually Zero
Defects Allowing for 1.50" Shift
Six Sigma Capability

Cp = 2
Cpk=I.5

Cp = 2
Cpk = 1.5

Virtually
Zero Defects
(3.4 ppm)

I
-60"

-50"

-40"

-30"

-20"

-10

0"

10"

20

30"

40"

± Six Sigma Design Specification Width

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
14-2

50"

60"

Figure 2. Motorola Logic & Analog Technologies Group Electrical AOQ
100
90
80
70
I=" 60
:z
w
<.>

a:

~ 50

(3

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30
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1988

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High Point Per Year, Normalized 1980 = 100%

Figure 3. Percentage of Parts with Zero PPM AOQ
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Percentage of Product Unes Each Month with 0 PPM for VI5/MECH and ELC AOQ

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
14-3

-

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-~ -~ lfu~- It; Ie; 1fi31~
-~ ~- Iff!
I ..., 1:5
..., Ig
 & K are constants, T is temperature, RH is
relative humidity, E is the electric field, etc.
The most familiar form of this equation deals with the first
exponential which shows an Arrhenius type relationship of
the failure rate versus the junction temperature of integrated
circuits, while the causes of failure generally remain the same.
Thus we can test devices near their maximum junction
temperatures, analyze the failures to assure that they are the
types that are accelerated by temperature and then applying
known acceleration factors, estimate the failure rates for lower
junction temperatures. The Eyring or Arrhenius relationships
should be used for failure rate projections in conjunction with
proper understanding of failure modes, mechanisms and
patterns such as infant mortality, constant failure rate (useful
region) and wearout. For example if by design and proper
process control infant mortality and useful period failures have
been brought to zero and wearout failures do not start until, let
us say, 30,000 hours at 125°C then failure rate projections at
lower temperatures must account for these facts and whether
the observed wearout failures occur at lower temperatures.
Figure 7 shows an example of a curve which gives
estimates of failure rates versus temperature for an integrated
circuit case study.
Arrhenius type of equation:
where:

A
A

e


K
T

A = Ae - -.i
KT

Failure Rate
Constant
2.72
Activation Energy
Botzman's Constant
Temperature in Degrees Kelvin

10

--l

rnw

~~
Ow

,
1\

Non·Burned·ln Product

-z
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1.0

w(.)

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C::>f!.

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;:;:®

0.01

\.

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0.001
500 400 300

200 150 100
50 25
TJ, JUNCTION TEMPERATURE (OC)

Figure 8. A Model for Failure Distribution
in Time Domain Bathtub Curve Model
- - - Parts/Equipment
- - - Integrated Circuits (Past)
- -Integrated Circuits (PresenUFuture)
A

B

C

w

~

w

c::

:3

I

',-.......

-----'1.'1:-_

ii:

/

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,
/'

LIFETIME

TJ = TA + BJA PD or TJ = TC + BJC PD
where:

TJ
Junction Temperature
TA = Ambient Temperature
TC = Case Temperature
BJA = Junction to Ambient Thermal
Resistance
BJC = Junction to Case Thermal
Resistance
PD = Power Dissipation

Life patterns (failure rate curves) for equipment and
devices can be represented by an idealized graph called the
Bathtub Curve (Figure 8).
There are three important regions identified on this curve. In
Region A, the failure rate decreases with time and it is
generally called infant mortality or early life failure region. In
Region B, the failure rate has reached a relatively constant
level and it is called constant failure rate or useful life region.
In the third region, the failure rate increases again and it is
called wearout region. Modern integrated circuits generally
do not reach the wearout portion of the curve when operating
under normal use conditions.

Decreasing Failure Rate

Constant Failure Rate

Increasing failure Rate

Infant Mortality

Useful Ufe

Wearout

Random (Chance) Defects
(No Pattern; Occur
Regularly)
Weibull
Exponential for Equipment
Log Normal for ICs

Material, Design,
Process Umitations

Burn-In
Manufacturing Variations
Workmanship Defects
Weibull
Log Normal
Gamma Distribution

Weibull
Normal (Gaussian)

The wearout portion of the curve can usually be identified by
using highly accelerated test conditions. For modern
integrated circuits, even the useful life portion of the curve may
be characterized by few or no failures. As a result the bathtub
curve looks like continuously declining (few failures, Figure 8,
Curve B) or zero infant and useful period failures (constant
failure rate until wearout, Curve C).
The infant mortality portion of the curve is of most interest
to equipment manufacturers because of its impact on
customer perception and potential warranty costs. In recent
years the infant mortality portion of the curve for integrated
circuits, and even equipment, has been drastically reduced

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
14-6

(Figure 8, Curve C). The reduction was accomplished by
improvements in technology, emphasis on statistical process
control, reliability modeling in design and reliability in
manufacturing (wafer level reliability, assembly level reliability,
etc.). In this respect many integrated circuit families have zero
or near zero failure patterns until wearout starts.
Does a user still need to consider burn-in? For this question
to be answered properly the IC user must consider the target
failure rate olthe equipment, apportioned to the components
used, application environment, maturity of equipment and
components (new versus mature technology), the impact of a
failure (Le. safety versus casual loss of entertainment),
maintenance costs, etc. Therefore, if the IC user is going
through these considerations for the first time, the question of
burn-in at the component level should be discussed during a
user-vendor interface meeting.
A frequently asked question is about the reliability
differences between plastic and hermetic packaged
integrated circuits. In general, for all integrated circuits
including analog, the field removal rates are the same for
normal use environments, with many claims of plastic being
better because of its "solid block" structure.
The tremendous decrease of failure rates of plastic
packages has been accomplished by continuous
improvements in piece parts, materials and processes.
Nevertheless, differences can still be observed under highly
accelerated environmental stress conditions. For example, if
a bimetallic (gold wire and aluminum metallization) system is
used in plastic packages and they are placed on a high
temperature operating life test (125°C) then failures in the form
of opens, at the gold to aluminum interface, may not be
observed until 30,000 hours of continuous operating life.
Packages, whether plastic or hermetic, with a monometallic
system (aluminum wire to aluminum metallization) will have no
opens because of the absence of the gold to aluminum
interface. As a result, a difference in failure rates will
be observable.
Differences in failure rates between plastics and hermetics
may also be observed if devices from both packaging systems
are placed in a moist environment such as 85°C, 85% RH with
bias applied. At some point in time plastic encapsulated ICs
should fail since they are considered pervious by moisture,
(the failure mechanism being corrosion of the aluminum
metallization) while hermetic packages should not fail since
they are considered impervious by moisture. The reason the
word "should" was used is because advances in plastic
compounds, package piece parts, encapsulation processes
and final chip passivation have made plastic integrated
circuits capable of operating more than 5000 hours without
failures in an 85°C, 85% RH environment. Differences in
failure rates due to internal corrosion between plastic and
hermetic packages may not be observable until well after 5000
operating hours.
The aforementioned two examples had environments
substantially more accelerated than normal life so the two
issues discussed are not even a factor under normal use
conditions. In addition, mechanisms inherent in hermetic
packages but absent in plastics were not even considered
here. Improved reliability of plastic encapsulated ICs has
decreased demand of hermetic packages to the point where
many devices are offered only in plastic packages. The user
then should feel comfortable in using the present plastic
packaging systems.

A final question that is asked by the IC user is, how can one
be assured that the reliability of standard product does not
degrade over time? This is accomplished by our emphasis on
statistical process control, in-line reliability assessment
and reliability auditing by periodic and strategic sampling
and accelerated testing of the various integrated circuit
device packaging systems. A description of these audit
programs follows.

Analog Reliability Audit Program
The reliability of a product is a function of proper
understanding of the application and environmental
conditions that the product will encounter during its life as well
as design, manufacturing process and final use conditions.
Inherent reliability is the reliability which a product would
have if there were no imperfections in the materials, piece
parts and manufacturing processes of the product. The
presence of imperfections gives rise to reliability risks. Failure
Mode and Effects Analysis (FMEA) is a technique for
identifying, controlling and eliminating potential failures from
the design and manufacture of the product.
Motorola uses on-line and off-line reliability monitoring in
an attempt to prevent situations which could degrade
reliability. On-line reliability monitoring is at the wafer and
assembly levels while off-line reliability monitoring involves
reliability assessment of the finished product through the use
of accelerated environmental tests.
Continuous monitoring of the reliability of analog integrated
circuits is accomplished by the Analog Reliability Audit
Program, which is designed to compare the actual reliability
to that specified. This objective is accomplished by periodic
and strategic sampling of the various integrated circuit device
packaging systems. The samples are tested by subjecting
them to accelerated environmental conditions and the results
are reviewed for unfavorable trends that would indicate a
degradation of the reliability or quality of a particular packaging
system. This provides the trigger mechanism for initiating an
investigation for root cause and corrective action.
Concurrently, in order to provide a minimum of interruption of
product flow and assure that the product is fit for use, a lot by
lot sampling or a non-destructive type 100% screen may be
used to assure that a particular packaging system released for
shipment does have the expected reliability. This rigorous
surveillance is continued until there is sufficient proof (many
consecutive lots) that the problem has been corrected.
The Logic and Analog Technologies Group has used
reliability audits since the late sixties. Such programs have
been identified by acronyms such as CRP (Consumer
Reliability Program), EPIIC (Environmental Package
Indicators for Integrated Circuits), LAPP (Linear Accelerated
Punishment Program), and RAP (Reliability Audit Program).
Currently, the Analog Reliability Audit Program consists of
a Weekly Reliability Audit and a Quarterly Reliability Audit.
The Weekly Reliability Audit consists of rapid (short time)
types of tests used to monitor the production lines on a real
time basis. This type of testing is performed at the
assemblyltest sites worldwide. It provides data for use as an
early warning system for identifying negative trends and
triggering investigations for root cause and corrective actions.

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

14-7

l1li

I

The Quarterly Reliability Audit consists of long term types of
tests and is performed at th u.s. Bipolar Analog Division
Center. The data obtained from the Quarterly Reliability Audit
is used to assure that the correlation between the short term
weekly tests and long term quarterly tests has not changed
and a new failure mechanism has not appeared.
A large data base is established by combining the results
from the Weekly Reliability Audit with the results from the
Quarterly Reliability Audit. Such a data base is necessary for
estimating long term failure rates and evaluating potential
process improvement changes. Also, after a process
improvement change has been implemented, the Analog
Reliability Audit Program provides a system for monitoring the
change and the past history data base for evaluating the affect
of the change.

Weekly Reliability Audit
The Weekly Reliability Audit is performed by each
assembly/test site worldwide. The site must have capability for
final electrical and quality assurance testing, reliability testing
and first level of failure analysis. The results are reviewed on
a continuous basis and corrective action is taken when
appropriate. The results are accumulated on a monthly basis
and published.
The Reliability Audit test plan is as follows:
Electrical Measurements: Performed initially and after
each reliability test, consist of critical parameters and
functional testing at 25°C on a go-no-go basis.
High Temperature Operating Life: Performed to detect
failure mechanisms that are accelerated by a combination of
temperature and electric fields. Procedure and conditions are
per MIL-STD-883, Method 1015 with an ambient temperature
of 145°C for 40 hours or equivalent based on a 1.0 eV
activation energy and the Arrhenius equation.
Approximate Accelerated Factors
125°C
4
1

50°C
4000
1000

Temperature CyclinglThermal Shock: Performed to
detect mechanisms related to thermal expansion and
contraction of dissimilar materials, etc. Procedures and
conditions are per MIL-STD-883, Methods 1010 or 1011, with
ambient temperatures of -65° to + 150°C or -40° to +125°C
(JEDEC-STD-22-Al 04), for a minimum of 100 cycles.
Pressure Temperature Humidity (Autoclave): Performed
to measure the moisture resistance of plastic encapsulated
packages. It detects corrosion type failure mechanisms due to
free ionic contaminants that may have entered the package
during the manufacturing processes. Conditions are per
JEDEC-STD-22, Method 102, a temperature of 121°C, steam
environment and 15 psig. The duration of the test is 96 hours
(minimum).
Analysis Procedure: Devices failing to meet the electrical
criteria after being subjected to an accelerated environment
type test are verified and characterized electrically, then
submitted for failure analysis.

Quarterly Reliability Audit
The Quarterly Analog Reliability Audit Program is performed
at the U.S. Bipolar Analog Division Center. This testing is
designed to assure that the correlation between the short term
weekly tests and the longer quarterly tests has not changed
and that no new failure mechanisms have appeared. It also
provides additional long term information for a data base for
estimating failure rates and evaluation of potential process
improvement changes.
Electrical Measurements: Performed initially and at
interim readouts, consist of all standard DC and functional
parameters at 25°C, measured on a go-no-go basis.
High Temperature Operating Life Test: Performed to
detect failure mechanisms that are accelerated by a
combination of temperature and electric fields. Procedure and
conditions are per MIL-STD-883, Method 1015, with an
ambient temperature of 145°C for 40 and 250 hours or
equivalent, based on 1.0 eV activation energy and the
Arrhenius equation.
Approximate Accelerated Factors
125°C
4
1

50°C
4000
1000

Temperature CyclinglThermal Shock: Performed to
detect mechanisms r~,lated to thermal expansion and
contraction, mismatch effects, etc. Procedure and conditions
are per MIL-STD-883, Methods 1010 or 1011, with ambient
temperatures of -65° to +150°C or -40° to +125°C
(J EDEC-STD-22-A 104) for 100, 500 and 1000 or more cycles,
depending on the temperature range used. Temperature
Cycling is used more frequently than Thermal Shock.
Pressure Temperature Humidity (Autoclave): Performed
to measure the moisture resistance of plastic encapsulated
packages. It detects corrosion type failure mechanisms due to
free ionic contaminants that may have entered the package
during the manufacturing processes. Conditions are per
JEDEC-STD-22, Method 102, a temperature of 121°C, steam
environment and 15 psig. The duration of the test is for 96
hours (minimum), with a 48 hour interim readout.
Pressure Temperature Humidity Bias (PTHB; Biased
Autoclaved): This test measures the moisture resistance of
plastic encapsulated packages. It detects corrosion type
failure mechanisms due to free and bounded ionic
contaminants that may have entered the package during the
manufacturing processes, or they may be bound in the
materials of the integrated circuit packaging system and
activated by the moisture and the applied electrical fields.
Conditions are per JEDEC-STD-22, Method 102, with bias
applied, a temperature of 121°C, steam environment and
15 psig. This test detects the same type of failures as the
Temperature Humidity Bias (85°C, 85% RH, with bias) test,
only faster. The acceleration factor between PTHB and THB
is between 20 and 40 times, depending on the type of
corrosion mechanism, electrical field and packaging system.
Highly Accelerated Stress Test (HAST) is increasingly
replacing the aforementioned PTHB test. The reason is that
the HAST test allows control of pressure, temperature and

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

14-8

humidity independently of each other, thus we are able to set
different combinations of temperature and relative humidity.
The most frequently used combination is 130°C with 85% RH.
This has been related to THB (85°C, 85% RH) by an
acceleration factor of 20 (minimum). The ability to keep the
relative humidity variable constant for different temperatures
is the most appealing factor of the HAST test because it
reduces the determination of the acceleration factor to a single
Arrhenius type of relationship. Motorola has been phasing
over to HAST testing since 1985.
Temperature, Humidity and Bias (THB): This test
measures the moisture resistance of plastic encapsulated
packages. It detects corrosion type failure mechanisms due to
free and bounded ionic contaminants that may have entered

the package during the manufacturing processes, or they may
be bound in the materials of the integrated circuit packaging
system and activated by moisture and the applied electrical
fields. Conditions are per JEDEC-STD-22, Method 102 (85°C,
85% RH), with bias applied. The duration is for 1008 hours,
with a 504 hour interim readout. The acceleration factor
between THB (85°C, 85% RH with bias) and the 30°C, 90%
RH is typically 40 to 50 times, depending on the type of
corrosion mechanism, electrical field and packaging system.
Analysis Procedure: Devices failing to meet the electrical
criteria after being subjected to an accelerated environment
type test(s) are verified and characterized electrically, then
they are submitted for root cause failure analysis and
corrective action for continuous improvement.

I

l1li

I

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
14-9

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

14-10

Applications and Product Literature

In Brief ...

s

Motorola Applications Literature provides guidance to
the effective use of its semiconductor families across a
broad range ofpractical applications. Many different topics
are discussed - in a way that is not possible in a device
data sheet - from detailed circuit designs complete with
PCB layouts, through matters to consider when embarking
on a design, to complete overviews of product families and
their design philosophies.
Information is presented in the form of Application
Notes, Article Reprints and detailed Engineering Bulletins.
Abstracts of all the applications documents are provided
as a guide to their content; each abstract also shows the
number of pages in the document, plus the origin of the
article in the case of Article Reprints. Documents new to
this issue are highlighted throughout.

Applications and Product Literature
The application literature listed in this section has been
prepared to acquaint the circuits and systems engineer with
Motorola Linear integrated circuits and their applications. To
obtain copies of the notes, simply list the publications number
or numbers and send your request on your company
letterhead to: Literature Distribution Center, Motorola
Semiconductor Products Inc., P.O. Box 20912, Phoenix,
Arizona 85036.

Application Note Abstracts
AN004E

Semiconductor Consideration for DC Power
Supply Voltage Protector Circuits

This paper addresses the requirements for the
semiconductor sensing circuitry and SCR crowbar devices
used in DC power supply over/under voltage protection
schemes. (8pp)

'Indicates New Document
AN559

AN569

Automotive Direction Indicator with Short
Circuit Detection Using the UAA 1041

Cold lamps and faulty wiring can cause false operation
when using the UAA1041 Automotive Direction Indicator IC.
This note provides simple solutions. (3pp)
AN531

MC1596 Balanced Modulator

The MC1596 Monolithic Balanced Modulator is a versatile
HF communications building block. It functions as a
broadband, double-sideband suppressed-carrier balanced
modulator without the need for transformers or tuned circuits.
This article describes device operation and biasing, and gives
circuit details for typical modulator/demodulator applications
in AM, SSB and suppressed-carrier AM. Additional uses as an
SSB Product Detector, AM Modulator/Detector, Mixer,
Frequency Doubler, Phase Detector and others are also
illustrated. An appendix gives detailed AC and DC analysis.
(13pp)
AN535

Phase-Locked-Loop Design Fundamentals

The fundamental design concepts for phase-locked-loops
implemented with integrated circuits are outlined. The
necessary equations required to evaluate the basic loop
performance are given in conjunction with a brief design
example. (12pp)
AN545A

Television Video IF Amplifier Using
Integrated Circuits

This applications note considers the requirements of the
video IF amplifier section of a television receiver, and gives
working circuit schematics using integrated circuits which
have been specifically designed for consumer oriented
products. The integrated circuits used are the MC1350,
MC1352, and the MC1330. (12pp)

Transient Thermal Resistance - General
Data and its Use

Data illustrating the thermal response of a number of
semiconductor die and package combinations are given. Its
use, employing the concepts of transient thermal resistance
and superposition, permit the circuit designer to predict
semiconductor junction temperature at any point in time during
application of a complex power pulse train. (16pp)
AN587

AN428

A Single Ramp Analog-to-Digital Converter

A simple single ramp AID converter which incorporates a
calibration cycle to ensure an accuracy of 12 bits is discussed.
The circuit uses standard ICs and requires only one precision
part - the reference voltage used in the calibration. This
converter is useful in a number of instrumentation and
measurement applications (1 Opp)

Analysis and Design of the Op Amp
Current Source

Voltage-controlled current sources based on operational
amplifiers are both versatile and accurate, yet the quality of op
amps required is unimportant. This note develops general
expressions for basictransfer function and output impedance,
and shows that simplified equations give a very accurate
description of actual circuit performance. Includes a section on
analysis of the errors)hat result from changes in circuit
parameters and temperature. (7pp)
AN703

Designing Digitally-Controlled Power
Supplies

This application note shows two design approaches; a
basic low voltage supply using an inexpensive MC1723
voltage regulator and a high current, high voltage, supply
using the MC1466 floating regulator with optoelectronic
isolation. Various circuit options are shown to allow the
designer maximum flexibility in an application. (9pp)
AN708A

Line Driver and Receiver Considerations

This report discusses many line driver and receiver design
considerations such as system description, definition of terms,
important parameter measurements, design procedures and
application examples. An extensive line of devices is available
from Motorola to provide the designer with the tools to
implement the data transmission requirements necessary for
almost every type of transmission system. (18pp)
AN719

A New Approach To Switching Regulators

This article describes a 24 V, 3.0 A switching mode supply.
It operates at 20 kHz from a 120 V AC line with an overall
efficiency of 70%. New techniques are used to shape the load
line. The control circuit uses a quad comparator and an
opto-coupler and features short circuit protection. (12pp)

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
15-2

Applications and Product Literature (continued)
AN740

Several converter design examples and numerous
applications circuits with test data are included. (38pp)

The Design of an N-Channel16k x 16 Bit
Memory System for the PDP-11

This application note describes the design and construction
of a mainframe memory system with MCM6605 N-channel
MOS memories. Topics included are: the interface to the
PDP-II, refresh control and bookkeeping, timing control logic
for the memories, memory system considerations and
organization. The memory also features new integrated
circuits that reduce package count and enhance memory
system performance. (16pp)
AN781 A

Revised Data Interface Standards

Revised data interface standards allow higher data rates
and longer cables. This note provides an overview and
comparison of the electrical and performance characteristics
of RS232-C, RS422, RS423, RS449 and RS485. Includes a
list of appropriate Motorola drivers and receivers with
performance summaries. (6pp)
AN829

Application of the MC1374 TV Modulator

Monomax: Application of the MC13001
Monochrome Television Integrated Circuit

This application note presents a complete 12" black and
white line-operated television receiver, including artwork for
the printed circuit board. It is intended to provide a good
starting point for the first-time user. Some of the most common
pitfalls are overcome, and the significance of component
selections and locations are discussed. (12pp)
AN917

Reading and Writing in Floppy Disk
Systems Using Motorola Integrated
Circuits

The floppy disk system has become a widely used means
for storing and retrieving both programs and data. A floppy disk
drive requires precision controls to position and load the head
as will as defined read/write signals in order to be a viable
system. This application note describes the use of the
MC3469 and MC3471 Write Control ICs and the MC3470
Read Amplifier which provide the necessary head and erase
control, timing functions, and filtering. (16pp)
AN920

AN921

Theory and Applications of the MC34063
and I1A 78S40 Switching Regular Control
Circuits

AN932

Application of the MC1377 Color Encoder

The MCI377 is an economical, high quality, RGB encoder
for NTSC or PAL applications. It accepts RGB and composite
sync inputs, and delivers a 1.0 Vp-p composite NTSC or PAL
video output into a 75 Q load. It can provide its own color
oscillator and burst gating, or it can easily be driven from
external sources. Performance virtually equal to high-cost
studio equiprnent is possible with common color receiver
cornponents. (12pp)
Interfacing the Speakerphone to the
MC34010111113 Speech Networks

Interfacing the MC34018 speakerphone circuit to the
MC34010 series of telephone circuits is described in this
application note. The series includes the MC34010,
MC34011, MC34013, and the new "An version of each of
those. The interface is applicable to existing designs, as well
as to new designs. (12pp)
AN958

Transmit Gain Adjustments for the
MC34014 Speech Network

The MC34014 telephone speech network provides for
direct connection to an electret microphone and to Tip and
Ring. In between, the circuit provides gain, drive capability,
and deterrnination of the ac impedance for compatibility with
the telephone lines. Since different microphones have
different sensitivity levels, different gain levels are required
from the microphone to the Tip and Ring lines. This application
note will discuss how to change the gain level to suit a
particular microphone while not affecting the other circuit
parameters. (2pp)
AN959

A Speakerphone with Receive Idle Mode

The MC34018 speakerphone system operates on the
principle of comparing the transmit and receive signals to
determine which is stronger, and then switching the circuit into
that mode. (2pp)
AN960

This paper describes in detail the principle of operation of
the MC34063 and I1A78S40 switching regulator subsystems.

Horizontal APCIAFC Loops

The most popular method used in modern television
receivers to synchronize the line frequency oscillator is the
phase locked loop. The operating characteristics and
parameters of the loops are discussed. (19pp)

AN957

The MC1374 was designed for use in applications where
separate audio and composite video signals are available,
which need converting to a high quality VHF television signal.
It's ideally suited as an output device for subscription TV
decoders, video disk and video tape players. (12pp)
AN879

*Indicates New Document

Equalization of DTMF Signals Using
the MC34014

This application note will describe how to obtain
equalization (line length compensation) of the DTMF dialing
tones using the MC34014 speech network. (2pp)

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
15-3

Applications and Product Literature (continued)
AN968

A Digital Voice/Data Telephone Set

This design provides standard analog telephone functions
while simultaneously transmitting 9600 baud asynchronous
data. It is based on Motorola's MC145422/26 UDLT family of
voice/data ICs which provide 80 kbps full-duplex synchronous
communication over distances up to 2 km. The circuit includes
a Codec/filter, Data Set Interface and pulse/tone dialer. (7pp)
AN976

A New High Performance Current Mode
Controller Teams Up with Current
Sensing Power MOSFETs

A new current mode control IC that interfaces directly with
current sensing power MOSFETs is described. Its second
generation architecture is shown to provide a variety of
advantages in current mode power supplies. The most
notable of these advantages is a "Iossless" current sensing
capability that is provided when used with current sensing
MOSFETs. The discussion includes subtle factors to watch
outlor in practical designs, and an applications example. (8pp)
AN980

VHF Narrowband FM Receiver Design
Using the MC3362 and the MC3363 Dual
Conversion Receivers

The MC3362 and MC3363 narrowband FM dual conversion
receivers feature excellent VHF performance with low power
drain, making them ideal for cordless telephones, narrowband
voice and data receivers and RF security devices. This note
provides a detailed description of the operation of the two
devices, plus circuits and descriptions for four applications: a
Single Channel VHF FM Narrowband Receiver; a Ten
Channel Frequency Synthesized Cordless Telephone
Receiver; a 256 Channel Frequency Synthesized Two-Meter
Amateur Band Receiver; and a Single Chip Weather Band
Receiver. (14pp)
AN983

A Simplified Power Supply Design Using
the TL494 Control Circuit

This application note describes the operation and
characteristics of the TL494 Switchmode™ Voltage Regulator
and shows its application of a 400 W offline power supply.
The TL494 is a fixed-frequency pulse width modulation
control circuit, incorporating the primary building blocks
required for the control of a switching power supply. (5pp)

line-powered circuit, line-powered circuit with booster for long
lines, and external supply-powered. Includes glossary of
telephone terms. (18pp)
AN1003

A Handsfree Featurephone Design
Using the MC34114 Speech Network
and the MC34018 Speakerphone ICs

A comprehensive application note which develops a full
featurephone circuit using the MC34114 Speech Network, the
MC34018 Speakerphone IC and the MC145412 Dialer.
Functions include 10 number memory pulse/tone dialer, tone
ringer, mike mute and line length compensation for both
handset and speakerphone operation. Options include

A Featurephone Design, with Tone
Ringer and Dialer, Using the MC34118
Speakerphone IC

This application note describes how to add a handset, dialer
and tone ringer to the MC34118 speakerphone circuit.
Although anyone of several speech networks could be used
as an interface between the MC34118 and the phone line this
application note covers the case where simplicity and low cost
are paramount. Two circuits are developed in this discussion:
line-powered and supply-powered versions. (13pp)
AN1004

A Handsfree Featurephone Design
Using the MC34114 Speech Network
and the MC34118 Speakerphone ICs

Complete designs for a featurephone providing 10 number
memory, pulse or tone dialling, tone ringer, microphone
muting, and line length compensation for both handset and
speakerphone operation. Includes line-powered, linepowered plus long-line booster, and supply-powered
versions. The MC34114 interfaces with tip and ring and
provides 2-to-4 wire conversion. (18pp)
AN1006

Linearize the Volume Control of the
MC34118 Speakerphone

A single resistor added 10 the volume control potentiometer
in an MC34118 speakerphone application will almost perfectly
linearize the control law. (1 pp)
AN1016

Infrared Sensing and Data Transmission
Fundamentals

Many applications need electrical isolation, remote control
or position sensing. Infrared light provides an excellent
solution due to its low cost, ease of use, availability of
components, and freedom from the licensing and interference
concerns of RF techniques. This note is a brief but informative
reference on the design principles for IR systems, including a
selection of receiver circuits. (6pp)
AN1019

AN1002

*1 ndicates New Document

NTSC Decoding USing the TDA3330, with
Emphasis on Cable In/Cable Out Operation

The TDA3330 is a Composite Video to RGB Color Decoder
originally intended for PAL and NTSC color TV receivers and
monitors - so its data sheet concentrates on picture tube
drive. This practical application note supplements the data
sheet by providing circuits for video cable drive as used in
video processing, frame store and other specialized
applications, and expands on TDA3330 functional details.
Includes PCB artwork and layout of an evaluation board. (8pp)

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
15-4

Applications and Product Literature (continued)
AN1040

Mounting Considerations for Power
Semiconductors

AN1080

The operating environment is a vital factor in setting current
and power ratings of a semiconductor device. Reliability is
increased considerably for relatively small reductions in
junction temperature. Faulty mounting not only increases the
thermal gradient between the device and its heatsink, but can
also cause mechanical damage. This comprehensive note
shows correct and incorrect methods of mounting all types of
discrete packages, and discusses methods of thermal system
evaluation. (20pp)
AN1044

The MC1378 provides an interface between a remote
composite color video source and local RGB. On-chip circuitry
can lock a local computer to the remote source, switching
between local and remote signals to generate composite
video overlays. This detailed note describes local and remote
operation; picture-in-picture applications and the design of
test fixtures to help system development. Printed circuit
artwork for an evaluation board is provided. The NTSC/PAL
color encoder is similar to the MCI3??, discussed in detail in
AN932. (13pp)
AN1046

Three Piece Solution for Brushless Motor
Control Design (Rev. 1)

Until recently, the design of compact but comprehensive
circuits taking full advantage of the unique attributes of
brush less DC motors has been difficult, while available power
transistors have not always performed as well as is necessary
for the application. This high-performance three-chip solution
couples the rugged MPM3003 three phase MOSFET bridge
(in a 12-pin power package) with the MC33035 Brushless DC
Motor Adapter. Design is simplified, board area reduced. Full
circuit, parts list, and discussion of practical considerations.
(10pp)
AN1077

Adding Digital Volume Control To
Speakerphone Circuits

Describes how to control speakerphone volume from UP
and DOWN switches in place of the more usual potentiometer.
Includes a fully annotated circuit using only three standard
CMOS ICs and no critical components. (4pp)

New Components Simplify Brush DC
Motor Drives

A variety of new components simplify the design of brush
motor drives. One is a brush less motor control IC which is
easily adapted to brush motors. Others include multiple Power
MOSFETs in H-Bridge configuration, a new MOS turn-off
device, and gain-stable opto level shifters. Several circuits
illustrate how the new devices can be used in practical motor
drives, in particular to control speed in both directions and
operate from a Single power supply. (6pp)

Minimize the "pop" in the MC34119
Low Power Audio Amplifier

Sometimes a "pop" is heard in the loudspeaker when the
MC34119 audio amplifier is re-enabled. There are several
possible causes, but this note offers a simple and low cost
remedy to satisfy the most demanding user. (3pp)
AN1101

One-Horsepower Off-Line Brushless
Permanent Magnet Motor Drive

Brushless Permanent Magnet (BPM) motors (brush less DC
motors) using MOSFET inverters are common in low voltage,
variable speed applications such as disk drives. Higher
voltage off-line applications can also use the same
technology, but there have been problems in designing a
reliable, low cost high side driver and understanding the more
subtle effects of diode snap and PCB layout. This
one-horsepower off-line BPM motor drive board uses
opto-isolators and a special MOSFET turn-off IC for level
translation. Includes PCB artwork and parts list, and a
discussion of the theory. (1 Opp)
AN1108

DeSign Considerations for a Two Transistor,
Current Mode Forward Converter

This design for a 150 W, 150 kHz, two transistor, current
mode forward converter illustrates solutions for noise control,
feedback circuit analysis and magnetic component designtopics that often create the most problems for designers.
Improved Schottky rectifiers, power MOSFETs and
optocouplers- and their effects on switch mode power supply
design - are also considered. Includes circuit, analysis, parts
list and theoretical discussion. (11 pp)
AN1122

AN1078

External-Sync Power Supply with Universal
Input Voltage Range for Monitors

As the resolution of color monitors increases, the
performance and features of their power supplies becomes
more critical. EMI/RFI generated by switching power supplies
can adversely affect resolution if switching frequency is not
synchronized to horizontal scanning frequency. This 90 W
flyback switching supply demonstrates the use of new high
performance devices in a low cost design, and includes a new
universal input voltage adapter. (20pp)
AN1081

The MC1378- A Monolithic Composite
Video Synchronizer

'Indicates New Document

Running the MC44802A PLL Circuit

The MC44802A provides the Phase-Lacked-Loop (PLL)
portion of a tuning circuit intended for TV, FM radio and set-top
converter applications up to 1.3 GHz; a complete tuning circuit
is formed by adding a Voltage Controlled Oscillator (VCO) and
mixer. The data sheet recommends use of an MCU for sending
the control bytes that set the tuning frequency. This note
describes a serial (12C) interface with an MC68HCll E9 in a
tuner design - the information is sufficiently general to allow
almost any MCU to be used. Includes M68HCll program
listing. (12pp)

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
15-5

Applications and Product Literature (continued)
*AN1126

Evaluation Systems for Remote Control
Devices on an Infrared Link

The availability at low cost of remote control devices and
infrared communication links provides opportunities in many
application areas. This note gives information for constructing
the basic building blocks to evaluate both IR links and the most
popular remote control devices. Schematics and single-side
PCB layouts are presented that should enable the designer
quickly to put together a basic control link and evaluate its
suitability for a given application in terms of data rate, effective
distance, error rate and cost. Sources for special parts are also
given. (10pp)
AN1203

A Software Method for Decoding the Output
from the MC144971MC3373 Combination

Infrared communication is now widely used as a simple and
effective means of remote control over short distances. A
variety of encoding methods is used, including the biphase
scheme implemented by the MC14497, a complete building
block for IR data transmission. The MC3373 is a companion
receiver chip to the MC14497, providing front-end processing
to interface a photo detector to a TTL level. This note
describes the decoding of the data at the output of the
MC3373, along with software listings for the MC68HC11 and
the MC68HC05. (5pp)
AN1300

Interfacing Microcomputers to Fractional
Horsepower Motors

In fractional horsepower motion control systems, command
signals are usually now generated by a microprocessor or
digital signal processor, while power is applied with MOSFETs.
The interface between the two can still present difficulties; for
small motors it will be, typically, 5.0 V logic to complementary
P-ChanneI/N-Channel MOSFET H-bridges. A number of
factors need to be considered, including diode snap, group
bounce, noise suppression and locking out invalid inputs. The
design discussed here is embodied in evaluation board
DEVB103. (8pp)
AN1301

Interfacing Analog Inputs to Fractional
Horsepower Motors

In many types of systems it is desirable to control motor
speed with an analog signal. Even in digital systems, it is often
cost effective to generate an analog signal from static speed
control bits or a lower frequency PWM signal than to use a
more expensive MCU capable of generating a 20 kHz+ PWM
signal directly. Although recent developments have simplified
analog input conversion and power MOSFET outputs, the
interface between signal processing circuits and power
outputs is still far from simple. This note discusses the issues
using the DEVB118 evaluation board as an example deSign.
(9pp)
AN1306

Thermal Distortion in Video Amplifiers

Thermal distortion is a problem in many high resolution
video amplifiers. It occurs when there are instantaneous
power changes in the transistor stages, and if the problem
remains uncompensated, this ieads to the visual effect known
as smearing. This note discusses what smearing is, what

*Indicates New Document

causes thermal distortion, how to measure it, and how to
compensate for it. (5pp)
*AN1307

A Simple Pressure Regulator Using
Semiconductor Pressure Transducers

Semiconductor pressure transducers offer an economical
means of achieving high reliability and performance in
pressure sensing applications. The completely integrated
MPX5100 (0 psi to 15 psi) series provides a temperature
compensated, high level linear output suitable for interfacing
directly with many linear control systems. This circuit
illustrates how the MPX5100 can be used with a simple
pressure feedback system based on the MC33033 Brushless
Motor Controller to establish pressure regulation. Includes
circuit diagram and PCB artwork. (7pp)
*AN1510

A Mode Indicator for the MC34118
Speakerphone Circuit

Within the MC34118 are two comparators driven by the level
detectors which are sensing the speech signals (see
MC34118/D Data Sheet, Figure 24). The comparators'
outputs drive the attenuator control block which sets the
operating mode. (2pp)
ANE424

50 W Current Mode Controlled Offline
Switch Mqde Power Supply Working
over 50% Duty Cycle using the UC3842A

Switch mode power supplies based on flyback architecture
and voltage-controlled PWM techniques are well established.
This note describes a way of improving their dynamic
characteristics using a Current Controlled PWM technique. A
dedicated bipolar IC, the UC3842A Off-Line Current Mode
PWM Controller, performs the current control, regulation and
safety features. Full analysis of transformer and other
components, plus discussion of the instability inherent in the
current control mode. (27pp)
ANHK02

Low Power FM Transmitter System
MC2831A

This application note provides information concerning the
MC2831 A, a one-chip low-power FM transmitter system
designed for FM communication equipment such as FM
transceivers, cordless telephones, remote control and RF
data link. (16pp)

Article Reprint Abstracts
AR301

Solid State Devices Ease Task of Designing
Brushless DC Motors

Brushless fractional-horsepower DC motors are gaining in
popularity over brush type motors. Their characteristics are
similar but they avoid the practical problems associated with
brushes. In the past control complexity has made them less
attractive, but dedicated control ICs like the MC33034, plus
current-sensing power MOSFETs, mean that much of the
control and protection electronics is available off the shelf.
(EON, 3 September 1987) (7pp)

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
15-6

Applications and Product literature (continued)
AR323

Managing Heat Dissipation in DPAK
Surface Mount Power Packages

EB124

Physically smaller than a lead-formed TO-220, the OPAK
was introduced to accommodate larger die than in previously
available SM packages like the SOT-89. But larger die implies
increased heat dissipation. New board materials and good
circuit design ensure that OPAK Power MOSFETs can readily
switch at their full pulse current ratings.
(Powertechnics, December 1988) (4pp)

The Low Forward Voltage Schottky

As feature sizes are scaled down in very high density
circuits, it wiil be necessary for the standard power supply
voltage to be reduced from 5.0 V to 3.3 V within the next few
years to avoid degrading performance in the new devices.
Also, greater power supply efficiency will be required if the
power supply is nollo occupy a disproportionate amount of the
total system volume. Since the major power loss in switching
power supplies is in the output rectification circuits, more
efficient rectifiers are needed. Schottky rectifier technology
shows the greatest potential. (Powertechnics, May 1990)
(3pp)

Engineering Bulletin Abstracts
*EB27A

Includes circuit, PCB artwork and layout for a 300 W
push-pull linear amplifier based on two MRF422s, designed to
operate over the 2.0 MHz to 30 MHz band. An MC1723 voltage
regulator is used as a bias supply. (4pp)
EB85A

EB128

The Application of a Telephone Tone
Ringer as a Ring Detector

The MOSFET Turn-Off Device - A New
Circuit Building Block

Technical developments have lead to a variety of discrete
devices using circuit integration to reduce system cost and
board space, while offering some performance improvement
over conventional solutions. The first of these new
components -dubbed SMALLBLOCKTM - is a building block
that simplifies and reduces the component cost of an active
gate-turn-off network for current-source driven MOSFETs. It is
available in TO-92, SOT-23 and SOT-223 packages. (8pp)

Product literature
OL136/0
HB206

SG56/0

Telephone ringers are driven by high voltage, low frequency
AC signals which are superimposed on the 48 V DC Tip-Ring
feed voltage. An electronic ring detector must sense the
presence of an AC Signal on the line and produce a
dielectrically isolated logic level to the system processor. (2pp)

SG73/0
SG79/0

SG96/0
EB123

Simple, Low-Cost Motor Controller

This low cost DC motor controller uses the cost effective
MPM3002 SENSEFET-based H-Bridge, plus the MC34060
PWM IC. It is capable of driving a 1/3 HP, permanent magnet
90 V DC motor, and includes dynamic braking and Soft-Start.
(2pp)

Full-Bridge Switching Power Supplies

A useful selection chart presenting preferred Bipolar,
power MOSFET, Rectifier and Control devices for various
areas of typical 500 W to 1000 W full-bridge switching power
supplies. (lp)
EB112

Ultra-Rapid Nickel-Cadmium Battery
Charger

Charging NiCad batteries is a particular problem when their
voltage exceeds the voltage of the available charging source.
The ultra-fast charger presented here is capable of charging
eight to twelve 1.5 V batteries at 1.2 A to 1.8 A in 30 to 45
minutes from a 10 V to 14 V source - a feat made possible by
the use of new sintered electrode technology by battery
manufacturers. Includes PC artwork and layout. (3pp)

EB142

Get 300 Watts EPE Linear Across 2 to
30 MHz from this Push-Pull Amplifier

MOSFETs Compete with Bipolars in Flyback
Power Supplies

Power MOSFETs with 400 V to 500 V breakdown ratings are
widely used in multiple-transistor off-line power supplies. Now
they can be used in flyback supplies as well, as breakdown
voltages are extended to 1000 V. A discussion of the
advantages and disadvantages, illustrated with typical 100 W
MOSFET and Bipolar designs. (2pp)
EB126

AR340

'Indicates New Document

A Simple Brush Type DC Motor Controller

A simple and cost effective way to drive brush type DC
motors is to use power MOSFETs with a Brushless DC Motor
Control IC. The low cost MC33033 controller and integrated
8.0 All 00 V MPM3002 H-bridge combine to give a minimum
parts count brush motor drive. (2pp)

SG98/0
SG127/0
SG368/0
SG41 0/0

Telecommunications Device Data
Linear & Switch mode Voltage Regulator
Handbook (See Back of Chapter 3)
(Out of Print)
TMOS Power MOSFET Selector Guide /
Cross Reference
Master Selection Guide
SWITCHMODE - A Designer's Guide for
Switching Power Supply Circuits and
Components
Linear/Interface ICs Selector Guide
Selector Guide and Cross Reference
Linear Telecom Cross Reference
Surface Mount Products Selector Guide
Video Capture Chip Sets Selector Guide
(See Front of Chapter 9)
Applications & Product Literature Selector
Guide / Cross Reference

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

15-7

MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA

15-8
Source Exif Data:
File Type : PDF File Type Extension : pdf MIME Type : application/pdf PDF Version : 1.3 Linearized : No XMP Toolkit : Adobe XMP Core 4.2.1-c043 52.372728, 2009/01/18-15:56:37 Create Date : 2011:07:13 19:35:17-08:00 Modify Date : 2011:07:14 06:54:38-07:00 Metadata Date : 2011:07:14 06:54:38-07:00 Producer : Adobe Acrobat 9.45 Paper Capture Plug-in Format : application/pdf Document ID : uuid:1a8a4f47-8716-4a69-84c4-5f7a95d2849c Instance ID : uuid:fcd6e8ca-843b-43d0-bb41-d8e5060c99a1 Page Layout : SinglePage Page Mode : UseNone Page Count : 1046
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1993_Motorola_Linear_Interface_ICs_Vol_2 1993 Motorola Linear Interface ICs Vol 2

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