1993_Real_Time_Clock_Handbook 1993 Real Time Clock Handbook
User Manual: 1993_Real_Time_Clock_Handbook
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400090
~ National
~ Semiconductor
REAL TIME CLOCK
HANDBOOK
1993 Edition
3-Volt Low Voltage Real Time Clocks
Real Time Clocks and
Timer Clock Peripherals
Application Notes
Appendices/Physical Dimensions
III
fJI
•
II
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NATIONAL'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR
SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
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or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions
for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.
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device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
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TWX (910) 339-9240
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied, and National reserves the right, at any time
without notice, to change said Circuitry or specifications.
Table of Contents
Alphanumeric Index. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Section 1 3-Volt Low Voltage Real Time Clocks
LV8571A Low Voltage Timer Clock Peripheral (TCP) ............... .............. .
LV8572A Low Voltage Real Time Clock (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LV8573A Low Voltage Real Time Clock (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Section 2 Real Time Clocks
TCP/RTC Family Comparisons.................................................
DP8570A Timer Clock Peripheral (TCP) .........................................
DP8571A Timer Clock Peripheral (TCP) .........................................
DP8572A/DP8572AM Real Time Clock (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DP8573A Real Time Clock (RTC) ...............................................
MM58274C-12 Microprocessor Compatible Real Time Clock. . . . . . . . . . . . . . . . . . . . . . .
MM58274C MicroprocessorCompatible Real Time Clock......................... .
MM58174A Microprocessor Compatible Real Time Clock......................... .
MM58167B Microprocessor Real Time Clock.................................... .
NS32FX211 Microprocessor Compatible Real Time Clock........................ .
Section 3 Application Notes
AN-353 MM58167B Real Time Clock Design Guide...............................
AN-359 The MM58174A Real Time Clock in a Battery Backed-Up Design Provides
Reliable Clock and Calendar Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AN-365 The MM58274C Adds Reliable Real-Time Keeping to Any Microprocessor
System ...................................................................
AN-588 Calibration of the DP8570A Family ......................................
AN-589 DP8570A Timer Clock Peripheral Test Mode and Test Considerations....... .
AN-595 Flexible Timers on the DP8570A and DP8571 A ...........................
AB-43 Typical DP8570A Interface to the IBM PC/XT for the Purpose of Engineering
Evaluation. . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AN-443 Add a Hardware Clock/Calendar to Your IBM PC......................... .
AN-893 Using External Oscillators for the DP857X Real Time Clocks with the Battery
Backed Mode Selected .....................................................
AN-894 DP8570A Experiments to Test the Low Battery Bit or Generate a Periodic
, Interrupt ...................... " . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AN-895 Change the Battery on any DP857X Family Member Using Software without
Losing Time................ .............................................. .
Section 4 Physical Dimensionsl Appendices
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bookshelf
Distributors
iii
iv
1-3
1-26
1-44
2-3
2-5
2-28
2-51
2-71
2-86
2-99
2-112
2-119
2-128
3-3
3-20
3-29
3-45
3-50
3-54
3-60
3-62
3-83
3-86
3-95
4-3
Alpha-Numeric Index
AB-43 Typical DP8570A Interface to the IBM PC/XT for the Purpose of Engineering
Evaluation ............................................................ '.' ............... 3-60
AN-353 MM58167B Real Time Clock Design Guide ............................................ 3-3
AN-359 The MM58174A Real Time Clock in a Battery Backed-Up Design Provides Reliable
Clock and Calendar Functions ........................................................... 3-20
AN-365 The MM58274C Adds Reliable Real-Time Keeping to Any Microprocessor System ......... 3-29
AN-443 Add a Hardware Clock/Calendar to Your IBM PC ...................................... 3-62
AN-588 Calibration of the DP8570A Family .................................................. 3-45
AN-589 DP8570A Timer Clock Peripheral Test Mode and Test Considerations .................... 3-50
AN-595 Flexible Timers on the DP8570A and DP8571 A ....................................... 3-54
. AN-893 Using External Oscillators for the DP857X Real Time Clocks with the Battery Backed
Mode Selected .............. '.' ......................................................... 3-83
AN-894 DP8570A Experiments to Test the Low Battery Bit or Generate a Periodic Interrupt ........ 3-86
AN-895 Change the Battery on any DP857X Family Member Using Software without Losing
Time .................................................................................. 3-95
DP8570A Timer Clock Peripheral (TCP) ...................................................... 2-5
DP8571A Timer Clock Peripheral (TCP) ..................................................... 2-28
DP8572A Real Time Clock (RTC) ........................................................... 2-51
DP8572AM Real Time Clock (RTC) .......................................................... 2-51
DP8573A Real Time Clock (RTC) ........................................................... 2-71
LV8571 A Low Voltage Timer Clock Peripheral (TCP) ........................................... 1-3
LV8572A Low Voltage Real Time Clock (RTC) ................................................ 1-26
LV8573A Low Voltage Real Time Clock (RTC) ................................................ 1-44
MM58167B Microprocessor Real Time Clock ............................................... 2-119
MM58174A Microprocessor Compatible Real Time Clock ..................................... 2-112
MM58274C Microprocessor Compatible Real Time Clock ...................................... 2-99
MM58274C-12 Microprocessor Compatible Real Time Clock ................................... 2-86
NS32FX211 Microprocessor Compatible Real Time Clock .................................... 2-128
iv
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Product Status Definitions
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Definition of Terms
Data Sheet Identification
Advance Information
Formative or
In Design
This data sheet contains the design specifications for product
development. Specifications may change in any manner without notice.
Preliminary
First
Production
This data sheet contains preliminary data, and supplementary data will
be published at a later date. National Semiconductor Corporation
reserves the right to make changes at any time without notice in order
to improve design and supply the best possible product.
No
Identification
Noted
Full
Production
This data sheet contains final specifications. National Semiconductor
Corporation reserves the right to make changes at any time without
notice in order to improve design and supply the best possible product.
Obsolete
Not In Production
This data sheet contains specifications on a product that has been
discontinued by National Semiconductor Corporation. The data sheet
is printed for reference information only.
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Definition
Product Status
National Semiconductor Corporation reserves the right to make changes without further notice to any products herein to
improve reliability, function or design. National does not assume any liability arising out of the application or use of any product
or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others.
v
Section 1
3-Volt Low Voltage
Real Time Clocks
III
Section 1 Contents
LV8571 A Low Voltage Timer Clock Peripheral (TCP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LV8572A Low Voltage Real Time Clock (RTC) .........................................
LV8573A Low Voltage Real Time Clock (RTC) .........................................
1·2
1-3
1-26
1-44
~National
U
PRELIMINARY
Semiconductor
LV8571A Low Voltage Timer Clock Peripheral (TCP)
General Description
The LV8571A is intended for use in microprocessor based
systems where information is required for multi-tasking, data
logging or general time of day/date information. This device
is implemented in low voltage silicon gate microCMOS technology to provide low standby power in battery back-up environments. The circuit's architecture is such that it looks
like a contiguous block of memory or I/O ports. The address
space is organized as 2 software selectable pages of 32
bytes. This includes the Control Registers, the Clock Counters, the Alarm Compare RAM, the Timers and their data
RAM, and the Time Save RAM. Any of the RAM locations
that are not being used for their intended purpose may be
used as general purpose CMOS RAM.
interrupt, and lock out the J.Lp interface. The time power fails
may be logged into RAM automatically when Vss > Vee.
Additionally, two supply pins are provided. When Vss
> Vee, internal circuitry will automatically switch from the
main supply to the battery supply. Status bits are provided
to indicate initial application of battery power, system power,
and low battery detect.
(Continued)
Features
• 3.3V ± 10% supply
• Full function real time clock/calendar
- 12/24 hour mode timekeeping
- Day of week and day of years counters
- Four selectable oscillator frequencies
- Parallel resonant oscillator
• Two 16-bit timers
- 10 MHz external clock frequency
- Programmable multi-function output
- Flexible re-trigger facilities
• Power fail features
- Internal power supply switch to external battery
- Power Supply Bus glitch protection
- Automatic log of time into RAM at power failure
• On-chip interrupt structure
- Periodic, alarm, timer and power fail interrupts
• Up to 44 bytes of CMOS RAM
• INTR/MFO pins programmable High/Low and push-pull
or open drain
Time and date are maintained from 1/100 of a second to
year and leap year in a BCD format, 12 or 24 hour modes.
Day of week, day of month and day of year counters are
provided. Time is controlled by an on-chip crystal oscillator
requiring only the addition of the crystal and two capacitors.
The choice of crystal frequency is program selectable.
Two independent multifunction 10 MHz 16-bit timers are
provided. These timers operate in four modes. Each has its
own prescaler and can select any of 7 possible clock inputs.
Thus, by programming the input clocks and the timer counter values a very wide range of timing durations can be
achieved. The range is from about 400 ns (4.915 MHz oscillator) to 65,535 seconds (18 hrs., 12 min.).
Power failure logic and control functions have been integrated on chip. This logic is used by the TCP to issue a power fail
Block Diagram
osc
osc
out
in
III
INTR
FIGURE 1
1-3
IolFO
TL/F/11416-1
c:r:
,...
......
I.l)
ClC)
>
..J
Absolute Maximum Ratings (Notes 1 & 2)
If Military/Aerospace specified devices are required,
Operation Conditions
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (Vee> (Note 3)
Supply Voltage (Vss) (Note 3)
DC Input or Output Voltage
(VIN, VOUT)
Operation Temperature (TA)
Electr-Static Discharge Rating
Typical Values
OJA DIP
-0.5Vto +7.0V
Supply Voltage (Vee>
DC Input Voltage (VIN)
-0.5V to Vee + 0.5V
DC Output Voltage (VOUT)
Storage Temperature Range
-0.5V to Vee + 0.5V
- 65°C to + 150°C
Power Dissipation (PO)
500mW
Lead Temperature (Soldering, 10 sec.)
260°C
OJA PLCC
Min
Max
Unit
3.0
2.2
3.6
Vee- O.4
V
V
0.0
Vee
V
-40
+85
1
°C
kV
Board
Socket
Board
Socket
59°C/W
65°C/W
77°C/W
85°C/W
DC Electrical Characteristics
Vee
= 3.3V ±10%, Vss = 2.5V, VPFAll > VIH, Cl = 100 pF (unless otherwise specified)
Symbol
Conditions
Min
Max
Units
VIH
High Level Input Voltage
(Note 4)
Any Inputs Except OSC IN,
OSC IN with External Clock
2.0
Vss -0.2
Vee + 0.3
V
V
Vil
Low Level Input Voltage
All Inputs Except OSC IN
OSC IN with External Clock
-0.3
-0.3
0.8
0.2
V
V
VOH
High Level Output Voltage
(Excluding OSC OUT)
lOUT = - 20 p.A
lOUT = - 2.0 mA
VOL
Low Level Output Voltage
(Excluding OSC OUT)
lOUT = 20 p.A
lOUT = 2.0mA
liN
Input Current (Except OSC IN)
VIN
loz
Output TRI-STATE® Current
VOUT
IlKG
Output High Leakage Current
MFa, INTR Pins
Outputs Open Drain
Icc
Parameter
Quiescent Supply Current
(Note 7)
= VeeorGND
= Vee or GND
VOUT = Vee or GND
Fose = 32.768 kHz
VIN = Vee or GND (Note 5)
VIN = VeeorGND(Note6)
VIN = VIH or Vil (Note 6)
Fose
Iss
0.2
0.3
V
V
±0.7
p.A
±1
p.A
±1
p.A
220
700
8
p.A
p.A
mA
6
8
mA
mA
60
6
p.A
mA
8
400
p.A
p.A
= 4.194304 MHz or
4.9152 MHz
VIN = VeeorGND (Note 6)
VIN = VIH or Vil (Note 6)
Icc
V
V
Vee -0.2
2.4
Quiescent Supply Current
(Single Supply Mode)
(Note 7)
Vss = GND
VIN = Vee or GND
Fose = 32.768 kHz
Fose ;". 4.9152 MHz or
4.194304 MHz
Standby Mode Battery
Supply Current
(Note 8)
Vee = GND
OSC OUT = open circuit,
other pins = GND
Fose = 32.768 kHz
Fose = 4.9152 MHz or
4.194304 MHz
2.2V s; Vss s; 2.6V
other pins at GND
0.8
p.A
Vee = GND, Vss = 2.6V
-0.8
Vee = 3.6V, Vss = 2.2V
p.A
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: For Fosc = 4.194304 or 4.9152 MHz, VBB minimum = 2.BV.ln battery backed mode. VBB ::;: Vcc -0.4V. Single Supply Mode: Data retention voltage is
2.2V min. In single Supply Mode (Power connected to Vcc pin) 3.0V ::;: VCC ::;: 3.6V.
Note 4: This parameter (VIH) is not tested on all pins at the same time.
Note 5: This speCification tests Icc with all power fail circuitry disabled, by setting 07 of Interrupt Control Register 1 to o.
Note 6: This specification tests Icc with all power fail circuitry enabled, by setting 07 of Interrupt Control Register 1 to 1.
Note 7: This specification is tested with both the timers and asc IN driven by a signal generator. Contents of the Test Register = OO(H), the MFa pin is not
configured as buffered oscillator out and MFa, INTR, are configured as open drain.
Note 8: This specification is tested with both the timers off, and only asc IN is driven by a signal generator. Contents of the Test Register = OOCH) and the MFa
pin is not configured as buffered oscillator out.
ISlK
Battery, Supply Leakage
1-4
r-
<
AC Electrical Characteristics
00
U1
Vcc = 3.3V ± 10%, Vss = 2.5V, VPm[ > VIH, CL = 100 pF (unless otherwise specified)
Symbol
I
I
Parameter
Min
I
I
Max
Units
.......
.....
>
READ TIMING
tAR
Address Valid Prior to Read Strobe
10
ns
tRW
Read Strobe Width (Note 9)
100
ns
tco
Chip Select to Data Valid Time
tRAH
Address Hold after Read (Note 10)
tRo
Read Strobe to Valid Data
100
ns
90
ns
ns
2
toz
Read or Chip Select to TRI-STATE
tRCH
Chip Select Hold after Read Strobe (Note 10)
0
80
ns
ns
tos
Minimum Inactive Time between Read or Write Accesses
70
ns
tAW
Address Valid before Write Strobe
10
ns
tWAH
Address Hold after Write Strobe (Note 10)
2
ns
tcw
Chip Select to End of Write Strobe
110
ns
tww
Write Strobe Width (Note 11)
100
ns
tow
Data Valid to End of Write Strobe
70
ns
tWOH
Data Hold after Write Strobe (Note 10)
2
ns
tWCH
Chip Select Hold after Write Strobe (Note 10)
0
ns
WRITE TIMING
INTERRUPT TIMING
tROLL
Clock rollover to INTR out is typically 20 ,..,S
Note 9: Read Strobe width as used in the read timing table is defined as the period when both chip select and read inputs are low. Hence read commences when
both signals are low and terminates when either signal returns high.
Note 10: Hold time is guaranteed by design but not production tested. This limit is not used to calculate outgoing quality levels.
Note 11: Write Strobe width as used in the write timing table is defined as the period when both chip select and write inputs are low. Hence write commences when
both signals are low and terminates when either signal returns high.
AC Test Conditions
Input Pulse Levels
Input Rise and Fall Times
Input and Output
Reference Levels
TRI-STATE Reference
Levels (Note 13)
GNDt03.0V
6 ns (10%-90%)
vee
1.3V
'"r"
I
Active High + 0.5V
Active Low - 0.5V
Note 12: CL = 100 pF, includes jig and scope capacitance.
Note 13: SI = Vee for active low to high impedance measurements.
SI = GND for active high to high impedance measurements.
S1 = open for all other timing measurements.
Capacitance (TA =
Symbol
Input 0 - -
~
25°C, f = 1 MHz)
Parameter
(Note 14)
Typ
Units
CIN
Input Capacitance
5
pF
COUT
Output Capacitance
7
pF
Device
Under
Test
Note 14: This parameter is not 100% tested.
Note 15: Output rise and fall times 25 ns max (10%-90%) with 100 pF load.
1-5
~
(Note 13)
_0
~
:
.
*
I\. =1 kG
Output
-- <;,
~
(Note 12)
TL/F/11416-2
•
..J
Read Timing Diagram
AO-4
-tR
~CH
RD
- - - - - " \ I " " " f - - - - - - ~W-----+i.r--"""'\I
DATA
Valid Data
TL/F/11416-3
Write Timing Diagram
AO-4
~-----~w----------~~
~----------tww----------~
---~--,I
IJ------~I
t:=tow
DATA
-------------~I(
Valid Data
TL/F/11416-4
1·6
r
General Description
PFAIL (Input): In battery backed mode, this pin can have a
digital signal applied to it via some external power detection
logic. When PFAIL = logic 0 the TCP goes into a lockout
mode, in a minimum of 30 fLs or a maximum of 63 fLs unless
lockout delay is programmed. In the single power supply
mode, this pin is not useable as an input and should be tied
to Vee. Refer to section on Power Fail Functional Description.
(Continued)
The LV8571 A's interrupt structure provides four basic types
of interrupts: Periodic, Alarm/Compare, Timer, and Power
Fail. Interrupt mask and status registers enable the masking
and easy determination of each interrupt.
One dedicated general purpose interrupt output is prOvided.
A second interrupt output is available on the Multiple Function Output (MFO) pin. Each of these may be selected to
generate an interrupt from any source. Additionally, the
MFO pin may be programmed to be either as oscillator output or Timer a's output.
<
co
(J1
......
.....
>
VBB (Battery Power Pin): This pin is connected to a backup power supply. This power supply is switched to the internal circuitry when the Vee becomes lower than Vss. Utilizing this pin eliminates the need for external logic to switch in
and out the back-up power supply. If this feature is not to be
used then this pin must be tied to ground, the TCP programmed for single power supply only, and power applied to
the Vee pin.
Pin Description
CS, RD, WR (Inputs): These pins interface to fLP control
lines. The CS pin is an active low enable for the read and
write operations. Read and Write pins are also active low
and enable reading or writing to the TCP. All three pins are
disabled when power failure is detected. However, if a read
or write is in progress at this time, it will be allowed to complete its cycle.
Vee: This is the main system power pin.
GND: This is the common ground power pin for both Vss
and Vee.
Connection Diagram
AO-A4 (Inputs): These 5 pins are for register selection.
They individually control which location is to be accessed.
These inputs are disabled when power failure is detected.
Dual-In-Line
OSC IN (Input): OSC OUT (Output): These two pins are
used to connect the crystal to the internal parallel resonant
oscillator. The oscillator is always running when power is
applied to Vss and Vee, and the correct crystal select bits in
the Real Time Mode Register have been set.
CS-l
iID-
\..J
iVR-3
MFO (Output): The multi-function output can be used as a
second interrupt output for interrupting the fLP. This pin can
also provide an output for the oscillator or the internal Timer
O. The MFO output can be programmed active high or low,
open drain or push-pull. If in battery backed mode and a
pull-up resistor is· attached, it should be connected to a voltage no greater than Vss. This pin is configured open drain
during battery operation (Vss > VeC>.
221-07
AO- 4
211-06
Al- 5
20 .... 05
A2- 6
191-04
A3- 7
18 .... 03
A4- 8
17 .... 02
16 .... 01
VBB - 9
OSC IN- 10
INTR (Output): The interrupt output is used to interrupt the
processor when a timing event or power fail has occurred
and the respective interrupt has been enabled. The INTR
output can be programmed active high or low, push-pull or
open drain. If in battery backed mode and a pull-up resistor
is attached, it should be connected to a voltage no greater
than Vss. This pin is configured open drain during battery
operation (Vss > VeC>.
24 ~Vcc
23 I- prAll
2
15 .... 00
OSC OUT- 11
14 .... INTR
GNO- 12
13 .... ~ro
TL/F/11416-5
Top View
Order Number LV8571AN
See NS Package Number N24C
00-07 (Input/Output): These 8 bidirectional pins connect
to the host fLP'S data bus and are used to read from and
write to the TCP. When the PFAIL pin goes low and a write
is not in progress, these pins are at TRI-STATE.
III
1-7
Functional Description
The memory map of the· TCP is shown in the memory addressing table. The memory map consists of two 31 byte
pages with a main status register that is common to both
pages. A control bit in the Main Status Register is used to
select either page. Figure 2 shows the basic concept.
Page 0 contains all the clock timer functions, while page 1
has scratch pad RAM. The control registers are split into
two separate blocks to allow page 1 to be used entirely as
scratch pad RAM. Again a control bit in the Main Status
Register is used to select either control register block.
The LV8571 A contains a fast access real time clock, two 10
.MHz 16-bit timers, interrupt control logic, power fail detect
logic, and CMOS RAM. All functions of the TCP are controlled by a set of nine registers. A simplified block diagram
that shows the major functional blocks is given in Figure 1.
The blocks are described in the following sections:
1. Real Time Clock
2. Oscillator Prescaler
3. Interrupt Logic
4. Power Failure Logic
5. Additional Supply Management
6. Timers
Page Select
=0
Page Select = 1
1F
RAM/TEST Register
1E
RAM
IF
RAM
10
Months Time Save RAM
IE
RAM
lC
Day of Month Time Save RAM
10
RAM
lB
Hours Time Save RAM
lC
RAM
lA
Minutes Time Save RAM
1B
RAM
19
Seconds Time Save RAM
lA
RAM
18
Day of Week Compare RAM
19
RAM
17
Months Compare RAM
18
RAM
16
Day of Month Compare RAM
17
RAM
15
Hours Compare RAM
16
RAM
14
Minutes Compare RAM
15
RAM
13
Seconds Compare RAM
14
RAM
12
Timer 1 MSB
13
RAM
11
Timer 1 LSB
12
RAM
10
Timer 0 MSB
1
RAM
OF
Timer 0 LSB
10
RAM
OE
Day of Week Clock Counter
OF
RAM
00
100's Julian Clock Counter
OE
RAM
OC
Units Julian Clock Counter
00
RAM
OB
Years Clock Counter
OC
RAM
OA
Months Clock Counter
OB
RAM
09
Day of Month Clock Counter
OA
RAM
08
Hours Clock Counter
09
RAM
07
Minutes Clock Counter
08
RAM
06
Seconds Clock Counter
07
RAM
06
RAM
05
Y1DO Second
Counter
"
''';'''' 5.1",· 0 /
,.,;,'" 5.1.01 • I
Interrupt Routing Register
04
Interrupt Control Register 1
Periodic Flag Register
03
Interrupt Control Register 0
Timer 1 Control Register
02
Output Mode Register
g
05
RAM
04
RAM·
03
RAM
02
RAM
1
RAM
R.ea.I.'~im~e:.M.Od.e_,.g/
Timer 0 co.:..tr.OI.R.e..is.te.r• •O.l• •
00
I
-
Main Status Register
TL/F/11416-6
FIGURE 2. LV8571A Internal Memory Map
1-8
Functional Description
(Continued)
Save Enable bit (D7) of the Interrupt Routing Register, and
then to write a zero. Writing a one into this bit will enable the
clock contents to be duplicated in the Time Save RAM.
Changing the bit from a one to a zero will freeze and store
the contents of the clock in Time Save RAM. The time then
can be read without concern for clock rollover, since internal logic takes care of synchronization of the clock. Because only the bits used by the clock counters will be
latched, the Time Save RAM should be cleared prior to use
to ensure that random data stored in the unused bits do not
confuse the host microprocessor. This bit can also provide
time save at power .tailure, see the Additional Supply Management Functions section. With the Time Save Enable bit
at a logical 0, the Time Save RAM may be used as RAM if
the latched read function is not necessary.
INITIAL POWER-ON of BOTH Vee and Vee
VBB and Vee may be applied in any sequence. In order for
the power fail circuitry to function correctly, whenever power
is off, the Vee pin must see a path to ground through a
maximum of 1 Ma. The user should be aware that the control registers will contain random data. The first task to be
carried out in an initialization routine is to start the oscillator
by writing to the crystal select bits in the Real Time Mode
Register. If the LV8571A is configured for single supply
mode, an extra 50 I1-A may be consumed until the crystal
. select bits are programmed. The user should also ensure
that the TCP is not in test mode (see register descriptions).
REAL TIME CLOCK FUNCTIONAL DESCRIPTION
As shown in Figure 2, the clock has 10 bytes of counters,
which count from 1/100 of a second to years. Each counter
counts in BCD and is synchronously clocked. The count sequence of the individual byte counters within the clock is
shown later in Table VII. Note that the day of week, day of
month, day of year, and month counters all roll over to 1.
The hours counter in 12 hour mode rolls over to 1 and the
AM/PM bit toggles when the hours rolls over to 12
(AM = 0, PM = 1). The AM/PM bit is bit D7 in the hours
counter.
INITIALIZING AND WRITING TO THE
CALENDAR-CLOCK
Upon initial application of power to the Tep or when making
time corrections, the time must be written into the clock. To
correctly write the time to the counters, the clock would
normally be stopped by writing the Start/Stop bit in the Real
Time Mode Register to a zero. This stops the clock from
counting and disables the carry circuitry. When initializing
the clock's Real Time Mode Register, it is recommended
that first the various mode bits be written while maintaining
the Start/Stop bit reset, and then writing to the register a
second time with the Start/Stop bit set.
All other counters roll over to O. Also note that the day of
year counter is 12 bits long and occupies two addresses.
Upon initial application of power the counters will contain
random information.
The above method is useful when the entire clock is being
corrected. If one location is being updated the clock need
not be stopped since this will reset the prescaler, and time
will be lost. An ideal example of this is correcting the hours
for daylight savings time .. To write to the clock "on the fly"
the best method is to wait for the 1/100 of a second periodic interrupt. Then wait an additional 16 I1-s, and then write
the data to the clock.
READING THE CLOCK: VALIDATED READ
Since clocking of the counter occurs asynchronously to
reading of the counter, it is possible to read the counter
while it is being incremented (rollover). This may result in an
incorrect time reading. Thus to ensure a correct reading of
the entire contents of the clock (or that part of interest), it
must be read without a clock rollover occurring. In general
this can be done by checking a rollover bit. On this chip the
periodic interrupt status bits can serve this function. The
following program steps can be used to accomplish this.
PRESCALER/OSCILLATOR FUNCTIONAL
DESCRIPTION
Feeding the counter chain is a programmable prescaler
which divides the crystal oscillator frequency to 32 kHz and
further to 100 Hz for the counter chain (see Figure 3). The
crystal frequency that can be seiected are: 32 kHz, 32.768
kHz, 4.9152 MHz, and 4.194304 MHz.
1. Initialize program for reading clock.
2. Dummy read of periodic status bit to clear it.
3. Read counter bytes and store.
4. Read rollover bit, and test it.
Once 32 kHz is generated it feeds both timers and the
clock. The clock and timer prescalers can be independently
enabled by controlling the timer or clock Start/Stop bits.
5. If rollover occured go to 3.
6. If no rollover, done.
To detect the rollover, individual periodic status bits can be
polled. The periodic bit chosen should be equal to the highest frequency counter register to be read. That is if only
SECONDS through HOURS counters are read, then the
SECONDS periodic bit should be used.
From
Oscillator
READING THE CLOCK: INTERRUPT DRIVEN
Enabling the periodic interrupt mask bits cause interrupts
just as the clock rolls over. Enabling the desired update rate
and providing an interrupt service routine that executes in
less than 10 ms enables clock reading without checking for
a rollover.
Frequency
Select
III
"1H"--,...---;:==t::==::::;---,
READING THE CLOCK: LATCHED READ
TL/F/11416-7
Another method to read the clock that does not require
checking the rollover bit is to write a one into the Time
FIGURE 3. Programmable Clock Prescaler Block
1-9
..J
Functional Description (Continued)
The oscillator is programmed via the Real Time Mode Register to operate at various frequencies. The crystal oscillator
is designed to offer optimum performance at each frequency. Thus, at 32.768 kHz the oscillator is configured as a low
frequency and low power oscillator. At the higher frequencies the oscillator inverter is reconfigured. In addition to the
inverter, the oscillator feedback bias resistor is included on
chip, as shown in Figure 4. The oscillator input may be driven from an external source if desired. Refer to test mode
application note for details. The oscillator stability is enhanced through the use of an on chip regulated power supply.
The interrupts are enabled by writing a one to the appropriate bits in Interrupt Control Register 0 and/or 1. Any of the
interrupts can be routed to either the INTR pin or the MFO
pin, depending on how the Interrupt Routing register is programmed. This, for example, enables the user to dedicate
the MFO as a non-maskable, interrupt pin to the CPU for
power failure detection and enable all other interrupts to
appear on the INTR pin. The polarity for the active interrupt
can be programmed in the Output Mode Register for either
active high or low, and open drain or push pull outputs.
TABLE I. Registers that are Applicable
to Interrupt Control
The typical range of trimmer capacitor (as shown in Oscillator Circuit Diagram Figure 4, and in the typical application) at
the oscillator input pin is suggested only to allow accurate
tuning of the oscillator. This range is based on a typical
printed circuit board layout and may have to be changed
depending on the parasitic capacitance of the printed circuit
board or fixture being used. In all cases, the load capacitance specified by the crystal manufacturer (nominal value
11 pF for the 32.768 crystal) is what determines proper oscillation. This load capcitance is the series combination of
capacitance on each side of the crystal (with respect to
ground).
Register Name
Main Status Register
Periodic Flag Register
Interrupt Routing
Register
Interrupt Control
Register 0
Interrupt Control
Register 1
Output Mode
Register
Internal Components
v+
Pin
....-----fDt---.......
OSC OUT
Pin
TLlF/11416-8
32/32.768 kHz
4.194304 MHz
4.9152 MHz
47pF 2 pF-22 pF
68 pF o pF-80 pF
68pF 29 pF-49 pF
X
0
OOH
03H
0
0
04H
1
0
03H
1
0
04H
1
0
02H
These register bits will be set when their associated timing
events occur. Enabled Alarm or Timer interrupts that occur
will set its Main Status Register bit to a one. However, an
external interrupt will only be generated if the appropriate
Alarm or Timer interruptenable bits are set (see Figure 5).
FIGURE 4. Oscillator Circuit Diagram
Ct
X
0
Status for the interrupts are provided by the Main Status
Register and the Periodic Flag Register. Bits 01-05 of the
Main Status Register are the main interrupt bits.
External
Components
Co
Address
Note that the Interrupt Status Flag will only monitor the state
of the MFO output if it has been configured as an interrupt
output (see Output Mode Register description). This is'true,
regardless of the state of the Interrupt Routing Register.
Thus the Interrupt Status Flag provides a true reflection of
all conditions routed to the external pins.
XTAL
XTAL
Page
Select
The Interrupt Status Flag DO, in the Main Status Register,
indicates the state of INTR and MFO outputs. It is set when
either output becomes active and is cleared when all TCP
interrupts have been cleared and no further interrupts are
pending (Le., both INTR and MFO are returned to their inactive state). This flag enables the TCP to be rapidly/polled by
the JJ.P to determine the source of an interrupt in a wiredOR interrupt system.
To
Prescaler
OSC IN
Register
Select
ROUT
(Switched
Internally)
Disabling the periodic bits will mask the Main Status Register periodic bit, but not the Periodic Flag Register bits. The
Power Fail Interrupt bit is set when the interrupt is enabled
and a power fail event has occurred, and is not reset until
the power is restored. If all interrupt enable bits are 0 no
interrupt will be asserted. However, status still, can be read
from the Main Status Register in a polled fashion (see Figure5).
150 kn to 350 kn
500n to 900n
500n to 900n
INTERRUPT LOGIC FUNCTIONAL DESCRIPTION
The TCP has the ability to coordinate processor timing activities. To enhance this, an interrupt structure has been implemented which enables several types of events to cause
interrupts. Interrupts are controlled via two Control Registers in block 1 and two Status Registers in block O. (See
Register Description for notes on paging and also Figure 5
and Table I.)
To clear a flag in bits 02-05 of the Main Status Register a 1
must be written back into the bit location that is to be
cleared. For the Periodic Flag Register reading the status
will reset all the periodic flags.
1-10
Functional Description
(Continued)
Interrupts Fall Into Four Categories:
To generate periodic interrupts at the desired rate, the associated Periodic Interrupt Enable bit in Interrupt Control Register 0 must be set. Any combination of periodic interrupts
may be enabled to operate simultaneously. Enabled periodic interrupts will now affect the Periodic Interrupt Flag in the
Main Status Register. The Periodic Route bit in the Interrupt
Routing Register is used to route the periodic interrupt
events to either the INTR output or the MFO output.
1. The Timer Interrupts: For description see Timer Section.
2. The Alarm Compare Interrupt: Issued when the value in
the time compared RAM equals the counter.
3. The Periodic Interrupts: These are issued at every increment of the specific clock counter signal. Thus, an interrupt is issued every minute, second, etc. Each of these
interrupts occurs at the roll-over of the specific counter.
When a periodic event occurs, the Periodic Interrupt Flag in
the Main Status Register is set, causing an interrupt to be
generated. The J.LP clears both flag and interrupt by writing a
"1" to the Periodic Interrupt Flag. The individual flags in the
periodic Interrupt Flag Register do not require clearing to
cancel the interrupt.
4. The Power Fail Interrupt: Issued upon recognition of a
power fail condition by the internal sensing logic. The
power failed condition is determined by the signal on the
PFAIL pin. The internal power fail signal is gated with the
chip select signal to ensure that the power fail interrupt
does not lock the chip out during a read or write.
If all periodic interrupts are disabled and a periodic interrupt
is left pending (Le., the Periodic Interrupt Flag is still set), the
Periodic Interrupt Flag will still be required to be cleared to
cancel the pending interrupt.
ALARM COMPARE INTERRUPT DESCRIPTON
The alarm/time comparison interrupt is a special interrupt
similar to an alarm clock wake up buzzer. This interrupt is
generated when the clock time is equal to a value. programmed into the alarm compare registers. Up to six bytes
can be enabled to perform alarm time comparisons on the
counter chain. These six bytes, or some subset thereof,
would be loaded with the future time at which the interrupt
will occur. Next, the appropriate bits in the Interrupt Control
Register 1 are enabled or disabled (refer to detailed description of Interrupt Control Register 1). The TCP then compares these bytes with the clock time. When all the enabled
compare registers equal the clock time an alarm interrupt is
issued, but only if the alarm compare interrupt is enabled
can the interrupt be generated externally. Each alarm compare bit in the Control Register will enable a specific byte for
comparison to the clock. Disabling a compare byte is the
same as setting its associated counter comparator to an
"always equal" state. For example, to generate an interrupt
at 3:15 AM of every day, load the hours compare with 0 3
(BCD), the minutes compare with 1 5 (BCD) and the faster
counters with 0 0 (BCD), and then disable all other compare
registers. So every day when the time rolls over from
3:14:59.99, an interrupt is issued. This bit may be reset by
writing a one to bit 03 in the Main Status Register at any
time after the alarm has been generated.
POWER FAIL INTERRUPTS DESCRIPTION
The Power Fail Status Flag in the Main Status Register
monitors the state of the internal power fail signal. This flag
may be interrogated by the J.LP, but it cannot be cleared; it is
cleared automatically by the TCP when system power is
restored. To generate an interrupt when the power fails, the
Power Fail Interrupt Enable bit in Interrupt Control Register
1 is set.
The Power Fail Route bit determines which output the interrupt will appear on. Although this interrupt may not be
cleared, it may be masked by clearing the Power Fail Interrupt Enable bit.
POWER FAILURE CIRCUITRY FUNCTIONAL
DESCRIPTION
Since the clock must be operated from a battery when the
main system supply has been turned off, the LV8571A provides circuitry to simplify design in battery backed systems.
This circuitry switches over to the back up supply, and isolates the LV8571A from the host system. Figure 6 shows a
simplified block diagram of this circuitry, which consists of
three major sections; 1) power loss logic: 2) battery switch
over logic: and 3) isolation logic ..
If time comparison for an individual byte counter is disabled,
that corresponding RAM location can then be used as general purpose storage.
Detection of power loss occurs when PFAIL is low. Debounce logic provides a 30 J.Ls-63 J.Ls debounce time, which
will prevent noise on the PFAIL pin from being interpreted
as a system failure. After 30 J.Ls-63 J.Ls the debounce logic
times out and a signal is generated indicating that system
power is marginal and is failing. The Power Fail Interrupt will
then be generated.
PERIODIC INTERRUPTS DESCRIPTION
The Periodic Flag Register contains six flags which are set
by real-time generated "ticks" at various time intervals, see
Figure 5. These flags constantly sense the periodic Signals
and may be used whether or not interrupts are enabled.
These flags are cleared by any read or write operation performed on this register.
1-11
LV8571A
"T1
Interrupt Control Registers
Interrrupt Control
Registers
Main Status
Register
C
Interrupt Routing
Register
Real
Timer
Periodic
Pulse
Signals
(also to
Periodic
Flags)
MUX
ILl..
rTV
ILl ..
rTV
Alarm
Interrupt
Enable
Timer 0
Interrupt
Enable
~
~
a-...-
I\J
Timer 0
Interrupt
Timer 1
Interrupt
O
CD
en
.,n
MFO
Signal
L.......--
Timer 0
Status
Bit
~
~
r--
Alarm
Compare
Signals
O·
e!-
Periodic
Status
Bit
Alarm
Status
Bit
n
Output Mode Register
Control Register
Bits
ruJ0-
r--
~
Alarm
Route
Bit
Timer 0
Route
Bit
I-
H--I?
Interrupt
Mode
Selected
t-
.......
MFO Output
-
-6'
O·
~
O"'
P"'
Buffer
(5
o
a.
S·
c::
(J)
S
r---
t-
I
C
II
INTR Output
Output
Buffer
Power
Fail
----,
Interrupt
Status
Bit
II
Cl
TL/F/11416-9
FIGURE 5. Interrupt Control Logic Overview
Functional Description
(Continued)
Battery Switchover
Vee
~
V+
~
Power
Fail Logic
Delayed
Lockout
Lockout
PFAIL ~--~----~
(External
power fail
signal)
Delay
Enable
Address
and
Control
Buffers
00:07
AO:A4
TL/F/11416-10
FIGURE 6. System-Battery Switch over (Upper Left), Power Fail
and Lock-Out Circuits (Lower Right)
The user may choose to have this power failed signal lockout the TCP's data bus within 30 JLs min/63 JLs max or to
delay the lock-out to enable JLP access after power failure is
detected. This delay is enabled by setting the delay enable
bit in the Routing Register. Also, if the lock-out delay was
not enabled the TCP will disconnect itself from the bus within 30 JLs min ~ 63 JLs max. If chip select is low when a
power failure is detected, a safety circuit will ensure that if a
read or write is held active continuously for greater than
30 JLs after the power fail signal is asserted, the lock-out will
be forced. If a lock-out delay is enabled, the LV8571A will
remain active for 480 JLs after power fail is detected. This
will enable the JLP to perform last minute bookkeeping before total system collapse. When the host CPU is finished
accessing the TCP it may force the bus lock-out before
480 JLs has elapsed by resetting the delay enable bit.
After the generation of a lock-out signal, and eventual
switch in of the battery supply, the pins of the TCP will be
configured as shown in Table II. Outputs that have a pull-up
resistor should be connected to a voltage no greater than
Vss·
TABLE II. Pin Isolation during a Power Failure
The battery switch over circuitry is completely independent
of the PFAIL pin. A separate circuit compares Vee to the
Vss voltage. As the main supply fails, the TCP will continue
to operate from the Vee pin until Vee falls below the Vss
voltage. At this time, the battery supply is switched in, Vee is
disconnected, and the device is now in the standby mode. If
indeterminate operation of the battery switch over circuit is
to be avoided, then the voltage at the Vee pin must not be
allowed to equal the voltage at the Vss pin.
Pin
PFAIL =
Logic 0
CS, RO, WR
AO-A4
00-07
Oscillator
PFAIL
INTR, MFO
Locked Out
Locked Out
Locked Out
Not Isolated
Not Isolated
Not Isolated
Standby Mode
Vee> Vee
Locked Out
Locked Out
Locked Out
Not Isolated
Not Isolated
Open Drain
The Timer and Interrupt Power Fail Operation bits in the
Real-Time Mode Register determine whether or not the timers and interrupts will continue to function after a power fail
event.
As power returns to the system, the battery switch over circuit will switch back to Vee power as soon as it becomes
greater than the battery voltage. The chip will remain in the
locked out state as long as PFAIL = O. When PFAIL = 1
1-13
III
~
,...
......
Il)
co
>
...J
r---------------------------------------------------------------~
Functional Description (Continued)
the chip is unlocked, but only after another 30 p.s min ~
63 p's max debounce time. The system designer must ensure that his system is stable when power has returned.
binary down counter and associated control. The operation
is similar to existing p.P peripheral timers except that several
features have been enhanced. The timers can operate in
four modes, and in addition, the input clock frequency can
be selected from a prescaler over a wide range of frequencies. Furthermore, these timers are capable of generating
interrupts and the Timer a output signal is available as a
hardware output via the MFO pin. Timer 1 output, however,
is not available as a hardware output signal. Both the interrupt and MFO outputs are fully programmable active high, or
low, open drain, or push-pull.
The power fail circuitry contains active linear circuitry that
draws supply current from Vee. In some cases this may be
undesirable, so this circuit can be disabled by masking the
power fail interrupt. The power fail input can perform all
lock-out functions previously mentioned, except that no external interrupt will be issued. Note that the linear power fail
circuitry is switched off automatically when using VBB in
standby mode.
Figure 7 shows the functional block diagram of one of the
timers. The timer consists of a 16-bit counter, two 8-bit input
registers, two 8-bit output registers, clock prescaler, mode
control logic, and output control logic. The timer and the
data registers are organized as two bytes for each timer.
Under normal operations a read/write to the timer locations
wi" read or write to the data input register. The timer contents can be read by setting the counter Read bit (RD) in the
timer control register.
LOW BATTERY, INITIAL POWER ON DETECT, AND
POWER FAIL TIME SAVE
There are three other functions provided on the LV8571A to
ease power supply control. These are an initial Power On
detect circuit, which also can be used as a time keeping
failure detect, a low battery detect circuit, and a time save
on power failure.
On initial power up the Oscillator Fail Flag will be set to a
one and the real time clock start bit reset to a zero. This
indicates that an oscillator fail event has occurred, and time
keeping has failed.
TIMER INITIALIZATION
The timer's operation is controlled by a set of registers, as
listed in Table "I. These consist of 2 data input registers and
one control register per timer. The data input registers contain the timers count down value. The Timer Control Register is used to set up the mode of operation and the input
clock rate. The timer related interrupts can be controlled by
programming the Interrupt Routing Register and Interrupt
Control Register o. The timer outputs are configured by the
Output Mode Register.
The Oscillator Fail flag wi" not be reset until the real-time
clock is started. This allows the system to discriminate between an initial power-up and recovery from a power failure.
If the battery backed mode is selected, then bit 06 of the
Periodic Flag Register must be written low. This wi" not affect the contents of the Oscillator Fail Flag.
Another status bit is the low battery detect. This bit is set
only when the clock is operating under the Vee pin, and
when the battery voltage is determined to be less than 2.1 V
(typical). When the power fail interrupt enable bit is low, it
disables the power fail circuit and wi" also shut off the low
battery voltage detection circuit as we".
To relieve CPU overhead for saving time upon power failure,
the Time Save Enable bit is provided to do this automatically. (See also Reading the Clock: Latched Read.) The Time
Save Enable bit, when set, causes the Time Save RAM to
follow the contents of the clock. This bit can be reset by
software, but if set before a power failure occurs, it wi" automatica"y be reset when the clock switches to the battery
supply (not when a power failure is detected by the PFAIL
pin). Thus, writing a one to the Time Save bit enables both a .
software write or power fail write.
TABLE IIL.Timer Associated Registers
Register Name
Register
Select
Page
Select
Address
Timer a Data MSB
Timer a Data LSB
Timer a Control Register
Timer 1 Data MSB
Timer 1 Data LSB
Timer 1 Control Register
Interrupt Routing Register
Interrupt Control Reg. a
Output Mode Register
X
X
0
X
X
0
0
1
1
a
a
a
a
a
a
a
a
a
10H
OFH
01H
12H
11H
02H
04H
03H
02H
A" these registers must be initialized prior to starting the
timer(s). The Timer Control Register should first be set to
select the timer mode with the timer start/stop bit reset.
Then when the timer is to be started the control register
should be rewritten identically but with the start/stop bit set.
SINGLE POWER SUPPLY APPLICATIONS
The LV8571A can be used in a single power supply application. To achieve this, the VBB pin must be connected to
ground, and the power connected to Vee and PFAIL pins.
The Oscillator Failed/Single Supply bit in the Periodic Flag
Register should be set to a logic 1, which will disable the
oscillator battery reference circuit. The power fail interrupt
should also be disabled. This wi" turn off the linear power
fail detection circuits, and will eliminate any quiescent power
drawn through these circuits. Until the crystal select bits are
initialized, the LV8571A may consume about 50 p.A due to
arbitrary oscillator selection at power on.
TIMER OPERATION
Each timer is capable of operation in one of four modes. As
mentioned, these modes are programmed in each timer's
Control Register which is described later. A" four modes
operate in a similar manner. They operate on the two 8-bit
data words stored into the Data Input Register. At the beginning of a counting cycle the 2 bytes are loaded into the timer
and the timer commences counting down towards zero. The
exact action taken when zero is reached depends on the
mode selected, but in general, the timer output will change
state, and an interrupt wi" be generated if the timer interrupts are unmasked.
(This extra 50 p.A is not consumed if the battery backed
mode is selected).
TIMER FUNCTIONAL DESCRIPTION
The LV8571A contains 2 independent multi-mode timers.
Each timer is composed of a 16-bit negative edge triggered
1-14
r-
Functional Description
<
CO
U1
(Continued)
er causes the same synchronization error that starting the
timer does. The range of errors is specified in Table V.
INPUT CLOCK SELECTION
The input frequency to the timers may be selected. Each
timer has a prescaler that gives a wide selection of clocking
rates. Table IV shows the range of programmable clocks
available and the corresponding setting in the Timer Control
Register. Note that the output of Timer 1 may be used as
the input to Timer O. This is a cascade option for the timers
and allows them to be clocked as a 32-bit down counter.
TABLE V. Maximum Synchronization Errors
Clock Selected
External
Crystal
Crystall4
10.7 kHz
1 kHz
100 Hz
10 Hz
1 Hz
TABLE IV. Programmable Timer Input Clocks
C2
C1
CO
Selected Clock
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Timer 1 Output
Crystal Oscillator
(CrystaIOsciliator)/4
93.5!-,-s (10.7 kHz)
1 ms (1 kHz)
10 ms (100 Hz)
1/10 Second (10 Hz)
1 Second (1 Hz)
.......
.......
»
Error
+ Ext. Clock Period
+ 1 Crystal Clock Period
+ 1 Crystal Clock Period
+32!-'-s
+32!-'-s
+32!-'-s
+32!-'-s
+32!-'-s
MODES OF OPERATION
Bits MO and M 1 in the Timer Control Registers are used to
specify the modes of operation. The mode selection is described in Table VI.
TABLE VI. Programmable Timer Modes of Operation
Note that the second and third selections are not fixedfrequencies, but depend on the crystal oscillator frequency
chosen.
Since the input clock frequencies are usually running asynchronously to the timer Start/Stop control bit, a 1 clock cycle error may result. This error results when the Start/Stop
occurs just after the clock edge (max error). To minimize
this error on all clocks an independent prescaler is used for
each timer and is designed so that its Start/Stop error is
less than 1 clock cycle.
M1
MO
Function
Modes
a
a
0
1
0
1
Single Pulse Generator
Rate Generator, Pulse Output
Square Wave Output
Retriggerable One Shot
Mode a
Mode 1
Mode2
Mode 3
1
1
MODE 0: SINGLE PULSE GENERATOR
When the timer is in this mode the output will be initially low
if the Timer Start/Stop bit is low (stopped). When this mode
is initiated the timer output will go high on the next falling
edge of the prescaler's input clock, the contents of the
The count hold/gate bit in the Timer Control Register can
be used to suspend the timer operation in modes 0, 1, and 2
(in mode 3 it is the trigger input). Suspending the timInlernal Data Bus
To MFO
or INTR
III
Selected Clock
Count Hold/Gate bit
Timer Start/Stop
!.lode 0
!.lode 1
RD bit
TL/F/11416-11
FIGURE 7. LV8571A Timer Block Diagram
1-15
...I
Functional Description
(Continued)
for one clock period of the timer clock. Then on the next
clock the counter is reloaded automatically and the countdown repeats itself. The output, shown in Figure 9, is a
waveform whose pulse width and period is determined by N,
the input register value, and the input clock period:
input data registers are loaded into the timer. The output will
stay high until the counter reaches zero. At zero the output
is reset. The result is an output pulse whose duration is
equal to the input Clock period times the count value (N)
loaded into the input data register. This is shown in Figure 8.
Pulse Width = Clock Period
x
Period = (N
N
+
1) (Clock Period)
Pulse Width = Clock Period
An interrupt is generated when the zero count is reached.
This can be used for one-time interrupts that are set to occur a certain amount of time in the future. In this mode the
Timer Start/Stop bit (TSS) is automatically reset upon zero
detection. This removes the need to reset TSS before starting another operation.
Again, the output polarity is controllable as in mode o. If
enabled, an interrupt is generated whenever the zero count
is reached. This can be used to generate a periodic interrupt.
MODE 2: SQUARE WAVE GENERATOR
The count down operation may be temporarily suspended
either under software control by setting the Count Hold/
Gate bit in the timer register high, or in hardware by setting
the GO or G1 pin high.
This mode is also cyclic but in this case a square wave
rather than a pulse is generated. The output square wave
period is determined by the value loaded into the timer input
register. This period and the duty cycle are:
The above discussion assumes that the MFO output is programmed to be non-inverting outputs (active high). If the
polarity of the output waveform is wrong for the application
the polarity can be reversed by configuring the Output Mode
Register. The drive configuration can also be programmed
to be push pull or open drain.
Period = 2(N
+ 1) (Clock Period)
Duty Cycle = 0.5
When the timer is stopped the output will be low, and when
the Start/Stop bit is set high the timer's counter will be loaded on the next clock falling transition and the output will be
set high.
The output will be toggled after the zero count is detected
and the counter will then be reloaded, and the cycle will
continue. Thus, every N + 1 counts the output gets toggled,
as shown in Figure 10. Like the other modes the timer operation can be suspended by setting the count hold/gate bit
(CHG) in the Timer Control Register. An interrupt will be
generated every falling edge of the timer output, if enabled.
MODE 1: RATE GENERATOR
When operating in this mode the timer will operate continuously. Before the timer is started its output is low. When the
timer is started the input data register contents are loaded
into the counter on the negative clock edge and the output
is set high (again assuming the Output Mode Register is
programmed active high). The timer will then count down to
zero. Once the zero count is reached the output goes low
I 1 I0 I
Internal
Counter
Clock
Timer
Start/Stop
Count Hold/
Gate Bit
Timer
Output
TL/F/11416-12
FIGURE 8. Typical Waveforms for Timer Mode 0
(MFO Output Programmed Active High)
Internal
Counter
Clock
Timer
Start/Stop
Count Hold/
Gate Bit
Timer
Output
TLlF/11416-13
FIGURE 9. Timing Waveforms for Timer Mod~ 1
(MFO Output Programmed Active High)
1-16
r
Functional Description
<
co
(Continued)
1312111013121
01
Those users who find the error rate unacceptable may reduce the problem effectively to zero by employing a hardware work-around that synchronizes the writing of the read
bit to the timer control register with respect to the decrementing clock. Refer to Figure 1 in Appendix A, for a suggested hardware work-around.
10 1
Internal
Counter
Clock
Timer
Start/Stop
Count Hold/
Gate Bit
A software work-around can reduce the errors but not as
substantial as a hardware work-around. Software workarounds are based on observations that the read following a
bad read appeared to be valid.
Timer
Output
TL/F/11416-14
This problem concerns statistical probability and is similar to
metastability issues. For more information on metastability,
refer to 1991 IEEE transactions on Custom Integrated Circuits Conference, paper by T.J. Gabara of AT&T Bell Laboratories, page 29.4.1.
FIGURE 10. Timing Waveforms for Timer Mode 2
(MFO Output Programmed Active High)
MODE 3: RETRIGGERABLE ONE SHOT
Once the timer Start/Stop bit is set the output stays inactive, and nothing happens until the Count Hold/Gate (CHG)
bit is set in the timer control register. When a transition
ocurs the one shot output is set active immediately; the
counter is loaded with the value in the input register on the
next transition of the input clock and the countdown begins.
If a retrigger occurs, regardless of the current counter value,
the counters will be reloaded with the value in the input
register and the counter will be restarted without changing
the output state. See Figure 11. A trigger count can occur at
any time during the count cycle. In this mode the timer will
output a single pulse whose width is determined by the value in the input data register (N) and the input clock period.
Normally reading the timer data register addresses, OFH
and 1OH for Timer 0 and 11 Hand 12H for Timer 1 will result
in reading the input data register which contains the preset
value for the timers.
To read the contents of a timer, the ,.,.p first sets the timer
read bit in the appropriate Timer Control Register high. This
will cause the counter's contents to be latched to 2-8 bit
output registers, and will enable these registers to be read if
the ,.,.p reads the timer's input data register addresses. On
reading the LSB byte the timer read bit is internally reset
and subsequent reads of the timer locations will return the
input register values.
Pulse Width = Clock Period X N
DETAILED REGISTER DESCRIPTION
The timer will generate an interrupt only when it reaches a
count of zero. This timer mode is useful for continuous
"watch dog" timing, line frequency power failure detection,
etc.
There are 5 external address bits: Thus, the host microprocessor has access to 32 locations at one time. An internal
switching scheme provides a total of 67 locations.
This complete address space is organized into two pages.
Page 0 contains two blocks of control registers, timers, real
time clock counters, and special purpose RAM, while page
1 contains general purpose RAM. Using two blocks enables
the 9 control registers to be mapped into 5 locations. The
only register that does not get switched is the Main Status
Register. It contains the page select bit and the register
select bit as well as status information.
READING THE TIMERS
National has discovered that some users may encounter
unacceptable error rates for their applications when reading
the timers on the fly asynchronously. When doing asynchronous reads of the timers, an error may occur. The error is
that a successive read may be larger than the previous
read. Experimental results indicate that the typical error rate
is approximately one per 29000 under the following conditions:
Timer clock frequency of 5 MHz.
Computer: 386/33 MHz PC/AT
Program:
A memory map is shown in Figure 2 and register addressing
in Table VII. They show the name, address and page locations for the LV8571 A.
Microsoft 'C' 6.0, reading and saving timer contents in a continuous loop.
Internal
Counter
Clock
Timer
Start/Stop
Count Hold/
Gate Bit
Timer
Output
TL/F/11416-15
FIGURE 11. Timing Waveforms for Timer Mode 3, MFO Output Programmed Active High
1-17
~
.....
»
«
,...
r-...
ll)
co
Functional Description
>
...I
(Continued)
TABLE VII. Register/Counter/RAM
Addressing for LV8571A
AO·4
PS
RS
(Note 1) (Note 2)
MAIN STATUS REGISTER
I PS I RS I
CONTROL REGISTERS
00
01
02
03
04
01
02
03
04
X
0
0
0
0
0
0
0
0
X
0
0
0
0
1
1
1
1
Til Tol
ALlpERI PFllNfi
L
Description
00 Interrupt Status
01 Power Fail Interrupt
02 Period Interrupt
Main Status Register
Timer 0 Control Register
Timer 1 Control Register
Periodic Flag Register
Interrupt Routing Register
Real Time Mode Register
Output Mode Register
Interrupt Control Register 0
Interrupt Control Register 1
03 Alarm Interrupt
04 Timer 0 Interrupt
05 Timer 1 Interrupt
06 Register Select Bit
07 Page Select Bit
TLlF/11416-16
COUNTERS (CLOCK CALENDAR)
05
06
07
08
09
0
0
0
0
0
X
X
X
X
X
OA
OB
OC
00
OE
0
0
0
0
0
X
X
X
X
X
1/100, 1/10 Seconds
Seconds
Minutes
Hours
Days of
Month
Months
Years
Julian Date (lSB)
Julian Date
Day of Week
The Main Status Register is always located at address 0
regardless of the register block or the page selected.
(0-99)
(0-59)
(0-59)
(1-12,0-23)
00: This read only bit is a general interrupt status bit that is
taken directly from the interrupt pins. The bit is a one when
an interrupt is pending on either the INTR pin or the MFO
pin (when configured as an interrupt). This is unlike 03-05
which can be set by an internal event but may not cause an
interrupt. This bit is reset when the interrupt status bits in the
Main Status Register are cleared.
(1-28/29/30/31 )
(1-12)
(0-99)
(1-99)
(0-3)
(1-7)
01-05: These five bits of the Main Status Register are the
main interrupt status bits. Any bit may be a one when any of
the interrupts are pending. Once an interrupt is asserted the
ILP will read this register to determine the cause. These
interrupt status bits are not reset when read. Except for 01,
to reset an interrupt a one is written back to the correspond·
ing bit that is being tested. 01 is reset whenever the PFAIL
pin = logic 1. This prevents loss of interrupt status when
reading the register in a polled mode. 01, 03-05 are set
regardless of whether these interrupts are masked or not by
bits 06 and 07 of Interrupt Control Registers 0 and 1.
TIMER DATA REGISTERS
OF
10
11
12
0
0
0
0
X
X
X
X
Timer 0 lSB
Timer 0 MSB
Timer 1 lSB
Timer 1 MSB
TIME COMPARE RAM
13
14
15
0
0
0
X
X
X
16
0
X
17
0
X
18
0
X
Sec Compare RAM
Min Compare RAM
Hours Compare
RAM
DOMCompare
RAM
Months Compare
RAM
DOW Compare RAM
10
0
0
0
0
0
X
X
X
X
X
Seconds Time Save RAM
Minutes Time Save RAM
Hours Time Save RAM
Day of Month Time Save RAM
Months Time Save RAM
1E
IF
0
0
1
X
RAM
RAMITest Mode Register
01-1F
1
X
2nd Page General Purpose RAM
(0-59)
(0-59)
(1-12,0-23)
06 and 07: These bits are Read/Write bits that control
which register block or RAM page is to be selected. Bit 06
controls the register block to be accessed (see memory
map). The memory map of the clock is further divided into
two memory pages. One page is the registers, clock and
timers, and the second page contains 31 bytes of general
purpose RAM. The page selection is determined by bit 07.
(1-28/29/30/31 )
(1-12)
(1-7)
TIME SAVE RAM
19
lA
1B
1C
1 PS-Page Select (Bit D7 of Main Status Register)
2 RS-Register Select (Bit D6 of Main Status Register)
1·18
r-
<
Functional Description
(X)
(Continued)
TIMER 0 AND 1 CONTROL REGISTER
U1
~O-OS:
These bits are set by the real time rollover events:
(Time Change = 1). The bits are reset when the register is
read and can be used as selective data change flags.
1CHG 1 RD 1 C2 1 C1 1CO 1 1.41 1 1.40 1TSSI
L
06: This bit performs a dual function. When this bit is read, a
one indicates that an oscillator failure has occurred and the
time information may have been lost. Some of the ways an
oscillator failure might be caused are: failure of the crystal,
shorting OSC IN or OSC OUT to GNO or Vee, removal of
crystal, removal of battery when in the battery backed mode
(when a "0" is written to 06), lowering the voltage at the
Vss pin to a value less than 2.2V when in the battery
backed mode. Bit 06 is automatically set to 1 on initial power-up or an oscillator fail event. The oscillator fail flag is
reset by writing a one to the clock start/stop bit in tl";e Real
Time Mode Register, with the crystal oscillating.
When 06 is written to, it defines whether the TCP is being
used in battery backed (normal) or in a single supply mode
application. When set to a one this bit configures the TCP
for single power supply applications. This bit is automatically
set on initial power-up or an oscillator fail event. When set,
06 disables the oscillator reference circuit. The result is that
the oscillator is referenced to Vee. When a zero is written to
06 the oscillator reference is enabled, thus the oscillator is
referenced to Vss. This allows operation in standard battery
standby applications.
At initial power on, if the LV8571A is going to be programmed for battery backed mode, the Vss pin should be
connected to a potential in the range of 2.2V to Vee-O.4V.
DO Timer Start/Stop
D1 Mode Select
D2 Mode Select
D3 Input Clock Select
D4 Input Clock Select
D5 Input Clock Select
D6 Timer Read
D7 Count Hold/Gate
TL/F/11416-17
These registers control the operation of the timers. Each
timer has its own register.
DO: This bit will Start (1) or Stop (0) the timer. When the
timer is stopped the timer's prescaler and counter are reset,
and the timer will restart from the beginning when started
again. In mode 0 on time out the TSS bit is internally reset.
01 and 02: These control the count mode of the timers.
See Table VI.
03-05: These bits control which clock signal is applied to
the timer's counter input. Refer to Table IV for details.
OG: This is the read bit. If a one is written into this location it
will cause the contents of the timer to be latched into a
holding register, which can be read by the JlP at any time.
Reading the least significant byte of the timer will reset the
RO bit. The timer read cycle can be aborted by writing RO to
zero.
For single supply mode operation, the Vss pin should be
connected to GNO and the PFAIL pin connected to Vee.
07: Writing a one to this bit enables the test mode register
at location 1F (see Table VII). This bit should be forced to
zero during initialization for normal operation. If the test
mode has been entered, clear the test mode register before
leaving test mode. (See separate test mode application
note for further details.)
07: The CHG bit has two mode dependent functions. In
modes 0 through 2 writing a one to this bit will suspend the
timer operation (without resetting the timer prescaler). However, in mode 3 this bit is used to trigger or re-trigger the
count sequence as with the gate pins. If retriggering is desired using the CHG bit, it is not necessary to write a zero to
this location prior to the re-trigger. The action of further writing a one to this bit will re-trigger the count.
INTERRUPT ROUTING REGISTER
I TS I LB IPFDIT1RITORIALRIPRRIPFRI
L
PERIODIC FLAG REGISTER
I Tt,j 10SF
lms 110ms 100msl 15 110.11 min]
I L=
......
......
»
DO Power fail route
D1 Periodic route
DO minutes flag
D2 Alarm route
01 10 second flag
D3 Timer 0 route
02 seconds flag
D4 Timer 1 route
03 100 millisec. flag
D5 PF Delay Enable
04 10 millisec. flag
05 mill i-seconds flag
D6 Low Battery flag
06 Oscillator Failed/Singl. Supply
D7 Time Save Enable
07 Tost t,jod. [nabl.
TL/F/11416-19
TL/F/11416-18
00-04: The lower 5 bits of this register are associated with
The Periodic Flag Register has the same bit for bit correspondence as Interrupt Control Register 0 except for 06
and 07. For normal operation (Le., not a single supply application) this register must be written to on initial power up or
after an oscillator fail event. 00-05 are read only bits, 06
and 07 are read/write.
the main interrupt sources created by this chip. The purpose
of this register is to route the interrupts to either the MFO
(multi-function pin), or to the main interrupt pin. When any
bit is set the associated interrupt signal will be sent to the
MFO pin, and when zero it will be sent to the INTR pin.
1-19
III
..J
Functional Description
(Continued)
02: The count mode for the hours counter can be set to
either 24 hour mode or 12 hour mode with AM/PM indicator.
A one will place the clock in 12 hour mode.
05: The Delay Enable bit is used when a power fail oc(;urs.
If this bit is set, a 480 p's delay is generated internally before
the p.P interface is locked out. This will enable the p.P to
access the registers for up to 480 p's after it receives a
power fail interrupt. After a power failure is detected but
prior to the 480 p.s delay timing out, the host p.P may force
immediate lock out by resetting the Delay Enable bit. Note if
this bit is aO when power fails then after a delay of 30 p.s
min/63 p's max the p.P cannot read the chip.
03: This bit is the master Start/Stop bit for the clock. When
a one is written to this bit the real time counter's prescaler
and counter chain are enabled. When this bit is reset to zero
the contents of the real time counter is stopped and the
prescaler is cleared. When the TCP is initially powered up
this bit will be held at a logic 0 until the oscillator starts
functioning correctly after which this bit may be modified. If
an oscillator fail event occurs, this bit will be reset to logic O.
06: This read only bit is set and reset by the voltage at the
Vss pin. It can be used by the p.P to determine whether the
battery voltage at the Vss pin is getting too low. A comparator monitors the battery and when the voltage is lower than
2.1 V (typical) this bit is set. The power fail interrupt must be
enabled to check for a low battery voltage.
04: This bit controls the operation of the interrupt output in
standby mode. If set to a one it allows Alarm, Periodic, and
Power Fail interrupts to be functional in standby mode. Timer interrupts will also be functional provided that bit 05 is
also set. Note that the MFO and INTR pins are configured
as open drain in standby mode.
07: Time Save Enable bit controls the loading of real-timeclock data into the Time Save RAM. When a one is written
to this bit the Time Save RAM will follow the corresponding
clock registers, and when a zero is written to this bit the time
in the Time Save RAM is frozen. This eliminates any synchronization problems when reading the clock, thus negating the need to check for a counter rollover during a read
cycle.
If bit 04 is set to a zero then interrupt control register 0 and
bits 06 and 07 of interrupt control register 1 will be reset
when the TCP enters the standby mode (Vss > Vee). They
will have to be re-configured when system (Vee) power is
restored.
05: This bit controls the operation of the timers in standby
mode. If set to a one the timers will continue to function
when the TCP is in standby mode. The input pins TCK, GO,
G1 are locked out in standby mode, and cannot be used.
This bit must be set to a one prior to power failing to enable
the Time Save feature. When the power fails this bit is automatically reset and the time is saved in the Time Save RAM.
Therefore external control of the timers is not possible in
standby mode. Note also that MFO and T1 pins are automatically reconfigured open drain during standby.
REAL TIME MODE REGISTER
I XT11 xTol TPFIIPF IcssI12H LY11 Lyol
I
06 and 07: These two bits select the crystal clock frequency as per the following table:
L.. 00 Leap Year LSB
L - O l Leap Year MSB
L..----02 12/24 hour mode
1 -_ _ _ _ _
03 Clock Start/Stop
L..-_ _ _ _ _ _ 04 Interrupt PF Operation
1 -_ _ _ _ _ _ _ _
05 Timer PF Operation
L..-_ _ _ _ _ _ _ _ _
06 Crystal Frequency LSB
L..-_ _ _ _ _ _ _ _ _ _ _
07 Crystal Frequency MSB
0
0
1
1
LYO
0
1
0
1
XTO
Crystal
Frequency
0
0
1
1
0
1
0
1
32.768 kHz
4.194304 MHz
4.9152 MHz
32.000 kHz
All bits are Read/Write, and any mode written into this register can be determined by reading the register. On initial
power up these bits are random.
TLIF/11416-20
00-01: These are the leap year counter bits. These bits are
written to set the number of years from the previous leap
year. The leap year counter increments on December 31st
and it internally enables the February 29th counter state.
This method of setting the leap year allows leap year to
occur whenever the user wishes to, thus providing flexibility
in implementing Japanese leap year function.
LY1
XT1
OUTPUT MODE REGISTER
I Mol MTI MPI MHllPl IHf TPI THl
I L::::
L..-_ _ _
Leap Year
Counter
L..-_ _ _ _ _
L..-_ _ _ _ _ _
Leap Year Current Year
Leap Year Last Year
Leap Year 2 Years Ago
Leap Year 3 Years Ago
L..-_ _ _ _ _ _ _
L..-_ _ _ _ _ _ _ _ _
1-_ _ _ _ _ _ _ _ _ _
D2 INTR Active Hi/lOW
D3 INTR Push pull/Open Drain
D4 MFO Active Hi/lOW
D5 MFO Push pull/Open Drain
D6 MFa pin as Timer a
07 MFa Pin as Oscillator
TLIF/11416-21
1-20
Functional Description
(Continued)
00 and 01: These bits are available as general purpose
switching is required. When all six bits are written to a 0 this
disables periodic interrupts from the Main Status Register
and the interrupt pin.
RAM.
02: This bit, when set to a one makes the INTR output pin
active high, and when set to a zero, it makes this pin active
low.
06 and 07: These are individual timer enable bits. A one
written to these bits enable the timers to generate interrupts
to the IlP.
03: This bit controls whether the INTR pin is an open drain
or push-pull output. A one indicates push-pull.
INTERRUPT CONTROL REGISTER 1
04: This bit, when set to a one makes the MFO output pin
active high, and when set to a zero, it makes this pin active
low.
I pre I ALelOOMI MOl OOM I HRI MN I SC I
IL=
05: This bit controls whether the MFO pin is an open drain
or push-pull output. A one indicates push-pull.
06 and 07: These bits are used to program the signal ap-
DO Second compare enable
01 Minute compare enable
02 Hour compare enable
03 Day of month enable
pearing at the MFO output, as follows:
04 t.4onth compare enable
05 Day of week enable
07
06
MFO Output Signal
0
0
1
X
2nd Interrupt
Timer 0 Waveform
Buffered Crystal Oscillator
0
1
D6 Alarm interrupt enable
07 Power fail interrupt enable
TL/F/11416-23
00-05: Each of these bits are enable bits which will enable
a comparison between an individual clock counter and its
associated compare RAM. If any bit is a zero then that
clock-RAM comparator is set to the "always equal" state
and the associated TIME COMPARE RAM byte can be used
as general purpose RAM. However, to ensure that an alarm
interrupt is not generated at bit 03 of the Main Status Register, all bits must be written to a logic zero.
INTERRUPT CONTROL REGISTER 0
I
TllTOllmltmlhml SiTS
I t.4N I
L
DO t.4inutes enable
01 10 second enable
02 Seconds enable
06: In order to generate an external alarm compare interrupt to the IlP from bit 03 of the Main Status Register, this
bit must be written to a logic 1. If battery backed mode is
selected then this bit is controlled by 04 of the Real Time
Mode Register.
03 100 millisec enable
04 10 millisec enable
05 millisec enable
06 Timer 0 enable
07: The MSB of this register is the enable bit for the Power
07 Timer 1 enable
Fail Interrupt. When this bit is set to a one an interrupt will
be generated to the IlP when PFAIL = O. If battery backed
mode is selected then this bit is controlled by 04 of the Real
Time Mode Register.
TL/F/11416-22
00-05: These bits are used to enable one of the selected
periodic interrupts by writing a one into the appropriate bit.
These interrupts are issued at the rollover of the clock. For
example, the minutes interrupt will be issued whenever the
minutes counter increments. In all likelihood the interrupt
will be enabled asynchronously with the real time change.
Therefore, the very first interrupt will occur in less than the
periodic time chosen, but after the first interrupt all subsequent interrupts will be spaced correctly. These interrupts
are useful when minute, second, real time reading, or task
This bit also enables the low battery detection analog circuitry.
.
If the user wishes to mask the power fail interrupt, but utilize
the analog circuitry, this bit should be enabled, and the
Routing Register can be used to route the interrupt to the
MFO pin. The MFO pin can then be left open or configured
as the Timer 0 or buffered oscillator output.
III
1-21
Control and Status Register Address Bit Map
07
06
Main Status Register PS = 0
R/W
R/W
05
RS = 0
R/W1
04
03
02
ADDRESS = OOH
R/W1
R/W1
01
00
1. Reset by
writing
1 to bit.
R/W1
2. Set/reset by
voltage at
PFAILpin.
3. Reset when
all pending
interrupts
are removed.
All Bits R/W
All Bits R/W
·4. Read Osc fail
Write 0 BattBacked Mode
Write 1 Single
Supply Mode
5. Reset by
positive edge
of read.
Interrupt Routing Register PS = 0
R/W
Time Save
Enable
RS = 0
Address = 04H
R6
R/W
R/W
R/W
R/W
R/W
R/W
Low Battery
Flag
Power Fail
Delay
Enable
Timer 1
Int. Route
MFO/INT
Timer 0
Int. Route
MFO/INT
Alarm
Int. Route
MFO/INT
Periodic
Int. Route
MFO/INT
Power Fail
Int. Route
MFO/INT
RS = 1
6. Set and reset
byVss
voltage.
Address = 01 H
All Bits R/W
All Bits R/W
Interrupt Control Register 0 PS = 0
Timer 1
Interrupt
Enable
Timer 0
Interrupt
Enable
1 ms
Interrupt
Enable
Interrupt Control Register 1 PS = 0
Power Fail
Interrupt
Enable
Alarm
Interrupt
Enable
DOW
Interrupt
Enable
RS = 1
10 ms
Interrupt
Enable
RS = 1
Month
Interrupt
Enable
Address = 03H
100 ms
Interrupt
Enable
Seconds
Interrupt
Enable
10 Second
Interrupt
Enable
Minute
Interrupt
Enable
All Bits R/W
Minute
Interrupt
Enable
Second
Interrupt
Enable
All BitsR/W
Address = 04H
DOM
Interrupt
Enable
1-22
Hours
Interrupt
Enable
Application Hints
ration, interrupt control and timer functions may be initialized.
6. Test bit 06 in the Periodic Flag Register:
IF a 1, go to 5.1 If this bit remains a 1 after 3 seconds,
then abort and check hardware. The crystal may be defective or not installed. There may be a short at OSC IN
or OSC OUT to Vee or GNO, or to some impedance that
is less than 10 MD..
IF a 0, then the oscillator is running, go to step 7.
7. Write a 0 to bit 06 in the Periodic Flag Register. This
action puts the clock chip in the battery backed mode.
This mode can be entered only if the OSC fail flag (bit
.06 of the Periodic Flag Register) is a O. Reminder, bit 06
is a dual function bit. When read, 06 returns oscillator
status. When written, 06 causes either the Battery
Backed Mode, or the Single Supply Mode of operation.
The only method to ensure the chip is in the battery
backed mode is to measure the waveform at the OSC
OUT pin. If the battery backed mode was selected successfully, then the peak to peak waveform at OSC OUT
is referenced to the battery voltage. If not in battery
backed mode, the waveform is referenced to Vee. The
measurement should be made with a high impedance
low capacitance probe (10 MD., 10 pF oscilloscope
probe or better). Typical peak to peak swings are within
0.6V of Vee and ground respectively.
8. Write a 1 to bit 07 of Interrupt Control Register 1. This
action enables the PFAIL pin and associated circuitry.
9. Write a 1 to bit 04 of the Real Time Mode Register. This
action ensures that bit 07 of Interrupt Control Register 1
remains a 1 when Vss > Vee (standby mode).
10. Initialize the rest of the chip as needed.
Suggested initialization procedure for LV8571 A in battery
backed applications that use the Vss pin ..
1. Enter the test mode by writing a 1 to bit 07 in the Periodic Flag Register.
2. Write zero to the RAM/TEST mode Register located in
page 0, address HEX 1F.
3. Leave the test mode by writing a 0 to bit 07 in the Periodic Flag Register. Steps 1, 2, 3 guarantee that if the
test mode had been entered during power on (due to
random pulses from the system), all test mode conditions are cleared. Most important is that the OSC Fail
Disable bit is cleared. Refer to AN-589 for more information on test mode operation.
4. After power on (Vee and Vss powered), select the correct crystal frequency bits (07, 06 in the Real Time
Mode Register) as shown in Table 1.
Table 1
07
06
32.768 KHz
0
0
4.194304 MHz
0
1
4.9152 MHz
1
0
32.0 KHz
1
1
Frequency
5. Enter a software loop that does the following:
Set a 3 second(approx) software counter. The crystal
oscillator may take 1 second to start.
5.1 Write a 1. to bit 03 in the Real Time Mode Register (try
to start the clock). Make sure the crystal select bits remain the same as in step 1. Under normal operation, this
bit can be set only if the oscillator is running. During the
software loop, RAM, real time counters, output configu-
Typical Application
A low going user
generated power
fail signal should
be presented t. the
LV8571A
L.
o
Timer
esc
Clock
Peripheral
VI
VI
CD
o
ea.
e
.~
PFAIL pin.
IN J--_---.
esc OUT
:::::E
2-22 pF
32.768 kHz
T
47pF
MFa
GND
TLIF/11416-24
·These components may be necessary to meet UL requirements for lithium batteries. Consult battery manufacturer.
1-23
Appendix A
-------------------------------~
+5
- -:h. -'
F· ~,016
..
-:- Dl
~
.....
::::E
-<
z
-'
-<
z
t!l
Vi
AEN
A5
, A6
A7
A8
A9
Tl = 2N2222
SPEED UP CAP.
75 pF SilVER MICA
1.5k :
~
All
A26
A25
A24
A23
A22
--
I/o
CH RDY
AEN 2
r---rr
r----rr
r---s
~
r----t7
~
+5V
AD
A4
A5
A3
A6
A7
C
Vee
~
B7
B6
..!..L
~
~
~
--4....g.
~
~
~
Al
A2
BO
Bl
B2
B3
To
EN
....1-1
~
B14
A31
A30
A29
A28
A27
DO
Dl
D2
D3
D4
D5
D6
D7
A9
A8
A7
A6
A5
A4
A3
A2
GND
A=8
750n
19
~
HEX 300 TO 31F
11 _
_.
1
ClK B20
11. 1 MHz
OSC B30
33 MHz
I
.h
8
o
,_10
A,....
[1210
_
•
1
cs Vee
3
ViR
2
4
5
6
7
8
RD
_ 13
'-
---~-------------
19
DIR
G
74lS245
Vee
+5V
GND
NOTE: AlS OR lS MAYBE US ED
28/24
•
ADDRO
ADDRI
ADDR2
ADDR3
ADDR4
9
8
7
6
5
4
3
2
8
,~
5
9
lOR
'AD
Al
A2
A3
A4
!
IS 1/4 OF A 74lS02
+5
V
B13
A
74lS164
ClK
12
20
GND
~O
11
12
13
14
15
16
17
18
WORK AROUND
INSIDE POLYGONS
2rll
RESET
"r;
84
9
8
o
+5
0
3
74AlS522
lOW
PROTECTS BASE-EMITTER
FROM BREAKDOWN
.. _. ---------
z
a:::
AID
Dl = lN914
DATAO
DATA 1
DATA2
DATA3
'DATA4
DATA5
DATA6
DATA7
H
EXTERNAL
OSCILLATOR
I
18
19
20
21
22
23
24
25
14/12
~
27/23
PFAll
AO
Al
A2
A3
A4 DP8570/71
DO
Dl
D2
03
D4
D5
D6
D7
Vaa
GND
OSC
IN
r1
OSC
OUT
112/10
113 /
11
B3
+5V
+5V B29
GND
81
GND B31
TLIF/11416-29
FIGURE A1. Typical Interface Where the "Write Strobe" is Synchronized to the Decrementing Clock of the Timer
1-24
Typical Performance Characteristics
Operating Current vs
Supply Voltage
(Battery Backed Mode
Fosc = 32.768 kHz,
Vee = 2.5V)
Operating Current vs
Supply Voltage
(Single Supply Mode
Fosc = 32.768 kHz)
200.----r----~--~----,
SOO.----r----~--~----,
f = 1 MHz
lS0r----r----~C-~----~
4S0r----r--~~--~----~
"" 100 r----r----_t_----:J;----~
,3
-~
400r---~----_t_--~~--~
SO I----+---
3.0
3S0r----+~~~----r---~
3.3
300
3.6
I - - - - _ + _ - CONDITIONS:
Vee (Volts)
f
= SQ.
TL/F/11416-25
RD. WR.
WAVE. VLO
3.0
=
CS
= Vee
AO -A4 = f
OV. VHI
Vee
3.3
=
3.6
Vee (Volts)
TLlF/11416-26
Standby Current vs Power
Supply Voltage
(Fosc = 32.768 kHz)
/
12
<-
,3
'"'"
4
Standby Current vs Power
Supply Voltage
(Fosc = 4.194304 MHz)
--'"
2.0
2.S
/
V
/
~
~
160
V
<-
/
,3 120
'"'"
/
/
V
80
3.0
3.S
4.0
4.S
2.S
Vaa (Volts)
3.0
3.S
4.0
4.S
Vaa (Volts)
TLlF/11416-27
TL/F/11416-28
1-25
«
C'\I
~ ~National
~
U
PRELIMINARY
Semiconductor
LV8572A Low Voltage Real Time Clock (RTC)
General Description
The LV8572A is intended for use in microprocessor based
systems where information is required for multi-tasking, data
logging or general time of day/date information. This device
is implemented in low voltage silicon gate microCMOS technology to provide low standby power in battery back-up environments. The circuit's architecture is such that it looks
like a contiguous block of memory or I/O ports. The address
space is organized as 2 software selectable pages of 32
bytes. This includes the Control Registers, the Clock Counters, the Alarm Compare RAM, and the Time Save RAM.
Any of the RAM locations that are not being used for their
intended purpose may be used as general purpose CMOS
RAM.
Time and date are maintained from 1/100 of a second to
year and leap year in a BCD format, 12 or 24 hour modes.
Day of week, day of month and day of year counters are
provided. Time is controlled by an on-chip crystal oscillator
requiring only the addition of the crystal and two capacitors.
The choice of crystal frequency is program selectable.
Power failure logic and control functions have been integrated on chip. This logic is used by the RTC to issue a power
fail interrupt, and lock out the ILP interface. The time power
fails may be logged into RAM automatically when VBB >
Vee. Additionally, two supply pins are provided. When
VBB > Vee, internal circuitry will automatically switch from
the main supply to the battery supply. Status bits are provided to indicate initial application of battery power, system
(Continued)
power, and low battery detect.
Features
• 3.3V ± 10% supply
• Full function real time clock/calendar
-12/24 hour mode timekeeping
- Day of week and day of years counters
- Four selectable oscillator frequencies
- Parallel resonant oscillator
• Power fail features
- Internal power supply switch to external battery
- Power Supply Bus glitch protection
- Automatic log of time into RAM at power failure
• On-chip interrupt structure
- Periodic, alarm, and power fail interrupts
• Up to 44 bytes of CMOS RAM
Block Diagram
osc
OSC
out
in
V+
Vee
Real Time
Clock Counters
Power
Fail
00-7
AO-4
TL/F/11417-1
FIGURE 1
1-26
Absolute Maximum Ratings
Operation Conditions
(Notes 1 & 2)
Specifications for the 883 version of this product are
listed separately.
Supply Voltage (Vee) (Note 3)
Supply Voltage (Vee)
- 0.5V to + 7.0V
Supply Voltage (Vss) (Note 3)
DC Input Voltage (VIN)
-0.5V to Vee +0.5V
DC Output Voltage (VOUT)
Storage Temperature Range
-0.5V to Vee + 0.5V
- 65°C to + 150°C
DC Input or Output Voltage
(VIN' VOUT)
Operation Temperature (TA)
Electr-Static Discharge Rating
Power Dissipation (PO)
500mW
Lead Temperature (Soldering, 10 sec.)
Typical Values
8JA DIP
260°C
8JA PLCC
Min
3.0
Max
3.6
Unit
V
2.2 Vee- O.4
V
0.0
Vee
V
-40
+85
1
°C
kV
Board
Socket
Board
Socket
61°C/W
6?-C/W
80°C/W
88°C/W
DC Electrical Characteristics
Vee = 3.3V ± 10%, Vss = 2.5V, VPFAIL > VIH, CL = 100 pF (unless otherwise specified)
Symbol
Parameter
Conditions
Min
Max
Units
VIH
High Level Input Voltage
(Note 4)
Any Inputs Except OSC IN,
OSC IN with External Clock
2.0
Vss -0.2
Vee +0.3
V
V
VIL
Low Level Input Voltage
All Inputs Except OSC IN
OSC IN with External Clock
-0.3
-0.3
0.8
0.2
V
V
VOH
High Level Output Voltage
(Excluding OSC OUT, INTR)
lOUT = - 20 p.A
lOUT = - 2.0 mA
VOL
Low Level Output Voltage
(Excluding OSC OUT)
lOUT = 20 p.A
lOUT = 2.0 mA
V
V
Vee -0,2
2.4
0.2
0.3
V
V
liN
Input Current (Except OSC IN)
VIN = Vee or GND
±0.7
p.A
loz
Output TRI-STATE® Current
VOUT = VeeorGND
±1
p.A
ILKG
Output High Leakage Current
MFO, INTR Pins
VOUT = Vee or GND
Outputs Open Drain
±1
p.A
lee
Quiescent Supply Current
(Note 7)
Fose
VIN =
VIN =
VIN =
220
700
5
p.A
p.A
rnA
4
6
rnA
rnA
30
3
p.A
rnA
8
400
p.A
p.A
0.8
p.A
p.A
= 32.768 kHz
Vee or GND (Note 5)
Vee or GND (Note 6)
VIH or VIL (Note 6)
Fose = 4.194304 MHz or
4.9152 MHz
VIN = Vee or GND (Note 6)
VIN = VIH or VIL (Note 6)
lee
Iss
ISLK
Quiescent Supply Current
(Single Supply Mode)
(Note 7)
Vss = GND
VIN = Vee or GND
Fose = 32.768 kHz
Fose = 4.9152 MHz or
4.194304 MHz
Standby Mode Battery
Supply Current
(Note 7)
Vee = GND
OSC OUT = open circuit,
other pins = GND
Fose = 32.768 kHzp.A
Fose = 4.9152 MHz or
4.194304 MHz
Battery Leakage
2.2V ~ Vss ~ 2.6V
other pins at GND
Vee = GND, Vss = 2.6V
Vee = 3.6V, Vss = 2.2V
-0.8
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: For Fosc = 4.194304 or 4.9152 MHz, VBB minimum = 2.SV. In battery backed mode, VBB s: Vcc -O.4V.
Single Supply Mode: Data retention voltage is 2.2V min.
In single Supply Mode (Power connected to Vcc pin) 3.0V s: Vcc s: 3.6.
Note 4: This parameter (VI H) is not tested on all pins at the same time.
Note 5: This specification tests Icc with all power fail circuitry disabled, by setting D7 of Interrupt Control Register 1 to O.
Note 6: This specification tests Icc with all power fail circuitry enabled, by setting D7 of Interrupt Control Register 1 to 1.
Note 7: OSC IN is driven by a signal generator. Contents of the Test Register = OO(H) and the MFO pin is not configured as buffered oscillator out.
1-27
AC Electrical Characteristics
Vcc
= 3.3V ± 10%, Vss = 2.5V, VPFAIL > VIH, CL = 100 pF (unless otherwise specified)
I
Symbol
I
Parameter
READ TIMING
Min
I
Max
I
Units
tAR
Address Valid Prior to Read Strobe
10
tRW
Read Strobe Width (Note 8)
100
ns
tco
Chip Select to Data Valid Time
tRAH
Address Hold after Read (Note 9)
tRo
Read Strobe to Valid Data
90
ns
toz
Read or Chip Select to TRI-STATE
80
ns
tAcH
Chip Select Hold after Read Strobe (Note 9)
0
ns
tos
Minimum Inactive Time between Read or Write Accesses
70
ns
tAW
Address Valid before Write Strobe
10
ns
tWAH
Address Hold after Write Strobe (Note 9)
2
ns
ns
100
ns
2
ns
WRITE TIMING
tcw
Chip Select to End of Write Strobe
110
ns
tww
Write Strobe Width (Note 10)
100
ns
tow
Data Valid to End of Write Strobe
70
ns
tWOH
Data Hold after Write Strobe (Note 9)
2
ns
twcH
Chip Select Hold after Write Strobe (Note 9)
0
ns
INTERRUPT TIMING
I
tROLL
Clock Rollover to INTR Out is Typically 20 !-,-S
I
I
I
Note 8: Read Strobe width as used in the read timing table is defined as the period when both chip select and read inputs are low. Hence read commences when
both signals are low and terminates when either signal returns high.
Note 9: Hold time is guaranteed by design but not production tested. This limit is not used to calculate outgoing quality levels.
Note 10: Write Strobe width as used in the write timing table is defined as the period when both chip select and write inputs are low. Hence write commences when
both signals are low and terminates when either signal returns high.
AC Test Conditions
Input Pulse Levels
Input Rise and Fall Times
Input and Output
Reference Levels
TRI-STATE Reference
Levels (Note 12)
Note 11: CL
Note 12: SI
GNDt03.0V
6 ns (10%-90%)
1.3V
vee
Active High + 0.5V
Active Low -0.5V
""r"
1
pF. includes jig and scope capaCitance.
Vee for active low to high impedance measurements.
GND for active high to high impedance measurements.
open for all other timing measurements.
= 100
=
81 =
81 =
CapaCitance
Symbol
(TA
Input 0---
~
= 25°C, f = 1 MHz)
Parameter
(Note 13)
Typ
Units
CIN
Input Capacitance
5
pF
COUT
Output Capacitance
7
pF
Device
Under
Test
Note 13: This parameter is not 100% tested.
Note 14: Output rise and fall times 25 ns max (10%-90%) with 100 pF load.
1-28
SI (Note 12)
0
*
*
~
:~
.~
Rt. = lK n
:: Output
- - <1(Note 11)
TL/F/I1417-2
Timing Waveforms
Read Timing Diagram
AO-4
~CH
~----------~W----------~·~--~I
DATA
Valid Data
TL/F/11417-3
Write Timing Diagram
AO-4
~-----------~w----------~~
~----------tww----------~
------~--'I
r----~,
/,::tow
DATA
-------------------<~
Valid Data
TL/F/11417-4
II
1-29
«
N
r-Lt)
co
>
...J
General Description
Vee: This is the main system power pin.
GND: This is the common ground power pin for both Vss
and Vee. .
(Continued)
The LV8572A's interrupt structure provides three basic
types of interrupts: Periodic, Alarm/Compare, and Power
Fail. Interrupt mask and status registers enable the masking
and easy determination of each interrupt.
Connection Diagrams
Pin Description
Dual-ln-L1ne
cs,
RD, WR (Inputs): These pins interface to p.P control
lines. The CS pin is an active low enable for the read and
write operations. Read and Write pins are also active low
and ~nable reading or writing to the RTC. All three pins are
disabled when power failure is detected. However, if a read
or write is in progress at this time, it will be allowed to complete its cycle.
cs
24
RD
23
prAll
WR
22
07
21
06
4
AO
AO-A4 (Inputs): These 5 pins are for register selection.
They individually control which location is to be accessed.
These inputs are disabled when power failure is detected.
OSC IN (Input): OSC OUT (Output): These two pins are
used to connect the crystal to the internal parallel resonant
oscillator. The oscillator is always running when power is
applied to Vss and Vee, and the correct crystal select bits in
the Real Time Mode Register have been set.
Vee
Al
05
A2
04
A3
03
A4
02
01
Vee
10
OSC IN
00
OSC OUT
11
INTR
GNO
12
Mro
MFO (Output): The multi-function output can be used as a
second interrupt output for interrupting the p.P. This pin can
also provide an output for the oscillator. The MFO output is
configured as push-pull, active high for normal or single
power supply operation and as an open drain during standby mode (Vss > Vee>. If in battery backed mode and a pullup resistor is attached, it should be connected to a voltage
no greater than Vss.
INTR (Output): The interrupt output is used to interrupt the
processor when a timing event or power fail has occurred
and the respective interrupt has been enabled. The INTR
output is permanently configured active low, open drain. If in
battery backed mode and a pull-up resistor is attached, it
should be connected to a voltage no greater than Vss.
TLlF/11417-5
Top View
Order Number LV8572AN
See NS Package Number N24C
Plastic Chip Carrier
00-07 (Input/Output): These 8 bidirectional pins connect
to the host p.P's data bus and are used to read from and
write to the RTC. When the PFAIL pin goes low and a write
is not in progress, these pins are at TRI-STATE.
PFAIL (Input): In battery backed mode, this pin can have a
digital signal applied to it via some external power detection
logic. When PFAIL = logic 0 the RTC goes into a lockout
mode, in a minimum of 30 p.s or a maximum of 63 p's unless
lockout delay is programmed. In the single power supply
mode, this pin is not useable as an input and should be tied
to Vee. Refer to section on Power Fail Functional Description.
uul~. .
-<
I~ I~ I~ > "-
4
1 28 27
0
u
:z
Al
07
A2
06
A3
05
A4
04
NC
03
NC
10
Vee
11
02
19
!!:
u
VI
0
Vee (Battery Power Pin): This pin is connected to a backup power supply. This power supply is switched to the internal circuitry when the Vee becomes lower than Vss. Utilizing this pin eliminates the need for external logic to switch in
and out the back-up power supply. If this feature is not to be
used then this pin must be tied to ground, the RTC programmed for single power supply only, and power applied to
the Vee pin.
~
=>
0
c
:z
C>
u
:z
...o
::::E
I~
~
!!:
01
0
c
u
VI
0
TL/F/11417-6
Top View
Order Number LV8572A V
See NS Package Number V28A
1-30
r-
<
Functional Description
Q)
U1
The memory map of the RTC is shown in the memory addressing table. The memory map consists of two 31 byte
pages with a main status register that is common to both
pages. A control bit in the Main Status Register is used to
select either page. Figure 2 shows the basic concept.
Page 0 contains all the clock timer functions, while page 1
has scratch pad RAM. The control registers are split into
two separate blocks to allow page 1 to be used entirely as
scratch pad RAM. Again a control bit in the Main Status
Register is used to select either control register block.
Tho LV8572A contains a fast access real time clock, interrupt control logic, power fail detect logic, and CMOS RAM.
All functions of the RTC are controlled by a set of seven
registers. A simplified block diagram that shows the major
functional blocks is given in Figure 1.
The blocks are described in the following sections:
1. Real Time Clock
2. Oscillator Prescaler
3. Interrupt Logic
4. Power Failure Logic
5. Additional Supply Management
.......
I\)
»
Page Select = 0
If'
RAM/TEST Register
1E
RAM
Page Select
If'
RAM
10
Months Time Save RAM
1E
RAM
lC
Day of Month Time Save RAM
10
RAM
lB
Hours Time Save RAM
lC
RAM
lA
Minutes Time Save RAM
lB
RAM
RAM
19
Seconds Time Save RAM
lA
18
Day of Week Compare RAM
19
RAM
17
Months Compare RAM
18
RAM
16
Day of Month Compare RAM
17
RAM
15
Hours Compare RAM
16
RAM
14
Minutes Compare RAM
15
RAM
13
Seconds Compare RAM
14
RAM
12
N/A
13
RAM
11
N/A
12
RAM
10
N/A
11
RAM
RAM
OF
N/A
10
OE
Day of Week Clock Counter
Of'
RAM
00
100's Julian Clock Counter
OE
RAM
OC
Units Julian Clock Counter
00
RAM
OB
Years Clock Counter
OC
RAM
OA
Months Clock Counter
OB
RAM
09
Day of Month Clock Cou nter
OA
RAM
08
Hours Clock Counter
09
RAM
07
Minutes Clock Counter
08
RAM
06
Seconds Clock Counter
07
RAM
06
RAM
05
Yl00
Second Counter
' " R.,,,,,, 5.,,,, "1
R.,;"" 5.1"," 0/
05
RAM
04
RAM
RAM
RAM
04
Interrupt Control Register 1
03
02
Periodic Flag Register
03
Interrupt Control Register 0
01
N/ A
02
Output Mode Register
Time Save Control Register
N_~
=1
RAM
R.e.alllll(~i~m~e.M.o.de_R~
..
A_ _ _ _ _.O.l_ _
00
I
-
Main Status Register
FIGURE 2. LV8572A Internal Memory Map
1-31
TL/F/11417-7
•
<
N
.....
an
ClO
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Functional Description
(Continued)
Save Enable bit (07) of the Time Save Control Register, and
then to write a zero. Writing a one into this bit will enable the
clock contents to be duplicated in the Time Save RAM.
Changing the bit from a one to a zero will freeze and store
the contents of the clock in Time Save RAM. The time then
can be read without concern for clock rollover, since internal logic takes care. of synchronization of the clock. Because only the bits used by the clock counters will be
latched, the Time Save RAM should be cleared prior to use
to ensure that random data stored in the unused bits do not
confuse the host microprocessor. This bit can also provide
time save at power failure, see the Additional Supply Management Functions section. With the Time Save Enable bit
at a logical 0, the Time Save RAM may be used as RAM if
the latched read function is not necessary.
INITIAL POWER-ON of BOTH Vee and Vee
Vss and Vee may be applied in any sequence. In order for
the power fail circuitry to function correctly, whenever power
is off, the Vee pin must see a path to ground through a
maximum of 1 Mn. The user should be aware that the control registers will contain random data. The first task to be
carried out in an initialization routine is to start the oscillator
by writing to the crystal select bits in the Real Time Mode
Register. If the LV8572A is configured for single supply
mode, an extra 50 ,..,A may be consumed until the crystal
select bits are programmed. The user should also ensure
that the RTC is not in test mode (see register descriptions).
REAL TIME CLOCK FUNCTIONAL DESCRIPTION
As shown in Figure 2, the clock has 10 bytes of counters,
which count from 1/100 of a second to years. Each counter
counts in BCD and is synchronously clocked. The count sequence of the individual byte counters within the clock is
shown later in Table VII. Note that the day of week, day of
month, day of year, and month counters all roll over to 1.
The hours counter in 12 hour mode rolls over to 1 and the
AM/PM bit toggles when the hours rolls over to 12
(AM = 0, PM = 1). The AM/PM bit is bit 07 in the hours
counter.
INITIALIZING AND WRITING TO THE
CALENDAR-CLOCK
Upon initial application of power to the RTC or when making
time corrections, the time must be written into the clock. To
correctly write the time to the counters, the clock would
normally be stopped by writing the Start/Stop bit in the Real
Time Mode Register to a zero. This stops the clock from
counting and disables the carry circuitry. When initializing
the clock's Real Time Mode Register, it is recommended
that first the various mode bits be written while maintaining
the Start/Stop bit reset, and then writing to the register a
second time with the Start/Stop bit set.
All other counters roll over to O. Also note that the day of
year counter is 12 bits long and occupies two addresses.
Upon initial application of power the counters will contain
random information.
The above method is useful when the entire clock is being
corrected. If one location is being updated the clock need
not be stopped since this will reset the prescaler, and time
will be lost. An ideal example of this is correcting the hours
for daylight savings time. To write to the clock "on the fly"
the best method is to wait for the 1/100 of a second periodic interrupt. Then wait an additional 16 ,..,S, and then write
the data to the clock.
READING THE CLOCK: VALIDATED READ
Since clocking of the counter occurs asynchronously to
reading of the counter, it is possible to read the counter
while it is being incremented (rollover). This may result in an
incorrect time reading. Thus to ensure a correct reading of
the entire contents of the clock (or that part of interest), it
must be read without a clock rollover occurring. In general
this can be done by checking a rollover bit. On this chip the
periodic interrupt status bits can serve this function. The
following program steps can be used to accomplish this.
PRESCALER/OSCILLATOR FUNCTIONAL
DESCRIPTION
Feeding the counter chain is a programmable prescaler
which divides the crystal oscillator frequency to 32 kHz and
further to 100 Hz for the counter chain (see Figure (3). The
crystal frequency that can be selected are: 32 kHz, 32.768
kHz, 4.9152 MHz, and 4.194304 MHz.
1. Initialize program for reading clock.
2. Dummy read of periodic status bit to clear it.
3. Read counter bytes and store.
4. Read rollover bit, and test it.
5. If rollover occured go to 3.
6. If no rollover, done.
To detect the rollover, individual periodic status bits can be
polled. The periodic bit chosen should be equal to the highest frequency counter register to be read. That is if only
SECONDS through HOURS counters are read, then the
SECONDS periodic bit should be used.
READING THE CLOCK: INTERRUPT DRIVEN
Enabling the periodic interrupt mask bits cause interrupts
just as the clock rolls over. Enabling the desired update rate
and providing an interrupt service routine that executes in
less than 10 ms enables clock reading without checking for
a rollover.
TL/F/11417-B
FIGURE 3. Programmable Clock Prescaler Block
READING THE CLOCK: LATCHED READ
Another method to read the clock that does not require
checking the rollover bit is to write a one into the Time
1-32
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<
Functional Description
C)
(Continued)
The oscillator is programmed via the Real Time Mode Register to operate at various frequencies. The crystal oscillator
is designed to offer optimum performance at each frequency. Thus, at 32.768 kHz the oscillator is configured as a low
frequency and low power oscillator. At the higher frequencies the oscillator inverter is reconfigured. In addition to the
inverter, the oscillator feedback bias resistor is included on
chip, as shown in Figure 4. The oscillator input may be driven from an external source if desired. Refer to test mode
application note for details. The oscillator stability is enhanced through the use of an on chip regulated power supply.
The typical range of trimmer capacitor (as shown in Oscillator Circuit Diagram Figure 4, and in the typical application) at
the oscillator input pin is suggested only to allow accurate
tuning of the oscillator. This range is based on a typical
printed circuit board layout and may have to be changed
depending on the parasitic capacitance of the printed circuit
board or fixture being used. In all cases, the load capacitance specified by the crystal manufacturer (nominal value
11 pF for the 32.768 crystal) is what determines proper oscillation. This load capcitance is the series combination of
capacitance on each side of the crystal (with respect to
ground).
U1
INTERRUPT LOGIC FUNCTIONAL DESCRIPTION
TABLE I. Registers that are
Applicable to Interrupt Control
Register Name
Main Status Register
Periodic Flag Register
Interrupt Control
Register 0
Interrupt Control
Register 1
Output Mode
Register
Prescaler
External
Components
X
0
X
0
OOH
03H
1
0
03H
1
0
04H
1
0
02H
Disabling the periodic interrupts will mask the Main Status
Register periodic bit, but not the Periodic Flag Register bits.
The Power Fail Interrupt bit is set when the interrupt is enabled and a power fail event has occurred, and is not reset
until the power is restored. If all interrupt enable bits are 0
no interrupt will be asserted. However, status still can be
read from the Main Status Register in a polled fashion (see
Figure 5).
TL/F/11417-9
FIGURE 4. Oscillator Circuit Diagram
47 pF 2 pF-22 pF
68 pF o pF-80 pF
68 pF 29 pF-49 pF
Address
These register bits will be set when their associated timing
events occur. Enabled Alarm comparisons that· occur will
set its Main Status Register bit to a one. However, an external interrupt will only be generated if the Alarm interrupt
enable bit is set (see Figure 5).
Pin
XTAL
32/32.768 kHz
4.194304 MHz
4.9152 MHz
Page
Select
Status for the interrupts are provided by the Main Status
Register and the Periodic Flag Register. Bits 01-05 of the
Main Status Register are the main interrupt bits.
OSC OUT
Ct
Register
Select
The Interrupt Status Flag DO, in the Main Status Register,
indicates the state of INTR and MFO outputs. It is set when
either output becomes active and is cleared when all RTC
interrupts have been cleared and no further interrupts are
pending (Le., both INTR and MFO are returned to their inactive state). This flag enables the RTC to be rapidly polled by
the J-tP to determine the source of an interrupt in a wiredOR interrupt system. (The Interrupt Status Flag provides a
true reflection of all conditions routed to the external pins.)
To
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»
The interrupts are enabled by writing a one to the appropriate bits in Interrupt Control Register 0 and/or 1.
Internal Components
XTAL
N
The RTC has the ability to coordinate processor timing activities. To enhance this, an interrupt structure has been implemented which enables several types of events to cause
interrupts. Interrupts are controlled via two Control Registers in block 1 and two Status Registers in block O. (See
Register Description for notes on paging and also A'gure 5
and Table I.)
v+
t---~nl----'
.......
ROUT
(Switched
Internally)
To clear a flag in bits 02 and 03 of the Main Status Register
a 1 must be written back into the bit location that is to be
cleared. For the Periodic Flag Register reading the status
will reset all the periodic flags.
150 kn to 350 kn
500n to 900n
500n to 900n
1-33
•
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"-
Functional Description
co
Interrupts Fall Into Three Categories:
Lt)
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(Continued)
Figure 5. These flags constantly sense the periodic signals
and may be used whether or not interrupts are enabled .
These flags are cleared by any read or write operation performed on this register.
1. The Alarm Compare Interrupt: Issued when the value in
the time compared RAM equals the counter.
2. The Periodic Interrupts: These are issued at every increment of the specific clock counter signal. Thus, an interrupt is issued every minute, second, etc. Each of these
interrupts occurs at the roll-over of the specific counter.
To generate periodic interruptsat the desired rate, the associated Periodic Interrupt Enable bit in Interrupt Control Register 0 must be set. Any combination of periodic interrupts
may be enabled to operate simultaneously. Enabled periodic interrupts will now affect the Periodic Interrupt Flag in the
Main Status Register.
3. The Power Fail Interrupt: Issued upon recognition of a
power fail condition by the internal sensing logic. The
power failed condition is determined by the signal on the
PFAIL pin. The internal power fail signal is gated with the
chip select signal to ensure that the power fail interrupt
does not lock the chip out during a read or write.
When a periodic event occurs, the Periodic Interrupt Flag in
the Main Status Register is set, causing an interrupt to be
generated. The p.P clears both flag and interrupt by writing a
"1" to the Periodic Interrupt Flag. The individual flags in the
periodic Interrupt Flag Register do not require clearing to
cancel the interrupt.
ALARM COMPARE INTERRUPT DESCRIPTON
The alarm/time comparison interrupt is a special interrupt
similar to an alarm clock wake up buzzer. This interrupt is
generated when the clock time is equal to a value programmed into the alarm compare registers. Up to six bytes
can be enabled to perform alarm time comparisons on the
counter chain. These six bytes, or some subset thereof,
would be loaded with the future time at which the interrupt
will occur. Next, the appropriate bits in the Interrupt Control
Register 1 are enabled or disabled (refer to detailed description of Interrupt Control Register 1). The RTC then compares these bytes with the clock time. When all the enabled
compare registers equal the clock time an alarm interrupt is
issued, but only if the alarm compare interrupt is enabled
can the interrupt be generated externally. Each alarm compare bit in the Control Register will enable a specific byte for
comparison to the clock. Disabling a compare byte is the
same as setting its associated counter comparator to an
"always equal" state. For example, to generate an interrupt
at 3:15 AM of every day, load the hours compare with 0 3
(BCD), the minutes compare with 1 5 (BCD) and the faster
counters with 0 0 (BCD), and then disable all other compare
registers. So every day when the time rolls over from
3:14:59.99, an interrupt is issued. This bit may be reset by
writing a one to bit 03 in the Main Status Register at any
time after the alarm has been generated.
If all periodic interrupts are disabled and a periodic interrupt
is left pending (Le., the Periodic Interrupt Flag is still set), the
Periodic Interrupt Flag will still be required to be cleared to
cancel the pending interrupt.
POWER FAIL INTERRUPTS DESCRIPTION
The Power Fail Status Flag in the Main Status Register
monitors the state of the internal power fail signal. This flag
may be interrogated by the p.P, but it cannot be cleared; it is
cleared automatically by the RTC when system power is
restored. To generate an interrupt when the power fails, the
Power Fail Interrupt Enable bit in Interrupt Control Register
1 is set. Although this interrupt may not be cleared, it may
be masked by clearing the Power Fail Interrupt Enable bit.
POWER FAILURE CIRCUITRY FUNCTIONAL
DESCRIPTION
Since the clock must be operated from a battery when the
main system supply has been turned off, the LV8572A provides circuitry to simplify design in battery backed systems.
This switches over to the back up supply, and isolates itself
from the host system. Figure 6 shows a simplified block
diagram of this circuitry, which consists of three major sections; 1) power loss logic: 2) battery switch over logic: and 3)
isolation logic.
If time comparison for an individual byte counter is disabled,
that corresponding RAM location can then be used as general purpose storage.
Detection of power loss occurs when PFAIL is low. Debounce logic provides a 30 p.s-63 p.s debounce time, which
will prevent noise on the PFAIL pin from being interpreted
as a system failure. After 30 p.s-63 P.s the debounce logic
times out and a signal is generated indicating that system
power is marginal and is failing. The Power Fail Interrupt will
then be generated.
PERIODIC INTERRUPTS DESCRIPTION
The Periodic Flag Register contains six flags which are set
by real-time generated "ticks" at various time intervals, see
1-34
."
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Interrupt Control Registers
Main Status
Register
~
Interrrupt Control
Register
C
CD
Output Mode
Register
Control
Bit
Real
Time
Periodic
Pulse
Signals
(also to
Periodic
Flags)
(f)
(")
..,
-
-0'
0'
:J
oo
~
MFO Output
---.
S"
I::
CD
Output
Buffer
-"
c.,
01
.3:
Interrupt
Mode
Selected
Alarm
Compare
Signals
Power
Fail
Detect
INTR Output
~
Output
Buffer
TL/F/11417-10
FIGURE 5. Interrupt Control Logic Overview
VlLSSA1
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Functional Description
(Continued)
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Battery Switchover
Vas
Vee
II ~f
V+
•
30 uS
Delay
Power
Fail Logic
prAll:::'
(External
power fail
signal)
I 30-63 uS l
I
Debounce
Delay
I
1480 uS
Delay
t
~
Lockout
Delayed
Lockout
MUX
~
Delay
Enable
Data
Address
and
Control
Buffers
,
8/ ...
I
5,
I
... 00:07
AO:A4
3,
1---
CS,RD,WR
TLIF/11417-11
FIGURE 6. System-Battery Switchover (Upper Left), Power Fail
and Lock-Out Circuits (Lower Right)
If chip select is low when a power failure is detected, a
safety circuit will ensure that if a read or write is held active
continuously for greater than 30 !-,-S after the power fail sig·
nal is asserted, the lock-out will be forced. If a lock-out delay
is enabled, the LV8572A will remain active for 480 !-,-S after
power fail is detected. This will enable the !-,-P to perform
last minute bookkeeping before total system collapse.
When the host CPU is finished accessing the RTC it may
force the bus lock-out before 480 !-'-S has elapsed by reset·
ting the delay enable bit.
resistor should be connected to a voltage no greater than
Vss·
TABLE II. Pin Isolation during a Power Failure
The battery switch over circuitry is completely independent
of the PFAIL pin. A separate circuit compares Vee to the
Vss voltage. As the main supply fails, the RTC will continue
to operate from the Vee pin until Vee falls below the Vss
voltage. At this time, the battery supply is switched in, Vee is
disconnected, and the device is now in the standby mode. If
indeterminate operation of the battery switch over circuit is
to be avoided, then the voltage at the Vee pin must not be
allowed to equal the voltage at the Vss pin.
After the generation of a lock·out signal, and eventual
switch in of the battery supply, the pins of the RTC will be
configured as shown in Table II. Outputs that have a pull·up
Pin
PFAIL =
Logic 0
CS,RO,WR
AO-A4
00-07
Oscillator
PFAIL
INTR, MFO
Locked Out
Locked Out
Locked Out
Not Isolated
Not Isolated
Not Isolated
Standby Mode
Vee> Vee
Locked Out
Locked Out
Locked Out
Not Isolated
Not Isolated
Open Drain
The Interrupt Power Fail Operation bit in the Real-Time
Mode Register determine whether or not the interrupts will
continue to function after a power fail event.
As power returns to the system, the battery switch over circuit will switch back to Vee power as soon as it becomes
greater than the battery voltage. The chip will remain in the
locked out state as long as PFAIL = o. When PFAIL = 1
1-36
Functional Description
(Continued)
the chip is unlocked, but only after another 30 J.Ls min ~
63 J.Ls max debounce time. The system designer must ensure that his system is stable when power has returned.
This complete address space is organized into two pages.
Page 0 contains two blocks of control registers, timers, real
time clock counters, and special purpose RAM, while page
1 contains general purpose RAM. Using two blocks enables
the 9 control registers to be mapped into 5 locations. The
only register that does not get switched is the Main Status
Register. It contains the page select bit and the register
select bit as well as status information.
The power fail circuitry contains active linear circuitry that
draws supply current from VCC. In some cases this may be
undesirable, so this circuit can be disabled by masking the
power fail interrupt. The power fail input can perform all
lock-out functions previously mentioned, except that no external interrupt will be issued. Note that the linear power fail
circuitry is switched off automatically when using Vss in
standby mode.
A memory map is shown in Figure 2 and register addressing
in Table III. They show the name, address and page locations for the LV8572A.
LOW BATTERY, INITIAL POWER ON DETECT, AND
POWER FAIL TIME SAVE
TABLE III. Register/Counter/RAM
Addressing for LV8572A
There are three other functions provided on the LV8572A to
ease power supply control. These are an initial Power On
detect circuit, which also can be used as a time keeping
failure detect, a low battery detect circuit, and a time save
on power failure.
AO-4
PS
RS
(Note 1) (Note 2)
Description
CONTROL REGISTERS
00
03
04
01
02
03
04
On initial power up the Oscillator Fail Flag will be set to a
one and the real time clock start bit reset to a zero. This
indicates that an oscillator fail event has occurred, and time
keeping has failed.
The Oscillator Fail flag will not be reset until the real-time
clock is started. This allows the system to discriminate between an initial power-up and recovery from a power failure.
If the battery backed mode is selected, then bit 06 of the
Periodic Flag Register must be written low. This will not affect the contents of the Oscillator Fail Flag.
X
X
0
0
0
0
0
0
0
0
1
1
1
1
Main Status Register
Periodic Flag Register
Time Save Control Register
Real Time Mode Register
Output Mode Register
Interrupt Control Register 0
Interrupt Control Register 1
COUNTERS (CLOCK CALENDAR)
Another status bit is the low battery detect. This bit is set
only when the clock is operating under the VCC pin, and
when the battery voltage is determined to be less than 2.1 V
(typical). When the power fail interrupt enable bit is low, it
disables the power fail circuit and will also shut off the low
battery voltage detection circuit as well.
05
06
07
08
09
0
0
0
0
0
X
X
X
X
X
OA
OS
OC
00
OE
0
0
0
0
0
X
X
X
X
X
1/100, 1/10 Seconds (0-99)
(0-59)
Seconds
(0-59)
Minutes
(1-12,0-23)
Hours
Days of
Month
(1-28/29/30/31 )
(1-12)
Months
(0-99)
Years
Julian Date (LSS)
(1-99)
(0-3)
Julian Date
(1-7)
Day of Week
TIME COMPARE RAM
To relieve CPU overhead for saving time upon power failure,
the Time Save Enable bit is provided to do this automatically. (See also Reading the Clock: Latched Read.) The Time
Save Enable bit, when set, causes the Time Save RAM to
follow the contents of the clock. This bit can be reset by
software, but if set before a power failure occurs, it will automatically be reset when the clock switches to the battery
supply (not when a power failure is detected by the PFAIL
pin). Thus, writing a one to the Time Save bit enables both a
software write or power fail write.
13
14
15
0
0
0
X
X
X
16
0
X
17
0
X
18
0
X
Sec Compare RAM
Min Compare RAM
Hours Compare
RAM
DOMCompare
RAM
Months Compare
RAM
DOW Compare RAM
(0-59)
(0-59)
(1-12, 0-23)
(1-28/29/30/31 )
(1-12)
(1-7)
TIME SAVE RAM
19
1A
1S
1C
10
0
0
0
0
0
X
X
X
X
X
Seconds Time Save RAM
Minutes Time Save RAM
Hours Time Save RAM
Day of Month Time Save RAM
Months Time Save RAM
1E
1F
0
0
1
X
RAM
RAMITest Mode Register
01-1F
1
X
2nd Page General Purpose RAM
SINGLE POWER SUPPLY APPLICATIONS
The LV8572A can be used in a single power supply application. To achieve this, the Vss pin must be connected to
ground, and the power connected to VCC and PFAIL pins.
The Oscillator Failed/Single Supply bit in the Periodic Flag
Register should be set to a logic 1, which will disable the
oscillator battery reference circuit. The power fail interrupt
should also be disabled. This will turn off the linear power
fail detection circuits, and will eliminate any quiescent power
drawn through these circuits. Until the crystal select bits are
initialized, the LV8572A may consume about 50 J.LA due to
arbitrary oscillator selection at power on.
1
2
(This extra 50 J.LA is not consumed if the battery backed
mode is selected).
DETAILED REGISTER DESCRIPTION
There are 5 external address bits: Thus, the host microprocessor has access to 28 locations at one time. An internal
switching scheme provides a total of 61 locations.
1-37
PS-Page Select (Bit 07 of Main Status Register)
RS-Register Select (Bit 06 of Main Status Register)
c:r:
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.....
an
>
....I
Functional Description
(Continued)
ClC)
The Periodic Flag Register has the same bit for bit correspondence as Interrupt Control Register 0 except for 06
and 07. For normal operation (Le., not a single supply application) this register must be written to on initial power up or
after an oscillator fail event. 00-05 are read only bits, 06
and 07 are read/write.
00-05: These bits are set by the real time rollover events:
(Time Change = 1). The bits are reset when the register is
read and can be used as selective data change flags.
MAIN STATUS REGISTER
I
PS
I
RS
I
R
R
I All PER I
PF
I INTI
IL:
DO Interrupt Status
01 Power Fail Interrupt
02 Period Interrupt
03 Alarm Interrupt
04 RAIA
05 RAIA
06 Register Select Bit
06: This bit }Jerforms a dual function. When this bit is read, a
one indicates that an oscillator failure has occurred and the
time information may have been lost. Some of the ways an
oscillator failure might be caused are: failure of the crystal,
shorting OSC IN or OSC OUT to GNO or Vee, removal of
crystal, removal of battery when in the battery backed mode
(when a "0" is written to 06), lowering the voltage at the
Vss pin to a value less than 2.2V when in the battery
backed mode. Bit 06 is automatically set to 1 on initial power-up or an oscillator fail event. The oscillator fail flag is
reset by writing a one to the clock start/stop bit in the Real
Time Mode Register, with the crystal oscillating.
07 Page Select Bit
TLlF/11417-12
The Main Status Register is always located at address 0
regardless of the register block or the page selected.
DO: This read only bit is a general interrupt status bit that is
taken directly from the interrupt pins. The bit is a one when
an interrupt is pending on either the INTR pin or the MFO
pin (when configured as an interrupt). This is unlike 03
which can be set by an internal event but may not cause an
interrupt. This bit is reset when the interrupt status bits in the
Main Status Register are cleared.
When 06 is written to, it defines whether the TCP is being
used in battery backed (normal) or in a single supply mode
application. When set to a one this bit configures the TCP
for single power supply applications. This bit is automatically
set on initial power-up or an oscillator fail event. When set,
06 disables the oscillator reference circuit. The result is that
the oscillator is referenced to Vee. When a zero is written to
06 the oscillator reference is enabled, thus the oscillator is
referenced to Vss. This allows operation in standard battery
standby applications.
At initial power on, if the LV8572A is going to be pro. grammed for battery backed mode, the Vss pin should be
connected to a potential in the range of 2.2V to Vee O.4V.
01-03: These three bits of the Main Status Register are the
main interrupt status bits. Any bit may be a one when any of
the interrupts are pending. Once an interrupt is asserted the
JLP will read this register to determine the cause. These
interrupt status bits are not reset when read. Except for 01,
to reset an interrupt a one is written back to the corresponding bit that is being tested. 01 is reset whenever the PFAIL
pin = logic 1. This prevents loss of interrupt status when
reading the register in a polled mode. 01 and 03 are set
regardless of whether these interrupts are masked or not by
bits 06 and 07 of Interrupt Control Registers 0 and 1.
04-05: General purpose RAM bits.
06 and 07: These bits are Read/Write bits that control
which register block 'or RAM page is to be selected. Bit 06
controls the register block' to be accessed (see memory
map). The memory map of the clock is further divided into
two memory pages. One page is the registers, clock and
timers, and the second page contains 31 bytes of general
purpose RAM. The page selection is determined by bit 07.
For single supply mode operation, the Vss pin should be
connected to GNO and the PFAIL pin connected to Vee.
07: Writing a one to this bit enables the test mode register
at location 1F (see Table III). This bit should be forced to
zero during initialization for normal operation. If the test
mode has been entered, clear the test mode register before
leaving test mode. (See separate test mode application
note for further details.)
PERIODIC FLAG REGISTER
n.
osr
lms
10ms 100msl Is 110.
1 min
I
I L=
DO minute. flag.
TIME SAVE CONTROL REGISTER
Dl 10 .econd flag
I
D2 .econds flag
D3 100 millis.c. flag
TS
I
lB
PFO
R I R
R
R
I
L- DO
R
I
D4 10 millisoc. flag
D5 milli-.econds flag
RAIA
01 RAIA
02 RAIA
D6 Oscillator railed/Single Supply Bit
03 RAIA
D7 Test lAode Enabl.
04 RAIA
TL/F/11417-13
05 PF Delay Enable
06 low Battery fl8g
07 Time Save Enable
TL/F/11417-14
00-04: General purpose RAM bits.
1-38
Functional Description
(Continued)
05: The Delay Enable bit is used when a power fail occurs.
02: The count mode for the hours counter can be set to
either 24 hour mode or 12 hour mode with AM/PM indicator.
A one will place the clock in 12 hour mode.
If this bit is set, a 480 JJ.s delay is generated internally before
the JJ.P interface is locked out. This will enable the JJ.P to
access the registers for up to 480 JJ.s after it receives a
power fail interrupt. After a power failure is detected but
prior to the 480 JJ.s delay timing out, the host JJ.P may force
immediate lock out by resetting the Delay Enable bit. Note if
this bit is a 0 when power fails then after a delay of 30 JJ.s
min/63 JJ.s max the JJ.P cannot read the chip.
03: This bit is the master Start/Stop bit for the clock. When
a one is written to this bit the real time counter's prescaler
and counter chain are enabled. When this bit is reset to zero
the contents of the real time counter is stopped and the
prescaler is cleared. When the RTC is initially powered up
this bit will be held at a logic 0 until the oscillator starts
functioning correctly after which this bit may be modified. If
an oscillator fail event occurs, this bit will be reset to logic O.
06: This read only bit is set and reset by the voltage at the
VBB pin. It can be used by the JJ.P to determine whether the
battery voltage at the VBB pin is getting too low. A comparator monitors the battery and when the voltage is lower than
2.1 V (typical) this bit is set. The power fail interrupt must be
enabled to check for a low battery voltage.
04: This bit controls the operation of the interrupt output in
standby mode. If set to a one it allows Alarm, Periodic, and
Power Fail interrupts to be functional in standby mode. Note
that the MFa pin is configured as open drain in standby
mode..
07: Time Save Enable bit controls the loading of real-timeclock data into the Time Save RAM. When a one is written
to this bit the Time Save RAM will follow the corresponding
clock registers, and when a zero is written to this bit the time
in the Time Save RAM is frozen. This eliminates any synchronization problems when reading the clock, thus negating the need to check for a counter rollover during a read
cycle.
If bit D4 is set to a zero then interrupt control register and
the periodic interrupt flag will be reset when the RTC enters
the standby mode (VBB > Ved. They will have to be reconfigured when system (Ved power is restored.
05: General purpose RAM.
06 and 07: These two bits select the crystal clock frequency as per the following table:
This bit must be set to a one prior to power failing to enable
the Time Save feature. When the power fails this bit is automatically reset and the time is saved in the Time Save RAM.
REAL TIME MOOE REGISTER
IXTlIXTOI R I IPFIcssI12HILYlILYOI
L
DO Leap Year LSB
01 Leap Year MSB
02 12(24 hour mode
XT1
XTO
Crystal
Frequency
0
0
1
1
0
1
0
1
32.768 kHz
4.194304 MHz
4.9152 MHz
32.000 kHz
All bits are Read/Write, and any mode written into this register can be determined by reading the register. On initial
power up these bits are random.
03 Clock Start,lSiOj)
04 Interrupt PF Operation
05 RAM
OUTPUT MOOE REGISTER
06 Crystal Frequency LSB
I 1.40 I R I R I R I R I R I R I R I
L
07 Crystal Frequency MSB
TLIF/11417-15
DO RAM
01 RAM
02 RAM
00-01: These are the leap year counter bits. These bits are
written to set the number of years from the previous leap
year. The leap year counter increments on December 31st
and it internally enables the February 29th counter state.
This method of setting the leap year allows leap year to
occur whenever the user wishes to, thus providing flexibility
in implementing Japanese leap year function.
03 RAM
04 RAM
05 RAM
06 RAM
07 MFO Pin as Oscillator
LY1
LYO
Leap Year
Counter
0
0
1
1
0
1
0
1
Leap Year Current Year
Leap Year Last Year
Leap Year 2 Years Ago
Leap Year 3 Years Ago
TLIF/11417-16
00-06: General Purpose RAM
II
1-39
Functional Description
(Continued)
07: This bit is used to program the signal appearing at the
MFO output, as follows:
07
MFO Output Signal
o
Power Fail Interrupt
Buffered Crystal Oscillator
1
INTERRUPT CONTROL REGISTER 1
IL
I pre I Ale I ootoll tolO lootoll HR I tolN I sc I
.'
R
I
R 11 m I tm
L
, ..bI,
~: ~:::t:o::~:r:n:nb::le
' - - - - - - - - 04 Month compare enable
I hm I SITS I MN I
I
S.~,d ~mp'"
' - - - - - - - 03 Day of month enable
INTERRUPT CONTROL REGISTER 0
I
DO
.....- - - - - - - 05 Day of week enable
00 Minutes enable
L - 01
.....- - - - - - - - - 06 Alarm Interrupt enable
L...________________
10 second enable
a comparison between an individual clock counter and its
associated compare RAM. If any bit is a zero then that
clock-RAM comparator is set to the "always equal" state
and the associated TIME COMPARE RAM byte can be used
as general purpose RAM. However, to ensure that an alarm
interrupt is not generated at bit 03 of the Main Status Register, all bits must be written to a logiC zero.
' - - - - - - - - 04 10 millisec enable
.....- - - - - - - - 05 millisec enable
RAM
'-----------------------07
RAM
Power fail interrupt enable
00-05: Each ofthese bits are enable bits which will enable
.....- - - - - 03 100 millisec enable
'-----------~-----06
07
TL/F/11417-18
' - - - - - 02 Seconds enable
· TL/F/11417-17
DO-05: These bits are used to enable one of the selected
06: In order to generate an external alarm compare interrupt to the ILP from bit 03 of the Main Status Register, this
bit must be written to a logic 1. If battery backed mode is
selected then this bit is controlled by 04 of the Real Time
Mode Register.
periodic interrupts by writing a one into the appropriate bit.
These interrupts are issued at the rollover of the clock. For
example, the minutes interrupt will be issued whenever the
minutes counter increments. In all likelihood the interrupt
will be enabled asynchronously with the real time change.
Therefore, the very first interrupt will occur in less than the
periodic time chosen, but after the first interrupt all subsequent interrupts will be spaced correctly. These interrupts
are u:seful when minute, second, real time reading, or task
switching is required. When all six bits are written to a 0 this
disables periodic interrupts from the Main Status Register
and the interrupt pin.
07: The MSB of this register is the enable bit for the Power
Fail Interrupt. When this bit is set to a one an interrupt will
be generated to the ILP when Vss > Vee. If battery backed
mode is selected then this bit is controlled by 04 of the Real
Time Mode Register.
This bit also enables the low battery detection analog circuitry.
D6 and 07: General Purpose RAM.
1-40
r<
co
Control and Status Register Address Bit Map
07
06
05
Main Status Register PS = X
R/W
R/W
04
RS = X
R/W
03
U1
......
02
ADDRESS = OOH
R/W
R/W1
01
N
DO
1. Reset by
writing
1 to bit.
R/W1
»
2. Set/reset by
voltage at
PFAILpin.
3. Reset when
all pending
interrupts
are removed.
Periodic Flag Register PS = 0
R/W
RS
=0
RS
R/W4
Address
RS
=
03H
RS
4. Read Osc fail
Write 0 BattBacked Mode
Write 1 Single
Supply Mode
RS
5. Reset by
positive edge
of read.
RS = 0
Time Save Control Register PS = 0
R/W
Time Save
Enable
Address = 04H
R6
R/W
R/W
R/W
R/W
R/W
R/W
Low Battery
Flag
Power Fail
Delay
Enable
RAM
RAM
RAM
RAM
RAM
6. Set and reset
RS = 1
byVss
voltage.
Address = 01 H
All BitsR/W
RS = 1
Output Mode Register PS = 0
Address = 02H
l
_M.....:F:....o_a_s-LI
__R_A_M_-lI__R_A_M_--L__R_A_M_--1-__
R_A_M_....l-_R_A_M_--L__R_A_M_--1-__
R_A_M----I1. All Bits R/W
Crystal
Interrupt Control Register 0 PS = 0
RAM
RAM
1 ms
Interrupt
Enable
Interrupt Control Register 1 PS = 0
Power Fail
Interrupt
Enable
Alarm
Interrupt
Enable
DOW
Interrupt
Enable
RS = 1
10 ms
Interrupt
Enable
RS = 1
Month
Interrupt
Enable
Address = 03H
100 ms
Interrupt
Enable
Seconds
Interrupt
Enable
10 Second
Interrupt
Enable
Minute
Interrupt
Enable
All BitsR/W
Minute
Interrupt
Enable
Second
Interrupt
Enable
All Bits R/W
Address = 04H
DOM
Interrupt
Enable
Hours
Interrupt
Enable
III
1-41
..J
Application Hints
Suggested Initialization Procedure for LV8572A in Battery
Backed Applications that use the VBB Pin .
main the same as in step 1. Under normal operation, this
bit can be set only if the oscillator is running. During the
software loop, RAM, real time counters, output configuration,. interrupt control and timer functions may be initialized.
1. Enter the test mode by writing a 1 to bit 07 in the Periodic Flag Register.
2. Write zero to the RAM/TEST mode Register located in
page 0, address HEX 1 F.
3.
6. Test bit 06 in the Periodic Flag Register:
IF a 1, go to 5.1. If this bit remains a 1 after 3 seconds,
then abort and check hardware. The crystal may be defective or not installed. There may be a short at OSC IN
or OSC OUT to Vee or GNO, or to some impedance that
is less than 10 MO.
Leave the test mode by writing a 0 to bit 07 in the Periodic Flag Register. Steps 1 ,2,3 guarantee that if the test
mode had been entered during power on (due to random pulses from the system), all test mode conditions
are cleared. Most important is that the OSC Fail Disable
bit is cleared. Refer to AN-589 for more information on
test mode operation.
IF a 0, then the oscillator is running, go to step 7.
7. Write a 0 to bit 06 in the Periodic Flag Register. This
action puts the clock chip in the battery backed mode.
This mode can be entered only if the OSC fail flag (bit
06 of the Periodic Flag Register) is a O. Reminder, Bit
06 is a dual function bit. When read, 06 returns oscillator status. When written, 06 causes either the Battery
Backed Mode, or the Single Supply Mode of operation.
4. After power on (Vee and VBB powered), select the correct crystal frequency bits (07, 06 in the Real Time
Mode Register) as shown in Table IV.
TABLE IV
07
06
32.768 kHz
0
0
4.194304 MHz
0
1
4.9152 MHz
1
0
32.0 kHz
1
1
Frequency
Set a 3 second(approx) software counter. The crystal
oscillator may take 1 second to start.
The only method to ensure the chip is in the battery
backed mode is to measure the waveform at the OSC
OUT pin. If the battery backed mode was selected successfully, then the peak to peak waveform at OSC OUT
is referenced to the battery voltage. If not in battery
backed mode, the waveform is referenced to Vee. The
measurement should be made with a high impedance
low· capacitance probe (10 MO, 10 pF oscilloscope
probe or better). Typical peak to peak swings are within
0.6V, of Vee and ground respectively.
5.1 Write a 1 to bit 03 in the Real Time Mode Register (try
to start the clock). Make sure the crystal select bits re-
8. Write a 1 to bit 07 of Interrupt Control Register 1. This
action enables the PFAIL pin and associated circuitry.
5. Enter a software loop that does the following:
9.
Typical Application
....
o
I/)
I/)
Initialize the rest of the chip as needed.
01·
Rl·
Main Supply
8attery Supply
A low going user
generated power
fail signal should
be presented 10 the
PFAIL pin .
"I"'-=~--'IJI
AO-A4
LV8572A
Real Time
Clock
Q)
o
o
....a.
....o
.:::::E~
osc
IN
OSC OUT
1---_-..
2-22 pF
32.768KHz
T
47 PF
MFO
GNo
TLlF/11417-19
·These components may be necessary to meet UL requirements
for lithium batteries. Consult battery manufacturer.
1-42
Typical Performance Characteristics
Operating Current vs
.Supply Voltage
(Battery Backed Mode
Fosc = 32.768 kHz,
Operating Current vs
Supply Voltage
(Single Supply Mode
Fosc = 32.768 kHz)
VBB = 2.5V)
500r----.----.-----.----,
200 r - - - - . - - - - . - - - - - . - - - - ,
f = 1 MHz
4501----+----~~--r_---i
150 I----+------bo.,r::;....--f----i
'<
.3
100 I-----+-----+------::I;---i
'<
..3
~
4001---~~--_i_--~u_---i
u
50 I-----'f-- CONDITIONS:
f
= SQ. WAVE.
3.0
_u 3501----+.~~_i_----r_---i
CS = Vee
RD. WR.
AO -A4 = f
VLO = av. VH1
Vee
=
300 I - - - - t - - CONDITIONS: CS
3.6
3.3
RD, WR,
f
Vce (Volts)
TLlF/11417-20
= SQ.
WAVE, VLO
=
3.3
3.0
=
Vee
AO-A4
f
OV, VH1 = Vee
=
3.6
Vce (Volts)
TL/F/11417-21
Standby Current vs Power
Supply Voltage
Fosc = 4.194304 MHz
Standby Current vs Power
Supply Voltage
(Fosc = 32.768 kHz)
L~
12
'<
..3
CD
_CD
4
/
V
/
V
'<
..3
2.5
120
CD
CD
80
---",'"
2.0
3.0
3.5
4.0
~
160
2.5
4.5
V
/
V
./
3.0
3.5
4.0
4.5
Vee (Volts)
Vee (Volts)
TL/F/11417-22
TLlF/11417-23
III
1-43
c:t
C")
~ ~National
=:i
D
PRELIMINARY
Semiconductor
LV8573A Low Voltage Real Time Clock (RTC)
General Description
The LV8573A is intended for use in microprocessor based
systems where information is required for multi-tasking, data
logging or general time of day/date information. This device
is implemented in low voltage silicon gate microCMOS technology to provide low standby power in battery back-up environments. The circuit's architecture is such that it looks
like a contiguous block of memory or I/O ports organized as
one block of 32 bytes. This includes the Control Registers,
the Clock Counters, the Alarm Compare RAM, and the Time
Save RAM.
Time and date are maintained from 1/100 of a second to
year and leap year in a BCD format, 12 or 24 hour modes.
Day of week and day of month counters are provided. Time .
is controlled by an on-chip crystal oscillator requiring only
the addition of the 32.768 kHz crystal and two capacitors.
Power failure logic and control functions have been integrated on chip. This logic is used by the RTC to issue a power
fail interrupt, and lock out the fLP interface. The time power
fails may be logged into RAM automatically when Vee >
Vee. Additionally, two supply pins are provided. When Vee
> Vee, internal circuitry will automatically switch from the
main supply to the battery supply.
The LV8573A's interrupt structure provides three basic
types of interrupts: Periodic, Alarm/Compare, and Power
Fail. Interrupt mask and status registers enable the masking
and easy determination of each interrupt.
Features
• 3.3V ± 10% supply
• Full function real time clock/calendar
-12/24 hour mode timekeeping
- Day of week counter
- Parallel resonant oscillator
• Power fail features
- Internal power supply switch to external battery
- Power Supply Bus glitch protection
- Automatic log of time into RAM at power failure
• On-Chip interrupt structure
- Periodic, alarm, and power fail interrupts
Block Diagram
OSC
out
V+
Vee
Vee
OSC
in
Logic
Real Time
Clock Counters
Power
rail
WR
00-7
J.l.P
Bus
Logic
AO-4
TLlF/11418-1
FIGURE 1
1-44
Absolute Maximum Ratings (Notes 1 & 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Operation Conditions
Supply Voltage (Vee) (Note 3)
Supply Voltage (Vss) (Note 3)
DC Input or Output Voltage
(VIN. VOUT)
Operation Temperature (TA)
Electr-Static Discharge Rating
Typical Values
Board
8JA DIP
Socket
8JA PLCC Board
Socket
-0.5Vto +7.0V
Supply Voltage (Vee)
DC Input Voltage (VIN)
- 0.5V to Vee + 0.5V
DC Output Voltage (VOUT)
-0.5V to Vee + 0.5V
Storage Temperature Range
- 65°C to + 150°C
Power Dissipation (PO)
500mW
Lead Temperature (Soldering, 10 sec.)
260°C
Min
3.0
2.2
Max
3.6
Vee- O.4
Unit
V
V
0.0
Vee
V
-40
+85
1
°C
kV
61°C/W
67"C/W
80°C/W
88°C/W
DC Electrical Characteristics
Vee = 3.3V ± 10%, Vss = 2.5V, VPFAIL > VIH, CL = 100 pF unless otherwise specified
Symbol
Parameter
Conditions
Min
Max
Units
VIH
High Level Input Voltage
(Note 4)
Any Inputs Except OSC IN,
OSC IN with External Clock
2.0
Vss - 0.2
Vee +0.3
V
V
VIL
Low Level Input Voltage
All Inputs Except OSC IN
OSC IN with External Clock
-0.3
-0.3
0.8
0.2
V
V
VOH
High Level Output Voltage
(Excluding OSC OUT, INTR)
lOUT = -20/-LA
lOUT = - 2.0 mA
VOL
Low Level Output Voltage
(Excluding OSC OUT)
lOUT = -20/-LA
lOUT = 2.0 mA
liN
Input Current (Except OSC IN)
VIN = VeeorGND
loz
Output TRI-STATE® Current
VOUT = Vee or GND
ILKG
Output High Leakage Current
MFa, INTR Pins
VOUT = Vee or GND
Outputs Open Drain
lee
Quiescent Supply Current
(Note 6)
Fose = 32.768 kHz
VIN = Vee or GND (Note 5)
VIN = Vee or GND (Note 6)
VIN = VIH or VIL (Note 6)
Quiescent Supply Current
(Single Supply Mode)
(Note 7)
lee
Iss
ISLK
V
V
Vee -0.2
2.4
0.2
0.3
V
V
±0.7
/-LA
±1
/-LA
±1
/-LA
220
700
5
/-LA
/-LA
mA
Vss = GND
VIN = Vee or GND
Fose = 32.768 kHz
30
/-LA
Standby Mode Battery
Supply Current
(Note 7)
Vee = GND
OSC OUT = open circuit,
other pins = GND
Fose =32.768 kHz
8
/-LA
Battery Leakage
2.2V ~ Vss ~ 2.6V
other pins at GND
Vee = GND, Vss = 2.6V
Vee = 3.6V, Vss = 2.2V
0.8
/-LA
/-LA
-0.8
Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Unless otherwise specified all voltages are referenced to ground.
Note 3: In battery backed mode, Vaa s:: Vcc - O.4V.
Single Supply Mode: Data retention voltage is 2.2V min.
In single Supply Mode (Power connected to Vcc pin) 3.0V s:: VCC s:: 3.6V.
Note 4: This parameter (VIH) is not tested on all pins at the same time.
Note 5: This specification tests Icc with all power fail circuitry disabled, by setting D7 of Interrupt Control Register 1 to O.
Note 6: This specificatio~ tests Icc with all power fail circuitry enabled, by setting D7 of Interrupt Control Register 1 to 1.
Note 7: OSC IN is driven by a signal generator. Contents of the Test Register = OO(H) and the MFO pin is not configured as buffered oscillator out.
Note 1:
Note 2:
1-45
III
...J
AC Electrical Characteristics
Vcc = 3.3V ±10%, VBB = 2.5V, VPFAIL
Symbol
I
> VIH, CL
= 100 pF unless otherwise specified
I
Parameter
Min
I
I
Max
Units
READ TIMING
tAR
Address Valid Prior to Read Strobe
10
tRW
Read Strobe Width (Note 8)
100
ns
tco
Chip Select to Data Valid Time
tRAH
Address Hold after Read (Note 9)
tRO
Read Strobe to Valid Data
90
ns
toz
Read or Chip Select to TRI-STATE
80
ns
tRCH
Chip Select Hold after Read Strobe (Note 9)
0
ns
tos
Minimum Inactive Time between Read or Write Accesses
70
ns
tAW
Address Valid before Write Strobe
10
ns
tWAH
Address Hold after Write Strobe (Note 9)
2
ns
tcw
Chip Select to End of Write Strobe
110
ns
tww
Write Strobe Width (Note 10)
100
ns
tow
Data Valid to End of Write Strobe
70
ns
tWOH
Data Hold after Write Strobe (Note 9)
2
ns
tWCH
Chip Select Hold after Write Strobe (Note 9)
0
ns
ns
ns
100
ns
2
WRITE TIMING
INTERRUPT TIMING
Clock rollover to INTR out typically 20 J-LS
tROLL
Note 8: Read Strobe width as used in the read timing table is defined as the period when both chip select and read inputs are low. Hence read commences when
both signals are low and terminates when either signal returns high.
Note 9: Hold time is guaranteed by design but not production tested. This limit is not used to calculate outgoing quality levels.
Note 10: Write Strobe width as used in the write timing table is defined as the period when both chip select and write inputs are low. Hence write commences when
both signals are low and terminates when either signal returns high.
AC Test Conditions
Input Pulse Levels
Input Rise and Fall Times
Input and Output
Reference Levels
TRI-STATE Reference
Levels (Note 12)
GNDto 3.0V
6 ns (10%-90%)
Vee
1.3V
~
Active High + 0.5V
Active Low - 0.5V
J
Note 11: CL = 100 pF, includes jig and scope capacitance.
Note 12: SI = Vee for active low to high impedance measurements.
SI = GND for active high to high impedance measurements.
SI = open for all other timing measurements.
Capacitance
Symbol
Input 0 - -
~
(TA = 25°C, f = 1 MHz)
Parameter
(Note 13)
Typ
Units
CIN
Input Capacitance
5
pF
COUT
Output Capacitance
7
pF
Device
Under
Test
Note 13: This parameter is not 100% tested.
Note 14: Output rise and fall times 25 ns max (10%-90%) with 100 pF load.
1-46
SI (Note 12)
0
~~)*
.~
:~
Rt. = lK n
*
-~
=
Output
<;,
(Note 11)
TL/F/11418-2
Timing Waveforms
Read Timing Diagram
AG-4~-tAR
-
,....--'RCH
--------~~----~---'Rw--------~J
DATA
Valid Data
TL/F/11418-3
Write Timing Diagram
AO-4
~----------~w----------~
----~_I
~---------~w----------~
----~--~I
IJ----~I
I,::: 'ow
DATA
------------~'<.
Valid Data
TLlF/11418-4
Pin Description
CS, RD, WR (Inputs): These pins interface to ,...p control
lines. The CS pin is an active low enable for the read and
write operations. Read and Write pins are also active low
and enable reading or writing to the RTC. All three pins are
disabled when power failure is detected. However, if a read
or write is in progress at this time, it will be allowed to complete its cycle.
output is permanently configured active low, open drain. If in
battery backed mode and a pull-up resistor is attached, it
should be connected to a voltage no greater than Vss.
00-07 (Input/Output): These 8 bidirectional pins connect
to the host ,...P's data bus and are used to read from and
write to the RTC. When the PFAIL pin goes low and a write
is not in progress, these pins are at TRI-STATE.
AO-A4 (Inputs): These 5 pins are for register selection.
They individually control which location is to be accessed.
These inputs are disabled when power failure is detected.
PFAIL (Input): In battery backed mode, this pin can have a
digital signal applied to it via some external power detection
logic. When PFAIL = logic 0 the RTC goes into a lockout
mode, in a minimum of 30 ,...S or a maximum of 63 ,...s unless
lockout delay is programmed. In the single power supply
mode, this pin is not useable as an input and should be tied
to Vee. Refer to section on Power Fail Functional Description.
Vee (Battery Power Pin): This pin is connected to a backup power supply. This power supply is switched to the internal circuitry when the Vee becomes lower than Vss. Utilizing this pin eliminates the need for external logic to switch in
and out the back-up power supply. If this feature is not to be
used then this pin must be tied to ground, the RTC programmed for single power supply only, and power applied to
the Vee pin.
Vee: This is the main system power pin.
OSC IN (Input): OSC OUT (Output): These two pins are
used to connect the crystal to the internal parallel resonant
oscillator. The oscillator is always running when power is
applied to Vss and Vee.
MFO (Output): The multi-function output can be used as a
second interrupt (Power fail) output for interrupting the ,...P.
This pin can also provide an output for the oscillator. The
MFO output is configured as push-pull, active high for normal or single power supply operation and as an open drain
during standby mode (Vss > Vee). If in battery backed
mode and a pull-up resistor is attached, it should be connected to a voltage no greater than Vss.
INTR (Output): The interrupt output is used to interrupt the
processor when a timing event or power fail has occurred
and the respective interrupt has been enabled. The INTR
GND: This is the common ground power pin for both Vss
and Vee.
1-47
III
Connection Diagrams
Dual·ln·Line
CS-l
RiJ-
~ Ir 17 I? f If ¥
24 -Vee
2
23 -prAll
iVR-3
4
22 -07
AO- 4
21 -06
Al- 5
20 -05
A2- 6
19 -04
A3- 7
3
2
1 28 27 26
Al- 5
25 f- 07
A2- 6
24 f- 06
A3- 7
23 f- 05
A4- 8
22 f- 04
NC -
9
21 ~03
NC -
10
20 ~02
-
11
18 -03
A4- B
Vee -
Plastic Chip Carrier
\.J
171-02
161-01
9
OSC IN- 10
Vee
15 f-OO
OSC OUT- 11
14 f-INTR
GNO- 12
13f-MFO
19 -01
12 13 14 15 16 17 18
Tl/F/1141B-5
Tl/F/1141B-6
Top View
Top View
Order Number LV8573AN
See NS Package Number N24C
Order Number LV8573AV
See NS Package Number V28A
Functional Description
The LV8573A contains a fast access real time clock, inter·
rupt control logic, and power fail detect logic. All functions of
the RTC are controlled by a set of seven registers. A simplified block diagram that shows the major functional blocks is
given in Figure 1.
IE
RAM
10
Months Time Save RAM
lC
Day of Month Time Save RAM
lB
Hours Time Save RAM
The blocks are described in the following sections:
lA
Minutes Time Save RAM
RAM/TEST Register
IF
1. Real Time Clock
2. Oscillator Prescaler
3. Interrupt Logic
19
Seconds Time Save RAM
18
Day of Week Compare RAM
17
Months Compare RAM
16
Day of Month Compare RAM
4. Power Failure Logic
15
Hours Com par. RAM
5. Additional Supply Management
14
Minutes Compare RAM
13
Seconds Compare RAM
12
N/A
11
N/A
10
N/A
The memory map of the RTC is shown in the memory addressing table (Figure 2). A control bit in the Main Status
Register is used to select either control register block.
INITIAL POWER·ON of BOTH Vaa and Vee
OF
N/A
Vss and Vee may be applied in any sequence. In order for
the power fail circuitry to function correctly, whenever power
is off, the Vee pin must see a path to ground through a
maximum of 1 MO. The user should be aware that the control registers will contain random data. The user should en·
sure that the RTC is not in test mode (see register descriptions).
OE
Day of Week Clock Counter
00
DO and 01 Bits Only
RAM'
OC
Years Clock Counter
OB
REAL TIME CLOCK FUNCTIONAL DESCRIPTION
As shown in Figure 2, the clock has 8 bytes of counters,
which count from 1/100 of a second to years. Each counter
counts in BCD and is synchronously clocked. The count sequence of the individual byte counters within the clock is
shown later in Table VII. Note that the day of week, day of
month, and month counters all roll over to 1. The hours
counter in 12 hour mode rolls over to 1 and the AM/PM bit
toggles when the hours rolls over to 12 (AM = 0, PM = 1).
The AM/PM bit is bit D7 in the hours counter.
OA
Months Clock Counter
09
Day of Month Clock Counter
08
Hours Clock Counter
07
Minutes Clock Counter
06
Seconds Clock Counter
05
Yloo Second Counter
Register Select
=0 /
All other counters roll over to O. Upon initial application of
power the counters will contain random information.
Register Select = 1
,
Time Save Control Register
04
Interrupt Control Register 1
Periodic Flag Register
03
Interrupt Control Register 0
N/ A
02
Output Mode Register
N/ A
01
Real Time Mode Register
00
I
Main Status Register
I
Tl/F/11418-7
FIGURE 2. LV8573A Internal Memory Map
1-48
r
Functional Description
<
co
(Continued)
(J1
READING THE CLOCK: VALIDATED READ
The above method is useful when the entire clock is being
corrected. If one location is being updated the clock need
not be stopped since this will reset the prescaler, and time
will be lost. An ideal example of this is correcting the hours
for daylight savings time. To write to the clock "on the fly"
the best method is to wait for the 1/100 of a second periodic interrupt. Then wait an additional 16 /Ls, and then write
the data to the clock.
Since clocking of the counter occurs asynchronously to
reading of the counter, it is possible to read the counter
while it is being incremented (rollover). This may result in an
incorrect time reading. Thus to ensure a correct reading of
the entire contents of the clock (or that part of interest), it
must be read without a clock rollover occurring. In general
this can be done by checking a rollover bit. On this chip the
periodic interrupt status bits can serve this function. The
following program steps can be used to accomplish this.
PRESCALER/OSCILLATOR FUNCTIONAL
DESCRIPTION
1. Initialize program for reading clock.
2. Dummy read of periodic status bit to clear it.
Feeding the counter chain is a programmable prescaler
which divides the crystal oscillator frequency to 32 kHz and
further. to 100 Hz for the counter chain (see Figure 3).
3. Read counter bytes and store.
To Real
4. Read rollover bit, and test it.
Time
5. If rollover occured go to 3.
Counters
6. If no rollover, done.
To detect the rollover, individual periodic status bits can be
polled. The periodic bit chosen should be equal to the highest frequency counter register to be read. That is if only
SECONDS through HOURS counters are read, then the
SECONDS periodic bit should be used.
TLIF/1141S-S
FIGURE 3. Programmable Clock Prescaler Block
In addition to the inverter, the oscillator feedback bias resistor is included on chip, as shown in Figure 4. The oscillator
input may be driven from an external source if desired. Refer to test mode application note for details. The oscillator
stability is enhanced through the use of an on chip regulated
power supply.
READING THE CLOCK: INTERRUPT DRIVEN
Enabling the periodic interrupt mask bits cause interrupts
just as the clock rolls over. Enabling the desired update rate
and providing an interrupt service routine that executes in
less than 10 ms enables clock reading without checking for
a rollover.
The typical range of trimmer capacitor (as shown in Oscillator Circuit Diagram Figure 4, and in the typical application) at
the oscillator input pin is suggested only to allow accurato
tuning of the oscillator. This range is basod on n typical
printed circuit board layout and may havo to bo changod
depending on the parasitiC capacitance of the printod circuit
board or fixture being used. In all cases, the load capacitance specified by the crystal manufacturer (nominal value.
11 pF for the 32.768 crystal) is what determines proper oscillation. This load capcitance is the series combination of
capacitance on each side of the crystal (with respect to
ground).
READING THE CLOCK: LATCHED READ
Another method to read the clock that does not require
checking the rollover bit is to write a one into the Time Save
Enable bit (07) of the Time Save Control Register, and then
to write a zero. Writing a one into this bit will enable the
clock contents to be duplicated in the Time Save RAM.
Changing the bit from a one to a zero will freeze and store
the contents of the clock in Time Save RAM. The time then
can be read without concern for clock rollover, since internal logic takes care of synchronization of the clock. Because only the bits used by the clock counters will be
latched, the Time Save RAM should be cleared prior to use
to ensure that random data stored in the unused bits do not
confuse the host microprocessor. This bit can also provide
time save at power failure, see the Additional Supply Management Functions section. With the Time Save Enable bit
at a logical 0, the Time Save RAM may be used as RAM if
the latched read function is not necessary.
Internal Components
v+
To
Prescaler
INITIALIZING AND WRITING TO THE
CALENDAR-CLOCK
Upon initial application of power to the TCP or when making
time corrections, the time must be written into the clock. To
correctly write the time to the counters, the clock would
normally be stopped by writing the Start/Stop bit in the Real
Time Mode Register to a zero. This stops the clock from
counting and disables the carry circuitry. When initializing
the clock's Real Time Mode Register, it is recommended
that first the various mode bits be written while maintaining
the Start/Stop bit reset, and then writing to the register a
second time with the Start/Stop bit set.
OSC IN
Pin
..----101-----41
OSC OUT
Pin
1
XTAL
External
Components
TLIF/1141S-9
FIGURE 4. Oscillator Circuit Diagram
1-49
........
w
:t>
Functional Description
(Continued)
3. The Power Fail Interrupt: Issued upon recognition of a
power fail condition by the internal sensing logic. The
power failed condition is determined by the signal on the
PFAIL pin. The internal power fail signal is gated with the
chip select signal to ensure that the power fail interrupt
does not lock the chip out during a read or write.
ROUT
150 k!l to 350 k!l
INTERRUPT LOGIC FUNCTIONAL DESCRIPTION
The RTC has the ability to coordinate processor timing activities. To enhance this, an interrupt structure has been implemented which enables several types of events to cause
interrupts. Interrupts are controlled via two Control Registers in block 1 and two Status Registers in block O. (See
Register Description for notes on paging and Table I.)
ALARM COMPARE INTERRUPT DESCRIPTON
The alarm/time comparison interrupt is a special interrupt
similar to an alarm clock wake up buzzer. This interrupt is
generated when the clock time is equal to a value programmed into the alarm compare registers. Up to six bytes
can be enabled to perform alarm time comparisons on the
counter chain. These six bytes, or some subset thereof,
would be loaded with the future time at which the interrupt
will occur. Next, the appropriate bits in the Interrupt Control
Register 1 are enabled or disabled (refer to detailed description of Interrupt Control Register 1). The RTC then compares these bytes with the clock time. When all the enabled
compare registers equal the clock time an alarm interrupt is
issued, but only if the alarm compare interrupt is enabled
can the interrupt be generated externally. Each alarm compare bit in the Control Register will enable a specific byte for
comparison to the clock. Disabling a compare byte is the
same as setting its associated counter comparator to an
"always equal" state. For example, to generate an interrupt
at 3:15 AM of every day, load the hours compare with 0 3
(BCD), the minutes compare with 1 5 (BCD) and the faster
counters with 0 0 (BCD), and then disable all other compare
registers. So every day when the time rolls over from
3:14:59.99, an interrupt is issued. This bit may be reset by
writing a one to bit 03 in the Main Status Register at any
time after the alarm has been generated.
If time comparison for an individual byte counter is disabled,
that corresponding RAM location can then be used as general purpose storage.
The interrupts are enabled by writing a one to the appropriate bits in Interrupt Control Register 0 and/or 1.
TABLE I. Registers that are Applicable
to Interrupt Control
Register Name
Register
Select
Main Status Register
Periodic Flag ,Register
Interrupt Control Register 0
Interrupt Control Register 1
Output Mode Register
X
0
1
1
1
Address
OOH
03H
03H
04H
02H
The Interrupt Status Flag DO, in the Main Status Register,
Indicates the stateof INTR and MFO outputs. It is set when
oither output becomes active and is cleared when all RTC
interrupts have been cleared and no further interrupts are
pending (i.e., both INTR and MFO are returned to their inactive state). This flag enables the RTC to be rapidly polled by
the ftP to determine the source of an interrupt in a wiredOR interrupt system. (The Interrupt Status Flag provides a
true reflection of all conditions routed to the external pins.)
Status for the interrupts are provided by the Main Status
Register and the Periodic Flag Register. Bits 01-05 of the
Main Status Register are the main interrupt bits.
PERIODIC INTERRUPTS DESCRIPTION
The Periodic Flag Register contains six flags which are set
by real-time generated "ticks" at various time intervals, see
Figure S. These flags constantly sense the periodic signals
and may be used whether or not interrupts are enabled.
These flags are cleared by any read or write operation performed on this register.
These register bits will be set when their associated timing
events occur. Enabled Alarm comparisons that occur will
set its Main Status Register bit to a one. However, an external interrupt will only be generated if the Alarm interrupt
enable bit is set (see Figure S).
Disabling the periodic interrupts will mask the Main Status
Register periodic bit, but not the Periodic Flag Register bits.
The Power Fail Interrupt bit is set when the interrupt is enabled and a power fail event has occurred, and is not reset
until the power is restored. If all interrupt enable bits are 0
no interrupt will be asserted. However, status still can be
read from the Main Status Register in a polled fashion (see
FigureS).
To clear a flag in bits 02 and 03 of the Main Status Register
a 1 must be written back into the bit location that is to be
cleared. For the Periodic Flag Register reading the status
will reset all the periodic flags.
To generate periodic interrupts at the desired rate, the associated Periodic Interrupt Enable bit in Interrupt Control Register 0 must be set. Any combination of periodic interrupts
may be enabled to operate simultaneously. Enabled periodic interrupts will now affect the Periodic Interrupt Flag in the
Main Status Register.
When a periodic event occurs, the Periodic Interrupt Flag in
the Main Status Register is set, causing an interrupt to be
generated. The ftP clears both flag and interrupt by writing a
"1" to the Periodic Interrupt Flag. The individual flags in the
periodic Interrupt Flag Register do not require clearing to
cancel the interrupt.
If all periodic interrupts are disabled and a periodic interrupt
is left pending (i.e., the Periodic Interrupt Flag is still set), the
Periodic Interrupt Flag will still be required to be cleared to.
cancel the pending interrupt.
Interrupts Fall Into Three Categories:
1. The Alarm Compare Interrupt: Issued when the value in
the time compared RAM equals the counter.
2. The Periodic Interrupts: These are issued at every increment of the specific clock counter signal. Thus, an interrupt is issued every minute, second, etc. Each of these
interrupts occurs at the roll-over of the specific counter.
1-50
"'T1
C
:::l
(")
O·
::::J
~
Interrupt Control Registers
Main Status
Register
C
Interrrupt Control
Register
CD
en
(")
.,
Output Mode
Register
Control
Bit
Real
Time
Periodic
Pulse
Signals
(also to
Periodic
Flags)
-
-6'
O·
:::l
oo
;:?
:;c
CD
MFO Output
.eo
-----+
Output
Buffer
~
Interrupt
Mode
Selected
Alarm
Compare
Signals
Power
Fail
Detect
INTR Output
Output
Buffer
Tl/F/11418-10
FIGURE 5. Interrupt Control Logic Overview
VClS8A1
II
...J
Functional Description
(Continued)
POWER FAIL INTERRUPTS DESCRIPTION
disconnected, and the device is now in the standby mode. If
indeterminate operation of the battery switch over circuit is
to be avoided, then the voltage at the Vee pin must not be
allowed to equal the voltage at the Vss pin.
The Power Fail Status Flag in the Main Status Register
monitors the state of the internal power fail signal. This flag
may be interrogated by the J-LP, but it cannot be cleared; it is
cleared automatically by the RTC when system power is
restored. To generate an interrupt when the power fails, the
Power Fail Interrupt Enable bit in Interrupt Control Register
1 is set. Although this interrupt may not be cleared, it may
be masked by clearing the Power Fail Interrupt Enable bit.
After the generation of a lock-out signal, and eventual
switch in of the battery supply, the pins of the RTC will be
configured as shown in Table II. Outputs that have a pull-up
resistor should be connected to a voltage no greater than
Vss·
POWER FAILURE CIRCUITRY FUNCTIONAL
DESCRIPTION
TABLE II. Pin Isolation during a Power Failure
Since the clock must be operated from a battery when the
main system supply has been turned off, the LV8573A provides circuitry to simplify design in battery backed systems.
This switches over to the back up supply, and isolates itself
from the host system. Figure 6 shows a simplified block
diagram of this circuitry, which consists of three major sections; 1) power loss logic: 2) battery switch over logic: and 3)
isolation logic.
Detection of power loss occurs when PFAIL is low. Debounce logic provides a 30 J-Ls-63 J-Ls debounce time, which
will prevent noise on the PFAIL pin from being interpreted
as a system failure. After 30 J-Ls-63 J-Ls the debounce logic
times out and a signal is generated indicating that system
power is marginal and is failing. The Power Fail Interrupt will
then be generated.
Pin
PFAIL =
Logic 0
CS, RD, WR
AO-A4
00-07
Oscillator
PFAIL
INTR, MFO
Locked Out
Locked Out
Locked Out
Not Isolated
Not Isolated
Not Isolated
Standby Mode
Vee> Vee
Locked Out
Locked Out
Locked Out
Not Isolated
Not Isolated
Open Drain
The Interrupt Power Fail Operation bit in the Real-Time
Mode Register determines whether or notthe interrupts will
continue to function after a power fail event.
As power returns to the system, the battery switch over circuit will switch back to Vee power as soon as it becomes
greater than the battery voltage. The chip will remain in the
locked out state as long as PFAIL=O. When PFAIL=1 the
chip is unlocked, but only after another 30 J-Ls min ~ 63
J-Ls max debounce time. The system designer must ensure
that his system is stable when power has returned.
The power fail circuitry contains active linear circuitry that
draws supply current from Vee. In some cases this may be
undesirable, so this circuit can be disabled by masking the
power fail interrupt. The power fail input can perform all
lock-out functions previously mentioned, except that no ex-
If chip select is low when a power failure is detected, a
safety circuit will ensure that if a read or write is held active
continuously for greater than 30 J-Ls after the power fail signal is asserted, the lock-out will be forced.
The battery switch over circuitry is completely independent
of the PFAIL pin. A separate circuit compares Vee to the
Vss voltage. As the main supply fails, the RTC will continue
to operate from the Vee pin until Vee falls below the Vss
voltage. At this time, the battery supply is switched in, Vee is
Battery Switchover
VBB
Vee
~
v+
~
30 uS
Delay
Power
Fail Logic
PFAIL
(External
power fail
signal)
~
Delayed
Lockout
I 30-63 uS I
I
Debounce
Delay
I
....
Data
Address
and
Control
Buffers
'"
8/ ...
I
5/
/
.. DO:D7
AO:A4
3/
I
CS,RD,WR
TL/F/11418-11
FIGURE 6. System-Battery Switchover (Upper Left), Power Fail
and Lock-Out Circuits (Lower Right)
1-52
Functional Description
(Continued)
TABLE III. Register/Counter/RAM
Addressing for LV8573A
ternal interrupt will be issued. Note that the linear power fail
circuitry is switched off automatically when using VSG in
standby mode.
AO·4
INITIAL POWER ON DETECT AND
POWER FAIL TIME SAVE
RS
(Note 1)
Description
CONTROL REGISTERS
There are two other functions provided on the LV8573A to
ease power supply control. These are an initial Power On
detect circuit, which also can be used as a time keeping
failure detect, and a time save on power failure.
00
01
02
03
04
01
02
03
04
On initial power up the Oscillator Fail Flag will be set to a
one and the real time clock start bit reset to a zero. This
indicates that an oscillator fail event has occurred, and time
keeping has failed.
The Oscillator Fail flag will not be reset until the real-time
clock is started. This allows the system to discriminate between an initial power-up and recovery from a power failure.
If the battery backed mode is selected, then bit D6 of the
Periodic Flag Register must be written low. This will not affect the contents of the Oscillator Fail Flag.
X
0
0
0
0
1
1
1
1
Main Status Register
N/A
N/A
Periodic Flag Register
Time Save Control Register
Real Time Mode Register
Output Mode Register
Interrupt Control Register 0
Interrupt Control Register 1
COUNTERS (CLOCK CALENDAR)
To relieve CPU overhead for saving time upon power failure,
the Time Save Enable bit is provided to do this automatically. (See also Reading the Clock: Latched Read.) The Time
Save Enable bit, when set, causes the Time Save RAM to
follow the contents of the clock. This bit can be reset by
software, but if set before a power failure occurs, it will automatically be reset when the clock switches to the battery
supply (not when a power failure is detected by the PFAIL
pin). Thus, writing a one to the Time Save bit enables both a
software write or power fail write.
SINGLE POWER SUPPLY APPLICATIONS
The LV8573A can be used in a single power supply application. To achieve this, the VSS pin must be connected to
ground, and the power connected to Vee. The Oscillator
Failed/Single Supply bit in the Periodic Flag Register should
be set to a logic 1, which will disable the oscillator battery
reference circuit. The power fail interrupt should also be disabled. This will turn off the linear power fail detection circuits, and will eliminate any quiescent power drawn through
these circuits.
05
06
07
08
09
OA
08
OC
OD
OE
X
X
X
X
X
X
X
X
X
X
1/100, 1/10 Seconds
Seconds
Minutes
Hours
Days of Month
Months
Years
RAM
DO, D1 bits only
Day of Week
OF
10
11
12
X
X
X
X
N/A
N/A
N/A
N/A
(0-99)
(0-59)
(0-59)
(1-12,0-23)
(1-28/29/30/31 )
(1-12)
(0-99)
(1-7)
TIME COMPARE RAM
13
14
15
16
17
18
DETAILED REGISTER DESCRIPTION
There are 5 external address bits: Thus, the host microprocessor has access to 28 locations at one time. An internal
switching scheme provides a total of 30 locations.
X
X
X
X
X
X
Sec Compare RAM
Min Compare RAM
Hours Compare RAM
DOM Compare RAM
Months Compare RAM
DOW Compare RAM
(0-59)
(0-59)
(1-12,0-23)
(1-28/29/30/31 )
(1-12)
(1-7)
TIME SAVE RAM
The only register that does not get switched is the Main
Status Register. It contains the register select bit as well as
status information.
A memory map is shown in Figure 2 and register addressing
in Table 1/1. They show the name, address and page locations for the LV8573A.
19
1A
18
1C
1D
X
X
X
X
X
Seconds Time Save RAM
Minutes Time Save RAM
Hours Time Save RAM
Day of Month Time Save RAM
Months Time Save RAM
1E
1F
1
X
RAM
RAM/Test Mode Register
Note 1: RS-Register Select (Bit 06 of Main Status Register) .
1-53
...J
Functional Description. (Continued)
Vss pin to a value less than 2.2V when in the battery
backed mode. Bit 06 is automatically set to 1 on initial power-up or an oscillator fail event. The oscillator fail flag is
reset by writing a one to the clock start/stop bit in the Real
Time Mode Register, with the crystal oscillating.
MAIN STATUS REGISTER
R
RS
R
R
AL PERI pr
INT
IL:
DO Interrupt Status
01 Power rail Interrupt
02 Period Interrupt
When 06 is written to, it defines whether the TCP is being
used in battery backed (normal) or in a single supply mode
application. When set to a one this bit configures the TCP
for single power supply applications. This bit is automatically
set on initial power-up or an oscillator fail event. When set,
06 disables the oscillator reference circuit. The result is that
the oscillator is referenced to Vee. When a zero is written to
06 the oscillator reference is enabled, thus the oscillator is
referenced to Vss. This allows operation in standard battery
standby applications.
03 Alarm Interrupt
04 RAt.!
05 RAt.!
06 Rogister Select Bit
07 RAt.!
TL/F/11418-12
The Main Status Register is always located at address 0
regardless of the register block selected.
00: This read only bit is a general interrupt status bit that is
taken directly from the interrupt pins. The bit is a one when
an interrupt is pending on either the INTR pin or the MFO
pin (when configured as an interrupt). This is unlike 03
which can be set by an internal event but may not cause an
interrupt. This bit is reset when the interrupt status bits in the
Main Status Register are cleared.
At initial power on, if the LV8573A is going to be programmed for battery backed mode, the Vss pin should be
connected to a potential in the range of 2.2V to Vee O.4V.
For single supply mode operation, the Vss pin should be
connected to GNO and the PFAIL pin connected to Vee.
07: Writing a one to this bit enables the test mode register
at location 1F (see Table III). This bit should be forced to
zero during initialization for normal operation. If the test
mode has been entered, clear the test mode register before
leaving test mode. (See separate test mode application
note for further details.)
01-03: These three bits of the Main Status Register are the
main interrupt status bits. Any bit may be a one when any of
the interrupts are pending. Once an interrupt is asserted the
f.tP will read this register to determine the cause. These
interrupt status bits are not reset when read. Except for 01,
to reset an interrupt a one is written back to the corresponding bit that is being tested. 01 is reset whenever the PFAIL
pin = logic 1. This prevents loss of interrupt status when
reading the register in a polled mode. 01 and 03 are set
regardless of whether these interrupts are masked or not by
bits 06 and 07 of Interrupt Control Registers 0 and 1.
TIME SAVE CONTROL REGISTER
DO RAt.!
01 RAt.!
02 RAt.!
04, 05 and 07: General purpose RAM bits.
' - - - - - - 03 RAt.!
06: Bit 06 controls the register block to be accessed (see
memory map).
' - - - - - - - 04 RAt.!
' - - - - - - - - 05 RAt.!
PERIOOIC FLAG REGISTER
Tt.!
osr 1m, 10m, 100m,I 10 110s 1 min
I L=
' - - - - - - - - - 06 N/A
' - - - - - - - - - - 07 Timo Savo Enablo
TL/F/11418-14
DO minutes flag
00-05: General purpose RAM bits.
01 10 ,econd flag
02 seconds flag
06: Not Available, appears as logic 0 when read.
03 100 millisec. flag
07: Time Save Enable bit controls the loading of real-timeclock data into the Time Save RAM. When a one is written
to this bit the Time Save RAM will follow the corresponding
clock registers, and when a zero is written to this bit the time
in the Time Save RAM is frozen. This eliminates any synchronization problems when reading the clock, thus negating the need to check for a counter rollover during a read
cycle.
04 10 millisec. flag
05 milli-seconds flag
06 Oscillator railed/Single Supply Bit
07 Tost t.!ode Enable
TL/F/11418-13
The Periodic Flag Register has the same bit for bit correspondence as Interrupt Control Register 0 except for 06
and 07. For normal operation (Le., not a single supply application) this register must be written to on initial power up or
after an oscillator fail event. 00-05 are read only bits, 06
and D7 are read/write.
This bit must be set to a one prior to power failing to enable
the Time Save feature. When the power fails this bit is automatically reset and the time is saved in the Time Save RAM.
REAL TIME MOOE REGISTER
00-05: These bits are set by the real time rollover events:
(Time Change = 1). The bits are reset when the register is
read and can be used as selective data change flags.
DO Loap Voar LSB
01 Loap Voar t.!SB
06: This bit performs a dual function. When this bit is read, a
one indicates that an oscillator failure has occurred and the
time information may have been lost. Some of the ways an
oscillator failure might be caused are: failure of the crystal,
shorting OSC IN or OSC OUT to GNO or Vee, removal of
crystal, removal of battery when in the battery backed mode
(when a "0" is written to 06), lowering the voltage at the
02 ·,2!U hour mod.
' - - - - - - 03 Clock Start/StOii
' - - - - - - - 04 Interrupt pr Oporation
" - - - - - - - 0 5 RAt.!
L - - - - - - - - 0 6 RAt.!
' - - - - - - - - - - 0 7 RAt.!
1-54
TL/F/11418-15
Functional Description (Continued)
00-01: These are the leap year counter bits. These bits are
written to set the number of years from the previous leap
year. The leap year counter increments on December 31 st
and it internally enables the February 29th counter state.
This method of setting the leap year allows leap year to
occur whenever the user wishes to, thus providing flexibility
in implementing Japanese leap year function.
INTERRUPT CONTROL REGISTER 0
I R I R 11ml~lhml sl~I~1
IL:
DO t.4inutes enable
01 10 second enable
02 Seconds enable
03 100 millisec enable
04 10 millisec enable
Leap Year
Counter
LYO
LY1
0
0
0
1
1
0
05 millisec enable
06 RAt.4
Leap Year Current Year
Leap Year Last Year
Leap Year 2 Years Ago
Leap Year 3 Years Ago
1
1
07 RAt.4
TL/F/11418-17
00-05: These bits are used to enable one of the selected
periodic interrupts by writing a one into the appropriate bit.
These interrupts are issued at the rollover of the clock. For
example, the minutes interrupt will be issued whenever the
minutes counter increments. In all likelihood the interrupt
will be enabled asynchronously with the real time change.
Therefore, the very first interrupt will occur in less than the
periodic time chosen, but after the first interrupt all subsequent interrupts will be spaced correctly. These .interrupts
are useful when minute, second, real time reading, or task
switching is required. When all six bits are written to a 0 this
disables periodic interrupts "from the Main Status Register
and the interrupt pin.
02: The count mode for the hours counter can be set to
either 24 hour mode or 12 hour mode with AM/PM indicator.
A one will place the clock in 12 hour mode.
03: This bit is the master Start/Stop bit for the clock. When
a one is written to this bit the real time counter's prescaler
and counter chain are enabled. When this bit is reset to zero
the contents of the real time counter is stopped. When the
RTC is initially powered up this bit will be held at a logic 0
until the oscillator starts functioning correctly after which
this bit may be modified. If an oscillator fail event occurs,
this bit will be reset to logic O.
06 and 07: General purpose RAM.
04: This bit controls the operation of the interrupt output in
standby mode. If set to a one it allows Alarm, Periodic, and
INTERRUPT CONTROL REGISTER 1
I pre I ALe I 00t.41 t.40 100t.41 HR I t.4N I
sc I
IL:
Power Fail interrupts to be functional in standby mode. Note
that the MFO pin is configured as open drain in standby
mode.
If bit 04 is set to a zero then the interrupt control register
and the periodic interrupt flag will be reset when the RTC
enters the standby mode (Vss > Vee>. They will have to be
re-configured when system (Vee> power is restored.
DO Second compare enable
01 t.4inute compare enable
02 Hour compare enable
03 Day of month enable
04 t.4onth compare enable
05 Day of week enable
05-07: General purpose RAM bits.
06 Alarm interrupt enable
OUTPUT MOOE REGISTER
07 Power fail interrupt enable
TLlF/11418-18
I t.40 I R I R I R I R I R I R I R I
IL
00-05: Each of these bits are enable bits which will enable
a comparison between an individual clock counter and its
associated compare RAM. If any bit is a zero then that
clock-RAM comparator is set to the "always equal" state
and the associated TIME COMPARE RAM byte can be used
as general purpose RAM. However, to ensure that an alarm
interrupt is not generated at bit 03 of the Main Status Register, all bits must be written to a logic zero.
06: In order to generate an external alarm compare interrupt to the p.P from bit 03 of the Main Status Register, this
bit must be written to a logic 1. If battery backed mode is
selected, then this bit is controlled by 04 of the Real Time
Mode Register.
07: The MSB of this register is the enable bit for the Power
Fail Interrupt. When this bit is set to a one an interrupt will
be generated to the p.P when a Vss > Vee. If battery
backed mode is selected, then this bit is controlled by 04 of
the Real Time Mode Register.
DO RAt.4
01 RAt.4
02 RAt.4
03 RAt.4
04 RAt.4
05 RAt.4
06 RAt.4
07 t.4rO Pin as Oscillator
TL/F/11418-16
00-06: General purpose RAM bits.
07: This bit is used to program the signal appearing at the
MFO output, as follows:
07
MFO Output Signal
0
1
Power Fail Interrupt
Buffered Crystal Oscillator
1-55
<
('I')
l"-
ii)
co
>
...I
Control and Status Register Address Bit Map
07
06
Main Status Register PS = X
R/W
R/W
03
05
04
RS = X ADDRESS = OOH
R/W1
R/W
R/W
02
01
00
R/W1
R2
R3
1. Reset by
writing
1 to bit.
2. Set! reset by
voltage at
PFAILpin.
3. Reset when
all pending
interrupts
are removed.
Periodic Flag Register PS = 0
R/W
R/W4
RS
=0
R5
Addiess
= 03H
R5
4. Read Osc fail
Write 0 BattBacked Mode
Write 1 Single
Supply Mode
R5
5. Reset by
positive edge
of read.
All Bits R/W
All Bits R/W
RS = 1
Output Mode Register PS = 0
L. .I_~- ,~_~_t:_:- - I.I
__R_A_M_----I.I__R_A_M_----,-__R_A_M_---,-__
RA_M_----I.__R_A_M_----'-__R_A_M_---'-_R_A_M_----'I All Bits R/W
Interrupt Control Register 0 PS = 0
RAM
RAM
1 ms
Interrupt
Enable
Interrupt Control Register 1 PS = 0
Power Fail
Interrupt
Enable
Address = 02H
Alarm
Interrupt
Enable
DOW
Interrupt
Enable
RS = 1
Address = 03H
10 ms
Interrupt
Enable
RS = 1
100 ms
Interrupt
Enab!e
Seconds
Interrupt
Enable
10 Second
Interrupt
Enable
Minute
Interrupt
Enable
All Bits R/W
Minute
Interrupt
Enable
Second
Interrupt
Enable
All Bits R/W
Address = 04H
Month
Interrupt
Enable
DOM
Interrupt
Enable
Hours
Interrupt
Enable
Application Hints
4. Enter a software loop that does the following:
Suggested Initialization Procedure for LV8573A in Battery Backed Applications .that use the VBB Pin
Set a 3 second(approx) software counter. The crYstal
oscillator may take 1 second to start.
1. Enter the test mode by writing a 1 to bit 07 in the Periodic Flag Register.
4.1 Write a 1 to bit 03 in the Real Time Mode Register (try
to start the clock). Under normal operation, this bit can
be set only if the oscillator is running. During the software loop, RAM, real time counters, output configuration, interrupt control and timer functions may be initialized.
2. Write zero to the RAM/TEST mode Register located in.
page 0, address HEX 1F.
3. Leave the test mode by writing a 0 to bit 07 in the Periodic Flag Register. Steps 1, 2, 3 guarantee that if the
test mode had been entered during power on (due to
random pulses from the system), all test mode conditions are cleared. Most important is that the OSC Fail
Disable bit is cleared. Refer to AN-589 for more information on test mode operation.
1-56
r
<
0)
Application Hints (Continued)
CJ1
The only method to ensure the chip is in the battery
backed mode is to measure the waveform at the OSC
OUT pin. If the battery backed mode was selected successfully, then the peak to peak waveform at OSC OUT
is referenced to the battery voltage. If not in battery
backed mode, the waveform is referenced to Vee. The
measurement should be made with a high impedance
low capacitance probe (10 MO, 10 pF oscilloscope
probe or better). Typical peak to peak swings are within
0.6V of Vee and ground respectively.
5. Test bit 06 in the Periodic Flag Register:
IF a 1. go to 4.1. If this bit remains a 1 after 3 seconds,
then abort and check hardware. The crystal may be defective or not installed. There may be a short at OSC IN
or OSC OUT to Vee or GNO, or to some impedance that
is less than 10 MO.
IF a 0. then the oscillator is running, go to step 7.
6. Write a 0 to bit 06 in the Periodic Flag Register. This
action puts the clock chip in the battery backed mode.
This mode can be entered only if the OSC fail flag (bit
06 of the Periodic Flag Register) is a O. Reminder, bit 06
is a dual function bit. When read, 06 returns oscillator
status. When written, 06. causes either the Battery
Backed Mode, or the Single Supply Mode of operation.
Typical Application
-
-
7. Write a 1 to bit 07 of Interrupt Control Register 1. This
action enables the PFAIL pin and associated circuitry.
B. Initialize the rest of the chip as needed.
Main Supply
RI'
T
" ."
..r-
~
::: .,
~8.,
"t:>
<0
I
.
A
0
Address Bus
't
A
AO-A4
I"
CI)
CI)
Q)
A
0
0
L.
a..
Data Bus
'of
OSC IN
'"
A
00-07
0
~
't
A
'"
OSC OUT
A
V
RO, WR. INT
"
A low going user
generated pow er
fail signal sho uld
be presented t a tho
PFAIL pin.
I"l'
'T '
00-07
--y
"
...£2.!!.!.!:21
't
AO-A4
LV8573A
Real Time
Clock
-y
L.
.~
'"
V
't
+
T
r. cs
-
'"
Battery Supply
.......
.....
Vee
Vee
PFAIL
L.
01'
RD
2-22 pF
32.768KHz
T
47 PF
WR
V INTR
't
+--
MFO
GNO
L.-
!
--- ....
TL/F/1141B-19
'These components may be necessary to meet UL requirements
for lithium batteries. Consult battery manufacturer.
1-57
.......
Col
l>
Typical Performance Characteristics
Operating Current vs
Supply Voltage
(Battery Backed Mode
Fosc = 32.768 kHz,
Vee = 2.5V)
Operating Current vs
Supply Voltage
(Single Supply Mode
Fosc = 32.768 kHz)
Standby Current vs Power
Supply Voltage
(Fosc = 32.768 kHz)
500 r---.-----r----,-----,
200 r--..,---..,-----y-----,
"
f
= 1 MHz
1501---t----t::..,c.--+-----l
.
..3
1001---+---+------:::10'----1
~
.
..3
~
501-------.01"""--
450
I--+--~-__t'----I
400
I-~£j--_t_-_'_:l;;__---I
3501----10-'""'---+----,.--1
300 I - - + - - CONDITIONS:
3.0
3.3
3.6
RD, Wi,
,f
Vee (Volts)
TL/F/11418-20
Cs = Vee
AO -A4 = f
=SQ. WAVE, VLO = OV, VHI = Vee
3.0
3.3
3.6
Vee (Volts)
TL/F/11418-21 ,
1-58
/1'
12
'/
/
/
/
----
2.0
2.5
3.0
3.5
4.0
4.5
Vee (Volts)
TL/F/11418-22
Section 2
Real Time Clocks
and Timer Clock
Peripherals
Section 2 Contents
TCP/RTC Family Comparisons. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DP8570A Timer Clock Peripheral (TCP) ...............................................
DP8571 A Timer Clock Peripheral (TCP) ...............................................
DP8572A/DP8572AM Real Time Clock (RTC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DP8573A Real Time Clock (RTC)............................................ .........
MM58274C-12 Microprocessor Compatible Real Time Clock ....................... :.....
MM58274C Microprocessor Compatible Real Time Clock................................
MM58174A Microprocessor Compatible Real Time Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MM581678 Microprocessor Real Time Clock ................................... :......
NS32FX211 Microprocessor Compatible Real Time Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2-2
2-3
2-5
2-28
2-51
2-71
2-86
2-99
2-112
2-119
2-128
-t
o
rcp Family Comparison Guide
Features
I
DP8570A
"'D
I
LV8571A/DP8571A
I
"'T1
LV8572A1DP8572A
-<
TIMEKEEPING
Mode
Range
Leap Year
Rollover
12 or 24 Hour
0.01 sec thru Years
Yes
Status Bit
12 or 24 Hour
0.01 sec thru Years
Yes
Status Bit
Q)
I LV8573A1DP8573A 2.
12 or 24 Hour
0.01 sec thru Years
Yes
Status Bit
12 or 24 Hour
0.01 sec thru Years
Yes
Status Bit
Parallel
5
8
.100 ns
Parallel
5
8
100 ns
Parallel
5
8
100 ns
44 Bytes
216-Bit
44 Bytes
216-Bit
44 Bytes
No
14 Bytes
No
0.001 sec thru 1 min
Yes
Yes
Yes
Yes
0.001 sec thru 1 min
Yes
Yes
Yes
Yes
0.001 sec thru 1 min
Yes
Yes
Yes
No
0.001 sec thru 1 min
Yes
Yes
Yes
No
4 Selectable (Note 1)
Yes
4 Selectable (Note ·1)
Yes
4 Selectable (Note 1)
Yes
32.768 kHz
Yes
4.5-5.5V
2.2Vmin
3-3.6V/4.5-5.5V
2.2Vmin
3-3.6V / 4.5-5.5V
2.2Vmin
3-3.6V /4.5-5.5V
2.2V min
5mA
10,...A
5mA
10,...A
5mA
1O,...A
5mA
1O,...A
microCMOS
microCMOS
microCMOS
microCMOS
28DIP
28 PCC (Note 2)
24 DIP (Note 2)
24 DIP (Note 2)
28 PCC (Note 2)
24 DIP (Note 2)
28 PCC (Note 2)
Parallel'
5
8
100 ns
INTERRUPTS
Programmable
Alarm Compare
Standby Mode
Status Register
Timer
TIMEBASE
Oscillator Frequency
Buffered Oscillator Output
POWER SUPPLY
Voltage
Operational
Standby
Current (32.768 kHz)
Operational
Standby (100 Max)
PROCESS TECHNOLOGY
PACKAGING
Pins/Type
....
Q)
rn·
:::s
RAM
On-Chip
Timer
"C
o
BUS
Mode
Address (# Bits)
Data (# Bits)
Max Access Time
(Address to Data Valid)
o
o
3
Note 1: 32 kHz. 32.76B kHz. 4.194304 MHz. 4.9152 MHz
Note 2: Socket equivalent pin outs
2-3
G)
c:
is:
CD
CD
"C
"5
~
RTC Family Comparison Guide
c
o
Features
UJ
"i: TIMEKEEPING
ca
Mode
Range
Leap Year
Rollover
C.
E
o
o
~
"eca
I
I
MM58167B
MM58174A
I
MM58274C
24 Hour
0.001 sec thru Months
No
Status Bit
24 Hour'
0.1 sec thru Months
Yes
Yes
12 or 24 Hour
0.1 sec thru Years
Yes
Status Bit
Mode
Address (# Bits)
Data (# Bits)
Max Access Time
(Address to Data Valid)
Parallel
5
8
1050 ns
Parallel
4
4
2.35,.,.s
Parallel
4
4
650 ns
On-Chip
56 Bits
(14 X 4)
No
No
BUS
LL
~
a:
RAM
I
I
I
INTERRUPTS
Programmable
0.1 sec thru Months
0.5, 5, and 60 sec
Alarm Compare
Standby Mode
Status Register
Yes
Yes
Yes
No
No
Yes (intr)
0.1,0.5,1,5,10,
30 and 60 sec
No
No
Yes
32.768 kHz
No
32.768 kHz
Yes (16.384 kHz)
32.768 kHz
Yes
4.5-5.5V
2.2Vmin
4.5-5.5V
2.2Vmin
4.5-5.5V
2.2Vmin
5mA
20,.,.A
1 rnA
1O,.,.A
1 rnA
10,.,.A
TIMEBASE
Oscillator Frequency
Buffered Oscillator Output
POWER SUPPLY
Voltage
Operational
Standby
Current
Operational
Standby (100 Max)
PROCESS TECHNOLOGY
I
I
CMOS
CMOS
I
CMOS
PACKAGING
Pins/Type
24 DIP
28PCC
16 DIP
2-4
16 DIP
20PCC
C
"tJ
~National
U
(X)
U1
.......
o
l>
Semiconductor
DP8570A Timer Clock Peripheral (TCP)
General Description
The DP8570A is intended for use in microprocessor based
systems where information is required for multi-tasking, data
logging or general time of day/date information. This device
is implemented in low voltage silicon gate microCMOS technology to provide low standby power in battery back-up environments. The circuit's architecture is such that it looks
like a contiguous block of memory or I/O ports. The address
space is organized as 2 software selectable pages of 32
bytes. This includes the Control Registers, the Clock Counters, the Alarm Compare RAM, the Timers and their data
RAM, and the Time Save RAM. Any of the RAM locations
that are not being used for their intended purpose may be
used as general purpose CMOS RAM.
interrupt, and lock out the I!P interface. The time power fails
may be logged into RAM automatically when Vss > Vee.
Additionally, two supply pins are provided. When Vss >
Vee, internal circuitry will automatically switch from the main
supply to the battery supply. Status bits are provided to indicate initial application of battery power, system power, and
low battery detect.
(Continued)
Features
• Full function real time clock/calendar
- 12/24 hour mode timekeeping
- Day of week and day of years counters
- Four selectable oscillator frequencies
- Parallel Resonant Oscillator
• Two 16-bit timers
- 10 MHz external clock frequency
- Programmable multi-function output
- Flexible re-trigger facilities
• Power fail features
- Internal power supply switch to external battery
- Power Supply Bus glitch protection
- Automatic log of time into RAM at power failure
• On-Chip interrupt structure
- Periodic, alarm, timer and power fail interrupts
• Up to 44 bytes of CMOS RAM
• INTR/MFO/T1 pins programmable High/Low and pushpull or open drain
Time and date are maintained from 1/100 of a second to
year and leap year in a BCD format, 12 or 24 hour modes.
Day of week, day of month and day of year counters are
provided. Time is controlled by an on-chip crystal oscillator
requiring only the addition of the crystal and two capacitors.
The choice of crystal frequency is program selectable.
Two independent multifunction 10 MHz 16-bit timers are
provided. These timers operate in four modes. Each has its
own prescaler and can select any of 8 possible clock inputs.
Thus, by programming the input clocks and the timer counter values a very wide range of timing durations can be
achieved. The range is from about 400 ns (4.915 MHz oscillator) to 65,535 seconds (18 hrs., 12 min.).
Power failure logic and control functions have been integrated on chip. This logic is used by the TCP to issue a power fail
Block Diagram
OSC
TCK GO/I T1 out
OSC
In
fJI
INTR
FIGURE 1
2-5
MFO
TL/F/8638-1
<
o
I'Lt)
CO
D..
C
Absolute Maximum Ratings
Operation Conditions
(Notes 1 & 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
-0.5V to + 7.0V
Supply Voltage (Vee>
Supply Voltage (Vee> (Note 3)
Supply Voltage (Vss) (Note 3)
DC Input or Output Voltage
(VIN, VOUT)
Operation Temperature (TA)
Electr·Static Discharge Rating TBD
DC Input Voltage (VIN)
- 0.5V to Vee + 0.5V
DC Output Voltage (VOUT)
-0.5V to Vee + 0.5V
Storage Temperature Range
- 65°C to + 150°C
Power Dissipation (PO)
500mW
Lead Temperature (Soldering, 10 sec.)
260°C
Transistor Count
Typical Values
6JA DIP
Min
4.5
2.2
Max
Unit
5.5
V
V
Vee- O.4
0.0
Vee
V
-40
+85
1
15,200
°C
kV
Board
Socket
Board
Socket
6JA PLCC
=
=
=
=
45°C/W
50°C/W
77°C/W
85°C/W
DC Electrical Characteristics
Vee
= 5V ± 10%, Vss = 3V, VPFAIL > VIH, CL = 100 pF (unless otherwise specified)
Symbol
VIH
Parameter
High Level Input Voltage
(Note 4)
Conditions
Any Inputs Except OSC IN,
OSC IN with External Clock
VIL
Low Level Input Voltage
All Inputs Except OSC IN
OSC IN with External Clock
VOH
High Level Output Voltage
(Excluding OSC OUT)
VOL
Low Level Output Voltage
(Excluding OSC OUT)
Input Current (Except OSC IN)
Output TRI·STATE® Current
= -20,....A
= -4.0 rnA
lOUT = 20,....A
lOUT = 4.0 rnA
VIN = VeeorGND
VOUT = Vee or GND
VOUT = Vee or GND
liN
102
ILKG
Icc
Icc
Iss
Output High Leakage Current
T1, MFO, INTR Pins
Quiescent Supply Current
(Note?)
Quiescent Supply Current
(Single Supply Mode)
(Note 7)
Standby Mode Battery
Supply Current
(Note 8)
lOUT
lOUT
Outputs Open Drain
Fose = 32.768 kHz
VIN = Vee or GND (Note 5)
VIN = Vee or GND (Note 6)
VIN = VIH or VIL (Note 6)
Fose = 4.194304 MHz or
4.9152 MHz
VIN = Vee or GND (Note 6)
VIN = VIH or VIL (Note 6)
Vss = GND
VIN = Vee or GND
Fose = 32.768 kHz
Fose = 4.9152 MHz or
4.194304 MHz
Vee = GND
OSC OUT = Open Circuit,
Other Pins = GND
Fose = 32.768 kHz
Fose = 4.9152 MHz or
4.194304 MHz
Min
2.0
Vss -0.1
Max
0.8
0.1
Vee -0.1
3.5
0.1
0.25
±1.0
±5.0
Units
V
V
V
V
V
V
V
V
,....A
,....A
±5.0
,....A
260
1.0
12.0
,....A
rnA
rnA
8
20
rnA
rnA
80
7.5
,....A
mA
10
400
,....A
,....A
2.2V ~ Vss ~ 4.0V
Other Pins at GND
1.5
p,A
Vee = GND, Vss = 4.0V
-5
p,A
Vee = 5.5V, Vss = 2.2V
~ote 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: For Fosc = 4.194304 or 4.9152 MHz, VBB minimum = 2.8V. In battery backed mode, VBB s: Vcc -0.4V.
Single Supply Mode: Data retention voltage is 2.2V min.
In single Supply Mode (Power connected to VCC pin) 4.5V s: Vcc s: 5.5V.
Note 4: This parameter (VI H) is not tested on all pins at the same time.
Note 5: This specification tests Icc with all power fail circuitry disabled, by setting D7 of Interrupt Control Register 1 to O.
Note 6: This specification tests Icc with all power fail circuitry enabled, by setting D7 of Interrupt Control Register 1 to 1.
Note 7: This specification is tested with both the timers and ase IN driven by a signal generator. Contents of the Test Register = OO(H), the MFa pin is not
configured as buffered oscillator out and MFa, T1, INTR, are configured as open drain.
Note 8: This specification is tested with both the timers off, and only asc IN is driven by a signal generator. Contents of the Test Register = OO(H) and the MFa
pin is not configured as buffered oscillator out.
ISLK
Battery Supply Leakage
2·6
AC Electrical Characteristics
VCC = 5V
± 10%, VBB
Symbol
= 3V, VPFAIL
I
> VIH, CL
= 100 pF (unless otherwise specified)
I
Parameter
Min
I
I
Max
Units
READ TIMING
tAR
Address Valid Prior to Read Strobe
20
tRW
Read Strobe Width (Note 9)
80
tco
Chip Select to Data Valid Time
tRAH
Address Hold after Read (Note 10)
tRO
Read Strobe to Valid Data
ns
ns
80
ns
70
ns
60
ns
3
ns
toz
Read or Chip Select to TRI-STATE
tRCH
Chip Select Hold after Read Strobe
0
ns
tos
Minimum Inactive Time between Read or Write Accesses
50
ns
tAW
Address Valid before Write Strobe
20
ns
tWAH
Address Hold after Write Strobe (Note 10)
3
ns
tcw
Chip Select to End of Write Strobe
90
ns
WRITE TIMING
tww
Write Strobe Width (Note 11)
80
ns
tow
Data Valid to End of Write Strobe
50
ns
tWOH
Data Hold after Write Strobe (Note 10)
3
ns
0
ns
Chip Select Hold after Write Strobe
tWCH
TIMER O/TIMER 1 TIMING
FTCK
Input Frequency Range
10
MHz
tCK
Propagation Delay Clock to Output ...fl..
DC
120
ns
tGO
Propagation Delay GO to G 1
to Timer Output (Note 12) ...tr
100
ns
tpGW
Pulse Width GO or G1 ...fl... (Note 12)
25
ns
tGS
Setup Time, GO, G1 to TCK (Note 13)
100
ns
INTERRUPT TIMING
I
I
I
I
Clock Rollover to INTR Out is Typically 16.5 Ils
tROLL
Note 9: Read Strobe width as used in the read timing table is defined as the period when both chip select and read inputs are low. Hence read commences when
both signals are low and terminates when either signal returns high.
Note 10: Hold time is guaranteed by design but not production tested. This limit is not used to calculate outgoing quality levels.
Note 11: Write Strobe width as used in the write timing table is defined as the period when both chip select and write inputs are low. Hence write commences when
both signals are low and terminates when either signal returns high.
Note 12: Timers in Mode 3.
Note 13: Guaranteed by design, not production tested. This limit is not used to calculate outgoing quality levels.
AC Test Conditions
Input Pulse Levels
Input Rise and Fall Times
Input and Output
Reference Levels
TRI-STATE Reference
Levels (Note 15)
GNDt03.0V
6 ns (10%-90%)
1.3V
Vee
Active High + O.5V
Active Low -0.5V
1
Note 14: CL = 100 pF, includes jig and scope capacitance.
Note 15: Sl = Vee for active low to high impedance measurements.
S1 = GND for active high to high impedance measurements.
Sl = open for all other timing measurements.
Capacitance
Symbol
CIN
Input 0---
Input Capacitance
Typ
Units
5
pF
Device
Under
Test
~
(TA = 25°C, f = 1 MHz)
Parameter
(Note 16)
s,
(Note 15)
0
-r
Output Capacitance
7
pF
COUT
Note 16: This parameter is not HiO% tested.
Note 17: Output rise and fall times 25 ns max (10%-90%) with 100 pF load.
2-7
:;
)~
~ RL =lK .n
~
*
Output
_ .... C
L
(Note 14)
TLIF/8638-23
<
o
[t;
Timing Waveforms
co
c..
C
Read Timing Diagram
AO-4
'RCH
~----------'Rw----------~,~--~I
DATA
Valid Data
TL/F/6636-24
Write Timing Diagram
AO-4
I----------tcw-----------I
----+-"1
~--------tww-----------.I
---~-,I
I:=t
DATA
J---" ,
1
--------------<,
DW - - -
Valid Data
TL/F/6636-25
2-8
~--------------------------------------------------------------~C
General Description
used then this pin must be tied to ground, the TCP programmed for single power supply only, and power applied to
the Vee pin.
(Continued)
The DP8570A's interrupt structure provides four basic types
of interrupts: Periodic, Alarm/Compare, Timer, and Power
Fail. Interrupt mask and status registers enable the masking
and easy determination of each interrupt.
TCK, G1, GO, (Inputs), T1 (Output): TCK is the clock input
to both timers when they have an external clock selected. In
modes 0, 1, and 2, GO and G1 are active low enable inputs
for timers a and 1 respectively. In mode 3, GO and G1 are
positive edge triggers to the timers. T1 is dedicated to the
timer 1 output. The T1 output can be programmed active
high or low, push-pull or open drain. Timer 0 output is available through MFO pin if desired. If in battery backed mode
and a pull-up resistor is attached to T1, it should be connected to a voltage no greater than Vss. The T1 pin is configured open drain during battery operation (Vss > Vee).
One dedicated general purpose interrupt output is provided.
A second interrupt output is available on the Multiple Function Output (MFO) pin. Each of these may be selected to
generate an interrupt from any source. Additionally, the
MFO pin may be programmed to be either as oscillator output or Timer a's output.
Pin Description
CS, RD, WR (Inputs): These pins interface to J.LP control
lines. The CS pin is an active low enable for the read and
write operations. Read and Write pins are also active low
and enable reading or writing to the TCP. All three pins are
disabled when power failure is detected. However, if a read
or write is in progress at this time, it will be allowed to complete its cycle.
Vee: This is the main system power pin.
GND: This is the common ground power pin for both Vss
and Vee.
Connection Diagrams
Dual-ln-L1ne
AO-A4 (Inputs): These 5 pins are for register selection.
They individually control which location is to be accessed.
These inputs are disabled when power failure is detected.
OSC IN (Input): OSC OUT (Output): These two pins are
used to connect the crystal to the internal parallel resonant
oscillator. The oscillator is always running when power is
applied to Vss and Vee, and the correct crystal select bits in
the Real Time Mode. Register have been set.
MFO (Output): The multi-function output can be used as a
second interrupt output for interrupting the J.LP. This pin can
also provide an output for the oscillator or the internal Timer
O. The MFO output can be programmed active high or low,
open drain or push-pull. If in battery backed mode and a
pull-up resistor is attached, it should be connected to a voltage no greater than Vss. This pin is configured open drain
during battery operation (Vss > Vee).
cs
vcc
RD
ViR
TCK
AO
07
Al
06
A2
05
A3
04
A4
03
Gl
02
prAll
Tl
00
Vee
OSC IN
INTR
OSC OUT
t.lro
GNO
INTR (Output): The interrupt output is used to interrupt the
processor when a timing event or power fail has occurred
and the respective interrupt has been enabled. The INTR
output can be.programmed active high or low, push-pull or
open drain. If in battery backed mode and a pull-up resistor
is attached, it should be connected to a voltage no greater
than Vss. This pin is configured open drain during battery
operation (Vss > Vee). The output is a DC voltage level. To
clear the INTR, write a 1 to the appropriate bit(s) in the Main
Status Register.
GO
TL/F/8638-5
Top View
Order Number DP8570AN
See NS Package Number N28B
Plastic Chip Carrier
00-07 (Input/Output): These 8 bidirectional pins connect
to the host J.LP'S data bus and are used to read from and
write to the TCP. When the PFAIL pin goes low and a write
is not in progress, these pins are at TRI-STATE.
25
Al
PFAIL (Input): In battery backed mode, this pin can have a
digital signal applied to it via some external power detection
logic. When PFAIL = logic a the TCP goes into a lockout
mode, in a minimum of 30 J.Ls or a maximum of 63 J.Ls unless
lockout delay is programmed. In the single power supply
mode, this pin is not useable as an input and should be tied
to Vee. Refer to section on Power Fail Functional Description.
07
A2
06
A3
05
A4
04
Gl
03
T1
10
02
Vee
11
01
~ § ~ 8 ~ ~ 8
o
Vaa (Battery Power Pin): This pin is connected to a backup power supply. This power supply is switched to the internal circuitry when the Vee becomes lower than Vss. Utilizing this pin eliminates the need for external logic to switch in
and out the back-up power supply. If this feature is not to be
~
o
TL/F/8638-6
Top View
Order Number DP8570A V
See NS Package Number V28A
2-9
"tJ
0)
CJ1
""'-I
o
l>
~
"C:"7'.-
DP8570A
-n
t:
Interrupt Control Registers
Real
Timer
Periodic
Pulse
Signals
(also to
Periodic
nags)
!.lain Status
Register
Interrrupt Control
Registers
0010- t...d-
~
,,
...
:l
Interrupt Routing
Register
n
Buffered Oscillator
O·
Output !.lode Register
Control Register
Bits
:l
e!-
Timer 0
O
C'D
en
n
~.
!.IFO output
...O·
'C
:l
Interrupt
!.lode
Selected
Alarm
Compare
Signals
~
.",.
oo
Output
Buffer
:a-S·
t:
Battery Switchover
Vee
~
V+
..
Power
Fail Logic
Lockout
prAlL
(External
power fail
signal)
Delayed
Lockout
---t
~-....
Delay
Enable
Data
Address
and
Control
Buffers
00:07
AO:A4
3
CS,iffi,WR
TL/F/B63B-B
FIGURE 6. System-Battery Swltchover (Upper Left), Power Fail
and Lock-Out Circuits (Lower Right)
After the generation of a lock-out signal, and eventual
switch in of the battery supply, the pins of the TCP will be
configured as shown in Table II. Outputs that have a pull-up
resistor should be connected to a voltage no greater than
The user may choose to have this power failed signal lockout the TCP's data bus within 30 I1-s min/63 I1-s max or to
delay the lock-out to enable I1-P access after power failure is
detected. This delay is enabled by setting the delay enable
bit in the Routing Register. Also, if the lock-out delay was
not enabled the TCP will disconnect itself from the bus within 30 I1-s min ~ 63 I1-s max. If chip select is low when a
power failure is detected, a safety circuit will ensure that if a
read or write is held active continuously for greater than
30 I1-s after the power fail signal is asserted, the lock-out will
be forced. If a lock-out delay is enabled, the OP8570A will
remain active for 480 J.Ls after power fail is detected. This
will enable the I1-P to perform last minute bookkeeping before total system collapse. When the host CPU is finished
accessing the TCP it may force the bus lock-out before
480 I1-s has elapsed by resetting the delay enable bit.
The battery switch over circuitry is completely independent
of the PFAIL pin. A separate circuit compares Vee to the
Vee voltage. As the main supply fails, the TCP will continue
to operate from the Vee pin until Vee falls below the Vee
voltage. At this time, the battery supply is switched in, Vee is
disconnected, and the device is now in the standby mode. If
indeterminate operation of the battery switch over circuit is
to be avoided, then the voltage at the Vee pin must not be
allowed to equal the voltage at the Vee pin.
Vee·
TABLE II. Pin Isolation during a Power Failure
Pin
CS, RD,WR
AO-A4
00-07
Oscillator.
TCK, GO, G1
PFAIL
INTR, MFO
T1
PFAIL =
Logic 0
Standby Mode
Vee> Vee
Locked Out
Locked Out
Locked Out
Not Isolated
Not Isolated
Not Isolated
Locked Out
Locked Out
Locked Out
Not Isolated
Locked Out
Not Isolated
Not Isolated
Open Drain
The Timer and Interrupt Power Fail Operation bits in the
Real-Time Mode Register determine whether or not the timers and interrupts will continue to function after a power fail
event.
As power returns to the system, the battery switch over circuit will switch back to Vee power as soon as it becomes
greater than the battery voltage. The chip will remain in the
locked out state as long as PFAIL = O. When PFAIL = 1
2-15
«
o
......
Il)
CO
a..
C
Functional Description (Continued)
the chip is unlocked, but only after another 30 p,s min ~
63 p,s max debounce time. The system designer must ensure that his system is stable when power has returned.
TIMER FUNCTIONAL DESCRIPTION
The DP8570A contains 2 independent multi-mode timers.
Each timer is composed of a 16-bit negative edge triggered
binary down counter and associated control. The operation
is similar to existing p,P peripheral timers except that several
features have been enhanced. The timers can operate in
four modes, and in addition, the input clock frequency can
be selected from a prescaler over a wide range of frequencies. Furthermore, these timers are capable of generating
interrupts as well as hardware output signals, and both the
interrupt and timer outputs are fully programmable active
high, or low, open drain, or push-pull.
Figure 7 shows the functional block diagram of one of the
timers. The timer consists of a 16-bit counter, two 8-bit input
registers, two 8-bit output registers, clock prescaler, mode
control logic, and output control logic. The timer and the
data registers are organized as two bytes for each timer.
Under normal operations a read/write to the timer locations
will read or write to the data input register. The timer contents can be read by setting the counter Read bit (RD) in the
timer control register.
The power fail circuitry contains active linear circuitry that
draws supply current from Vee. In some cases this may be
undesirable, so this circuit can be disabled by masking the
power fail interrupt.· The power fail input can perform all
lock-out functions previously mentioned, except that no external interrupt will be issued. Note that the linear power fail
circuitry is switched off automatically when using Vss in
standby mode.
LOW BATTERY, INITIAL POWER ON DETECT, AND
POWER FAIL TIME SAVE '
There are three other functions provided on the DP8570A to
ease power supply control. These are an initial Power On
detect circuit, which also can be used as a time keeping
failure detect, a low battery detect circuit, and a time save
on power failure.
On initial power up the Oscillator Fail Flag will be set to a
one and the real time clock start bit reset to a zero. This
indicates that an oscillator fail event has occurred, and time
keeping has failed.
TIMER INITIALIZATION
The timer's operation is controlled by a set of registers, as
listed in Table III. These consist of 2 data input registers and
one control register per timer. The data input registers contain the timers count down value. The Timer Control Registeris used to set up the mode of operation and the input
clock rate. The timer related interrupts can be controlled by
programming the Interrupt Routing Register and Interrupt
Control Register o. The timer outputs are configured by the
Output Mode Register.
The Oscillator Fail flag will not be reset until the real-time
clock is started. This allows the system to discriminate between an initial power-up and recovery from a power failure.
If the battery backed mode is selected, then bit 06 of the
Periodic Flag Register must be written low. This will not affect the contents of the Oscillator Fail Flag.
Another status bit is the low battery detect. This bit is set
only when the clock is operating under the Vee pin, and
when the battery voltage is determined to be less than 2.1 V
(typical). When the power fail interrupt enable bit is low, it
disables the power fail circuit and will also shut off the low
battery voltage detection circuit as well.
TABLE III. Timer Associated Registers
To relieve CPU overhead for saving time upon power failure,
the Time Save Enable bit is provided to do this automatically. (See also Reading the Clock: Latched Read.) The Time
Save Enable bit, when set, causes the Time Save RAM to
follow the contents of the clock. This bit can be reset by
software, but if set before a power failure occurs, it will automatically be reset when the clock switches to the battery
supply (not when a power failure is detected by the PFAIL
pin). Thus, writing a one to the Time Save bit enables both a
softwa~e write or power fail write.
.
SINGLE POWER SUPPLY APPLICATIONS
The DP8570A can be used in a single power supply application. To achieve this, the Vss pin must be connected to
ground, and the power connected to Vee and PFAIL pins.
The Oscillator Failed/Single Supply bit in the Periodic Flag
Register should be set to a logic 1, which will disable the
oscillator battery reference circuit. The power fail interrupt
should also be disabled. This will turn off the linear power
fail detection circuits, and will eliminate any quiescent power
drawn through these circuits. Until the crystal select bits are
initialized, the DP8570A may consume about 50 p,A due to
arbitrary oscillator selection at power on.
(This extra 50 p,A is not consumed if the battery backed
mode is selected).
Register Name
Register
Select
Page
Select
Address
Timer 0 Data MSB
Timer 0 Data LSB
Timer 0 Control Register
Timer 1 Data MSB
Timer 1 Data LSB
Timer 1 Control Register.
Interrupt Routing Register
Interrupt Control Reg. 0
Output Mode Register
X
X
0
X.
X
0
0
1
1
0
0
0
0
0
0
0
O.
0
10H
OFH
01H
12H
11H
02H
04H
03H
02H
All these registers must be initialized prior to starting the
timer(s). The Timer Control Register should first be set to
select the timer mode with the timer start/stop bit reset.
Then when the timer .is to be started the control register
shoul~ be rewritten identically butwith the start/stop bit set.
TIMER OPERATION
Each timer is capable of operation in one of four modes. As
mentioned, these modes are programmed in each timer's
Control Register which is described later. All four modes
operate in a similar manner. They operate on the two 8-bit
data words stored into the Data Input Register. At the begin·
ning of a counting cycle the 2 bytes are loaded into the timer
and the timer commences counting down towards zero. The
exact action taken when zero is reached depends on the
mode selected, but in general, the timer output will change
state, and an interrupt will be generated if the timer interrupts are unmasked.
2-16
c
Functional Description
-a
co
(Continued)
U1
INPUT CLOCK SELECTION
together, so that when either is high the timers are suspended. Suspending the timer causes the same synchronization
error that starting the timer does. The range of errors is
specified in Table V.
The input frequency to the timers may be selected. Each
timer has a prescaler that gives a wide selection of clocking
rates. In addition, the DP8570A has a single external clock
input pin that can be selected for either of the timers. Table
IV shows the range of programmable clocks available and
the corresponding setting in the Timer Control Register.
C1
CO
Selected Clock
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
External
Crystal Oscillator
(Crystal Oscillator)/4
93.5 J.Ls (10.7 kHz)
1 ms (1 kHz)
10 ms (100 Hz)
1/10 Second (10Hz)
1 Second (1 Hz)
o
»
TABLE V. Maximum Synchronization Errors
Clock Selected
External
Crystal
Crystal/4
10.7 kHz
1 kHz
100 Hz
10 Hz
1 Hz
TABLE IV. Programmable Timer Input Clocks
C2
......
Error
+ Ext. Clock Period
+ 1 Crystal Clock Period
+ 1 Crystal Clock Period
+32 J.Ls
+32 J.Ls
+32J.Ls
+32J.Ls
+32J.Ls
MODES OF OPERATION
Bits MO and M1 in the Timer Control Registers are used to
specify the modes of operation. The mode selection is described in Table VI.
Note that the second and third selections are not fixed frequencies, but depend on the crystal oscillator frequency
chosen.
TABLE VI. Programmable Timer Modes of Operation
M1
MO
Function
Modes
0
0
1
1
0
1
0
1
Single Pulse Generator
Rate Generator, Pulse Output
Square Wave Output
Retriggerable One Shot
Mode 0
Mode 1
Mode 2
Mode 3
Since the input clock frequencies are usually running asynchronously to the timer Start/Step control bit, a 1 clock cycle error may result. This error results when the Start/Stop
occurs just after the clock edge (max error). To minimize
this error on all clocks an independent prescaler is used for
each timer and is designed so that its Start/Stop error is
less than 1 clock cycle.
MODE 0: SINGLE PULSE GENERATOR
The count hold/gate bit in the Timer Control Register and
the external enable pins, GO/G1, can be used to suspend
the timer operation in modes 0, 1, and 2 (in mode 3 it is the
trigger input). The external pin and the register bit are OR'ed
When the timer is in this mode the output will bo initially low
if the Timer Start/Stop bit is low (stopped). Whon this modo
is initiated the timer output will go high on the next falling
edge of the prescaler's input clock, the contents
Internal Oata Bus
32KHz
Prescaler
Logic
TImer
Output
Crystal Clock
External Clock
TImer
Start/Stop
Gate
Control
Logic
Selected Clock
Clock
} Select
Gate
TImer Start/Slop
lAode 0
lAodel
RD Bit
TL/F/8638-9
FIGURE 7. DP8570A Timer Block Diagram
2-17
Ell
o<
.....
Lt)
CO
D..
C
Functional Description (Continued)
of the input data registers are loaded into the timer. The
output will stay high until the counter reaches zero. At zero
the output is reset. The result is an output pulse whose duration is equal to the input clock period times the count
value (N) loaded into the input data register. This is shown
in Figure 8.
Pulse Width = Clock Period x N
for one clock period of the timer clock. Then on the next
clock the counter is reloaded automatically and the countdown repeats itself. The output, shown in Figure 9, is a
waveform whose pulse width and period is determined by N,
the input register value, and the input clock period:
An interrupt is generated when the zero count is reached.
This can be used for one-time interrupts that are set to occur a certain amount of time in the future. In this mode the
Timer Start/Stop bit (TSS) is automatically reset upon zero
detection. This removes the need to reset TSS before starting another operation.
The GO or G1 pin and the count hold/gate bit can be used
to suspend the appropriate timer countdown when either is
high. Again, the output polarity is controllable as in mode o.
If enabled, an interrupt is. generated whenever the zero
count is reached. This can be used to generate a periodic
interrupt.
Period = (N + 1) (Clock Period)
Pulse Width = Clock Period
The count down operation may be temporarily suspended
either under software control by setting the Count Hold/
Gate bit in the timer register high, or in hardware by setting
the GO or G1 pin high.
MODE 2: SQUARE'WAVE GENERATOR
This mode is also cyclic but in this case a square wave
rather than a pulse is generated. The output square wave
period is determined by the value loaded into the timer input
register. This period and the duty cycle are:
Period = 2(N + 1) (Clock Period)
Duty Cycle = 0.5
The above discussion assumes that the timer outputs were
programmed to be non-inverting outputs (active high). If the
polarity of the output waveform is wrong for the application
the polarity can be reversed by configuring the Output Mode
Register. The drive configuration can also be programmed
to be push pull or open drain.
When the timer is stopped the output wi" be low, and when
the Start/Stop bit is set high the timer's counter will be loaded on the next clock falling transition and the output will be
set high.
The output will be toggled after the zero count is detected
and the counter will then be reloaded, and the cycle will
continue. Thus, every N + 1 counts the output gets toggled,
as shown in Figure 10. Like the other modes the timer operation can be suspended either by software setting the count
hold/gate bit (CHG) in the Timer Control Register or by using the gate pins. An interrupt wiIJ be generated every falling
edge of the timer output, if enabled.
MODE 1: RATE GENERATOR
When operating in this mode the timer will operate continuously. Before the timer is started its output is low. When the
timer is started the input data register contents are loaded
into the counter on the negative clock edge and the output
is set high (again assuming the Output Mode Register is
programmed active high). The timer will then count down to
zero. Once the zero count is reached the output goes low
1
N
1 N-ll N-2 1
1 1 .10 1
Internal
Counter
Clock
TImer
Start/Stop
Count Hold/
Gate Bit
TImer
Output
TL/F/8638-10
FIGURE 8. Typical Waveforms for Timer Mode 0
(Timer Output Programmed Active High)
Internal
Counter
Clock
TImer
Start/Stop
Count Hold/
Gate Bit
TImer
Output
TL/F18638-11
FIGURE 9. Timing Waveforms for Timer Mode 1
(Timer Output Programmed Active High)
2-18
c
Functional Description
-a
0)
(Continued)
1312111013121
U1
read. Experimental results indicate that the typical error rate
Is approximately one per 29,000 under the following conditions:
101
Internal
Counter
Clock
TImer
Start/Stop
.......
o
»
Timer clock frequency of 5 MHz.
Computer: 386/33 MHz PCI AT
Count Hold/
Gate Bit
Program:
TImer
Output
Those users who find the error rate unacceptable may reduce the problem effectively to zero by employing a hardware work-around that synchronizes the writing of the read
bit to the timer control register with respect to the decrementing clock. Refer to Figure 1 in Appendix A, for a suggested hardware work-around.
TLIF/8638-12
FIGURE 10. Timing Waveforms for Timer Mode 2
(Timer Output Programmed Active High)
MODE 3: RETRIGGERABLE ONE SHOT
A software work-around can reduce the errors but not as
substantial as a hardware work-around. Software workarounds are based on observations that the read following a
bad read appeared to be valid.
This mode is different from the previous three modes in that
this is the only mode which uses the external gate to trigger
the output. Once the timer StartlStop bit is set the output
stays inactive, and nothing happens until a positive transition is received on the G1 or GO pins, or the Count Holdl
Gate (CHG) bit is set in the timer control register. When a
transition ocurs the one shot output is set active immediately; the counter is loaded with the value in the input register
on the next transition of the input clock and the countdown
begins. If a retrigger occurs, regardless of the current counter value, the counters will be reloaded with the value in the
input register and the counter will be restarted without
changing the output state. See Figure 11. A trigger count
can occur at any time during the count cycle and can be a
hardware or software signal (GO, G1 or CHG). In this mode
the timer will output a single pulse whose width is determined by the value in the input data register (N) and the
input clock period.
Pulse Width = Clock Period
Microsoft "C" 6.0, reading and saving timer contents in a continuous loop.
This problem concerns statistical probability and is similar to
metastability issues. For more information on metastability,
refer to 1991 IEEE transactions on Custom Integrated Circuits Conference. paper by T.J. Gabara of AT&T Bell Laboratories, page 29.4.1.
Normally reading the timer data register addresses, OFH
and 1OH for Timer 0 and 11 Hand 12H for Timer 1 will result
in reading the input data register which contains the preset
value for the timers.
To read the contents of a timer, the J-LP first sets the timer
.read bit in the appropriate Timer Control Register high. This
will cause the counters contents to be latched to 2-bit-8-bit
output registers, and will enable these registers to be read if
the J-LP reads the timers input data register addresses. On
reading the LSB byte the timer read bit is internally reset
and subsequent reads of the timer locations will return the
input register values.
xN
Before entering mode 3, if a spurious edge has occurred on
GO/G1 or the CHG bit is set to logic 1, then a pulse will
appear at MFO or T1 or INTR output pin when the timer is
started. To ensure this does not happen, do the following
steps before entering mode 3: Configure the timer for mode
0, load a count of zero, then start the timer.
DETAILED REGISTER DESCRIPTION
There are 5 external address bits: Thus, the host microprocessor has access to 32 locations at one time. An internal
switching scheme provides a total of 67 locations.
The timer will generate an interrupt only when it reaches a
count of zero. This timer mode is useful for continuous
"watch dog" timing, line frequency power failure detection,
etc.
This complete address space is organized into two pages.
Page 0 contains two blocks of control registers, timers, real
time clock counters, and special purpose RAM, while page
1 contains general purpose RAM. Using two blocks enables
the 9 control registers to be mapped into 5 locations. The
only register that does not get switched is the Main Status
Register. It contains the page select bit and the register
select bit as well as status information.
READING THE TIMERS
National has discovered that some users may encounter
unacceptable error rates for their applications when reading
the timers on the fly asynchronously. When doing asynchronous reads of the timers, an error may occur. The error is
that a successive read may be larger than the previous
A memory map is shown in A'gure 2 and register addressing
in Table VII. They show the name, address and page locations for the DP8570A.
1013121110101312131211101
•
Internal
Counter
Clock
TImer
Start/Stop
~~~~tB~Old/
Timer
Output
~,.+-----..LJl9\Lfl
_ _ _......
L
TL/F/8638-13
FIGURE 11. Timing Waveforms for Timer Mode 3, Output Programmed Active High
2-19
«
o
r-...
LI)
Functional Description
CX)
(Continued)
TABLE VII. Register/Counter/RAM
Addressing for OP8570A
D-
C
AO-4
PS
RS
(Note 1) (Note 2)
MAIN STATUS REGISTER
I PS I RS I Tll TO I ALI PERI PFlINTI
L
Description
CONTROL REGISTERS
00
01
02
03
04
01
02
03
04
X
0
0
0
0
0
0
0
0
X
0
0
0
0
1
1
1
1
0
0
0
0
0
X
X
X
X
X
OA
OB
OC
00
OE
0
0
0
0
0
X
X
X
X
X
03 Alarm Interrupt
04 TImer 0 Interrupt
05 TImer 1 Interrupt
06 Register Select Bit
07 Page Select Bit
TLlF/B63B-14
The Main Status Register is always located at address 0
regardless of the register block or the page selected.
1/100,1/10 Seconds (0-99)
(0-59)
Seconds
(0-59)
Minutes
(1-12,0-23)
Hours
Days of
Month
(1-28/29/30/31 )
(1-12)
Months
(0-99)
Years
Julian Date (LSB)
(0-99) (Note 3)
(0-3)
Julian Date
(1-7)
Day of Week
DO: This read only bit is a general interrupt status bit that is
taken directly from the interrupt pins. The bit is a one when
an interrupt is pending on either the INTR pin or the MFO
pin (when configured as an interrupt). This is unlike 03-05
which can be set by an internal event but may not cause an
interrupt. This bit is reset when the interrupt status bits in the
Main Status Register are cleared.
01-05: These five bits of the Main Status Register are the
main interrupt status bits. Any bit may be a one when any of
the interrupts are pending. Once an interrupt is asserted the
p.P will read this register to determine the cause. These
interrupt status bits are not reset when read. Except forD1,
to reset an interrupt a one is written back to the corresponding bit that is being tested. 01 is reset whenever the PFAIL
pin = logic 1. This prevents loss of interrupt status when
reading the register in a polled mode. 01, 03-05 are set
regardless of whether these interrupts are masked or not by
bits 06 and 07 of Interrupt Control Registers 0 and 1.
TIMER DATA REGISTERS
OF
10
11
12
0
0
0
0
X
X
X
X
Timer 0 LSB
TimerOMSB
Timer 1 LSB
Timer 1 MSB
TIME COMPARE RAM
(0-59)
(0-59)
13
14
15
0
0
0
X
X
X
16
0
X
17
0
X
18
0
X
Sec Compare RAM
Min Compare RAM
Hours Compare
RAM
DaM Compare
RAM
Months Compare
RAM
DOW Compare RAM
10
0
0
0
0
0
X
X
X
X
X
Seconds Time Save RAM
Minutes Time Save RAM
Hours Time Save RAM
Day of Month Time Save RAM
Months Time Save RAM
lE
1F
0
0
1
X
RAM
RAM/Test Mode Register
01-lF
1
X
2nd Page General Purpose RAM
06 and 07: These bits are Read/Write bits that control
which register block or RAM page is to be selected. Bit 06
controls the register block to be accessed (see memory
map). The memory map of the clock is further divided into
two memory pages. One page is the registers, clock and
timers, and the second page contains 31 bytes of general
purpose RAM. The page selection is determined by bit 07.
(1-12,0-23)
(1-28/29/30/31 )
(1-12)
(1-7)
TIME SAVE RAM
19
1A
1B
lC
01 Power rail Interrupt
02 Period Interrupt
Main Status Register
Timer 0 Control Register
Timer 1 Control Register
Periodic Flag Register
Interrupt Routing Register
Real Time Mode Register
Output Mode Register
Interrupt Control Register 0
Interrupt Control Register 1
COUNTERS (CLOCK CALENDAR)
05
06
07
08
09
00 Interrupt Status
Note 1: PS-Page Select (Bit 07 of Main Status Register)
Note 2: RS-Register Select (Bit 06 of Main Status Register)
Note 3: The LSB counters count 0-99 until the hundreds of days counter
reaches 3. Then the LSB counters count to 65 or 66 (if a leap year). The
rollover is from 365/366 to 1.
2-20
C
Functional Description
"C
en
(Continued)
CJ1
TIMER 0 AND 1 CONTROL REGISTER
00-05: These bits arc set by tho roal timo rollover events:
(Time Change = 1). The bits are reset when the register is
read and can be used as selective data change flags.
I CHGT RO I C2 I Cl I CO I 1.41 I 1.40 I TSSI
L
06: This bit performs a dual function. When this bit is read, a
one indicates that an oscillator failure has occurred and the
time information may have been lost. Some of the ways an
oscillator failure may be caused are: failure of the crystal;
shorting OSC IN or OSC OUT to GNO or Vee; removal of
crystal; removal of battery when in the battery backed mode
(when a '0' is written to 06); lowering the voltage at the Vss
pin to a value less than 2.2V when in the battery backed
mode. Bit 06 is automatically set to 1 on initial power-up or
an oscillator fail event. The oscillator fail flag is reset by
writing a one to the clock start/stop bit in the Real Time
Mode Register, with the crystal oscillating.
00 TImer Start/Stop
01 Mode Select
02 Mode Select
03 Input Clock Select
04 Input Clock Select
05 Input Clock Select
06 TImer Read
07 Count Hold/Gate
TL/F/6636-15
When 06 is written to, it defines whether the TCP is being
used in battery backed (normal) or in a single supply mode
application. When set to a one this bit configures the TCP
for single power supply applications. This bit is automatically
set on initial power-up or an oscillator fail event. When set,
06 disables the osc.illator reference circuit. The result is that
the oscillator is referenced to Vee. When a zero is written to
06 the oscillator reference is enabled, thus the oscillator is
referenced to Vss. This allows operation in standard battery
standby applications.
These registers control the operation of the timers. Each
timer has its own register.
00: This bit will Start (1) or Stop (0) the timer. When the
timer is stopped the timer's prescaler and counter are reset,
and the timer will restart from the beginning when started
again. In mode 0 on time out the TSS bit is internally reset.
01 and 02: These control the count mode of the timers.
See Table VI.
03-05: These bits control which clock signal is applied to
the timer's counter input. There is one external clock input
pin (TCK) and either (or both) timer(s) can be selected to
run off this pin: refer to Table IV for details.
At initial power on, if the OP8570A is going to be programmed for battery backed mode, the Vss pin should be
connected to a potential in the range of 2.2V to Vee O.4V.
06: This is the read bit. If a one is written into this location it
will cause the contents of the timer to be latched into a
holding register, which can be read by the ,uP at any time.
. Reading the least significant byte of the timer will reset the
RO bit. The timer read cycle can be aborted by writing RO to
zero.
For single supply mode operation, the Vss pin should be
connected to GNO and the PFAIL pin connected to Vee .
07: Writing a one to this bit enables the test mode register
at location 1F (see Table VII). This bit should be forced to
zero during initialization for normal operation. If the test
mode has been entered, clear the test mode register before
leaving test mode. (See separate test mode application
note for further details.)
07: The CHG bit has two mode dependent functions. In
modes 0 through 2 writing a one to this bit will suspend the
timer operation (without resetting the timer prescaler). However, in mode 3 this bit is used to trigger or re-trigger the
count sequence as with the gate pins. If retriggering is desired using the CHG bit, it is not necessary to write a zero to
this location prior to the re-trigger. The action of further writing a one to this bit will re-trigger the count.
INTERRUPT ROUTING REGISTER
I TS I LB IPFDIT1RITORIA LRI PRRI PFRI
L
PERIOOIC FLAG REGISTER
TM
OSf 1m. 10ms 100m.' 15
01 Periodic route
02 Alarm route
10s11 min I
I L:
00 Power fail route
DO minutes flag
03 TImer 0 route
01 10 second flag
04 TImer 1 route
02 seconds flag
05 PF Oelay Enable
03 100 mllllsec. flag
04 10 mllllsec. flag
06 Low Battery flag
05 mUll-seconds flag
07 TIme Save Enable
06 Oscillator faU.d/Slng~. Supply
TL/F 16636-17
00-04: The lower 5 bits of this register are associated with
the main interrupt sources created by this chip. The purpose
of this register is to route the interrupts to either the MFO
(multi-function pin), or to the main interrupt pin. When any
bit is set the associated interrupt signal will be sent to the
MFO pin, and when zero it will be sent to the INTR pin.
07 Test Mode Enable
TLlF/6636-16
The Periodic Flag Register has the same bit for bit correspondence as Interrupt Control Register 0 except for 06
and 07. For normal operation (Le., not a single supply application) this register must be written to on initial power up or
after an oscillator fail event. 00-05 are read only bits, 06
and 07 are read/write.
2-21
.......
o
l>
Vee). They
will have to be re-configured when system (Vee) power is
..
restored.
05: This bit controls the ope~ati6n of the timers in standby
mode. If set to a one the timers will continue to function
when the TCP is in standby mode. The input pins TCK, GO,
G1 are locked out in standby mode, and cannot be used.
Therefore external control of the timers is not possible in
standby mode. Note also that MFO and T1 pins are automatically reconfigured open drain during standby.
REAL TIME MOOE REGISTER
I XT11 XTO I TPFIIPF IcsSI12H I LY1I LYOI
L
06 and 07: These two bits select the crystal clock frequency as per the following table:
00 Leap Year LSB
01 Leap Year folSB
02 12/24 hour mode
03 Clock Start/Stop
04 Interrupt· PF Operation
05 TImer PF Operation
XT1
XTO
Crystal
Frequency
0
0
1
1
0
1
0
1
32.768 kHz
4.194304 MHz
4.9152 MHz·
32.000 kHz
06 Crystal Frequency LSB
All bits are Read/Write, and any mode written into this register can be determined by reading the register. On initial
power up these bits are random.
07 Crystal Frequency folSB
TL/F18638-18
00-01: These are the leap year counter bits. These bits are
written to set the number of years from the previous leap
year. The leap year counter increments on December 31st
and it internally enables the February 29th counter state.
This method of setting the leap year allows leap year to
occur whenever the user wishes to, thus providing flexibility
in implementing Japanese leap year function.
LY1
LYO
Leap Year
Counter
0
0
1
1
0
1
0
1
Leap Year Current Year
Leap Year Last Year
Leap Year 2 Years Ago
Leap Year 3 Years Ago
OUTPUT MOOE REGISTER
I lAO I IAT I lAP I IAH I IP I IH I TP I TH I
IL:
DO Tl Active HI/Low
01 Tl Push pull/Open Drain
02 INTR Active HI/Low
03 INTR Push pull/Open Drain
05 t.lrO Push pull/Open Drain
04 IAro Active HI/Low
06 t.lFO pin as TImer 0
07 t.lrO Pin as Oscillator
TL/F/8638-19
2-22
Functional Description
(Continued)
00: This bit, when set to a one makes the T1 (timer 1)
output pin active high, and when set to a zero, it makes this
pin active low.
periodic time chosen, but after the first interrupt all subsequent interrupts will be spaced correctly. These interrupts
are useful when minute, second, real time reading, or task
switching is required. When all six bits are written to a 0 this
disables periodic interrupts from the Main Status Register
and the interrupt pin.
01: This bit controls whether the T1 pin is an open drain or
push-pull output. A one indicates push pull.
02: This bit, when set to a one makes the INTR output pin
active high, and when set to a zero, it makes this pin active
low.
06 and 07: These are individual timer enable bits. A one
written to these bits enable the timers to generate interrupts
to the J.LP.
03: This bit controls whether the INTR pin is an open drain
or push-pull output. A one indicates push-pull.
INTERRUPT CONTROL REGISTER 1
04: This bit, when set to a one makes the MFO output pin
active high, and when set to a zero, it makes this pin active
low.
I pre I ALe I DOMI MO IDOMI HR I MN I SC I
IL=
05: This bit controls whether the MFO pin is an open drain
or push-pull output. A one indicates push-pull.
06 and 07: These bits are used to program the signal appearing at the MFO output, as follows:
DO Second compare enable
Dl I.linute compare enable
D2 Hour compare enable
D3 Day of month enable
04 I.lonth compare enable
07
06
MFO Output Signal
0
0
1
0
1
2nd Interrupt
Timer 0 Waveform
Buffered Crystal Oscillator
X
05 Day of week enable
06 Alarm interrupt enable
07 Power fail interrupt enable
TLIF/8638-21
00-05: Each of these bits are enable bits which will enable
a comparison between an individual clock counter and its
associated compare RAM. If any bit is a zero then that
clock-RAM comparator is set to the "always equal" state
and the associated TIME COMPARE RAM byte can be used
as general purpose RAM. However, to ensure that an alarm
interrupt is not generated at bit 03 of the Main Status Register, all bits must be written to a logic zero.
INTERRUPT CONTROL REGISTER 0
I T1 I TO 11ml tmlhml S I TSI MNI
L
DO Minutes enable
01 10 second enable
02 Seconds enable
03 100 millisec enable
06: In order to generate an external alarm compare interrupt to the J.LP from bit 03 of the Main Status Register, this
bit must be written to a logic 1. If battery backed mode is
selected and the OP8570A is in standby (Vss > Vee), then
this bit is controlled by 04 of the Real Time Mode Register.
04 10 millisec enable
05 millisec enable
06 TImer 0 enable
07: The MSB of this register is the enable bit for the Power
Fail Interrupt. When this bit is set to a one an interrupt will
be generated to the J.LP when PFAIL = O. If battery backed
mode is selected and the OP8570A is in standby
(Vss > Vee), then this bit is controlled by 04 of the Real
Time Mode Register.
07 TImer 1 enable
TL/F/8638-20
If battery backed mode is selected and the OP8570A is in
standby (Vss > Vee), then all bits are controlled by 04 of
the Real Time Mode Register.
00-05: These bits are used to enable one of the selected
periodic interrupts by writing a one into the appropriate bit.
These interrupts are issued at the rollover of the clock. For
example, the minutes interrupt will be issued whenever the
minutes counter increments. In all likelihood the interrupt
will be enabled asynchronously with the real time change.
Therefore, the very first interrupt will occur in less than the
This bit also enables the low battery detection analog circuitry.
If the user wishes to mask the power fail interrupt, but utilize
the analog circuitry, this bit should be enabled, and the
Routing Register can be used to route the interrupt to the
MFO pin. The MFO pin can then be left open or configured
as the Timer 0 or buffered oscillator output.
2-23
Vee (Standby Mode).
10. Initialize the rest of the chip as needed.
Typical Application
Main Supply
-
~
r-
~
rv-v
:I"
I! "8
~.!:
....
Adc
0
'j.
Q)
A
ress Hus
~cs
II.
AO-A4
V'
CIl
CIl
u
ec..
eu
:i
~
Data 8us
'j
AD-A4
v
"v
00-07
~Control~
+--- A low going u
generated po wer
fall signal sho uld
be presented to the
PFAIL pin •
-
"
" 00-07
DP8570A
Timer
Clock
Peripheral
OSC IN
OSC OUT
A
RO WR INT
'j
-!T
Vee
PFAIL
A
8attery Supply
01'
I .....
I
Vee
.., u
Rl'
I~
T
"
RD
V'
WR
INTR
+--
IoIFO
----I1r
~2-22 pF
32.768KHz
47 PF
GNO
!
- .... -
·These components may be necessary to meet UL requirements
for lithium batteries. Consult battery manufacturer.
2-25
TLIF/8638-22
.......
o
l>
Vee.
Additionally, two supply pins are provided. When Vss
> Vee, internal circuitry will automatically switch from the
main supply to the battery supply. Status bits are provided
to indicate initial application of battery power, system power,
and low battery detect.
(Continued)
Features
• Full function real time clock/calendar
- .12/24 hour mode timekeeping
- Day of week and day of years counters
- Four selectable oscillator frequencies
- Parallel resonant oscillator
• Two 16-bit timers
- 10 MHz external clock freque'ncy
- Programmable multi-function output
- Flexible re-trigger facilities
• Power fail features
-Internal power supply switch to external battery
- Power Supply Bus glitch protection
- Automatic log of time into RAM at power failure
• On-Chip interrupt structure
- Periodic, alarm, timer and power fail interrupts
• Up to 44 bytes of CMOS RAM
• INTR/MFO pins programmable High/Low and push-pull
or open drain
Block Diagram
INTR
FIGURE 1
2-28
tolFO
osc
osc
out
In
TLlF/9979-1
Absolute Maximum Ratings
Operation Conditions
(Notes 1 & 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (Ved (Note 3)
Supply Voltage (Vss) (Note 3)
-0.5V to + 7.0V
Supply Voltage {Ved
DC Input Voltage (VIN)
DC Output Voltage (VOUT)
Storage Temperature Range
-0.5V to Vee +0.5V
-0.5V to Vee + 0.5V
- 65·C to + 150·C
Power Dissipation (PD)
Lead Temperature (Soldering, 10 sec.)
500mW
260·C
Min
4.5
Max
5.5
2.2 Vee- O.4
Unit
V
V
DC Input or Output Voltage
0.0
(VIN, VOUT)
-40
Operation Temperature (TA)
Electr-Static Discharge Rating TBD
Vee
V
+85
1
·C
Transistor Count
15,200
Typical Values
9JA DIP
Board
Socket
Board
Socket
9JA PLCC
kV
n·c/w
85·C/W
DC Electrical Characteristics
Vee
= 5V ± 10%, Vss = 3V, VPFAIL > VIH, CL = 100 pF (unless otherwise specified)
Symbol
Conditions
Min
VIH
High Level Input Voltage
(Note 4)
Parameter
Any Inputs Except OSC IN,
OSC IN with External Clock
2.0
Vss -0.1
VIL
Low Level Input Voltage
All Inputs Except OSC IN
OSC IN with External Clock
VOH
High Level Output Voltage
(Excluding OSC OUn
VOL
Low Level Output Voltage
(Excluding OSC OUn
= - 20 p-A
= -4.0 mA
lOUT = 20 p-A
lOUT = 4.0mA
VIN = Vee or GND
VOUT = Vee or GND
VOUT = Vee or GND
liN
Input Current (Except OSC IN)
loz
Output TRI-STATE® Current
ILKG
Output High Leakage Current
T1, MFa, INTR Pins
Icc
Quiescent Supply Current
(Note 7)
lOUT
lOUT
Outputs Open Drain
Fose = 32.768 kHz
VIN = Vee or GND (Note 5)
VIN = Vee or GND (Note 6)
VIN = VIH or VIL (Note 6)
Fose
4.9152 MHz
Quiescent Supply Current
(Single Supply Mode)
(Note 7)
Units
V
V
0.8
0.1
V
V
V
V
Vee -0.1
3.5
0.1
0.25
V
V
±1.0
p-A
±5.O
p-A
±5.O
p-A
260
1.0
12.0
p-A
mA
mA
8
20
mA
mA
80
7.5
p-A
mA
10
400
p-A
p-A
= 4.194304 MHz or
= Vee or GND (Note 6)
= VIH or VIL (Note 6)
Vss = GND
VIN = Vee or GND
Fose = 32.768 kHz
Fose = 4.9152 MHz or
VIN
VIN
Icc
Max
4.194304 MHz
ISS
Standby Mode Battery
Supply Current
(Note 8)
Vee = GND
OSC OUT = open circuit,
other pins = GND
Fose = 32.768 kHz
Fose = 4.9152 MHz or
4.194304 MHz
2.2V :0:; Vss :0:; 4.0V
other pins at GND
1.5
p-A
Vee = GND, Vss = 4.0V
-5
p-A
Vee = 5.5V, Vss = 2.2V
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: For Fosc = 4.194304 or 4.9152 MHz, Vss minimum = 2.SV.ln battery backed mode, Vss !S: Vcc -O.4V. Single Supply Mode: Oata retention voltage is
2.2V min. In Single Supply Mode (Power connected to Vcc pin) 4.5V !S: Vcc !S: 5.5V.
Note 4: This parameter (VI H) is not tested on all pins at the same time.
Note 5: This specification tests Icc with all power fail Circuitry disabled, by setting 07 of Interrupt Control Register 1 to O.
Note 6: This speCification tests Icc with all power fail circuitry enabled, by setting 07 of Interrupt Control Register 1 to 1.
Note 7: This specification is tested with both the timers and OSC IN driven by a signal generator. Contents of the Test Register = OO(H), the MFO pin is not
configured as buffered oscillator out and MFO, INTR, are configured as open drain.
Note 8: This specification is tested with both the timers off, and only OSC IN is driven by a Signal generator. Contents of the Test Register = OO(H) and the MFO
pin is not configured as buffered oscillator out.
ISLK
Battery, Supply Leakage
2-29
«
.....
r-Lt)
co
c..
C
AC Electrical Characteristics
Vcc = 5V ± 10%, Vss = 3V, VPFAIL
SYr:n bol
I
> VIH, CL
= 100 pF (unless otherwise specified)
I
Parameter
Min
I
I
Max
Units
READ TIMING
tAR
Address Valid Prior to Read Strobe
20
tRW
Read Strobe Width (Note 9)
80
tco
Chip Select to Data Valid Time
tRAH
Address Hold after Read (Note 10)
tRO
Read Strobe to Valid Data
ns
ns
80
ns
70
ns
3
ns
toz
Read or Chip Select to TRI-STATE
tRCH
Chip Select Hold after Read Strobe
0
60
ns
ns
tos
Minimum Inactive Timebetween Read or Write Accesses
50
ns
tAW
Address Valid before Write Strobe
20
ns
tWAH
Address Hold after Write Strobe (Note 10)
3
ns
tcw
Chip Select to End of Write Strobe
90
ns
tww
Write Strobe Width (Note 11)
80
ns
tow
Data Valid to End of Write Strobe
50
ns
twoH
Data Hold after Write Strobe (Note 10)
3
ns
tWCH
Chip Select Hold after Write Strobe
0
ns
WRITE TIMING
INTERRUPT TIMING
Clock rollover to INTR out is typically 16.5 I-'-S
tROLL
Note 9: Read Strobe width as used in the read timing table is defined as the period when both ~hip select and read inputs are low. Hence read commences when
both signals are low and terminates when either signal returns high.
Note 10: Hold time is guaranteed by design but not production tested. This limit is not used to calculate outgoing quality levels.
Note 11: Write Strobe width as used in the write timing table is defined as the period when both chip select and write inputs are low. Hence write commences when
both signals are low and terminates when either signal returns high.
AC Test Conditions
Input Pulse Levels
Input Rise and Fall Times
Input and Output
Reference Levels
TRI-STATE Reference
Levels (Note 13)
GNDt03.0V
6 ns (10%-90%)
Vee
1.3V
-r-
Active High + 0.5V
Active Low -0.5V
I
Note 12: CL = 100 pF, includes jig and scope capacitance.
Note 13: Sl = Vee for active low to high impedance measurements.
Sl = GND for active high to high impedance measurements.
Sl = open for all other timing measurements.
Capacitance
Symbol
Input 0 -
~
(TA = 25°C, f = 1 MHz)
Parameter
(Note 14)
Typ
Units
CIN
Input Capacitance
5
pF
COUT
Output Capacitance
7
pF
Device
Under
Test
Note 14: This parameter is not 100% tested.
Note 15: Output rise and fall times 25 ns max (10%-90%) with 100 pF load.
2-30
SI (Note 13)
0
'*
*
(
:.
=
RL lK .n
_ Output
_ .... C
L
(Note 12)
TL/F/9979-2
Timing Waveforms
Read Timing Diagram
AO-"
'RCH
~---------'Rw----------~·~--~I
DATA
Valid Data
TL/F/9979-3
Write Timing Diagram
AO-"
~---------tww----------~
------~--,I
IJ------, ,
i-
DATA
--------------------------(1(
tDW
-
Valid Data
TL/F/9979-4
2-31
Vee).
22 1-07
AO- 4
21
~06
A1- 5
20
~05
A2- 6
19
~04
A3- 7
18
~03
A4- 8
171-02
161-01
Vee - 9
OSC IN- 10
INTR (Output): The interrupt output is used to interrupt the,
processor when a timing event or power fail, has occurred
and the respective interrupt has been enabled. The INTR
output can be programmed active high or low, push-pull or
open drain. If in battery backed mode and a pull-up resistor
is attached, it should be connected to a voltage no greater '
than Vss. This pin is configured open drain during battery ,
operation (Vss > Vee). The output is a DC voltage level. To
clear the INTR, write a 1 to the appropriate bites) in the Main
Status Register.
24 I-Vcc
23 I-PF'AIL
2
151-00
OSC OUT- 11
141-INTR
GNO- 12
131-t.lF'O
TL/F/9979-5
Top View
Order Number DP8571AN
See NS Package Number N24C
DO-D7 (Input/Output): These 8 bidirectional pins connect
to the host ,..,P's data bus and are used to read from and
write to the TCP. When the PFAIL pin goes low and a write
is not in progress, these pins are at TRI-STATE.
2-32
· ...
~-,,,,,,,.
Functional Description
The OP85?1 A contains a fast access real time clock, two 10
MHz 16-bit timers, interrupt control logic, power fail detect
logic, and CMOS RAM. All functions of the TCP are controlled by a set of nine registers. A simplified block diagram
that shows the major functional blocks is given in Figure 1.
The memory map of the TCP is shown in the memory addressing table. The memory map consists of two 31 byte
pages with a main status register that is common to both
pages. A control bit in the Main Status Register is used to
select either page. Figure 2 shows the basic concept.
Page a contains all the clock timer functions, while page 1
has scratch pad RAM. The control registers are split into
two separate blocks to allow page 1 to be used entirely as
scratch pad RAM. Again a control bit in the Main Status
Register is used to select either control register block.
The blocks are described in the following sections:
1. Real Time Clock
2. Oscillator Prescaler
3. Interrupt Logic
4. Power Failure Logic
5. Additional Supply Management
6. Timers
Page Select = 0
lF'
RA~/TEST Register
lE
RA~
10
lC
18
. lA
~onths
Day of
RA~
TIme Save
RA~
Hours TIme Save
RA~
lE
RA~
10
RAM
lC
RAM
TIme Save
RA~
18
RAM
19
Seconds TIme Save
RA~
lA
RAM
18
Day of Week Compare
RA~
19
RAM
Compare RAM
Day of ~onth Compare RA~
18
RA~
17
RAM
17
16
15
14
13
~inutes
RA~
TIme Save
~onth
Page Select = 1
lF'
~onths
Hours Compare
RA~
Minutes Compare RAM
16
RA~
RAM
12
TImer 1
~S8
15
14
13
11
TImer 1 LS8
12
RAM
10
TImer 0 MS8
11
RAM
OF'
OE
TImer 0 LS8
10
RAM
Day of Week Clock Counter
RA~
00
100's Julian Clock Counter
OF'
OE
OC
Units Julian Clock Counter
00
RA~
08
Years Clock Counter
OC
RAM
OA
09
08
Months Clock Counter
07
Minutes Clock Counter
08
OA
09
08
RAM
Day of Month Clock Counter
06
Seconds Clock Counter
07
RAM
05
Y,oo Second Counter
06
RAM
Register Select
Seconds Compare RAM
Hours Clock Counter
=0 /
Register Select
=1
RAM
RAM
RA~
RAM
RAM
RAM
05
RA~
04
RAM
03
RAM
RAM
RAM
00
I
~ain Status Register
TlIF/9979-6
FIGURE 2. DP85?1A Internal Memory Map
2-33
.........<
I.t)
co
a.
C
r---------------------------------------------------~----------~
Functional Description
(Continued)
INITIAL POWER-ON of BOTH VBB and Vee
Save Enable bit (D7) of the Interrupt Routing Register, and
then to write a zero. Writing a one into this bit will enable the
clock contents to be duplicated in the Time Save RAM.
Changing the bit from a one to zero will freeze and store
the contents of the clock in Time Save RAM. The time then
can be read without concern for clock rollover, since internal logic takes care of synchronization of the clock. Because only the bits used by the clock counters will be
latched, the Time Save RAM should be cleared prior to use
to ensure that random data stored in the unused bits do not
confuse the host microprocessor. This bit can also provide
time save at power failure, see the Additional Supply Management Functions section. With the Time Save Enable bit
at a logical 0, the Time Save RAM may be used as RAM if
the latched read function is not necessary.
Vss and Vee may be applied in any sequence. In order for
the power fail circuitry to function correctly, whenever power
is off, the Vee pin must see a path to ground through a
maximum of 1 Mn. The user should be aware that the control registers will contain random data. The first task to be
carried out in an initialization routine is to start the oscillator
by writing to the crystal select bits in the Real Time Mode
Register. If the DP8571A is configured for single supply
mode, an extra 50 IJ-A may be consumed until the crystal
select bits are programmed. The user should also ensure
that the TCP is not in test mode (see register descriptions).
a
REAL TIME CLOCK FUNCTIONAL DESCRIPTION
As shown in Figure 2, the clock has 10 bytes of counters,
which count from 1/100 of a second to years. Each counter
counts in BCD and is synchronously clocked. The count sequence of the individual byte counters within the clock is
shown later in Table VII. Note that the day of week, day of
month, day of year, and month counters all roll over to 1.
The hours counter in 12 hour mode rolls over to 1 and the
AM/PM bit toggles when the hours rolls over to 12
(AM = 0, PM = 1). The AM/PM bit is bit D7 in the hours
counter.
INITIALIZING AND WRITING TO THE
CALENDAR-CLOCK
Upon initial application of power to the TCP or when making
time corrections, the time must be written into the clock. To
correctly write the time to the counters, the clock would
normally be stopped by writing the Start/Stop bit in the Real
Time Mode Register to a zero. This stops the clock from
counting and disables the carry circuitry. When initializing
the clock's Real Time Mode Register, it is recommended
that first the various mode bits be written while maintaining
the Start/stOP bit reset, and then writing to the register a
second time with the Start/Stop bit set.
All other counters roll over to O. Also note that the day of
year counter is 12 bits long and occupies two addresses.
Upon initial application of power the counters will contain
random information.
The above method is useful when the entire clock is being
corrected. If one location is being updated the clock need
not be stopped since this will reset the prescaler, and time
will be lost. An ideal example of this is correcting the hours
for daylight savings time. To write to the clock "on the fly"
the best method is to wait for the 1/100 of a second periodic interrupt. Then wait an additional 16 IJ-s, and then write
the data to the clock.
READING THE CLOCK: VALIDATED READ
Since clocking of the counter occurs asynchronously to
reading of the counter, it is possible to read the counter
while it is being incremented (rollover). This may result in an
incorrect time reading. Thus to ensure a correct reading of
the entire contents of the clock (or that part of interest), it
must be read without a clock rollover occurring. In general
this can be done by checking a rollover bit. On this chip the
periodic interrupt status bits can serve this function. The
following program steps can be used to accomplish this.
PRESCALER/OSCILLATOR FUNCTIONAL
DESCRIPTION
Feeding the counter chain is a programmable prescaler
which divides the crystal oscillator frequency to 32 kHz and
further to 100 Hz for the counter chain (see Figure 3). The
crystal frequency that can be selected are: 32 kHz, 32.768
kHz, 4.9152 MHz, and 4.194304 MHz.
1. Initialize program for reading clock.
2. Dummy read of periodic status bit to clear it.
3. Read counter bytes and store.
4. Read rollover bit, and test it.
Once 32 kHz is generated it feeds both timers and the
clock. The clock and timer pre scalers can be independently
enabled by controlling the timer or clock Start/stOP bits.
5. If rollover occured go to 3.
6. If no rollover, done.
To detect the rollover, individual periodic status bits can be
polled. The periodic bit chosen should be equal to the highest frequency counter register to be read. That is if only
SECONDS through HOURS counters are read, then the
SECONDS periodiC bit should be used.
From
Oscillator
READING THE CLOCK: INTERRUPT DRIVEN
Enabling the periodic interrupt mask bits cause interrupts
just as the clock rolls over. Enabling the desired update rate
and providing an interrupt service routine that executes in
less than 10 ms enables clock reading without checking for
a rollover.
READING THE CLOCK: LATCHED READ
TL/F/9979-7
Another method to read the clock that does not require
check,ing the rollover bit is to write a one into the Time
FIGURE 3. Programmable Clock Prescaler Block
2-34
C
"'tJ
Functional Description
0)
(Continued)
The oscillator is programmed via the Real Time Mode Register to operate at various frequencies. The crystal oscillator
is designed to offer optimum performance at each frequency. Thus, at 32.768 kHz the oscillator is configured as a low
frequency and low power oscillator. At the higher frequencies the oscillator inverter is reconfigured. In addition to the
inverter, the oscillator feedback bias resistor is included on
chip, as shown in Figure 4. The oscillator input may be driven from an external source if desired. Refer to test mode
application note for details. The oscillator stability is enhanced through the use of an on chip regulated power supply.
U1
The interrupts are enabled by writing a one to the appropriate bits in Interrupt Control Register 0 and/or 1. Any of the
interrupts can be routed to either the INTR pin or the MFO
pin, depending on how the Interrupt Routing register is programmed. This, for example, enables the user to dedicate
the MFO as a non-maskable interrupt pin to the CPU for
power failure detection and enable all other interrupts to
appear on the INTR pin. The polarity for the active interrupt
can be programmed in the Output Mode Register for either
active high or low, and open drain or push pull outputs.
TABLE I. Registers that are Applicable
to Interrupt Control
The typical range of trimmer capacitor (as shown in Oscillator Circuit Diagram Figure 4, and in the typical application) at
the oscillator input pin is suggested only to allow accurate
tuning of the oscillator. This range is based on a typical
printed circuit board layout and may have to be changed
depending on the parasitic capacitance of the printed circuit
board or fixture being used. In all cases, the load capacitance specified by the crystal manufacturer (nominal value
11 pF for the 32.768 crystal) is what determines proper oscillation. This load capcitance is the series combination of
capacitance on each side of the crystal (with respect to
ground).
Register Name
Main Status Register
Periodic Flag Register
Interrupt Routing
Register
Interrupt Control
Register 0
Interrupt Control
Register 1
Output Mode
Register
Internal Components
v+
OSC OUT
Pin
32/32.768 kHz
4.194304 MHz
4.9152 MHz
47 pF 2 pF-22 pF
68 pF o pF-80 pF
68 pF 29 pF-49 pF
0
OOH
03H
0
0
04H
1
0
03H
1
0
04H
1
0
02H
These register bits will be set when their associated timing
events occur. Enabled Alarm or Timer interrupts that occur
will set its Main Status Register bit to a one. However, an
external interrupt will only be generated if. the appropriate
Alarm or Timer interrupt enable bits are set (see Figure 5).
TL/F/9979-B
FIGURE 4. Oscillator Circuit Diagram
Ct
X
Status for the interrupts are provided by the Main Status
Register and the Periodic Flag Register. Bits 01-05 of the
Main Status Register are the main interrupt bits.
External
Components
Co
X
0
Address
Note that the Interrupt Status Flag will only monitor the state
of the MFO output if it has been configured as an interrupt
output (see Output Mode Register description). This is true,
regardless of the state of the Interrupt Routing Register.
Thus the Interrupt Status Flag provides a true reflection of
all conditions routed to the external pins.
XTAL
XTAL
Page
Select
The Interrupt Status Flag DO, in the Main Status Register,
indicates the state of INTR and MFO outputs. It is set when
either output becomes active and is cleared when all TCP
interrupts have been cleared and no further interrupts are
pending (Le., both INTR and MFO are returned to their inactive state). This flag enables the TCP to be rapidly polled by
the ,...p to determine the source of an interrupt in a wiredOR interrupt system.
To
Prescaler
.----10.-----.
Register
Select
ROUT
(Switched
Internally)
Disabling the periodic bits will mask the Main Status Register periodic bit, but not the Periodic Flag Register bits. The
Power Fail Interrupt bit is set when the interrupt is enabled
and a power fail event has occurred, and is not reset until
the power is restored. If all interrupt enable bits are 0 no
interrupt will be asserted. However, status still can be read
from the Main Status Register in a polled fashion (see Figure 5).
150 kn to 350 kn
500n to 900n
500n to 900n
INTERRUPT LOGIC FUNCTIONAL DESCRIPTION
The TCP has the ability to coordinate processor timing activities. To enhance this, an interrupt structure has been implemented which enables several types of events to cause
interrupts. Interrupts are controlled via two Control Registers in block 1 and two Status Registers in block O. (See
Register Description for notes on paging and also Figure 5
and Table I.)
To clear a flag in bits 02-05 of the Main Status Register a 1
must be written back into the bit location that is to be
cleared. For the Periodic Flag Register reading the status
will reset all the periodic flags.
2-35
.......
......
»
---+--....
00:07
Delay
Enable
and
Control
Buffers
5
AO:A4
3
CS,Rfi,WR
TL/F/9979-10
FIGURE 6. System-Battery Swltchover (Upper Left), Power Fall
and Lock-Out Circuits (Lower Right)
After the generation of a lock-out signal, and eventual
switch in of the battery supply, the pins of the TCP will be
configured as shown in Table II. Outputs that have a pull-up
resistor should be connected to a voltage no greater than
The user may choose to have this power failed signal lockout the TCP's data bus within 30 ,...s min/63 ,...s max or to
delay the lock-out to enable ,...p access after power failure is
detected. This delay is enabled by setting the delay enable
bit in the Routing Register. Also, if the lock-out delay was
not enabled the TCP will disconnect itself from the bus within 30 ,...S min -+ 63,...s max. If chip select is low when a
power failure is detected, a safety circuit will ensure that if a
read or write is held active continuously for greater than
30 ,...s after the power fail signal is asserted, the lock-out will
be forced. If a lock-out delay is enabled, the DP8571 A will
remain active for 480 ,...s after power fail is detected. This
will enable the ,...p to perform last minute bookkeeping before total system collapse. When the host CPU is finished
accessing the TCP it may force the bus lock-out before
480 ,...S has elapsed by resetting the delay enable bit.
Vss·
TABLE II. Pin Isolation during a Power Failure
The battery switch over circuitry is completely independent
of the PFAIL pin. A separate circuit compares Vee to the
Vss voltage. As the main supply fails, the TCP will continue
to operate from the Vee pin until Vee falls below the Vss
voltage. At this time, the battery supply is switched in, Vee is
disconnected, and the device is now in the standby mode. If
indeterminate operation of the battery switch over circuit is
to be avoided, then the voltage at the Vee pin must not be
allowed to equal the voltage at the Vss pin.
Pin
PFAIL =
Logic 0
CS,RD,WR
AO-A4
DO-D7
Oscillator
PFAIL
INTR, MFO
Locked Out
Locked Out
Locked Out
Not Isolated
Not Isolated
Not Isolated
Standby Mode
Vee> Vee
Locked Out
Locked Out
Locked Out
Not Isolated
Not Isolated
Open Drain
The Timer and Interrupt Power Fail Operation bits in the
Real-Time Mode Register determine whether or not the timers and interrupts will continue to function after a power fail
event.
As power returns to the system, the battery switch over circuit will switch back to Vee power as soon as it becomes
greater than the battery voltage. The chip will remain in the
locked out state as long as PFAIL = O. When PFAIL = 1 .
2-38
Functional Description
(Continued)
binary down counter and associated control. The operation
is similar to existing J.LP peripheral timers except that several
features have been enhanced. The timers can operate in
four modes, and in addition, the input clock frequency can
be selected from a prescaler over a wide range of frequencies. Furthermore, these timers are capable of generating
interrupts and the Timer 0 output signal is available as a
hardware output via the MFO pin. Timer 1 output, however,
is not available as a hardware output signal. Both the inter. rupt and MFO outputs are fully programmable active high, or
low, open drain, or push-pull.
the chip is unlocked, but only after another 30 J.Ls min --+
63 J.Ls max debounce time. The system designer must ensure that his system is stable when power has returned.
The power fail circuitry contains active linear circuitry that
draws supply current from Vee. In some cases this may be
undesirable, so this circuit can be disabled by masking the
power fail interrupt. The power fail input can perform all
lock-out functions previously mentioned, except that no external interrupt will be issued. Note that the linear power fail
circuitry is switched off automatically when using Vss in
standby mode.
Figure 7 shows the functional block diagram of one of the
timers. The timer consists of a 16-bit counter, two B-bit input
registers, two B-bit output registers, clock prescaler, mode
control logic, and output control logic. The timer and the
data registers are organized as two bytes for each timer.
Under normal operations a read/write to the timer locations
will read or write to the data input register. The timer contents can be read by setting the counter Read bit (RD) in the
timer control register.
LOW BATTERY, INITIAL POWER ON DETECT, AND
POWER FAIL TIME SAVE
There are three other functions provided on the DPB571 A to
ease power supply control. These are an initial Power On
detect circuit, which also can be used as a time keeping
failure detect, a low battery detect circuit, and a time save
on power failure.
On initial power up the Oscillator Fail Flag will be set to a
one and the real time clock start bit reset to a zero. This
indicates that an oscillator fail event has occurred, and time
keeping has failed.
TIMER INITIALIZATION
The timer's operation is controlled by a set of registers, as
listed in Table III. These consist of 2 data input registers and
one control register per timer. The data input registers contain the timers count down value. The Timer Control Register is used to set up the mode of operation and the input
clock rate. The timer related interrupts can be controlled by
programming the Interrupt Routing Register and Interrupt
Control Register o. The timer outputs are configured by the
Output Mode Register.
The Oscillator Fail flag will not be reset until the real-time
clock is started. This allows the system to discriminate between an initial power-up and recovery from a power failure.
If the battery backed mode is selected, then bit 06 of the
Periodic Flag Register must be written low. This will not affect the contents of the Oscillator Fail Flag.
Another status bit is the low battery detect. This bit is set
only when the clock is operating under the Vee pin, and
when the battery voltage is determined to be less than 2.1 V
(typical). When the power fail interrupt enable bit is low, it
disables the power fail circuit and will also shut off the low
battery voltage detection circuit as well.
TABLE III. Timer Associated Registers
To relieve CPU overhead for saving time upon power failure,
the Time Save Enable bit is provided to do this automatically. (See also Reading the Clock: Latched Read.) The Time
Save Enable bit, when set, causes the Time Save RAM to
follow the contents of the clock. This bit can be reset by
software, but if set before a power failure occurs, it will automatically be reset when the clock switches to the battery
supply (not when a power failure is detected by the PFAIL
pin). Thus, writing a one to the Time Save bit enables both a
software write or power fail write.
Register Name
Register
Select
Page
Select
Address
Timer 0 Data MSB
Timer 0 Data LSB
Timer 0 Control Register
Timer 1 Data MSB
Timer 1 Data LSB
Timer 1 Control Register
Interrupt Routing Register
Interrupt Control Reg. 0
Output Mode Register
X
X
0
X
X
0
0
1
1
0
0
0
0
0
0
0
0
0
10H
OFH
01H
12H
11H
02H
04H
03H
02H
All these registers must be initialized prior to starting the
timer(s). The Timer Control Register should first be set to
select the timer mode with the timer start/stop bit reset.
Then when the timer is to be started the control register
should be rewritten identically but with the start/stop bit set.
SINGLE POWER SUPPLY APPLICATIONS
The DPB571 A can be used in a single power supply application. To achieve this, the Vss pin must be connected to
ground, and the power connected to Vee and PFAIL pins.
The Oscillator Failed/Single Supply bit in the Periodic Flag
Register should be set to a logic 1, which will disable the
oscillator battery reference circuit. The power fail interrupt
should also be disabled. This will turn off the linear power
fail detection circuits, and will eliminate any quiescent power
drawn through these circuits. Until the crystal select bits are
initialized, the DPB571A may consume about 50 J.LA due to
arbitrary oscillator selection at power on.
TIMER OPERATION
Each timer is capable of operation in one of four modes. As
mentioned, these modes are programmed in each timer's
Control Register which is described later. All four modes
operate in a similar manner. They operate on the two B-bit
data words stored into the Data Input Register. At the beginning of a counting cycle the 2 bytes are loaded into the timer
and the timer commences counting down towards zero. The
exact action taken when zero is reached depends on the
mode selected, but in general, the timer output will change
state, and an interrupt will be generated if the timer interrupts are unmasked.
(This extra 50 J.LA is not consumed if the battery backed
mode is selected).
TIMER FUNCTIONAL DESCRIPTION
The DPB571 A contains 2 independent multi-mode timers.
Each timer is composed of a 16-bit negative edge triggered
2-39
«
,...
......
co
In
Functional Description
0..
INPUT CLOCK SELECTION
C
The input frequency to the timers may be selected. Each
timer has a prescaler that gives a wide selection of clocking
rates. Table IV shows the range of programmable clocks
available and the corresponding setting in the Timer Control
Register. Note that the output of Timer 1 may be used as
the input to Timer o. This is a cascade option for the timers
and allows them to be clocked as a 32-bit down counter.
(Continued)
er causes the same synchronization error that starting the
timer does. The range of errors is specified in Table V.
TABLE V. Maximum Synchronization Errors
Clock Selected
External
Crystal
Crystal/4
10.7 kHz
1 kHz
100 Hz
10 Hz
1 Hz
TABLE IV. Programmable Timer Input Clocks
C2
C1
CO
Selected Clock
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Timer 1 Output
Crystal Oscillator
(CrystaIOsciliator)/4
93.5 p,s (10.7 kHz)
1 ms (1 kHz)
10 ms (100 Hz)
1/10 Second (10Hz)
1 Second (1 Hz)
Error
+ Ext. Clock Period
+ 1 Crystal Clock Period
+ 1 Crystal Clock Period
+32p,s
+32p,s
+32p,s
+32p,s
+32p,s
MODES OF OPERATION
Bits MO and M1 in the Timer Control Registers are used to
specify the modes of operation. The mode selection is described in Table VI.
TABLE VI. Programmable Timer Modes of Operation
Note that the second and third selections are not fixed frequencies, but depend on the crystal oscillator frequency
chosen.
Since the input clock frequencies are usually running asynchronously to the timer Start/Stop control bit, a 1 clock cycle error may result. This error results when the Start/Stop
occurs just after the clock edge (max error). To minimize
this error on all clocks an independent prescaler is used for
each timer and is designed so that its Start/Stop error is
less than 1 clock cycle.
M1
MO
Function
Modes
0
0
1
1
0
1
0
1
Single Pulse Generator
Rate Generator, Pulse Output
Square Wave Output
Retriggerable One Shot
Mode 0
Mode 1
Mode 2
Mode 3
MODE 0: SINGLE PULSE GENERATOR
When the timer is in this mode the output will be initially low
if the Timer Start/Stop bit is low (stopped). When this mode
is initiated the timer output will go high on the next falling
edge. of the prescaler's input clock, the contents of the
The count hold/gate bit in the Timer Control Register can
be used to suspend the timer operation in modes 0, 1, and 2
(in mode 3 it is the trigger input). Suspending the tim-
32KHz
Crystal Clock
To MrO
or INTR
Start/Stop
Count Hold/Gat. bit
Selected Clock
Clock
} Select
Count Hold/Gate bit
TImer Start/Stop
Mode 0
Model
RD bit
TLIF/9979-11
FIGURE 7. DP8571A Timer Block Diagram
2-40
C
Functional Description
""'D
co
(Continued)
U1
input data registers are loaded into the timer. The output will
stay high until the counter reaches zero. At zero the output
is reset. The result is an output pulse whose duration is
equal to the input clock period times the count value (N)
loaded into the input data register. This is shown in Figure B.
Pulse Width = Clock Period x N
for one clock period of the timer clock. Then on the next
clock the counter is reloaded automatically and the countdown repeats itself. The output, shown in Figure 9, is a
waveform whose pulse width and period is determined by N,
the input register value, and the input clock period:
An interrupt is generated when the zero count is reached.
This can be used for one-time interrupts that are set to occur a certain amount of time in the future. In this mode the
Timer Start/Stop bit (TSS) is automatically reset upon zero
detection. This removes the need to reset TSS before starting another operation.
Pulse Width = Clock Period
Period = (N
+
1) (Clock Period)
Again, the output polarity is controllable as in mode O. If
enabled, an interrupt is generated whenever the zero count
is reached. This can be used to generate a periodic interrupt.
MODE 2: SQUARE WAVE GENERATOR
The count down operation may be temporarily suspended
either under software control by setting the Count Hold/
Gate bit in the timer register high, or in hardware by setting
the GO or G1 pin high.
This mode is also cyclic but in· this case a square wave
rather than a pulse is generated. The output square wave
period is determined by the value loaded into the timer input
register. This period and the duty cycle are:
The above discussion assumes that the MFO output is programmed to be non-inverting outputs (active high). If the
polarity of the output waveform is wrong for the application
the polarity can be reversed by configuring the Output Mode
Register. The drive configuration can also be programmed
to be push pull or open drain.
Period
=
2(N
+
1) (Clock Period)
Duty Cycle
=
0.5
When the timer is stopped the output will be low, and when
the Start/Step bit is set high the timer's counter will be loaded on the next clock falling transition and the output will be
set high.
The output will be toggled after the zero count is detected
and the counter will then be reloaded, and the cycle will
continue. Thus, every N + 1 counts the output gets toggled,
as shown in Figure 10. Like the other modes the timer operation can be suspended by setting the count hold/gate bit
(CHG) in the Timer Control Register. An interrupt will be
generated every falling edge of the timer output, if enabled.
MODE 1: RATE GENERATOR
When operating in this mode the timer will operate continuously. Before the timer is started its output is low. When the
timer is started the input data register contents are loaded
into the counter on the negative clock edge and the output
is set high (again assuming the Output Mode Register is
programmed active high). The timer will then count down to
zero. Once the zero count is reached the output goes low
I 1 I0 I
Internal
Counter
Clock
TImer
Start/Stop
Count Hold/
Gate Bit
TImer
Output
TL/F/9979-12
FIGURE 8. Typical Waveforms for Timer Mode 0
(MFO Output Programmed Active High)
Internal
Counter
Clock
TImer
Start/Stop
Count Hold/
Gate Bit
TImer
Output
TLIF/9979-13
FIGURE 9. Timing Waveforms for Timer Mode 1
(MFO Output Programmed Active High)
2-41
-...J
~
l>
«
'9"'"
.....
Ln
Functional Description
co
c..
C
(Continued)
1312111013121
Those users who find the error rate unacceptable may reduce the problem effectively to zero by employing a hardware work-around that synchronizes the writing of the read
bit to the timer control register with respect to the decrementing clock. Refer to Figure 1 in Appendix A, for a suggested hardware work-around.
101
Internal
Counter
Clock
Timer
Start/Stop
Count Hold/
Gate Bit
A software work-around can reduce the errors but not as
substantial as a hardware work-around. Software workarounds are based on observations that the read following a
bad read appeared to be valid.
Timer
Output
TL/F 19979-14
This problem concerns statistical probability and is similar to
metastability issues. For more information on metastability,
refer to 1991 IEEE transactions on Custom Integrated Circuits Conference, paper by T.J. Gabara of AT&T Bell Laboratories, page 29.4.1.
FIGURE 10. Timing Waveforms for Timer Mode 2
(MFO Output Programmed Active High)
MODE 3: RETRIGGERABLE ONE SHOT
Once the timer Start/Stop bit is set the output stays inactive, and nothing happens until the Count Hold/Gate (CHG)
bit is set in the timer control register. When a transition
ocurs the one shot output is set active immediately; the
counter is loaded with the value in the input register on the
next transition of the input clock and the countdown begins.
If a retrigger occurs, regardless of the current counter value,
the counters will be reloaded with the value in the input
register and the counter will be restarted without changing
the output state. See Figure 11. A trigger count can occur at
any time during the count cycle. In this mode the timer will
output a single pulse whose width is determined by the value in the input data register (N) and the input clock period.
Normally reading the timer data register addresses, OFH
and 1OH for Timer 0 and 11 Hand 12H for Timer 1 will result
in reading the input data register which contains the preset
value for the timers.
To read the contents of a timer, the ,...p first sets the timer
read bit in the appropriate Timer Control Register high. This
will cause the counter's contents to be latched to 2-bit-8-bit
output registers, and will enable these registers to be read if
the ,...p reads the timer's input data register addresses. On
reading the LSB byte the timer read bit is internally reset
and subsequent reads of the timer locations will return the
input register values.
Pulse Width = Clock Period x N
DETAILED REGISTER DESCRIPTION
The timer will generate an interrupt only when it reaches a
count of zero. This timer mode is useful for continuous
"watch dog" timing, line frequency power failure detection,
etc.
There are 5 external address bits: Thus, the host microprocessor has access to 32 locations at one time. An internal
switching scheme provides a total of 67 locations.
This complete address space is organized into two pages.
Page 0 contains two blocks of control registers, timers, real
time clock counters, and special purpose RAM, while page
1 contains general purpose RAM. Using two blocks enables
the 9 control registers to be mapped into 5 locations. The
only register that does not get switched is the Main Status
Register. It contains the page select bit and the register
select bit as well as status information.
READING THE TIMERS
National has discovered that some users may encounter
unacceptable error rates for their applications when reading
the timers on the fly asynchronously. When doing asynchronous reads of the timers, an error may occur. The error is
that a successive read may be larger than the previous
read. Experimental results indicate that the typical error rate
is approximately one per 29,000 under the following conditions:
Timer clock frequency of 5 MHz.
Computer: 386/33 MHz PC/AT
Program:
Microsoft "C" 6.0, reading and saving timer contents in a continuous loop.
Internal
Counter
Clock
Timer
Start/Stop
Count Hold/
~
Gate Bit
Timer
_ _ _ _...
-----""~
n~
Output
L..-.J
.....----1--- II
_
___
1
L-
10._ _ _ _
TL/F/9979-15
FIGURE 11. Timing Waveforms for Timer Mode 3, MFO Output Programmed Active High
2-42
C
Functional Description
""D
CX)
(Continued)
U1
A memory map is shown in Figure 2 and register addressing
in Table VII. They show the name, address and page locations for the OP8571A.
IPSIRS
TABLE VII. Register/Counter/RAM
Addressing for OP8571A
AO·4
PS
RS
(Note 1) (Note 2)
X
0
0
0
0
0
0
0
0
X
0
0
0
0
1
1
1
1
OA
OB
OC
00
OE
0
0
0
0
0
0
0
0
0
0
X
X
X
X
X
X
X
X
X
X
0
0
0
0
X
X
X
X
1/100,1/10 Seconds
Seconds
Minutes
Hours
Days of
Month
Months
Years
Julian Date (lSB)
Julian Date
Day of Week
01 Power ,1111 Interrupt
02 Period Interrupt
TL/F/9979-16
01-05: These five bits of the Main Status Register are the
main interrupt status bits. Any bit may be a one when any of
the interrupts are pending. Once an interrupt is asserted the
,...p will read this register to determine· the cause. These
interrupt status bits are not reset when read. Except for 01,
to reset an interrupt a one is written back to the corresponding bit that is being tested. 01 is reset whenever the PFAIL
pin = logic 1. This prevents loss of interrupt status when
reading the register in a polled mode. 01, 03-05 are set
regardless of whether these interrupts are masked or not by
bits 06 and 07 of Interrupt Control Registers a and 1.
Timer 0 lSB
Timer 0 MSB
Timer 1 lSB
Timer 1 MS8
0
X
X
X
16
0
X
17
0
X
18
0
X
Sec Compare RAM
Min Compare RAM
Hours Compare
RAM
DOMCompare
RAM
Months Compare
RAM
DOW Compare RAM
06 and 07: These bits are Read/Write bits that control
which register block or RAM page is to be selected. Bit 06
controls the register block to be accessed (see memory
map). The memory map of the clock is further divided into .
two memory pages. One page is the registers, clock and
timers, and the second page contains 31 bytes of general
purpose RAM. The page selection is determined by bit 07.
X
X
X
X
X
Seconds Time Save RAM
Minutes Time Save RAM
Hours Time Save RAM
Day of Month Time Save RAM
Months Time Save RAM
(0-59)
(0-59)
(1-12,0-23)
(1-28/29/30/31 )
(1-12)
(1-7)
TIME SAVE RAM
19
1A
18
1C
10
0
0
1E
1F
0
1
X
RAM
RAM/Test Mode Register
01-1F
1
X
2nd Page General Purpose RAM
0
IL:
DO Interrupt Stlltus
The Main Status Register is always located at address a
regardless of the register block or the page selected.
00: This read only bit is a general interrupt status bit that is
taken directly from the interrupt pins. The bit is a one when
an interrupt is pending on either the INTR pin or the MFO
pin (when configured as an interrupt). This is unlike 03-05
which can be set by an internal event but may not cause an
interrupt. This bit is reset when the interrupt status bits in the
Main Status Register are cleared.
(1-28/29/30/31)
(1-12)
(0-99)
(0-99) (Note 3)
(0-3)
(1-7)
0
0
»
INTI
07 Page Select Bit
(0-99)
(0-59)
(0-59)
(1-12,0-23)
13
14
15
0
0
p,
06 Register Select Bit
Main Status Register
Timer 0 Control Register
Timer 1 Control Register
Periodic Flag Register
Interrupt Routing Register
Real Time Mode Register
Output Mode Register
Interrupt Control Register 0
Interrupt Control Register 1
TIME COMPARE RAM
0
AL PER
04 TImer 0 Interrupt
TIMER DATA REGISTERS
OF
10
11
12
TO
05 TImer 1 Interrupt
COUNTERS (CLOCK CALENDAR)
05
06
07
08
09
T1
03 Alarm Interrupt
Description
CONTROL REGISTERS
00
01
02
03
04
01
02
03
04
-.....
......
MAIN STATUS REGISTER
Note 1: PS-Page Select (Bit 07 of Main Status Register)
Note 2: RS-Register Select (Bit 06 of Main Status Register)
Note 3: The lSB counters count 0-99 until the hundreds of days counter
reaches 3. Then the lSB counters count to 65 or 66 (if a leap year). The
rollover is from 365/366 to 1.
2-43
Functional Description
(Continued)
TIMER 0 ANO 1 CONTROL REGISTER
00-05: These bits are set by the real time rollover events:
(Time Change = 1). The bits are reset when the register is
read and can be used as selective data change flags.
I CHGI RO I C21 Cl I CO 11.411 MOITSSI
L
06: This bit performs a dual function. When this bit is read, a
one indicates that an oscillator failure has occurred and the
time information may have been lost. Some of the ways an
oscillator failure may be caused are: failure of the crystal,
shorting OSC IN or OSC OUT to GNO or Vee, removal of
crystal, removal of battery when in the battery backed mode
(when a "0" is written to 06), lowering the voltage at the
VBB pin to a value less than 2.2V when in the battery
backed mode. Bit 06 is automaticaily set to 1 on initial power-up or an oscillator fail event. The oscillator fail flag is
reset by writing a one to the clock start/stop bit in the Real
Time Mode Register, with the crystal oscillating.
00 Timer Start/Stop
01 Mode Select
02 Mode· Select
03 Input Clock Select
04 Input Clock Select
05 Input Clock Select
06 Timer Read
07 Count Hold/Gate
TL/F/9979-17
When 06 is written to, it defines whether the TCP is being
used in battery backed (normal) or in a single supply mode
application. When set to a one this bit configures the TCP
for single power supply applications. This bit is automatically
set on initial power-up or an oscillator fail event. When set,
06 disables the oscillator reference circuit. The result is that
the oscillator is referenced to Vee. When a zero is written to
06 the oscillator reference is enabled, thus the oscillator is
referenced to VBB. This allows operation in standard battery
standby applications.
These registers control the operation of the timers. Each
timer has its own register.
00: This bit will Start (1) or Stop (0) the timer. When the
timer is stopped the timer's prescaler and counter are reset,
and the timer will restart from the beginning when started
again. In mode 0 on time out the TSS bit is internally reset.
01 and 02: These control the count mode of the timers.
See Table VI.
03-05: These bits control which clock signal is applied to
the timer's counter input. Refer to Table IV for details.
At initial power on, if the DP8571 A is going to be programmed for battery backed mode, the VBB pin should be
connected to a potential in the range of 2.2V to Vee-OAV.
06: This is the read bit. If a one is written into this location it
will cause the contents of the timer to be latched into a
holding register, which can be read by the JLP at any time.
Reading the least significant byte of the timer will reset the
RO bit. The timer read cycle can be aborted by writing RO to
zero.
For single supply mode operation, the VBB pin should be
connected to GNO and the PFAIL pin connected to Vee.
07: Writing a one to this bit enables the test mode register
at location 1F (see Table VII). This bit should be forced to
zero during initialization for normal operation. If the test
mode has been entered, clear the test mode register before
leaving test mode. (See separate test mode application
note for further details.)
07: The CHG bit has two mode dependent functions. In
modes 0 through 2 writing a one to this bit will suspend the
timer operation (without resetting the timer prescaler). However, in mode 3 this bit is used to trigger or re-trigger the
count sequence as with the gate pins. If retriggering is desired using the CHG bit, it is not necessary to write a zero to
this location prior to the re-trigger. The action of further writing a one to this bit will re-trigger the count.
INTERRUPT ROUTING REGISTER
I TS I LB I PFDITIR ITORIALRlpRRlpFRI
L
PERIOOIC FLAG REGISTER
TM I osr
1m. 10ms 100m. 10
lOs 1 min
I L=
00 Power fail route
01 Periodic route
02 Alarm route
00 minutes flag
01 10 second flag
03 Timer 0 route
02 seconds flag
04 Timer 1 route
03 100 millisec. flag
05 PF Oelay Enable
04 10 millisec. flag
05 mi1li-seconds flag
06 Low Battery flag
06 Oscillator railed/Single Supply
07 Time Save Enable
TL/F/9979-19
07 Test Mode [nable
TLIF/9979-18
00-04: The lower 5 bits of this register are associated with
The Periodic Flag Register has the same bit for bit correspondence as Interrupt Control Register 0 except for 06
and 07. For normal operation (Le., not a single supply application) this register must be written to on initial power up or
after an oscillator fail event. DO-OS are read only bits, 06
and 07 are read/write.
the main interrupt sources created by this chip. The purpose
of this register is to route the interrupts to either the MFO
(multi-function pin), or to the main interrupt pin. When any
bit is set the associated interrupt signal will be sent to the
MFO pin, and when zero it will be sent to the INTR pin.
2-44
Functional Description
(Continued)
02: The count mode for the hours counter can be set to
either 24 hour mode or 12 hour mode with AM/PM indicator.
A one will place the clock in 12 hour mode.
05: The Delay Enable bit is used when a power fail occurs.
If this bit is set, a 480 fLs delay is generated internally before
the fLP interface is locked out. This will enable the fLP to
access the registers for up to 480 fLs after it receives a
power fail interrupt. After a power failure is detected but
prior to the 480 fLs delay timing out, the host fLP may force
immediate lock out by resetting the Delay Enable bit. Note if
this bit is a a when power fails then after a delay of 30 fLs
min/63 fLs max the fLP cannot read the chip.
03: This bit is the master Start/Stop bit for the clock. When
a one is written to this bit the real time counter's prescaler
and counter chain are enabled. When this bit is reset to zero
the contents of the real time counter is stopped and the
prescaler is cleared. When the TCP is initially powered up
this bit will be held at a logic a until the oscillator starts
functioning correctly after which this bit may be modified. If
an oscillator fail event occurs, this bit will be reset to logic O.
06: This read only bit is set and reset by the voltage at the
Vss pin. It can be used by the fLP to determine whether the
battery voltage at the Vss pin is getting too low. A comparator monitors the battery and when the voltage is lower than
2.1 V (typical) this bit is set. The power fail interrupt must be
enabled to check for a low battery voltage.
04: This bit controls the operation of the interrupt output in
standby mode. If set to a one it allows Alarm, Periodic, and
Power Fail interrupts to be functional in standby mode. Timer interrupts will also be functional provided that bit D5 is
also set. Note that the MFa and INTR pins are configured
as open drain in standby mode.
07: Time Save Enable bit controls the loading of real-timeclock data into the Time Save RAM. When a one is written
to this bit the Time Save RAM will follow the corresponding
clock registers, and when a zero is written to this bit the time
in the Time Save RAM is frozen. This eliminates any synchronization problems when reading the clock, thus negating the need to check for a counter rollover during a read
cycle.
If bit 04 is set to a zero then interrupt control register a and
bits 06 and 07 of interrupt control register 1 will be reset
when the TCP enters the standby mode (Vss > Vee). They
will have to be re-configured when system (Vee) power is
restored.
05: This bit controls the operation of the timers in standby
mode. If set to a one the timers will continue to function
when the TCP is in standby mode. The input pins TCK, GO,
G1 are locked out in standby mode, and cannot be used.
This bit must be set to a one prior to power failing to enable
the Time Save feature. When the power fails this bit is automatically reset and the time is saved in the Time Save RAM.
Therefore external control of the timers is not possible in
standby mode. Note also that MFa and T1 pins are automatically reconfigured open drain during standby.
REAL TIME MODE REGISTER
I xnl xToITpFlIPFlcssI12HI
LY11 LYOI
IL:
06 and 07: These two bits select the crystal clock frequency as per the following table:
00 Leap Year LSB
01 Leap Year t.lSB
02 12/24 hour mode
XT1
XTO
Crystal
Frequency
a
0
1
0
1
32.768 kHz
4.194304 MHz
4.9152 MHz
32.000 kHz
03 Clock Start/Stop
04 Interrupt Pf Operation
0
1
1
05 TImer Pf Operation
06 Crystal frequency LSB
07 Crystal frequency t.lSB
All bits are Read/Write, and any 'mode written into this register can be determined by reading the register. On initial
power up these bits are random.
TLlF/9979-20
00-01: These are the leap year counter bits. These bits are
written to set the number of years from the previous leap
year. The leap year counter increments on December 31 st
and it internally enables the February 29th counter state.
This method of setting the leap year allows leap year to
occur whenever the user wishes to, thus providing flexibility
in implementing Japanese leap year function.
LY1
LYO
a
a
a
1
1
1
a
1
OUTPUT MODE REGISTER
r t.40-1 t.4fT t.4PI t.4HI IPI
Leap Year
Counter
Leap
Leap
Leap
Leap
IHI TP-r
THl
IL=
00 RAIA
01 RAIA
02 INTR Active Hi/Low
03 INTR Push pull/Open Drain
04 IAro Active Hi/LOW
Year Current Year
Year Last Year
Year 2 Years Ago
Year 3 Years Ago
05 IAro Push pull/Open Drain
06 IAro pin as TImer 0
07 IAro Pin as Oscillator
TLlF/9979-21
2-45
Vecl then
this bit is controlled by 04 of the Real Time Mode Register.
05 millisec enable
06 Timer 0 enable
07 Timer 1 enable
TL/F/9979-22
07: The MSB of this register is the enable bit for the Power
Fail Interrupt. When this bit is set to a one an interrupt will
be generated to the p.P when PFAIL = O. If battery backed
mode is selected and the OP8571A is in standby
(Vee > Vecl then this bit is controlled by 04 of the Real
Time Mode Register.
If battery backed mode is selected and the OP8571 A is in
standby (Vee > Vecl then all bits are controlled by 04 of
the Real Time Mode Register.
00-05: These bits are used to enable one of the selected
periodic interrupts by writing a one into the appropriate bit.
These interrupts are issued at the rollover of the clock. For
example, the minutes interrupt will be issued whenever the
minutes counter increments. In all likelihood the interrupt
will be enabled asynchronously with the real time change.
Therefore, the very first interrupt will occur in less than the
periodic time chosen, but after the first interrupt all subse-
This bit also enables the low battery detection analog circuitry.
If the user wishes to mask the power fail interrupt, but utilize
the analog circuitry, this bit should be enabled, and. the
Routing Register can be used to route the interrupt to the
MFa pin. The MFa pin can then be left open or configured
as the Timer 0 or buffered oscillator output.
2-46
C
."
co
Control and Status Register Address Bit Map
07
06
Main Status Register PS = 0
R/W
R/W
05
RS = 0
R/W1
04
03
CJ1
02
ADDRESS = OOH
R/W1
R/W1
01
........
.....
00
1. Reset by
writing
1 to bit.
R/W1
2. Set/reset by
voltage at
PFAIL pin.
3. Reset when
all pending
interrupts
are removed.
All Bits R/W
All Bits R/W
4. Read Osc fail
Write 0 BattBacked Mode
Write 1 Single
Supply Mode
5. Reset by
positive edge
of read.
Interrupt Routing Register PS = 0
R/W
R6
R/W
Time Save
Enable
Low Battery
Flag
Power Fail
Delay
Enable
RS = 0
Address = 04H
R/W
R/W
R/W
R/W
R/W
Timer 1
Int. Route
MFO/INT
Timer 0
Int. Route
MFO/INT
Alarm
Int. Route
MFO/INT
Periodic
Int. Route
MFO/INT
Power Fail
Int. Route
MFO/INT
RS = 1
6. Set and reset
byVSS
voltage.
Address = 01 H
All BitsR/W
All Bits R/W
Interrupt Control Register 0 PS = 0
Timer 1
Interrupt
Enable
Timer 0
Interrupt
Enable
1 ms
Interrupt
Enable
Interrupt Control Register 1 PS = 0
Power Fail
Interrupt
Enable
Alarm
Interrupt
Enable
DOW
Interrupt
Enable
RS = 1
10 ms
Interrupt
Enable
RS = 1
Month
Interrupt
Enable
Address = 03H
100 ms
Interrupt
Enable
Seconds
Interrupt
Enable
10 Second
Interrupt
Enable
Minute
Interrupt
Enable
All BitsR/W
Minute
Interrupt
Enable
Second
Interrupt
Enable
All Bits R/W
Address = 04H
DaM
Interrupt
Enable
2-47
Hours
Interrupt
Enable
»
«
,...
.......
Lt)
co
D..
C
Application Hints
Suggested initialization procedure for OP8571A in battery
backed applications that use the Vee pin.
ration, interrupt control and timer functions may be initialized.
6.
1. Enter the test mode by writing a 1 to bit 07 in the Periodic Flag Register.
Test bit 06 in the Periodic Flag Register:
IF a 1, go to 5.1 If this bit remains a 1 after 3 seconds,
then abort and check hardware .. The crystal may be
defective or not installed. There may be a short at OSC
IN or OSC OUT to Vee or GNO, or to some impedance
that is less than 10 MO.
2. Write zero to the RAM/TEST mode Register located in
page 0, address HEX 1F.
3. Leave the test mode by writing a 0 to bit 07 in the Periodic Flag Register. Steps 1, 2, 3 guarantee that if the
test mode had been entered during power on (due to
random pulses from the system), all test mode conditions are cleared. Most important is that the OSC Fail
Disable bit is cleared. Refer to AN-589 for more information on test mode operation.
IF a 0, then the oscillator is running, go to step 7.
7.
Write a 0 to bit 06 in the Periodic Flag Register. This
action puts the clock chip in the battery backed mode.
This mode can be entered only if the OSC fail flag (bit
06 of the Periodic Flag Register) is a o. Reminder, bit
06 is a dual function bit. When read, 06 returns oscillator status. When· written, 06 causes either the Battery
Backed Mode, or the Single Supply Mode of operation.
. The only method to ensure the chip is in the battery
backed mode is to measure the waveform at the OSC
OUT pin. If the battery backed mode was selected successfully, then the peak to peak waveform at OSC OUT
is referenced to the battery voltage. If not in battery
backed mode, the waveform is referenced to Vee. The
measurement should be made with a high impedance
low capacitance probe (10 MO, 10 pF oscilloscope
probe or better). Typical peak to peak swings are within
O.6V of Vee and ground respectively.
Set a 3 second(approx) software counter. The crystal
oscillator may take 1 second to start.
8.
Write a 1 to bit 07 of Interrupt Control Register 1. This
action enables the PFAIL pin and associated circuitry.
5.1 Write a 1 to bit 03 in the Real Time Mode Register (try
to start the clock). Make sure the crystal select bits remain the same as in step 1. Under normal operation, this
bit can be set only if the oscillator is running. During the
software loop, RAM, real time counters, output configu-
9.
4. After power on (Vee and Vee powered), select the correct crystal frequency bits (07, 06 in the Real Time
Mode Register) as shown in Table 1.
Table 1
Frequency
07
06
32.768 KHz
0
0
4.194304 MHz
0
1
4.9152 MHz
1
0
32.0 KHz
1
1
5. Enter a software loop that does the following:
Write a 1 to bit 04 of the Real Time Mode Register. This
action ensures that bit 07 of Interrupt Control Register
1 remains a 1 when Vee> Vee (standby mode).
10. Initialize the rest of the chip as needed.
Typical Application
A low going user
generated power
fall signal should
be presented to the
PrAlL pin.
DP8571A
L..
oVl
Timer
Vl
(1)
OSC IN 1 - - , - - - ,
Clock
u
ea.
2-22
Peripheral
pr
32.768KHz
o
L..
U
OSC OUT
~
T
47 Pr
t.4FO
GND
TL/F/9979-24
"These components may be necessary to meet UL requirements for lithium batteries. Consult battery manufacturer.
2-48
Appendix A
r-------------------------------~
+5
1.5k
.
--1h
~
Z
...J
-<
z
(!)
en
3k
~
Z
0:
AID
_
All
A26
A25
A24
A23
'A22
I/o CH RDY
6
+5V )
r---rt"
r---tr
~
~
r--tr
~
AD
A4
AS
A3
A6
A7
Vee
B7
B6
~
.19...
~
~
...!..L
3-
...4-
I~
~
1.-4.
I~
~1
'"
AI
A2
BO
Bl
B2
B3
B4
A=B
'V
7500
19
~,
....I
B13
00
Dl
D2
03
04
D5
D6
D7
ClK B20
OSC B30
+5V B3
+5V B29
GND Bl
GND B31
DIR
Vee
11.1 MHz
33 1.4 Hz
G
·74lS245
!
GND
o
20
GND
~O
11
12
13
14
15
16
17
18
WORK AROUND
INSIDE POLYGONS
IS 1/4 Of A 74LS02
NOTE: AlS OR LS MAY BE US ED
I
Ih
. 28/24
HEX 300 TO 31f
11_
-±l0 .A
fi210
__ 10 _
I
,-
-..13
1
3
_. ~- --":":" - - --- -- - - - - --
2
4
5
6
7
8
19
1
+5V
B
~
ADDRO
ADDRI
ADOR2
ADDR3
ADDR4
9
8
7
6
5
4
3
2
A
5
8
. A9
A8
A7
A6
AS
A4
A3
A2
I
I
2rll
74lS164
ClK
12
I
. +5
ITo EN'
II-'-"- GND
lOR B14
AD A31
AI A30
A2 A29
A3 A28
A4 'A27
9
8
I
I
+5
RESET
74AlS522
lOW
PROTECTS BASE-EMITTER
fROM BREAKDOWN
5
._. --------AEN '. 2.
AEN
AS
A6
A7
A8
A9
01 = lN914
~TD1
'=~
.n.
....::E
-<
T1 = 2N2222
SPEED UP CAP.
75 pF. SilVER MICA
DATAO
DATAl
DATA2
DATA3
DATU
DATA5
DATA6
DATA7
M
EXTERNAL
OSCILLATOR
J
18
19
20
21
22
23
24
25
14/12
~
cs Vee
27/23
PF.AIL
WR
RD
AD
AI
A2
A3
A4 DP8570/71
DO
Dl
D2
D3
D4
D5
D6
D7
VBB
GND
OSC
IN
r1
OSC
OUT
112/10
113 /
11
TL/F/9979-29
FIGURE A1. Typical Interface Where the "Write Strobe" Is Synchronized to the Decrementing Clock of the Timer
2-49
....
c(
rn
co
a..
Typical Performance Characteristics
C
Operating Current vs
Supply Voltage
(Single Supply Mode
Fosc = 32.768 kHz)
Operating Current VB
Supply Voltage
(Battery Backed Mode
Fosc = 32.768 kHz)
1400
I
160
~
-
V
140
~
/
120
20
3.0
4.0
J
~
~
/
1000
/
800
/
600
6.0
5.0
/
1200
Vee (Volts)
TLlF/9979-25
20
3.0
4.Q
s.o
6.Q
Vcc(Volts)
TLlF/9979-26
Standby Current vs Power
Supply Voltage
(Fosc = 32.768 kHz)
/~
12
8
4
--'
20
Standby Current VB Power
Supply Voltage
.
Fosc = 4.194304 MHz
2.5
/
/
/
160
V
~
m
120
.J!l
/
V
.....
"
V
./
80
3.0
3.5
4.0
4.5
25
VBB (Volts)
3.0
3.5
4.0
4.5
VBB(Volts)
TLlF/9979-27
TLlF/9979-28
2-50
~National
U
Semiconductor
DP8572A/DP8572AM Real Time Clock (RTC)
General Description
The DP8572A (8572AM-militarized version) is intended for
use in microprocessor based systems where information is
required for multi-tasking, data logging or general time of
day/date information. This device is implemented in low
voltage silicon gate microCMOS technology to provide low
standby power in battery back-up environments. The circuit's architecture is such that it looks like a contiguous
block of memory or I/O ports. The address space is organized as 2 software selectable pages of 32 bytes. This includes the Control Registers, the Clock Counters, the Alarm
Compare RAM, and the Time Save RAM. Any of the RAM
locations that are not being used for their intended purpose
may be used as general purpose CMOS RAM.
Time and date are maintained from 1/100 of a second to
year and leap year in a BCD format, 12 or 24 hour modes.
Day of week, day of month and day of year counters are
provided. Time is controlled by an on-chip crystal oscillator
requiring only the addition of the crystal and two capacitors.
The choice of crystal frequency is program selectable.
Power failure logic and control functions have been integrated on chip. This logic is used by the RTC to issue a power
fail interrupt, and lock out the JlP interface. The time power
fails may be logged into RAM automatically when Vss >
Vee. Additionally, two supply pins are provided. When
Vss > Vee, internal circuitry will automatically switch from
the main supply to the battery supply. Status bits are provided to indicate initial application of battery power, system
(Continued)
power, and low battery detect.
Features
II
a
•
•
II
•
Full function real time clock/calendar
- 12/24 hour mode timekeeping
- Day of week and day of years counters
- Four selectable oscillator frequencies
- Parallel resonant oscillator
Power fail features
- Internal power supply switch to external battery
- Power Supply Bus glitch protection
- Automatic log of time into RAM at power failure
On-chip interrupt structure
- Periodic, alarm, and power fail interrupts
Up to 44 bytes of CMOS RAM
MIL-STD-883C compliant
SMD #5962-91641-01MJX (future)
Block Diagram
OSC
out
OSC
in
V+
Vee
Real TIme
Clock Counters
INTR
MFO
TLIF/9980-1
FIGURE 1
2-51
:E
VIH, Cl
=
100 pF (unless otherwise specified)
Parameter
Conditions
Min
VIH
High Level Input Voltage
(Note 4)
Any Inputs Except OSC IN,
OSC IN with External Clock
2.0
Vss -0.1
Vil
Low Level Input Voltage
All Inputs Except OSC IN
OSC IN with External Clock
VOH
High Level Output Voltage
(Excluding OSC OUT)
VOL
Low Level Output Voltage
(Excluding OSC OUT)
= -20/-tA
= -4.0 mA
lOUT = 20/-tA
lOUT = 4.0 mA
VIN = Vee or GND
VOUT = Vee or GND
VOUT = Vee or GND
liN
Input Current (Except OSC IN)
102
Output TRI-STATE® Current
IlKG
Output High Leakage Current
MFO, INTR Pins
lee
Quiescent Supply Current
(Note 7)
lOUT
lOUT
lee
Quiescent Supply Current
(Single Supply Mode)
(Note 7)
0.1
0.25
V
V
±1.0
/-t A
±5.0
/-t A
±5.0
/-t A
250
1.0
12.0
/-tA
rnA
mA
8
20
mA
mA
40
7.5
/-t A
rnA
10
400
/-t A
/-t A
1.5
/-t A
/-t A
=
4.194304 MHz or
4.9152 MHz·
Vee or GND (Note 6)
VIH or Vil (Note 6)
=
=
Vss = GND
VIN = Vee or GND
Fose = 32.768 kHz
Fose = 4.9152 MHz or
VIN
VIN
V
V
V
V
Vee -0.1
3.5
Fose = 32.768 kHz
VIN = VeeorGND (Note 5)
VIN = Vee or GND (Note 6)
VIN = VIH or Vil (Note 6)
Units
V
V
0.8
0.1
Outputs Open Drain
Fose
Max
4.194304 MHz
Iss
ISlK
Standby Mode Battery
Supply Current
(Note 7)
Battery Leakage
Vee = GND
OSC OUT = open circuit,
other pins = GND
Fose = 32.768 kHz
Fose = 4.9152 MHz or
4.194304 MHz
2.2V :S:: Vss :S:: 4.0V
other pins at GND
Vee = GND, Vss = 4.0V
Vee = 5.5V, Vss = 2.2V
-5
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: For Fose = 4.194304 or 4.9152 MHz, VBB minimum = 2.8V. In battery backed mode, Vaa ,;; Vee -O.4V.
Single Supply Mode: Data retention voltage is 2.2V min.
In single Supply Mode (Power connected to Vce pin) 4.5V ,;; Vee';; 5.5V.
Note 4: This parameter (VIH) is not tested on all pins at the same time.
Note 5: This specification tests IcC with all power fail Circuitry disabled, by setting 07 of Interrupt Control Register 1 to O.
Note 6: This specification tests Icc with all power fail Circuitry enabled, by setting 07 of Interrupt Control Register 1 to 1.
Note 7: OSC IN is driven by a signal generator. Contents of the Test Register = OO(H) and the MFO pin is not configured as buffered oscillator out.
2-52
C
""C
8572A
CO
AC Electrical Characteristics
Vcc = sv ± 10%, VBB = 3V, VPFAIL > VIH, CL =
.......
Symbol
U1
'""-I
I
I\)
»
c
100 pF (unless otherwise specified)
I
Parameter
Min
I
I
Max
Units
READ TIMING
20
tRW
Read Strobe Width (Note 8)
80
tCD
Chip Select to Data Valid Time
tRAH
Address Hold after Read (Note 9)
tRD
Read Strobe to Valid Data
tDZ
Read or Chip Select to TRI-STATE
tRCH
Chip Select Hold after Read Strobe
tDS
ns
ns
80
ns
70
ns
60
ns
3
ns
0
ns
Minimum Inactive Time between Read or Write Accesses
SO
ns
tAW
Address Valid before Write Strobe
20
ns
tWAH
Address Hold after Write Strobe (Note 9)
3
ns
tcw
Chip Select to End of Write Strobe
90
ns
tww
Write Strobe Width (Note 10)
80
ns
tow
Data Valid to End of Write Strobe
SO
ns
tWDH
Data Hold after Write Strobe (Note 9)
3
ns
tWCH
Chip Select Hold after Write Strobe
0
ns
WRITE TIMING
INTERRUPT TIMING
I
Clock Rollover to INTR Out is Typically 16.S )J-s
I
I
I
Read Strobe width as used in the read timing table is defined as the period when both chip select and read inputs are low. Hence read commences when
both signals are low and terminates when either signal returns high.
Note 9: Hold time is guaranteed by design but not production tested. This limit is not used to calculate outgoing quality levels.
Note 10: Write Strobe width as used in the write timing table is defined as the period when both chip select and write inputs are low. Hence write commences when
both signals are low and terminates when either signal returns high.
Note 8:
AC Test Conditions
Input Pulse Levels
Input Rise and Fall Times
Input and Output
Reference Levels
TRI-STATE Reference
Levels (Note 12)
GNDt03.0V
6 ns (10%-90%)
1.3V
Active High
Active Low
Vee
-r-
+ O.SV
I
-o.sv
= 100 pF, includes jig and scope capacitance.
12: Sl = Vce for active low to high impedance measurements.
SI = GNO for active high to high impedance measurements.
SI = open for all other timing measurements.
Note 11: CL
Note
Capacitance
Symbol
CO
U1
'""-I
I\)
Address Valid Prior to Read Strobe
tAR
tROLL
""C
(TA
=
2SoC, f
Parameter
(Note 13)
=
Input 0 - -
Device
Under
Test
~
1 MHz)
Typ
Units
CIN
Input Capacitance
S
pF
COUT
Output Capacitance
7
pF
Note 13: This
parameter is not 100% tested.
Note 14: Output rise and fall times 25 ns max (10%-90%) with 100 pF load.
2-S3
51 (Note 12)
0
\
*
RL
=1K !l
_ Output
-'- CL
~
(Note 11)
TL/F/9980-2
»
:::
:E
«C\I
.....
8572AM-Military Version
Operation Conditions
Absolute Maximum Ratings
Supply Voltage (Vee) (Note 3)
Supply Voltage (Vss) (Note 3)
DC Input or Output Voltage
(VIN, VOUT)
Operating Temperature (TA)
Electro-Static Discharge Rating
Typical Values
Board
(}JA DIP
Socket
Min
Max
Unit
4.5
5.5
V
2.2 Vee- O.4 V
II)
co
D.
C
«'C\I
.....
II)
co
D.
C
(Notes 1 & 2)
The BB3 specifications are written to reflect the current
(at the time of printing) Rei Electrical Test Specifications (RETS) established by National Semiconductor for
this product. For a copy of the latest version of the
RETS please contact your local National Semiconductor sales office or distributor.
Supply Voltage (Vee)
-0.5Vto +7.0V
DC Input Voltage (VIN)
-0.5V to Vee + 0.5V
0.0
Vee
V
-55
+125
1
°C
kV
45°C/W
52°C/W
DC Output Voltage (VOUT)
-0.5V to Vee + 0.5V
Storage Temperature Range
- 65°C to + 150°C
Power Dissipation (PO)
500mW
Lead Temperature (Soldering, 10 sec.)
260°C
DC Electrical Characteristics
Vee = 5.0V ± 10%, Vss = 3V
Symbol
Parameter
Vee
Conditions
Min
Max
2.0
Vss - 0.1
Units
VIH
High Level Input Voltage
(Note 4)
All Inputs Except OSC IN.
OSC IN with External Clock
V
V
VIL
Low Level Input Voltage
All Inputs Except OSC IN.
OSC IN with External Clock
VOH
High Level Output Voltage
(Excluding OSC OUT)
5.5V
5.5V
lOUT = -20 JJ-A
lOUT = -4.0 mA
VOL
Low Level Output Voltage
(Excluding OSC OUT)
5.5V
5.5V
lOUT = 20 JJ-A
lOUT = 4.0 mA
0.1
0.25
V
V
0.8
0.1
V
V
V
V
Vee - 0.1
3.5
liN
Input Current (Except OSC IN)
5.5V
VIN = Vee or GND
±1.0
JJ-A
10Z
Output TRI-STATE Current
5.5V
VOUT = Vee or GND
±5.0
JJ-A
ICC
Quiescent Supply Current
(Note 7)
5.5V
5.5V
5.5V
Fose
VIN =
VIN =
VIN =
275
1.0
12.0
JJ-A
mA
mA
5.5V
5.5V
Fose = 4.9152 MHz
VIN = Vee or GND (Note 6)
VIN = VIH or VIL (Note 6) .
8
20
mA
mA
5.5V
Vss = GND, VIN = Vee or GND
Fose = 32.768 kHz
Fase = 4.9152 MHz
40
7.5
JJ-A
mA
OSC OUT = Open Circuit,
Other Pins = GND
Fose = 32.768 kHz
Fose = 4.9152 MHz
10
400
JJ-A
JJ-A
1.5
3.5
3.5
JJ-A
JJ-A
JJ-A
Icc
Iss
ISLK
Quiescent Supply Current
(Single Supply Mode)5.5V
(Note 7)
Standby Mode Battery
Supply Current
(Note 7)
OV
OV
Battery Leakage
5.5V
5.5V
5.5V
32.768 kHz
Vee or GND (Note 5)
Vee or GND (Note 6)
VIH or VIL (Note 6)
=
2.2V :::;: Vss :::;: 4.0V
25°C
-55°C
+ 125°C
-5
-5
-5
Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Unless otherwise specified all voltages are referenced to ground.
Note 3: For Fosc = 4.194304 or 4.9152 MHz. VBB minimum = 2.BV. In battery backed mode. VBB ,;; VCC - O.4V.
Single Supply Mode: Data retention voltage is 2.2V min.
In single Supply Mode (Power connected to Vcc pin) 4.5V ,;; VCC ,;; 5.5V.
Note 4: This parameter (VIH) is not tested on all pins at the same time.
Note 5: This specification tests Icc with all power fail circuitry disabled. by setting D7 of Interrupt Control Register 1 to O.
Note 6: This specification tests IcC with all power fail circuitry enabled. by setting D7 of Interrupt Control Register 1 to 1.
Note 7: asc IN is driven by a signal generator. Contents of the Test Register = OO(H) and the MFa pin is not configured as buffered oscillator out.
Note 1:
Note 2:
2-54
C
"C
8572AM-Military Version
(X)
U1
.......
N
l>
AC Electrical Characteristics
VCC
=
4.5V and 5.5V, VBB
Symbol
=
3V, V~
> VIH, CL = 100 pF (unless otherwise specified)
I
I
Parameter
Min
I
I
Max
Units
READ TIMING
tAR
Address Valid Prior to Read Strobe
20
ns
tRW
Read Strobe Width (Note 8)
80
ns
tco
Chip Select to Data Valid Time
80
ns
tAD
Read Strobe to Valid Data
70
ns
toz
Read or Chip Select to TRI·STATE
60
ns
tACH
Chip Select Hold after Read Strobe
0
ns
tos
Minimum Inactive Time between Read or Write Accesses
50
ns
tAW
Address Valid before Write Strobe
20
ns
tcw
Chip Select to End of Write Strobe
90
ns
tww
Write Strobe Width (Note 9)
80
ns
tow
Data Valid to End of Write Strobe
50
ns
tWCH
Chip Select Hold after Write Strobe
0
ns
WRITE TIMING
Note 8: Read Strobe width as used in the read timing table is defined as the period when both chip select and read inputs are low. Hence read commences when
both signals are low and terminates when either signal returns high.
Note 9: Write Strobe width as used in the write timing table is defined as the period when both chip select and write inputs are low. Hence write commences when
both Signals are low and terminates when either signal returns high.
AC Test Conditions
Input Pulse Levels
Input Rise and Fall Times
Input and Output
Reference Levels
TRI·STATE Reference
Levels (Note 11)
GNDto 3.0V
6 ns (10%-90%)
vee
1.3V
-r-
1
Active High + 0.5V
Active Low - 0.5V
Note 10: CL = 100 pF, includes jig and scope capacitance.
Input 0 -
Note 11: 51 = Vee for active low to high impedance measurements.
51 = GND for active high to high impedance measurements.
51 = open for all other timing measurements.
Capacitance
Symbol
(TA
=
25°C, f
Parameter
(Note 12)
~
= 1 MHz)
Typ
Units
CIN
Input Capacitance
5
pF
COUT
Output Capacitance
7
pF
Device
Under
Test
Note 12: This parameter i.s not 100% tested.
Note 13: Output rise and fall times 25 ns max (10%-90%) with 100 pF load.
2·55
51 (Note 11)
0
*=
*
c
\ = lK n
Output
-- G.
(Note 10)
TL/F/9980-24
C
'"
"C
(X)
U1
.......
N
l>
==
:ill
Vee>. If in battery backed mode and a pullup resistor is attached, it should be connected to a voltage
no greater than Vss.
3:
Vee
20
05
A2
19
04
A3
18
03
A4
17
02
Vee
16
01
DO
OSC IN
15
OSC OUT
14
INTR
GND
13
MFO
TL/F/9980-5
Top View
Order Number DP8572AN or DP8572AMD/883
See NS Package Number D24C or N24C.
Plastic Chip Carrier
INTR (Output): The interrupt output is used to interrupt the
processor when a timing event or power fail has occurred
and the respective interrupt has been enabled. The INTR
output is permanently configured active low, open drain. If in
battery backed mode and a pull-up resistor is attached, it
should be connected to a voltage no greater than Vss. The
output is a DC voltage level. To clear the INTR, write a 1 to
the appropriate bit(s) in the Main Status Register.
~ I~ I~ I~ >~I~
a.. 0z
00-07 (Input/Output): These 8 bidirectional pins connect
to the host J.LP's data bus and are used to read from and
write to the RTC. When the PFAIL pin goes low and a write
is not in progress, these pins are at TRI-STATE.
PFAIL (Input): In battery backed mode, this pin can have a
digital signal applied to it via some external power detection
logic. When PFAIL = logic 0 the RTC goes into a lockout
mode, in a minimum of 30 J.Ls or a maximum of 63 J.Ls unless
lockout delay is programmed. In the single power supply
mode, this pin is not useable as an input and should be tied
to Vee. Refer to section on Power Fail Functional Description.
AI
07
A2
06
A3
05
A4
04
NC
03
NC
02
Vee
01
~
0
VI
0
t::I
0
0
e
Z
<..:>
0
Z
e If!:a:
::::E
8
VI
0
TL/F/9980-6
..
Top View
Order Number DP8572A V
See NS Package Number V28A
Vee (Battery Power Pin): This pin is connected to a backup power supply. This power supply is switched to the internal circuitry when the Vee becomes lower than Vss. Utilizing this pin eliminates the need for external logic to switch in
and out the back-up power supply. If this feature is not to be
used then this pin must be tied to ground, the RTC programmed for single power supply only, and power applied to
the Vee pin.
.
2-57
:e
«
C\I
......
it)
co
c..
C
......
«
C\I
......
it)
co
c..
C
Functional Description
The memory map of the RTC is shown in the memory addressing table. The memory map consists of two 31 byte
pages with a main status register that is common to both
pages. A control bit in the Main Status Register is used to
select either page. Figure 2 shows the basic concept.
Page 0 contains all the clock timer functions, while page 1
has scratch pad RAM. The control registers are split into
two separate blocks to allow page 1 to be used entirely as
scratch pad RAM. Again a control bit in the Main Status
Register is used to select either control register block.
The DP8572A contains a fast access real time clock, interrupt control logic, power fail detect logic, and CMOS RAM.
All functions of the RTC are controlled by a set. of seven
registers. A simplified block diagram that shows the major
functional blocks is given in Figure 1.
The blocks are described in the following sections:
1. Real Time Clock
2. Oscillator Prescaler
3. Interrupt Logic
4. Power Failure Logic
5. Additional Supply Management
Page Select
=0
1F
RAM/TEST Register
1E
RAM
Page Select
1F
1D
Months TIme Save RAM
1E
RAM
1C
18
Day of Month TIme Save RAM
RAM
Hours TIme Save RAM
1D
1C
1A
Minutes TIme Save RAM
18
RAM
19
18
17
16
15
14
13
12
11
10
OF
OE
OD
OC
08
OA
09
08
07
06
05
Seconds TIme Save RAM
1A
RAM
Day of Week Compare RAM
19
RAM
Months Compare RAM
18
RAM
Day of Month Compare RAM
17
16
15
14
13
12
11
10
OF
OE
OD
OC
08
OA
09
08
07
06
05
04
RAM
03
02
RAM
01
RAM
Register Select
Hours Compare RAM
Minutes Compare RAM
Seconds Compare RAM
N/A
N/A
N/A
N/A
Day of Week Clock Counter
100's Julian Clock Counter
Units Julian Clock Counter
Years Clock Counter
Months Clock Counter
Day of Month Clock Counter
Hours Clock Counter
Minutes Clock Counter
Seconds Clock Counter
Yl00
Second Counter
=0 /
"
Register Select == 1
TIme Save Control Register
04
Interrupt Control Register 1
Periodic Flag Register
N/A
03
02
Interrupt Control Register 0
Output Mode Register
~_A
=1
RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM
TI.i~e:..M.Od.e R~/
N.. _ _ _ _ _0.1_.R.e.a.1
00
I
..
-
Main Status Register
TL/F/99BO-7
FIGURE 2. DP8572A Internal Memory Map
2-58
Functional Description
(Continued)
Save Enable bit (07) of the Time Save Control Register, and
then to write a zero. Writing a one into this bit will enable the
clock contents to be duplicated in the Time Save RAM.
Changing the bit from a one to a zero will freeze and store
the contents of the clock in Time Save RAM. The time then
can be read without concern for clock rollover, since internal logic takes care of synchronization of the clock. Because only the bits used by the clock counters will be
latched, the Time Save RAM should be cleared prior to use
to ensure that random data stored in the unused bits do not
confuse the host microprocessor. This bit can also provide
time save at power failure, see the Additional Supply Management Functions section. With the Time Save Enable bit
at a logical 0, the Time Save RAM may be used as RAM if
the latched read function is not necessary.
INITIAL POWER-ON of BOTH VBB and Vee
Vss and Vee may be applied in any sequence. In order for
the power fail circuitry to function correctly, whenever power
is off, the Vee pin must see a path to ground through a
maximum of 1 Mfl. The user should be aware that the control registers will contain random data. The first task to be
carried out in an initialization routine is to start the oscillator
by writing to the crystal select bits in the Real Time Mode
Register. If the DP8572A is configured for single supply
mode, an extra 50 p.A may be consumed until the crystal
select bits are programmed. The user should also ensure
that the RTC is not in test mode (see register descriptions).
REAL TIME CLOCK FUNCTIONAL DESCRIPTION
As shown in Figure 2, the clock has 10 bytes of counters,
which count from 1/100 of a second to years. Each counter
counts in BCD and is synchronously clocked. The count sequence of the individual byte counters within the clock is
shown later in Table VII. Note that the day of week, day of
month, day of year, and month counters all roll over to 1.
The hours counter in 12 hour mode rolls over to 1 and the
AM/PM bit toggles when the hours rolls over to 12
(AM = 0, PM = 1). The AM/PM bit is bit 07 in the hours
counter.
INITIALIZING AND WRITING TO THE
CALENDAR-CLOCK
Upon initial application of power to the RTC or when making
time corrections, the time must be written into the clock. To
correctly write the time to the counters, the clock would
normally be stopped by writing the Start/Stop bit in the Real
Time Mode Register to a zero. This stops the clock from
counting and disables the carry circuitry. When initializing
the clock's Real Time Mode Register, it is recommended
that first the various mode bits be written while maintaining
the Start/Stop bit reset, and then writing to the register a
second time with the Start/Stop bit set.
All other counters r.oll over to O. Also note that the day of
year counter is 12 bits long and occupies two addresses.
Upon initial application of power the counters will contain
random information.
The above method is useful when the entire clock is being
corrected. If one location is being updated the clock need
not be stopped since this will reset the prescaler, and time
will be lost. An ideal example of this is correcting the hours
for daylight savings time. To write to the clock "on the fly"
the best method is to wait for the 1/100 of a second periodic interrupt. Then wait an additional 16 p.s, and then write
the data to the clock.
READING THE CLOCK: VALIDATED READ
Since clocking of the counter occurs asynchronously to
reading of the counter, it is possible to read the counter
while it is being incremented (rollover). This may result in an
incorrect time reading. Thus to ensure a correct reading of
the entire contents of the clock (or that part of interest), it
must be read without a clock rollover occurring. In general
this can be done by checking a rollover bit. On this chip the
periodic interrupt status bits can serve this function. The
following program steps can be used to accomplish this.
PRESCALER/OSCILLATOR FUNCTIONAL
DESCRIPTION
Feeding the counter chain is a programmable prescaler
which divides the crystal oscillator frequency to 32 kHz and
further to 100 Hz for the counter chain (see Figure 3). The
crystal frequency that can be selected are: 32 kHz, 32.768
kHz, 4.9152 MHz, and 4.194304 MHz.
1. Initialize program for reading clock.
2. Dummy read of periodic status bit to clear it.
3. Read counter bytes and store.
4. Read rollover bit, and test it.
5. If rollover occured go to 3.
6. If no rollover, done.
from
Oscillator
To detect the rollover, individual periodic status bits can be
polled. The periodic bit chosen should be equal to the highest frequency counter register to be read. That is if only
SECONDS through HOURS counters are read, then the
SECONDS periodic bit should be used.
Frequency
Select
4rt---,--;:==t===::::;---,
READING THE CLOCK: INTERRUPT DRIVEN
Enabling the periodic interrupt mask bits cause interrupts
just as the clock rolls over. Enabling the desired update rate
and providing an interrupt service routine that executes in
less than 10 ms enables clock reading without checking for
a rollover.
32.000KHz
TLIF/9980-8
FIGURE 3. Programmable Clock Prescaler Block
READING THE CLOCK: LATCHED READ
Another method to read the clock that does not require
checking the rollover bit is to write a one into the Time
2-59
Functional Description (Continued)
The oscillator is programmed via the Real Time Mode Register to operate at various frequencies. The crystal oscillator
is designed to offer optimum performance at each frequency. Thus, at 32.768 kHz the oscillator is configured as a low
frequency and low power oscillator. At the higher frequencies the oscillator inverter is reconfigured. In addition to the
inverter, the oscillator feedback bias resistor is included on
chip, as shown in Figure 4. The oscillator input may be driven from an external source if desired. Refer to test mode
application note for details. The oscillator stability is enhanced through the use of an on chip regulated power supply.
INTERRUPT LOGIC FUNCTIONAL DESCRIPTION
The RTC has the ability to coordinate processor timing activities. To enhance this, an interrupt structure has been implemented which enables several types of events to cause
interrupts. Interrupts are controlled via two Control Registers in block 1 and two Status Registers in block O. (See
Register Description for notes on paging and also Figure 5
and Table I.)
The interrupts are enabled by writing a one to the appropriate bits in Interrupt Control Register 0 and/or 1.
TABLE I. Registers that are
Applicable to Interrupt Control
The typical range of trimmer capacitor (as shown in Oscillator Circuit Diagram Figure 4, and in the typical application) at
the oscillator input pin is suggested only to allow accurate
tuning of the oscillator. This range is based on a typical
printed circuit board layout and may have to be changed
depending on the parasitic capacitance of the printed circuit
board or fixture being used. In all cases, the load capacitance specified by the crystal manufacturer (nominal value
11 pF for the 32.768 crystal) is what determines proper oscillation. This load capcitance is the series combination of
capacitance on each side of the crystal (with respect to
ground).
Register Name
Main Status Register
Periodic Flag Register
Interrupt Control
Register 0
Interrupt Control
Register 1
Output Mode
Register
Register
Select
Page
Select
Address
X
0
X
0
OOH
03H
1
0
03H
1
0
04H
1
0
02H
The Interrupt Status Flag DO, in the Main Status Register,
indicates the state of INTR and MFO outputs. It is set when
either output becomes active and is cleared when all RTC
interrupts have been cleared and no further interrupts are
pending (Le., both INTR and MFO are returned to their inactive state). This flag enables the RTC to be rapidly polled by
the ,..,p to determine the source of an interrupt in a wiredOR interrupt system. (The Interrupt Status Flag provides a
true reflection of all conditions routed to the external pins.)
Internal Components
To
Prescaler
Status for the interrupts are provided by the Main Status
Register and the Periodic Flag Register. Bits 01-05 of the
Main Status Register are the main interrupt bits.
OSC OUT
+---101---....
These register bits will be set when their associated timing
events occur. Enabled Alarm comparisons that occur will
set its Main Status Register bit to a one. However, an external interrupt will only be generated if the Alarm interrupt
enable bit is set (see Figure 5).
Pin
XTAL
External
Components
Disabling the periodic interrupts will mask the Main Status
Register periodic bit, but not the Periodic Flag Register bits.
The Power Fail Interrupt bit is set when the interrupt is enabled and a power fail event has occurred, and is not reset
until the power is restored. If all interrupt enable bits are 0
no interrupt will be asserted. However, status still can be
read from the Main Status Register in a polled fashion (see
Figure 5).
TL/F/9980-9
FIGURE 4. Oscillator Circuit Diagram
XTAL
Co
Ct
ROUT
(Switched
Internally)
32/32.768 kHz
4.194304 MHz
4.9152 MHz
47 pF
68 pF
68 pF
2 pF-22 pF
·0 pF-80 pF
29 pF-49 pF
150 kn to 350 kn
500n to 900n
500n to 900n
To clear a flag in bits 02 and 03 of the Main Status Register
a 1 must be written back into the bit location that is to be
cleared. For the Periodic Flag Register reading the status
will reset all the periodic flags.
2-60
C
Functional Description
""C
CD
(Continued)
Interrupts Fall Into Three Categories:
Figure 5. These flags constantly sense the periodic signals
and may be used whether or not interrupts are enabled.
These flags are cleared by any read or write operation performed on this register.
1. The Alarm Compare Interrupt: Issued when the value in
the time compared RAM equals the counter.
2. The Periodic Interrupts: These are issued at every increment of the specific clock counter signal. Thus, an interrupt is issued every minute, second, etc. Each of these
interrupts occurs at the roll-over of the specific counter.
To generate periodic interrupts at the desired rate, the associated Periodic Interrupt Enable bit in Interrupt Control Register 0 must be set. Any combination of periodic interrupts
may be enabled to operate simultaneously. Enabled periodic interrupts will now affect the Periodic Interrupt Flag in the
Main Status Register.
3. The Power Fail Interrupt: Issued upon recognition of a
power fail condition by the internal sensing logic. The
power failed condition is determined by the signal on the
PFAIL pin. The internal power fail signal is gated with the
chip select signal to ensure that the power fail interrupt
does not lock the chip out during a read or write.
When a periodic event occurs, the Periodic Interrupt Flag in
the Main Status Register is set, causing an interrupt to be
generated. The fLP clears both flag and interrupt by writing a
"1" to the Periodic Interrupt Flag. The individual flags in the
periodic Interrupt Flag Register do not require clearing to
cancel the interrupt.
If all periodic interrupts are disabled and a periodic interrupt
is left pending (Le., the Periodic Interrupt Flag is still set), the
Periodic Interrupt Flag will still be required to be cleared to
cancel the pending interrupt.
ALARM COMPARE INTERRUPT DESCRIPTON
The alarm/time comparison interrupt is a special interrupt
similar to an alarm clock wake up buzzer. This interrupt is
generated when the clock time is equal to a value programmed into the alarm compare registers. Up to six bytes
can be enabled to perform alarm time comparisons on the
counter chain. These six bytes, or some subset thereof,
would be loaded with the future time at which the interrupt
will occur. Next, the appropriate bits in the Interrupt Control
Register 1 are enabled or disabled (refer to detailed description of Interrupt Control Register 1). The RTC then compares these bytes with the clock time. When all the enabled
compare registers equal the clock time an alarm interrupt is
issued, but only if the alarm compare interrupt is enabled
can the interrupt be generated externally. Each alarm compare bit in the Control Register will enable a specific byte for
comparison to the clock. Disabling a compare byte is the
same as setting its associated counter comparator to an
"always equal" state. For example, to generate an interrupt
at 3:15 AM of every day, load the hours compare with 0 3
(BCD), the minutes compare with 1 5 (BCD) and the faster
counters with 0 0 (BCD), and then disable all other compare
registers. So every day when the time rolls over from
3:14:59.99, an interrupt is issued. This bit may be reset by
writing a one to bit 03 in the Main Status Register at any
time after the alarm has been generated.
POWER FAIL INTERRUPTS DESCRIPTION
The Power Fail Status Flag in the Main Status Register
monitors the state of the internal power fail signal. This flag
may be interrogated by the fLP, but it cannot be cleared; it is
cleared automatically by the RTC when system power is
restored. To generate an interrupt when the power fails, the
Power Fail Interrupt Enable bit in Interrupt Control Register
1 is set. Although this interrupt may not be cleared, it may
be masked by clearing the Power Fail Interrupt Enable bit.
POWER FAILURE CIRCUITRY FUNCTIONAL
DESCRIPTION
Since the clock must be operated from a battery when the
main system supply has been turned off, the DP8572A provides circuitry to simplify design in battery backed systems.
This switches over to the back up supply, and isolates itself
from the host system. Figure 6 shows a simplified block
diagram of this circuitry, which consists of three major sections; 1) power loss logic: 2) battery switch over logic: and 3)
isolation logic.
If time comparison for an individual byte counter is disabled,
that corresponding RAM location can then be used as general purpose storage.
Detection of power loss occurs when PFAIL is low. Debounce logic provides a 30 fLS-63 fLs debounce time, which
will prevent noise on the PFAIL pin from being interpreted
as a system failure. After 30 fLS-63 fLs the debounce logic
times out and a signal is generated indicating that system
power is marginal and is failing. The Power Fail Interrupt will
then be generated.
PERIODIC INTERRUPTS DESCRIPTION
The Periodic Flag Register contains six flags which are set
by real-time generated "ticks" at various time intervals, see
2-61
CJ1
......
N
»
.......
c
""C
CD
CJ1
......
N
»
=:
D.P8572A/DP8572AM
"T1
I:
:::s
...
(")
O·
:::s
~
Interrupt Control Registers
Real
TIme
Periodic
Pulse
Signals
(also to
Periodic
Flags)
loIain Status
Register
C
Interrrupt Control
Register
~m
CD
tn
(")
...
::!.
"C
I
Output Mode
~~~~~~~r
Buffered 0
lscmator
O·
Bit
:::s
oo
~
5"
t.4FO
Signal
t.4UX
c
CD
t.4FO Output
S
----+
Output
Buffer
Interrupt
t.4ode
Selected
I\)
m
I\)
Alarm
Compare
Signals
Power
Fail
~utput
Output
Buffer
TLIF/99BO-10
FIGURE 5. Interrupt Control Logic Overview
Functional Description
(Continued)
Battery Switchover
Vee
~
V+
~
Power
Fail Logic
lockout
PFAll
(External
power fall
signal)
Delayed
lockout
>--+---1
Delay
Enable
Data
Address
and
Control
Buffers
00:07
5
AO:A4
3
CS,iffi,WR
TLIF/9980-11
FIGURE 6. System-Battery Swltchover (Upper Left), Power Fail
and Lock-Out Circuits (Lower Right)
resistor should be connected to a voltage no greater than
If chip select is low when a power failure is detected, a
safety circuit will ensure that if a read or write is held active
continuously for greater than 30 fJ-s after the power fail sig·
nal is asserted, the lock·out will be forced. If a lock-out delay
is enabled, the OP8572A will remain active for 480 fJ-s after
power fail is detected. This will enable the fJ-P to perform
last minute bookkeeping before total system collapse.
When the host CPU is finished accessing the RTC it may
force the bus lock-out before 480 fJ-s has elapsed by reset·
ting the delay enable bit.
Vss·
TABLE II. Pin Isolation during a Power Failure
Pin
~,RO,WR
AO-A4
00-07
Oscillator
PFAIL
INTR, MFO
The battery switch over circuitry is completely independent
of the PFAIL pin. A separate circuit compares Vee to the
Vss voltage. As the main supply fails, the RTC will continue
to operate from the Vee pin until Vee falls below the Vss
voltage. At this time, the battery supply is switched in, Vee is
disconnected, and the device is now in the standby mode. If
indeterminate operation of the battery switch over circuit is
to be avoided, then the voltage at the Vee pin must not be
allowed to equal the voltage at the Vss pin.
PFAIL =
Logic 0
Locked Out
Locked Out
Locked Out
Not Isolated
Not Isolated
Not Isolated
Standby Mode
Vas> Vee
Locked Out
Locked Out
Locked Out
Not Isolated
Not Isolated
Open Drain
The Interrupt Power Fail Operation bit in the Real-Time
Mode Register determine whether or not the interrupts will
continue to function after a power fail event.
As power returns to the system, the battery switch over circuit will switch back to Vee power as soon as it becomes
greater than the battery voltage. The chip will remain in the
locked out state as long as PFAIL = o. When PFAIL = 1
After the generation of a lock-out signal, and eventual
switch in of the battery supply, the pins of the RTC will be
configured as shown in Table II. Outputs that have a pull-up
2-63
==
«
N
.....
Lt)
co
D-
C
......
«
N
.....
Lt)
co
D-
C
Functional Description
(Continued)
the chip is unlocked, but only after another 30 J-Ls min ~
63 J-Ls max debounce time. The system designer must ensure that his system is stable when power has returned .
The power fail circuitry contains active linear circuitry that
draws supply current from VCC. In some cases this may be
undesirable, so this circuit can be disabled by masking the
power fail interrupt. The power fail input can perform all
lock-out functions previously mentioned; except that no external interrupt will be issued. Note that the linear power fail
circuitry is switched off automatically when using Vss in
standby mode.
. This complete address space is organized into" two pages.
Page 0 contains two blocks of control registers, timers, real
time clock counters, and special purpose RAM, while page
1 contains general purpose RAM. Using two blocks enables
the 9 control registers to De mapped into 5 locations. The
. only register that does not get switched is the Main Status
'Register. It contains the' page select bit and the register
select bit as well as status information.
A memory map is shown in Figure 2 and register addressing
in Table III. They show theriame; address and page locations for the OP8572A.
LOW BATTERY, INITIAL POWER ON DETECT, AND
POWER FAIL TIME SAVE
.
TABLE III. Register/Counter/RAM
Addressing for DP8572A
There are three other functions provided on the OP8572A to
ease power supply control. These are an initial Power On
detect circuit, which also can be used as a time. keeping
failure detect, a low battery detect circuit, and a time save
on power failure.
'
AO-4
PS
RS
(Note 1) (Note 2)
Description
CONTROL REGISTERS
00
03
04
01
02
03
04
On initial power up the Oscillator' Fail Flag will be set to a
one and the real time clock start bit reset to a zero. This
indicates that an oscillator fail event has occurred, and time
keeping has failed.
The Oscillator. Fail flag will not be reset until the real-time
clock is started. This allows the system to discriminate between an initial power-up and recovery from a power failure.
If the battery backed mode is selected, then bit 06 of the'
Periodic Flag Register must be written low. This will noraffect the contents of the Oscillator Fail Flag.
X
X
0
0
0
0
0
0
0
0
1
1
1
1
Main Status Register
Periodic Flag Register
Time Save Control Register
Real Time Mode Register
Output Mode Register
Interrupt Control Register 0
Interrupt Control Register 1
COUNTERS (CLOCK CALENDAR)
Another status bit is the low battery detect. This bit is set
only when the clock is operating under the VCC pin, and
when the battery voltage is determined to .beless than 2.1 V
(typical). When the power fail interrupt enable bit is low, it
disables the power fail circuit and will also shut off the low
battery voltage detection circuit as well.
05
06
07
08
09
0
0
0
0
0
X
X
X
X
X
OA
'OS
OC
00
OE
0
0
0
0
0
X
X
X
X
X
1/100, 1/10 Seconds (0-99)
(0-59)
Seconds
(0-59)
Minutes
(1-12, 0-23)
Hours
Days of
. Month
(1 ~28/29/30/31)'
' Months
(1-12)
Years
(0-99)'
Julian Date (LSS) . (0-99) (Note 3)
(0-3)
Julian Date
(1-7)
Day of Week
TIME COMPARE RAM
To relieve CPU overhead for saving time upon power failure,
the Time Save Enable bit is provided to do this automatical-:
Iy. (See also Reading the Clock: Latched Read.) The Time
Save Enable bit, when set, causes the Time Save RAM to
follow the contents of the clock. This bit can be reset by
software, but if set before a power failure occurs, it will auto-'
matically be reset when the clock switches to'thebattery
supply (not when a power failure is detected by the PFAIL
pin). Thus, writing a one to the Time Save bit enables both a
software write or power fail write.
X
X
X
Sec Compare RAM
Min Compare RAM
Hours Compare
RAM
16'
0
X
DOMCo~pare
,17 '
0
X
RAM
Months Compare
0
X
(1-12)
RA~
DOW Compare RAM (1-7)
"
18
,
The OP8572A can be used in a single power supply applica-'
tion. To achieve this, the Vss pin must be connected to
ground, and the power connected to VCC and PFAIL pins.
The Oscillator Failed/Single Supply bit in the Periodic Flag
Register should be set to a logic 1, which will disable the
oscillator battery reference circuit. The power fail interrupt
should also be disabled. This will turn off the linear power
fail detection circuits, and will eliminate any quiescent power
drawn through these circuits. Until the crystal select bits are
initialized, the OP8572A may consume about 50 J-LA due to
arbitrary oscillator selection at power on.
(0-59)
(0-59)
,.
(1-12, 0-23)
(1-28/29/30/31 )
:
, TIME SAVE RAM
SINGLE POWER SUPPLY APPLICATIONS
I
'0
0
0
·13
14
15
X
.,
Seconds Time Save RAM
','
Minute's Time Save RAM
Hours Time Save RAM
Day of MonthTime Save RAM
Months Time,Save RAM
19
1A
1S
1C
10
0
0
0,
,0
0 ,.
1E
1F
0
0
1
X
RAM
RAM/Test Mode Register
01-1F
1
X
2nd Page General Purpose RAM
"
X
, X.
X
X
Note 1: PS-Page Select (Bit D7 of Main Status Register)
Note 2: RS-Register Select (Bit D6 of Main Status Register)
Note 3: The lSB counters count 0 -+ 99 until the hundreds of days counter
reaches 3. Then the lSB counters count to 65 or 66 (if a leap year). The
rollover is from 365/366 to 1.
(This extra 50 J-LA is not consumed if the battery backed
mode is selected).
DETAILED REGISTER DESCRIPTION
There are 5 external address bits: Thus, the host microprocessor has access to 28 locations at one time. An internal
switching scheme provides a total of 61 locations.
2-64
Functional Description
(Continued)
MAIN STATUS REGISTER
L PS
The Periodic Flag Register has the same bit for bit correspondence as Interrupt Control Register 0 except for 06
and 07. For normal operation (Le., not a single supply application) this register must be written to on initial power up or
after an oscillator fail event. 00-05 are read only bits, 06
and 07 are read/write.
I RS I R I RIAL I PERI PF liNT]
I
I
L
DO Interrupt Status
L - 01
Power rail Interrupt
' - - - - - 02 Period Interrupt
L-_ _ _ _ 03 Alarm Interrupt
L-_ _ _ _ _ 04 RAI.l
00-05: These bits are set by the real time rollover events:
(Time Change = 1). The bits are reset when the register is
read and can be used as selective data change flags.
L - - - - - - - O S RAI.l
' - - - - - - - - - - 06 Register Select Bit
'--_ _ _ _ _ _ _ _ _ 07 Page Select Bit
06: This bit performs a dual function. When this bit is read, a
one indicates that an oscillator failure has occurred and the
time information may have been lost. Some of the ways an
oscillator failure might be caused are: failure of the crystal,
shorting OSC IN or OSC OUT to GNO or Vee, removal of
crystal, removal of battery when in the battery backed mode
(when a "0" is written to D6), lowering the voltage at the
Vee pin to a value less than 2.2V when in the. battery
backed mode. Bit 06 is automatically set to 1 on initial power-up or an oscillator fail event. The oscillator fail flag is
reset by writing a one to the clock start/stop bit in the Real
Time Mode Register, with the crystal oscillating.
TL/F/99BO-12
The Main Status Register is always located at address 0
regardless of the register block or the page selected.
00: This read only bit is a general interrupt status bit that is
taken directly from the interrupt pins. The bit is a one when
an interrupt is pending on either the INTR pin or the MFO
pin (when configured as an interrupt). This is unlike 03
which can be set by an internal event but may not cause an
interrupt. This bit is reset when the interrupt status bits in the
Main Status Register are cleared.
When 06 is written to, it defines whether the TCP is being
used in battery backed (normal) or in a single supply mode
application. When set to a one this bit configures the Tep
for single power supply applications. This bit is automatically
set on initial power-up or an oscillator fail event. When set,
06 disables the oscillator reference circuit. The result is that
the oscillator is referenced to Vee. When a zero is written to
06 the oscillator reference is enabled, thus the oscillator is
referenced to Vee. This allows operation in standard battery
standby applications.
01-03: These three bits of the Main Status Register are the
main interrupt status bits. Any bit may be a one when any of
the interrupts are pending. Once an interrupt is asserted the
fLP will read this register to determine the cause. These
interrupt status bits are not reset when read. Except for 01,
to reset an interrupt a one is written back to the corresponding bit that is being tested. 01 is reset whenever the PFAIL
pin = logic 1. This prevents loss of interrupt status when
reading the register in a polled mode. 01 and 03 are set
regardless of whether these interrupts are masked or not by
bits 06 and 07 of Interrupt Control Registers 0 and 1.
At initial power on, if the OP8572A is going to be programmed for battery backed mode, the Vse pin should be
connected to a potential in the range of 2.2V to Vee O.4V.
04-05: General purpose RAM bits.
06 and 07: These bits are Read/Write bits that control
which register block or RAM page is to be selected. Bit 06
controls the register block to be accessed (see memory
map). The memory map of the clock is further divided into
two memory pages. One page is the registers, clock and
timers, and the second page contains 31 bytes of general
purpose RAM. The page selection is determined by bit 07.
For single supply mode operation, the Vse pin should be
connected to GNO and the PFAIL pin connected to Vee.
07: Writing a one to this bit enables the test mode register
at location 1F (see Table III). This bit should be forced to
zero during initialization for normal operation. If the test
mode has been entered, clear the test mode register before
leaving test mode. (See separate test mode application
note for further details.)
PERIODIC FLAG REGISTER
n.t
OSF 11m. 10ms 100m. Is 110. 1 min
I
LOO minutes flag
TIME SAVE CONTROL REGISTER
L - O l 10 second flag
L...-_ _ _ 02 second. flag
L Tn LBTpF"D1
R I R I RI R I R I
I L::~
' - - - - - - 03 100 mllllsec. flag
' - - - - - - - - 04 10 mlilisec. flag
02 RAM
' - - - - - - - - - - 05 mlill-seconds flag
' - - - - - - - - - - - 06 Oscillator Failed/Single Supply Bit
' - - -_ _ _ _ _ _ _ _ _ _ 07 T.st Mod. Enabl.
' - - - - - - 03 RAM
' - - - - - - - 04 RAM
TL/F/99BO-13
' - - - - - - - - 05
pr Delay Enabl.
' - - - - - - - - - - 06 Low Battery flag
' - - - - - - - - - - - 07 TIm. Save Enable
TLlF/9980-14
00-04: General purpose RAM bits.
2-65
Functional Description
(Continued)
05: The Delay Enable bit is used when a power fail occurs.
02: The count mode for the hours counter can be set to
either 24 hour mode or 12 hour mode with AM/PM indicator.
A one will place the clock in 12 hour mode.
If this bit is set, a 480 IJ-s delay is generated internally before
the IJ-P interface is locked out. This will enable the IJ-P to
access the registers for up to 480 IJ-s after it receives a
power fail interrupt. After a power failure is detected but
prior to the 480 IJ-s delay timing out, the host IJ-P may force
immediate lock out by resetting the Delay Enable bit. Note if
this bit is a 0 when power fails then after a delay of 30 IJ-s
min/63 IJ-s max the IJ-P cannot read the chip.
03: This bit is the master Start/Stop bit for the clock. When
a one is written to this bit the real time counter's prescaler
and counter chain are enabled. When this bit is reset to zero
the contents of the real time counter is stopped and the
prescaler is cleared. When the RTC is initially powered up
this bit will be held at a logic 0 until the oscillator starts
functioning correctly after which this bit may be modified. If
an oscillator fail event occurs, this bit will be reset to logic O.
06: This read only bit is set and reset by the voltage at the
Vee pin. It can be used by the IJ-P to determine whether the
battery voltage at the Vee pin is getting too low. A comparator monitors the battery and when the voltage is lower than
2.1 V (typical) this bit is set. The power fail interrupt must be
enabled to check for a low battery voltage.
04: This bit controls the operation of the interrupt output in
standby mode. If set to a one it allows Alarm, Periodic, and
Power Fail interrupts to be functional in standby mode. Note
that the MFO pin is configured as open drain in standby
.
mode.
07: Time Save Enable bit controls the loading of real-timeclock data into the Time Save RAM. When a one is written
to this bit the Time Save RAM will follow the corresponding
clock registers, and when a zero is written to this bit the time
in the Time Save RAM is frozen. This eliminates any synchronization problems when reading the clock, thus negating the need to check for a counter rollover during a read
cycle.
If bit 04 is set to a zero then bits 00-05 of Interrupt Control
Register 0 and bits 06 and 07 of Interrupt Control Register
1 will be reset when the RTC enters the standby mode
(Vee> Vec>. They will have to be re-configured when system (VeC> power is restored.
05: General purpose RAM.
06 and 07: These two bits select the crystal clock frequency as per the following table:
This bit must be set to a one prior to power failing to enable
the Time Save feature. When the power fails this bit is automatically reset and the time is saved in the Time Save RAM.
REAL TIME MOOE REGISTER
I XTlI xTol R IIPF IcssI12HI LY1I LYOI
L:
DO Leap Year LSB
01 Leap Year MSB
02 12/24 hour mode
XT1
XTO
Crystal
Frequency
0
0
1
1
0
1
0
1
32.768 kHz
4.194304 MHz
4.9152 MHz
32.000 kHz
All bits are Read/Write, and any mode written into this register can be determined by reading the register. On initial
power up these bits are random.
03 Clock Start/Stop
04 Interrupt PF Operation
05 RAM
OUTPUT MOOE REGISTER
06 Crystal Fre·quency LSB
I MO I R I R I R I R I R I R I R I
07 Crystal Frequency MSB
L
TLIF/9980-15
00-01: These are the leap year counter bits. These bits are
written to set the number of years from the previous leap
year. The leap year counter increments on December 31st
and it internally enables the February 29th counter state.
This method of setting the leap year allows leap year to
occur whenever the user wishes to, thus providing flexibility
in implementing Japanese leap year function.
LY1
LYO
DO RAM
01 RAM
02 RAM
03 RAM
04 RAM
05 RAM
06 RAM
07 MFO Pin as Oscillator
Leap Year
Counter
TL/F/9980-16
00-06: General Purpose RAM
0
0
1
1
0
1
0
1
Leap Year Current Year
Leap Year Last Year
Leap Year 2 Years Ago
Leap Year 3 Years Ago
2-66
c
-a
Q)
U1
......
Functional Description
(Continued)
07: This bit is used to program the signal appearing at the
MFO output, as follows:
07
MFO Output Signal
o
Power Fail Interrupt
Buffered Crystal Oscillator
1
INTERRUPT CONTROL REGISTER 1
Lpre~ALtlOO~J"o lDO!t
N
HR~ I.tH~ SCl
I
I
L-- DO Second compare enable
L - 01
I.tlnute compare enable
- - - - 02 Hour compare enable
' - - - - - 0 3 Day of month enable
INTERRUPT CONTROL REGISTER 0
' - - - - - - - 04 I.tonth compare enable
" ' - - - - - - - - 05 Day of week enable
I R I R 11ml tm Ihml SITS I "'HI
L DO t.!lnutes enable
I
L - 01
.....- - - - - - - - 06 Alarm Interrupt enable
10 second enable
" ' - - - - - - - - - - - 07 Power fall Interrupt enable
TL/F/9980-18
" ' - - - - 02 Seconds enable
00-05: Each of these bits are enable bits which will enable
" ' - - - - - - 03 100 mlilisec enable
a comparison between an individual clock counter and its
associated compare RAM. If any bit is a zero then that
clock-RAM comparator is set to the "always equal" state
and the associated TIME COMPARE RAM byte can be used
as general purpose RAM. However, to ensure that an alarm
interrupt is not generated at bit D3 of the Main Status Register, all bits must be written to a logic zero.
" ' - - - - - - - 0 4 10 mlilisec enable
" ' - - - - - - - - 0 5 mlilisec enable
~---------06
RAt.!
L----_______ 07 RAt.!
TL/F/9980-17
06: In order to generate an external alarm compare interrupt to the p.P from bit D3 of the Main Status Register, this
bit must be written to a logic 1. If a battery backed mode is
selected and the DP8572A is in standby (Vaa > Vee), then
this bit is controlled by D4 of the Real Time Mode Register.
00-05: These bits are used to enable one of the selected
periodic interrupts by writing a one into the appropriate bit.
These interrupts are issued at the rollover of the clock. For
example, the minutes interrupt will be issued whenever the
minutes counter increments. In all likelihood the interrupt
will be enabled asynchronously with the real time change.
Therefore, the very first interrupt will occur in less than the
periodic time chosen, but after the first interrupt all subsequent interrupts will be spaced correctly. These interrupts
are useful when minute, second, real time reading, or task
switching is required. When all six bits are written to a 0 this
disables periodic interrupts from the Main Status Register
and the interrupt pin. If a battery backed mode is selected
and the DP8572A is in standby (Vaa > Vee), then these bits
are controlled by D4 of the Real Time Mode Register.
07: The MSB of this register is the enable bit for the Power
Fail Interrupt. When this bit is set to a one an interrupt will
be generated to the p.P when Vaa > Vee. If a battery
backed mode is selected and the DP8572A is in standby
(Vaa > Vee), then this bit is controlled by D4 of the Real
Time Mode Register.
This bit also enables the low battery detection analog circuitry.
.06 and 07: General Purpose RAM.
2-67
l>
'"
C
-a
Q)
......
U1
N
l>
3:
:E
Vee (Standby Mode).
10. Initialize the rest of the chip as needed.
Typical Application
RIO
Iotaln Supply
Battery Supply
01 0
A low going user
generated power
flln signal should
b. presented to the
prAll pin.
~
o
III
III
DP8572A
Q)
(,)
OSC INt--+----.
Real Time
o
a.
o
~
2-22 pr
Clock
32.768KHz
~
(,)
~
OSC OUT
T
J.7PF
GNO
TLIF /9980-19
-These components may be necessary to meet UL requirements for lithium batteries. Consult battery manufacturer.
2-69
......
N
»
......
c
"'D
CD
U1
......
N
»
3:
Typical Performance Characteristics
Operating Current va
Supply Voltage
(Single Supply Mode
Fosc = 32.768 kHz)
Operating Current va
Supply Voltage
(Battery Backed Mode
Fosc = 32.768 kHz)
1400
I
160
J
1/
2.0
4.0
3.0
V
~ 1000
/
120
/
1200
~
600
6.0
5.0
/
/
800
VcC
Vee. Additionally, two supply pins are provided. When Vss
> Vee, internal Circuitry will automatically switch from the
main supply to the battery supply.
The DP8573A's interrupt structure provides three basic
types of interrupts: Periodic, Alarm/Compare, and Power
Fail. Interrupt mask and status registers enable the masking
and easy determination of each interrupt.
Features
• Full function real time clock/calendar
- 12/24 hour mode timekeeping
- Day of week counter
- Parallel resonant oscillator
• Power fail features
- Internal power supply switch to external battery
- Power Supply Bus glitch protection
- Automatic log of time into RAM at power failure
• On-Chip interrupt structure
- Periodic, alarm, and power fail interrupts
Block Diagram
OSC
out
V+
Vea
vee
Logic
RD
Power
Real Time
Clock Counters
CS
WR
OSC
In
Fall
",p
Bus
Alarm Compare
and Time Save
RAM
INTR
FIGURE 1
2-71
t.tFO
TLIF/9981-1
Absolute Maximum Ratings
Operation Conditions
(Notes 1 & 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
-0.5Vto +7.0V
Supply Voltage (Vee)
Supply Voltage (Vee) (Note 3)
Supply Voltage (Vss) (Note 3)
DC Input or Output Voltage
(VIN' VOUT)
Operation Temperature (TA)
Electr-Static Discharge Rating
Transistor Count
Typical Values
Board
OJA DIP
. Socket
DC Input Voltage (VIN)
-0.5V to Vee +0.5V
-0.5V to Vee + 0.5V
DC Output Voltage (VOUT)
Storage Temperature Range
- 65°C to + 150°C
Power Dissipation (PD)
500mW
Lead Temperature (Soldering, 10 sec.)
260°C
0JA PLCC
Board
Socket
Min
4.5
2.2
Max
5.5
Vee- 0.4
Unit
V
V
0.0
Vee
V
-40
+85
1
10,300
°C
kV
I
59°C/W
65°C/W
80°C/W
88°C/W
DC Electrical Characteristics
Vee = 5V ±10%, Vss
Symbol
= 3V, VPFAll > VIH, Cl = 100 pF (unless otherwise specified)
Conditions
Min
VIH
High Level Input Voltage
(Note 4)
Parameter
Any Inputs Except OSC IN,
OSCIN with External Clock
2.0
Vss -0.1
Vil
Low Level Input Voltage
All Inputs Except OSC IN
OSC IN with External Clock
VOH
High Level Output Voltage
(Excluding OSC OUT)
lOUT
lOUT
= -20 J-tA
= -4.0 mA
VOL
Low Level Output Voltage
(Excluding OSC OUT)
lOUT
lOUT
= 20 J-tA
= 4.0 mA
Max
V
V
0.8
0.1
V
V
V
V
Vee -0.1
3.5
= Vee or GND
Units
0.1
0.25
V
V
liN
Input Current (Except OSC IN)
VIN
±1.0
J-tA
IOZ
Output TRI-STATE® Current
VOUT
= Vee or GND
±5.0
J-tA
IlKG
Output High Leakage Current
T1, MFa, INTR Pins
VOUT = Vee or GND
Outputs Open Drain
±5.0
J-tA
lee
Quiescent Supply Current
(Note 6)
~VIN =
250
1.0
12.0
J-tA
mA
mA
Quiescent Supply Current
(Single Supply Mode)
(Note 7)
Vss = GND
VIN = Vee or GND
Fose = 32.768 kHz
40
J-tA
Standby Mode Battery
Supply Current
(Note 7)
Vee = GND
OSC OUT = open circuit,
other pins = GND
Fose = 32.768 kHz
10
J-tA
Battery Leakage
2.2V :5: Vss :5: 4.OV
other pins at GND
Vee = GND
Vee = 5.5V
1.5
J-tA
J-tA
lee
Iss
ISlK
.
Fose
= 32.768 kHz
Vee or GND (Note 5)
VIN = Vee or GND (Note 6)
VIN = VIH or Vil (Note 6)
-5
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: In battery backed mode, VBB :S: Vcc - O.4V.
Single Supply Mode: Data retention voltage is 2.2V min.
In single Supply Mode (Power connected to VCC pin) 4.5V s: Vee :S: 5.5V.
Note 4: This parameter (VI H) is not tested on all pins at the same time.
Note 5: This specification tests Icc with all power fail Circuitry disabled, by setting 07 of Interrupt Control Register 1 to O.
Note 6: This specification tests Icc with all power fail Circuitry enabled, by setting 07 of Interrupt Control Register 1 to 1.
Note 7: OSC IN is driven by a signal generator. Contents of the Test Register = OO(H) and the MFO pin is not configured as buffered oscillator out.
2-72
I
AC Electrical Characteristics
Vcc
= 5V ± 10%, VBB = 3V, VPFAIL > VIH, CL = 100 pF (unless otherwise specified)
Symbol
I
I
Parameter
Min
I
I
Max
Units
READ TIMING
tAR
Address Valid Prior to Read Strobe
20
tRW
Read Strobe Width (Note 8)
80
tco
Chip Select to Data Valid Time
tRAH
Address Hold after Read (Note 9)
ns
ns
80
ns
ns
3
tRO
Read Strobe to Valid Data
70
ns
toz
Read or Chip Select to TRI-STATE
60
ns
tRCH
Chip Select Hold after Read Strobe
0
ns
tos
Minimum Inactive Time between Read or Write Accesses
50
ns
tAW
Address Valid before Write Strobe
20
ns
tWAH
Address Hold after Write Strobe (Note 9)
3
ns
tcw
Chip Select to End of Write Strobe
90
ns
tww
Write Strobe Width (Note 10)
80
ns
tow
Data Valid to End of Write Strobe
50
ns
tWOH
Data Hold after Write Strobe (Note 9)
3
ns
tWCH
Chip Select Hold after Write Strobe
0
ns
WRITE TIMING
INTERRUPT TIMING
Clock rollover to INTR out typically 16.5 P.S
tROLL
Note 8: Read Strobe width as used in the read timing table is defined as the period when both chip select and read inputs are low. Hence read commences when
both signals are low and terminates when either signal returns high.
Note 9: Hold time is guaranteed by design but not production tested. This limit is not used to calculate outgoing quality levels.
Note 10: Write Strobe width as used in the write timing table is defined as the period when both chip select and write inputs are low. Hence write commences when
both signals are low and terminates when either signal returns high.
AC Test Conditions
Input Pulse Levels
Input Rise and Fall Times
Input and Output
Reference Levels
TRI-STATE Reference
Levels (Note 12)
GNDt03.0V
6 ns (10%-90%)
Vee
1.3V
-r-
Active High + 0.5V
Active Low - 0.5V
I
Note 11: CL = 100 pF, includes jig and scope capacitance.
Note 12: Sl = Vee for active low to high impedance measurements.
S1 = GNO for active high to high impedance measurements.
Sl = open for all other timing measurements.
Capacitance
Symbol
(TA
Input 0 - -
~
= 25°C, f = 1 MHz)
Parameter
(Note 14)
Typ
Units
CIN
Input Capacitance
5
pF
COUT
Output Capacitance
7
pF
Device
Under
Test
Note 13: This parameter is not 100% tested.
Note 14: Output rise and fall times 25 ns max (10%-90%) with 100 pF load.
2-73
SI (Note 12)
0
.~
.~
:.
~
=
RL lK D-. Output
*
-'- CL
(Nota 11)
TLlF/9981-2
Timing Waveforms
=t-tAR-----Read Timing Diagram
'0-'
,...---
~CH
------~~----~---~W--------~~~-'I
DATA
Valid Data
TL/F/9981-3
Write Timing Diagram
Ao-4
I+------tww-----.r
------~~I
I"--~I
'-tow
DATA
- - - - - - - - - - - - - ( C - V a - l i d - D a - - t a........ ) - - - TLlF/9981-4
Pin Description
CS, RD, WR (Inputs): These pins interface to tJoP control
lines. The CS pin is an active low enable for the read and
write operations. Read and Write pins are also active low
and enable reading or writing to the RTe. All three pins are
disabled when power failure is detected. However, if a read
or write is in progress at this time, it will be allowed to complete its cycle.
battery backed mode and a pull-up resistor is attached, it
should be connected to a voltage no greater than Vss. The
output is a De voltage level. To clear the INTR, write a 1 to
the appropriate bites) in the Main Status Register.
DO-D7 (Input/Output): These 8 bidirectional pins connect
to the host tJoP's data bus and are used to read from and
write to the RTe. When the PFAIL pin goes low and a write
is not in progress, these pins are at TRI-STATE.
AO-A4 (Inputs): These 5 pins are for register selection.
They individually control which location is to be accessed.
These inputs are disabled when power failure is detected.
PFAIL (Input): In battery backed mode, this pin can have a
digital signal applied to it via some external power detection
logic. When PFAiL = logic 0 the RTe goes into a lockout
mode, in a minimum of 30 tJos or a maximum of 63 tJos unless
lockout delay is programmed. In the single power supply
mode, this pin is not useable as an input and should be tied
to Vee. Refer to section on Power Fail Functional Descrip.
tion.
OSC IN (Input): OSC OUT (Output): These two pins are
used to connect the crystal to the internal parallel resonant
oscillator. The oscillator is always running when power is
applied to Vssand Vee.
MFO (Output): The multi-function output can be used as a
second interrupt (Power fail) output for interrupting the tJoP.
This pin can also provide an output for the oscillator. The
MFO output is configured as push-pull, active high for normal or single power supply operation and as an open drain
during standby mode (Vss > Vee>. If in battery backed
mode and a pull-up resistor is attached, it should be connected to a voltage no greater than Vss.
Vaa (Battery Power Pin): This pin is connected to a backup power supply. This power supply is switched to the internal circuitry when the Vee becomes lower than Vss. Utilizing this pin eliminates the need for external logic to switch in
and out the back-up power supply. If this feature is not to be
used then this pin must be tied to ground, the RTe programmed for single power supply only, and power applied to
the Vee pin.
Vee: This is the main system power pin.
INTR (Output): The interrupt output is used to interrupt the
processor when a timing event or power fail has occurred
and the respective interrupt· has been enabled. The l'NiFf
output is permanently configured active low, open drain. If in
GND: This is the common ground power pin for both Vss
and Vee.
2-74
Connection Diagrams
Dual-In-Llne
Cs
24
Rii
Plastic Chip Carrier
~ I; I~ I~
Vee
I~ ~
>H
prAlL
D7
D6
D5
D4
D3
A4
D2
V88
Dl
OSC IN
DO
OSC OUT
Al
25
D7
A2
24
DII
A3
23
D5
A4
22
D4
NC
21
D3
NC
10
20
D2
Vaa
11
19
01
12 13 14 15 16 17 18
INTR
GND
a5
wro
lil
0
TL/F/9981-5
t::>
oz
0
0z
I'"
0
.....
~
~
2
(!)
0Q
lil
0
TL/F/9981-6
Top View
Top View
Order Number DP8573AN
See NS Package Number N24C
Order Number DP8573AV
See NS Package Number V28A
Functional Description
The DP8573A contains a fast access real time clock, interrupt control logic, and power fail detect logic. All functions of
the RTC are controlled by a set of seven registers. A simplified block diagram that shows the major functional blocks is
given in Figure 1.
RAW/TEST Register
RAW
Wonths TIm. Sav. RAW
lr
IE
lD
Ie
Day of Wonth TIm. Sav. RAW
Hours TIme Sav. RAW
Wlnut.. TIme Save RAW
lA
S.conds TIme Sav. RAW
19
Day of W"k Compare RAW
18
Wonths Compar. RAM
17
16 Day of Month Compare RAW
Hours Compar. RAW
15
Win utes Compare RAW
14
lB
The blocks are described in the following sections:
1. Real Time Clock
2. Oscillator Prescaler
3. Interrupt Logic
4. Power Failure Logic
5. Additional Supply Management
The memory map of the RTC is shown in the memory addressing table (Figure 2). A control bit in the Main Status
Register is used to select either control register block.
13
Stconds Compare RAW
12
INITIAL POWER-ON of BOTH Vaa and Vee
or
NIA
NIA
NIA
NIl.
Vss and Vee may be applied in any sequence. In order for
the power fail circuitry to function correctly, whenever power
is off, the Vee pin must see a path to ground through a
maximum of 1 MO. The user should be aware that the control registers will contain random data. The user should ensure that the RTC is not in test mode (see register descriptions).
Ot
OD
11
10
oc
OB
01.
09
08
07
REAL TIME CLOCK FUNCTIONAL DESCRIPTION
06
As shown in Figure 2, the clock has 8 bytes of counters,
which count from 1 /1 00 of a second to years. Each counter
counts in BCD and is synchronously clocked. The count sequence of the individual byte counters within the clock is
shown later in Table VII. Note that the day of week, day of
month, and month counters all roll over to 1. The hours
counter in 12 hour mode rolls over to 1 and the AM/PM bit
toggles when the hours rolls over to 12 (AM = 0, PM = 1).
The AM/PM bit is bit 07 in the hours counter.
05
Day of W"k Clock Count.r
DO and Dl Bits Only
RAW
Years Clock Counter
Months Clock Count.r
Day of Wonth Clock Counter
Hours Clock Counter
Minutes Clock Counter
Seconds Clock Counter
V, 00 Stcond Count.r
=
,
R.glster s.lect 0 /
All other counters roll over to O. Upon initial application of
power the counters will contain random information.
Register S.1ect
=1
TIme Save Control R.glst.r
04
Interrupt Control Register 1
P.rIodlc flag Reglst.r
03
NIl.
NIl.
02
Int.rrupt Control R.glst.r 0
Output Wod. Reglst.r
01
R.al TIme Wod. Rlglster
Wain Status Rlglster
TL/F/9981-7
FIGURE 2. DP8573A Internal Memory Map
2-75
•
Functional Description
(Continued)
The above method is useful when the entire clock is being
corrected. If one location is being updated the clock need
not be stopped since this will reset the prescaler, and time
will be lost. An ideal example of this is correcting the hours
for daylight savings time. To write to the clock "on the fly"
the best method is to wait for the 1/100 of a second periodic interrupt. Then wait an additional 16 P.s, and then write
the data to the clock.
READING THE CLOCK: VALIDATED READ
Since clocking of the. counter occurs asynchronously to
reading of the counter, it is possible to read the counter
while it is being incremented (rollover). This may result in an
incorrect time reading. Thus to ensure a correct reading of
the entire contents of the clock (or that part of interest), it
must be read without a clock rollover occurring. In general
this can be done by checking a rollover bit. On this chip the
periodic interrupt status bits can serve this function. The
following program steps can be used to accomplish this.
PRESCALER/OSCILLATOR FUNCTIONAL
DESCRIPTION
1. Initialize program for reading clock.
Feeding the counter chain is a programmable prescaler
which divides the crystal oscillator frequency to 32 kHz and
further to 100 Hz for the counter chain (see Figure 3).
2. Dummy read of periodic status bit to clear it.
3. Read counter bytes and store.
4. Read rollover bit, and test it.
To Real
Tlme
Counters
From
Oscillator
5. If rollover occured go to 3.
6. If no rollover, done.
To detect the rollover, individual periodic status bits can be
polled. The periodic bit chosen should be equal to the highest frequency counter register to be read. That is if only
SECONDS through HOURS counters are read, then the
SECONDS periodic bit should be used.
TLlF/9981-8
FIGURE 3. Programmable Clock Prescaler Block
In addition to the inverter, the oscillator feedback bias resistor is included on chip, as shown in Figure 4. The oscillator
input may be driven from an external source if desired. Refer to test mode application note for details. The oscillator
stability is enhanced through the use of an on chip regulated
power supply.
READING THE CLOCK: INTERRUPT DRIVEN
Enabling the periodic interrupt mask bits cause interrupts
just as the clock rolls over. Enabling the desired update rate
and providing an interrupt service routine that executes in
less than 10 ms enables clock reading without checking for
a rollover.
The typical range of trimmer capacitor (as shown in Oscillator Circuit Diagram Figure 4, and in the typical application) at
the oscillator input pin is suggested only to allow. accurate
tuning of the oscillator. This range is based on a typical
printed circuit board layout and may have to be changed
depending on the parasitic capacitance of the printed circuit
board or fixture being used. In all cases, the load capacitance specified by the crystal manufacturer (nominal value
11 pF for the 32.768 crystal) is what determines proper oscillation. This load capcitance is the series combination of
capacitance on each side of the crystal (with respect to
ground).
READING THE CLOCK: LATCHED READ
Another method to read the clock that does not require
checking the rollover bit is to write a one into the Time Save
Enable bit (07) of the Time Save Control Register, and then
to write a zero. Writing a one into this bit will enable the
clock contents to be duplicated in the Time Save RAM.
Changing the bit from a one to a zero will freeze and store
the contents of the clock in Time Save RAM. The time then
can be read without concern for clock rollover, since internal logic takes care of synchronization of the clock. Because only the bits used by the clock counters will be
latched, the Time Save RAM should be cleared prior to use
to ensure that random data stored in the unused bits do not
confuse the host microprocessor. This bit can also provide
time save at power failure, see the Additional Supply Management Functions section. With the Time Save Enable bit
at a logical 0, the Time Save RAM may be used as RAM if
the latched read function is not necessary.
Internal Components
v+
To
Prescaler
INITIALIZING AND WRITING TO THE
CALENDAR-CLOCK
Upon initial application of power to the TCP or when making
time corrections, the time must be written into the clock. To
correctly write the time to the counters, the clock would
normally be stopped by writing the Start/Stop bit in the Real
Time Mode Register to a zero. This stops the clock from
counting and disables the carry circuitry. When initializing
the clock's Real Time Mode Register, it is recommended
that first the various mode bits be written while maintaining
the Start/stOp bit reset, and then writing to the register a
second time with the Start/Stop bit set.
OSC IN
Pin
.----.-t0t----..
OSC OUT
Pin
XTAL
External
Components
TLlF/9981-9
FIGURE 4. Oscillator Circuit Diagram
2-76
Functional Description
(Continued)
3. Tho Power Fail Interrupt: Issued upon recognition of a
power fail condition by the internal sensing logic. The
power failed condition is determined by the signal on the
PFAIL pin. The internal power fail signal is gated with the
chip select signal to ensure that the power fail interrupt
does not lock the chip out during a read or write.
ROUT
150 kD. to 350 kD.
INTERRUPT LOGIC FUNCTIONAL DESCRIPTION
The RTC has the ability to coordinate processor timing activities. To enhance this, an interrupt structure has been implemented which enables several types of events to cause
interrupts. Interrupts are controlled via two Control Registers in block 1 and two Status Registers in block O. (See
Register Description for notes on paging and Table I.)
ALARM COMPARE INTERRUPT DESCRIPTON
The alarm/time comparison interrupt is a special interrupt
similar to an alarm clock wake up buzzer. This interrupt is
generated when the clock time is equal to a value programmed into the alarm compare registers. Up to six bytes
can be enabled to perform alarm time comparisons on the
counter chain. These six bytes, or some subset thereof,
would be loaded with the future time at which the interrupt
will occur. Next, the appropriate bits in the Interrupt Control
Register 1 are enabled or disabled (refer to detailed description of Interrupt Control Register 1). The RTC then compares these bytes with the clock time. When all the enabled
compare registers equal the clock time an alarm interrupt is
issued, but only if the alarm compare interrupt is enabled
can the interrupt be generated externally. Each alarm compare bit in the Control Register will enable a specific byte for
comparison to the clock. Disabling a compare byte is the
same as setting its associated counter comparator to an
"always equal" state. For example, to generate an interrupt
at 3:15 AM of every day, load the hours compare with 0 3
(BCD), the minutes compare with 1 5 (BCD) and the faster
counters with 0 0 (BCD), and then disable all other compare
registers. So every day when the time rolls over from
3:14:59.99, an interrupt is issued. This bit may be reset by
writing a one to bit 03 in the Main Status Register at any
time after the alarm has been generated.
If time comparison for an individual byte counter is disabled,
that corresponding RAM location can then be use~ as general purpose storage.
The interrupts are enabled by writing a one to the appropriate bits in Interrupt Control Register 0 and/or 1.
TABLE I. Registers 'that are Applicable
to Interrupt Control
Register Name
Register
Select
Address
Main Status Register
Periodic Flag Register
Interrupt Control Register 0
Interrupt Control Register 1
Output Mode Register
X
0
1
1
1
OOH
03H
03H
04H
02H
The Interrupt Status Flag DO, in the Main Status Register,
indicates the state of INTR and MFO outputs. It is set when
either output becomes active and is cleared when all RTC
interrupts have been cleared and no further interrupts are
pending (Le., both INTR and MFO are returned to their inactive state). This flag enables the RTC to be rapidly polled by
the J-lP to defermine the source of an interrupt in a wiredOR interrupt system. (The Interrupt Status Flag provides a
true reflection of all conditions routed to the external pins.)
Status for the interrupts are provided by the Main Status
Register and the Periodic Flag Register. Bits 01-05 of the
Main Status Register are the main interrupt bits.
. PERIODIC INTERRUPTS DESCRIPTION
The Periodic Flag Register contains six flags which are set
by real-time generated "ticks" at various time intervals, see
Figure S. These flags constantly sense the periodic signals
and may be used whether or not interrupts are enabled.
These flags are cleared by any read or write operation performed on this register.
To generate periodic interrupts at the desired rate, the associated Periodic Interrupt Enable bit in Interrupt Control Register 0 must be set. Any combination of periodic interrupts
may be enabled to operate simultaneously. Enabled periodic interrupts will now affect the Periodic Interrupt Flag in the
Main Status Register.
When a periodic event occurs, the Periodic Interrupt Flag in
the Main Status Register is set, causing an interrupt to be
generated. The J-lP clears both flag and interrupt by wrlting a
"1" to the Periodic Interrupt Flag. The individual flags in the'
periodic Interrupt Flag Register do not require clearing to
cancel the interrupt.
These register bits will be set when their associated timing
events occur. Enabled Alarm comparisons that occur will
set its Main Status Register bit to a one. However, an external interrupt will only be generated if the Alarm interrupt
enable bit is set (see Figure S).
Disabling the periodic interrupts will mask the Main Status
Register periodic bit, but not the Periodic Flag Register bits.
The Power Fail Interrupt bit is set when the interrupt is enabled and a power fail event has occurred, and is not reset
until the power is restored. If all interrupt enable bits are 0
no interrupt will be asserted. However, status still can be
read from the Main Status Register in a polled fashion (see
FigureS).
To clear a flag in bits 02 and 03 of the Main Status Register
a 1 must be written back into the bit location that is to be
cleared. For the Periodic Flag Register reading the status
will reset all the periodic flags.
Interrupts Fall Into Three Categories:
If all periodic interrupts are disabled and a periodic interrupt
is left pending (Le., the Periodic Interrupt Flag is still set), the
Periodic Interrupt Flag will still be required to be cleared to
cancel the pending interrupt.
1. The Alarm Compare Interrupt: Issued when the value in
the time compared RAM equals the counter.
2. The Periodic Interrupts: These are issued at every increment of the specific clock counter signal. Thus, an interrupt is issued every minute, second, etc. Each of these
interrupts occurs at the roll-over of the specific counter.
2-77
DP8573A
"
C
:J
...n
S·
:J
Interrupt Control Registers
Real
Time
Periodic
Pulse
Signals
(also to
Periodic
Flags)
Main Status
Register
e.
Interrrupt Control
Register
11-11-
C
CD
Output Mode
i
Power
Fail
Detect
3-
I.4FO
Signal
:r
r::
MFO Output
MUX
(I)
--+
.s
Output
Buffer
Interrupt
Mode
Selected
}. E~~~~e:~.:·,: .:;
:\.::.::::::::::.))~.:(:~i
,:.~ ':p~'w~;' 'fai"': :":
~ :".lnterrupt••:.: ::.
g>
!
r.
:~
-6.
:J
:~:?r~~:~:li:~::~t.:~;
Alarm
Compare
Signals
...
S·
~~~~~~r
Bit
•• ·.lnterrupL·. .,
.!.J
Q)
...
n
I
Buffered °lSCiliator
,::~ .•::~. Aiar~ ':":": ::.:!
I\)
en
::
I
WfdBiKJiiij
,'..••.. Status ••... r.:.:
: : : .::.\.:... ~!~..:..:~.::.:: {:
INTR Output
Output
Buffer
,::.::.\.:.):.::.::~.::(.::./
TL/F/9981-10
FIGURE 5. Interrupt Control Logic Overview
C
Functional Description
."
Q)
(Continued)
c.n
POWER FAIL INTERRUPTS DESCRIPTION
disconnected, and the device is now in the standby mode. If
indeterminate operation of the battery switch over circuit is
to be avoided, then the voltage at the Vee pin must not be
allowed to equal the voltage at the Vss pin.
The Power Fail Status Flag in the Main Status Register
monitors the state of the internal power fail signal. This flag
may be interrogated by the I-1P, but it cannot be cleared; it is
cleared automatically by the RTC when system power is
restored. To generate an interrupt when the power fails, the
Power Fail Interrupt Enable bit in Interrupt Control Register
1 is set. Although this interrupt may not be cleared, it may
be masked by clearing the Power Fail Interrupt Enable bit.
.....
w
:I>
After the generation of a lock-out Signal, and eventual
switch in of the battery supply, the pins of the RTC will be
configured as shown in Table II. Outputs that have a pull-up
resistor should be connected to a voltage no greater than
Vss·
POWER FAILURE CIRCUITRY FUNCTIONAL
DESCRIPTION
TABLE II. Pin Isolation during a Power Failure
Since the clock must be operated from a battery when the
main system supply has been turned off, the DP8573A provides circuitry to simplify design in battery backed systems.
This switches over to the back up supply, and isolates itself
from the host system. Figure 6 shows a simplified block
diagram of this circuitry, which consists of three major sections; 1) power loss logic: 2) battery switch over logic: and 3)
isolation logic.
Detection of power loss occurs when PFAIL is low. Debounce logic provides a 30 I-1s-63 I-1s debounce time, which
will prevent noise on the PFAIL pin from being interpreted
as a system failure. After 30 I-1s-63 I-1s the debounce logic
times out and a signal is generated indicating that system
power is marginal and is failing. The Power Fail Interrupt will
then be generated.
Pin
PFAIL =
Logic 0
CS,RD,WR
AO-A4
00-07
Oscillator
PFAIL
INTR,MFO
Locked Out
Locked Out
Locked Out
Not Isolated
Not Isolated
Not Isolated
Standby Mode
Vee> Vee
Locked Out
Locked Out
Locked Out
Not Isolated
Not Isolated
Open Drain
The Interrupt Power Fail Operation bit in the Real-Time
Mode Register determines whether or not the interrupts will
continue to function after a power fail event.
As power returns to the system, the battery switch over circuit will switch back to Vee power as soon as it becomes
greater than the battery voltage. The chip will remain in the
locked out state as long as PFAI L = O. When PFAI L = 1 the
chip is unlocked, but only after another 30 I-1s min ---+63
I-1s max debounce time. The system designer must ensure
that his system is stable when power has returned.
If chip select is low when a power failure is detected, a
safety circuit will ensure that if a read or write is held active
continuously for greater than 30 I-1s after the power fail signal is asserted, the lock-out will be forced.
The battery switch over circuitry is completely independent
of the PFAIL pin. A separate circuit compares Vee to the
Vss voltage. As the main supply fails, the RTC will continue
to operate from the Vee pin until Vee falls below the Vss
voltage. At this time, the battery supply is switched in, Vee is
The power fail circuitry contains active linear Circuitry that
draws supply current from Vee. In some cases this may be
undesirable, so this circuit can be disabled by masking the
power fail interrupt. The power fail input can perform all
lock-out functions previously mentioned, except that no ex-
Battery Switchover
VBB
Vee
~
prAlL:;'
(External
power fail
signal)
v+
•
30 uS
Delay
Power
Fail Logic
I 30-63 uS I
Delayed
Lockout
I Debounce
I
Delay
... 8, ..
Data
Address
and
Control
Buffers
'"
, "'00:07
5,
I
fII
AO:A4
3,
'es,RD,ViR
TL/F/9981-11
FIGURE 6. System-Battery Swltchover (Upper Left), Power Fall
and Lock-Out Circuits (Lower Right)
2-79
Functional Description
(Continued)
ternal interrupt will be issued. Note that the linear power fail
circuitry is switched off automatically when using Vss in
standby mode.
TABLE III. Register/Counter/RAM
Addressing for DP8573A
RS
AO-4 (Note 1)
INITIAL POWER ON DETECT AND
POWER FAIL TIME SAVE
Description
CONTROL REGISTERS
There are two other functions provided on the DP8573A to
ease power supply control. These are an initial Power On
detect circuit, which also can be used as a time keeping
failure detect, and a time save on power failure.
00
01
02
03
04
01
02
03
04
On initial power up the Oscillator Fail Flag will be set to a
one and the real time clock start bit reset to a zero. This
indicates that an oscillator fail event has occurred, and time
keeping has failed.
The Oscillator Fail flag will not be reset until the real-time
clock is started. This allows the system to discriminate between an initial power-up and recovery from a power failure.
If the battery backed mode is selected, then bit 06 of the
Periodic Flag Register must be written low. This will not affect the contents of the Oscillator Fail Flag.
X
0
0
0
0
1
1
1
1
Main Status Register
N/A
N/A
Periodic Flag Register
Time Save Control Register
Real Time Mode Register
Output Mode Register
Interrupt Control Register 0
Interrupt Control Register 1
COUNTERS (CLOCK CALENDAR)
To relieve CPU overhead for saving time upon power failure,
the Time Save Enable bit is provided to do this automatically. (See also Reading the Clock: Latched Read.) The Time
Save Enable bit, when set, causes the Time Save RAM to
follow the contents of the clock. This bit can be reset by
software, but if set before a power failure occurs, it will automatically be reset when the clock switches to the battery
supply (not when a power failure is detected by the PFAIL
pin). Thus, writing a one to the Time Save bit enables both a
software write or power fail write.
SINGLE POWER SUPPLY APPLICATIONS
The DP8573A can be used in a single power supply application. To achieve this, the Vss pin must be connected to
ground, and the power connected to Vee. The Oscillator
Failed/Single Supply bit in the Periodic Flag Register should
be set to a logic 1, which will disable the oscillator battery
reference circuit. The power fail interrupt should also be disabled. This will turn off the linear power fail detection circuits, and will eliminate any quiescent power drawn through
these circuits.
05
06
07
08
09
OA
08
OC
00
OE
X
X
X
X
X
X
X
X
X
X
1/100,1/10 Seconds
Seconds
Minutes
Hours
Days of Month
Months
Years
RAM
DO, 01 bits only
Day of Week
OF
10
11
12
X
X
X
X
N/A
N/A
N/A
N/A
(0-99)
(0-59)
(0-59)
(1-12, 0-23)
(1-28/29/30/31 )
(1-12)
(0-99)
(1-7)
TIME COMPARE RAM
13
14
15
16
17
18
DETAILED REGISTER DESCRIPTION
There are 5 external address bits: Thus, the host microprocessor has access to 28 locations at one time. An internal
switching scheme provides a total of 30 locations.
X
X
X
X
X
X
Sec Compare RAM
Min Compare RAM
Hours Compare RAM
DOM Compare RAM
Months Compare RAM
DOW Compare RAM
(0-59)
(0-59)
(1-12,0-23)
(1-28/29/30/31)
(1-12)
(1-7)
TIME SAVE RAM
10
X
X
X
X
X
Seconds Time Save RAM
Minutes Time Save RAM
Hours Time Save RAM
Day of Month Time Save RAM
Months Time Save RAM
1E
1F
1
X
RAM
RAMITest Mode Register
19
1A
18
1C
The only register that does not get switched is the Main
Status Register. It contains the register select bit as well as
status information.
A memory map is shown in Figure 2 and register addressing
in Table III. They show the name, address and page locations for the DP8573A.
Note 1: RS-Register Select (Bit D6 of Main Status Register)
2-80
Functional Description
(Continued)
backod modo. Bit 06 is automatically sot to 1 on initial power-up or an oscillator fail event. The oscillator fail flag is
reset by writing a one to the clock start/stop bit in the Real
Time Mode Register, with the crystal oscillating.
MAIN STATUS REGISTER
DO Interrupt Status
01 Power rell Interrupt
When 06 is written to, it defines whether the TCP is being
used in battery backed (normal) or in a single supply mode
application. When set to a one this bit configures the TCP
for single power supply applications. This bit is automatically
set on initial power-up or an oscillator fail event. When set,
06 disables the oscillator reference circuit. The result is that
the OSCillator is referenced to Vee. When a zero is written to
06 the oscillator reference is enabled, thus the oscillator is
referenced to Vss. This allows operation in standard battery
standby applications.
02 Period Interrupt
' - - - - - - 0 3 Alarm Interrupt
' - - - - - - - 0 4 RAhA
1 . - - - - - - - 0 5 RAhA
1 . - - - - - - - - 0 6 Register Select Bit
1.-_ _ _ _ _ _ _ _ _ 07 RAhA
TLIF/9981-12
The Main Status Register is always located at address 0
regardless of the register block selected.
DO: This read only bit is a general interrupt status bit that is
taken directly from the interrupt pins. The bit is a one when
an interrupt is pending on either the INTR pin or the MFa
pin (when configured as an interrupt). This is unlike 03
which can be set by an internal event but may not cause an
interrupt. This bit is reset when the interrupt status bits in the
Main Status Register are cleared.
At initial power on, if the OP8573A is going to be programmed for battery backed mode, the Vss pin should be
connected to a potential in the range of 2.2V to Vee O.4V.
For single supply modo operation, the VSB pin should be
connected to GNO and the PFAIL pin connected to Vee.
07: Writing a one to this bit enables the test mode register
at location 1 F (see Table III). This bit should be forced to
zero during initialization for normal operation. If the test
mode has been entered, clear the test mode register before
leaving test mode. (See separate test mode application
note for further details.)
01-03: These three bits of the Main Status Register are the
main interrupt status bits. Any bit may be a one when any of
the interrupts are pending. Once an interrupt is asserted the
p.P will read this register to determine the cause. These
interrupt status bits are not reset when read. Except for 01,
to reset an interrupt a one is written back to the corresponding bit that is being tested. 01 is reset whenever the PFAIL
pin = logic 1. This prevents loss of interrupt status when
reading the register in a polled mode. 01 and 03 are set
regardless of whether these interrupts are masked or not by
bits 06 and 07 of Interrupt Control Registers 0 and 1.
TIME SAVE CONTROL REGISTER
TS
N A
R
R
DO RAhA
01 RAM
02 RAM
04, 05 and 07: General purpose RAM bits.
1 . . - - - - - 0 3 RAM
06: Bit 06 controls the register block to be accessed (see
memory map).
1 . - - - - - - 0 4 RAM
1 . - - - - - - - 0 5 RAM
PERIODIC FLAG REGISTER
TU
L . . - - - - - - - - - 0 6 N/A
1..-_ _ _ _ _ _ _ _ _ 07 TIme Save Enable
osr 11m, 10m, 100mST Is Tl0,Tl min]
I
L=
DO minutes flag
TL/F/9981-14
01 10 second flag
00-05: General purpose RAM bits.
02 seconds flag
06: Not Available, appears as logic 0 when read.
03 100 millisec. flag
07: Time Save Enable bit controls the loading of real-timeclock data into the Time Save RAM. When a one is written
to this bit the Time Save RAM will follow the corresponding
clock registers, and when a zero is written to this bit the time
in the Time Save RAM is frozen. This eliminates any synchronization problems when reading the clock, thus negating the need to check for a counter rollover during a read
cycle.
04 10 millisec. flag
05 milll-seconds flag
06 Oscillator railed/Single Supply Bit
07 Test hAode Enable
TLIF/9981-13
The Periodic Flag Register has. the same bit for bit correspondence as Interrupt Control Register 0 except for 06
and 07. For normal operation (Le., not a single supply application) this register must be written to on initial power up or
after an oscillator fail event. 00-05 are read only bits, 06
and 07 are read/write.
This bit must be set to a one prior to power failing to enable
the Time Save feature. When the power fails this bit is automatically reset and the time is saved in the Time Save RAM.
REAL TIME MOOE REGISTER
00-05: These bits are set by the real time rollover events:
(Time Change = 1). The bits are reset when the register is
read and can be used as selective data change flags.
DO Leap Year LSB
06: This bit performs a dual function. When this bit is read, a
one indicates that an oscillator failure has occurred and the
time information may have been lost. Some of the ways an
oscillator failure might be caused are: failure of the crystal,
shorting OSC IN or OSC OUT to GNO or Vee, removal of
crystal, removal of battery when in the battery backed mode
(when a "0" is written to 06), lowering the voltage at the
Vss pin to a value less than 2.2V when in the battery
01 Leap Year MSB
02 12/24 hour mode
L . . - - - - - - 0 3 Clock Start/Stop
1 . - - - - - - 0 4 Interrupt pr Operation
1 . - - - - - - - 0 5 RAM
L . . - - - - - - - - - 0 6 RAM
L..-_ _ _ _ _ _ _ _ _ 07 RAM
TL/F/9981-15
2-81
Functional Description (Continued)
00-01: These are the leap year counter bits. These bits are
written to set the number of years from the previous leap
year. The leap year counter increments on December 31st
and it internally enables the February 29th counter state.
This method of setting the leap year allows leap year to
occur whenever the user wishes to, thus providing flexibility
in implementing Japanese leap year function.
INTERRUPT CONTROL REGISTER 0
DO Minutes enable
, 01 10 second enable
' - - - - 0 2 Seconds enable
L.-_ _ _ _ 03 100 mlllisec enable
L . - - - - - - 0 4 10 mlilisec enable
LY1
LYO
Leap Year
Counter
0
0
1
1
0
1
0
1
Leap Year Current Year
Leap Year Last Year
. Leap Year 2 Years Ago
Leap Year 3 Years Ago
L . - - - - - - - 0 5 mlilisec enable
~---------06 RAM
' -_ _ _ _ _ _ _ _ _ 07 RAM
TL/F/9981-17
00-05: These bits are used to enable one of the selected
periodic interrupts by writing a one into the appropriate bit.
These interrupts are issued at the rollover of the clock. For
example, the minutes interrupt will be issued whenever the
minutes counter increments. In all likelihood the interrupt
will be enabled asynchronously with the real time change.
Therefore, the very first interrupt will occur in less than the
periodic time chosen, but after the first interrupt all subsequent interrupts will be spaced correctly. These interrupts
are useful when minute, second, real time reading, or task
switching is required. When all six bits are written to a 0 this
disables periodic interrupts from the Main Status Register
and the interrupt pin. If battery backed mode is selected and
the DP8573A is in standby (Vee> Vec), then these bits are
controlled by D4 of the Real Time Mode Register.
06 and 07: General purpose RAM.
02: The count mode for the hours counter can be set to
either 24 hour mode or 12 hour mode with AM/PM indicator.
A one will place the clock in 12 hour mode.
03: This bit is the master Start/stOP bit for the clock. When
a one is written to this bit the real time counter's prescaler
and counter chain are enabled. When this bit is reset to zero
the contents of the real time counter is stopped. When the
RTC is initially powered up this bit will be held at a logic 0
until the oscillator starts functioning correctly after which
this bit may be modified. If an oscillator fail event occurs,
this bit will be reset to logic O.
04: This bit controls the operation of the interrupt output in
standby mode. If set to a one it allows Alarm, Periodic, and
Power Fail interrupts to be functional in standby mode. Note
that the MFO pin is configured as open drain in standby
mode.
INTERRUPT CONTROL REGISTER 1
DO Second compare enable
If bit 04 is set to a zero then bits OO-D5 of Interrupt Control
Register 0 and bits D6 and D7 of Interrupt Control Register
1 will be reset when the RTC enters the standby mode.
They will have to be re-configured when system (Vee) power is restored.
01 Minute compare enable
......---02 Hour compare enable
.....- - - - 0 3 Day of month enable
' - - - - - - 0 4 Month compare enable
05-07: General purpose RAM bits.
L . - - - - - - - 0 5 Day of week enable
OUTPUT MOOE REGISTER
I~IRIRIRIRI
.....- - - - - - - - - 0 6 Alarm Interrupt enable
....._ _ _ _ _ _ _ _ _ 07 Power fall Interrupt enable
RI RIRI
IL:
DO RAM
TL/F/9981-18
01 RAM
00-05: Each of these bits are enable bits which will enable
a comparison between an individual clock counter and its
associated compare RAM. If any bit is a zero then that
clock-RAM comparator is set to the "always equal" state
and the associated TIME COMPARE RAM byte can be used
as general purpose RAM. However, to ensure that an alarm
interrupt is not generated at bit D3 of the Main Status Register, all bits must be written to a logic zero.
02 RAM
03 RAM
04 RAM
05 RAM
06 RAM
07 MFO Pin as Oscillator
06: In order to generate an external alarm compare interrupt to the J.LP from bit D3 of the Main Status Register, this
bit must be written to a logic 1. If battery backed mode is
selected and the DP8573A is in standby (Vee> Vec), then
this bit is controlled by D4 of the Real Time Mode Register.
TL/F/9981-16
00-06: General purpose RAM bits.
07: This bit is used to program the signal appearing at the
MFO output, as follows:
07
MFO Output Signal
0
1
Power Fail Interrupt
Buffered Crystal Oscillator
07: The MSB of this register is the enable bit for the Power
Fail Interrupt. When this bit is set to a one an interrupt will
be generated to the J.LP when Vee> Vee. If battery backed
mode is selected and the DP8573A is in standby (Vee >
Vec), then this bit is controlled by D4 of the Real Time
Mode Register.
2-82
Control and Status Register Address Bit Map
07
06
Main Status Register PS = X
R/W
R/W
05
04
03
RS = X ADDRESS = OOH
R/W
R/W
R/W1
02
01
00
1. Reset by
writing
1 to bit.
R/W1
2. Set/reset by
voltage at
PFAILpin.
3. Reset when
all pending
interrupts
are removed.
Periodic Flag Register PS = 0
R/W
RS = 0
RS
R/W4
RS
Address = 03H
RS
4. Read Osc fail
Write 0 BattBacked Mode
Write 1 Single
Supply Mode
5. Reset by
positive edge
of read.
All Bits R/W
All BitsR/W
L-1_~.....;~:-~_t:_~_I1-_R_A_M_--LI
__R_A_M_--L__R_A_M_--L__R_A_M_--L__R_A_M_--L__R_A_M_--L__R_A_M_--11 All Bits R/W
Interrupt Control Register 0 PS = 0
RAM
RAM
1 ms
Interrupt
Enable
Interrupt Control Register 1 PS = 0
Power Fail
Interrupt
Enable
Address = 02H
RS = 1
Output Mode Register PS = 0
Alarm
Interrupt
Enable
DOW
Interrupt
Enable
RS = 1
Address = 03H
10ms
Interrupt
Enable
RS = 1
100 ms
Interrupt
Enable
Seconds
Interrupt
Enable
10 Second
Interrupt
Enable
Minute
Interrupt
Enable
All Bits R/W
Minute
Interrupt
Enable
Second
Interrupt
Enable
All BitsR/W
Address = 04H
Month
Interrupt
Enable
DaM
Interrupt
Enable
Hours
Interrupt
Enable
Application Hints
Suggested Initialization Procedure for OP8573A in Battery Backed Applications that use the Vee Pin
4. Enter
~
software loop that does the following:
Set a 3 second(approx) software counter. The crystal
oscillator may take 1 second to start.
1. Enter the test mode by writing a 1 to bit 07 in the Periodic Flag Register.
4.1 Write a 1 to bit 03 in the Real Time Mode Register (try
to start the clock). Under normal operation, this bit can
be set only if the oscillator is running. During the software loop, RAM, real time counters, output configuration, interrupt control and timer functions may be initialized.
2. Write zero to the RAM/TEST mode Register located in
page 0, address HEX 1F.
3. Leave the test mode by writing a 0 to bit 07 in the Periodic Flag Register. Steps 1, 2, 3 guarantee that if the
test mode had been entered during power on (due to
random pulses from the system), all test mode conditions are cleared. Most important is that the OSC Fail
Disable bit is cleared. Refer to AN-589 for more information on test mode operation.
2-83
~r----------------------------------------------------------------C")
an
.....
Application Hints (Continued)
CQ
£L
5. Test bit 06 in the Periodic Flag Register:
C
The only method to ensure the chip is in the battery
backed mode is to measure the waveform at the OSC
OUT pin. If the battery backed mode was selected successfully, then the peak to peak waveform at OSC OUT
is referenced to the battery voltage. If not in battery
backed mode, the waveform is referenced to Vee. The
measurement should be made with a high impedance
low capacitance probe (10 MO, 10 pF oscilloscope
probe or better). Typical peak to peak swings are within
O.6V of Vee and ground respectively.
IF 81, go to 4.1. If this bit remains a 1 after 3 seconds,
then abort and check hardware. The crystal may be de~
fective or not installed. There may be a short at OSC IN
or OSCOUT to Vee or GNO, or to some impedance that
is less than 10 MO.
.
IF 8 0, then the oscillator is running, go to step 7.
6. Write a 0 to bit 06 in the Periodic Flag Register. This
action puts the clock chip in the battery backed mode.
This mode can be entered only if the OSC fail flag (bit
06 of the Periodic Flag Register) is a o. Reminder, bit 06
is a dual function bit. When read, 06 returns oscillator
status. When written, D6 causes either the Battery
Backed Mode, or the Single Supply Mode of operation.
Typical Application
-
..-
r--
7. Write a 1 to bit 07 of Interrupt Control Register 1. This
action enables the PFAIL pin and associated circuitry.
8. Write a 1 to bit D4 of the Real Time Mode Register. This
action ensures that bit 07 of Interrupt Control Register 1
remains a 1 when Vss > Vee (Standby Mode).
9. Initialize the rest of the chip as needed.
T
,.....--
~
:l ..
.
~~
."
."
~
u
Vaa
T
cs
...:'"
PFAIL
0
(I)
(I)
(J)
0
0
L.
a..
"'"""-
...
IA
L.
AO-A4
"
...
A
'4
Y
'4
"
...
.A
0
~
AO-A4
,DP8573A
Real Time
Clock
OSC IN
Data Bus
00-07
L.
.~
...
IA
Adc ress Bus
'4
IA..
.J...
l'f
-y
'4
00-07
OSC OUT
... RD
.A
RO WR, INT
"
A low going user
generated po wer
filii signlll sh ould
be presented to the
PFAIL pin.
1. ~2-2
T
c::::::I
"
Control
'4
~
I~
I
Vee
Battery Supply
.....
t.lain Supply
2 pF
32.768KH
T
47 PF
WR
INTR
~ t.lFO
GNO
--
-
!
I...
TLIF/9981-19
'These components may be necessary to meet UL requirements
for lithium batteries. Consult battery manufacturer.
2-84
Typical Performance Characteristics
Operating Current V8
Supply Voltage
(Single Supply Mode
Fosc
=
Operating Current V8
Supply Voltage
(Battery Backed Mode
32.768 kHz)
160
J
/
1400 Fosc
I
120
= 32.768 kHz)
~
JJ
I
1000
3.0
.c.o
5.0
= 32.768 kHz)
/~
12
J.
800
/
/
/
/
--'
/
600
2.0
(Fosc
/
1200
/
Standby Current vs Power
Supply Voltage
:z.o
6.0
2.5
3.0
15
.c.o
.ci
VSB(VoIts)
Vcc(VoItt)
. TL/F/9981-22
TL/F/9981-20
TUF/9981-21
2-85
~National
U
Semiconductor
MM58274C-12
Microprocessor Compatible Real Time Clock
General Description
Features
The MM58274C-12 is fabricated using low threshold metal
gate CMOS technology and is designed to operate in bus
oriented microprocessor systems where a real time clock
and calendar function are required. The on-chip 32.768 kHz
crystal controlled oscillator will maintain timekeeping down
to 2.2V to allow low power standby battery operation. This
device is pin compatible with the MM58174A but continues
timekeeping ~p to tens of years.
• Same pin-out as MM58174A, MM58274B, MM58274C,
and MM58274
• Timekeeping from tenths of seconds to tens of years in
independently accessible registers
• Leap year register
• 12 hour operation only
• Buffered crystal frequency output in test mode for easy
oscillator setting
• Data-changed flag allows simple testing for time
rollover
• Independent interrupting time with open drain output
• Fully TTL compatible
• Low power standby operation (10 IlA at 2.2V)
• Low cost 16-pin DIP and 20-pin PCC
Applications
•
•
•
•
•
Point of sale terminals
Teller terminals
Word processors
Data logging
Industrial process control
Block Diagram
TL/F/S602-1
FIGURE 1
2-86
Absolute Maximum Ratings
Operating Conditions
(Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
DC Input or Output Voltage
DC Input or Output Diode Current .
-0.3V to Voo + 0.3V
±5.0mA
Storage Temperature, TSTG
Supply Voltage, Voo
- 65'C to
Max
5.5
5.5
Voo
85
Units
V
V
V
°C
+ 150'C
6.5V
Power Dissipation, Po
Lead Temperature
(Soldering, 10 seconds)
500mW
260·
Electrical Characteristics Voo =5V ±10%, T =
Symbol
Min
4.5
2.2
0
-40
Operating Supply Voltage
Standby Mode Supply Voltage
DC Input or Output Voltage
Operating Temperature Range
Parameter
-40·Cto +85°Cunlessotherwisestated.
Conditions
Min
Typ
Max
Units
VIH
High Level Input
Voltage (except
XTAL IN)
VIL
Low Level Input
Voltage (except
XTALIN)
VOH
High Level Output
Voltage (080-083)
IOH = -20/-LA
IOH = -1.6 mA
Voo - 0.1
3.7
V
V
VOH
High Level Output
Voltage (INT)
IOH = -20/-LA
(In Test Mode)
Voo - 0.1
V
VOL
Low Level Output
Voltage (080-083,
INn
IOL = 20/-LA
iOL = 1~6 rnA
IlL
Low Level Input Current
(AOO-A03, 080-083)
VIN = Vss (Note 2)
IlL
Low Level Input Current
(WR,RO)
Low Level Input Current
IlL
V
2.0
0.8
V
0.1
0.4
V
V
-5
-80
/-LA
VIN = Vss (Note 2)
-5
-190
/-LA
VIN = Vss (Note 2)
-5
-550
/-LA
2.0
/-LA
4
10
1
/-LA
mA
5
10
pF
(CS)
IOZH
100·
CIN
COUT
Ouput High Level
Leakage Current (INn
VOUT = Voo
Average Supply Current
All VIN = Vee or Open Circuit
Voo = 2.2V (Standby Mode)
Voo = 5.0V (Active Mode)
Input Capacitance
Output Capacitance
(Outputs Disabled)
10
pF
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur. All voltages referenced to ground unless otherwise noted.
Note 2: The DBO-DB3 and ADO-AD3 lines all have active P-channel pull-up transistors which will source current. The ~, RI5, and WR lines have internal pull-up
resistors to Voo.
2-87
AC Switching Characteristics
READ TIMING: DATA FROM PERIPHERAL TO MICROPROCESSOR Voo
Symbol
= 5V ±0.5V, CL = 100 pF
Commercial
Specification
Parameter
TA
=
Min
Units
-40·Cto +85·C
Typ
Max
tAD
Address Bus Valid to Data Valid
390
650
ns
tcso
Chip Select On to Data Valid
140
300
ns
tRO
Read Strobe On to Data Valid
140
300
ns
tRw
Read Strobe Width (Note 3, Note 7)
tRA
Address Bus Hold Time from Trailing Edge
of Read Strobe
0
ns
tCSH
Chip Select Hold Time from Trailing Edge
of Read Strobe
0
ns
tRH
Data Hold Time from Trailing Edge
of Read Strobe
70
tHZ
Time from Trailing Edge of Read Strobe
Until alP Drivers are TRI-STATE®
DC
ns
250
WRITE TIMING: DATA FROM MICROPROCESSOR TO PERIPHERAL Voo
Symbol
160
= 5V
±0.5V
Commercial
Specification
Parameter
TA
ns
=
Units
-40·C to +85·C
Min
Typ
tAW
Address Bus Valid to Write Strobe -'"
(Note 4, Note 6)
400
125
ns
tcsw
Chip Select On to Write Strobe -'"
250
100
ns
tow
Data Bus Valid to Write Strobe -'"
400
220
ns
tww
Write Strobe Width (Note 6)
250
95
ns
twcs
Chip Select Hold Time Following
Write Strobe -'"
0
ns
tWA
Address Bus Hold Time Following
Write Strobe .-r
0
ns
two
Data Bus Hold Time Following
Write Strobe .-r
100
35
Max
ns
Address Bus Valid Before
70
20
ns
Start of Write Strobe
Note 3: Except for special case restriction: with interrupts programmed, max read strobe width of control register (ADDR 0) is 30 ms. See section on Interrupt
Programming.
Note 4: All timings measured to the trailing edge of write strobe (data latched by the trailing edge of \Wi).
Note 5: Input test waveform peak voltages are 2.4V and 0.4V. Output Signals are measured to their 2.4V and O.4V levels.
Note 6: Write strobe as used in the Write Timing Table is defined as the period when both chip select and write Inputs are low, ie., WS, = ~ + \Wi. Hence write
strobe commences when both Signals are low, and terminates when the first signal returns high.
Note 7: Read strobe as used in the Read Timing Table is defined as the period when both chip select and read inputs are low, ie., ~ = ~ + lm.
Note 8: Typical numbers are at Vee = 5.0V and TA = 25°C.
tAWS
2-88
Switching Time Waveforms
Read Cycle Timing (Notes 5 and 7)
,.----------------~ , . - - - 2 . 4 V
ADDRESS VALID
A3-AD
r------------------'i
'---t----tcsD----l
D.4V
2.4V
11-_ _ _ _ _ _
2.4V
- - - - + - - - + - - - - - - D.4V
03-00
---+-----------<1
TL/F/5602-3
Write Cycle Timing (Notes 5 and 6)
, . - - - - - - - - - - - - - - - - - - , . ~--- 2.4V
ADDRESS VALID
A3-AD
r------------------'I
"---I - - - - - - t c s w - - - - -.....-
D.4V
2.4V
1----lAws---~--
I---tow---i03-00
--+------(1
DATA VALID
TL/F/5602-4
Connection Diagrams
PCC Package
Dual·ln·Line Package
::!!:
cs
VDD
iiii
XTAL IN
\Vii
XTAL OUT
DB3
iNf
DB2
ADO
DBl
ADl
DBO
AD2
Vss
AD3
I~ I~ I~
.}
~
N/C
XTAL OUT
N/C
(NT
DB3
N/C
DB2
ADO
N/C
ADl
TL/F/5602-13
Top View
Top View
TL/F/5602-2
FIGURE 2
Order Number MM58274CJ·12, MM58274CN·12 or MM58274CV·12
See NS Package J16A, N16A, or V20A
2-89
Functional Description
The MM58274C-12 is a bus oriented microprocessor real
time clock. It has the same pin-out as the MM58174A while
offering extended timekeeping up to units and tens of years.
To enhance the device further, a number of other features
have been added including: 12 hour counting, a testable
data-changed flag giving easy error-free time reading and
simplified interrupt control.
CIRCUIT DESCRIPTION
The block diagram in Figure 1 shows the internal structure
of the chip. The 16-pin package outline is shown in Figure 2.
Crystal Oscillator
This consists of a CMOS inverter/amplifier with an on-chip
bias resistor. Externally a 20 pF capacitor, a 6 pF-36 pF
trimmer capacitor and a crystal are suggested to complete
the 32.768 kHz timekeeping oscillator circuit.
The 6 pF-36 pF trimmer fine tunes the crystal load impedance, optimizing the oscillator stability. When properly adjusted (i.e., to the crystal frequency of 32.768 kHz), the circuit will display a frequency variation with voltage of less
than 3 ppmlV. When an external oscillator is used, connect
to oscillator input and float (no connection) the oscillator
output.
When the chip is. enabled into test mode, the oscillator is
gated onto the interrupt output pin giving a buffered oscillator output that can be used to set the crystal frequency
when the device is installed in a system. For further information see the section on Test Mode.
A buffered oscillator signal appears on the interrupt output
when the device is in test mode. This allows for easy oscillator setting when the device is initially powered up in a system.
The counters are arranged as 4-bit words and can be randomly accessed for time reading and setting. The counters
output in BCD (binary coded decimal) 4-bit numbers. Any
register which has less than 4 bits (e.g., days of week uses
only 3 bits) will return a logic 0 on any unused bits. When
written to, the unused inputs will be ignored.
Writing a logic 1 to the clock start/stop control bit resets the
internal oscillator divider chain and the tenths of seconds
counter. Writing a logic 0 will start the clock timing from the
nearest second. The time then updates every 100 ms with
all counters changing synchronously. Time changing during .
a read is detected by testing the data-changed bit of the
control register after completing a string of clock register
reads.
Interrupt delay times of 0.1 s, 0.5s, 1s, 5s, 10s, 30s or 60s
can be selected with single or repeated interrupt outputs.
The open drain output is pulled low whenever the interrupt
timer times out and is cleared by reading the control register.
(
SEE APPLICATION NOTE)
AN365
Divider Chain .
The crystal oscillator is divided down in three stages to produce a 10Hz frequency setting pulse. The first stage is a
non-integer divider which reduces the 32.768 kHz input to
30.720 kHz. This is further divided by a 9-stage binary ripple
counter giving an output frequency of 60 Hz. A 3-stage
Johnson counter divides this by six, generating a 10Hz output. The 10Hz clock is gated with the 32.768 kHz crystal
frequency to provide clock setting pulses of 15.26 p,s duration. The setting pulse drives all the time registers on the
r:-------,
~--------------------~----~--"--~~---'-5V
100 nF
I ~SC. GUARD GND 6 pF·38 pF
DISK
I (OPTIONAL)
r-
16
15
I
-..I
Jili
DB3
,
Rl
3.3k
DBZ
DBl
DBO
i
OV
AD3
ADZ
ADl
ADO
·Use resistor with Ni·cad cells only
TL/F/S602-S
FIGURE 3. Typical System Connection Diagram'
2-90
Functional Description (Continued)
device which are synchronously clocked by this signal. All
time data and data-changed flag change on the falling edge
of the clock setting pulse.
Both counters may be accessed for read or write operations
as desired.
The tens of hours register has only one active bit and the
top three bits are set to logic O. Data bit 1 of the clock
setting register is the AM/PM indicator; logic 0 indicating
AM, logic 1 for PM.
Bit 0 of the clock setting register must be written to 0 for
correct 12 hour operation.
Data-Changed Flag
The data-changed flag is set by the clock setting pulse to
indicate that the time data has been altered since the clock
was last read. This flag occupies bit 3 of the control register
where it can be tested by the processor to sense datachanged. It will be reset by a read of the control register.
See the section, "Methods of Device Operation", for suggested clock reading techniques using this flag.
Days Counters
There are two days counters:
a) units of days
b) tens of days.
The days counters will count up to 28, 29, 30 or 31 depending on the state of the months counters and the leap year
counter. The microprocessor has full read/write access to
these registers.
Seconds Counters
There are three counters for seconds:
a) tenths of seconds
b) units of seconds
c) tens of seconds.
The registers are accessed at the addresses shown in Table I. The tenths of seconds register is reset to 0 when the
clock start/stop bit (bit 2 of the control register) is set to
logic 1. The units and tens of seconds are set up by the
processor, giving time setting to the nearest second. All
three registers can be read by the processor for time output.
Months Counters
There are two months counters:
a) units of months
b) tens of months.
Both these counters have full read/write access.
Years Counters
There are two years counters:
a) units of years
b) tens of years.
Minutes Counters
There are two minutes counters:
a) units of minutes
b) tens of minutes.
Both these counters have full read/write access. The years
will count up to 99 and roll over to 00.
Both registers may be read to or written from as required.
Hours Counters
There are two hours counters:
a) units of hours
b) tens of hours.
TABLE I. Address Decoding of Real-Time Clock Internal Registers
Address (Binary)
Register Selected
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Control Register
Tenths of Seconds
Units Seconds
Tens Seconds
Units Minutes
Tens Minutes
Unit Hours
Tens Hours
Units Days
Tens Days
Units Months
Tens Months
Units Years
Tens Years
Day of Week
Clock Setting/
Interrupt Registers
AD3
AD2
AD1
ADO
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
1
2-91
(Hex)
Access
0
1
2
3
4
5
6
7
8
9
A
B
C
0
Split Read and Write
Read Only
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
E
F
•
~
.....
o
0lI::l'
.....
~
co
Lt)
:E
:E
r---------------------------------------------------------------------------~-----------
Functional Description (Continued)
Day of Week Counter
The day of week counter increments as the time rolls from
(11 :59 PM to 12:00 AM). It counts from 1 to 7 and rolls back
to 1. Any day of the week may be specified as day 1.
The AM/PM indicator returns a logic 0 for AM and a logic 1
for PM. It is clocked when the hours counter rolls from 11 :59
to 12:00.
Clock Setting Reglster/lnterrupt Register
The interrupt select bit in the control register determines
which of these two registers is accessible to the processor
at address 15. Normal clock and interrupt timing operations
will always continue regardless of which register is selected
onto the bus. The layout of these registers is shown in
Table II.
The clock setting register is comprised of three separate
functions:
The 12-hour mode bit is set to logic 0 for 12-hour mode,
logic 1 is illegal.
IMPORTANT NOTE: Hours mode and AM/PM bits cannot
be set in the same write operation. See the section on Initialization (Methods of Device Operation) for a suggested
semng routine.
All bits in the clock setting register may be read by the processor.
The interrupt register controls the operation of the timer for
interrupt output. The processor programs this register for
single or repeated interrupts at the selected time intervals.
The lower three bits of this register set the time delay period
that will occur between interrupts. The time delays that can
be programmed and the data words that select these are
outlined in Table liB.
Data bit 3 of the interrupt register sets for either single or
repeated interrupts; logic 0 gives single mode, logiC 1 sets
for repeated mode.
USing the interrupt is described in the Device Operation section.
a) leap year counter: bits 2 and 3
b) AM/PM indicator: bit 1
c) 12-hour mode set: bit 0 (see Table IIA).
The leap year counter is a 2-stage binary counter which
is clocked by the months counter. It changes state as the
time rolls over from 11 :59 on December 31 to 00:00 on
January 1.
The counter should be loaded with the 'number of years
since last leap year' e.g., if 1980 was the last leap year, a
clock programmed in 1983 should have 3 stored in the leap
year counter. If the clock is programmed during a leap year,
then the leap year counter should be set to O. The contents
of the leap year counter can be read by the ,...P.
TABLE IIA. Clock Setting Register Layout
Data Bits Used
Function
Leap Year Counter
AM/PM Indicator
12-Hour Bit
DB3
DB2
X
X
DB1
Comments
Access
oIndicates a Leap Year
0= AM 1 = PM
o = 12-Hour Mode
1 = Illegal
R/W
R/W
R/W
DBO
X
X
TABLE liB. Interrupt Control Register
Function
No Interrupt
0.1 Second
0.5 Second
1 Second
5 Seconds
10 Seconds
30 Seconds
60 Seconds
Control Word
Comments
Interrupt output cleared,
start/ stop bit set to 1.
DB3 .= 0 for single interrupt
DB3 = 1 for repeated interrupt
Timing Accuracy: single interrupt mode (all time delays): ± 1 ms
Repeated Mode: ± 1 ms on initial timeout, thereafter synchronous
with first interrupt (I.e., timing errors do not accumulate).
2-92
DB3
DB2
DB1
DBO
X
0
0
0
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0
0
0
1
1
1
1
0
1
1
0
0
1
1
1
0
1
0
1
0
1
Functional Description
3:
3:
(Continued)
U1
A logic 0 in the interrupt select bit makes the clock setting
register available to the processor. A logic 1 selects the
interrupt register.
Control Register
There are three registers which control different operations
of the clock:
The interrupt start/stop bit controls the running of the interrupt timer. It is programmed in the same way as the clock
start/stop bit; logic 1 to halt the interrupt and reset the timer, logic 0 to start interrupt timing.
a) the clock setting register
b) the interrupt register
c) the control register.
I
Q)
N
......
0I:loo
o
.
.....
N
When no interrupt is programmed (interrupt control register
set to 0), the interrupt ~tart/stop bit is automatically set to a
logic 1. When any new interrupt is subsequently programmed, timing will not commence until the start/stop bit
is loaded with O.
The clock setting and interrupt registers both reside at address 15, access to one or the other being controlled by the
interrupt select bit; data bit 1 of the control register.
The' clock setting register programs the timekeeping of the
clock. The 12-hour mode and the AM/PM indicator occupy
bits 0 and 1, respectively. Data bits 2 and 3 set the leap year
counter.
In the single interrupt mode, interrupt timing stops when a
timeout occurs. The processor restarts timing by writing logic 0 into the start/stop bit.
The interrupt register controls the operation of the interrupt
timer, selecting the required delay period and either single
or repeated interrupt.
In repeated interrupt mode the interrupt timer continues to
count with no intervention by the processor necessary.
The control register is responsible for controlling the operations of the clock and supplying status information to the
processor. It appears as two different registers; one with
write only access and one with read only access.
Interrupt timing may be stopped in either mode by writing a
logic 1 into the interrupt start/stop bit. The timer is reset and
can be restarted in the normal way, giving a full time delay
period before the next interrupt.
The write only register consists of a bank of four latches
which control the internal processes of the clock.
In general, the control register is set up such that writing O's
into it will start anything that is stopped, pull the clock out of
test mode and select the clock setting register onto the bus.
In other words, writing 0 will maintain normal clock operation
and restart interrupt timing, etc.
The read only register contains two output data latches
which will supply status information for the processor. Table
III shows the mapping of the various control latches and
status flags in the control register. The control register is
located at address o.
The read only portion of the control register has two status
outputs:
The write only portion of the control register contains four
latches:
Since the MM58274C-12 keeps real time, the time data
changes asynchronously with the processor and this may
occur while the processor is reading time data out of the
clock.
A logic 1 written into the test bit puts the device into test
mode. This allows setting of the oscillator frequency as well
as rapid testing of the device registers, if required. A more
complete description is given in the Test Mode section. For
normal operation the test bit is loaded with logic o.
Some method of warning the processor when the time data
has changed must thus be included. This is provided for by
the data-changed flag located in bit 3 of the control register.
This flag is set by the clock setting pulse which also clocks
the time registers. Testing this bit can tell the processor
whether or not the time has changed. The flag is cleared by
a read of the control register but not by any write operations.
No other register read has any effect on the state of the
data-changed flag.
The clock start/stop bit stops the timekeeping of the clock
and resets to 0 the tenths of seconds counter. The time of
day may then be written into the various clock registers and
the clock restarted synchronously with an external time
source. Timekeeping is maintained thereafter.
A logic 1 written to the start/stop bit halts clock timing. Timing is restarted when the start/stop bit is written with a logic
Data bit 0 is the interrupt flag. This flag is set whenever the
interrupt timer times out, pulling the interrupt output low. In a
polled interrupt routine the processor can test this flag to
determine if the MM58274C-12 was the interrupting device.
This interrupt flag and the interrupt output are both cleared
by a read of the control register.
o.
The interrupt select bit determines which of the two registers mapped onto address 15 will be accessed when this
address is selected.
TABLE III. The Control Register Layout
DB3
DB2
DB1
DBO
Data-Changed Flag
0
0
Interrupt Flag
Test
Clock Start/Stop
0= Clock Run
1 = Clock Stop
Access (addrO)
Read From:
Write To:
0= Normal
1
= Test Mode
2-93
Interrupt Select
Clock Setting Register
1 = Interrupt Register
o=
Interrupt Start/Stop
o = Interrupt Run
1 = Interrupt Stop
•
Functional Description (Continued)
Both of the flags and the interrupt output are reset by the
trailing edge of the read strobe. The flag information is held
latched during a control register read, guaranteeing that stable status information will always be read out by the processor.
1) Disable interrupt on the processor to allow oscillator setting. Write 1510 into the control register: The clock and interrupt start/stop bits are set to 1, ensuring that the clock and
interrupt timers are both halted. Test mode and the interrupt
register are selected.
2) Write 0 to the interrupt register: Ensure that there are no
interrupts programmed and that the oscillator will be gated
onto the interrupt output.
3) Set oscillator frequency: All timing has been halted and
the oscillator is buffered out onto the interrupt line.
4) Write 5 to the control register: The clock is now out oitest
mode but is still halted. The clock setting register is now
selected by the interrupt select bit.
5) Write 0001 to all registers. This ensures starting with a
valid BCD value in each register.
6) Set 12-hour mode: Write 0 to data bit 0 of the clock
setting register.
7) Load Real-Time Registers: All time registers (including
Leap Years and AM/PM bit) may now be loaded in any
order. Note that when writing to the clock setting register to
set up Leap Years and AM/PM, the Hours Mode bit must
not be altered from the value programmed in step 5.
8) Write 0 to the control register: This operation finishes the
clock initialization by starting the time. The final control register write should be synchronized with an external time
source.
In general, timekeeping should be halted before the time
data is altered in the clock. The data can, however, be altered at any time if so desired. Such may be the case if the
user wishes to keep the clock corrected without having to
stop and restart it; i.e., winter/summer time changing can be
accomplished without halting the clock. This can be done in
software by sensing the state of the data-changed flag and
only altering time data just after the time has rolled over
(data-changed flag set).
Interrupt timeout is detected and stored internally if it occurs
during a read of the control register, the interrupt output will
then go low only after the read has been completed.
A clock setting pulse occurring during a control register read
will not affect the data-changed flag since time data read
out before or after the control read will not be affected by
the time change.
METHODS OF DEVICE OPERATION
Test Mode
National Semiconductor uses test mode for functionally
testing the MM58274C-12 after fabrication and again after
packaging. Test mode can also be used to set up the oscillator frequency when the part is first commissioned.
Figure 4 shows the internal clock connections when the device is written into test mode. The 32.768 kHz oscillator is
gated onto the interrupt output to provide a buffered output
for initial frequency setting. This signal is driven from a
TRI-STATE output buffer, enabling easy oscillator setting in
systems where interrupt is not normally used and there is no
external resistor on the pin.
If an. interrupt is programmed, the 32.768 kHz output is
switched off to allow high speed testing of the interrupt timer. The interrupt output will then function as normal.
The clock start/stop bit can be used to coritrol the fast
clocking of the time registers as shown in Figure 4.
Initialization
When it is first installed and power is applied, the device will
need to be properly initialized. The following operation steps
are recommended when the device is set up (all numbers
.
are decimal):
CLOCK
START/STOP
BIT
XTAL OUT - - -.....
INT OUT
TL/F/5602-6
FIGURE 4. Test Mode Organization
2-94
Functional Description (Continued)
Reading the Time Registers
Single Interrupt Mode:
Using the data-changed flag technique supports microprocessors with block move facilities, as all the necessary time
data may be read sequentially and then tested for validity as
shown below.
1) Read the control register, address 0: This is a dummy
read to reset the data-changed flag (DCF) prior to reading
the time registers.
When appropriate, write 0 or 2 to the control register to
restart the interrupt timer.
Repeated Interrupt Mode:
Timing continues, synchronized with the control register
write which originally started interrupt timing. No further intervention is necessary from the processor to maintain timing.
In either mode interrupt timing can be stopped by writing 1
into the control register (interrupt start/stop set to 1). Timing
for the full delay period recommences when the interrupt
start/stop bit is again loaded with 0 as normal.
2) Read time registers: All desired time registers are read
out in a block.
3) Read the control register and test DCF: If DCF is cleared
(logic 0), then no clock setting pulses have after occurred
since step 1. All time data is guaranteed good and time
reading is complete.
Interrupt Programming
IMPORTANT NOTE: Using the interrupt timer places a constraint on the maximum Read Strobe width which may be
applied to the clock. Normally all registers may be read from
with a tRW down to DC (Le., CS and RD held continuously
low). When the interrupt timer is active however, the maximum read strobe width that can be applied to the control
register (Addr 0) is 30 ms.
The interrupt timer generates interrupts at time intervals
which are programmed into the interrupt register. A single
interrupt after delay or repeated interrupts may be programmed. Table liB lists the different time delays and the
data words that select them in the interrupt register.
This restriction is to allow the interrupt timer to properly reset when it times out. Note that it only affects reading of the
control register-all other addresses in the clock may be
accessed with DC read strobes, regardless of the state of
the interrupt timer. Writes to any address are unaffected.
Once the interrupt register has been used to set up the
delay time and to select for single or repeat, it takes no
further part in the workings of the interrupt system. All activity by the processor then takes place in the control register.
NOTES ON AC TIMING REQUIREMENTS
Although the Switching Time Waveforms show Microbus
control signals used for clock access, this does not preclude the use of the MM58274C-12 in other non-Microbus
systems. Figure 5 is a simplified logic diagram showing how
the control signals are gated internally to control access to
the clock registers. From this diagram it is clear that CS
could be used to generate the internal data transfer strobes,
with RD and WR inputs set up first. This situation is illustrated in Figure 6.
If DCF is set (logic 1), then a time change has occurred
since step 1 and time data may not be consistent. Repeat
steps 2 and 3 until DCF is clear. The control read of step 3
will have reset DCF, automatically repeating the step 1 action.
Initializing:
1) Write 3 to the control register (ADO): Clock timing continues, interrupt register selected and interrupt timing stopped
2) Write interrupt control word to address 15: The interrupt
register is loaded with the correct word (chosen from Table
liB) for the time delay required and for single or repeated
interrupts.
3) Write 0 or 2 to the control register: Interrupt timing commences. Writing 0 selects the clock setting register onto the
data bus; writing 2 leaves the interrupt register selected
Normal timekeeping remains unaffected
The internal data busses of the MM58274C-12 are fully
CMOS, contributing to the flexibility of the control inputs.
When determining the suitability of any given control signal
pattern for the MM58274C-12 the timing specifications in
AC Switching Characteristics should be examined. As long
as these timings are met (or exceeded) the MM58274C-12
will function correctly.
On Interrupt:
Read the control register and test for Interrupt Flag (bit 0).
If the flag is cleared (logic 0), then the device is not the
source of the interrupt.
When the MM58274C-12 is connected to the system via a
peripheral port, the freedom from timing constraints allows
for very simple control signal generation, as in Figure 7. For
reading (Figure 7a), Address, CS and RD may be activated
simultaneously and the data will be available at the port
after tAD-max (650 ns). For writing (Figure 7b), the address
and data may be applied simultaneously; 70 ns later CS and
WR may be strobed together.
If the flag is set (logic 1), then the clock did generate an
interrupt. The flag is reset and the interrupt output is cleared
by the control register read that was used to test for interrupt.
2-95
Functional Description
(Continued)
110 BUFFERS
DATA
BC~ c:=::======~
Ro--+--'-~~+-_~
CS--fo--<>
EXTERNAL
SIGNALS
WR---i---L_'
ACCESS
ENABLE
ADDRESS ENABLE
ADDRESS
BC~ c::='.:========~)1
ADDRESS
ENABLES
TO OTHER
) COUNTERS
ADDRESS
DECODER
MM58274C·12
TL/F/5602-7
FIGURE S. MMS8274C-12 Microprocessor Interface Diagram
ADDR:~~
==><
READ ACCESS CYCLE
X
WRITE ACCESS CYCLE
x==
FIGURE 6. Valid MMS8274C-12 Control Signals Using Chip Select Generated Access Strobes
2-96
Functional Description
(Continued)
ADDR:~~ _ _ _JX",___A_DD_R_ES_S_1_ _--,X",___AD_D_RE_S_S_2_ _...,X",___
ifii
«<
DATA
BUS
}1Ii{
VALID DATA 1
VALID DATA 2
a. Port Generated Read Access-2 Addresses Read Out
ADDRESS
BUS
X
X
LI
LI
CS
WR
DATA
BUS
ADDRESS 1
(
WRITE DATA 1
ADDRESS 2
>-
TL/F/5602-9
X
LI
LI
X
WRITE DATA 2
b. Port Generated Write Access-2 Addresses Written To
FIGURE 7. Simple Port Generated Control Signals
2-97
)
TL/F/5602-10
Functional Description
(Continued)
2) Read control register ADO: This is a dummy read to reset
the data-Changed flag.
APPLICATION HINTS
Time Reading Using Interrupt
3) Read control register ADO until data-changed flag is set.
In systems such as point of sale terminals and data loggers,
time reading is usually only required on a random demand
basis. Using the data-changed flag as outlined in the section
on methods of operation is ideal for this type of system.
Some systems, however, need to sense a change in real
time; e.g., industrial timers/process controllers, TV /vCR
clocks, any system where real time is displayed.
4) Write 0 or 2 to control register. Interrupt timing commences.
Time Reading with Very Slow Read Cycles
If a system takes longer than 100 ms to complete reading of
all the necessary time registers (e.g., when CMOS processors are used) or where high level interpreted language routines are used, then the data-changed flag will always be set
when tested and is of no value. In this case, the time registers themselves must be tested to ensure data accuracy.
The interrupt timer on the MM58274C-12 can generate interrupts synchronously with the time registers changing, using software to provide the initial synchronization.
The technique below wiii detect both time changing between read strobes (Le., between reading tens of minutes
and units of hours) and also time changing during read,
which can produce invalid data.
In single interrupt mode the processor is responsible for initiating each timing cycle and the timed period is accurate to
±1 ms.
In repeated interrupt mode the period from the initial processor start to the first timeout is also only accurate to ± 1 ms.
The following interrupts maintain accurate delay periods relative to the first timeout. Thus, to utilize interrupt to control
time reading, we will use repeated interrupt mode.
1) Read and store the value of the lowest order time register
required.
2) Read out all the time registers required. The registers
may be read out in any order, simplifying software requirements.
In repeated mode the time period between interrupts is exact, which means that timeouts will always occur at the
same point relative to the internal clock setting pulses. The
case for 0.1s interrupts is shown in FigureA-1. The same is
true for other delay periods, only there will be more clock
setting pulses between each interrupt timeout. If we set up
the interrupt timer so that interrupt always times out just
after the clock setting pulse occurs (Figure A-2), then there
is no need to test the data-changed flag as we know that
the time data has just changed and will not alter again for
another 100 ms.
3) Read the lowest order register and compare it with the
value stored previously in step 1. If it is still the same, then
all time data is good. If it has changed, then store the new
value and go back to step 2.
In general, the rule is that the first and last reads must both
be of the lowest order time register. These two values can
then be compared to ensure that no change has occurred.
This technique works because for any higher order time register to change, all the lower order registers must also
change. If the lowest order register does not change, then
no higher order register has changed either.
This can be achieved as outlined below:
1) Follow steps 1 and 2 of the section on interrupt programming. In step 2 set up for repeated interrupt.
I
i l - 16 p.S
~1DDms-
J
n
INTERNAL
PULSES
CLOCK
SmlNG
PULSES ......11 ..._ _ _ _ _........._ _ _ _ _........_ _
-tOELAV-j
-tOELAV-j
UI
INTERRUPT
DIP
INTERRUPT
SERVICED
UI
INTERRUPT
SERVICED
TL/F/5602-11
FIGURE A-1. Time Delay from Clock Setting Pulses to Interrupt is Constant
j-1DD
':~~:J.
PULSES
INTERRUPT
DIP
mS---J
~. . .------L
.....-----~I
---u
u
FIGURE A-2. Interrupt Timer Synchronized with Clock Setting Pulses
2-98
TLIF/5602-12
~National
U
Semiconductor
MM58274C
Microprocessor Compatible Real Time Clock
General Description
Features
The MM58274C is fabricated using low threshold metal gate
CMOS technology and is designed to operate in bus oriented microprocessor systems where a real time clock and calendar function are required. The on-chip 32.768 kHz crystal
controlled oscillator will maintain timekeeping down to 2.2V
to allow low power standby battery operation. This device is
pin compatible with the MM58174A but continues timekeeping up to tens of years. The MM58274C is a direct replacement for the MM58274 offering improved Bus access cycle
times.
• Same pin-out as MM58174A, MM58274B, and
MM58274
• Timekeeping from tenths of seconds to tens of years in
independently accessible registers
Applications
•
•
•
•
•
Point of sale terminals
Teller terminals
Word processors
Data logging
Industrial process control
Bloc~
• Leap year register
• Hours counter programmable for 12 or 24-hour
operation
• Buffered crystal frequency output in test mode for easy
oscillator setting
• Data-changed flag allows simple testing for time
rollover
.
•
•
•
•
Independent interrupting tirne with open drain output
Fully TTL compatible
Low power standby operation (10 IlA at 2.2V)
Low cost 16-pin DIP and 20-pin PCC
Diagram
TL/F/11219-1
FIGURE 1
2-99
Ell
Absolute Maximum Ratings (Note 1)
Operating Conditions
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
DC Input or Output Voltage
DC Input or Output Diode Current
Storage Temperature, TSTG
-0.3V to Voo + 0.3V
±5.0mA
- 65·C to + 150·C
Supply Voltage, Voo
260·
Parameter
VIH
High Level Input
Voltage (except
XTALIN)
VIL
Low Level Input
Voltage (except
XTAL IN)
-40·Cto +85·C unless otherwise stated.
Conditions .
Min
Typ
0.8
= -20 p,A
= -1.6 mA
IOH
IOH
VOH
High Level Output
Voltage (INT)
IOH = -20 p,A
(In Test Mode)
VOL
Low Level Output
Voltage (080-083,
INT)
IOL
iOL
= 20/-LA
= 1.6mA
IlL
Low Level Input Current
(ADO-AD3, 080-083)
VIN
= Vss (Note 2)
IlL
Low Level Input Current
(WR.RD)
VIN
IlL
Low Level Input Current
(CS)
VIN
Ouput High Level
Leakage Current (INT)
VOUT
Average Supply Current
All VIN = Vee or Open Circuit
Voo = 2.2V (Standby Mode)
Voo = 5.0V (Active Mode)
(Outputs Disabled)
10
CIN
V
Voo - 0.1
3.7
V
V
Voo - 0.1
V
0.1
0.4
V
V
-5
-80
p,A
= Vss (Note 2)
-5
-190
p,A
= Vss (Note 2)
-5
-550
p,A
2.0
p,A
4
10
1
p,A
mA
5
10
pF
= Voo
Input Capacitance
Output Capacitance
Units
V
High Level Output
Voltage (080-083)
COUT
Max
2.0
VOH
100
Voo
85
Units
V
V
V
·C
500mW
Electrical Characteristics Voo = 5V ±10%, T =
IOZH
Max
5.5
5.5
6.5V
Power Dissipation, Po
Lead Temperature
(Soldering, 10 seconds)
Symbol
Min
4.5
2.2
0
-40
Operating Supply Voltage
Standby Mode Supply Voltage
DC Input or Output Voltage
Operating Temperature Range
pF
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur. All voltages referenced to ground unless otherwise noted.
Note 2: The DBO-DB3 and ADO-AD3 lines all have active P-channel. pull-up transistors which will source current. The ~, l'il5, and WR lines have internal pull-up
resistors to Voo.
2-100
AC Switching Characteristics
= 5V ±0.5V, CL = 100 pF
READ TIMING: DATA FROM PERIPHERAL TO MICROPROCESSOR Voo
Symbol
Commercial
Specification
Parameter
TA
Min
Units
= -40°C to +85°C
Typ
Max
tAD
Address Bus Valid to Data Valid
390
650
tcso
Chip Select On to Data Valid
140
300
ns
tRO
Read Strobe On to Data Valid
140
300
ns
tRW
Read Strobe Width (Note 3, Note 7)
tRA
Address Bus Hold Time from Trailing Edge
of Read Strobe
0
ns
tCSH
Chip Select Hold Time from Trailing Edge
of Read Strobe
0
ns
tRH
Data Hold Time from Trailing Edge
of Read Strobe
70
tHZ
Time from Trailing Edge of Read Strobe
Until alP Drivers are TRI-STATE®
DC
ns
160
250
WRITE TIMING: DATA FROM MICROPROCESSOR TO PERIPHERAL Voo
Symbol
ns
= 5V ±0.5V
Commercial
Specification
Parameter
TA
....r
ns
Units
= -40°C to +85°C
Max
Min
Typ
400
125
ns
250
100
ns
400
220
ns
250
95
ns
tAW
Address Bus Valid to Write Strobe
(Note 4, Note 6)
tcsw
Chip Select On to Write Strobe
tow
Data Bus Valid to Write Strobe
tww
Write Strobe Width (Note 6)
twcs
Chip Select Hold Time Following
Write Strobe
0
ns
tWA
Address Bus Hold Time Following
Write Strobe
0
ns
two
Data Bus Hold Time Following
Write Strobe
100
35
ns
tAWS,
Address Bus Valid Before
Start of Write Strobe
70
20
ns
....r
....r
....r
....r
....r
Note 3: Except for special case restriction: with interrupts programmed, max read strobe width of control register (ADDR 0) is 30 ms. See section on Interrupt
Programming.
Note 4: All timings measured to the trailing edge of write strobe (data latched by the trailing edge of WR).
Note 5: Input test waveform peak voltages are 2.4V and 0.4V. Output signals are measured to their 2.4V and O.4V levels.
Note 6: Write strobe as used in the Write Timing Table is defined as the period when both chip select and write inputs are low, ie., WS, = ~ + WR. Hence write
strobe commences when both signals are low, and terminates when the first signal returns high.
Note 7: Read strobe as used in the Read Timing Table is defined as the period when both chip select and read inputs are low, ie., AS = CS + RD.
Note 8: Typical numbers are at Vec = 5.0V and TA = 25°C.
2-101
Switching Time Waveforms
Read Cycle Timing (Notes 5 and 7)
, , - - - - - - - - - - - - - - - - -...... , - - - - Z.4V
ADDRESS VALID
A3-AO
~-----------------'I
I
t-----ItSD-----l·
----
D.4V
Z.4V
11-_ _ _ _ _ _
iiii
D3-DO
Z.4V
---o+---,-!-------- 0.4V
---+------------Cl
t------~D------~
Tl/F/11219-2
Write Cycle Timing (Notes 5 and 6)
~----------------"""'" 1'---Z.4V
A3-AD
ADDRESS VALID
1'------------------'1 ---t------tcsw-----+I
D.4V
Z.4V
1----~ws----t~I_--
1-----bN----~
D3-DO
---+-------<.1
DATAVAUD
TLlF/11219-3
Connection Diagrams
PCC Package
Dual-In-Llne Package
Cs
Ro
16
VOD
15
XTAL IN
WR
1-4
DB3
. 13
-4
INT
Nle
Nle
XTAL OUT
XTAL OUT
INT
DB2
12
ADO
DB3
Nle
DBI
11
ADI
DB2
ADO
DBO
10
AD2
Nle
ADI
AD3
Vss
Top View
Tl/F/11219-4
Tl/F/11219-5
Top View
FIGURE 2
Order Number MM58274CJ, MM58274CN or MM58274CV
See NS Package J16A, N16A, or V20A
2-102
Functional Description
The MM58274C is a bus oriented microprocessor real time
clock. It has the same pin-out as the MM58174A while offering extended timekeeping up to units and tens of years. To
enhance the device further, a number of other features have
been added including: 12 or 24 hours counting, a testable
data-changed flag giving easy error-free time reading and
simplified interrupt control.
CIRCUIT DESCRIPTION
The block diagram in Figure 1 shows the internal structure
of the chip. The 16-pin package outline is shown in Figure 2.
Crystal Oscillator
This consists of a CMOS inverter/amplifier with an on-chip
bias resistor. Externally a 20 pF capacitor, a 6 pF-36 pF
trimmer capacitor and a crystal are suggested to complete
the 32.768 kHz timekeeping oscillator circuit.
A buffered oscillator signal appears on the interrupt output
when the device is in test mode. This allows for easy oscillator setting when the device is initially powered up in a system.
The 6 pF-36 pF trimmer fine tunes the crystal load impedance, optimizing the oscillator stability. When properly adjusted (Le., to the crystal frequency of 32.768 kHz), the circuit will display a frequency variation with voltage of less
than 3 ppmlV. When an external oscillator is used, connect
to oscillator input and float (no connection) the oscillator
output.
The counters are arranged as 4-bit words and can be randomly accessed for time reading and setting. The counters
output in BCD (binary coded decimal) 4-bit numbers. Any
register which has less than 4 bits (e.g., days of week uses
only 3 bits) will return a logic 0 on any unused bits. When
written to, the unused inputs will be ignored.
When the chip is enabled into test mode, the oscillator is
gated onto the interrupt output pin giving a buffered oscillator output that can be used to set the crystal frequency
when the device is installed in a system. For further information see the section on Test Mode.
Writing a logic 1 to the clock start/stop control bit resets the
internal oscillator divider chain and the tenths of seconds
counter. Writing a logic 0 will start the clock timing from the
nearest second. The time then updates every 100 ms with
all counters changing synchronously. Time changing during
a read is detected by testing the data-changed bit of the
control register after completing a string of clock register
reads.
Interrupt delay times of 0.15, 0.5s, 1S, 55, 105, 30s or 60s
can be selected with single or repeated interrupt outputs.
The open drain output is pulled low whenever the interrupt
timer times out and is cleared by reading the control register.
(
SEE APPLICATION NOTE)
AN365
Divider Chain
The crystal oscillator is divided down in three stages to produce a 10Hz frequency setting pulse. The first stage is a
non-integer divider which reduces the 32.768 kHz input to
30.720 kHz. This is further divided by a 9-stage binary ripple
counter giving an output frequency of 60 Hz. A 3-stage
Johnson counter divides this by six, generating a 10Hz output. The 10Hz clock is gated with the 32.768 kHz crystal
frequency to provide clock setting pulses of 15.26 P.s duration. The setting pulse drives all the time registers on the
r---------------------~-----1~_.----._--~~5V
100 nF
DISK
R2
470n
01
Si
TR3
2N2907
iiii
DB3
DB2
02
3.6V
Rl
3.3k
OBI
:E
en
:::>
'"
-=-+
-=-
DBa
0
a:
'-'
:iE
BATT
3V NOM
R3
10 k
R4
22011
OV
AD3
AD2
AOI
ADO
'Use resistor with Ni-cad cells only
TL/F/11219-6
FIGURE 3. Typical System Connection Diagram
2-103
Functional Description
(Continued)
device which are synchronously clocked by this signal. All
time data and data-changed flag change on the falling edge
of the clock setting pulse.
Both counters may be accessed for read or write operations
as desired.
In 12-hour mode, the tens of hours register has only one
active bit and the top three bits are set to logic O. Data bit 1
of the clock setting register is the AM/PM indicator; logic 0
indicating AM, logic 1 for PM.
Data-Changed Flag
The data-changed flag is set by the clock setting pulse to
indicate that the time data has been altered since the clock
was last read. This flag occupies bit 3 of the control register
where it can be tested by the processor to sense datachanged. It will be reset by a read of the control register.
See the section, "Methods of Device Operation", for suggested clock reading techniques using this flag.
When 24-hour mode is programmed, the tens of hours register reads out two bits of data and the two most significant
bits are set to logic O. There is no AM/PM indication and bit
1 of the clock setting register will read out a logic O.
In both 12/24-hour modes, the units of hours will read out
four active data .bits. 12 or 24-hour mode is selected by bit 0
of the clock setting register, logic 0 for 12-hour mode, logic
1 for the 24-hour mode.
Seconds Counters
There are three counters for seconds:
a) tenths of seconds
Days Counters
b) units of seconds
There are two days counters:
c) tens of seconds.
a) units of days
The registers are accessed at the addresses shown in Table I. The tenths of seconds register is reset to 0 when the
clock start/stop bit (bit 2 of the control register) is set to
logic 1. The units and tens of seconds are set up by the
processor, giving time setting to the nearest second. All
three registers can be read by the processor for time output.
The days counters will count up to 28, 29, 30 or 31 depending on the state of the. months counters and the leap year
counter. The microprocessor has full read/write access to
these registers.
b) tens of days.
Months Counters
Minutes Counters
There are two months counters:
There are two minutes counters:
a) units of months
a) units of minutes
b) tens of months.
b) tens of minutes.
Both these counters have full read/write access.
Both registers may be read to or written from as required.
Years Counters
Hours Counters
There are two years counters:
There are two hours counters:
a) units of years
a) units of hours
b) tens of years.
b) tens of hours.
Both these counters have full read/write access. The years
will count up to 99 and roll over to 00.
TABLE I. Address Decoding of Real-Time Clock Internal Registers
Address (Binary)
Register Selected
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Control Register
Tenths of Seconds
Units Seconds
Tens Seconds
Units Minutes
Tens Minutes
Unit Hours
Tens Hours
Units Days
Tens Days
Units Months
Tens Months
Units Years
Tens Years
Day of Week
Clock Setting/
Interrupt Registers
AD3
AD2
AD1
ADO
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
0
1
1
1
0
2-104
1
(Hex)
Access
0
1
2
3
4
5
6
Split Read and Write
Read Only
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7
8
9
A
B
C
D
E
F
Functional Description
(Continued)
Day of Week Counter
The day of week counter increments as the time rolls from
23:59 to 00:00 (11 :59 PM to 12:00 AM in 12-hour mode). It
counts from 1 to 7 and rolls back to 1. Any day of the week
may be specified as day 1.
The AM/PM indicator returns a logic 0 for AM and a logic 1
for PM. It is clocked when the hours counter rolls from 11 :59
to 12:00 in 12-hour mode. In 24-hour mode this bit is set to
logic O.
The 12/24-hour mode set determines whether the hours
counter counts from 1 to 12 or from 0 to 23. It also controls
the AM/PM indicator, enabling it for 12-hour mode and forcing it to logic 0 for the 24-hour mode. The 12/24-hour mode
bit is set to logic 0 for 12-hour mode and it is set to logic 1
for 24-hour mode.
Clock Setting Register/Interrupt Register
The interrupt select bit in the control register determines
which of these two registers is accessible to the processor
at address 15. Normal clock and interrupt timing operations
will always continue regardless of which register is selected
onto the bus. The layout of these registers is shown in
Table II.
IMPORTANT NOTE: Hours mode and AM/PM bits cannot
be set in the same write operation. See the section on Ir.:tialization (Methods of Device Operation) for a suggested
setting routine.
All bits in the clock setting register may be read by the processor.
The interrupt register controls the operation of the timer for
interrupt output. The processor programs this register for
single or repeated interrupts at the selected time intervals.
The lower three bits of this register set the time delay period
that will occur between interrupts. The time delays that can
be programmed and the data words that select these are
outlined in Table liB.
Data bit 3 of the interrupt register sets for either single or
repeated interrupts; logic 0 gives single mode, logic 1 sets
for repeated mode.
Using the interrupt is described in the Device Operation section.
The clock setting register is comprised of three separate
functions:
a) leap year counter: bits 2 and 3
b) AM/PM indicator: bit 1
c) 12-hour mode set: bit 0 (see Table IIA).
The leap year counter is a 2-stage binary counter which
is clocked by the months counter. It changes state as the
time rolls over from 11 :59 on December 31 to 00:00 on
January 1.
I
The counter should be loaded with the 'number of years
since last leap year' e.g., if 1980 was the last leap year, a
clock programmed in 1983 should have 3 stored in the leap
year counter. If the clock is programmed during a leap year,
then the leap year counter should be set to O. The contents
of the leap year counter can be read by the J.LP.
TABLE IIA. Clock Setting Register Layout
Data Bits Used
Function
Leap Year Counter
AM/PM Indicator (12-Hour Mode)
DB3
DB2
x
x
DB1
Comments
Access
o Indicates a Leap Year
0= AM 1 = PM
o in 24-Hour Mode
o = 12-Hour Mode
1 = 24-Hour Mode
R/W
R/W
DBD
x
x
12/24-Hour Select Bit
R/W
TABLE liB. Interrupt Control Register
Function
No Interrupt
0.1 Second
0.5 Second
1 Second
5 Seconds
10 Seconds
30 Seconds
60 Seconds
Control Word
Comments
Interrupt output cleared,
start/stop bit set to 1.
DB3 = 0 for single interrupt
DB3 = 1 for repeated interrupt
Timing Accuracy: single interrupt mode (all time delays): ± 1 ms
Repeated Mode: ± 1 ms on initial timeout, thereafter synchronous
with first interrupt (Le., timing errors do not accumulate).
2-105
DB3
DB2
DB1
DBD
X
0
0
0
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0
0
0
1
1
1
1
0
1
1
0
0
1
1
1
0
1
0
1
0
1
Functional Description
(Continued)
A logic 0 in the interrupt select bit makes the clock setting
register available to the processor. A logic 1 selects the
interrupt register.
Control Register
There are three registers which control different operations
of the clock:
The interrupt start/stop bit controls the running of the interrupt timer. It is programmed in the same way as the clock
start/stop bit; logic 1 to halt the interrupt and reset the timer, logic 0 to start interrupt timing.
.
a) the clock setting register
b) the interrupt register
c) the control register.
When no interrupt is programmed (interrupt control register
set to 0), the interrupt start/stop bit is automatically set to a
logic 1. When any new interrupt is subsequently programmed, timing will not commence until the start/stop bit
is loaded with O.
The clock setting and interrupt registers both reside at address 15, access to one or the other being controlled by the
interrupt select bit; data bit 1 of the control register.
The clock setting register programs the timekeeping of the
clock. The 12/24-hour mode select and the AM/PM indicator for 12-hour mode occupy bits 0 and 1, respectively. Data
bits 2 and 3 set the leap year counter.
In the single interrupt mode, interrupt timing stops when a
timeout occurs. The processor restarts timing by writing logic 0 into the start/stop bit.
The interrupt register controls the operation of the interrupt
timer, selecting the required delay period and either single
or repeated interrupt.
In repeated interrupt mode the interrupt timer continues to
count with no intervention by the processor necessary.
The control register is responsible for controlling the operations of the clock and supplying status information to the
processor. It appears as two different registers; one with
write only access and one with read only access.
Interrupt timing may be stopped in either mode by writing a
logic 1 into the interrupt start/stop bit. The timer is reset and
can be restarted in the normal way, giving a full time delay
period before the next interrupt.
The write only register consists of a bank of four latches
which control the internal processes of the clock.
In general, the control register is set up such that writing O's
into it will start anything that is stopped, pull the clock out of
test mode and select the clock setting register onto the bus.
In other words, writing 0 will maintain normal clock operation
and restart interrupt timing, etc.
The read only register contains two output data latches
which will supply status information for the processor. Table
III shows the mapping of the various control latches and
status flags in the control register. The control register is
located at address O.
The read only portion of the control register has two status
outputs:
Since the MM58274C keeps real time, the time data
changes asynchronously with the processor and this may
occur while the processor is reading time data out of the
clock.
The write only portion of the control register contains four
latches:
A logic 1 written into the test bit puts the device into test
mode. This allows setting of the oscillator frequency as well
as rapid testing of the device registers, if required. A more
complete description is given in the Test Mode section. For
normal operation the test bit is loaded with logic o.
Some method of warning the processor when the time data
has changed must thus be included. This is provided for by
the data-changed flag located in bit 3 of the control register.
This flag is set by the clock setting pulse which also clocks
the time registers. Testing this bit can tell the processor
whether or not the time has changed. The flag is cleared by
a read of the control register but not by any write operations.
No other register read has any effect on the state of the
data-changed flag.
The clock start/stop bit stops the timekeeping of the clock
and resets to 0 the tenths of seconds counter. The time of
day may then be written into the various clock registers and
the clock restarted synchronously with an external time
source. Timekeeping is maintained thereafter.
A logic 1 written to the start/stop bit halts clock timing. Timing is restarted when the start/stop bit is written with a logic
Data bit 0 is the interrupt flag. This flag is set whenever the
interrupt timer times out, pulling the interrupt output low. In a
polled interrupt routine the processor can test this flag to
determine if the MM58274C was the interrupting device.
This interrupt flag and the interrupt output are both cleared
by a read of the control register.
o.
The interrupt select bit determines which of the two registers mapped onto address 15 will be accessed when this
address is selected.
TABLE III. The Contr,ol Register Layout
Access (addrO)
Read From:
Write To:
DB3
DB2
DB1
DBO
Data-Changed Flag
o
o
Interrupt Flag
Test
Clock Start/Stop
0= Clock Run
1 = Clock Stop
0= Normal
1 = Test Mode
2-106
Interrupt Select
Clock Setting Register
1 = Interrupt Register
o=
Interrupt Start/Stop
o = Interrupt Run
1 = Interrupt Stop
Functional Description
(Continued)
Both of the flags and the interrupt output are reset by the
trailing edge of the read strobe. The flag information is held
latched during a control register read, guaranteeing that stable status information will always be read out by the processor.
1) Disable interrupt on the processor to allow oscillator setting. Write 1510 into the control register: The clock and interrupt start/stop bits are set to 1, ensuring that the clock and
interrupt timers are both halted Test mode and the interrupt
register are selected
Interrupt timeout is detected and stored internally if it occurs
during a read of the control register, the interrupt output will
then go low only after the read has been completed.
2) Write 0 to the interrupt register: Ensure that there are no
interrupts programmed and that the oscillator will be gated
onto the interrupt output.
A clock setting pulse occurring during a control register read
will not affect the data-changed flag since time data read
out before or after the control read will not be affected by
the time change.
3) Set oscillator frequency: All timing has been halted and
the oscillator is buffered out onto the interrupt line.
4) Write 5 to the control register: The clock is now out of test
mode but is still halted The· clock setting register is now
selected by the interrupt select bit.
METHODS OF DEVICE OPERATION
5) Write 0001 to all registers. This ensures starting with a
valid BCD value in each register.
Test Mode
National Semiconductor· uses test mode for functionally
testing the MM58274C after fabrication and again after
packaging. Test mode can also be used to set up the oscillator frequency when the part is first commissioned.
6) Set 12/24 Hours Mode: Write to the clock setting register
to select the hours counting mode required
7) Load Real-Time Registers: All time registers (including
Leap Years and AM/PM bit) may now be loaded in any
order. Note that when writing to the clock setting register to
set up Leap Years and AM/PM, the Hours Mode bit must
not be altered from the value programmed in step 5.
Figure 4 shows the internal clock connections when the device is written into test mode. The 32.768 kHz oscillator is
gated onto the interrupt output to provide a buffered output
for initial frequency setting. This signal is driven from a
TRI-STATE output buffer, enabling easy oscillator setting in
systems where interrupt is not normally used and there is no
external resistor on the pin.
8) Write 0 to the control register: This operation finishes the
clock initialization by starting the time. The final control register write should be synchronized with an external time
source.
If an interrupt is programmed, the 32.768 kHz output is
switched off to allow high speed testing of the interrupt timer. The interrupt output will then function as normal.
In general, timekeeping should be halted before the time
data is altered in the clock. The data can, however, be altered at any time if so desired. Such may be the case it'the
user wishes to keep the clock corrected without having to
stop and restart it; i.e., winter/summer time changing can be
accomplished without halting the clock. This can be done in
software by sensing the state of the data-changed flag and
only altering time data just after the time has rolled over
(data-changed flag set).
The clock start/stop bit can be used to control the fast
clocking of the time registers as shown in Figure 4.
Initialization
When it is first installed and power is applied, the device will
need to.be properly initialized. The following operation steps
are recommended when the device is set up (all numbers
are decimal):
CLOCK
START/STOP
BIT
XTAllN
XTAL OUT - - -...
INT OUT
TL/F/11219-7
FIGURE 4. Test Mode Organization
2-107
Functional Description
(Continued)
Reading the Time Registers
Using the data-changed flag technique supports microprocessors with block move facilities, as all the necessary time
data may be read sequentially and then tested for validity as
shown below.
Single Interrupt Mode:
When appropriate, write 0 or 2 to the control register to
restart the interrupt timer.
Repeated Interrupt Mode:
Timing continues, synchronized with the control register
write which originally started interrupt timing. No further iritervention is necessary from the processor to maintain timing.
1) Read the control register, address 0: This is a dummy
read to reset the data-changed flag (DCF) prior to reading
the time registers.
2) Read time registers: All desired time registers are read
out in a block.
In either mode interrupt timing can be stopped by writing 1
into the control register (interrupt start/stop set to 1). Timing
for the full delay period recommences when the interrupt
start/stop bit is again loaded with 0 as normal.
3) Read the control register and test DCF: If DCF is cleared
(logic 0), then no clock setting pulses have after occurred
since step 1. All time data is guaranteed good and time
reading is complete.
Interrupt Programming
IMPORTANT NOTE: Using the interrupt timer places a con~
straint on the maximum Read Strobe width which may be
applied to the clock. Normally all registers may be read from
with a tRW down to DC (Le., CS and RD held continuously
low). When the interrupt timer is active however, the maximum read strobe width that can be applied to the control
register (Addr 0) is 30 ms.
The interrupt timer generates interrupts at time intervals
which are programmed into the interrupt register. A single
interrupt after delay or repeated interrupts may be programmed. Table liB lists the different time delays andthe
data words that select them in the interrupt register.
This restriction is to allow the interrupt timer to properly reset when it times out. Note that it only affects reading of the
control register-all other addresses in the clock may be
accessed with DC read strobes, regardless of the state of
the interrupt timer. Writes to any address are unaffected.
If DCF is set (logic 1), then a· time change has .occurred
since step 1 and time data may not be consistent. Repeat
steps 2 and 3 until DCF is clear. The control read of step 3
will have reset DCF, automatically repeating the step 1 action.
Once the interrupt register has been used to set up the
delay time and to select for single or repeat, it takes no
further part in the workings of the interrupt system. All activity by the processor then takes place in the control register.
Initializing:
NOTES ON AC TIMING REQUIREMENTS
Although the Switching Time· Waveforms show Microbus
control signals used for clock access, this does not preclude the use of the MM58274C in other non-Microbus systems. Figure 5 is a simplified logic diagram showing how the
control signals are gated internally to control access to the
clock registers. From this diagram it is clear that CS could
be used to generate the internal data transfer strobes, with
RD and WR inputs set up first. This situation is illustrated in
Figure 6.
1) Write 3 to the control register (ADO): Clock timing continues, interrupt register selected and interrupt timing stopped.
2) Write interrupt control word to address 15: The interrupt
register is loaded with the correct word (chosen from Table
liB) for the time delay required and for single or repeated
interrupts.
The internal data busses of the MM58274C are fully CMOS,
contributing to the flexibility of the control inputs. When determining the suitability of any given control signal pattern
for the MM58274C the timing specifications in AC Switching
Characteristics should be examined. As long as these timings are met (or exceeded) the MM58274C will function correctly.
3) Write 0 or 2 to the control register: Interrupt timing commences. Writing 0 selects the clock setting register onto the
data bus; writing 2 leaves the interrupt register selected.
Normal timekeeping remains unaffected.
On Interrupt:
Read the control register and test for Interrupt Flag (bit 0).
If the flag is cleared (logic 0), then the device is not the
source of the interrupt.
When the MM58274C is connected to the system via a peripheral port, the freedom from timing constraints allows for
very simple control signal generation, as in Figure 7. For
reading (Figure 7a), Address, CS and RD may be activated
simultaneously and the data will be available at the port
after tAD-max (650 ns). For writing (Figure 7b), the address
and data may be applied simultaneously; 70 ns later CS and
WR may be strobed together.
If the flag is set (logic 1), then the clock did generate an
interrupt. The flag is reset and the interrupt output is cleared
by the control register read that was used to test for interrupt.
2-108
Functional Description
(Continued)
110 BUFFERS
DATA
BG~ -
~+
. .- - - -. .
Ro---+----~~~+---~
cs---+--.
EXTERNAL
SIGNALS
WR---+--LJI'
ADDRESS
BG~ -
~
. .- - - -...
ADDRESS
DECOOER
MM58214C
TL/F/11219-8
FIGURE 5. MM58274C Microprocessor Interface Diagram
ADDRESS~
\J
cs
iiii
X
READ ACCESS CYCLE
BUS
x=
\J
I
\
I
\
WR
DATA
BUS
WRITE ACCESS CYCLE
@
DATA
(
WRITE
DATA
r-
TL/F/11219-9
FIGURE 6. Valid MM58274C Control Signals Using Chip Select Generated Access Strobes
fII
2-109
Functional Description
(Continued)
ADDR:~~ _ _ _JX,,___A_DD_R_ES_S_l___-.JX,"___A_DD_R_ES_S_2_ _--'X"'___
..
•
iii)
DATA
BUS
VALID DATA 1
VALID DATA 2
)TLlF/11219-10
a. Port Generated Read Access-2 Addresses Read Out
ADDRESS
BUS
X
X
'---I
LJ
cs
WR
DATA
BUS
ADDRESS 1
(
WRiTE DATA 1
ADDRESS 2
X
'---I
'---I
X
WRITE DATA 2
b. Port Generated Write Access-2 Addresses Written To
FIGURE 7. Simple Port Generated Control Signals
2·110
)
TL/F/11219-11
Functional Description
(Continued)
2) Read control register ADO: This is a dummy read to reset
the data-changed flag.
APPLICATION HINTS
Time Reading Using Interrupt
3) Read control register ADO until data-changed flag is set.
In systems such as point of sale terminals and data loggers,
time reading is usually only required on a random demand
basis. Using the data-changed flag as outlined in the section
on methods of operation is ideal for this type of system.
Some systems, however, need to sense a change iri real
time; e.g., industrial timers/process controllers, TV /vCR
clocks, any system where real time is displayed.
4) Write 0 or 2 to control register. Interrupt timing
mences.
COm~
Time Reading with Very Slow Read Cycles
If a system takes longer than 100 ms to complete reading of
all the necessary time registers (e.g., when CMOS processors are used) or where high level interpreted language routines are used, then the data-changed flag will always be set
when tested and is of no value. In this case, the time registers themselves must be tested to ensure data accuracy.
The interrupt timer on the MM58274C can generate interrupts synchronously with the time registers changing, using
software to provide the initial synchronization.
The technique below will detect both time changing between read strobes (Le., between reading tens of minutes
and units of hours) and also time changing during read,
which can produce invalid data.
In single interrupt mode the processor is responsible for initiating each timing cycle and the timed period is accurate to
±1 ms.
In repeated interrupt mode the period from the initial processor start to the first timeout is also only accurate to ± 1 ms.
The following interrupts maintain accurate delay periods relative to the first timeout. Thus, to utilize interrupt to control
time reading, we will use repeated interrupt mode.
1) Read and store the value of the lowest order time register
required.
2) Read out all the time registers required. The registers
may be read out in any order, simplifying software requirements.
3) Read the lowest order register and compare it with the
value stored previously in step 1. If it is still the same, then
all time data is good. If it has changed, then store the new
value and go back to step 2.
In general, the rule is that the first and last reads must both
be of the lowest order time register. These two values can
then be compared to ensure that no change has occurred.
This technique works because for any higher order time register to change, all the lower order registers must also
change. If the lowest order register does not change, then
no higher order register has changed either.
In repeated mode the time period between interrupts is exact, which means that timeouts will always occur at the
same point relative to the internal clock setting pulses. The
case for 0.1 s interrupts is shown in Figure A-t. The same is
true for other delay periods, only there will be more clock
setting pulses between each interrupt timeout. If we set up
the interrupt timer so that interrupt always times out just
after the clock setting pulse occurs (Figure A-2), then there
is no need to test the data-changed flag as we know that
the time data has just changed and will not alter again for
another 100 ms.
This can be achieved as outlined below:
1) Follow steps 1 and 2 of the section on interrupt programming. In step 2 set up for repeated interrupt.
.~
_11_16~
1-100ms-
r
n
INTERNAL
PULSES
CLOCK
SmlNG
PULSES _1 ..._ _ _ _ _ _.. """_ _ _ _ _ _...._ __
-tDELAy-j
-tDELAy-j
UI
INTERRUPT
DIP
INTERRUPT
SERVICED
UI
INTERRUPT
SERVICED
TL/F/11219-12
FIGURE A-1. Time Delay from Clock Setting Pulses to Interrupt Is Constant
j-100ms~
IN:~~~~
PULSES
INTERRUPT
O/P
J
--U
~
L
u
FIGURE A-2. Interrupt Timer Synchronized with Clock Setting Pulses
2-111
Ell
TL/F/11219-13
-
'-/
2
W'R-3
The addressable reset latch causes the pre-scaler, tenths of
seconds, seconds, and tens of seconds to be held in a reset
condition. If a register is updated during a read operation the
I/O data is prevented from updating and a subsequent read
will return the illegal b.c.d. code '1111'. The interrupt timer
may be programmed for intervals of 0.5 second, 5 seconds,
or 60 seconds and may be coded as a single or repeated
operation. The open drain interrupt output is pulled to Vss
when the timer times out and reading the interrupt register
provides the internal selected information.
16 -Voo
15 -CRYSTAL IN
14 -CRYSTAL OUT
083- 4
13 - INTERRUPT
082- 5
12 -ADO
081- 6
II~AOI
080- 7
10
~A02
9
~A03
VSS -
8
TL/F/66Bl-2
Top View
Order Number MM58174AN
See NS Package Number N16A
The possibility may be overcome by implementing a further
read of the tenths of seconds register at the end of every
series of reads (starting with a read at the tenths of seconds
register) and checking for unchanged data.
Circuit Description
The block diagram shown in Figure 1 shows the structure of
the CMOS clock chip. A 16-pin OIL package is used.
SECONDS COUNTERS
CRYSTAL OSCILLATOR
There are three counters for Seconds:
This consists of a CMOS inverter/amplifier with on-chip bias
resistor and capacitors. A single 6 pF-36 pF trimmer is all
that is required to fine tune the crystal (see Figure 2). However, for improved stability, some crystals may require a capacitor of typical value 20 pF to be added between pin 14
and ground. The output of the oscillator is blocked by the
start/stop F/F.
a) tenths of seconds
b) units of seconds
c) tens of seconds
The outputs of all three counters can be separately multiplexed on to the command 4-bit output bus. Table I shows
the address decoding for each counter. All three counters
are reset to zero by the start/stop F/F.
NON-INTEGER DIVIDER
MINUTES COUNTERS
This counter divides the incoming 32,768 Hz frequency by
15/16 down to 30,720 Hz.
There are two Minutes counters:
a) units of minutes
FIXED DIVIDER (512)
b) tens of minutes
This is a standard 9-stage binary' ripple counter. Output frequency is 60 Hz. This counter is reset to zero by start/stop
F/F.
Both counters are parallel loaded with data from the 4-bit
input bus when addressed by the microprocessor and a
Write Data Strobe pulse given. Similarly, the output of both
counters can be read separately onto the common 4-bit output bus (Table I).
FIXED DIVIDER (6)
This is a 3-stage Johnson counter with a 10Hz output signal. This counter is reset to zero state by the start/stop F/F.
HOURS COUNTERS
There are two Hours counters which will count in a 24-hour
mode:
SYNCHRONIZATION STAGE
Both 10Hz and 32,768 Hz clocks are fed into this section. It
is used to generate a pulse of 15.25 I1-s width on the rising
edge of each 10Hz pulse.
a) units of hours
This pulse is used to increment all the seconds, minutes,
hours, days, months, and year counter and also to set the
data changed F/F.
Both counters have identical parallel load and read mUltiplex features to the Minutes counters.
b) tens of hours
SEVEN DAY COUNTER
DATA CHANGED F/F
There is a 7-state counter which increments every 24 hours.
It will have identical parallel load and read multiplex capabilities to the Minutes and Hours counters. The counter counts
cyclically from 1-7.
This is set by the rising edge of each 10Hz pulse to indicate
that the clock value has changed since the last read operation. It is reset by any clock read command.
The flip flop sets all data bus bits to a "1" during RD time
indicating that a register has been updated. This transient
condition may occur at the end of the Read Data strobe.
Hence, invalid data may still be read from the clock, if the
strobe width was less than 3 I1-s.
2-114
Circuit Description
(Continued)
20M
200k
I
15
8PF
14
~----~D~----~
I...,20 PF
TL/F/6681-3
FIGURE 2. Crystal Oscillator
DAYS COUNTER
There are two Days counters:
a) units of days
b) tens of days
The Days counters will count up to 28, 29, 30, or 31 days
depending on the state of the Months counters and the
Years Status Register. Days counters have parallel load and
read multiplex capabilities.
TLlF/6681-4
FIGURE 3. Test Mode Organization
MONTHS COUNTERS
START/STOP(RESET) LATCH
There are two Months counters:
A logic "1" on DBO at chip address 14 (E) will start the clock
running, a logic "0" will stop the clock. This function aHows
the loading of time data into the clock and its precise starting. The clock starts at 0.1 seconds.
a) units of months
b) tens of months
The Months counters have parallel load and read multiplex
capabilities.
TEST MODE
YEARS STATUS REGISTER
This mode is incorporated to facilitate production testing of
the circuit. In this mode, the 32,768 Hz clock is fed forward
as shown in Figure 3. For normal operation, the circuit must
be set to the non-test mode as part of the system initialization. This is accomplished by writing a logic "0" to DB3 at
ADO.
The Years Status register is a shift register of 4 bits. It will be
shifted every year on December 31 st. The status register
must be set in accordance with Table III. No readout capability is provided.
CHIP SELECT (CS)
TABLE I. Address Decoding for Internal Registers
An external chip select is provided. The chip enable is active low.
Selected
Counter
COUNTER AND REGISTER SELECTION
Table I shows the coding on the address lines ADO-AD3
which select the registers in the circuit to be either parallel
loaded or read on to the output bus.
0 Test Only
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
2-115
Tenths of Sees.
Units of Secs.
Tens of Sees.
Units of Mins.
Tens of Mins.
Units of Hours
Tens of Hours
Units of Days
Tens of Days
Day of Week
Units of Months
Tens of Months
Years
Stop/Start
Interrupt
Address Bits
Mode
AD3 AD2 AD1 ADO
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
1.
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Write Only
Read Only
Read Only
Read Only
Read or Write
Read or Write
Read or Write
Read or Write
Read or Write
Read or Write
Read or Write
Read or Write
Read or Write
Write Only
Write Only
Read or Write
•
Circuit Description
(Continued)
TABLE lIa.lnterrupt Selection Data
Mode: Address 15, Write Mode
Function
DB3
DB2
DB1
DBO
No Interrupt
Int. at 60 Sec. Intervals·
Int. at 5.0 Sec. Intervals·
Int. at 0.5 Sec. Intervals·
X
0/1
0/1
0/1
0
1
0
0
0
0
1
0
0
0
0
1
.+
TLlF/6681-5
Cl ::::: 0.003 pF
Co::::: 3.0 pF
FIGURE 4. Typical Crystal Parameters
16.6 ms
DB3
= 0, single interrupt
DB3
=
DEVICE INITIALIZATION AND OSCILLATOR SETTING
When first installed or if the battery back-up has failed, the
MM58174A will require to be properly initialized. The following sequence is a suggested flow of operations to achieve
this.
1, repeated interrupt
TABLE lib. Interrupt Read Back (Status)
Mode: Address 15, Read Mode
Interrupt Status
DB3
DB2
DB1
DBO
X
X
X
X
0
1
0
0
0
0
1
0
0
0
0
1
Reset
60 Sec. Signal
5.0 Sec. Signal
0.5 Sec. Signal
x=
Rs::::: 35 k!l
Action
1) Apply power.
don't care state
TABLE III. Years Status Register
Mode: Address 13, Write Mode
DB3
DB2
DB1
DBO
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
Leap Year
Leap Year-1
Leap Year-2
Leap Year-3
Note: leap year counter rolls over on December 31
@
2) Write "0" to address 15.
Result
Clears interrupt timer
chain.
3) Read 3 times from
address 15.
Clears interrupt output
logic.
4) Write "0" on DB3 to
address O.
Clears test mode.
5) Write "0" on DBO to
address 14.
Stops clock running.
6) Set up timekeeping
registers.
Load real-time into device
time registers, minutes to
leap years.
7) Write "1" on DBO to
address 14.
Starts timekeeping
synchronized to an
external time source.
8) Program and start
interrupts.
Commence interrupt
timing, if so required.
23:59:59.
OSCILLATOR SETTING
INTERRUPT SYSTEM
Directly connecting a frequency meter to the Crystal Out pin
(14) will not allow correct frequency setting because of the
extra capacitive loading of the meter. One possibility for setting is to use a high impedance probe or a CMOS buffer to
keep the loading as low as possible (e.g., 100 x 2 pF probe).
Alternatively, a buffered output of 16.384 kHz OSC/2 can
be produced on DBO by applying the following procedure:
The interrupt output and its frequency of operation is enabled by writing to address 15 (see Table lIa). To ensure
correct operation, the interrupt should be serviced within
16.6 ms.
The interrupt is initialized by writing "0" to address 15 and
reading the interrupt, Le., reading at address 15 three times.
Initialization must be performed at power on and also if the
interrupt is not serviced correctly within 16.6 ms.
Action
Result
1) Write a "1" on DB3 to
address O.
Selects test mode.
In a typical system the open drain interrupt output is wired to
the processor interrupt system. Hence, when the interrupt
timer times out, the interrupt output is pulled low and the
processor is interrupted.
2) Write a "1" on DBO to
address 14.
Starts clock timing.
3) Read at address 1 (tenths
of secs).
"Data Changed" signal is
read.
The processor may then reset the interrupt by utilizing the
following procedure:
4) Read at address 1 and
HOLD the strobe LOW.
16.384 kHz appears on
DBO.
SERVICING THE INTERRUPT
Read Address 15 three times.
5) Adjust trimmer capacitor.
This resets the interrupt output and restarts the interrupt
timer when in the repeat mode.
There must be no extra activity on the RD line between
steps 3 and 4 or only the normal "Data Changed" signal will
be observed on the data bus. Thus if the· normal host processor system is being used to generate the chip waveforms,
proper care must be taken.
It is recommended that the interrupt output is connected to
a unique processor port.
CRYSTAL PARAMETERS
Figure 4 is an electrical representation of the crystal along
with some typical values. The 32.768 kHz crystal is an NT
CUT (tuning fork type) or XY BAR for use in a parallel resonant Pierce oscillator.
2-116
Timing Waveforms
READ MODE
WRITE MODE
Figure 6 gives detailed timing for the transfer of data from
peripheral to microprocessor. See Table IV.
Figure 7 gives detailed timing for the transfer of data from
microprocessor to peripheral. See Table V.
All times are measured from (or to) valid logic
O.BV or valid logic "1" level = 2.0V.
"a"
level =
-=- 3V
..L
16
15
WR
DB3
DB2
DBI
DBO
14
4
5
MM58174A
6- 36 pF
13
STANDBY
SELECT
12
-
6
AD3
AD2
ADI
ADO
MICROPROCESSOR BUS
TLlF/6681-6
FIGURE 5. Typical Microprocessor Interface
A3-AO
-,
---A\
ADDRESS VALID
V-
V-
---AL
___
_ _ _~
A3-AO - - ,_ _ _
ADDRESS
VALID
~
tcsw
f.--
tAW
tww
_-'''-_.II
--I
------""'X
tow
D3-oo
D3-oo
DATA VALID
I-- two
X~--TLlF/6681-8
FIGURE 7. Write Cycle Waveforms
TLlF/6681-7
FIGURE 6. Read Cycle Waveforms
60
I
50
'I
J
40
~
30
20
10
o
o
/
/
V
,/
3
Voo (V)
TLlF/6681-9
FIGURE 8. Typical Supply Current vs Supply Voltage during Power Down
2-117
Operating Conditions MM58174AN
TA
=
-40°C to 85°C, Voo
=
5V
TABLE IV. Read Timing: Data from Peripheral to Microprocessor
Symbol
MM58174AN
Parameter
Min
=
tAcsa
Address Bus Valid to Chip Select ON (CS
tCSR
Chip Select ON to Read Strobe
tRO
Read Cycle Access Time from
Read Strobe to Data Bus Valid
tRH
Data Hold Time from Trailing Edge of
Read Strobe
0
tRA
Address Bus Hold Time from
Trailing Edge of Read Strobe
70
tACS1
Address Change to Chip Select OFF
0
tAO
Address Bus Valid to Data Valid
tHZ
Time from Trailing Edge of Read
Strobe until Interface Device Bus
Drivers are in TRI-STATE® Mode
tRW
Read Strobe Width
tAR
Address Bus Valid to Read Strobe
0)
Typ
Units
0
ns
0
ns
900
450
330
1850
0
Comments
' Max
ns
CL
=
100 pF
CL
=
100 pF
ns
500
ns
40
ns
850
ns
330
ns
14
,..,s
500
ns
Note 1: In order not to degrade timekeeping accuracy, the number of Read strobes in anyone second should be less than 10,000.
Note 2: If address and read occur simultaneously then they must exist for tAR
+
tAD,
TABLE V. Write Timing: Data from Microprocessor to Peripheral
Symbol
MM58174AN
Parameter
Min
=
0)
Typ
Units
Max
tAcsa
Address Bus Valid to Chip Select ON (CS
tcsw
Chip Select ON to Write Strobe
0
tAW
Address Bus Valid to Write Strobe
725
ns
tww
Write Strobe Width
670
ns
0
ns
450
ns
tow
Data Bus Valid before Write Strobe
70
ns
tWA
Address Bus Hold Time following Write Strobe
165
ns
two
Data Bus Hold Time following Write Strobe
185
ns
tACS1
Address Change to Chip Select OFF (CS
0
ns
=
1)
Note 3: If address and write occur simultaneously, then they must exist for tAW and tww.
2-118
Comments
~National
U
Semiconductor
MM581678
Microprocessor Real Time Clock
General Description
The MM581678 is a low threshold metal gate CMOS circuit
that functions as a real time clock in bus oriented microprocessor systems. The device includes an addressable real
time counter, 56 bits of RAM, and two interrupt outputs. A
POWER DOWN input allows the chip to be disabled from
the rest of the system for standby low power operation. The
time base is a 32.768 Hz crystal oscillator.
Features
• 56 bits of RAM with comparator to compare the real
time counter to the RAM data
• 2 INTERRUPT OUTPUTS with 8 possible interrupt signals
• POWER DOWN input that disables all inputs and outputs except for one of the interrupts
• Status bit to indicate rollover during a re~d
• 32.768 Hz crystal oscillator
• Four-year calendar (no leap year)
• 24-hour clock
• Microprocessor compatible (8-bit data bus)
• Milliseconds through month counters
Connection Diagrams
Dual-In-Line Package
cs
RB
2
PCC Package
24
Voo
23
POWER DOWN
I~ I~ I~
ViR
3
07
ROY
ROY
4
06
AO
AO
5
05
AI
AI
6
04
N/c
A2
7
A3
8
03
A2
17
02
A3
16
01
A4
15
DO
OSC OUT
14
Vss
13
STANDBY INTERRUPT
INTERRUPT
OUTPUT
A4
OSC IN
10
~ ~I~
~
25
06
05
04
N/C
03
02
19
01
12
~
l-
(,)
I-
::J
0
V!
~""""::J
z 0
(,)
c:
0
V!
0
TLlF/6148-1
V)
(,)
~
~
Top View
ao:
.....
I-
0
Q
~
>m
Q
:z
lV!
TL/F/6148-2
Order Number MM58167BN
See NS Package Number N24A
Top View
Order Number MM58167BV
See NS Package Number V28A
2-119
III
......
(D
,...
co
LI)
:::E
:::E
Absolute Maximum Ratings
Storage Temperature
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Voltage at All Pins
Vss - 0.3V to Voo + 0.3V
Operating Temperature
O°C to 70°C
- 65°C to
Voo-Vss
Lead Temperature (Soldering, 10 sec.)
ESD rating is to be determined.
+ 150°C
6.0V
300°C
Electrical Characteristics Vss = OV, O°C ~ TA :S: 70°C
Parameter
Supply Voltage
Voo
Voo
Supply Current
100, Dynamic
100, Dynamic
Conditions
Min
Max
Units
Outputs Enabled
' POWER 50WN Mode
4.5
2.2
5.5
5.5
V
V
20
/-LA
5
mA
0.0
2.0
0.8
Voo
V
V
-1
1
/-LA
0.4
1
V
V
V
/-LA
0.4
10
V
/-LA
Outputs TRI-STATE@
fiN = 32.768 kHz, Voo
VIH ~ Voo - 0.3V
VIL :S: Vss + 0.3V
= 5.5V
Outputs TRI-STATE
fiN = 32.768 kHz, Voo = 5.5V
VIH = 2.0V, VIL = 0.8V
Input Voltage
Logical Low
Logical high
Input Leakage Current
Vss :S: VIN :S: Voo
Output Impedance
Logical Low
Logical High
1/0 and INTERRUPT OUT
Voo = 4.5V, IOL = 1.6 mA
Voo = 4.5V, IOH = -400 /-LA
IOH = -10/-LA
Vss :S: VOUT :S: Voo
TRI-STATE
Output Impedance
Logical Low, Sink
Logical High, Leakage
RDY and STANDBY INTERRUPT
(Open Drain Devices)
Voo = 4.5V, IOL = 1.6 mA
VOUT:S: Voo
2-120
2.4
0.8 Voo
-1
Functional Description
The unused bits in the real time counter will compare only to
zeros in the RAM.
Real Time Counter
The real time counter is divided into 4-bit digits with 2 digits
being accessed during any read or write cycle. Each digit
represents a BCO number and is defined in Table I. Any
unused bits are held at a· logical zero during a read and
ignored during a write. An unused bit is any bit not necessary to provide a full BCO number. For example tens of
hours cannot legally exceed the number 2, thus only 2 bits
are necessary to define the tens of hours. The other 2 bits in
the tens of hours digit are unused. The unused bits are designated in Table I as dashes.
An address map is shown in Table III.
Interrupts and Comparator
There are two interrupt outputs. The first is the INTERRUPT
OUTPUT (a true high signal). This output can be programmed to provide 8 different output signals. They are:
10Hz, once per second, once per minute, once per hour,
once a day, once a week, once a month, and when a RAM/
real time counter comparison occurs. To enable the output
a one is written into the interrupt control register at the bit
location corresponding to the desired output frequency (Figure 1). Once one or more bits have been set in the interrupt
control register, the corresponding counter's rollover to its
reset state will clock the interrupt status register and cause
the interrupt output to go high. To reset the interrupt and to
identify which frequency caused the interrupt, the interrupt
status register is read. Reading this register places the contents of the status register on the data bus. The interrupting
frequency will be identified by a one in the respective bit
position. Removing the read will reset the interrupt.
The addressable portion of the counter is from milliseconds
to months. The counter itself is a ripple counter. The ripple
delay is less than 60 J1-s above 4.5V and 300 J1-s at 2.2V.
RAM
56 bits of RAM are contained on-chip. These can be used
for any necessary power down storage or as an alarm latch
for comparison to the real time counter. The data in the
RAM can be compared to the real time counter on a digit
basis. The only digits that are not compared are the unit ten
thousandths of seconds and tens of days of the week
(these are unused in the real time counter). If the two most
significant bits of any RAM digit are ones, then this RAM
location will always compare. The rule of thumb for an
"alarm" interrupt is: All nibbles of higher order than specified are set to C hex (always compare). All nibbles lower
than specified are set to "zero". As an example, if an alarm
is to occur everyday at 10: 15 a.m., configure the bits in RAM
as shown in Table II.
The second interrupt is the STANOBY INTERRUPT (open
drain output, active low). This interrupt occurs when enabled
and when a RAM/real time counter comparison occurs. The
ST ANOBY INTERRUPT is enabled by writing a one on the
00 line at address 16H or disabled by writing a zero on the
00 line. This interrupt is not triggered by the edge of the
compare signal, but rather by the level. Thus if the compare
is enabled when the STANOBY INTERRUPT is enabled, the
interrupt will turn on immediately.
The RAM is formatted the same as the real time counter, 4
bits per digit, 14 digits, however there are no unused bits.
TABLE I. Real Time Counter Format
Units
Counter Addressed
Milliseconds
Hundredths and Tenths Sec
Seconds
Minutes
Hours
Oay of the Week
Oay of the Month
Month
DO
(OOH)
(01H)
(02H)
(03H)
(04H)
(05H)
(06H)
(07H)
D1
D2
D3
-
-
-
-
00
00
00
00
00
00
00
01
01
01
01
01
01
01
02
02
02
02
02
02
02
03
03
03
03
( ) indicates unused bits
2-121
03
03
Max
BCD
Code
0
9
9
9
9
7
9
9
Tens
D4
D5
D6
D7
04
04
04
04
04
05
05
05
05
05
06
06
06
06
07
07
-
-
04
04
05
-
-
-
Max
BCD
Code
9
9
5
5
2
0
3
1
Functional Description
(Continued)
TABLE II. Clock RAM Bit Map for Alarm Interrupt Everyday at 10:15 a.m.
Data
Address
Function
HI Nibble
Lo Nibble
4
3
2
1
0
7
6
5
4
Milliseconds
0
1
0
0
0
0
0
0
0
Hundredths and
Tenths of Seconds
0
1
0
0
1
0
0
0
0
0
0
0
0
Seconds
0
1
0
1
0
0
0
0
0
0
0
0
0
Minutes
0
1
0
1
1
0
0
0
1
0
1
0
1
Hours
0
1
1
0
0
0
0
0
1
0
0
0
0
Day of Week
0
1
1
0
1
1
1
X
X
Day of Month
0
1
1
1
0
1
1
X
X
1
1
X
X
Months
0
1
1
1
1
1
1
X
X
1
1
X
X
No RAM Exists
3
2
1
0
No RAM Exists
TABLE III. Address Codes and Function
A4
A3
A2
A1
AO
Function
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Counter-Milliseconds
Counter-Hundredths and Tenths of Seconds
Counter-Seconds
Counter-Minutes
Counter-Hours
Counter-Day of Week
Counter-Day of Month
Counter-Month
RAM-Milliseconds
RAM-Hundredths and Tenths of Seconds
RAM-Seconds
RAM-Minutes
RAM-Hours
RAM-Day of Week
RAM-Day of Month
RAM-Months
Interrupt Status Register
Interrupt Control Register
Counters Reset
RAM Reset
Status Bit
GOComand
STANDBY INTERRUPT
Test Mode
All others unused
The comparator is a cascaded exclusive NOR. Its output is
latched 61 p,s after the rising edge of the 1 kHz clock signal
(input to the milliseconds counter). This allows the counter
to ripple through before looking at the comparator. For operation at less than 4.5V, the thousandths of seconds counter
should not be included in a compare because of the possibility of having a ripple delay greater than 61 p,s. (For output
timing see Interrupt Timing.)
Power Down Mode
The POWER DOWN input is essentially a second chip select. It disables all inputs and outputs except for the
STANDBY INTERRUPT. When this input is at a logical zero,
the device will not respond to any external signals. It will,
however, maintain timekeeping and turn on the STANDBY
INTERRUPT if programmed to do so. (The programming
must be done before the POWER DOWN input goes to a
2-122
Functional Description
(Continued)
logical zero.) When switching VOO to the standby or power
down mode, the POWER DOWN input should go to a logical
zero at least 1 }-ts before VOD is switched. When switching
VOO all other inputs must remain between Vss - 0.3V and
VOO + 0.3V. When restoring Voo to the normal operating
mode, it is necessary to insure that all other inputs are at
valid levels before switching the POWER DOWN input back
to a logical one. These precautions are necessary to insure
that no data is lost or altered when changing to or from the
power down mode.
If a sequential read of the clock counters is made, then the
rollover status bit should be read after the last counter is
read.
Example: Read hours, minutes, seconds, then read the rollover status.
Oscillator
The oscillator used in the standard Pierce parallel resonant
oscillator. Externally, 2 capacitors, a 20 MO resistor and the
crystal are required. The 20 MO resistor is connected between OSC IN and OSC OUT to bias the internal inverter in
the linear region. For micropower crystals a resistor in series
with the oscillator output may be necessary to insure the
crystal is not overdriven. This resistor should be approximately 200 kO. The capacitor values should be typically
20 pF-25 pF. The crystal frequency is 32,768 Hz.
Counter and RAM Resets; GO Command
The counters and RAM can be reset by writing all1's (FF) at
address 12H or 13H respectively.
A write pulse at address 15H will reset the thousandths,
hundredths, tenths, units, and tens of seconds counters.
This GO command is used for precise starting of the clock.
The data on the data bus is ignored during the write. If the
seconds counter is at a value greater than 39 when the GO
is issued, the minute counter will increment; otherwise the
minute counter is unaffected. This command is not necessary to start the clock, but merely a convenient way to start
precisely at a given minute.
The oscillator input can be externally driven, if desired. In
this case the oscillator output should be left floating and the
oscillator input levels should be within 0.3V of the supplies.
A ground line or ground plane between pins 9 and 10 may
be necessary to reduce interference of the oscillator by the
A4 address.
Control Lines
Status Bit
The READ, WRITE, AND CHIP SELECT signals are active
low inputs. The READY signal is an open drain output. At
the start of each read or write cycle the READY line (open
drain) will pull low and will remain low until valid data from a
chip read appears on the bus or data on the bus is latched
in during a write. READ and WRITE must be accompanied
by a CHIP SELECT (see Figures 3 and 4 for read and write
cycle timing).
The status bit is provided to inform the user that the clock is
in the process of rolling over when a counter is read. The
status bit is set if this 1 kHz clock occurs during or after any
counter read. This tells the user that the clock is rippling
through the real time counter. Because the clock is rippling,
invalid data may be read from the counter. If the status bit is
set following a counter read, the counter should be reread.
The status bit appears on DO when address 14H is read. All
the other data lines will zero. The bit is set when a logical
one appears. This bit should be read every time a counter
read or after a series of counter reads are done. The trailing
edge of the read at address 14H will reset the status bit.
During a read or write, address bits must not change while
chip select and control strobes are low.
Test Mode
The test mode is for production testing. It allows the counters to count at a higher than normal rate. In this mode the
32.768 kHz oscillator input is connected directly to the ten
thousandths of seconds counter. The chip select and write
lines must be low and the address must be held at 1 FH.
Using the Rollover Status Bit
If a single read of any clock counter is made, it should be
followed by reading the rollover status bit.
Example: Read months, then read rollover status.
DO
01
02
03
04
D5
06
07
,.......J.......,.-.L-""T"......L--r-...&..--,r--~-r----:I;-"T""-7.:-r-~..., INTERRUPT
WRITE
ONLY
CONTROL
REGISTER
L...--ir-.-L--:r...L.--r-.L...-T-JL-.--T-L.-,..-'--.y.-......-,r' ADDRESS=ll H
l/MIN
--f---+--+---,
l/SEC
---1---+-.,
10/SEC
.--I---f.---+---~ I/HOUR
..--I---+--~ l/DAY
-~I--.
r--t---+-l/WEEK
COMPARE
l/MONTH
,....JL.....JL.....,-L.-L...,..-'--'-.,...~~~~"""T~~"T'"~~r-:~~
READ
ONLY
L-...;:..;;....L-;:-..L-T~.L...-r-.....J'---r--L.-----:r-..I..-r-.......,...-
INTERRUPT
STATUS
REGISTER
ADDRESS=l 0H
L----------I INTERRUPT
LOGIC
INTERRUPT
OUTPUT
(ACTIVE
LOGIC HIGH)
TLIF/6148-3
FIGURE 1. Interrupt Register Format
2-123
Functional Description
(Continued)
Typical Supply Current
vs Supply Voltage
during Power Down
Standby Interrupt
Typical Characteristics
1.5
14
1.0
!
I::;)
_0
:/1
0.0
/
/
~
~
12
..S>
u
10
0
:i
4(
~
6
~
4
/
/
,,-/
V
2
0.5
1.0
0
1.5
I
/
1/
8
-l
~
I
II
1
2
/
4
3
5
6
Voo (V)
Your (V)
TLlF/6148-5
TLlF/6148-4
FIGURE 2
Interrupt Timing
O°C ~ TA ~ 70°C,4.5V ~ VOO ~ 5.5V, Vss == OV
Max
Units
tiNTON
Status Register Clock to INTERRUPT OUTPUT
(Pin 13) High (Note 1)
5
p's
tSBYON
Compare Valid to STANDBY INTERRUPT
(Pin 14) Low (Note 1)
5
p.s
tlNTOFF
Trailing Edge of Status Register
Read to INTERRUPT OUTPUT Low
5
p.s
Symbol
Parameter
Min
Trailing Edge of Write Cycle
(DO = 0; Address = 16H)tO STANDBY
5
p's
INTERRUPT Off (High Impedance State)
Note 1: The status register clocks are: the corresponding counter's rollover to its reset state or the compare becoming valid. The compare becomes valid 61 II-s
after the 1/10,000 of a second counter is clocked, if the real time counter data matches the RAM data.
tSBYOFF
Read Cycle Timing
Symbol
O°C ~ TA ~ 70°C, 4.5V ~ VOO ~ 5.5V, VSS = OV
Min
Parameter
Max
Units
ns
tAR
Address Bus Valid to Read Strobe (Note 3)
100
tCSR
Chip Select to Read Strobe (Note 2)
tRRY
Read Strobe to Ready Strobe
150
ns
tRYO
Ready Strobe to Data Valid
800
ns
tAD
Address Bus Valid to Data Valid
1050
tRH
Data Hold Time from Trailing Edge of Read Strobe
tHZ
Trailing Edge of Read Strobe to TRI·STATE Mode
tRYH
Read Hold Time after Ready Strobe
0
ns
tRA
Address Bus Hold Time from Trailing Edge of Read Strobe
50
ns
ns
0
0
250
100
Rising Edge of Ready to Data Valid
tRYOV
Note 2: When reading, a deselect time of 500 ns minimum must occur between counter reads. Deselect is: "CS = 1 or (Wl1) • (REi) = 1.
Note 3: If tAR = 0 and Chip Select, Address Valid or Read are coincident then they must exist for 1050 ns.
2·124
ns
ns
ns
ns
Write Cycle Timing o·c ~ TA ~ 70·C, 4.5V ~ Voo ~ 5.5V, Vss =
Symbol
Parameter
OV
Min
tAW
Address Valid to Write Strobe
tcsw
Chip Select to Write Strobe
tow
Data Valid before Write Strobe
tWRY
Write Strobe to Ready Strobe
Max
Units
100
ns
0
ns
100
ns
150
tRY
Ready Strobe Width
tRYH
Write Hold Time after Ready Strobe
ns
800
ns
0
ns
two
Data Hold Time after Write Strobe
110
ns
tWA
Address Hold Time after Write Strobe
50
ns
Note 4: If data changes while ~ and \tffi are low, then they must remain coincident for 1050 ns after the data change to ensure a valid write. Data bus loading is
100 pF. Ready output loading is 50 pF and 3 kn pull-up.
Input and output AC timing levels:
Logical one = 2.0V
Logical zero = o.sv
Read and Write Cycle Timing Diagrams
AO-A4
X
X
ADDRESS VALID
I--tAR-+
cs
..... t RRy -
I--tcSR -
I-- tRA -
\
Ri5
/
.. t
\
ROY
-I.
RyH
f4- tRyoy
t RyO
,J
00-07
_
tAD
!-t
RH -
DATA VALID}
f-t HZ TL/F/6148-6
FIGURE 3. Read Cycle Timing
AO-A4
X
X
ADDRESS VALID
I'
r-- tWA--l
tAW
cs
I-t
-t
_tWRY -
csw -
I_ two _
\
WR
RyH -
_tRY_
ROY
,t
00-07
,,
Dw -
~
/
DATA VALID
,
J
TL/F/6148-7
FIGURE 4. Write Cycle Timing
2-125
m
,...
I'
CD
co
it)
:E
:E
Typical Applications
SYSTEt.l
ADDRESS BUS
SYSTEt.l DATA
BUS
AS
+ STANDBY
CHIP
SELECT
LOGIC
A6
A7
BATTERY
CS
AO
RD·
ViR
ViR
ROY
D7
AD
D5
RDY
Al
A3
8
A4
9 .
NOTE 4
10
Rl
11
lk
3V:tl0%
D4
t.lt.l58167B
A2
D3
A3
D2
A4
Dl
OSC IN
DO
STDBY
OSC OUT
12
R2
N2DDk
(OPTIONAL)
5V
PWR DOWN (rROt.l SYSTEt.l)
D6
Al
A2
2N2907
24
VDD
PWR DOWN
RD
.I: 3V
lOOk
lN4148
5k
16
14
13
INT
VSS
-
15
iNT
(OPERATIONAL DURING
PWR DOWN CONDITION)
Rl = 20 MO ±20%
Cl = 6 pF - 36 pF
R2 to be selected
based on crystal used.
SYSTEt.l
INTERRUPT
(NORt.lAL POWER ON
SYSTEt.l INTERRUPT)
Cl
TL/F/614B-B
Note 5: A ground line or ground plane guard lrace should be included between pins 9 and 10 to insure the oscillator is not disturbed by the address line.
FIGURE 5. Typical Connection Diagram
SYSTEt.l
ADDRESS BUS
+ STANDBY
5V
lOOk
A5-A7
24
cs
WAIT
-=- BATIERY
.l:
3V
24
Voo=5V
16
1.
AO-AI5 25-40
AO-Ao4
5-9
16
13
-=
-5V
11
22
15
8080
01
ViR
02
DBIN
10
.2
HDLA
12
14
9
18
HOLD
INTE
READY
00-07
INT
23
14
16
Rli
ViR
DB IN
HLDA
32kHz
11
14
12
INT
OUT
13
3-10
Ne
I
~opr
-=
ROY
4
00-07
~P
25
DATA
BUS
BUSEN
OSC IN
t.lt.458167B
00-07
ViR
17
21
AO-A4
OSC OUT
RESET
19 SYNC
8224
16
15-22
SYSTEt.l
DATA BUS
10
22
INTA
INTERRUPT
READY
20k
VOD
TLlF/614B-9
Note 6: Must use 8238 or equivalent logiC to insure advanced IIOW pulse; so that the ready output of the MM58167B is valid by the end of <1>2 during the T2
microcycle.
Note 7:
t2 ;;, tAS80BO
+
tDL8238
+
tWAY5BI67S·
FIGURE 6. 8080 System Interface with Battery Backup
2-126
Block Diagram
8 BITS
OSC IN
OSC OUT
Rii
ROY
ViR
DO
01
02
03
8-BIT BI-DIRECTIONAL BUS
0-4
05
06
RO"CS
07
WR"CS
ADDRESS DECODES
19 ADDRESSES
2 RESETS
2 SPECIAL COMMANDS
1 TEST MODE
CS
POWER
DOWN
AO
AI
A2
ADDRESS
INPUT
ADDRESS
DECODER
A3
A-4
TLlF/6148-10
FIGURE 7
2-127
,...
,...
2 ~National
~
z
D
Semiconductor
NS32FX211 Microprocessor Compatible Real Time Clock
General Description
Features
The NS32FX211 is fabricated using low threshold CMOS
technology and is designed to operate in bus oriented microprocessor systems where a real time clock and calendar
function are required. The on-chip 32.768 kHz crystal controlled oscillator will maintain timekeeping down to 2.2V to
allow low power standby battery operation.
• Low power standby operation (10 j.LA at 2.2V)
• 16-pin DIP and 20-pin PLCC
• Timekeeping from tenths to seconds to tens of years in
independently accessible registers
• Leap year register
• Hours counter programmable for 12 or 24-hour
operation
• Fully TTL/CMOS compatible
Applications
•
•
•
•
•
Fax machines
Laser printers
Word processors
Data logging
Industrial process control
Connection Diagrams
Dual·ln·Llne Package
PCC Package
CS
voo
iiii
XTALIN
=
10 I'" c ~
I~1Xc.»c~
IX
Wii
XTAL OUT
oB3
iNi
Hie
Hie
oB2
ADO
083
Hie
DB2
ADO
Hie
AD1
oBl
Aol
oBO
AD2
Vss
A03
XTAL OUT
IHT
TL/F/ll011-2
TLlF/ll0ll-l
Top View
FIGURE 1
Order Number NS32FX211N, NS32FX211V
See NS Package Number N16A or V20A
2·128
z
I
I
(Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
DC Input or Output Voltage .
-0.3V to Voo +0.3V
±5.0 rnA
DC Input or Output Diode Current
Storage Temperature, (TSTG)
- 65°C to + 150°C
6.5V
Supply Voltage, (Voo)
Power Dissipation, (Po)
500mW
Lead Temperature
260°C
(Soldering, 10 seconds)
Electrical Characteristics Voo =
Symbol
en
w
Operating Condit"ions
Absolute Maximum Ratings
Operating Supply Voltage
Standby Mode Supply Voltage
DC Input or Output Voltage
Operating Temperature Range
Min
4.75
2.2
0
0°
Max
5.25
5.5
Voo
70°
Units
V
V
V
°C
5V ± 5%. T = O°C to + 70°C unless otherwise stated
Parameter
Conditions
Min
Typ
Max
Units
VIH
High Level Input Voltage
(except XTAL IN)
VIL
Low Level Input Voltage
(except XTAL IN)
VOH
High Level Output Voltage
(080-083)
IOH = -20 p.A
IOH = -1.6 rnA
Voo - 0.1
3.7
V
V
VOH
High Level Output
Voltage (INT)
IOH = -20 p.A
(In Test Mode)
Voo - 0.1
V
VOL
Low Level Output Voltage
(080-083, INn
IOL = 20 p.A
IOL = 1.6 rnA
IlL
Low Level Input Current
(ADO-AD3, 080-083)
VIN = Vss (Note 2)
IlL
Low Level Input Current
(WR.RD)
VIN = Vss (Note 2)
IlL
Low Level Input
Current (CS)
VIN = Vss (Note 2)
IOZH
Output High Level
Leakage Current (INn
VOUT
100
Average Supply Current
All VIN = Vee or Open Circuit
Voo = 2.2V (Standby Mode)
Voo = 5.0V (Static Mode)
CIN
Input Capacitance
COUT
Output Capacitance
2.0
V
0.8
0.1
0.4
V
V
-5
-90
p.A
-5
-200
p.A
-5
-570
p.A
2.0
p.A
4
10
1
p.A
rnA
5
10
pF
= Voo
(Outputs Disabled)
V
10
pF
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur. All voltages referenced to ground unless otherwise noted.
Note 2: The DBO-DB3 and ADO-AD3 lines all have active P·channel pull·up transistors which will source current. The ~, RO, and WR lines have internal pull·up
resistors to Voo.
2-129
N
."
><
N
...A.
...A.
....
....
N
><
LL.
N
C")
AC Switching Characteristics
READ TIMING: DATA FROM PERIPHERAL TO MICROPROCESSOR Voo = 5V ± 5%, CL = 100 pF
tJ)
Commercial Specification
Z
Units
TA = DOC to +75°C
Parameter
Symbol
Min
Typ
Max
tAD
Address Bus Valid to Data Valid
390
650
ns
tcso
Chip Select On to Data Valid
140
300
ns
tRO
Read Strobe On to Data Valid
140
300
ns
DC
ns
tRW
Read Strobe Width (Note 3, Note 7)
300
tRA
Address Bus Hold Time from Trailing
Edge of Read Strobe
0
ns
tCSH
Chip Select Hold Time from Trailing
Edge of Read Strobe
0
ns
tRH
Data Hold Time from Trailing
Edge of Read Strobe
70
tHZ
Time from Trailing Edge of Read Strobe
Unitl alP Drivers are TRI-STATE®
ns
160
250
ns
WRITE TIMING: DATA FROM MICROPROCESSOR TO PERIPHERAL Voo = 5V ± 5%
Commercial Specification
TA = DOC to +7DoC
Parameter
Symbol
Units
Min
Typ
400
125
ns
Chip Select On to Write Strobe
250
100
ns
tow
..r
Data Bus Valid to Write Strobe ..r
400
220
ns
tww
Write Strobe Width (Note 6)
250
95
ns
twcs
Chip Select Hold Time Following
Write Strobe
0
ns
tWA
Address Bus Hold Time Following
Write Strobe
0
ns
two
Data Bus Hold Time Following
Write Strobe
100
35
ns
tAWS
Address Bus Valid before
Start or Write Strobe
70
20
ns
tAw
Address Bus Valid to Write Strobe
(Note 4, Note 6)
tcsw
..r
..r
..r
..r
Max
Note 3: Except for special case restriction: with interrupts programmed, max read strobe width of control register (ADDR 0) is 30 ms. See section on Interrupt
Programming.
Note 4: All timings measured to the trailing edge of write strobe (data latched by the trailing edge of
WR).
Note 5: Input test waveform peak voltages are 2.4V and O.4V. Output signals are measured to their 2.4V and O.4V levels.
Note 6: Write stobe as used in the Write Timing Table is defined as the period when both chip select and write inputs are low, ie., WS,
strobe commences when both signals are low, and terminates when the first signal returns high.
Note 7: Read strobe as used in the Read Timing Table is defined as the period when both chip select and read inputs are low, ie.,
Note 8: Typical numbers are at Vee
=
5.0V and TA
=
25°C.
2-130
= cs + WR. Hence write
AS = ~ + RD.
I
z
en
Switching Time Waveforms
w
N
"T1
Read Cycle Timing (Notes 5 and 7)
.r-----------------~
Al-AD
ADDRESS VALID
,..----
1'-------------------'1
'---f+-----ItSD----.j
><
N
.....
.....
2.4V
D.4V
2.4V
Ir-------
iiii
2.4V
----+---,-/------- D.4V
D3-DD - - - + - - - - - - - - - - - C l
I~--------~D-------~
TUF/11011-3
Write Cycle Timing (Notes 5 and 6)
.r-----------------~
A3-AD
_---
1'------------------"1 ,,--ADDRESS VALID
2.4V
D.4V
~---------Itsw----------~--
2.4V
1 - - - - ~WS----_J_o---
I----~------~
D3-DO ---+-----~~I
DATA VALID
I~------------~W-----------~
TlIF/11011-4
FIGURE 2
Functional Description
Johnson counter divides this by six, generating a 10Hz output. The 10 Hz clock is gated with the 32.768 kHz crystal
frequency to provide clock setting pulses of 15.26 p,s duration.The setting pulse drives all the time registers on the
device which are synchronously clocked by this signal. All
time data and data-changed flag change on the falling edge
of the clock setting pulse.
The NS32FX211 is a bus oriented microprocessor real time
clock.
Crystal Oscillator
This consists of a CMOS inverter/amplifier with an on-chip
bias resistor. Externally a 22 pF capacitor, a 6 pF-40 pF
trimmer capacitor and a crystal are suggested to complete
the 32.768 kHz timekeeping oscillator circuit.
Data-Changed Flag
The 6 pF-40 pF trimmer fine tunes the crystal load impedance, optimizing the oscillator stability. When properly adjusted (Le., to the crystal frequency of 32.768 kHz), the circuit will display a frequency variation with voltage of less
than 3 ppmlV. When an external oscillator is used, connect
to oscillator input and float (no connection) the oscillator
output.
The data-changed flag is set by the clock setting pulse to
indicate that the time data has been altered since the clock
was last read. This flag occupies bit 3 of the control register
where it can be tested by the processor to sense datachanged. It will be reset by a read of the control register.
See the section, "Methods of Device Operation", for suggested clock reading techniques using this flag.
When the chip is enabled into test mode, the oscillator is
gated onto the interrupt output pin giving a buffered oscillator output that can be used to set the crystal· frequency
when the device is installed in a system.
Seconds Counters.
There are three counters for seconds:
a. tenths of seconds
Divider Chain
b. units of seconds
The crystal oscillator is divided down in three stages to produce a 10Hz frequency setting pulse. The first stage is a
non-integer divider which reduces the 32.768 kHz input to
20.720 kHz. This is further divided by a 9-stage binary ripple
counter giving an output frequency of 60 Hz. A 3-stage
c. tens of seconds
The registers are accessed at the addresses shown in Table I. The tenths of seconds register is reset to 0 when the
clock start/stop bit (bit 2 of the control register) is set to
2-131
.....
.....
e\!
><
Functional Description
(Continued)
Lle\!
Cf)
en
EXTERNAL
POWER FAil
SIGNAL
z
r---------------------~----~--._--_4~--~5V
100 nF
DISK
D2
3.6V
+
-=-=-
BAn
3VNOM
R4
220n
R3
10 k
OV
·RCH only used for
recharageable batteries
AD2
ADl
ADO
TL/F/11011-5
FIGURE 3. Typical System Connection Diagram
logic 1. The units and tens of seconds are set up by the
processor, giving time setting to the nearest second. All
three registers can be read by the processor for time output.
of the clock setting register, logic 0 for 12-hour mode, logic
1 for the 24-hour mode.
Minutes Counters
There are two days counters:
There are two minutes counters:
a. units of day
Days Counters
a. units of minutes
b. tens of days
b. tens of minutes
The days counters will count up to 28, 29, 30 or 31 depending on the state of the months counters and the leap year
counter. The microprocessor has full read/write access to
these registers.
Both registers may be read to or written from as required.
Hours Counters
There are two hours counters:
Months Counters
a. units of hours
There are two months counters:
b. tens of hours
a. units of months
Both counters may be accessed for read or write operations
as desired.
b. tens of months
Both these counters have full read/write access.
In 12-hour mode, the tens of hours register has only one
active bit and the top three bits are set to logic O. Data bit 1
of the clock setting register is the AM/PM indicator; logic 0
indicating AM, logic 1 for PM.
Years Counters
There are two years counters:
a. units of years
When 24-hour mode is programmed, the tens of hours register reads out two bits of data and the two most significant
bits are set to logic O. There is no AM/PM indication and bit
1 of the clock setting register will read out a logic O.
b. tens of years
Both these counters have full read/write access. The years
will count up to 99 and roll over to 00.
In both 12/24-hour modes, the units of hours will read out
four active data bits. 12 or 24-hour mode is selected by bit 0
2-132
z
Functional Description
en
Cot)
(Continued)
N
."
><
N
TABLE I. Address Decoding of Real-Time Clock Internal Registers
Address (Binary)
Registered Select
AD3
AD2
AD1
ADO
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
·0
.0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
o Control Register
1 Tenths of Seconds
2 Units Seconds
3 Tens Seconds
4 Units Minutes
5 Tens Minutes
6 Unit Hours
7 Tens Hours
8 Units Days
9 Tens Days
10 Units Months
11 Tens Months
12 Units Years
13 Tens Years
14 Days of Week
15 Clock Settingl
Interrupt Registers
(Hex)
Access
0
1
2
3
4
5
6
Split Read and Write
Read Only
7
8
9
A
B
C
D
E
F
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
The AM/PM indicator returns a logic 0 for AM and a logic 1
for PM. It is clocked when the hours counter rolls from 11 :59
to 12:00 in 12-hour mode. In 24-hour mode this bit is set to
logic o.
Day of Week Counter
The day of week counter increments as the time rolls from
23:59 to 00:00 (11 :59 PM to 12:00 AM in 12-hour mode). It
counts from 1 to 7 and rolls back to 1. Any day of the week
may be specified as day 1.
The 12/24-hour mode set determines whether the hours
counter counts from 1 to 12 or from 0 to 23. It also controls
the AM/PM indicator, enabling it for 12-hour mode and forcing it to logic 0 for the 24-hour mode. The 12/24-hour mode
bit is set to logic 0 for 12-hour mode and it is set to logic 1
for 24-hour mode.
Clock Setting Register/Interrupt Register
The interrupt select bit in the control register determines
which of these two registers is accessible to the processor
at address 15. Normal clock and interrupt timing operations
will always continue regardless of which register is selected
onto the bus. The layout of these registers is shown in Table
IMPORTANT NOTE: Hours mode and AM/PM bits cannot
be set in the same write operation. See the section on Initialization (Methods of Device Operation) for a suggested
setting routine.
II.
The clock setting register is comprised of three separate
functions:
All bits in the clock setting register may be· read by the processor.
a. leap year counter: bits 2 and 3
b. AM/PM indicator: bit 1
The interrupt register controls the operation of the timer for
interrupt output. The processor programs this register for
single or repeated interrupts at the selected time intervals.
c. 12/24-hour mode set: bit 0 (see Table lIA).
The leap year counter is a 2-stage binary counter which is
clocked by the months counter. It changes state as the time
rolls over from 11 :59 on December 31 to 00:00 on January
The lower three bits of this register set the time delay period
that will occur between interrupts. The time delays that can
be programmed and the data words that select these are
outlined in Table liB.
1.
The counter should be loaded with the 'number of years
since last leap year' e.g., if 1980 was the last leap year, a
clock programmed in 1983 should have 3 stored in the leap
year counter. If the clock is programmed during a leap year,
then the leap year counter should be set to O. The contents
of the leap year counter can be read by the JLP.
Data bit 3 of the interrupt register sets for either single or
repeated interrupts; logic 0 gives single mode, logic 1 sets
for repeated mode.
Using the interrupt is described in the Device Operation section.
2-133
......
......
.....
.....
N
><
Functional Description
LL
N
(Continued)
TABLE IIA. Clock Setting Register Layout
~
U)
Z
Data Bits Used
Function
Leap Year Counter
AM/PM Indicator (12-Hour Mode)
DB3
DB2
x
x
Comments
Access
oIndicates a Leap Year
0= AM 1 = PM
o in 24-Hour Mode
o = 12-Hour Mode
1 = 24-Hour Mode
R/W
R/W
DBD
DB1
x
x
12/24-Hour Select Bit
. R/W
TABLE liB. Interrupt Control Register
Function
No Interrupt
0.1 Second
0.5 Second
1 Second
5 Seconds
10 Seconds
30 Seconds
60 Seconds
Control Word
Comments
Interrupt Output Cleared,
Start/Stop Bit Set to 1.
DB3 = 0 for Single Interrupt
DB3 = 1 for Repeated Interrupt
DB3
DB2
DB1
DBD
X
0
0
0
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0
0
0
1
1
1
1
0
1
1
0
0
1
1
1
0
1
0
1
0
1
Timing Accuracy: Single Interrupt Mode (all time delays): ± 1 ms
Repeated Mode: ± 1 ms on Initial Timeout, Thereafter Synchronous with First Interrupt (i.e, timing errors do not
accumulate).
'
Control Register
There are three registers which control different operations
of the clock:
a. the clock setting register
b. the interrupt register
c. the control register
A logic 1 written into the test bit puts the device into test
mode. This allows setting of the oscillator frequency. For
normal operation the test bit is loaded with logic O.
The clock start/stop bit stops the timekeeping of the clock
and resets to 0 the tenths of seconds counter. The time of
day may then be written into the various clock registers and
the clock restarted synchronously with an external. time
source. Timekeeping is maintained thereafter.
A logic 1 written to the start/stop bit halts clock timing. Timing is restarted when the start/stop bit is written with a logic
The clock setting and interrupt registers both reside at address 15, access to one or the other being controlled by the
interrupt select bit; data bit 1 of the control register.
The clock setting register programs the timekeeping of the
clock. The 12/24-hour mode select and the AM/PM indica~
tor for 12-hour mode occupy bits 0 and 1, respectively. Data
bits 2 and 3 set the leap year counter.
The interrupt register controls the operation of the interrupt
timer, selecting the required delay period and either single
or repeated interrupt.
The control register is responsible for controlling the operations of the clock and' supplying status information to the
processor. It appears as two different registers; one with
write only access and one with read only access.
The write only register consists of a bank of four latches
which control the internal processes of the clock.
The read only register contains two output data latches
which will supply status information for the processor. Table
III shows the mapping of the various control latches and
status flags in the control register. The control register is
located at address O.
The write only portion of the control register contains four
latches:
O.
The interrupt select bit determines which of the two registers mapped onto address 15 will be accessed when this
address is selected.
A logic 0 in the interrupt select bit makes the clock setting
register available to the processor. A logic 1 selects the
interrupt register.
The interrupt start/stop bit controls the running of the interrupt timer. It is programmed in the same way as the clock
start/ stop bit; logic 1 to halt the interrupt and reset the tim'
er, logic 0 to start interrupt timing.
When no interrupt is programmed (interrupt control register
set to 0), the interrupt start/stop bit is automatically set to a
logic 1. When any new interrupt is subsequently programmed, timing will not commence until the start/stop bit
is loaded with O.
In the single interrupt mode, interrupt timing stops when a
timeout occurs. The processor restarts timing by writing logic 0 into the start/stop bit.
In repeated interrupt mode the interrupt timer continues to
count with no intervention by the processor necessary.
2-134
z
Functional Description
en
w
(Continued)
I\)
."
TABLE III. The Control Register Layout
Access (addrO)
Read From:
Write To:
DB3
I\)
DB1
DB2
DBO
Data-Changed Flag
0
0
Interrupt Flag
Test
0= Normal
1 = Test Mode
Clock Start/Stop
0= Clock Run
1 = Clock Stop
Interrupt Select
o = Clock Setting Register
1 = Interrupt Register
Interrupt Start/Stop
o = Interrupt Run
1 = Interrupt Stop
2) Write 0 to the interrupt register: Ensure that there are no
interrupts programmed and that the oscillator will be gated
onto the interrupt output.
Interrupt timing may be stopped in either mode by writing a
logic 1 into the interrupt start/stop bit. The timer is reset and
can be restarted in the normal way, giving a full time delay
period before the next interrupt.
3) Set oscillator frequency: All timing has been halted and
the oscillator is buffered out onto the interrupt line.
In general, the control register is set up such that writing O's
into it will start anything that is stopped, pull the clock out of
test mode and select the clock setting register onto the bus.
In other words, writing 0 will maintain normal clock operation
and restart interrupt timing, etc.
The read only portion of the control register has two status
outputs:
Since the NS32FX211 keeps real time, the time data changes asynchronously with the processor and this may occur
while the processor is reading time data out of the clock.
4) Write 5 to the control register: The clock is now out of test
mode but is stl71 halted The clock setting register is now
selected by the interrupt select bit.
5) Write 0001 to all registers. This ensures starting with a
valid BCD value in each register.
6) Set 12/24 Hours Mode: Write to the clock setting register
to select the hours counting mode required
7) Load Real-Time Registers: All time registers (including
Leap Years and AM/PM bit) may now be loaded in any
order. Note that when writing to the clock setting register to
set up Leap Years and AM/PM, the Hours Mode bit must
not be altered from the value programmed in step 5.
Some method of warning the processor when the time data
has changed must thus be included. This is provided for by
the data-changed flag located in bit 3 of the control register.
This flag is set by the clock setting pulse which also clocks
the time registers. Testing this bit can tell the processor
whether or not the time has changed. The flag is cleared by
a read of the control register but not by any write operations.
No other register read has any effect on the state of the
data-changed flag.
Data bit 0 is the interrupt flag. This flag is set whenever the
interrupt timer times out, pulling the interrupt output low. In a
polled interrupt routine the processor can test this flag to
determine if the NS32FX211 was the interrupting device.
This interrupt flag and the interrupt output are both cleared
by a read of the control register.
8) Write 0 to the control register: This operation finishes the
clock initialization by starting the time. The final control register write should be synchronized with an external time
. source.
In general, timekeeping should be halted before the time
data is altered in the clock. The data can, however, be altered at any time if so desired. Such may be the case if the
user wishes to keep the clock corrected without having to
stop and restart it; i.e., winter/summer time changing can be
accomplished without halting the clock. This can be done in
software by sensing the state of the data-changed flag and
only altering time data just after the time has rolled over
(data-changed flag set).
Both of the flags and the interrupt output are reset by the
trailing edge of the read strobe. The flag information is held
latched during a control register read, guaranteeing that stable status information will always be read out by the processor.
Interrupt timeout is detected and stored internally if it occurs
during a read of the control register, the interrupt output will
then go low only after the read has been completed.
Reading the Time Registers
Using the data-changed flag technique supports microprocessors with block move facilities, as all the necessary time
data may be read sequentially and then tested for validity as
shown below.
1) Read the control register, address 0: This is a dummy
read to reset the data-changed flag (DCF) prior to reading
the time registers.
A clock setting pulse occurring during a control register read
will not affect the data-changed flag since time data read
out before or after the control read will not be affected by
the time change.
2) Read time registers: All desired time registers are read
out in a block.
3) Read the control register and test DCF: If DCF is cleared
(logic 0), then no clock setting pulses have after occurred
since step 1. All time data is guaranteed good and time
reading is complete.
Initialization
When it is first installed and power is applied, the
NS32FX211 will need to be properly initialized. The following operation steps are recommended when the device is
set up (all numbers are decimal):
If DCF is set (logic 1), then a time change has occurred
since step 1 and time data may not be consistent. Repeat
steps 2 and 3 until DCF is clear. The control read of step 3
will have reset DCF, automatically repeating the step 1 action.
1) Disable interrupt on the processor to allow oscillator setting. Write 1510 into the control register: The clock and interrupt start/stop bits are set to 1, ensuring that the clock and
interrupt timers are both halted Test mode and the interrupt
register are selected
2-135
><
.....
.....
.....
.....
N
><
U-
Functional Description
(Continued)
N
Interrupt Programming
APPLICATION HINTS
C/)
The interrupt timer generates interrupts at time intervals
which are programmed into the interrupt register. A single
interrupt after delay or repeated interrupts may be programmed. Table liB lists the different time delays and the
data words that select them in the interrupt register.
Once the interrupt register has been used to set up the
delay time and to select for single or repeat, it takes no
further part in the workings of the interrupt system. All activity by the processor then takes place in the control register.
Time Reading Using Interrupt
C")
Z
In systems such as point of sale terminals and data loggers,
time reading is usually only required on a random demand
basis. Using the data-changed flag as outlined in the section
on methods of operation is' ideal for this type of system.
Some systems, however, need to sense a change in real
time; e.g., industrial timers/process controllers, TV!VCR
clocks, any system where real time is displayed.
The interrupt timer oln the NS32FX211 can generate interrupts synchronously with the time registers changing, using
software to provide the initial synchronization.
Initializing:
1) Write 3 to the control register (ADO): Clock timing continues, interrupt register selected and interrupt timing stopped.
In single interrupt mode the processor is responsible for initiating each timing cycle and the timed period is accurate to
±1 ms.
2) Write interrupt control word to address 15: The interrupt
register is loaded with the correct word (chosen from Table
liB) for the time delay required and for single or repeated
interrupts.
In repeated interrupt mode the period from the initial processor start to the first timeout is also only accurate to ± 1 ms.
The following interrupts maintain accurate delay periods relative to the first timeout. Thus, to utilize interrupt to control
time reading, we will use repeated interrupt mode.
3) Write 0 or 2 to the control register: Interrupt timing commences. Writing 0 selects the clock setting register onto the
data bus; writing 2 leaves the interrupt register selected.
Normal timekeeping remains unaffected.
In repeated mode the time period between interrupts is exact, which means that timeouts will always occur at the
same point relative to the internal clock setting pulses. The
case for 0.1 s interrupts is shown in Figure A-f. The same is
true for other delay periods, only there will be more clock
setting pulses between each interrupt timeout. If we set up
the interrupt timer so that interrupt always times out just
after the clock setting pulse occurs (Figure A-2), then there
is no need to test the data-changed flag as we know that
the time data has just changed and will not alter again for
another 100 ms.
This can be achieved as outlined below:
On Interrupt:
Read the control register and test for Interrupt Flag (bit 0).
If the flag is cleared (logic 0), then the device is not the
source of the interrupt.
If the flag is set (logic 1), then the clock did generate an
interrupt. The flag is reset and the interrupt output is cleared
by the control register read that was used to test for interru~
.
Single Interrupt Mode:
When appropriate, write 0 or 2 to the control register to
restart the interrupt timer.
1) Follow steps 1 and 2 of the section on interrupt programming. In step 2 set up for repeated interrupt.
Repeated Interrupt Mode:
Timing continues, synchronized with the control register
write which originally started interrupt timing. No further intervention is necessary from the processor to maintain timing.
2) Read control register ADO: This is a dummy read to reset
the data-changed/lag.
3) Read control register ADO until data-changed flag is set.
4) Write 0 or 2 to control register. Interrupt timing commences.
In either mode interrupt timing can be stopped by writing 1
into the control register (interrupt startlstop set to 1). Timing
for the full delay period recommences when the interrupt
start/stop bit is again loaded with 0 as normal.
Time Reading wlthVery Slow Read Cycles
If a system takes longer than 100 ms to complete reading of
all the necessary time registers (e.g., when CMOS processors are used) or where high level interpreted language routines are used, then the data-changed flag will always be set
when tested and is of no value. In this case, the time registers themselves must be tested to ensure data accuracy.
IMPORTANT NOTE: Using the interrupt timer places a constraint on the maximum Read Strobe width which may be
applied to the clock. Normally all registers may be read from
with a tRW down to DC (Le., cg and RD held continuously
low). When the interrupt timer is active however, the maximum read strobe width that can be applied to the control
register (Addr 0) is 30 ms.
The technique below will detect both time changing between read strobes (i.e., between reading tens of minutes
and units of hours) and also time changing during read,
which can produce invalid data.
This restriction is to allow the interrupt timer to properly reset when it times out. Note that it only affects reading of the
control register-all other addresses in the clock may be
accessed with DC read strobes, regardless of the state of
the interrupt timer. Writes to any address are unaffected.
1) Read and store the value of the lowest order time register
required.
2-136
z
Functional Description
en
w
(Continued)
N
In general, the rule is that the first and last reads must both
be of the lowest order time register. These two values can
then be compared to ensure that no change has occurred.
This technique works because for any higher order time register to change, all the lower order registers must also
change. If the lowest order register does not change, then
no higher order register has changed either.
2) Read out all the time registers required. The registers
may be read out in any order, simplifying software requirements.
3) Read the lowest order register and compare it with the
value stored previously in step 1. If it is still the same, then
all time data is good. If it has changed, then store the new
value and go back to step 2.
r
-11- 16pJ
I
n
1-100ms-
INTERNAL
CLOCK
SmlNG
PULSES .........._ _ _ _ _
PULSES
..1,______.....__
-tOELAY
-j
-IoELAY-j
UI
INTERRUPT
DIP
INTERRUPT
SERVICED
UI
INTERRUPT
SERVICED
TL/F/ll011-6
FIGURE A·1. Time Delay from Clock Setting Pulses to Interrupt Is Constant
j-l00ms~
IN:~~~J
n
PULSES
INTERRUPT
DIP
--U
L
u
FIGURE A·2. Interrupt Timer Synchronized with Clock Setting Pulses
2·137
TL/F/ll011-7
"T1
><
N
.....
.....
Section 3
Application Notes
Ell
Section 3 Contents
AN-353 MM58167B Real Time Clock Design Guide.....................................
AN-359 The MM58174A Real Time Clock in a Battery Backed-Up Design Provides Reliable
Clock and Calendar Functions .....................................................
AN-365 The MM58274C Adds Reliable Real-Time Keeping to Any Microprocessor System. . .
AN-588 Calibration of the DP8570A Family ............................................
AN-589 DP8570A Timer Clock Peripheral Test Mode and Test Considerations..............
AN-595 Flexible Timers on the DP8570A and DP8571 A .................................
AB-43 Typical DP8570A Interface to the IBM PC/XT for the Purpose of Engineering
Evaluation ...... ". . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AN-443 Add a Hardware Clock/Calendar to Your IBM PC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AN-893 Using EXternal Oscillators for the DP857X Real Time Clocks with the Battery Backed
Mode Selected. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AN-894 DP8570A Experiments to Test the Low Battery Bit or Generate a Periodic Interrupt. .
AN-895 Change the Battery on any DP857X Family Member Using Software without Losing
Time............................................................................
3-2
3-3
3-20
3-29
3-45
3-50
3-54
3-60
3-62
3-83
3-86
3-95
MM581678 Real Time Clock
Design Guide
National Semiconductor
Application Note 353
Milt Schwartz
The MM58167B is a real-time 24-hour format clock with input/output structure and control lines that facilitate interfacing to microprocessors. It provides a reliable source of calendar data from milliseconds through months, as well as 6
bytes plus 2 nibbles of RAM, which are available to the user
if the alarm (compare) interrupt is not used. The MM58167B
features low power consumption (typically 4.5 microamperes at 3-volt supply) during battery backed mode, flexible
interrupt structure (alarm and repetitive), and a fast internal
update rate (1 kHz). Systems utilizing this device include,
personal computers, process control, security, and data acquisition.
Hardware Description Overview
1.0 Figure 1 is a functional block diagram of the MM58167B.
It can be subdivided into the following sections:
1.1 Oscillator
The oscillator consists of an internal inverter to which
the user connects a 32.768 kHz crystal, bias resistor
and capacitors, to form a Pierce parallel resonant circuit.
1.2 Prescaler
The prescaler divides the 32.768 kHz oscillator down to
1 kHz using pulse swallowing techniques. The 1 kHz
pulse rate is the incrementing signal for the timekeeping
counters.
This application note covers hardware interface to microprocessors, clock interrupts, oscillator operation, accuracy,
calibration techniques, software, and battery back-up considerations.
Block Diagram
DO
8 BITS
OSC IN
OSC OUT
INTERRUPT
OUTPUT
(NOT OPERATIONAL
DURING JiWA I!lIWR
CONDITION)
I!II
OPEN-. JmY
DRAIN
Wi!
DO
01
02
03
04
05
06
07
C!
J5OWEIrDl!WR
AD
A1
A2
A3
A4
mR9Y
IRTEI!IIUJiT
l' IIllTJIllT
(OPEN DRAIN
OPERATION DURING
PWIIl!lIWR CONDITION)
23
ADDRESS
DECODER
t------I.
ADDRESS DECODES
TLIF/5727-1
FIGURE 1
3-3
('t)
1.1')
C?
Hardware Description Overview (Continued)
=35,000
load Capacitance (Cl)
Power Rating
3-4
9 to 13 Picofarad
20 Microwatt Max.
Accuracy
User Choice
Temperature Coefficient
User Choice
»
z
Detail Descriptions (Continued)
I
w
en
w
20M
TYP
CMDS
8 pF
TYP
tODk
TYP
!r---tlt----.
PIN 11
PIN 10
INTERNAL
EXTERNAL
01 =32,768 Hz
Mnfg.
Tel.#
RCD
800-228-8108
Saronix
415-856-6900
Reeves-Hoffman 717-243-5929
C1= 5-+ 30 pi
aoM±2D%
Circuit Specialists
Part # 275-0430-005
Tel. # 1-800-528-1417
Johanson #9613 or #9410-3 pc.
Tel.# 201-334-2676
C2=15-+ 20 pi mica
C1
TL/F/5727-2
FIGURE 3. OSCillator Circuit and Recommended Connections
2DM
2DM
1DDk-470k
MM74HC4D4
OUTPUT
6 pF-36 pF
~2DPF
TLlF/5727-4
FIGURE4b.
TLlF/5727-3
FIGURE4a
3_ Use an external oscillator and drive pin 10 with a
low impedance device (CMOS or transistor), leave
pin 11 open circuit.
4. Connect all oscillator components as close as
possible to pins 10 and 11.
When used with a crystal, the accuracy of the oscillator circuit over voltage and temperature is about + / - 10 PPM.
Voltage variations cause about 50% of the inaccuracy and
temperature variations account for the other half. This inaccuracy results in an error of about 5 minutes per year. Errors
due to external components must be taken into account by
the user. If an external oscillator is used, then it determines
the accuracy of the clock. The oscillator input pin (pin 10), is
a high impedance node that is susceptible to 'noise'. The
usual result is the clock gains time at a high rate (on the
order of seconds per hour or greater). This noise is usually
the result of coupling from pin 9 which is a low order address bit if tied directly to a microprocessor bus. Suggestions to alleviate this condition are:
CALIBRATION
To calibrate the oscillator the following method is suggested. The one second repetitive interrupt is activated. This is
done by first connecting the interrupt (pin 13) of the clock to
the interrupt of the microprocessor. Next a short program is
written that sets bit 02 of the interrupt control register, and
then enters a loop that wastes time while awaiting an interrupt. The interrupt service routine only needs to read the
interrupt status register, which clears the interrupt, and then
returns. The result is a 1 second periodic signal at pin 13.
The flow chart of Figure 5 is an example of the detail steps.
A time event meter is used to measure the time interval
between successive positive going edges of the interrupt
output wllile adjusting the variable capacitor C1. This period
will be 1 second when the oscillator is at 32,768 Hertz.
1. Gate pin 9 with chip select.
2_ Use a slow rise and fall time non inverting buffer
such as a CMOS to drive pin 9. If this choice is
made, similar CMOS should drive the write and
read strobes to avoid timing conflicts.
3-5
.
Mr-------------------------------------------------------------~
Lt)
M
z
Detail Descriptions (Continued)
dropping three pulses every 128 counts of the 32,768 Hertz
signal. The resulting 32 kHz is then divided to produce 1
kHz which is the internal incrementer for the rest of the
timekeeper. This 1 kHz waveform is nonmonotonic with respect to individual periods. As a result, there are 750 short
and 250 long periods within a one second interval.
- - - - - - - - - i
f'
cs>-----I
WR>-----I
DECDDE~~~E:6~>-----I
1kHz
:.
~
,.....,
PIN 13
N
DATA BUS
FIGURE 9. Interrupt Registers and Logic
3-10
TL/F/5727-13
~
rnrz
I
I
I
0
COMPARE
INTERRUPT
OUTPUT
STANDBY
INTERRUPT
OUTPUT
~
~
COMPARE
(PI~
(r
(~
13)
CAUSED BY
" } - - - READING INTERRUPT
STATUS REGISTER
\
(PI~ 14)
1--
'-I
CAUSED BY
WRITINGAO
TO ADDRESS 16 HEX
1kHz
COUNTER
ROLLOVER
~
•
~
CAUSED'~~
REPETITIVE
INTERRUPT
OUTPUT
READING INTERRUPT
STATUS REGISTER
rL
~
I
TL/F/5727-14
FIGURE 10. Internal Interrupt Timing
DATA
Address
La Nibble
HI Nibble
Function
4
3
2
1
0
7
6
5
4
Milliseconds
0
1
0
0
0
0
0
0
0
Hundredths and
Tenths of Seconds
0
1
0
0
1
0
0
0
0
0
0
0
0
Seconds
0
1
0
1
0
0
0
0
0
0
0
0
0
Minutes
0
1
0
1
1
0
0
1
0
0
0
1
0
Hours
0
1
1
0
0
0
0
0
1
0
0
0
0
Day of Week
0
1
1
0
1
1
1
X
X
Day of Month
0
1
1
1
0
1
1
X
X
1
1
X
X
Months
0
1
1
1
1
1
1
X
X
1
1
X
X
No RAM Exists
FIGURE 11. Ram Mapping for Alarm Interrupt at 10:22:00 Every Day
3·11
3
2
1
0
No RAM Exists
NAME (' 1500Hz' )
TITLE 58167 500HZ REPETITIVE INTERRUPT (10/13/83)
;THIS PROGRAM IS FOR USE WITH THE 58167 POWER DOWN BOARD
;INTERFACED TO THE NSC888 BOARD. CODE IS NSCBOO.
;A 500HZ SIGNAL IS GENERATED AT THE INTERRUPT PIN (13).
;THIS SIGNAL IS GENERATED USING THE COMPARE INTERRUPT
;AND UPDATING THE' 'RAM" FOR THE NEXT INTERRUPT
ORG OBOOH
4092
4091
4090
40BF
40BE
40BD
40BC
40BB
40BA
40B9
40BB
101C
101D
0800'
0802'
OB05'
OB07'
OBOA'
OBOC'
OBOE'
OBll'
OB13'
OB16'
OB1B'
OB1B'
OB1E'
OB20'
OB23'
OB26'
OB29'
OB2C'
OB2F'
OB32'
OB35'
OB37'
OB3A'
OB3C'
OB3E'
OB40'
OB41'
RESET
CONT
STAT
MON
DOM
DOW
HRS
MIN
SEC
HT
MIL
VEC1
VEC2
3E
32
3E
32
3E
D3
31
3E
32
3E
32
3A
3E
32
32
32
32
32
32
32
3E
32
3E
32
FB
00
C3
00
101C
09
1010
08
BB
1FFF
FF
4092
00
4091
4090
CC
40BF
40BE
40BD
40BC
40BB
40BA
40B9
00
40BB
01
4091
INIT:
NOP:
OB40
EQU 04092H
EQU 04091H
EQU 04090H
EQU·040BFH
EQU 040BEH
EQU 040BDH
EQU 040BCH
EQU 040BBH
EQU 040BAH
EQU 04089H
EQU ·04088H
EQU 0101CH
EQU 0101DH
LD
LD
LD
LD
LD
OUT
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
EI
NOP
JP
A,O
SET UP INTRPT FOR NSCBBB
(VEC1) ,A
A,009H
(VEC2) ,A
A,B
(OBBH) ,A
SP,OlFFFH
A,OFFH
(Reset) ,A
INIT STACK POINTER
;RESET ALL CLOCK COUNTERS
A,O
(CONT) ,A
A, (STAT)
A,OCCH.
(MON) ,A
(DOM) ,A
(DOW) ,A
(HRS) ,A
(MIN) ,A
(SEC) ,A
(HT) ,A
;CLEAR INTRPT CONTROL
;CLEAR ANY PENDING INTRPT
;SET RAM FOR INTRPT
A,O
(MIL) ,A
A,l
(CONT), A
;SET COMPARE INTRPT
NOP
;WASTE TIME AWAITING
; INTERRUPT
;INTERRUPT SERVICE ROUTINE GETS THE VALUE IN THE
;MILLISECOND RAM, TEST FOR B. IF YES THEN SET RAM
;EQUAL TO 0, CLEAR INTERRUPT AND RETURN.
;IF NO, ADD 2 TO RAM MILLISECOND,
;CLEAR INTERRUPT AND RETURN.
;' 'REMEMBER" RAM MILLISECONDS IS "HIGH" ORDER NIBBLE
;ONLY
ORG 0900H
0900'
0903'
0905'
0907'
090A'
090C'
090F'
0912'
0914'
0917'
091A'
091B'
3A
E6
FE
CA
C6
32
C3
3E
32
3A
FB
C9
40BB
FO
BO
0912'
20
40BB
0917'
00
40BB
4090
LD
AND
CP
JP
ADD
LD
JP
ZERO:
LD
LD
RETRN: LD
EI
RET
A, (MIL)
OFOH
OBOH
Z,ZERO
A,020H
(MIL) ,A
RETRN
;GET RAM MILLSEC
;MASK
;? RAM=B
A,O
(MIL) ,A
A, (STAT)
;CLEAR INTRPT
END
FIGURE 12. NSC800 Assembly Code for 500 Hz Interrupt
3-12
STANDBVINTERRUPT
essor ports (for single chip microprocessors like the 8048),
peripheral adapter, and separate latches. The advantage of
memory mapped interface is use of all memory reference
instructions. The disadvantages are the processor may
need to be "wait-stated" and the environment is noisier with
respect to the crystal oscillator. Refer to Figure 13 for typical bus interface.
A "1" written to address 16 hex enables the standby interrupt and a "0" disables it. This interrupt also becomes active when a match exists between time keeping counter(s)
and a value written into RAM. The standby interrupt can be
cleared as soon as it is recognized. The user should ensure
that a delay of one millisecond or greater exists prior to
reenabling the standby interrupt. This delay is necessary
because of the internal signal level which causes the interrupt. If this delay does not occur, then the standby interrupt
becomes reactivated until the internal latched compare
goes away, which occurs at the next 1 kHz clock. Figure 10
illustrates interrupt timing.
Microprocessors that have separate ports (16 are sufficient)
offer the capability to interface directly without "wait-stating", or additional device count. Eight of the port bits (data)
need to be bidirectional for this interface. Figure 14 indicates port interface. Programmable peripheral interface devices such as the 8255A or NSC810 afford the user the
advantage of timing control by data bit manipulation, as well
as a less noisy environment with respect to the oscillator
circuit. Figure 15 depicts the 8255A and NSC810 interface.
RAM
RAM is organized as shown in Figure 2. There are 4 bits of
RAM for each BCD counter. The RAM may be used as general purpose or for an alarm interrupt. It is possible under
certain conditions to perform the compare interrupt and use
selected bits of the RAM for general purpose storage. Any
RAM position that is set for the 'always compare' condition
allows the user to manipulate the 2 LO order bits in each
nibble. However, the 2 high order bits in each nibble position
must be maintained as logic 1'S. For example, the user may
have an alarm interrupt that does not use the day of the
week as a condition for interrupt. Therefore the 2 low order
bits might be used as a 4 state software counter to keep
track of leap year. Reading and writing the RAM is the same
as any standard RAM.
External latches may be used in place of the programmable
peripheral interface device. This results in higher package
count but easier troubleshooting. Also, the latches do not
have to be manipulated through a control register. Figure 16
illustrates the external latch approach. For the peripheral
approaches, address, data, chip select, read and write
strobes are manipulated by controlling the data bus bits via
program execution. The peripheral interface approach facilitates calibration of the oscillator because the chip select,
read strobe, and address lines can be set to steady state
logic levels. Refer to calibration techniques for more detail.
HARDWARE INTERFACE CONSIDERATIONS
There are four basic methods of interfacing the MM58167B
to a microprocessor. They are memory mapped, microproc-
(SOS5)
(ZSO
NSCSOO)
p.P SYSTEM
BUS (NON-MUXED)
fOR NSCBOO,
lBO. S085,
OR ANY
PROCESSOR
WITH WAIT
STATE CAPABIlITY
TL/F/S727-15
FIGURE 13. Typical ,...p Bus Interface
II
3-13
~
LI)
,---------------------------------------------------------------------------------------,
~
z<
PORT 1
8048
CS
RD
WR
A4
A3
A2
CS
iiii
WR
A4
A3 MM58167B
A2
A1
AD
PORT 2
A1
AD
....
....
DATA BUS
,..
""III
07-00
TL/F/5727-16
FIGURE 14. MM58167B Interfaced to Single Chip Microcomputer
r--
CS
RD
WR
ADDRESS
"p
BUS
....
DATA
""III
...
IOTIM
ALE
....
,..
III.
,..
mMl{
CS
RD
WR
A4-AO
NSC810
OR
INS8255
}NSC610
PORT 2
....
DATA
""III
....
,..
III.
,..
MM58167B
07-00
TL/F/5727-17
FIGURE 15. MM58167B Interfaced to J.LP Through Peripheral Adapter
ADDRESS
BUS
cs
iii!
Wii
A4
A3
A2
A1
AD MM58167B
"p
t-.....~..~ 07-00
BUS
)0---11------1 ac
iiii
Wii
TL/F/5727-18
FIGURE 16. MM58167B Interfaced to J.LP Using TRI-STATE Latches
3-14
.
l>
saturation of a PNP transistor (0.1 volt) to take care of the
above situation. The NPN transistor is used to achieve isolation. The zener diode ensures that the circuit stops conducting and appears open circuit before the battery switches in.
POWER DOWN/BATTERY BACKED CONSIDERATIONS
Battery back up of the clock may be considered by the user
to maintain time during power failure, provide a "wake-up"
alarm, save the time that power failure occurred, calculate
how long power failure lasted. The first step in providing a
battery backed system is to isolate the system supply from
the battery. This is to ensure that the battery is not discharged by the system supply when power failure occurs.
Figure 17 shows two techniques to achieve isolation. Figure
17A is implemented using diodes to isolate. In one case a
Schottky diode is used to guarantee minimum voltage drop
loss, while in the other case an adjustable voltage regulator
(LM317) is used from a higher voltage and regulated to
about 5.7 volts. A 1N914 diode in series with the regulator
achieves the 5 volts for the clock. The Schottky diode has a
drop of about 0.3 volts. Thus the V+ of the clock is typically
at 4.7 volts. The user must be cautious about input signals
not exceeding the 4.7 volt V+, since the clock is a CMOS
device. This situation could arise if the devices driving the
inputs of the clock were CMOS and received power from
the 5 volt system supply. Figure 178 makes use of the low
Some basic considerations must be adhered to in a power
down situation where the real time clock is battey backed.
One is to ensure no spurious write strobes accompanied by
a chip select occur during power down or power up. Another
is to guarantee the system is stable when selecting/deselecting the clock. Also, any legitimate write-in-progress
should be completed. To accomplish this, hardware is implemented such that early power failure is detected (usually
a comparator detects DC failure, a retriggerable one-shot
detects AC failure) See Figures 18 and 19. At this point the
clock chip is deselected. The worst case is the power fails
faster than the detection circuit can cause deselection.
When power returns, the hardware detects power on, but
the system must be stable. before communication is allowed
with the real-time-clock.
12Y
5Y--~~-----'----~~----~
lN914
TL/F/5727-19
A
5Y
02
lN914
-=-
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CHOOSE 01 WITH BREAKDOWN=VSATT
TL/F/5727-20
B
FIGURE 17. Isolating System Supply from Battery
5Vr---------------~
SYSTEM
5Y
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TL/F/5727-21
FIGURE 18. Sensing D.C. Failure Using a Comparator
3-15
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FIGURE 19. Sensing AC Line Failure Using Retriggerable One Shot
goes low. Figure 19 shows AC sensing. This technique
could cause a spurious deselect of the clock if a "glitch"
occurs on the AC line resulting in a missed cycle.
The 5-volt system supply rise and fall time characteristics
during power turn on and power failure must be known.
Care should be taken to allow a legitimate write in progress
to be completed. This is necessary because a "short write"
could cause erroneous data to be entered to the clock. If
the clock is used as a "read only" device (except for initialization of calendar and time), the circuitry to allow a write in
progress to be completed does not have to be considered.
For this situation, a switch in series with the write strobe
could be implemented such that the write line to the clock is
"tied high" after initialization.
For this application, the circuit shown in Figure 20 was implemented. The MM58167B was interfaced to the NSC800
in memory mapped locations. A demo program was written
to exercise the clock, and display time, date and calendar.
Power was switched on and off at irregular intervals, to test
the battery backed circuitry. The results were that the clock
kept correct time. Battery backed current for all circuitry was
10 microamp. For general consideration, this circuitry allows
a chip select in progress to be completed.
To sense system DC power failure a comparator and voltage reference may be used. Figure 20, detail 1, shows the
comparator and voltage reference configured such that the
comparator output is "low" when 5-volt system power is
greater than 4.6 volts. If possible, the power fail trip point
should be referenced to a lightly loaded (fast collapse) DC
supply, preferably higher than the 5-volt system. This would
allow early sense of power failure. When using comparators,
the output may oscillate as the trip point is approached. The
oscillation is caused by noise on the DC line appearing at
the input to the comparator when at or near the trip voltage.
The cleaner the supply, the less chance of oscillation. In all
cases, hysteresis should be used to minimize oscillations.
Note that the 20 kohm pull-up resistor is connected to the
battery backed node, while the LM139 V+ pin is connected
to the 5-volt system supply. Used this way, the comparator
does not draw any current except leakage from the battery
and the output remains high during power down.
FUNCTIONAL OPERATION OF FIGURE 22
Power up sequencing consists of the LM139 (comparator)
making a high to low transition when the 5-volt system supply exceeds 4.6 volts. This transition triggers the 0.5 second
one-shot causing its output to be low and removes the low
reset on the D flip-flop through nand gate J. The output of
the 2 microsecond one-shot is "don't care" once the comparator switches from high to low. After 0.5 seconds, the
system is assumed to be stable, and the D flip-flop output
which was reset is clocked high by the low to high transition
of the 0.5 second one-shot. Thus, the clock chip is enabled
allowing normal communication with the microprocessor.
The power down sequence consists of the comparator making a low to high transition when the 5-volt supply is less
than 4.6 volts. If no chip select is present, the D flip-flop is
reset through nand gate J, causing pin 23 of the clock to be
low (deselected). If a legitimate chip select was in progress,
the reset action through nand gate J would be delayed by
the low level of the 2-microsecond one-shot.
To sense AC failure, a retriggerable one-shot may be used.
The RC time out may be adjusted to allow for one or more
cycles of 60 Hertz to be missed. Using this approach, the Q
output of the one-shot is always high while 60 Hertz is present. When a cycle is missed the one-shot times out and Q
3-16
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variable capacitor (Erie. Circuit Specialists)
FIGURE 3. Real Time Clock Interface with Wait States
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35,000 and a
frequency of 32,768 kHz. The load capacitance required
ranges from 9 pF to 13 pF. The maximum power rating is
20 p,W. The choice of crystal accuracy and temperature coefficient are left to the user. Two crystals used in our lab are
RCD's # RV-38 and Saronix's # NTF3238C.
201.4
15
H>,=
'y
200k
-_. ----------
To drive the oscillator from an external clock, connect the
clock to pin 14 (crystal out) and tie pin 15 (crystal in) high.
8PF
CONCLUSION
14
The MM58174A can easily be interfaced to a microprocessor to bring the functions of a real time clock and calendar
to any system. With a power-fail/back-up circuit, the system
will be able to keep accurate time for years, independent of
the system power supply.
200k (OPTIONAL)
32.768 kHz
...---101---...
6 pF- 36 pF
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TL/F/6169-5
FIGURE 10. Crystal Oscillator
3-28
National Semiconductor
Application Note 365
Peter K. Thomson
The MM58274C Adds
Reliable Real-Time
Keeping to Any
Microprocessor System
1.3 POWER SUPPLY ISOLATION SCHEMES
1.3.1 The Need for Isolation
1.3.2 Isolation Techniques 1-5V Supply Only
1.3.3 Isolation Techniques II-Negative
Supply Switched
1.3.4 Other Methods
INTRODUCTION
When a Real-Time Clock (RTC) is to be added into a digital
system, the designer will face a number of design constraints and problems that do not usually occur in normal
systems. Attention to detail in both hardware and software
design is necessary to ensure that a reliable and trouble
free product is implemented.
The extra circuitry required for an RTC falls into three main
groups: a precise oscillator to control real-time couting; a
backup power source to maintain time-keeping when the
main system power is removed; power failure detection and
write protection circuitry. The MM58274C in common with
most RTC devices uses an on-chip oscillator circuit and an
external watch crystal (frequency 32.768 kHz) as the time
reference. A battery is the usual source of backup power,
along with circuitry to isolate the battery-backed clock from
the rest of the system. Like any CMOS component, the RTC
must be protected against data corruption when the main
system power fails; a problem that is very often not fully
appreciated.
Rather than dealing strictly with anyone particular application, this applications note discusses all of the aspects involved in adding a reliable RTC function to a microprocessor system, with descriptions of suitable circuitry to achieve
this. Hardware problems, component selection, and physical board layout are examined. The software examples given in the data sheet are explained and clarified, and some
other software suggestions are presented. Finally a number
of otherwise unrelated topics are lumped together under
"Miscellany"; including a discussion on how the MM58274C
may be used directly to upgrade an existing MM58174A installation.
1.4 POWER FAIL PROTECTION
1.4.1 Write Protect Switch
1.4.2 5V Sensing
1.4.3 Supply Pre-Sense
1.4.4 Switching Power Supplies
1.4.5 Summary
2.0 SOFTWARE
2.1 DATA VALIDATION
2.1.1 Post-Read Synchronization
2.1.2 Pre-Read Synchronization
2.2 INTERRUPT AS A "DATA-CHANGED" FLAG
2.3 WRITING WITHOUT HALTING TIME-KEEPING
2.4 THE CLOCK AS A J.LP WATCHDOG
2.5 THE JAPANESE CALENDAR
3.0 MISCELLANY
3.1 CONNECTION TO NON-MICROBUS SYSTEMS
3.2 TEST MODE
3.3 TEST MODE AND OSCILLATOR SETTING
3.4 UPGRADING AN MM58174A SYSTEM WITH THE
MM58274C
3.5 WAIT STATE GENERATION FOR FAST p.Ps
CONTENTS
APPENDIX A-1 Reading Valid Real-Time Data (Reprinted
from the MM58274C Data Sheet)
1.0 HARDWARE
APPENDIX A-2 MM58274C Functional Truth Tables
1.1 COMPONENT SELECTION
1.1.1 Crystal
1.1.2 Loading Capacitors
1.1.3 Backup Battery:
Capacitors
Nickel-Cadmium Cells
Alkaline
Lithium
Other Cells and Notes
Temperature Range
1.0 HARDWARE
Selecting the correct components for the job and implementing a good board layout is crucial to developing an accurate and reliable Real-Time Clock function. The range of
component choices available is large and the suitability of
different types depends on the demands of the system.
1.1 COMPONENT SELECTION
With reference to Figure 1, the oscillator components and
the battery are examined and the suitability of different
types is discussed.
1.2 BOARD LAYOUT
1.2.1 Oscillator Connection
1.2.2 Battery Placement
1.2.3 Other Components
•
3-29
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100 nF DISK
TLlF/6737-1
FIGURE 1. MM58274C System Installation
1.1.1 Crystal
The capacitors are the components most likely to affect the
overall accuracy of the oscillator and care must be exercised in selection. Ceramic capacitors offer good operating
temperature range with close tolerance and low temperature coefficients (typically ± 3 ppm/K, for good quality examples). If trimming is undesirable a pair of close tolerance
(±5% or better) capacitors in the range 18 pF-20 pF may
be used. The average time-keeping accuracy for this configuration is within ± 20 seconds per month.
The oscillator is designed to work with a standard low power
NT cut or XV Bar clock crystal of 32.768 kHz frequency. The
circuit is a Pierce oscillator and is shown complete in Figure
2. The 20 Mn resistor biases the oscillator into its linear
region and ensures oscillator start-up. The 200 kn resistor
prevents the oscillator amplifier from overdriving the crystal.
If very low power crystals are used (Le., less than 1 p.W) an
external resistor of around 200 kn may have to be added to
reduce the drive to the crystal.
1.1.3 Backup Battery
The oscillator will drive most normal watch crystals, with up
to 20 p.W drive available from the on-chip oscillator.
There are a number of different cell types available that can
be used for time-keeping retention. Some cells are more
suitable than others, and the way in which the system is
used also influences the choice of cell. Ideally the standby
voltage of the RTC should be kept as low as possible, as
the supply current increases with increasing voltage (Figure
3). Four different power sources are discussed: capacitors,
nickel-cadmium rechargeable cells, alkaline and lithium primary cells.
CLOCK TO
COUNTER
CIRCUITRY
50
II
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40
~ 30
TL/F/6737-2
I
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FIGURE 2. Complete Oscillator Diagram
1.1.2 Loading Capacitors
10
Two capacitors are used to provide the correct output loading for the crystal. One is a fixed value capacitor in the
range 18 pF-20 pF and the other is a variable 6 pF-36 pF
trimmer capacitor. Adjusting the trimmer allows the crystal
loading (and hence the oscillator frequency) to be fine tuned
for optimal results.
o
1/
/
/
1
VDD (V)
TLlF/6737-3
FIGURE 3. Typical 100 (p.A) vs Voo (V) for MM58274C in
Standby Mode (TA = 25°C)
3-30
»
Capacitors
When the system is permanently powered, and any long
term removal of system power (i.e., more than a few hours)
requires complete restarting, then a 1-2 Farad capacitor
may be sufficient to run the clock during the power down.
This can keep the clock running for 48-72 hours.
Other Cells and Notes
There are many other types of cells, both primary and secondary, which may be adapted for RTC use. When selecting
a cell type, attention must be paid to:
Nickel-Cadmium Cells
Nickel-cadmium (Ni-Cad) cells can be trickle-charged from
the system power supply using a resistor as shown in Figure
1. The exact value of resistor used depends on the capacity
and number of cells in the battery. Consult the manufacturers data for information on charging rates and times.
a.
Cell capacity and physical size.
b.
c.
Storage (shelf) life.
Voltage variation over use.
d.
Operating temperature range.
e.
The method of battery connection and mounting.
In general, soldered cells are preferable to connector
mounted cells. With replaceable batteries, the battery and
connector contacts must be kept thoroughly clean. Dirty or
corroded contacts can cause the clock to be staNed of
power, giving erratic and unreliable performance. The ease
of operator access for cell replacement should also be considered.
A 3- or 4-cell battery should be used to power the clock (the
nominal battery voltages are 3.6V for 3 cells in series and
4.8V for 4 cells), with 3 cells preferable. PCB mounting batteries of 100 mAh capacity are available and these will give
around 6 months data retention (at normal room temperature). For this cell type to be used the system must spend a
large proportion of its time turned on to keep the battery
charged (i.e., used daily).
Temperature Range
The performance of any cell will be satisfactory for most
office or domestic environments. When "ruggedized" equipment is to be used (i.e., field portable equipment, automotive, etc.) the temperature specification of different cell
types should be taken into account when selecting a cell.
Lithium cells offer good performance over O·C-70·C with
little loss in capacity. Once again, the manufacturer's data
should be examined to determine suitability, especially
since different cells of the same type can have markedly
different characteristics.
Alkaline
Alkaline cells are among the least expensive primary cells
which are suitable for use in real-time clock applications.
They are available in a large range of capacities and shapes
and have a very good storage (shelf) life.
Two cells in series will provide a nominal 3V, which is adequate to power the clock (via the isolating diode). The main
problem with the alkaline system is that the cell terminal
voltage drops slowly over the life of the cell. When the voltage at the clock supply pin drops to 2.2V, the cells must be
replaced (battery voltage around 2.6V-2.7V). With present
alkaline cells, this point is usually reached when the cells
are only % to % discharged.
Few types of cells will offer any useful capacity at temperatures in or below the range 0·C-10·C, and fewer still will
operate over the full military temperature range (- 55·C to
+ 125·C). Solid lithium cells and mercury-cadmium cells are
two systems which can cover this range.
1.2 BOARD LAYOUT
Provisions must be made either to check the battery voltage
at regular inteNals or to replace the cells regularly enough
to avoid the danger of using discharged cells. Once again
the manufacturers data regarding capacity and cell voltage
against time must be examined to determine a suitable cell
selection. A good alkaline system will supply 1-2 years continuous time-keeping.
1.2.1 Oscillator Connection
The oscillator components must be built as close to the pins
of the clock chip as is physically possible. The ideal configuration is shown in Figure 4. From Figure 2, the oscillator
circuit, it can be seen that both Osc In and Osc Out are high
. impedance nodes, susceptible to noise coupling from adjacent lines. Hence the oscillator should, as far as is practicable, be surrounded by a guard ground. The absolute maximum length of PCB tracking on either pin is 2.5 cm (1 inch).
Longer tracks increase the parasitic track to track capacitances, increasing the risk of noise coupling and hence reducing the overall oscillator stability.
Where the system operates in humid or very cold environments (below 5·C), condensation or ice may form on the
PCB. This has the effect of adding parasitic resistances and
capacitances between pins 14 and 15, and also to ground.
This variation in loading adversely affects the stability of the
oscillator and in extreme cases may cause the oscillator to
stop.
Lithium
Lithium cells are the most suitable for real-time clock applications. A single cell with 3V potential is sufficient to power
the system. The cell potential is very stable over use and
the storage life is excellent. The energy density of lithium
cells is very high, giving enough capacity in a physically
small cell to power the clock continuously for at least 5
years (at room temperature using a 1,000 mAh cell).
Several cells which are recommended for RTC use are
D2/3A*, D2A*, and 1/6DEL/P*. Each have 1,000 mAh capacity. These cells are available with solder pin connections
for PCB mounting, giving a reliable backup supply.
'Ouracell Trade Number.
"Tadiran Trade Number.
3-31
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1.2.2 Battery Placement
For the battery, placement is less critical than with the oscillator components. Practical considerations are of greater
importance now; i.e., accessibility. The battery should be
placed where it is unlikely to be accidentally shorted or disconnected during routine operation and servicing of the
equipment.
When replaceable cells are used, connecting a 100 JLF capacitor across the ATC supply lines will keep the clock operating for 30-40 seconds with the battery disconnected (Figure 5). This allows the battery to be replaced regardless of
whether or not the main supply is active.
Keeping the PCB tracks as short as possible will help to
minimize the problem, and on its own this may be sufficient.
Where the operating conditions are particularly severe, the
PCB and oscillator components should be coated with a
suitable water repellent material, such as lacquer or silicon
grease (suitability being determined by the electrical properties of the materials-high impedance and low dielectric
constant)"
Figures 2 and 4 show the trimmer placed on Osc Out. The
placement of the trimmer capacitor on either Osc In or Osc
Out is not critical. Placing the trimmer on Osc Out yields a
smaller trim range, but less susceptibility to changes in trimmer capacitance. Placement of the trimmer capacitor on
Osc In gives a wider trim span, but slightly greater susceptibility to capacitance changes.
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FIGURE 4. Oscillator Board Layout
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3.6V
BATTERY ~
220
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100 nF
TL/F/6737-5
FIGURE 5. Simplified Power Supply Diagram with 100 JLF Capacitor Added
3-32
1.2.3 Other Components
The placement of the other ATC dedicated components
(e.g., supply disconnection and power failure protection
components) is not particularly critical. However, the same
guidelines as applied to the battery should be followed
when the PCB layout is designed.
is a complete waste and serves only to reduce the cell life.
Depending on the value of As, the voltage level at the pin
may fall low enough to turn on the internal TIL level buffer,
wasting further current as the buffer is no longer fully
CMOS.
With Vss disconnected (Figure 6b), there is no return path
to the battery and the pin is pulled completely up to Voo.
The TIL buffer is switched off and no power is lost.
1.3 POWER SUPPLY ISOLATION SCHEMES
1.3.1 The Need for Isolation
There are two reasons for disconnecting the clock circuit
from the rest of the system:
1. To prevent the backup battery from trying to power the
whole system when the main power fails.
2. To minimize the battery current (and extend battery life)
by preventing current leakage out of the ATC input pins.
The MM58274C inputs have internal pull-up devices which
pull the inputs to Vooin power down mode. This turns off
the internal TIL input buffers and causes the J.LP interlace
functions of the clock to go to full CMOS logic levels, drawing no supply current (except for the unavoidable leakage
current of the internal MOS transistors). For the MM58274C
this is achieved by isolating the ground (Vss) supply line
from the rest of the system.
Figures 6a and 6b show the two cases where first Voo (6a)
and then Vss.(6b) are open-circuited. The line out from the
MM58274C represents any of the Control, Address, or Data
lines on the ATC, with the internal pull-up resistor shown.
The two diodes and resistor As represent the logic device
connected to the ATC input and the resistance of the rest of
the system with no power applied.
When Voo is open-circuit as in Figure 6a, there is a complete current path, shown by the arrows, out of the ATC
input and through the external circuitry. This battery current
1_3.2 Isolation Techniques 1-5V Supply Only
Figure 7 shows the isolation circuit suggested in the
MM58274C data sheet. This circuit provides complete disconnection where only the system + 5V is available for
switching control.
~--------'_--------------.---~~+5V
ZDl
3,6V
.....- - - - - - - - . - - - - - - - - - - -.....---t
TL/F/6737-B
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FIGURE 7. 5V Isolation Circuit
TA2 is the disconnecting device, which is controlled by TA3
and its associated circuitry. TA3 is turned on by its bias
chain A2, ZD1, A4 as the system supply rises up to 4.2V.
TA3 and A3 'then turn on TA2 to connect the clock to the
system supply. D1 isolates the backup battery when the
system supply is active. The 100 nF disk capacitors decouple the supply during A/W operations and should be included in any disconnection scheme.
TA3 is necessary to prevent A3 and TA2 from leaking battery current in the power down condition. The circuit without
TR3 is shown in Figure 8 where TA2 has been replaced by
equivalent diodes to clearly show the problem. The circuitry
could be simplified· by replacing TA3 with a Zener diode
(Figure 9). There will be a sma" loss of current down
through TR2 however, as the Zener wi" pass a sma" leakage current at below its "knee" voltage. Thus the Zener
should be selected for its low current capability.
,
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(EQUIVALENT SYSTEM
Rs RESISTANCE WITH NO
POWER APPLIED)
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TLlF/6737-6
a) Vee Disconnection
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EQUIVALENT
b) Vss Disconnection
FIGURE 6. Current Leakage Prevention
by Proper Supply Disconnection
TL/F/6737-9
As
= System Aesistance
with No Power Applied
FIGURE 8. Current Leakage in Simplified
Disconnection Schemes
3-33
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1.3.3 Isolation Techniques /1Negative Supply Switched
.....- - +5V
r---~.---
Where a negative voltage supply is available (either regulated or unregulated) the circuit of Figure 11 may be used. This
is similar in operation to its diode equivalent shown in Figure
12, where the voltage drops across the diodes provide the
correct potential to the clock. Figure 11 has the advantage,
however, that the clock power is supplied from the ground
line by transistor action, rather than via the resistor as in
Figure 12. Less lower is dissipated in the resistor as only
transistor bias current need be drawn.
OV
TL/F/6737-10
FIGURE 9. Alternative Supply Disconnection Scheme
Sensing 5V (Decoupling Capacitors
Omitted for Clarity)
. . . - - -.....- - - - - - + 5 V
Finally TR1 and R1 (Figure 7) are optional components
which are only required when the interrupt output is used. If
interrupts are left programmed when the power fails, the
interrupt timer will still time-out setting the interrupt output.
Since this is an active low pull-down transistor it effectively
shorts directly across TR2, destroying the RTC isolation and
discharging the battery into the rest of the system (Figure
10). In order to prevent this from occurring, TR1 and R1 are
added.
L....------OV
-Va
TLIF16737 -12
EQUIVALENT
CIRCUIT FOR A
CMOS DEVICE DIP
FIGURE 11. Negative Voltage Driven Supply
Disconnection Scheme (Decoupling
Capacitors Omitted for Clarity)
(PDWER SUPPLY
EQUIVALENT
POWERED DOWN
SOURCE
RESISTANCE)
r - - - -....- - - +5V
OV
TL/F/6737-11
FIGURE 10. Battery Discharge Path via
Un isolated Interrupt Output
None of the disconnection components are at all critical,
with general purpose transistors being completely adequate
for the task. D1 should be a small-signal silicon or germanium diode.
TL/F/6737-13
FIGURE 12. Diode Equivalent Circuit of Figure 11
1.3.4 Other Methods
There are many other possibilities for supply disconnection
schemes, Le., relay disconnection. When designing a disconnection scheme, the performance must be analyzed
both with the system power applied and with system power
absent. Check for leakage paths and undue voltage drops
and try to set up so that disconnection and reconnection will
take place as near to the backup voltage as possible.
3-34
.
l>
1.4 POWER FAIL PROTECTION
Three methods of power fail protection are discussed, although there are also many other possibilities.
One of the major causes of unreliability in RTC designs is
due to inadequate power failure protection. As the system is
powered up and down, the ILP and surrounding logic can
produce numerous spurious signals, including spurious
writes and illegal control signals (Le., RD and WR both active together).
By far the simplest and potentially the most hazard-free
method is to use a switch on the WR control line to the
clock (Figure 14). This is completely adequate, but requires
the intervention of an operator to alter time data or program
interrupts.
Some thought must be given to ensuring that the operator
cannot accidentally leave the WR line switched in. This may
be achieved by the physical access method used (Le., the
machine is impossible to operate or switch off when in the
time setting mode, because of the placement of access
. hatches, etc.) or with software. The switch state could be
sensed by trying to alter the data in the Tens of Years counter or Interrupt register just prior to leaving the clock setting
routine, and refusing to leave the routine until the WR switch
has been opened. The switch condition should similarly be
checked whenever the system is initialized or reset.
In order to protect the time data, the system must be physically prevented from writing to the clock when the power
supply is not stable. The ideal situation is to ban Write access to the clock before the system + 5V starts to fail, and
then keep the chip "locked-out" until the power is restored
and stabilized. This ideal access control signal is illustrated
in Figure 13.
The physical location of the switch should also be considered for ease of accessibility. How easy the switch is to
reach will depend on the system; Le., in some cases a "tamper proof" clock may be required.
SYSTEM SUPPLY
"TN"
PRE· FAILURE
LOCKOUT PERIOD
SYSTEM 5V
I
SYSTEM SUPPLY
UNDEFINED
NORMAL STANDBY
....,_ _ _ _"ODE
OPERATION
-iA!II
PDST.FAILURE
LDCKDUT PERIDD
I
I
~L - -__________....
WRITE ACCESS'"iNABLE
TL/F/6737-14
FIGURE 13. RTC Access Lockout Definition
TL/F/6737-15
FIGURE 14. Write Protection by Manually Switching WR
3-35
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1.4.1 Write Protect Switch
Bipolar logic devices can produce spikes anc~ glitches as the
internal biasing switches off around 3V-3.5V, and the transistors operate in their linear region for a short time. Any
such spurious signals, if applied to the RTC, could cause the
time data to be corrupted. Systems using 74HC logic and
CMOS processors are less stringent in their power failure
requirements as the devices tend to work right down to
around 2V. Some form of write protection is still required,
however.
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1.4.2 5V Sensing
F2 prevents P.Fail from locking out the clock if there is a
Write cycle in progress. F1 isolates the WR input on the
clock when F2 passes the P.Fail signal. C1, R2 and D1 do
not slow the advent of P.Fail, but they cause a delay in the
release of the function to mask any comparator noise or
oscillation as the comparator switches off or on (Le., during
the undefined supply periods).
The circuit of Figure 15 senses the system 5V supply and
prevents access to the clock if the supply falls below 4.2V4.3V. This circuit should be used where only the system 5V
is available for reference. The LM139 comparator and associated components sense the 5V supply and generate the
power fail signal (P.Fail). The 74HC75 and components disconnect the WR line.
D2, C3 and R6 smooth the comparator supply and help it to
function effectively. The time constants of the RC networks
should be selected to suit the power supply of the system
that is used. Comparing the functioning of this circuit with
the ideal case of Figure 13 shows that most of the conditions can be satisfied, except that there is no real pre-failure
lock-out period. This cannot be achieved without some form
of look ahead power failure.
R3 and ZD1 provide a reference voltage of 2V-3V for the
comparator. R4 and VR1 form a potential divider chain
sensing the 5V line, and VR1 is adjusted to switch the comparator output at 4.2V-4.3V. An alternative to VR1 would be
to use a pair of close tolerance resistors (± 2 %) with values
selected to suit the Zener diode reference used. The combi- .
nation of R4, D3 and C2 provide an RC time constant to
delay the comparator when sensing the return of 5V (to provide the post-failure delay in Figure 13). The LM139 has an
open-collector output which is held low when 5V is present
and is switched off when 5V fails. This line is pulled high by
R5 to flag power failure (P.Fail). Since the comparator is a
linear device drawing a bias current, it is powered by the
system 5V supply to avoid consuming battery power.
As an alternative to F1 a permanently powered 74HC4066
analog switch could be used as the isolating component
(Figure 16). The 74HC4066 does not require pull-up resistors on its inputs as there are no internal CMOS buffers
inside this device which must be controlled. The resistor on
the WR line is for the benefit of the 74HC75.
Note that both of the devices mentioned must be permanently powered from the battery to be useful in this way.
Unused gates in any such device must NOT be used in
combinational logic that is not permanently powered. All unused inputs should be tied to Voo or Vss to render them
inactive.
.
One 74HC75 package contains four latches, of which two
are used. These are transparent latches controlled by the
"G" input. With G high, the latch is transparent and the Q
and Q outputs follow the Data input. When G is low, the
state of Q and Q on the falling edge is latched. In this way,
Wii FROM!,P
CONTROL BUS
r-----.--------.------~------~--~~~--_.----~--~~----~~----+5V
D2
Voo
VBAl.I.
Vss
~---e----~--~.---~~OV
TL/F/6737-16
FIGURE 15. Power Supply Failure Detection and Write Protection Circuitry
3-36
l>
1.4.3 Supply Pre-Sense
z
1.4.4 Switching Power Supplies
The same circuit of Figure 15 can be used with unregulated
supplies or other voltage lines which will fail before the SV
line. To achieve this, point X is connected to the sensed
voltage instead of SV, and the R4IVR1 ratio is adjusted to
suit. The major benefit here is that advance warning of an
impending SV failure can be detected, allowing a pre-failure
lockout signal to be generated.
I
Switching power supplies are available which generate power failure signals. This signal may be adequate for direct use
as a P.Fail line, but the manufacturer's information should
be consulted to determine the suitability of a given power
unit. P.Fail must still be gated with the Write signal for the
clock, regardless of the actual detection method employed.
1.4.5 Summary
Less precision is required to sense the unregulated supply
than the system SV supply. Consequently less complex circuitry can be used to do the detection and this is reflected in
the circuit of Figure 17. Most SV regulators will operate with
an input voltage from 7V to 2SV. Typically the input voltage
is around 9V to 12V, giving some headroom. In Figure 17
this voltage is high enough to drive a current through the
Zener diode and turn on transistor TR1, holding P.Fail low.
RUM limits the Zener current. The Zener voltage is selected
to switch off before the regulator fails, around 7.SV-8.SV
depending on the time constant of the supply. With no current, TR1 switches off and Rp pulls P.Fail high.
The general guidelines for power fail protection are:
1. Physically isolate the WR input to the clock. The J.LP cannot be relied upon to logically operate the isolation mechanism.
2. The clock should be isolated before the SV power line
starts to fail, and stay isolated until after it has reestablished.
3. Consider the action of the sensing and protection circuitry
if the supplies oscillate or if a momentary glitch occurs.
4. The Power Fail signal must be gated with Write strobes to
the RTC. A foreshortened Write may also cause data corruption.
When power is re-applied the SV supply will stabilize before
the Zener switches on, removing P.Fail. To provide a longer
post-failure lockout period RUM could be replaced with two
resistors and a diode/capacitor delay as in Figure 15.
5. Logic components (and ICs in general) should be avoided
when designing power failure schemes. Discrete components are far more predictable in their performance when
the power supplies are not well defined. The exception to
this general rule is when using permanently powered
HCMOS logic devices. They will function in a reliable
manner down to 2V.
Figure 18 is another extension of the same basic idea to
provide an advance interrupt signal to allow J.LP housekeeping before the RTC (and CMOS RAM) is locked out. The
extra rectifying components D1, Ct and Rt keep NMI off as
long as input power is present. Time constant T2 is selected
to be at 2-3 times faster than T1, the supply time constant.
The interrupt signal is thus asserted before P.Fail.
System-powered logic devices cannot be relied on for power failure or Write isolation (not even CMOS).
r---~~------------~~-----,----------~---,----+5V
P. FAIL
OV
TL/F/6737-17
FIGURE 16. F1 Replaced by a 74HC4066 Analog Switch (Pull-Up Resistors Not Required on CS or RD Inputs)
+5V
P. FAIL
~--------~.-------e-e---~--OV
TLlF/6737-18
FIGURE 17_ Power Fail Signal Generation from Unregulated Supplies
3-37
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START/STOP
XT~~ o--C>o-.....--L....J
X~~~ o--'l20"'0"k!""/..
NO INTERRUPT
PROG'D
TEST MOOE
DIVIDE
COUNT
0.1
0.5
1
INTERRUPT
START/STOP--'~'--"'-"
5
10
30
60
+49
+241
+481
+2401
+4801
+14401
+28801
TLIF/6737-22
FIGURE 20. Test Mode Interconnection Diagram of Internal Counter Stages
10
,,$ :s Iw
VIH ;;,: 75% Vee
OSC IN
(PIN 15)
:s 35 ,,$ (Vee = 2V-5.5V)
I'
I
\
VIL :s 25% Vee
TLIF/6737-23
FIGURE 21. Oscillator Waveform for Counter Clocking in Test Mode
Note that oscillator frequency will vary slightly as the supply
varies between operating and standby voltages. Typically
this variation will be around ± 6 seconds per month
(VSTANDBY = 2.4V), slowing at standby voltage. When the
clock will spend the greater part of its working life in standby
mode, it may prove worthwhile to correct for this in the tun·
ing. This can be done by tuning at standby voltage (by writing the RTC into test mode, then disconnecting it from the
system to tune on battery backup). Alternatively, the clock
can be slightly overtuned at operational voltage, tuning to
32.7681 kHz.
The pulse width limits for reliable clocking are shown on the
diagram. When running with a 32 kHz crystal, the normal
pulse width is 15.26 /J-s. With no forcing input, the oscillator
will self bias to around 2.5V (VDD = 5V). While a few hun·
dred mV swing above and below this level is sufficient to
drive the oscillator, for guaranteed test clocking the input
should swing between VIH ~ 75% VDD and VIL ~ 25%
VDD· .
3.3 TEST MODE AND OSCILLATOR SETTING
When Test Mode is used to set the oscillator frequency, the
interrupt timer must be disabled (interrupt register pro·
grammed with all Os) for the oscillator frequency to appear
on the interrupt output. No test equipment should be con·
nected directly to either oscillator pin, as the added loading
will alter the characteristics of the oscillator making precise
tuning impossible.
In a similar way, where the RTC spends equal amounts of
time in both operational and standby modes (I.e., powered
by day, standby at night), the oscillator may be tuned some·
where between the two conditions. Following these tuning
suggestions will not eliminate time·keeping errors, but they
will help in minimizing them.
3-40
»
Time-keeping accuracy cannot be exactly specified. It depends on the quality of the components used in the oscillator circuit and their physical layout, also the stability of the
supply voltage, the variations in ambient temperture, etc.
With good components and a reasonably stable environment however, time-keeping accuracy to within 4 seconds/month can be achieved, although 8 seconds/month is
somewhat more typical in practical systems.
vations. The two devices are not quite the same in their
external circuit appearances, and this is reflected in their
applications circuits. In addition, the MM58274C is not software compatible with the MM58174A, requiring a change in
the operating system to use the MM58274C.
Figure 22 shows the circuit diagram for the MM58174A system connection. There are two major differences between
this and the MM58274C diagram (Figure 1); a) the oscillator
circuit and b) the supply disconnection scheme.
3.4 UPGRADING AN MM58174A SYSTEM
WITH THE MM58274C
The MM58274C has the same pin-out as the MM58174A
and can be used as a direct replacement, with certain reser-
l00"'J
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READY
+--
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DELAY
STROBE
GENERATOR
(SEE
fiGURE 9)
CHIP
SELECT
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4
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RD
2
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3
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DB3
4
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082
5
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1"'l1lI
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74HC4066
081
6
080
7
....
16
t---
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~ 220
10k
f..t
~ 3-5V
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470
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n
OSCilLATOR GUARD GROUND (OPTIONAL)
.. ____________________
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15---·
14
13 - - - - - - - - . ,
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AD3
+5V
th~~
AD2
ADl
ADO
INTERRUPT
TLIF/6737-24
·Use resistor with Ni-Cad cells only.
FIGURE 22. MM58174A System Installation
3-41
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2
system clock.
After n 4>2 clocks (where n is the number of flip-flops in the
shift register) a logic 0 shifts out from the nth F/F, resetting
the main flip-flop. The main F/F then presets the shift register and clears the WAIT signal, ready for the next CS edge
to repeat the cycle. On power-up the delay generator 'will
initialize itself after a maximium of n system clocks have
occurred so no reset signal is required. Some fJ-Ps demand
that a WAIT/READY input is synchronized with 4>2 of the
system clock. This can readily be achieved by selecting the
correct 4>2 edge as the clock signal for the shift register
chain.
The largest penalty in inserting an MM58274C into an
MM58174A circuit is the battery current that is lost through
the pull-up devices. This will increase the typical supply current from 4 fJ-A to 50-100 fJ-A and it is up to the individual
user to decide whether or not this drain is tolerable in a
particular application.
The most important requirement is that the WR input should
be electrically isolated or current leakage through pin inputs
may force the inputs low enough to cause spurious writes to
TO I'P WAIT/READY I/P
<1>2 OR ¢z
(CHECK IlP 0------+--...- - - -...- - - REQUIREMENTS)
TL/F/6737-25
Flip·Flop-MM74HC74 D·Type Latch
FIGURE 23. Access Delay Generator (Clocked Wait State Generator)
3-42
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4. Read control register ADO repeatedly until data-changed
flag is set.
APPENDIX A·1. READING VALID REAL·TIME DATA
TIME READING USING DCF
5. Write 0 or 2 to control register. Interrupt timing commenc-
Using the Data-Changed Flag (DC F) technique supports mi·
croprocessors with block move facilities, as all the neces·
sary time data may be read sequentially and then tested for
validity as shown below.
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When interrupt occurs, read out all required time data.
There is no need to test DCF as the interrupt "pre-synchronizes" the time reading already. The interrupt flag is automatically reset by reading from ADDRO to test it. In repeat
interrupt mode, the timer continues to run with no further J.LP
intervention necessary.
1. Read the control register, address 0: This is a dummy
read to reset the data-changed flag (DCF) prior to reading
the time registers.
2. Read time registers: All desired time registers are read
out in a block.
3. Read the control register and test DCF: If DCF is still
clear (logic 0), then no clock setting pulses have occurred
since step 1. All time data is guaranteed good and time
reading is complete.
If DCF is set (logic 1), then a time change has occurred
since step 1 and time data may not be consistent. Repeat
TIME READING WITH VERY SLOW READ CYCLES
If a system takes longer than 100 ms to complete reading of
all the necessary time registers (e.g., when CMOS processors are used or where high level interpreted language routines are used) then the data-changed flag will always be
set when tested and is of no value. In this case, the time
registers themselves must be tested to ensure data accuracy.
steps 2 and 3 until DCF is clear. The control read of step 3
will have reset DCF, automatically repeating the step 1 action.
The technique below will detect both time changing between read strobes (Le., between reading tens of minutes
and units of hours) and also time changing during read,
which can produce invalid data.
TIME READING USING AN INTERRUPT
In systems such as point-of-sale terminals and data loggers,
time reading is usually only required on a random demand
basis. Using the data-changed flag as outlined above is
ideal for this type of system. Where the J.LP must respond to
any change in real-time (e.g., industrial timers/process controllers, TV /vCR clocks or any system where real-time is
displayed) then the interrupt timer may be for time reading.
Software is used to synchronize the interrupt timer with the
time changing as outlined below:
1. Read and store the value of the lowest order time register
required.
2. Read out all the time registers required. The registers
may be read out in any order, simplifying software requirements.
3. Re-read the lowest order register and compare it with the
value stored previously in step 1. If it is still the samo,
then all time data is good. If it has changed, then storo
the new value and go back to step 2.
1. Select the interrupt register (write 2 or 3 to ADDRO).
In general, the rule is that the first and last reads must both
be of the lowest order time register. These two values can
then be compared to ensure that no change has occurred.
This technique works because for any higher order time register to change, all the lower order registers must also
change. If the lowest order register does not change, then
no other register has changed either.
2. Program for repeated interrupts of the desired time interval (see Table lib in Appendix A-2): Do not start the timer
yet.
3. Read control register ADO: This is a dummy read to reset
the data-changed flag.
APPENDIX A·2. FUNCTIONAL TRUTH TABLES FOR MM58274C
TABLE I. Address Decoding for Internal Registers
Address Bits
Register Selected
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Control Register
Tenths of Secs
Units Seconds
Tens Seconds
Units Minutes
Tens Minutes
Units Hours
Tens Hours
Units Days
Tens Days
Units Months
Tens Months
Units Years
Tens Years
Day of Week
Clock Setting/lnterrupt Registers
Access
AD3
AD2
AD1
ADO
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
a
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
1
3-43
a
Split Read and Write
Read Only
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
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TABLE lIa. Clock Setting Register Layout
('I)
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co
co
co
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Voo.
(See datasheet for hardware configurations.)
In standby the timers are still operational if bit 05 of the real
. time mode register is set, and if so, timer (and other) interrupts can be operational in standby if bit 04 is set. The TCK
and G input pins, however, are locked out. In standby, MFO,
INTR and T1 outputs are automatically configured in as
open-drain outputs. When power is restored (Voo > Vss)
they return to the output mode register configuration.
f) Interrupt Routing Register: Route TO/1 interrupts (0 to
INTR, 1 to MFO) if required.
g) Main Status Register: PS = 0, RS = 1.
h) Output Mode Register: Configure T1, INTR and MFO
Outputs (Table IV).
i) Interrupt Control Register 0: Set TO/1 interrupt enable
bits if required.
j) MSB/LSB TO/1 Registers: Load values for timer counter(s).
k) READ: main status register to clear old interrupts.
I) Main Status Register: PS = 0, RS = o.
m) TO and/or T1 Control Registers: start timer(s) with bits
set for mode (Table I) and input clock (Table III).
t.4FO
Output
TImer 0
Interrupt
TImer 1
Interrupt
INTR
Output
TLlF/10372-6
FIGURE 6. DP8570A Timer Interrupts
3-57
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16
MFO
17
INT
26
TCK
15
GO
G1 ~
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Battery
~ (3.,V Uthl,m)
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2x 10k.Q.
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...L0.047 ...L0.047 ...L4.7
T p.F T p.F .Tp.F
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TLlF/10402-1
FIGURE 1. DP8570A Timer Clock Peripheral Interface to IBM/XT
3-61
~r-------------------------------------------------------------~
National Semiconductor
Application Note 443
Wesley Lee
"'1:1"
Z Add a Hardware Clock!
« Calendar to Your IBM PC
By installing a clock/calendar chip, some interface circuitry,
a battery backup system, and two simple programs in your
IBM PC, you can add a real-time hardware clock to your
computer.
For many personal-computer applications, you need to use
time-of-day information to time-stamp files (Le., to keep
track of when you initiated files and when you last updated
them), run datebook software, enable autoanswer/autodial
modems, and perform other tasks. The IBM PC-DOS maintains a software clock/calendar, but.it requires you to enter
both date and time from the keyboard every time you power
up the computer. However, by adding an inexpensive hardware real-time clock, you can eliminate manual date/time
entry.
To add a hardware clock to your PC, you need only a clock/
calendar chip, some interface circuitry, a battery backup
system, and two simple programs that let you initialize, read
from, and write to the chip. You can use a chip like the
MM58274 clock/calendar chip from National Semiconductor as a real-time clock. Although it's fabricated in low-power CMOS, the chip is directly compatible with TTL-level systems. Because of the chip's low current drain in standby
mode (1 a Il-A at 2.2V), you can use a small lithium battery
for standby operation. If the battery and clock chip are isolated from all other computer circuitry, the chip will continue
keeping correct time for years in standby mode.
THE MM58274 CLOCK/CALENDAR CHIP
At the heart of the MM58274 are fourteen cascaded counters that provide the timekeeping functions (Figure 1).
These counters range from tenths of seconds to tens of
years; one of them keeps track of the day of the week. A
2-bit register keeps track of. the years since the last leap
year; you have to set this register during initialization, but it's
not otherwise accessible to the user. The fastest counter
(tenths of seconds) is clocked by a 1a-Hz reference signal
that the chip produces by prescaling the 32.768-kHz output
of the internal crystal oscillator. As each counter rolls over,
the resulting carry pulse clocks the next counter.
Each timing counter is individually addressable for reading
or writing; when you place an address (in the range 1HEX
through EHEX) on the MM58274's four address lines, the
corresponding counter is connected to the four data lines
for a data transfer in BCD format. Unused bits (eg, bit 3 in
the tens-of-minutes counter, which counts only from a
through 5) are forced to zero in the read mode and are
ignored in the write mode.
,
TL/F/B690-1
FIGURE 1. Although It s fabricated In low-power CMOS, the MM58274 clock/calendar chip Is directly compatible
with TTL-level systems. It Includes 14 cascaded counters that provide the timekeeping functions.
Printed previously by EON Magazine.
3-62
TABLE I. I/O Address Map
HEX RANGE
OOO-OOF
020-021
040-043
060-063
080-083
OAX
OCX
OEX
200-20F
210-217
220-24F
278-27F
2CO-2DF
2FO-2F7
2F8-2FF
300-30F
310-31F
320-32F
378-37F
380-38C
380-389
3AO-3A9
3BO-3BF
3CO-3CF
3DO-3DF
3EO-3E7
3FO-3F7
3F8-3FF
USAGE
12/24
SELECT
DMA8237A-5
INTERRUPT 8259A
TIMER 8253-5
PP18255A-5
DMA PAGE REGISTERS
NMI MASK REGISTER
RESERVED
RESERVED
GAME CONTROL
EXPANSION UNIT
RESERVED
RESERVED
AST "SUPER PAK" CARD
RESERVED
ASYNCH COMM (SECONDARY)
MM58274 REAL-TIME CLOCK
OTHER PROTOTYPE CARDS
FIXED DISK
PRINTER
SDLCCOMM
BS COMM (SECONDARY)
BS COMM (PRIMARY)
IBM MONOCHROME DISPLAY/PRINTER
RESERVED
COLOR/GRAPHICS
RESERVED
DISKETIE
ASYNCH COMM (PRIMARY)
'-----AM/PM
SELECT
' - - -.......-----LEAP-YEAR
COUNTER
0= 12-HR !.lODE
1 = 24-HR !.lODE
O=AM
1 = PM
(0 IN 24-HR MODE)
0= LEAP YEAR
1 = 1 YR FROM LEAP YEAR
2 = 2 YRS FROM LEAP YEAR
3 = 3 YRS FROM LEAP YEAR
TL/F/8690-4
(b)
FIGURE 2. The MMS8274's control register (a), In
response to a nibble written to It, determines mode,
starts and stops the clock, and selects Interrupt
frequency. The status register (b), a read-only register,
Indicates changes In clock data and signals an
Interrupt. Both registers reside at address 0HEX, which
may be offset from location 0HEX In a host computer's
I/O space.
DATA CHANGED FLAG (DCF)
'-----ALWAyS
' - - - - - - - ALWAYS
a
a
'---------INTERRUPT FLAG
TLIF/8690-3
(a)
OBI
Note that the timing counters account for only 14 of the
chip's 16 addresses. The remaining two-0HEX and FHEXare described in Figures 2 and 3, respectively. Address
0HEX operates as a control register when written to and as a
status register when read from; address FHEX is the clocksetting or interrupt register, depending on the state of bit
DB2 in the control register. (Note that the 16MM58274 addresses can be offset from the IBM PC's 0HEX I/O address
space. The chip might occupy locations 300HEX to 30FHEX
in the computer's I/O space, for example, as Table I
shows.)
DBO
I
X
FUNCTION
NO INTERRUPT
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0.1 SEC
0.5 SEC
1 SEC
5 SEC
10 SEC
30 SEC
60 SEC
COMMENTS
INTERRUPT OUTPUT CLEARED
START / STOP BIT SET TO 1
DB3 = 0, SINGLE INTERRUPT
DB3 = 1, PERIODIC INTERRUPT
TLIF/8690-5
(b)
FIGURE 3. The state of bit DB2 In the control register at
address 0HEX selects one of two command registers at
address FHEX. If the control register's DB2 equals 0,
then FHEXbecomes the clock-setting register (a). If DB2
is 1, then FHEX becomes the Interrupt register (b).
TEST:
a = NORMAL
1 = TEST MODE
L-.---CLOCK START / STOP:
a = CLOCK RUN
1 = CLOCK STOP
'-------INTERRUPT SELECT:
a = CLOCK SETTING REGISTER
1 = INTERRUPT REGISTER
'---------INTERRUPT START/STOP:
a = INTERRUPT RUN
1 = INTERRUPT STOP
TL/F/8690-2
(a)
3-63
The control register (address 0HEX, write mode) selects normal or test mode, clock start and stop functions, and interrupt start and stop functions; the register also determines
whether the clock-setting register or the interrupt register
will be accessed by the next write to address FHEX. The
status register (address 0HEX, read mode) has only two active bits: the Interrupt flag and the Data Changed flag, which
is set if any of the timing counters change state during a
read operation. Both flags are cleared on completion of a
read operation. The clock-setting register (address FHEX,
control register bit DB2 = 0, write mode) is used only during
initialization to set 12- or 24-hr mode, the AM/PM flag (if the
clock is in 12-hr mode), and the number of years (zero to
three) since the last leap year. The interrupt register (address OFHEX, control register bit DB2 = 1, write mode) determines the interval at which interrupts (if any) are generated.
low for an I/O operation), and the upper six address bits (Ag
through A4). The base address of the MM58274 is set by
the six DIP switches connected to the corresponding Q inputs of the comparator. Address lines A3 through Ao are
connected directly to the MM58274 address inputs.
The 74HCT688 compares the eight P and Q inputs for
equality. When a P = Q condition becomes true, the comparator generates an active-low device-enable strobe
(DEN). This signal enables the MM58274, a MM74HCT164
(a wait-state generator), and a 74HCT245 bidirectional bus
driver connecting the clock data lines to the IBM bus. Pullup
and pulldown resistors on the bus driver force the upper
nibble of the IBM bus to 3HEX during an I/O read operation,
thus adding 30HEX to the BCD output of the clock to convert
the BCD number to the corresponding ASCII character.
You don't need to use DIP switches to change the base
address of the MM58274 (you could, for instance hard-wire
the address), but it's standard practice to include DIP
switches on I/O interface cards that are added to any microcomputer. Take care not to assign the same I/O address or
addresses to more than one device; if you do, I/O devices
will contend for the bus, with unpredictable results. Table 1
shows the standard I/O addresses recognized by PC-DOS
version 2 as well as the address space used by the
MM58274 (300HEX to 30FHEX) and, incidentally, by the popular AST Super-Pack card. If you have any other add-in
cards in your system, be sure to check the documentation
The I/O channel of the IBM PC is an extension of the 8088
microprocessor bus. The control, address, and data lines of
the IBM PC's I/O channel are essentially the same as those
of the 8088 p.P bus, but the PC's I/O channel also has
interrupt DMA (direct memory access) functions. In the PC,
however, I/O addresses are limited to the range 0HEX
through 03FFHEX, so that only 10 address lines (Ag through
Ao) need to be decoded. In the Figure 4 circuit, a 74HCT688
8-bit comparator, via its Po through P7 lines, decodes eight
signals: the negative-logic OR of lOR and lOW (the I/O read
and write strobes), the DMA strobe (AEN, which is always
SV
SV
SV
INT
iOR
iOW
DIP
AEN
Ag
Aa
A7
As
As
A,
------------------------+
SV
WAIT-STATE
GENERATOR
S.1 kA
0,
Os
SV
REAL mlE
CLOCK
lrh
A
B Vee
iOW
ClK
WR
Os
OJ
7
DBs 6
14
13 Bs
DBs S
12 Bs
DB7 ,
11 B7
Ba
DBa
Do
01
O2
03
BATTERY NEG
-=
iOR
BIDIRECnONAl
BUS DRIVER
Tl/F/8690-6
FIGURE 4. The MM58274 requires relatively few support chips: Adding a bidirectional bus driver, a walt-state
generator, and an address decoder lets you Implement all essential functions of the MM58274.
3-64
to determine which addresses they use, so you can avoid
I/O address duplication.
When Os shuts off, the power-failure circuitry disables the
clock chip by forcing the CS (chip select) signal high. The
CS signal is the negative-logic AND of DEN (the device-enable signal) and PFD, both of which are active-low. If either
one goes high (because the clock is not being addressed, or
because system power is low or off), the two sections (IC4A
and IC4B in Figure 4) of the 74HCT02 drive the CS input
high to disable the clock chip.
ISOLATION PROLONGS BATTERY LIFE
The battery-isolation circuits in Figure 4 prevent reverse current from flowing through the battery when the main power
supply is on, and they minimize current drain in the battery
backup mode. Diode D3 (Figure 4) isolates the battery during system power-up. As long as the system power supply is
at least one diode drop (0.6V) above the battery voltage
( - 3V), diode D3 is reverse-biased, and no current can flow
into or out of the battery. If the supply voltage drops below
this level, the battery powers the clock.
TIMING CONSIDERATIONS
Your interface circuitry will have to compensate for some
incompatibility between the PC and the MM58274. The IBM
PC requires that data be read from a device in three clock
cycles (630 ns). However, the read-access time of the
MM58274 is 850 ns. To slow down the computer, you need
a wait-state signal that pulls the I/O CH RDY bus line low for
one or more clock cycles. The wait-state generator (Figure
4) consists of an MM74HCT164 shift register, a negativelogic AND gate (IC4C, one section of a 74HCT02 NOR chip),
and an open-collector inverter (ICIC, one section of a
74LS03). Until the clock is addressed, DEN remains high,
clearing the shift register via inverter ICl B; at this time the
OH output of the shift register is low. When the clock is
addressed, DEN goes low, removing the CLR signal from
the shift register and enabling the s'econd input of IC4C so
that liD GH RDY goes low and puts the microprocessor into
a wait state. Subsequent clock pulses gradually fill the shift
register with ones, starting from the left. The number. of wait
states generated depends on which output of the shift register you use. This application uses the last tap, so that the
microprocessor is delayed for eight clock pulses (8 X 210
ns). The delay allows plenty of time for MM58274 read and
write operations to take place. When the OH output goes
high, I/O CH RDY also goes high to terminate the wait
state.
To prolong battery life in standby mode, you should elimi. nate all leakage paths to ground. Don't insert a switch in the
+ 5V bus, though; that alone would be ineffective, as Figure
5 shows. A ground-disconnect switch (02 in Figures 4 and
5) eliminates leakage from the RD, WR, and CS pins
through the protection diodes. However, even when the
ground-disconnect switch is open, a leakage path still exists
through the INT pin and an open-drain transistor to ground;
thus, a second switch (03) is needed to open this path also.
When the system powers down, transistor 01 shuts off,
thereby also shUtting off 02 (the ground-disconnect switch),
03 (the interrupt-disconnect switch), and Os (the power-failure detector). Shutting off these transistors not only isolates
the negative terminal of the battery from the system ground
bus but also breaks the leakage paths indicated in Figure 5.
5V DISCONNECT
(INEFFECTIVE; NOT IMPLEMENTED)
.----.
•
.....,.•
r-------...--~
BLOCKING
DIODE 03
5V BUS
I
SOURCE
: RESISTANCE
I OF POWER
I
SUPPLY
I
(IN
I POWER-OFF
: MODE)
BATTERY
GROUND DISCONNECT
Another incompatibility between the IBM PC and the
MM58274 occurs in the write-cycle specification, two (Data
Bus Hold Time Following Write strobe). The MM58274 requires the system to hold data for 200 ns after the end of
the write strobe, whereas the IBM PC holds data on the bus
for only 100 ns. However, by disabling the bus driver immediately after writing data to the MM58274, the 3-state capacitance (typically 25 pF) of the bus driver maintains the
data on the clock lines for a period of time after the end of
the write stobe. When this technique was used experimentally, the typical measured values of the Data Bus Hold Time
ranged from 500· to 600 ns.
R3
SYSTEM
GROUND BUS
°2
TLlF/8690-7
The time-base reference of the MM58274 is a 32.768-KHz
pulse obtained from a crystal-controlled internal oscillator.
One side of the crystal is loaded with a 20-pF fixed capacitor and the other side with a 6- to 36-pF trimmer capacitor
(Figure 4). For accurate timekeeping (within 30 sec/month),
you must adjust this trimmer capacitor so that the crystal
oscillates at the correct frequency. You shouldn't connect
measuring instruments directly across the crystal, because
FIGURE 5. J'o prevent leakage from the battery .vla CS,
RD, WR, and INT, you must break the INT path and
disconnect battery negative from system ground. A
switch in the + 5V lead wouldn't break the leakage
paths and thus Isn't implemented.
3-65
if you were to do so, the capacitance of the leads and instrument would change the oscillator frequency. However, writing 8HEX to the MM58274's control register places
MM58274 in the test mode. In the test mode, the crystal
oscillator's output is diverted to pin 13 (INT) to provide a
buffered signal for an oscilloscope or frequency counter.
24-hr display mode and, if you select 12-hr mode, to set AM
or PM. You will then be prompted to enter the number of
years since the last leap year, the day of the week, and the
current date and time. Each item is written to the MM58274
when you enter it. The clock starts when you press any key,
and you exit to PC-DOS. The next time you wish to initialize
the hardware, invoke RTCWR without the C option, unless
you wish to recalibrate the oscillator.
PROGRAM THE MM58274 TO PRODUCE INTERRUPTS
You can program the clock chip to produce a single interrupt or repetitive interrupts at anyone of seven intervals
from 0.1 to 60 sec by loading the interrupt register (Figure
3). To make use of interrupts, connect the INT output from
transistor Os (Figure 4) to one of the IRO lines of the IBM
PC bus. Six of the eight interrupt levels are reserved for IBM
devices; only IR03 and IROs are available for use with the
clock. If you have other add-in cards that use interrupts,
however, IR03 and IROs may be pre-empted, so you won't
be able to use interrupts.
To read the real-time clock, run the program RTCRD.EXE.
In short, the program reads the date, places it in a temporary buffer, and displays it. It then reads and displays the
time in the same manner. All data reads are validated by
means of the Data Changed flag. The program also writes
the date and time into the PC-DOS software clock.
RTCRD calls the BIOS display by using the following instruction sequence:
MOV AH, 2
MOV BH, 0
MOV DH, ROW
MOV DL, COL
INT 10H
To integrate the hardware clock/calendar into your system,
you use two 8088 assembly-language programs (the source
listings are coded for DOS 2.0). The first, RTCWR (see listing 1) allows you to put the MM58274 either in test mode to
calibrate the crystal clock or in normal mode to initialize time
and date. The other routine, RTCRD (see Listing 2) reads
the clock, displays the date and time in the upper right corner of the screen, and writes the date and time into the
software clock that PC-DOS maintains. Thus, if your
AUTOEXEC.BAT file invokes RTCRD, the routine automatically updates the PC-DOS clock from the hardware clock
whenever you turn on the system.
This call displays the day, date, and time in the upper right
corner of the screen. You can change the location of the
display by changing the values for row and column (ROW
and COL).
Date and time information needs to be validated by means
of the Data Changed flag (DC F), because a carry pulse from
one counter may ripple through other counters in the chain.
It is possible (although statistically improbable) that an incorrect data read may occur during this ripple period.
RTCRD assures that data is valid by reading the DCF in the
control register twice. The first read, which RTCRD performs before reading any other register, clears the DCF to
zero. Then after RTCRD reads all the other registers, it
reads the DCF again; if this flag is set, a change in data has
occurred and the data read is invalid; otherwise, the data is
good.
Incidentally, RTCWR and RTCRD don't contain routines to
perform keyboard input and screen output; they use standard function calls to DOS and BIOS routines (of which a
complete listing is given in the IBM PC Technical Reference
Manualj to perform these functions. Placing a function code
in the AH register and executing the appropriate softwareinterrupt instruction invokes these routines. The PC DOS
Programmer's Manual gives full details on how to make
service requests of this kind.
When you invoke RTCRD from your AUTO-EXEC. BAT file,
you ensure that the PC-DOS clock will be automatically updated from the MM58274 whenever you turn the system on
or reset it. If you do not have an AUTOEXEC.BAT file, create one as follows:
After assembling and linking the RTCWR.ASM and
RTCRD.ASM programs, copy the resulting RT-CWR.EXE
and RTCRD.EXE files to your system disk. To calibrate the
crystal oscillator, connect an· oscilloscope or frequency
counter between pin 13 of the MM58274 and ground. At the
A> prompt, type the following command:
• Enter COPY CON: AUTOEXEC.BAT and press the Return
key.
RTCWR/C
• Enter RTCRD and press the Return key.
The C option puts the clock in the test mode, diverting the
32.768-kHz oscillator output through a buffer to pin 13 of the
chip. Adjust the trimmer capacitor until the frequency is correct. Then type "S" to exit from the calibration mode to the
time-setting mode. RTCWR will prompt you to select 12- or
• Press the F6 function key and then the Return key to write
an end-ot-tile mark and save the new AUTOEXEC.BAT
file.
It you already have an AUTOEXEC.BAT file, use your normal editor to insert "RTCRD" as the tirst line in the tile.
3-66
LISTING 1-RTCWR.ASM
THIS PROGRAM WRITES TO THE REAL-TIME CLOCK (MM58274)
DATA IS ENTERED FROM THE KEYBOARD AND THEN IS WRITTEN
TO. THE MM58274. ALSO, THE CALIBRATION OF THE CRYSTAL
CAN BE PERFORMED VIA THIS PROGRAM.
TABLE OF EQUATES
REGO
REGl
REG2
REG3
REG4
REG5
REG6
REG7
REG8
REG9
REGIO
REGll
REG12
REG13
REG14
REG15
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
300H
301H
302H
303H
304H
305H
306H
307H
308H·
309H
30AH
30BH
30CH
30DH
30EH
30FH
;CONTROL REGISTER
;TENTHS OF SECONDS
;UNITS OF SECONDS
;TENS OF SECONDS
;UNITS OF MINUTES
;TENS OF MINUTES
;UNITS OF HOURS
;TENS OF HOURS
;UNITS OF DAYS
;TENS OF DAYS
;UNITS OF MONTHS
;TENS OF MONTHS
;UNITS OF YEARS
;TENS OF YEARS
;DAYS
;CLOCK SETTING AND INTERRUPT REGISTER
STACK SEGMENT PARA STACK 'STACK'
DB
256 DUP(O)
;256 BYTES OF STACK SPACE
STACK ENDS
DATA SEGMENT PARA PUBLIC 'DATA'
DB·
PARM
8 DUP(O)
;BUFFER SPACE FOR DATE AND TIME
DB
16 DUP(O)
BUFFl
'12/24 Hour mode selection:
MSGO
DB
Enter '0' for 12 hour mode or
DB
MSGI
DB
enter '1' for 24 hour mode.
MSG2
'AM/PM Mode selection. Enter 'A' or 'Pl.
DB
MSG3
MSG4
DB
'No. of yrs. from last leap year (0-3)
DB
MSG5
'Enter date - (MM/DD/YY)
DB
'Enter time - (HR:MM:SS)
MSG6
DB
'Hit any key to start clock
MSG7
• • • INVALID ENTRY. •.• TRY AGAIN '
MSG8
DB
'Enter day- '1' for Sun, '2' for Mon, etc.'
MSG9
DB
'In calibration mode. Adjust trimmer cap. '
MSGIO
DB
'so that osc. output = 32.768 KHz. Measure'
MSGll
DB
'this is INTR, output (pin 13)
MSG12
DB
'When finished, hit key's' to set clock
MSG13
DB
DATA ENDS
STANDARD PROGRAM PROLOG
-RETURNS CONTROL TO DOS AFTER TERMINATION OF PROGRAM
3·67
.
~
"1:1"
"1:1"
Z
<
LISTING 1-RTCWR.ASM (Continued)
CODE SEGMENT PARA PUBLIC 'CODE'
PUBLIC START
START PROC FAR
ASSUME CS:CODE
PUSH
DS
MOV
AX,O
PUSH
AX
MOV
AX ,DATA
MOV
ES,AX
ASSUME ES:DATA
;START MAIN PROGRAM
.
;SAVE RETURN ADDR. TO DOS
;
:LOAD DATA SEGMENT ADDR.
; MOVE PARAMETERS FROM COMMAND LINE INTO DATA SEGMENT
MOV
MOV
MOV
CLD
REP
SI,80H
DI,OFFSET PARM
CX,8
;MOVE TO PARM. LIST IN PSP
;SET STRING MOVE FORWARD
;MOVE STRING
MOVSB
ESTABLISH NORMAL DATA SEGMENT ADDRESSIBLY
MOV
ASSUME
DS,AX
DS:DATA
CHECK TO SEE IF WE GO INTO CALIBRATION MODE
CMP
JNZ
PARM,3
SET
;IS CHAR. LENGTH = 3?
;NO, BRANCH AND SET CLOCK
CALIBRATE TRIMMER CAPACITOR
CLI
MOV
AL,OFH
MOV
OUT
MOV
MOV
OUT
MOV
CALL
MOV
CALL
MOV
CALL
CALL
CALL
MOV
CALL
DX,REGO
DX,AL
AL,O
DX,REG15
DX,AL
BX,OFFSET
DISPLAY
BX,OFFSET
DISPLAY
BX,OFFSET
DISPLAY
CR_LF
CR_LF
BX,OFFSET
DISPLAY
;CLEAR INTR OF 8088
:WRITE TO CONTROL REG.
-IN TEST MODE
-STOP CLOCK
-SELECT INTR REG
-STOP INTR
;GATE OSC. OUTPUT TO INTR. PIN
MSGIO
;DISPLAY MESSAGES
MSGll
MSG12
;TWO AND
MSG13
3-68
LISTING 1-RTCWR.ASM (Continued)
LUP8:
MOV
INT
CMP
JE
CMP
JE
JMP
AH,O
16H
AL, IS'
SET
AL, IS'
SET
LUP8
;FUNCTION=READ CHAR. FROM KEYBOARD
;INVOKE BIOS ROUTINE
;IS CHAR. AN'S'
;YES, BRANCH AND SET CLOCK
;IS CHAR. AN's'?
;YES, BRANCH AND SET CLOCK
;WAIT, CRYSTAL IS BEING ADJUSTED
INITIALIZE RTC FOR SETTING IT
SET:
STI
MOV
AL,07H
MOV
OUT
MOV
MOV
OUT
MOV
MOV
OUT
DX,REGO
DX,AL
AL,O
DX,REG15
DX,AL
AL,5
DX,REGO
DX,AL
;WRITE TO CONTROL REG
-CLOCK STOP
-INTR REG SELECTED
-INTR STOP
;CLEAR INTERRUPT OUTPUT
;WRITE TO CNTL REG
-CLOCK SETTING REG SELECTED
DETERMINE 12 OR 24 HOUR MODE
LP1:
LUP1:
MOV
CALL
MOV
CALL
MOV
CALL
CALL
CALL
CMP
JE
CMP
JE
MOV
CALL
JMP
BX,OFFSET
DISPLAY
BX,OFFSET
DISPLAY
BX,OFFSET
DISPLAY
INPCHAR
DISPCHAR
AL,'O'
MD12
AL, '1'
MD24
BX,OFFSET
DISPLAY
LUPl
MSGO
MSGl
MSG2
MSG8
;LOAD STARTING ADDR. OF MSGO
;DISPLAY MESSAGE
;LOAD STARTING ADDR. OF MSGl
;DISPLAY MESSAGE
;LOAD STARTING ADDR. OF MSG2
;DISPLAY MESSAGE
;INPUT CHAR. FROM KEYBOARD
;ECHO CHAR.
;IS CHAR. FROM KEYBOARD to'?
;YES, JUMP TO 12 HOUR ROUTINE
;IS CHAR. FROM KEYBOARD Ill?
;YES, JUMP TO 24 HOUR ROUTINE
;LOAD STARTING ADDR. OF MSG8
;DISPLAY ERROR MESSAGE
;GO BACK AND TRY AGAIN
IN 12 HOUR MODE - SET LEAP YEAR AND AM/PM MODE
MD12:
CALL
MOV
MOV
OUT
CALL
CALL
CR_LF
AL,O
DX,REG15
DX,AL
AMPM
CR_LF
; AND
;LOAD CODE FOR 12 HOUR MODE
;SELECT AM OR PM TIME
; AND
3·69
LISTING 1-RTCWR.ASM (Continued)
CALL
CALL
JMP
LEAp·
CR_LF
DAY
;ENTER NO. OF YRS. FROM LEAP YR.
; AND
:GOTO TO INPUT DAY ROUTINE
IN 12 HOUR MODE - SET LEAP YEAR
MD24:
CALL
MOV
MOV
OUT
CALL
CALL
; AND
AL,l
DX,REG15
DX,AL
LEAP
CR_LF
;LOAD CODE FOR 24 HOUR MODE
;ENTER NO. OF YRS. FROM LEAP YR.
; AND
INPUT DAY OF WEEK - '1' FOR SUN, '2' FOR MON, ETC.
DAY:
LUP7:
ERR2:
MOV
CALL
CALL
CALL
CMP
JG
CMP
JL
MOV
OUT
CALL
JMP
MOV
CALL
JMP
BX,OFFSET MSG9
DISPLAY
INPCHAR
DIPSCHAR
AL, '7'
ERR2
AL, '1'
ERR2
DX,REG14
DX,AL
CR_LF
DATE
BX,OFFSET MSG8
DISPLAY
LUP7
;DISPLAY MESSAGE
;INPUT CHAR.
;ECHO IT
;IS CHAR. OUT OF RANGE?
;NO, LOAD IN DAY
;CARRIAGE RTRN AND LINE FEED
;DISPLAY ERROR MESSAGE
INPUT DATA INTO A BUFFER
DATE:
MOV
CALL
CALL
CALL
BX,OFFSET MSG5
DISPLAY
BUFFER
CR_LF
;LOAD STARTING ADDR. OF MSG5
;DISPLAY MESSAGE
;INPUT DATA INTO A BUFFER
; AND
; WRITE DATA OF BUFFER INTO REAL-TIME CLOCK
MOV
MOV
MOV
OUT
INC
MOV
MOV
OUT
INC
INC
MOV
MOV
BX,OFFSET BUFFl
AL,[BXl
DX,REGll
DX,AL
BX
AL,[BXl
DX,REGIO
DX,AL
BX
BX
AL,[BXl
DX,REG9
;MOVE TO STARTING ADDR. OF BUFFER
;WRITE THE TENS OF MOnTHS
;WRITE THE UNITS OF MONTHS
3·70
LISTING 1-RTCWR.ASM (Continued)
OUT
INC
MOV
MOV
OUT
INC
INC
MOV
MOV
OUT
INC
MOV
MOV
OUT
DX,AL
BX
AL,[BX]
DX,REG8
DX,AL
BX
BX
AL,[BX]
DX,REGl3
DX,AL
BX
AL,[BX]
DX,REGl2
DX,AL
;WRITE THE TENS OF DAYS
;WRITE THE UNITS OF DAYS
;WRITE THE TENS OF YEARS
;WRITE THE UNITS OF YEARS
INPUT TIME OF DAY INTO A BUFFER
MOV
CALL
CALL
CALL
BX,OFFSET MSG6
DISPLAY
BUFFER
CR_LF
;LOAD STARTING ADDR. OF MSG6
;DISPLAY MESSAGE
;INPUT DATA INTO BUFFER
; AND
; WRITE THE TIME OF DAY INTO REAL-TIME CLOCK
MOV
MOV
MOV
OUT
INC
MOV
MOV
OUT
INC
INC
MOV
MOV
OUT
INC
MOV
MOV
OUT
INC
INC
MOV
MOV
OUT
INC
MOV
BX,OFFSET BUFFl
AL,[BX]
DX,REG7
DX,AL
BX
AL,[BX]
DX,REG6
DX,AL
BX
BX
AL,[BX]
DX,REG5
DX,AL
BX
AL,[BX]
DX,REG4
DX,AL
BX
BX
AL,[BX]
DX,REG3
DX,AL
BX
AL,[BX]
;MOVE TO STARTING ADDR. OF BUFFER
;WRITE THE TENS OF HOURS
'jWRITE THE UNITS OF HOURS
;WRITE THE TENS OF MINUTES
;WRITE THE UNITS OF MINUTES
;WRITE THE TENS OF SECONDS
3-71
LISTING 1-RTCWR.ASM (Continued)
MOV
OUT
DX,REG2
DX,AL
;WRITE THE UNITS OF SECONDS
START CLOCK ON KEY STRIKE
LP6:
MOV
CALL
MOV
BX, OFFSET MSG7
DISPLAY
AH,I
MOV
OR
INT
BH,O
BH,BH
I6H
JZ
MOV
MOV
OUT
RET
LP6
AL,O
DX,REGO
DX,AL
;LOAD STARTING ADDR. OF MSG7
;DISPLAY MESSAGE
;FUNCTION = INPUT FROM KEYBOARD
AH IS A FUNCTION PARAMETER IN BIOS ROUTINE
;SET ZF = I
;INVOKE BIOS ROUTINE RETURNS ZF = 0 IF KEY IS STRUCK
OTHERWISE ZF = I
;LOOP BACK IF ON KEY IS STRUCK
;GIVE START COMMAND TO CLOCK
;RETURN TO DOS
;-----------------------------------------------------------------------------------------"BUFFER" SUBROUTINE
-STORES THE DATE OR TIME OF DAY IN a BYTE
BUFFER. STARTING LOCATION OF BUFFER IS AT
LABEL BUFFI
ENTRY: NONE
OUTPUT: BUFFI ARRAY CONTAINS TIME OR DATE
AX,BX,CX ALTERED
;------------------------------------------------------------------------------------------
PUBLIC BUFFER
BUFFER PROC NEAR
INPUT: MOV
CL,9
BX,OFFSET BUFFI
MOV
CALL
INP:
INPCHAR
CALL
DISPCHAR
[BX],AL
MOV
DEC
CL
BX
INC
AL,ODH
CMP
JE
CK
INP
JMP
CL,a
CMP
CK:
JE
EXITl
CL,O
CMP
EXITl
JE
MOV
BX,OFFSET MSGa
CALL
DISPLAY
JMP
INPUT
EXITl: RET
BUFFER ENDP
;MOVE TO STARTING ADDR. OF BUFFER
;INPUT CHAR. FROM KEYBOARD
;ECHO CHAR.
;IS CHAR. A CARRIAGE RETURN?
;YES, JUMP
;NO, GO BACK AND INPUT ANOTHER CHAR.
;IS FIRST CHAR. A ?
;YES, DON'T CHANGE BUFFER • • • • EXIT
;IS LAST CHAR. A < CR> ?
;YES, BUFFER FULL • • • • EXIT
;LOAD STARTING ADDR. OF MSGa
;DISPLAY ERROR MESSAGE
;RELOAD BUFFER
3-72
.LlSTING 1-RTCWR.ASM (Continued)
;-----------------------------------------------------------------------------------------;"AMPM', SUBROUTINE - INPUTS AN 'A' OR A 'P' FROM THE KEYBOARD VIA BIOS
TO SET AM OR PM TIME
ENTRY: NONE
OUTPUT: AX,BX ALTERED
;------------------------------------------------------------------------------------------
PUBLIC
AMPM PROC NEAR
LP4:
MOV
CALL
LUP2:
CALL
CALL
CMP
JE
CMP
JE
CMP
JE
CMP
JE
MOV
CALL
JMP
AM:
MOV
MOV
OUT
JMP
PM:
MOV
MOV
OUT
EXI:
RET
AMPM ENDP
AMPM
BX,OFFSET MSG3
DISPLAY
INPCHAR
DISPCHAR
AL, 'A'
AM
AL, 'a'
AM
AL, 'p'
PM
AL, 'P'
PM
BX,OFFSET MSG8
DISPLAY
LUP2
AL,O
DX,REGl5
DX,AL
EXI .
AL,2
DX,REGl5
DX,AL
;LOAD STARTING ADDR. OF MSG3
;DISPLAY MESSAGE
;INPUT CHAR. FROM KEYBOARD
;ECHO CHAR.
;IS CHAR. AN 'A'?
;YES, SET AM TIME
;IS CHAR. AN 'a'
;YES, SET AM TIME
;IS CHAR. A 'p'
;YES, SET PM TIME
;IS CHAR. A 'P'?
;YES, SET PM TIME
;LOAD STARTING ADDR. OF MSG8
;DISPLAY ERROR MESSAGE
;BAD ENTRY • • • • RENTER CHAR.
;LOAD CODE FOR AM TIME
;LOAD CODE FOR PM TIME
;-----------------------------------------------------------------------------------------;"LEAP"
SUBROUTINE - INPUTS A NUMBER FROM 0 TO 3 FROM TO KEYBOARD. THIS
NUMBER IS THE NUMBER OF YEARS FROM LAST LEAP YEAR.
ENTRY: NONE
OUTPUT: AX,BX,CX ALTERED
;------------------------------------------------------------------------------------------
PUBLIC
LEAP PROC NEAR
LP5:
MOV
CALL
LUP3:
CALL
CALL
CMP
JAE
CMP
JL
AND
MOV
LEAP
BX,OFFSET MSG4
DISPLAY
INPCHAR
DISPCHAR
AL, '4'
ERRl
AL, '0'
ERRl
AL,OFH
CL,2
;LOAD STARTING ADDR. OF MSG4
;DISPLAY MESSAGE
;INPUT CHAR. FROM KEYBOARD
;ECHO CHAR.
;CHECK FOR INVALID ENTRY
;CLEAR UPPER NIBBLE OF AL
3-73
C")
~
~
Z•
ct
LISTING 1-RTCWR.ASM (Continued)
ROL
MOV
MOV
IN
AND
OR
OUT
JMP
ERRI:
MOV
CALL
JMP
RTRN:
RET
LEAP ENDP
AL,CL
BL,AL
DX,REGI5
AL,DX
AL,03H
AL,BL
DX,AL
RTRN
BX,OFFSET MSG8
DISPLAY
LUP3
;ROTATE LEFT TWO TIMES
;SAVE AL IN BL
;INPUT CLOCK SETTING REG
;CLEAR DB3 TO DB2
;WRITE TO ONLY DB3, DB2 OF CLK SET. REG
;LOAD STARTING ADDR. OF MSG8
;DISPLAY ERROR MESSAGE
;GO BACK AND TRY AGAIN
;----------------------------------------------------- ------~------------------------------
"INPCHAR', SUBROUTINE - INVOKES BIOS ROUTINE TO INPUT CHARACTER FROM
KEYBOARD
ENTRY: NONE
OUTPUT: AX ALTERED
;-----------------------------------------------------------------------------------------PUBLIC INPCHAR
INPCHAR PROC NEAR
MOV
AH,O
INT
RET
INPCHAR ENDP
ISH
;FUNCTION = INPUT CHAR. INTO AL
AH IS A FUNCTION PARAMETER FOR BIOS ROUTINE
;INVOKE BIOS ROUTINE
;-----------------------------------------------------------------------------------------"DISPLAY"
SUBROUTINE - DISPLAYS MESSAGES AT MEMORY LOCATIONS MSGO TO MSGI5.
USES DISPCHAR SUBROUTINE FOR BIOS CALL
ENTRY:
BX= OFFSET OF MESSAGE
OUTPUT: AX,CX ALTERED
;-------------------------------------------------------------------------~----------------
PUBLIC DISPLAY
DISPLAY PROC NEAR
MOV
CX,40
AL,[BX]
DISPI: MOV
CALL
DISPCHAR
INC
BX
LOOP
DISPI
CR_LF
CALL
RET
DISPLAY ENDP
;LOAD MESSAGE CHAR. COUNTER
;SINGLELY LOAD CHAR. OF MESSAGE
;DISPLAY THAT CHAR.
;LOOP BACK 40 TIMES
; AND
;------------------------------------------------~----------------------------------------;"DISPCHAR" SUBROUTINE - INVOKES BIOS ROUTINE TO DISPLAY A CHARACTER
ON THE SCREEN
ENTRY: NONE
OUTPUT: AX ALTERED
;------------------------------------------------------------------------------------------
3-74
LISTING 1-RTCWR.ASM (Continued)
PUBLIC DISPCHAR
DISPCHAR PROC NEAR
PUSH
BX
MOV
BX.O
MOV
AH.14
INT
POP
RET
DISPCHAR ENDP
lOH
BX
jSAVE REC. BX
jFUNCTION = WRITE TO SCREEN
JAH IS A FUNCTION PARAMETER FOR BIOS ROUTINE
jINVOKE BIOS ROUTINE
jRESTORE REG. BX
;-----------------------------------------------------------------------------------------j"CR_LF"
SUBROUTINE - PRODUCES A CARRIAGE RETURN AND LINE FEED ON THE
SCREEN.
ENTRY:
NONE
OUTPUT: ALL REGISTERS PRESERVED
;------------------------------------------------------------------------------------------
PUBLIC CR_LF
CR_LF PROC NEAR
PUSH
AX
MOV
AL.ODH
CALL
DISPCHAR
MOV
AL.OAH
CALL
DISPCHAR
POP
AX
RET
CR_LF ENDP
START ENDP
CODE ENDS
END
jSAVE AX
jCARRIAGE RETURN
jLINE FEED
jRESTORE AX
jEND OF MAIN PROGRAM
START
3-75
LISTING 2-RTCRD.ASM
THIS PROGRAM READS FROM THE REAL-TIME CLOCK (MM582774).
DATA IS READ FROM THE MM58274 AND CHECK WITH THE 'DATA
CHANGED FLAG'. THE TIME AND DATE IS,DISPLAYED IN THE
UPPER RIGHT CORNER. THE PROGRAM ALSO WRITES THE TIME
AND DATE TO INITIALIZE THESE FUNCTIONS IN PC DOS.
TABLE OF EQUATES
REGO
REGl
REG2
REG3
REG4
REG5
REG6
REG7
REG8
REG9
REGlO
REGll
REGl2
REG13
REG14
REG15
EQU
EQU
EQU
EQU
EQU
EQU
EQU
,EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
300H
30lH
302H.
303H
304H
305H
306H
307H
308H
309H
30AH
30BH
30CH
30DH
30EH
30FH
;CONTROL REG
;TENTHS OF SEC
;UNITS OF SEC
;TENS OF SEC
;UNITS OF MINUTES
;TENS OF MINUTES
;UNITS OF HOURS
;TENS OF HOURS
;UNITS OF DAYS
;TENS OF DAYS
;UNITS OF,MONTHS
;TENS OF MONTHS
;UNITS OF YEARS
;TENS OF YEARS
;DAY OF WEEK
;CLOCK SETTING AND INTERRUPT REG
STACK SEGMENT PARA STACK 'STACK'
DB
256 DUP(O)
STACK ENDS
DATA SEGMENT PARA'PUBLIC 'DATA'
MON_NO DB
0
MONTH
DB
'JAN', 'FEB', 'MAR', 'APR', 'MAY', 'JUN', 'JUL', 'AUG', 'SEP'
'OCT', 'NOV', 'DEC'
DB
DAY
'SUNDAY
','MONDAY
','TUESDAY
','WEDNESDAY
DB
'THURSDAY
','FRIDAY
','SATURDAY
DB
DATE
;***ARRAY FOR DATE
DB
'MMM DD, 19YR'
;***ARRAY FOR TIME
TIME
DB
'HR:MM:SS
MON_LEN DB
;NO. OF CHARS. IN A MONTH
3
DALLEN DB
;NO. OF CHARS. IN A DAY
12
D_OF_W DB
;LOCATIONTO SAVE THE 'DAY OF WEEK'
o
DATA ENDS
CODE SEGMENT PARA PUBLIC 'CODE'
PROGRAM PROLOG - RETURN TO DOS AT TERMINATION OF PROGRAM
PUBLIC START
START PROC FAR
ASSUME CS: CODE
PUSH
DS
MOV
AX,O
PUSH
AX
;BEGIN MAIN PROGRAM
;SAVE RETURN ADDR. FOR DOS
3-76.
-------------------------------------------------------------------------, >
z
LISTING 2-RTCRD.ASM (Continued)
MOV
AX, DATA
MOV
DS,AX
MOV
ES,AX
ASSUME DS: DATA,ES:DATA
J:,..
~
w
;DATA AND EXTRA SEGMENT ARE THE SAME
PERFORM DUMMY READ OF CNTL REG TO SET DCF = 0
READ:
MOV
IN
DX,REGO
AL,DX
; READ DAY OF WEEK
MOV
IN
MOV
READ
ADD1:
TEN:
DX,REG14
AL,DX
D_OF_W,AL
;READ DAY - CODE IS 1-7 WHERE SUN.
;SAVE DAY OF WEEK
DATE
MOV
IN
SUB
CMP
JE
MOV
MOV
MOV
IN
SUB
ADD
MOV
SUB
MUL
MOV
ADD
MOV
CALL
INC
MOV
IN
CMP
JNE
MOV
MOV
INC
MOV
IN
MOV
ADD
MOV
IN
MOV
DX,REGll
AL,DX
AL,30H
AL,O
ADD1
AL,lOD
BL,AL
DX,REG10
AL,DX
AL,30H
AL,BL
MON_NO,AL
AL,l
MON_LEN
SI,OFFSET MONTH
SI,AX
DI,OFFSET DATE
MOV_STR
DI
DX,REG9
AL,DX
AL,30H
TEN
AL,' ,
[DI],AL
DI
DX,REG8
AL,DX
[DI],AL
DI,5
DX,REG13
AL,DX
[DI],AL
;READ TENS OF MONTHS
;CONVERT TO BCD
;IS MONTHS=O
;YES, JUMP
;NO, SET MONTHS = 10
;SAVE AL IN BL
;READ UNITS OF MONTHS
;CONVERT TO BCD
;(TENS OF MONTH) + (UNITS OF MONTHS)
;SAVE THE MONTH NUMBER
;AX=AL* (NO. OF CHARS. IN A MONTH)
;SI=STARTING ADDR. OF ARRAY 'MONTH'
;SI=OFFSET INTO ARRAY 'MONTH'
;DI=STARTING ADDR. OF ARRAY 'DATE'
;MOVE MONTH INTO 'DATE' ARRAY
;READ TENS OF DAYS
;IS 'TENS OF DAYS' = 0
;NO, JUMP
;YES, MOVE IN A BLANK FOR TENS OF DAYS
;MOVE IT INTO 'DATE' ARRAY
;READ UNITS OF DAYS
:MOVE IT INTO 'DATE' ARRAY
;READ TENS OF YEARS
;MOVE IT INTO 'DATE' ARRAY
3-77
1
C")
-.::t'
-.::t'
:2:
LISTING 2-RTCRD.ASM (Continued)
INC
MOV
IN
MOV
ct
DI
DX,REG12
AL,DX
[DI],AL
iREAD UNITS OF YEARS
iMOVE IT INTO 'DATE' ARRAY
i READ TIME OF DAY AND MOVE IT INTO ARRAY 'TIME'
MOV
BX,OFFSET TIME
iMOVE TO STARTING ADDR. OF ARRAY 'TIME'
MOV
DX,REG7
IN
AL,DX
iREADS TENS OF HOURS
[Bx1,AL
iMOVE IT INTO 'TIME' ARRAY
MOV
INC
BX
MOV
DX,REG6
IN
AL,DX
iREAD UNITS OF HOURS
[BX],AL
MOV
iMOVE IT INTO 'TIME' ARRAY
ADD
BX,2
DX,REG5
MOV
IN
iREAD TENS OF MINUTES
AL,DX
MOV
[Bx1,AL
INC
BX
MOV
DX,REG4
IN
AL,DX
iREAD UNITS OF MINUTES
MOV
[Bx1,AL
ADD
BX,2
MOV
DX,REG3
IN
AL,DX
iREAD TENS OF SECONDS
[BX] ,AL
MOV
INC
BX
DX,REG2
MOV
IN
AL,DX
iREAD UNITS OF SECONDS
MOV
[Bx1,AL
i DATA VALIDATION CHECK
MOV
IN
TEST
JZ
JMP
DX,REGO
AL,DX
AL,08H
DSPLY
READ
iREAD CNTL REG
iIS DCF=l?
;NO, DISPLAY DATE AND TIME
iYES, INVALID DATE • • • • READ AGAIN
i DISPLAY DATE AND TIME
DSPLY
MOV
SUB
MUL
AL,D_OF_W
AL,31H
DALLEN
MOV
ADD
MOV
BX,OFFSET DAY
BX,AX
DX,0040H
iAL = 'DAY OF WEEK'
iCONVERT ASCII TO BCD
iAX=AL* (DAY_LEN) ••• CALCULATING OFFSET INTO
ARRAY 'DAY'
iMOVE TO STARTING ADDR OF ARRAY 'DAY'
' ;
iBX= STARTING ADDR OF DAY STRING
iDH AND DL PARAMETERS TO BE SENT TO BIOS
DH=ROW DL=COL
3-78
'LISTING 2-RTCRD.ASM (Continued)
CALL
CALL
MOV
MOV
CALL
CALL
MOV
MOV
CALL
CALL
SET_CURSOR
DISPLAY
BX,OFFSET DATE
DX,0140H
SET_CURSOR
DISPLAY
BX,OFFSET TIME
DX,0240H
SET_CURSOR
DISPLAY
;MOVE CURSOR TO ROW 0, COL 48
;DISPLAY THE DAY
;MOVE TO STARTING ADDR OF ARRAY 'DAY'
;SET CURSOR TO ROW 1, COL 48
;DISPLAY THE DATE
;MOVE TO STARTING ADDR. OF ARRAY 'DATE'
;SET CURSOR TO ROW 2, COL 48
;DISPLAY THE TIME
; MOVE CURSOR TO BOTTOM OF SCREEN
MOV
MOV
MOV
INT
DX,1700H
AH,2
BX,O
10H
;ROW=24 COL. =0
;FUNCTION=MOVE CURSOR
;INVOKE BIOS ROUTINE
; WRITE DATE TO DOS
MOV
MOV
MOV
ADD
CALL
CALL
MOV
ADD
CALL
CALL
CBW
MOV
ADD
MOV
INT
AL,MON_NO
DH,AL
SI,OFFSET DATE
SI,4
INP_BCD
CONVERT
DL,AL
SI,5
INP_BCD
CONVERT
CX,076CH
CX,AX
AH,02BH
21H
;MOVE IN MONTH NUMBER
;DH=MONTHS _ PARM FOR DOS ROUTINE
;MOVE IN STARTING ADDR. OF ARRAY 'DATE'
;MOVE TO DAYS INTO ARRAY 'DATE'
;INPUT DAYS OF MONTH
;CONVERT BCD TO BINARY
;DL=DAYS _ PARM. FOR DOS ROUTINE
; INPUT YEARS
;MAKE AL INTO 16 BITS
;MOVE IN 1900D
;CX=1900+ (YEARS)
;FUNCTION= SET DATE IN DOS
;INVOKE DOS ROUTINE
; WRITE TIME TO DOS
MOV
CALL
CALL
MOV
ADD
CALL
CALL
MOV
ADD
CALL
SI,OFFSET TIME
INP_BCD
CONVERT
CH,AL
SI,2
INP_BCD
CONVERT
CL,AL
SI,2
INP_BCD
;MOVE TO STARTING ADDR. OF ARRAY 'TIME'
; INPUT HOURS
;CH=HOURS _ PARM. FOR DOS
;INPUT MINUTES
;CL=MlNUTES _ PARM. FOR DOS
;INPUT SECONDS
Ell
3-79
~
v
v
z•
z
LISTING 2-RTCRD.ASM (Continued)
AND ADD
RET
CONVERT ENDP
-BL,OFH
AL,BL
I
=BINARY EQUIV. OF MOST SIG. BCD
;CLEAR OFF MOST SIGBCD DIGIT IN BL
;ADD BINARY EQUIV. OF BOTH BCD DIGITS
;-----------------------------------------------------------------------------------------;"SET_CURSOR', SUBROUTINE - SETS THE CURSOR AT DESIRED POSITION. THE
POSITION IS INDICATED BY DH, DL.
Le. DH=ROW DL=COLUMN
ENTRY: DX
;-----------------------------------------------------------------------------------------PUBLIC SET_CURSOR
SET_CURSOR PROC NEAR
AH,2
MOV
BH,O
MOV
- IN!
lOH'
RET
SET_CURSOR ENDP
;FUNCTION=MOVE CURSOR
;INVOKEBIOS ROUTINE'
;---------------------------------------------.-------------------------------------------"MOV_STR"
SUBROUTINE -
MOVES A STRING OF 3 CHARS. FROM THE 'MONTH'
ARRAY INTO THE 'DATE' ARRAY. THESE 3 CHARS.
REPRESENT A MONTH ego MAR = MARCH.
ENTRY:
DI=OFFSET OF DATE
SI=OFFSET OF MONTH
OUTPUT: DI,SI, BOTH INCREMETED BY 3
AX ALTERED
;-----------------------------------------------------------------------------------------PUBLIC MOV_STR
MOV_STR PROC NEAR
CX,3
MOV
AL, [SI]
LP1:
MOV
[D],AL
MOV
DI
INC
INC
SI
LPl
LOOP
RET
MOV_STR ENDP
;MOVE CHARS. OF 'MONTH' ARRAY INTO
'DATE' ARRAY
;----------------------------------------------------------------------------~-------------
"DISPLAY" SUBROUTINE - DISPLAYS EITHER DAY, DATE, OR TIME
ENTRY: BX=STARTING ADDR. OF 'TIME', 'DATE', OR 'TIME' ARRAY
OUTPUT: AX,BX,CX ALTERED
;-----------------------------------------------------------------------------------------PUBLIC DISPLAY
DISPLAY PROC NEAR
CX,12D
MOV
AL,[BX]
DISP1: MOV
CALL
DISPCHAR
BX
INC
DISPl
LOOP
CR_LF
CALL
RET
;LOAD CHAR. COUNTER
;LOAD IN CHARS.
;DISPLAY CHARS.
; AND
3-81
0l:Io
0l:Io
W
~
.
,------------------------------------------------------------------------------------
:::
LISTING 2-RTCRD.ASM (Continued)
~
DISPLAY ENDP
;-----------------------------------------------------------------------------------------;nDISPCHARn SUBROUTINE - INVOKES BIOS ROUTINE TO DISPLAY CHARACTER
ON SCREEN
ENTRY: NONE
OUTPUT: AX ALTERED
;------------------------------------------------------------------------------------------
PUBLIC DISPCHAR
DISPCHAR PROC NEAR
PUSH
BX
MOV
BX.O
MOV
AH.14
INT
10H
POP
BX
RET
DISPCHAR ENDP
;SAVE REG. BX
;FUNCl'ION=WRITE TO SCREEN
;INVOKE BIOS ROUTINE
;RESTORE REG. BX
;-----------------------------------------------------------------------------------------;nCF_LF" SUBROUTINE - PRODUCES A CARRIAGE RETURN AND LINE FEED ON THE
SCREEN.
ENTRY: NONE
OUTPUT: ALL REG. PRESERVED
;------------------------------------------------------------------------------------------
PUBLIC CR_LF
CR_LF PROC NEAR
PUSH
AX
MOV
AL.ODH
CALL
DISPCHAR
AL.OAH·
MOV
CALL
DISPCHAR
POP
AX
RET
CR_LF ENDP
;SAVE AX
;CARRIAGE RETURN
;LINE FEED
;RESTORE AX
;------------------------------------------------------------------------------------------
START ENDP
CODE ENDS
END
;END MAIN PROGRAM
START
3-82
~---------------------------------------------------------------.~
~i
Using External Oscillators
for the DP857x Real Time
Clocks with the Battery
Backed Mode Selected
National Semiconductor
Application Note 893
Milt Schwartz
This application note describes how external oscillators may
be used with the DP857x family of real time clocks, by using
the "test mode" to configure the DP857x in the battery
backed mode prior to starting the clock.
any oscillator signal. This action references the internal inverter to Vss. As a result, the inverter will pass the external
oscillator signal which is set to the battery voltage plus one
diode drop. Once the chip is operating in the battery backed
mode, clear the "test mode" register and leave the test
mode. The circuits of Figures 1 and 2 were used to check
out this solution. Both the LP2951 and LM611 are available
as mini-dip packages. The LP2951 is more expensive, but is
designed to do this type of application and is fully compensated for temperature and voltage changes. As shown, the
circuits provide for battery backed operation of the external
oscillator and DP857x. The disadvantage is extra current
drain from the battery. The advantage is that the user has
complete control over the oscillator design and can temperature compensate as well as tune the oscillator for maximum accuracy. The external oscillator was implemented using a 74HC04 (see Figures 3 and 4). The 74HC device was
chosen because it is specified to operate down to 2.0V. A
commercial oscillator could be used as long as it can operate at the Vss voltage chosen by the user. Figure 5 is a set
of curves of COUT versus CIN for a 32.768 kHz Pierce parallel resonant oscillator. These curves are helpful for choosing starting values for the oscillator to ensure reliable start
up and nominal operation.
THE PROBLEM
In the battery backed mode, the external oscillator peak-topeak voltage must not exceed the voltage at the Vss pin.
When the chip is first time powered up, it is in the single
supply mode. The single supply mode references the oscillator inverter to Vee. This means that in normal operation
the OSC in pin needs to swing positively to about 3.5V minimum. If an external oscillator is set to the Vss value, then its
high going signal may not be high enough to trip the internal
inverter. If the internal inverter doesn't pass the external
signal, you cannot program the chip into the battery backed
mode, because the internal OSC fail signal will always be
set (catch-22).
THE SOLUTION
General Description
Select the test mode and disable the oscillator fail circuitry
(refer to AN 589 in the Real Time Clock Handbook). Now,
the battery backed mode may be selected independent of
+5V
100 k
01
10,uA < I.
tl
< lmA
~...._ _ _ _~~_......~ To
ERROR
SENSE
Vee pin
of OP857x
LP2951
5V TAP
SO
GND
4
CMOS OSC
74HC04
..
O.I,uF
To OSC IN
32.768 kHz or
pin of OP857x
4.9152MHz
TL/F/llB46-1
FIGURE 1. Voltage Regulator as a Vcc Supply for an External Oscillator
3-83
r)
CD
CO
r--------------------------------------------------------------------------------------+5V
Z•
c(
~.....--1~....- - - -.....-
32.768 kHz or
4.9152 MHz
......~ To Vee pin
of DP857x
To OSC IN
pin of DP857x
TLlF/11846-2
FIGURE 2. LM611 as a Vee Supply for'an External Oscillator
10 MEG
DETAILED DESCRIPTION
To OSC IN
pin of DP8570/71
74HC04
Initialization procedure for first time power on:
1. Adjust output of voltage regulator to' be 0.2SV higher
than Vee. This will make sure that D2 is reversed biased
and the battery will not power the external oscillator
when Vee is powered. For this case D1 and D2 are the
same diodes (1 N914). An alternate method is to use a
Schottky diode for D1 and a 1N914 for D2. Then adjust
the output of the voltage regulator equal to the battery.
D3 is a Schottky diode (1 N6263) that ensures the high
level output of the oscillator is slightly lower than Vee.
200k
GN
22 pF'
l
TL/F/11846-4
2. Connect external oscillator to OSC IN pin, and leave
OSC OUT unconnected. ;
FIGURE 3. 32.768 kHz Oscillator using 'HC Inverter
3. Select the clock frequency by writing to bits D6,D7 of the
Real Time Mode Register (RTMR).
1 MEG
r----IW'Ir----. To OSC IN
pin of DP8570/71
74HC04
4. Write a "1" to D7 of the Periodic Flag Register (PFR).
This selects the test mode.
5. Write a "1" to D7 of the RAM/Test Mode Register locat-
lk
ed at address Ox1 F of page O. Other bits = O. The oscillator fail flag is now disabled.
-
4.9152 MHz
crystal
GN
36 PF'l
D
COUT
l
6. Write "0" to D6 and "1" to D7 of the PFR. This action
selects battery backed mode and test mode.
68 pF
7. Start the clock by writing "1" to D3 of the RTMR. To
check that the clock is actually running, read D3 of the
RTM R and test that it is a "1".
TL/F/11846-5
FIGURE 4. 4.9152 MHz Oscillator using 'HC Inverter
8. Clear the RAM/TEST Mode Register.
9. Write "0" to D7,D6 of the PFR. You have now left the
test mode and are in battery backed mode.
10. Read D3 of the RTMR and test for a "1". This is a
double check that the clock is running.
11. Continue yO!Jr regular initialization of the chip.
The above concept could be applied to any chip that uses
an oscillator and has separate VeelVee pins that require
mode selection for battery/single supply operation.
3-84
.
l>
32.768 kHz Oscillator Hints for a Pierce Parallel Resonant Circuit
The below curves are a plot of COUT versus CIN for constant Load Capacitance (Cu. The load capacitances selected show the
typical range specified by various manufacturers.
1
1
The expression for calculating CL is c = -c + - C
1
L
IN
OUT
Where COUT is usually greater than CIN
50
40
30
COUT
(pF)
20
10
I'
I
I
10
c;, = 15 pF
c;, =10 pF
Practical lower limit for <1N to guarantee reliable
start up. Contact crystal manufacturer for exact value
for the particular crystal chosen.
15
<1N (pF)
Refer to AN-588 for additional information.
FIGURE 5
3-85
20
25
30
TLIF/11846-3
Z
0)
co
w
~r-----------------------------------------------------------------~
.
en
co
Z
ct
DP8570A Experiments to
Test the Low Battery Bit or
Generate a Periodic
Interrupt
National Semiconductor
, Application Note 894
Milt Schwartz
SUMMARY
This application note describes two experiments. One experiment allows the user to check that the low battery bit is
working correctly. The other allows the user to generate a
10 ms periodic interrupt.
A program named RTC, written in MicrosoftTM Quick C version 1, is used for both experiments. The code works with
the circuit shown in Figure 3. This circuit is a general purpose interface for use with an IBM® PC-XT® or PC-AT® (or
equivalent). Keyboard entries may be either upper or lower
case, but the underscores must be included.
Type rtc to execute the program, then follow the instructions
on the monitor.
Monitor the waveform at the OSC OUT pin. Observing the
peak-to-peak voltage of this waveform is the only way to
know that the DP8570A is in the battery backed mode, unless the test mode is selected. The waveform is sinusoidal
in form and swings within 0.6V of Vss and ground. Refer to
Figures 1a, 1b, 1c.
, Vary the Vss voltage slowly as you approach 2.3V. If the
Vss voltage gets too low (less than 1.8V) the oscillator may
stop. During the low battery bit mode, if Vss is grounded or
a too low a voltage, you will not get any indication on
screen. If you hit the spacebar and re-enter the
LOW_BATT_BIT mode, Message 1 warning will appear
on the monitor.
LOW BATTERY BIT EXPERIMENT
Equipment: Variable lab supply or 20k pot, center tapped
to the Vss pin.
An oscilloscope with 10 Mn, 10 pF probe or
higher impedance.
The initial screen output is shown in Message 1. Before
selecting the LOW_BATT_BIT mode, set the voltage at
the Vss pin to about 2.5V. If Vss is GND or too Iowa voltage, a message should appear (see Message 2). Once the
LOW_BATT_BIT mode is running, you should see screen
output (see Message 3). The status of the low battery bit Is
displayed in the lower left of the monitor. A value of 0 indicates Vss is higher than the internal threshold detector. A
value of 40 indicates the low battery bit is set.
10 mS INTERRUPT EXPERIMENT
Equipment: An oscilloscope is needed to monitor the INTR
pin.
Before starting this section of the program, connect Vss to
ground. The INTFL-10 ms code configures the DP8570A in
the Single Supply mode. Message 4 is output to the monitor
indicating you are in the 10 ms Interrupt mode. Figure 2a
shows expected waveforms for a PC-XT (4.77 MHz); Figure
2b a 386/33 MHz AT.
Check that the Oscillator has started.
If you don't get osc running in 5 seconds, the program will abort
The Oscillator is running. The Clock is started.
You may choose the
'Low Battery Bit' Test
or
'the lOms Interrupt' Test or
'END to return to DOS'
Type in your choice in the following format, then hit ENTER:
Choices are:
LOW_BATT_BIT
or
INTR_lOms
or
END
to exit the Program
Enter your choice now:
Message 1: Initial Screen Display (Normal Operation)
3-86 '
.
l>
z
Watch out! VBB is at Ground or some illegal value
CC)
<0
~
VBB voltage should be between 2.2V and VCC - 0.4V
Message 2: Vaa Warning
Battery backed mode selected.
Check waveform at osc out to see if referenced
to the battery voltage
Peak value should be less than the battery voltage
Adjust voltage on VBB pin while monitoring screen.
The bottom left side of the screen will display zero
if VBB > threshold (about 2.1 volts),
or 40 if VBB < threshold.
This test may be ended by hitting the space bar.
Message 3: Normal Message after Selecting LOW_BATT_BIT
II
3-87
.
~
orr
0)
co
AI
z
1.16V
Z
The
Now
Use
Hit
Oscillator is running. The Clock is started.
you are in the lOms_Interrupt mode
an oscilloscope to view the waveform at the INTR pin
spacebar to return to 'Selection Menu'
Message 4: Normal Message after Selecting INTR-10ms
A1
O.20V
Conditions:
Vee = 5V
vaa = GND
INTR pin out running
on a PC/XT (4.77 MHz)
•
I
-
GND
2 ms
1V
Tl/F/11B47-5
.FIGURE 2a: Expected Waveforms at INTR Pin
A1
-O.15V
I
l
Conditions:
Vee = 5V
Vaa = GND
INTR pin out running
on a 366133 MHz AT
~---r----~---+----~---+----+----+----+---~I~---iGND
1V
2 ms
Tl/F/llB47-6
FIGURE 2b: Expected Waveforms at INTR Pin
3-89
CO
CD
~
AN·894
:
j
1
"
in
ii:
A9
AS
A7
A22
A23
A24
A25
A26
All
AS
A5
AtM
r=l
20
GND
=====t
Vee
A7
AS
87
86
~~
:~
r"
~~~:~
I
1.. ...
"fiI'
80
74ALS522
~
A=r'
u
81'
lOW
813
AO
AI
A2
A31
A30
A29
A28
A27
A9
A3
A4
00
01
02
03
04
c.l
cD
0
06
D5
07
~ Vee
IRQ7
IRQ6
IRQ5
IRQ4
IRQ3
82
822
823
824
825
~
83
GND
81
83
I
Cs
PFAIL
Ro"
WR
INTR
-
0
M.{1
15
5
6
~
1
12
II
~.jiy*
17
18
TCK
GO
Gl
AO
AI
A2
A3
IV"'~
r-" "
R3,R4
DP8570
DO
Dl
D2
D3
D4
D5
D6
D7
R2
27
A4
.:...
.
Vee
OSC
IN
0
0
0
0
0
112
11
-.!:-VS8
Battery
or lab
Supply
GND
II
Cl
~~C2
~t-
C3
Ht-~4
L;I--
C5
OSC
OUT
1 13
r]126
~ Ro"WR
Cs
~
P
8
+5V
o
o
o
o
o
1
Sttportfor
R6 comparator to
10k Irlp 01 4.SV
1o lurn
port
1TO
4.77 101Hz
83
82
Vee
2
GND
82
+5V
Vee
--""
't. ~
':!
.../T
.:
28
GND
G
CSC
+5V
.-:l
74LS245
CLK
GND
J"
.~ R9
11
DIR
T
~
~
4
9
comparal:
10
3
I §
AS
A7
AS
A5
A4
A3
A2
T
op amp.
L..,;""..;;..
3
2
9
.A
~
7
~
19 Hex 300 10 31F
lOR
LM613
1
I: : ..
J3 :
....
r:: "
j
t
'SWi""
_....
~R5
4
R7
•
~
~
f-
Vee
PFAil f- 23
AO
AI
INTR
~
MFO
.!l..-
A2
-
A3
A4
DP8571/72/73
DO
Dl
D2
03
04
05
Vss = 3.0V to 3.4V Uthium battery (coin cell)
CRI
os
07 ose
IN
10
Component and Placement Ust
pot 1 = 10kfi
CRl = see Table I
C,N = see Table I
GoUT = see Table I
Cl = 0.047 JLF ceramic placed at Ul
C2 = 0.047 JLF ceramic placed at U2
C3 = 0.047 JLF ceramic placed at U3
C4 = 0.047 JLF ceramic placed at U4
C5 = 5.6JLF solid tantalum placed at card edge
01,02,03 = lN914 or lN4001 or lN4933
Rl = 2.7kfi
R2 = 3.9kfi
R3 = 10kfi
R4 = 10kfi
R5 = 3.3kfi
R6 = 10tum 10kfi
R7 = 20kfi
R8 = 39kfi
R9 = 5kfi
I
',,'
ose
OUT
-~-~
o
f" o-ft-o f---c
0
0
"1
0
o-ft-o
o 0
o
Nate: Thl. sock.t to be uMd with
a hn.d.r f«component
0
0
"7
p
Table I
n
ou
C,N
CR1
(crystal)
CIN
(pF)
COUT
(pF)
32.768/32.0 kHz
4.194304 MHz
4.9152 MHz
15
36
36
47
68
68
TL/F/11847-7
FIGURE 3. General Purpose Interface to IBM PC-XT or PC-AT for Experiments
~
/*************************************************************************
* This program RTC.C is designed to work with the DPS57x family of
*
* Real Time Clocks. It works with a demoboard interfaced to a PC/XT
*
* or PC/AT. This 'c' program is written in Microsoft C (version 6.0).
*
* This program has two parts:
*
* Part 1 allows testing the Low Battery Bit, in the Batt Back Mode.
*
* Part 2 initializes the 10 millisecond periodic interrupt.
*
*
* Also, it delays clearing the INT, after polling the int flag in
* the 'MSR' for the purpose of observing the output on an Oscilloscope. *
* ***********************************************************************/
#include
#include
#include
#include
#define
#define
#define
#define
#define
#define
#define
#define
#define
#define
MSR
PFR
RTMR
IRR
OMR
ICRO
ICRl
TCRO
TCRl
TESTR
Ox300
Ox303
Ox30l
Ox304
Ox302
Ox303
Ox304
Ox30l
Ox302
Ox31F
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
main status register
periodic flag register
real time mode register
interrupt routing register
output mode register S
interrupt control register 0
interrupt control register 1
timing control register 0
timing control register 1
Test Mode register
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
enum { LOW BATT BIT, INTR_10ms, END} mode;
char buf[SO]; char *mode_str[] .. { "LOW_BATT_BIT", "INTR_10ms", "END" };
maine)
{
.
char *input;
int i;
/* Initialize the RTC, select 32.76SKHz.
*/
/*
/*
/*
/*
*/
*/
*/
*/
The following while loop tries to start the clock
and tests the osc fail bit to see that the oscillato
is running. The oscillator must be running in order
to configure the DPS57X for battery back mode
clearscreen( GCLEARSCREEN);
printf("\n\t Check that the Oscillator has started.");
printf("\nIf you don't get osc running in 5 seconds, the program will abort\n")
init();
'Low Battry Bit' Test\tor");
printf("\n\nYou may choose the
'the 10ms Interrupt' Test\tor");
printf("\n
'END to return to DOS'
." ) ;
printf("\n
outp(MSR,O);
mode
1;
do {
while (mode 1- LOW_BATT_BIT && mode 1= INTR_10ms && mode 1= END)
{
printf("\n\nType in your choice in the following format,then hit ENTER:");
TL/F/11847-8
3·91
printf("\n\nChoices are:\tLOW BATT BIT
or\n\t\tINTR 10ms
printf("\t\tEND
tb exit the Program\n");
printf("\nEnter your choice now: \n\n");
or\n");
input - gets(buf);
for (i-O; i<-3; i++)
if (lstrcmpi(input, mode str[i]»
mode - i;
}
switch(mode)
{
case LOW_BATT_BIT:
init();
batbak( );
mode = -I;
break;
1* Call 'init' function *1
1* Call 'batbak' function *1
case INTR_10ms:
init( );
intr( );
mode - -1;
break;
1* Call init routine *1
1* Call intr Routine *1
case END:
. printf("\n This is the END of the Program");
break;
}
} while (mode 1- END):
}
batbak()
1* This program configures the DPB57X 32.76BKHz oscillator
Conditions: Vcc - 5V, VBB .. 3.0V (adjustable),
T - ambient temperature
outp(MSR,Ox40);
outp(ICR1,OxBO);
outp(MSR,O);
outp(PFR,O);
.
*/
1* select bank 1
1* set PFAIL enable in ICR1
*1
*1
1* select battery backed mode
*1
if(inp(IRR) & Ox40)
{
clearscreen( GCLEARSCREEN);
-settextpositIon(11,15);
printf("Watch outl VBB is at Ground or some illegal value");
settextposition(13,15);
printf("VBB voltage should be between 2.2V and VCC - O.4V");
settextposition(24,O);
mode .. -1;
exit();
}
clearscreen( GCLEARSCREEN);
printf("\n\t Battery backed mode selected.");
printf("\n\t Check waveform at osc out to see if referenced");.
printf("\n\t to the battery voltage.\n\t Peak value should be less");
printf(" than the battery voltage\n");
TL/F/11847-9
3-92
printf("\n\n");
printf("\n\t Adjust voltage on VBB pin while monitoring screen.");
printf("\n\t The bottom left side of the screen will display zero");
printf("\n\t if VBB > threshold (about 2.1volts),");
printf("\n\t or 40 if VBB < threshold.");
printf("\n\t This test may be ended by hitting the space bar.");
printf("\n\n\n");
outp(MSR,O);
1* select bank 0
*1
while( I kbhi t( ) )
(
settextposition(24,0);
-printf("%x",inp(IRR) & Ox40);
/* display low batt bit
*1
}
getch( );
intr()
(
int i;
- 0;
i
outp(MSR,Ox3E);
outp(PFR,Ox40);
outp(TCRO,O);
outp(TCR1,0);
outp(IRR,Ox1D);
outp(MSR, Ox40);
outp(OMR,OxB);
outp(ICRO,Ox10);
outp(ICR1,OxBO);
1* clear all pending interrupts
1* select per. intr to intr pin
1* select register bank 1
1* intr - push pull active 10
/* select 10ms periodic intr
*1
*1
*1
*1
*/
printf("\n\Now you are in the 10ms Interrupt mode");
printf("\nYou can use Oscilloscope-to view the waveform");
printf("\nHit spacebar to return to 'Selection Menu'");
do {
for (i-O; (i < 1300) && «inp(MSR) & Ox05) !- 5); i++)
if (i ... 1300)
(
printf("\nThere is something WRONG !!");
printf("\n Please check the Voltage at the VBB pin");
exit();
}
else
for(i-O; i < 300; i++)
/* this loop is for
/* viewing the waveform
1* The value in the, 'FOR' loop is dependent on the speed of
1* the Processor. The value '200' in this example is for
1* the PC/XT running at 4.7 MHz.
1* clear per intr
outp(MSR,Ox3E);
*1
*1
*1
*1
*1
*1
} while (!kbhit(»;
getch( );
}
TLlF/11847-10
•
3-93
~
Q)
co
z•
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