1993_Ricoh_General Purpose_IC_Data_Book 1993 Ricoh General Purpose IC Data Book

User Manual: 1993_Ricoh_General-Purpose_IC_Data_Book

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ICD©®DO

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ELECTRONIC DEVICES
GENERAL-PURPOSE IC
DATA BOOK

..

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ELECTRONIC DEVICES
GENERAL-PURPOSEIC
DATA BOOK
1.GENERAL INFORMATION
2. QUALITY ASSURANCE SYSTEM
3. ASSP
4. MPU
5.DSP
6. MEMORY
7. LINEAR IC
8. APPLICATION MANUAL

ICD©®OO
RICOH COMPANY, LTD.
ELECTRONIC DEVICES DIVISION

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I

NOTICE

* Specifications described herein are subject to change without notice.
* The application circuit diagrams and circuit constants herein are included as an example and
provide no guarantee for designing equipment to be mass-produced.

* RICOH COMPANY, LTD. does not assume any liability arising out ofthe application or use
of any product or circuits described herein, neither does it convey any license under its
patent rights nor the patent rights of others.

copy right © 1993

RICOH COMPANY, LTD. Electronic Devices Division

Printed in Japan

Table of Contents
Page
1. GENERAL INFORMATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

1· 1

2. QUALITY ASSURANCE SYSTEM. . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

2· 1

3. ASSP
3.1

REAL TIME CLOCK RP5COl . . . . . . . . . . . . . . . . . . . . . . . . . . ..

3· 1

3.2

REAL TIME CLOCK RP/RF/RJ5C15 . . . . . . . . . . . . . . . . . . . . . .

3·15

3.3

REAL TIME CLOCK RP/RF5C62 . . . . . . . . . . . . . . . . . . . . . . . ..

3·23

3.4

CRT CONTROLLER RF5C16A/RP5C16.... . . . . . . . . . . . . . . . ..

3·29

3.5

QUAD. UART RF5C59 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3 - 41

3.6

PIO RF5C60 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-49

3.7

PCM SOUND GENERATOR RF5C68A . . . . . . . . . . . . . . . . . . . . .

3-53

3.8

PWM GENERATOR RF5C86 . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3 - 71

3.9

2-dimension Filter RF5C67 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

3 - 87

3.10 Transversal Filter5C136 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-113

4. MPU
4.1

CMOS 8bit MPU RP65C02G/G-06. . . . . . . . . . . . . . . . . . . . . . . . ..

4-1

Digital Signal Processor RP5C72

...........................

5-1

6.1

CMOS 256Kbit MASK ROM RP/RS53256E . . . . . . . . . . . . . . . . . ..

6-1

6.2

CMOS 1Mbit MASK ROM RP/RS531010E. . . . . . . . . . . . . . . . . . ..

6-5

6.3

CMOS 2Mbit MASK ROM RP/RS532010E. . . . . . . . . . . . . . . . . . ..

6-9

6.4

CMOS 4Mbit MASK ROM RP/RS534040E. . . . . . . . . . . . . . . . . . ..

6 - 13

6.5

NMOS 64Kbit MASK ROM RP2364E . . . . . . . . . . . . . . . . . . . . . ..

6 - 19

6.6

NMOS 128Kbit MASK ROM RP23128E . . . . . . . . . . . . . . . . . . . . .

6 - 23

5. DSP
5.1

6. MEMORY

6.7

NMOS 256Kbit MASK ROM RP23256D/E, RP23257D/E . . . . . . . . ..

6 - 27

6.8

NMOS 1Mbit MASK ROM RP231027D/E . . . . . . . . . . . . . . . . . . . .

6 - 31

6.9

NMOS 4Mbit MASK ROM RP234096 . . . . . . . . . . . . . . . . . . . .. ..

6 - 35

6.10 CMOS 64bit PROM R F/RP5HOl . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 41

7. LINEAR IC
7.1

VOLTAGE DETECTOR RX5VA Series

7.2

VOLTAGE DETECTOR RN5VL Series ............... - . - . ..

7-1
7-7

7.3

VOLTAGE DETECTOR RN5VT Series . . . . . . . . . . . . . . . . . . . . .

7 - 13

7.4

VOLTAGE REGURATOR RX5RA Series. . . . . . . . . . . . . . . . . . ..

7 - 19

7.5

VOLTAGE REGURATOR RN5RL Series. . . . . . . . . . . . . . . . . . ..

7 - 25

7.6

VOLTAGE REGURATOR RX5RE Series. . . . . . . . . . . . . . . . . . ..

7 - 29

7.7

STEP-UP DC/DC CONVERTER RH5RC301/302/501/502. . . . . . . ..

7 - 33

7.8

STEP-UP/DOWN DC/DC CONVERTER RF5RD301/501 . . . . . . . . ..

7 - 41

7.9

STEP-UP/STEP-DOWN PWM DC/DC CONVERTER with
VOLTAGE DETECTOR RS5RM

Seri~

.....................

7-47

7.10 STEP-UP/STEP-DOWN VFM DC/DC CONVERTER with
VOLTAGE DETECTOR RS5RJ

Seri~

......................

7-53

7.11 PWM STEP-UP SWITCHING REGULATOR RH5RH Series .......

7-59

7.12 VFM STEP-UP SWITCHING REGULATOR RH5RI Series. . . . . . ..

7 - 69

7.13 DC/DC MULTI POWER SUPPLY RF5C133 . . . . . . . . . . . . . . . . ..

7 - 79

7.14 MULTI POWER SUPPLY RS5VE . . . . . . . . . . . . . . . . . . . . . . . . .

7 - 95

8. APPLICATION MANUAL
8.1

REAL TIME CLOCK RP5C01/RP5C15 APPLICATION MANUAL ..

8-1

8.2

REAL TIME CLOCK RP/RF5C62 APPLICATION MANUAL. . . . ..

8 - 75

8.3

2-dimension Filter 5C67 APPLICATION MANUAL ..............

8 - 117

8.4

VOLTAGE DETECTOR RX5VA Series APPLICATION MANUAL ..

8 - 135

8.5

VOLTAGE REGURATOR RX5RA Series APPLICATION MANUAL.

8 - 157

8.6

VOLTAGE REGURATOR RX5RE Series APPLICATION MANUAL.

8 - 181

8.7

STEP-UP DC/DC CONVERTER RH5RC Series APPLICATION
MANUAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.8

8 - 203

STEP-UP/DOWN DC/DC CONVERTER RF5RD Series
APPLICATION MANUAL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

8 - 227

1.GENERAL INFORMATION

I

RICOH ASIC
EPL
Features
This is the ASIC which allows the user to
program optional logic circuits with
many standard PAL programmers. This is
optimum replacement for small·scale
logic and CPU peripheral devices. EPL's
provide a quick evaluation and correction
of logic circuits.

Lineup
Configuration

Model name

-Upward compatible to AMD PAL.
-CMOS EPROM process
• Low current consumption and
high programmability.
• Erasable by ultraviolet light
(ceramic window package).
-Maximum access time 25/35ns
-20pin, 24pin types
- Up to 900 gate equivalents
-Security fuse
-Output polarities are program·
mabie.
Power

supply

I
\'

Electrical characteristics

Max. Icc
Operation Standby

Max. operaMax.
access time ting freq.

Package

G EPLlOP8
I
EPLl2P6

B 10 input 8 output
AND·OR/XOR Array
B 12 input 6 output
AND·OR/XOR Array
EPLl4P4 B 14 input 4 output
AND·OR/XOR Array
EPLl6P2 B 16 input 2 output
AND·OR/XOR Array
G EPL16P8 B 10 input 6 input/output
IT
AND·OR/XOR Array
EPL16RP8 B 8 input 8 feedback 8 output
SV±S%
8 register AND·OR/XOR Array
EPL16RP6 B B input 6 feedback 2 input/

Compatible
products

PALlOL8. 10H8
PAL12L6,12H6
SOmA*

40mA*

PALl4L4. 14H4
PAL 16L2. 16H2
20DIP
3Sns

20MHz

(plastic, ceramic

PAL 16L8

with window)

PALl6R8
70mA

60mA

PAL16R6

output 6 output 6 register

AND·OR/XOR Array
EPL16RP4 B B input 4 feedback 4 input/

PAL16R4

output 4 output 4 register

EPL241 ED/
EP/EJ

AND·OR/XOR Array
6 input 16 input/output
16 feedback 16 macrocell
clock select

140mA**

120mA**

2Sns

70mA

SOmA

2Sns

80m A

70mA

70mA

60mA

24DIP
28PLCC

22Vl0 & others

30MHz

20DIP

16V8,18PB
and other
20pin PAL

2Sns

30MHz

24DIP (Plastic)
24CERDIP
28PLCC

20V8

ISns

40MHz

20DIP
20CERDIP
20PLCC

Same as GIT

30MHz

asychronous reset with
16 register
EPL204ED/
EP

10 input 8 input/butput
8 feedback 8 macrocell
clock select
asynchronous reset with

8 register
EPL242***

16 input 8 input/output
8 macracell

asynchronous reset with
8 register
EPL20F***

Same as GIT type
(except for XOR)

GI: Group I
GIT: Group IT
...
. .
* Since Group I has twice as many product terms as PAL products, typical currents will be reduced to a half of the above specification values by
power-down circuits in R ICOH's EPL.
** It will proportional to the product term usage. (40 mA at 35% utilization)
***Under development

Interface

Support Tool
Software

Hardware

@EPLASM (RICOH)
@ABEL (Data 1/0)
Hardware
@Universal Programmer

UNISITE40, 29B (Data I/O)
@Model 60A (Data I/O)
@Model PW9B·20 (RICOH)
@EPROGRAMER241 (RICOH)
• Pecker 30 (AVAL)

Customer

RtCQH or Distributors

• SW16 (Ricoh)
(RICOH)
• IBM·PC AT (IBM)
• PC9801 (NEG)

•

• PROMAC Model 11 (Japan Macnics)

If the customer has the programer, it can be
programed by the customer .

@mark: Products handled by RICOH'ssales

1-1

RICOH ASIC
GATE ARRAY
Features
eA variety of line-up
High speed (O.38ns) High density (200k Gate), Low power operation (3V), Small gates
wim a number of I/0s.
e Design support system is available for a Work Station (SPARe).

Memory Build-in type

5GU Series (CMOS Gate Array, D.SIl Design rule)
5GU
Series

Gate Delay
Time

Gates

No. 01
1/0'

5GU020

2t.976

136

5GU030

33.000

164

0.38nstgate

5GU040

43.092

188

(3V operation)

5GU050

54 ..016

208

O.63nstgate

5GU075

82.056

256

Load

5GU100

109.080

292

FAN OUT=2

5GU200

194.400

384

wire length=2mm

Output Drive

Supply Voltage

flO Level

5V±100/0

CMOSITTL

Type

Current

(5V operation)
(5Voperation)
4/8/12mA

Sea

(3Voperation)

Gate

of

Compatible
3V±100/0

21416 mA

5GL Series (CMOS Gate Array, 1.21l Design rule, Small gates with a number of 1/05)
5GL
Series

5GL005

Gates

No. 01
1/0'

Gate Delay
Time

64

(5V operation)

500

Supply Voltage

Package (Number of Pins)

flO level

5GL009

900

84

0.8nstgate

5(3L015

1500

104

(3V operation)

5GL026

2600

132

1.6nstgate

5GL035

3500

148

Load

5GL045

'4500

164

FAN OUT=2

5Gl100

10000

236

wire length=2mm

5V±100/0

64

64

64,80

64.80

CMOSITTL

64.80.100

64,80,100

Compatible

64,80,100

64,80,100.128

3V±100/0

• 8 pins in flO pads are dedicated to Vee and GND.

SOFP

OFP

80,100,128,144

80.

100,128.144

loa. 128
100

128,144,160

208

64, 80 and t 28 pin type of SOFP are under development.

5GV Series (CMOS Gate Array, 1.21l Design rule)
5GV
Series

Gates

No. 01
1/0'

Gate Delay
Time
(5Voperation)
0.8nstgate

5GV041

4100

1.06

5GV053

53.00

118

5GV073

73.0.0

136

5GV094

9400

5GV124
5GV161
* 8

Supply
Voltage

Package (Number 01 pins)

flO level
DIP
24,28,40

SDIP
42,64

60. 64, 80, 100

FLAT

SOFP
64,80,100

PLCC
44.68,84

24,28,40

42,64

60, 64, 80, 100, 128

64,80,100.128 44,68.64

(3V operation)
1,6nstgate

CMOSITTL

24,28,40

42.64

60,64,80,100,128,144

64,80,1.0.0

154

Load

Compatible

24.28.40

42.64

64,8.0,100,128,144

64.80.100,128 44,68,84

12400

178

FAN OUT=2

-

42,64

64,80.

16100

2.04

wire'length=2mm

-

42.64

80,

5V±100/0

3V±100/0

pins in 110 pads are dedicated to Vee and GND.

lao. 128, 144. 160
loa, 128. 144, 160

64, 80 and 128 pin type of SQFP are under development.

1-2

44,68,64

64, 80, 100, 128 44.68,84
80,10.0.128 44,68,84

RICOH ASIC
lIIIl ~~eo;;°ry

Features of 5GF Series
5GF Series Gate Arrays allow memory (ROM, RAM) in
conjunction with Logic requirements.
RICOH's unique system of constituting the memory using
wired area, as shown on the right diagram. Since it does not
require the master for memory, the cost for development can
be kept down in case of memory integrated.

D

Logic Ar.0r-r---:-=-::-:-,.-,....,

1/0 Cell

,...........c=:J
1!I!IiIlIlllIIILC::=:J

'-:c=:J
_:c::=:J

1/0
1/0
C.II
C.II,._ ....... :~

a-:-'

I

1/0 Cell

1/0 Cell
5GF Series

EXAmDle of other systems

5GF Series (CMOS Gate Array, 1.511 Desigrlrule)
5GF

Max. loading

~~\::(~J~(g:W
(~~)
(~~)

No. of

Series

Gates

5GF21

2100

SGF26

2600

SGF32

3200

5GF45

4500

SGFS8

5800

8K
(16K)

138

SGF82

8200

(1~~)

168

(~ ~)
(~ ~)

1/0

Package (Number of pins)

Supply

Gate Delay
Time

1/0 level

Voltage

DIP

Shrink DIP

84

40

84

44,60,84,80,100

FLAT

PLCC
68

94

40

64

44, 60, 84, 80, 100

68

CMOS/TTL

40

84

44,60,84,80,100

68

Compatible

40

64

60, 64, 80, 100

68

40

64

84,80,100

68

40

84

80,100

68

1.0ns/gale
102

120

SV±10%
Load
2 inpul NAND
FAN OUT = 3
3mm

Note: Available number of gates for logic are reduced due to memory capacity.

5GH Series (CMOS Gate Array, 2,011 Design rule)
.5GH

No, of

Series

Dates

SGHOS

560

40

SGH10

1000

60

110

Gate De!ay
Time

SGH16

1600

72

2300

88

Load
2 inpul NAND

2900

98

5GH38

3800

108

Package (Number 01 pins)

110 level

FAN OUT

5V±10%

=3

DIP

Shrink DIP

FLAT

14,16,18,20,22,24,28,40

-

-

24,28,40,48

1.Sns/gate

5GH23
5GH29

Supply
Voltage

28

60,44

PLCC

44',52,68

CMOSITTL

24, 28, 40, 48'

28,42,64

60,80,44

44',68

Compalible

28,40,48'

64

60,80,100

68,84'

28,40,48'

64

60,100

68',84'

40,48'

64

60,80,100

68',84'

(*): Under Development

1-3

RICOH ASIC
STANDARD CELL
Features
• Abundant Cell Library
(CPU: 8/16 bit, CPU peripheral Cell, Compiled Cell, Analog Cell (AID, D/A)).
• High-Speed (O.26ns).
• Low voltage operation (5V/3V).
• Design support system is available for a Workstation (SPAPC).

Development Example

I ASIC

Micro Computor

I

RICOH prepairs 3 CPUs; & Ru 8 (8bit). 65C02 (8bit) and 65C816 (16bit). These CPUs are
High-speed (pipe-line archtecture, powerful addressing mode) and small size.

Example (Using 65C02)

I Compiled

Cell

I

RICOH prepairs large scale cells. (Compiled cell).

IDigital/Analog

Example
(Image Processing IC)

Celli

Digital circuit and Analog Circuit can be integrated on a chip.

Example (Controller IC)

1-4

RICOH ASIC

Cell Name

Basic Cell

CPU Cell

CPU
Perlpheral Cell

Cells

Macro Cell

8bit:

Ru8, R65C02

16bit:

R65C816

ACi

(Asynchronous communication interface)

INTC

(Interrupt controller)

TCC

(Timer/Counter)

Cell

Analog

Cell

(3eells)

PIO&HS (Parallel input/output)
RTC8

Compiled

(411 Cells)

Macrofunction Cell

(Real Time Clock)

MUL

(Multiplier)

ALU

(Arithmetic Logic Unit)

ADS

(Adder/Subtructor)

BRS

(Barrel Shifter)

RGF

(Register file)

DMX

(Multiplexer)

SEQ

(Microprogram sequencer)

PIP

(Pipeline register)

MRO

(Mask ROM Asynchronous)

SRA

(SRAM Asynchronous)

HSR

(SRAM Synchronous)

AD8SRA

(8 bit Successive Approximation AID Convertor)

AD8TRW/AD8TRWL

(8 bit Series - Parallel AID Convertor)

DA8RRVIDASRRI

(8 bit R-2R D/A Convertor)

DA8VA

(8 bit Current Adder D/A Convertor)

(5 Cells)

(11 Cell~)

(4 Cells)

I

RICOH ASIC
Interface
Type

Customer

RICOH

I. Schematic
interface

Software development

• R leOH cell library

Hardware
development

• Simulation data
• Software for
development

H. CAD
interface

• Schematic data
• Test pattern data

Timing
simulation
I---ct:onfirmatioill>_------:--------IL--_
_
_ _- '

L.-"-.ct:onfirmstio1t>_-----.>--------I

Mas'k creation .....
sample preparation

Mass production

Notel The CAD interface system provides software development for any practical circuit.

1-6

RICOH STANDARD
MASK ROM
lineup
Max. power consumption
Memory
Access
configuration time (osec)

Memory
capacity

Process

Model name

ImW)

Power supply

voltage

No. of pins

Pin
compatibility

Standby

Operation

PR2D32/33

32K

4096x8

250

440

-

24

TI/INTEL

RP2364E

64K

8192x8

200

550

110

28

INTEL

RP23128E
NMOS

RP23256D/E
RP231027D/E
RP231028E
RP234096

.
.

128K

16384x8

200

256K

32768x8

250/200

1M

131072x8

250/200

5V±10%

550

110

28

INTEL

550

110

28

INTEL

550

165

28

1M

131072x8

200

275

110

28

4M

524288x8

200

440

-

32
* Under development

Interface
Customer

RICOH

• EPROM for code check 2 pes.

1stcheck

CD

)

®

Ordering ~ Function
format
terminal

f----'-N:.:;O-----------t----------'
3rd check

YES

(

2nd CheCk)

)

YESL--~========~---t_----L~~~~~

I

~- - - - - - - - - - - - - - - - - - - - - - : - - - - - - ___ ..J '--l~===-------~
The above processes are omitted
I
by R leOH to deliver mass
l
production to the customers at

r

the ear.liest possible opportunity.

I
I

(

I

r------------c---...,

1-7

Final test, quality

guarantee test, etc.

4th cheek)

I

RICOH STANDARD
EPROM
Max. power consumption

Model name

RP/RF5HOI

Type

CMOS

Memory

Configu-

capacity

ration

64 bits

64xl

Access
time (I's)

1

(mW)

Power supply
voltage

No. of pin

Pin

compatible

Operation

I

Standby

55

r

0.55

8

-

Operation

Cycle time

Package

5V±5%

MPU
Power consumption

RP65C02G/G-06

(MAX.)

Circuit function

Model J;1ame

frequency
Operation

Standby

5mA/MHz

281'A

4/6MHz
(MAX,)

Circuit function

Power supply
voltage

Supply
current
(TYP.)

Execution
speed

Clock
(MAX.)

Package

Digital Signal Processor (fixed point operation)

5V ± 5%

60mA

lOOns/
Instruction

40MHz

28pin DIP

8bit CMOS MPU

250/166ns
(MIN_)

40pin DIP

DSP
Model name

RP5C72

REAL-TIME CLOCK
Max. current consumption
Model name

Power supply
voltage

Circuit function

RP/RF/RJ5CI5

REAL TIME CLOCK

RP5COI

REAL TIME CLOCK with RAM

RP/RF5C62

REAL TIME CLOCK

Operation

During

Backup
Package

power

backup

voltage

250I'A

151'A

2.0V

250l'A

151'A

2_2V

18-DIP

5OI'A

31'A

2.0V

18DIP/18S0P

18DIP/18S0P/28PLCC

5V±10%
5V±10%

CRT CONTROLLER
Model name

Circuit function

Power
supply

Power
supply
voltage

current

Package

RF5CI6A/RP5CI6

CRT DISPLAY CONTROLLER (All in One Type)
640x200 or 80x25 (character x line)

5V±10%

50mA

64-FLAT
64-DIP

RF5C56

CRT DISPLAY CONTROLLER (All in One Type with Look up Table and
analog RGB)
512x192 dots or 32x24 characters display

5V±10%

SOmA

64-DIP

Notel EPL is a registered trademark of RICOH. LOGICIAN is a registered tradamark of Daisy Systems Co. IDEA1000 is a registered trademark
of Mentor Graphics Co. IBM-PC is a registered trademark of IBM Co. DASH is a registered trademark of FutureNet Co. CADAT is a registered trademark of HHB Systems Co_ PAL is a registered trademark of Advanced Micro Devices. INC.

1-8

RICOH STANDARD
QUAD. UART
Model name

RF5C59

Power supply Max. power
voltage
current

Circuit function
Asynchronous receiver transmitter with 4 channel ports.

5V

20mA

Package

60·FLAT

PARALLEL I/O
Model name

RF5C60

Circuit function

6 I/O Port (8 bit I/O x 5. 5 bit I/O x I)

Supply

Power supply
voltage

(MAX.)

5V ± 10%

30mA

SOpin FLAT

current

Package

PCM SOUND GENERATOR
Model name

RF5C68A

Circuit function

8 ch. stereo output

Supply

Power supply
voltage

current

Clock
(MAX.)

Package

(MAX.)

5V ± 10%

30mA

10MHz

80pin FLAT

PWM

PWM GENERATOR
Model name

RF5C86

Circuit function

8 ch. PWM output

Supply

Power supply
voltage

current

resolution

Clock
(MAX.)

Package

(MAX.)

5V ± 10%

30mA

16 bit

16MHz

28pin SOP

Power supply

voltage

Clock
(MAX.)

Processing
speed
(MAX.)

Package

5V ± 10%

20MHz

25ns/element

l00pin FLAT

2 DIMENSION FILTER
Model name

RF5C67

Circuit function

5 x 5 image element filtering process

VOLTAGE DETECTOR
Voltage
Model Name

Function

Detect

Accuracy

*

Operation
Voltage

Current
Consumption

Package

RXSVL

Voltage Deleclion.
Possible to set delecl voltage al O.IV step.

±2.S%

1.5 - IOV

I~A

(SOT·S9)
TO·92, SOT·23·S

RNSVr

Voltage Detection.
Low voltage operation.

±2.S%

O.7-IOV

I~A

Mini mold 5 pin
(SOT·23·5)

Output
Voltage
Accuracy

Operation
Voltage

Current
Consumption

Package

Under Development

VOLTAGE REGULATOR
Model Name

Function

RX5RL

Power Supply.
Possible 10 sel oulpul voltage al 0.1 V slep.

±2.5%

I.S - IOV

I~A

(SOT·S9)
TO·92, SOT·23·5

RXSRE

Power Supply.
Large currenl oulput

±2.5%

1.5 - lOV

I~A

Mini Power mold
TO·92

1-9

I

RICOH STANDARD
DC/DC CONVERTOR
Function

Model Name

Starting

Output

Current

Voltage

Voltage

Consumption

Package

RHSRC

Step-up voltage switching regulator, low voltage operation

0.9 -I.OV

3V, 3.SV, SV

3.5~

Mini power mold

RF5RD

Step-up/down voltage series regulator.

1.2V

3V. SV

6uA

8-S0P

RSSRM'

Series Regulator, Voltage Detect, Enable,
PWM type Step-up/down.

1.2V

-

10uA

8-S0P

RSSRJ'

Series Regulator, Voltage Detect, Enable,
VFM type. Step-up/down.

1.2V

-

10uA

8-S0P

Starting
Voltage

Output
Voltage

Consumption

, Under Development

SWITCHING REGULATOR
Model Name

FUnction

Current

Package

RH5RH

PWM type Step-up Voltage Switching Regulator

0.9

-

SuA

Mini power mold
(SOT-89)

RHSRI'

VFM type Step-up Voitage Switching Regulator

-

-

-

-

"' Under Development

MULTI POWER SUPPLY
Function

Model Name

*

Voltage

Operation

Accuracy

Voltage

Package

RFSCI33

Multi Power Supply for Audio (DC/DC + Power Supply)

±2.5%

SV(TYP.)

SSOP24

RSSVE'

Multi Power Supply for Communication (Regulation + Detector)

±2.S%

I.S -IOV

SSOPI6

Under Development

1-10

2. QUALITY ASSURANCE SYSTEM

I

THE POLICY OF QUALITY ASSURANCE
RICOH, Electronic Devices Division, keeps in mind to develop devices and assure the quality putting ourselves
in customers' place. RICOH pursuits following 5 points night and day to offer the best quality timely with
the optimum cost to the customers.

REQUIRED QUALITY
REALIZATION

EARLY STAGE
CONTROL

I
TOTAL ASSURANCE
CONTROL

FAILURE RELAPSE
PREVENTION

HIGH QUALITY
HIGH RELIABILITY

I. Accomplish the quality aim satisfying the use condition and requirements of customers.
2. Control the first stage thoroughly to make in the quality on development and manufacturing steps.
3. Recognize the importance of quality through quality improvements and quality educations, and then
aim at the high quality and high reliability.
4. Inquire into the cause of failure in cooperation with other sections and take measures immediately and
completely not to meet the recurrence.
5. Complete the synthetic assurance and control system which satisfy quality, cost, and delivery.

2-1

QUALITY CONTROL FLOW CHART IN MANUFACTURE

Quality Level Check

Machines, Dimension
Environment, Process
Parameter, Sub
Materials, Operators

In-Process Q.C.

Quality Level Check

'---===:r...:..:=..::...--' ----- ------------------------------- '--_--''---.-'-___-' --- mJ,--_T_e_s_t_,I_n_s_pe_c_t_io_n_-,
------

Quality Level Check

Quality Level Check

Quality Level Check

~----~~"~----~

------1

Test, Inspection

Sample, Lot Judge,
Quality Level Check

----------------

Claims
Field Information
etc.

2-2

L---"-'-'-T""':';;';':";":'-~ ------~

Sample, Lot Judge.

QUALITY ASSURANCE SYSTEM
An effective quality assurance system cannot be undertaken on an individual basis. Only a cooperative effort
among all divisions can consistently achieve a solid guarantee of top quality. Put into practical use, a system
of this type must be functional, it must be based on the idea of standardization, and it must quickly accommodate the data and feedback that continually pass between departments.
We have developed a Quality Assurance System that incorporates these concepts. Our Quality Assurance
Department is set up to ensure fast, accurate relay of information between divisions and prompt execution
of quality assurance tasks at each step in tht manufacturing process - from product development to mass
production.
At the product development stage, the tasks required in all succeeding stages are defined and responsibility
for their execution is assigned. The Quality Assurance Department then undertakes inspections from a comprehensive point of view, through its inquiry groups. Our quality and reliability criteria are geared to meet
reliability and qualification testing standards such as MIL, EIAJ, and JIS to ensure that our product designs,
processes, and conformity to standards are approved.
At the mass-production stage, the Manufacturing Department undertakes strict control of processes, product
quality within processes, equipment, and the environment, in order to build in quality at each step. The
Quality Assurance Department safeguards overall quality by inspecting incoming materials, controlling product amendments, maintaining accuracy in measurement devices, inspecting wafers and making final checks,
monitoring quality, and undertaking quality assurance checks which ensure that no defective products reach
the market.

2-3

I

FAILURE ANALYSIS FLOW CHART

,

,

Customer

1

,

Sales & Marketing Dep.

,

Quality Assurance Dep.

T

,

: Claims (Defective devices
& Field Information)

, : Failure Analysis

1

r------ -~~.--------l

I

External Visual

I

L------~n~I.:elc!!~n------J

: Scope/X ray Video

r-------- --------, Auto Tester

r

Research Data
Process Data
Q.A. Data

:
Electrical Analysis
: Manual Checker
L--------------1 Oscilloscope
Parametric Analyzer

_ _ _ _ _ _ _ _ _ _ i----Fa;iU~e Mod-;;----.."I _ _ _ _r--------,
,,: Reappearance:
!~ii0!9!!.s_____
L ___ -- - - - I

J

L____

1

i illteri1al V~uall

Life Test
Environmental
Test

De Encapsulation
Scope
S.E.M.

L__IE~ec.!.i<::.n__ J

Manual Probe
X.M.A. (E.D.S., W.D.S.)
Cross Section
EB Tester

F.LB.

r----J-----L-----,
Classification of
I
~ __ !~i,!:J!:.e_Ml~~~i~m____ J

1

r
Production Dep.
'

I

•

111-----------~----------_<1
Design De p.'
I
Report

lL-______________~

1

,

r

+

Quality Assurance Dep.

I

j
Sales & Marketing Dep.

j

r

: Action to
Prevent Failure

Customer

2-4

: Advise and Confirmation
of the Action
Failure Analysis Report

,

,

LOT ASSURANCE INSPECTION
( +ASSEMBL Y INCOMING INSPECTION)

Sampling: Every Wafer Lot

No.

TEST ITEMS

LTPD
(%)

TEST METHODS

Maximum
Accept No.

I

ELECTRICAL
(Open, Short check)

Auto Tester
QAT Specification

5

0

2

HIGH TEMPERATURE
OPERATING LIFE

Ta = T jmax 125°C
20 Hrs.
Dynamic Operation

10

0

3

THERMAL SHOCK
(liquid)

Ta = T stgmin - T stgmax
(5' -10" -5')

20

0

20

0

I 0 Cycles
MIX PCT

TYPE A
DIP
package

TYPEB
QFP, SOP
package

TYPEC
PLCC
package

SOLDERING HEAT

260°C
Lead only
10 sec.

260°C
Full dip
5 sec.
or
IR Reflow
2 times
or
VPS
215°C
60 sec.

IR Reflow
2 times
or
VPS
215°C
60 sec.

THERMAL SHOCK

T stgmin

T stgmin

T stgmin

I

I

I

T stgmax
10 Cycles

T stgmax
10 Cycles

T stgmax
10 Cycles

PRESSURE COOKER

121°C

121 °c

121°C

2 atms
20 Hrs.

2 atms
20 Hrs.

2 atms
20 Hrs.

I

OUTGOING INSPECTION
Sampling Method: MIL-STD 105D
No.
I

DIVISION
ELECTRICAL

TEST ITEMS

CRITERIA

Function
DC
AC

QAT Specification

LEVEL
AQL
0.25%
*1)

2

* I)

APPEARANCE

Heavy Defect
Light Defect

Visual Inspection
Criteria

Catastrophic Failures (short, open, or functially inoperative) AQL 0.065%

2-6

0.65%
1.0%

RELIABILITY TEST REQUIREMENTS
TABLE I RELIABILITY/ENVIRONMENTAL
PACKAGE TYPE
TEST ITEMS

No.

TEST CONDITION
PLASTIC

1
2
3
4
S
6
7
8
9
10
II
12
13

High Temp. Operating Life
High Temp. Reverse Bias
High Temp. Storage
Low Temp. Storage
8S/8S Temp. Humidity Bias
Low Temp. Operating Life
Pressure Cooker
Thermal Shock
Temp. Cycle
ESD Sensitivity
Latch Up (CMOS Device Only)
Mechanical Shock
Vibration

CERAMIC

12SoC (lSO°C) Vcc Max
12SoC (lSO°C) Max
12SoC (lSO°C)

M

M

0

0

M

M

-SSoC (-6S°C)

0

0

8SoC/8S% RH Vcc Max
-20°C (-40°C)

M

M

0

0

121°C/ISPSIG/lOO% RH
-SS-12S°C( -6S-ISO°C)
-SS-12S0C( -6S-ISO°C)
1000V(MIL)/200V(EIAJ)

M
M
M
M
M

-

*
*

IS00g/ZI, Yl, XI
20 - 2 kHz

QUALIFY
TEST TIME
1000 Hrs.
1000 Hrs.
1000 Hrs.
1000 Hrs.
1000 Hrs.
1000 Hrs.
200 Hrs.
200 Cycles
1000 Cycles

*
M
M
M
M
M
M

-

4 Cycles
): Option

TABLE

n

MECHANICAL
PACKAGE TYPE

No.
14
IS
16
17
18
19

TEST ITEMS
Physical Dimensions
Marking Permanency
Visual and Mechanical
Solderability
Lead Integrity
(Fatigue, Forming, Pull)
Hermeticity
(Fine, Gross)

TEST CONDITION
CERAMIC

M
M
M
M

M
M
M
M

-

0

0

-

*

M

-

-

COND.B or D
-

24SoC Ssec
-

F/L: S x 10 8 ATMcc/sec
G/L: 2 Hrs. at 60 PSIG
M: Mandatory

2-7

QUALIFY
TEST TIME

PLASTIC

0: Optional

-

-

*. Not Applicable

I

QUALITY & RELIABILITY ASSURANCE FUNCTION

TOKYO (JAPAN)

OSAKA VLSI
DESIGN
DEP.

USA

NIES

REDD: RICOH ELECTRONIC DEVICE DIV.
RC
: RICOH CORP ./RATION.

2-8

3. ASSP

I

_IC_D©~®~[]{]_~/

No. 84-01 4-1-1984

REAL TIME CLOCK

RP5COl
•

•

GENERAL DESCRIPTION

PIN CONFIGURATION (Top view)

The RP5COI bus compatible real-time clock is
designed for use with most of the popular
microprocessors such as the 8085A, 2-80 and others.
Time setting and readout can be readily done in the
same manner as writing/readout in and from
meI11Cry. This RTC device features: counters for
complete 'time-of-day clock alarm, a hundred year
calendar, also a 26 x 4· bit RAM providing battery
backed up functions and applications as an
involatile RAM.
•

cs
H;

Au

OSC IN

ALAI(M

I
WI(

FEATURES

• Direct connection with CPU - Bus
.4 bit bi-directional bus: Do-D,
.4-bit address input: A.-A,
.Counters for Time (hour, minute, second) and
Calendar (leap year, year, month, date, day of the
week) are built in .
• 24 Hours, or 12 Hours am/pm display
• All the clock data is BCD encoded
• AD] terminal for ±:lO seconds adjustment
• Provision for battery-backup
•

OUT

CS

AIl.J

• Self contained 26 x 4-bit RAM
• Provision for Alarm signal, or 16Hz or 1Hz
Timing pulse output.

BLOCK DIAGRAM

I - - - - - - - - f - - + + I Alarm ALAHM
Output

10

Mode II

26 x 4bits

IU\M
Ao A, A, A,

1l,Il, ll,J),

---------------ICO®®OO3-1

RP5C01

• ABSOLUTE MAXIMUM RATINGS
Symbol
Vee

VI
Vo

p.
Topr

Tsu:

Parameters
Supply Voltage
Input Voltage
Output Voltage
Power Dissipation
Operating Ambient Temperature
Storage Temperature

Conditions

Unit
V
V
V
mW
"C
"C

Limits
-0.3-7
-0.3-7
-0.3-7
700
0-70
-40-)25

With respect to GND
Ta=25"C

• RECOMMENDED OPERATING CONDITIONS(Unless Noted: Ta=0-70"C)
Symbol
Vee
VUII

IXT

Parameters
Supply Voltage
Data Hold Voltage
Crystal Oscillation Frequency

Min
4.5
2.2

Limits
Typ
Max
5.5
5
5.5
32.768

Unit
V
V
kHz

• ELECTRICAL CHARACTERISTICS
• DC ELECTRICAL CHARACTERISTICS(Un\ess Noted: Ta=0-70·C. Vcc =5V±10%)
Symbol

Parameters

Measuring Conditions

Input High Voltage
Input Low Voltage
Output High Voltage
1011 = -400J'A
VOl!
Output Low Voltage
IOI.=2mA
VOl.
Input Current
VI=0-5.5V
II
Output Leakage Current
I~o
Standby Suppl y Current
f'T=32.768kHz
leCI
Operating Supply Current
f'T=32.768kllz
len
(NOTE I) : Current flow is 'positive' when flowing toward the Ie.
(NOTE 2) : When connected to a CPU R/W cycle·time is JOJ's .
V\H
VII.

Min
2.0
-0.3
2.4

Limits
Typ
Max
Vee
0.8
0.4
±IO
±10
15
250

Vee=2.2V
Vee =5.0V(N2)

Unit
V
V
V
V
J'A
J'A
J'A
J'A

• AC ELECTRICAL. CHARACTERISTICS(Un\ess Noted: Ta=0-70"C, Vec =5V±5%)
Symbol
tAe
tee

teA
t.o
tROll

t wUl.

two

Parameters

Measuring Conditions

Address- 1m/WI{ Delay Time
Im/WR Pulse Width
Address Valid Time After
Rise
Data Delay Time After RD Fall
Data Hold Time After lID Rise
Data Delay Time After WR Fall
Data Hold Time After WI{ Rise

Min
170
400

Limits
Typ
Max
10000

340
0
40
20

ns
ns
ns

10

IID/WR Pulse

Unit

ns
ns
ns
ns

-IIO@®OO-------------3-2

RP5COl

SI'ECIFICA TIONS Under Vee = 5V ± ]0% are as follows .
• AC ELECTRICAL CHARACTERISTICS(Unless Noted: Ta=O-70"C, Vcc=5V±IO%)
Symbol

Adress- RD/WR Delay Time
RIT/WR Pulse Width
Effective Address Time After
RIT/WR Pulse Hise
Data Delay Time AfterRD Fall
Data Hold Time After RD Rise
Data Delay Time After WR Fall
Data Hold Time After WI< Rise

t AC
tee

teA
t M\)
tlt!)11

tWill.

twu

•

Measuring Conditions

Parameters

Min
170

Limits
Typ
Max

~~ - - - - 10000

ns
ns
ns

10
400
0

40
20

Unit

ns
ns
ns
ns

PIN DESCRIPTION

CS, CS

Pin No.
1,2

ADJ

3

A.-A.

~

4,5,6,7'
8
9
10
11, 12, 13, 14
15

asc. N , aSCO"T
V,e

16,17
18

Symbol

1m

GND

Wif
0.-0,

Function
Valid when CS=II, CS"=L CS is
connected to the power-down detector of peripheral circiut power supply,
and CS" is connected to the microcomputer.
This pin provides easy zero setting for the "seconds" independently of the
CPU. When ADJ = II in the range of from 0 to 29 secs, the "seconds" are
preset at zero and not released in the range of 30 to 59 secs by countup
until the full minute expires.
ADDHESS pin. Connected to ADDlmSS bus of CPU.
I/O control input. L when CPU·· RI'5COI.
OV
I/O control input. L when CI'U~RP5COI.
Hi-directional data bus. Connected to the data bus of CPU.
Alarm signal and pulse (1611z CK or IlIzCK) are put out. Open drain
output.
Crystal resonator connecting terminal. 32. 768k lIz.
+5V power supply.
Termirlals for external interfacing.

---------------ICO®®OO3-3

I

RP5COl

• ADDRESS MODES
MODE
A,-A.
II

Contents

MODE 00
D,
1),

0,

D"

Contents

I Sec Counter

I

III Sec Counter

2

I Min Counter

3

III Min Counter

x

x

-1

I IIr Counter

5

III IIr Counter

x

6

Day Counter

x.

7

I Day Counter

R

III Day Counter

9

I Mo Counter

A

10 1,10 Counter

B

I Yr Counter

C

10 Yr COllnter

D

~IOOE

E

TEST Register

F

RESET Controller
ane Others

Register

Alarm
I ~Iin Register
Alarm
III Min Hl'gister
Alann
I II r Register
Alarm
III II r Register
Alarm
Day Hegister
Alarm
I Day Hegist"r
Alarm
!tIDay Hegistcr

x

x

x

x

x

X

TflTi'/24 IIr
Selector
Leap Year
COllnter

MODE 01
D,

0,

D.

x

x

x

x

x

x

x

x

D,

10

11

Contt'nb; Contents

block
10

block
II

4bit

4bit

x

x

1:1

13

RAM

HAM

x

x

x

x

x

x

x

x

X

x

x

x

x

x

x

X

x

x

x

Timer

J\larm

EN

~:N

MODE Register
MI
Mil

Timer
EN

Alann
EN

MODE Register
MI
MO

As
at left

As
at left

Test
3
IlIz
ON

Test
2
1611z
ON

Test
Test
I
II
Timer Alarm
RESET RES~:T

Test
3
IlIz
ON

Test
2
1611z
ON

Test
Test
I
0
As
Timer Alann at left
RESET RESET

As
at left

x indicates: don't cart' for WI{, always zero for I{D.

-IlO®@OO------------3-~

RP5COl

• MODE REGISTER (A" A" A .. Au)
D.t

D,
MJ

Timl'r

EN

o

(I, I, 0, 1)

DII
Mil

EN

Time setting and readout
Alarm, 12Hr/241Ir & Leap Year setting and readout
RAM Write & Readout. ,BLOCK.lO
RAM Write & Readout. BLOCK.ll
I : Alarm output ENABLE
0: Alarm output DISABLE (16Hz and 1Hz signals have no relation)
1 : Time count starts
count after Second stops

o : Time

• LEAP YEAR Counter
Leap year when 0, =0,=0. It counts up
simultaneously with Year Counter.
• 12h/24h Selector
24-hour counter when Do = 1
12-hour counter when 0 0 =0
I'M when 0, = I, and AM when 0, =0 respectively
of IOh counter
• RESET Controller 16Hz· IHzCK Register
(A" A" A.. Ao)=(I, I, I, 1)=1'
Do = I: Resetting of all alarm registers
D, = I : Resetting of frequency divisions before
Second
D, =0 : 16Hz CK pulse ON
D, =0 : 1Hz CK pulse ON

• ADDRESS 0- D
Both READ and WRITE are possible.
.ADRESS E-F
WRITE only is possible.

--------------1l0©®(]{]-3-5

I

RP5COl

•

TIMING .DIAGRAM
• WRITE CYCLE (CS="H")

CS

/

\

I--tCA-l

r
Do-il,

1(
Iwn

1

tAr

l~

WI{

j
~I

"'

I.t:l'

READ CYCLE (CS="H")

t---t<~

)

/

}(
t HIIII

1\

Do-il,

..jl

tM'

I

t !til

-f
"I

1i

-,

tn:

•

APPLICATION NOTES

1. Oscillating Circuit
1-1 When using a crystal oscillating element.
The oscillator circuit is shown in Figure 1.
Externally connected parts consist of : resistor,
capacitors and a trimmer capacitor. To adjust the
frequency, use the trimmer capacitor (The 16Hz or
1Hz signal output at the ALARM pin should be
used), for calibration.
When calibrating with the 1611z signal:
The Address is (A" A" AI, A.)=(1, I, I, 1).
The Data is (1, n, 0, x).
When calibrating with the I Hz signal:
The Address is (A" A" A .. A.)=(l, I, I, 1)
The Data is (0,1,0, x).

OSC IN

.---'VV'v--....,

a

GND
C I = IOpF -30pF

RP5COl

-C,=:lOpF
C:t=·56pF'

It =100kO
(Thl' crystal emph)y(~ i~ Nippon 1>el11pa KOJ(Yo MX:Un'l~r ('(lui\'f11('III)

Fig. 1

-ICO©®OO·
3-6

RP5COl

1-2 When using an external Clock
The external clock should be connected through the circuits shown in Fig.2(a), and (b).
should be left with no connection.
() S CrI_N-"v",,"~--'

/

The OSCOUT pin

OS C..-'I:.:.N'-AJ'J\r_-,

()SC OUT

/

''"" OOT

CMOS (·1096)
TTL( 74LS04)

RP5COl

RP5COl

Fig.2 (b) TTL INVERTER CONNECTION

Fig.2 (a) CMOS INVERTER CONNECTION

2. Input/Output, and Chip selection Pins.
2-1 Input/Output Pins
In order to stabilize the potential at the Input/Output Pins during 'battery backup' operation, and a pull
-down resistor (IOO-300kO), and a pull up resistor (4.7 -47kO)

1--_-- TO 1'11" POW"R SUPPLY CmCUIT
TO TilE POWEIUlOWN
S"NSING CIRCUIT

:1

3qAllJ

OSC IN

HI!

ALARM

IS

J-~==----,

1\1>
S

A,

0

A,

7

A,

K

I\ll

!1

GND

1\1>

D,

Ill>

1(,,= lOOk!} -:lOOk!}

~~~----~---5V

1\1>

1\,.=4.7k!}-47k!}

HI>

Fig. 3

2-2 Chip selection Pins
There are two chip selection Pins. The CS pin should be connected to the powerdown sensing circuit, and
the CS pin to the CPU. CS is active "H", whereas CS is active "L".

--------------uo©®oo3-7

I

RP5COl

3. Interfacing with typical CPU
3-1 Applicable CPU
CPU

(NOTE 1) Not needed when the X'tal used is below
5MHz

External Circuit
Nil
74LS74 (NOTE J)
74LSOO, 74LS04

Z-80A
808SA
6800

3-2 Standard Interfacing examples.
Examples of Interfacing the RTC with typical
CPU (Z80,8085,6800) are presented hereunder.
(I) Z80
The Data Bus, Address Bus, and Ru, WR pins
are connected to the corresponding pins of the Z-80
(the same symbols are used). The CS pin of the
RP5COI should connect with the IORQ pin, or one
Bit of the Address Bus (e.g.A.).

~o~

::s

f-<
::0

RP5COl

uu o

DaD, DzD,

AfJl\.lA z A3

-RD WR CS

'-v---'

'----v--'
CIlUl

UlUl

00

«'UJ

en::.J

f-<::O

iijOl

~Cll

a

0
0

-<
Fig. 4

I~I~I~

Z-80

CONNECTION DIAGRAM WITH Z-80

TIMING CHART

'1',

CLOCK

--'

Z-80

11 0 -11,
[()I{(l
HIl

.-

T,

'1',

'1;'

T,

~ ~ ~ ~rL

:,..-

IX

- D\
\

/

i\

/
}

RP5COl
Z 80

RP5COl

lJo-l)'
WH
Il o-I)'

READ

CYCLE

{?,\JTl'U'I/

/

1\

} WRITE

CYCLE

INPUT

II

- .I C O ® ® O O - - - - - - - - - - - - - 3-8

RP5COl

8085
The Data Bus, Address Bus, and RD, WR pins of
the RTC correspond with those of the 8085 (the
same symbols are used). The C"S" pin of the
RI'5COI should connect with one Bit of the 8085

(2)

Address Bus (e.g. pin Ao).
When the crystal oscillator used has a frequency of
6MIIz, a 74LS74 (externally connected circuit shown
in the dotted line) should be added to provide I·
Wait.

Connection Diagram

o
RP5COI

I

r-----------,
I
I
I

L __________ _

Fig. 5

CONNECTION EXAMPLE WITH 8085

Timing Chart
'1",

CLOCK

8085

{

A;-A"
ItEAIl

I
- LrLrLrLr
Lr
T~

WIUTE

T.

T,

- lX

'i
!

1\

{itm;u:r
L~

RP5COI Il,,-Il,
8085

Tw

II.........:.

I

READ

CYCI.E

1\
}

RP5COI Il,,-Il,
8085

HEAIlY

WRITE

CYCLE

INI'UT

LJ

--------------ICO@®OO3-9

RP5COl

connected to the " and RjW pins of the 6800, but
with the addition of the following: two 74LS()4
inverters, two input NANDs and two 74LSOO.
Besides, the CS pin of the RTC should be connected
to one Bit of the 6800 Address Bus (e.g. A.).

6800
The pin connections for the RTC are compatible
with the Data Bus, Address Bus of the. 6800. (The
symbols are the same).
The RD. WR, pins of the RP5COl should be

(3)

Connection Diagram

"I',

Timing Chart

o
6S00

RP5COI

J

I

=x'--_____>C

R/W

x=:

J

All))

-----J'jIIEAIJ

L - -_ _

CYCLI,

D.-D,
DATA Bl'S ADLJHESS -

CYCLE

Do-D,

Fig. 6

. ~_

INPUT

.

3-3 Interrupt into the CPU

The Data of RI'5COl is read-out by using
Interrupt to the CPU at the rate of once every
second.
III

(2)

8085

RP5COl

-ALAI{M

ZSO

1'"Z

RP5COI

I{ST7.!i

SOS5
(::) 6800

z-SO
RP5COI
AI.AI{M

1,Il?SI<;NAL

.------..L.....,
NMI

6800

-ItO©®oo-:--~--------,------3~10

RP5COl

4, Example of a program for setting Time/Alarm
4-1 Flowchart for the time setting operation
By setting Data (D3 , D,. D,. Do) in the test register
(Address (A 3 • A2 • A,. Ao)=(l. I. 1. 0)), operation of
the clock is maintained.
(1)

Timer Setting Program

(2)

TIMEII IS STOPPED
MODE

I

"H" input voltage
"L" input voltage
"H" output voltage
"L" output voltage
Input leakage current
3-state floating current
Supply current
Clock input "H" input voltage
Clock input "L" input voltage

Condition

IOH = -400/.LA
IOL = 3.2mA
O~ VI ~ Vee
0.4 ~ VI ~ 2.4

Value
Min.
2.0
-0.3
2.4

Typ.

Max.
Vee + 0.3
0.8
0.4
10
10
50

0.7 x Vee
0.3 x Vee

Unit
V
V
V
V
Jl.A
Jl.A
rnA
V
V

---------------IlD©®[}{]3-31

RF5C 16A/RP5C 16
• AC characteristics (Vee =S.OV ± 10%, Ta =-10-70°C) and Timing diagram
(1)

(Unit: ns)

CPU-5C16 READ/WRITE
No. Symbol

I
2
3
4
5
6
7
8
9
10
11
12
13
14

taee
tder
twrh
ther
tddr
thdr
tdew
twwh
twwl
thew
tsdw
thdw
tddg!
tddgh

15

tdinll

16
17

tdinl2
tdinh

(1-1)

Parameter
Access time from "Cs. Ao-A. and DACK
RD delay time from cs. Ao-A. and DACK
RD pulse width (H-threshold)
CS", Ao -A. and DACK hold time during read
Data delay time from RIi
Data hold time during read
WR delay time from CS A.-A. and DACK
WR pulae width (H-threshold)
Wi: pulse width (L-threshold)
CS, Ao-A, and DACK hold time from WR
Data setup time
Data hold time during write
DREG • delay time from CLK OUT
DREG t delay time from CLK OUT
INT • delal time from RJ) or WR
(End of IN by Buffer Ready)
INT • delay time from CLK OUT
INT t delay time from CLK OUT

CPU READ 5C16

Value
Typ.

Min.

(1-2)

.,-A,

Max.
200

90
60

ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

410

ns

120
90

ns
ns

30
10
5
120
85

0
30

Unit

10

ISO
10
ISO
10

CPU WRITE IN 5C16

::::::><1--------1><'----(I,

twwh

'"

,~.'"
tal ..

o.-o,---====CFG3--CFG2io---CBG3
CBG2
>===="CBD:n
CBD·cSL-SV-X-SH

Transfer Reldster L
Transfer Redster M
Transfer Address L
Transfer Address M
Transfer mode interrupt muk
DIsDlay mode
Cursor coordinate HL
Cursor coordinate V
Chara. Gen. Baae Address M cunor coordinate CsHm
Fore Ground Baae Address M
Back Ground Baae Address L
Back Ground Baae Address M
FG 3rd color FG 2 color
BG 3rd color BG 2 color
BD color (DOriDheral
BD color center
Dot Scroll V direction H direction

RD>
0
I
2
3
4

MV

MH

MB

TR·L
TR·M
Add·L
Add·M
X
FV

FH

FB

X

Transfer Reldster
Transfer Reldster
Transfer Address
Transfer Address
InterruJlt nag

L
M
L
M

--------------IIO@®[}{]3-35

RF5C I 6A/RP5C I 6

• Description of function
(1)

Display mode

• Following 4 display modes are available.
B. 640 X 200 dot graphic dispaly mode
(only back ground)

A. 80 character X 25 line character
display mode (only back ground)

640 dots

80 characters
:l
.!l

.."til

~

'"
0
0

'5

M

."

M

D. 40 character - 320 dot display

C. 40 characters - 40 character display mode
Background

Background

I
I

40 characters

·1

~'

.!l

"~

-~
t;

."

'5

..til

-5
M

Jore ground

40 characters

f-

"0

-~

'"00

I
I
________ JI

~

M

--"'"

."

M

(2)

40 characters
I
I
I
_ _ _ _ _ _ _ _ 4I

."

M

Picture simultaneous display (display mode 3 and 4)

• 2 pictures of fore ground face and back ground
face are simultaneously displayed.
• When overlapping of FG face pattern with BG
face pattern, FG face is displayed.
• In case where there is neither pattern present on
FG face nor on BG face, backdrop color (CBD-C)
is displayed.
• As far as the distance ranging from the outside of
display window to the edge of cathode ray tube,
the color of backdrop face (CBD-P) is displayed.
(Backdrop color is specified by register E)
(3)

I ~ore groun d

320 dots

:20INPOTAA
30: FOR S=1 TO 14 STEPO.2
40: W=2*3.14*S
50: 8=A

---

BGface

~

I
Backdrop face

I
FG face

15 color display

15 colors can be displayed.
Color

Color code

B

G

R

Black

I

Red

1

Green

I

Yellow

1
1
1
1

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0

B

G

R

0
0
0
0
0
0
0
0

0
0
0
0
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1

Magenta

0
1

Cyan

1

1
1

Color

Color code
Lid

Lid

Blue
I

1

Gray

Black
Pink
Light Green
Light Yellow
Light Blue

1

Light Magenta

0
1

Light Cyan
White

-ICO©®OO--------------3-36

RF5C I 6A/RP5C I 6

(4)

R, G, B output

• V -SYNC, C-SYNC and H-SYNC terminals tum to output terminal (open drain)
under master mode and to input terminal
under slave mode.
(Refer "Terminal function (3) Clock and
Video output")

• Following outputs are held as image signal.
R, G, B, Lid, C-SYNC, V -SYNC and
H-SYNC
• RGB terminal takes the following output
levels at 3 value output.
Max.
Vee
M·LEVEL+O.4
0.4

Min.
4.4
M·LEVEL-O .6
-

High
Middle
Low

Vcc=5V, M-LEVEL=2.5V, Io=±lmA
(5)

I

Character display

• The size of character at character display
is 8 X 8 dots.
• Fonts are kept in memory area of 2K
words from character generator base
address (BCG-M).
(Max. 256 kinds)
• Data of code area
b,

IColor code I
lst color

• Configuration of character font

~-llilllllll
bo

I
Character code

Attribute

008811

Font of

000811

character

006811

code -'ooH"

OOARII
007011
OOASII
007011
000011
fnOl1
ff8811
fF8811
FFF811

@

Font of

character
code"OlH"

A

0:0
.:1
• When

displaying

MSByte

in

~~~:~ c~~~~~t:~C~tc~S al~lf,~~~~;
all "1" is used .
• When drawing the picture such

as game, etc, 4 colors can be

.Character
generator value

00
01
10
11

(6)

displayed at each dot with 2 bit
of combination such as bit 15
with bit 7, bit 14 with bit 6 and
so on.

Display
color
Qear
1st color
2nd color
3rd color

2nd and 3rd colors are specified
by control register(C, D).

Graphic display

• I dot is consisted of 4 bits, and 8 dots are
allocated as I block.
• Display color is decided by 4 face synthesis of R, G, B and Lid.

t-1

BSG+2
LId

tt

~~~

o

/v

0

0

+o +0 +0 ..

II
display screen

$P

1'1 I I I I I 1

BBG+4
Lid: Light/dark
8: BLue

G:Gretn
R:Red

---------------1I0©®[]{]3-37

RF5C I 6A/RP5C I 6
(7)

Attribure (character display)

• 4 kinds of attribute can be decided with bit
8 - bit 11 of code area data.

Black white invert

Longitudinal invert

Transverse invert
lU~ck

white invert : Invert hi color and dear

'----~ Transverse invert

: (IIvcrt priurity uf display

' - - - - - - - Longitudinal invert: Invert longitudinal of ('('11

' - - - - - - - - - - Vertical invert

: Invert vertical of cell

b9-0
F,G

bl1=1

F.G

Shape of cursor
9 dots

Dot scroll (only back ground)

• It allows scroll of 0 -7 dots in the horizontal and vertical directions. The number of
shift to the horizontal and vertical directions is specified by respective dot scroll
register SH and SV.
(10)

0

Cursor

• Cross hair cursor is displayed. The coordinate of cursor in the horizontal direction is
specified with 10 bits of cursor register
CsHm and CsHL while in the vertical direction with 8 bits of CsV. 2 bits of cursor
register CsHm will not become effective
unless CSHL is written.
(9)

bl1~

~!] ~~
B.G

(8)

Vertical invert

b9-1
B.G

Shift to VertiCal

,......

~

di:.~C:~ior r~
Shift to horizontal direction

Control of video memory area

• Base address
BG base address (BBG.M, BBG-L) is
consisted of 16 bits and allows to specify
by I character unit. Therefore, the change
of BG base address allows scroll in the
column or line direction. BBG-M becomes
effective when BBG-L is written. Those
subsequent to this address area fall in code
data of back ground. In case of graphic,
too, data are stored here.
FG base address (BFG-M) allows paging
of each 1,024 characters with 6 bit. Subsequent to this address, code data of fore
ground are stored in 1,000 words (40
character X 25 line).
Character generator base address (BCGM) is able to specify the start address of
character font for each 2,048 words

with 5 bit. Character font is consisted
of 1 cell 8 words and is able to select
256 patterns. (Refer diagram) It will
not be used for only graphic display.
8 7

OOOOH
BFG-M

Bac'M, L.

Bcc-M
I
I
I

I
I
I
I
I
t
I
IL ___ .JI _____ .L
I _________ I

~

mrH

-ICO©®DO-------------3-38

RF5C I 6A/RP5C I 6
64 K word max.

• Width of code area (No. of character AH)
FG is fixed with 40 characters. BG can
be selected from 40 characters (320 dots),
64 characters (512 dots), 80 characters
(640 dots) and 128 characters (l,024 dots).
With this, the width of virtual screen is set.

Roc·M.1.

B.C
Cade Area

Display
window

------:-A-.- - - - I
(Code area, number of character
in horizontal direction)

(11)

Updating function of frame buffer

• The mode of increment + 1/+2+2 of
address counter is used in graphic
display, for example, only the face of
BLUE is rewritten in sequence.

• Since it has the transfer register and address
counter, it allows read/write of frame
buffer data, making use of retrace line
section in horizontal/vertical direction
without relying on externally mounted
circuit.
• Write mode/read mode/read modify write
mode (see diagram below)
• Word transfer/Byte transfer (see diagram
below)
Readm lilywrlte
Rudmode
Writcmodt
Word UUIIIer Byte tnnIIu Word lnDIfcr Byle uanslOI" Word tnDIf'or Byte " ....I.r
ReadT.....
Add+l-RT

RudTR-L

WriteTR-L

WT-Add+l

WT-Add+l

WriteAdHI
WriteAddo-L

Ad4+1-RT
Add+l-RT

WT-Add+l

wr

WT-Add+l

WriteTll-M

• DMA transfer
In case of DMA transfer, it is necessary to set whether to read or write to LSB
of transfer register, or to read or write to
MSB. In case of word transfer, TR-L
and TR-M vary at every 1 byte. In case
of byte transfer, it is always written in
the register that has been set.

wr

wr

WT-Add+l
-RT

-RT
WT-Add+!
-RT

RT

RT

RT

RT

RT: Read UUlIf., (frame buD'. read)
WT: (frame burr., wrlle)

TR: TraIlIf'err....ter
Add: Ailldreu COWlter

The reiadO!llhip .. -" blcwetII. rad/wrlte opeladoD of trlRlf" ,...,., .nd read/write IoWald I'rame burr.r
reprelenb the IeqlHlDCe ofproc:ea. For ......,... when CPU ddt read TR·L lqisl" under (I.d mode), fUll of

aD, number of addrna cowuer ...t
are belna taken for frame buffer.

(12)

u +1, then, perform ..... orrram,tn.rr" ... _ .. reprelCfttithat no stops

O-RAM refresh

• 8 addresses per 1 H (64 ps) are refreshed
within retrace line section.

Vertical retrace
line section

Display section
D·RAM

refresh
(8 cycle)

!-1~~~~~~~=+~=I=± Vertical retrace
line section

2.311s

Horizontal
line section

Horizontal
line section

---------------ICO©@IXl3-39

I

RF5C I 6A/RP5C I 6
• 64 pin flat package dimension (Unit: mm)
(976"'" )

(.787

)

• 64pin OIL package dimension (Unit: mm)

f~
::: \
-L

0.25 +0.13
-0.05

~.
0 -15

-ICD©®OO-------------3-40

~I

!!!!!!!!!!!!I
C!!!!!!!!!!!!!!!D
©!!!!!!!!!!!!!!!®!!!!!!!!!!!!!!!OO

No. EKH-9-871 1

QUAD.UART
RF5C59

• GENERAL DESCRIPTION

RF5C59 is the CMOS LSI with 4 channels of serial port built-in for application to asynchronous
communication. The operations including transfer rate, transmit/receive of communication and etc.
can be specified by program independently for each channel and it allows the use as peripheral circuit
of CPU.

• FEATURES

• Double-buffer mode transmitter/receiver
• Dual transmit/receive of communication is practicable for all 4 channels.
• Setting of transfer rate at each channel for both hardware and software is practicable.
When input clock is 14.7456 MHz, the following rates are applicable.
614.4 KHz, 307.2 KHz, 153.6 KHz, 76.8 KHz, 38.4 KHz, 19.2 KHz, 9.6 KHz and 4.8 KHz.
• Freedom of combination of logical address with physical address for 4 channels.
• Data length 8 bit, stop bit I bit fixed.
• Overrun and framing error are detectable.
• Error start bit is detectable.
• Direct connection to 8 bit bidirectional data bus and data bus is practicable .
• 4 bit address input.
• Hardware interrupt signal of TXRDY and RXRDY that can be masked.
• Connection to high speed CPU is practicable.
• 5V single voltage supply.
• 60 pin flat package.

• PIN CONFIGURATION

:.
TXRDY
RXRDY
WR

Ii

~

55

35

TEST

30

RXCA
RXCB
RXCC
RXCD

1m
CLK
GND

60

V"

A2
Al
AO

c/o

25

Cs
::

~

.:

TXU
TXCA
TXCB
TXCC
TXCD

--------------ICO©@OO-3-41

I

RF5C59
• BLOCK DIAGRAM

DO- D7

AO- A2
C/D

CS
Rii

WR
CLK

T T

X X

R R

X X

D CDC

A A

A A

T T
X X

R R
X X

D CDC
B B
B B

T T

R R

X X

X X

D CDC
C C
C C

T T

X X

R R

X X

D CDC

D D

D D

• DESCRIPTION OF FUNCTION

RF5C59, which is the UART for data communication, is used as peripheral circuit of CPU, and
operation under serial data transfer mode can be specified with program.
RF5C59 has the transmit/receive ports with 4 channels, which receive parallel data from CPU,
convert them into serial data and feed them out from TXD * terminal. In addition, RF5C59 receives
data fed to RDX * terminal and feed them to CPU.
All 4 channels are controllable independently. Reading of status register 1 will not only make it
possible to find the condition of transmit/receive operation but also allow to notify CPU of hardware
interrupt signal from TXRDY terminal and RXRDY terminal.
The combination of logical port with physical port can be freely set with instruction register 3.
In other words, logical ports in plural number can be assigned to one physical port. The transfer
rate is 1/(24 * n) of input clock. (n: 1,2,4,8, 16,32,64, 128)

-.- I C O © ® [ ] { I - - - - - - - - - - - - - 3-42

RF5C59

• PIN DESCRIPTION
PIN No.
6,7,8,9
10,11
12, 13

Symbol

DO

-

I/O
I

D7

36

RESET

I

5

CS

I

57

WR

I

58

RD

I

4

C/D

I

1,2,3
56

A2,AI
AO
RXRDY

0

I

59

CLK

I

20
21
22
23

TXDA
TXDB
TXDC
TXDD

0
0
0
0

IS
16
17
18

RXDA
RXDB
RXDC
RXDD

I
I
I
I

29
34, 37

Vee
Vee

14
19,60

GND
GND
TXRDY

55

28
54
53
52
51
50
49
48
47
45
44
43
42
41
40
39
38
27
26
25
24

TX 24
DlVAEN
DVRA2
DVRAI
DVRAO
DlVBEN
DVRB2
DVRBI
DVRBO
DlVCEN
DVRC2
DVRCI
DVRCO

~

DVRD2
DVRDI
DVRDO
TXCA
TXCB
TXCC
TXCD

33
32
31
30

RXCA
RXCB
RXCC
RXCD

35

TEST

Function
Bidirectional 3 state data bus used for transfer of command, data and status between RFSC59 and CPU.
TTL compatible input.
Reset input. Active LOW. During reset,
• All interrral registers turn to reset or default value.
• Transmit outputs TXDA and TXDD turn to mark (HIGH) condition.
• All transmit/receive ports are enabled.
• TXRDY and RXRDY lines turn to active.
(CMOS compatible Schumit input)
Chip select input. Active LOW. Wh-en CS is at LOW level, it allows data transfer
with CPU. TTL compatible.
WR input. When WR is LOW and CS is LOW, the data on DO""'" D7 are written
in this LSI. TTL compatible.
RD input. When RD is LOW and CS is LOW, the content of internal register of
specified address is read on DO . . . . 07. TTL compatible.
C/O represents the input which informs whether the data on the bus is control
information or status information. TTL compatible.
Address input. TTL compatible.
Interrupt signal to CPU which informs the receipt of data. If the data exist in
anyone of the receive ports being unmasked by RIM * flag of instruction register
1, it turns to LOW. When the data are read from all unmasked receive ports and
each receive buffer has the space, it turns to HIGH. When RIM* flags are all
turned to 1, it also turns to HIGH. Meanwhile, aparting from this signal, CPU is
also able to confirm the existence of receive data by reading RXRDY bit of status
register.
System clock input. CMOS compatible.
Transmit receive section of channel A -- D serial data output. Following the start
bit, it is output from LSB and after MSB, 1 bit of stop bits is added. During
disable of port or during idle, it holds the "MARK" condition. With 'Mark' at
HIGH level and 'Space' at LOW level, it performs Enable/Disable of coordinate
ports with bit 7 and bit 3 of instruction register 4 and 5.
Receive section of channel A""" D serial data input. Receive from LSB. 'Mark'is
HIGH and 'Space' is LOW. It performs Enable/Disable of coordinate ports with
bit 7 and bit 3 of instruction register 4 and 5.
+5V power supply. Make sure 29 Pin is connected with power supply.

0

0
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I

0
0
0
0
0
0
0
0
I

Interrupt signal to CPU which informs that the data are transmissible. If anyone
of the transmit ports unmasked by TIM* flag of instruction register 1 is in trans·
missible condition, LOW output. (NOR output of TXRDY flag of each port)
When TXRDY flags of all ports are masked, it turns to HIGH. Meanwhile, apart·
ing from this signal, CPU is also able to confirm the condition of transmit register
buffer by reading TXRDY* flag of status register 1.
1/24 frequency division output of CLK input.
Preset input by hardware of transfer rate. When DIV*EN is LOW, transfer rate

~h~~O~~iO~\FJ~:t~~g~~i~r~~~f~/~rt~t i~d~~:~~d ~; R~::t~' ~rYt~e:l i~~~s?r~~too~

register 4 and S. All pull-up Schumit input. When CLK input is 14.7454 MHz,
the transmit rates are:
Frequency
division ratio
Transmit rate
DVR*2
DVR*1
DVR*O
(vs. CLK/24)
614.4 KHz
L
L
L
I
307.2
L
H
L
1/2
153.6
H
L
L
1/4
76.8
L
H
H
1/8
38.4
L
L
H
1/16
19.2
H
L
H
1/32
9.6
H
H
L
1/64
H
4.8
H
H
1/128
Transfer clock output during transmit of each port. Transmit data are output in
synchronizing with the rise of this clock.

Transfer clock output during receive of each port.
taken in synchronizing with the rise of start bit.

Frame synchronization is

It turns to test mode at HIGH active. 1/24 frequency division circuit of eLK is
bypassed under the test mode. Normally. it is kept LOW.

---------------ICO©®OO3-43

I

RF5C59
• ABSOLUTE MAXIMUM RATING
'-.

Test
condition

Parameter

Symbol

--

Vee

Supply voltage

VI

Input voltage

c----Vo
r-----tPd

1--------- f---

Topg

GND=OV

Output voltage

Unit
V

-0.3- Vee +0.3

V

-0.3- Vee +0.3

V

200

rnW

0-70

t:
t:

Power consumption
Operating ambient temperature

I--

• DC CHARACTERISTICS (Ta = 0 -70'C, Vee

~bOI

--

':"40-125

Storage ambient temperature

Tstg
L - - -_ _ _

= 5 V ± 10 %)
Test
,---_.condition
MIN.

Parameter

Value
TYP.

MAX.

Unit

"R" input voltage (TTL)

2.2

Vee +0. 3

V

VIL

"L" input voltage (TTL)

-0.3

0.8

V

VIH2

"R" input voltage (CMOS)

Vee xO. 7

Vec+0.3

V

VIL2

"L" input voltage (CMOS)

-0.3

Vee XO. 3

V

VOH

"R" output voltage

VIH

- - - - - f---------1---

Value
-0.3-7

r---

IOH=-4rnA

V

2.4

V

"L" output voltage

IOL=4rnA

0.4

ILl

Input leakage current

O;;;;VI;;;;Vee

±10

J.lA

I LO

Output leakage current

0;;;; VO;;;; Vee

±10

J.lA

VT

Input rise threshold voltage

3.8

V

VT

Input fall threshold voltage

Icc

Supply current

20

rnA

VOL

V

1.3

'-------'----

• AC ELECTRICAL CHARACTERISTICS
Symbol

TYP.

MAX.

Unit

WR pulse width

200

ns

Twos

WR data setup time

60

ns

TwoH

WR data hold time

45

ns

WR before rise - address setup time

50

ns

TWA

1

WR after rise - address hold time

80

ns

T ACS

I

CS after fall- address setup time

0

ns

TcsA

_I

CS before rise - address hold time

0

ns

I

L_~_~RD
1

t~~- I
TDH

t

Value
MIN.

Tww

[T,"
!

Test
Condition

Parameter

I

TRA

I

CL=100pF

RD data delay time
RD data hold time

!~_~RD before rise -

ns

200

pulse width

-

I

address setup time

RD after rise - address hold time

105

ns

10

ns

50

ns

80

ns

-.- I C O ® ® O O - - - - - - - - - - - - - - 3-44

RF5C59
• TIME CHART
A2, AI,

>

AO, C/D

C><
-E-TACS ~

CS

"'"" TcsA";'

~

/'

~ TAR - - - , ; . - E - - - TRR

TRA-

RD

V

""'"

~ TDH~

~TRD~
/'

DO -D7

"-

VALID

'-,

f

D:,~:-----------t-->f h",,~T""~
k--

Tww

TAW----'>

-~

TWA-

I

______

• EXAMPLE OF APPLICATION
TXDA
Personal

r -------------------1
I

RXDA

I

I

I
I

TXRDY

I
I
I

RXRDY

I
I

~
I

TXDB

I

I

I

computer

QUAD
Address
control

CPU

J\
V
~

IA

Data bus
'f

I

UART

I

RF5C 59

I

I

TXDC

I
I

--y

Printer

RXDB

I

Host

I

l

Modem

RXDC

~ Telephone line

~
I
I

I
L

TXDD

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ -1I

Control device

RXDD

Host machine

(D&A)

r-- Sensor signal

Peripheral devices

---------------ICD®@o{]3-45

RF5C59
• REGISTER MAP
register

instr. 1

b7

b6

b5

b4

b3

b2

b1

bO

RIMA

RIMB

RIMC

RIMD

TIMA

TIMB

TIMC

TIMD

L. P. A

L. P. B

L. P . C

L. P. D

L. P. A

L. P. B

L. P. C

L. P. D

ERSTB

ERSTC

ERSTD

o : non

mask

1 : mask
INIRER

-------- --------

o : NOP

instr. 2

1 : Ini tial Reset
LPAbl

LPAbO

LPBbl

-----

ERSTA

LPBbO

LPCb1

0: NOP
1 : Error Flag Reset
LPCbO

LPDbl

LPDbO

BDIV1

BDIVO

11 : physical port A
instr. 3

10: physical port B
01 : physical port C
00 : physical port D
ENLPA

instr. 4

ADIV2

L. P. A

o : DIS
ENLPC

CDIV2

o : DIS

CDIV1

ENLPB

physical port B

o : DIS

note 1

1 : ENA
CDIVO

ENLPD

DDIVI

DDIV2

o : DIS

note 1

DDIVO

note 1

1 : ENA

RXRDYA

RXRDYB

RXRDYC

RXRDYD

TXRDYA

TXRDYB

TXRDYC

TXRDXD

L. P. A

L. P. B

L. P. C

L. P. D

L. P. A

L. P. B

L. P. C

L. P. D

0 : no receive data

0 : transmi t busy

1 : receive data in buffer

stat. 2

BDIV2

L. P. B

note 1

1 : ENA

stat. 1

ADIVO

physical port A

1 : ENA
instr.5

ADIV1

1 : transmi t ready

FREA

FREB

FREC

FRED

OVEA

OVEB

OVED

OVEE

L. P. A

L. P. B

L. P. C

L. P. D

L. P. A

L. P. B

L. P. C

L. P. D

0 : no error

0 : no error

1 : framing error

1 : over run error'·

*

*.

L. P.
Logical Port
note 1 : 000: 1/1. 001: 1/2. 010: 1/4. 011: 1/8. 100: 1/16. 101: 1/32. 110: 1/64. 111: 1/128

• ADDRESS ASSIGNMENT OF REGISTER
C/D

A 2

A 1

A 0

L

L

L

L

L

L

L

L

L

L

L

H
H

H
H
H
H
H
H
H

L
L
L
L

H
H
H

write register

read register

TXDA (Logical port)

RXDA (Logical port)

H

TXDB (Logical port)

RXDB (Logical port)

L

TXDC (Logical port)

RXDC (Logical port)

H

TXDD (Logical port)

RXDD (Logical port)

L

L

instruction register 1

instruction register 1

L

H

instruction register 2

instruction register 2

H
H

L

instruction register 3

instruction register 3

H

i nstruet i on regi ster 4

instruction register 4

L

L

instruction register 5

instruction register 5

L

H

status register 1

H

L

status register 2

-ICD®@OO--------------3-46

RF5C59

• PACKAGE DIMENSIONS (60 pin FLAT)

24.8 ±O,4
(.976 ±"'")

20.

OTYP

(. 787 TYP )

54

I

35

. .f'
o



PORT

POo-PO,

ALE

<:=:::>
<:=:::>
<:=:::>

CS

WR

ADo-AD,

DATA

0

BUS
BUFFER

*

<:=:::>
<:=:::>

<=>

P1 o-P1,

P2 o-P2,

P3o-P3,

P4o-P4,

P5o-P5,

Addres;ing
AD.

AD,

ADo

select

AD,

L

L

L

PORT 0

H

AD,

ADo

select

L

L

PORT 4

I

L

L

H

PORT 1

H

L

H

PORT 5

L

H

L

PORT 2

H

H

L

-

L

H

H

PORT 3

H

H

H

DDR

• Absolute Maximum Ratings
Symbol

Parameter

Vee

Supply Voltage

VI

Input Voltage

Vo

Output Voltage

Pd

Power Consumption

Topr

Operating Temperature

Tstg

Storage Temperature

Condition

Value

Unit

-0.3-7

V

GND = OV

-0.3 - Vee + 0.3

V

-0.3 - Vee + 0.3

V

200

mW

0-70

°c

-40-125

°c

-IIO©®DO--------------3-50

RF5C60

• DC Electrical Characteristics (Ta=O-70°C, Vcc=5V±10%)
Symbol

MAX.

Unit

V IH

"H" I nput Voltage

2.2

Vcc+0.3

V

V IL

"L" Input Voltage

-0.3

0.8

V

VT+

Input Rise Threshold Voltage

1.3

1.9

2.4

V

VT

Input Fall Threshold Voltage

0.7

1.2

1.7

V

Hysteresis Voltage

0.4

0.5

TV+-VT

Parameter

Condition

V OH

"H" Output Voltage

IOH=-4mA

VOL

"L" Output Voltage

IOL =4mA

MIN.

O;:;V!;:;Vcc

-10

loz

Output Leakage Current (off)

OV~Vo~Vcc

-10

Icco

Power Supply Current (operating)

Icc!

Power Supply Current(standby)

Note1: The values are for CS, ALE, RD, WR and AD, -AD,.

Note
Note 1

Note 2

V
V

2.4

Input Leakage Current

II

TYP.

0.4

V

10

JlA

10

JlA

30

mA

200

JlA

I

Note 2: The values are for RESET and PO, -P5 •.

• AC Electrical Characteristics (Ta=O-70°C, Vcc=5V±10%)
Symbol

Parameter

Condition

MIN,

TYP,

MAX.

Unit

tLL

ALE Pulse Width

80

ns

tAL

Address Setup Time
(to ALE t)

40

ns

tLA

Address Hold Time
(to ALEt)

40

ns

CS Setup Time

(to ALEt)

30

ns

(to ALEt)

40

ns

tSL
t LS

CS Hold Time

t LC

ALE t RD/WR Delay Time

30

ns

tCC!

RD Pulse Width

160

ns

WR Pulse Width

120

ns

tCC2
tCL
tRO
t ROF
tpR
tRP
tow
two

25

RD/WR t-ALEt Delay Time
RD t-Data Output Delay Time

CL=0-150pF

30

RD t-Data Float Delay Time

ns
120
80

ns
ns

Poat Input Setup Time

50

ns

Port Input Hold Time

50

ns

Data I nput Setup Time

100

ns

Data Input Hold Time

30

ns

twp

WR t Port Output Delay Time

300

ns

tFP

WR t Poat Output Mode Delay Time

400

ns

tpF

WR t Poat Input Mode Delay Time

400

ns

CL=150pF

--------------IID©®OO-

RF5C60

• Timing Chart
READ CYCLE

ALE

ADo-AD,

-.!',,

~~

=><

tLL

.:

____~____________~____________________~____-J;('

1.

l!
!i

'•

l

'teL

)>----~~,!
{,>-----<<=
'------·..,'I-.--'l"tR-·O-'--

, --"'"t.-L---i'..;'----------...;
""--";1

cs

I

tLA

=x!
I

tal

I

~,

I

1:,
_---:-_-iI.
tRD
.

r: ;.:_..::tLO!S,--~

_-+-1----><=
I

~!!l',:r---------------------------RD
I~1-o._--=t",LC~_-i1:l'i':::===:;:::====~A'i
I..
r : I
POo-P5.-------------------......
tCCI
X,

'\

x

'!

i'

!

: tp, :

~

t

' '---------

~

WRITE CYCLE

ALE

---r
1

ADo-AD,

;(

~
tLL

:

i'".---:-tL-.------------------"'-------,---:t,..C-L-J!

~~t-.L--..;j+i--------~~'---------~t-DW--------------~!-·----~tW-D-----~

CS==X~·!~!--~X~________*ii·----~x==
[:
~!

I I

!

I

WR

~-~

I,'
fo"_

_ _ _

~

_ _ _ _ _ _ _ _ _ _ _ __

~,
L,',:r twp
-=t: :LC:. . ,.__~:;'r'!..:===:;:::=====~Ii'iI I tFP--i
tee2

II ~tPF

- - - -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

I

X'

-..J'~

_ _ _ _ _ __

-IIO©®OO---------'---------3--:52

EK-013-8811

Sound Generator

Ie

RF5C68A
• GENERAL DESCRIPTION

RFSC68A is a sound generator IC that uses pulse code modulation (PCM). It has a digital control
oscillator (DCa) and digital control amplifier (DCA) built in. You can structure a PCM sound generator system by connecting external waveform data memories (pseudo SRAM, SRAM, or mask ROM)
and D/A converters, controlling them with a microcomputer.

I

• FEATURES

•
•
•
•
•
•
•
•
•
•
•
•

•

•
•
•

PCM sound generation method
Number of channels .................................. 8
Source clock frequency ............................... 10 MHz max.
Sampling frequency .................................. 19.8 kHz (source clock = 7.6 MHz)
Waveform data width ................................. 8 bits
Number of waveform words ........................... Any
Waveform memory space .............................. 64 K-bytes max.
Envelope data width ................................. 8 bits
Left(L) and Right(R) stereo output at arbitrary orientation level
Pitch fine adjustment
Interface with 8-bit CPUs
Interface with waveform memories
Can be directly coupled with two 2S6K (32K X 8) pseudo SRAMs.
Can be directly coupled with two 2S6K (32K X 8) mask ROMs.
Can be directly coupled with two 2S6K (32K X 8) SRAMs.
Interface with D/A converters
Can be directly coupled with lO-bit serial D/A converters.
Can be directly coupled with 8-bit parallel D/A converters.
Silicon gate CMOS process
SV single power supply
Package ...... , .................................... 80-pin flat package.

• APPLICATIONS

Sound generator for personal computers, electronic instruments, TV games, and toys.

-------------ICO©@[J{]3-53

RF5C68A

• PIN CONFIGURATION (Top View)

RAMA7
RAMA6
RAMA5
RAMA4
VCC
XIN
XOUT
GND
RAMA:l
RAMA2
RAMAl
RAMAO
CS8
AI2
All
AIO

DACO
OACl
OAC2
DAC3
SDLH
SDLL
OAC4
DAC5
OAC6
DAC7
SHR
SHL
DO
D1
D2
03

• BLOCK DIAGRAM

..---

'CPU

r:

' ADDRESS

I/F

AO
-AIZ ~

DO
-D7

~I

¢::::::;

INTERNAL
MEMORY
CRAMI

I

I~~I

ADDRESS
POINTER
I

~I

I

L...--

IF

J
-I

I

RAM. ROM

U "--

ir=fSERIAL DAC IfF
I rtSERIAL DAC IfF

~r TIMING CON TROLl

....I\.

-V

~

RAMAO
-RAMA14

RAMADO
-RAMAD7

IWAVE DATA

DCA

'I

II
WRB 0 - - Rf)8
CSB ~

EXTERNAL

m\~IB
0
0
0
0

RAMCIB
RAMC2B
SDRH
SORL
SOLH
SDLL
SHR
SHL

TEST! 0 - - - TEST? 0 - - TEST3 o----r
XIN XOUT

Rt-:SETR

-IID©®[]{]-------------3-54

RF5C68A

• PIN DESCRIPTION
PIN NAME

FUNCTION

DESCRIPTION

I/O

AO-A12

Address input

DO- D17

Data input output

CSB

Ch ip select input

I

RDB

Read enable input

I

Read signals input from a microcomputer

WRB

Write enable input

I

Write signals input from a microcomputer

I
I/O

Address signals input from a microcomputer
Data bus signals between R F5C68A and a microcomputer
Chip select signals input from a microcomputer

When pseudo SRAMs are connected, these are multiplex
signals of lower addresses/data between R F 5C68A and
SRAMs_ When MROMs are connected, these are data
input signals from MROMs_
When SRAMs are connected, these are data bus signals
between RF5C68A and SRAMs_

RAMADO
- RAMAD7

RAM address input output

RAMA8
- RAMA14

RAM address output

0

Higher address signals of SRAM and MROM

RAMAO
- RAMA7

RAM address output

0

Lower address signals of SRAM and MROM
SRAM and MROM select signals of higher 32 K-bytes

I/O

RAMC2B

Memory select output

0

RAMC1B

Memory select output

0

SRAM and MROM select signals of lower 32 K-bytes

RAMWEB

RAM write enable output

0

Write signals of pseudo SRAM and SRAM

RAMOEB

Memory output enable output

0

Read signals of pseudo SRAM, SRAM, and MROM

SDLH

Higher "L" data output

0

Higher "L" data signals output to serial DACs

SDLL

Lower "L" data output

0

Lower "L" data signals output to serial DACs

SDRH

Higher "R" data output

0

Higher "R" data signals output to serial DACs

SDRL

Lower" R" data output

0

Lower "R" data signals output to serial DACs

DACO
-DAC7

Multiplex signal output

0

"R" data/"L" data multiplex signals output to parallel
DACs

SHL

"L" data sample/hold signals output

0

"L" data sample/hold signals of DACO to DAC7

SHR

"R" data sample/hold signals output

0

"R" data sample/hold signals of DACO to DAC7

RESETB

Reset signals input

I

Reset signals

XIN

Crystal signals input

I

XOUT

Crystal signals output

0

External terminal of crystal oscillator
Clock can be directly input to XIN_

TEST 1
TEST 2
TEST 3

Test input pin

I

VCC

Power supply

GND

Ground

-

These are test inputs usually set to logic "L"_
When MROM or SRAM is used for memory, TEST2 is
set to logic "H"_
Power supply terminal
Grounding terminal

--------------IIO©®OO3-55

I

RF5C68A

• APPLICATION EXAMPLE

Digital
Sound
Data

pCOM

RF5C68A

Scanner

Wave Form
Memory
(RAM or
ROM)

DAC

Key
Board

• ABSOLUTE MAXIMUM RATINGS
Symbol

Parameter

Condition

Limit

Vee

Supply voltage

GND = OV

-0.3-7

VTE

Input and Output Voltage

GND =OV

Pd

-0.3 - Vee

Maximum Power consumption

Unit

+ 0.3

V
V

200

mW

°c
°c

Topr

Operating Ambient Temperature

0-70

Tstg

Storage Temperatu re

-40-125

• RECOMMENDED OPERATING CONDITIONS

Symbol

Parameter

Specified Value
Min

Typ.

Max.

Unit

Vee

Supply Voltage

VIH

Input High Voltage

2.2

VIL

Input low Voltage

-0.3

0.8

V

0

70

°c

Ta

Ambient Temperature

4.5

5.5
Vee

+ 0.3

V
V

- .I I D © ( [ ) [ } I J - - - - - - - - - - - - - - 3-56

RF5C68A

• DC CHARACTERISTICS
(Ta = 0 - 70·C, Vee = 5V ± 10%)
Symbol

Parameter

Specified Value

Test Condition
Min.

Typ.

Max.

Unit

Vee + 0.3

V

0.8

V

Vee + 0.3

V

VIH1

Input High Voltage (TTL Compatible)

2.0

VILl

Input Low Voltage (TTL Compatible)

-0.3

VIH2

Input High Voltage (XIN pin)

3.5

VI1.2

Input Low Voltage (XIN pin)

-0.3

1.5

V

ILl

I nput Leakage Current

-10

10

/lA

VOH

Output High Voltage

IOH

VOL

Output Low Voltage

IOL

0.4

V

loz

Output Leakage Current for OFF State

Ov ~ VOlIT ~ Vee

10

/lA

leea

Standby Supply

ice1

Operating Supply Current

Cu~rent

OV~VIN ~Vee

= -4.0 mA
= 4.0 mA

V

2.4

-10

= OV, Vee
fOPR = 10 MHz
VIN

300

/lA

30

mA

• AC CHARACTERISTICS
(Ta = 0 - 70·C, Vee = 5V ± 10%)
Symbol

Parameter

Specified Value

Test Condition
Min.

fOPR

Input Clock Frequency

TCE

RAMCE 1, 2 Pulse Width

TAS

Address to RAMCE 1, 2

TRAH

RAMCE 1, 2 to Row Address

TOHC

RAMCE 1,2 to RAMOEB

TOEA

RAMOEB to Read Data Valid

TOHZ

RAMOEB to Read Data Float

Typ.

Max.
10

200

Unit
MHz
ns

0

ns

30

ns
ns

0
50

ns

20

ns

TQIV

RAMCE 1, 2 to RAMWEB High

200

ns

Twp

RAMWEB Pulse Width

35

ns

Tow

Write·Data Valid to RAMWEB High

30

ns

TDH

Write-Data Hold after RAMWEB High

TRDA

Read·Data Valid to ROB High

TRD-l

Read-Data Hold after ROB High

10

ns

TWRH

Write-Data Valid to WRB High

30

ns

TWRH

Write-Data Hold after WRD High

30

ns

ns

0
100

ns

---------------ltD©®OO3-57

I

RF5C68A

• TIMING CHART
1. Psendo SRAM Interface

* Read Cycle
tn:

RAMClB
RAMC2B

RAMADO-7
(AO-7)

VALID

RAMA8-14
RAM WEB
tow

tOEA

RAMOEB

RAMADO-7
(D0-7)

* Write Cycle
tn:

RAMCIB
RAMC2B

RAMADO-7
(AO-7)

RAMA8-14

VALID

RAMWEB

RAMOEB

RAMADO-7
(D0-7)

-ICD©®OO-------------3-58

RF5C68A

2. Mask ROM Interface

* Read Cycle
RAMClB
RAMC2B

RAMADO-7

RAMA8-14
RAMOEB

I

RAMADO-7
(00-7)

3. CPU In terface

* Read Cycle
CSB

AO-12

-;tt-VALlD------.~r----

WRB

~:j

RDB

DO-7

________________

~~ V~~-t-RIl-H--------------

* Write Cycle
CSB

~
AO-12

f\

)

VALID
twp

}

WRB
tel'
RDB

DO-7

0

~r
VALID

/I

--------------ltO©®OD3-59

RF5C68A

• FUNCTIONS

1. PCM Sound Generation
Waveform data (WAVE DATA) is specified by the internal address pointer of RFSC68A, and is
read from external waveform memories. RFSC68A multiplies it with envelope data (ENV DATA) or
stereo pan pot data (PAN DATA) that are stored in the internal memory (RAM). The operation above
is performed for each of the eight channels. RFSC68A outputs the total of the results as single-sample
PCM sound data.(digital data).
RFSC68A performs the operation even to the channel that is not sounding. Therefore, one sampling
requires a fixed time (one cycle of source clock X 384).
However, the operation result of the channel that is not sounding does not affect the output PCM
sound data.
The digital control amplifier (DCA) block, which executes the above processing, is described below.
[DCA block]
The digital control amplifier block generates musical tones using the data read from internal and

external memories.
The figure below shows how each type of data is processed.
The above processing is performed sequentially for each of the channels I to 8. Every time the R
and L outputs of the eight channels are totaled, sample/hold signals for Rand L are generated.
If there is a plus side overflow while totaling the values of the eight channels, the limiter circuit
sets FFFFH as the result. If there is a minus side overflow, the limiter sets OOOOH as the result.

I

I

ENVDATA

ADD/SUB CONTROL

T L LorR OUTPUT FROM 0 TO X cu.
15 14 13 12 II 10 9 8 7 6 5 4 3 2

I

0

""'~"': ............... '

TO SERIAL DAC I/F & OUTPUT PIN (DACH)

-ICD©®OO-------------3-60

RF5C68A

[Example of waveform data format]

The figure below shows an example format of waveform data to be stored in an external waveform
memory. In this example, digital sampling is performed assuming that the values of the analog waveform are 127 at the center, 253 at maximum, and 0 at minimum.
The 'FFH' waveform data is handled as loop stop data (therefore, 'FFH' cannot be used as waveform data). If 'FFH' data is read from the waveform memory, the waveform memory read address is
reset to the LSH and LSL data (see 2. Wave Form Memory Read), and waveform data is read again.

SAMPLING TIME

ml::::::::::::::~~

I

.;)

:~
...
[~ jHc<>~NA= WAVE
123

···:··;··f·······;·· ;··~·······H·~

1iHtjTt,

I
I

~

SHL

___--lnl.-___
I

SHR

"L" Data Output

I

~

X,------,'fJJb.

DACO-7

: "R" Data Output
I

~NLHX2¢1--~·~1

'r---------------~

------i~

SDLH
SDLL

,r-------- HiZ

"H"or',!:'

HiZ

i,H"""

,J

t;==NRH X 2¢1==:j

---------«

SDRH
SDRL

)r-----

"War''!:'

"H" o_r''!:'_-----',t - - I

('---._ _
1

HiZ
HiZ

-~---NRLX2¢1---"""'-·

f-o.

However, NLH, NLL, NRH, and NRL are the number of bits of the absolute value of the difference
of the previous sound data. If it is larger than the previous data, the output value is "H", and if it is
smaller, the ou tpu t value is "L"
[Example]

a9
- b9

as
bs

a7
b7

a6
b6

as
bs

C9

Cs

C7

C6

Cs
I

NLHorNRH

a4
b4

a3
b3

a2
b2

ao
bo

<-

b,

Previous sound data
(10 bits)

C4

C3

C2

C,

Co

<-

Absolute value of the sound
data difference

,

a,

NLL or NRL

-------------IID®®OO3-69

RF5C68A

• PACKAGE DIMENSION

O.80±O.15

25.6±O.4

J

61111111111111111111111111111111111111111111111&

Unit: mm

-IIO©®o{]-------------3-70

©! ! ! ! ! ! ! !®! ! ! ! ! ! ! !O ! ! ! ! ! ! ! !~I

EK-019-8811

PWM GENERATOR

!!!!!!!!!!!!!!!IC!!!!!!!!!!!!!!!D

RF5C86
Ricoh's RF5C86 is an integrated circuit (IC) for generating pulse width modulation (PWM) signals.
It has eight output channels. The pulse cycle, pulse high width, and output mode can be set. The
RF5C86 is ideal for servo control of motor lamps and actuators. If the multiplier (MPL) mode is set,
it operates as an analog multiplier, so it can be used as four electronic volumes .
• FEATURES

• Three types of mode for various purposes (modes may also be mixed)
PWM mode: The period value can be set for every two channels. It can be used as a PWM generator
for up to eight channels.
The pulse high width can be set for all eight channels.
One-shot mode: Outputs a one-shot pulse using an external TRG signal.
MPL mode: Can be used as an analog multiplier and as up to four electronic volumes.
• Built-in prescaler: One of fCLK/2, fCLK/8, fCLK/32, or fCLK/128 can be chosen for each channel
(fCLK = 16 MHz maximum).
• The external trigger can be selected (common in all channels).
• The output polarity can be selected (PWM mode only).
• The register values can be changed after completion of the current cycle.
• Direct link to CPU bus
• 5 V single power supply
• CMOS process
• 28-pin SOP package
• BLOCK DIAGRAM
rRG

WR C/D cs

CLK

RESVee GND-

I---;r----~l----

,

~i

,
"

'

"

,

'

'I

i

'I

'

~I

;:

-~

~'

~,

!

I'

~,~~H'EG'~A
TE

!

@i~CO~M~P~A~RE====:C~OM~P~A~R~E~

Lr~-T-T~-~-~m~.'
PWM3B PWM3A

PWM2B

PWM3B

PWMIB

PWMIA

PWMOB

PWMOA

--------------IID©®OO3-71

I

RF5C86
• PIN CONFIGURATION

CLK
PWMOB
PWMOA
NC
PWMIB
PWMIA
PWM2B
PWM2A
PWM3B
PWM3A
TRG
WR
CS
GND

28
27
26
25
24
23
22
21
20
19
18
17
16
15

2
3
4
5
6
7
8
9
10
11
12
13
14

Vcc
DO
Dl
D2
D3
D4
D5
D6
D7
NC
NC
C(fj
RES
NC

• PIN DESCRIPTION

Pin No.

Name

Function

I/O

1

CLK

I

2

PWMOB

I/O

3

PWMOA

0

4

NC

No connection

5

PWMIB

PWM mode: PWM signal output, MPL'mode: Vref input

6

PWMIA

0

7

PWM2B

I/O

I/O

8

PWM2A

0

9

PWM3B

I/O

10

PWM3A

Clock input
PWM mode: PWMsignaloutput, MJ>L mode: Vref input
PWM signal output

PWM signal output
PWM mode: PWM signal output, MPL mode: Vref input
PWM signal output
PWM mode: PWM signal output, MPL mode: Vref input
PWM signal output

11

TRG

0
I

12

WR

I

Write signal input

13

CS

I

Chip select signal input

External trigger input, active high edge

14

GND

Ground

15

NC

No connection

16

RES

I

17

C/D
NC

I

18
19

NC

20 - 27
28

DO~D7

Vcc

Internal register or counter reset signal input
Selection of command input/data input
No connection
No connection

I

Data input
Power supply

-ICO©®OO-------------3-72

RF5C86
• ABSOLUTE MAXIMUM RATINGS
Symbol
Vcc

Parameter

Condition

Supply Voltage

Limit

Unit

-0.5-+7.0

V

VI

Input Voltage

-O.5-Vcc+O.3

V

Vo

Output Voltage

-0.5-Vcc+0.3

V

0-70

°c
°c

Topr

Operating Ambient Temperature

Tstg

Storage Temperature

• DC CHARACTERISTICS (Ta

-40-125

= 0-70°C,

Vee

= SV±10%)
Specified Value

Symbol

Condition

Parameter

Unit
MIN

Vrn

Input High Voltage

2.2

VIL

Input Low Voltage

-0.5

VOH

Output High Voltage

IOH =-4mA

VOL

Output Low Voltage

IOL = 4mA

TYP

MAX
Vcc+O.3

V

0.8

V

2.4

V
0.4

V

-10

10

J.l.A

-300

10

J.l.A

30

rnA

10

J.l.A

VI =0, Vcc
CLK, cr, WR, C/D, GATE

ILl
Input Leakage Current

Data bus

ILl(l)

RESET VI =0

lee 1

16 MHz Operations

Ice2

Supply Current

Input: 0 or Vce
Output : OPEN

RON

Input Resistance

VAl

Input Analog Voltage

VAO

Output Analog Voltage'

Analog Switch
2.0
VAI-

100

n

Vcc+O.3

V

VAO+

V

Note: Input Pull-Up Pin

• TERMINAL CAPACITANCE (Ta

= 2SoC,

Vee

= OV)
Specified Value

Symbol

Parameter

Unit

Condition
MIN

CI

Input Capacitance

Co

Output Capacitance

TYP

MAX

feLK = 1 MHz

10

pF

oV except at pins to be measured

20

pF

--------------ltO©®[J{]3-73

I

RFSC86
• AC CHARACTERISTICS (Ta

= 0-70°C,

Vee = SV±lO%)

~>O~WW~QQQQQ

DDI4
DDI5
DDllO
DDIII
DDII2
DDII3
DDII4
DDII5
VDD
Vss

DEIO
DEI I
DEI2
DEI3
DEI4
DEI5
DElla
DEllI
DEII2
DEII3

~~

70

60

65

55

50

85

45

90
40

-qr

95

25

....

30

DBllO
DBI5
DBI4
DBI3
DBI2
DBII
DBIO
eLK
VnD
Vss

DAll5
DAII4
DAII3
DAII2
DAIII
DAlIa
DAI5
DAI4
DAI3
DAI2

~Ow __
~~
wO
~«
QQ
~QQ
'-.:t< U? 0

-ICO®®[}[]--------------3-88

5C67
• Pin Description

Pin name

I/O

VDO
VSS

-

ClK

I

Element clock. Element data is input, processed and output in
synchronization with the rising edge of this clock.

OAIO- 5

I

Element data input of the first line

0810- 5

I

Element data input of the second line

OCIO- 5

I

Element data input of the third line

0010- 5

I

Element data input of the fourth line

OEIO- 5

I

Element data input of the fifth line

OAIIO- 5

I

Element data input of the first line

08110- 5

I

Element data input of the second line

OCIIO- 5

I

Element data input of the third line

Description
Power supply
Power supply

00110- 5

I

Element data input of the fourth line

OEIIO- 5

I

Element data input of the fifth line

00-5

0

Element output data

00-7

I

Data input to internal coefficient register

WR

I

Write pulse input to internal coefficient register

AO-4

I

Select signal input of internal coefficient register

FA

I

Format adjustment input
"H"; Negative values become absolute.
"L" : Negative values are rounded to O.

CS

I

Chip select input in host interfacing

OE

I

Element output enable
"Hit : 0000 to 5 and OOEO to 5, SGN, and OVR become high
impedance.

SGN

0

Outputs the sign before format adjustment.
"H" : Negative value
"L": Positive value

OVR

0

"H":

SPMS

I

Select signal of serial and odd-even mode
SPMS = "H": serial mode
SPMS = "l"; odd-even mode

-

-

Overflow or underflow in format adjustment

--------------IID©®OO3-89

I

se67
OEMS

I

In odd-even mode
Selects odd or even output.
In odd output (OEMS = "L"I
Odd data is input to DAI to DEI and even data is input to DAII
to DElI.
In even output (OEMS = "H"I
Even data is input to DAI to DEI and odd data is input to DAII
to DEli.

SET

I

Reset signal of multiplication coefficient
Setting this signal L makes
W33= 1, Wll =W12=W13= ..... =W55=Q
Division coefficient 1 is set, and data before processing can be
output.

TIN

I

Test terminal

TOUT

0

Test terminal

TESTl

I

Test terminal

TEST2

I

Test terminal

--

-IIO©®OO------------,-----3-90

5C67
• Block Diagram

SPMS
OEMS
DAI

O~5

DAlIO~5
DO~D7

OIA

:6,
:6,
8

OIB
eIN

W

SPMS

LINE/
ADD

OEMS

(8)

SPMS
OEMS

I-

DOUT

~

--!-' WR1.2.3
3

DBI

O~5

DBlIO~5

1

6
6

OIA

r--

:;
3

DC I

O~5

DClIO~5

6
6

r-

-

~

6

~~:

LIN E/
WRl.23 ADD

OIA
OIB

eIN
WRL 2.3

OJ)

OIA
OIB

6

(C)

LINE/
ADD

r-- r - eIN

~

6

LINE/
ADD

4

~ OB

SUM

DIV

OA

--

oe
00

r - OE

01

'-SUM

f-------

WR

SUM

FA,OE

-!-.o

OO~05

---r-" SGN,OVR
~

FA,OE

SPMS_
OEMS
DOUT

SPMS
OEMS
DOUT

r-

WR1.2.3

OIA
DIB

(E)

6 ~r-eIN LINE/

A OWI{

00lY[

~Ir~'"

SPMS
OEMS
OOUT-

ADD

16

CS

SET
CLK

0---0----

• Description of Block

• LINE ADD
Multiplies and adds five data items (A to E) in the main scanning direction and the preset
filter coefficient for each line,

• SUM
Adds the results of LINE ADD operation of all main scanning lines, Operation results are
expressed by 13-bit integer two's compliment.
• DIV/FA
Divides the final results of the addition, and rounds down the results.

----'------------------IIO©®OO3-91

I

5C67
• Absolute Maximum Ratings

Symbol

Parameter

Condition

Ratings

Unit

VCC

Supply Voltage

GND=OV

-0.3 - 7

V

VTE

Terminal Voltage

GND=OV

-0.3 - VCC +0.3

V

Pd

Power Consumption

700

mW

Topr

Operating Ambient
Temperature

0-70

°C

Tstg

Storage Temperature

-40 -

125

°C

• DC Electrical Characteristics

(Ta=O-70°C, VCC=5V±10%)
Symbol

Parameter

VIH

"H" Input Voltage

VIL

"L" Input Voltage

III

Input Leakage Current

VOH

"H" Output Voltage

VOL

"L" Output Voltage

ICC

Supply Voltage Current
(Operating)

Condition

MIN.

MAX.

Unit

2.2

VCC
+0.3

V

-0.3

0.8

V

±10

p.A

OsVlsVCC
IOH= -4.0 mA
IOL=4.0 mA

TYP.

2.4

Note

V
0.4

V

100

mA

Notel

Note 1: When the carriers of all multipliers are propagated from the lowest bit to the highest bit.

-ICD®®[J{]-------------3-92

5C67
• AC Electrical Characteristics

Symbol

Item

MIN.

MAX.

Unit

50

-

ns

30

-

ns

-

ns

ticyc

Clock cycle

tist

Element input set-up time

tiHD

Element input hold time

5

tiPD

Element output pipeline delay time (odd-even)
(serial)

tiCD

Delay time from element output and SGN and
OVR clocks

tFST

Format adjustment set-up time

tODD

Disable time of element output from OE and SGN
and OVR outputs

30

ns

1DED

Enable time of element output from OE and SGN
and OVR outputs

30

ns

tDST

Coefficient data input set-up time

30

ns

tDHD

Coefficient data input hold time

10

ns

tWP

Write pulse width

40

ns

tWO

Set-up time for -A signal (to RW)

30

ns

tWR

Hold time for -A signal (to RW)

30

ns

tFMD

Format adjustment hold time

40

ns

650
700

ns

30
40

ns
ns

---------------IIO®®OO3-93

I

5C67
• Timing Chart
ticyc

tIPD

CLK

DXO
DXE
X:A~E

( input data )

OE

I-----f.~

tIIID

--------+---f-i-

FA

_I
Ao~,

V--

I

1-

-!
CS

/

\

'

,
I

WR
tWD

i

tWP

tWRi

T

I

~
,tDSTtDHD

I

II

-IID©®[]{]--------------3-94

5C67
• Operation

1. Flat surface filtering

1

2

4

3

1

Dl1

D ••

2

D ••

D ••

3

D ••

D ••

4

D41

D ...

5

Ds.

D sa

D ••

D'4

5

6

D. s

n

Da (n-.) Dan
D. (n-.) D.n

D ••

Fig-1

Flat Surface Element Data

W••

W ••

W ••

W ...

W. s

W ••

Waa

Wo•

Wa ..

Was

W ••

W. a

W ••

W ...

W. s

W ...

W ...

W ...

W ...

W .. s

W s•

Ws •

W s•

Ws ..

Wss

Fig-2

D ..

n-l

D. (n-.) D.n

Filter Coefficient

When performing flat surface filtering on element data as shown in Fig-1 with filter coefficients
as shown in Fig-2, the operation results of element data 033 is as follows:
F (033)

=

5

5

E (E Wij Dij)
i= 1 j= 1

The RF5C67 IC performs the above flat surface filtering on consecutive input elements.
The coefficients are as follows:
Wi5

±Wil
±Wi2

0= 1-5)

2. Data input
The RF5C67 IC has two modes of element data input:
1) serial mode and
2) odd-even mode.

--------------IID@®OO3-95

I

5C67
1 ) Serial mode
When flat-surface element data in Fig-1 is input as in Fig-3:

CLK

Fig-3

Data Input in Serial mode

The RF5C67 outputs results of processing accordingly, as shown in Fig-4.
Data in the first line is input simultaneously to DAI and DAII.
Data in the second to fifth lines are also input to I and II.

DAI
DAII

CLK

D32 ,D 31 ,D z n'" D23,D22,D21
X,X,F(D 33 ),FCD,,) "'F(D 3n -,)XX
X,X,F(D,,), F(D.. )

t=DAI
DAII

Fig-4

SPMS

(X.... Undefined)

Flow of Data Processing in Serial Mode

-ICO©®OlJ-------------3-96

5C67
2) Odd-even mode
When the flat-surface element data in Fig-1 is input as in Fig-5:

eLK

I

Fig-5

Data Input in Odd-even mode

Two RF5C67 are required for flat-surface filtering. as shown in Fig-6. The odd data in
the first line is input to DAI of the RF5C67 in odd mode and to DAII of the other RF5C67
in even mode. Even data is input to both DAII and DAI. Data in the second to fifth lines
is also treated in the same way.

--------------ICO©®OO3-97

5C67

DAI

D2I Din-I··· D 13 D"
D.. Din ... D 14 D"
D3I D'n-I···D '3 D2I
D" D'n ... D .. D"
D.. D3n- I ···D 33 D31
Il.. D3n ... D.. D"
DSI D.n-I ... D 43 D ..
Ds, D'n ···D .. D..
DSI D'n-I···D 53 D5l
Ds, Dsn ... D
" D"

II

DBI

n

5C67(0)
Odd mode

DCI

0

0 --.1

II

X,I« D 33 ), F(D,,), F(D,,)
F(D .,), F(D .. )

DDI
II

DEI

SPMS 1Ir
OEMS ---..,.

II

DAI
II

-

DBI

L---

5C67(E)
Even mode

II

DCI
~

00-5

II

X,F (D .. ) , F(D 3s ), F(D,,) .. .
F( D .. ) , F(D .. ), F(D.. ) .. .

DDI
II

Fig-6

DEI

SPMS

II

OEMS

r~

Flow of Data Processing in Odd-even mode

The processing results of elements Di2m-1, DI2m (m is integer) are output simultaneously
from the RF5C67 (0) and the RF5C67 (E).
1) and 2) modes are switched at the SPMS (serial/parallel mode select) and the OEMS
(odd-even mode select) terminals. (See Table-1.)

SPMS

OEMS

L

L

Odd-even mode, odd data output

L

H

Odd-even mode, even data output

H

X

Serial mode

Mode of RF5C67

Table c 1

Mode Switching of RF5C67

-IIO©®[}{]-------------3-98

5C67

3. LINE ADD
This section explains the flow of signals in the LINE ADD block shown in Block Diagram.
1) Serial mode
Fig-7 shows the flow of signals in LINE ADD when using the RF5C67 in serial mode.

DIA

I

Fig-7

Flow of Signals in Serial mode

As shown in the figure, data items are input from DIA in the order: Di" Di2, Di3, ... ,
and are multiplied by Wi', Wi2, and Wb. The results of multiplication is delayed by an
appropriate clock in the delay unit, then added or subtracted.
F (Din) = Wi' • Din+2 +Wi2 • Din+' + Wi3 • Din
±Wi2· Din-' ±Wi' • Din-2
Dou, outputs the following as a result:
Determine the sign (+ or -) by writing it from the CPU to a register simultaneously with
the coefficient of multiplier, as described later.
2) Odd-even mode

Fig-8 shows the folow of signals in LINE ADD in odd-even mode.

--------------ICD©®OO3-99

5C67

DI A - - - . - - - l
DOUT

selectior

DIB----~ 1 ~ 1+
~
Fig-8

z

Flow of Signals in Odd-even Mode

The flows of signals are a little different in odd mode (odd data output) and even mode
(even data output). Table-2 shows the relationship of data I/O in each mode.
Odd mode

Even mode

OIA

Oil, 013, 015, ... , 012n-l,

012, 014, 016, ... , 012n, ...

OIB

012, 014, Ole, ... , 012n, ...

011, 013, 015, ... , 012n-1, ...

OOUT

F (013). F (015), F (02n-1)

F (04), F (Oe), ... F (012n) ...

Table-2
At the selector, 0 is selected in odd mode and E is selected in even mode.
In odd mode, the processing result of odd data is output as follows:
F (012n-1)

=

WI1 • 012n+1

+

WI2 • 012n

+

WI3 • 012n-1

± WI2 • 012n-2 ± Wil • 012n-3
At the same time, in even mode, the processing result of even data is output as follows:
F (012n) = Wil • 012n+2

+

W12. 011n+1

+

WI3 • 013n

± WI2 • 012n-1 ±WiI • 012n-2
As seen in the comparison .of Fig-7 and Fig-8, the multipliers, which multiply the filter
coefficients Wil and W12, are different. in 1) serial mode and 2) odd-even mode.

-ltD@®OO-------------3-100

5C67
As described later, when setting filter coefficients from the CPU,
written to different addresses in different modes.

Wi1

and

Wi2

must be

4. DEV/FA
a) Division circuit
The RF5C67 performs division using a shifter and addition/subtraction unit. Fig-9 shows
the circuit diagram of the part of DIV/FA that performs division.

DIN
13

I

SHFI

SW1--*==~

SI SO

J.=~~~-~-~-----PMl

P12

P2PO

ADD/Reg (1)
(B)

em
MSB

13

SHF2

SW2

PM2

Fig-9

Division Circuit

--------------.,----IIO@®UO3-101

5e67
shift (1 ), shift (2)
shift (3)
ADD/Reg
SW1, SW2
PM1, PM2
SHF1, SHF2, SHF3:

Arbitrary 0- to 4-bit shift to right
Arbitrary 0- to 5-bit shift to right
13-bit adder + register
Selects whether to enter data or 0 in one input of the adder.
Selects whether to add or subtract the other input of the adder.
Determines the shift length of shifts (1), (2), and (3).

b) Principle of division
Input (DIN)
Length of shift (1)
Length of shift (2)
Length of shift (3)

X
p
q

When SW1 =SW= 1 and PM1 =PM2=0, the values output to (A), (B), (e), (D), and (E)
in Fig-1 are as follows:
(A)

=

2- P

•

X

(B)

=X +

(e)

= 2-(P+Q) • X

2 -p

•

X

+ 2- P • X + 2-(P+Q) • X
(E) ,;" 2- r • X + 2-(P+r) • X + 2-(P+Q+r) • X
(D) = X

For example, to calculate 1/25X,
1/25 = 0.04 -5
=. 1 x 2

-7

+ 1x2

+ 1

X

2- 10 (=0.040039)

Therefore, the following values calculate 1/25X:
r=5, p=2, q=3
1/15 = 0.06666

=.

1 x 2

-4

+ 1x 2

Therefore, the following
O-bit shift of shift (1)
4-bit shift of shift (2)
4-bit shift of shift (3)

-8

(=0.06640)

values calculate 1/15X:
(p=O), SW1 =0
(q = 4), SW1 = 1
(r = 4)

-ICO©@OO--------------3-102

5C67
Then obtain 1/9:
1/9 = 0.1111
-4
'" 1 x 2
+

x 2

-5

+ 1 x 2

-6

+ 1x 2

-9

( = O. 11132)

3-bit shift of shift (1) (p = 3)
PM 1 = 1 (subtraction)
SWl = 1
Then,
-3
-1
-2
-3
(C) = X - 2
X
2
oX+2
oX+2
oX
0

3-bit shift of shift (2) (q = 3)
PM2 = 0 (addition)
SWl = 1
3-bit shift of shift (3) (r = 3)
Then,
-3
-1
-2
(E)
2
(2
0
X + 2
2 -4
'" 1/9

0

X + 2- 5

0

0

X + 2

X + 2- 6

-3
0

X + 2

X + 2- 9

0

0

I

-6
0

X)

X

X

0

For 1/2n, n is changed by operation of SHF1, SHF2, and SHF3, within O;an;a 11 (see Table-3).

p(SHFl)

PM1

SW1

q(SHF2)

PM2

SW2

Approximation

r(SHF3)

1125' X

2

0

1

3

0

1

5

(2- 5 + 2- 7 +2-10 )

1115' X

0
1

0
1

4

0

1

4

(2- 4 +2- 0

119 'X

0
3

3

1

3

(2- +2- +2- 6 +2-'). X

X

0

0

0

0

0
0

0

0
1

2- 1

112 'X

0

0
Table-3

0

0

0

0

4

).

•

X

X

5

X
•

X

Division Coefficient and Its Input Setting

c) Operation deviation
In performing divisions using the circuit in Fig-9, errors occur due to following two
reasons:

--------------ICO©®DO3-103

5C67

1. Errors due to expressing divisions in the approximation.
2. Errors due to truncating the lower bits of data in shifts (1), (2). and (3).
Table-4, -5, and -6 show the errors in executing divisions of 1/25, 1/15, and 1/9.

Quotient

Division

,

,
!

CD 51/25
® 76/25

Maximum error
,

I

I

!

!

2

1

3

0

,

,

,

I

I

I

!

!

!

-

75/25
99/25

The following is an explanation of Table-4, -5, and -6 with the above example:

CD

The result of divisions from 51/25 to 75/25 is always 2. At that time, 75/25 = 3 actually,
so the maximum error in this operation is 1.

®

The result of divisions from 76/25 to 99/25 is always 3. At that time, 99/25 = 3.96
actually, so the maximum error in this operation is 0 considering the divisions that cuts
off the values after the decimal point.

-ICD©®[}{]--------------3-104

5e67

Division
0/25
25/25
26/25
50/25
51125
75/25
76/25
99/25
100/25
125/25
126/25
150/25
175/25
151125
176/25
199/25
200/25
224/25
225/25
250/25
275/25
251125
299/25
276/25
300/25
324/25
325/25
350/25
375/25
351125
376/25
399/25
400/25
424/25
425/25
499/25
450/25
475/25
476/25
499/25
500/25
524/25
525/25
549/25
550/25
575/25
576/25
599/25
600/25
624/25
625/25
649/25
650/25
674/25
675/25
699/25
700/25
724125
725/25
749/25
750/25
774125
775/25
799/25
800/25
824/25
825/25
849/25
850/25
874/25
875/25
899/25
900/25
924/25
925/25
949/25
950/25
974/25
975/25
999/25
1000/25 ~ 1023/25
1024/25 ~ 1049/25
1050/25 ~ 1074/25
1075/25 - 1099/25
1100/25 - 1123/25
1124/25 - 1149125
1150/25 - 1174/25
1175/25 ~ 1199/25
1200/25 - 1223/25
1224/25 - 1248/25
1249/25 - 1274/25
1275/25 - 1299/25
1300/25 ~ 1323/25
1324/25 - 1348/25
1349/25 - 1374/25
1375/25 - 1399/25
1400/25 - 1423/25
1424/25 - 1448/25
1449/25 - 1473/25
1474/25 - 1499/25
1500/25 ~ 1523/25
1524/25 - 1548/25
1549/25 ~ 1573/25
1574/25 - 1599/25

Quotient

Maximum error

0

1
1
1
1

1

2
3
4

0

9

0
0

5
6
7
8

10
11

12
1:1
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63

1
1
]

1
1

0
0

1
1

0
0
0

1

0
0
0

1

0

0

0
0
0
0
0
0
0
0
0
0
0

0

0
0
0

- 1

0
0
0

-1

0
0

0

-1
- 1

0
0

-1
-1

0
0

- 1
-1
-1

0

-1
-1

- 1

Table-4 Errors in 1125 Operation

ICO©®OO3-105

I

5e67
Division
0115
16115
31115
46/15
61/15

76/15

91115
106115
121115

136/15

151115
166115
181115
196/15
211115
226/15
241115
256/15

272115

287115
302115
317/15

332115

347/15

362115
377/15

392115
407/15

422115

437115

452115
467115
482115
497115

512115
528/15
543/15

558/15
573/15

588/15
603/15

15115
30115
45115
60/15

75/15

90115
105/15

120/15

135/15

150/15
165/15
180/15

195115
210/15
225115

240/15

255115
271115
286/15
301115
316115
331115
346/15
361/15
376115
391115
406115
421115

436/15

451115
466/15
481115

496/15

511115
527/15

542115

557115
572/15
587115
602115

618/15

617/15
632115

648/15
663/15
678115

662115
677/15

633/15
693/15

708115
723115

738/15
753115

768/15
784/15
799/15

814115
829/15

844/15
859/15
874/15
889/15

904115

919/15
949/15

934115

647115
692/15
707115
722/15
737115
752/15
767115

783/15
798/15
813/15
828/15
843/15
858/15
873/15
888/15
903115
918115
933/15
948115

963/15

Quotient

Maximum error

0

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63

Table-5 Errors in 1115 Operation

-IID©®1Xl
3-106

5e67
Division

o /9

9 /9
18 /9
27 /9
36 /9
45 /9
54 /9
63 /9
71 /9
81 /9
90 /9
99 /9
108 /9
117 /9
126 /9
134 /9
143 /9
153 /9
162 /9
171 /9
180 /9
189 /9
197 /9
206 /9
215 /9
225 /9
234 /9
243 /9
252 /9
260 /9
269 /9
278 /9
287 /9
297 /9
306 /9
315 /9
323 /9
332 /9
341 /9
350 /9
359 /9
369 /9
378 /9
386 /9
395 /9
404 /9
413 /9
422 /9
431 /9
441 /9
449 /9
458 /9
467 /9
476 /9
485 /9
494 /9
503 /9
512 /9
521 /9
530 /9
539 /9
548 /9
557 /9
566 /9

Quotient

Maximum error

0

0
0
0
0
0
0
0
0

8/9
1719
26/9
35/9
44/9
53/9
62/9
70/9
80/9
89/9
98/9
10719
116/9
125/9
133/9
142/9
152/9
161/9
170/9
179/9
188/9
196/9
205/9
214/9
224/9
233/9
242/9
251/9
259/9
268/9
277/9
286/9
296/9
305/9
314/9
322/9
331/9
340/9
349/9
358/9
368/9
377/9
385/9
394/9
403/9
412/9
421/9
430/9
440/9
448/9
45719
466/9
475/9
484/9
493/9
502/9
511/9
520/9
529/9
538/9
54719
,556/9
565/9
574/9

1

2

3

4
5
6
7
8
9

10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63

-1

0
0
0
0
0
0
- 1
- 1

0
0
0
0

a
-1
- 1
- 1
0

a
0

0

- 1
- 1
- 1
- 1

--

0
0
0

1
1
1
1
1

0
0
- 1

- 1
-1
- 1
- 1

- 1
0

- 1

- 1

- 1
-1
-1

-l
-l
- 1

-1
-1
-1
-1
-1

- 1

Table-6 Errors in 1/9 Division

IID©®[}{]3-107

I

SC67
d) FA (Format Adjust)
The result output of shifter (3) is finally made into a 6-bit absolute integral value. Two
ways are available for handling negative values:
When FA=1
The negative value is converted into a positive value with the same absolute value.
Then, values not smaller than 64 are rounded down to 63.
When FA=O
Negative values are rounded to O. Values not smaller than 64 are rounded down to 63.

S. Coefficient Input
a) Coefficient address
When performing space filtering with the RFSC67 IC, the filter coefficient and division
coefficient must be prespecified. Select a corresponding register at AO to A4 terminals,
and write 8-bit data with CS and WR signals. Table-7 shows AO to A4 signals and registers
to be selected. As described earlier, the addresses to select filter coefficients Wi1 and Wi2
are different in serial mode and in odd-even mode.

A

4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

3

1

2

0

0

0

0
0
0
0
0
0
0
1
1
1
1
1
1
1

0
0
0
1
1
1
1

0
1
1
0
0
1
1
0

0
0
0
0
1
1
1

0
1
1
0
0
1

0
0
1
0
1
0
1
0
1

Odd-

Ser-

even

ial

mode mode

4

3

2

1

W..

W.z

1

W..
W,.

W••

1

W••

1

0
0
0

0
0
0

0
0
1

Wz•

Wzz

W..

W..

W..
W..

W..

W.z

W. z
W••

0
1

W••

W••

W••

W. z

0
1
0
1
0

W. z W••
W••
Ws•

0
0
1
0

LATCH!
LATCH2
LATCH3

W ••
Wsz

Wsz

Ws•

Ws •

Ws •

Filter coefficient
Table-7

A

Division coefficient

AO to A4 Signals and Selected Coefficient

-ICD®®o{]--------------3-108

5C67

b) Coefficient format
The coefficient to be specified consists of eight bits. The filter and division coefficients
are different.
1) Filter coefficient

A filter coefficient consists of the following eight bits:

Y:

7-bit integral two's compliment of Wi1, WI2, and Wi3
Expression
06 indicates the sign bit.
DO indicates LSB.

PM:

Indicates whether the sign of Wi5 and Wi4 is reversed for Wi1 and Wi2.
When PM=O, Wi5=Wil and Wi4=Wi2
When PM= 1, Wi5= -Wi1 and Wi4= -Wi2
With Wi3, PM is ignored.

---------------ltD©®[]{]3-109

I

5C67
2) Division coefficient
Setting division coefficients
Select a coefficient register (LATCH 1, 2, and 3) by AO to A4, and write a specific value
to each.
The formats of LATCH 1, 2, and 3 are as follows:

LATCHl
07

I

X

6

5

4

IPM1ISWli

:

p

:

q

LATCH2

I X IPM21SW21
LATCH3

I

X

: X

I

:

++ :
++ :
++ :
3

:r

2

1

0

I

I

I

As shown in Section 4 b). PM1, SW1, p, PM2, SW2, q, and r indicate sign control,

o selection, and shift length.

_. ICO®®OO------~------3-110

5C67
The relationship between the shift length of the shifters and the register coefficient is
as follows:
4

05

3

1

2

0

I0

0

I

0

I

0

I

0

I

1

I

o bit shift

I0

0

I

0

I

0

I

1

I

0

I

1 bit shift

I0

0

I

0

I

1

I

0

I

0

I

2 bit shift

I0

0

I

1

I

0

I

0

I

0

I

3 bit shift

I0

1

I

0

I

0

I

0

I

0

I

4 bit shift

I1

0

I

0

I

0

I

0

I

0

I

5 bit shift

I

The division coefficient is as shown in Table-3.
Table-8 shows the data input to LATCH1 (address 10), LATCH2 (11), and LATCH3
(12) to calculate 1/25, 1/15, 1/9, 1/3, and 1/8.
Division
coefficient
1/25

1/15

1/9

1/3

1/8

Address
1 0
1 1
1 2
1 0
1 1
1 2
10
1 1
12
1 0
1 1
1 2
10
1 1
1 2

07
X
X
X
X
X
X
X
X
X
X
X
X
X

D.
0
0
X
0
0
X
1
0
X
0
0
X
0

X

X

rx--O

05
1
1
1
0
1
0
1
1
0
1
1
0
0
0
0

04
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0

Input
D.
0
1
0
0
0
0
1
1
1
0
0
0
0
0
1

data

D. 0 , Do
1
0
0
0
0
0
0
0
0
1
1
1
0
0
0

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

0
0
0
0
0
0
0
0
0
0
0
0
1
1
0

HEX
24
28
20
00
30
1 0
68
28
08
24
24
----04
o1
01
08

X: Don't Care

Table-8

Division coefficient and input data

---------------ltO©®OO3-111

5C67
6. Set Function
The RF5C67 has SET terminal. Setting this terminal to 0 sets W33 = 1, W" = W'2 =.....
0 to filter coefficients and sets 1 to division coefficient. Then, unprocessed
data is output.
W54 = W56 =

7. Value Format
The following defines the format of external signals and internal operation values:
1) Input signal DAO to DEO, DAE to DEE (0 to 63)

6 bit integer unsigned magnitude

IL-IL-....JIL-....JIL-....JI---L--JI·

Decimal point
2) Filter coefficient Wll to W33 (- 64 to 63)

I

1

1

1

1

1

1

I·

7 bit integer two's compliment

3) Intermediate operation (sum of products) (- 4096 to 4095)

_2 10 2"2 '0 2" 2" 27 2" 2 5 2

4

2' 2 z 2' 2 0

13bit integer two's compliment
4) Division output (shifter 2 output) (- 8192 to 8191)

_2132102"2'02928272625242' 2 z 2' 2 0
14bit integer two's compliment
5) Format adjustment circuit output (0 to 63)

6 bit integer unsigned magnitude

8. Overflow in convolution
The sum-of-product operation of intermediate 25 elements are performed in 13-bit two's
compliment. Therefore, the intermediate result must be within· - 4096 to 4095. Otherwise
the results will be incorrect because of overfloWl or underflow.

-ICD®®OO-------------3-112

_IC_D©_®_[}{]__~I
RF5C136

EK-048-9007

Transversal Filter for
Video Signal

The RF5C136 Video Signal transversal Filter performs a ghost canceller of TV pictures by use of GCR
signal on the TV signal.
The LSI has a-bit signal Inputs and a-bit coefficient Inputs and includes 32 multipliers and 32 adders.
The 5C136 is fabricated in low-power COMS technology and is available in a 80 pin QFP .

• Features
(Function)
• Asymmetric 32 taps transversal filter (Cascade connection available)
(Data length)
a bit (Possible to switch absolute value with no-sign and 2's complement.)
• Input data
• Input coefficient: 8 bit (2's complement)
16 bit (2's complement, SUM output reset)
• SUM I/O
8x8 => 16bit
• Multiplier
16+19=> 19bit· SUM output 16bit
• Adder
(Operating frequency)
• Max. 16 MHz (Clock rate)
(Rewriting coefficient)
• Specifing the address of the coefficient register
• 8 bit parallel
• Coefficient reset
(Overflow detection)
• Overflow detect pin
• Possible to detect the overflow in the cascade connection by the use of daisy chain.
(Package)
.80 PIN QFP

• Application
• Ghost canceller

• Digital Video

• etc.

-------------ICD©®OO3-113

I

RFSC136

• Block Diagram
Coefficient Address
5bit

Decoder
(00000)

(00001)

(00010)

Data Output
8bit

Ollll)

Data Input
8bit

Coefficient Input
8bit

Note)

Coefficient Reset

0:
Chip Select

0---

Absolute Value/
2's Complement

0---

Register

181 : Multiplier

EEl:

Accumulator

Accumulated Data Output
16bit

Accumulated Data Input
16bit

• Pin Configuration
""MC"I .... OC'l'Xlt--O'Oll)"'"
....................

oooooooooOOUCOOOQt--O'Oll)""MN ....

~~~~~~~~~~~~s~~~~g888888

DOD
OFO
CAD
CAl
CA2
CA3
CM
VCC
GND
N.C

DAOIS
SOR
CRST
CDIO
CDII
CDI2
CDI3
VCC
GND
CDI4
CDIS
CDI6
CDI7
N.C.
N.C.

cs

CLK
WCK
DTC

OFT
010

DAI15

.... _ _ .... -

UQ

t--!'o~""'MN_

«««««<>O««OOQQOQQ
-~---------uz----------0000

OQOOOOOOOOQ

-IID©®OO--------------

RF5C136

• Pin Description
Pin Name

Description

I/O

Vcc

Power Supply

GND

GND

DI,-Dl o

I

Data Input
01, (MSB) - Dlo (lSB)
Data are input on the rising edge of ClK.

DO,-DO o

0

Data Output
DO, (MSB) - DOo(lSB)

DAIIs-DAl o

I

SUM Data Input
DAI IS (MSB) ~ DAlo(lSB)
Data are input on the rising edge of ClK.

0

SUM Data Output
DAO Is (MSB) ~ DAOo(lSB)

I

Coefficient Data Input
Data are input on the rising edge of WCK.

DAOIS~DAOo
COl,~CDlo

CA4~CAo

I

Coefficient Address Input
CA4 CA 3 CA 2 CAl CAo
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0

..

1

1

.
.

. ..
.

1

1

I

Number of Coefficient Register
0
1
2

1

··
·
31

CS

I

Chip Select (lOW Active)
When CS is low, the coefficient can be input.

DTC

I

Data Input Switch
High Absolute value format
lOW 2's complement

OFI

I

Overflow Input
OFI is used for cascade connection for overflow signal.
overflow is detected.

OFO

0

Overflow Output
OFO becomes low for overflow on the rising edge of ClK.

ClK

I

Clock Input

WCK

I

Clock Input for coefficient input

SOR

I

SUM Data output reset (lOW Active)
When SOR is low, all SUM.out data become low on the rising edge of
ClK.

CRST

I

Coefficient Reset Input (lOW Active)
When CRST is low, all coefficient registers become low on the rising
edge of ClK.

When low,

---------..,-------IIO©®OO3-115

RFSC136

• Absolute Maximum Ratings
Symbol
Vcc

Parameter
Supply Voltage

Condition

-0.3-7
-0.3-Vcc+O.3

V

1200
11

VTE

Voltage Range on Any Pin

GND=OV

Pd

Power Consumption
Power Reduction Rate

Ta~25°C

Topr

Operating Temperature

Tstg

Storage Temperature

Unit

Rating

GND=OV

Ta>25°C

Note

V

0-70

mW
mWrC
DC

-40-125

°c

Mounted
on a Board

• Recommended Operating Condition
Symbol

Parameter

Vcc

Supply Voltage

Ta

Operating Temperature

Condition

Value

Unit

4.5-5.5

V

0-70

°c

• DC Electrical Characteristics
Symbol

Parameter

Note

(Ta=Q-70°C Vcc=5V±10%)

Condition

Min.

Typ.

Max.

Unit

2.0

Vcc+0.3

V

VIH

"H" Input Voltage

VIL

ilL" Input Voltage

-0.3

0.8

V

ILl

Input Leakage Current

VIN=O-VCC

-10

10

p.A

VOH

"H" Output Voltage

IOH=-4mA

2.4

Note

V

VOL

ilL" Output Voltage

IOL=4mA

0.4

V

Icc!

Supply Current (stand by)

VIN=VCC

300

p.A

IcC2

Supply Current (operating)

14.3MHz

125

mA

-IIO®®OO------------3-116

RF5C136

• AC Electrical Characteristics
Symbol

Parameter

(Ta = 25°C Vcc=50V)

Condition

Min.

Typ.

Max.

Unit

Note

TClK

Clock Cycle

62

nsec

ClK
WCK

[Note lJ

TClK l

"l" level
Clock Pulse Width

20

nsec

ClK
WCK

[NotelJ

TClK H

"H" level
Clock Pulse Width

20

nsec

ClK
WCK

[Note 1 J

IMlS

Picture Input
Setup Time

refer to ClK

25

nsec

[Note2J

IMIH

Picture Input
Hold Time

refer to ClK

5

nsec

lNote2J

RDIS

Accumulated Data Input
Setup Time

refer to ClK

25

nsec

[Note 2J

RDIH

Accumulated Data Input
Hold Time

refer to ClK

5

nsec

[Note2J

CDS

Coefficient Data
Setup Time

refer to WCK

25

nsec

[Note3J

CDH

Coefficient Data
Hold Time

refer to WCK

5

nsec

[Note3J

CSS

Chip Select
Setup Time

refer to WCK

25

nsec

[Note3J

CSH

Chip Select
Hold Time

refer to WCK

5

nsec

[Note 3J

CAS

Coefficient Address
Setup Time

refer to WCK

30

nsec

[Note3J

CAH

Coefficient Address
Hold Time

refer to WCK

5

nsec

[Note3J

ODD

Output Data
Delay Time

from ClK

nsec

[Note4J

SORS

SOR
Setup Time

refer to ClK

25

nsec

[Note2J

SORH

SOR
Hold Time

refer to ClK

5

nsec

[Note 2J

CRTS

Coefficient Reset
Setup Time

refer to WCK

25

nsec

[Note3J

CRTH

Coefficient Reset
Hold Time

refer to WCK

5

nsec

[Note3J

35

Note) Output load=35pF

-------------ICO@®[J{]3-117

I

RF5C136

(Timing Chart)
Note 1)

Note 2)

TCLKH

CLK
WCK

CLK
TCLKL

~

=xL

TCLK

><==

~ ~old
~
time
time

Setup

Note 3)

Note 4)

WCK

CLK

g~:'!.7cCfI"

CS, CRST

=x

D07~DOo

: ~--~-~

DAO,,-DAO o

><==:',

___________-+i____~,'

i

~

'--000--'

i

Setup
: Hold-i
r-time ----- time

• Description

(1) Data Input Format
Input Format
DTC
Absolute value
2'5 complement

High
Low

(Absolute value format)

v

decimal point

Dh

D16
-2
2

- 1

2

DIs
-3

DI4
-4

Db
-5

Db
-6

DII

2

2

2

2

- 7
2

DI4
-3

Db
-4

DI2
-5

Dh
-6

2

2

2

2

DIo
-8
2

(2'5 complement)

v

Dh
- 2

a

decimal point

DI6

DIs

- 1

-2
2

2

DIo
- 7
2

-IID®®OO-------------3-118

RFSC136

(2) Coefficient data format (2's complement)

v

decimal point

CD7

CD6

0
-2

- 1
2

CD5
-2
2

CD,

CD3

CD4

CD,

CDo

-3

-4

-5

-6

-7

2

2

2

2

2

--

(3) Input/Output data on multiplier
(Absolute value format)

v
Signal data
(8 bit)

decimal point

1 ;1! ;2! ;3! ;4! ;5! ;6! ;1! ;8!

Coefficient data
(8 bit)

[7]; 1I ; 2!

; 3! ; 41 ; 5! ; 6! ; 1!

2's complement of
multiplied data
Multiplied
data output
SUM data
output
multiply data (13 bit)

expanded 3 bit

(2's complement)

v

decimal point

Signal data
(8 bit)

I_2°! ;1! ;21 ;3! ;41 ;5! ;6! ;1!

Coefficient data
(8 bit)

1_2 0 !;11;2!;31;41;5!;6!;1!

2's complement of
multiplied data
Multiplied
data output
SUM data
output

I

I

expanded 3 bit

multiply data (13 bit)

--------------ICO©@DO3-119

I

RFSC136

• Package Demension

2.9 max

18.8±0.4
(.740±0,016)

1.114 max)
0.15±0.05
1.006±0.002)

14.0 TYP
1.551 TYP)

0.2 TYP
1.008 TYP)

<0

",0
_0

~c;f

ON

~8

0-,

<0

a.Q:

'";:; >->f-f?,~

"""
~§

or-·co
~r-;

Unit:

(:::~)

-ICD©®DO-------------3-120

I

4. MPU

I

©! ! ! ! ! ! ! '®! ! ! ! ! ! ! '[}{]! ! ! ! ! ! ! '~I

EK·011·9007

!!!!!!!!!,!!!!!IC!!!!!!!!!!!!!!,O

CMOS 8bit MPU

RP65C02G/G·06
• GENERAL DESCRIPTION

• PIN CONFIGURATION (TOP VIEW)

The RP65C02 is 8·bit CMOS MPU. It has the instruction

RES

set and pins which are fully compatible with the NMOS
6502 MPU, and in addition with 59 new instructions. It is

tI.(OUT)

provided with the features of the CMOS such as the power·

SO

down standby mode, etc.

tI.(IN)
NC

WI

• FEATURES
•

68·type 210 instructions

•

Powerful 13·type" addr.essing modes

•

Programmable stack pointer

•

Maskable interrupt and non·maskable interrupt

•

6·type internal registers

•

Enable to connect the external memory with up to

•

8·bit bi:directional data bus, parallel processing

•

Clock

•

Computable decimal and binary

NC

6

SYNC 7

D.
D,

A,
A.
A.
A.
A.

64Kbytes
RP65C02G. • • . . . • . . •. 4 MHz
RP65C02G-06 • • • . . . . • • 6 MHz

•

8us compatible with M6800

•

Pin compatible with ROCKWELL R65C02

•

Single power supply 5V operation

•

Low power dissipation

R/W

D.
D,
D.

A.

Ds
D,
D,

A,
As
A,
A,.

AI5
AI<
AI3
A,.

v.s

• PIN DESCRIPTION
PIN NAME

PIN NAME

FUNCTION

FUNCTION

Vss

Internal Logic Ground

Vcc

+5V Power Supply

RDY

Ready

Ao -A,s

Address 8us

1/1, (OUT)

Clock 1 Out

RES

Reset

IRQ

Interrupt Request

1/12 (OUT)

Clock 2 Out

NC

No Connection

SO

Set Overflow

NMI

Non·Maskable Interrupt

1/10 (IN)

Clock 0 In

SYNC

Synchronize

RiW

ReadlWrite

Do - D7

Data Bus

-

---'--------------IIO©@[}[]4-1

I

RP65C02 G/G-06

• BLOCK DIAGRAM

40 RES
Ao

9

AI
Az
A3
A4

10
11
12
13
14
15
16

As

A6
A7

4 IRQ
6 NMI
2 RDY

37 1/>0 (IN)
31/>1 (OUT)
391/>2 (OUT)

As
A9
AIO
Au

A12
A13
AI4
A ls

17

- 34

18
19

33
32
31
30
29

20
22

23
24
25

RiW
Do

DI
D2
D3

D4
28 Ds

L-=================~~============~_27
26

D6
D7

• ABSOLUTE MAXIMUM RATINGS
Symbol

Parameters

Limits

Vee

Supply Voltage

-0.3~

+7.0

VI

Input Voltage

-0.3

+'7.0

Pd

Power Dissipation

Topr

Operating Ambient Temperature

Tstg

Storage Temperature

~

Unit

V
V

500

mW

0~+70

°c
°c

-40~+125

-ICO@®OO--------------4-2

RP65C02 G/G-06

• ELECTRICAL CHARACTERISTICS
• DC ELECTRICAL CHARACTERISTICS (Vee = 5.0 ± 5%, Ta = 0 - +70°C)
Symbol

Parameters

Measuring
Conditions

Specified Value
Min

Typ

Max

Unit

VIH

Input High Voltage
rf>o (IN), NMI
RES, ROY, IRQ, SO, Do - 0 7

0.7·Vcc
2.0

Vcc+0.3
Vcc+0.3

V
V

VIL

Input Low Voltage
rf>o (IN), NMI
RES, ROY, IRQ, SO; Do - 0 7

-0.3
-0.3

0.2
0.8

V
V

ILl

ILO

VOH

VOL

loc

C

Input Leak Current
RES, NMI, ROY, TAO, SO
(Internal Pull·Up)
rf>o (IN)
Output Floating Leakage Current
Do - 0 7
Output High Voltage
rf>, (OUT),rf>2 (OUT), SYNC, Do - 0 7 ,
Ao -A,s, RNi
Output Low Voltage
rf>, (OUT), rf>2 (OUT), SYNC, Do - 0 7 ,
Ao - A 15 , RNi
Power Disspation (No·Load)
Stand-By
Active
Low-Power
I nput Capacitance
Logic,rf>o (IN)
rf>, (OUT),rf>2 (OUT), SYNC, Do - 0 7 ,
Ao -A,s, R/W

Vcc - 5.25V
VIN = 0 - 5.25V

-100

10

/lA

-10

10

/lA

-10

10

/lA

VIN = 0 - 5.25V
ILOAD = -100/lA
Vcc = 4.75V

V

2.4

ILOAD = 1.6 mA
Vcc = 4.75V

0.4

rf>o • = Vcc or 0,

28

!lA

5
2

mA/MHz
mA/MHz

10
20

pF
pF

VIN = Vcc
RDY=O

V

VIN = 0, f = 1 MH

• AC ELECTRICAL CHARACTERISTICS (Vee = 5V ± 10% Ta = 0 - 70°C)
Symbol
tcYC

PW02L
PW02H
tR, tF
tAos
tHA
tRWS
tHRw
tDSU
tHR
twos
tHw
tAcc
'!pes
toLY
toLY,

65C02G (4 MHz)

Parameters
Cycle Time
rf>2 (OUT) "Low" Clock Pulse Width
rf>2 (OUT)"High" Clock Pulse Width
Clock Rising Time, Clock Falling Time
Address Delay Time
Address Hold Time
R/W Delay Time
R/W Hold Time
Read Data Set-Up Time
Read Data Hotel Time
Write Data Delay Time
Write Data Hold Time
Read Access Time
Processor Control Set-Up Time
(ROY, SO, IRQ, NMI, RES)
Delay Time rf>o (IN) to rf>2 (OUT)
Delay Time rf>, (OUT) to rf>2 (OUT)

65C02G-06 (6 MHz)

Min

Max

Min

Max

250
100
110

DC
DC
DC
10
80

166
75
80

DC
DC
DC
10
70

Unit

30
140

20
76

ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

60

40

ns

15

15
80

80
20
30
10

15
20
10
50

60

-20

50
20

-20

40
20

ns
ns

(Output Load Includes Scope and Jig Capacitance is 130pF)

----------~----IIO©®[]{]4-3

I

RP65C02 GIG 06

• TIMING CHART
1------------tCyc:--------=L--~-i

¢o (IN)

tR~------__tF~~----------

__________
~tDLY

¢l(OUT)

PW02H

¢,(OUT)

I
I

tADS

-----:

Ao-A1s, ------+--~ I.--..;,;,;,:..:....---+----------+-~

SYNC

I

1 - - - - - - - - - - ; - ' tACC-------I

I

I

--,I
R/W
Do-D7
(R/W=H1GH)
Do-D7
(R/W=LOW)

,,
I

~tpcs

RDY, IRQ

NMI, RES

I

:-----tpcs

SO

• PIN DESCRIPTION
• Clock Input (4)0 (IN))
It is the input terminal to generate the system clock in the
inside and input the reference clock from the outside. The
operating frequency is between 4 and 8 MHz. And when

I

4>0 (IN) stops at highlevel or lowlevel, the CPU becomes

I

I

I

I

: ADDRESS VALID

the stand·by mode.

\6,(OUT)_

tDLY1

• Clock Output (4)1 (OUT), 4>2 (OUT))
The two signal 4>1 (OUT) or 4>2 (OUT) for the system·clock
output.

DATA VALID

These are provided with each device for control

Fig. 1 Phase Relation by System·Clock 1/>1 (OUT),
1/>2 (OUT)

bus synchronous signal. Phase relation 1/>1 (OUT), 1/>2 (OUT)
are as shown in Fig. 1

-IIO@®[l{]-------------4-4

RP65C02 G/G-06

• Address Bus (Ao ~ A 15

• Bus Direction Indicative Signal (RIW)

)

Ao ~ AI5 constitute a 16-bit address bus. The address that

It is the signal to decide the direction of data bus.
In reading (input data from other device to the CPU) "1"

is indicated with these bits are hexadecimal $0000 ~ F F F F.
(decimal 0

~

65535)

is output, and in writing (output data from the CPU to
other) "0" is output. Read or write timing are as shown in

• Data Bus (Do ~ 0 7 )
Do

~

Fig. 2, Fig. 3.

D7 constitute the B-bit bidirectional data bus, input

or output.

;, (OUT)
;2(OUT)

I
0 0 -0,

I

Not Valid
I

Fig. 2 Read Mode Timing

;,(OUT)
;2(OUT)

R/W

0 0 -0,
Fig.3 Write Mode Timing

---------------IID©®OO4-5

RPS5C02 GIG-OS

• Ready Signal (ROY)
This RDY input allows to single·step operation or stop on

and to start. During that the input is Low level, READ/
WR ITE to the CPU is not all accepted. When the rising

all cycles.

time signal of the pin is detected, the CPU becomes the

When the falling edge of ¢2 (OUT) is detected,

the CPU stop. When the CPU stop, the address line fetch

reset mode at once.

the current address and when the operation is WR ITE

After initial setting time of the 5 clock time, the interrupt

mode, the data bus fetch the current data. When the Po DY

mask flag is set, the CPU reads the vector address from each

input is low, the CPU becomes low·power mode.

location (FFFC)(FFFD), and sets the program-counter.

• System Reset (RES)

The input consists of the Schmitt trigger circuit as which
power on reset is acted by only CR.

The input is used to reset the CpU in a power down state

I
I
i 1 I i 2 I i3

I

i4

i 5 I

I

I

i 6 I i 7 I

I

¢2(OUT)

Address

Data

I

R/W
I

I
I

-8 I

nl----+I----~--~---T----L---~---L--~~

I
I

SYNC

I
I

I-

I

I tpes

I

I

I

r----\I

I

I

I

~~--4---~--~---L--~--_~

0I

Fig. 4 Reset Moue Timing

• Interrupt Request Signal (I RQ, NMI)
I RQ (Interrupt Request)

counter. The program control is changed a memory vector

If the TTL compatible input is the low level, the CPU starts

which is stored these location.

the interrupt operation. When the instruction in execution

To accept an interrupt, RDY signal should be high level.

is finished, the CPU allows the interrupt request, but at

These are just same with all interruptions. When it is used

the same time, the interrupt mask bit in the status code

to the wired OR with this pin, it must use a pullup resistor.

register is checked, and if not set, the CPU begins the

NMI (Nonmaskable Interrupt)

execution of the interrupt sequence. The program-counter

When the falling signal is input in pin, the CPU detects

and status register are loaded with stack, the interrupt mask

this edge, and starts the nonmaskable interrupt operation.

flag is set so as not to accept any other interrupts. At the
end of this cycle, the content of location FFFF load into

NMI is unconditional interrupt request. When the instruction in execution becomes end, the similar operation to

high order a-bit of program-counter, and the content of

I RQ is executed regardless of the state of interrupt mask

location FFFE load into low order a-bit of program-

flag.

I

-IIO®@[]{]------~------4-6

RP65C02 G/G-06

In the vector address which is loaded to program-counter,
high order B-bit are contents of location FFFB, and low
order B-bit are contents of location F F FA. The programcounter changes to these addresses. When it uses the wired
OR with this pin, it must use the puliup resistor.
IRQ and NMI are interrupt inputs of hardware which is
sampled in the inside of the CPU during ¢z time. After a
instruction in execution comes at the end, it executes
next interrupt routine from the first ¢1 time.
I
I"'i«-(-------- Interrupt Sequence ---------:)'"'""<

Interrupt Routine

I

I

:11: 6

Data
I

I

,4

·1

IRQ

NMI

I

I
I

I
I

SYNC

~l
I
I

I
I

I
I

I_---L--~:----~

~

n
I

I

I

\

I
I
I

It;cs

I

I

I
I

~

II

R/W

:11: 7

__~__~----JI

I

I

I

I

I
I

I
I

I

I

L _ - - I_ _--1_ _--l_ _--i_ _--II--_ _ I

I

I'L

I
I

I

I

* SP: Stack Pointer
P: Processor Status Register

Fig. 5 Interrupt Operation Timing

• Overflow Flag Set Signal (SO)

MSB

As this signal is

sampled by the rising edge of ¢z (OUT), the input must be
synchronized outside.

• I nstruction
(SYNC)

Vector Address of NMI FFFA/FFFB
Vector Address

The overflow flag bit (V) in the status code register is set
by the falling edge input to this pin.

*** Vector Address of IRQ FFFE/FFFF

Fetch Cycle Synchronous Signal

LSB

Signal Names

FFFF

FFFE

FFFD

FFFC

IRQ
RES

FFFB

FFFA

NMI

This output signal indicates the cycle that the CPU fetch
the instruction code.

It becomes "High Level" at the

instruction is load and during the cycle time that SYNC
is high level. During cycle time that SYNC is high level, if
RDY input is set at the low level, the CPU halts with the
state until RDY becomes high level.
The single step execution is enabled by control of RDY.

---------------ICO@®[J{]4-7

•

RP65C02G/G-06

• ADDRESSING MODE
The Fig. 6 shows a sample of pattern which machine
language is stored in t,he memory. Generally the instruction
consists of OP-code and operand (modifies the OP-code).
The operand gives the information of address. Instruction
1 consists of the OP-code, and instruction 2 consists of the
l-byte OP-code and operand. Instruction 3 consists l-byte
OP-code, 2-byte operand. The CPU is informed the length
of each instruction by the OP-code and is fetch the operand
of the number of the required bytes by this information.
The OP-code have the information which shows the kind
of the operand. The kind of this operand is equivalent to
the addressing mode.

0
/ IBI
'------""'" '--.-/
A

Instruction 1

/ A

B

B

<:::::::_____7

Instruction 2

I

Instruction 3

A: OP-code
B : Operand

• Absolute Addressing
This type is 3-byte instruction (OP-code .is i-byte and
operand is 2-byte). The 2-byte address indicates the low
order, the third byte address the high order, all of 64
Kbytes is accessed.
Low Order Address

High Order Address

Describes directly the execution address.
Fig. 9 Absolute

• Zero Page Addressing
This type is 2-byte instruction of OP-code and operand.
The high order address is automatically set "00". With
addressing a low order address, it is able to code and the
short of the execution. It is able to use efficiently the
memory space and execute time by using the addressing
suitably.
lOP-code

Fig. 6 A Sample of Pattern which Machine
Language is Stored in Memory

ILow Order Address

Execution high order address becomes "00" .

• Accumulator Addressing
This type includes the addressing in the single byte and is
equivalent to the execution in the accumulator.

Fig.10 Zero Page

• Implied Addressing
The instruction code is l-byte order. Almost all of the
instruction control registers which is the internal memory
equipment of the CPU, and needs no addressing.

OP-code

t
The execution on the accumulator.

OP-code
Fig. 7 Accumlator

I

Without address.

• Immediate Addressing
This type is 2-byte instructions having the OP-code and
operand. The operand has not information of addressing,
but describes the data itself.

IOP-code IData
t
Address is not needed.
Fig. 8 Immediate

Fig. 11 Implied

• Indexed Zero Page Addressing
This is 2-byte instruction of OP-code and operand. It is
called as "ZERO PAGE X" or "ZERO PAGE V' because
the execution ad.dress is addressad with the indexed register
(Xor V).
This is one of the zero page addressing. The high order
addressing is set automatically "00", and low address is
added with the content of the 2-byte. As the carry after
the calculation is not added, the execute address does not
exceed zero page.

-IIO©(IDOO----~--------4-8

RP65C02 G/G-06

IOP-code I LOW Order AddrE'ss I

• Indexed Indirect Addressing
This is 2-byte instruction of OP·code and operand. As
execute address is indirectly addressed, it is called as
"Indirect X"
The execute address is added with 2-byte of instruction and
content of X·register, and the carry is neglected. When the
content of calculation is the address of Zero page the
content stored in the address becomes the low order 8-bit
of effective address, and the content of n~xt address
becomes the high order. The address of stored memory
(high and low order) that appoints the effective address
must be in the zero-page.
The content is stored in the address is low order 8-bit of
effective address.

Execution High Order Address: 00
Execution Low Order Addre;:.s=s~:_ _ _ _ _ _ _----,
Low Order Address + Index register (X or V)

I

I I

Neglect the carry.
Fig. 12 Z Page X; Z Page Y

• Indexed Absolute Addressing
This is 3-byte instruction of 1-byte OP-code, 2-byte operand. The execute addressing is addressed with the index
(X or V). It is called as "absolute X" or "absolute V".
This is one of the absolute addressing. Execute address is
added with the content of index register. The count of
index and content of count are stored in the index register.
And it is able to address the base address by the OP-code.
It is able to modify the plural areas by using some base
address and index, and the code and execution time can be
shortened.
Low Order Address

IOP·code I Low Order Address
Execution Address Low Order:
Low Order Address
+ X register

High Order Address

Execution Address High Order:

Execution address:

IHigh Order Address I Low Order Address

Low Order Address
+ X register + 1

1+

I Index Register (X or V) I

• Indirect Indexed Addressing
This is 2·byte instruction of OP·code and operand. It is
called as "Indirect, V" as it appoints indirectly effective
address. The 2-byte of OP-code shows the address of Zero
page. The content of V register is added with the content
of memory, and the result becomes the low 8·bit of effective address. Carry is added to the content of next memory
in the zero-page and it becomes the high order 8·bit of
effective address.

• Relative Addressing
This is 2·byte instruction of OP-code and operand. It is
used only for the jump OP-code, and appoints the jump
address, 2-byte oder of OP-code is called as "offset" and
is added with the content of offset to the low oder 8·bit
of program-counter set to the location of next instruction.
It has the range of -128 to +127-byte. The range of the
branch is -128 to 127 ·byte from the head address of next
instruction.
OP-code

content of
the address

Fig. 15 (lND, X)

Fig. 13 ABS, X; ABS, V

I

content of
address

I OP-code I Low Order Address

I

Offset

Execution Address Low Order:

I00 I Low Order Address I

Offset value is -128(80H) - +127(7FH)
Content of Address + V register
Fig. 14 Relative

---------------ICO©®OO4-9

•

RP65C02 G/G-06

Execution Address High Order:

I00 I Low Order Address + 1 I
Content of Address + Carry
Fig. 16 liND), V

• Indirect Addressing
This instruction is 2-byte of OP-code and operand. Execution address is address of Zero page.
Contents of this address becomes low order a-bit of execution address, and contents of the next address becomes high
order a-bit of execution address. This is the same operation
as in the ease of X being zero in "indirect, X".

• Absolute Indirect Addressing
The 2-byte of the instruction contains the low order a-bit
of a memory location. The high order a-bit of that memory location are contained in the 3-byte of the instruction.
The contents of the fully specified memory location are
the low order byte of the effective address. The next
memory location contains the high order byte of effective
address which is loaded into the 16-bit of the program
counter.
Low Order Address

Content of Address

IOP-code I Low Order Address I
Execution Address Low Order:
00 Low Order Address content of address

I I

High Order Address

I

Next memory data

Fig. 19 JMP liND)

Low Order Address
content of address
+1

• Bit Addressing
Fig. 17 Indirect

• Indexed Absolute Indirect Addressing
This is 3-byte instruction lOP-code is 1-byte, operand is
2-byte). The result which adds the content of 2-byte or
3-byte to content of X register becomes the memory
address that stores information of execution low order
address a-bit. The content of next address becomes high
order a-bit of the execution address.
Low Order Address

In the instruction set IBBR, BBS, RMB, 5MB), Op-code
corresponds to bit OP-code .
[BBR, BBS] This is 3-byte instruction lOP-code is 1-byte,
operand is 2-byte). Execution address is zero page. Low
order address is 2-byte of instruction.
3-byte of instruction is offset content which points the
address of branching.

IOP-code I Low Order Address I Offset
Execution Address: I 00 I Low Order Address I

High Order Address

Fig. 20 BBR, BBS

Execution Address Low Order:

I High Order Address ILow Order Address I+
Content of Address
IX Register I

[RMB, 5MB] This is 2-byte instruction of OP-code, operand. Execution address is zero page, low order address is
2-byte of instruction.

Execution Address High Order:

I High Order Address I Lo~ Order Address I+
Next Memory data
IX Register I

OP-code

I Low Order Address

Execution Address:

I00 I Low Order Address

Fig. 21 RMB, 5MB

Fig. 1a JMP liND), X

-IIO@®[J{]I-------------4-10

RP65C02 G/G-06

• INTERNAL REGISTER
PROCESSOR STATUS REGISTER "P"

o

7

o
7
I...-_--:..!._---'[
A
I

[N[V[
ACCUMULATOR A

7
.:-_~_--;O
INDEX

L---.!...----'ci

I

Y

Y

REGISTER
7
.:---:-:----; INDEX
X
REGISTER

IL---!!.----.Jci
7
I PROGRAM
PCH
I PCL
IL---~~--L---~~~o
COUNTER
15
7
I
STACK
01
S
I
IL-__
POINTER
15

[B1D111z1cl

L---

X

1 = WITH CARRY

ZERO

1 = RESULT
ZERO

IRQ INHIBIT 1 = INHIBIT

"PC"

~_----.JL-_~_----J

CARRY

"s"

DECIMAL
MODE

1 = DECIMAL
MODE

BREAK
COMMAND

1 = BREAK

OVERFLOW 1 = OVERFLOW
NEGATIVE

•

NEGATIVE
1 = NUMBERS

INSTRUCTION SET (Alphabetical order}

(2) ADC

Add memory and accumulator with carry

CPX

Compare memory with index register X

(2) AND

Logical AND memory and accumulator

CPY

Compare memory with index register Y

ASL

One bit left shift (memory or accumulator)

(2) DEC

Decrement memory

(1 ) BBR

Branch if bit reset

DEX

Decrement index register X

(1) BBS

Branch if bit is set

DEY

Decrement index register Y

BCC

Branch if carry is cleared

(2) EOR

Exclusive OR memory or accumulator

BSC

Branch if carry is set

(2) INC

Increment memory

BEQ

Branch if result is zero

INX

Increment index register X

Test memory bit with accumulator

IN Y

Increment index register Y

(2) BIT

BM I

Branch if result is negative

(2) JMP

BNE

Branch if result is not zero

JSR

BPL
(1) BRA

Branch if result is positive

(2) LOA

Jump to new location
Jump to new location, hold return address
Load memory into accumulator

Unconditional branch

LOX

Load memory into index register X

BRK

Forced break

LOY

"Load memory into index register Y

BVC

Branch if overflow is cleared

LS R

One bit right shift (memory or accumulator)

BVS

Branch if overflow is set

NOP

No operation

CLC

Clear carry flag

CLD

Clear decimal mode

(2) ORA

PHA

Logical OR memory and accumulator
Push accumulator on stack

CLI

Clear disable interrupt

CLV

Clear overflow flag

(1) PHX

Push X register on stack

Compare memory with accumulator

(1) PHY

Push Y register on stack

(2) CMP

PHP

Push processer status on stack

ItD©®OO4-11

I

RP65C02 G/G-06

(2) STA

Store accumulator to memory

PLA

Pull accumulator from stack

PLP

Pull processer status from stack

STX

Store index register X to memory

(1) PLX

Pull X register from stack

STY

Store index register Y to memory

(1) PLY

Pull Y register from stack

(1) STZ

(1) RMB

Reset memory bit

TAX

Transfer accumulator to index register X

Rotate left circular of one bit (memory or

TAY

Transfer accumulator to index register Y

ROL

(1) TRB

accumulator)

Zero store

Test or reset bit

Rotate right circular of one bit (memory or

TSB

Test or set bit

accumulator)

TSX

Transfer stack pointer to accumulator

RT I

Return from interrupt

TXA

Transfer index register to accumulator

RTS

Return from subroutine

TXS

Transfer index register to stack pointer

Subtract memory ar.d borrow from accumu·

TYA

Transfer index register to accumulator

ROR

(2) SBC

lator
SEC

Set ca rry fl ag

SED

Set decimal

SEI

Set disable interrupt ststus

(1 ) 5MB

Set memory bit

Note (1): the instructions are newly designed in
65C02
(2): the instructions are added addressing in
65C02

-110 ©®0 0 - - - - - - - - - - - - - - 4-12

RPS5C02 GIG-OS

• INSTRUCTION SET (Matrix Map)

- Operation Code
- Addressing Mode
- Bytes: Cycles

LSD

A

BRK
IMP
17
BPL
REL
22"

JSR
ABS
36
8MI
REL
22"

RTI
IMP
16
BVC
REL

22"
RTS
IMP
16
BVS
REL
22"
BRA
REL
23
BCC
REL
22"

A

B

C

LOY
IMM
22
BCS
REL

22"
CPY
IMM
22

D

BNE
REL
22"

E

CPX
IMM
22

F

BED
REL
22"

ORA
(lND.XI
26
ORA
(INDI,Y
2 5'
AND
(IND,XI
26
AND
(INDI,Y
2 5'
£OR
(IND,XI
26
£OR
(INDI,Y
2 5'

ORA
UNO)
25

AND
(INDI
25

TSB
ZP
25
TRB
ZP
25
BIT
ZP
23
BIT
ZP,X
24

£OR
(lNDI
25

AIlC

(IND,X)
2 6t
AIlC

AIlC

(IND),Y
2 5"
STA
(IND,X)
26
STA
(IND),Y
26
LOA
(IND,X)
26
LOA
(IND),Y
2 5'
CMP
(lND,X)
26
CMP
(IND),Y
2 5'
SBC
(lND,X)
26t
SBC
(IND),Y
2 5't

(lND)
2st

STA
(lND)
25
LOX
IMM
22
LOA
(lND)
25

STZ
ZP
23
STZ
ZP,X
24
STY
ZP
23
STY
ZP,X
24
LOY
ZP
23
LOY
ZP,X
24
Cpt
ZP
23

CMP
(IND)
25
CPX
ZP
23
SBC
(lND)
25t

ORA
ZP
23
ORA
ZP,X
24
AND
ZP
23
AND
ZP,X
24
£OR
ZP
23
EOR
ZP,X
24
AIlC

ZP
23t
ADC
ZP,X
24t
STA
ZP
23
STA
ZP,X
24
LOA
ZP
23
LOA
ZP,X
24
CMP
ZP
23
CMP
ZP,X
24
SBC
ZP
23t
SBC
ZP,X
24t

ASL
ZP
25
ASL
ZP,X
26
ROL
ZP
2.5
ROL
ZP,X
26
LSR
ZP
25
LSR
ZP,X
26
ROR
ZP
25
ROR
ZP,X
26
STX
ZP
23
STX
ZP,Y
24
LOX
ZP
23
LOX
ZP,Y
24
DEC
ZP
25
DEC
ZP,X
26
INC
ZP
25
INC
ZP,X
26

RMBO
ZP
25
RMBI
ZP
25
RMB2
ZP
25
RMB3
ZP
25
RMB4
ZP
25
RMB5
ZP
25
RMB6
ZP
25
RMB7
ZP
25
5MBO
ZP
25
5MBI
ZP
25
5MB2
ZP
25
5MB3
ZP
25
5MB4

tp

25
5MB5
ZP
25
5MB6
ZP
25
5MB7
ZP
25

PHP
IMP
13
CLC
IMP
12
PLP
IMP
14
SEC
IMP
12
PHA
IMP
13
CU

IMP
12
PLA
IMP
14
SEI
IM~

12
DEY
IMP
12
TYA
IMP
12
'TAY
IMP
12
CLV
IMP
12
INY
IMP
12
CLO
IMP
12
INX
IMP
12
SED
IMP
12

ORA
IMM
22
ORA
ASS.Y
3 4'
AND
IMM
22
AND
ABS,Y
34'
£OR
IMM
22
£OR
ABS,Y
3 4'
AIlC

IMM
22t
AIlC

ABS,Y
34't
BIT
IMM
22
STA
ASS,Y
35
LOA
IMM
22
LOA
ABS,Y
34'
CMP
IMM
22
CMP
ABS,Y
34'
SBC
IMM
22t
SBC
ABS,Y
34't

A

D

t

B

ASL
ACC
12
INC
ACC
12
ROL
ACC
12
DEC
ACC
12
LSR
ACC
12
PHY
IMP
I3
ROR
ACC
12
PLY
IMP
14
TXA
IMP
12
TXS
IMP
12
TAX
IMP
I2
TSX
IMP
12
DEX
IMP
I2
PHX
IMP
13
NOP
IMP
12
PLX
IMP
14
B

C
TSB
ABS
36
TRB
ABS
36
BIT
ABS
34
BIT
ABS,X
34'
]MP
ABS
33

D

E

F

ORA
ABS
34
ORA
ABS,X
34'
AND
ASS
34
AND
ASS,X
34'
£OR
ABS
34
EOR
ABS,X
34'

ASL
ABS
36
SAL
ABS,X
3.6'
ROL
ABS
36
ROL
ASS,X
36'
LSR
ABS
36
LSR
ASS,X
36'
ROR
ABS
36
ROR
ASS,X
36'
STX
ABS
34
STZ
ASS,X
35
LOX
ASS
34
LOX
ASS,Y
34'
DEC
ABS
36
DEC
ASS,X
3 6'
INC
ASS
36
INC
ASS,X
36'

BBSO
ZP
35"
BBRI
ZP
35"
BBR2
ZP

AIlC
JMP
ASS
IND
36
34t
AIlC
JMP
(IND),X ABS,X
34't
36
STY
STA
ASS
ASS
34
34
STZ
STA
ASS ASS,X
34
35
LOY
LOA
ASS
ASS
34
34
LOY
LOA
ABS,X ABS,X
34'
3 4'
CPY
CMP
ABS
ABS
34
H
CMP
ASS,X
34'
CPX
SBC
ABS
ASS
34
34t
SBC
ABS,X
34't
D
C

E

o

35"

BBR3
ZP
35"

BBR4
ZP
35"

BBR5
ZP
35"
BBR6
ZP
35"
BBR7
ZP

I

35"

BBRO
ZP
35"
BBSI
ZP
35"

BBS2
ZP
35"
BBS3
ZP
35"
BBS4
ZP
35"
BBS5
ZP
35"
BBS6
ZP

A

B

C

D

E

35"

BBS7
ZP
35"

F

F

Cycles Add 1 when decimal mode
Cycles Add 1 when page crossing occurs

Newly Designed Instruction

Cycles Add 1 when branch in same page
Add 2 when branch in different page

~----'------------ltD©®[]{]4-13

RP65C02 G/G-06

• INSTRUCTION SET
MNEMOMC
ADC
AND
ASL
BBR(#0-7)
BBS(#0-7 )
BCC
BCS
BEQ
BIT
BMI
BNE
BPL
BRA
BRK
BVC
BV8
CLC
CLD
CLI
CLV
CMP
CPX
CPY
DEC
DEX
DEY
EOR
INC
INX
INY
JMP
J8R
LDA
LDX
LDY
LSR
NOP
ORA
PHA
PHP
PHX
PHY
PLA
PLP
PLX
PLY
RMB(#0-7)
ROL
ROR
RTI
R'l'S
SBC
SEC
SED
SEI
5MB(#0-7 )
STA
STX
STY
STZ
TAX
TAY
TRB
T8B
TSX
TXA
TXS
TYA

ADDRESSING

OPERATION
A+M+C~A

A~¥~*r-(1)
C--0

op n

0 op

n

0 op

n

ACCUM IMPLIED (IND. X) ONDl. Y
0 op n 0 op n 0 00 n 0 op n 0

69 2
29 2

2 6D 4
2 2D 4
OE 6

3 65
3 25
3 06

3
3
5
5
5

2
2
2 OA 2
3
3

3

2

IMMEDIATE ABSOLUTE ZEROPAGE

(1X5)

(1)

Branch on Mb=O
Branch on Mb=1
Branch on C =0 (2)
Branch on C = I (2)
Branch on Z = I (2)
AJ\M
Branch on N =1 (2
Branch on Z =0 (2)
Branch on N =0 (2)
Branch Allways (2)
Break
Branch on V =0 (2)
Branch on V = 1 (2)
O-C

(6l

-

89

2

2 2C 4

3 24

I

O~D
O~I

O-V
A-M (1)
X-M
Y-M
M-I-M (1)
X-I-X
Y-I-Y
VVM-A (1)
M+I-M (1)
X+I-X
Y+ I~Y
Jumo to New Lac
JumX Sub
M~

(1)

M-X (1)

M~J
o

(al

(1)
-C
No Ooerat ion
AVM-A (1)
A-Ms S-I-S~
P-Ms S-I-S
X-Ms S-I-S
Y-Ms S-I-S
8+I-S Ms-A
S+I-S Ms-P
8+I-S Ms-X
8+1--+S Ms-Y
O-Mb (4)

~

X:
Y:
A:
M:

49

2

2 CD 4
2 EC 4
2 CC 4
<;:E 6

3
3
3
3

C5 3
E4 3
C4 3
C6 5

2
2
2
2 3A 2

I

2 4D 4
EE 6

3 45 3
3 E6 5

2
2 IA 2

I

A9
A2
AO

2
2
2

4C 3
20 6
2 AD 4
2 AE 4
2 AC 4
4E 6

3
3
3
3
3
3

09

2

2 OD 4

3 05 3

A5 3
A6 3
A4 3
46 5

2E 6
6E 6

(1)
(1)

Rtrn Su.b
A-M-C-A (1)(5)
I-C
I-D
1- I
I-Mg (4)
A-M
X-M
Y-M
O-M
A-X
A-Y
AJ\M-M
AVM-M
8-X
X-A
X-S
V-A

(Synibol Description)

C9 2
EO 2
CO 2

E9

Index X
Index Y
Accumulator
Designated Memory
with Effective Address

2

2 ED 4

8D
8E
8C
9C

4
4
4
4

IC 6
OC 6

3 26
3 66

5
5
5

2
2
2
2 4A 2

3 E5 3

2

-

2
2
2

3
3
3
3

85
86
84
64

5
3
3
3
3

3 14 5
3 04 5

7

I

18
D8
58
B8

2
2
2
2

I
I
I
I

CA 2
88 2
E8
C8

6

2 71
2 31

5
5

2
2

CI

6

2 DI

5

2

41

6

2 51

5

2

I
I
I
1

I
1

EA 2

1

48
08
DA
5A
6.8
28
FA
7A

3
3
3
3
4
4
4
4

1
1
1
I
1
1
I
1

40 6
60 6

I
1

38 2
F8 2
78 2

1
I
I

7C 6

3

Al

6

2 BI

5

2

01

6

2 11

5

2

EI

6

2 FI

5

2

81

6

2 91 6

2

2

2
2
2

AA 2
A8 2

I
1

2

1
I
1
I

BA
8A
9A
98
Ms:
Mb:
M,:
M,:

2
2

21

1

2

2
2 2A 2
2 6A 2

00

61 6

2
2
2

Designated Memory with Stack pointer +: Add
Zero page Memory Bit
-: Subtract
Memory Bit 7
1\ : Logical AND
Memory Bit 6
V : Logical OR

V : Exclusive OR
n: Machine Cycles
#: Bytes

-IID©(ID[]{]--------------4-14

RP65C02 G/G-06

PROCESSOR STATUS
CODES
ZPAGE, X ZPAGE,Y ABS,X
ABS, Y RELATIVE INDIRECT BIT ADDRESSING(OP BY BIT 0) 7 6 5 4 3 2 1 0
B D I Z C
Op n 0 Op n 0 Op n 0 Op n 0 op n 0 Op n 0 0 1 2 3 4 5 6 7 N V
Z C
75 4 2
7D 4 3 79 4 3
72 5 2
N V
32 5 2
N
Z
35 4 2
3D 4 3 39 4 3
16 6 2
N
Z C
IE 6 3
OF IF 2F 3F 4F 5F 6F 7F
8F 9F AF BF CF DF EF FF
90 2 2
BO 2 2
FO 2 2
M7 M6 •
34 4 2
3C 4 3
Z
30 2 2
DO 2 2
10 2 2
80 3 2
1
1
50 2 2
70 2 2

MODE

0

0
D5

4

2

DD 4

3 D9

D6

6

2

DE 6

3

55 4
F6 6

2

2

5D 4
FE 6

3 59
3

4

2

BD 4

B4 4
56 6

2

15 4

B5

4

3

D2

5

2

4

3

52

5

2

6C 5

3

3
3

B2

5

2

BC 4
5E 6

3 B9 4
BE 4
3
3

2

1D 4

3 19

3

12

5

B6

4

2

4

0
N
N
N
N
N
N
N
N
N
N

Z C
Z C
Z C
Z
Z
Z
Z
Z
Z
Z

2

N
N
N
0

Z
Z
Z
Z C

2

N

Z

N

36 6
76 6

2

3E 6
7E 6

3
3

F5

2

FD 4

3 F9

4

2

07 17 27 37 47 57 67 77

4

3

F2

5

2

(Restored)

N
N

2

94 4
74 4

2

2

96 4

2

9D 3

3 99 5

9E 3

3

3

92

5

2

(Restored)

Add 1 to "N" when machine'cycles or zero page crossing.
Add 1 to "N" when branch in same page, Add 2 to "N" when branch in different page,
Not carry = borrow
Effect when zero page address.
Add 1 when decimal mode.
When the BIT (iMM mode), not related to M, or M, bit (N, V flag) of register P.

1

N
N

Z
Z
Z
Z
Z
Z

N

Z

N
N

NOTE (1)
(2)
(3)
(4)
(5)
(6)

Z C
Z C
Z (31
1

N V

87 97 A7 B7 C7 D7 E7 F7

Z
Z
Z

N
N

1
95 4

0

---------------ICO©®DO4-15

I

RP65C02 G/G-06
• Instruction Description (Alphabetical Order)
Description of symbol using in list
A

Accumulator

Subtract
Exclusive OR
-+
Transfer
Transfer
---V Logical OR
PCH Program Counter High
PCL Program Counter Low

X,V Index Register
M
p
S
Ms
Mb
+

'rf

Memory
Processor Status Register
Stack Pointer
Stack Memory
Memory Bit
Add
Logical AND

ADC Add with carry of memory and accumulator.
Operation: A+M+C -+ A
"P" Register: N, V, Z, C

Bee Branctl if the carry is reset.
Operation: branch when C = 0
"P" Register: Not affected

AND Logical AND of memory. and accumulator. The result is stored in accumulator.
Operation: A M -+ A

BCS Branch if the carry is set.
Operation: branch when C = 1
"P" Register: Not affected

"P" Register: N, Z
ASL One bit left shift.

BEQ Branch if the zero flag is set.
Operation: branch when Z = 1
"P" Register: Not affected

LSB is placed "0". Contents of

MSB is pla"ed C',-,-.---.--r--.--.,-,,--,
Operation: C ---17/6/5/4/3/2/1/ 0 / <- "0"
"P" Register: N, Z, C

BIT Test the memory bit by the accumulator.
Operation: A M, M, -+ N, M6 -+ V
The bit 6 and bit 7 of the memory are transferred
to "P" Register.
If the result of A M is zero, Z = 1
"P" Register: N, V, Z
(M,)(M 6 )

BBR If specific bit of zero page is a reset state, branch
relatively.
3-byte
/ OP-Code / Low Order Address J Offset /
instructi on
If the specific bit (a bit is decided on the instruction
code) of effective address / 00 / Low Order Address /
is a reset state, relative branch by the Offset value
on the basis of lead address of next instruction.
Operation: branch When Mb = 0
"P" Register: Not affected

BMI Branch if result is negative.
Operation: branch when N = 1
"P" Register: Not affected
BNE Branch if result is not zero.
Operation: branch when Z = 0
"P" Register: Not affected

BBS If specific bit of zero page is a set state, branch relatively.
/ OP-code / Low Order Address / Offset /
3-byte
instruction
If the specific bit (a bit is decided on the instruction
code) of effective address 00 / Low Order Address /
is a set state, relative branch by the Offset value
to base with lead address of next instruction.
Operation: branch when Mb = 1
"P" Register: Not affected

I

I

BPL Branch if result is positive.
Branch if result is positive.
Operation: branch when N lo; 0
"P" Register: Not affected

I

BRA Unconditional branch.
"P" Register: Not affected

-IIO©®IJ[]----------'---------4-16

RP65C02 G/G-06

BRK Forced break
Operation: Execute the interrupt. In this instruction,
a lead address (2·byte) of next instruction is stored
in the stack. At the same time, it is stored into
Program-counter
contents of "P" Register.
(FFFE) -+ PCl, (FFFF) -+ PCH, and Execution
of program is same vector address with IRO. The
difference from the IRO interrupt is that in the
BKK operation, the B flag of "P" register is set
"1" and can't mask by the I flag.
"P" Register:

~

BVC Branch if the overflow flag is reset.
Operation: branch when V = 0
"P" Register: Not affected
BVS B.ranch if the overflow flag is set.
Operation: branch when V = 1
"P" Register: Not affected

CPY Compare memory with the index register Y.
Operation: YoM
Flag condition of "p" Register is the same as CMP.
"p" Register: N, Z, C
DEC Decrement the contents of memory.
Operation: M-1 -+ M
"P" Register: N, Z
DEX Decrement the contents of index register X.
Operation: X-1 -+ X
"p" Register: N, Z
DEY Decrement the contents of index register Y.
Operation: Y-1 -+ Y
"p" Register: N, Z
EOR Execute the exclusive OR of memory and accumulator
Operation: A M -+ A

ClC Clear the carry flag (C).

"P" Register: N, Z

Operation: 0 -+ C
"p" Register:

8

"P" Register:

~

ClD Clear the decimal mode.
Operation: 0 -+ C

Cli Clear the interrupt disenable flag (I).
Operation: 0 -+ I
"P" Register: ~
ClV Clear overflow flag.
Operation: 0 -+ V
"p" Register: ~
CMP Compare memory with accumulator.
Operation: A-M
The result is not stored. If it is negative, N flag is
set 1. If it is positive, C flag is set 1. And if it is
zero, Z and C flags are respectively 1..
"p" Register: N, Z, C
CPX Compare memory with the'index registerX.
Operation: YoM
Flag condition of "p" Register is the same as CMP.
"p" Register: N~ Z, C

INC Increment the contents of memory.
Operation: M+1 .... M
"p" Register: N, Z
INY Increment the contents of index register Y.
Operation: Y+1 -+ Y
"p" Register: N, Z
JMP Execution of program jumps to designation address.

I

I

I

Operation: lOP-Code Operand Operand
The designation address by operands with 2-bytes
is placed in PCl and PCH.
"p" Register: Not affected
JSR The execution of program jumps to designation
address.
Operation: When jump to designation address, return
address (lead address of next instruction) is stored
into stack. The return is executed by RT5.

I

I

I

lOP-Code Operand Operand
The disignation address by operands with 2-bytes
is stored into the PCl and PCH.
lead address of next instruction (2-byte)
I -+ Ms, 5-1 -+ 5
L... Ms, 5-1 -+ 5 "P" Register: Not affected

-------------'----IIO©®[}{]-

I

RP65C02 G/G-06

LOA Load the contents of memory to the accumulator.
Operation: M -+ A

PLP Pull processer status from stack.

"P" Register: N, Z

Operation: Ms -+ P, S + 1 -+ S
"P" Register: Restore

LOX Load the contents of memory to index register X.
Operation: M -+ X

PLX Pull X register from stack.
"P" Register: N, Z

Operation: Ms -+ X, S + 1 -+ S
"P" Register: N, Z

LOY Load the contents of memory to index register Y.
Operation: M -+ Y

PL Y Pull Y register from stack.
"P" Register: N, Z

Operation: Ms -+ Y, S

+ 1 -+ S
"P" Register: N, Z

LSR One bit right shift. MSB (7 bit) is placed to 0, LSB
(0 bit) is loaded the C.
Operation: 0 -+ '::-!7:;"!6':':!~5!-4r-!3"-!2-r!1-o!......,0! -+ C
"P" Register:

RMB Reset the specific bit in the zero page address.
1OP·Code 1 Low Order Bit 1 2·byte instruction

~, Z, C

The specific bit (a bit is decided by the instruction
code) of execution address 1001 Low Order Address!
is reset.

NOP No·operation
Operation: No operation
"P" Register: Not affected

Operation: 0 -+ Mb
"P" Register: Not affected

ORA Logical OR of memory and accumulator. The result

ROL Rotate left circular of one bit. The contents of the

is stored into the accumulator.
Operation: A M -+ A

MSB are moved into the C, the contents of the Care
moved into the LSB.
Operation: yr;=7;:'16:;:15:;:1::;41=3:;::12=11::;:1=0;-F@j=J-;:c=;-i

"P" Register: N, Z

"P" Register: N, Z, C
PHA Store the contents of .the accumulator into the memo
ory stack.
Operation: A ..... Ms, S-1 -+ S

ROR Rotate right circular of one bit. The contents of the
C are moved into the MSB, the contents of the LSB

"P" Register: Not affected

are moved into the C.
Operation: r;q

=7;:::16:;:15~1:::;41=3:;::12:;::1::;11=0::-HDJ-;:::c=;-

PHP Store the contents of the register P into the stack.

"P" Register: N, Z, C

Operation: P -+ Ms, S-1 -+ S
"P" Register: Not affected

RTI

Return from interrupt. The return address in stack is
loaded into the program counter, and it becomes the

PHX Store the contents of the index register X into the

lead address of a next instruction of the interrupt.
Operation: Ms -+ P,

stack.
Operation: X -+ Ms, S-1 -+ S
"P" Register: Not affected

S + 1 -+ S

Ms -+ PC L, S + 1 -+ S
Ms .... PCH, S + 1 -+ S
"P" Register: Restore

PHY Store the contents of the index register Y into the
stack.
Operation: Y -+ Ms, S-1 -+ S

RTS Return from subroutine.
The return address in stack is loaded into the program

"P" Register: Not affected

counter .It becomes the lead address of a next in·
struction of the JSR.
Operation: Ms -+ PCL, S + 1 -+ S
Ms -+ PCH, S + 1 -+ S

PLA Pull accumulator from stack.
Operaton: Ms -+ A, S + 1 -+ S
"P" Register: N, Z

"P" Register: Not affected

-IIO©®OO-------------4-18

RP65C02 G/G-06

SBC Subtract memory and borrow from accumulator, and

TAX Transfer the contents of the accumulator to the

the result is stored into the accumulator.
Operation: A - M - C'" A

index register X.
Operation: A -+ M
"P" Register: N, Z

C = borrow
"P" Register: N, V, Z, C

TAV Transfer the contentlr of the accumulator to the

index register V.
Operation: A'" V

SEC Set carry flag.

Operation: 1 -+ C
"P" Register:

f

"P" Register: N, Z
TRB Reset the contents of memory by accumulator, and

SED Set decimal flag.

test at the same time.
Operation: A f\. M'" M
If the result is zero, Z flag =1
"P" Register: Z

Operation: 1'" D
"P" Register: ~
SEI

Set disable interrupt status.
Operation: 1 -+ I
"P" Register:

~

TSB Set the contents of memory by accumulator, and test

at the same time.
Operation: A V M ... M

5MB Set the specific bit of zero page address.

I OP·Code I Low Order Bit I 2-byte instruction

If the result is zero, Z flag = 1
"P" Register: Z

It sets the specific bit (a bit is decided on the instruction code) of effective address

I00 I Low Order Address I

TSX Transfer stack pointer to the index register X.

Operation: S -+ X

Operation: 1'" Mb

"P" Register: N, Z

"P" Register: Not affected
STA Store the contents of the accumulator into the

TXA Transfer the contents of the index register X to the

accumu lator.
Operation: ·X ... A

memory.
Operation: A -+ M

"P" Register: N, Z

"P" Register: Not affected
STX Store the contents of the index register X into the

TXS Transfer the contents of the index register X to stack

pointer.
Operation: X -+ S

memory.
Operation: X -+ M

"P" Register: Not affected

"P" Register: Not affected
STY Store the contents of the index register Y into the

TVA Transfer the contents of the index register Y to the

accumulator.
Operation: y ... A

memory.
Operation: Y -+ M

"P" Register: N, Z

"P" Register: Not affected
STZ Clear the contents of memory.

Operation: 0'" M
"P" Register: Not Affected

--------------ltD©®OO4-19

I

RP65C02 G/G-06

• DETAILED INSTRUCTION OPERATION
ADDRESS MODE

CYCLE

Immediate
IMM
LDA(A9), AND(29), ORA(09), EOR(49), CMP(C9),
BIT(89), ADC(69), SBC(E9), LDX(A2), LDY(AO),
CPX(EO), CPY(CO)
2a

Absolute

ABS

LDA(AD), STA(8D), ADC(6D), SBC(ED), AND(2D),
ORA(OD), EOR(4D), CMP(CD), BIT(2C), LDX(AE),
LDY(AC), STX(8E), STY(8C), CPX(EC), CPY(CC),
STZ(9C)
ABS
2b Absolute (R-M-W)
TRB(lC), TSB(OC), LSR(4E), ASL(OE), ROL(2E),
ROR(6E), INC(EE), DEC(CE)

2
(l)2a

Absolute (JUMP)

2d

Absolute (Jump to subroutine)

3a

LDY(A4), STX(86), STY(84), CPX(E4), CPY(C4),

PC+1

ID

PC+2

10

PC

OP CODE
AAL

3
4
(1)4a

PC+2
AA

AAH
DATA

110

PC+3

10

1

PC

OP CODE

PC+1
PC+2

AAL

AA

DATA

6

AA
AA

10
DATA

PC

OP CODE

2

PC+1

3

PC+2
NEW PC

PCL
PCH

2
3
4

AAH
1
0

1

OP CODE
OP CODE
NEW PCL

3

PC
PC+1
01,S

10

1

4

01,S

PCH

5
6

01,S-1
PC+2

PCL+2
NEW PCH

0
0

1

NEW PC

OP CODE

1

PC

OP CODE

1

2

PC+1
OO,BAL

BAL
DATA

1
110

PC+2

10

2

Zero Page
ZP
LDA(A5), STA(85), ADC(65), SBC(E5), AND(25),
ORA(05), EOR(45), CMP(C5), BIT(24), LDX(A6),

OP CODE

PC+1

1

ABS

JSR(20)

PC

R/W

1

ABS

JMP(4C)

DATA BUS

2

5

2c

ADDRESS BUS

3
(1)3a

STZ(64)
3b

Zero Page (R-M-W)
ZP
TRB(l4), TSB(04), LSR(46), ASL(06), ROL(26),
ROR(66), INC(E6), DEC(C6)

-IID©®OO
4-20

1

PC

2

PC+1

OP CODE
BAL

3
4

OO,BAL

DATA

OO,BAL

10

1

5

OO,BAL

DATA

0

RP65C02 G/G-06

CYCLE

ADDRESS MODE
4

ACC
Accumulator
LSR(4A), ASL(OA), ROL(2A), ROR(6A), INC(IA),

ADDRESS BUS DATA BUS

RIW

1
2

PC
PC+l

OP CODE
10

1
1

1
2

PC
PC+l

OP CODE
10

1

1
2
3

PC
PC+l
01,S

OP CODE
10
REG

1
1
0

2
3
4

PC
PC+l
01,S
01,S+1

OP CODE
10
10
REG

1
1
1
1

PC
PC+l
01,S
01,S+1
01,S+2
NEW PC
PC+l

OP CODE
10
10
NEW PCL
NEW PCH
10
OP CODE

1
1
1

PC
PC+l
01,S
01,S+1
01,S+2
01,S+3
NEW PC

OP CODE
10
10
P
NEW PCL
NEW PCH
OP CODE

PC

OP CODE
10
PCH

DEC(3A)
5a

Implied
IMP
SEC(38), CLC(18),
CLD(D8), CL V(B8),
DEX(CA), DEY(88),
TYA(98), TSX(BA),

SEI(78), CLI(58), SED(F8),
NOP(EA), INX(E8), INY(C8),
TAX(AA), TXA(8A), TAY(A8),
TXS(9A)

5b

IMP
Implied (Stack Push)
PHA(48), PHP(08), PHX(DA), PHY(5A)

5c

IMP
Implied (Stack Pull)
PLA(68), PLP(28), PLX(FA), PLY(7A)

5d

5e

5f

Implied (Return from subroutine)
RTS(60)

Implied (Return from interrupt)
RTI(40)

1
2
3
4
5
6

IMP

1
2
3
4
5
6
1

IMP

1
2
3
4
5
6
7

IMP
Implied (Interrupt)
BRK(OO), RES, IRQ, NMI

• RESET: "I"
•• BRK: PC + 1
••• BRK: PCL+ 2

PC**
01,S
01,S-1
01,S-2
VA
VA+l
AAV

PCL***
P
AAVL
AAVH
OP CODE

1
1

1

1
1
1

1/0*
1/0*
110*
1

ItO@®[]{]4-21

I

RP65C02 G/G-06

ADDRESS MODE
6

7

8a

8b

9

Indexed Indirect
(IND, X)
LDA(A1), STA(81), ADC(61), SBC(E1), AND(21),
ORA(Ol), EOR(41), CMP(C1)

Indirect Index
(IND), Y
LDA(B1), STA(91), ADC(71), SBC(F1), AND(31),
ORA(ll), EOR(51), CMP(Dl)

Zero Page Index X
ZP, X
LDA(B5), STA(95), ADC(75), SBC(F5), AND(35),
ORA(15), EOR(55), CMP(D5), BIT(34), LDY(B4),
STY(94), STZ(74)

Zero Page Index X (R-M-W)
ZP, X
LSR(56), ASL(16), ROL(36), ROR(76), INC(F6),
DEC(D6)

Zero Page Index Y
LDX(B6), STX(96)

ZP, Y

lOa Absolute Index X
ABS, X
LDA(BD), STA(9D), ADC(7D), SBC(FD), AND(3D),
ORA(lD), EOR(5D), CMP(DD), BIT(3C), LDY(BC),
STZ(9E)

CYCLE

ADDRESS BUS

DATA BUS

R/W

1

PC

OP CODE

2

PC+1

BAL

3
4

PC+1
OO,BAL+X

AAL

5

00,BAL+X+1

6
(1)6a

AA

AAH
DATA

1/0

PC +2

10

1

PC

OP CODE
IAL

1

AAL

1

2

PC+1
OO,IAL

10

3
4
(4)(2)4a

00,IAL+1

10

5
(1)5a

AA+Y
PC+2

DATA

PC

OP CODE

2

PC+1

BAL

3
4
(1)4a

PC+1
OO,BAL+X

DATA

PC +2

10

00,IAL+1

AAH

1/0

10

10
1/0

1

PC

OP CODE

2

PC+1

BAL

3
4

PC+1
OO,BAL+X

DATA

5

OO,BAL+X

10

1

6

OO,BAL+X

DATA

0

10

1

PC

OP CODE

2

PC+l

BAL

3
4

PC+1
OO,BAL+Y

DATA

10
1/0

1

PC

OP CODE

2

PC+1

3
(4) (2)3a

PC+2

AAL
AAH

PC+2
AA+X

DATA

1/0

PC+3

10

1

4
(1)4a

10

-IIO@oooo------------4-22

RP65C02 G/G-06

ADDRESS MODE

CYCLE

lOb Absolute Index X (R-M-W)

ABS, X
LSR(5E), ASL(lE), ROL(3E), ROR(7E), INC (FE),
DEC(DE)

11

12

Absolute Index Y

ABS, Y

1

PC

OP CODE

2

PC+1

AAL

3
(2)3a

PC+2

AAH

PC+2

10

4

AA+X

DATA

5

AA+X

10

1

5

AA+X

DATA

0

1

PC

OP CODE

PC+1

AAL

ORA(19), EOR(59), CMP(D9), LDX(BE)

3

PC+2

AAH

(4)(2)3a

PC+2

10

4

AA+Y

DATA

110

(l)4a

PC+3

10

1

1

PC

OP CODE

2
(3)2a

PC+1

off

PC+2

10

PC+2
PC+2+(off)

OP CODE

Relative

REL

(2)2b
(5)1

Indirect
IND
LDA(B2), STA(92), ADC(72), SBC(F2), AND(32),

2

ORA(12), EOR(52), CMP(D2)

Absolute Indirect

(IND)

JMP(6C)

15

R/W

2

BNE(DO), BVS(70), BVC(50), BRA(80)

14

DATA BUS

LDA(B9), STA(99), ADC(79), SBC(F9), AND(39),

BMI(30), BPL(lO), BCC(90), BCS(BO), BEQ(FO),

13

ADDRESS BUS

Absolute Indexed Indirect

10

PC

OP CODE
IAL

3

PC+1
OO,IAL

4

00,IAL+1

AAH

5
(l)5a

AA

DATA

1/0

PC+2

10

1

AAL

1

PC

OP CODE

2

PC+1

AAL

3

PC+2

AAH

4

PC+2

10

5

AA

PCL

6

AA+1
NEW PC

OP CODE

(IND), X

JMP(7C)

I

PCH

PC

OP CODE

2

PC+1

AAL

3

PC+2

AAH

4

PC+2

10

5

AA+X

PCL

6

AA+X+1

PCH

NEW PC

OP CODE

ICO©®DO4-23

RP65C02 G/G.,...06

ADDRESS MODE
16a Bit Addressing (R-M-W)
RMB(07-77), 5MB(87-F7)

CYCLE

ADDRESS BUS

DATA BUS

R/W

1
3
4

PC
PC+l
OO,BAL
OO,BAL

5

OO,BAL

OP CODE
BAL
DATA
10
DATA

0

2

16b Bit Addressing (Branch)
BBR(OF-7F), BBS(8F-FF)

1

PC

2

PC+l
OO,BAL
OO,BAL
PC +2

3
4
5
5a
5b

PC+3
PC +3
PC+3+off

OP CODE
BAL
DATA
10
off
10
IO
OP CODE

1

1
1
1
1
1
1
1
1

ABBREVIATIONS
AA

-L

Absolute Address

Lower 8 bit Address

10

Internal Operation

10

Immediate Data

REG

Data of Each Register (ACC, X, Y, P)

DATA

Memory Data

PC

Program CQunter

BAL

Base Address (Low)

S

Stack Address

off

Off-Set Data

VA

Vector Address

IA

Indirect Address

AAV

Absolute Address Vector

X,Y

Index Register

P

Processor Status Register

R-M-W

Read-Modify-Write

-H

Higher 8 bit Address

NOTE: (1) Add 1 cycle if decirnal rnode of ADC. SBC
(2) Add 1 cycle if page boundary is crossed
(3) Add 1 cycle if branch is taken
(4) Add 1 cycle for write
(5) PC+2 if branch is not taken

-IIU@([)OOI------------4-24

RP65C02 G/G-06

mm

• 40-PIN DUAL-IN-LINE PACKAGE (UNIT: -.- )
Inch

•
2.54TYP

o.48±O·1

.IOOTYP

.OI9±O.OO4

---------------IIO©®[}[]4-25

S.DSP

I

IPRELIMINARY I
EK-030-8905

Digital Signal Processor

RP5C72
The RP5C72 is a high-performance general-purpose digital signal processor (DSP). Its 32-bit internal
operation includes a 512-word data RAM (1 word = 16 bits), 4k-word ROM (1 word = 16 bits) that can
be assigned to both program and data areas, and a 32-bit multiplier (16 X 16 bits, fixed point operation).
It processes at 100 ns per instruction.
The index function of the memory has two sets of hardware (index units) that contain ALUs dedicated
to addressing, enabling operations required for various digital signal processing.
By changing software in the built-in program memory, the RP5C72 can be adapted to various applications.

• FEATURES
• Fast processing: 100 ns/instruction (for fck = 40 MHz)
.16 X 16 bits ~ 32-bit MPY/ACC built-in
• 32-bit width ALU built-in
.4-stage pipeline architecture

(Fixed decimal point operation)

.512 words X 16 bits RAM built-in (for data only)
.4 k words X 16 bits ROM built-in (mask programmable)
(for data and program)
• Repeat instruction function, HOLD function
• External interrupt/internal condition acknowledge

EVENT port (2 pins)
I/O port (2 pins)

• Two EVENT registers and one TIMER register built·in (l6-bit width)
• Serial I/O port (3-line X 1)
• Parallel I/O port (8-bit X 1)
• 2-layer metalCMOS process
• 28-pin D I L plastic package
• Power consumption: 630 mW (max.)

• APPLICATION
Fast MODEM

Echo canceller

Filter bank

Motor control

Digital filters

Voice composition/recognition
FFT

ADPCM

---------------IIO@®[}[]5-1

I

RP5C72
• BLOCK DIAGRAM

~

~

!

OSCILLATOR

~ INSTRUCTION
ADDRESS

CLOCK
GENERATOR

GENERATOR

11\

I I

STACK:
POINTER

I

~,

J;
UNIT 0

UNIT I

ADDRESS BUS 0

~

l

,II
INST. ADDR.

I\

CONTROLLER

I

INST.

J;

J;

ADDRESSO

ADDRESS I

I DATA ADDR.

DUAL PORT
INSTRUCTION!
DATA ROM
4096 x 16

I

DATA

DATAO

REGISTERS
INTERRUPT
MASK
STATUS

I
I

J

k:J REGISTER

II'

,II

\ JI

K

X

AH

MODE
DB

r

II

~ODE

t

28
27
26
25
24
23
22
21
20
19
18
17
16

10

]/0[1l

11

]/O[OJ
EVENT[!J
VSS

12
13
14

-ICD©®[]{]
5-2

~

I

~

PARALLEL
PORT

~

TIMER
EVENT
UNIT

Y

I

AL

11\

11\

1;

V

• PIN CONFIGURATION

YBCLK
CLOCK
XSTLl
XSTL2
RESET
HOLD
TEST
SO
SI
SCLK

SERIAL
PORT

bATA BUS I

ENGINE
16x 16 MPY!ADD
ALU!SHIFT
32

10 STATUS

~
DATA BUS 0

1[\

4

I DECODE

DATAl

t

1
INSTRUCTION
DECODE

ADDRESS BUS I

DUAL PORT
DATA RAM
512x 16

\I;

I
I

\

VDD
PORT [0]
PORT [1]
PORT[2]
PORT[3]
PORT[4]
PORT[5]
PORT[6]
PORT[7]
PAO

RP5C72
• PIN DESCRIPTION
Pin Name

Pin No.

I/O

VDD

28

I

+5 V power supply

VSS

14

I

GND

XSTL 1

3

I

System clock input (external clock input)
Connecting a crystal oscillator between XSTL 1 and XSTL2
structures an oscillation circuit. (An oscillation circuit is
built-in.)

XSTL 2

4

0

CLOCK

2

0

Internal clock output. Clock signal which is half frequency
of XSTL 1 is out from the CLOCK pin.

YBCLK

1

0

Internal instruction bus clock output. v.. of the XSTL 1 input
frequency. When HOLD is High, the output is fixed to the
Low level.

RESET

5

I

Reset input. Initializes the chip.
Sets bus mode, clears the MASK, INTR, STAT, 10STAT,
MODE, and DEBMODE registers, and initializes the serial/
parallel port.
Starts a program from the address of the values stored in
memory address' hOOOO.

(Schmit
Input)

HOLD

6

EVENT [0]

15

EVENT [1]

13

I/O [1]

11

I/O [0]

12

I

Description

Hold internal clock except for serial port, parallel port and
timer event unit.

I/O

EVENT/Compare I/O pin.
This pin can be programmed to input or output. Performs
sampling timing, real-time timer event, and timer value read.

I/O

Programmable I/O port pin.
Input : Senses external signals and generates interrupts to
DSP.
Output: For transfers of data written to internal MODE
register bits 2 and 3 to the outside.

SI

9

I

Serial port data input pin.
The input data synchronized with the SCLK Low timing is
an input enable signal (SIEN). The input data synchronized
with the SCLK High timing is SI data.

SO

8

0

Serial port data output pin.
The output data synchronized with the SCLK Low timing is
an output enable signal (SOEN). The output signal synchronized with the SCLK High timing is SO data.

---------------IIO©®[}[]5-3

I

RP5C72

Pin Name

Pin No.

I/O

Description

10

0

Serial clock output. Synchronized with the DSP internal
clock, 1/16 of the original oscillation frequency (XSTL1) is
output.
Example) When fck = 40 MHz, SCLK = 2.5 MHz (400 ns
cycle)

27-20

I/O

8-bit parallel port data pin.

17

I

Parallel port write strobe.
When PW = "L" and PCS

= "L", the PORT

Parallel port output enable.
WlienPOE = "L" and PCS

= "L", the PORT is output state.

SCLK

PORT 0PORT 7

PW
POE

16

I

is input state.

PCS

18

I

Parallel port chip select.

PAO

19

I

Parallel port address select.
When PAO = "L", selects the lower eight bits of the parallel
port register (l6-bit width)
When PAO = "H", selects the upper eight bits of the parallel
port register (16-bit width)

Parallel port control pin assignment

PCS fiDE PW

PAO

PORT[7] - PORT[O]

Selected register

0
0

0
0

1
1

0
1

0
0
0
0
1

1
1

0
0
0

0
1
x

1
x

x

Prohibition
Hi

No Transfer

x

Hi

No Transfer

0
1
x

Lower 8 bit read

Lower eight bits of parallel port output

Upper 8 bit read
Lower 8 bit write
Upper 8 bit write

Upper eight bits of parallel port output
Lower eight bits of parallel port input
Upper eight bits of parallel port input

-z
-z

x : Don't Care.
TEST

7

I
(Schmit
Input)

Test mode input. Using this terminal and the RESET pin
starts the test mode. Set to VDD level normally.

Note: Hi-Z: high impedance state

-IID©®(JO~-----------5-4

RPSC72
• ABSOLUTE MAXIMUM RATING
Symbol

Parameter

Vee

Supply Voltage

VI

Input Voltage

Vo

Output Voltage

PO

Power Consumption

Topr

Operating Temperature

Tstg

Storage Temperature

Condition

Vss

Ta

= OV

Ratings

Unit

-0.3-+7.0

V

-0.3 - Vee +0.3

V

-0.3 - Vee +0.3

V

1.0

W

0-70

°c

-40 - +125

°c

= 25°C

• RECOMMENDED CONDITIONS ITa = 0 - +70°C. Vss = OV)
Parameter

Min.

Typ.

Max.

Unit

Supply Voltage

4.75

5.0

5.25

V

Symbol
Vee

"H" Input
VIH

Voltage

"L" Input
VIL

Voltage

TTL Level

2.0

Vee +0.3

V

CMOS Level

3.5

Vee +0.3

V

Schmitt Input Level

2.4

Vee +0.3

V

TTL Level

-0.3

0.8

V

CMOS Level

-0.3

1.5

V

Schmitt Input Level

-0.3

0.6

V

--------------IIO©®Ol]5-5

I

RP5C72
• DC ELECTRICAL CHARACTERISTICS

(Ta=0-70°C, Vcc=5V±5%)

Parameter

Symbol

Condition

Min.

Typ.

Max.

Unit

III

Input Leakage Current

VIN = OV

~

Vee

-10

10

J.lA

ILO

Output Off Leakage Current

Vo = OV

~

Vee

-10

10

J.lA

VIH

"H" Input
Voltage

TTL Level

2.0

Schm itt I nput Level
(RESET, TEST)

2.4

Clock Input Level
(XSTL 1)

4.0

Vee

"L" Input
Voltage

+

V

0.3

TTL Level

VIL

V

V

-0.3

0.8

V

Schmitt Input Level
(RESET, TEST)

-0.3

0.6

V

Clock Input Level
(XSTL 1)

-0.3

1.0

V

VOH

"H" Output Voltage

Vee = Min
IOH = -0.4 mA

VOL

"L" Output Voltage

Vee = Min
IOL = 2mA

0.5

V

Icc

Operating Current

Vee = Max note)
VIN = Vss or Vee
fck = 40 MHz

120

mA

Max.

Unit

2.4

V

Note 1) Output pins are measured with output unloaded
Input pins are fixed in GND or Vcc .

• Capacitance
Symbol

(Ta = 25°C, f = 1 MHz)

Parameter

Condition

Min.

Typ.

CI

Input Capacitance

VIN = OV note 2)

5

pF

Co

Output Capacitance

VOUT=OV note 2)

7

pF

Note 2) This parameter is periodically sampled and not 100% tested.

-ICO®®OO-------------5-6

RP5C72
• ELECTRICAL CHARACTERISTICS
1.

Clock characteristics
RP5C72 can use both internal oscillation circuit (Crystal oscillation) and external oscillator
clock input.

1-(1) Internal clock circuit
The internal clock circuit starts oscillation when inserting a crystal oscillator between XSTL
1 and XSTL 2 pins.

fCK",20MHz

RP5C72
XSTLI
(IN)

R

XSTL2
(OUT)

I

20MHz o.

(PC) .... PC. n·1 .... n

if n

= O.

(PC) + 1 .... PC

n: lower 7-bits of the instruction code

(0;:; n;:; 127)
27.

MAC

FLAG:

Adds the accumulator and the result of multiplication

No change
1/1+1 (a)

A group

of the X and Y registers.
Operation:

28.

MACAX

(A) + (X) X (V) .... A. (PC) + 1 .... PC

FLAG:

Adds the X@O register (32·bit) and the result of
multiplicati'on of the upper 16·bits of the

V.C.N.Z
1/1+1(a)

A group

I

accumulator and the Y register.

Operation:

29.

MACK

FLAG:

Adds the X@O register and the result of multiplication
of the K and Y registers, and outputs to the accumulator.
Operation:

30.

(X @ 0) + (AH) X (V) .... A, (PC) + 1 .... PC

MSB

(X @ 0) + (K) X (V) .... A, (PC) + 1 .... PC

V,C,N,Z
1/1+1 (a)

FLAG:

Subtracts the result of multiplication of the X and V

A group

V,C,N,Z
1/1+1(a)

A group

registers from the accumulator.
Operation:

31.

MUL

(A) - (X) X (V) .... A, (PC) + 1 .... PC

FLAG:

Outputs the result of the multiplication of the X and V

V,C,N,Z,
1/1+1(a)

A group

registers to the accumulator.
Operation:

32.

33.

34.

OR

(X) X (V) .... A, (PC) + 1 .... PC

FLAG:

Logical add of the accumulator and the X@Y register.
Operation:

(A) OR (X @ V) .... A, (PC) + 1 .... PC

Operation:

(X @ 0) OR (V @O) .... A, (PC) + 1 .... PC

Operation:

(SP) + 1 -->SP, (SP) .... reg (All registers)

ORXV

PSH

FLAG:

Operation:

RTI

No change

1/1+1 (b)

FLAG:

Return from the interrupt routine.
Operation:

B group

B group

(reg) .... (SP), (SP) - 1 --> SP
(PC) + 1 .... PC

36.

A group

N,Z,B
1/1+(b)

Stores the register value in the stack.

A group

N,Z,B
1/1+1 (a)

FLAG:

Draws data from the stack to the register.

(PC) + 1 .... PC

35.

FLAG:

Logical add of the X@O register and the V@O register.

POP

V,N,Z
1/1+1(.)

No change
1/3

C group

(SP) + 1 .... SP
(SP) .... PC

FLAG:

No change

Return from the interrupt routine by storing the value
again from the stack pointer to the program counter.

IID©®OO5-19

RPSC72
37.

RTS

1/3

Return from subroutine

Operation:

C group

(SP) + 1 .... SP
(SP) .... PC

FLAG:

No change

Return from the subroutine by storing the value
again from the stack pointer to the program counter.

38.

Operation:
C

SHR

A group

(A) shift left I-bit -+ A, (PC) + 1 -+ PC
FLAG:

3rl__~1~6rl~5__~O

D--1
39.

1/1+1(a)

Accumulator value logical shift instruction
(I-bit to the leftl

SHL

AH

1

C. N, Z, B

1-0

AL

1/1+1 (a)

Accumulator value logical shift instruction

A group

(I-bit to the rightl
Operation:

(A) shift right I-bit -+ A, (PC) + 1 -+ PC
31

1616

"'::;1

@--jr----A-H '-;I=-A-L
40.

STIX

0

FLAG:

1/1

Index store from the fast register to the memory

Operation:

42.

FLAG:

Subtracts the X@V register value from the accumulator_

SUB
Operation:

(A) - (X@Y) .... A, (PC) + 1 .... PC

Operation:

If (A) - (X@Y)

SUBC

B group

(freg) .... (rO) + sx(ra)
(freg) .... (rll + sx(ra)

41.

C, N. Z, B

1/1+1(a)

FLAG:

(A) X 2 .... A, LSB

A group

V, C, N, Z, B

1/1

Conditions.1 subtract instruction

< O.

No change

A group

=0

If (A) - (i(@y) ;?; 0, [(A) - (X@YIl X 2 -+ A

FLAG:

V,C.N,Z

LSB= 1

(Division) Using the loop instruction and SUBC in combination,
the division results (quotient and remainder) can be
obtained by the accumulator.
31

I

43.

SUBI

45.

46.

I

0

AL (quotientl

I

result of division

Subtracts the accumulator value from the X@Y register_
Operation:

44.

1615

AH (remainder)

SUBXY

(X @ V) - (A) .... A, (PC) + 1 .... PC

1/1+1(a)

FLAG:

1/1+1(a)

Subtracts the V@O register value from the X@O register.
Operation:

(X @O) - (V @ 0) .... A, (PC) + 1 .... PC

Operation:

(V @ X) - (X @ 0) .... A, (PC) + 1 .... PC

Operation:

(reg) .... reg, (PC) + 1 .... PC

FLAG:

Subtracts the X@O register value from the V@O register.

SUBYX

XFR

FLAG:

A group

V, C, N, Z, B
1/1+1(b)

Data transfer instruction between any registers

A group

V, C, N, Z, B
1/1+1(a)

FLAG:

A group

V, C, N, Z, B

B group

No change

reg is all registers (l6-bit width).
47.

XOR

Exclusive logical add of the accumulator and
the X@V register
Operation:

48.

XORXY

(A) XOR(X @ V) .... A, (PC) + 1 .... PC

1/1+1(a)

FLAG:

Exclusive logical add of the X@O register and
the V@O register
Operation:

(X @ 0) XOR (V @ 0) .... A, (PC) + 1 .... PC

N, Z, B
1/1+1(a)

FLAG:

A group

A group

N, Z, B

-IIO®®[]{]-----------~5-20

RP5C72
• INSTRUCTION SET SUMMARY

( A) Arithmetic/L()gic Instruction
MNEMONIC WORDS CYCLES
ENOP
ADD
ADDXY
SUB
SUBXY
SUBI
SUBYX
SUBC

1
1
1
1
1
1
1
1

1 +l(a)
1 +l{a)
1 +1 (a)
l+l{a)
1+I(a)
1 +1 (a)
l+l{a)
1

MUL
MAC
MACAX
MACK
MSB
AND
ANDXY
OR
ORXY
XOR
XORXY
SHR
SHL

1
1
1
1
1
1
1
1
1
1
1
1
1

1+I(a)
1+I(a)
1+I(a)
l+1(a)
1 +l{a)
1+I(a)
1 +l(a)
1 +l{a)
1 +l{a)
1 +1(a)
1 +l{a)
1 +1 (a)
1+I(a)

Instruction Bit Pattern
DESCRIPTION

OPERANDS

Inelexing only
A +- (A) + (X@Y)
A+- (X@O)+(Y@O)
A+- (A)-(X@y)
A+- (X@O)-(Y@O)
A+- (X@Y)-(A)
A+- (Y@O)-(X@O)
If (A)-(X@Y)(O then (A)*2-) A.LSB=O
(A)-(X@Y)20 then (A-X@Y)*2-+A,
LSB=1
The Result AH = the re""ineler
AL = the quotient
A +- (X) * (Y)
A +- (A) + (X) * (Y)
A+- (X@O)+(AH)*(y)
A+- (X@O)+(K*y)
A +- (A) - (X) * (Y)
A +- (A) AND (X @ y)
A+- (X@O)AND(Y@O)
A +- (A) OR (X@Y)
A+- (X@O) OR (Y@O)
A +- (A) XOR (X@Y)
A+- (X@O) XOR (Y@O)
A +- (A) SHR 1 (right)
A +: (A) SHL 1 (left)

(eidx)
(eidx)
(eidx)
(eidx)
(eidx)
(eidx)
(eidx)

----

15 14 13 12 1110 9 8 7 6 5 4 3 2 1 0
0
0
0
0
0
0
0
I

0
0
0
0
0
0
0
1

0
0
0
0
1
1
1
0

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
0

f---eidx
~
f---eidx
~
f---eidx
~
f---eidx
~
f---eidx
~
f---eidx
~
f---eidx
~
10111000010

0
0
0
0
0
0
0
0
0
1
1
1
1

0
1
1
1
1
1
1
1
1
0
0
0
0

1
0
0
0
0
1
1
1
1
0
0
0
0

1
0
0
1
1
0
0
1
1
0
0
1
1

1
0
1
0
1
0
1
0
1
0
1
0
1

f---eidx
f---eidx
f---eidx
f---eidx
f---eidx
f---eidx
f---eidx
f---eidx
f---eidx
f---eidx
f---eldx
f---eidx
f---eidx

-(eidx)
(eidx)
(eidx)
(eidx)
(eidx)
(eidx)
(eidx)
(eidx)
(eidx)
(eidx)
(eidx)
(eidx)
(eidx)

(B) Load/Store Instruction
MNEMONIC WORDS CYCLES
2+1(b)

STiX

1

1

XFR

1

1+I(b)

PSH

1

1 +l{b)

POP

1

1+I(b)

Pop reg. from stack

2

LDB

1

1 +l(b)

LDiX

1

1 +1 (b)

~
~
~

l
~
~

l
~
~

l
~

l

Instruction Bit Pattern
DESCRIPTION

Load 16_bit immediate value into
register.
Load 8_bit immediate value into
fast register with sign extend.
Indexed load to fast register.
(freg)
Indexed store to fast register.
(freg)
Register transfer, any registers.
SIC -) dst (SIC and dst are reg)
Push reg. onto stack.

LDW

~

OPERANDS
(const 16) (reg)

15 14 13 12 1110 9 8 7 6 5 4 3 2 1 0

(const 8) (freg>

1 1 0 1 0 1 0 1 0 1 0 ~reg~
~
imm 16
J 1 0 Of-freg-l ~imm 8----}

(dir. Ix) 

1 1 0 1 0 1 0 1 0 0 1 ~reg--l


Idx

Bit Pattern
10 9 8 7 6 5 4 3 2 1 0

Assembler Syntax
(eidx)

------------------(y index) (x index)

e e e e e e e e e e e

-- - - - - -- -- - -- ------ - - ------

(const 8)
x
(const 8)
y
(rO, (const 7» x
(d, (const 7» y
ah (rO, (const 7»
ah (d, (const 7»

0
1
1
1
1
1
I

Y Y Y Y Y x x x x. x
0 0 I I I I I I I I

0
1
1
1
1

(direct Ix)

1
0
0
1
1

1
0
1
0
1

1
I
I
I
I

I I 1 1
I I I I
I 1 I I
I I I I
I I I 1

u u u u u u u u u

0
0
1
1

(d, (const 7»

1
I
1
I

I
I
I
I

I
I
I
I

I
I
I
I

I
I
I
I

I
I
I
I

-- --- --- - - ---------------- - -----Two field. of five bit•.
X +- .x(imIrt8)
Y. +- sx(imm8)
X +- (rO + sx(ldx7»
Y +- (d + sx(ldx7»
(rO + sx(idx7» +- AH
(d + sx(ldx7» +- AH

I I
I 1
I I
I I
I I

------- --.---------- -- ... ------- -- - ----------------(rO, (const 7»

Description.

I
I
I
I

---- - ---- -- ---- ----- ------- ---- ---

I
I
1
I

= N.B. = sx -)

freg +- (rO + sx(ldx7»
(rO + sx(ldx7» +- freg
freg +- (d + sx(ldx7»
(d + sx(ldx7» +- freg

: LDIX
: STIX

Sign extend

- EDUAL (engine dual) INDEXING DESCRIPTION
Mnemonic

Pattern

Description

(y index)

(x index)

yyyyy
xxxxx

Description for (x index)

nopl
Oy
-ly
!pl+
!pl!pl+1
!pl+r
!plc

nopO
Ox
-Ix
!pO+
!pO!pO+1
!pO+r
!pOc

00000
00010
00110
00001
00111
00011
00100
00101

ah(pl)
ah(d)
ah(tl)
ah(pl +1)
ah(pl +r)
ah(!plc)

ah(pO)
ah(rO)
ah(tO)
ah(pO+I)
ah(pO+r)
ah(!pOc)

01000
01001
01010
01011
01100
01101

ah(!pl +1)
ah(!pl +r)
(pi )y
(tl)y
(d)y
(pi +)y
(pi ++)y
(pl-)y
(pl--)y
(pl+l)y
(pi +r)y
(!pl+)y
(!pl ++)y
(!pl- )y
(!pl --)y
(!pl +I)y
(!pl +r)y
(!plc)y

ah(!pO+I)
ah(!pO+r)
(pO)x
(to)x
(rO)x
(pO+)x
(pO++)x
(pO -)x
(pO--)x
(pO+l)x
(pO+r)x
(!pO+)x
(!pO++)x
(!pO-)x
(!pO--)x
(!pO+I)x
(!pO+r)x
(!pOc)x

01110
01111
10000
10101
11000
10001
10010
10111
10110
10011
10100
11001
11010
11111
11110
11011
11100
11101

Mnemonic

no operation for IUO
x+-O
x +--1
pO+-pO+l
pO+-pO-l
pO+-pO+IO
pO+-pO+rO
if pO = to then pO +- rO,


Ai(i=0~14)

CE

tACC

IcE

I

/

,-------

OE

>

--------

--'\

,(

,----tOF

- - - - - - - - - - - - ______ 1

OE

I
----

tOE
tOH

ILL
\\\

Oi(i=0~7)

,\\

Valid Data

'II

-CAPACITANCE
Symbol

Parameter

Ci

Input Capacitance

Co

Output Capacitance

Condition

Min.

Typ.

Max.

Unit

-

f = 1MHz

10

pF

12

pF

-----------------ICO©®OO6-3

RP/RS53256E

•

PACKAGE DIMENSION (Unit: mm/inch)

e28PIN DIP (RP53256E)
37.8max
1.488max

28

15

~n~- _-

-

~ ~

~~~~,">r~~~~. .~~

15.24""
.600 TYP

14

.~.~

1,j 1,j

r----------------,-~ 0 - E E-

~ ~

o

2.54 TYP
.100 TYP

..

II • 0.48
,019

.

~
lri

8~

±01

±O.004

e28PIN SOP (RS53256E)

1031 ±0.3
.406 ±O.O12

14

~ ~

_~~8~

". C\J
OJ m

C\l q

dq

\JUUL . . JUUUL JLJUUU_

.!J
_ 8

1.27TYP
.050 TYP

0.41 ~g:65
,016 ~8:gg~

7.47 TYP
.294 TYP

+I +I
In 0
C\J ~

\\.

II 0.66
~

~ ~
C\J co
'0
o ~

±02

-ICD®CID[)[]----------------6-4

~IC~D~@~®~OO~~~/ CMOS 1Mbil MASK RO'~~"'~
RP/RS531 01 OE

(131,072 word x 8 bit)

• PIN CONFIGURATION
RP/RS531 01 OE is a 1 Mbit programmable mask

NC
A16
A"
Au
A,
A.
A,
A.
A3
A2
A,
Ao
00
0,

ROM using CMOS process technology.
It has also been provided with a power down
function which reduces supply current from
30mA (Max.) to 1001.1 A (Max.) by setting the
CE input to the .. H " level.
In addition, the logic level of the output enable
can be selected from among three types of logic
levels, ACTIVE HIGH, ACTIVE LOW and ISOLATED.

(TOPVIEW)

32

Vee

31

OE1/0El/NC
OE2/0E2/NC

30

A.
Al1

• FEATURES
1.

Organization: 131072 words x 8 bits

2.

Access Time : 200 ns

3.

TIL Compatible Input/Output

4.

Single 5V Power Supply

5.

Power Consumption:
operation
standby

• PIN DESCRIPTION

165 mW (Max.)
O. 55 mW (Max.)

6.

3 - state Output

7.

Package: RP531010E'
RS531 01 OE •

Pin Name
Ao-A16

Function
Address Input

00-07
OE/OE

Output Enable Input

OE1/0E1

Output Enable Input

-

. 32 pin DIP
. 32 pin SOP

Data Output

OE2/0E2

Output Enable Input

CE

Chip Enable Input

Vce

Power Supply (+ 5V)

GND

Ground

NC

No connection

CE_
OE/OL
OE1/0El
OE2/0E2
Memory Cell

(13l072word X8bit)

Timing Control Circuit

----------------IID®®[l[]6-5

I

RP/RS531 01 OE

• ABSOLUTE MAXIMUM RATING
Parameter

Symbol
Vee

Supply Voltage

VI

Input Voltage

Vo

Output Voltage

Pd

Power Consumption

Topr

Operating Temperature

Tstg

Storage Temperature

Condition

Limit
- 0.3

With respect to GND

Unit
7

V

- 0.3

~

Vee + 0.5

V

- 0.3

~

Vee + 0.3

V

Ta = 25'C

~

mW

210
70

o~
- 40

'C

~125

'C

• RECOMMENDED OPERATING CONDITION (Ta=0~70'C)
Symbol

Parameter

Min.

Typ.

Max.

Unit

Vee

Supply Voltage

4.5

5.0

5.5

V

VIH

" H " Input Voltage

2.2

Vee

V

VIL

" L" Input Voltage

0

0.8

V

• ELECTRICAL CHARACTERISTICS
• DC ELECTRICAL CHARACTERISTICS (Ta=0~70'C, Vee=5V± 10%)
Parameter

Symbol

Condition

Min.

10= 0 rnA. CE =2.2V

ISbl

Supply Current (Standby)

ISb2

Supply Current (Standby)

Total input = 2.2Vor 0.8V

Typ.

Max.

Unit

3

rnA

0.1

rnA

30

rnA

10

rnA

10=0 rnA. CE=Vee-0.2V
Total input=Vee-0.2Vor

\
leel

Supply Current (Operation)

GND+0.2V

10= 0 rnA, tRe = 200 ns
tRe= 1Ils(CL=100PF)
CE , OE = GND + 0.2V

lee2

Supply Current (Operation)

VOHl

" H " Output Voltage

10H=-0.4mA

2.4

V

VOH2

" H " Output Voltage

10H = -0.1 rnA

Vee x 0.8

V

VOL

" L" Output Voltage

10L =

VIH
VIL

" H" Input Voltage
L Input Voltage

III

Input Leakage Current

V IL = GND +0.2V
V IH = Vee -0.2V

ILo

II

3.2 rnA

II

Output Leakage Current

VI = OV
Vo =

~

Vee

OV~

Vee

Chip Deselected

0.4

V

2.2

Vee

V

-0.3

0.8

V

- 10

10

IlA

- 10

10

IlA

-ICD©®[)o---------------6-6

RP/RS531 01 OE

• AC ELECTRICAL CHARACTERISTICS (Ta=0~70'C, Vcc=5V± 10%)
Parameter

Symbol

Max.

Typ.

Min.

Unit
ns

tRC

Read Cycle Time

tACC

Address Access Time

200

ns

tCE

Chip Enable Access Time

200

ns

tOE

Output Enable Access Time

80

ns

tDF

Output Floating Delay Time

0

80

ns

tOH

Output Hold Time

0

200

Input Voltage

: V IL = 0.6V,

Output Load

: 1 TTL

Measuring Voltage

: V IL = 0.8V,

+

VIH = 2.4V,

ns
tr. tf = IOns

100 pF
VIH = 2.2V, VOL = 0.8V,

VOH = 2.2V

• TIMING CHART
tRC

Ai(i

>

=0~16)

tAcc

tCE

I

V

CE
OE

)

/-------

--------

--,

OE

I

k' ---------\

- - - - - - - - - - - - ______ 1

to,

tOE
tOH

III
\\\

Oi(i=0~7)

,\\
'II

Valid Data

NOTE
(Valid data after power on )
After power on, with CE set to GND level, valid data output will be sent after IAcc, from a change in at least one address input.
If other than the above parameters, the valid data output will be sent after tCE due to the CE rise pulse.

• CAPACITANCE
Symbol

Parameter

Ci

Input Capacitance

Co

Output Capacitance

Condition
f = 1MHz

Min.

Typ.

Max.

Unit

10

pF

15

pF

-----------------ICD©®OO6-7

RP/RS531010E

• PACKAGE DIMENSION

(Unit:mm/inch)

• 32PIN DIP (RP531 01 OE)

15.24'yp

16

PIN#1

2.54 TYP
. •

(.100 TYP )

II

0.48 ±o,
• (.019 ±o'''''')

• 32PIN SOP (RS531 01 OE)

32

20.9max.
(0.823max.)

17

141 ±O.3

16

(0.555 ±o.o>')

~~8
0e•

11.3 TYP
(0.445 TYP

+

'"
~ co
0

'0

jj

)

\\,

ii

0.8 TYP
• • (0.031 TYP)

~ICD®®OO-~~~~--~~~~~~~~~~~

6-8

~IC!,!!!!!,!!,!!D!'!!!!!'!!'!!©~®~O{]~~~I CMOS 2Mbit MASK RO';;"·RP/RS532010E

(262,144 word x 8 bit)

RP/RS532010E is a 2 Mbit programmable

•

PIN CONFIGURATION

•

PIN DESCRIPTION

(TOP VIEW)

mask ROM using CMOS process technology.
It has also been provided with a power down
function which reduces supply current from
50 mA (Max,) to 100 Il A (Max,) by setting the
CE input to the .. H " level.
In addition, the logic level of the number 31 pin
output enable can be selected from among three
types of logic levels, ACTIVE HIGH, ACTIVE LOW
and ISOLATED. Further the logic level of the
number 24 pin output enable can be specified from
among two types either ACTIVE HIGH or ACTIVE
LOW.

• FEATURES

(TOP VIEW )

1.

Organization: 262144 words x 8 bits

2.

Access Time: 200 ns

Pin Name
Ao-A17

Function
Address Input

3.

TTL Compatible Input/Output

00-07

Data Output

Single 5V Power Supply

OE/OE

Output Enable Input

Power Consumption :

OE1/0E1

Output Enable Input

CE

Chip Enable Input

Vcc

Power Supply ( + 5V)

GND

Ground

NC

No connection

4.
5.

operation

275 mW (Max.)

standby O. 55 mW (Max,)
6.

3 - state Output

7.

Package: RP532010E •
RS532010E •

. 32 pin DIP
. 32 pin SOP

Ao
At
A,
A,
A.
A,
A.
A17

CE
OE/OE
OE1/0El
Memory Cell
(262l44word x 8bit)

Timing Control Circutt

----------------ICD®®T]{]6-9

I

RP/RS532010E

• ABSOLUTE MAXIMUM RATING
Symbol
Vee

Parameter

Condition

Limit

Supply Voltage

VI

Input Voltage

Vo

Output Voltage

Pd

Power Consumption

Topr

Operating Temperature

Tstg

Storage Temperature

With respect to GND

Unit
7

V

- 0.3 -

Vee + 0.5

V

- 0.3 -

Vee + 0.3

- 0.3 -

Ta = 25°C

V
mW

350
0-70

°C

- 40 -125

• RECOMMENDED OPERATING CONDITION

°C

(Ta=0-70°C)

Symbol

Parameter

Min.

Typ.

Max.

Unit

Vee

Supply Voltage

4.5

5.0

5.5

V

VIH

" H " Input Voltage

2.2

Vee

V

VIL

" l " Input Voltage

0

0.8

V

• ELECTRICAL CHARACTERISTICS
• DC ELECTRICAL CHARACTERISTICS (Ta=0-70°C, Vee=5V±10%)
Symbol

Parameter

Condition

Min.

10= 0 rnA, CE =2.2V

ISbl

Supply Current (Standby)

ISb2

Supply Current (Standby)

Total input = 2.2Vor 0.8V

Typ.

Max.

Unit

3

rnA

0.1

rnA

50

rnA

10

rnA

10= 0 rnA, CE =Vee-0.2V
Total input = Vee - 0.2V or
GND+0.2V
leel

Supply Current (Operation)

10 =OmA, tRe=200ns
tRe = 1 Ils (Cl = 100PF)
CE,

OE=GND + 0.2V

lee2

Supply Current (Operation)

VOHl

" H " Output Voltage

10H=-0.4mA

2.4

VOH2

" H " Output Voltage

10H =-0.1 rnA

Vee x 0.8

VOL

" l " Output Voltage

10L =

VIH

" H " Input Voltage

VIL

" l " Input Voltage

III

Input leakage Current

VIL = GND +0.2V
VIH = Vee - 0.2V

ILo

Output leakage Current

3.2 rnA

VI = OV- Vee
Vo= OV- Vee
Chip Deselected

V
V
0.4

V

2.2
-0.3

Vee+0.3

V

0.8

V

- 10

10

IlA

- 10

10

IlA

-ICD®®[l{]--------------6-10

RP/RS532010E

• AC ELECTRICAL CHARACTERISTICS (Ta=0~70°C, Vcc=5V±10%)
Symbol

Parameter

Typ.

Min.

Max.

Unit
ns

tAC

Read Cycle Time

tACC

Address Access Time

200

ns

tCE

Chip Enable Access Time

200

ns

tOE

Output Enable Access Time

80

ns

80

ns

200

tDF

Output Floating Delay Time

0

tOH

Output Hold Time

0

Input Voltage

ns

: V IL = 0.6V, V,H = 2.4V, tr,

+

Output Load

: 1 TTL

Measuring Voltage

: V IL = O.BV, V,H = 2.2V,

tf = 10 ns

100 pF
VOL = O.BV, VOH = 2.2V

• TIMING CHART
tRC

>

Ai(i=0~17)

tACC

tCE

I

il

CE

/------- - - - - - - - -

OE

>

--'\

- - - - - - - - - - - - ______ 1

OE

I

k'\_--------tOF

tOE
tOH

II/,

Oi(i=0~7)

\\\

,\\

Valid Data

'II

NOTE
(Valid data after power on )
After power on, with CE set to GND level, valid data output will be sent after tAcc, from a change in at least one address input.
If other than the above parameters, the valid data will be sent after tCE due to the CE rise pulse.

• CAPACITANCE
Symbol

Parameter

Ci

Input Capacitance

Co

Output Capacitance

Condition
f = 1MHz

Min.

Typ.

Max.

Unit

10

pF

15

pF

-------------'------ICO®®DO6-11

RP/RS532010E

• PACKAGE DIMENSION

(Unitmm/inch)

• 32PIN DIP (RP531 01 OE)
42.5max
(1.673max)
32

17

PIN#l

16

15.24TVP
(.600 TVP )

c '2'
'E'E tHl
,---------------""\-~ o-E E-

~

2.54 TYP
•

3

~~

II • (.019
0.48'01
±C.004)

• 32PIN SOP (RS531 01 OE)

32

20.9max.
(0.823max.)

17

16

141'0.3
(0.555 '0.012)
11.3 TVP.
(0.445 TVP.)

~~
~~f
0e.If

\\.

ii

0.8TVP
• • (0.031 TYP.)

-ICD®®OO---------------6-12

",! ! ! ! ! !,IC!,! ! ! ! !D!,! ! ! ! !©~®!,! ! ! ! !o{]!,! ! ! ! ! ,! !,! ! ! ! ! ,! ~/ CMOS 4Mbil MASK RO~~"ro
RP/RF534040E

(524,288 word x 8 bit I 262,144 word x 16 bit)

RP/RF534040E is a 4 Mbit programmable mask ROM using CMOS process technology.
It has also been provided with a power down function which reduces supply current from 50mA (Max.)
to 100 I..l A (Max.) by setting the CE input to the .. H " level.
In addition, the logic level of the output enable can be selected from among three types of logic levels,
ACTIVE HIGH, ACTIVE LOW and ISOLATED .

• FEATURES
1.

Organization:

524288 words x 8 bits
262144 words x 16 bits

2.

Access Time :

3.

TTL Compatible Input/Output

200 ns

4.

Single 5V Power Supply

5.

Power Consumption : operation
standby

6.

3 - state Output

7.

Package:

275 mW (Max.)

O. 55 mW (Max.)

RP534040E'

40 pin DIP

RF534040E'

64 pin QFP

•

• BLOCK DIAGRAM

000,02030.0,0,0,0,0.0,,011 0,20130 .. 0"

CE

OEIOE
A-,

BYTE

Timing Control Circun

---------------IIO©®IJ[]6-13

RP/RF534040E

• PIN DESCRIPTION
• RF534040E (64PIN QFP)

• RP534040E (40PIN DIP)

0.00.880."0.0
ZOZOO»OOOZOZ
a;i2fl11Dgmi8~i8~~i6f:!

0"
0,
O,s/A-1

NC
GND
GND
NC
NC
BYTE
NC

6

O.

50

0,

49

O.

48

00

47

NC
OE/OE/NC
GND
GND
NC
NC
NC
CE

46
45
44

9

43

10

42

11

41

12

40

39 Ao

13

A16 14

38
37

NC
A,

A"
A"

15

A13

17

36
35

A"

,.

34

A,
A.

33

NC

NC
21

51

Vee

16
18

A2

~C\j~~~~re:;;:;~&lgc;;~
O::()~<1>"'CI~

..... U",()

Z<{Z<{<{<{Z<{<{<{Z<{Z
Cl

• PIN DESCRIPTION
Function

Pin Name
A-1-A17

Address Input

00-0,5

Data Output

-

OE/OE

Output Enable Input

CE

Chip Enable Input

BYTE

BYTE output/WORD MODE swiching

-Vcc

Power Supply (+ 5V)

GND

Ground

NC

No connection

• OUTPUT MODE SWITCHING
Output mode switching is done by BYTE input. BYTE input at high level sets to WORD MODE (16 bit output) . BYTE input at low level sets to BYTE MODE (8 bit output) . During BYTE MODE the 0,5 output
pin switches to A-1 input pin.
-

-

CE

OE (OE)

H

X

--

BYTE

X

A-1
(015)

X

00-7

Oe-15

MODE

LSB

MSB

Hi-Z

Hi-Z

Standby

-

-

Output
Hi-Z

-

-

WORD

Ao

A17

BYTE

A-1

A17

L

H (L)

X

X

Hi-Z

Hi-Z

L
L
L

L(H)
L 0-1)
L (H)

H
L
L

Inhibit
L
H

00-7
00-7
Oe-15

Oe-15
Hi-Z
Hi-Z

(Note)

x:

Don't Care
Hi - Z : High Impedance

-IID©®OO---------------6-14

RP/RF534040E

• ABSOLUTE MAXIMUM RATING
Symbol

Parameter

Condition

Vee

Supply Voltage

VI

Input Voltage

Vo

Output Voltage

Pd

Power Consumption

Topr

Operating Temperature

Tstg

Storage Temperature

Limit
- 0.3 -

With respeet to GND

- 0.3 -

Vee

- 0.3 - Vee
Ta = 25·C

Unit
7

V

+ 0.5
+ 0.3

V

350

mW

0-70

·C

- 40 -125

• RECOMMENDED OPERATING CONDITION

V

·C

(Ta=0-70·C)

Symbol

Parameter

Min.

Typ.

Max.

Vee

Supply Voltage

4.5

5.0

5.5

V

VIH

" H " Input Voltage

2.2

Vee

V

VIL

" L " Input Voltage

0

0.8

V

Unit

• ELECTRICAL CHARACTERISTICS
• DC ELECTRICAL CHARACTERISTICS (Ta=0-70·C, Vcc=5V±10%)
Parameter

Symbol

Condition

ISb'

Supply Current (Standby)

ISb2

Supply Current (Standby)

Min.

*1
*2
10= 0 mA, tRe = 200 ns

Typ.

Max.

Unit

0.1

mA

2

mA

50

mA

0.4

V

lee

Supply Current (Operation)

VOH

" H " Output Voltage

IOH = -0.4 mA

VOL

" L " Output Voltage

10L = 2.5 mA

VIH

" H " Input Voltage

2.2

Vcc+O.3

V

VIL

" L " Input Voltage

-0.3

0.8

V

Input Leakage Current

- 10

10

Il A

- 10

10

Il A

III
ILO

Output Leakage Current

* 1 : CE = Vee -

*

2 : CE

O.2V, Total input

= 2.2V, Total input =

=

VI = OV - Vee
Vo = OV -

Vee

Chip Deselected

O.2V or Vee - O.2V, 10

2.4

V

= 0 rnA

O.8V or 2.2V, 10 = 0 rnA

~--~-~----~~----IID@®[l{]~

6-15

•

RP/RF534040E

• AC ELECTRICAL CHARACTERISTICS (Ta=0~70°C, Vcc=5V±10%)
Symbol

Parameter

Typ.

Min.

Unit

Max.

ns

tRC

Read Cycle Time

tACC

Address Access Time

200

ns

tCE

Chip Enable Access Time

200

ns

tOE

Output Enable Access Time

80

ns

tOF

Output Floating Delay Time

0

80

ns

tOH

Output Hold Time

0

200

ns

Input Voltage

: V IL = O.BV. VIH = 2.4V, tr,

Output Load

: 1 TTL

Measuring Voltage

: V IL = 0.8V, VIH = 2.2V,

+

If = 10 ns

100pF
VOL = 0.8V, VOH = 2.2V

• TIMING CHART
tRC

>

Ai(i=-1~17)

tACC

I

tCE

V

CE

/------- --------

OE

>

--,

- - - - - - - - - - - - ______ 1

OE

k',---------to,

toe
tOH

II/,

Oi(i=0~15)

\\\

,\\

Valid Data

'II

NOTE
(Valid data after power on )
After power on, with CE set to GND level, valid data output will be sent after lAce, from a change in at least one address input.
I! other than the above parameters, the valid data output will be sent after tCE due to the CE rise pulse.

• CAPACITANCE
Symbol

Parameter

Ci

Input Capacitance

Co

Output Capacitance

Condition
f = 1MHz

Min.

Typ.

Max.

Unit

10

pF

15

pF

-ICD®®[]{]----------------~

RP/RF534040E

• PACKAGE DIMENSION

(Unit: mm/inch)

• 40PIN DIP (RP534040E)
53.3max
(2.09Smax)
40

21

PIN#l

20

.~ ~ ~ ~
Ll? ~ ~ g

_O-EE-

~
II
~~~r-'2
0...;..

2.54'"

.

,

0.4S'"

(.100"')

Iri ~

'O~

(.019 "'''''')

• 64PIN QFP (RF534040E)
2.9max
(.114max)
O.15±O.05

18.8±o.4
(.740±O.01tl)

14.0 TYP

(.006"''')

(.551"")

O.2 TYP
(.OOS"')

33

1 ==!!:mrn;:m;;;:;:;:;:;:;m:;:;::;::r.rr-~ 1
L-=5.c.:

~"' f...

g §.

----------------ICO@®IJO6-17

I

©!!!!!!!!!!!!!!!®!!!!!!!!!!!!!!![J{]~I

EKM·7.8807

NMOS 64 Kbit MASK ROM

!,!!!!!!!!!!!!!I
C!!!!!!!!!!!!!!!D

(8,192 word X 8 bit)

RP2364E
•

GENERAL DESCRIPTION

•

The RP2364E is static NMOS Read Only Memory organized as 8,192 words by 8-bits and operate from a single +5V
supply.
The RP2364E features automatic power-down mode.
When Chip ,Enable (CE) goes HIGH level, the supply
current is reduced from 100mA (max.) to 20mA (max.).
The device has Chip Enable (CE) input and output
Enable (OEjOE) inputs allowing up to 32 wired ORs to
be tied without external decoding.
According to your order, logic of the following pins
may be selected ACTIVE LOW or ACTIVE HIGH or NC.
Pins I, 22, 26 and 27.
and Pin 20 may be selected as CE or OE.
•

PIN CONFIGURATION (Top view)
OE'; lJE2/NC

Vee

A"
A7

OE3/lJE21NC

A,

As

As

As

OE./OE./NC

A.

All

A3

OE.(DE1

A2

AIO

Al
Ao

CE/oEs/lJE2
07

00

0,

0,

05

02

O.

GND

03

FEATURES
•

e8,192 words X8 bits organization
eLow power dissipation: Active
550mW max.
Standby 110mW max.
e Fast access time: 200ns max.
eSingie +5V(±10%} power supply
eCompletely TTL compatible: All outputs and inputs

•

PIN NAME

FUNCTION

Ao - Al2
00 - 07
OEI- OEs
CE
NC
Vcc
GND

Address Input
Data Output
Output Enable
Chip Enable
No Connection
Power Supply
GND

DATA OUTPUTS

BLOCK DIAGRAM

Ao
Al
A2
A3
A.

ADDRESS INPUTS

PIN DESCRIPTION

As
A6
A7
As
As
A,o
All
A"

OEl/OEl
OUTPUT
ENABLE
~

w

""-

::0

co

if)
if)

w
~

Cl
Cl

- ) CHIP
CE ENABLE

..:

---------------IIO@®OO6-19

I

RP2364E

• ABSOLUTE MAXIMUM RATINGS
Symbol
Vcc
VI
Vo
Pd
Topr
Tstg

Parameter
Supply Voltage
Input Voltage
Output Voltage
Maximum Power Dissipation
Operating Ambient Temperature
Storage Temperature

Unit
V
V
V
mW
·C

Limit
-0.5-7
-0.5-7
-0.5-7
700
0-70
-40-125

Condition
With respect to GND
Ta=25'C

·c

• RECOMMENDED OPERATING CONDITIONS (Ta=0-70'C)
Symbol
Vcc
VIH
VIL

Parameter
Supply Voltage
Input High Voltage
Input Low Voltage

Specified Value
Typ
Min
Max
4.5
5.0
5.5
2.0
Vcc
-0.5
0.8

Unit
V
V
V

• ELECTRICAL CHARACTERISTICS
e DC ELECTRICAL CHARACTERISTICS (Ta= (}--70·C. Vcc= 5V± 10%)
Symbol

icC!

Parameter

Icc2
VOH
VOL
VIH
VIL
ILl

Supply Current (Standby)
Supply Current (Active)
Output High Voltage
Gutput Low Voltage
Input High Voltage
Input Low Voltage
Input Leakage Current

ILO

Output Leakage Current

Specified Value
Typ
Min
Max
20
100
2.4
0.4
2.0
Vcc
-0.5
0.8
-10
10

Test Condition
CE=Vcc
Io=OmA
IOH= -400J,lA
IOL=3.2mA

VI =OV-Vcc
Vo=OV-Vcc
Chip Deselected

-10

10

eAC ELECTRICAL CHARACTERISTICS (Ta=O-70·C. Vcc=5V±10%)
Symbol

Parameter

tRC
tACC
tCE
tOE

Read Cycle Time
Address Access Time
Chip Enable Access Time
Output Enable Access Time

tDF

Output Hold Time after
Output Enable Change

tOH

Output Hold Time after
Address Change

tCH

Output Hold Time after Chip
Enable Change

Test Condition

Specified Valve
Min Typ Max
200
200
200
80

Output Load =
lTTL+IOOpF

80

80

-ICD@®[]{]
6-20

ns
ns
ns
ns
ns
ns

0

Notes: 1. Input Pulse Levels: VIL=0.6V. VIH=2.2V
2. Output Timing Reference Level: VOL =0.8V, VOH =2.0V

Unit

ns

Unit
rnA
rnA
V
V
V
V
J,lA
J,lA

RP2364E

eTERMINAL CAPACITANCE
Symbol
Ci
Co

Parameter

Specified Value
Min
Typ
Max

Test Condition

Input Capacitance
Output Capacitance

8

f=lMHz

12

Unit
pF
pF

• TIMING CHART

ADDRESS INPUT

(OE)

bc

==>K

)

K

tACC

___________ J

I

'\, ~,------ --""' /
,
r-....

/

'---- 1----- --tOH

tOE
tOF

-'

K"

7

tCH

tCE

./

DATA OUTPUT

L

"

) t--

---------------ICO®®OO-·6-21

RP2364E

•

28 PIN PLASTIC PACKAGE (Unit: mm)

14

15.24

II
-iJ..::

0.25 +0.13
-0.05

--ICD@([J[}{]~---------------6-22

EKM·8·8807

NMOS 1 28kbit MASK ROM
(16,384word X 8blt)

RP23128E
•

•

GENERAL DESCRIPTION
The RP23128E is static NMOS Read Only Memory
organized as 16,384 words by 8-bits and operate from a
single + 5V supply.
The RP23128E features automatic power-down mode.
When Chip Enable (CE) goes HIGH level, the supply
current is reduced from 100mA (max.) to 20mA (max.).
These devices have Chip Enable (CE) input and output
Enable (OE/OE) inputs allowing up to 16 wired ORs to be
tied without external decoding.
According to your order, logic of the following pins may be
selected.
Pin 22 (active low/active high)
Pin 1,27 (active low/active high/No Connection)
Pin 20 (Chip Enable/active low/active high)

OE,!OE,!NC

AI:!

A.
A,

A"
GEl/GEl

•

A,

CE'OE,OE,

A"

0,

0"
0,

0.
0,

0,

0,

GND

0,

PIN DESCRIPTION
FUNCTION

PIN NAME
Ao'CA1)
00'007
OE 1'COE4
CE
NC
Vcc
GND

Address Input
Data Output
Output Enable
Chip Enable
No Connection
Power Supply
GND

I

DATA OUTPUTS

BLOCK DIAGRAM

A"
A,
A,

OE,/C)l"
OEd Cffiz } OUTPUT
- - - - - . 0 OE3/ OE3
EN ABLE

A10

A"

ADDRESS INPUTS

Vee

OE" OE:l , NC

• FEATURES
• 16,384 words x 8 bits organization
• Low power dissipation: Active 550mWmax.
Standby II0mW max.
• Fast access time: 200ns max.
• Single + 5V (±1O%) power supply
• Completely TTL compatible: All outputs and inputs

•

PIN CONFIGURATION (Top view)

OE4/0E4

16.384 WORD

A3
A,
A,
A,
A,
A,
A,

0---

A I2

0--

X8BlT

0---~

0---~
~

if)
if)

MEMORY CELL

'"c'"
c

---0

~

CE

l

CHIP
ENABLE

0----

AI,l~

--------------ltO©®OO6-23

RP23128E

• ABSOLUTE MAXIMUM RATINGS
Symbol

Condition

Parameter
Supply Voltage

Vcc
VI
Vo
Pd
Topr

Input Voltage
Output Voltage
Maximum Power Dissipation
Operating Ambient Temperature

Tstg

Storage Temperature

Limit
-0.3-7
-0.3-Vcc+ 0.3
-0.3- Vcc+ 0.3

With respect to GND
Ta=25·C

700
0-70
-40-125

Unit
V
V
V
mW
~C

·C

• RECOMMENDED OPERATING CONDITIONS (Ta=O-70·C)
Symbol

Parameter
Supply Voltage
Input High Voltage

Vcc
VIH
VIL

Input Low Voltage

Specified Value
Typ
Min
Max
4.5
5.0
5.5
2.0
Vee
-0.3
O.S

Unit
V
V
V

• ELECTRICAL CHARACTERISTICS
e DC ELECTRICAL CHARACTERISTICS (Ta= (}--70·C. Vcc= 5V± 10%)
Symbol

Parameter

leC!
leC2

Supply Current (Standby)
Supply Current (Active)

VOH
VOL
VIH
VIL
III

Output High Voltage
Output Low Voltage
Input High Voltage
Input Low Voltage
Input Leakage Current

lLa

Output Leakage Current

Test Condition
CE=Vec
lo=OmA
10II= -400,uA
10L= 2.0mA

VI =OV-Vcc
Vo=OV-Vcc
Chip Deselected

Specified Value
Typ
Min
Max
20
100
2.4
0.4
2.0
Vcc
-0.3
0.8
-10
10
-10

10

Unit
rnA
rnA
V
V
V
V
,uA
,uA

eAC ELECTRICAL CHARACTERISTICS (Ta=O-70·C. Vcc=5V±lO%)
Symbol

Parameter

tRC

Read Cycle Time

tACC
tCE
tOE
tDF

Address Access Time
Chip Enable Access Time
Output Enable Access Time
Out put Floating Delay Time

tOH

I

Output Hold Time

Note) Test Condition

Specified Valve
Min
200

ns

I

i

200
I 200

I so
I so

0

Unit

Typ I Max

I

I

ns
ns
ns
ns
ns

Input Pulse Voltage: VIL=0.6V.
VIH=2.4V
Input Pulse Rise/Fall Time: IOns
Timing Measuring Voltage:

Input VIL=O.SV. VIH=2.2V
Output VOL=O.SV. VOH=2.0V
Output Load: I TTL + IOOpF
(including jig capacitance)

-ICD©®OO--------------6-24

RP23128E

-TERMINAL CAPACITANCE
Symbol
Ci
Co

•

Test Condition

Parameter
Input Capacitance
Output Capacitance

f=lMHz

Specified Value
Typ
Min
Max
8
12

Unit
pF
pF

TIMING CHART

tRc

ADDRESS INPUT

I

tACC

OE-----'

,

OE - - - - - - - - - - ,

tOE

CE---_
tCE

DATA OUTPUT

ICO@®OO6-25

RP23128E

• 28 PIN PLASTIC PACKAGE (Unit: mm)

14

-ICO©®[]{]--------------6-26

ICD©®OO

EKM·9·8807

NMOS 256 Kbit MASK ROM
(32,768word x 8bit)

RP23256D/E, RP23257D/E
•

•

GENERAL DESCRIPTION
The RP23256D/E and RP23257D/E are static NMOS
Read Only Memories organized as 32,768 words by 8·
bits and operate from a single + 5V supply.
The RP23256D/E and RP23257D/E features automatic
power· down mode. When Chip Enable (CE) goes HIGH
level, the supply current is reduced from 100mA (max.)
to 20mA (max.).
These devices have Chip Enable (CE) input and two
output Enable (OE/DE) inputs allowing up to eight
wired ORs to be tied without external decoding.
According to your order, logic of the following pins
may be selected ACTIVE LOW or ACTIVE HIGH.
Pins. 1, and 22 for RP23256D/E
Pins 1, and 26 for RP23257D/E
and OE2 may be changed to NC (No Connection), CE
may be selected to OE3.

OUTPUT ENABLE
OEZ/OEi/NC

As
A,

OUTPUTS

ADDRESS
INPUTS

Au

ADDRESS
INPUTS

OE1/0El Oug~~LE
AlO ADDRESS INPUT
CHIP
ENABLE

{~:

OUTPUTS

11
O.
GND 14

.'-----'

OUTPUT ENABLE
28 Vee
A14 ADDRESS

OE./OEi/NC 1

OE,/ DEl

INPUT

OUTPUT

As }
ENABLE
24 A9
ADDRESS INPUTS

550mW max.
1l0mW max.
• Fast access time: RP23256D/257D 250ns max.
RP23256E/257E 200ns max.
• Single + 5V(± 10%) power supply
• Completely TTL compatible: All outputs and inputs
.3·state outputs for wired·OR expansion
• Pin compatible with: Intel 27256 EPROM (RP23256D/E)
TI 2564 EPROM (RP23257D/E)
BLOCK DIAGRAM

1

AD

• FEATURES
.32,768 words x 8 bits organization
• Low power dissipation: Active
Standby

•

PIN CONFIGURATION (Top view)

ADDRESS
INPUTS

23

Al2

22 CElOE3/0Ei

21 AIO}
20 All

OUTPUTS

{~:

~~~BLE

ADDRESS INPUTS

19 07 )
18 06

11

17 05

O.

OUTPUTS

16 O.

03

DATA OUTPUTS

..........,vcc
_GND

A.
Al

~-r-,--r--,;r.,

OEJ/O'£i }
0&/ O'£i OUTPUT
OE,/O'£i ENABLE

A,

A..
Au

A,

ADDRESS INPUTS

~:
Po.

A,
A.
A.

CE

) CHIP
ENABLE

Au
Au
Au

---------------ICO©®OO6-27

I

RP232560 IE, RP2325 70 IE

•

ABSOLUTE MAXIMUM RATINGS

Symbol
Vcc
VI
Vo
Pd
Topr
Tstg
•

Limit
-0.5-7
-0.5-7
-0.5-7
700
0-70
-40-125

Condition
With respect to GND
Ta=25'C

Unit
V
V
V

mW
·C
·C

RECOMMENDED OPERATING CONDITIONS (Ta=O-70·C)

Symbol
Vcc
VlH
VIL
•

Parameter
Supply Voltage
Input Voltage
Output Voltage
Maximum Power Dissipation
Operating Ambient Temperature
Storage Temperature

Parameter
Supply Voltage
Input High Voltage
Input Low Voltage

Specified Value
Typ
Min
Max
5.0
5.5
4.5
2.0
Vcc
-0.5
0.8

Unit
V
V
V

ELECTRICAL CHARACTERISTICS
-DC ELECTRICAL CHARACTERISTICS (Ta=(}-70·C. Vcc=5V±10%)

Symbol

Parameter

IcC!
Icc,
VOH
VOL
VlH
VIL
III

Supply Current (Standby)
Supply Current (Active)
Output High Voltage
Output Low Voltage
Input High Voltage
Input Low Voltage
Input Leakage Current

ILO

Output Leakage Current

Test Condition
CE=Vcc
Io=OmA
IOH= -400!LA
IOL=3.2mA

VI =OV-Vcc
Vo=OV-Vcc
Chip Deselected

Specified Value
Typ
Min
Max
20
100
2.4
0.4
2.0
Vcc
-0.5
0.8
-10
10
-10

10

Unit
rnA
rnA
V
V
V
V
!LA
!LA

.AC ELECTRICAL CHARACTERISTICS (Ta=O-70·C, Vcc=5V±10%)

Symbol

Parameter

tDF

Read Cycle Time
Address Access Time
Chip Enable Access Time
Output Enable Access Time
Output Hold Time after
Output Enable Change

tOH

Output Hold Time after
Address Change

tCH

Output Hold Time after Chip
Enable Change

tRC
tACC
tCE
tOE

Test Condition

RP23256D/257D
Min Typ Max
250
250
250
100

Output Load =
ITTL+IOOpF

RP23256E/257E
Min Typ Max
200
200
200
80

100
0

80

ns
ns
ns
ns
ns
ns

0
100

Unit

80

ns

Notes: I. Input Pulse Levels: VIL=0.6V. VlH=2.2V
2. Output Timing Reference Level: VOL=0.8V. VOH=2.0V

-ICO©®[}{]-------------6-28

RP23256D/E, RP2325 7D/E

-TERMINAL CAPACITANCE
Symbol
Ci
Co

Parameter

Specified Value
Typ
Min
Max

Test Condition

Input Capacitance
Output Capacitance

8
12

f=lMHz

Unit
pF
pF

• TIMING CHART
bc
ADDRESS INPUT

~(

)(
tACC

(OEt-3)

___________ J

"-,

t',.---- -- ....,

/

"-

/,

'---- -----

-

-

tOH

tOE
tOF

~

~

"/

tCH

tCE

V
['...

DATA OUTPUT

L

..
) t--

---------------ICD©®OO6-29

•

RP23256D/E,RP23257D/E

• 28 PIN PLASTIC PACKAGE (Unit: mm)

14

-ICO©®DO------------6-30

_IC_D®_@_OO~~/

EK ·047 ·9006

NMOS 1Mbit MASK ROM
(131 ,072 word X 8 bit)

RP231027D/E
• GENERAL DESCRIPTION
The RP231027D/E is a static NMOS read only
Memory organized as 131,072 words by 8 bits and
operates from a single+5V supply.
The RP231027D/E features automatic power·down
mode. When Chip Enable (eE) goes HIGH level, the
supply current is reduced from 100mA (max.) to 30mA
(max.).
Pin 20 can be used as OE.
According to your order, Logic of the OE pin may
be selected ACTIVE LOW or ACTIVE HIGH.
• FEATURES
e131,072 words x 8 bits organization
e Low power dissipation Active
550m W max.
Standby
165mW max.
e Fast access time
RP231027D 250ns max.
RP231027E 200ns max.
eSingle +5V (±10%) power supply
e Completely TTL compatible: All outputs and inputs
e 3-state outputs for wired-OR expansion
e Pin compatible with Intel 27512

• PIN CONFIGURATION (Top view)

vee
AI.

ADDRESS
INPUTS

A7

AI,

A,

As

As

A,

A.

All

A,

AI,

A2

21

Al

20 CE/OEiOE

Ao

OUTPUTS

ADDRESS
INPUTS

ro

AIO

~~tBLE

07
11

0,

01

Os

02

0,

GND

0,

OUTPUTS

I

• BLOCK DIAGRAM

Ao
Al
A2

AlO
All

A3

A.

CE/OE/OE

As
A6

A7
As

A,

MEMORY CELL ARRAY

AI2

A13
Al4
Ais
AI6

----------------ICO©®[]{]6-31

RP231027D/E

• ABSOLUTE MAXIMUM RATINGS
Symbol
Vee
VI
Vo
Pd
Topr
Tstg

Parameter
Supply Voltage
Input Voltage
Output Voltage
Maximum Power Dissipation
Operating Ambient Temperature
Storage Temperature

Condition

Limit
-0.3-7
-0.3-Vcc+0.3
-0.3-Vcc+0.3
700
0-70
-40-125

With respect to GND
Ta=25'C

Unit
V
V
V
mW
·C
·C

• RECOMMENDED OPERATrNG CONDITIONS (Ta=O-70'C)
Symbol
Vee
VIH
\TIL

Parameter
Supply Voltage
Input High Voltage
Input Low Voltage

Specified Value
Typ
Min
Max
4.5
5.0
5.5
2.0
Vee
-0.3
0.8

Unit
V
V
V

• ELECTRICAL CHARACTERISTICS
eDC ELECTRICAL CHARACTERISTICS (Ta=0-70·C. Vcc=5V±10%)
Symbol
leel
lee2
VOH
VOL
VIH
VIL
ILl
lLO

Supply Current. (Standby)
Supply Current (Active)
Output High Voltage
Output Low Voltage
Input High Voltage
Input Low Voltage
Input Leakage Current
Output Leakage Current

Specified Value
Typ
Min
Max
30
100
2.4
Vcc
0.4
2.0
0.8
-0.3
10
-10
-10
10

Test Condition

ParametE:r

CE=Vee
10=OmA
10H= -400JlA
IOL=2.0mA

VI=OV-Vcc
Vo=Vee.Chlp Deselected

Unit
rnA
rnA
V
V
V
V
JlA
JlA

eAC ELECTRICAL CHARACTERISTICS (Ta=O-70·C. Vee=5V±10%)
Symbol
tRC
tACC
tCE
tOE
tnF
tOH

Parameter
Read Cycle Time
Address Access Time
Chip Enable Access Time
Output Enable Access Time
Output Floating Delay Time
Output Hold Time

Min
250

RP231027D
Typ
Max
250
250
100
100

0
0

Min
200

0
0

RP231027E
Typ

Max
200
200
80
80

Unit
ns
ns
ns
ns
ns
ns

Note) Test Conditipn
Input Pulse Voltage:VIL=O.6V. VIH=2.4V
Input Pulse Rise/Fall Time: IOns
Timing Measuring Voltage: Input VIL=O.8V. VIH=2.2V
. Output VOL=0.8V, VOH= 2.0V
Output Load: 1TTL + 100pF (including jig capacitance)

--HDm@oo--------------~-----------6-32

RP231027D/E

eTERMINAL CAPACITANCE
Symbol
Ci
Co

•

Specified Value
Typ
Min
Max

Test Condition

Parameter
Input Capacitance
Output Capacitance

8
12

f=lMHz

Unit
pF
pF

TIMING CHART

tRC

Ai(i=O -16)

)
tAce

I

OE
OE

I

tCE

)

r------

------

--,

K.. _________

__ - ____ - - ______ 1

tD,

tOE

tOH

Oi(i=O -7)

III
\\\'

l\'
'1/

----------------IIO©®OO6-33

RP231027D/E

•

28 PIN PLASTIC PACKAGE (Unit:mm)

14

15.24

II

~

0.25+ 0 . 13
-0.05

o·
15·

-IID©®OO-------------6-34

_IC_D®_®_OO__!!!!!!!!!!!!!!!I

EK-043-9004

NMOS 4Mbit MASK ROM
(524,288word x 8bit)

RP234096
The RP234096 is static NMOS Read Only Memory

• PIN CONFIGURATION (Top view)

organized as 524288 words X 8 bits and operates from
a single +5V Supply. And the consumption current

[

1

32

vcc

is 50mA (MAX). Tow Output Enable signals allows

[ 2

31

up to 4 wired ORs.

3

30

OEVOEVNC
NC

The Output Enable of the pin31 can be selected as

4

29 ]

5

28 ]

6
7

27
26

Active High, Active Low or NC (No Connection).
A5

8

25

A,

9

24

A,

10

524288words X8bits

A,

11

22 ]

200ns (MAX.)

Ao

12

21) 0,

• FEATURES
1.

Organization:

2.

Access Time:

3.

Input/Output Level: TTL

4.

Single 5V power supply

5.

00

13

0,

[ 14

20 ] 0,
19 0 5

0,

[ 15

18

GND>[ 16

Package: 32pin plastic DIP

23 ]

0,

17 ] 0,

I

• PIN DESCRIPTION
Pin Name

Description

Ao -AlB

Address Input

00 -0,

Data Output

OE

Output Enable Input

OE1/0E1

Output Enable Input

NC

No Connection

Vcc

Power Supply (+5V)

GND

Ground

---------------IIO©@Oil6-35

RP234096

• BLOCK DIAGRAM

~VCC
~GND

Ao
Al
Az
Alo
All

~OE
~

OElIOElINC

524288word

x
8bit

MEMORY CELL

-ICD@®OO-------------6-36

RP234096

• ABSOLUTE MAXIMUM RATING
Symbol

Parameter

Va;

Supply Voltage

VI

Input Voltage

Vo

Output Voltage

Pd

Power Consumption

Topr

Operating Temperature

Tstg

Storage Temperature

Condition

With respect to GND

Limit

Unit

-0.3-7

V

-0.3 - Vcc+0.3

V

-0.3 - Vcc+O.3

V

350

mW

0-70

·C

-40-125

·C

Ta = 25·C

• RECOMMENDED OPERATING CONDITION (Ta = 0 - 70°C)
Symbol
Va;
VIH
VIL

Parameter

MIN.

TYP.

Supply Voltage

4.5

5.0

"H" Input Voltage

2.0

"L" Input Voltage

-0.3

MAX.

Unit

5.5

V

Vcc+B.3

V

0.8

V

I

• ELECTRICAL CHARACTERISTICS
• DC Electrical Characteristics (Ta = 0 -70·C. Vee = 5V±10%)
Symbol

Parameter

Ia;

Supply Current
(operation)

lo=OmA

VOH

"H" Output Voltage

IOH =-400pA

VOL

"L" Output Voltage

IOL =3.2mA

VIH

"H" Input Voltage

VIL

"L" Input Voltage

ILl

Input Leakage Current

VI = OV -Vee

ILO

Output Leakage Current

Vo = OV -Vee
Output Deselected

Condition

MIN.

TYP.

MAX.

Unit

50

mA

2.4

V
0.4

V

2.0

Va;40.3

V

-0.3

0.8

V

-10

10

pA

-10

10

pA

---------------IID©®OO6-37

RP234096

eAC Electrical Characteristics (Ta

Symbol

= 0-70o C,

Parameter

Vcc = 5V±10%)

MIN.

TYP.

MAX.

tRC

Read Cycle Time

1:Acx:

Address Access Time

toe

Output Enable
Access Time

tDF

Output Floating
Delay Time

0

toH

Output Hold Time

0

Note)

Test Condition
Input Pulse Voltage: VIL = 0.6V, VIH = 2.4V
Input Pulse Rise/Fall Time: 10 ns
Timing Measuring Voltage: Input VIL = o.av, VIH = 2.2V
Output VOL = o.av, VOH = 2.2V
Output Load: ITTL + 100pF (Including Jig capacitance)

200

Unit
ns

200

ns

ao

ns

ao

ns
ns

e Timing Chart

t RC

Ai 0=0-1 8)

>

t

ACC

OE
OE

__________________________ J

~

r----------

---------- --"

\

i ...-------------\

I---

tOE - -

III,

OiO=0-7 )

t DF -

-

I--

\\\

Valid Data

tOH

-

~\\

'II

* Valid data at power·on
Valid data is output after 1:Acx: from the change of at least one of the Address Input signals
at the power·on.
.

-IID©®UO-------------6-38

RP234096

• Capacitance
MAX.

Unit

Ci

Input Capacitance

Parameter

f= 1MHz

8

pF

Co

Output Capacitance

f= 1MHz

12

pF

Symbol

Condition

MIN.

TYP.

• PACKAGE DIMENSION (unit: (~:))
32 pin DIP

1524 TYP'

I. 600 TYPI
16

II

I
J

2 54 TYP

I. 1OOTYPI

0.48±0.1
(.019±0.0041

--I-

0-15'

---------------IID@®o{]6-39

I

!!!!!!!!!!!!!!!~I

No. 84-01 4-1-1984

I!!!!!!!!!!!!!!!CD!!!!!!!!!!!!!!!©!!!!!!!!!!!!!!!®!!!!!!!!!!!!!!!OO

RF/RP5HOl
•

•

GENERAL DESCRIPTION

PIN CONFIGURATION (Top view)

RF5H01/RP5HOI is a PROM with 64 x Ibit
organization (+ dummy 8 bits), employing 2-layer
silicon gate CMOS processing technology.
•

DATA

COUNTER OUT

CE/Vpp

RESET

Vee

DATA CLOCK

GND

TEST

FEATURES

.64 x Ibit organization (+ dummy 8 bits)
• Low power dissipation
Active
55mW (max)
550# W (max)
Standby
• Access time
l#s (max)
• Single power supply 5V ± 10%
• Serial outputs
• Inputs and outputs TTL level
.3-state. (Tri-state) outputs

•

CMOS 64 bit PROM

BLOCK DIAGRAM

----CHIP ENABLE
PROGRAM
CONTROL

CE/Vpp

DATA

OUTPUT
BUFFER

~v"

4 GND

I

Y DECODER

RESET 7
6/7-BIT
BINARY
COUNTER

XDECODER

DATA
CLOCK 6

64 x I-BIT
MEMORY
CELL

I
I

I
I

TEST

COUNTER
CONTROL

OUTPUT
BUFFER

I
I

L _____

8
COUNTER OUT

-~

---------------IID@®DIJ-6-41

•

RF/RP5HOl

• ABSOLUTE MAXIMUM RATINGS
Symbol
Vee
V pp
V,
Vo

p.
Topr

T stg

Parameters
Vee Supply Voltage
V pp Supply Voltage
Input Voltage
Output Voltage
Maximum Power Dissipation
Operating Temperature Range
Storage Temperature

Conditions
With respect to GND

Ta=25'C

Limits
-0.3-7
-0.3-22
--0.3-7
-0.3-7
0.3
-20-70
-40-125

Unit
V
V
V
V
W
·C
·C

Limits
Typ

Unit

• RECOMMENDED OPERATING CONDITIONS (Ta = - 20 -70'C)
Symbol
Vee
V'H
V IL

Parameters
Supply Voltage
Input High Voltage
Input Low Voltage

Min
4.5
2.0
-0.1

Limits
Typ
Max
5.5
5.0
VcctO.3
0.8

Unit
V
V
V

• ELECTRICAL CHARACTERISTICS
• READ OPERATION D.C. CHARACTERISTICS(Ta= -20-70°C, Vee =5V ± 10%)
Symbol

Parameters

IcC!

Standby Vee Supply Current

1cc2

Operating Vee Supply Current
Output High Voltage
Output Low Voltage
Input High
Except TEST
Voltage
TEST
Except TEST
Input Low
TEST
Voltage
Input Leakage RESET.DATA CLOCK
Current
TEST,cr/V pp
Output Leakage Current

VOH
VOL
V'H
V rL

ILl
ILo

Test Conditions
cr/V pp = Vee ± 0.3V
DATA CLOCK,RESET = Vcc or Open
TEST=GND or Vcc±O.ilV
louT=omA
IOH = -400",A
IOL=2.1mA

Min

100

",A

10

rnA
V
V
V
V
V
V
",A
",A
",A

2.4
2.0
4.0
-0.1
-0.1
-180
-10
, -10

V,=OV,vec=5.5V
V,=OV-Vee
Vo=OV-Vee

Max

0.45
Vcc t O.3
Vcc tO.3
0.8
1.0
-20
10
10

• READ OPERATION, A.C. CHARACTERISTICS(Ta=-20-70°C, Vee=5V±10%)
Symbol
tAce
to:

tDF
tRw
tew

Parameters
Clock to Output Delay
cr to Output Delay
cr High to Output Float
Reset pulse width
Clock pulse width

Test Conditions

Min

CE/VPP=V'L
Load=
!TTLt 100pF

0
2
2

Limits
Typ
Max
1
1
200

Unit
",s
I's

ns
",s
",s

-IIO©®OO------~------6-42

R.F/RP5HOl

• D.C. PROGRAMMING CHARACTERISTICS (Ta=25°C±5°C, V ee =5V±5%)
Symbol
Ipp
lee
VIH
VIC

Parameters

Test Conditions

V pp Supply Current
Vee Supply Current
Input High
Except TEST
Voltage
TEST
Input Low
Except TEST
Voltage
TEST
Program
Voltage

pulse

Input

High

V[HP

Program
Voltage

pulse

Input

V[LP

Low

III

Input leakage
Current

RESET.DAT A CLOCK

TEST

Min

<:E/V pp = V IHP
2.0
4.0
-0.1
-0.1

Limits
Typ
Max
5
0.5
VcctO.3
Vcc tO.3
0.8
1.0

mA
mA
V
V
V
V

20.5

21.0

21.5

V

2.0

Vee

6.0

V

-20
10

J.lA
J.lA

-170
-10

V,=OV. Vee=5.25V
VI=OV-Vee

Unit

• PROGRAMMING CHARACTERISTICS (Ta=25°C ±5°C. Vee =5V ±5%)
Symbol
t AS
tes
tos
tOH
tOF
teE
tpw
t p•
t pF
low
tew
•

Parameters

Min
2
2
2
2
0

Address Set·up Time

IT Set·up Time
Data Set·up Time
Data Hold Time
cr to Output Float
IT to Output Delay
Program pulse width
V pp Pulse rise time
V pp Pulse fall time
Reset pulse width
Clock puls€ width

45
0.5
0.5
2
2

Limits
Typ
Max

200
1
55
100
100

50

Unit
J.ls
J.ls
J.lS
J.lS
ns
J.lS
ms
J.lS
J.lS
J.lS
J.lS

I

TIMING DIAGRAM
RESET

~

\

\

DATA CLOCK
tRW

tew

CE/V pp

.1

I

)<

DATA

~

I tACC

,
t DF

tCE

--------------ltD©®[]{]6-43

RF/RP5HOl
• PROGRAM MODE
RESET

--+..".",-+---------_ __.

DATA CLOCK

~~--------Hi -Z

Hi-Z

DATA INPUT

CE/Vpp
tpw

tpw

t PR

IOH

les

t

OF

• OPERATING MODES
Mode
~
Read
Standby
Program

TEST(5)=GND
TEST (5)= Vee

•

Data

Counter output

1

8

Data Output
High impedance
Data Input

Clock (AS) Output
High impedance
High impedance

<::E/V pp
2
VIL
VIH
VIHP

Vee

GND

3

4

Vee
Vee
Vee

GND
GND
GND

Counter operation mode
6 bits
7 bits

EXPLANATION ON OPERATION

.READ MODE

.STANDBY MODE

RF5HOl/RP5HOl is a serial address type PROM
with 6-bit/7-bit counter. The first bit can be read
out by adding reset pulse after CE"/VPP=V IL . The
2nd bit-the 64th bit can be sequencially read out
by adding data clock pulse. The output data is
valitl after a delay of t ACC from reset rise up or
data clock fall down, in the state of CE/V pp = VIL.
In the state of TEST=GND, the counter operates
as a 6-bit counter. It returns to the reset condition
(address 000000), if it is added with 64-time data
clock pulses after the reset pulse is applied.
The counter output pin is for operation test of
the built-in counter. It puts out the highest output
(A5) of the 6-bit counter.

RF5HOl/RP5HOl is provided with power down
function that is controlled by IT input. If TTL
high level is given to the chip enable input (CE), the
device comes to be the Standby Mode, and the
output is in the state of high impedance.

-IID©®[J[]I------------6-44

RFlRP5HOl

• PROGRAM MODE

.DUMMY BITS

Initially, all bits of RF5HOl/RP5HOI are in the
"I" state. Data is introduced by selectively
programming "O"into the desired bit locations.
The program is operated by setting up CE"/V pp =
V,H , and adding the reset pulse, and then applying
the 50mS 21 V program pulse. The data are
verified by making CE"/V pp = V,L. The 2nd bit-the
64th. bit are programmed by progressing the
addresses in sequence by means of adding the data
clock pulse.

RF5HOl/RP5HOI is a one-time PROM. For this
reason, it is provided with a dummy bit of 8 bits
for test programming. The dummy bit is located
after the practical use 64th bit. The address is 8
bits of 1000000-1000111. The built-in counter
operates as a 7-bit counter when "Test" (5 pins) is
set at Vee level, enabling to select the dummy bit.
In the case of the "Test" being GND level, the
counter operates as the 6-bit counter, being unable
to select the dummy bit. In the 7-bit counter, when
the clock pulse is added in sequence, the address
progresses ftom 0000000 to 1111111, and then returns
to 0000000.

• 8-PIN PLASTIC FLAT PACKAGE (EXTERNAL VIEW) (UNIT: mm)

I

- ...

ci
+1
o
~

ci

+1
00

c.O

0.15typ

lI=itt

0.95typ
1.27 typ

1.6 ± 0.15 0.15! 8:65

5.0± 0.15

Co

.':'
00

o

--------------ICD@®OO6-45

RFlRP5HOl
.8-PIN PLASTIC OIL PACKAGE (EXTERNAL VIEW) (UNIT: mm)
8.8±0.2S

8

7

6

5

2

3

4

. yp
787t

-l-l-l.Otyp

1ooI-__r+. ....--.......=f-...- -

t-

~

0

O.15TYP

"-

~~

O.3TYP

5.0±O.15

'"

.,;

.tj,

(Unit: mm)

--------------IID©®OO7-45

ICOrrutmOO

uoJlJ

I

PRELIMINARY I

ES-116-9202

STEP-UP/STEP-DOWN PWM DC/DC CONVERTER

Product News \ . . . ._w_ith_V_O_L1_AG_E_D_E_TE_C_TO_R_R_S5_R_M_S_eri_es_ __
• OUTLINE

RS5R Series are compact DC/DC converter ICs with a voltage detector and are developed with CMOS
process technology. The devices consist of a PWM type DC/DC converter, a series regulator and a voltage
detector. As external components, a' coil, a diode, and a capacitor are available for making the output
constant. When the input voltage is sufficiently high, they work as series regulators. When the input
voltage falls down, they work as step-up DC/DC converters. The RS5RM series include a voltage detector
and the output voltage can be detected. The chip enable can switch off the DC/DC converter and the
voltage detector, and can save consumption current at standby state. The RS5R is fit for batteryoperated equipment.

• FEATURES
• Small invalid current .................... TYP50JlA (RS5RM3624; Yin = 3.0V, no Load)
• Standby mode. . . . . . . . . . . . . . . . . . . . . . . .. Istb

= MAX1.0 JlA

• Low voltage operation ................... operating voltage Yin = 0.9 -1 OV
• High accuracy of output voltage ........... fixed output voltage, accuracy ± 2.5%
• Variety of output voltage level
• Output voltage is in the neighborhood of battery voltage due to the step-up/step-down function
(Ex. getting 3V output using 3V-battery)
• Soft start and driver proof circuit
• Phase conpensation circuit
• Large current can be get by connecting a driving transistor externally.
• Small package ......................... 8 pin SOP

• APPLICATION
• Camera, Video camera, Hand-held audio system.
• Book type personal computer, Word processor, small size office automation equipment.
• Pocket bell, Code-less telephone, Hand-held telephone.

--------------IID@®OO7-47

I

RS5RM

• BLOCK DIAGRAM

VIN

EXT

........--17

+

• DESCRIPTION
Pin No.
Symbol
1
VSS
2
CE
3
VDOUT
4
VDIN
5
VOUT
6
VDD
7
EXT
8
LX

Description
Ground
Chip Enable. Set the pin to VDD then the device become standby state.
Output for voltage detector (NMOS open drain output)
Input for voltage detector
Output for voltage regulator
Output for step-up voltage. Power supply for the device.
Driving output for external transistor
Output for switching

-IIO®®OO--------------,--7-48

RSSRM

• ABSOLUTE MAXIMUM RATINGS (Ta
Parameter

Symbol

= 2SoC,

Vss

= OV)

Rating

Unit

Power Supply Voltage

VDD

-0.3-12

V

Output Voltage LX Pin

VLX

-0.3-12

V

EXT Pin

VEXT

-0.3 - VDO + 0.3

V

VOUT Pin

VOUT

-0.3 - VDO + 0.3

V

VDOUTPin

VDOUT

-0.3-12

V

I nput Voltage

VCE

-0.3-VDO+0.3

V

Output Cu rrent LX Pi n

ILX

250

mA

300

mW
°c

Power Consumption

Pd

Operating Temperature

Topr

-30-+S0

Storage Temperatu re

Tstg

-40-+ 125

Soldering Condition

Tsolder

260°C

°c
10sec

• ELECTRICAL CHARACTERISTICS
• RSSRM3624 (3.6V Output)
Yin = 4.0V, Ta = 2SoC
Parameter

Symbol

Condition

MIN

No Load

0.9

Input Voltage

Vin

Holding Voltage

Vinhd

No Load Vin = H ~ L

Output Voltage

Vout

Vin = 4.0V, lout = 5mA

Input Voltage Stability

LWout!Vin

Load Stability

D. Vout/lout

Step-up Output Voltage

Vdd

Max. Oscillating Frequency

fosc

Duty Ratio

DfMAX

Lx Switch on Voltage

VaLl

Lx Switch Leakage Current

Ileak

Detect Vo Itage

Vdet

Detect Voltage Hysteresis

Vhys

V
V

lout = 1mA, Vin = 0.9V - SV

10

100

mV

Vin = 1.SV, lout = 1-30mA

10

100

mV

4.10

4.21

Vin = 1.SV, lout = 5mA

3.51

3.99

50

2.3

CE "L" Input Voltage

VCEL

CE "H" Input Current

ICEH

CE = 3.5V

CE "L" Input Current

ICEL

CE = OV

%
V

2.0
2.4

2.5

120

240

mV

0.5

V

O.S VOD

Vin=3V (Step-up). No Load

0.5

JlA
V

IOL=5mA

0
-0.5

V
kHz

SO
ILX = 50mA

VdOL

Istb

V

3.69

VCEH

Standby Current

Unit

10
3.60

VO Output on Voltage

lin

MAX
O.S

CE "H" Input Voltage

Consumption Current

TYP

0.5
50

VDO

V

0.2VDD

V

1.0

JlA

0.5

JlA

100

JlA

Vin=SV (Step-down). No Load

10

JlA

Vin = 3V, No Load

1

JlA

-------------ICO©®[J[]7-49

I

RS5RM

• SELECTION GUIDE
You can define the output voltage, the detect voltage and the taping direction of RS5RM series.
The devices are defined by the following characters.
RS5RMXXXXX-X +-Typenumber

t t

t

abc

t

d

Meaning

Number
a
b

Defines output voltage (Vout).
• The range for Vout is 2.0V to 6.0V in units of 0.1V, with an accuracy of ±2.5%.
Defines detect voltage (- Vdet).
• The range for - Vdet is 2.0V to 6.0V in the units of 0.1 V, with an accuracy of ±2.5%.

c

Defines version.

d

Defines taping direction with T1 and T2. (See below)

Note)

Taping Information (1000 pieces/reel)

;l1.55±O.05

o

0

0

0

T1 Type

T2 Type
(Unit: mm)

-ICD©®OO-------------7-50

RSSRM

• PACKAGE DIMENSION (Unit: mm)

M

d

+1

'"



d

I

O.4±O.l

--------------IID@®[}[]7-51

rrurnlOO
IID l!!J
lOJ

I

PRELIMINAI{Yj

ES-1l5-9202

STEP-UP/STEP-DOWN VFM DC/DC CONVERTER

Product News \ __w_ith_V_O_Ll_AG_E_D_E_TE_C_TO_R_R_S5_R_J_S_eri_es_ __

• OUTLINE
RS5RJ Series are compact DC/DC converter ICs with a voltage detector and are developed with CMOS
process technology. The devices consist of a VFM type DC/DC converter, a series regulator and a voltage
detector. As external components, a coil, a diode, and a capacitor are available for making the output
constant. When the input voltage is sufficiently high, they work as series regulators. When the input
voltage falls down, they work as step-up DC/DC converters. The RS5RJ series include a voltage detector
and the output voltage can be detected. The chip enable can switch off the DC/DC converter and the
voltage detector, and can save consumption current at standby state. The RS5RJ is fit for batteryoperated equipment.

• FEATURES
• Small invalid current .................... TYP15J.!A (RS5RJ3624; Vin = 3.0V, no Load)
• Standby mode ......................... Istb = MAX1.0 J.!A
• Low voltage operation ................... operating voltage Vin = 0.9 - 10V
• High accuracy of output voltage ........... fixed output Voltage, accuracy ± 2.5%
• Variety of output voltage level
• Output voltage is in the neighborhood of battery voltage due to the step-up/step-down function
(Ex. getting 3V output using 3V-battery)
• Soft start and driver proof circuit
• Phase conpensation circuit
• Large current can be get by connecting a driving transistor externally.
• Small package ......................... 8 pin SOP

• APPLICATION
• Camera, Video camera, Hand-held audio system.
• Book type personal computer, Word processor, small size office automation equipment.
• Pocket bell, Code-less telephone, Hand-held telephone.

--------------ICO©®DO7-53

I

RS5RJ

• BLOCK DIAGRAM

VIN

EXT
1.....---17

+

VOUT
....--V'J\,f>---+-----151--+

• DESCRIPTION
Pin No.
1

2
3
4

5
6
7

8

Symbol
VSS
CE
VDOUT
VDIN
VOUT
VDD
EXT
LX

Description
Ground
Chip Enable. Set the pin to VDD then the device become standby state.
Output for voltage detector (NMOS open drain output)
Input for voltage detector
Output for voltage regu lator
Output for step-up voltage. Power supply for the device.
Driving output for external transistor
Output for switching

-ICD@®OO-------------7-54

RS5R.J

• ABSOLUTE MAXIMUM RATINGS (Ta = 25°C, Vss = OV)
Rating

Unit

Power Supply Voltage

VDD

-0.3-12

V

Output Voltage LX Pin

VLX

-0.3-12

V

Parameter

Symbol

EXT Pin

VEXT

-0.3-VDD+0.3

V

VOUT Pin

VOUT

-0.3 - VDD + 0.3

V

VDOUT Pin

VDOUT

I nput Voltage

VCE

-0.3-12

V

-0.3-VDD+0.3

V

Output Current LX Pin

ILX

250

mA

Power Consumption

Pd

300

mW
°c

Operating Temperature

Topr

-30-+S0

Storage Temperatu re

Tstg

-40-+ 125

Soldering Condition

Tsolder

260°C

°c
10sec

• ELECTRICAL CHARACTERISTICS
• RS5 RJ3624 (3.6V Output)
Vin = 4.0V, Ta = 25°C
Parameter

Symbol

Condition

MIN

No Load

0.9

I nput Voltage

Vin

Holding Voltage

Vinhd

No Load Vin = H -+ L

Output Voltage

Vout

Vin = 4.0V, lout = 5mA

Input Voltage Stability

I1VoutlVin

lout = 1mA, Vin = 0.9V - SV
Vin = 1.SV, lout = 1 - 30mA

Load Stabil ity

I1 Vout/lout

Step-up Output Voltage

Vdd

Max. Oscillating Frequency

fosc

Duty Ratio

DfMAX

Lx Switch on Voltage

VOLl

Lx Switch Leakage Current

lIeak

Detect Voltage

Vdet

Detect Voltage Hysteresis

Vhys

Vin = 1.SV, lout = 5mA

3.51

3.99

TYP

MAX

Unit

10

V

O.S

V

3.60

3.69

V

10

100

mV

10

100

mV

4.10

4.21

100
SO
ILX = 50mA
2.3

VD Output on Voltage

VdOL

CE "H" Input Voltage

VCEH

CE "L" Input Voltage

VCEL

CE "H" Input Current

ICEH

CE = 3.5V

0

CE "L" Input Current

ICEL

CE =OV

-0.5

Consumption Current

lin

Standby Current

Istb

V
kHz

0.5

%
V

2.0

JlA

2.4

2.5

V

120

240

mV

0.5

V

IOL = 5mA
O.S VDD
0.5

VDD

V

0.2VDD

V

1.0

JlA

0.5

JlA

30

JlA

Vin=SV(Step·down). No Load

10

JlA

Vin = 3V, No Load

1

JlA

Vin=3V (Step·up). No Load

15

--------------ICD©®[]{]7-55

I

R55R..J

• SELECTION GUIDE
You can define the output voltage, the detect voltage and the taping direction of RSSRJ series.
The devices are defined by the following characters.
RSSRJ X X X X X-X +- Type number

t t t t
abc

d

Meaning

Number
a
b

Defines output voltage (Vout).
• The range for Vout is 2.0V to 6.0V in units of 0.1 V, with an accuracy of ±2.S%.
Defines detect voltage (-Vdet).
• The range for - Vdet is 2.0V to 6.0V in the units of 0.1 V, with an accuracy of ±2.S%.

c

Defines version.

d

Defines taping direction with T1 and T2. (See below)

Note) Taping Information (1000 pieces/reel)

¢1,55 ±0.05

000 0

T1 Type

T2 Type
(Unit: mm)

-IIO©®OO------------------:7-56

RS5RJ

• PACKAGE DIMENSION (Unit: mm)

M

o

+1

c-.>


""
o

+1

1.27

<:>
""
o

I

0.4± O.l

--------------ICO©®OO7-57

ICD©®o{]

I

PRELIMINARY I

ES-112-9205

PWM STEP-UP SWITCHING REGULATOR

Product News \'-__R_H_S_R_H_X_X_I_A_I_X_X_2_B_s_e_r_ie_s_ _ _ __
RH5RHxx1A/xx2B Series ICs are PWM control step-up switching regulators developed with CMOS
technology.
The xx1 A Series ICs consist of an oscillator circuit, PWM control circuit, control transistor (Lx switch),
reference voltage source, error amplifier circuit, phase correction circuit, voltage detection resistor,
slow start circuit, and Lx switch protection circuit.
Unlike other PWM switching regulator ICs, the xx1A Series ICs do not require complex external
circuits.

Only three components - coil, diode, and capacitor - are required for the low-ripple, high-

efficiency step-up switching regulator ICs.
The xx2B ICs internally use the same chip as the xx1A Series, but have an external transistor drive
pin (EXT) instead of an Lx pin.

Attaching an external power transistor with a small ON resistance

allows large current to flow in the coil, thus achieving a large output current. The xx2B Series ICs are
suitable for applications that require large output current between 10 mA and 100 mAo
The new PWM control circuit suppresses the self-power consumption of these ICs to Typ. 30 f.lA
(5V models), which compares to VFM (chopper) control type switching regulators that consumes
relatively low power.
When the input voltage is higher than the specified output voltage plus the voltage drop in the diode
coil, the oscillator circuit stops to reduce its own power consumption to Typ. 2 f.lA.
These ICs are suitable for users who need low ripples but cannot use conventional PWM switching
regulators because of high power consumption.
The high performance and low power consumption of these ICs makes them suitable for batteryoperated devices .
•

FEATURES
• Only 3 peripheral parts ..................... Coil, diode, capacitor
• Low consumption current ................... 30 f.lA (Typ. 501 A)
• Small ripple, Low noise
• Low voltage operation (Output current 1 mAl ... 0.9V (Max.)
• High output voltage accuracy ................ ±2.5% (Max.)
• High efficiency ........................... 85% (Typ.)
• Small temperature drift of output voltage ....... ±50 ppm (Typ.)
• Slow· start .............................. 500 f.lS (Min.)
• Compact package ......................... Mini power mold (SOT-89 3 pin)

•

APPLICATIONS
• Constant voltage supply for battery-operated devices
• Constant voltage supply for cameras, camcorders, electronic, and portable communication devices
• Constant voltage source for devices that require low noise and low power consumption such as
portable audio equipment
• Constant voltage source for devices that require a higher voltage than battery voltages

7-59

I

RH5RH

•

BLOCK DIAGRAM

II

VLx limiter

...

,--s_'lo_w_sta_rt---.JH Vref.
.----....., ....,.--~ Vout

Yin
+

The gain of the Error. Amp. is 80 dB. The internal Phase Compo circuit yields a frequency characteristics where the 1st pole is at 0.05 Hz and zero point is at 500 Hz. And the dividing resistor and
capacitor connected to Vout pin yields a zero point at fz = 1.5 kHz.
•

PIN CONFIGURATION

~
2

•

Pin No.
xx1

xx2

1
2

1
2

3

-

•

3

PIN DESCRIPTION

3

Name

Description

Vss
Vout
Lx
EXT

Ground
Voltage Output
Switching pin (Open Drain)
Transistor drive pin (CMOS output)

RH5RH Series

RH5RHm~~~o,

~outPut

voltage
Example: RH5RH501A ... Output Voltage 5.0V (Transistor mounted)
RH5RH352B ... Output Voltage 3.5V (Transistor connected externally)

7-60

RH5RH

.ABSOLUTE MAXIMUM RATINGS
(Vss = OVI
Parameter

Rating

Unit
V

Vout Voltage

Vout

12

Lx Voltage

VLx

12

V

VEXT

-0.3 - Vout + 0.3

V
mA

EXT pin Voltage
Lx Output Current

•

Symbol

ILx

250

EXT pin Current

IEXT

±50

mA

Power Dissipation

Pd

500

mW

Operating Temperature

Topr

-30-+80

·C

Storage Temperature

Tstg

-40 - +125

·C

ELECTRICAL CHARACTERISTICS

RH5RH501A

(Vout= 5VI

Parameter

Symbol

Condition

Input Voltage

Vin

Starting Voltage

Vst

lout = 1 mA, Vin : 0 -+ 3V

Holding Voltage

Vhld

lout = 1 mA, Vin : 3 -+ OV

Current Consumption 1

Iddl

at Vout pin

Current Consumption 2

Idd2

at Vout pin, Vin = 5.5V

Output Voltage

Vout
VLx = 0.4V

Lx Leakage Current

ILxL

VLx = SV, Vin = 5.5V

Oscillating Frequency

fosc

Max. Duty Ratio

Maxdty

Efficiency
Slow start Time
V Lx Limit Voltage

Condition: Vin

on (VLx "L"I

Effi

Max.

Unit

8

V

0.8

0.9

V

30

45

!J.A

2

5

!J.A

5.000

5.125

0.7

4.875

ILx

Lx Switching Current

Min.

Typ.

V

0.5

!J.A

40

50

60

kHz

70

80

90

%

70

85

tst

Time for Vout = 0 -+ 5V

0.5

2.0

VLxlmt

Lx Switch on

0.S5

0.8

7-61

V

•

mA

80

= 3V, Vss = OV, lout = 10 rnA, Ta = 2S·C (See Fig. 1)

Note

%

1.0

ms

1

V

2

RH5RH

(Vout = 5V)

RH5RH502B
Parameter
Input Voltage

Symbol

Condition

Min.

Typ.

Vin

Max.

Unit

S

V

Starting Voltage

Vst

EXT no Load, Vout : 0 -+ 3V

0.7

0.8

V

Current Consumption 1

Iddl

EXT no Load, Vout = 4.SV

60

gO

IlA

Current Consumption 2

Idd2

EXT no Load, Vout = 5.5V

2

5

IlA

Output Voltage

Vout

5.000

5.125

4.S75

V

EXT "H" Output Current

IEXTH

VEXT = Vout -0.4V

-2

mA

EXT "L" Output Current

IEXTL

VEXT=0.4V

2

mA

SO

100

120

Maxdty

VEXT"H"

70

SO

90

tst

Vout = 0-+ 5V

0.5

2.0

Oscillating Frequency
Max. Duty Ratio
Slow start Time

fosc

Condition: Vin = 3V, Vss = OV, lout = 10 mA, Ta = 25°C (See Fig. 2)

7-62

Note

kHz
%

ms

Note 1

RH5RH

RH5RH301A
Parameter
Input Voltage

Symbol

Condition

Starting Voltage

Vst

lout = 1 mA, Vin : 0 -> 2V

Holding Voltage

Vhld

lout = 1 mA, Vin : 2 -> OV

Current Consumption 1

Iddl

at Vout pin

Current Consumption 2

Idd2

at Vout pin, Vin = 3.5V

Output Voltage

Vout

Lx Switching Current

Typ.

Max.

Unit

8

V

0.8

0.9

V

15

25

JJ.A

2

5

JJ.A

3.000

3.075

VLx = O.4V

Lx Leakage Current

ILxL

VLx = 6V, Vin = 3.5V

Oscillating Frequency

fosc
Maxdty

0.7

2.925

ILx

Max. Duty Ratio

Min.

Vin

V

0.5

JJ.A

50

60

kHz

70

80

90

%

70

85

%
ms

Note 1

V

Note 2

Efficiency

Effi

Slow start Time

tst

Time for Vout = 0 -> 5V

0.5

2.0

VLxlmt

Lx Switch

0.65

0.8

V Lx Limit Voltage

V
mA

60

40
on (VLx "L")

Note

1.0

Condition: Vin = 2V, Vss = OV, lout = 10 rnA, Ta = 25°C (See Fig. 1)

I

7-63

RH5RH

(Vout = 5V)

RH5RH302B
Parameter

Symbol

Input Voltage

Condition

Min.

Typ.

Vin

Max.

Unit

8

V

Starting Voltage

Vst

EXT no Load, Vout : 0 .... 2V

0.7

0.8

V

Current Consumption 1

Iddl

EXT no Load, Vout = 2.9V

30

50

fJA

Current Consumption 2

Idd2

EXT no Load, Vout = 3.5V

2

5

fJA

Output Voltage

Vout

3.0

3.075

2.925

EXT "H" Output Current

IEXTH

VEXT = Vout -O.4V

-1.5

EXT "H" Output Current

IEXTL

VEXT= 0.4V

1.5

Oscillating Frequency
Max. Duty Ratio
Slow start Time

Condition: Vin

fosc

80

mA
100

120
90

VEXT"H"

70

80

tst

Vout =0 .... 3V

0.5

2.0

lout = 10 mA, Ta

V
mA

Maxdty

= 2V, Vss = OV,

Note

kHz

%
ms

Note 1

= 25°C (See Fig. 2)

Note 1: The slow start circuit follows the sequence below:
Vin application .... Vref is kept at OV for about 200 fJs .... During this period, error amplifier
output is brought to "H" .... Vref rises and then the error amplifier output gradually lowers
to the appropriate value due to the internal phase compensator circuit. Accordingly, the
output gradually lowers.
Note 2: I Lx gradually rises after the Lx switch is turned on, and VLx rises accordingly. If the voltage
reaches V Lxlmt, the Lx switch protection circuit turns off the Lx switch.

7-64

RH5RH

•

CIRCUIT EXAMPLE
1.

RH5RHxx1A
Diode

Vout
Voutt----"1t--.....

'---+--i Lx

+

Vss

Parts

Coil

: 120/iH (Sumida Electric Company Ltd. CM-5)

Diode

: MA721 (Matsushita Electronics Corp. type Schottkey)

Capacitor

: 22/1 F (Tantalum type)

Fig. 1
2.

RH5RHxx2B
Coil
Diode

Vout
Vout t---2V

0.7

0.8

V

Current Consumptin 1

Idd 1

EXT No Load, Vout=2.9V

30

50

IlA

Current Consumptin 2

Idd 2

EXT No Load, Vou=3.5V

2

5

IlA

EXT"H" Output Current

IEXTH

VEXT=Vout-O.4V

-1.5

mA

EXT"H" Output Current

IEXTL

VEXT=O.4V

1.5

mA

Max Oscillating Frequency
Duty Ratio

fosc
maxdty

VEXT"H"

80

100

120

kHz

65

75

85

%

Condition : Vin=2 V, Vss=O V, lout= 10 mA, Ta=25°C (See Fig. 2)
Note

: The ILx increases steadily after the Lx switch is set to ON due to use of an external coil. The.
accompanying VLx also increases. When the VLx reaches the VLxlmt, the Lx switch is set to
OFF by the protective circuit.

-IID@®[][]---------------7-74

RH5RI

• CIRCUIT EXAMPLE
RH5RI x x 1B
Coil

Vout
Voutt--+-.....

I

+

Fig.1
Parts

Coil··· ............... 821l H

(Sumida Electric Company, CM - 5)

Diode ............ , .. MA721

(Matsushita Electronics Corp. Schottkey type)

Capacitor········· 221l F

(Tantalum type)

RH5RI x x2B
Coil

Diode

Vout
Voutl----+-.....

EXT

+

I
Fig.2
Parts : Coil ....................................... 281l H

(Troidal Core Type)

: Diode··············· ... ............ ...... HRP22

(Hitachi Schottkey Type)

: Capacitor······ ... ......... ... ... ... ... 100 Il F

(Tantalum Type)

: Transistor······························ 2SD1628G
Base Resistor ........................ 300n
: Base Capacitor························ 0.01 Il F

---------------ICD@®[]{]-

RH5RI

• OUTPUT CURRENT and PERIPHERAL COMPONENT
The following describes the interaction between the output current and peripheral components in the
circuit of Figure 1.
With a coil inductance set at L, the maximum current during intermittent mode ( VFM normal operating
mode) is
10ut=Vin' . maxdy' / {20000 . fosc . L' (Vout - Vin )}
At this time the peak current flowing through the Lx switch coil diode is
ILxmax=Vin . maxdty / ( 100 . fosc . L)
The ILxmax is an important I/O power factor that must be considered when choosing the peripheral
components.
The above are calculations under ideal conditions and do not include losses in the external components and the Lx switch which may, in fact, amount to between 50 and 80 percent. Caution is particularly needed at times such as when the ILx is large and Vin is low as Vin loss will occur due to VLx.
It is also necessary to take into account the amount of diode Vf ( about 0.3 V) for calculating the actual Vout.
When ILx and Vlx become a problem, use the RH5RI x x 2B and utilize a peripheral transistor with
low resistance while switched on.

-ICO©®OO---------~----7-76

RH5RI

• NOTICE
Observe the following precautions when using this IC.
• Locating external components as closes as possible to the IC and keep the wiring short. In particular, capacitor wiring connected to the Vout terminal should be kept to a minimum length.
• Make sure ground wiring is of sufficient strength as a large current will flow at the Vss terminal
due to transistor switching. When Vss wiring impedance is high and the IC's internal electrical
potential deviates due to current switching, device operation can become unstable.
• Make sure the capacitor has a capacitance of at least 10 J..l F and has good high frequency characteristics such as obtained with a tantalum capacitor or aluminum electrolytic and ceramic capacitor.
When choosing the capacitor, it is recommended that it be able to withstand a voltage at least three
times higher than the normal capacitor voltage o.utput since a high voltage spike may be generated
from the coil when the Lx transistor is

o~.

• Care is also required when selecting the coil. Select a coil with low resistance to direct current,
adequate current carrying capacity and resistance to magnetic saturation. The ILx may exceed its
absolute maximum rated value during a maximum load when the coil inductance value it too low.
Therefore, please select a suitable inductance value ( reter to page 8 ).
• When choosing a diode, select a high speed switching Schottky type .
.Ensure it has adequate. current carrying capacity ( refer to page 8).

'*

The performance of the power supply circuit using this IC is greatly influenced by the peripheral circuit. Ensure that the component parts for the peripheral circuit have the correct circuit values needed
before use.
It is essential that allowance is made in the circuit design so that the rated velues ( voltage, current
and power) are not exceeded in each part of the circuit board and IC.

---------------ICO©@[j{]7-77

•

RH5RI

• PACKAGING INFORMATION
1. The packaging method is specified with device model number as follows.
RH5RI 301 B • T1 : Taping
RH5RI 301 B· T2 : Taping
2. Taping method

000

0

I!ll"'
C::Ylbd];==;;=;;=lbd]=n== c::n=~~~:::;:r::=
lbd] lbd] =hh
T1 Type

T2Type

• PACKAGE DIMENSION
•
I

~g:

n

1.5±0.1

•I

4.5±0.1
1.S±0.1

1.1

-G]

======!=======i.

c:oZ

o:!i

I

1 104 +0.03
-t-t-. . 0.05

@

- . IIO©®[JI]~-------------7-78

! ! ! I! ! ! C! ! ! ! ! ! O! ! ! ©! ! ! ! ! ! ®! ! ! O! ! ! ! ! ! []{]! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ~/DC/DC

MULTI'POWER

RF5C133

S~;;~

RF5C133 is a power circuit controller IC containing three CMOS process DC/DC converter control
circuit systems (two ON-time control PWM systems and one OFF-time control VFM system).
With additional components, can RF5C133 configure three SWR systems to generate the CPU power
supply voltage, charging voltage, or circuit power supply voltage from AC adapters, dry batteries, or
rechargeable batteries. Furthermore, RF5C133 has the following six functions:

1. With the built-in power supply voltage detector, RF5C133 outputs low voltage alarms for dry or
rechargeable batteries and for the CPU power supply. (Alarms for batteries are output in frequencies. A V /F converter'converts the voltages into frequencies.)
2.

RF5C133 controls the charging of rechargeable batteries by AC adapter output. The batteries are
charged by a constant current initially, then by a constant voltage after the upper limit voltage
is reached.
ba~teries

The values for the constant current and voltage are specified externally.

While the

are being charged, R F5C133 outputs charge indication signals. Upon detection of a low

charge current, R F5C133 stops the signals.
3. To protect the charge system, RF5C133 detects and latches output overcurrents and set heating
(an external diode must be added externally) and sends alarms. The alarms are released at the rising
edge of charge control input signals.
4. The power saving function turns off the circuit power supply voltage generator.
5.

RF5C133 can be soft-started to prevent rush current occurring when the output in the circuit or
charge system rises.

6.

RF5C133 can operate based solely on the internal clock. After self-activation, external sync clocks
can be input.

•

I

FEATURES

• Step-up, step-down, and inversion DC/DC converters can be easily designed by combining RF5C133
with coils, capacitors, and diodes.
• Low current consumption .......................... 25 p.A (Typ., stand-by)
• High efficiency .......................................... 70% to 80% (Typ., depends on circuit configuration)
• Accurate output voltage ............................ ±5%
• Small temperature drift of output voltage. ± 100 ppm! C
• Package ..................................................... 24-pin shrink SOP

•

APPLICATIONS

Voltage control for portable CD players, electronic book players, video equipment, notebook personal
computers, and other battery-operated equipment.

---------------ICD©®OO7-79

RF5C133

•

PIN CONFIGURATION

VSS

VFIN
VFOUT

CPU RST

SYNCCLK

CPU VDD
VDDIN

CR

VDDDRV

CIRDRV
GND

GND

oun

ERR

CHG DRV

ERRINl

CHGCUR+

PCON

CHG CUR-

ALM OUT

ERR OUT2

CHG CON

ERRIN2

CHG DPY

TEMP SENS

• PIN DESCRIPTION
To use pins marked *, pull up the signals to the "H" level.
Pin No.

Signal Name

Pin Name

1/0

Description

1

VF IN

VF Converter

Input

Connect to the positive pole of a dry or rechargeable battery. During
operation of the circuit or charge system, the potential of the dry or
rechargeable battery is detected at this pin.

2

VF OUT'

VF Converter

Nch Open
Drain Output

The potential (1.8 to 3.3 VI detected at VF lili is converted into a
frequency (1/(4096 X 321 to 1/(4096 X 21 of the external or internal
clock OSC21 and output through this pin.

3

SYNC CLK

Synchronized Clock

Input

To synchronize the operation of circuit or charge SWR with an external

clock, sync clock signals are input through this pin (176 kHzl. The
external and built-in clocks are switched automatically. A pull-down
resistor is built in.

4

CR

CR

Input

5

CIR DRV

Circuit

CMOS
Output

ON-time control PWM.

GND

This is the power grounding pin to feed the source current to CIA

SWR Drive

Use an external CR to specify the oscillating frequency for the circuit
or charge systems or to specify the maximum duty of the circuit
system.
Through this pin, the driver transistor for the circuit SWA is driven by

6

GND

7

ERA OUT1

Error Amp.
Output 1

Output

The error output of the circuit power supply voltage is amplified and
output through this pin. To adjust the feedback constant, use the C

8

ERRIN1

Error Amp.
Input2

Input

The error voltage of the circuit power supply v'oltage is detected at this
pin. To specify the circuit power supply voltage, use an external
resistor.

DRV.

and R externally attached between ERR IN1 and this pin.

-IID®®[}[]-------------7-80

RF5C133

Pin No.

Pin Name

1/0

Signal Name

Description

= "H",

9

P CON

Power Save Switch

Input

10

ALM OUT'

Alarm

Nch Open
Drain Output

11

CHG CON

Charge Control

Input

When CHG CON = "H", charging is possible. The ALM OUT output
is reset at the rising edge of CHG CON = ilL" --+ "H". A pull-down

12

CHG DPY •

Charge Display

Nch Open
Drain Output

When a normal charge current is detected while CHG CON = "H",
signals are output through this pin.

13

TEMPSENS

Temperature Senee

Input

This pin is used to feed a forward current to an external diode. According to the temperature characteristics of the VF of the diode, abnormal
heat is detected. A regulated current source from internal Vref (2 VI is
built in.

14

ERRIN2

Error Amp.
Input 2

Input

The error voltage of the charge power supply voltage is detected. To
specify the voltage and temperature characteristics of the charging
source, add an external resistor and diode.

15

ERR OUT2

Error Amp.
Output 2

Output

The error voltage of the charge power supply voltage is amplified and
output through this pin. To adjust the feedback constant, use the C
and R externally attached between ERR IN and this pin.

16

CHG CUR-

Charge Current (-)

Input

The current of the charge system is detected at this pin. Attach an
external resistor (D.SS'l) between CHG CUR+ and this pin to detect
the current.

17

CHG CUR+

Charge Current (+)

Input

The current of the charge system is detected at this pin. Attach an
external resistor (D.SS'l1 between CHG CUR- and this pin to detect
the cu rrent.

18

CHG DRV

Charge SWR Drive

Nch Open
Drain Output

Through this pin, the driver transistor for the charge SWR is driven by
ON·time control PWM.

19

GND

GND

This is the power grounding pin to feed the source current to the
charge system and CPU power supply drive.

20

VDD DRV

VDD SWR Drive

Nch Open
Drain Output

Through this pin, the SWR for the self-bias and CPU power supply
system is driven by OFF-time control VFM.

21

VDD (lC)

VDD(lC)

Input

The voltage obtained by SWR through VDD DRV (Typ. 4.0 V) is
input to this pin. This voltage is used as the potential of the IC board
(lC power supply potential).

22

CPU VDD

CPU Power Supply

Output

A constant voltage (Typ. 3.5 V), obtained by stepping down the
VDD (tCI voltage with a series regulator, is output through this pin.

23

CPU RST'

CPU Reset

Nch Open
Drain Output

The CPU VOD output voltage is detected at this pin. When the voltage
becomes lower than the specified value (Typ. 2.4 Vl, signals are output
through this pin.

24

VSS

VSS (lC)

GND

This is the internal logic grounding of the IC. Connect to the grounding.

When P CON

the circuit power supply voltage generator circuit

stops. A pull-up resistor is built in.
When a 1 Qvercurrent or 2 TEMP SENSE input abnormality (of the
AC adapter output) is detected and latched, an alarm is output through

this pin.

resistor is built in.

--------------ICD©®OO-

I

RF5C133

•

BLOCK DIAGRAM

-IIO©®DD-------------7-82

RF5C133

• DESCRIPTION
1. Internal Oscillator
OSCl (OSCl and OSC2 are asynchronous.)
OSCl is an oscillator circuit using a ring oscillator. (Typ. 100 kHz, ON-time duty is Typ. 65%.)
• OSCl generates clock signals for VDD (CPU) VFM operation. The VDD (CPU) PWM operation
generates the power supply voltage (VDD) for RF5C133 between the external diode and capacitor.
• OSCl is activated by applying the minimum operating voltage or a higher voltage to the VDD (IC)
pin@
OSC2
OSC2 is an oscillator circuit by means of external C and R. (Typ. 130 kHz)
• OSC2 generates clock signals for the PWM operation of the circuit and charge systems.
• Connect C and R between CPU VDD @ and VSS @. C = 470 pF (±5%) and R = 18 kn (±0.5%).
• OSC2 is activated when P CON
is set to "l" or CHG CON @ is set to "H".

®

2. Clock Switch
This circuit switches internal and external clocks. (OSC2 -+ SYNC ClK)
• To synchronize the PWM operation of the circuit and charge systems with an external clock, input
external clock signals to SYNC ClK pin@. (Typ. 176 kHz)
• Upon detection of the rising edge of external clock signals ("l" -+ "H"I, the clock for the IC is
switched from the internal clock (Typ. 130 kHz) to an external clock (Typ. 176 kHz).

3. Start-up Sequencer
The start-up sequencer prevents the rush current from entering the coil when the circuit or charge
SWR is activated.
• The circuit SWR is soft·started when P CON
goes "l".
• The charge SWR is soft-started when CHG CON @ goes "H".
• When P CON
= "l" and CHG CON @ = "H" compete, priority is given to the first to be input.
• If the interval between the two inputs is within 252.1 msec, the two outputs change simultaneously.
See the table below.
• If the interval between the two inputs is over 252.1 msec, output for the later input starts after a
delay of 0 to 252.1 msec.
• The table below shows the change of driver output duty at OSC2 = 130 kHz.

®

®

Time after Priority Signal Input (OSC2 ClK)
0 252.1 283.6 315.1 -

252.1
283.6
315.1
346.6

msec
msec
msec
msec

(4096
(4096
(4096
(4096

x
x
x
x

8 ClKS)
9 ClKS)
10 ClKS)
11 ClKS)

Driver Output Duty Ratio
OFF
1/8
2/8
3/8

:

:

(MAX. 504.1 msec, 4096 x 16 ClKS)

Normal PWM Wave Form

-------------ltD®®[J{]7-83

I

RFSC133

4. Circuit PWM
The circuit PWM circuit controls the circuit SWR ON·time.
• To determine the circuit constant, externally attach resistors Rl, R2, R3, R4, and R5 and capacitor
C1.

• The PWM circuit detects the error between the circuit voltage *Rl/(Rl + R2) and the reference
voltage in the IC (Typ. 1.5 V), and amplifies the error voltage by multiplying by R5/R3. Then,
based on the voltage integrated by the time constant of Cl x R4, PWM control is performed.
• The above voltage is compared with the CLOCK SWITCH output voltage. The CI R D RV output is
set to ON while the above voltage is higher than the clock switch output Voltage. The ON·timing
for the output is synchronized with the clock switch output.
• The maximum duty (at maximum load) is determined by external C7 and R12.
When C7 = 470 pF and R12 = 18 kn
Maximum duty = 84% (at 176 kHz external clock)
Maximum duty = 62% (at 130 kHz internal clock)
• The audio PWM circuit is activated when P CON
is set to "L".
• The C-MOS output is used as the driver of the audio PWM circuit.
• The mask option can be used to invert the output signals. This does not affect the drive performance.
• To soft-start the audio PWM circuit, use the start-up sequencer.
• During stand-by, the CI R DRV output@impedance becomes high.

®

5. V-F Converter
The V-F converter converts the voltage applied to the VF IN 1 pin into a frequency during operation of the circuit or charge SWR.
• The V-F converter becomes operable when the P CON
= "L" or CHG CON (jJ) = "H".
• The output "H" width is fixed to 4096 times the external or internal clock (OSC2) cycle.
• When P CON
= "H" and CHG CON (jJ) = "L" simultaneously, the VF OUT@output impedance becomes high.

®

®

VF IN 1 Inp~Voltage
3.3V
3.2 - 3.3 V
3.1 - 3.2 V
3.0- 3.1 V
2.9- 3.0 V
2.8- 2.9 V
2.7 - 2.8 V
2.6 - 2.7 V
2.5 - 2.6 V
2.4 - 2.5 V
2.3 - 2.4 V
2.2- 2.3 V
2.1 - 2.2 V
2.0- 2.1 V
2.9- 2.0 V
1.8-1.9V
1. -1.8V

VF OUT 2 Output Frequency
"H" ; Nch Output OFF
Clock frequency x 1/(4096 x 2)
Clock frequency x 1/(4096 x 3)
Clock frequency x 1/(4096 x 4)
Clock frequency x 1/(4096 x 5)
Clock frequency x 1/(4096 x 6)
Clock frequency x 1/(4096 x 7)
Clock frequency x 1/(4096 x 8)
Clock frequency x 1/(4096 x 9)
Clock frequency x 1/(4096 x 10)
Clock frequency x 1/(4096 x 11)
Clock frequency x 11(4096 x 12)
Clock frequency x 1/(4096 x 13)
Clock frequency x 1/(4096 x 14)
Clock frequency x 1/(4096 x 15)
Clock frequency x 1/(4096 x 16)
"L" ; Nch Output ON

2 Output Duty
1
1/2
1/3
1/4
1/5
1/6
1/7
1/8
1/9
1/10
1/11
1/12
1/13
1/14
1/15
1/16
0

-ICO©®OO-------------7-84

RF5C133

6. Temperature Sensor
The temperature sensor detects heating of the set using the Vf temperature characteristics of the
external diode.
• A regulated current source from Vref in the IC (2 V) is built in (Typ. 100 !lA).
• Approximate VF temperature characteristics of the external diode (sample DAN202U, If = 100 !lA,
measured values)
Ambient Temperature
25°C
50°C

VF
495mV

75°C

36SmV

100°C

302mV

125°C

247 mV

150°C

171 mV

432 mV

• With the target detection voltage value of 210 mA, high temperatures between 100 and 170°C
(range of dispersion) are detected.
• When Vf becomes lower than the detection voltage, the ALM OUT pin output
is latched to

®

"L".
• The temperature sensor is activated when the CHG CON is set to "H". Detection is enabled after
completion of soft-start.

7 . Charge Current Sensor
The charge current sensor detects abnormal charge currents flowing from the charging source to the
rechargeable battery.
• Attach external resistor RS (0.5n) between input pins @ and @.
• Completion of charging is detected when the voltage drop at RS becomes 0.045 V or less (90 mAl.
Upon detection of 0.045 V or a lower voltage, the CHG DPY output @ goes OFF.
is set to "L".
• Output from CHG DPY @ is possible even when PCON
• Overcurrent during charging is detected when the voltage drop at RS becomes 0.6 V or more
is latched to "L".
(1.2 A). Upon detection of 0.6 V or a higher voltage, the ALM OUT output
• During soft-start, overcurrent is not detected.
• For the sensor to operate, the voltage at input pins @ and @ must be 0.5 V to VDD + 0.3 V.
• If pins @ and @ may have a higher potential than pin @, an external resistor of 1 to 10 kn
must be attached to input pins @ and @ to limit the board current flowing into the IC.

®

®

8. Charge PWM
The charge PWM circuit controls the charge SWR ON-time.
• To determine the circuit constant, externally attach resistors R6, R7, RS, R9, R10, and R11,
capacitor C6, and diodes D2 and D3. The diode is used for adjusting the temperature characteristics
of the charge power supply voltage.

--------------IIO©®[J{]7-85

I

~F:5C133

• The PWM circuit detects the error between (charge power supply voltage - Vf·P2 - Vf·D3)xR6/
(R6+R7) and the reference voltage in the IC (Typ. 1.5 V), and amplifies the error voltage by "multiplaying by R11/R9. Then, based on the voltage integrated by the time constant of C6 x R10,
PWM control is performed.
• The above voltage is compared with the CLOCK SWITCH output voltage. The CHG DRV output
is set to ON while the above voltage is higher than the CLOCK SWITCH output voltage. The
ON-timing for the output is synchronized with the clock switch output.
• The maximum duty (at maximum load) is 100%.
• The charge PWM circuit is activated when CHG CON Qj) is set to "H". To soft-start the audio
PWM circuit, use the start-up sequencer.
• When P CON
= "H" and CHG CON Qj) = "H" simultaneously, RF5C133 enters charge mode
and starts constant current charging (300 mAl. During charging, the charge power supply voltage
is varied to maintain the voltage drop at R8 at 0.15 V. When the charge power supply voltage
exceeds the specified Voltage, RF5C133 is automatically switched to constant voltage mode.
• When P CON
"L" and CHG CON Qj) "H" simultaneously, RF5C133 enters constant voltage
operation mode and feeds current to the circuit directly from the charge power supply. When the
rechargeable battery and the AC adapter is used at the same time, current is fed to the circuit while
the battery is charged.
• When CHG CON Q]) = "L", the charge PWM circuit is disabled.

®

®=

=

9. VDD (for CPU) PWM
The VDD PWM circuit controls the VDD DWR OFF-time.
• The VDD PWM circuit is activated by applying the minimum operating voltage or a higher voltage
to the VOD IN @ pin.
• After activation, the VDD PWM circuit fetches a self-rectified voltage at the VDD IN @ pin and
uses it as the power supply voltage.
• If the VDD voltage becomes lower than the detection voltage (fixed to Typ. 4.0 V by a built-in
resistor), the VDD DRV @ output goes ON.
• The output ON timing is synchronized with the OSC1 output.

10. Series Regulator (for CPU)
The series regulator steps down the VDD IN voltage and outputs a constant potential.
• The series regulator steps down the VDD IN @ voltage and outputs a constant voltage through
CPU VDD @
• The output voltage is fixed by a built-in resistor. (Typ. 3.5 V)

11. Voltage Detector (for CPU)
The voltage detector detects drops in the CPU power supply voltage.
• When the CPU power supply voltage drops to the detection voltage or lower, the CPU RST output
goes ON.
• The detection voltage is fixed by a built-in resistor. (Typ. 2.4 V)

-IIO®®OO·-------------7-86

RF5C133

•

ABSOLUTE MAXIMUM RATING
Parameter

Symbol

Rating

Unit

VDD

-0.3-6

V

VOUTI
VOUT2

VSS-0.3 - VDD+O.3
VSS-0.3 - 12

V
V

VIN

VSS-0.3 - VDD+0.3

V

IOUTl
IOUT2
IOUT3

MAX. 200
MAX. 200
MAX. 100

mA
mA
mA

Pd

MAX. 500

mW

Operating Ambient Temperature

Topr

-30-80

°c

Storage Temperature

Tstg

-40 -125

°c

Tsolder

260°C 10 sec

Power Supply Voltage
Output Voltage
1. CMOS Output
2. Nch Open Drain Output
Input Voltage
CMOS Input
Coil Drive Output Current
1. Circuit (Circuit PWM Output)
2. Charge (CHG. PWM Output)
3. CPU (VDD. PWM Output)
Power Consumption

Soldering Temperature

•

RECOMMENDED OPERATING CONDITION of RF5C133 and EXTERNAL CIRCUIT
Parameter

.,
~

MIN.

TYP.

MAX.

Unit

AIC Adapter Output Voltage

5

V

Dry Battery Output Voltage

3

V

Storage Battery Output Voltage

4

V

O. Internal Power Supply Voltage (Self·Generated)

4

V
V
mA
V
mA

:;:
0
c..

...
~

Co

-=

.,

1. Circuit 1
(External Tr. necessary)

Power Supply Voltage
Power Supply Current

...

Circuit 2
(External Tr. necessary)

Power Supply Voltage
Load Current

5.8
70
3.5
100

2. Charge
(External Tr. necessary)

Power Supply Voltage
Load Current

5
300

V
mA

3. CPU

Power Supply Voltage
Load Current

3.5
10

V
mA

~

~

c..
~

...

Co
~

0

--------------IIO©@[j[]7-87

I

RF5C133

•

ELECTRICAL CHARACTERISTICS
VDD = 4.0V,

O°C::;;; Ta ::;;; lO°C,

the TYP values are measured at

®@ @ @,~@@)

1. INTERNAL OSCILLATOR (Associated Pin No.
Symbol

Parameter

Condition

OSCl Oscillation Start Voltage

VOSClst

VDD Rise

OSCl Oscillation Frequency

fOSCl

Ta

= 25'C

OSCl Oscillation Duty

DOSCl

OSC2 Oscillation Start Voltage

VOSC2nd

VDD Rise

OSC2 Oscillation Frequency

fOSC2

C7

2. CLOCK SWITCH (Associated Pin No.

25°C.

MIN.

90
60

= 470pF, R12 = 18 kn

TYP.

MAX.

0.65

1.8

V

100

110

kHz

Unit

65

70

%

1.35

1.8

V

100

130

160

kHz

@@]XID@@)

Parameter

Condition

Esternal Clock Frequency

3. START UP SEQUENCER (Associated Pin No.

Parameter
. IIStart)
SOFT START Valid Range I
lEnd)

MIN.

TYP.

MAX .

Unit

tST

OSC2

= 130 kHz

242

252

262

ms

tEND

OSC2

= 130 kHz

484

504

524

ms

MIN.

TYP.

MAX.

Unit

VDD

V

1.6

V

0

VDD

V

GND

VDD

V

4. CIRCUIT PWM (Associated Pin No.
Parameter

@(§):])@@@)

Symbol

Condition

~®:ID@ @)
Symbol

Condition

Error Amp. Input Voltage Range

VINTERl

0

Error Amp. Input Reference Voltage

VREFERl

1.4

Error Amp. Output Voltage

VOUTERl

PWM Driver Supply Voltage Range

VDRVl

PWM Driver Nch ON Voltage

VOLl

101 = 50 mA

PWM Driver Pch ON Voltage

VOHl

loh = -5 mA

5. V-F CONVERTER (Associated Pin No. ~@
Parameter

Symbol

1.5

0.22

0.5

V

VDD-0.5

VDD-0.25

VDD

V

MIN.

TYP.

MAX.

Unit

@)
Condition

Input Voltage Range

VINVF

0

VDD

V

Detect Voltage Set Range

VDVF

1.8

3.3

V

Detect Voltage Set Step

VUNITVF

Output Frequency Range

fVF

C LK

Output ON Voltage

VDlVF

101 = 5 mA

0.09
~

OSC2/4096 I kHz)

0.1

CLK/16

0.3

0.11

V

ClK/2

kHz

0.5

V

-ICD®®OO-------------7-88

RF5C133
6. TEMPERATURE SENSOR (Associated Pin No.

® @ © @ 13)

Symbol

Parameter
Input·Const. Current

ITMP

Input·"L" Detect Voltage

VDTMP

Detect Voltage Hysteresis Width

llVDTMP

Condition

TEMP SENS

7. CHARGE CURRENT SENSOR (Associated Pin No.

@ ~ OV

MIN.

TYP.

MAX.

Unit

50

100

200

I'A

0.155

0.21

0.265

V

10.5

21

42

mV

®® @ @ @ ® @@ 13 )

The current values are transformed into the voltage fall through the external resistance and shown as below.
Parameter

Symbol

MIN.

TYP.

MAX.

0.027

0.045

0.063

V

llVDCMIN

3

6

12

mV

Charge Detect Current

VDCMIN

Charge Detect Current Hysteresis

Condition

Unit

Width

Over eu rrant Detect
Over

eu rrant

Detect Hysteresis Width

Input Voltage Range

VDCMAX

0.5

0.6

0.7

V

llVDCMAX

30

60

120

mV

VINCUR

0.5

VDD+0.3

V

MAX.

Unit

VDD

V

1.6

V

8. CHARGE PWM (Associated Pin No.
Parameter

@ (j3l @ ® @ ® @ @ 13)
Symbol

Error Amp. Input Voltage Range

VINER2

Error Amp. Input Reference Voltage

VREFER2

Con st. Current

Condition

MIN.

TYP.

0

VREFCC

R8 = 0.5on

1.4

1.5

0.12

0.15

0.18

V

Error Amp. Output Voltage Range

VOUTER2

0

VDD

V

PWM Output Supply Voltage Range

VDRV2

0

10

V

PWM Output ON Voltage

VDL2

PWM Output Leakage Current

IOH2

Reference Voltage for

9. VDD (for CPU) PWM (Associated Pin No.
Parameter

101 = 50 mA

0.5

V

0.01

10

I'A

TYP.

MAX.

Unit

10

V
V

@ ® @ 13 )

Symbol

PWM Output Supply Voltage Range

VDRV3

Output Voltage

VOUTVDD

PWM Driver ON Voltage

VOL3

PWM Driver Leakage Current

VOH3

Condition

MIN.

3.9

4.0

4.1

0.22

0.5

V

0.01

10

I'A

MIN.

TYP.

MAX.

Unit

3.4

3.5

3.6

V

100

mV

101=50mA

10. SERIES REGURATOR (for CPU) (Associated Pin No.
Parameter

0.22

Symbol

@ @ 13)
Condition

Output Voltage I@ Pin)

VCPUVDD

Input/Output Voltage Difference

VDIF

IRL=-10mA

Load Stability

llVCPU

-30 mA

f

IRL

V

0.5

f

0 mA

35

--------------IIO®@[JIJ7-89

I

RF5C133

11. VOLTAGE DETECTOR (for CPU) (Associated Pin No
Symbol

Parameter

@ @ @@)
Condition

MIN.

TYP.

MAX.

Unit

VDD

V

Input Voltage Range

VINRST

0

Input-"L" Datect Voltage

VDRST

2.3

2.4

2.5

V

Detect Voltage Hysteresis Width

"VDRST

60

120

240

mV

TYP.

12. INPUT SIGNAL
Pin including Input Pull·Up Resistance (Associated Pin NO.@ : 250 k!l poly,Si resistance)
Symbol

Parameter
"H" Input Voltage

VIMI

"L" Input Voltage

VILI

Condition

"H" Input Cu rrent

IIHI

VDD = 4.0V. Vih = 4.0V

ilL" Input Current

IILI

VDD = 4.0V. Vii = OV

MAX.

Unit

0.8VDD

MIN.

VDD

V

0

0.2VDD

V

0.01

1

/LA

16

32

/LA

TYP.

8

Pin including Pull· Down Resistance (Associated Pin NO.@@: 250 k!l poly·Si resistance)
Parameter

MAX.

Unit

"H" Input Voltage

VIH2

Symbol

0.8VDD

VDD

V

"L" Input Voltage

VIL2

0

0.2VDD

V

"H" Input Current

IIH2

VDD = 4.0V. Vih = 4.0V

16

32

/LA

"L" Input Current

IIL2

VDD = 4.0V. Vii = OV

0.01

1

/LA

TYP.

MAX.

Unit

Condition

MIN.

8

13. OUTPUT SIGNAL
Nch Open'Drain Output (to CPU) (Associated Pin NO.@@
Symbol

Parameter

@@)

Condition

Output ON Voltage

VOL4

101 =5mA

Output Supply Voltage

VDRV4

(MAX = VDD for

Output Leakage Current

IOH4

MIN.

0.5

V

10

V

0.01

5

/LA

TYP.

MAX.

Unit

1.2

1.8

V

.

V

/LA

0.3

@ pin)

'.

0

14. ICTOTAL (Associated Pin No.@@@@)
Symbol

Parameter
Min. Operating Voltage

VINMIN

Max. Operating Voltage

VINMAX

Current Consumption
*Ta=5o"C
•• Except for Output Driver SINK
Current

Is
100

Condition

MIN.

6
Vin = 2.0V. L = 1201lH. C = 221'F
PCON = H, CHGCON = L, No Load

25

60

Vin = 2.0V, L = 120/LH, C = 221'F

**

.*

400

1000

PCON = L, CHGCON = H, No Load

/LA

-IID©®OO-------------7-90

RF5C133
•

EXTERNAL CIRCUIT
1. CIRCUIT STEP-UP DC/DC CONVERTER

2. CIRCUIT POLARITY INVERSE DC/DC CONVERTER

VIN

I
VOUT

--------------IID©®/Xl7-91

RF5C133

3. CHARGE·UP STEP·DOWN DC/DC CONVERTER

4. CPU STEP·UP/STEP·DOWN DC/DC CONVERTER

VOUT

VIN

-ICD©®OO-------------7-92

RF5C133

•

PACKAGE DIMENSION (Unit: mm)

~

0.70 TYP

0-10'

10.2±0.3

o

+1

00

,...;

0.8

0.36±O.l

O.l2~

•
--------------IIO©®[JI]7-93

110 ©(ill [}{]

[Preliminary[

I

Multi - Power - Supply

RS5VEOXX Series

s~;;;'

The RS5VEOXX series are high precision, low current consumption multipower supply ICs. This chip series
internally comprises 4 voltage regulators, 2 voltage ( monitoring) detectors and a control switch
manufactured with CMOS process technology. The device design allows the user to select the ideal power
supply to match his system with a mask option providing features such as user setting of pin terminals
and ON/OFF control of each circuit.
RICOH's unique trimming technology allows the output voltage and detection voltage to be set internally
in the IC. The device package is the SOP 16 pin ( O.Smm pitch) type.

• FEATURES
• Low power consumption·
• Wide operating voltage range ...... ;............................................... 1.5 V-10.0 V
• High accuracy of Output voltage and Detect voltage ........................ ±2.5%
• Voltage selection of output and Detect.......................................... 0.1 V step
• Low temperature coefficient of output and Detect··························· TYP. ± 100 ppm / ·C
• Small input - output voltage difference· .......................................... 50 mV for 10ut=SO mA
• Small packege ........................................................................... SOP 16 ( O.S mm pitch)
• Possible direct connection to CPU due to the built - in level shift circuit

• APPLICATIONS

I

• Constant - voltage power supply for handy communication equipment
• Constant - voltage power supply for battery - powered equipment

• PIN CONFIGURATION

•

(RS5VE001 )

ROUT4
VSEN2

CD

0

PACKAGE DIMENSION
SOP 16 pin 0.8 mm pitch

VDD
ROUT3
0>

VSEVl

Co

RESET

CSW3

o

DouT

CSW2

Roun

CSWl

IBCl

ROUT2

GND

IBC2

1+
i:.>

4A±0.2

6.2±0.3

(Unitmm)

----------------ICD@®[}[]7-95

RS5VEOXX

• SYSTEM BLOK DIAGRAM
• RS5VEOXXX ( Mask option)

• RS5VE001X

VDD~----------~~

r::---,---,._ _-" IBCl
~~___'"--"V

VDDo-------------~__,

Roun

r::---~------'...

IBC1

~~___'"-v--""

R oun

r::---,---,.--....

IBC2

~-'=----'"~~"M

R OUT2

CSWl
r::--,---,._ _.A IBC2
~--"----I--"V

R OUT2

CSW2

ROUT3

ROUT3

ROUT.

ROUT.

CSW3

VSEN1

o--------~

m

o OUT

U)

:::>

VSEN2

RESET "----_--s-==-:o

GND

Cov-----..--""-""'-'--'

RESET
Co

GND

• SELECTION GUIDE
In the RS5VEOXX series the user can specify standard type and a mask option type. Voltage settings
for 6 circuits can each be separately selected. Use the rules in the selection guide below to match your
appli-cation.

-

RS5VEOXXXX

->

Type number

t t tt

abc d
No.

Meaning

a

The RX5VE series ( multipower supply) Ie production serial number.

b

Mask option part production serial number
· 01 is for standard parts
· The mask option part number runs in sequence starting from 02.

c

Voltage setting serial number
• The letters run in sequence from A to Z in order of production.

d

Used for taping selection
• Runs in the E1 and E2 directions.( Refer'to the taping Information).

-IID©®[}[]---------------7-96

RS5VEOXX

• PIN DESCRIPTION
1. RS5VE001 X
Terminal No. Terminal Code
1

ROUT4

2

VSEN2

3

Co

Terminal Description
Voltage regulator 4 output terminal.
Voltage detector 2 output detecting terminal.
Voltage detector 2 terminal for connection to external capacitor for delay s
ettings.

4

RESET

Voltage detector 2 output terminal.Nch open drain output.
Detector "L" is output.

5

DouT

Voltage detector 1 output terminal.Nch open drain output.
At detection "L" is output.

6

ROUT1

Voltage regulator 1 output terminal.This terminal connects to the PNP transistor collector and also comprises an OlJtput voltage detection terminal.

7

IBC1

S

GND

This terminal connects to the base of the PNP transistor externally connected
to voltage regulator 1 for regulation of base current.

9

IBC2

10

ROUT2

11

CSW1

12

CSW2

Ground terminal.
This terminal connects to the base of the PNP transistor externally connected
to voltage regulator 2 for regulation of base current.
Voltage regulator 2 output terminal.This terminal connects to the PNP transistor collector and also comprises an output voltage detection terminal.
Control switch input terminal for ON I OFF of voltage regulator 1. Active "H"
input. Level shift achieved by means of ROUT4 output voltage.
Control switch input terminal for ON I OFF of voltage regulator 2. Active "H"
input. Level shift by means of ROUT4 output voltage.
Control switch input terminal for ON I OFF of voltage regulator 3. Active "H"

13

CSW3

14

VSEN1

Voltage detector 1 Voltage detection input terminal.

15

ROUT3

Voltage regulator 3 output terminal.

16

Voo

input. Level shift by means of ROUT4 output voltage.

Voo terminal.

2. RS5VEOXXX ( Mask Option)
Terminal Description

Terminal No. Terminal Code
2
11
12
13
14

The user can specify the 5 terminal numbers 2, 11, 12, 13, 14 as input termiUser
designated
symbol

nals. See the mask option guide for a terminal description. Descriptions
of other than these 5 terminals are the same as RS5VE001 X ( standard
type ).

-----------------ICD©®DO7-97

I

RS5VEOXX

• MASK OPTION GUIDE
In the RS5VEOXX Series the user can specify the following items.
Description

Item
Viltage detector
terminals 1 or 2
ON /OFF
control for each circuit

ON / OFF control
with toggle input

•
•
•
•
•

(1 input only)

•
User designated
terminals

Output of voltage
detectors 1 and 2

•

•
•
•
•
•
•
•
•

The voltage detector 1 or 2 terminals can be connected to the voltage regulator output ROUT1 ,ROUT2,ROUT3, ROUT4 and VDD.
ON / OFF control of voltage regulators 1 through 4 and voltage detector
1 is done by using 3 AND input.
Direct ON / OFF control of voltage detector 2.
ON / OFF control with AND toggle input and level input of main power supply.
When the edge trigger flip flop ( triggers on rising edge) triggers on power
'supply rise and voltage detector 2 activates, the circuit resets to initial value.
Reset can be triggered at detection with a one - shot pulse or during the
detection period.
Five input terminals can be designated as user terminals.
ON / OFF control input terminals for each circuit.
Voltage detector input I/O terminals 1 and 2.
Designation of active "H" and active "L".
Terminal No.11, can be used as a toggle input for the Schumitt trigger.
The voltage detector 1 and 2 output, RESET or DOUT can be designated
"L" or "H" during detection.
The voltage detector 1 and 2 output, RESET or DOUT can be designated
"L" or "H" during OFF by ON / OFF control.
ON / OFF control of voltage regulators 1 through 4 with the output of voltage detectors 1 and 2.

Functoins of user designated input terminals
User designated input terminals have the functions descrided in the table below.
User terminal

Pin No.

Input terminal functions

User terminal 1

2

Control switch for each circuit, voltage detecion terminals 1 or 2.

User terminal 2

11

Control switch for each circuit, Schmitt trigger input

User terminal 3

12

Only as control switch for each circuit

User terminal 4

13

Only as control switch for each circuit

User terminal 5

14

Control switch for each circuit, voltage detecion terminals 1 or 2.

-ICD®@OO-~-------------7-98

RS5VEOXX

• CIRCUIT DESCRIPTION
1. Voltage Regulators 1 and 2
•

These are series regulators with an external PNP transistor for extracting a large output current

•

The output voltage can be set in 0.1 V steps from 3 to 6 volts by means of trimming.

from a small I/O difference voltage.
•

ON/OFF switching with the control terminal.

•

Use a low saturation type transistor with an hfe of 100 or more. Provide a minimum 10 ~ F capacitor at the output.

2. Voltage Regulators 3 and 4
•

These are CMOS type series regulators of the same configuration as the RICOH three terminal

•

The output voltage can be set in 0.1 V steps from 2 to 6 volts by means of trimming.

•

ON/OFF switching with the control terminal

RX5RA, RX5RE voltage regulator series.

3. Voltage Detector 1
•

This has the same configuration as the RICOH RX5VA 3 terminal voltage detector.

•

The output sets to "L" when a VDD voltage drop is detected. Output is taken from an Nch open drain

•

The following settings can be made with the mask option.

device.
1. Selection for ON/OFF control

2. Selection of an "L" or "H" level output can be made during detection.

3. Selection of an "L" of "H" level output can be made during OFF.
4. The voltage detection terminal can be bonnected to the voltage regulator outputs ROUT', ROUT2,
ROUT3, ROUT4 and Voo.

4. Voltage Detector 2
•

The output sets to "L" when a VSEN voltage drop is detected.Output is taken from an Nch open
drain device.

•

Reset delay settings can be made. Delay time settings can be made with an external CD ( capacitor ).

•

The following settings can be made with the mask option.
1. Selection for ON/OFF control
2. Selection of an "L," or "H" level output can be made during detection.

3. Selection of an "L" or "H" level output can be made during OFF.
4. The voltage detection terminal can be connected to the voltage regulator outputs ROUT1, ROUT2,

ROUT3, ROUT4 and Voo.

----------------IID@®DO-

I

RS5VEOXX

•

Delay time settings are determined by the following formula.
TD=0.69 x RD x CD

Rd is an internal resistor set at 1 MO which gives the following formula.
TD=0.69 x 10' x CD

A block diagram of the RS5VEOOXX delay generator circuit is shown on the next page.
•

Delay generator circuit block diagram.
VSEN

VDD
Canst.
Current

RD

RESET

VREF

VSS

CD
Capacitor

I

5. Main Power Supply Regulation ( Mask Option)
•

Use of an internal edge trigger flip flop ( triggers on rising edge) allows control of the main power

•

When voltage detector 2 senses a voltage drop, the flip flop is reset by means of the one-shot pulse

supply POWER ON/OFF with AND ( gate) toggle input and level input.
generator circuit.( Reset can also be done during the voltage detection period ).

-ltO@®[J[]-----------------

RS5VEOXX

• ABSOLUTE MAXIMUM RATING
Parameter
Input Voltage

Symbol

Rating

Unit

Yin

+ 12

V

150

mA

Output Current

lout

Output Voltage

Vout

Power Dissipation

-0.3

~

Pd

Vin+ 0.3

500

Operating Temperature

Topr

- 30

~

+ 80

Storage Temperature

Tstg

- 40

~

+125

Soldering Temperature

Tsolder

260'C

V
mW

'c
'c

10sec,

• ELECTRONIC CHARACTERISTICS
•

CHIP CHARACTERISTICS
Condition

MIN

Output Voltage select range1 ROUT1.2

0.1 Vstep

Output Voltage select range2. ROUT3.4

0.1 Vstep

VDET

Symbol

Parameter
Operating Voltage range

Detect Voltage select range
•

Symbol

MAX

Unit

1.5

10.0

V

3.0

6.0

V

2.0

6.0

V

0.1 Vstep

2.0

6.0

V

Condition

MIN

MAX

Unit

(ROUT)

(RouT)

V

x 0.975

x 1.025

VDD

TYP

Voltage Regurator 1, 2
Parameter
Output Voltage

RouT1.2

Suppry Current for No Load

Istb1.2

lout = OmA

Invalid Current

lopr1.2

lout =80mA

Input Output Voltage Difference

Vdif1.2

Rout 1,2= 5.0V, lout = 80mA

Load Reguration
Line Reguration

TYP

0.05

f"."Vout Rout 1,2 = 5.0V
1mA ;£ lout ;£ 80mA
f"."Vout Rout 1,2+ 0.3V;£ VDD ;£ 10V

0.05

---

100

IlA

1

mA

0.3

V

50

mV

0.3

%/V

5

mA

6Vin -Vou!

f = 120Hz,

Ripple rate
Limit Current
Temperature Coefficient

lIim

Ripple 0.5Vrms

I B1.2 ( PNP transistor Base Current)

40

±100

6Vout/ u Topr

dB

60

1

ppm/ 'C

Note1: Common condition Voo=6.0 V, lout=50 mA, Co=101l F, Ta=25'C
Note2 : External transistor hfe;;; 100

-----------------ltO©®OO7-101

I

RS5VEOXX

•

Voltage Regurator 3
Parameter

Symbol

Output Voltage

Rout3

Supply Current

Iss3

Input Output Voltage Difference
Load Reguration
Line Reguration

Vdif3

Condition

MAX

Unit

(Rout)

(Rout)

V

x 0.975

x 1.025

MIN

TYP

5.0

10.0

IlA

Rout 3 = 5.0 V, lout = SOmA

0.3

V

f':,Vout

Rout 3 = 5.0V
1mA;:;; lout ;:;; 50 mA

50

mV

f':,Vout

Rout 3 +0.5 V;:;;Voo ;:;; 10 V

0.3

%/V

---

0.05

!Win -Vout

Limit Current
Temperature Coefficient

Ilim3

100

300
±100

L out 16 Topr

mA
ppm/"C

Note: Common condition Voo=6.0 V, lout=30 mA, Ta=25"C

•

Voltage Regurator 4
Parameter
Output Voltage

Symbol
Rout.

Supply Current

Iss4

Input Output Voltage Difference

Vdif4

Load Reguration
Line Reguration

Condition

MAX

Unit

(Rout)

MIN

TYP

(Rout)

V

x 0.975

x 1.025

1.3

3.9

IlA

Rout 4 = 5.0 V, lout = 50 mA

0.3

V

f':,Vout

Rout4 = 5.0V
1mA ;:;; lout;:;; SOmA

50

mV

f':,Vout

Rout3 + 0.5V;:;;Voo ;:;; 10V

0.3

%/V

---

0.05

""Vin -Vout

Limit Current
Temperature Coefficient

Ilim4

100

300
±100

.6.outJf:::.. Topr

mA
ppm/"C

Note: Common condition Voo=6.0 V, lout=10 mA, Ta=25"C

-IIO©®[][]--------------7-102

RS5VEOXX

•

Voltage Detector 1, 2
Parameter
Detect Voltage
Hysteresis

Symbol

Condition

- VOET1.2

MIN

TYP

MAX

Unit

(-VOET)

(- VOET)

V

x 0.975

x 1.025

(- VOET)

VHYS

V

x 0.05

Supply Current

Output Current

Iss5

Voltage Detector 1

1.3

3.9

IlA

Iss6

Voltage Detector 2

1.5

4.5

IlA

Vos = 0.5V, Voo = 1.0V

0.5

Vos = 0.5V, Voo = 2.4V

3.6

VOS = 0.5V, Voo = 3.6V

6.5

louT

Delay Circuit Resistance

Rd

Detect Pin Current

ISEN

Temperature Coefficient

LVout/6Topr

Vos = 0.5V, Voo = 4.6V

8.6

Vos = 0.5V, Voo = 6.0V

11.6

Voltage Detector 2

0.5

mA

1.0

2.0

0.5

2

±100

lout = 10 mA

MO
IlA
ppm/ 'C

Note: Common condition VOD=6.0 V, Ta=25'C

•

Input
Parameter

Symbol

Condition

MIN
- 1

Input Leackage Current

III

Control switch "L" level

V,L

CSW 1

~

4

V,H

CSW 1

~

4

VSIL

Option

VSIH

Option

VHYS

Option

I
I

TYP

I
I

MAX

Unit

1

IlA

Input Current
Control switch "H" level
Input Voltage
Schumitt trigger "L" level

See Reference

V

Input Voltage
Schumitt trigger "H" level
Input Voltage
Schumitt trigger Hysteresis
Voitage

-----------------ICD©®[]{]7-103

I

RS5VEOXX

• PACKAGE DIMENSION

(Unit: mm)

0.60TYP
O~

10

6.S±0.3

• TAPING INFORMATION

(Unit: mm)
40
. +- 0 .1

"":

~l

2.0 + 0.1
6.9

/ 0

0

o

0

0

II re---&

D D \\

-

~5

e- --E11- --1~ -

I

1°1

+

~~

I~O+

I~

12.0 + 0.1

(

ci

i \
~

ci
~ +1'"

N

....

,.:-

0

to

\

I
II)

0

ci

"":

Drawing Direction

c::::::======>
-ICO®®[}o---------------7-104

8. APPLICATION MANUAL

I

Real Time Clock RP5C01/5C15
Application Manual

I

8-1

RP5COl/RP5C15 Application Manual

Contents
1. Specifications of RP5COI
2. Specifications of RP5Cl5
3. Construction of oscillator circuit
4. Power dissipation
5. Connection to CPU
6. CS and CS terminals
7. Reading clock data
8. Writing clock data
9. Use of alarm
10. Setting leap years
11. Test register
12. Week counter
13. Year counter
14. State of RP5COI and RP5C15 at power on
15. Adjustment function
16. Flowchart
17. Items to check after program preparation
18. Malfunction during testing
19. Power supply
20. Differences between RP5COI and RP5C15

8-3

(1) Specifications of RPSCOI

Outline:
The RPSCOI is a real-time clock
that can be connected directly to
the bus of microprocessors using

cs

the 808SA, 280, 6809, 6S02 or other

cpu.

Time can then be written to

ADJ

:e

or read from the clock in the same

"0

way as writing to or reading from

Al

RAM.

A2

As well as calendar and time

0

counters and alarm function, the

A3

RPSCOI has a 26 x 4-bit RAM,

RD

allowing battery backup.

It can

(J1

(J
~

GND

therefore be used as a non-volatile
RAM.
Features:

*

Direct connection to

cpu

* 4-bit bidirectional bus DO-D3

*

4-bit address inputs AO-A3

* Internal counters for time (hours, min., sec.) and date (100
years, leap years, months, days, and days-of-the-week)

* Choice of 24-hour or 12-hour (AM/PM) system

*
*

All clock data expressed in BCD code

*

Provision for battery backup

+30 sec. adjustment function

* Internal 26 x 4-bit RAM
* Alarm signal, 16 Hz clock signal or 1 Hz clock signal output

8-5

•

Terminal connection diagram
Block diagram

OSCIN
OSCOUT

===__+-_-H

i -_ _
L,-..J..,.-L...~-Ly-~-J,,.-J

DO. D1. D2. D3

8-6

ALARM
OUTPUT

ALARM

Absolute max. ratings
vcc

Item
Supply voltage

VI

Inpu t vol tage

symbol

Values

Conditions

-0.3
Vol tage a t any pin

-

+7

Units
V
V

-0.3-Vcc+0.3

with respect to GND
Va
pd

au tpu t vol tage
Max. power com-

V

-0.3-Vcc+0.3

mW

700

Ta=25°C

sumption
Topg

Under bias

Tstg

Storage

- 70
-40 - 125
0

°c
°c

temperature
Recommended operating conditions (Ta=O - 70°C unless otherwise
specified)
Symbol

Item

Values

vcc

Supply vol tage

Min
4.75

VDH
fXT

Data preservation voltage

2.2

Oscillation frequency of

Units

TYP
5

Max.
5.25

V
V

5.25
32.768

kHz

crystal oscillator
DC electrical characteristics
Ta=O - 70°C, Vcc=5V -+10% unless otherwise specified.
Symbol

I tern

Measurement
conditions

Values
Min.

TYP

Max.

Units

VIH

uH II

input voltage

2.0

Vcc

V

VIL

"L"

inpu t vol tage

-0.3

0.8

V

VOH

"HII

output vol tage

VOL

ItL"

output voltage

I1
IOZ

Input current
Output leakage

Iccl

Vcc power supply

fXT=32.768kHz

current

Vcc=2.2V

Icc2

vcc power supply

fXT=32.786kHz

curren t

Vcc=5.0V (Note 2)

IOH=-400IlA

2.4

IOL=2mA
VI=O - 5.5V

V
0.4
+10

V

-

IlA

+10

Il A

15

Il A

250

Il A

current

Note 1: current towards IC is considered positive (no sign)
Note 2: When connected to CPU (read/write cycle lOllS)

8-7

I

AC electrical characteristics
(Ta=O - 70°C, Vcc=5V -+5% unless otherwise specified)
Measurement
Values

Symbol

conditions
tAC

Address RD/WR delay

Min.

TYP

Max.

170

Units
ns

time
tcc
tCA

RD/WR pulse width

400

Address valid time af-

10000

10

ns
ns

ter Im/WR leading edg.e
tRD

Data delay time after

400

ns

RD trailing edge
tRDH

Data hold time after

0

ns

RD leading edge
tWDL

Data delay time after

40

ns

WR trailing edge
tWD

Data hold time after

20

ns

WR 1 ead ing edge
AC electrical characteristics are as follows when Vcc=5V -+10%.
Symbol

Measurement
conditions

tAC

Address RD/WR delay

Values
Min.

TYP

Max.

170

Units
ns

time
tcc

RD/WR pulse width

tCA

Address valid time af-

450

10000

10

ns
ns

ter RD/WR leading edge
tRD

Data delay time after

400

ns

RD trailing edge
tRDH

Data hold time after

0

ns

RD leading edge
tWDL

Da ta delay time after

40

ns

WR trail ing edge
tWD

Data hold time after

20

WR leading edge
*Refer to the timing chart of page 51

to check the symbols.

8-8

ns

Function of pins
Name of pin

No. of pin

<::S. CS

1,2

Function
External in terface terminals, valid
when CS = H and CS = L. CS is connected to the power-down detector of
the peripheral circuitry and CS to a
CPU address decoder.

ADJ

3

For easy adjustment of the second
counter without connection to a CPU.
I f ADJ is set to high when the second

counter registers 0

-

29, the seconds

are set to 0, and if ADJ is set to
high when the second coun ter reg isters
30 -

59, the seconds are set to 0 and

the minutes are incremented.

This ter-

minal is designed not for edge detection
but for level detection.
Il sec • is

A min imum of 100

required for high-level

adjustments.
AO - A3

4,5,6,7

Address terminals.

Connected to

address bus of CPU.
RD

S

I/O control terminal.

Low when RP5COI

is read by CPU.
GND

9

WR

10

OV
I/O control terminal. Low when RP5COl
is written by CPU.
Bidirectional data bus.

Connected to

DO - D3

11,12,13,14

ALARM

15

OSCIN,

16

For connection to 32.76SkHz crystal

OSCOUT

17

osc illator c ircui t.

Vcc

IS

+5V power supply terminal

I

data bus of CPU.
For output of alarm signal or 16Hz/1Hz
clock signals.

8-9

Open-drain output.

--

Address allocation of MODE 00 (Note 1)
MODE

-

A3

MODE 00
Al

Contents

a

I-sec counter

1

la-sec counter

2

I-min counter

3

1 O-m in counter

4

I-hour counter

D3

la-hour counter(Note 2)

x

Day'-of-the-week counter

x

I-day counter
la-day co un ter

DO

x

6
7

Dl

x

5

8

D2

x

x

x

x

x

9

I-month counter

A

la-month counter

B

I-year counter

C

la-year coun ter

D

MODE Register

Timer EN

Alarm EN

E

Test Register

Test 3

Test 2

Ml
Test 1

MO
Test a

F

RESET Controller

1Hz ON

16Hz ON

Timer

Alarm

RESET

RESET

x

MODE selector

X indicates that the counter may take any value during write operations,
but always be 0 when read out.

(Note 1) MODE 00 is set by writing data (X,X,O,O) to address D.
(Note 2) Bit 1 of the 10-hour counter should be as follows when
the 12-hour system-is selected,
Dl
1 (PM)
Dl = 0 (AM)

8-10

Address allocation of MODE 01 (Note 1)
MODE 01

MODE
A3-Al
0

Contents

1

D3
x

D2
x

Dl
x

DO
x

x

x

x

x

x

2

Alarm I-min register

3

Alarm 10-min register

4

Alarm I-hour register

5

Alarm 10-hour register

x

6

Alarm day-of-the-week

x

7

Alarm I-day register

8

Alarm 10-day register

x
x

register
x

x

x

x

x

x

x

x

Leap-year counter

x

x

x

D

Mode Register

Timer

x
Alarm

EN

EN

E

Test Register

Test 3

Test 2

Test 1

Test 0

F

Reset Controller

1Hz

16Hz

Timer

Alarm

ON

ON

RESET

RESET

9

A

12-hour/24-hour
selector

B

C

x
x
MODE selector
Ml

MO

(Note 1) MODE 01 is set by writing
data (X,X,O,l) to address D.

I

8-11

Address allocation of MODE 10 and 11 (Note 1 )
MODE

MODE 10 (RAM)

MODE 11 (RAM)

AJ-Al
0

Contents

Contents

1
block 10

block 11

5

4 bit

4 bit

6

x

X

7

13

13

RAM

RAM

2

3
4

8
9

A
B

C
Alarm

MODE selector

D

Timer
EN

EN

E

Test

Test

3

2

F

1Hz

16Hz

ON

ON

RESET

(Note 1) MODE 10 is
to address
MODE 11 is
address D.

Timer

Alarm MODE selector

MO
Test

EN

EN

Test

Test

1

0

3

2

1

0

Timer

Alarm

1Hz

16Hz

Timer

Alarm

RESET

ON

ON

RESET

RESET

Ml
Test

set to by writing data (X,X,l,O)
D.
set by writing data (X,X,l,l) to
(MODE 10 and 11 are in RAM areas)

8-12

Ml

MO

Test

Test

*

Mode register (A3,A2,Al,AO)

03

02

Timer
EN

01

DO

Ml

MO

(1,1,0,1)

o

Alarm
EN

0

0

MODE 00: se t ti ng or reading time

0

1

MODE 01: se t ti ng or reading of Alarm
da ta, 12/24 hour system, or
leap year

1

0

1

1

'---------";>

Block 10 in RAM
Wr i ting to or reading Block 11 in RAM
Wr iting to or reading

Set 1 to enable alarm output.
Set 0 to disable alarm output (16Hz/
1Hz clock signals not affected)

'----------------":>Set 1 to start clock.

Set 0 to stop

seconds and subsequent counters.

* The leap-year counter registers a leap year when 01

DO

O.

It simultaneously counts with the year counter.

* The 12-hour/24-hour selector sets the 12-hour system when
DO = 0 and the 24-hour system when 00=1. PM or AM is selected
when 01 in the 10-hour counter is lor 0, respectively (see page 47).

*

Reset controller 16Hz/1Hz clock register.
( A3 , A2 , Al , AO) = (1 , 1 , 1 , 1) = F
DO

1: resets all alarm registers and internal Alarm F/Fs.

01

1: resets the IS-stage dividers before the seconds register.

02

0: switches on the 16Hz clock pulse generated from the

03

0: switches on the 1Hz clock pulse generated from the

ALARM terminal.
ALARM terminal.

*
*

Addresses 0 - 0: able to read and write.
Addresses E - F: only able to wr i te and OB always appears
when read ou t.

8-13

I

Timing chart
WRITE CYCLE (CS = "H")
CS
(Note
AO - A3
Jc-----'-....::=t::::::;r- t WD
DO - D3 ---+-...,---{I
1)--------

WR
(Note 1)
tcc
(Note 1) The RP5COI accepts a WR signal when both CS
= high.

of the

= low

and CS

The timing of CS is not specified, but because
co~struction

of the RP5COl, the WR signal in the

above diagram should be taken as the CS·CS.WR signal.
(For details, see the block diagram of the RP5COI or
Section 4 of these Application Notes.)
READ CYCLE (CS = "H")
CS
~
(Note 2)
\

tCA
f------...l

AO - A3

~

DO - D3

~i::=t.tAC

RD
(Note 2)

~

/

K

-f--.--:t t RDH
.¥.

tRD

j
1

tcc

(Note 2) The RP5COI accepts an

RD

signal when both CS = low and

CS = high, in the same way as for a WR signal.

The

~

signal in the above diagram should therefore be taken as
the CS·CS.RD signal in the same way as the WR signal.
(For details, see the block diagram of the RP5COI or
Section 4 of these Application Notes.)

8-14

Application Notes
(1) Oscillator circuit
(1-1) When constructing the oscillator circuit using a crystal
oscill ator.
The oscillator circuit should be constructed as shown in Fig. 1.
External components needed are a resistor, a condenser, and a
trimmer condenser for fine adjustment of the frequency.

The

oscillation frequency should be adjusted by altering the value of
the trimmer condenser usi.ng the standard 16Hz or 1Hz clock signal
output from the ALARM terminal.
When adjusting with the 16Hz signal:
Address: (A3,A2,Al,AO)
Da ta :

=

(1,1,1,1)

(1 , 0 , 0 , 0 )

When adjusting with the 1Hz signal:
Add ress: (A3, A2, AI, AO) = (1,1,1,1)
Da ta : (0 , 1 , 0 , 0 )
OSCIN

RPSCOI
(Note 3)

Cl = 10PF - 30PFr
C2 = 30PFr(Note 3)
R = 100kn
Crystal oscillator: Nihon
Denpa Kogyo MX38T

Fig. 1

I

(Note 3) Different values of Cl, C2, and R may be used, and the
crystal oscillator is not definitely specified.

The values of

Cl, C2, and R noted above are the best values for the MX38T
oscillator used in the measurements carried out by Ricoh.
A bypass condenser set between pin 17 and GND is sometimes
effective for external noise. Its value should be less than 60
PFr according to the measurements. For details, see Section 1
of these Application Notes.

8-15

(1-2) When using an external clock
When an external clock is used, the arrangement shown in Figs.
2-(a) and 2-(b) below should be adopted.

The OSCIN terminal is

not TTL-compatible but CMOS-compatible.
1) With CMOS inverter

32.768kHz

OSCOUT
CMOS
MC4069UB
RPSCOI

Fig. 2-(a)

2) With TTL inverter

Rp
32.768kHz

I

16

170----./
OSCOUT

TTL
(74LS04)

Rp=lkO - 2kO
RPSCOI

Fig. 2-(b)

8-16

(2) Input/output terminals and chip selection terminals

(2-l)Input/output terminals
Pull-up (4.7-47kn) or pull-down (100-300kn) resistors should be
installed to fix the potentials of the I/O terminals during battery backup.

(See Note 4 on page 16.)

Vcc 18
OSCOUT
30ADJ

OSCIN

AO

(See Note 5 on page 16.)

ALARM
:;0

"0

Al

\Jl

n

D3

0
~

A2

D2

A3

Dl

RD

DO

GND

WR

r-------~-----5V

RD
Rp

100kn.
-300kn.
4.7kn.
-47kn.

RD

Fig. 3

(2-2) Chip select terminals
Two chip select terminals are provided. The CS terminal
should be connected to the power-down detection circuit and the

cs

terminal to the CPU.

CS is active when high and CS is active

when low.

8-17

I

(Note 4)
The values of the pull-up and pull-down resistors need not
necessarily be those given above (4.7- 47kn and 100 - 300kn,
respectively), but they should be chosen so that the RP5COl's
DC characteristics VIH, VIL, VOH and VOL are satisfied.

These

resistors are used to maintain the level of the I/O terminals
(DO-D3) and the input terminals at any time (e.g., during battery backup), and they have the effect of reducing the current
consumption during battery backup.

It is immaterial whether

pull-up or pull-down resistors are selected for any of the I/O
or input terminals.

However, it is recommended that pull-up

resistors be used for CS, RD, and WR, since if pull-down
resistors are used for these terminals, they will become
active when the CPU is on hold (e.g.,at DMA cycle, control lines
of

CS, RO, and WR start to float instantaneously) and this may

lead to problems. The arrangement of resistors shown in Fig.
3 is an example only, and may be altered.
Sec tion 3 of these Appl ica tion

For details, see

Notes.

(Note 5)
If terminal 15 (the ALARM terminal) is to be used during battery backup, it should be pulled up by the same battery power
source as the RP5COl.

If i t is not to be used during battery

backup, it· should be pulled up by the system power source,
which cannot supply voltage during power down.

8-18

(2) Specifications of RP5C15

Outline:
The RP5Cl5 is a real-time clock

CS

1

18 Vcc

CS

2

17 OSC.OUT

that can be connected directly
to the bus of microprocessors
using not only the a-bit CPU such

CKOUT 3

as 8085, Z80, 6809, 6502 but also
the 16-bit CPU such as 8086, Z8000,

AD 4

68000 or others. Time can then be

Al

U)

15 ALARM

.--j

written to or read from the clock

5

alarm function allowing battery

~

14 03
13 02

7

12 01

RD 8

11 DO

9

10 WR

A3

reading from RAM. As well as
calendar and time counters and

u

U)

Po.

A2 6

in the same way as writing to or

GND

backup.

16 OSC.IN

Pin configuration
Featrues:

* Direct connection to CPU and Hi-speed
access

*

4-bit bidirectional bus 00-03

*

4-bit address inputs AO-A3

*

Internal counters for time (hours,
min., sec.) and date (100 years,
leap years, months, days, and daysof-the-week)

*

All clock data expressed in BCD code

*
*

±30 sec. adjustment function
Provision for battery backup

*

Choice of standard clock from 16 kHz,

*

Alarm signal, 16 Hz clock signal or

1.024 kHz, 128 kHz, 16 Hz, 1 Hz, 1/60 Hz
I Hz clock signal output

8-19

•

Block diagram

OSCIN
OSCOUT

CKOUT

f---=:C-==--+---+-I

AOAIA2A3

00010203

8-20

ALARM

ALXRM

Absolute maximum ratings (See Note 1)

Symbol

Item

Measurement

Values

Units

-0.3-+7

V

conditions
vee

Supply voltage

GND = 0

VI

Input voltage

GND = 0

-0.3 - vee+o. 3

V

ve

Output voltage

GND = 0

-0.3 - vee+o. 3

V

PD

Maximum power

TOPG

Ambient temp.

dissipation

Ta = 25°e

during operation
TSTG

mW

600
-20 - 70

°e

-40 - 125

°e

Ambient temp.
during storage

(Note 1) Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device.

This is

a stress rating only and functional operation of the
device at these or any other conditions above those
indicated in the operational sections of this
specification is not impl ied.

Exposure to absolute

maximum rating conditions for extended periods may
affect device reliability.

Recommended operatIng conditions
Ta

-20 o e to 70 0 e unless otherwise specified.

Symbol

Item

Values
Min.

Typ.

Max.

5.0

5.5

V

5.5

V

vee

Supply voltage

4.5

VDH

Data backup voltage

2.0

fxt

Oscillation frequency of
crystal oscillator

Units

32.768

kHz

•

DC characteristics during normal operation
Ta = -20°C to 70°C, vcc = 5V ±10% unless otherwise specified.
Symbol

Item

Measu remen t
conditions

Values
Min. Typ. Max.

units

Remarks

VIH

"H" input
voltage
I"L" input
VIL
voltage
VOH
"H" output
voltage
IlL" output
VOL
voltage
!ILK Input leakage current
IFLK Floating leakage current
1001 Current consumed
during operation

2.0
-0.3
IOH=-400jlA

Vcc+0.3
0.8

2.4

IOL=2mA

V
V
V

0.4

V

VIN=O - VCC

-10

10

jlA

VFV=O - vcc

-10

10

jlA

300

jlA

(Note 2)

Except for
pin 3,15

(Note 2) Vcc = 5V; R/W signal f =lOOkHz; Input terminals, Vcc or
GNO; Output terminals on no-load; Crystal oscillator
(32.768kHz); Measurement temp. (25°C).

8-22

AC electrical characteristics
Ta=-20 o C to 70 o C, Vcc=5V±10% unless otherwise specified.
Symbol

Item

Measurement
conditions

M~n.

tAC

Address valid -RD!WR trailing edge

50

tccR
tccW

RD pulse width
WR _pulse width

20
20

tRD

RD trailing edge

(Note 1)

Values
Units
Typ. Max.
ns
13000

ns

13000

ns

120

ns

Remarks
CS=low and
address valid

--data valid
tcA

RD/WR: leading edge

10

ns

--address hold
tWDS

Write data setup
time

100

ns

tWDH

Write data hold
time

20

ns

tRDH

RD leading edge
--data valid

10

ns

lOa

I'S

tEN-DIS Timer Enable-Timer Disable
tADJ

Adjustment
completion time

tAINH

Alarm data write
inhibit time after
alarm reset

100

I'S

tRCV

RD!WR recovery time

1

I'S

100

I'S

I

8-23

Timing chart
READ cycle (CS

"H")

Valid

CS,AO - A3
l,tAC,

12.4v

0.4V

'1

tRDH

tCCR

Valid

DO - D3

~
WRITE cycle ,(CS = "H")

Valid

CS,AO - A3
tAC

tCCW

tCA

tWDS tWDH

Valid

DO - D3

Others

8-24

Function of pins
Name of pin

No. of pin

Function

CS
CS

1
2

Ex ternal interface terminals.
Valid when both CS = H and CS = L.
CS is connected to the power-down
detector of the peripheral circuitry, and CS to the address decoder of the CPU.

CKOUT

3

Output terminal for standard clock
signal. Can take 8 different states depending on contents of CKOUT
selection register. N-ch open
drain output.

AO -A3

4,5,6,7

Address input. Connected to
address bus of CPU.

RD

8

I/O control input. Set to low when
da ta of RP5C15 is read. Low active
input.

GND

9

OV

~

DO - D3

10

11,12,13,14

I/O control input. Set to low when
da ta of RP5C15 is written. Low
active input.
Bidirectional bus. Connected
directly to CPU data bus.

~

15

Output terminal for alarm signal
and 1Hz/16Hz clock signals. N-ch
open-drain output.

OSC IN

16

Connected to 32.768kHz crystal
oscillator circuit.

OSC OUT

17

Connected to 32.768kHz crystal
oscillator circuit.

VCC

18

+5V power supply

8-25

I

* I I X ' I means "Don't care" ~hen written,
and always 1'0" when read out.

* Address

O~D:

able to read to and write from,
except for ADJUST register
which can only be written to.
Address E-'F: "write" only (always "0" when
read out)

Address allocation

Bank 0
A3-AO
0

Con ten ts

Bank I

D3

DI

D2

DO

I-sec.

CKOUT sel,ec-

counter

tion register

coun ter
2
3

5

Alarm I-min.

counter

register

IO-min.

Alarm IO-min.
register

X

counter

register

IO-hour

Alarm IO-hour
register

X

X

8

9

I-day

register

IO-day

Alarm IO-day
register

X

X

I-month
counter

A
B
C

X

X

selector

X

I-year

Leap-year

counter

counter

Mode
register

E

Test

Timer Alarm
EN

Reset
controller

EN

Test

Test

2

3

register
F

CKI

CKO

X

X

Adjust

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

IO-year
counter

D

CK2

TI/24 hour

IO-month
counter

X

Alarm I-day

counter
counter

DO

the-week

X

register
7

DI

Alarm day-of-

Day-of-theweek counter

D2

Alarm I-hour

I-hour

coun ter
6

gister

X

I-min.

counter
4

D3

Adjust re-

IO-sec.

I

Con ten ts

rHz
ON

I6Hz

ON

X
Test

I

Bank

Mode

1/0

register

Test

Test

0

Timer Alarm

X
EN

EN

Test

Test

3

2

register

Timer Alarm

Reset

TIfZ

RESET RESET

controller

ON

8-26

X

X
Bank
1/0

Test

I

IbHz Timer

em

RESET

Test

0
Alarm
RESET

CKOUT selection register
D3

D2

X
X
X
X
X
X
X
X

Dl

DO

° ° °
° ° 1
° 1 °
° 1 1
1
° °
1
° 1
1
1
°
1

1

Remarks

CKOUT
"2"

High-impedance

16.384kHz

Duty 50%

1. 024kHz

Duty 50%

1

128Hz

Duty 50%

16Hz

Duty 50%

1Hz
1160Hz
ilL"

.fSeconds counter increment • Duty 50%
~Minutes

counter increment. Duty 50%

Low Level

Adjustment function
BANK

1~

°

Second counter backs to

ADDRESS (A3,A2,Al,AO)=(0,0,0,1)

when it's adjusted

°-

29

sec.
DATA (D3,D2,Dl,DO)=(X,X,X,1)

I f it's adjusted on 30 -

59 sec. , the second
counter

goes up to

sec. and the minute

°

counter shows the next
minute.

Oscillator circuit
Not required because an output ballast registor (Approx. lOOkn )
is used.
Cl
CO
RP5C15

8-27

15pF Standard
39pF Standard

I

(l,1,0,1) = D

*Bank register (A3,A2,Al,AO)
D3

D2

Dl

DO

BANKO:setting or rate time

Timer

Alarm

X

0

EN

EN

x

1

BANKl:setting or rate of Alarm
data, 12/24 hour system, leap

~I

year, choice of CLKOUT, and
adjustment

-----------------------Set 1 to enable alarm output
Set 0 to disable alarm output
(16Hz/1Hz clock signals not
affected)

L--------------------------------Set 1 to start clock. Set 0 to
stop seconds and subsequent
counters.
*The leap-year counter registers a leap year when Dl

DO

O.

It simultaneously counts with the year counter.
*The 12-hour/24-hour selector sets the 12-hour system when DO

=0

and the 24-hour system when DO = 1. PM or AM is selected when
Dl in the 10-hour counter is 1 or 0, respectively.
*Reset controller 16Hz/1Hz clock register.
(A3, A2, AI, AO) = (1, 1, 1, 1) = F
DO
Dl

l:resets all alarm register and internal Alarm F/Fs.
l:dividers before seconds counter reset.

D2

O:switches on the 16Hz clock pulse generated from

D3

O:switches on the 1Hz clock pulse generated from

the ALARM terminal.
the ALARM terminal.
*Addresses O-D:able to read and write.
*Addresses E - F:only able 'to write and OH always appears when
read out.
*TEST register (A3,A2,Al,AO) = (1,1,1,0) = E:use for inspections
at Ricoh Co., Ltd. Normal watch function is achieved by setting
of the data (D3,D2,Dl,DO)

=

(0,0,0,0).

For details, refer to the Application Manual.

R-?R

(3) Construction of oscillator circuit
The following external parts are required for constructing the
oscillator circuit:
(1) One 32.768 kHz crystal oscillator

(2) Two condensers (including one trimmer condenser)
(3) One resistor of approx. 100 kn, for RP5COI only
The oscillator is easily affected by external noise, leading to
error in the clock.

Care should therefore be exercised when

constructing it on the PCB, and the following general points
should be observed when constructing the oscillator circuit on the
PCB:
(a) The crystal oscillator and the load capacitor CL should be
mounted as close as possible to the OSC terminals.
(b) Signal lines and power supply lines should be placed as far
as possible from the oscillator circuit, since they can
interfere with its proper operation.
(c) The resistance of the PCB between OSCIN and OSCOUT and the
resistance between the pins should be made as high as
possible.

RP5C15

-+------------~----

Fig. 3-A

Signal lines should not be
placed here.

No particular specifications are set for the crystal oscillator.
The accuracy of the clock generally depends on the following
parameters:
(1) The accuracy of the crystal oscillator
(2 )

The capacity of the condensers

(3 )

The ambient temperature

(4 )

The supply voltage

(5 ) The gain of the built-in ampl i f ier in the RP5COI and RP5C15

8-29

I

Data on the oscillator circuit obtained by Ricoh, Ltd. are given
for reference in Fig. 4-1 and subsequent diagrams on page 30. However, because of the effect of external stray capacity and other
factors,

the same results will not necessarily be obtained even

if exactly the same measurement circuit is used, and the results
therefore cannot be guaranteed. The oscillation accuracy, backup
current and oscillation stability should therefore be checked
under dif.ferent supply voltages and ambient temperature conditions
with the device mounted on the particular PCB with which it is to
be used.
The accuracy of the oscillation frequency should be measured by
causing a standard clock signal to be output from terminal 3
(CKOUT) or terminal 15 (ALARM)

in the case of the RP5C15, or, in

the case of the RP5COI, from terminal 15 only.

The RP5C15 is

programmed to output a 16 kHz clock signal from terminal 3,
making it particularly easy to check the accuracy of the oscillation frequency by connecting the CKOUT terminal to a frequency
counter.
The measuring probes of a frequency counter or oscilloscope
should not be connected directly to the OSCIN or OSCOUT termiral,
/

since the capacity of the probes will alter the oscillation Conditions and make correct measurement impossible.

When either

the RP5COI or RP5Cl5 is oscillated externally, a 32.768 kHz
clock signal should be input via the OSCIN terminal.

However,

since the input level of this terminal is not the TTL level for
either the RP5COl or RP5CI5, a TTL output cannot be connected
directly to it (See Fig. 3-8).

T

4. 7kn

32.768

kHZ~
74LS04

32.768 kHZ----{>o-OSCIN of the
RP5COI and RP5Cl5
MC4069UB

Connection of TTL and CMOS
outputs to OSCIN terminal
of the RP5COI and RP5Cl5
Fig. 3-B

8-30

(4) Power dissipation

Except for OSCIN and CS, all the inputs of the RP5COI and RP5C15
are designed to be TTL-compatible, but the operating current differs depending on whether the input voltage VIN gives VIH = 2.0V
(the minimum) or Vcc.

To make the power dissipation as low as

possible, the input voltage should be set as close as possible to
the supply voltageVcc or GND.

Also, most of the power dissipat-

ed during backup is consumed by the oscillator circuit.

The

power dissipation depends closely on the backup voltage, and the
results of measurement carried out by Ricoh on this are shown in
Tables 4-1 and 4-2 below.

supply voltage

2.2V

2.5V

3.0V

3.7V

5.0V

standby current

7.9

13.2

26.5

56.7

153.8

Unit
/lA

No. of samples: 10 (average) at 25°C
Input terminal: vcc or GND.

Output terminals on no-load.

Table 4-1 PO\'/er dissipation of RP5COI

Supply voltage

2.0V

2.5V

3.0V

3.5V

5.0V

Unit

Standby current

3.0

4.9

8.8

15.3

57.2

/lA

No. of samples: 10 (average) at 25°C
Input terminals: vcc or GND.

Output terminals on no-load.

Table 4-2 Power dissipation of RP5C15

8-31

I

Characteristics of oscillator circuit for RPSCOI

Measurement conditions
crystal oscillator used: Kinsekisha Lab. Type-P3

RPSCOI
OSCIN

OSCOUT

lOOK

1Hz

10K

o
33pF

I

cs

H

cs

L
F (1,1.,1,1)
B (1,0,1,1)

ADDRESS
DATA

Measuring 1Hz from ALARM terminal
(For temperature characteristics,
RPSCOI alone in a stable-temperature
chamber and other components in ambient
temperature during measurement)
Fig.

4-1

8-32

RP5COl
Dependence of oscillation frequency on power supply voltage at
room temperature (25°C) (0 PPM is set at 5 volts.)

-~

PPM

10

X Sample No.1

o Sample No.2

I

I

2.0

I

3.0

I

4.0

Vcc

(V)

I
---5.0

Fig. 4-2

8-33

RP5COI
Dependance of oscillation frequency on temperature (Vee

5V)

(0 PPM is set at 25°C.)

(PPM)

Vee

5V

- f - 5.0

-20 -10

I

10

20

~;O

~O

~

60

70

80

90

o~

o~
o~

-f-

-5. 0

Fig. 4-3

8-34

---0-

Ta (OC)

RP5COI
Dependence of oscillation frequency on temperature (Vcc

3V)

(0 PPM is set at 25°C.)

(PPM)

Vcc

3V

-;-5.0

40

-20 -10

I

10

20

;0'---0

I

50 60

~o

~o

70

80

90 Ta

~o

---- 0____.0_
-1--5.0

Fig. 4-4

8-35

(OC)

•

RP5COl
Dependence of oscillation frequency on temperature (Vcc
(0 PPM is set at 25°C.)

(PPM)

Vcc

-f-5.0

40

-20 -10

~

10

I

20

-f--5.0

Fig.

4-5

8-36

2.2V

2.2V)

Characteristics of oscillator circuit for RP5C15

(1) Dependence of standby supply current of RP5C15 (ICC2) on
ambient temperature:
Measurement conditions

N

U
U

=

H

Cd

OSCOUT'r-+-----i I-----{>
t--t----i GND

~- - - - - - - - - - - - '

Constant-temp. chamber

CS

H

CS

L

AO-A3

H

RD,WR
00-03
CKOUT
Cd
Cg

H

GND
OPEN
39PF
3-11PF
trimmer
condenser

50

...
~

<
3

40

~

~

Vcc = 5.0V

N

U
U

H

c

'--

1-1
1-1

"r-

Q)

::l
U

>.

I

I

6

I

.-t

0.
0.

•

I

30

~

4

::l
Ul

2

x-

x-

-x- -x- -x- -x- -x- -x- _x __ x- -x- _x-Vcc = 2.0V
I

I

I

I

I

10

20

30

40

I

I

60

70

I
-30 -20 -10

0

50

Ambient temperature Ta (OC)

8-37

80

(2) Dependence of oscillation frequency of RPSC1S on supply voltage
at 25°C
Measurement conditions
Cg
OSCIN ~~~__~>
Vcc
=
OSCOUT

f------t>
Cd

GND

CKOUT

CS

H

CS

GND

AD-A3

Vcc

RD,WR

vcc

00-03

GND

Cd

39PF

Cg

3-11PF
trimmer
condenser

Output 16 kHz via
CKOUT and measure with
frequency counter.

4 -

o e;

-

.j..lo.

0 ---\

c~

.~

0.

IO~

;::>.
.~

()

2

-2 -

() c
en Q)
o ;::l0'
-4
c.Q)

.~ .t:
Q)
01
c

10

..c::

-6

-8

u

-10

\

I IIJ~
I

4.....-·
5
6
• Supply vol tage
vcc (V)

~ _

1/·
/.

-

-

3

2

•

-(
•

I

8-38

(3) Dependence of oscillation frequency of RPSC1S on ambient

---,

temperature

,

r---------~

.---+---l VC C

I

Cg
OS CI NI------l,{::------j,>

,

OSCOUT

~---l--i

GN D

I

CS

H

CS

L

AD-A3

H

RD,WI<

H

DO-D3

L

C KO UT f-----<~---+__1

L_______ ~
Constant-temperature chamber

Cd

39PF

Cg

3-11PF
trimmer
condenser

Output 16 kHz via CKOUT
terminal and measure with
Ambient temperature Ta (OC)
-30 -20 -10

o

/

10

20

30

40

50

frequency counter_

60

70

C

o

-20-~

co
rl
30 rl ~ -+----+----1---M

S

uo.
- 4 0 ~ !:' -t-----I----t-----IC>,

-+--+- 5 0 -M
I

I

----l /
>(

g -t-----I----t----+_-

(J)(J)
01 :l

1---+---+- 6 0 ~
.c

g
1-1

- - - - vcc =5. OV

--x-~::E
-90~

Vcc=2. OV

Note: The variation in oscillation frequency can be reduced
slightly by the use of a temperature-stabilized condenser for Cd.

However, the frequency variation

obtained here results almost entirely from the characteristics of the crystal oscillator used.

8-39

I

100
90
80
70
60
50
40

c...
p..
'0
U

--i\-t-i-t
I

I

I

I I

\~_i_l-i\-~
l 'I
I
1--

__ L-_'.1_..L_.1 _ _

'~I
I

,

I

,

I

I

I

-·-r- -T-r-r-,--

-+ t\{~-t-~--~
I

I

I

I

II I
!I , 'I
I

I

I

--~-~-T

II

I

I

'"

I

~-~---

-T
I

30 --~-1-1-t-~----r~--

:::::\:~'

I

I

,

r

I

I

I

I

I

I

I

"

20 --~-f-f-T-~-----k--~--

__

r
~_l_l_l_~

tIl

: ::-::
:

1,0
9
8

I

I

-- :

I

"

:

:
,:

_____ ~ __~ ______ ~_

:::

:

:,

,

__ :__ +_+_}_~ _____ }___ ~ ___ .___ :_ ~_ ~ ___ ~ __ :__ +_ }_~
__ ,_ _ l.:" .1._.1. _1. _____ L ___
IIIII

t

I

I

..1 ______ L

I

-10ppm
32.768kHz
,+10ppm
I

~~Oppm

___ ~ __ L. __ ' __ 1._ L_L_L __

I

I

~I

1'111

--:- -t- i - T-~ ----- ~ --. -~- -- -- -i ---~ - --, ~ T- T-t-:----~-T-~-~ -f -- --- t-- - --:---~- -i ---~ ---~- -:- -N-~+50ppm
--:- -+- +- ~ -\- ----- ~-- --l--- - - -:- -- - ~ - - - \-- -:--+ -}- ~ -,--I

I

I

I

8 9 10

I

I

I

20

30

40

Cg

[PFj

Fig. 4-9

8-40

I

I

t

I

I

I

50 60708090100

(5) Connection to CPU

CS
CS -t----<:i.-.-J

I

Input

_:~

terminal~

Input
terminal-+--~iJ

I

I
I

L

_____ _

RP5C15

RP5COI
Fig.

5-1

Fig.

5-2

Because of the structure of the input terminals of the RP5COI
(WR,RD, AO-A3, DO-D3,ADJUST, and CS) as shown in Fig. 5-1, a
through current flows at the input buffer transistor when an
input is allowed to float, making it necessary to connect a pullup or pull-down resistor externally.
the structure shown in Fig.

The RP5C15, however, has

5-2, and there is no danger of

through current flow even if terminals other than CS and OSCIN
are allowed to float.

The pull-up or pull-down resistors needed

with the RP5COI are therefore unnecessary with the RP5C15.

The

resistors used with the RP5COI are for the purpose of keeping the
input terminal levels equal to vcc or GND, and it is immaterial
whether pull-up or pull-down resistors are used.
all inputs.

This applies to

However, it is recommended that pull-up resistors be

used with WR, RD, and CS so that these terminals become nonactive, for example, when the CPU is in the "hold" state and the
control signals of the CPU start to float instantaneously.
instantaneous WR

=

CS

=

low state may affect memory or cause

peripherals to write invalid data.

8-41

This

I

x8

00
01
02
03

11
12
13
14

AO
Al
A2
A3

4
5
6
7

'"0
or>
'"

00
01
02
03

17 lOOk
OSCIN
AO
Al
A2
16
A3 OSCOUT

WR

'"

RO

11 00

AO
Al
A2
A3

4AO
5 Al
6 A2
7 A3

12 01
13 02
14 03
OSCOUT

'"
0
or>
'"

'"U
'"

0

a.
u

00
01
02
03

17

'"

'"U

'"a.
u

'"
A13
A14
AIS

CS

10AOJ 3

rR\)

ALARM

Connection example for RP5COI

Connection example for RPSC15

Fig. 5-3
A further specification to which attention must be paid when
connecting the RP5COI and RP5CI5 to a CPU is the AC characteristics tACo

An example is shown in Fig. 5-4,

where connection

to a 6809 CPU in the way shown will result in tAC failing to
reach the required value.
shown in Fig.

5-5.

The correct method of connection is

When the RP5COl is used, care must also be

taken that tWDL is satisfied.

If a CPU is to be used which does

not give the correct value of tWDL (e.g., 8-bit I-chip microcomputers, such as

MC680l, HD630l, pPD78C05, etc.) care should be

taken.

0'1
0

co
\£)

R/W

rrc

0'1

o

RD

co

R/W
E t-1-_._-1

,

\£)

WR

:::>
l/).-<
.-<0

:::>

0..

u

UU
l/)l/)

0..

U

0..0..
0::0::

Inappropr ia te
Fig. 5-4

Appropr ia te
Fig. 5-5

8-42

It should also be noted that the definition of the AC characteristic tAC (see pages 12 and 21Jdiffers for the RP5COl and
RP5C15 as follows:
(1) In the case of the RP5C01, tAC is the time taken from address
valid to logical AND (CS'CS'RD) or (CS'CS'WR)

(See page 12).

(2) In the case of the RP5C15, tAC is the time taken from logical
AND (CS'CS'address valid)
(CS'CS'WR)

to logical AND (CS'CS'RD) or

(See page 21).

The following explanation shows how (1) and (2) above apply to
connection to a 6809 or Z80:

,---

0\

0

Al3
A14
A15
BS
BA
E

00
~

:::> R/'"

p..

u

1
2
3
4
5

Al3
A14
A15
IORQ

00
M
.-I

Ul

....:I

o-----! CS

LIl
.-I

u

LIl

6 Gl

p..

p::

'---

~~ WR
-rj>----1Q RD

0
00

~

1
2

d

r00
M

3

.-I

4

....:I

Ul

0

u

:::>

p..

u

IX<

u

p..

p::

G1
~

~

WR

8 WR

RD

10 RD

p..

LIl

LIl
.-I

LIl

lSI

.-I

~ CS

.-I

0

u

LIl

p..

p::

IpOWER-DOW~~
CS
DETECTOR

POWER-DOWN~ CS
DETECTOR
Fig. 5-6 Connection to 6809

Fig. 5-7 Connection to Z80

Fig. 5-6 shows the RP5COl connected to a 6809 CPU.

The following

explanation applies when CS is high, i.e., when the supply
voltage is normal. If a 6809 CPU is connected as shown in Fig.
5-6, the timing chart will be as shown in Fig. 5-8 below, if
decoder and gate propagation delays between the CPU, the RP5COl
and the RP5C15 are ignored.

8-43

I

ADDR

-+-----<~

)>---

Val id

BA, BS)~I----+-~----------.

R/~ .~~__~_____~:_____________--J)~------~tAC

~-----b----~~I

for RP5Cl5 (~ 0)

____________~

I
:-----~·I

Fig.

tAC for RP5COl

5-8 (Timing chart for arrangement shown in Fig. 5-6 )

The following points arising from the timing shown in Fig.

5-8

should be noted about the connection to the 6809 CPU shown in
Fig. 5-6:
(a) There is no problem when using the RP5COl.
(b) With the RP5Cl5,

tAC

~

0, and the arrangement shown in Fig.

5-6 cannot be used.
The same considerations apply when a Z80 is connected as shown
in Fig. 5-7. The timing chart for this arrangement is shown in
Fig. 5-9, which shows that CS does not become active until IORQ
becomes active.

Thus in the case of the RP5Cl5, tAC

~

0 and

the AC characteristics are not satisfied.
Thus the connection to a Z80 shown in Fig. 5-7 can be used with
the RP5COl, but not with the RP5Cl5.

8-44

~------------------~>~----

ADDR

\'--____________--.J;---'tAC for RP5COl
/
'.
~'~-------------.J
=t=i-tAC for RP5C15
0)

(~

--------~\

/~------

'-._ _ _ _ _ _ _ _ _ _---.J

Fig.

A13
A14
A15
BS
BA

5-9 (Timing chart for arrangement shown in Fig. 5-7)

21
22
23
5
6

1
2

r--

Al3 3
A144
A15 5

00
M

3

.-f

r.Il

4
5

....:l

0
00

~

'"p..

8

r1

ly=)

I

.-f

r.Il

....:l

1 CS

I
N

Ll')

::J

.-f

p..

.-f

U

U

Ll')

Ll')

U

Ll')

::J

32
u R/W 3A
E

00
M

0
00

ti Gl o-L CS

C\

1
2

POWER-DOWN
DETECTOR

WR

p..
il:

8 VJR
10 RD

10 RD

rL

2

p..
il:

2

CS

Fig. 5-10
Connection of RP5C15 to 6809

CS

Fig. 5-11
Connection of RP5C1S to Z80

The necessary arrangements for achieving the required value of
tAC when the RP5C15 is connected to a 6809 or Z80 CPU are shown
in Fig. 5-10 and Fig. 5-11.

If these arrangements are used,

the timing will be as shown in Fig. 5-12 and tAC will reach the
required value even when the RP5C15 is used.
ADDRESS

---
~

CJ
.j.J
.....

.a
I

~

INT
PIO
PIl
PI2
PCO
PCl
PC2
PC3
PEO
PEl
PE2
PE3

ALARM
CS
RD
WR
DO
Dl 0
D2 CJ
U'l
p:,
D3 p::
AO
Al
A2
A3
~

M
~

Ei
0

()

::t.

..
::>
~

CJ
.j.J
.....

.a
I

~

(4-bit CPU: NEC

r

ALARM
CS
RD
WR
DO
Dl U'l
D2
CJ
D3 U'l
~
AO p::
Al
A2
A3
~

l

POWER-DOWNj>-DETECTOR

CS
Fig. 5-13 Connection of RP5COI
to 4-bit CPU

INT
PIO
PIl
PI2
PCO
PCl
PC2
PC3
PEO
PEl
PE2
PE3

CS

Fig. 5-14 Connection of RP5C15
to 4-bit CPU

~com-43)

(4-bit CPU: NEC

8-46

~com-43)

An example of data readout is given below for connection to a
4-bit CPU
Data readout flowchart for RP5COl (when arranged as shown in
Fig. 5-13)
[Expl ana t ion]
Set data to ports EO - E3

(Set addresses)

Set 4H to ports IO - 12

(CS

low, WR

high)

Input data to ports CO-C3
Set 7H to ports IO - I2

(CS

high)

Data readout flowchart for RP5C15 (when arranged as shown in
Fig. 5-14)

Set data to ports EO - E3

(Set addresses)
low, RD

Set 6H to ports IO - I2
Set 4H to ports IO - I2

(CS

high)

low, WR

(NOTE 1)

high)

I

Input data to ports CO - C3
Set 7H to ports 10 - I2

(CS

high)

(NOTE 1) When reading out data with the RP5C15, do not set CS and
RD to low simultaneously, and when writing data, do not set CS
and WR to low simultaneously, so as to obtain the minimum value
of tACo

8-47

When using a 4-bit CPU, care should be taken with the AC characteristics tcc (max.)

(See pages 12 and 21).

of tcc (max.) for the RP5COl is 10

~sec.,

The specified value

and the specified value

of tccR (max.) and tccW (max.) for the RP5C15 is 13
meaning of tcc (max.)

~sec.

The

is that if the data is not read out within

the specified time, the CPU may read out incorrect data.

This

does not mean that the data of the RP5COl or RP5C15 is destroyed.
When reading out data with a 4-bit CPU, it is thus necessary for
the CPU to take in the data

from the RP5COl or RP5C15 within tcc

(max.) after CS and RD have become active.

For this reason, the

interrupt service routine,

which may make tcc longer than tcc

(max.), should be disabled

during read/write operations (Note

3-1) •

If the backup power supply is arranged as in Fig.

5-15, the

supply voltage of the RP5COl and RP5C15 will be about 0.6V lower
than the system supply voltage at 25°C, and the maximum value of
the input voltage VIN will be Vcc + 0.6V.

Thus the DC electrical

characteristic VIN (max.)

=

arrangement shown in Fig.

5-15 does not meet the DC specifica-

tions.

vcc + 0.3V will not be satisfied. The

(This is identical to CMOS static RAM.)
Approx. 0.6V voltage drop occurs

System power

SUPPIY~VCC

Fig.

of SCOI, SCIS

5-15

(Note 3-1) The interrupt service makestcc exceed tcc (max.)
when the interrupt service routine begins at the status where
data is not read out,although RD and CS are active.

8-48

Ideal backup power supply

System power supply
Vcc

1
Power down
detector
circuit

CS

I

8-49

(6)

cs

and CS terminals

Some of the functions of CS and CS are different between the RP5COl
and RP5C15.

(6-1) In the case of the RP5C1S:
When CS = low or CS = high
(1) External WR or RD signals are not accepted.
(2) No through current flows at the input buffer transistor even
if the input terminals are allowed to float.
Fig. 6-1 shows the above functions of CS and CS.

I

As this figure

shows, terminal CS cannot be allowed to float.

CS
CS

-.-------cL~

WR -+------+--<::1

Internal WR signal
of SC15

RD -+----1--<1

Internal RD signal
of SC1S

Input terminal-+----~
(e.g., AO-A3,
DO-D3)

Internal input signal
of SC1S

Fig. 6-1

8-50

The following points should be noted about CS and CS:
(I) CS can be allowed to float when CS

=

low.

(II) CS cannot be allowed to float under any circumstances.
If it is allowed to do so, a current will flow at the input
buffer and cause rapid battery power consumption at battery start-up.

Thus the voltage input to CS must be set to

Vce or GND at all times, regardless of whether or not the
system is actually operating.

The voltage level input to CS

should therefore be set by connecting the CPU address
decoder and the power-failure detection circuit to CS.
CS is sometimes used in the pull-up mode on other systems.
However, when the system supply voltage is shut off as a result
of main power failure or some other cause, the CPU can go into
abnormal operation and produce the state CS

= WR = low

in the

RP5COI and RP5C15, with possible destruction of the RPSCOI and
RP5C15's data because CS is always high.

Terminal CS should

therefore be set to low immediately after the system supply
voltage is shut off.
(6-2) In the case of the RP5COl:
The RP5COI differs from the RP5C15 in the following two respects:
(1) The input terminals of the RP5COI should not be allowed to
float, but should be pulled up or down to Vcc or GND at all
times, regardless of the state of CS
(2) When CS

=

~

CS.

low, the ADJUST signal is~not accepted.

Fig. 6-2 shows above (1) and (2).

ADJ

I

Ir

cs

CS

RD
WR

Fig. 6-2

8-51

(7) Reading clock data
A

possibl~

source of error in reading out the clock data occurs

when the clock counts up during readout, causing the CPU to read
out incorrect data.
Example 7-1 shows the situation that occurs when the CPU starts
to read out the clock data at 59 min., 59 sec. past the hour.

If

the clock counts up while the CPU is still reading out the data,
the CPU will read the hour incorrectly.

Time at which CPU starts to read out data:
Time at which CPU finishes reading out data:
Data read by CPU:

@®:

®®

0 0

0 0

11: 5 9

5 9

1 0

CDCD:

:

(Note: circled figures are values read by CPU)
Example 7-1

There are following three methods -- (7-1) through (7-3) -- to
avoid this problem.
(7-1) Stop the clock. (Set bit 3 of address D to 0.)
(7-2) Read the clock data twice.
(7-3) Read the data in synchronization with a 1Hz signal which is
output from an ALARM terminal.
A detailed explanation of the above three methods follows.

See

Section 16 for the flowchart.
(7-1)

Stopping the clock

To stop the clock, write 0 to the Timer Enable F/F (bit 3 of
address D).

(Fig. 7-1 )

If 0 is written to the Timer Enable F/F, the internal Clock Hold
circuit of the RP5COl or RP5C15 is brought into operation (see
block diagram), and a 1Hz pulse generated while the clock is
stopped is stored for a maximum of 1 sec. in the Clock Hold circuit.

8-52

The following points should be noted if the clock is stopped:
(7-1-1) The I-sec. signal stored in the internal Clock Hold circuit will be revised within 100 Msec. after 1 is written
to the Timer Enable F/F.

To prevent the data from being

read incorrectly, the clock data cannot be read out
during this 100 Msec. period.
(7-1-2) If the power supply is shut off for more than 1 sec.
while the Timer Enable F/F is set to 0, the clock will be
delayed.

If power shutoff is detected, the Timer Enable

F/F should therefore immediately be set to 1, restarting
the clock, and terminal CS should be set to low.

M~DE

D

regIster

~I
EN

Fig. 7-1

ALARM
EN

I

Ml

MO

(Mode register is allocated
at address D)

(7-2) Using software to read the clock data twice
This method prevents the necessity to stop the clock.

The clock

data is read once and then a second time, and the two readings
are compared.

If the readings are different, this indicates that

the clock data changed during the readout procedure, and it is
therefore necessary to read the data again.
(7-3) Reading out the clock data in synchronization with a 1Hz
signal.
The RPSCIS can be made to output a 1Hz signal from the CKOUT terminal by setting the internal CKOUT Selection Register (Address
of Bank 0) or the ALARM terminal.
and the internal

The timing of the 1Hz signal

counter is as follows:

The clock data is altered after (a)

the leading edge of the 1Hz

signal in the case of the CKOUT terminal, or (b) about 96psec.

8-53

a

I

after the trailing edge of the 1Hz signal in the case of the
ALARM terminal.

Because of this, 1Hz signals output from the

CKOUT and ALARM terminals will be approximately 180 0 out of
phase.

But an interrupt to CPU should be requested at the

leading edge.

With the RPSC01, a 1Hz signal can be output from

the ALARM terminal only, so the clock data should be read out at
the leading edge of this signal if this method is adopted.

1Hz

signals output from the ALARM terminals of the RPSCOl or RPSC1S
will be exactly in phase.

8-54

(8) Writing clock data
The correct clock data will not be written if the data changes
during the writing operation.

As with reading the clock data,

there are three possible methods of ensuring that the data does
not change during the writing operation.

These are as follows:

(8-1) Stop the clock by writing 0 to the internal Timer Enable
F/F
(8-2) Reset the internal IS-stage divider (by setting the internal Timer Reset F/F of address F of bit 1) and write the
clock data within 1 sec.
(8-3) Write in synchronization with a 1Hz signal
The procedure for (8-1) and (8-3)
clock data.

is the same as for reading the

However, it is recommended that, if method (8-1) is

adopted, the IS-stage dividers be reset before writing data in
the same way as for method (8-2).

This is because, if a I-sec.

signal is generated internally while data is being written, a 1Hz
pulse is stored in the internal Clock Hold circuit, and the data
is revised upwards by 1 sec.

in the 100

~sec.

immediately after

the write operation is finished and the clock is restarted by
setting the
the clock

Timer Enable F/F. The first second after restarting
thus appears to pass extremely quickly.

In method (8-2), resetting the IS-stage divider stops the clock
data from being altered for 1 sec.

with both the RPSCOI and

RPSClS, writing 1 to the Timer Reset F/F generates an internal
one-shot reset signal, and there is thus no need to write 0 to
the Timer Reset F/F after the reset operation.
reset pulse width is about 100

~sec

The internal

with the RPSCIS and is the

duration of WR = low with the RPSCOI.
When writing the clock data, the following two items should
always be set at the same time:
(1) Set the hour counter to either the 12 or the 24 hour system.
(2) Set the Leap-Year counter (details of this are given later).
Care should also be taken that the software does not write
impossible clock data (e.g., 10 or more to the second counter),
since there is nothing in the hardware of either the RPSCOI or
the RPSCIS to prevent this.

8--55

I

(9) Use of alarm

(9-1) Structure of ALARM terminal
For the internal structure of the ALARM terminal, see Fig. 9-1.

*
Alarm comparator
****
Alarm EN

OUT

.---:.-+-----;A!\'LLA!\'RroMW te rm ina 1
of SCOl/SClS

16Hz s ignal._rr----..

**
16HZON
1Hz signal

* ** _rr----..
1 H ZONI-C1.-----"
Fig. 9-1

(*) A detailed explanation of the Alarm Comparator is
given in (9-2)
(**) 16HZON is in bit 2 of the Reset Controller
(address F)
(***) IHZON is in bit 3 of the Reset Controller
(address F)
(****) Alarm EN is in bit 2 of the Mode Register
(address D)

As shown in Fig. 9-1, the 16Hz signal, the 1Hz signal and the
alarm signal can all be output independently.
For example, setting Alarm EN = 1, 16HZON = 0 and 1HZON
o will
cause the alarm signal, the 1Hz signal and the 16Hz signal to be
output simultaneously from the Alarm terminal.

8-56

(9-2) Alarm Comparator OUT
The Alarm Comparator OUT signal is an internally-generated
signal, and it is output when the contents of the Alarm Register
and the Clock Counter match completely.

(Fig. 9-2)

I-min. counter and I-min.
alarm register match
10-min. counter and 10-min.
alarm register match
l~hour

counter and I-hour

alarm register match
10-hour counter and 10-hour

Alarm Comparator

alarm register match

OUT

Day-of-the-week counter and dayof-the-week alarm register match
I-day counter and I-day
alarm register match
10-day counter and 10-day
alarm register match
Fig. 9-2

However, if the structure shown in Fig.

9-2 is adopted, the

required software is extremely cumbersome if, for example, it is
desired to output the alarm signal from the Alarm terminal at
10:00 daily.

The reason for this is that, in order to match

all the items, the contents of the day-of-the-week, I-day and
10-day Alarm Registers must be rewritten by CPU every day.

To

reduce the amount of software required, the Alarm Reset function
can be used, by writing 1 to bit 0 of address F.

8-57

I

When "I" is written in the alarm reset, all four contents of the
alarm register are set at "0". This means the resister is open
and ready for resetting, erasing the previous alarm setting.
Thus, for example if you write "5" into the minute counter only,
the alarm output sounds for one minute at five minutes past every
hour.

Minute
counter

(IO-min.)
IM8BL IL8BI

(I-min.)
IM8BI L IL8BI

rL-Ll--_LJJ_l-,

i

~ D-

(I-min. matching
signal)

,-------1,.,--....

.
Lr-I-1---[JJ-J
~:~~::erIM8BI IL8BI IM8BI CIL8BI

(IO-min. matching
signal)

(IO-min.)
(I-mIn.)
BANK 1 WR

'-~-----Alarm

FIF

I-min. register address_
IO-min. register addr'ess

GA1~a~r;m~R~ES~E~T>--------J>---*
Fig. 9-3

Alarm RE8ET signal is
put in all the reset
input of Alarm F/Fs.

Fig. 9-3 is a block diagram of the matching circuit for the 1min. register and I-min. counter of the RPSCOI.

It is almost the

same as for the RPSCIS except for tne way in which Alarm F/Fs are
set.

Each Alarm Register contains an Alarm F/F, and the Alarm

Reset signal resets all the Alarm FIFs as shown in Fig. 9-3.

The

following precautions should be taken when resetting the Alarm F/Fs:
(1.)

When the Alarm F /Fs are reset, the con ten ts of all the Alarm
Registers are treated as matching the corresponding clock
counters, and an ALARM signal will be output externally.
Alarm EN should therefore be set to 0 before resetting the
alarm.

8-58

(2) In the case of the RP5C15, no data can be written to the
Alarm Register for 100 ~sec. after the Alarm F/Fs have been
reset.

This is because an Alarm Reset signal lasting a maxi-

mum of 100
edge of WR.
the

~sec.

is generated internally after the leading

In contrast to this, the Alarm Reset signal in

RP5COI is generated within the duration of WR = low,

making

it possible to write data into the Alarm Registers

immediately (See Fig. 9-4).

CPU WR signal~L__________~
5COl's internal
Alarm RESET signal
CPU WR signal~
I
5C15's internal
~----------~
Alarm RESET signal
~f

I

------------------~Max.lOO~sec.~------

I

I

Fig. 9-4

(9-3) Alarm function when battery backed-up
Alarm can be used when battery is backed-up.
The characteristics

between VOL and IOL and ALARM

terminal (open-drain output) at

the temperature of

Ta = 25°C is shown in Fig. 9-5.
VOL (V)
0.5

I

0.4

0.3

0.2

0.1

Fig. 9-5

o

2

3

456

IOL(mA)

8-59

(10) Setting leap years

Initial setting of leap years is necessary for both the RP5COI
and RP5C15.
The Leap-Year Counter consists of a Mod 4 count-up counter which
counts up at exactly midnight on 31 December in the same way as
the year counter.

Twenty-nine days are counted in February when

the Leap-Year Counter is 00.
Table 10-1 illustrates the relation between the Leap-Year Counter
and the leap year.

Leap-Year Counter
Dl

DO

0

0

The current year is a leap year

0

1

A

leap year is due 3 years from now

1

0

A

leap year is due 2 years from now

1

1

Next year is a leap year
Table 10-1

I f the Leap-Year Coun ter is in i t ial ized correctly, and prov ided

that the contents of the counter are not destroyed by battery
failure or other causes, the date will be adjusted automatically
for leap years up to the year 2099.

(The year 2100 is not a leap

year.)

8-60

(11) Test Register

The Test Register is for high-speed function testing of the

RP5COI and RP5C15 when shipped by Ricoh, and its contents must be
set to (0,0,0,0) for correct clock operation. with the RP5C15,
it is immaterial how many times 0 is written to this register,
but with the RP5COl, there is a danger of destroying the clock
data depending on the particular CPU in use.

This problem may

arise with CPUs that do not satisfy the AC characteristics tWDL
max.

40 nsec., but will not arise with ZSO, 6S09, S085, 6S00 or

6502 CPUs.

Some 8-bit single-chip microcomputers do not satisfy

tWDL.
It is therefore recommended that with the RP5COl, the Test Register should be cleared immediately before clock data is written at
the initialization of the RP5COl, rather than each time the power
is turned on. For details, please refer to the flowchart.

I

8-61

(12) Week counter
The week counter is a Mod 7 count-up counter.
The relation between the counter value and the day of the week
can be chosen freely by the user.

(13) Year counter
The year counter is a Mod 100 counter (two Mod 10 counters.)
It can be used for either the Japanese calendar (Showa era) or
the Western calendar.

(14) State of the RP5COI and RP5C15 at switch-on
None of the bit-values of either the RP5COI or the RP5C15 are
fixed at switch-on.

They should therefore be initialized by

software. Particular care should be taken to set the Test Register to 0 as mentioned in (11) above.

If the RP5COI or RP5C15

are properly backed up, none of their data will be destroyed.

8-62

(1S) Adjustment function
The RPSCOI has an ADJUST terminal and can be adjusted directly as
shown in Fig. IS-I, but in the case of the RPSClS, the adjustment
function is effected by an internal register.

Commands must

therefore be written to this register from the CPU.

Fig. 15-2

shows an example of adjusting the RPSCIS using the CPU interrupt.

Adj. SW

~r
3
0--

"

Adj us t

RP seDl

Fig. 15-1 Connection of adjust
terminal of RPSCOI
,
,

:r-

Adj. SW-{]

~

DO
RST7.S

Dl
D2
D3

7fT

CPU

AO

808S

Al
A2
A3

R1J

R15

WR

WR

IO/M"
AIS
A14

Fig.

~

L()

.-i

u

L()

p.,

Il::

CS

lS-2 Example of connection of adjust
terminal of RP5C15 (with CPU8085)

8-63

I

(16) Flowchart
(16-1) When system power is
(16-2-2) When reading clock

switched on

data twice (Note 3)
START

Write (0,0,0,0) to Test Register (address E) (Note 1)

(16-2) Read clock data

NO

(16-2-1) When stopping clock
to read data (Note 2)

again

Write (O,X,O,O) to Mode
Register and stop clock

NO

Write (l,X,X,X) to Mode
Register and restart clock

NO

*X denotes "1" or "o"L------;=~~~
(determined by program)
(Note 1) The above flowchart applies to the RP5C15 when used with
any

cpu.

When the RP5COI is used with a

cpu

that does not

satisfy the AC characteristics tWDL(max.) = 40 nsec., however,
the Test Register should be cleared whenever the clock data is
rewritten. (Refer to 16-3.)
(Note 2) When a power failure is detected, the clock should be
started immediately.
(Note 3) When reading out the clock data twice, there is a possibility of incorrect data being read out only when the seconds
count is '9'.

There is no possibility of this when the

seconds count is other than '9', so it is not necessary to
read the clock data twice.

8-64

(16-3) Writing clock data
(16-3-1) When stopping clock

(16-3-2) When writing data without

to write data

Write (0,0,0,0)

stopping clock (Note 5)

(0,0,0,0) to Test

to Test

Register (Note 4)

Register (Note 4)

Write (O,X,O,l) to Mode Register and stop clock (Note 7)

l.Set to 12 or 24 hour system
2.Set Leap-Year Counter

NO

Finished?

Write (O,X,O,O) to Mode Register, stop clock and set
BANK to 0 (Note 8)

(Note 4) This step is unnecessary if

a

Reset15-stagedivider(Note6)

is written to the Test Register

when the power is switched on.
(Note 5) When clock data is written
without stopping the clock, the
writing operation must be completed within 1 sec. including
any time for which the power is

Finished? >-_-=N.:..:O,-,

shut off, and must be set to the
12/24 hour system and Leap-Year

YES

Counter.

Write (I,X,X,X) to Mode Register and restart clock

(Note 6) Write '1'

to bit 1 of ad-

dress F so that the 15-stage
dividers are reset.
(Note 7)

(O,X,O,l) applies to the

RP5COI only.

For the RP5C15,

read (O,X,X,l).
(Note 8) BANK

a

applies to the

RP5C15, MODE 00 to the RP5COI.

8-65

I

(16-4) Setting alarm

To disable KEARN output, write
(1, 0, 0, 1) to Mode Register

To reset alarm, write (X, X, 0, 1)
to Re se t Con troll er (Address F)

100 Ilsec.?

NO

(Note 9)
YES

Finished?

t\o

YES
To enable ALARM output, write
(1, 1, X, X) to Mode Register

(Note 9) The 100 Ilsec. wait time is necessary with the RP5C15
only, not with the RP5COI (See pages 56 and 57).
(Note 10) When using the RP5COI with a CPU which does not satisfy
the AC characteristic tWDL = max. 40 nsec., special care
must be taken when writing to addresses D, E, and F.

The

sales department of Ricoh should be consulted for technical
advice in this case.

8-66

(17) Items to check after program preparation

(17-1) When the clock only is to be used (not the alarm)
(a) Has the hour counter been set to either the 12-hour or the
24-hour system? (Address A of Bank 1)
(b) Has the Leap-Year Counter been set? (Address B of Bank 1)
(c) Has (0,0,0,0) been written to the Test Register?

(Address E)

Note: "Bank 1" is used in the RP5C15 and "Mode 01" in the RP5COl.

(17-2) When using the alarm
(a) Was the Alarm F/F reset before writing data to the Alarm
Register (bit

a

of address F)?

(b) Was the alarm disabled before being reset (bit 2 of address
D) ?

(c) Is there a wait time of at least 100 Msec. between resetting
the Alarm F/F and writing data to the Alarm Register? (only
needed with the RP5C15.)

I

8-67

(18) Malfunction during testing

(18-1) Clock data advances extremely fast.
possible causes:

(1) OB has not been written to the Test Register -- see Section

11.
(2) The clock is oscillating incorrectly -- see Section 3.
Check point:
Output a standard clock signal from the ALARM terminal (in
the case of the RP5COl and RP5C15) or CKOUT terminal
(in the case of the RP5C15) and check whether or not the
clock is oscillating correctly.

For the RP5COl, the bypass

condenser set between pin 17 and GND is sometimes
for external noise.

effective

Its value should be less than 60 PFr

according to the measurements carried out by Ricoh.

(18-2) The hour counter goes past 52 and up to 60.
possible cause:
(1) The 12/24 Register has not been set when data is written.
This fault occurs because the clock is set to the 12-hour
system when .the power is switched on, and hour da ta from
12 - 23 is written into the hour counter.
-- See Section 17.
Check point:
Check whether the clock has been set to the 12 or 24 hour
system.

8-68

(18-3) The alarm does not function correctly.
Possible cause:
(1) The alarm has not been reset.
-- See Section 9.
Check point:
Check whether the alarm is being reset before data is written into the Alarm Register.

(18-4) The ALARM terminal remains at low.
Possible causes:
(1) The pull-up resistor is not properly connected.
-- See Section 9.
(2) The alarm is being reset internally when the power switched
on (when not in the battery back-up mode), and the Alarm EN
F/F is also being enabled, causing the ALARM terminal to go
low. -- See Section 9.
Check points:
(1)

Check the pull-up resistor.

(2) If the alarm is being used, write data into the Alarm
Register.

If the alarm is not being used, the Alarm

EN F/F should be disabled.

I

8-69

(19) Power supply
(19-1) Battery backup
Power-down
a) System
power supply
I
5V
b) RP5COl, _~_ _-+~ I (A) 5V-5% (10%) I I
Z~,,--RP5C15
VBATT
:~=--n
I
I
c) cs

~'--r---------t~

. .'1"<;::-------+:

II:
i

d)

r-

i i

I

./(B)

III
II,
access I I I
access
I I access
- - poss ible rl"1l>,,:""";--inhibi ted-----r-r-I+1;0101 poss ible
,-I-l, ,

I

Fig. (19-1)

tAC

(Note) VBATT means battery backup voltage and tAC is one of AC
electrical characteristics.
With both the RP5COl and the RP5C15, the time taken for the
power supply Vcc to rise or fall depends mainly on the relative
timing of the power-down signal CS and Vcc. It therefore depends
strongly on the structure of the power-down detection circuit.
If, for example, either the RP5COl or RP5C15 is being used with
Vcc ~ 5% (10%) as the standard, CS must go low by the time Vcc
crosses po in t (A) of Fig. 19-1, and hig h after the time Vce crosses
point (B). In other words, the rise time of Vcc must be set so
that the output of CS can satisfy these conditions. As long as
this is done, there are no other particular restriction on the
rise and fall of Vcc.
However, so as to keep within the usual limits for CMOS-ICs,
the input voltage to all terminals, VIN, should always satisfy
the following relation:
VIN ~ vcc + O. 3
When constructing the circuit, the timing shown in Fig. 19-1 ca
be achieved by suitable selection of the capacitance of the
bypass condenser shown in Fig. 19-2.
The best way of simplifying the circuit for generating CS is
usually to make the decay time of Vcc long and the rise time
short.

8-70

r---~----~--~Vcc

R

Fig.

RP5COl

19-2

It is also important to ensure that no voltage exceeding vcc +
O.3V is applied to any of the terminals of the RP5COl or RP5C15,
especially while vcc is going positive or negative as the switch
is turned on.

It is therefore recommended that the RP5COl or

RP5C15 be accessed via a CMOS driver, open-collector buffer or
open-drain buffer using a common power supply for Vcc.

I

8-71

(20) Differences between RP5COI and RP5C15

The design of the RP5C15 is based on that of the RP5COl, but the
following differences exist:
(a) The RP5C15 has no 26 x 4-bit RAM
(b) pin 3 is the ADJUST input terminal in the case of the RP5COl,
but the CKOUT output terminal in the case of the RP5C15.

The

adjustment function is carried out by an internal register in
the case of the RP5C15.
(c) It is necessary to pull up or pull down the address bus and
other input terminals and the data bus and other output terminals in the case of the RP5COl, but not in the case of the
RP5C15.
(d) A 100kn resistor is needed for the OSCOUT terminal of the oscillation circuit in the RP5COl, but not in the RP5C15.
(e) The definition of the AC characteristic tAC is different for
the two clocks.

In the RP5COl, it is defined as the time

between address valid and the trailing edge of CS·CS·RD!WR,
while in the RP5C15, it is defined as the time from CS =
high, CS = low and address val id to the trail ing edge of
CS·CS·RD!WR.

(See Section 5).

Compatibility of RP5COI and RP5C15
The RP5COI and RP5C15 were designed to be compatible in terms of
both software and hardware.

If an RP5C15 currently in use satis-

fies the following conditions, it can be replaced by an RP5C15
without modifications.

8-72

(1) The RAM is not being used.
(2) The adjustment function is not being used.
(3) The alarm function is not being used.

However, if the ALARM

terminal (pin 15) is being used to output a 1Hz or 16Hz clock
signal only, then satisfying conditions

(1), (2) and (4) is

sufficient to guarantee software and hardware compatibility.
(4) The AC characteristic tAC of the RPSCIS is satisfied.

The reason why the alarm functions of the RPSCOI and RPSCIS
are not compatible is as follows:
(a) The RPSCOI allows data to be written to the Alarm Register
immediately after the alarm has been reset (bit 0 of address
F is Alarm Reset F/F).
(b) With the RPSClS, data cannot be written to the Alarm Register
for 100

~s

after the alarm has been reset (bit 0 of address

F). However, if the RPSCOI is programmed so as not to allow
data to be written to the Alarm Register for 100

~s

after the

alarm has been reset, the two clocks will be software-compatible even if the alarm function is used.

As stated above,

pin 3 is an input terminal for the RPSCOI and an open-drain
output terminal for the RPSClS, so if its ADJUST terminal is
pulled down (i.e., if the adjustment function is not being used),
there will be no problem in replacing an RP5COI by an RPSClS,
even if the open-drain output of the latter is pulled down.

I

8-73

Real Time Clock RP/RF 5C62
Application Manual
Version 1.1

I

EA-012·8904

8-75

Contents
CHAPTER 1 SPECIFICATIONS
FEATURES
BLOCK DIAGRAM
PIN CONFIGURATION
PIN DESCRIPTION
ABSOLUTE MAXIMUM RATINGS
RECOMMENDED OPERATING CONDITION
DC CHARACTERISTICS
AC CHARACTERISTICS
TIMING DIAGRAM
PACKAGE DIMENSION
FUNCTIONAL DESCRIPTION

CHAPTER 2 DATA SHEET
1. OSCILLATOR
1) Oscillator circuit
2) Note in design using the oscillator circuit
3) Measurement of oscillation frequency
4) Fluctuation in oscillation frequency
5) Adjusting the oscillation frequency
6) Others
2. CONSUMED CURRENT
1) Reset current consumption
2) Operating current consumption
3. CONNECTION TO CPU
1) 1/0 interface circuit
2) CPU connection circuit
3) AC timing
4. POWER SUPPLY CIRCUIT
1) Power supply switching sequence
2) Power supply switching circuit
5. EXPLANATION OF OPERATIONS
1) Operation
2) Software processing

CHAPTER 1

SPECIFICATIONS

I

RP5C62 and RF5C62 are CMOS real time clock LSls for microcomputers. RP5C62 and RF5C62
have clock, calendar, and alarm functions. They can be directly connected to the data buses of
8 bit or 16 bit CPUs such as 8086, Z80, 6809, 6502 and 68000. With a built-in timer counter,
they can be used as watch-dog-timer or interrupt timer.

• FEATURES

• Directly connected to CPU, enabling fast access.
• 4 bit bidirectional data bus, and 4 bit address bus
• The oscillator is driven by a constant voltage, so the oscillation frequency is stable (within
± 1 ppm) even when the power supply voltage fluctuates.
• Built-in timer counter using internal clock
• Generates cyclic c.PU interrupts, and generates alarm-match interrupts.
• Interrupt flag and interrupt inhibit
• Clock (hour, minute, second), calendar (leap year, year, month, day, day of the week), alarm
(hour, minute)
• 12- or 24-hour mode is selectable.
• Recognizes leap years automatically.
• 'All clock and alarm data expressed in BCD codes
• ± 30 secQnds adjustment function
• Determines whether clock data is valid or invalid.
• Consumes very ,low power due to CMOS technology, so it can be backed up by batteries.
• 5V single power supply
• Package: 18-pin DIP for RP5C62, 18-pin SOP for RF5C62 .

• BLOCK DIAGRAM

OSCIN
OSCOUT

,INTR

I

CE

cs
iii -ft:::U~-tll~--------1----+t-<*-..j

TIMER

,TMOUT

LVDD
;;-vss
Ilil III If! 11.:1

All AI A'!. AJ

8-79

• PIN CONFIGURATION

18 PIN DIP & SOP

cs

VDD
OSCOUT
OSCIN
INTR
D3
D2
DI
DO
WR

CE
TMOUT
AO
Al
A2
A3
RD
VSS
TOP VIEW

• PIN DESCRIPTION
Symbol

Name

Function

CS
CE

Chip select
Chip enable input

CS and CE are used when interfacing external devices. They may be accessed
when CS is low and CE is high. CE is connected to a power down detector on
the system power supply side, and CS is connected to the microcomputer adress bus.

TMOUT

Timer outpu t

Timer output may be used as an interrupt free-run timer or watchdog timer.
When CE is low (running on battery backup), operation stops (there is no output). It is N-ch open drain output.

AO-A3

Address input

Address input is connected to the CPU address bus. It is gated internally with
CEo

RO

Read control input

When RO is set low, the contents of the counters or registers specified by AOA 3 are output to DO - D 3. It is valid when CS is low and CE is high. It is
CMOS input.

WR

Write control input

When WR is low or rises from low to high, the contents of DO - D 3 are written to registers or counters specified by A 0- A 3. WR is valid when CS is low
and CE is high. It is CMOS input.

DO-D3

Bi-directional data
bus

DO - D 3 are connected to the CPU data bus. The input section is gated internally with CEo It is CMOS input/output.

INTR

Interrupt output

INTR outputs timing CLOCK interrupts or alarm match interrupts to CPU. It also
operates when CE is low (at battery backup). It is N-ch open drain output.

OSCIN
OSCOUT

Oscillator circuit
input/output

Crystal oscillator of 32.768 KHz must be connected between OSCIN and
OSCOUT. Capacitance is connected externally between VDD and OSCIN and
VDD and OSCOUT, fOrn\ing the oscillator circuit.

VDD
VSS

Power supply

VDD connects to +5V and VSS to ground_

8-80

• ABSOLUTE MAXIMUM RATINGS
Symbol

Parameter

VDO
VI
VO
PO
TA
TSTG

Supply Voltage
Input Voltage
Output Voltage
Maximum Power Consumption
Operating Temperature
Storage Temperature

Condition
VSS=O
TA = 2S o C

Value

• RECOMMENDED OPERATING CONDITION
Symbol
VOO
VCLK
fXT

Parameter
Supply Voltage
Supply Voltage of Clock
Crystal Oscillation Frequency

Unit

-0.3-+7.0
-0.3 - VOO+0.3
-0.3 - VDO+0.3
300
-20-+70
-40 - +12S

V
V
V
mW
DC
DC

(vss=ov. TA--20 - +Jo·el
Condition

MIN.

Typ.

s.o
2.0

MAX.
6.0
6.0

Unit
V
V
kHz

MAX.

Unit

VOO+03
0.8
VOD+03
0.2.VOO
0.4
0.4

V
V
V
V
V
V
V

32.768

• DC CHARACTERISTICS
Symbol

Parameter

Pin Name

VIHI
VILI
VIH2
VIL2
VOHI
VOLI
VOl2

"H" input voltage
"l" input voltage
"H" inpu t voltage
"L" input voltage
"H" output voltage
"L" output voltage
"L" output voltage

Ao-A3,Oo-03
CS,RD,WR
CE

IILK

Input leak current

lOll
IIOl2
IDOl

1D02
af

Output off leak
current
Consumption
current for
back·up
Consumption
current for
stand-by
Oscillation frequency drift for
voltage drift

Condition

DO-03
INTR, TMOUT
Ao-A3,CE,
CS,RD,WR
00-03
INTR, TMOUT

IOHI = -4001lA
lOLl =2mA
IOL2= 2mA

MIN.
2.2
-03
0.8.VOO
-0.3
2.4

Typ.

VIlK = VOO or VSS

-I

I

pA

VOII = VOO or VSS
VOI2=VOO

-S
-2

S
2

IIA
pA

VOO

VOO=2.SV

Input:
VOOorVSS

3

pA

VOO

VOO=S.sV

Output:
OPEN

8

IIA

I

PPM

OSCIN
OSCOUT

VOO=2.S-S.SV
Ta=2S·C

-I

(Unless Noted, VSS=OV, VDD=SV±10%, TA= -20 - +70·C,
X'tal=32.768 kHz (CI;:a3S KG), Co= S pF, CD= 10 pF)

8-81

I

• AC CHARACTERISTICS

-

-

(vss=OV TA- -20-70'C Notel; VDO-lV±IO'I. Note2' VOD=3V+IO'I. Note)' VOD=IV+20'l.)
Symbol
tCES
tCEH
tAA

Description
Time for which CE musl be kept "HOI before the address is determined.

Note2

Note3
MIN 100 MIN 1000 MIN 100

Unit
nS

CE hold lime

Time for which CE must be kept "H" until the address rinishes
changing.

MIN 100 MIN 1000 MIN 100

nS

Address setup time
(llD)

Time for which the address must be determined before CS=RD=lOl",

MIN 20

nS

ICS

CS setup time (RD)

IRD

RD selup lime (RD)

tOH
IC5Z
tRDZ

Data hold time (RD)
CS output delay time

WR selup time (WR)

tWC5
tWR

cS pulse width (WR)

IWH

WR pulse width (WR)
Data setup time (WR)

Address CS hold lime
(WR)
Addre.. WR hold time
(WR)
Data hold lime (WR)

nS

MAX 120 MAX 291 MAX 110

nS

MIN 10

n5

MAX 71

n5

MAX 70 MAX 91

MAX 71

n5

MIN 20

MIN 20

MIN 20

n5

or WR while CS is "L".

MIN 20

MIN 20

MIN 20

n5

Pulse width when writing by CS while WR is ilL".
Pulse width when writing by WR while CS is "L".
Time for which the data must be determined before the rising edge of CS

MIN 120 MIN 191 MIN 110
MIN 120 MIN 191 MIN 110

n5
nS

MIN 60

MIN 95

MIN 75

n5

MIN 10

MIN 10

MIN 10

n5

MIN 10

MIN 10

MIN 10

n5

MIN 10

MIN 10

MIN 10

n5

...ror

or RD.
Time for which the address needs 10 be held after Ihe rising edge of

CS.

Time for which the address needs to be held after the rising edge of WR.
Time for which the data needs to be held after the rising edge of CS or

WR .

MIN 10

• TIMING DIAGRAM

Read Cycle

CE

Write Cycle

MIN 20

MIN 10

impedance.

(RD)

MIN 20

MAX 120 MAX 291 MAX 110

MAX 70 MAX 91

Time between che rising edge of RD and the data bus line becoming high
impedance.
Tir~~.
which che address must be determined before the trailing edge
of CS while WR is "Lit.
Time for which the address must be determined before the trailing edge

tAC5

IWDH

is determined and CS="L" (CL= 100 of)
lime for which data does not change though the address ch.mges, when
C5=RD="L".
Time between the rising edge of CS and the data bus line becoming high

RD output delay time

IAWR

tCSH

Time between the trailing edge of CS and data output, after the address
is determined and RO""I'L" (CL=I00.fI!"').
Time between the trailios edge of RD and data output, after the address

(RD)

CS setup time (WR)

IWDS

Notet

Parameter
CE setup time

AO-A3

I:tWDS
DO - D3 ...........................................................{._V_a_hd_ _ _ _ _-A

8-82

Input/Output Condition
(VDD=SV± 10'1.)
VIH = 2.2V
VIL = 0.8V
VOH;: 2.2V
VOL;; 0.8V

(VDD=3V±10'1.)
VIH = 0.8 x VDD
VIL = 0.2 x VDD
VOH = 0.8 x VDD
VOL = 0.2 x VDD

(VDD=SV±20'1.)
VIH = 2.4V
VIL = O.4V
VOH;: 2.4V
VOL;!! 0.4V

• PACKAGE DIMENSION (Unit: mm/inch)

• RP5C62 (18pin DIP)

I

Zl.g MAX

1.976 MAX)

•

I

w

r:: :::::::1]
~

I'IN#1

; .Ii~ Tn

\

rr

7

• RF5C62 (18pin SOP)
Il.XI MAX
,,1116
19

10

I
10.11*0.3

PIN#I

.406 tO.OIZ
I

.~ ~N

~

~

1.21TYP

O.4I TYP

~:A!i

,050TYP

,DI6TYP

j:&gl

~

a

\

8-83

a
"~
r,
blJT

7.49 TYP

1.4TYP

.19STYP

.os,TYP

nn
~

,II

066-+0 :I

.016*°·008

\h

• FUNCTIONAL DESCRIPTION
1. Addressing
Address Bus
0

0

I
2

Second Counter

0

I

10 ....

I

I

0

I min.

I

0

I

I

10 min.

I

I

0

0

I hour

I

0

0

0

0

0

3 0
4

0

R/W

0

0

S 0

I

0

I

10 hour

I

6 0

I

I

0

day or week

I

I;>escription

D3

D2

DI

DO

SI

S.

Sz

Cyclic interrupt select RCI.

W/O

S..

S20

SI
S,.

Adjust Reg.

W/O

M.
M..

M.
M,.

MI
M,.

Alarm I min. Reg.

R/W

I 10 min.

I

Hz

HI

I I hour

I

Mi
HI

H.

piA
or H2O

W.

D.

DI
D,.

I 10 hour

I

I month

I
I

MO.

10 month

12124 .elccl Reg.

W/O

I

I year

I

YI

Y.

Y.

Y,

Leap Year Reg.

RIO
R/W

0

10 year

I

y,.

yO!

Y20

Y,.

Timer Clock Select Reg.

W/O

0

I

Control Res. I

W/O WTBN ALBN

I

0

Control RCI. 2

RIO
RIW

BSY

I

I

Control Reg. 3

W/O

TSTA

I

C

I

I

0

D I

I

B I

I

f

I

D..
MO.

MO.

crfO ALfO

TSTiI WTRST

D2

en

AMI

AM.

DI
cr,

DO

cr.
ADJ

AM..
AHa

AH.

AM.
AM,.

AMI
AM,.

AH.

AHI

APIA
AH,.
orAHzo

MO,
MO,.

TMR

D3

cr.

I

I

0

D.

W,

I day

B I

D.

H,.

W.

10 day

7 0 I I I
I 0 0 0
9 I 0 0 I
A I 0 I 0
8

I

BANK I (BANK = I)

BANK 0 (BANK = 0)

Description

A31A21AilAO

RIO

11124
LY,

LY.

TMI

TM.
TMFO

TMR

BANK

LYB
TMI
TM.

TM.

BANK Control Reg. I

W/O WTBN ALBN

XSTP Control Res. 2

RIO
R/W

Control Rei. 3

W/O

BSY
crFO ALFO XSTP
TSTA TSTB WTRST

Note I) R/W bits can be read and written. RIO bits can only be read. W10 bits can only be written.
Note 2) It is no problem to attempt writing to RIO bits and don't care bits, but the attempt will fak
Note 3) If W10 bits and don't care bits are read, the returned value is o.

2. Counter/register functions
1) Clock and calendar counter (addresses 0 to C of BANK 0) (read and write)
• The clock is in units of hour. minute. and second. The calendar function includes year,
month. day and day of the week.
• Data is expressed in BCD codes.
• 12- or 24-hour time display is selectable for clock output. The display in the hour counter
is as follows:
12-hour display: AM12-+AM1-+···-+AM11-+PM12-+PM1-+···-+PM11-+AM12
(The piA bit indicates AM when 0 and PM when 1.)
24-hour display: 0-+"'-+23-+0
• Write to the hour counter after selecting 12- or 24-hour time display by the 12/24 select
register.
• The day-of-week counter is a septinary counter. and is incremented when carried to the
day counter.
(Count W4·W2·Wl =000-+001-+01 0-+ ... -+ 11 0-+000)
Note 11 DO NOT write values which are not valid (such as AM 15. or February 30). This
causes misoperation.

8-84

2) Cyclic interrupt select register (BANK 1 address 0) (write only)
• Selects the cycle for cyclic interrupt based on the INTR output and the output mode.

--

CT3 CT2 CT. CTo

*
*
*
*
*
*
*
*
0
1

Description

INTR

0

0

0

"OFF"

Inhibit cyclic interrupt

0

0

1

2048 Hz

Cycle T

0.488 ms (2048 Hz)

0

1

0

1024 Hz

1

1

128 Hz

1

0

0

16 Hz

1

0

1

1 Hz

1

1

0

1160 Hz

t
t
t
t
t

0.977 ms (1024 Hz)

0

1

1

1

"ON"

* * *
* * *
Note 1)

7.813 ms ( 128 Hz)
62.5 ms (

16 Hz)

1

s(

1 Hz)

60

s (1160 Hz)

INTR Output = "L"

Pulse mode

Cyclic pulse

Level mode

Note 1)

duty 500/0

INTR
(interrupt)

interrupt

interrupt

Write 0 to CTFG
Note 2)

INTR and Second Count-up
(j)pulse mode (1 Hz or 1/60 Hz select)

-i

1-+-30.5"s

Second Count-up--.J
@Ievel mode (1 Hz or 1/60 Hz select)
INTR

Second Count-up

3) Adjustment register (BANK 1 address 1) (write only)
• The adjustment register is for correcting seconds of clock and calendar counters. The
second is adjusted by writing 1 to the ADJ bit.
(a) When the second is 00 to 29: Makes the second counter 00, and does not carry
to the minutes counter.
(b) When the second is 30 to 59: Makes the second counter 00, and carries to the
minutes counter.
• It takes 122.1 J.Ls at most to complete the adjustment after writing 1 to the ADJ bit.
The BSY bit of the control register 2 is set to 1 until adjustment is completed. During
that time, do not write to or read from the clock or calendar counter.

8-85

I

4) Alarm register (BANK 1 addresses 2 to 5) (read and write)
• This register stores hours and minutes for the alarm.
• Data is expressed in BCD codes.
iDa NOT write invalid values such as AM 15. This causes misoperation.)
5) "1""2/24 select register (BANK 1 address A) (write only)
• When the "1""2/24 bit of the "1""2/24 select register is 1, the 12-hour time display selected.
If it is 0, the 24-hour time display is selected .
• Set the 12- or 24-hour time display before adjusting the clock or setting the alarm.
6) Leap year register (BANK 1 address B) (write and read)
• This register indicates leap years; When LY 1= LYo = 0, it is a leap year. (LY 1 and LYo are
read only.)
Every time the year counter is incremented, LY1 and LYo change as follows:
00-+01-+ 10-+ 11-+00.
• Setting the year counter automatically sets the leap year register. (A leap year is set when
84, 88, ••• and 00 are set to the year counter.)
• The LYE bit can be written to. It performs leap year operation when set to 0, and does
not when set to 1. Writing to the year counter sets the LYE bit to O.
7) Timer clock select register (BANK 1 address C) (write and read)
• Selects the input clock for the timer counter (in the write mode).
TM3 TMz TMI TMo

TI

Note I)

T2 Note 2)

Timer Inhibit Note 5)
(TMOUT '" OFF)

T3

Note 3)

0

* * *

1

0

0

0

562 ms

562 -

626 ms

625

1

0

0

1

281 ms

281 -

313 ms

312.5 ms

1

0

1

0

140 ms

140 -

157 ms

156.3 ms

1

0

1

1

70.3 ms

70.3 - 78.2 ms

78.13 ms

1

1

0

0

35.1 ms

35.1 - 39.1 ms

39.06 ms

1

1

0

1

17.5 ms

17.5 - 19.6 ms

19.53 ms

1

1

1

0

8.78 ms

8.78 - 9.77 ms

9.766 ms

1

1

1

1

4.39 ms

4.39 - 4.89 ms

4.833 ms

+-

Note 1)

Note
Note

Note
Note
Note

+-

ms

The maximum time for the reset cycle (maximum reset cycle when used as a watch-dog timer)
not to output L from the TMOUT output after resetting the timer counter (writing 1 to the
TMR bit of the control register 1).
2) Time between the timer counter reset and the "L" pulse output from the TMOUT output.
3) The cycle of a pulse output from the TMOUT output when the timer counter is not reset (That
is, when used as a free-run timer. However, the time between the timer counter reset and
the first pulse output from the TMOUT output is T2. The cycle for the second and subsequent
pulses is T3).
4) When CE '" "L" (battery backup), the timer stops (TMOUT output", OFF).
5) When oscillation stop is detected (XSTP bit'" '1), the TM3 bit is reset to 0 and the timer is
inhibited (TMOUT output", OFF).
6) When TM3 bit'" 0, the timer counter is reset.

8-86

• When the TMOUT output is "L", the TMFG bit is "H" (in read mode).

U

-+l I+- O.244ms

TMFG

____~----~--~rl~----~
rTlTT2

Writing I
10 TMR bil

~14

T3-------.J

Wriling I
10 TMR bil

8) Control register 1 (address 0 of BANK 0 or 1) (write only)
• Correspondence with data buses
03
02
01
DO
WTEN
ALEN
TMR
BANK
CDWTEN bit ........ When the WTEN bit is 1, clock counting is valid. When it is 0, clock
counting is disabled (carrying of seconds is inhibited). This bit is also
used when reading the time. (To read time, this bit is set to 0, then
returned to 1 after reading. If a carry pulse is input to the seconds'
counter while WTEN =0, the seconds' counter is incremented by only
+ 1 for compensation when WTEN bit is returned to 1. Only one carry
is compensated correctly by + 1. Even when there are two carries, only
one carry is compensated.) When the CE input terminal is "L", this bit
is set to 1.
®ALEN bit ......... When the ALEN bit is 1, the INTR output becomes "L" if the specified
alarm time and the actual time match (alarm match operation). When
this bit is 0, the alarm match operation is disabled.
@TMR bit .......... Writing 1 to this bit resets the timer counter. This bit is used for watchdog timers.
@)BANK bit ......... The BANK bit is for switching the address banks. When this bit is set
to 0, BANK 0 is selected. When set to 1, BANK 1 is selected.

8-87

I

9) Control register 2 (address E of BANK 0 or 1) (read, partially write)
• Correspondence with data buses

03

02

01

DO

BSY

CTFG

ALFG

XSTP

CDBSY bit ...... When the BSY bit is 1, DO NOT read or write the time or calendar. The
BSY bit is read only.
This bit is set to 1 in the following cases:
iii ± 30 second adjustment

----IF

(ii)

+ 1 compensation
(When one second is carried
for compensation when returning WTEN from 0 to 1.)

----IF

=-11----

MAX122.1ps

Write I to AD] bit

Adjustment completed

MAX122.1ps

=+!I----

+ 1 compensation completed

Write I to WTEN bit

(iii) Normal one second carry
91. 61'S

~

.

30. 51's

~

Carry to the second counter

(iv)WTRST
(Resetting the 8 Hz to 1 Hz
dividers)

----IF

MAX122.1ps

Write I to WTRST bit

11--Reset completed

@CTFG bit ..... The CTFG bit is set to 1 when cyclic interrupts occur (lNTR = "L'·'). The
CTFG can be read. Only 0 can be written to it. A value of 1 cannot be
written to it.
When CT 3 bit= 0
(pulse mode)

CTFG _ _......J

When CT3 bit = 1
(level mode)

CTFG _ _---I

When CT3= 1 (level mode), writing 0 to this bit makes the INTR output "OFF"
(in pulse mode, a write is not possible).

8-88

@ALFG bit ........ The ALFG bit is set to 1 when there is an alarm match interrupt
(lNTR = "L"). The ALFG can be read. Only 0 can be written to it. 1
cannot be written to it.

ALFG _ _---'
INTR
Alarm match

Alarm match

Alarm match

Write 0 to ALFG bit

When ALFG = 1, writing 0 to this bit makes the INTR output "OFF".
@XSTP bit ........ The XSTP bit is an oscillator stop detection bit, and is set to 1 once
oscillation stops. This value is maintained even after oscillation restarts.
When power is initially applied, this bit is set to 1 before oscillation
starts. This bit can be used for determining whether the clock or alarm
data is valid. The XSTP bit can be read. Only 0 can be written to it.
A value of 1 cannot be written to it. When an oscillation stop is detected,
the TM3 bit of the timer clock select register is reset to 0, and the
timer is inhibited (TMOUT output = OFF).

10) Control register 3 (Address F of BANK 0 or 1) (write only)
• Correspondence with data buses
03
02
01
00
TST A
TSTB WTRST
CDTSTA bit ....... The TSTA bit is a test bit. Writing 0 to this bit sets the test mode. Set
this bit to 1 at initialization. This bit is set to 1 when CE = "L".
@TSTB bit ........ The TSTB bit is a test bit. Writing 0 to this bit sets the test mode. Set
this bit to 1 at initialization. This bit is set to 1 when CE = "L".
@WTRST bit ..... Writing 1 to the WTRST bit resets 8 Hz to 1 Hz dividers. The reset is
released and counting starts a maximum of 122.1 J.LS after 1 is written
to this bit. This bit is used to adjust the values of the seconds and lower
counter.

I

CHAPTER 2

DATA SHEET

I

8-91

1 . OSCILLATOR
1) Oscillator circuit

VDD

RI'

Recommended crystal oscillator is:
32768 Hz CI value;;li 35 kll
Recommended working ranges of
CG and Co are:
CG: 5 pF to 35 pF
CD: 5 pF to 35 pF
RF: Typical 8 Mil built in
RD: Typical 250 kll built in

I

I

:-A

I

-----;;;..:

Figl,lre 1
The oscillation circuit for 5C62 can be made up from a 32 kHz crystal oscillator and two
capacitors externally attached as shown in Figure 1. The 5C62 has a feedback resistor (RF),
a stabilizing resistor (RD), and an inverter built in.
A crystal oscillator with CI (series resistance) value equal to or smaller than 35 kll is
recommended. To fine-adjust the oscillation frequency, use either CG or CD as a trimmer
capacitor. The oscillator circuit of the IC is driven by a constant voltage circuit using VDD as
reference, so connect one side of the oscillation capacitor to VDD, not to VSS.

2) Note in design using the oscillator circuit
To design a PC board around the oscillator, consider the following:
(a) Locate the crystal, CG, and CD as close to the IC as possible.
(b) DO NOT route a signal line or power line near the oscillator (especially near segment
A in Figure 1).
(c) Raise the impedance between the OSCIN and OSCOUT terminals and the PC board
sufficiently.
(d) DO NOT route OSCIN and OSCOUT in parallel or with long conductor runs.
(e) When there is a possibility of condensation on the PC board due to changes in the
environment, it is recommended to coat the soldered part of pins 16 and 1 7, crystal
oscillator, CG, and CD on the PC board and the routing of OSCIN and OSCOUT with
damp proofing materials. This is because condensation often stops the oscillation.
When the oscillation stops, the oscillation detection flag is set and the timer is disabled
at the same time. So, to use the functions of the oscillation detection flag or the
timer, take precautions to prevent oscillation from stopping due to condensation.

8-93

I

3) Measurement of oscillation frequency

To check the frequency of the crystal oscillation, set the internal registers as indicated
below. Use a frequency counter to measure the clock output from the INTR terminal. DO
NOT attach a probe directly to the OSCIN or OSCOUT terminal; the CG and Co values change
after a probe is attached, affecting the oscillation frequency, so it cannot be measured
correctly.

Control register 1 +- (1)H

ALEN bit is 0, BANK bit is 1.

Control register 3 +- (CIH

TST A and TSTB bits are 1.

Control register 2 +- (O)H

CTFG and ALFG bits are O.
CT3, CT2, and CTt bits are 0, and CTo
bit is 1.

Cyclic interrupt select register +- (1 )H

To write to a register, set the CE terminal to H. After the above processing, a 2048 Hz clock
signal is output from the INTR terminal (which must be pulled up to VDD with a resistor).
(To measure the frequency in a precision of about 1 ppm, use a frequency counter with a
six to seven digit display.)

4) Fluctuation in oscillation frequency
After mounting the crystal oscillator, the crystal oscillation frequency fluctuates according
to the externally attached oscillation circuit capacity (CG, CD), power supply voltage, and
changes in the ambient temperature. Figures 2 to 5 show examples of these typical
characteristics.
Figure
Figure
Figure
Figure

2
3
4
5

Typical oscillation frequency characteristics when CD is fixed and CG is varied
Typical oscillation frequency characteristics when CG is fixed and CD is varied
Typical oscillation frequency characteristics when VDD is changed
Typical oscillation frequency characteristics when the ambient temperature
is changed

Note) Figures 2 to 5 do not indicate absolute deviation of oscillation frequency (that is,
precision); they indicate relative deviation from a certain base point.

8-94

Figure 2

Typical oscillation frequency characteristics VS CG

(PPM)
..................................

+80

I

I

I

I

I

!

I

II

I
I

+60 ···············..··············f···· ..........!.................................. , ........·························r··········..·················...,..................................,...................................
i
I
I
I
i
!!

ii

I i
,

>.

u
&::
--A.-A.

• A. -A.

D.-D.

D.-D.

RD
WR

I

POllerdolln
detector

r

BS

BA

A. -A. t======~A. -A.
D. -D.
R/W 1---.----;-,

CE

68000 and 5C62

5C62
Address
Decoder

ALE

--

~-19 ~

AD.-..

JE

1~
A.-

68000

5C62

CS
A.-A.

A.-A.

19

D.-D.

BJf[

D.-D.

Latch

RD
WR

I

~

D. -D.

E f--t...f---LJ

RD
WR

8086 and 5C62

8086

5C62

6809

POllerdolln
detector

R/W
LOS

D.-D.

r

RD
WR

RD
WR

CE

8-109

I

4. POWER SUPPLY CIRCUIT
1) Power supply switching sequence
There are two types of power supply: the supply for system operation and the battery
for system stand-by. To switch between these supplies, vary the CE input terminal level
as shown in Figure 15.

VDD - - System power
/
supply voltage ~

1-

Lower limit of CPU
operation voltage
.

I~ Battery voltage
I

o.2~1

CE

j
!

i

H
Figure 15

i

i

I
I

!ko

I
I

h

I

Hn~ OiJlS

Iml OiJlS

To switch to the battery voltage, decrease CE to the "L" level before the voltage goes
lower than the CPU operation voltage. To switch to the system power supply, wait until
VDD is higher than the operating voltage of the CPU and set the CE input to "H" level.
2) Power supply switching circuit

System power supply

5C62

INTR
THOUT
OSCIN
Cl

OSCOUT
VDD

Figure 16 shows an example of the circuit
around the power supply circuit. In the
example, a lithium battery is used. Locate
the capacitor as close to the IC as possible
(if possible, use a ceramic capacitor of
O.OlI'F or more and a tantalum capacitor in
parallel). Connect one side of the oscillation
circuit capacitor to VDD (the oscillation
circuit is driven by a negative regulator from
VDD, with VDD as reference).
Pull up the INTR and TMOUT outputs to the
system power supply side so that no invalid
current flows from the battery during battery
backup (the INTR output operates when
CE = "L", and the TMOUT output does not
operate when CE = "L"I.

Figure 16

8-110

5. EXPLANATION OF OPERATIONS
1) Operation
(a) Write
To write values to the internal counter register, set the CE terminal "H" and specify
the counter register address at terminals AO to A3. Then set the CS terminal "L" and set
the WR terminal "H" -+ "L" -+ "H" (CS and WR may become "L" at the same time,
or WR may become "L" first). Likewise, the. data input to DO to D3 terminals are written
internally. Read-only bits are not affected by this write operation.
(b) Read
To read the internal counter register, set the CE terminal "H" and specify the counter
register address at AO to A3 terminals. Then set the CS terminal "L" and set the RD terminal
"H" -+ "L" (CS and RD may become "L" at the same time, or RD may become "L" first).
Likewise, internal data can be read from DO to D3 terminals. Write-only bits are reset to
by this read operation.

o

(c) Clock, calendar
5C62 has an hours/minutes/seconds counter in BCD code for the clock and a leap
year/year/month/day/week register and counter for the calendar. When the year is specified
by the dominical year, leap year operation is automatically performed. After setting the
year, you can set the leap-year register not to perform the leap-year operation.
(d) Alarm
5C62 has alarm registers (hours and minutes) for generating interrupts at specified time.
These registers may be used for daily alarms. An alarm interrupt can operate even when
the CE terminal is "L" (such as during battery backup), and is output from the INTR terminal.
Alarm interrupt and clock interrupt are ORed together and output from the INTR terminal.
(e) Clock interrupt
A timing clock interrupt or level interrupt can be output from the INTR terminal every
0.448 msec to 60 sec. The counter for this interrupt is the same as the counter for the
clock, so the clock interru'pt cannot restart. 0.488, 0.997, 7.813 and 62.5 ms interrupt
cycles are not affected by clock operations. The 1-sec interrupt cycle is affected when
1 is written to the ADJ bit or the WTRST bit. The 60-sec interrupt cycle is affected when
1 is written to the ADJ bit (for the effect of the ADJ bit, see the next section, Software
Processing, ± 30 sec adjustment of the seconds digit. When operating the WTRST bit,
the change timing of the INTR output is the same as that of the ADJ bit). Clock interrupt
is output even when CE is "L" (such as during battery backup).
(f) Timer interrupt
5C62 has an independent timer counter. You can select a timer interval from 4.883 ms
to 625 ms. The timer output is output from the TMOUT terminal. The timer can restart,
and can be used not only as an ordinary timer but also as a free run timer or a watch-dog
timer. When CE is "L", the TMOUT terminal is OFF and timer operation stops temporarily.
When CE becomes "H", the timer restarts and it outputs pulses. When the XSTP bit is
set to 1 upon detection of oscillation stop, the timer operation is disabled. (At that time
the D3 bit of the timer clock set register is reset, and the timer is reset.) The timer is affected
by the output of the oscillation stop detection circuit, so set the XSTP bit to 0 when using
the timer (if the oscillation is not stopped, the timer starts o.peration when the timer clock
select register is set even when XSTP = 0). For a fail-safe system using a timer, it is

8-111

I

recommended to have a routine to write the timer cycle setting data occasionally to the
timer clock select register.
(g) Oscillation stop detection
5C62 !;las a built-in circuit to detect oscillation. When the oscillation detection circuit
detects an oscillation stop, the internal XSTP bit is set. This bit is set to 1 when the power
supply voltage decreases and the oscillation stops, and is maintained at 1 even if oscillation
restarts. This bit is also set to 1 at power-on, and is maintained at 1 even if the oscillation
restarts. The minimum working voltage for oscillation is about equal to the sum of the
threshold voltage of MOSTr of Pch and Nch. Internal data is held as long as oscillation
is maintained.
The XSTP bit can be used to judge whether the system has risen from OV or from the
battery voltage, or whether the backup batteries are weak. To use the XSTP bit, consider
the following: condensation on the PC board may stop the oscillation and make the XSTP
bit 1. Prevent condensation around the oscillator beforehand. Also, take care to prevent
temporary power failure and check the layout of the PC board around the oscillation circuit.
2) Software processing
The following is an example of software processing. Flowcharts are shown later.
(a) Processing when power is turned on.
At initial power on, internal conditions are not determined, initialization is required. There
are two flowcharts for processing at power on: one does not use the XSTP bit, the other
uses it. The XSTP bit can be used to judge the validity of the internal data at initial power
on. In the second example, the XSTP bit is used for judging the necessity"of initialization
routine.
(b) Read and write of-clock and calendar
The clock and calendar must be written to only while a carry is not performed. When
writing data, stop the clock by setting the WTEN bit to 0, and check that a carry is not
being performed, using the BSY bit. Also, the clock and calendar must be read only while
a carry is not performed, because wrong data may be read while carry is performed. To
prevent this, it is recommended to use one of the following three methods for reading:
CD Stop the clock temporarily, and read the value while the clock is stopped. If the clock
is stopped for 1 sec or less, the clock does not delay and there is no problem (even if
the system enters the backup mode while the clock is stopped, the clock starts counting
when the CE terminal becomes "L". If it does not become "L", counting must be started
by the software).
® Use a clock interrupt to read the value.
@) Read the clock twice, and judge it correct if the two values match.
(c) Writing to alarm clock
Example of writing the alarm time.
(d) ± 30 seconds adjustment of the seconds digit
Shows an example of ± 30 seconds adjustment of the seconds digit.

8-112

Power on procedure

G2

(XSTP bit is not used) Power-on procedure (2) (XSTP bit is used)
(Initialization follow)
(as when batteries are used)
Internal register and output

Considerations In using XSTP
1. Prevention of oscillator condensation
2. Prevention of temporary
VOD failure
3. Prevention against noise by
PC board design for the oscillation circuit

terminal values are not de-

termined when the power
is turned on from

ov.

Processing to make the
INTR and TMOUT outputs "H" 10FF)

..___....»:___--,

.....

I

Processing to set the
jlNTR output to "H"
(OFF)

I

V((TMOUT Is "H" (OFF))
when XSTP = 11

....

........
To raise VOO from OV, a wait time
Is required to activate the 32 kHz
crystal oscillator. Also, set the
timeout processing to escape
from this loo~.

Setting
12/24-hour time display Clock, calendar
Alarm time Cyclic
Interrupt TIMER output cycle
\......................

'-----,,-----'

..............

..

Setting
12/24-hour time display Clock, calendar
Alarm time Cyclic
Interrupt TIMER out::~
put cycle

I

After setting the clock and alarm,
set WTEN or ALEN to 1 to activate them •

............................... _ •• , ...................................... ,1

lock and alarm time need not be set when VDD
Judged to have risen from backup voltage such
I batteries by another processing route.

This Is the path when the Internal data Is
judged to be valid.

8-113

Write of clock and calendar

or

read of clock and calendar

ill

.. ,," Set this once before writing to tha clock.
..... Set it at power-on initialization .

.....

When the BSY bit is 1. continue reading until it
.............•. becomes 0, or wait at least for 122.1~s.

Write to clock and
calendar

If the one-year or ten-year counter is written to. the leap year operation is

-:::........... performed (There is no need to set the leap-year register). To disable the leap-

OR

Read of clock and
calandar

L-----,r-~---l ..~~............

year operation, write 4H (LYE = 1) to the leap-year register after setting the
clock and calendar (writing to the one-year or ten-year counter sets LYE to
0). There is no problem if an invalid value occurs during setting. Make it a
valid value, however, before returning WTEN to 1 (leap year operation is
performed without compensation " ...til 2099).

WTEN is set to 1 when the CE input is "L" (such as when the system power
is off).

Make the reading time 1 second or less. If it Is 1 second or less. the carry that occurred

while reading is compensated by the Increment when WTEN is returned to 1. If it is longer
than 1 second, two carries may occur, and compensation is made only once when WTEN
Is returned to 1, resulting in a delay of 1 second.

8-114

Read of clock and calendar

®
(Note 11
When INTR is set to the level

Interrupt to CPU
by the INTR output of 5C62

.:::........••............ m.o~e interrupt '103 bit ~f th~ cY'-1
chc Interrupt se ect register IS
•.

........

No

~----~ To interrupt processing of other ICs

(Note 21
When reading the clock and calendar finishes within (lNTR set cycle - 30. 5,.sl after the INTR output goes "L". (To prevent reading
mistakes due to a carry during
readl

.........

• This read is possible when the above two conditions (notes' and 21 are met.
If the INTR set Interrupt cycle is short, be careful of the Interrupt processing
time.

Read of clock and calendar @

111;:••••••- •• _ .........

•.:::~. Carry of the clock and the calendar is performed In the following order:
..•...•.....
, second digit (address 01 ... , 0 seconds digit (address '1 .........
....
1 year digit (address 81'" 10 years digit (address CI. (including delay
timel. Read the clock 'In the order from eddress , to address C .

. The path for re-reading to prevent wrong values from being read, when
• .....••-•..••... the first' second digit data does not match the second data because
.....
data Is reed before end after the carry.

The path when the values are correctly read.

8-115

I

Write of alarm time

, If an invalid value i•• elln Ihe alarm regisler, il i. no problam; Ihe alarm malch
/ operation i. ju.t nol performed. Afler setting ALEN to 1, however, set an

,/

;~.,;'w••

r-----l~---,;..:..

When the alarm time Is sel 10 Ihe same time as Ihe clock, eilher of Ihe
following occurs:
ALEN = 0: ALFG is O.
ALEN = 1: ALFG i. sel to 1 and INTR to "L" within 61.1I's.

Raference)
When the ALEN bil is 1 and the clock malches the alarm lime, ALFG = 1
and INTR - "L". There are two ways to set INTR = "OFF" and ALFG = 0:
wriling 0 10 Ihe ALFG bil and wrillng 0 10 Ihe ALEN bil. Afler wrillng 0
to Ihe ALEN bit, returning the ALEN bil from 0 10 1 while the clock matches
the alarm time, ALFG becomes 1 and INTR becomes "L" wilhin 61. 11's
al mOSI.

+ 30 seconds adjustment of the seconds digit

....•.

r----.....---...,.~::. /'

The 8 Hz to 1 Hz divider below the digll of second is reset and restarted.
When 8 clock Interrupt of 1-second or 60-second cycle Is set end iiiiTR = "L",
INTR becomes OFF In the timing shown below.
(There Is no effect on INTR if the cycle Is other than 1-second or 60-second.l

OFF
L

./

t;?

Writing 1
to ADJ

\..
U
200
- - P to
I's

\
Up to 122.11's Is required to finish the adjustment. During the adjustment,
the 8SY bit Is 1.

8-116

2-Dimension Filter 5C67
User Manual

I

NO. EU-005-8908

8~117

5C67

• Space filtering
Space filtering means to extract specific
information and elements required for input
image data. It is analogous to general FIR type
filters (such as low-pass and band-pass filters for
communications), performed on image data that
consists of i X j dot matrix.
To perform image filtering on pixel m in
Figure 1, output M is calculated by equation (1)
from point m and from data of surrounding
points (neighbor pixel areas, for example, from
point a to point y).

M = a X W 11

+ .... +

+b

Neighbor pixel a rea

1
a

b

f

g

k

1

p

q

r

s

t

u

v

w

x

y

(a

+

b

+

c

+ .... +

m

+ .... +

d

e

h

i

j

m

n

0

c

Figure 1 Input pixels

+ .... +

m X W33
Y X W55 ............................................... (1)

X W 12

Wij is a two-dimensional filter coefficient as
shown in Figure 2. Performing the operation on
all input pixels enables space filtering.
Space filtering enables various image processing, for example, smoothing images, extracting edges, and enhancing edges. To
smooth images, specify filter coefficients as
shown in Figure 3. The neighbor pixel data items
are averaged by equation (1) as follows:

1
M =25

Processed pixel

W
11

12

13

14

1S

21

22

23

24

Z5

31

a2

W
a •

.4

.s

41

42

4a

44

45

51

52

53

54

55

Figure 2 Filter coefficients

y)

1125
With the output of the average value, pixels
are smoothed. This operation can be used to
eliminate fine noise on images.
Figure 4 shows the filter coefficients for edge
enhancement, which displays characters
clearly.
Space filtering can be applied to various
types of processing by changing filter

1125

1125

1/25

1125

1125

1125

1125

1125

1125

1125
1125
1125

1125

1125
1/25
1125

1125

1125

1125
1125

1125
1125

1/25
1125

Figure 3 Filter coefficient example

coefficients.

-1
-1

-1
-1

-1

-1

-1
-1
-1

25

-1

-1

-1

-1

-1

-1

-1
-1

-1

-1

-1
-1
-1
-1
-1

Figure 4 Filter coefficient example

---------------ltD©®OO8-119

I

5C67

• Outline of 5C67
Space filtering takes a long processing time when performed on a general-purpose CPU or DSP. So
it is necessary to write all image data to memory before filtering, which makes it difficult to perform
real-time filtering. Also, when a speciallC for filtering is designed with gate arrays, filter coefficients must
be fixed because the circuit scale is large, which means different gate arrays must be made for different
types of processing. RICHO's two-dimensional image filter RF5C67 solves these problems. RF5C67 is a
special LSI that performs space filtering on 5 X 5 pixel area quickly and flexibly.
• High speed: 25 ns/pixel max.
• Flexible:
Possible to change filter coefficients
• 5C67 Features
• 5 X 5 image area flat surface filtering
• Operating frequency:
20 MHz
25 ns/pixel (Odd-Even mode, two 5C67s use)
• Processing speed:
50 ns/pixel (Serial mode, one 5C67 use)
6-bit, integer
• Pixel data:
7-bit, two's compliment, changeable
• Coefficient data:
10 (Odd-Even mode)
• Number of input data items:
5 (Serial mode)
• CMOS process
V single power supply
• Package:
• Rounding:

• +5

100-pin flat package
.When the calculation result is a positive value and overflows, it is
rounded to 63 (maximum value).
When the calculation result is a negative value:
Rounded to 0
Absolute value is taken

}seIecta bl e

-IIU©®OO---------,-------8-120

SC67

• Operation
RF5C67 contains 15 multipliers, a divider,
and an FA block that performs rounding. Figure
4 shows the internal block diagram.
(1) Product sum calculation unit
Performs product sum calculation of five
data items for each main scanning line.
(2) Addition unit
Adds the resultant data of the product sum
operation for five lines.
(3) Division unit
Divides the resultant data of the product
sum operation of 25 pixels.
(4) FA block
Rounds the final result of space filtering,
and obtains the final output result.

Division
unil

l

figu~

E nlarged
sum calculation unit

UQ

_______
~

Figure 4 Block diagram

I

----------------ICD©®DO8-121

5C67

(a) Filter coefficient
To perform MTF compensation (edge enhancement) with the coefficients shown in Figure 5, regard
these coefficients as shown in Figure 6. Specify coefficients 0, - 1, - 2, and 32 to the 15 multipliers
and coefficient 1/16 to the divider.
To specify coefficients to multipliers and dividers, use address inputs Ao to A4 and CS and WS
terminals.
Filter coefficients must be symmetrical, or with reverse sign, to the sub scanning lines, including
the attention pixel. So there are 15 coefficients as shown in Figure 7. For specification, enter those
15 coefficients and 10 plus and minus signs.

1

-]

Y6
1

1

1

16 -8- 16
1
1 ~
2 ~
8 ~
16 8

1

16

1

1

-8- 16

-2

-1
-1

-2

-1

32 -2

-2

-]

1

I6

-1

Figure 5

Figure 6

(b) Serial mode and Odd-Even mode
RF5C67 performs space filtering in two

-1

IIIll

III •• 111., ±III, • ±Wu

III ••

IIIz• 111., ±W •• ±III Zl

1
X

Hf \11.,

III,.

W
... ±W •• ±W31

W4].

W.z

III ••

-1

W
s• W"

±W •• ±W41

W
s• ±Wsz ±Ws•
Figure 7

--~

Main scanning direction

011 DlZ DlO D'4 D15 D•• .. .. .. ..

modes:
CD Serial mode
® Odd-Even mode
In the serial mode, one pixel data item is
entered for each of the five main scanning
lines (totally five data items) simultaneously, and one pixel processing result is
output. The processing speed is 50 ns/pixel max.
In the Odd-Even mode, two pixel data items
are entered for each of the five main
scanning lines (totally ten data items) simultaneously, and two filtering results are
output for one line simultaneously. This

Dz.
D31
D41
D»
D••

Dz•
D3•
D••
D,.
D••

Dz•
D.,
D••
Os.
D••

D..
D••
DH
Ds.
D••

D2 S
D35
D. s
Dss
D. s

D. s . ... .. ..
D•• .... .. ..
D46 ... ' ....
Ds• . ... .. ..
D•• . ... .. ..

gives processing twice as fast as that in the serial mode: 25 ns/pixel. However, in the Odd-Even
mode, two RF5C67 filters must be used.
The following explains the processing of the image data shown in the above figures in the serial
and Odd-Even modes:

-ICD®®[){]--------------8-122

5C67

CD

Serial mode

Figure 8 shows a 5 X 5 area, with the
pixel to be filtered at the center. Enter the
five pixel data items on the same sub
scanning line in order, and synchronized
with the clock. The processing results are
output in order, after a certain delay time,
in synchronization with the clock.

I

For example, when pixel data items are
entered in the following order: (011, 021,
031,041,051), (0 12,022,032,042,052), (013,
023, 033, 043, 053), ... , filtering results are
output as follows: F(033). F(034), F(035), ...
The same pixel data item must be entered

I)Il,D 11.D"

DII.O,,,O,"

nAT

C
L DAI
L DAI

('LK

DAn

D'1.D "'[)2n

0

11 ,0,.,1)"

Du,DOI,D,"

[)Il,DJ!,D l1

DAII

0.,.,

-X,X,F([),,),r(D H )

D",D",[),"

D".I)",O"

[)

Q'

r~

L-I~

DCIIO-'

Do-D,

-'!.....

01 SI

••

SPliS
OlliS

D810-5

DCI0-5
~-

Output
Data

n11 n iT

AO-A4

D8HO-·5

'----> D3

f--l-

TlST2

D.U[O-5

'--. D2

.
b

TIN~

DI1[0-5

~

~
D'

DOIO-5
01.10-5

Q'

~t

00-'
SGN
OVR

DOI0-5
-----<0

=l

5 C 61

DOIO-5

'---

(MAX

0_••

D810-5

CK

CKQ~I

iT 3

DBRO-5

rm ..,e Data

~

Address BUS

. DQ-DJ 01 SET

DUO-'
DAlIO-5

L'

:>----CLok

-

Bus

5C6 1
0 0-

7

DDIO-S

DDIIO-'
DII0-5
DI.D:O-5

f--.CLK

Et
f--t-

SGN
OVR
TINi
TISTI
T18T2

I

.on.)

---------------ICO®®OO8-133

I

Voltage Detector RX5VA series
Application Manual
Version 1.0

I

NO. EA-8-8809

8-135

RX5VA Application Manual
Contents

§1

Specifications
Outline
Features
Applications
Block Diagram
Pin Configuration
System Block Diagram
Absolute Maximum Ratings
Electrical Characteristics
Functional Description
Measurement Circuit
Typical Characteristics
Package Information
Taping Specification

§2

Application
RX5VAX X AStandard Circuit
RX5VAX X B Standard Circuit
RX5VAXXCStandard Circuit
RX5VAx X ASprit Vss Sources
RX5VAX X B Sprit Vss Sources
RX5VAXXAPropagation Delay Circuit (1)
RX5VAXXAPropagation Delay Circuit (2)
Memory Backup Circuit
Voltage Level Indicator LED Driver Circuit
Voltage Level Indicator LED Driver Circuit
Higher Voltage Detector
Window Comparator Circuit
Over Charge Protection

§3

Selection Guide
Selection Guide

8-137

I

§1

Specifications

I

8-139

RX5VA Appli. Manual

• Outline
RX5VA series, developed with C-MOS processing technology are accurate, low-power-consumption
voltage detectors. The detectors include comparators, output drivers and hysteresis circuit.
The value of detect voltage is set internally, and is accurately controlled by Laser Trimming.
There are three types of output: N-ch open-drain, P-ch open-drain, and C-MOS. There are two
convenient packages: mini-power-mold and TO-92. The RX5VA series can be used as a reference
voltage supply for ICs in many applications.

• Features
•
•
•
•
•
•

Extremely low power consumption. . . . . . . . . . . . . . . . . . . . . ..
Wide voltage range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Variety of detect voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
High accuracy .......................................
Good temperature characteristic for detect voltage. . . . . . . . . ..
Output Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

• Compact Package ....................................

TYP. 1.0p,A (VDD=3.OV)
1.5V to 10.0V
0.1 V step
±2.5%
TYP. ±100 PPM;oC
N-ch open drain,
P-ch open drain,
CMOS
TO-92, min-power-mold

• Applications
• Resets circuit of P-ch, N-ch, and C-MOS microcomputers
•
•
•
•
•

Battery checker
Logic circuit reset
Level discriminator
Waveform shaping circuit
Switching circuit for battery backup

• Power failure detector
• Pin Configuration

• Block Diagram

TO-92

Mini-Power-Mold

I~Woll
3

1 23

(TIT)

o

Fig. 1

Block Diagram

OUT

3. VSS

Fig. 2

8-140

1.

2. VDD

Pin Configuration

RX5VA Appli. Manual

• System Block Diagrams
Figure 2 is block diagrams of RX5VA series and shows the system with three terminals.
The system has three types of output drive: N-ch open-drain, P-ch open-drain, and C-MOS.

N-ch open-drain

P-ch open-drain

(RX5VAXXAX)

(RX5VAXXBX)

C-MOS
(RX5VAXXCX)

en

E

~
.!!!

C>

o

~

tJ

.2
Cl

VDD
-VOET

...."-

vss

<0

.s:;

u

(1)

E

VDD

i=

vss

3-terminals
mini-power-mold
TO-92

Fig. 3

System Block Diagram

8-141

I

RX5VA Appli. Manual

• Absolute Maximum Ratings
SYMBOL

RATINGS

Supply Voltage

VDD

12

Output Voltage

VOUT

VSS-0.3-VDD+0.3

Output Current

lOUT

70

mA

Pd

300

mW

Operating Temperature Range

Topr

-30-+80

Storage Temperature Range

Tstg

-40-+125

PARAMETER

Power Dissipation

Soldering Temperature

Tsolder

UNIT
V

°c

260°C (10 Sec)

• Electrical Characteristics
PARAMETER
Detect Voltage
Hysteresis

Supply Current

Operating
Voltage

SYMBOL

CONDITION

MIN.

TYP.

(-VDET)
X 0.975

-VDET

MAX.

UNIT

(-VDET)
X 1.025

V

(-VDET)
X 0.05

VHYS

V

VDD= 2.0V

0.9

2.7

3.0V

1.0

3.0

4.5V

1.15

3.45

6.0V

1.3

3.9

10.0V

1.7

5.1

Iss

VDD

1.5

10.0

p.A

V

Nch

VDS=O.5V

Output Current

lOUT

VDD:l.0V

0.5

2.4V

3.6

3.6V

6.5

4.6V

8.6

6.0V

11.6

'10.0V

19.6

mA

Pch

VDS=2.1V
Temperature
Coefficient

~(-VDET)

/~Ta

VDD:4.5V

-30°C ~Ta~80°C

8-142

0.04
±100

PPMtC

RX5VA Appli. Manual

• Functional Description
VDD

0

In the case of the RX5VAXXA
type, the drain of the Nch. transistor is connected to the OUT
terminal.

o In the case of the RX5VAXXB
type, the drain of the Pch. transistor is connected to the OUT
terminal.
o In the case of the RX5VAXXC
type, the drain of the Nch. transistor and the drain of the Pch.
transistor are connected to the
OUT terminal.

VSS
Fig. 4

Block Diagram
Internal Conditions

Operating Conditions

Supply
Voltage
(VDD)

Operating State

(i)

®

®

@

®

Comparator
(+) Input Voltage

I

II

II

II

I

e~7f:~e

+VDET

e~~;~e

Comparator Output

H

L

L

L

H

-VDET

Tr . .1

OFF

ON

ON

ON

OFF

ON

OFF X:
Unstable OFF

ON

OFF

ON

X:
Unstable ON

OFF

Min. operating

Output Tr.

Voltage
VSS

II Pch
Nch

Rb+Rc

I. Ra+Rb+Rc· VDD
II.

Output Voltage

Ra~Rb

• VDD

VSS

Fig. 5

Operating State Description

Description of Operation
CD Output voltage is equal to supply voltage (VDD).
~ On the A point, Vref ~ VDD· (Rb + Rc) I(Ra + Rb + Rc) and then the output of the comparator

is inverted to VSS.
The A point shows the detect voltage (-VDET).

Gl When the supply voltage is smaller than the minimum operating voltage, the output transistor
becomes "Unstable" and outputs VDD voltage if the output is pulled up.
@) Output voltage is equal to VSS.
lID On the B point, Vref ~ VDD . Rbi (Ra + Rb) and then the output of the comparator is inverted
to VDD.
The B point shows the cancel voltage (+VDET).
The hysteresis width is the difference between the cancel voltage (+VDET) and the detect voltage
(-VDET).

8-143

I

RX5VA Appli. Manual

• Measurement Circuit

VDD----=:.......,

VDD----r----,

Rn: RX5VAX XA
IOOKO

I-"O'-¢-VDET

Rp: RX5VAx XB
lOOKO

VSS----+---------- VSS

VSS--'"
Fig. 6

Fig.7

Consumption Current Measurement Circuit

VDDI---...,

Voltage Detect Measurement Circuit

VDD---...,

f-o---VDD-Z.IV

vss----+-----vss

vss - - - + - - - - - vss
Fig.8

Nch Driver Output Current Measurement
Circuit

Fig.9

Pch Driver Output Current Measurement
Circuit

+7.0V

+7.0V

Ro
6.0VJI
l.OV
P.G.

VSS--

ru

lOOKO
r-o-""""-+--OUT
Co

Ro
6.0VJI
l.OV
P.G.

VSS--

~---+---~--vss

Fig. 10

ru

lOOKO
!--<>--+-OUT

~~---+----.vss

Fig. 11

Propagation Delay Time Measurement
Circuit (1)

8-144

Propagation Delay Time Measurement
Circuit (2)

RX5VA Appli. Manual

• Example of the RE5VA40C
2.5

T~~

0

V

V
v: ~

....

~ l. 5

:;
c

.Q 1.0

V

.~
.... v

E
Oil

II

f-

::J

g 3.0
OJ

I

:§; 2.0
....:::J
B
:::J

~

15.

V
RL;'100KO

2: 4.0

25·C

V , /V
V ....... V V

I~

U

§

5.0

o

0.5

1.0

U

1/ \
9

10

1.0

2.0

Fig.12

Fig.13

Consumption Current - Input Voltage

20

5.0

E
- 14

./'

f-

o

f.--

VIN
3.0V

./

12

E 10

/

~

88

/

~V
V r-

~ 6

84
r

~V
0.5

3.0

~ 2.0

u

SQ.

8

1.0

1.5

2.0

2.5

3.0

3.5

I

V

/
1.0

2.0

3.0

4.0

Input Voltage VIN (V)

VDS (V)

Fig.14

/

'//
/1/

OJ

2.0V

/

.AI /

....c

1.5V
1.0

:I

E

§
2.5V

/SO!C./

~ 4.0

f-

.....-

5.0

-3J·cA 5-cY

JsvA10c

VDS=0.5V

~ 16

4.0

Output Voltage - Input Voltage

-'

18

::J

3.0

Input Voltage VIN (V)

I nput Voltage VIN (V)

Fig. 15

Nch Driver Output Current - Vos

8-145

Nch Driver Output Current - Input
Voltage

5.0

•

RX5VA Appli. Manual

~

I-

2"/",

RESVA40C
Ta=2S'C

/

:::l

.Q 2.0

/

t:CD
t::

1.0

::J

o

4.3

tuo

1.5~
7

V

+VDET

>CD

C)

~
o

>

_ f..-- ~~

o

4.1

&l

VDET



3.9
-40

-20

o

20

Pch Driver Output Current - Input Voltage

Fig. 17

".

1111111

1,

60

80

100

Detect Voltage - Ambient Temperature

I J 111111

J:1m\rl

10

R~J~l~~l

/

B-

40

Ambient Ta (oC)

Input Voltage VIN (V)

10

t--- I---

4.0

S

Fig. 16

-

4.2

l--- ~

--

V

::J

U

~

RESh40C

VDS=-

3:0

~

4.4

I

• tPLH'

Vv

B- 1
CD

CD

teLH

E

E

i=

i=

o'"

'"
o

>-

>-

tPHL

Q;

Q;

].I

10- 1

10-

1

V

trHL

10-'
10-'
10-'
10- 1
Output Terminal External Capacity Co (IlF)

Fig. 18

10-'
10-'
10-'
10- 1
Input Terminal External Capacity Ci (IlF)

Propagation Delay Time - Output
Terminal External Capacity

Fig. 19

8-146

Propagation Delay Time - Input Terminal
External Capacity

RX5VA Appli, Manual

• Package Information

* SOT-89 Mini-Power-Mold . Plastic Package

• Pi n Configuration

1: OUT
2': VDD

3: VSS

• Mark

CD0 : Type Number (Code Number)
®® : Lot Number

Fig. 20

* TO-92 Plastic Package for Taping Method

* TO-92 Plastic Package
5.2MAX

I

'I

4.2MAX

E

[dj~J

~

[~J

#.,

5.2MAX

'I

[~J

~

[~~

r~j

[~~l
~
~

O.6;"'lAX

~
N

'I

Z

t
~

O.5 MAX

o
UNIT: mm

Fig.21

UNIT: mm

• Pin Configuration

Fig. 22

1: OUT
2: VDD

3: VSS
• Mark

CD0®®®®CV® : Type Number
®@@@

Lot Number

8-147

I

RX5VA Appli. Manual

• Taping Specification
* SOT-89 Mini-Power-Mold . Plastic Package
• Tape Dimension and Direction

2 kinds of taping method (n, T2) are available.
4.0±O.1

o o o o
'"<:>

+1

'"

=~IJ (~I===.JIJ
n Type

1.:::11

=~IJ

1.:::11

===.JIJ_...:......:=..JL-

[I!::I

T2 Type

UNIT: mm

Fig. 23

• Reel Dimension

1000 pieces can be contained in one reel.

C"I')

iI

li~7

==:;-1,--rlr--r=====:

+1

'"
rb178+2

Fig. 24

8-148

UNIT: mm

RX5VA Appli. Manual

* TO-92 Plastic Package
• Tape Dimension and Direction

2 kinds of Taping Method (RF, RR) are available.

14.5 MAX

.7±O.2
00

j

~~"±"'
RF Type

UNIT:

mOl

RR Type
Fig. 25

• Reel Dimension

2000 pieces can be contained in one reel.

I
--j

r-.p30

:

T'L
I

I.

.p360

~
Fig. 26

8-149

TI
.1

UNIT: mm

§2 Application

I

8-151

RX5VA Appli. Manual

• RX5VAXXA Standard Circuit
(Nch Open drain)

• RX5VAXXB Standard Circuit
(Pch Open drain)

r-----~------~----~VDD

r-------------~----~VDD

VDD

CPU

CPU

GND
R
IOOKO

• RX5VAXXC Standard Circuit
(C-MOS Output)

GND

• RX5VAXXA Sprit Voo Sources
(Nch Open drain)

r-----------~~-----1VDD

VDDl

.... VDD2

r-----~------

Von

VDD

CPU

CPU

GND

• RX5V AXXB Sprit Vss Sources
(Pch Open drain)

Minimum Operating
GND~
1- VOETI:
!
Voltage

-VSSI

::

:

GND

L-____-4______.... -

,

: :

I+VDETI

~~~SlIJIi
:!
,

CPU
R
lOOKO

,

:,
:,
,

VSS2

:

'

:'

:,,
'

-VSS2

• RX5VAXXA Propagation Delay Circuit (1)
(Nch Open drain)

• RX5VAXXA Propagation Delay Circuit (2)
(Nch Open drain)

r-----~----~~-----.VDD

r-----------~------~------VDD

Rl
lOOKO

VO[)

CPU

GND

8-152

RX5VA ADDIi. Manual

• Memory· Backup Circuit
VDD~~~~----~--------~~----~----~----,

Dt

D2

VOl>

• Voltage Level Indicator
LED Driver Circuit
(Pch Open drain)

• Voltage Level Indicator
LED Driver Circuit
(Nch Open drain)

,..--------,---- VDD

• Higher Voltage Detector
(Nch Open drain)

,..-----.. VDD

VDD

Detect Voltage = Ra;bRb . (-VDETl

Ra

Hysteresis Voltage = Ra;bRb . (- VHYSl
Note) The detect voltage may be differ·
ent from the calculated voltage value
due to the voltage drop that derives
from increase of the current at the
Ra of the Ie when the value of Ra is
large.

Rb

• Window Comparator Circuit
(Nch Open drain)
r-----~----~----,---VDD

Vun

VDD~DETI

,

VDET2

,,

,,

'P.>+--OUT
VSS----+-----~---

OUT

rl

Vss----~-------------~---

8-}53

I

RX5VA Appli. Manual

• Over-Charge Protection

light

~

* Note

VDD

VDD
R

RX5VA
series

OUT

OUT

VSS

-=Fig. 27

1.

Fig. 28

Don't connect an impedance between VDD and Voo of the RX5VAXXB or the RX5VAXXC as
shown in Fig. 27, or oscillation may happen.
In use of the RX5VAXXA series, the detect voltage may change due to the voltage drop that
derives from increase of the current in the IC when R is large.

2.

Don't connect as shown as Fig. 28 in all RX5VA series, or oscillation may happen.

8-154

§3 Selection Guide

I

8-155

RX5VA Appli. Manual

• Selection Guide
You can define several options, including output driver type, package and packing method with the
RX5VA series.
The devices are defined by the following characters.
RX5VAXXXX

t

+-

Type number

t t t

abc d
Character

Meaning

a

Defines the packaging type
E: TO-92

b

Oefines the voltage value that is to be monitored (-VDET)
The monitor range is 2.00V to 6.00V in O.1V units, with an accuracy of ±2.5%

c

Defines the output type
A: N-ch open drain

d

Defines the packing method
A-T1 : Taping-T 1 type
A-T2 : Taping-T2 type
A-RF: Taping'RF type
A-RR: Taping-RR type
B: Gluing (Gluing is for mini power mold package as a sample)
C: Electric conductive bagging (for TO-92)

H: Mini-power-mold

B:

P-ch open drain

C:

C-MOS

Table 1

• Type Number Example
Type
number
RX5VA20AX
RX5VA20BX
RX5VA20CX
RX5VA21AX
RX5VA21B X
RX5VA21CX
RX5VA27AX
RX5VA27BX
RX5VA27CX
RX5VA45AX
R.X5VA45BX
RX5VA45CX
RX5VA47AX
RX5VA47BX
RX5VA47CX
RX5VA55AX
RX5VA55BX
RX5VA55CX

Voltage Detect (-VDET)
MIN.(V)

TYP.(V)

MAX. (V)

1.950

2.000

2.050

2.048

2.633

4.388

4.583
5.363

2.100

2.700
4.500

4.700
5.500

2.152

2.767

4.612

4.817
5_637

Output Driver
N-ch
P-ch
C-MOS
Open-Drain Open-Drain

0
0
0
0
0
0

0
0

Package

Packing
method

0
0
A: Taping

0
0
0
0

0
0

E: TO-92
B: Gluing
H: Minipower
mold
(SOT-89)

C: Electric
Conductive
bagging

0
0

Table 2

* Consult the guide to determine specifications other than those shown in Table 2.

8-156

Use the type number.

Voltage Regulator RX5RAseries
Application Manual
Version 1.0

I

EA-7-8809

8-157

RX5RA Application Manual
Contents

§ 1 Specifications

OUTLINE
FEATURES
APPLICATIONS
BLOCK DIAGRAM
PIN CONFIGURATION
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
OPERATIONAL EXPLANATION
MEASUREMENT CIRCUIT
TYPICAL CHARACTERISTICS CURVES
PACKAGE INFORMATION
TAPING SPECIFICATION
§ 2 Application

STANDARD CIRCUIT
INCREASED VOLTAGE CIRCUIT
DUAL VOLTAGE CIRCUIT
CURRENT BOOST CIRCUIT
CURRENT BOOST CIRCUIT with OVER-CURRENT PROTECTION
CONSTANT CURRENT POWER SUPPLY
§3 Selection Guide
SELECTION GUIDE

8-158

§ 1 Specifications

I

8-159

RX5RA Appli. Manual

• OUTLINE
The RX5RA series, developed with C·MOS processing technology, are highly accurate, low-powerconsumption, fixed three terminal voltage regulators. They include reference voltage supply, error
amplifier, control transistor, and resistor network to control the output voltage. The output voltage
is fixed in the IC.
The RX5RA series are both available in two different types of package: mini-power-mold and TO-92.

• FEATURES
• Extremely low power consumption .......................................... TYP. 1.0pA
• Small input-output voltage difference ....................................... TYP. 60mV

Vout = 3.0V
lout = 1.0mA

• Low temperature coefficient for output voltage ....................... TYP. ±100PPMfC
• Stable input rate ....................................................................... TYP.O.1%/V
• Accurate output voltage ........................................................... ±2.5%
• Variety of output voltage levels ................................................ 0.1 V step
• Compact package ...................................................................... TO-92, mini power mold

• APPLICATIONS
• Constant-voltage power supply for battery-powered devices
• Constant-voltage power supply for camera, communication, and video equipment
• Stable standard voltage supply

• PIN CONFIGURATION

• BLOCK DIAGRAM

TO-92

RL

Mini-Power Mold

~ ~
1 2 3

CJ
DDa

Fig. 1 Block Diagram

2

3

1 GND
2 Yin
3 Vout

Fig. 2 Pin Configu ration

8-161

I

RX5RA Appli. Manual

• ABSOLUTE MAXIMUM RATINGS

PARAMETER
Input Voltage

SYMBOL

RATINGS

UNITS

Yin

+12

V

Output Current

lout

150

mA

Output Voltage

Vout

Vin+0.3--0.3

V
mW

Power Dissipation

Pd

300

Operating Temperature Range

Topr

-30- +80

Storage Temperature Range

Tstg

-40-+125

Soldering Temperature

Tsolder

260"C

"C

10 Sec

• ELECTRICAL CHARACTERISTICS

Topr: 25"C
PARAMETER

SYMBOL

Output Voltage

Vout

CONDITION
Iout=10mA

MIN.

TYP.

MAX.

(Vout)

(Vout)

XO.975

x 1.025

UNIT
V

Vin- Vout =2.0V
Output Current

lout

Vout =3.0V

40

Vout =5.0V

60

mA

Vin-Vout =2.0V
Load

Vout =3.0V
6. Vout

ImA~Iout~20mA

Regulation

lmA~Iout~40mA

Input·Output
Voltage
Difference

60

mV

Vout =5.0V
40

Iout=1mA
Vdif

Vout =3.0V

60

=5.0V

30

8-162

mV

RX5RA Appli. Manual

• ELECTRICAL CHARACTERISTICS
Type

Number
Condi·

Topr' 25·C

Output Voltage

Output Current

Vout (V)

lout (rnA)

Load Regulation
LWout

(mV)

lnput..()utput
Voltage Difference

. Quiescent
Current

Vdif (mV)

Iss (pA)

MIN.

ondi MIN. TYP. MAX. ondi MIN. TYP.
ondi
ondi
TYP. MAX. ion
MAX. ion MIN. TYP. MAX. ion MIN. TYP. MAX.
ion

RXSRA20Ax

1.950

2.000 2.050

RX5RA2IAx

2.048 2.100 2.152

RXSRA22Ax

2.145 2.200

RX5RA23Ax

2.243 2.300 2.357

RX5RA24Ax

2.340

RXSRA25Ax

2.438 2.500

2.562

RX5RA26Ax

2.535

2.600

2.665

2.633 2.700

2.767

tion

RX5RA27Ax

2.400 2.460

RX5RA28Ax

VinVout

2.730

RX5RA29Ax

~2.0V

2.828 2.900 2.972 VinVout
2.925 3.000 3.075 =2.0V

RX5RA30Ax
RX5RA3IAx

lout

VinVout
=2.0V

f--

20 30
1.0 3.0

lmA;>
lout
:i20mA

70 160

-

2.800 2.870

3.023

3.100

RX5RA32Ax

3.120

3.200 3.280

RX5RA33Ax

3.218 3.300

RX5RA34AX

3.315

3.400 3.485

RX5RA35Ax

3.413

3.500 3.587

RX5RA36Ax

3.510

3.600 3.690

RXSRA37Ax

3.608 3.700

RX5RA38Ax

3.705

RX5RA39Ax

3.705 3.900 3.997

~lOmA

80

2.255

60 90

60

lout~

f--

lmA

3.177

VinVout
=2.0V

-

VinVout
=2.0V

3.382

50 100
1.1 3.3

27 40
I.A;>
lout
:i40mA

3.792

f--

40

3.800 3.895

I

8-163

RX5RA Appli. Manual

Topr: 25'C
Type
Number
Condi-

Output Voltage

Output Current

Load Regulation

Input-Output
Voltage Difference

Vout [V)

lout [rnA)

6Vout [mY)

6Vdif [mY)

Quiescent
Iss [I'A)

Current

MIN.

andi·
andi·
ondi· MIN. TYP. MAX. ondi· MIN. TYP. MIX.
TYP. MAX. ion
MIN. TYP. MAX. ion
MIN. TYP. MAX. ion
tion

RX5RA40Ax

3.900

4.000

4.100

RX5RA4IAx

3.998

4.100

4.202

RX5RA42Ax

4.095

4.200

4.305

RX5RA43Ax

4.193

4.300

4.407

RX5RA44Ax

4.290

4.400

4.510

RX5RA45Ax

4.388

4.500

4.612

RX5RA46Ax

4.485

4.600

4.715

RX5RA47Ax

4.583

4.700

4.817

RX5RA48Ax Yin-You! 4.680
RX5RA49Ax =2.0V 4.778

4.800

4.920

4.900

tion

RX5RA50Ax
RX5RA51Ax
RX5RA52Ax

Iou!
= lOrnA

4.875

5.000

5.022 VinYou!
5.125 =2.0V

4.973

5.100

5.227

5.070

5.200 5.330

RX5RA53Ax

5.168

5.300

5.432

RX5RA54Ax

5.265

5.400

5.535

RX5RA55Ax

5.363

5.500 5.637

RX5RA56Ax

5.460

5.600

RX5RA57Ax

5.558

5.700 5.842

RX5RA58Ax

5.655

5.800 5.945

RX5RA59Ax

5.753 5.900 6.047

RX5RA60Ax

5.850

6.000

33 50

1.2 3.6

VinVout
=2.0V
Iou!=
ImA;:;;
lout

40 60

lrnA

VinYou!
30 60 =2.0V

;:;;20.A

40 60

5.740

6.150

8-164

1.3 3.9

RX5RA Appli. Manual
• OPERATIONAL EXPLANATION
OPERATION
Yin

o--_--------+~

....--..--

9

.

fo

25'C
VIN=7.0V

~

80'C

8

I

7

20

5. 0

f-<

60

80

./

4. 8

/
/

1/

17

V

V

100

VIN=7.0V
Ta=25'C- I--

V

4. 217
4.6

Output Current lOUT (rnA)
Fig. 7 Output Voltage-Output Current

VlOmA

V

./

./

V

./

5r:.A./ V

4. 6

V

./

::>

4.8

5.0

5.2

5.4

Input Voltage VIN (V)
Fig. 8 Output Voltage-Input Voltage

5.05

0

5.04

8

7

80'C
5.03

6

€

5.02

4

~

5.01

1/

1

0

4.99

8

4.98

6

14.9

7

./

.;'j
/

4

4.96

2~ ~
6.0

7.0

8.0

9.0

5

10.0

Input Voltage VIN (V)
Fig. 9 Output Voltage-Input Voltage

V
I-/.;'1/ ~'V
./

!7

t/ V

~

[;7

10

15

~

4.95
5.0

V

A5'C V

2
Ta=25'C
IouT=lmA I--

5.00

/

25

30

35

40

45

50

Output Current lOUT (rnA)
Fig. 10 Input/Output Voltage DifferenceOutput Cu rrent

8-}66

RX5RA Appli, Manual

5. 1

1. 5
1. 4

VIN=7.0V

-t---

r-

~

!
~

0

;::

~

r---......

...c

U

Ta=2S'C

1. 3
1. 2
1. 1
1. 0

o. 9
~
o.
·13 8
0
o. 7
o. 6
4. 9
-40

-20

20

40

60

80

O. 5
5.0

100

AmbientTemperature Ta (C)

6.0

7.0

8.0

9.0

10.0

Input Voltage VIN (V)

Fig, 11 Output Voltage-Ambient Temperature

Fig, 12 Quiescent Current-Input Voltage

100

1.5

-30'C
0

VIN=7.0V

VI-'
0

..

l......-

i.---

t--

'-

V

j60
"' 70

I--"

::>

.9

60

~::s

0

./

u 4

I

-=
So

O~

30

6 20 t/'

V

l/ V
VV V v
~V

V
V

I-'

-

~~
~~

i...,..-- V
Ta=2S'C
VIN=Vreg+2.0V

I

10

o

O. 5
-40

-20

0

20

40

60

80

100

1.0

Ambient Temperature Ta (0C)

2.0

3.0

4.0

5.0

6.0

Output Regulated Voltage Vreg (V)

Fig, 13 Quiescent Current-Ambient Temperature

8-167

Fig, 14 Output Current-Output Regulated
Voltage

RX5RA Appli. Manual

~

o. 7

~
>

0.6

~

0.5

a

o. 4

~
>

\

.2l

¥

t:

Input
~-+-+---- ---- ---- -----+---+--1
,1-----1I----+_-+_+_+.,..--+----1I-~
Voltage
!to 7.0

!;:;

\

-""
'--"

~

Iout=lOmA

o. 3
2

r---

"'- t--

I

...........

oS

1.0

2.0

3.0

4.0

.e.;:;

Po

oS

-

5mA

5.0

8.0

~

7.0

~

6.0

~

5.0

~
Po

6.0

4.0

~-+-oool----- ---- ---- -----I--+-oool ~:l~!ge

0

oS

0.5

1.0

1.5

2.0

2.5

3.0

3.5

5.01I+++toIi-++++l.+bi..M-_+++_t-I+_.f.H~i-++~ Output

V

Voltage

4.0
0.5

1.0

1.5

2.0

2.5

3.0

3.5

Time t(ms)

!!

;:;

6.0

Fig. 16 Input Transition Responce 1
(lout = 1 mAl

ImA

Output Regulated Voltage Vreg (V)
Fig. 15 Input/Output Voltage DifferenceOutput Regulated Voltage

~
>

8.0

4.0

Time t (ms)
Fig. 17 Input Transition Responce 2
(lout = 10 mAl

8-168

4.0

RX5RA Appli. Manual

• PACKAGE INFORMATION

* SOT-89 Mini-Power-Mold

- Plastic Package

e Pin Configuration

o

1: GND
2: Yin
3: Vout

><

+1 ~

"' "'
N

eMark

CDCZ) : Code Number
@@ : Lot Number

UNIT: mm

Fig_ 18 SOT-89

* TO-92

* TO-92 Plastic Package for Taping Method

Plastic Package

"I

I'

4.2MAX

'I

S.2MAX

[~J

[~J

[~J

[~

[~J

~J

'I

I'

MAX

42

'I

O.SMAX

I

o
UNIT: mm

Fig. 19 TO-92

UNIT: mm

e Pin Configuratiort

Fig. 20 TO-92

1: GND
2: Yin
3: Vout

eMark

~®®CV®

®@@@

8-169

: Type Number
Lot Number

RX5RA Appli. Manual
• TAPING SPECIFICATION

* SOT-89 Mini-Power-Mold . Plastic Package
• Tape Dimension and Direction
2 Kinds of Taping Method (T1, T2) are available.
4.0±O.1

o

0

o

0

'"
o
o

~

+1
t2

N

"'

~

o

+1

'--_ _ _ _ _ _ _ _ _- ' '---+-:-:----;-_---1'0
'"

C:::;;::ll,bi:=:~:;:;::I)==nll,bl=====:::;!i=il);==

=ii;::=J;~8~.O;±~O.~l;;~=n= ~:;;I ~
=::::!JI) I\!::::I==-1) - , -5[
I,bU

T2 Type

Tl Type

UNIT: mm

Fig. 21

• Reel Dimension
1000 pieces can be contained in one reel.

UNIT: mm

Fig. 22

8-170

RX5RA Appli. Manual

* TO-92 Plastic Package
• Tape Dimension and Direction
2 Kinds of Taping Method (RF, RR) are available.

.7±0.2

~~o±"'
RF Type

UNIT: mm

RR Type
Fig. 23

• Reel Dimension
2000 pieces can be contained in one reel.

I
-j

1""-<,630

T'L
I
I.

~
<,6360

Fig. 24

8-171

TI
J

UNIT: mm

§

2 Application

I

RX5RA Appli. Manual

• STANDARD CIRCUIT

VIN

o--__

1-6-+---0 VOUT

~

Cl

C2

GND~----------~C---------~GND

•

RX5RA series can regulate voltage without capacitor
Cl and C2. When the input wire is long, use capacitor Cl. Capacitor C2 makes the transient of output
load variation smailer.
Keep the wiring as short as possible when putting
capacitor Cl and C2 of 0.1 j.lF to 2.0 j.lF between
regulator terminals and GNO terminal.

INCREASED VOLTAGE CIRCUIT
The following equation explains the output voltage.

Yin
VIN()....-.-H

\...:o~-_--()VOUT

VOUT = Vreg.(l + R2/Rl) + Iss. R2
C2

Rl

I Iss

The RX5RA series use low supply current, so R 1 and
R2 can be set high (several hundred k ohms) and
supply current of the whole circuit itself can be kept
low.
RX5RA works with constant current, so the input
voltage scarcely affects supply current of the circuit.

R2

• Vreg: Fixed output voltage of RX5RA series

• DUAL VOLTAGE CIRCUIT

VOUTl
5V

VIN n-"""::0::..1
D

VOUT2
3V
C2

As the figure shows, two RX5RA devices can be
made into a dual power circuit.
The figure shows examples with output of 3V and
5V. R is not needed when the minimum load current
of IC2 is larger than Iss of IC1. Diode 0 protects
ICl when VOU r2 larger than voun.

R

GND()....~--~---~-~~ GND

8-175

I

RXSRA Appli. Manual

• CURRENT BOOST CIRCUIT
When an output voltage more above 60 mA is neces-

Tr.l.,...._ _ _ _ _ _--.

sary. construct a current boost circuit as shown in
the figure.

!;-I5.-+-+--f"IVOUT
C2
GND~---~--~--~--f"IGND

• CURRENT BOOST CIRCUIT with OVER-CURRENT PROTECTION
The figure on the left explains the circuit construcR2

tion to protect Tr.1 from short output circuit or
over current.
lOUT
--+

By adding Tr.2 and R2 to current boost circuit
(above figure). voltage drops to Vbe2 of Tr.2 because

VIN ~-+.J\IoI\,-~---+_<>-I
Rl

VOUT
C2

GND~-------------L----~----~--~

GND

of current through R2 (It lOUT).

When' it drops.

Tr.2 will be on and will supply current to Tr.1 base.
Tr.1 will be off and will limit output current.
The

following equation

explains the

operation

current of the overcurrent protection circuit.
lOUT = Vbe/R2

• CONSTANT CURRENT POWER SUPPLY

lOUT
VINo-_~

As the figure shows. the construction can be used as
constant current power supply. Output current.
lOUT. can be found by the following equation.
lOUT = Vreg/R + Iss
Do not exceed the allowable current.
Vreg: Fixed output voltage of RX5RA series

8-176

§ 3 Selection Guide

I

8-177

RX5RA Appli. Manual

• SELECTION GUIDE
You can define the output voltage and package of the RX5RA series.
The devices are defined by the following characters.
RX5RAXXXX

.... Type number

'-.--'

t

t

t t

abc d

Meaning

No.

Defines the packaging type
a

E: TO-92
H: Mini power mold (SOT-89)

Defines output voltage (Vout)
b

The range for Vout is 2.0V to 6.0V in units of O.IV,
with an accuracy of ±2.S%.

c

Defines the output current type
A: Standard type
Defines the packaging method for shipment

d

A-Tl : Taping-Tl type (See Fig. 2)
A-T2 Taping - T2 type (See Fig.2)
A-RF: Taping - RF type (See Fig. 2)
A-RR: Taping - RR type (See Fig. 2)
B Gluing (Gluing is for mini power mold package
as a sample)
C

Electric conductive bagging (for TO-92)
Table 1

8-179

I

RX5RA Appli. Manual

• Type Number Example

Type numbers

output voltage (V out)
MIN.(V)

TYP.(V)

MAX. (V)

RX5RA21AX

2.048

2.100

2.152

RX5RA30AX

2.925

3.000

3.075

RX5RA33AX

3.218

3.300

3.382

Package

A:Taping
E:TO-92

RX5RA37AX

3.608

3.700

3.792

RX5RA40AX

3.900

4.000

4.100

RX5RA50AX

4.875

5.000

5.125

RX5RA60AX

5.850

6.000

6.150

Packing
method

H:Mini power
mold

B:Gluing
C:Electric
conductive
bagging

Table 2

* Following the selection guide, determine specification other than those shown in Table 2.
Use the type number.

8-180

Voltage Regulator RX5REseries
Application Manual

I

EA.,.016-8911
8-181

RX5RE Application Manual

Contents

§ 1

Specifications
Features
Applications
Block Diagram
Pin Configuration
Absolute Maximum Ratings
Description of Operation
Measurement Circuit
Typical Characteristics
Package Information
Taping Specification

§ 2

Application
Standard Circuit
Increased Voltage Circuit
Dual Voltage Circuit
Current Boost Circuit
Current Boost Circuit with Over-current Protection
Constant Current Power Supply

§ 3

I

Selection Guide
Selection Guide

8-183

§ 1 Specification

I

8-185

VR 5RE Manual

The RX5RE series, developed with CMOS processing technolOgy, are highly accurate, low power consumption, large output current 3-terminal voltage Regulators. They include reference voltage supply,
error amplifier, control transistor, and resistor network to control the output voltage. Because of small
input-output voltage difference, effective constant-voltage power supply can be designed. The RXSRE
series have a current control circuit to protect themself from the destruction due to over current: The
output voltage is fixed in the device. The RXSRE series are both available in two different types of
package: mini-power-mold and TO-92.
•

FEATURES
• Extremely low power consumption. . . . . . . . . . . .. TYP. 1.1p.A

(RXSRE30X, Vin = S.OV)

• Small input-output voltage difference. . . . . . . . . .. TYP. 0.5V

lout = 60mA (RXSRESOX)

• Large output current. . . . . . . . . . . . . . . . . . . . . . .. TYP. 120mA (RXSRE50X)
• Low temperature coefficient for output voltage . .. TYP. ± 1OOPPMt C
• Wide operating voltage range. . . . . . . . . . . . . . . . .. MAX. 10.0V
• Stable input rate .... : . . . . . . . . . . . . . . . . . . . . .. TYP. 0.1 %/V
• Accurate output voltage. . . . . . . . . . . . . . . . . . . .. ±2.S%
• Variety of output voltage levels. . . . . . . . . . . . . . .. 0.1V step (Note)
• Compact package .......................... TO-92, mini power mold
(Note: RX5RE30X and RXSRE50X are standard. Custom type is also available.)
• APPLICATIONS
• Constant-voltage power supply for battery-powered devices
• Constant-voltage power supply for camera, communication, and video equipment
• Stable standard voltage supply
•

• PIN CONFIGURATION

BLOCK DIAGRAM

TO-92

RL

~ ~
1

2

1 2 3

~
eeD

8-187

1 GND
2 Vin
3 Voul

3

I

VR 5RE Manual

• ABSOLUTE MAXIMUM RATINGS

Input Voitage

Yin

+12

Output· Current

lout

150

UNITS
V
rnA

Output Voltage

Vout

Vin+0.3--0.3

V

PARAMETER

SYMBOL

RATINGS

Pd

300

mW

Operating Temperature Range

Topr

-30-+80

Storage Temperature Range

Tstg

-40-+125

·c

Power Dissipation

Soldering Temperature

Tsolder

260'C

10Sec

• RX5RE50X (Vout = 5.0V)
PARAMETER
Output Voltage
Output Current
Load Regulation
Input-Output
Voltage Difference
Consumption Current
line Regulation
Input Voltage
limit Current
Temperature
Coefficient

SYMBOL
Vout
lout
AVout
Vdif
Iss
·AVout
AVinVout
Yin
I1im
AVout
ATopr

CONDITION
lout -lOrnA
Yin - 7.0V
Yin = 7.0V, ImA;;; lout;;; 80mA

MIN.
4.875
80

TYP.
5.000
120
40

or:
MAX. UNIT
V
5.125
rnA
mV
80

lout = 60mA

0.5

0.7

V

Vin= 7.0V
lout = lOrnA
I Vout i + 1.0V~ I Yin I ~ 10V

1.3

3.9

p.A

%/V

0.1
10
240

lout -lOrnA
_30°C ~ Topr ~ 80°C

±IOO

V
rnA
PPM

OC

• RX5RE30X (Vout = 3.0V)
PARAMETER
Output Voltage
Output Current
Load Regulation
Input-Output
Voltage Difference
Consumption Current
line Regulation
Input Voltage
limit Current
Temperature
Coefficient

SYMBOL
Vout
lout
AVout
Vdif
Iss
AVout
AVin·Vout
Yin
I1im
AVout
ATopr

CONDITION
lout - lOrnA
Yin = 5.0V
Yin = 5.0V, ImA ~ lout ~ 60mA
Iout=40mA
Yin =5.0V
lout = lOrnA
I Vout i + 1.0V~ I Yin I ~ IOV

MIN.
2.925
50

TYP.
3.000
80
40

To r: 25
MAX. UNIT
V
3.075
rnA
mV
80

0.5

0.7

1.1

3.3

10
lout = lOrnA
_30°C ~ Topr~ 80°C

8-188

±IOO

/lA

%/V

0.1
240

V

V
rnA
PPM

VC

VR 5RE Manual

•

DESCRIPTION OF OPERATION
Yin

0-_o__-----.......,.

""'---;0---0

Vout

The variation of output voltage, Vout, is sent to an
error amplifier by feedback resistors R1 and R2. The
error amplifier compares the variation with reference
voltage, compensates it to the opposite direction, and
adjusts the Regulator to nominal output voltage.

Rl

R2
GND~~---------~~

Fig.3 Block Diagram

• MEASUREMENT CIRCUIT

VIN

Vih

Vout

RX5RE
Series

Ci _"JpF -r-

~

~

VOUT

Co

Yin

Ci

GND ::~ IpF

IpF::~

RXSRE
Series

1--0 VOUT

GND

- '-

- '-

Fig. 4 Measurement Circuit

Vin

VIN

RXSRE
Serles

Fig. 5 Quiescent Current Measurement Circuit

I

Vout

1 - 0 - - _ - - VOUT

GND

Ro

Co
O.lpF

Fig. 6 Input Transition Relponce
Measurement Circuit

8-189

VR 5RE Manual

• TYPICAL CHARACTERISTICS (Example of RH5RE50X)
•
VIN- 70V

5. 1

5. 0

- -...-- r-...

...::r-

r-

'I - t--

F'

9

"

'\

8

5. 0 - b.

'Z1'=-30'C

r--....

1\

t-..::::::: h:- I---

t"-.

~

~·4. 9

\25'C \

80~

T a- 25'C VIN-70V
.

5. 1

Without Heat Sink

~
"0

\

With Heat Sink

"\

1\

\ \

:: 4. 8

r\

t

4. 7

\

4. 7f- Use of 30x30x lrnrn
Heat Sink

\
50

100

150

Output Current

lOUT

zoo

\

250

Fig.7 Output Voltage VS. Output Current(1)

150
lOUT

o. 8

/

Eo. 7
~

5. 0
lOUT

~

~
o

~

f·
.s

2

o. 1

VI II
4.5

5.0

/

~ V VI7

g,

III I

4. 2

0.4

~:> o. 3

J

4. 4

5.5

6.0

/~ I/'

I~

~

6.5

Input Voltage V" (V)

Fig.9 Output Voltage VS. Input Voltage

60
lOUT

so

100

(rnA)

-

5. I

5.03

5.02

;; 5.0 I
~
~ 5.00

lOUT

=

t--

IrnA

0

:: 4.99

!

40
Output Current

Fig.10 Input/Output Voltage- Difference VS.
Output Current

5.04

:;

zo

T a- 2S'C

5.05

t;

,/ 2S'C V
V 1/V V
V V V -30'C
/'

~

7J j
III I

4. 6

Tl-sol/

o. 6

~ 5
o.

I~ornl
~ r/~rnA

~

~ 4. 8

I

~

IrnAJ

~

250

200
(rnA)

Fig. 8 Output Voltage VS. Output Current(2)

T a- 25'C

5. I

100
Output Current

50

(rnA)

-

............. f.....

............

I rnA

~

4.98
4.97
4.96
4.95

I' (V)

4. 9

10

-20

ZO

40

60

80

100

Ambient Temperature Ta (-C)

Input Voltage V

Fig.11 Output Voltage VS. Input Voltage

Fig.12 Output Voltage VS. Ambient Temperature

8-190

VR 5RE Manual

VIN-70V
-

1.5
1.4

,,/

1.2

,,/

1: II
~

.

il

/'

<3 1.0

c

./

§ 0.8

V

:g

l.l ~=1==l==i=:::j:=::j:=+=~

u~ 1.0f---t--t--+--+--+--+---I

L

c

'R 0.9
8

1.41--+-+--1--+-+-----1---1
~ 1.3f--j--t--+--+--+--+---I
~ 1.21--+--1--+--11--+-+-1

,,/

:(
,3 1.3
~

1.5,----,_---,_--,_-,--'--r_T
"'a;-=....25"C...."

/'

.~

0.9f--j--t--+--+--+--+---I

~

0.8f--j--j---f---f--t--+--1

0.7

8 0.7f---j--t--+--+--+--+---I

0.6

0.61--+-+--1--+-+-----1---1

0.5

-20
20
40
60
80
Ambient Temperature Ta ('C)

0.5 L---;.-+-~----:~-+.10--711;----:!12

100

Input Voltage V IN (V)

Fig.13 Consumption Current VS.
Ambinet Temperature

Fig.14 Consumption Current VS.
Input Voltege

Ta-25'C
-

0.7

IoJrr=ImA

\

\

8.01--+--+-+--1-----1-+--+--1

f-+--+--- --- ---

~

---,....-- Input Voltage

gj 7.0f---+-+--+--+--t--+-+--+

~
~

\

"'"

\

J

---

'" -

~

6.0

~T=!> mA

..... 5 Of->+t<-+V_>4+<-I--+-t++'l>ot-o-ioutput Voltage

j'

4.01-+--1--+--+-+--+-+-...,
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0

t'-...

Time (ms)
I rnA
rnA

Fig.16 Input Transition Responce (1)

Output Regulated Voltage Vreg (V)

Fig.15 Input/Output Voltege Difference VS.
Output Regulated Voltage
IouT-~mA

~

8.0

>

f--+-+---- --- --- ---r-- -

gj
~

7.0f--+-f--+-+-f--+-f--I

~

I

Input Voltage

6.0f---+-+--+--+--f---+-+--+

i
Q

5.0f->4<-+I/_>4+<-I-+-+++~.......,outPut Voltage

\.

j

4.0f---+-+--+--+--t--+-+--I
O~

I~

I~

2~

2.5

3~

3~

4~

Time (ms)

Fig.17 Input Transition Responce (2)

8-191

VR

5'~E

Manual

• PACKAGE INFORMATION

* SOT-B9 Mini-Power-Mold . Plastic Package
4.5±0.1

...

1 6 +0.15
. -0.2

<:>

- Pin ConfigUration

\

0
+1

1 :GND
2: Yin

i

3: Vout

'" '"
'" '"....

zOO

3 20

w

8'

~

-Mark

O 4 +0.03

CD® :

Code Number
@@ : Lot Number

. -0,02

UNIT:mlJ\

Fig. 18 SOT-89

* TO-92 Plastic Package for Taping Method

* TO-92 Plastic Package

I

5 2MAX

'f'

I

'j

, ,42
' MAX t

I'

t

5.2MAX

[~J

[~]

[~J

[~

'\

I

,,'

42

MAX

:I

I

r~J

19n=n=;:;='l.! ~
O.6 MAX

::

·i

...
~

0,5 MAX

0.5MAX

o
UNIT: mm

Fig.19 TO-92

UNIT:mm

- Pin ConfigtU'ation

Fig. 20

TO~92

1: GND
2: Yin
3: Vout

-Mark

~:

®@@@

8-192

Type Number
Lot Number

VR 5RE Manual

• TAPING SPECIFICATION
* SOT-89 Mini-Power-Mold . Plastic Package
• Tape Dimension and Direction
2 Kinds of Taping Method

(n. T2) are available.
4.0±O.1

o 0

0

0
N

o

+1

!::l

~------------------~~---+--~----~--~~

o~ I
c:;:r===;;=:::;:;===;;r==- C=n=:::::l;;;;~8~.O~±~O.~l;;;;;;;~=;:;= +I-=>

Ill!:::=::!JJJ

u::11=::!JIJUl!:::=::::!IJJ

:; ;
\!: :I =::::::::!I~J __,....:....::.~L-r

T2 Type

Tl Type
Fig.

+1

UNIT:mm

~1

• Reel Dimension
1000 pieces can be contained in one reel.

I

UNIT:mm

Fig. 22

8-193

VR 5RE Manual

* TO-92 Plastic Package
• Tape Dimension and Direction
2 Kinds of Taping Method (RF, RR) are available_

.7±0.2

~~"W
RF Type

UNIT: mm

RR Type
Fig. 23

• Reel Dimension
2000 pieces can be contained in Qne reel.

-j r-
...---0 VOUT

Cl

C2

GND~----~~----~DGND

Cl and C2. When the input wire is long, use capacitor Cl. Capacitor C2 makes the transient of output
load variation smaller.
Keep the wiring as short as possible when putting
capacitor Cl and C2 of 0.1 /.IF to 2.0 /.IF between
regulator terminals and GND terminal.

•

INCREASED VOLTAGE CIRCUIT
The following equation explains the output voltage.

Yin
VI N 0-........<>--4

I-<>....,..-"""f--O VOUT

VOUT = Vreg* (1 + R2/R 1) + Iss. R2

IIss

The RX5RE series use low supply current, so Rl and
R2 can be set high (several hundred k ohms) and
R2

supply current of the whole circuit itself can be kept
low.
RX5RE works with constant current, so the input
voltage scarcely affects supply current of the circuit.
* Vreg: Fixed output voltage of RX5RE series

• DUAL VOLTAGE CIRCUIT
As the figure snows, two RX5RE devices can be
VINo-........o-I

made into a dual power circuit.
The figure shows examples with output of 8V and
5V. R is not needed when the minimum load current
of IC2 is larger than Iss of IC1. Diode 0 protects
ICl when VOUT2 larger than VOUT1.

C2
GND~~--~---+-~~

8-197

I

VR SRE Manual

• CURRENT BOOST CIRCUIT
When an output voltage more above 120 mA is neces-

Tr.lj-_ _ _ _ _ _---,

sary, construct a current boost circuit as shown in
the figure.
VIN

o-~I\N\,-4_-o-I

I-o-.--+--{)VOUT

C2
GND~---~--~--~--~GND

• CURRENT BOOST CIRCUIT with OVER-CURRENT PROTECTION

R2

The figure on the left explains the circuit construction to protect Tr.1 from short output circuit or
lOUT
--+

VIN 0--4--'1/1/\,-_-_-4-_._0--1
Rl

over cu rrent.
By adding Tr.2 and R2 to current boost circuit

VOUT
C2

(above figure), voltage drops to Vbe2 of Tr.2 because
of current through R2 ('> lOUT).

GND~-----------~------t_---~--O

GND

When it drops,

Tr.2 will be on and will supply current to Tr.1 base.
Tr.1 will be off and will limit output current.
The

following

equation

explains

the

operation

current of the overcurrent protection circuit.
lOUT = Vbe/R2

• CONSTANT CURRENT POWER SUPPLY

lOUT
VINo-.....o-I

As the figure shows, the construction can be used as
constant current power supply.

Output current,

lOUT, can be found by the following equation.
lOUT = Vreg/R + Iss
Do not exceed the allowable current.
Vreg: Fixed output voltage of RX5RE series

8-198

§8 Selection Guide

I

8-199

VR 5RE Manual

• SELECTION GUIDE
You can define the output voltage and package of the RX5RE series.
The devices are defined by the following characters.
RX5REXXX

+-

Type number

'--.-'

t

t

t

abc

Meaning

No.

Defines the packaging type
a

E: TO-92
H: Mini power mold (SOT-89)

Defines output voltage (Vout)
b

The range for Vout is 2.0V to 6.0V in units of O.IV,
with an accuracy of ±2.S%.
Defines the packaging method for shipment
A: Taping

(Taping Method, Tl/T2, RF/RR Types)

c

B

Gluing (Gluing is for mini power mold package
as a sample)

C

Electric conductive bagging (for TO-92)

I

8-201

STEP-UP DC/DC CONVERTER
RH5RCseries
Application Manual

I

EA-QI5-8908

8-203

Contents

Features
Application
Block Diagram
Pin Configuration
Pin Description
Absolute Maximum Ratings
Electrical Characteristics
Measurement
Packing
Package Dimension
DC/DC Converter
Principle of Step-up Operation
Operation
Design of the DC/DC Converter
Selection of External Parts
Characteristics
Application Circuit

I

8-205

DC/DC C. 5RC Manual

RH5RC301/302/501/502 are compact step-up DC/DC converter ICs, developed with the CMOS
process technology.

They consist of reference voltage source, error amplifier, control transistor, oscil-

lation circuit, and output voltage setting resistor. As external parts, a coil, a diode, and a capacitor are
available for obtaining a constant output voltage (3V, 5V) higher than the input voltage.
The package is a compact three-terminal mini power mold type .

• Features
• RH5RC301 ...............................
RH5RC302 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

3V output, normal type
3V output, low input voltage type

RH5RC501 ...............................

5V output, normal type

RH5RC502 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

5V output, low input voltage type

• Small invalid current. . . . . . . . . . . . . . . . . . . . . . ..

2.5J.1A (Typ., no step-up, RH5RC301/302)

• Low voltage operation. . . . . . . . . . . . . . . . . . . . . ..

Input voltage Vin ~ 0.9V (RH5RC302/502)

• High efficiency ............................

80% (Typ.)

• High output voltage accuracy .................

±5%

• Small temperature drift of output voltage. . . . . . ..

±50ppm (Typ.)

• Compact package ..........................

Mini pQwer mold (SOT-89)

• Application
Constant voltage source for battery-operated devices.
Constant voltage source for cameras, communications equipment, and videos.
Local regu lator for different operating voltages.

I

8-207

DC/DC C. 5RC Manual

• Block Diagram

Yin

Oscillator

• Pin Description

• Pin Configuration

Pin No.

~
2

3

Function

Name

1

Vss

Ground

2

Out

Voltage Output

3

Lx

Switching pin

• Absolute Maximum Ratings

(Vss=OV)
Symbol

Limit

Unit

Yin

7

V

Vout

7

V

Output Current of Lx pin

ILx

120

mA

Power Dissipation

Pd

300

mW

Operating Temperature

Topr

-20-+70

°c

Storage Temperature

Tstg

-40-+125

°c

Parameter
Input Voltage
Output Voltage

8-208

DC/DC C. 5RC Manual

• Electrical Characteristics

1. RH5RC301
Parameter

(Ta=25°C, Vss=OV)
Symbol

Condition

Min.

Typ·.

Max.

Unit

6

V

Note

Input Voltage

Vin

Starting Voltage

Vst

No Load

1.0

V

1

Holding Voltage

Vhld

No Load

0.6

V

1

Current Consumption

Output Voltage

2.5

6

p.A

Vin = 1.5V

7.5

20

p.A

1

3.15

V

1

Vout

Output Current of Lx pin

ILx

Leakage Current of Lx pin

ILxL

Oscillating Frequency

fose

Duty Ratio of Oscillation

Vin=5V
lin

2.85
VOL =0.4V

40

rnA

60

Of

2

p.A

90

KHz

50

%

2. RH5RC302
Parameter

(Ta=25°C, Vss=OV)
Symbol

Condition

Min.

Typ.

Max.

Unit

2

V

Note

Input Voltage

Vin

Starti ng Voltage

Vst

No Load

0.9

V

1

Holding Voltage

Vhld

No Load

0.5

V

1

Current Consumption

Output Voltage

Vin =5V

2.5

6

p.A

Vin = 1.5V

7.5

20

p.A

1

3.15

V

1

lin

Vout

Output Current of Lx pin

ILx

Leakage Current of Lx pin

ILxL

Oscillating Frequency

fosc

Duty Ratio of Oscillation

Of

2.85
VOL =0.4V

rnA

40

60
25

8-209

2

jJA

100

KHz
%

2

I

DC/DC C. 5RC Manual

3. RH5RC501

(Ta=25°C, Vss=OV)

Parameter

Symbol

Condition

Min.

Typ.

Max.

Unit

6

V

Note

Input Voltage

Yin

Starting Voltage

Vst

No Load

1.0

V

1

Holding Voltage

Vhld

No Load

0.6

V

1

Current Consumption

Output Voltage

Yin =7V

3.5

9

IlA

Yin =2.4V

12

32

IlA

1

5.25

V

1

lin

4.75

Vout

Output Current of Lx pin

ILx

Leakage Current of Lx pin

ILxL

Oscillating Frequency

fosc

Outy Ratio of Oscillation

Of

VOL =0.4V

mA

60

100

9

IlA

140

KHz

50

%

4. RH5RC502

(Ta=25°C, Vss=OV)

Parameter

Symbol

Condition

Min.

Typ.

Max.

Unit

2

V

Note

Input Voltage

Yin

Starting Voltage

Vst

No Load

0.9

V

1

Holding Voltage

Vhld

No Load

0.5

V

1

Current Consumption

Output Voltage

Yin =7V

3.5

9

IlA

Yin =2.4V

12

32

/JA

1

5.25

V

1

lin

Vout

Output Cu rrent of Lx pin

ILx

Leakage Cu rrent of Lx pin

ILxL

Oscillating Frequency

fosc

Outy Ratio of Oscillation

4.75
VOL =0.4V

mA

60

110
25

Of

2

IlA

150

KHz
%

Note: 1. The above table assumes that L=270j.1H (Sumida Electric Company LTO. CM·5), 0=MA721 (Matsushita
Electronics), and C=33p.F Tantaru Capacitor, or equivalent products are used for external parts.
2. Outy Ratio of (lscillation Of is expressed as follows:
.
Of =

tH
tH + tL

x 100(%)

8-210

2

DC/DC C. 5RC Manual

• Measurement

lout
Out

Lx

Vss

Circuit·1

/

Out 1-............-.......,

Lx

Observation with
oscilloscope

Vss

Circuit·2

1) Starting voltage (circuit·1)
Gradually raise input voltage Vin from 0 V, and find out the point where Vout exceeds Vin (Vin

<

Vout). The voltage at that point is the starting voltage.
2) Operation hold voltage (circuit-1)
While the specified voltage (2.85 V to 3.15 for 301/302) is output, gradually lower the input
voltage and find the point where the output voltage becomes smaller than the specified voltage. The
voltage at that point is the operation hold voltage.
3) Consumption current (circuit-1)
The RH5RC IC uses the input current as the consumption current. So when Vin ~ Vout, rush
current flows at intervals. Rectify it by inserting an L-C configuration line filter, and use the averaged current as the consumption current.
4) Maximum oscillation frequency (circuit-2)
To measure the maximum oscillation freqency, apply power to RH5RC between Out and Vss.
When Vout (voltage applied to the Out terminal) is smaller than the specified voltage, the Lx terminal
outputs oscillation waveforms.

The maximum oscillation frequency is the waveform output from

the Lx terminal when Vout = specified voltage -50 mV.
5) Oscillation duty ratio
Use the duty ratio of the oscillation waveform output from the Lx terminal when the maximum
oscillation frequency is measured.

8-211

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DC/DC C. 5RC Manual

• Packing
1. You can select packing method from Taping and conductive bag.
The devices are defined by the following characters.
RH5RC301A·Tl: Taping
RH5RC301A·T2: Taping
RH5RC301~ Conductive bag (for sample use only)
definition of the packing method.
2. Taping

o

0

0

0

L::JJ L:JJ
T1 type

L::JJ

c::J),---"",--,-

T2 type

• Package Dimension

n

{J]
4 0 . 4 + 0 . 03
.

8-212

-0.05

DC/DC C. 5RC Manual

• DC/DC Converter
RH5RC can be regarded as a DC/DC converter, in that it generates a direct current from another
direct current. DC/DC converters are largely classified into two according to their power supply
conversion type:
Charge-pump type
DC/DC converter {
Switching regulator type
RH5RC is a switching regulator type IC.

The switching regulator type ICs are further classified

into two according to the insulation between the primary and secondary power supplies:
Un insulated type (chopper type)
Switching regulator - [
Insulated type (converter type)
In RH5RC, input and output are separated only by a diode and cannot be isolated electrically. So
the IC is an uninsulated chopper type switching regulator.
Therefore, RH5RC cannot be used as a line-operated type power supply with commercial power
supplies. For input power supply, use batteries or a power supply which has been reduced and rectified by a commercial power transformer.

• Principle of Step-up Operation
Figure 1 shows the basic circuit configuration of the step-up operation of the IC. In that configuration, when the transistor 1 (Tr. 1) is entirely OFF, the output voltage Vout is the value of the input
voltage Vin minus the voltage reduced by coil L and diode D.
When Tr. 1 has been ON for time ton and is suddenly turned off, voltage VL is generated at the
edges of L because of the energy accumulated during the ton period. Therefore, the peak value of
the voltage generated at that time is Vin + VL, and it is stored in the output capacitor C via D. This
generates the step-up output voltage Vout that is equal to or larger than Vin.

D
Vin

Vout

JU1..1

Tr.l

GXD

Figure 1

8-213

c

I

DC/DC C. 5RC Manual

• Operation
1) Control system
Figure 2 shows the control system of RH5RC, which regulates the step-up output voltage Vout,
obtained by the principle explained in the previous section, to generate a constant voltage source.

Power conversion circuit

Input voltage

,---------- -----------------,,
,
:
Chopper
Rectifying rIL...<'---~~_ Stabilized output
:

circuit

I'

~--- ----}---- - -- -- - -- ----- - ---;

,------,

Pulse
generator

~----iVoltage

comparator

~---l

Reference
voltage
source

Figure 2

The volgage is stabilized by detecting the fluctuation of the output by the reference voltage source
and the voltage comparator and operating the pulse generator at intervals. RH5RC consumes less
current than other types, because there is no need to operate the pulse generator constantly.
In general, there are two types of switching regulator control method: pUlse-width modulation (a)
and frequency modulation (b). R H5RC can be regarded as a modified pulse-width modulation type,
since the chopper drive period (ON-time) is constant and the period that the pulse generator is not
operated (OFF-time) is varied according to the input voltage and load.
2) Starting operation
R H5RC does not have a VDD (+ power supply) terminal. The Out terminal is used as the output,
+ power supply, and output voltage detection terminals.
When power is applied, the input voltage is provided to the Out terminal via coil L and diode D.
Once operation is started with the provided power, the IC operates by the step-up voltage generated
by itself. Therefore the step-up voltage is used as the gate drive voltage of the control transistor. This
reduces the MOSFET ON resistance and enables large current drive by a small transistor, which then
enables mounting to a three-terminal mini power mold (SOT-89).
Due to the circuit configuration described above, load applied at power-on increases the forward
voltage VF of the diode, and reduces the actual activation voltage of the IC. So we recommend you
to take measures such as attaching low-power reset function to the load circuit, so that only small
load is applied when power is turned on or the output voltage is lowered.

8-214

DC/DC C. 5RC Manual

When an input power supply having high impedance ZB is used, the starting voltage tends to be
higher than usual. This is because the control transistor switch current I LX and ZB decrease the actual
activation voltage of the IC. The IC is designed to prevent excessive ILX (soft start). but we recommend you to use an input power supply with ZB equal to or smaller than 5n.
3) Steady-state operation
After power is turned on and the output voltage has reached the specified voltage (3 V or 5 V), the
control transistor is switched in frequencies corresponding to the input voltage and load to maintain
a constant output voltage. When no load is applied, the IC needs to step up only the power that it
consumes by itself, so the switching operation is performed with a very low frequency (lower than
10 Hz).
In steady-state operation, when the control transistor has been ON for ton period, switching current
I LX flows from input power supply Vin through coil L. ILX increases proportionally to time, so it is
expressed as follows:

ILX

Vin
- - . ton ................................................................... (1)
Lx

(Lx is the inductance of the coil, and the voltage decrease due to the ON-resistance of the transistor
is ignored.)
For recommended coils (see p.13), the ton period is set inside the IC so that ILX does not exceed
the rated value (120 mA). Always check the ILX value according to the operation conditions.

• Design of the DC/DC Converter
1) Output current

In the circuit configuration of RH5RC, output is obtained by accumulating energy in the coil while
the control transistor is ON and superimposing it on the input power supply while the control transistor is OFF.
The electric power Pon accumulated in the coil when the control transistor is switched once is
expressed as follows:

Pon =

f 0ton

Vin 2
Lx

tdt ...................................................... (2)

(ton is the ON-time of the control transistor, Vin is the input voltage, and Lx is the coil inductance.)

8-215

I

DC/DC C. 5RC Manual

RH5RC uses the OFF·time control method, in which the ton time is constant and a pulse is sent
when the output voltage becomes smaller than the specified value VT (= Vout). Therefore, when the
load is heavy or the input voltage is low, switching is performed fosc (maximum oscillation frequency)
times at maximum. The power PL accumulated in the coil at that time is expressed as follows:
PL = Pon . fosc .......................................................................... (3)
At that time, the following relationship is established in RH5RC301 and 501:

ton = toff = 2. fosc

..................................... ,....................... (4)

And the following relationship is established in RH5RC302 and 502:

ton = 3 . toff =

3
---=-4· fosc

.......................................................... (5)

From expressions (1) to (5), the maximum output current lout in a design of DC/DC converter
using RH5RC is as follows:
For RH5RC301 and 501:
PL
lout = (Vout-Vin)

............................................................... (6)

8·fosc· Lx ·(Vout-Vin)

............................................... (7)

For RH5RC302 and 502:
9· Vin 2
lout = 32·fosc·Lx ·(Vout-Vin)

............................................ . (8)

Due to such matters as efficiency, the actual output voltage will be 50% to 80% of the results of
expressions (6) and (8).
Therefore, to increase the output current, the inductance Lx of the coil must be smaller. However,
if the inductance is too small, the I LX value will exceed the ratings as described in the previous section,
Operation description-3) Rated operation. In general, the appropriate inductance is:
Lx = 82 - 270SLH ..................................................................... (9)

8-216

DC/DC C. 5RC Manual

2) Ripple characteristics
Ripples that appear in the output of a DC/DC converter using RH5RC are classified into four:
(1) Ripples due to coil switching.
(2) Ripples due to fluctuation of the voltage accumulated in output capacitor C.
(3) Ripples due to the characteristics of output capacitor C.
(4) Ripples due to wiring.

The ripples of (1) occur at the moment the control transistor is turned off. The frequency spectrum spreads very widely (over several MHz) and the amplitude is several tens of mV. The main cause
is the floating capacity on the Lx terminal and the turn·on time of the diode. Place the Lx terminal,
coil and diode as close together as possible, and use a diode with short turn-on time. The ripples can
also be reduced by inserting a capacitor of several tens of pF between the anode and cathode (see
Figure 3).
The ripples of (2) are the disadvantage of the off-time control method used by RH5RC. They are
caused because even under small load, the same potential as that for the maximum load is applied to
the output capacitor at every switching. So use a coil with as large an inductance as possible within
the desired range of the output current capacity.
The ripples can also be reduced by increasing the capacity of the output capacitor. This is easy to
see since the ripple Vp is expressed as follows:

Vp=

J+

iDdt ..............................................................•... (,.0)

(iD is the current flowing in the diode.)
Ripples of (3) are caused by equivalent resistance and frequency response of the output capacitor.
The capacitor impedance Zc is expressed as follows:

Zc

1
wC

= R + w L + - - .............................................................. (11)

Zc causes ripples in combination with the charged current.

Against this type of ripple, insert a

capacitor of about O.lpF in parallel with output capacitor C (see Figure 3).
Ripples of (4) are caused mainly by the routing of the power supply grounding. The grounding
must be one-point and routed as short as possible to avoid any excessive impedance (especially Rand
L elements) (see Figure 3).

8-217

I

DC/DC C. SRC Manual

Vin _ _--J

Reduce floating capacity.

r---

Vout

r

.1..

I

I
I

GND
Wire as short as possible.
Figure 3

3) Efficiency
There are two major causes to degrade the efficiency in a DC/DC converter using RH5RC:
(1) Power loss in diode
(2) Power loSs in control transistor

Loss of (1) Pd is expressed as follows:
Pd = Vf· lout ........................................................................... (12)
To improve the efficiency, use a diode with a small Vf value.
Loss of (2) PT is expressed as follows from equation (1):
Pt= ILx • RT ............................................................................ (13)
Vin
Lx

. ton· RT ............................................................. (14)

(RT is the ON-resistance of the control transistor.)
To improve the efficiency, use a coil with a large Lx value.

8-218

DC/DC C. 5RC Manual

• Selection of External Parts
1) Coil
To select choke coils, consider the following points:
• The core must not be saturated magnetically.
• There must be a sufficient margin of the rated current.
• DC resistance must be sufficiently low.
• The allowable loss must be sufficiently large.
For RH5RC, the following coils are recommended:
• CMD-6L (Sumida Electric Company Ltd., Model 6303-014, 015, 016,017)
• CM-5 (Sumida Electric Company Ltd., Model 6301-064, 065, 066)
• CP-4LBM (Sumida Electric Company Ltd., Model 5201-053,055,066)
2) Diode
To select diodes, consider the following points:
• The forward voltage must be small.
• The turn-on time must be short.
• There must be a sufficient margin of the rated current.
In general, a schottky diode is suitable.
reverse current at a high temperature.

Be careful, because some of them may have increased

3) Capacitor
To select capacitors, consider the following points:
• The capacity must be comparatively large.
• The equivalent resistance must be small.
In general, tantalum (aluminum) electrolytic capacitors and layered ceramic capacitors are suitable.

I

8-219

DC/DC C. 5RC Manual

• Characteristics

1) Output Voltage VS. Input Voltage (Ta

= 25°C)
(2) RH5RC302

III RH5RC301

L=82tLH(CM-5), D=MA721

L=82tLH(CM-5), D=MA721

€ 3. 0 f-------b---II,.j.,I{--~+_-+---1

H

~
;

~

2.0

3. 0 f--~'--r'+--+-~

1,1,

II
I

€
'"

/"--1'
---....
/'"-Jf..- -......lout=lmA_~_ _--i

~

!--...... : ~:~ - - + - - i

~

I II -. .

;

2.0

I--t--++cl

II
1.0

3.0

2.0

1.0
Input Voltage (V)

Input Voltage (V)

L=120tLH(CM-5), D=MA721

L=120tLH(CM-5), D=MA721

1,1,

'"

~
;

0..

;

o

2.0

€

~-......I I
~lout=lmA
,/ ,/~, -.......:
=3mA
=5mA
1.0

~
"[ 2.0 1---+--++-+-",,+

3.0

2.0

I~I

1.0

=5mA

1.0

2.0

Input Voltage (V)

L= 270tLH (CM-5), D=MA721

€

rI
I

lout= lmA
= 3mA

8

L=270tLH(CM-5), D=MA721

I

3.0 f--~+-r"J+--+-~

-><;;

Input Voltage (V)

I

2.0

3.0 f--t...-,p.,.--I--""'1

~

-...... lout= 1mA
'=3mA

'--...

-

2.0 1--_+----,I-'II-...,,-lout=lmA

0..

=3mA

0;

=5mA

2 . .0

~;

3.0

Input Voltage (V)

8-220

=5mA

1.0
Input Voltage (V)

2.0

DC/DC C. 5RC Manual

(3) RH5RC501

(4) RH5RC502

L=82tlH(CM-5), D=MA721

L f
I N

€

r

1 I

L=82tlH(CM-5J. D= MA72!

I-S

t'----
out= 1rnA
t'----

1.0

'S 4 . 0 1-_--I---...j~IoI.:,--lout = 1rnA

=3mA

=2mA
=SmA

O

=5mA

2.0

5.01---+__-i-.......+-.......j

3.0

1.0

Input Voltage (V)

L=120tlH(CM-5), D=MA721

€

5.0

L=120tlH(CM-5), D=!20 tlH

€

II

J

.

1 1

'"
I'-...

~

'[ 4. 0 I--+-I---I-H~

:3

=SmA

2.0

1.0"

5.0 I---+---,......j....,,.....,..j.-.......j

~

~ ~lout=lmA
=3mA

I

1.0

3.0

Input Voltage (V)

L=270tlH(CM-5), D=MA721

€

r-- ~ I 7
1.0

5.0

2.0

=3mA
=5mA

3.0

J

"i t---~Iout=
I

'-

1.0
Input Voltage (V)

Input Voltage (V)

8-221

I

I

J

~ ~lout=lmA

I It:

2.0

Input Voltage (V)

L= 270tlH (CM-5), D=MA721

I

2.0

Input Voltage (V)

lmA
= 3mA
SmA

I

2.0

DC/DC C. 5RC Manual

2") Output Voltage VS. Output Current (Ta = 25°C)
(1) RH5RC301, 302
L=120t'H(CM-5). D=MA721

"'~-\

-301

"

\,

'1\
\

1\

\
Vin=O.9V \

ViT1.y

5.0

- - - 302

\
\
\

\

Yin (ZV

Vir-lf

15.0

10.0
Output Current (rnA)

(2) RH5RC501, 502
L=82t'H(CM-5), D=MA721

\

\

r\

\

\

\

\

'.
\

Vjn=2.4V

1

- - - 502

'\

\
\,

\

\

-501

\ Vin= l.BV

Vin,1. 5

10.0

20.0
Output Current (rnA)

30.0

3) Efficiency VS, Input Voltage (Ta = 25°C)
(1) RH5RC301

(2) RH5RC302

D=MA721. Iout=3rnA

80

..

D=MA721, Iout=3rnA

80

II

L=Z70.uH .......

I- =l20,uH

/

,.".

:=Z70.uH0

K.

........ ...-

-,

= lZO.uH /

1.0

t--...

2.0

1.0

Input Voltage (V)

Input Voltage (V)

8-222

2.0

DC/DC C. 5RC Manual

(3) RH5RC501

(4) RH5RC502

L= 120,..H (CM-5). D= MA721. Iout= 1rnA

80

L= 120,..H(CM-5). D=MA721. Iout= I rnA

80

~ ~ i/
I--- L =120,uH

T 82,uH

1.0

~

V/
1/

~

3.0

2.0
Input Voltage (V)

1I--"

L= 120,uH
= 82,uH

7
1/

f7

1.0
Input Voltage (V)

2.0

4) Operation Start Voltage VS. Output Current (resistance load) (Ta = 25°C)

RH5RC301. 302

(1)

L= 120,..H (CM-5). D= MA721

~
~

l.2

~~

~

V

t::

£1

l.0

§
+:I

f

""''"

0

V

/

--

-

~

fo-'

302 I,.....-- ~ I--"

,/

/f7
0.8

3.0

2.0

1.0
Output Current (rnA)

(2) RH5RC501. 502
L=120,..H(CM-5). D=MA721
l.2

~

1
>

l.0

l/
;7'

V
V

--

~

~

~

5!!.J, ~I - ~

~~

~

l...- ~

.....
l - I--

I

-

"".,

2.0

1.0
Output Current (rnA)

8-223

3.0

DC/DC C. 5RC Manual

(2) RH5RC501. 502
L= 120,uH(CM-5). D=MA721. Iout= ImA. C=33,uF. except spike

9:

s~

200

1
j

~ 100

502
1.0

-

-

i--"':::

501

-

4.0

2.0
3.0
Input Voltage (V)

5) Current Consumption VS. Input Voltage (Ta

~

",

=25°C)

L=120,uH(CM-5). D=MA721. Noload

40
\

<-

30

,5

,

t

I

20

\

Co)

;::

"t::

=

Co)

10

,
1\

/3p1. i02

\

/

/5'01. J02

X/

'V

" '"
~

1.0

r----

""- r-....

2.0
3 0
4.0
Input Voltage (V)

5.0

6) Operation Start Voltage VS. Temperature
(1)

RH5RC301. 302
L=120,uH(CM-5). D=MA721. Iout=lmA

- --.........

r- ~ r-

r- r--

-20

o

~

-r-

r-- r-

r--

30
Temperature ("C)

70

8-224

6.0

v
5.0

DC/DC C. 5RC Manual

7) Maximum Oscillating Frequency VS. Temperature

'140

........

,~

~ 120

"""

>.

ii3

g.

J:

gp

100

~

:ao

...........

§

'" "

RH5RC501

.......

u

80

I'...

J

r-....
............

r-.... ~~301
""""-

r-

60

o

-20

--

30
Temperature ('C)

8) Ripple Voltage VS. Input Voltage (Ta
(1)

r-....

70

= 25°C)

RH5RC301, 302
L=120,l1H(CM-5), D=MA721, Iout=lmA. C=33,l1F. Except Spike

-

-

302.L-

I"'"

V

l---

1.0

/

-

2.0
In pu t Voltage (V)

8-225

./
./
301

3.0

I

DC/DC C. 5RC Manual

• Application Circuit
• Step·up DC/DC Converter

Out 1-----41__--.

I

Vss

• Power Switching Circuit

II

Outl-+---;~

Vss

• Step-down DC/DC Converter

I

L....---+-..J\Mr~Lx

Outl--t---..-

• Power Saving Circuit

Out

I

L-.4---PS

8-226

STEP-UP/STEP-DOWN
DC/DC CONVERTER
RF5RD Series
Application Manual

I

EA'::017-8912

8-227

DC/DC C. SRD MANUAL

RF5RD301/501 are compact DC/DC converter ICs developed with the CMOS process technology.
When the input voltage is sufficiently high, they work as series regulators. When the input voltage falls
down, they work as step-up switching regulators.
They consist of a step-up switching regulator circuit and series regulator circuit. The switching regulator circuit consists of the reference voltage source, error amplifier, control transistor, oscillation circuit,
and output voltage setting resistor. The series regulator circuit consists of the reference voltage source
(shared with the switching regulator circuit), error amplifier, output transistor, and output voltage
setting resistor.
As external parts, a coil, a diode, and a capacitor are available for making the output voltage constant
even when the input voltage changes across the output voltage .

• Features
• RF5RD301
RF5RD501

Output voltage 3V (Typ.)
Output voltage 5V (Typ.)

• Low idle current .......................... .

4.01lA (Typ., no step up, RF5RD301)

•
•
•
•

Input voltage Yin ~ 1.2V (no load)
70% (Typ., step up)

Small idle current ......................... .
High efficiency ........................... .
High output voltage accuracy ................ .
Small temperature drift of output voltage ....... .

• Small package ............................ .

±5%
±100ppm (Typ.)
a-pin SOP

• Application
• Constant voltage source for battery~perated devices.
• Constant voltage source for cameras, communication equipment, and videos.
• Local regulator for different operating voltages.

8-229

I

DC/DC C. SRD MANUAL

• Block Diagram

Vsw

Vout

______________________________- J
~----------------~5~--------------------..J
V~

• Pin Description

• Pin Configuration

1: Vout

•

2:NC

• Absolute Maximum Ratings
Parameter

Pin No.

Name

Function

1

Vout

Output Voltage

2,3

NC

No Connection

4

Lx

Switching pin

5

Vss

Ground

6, 7

NC

No Connection

8

Vsw

Step·up Output

(Vss=OV)
Symbol

Limit

Unit

Yin

12

V

Vout

12

V

Output Current of Lx pin

ILx

100

mA

Power Dissipation

Pd

300

mW

Operating Temperature

Topr

-20-+70

°c

Storage Temperature

Tstg

-40-+125

°c

I nput Voltage
Output Voltage

8-230

DC/DC C. 5RD MANUAL

.Electrical Characteristics
• RF5RD301 (3V Output)
Parameter

(Ta=25°C
Svmbol

Condition

Min.

TVp.

Vss=OV)

Max.

Unit

8

V

Input Voltage

Vin

Starting Voltage

Vst

No Load

1.2

V

Holding Voltage

Vhld

No Load

0.8

V

Current Consumption

No Load, Vin = 5V

4

9

IJA

No Load, Vin = 2.4V

7

20

JJA

3.15

V

lin

Output Voltage

Vout

Output Current

lout

Output Current of Lx pin

ILx

Leakage CUrrent of Lx pin

ILXL

Oscillating Frequencv

fosc

2.85
Vin =5V

40

mA

Vin=2.4V

15

mA

Vol =0.4V

mA

40

SO

• RF5RD501 (5V Output)
Parameter

1

IJA

90

KHz

(Ta = 25°C
Svmbol

Condition

Min.

TVp.

Vss = OV)

Max.

Unit

8

V

Input Voltage

Vin

Starting Voltage

Vst

No Load

1.2

V

Holding Voltage

Vhld

No Load

0.8

V

Current Consumption

Output Voltage

Vout

Output Current

lout

Output Current of Lx pin

ILx

Leakage Current of Lx pin

ILxl

Oscillating Frequency

fosc

Note:

No Load, Vin = 7V

S

11

JJA

No Load, Vin = 3.SV

15

40

IJA

5.25

V

lin

4.75
Vin =7V

40

mA

Vin =3.SV

20

mA

Vol =0.4V

SO

100

mA
1

IJA

140

KHz

The above table assumes that L = 120IJH (CMDSL), MA721 diode or equivalent, and C =22JJF are used for
external parts.

8-231

I

DC/DC C. 5RD MANUAL

• Measurement

Vsw

22tLF

Vout
Vout

Circuit-1

f

vsw 1----4t-----,

Lx

Observation with oscilloscope

Vss

Circuit-2

1) Operation start voltage (circuit-1)
Raise input voltage Yin from OV gradually, and find out the point where Vout exceeds Yin.
The input voltage at that point is the operation start voltage.
2) Operation hold voltage (circuit-1)
Keep the output to be the specified voltage (2.85V to 3.15V for 301). Lower the input vol tag"
gradually, and find out the point where the output voltage becomes lower than the specified voltage.
The input voltage at that point is the operation hold voltage.
3)· Consumed current (circuit-1)
For the RF5R 0301 and RF5R0501, the input current is the consumed current. Therefore, rush
current intermittently flows when Yin is equal to or lower than Vout. So rectify the current by, for
example, inserting a line filter of LIC configuration, and use the average current for the consumed
current.
4) Maximum oscillation frequency (circuit-2)
To measure the maximum oscillation frequency, set the power supply for the RF5R0301 and
RF5R0501 to within Vm and Vss. An oscillation waveform is output to the Lx terminal when the
voltage Vm applied to the Vm terminal is lower than the specified voltage. The maximum
oscillation frequency is the waveform ·output from the Lx terminal when Vm = specified voltage
-50mV.

8-232

DC/DC C. 5RD MANUAL

• Package -Dimension

~

+1

f,

C;

~

M

<0

.;

-$-

0.

...>

~

0

O.lSTYP

0.

~gs

O.3TYP

S.O±O.IS

0.-

>r--

"'0
0.0>

....
>r--

~

~

u:

0

(Unit: mm)

I

8-233

DC/DC C. 5RD MANUAL

• Operation
1) Switching between step-up and step-down operations
The RF5RD301 and RF5RD501 perform step-down operation when the input voltage is
sufficiently higher than the specified output voltage, and work as series regulators. They perform
step-up operation when the input voltage is lower than the specified output voltage, and work as
step-up switching regulators + series regulators.
The input voltage Vinu/D that causes switching of the- step-up and step 'Clown operations is:
Vinu/D ,,;; Vm

+ VF

................................ (1)

(Vm is the specified step-up output voltage, VF is the forward voltage of the diode.)
To suit the capacity of the output transistor of the series regulator, Vm is set in the IC chip as:
Vm "'" Vout + O.5(V) ............................... (2)
(Vout is the specified output voltage.)
From (1) and (21. Vinu/D is expressed as follows:
Vinu/D "'" Vout + VF + O.5(V)

....................... (3)

2) Control system

The RF5RD301 and RF5RD501 use the control system shown in Figure 2 to obtain regulated
constant voltage from the output voltage Vout obtained from the step-up and step 'Clown operations
above.
Power converter circuit
r -- -- -- --- --- ----- -- - --- - - --,
I

,,I

Input voltage

Regulated output

Reference
voltage
source

generator

Switching regulator

Series regulator

Figure 2

8-234

DC/DC C. 5RD MANUAL

When Vin is higher than Vinu/D, the RF5RD301 and RF5RD501 perform step-down operation
and the pulse generator does not work. 50 the input voltage goes through the power converter
circuit as is, and is applied to the series regulator. Then the regulated output is obtained.
When Vin is equal to or lower than Vinu/D, the RF5RD301 and RF5RD501 perform step-up
operation and the step-up switching regulator works_ The step-up voltage is applied to the series
regulator and the regulated output is obtained. At that time, the step-up DC/DC converter uses the
reference voltage source and the voltage comparator to detect the amount of fluctuation in the
step-up output, and operates the pulse generator intermittently.

This eliminates the need to

constantly operate the pulse generator, enabling low power consumption in step-up operation as
well as instep-down operation.

3) Operation start
The RF5RD301 and RF5RD501 do not have a Voo terminal (+power supply terminal). The
Vsw terminal is used as the step-up output terminal, +power supply terminal, and step-up output
voltage detection terminal.
At power on, the input voltage is applied to the Vsw terminal via coil L and diode 0, and the
IC starts operation.
When Vin is equal to or smaller than Vin U/D, the IC starts operation as a step-up switching
regulator. If a heavy load is applied to the output terminal at power on, the forward voltage VF of
diode 0 increases and causes lowering of the actual activation voltage of the IC. 50 take some
measure to lower the load at power on and at low output voltage, for example by attaching the low
voltage reset (low power) function.
When an input power supply with high power supply impedance ZB is used, the operation start
voltage tends to be higher than usual. This is because the voltage is lowered by the switch current
I Lx and ZB of the control transistor, and as a result the actual activation voltage of the IC is lowered. RF5RD301 and RF5RD501 are designed so that ILx does not become excessive at power on
(soft start), but it is recommended to use an input power supply with ZB lower than 5 n.

4)

5teady-state operation
After the IC starts operation and the output voltage reaches the specified voltage, the output
voltage is kept constant even when the input voltage sharply fluctuates across the specified output
voltage. This is enabled by the comparatively fast step-up/down switching and the filtering effect
of the externally attached Land C.
In the RF5RD301 and RF5RD501, the series regulator also works as a ripple filter in step-up
operation. This suppresses the ripples generated by the step-up switching regulator, and constantly
offers low-ripple output.

I

DC/DC C. 5RD MANUAL

• DC/DC Converter design
1) Output current
In designing a DC/DC converter using the RF5RD301 and RF5RD501, the output current lout
generally depends on the output current of the series regulator in step-down operation, and depends
on the capability of the step-up switching regulator in step-up operation.
( Step-down >
In a series regulator of CMOS configuration, the output current loutR is generally expressed as:
lout = loutR = Kp· (Input/Output Voltage Difference) •••.. (4)
(KP is the conduction coefficient of the output transistor.)
In the RF5RD301 and RF5RD501, the input voltage ofthe series regulator is supplied via diode
D, so lout is expressed as:
lout = KP,(Vin-VF-Vout) ......................... (5)
(Step-up>
In step-up operation, the difference in the I/O voltages of the series regulator is fixed to about
0.5V. Therefore,lautR is expressed as:
lautR = 0.5 'KP ............................•..... , (6)
The output current lau1S of the step-up switching regulator is expressed as:
lau1S = K

Vin 2
8 'fosc 'Lx • (Vout +0.5-Vin)

. . . . . . . . . . . . ..

(7)

(Lx is the inductance of the coil used, K=0.5 to 0.8.)
Therefore, the output current of lout of the switching regulator is limited by the smaller of
expressions (6) and (7) (see the section below, the output current of the step-up switching regulator).
When Vin is comparatively high and (Vaut - Vin) is small, lautR &; lou1S. In other cases, lautR ~
lau1S.

- The output current of the step-up switching regulatorThe step-up switching regulator incorporated in the RF5RD301 and RF5RD501 has a
circuit configuration that stores energy in the coil when the control transistor is on and takes
-out the output by superimposing the energy to the input power supply when the control
transistor is off.

8-236

DC/DC C. 5RD MANUAL

When the control transistor switches once, the power PON stored in the coil is expressed as:
rtorVin
PON =)0
tdt

Lx

................................ (8)

(ton is the on-time of the control transistor, Vin is the input voltage, and Lx is the
Inductance of the coil.)
This circuit uses the off-time control method. The ton is fixed, and pulses are sent when
the step-up output voltage becomes lower than the specified value Vsw (= Vout +0.5 ).
Therefore, when the load is heavy or input voltage is low, the transistor switches fosc
(maximum oscillation frequency) times at maximum. At that time, the power PL stored in
the coil is expressed as:
PL = PON 'fosc

. . . • • . . . . . . . • . . . . • . . . • . . . . • . . . . . • . . (9)

At that time, the following relationship is established:

1
ton = toff = - - ............................... (10)

2 'fosc

Thus, the maximum output current obtained by the step~up switching regulator is:
louts =

8

• fosc • Lx •

Vin 2
(V

out

+ 05
. - V.)
In

................ (11)

In actual operation, the output current will be 50% to 80% of expression (11), due to such
factors as efficiency.
As indicated above, the inductance value Lx of the coil must be small to increase the stepup output current. However, if the Lx value is too small, I Lx may exceed the rated value
(120mA) since the I Lx is expressed as follows:
Vin
ILx = - - ·ton
Lx

..................................(12)

(Voltage lowered by the on-resistance of the transistor is ignored.)
Be carefu I of the I Lx value.
Generally, the appropriate value is:
Lx = 82 -4701lH ................................. (13)

8-237

I

DC/DC C. 5RD MANUAL

2) Efficiency characteristics
There are three factors that worsen the efficiency characteristics of the DC/DC converter using
the RFSRD301 or RFSRDS01:
(1) Power loss in the series regulator
(2) Power loss in the diode

(3) Power loss in the control transistor
In step-down operation, the step-up switching regulator is not operating. So the worsening
factors are (1) and (2).
In the RFSRD301 and RFSRDS01, the power consumption of the IC itself is very small. If it
is ignored, the efficiency 7/D in step-down operation is:
7/0 =

Vout
Vin + VF

.................................. (14)

In step-up operation, the step-up switching regulator is operating. So all of (1), (2), and (3)
are worsening factors. Efficiency 7/R due to loss (1) is:
7/R =

Vout
Vout + O.S

................................(1S)

Loss of (2) PO is:
PO = VF • lout ................................... (16)
Loss of (3) PT is expressed as follows with the on-resistance of the control transistor as RT:
Vin
PT = - - . ton' RT .............................. (17)
Lx
Therefore, the efficiency 7/U of the DC/DC converter in step-up operation is:
7/U =

1-(PD+PT)

Vout

Vin • lout

Vout + O.S

.................. (18)

8-238

DC/DC C. 5RD MANUAL

• Selecting external parts
1) Coil
In selecting the choke coil, the following should be satisfied:
• The core does not suffer magnetic saturation.
• There is a sufficient margin in the rated current.
• DC resistance is sufficiently low.
• Allowable loss is sufficiently large.
The following coils are recommended:
• CMD-6L (Sumida Electric Company Ltd., Model 6303-014,015,016 and 017)
• CM-5 (Sumida Electric Company Ltd., Model 6301-064,065 and 066)
• CP-4LBM (Sumida Electric Company Ltd., Model 5201-053,055,066)
2) Diode
In selecting the diode, the following should be satisfied:
• The forward voltage is low.
• The turn-on time is short.
• There is a sufficient margin in the rated current.
Generally, Schottoky diodes are appropriate. Some, however, may increase the reverse current
at high temperature.
3) Capacitor
In selecting capacitors, consider the following:
• The capacity "is relatively large.
• The equivalent resistance is small.
Generally, tantalum (aluminum) electrolytic capacitors and laminated ceramic capacitors are
appropriate.

8-239

I

DC/DC C. 5RD MANUAL

• Characteristics
1) Output Voltage VS. Input Voltage (Ta=25°C)

(1)RF5RD301
L=82tlH(CM-5)

L J If!

~

I
o

I

't rr:. ::::::::
-- r---I

11--

2.0

1.0

D=MA721

---

r-Iout= 5mA
=lOmA
=15mA
t-- =20mA

4.0

3.0

5.0

6.0

7.0

8.0

6.0

7.0

8.0

6.0

7.0

8.0

Input Voltage (V)

L=120tlH(CM-5)

€

rIiU

3.0

.t

D=MA721

V II It1----=
r--.-

'0

>

=:; 2.0

g

II~

I

o

1.0

2.0

::::::'Iout= 5mA
=lOmA
-........... .......
= 15mA
=20mA

4.0

3.0

5.0

Input Voltage (V)

L=270tlH(CM-5)

Jf:::::
fF
t--.

j--f&
I

r-...

/ II
o

1.0

2.0

r--

D=MA721

lout = 5mA
=lOmA
= 15mA
=20mA

4.0

3.0

Input Voltage (V)

8-240

5.0

DC/DC C. 5RD MANUAL

(2) RFSRDSOI
L=82.aH(CM-S)
~

s.o

JI-

1

/
I

=:; 4.0
go

c5
o

1.0

~

I ;{

11-

--

- lout

J

I I /-13.0

2.0

D=MA721

SmA
=lOmA
=lSmA
=20mA

4.0

6.0

S.O

7.0

8.0

7.0

8.0

Input Voltage (V)

L=120.aH(CM-S)

f ~ If-J V r t= r;t
t--

I

o

1.0

2.0

I

II--I'--

--

D=MA721

Iout= SmA
=lOmA
=lSmA
=20mA

4.0

3.0

6.0

S.O

Input V<:'itage (V)

L=270.aH(CM-S)

LJ / I
t /... L -I
V
/
-

1

I

=:; 4.0

g

1

-lout

I

'-

o

1.0

2.0

4;0

3.0

Input Voltage (V)

8-241

I

D=MA721

S.O

SmA
=lOmA
=lSmA
=20mA

6.0

7.0

8.0

DC/DC C. 5RD MANUAL

2) Output Voltage VS. Output Current (Ta=25°C)
(1)

RF5RD301
Lx=120pH(CM-5)

1\

D=MA721

r - r-r-

"'- .......

'"

~

.

\

im=rv

o

5.0

Vin=2.0V-=:

.......

..........

vr=rv
15 .. 0

10.0
Output Current (rnA)

(1)

RF5RD501
Lx=120pH(CM-5)

"

"-

D=MA721

--.r-

rr- r-

~n

3.6V

r-r-

Vin=3.0V r-- r-

""t'
v1m=lov

o

30.0

20.0

10.0

Output Current (rnA)

3) Efficiency VS. Input Voltage (Ta=25°C)
(1)

RF5RD301
Iout=5mA Lx=120pH D=MA721

80

/

.f

!8 70

/\
\

r- ~

~

o

1.0

2.0

\
\

3.0

4.0

\
5.0

Output Voltage (V)

8-242

6.0

7.0

8.0

DC/DC C. 5RD MANUAL

(2) RF5RD501
Iout=5mA Lx=120tlH D=MA721

-

80

"-

i'. ,
"

o

1.0

2.0

3.0

4.0
5.0
Input Voltage (V)

6.0

'" "

7.0

8.0

4) Start Voltage VS. Output Current (with Load) (Ta=25°C)
Lx=120tlH D=MA721

.."

/

/'

......
".. V

---

:.--

-

RF5RD301, 501

I

If

o

1.0
Output Current (rnA)

'2.0

5) Start Voltage VS. Temperature
Lx=270tlH D=MA721 Iout=lmA

..........

--

RF5RD30L 501

r- ..........

1.2

-20

o

-- --

20
40
Temperature fC)

8-243

r-

60

I

DC/DC C. 5RD MANUAL

6) Consumed Current VS. Input Voltage (Ta=25°C)
Lx= 120.uH

40

~

D= MA721

1\

30

\
\.

\

'5

\

\

~ 20
!3

I\.

'\

1\

1

'\..501

'"

~01

u

10

"-t--....
o

1.0

2.0

3.0

...........

............

4.0
Input Voltage (V)

7) Maximum Oscillation Frequency VS. Temperature

140

"'- ......

r-.... I'-....

,-.. 120

~

501 j'-..... .............

~
g. 100
J:
!3

...........

'l:l

~

80

·:::!!1

60

(without Load)

-20

............

........

o

r-.....

---r--

~ r--......

20

...... j'-.....

40

60

Temperature rC)

8-244

5.0

6.0

7.0

8.0

Ie

ICD©®OD

RICOH COMPANY, LTD.
ELECTRONIC DEVICES DIVISION
. HEAD QUARTERS
13- 1, HIMEMURO·CHO, IKEDA·SHI , OSAKA 'f563 JAPAN
PHONE 0727(53) 1111 FAX 0727(53) 8522
. TOKYO OFFICE
1-15-5, MINAMIAOYAMA, MINATO·KU, TOKYO 'f 107 -:JAPAN
PHONE 03(3479)3111 FAX 03 ( 3479) 3037

RICOH CORPORATION
ELECTRONIC DEVICES DIVISION
. SAN JOSE OFFICE
3001 ORCHARD PARKWAY SAN JOSE, CA. 95134 - 2088 USA
PHONE 408-432-8800 FAX 408-432-8375



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