1993_TI_Data_Transmission_Circuits_Data_Book 1993 TI Data Transmission Circuits Book
User Manual: 1993_TI_Data_Transmission_Circuits_Data_Book
Open the PDF directly: View PDF 
.
Page Count: 1282
| Download | |
| Open PDF In Browser | View PDF |
~TEXAS
INSTRUMENTS
Data Transmission Circuits
I.ine Drivers, Receivers, Transceivers, UARTs
1993
1993
Linear Products
General Information
..
~~~~~~~~~
Line Drivers, Receivers, Transceivers
Universal Async Receivers/TransmiHers . .
Explanation of Logic Symbols
•
Applicationslll
Mechanical Data
..
Data Transmission Circuits
Data Book
Line Drivers, Receivers, Transceivers, UARTs
IMPORTANT NOTICE
Texas Instruments Incorporated (TI) reserves the right to make changes to its
products or to discontinue any semiconductor product or service without notice,
and advises its customers to obtain the latest version of relevant information to
verify, before placing orders, that the information being relied on is current.
TI warrants performance of its semiconductor productS and related software to
current specifications in accordance with Tl's standard warranty. Testing and
other quality control techniques are utilized to the extent TI deems necessary to
support this warranty. Specific testing of all parameters of each device is not
~ecessarily performed, except those mandated 'by govemment requirements.
Please be aware that TI products are not Intended for use in life-support
appliances, devices, or systems. Use of TI product in such applications requires
the written approval of the appropriate TI officer. Certain applications using
semiconductor devices may involve potential risks of personal injury, property
damage, or loss of IHe. In order to minimize these risks, adequate design and
operating safeguards should be provided by the customer to minimize inherent
or procedural hazards. Inclusion ofTi products in such applications is understood
to be fully at the risk of the customer using TI. devices or systems.
TI assumes no liability for applications asSistance, customer product deSign,
software performance, or infringement of patents or services described herein.
Nor does TI warrant or represent that any license, either express or implied, is
granted under any patent right,' copyright, mask work right, or other intellectual
property right of TI covering OJ relating to any combination, machine, or process
in which such semiconductor products or services might be or are used.
Copyright © 1993, Texas Instruments Incorporated
Printed in the U.S.A.
INTRODUCTION
In the 1993 Data Transmission Circuits Data Book, the Linear Products Division of Texas instruments
presents technical information on various products for electronic media and electronic devices.
The Texas Instruments data transmission circuits represent technologies from classic bipolar through
Advanced Low-Power Schottky (ALS), IMPACTTM, LinBiCMOS™, CMOS, and BiMOS processes. The ALS
and IMPACT oxide-isolated technologies provide the data transmission family with improved speed-power
characteristics. LinBiCMOS technology features a step-function improvement in impedance, speed, power
dissipation, and threshold stability.
This data book provides information on the following types of products:
•
Data line drivers
•
Data line receivers
•
Data line transceivers
• Asynchronous communication elements (UARTs)
The data transmission line drivers, receivers, and transceivers, which support many popular data
transmission standards, can connect electronic devices and systems at high data rates over significant cable
lengths. The UARTs can control the sending and receipt of data through serial asynchronous data links.
Among new products offered by TI in the 1993 Data Transmission Circuits Data Book are numerous
LinBiCMOS circuits for EIA RS-485, EIA-232, and IEEE 802.3 10BaseTdata transmission standardS. New
packaging includes the shrink sman-outline package (SSOP and DB) as well as surface-mount packages for
popular mature products.
The data book is organized for quick location of a data sheet. The sequence is alphanumeric except for the
SN prefixed parts; these data sheets are in base part number order, i.e., SN75ALS176 is located next to the
SN75176B. The alphanumeric index provides a quick method of locating the data sheet for a known part
number and indicates new products in this edition. The selection guide is grouped by industry standard and
includes key features and the standard device footprint of the products in each category. The cross-reference
guide lists other manufacturers' devices with the suggested TI replacement. Ordering information and
mechanical data are in the last section of the data book.
An applications section has been added in this edition of the data book. This section is a reprint of material
developed for the popular Linear Applications seminar series presented around the world. In this section are
answers to the most commonly asked questions regarding data line circuits and applications.
While this data book offers design and speCification data only for data transmission products, complete
technical data for any TI semiconductor product is available from your nearest TI Field Sales Office, local
authorized TI distributor, or by writing directly to:
Texas Instruments Incorporated
LITERATURE RESPONSE CENTER
P.O. Box 809066
DALLAS, TEXAS 75380-9066
or telephone the Texas Instruments Literature Response number: 1-800-477-8924.
We sincerely believe the new 1993 Data Transmission Circuits Data Bookwill be a valuable addition to your
collection of technical literature.
IMPACT and UnBiCMOS are trademarks of Texas Instruments Incorporated.
v
vi
1-1
Contents
Page
Alphanumeric Index ...................................................... 1-3
Selection Guide ........................................................... 1-5
Cross-Reference Guide ................................................... 1-13
C)
CD
::J
CD
;I
-a'
...3
::J
...o-D)
::J
1-2
ALPHANUMERIC INDEX
AM26C31
t
AM26C32
AM26LS31
AM26LS32A ..............
AM26LS33A •.••.••.••••••
AM26S10 ••..••••••••••••
AM26S11 •.•••••.•••••••••
DP8480 •••••.•••••••.•••.
DP8481 •..•••••••••••••••
DS8820A ••••.• ~ • • . • . • • • ••
OS8830 •..•••• ~ . • • • • • • • •.
LT1030C ••.••• f ......... .
LT1039 ••..••••••••••••••
LT1080 •.••.•• tf ......... .
LT1081 ••••••••.•••••••••
MAX232 .•••••••••••..••.
MC1488 •.•.•• ~ .••••.•••.
MC1489 •••••. ~ ••••••••••
MC1489A •••.• ~ .•••.•••••
MC3450
MC3452
MC3453
MC3486
MC3487
MC3550
MC3552
MC3553 •..••• f . . . . . . . . ..
N8T13 •.•.•.•. f . . . . . . . . ..
N8T14 •••••••.••.••••.•••
N8T23 •••.•.•. ~ • • • • • • • . ••
SN55107A
SN55107B
SN55108A
SN55108B
SN55109A
SN55110A
SN55113
SN55114
SN55115
SN55116
SN55121
SN55122
SN55138
SN55173
SN55182
SN55183
SN55188
SN55189
SN55189A .•..••..•••..••.
SN55ALS056
SN55ALS057
SN55ALS160
SN55ALS161
SN55ALS192
:::::f:::::::::
2-3
2-9
2-13
2-21
2-21
2-31
2-31
2-39
2-43
2-695
2-705
2-47
2-53
2-59
2-59
2-71
2-737
2-751
2-751
2-75
2-75
2-83
2-87
2-93
2-75
2-75
2-83
2-259
2-253
2-259
2-171
2-171
2-171
2-171
2-187
2-187
2-197
2-209
2-217
2-227
2-241
2-253
2-317
2-549
2-595
2-705
2-737
2-751
2-751
2-105
2-105
2-413
2-437
2-n3
SN55ALS194 ••••••••••••••
SN55ALS195 ••••••••••••••
SNSSLBC176 •••t ..........
SN65076B •••••••••••••.••
SN65173 •••••••t..........
SN65175 ••••••• t..........
SN65176B ••••••••••••••••
SN65179B ••••.•••••••.•••
SN65ALS172A •• ~ •••••••••
SN65ALS174A •• ~ ••••.••••
SN65ALS176 ••.•••••.•••••
SN65ALS180 .••.•••••..•••
SN65C185 ••••.••••••••.••
SN65C188 .•.••••••••.••••
SN65C189 ••.••• f .........
SN65C189A •.•••••••••.••
SN65C198 ••••••.•••..••••
SN65C1154 ••••• f .........
:~=~~~: :::::~:::::::::
SN65C1406 •.•..•..•••.•••
SN65LBC176 ••. t..........
SN75061 •.•••..•••.•••...
SN75076B ••.•••.•.•.•••••
SN75107A
SN75107B
SN75108A
SN75108B
SN75109A
SN75110A
SN75112
SN75113
SN75114
SN75115
SN75116
SN75117 •.•.•.•.••..•••••,
SN75118
SN75119
SN75121
SN75122
SN75123
SN75124
SN75125
SN75126
SN75127
SN75128
SN75129
SN75130
SN75136
SN75138
SN75140
SN75141
SN75146
SN75150
2-795
2-805
2-839
2-135
2-549
2-5n
2-503
2-567
2-543
2-571
2-527
2-575
2-713
2-743
2-759
2-759
2-829
2-901
:::
2-935
2-839
2-123
2-135
2-171
2-171
2-171
2-171
2-187
2-187
2-187
2-197
2-209
2-217
2-227
2-227
2-227
2-227
2-241
2-253
2-259
2-267
2-273
2-279
2-273
2-291
2-291
2-297
2-311
2-317
2-329
2-329
2-337
2-343
SN75151
SN75153
SN75154
SN75155
SN75157
SN75158
SN75159
SN75160B
SN75161B
SN75162B
SN75163B
SN75164B
SN75172
SN75173
SN75174
SN75175
SN75176A
SN75176B
SN75177B
SN75178B
SN75179A
SN75179B
SN75182
SN75183
SN75186
SN75188
SN75189
SN75189A •••••••••••••.••
SN75207 •••••••.•••••••••
SN75207B
SN751177
SN751178
SN751730
SN75ALS053
SN75ALS056
SN75ALS057
SN75ALS085
SN75ALS121
SN75ALS123
SN75ALS126
SN75ALS130
SN75ALS180
SN75ALS161
SN75ALS162
SN75ALS163
SN75ALS164
SN75ALS165
SN75ALS170
SN75ALS171 ••••••••..••••
SN75ALS172A ••.t. . . . . . . ..
SN75ALS173 ••.•.t. . . . . . . ..
SN75ALS174A ••.t. . . . . . . ..
SN75ALS175 ••••.t. . . . . . . ..
SN75ALS176 •••••••••••.••
2-349
2-349
2-361
2-369
2-379
2-385
2-393
2-405
2-423
2-423
2-459
2-475
2-535
2-549
2-563
2-577
2-593
2-603
2-649
2-849
2-659
2-667
2-595
2-705
2-721
2-737
2-751
2-751
2-851
2-851
2-917
2-917
2-951
2-97
2-105
2-105
2-145
2-247
2-263
2-285
2-303
2-413
2-437
2-449
2-467
2-465
2-495
2-505
2-519
2-543
2-557
2-571
2-587
2-627
tNew devices added to this volume
1ExAS ."
INSIRUMENTS
POST OFFICE BOX 655303 • DALlAS, TEXAS 75265
1-3
ALPHANUMERIC INDEX
.............
......... ....
..............
SN75ALS176A
SN75ALS176B
SN75ALS180
SN75ALS181 ..............
SN75ALS191 ..............
SN75ALS192 ..............
SN75ALS193 ..............
SN75ALS194 ..............
SN75ALS195 ..............
SN75ALS197 ..............
SN75ALSl99
SN75ALS1177
SN75ALS1178
SN75ALS1711 .............
···f········· .
··f······ ....
··f········· .
2-627
2-627
2-875
2-687
2-769
2-773
2-783
2-795
2-805
2-817
2-639
2-825
2-825
2-943
SN75C185 ................
SN75C188 ................
SN75C189 ........... .....
SN75C189A ...............
SN75C198 ................
SN75C1154
SN75C1167
SN75C1168 .......... .....
SN75C1406 •••••
SN75LBC086 •••
SN75LBC176
SN75LBC187
SN75LBC241
SN75LBC976
~
·····f········ .
·····f········ .
f .........
f .........
···f········ .
:::~::::::::
:
... .........
2-713
2-743
2-759
2-759
2-829
2-801
2-$09
2-809
2--s35
2-161
2-839
2-731
2-859
2-865
tNew devices added to this volume
1ExAs ."
INSTRUMENTS
1-4
POST OFFICE BOX 8~ • DALLAS, TEXAS 75265
t
SN75LBC978
SN75LV4735 . .............
SN95176B
TL16C450 ................
TL16C451 "'
TL16C452 ................
TL16C550A
TL16C552
TL3695 ..................
uA9636AC
uA9637AC . ...............
uA9636C .................
uA9639C
·r··········
I
•••••••••••••••
•
3-3
..............
3-27
3-27
···r··········
3-49
10
I
2-887
2-957
2-815
••••••••••••••
•••••••••••••••
••••••••••••••
II
3-79
2-967
2-979
2-985
2-991
2-995
DATA TRANSMISSION CIRCUITS
SELECTION GUIDE
EIARS-485
DRIVERS/RECEIVERS
PER PACKAGE
DRIVER/RECEIVER
tpd (ns)
(mA)
'Z7
'Z7
35
ICC
70
FOOTPRINT
AM26LS32
0/4
27
27
35
70
25/45
MC3486
5.4
13/19
30
11.5/18
SN75176
10/16.5
22/37
1/1
50
60/35
70
22/40
212
3/3
4/0
9/9
13/19
30
22/37
50
35/35
110
22/37
50
35/35
110
13/19
90
22/37
72
22
55
PAGE
NUMBER
SN75ALS173
2·557
SN55173
2·549
SN65173
2·549
SN75173
2·549
SN75ALS175
2·587
SN65175
SN75175
2·5n
2·5n
SN55LBC176
2-639
SN65LBC176
2·639
SN75LBC176
2-639
SN65ALS176
2-627
SN75ALS176
2·627
SN75ALS176A
2-627
SN75ALS176B
2·627
TL3695
2·967
SN75176A
2·593
SN65176B
2-603
SN75176B
2-603
SN95176B
2-615
SN751n
SN751nB
2·649
SN75178
SN75178B
2·649
SN75178
SN75179B
2-667
SN65ALS180
2·675
55
22/35
DEVICE TYPE
SN75ALS180
MC34050
MC34051
SN75ALS170
SN75ALS171
AM26LS31
SN75ALS180
2·675
SN75ALS11n
2·925
SN7511n
2·917
SN75ALS1178
2·925
SN751178
2·917
SN75ALS170
2·505
SN75ALS171
2·519
SN75ALS1711
2·943
SN65ALS172A
2·543
SN75ALS172A
2·543
65
60
SN75172
2·535
22
55
SN75ALS174A
2·571
65
60
SN75174
2·563
SN75LBC976
SN75LBC976
2-865
SN75LBC978
SN75LBC978
2-887
19.6/33
26.4/30.7
45
MC3487
TEXAS,If
INSIRUMENfS
POST OFFICE BOX 656300 • 1lALIJIS, TEXAS 75265
1-0
DATA TRANSMISSION CIRCUITS
SELECTION GUIDE
EIA RS-422A, CCITT v.11
DRIVERSIRECEIVERS
PER PACKAGE
DRIVERIRECEIVER
tpd (n.)
Icc
(mA)
25
0/2
300
FOOTPRINT
SN75157
50
25
65
50
30
14
27
24
22
35
uA9637
uA9639
AM26LS32
35
70
0/4
27
22
27
35
MC3486
35
70
85
13/19
11.5/18
30
10/16.5
1/1
60/35
50
22/37
50
22/35
22/40.
13/1~
25
2/0
SN75176
55
70
PAGE
NUMBER
SN75157
2-379
SN75146
2-337
uA9637A
2-985
uA9639C
2-995
AM26C32
2-9
AM26LS32A
2-21
SN75ALS173
2-557
SN75ALS193
2-783
SN75ALS197
2-817
AM26LS32A
2-21
AM26LS33A
2--21
SN55173
2-549
SN65173
2-549
SN75173
2-549
SN75ALS175
2-587
SN55ALS195
2-805
SN75ALS195
2-805
SN75ALS199
2-839
SN65175
2-577
SN75175
2-577
MC3486
2-87
SN65ALS176
2-527
SN75ALS176
2-527
SN75ALS176A
2-527
SN75ALS176B
2-527,
SN75176A
2-593
TL3695
2-967
SN65176B
2-503,
SN75176B
2-503
SN95176B
2-515
SN75177
SN75177B
2-549
SN75178
SN75178B
2-549
SN75179
SN75179B
2-667
SN65ALS180
2-575
SN75ALSl80
2-575
30
SN75ALS180
50
SN75158
SN75158
2-385
65
SN75159
SN75159
2-393
7
40
15
65
uA9638
TEXAS
..If
INSIRUMENTS
1-8
DEVICE TYPE
POST OFFICE BOX 655303 • OAUAS. TEXAS 75265
, SN75ALS191
2-769
uA9638C
2-991
DATA TRANSMISSION CIRCUITS
SELECTION GUIDE
EIA RS-422A, CCITT v.11 (continued)
DRIVERSlRECEIVERS
PER PACKAGE
2/2
3/3
DRIVERlRECEIVER
lpeI (n8)
12/27
9
22/37
50
35/35
110
12/27
9
22/37
50
35/35
110
13/19
90
22/37
72
13/19
90
12
14
4/0
ICC
(rnA)
FOOTPRINT
MC34050
MC34051
SN75ALS170
SN75ALS171
3
45
AM26LS31
DEVICE TYPE
PAGE
NUMBER
SN65C1167
2-909
SN75C1167
2-909
SN75ALS1177
2-925
SN751177
2-917
SN65C1168
2-909
SN75C1168
2-909
SN75ALS1178
2-925
SN751178
2-917
SN75ALS170
2-505
SN75ALS1711
2-943
SN75ALS171
2-519
AM28C31
2-3
SN55ALS192
2-773
SN75ALS192
2-773
SN65ALS172A
2-543
SN75ALS172A
2-543
22
55
85
60
SN75172
2-535
20
80
AM26LS31
2-13
SN55ALS194
2-795
SN75ALS194
2-795
14
45
22
55
65
60
SN65ALS174A
2-571
SN75ALS174A
2-571
SN75174
2-563
MC3487
2-93
SN75151
SN75151
2-349
SN75153
SN75153
2-349
MC3487
20
30
80
1ExAs ~
INSIRUMENTS
POST OFFICE BOX 85S303 • DALLAS, TEXAS 76265
1-7
DATA TRANSMISSION CIRCUITS
SELECTION GUIDE
EIA/TIA-232
DRIVERSIRECEIVERS
PER. PACKAGE
SUPPLY VOLTAGE(S)
. 5V
MC1489
0/4
1/1
210
212
MC1489
2·751
SN55189
2·751
SN75189
2·751
MC1489A
2·751
SN55189A
2·751
SN75189A
2·751
SN85C189
2·759
SN75C189
2·759
SN85C189A
2·759
SN75C189A
2·759
2-361
SN75154
SN75154
:t5V
SN75155
SN75155
2-389
SN75150
SN75150
2-343
uA9636
uA9636AC
2·979
LT1080
2-59
:t12V
LT1080
5V
LT1039
3/3
MC145408
:t5V
SN75C165
3/5
5V
SN75LBC187
:t9V
MC1488
4/0
:t5V
LT1030
SN75C198
:t12V.5V
4/5
:t5V
5V
SN75188
SN75C1154
MAX241
LT1081
2-59
MAX232
2·71
LT1039
2-53
SN65C1408
2·935
SN75C1408
2·935
SN65C185
2·713
SN75C185
2·713
SN75LBC187
2·731
MC1489
2·737
SN55188
2·737
SN75188
2·737
SN65C188
2·743
SN75C188
2·743
LT1030C
2-47
SN65C198
2-829
SN75C198
2-829
SN75188
2·721
SN65C1154
2·901
SN75C1154
2·901
SN75LBC241
2-859
1ExAs ."
INSIRUMENTS
1-8
PAGE
NUMBER
5Vor12V
MAX232
4/4
DEVICE TYPE
FOOTPRINT
POST OFFICE BOX 856303 • DAI.IAS. TEXAS 76285
DATA TRANSMISSION CIRCUITS
SELECTION GUIDE
miscellaneous standards
STANDARD
DRIVERJRECEIVER
PER PACKAGE
1/1
IEEE 802.3 (Ethemet)
212
4/4
IEEE 896.1 (Futurebus)
SN75061
2-123
SN75ALS085
SN75ALS085
2-145
SN75LBC086
SN75LBC086
2-161
OS3893
SN75ALS053
2-97
SN55ALS057
2-105
SN75ALS057
2-105
SN55ALS056
2-105
SN75ALS056
2-105
OS3897
SN75160
2-423
SN75ALS162
2-449
SN75163B
2-459
SN75ALS163
2-467
SN75164B
2-475
SN75ALS164
2-485
SN75165
SN75ALS165
2-495
N8T24
SN75124
2-267
SN75128
SN75128
2-291
SN75129
SN75129
2-291
SN75123
2-259
SN75ALS123
2-263
N8T23
2-259
SN751730
2-951
SN75126
2-279
N8T23
SN751730
MC3481
4/0
MC3485
0/4
2-413
2-437
2-437
IBM 360/370
EIARS-423
SN75ALS160
SN55ALS161
SN75162B
SN75164
3/3
2-405
2-423
SN75163
2/0
2-413
SN75160B
SN75161B
SN75162
0/8
SN55ALS160
SN75ALS161
SN75161
8/8
0/3
PAGE
NUMBER
SN75061
OS3896
IEEE 488 (GPIB)
DEVICE TYPE
FOOTPRINT
AM26LS32
1ExAs
SN75ALS126
2-285
SN75130
2-297
SN75ALS130
2-303
AM26C32
2-9
AM26LS32A
2-21
AM26LS33A
2-21
,If
INSIRUMENTS
POST OFFICE BOX 865303 • DALLAS. TEXAS 75265
HI
DATA TRANSMISSION CIRCUITS
SELECTION GUIDE
miscellaneous standards (continued)
DRIVER/RECEIVER
PER PACKAGE
STANDARD
AM26LS32
2-549
SN65173
2-549
SN75173
2-549
SN75ALS173
2-557
SN75ALS193
2-763
2-817
2-87
SN55ALS195
2-805
SN75ALS195
2-805
SN65175
2-577
SN75175
2-577
SN75ALS175
2-587
SN75ALS199
2-839
SN75157
2-379
SN75148
2-337
uA9637AC
2-985
uA9639
uA9639C
2-995
uA9636
uA9636AC
2-979
SN75157
uA9637
2/0
SN55173
MC3466
MC3486
0/2
PAGE
NUMBER
SN75ALS197
0/4
EIARS-423
DEVICE TYPE
FOOTPRINT
general purpose
DRIVERS/RECEIVERS
PER PACKAGE
TYPE OF
LINE CIRCUIT
Differential, -15 < V,CM < 15 V
Differential, -3 < VICM < 3 V
DRVA (Rul
RVA (Vth)
1000 mV
FOOTPRINT
DS8820
10mV
SN75107
0/2
Differential, -6 < VICM < 6 V
Differential, -15 < V,CM < 15 V
Single Ended
Adjustable
DS8820A
2-895
SN55182
2-895
SN75207
2-851
SN75207B
2-851
SN55107A
2-171
SN55107B
2-171
SN75107A
2-171
SN75107B·
2-171
2-851
SN75207B
2-851
SN55108A
2-171
SN55108B
2-171
SN75108A
2-171
SN75108B
2-171
SN55115
2-217
SN75115
2-217
SN75140
SN75140
2-329
SN75141
SN75141
2-329
SN75115
1ExAs .."
INSIRUMENTS
1-10
PAGE
NUMBER
SN75207
25mV
1000mV
DEVICE TYPE
POST OFFICE BOX 655303 • DALlAS, TEXAS 75265
DATA TRANSMISSION CIRCUITS
SELECTION GUIDE
general purpose (continued)
DRIVERS/RECEIVERS
PER PACKAGE
0/3
TYPE OF
LINE CIRCUIT
DRVR (RIJI
RVR (Vth)
Single Ended, 600-mV Hysteresis
TTL
ECL to TTL With Latch
0/4
ECL
FOOTPRINT
N8T14
DP8480
MC3450
Differential~ -3 < VICM < 3 V
25mV
MC3452
Differential, Wired-OR
111
300C/200mV
Differential, -15 < VICM < 15 V
SN75116
2-253
N8T14
2-253
DP8480
2-39
MC3450
2-75
MC3550
2-75
MC3452
2-75
MC3552
2-75
SN65076B
2-135
SN7S076B
2-135
SN55116
2-227
2-227
2-227
Differential, -15 < VICM < 15 V
SN75118
SN75118
2-227
Differential, 0 < VICM < 6 V
SN75119
SN75119
2-227
DS8830
2-705
SN55183
2-705
Differential, Voltage Mode
100C
50C
Differential, Current Mode
NA
DS8830
N8T13
Differential, Voltage Mode
Differential, Current Mode
NA
Single Ended, Open Collector
50C
Single Ended
100C
Single Ended, Open Collector
SOC
TEXAS
2-241
SN75121
2-241
SN75ALS121
2-247
N8T13
2-259
SN55109A
2-187
SN75109A
2-187
SN75110
SN75114
10KECL
2-705
SN55121
SN75109
100C
TTL to ECL With Latch
SN75183
SN75109
SN75113
4/4
2-253
SN75122
SN75117
SN75112
4/0
SN55122
SN75116
100 0{1000 mV
Single Ended, Emitter Follower
2/0
PAGE
NUMBER
SN75117
Differential, 0 < VICM < 6 V
2/0
SN75076B
DEVICE TYPE
SN55110A
2-187
SN75110A
2-187
SN75112
2-187
SN55113
2-197
SN75113
2-197
SN55114
2-209
SN75114
2-209
DP8481
DP8481
2-43
MC3453
MC3453
2-83
MC3453
MC3553
2-83
AM26S10
AM26S10
2-31
AM26S11
AM26S11
2-31
N8T26
SN75136
2-311
SN55138
2-317
SN75138
2-317
SN75138
~
INSIRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
1-11
DATA TRANSMISSION CIRCUITS
SELECTION .GUIDE
controllers
DESCRIPTlON
FUNCTION
PRODUCT FEATURES
DEVlCETVPE
PACKAGE
PAGE
NUMBER
FN,N
3-3
UARrt
Single ACE Without FIFO* . Programmable Baud Generation
UARrt
Single ACE With Parallel
Port and Without FIFO*
Programmable Interface Characteristics TL16C451
FN
3-27
UARTt
Dual ACE WRh Parallel
Port and WRhout FIFO:!:
Programmable Interface Characteristics
FN
3-27
FN,N
3-49
UARrt
Single ACE WRh FIFO*
Functfonal Upgrade of the 16C450
tUART - Universal Asxnchronous Receivers/Transmitters
* FIFO - First In Rrst Out
1ExAs
1-12
..If
INSTRUMENTS
POST OFFICE BOX 866303 • DAUAS. TEXAS 75265
TL16C450
TL16C452
TL16C55OA
DATA TRANSMISSION CIRCUITS
CROSS·REFERENCE GUIDE
Texas Instruments makes no warranty as to the information furnished and the buyer assumes all risk in the use
thereof. No liability is assumed for damages resulting from the use of the information contained herein.
Manufacturers are arranged in alphabetical order.
AMD
SUGGESTED
TI
REPLACEMENT
AM26LS31
AM26LS32
AM26LS32A
AM26LS33
AM26S10
AM26S11
26LS31
26LS32
AM26LS31
AM26LS32A
AM26LS32A
AM26LS33A
AM26S10
AM26S11
AM26LS31
AM26LS32A
AT&T
SUGGESTED
TI
REPLACEMENT
41LF
41LG
LINEAR
TECHNOLOGY
LT1030
LT1039
LT1080
LT1081
MAXIM
MAX232
MAX241
MOTOROLA
AM26LS31
AM26LS32
MC1488
MC1489
MC1489A
MC26S10
MC3450
MC3452
MC3453
MC3481
MC3485
AM26LS32A
AM26LS31
SUGGESTED
TI
REPLACEMENT
LT1030C
LT1039
LT1080
LT1081
PAGE
NO.
2-13
2-21
2-21
2-21
2-31
2-31
2-13
2-21
PAGE
NO.
2-21
2-13
PAGE
NO.
2-47
2-53
2-59
2-59
SUGGESTED
TI
REPLACEMENT
PAGE
NO.
MAX232
SN75LBC241
2-71
2--859
SUGGESTED
TI
REPLACEMENT
PAGE
NO.
AM26LS31
AM26LS32A
SN75188
SN75189
SN75189A
AM26S10
MC3450
MC3452
MC3453
SN75126
SN75130
2-13
2-21
2-737
2-751
2-751
2-31
2-75
2-75
2--83
2-279
2-297
TEXAS
,If
INSIRUMENTS
1-13
POST OFFICE BOX 856303 • DAllAS, TEXAS 75266
~--
.--.~
- - - - - - _ .._..-
DATA TRANSMISSION CIRCUITS
CROSS-REFERENCE GUIDE
SUGGESTED
.TI
REPLACEMENT
MOTOROLA
MC3486
MC3487
MC3488A
MC34050
MC34051
MC6880A
MC75107
MC75107
MC75108
MC75108
MC75127
MC75128
MC75129
MC75S110
MC8T26A
SN75172
SN75173
SN75174
SN75175
MC3486
MC3487
uA9636A
SN751177
SN751178
SN75136
SN75107A
SN751 078
SN75108A
SN751 088
SN75127
SN75128
SN75129
SN75110A
SN75136
SN75172
SN75173
SN75174
SN75175
NATIONAL
SEMICONDUCTOR
OM26LS32
OP8480
OP8481
OS1488
OS1489
OS1489A
.OS14C232
OS14C241
OS14C88
OS14C88T
OS14C89A
OS14C89T
OS16F95
OS26C31
DS26C32A
OS26F31
OS26F32
OS26LS31
OS26LS32
OS26LS33
OS26LS33A
OS26S10.
PS26S11
083486
2-87
2-93
2-979
2-917
2-917
2-311
2-171
2-171
2-171
2-171
2-273
2-291
2-291
2-187
2-311
2-535
2-549
2-563
2-5n
SUGGESTED
TI
REPLACEMENT
PAGE
NO.
AM26LS32A
DP8480
DP8481
SN75188
SN75189
SN75189A
MAX232
SN75L8C241
SN75C188
SN65C188
SN65C189A
SN75C189A
SN951768
AM26C31
AM26C32
SN75ALS192
SN75ALS193
AM26LS31
AM26LS32A
AM26LS33A
AM26LS33A
AM26S10
AM26S11
MC3486
2-21
2-39
2--43
2-737
2-751
2-751
2-71
2-859
2-743
2-743
2-759
2-759
2--615
2-3
2-9
TEXAS·'"
1-14
PAGE
NO•
INSIRUMENTS
POST OFFICE BOX 855303 • DALLAS, 1EXAS 75266 .
2-n3
2-763
2-13
2-21
2-21
2-21
2-31
2-31
2-87
DATA TRANSMISSION CIRCUITS
CROSS·REFERENCE GUIDE
NATIONAL
SEMICONDUCTOR
053487
0534F86
0534F87
0535F86
0535F87
083603
083603
083603
083603
083650
083652
083695
083695
083695A
083695A
083697
0836F95
0855107
0855108
0855110A
0855113
0855121
0855122
0855173
0875107
0875107A
0875108
0875108A
0875113
0875114
0875115
0875121
0875123
0875124
0875129
0875150
0875154
08751768
08751768
08751768T
087820A
087830
088820
088830
088830
088832
8UGGESTED
TI
REPLACEMENT
PAGE
NO.
MC3487
8N75AL8195
8N75AL8194
8N55AL8195
8N55AL8194
8N75107A
8N751 078
8N75108A
8N751 088
MC3450
MC3452
8N751768
Tl3695
8N751768
Tl3695
8N751778
8N75AL8176
8N551 078
8N551 088
8N55110A
8N55113
8N55121
8N55122
8N55173
8N75107A
8N751 078
8N75108A
8N751 088
8N75113
8N75114
8N75115
8N75121
8N75123
8N75124
8N75129
8N75150
8N75154
8N751768
Tl3695
8N651768
8N55182
8N55183
088820A
088830
8N75182
8N75183
2-93
2-805
2-795
2-805
2-795
2-171
2-171
2-171
2-171
2-75
2-75
2-603
2-967
2-603
2-967
2-649
2-627
2-171
2-171
2-187
2-197
2-241
2-253
2-549
2-171
2-171
2-171
2-171
2-197
2-209
2-217
2-241
2-259
2-267
2-291
2-343
2-361
2-603
2-967
2-603
2-695
2-705
2-695
2-705
2-695
2-705
1ExAs ."
INSIRUMENTS
POST OFFICE BOX 85530G • DALlAS, TEXAS 75265
1-ts
DATA TRANSMISSION CIRCUITS
CROSS·REFERENCE GUIDE
NATIONAL
SEMICONDUCTOR
OS96110A
OS9614
OS9615
OS96172
OS96173
OS96174
OS96175
OS96177
OS9636A
OS9637A
OS9638
OS9639A
OS96F172
OS96F173
OS96F174
OS96F175
MC145406
uA26LS32
uAE/636A
uA9637A
uA9639
SIGNETICS
AM26LS31
AM26LS32
AM26LS33
MC1488
MC1489
MC1489A
SUGGESTED
TI
REPLACEMENT
PAGE
NO.
SN75110A
SN55114
SN55115
SN75172
SN75173
SN75174
SN75175
SN75177B
uA9636AC
uA9637AC
uA9638C
uA9639C
SN75ALS172A
SN75ALS173
SN75ALS174A
SN75ALS175
SN75C1406
AM26LS32A
uA9636AC
uA9637AC
uA9639C
2-187
2-209
2-217
2-535
2-549
2-563
2-577
SUGGESTED
TI
REPLACEMENT
PAGE
NO.
AM26LS31
AM26LS32A
AM26LS33A
SN75188
MC1489
MC1489A
2-13
2-'-21
2-21
2-737
2-751
2-751
1ExAs . "
1-16
2~49
2-979
2-985
2-991
2-995
2-543
2-557
2-571
2"":58,7
2-935
2-21
2-979
2-985
2-995
INSJRUMENTS
POST OFFICE BOX 655303 • DAUAS, TEXAS 75265
2-1
2-2
AM26C31 C, AM26C31I
QUADRUPLE DIFFERENTIAL LINE DRIVERS
SLlS103B -
•
DECEMBER 1990 - REVISED
Meets EIA Standard RS-422-A and ccrn"
Recommendation V.11
•
Low Power. Icc = 100 JAA Typ
•
Operates From a Single SOV Supply
D OR N PACKAGE
croP VIEW)
Vee
4A
4Y
= tpHL = 7 ns Typ
•
High Speed. tpLH
•
Low Pulse Distortion (tak(p)
•
High Output Impedance In Power-Oft
Conditions
•
Direct Replacement for NaUonal
Semiconductor DS26C31
•
Improved Replacement for AM26LS31
•
ESD Protection Exceeds 2000 V Per
MIL-8TD-883C. Method 3015
4Z
G
= 0.5 ns Typ)
2Y
8
2A
GND
7
8
11
3Z
3Y
3A
FUNCTION TABLE
(each drive.,
INPUT
A
H
L
H
L
X
description
ENABLES
G
OUTPUTS
G
Y
X
H
L
H
L
Z
L
X
H
L
L
L
X
H
L
Z
Z
H
x =Irrelevant
Z = high Impedance (off)
H
H
X
The AM26C31C and AM26C311 are quadruple
complementary-output line drivers designed to
H =high level
meet the requirements of EIA Standard RS-422-A
L= low level
and CCITT V.11. The 3-state outputs have highcurrent capability for driving balanced lines such as twisted-pair or parallel-wire transmission lines, and they
provide a high-impedance state in the power-off condition. The enable function is common to all four drivers and
offers the choice of an active-high or active-low enable input. BiCMOS circuitry reduces power consumption
without sacrificing speed.
The AM26C31C is characterized for operation from O·C to 70·C, and the AM26C31I is characterized for
operation from -40·C to 8S·C.
logiC symbol t
G
G
1A
2A
3A
4A
4
logic diagram (positive logic)
21
G
EN
12 .........
G
1A
r
1
t>
V
V
.........
2
3
8
7
.........
6
.........
10
11
14
13
9
15
!'...
1Y
1Z
2A
2Y
2Z
3A
3Y
3Z
4A
4Y
4Z
1Y
1Z
2Y
2Z
3Y
3Z
4Y
4Z
t This symbol is in accordance with ANSI/IEEE Std 91-1984 and lEe
Publication 617-12.
1ExAs..lf
Copyright@1993, Texas Instruments Incorporated
INSTRUMENTS
POST OFFICE BOX 855303 • DALLAS, TEXAS 75265
2-3
AM26C31 C, AM26C31I
QUADRUPLE DIFFERENTIAL LINE DRIVERS
SL.LS103B -03636, DECEMBER 1990- REVISED JANUARY 1993
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, Vee (see Note 1) .............................................. -0.5 Vto 7V
Input voltage range, VI ...................................................... -0.5 V to Vee + 0.5 V
Output voltage range, Vo ........................................................... -0.5 V to 7 V
Input or output clamp current, 11K or 10K •••..•••..•••••.•..••..•........•...•..•••••.•.•••. ±20 mA
Output current, 10 •.••...•..•..•••..••••••••.•••.••..•..•......•........••..••.•••••••. ± 150 mA
Vee current ............................................................................ 200 mA
GND current ......................................................................... -200 mA
Continuous total power dissipation ..................................... See Dissipation Rating Table
Operating free-air temperature range, TA: AM26C31 C .................................. O°C to 70°C
AM26C31I ................................. -40°C to 85°C
Storage temperature range ....................................................... -65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds ............................... 260°C
NOTE 1: All voltage values, except differential output voltage VOD, are with respect to network ground terminal.
DISSIPATION RATING TABLE
PACKAGE
-0
N
- TA" 25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
TA = 70°C
POWER RATING
TA = S5°C
POWER RATING
950 mW
1150 rnW
7.6 mwrc
9.2 rnwrc
608 mW
736 rnW
494 mW
598 rnW
recommended operating conditions
Supply voltage, VCC
High-level Input voltage, VIH
MIN
NOM
MAX
4.5
5
5.5
2
Low-level Input voltage,' VIL
High-level output current, 1011
Low-level output current, 10L
Operating free-air temperature, TA
2-4
IAM26C31C
I AM26C31 I
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
UNIT
V
V
0.8
V
-20
rnA
20
rnA
0
70
-40
85
°c
AM26C31 C, AM26C31I
QUADRUPLE DIFFERENTIAL LINE DRIVERS
I
SUS103B - 03636, DECEMBER 1990 - REVISED JANUARY 1993
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VOH
High-level output voltage
10 =-20 rnA
VOL
Low-level output voltage
10=20mA
MIN
TYpt
2.4
3.4
0.2
MAX
UNIT
V
0.4
IVODI
Differential output voltage
RL= 100 g
AIVODI
Change in magnitude of differential output voltage*
RL= 100 g
±0.4
V
VOC
Common-mode output voltage
RL= 100 g
3
V
AlVocl
Change In magnitude of common-mode output voltage*
RL=100g
±0.4
II
Input current
VI at VCC, VIH, VIL, or GNO
10(0ff)
Driver output curent wHh power off
lOS
Driver output short-circuit current
10Z
Off-state (high-impedance state) output current
ICC
Quiescent supply current
Ci
Input capacitance
2
VCC=O,
VO=6V
VCC=O,
VO=-0.25V
3.1
V
V
±1
100
-100
-30
V
t.tA
t.tA
-150
rnA
Vo =2.5V
20
VO=0.5V
-20
100
t.tA
t.tA
t.tA
3
rnA
VO=O
10=0,
VI =OVor5V
10=0,
See Note 2
VI = 2.4 V or 0;5 V,
1.5
6
pF
t All typical values are at VCC = 5 V and TA = 25°C.
* AIVODI and AIVocl are the changes in magnitude of VOO and VOC, respectively, that occur when the input is changed from a high level to a
low level.
NOTE 2: Measured per input. Ali other inputs are at 0 Vor 5 V.
switching characteristics, Vee = 5 V, TA = 25°e
PARAMETER
TYP
MAX
7
12
ns
7
12
ns
0.5
4
ns
5
10
ns
Output enable time to high level
10
19
ns
Output enable time to low level
10
19
ns
7
16
ns
7
16
TEST CONDITIONS
tpLH
Propagation delay time, low-to-high-Ievel output
tPHL
Propagation delay time, high-to-Iow-Ievel output
tsk(p)
Pulse skew (ItPLH -tPHLil
tro, tfD
Differential output rise and fali times
tpZH
tpZL
tpHZ
Output disable time from high level
tpLZ
Output disable time from low level
Cpd
Power dissipation capacitance (see Note 3)
See Figures 1 and 2,
See Figures 1 and 4,
See Figures 1 and 3,
No load
51 is open
51 is open
51 is closed
MIN
100
UNIT
ns
pF
NOTE 3: Cpd is used to estimate the switching losses according to Po = Cpd VCC2 f where Po is in watts, Cpd is in farads, VCC is In volts, and
f is in hertz.
TEXAS
,If
INSIRUMENTS
POST OFFICE BOX 655303 • DAUAS, TEXAS 75265
AM26C31 C, AM26C31I
QUADRUPLE DIFFERENTIAL LINE DRIVERS
Su.s1 038 - D3636. DECEMBER 1990 - REVISED JANUARY 1993
PARAMETER MEASUREMENT INFORMATION
SOg
40pF
SOOg
40pF
Input
_----"vll/lr--(J 0-- 1.5 V
50g
40pF
S1
Figure 1. Test Circuit
I
I
I
I
OutputY
tpHL
::
~~~---
Input A --1(1.3 V
(see Note 8) ~
tPLH~
.
.
I
Skew?
~
14
14
I
I
.1
tPHL
\! -:-:-::-
~
I
Skew-J.-.;
I+-
VOL
tpLH ~
)I
'\.1.5
V _ _ _ _..L..
......._
OutputZ
VOH
VOH
VOL
Figure 2. Propagation Delay Times and Skew Waveforms
EnableG ~- (seeNoteC) 1.5V
EnableG I
~
Waveform 1
(see Note D)
-.-
tpZL
.
-- -- --
~
I~
14-
tpZH
tpLZ
--4.5V
~
I 61 Closed
I
I
I
-V
1.5V
l
tpHZ
3V
7.,1.5 V
.1"-- - . - - I,.
.1
I
I
I 61 Closed
I
1-£_.
I
- -'[--I
O.SV
14
·1 0.5 V
\= =} - -
!I:':::'"
Waveform 2
S1 Open
(seeNoteD)_ _ _ _ _ _ _.JF"!:..5:!.. -OV
S1 Closed
OV
-1.5V
VOL
VOH
-1.5 V
Figure 3. Enable and Disable Time Waveforms
NOTES: A.
B.
C.
D.
All Input pulses are supplied by generators having the following characteristics: PRR " 1 MHz. Zo - 50 g. tr " 15.ns. and tf " 6 ns.
When measuring propagation delay times and skew. switch $1 is open.
Each enable is tested separately.
Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2
Is for an output with internal conditions such that the output is high except when disabled by the output control.
TEXAS
~
INSIRUMENTS
2-6
POST OFFICE BOX 655303 • DAUAS. TEXAS 75265
AM26C31 C, AM26C31I
QUADRUPLE DIFFERENTIAL LINE DRIVERS
Sl.LS1 03B - 03636, DECEMBER 1990 - REVISED JANUARY 1993
PARAMETER MEASUREMENT INF,ORMATION
3V-~-Input
'
ov
Output
(differential)
90%~ 90%
~!
!~
I I
~ ~ tro
I I
tro
~
!+-
Figure 4. Differential Output Rise and Fall Times
1ExAs'"
INSIRUMENIS
POST OFFICE BOX 655303 • DALlAS, TEXAS 75265
2-7
AM26C32C, AM26C321
QUADRUPLE DIFFERENTIAL LINE RECEIVERS
1992
SL.LS104B-
•
•
•
Meets EIA Standards R8-422-A, RS-423-A,
and CCITT Recommendation V.11
D, N, OR NSt PACKAGE
(TOP VIEW)
Low Power, ICC = 9 mA lYP
18
1A
:!: 7-V Common-MOde Range With :!:20G-mV
Sensitivity
•
Input Hysteresis ••• 60 mV Typical
•
tpd = 19 ns (Typ)
•
Operates From a Single SOV Supply
•
3-State Outputs
•
Input Fall-Safe Circuitry
•
Improved Replacement for AM26LS32
Vce
48
4A
4Y
G
3Y
3A
38
t The NS package Is available in
left-ended taped and reeled (order
device AM26C32CNSLE).
description
The AM26C32C and AM26C321 are quadruple differential line receivers for balanced and unbalanced digital
data transmission. The enable function is common to all four receivers and offers a choice of active-high or
active-low input. Three-state outputs permit connection directly to a bus-organized system. Fail-safe design
ensures that if the inputs are open, the outputs will always be high.
The AM26C32 is manufactured using a BiCMOS process, which is a combination of bipolar and CMOS
transistors. This process provides the high voltage and current of bipolar with the low power of CMOS to reduce
the power consumption to about one-fifth that of the standard AM26LS32 while still maintaining ac and dc
performance.
The AM26C32C is characterized for operation from O°C to 70°C, and the AM26C321 is characterized from
.
-40 °C to 85°C.
FUNCTION TABLE
(each receiver)
DIFFERENTIAL
ENABLES
OUTPUT
INPUT
G
G
VIO:oVT+
H
X
X
L
H
H
VT-"VIO"VT+
H
X
X
L
?
?
VIO"VT+
H
X
X
L
L
L
X
L
H
Z
H = high level, L =low level, X =Irrelevant
Z =high impedance (off), ? =indeterminate
Copyright © 1992, Texas Instruments Incorporated
TEXAS .."
INSIRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2-9
AM26C32C, AM26C321
QUADRUPLE DIFFERENTIAL LINE RECEIVERS
$LLS1 O4B - 03634. DECEMBER 1990 - REVISED DECEMBER 1992
logic symbol t
logic diagram (positive logic)
G ""4..........c-"'....
G _1 2- u , - - " ,
1A
3
1Y
5
2Y
11
3Y
13
4Y
3
1Y
5
2Y
11
3Y
1B
2A
2B
3A
t This symbol Is in accordance with ANSI/IEEE Std 91-1984 and
3B
IEC Publication 617-12.
4A
4B
EQUIVALENT OF A OR B INPUT
VCC ---~~--.-
EQUIVALENT G OR G INPUT
TYPICAL OF ALL OUTPUTS
VCC--~~----'--
VCC
1.7kO
NOM
-....,V\J\.,......_---t--
Input
288kO
NOM
VCC(A)
__ .-J
or
GND(B)
GND
Output
Input ~'V\f\""""""''IN\r-''
---~H'---'
GND----*--~~~--
- - - <....__..- GND
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) ............................................................. 7 V
Input voltage range, VI: A or B inputs .............................................. -11 V to 14 V
G or G inputs ........................................................ 7 V
Output voltage, Vo .......................................................................... 7 V
Output current, 10 ................................................... .... .. . .. .. .. .. .. ... ±25 rnA
Continuous total power dissipation ..................................... See Dissipation Rating Table
Operating free-air temperature range, TA: AM26C32C .................................. O°C to 70°C
AM26C321 ................................. -40°C to 85°C
Storage temperature range ............•........................................ ~. -65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds ............................... 260°C
NOTE 1: All voltage values, except differential output voltage. VOD. are with respect to network ground terminal. Currents into the device are
positive and currents out of the device are negative.
1ExAs . "
INSIR.UMENTS
2-10
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
AM26C32C, AM26C321
QUADRUPLE DIFFERENTIAL LINE RECEIVERS
SLlS104B-D3634, DECEMBER 1990-REVISED DECEMBER 1992
DISSIPATION RATING TABLE
TA,,25"C
POWER RATING
DERATING FACTOR
ABOVE TA = 25"C
D
950mW
N
1150mW
NS
625mW
PACKAGE
TA=70"C
POWER RATING
TA=85"C
POWER RATING
7.6mW/"C
608rnW
494mW
9.2mW/"C
736mW
598rnW
5.0mW/"C
400rnW
325mW
recommended operating conditions
Supply voltage, VCC
High-level Input voltage, VIH
MIN
NOM
MAX
4.5
5
5.5
UNIT
V
V
2
Low-level Input voltage, VI L
O.B
Common-mode input voltage, VIC
",7
V
High-level output current, IOH
-6
rnA
6
rnA
Low-level output current, IOL
IAM26C32C
Operating free-air temperature, TA
IAM26C321
0
70
-40
85
V
"C
electrical characteristics over recommended ranges of Vee. VIC. and operating free-air
temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VT+
VT-
Differential Input high-threshold voltage
VO=VOHrnin,
IOH = -440 !lA
Differential Input low-threshold voltage
Vo = 0.45 V,
IOL=8mA
Vhvs
Hysteresis (VT+ -
MIN
TVPt
MAX
0.2
-0.2:1:
VT-I
VIK
Enable input clamp voltage
VCC=4.5V,
11=-18mA
High-level output voltage
VID = 200 mV,
IOH=-6mA
VOL
Low-level output voltage
VID = -200 mY,
IOL=6mA
IOZ
Off-state (high-Impedance-state)
output current
Vo = VCC or GND
II
Une input current
V
-1.5
V
0.2
0.3
V
",0.5
",5
t.tA
2.7
V
VI = 10V,
Other inpuf at 0 V
1.5
VI =-10V,
Other Input at 0 V
-2.5
IIH
High-level enable current
VI = 2.7V
20
IlL
Low-level enable current
VI =O.4V
-100
ri
Input resistance
One input to ac ground
ICC
Supply current
VCC=5.5V
V
rnV
60
VOH
UNIT
9
I All outputs enabled
12
t.tA
t.tA
kQ
17
I All outputs disabled
rnA
14
rnA
1ExAs " ,
INSIRUMENTS
POST OFFICE BOX 655303 • DAUAS, TEXAS 75265
2-11
AM26C32C, AM26C321
QUADRUPLE DIFFERENTIAL LINE RECEIVERS
SLLS104B - 03634. DECEMBER 1990- REVISED DECEMBER 1992
switching characteristics over recommended ranges of VCC. VIC. and operating free-air
temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYPT
MAX UNIT
tPLH
Propagation delay time. low-to-high-Ievel output
10
19
30
ns
tpHL
Propagation delay time. high-to-low-Ievel Output
10
19
30
ns
tf
Output fall time
4
9
ns
tr
Output rise time
4
9
ns
tPZH
Output enable time to high level
13
ns
tpZL
Output enable time to low level
13
tpHZ
Output disable time from high level
13
22
22
22
See Figure 1
ns
ns
13
22
ns
Output disable time from low level
tPLZ
t All typical values are at VCC 5 V. TA 25·C. and VIC O.
The algebraic convention. where the less positive (more negative) limit is deSignated as minimum. is used in this data sheet for tiueshold levels
only.
=
*
=
=
PARAMETER MEASUREMENT INFORMATION
Teet Point
From Output
Under Teet
VCC
---'-~__--~r-~
I
(aee Note B)
oV~----2.SV
---.Il
=1 kg
RL
fov
Input
Sl
~
I
I
I
tPLH
--l4--+i
90%
TEST CIRCUIT
____
:~
III
II
III
EnableG l~V
I
N
C)'
(_ote
I 10%
tpzH
I I
l4-
90%*=----
3V
ov
10%
III
II
,90%
~
11
II
EnableG
(see Note C)
III
III
III .
.
III
~9O%3V·
10%
•
3V
L----OV
~
:.
1.3 V
tpHZ ~
VOL
14- tf
-1.4 V
-+;
14- ,,5ns
~----3V
I
1.3VII 10%
ov
III
III
III
3V
90,
I
tpZL
~
_ _~II
-----oV
I.
tpLZ ~
I
Output Sl Closed
Sl Closed
S2Cloaed
1.3 V
Sl Closed
S2Closed
O.SV
~_
_
-1.4 V
S20pen
- - - , VOL
VOLTAGE WAVEFORMS FOR tpLZ. tpZL
VOLTAGE WAVEFORMS FOR tpHZ. tPZH
NOTES: A CL includes probe and jig capacitance.
B. All diodes are 1N3064 or equivalent.
.
C. Enable G is tested with G high; G Is tested with Glow.
FIgure 1. Test CIrcuIt and Voltage Waveforms
1ExAs
2-12
~
VOH
90%~
~
1.3V
10%
10%
1.3V·
EnableG
(_NoteC)
0.5V
1=F~
I I
S10pen
S2 Closed
1•3V
1
--VOH
Output
V
I I
j4- "Sns
~
14-,,5n.
1.3V 11
~
2.S V
VOLTAGE WAVEFORMS FOR tpLH. tpHL
,,5n. --.;
~i! 1.3V
90% "X..~
1.3
It--
tr~
EnableG
(aeeNoteC)
-
1 3 V Jl"
.:.:10%=l,:..r1 Sl and S2 Closed!
Output
__
~ ~
•
I+----+j- tpHL
..If
INSlRUMENTS
POST OFFICE BOX 655303 • DALlAS. TEXAS 75265
AM26LS31C
QUAD DIFFERENTIAL LINE DRIVER
SLlS114-
•
•
Meets EIA Standard RS-422-A
JANUARY 1979 - REVISED MAY 1990
D OR N PACKAGE
(TOP VIEW)
Operates From a Single S-V Supply
•
•
•
TTL Compatible
•
Complementary Output Enable Inputs
Vee
4A
Complementary Outputs
4Y
4Z
High Output Impedance In Power-Off
Conditions
G
3Z
3Y
description
The AM26LS31 C is a quad complementaryoutput line driver designed to meet the
requirements of EIA Standard RS-422-A Federal
Standard 1020. The 3-state outputs have
high-current capability for driving balanced lines
such as twisted-pair or parallel-wire transmission
lines, and they provide a high-impedance state in
the power-off condition. The enable function is
common to all four drivers and offers the choice of
an active-high or active-low enable input.
Low-power Schottky circuitry reduces power
consumption without sacrificing speed.
FUNCTION TABLE
(each driver)
ENABLES
INPUT
A
G
Y
Z
H
L
H
L
Z
L
H
L
H
Z
H
L
H
L
H
H
X
X
X
X
X
L
L
L
H
H =high level
L = low level
OUTPUTS
G
X =irrelevant
Z = high impedance (011)
The AM26LS31 C is characterized for operation
from O°C to 70·C.
logic symbol t
G
G
1A
logic diagram (positive logic)
,,1
4
12
G
EN
G
'"
1
r
I>
1A
2
'il
3
'il
2A
3A
4A
7
9
15
6
5
10
11
14
13
1Y
1Z
2A
1Y
1Z
2Y
2Z
2Y
2Z
3Y
3A
3Z
3Z
4Y
3Y
4A
4Z
4Y
4Z
t This symbol is in accordance with ANSI/IEEE Std 91-1984 and
lEe Publication 617-12.
Copyrigu@ 1990, Texas Instruments Incorporated
POST OFFICE BOX 655303 • DAlLAS, TEXAS 75265
2-13
AM26LS31C
QUAD DIFFERENTIAL LINE DRIVER
SLLS114-D2433, JANUARY 1979 - REVISED MAY 1990
schematic (each driver)
Input A
r----------~~~~~~~u~=:----
-~
VCC
To Three
Other
Drlvere
EnableG - ......-liIII......- ....HH
I
I
I
GND
___________________________ JII
Enable G --t--:r-~t-tI-J~---"i==:.j
~
All resistor values are nominal.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) .......... , .............. , .................... , ............... 7 V
Input voltage, V, ............................................................................ 7 V
Output offstate voltage ............................... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Continuous total power dissipation ..................................... See Dissipation Rating Table
Operating free-air temperature range, TA .............................................. O·C to 70·C
Storage temperature range ....................................................... -65·C to 150·C
. Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds ............................... 260·C
NOTE 1: All voRage values, except differential output voRage VOD, are with respect to network ground terminal.
DISSIPATION RATING TABLE
PACKAGE
o
N
DERATING FACTOR
ABOVE TA = 25°C
TA 70°C
POWER RATING
950 mW
1150mW
7.6 mwrc
9.2mWrC
608 mW
736mW
1ExAs ."
INSIRUMENTS
2-14
=
TA" 25°C
POWER RATING
POST OFFICE BOX 655303 • DAUAS. 1EXAS 75265
AM26LS31C
QUAD DIFFERENTIAL LINE DRIVER
Su.5114- D2433,JANUARY 1979- REVISED MAY 1990
recommended operating conditions
Supply voltage, Vee
MIN
NOM
MAX
4.75
5
5.25
UNIT
V
V
2
High-level Input voltage, VIH
Low-level input voltage, VIL
High-level output current, 10H
Low-level output current, 10L
Operating free-air temperature, TA
0
0.8
V
-20
mA
20
mA
70
·e
electric..1characteristics over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VIK
Input clamp voltage
Vee = 4.75 V,
11=-18mA
VOH
High-level output voltage
Vee = 4.75 V,
IOH=-20mA
VOL
Low-level output voltage
Vee =4.75 V.
10Z
Off-state (high-Impedance state) output current
Vee = 4.75 V
MIN
TYpt
MAX
-1.5
UNIT
V
V
2.5
0.5
IOL=20mA
I Vo=0.5V
-20
I VO=2.5V
20
V
IIA
II
Input current at maximum Input voltage
Vee = 5.25 V,
VI=7V
0.1
mA
IIH
High-level input current
Vec = 5.25 V,
VI =2.7V
20
IlL
loW-level input current
Vec=5.25V,
VI =0.4V
-0.36
IIA
IIA
lOS
Short-circuit output current*
Vee = 5.25 V
ICC
Supply current
Vee = 5.25 V,
-30
-150
mA
32
80
mA
TYP
MAX
14
20
14
20
1
6
ns
ns
ns
2.5
40
ns
37
45
ns
21
30
23
35
ns
ns
All outputs disabled
t All tyPIcal values are at Vee = 5 V and TA = 25·e.
* Not more than one output should be shorted at a time, and duration of the short circuit should not exceed one second.
switching characteristics, Vee = 5 V, TA = 25°C
PARAMETER
TEST CONDITIONS
tpLH
Propagation delay time, low-to-hlgh-Ievel output
tPHL
Propagation delay time, high-to-Iow-Ievel output
CL=30pF,
See Figure 1
S1 and S2 open,
RL=75C,
Output-to-output skew
tpZH
Output enable time to high level
eL=30pF,
See Figure 1
tpZL
Output enable time to low level
eL=30pF,
See Figure 1
RL=180C,
tpHZ
Output disable time from high level
Output disable time from low level
CL= 10 pF,
See Figure 1
S1 and S2 closed,
tpLZ
MIN
UNIT
.1ExAs'"
INSIRUMENIS
POST OfFICE BOX 655303 • DAllAS, TEXAS 75265
2-15
AM26LS31C
QUAD DIFFERENTIAL LINE DRIVER
Su.s114- 02433. JANUARY 1979- REVISED MAY 1990
PARAMETER MEASUREMENT INFORMATION
Te8tPolnt
Vcc
J'~o
S1
From Output
UndarTeat
CL
(seeNateA)
I
.-J(1.3V
Input A
(aeeNateeB
and C)
750
OV
~ tpLH~
II
OutputY
tpHL
t
Sk8W~
I..
.1
I~
.1
I
I
EVOH
1.6V
TEST CIRCUIT
'+-1
WIIV8I'orm2
(see Note E)
)t
VOH
-
VOL
PROPAGATION DELAY TIMES AND SKEW
EnablaG ~-
Vee=5V
Load = 470 Q to GND
See Note A
Vee = 5.25 V
Vee=5V
3
I
t
~
i
o
I
~
0
0
0
1
2
VI - Enable G Input Voltage - V
0
3
Figure 3
OUTPUT VOLTAGE
OUTPUT VOLTAGE
vs
vs
ENABLE G INPUT VOLTAGE
ENABLE G INPUT VOLTAGE
5
~
Vee=5V
Vee = 4.75 V
4
,
Load = 470 Q to Vee
See Note B
TA=25·e
-
Vee=5V
Load = 470 Q to Vee
See Note B
5
>I
i
3
3
I
2
~
~
4
!i
!
2
o
2
3
o
--
.1
r- ,~
TA=7o·e I
TA=25·e -
~
I\\+-
i- TA=o·e
\\
\ \\
.\.
o
3
6
Vee = 5.25 V
I
2
VI- Enable G Input Voltage - V
Figure 2
6
J
-
2
J
~
f
TA=o·e
TL25"e
~.
2
I
l-
t
I
>I
J
3
>I
Vee = 4.75 V
iA =70·J
o
1
2
3
VI- Enable G Input Voltage - V
VI - Enable G Input Vonage - V
Figure 4
Figure 5
NOTES: A The A input is connected to Vee during the testing of the Y outputs and to ground during testing of the Z outputs.
B. The A input is connected to ground during the testing of the Y outputs and to Vee during the testing of the Z outputs.
1ExAs
~
INSIRUMENTS
POST OFFICE BOX 655303 • DAUAS. TEXAS 75265
2-17
AM26LS31C
QUAD DIFFERENTIAL LINE DRIVER
Su.s114- 02433, JANUARY 1979 - REVISED MAY 1990
TYPICAL CHARACTERISTICS
HIGH-LEVEL OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
HIGH-LEVEL OUTPUT CURRENT
5
,
>I
•
V~C=~.25~
.... ......... ~r--.....
..... .........
I
4
3
......... r--.....
~
.-
t I -'
VCC=5V
......... r-.....,.r--..... ......... V·
....
3
'OH=-2OmA
I
~
r--..... ......... r-.... ::::~
VCC=4.75V
'OH=-4OmA
0
!
4
I
VCC=5V
See Note A
~
1.'S
HIGH-LEVEL OUTPUT VOLTAGE
vs
2
r- . . . . . 1\
,
2
SP
:E:
I
~
TA = 25°C
See Note A
o
0
0
10
20
30
40
50
60
70
TA - Free-Air Temperature _ °C
60
I
o
I
I
-60 . -100
-40
-60
-20
'OH - High-Level Output Current - mA
Figure 6
Figure 7
LOW-LEVEL OUTPUT VOLTAGE
0.5
>I
&
i
i
LOW-LEVEL OUTPUT VOLTAGE
VS
vs
FREE-AIR TEMPERATURE
LOW-LEVEL OUTPUT CURRENT
VCC=5V
IOL=4OmA
See NoteB
I
..J
~
i
0.6
>I
0.4
•
'-
~
0.3
0
)
,
TA=I25o C I
0.9 I- 8eeNoteB
0
~
0.2
~
J
0.8
I
0.7
VCC=~ -:?"
0.5
0.4
~
0
0
25
50
TA - Free-Air Temperature - °C
75
~V
0.2
/"'"
0.1
o
o
100
20
40
60
60
IOL - Low-Level Output Current - mA
Figure 8
Figure 9
NOTES: A The A input Is connected to Vee during the testing of the Y outputs and to ground during testing of the Z outputs.
B. The A Input Is connected to ground during the testing of the Y outputs and to Vee during the testing of the Z inputs.
1ExAs
2-18
V. . . .
h VvCC =5.25V
0.3
I
0.1
I
,If
INSIRUMENTS
POST OFFICE BOX 655303 • OAUAS, TEXAS 75265
120
AM26LS31C
QUAD DIFFERENTIAL LINE DRIVER
SUSl14- D2433, JANUARY 1979- REVISED MAY 1990
TYPICAL CHARACTERISTICS
Y OUTPUT VOLTAGE
Y OUTPUT VOLTAGE
vs
vs
DATA INPUT VOLTAGE
DATA INPUT VOLTAGE
5
5
No Load
TA=25°e
No Load
TA=25°e
4
>I
•
I
4
Vee = 5.25 V
Vee=5V
>
Vee = 4.75 V
i
I
3
~
'!i
Q.
'!i
0
TA=7ooe -
(
3
~
io
2
I
TA=ooe
-
TA=25°e 2
I
-?
-?
o
o
2v
VI- Oma Input Voltage - V
3
o
o
Figure 10
2
VI - Oma Input Voltage - V
3
Figure 11
1ExAs
,If
INSIRUMENTS
POST OFFICE BOX 655303 • DALlAS, TEXAS 75265
2-19
2-20
AM26LS32AC, AM26LS33AC, AM26LS32AM, AM26LS33AM
QUAD DIFFERENTIAL LINE RECEIVERS
OCTOBER 1980 - REVISED MARCH 1993
SLLSll5A-
• AM26LS32A Meets EIA Standards RS-422-A
and RS-423-A
AM26LS32AC, AM26LS33AC ••• D OR N PACKAGE
AM26LS32AM, AM26LS33AM ••• J PACKAGE
(TOP VIEW)
• AM26LS32A Has :I: 7-V Common-Mode
Range With :l:20D-mV Sensitivity
Vee
• AM26LS32A Has ± 15-V Common-Mode
Range With ±500-mV Sensitivity
4B
4A
• Input Hysteresis •.. 50 mV Typical
• Operates From a Single 5-V Supply
• Low-Power Schottky Circuitry
•
•
•
•
2A
4Y
G
3Y
2B
3A
2Y
3-State Outputs
Complementary Output Enable Inputs
Input Impedance ••• 12 kQ Min
Designed to Be Interchangeable With
Advanced Micro Devices AM26LS32 and
AM26LS33
GND
AM26LS32AM, AM26LS33AM ••• FK PACKAGE
(TOP VIEW)
description
Compared to the AM26LS32 and the AM26LS33,
the AM26LS32A and AM26LS33A incorporate an
additional stage of amplilfication to improve
sensitivity. The input impedance has been
increased resulting in less loading of the bus line.
The additional stage has increased propagation
delay; however, this will not affect interchangeability in most applications.
3 2
1Y
The AM26LS32A and AM26LS33A are quad line
receivers for balanced and unbalanced digital
data transmission. The enable function is
common to all four receivers and offers a choice
of active-high or active-low input. The 3-state
outputs permit connection direct to a busorganized system. Fail-safe design ensures that if
the inputs are open, the outputs will always be
high.
4
5
6
7
8
G
NC
2Y
2A
1 2019
18
17
16
15
14
9 10 11 12 13
4A
4Y
NC
G
3Y
alOOal«
N Z
Z
C')
C').
(!)
NC-No Internal connection
FUNCTION TABLE
(each raceiver)
DIFFERENTIAL
A-B
VID",VTH
The AM26LS32AC and AM26LS33AC are
characterized for operation from O·C to 70·C. The
AM26LS32AM
and
AM26LS33AM
are
characterized for operation over the full military
temperature range of-55·C to 125·C.
VTL"VID"VTH
VID" VrL
X
Open
=
H high level,
X =irrelevant,
=
ENABLES OUTPUT
y
G
G
H
X
H
X
H
X
L
X
L
H
H
X
L
X
L
H
L
L
Z
H
X
X
L
H
H
?
?
=
L low level, ? indeterminate;
Z =high impedance (off)
Copyright © 1993, Texas Instruments Incorporated
TEXAS .."
INSIRUMENTS
POST OFFICE BOic 655303 • DALlAS, TEXAS 75265
2-21
AM26LS32AC, AM26LS33AC, AM26LS32AM, AM26LS33AM
QUAD DIFFERENTIAL LINE RECEIVERS
SI.1S11!5A- 02434, OCTOBER 1980- REVISED MARCH 1993
logic symbol t
G
4
logic diagram (positive logic)
.. 1
G
EN
G
]
1A
1B
G
Jrl>
1A
3
1Y
3
1Y
'il
1B
2A
5
2A
5
%f
2B
%f
2B
3A
3A
11 3Y
3B
4A
11
3Y
3B
4A
13 4Y
13
4Y
4B
4B
t This symbol is In accordance with ANSVIEEE Sid 91-1984
and lEe Publication 617-12.
Pin numbers shown are for D, J,
I
>
II
III
I
J
f
~
i'S
3
0
~J::.
Vce=5V
vIO=0.2mV
IOH = - 440 !LA
4
r-
'S
Q.
'S
3
~
2
0
ii
2
.c
.rP
CI
Z
:i:
I
I
Z
Z
~
~
-30
-40
-10
-20
IOH - High-Level Output Cu"ent - mA
o
o
-50
10
20
30
40
50
60
TA - Free-Air Temperature - °e
Figure 2
I
j
vs
LOW-LEVEL OUTPUT CURRENT
FREE-AIR TEMPERATURE
0.4
'S
!
0
~
!
0.2
I
...J
~
./
0.3
V
/
LOW-LEVEL OUTPUT VOLTAGE
vs
0.6
>
/
V
/
0.5
V
>
I
j
./
i
o
V
I
I
...J
~
0.1
o
I
o
10
5
15
25
20'
IOL - Low-Level Output Cu"ent - mA
30
0.4
.~
r--
~
I
Vee=5V
VIO=-0.2V
IOL=8mA
0.3
0.2
0.1
o
o
10
Figure 4
20
30
40
50
60
TA - Free-Air Temperature _ 0p
Figures
t Vee = 5.5 V and Vee = 4.5 V applies to M suff~ devices only.
TEXAS
~
INSIRUMENTS
2~6
eo
Figure 3
LOW-LEVEL OUTPUT VOLTAGE
VCd=5V I
TA = 25°C
0.5 r- VIO = -0.2 mV
70
POST OFFICE BOX 655303 • DAUAS. TEXAS 75265
70
eo
AM26LS32AC, AM26LS33AC, AM26LS32AM, AM26LS33AM
QUAD DIFFERENTIAL LINE RECEIVERS
SUSll5A-D2434. OCTOBER 1960-REVISED MARCH 1993
TYPICAL CHARACTERISTICS
OUTPUT VOLTAGE
OUTPUT VOLTAGE
va
va
ENABLE VOLTAGE
ENABLE VOLTAGE
5
5
VIO =O.2V
TA=25°e
Load = 8 kg to GND
4.5
4
>
I
~
'5
Go
'5
0
=
Vee=5V
3.6
III
J
Vee=5V
4.5 I- VIO=0.2V
Load 8 kQ to GND
4 l-
.!
~
Vee=6.5V
>I
Vee=4.5V
3
III
f
2.5
'5
t
2
~
I
1.5
3
2.5
2
0
I
I
TA=70oe
TA=25°e
TA=ooe
3.5
~
0.5
1.5
0.5
o
o
0.5
1.5
2
2.5
o
o
3
0.5
OUTPUT VOLTAGE
va
ENABLE VOLTAGE
ENABLE VOLTAGE
I
Vee=5.5V
Vee=4.5V
I
f
i
I
6
I
VIO=-0.2V
Load = 1 kg to Vee
TA=25°e
Vee=5V
3
OUTPUT VOLTAGE
va
6
>
2.5
2
Figure 7
Figure 6
5
1.5
Enable G Voltage - V
Enabla G Voltage - V
5
>
I
4
3
f
3
I
2
i
2
~
.-
4
------
TA =O"e
TA=25°e
-
TA=70oe
~
o
o
0.5
1.5
2
2.5
3
o
Vee=5V
VIO=-0.2V
Load = 1 kg to Vee
o
0.5
1.5
2
2.5
3
Enable G Voltage - V
Enable G Voltage - V
Figure 8
Figure 9
1ExAs,lf
INS1RUMENTS
POST OFFICE BOX 655303 • DAUAS. TEXAS 75265
2~7
AM26LS32AC, AM26LS33AC, AM26LS32AM, AM26LS33AM
QUAD DIFFERENTIAL LINE RECEIVERS \
SLLS115A.-D2434. OCTOBER 1980-REVlSEo MARCH 1993
TYPICAL CHARACTERISTICS
AM26LS32A
OUTPUT VOLTAGE
AM26LS33A
OUTPUT VOLTAGE
va
vs
DIFFERENTIAL INPUT VOLTAGE
DIFFERENTIAL INPUT VOLTAGE
5
4.5
4
>
I
5
'SQ.
'S
0
3.5
4
>
VIC = r- VIC'
ov
7V
I
~
I§l
1--
vT_
i
VT+
vT+
2.5
2
r-- I-
VT_
1.5
r- VT-
0
VT+
-?
-
I- vic = r-r-- VIC = 1 ov
15V
3
2.5
2 -
VT_
I
0.5
o
VIJ=
-15V
3.5
II
3
I
-?
4.5
VIC·
-7V
II
I§l
VCC=IiV, 10=0, TA=25°C
VCC=IiV
10=0
TA = 25°C
- r-
VT_
VT+
1.5
VT_
r---
VT+
0.5
-200-150 -100 -50
0
50
100
o
150 200
-200-150 -100 -50
0
50
100 150 200
VID - Differential Input Vohage - mV
VID - Differential Input Voltage - mV
Figure 10
Figure 11
INPUT CURRENT
va
INPUT VOLTAGE
4
r--"T"""......-
31-+--+-
~
21-+--+-
I
!
01---+--+-
i
I
The Unshaded Area
Shows Requirements of
Paragraph 4.2.1 of EIA
Standards RS-422-A and
RS-423-A
-2
- 3
1--+---+-
_4'-...L...--L-25-20-15-10-5
0
Ii
10
15
VI-Input Voltage - V
Figure 12
1ExAs
2-28
VT+
.Jf
INSIRUMENTS
POST OFFICE BOX 655303 • DALlAS. TEXAS 75265
20
25
AM26LS32AC, AM26LS33AC, AM26LS32AM, AM26LS33AM
QUAD DIFFERENTIAL UNE RECEIVERS
SUS115A- 02434, OCTOBER 1980 - REVISED MARCH 1993
APPLICATION INFORMATION
1/4 AM26LS31AC
1/4 AM26LS32AC
Data
Data In
Out
1/4 AM26LS32AC
1/4 AM26LS33AC
Dm
Dm
Out
Out
t AT equals the characteristic impedance of the line.
Figure 13. Circuit With Multiple Receivers
1ExAs ."
INSIRUMENTS
POST OFFICE BOX 655303 • bAUAS, TEXAS 75265
2~9
2-{30
AM26S10C, AM26S11C
QUADRUPLE BUS TRANSCEIVERS
JANUARY 1977 - REVISED JANUARY 1993
• Schottky Circuitry for High Speed, Typical
Propagation Delay Time ..• 12 ns
• Drivers Feature Open-Collector Outputs for
Party-Line (Data Bus) Operation
• Driver Outputs Can Sink 100 rnA at 0.8 V
Maximum
• PNP Inputs for Minimal Input Loading
• Designed to Be Interchangeable WHh
Advanced Micro Devices AM26S10 and
AM26S11
D OR N PACKAGE
(TOP VIEW)
GNO
18
16
Vee
48
4R
13 40
12 S
11 30
10 3R
9 38
15
14
20
2R
28
GNO
description
The AM26S10C and AM26S11 C are quadruple bus transceivers utilizing Schottky-diode-clamped transistors
for high speed. The drivers feature open-collector outputs capable of sinking 100 rnA at 0.8 V maximum. The
driver and strobe inputs use pnp transistors to reduce the input loading.
The driver of the AM26S10C is inverting; the driver of the AM26S11 C is non inverting. Each device has two
ground connections for improved ground current-handling capability. For proper operation, the ground pins
should be tied together.
The AM26S1 OC and AM26S11 C are characterized for operation over the temperature range of O·C to 70·C.
Function Tables
AM26S1OC
(tranamltting)
INPUTS
OUTPUTS
S
D
B
R
L
H
L
H.
L
L
H
L
AM26S11C
(transmitting)
INPUTS
OUTPUTS
S
D
B
L
H
H
L
L
L
L
H
R
AM26S10C AND AM26S11C
(receiving)
INPUTS
OUTPUT
S
B
D
R
H
H
H
L
X
X
H
L
H = high level. L = low level. X = Irrelevan!
1ExAs
.Jf
Copyright © 1993. Texas Instruments Incorporated
INSIRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
2-31
AM26S1OC, AM26S11C
QUADRUPLE BUS TRANSCEIVERS
SLLS116A-D2298. JANUARY 1977 ~ REVISED JANUARY 1993
logic symbols t
AM26S1OC
AM26S11C
2
20
2R
3D
3R
7
9
15
4D
4R
1B
2B
p........_7 2B
3B
f'>--<.....- 3 B
4B
15
f'>--<.....~4B
9
t These symbols are in accordance wRh ANSVIEEE SId 91-1984 and IEC Publication 617-12.
logic diagrams (positive logic)
AM26S11C
AM26S1OC
S
S
10
D---I..........._
:2:. 1B
1R
10
1R
D---I..........._ _
7 2B
D---I..........._ _
7 2B
2D
20
2R
2R
3D
D---I..........._=-9 3B
4R
3D
D---I...........~15::... 4B
40
4R
1ExAs . "
INSIRUMENfS
2-32
D---I..........._~9 3B
3R
3R
40
D---I..........._.=2 1B
POST OFFICE BOX 855303 • DAUAS. TEXAS 75265
D---I...........~1""-5 4B
·
AM26S10C, AM26S11C
QUADRUPLE BUS TRANSCEIVERS
SLLSll6A- 02298. JANUARY 1977 - REVISED JANUARY 1993
schematic (each transceiver)
B------;======;=========;==~--~~~~--------~~------~--._vcc
2kO
1100
NOM
NOM
R
D~---I
~--~------+-----~--~---+-----+~-+----~--+---~--~~-----GND
r-------------- ---------- ---------,
I
IL ______ ,
2.7kQ
NOM
Common
I
I
I
Drivers
I
ToOne
To Two
I--+------Other
I
Other
Receivers
Receiver
s
I
I
I
L __________________________________________ JI
Circuitry
To Three
Other
1-------
POST OFFICE BOX 655300 • DAUAS. TEXAS 75265
2--'33
AM26S10C,AM26S11C
QUADRUPLE BUS TRANSCEIVERS
SUS116A- 02298, JANUARY 1977 - REVISED JANUARY 1993
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) """,............................................. -0.5 V to 7 V
Driver or strobe input voltage range, VI ...................•......................... -0.5 V to 5.5 V
Bus voltage range, driver output off, Vo ........................................... -0.5 Vto 5.25 V
Driver or strobe input current range, II ............................................ -30 mA to 5 mA
Driver output current, 10 ................................................................. 200 mA
Receiver output current, 10 ................................................................ 30 mA
Continuous total power dissipation ..................................... See Dissipation Rating Table
Operating free-air temperature range .................................................. O°C to 70°C
Storage temperature range ....................................................... -65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds ............................... 260°C
NOTE 1: All voltage values are with respect to network ground terminals connected together.
DISSIPATION RAllNG TABLE
TAs25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
TA = 70°C
POWER RATING
0
950mW
7.SmWre
S06mW
N
1150mW
9.2mWre
736mW
PACKAGE
recommended operating conditions
Supply voltage, Vee
High-Ievael input voltage, VIH
Low-level input voltage, VIL
MIN
NOM
MAX
UNIT
4.75
5
5.25
V
2
OorS
B
DorS
0.8
B
1.75
Driver
100
-1
Receiver high-level output current, IOH
Low-level output current, IOL
20
Receiver
Operating free-air temperature, TA
0
1ExAs
~
INSIRUMENTS
2-34
V
2.25
POST OFFICE BOX 655303 • DAUAS, TEXAS 75265
70
V
rnA
rnA
°e
AM26S1 DC, AM26S11 C
QUADRUPLE BUS TRANSCEIVERS
SLLSll6A- D2298, JANUARY 19n - REViseD JANUARY 1993
electrical characteristics over recommended operating free-air temperature range
PARAMETER
VIK
Input clamp voltage
VOH
High-level output voltage
Vee = 4.75 V,
11=-18mA
R
Vee = 4.75 V,
10H=-1 mA
VIH=2V,
VIL=0.8V,
R
VOH
10(off)
Low-level output voltage
IIH
High-level input current
II
Input current at maximum
input voltage
IlL
Low-level input current
lOS
Short-circuit output current*
ICC
Vee = 4.75 V,
VIL=0.8V
VIH =2V,
VIL=0.8V
B
0
S
OorS
0
S
R
VIH=2V,
MAX
UNIT
-1.2
V
V
3.4
0.5
10L=40mA
0.33
0.5
IOL=70mA
0.42
0.7
10L= l00mA
0.51
VO=0.8V
-50
Vee = 5.25 V,
VO=4.5V
100
Vee=O,
VO=4.5V
100
Vee = 5.25 V,
VI=2.7V
Vee = 5.25 V,
VI=5.5V
Vee = 5.25 V,
VI =0.4V
30
20
100
-0.54
-0.36
-18
Vee = 5.25 V
-60
45
No load,
V
0.8
Vee = 5.25 V,
strobe at 0 V,
Vee = 5.25 V,
All driver outputs low
Supply current
2.7
10L=20mA
B
Off-stage output current
TYPT
MIN
TEST CONomONS
OorS
70
80
(.IA
(.IA
(.IA
mA
mA
mA
t All typical values are at TA = 25°C and Vee = 5 V.
* Not more than one output should be shorted to ground at a time, and duration of the short circuit should not exceed one second.
switching characteristics, Vee = 5 V, TA = 25°e
PARAMETER
tPLH
Propagation delay time,
low-to-high-Ievel output
tpHL
Propagation delay time,
high-to-Iow-Ievel output
tpLH
Propagation delay time,
low-to-high-Ievel output
tpHL
Propagation delay time,
high-to-Iow-Ievel output
tpLH
Propagation delay time,
low-to-high-Ievel output
tpHL
Propagation delay time,
high-to-Iow-Ievel output
ITLH
Transition time,
low-to-high-Ievel output
ITHL
Transition time,
high-to-Iow-Ievel output
FROM
(INPUT)
TO
(OUTPUT)
0
B
S
TEST
CONOmONS
AM26S11C
AM26S1OC
MIN
TYP
MAX
10
MIN
TYP
MAX
15
12
19
10
15
12
19
14
18
15
20
13
18
14
20
10
15
10
15
10
15
10
15
UNIT
ns
B
ns
See Figure 1
B
ns
R
4
10
4
10
2
4
2
4
B
ns
POST OFFICE SOX 655303 • DAllAS. TEXAS 75265
2-35
AM26S10C, AM26S11C
QUADRUPLE BUS TRANSCEIVERS
SllS116A- 02298, JANUARY 1977 - REVISED JANUARY 1993
PARAMETER MEASUREMENT INFORMATION
VCC
r-------------------------,
I
~g
.------~-~-.JVII'v----___.
AM26S11C
r-+-t:r-4- - [>0- l
280g
Receiver
I
I
I
1
I .--
__________
(_NoteC)
~pF
(see Note B)
Pulse
I
15PFI
(_NoteB)
Generator
(see Note A)
D
S
R
B
TEST CIRCUIT
. . .,". .]
AM26S11C
I
I
*------------------ ::v
AM26S1OC
Strobe Input!
I
I
OV
J
!
_ __~I------~I~-----J"
I
~
j4- tpLH
I
-~
-.I
I
~ j4""
I
DtoB
tpHL
DtoB
-J.
r- s
t PLH
to B
-.!
-.I
j4- tli"HL
BtoR
j4- tpLH
I
...Jf
ReceiverOutput--""'\I-_ _
BtoR
I
tpHL
StoB
\""'---- - ~- - ::
\I...------...Jl
I
14-
-.j j4- tpHL -./
BtoR
I
j4- tpLH
I
-'F
BtoR
\'-__
VOLTAGE WAVEFORMS
\
NOTES: A. The pulse generators have the following characteristics: Zo = SO g, tr = 10 ,. 5 ns.
B. Ineludes probe and jig capacitance.
C. All diodes are 1N916 or equivalent.
Figure 1. Test Circuit and Voltage Waveforms
2-36
POST OFFICE BOX 655303 .' DAUAS, TElWl 75265
VOH
1.5V
VOL
AM26S10C, AM26S11C
QUADRUPLE BUS TRANSCEIVERS
SUSll6A- 02298. JANUARY 1977 - REVISED JANUARY 1993
APPLICATION INFORMATION
Strobe
Strobe
Driver
Inputs
lffi
DDDD
5V
Receiver
Outputs
~
S R
AM26S1OCI
AM26S11C
B B B B
1000
1
Strobe
Driver
RRR-
Driver
Inputs
lffi
DDDD
Receiver
Outputs
~
B B B B
lffi
DODD
S R
AM26S1OCI
AM26S11C
Inputs
R-
R-
Outputs
~
S R
AM26S1OCI
AM26S11C
R-
1
Receiver
B B B B
1
R-
5V
RR1000
1000
1000
1000
1000
1000
1000
100-0 Transmission Une
Figure 2. Party-Line System
1ExAs
..If
INSIRUMENTS
POST OFFICE BOX 655303 • DAUAS. TEXAS 75265
2-37
2-38
DP8480
10K ECl·TO·TTl lEVEL TRANSLATOR WITH LATCH
SLLS0358-
FEBRUARY 1993
• ECl Control Inputs
NPACKAGE
(TOP VIEW)
• 3-State Outputs
• 10K ECl Input Compatible
00
Vee
00
01
01
VEE
• Direct Replacement for National
Semiconductor DP8480
02
02
03
description
This circuit translates ECL-input levels to TTLoutput levels and provides an inverting
transparent latch. The 3-state outputs are
designed to drive highly capacitive loads. All
inputs operate at ECL levels.
03
04
DE
GND
If latch enable (LE) is low, the latches are transparent and the Q outputs follow the complement of the D inputs.
If LE is high, the outputs are latched. If output enable (OE) is high, the outputs are in the high-impedance state,
as they are during power up and power down.
The DP8480 is characterized for operation from
logic symbol t
10
7
DO
D1
D2
D3
D4
2
logic diagram
r.... EN
r.... C1
ECL/TTL
.,
r
15
V
1D
3
a·e to 75·C.
14
4
13
5
12
6
11
OE
~ i'......
LE
~
Qo
Q1
Q2
Q3
DO
t>
2
ECL/TTL
~ C1
1D
I-
ECL/TTL
and lEe Publication 617-12.
D1
3
.....c C1
1D
I-
EN
- -
FUNCTION TABLE
(each latch/tranalator)
L
L
L
v~ QO
Q4
t This symbol is In accordance w~h ANSI/IEEE SId 91-1984
OE
H
EN
- -
v~
ECL/TTL
LE
D
Q
X
L
L
X
L
H
Z
H
L
H
X
00
D2
4
.....c C1
1D
I-
EN
- -
v~
ECL/TTL
D3
5
.....c C1
1D
I-
-
EN
-
v~
ECL/TTL
-C C1
D4
1ExAs
6
~
1D
r--
EN
v~
Copyright © 1993, Texas Instruments Incorporated
INSIRUMENTS
POST OFFICE BOX 655303 • DALlAS. TEXAS 75265
2~9
DP8480
10K ECl-TO-TTL lEVEL TRANSLATOR WITH LATCH
Su.s035B - D3058, NOVEMBER 1987 - REVISED FEBRUARY 1993
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee ................... _.................................................... 7 V
Supply voltage, VEE ....................................................................... -8 V
Input voltage range, VI ................................................................ 0 V to VEE
Output voltage, Vo ........................................................................ 5.5 V
Continuous total dissipation ........................................... See Dissipation Rating Table
Operating free-air temperature range ...............•.................................. O°C to 75°C
Storage temperature range ....................................................... -65°C to 150°C
Lead temperature 1,6 mm (1116 inch) from case for 10 seconds ............................... 260°C
)
DISSIPATION RATING TABLE
PACKAGE
TAS2S·C
POWER RATING
DERATING FACTOR
ABOVE TA = 25"C
TA=75·C
POWER RATING
N
1150mW
9.2mW/"C
690mW
recommended operating conditions
MIN
NOM
MAX
Supply voltage, VCC
4.5
5
5.5
V
Supply voltage, VEE
-4.68
-5.20
-5.72
V
-1145
-840
TA=25·C
-1105
-810
TA=75·C
-1045
-720
TA=O·C
High-level Input voltage, VIH (see Note 1)
Low-level Input voltage, VIL (see Note 1)
TA=O·C
-1870
-1490
TA=25·C
-1850
-1475
TA=75·C
-1830
-1450
UNIT
mV
mV
ns
Pulse duration, LE low, tw (see Figure 1)
5
Setup time, data before LE t, tsu (see Figure 1)
3
ns
Hold time, data after IEt, th (see Figure 1)
3
ns
Operating free-air temperature, TA
0
..
75
·C
NOTE 1: The algebraic convention, In which the least positive (most negatIVe) value is deSignated minimum, Is used In thIS data sheet for logIC
levels only.
electrical characteristics over recommended ranges of supply voltages and operating free-air
temperature (unless otherwise noted)
PARAIIIETER
TEST CONDITIONS
MIN
TYpt
MAX
0.2
0.5
V
75
350
50
85
!lA
!lA
VOH
High-level output voltage
IOH =-10mA
VOL
Low-level output voltage
IOL= 12 mA
IIH
High-level input current
VIH=VIH max
IlL
Low-level input current
VIL = VIL min·
IOSH
High-state short-cIrcuit output current
VOSH=O,
See Note 2
-70
-150
IOSL
High-state short-circuit output current
VOSL = 2.5 V.
See Note 2
70
150
IOZ
High-impedance state output current
Vo =Ot05V
ICC
Supply current from Vec
Outputs open,
Inputs = VIL
16
lEE
Supply current from VEE
Outputs open,
Inputs = VIL
-30
UNIT
V
VCC-2
",1
mA
rnA
",50
35,
-50
!lA
mA
mA
t TYPical values are at VCC = 5 V. VEE = -5.2 V, TA = 25·C.
NOTE 2: During testing of IOSH or IOSL, only one output should be tested at a time and the current should be limited to a maximum of ",120 mA.
1ExAs,lf
INSIRUMENTS
2-40
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DP8480
10K ECl·TO·TTl lEVEL TRANSLATOR WITH LATCH
j
Su..s035B - 03058, NOVEMBER 1987 - REVISED FEBRUARY 1993
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
MIN
TYpt
MAX
tpLH
Propagation delay time, Iow-to-hlgh-Ievel output from LE Input
4
10
15
ns
tpHL
Propagation delay time, high-to-Iow-Ievel output from LE Input
4
11
15
ns
3.5
10
15
ns
3.5
11
15
ns
PARAMETER
TEST CONDITIONS
UNIT
tpLH
Propagation delay time, low-to-high-Ievel output from D Input
tPHL
Propagation delay time, hlgh-to-Iow-Ievel output from D input
len
Output enable time from OE Input
6
12
25
ns
Output disable time from OE Input
4.5
S
22
ns
CL=50 pF,
See Figure 1
!dIs
t Typical values are at VCC = 5 V. VEE = -5.2 V, TA = 25°C, and with all channels switched simuHaneously.
PARAMETER MEASUREMENT INFORMATION
7V
!
Sl
5000
Q
-<1..-----..
CL
(8ee Note A)
500 0
LOAD CIRCUIT
----,.U"".----------,\.:V\-----------·
14
LE
I
-I tw
--t I-- th
r----~--------~
1
1
D
-1.SV
I
1
t--+ tau -.I 1
III
I
I
\t
-----;.1---'" 1 2.4V
O.SV
I4-tPLH ....
_OE
_____
-J;.f_~
-O.SV
+-------
1
!+-tPHL....
Q (S1 open)
-O.SV
-l.SV
1
1
1
~-.J
__ _ VOH
I
. 1
I
1
'-tpHL....
2.4V
1
O.SV
14-tpLH-+I
______ _
-1.10V
O~;;------ -1.10V
1.
-1.47V
-1.47V
I4-ten ~
~1d18
-Q---nVO~H~-~~~3~V~
3,5 V
S1 Closed
:VOL+~3V~ OV
Q S1CI 088d
I
~
S:;.1:..;0::.rp;:::e;:.:n___
2.4V
VOH
O.S V
VOL
S10pen
NOTES: A. CL Includes probe and jig capacitance.
B. ECL Input rise times and fall time are 2 ns '" 0.2 ns from 20% to SO%.
Figure 1. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303 • DAUAS, TEXAS 75265
2-41
2-42
DP8481
10K TTL·TO·ECL LEVEL TRANSLATOR WITH LATCH
SLlS036B
•
•
•
•
ECl Control Inputs
10K ECl Compatible
Propagation Delay ... 4 ns Typ
Direct Replacement for National
Semiconductor DP8481
NOVEMBER 1987 - REVISED FEBRUARY 1993
NPACKAGE
(TOP VIEW)
Vee
VEE
00
01
02
03
04
description
This circuit translates TTL-input levels to ECloutput levels and provides a 5-bit transparent
latch. The outputs are gated by output enable
(OE) and can be wire-OR connected. The latch
enable (lE) and OE inputs are ECL.
DO
OE
11
10
GNO
9
6
01
02
03
04
LE
GNO
If latch enable (lE) is low, the latches are transparent and the Q outputs follow the complement of the D inputs.
If lE is high, the outputs are latched. If output enable (OE) is low, the outputs are forced to the low level.
The DP8481 is characterized for operation from QOC to 75°C.
logic symbol t
OE
LE
7
10
logic diagram (positive logic)
,
EN [ECl]
",I C1 [ECl]
ECl/TTL.
01
02
13
2 Qo
3
Q1
4
03
12
5
11
6
DO
D4
15
10
~
14
QO
Ci2
Q3
Q4
t This symbol is In accordance with ANSI/IEEE Std 91-1984 and
Q1
01
lEe Publication 617-12.
Ci2
FUNCTION TABLE
(each latch/translator)
OE
H
H
H
L
lE
L
L
H
X
0
H
Q
L
X
X
H
Q3
L
00
L
D4
1ExAs
..Jf
Q4
Copyright © 1993, Texas Instruments Incorporated
INSIRUMENTS
POST OFFICE BOX 655303 • DALlAS. TEXAS 75265
2-43
DP8481
10K TTl-TO-ECl lEVEL TRANSLATOR WITH LATCH
SLLS036B - 03059, NOVEMBER 1987':' REVISED FEBRUARY 1993
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee ........................................................................ 7 V
Supply voltage, VEE ....................................................................... -8 V
Input voltage range, VI: OE or LE input ...................................•............. 0 V to VEE
D inputs ..................................... ; ............... -1 Vto 5.5 V
Output current, 10 ...•..•.......•.......••.....•.......•.•.•...•...•.•....•.•........... -50 mA
Continuous total dissipation ........................................... See Dissipation Rating Table
Operating temperature range, TA ..................................................... O°C to 75°C
Storage temperature range ....................................................... -65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds ............................... 260°C
DISSIPATION RATING TABLE
PACKAGE
TA s 25·C
POWER RATING
DERATING FACTOR
ABOVE TA = 25·C
TA =75"C
POWER RATING
N
1150mW
9.2mW/"C
690mW
recommended operating conditions
MIN
NOM
MAX
Supply voltage, Vce
4.5
5
5.5
V
Supply voHage, VEE
-4.68
-5.20
-5.72
V
High-level input voltage, VIH (TTl-level 0 inputs)
0.8
-1145
-840
TA=25·C
-1105
-810
TA=75·C
-1045
-720
TA=O·C
High-level input voltage, VIH
(ECl-level OE and IE inputs) (see Note 1)
Low-level Input voltage, Vil
(ECl-level OE and lE inputs) (see Note 1)
TA=O·C
-1870
-1490
TA=25·e
-1850
-1475
TA=75·C
-1830
-1450
Pulse duration, lE low, tw (see Figure 1)
Setup time, tsu
V
2
Low-level input voltage, Vil (TTl-level 0 Inputs)
before lE t (see Figure 1)
~ata
before OEt (see Note 2 and Figure 1)
5
1
Operating free-air temperature, TA
0
..
..
mV
mV
ns
5.5
Hold time, data after lE t ,th (see Figure 1)
V
ns
5
~ata
UNIT
ns
75
·e
NOTES: 1. The algebraic convention, In which the least positive (most negatIVe) value IS deSignated minimUm, IS used In thiS data sheet for logic
levels only.
2. This setup time applies when operating in the transparent mode ([E Is low) and it Is necessary that valid data be available at the output
immediately after the outputs are enabled.
.
1ExAs ..,
INSIRUMENTS
2--44
POST OFFICE BOX _
• DAUAS. TEXAS 75265
DP8481
10K TTl·TO·ECl lEVEL TRANSLATOR WITH LATCH
SLLS036B - 03059. NOVEMBER 1987 - REVISEO FEBRUARY 1993
electrical characteristics over recommended ranges of supply voltages and operating free-air
temperature (unless otherwise noted)
PARAMETER
VIK
Input clamp voltage
IIH
High-level input current
IlL
Low-level input current
VOH
VOH(C)
VOL
VOL(C)
TEST CONDITIONS
00-04
11=-12mA
00-04
VI =2.SV
Oe.Le
VI =-0.8 V
00-04
VI=O.SV
oe.~
VI=-1.8 V
High-level output voltage
(see Notes 1 and 3)
Critical high-level output voltage
(see Notes 1 and 3)
Low-level output voltage
(see Notes 1 and 3)
Cr~icallow-level
output voltage
(see Notes 1 and 3)
MIN
TYpt
MAX
UNIT
-0.8
-1.2
V
1
40
200
-SO
-200
ISO
Vee=-S.2V.
TA=O°C
-1000
-840
Vee=-S.2V.
TA=2SoC
-960
-810
Vee=-S.2V.
TA=7SoC
-900
-720
Vee=-S.2V.
TA=O°C
-1020
Vee=-S.2V.
TA=2SoC
-980
Vee=-S.2V.
TA=7SoC
-920
TA=O°C
-1870
TA=2SoC
-1850
-16S0
Vee =-S.2 V,
TA=7SoC
-1830
-162S
Vee=-S.2v,
TA=O°C
-164S
Vee=-S.2v,
TA=2SoC
-1630
Vee=-S.2V,
TA=7SoC
-160S
Supply current from VCC
VCC= S.SV
Supply current from Vee
Vee=-S.7V
mV
-166S
Vee=-S.2V.
lee
IIA
mV
Vee=-S.2v,
ICC
IIA
mV
mV
20
mA
-90
mA
NOTes: 1. The algebraic convention. in which the least positive (most negative) value is designated one minimum. is used in this data sheet for
logic levels only.
3. VOH and VOL are tested using the outer-limit values VIH max and VIL min. The critical values VOH(C) and VOL(C) are tested using
the inner-limit values VIH min and VIL max. The latter values ensure the noise margins of ISS-mV high and 12S-mV low associated
with 10KeCL
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
MIN
TYpt
MAX
tpLH
Propagation delay time. low-to-high-Ievel output from LE input
I.S
4
6
ns
tpHL
Propagation delay time. high-to-Iow-Ievel output from LE input
I.S
4
6
ns
2.S
4
7.S
ns
2.S
4
7.S
ns
PARAMETER
TEST CONDITIONS
UNIT
tpLH
Propagation delay time. low-to-high-Ievel output from 0 input
tpHL
Propagation delay time. high-to-Iow-Ievel output from 0 input
ten
Output enable time from oe input
1
3
4
ns
!dis
Output disable time from oe input
1
3
4
ns
RL = SO cto-2V.
See Figure 1
t TYPical values are at VCC = S V, Vee = -S.2 V, TA = 2SoC.
1ExAs ..,
INSIRUMENTS
POST OFFICE BOX 655303 • DAUAS. TEXAS 75265
2-4S
DP8481
10K TTL·TO·ECl lEVEL TRANSLATOR WITH LATCH
SI.LS036B - 03059, NOVEMBER 1987 - REVISED FEBRUARY 1993
PARAMETER MEASUREMENT INFORMATION
/60%
OE
\~-----
----'
I
14
o
I
I)
tj tau
VIL
.1
j4-tdiS-1
-V--T--- 3V
\1,5V
VIH
I
I
II
I+-ten -I
I
OV
f"m-~--------~.-t--
Q
50%~ VOL
_ _ _ _ _ _ _J.
VOH
1+-.-'
----0,.---------W\------------- :::
I
I~
141
~teu~ I
I I
I I
1
I
I
I
I
I
I
~
t-5O%
I
I
tl
-----3V
1.5V
1.5V
I
tl
I--------------------~I
1
14
I
I
I
~_ _+ I - - - - -__
tpHL
\50%
I
I
i
I
l!+4-
tpLH
+------- ov
tl
14
tpHL
FeVOH
I
___
tor!
VOL
tpLH
NOTE A:. EeL input rise and faU times at OE and LE are 2 ns ",0.2 ns from 20% to 80%. TTL input rise and faU times at D inputs are 3 ns maximum
measured between 10% and 90%.
Figure 1. Switching Time Waveforms
1ExAs ",
2-46
INSIRUMENTS
POST OFFICE BOX 655303 • DAUAS. TEXAS 75265
LT1030C
QUAD LOW-POWER LINE DRIVER
APRIL 1989- REVISED MARCH 1993
•
Low Supply Voltage ... ±5 V to ±15 V
o OR N PACKAGE
•
•
•
•
•
•
Supply Current •.• 500 !1A Typ
Zero Supply Current When Shut Down
Outputs Can Be Driven ±30 V
Output Open When Off (3.State)
10-mA Output Drive
Output of Several Devices Can Be
Paralleled
(TOPVJEW)
•
Meets ANSI/EIA·232·D·1986 Specifications
(Revision of EIA Std RS·232·C)
Designed to Be Interchangeable With
Linear Technology LT1030
•
1
VCCIN1
2
VCC+
STROBE
OUT1
3
IN4
ON/OFF
4
OUT4
IN2
5
NC
OUT2
6
IN3
GND
7
OUT3
NC - No internal connection
AVAILABLE OPTIONS
PACKAGE
description
The LT1 030C is an EIA-232 line driver that
operates over a ±5-V to ± 15-V supply voltage
range on low supply current. The device can be
shut down to zero supply current. Current limiting
fully protects the outputs from externally-applied
voltages of ±30 V. Since the output swings to
within 200 mV of the positive supply and to within
1 V of the negative supply, supply voltage
requirements are minimized.
TA
SMALL OUTLINE
(D)
PLASTIC DIP
(N)
O·Cto 70·C
LT1030CD
LT1030CN
The 0 package is available taped and reeled. Add the
suffix R to the device type (i.e., LT1030CDR).
logic symbol t
STROBE
A major advantage of the LT1030C is the
high-impedance output state when the device is
off or powered down. This feature allows several
different drivers on the same bus.
ON/OFF
IN1
IN2
The divide can be used as an EIA-232 driver,
micropower interface, or level translator, among
others.
The LT1030C is characterized for operation from
O'Cto70'C.
IN3
IN4
13
4
"
G1
~N
2
5
9
12
'" 1
'"
"
'"
t>
3
6
8
11
OUT1
OUT2
OUT3
OUT4
tThis symbol Is in accordance with ANSVIEEE SId 91-1984
and IEC Publication 617-12.
Terminal Functions
PIN
NAME
GND
DESCRIPTION
NO
7
Ground pin
IN1,IN2,
IN3,IN4
2,5,
9, 12
Logic inputs. Operate properly on TTL or CMOS levels. Output valid from VI = VCC- + 2 V to 15 V. Connect to 5 V
when not used.
ON/OFF
4
Shuts down entire circuit. Cannot be left open. For normally on operation, connect between 5 V and 10 V. If VIL is
at or near 0.8 V, significant settling time may be required.
OUT1,OUT2,
OUT3,OUT4
3,6,
8,11
Une driver outputs
STROBE
13
Forces all outputs low. Drive with 3 V. Strobe terminal input impedance Is approximately 2 kg to GND. Leave open
when not used.
VCC+
14
POSitive supply
VCC-
1
Negative supply
1EXAs .Jf
Copyright@1990, Texas Instruments Incorporated
INSIRUMENI'S
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2-47
LT1030C
QUAD LOW-POWER LINE DRIVER
Su.s048C ~ D3297, APRIL 1989 - REVISED MARCH 1993
logic diagram
4
ON/OFF
13
STROBE
3
2
IN1
6
5
1N2
8
9
IN3
11
12
IN4
OUT1
OUT2
OUT3
OUT4
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, Vcc+ (see Note 1) ............................................... OVto 15V
Supply voltage range, Vcc- ........... ~. .... .. ... .. .. . .... ...... ...... .. .. ..... . .. .. 0 Vto-15 V
Input voltage range, logic inputs, VI .................................................. Vcc- to 25 V
Input voltage range at ON/OFF, VI ..................................................... 0 V to 12 V
Output voltage range (any output) ...................................... VCC+ - 30 V to Vcc- + 30 V
Duration of output short circuit to ±30 V at (or below) 25°C (see Note 2) ...................... unlimited
Continuous total dissipation ........................................... See Dissipation Rating Table
Operating free-air temperature range, TA .............................................. O°C to 70°C
Storage temperature range ....................................................... -65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds ............................... 260°C
NOTES: 1. All voltage values, except differential voltages, are with respect to GND.
2. The output may be shorted to either supply. Temperature and/or supply voltages must be limited to ensure that the maximum
dissipation rating is not exceeded.
DISSIPATION RATING TABLE
TA,,25·C
POWER RATING
DERATING FACTOR
ABOVE TA = 25·C
0
950mW
7.6mWrC
608mW
N
1150mW
9.2mWrC
736mW
PACKAGE
TA=70·C
POWER RATING
recommended operating conditions
UNIT
MIN
MAX
Supply voltage, VCC+
5
15
Supply voltage, VCC-
-5
-15
V
2
15
V
High-level input voltage, VIH (see Note 3)
Low-level input voltage, VIL (see Note 3)
Operating free-air temperature, TA
0
NOTE 3: These VIH and VIL specifications apply only for inputs IN1-IN4. For operating levels for ON/OFF,see Figure 2.
1E:xAs
..If
INSIRUMENfS
2-48
POST OFFICE BOX 6615303 • DAUAS, TEXAS 75266
V
0.8
V
70
·C
LT1030C
QUAD LOW·POWER LINE DRIVER
SllS048C - D3297,APRIL 1989- REVISED MARCH 1993
electrical characteristics over operating free·air temperature range, VCC:t =:t5 V to :t15 V (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VOM+
Maximum positive peak output voRage swing
10=-2mA,
TA = 25°C
VOM-
Maximum negative peak output voRage swing
10=2mA,
TA = 25°C
IIH
High-level input current
VI .. 2V,
TA=25°C
IlL
Low-level Input current
VI ,,0.8V,
TA = 25°C
MIN
TYpt
VCC+-0.3
VCC+-O.l
VCC-+0.9
Input current, ON/OFF
10
Output current
TA = 25°C
10Z
Off-state output current
VO=.,15V,
TA=25°C,
ON/OFF at 0.4 V
ICC
Supply current (all outputs low)
VI .. at2.4V,
VI=5V
ICC(ofl)
5
10=0
V
10
20
-0.1
-10
30
65
IlA
mA
12
",2
.,100
IlA
500
1000
IlA
10
0NJ5FF at 0.1 V
V
IlA
IlA
20
ON/OFF at 0.4 V
Off-state supply current
UNIT
VCC-+l.4
2
VI=O
II
MAX
IlA
150
10
operating characteristics, VCC:t =:t5 V to :t15 V, TA = 25°C
PARAMETER
SR
TEST CONDITIONS
RL = 3 ko,
Driver slew rate
CL = 51 pF
MIN
TYpt
MAX
4
15
30
t All typical values are at VCC., = ",12V, TA = 25°C.
POST OFFICE BOX 655303 • DAUAS, TEXAS 75265
2-49
LT1030C
QUAD LOW-POWER LINE DRIVER
SLLS048C-D3297.APRIL 1989-REVISEDMARCH 1993
TYPICAL CHARACTERISTICS
MAXIMUM PEAK OUTPUT VOLTAGE SWING
,vs
OUTPUT CURRENT
FREE-AIR TEMPERATURE
- § '"" -"1.8
"-
,
~ .....
=:- 1.4
Co
&
VCC_+ 1•4
.I'l 1.2
~
Vce- +1.2
Vcc-+ 1
VCC_+0.8
!.~
----
./
I'
o
.. 2
o
GND
.. 3
I
o
I
vs
140
IT
I
0
1a..
10=5rnA
~
i
VCC_+ 0•8
....
!
10=-1 rnA _
I
VCC .. = .. 12V
VCC_+0.6
100
/
80
::I
10=-5mA
VCC- +1
I
o
I
I
10
20
30
40
50
60
-
70
80
E
~
40
III:
20
~
0
/
0
-20
v
o
TA - Free-Air Temperature - °c
Figure 3
V
/
~
1kxAs ~
POST OFFICE BOX 655303 • DAu.AS. TEXAS 75265
/
/
V
2.5
5
7.5
10
12.5
ON/OFF Terminal Voltage - V
Figure 4
INSIRUMENTS
2--50
I
I
E VCe-+ 1•2
::I
E
~
c(
0
::E
I
VCC .. = .. 12V
TA=25OC
120
J
VCC-+ 1.4
i
::E
70
ON/OFF TERMINAL CURRENT
ON/OFF TERMINAL VOLTAGE
10=1 rnA
~
I
FREE·AIR TEMPERATURE
CD
~
!i VCc+- 0 ',4
I:L
!i
::
r--
vs
I
co VCC+-0.2
10...
-
Figure 2
MAXIMUM PEAK OUTPUT VOLTAGE SWING
!
--
Max Off Voltage
10 < 200 iAA
20
30
40
50
60
TA - Free-Air Temperature - °c
10
Figure 1
Vcc+
-r-........ "",-1 I
II-
0.4
10-Output Current - rnA
>I
I
Max Off Voltage
0.2 f- 10 < 20 iAA
VCC .. = .. 12V
TA=25°C
VCC_+O.2
I
Min On VOltage
t\,
~6
VCC_+0.4
VCC-
..........
{! 0.8
OutputLow _
VCC .. = .. 12V
RL=3ka
1'-0.
1.6
Output High
VCC_+0.6
ON/OFF TERMINAL VOLTAGE
vs
15
LT1030C
QUAD LOW-POWER LINE DRIVER
Su.s048C - 03297, APRIL 1989 - REVISED MARCH 1993
TYPICAL CHARACTERISTICS
OUTPUT CURRENT LIMIT
OFF·STATE OUTPUT CURRENT
vs
vs
FREE·AIR TEMPERATURE
FREE·AIR TEMPERATURE
30
-1
Vcc., = .,12V
27,5
1
I
I
(,)
1
d
I
...... ........
25
'"
"
"
(,)
"
!i
Sinking
............
!
i'--.
V
-0,1
0
•
I
J
/
/
/
-0,01
10
20
30
40
50
60
TA - Free-AI.r Temperature - ·C
70
V
25
V
30
35
40 45 50
55 60
TA - Free·Alr Temperature -'C
Figures
FREE·AIR TEMPERATURE
'"
::II
iI:
:3
(,)
5
I
VCC.,==12V
ON/OFF at 0,4 V
0,07
0,05
}to
t
/
U)
•
I
0,03
I
!
~
/
0,01
45
V
, 50
/
V
/
4
1
I
C
~
:3
(,)
i
/
55
TA=25'C
4,5
/
:3
70
SUPPLY CURRENT
VB
SUPPLY VOLTAGE
VS
I
65
Figure 6
OFF-STATE SUPPLY CURRENT
01
/
/'
~
17.5 I- Sourcing
~
/
:3
E
i
/
!
.........
20
°
./
/
I
22.5
15
VCC.,=,.12V
VO=-25V
::l-
:3
----
3,5
3
All Outputs High -
2,5
2
U)
I
(,)
E
1.5
All Outputs Low
0,5
60
65
70
°
10 12.5
TA - Free-Air Temperature-OC
15
17.5
20
22.5
25
27,5
30
IVcc + - Vcc-I- Total Supply Voltage - V
Figure 7
Figure 8
INSIRUMENfS
1ExAs '"
POST OFFICE BOX 655303 • DAllAS, TEXAS 75265
2--51
LT1030C
,
QUAD LOW-POWER LINE DRIVER
\
SLlS048C - D3297. APRIL 1989- REVISED MARCH 1993
TYPICAL CHARACTERISTICS
SUPPLY CURRENT
SLEW RATE
va
va
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
4
17
VCC±=±12V
3.5
~
3
I
i
2.&
b-----:
::I
c;
1".
~r
2
--
~-
All Outputs High
-
VCC±","'12V
RL =3kQ
CL .. &1 pF
•:s.
~
~
I
i
I
15
iii
I
a::
11)
1.5
I
o
!!
"
All Outputs Low
o
o
13
10
20
30
40
50
60
TA ~ Free-Air Temperature _·C
70
V
o
."....,
10
Figure 9
V
V
Failing .-"""
"""-
14
0.5
I
16
...--f--
-
RIsing
20
30
40
50
60
TA - Free-Alr Temperature - ·C
70
Figure 10
APPLICATION INFORMATION
forward biasing the substrate
Mwith other bipolar integrated circuits. forward biasing the substrate diode can cause problems. The LT1 030C
will draw high current from VCC+ to GND if VCC- is open circuited or pulled above ground. If this is possible.
connecting a diode from VCC- to GND will prevent the high-currentstate. Any low-cost diode can be used (see
Figure 11).
LT1030C
14
1N4OO1
7
8
. Figure 11. Connecting a Diode From VCC- to GND
2-52
1ExAs'"
INSTRI.JMENIS
POST OFFICE BOX _
• DAUAS. TEXAS 75265
LT1039
TRIPLE EIA·232 LINE TRANSCEIVER
SLLS105B-
•
Meets All EIA-232-D (Revision of RS-232-C)
Specifications
•
Three Independent Drivers and Receivers
Per Package
•
EIA-232 Inputs and Outputs Withstand
:1:30 V
•
3-State Outputs
•
All Outputs Are Short-Circuit Protected
•
Virtually Zero Supply Current When
Shutdown
•
Output of Several Devices Can Be
Paralleled
•
•
Operates From :l:S-V to :l:1S-V Supplies
FEBRUARY 1991 - REVISED JANUARY 1992
DW OR N PACKAGE
(TOP VIEW)
VCC
VOO+
BIAS
RlIN
01 OUT
R21N
020UT
R31N
D30UT
VOO-
3
6
7
8
9
12
11
10
ON/OFF
Rl0UT
OliN
R20UT
021N
R30UT
D31N
GND
Designed to Be Interchangeable With
Linear Technology LT1039
description
The LT1039 is a triple EIA-232 line transceiver designed to meet the requirements of Standard EIA-232-D. All
outputs are fully protected against an overload or short to ground. A major advantage of the LT1039 is
high-impedance output states when the device is off or powered down. This feature allows several different
devices to be connected together on the same bus.
The bias pin provides a receiver to be kept alive when the LT1039 is shutdown (ON/OFF = lOw).
The LT1039 is characterized for operation from O°C to 70°C.
AVAILABLE OPTIONS
TA
PACKAGE
SMALL OUTLINE
PLASTIC DIP
(OW)
(N)
O·Cto 7O·C
LT1039CN
LT1039COW
The OW package IS available taped and reeled. Add the suffix R to the
device type (i.e., LT1039COWR).
1ExAs
~
Copyright C> 1992, Texas Instruments Incorporated
INSIRUMENTS
POsT OFFICE BOX 655303 • DALlAS. TEXAS 75265
2-63
LT1039
TRIPLEEIA·232 LINE TRANSCEIVER
,
SLLSl 058 - D3627, FEBRUARY 1991 - REVISED JANUARY 1992
logic symbol t
BIAS
Rl0UT
RllN
R21N
R20UT
R3IN
R30UT
DllN
Dl0UT 4
13
D2IN
11 D31N
t This symbol Is in accordance wHh ANSi/IEEE Std 91-1984 and lEe Publication 617-12.
logic diagram
ON/OFF ...;.17"--_ _•
BIAS
2
(
~o---f-...;.16,,- Rl0UT
R2IN
R3IN
5
roo--I-...;.14..:-. R20UT
12::..
-'-UT.:x>-r-::
Dl0UT
R30UT
1---+-,,15:- DllN
1-~13:.... D2IN
1---+-,1..;...1 D31N
2-54
IN~~
POST OFACE BOX _
• DAU.AS, TExAs 75285
LT1039
TRIPLE EIA·232 LINE TRANSCEIVER
SLLS105B - 03627, FEBRUARY 1991 - REVISED JANUARY 1992
Terminal Functions
PIN
NAME
DESCRIPTION
NO.
BIAS
2
011N, 021N, 031N
15,13,
11
Une driver inputs. Operate properly on TTL or CMOS levels. Output valid from VI =
Connect to 5 V when not used.
Keeps receiver 1 alive while the LT1039 is in the shutdown mode. Leave BIAS open when not in use.
010UT, 020UT,
030UT
4,6,8
Une driver outputs
(voo-l + (2 to 15 V).
GNO
10
Ground
ON/OFF
17
Shuts down entire circuit. Cannot be left open. IfVIL is at or near 0.8 V. significant settling time may be required.
R1IN, R21N, R31N
3,5,7
Receiver inputs. Input impedance is normally 30 kg. Accepts EIA-232 voltage levels and has 0.4 V of
hystereSis to provide noise immunity.
R10UT, R20UT,
R30UT
16,14,
12
Receiver outputs with TTl/CMOS voltage levels
Positive supply voltage for driver
VOO+
1
VOO-
9
Negative supply voltage for driver
VCC
18
5-V supply voltage for receivers
absolute maximum ratings over operating free-air temperature range (unless .otherwise noted)
Supply voltage range, Voo+ (see Note 1) ... , ... ,., ............. ,.,., ... , ....... , ... , ... 0 V to 15 V
Supply voltage range, Voo- ....... , ... ,.,.,',.,"""",.,.,.,.,., ... ,.,.,.,.,.,.,., 0 V to -15 V
Supply voltage, Vee , ....................................................................... 7 V
Input voltage range, driver input ...................................................... Voo- to 25 V
receiver input ......................................................... :1:30 V
Input voltage range, ON/OFF .......................................................... 0 V to 12 V
Output voltage range, driver output ..................................... Voo+ -30 V to Voo- + 30 V
Duration of output short circuit at (or below) TA =25'C (to :1:30 V, see Note 2) ................. unlimited
Continuous total dissipation ........................................... See Dissipation Rating Table
Operating free-air temperature range, TA ............................................. O'C to 70'C
Storage temperature range ....................................................... -65'C to 150'C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds ............................... 260'C
NOTES: 1. All voltage values, except differential voltages, are with respect to the GNO terminal.
2. The output may be shorted to either supply. Temperature and/or supply voltages must be limited to ensure that the maximum
dissipation rating is not exceeded.
DISSIPATION RATING TABLE
PACKAGE
TAs25·C
POWER RATING
DERATING FACTOR
ABOVE TA = 25·C
OW
1025mW
8.2mWrC
656mW
N
1150mW
9.2mWrC
736mW
1ExAs
TA=70·C
POWER RATING
~
INSIRUMENIS
POST OFFICE BOX 655303 • DAliA$, TEXAS 75265
2-55
LT1039
TRIPLE EIA·232 LINE TRANSCEIVER
SUS1058 - D3627, FEBRUARY 1991 - REVISED JANUARY 1992
recommended operating conditions
MIN
NOM
MAX
Supply voltage; VOO+
5
12
15
V
Supply voltage, VOO-
-5
-12
-15
V
4.75
5
5.25
V
SUpply voltage, VCC
2
High-level Input voltage, VIH (see Note 3)
Low-Ievel input voltage, VIL (see Note 3)
V
O.B
V
70
·C
0
Operallng free-air temperature, TA
UNIT
NOTE 3: VIH and VIL specifications apply only for inputs OliN to 031N.
DRIVER SECTION
electrical characteristicsoverrecommended operating free-air temperature range, Voo± = ±11.4 V
to ±12.6 V, ON/OFF at 2.5 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYpt
MAX
VOM+
Maximum positive peak output
voltage swing
VOM-
Maximum negative peak output
voltage swing
IIH
High-level input current
VI>:2V
1
20
IlL
Low-Ievellnput current
VlsO.BV
5
20
VOO+-0.4
V
VOO-+l.0
VOO-+1.5
VI=O
15
VI=5V
BO
Sourcing current,
VO=O
5
15
Sinking current,
VO=O
-5
-15
ONIOFF aI 0.4 V
Off-stale output current
VO=",1BV,
ICC
Supply current
10=0
ICC(off)
Off-stale supply current
O.NIOFF aI 0.4 V
SR
SleWrale
RL=3kg,
VI=O,
CL=51 pF
tAil typical values are alVOO", = ",12 V, TA= 25·C.
2-66
VOO+-0.4
Load = 3 kg to GNO
10Z
UNIT
1ExAs,lf
INSIRUMENTS
POST OFFICE BOX 655303 • DAUAS, TEXAS 75265
4
J1A
J1A
",10
",200
J1A
4
B
mA
1
100
J1A
15
30
V/IJB
LT1039
TRIPLE EIA-232 LINE TRANSCEIVER
SU.81058- 03621, FEBRUARY 1991 - REVISED JANUARY 1992
RECEIVER SECTION
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature, ON/OFF at 2.5 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VrVr+
Positive-golng Input Ihreshold voltage
Vhvs
Hysteresis
VOL
Low-level output voltage
10=-1.6mA
VOH
High-level output vollage
10 = 160 (.IA
Negative-going Input Ihreshold vollage
MIN
TYpt
0.5
1.3
1.7
I
•
f
5D-
~
6
VCC=5V
VCC=4.5V
4
0
Output High
i
2
o
RL=3kQ
-2
Output Low
I
-4
I
E
~
-6
'T
.c
-25
0
25
0.4
Il
J
~
VCC=5.5V
50
75
100
0.1
-60
125
I
/
lI
...
-10
-50
,
a.
VCC=5V
VCC=4.5V
-8
/
0
f!
11•
i
4
::I
Vr30~
-25
TA - Free-Air Temperature - ·C
0
/
/
Vr-~V
I II
25
50
75
100
125
TA - Free-Air Temperature - ·C
Figure 1
,
Figure 2
POSITIVE-GOING AND NEGATIVE-GOING
RECEIVER INPUT THRESHOLD VOLTAGE
RECEIVER SOURCE CURRENT
AND SINK CURRENT
va
va
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
3
100
2.75
>I
&
!
2.5
~
2.25
'0
2
'1:1
j
F
I
1.5
I
1.25
~
C
~
::I
....V
VT+
1.75
5
a.
S
r-
~
......V
./
_V-
i-""""
I"'"
IOLS (sinking)
10
0
~
c
iii
.... "
IOHS (sourcing)
is
~ VT-
~
S
UI
0.75
0.5
-50
-25
0
25
50
75
100
TA - Fr_Alr Tempersture _·C
125
0.1
-50
-25
0
25
50
75
100
125
TA - Free-Air Temperature - ·C
Figure 3
Figure 4
t Data at high and low temperatures are applicable only wtthin the rated operating free·air temperature ranges ofthe various devices.
1ExAs
..If
INSIRUMENTS
POST OFFICE BOX 655303 • DAUAS. TEXAS 75265
2~3
LT1080, LT1081
ADVANCED LOW-POWER
s-v DUAL EIA-232 DRIVER/RECEIVERS
SUS05OA- 03121. SEPTEMBER 1989- REVISED FEBRUARY 1991
TYPICAL CHARACTERISTICSt
SUPPLY OUTPUT VOLTAGE
SUPPLY OUTPUT VOLTAGE
10
8
va
va
OUTPUT CURRENT
ELAPSED TIME
-
10
v~ +
r-
Loaded to Vs _ -
8
Vs+
t.dadad to GND
6
>I
6
>I
4
III
f
&
!
2
~
VCC-SV
5Q.
5
5Q.
5
0
0
-2
t
-4
Q.
::s
III
Loedad to VS+
-6
-8
-10
o
I
l~ t::-
2
4
-I
t:
-4
VCC=5V
C1-C4 .. 1...,. RL 4.7 kCl
\
=
I'
VS_
III
-6
VS-
-8
-10
6
8 10 12 14 16
10 - Output Current- mA
18
20
o
1 1.2 1.4 1.6 1.8
t-Tlme-ma
ONJOFF INPUT VOLTAGE·
va
va
INPUT VOLTAGE
FREE-AIR TEMPERATURE
40
5
35
4.5
/
30
25
/~
I
I
20
0
15
i
10
.5
>
I
i
=
~
5Q.
.5
/
~
0
I
:;-
~
IV
-5
o
3.5
III
/'
5
-10
4
/
/
I
:-
3
2.5
.......... ~in On Voltage
2
........ -..........
1.5
r- t--
---
~
Max Off Voltage
0.5
2
3
VI-Input Voltage - V
4
5
o
-50
-25
Figure 7
r-r-
0
25
50
75
100
TA - Free-Air Temperature - ·C
FigureS
t Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
2-64 .
2
Figure 6
ONJOFF INPUT CURRENT
:1-
"- ....... r--
0.2 0.4 0.6 0.8
Figure 5
VCC=5V
Rl=3kC
Cl=51 pF
TA = 25°C
I'
/
o
I
a
t::s
5
o
-5
0.5
1
1.5
2
2.5
3
3.5
4
4.5
o
0.5
1
1.5
2
2.5
3
3.5
4
4.5
t-TJme-ms
t-Tlme-ms
Figure 11
Figure 12
t Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
1ExAs,lf
INSIRUMENfS
POST OFFICE BOX 656303 • DAUAS, TEXAS 7!!2e5
2~5
LT1080,LT1081
ADVANCED LOW-POWER
S-V DUAL EIA-232 DRIVER/RECEIVERS
SLLS05OA- 03121, SEPTEMBER 1989 - REVISED FEBRUARY 1991
APPLICATION INFORMATION
The driver output stage of the LT1080 offers significantly improved protection over older bipolar and CMOS designs
(see Figures 13 and 14). In addition to limiting current, the driver output can be externally forced to:3O V without
damage, excessive current flow, or supply disruption. Some drivers have diodes connected between the outputs and
the supplies, allowing externally applied voltages to cause excessive supply voltage to deVelop.
v+
~
-t>o- JL~30V
.
output Can Be
Externally Forced
W1thSomeDrlvers;
Externally Applied
Voltage Can Force
the Supplies
vFigure 13. LT10801LT1081 Driver
Figure 14. Older EIA-232 Drivers
,and CMOS Drivers
Placing the LT1080 in the shutdown mode (pin 18 low) puts both the driver and receiver outputs in a high-impedance
state. This allows for bus operation and transceiver applications (see Figures 15-17). The shutdown mode also drops
input supply current (Vee> to near zero for power-conscious systems.
Logic
ON/OFF
(channel Select)
Input
Inverter
Figure 15. Sharing a Receiver Une
2-66
POST OFFICE BOX _
Figure 16. Sharing a Transmitter Une
• DALLAS, TEXAS 75265
LT1080, LT1081
ADVANCED LOW-POWER
S-V DUALEIA-232 DRIVER/RECEIVERS
SlLS05OA-03121, SEPTEMBER 1989-REVISED FEBRUARY 1991
APPLICATION INFORMATION
LT1080
Driver 1
Logic
Tranemlt/Recelve~"""'-I
X>--_.-
Une
EIA-232
Tranamlt/Receive
Une
LT1080
Receiver 2
logic
Inverter
ON/OFF ~t--I
(transmit/receive)
Figure 17. Transceiver
To protect against receiver input overloads in excess of :1:30 V, a voltage clamp can be placed on the data line and
still maintain EIA-232 compatibility (see Figure 18).
When driving CMOS logic from a receiver that will be used in the shutdown mode and when there is no other active
receiver on the line, a 51-kQ resistor can be placed from the logic input to Vee to force a definite logic level when the
receiver output is in a high-impedance state (see Figure 19).
The generated driver supplies (Vs+ and Vs-) may be used to power external circuitry such as other EIA-232 drivers
or operational amplifiers (see Figure 20). They should be loaded with care, since excessive loading can cause the
generated supply voltages to drop, causing the EIA-232 driver output voltages to fall below EIA-232 requirements.
See Figure 5 for a comparison of generated supply voltage versus supply current.
Vee
1 kQ
(eaeNoteA)
EIA-232 ---'W"v--'~"""''''''
Input
30V
LT1080
Receiver
logic
Output
51 kQ
(see Note A)
EIA-232
Input
30V
ON/OFF
NOTE A: A PTe thermistor will allow continuous overload of
greater than '" 100 V.
Figure 18. Input Overload Protection
NOTE A: Forces logic input state when VI is low.
Figure 19. Forcing a Definite Logic Level
POST OFFICE BOX 655303 • DAUAS. TEXAS 75265
2-e7
LT1080, LT1081
ADVANCED LOW-POWER
S-V DUAL EIA-232 DRIVER/RECEIVERS
SLl.S05OA- 03121. SEPTEMBER 1989- REVISED FEBRUARY 1991
APPLICATION INFORMATION
LT1080
External
OpAmp
Figure 20, Powering External Circuitry
5V
sh~n-~-;==========~--------~~------~============~l
18
LT1080
17
18
LT1039 _
17
VCC .......- - - -.....- - - - - - 1 VCC
ON/OFF
TTL In --t--_t x ) - - - - t - - EIA-232 Out
TTL In --1---1
TTL Out --I----iOC
x>-....:-....:--t--
H~--I-
EIA-232 Out
EIA·232In
ON/OFF
TTL In -'--t----t
.x....---+--
EIA-232 Out
TTL In -t----t
.x....---'--+--
EIA·232 Out
TTL In -+---1
XJ---+--
EIA·232 Out
TTL Out -t--o< H " " - - - + - - EIA-232ln
ake
TTL Out --I----iOC
C1t
1 t#
+
2
4
a
1 t#
+
6
30ke
H~--I-
EIA·232 In
TTL Out -t--o< H....---+-- EIA-232ln
5kD
C1+
30kD
TTL Out -t--o< H....---+-- EIA·232ln
C1-
30kD
C2+
C2-
7
GND
9
Vs_I---+-----~.--_t
16
VS-
GND
~------e--~--~-----~
10
t In applications In which a separate second positive supply is available (such as 5 V and 12 V). the 12-V supply may be connected to pin 2 end
C1 deleted. The power circuitry win then Invert the12-V supply. The 5-V supply is stili needed to power the biasing circuitry and receivers.
Figure 21. Supporting an LT1039 (Triple Driver/Receiver)
2-68
POST OFFICE BOX 65S303 • DAUAS. TEXAS 75265
LT1080, LT1081
ADVANCED LOW-POWER
S-V DUAL EIA-232 DRIVER/RECEIVERS
SLLS05OA- 03121. SEPTEMBER 1989 - REVISED FEBRUARY 1991
APPLICATION INFORMATION
12Vlnput t
LT1080
2
17
4
5
+
11Af
TTL In
TTL In
TTL Out
6
5Vlnput
3
7
C2+
VO=-12V
+T 11Af
C2-
12
15
11
8
13
14
EIA-232 OUt
EIA-232 OUt
EIA-232 In
5kO
TTL Out
10
9
EIA-232 In
5kO
ON/OFF
18
-=-
16
-=t C1 + used on LT1081
Figure 22. Operating With 5 V and 12 V
TEXAS
~
INSIRUMENIS
POST OFACE BOX 655303 • DAUAS. TEXAS 75265
2-69
2-70
MAX232, MAX2321
DUAL EIA·232 DRIVER/RECEIVER
SLLS047C - 031
•
•
•
•
•
•
Operates With Single 5-V Power Supply
UnBICMOSTM Process Technology
Two Drivers and Two Receivers
±3O-V Input Levels
Low Supply Current ••• 8 rnA Typ
Meets ANSI/EIA-232-D-1986 Specifications
(Revision of EIA Standard RS-232-C)
• Designed to be Interchangeable WHh
Maxim MAX232
• Applications
EIA-232 Interface
Battery-Powered Systems
Terminals
Modems
Computers
• ESO Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015
0, OW, OR.N PACKAGE
(TOP VIEW)
C1+
16
15
14
13
12
11
10
9
C2+
C2-
VsT20UT
R2IN
7
Vec
GND
T10UT
R11N
R10UT
T1IN
T2IN
R20UT
logic symbol t
5V
15
C1+
C1C2+
description
The MAX232 is a dual driver/receiver that
includes a capacitive voltage generator to supply
EIA-232 voltage levels from a single 5-V supply.
Each receiver converts EIA-232 inputs to 5-V
TTLJCMOS levels. These receivers have a typical
threshold of 1.3 V and a typical hysteresis of
0.5 V, and can accept ±30-V inputs. Each driver
converts TTLJCMOS input levels into EIA-232
levels. The driver, receiver, and voltage-generator
functions are available as cells in the Texas
Instruments LinASICTM library.
FEBRUARY 1988 - REVISED MARCH 1993
02T1IN
T2IN
3
4
5
C1+
C1C2+
VCC
2VCC-1.5V
-2VCC+1.5V
2
6
Vs+
Vs-
C2-
11
I>
10
I>
14
T10UT
7
T20UT
R10UT
R11N
R20UT
R21N
t This symbol Is in accordance with ANSI/IEEE Std 91-1984 and
The MAX232 is characterized for operation from
O°C to 70°C. The MAX2321 is characterized for
operation from -40°C to 85°C.
IEC Publication 617-12.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Input supply voltage range, VCC (see Note 1) .......................................... - 0.3 V to 6 V
Positive output supply voltage range, Vs+ ....................................... Vcc - 0.3 V to 15 V
Negative output supply voltage range, Vs- .......................................... -0.3 V to -15 V
Input voltage range: Driver ................................................. -0.3 V to Vcc + 0.3 V
Receiver ............................................................. ±30 V
Output voltage range: T10UT, T20UT ................................... Vs_-0.3 Vto Vs+ + 0.3 V
R10UT, R20UT ...................................... -0.3 Vto Vee + 0.3 V
Short-circuit duration: T10UT, T20UT ................................................... unlimited
Operating free-air temperature range: MAX232 ........................................ O°C to 70°C
MAX2321 ...................................... -40°C to 85°C
Storage temperature range ............................................•.......... -65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds .............................. 260°C
NOTE 1: Ail voltage values are with respect to network ground terminal.
UnASIC and UnBiCMOS lire trademarks of Texas Instruments Incorporated.
1ExAs
..If
copyright@ 1993. Texas Instruments Incorporated
INSIRUMENIS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
2-71
MAX232, MAX2321 .
DUAL EIA·232 DRIVER/RECEIVER
Sll.S047C - 03120, FEBRUARY 1989 - REVISED MARCH 1993
recommended operating conditions
MIN
4.5
2
Supply voltage, VCC
High-level Input voltage, VIH (T1IN,T2IN)
Low-level Input voltage, VIL (T11N, T21N)
Receiver input voltage, R11N, R21N
Operating free-air temPerature,TA
NOM
5
MAX
5.5
0.8
,.30
0
70
UNIT
V
V
V
V
°c
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature range (unless otherwise noted)
TEST CONDITIONS
PARAMETER
VOH
High-level output voltage
VOL
Low-level output voltage:l:
Vr+
Vr-
T10UT, T20UT
RL = 3 kg to GND
R10UT, R20UT
10H=-1 rnA
7
-7
RL = 3 kg to GND
R10UT, R20UT
10L = 3.2 rnA
Receiver posltlve-going input
threshold voltage
R11N, R21N
VCC=SV,
TA = 25°C
Receiver negative-going input
threshold voltage
R1IN, R21N
VCC=SV,
TA = 25°C
Vhys
Input hysteresis
R1IN,R2IN
VCC=SV
I'j
Receiver Input resistance
R11N, R2IN
VCC=S,
TA = 25°C
ro
10S§
Output resistance
T1 OUT, T20UT
Vs+=VS-=O,
VO=,.2V
ShQrt-circult output current
T10UT, T20UT
VCC = 5.5 V,
VO=O
liS
Short-circuit input current
T1IN, T21N
MAX
UNIT
V
-5
0.4
1.7
2.4
0.8
1.2
0.2
0.5
1
3
5
7
V
V
kg.
0
,.10
All outputs open,
V
V
300
VI=O
VCC=s.SV,
TA=2SoC
Supply current
TVPt
5
3.5
T10UT, T20UT
ICC
MIN
8
rnA
200
JlA
10
rnA
t All tyPical values are at VCC = 5 V, TA = 25°C.
.
:I: The algebraic convention, in which the least positive (most negative) value is deSignated minimum, Is used In this data sheet for logic voltage
levels only.
§Not more than one output should be shorted at a time.
switching characteristics, Vee
PARAMETER
=5 V, TA =25°C
TEST CONDITIONS
MIN
TVP
MAX
UNIT
tPLH(R)
Receiver propagation delay time,
low-to-hlgh-Ievel output
See Figure 2
500
ns
tPHL(R)
Receiver propagation delay time,
hlgh-to-Iow-Ievel output
See Figure 2
500
ns
SR
Driver slew rate
RL = 3 koto 7 kg,
SR(tr)
Driver transition region slew rate
See Figure 4
See Figure 3
1ExAs . "
INSTRIJMENTS
2-72
POST OFF1Ce sox 655303 • DAUAS. TEXAS 75265
30
3
VI!1S
VIlIS
MAX232, MAX2321
DUAL EIA·232 DRIVER/RECEIVER
SLLS047C - 03120. FEBRUARY 1989- REVISED MARCH 1993
APPLICATION INFORMATION
SV
~
1
:::;:::
C1+
3
From CMOS or TTL
To CMOS or TTL
{
{
8.5V
2VCC-1.5V
6
-2VCC+1.SV
C2+
5
~1 I1F
2
C1-
4
~
16
VCC
+
C2-
11
"-
I>
10
14
7
I>
12
13
.IT
9
8
.IT
OV
:;!;:
-8.5 V
1 ....
E1A-232 0 utput
E1A-232 0 utput
E1A-232 Input
E1A-232 Input
f,s
GND
Figure 1. Typical Operating Circuit
PARAMETER MEASUREMENT INFORMATION
VCC
R10UT
R11N
or
Pulse
Generator
CseeNoteA)
C_NoteC)
R2IN
CL=50pF
Ceee Note B)
T
TEST CIRCUIT
"10ns .....1 ~
~
1
i
J{:
~
Input_............
10%
9O%~11-------3V
5O%~1
50%
5OOn.
lJ>tiL --l+---+I
1
Output
'+-,,10n.
11
10%
IIOo...;..;.;-----OV
~tpLH
1
1.5v\k
1.5V
y,.--_-_-_::
WAVEFORMS
NOTES: A. The pulse generator has the following characteristics:
B. CL includes probe and jig capackance.
C. All diodes are 1N3064 or equivalent.
Zo = 50 Q. duty cycle" 50%.
Figure 2. Receiver Test Circuit and Waveforms for tpHL and tpLH Measurement
IN~
POST OFFICE BOX 655303 • DALlAS, TEXAS 75265
2-73
MAX232, MAX2321
DUALEIA·232 DRIVER/RECEIVER
Su.s047C - 03120, FEBRUARY 1989 - REVISED MARCH 1993
PARAMETER MEASUREMENT INFORMATION
T1IN or
T2IN
Pulse
Generator
(aeeNoteA)
T1OUTor
T20UT
~~---e----~~------ Output
E~~
T
CL=10pF
(see Note B)
TEST CIRCUIT
i-'
~
,,10n8
~
I+.90%
Input
10%
'50%
,
14------
,
90%
~+--------- 3V
50%',
~I
tpLH
i'T9O%
.
VOH
10%~!
-r-------- VOL
-.I
i+-.
0.8 (VOH - VOL)
'rLH
SR -
OV
. ,
,
,
1¥..
trHL -+I
10%
5!.1S---.I
tPHL4
Output
i+-,,10ns
or
I+-trLH
0.8 (VOL - V OH)
'rHL
WAVEFORMS
NOTES: A The pulse generator has the following characteristics: Zo = 50 0. duty cycle" 50%.
B. CL Includes probe and jig capacHance.
Figure 3. Driver Test Circuit and Waveforms for tpHL and tpLH Measurement (5-JA.S Inp,ut)
Pulse
Generator
(_NoteA)
>0----....-----411------- E~·232
Output
3kC
Input
"0M}
10%
r_
I
CL =2.5 nF
TEST CIRCUIT
..:i ~ .10M
)j 1.5V
1.5;1\:,....;,10%.;...;.;.._ _ __
~20!.IS--+I
tr~L-.I I+-
,,
Output
."'1
, 'I+- trLH
----3~V~\. ~i TIt"~3~V--- VOH
-3 V '\;,..
____
-.;:::3,.:.V..J-L - - - - SR =
VOL
6V
tTHL or 'rLH
WAVEFORMS
NOTES: A. The pulse generator has the following characteristics: Zo = 50 C, duty cycle" 50%.
Figure 4. Test Circuit and Waveforms for trHL and tTLH Measurement (20-JA.S .Input)
2-74
1ExAs'"
INSIRUMENIS
POST OFFICE BOX 655303 • DAUAS, TEXAS 75265
MC3450, MC3452, MC3550, MC3552
QUAD DIFFERENTIAL LINE RECEIVERS
SUS012B-
• Four Independent Receivers With Common
Enable Input
•
•
•
•
•
FEBRUARY 1986 - REVISED FEBRUARY 1993
MC3450, MC3452 ••• 0 OR N PACKAGE
MC3550, MC3552 ••• J PACKAGE
(TOP VIEW)
High Input Sensitivity ••• 25 mV Max
High Input Impedance
MC3450 and MC3550 Have 3-State Outputs
MC3452 Has Open-Collector Outputs
Glitch-Free Power-Up/Power-Down
Operation
16
15
14
13
2A
6
GND
The MC3450, MC3550, MC3452, and MC3552
are quad differential line receivers designed for
use in balanced and unbalanced digital data
transmission. The MC34/3550 and MC34/3552
are the same except that the MC3450 and
MC3550 have 3-state outputs whereas the
MC3452 and MC3552 have open-collector
outputs, which permit the wire-AND function with
similar output devices. The 3-state and opencollector outputs permit connection directly to a
bus-organized system.
46
4A
4Y
Vcc3Y
3A
9 36
26
description
12
11
10
Vcc+
MC3550, MC3552 ••• FK PACKAGE
(TOP VIEW)
1Y
EN
NC
2Y
2A
The MC3450, MC3550, MC3452, and MC3550
are deSigned for optimum performance when
used with either the MC3453 or MC3553 quad
differential line driver or SN75109A, SN75110A,
and SN75112 dual differential drivers.
4
5
6
7
8
1 2019
18
17
16
15
14
9 10 11 12 13
3 2
4A
4Y
NC
VCC3Y
NC-No internal connection
The MC3450 and MC3452 are characterized for
operation from O°C to 70°C. The MC3550 and
MC3552 are characterized for operation over the
full military tempe~ature range of -55°C
to 125°C.
THE MC3452 IS NOT
RECOMMENDED FOR NEW DESIGN
FUNCTION TABLE
DIFFERENTIAL INPUTS
A-B
ENABLE
EN
VI02: 25 mV
-25 mV
3
'i1
5
15
1Y
18
2A
2Y
"
11
2B
3A
3Y
~
14
1A
13
"
3B
4A
4Y
48
4
2
1
7
9
15
2
3
2A
28
3A
3B
6
1Y
5
7
2Y
10
11
3Y
9
14
4A
15
48
13
4Y
1ExAs ."
2-76
INSIRUMENTS
POST OFFICE BOX 655303
0,
DALlAs. TEXAS 75265
]
t>
~
3
5
.....
11
~
14
4
1B
~
10
logic diagram (positive logic)
1A
~
6
t These symbols are in accordance wkh ANSVIEEE SId 91-1984 and lEe Publication 617-12.
6
~EN
13
"
1Y
2Y
3Y
4Y
MC3450, MC3452, MC3550, MC3552
QUAD DIFFERENTIAL LINE RECEIVERS
SLLS012B - 03006; FEBRUARY 1986 - REVISED FEBRUARY 1993
schematics of inputs and outputs
VCC+--~'----
1 kO
NOM
Input
TYPICAL OF MC3450
OUTPUT
EQUIVALENT OF
ENABLE INPUT
EQUIVALENT OF
AORBINPUT
TYPICAL OF MC3452
OUTPUT
- - - - - - - - -....- VCC
3kO
NOM
1400
NOM
Output
Input
Output
2000
VCC-·-+-~~~""'-
NOM
VCC_·-~t-+-
__
'---+--GND
GND-.....- - - - -
---41---..--.....- GND
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vcc+ (see Note 1) ............................................................ 7 V
Supply voltage, Vcc- ..................................................................... -7 V
Differential input voltage (see Note 2) ........................................................ :1:6 V
Common-mode input voltage (see Note 3) ................................................... :1:5 V
Enable input voltage ....................................................................... 5.5 V
Continuous total dissipation ............................................. See DisSipation Rating Table
Operating free-air temperature range .................................................. O°C to 70°C
Storage temperature range ....................................................... -65°C to 150°C
Case temperature for 60 seconds: FK package ..................................... .'........ 260°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: D or N package ................ 260°C
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: J package ..................... 300°C
NOTES: 1. All vottage values, except differential Input voltage, are with respect to network ground terminal.
2. Differential Input vottage is measured at the noninverting input wfth respect to the corresponding inverting input.
3. Common-mode input vottage is the average of the vottages at the A and B inputs.
DISSIPATION RATING TABLE
PACKAGE
TAs25°C
POWER RATING
OPERATING FACTOR
ABOVE TA = 25°C
TA=70°C
POWER RATING
TA=125°C
POWER RATING
0
950mW
7.6mW/"C
608mW
FK
1375mW
11.0mW/"C
880mW
275mW
J
1375mW
11.0mW/"C
880mW
275mW
N
1150mW
9.2mW/"C
736mW
1ExAs
,If
INSIRUMENTS
POST OFFICE BOX 655303 • OAUAS. TEXAS 75265
2-77
MC3450, MC3452, MC3550, MC3552
QUAD DIFFERENTIAL LINE RECEIVERS
SLLS012B- D3OO6, FEBRUARY 1986 - REVISED FEBRUARY 1993
recommended operating conditions
MIN
SupplyvoHage, VCC+
SupplyvoRage, VCC-
TA",25°C
4.5
TA < 25°C
4.75
NOM
5
5,
MAX
5.5
5.5
TA"'25°C
-4.5
-5
-5.5
TA < 25°C
-4.75
-5
-5.5
High-level enable Input voHage, VIH
2
Low-Ievel enable Input voltage, VIL
Low-level output current, IOL
UNIT
V
V
V
0.8
V
-16
mA
Oifferential input voltage, VIO (see Note 4)
-5t
5
V
Common-mode Input voltage, V'C (see Note 4)
-3t
3
V
Input voltage range, any different Input to GNO
V
Operating free-alr temperature, TA
-5t
3
I MC3450, MC3452
0
70
MC3550, MC3552
-55
125
°c
...
t The algebrBlc convention, In which the less pOSitive (more negative) limit IS designated minimum, Is used in thiS data sheet for common-mode
Input voRage.
NOTE 4: The recommendeil combinations of input voltages fall within the shaded area of Figure, 1.
RECOMMENDED COMBINATIONS OF INPUT VOLTAGES
>I
J
~
~o
..
-
c(
'!i a..
.5 - 41---fo-5 -4 -3 -2 -1
0
1
2
3
Input B to GNO Voltage - V
Figure 1
2-78
1ExAs'"
INSTRlJMENTS
POST OFFICE BOX _
• DAUAS, TEXAS 75265
MC3450, MC3452, MC3550, MC3552
QUAD DIFFERENTIAL LINE RECEIVERS
Su.s012B - 03006. FEBRUARY 1986 - REVISED FEBRUARY 1993
electrical characteristics over recommended operating free-air temperature range,
(unless otherwise noted)
PARAMETER
TEST CONDITIONS
VOH
High-level output voHage
VOL
Low-level output voltage
10H
High-level output current
VCC .. = .. 4.75 V, VIO=25mV,
EN at 0.8 V.
10H = - 400 IIA
VIC =-3 Vto 3V
MC3450, MC3550
MIN
TYpt
Vcc:!: =MAX
MC3452, MC3SS2
MAX
MIN
TYpt
MAX
UNIT
V
2.4
~C .. = .. 4.75 V,
High-level
input current
IIH
VIO=-25mV.
ENat2V.
IOL=16mA,
VIC = -3 V to 3 V
0.5
VCC .. = .. 4.75 V, VOH = 5.25 V
0.5
V
250
IIA
A inputs
VIO=-2V
30
75
30
75
B inputs
VIO=-2V
30
75
30
75
EN
VIH=2.4V
40
40
IIA
VIH = 5.25 V
1
1
rnA
A inputs
VIO=2V
-10
-10
B inputs
VID = 2V
-10
-10
EN
VIL=0.4V
-1.6
-1.6
Vo =2.4V
40
IlL
Low-level
Input current
10Z
High-impedance state
output current
lOS
Short-circuit output current;
ICCH+
Supply 'current from VCC +.
outputs high
ICCH-
Supply current from VCC-.
outputs high
IIA
VID=25mV.
ENatO.8V
VO=O.
A inputs at GNO.
ENat3V
B inputs at 3 V.
-18
rnA
IIA
-40
VO=0.4V
IIA
mA
-70
60
60
rnA
-30
-30
rnA
t All typical values are at VCC+ = 5 V. VCC- = -5 V. TA = 25°C.
; Not more than one output should be shorted at a time.
switching characteristics, VCC± - ±5 V, TA =25°C
TO
PARAMETER
FROM
(INPUT)
(OUTPUT)
tpLH
AandB
y
tpHL
AandB
Y
tpZH
EN
y
tpZL
EN
y
tpHZ
tpLZ
I
EN
y
EN
y
TEST
CONDITIONS
CL= 50pF.
See Figure 2
CL=15pF.
See Figure 2
CL= 50pF.
See Figure 2
CL= 15pF.
See Figure 2
CL=50pF.
See Figure 2
CL= 15pF.
See Figure 3
MC3452, MC3552
MC3450,MC3550
MIN
TYpt
MAX
17
25
17
MIN
TYpt
MAX
19
25
19
25
25
21
UNIT
ns
ns
ns
27
18
ns
29
tpLH
EN
y
CL=15pF.
See Figure 4
25
ns
tpHL
EN
y
CL= 15pF.
See Figure 4
25
ns
t All typical values are at VCC+ = 5 V. VCC- = -5 V. TA = 25°C.
1ExAs . "
INSIRUMENTS
POST OFFICE sox 655303 • DAllAS. TEXAS 75265
2-79
MC3450, MC3452, MC3550, MC3552
QUAD DIFFERENTIAL LINE RECEIVERS
Su..sol2B - D3OO6, FEBRUARY 1988 - REVISED FEBRUARY 1\193
PARAMETER MEASUREMENT INFORMATION
5V
Output
6V
.~
3900
1500
ForMC34&2
orMC3652
t---"100mV
'-----~
,
For MC3450 or MC3552
(see Note C)
TEST CIRCUIT
Input--'100mv
I
I
tpLH~
OV
tpHL~
~
1.5V
1.5V
I
Output
t:~V-- 200mV
-t---VOH
VOL
VOLTAGE WAVEFORMS
NO:reS: A. The Input pulse Is supplied by a ganerator having the following characteristics: PRR os 1 MHz, dilly cycle
B. CL includes probe and jig capacitance.
C. All diodes are 1N916 or equivalent.
Figure 2. Test Circuit and VoHage Waveforms
1ExAs ..,
2-aO
INSIRUMENTS
POST OFFICE BOX 655303 • DAllAS, TEXAS 75265
=50%, Ir os 6 ns, tf os 6 ns.
MC3450, MC3452, MC3550, MC3552
QUAD DIFFERENTIAL LINE RECEIVERS
SLLS012B - 03006, FEBRUARY 1986 - REVISED FEBRUARY 1993
PARAMETER MEASUREMENT INFORMATION
tpZH
tPZL
tpHZ
tpLZ
A
l00mV
GND
l00mV
GND
B
Sl
Open
Closed
GND
l00mV
GND
100mV
Closed
Closed
Output
S2
Closed
Open
Closed
Closed
Sl
3900
(see Note C)
1 kO
Generator
(see Note A)
0 - - 5V
500
TEST CIRCUIT
~:v-----::
~~------3V
EN
I
I
tPZH~
I
--It:___
Output _ _ _ _
VOH
ov
0_
I
~:V----"
"'·----VOL
3V
i~v_____ .v
EN
tpHZ
---.t I+--
-----i=~~~~
~-l'5V
VOH
Output
.
OV
tpZL~
EN
tpLZ
i------
3V
'V
----*-'
~_1.5V
---L._~~::_
.
Output
VOL
VOLTAGE WAVEFORMS
NOTES: A The input pulse is supplied by a generator having the following characteristics: PRR ,,1 MHz, duty cycle
B. CL includes probe and jig capackance.
C. All diodes are 1 N916 or equivalent.
=50%, tr "
6 ns, tf" 6 ns.
Figure 3. MC3450 and MC3550 Test Circuit and Voltage Waveforms
POST OFFICE BOX 655303 • DAllAS, TEXAS 75265
2-81
MC3450, MC3452, MC3550, MC3552
QUAD DIFFERENTIAL LINE RECEIVERS
Su.80128 - D3OO6, FEBRUARY 1986 - REVISED FEBRUARY 1993
PARAMETER MEASUREMENT INFORMATION
6V
3900
~--~--.----
Ompm
Generator
(He Note A)
TEST CIRCUIT
3V
OV
I
tpLH --l+--+I
1
1'----'"'\
VOH
I
Outpm
VOL
VOLTAGE WAVEFORMS
NOTES: A. The Input pulse Is supplied by a generator having the following characteristics: PRR :< 1 MHz, duty cycle
B. CL includes probe and jig capackance.
Figure 4. MC3452 and MC3552 Test Circuit and Voltage Waveforms
1ExAs .."
INSIRUMENTS
2-82
POST OFFICE BOX 655303 • DAUAS. TEXAS 75265
=50%, tr :< 6 ns, tf:< 6 ns.
MC3453, MC3553
QUAD LINE DRIVERS WITH COMMON ENABLE
1986-REVISED
• Similar to a Dual Version of SN55/75110A
Une Driver
1993
D, J, OR N ••• PACKAGE
(TOP VIEW)
• Improved Stability Over Supply Voltage and
Temperature Ranges
VCC+
• Constant-Current Outputs
• High Output Impedance
• High Common-Mode Output Voltage Range
-3Vt010V
4A
4Y
4Z
3Z
3Y
2Y
ENABLE
6
2A
• Glitch-Free Power-UplPower-Down
Operation
3A
GND
• TTL-Input Compatibility
• Common-Enable Circuit
• Designed to Be Interchangeable With
Motorola MC3453 and Mllitary-TemperatureRange Version of MC3553
FKPACKAGE
(TOP VIEW)
+
~ ~
()
z?$
1Z
4
3 2 1 20 19
18
2Z
5
17
NC
6
16
NC
2Y
7
15
ENABLE
8
3Z
3Y
description
The MC3453 and MC3553 feature four line drivers
with a common-enable input. When the ENABLE
input is high, a constant output current is switched
between each pair of output terminals in response
to the logic level at that channel input. When the
ENABLE is low, all channel outputs are
nonconductive (transistors biased to cutoff). This
minimizes loading in party-line systems where a
large number of drivers share the same line.
()
14
9 10 1112 13
~O()
zz
Cl
4Y
4Z
1«
()C'?
?
NC-No Internal connection
The driver outputs have a common-mode voltage
range of -3 V to 10 V, allowing common-mode
voltages on the line without affecting driver
performance.
FUNCTION TABLE
All outputs should be maintained within the
recommended common-mode output voltage
range to ensure that the channels do not interact
with each other. To minimize power dissipation, all
unused outputs should be grounded.
ENABLE
INPUT
Z
Y
H
H
On
Off
L
H
L
L
Off
Off
Off
On
H
L
L
OUTPUT
CURRENT
LOGIC
INPUT
=low logiC level,
H
Off
Off
=high logiC level
All inputs are diode clamped and are designed to satisfy TTL-system requirements. The inputs are tested at 2 V
for high-logic-level input conditions and 0.8 V for low-logic-level input conditions. These tests ensure 400 mV
of noise margin when interfaced with Series 54f74 TTL.
The MC3453 is characterized for operation from O°C to 70°C. The MC3553 is characterized for operation over
the full military temperature range of -55°C to 125°C.
Copyright@ 1993, Texas Instruments Incorporated
1ExAs . "
INSIRUMENIS
POST OFFICE BOX _
• DAUAS. TEXAS 75l!65
2-83
MC3453, MC3553
, QUAD LINE DRIVERS WITH COMMON ENABLE
SLLS119A- D3OOO, FEBRUARY 1986 - REVISED FEBRUARY 1993
logic symbol t
ENABLE
1A
2A
3A
4A
logic diagram (positive logic)
6
ENABLE
I EN
l;'
I>
1
2
~
3
~
5
7
4
11
10
12
14
15
13
1Y
1A
1Z
1Y
1Z
2Y
2A
2Y
2Z
2Z
3Y
3Y
3A
3Z
3Z
4Y
4Y
4A
4Z
4Z
t This symbol is in accordance wHh ANSI/IEEE Std 91-1984 and
lEe Publication 617-12.
schematics of InpUts and outputs
EQUIVALENT OF EACH INPUT
TYPICAL OF ALL OUTPUTS
r--------
vcc+--------.-----
Output
--._-1
Input ....
' - - - - - - - - Output
vcc--+------~~----
---.--.----------VCC-
GND-*---
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vcc+ (see Note 1) ........................................................... 7 V
Supply voltage, VCC- ..................................................................... -7V
Input voltage (any input) ........ , ...........................................................5.5 V
Output voltage range (any output) .................................................... -5 V to 12 V
Continuous total dissipation ............................................. See Dissipation Rating Table
Operating free-air temperature range: MC3453 ...................................... , O°C to 70°C
MC3553 ................................... -55°C to 125°C
Storage temperatu're range .............................•......................... -65°C to 150°C
Case temperature for 60 seconds: FK package .............................................. 260°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: D or N package ............. . .. 260°C
Lead temperature 1,6 mm (1116 inch) from case for 60 seconds: J package ..................... 300·C
NOTE 1: All voltage values are with respect to network ground terminal.
1ExAs
2-84
.Jf
INSIRUMENIS
POST OFFICE BOX _
• DAUAS. TEXAS 75265
MC3453, MC3553
QUAD LINE DRIVERS WITH COMMON ENABLE
SLLS119A- 03000, FEBRUARY 1986- REVISED FEBRUARY 1993
DISSIPATION RAnNG TABLE
PACKAGE
OPERAnNG FACTOR
ABOVE TA = 25°C
TA:s25°C
POWERRAnNG
=
TA 70°C
POWER RATING
TA = 125°C
POWERRAnNG
0
950mW
7.6mW/"C
608mW
FK
1375mW
11.0mW/"C
880mW
275mW
J
1375mW
11.0mW/"C
880mW
275mW
N
1150mW
9.2mW/"C
736mW
recommended operating conditions
Supply voltage, VCC+
Supply voltage, VCC-
MIN
TYP
MAX
TA:025°C
4.5
5
5.5
TA < 25°C
4.75
5
5.5
TA:025°C
-4.5
-5
-5.5
TA<25°C
-4.75
-5
-5.5
UNIT
V
V
High-ievellnput voRage, V,H
2
5.5
V
Low-Ievellriput voltage, V,L
0
O.B
V
VOCR+
0
10
V
VOCR-
0
-3
V
MC3453
0
70
MC3553
-55
125
Common-mode output voRage range
Operating free-air temperature, TA
electrical characteristics over recommended operating free-air temperature range,
(unless otherwise noted)
PARAMETER
V,K
Input clamp voRage
10(on)
On-state output current
1010ffi
Off-state output current
"H
High-level input current
I,L
Low-level input current
TEST CONDInONSt
MIN
1,=-12mA
VCC+ = MAX
VCC-= MAX
VCC+ = MIN,
VCC-= MIN
Vcc+ = MIN,
VCC-= MIN,
Vcc: = MAX
MAX
UNIT
-0.9
-1.5
V
11
15
11
6.5
V, =VCC+ max
A inputs at 0.4 V
ICC-
Supply current from VCC-
A Inputs at 0.4 V
!AA
!AA
1
rnA
-1.6
rnA
ENABLEat2V
33
50
ENABLE at 0.4 V
33
50
ENABLEat2V
-68
-90
ENABLE at 0.4 V
-31
-40
..
t For condilJons shown as MIN or MAX, use the appropriate value specified under recommended operating condRions .
mA
40
100
VO=10V
V, = 0.4 V
Supply current from VCC+
.
TYP*
V, =2.4V
ICC+
°c
rnA
mA
*
All typical valuas are at VCC+ = 5 V, VCC- = -5 V, and TA = 25°C.
switching characteristics, VCC+
=5 V, VCC- =-5 V, RL =50 £"2, CL =40 pF, TA =25°C
PARAMETER
FROM
(lNPU1)
TO
(OUTPUT)
TEST
CONDInONS
MIN
TYP
MAX
UNIT
tpLH
Propagation delay time, low-ta-high level output
A
VorZ
9
15
' ns
tpHL
Propagation delay time, high-to-Iow level output
A
VorZ
7
15
ns
tpLH
Propagation delay time, low-to-high level output
ENABLE
VorZ
14
25
ns
tpHL
Propagation delay time, high-to-low level output
ENABLE
VorZ
15
25
ns
1ExAs'"
See Figure 1
INSIRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2-85
MC3453
QUADRUPLE LINE DRIVER WITH COMMON ENABLE
SLLS119- D3OOO, FEBUARY 1986- REVISED JULY 1990
PARAMETER MEASUREMENT INFORMATION
. - - - _ . - - . . . - - ' - - OLdputY
A Input - - - - - - - - ,
CL-40pF
Pulse
Generator
#1
D----._---...---Outputz
ENABLE - - - - - - - - ,
CL=40pF
Pulse
Generator
#2
TEST CIRCUIT
A Input
---I!~50%
-_.- I~~-I
rtw1~
I
I
II
I
.I I
~
I
I
I
50%
50% "
tw2
---.!.'
I
-JI~
____
I
I
\.--..!-tPLH
I
V
T
I
I'
I I
tpHL ~
50%
__ ::
I I
~tpHL·
-loft
~~.:-
50%
L..
I
I
I
,
I
'
I
50%
I I·
j
,------------------I4-*- tPLH
~
I
z
j
~IpHL
I
I
I
Output
!4-'.--
i
I I
tpLH~
output Y
''\l
~\"~
I
ENABLE
-----oV
on
oft
on
VOLTAGE WAVEFORMS
NOTES: A. The pulse generators have the fOllowing characteristics:
.
PRR s 500 kHz.
B. CL includes probe and jig capacitance.
Zo = 50 C,It = tf =10 .. 5 ns, tw1
Figure 1. Test Circuit and Voltage Waveforms
1ExAs
2-86
~
INSIRUMENTS
POST OFFICE &Ox 655303 • DALlAS, TEXAS 75265
= 200 ns, PRR s 1 MHz, tw2 = 1 iJS,
MC3486
QUAD DIFFERENTIAL LINE RECEIVER
WITH 3-STATE OUTPUTS
1980 - REV1SED FEBRUARY 1993
• Meets EIA Standards RS-422·A and
RS423-A and Federal Standards 1020
and 1030
•
•
•
•
D OR N PACKAGE
(TOP VIEW)
1B
3-State, TTL-Compatlble Outputs
Fast Transition Times
Operates From Single S·V Supply
Designed to Be Interchangeable With
Motorola MC3486
1,2EN
The MC3486 is a monolithic quad differential line
receiver designed to meet the specifications of
EIA Standards RS-422-A and RS-423-A and
Federal Standards 1020 and 1030. The MC3486
offers four independent differential-input line
receivers that have TTL-compatible outputs. The
outputs utilize 3-state circuitry to provide a highimpedance state at any output when the
appropriate output enable is at a low logic level.
1,2EN
1A
1B
2A
28
3,4EN
3A
The MC3486 is characterized for operation from
0°Ct070°C.
3B
4A
48
FUNCTION TABLE
(each receiver)
VID,,0.2V
H
H
H
?
VID,,-0.2V
H
L
4
~
~N
2
~
1
]
I>
3
V
6
5
7
I'.
12
9
I'.
14
]
I>
11
V
13
15
2Y
~
~N
10
1Y
I'.
3Y
4Y
and lEe Publication 617-12.
Y
-0.2V
1
'V
'V
1,2EN
2
3
6
7
5
1Y
2
1Z
1A
2Y
6
2Z
2A
3,4EN
3A
4A
12
,..I
~N
9
£>
'V
'V
15
10
11
14
13
3
5
1Y
1Z
2Y
2Z
3,4EN
3Y
3Z
10
4Y
3A
11
4Z
14
t This symbol is in accordance with ANSVIEEE Std 91-1984
4A
and lEe Publication 617-12.
13
3Y
3Z
4Y
4Z
Copyright ~ 1986. Texas Instruments Incorporated
1ExAs . "
INSIRUMENTS
POST.OFFrCE BOX 655303 • DALLAS. TEXAS 75265
2-a3
MC3487
QUAD DIFFERENTIAL LINE DRIVER
WITH 3-STATE OUTPUTS
SLLS098 - 02578. MAY 1980- REVISED SEPTEMBER 1988
FUNCTION TABLE
(each driver)
OUTPUTS
INPUT
OUTPUT
ENABLE
V
H
H
H
L
L
H
L
H
X
L
Z
High-impedance
H = TTL high level.
L = TTL low level.
High-Impedance
X = Irrelevant
schematics ot Inputs and outputs
EQUIVALENT OF EACH INPUT
TYPICAL OF ALL OUTPUTS
vcc
VCC - , - - - - . - - -
Input
90NOM
Output
.----t-..........-
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage. Vee (see Note 1) .............................................................. 8 V
Input voltage ............................................................................ 5.5 V
Continuous total power dissipation ................................ '. . . .. See Dissipation Rating Table
Operating free-air temperature range .................................................. O°C to 70°C
Storage temperature range ....................................................... -65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: J package ..................... 300°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: D or N package' ................ 260°C
NOTE 1: All vollage values. except differential output volJage. VOO. are with respect to the network ground terminal.
DISSIPATION RATlN'G TABLE
PACKAGE
TA:s25°C
POWER RATING
DERATING FACTOR
ABOVE TA 25°C
TA = 70°C
POWER RATING
608mW
=
0
950mW
7.6mW/"e
J
1025mW
8.2mW/"e
656mW
N
1150mW
9.2mW/"e
736mW
recommended operating conditions
Supply voltage. Vee
High-level input voltage. VIH
MIN
NOM
MAX
UNIT
4.75
5
5.25
V
0.8
V
70
°e
2
Low-level input voltage. VIL
Operating free-air temperature. TA
0
1ExAs ."
INS1RIJMENTS
.2-94
POST OFFICE BOX 655303 • DAUAS. TEXAS 75265
V
MC3487
QUAD DIFFERENTIAL LINE DRIVER
WITH 3-STATE OUTPUTS
Su..s098 - 02578, M,j\V 1980 - REVISED SEPTEMBER 1986
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
PARAMETER
MIN
TEST CONDITIONS
MAX
UNIT
-1.5
V
VIK
Input clamp voltage
II =-18mA
VOH
High-level output voltage
VIL=0.8V,
VIH=2V,
10H =-20 rnA
VOL
Low-level output voltage
VIL= 0.8 V,
VIH=2V,
10L= 48 rnA
!VoDI
Differential output voltage
RL= 100 0,
See Figure 1
AIVODI
Change in magnitude of
differential output voltage t
RL= 1000,
VOC
Common-mode output voltage*
AIVocl
Change in magnitude of
common-mode output voltage t
10
Output current with power off
VCC=O
10Z
High-impedance-state output current
Output enables at 0.8 V
II
Input current at maximum input voltage
VI =5.5V
100
IIH
High-level input current
VI=2.7V
50
0.5
V
See Figure 1
,.0.4
V
RL= 1000,
See Figure 1
3
V
RL=1OO0,
See Figure 1
,.0.4
V
IlL
Low-level input current
VI =0.5V
lOS
Short-circuit output current§
VI=2V
ICC
Supply current (all drivers)
V
2.5
2
100
VO=6V
-100
VO=-0.25V
VO=2.7V
100
VO=0.5V
-100
-40
Outputs disabled
Outputs enabled,
JAA
-400
JAA
JAA
JAA
-140
rnA
105
No load
JAA
85
rnA
t A IVODI and A IVocl are the changes In magnitude of VOD and VOC, respectively, that occur when the Input IS changed from a high level to
a low level.
* In EIA Standard RS-422-A, Voc, which is the average of the two output voltages with respect to ground, is called output offset voltage, VOS.
§ Only one output at a time should be shorted, and duration of the short circuit should not exceed one second.
switching characteristics over recommended range of operating free-air temperature, VCC =5 V
PARAMETER
TEST CONDITIONS
tpLH
Propagation delay time, low-to-hlgh level output
tpHL
Propagation delay time, high-ta-Iow level output
MIN
MAX
20
CL= 15 pF,
See Figure 2
20
CL=15pF,
See Figure 3
20
Skew
6
UNIT
ns
ns
ns
ns
ns
ttD
Differential-output transition time
tPZH
Output enable time to high level
30
tPZL
Output enable time to low level
30
ns
tpHZ
Output disable time from high level
25
ns
tpLZ
Output disable time from low level
30
ns
CL= 50 pF,
See Figure 4
PARAMETER MEASUREMENT INFORMATION
Figure 1. Differential and Common-Mode Output Voltages
1ExAs ."
INSIRUMENTS
POST OFFICE BOX 655303 • DAUJ\S, TEXAS 75265
2-95
MC3487
QUAD DIFFERENTIAL LINE DRIVER
WITH 3-STATE OUTPUTS
SUS098 - 02578. MAY 1980- REVISED SEPTEMBER 1986
PARAMETER MEASUREMENT INFORMATION
Inp':!1.5V
tp
LH
YOutput
Generator
(see Note A)
i'4
1.5V
t ------ ::
.'
~
14
tpHL
I ,...--t-I-""ct"
V
I
11.5V I 1 . 5 V \ . - - - - OH
,
. I
I
I.
VOL
I Skew -tt 14-1 I
-J
1 - Skew
I
I
I
~ tpHL--+j
\+- tpLH~
\1.5
ZOutput
TEST CIRCUIT
V
1.5V;C :::
VOLTAGE WAVEFORMS
~---3V
InputJ
\.....1
ov
1
-1
l-ITD
~
Generator
(see Note A)
3V
Output
CL-15pF
(see Note B)
I
90%
10%
TEST CIRCUIT
VOLTAGE WAVEFORMS
Figure 3. Test Circuit and Voltage Waveforms
5V
1:>-.........-*-.S_W
cr1
Oor3V
I
r:-~~~I~
I CL= 50PF
Generator
I- _ _ _ _ J'see Note B)
(see Note A)
J
200 g
(see Note C)
1 kg
-=-
50 g
TEST CIRCUIT
Output
Enable
Input
Output
, - - - 3V
Enable
Input 1.5V
OV
tPHZ-'~v
, ---oW S~~ Closed
Output
f"=I- ~~ ~IOsed
tpLZ ~ j4Output
~
~~
.
_ 1.5 V
SW1 Closed
SW2Closed
VOL
...f
OV
tP2l.1
3V
15V
•
\1
SW1 Closed
SW20pen
I 1.5 V
I
VOL
tpZH ~ ~
VOH
Output
. . ~W10pen
y 5W2 Closed
Output
- - ' I."
VOLTAGE WAVEFORMS
Figure 4. Driver Test Circuit and Voltage Waveforms
NOTES: A. The Input pulse is supplied by a generator having the following characteristics: Ir " 5 ns, If " 5 ns, PRR" 1 MHz, duty cycle = 50%.
Zo=50g.
B. CL includes probe and stray capacitance.
C. All diodes are 1N916 or 1N3064.
1ExAs
..If
INSIRUMENIS
2~6
POST OFFICE BOX 655303 • OAUAS. TEXAS 75265
SN75ALS053
QUAD FUTUREBUS TRANSCEIVER
SEPTEMBER 1989
•
•
•
•
•
•
•
•
•
•
•
•
High-Speed Quad Transceiver
Fully Compatible With IEEE
Std. 896.1 - 1987 Futurebus Requirements
Drives Load Impedances as Low as 10 g
High-Speed Advanced Low-Power Schottky
Circuits
Low Power Dissipation ••• 81 mW Max per
Channel
High-Impedance PNP Inputs
BTL1M LogiC Leve11-V Bus Swing Reduces
Power Consumption
Low Bus-Port Capacitance
Power-Up!Power-Down Protection
(Glitch Free)
Open-Collector Driver Outputs Allows
Wired-OR Connections
Multiple Bus Channel Ground Returns to
Reduce Channel Noise Interference
Designed to Be a Faster, Lower Power
Functional Equivalent of National DS3893
description
NPACKAGE
{TOP VIEW)
BGGNO
BUSGNO
B1
B2
BUSGNO
B3
B4
BUSGNO
Vcc
01
R1
02
R2
LOGICGNO
03
R3
04
R4
6
7
8
9
10
fiE
FNPACKAGE
{TOP VIEW)
00
Z~
o~
!J)
a: c :§? ~ ffi
02
R2
LOGICGNO
03
R3
B1
B2
BUSGNO
B3
B4
The SN75ALS053 is a four-channel, monolithic,
high-speed, advanced low-power Schottky device
v v wlw 0
OII:I-II:Z
designed for two-way data communication in a
~
densely populated backplane. The SN75ALS053
~
has independent driver input (On) and receiver
CD
output (Rn) pins and separate driver and receiver
disables. This transceiver is designed for use in high-speed bus systems and is similar to the SN75ALS057
transceiver except that the trapezoidal feature has been eliminated to speed up the propagation delays.
These transceivers feature open-collector driver outputs, each with a series Schottky diode to reduce capacitive
loading to the bus. By using a 2-V pullup on the bus, the output signal swing will be approximately 1 V, which
reduces the power necessary to drive the bus load capacitance. The driver outputs are capable of driving an
equivalent dc load of as low as 10 g.
The receivers have a precision threshold set by an internal bandgap reference to give accurate input thresholds
over VCC and temperature variations.
These transceivers are compatible with Backplane Transceiver Logic (BTLTM) technology at significantly
reduced power dissipation per channel.
The SN75ALS053 is characterized for operation from O· to 70·C.
BTL is a trademark of National Semiconductor Corporation.
IN~
POST OFFICE BOX 65~ •
DALlAS. TEXAS 75265
Copyright@ 1989. Texas Instruments Incorporated
2--f17
SN75ALS053
QUAD FUTUREBUS TRANSCEIVER
Sll.S()34B -' D3077, JANUARY 1988 - REVISED SEPTEMBER 1989
logic d!agram (positive logic)
FUNcnON TABLE
TRANSMIT/RECEIVE
CONTROLS
CHANNELS
I'fE
o-B
B-R
L
0
R
L
L
H
0
0
H
L
T
R
H
H
0
T
H = high level, L = low level, R = receive,
T = transmit, 0 disable
TE
Direction of data transmission is from On to
Bn, direction of data reception Is from
to Rn.
R1
TE
RE
11
12
Xmlt
01
=
en
18
+-
01
R1
02
R2
03
R3
D4
R4
12
18
3
4
17
5
7
15
8
9
10
14
D4
9
B1
R4
10
B2
B3
B4
tThis symbol Is in accordance with ANSI/IEEE Sid 91-1984
and lEe Publication 617-12.
2-'98
Rae
2 Identical C~annel8 Not Shown
_~1~1__~~~B1I---'
2
B1
3
logic symbol t
TE
RE
-+
2
POST OFFICE BOX 655303 • DALlAS, TEXAS 75285
~r
14
B4
SN75ALS053
QUAD FUTUREBUS TRANSCEIVER
SlJ..S034B -
D30n. JANUARY 1988- REVISED SEPTEMBER 1989
schematics of Inputs and outputs
DRIVER OUTPUT
RECEIVER INPUT
VCC-----e-----------+--~----~-------
REINPUT
VCC
2OkO
GND __-.~__________~
GND-----e--~~_.~-+--r_------_.-----
RECEIVER OUTPUT
DRIVER INPUT
VCC --------------~------~----T_------~~------_.---2OkO
TE
ESD
Protect
GND--------------~--~--~----+_--e---_.~e_----__------~----__---
All resistor values shown are nominal.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) ............................................................. 6 V
Control input voltage ...................................................................... 5.5 V
Driver input voltage ....................................................................... 5.5 V
Driver output voltage ....................................................................... 2.5 V
Receiver input voltage ..................................................................... 2.5 V
Receiver output voltage .................................................................... 5.5 V
Continuous total power dissipation ..................................... See Dissipation Rating Table
Operating free-air temperature range .................................................. O°C to 70°C
Storage temperature range ....................................................... - 65°C to 150°C
Case temperature for 10 seconds: FN package .............................................. 260°C
Lead temperature 1,6 mm (1/16 in) from case for 10 seconds: N package ....................... 260°C
NOTE 1: Voltage values are with respect to network ground terminal.
DISSIPATION RATING TABLE
PACKAGE
TAS,25·C
POWER RATING
DERATING FACTOR
ABOVE TA = 25·C
FN
1400MW
11.2 Mwrc
896MW
N
1150 MW
9.2MWrc
736mW
1ExAs ~
INSTRIJMENTS
POST OfFICE BOX 656303 • DALLAS. TEXAS 75265
TA=70·C
POWER RATING
2-&9
SN75ALS053
QUAD FUTUREBUS TRANSCEIVER
SLLS034B - D30IT. JANUARY 1988 - REVISED SEPTEMBER 1989
recommended operating conditions
Supply voltage. Vcc
High-level driver and control Input voltage. VIH
MIN
NOM
MAX
4.75
5
5.25
Low-level driver and control input voltage. VIL
0.8
Operating free-air temperature. TA
V
V
2
Bus termination voKage
UNIT
V
1.9
2.1
V
0
70
·C
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VIK
Input clamp voltage at On. DE. or RE
VT
Receiver input threshold voKage at Bn
VOH
High-level output voltage at Rn
VOL
LOW-level output voltage
IIH
High-level input current
MIN
1.426
Bnat1.2V.
IOH",-1 rnA
REat 0.8V.
Rn
8nat2V.
10L'" 20 rnA
REatO.8V.
Bn
Dnat2.4V.
VL"'2V.
TEat2.4V.
RL'" 109
On. TEorRE
VI ",VCC
Bn
VI "'2V.
On at 0.8 V.
MAX
UNIT
-1.5
V
1.674
V
2.5
V
0.5
See Figure 1.
V
0.75
1.2
40
VCC '" 0 or 5.25 V.
TE at 0.8V
IlL
Low-level input current at On. TE or RE
VI ",0.4V
lOS
Short-circuit output at Rn
RnatOV.
Bn at 1.2V.
ICC
Supply current
CO(8)
Driver output capac Rance
'vCC",5V.
TA",25D C
1ExAs
REatO.8V
,If
INSIRUMENTS
2-100
TYP
11",-18mA
POST OFFICE BQX 655303 • DAUAS. TEXAS 75266
100
-70
6.5
I4A
-400
I4A
-200
rnA
65
rnA
pF
SN75ALS053
QUAD FUTUREBUS TRANSCEIVER
SLLS034B -
D30n; JANUARY 1988 - REVISED SEPTEMBER 1989
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature
driver
FROM
(lNPUl)
PARAMETER
tpLH
Propagation delay time low-to-high-Ievel output
tPHL
Propagation delay time high-to-Iow-Ievel output
tpLH
Propagation delay time low-to-hlgh-Ievel output
tpHL
Propagation delay time hlgh-to-Iow-Ievel output
t-rLH
Transition time, low-to-hlgh-level output
t-rHL
Transition time, hlgh-to-Iow-Ievel output
Skew between driver channels t
TO
(OUTPUl)
TEST CONDITIONS
On
Bn
TEat3V,
See Figure 2
VL=2V,
On
Bn
Onat3V,
See Figure 2
VL=2\/,
On
Bn
TEat3V,
See Figure 2
VL=2V,
On
Bn
TE at 3V,
VL=2V
MIN
MAX
2
7
2
7
2
7
2
7
O.S
S
O.S
S
1
UNIT
ns
ns
ns
ns
receiver
PARAMETER
FROM
(INPUl)
TO
(OUTPUl)
Bn
An
TEST CONDITIONS
MIN
MAX
2
8
2
8
UNIT
tpLH
Propagation delay time,
low-to-high-Ievel output
tpHL
Propagation delay time,
high-to-Iow-Ieve! output
tPl2
Output disable time
from low level
AE
An
Bn at 2V,
CL=SpF,
TE at 0.3\/,
ALl = SOO 0,
VL=SV,
See Figure 4
6
ns
tPZL
Output enable time
to low level
AE
An
Bnat2V,
CL=SpF,
TE at 0.3 V,
ALl = SOO 0,
VL=SV,
See Figure 4
12
ns
tpHZ
Output disable time
from high level
AE
Rn
Bnat1V,
CL=SpF,
TEatO.3V,
RLl = SOD 0,
VL=O,
See Figure 4
6
ns
tpZH
Output enable time
to high level
AE
Rn
BnatlV,
CL= SpF,
TE at 0.3 \/,
ALl = SOD 0,
VL=O,
See Figure 4
12
ns
Skew between receiver
channelst
Bn
An
AE at 0.3 V,
TE at 0.3 V
1
ns
AE at 0.3 V,
ns
TE at 0.3 V
t Skew Is the difference between the propagation delay time (tpLH or tpHU of one receiver channel and that same propagation delay time of any
other receiver channel. It applies for both tpLH and tpH L.
1ExAs'"
INSIRUMENTS
POST OFFICE BOX 656303 • DAllAS, TEXAS 75265
2-101
SN75ALS053
QUAD FUTUREBUS TRANSCEIVER
SLLS034B - 03077, JANUARY 1988 - REVISED SEPTEMBER 1988
PARAMETER MEASUREMENT INFORMATION
(Bn)
Vo
Figure 1. Driver Low-Level-output-Voltage Test Circuit
Vl(On, TE)
Vo
30 pF (Includes Jig capacitance)
TEST CIRCUIT
Vl(On, TE)
VO(Bn)
VOLTAGE WAVEFORMS
NOTE: Ir
=If s; 5 ns from 10% 10 90%
~
Figure 2. Driver Test Circuit and Voltage Waveforms
1ExAs
2-102
,If
INSIRUMENIS
POST OFFICE BOX 655303 • DAUAS, TEXAS 76265~
SN75ALS053
QUAD FUTUREBUS TRANSCEIVER
ooon. JANUARY 1988 - REVISED SEPTEMBER 1989
SLLS034B -
PARAMETER MEASUREMENT INFORMATION
VI(Bn)
SN75ALS053II-::(R:-n):---41'-- Vo
T
50 pF (Includes jig capacitance)
TEST CIRCUIT
2V
1V
___
f
~55~~.lo..._ _ _ _ _ _ _ _1_.55~V
-+l
tpLH
VOH _ _
_ _---+j
___
VO(Rn)
I+-!-,
1.5 V/
VOL ------I
1I+--
tPHL
1.5 V\\-.____
VOLTAGE WAVEFORMS
NOTE: tr
= tf S 10 ns from 10% to 90%
Figure 3. Receiver Test Circuit and Voltage Waveforms
J--.__-e--
T
Vo
CL (Includes jig capacitance)
TEST CIRCUIT
\ , 1.5V
1
---+t
1"-- tpZH
11,..----
-.l.I
VO(Rn)
1.5V
1
--.. 1"--
tPZL
1
~...1_.5_V_ _ __
VO(Rn)
VOLTAGE WAVEFORMS
NOTE: tr
=tf S 5 ns from 10% to 90%
Figure 4. Test Circuit and Voltage Waveforms From RE to Rn
1ExAs ."
INSIRUMENfS
POST OFFICE BOX 655303 • DAUAS. TEXAS 75265
2-103
2-104
SN55ALS056, SN55ALS057, SN75ALS056, SN75ALS057
TRAPEZOIDAL-WAVEFORM INTERFACE BUS TRANSCEIVERS
993
SUITABLE FOR IEEE STANDARD 896 APPLICATIONSt
•
•
•
•
•
SN55ALS056 and SN75ALS056 are Octal
Transceivers
SN55ALS057 and SN75ALS057 are Quad
Transceivers
High-Speed Advanced Low-Power Schottky
Circuitry
Low Power Dissipation:
SNSS' Devices ••• 60 mW/Channel Max
SN75' Devices ••. 52.5 mW/Channel Max
High-Impedance PNP Inputs
•
•
•
•
•
logic Level 1-V Bus Swing Reduces Power
Consumption
Trapezoidal Bus Output Waveform Reduces
Noise Coupling to Adjacent Lines
Power-Up/Power-Down Protection
(Glitch Free)
Open-Collector Driver Outputs Allow
WIred-OR Connections
Designed to Be a Faster, Lower Power
Functional Equivalent of National DS3896,
DS3897
SN55Al.S056 ••• J OR W PACKAGE
SN75ALS066 ••• OW OR N PACKAGE
SN55ALS057 ••• J OR W PACKAGE
SN75ALS057 ••• ow OR N PACKAGE
(TOP VIEW)
(TOP VIEW)
B1
01
81
B2
R1
E1
B3
02
B4
R2
AS
B5
A6
B6
83
E3
CS
9
B7
B8
04
8
12
R4
9
11
T/R
TE
10
""""'-_--T
SN55AL.S056 ••• FK PACKAGE
(TOP VIEW)
~~nal ESD protection is on the 'ALS057, which has separate receiver output and driver input pins.
1ExAs
2-108
..If
INSIRUMENTS
POST OFFICE BOX 655303 • DALlAS, TEXAS 75265
SN55ALS056,SN55ALS057,SN75ALS056,SN75ALS057
TRAPEZOIDAL·WAVEFORM INTERFACE BUS TRANSCEIVERS
SLLS028D -D3025, AUGUST 1987 - REVISED MARCH 1993
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) ............................................................. 6 V
Control input voltage ...................................................................... 5.5 V
Driver input voltage ....................................................................... 5.5 V
Driver output voltage .............................•........................................ 2.5 V
Receiver input voltage ..................................................................... 2.5 V
Receiver output voltage ............................. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5.5 V
Continuous total power dissipation ..................................... See Dissipation Rating Table
Operating free-air temperature range: SN55ALS05_ ................................ -55·C to 125·C
SN75ALS05 ... . .. .. .. .. .. . .. . .. . .. .. . .. . .. . . . . O·C to 70·C
Storage temperature range .....................--:................................. - 65·C to 150·C
Case temperature for 60 seconds: FK package ............................................. 300·C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: DW or N package .............. 260·C
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: J or W package ............... 300·C
NOTE 1: Voltage values are with respect to network ground terminal.
DISSIPATION RATING TABLE
DERATING FACTOR
ABOVE TA = 25°C
TA=70°C
POWER RATING
1025mW
8.2mW/"C
656mW
1375mW
11.0 mW/"C
aaOmW
N
1150mW
9.2mW/"C
736mW
J
1375mW
11.0mW/"C
aaOmW
275mW
W
1000mW
8.0mW/"C
640mW
200mW
PACKAGE
TA,.25°C
POWER RATING
OW
FK
TA = 125°C
POWER RATING
275mW
recommended operating conditions
Supply voltage, VCC
MIN
NOM
MAX
I SN55ALS05
4.5
5
5.~
I SN75ALS05
4.75
5
5.25
High-level driver and control input vottage, VIH
2
Low-level driver and control input voltage, VIL
0.8
Bus termination voltage
Operating free-air temperature, TA
1.9
2.1
I SN55ALS05
-55
125
I SN75ALS05
0
70
UNIT
V
V
V
V
°c
1ExAs . "
INSIRUMENTS
POST OFFICE BOl( 655303 • DAUAS. TEXAS 75265
2-109
SN55ALS056,SN75ALS056
TRAPEZOIDAL-WAVEFORM INTERFACE BUS TRANSCEIVERS
Su.s028D,- 03025. AUGUST'987 - REVISED MARCH '993
SN55ALS056 electrical characteristics over recommended ranges of supply voltage and operating
free-air temperature (unless otherwise noted)
PARAMETER
VIK
TEST CONDITIONst
Input clamp voltage at An. T/R. or CS
VCC=5V.
UNIT
V
1.4
1.7
Vee=4.5V.
eSatO.8V.
10H = - 400 !lA
Bn at 1.2 V,
T/R at 0.8 V,
2.4
An
Vee=4.5V.
eSatO.8V.
10L= 16 rnA
Bnat2V,
T/R at 0.8 V,
Bn
Vce= 4.5V.
eSatO.8V.
See Figure 1
An at 2V,
T/Rat2V.
High-level output voltage at An
Low-level output voltage
An. T/R or CS
VI =Vce =5.5V
Bn
Vce= 5.5V.
An at 0.8 V,
V
V
0.5
V
0.75
1.2
40
VI.=2V.
100
T/RatO.8 V
Low level Input current at An. TIR. or CS
Vce= 5.5V.
VI =0.4V
lOS
Short-cIrcuit output current at An
Vee = 5.5V.
Bn at 1.2 V,
T/RatO.8V
AnatOV,
eSatO.8V.
ICC
Supply current
Vee=5.5V
Co(B)
Driver output capacitance
IlL
MAX
-1.5
TA = -55°C to 125°C
VOH
High-level input current
TA = 25°C
TYpt
1.65
Receiver Input threshold voltage at Bn
IIH
Vee=5V.
MIN
1.45
v-r
VOL
Vee=4.5V.
11';-18rnA
-35
,
!lA
-400
!lA
-125
rnA
85
rnA
4.5
pF
SN75ALS056 electrical characteristics over recommended ranges of supply voltage and operating
free-air temperature (unless otherwise noted)
.
PARAMETER
TEST CONDITIONst
VIK
Input clamp voltage at An. T/R. or es
v-r
Receiver Input threshold voltage at Bn
VOH
High-level output voltage at An
I
VOL
TYpt
Bnat1.2V,
T/R at 0.8 V,
es at 0.8 V.
10H = -400!lA
An
Bnat2V.
T/Rat 0.8 V.
CSatO.8V.
IOL=16rnA
Bn
Anat2V.
T/Rat2V.
RL= 18.5Q.
es at 0.8 V.
VL=2V.
See Figure 1
An. T/RorCS
VI =VCC
Bn
VI =2V,
An at 0.8V.
Low-level output voltage
High-level input current
IlL
Low level input current at An. T/R. or CS
VI =0.4V
lOS
Short-circuit output current at An
AnatOv,
CSat 0.8V.
ICC
Supply current
Co(B)
Driver output capacitance
MAX
UNIT
-1.5
V
1.674
1.426
IIH
V
V
2.4
(
0.5
V
0.75
1.2
40
VCC = 0 or 5.25 V.
T/RatO.8V
Bn at 1.2 V.
T/RatO.8V
100
-40
4.5
t All typical values are atVcc = 5 V. TA = 25°C.
2-110
MIN
II =-18 rnA
POST OFFICE eox 655303 • DAUAS. TEXAS 75265
!lA
-400
!lA
-120
rnA
75
rnA
pF
SN55ALS057,SN75ALS057
TRAPEZOIDAL-WAVEFORM INTERFACE BUS TRANSCEIVERS
SLLS0280 - 03025. AUGUST 1987- REVISED MARCH 1993
SN55ALS057 electrical characteristics over recommended ranges of supply voltage and operating
free-air temperature (unless otherwise noted)
MAX
UNIT
MIN TYpt
PARAMETER
TEST CONDITIONS
-1.5
V
1.45
1.65
V
TA = -55°C to 125°C
1.4
1.7
Vee = 4.5 V,
REat O.BV.
Bnat 1.2V.
10H = -400
2.4
Rn
Vee = 4.5V.
REatO.BV.
Bn at 2V.
10L= 16mA
Bn
Vee=4.5V.
Enat2V.
See Figure 1
Dnat2V.
TEatO.BV.
On. En. TE. or
RE
VI =Vee= 5.5V
Bn
Vee =5.5V.
OnatO.BV.
TEatO.BV
VI=2V.
En at O.B V,
Low-level input current at On. En. TE. or RE
Vee =5.5V.
VI =0.4V
lOS
Short-circuit output current at Rn
Vee =5.5V.
Bn at 1.2 V.
RnatOV.
REatO.BV
ICC
Supply current
Vee = 5.5V
eoCB)
Driver output capacitance
VIK
Vy
VOH
VOL
IIH
IlL
Input clamp voltage at Dn. En. TE. or RE
Receiver Input threshold voltage at Bn
High-level output voltage at Rn
Low-level output voltage
High-level Input current
Vee = 4.5V.
11=-lBmA
Vee=5V.
TA=25°e
Vee=5V.
tAA
V
0.5
V
0.75
1.2
,
40
tAA
100
-435
-400
tAA
-125
mA
45
mA
4.5
pF
t All typical values are at Vee = 5 V. TA = 25°C.
SN75ALS057 electrical characteristics over recommended ranges of supply voltage and operating
free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYpt
MAX
UNIT
VIK
Input clamp voltage at On. En. TE. or RE
Vy
Receiver input threshold voltage at Bn
VOH
VOL
IIH
11=-lBmA
1.43
Bn at 1.2 V.
10H = - 400 tAA
REatO.BV.
Rn
Bn at2V.
10L= 16mA
REatO.BV,
Bn
Onat2V,
TEat O.BV.
RL= lB.5Q.
Enat2V,
VL=2V.
See Figure 1
On, En. TE.
orRE
VI = Vee
Bn
VI=2V.
OnatO.BV.
TEatO.BV
High-level output voltage at Rn
Low-level output voltage
High-level input current
Low-level input current at On. En. TE. or RE
VI =0.4V
lOS
Short-circuit output current at Rn
RnatOV.
REatO.BV
ICC
Supply current
eoCB)
Driver output capacitance
IlL
-1.5
V
1.65
V
2.4
V
0.5
V
1.2
0.75
40
tAA
Vee = 0 or 5.25 V.
En at O.BV,
Bn at 1.2 V.
100
-40
4.5
-400
tAA
-120
mA
40
mA
pF
t All typical values are at Vee = 5 V. TA = 25°C.
TEXAS ~
INSIRUMENIS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
2-111
SN55AlS056, SN75AlS056
TRAPEZOIDAl·WAVEFORM INTERFACE BUS TRANSCEIVERS
SLLS028D - D3025, AUGUST 1987 - REVISED MARCH 1993
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature
SN55ALS056 driver
PARAMETER
tPLH
FROM
(lNPUl)
TO
(OUTPUT)
Propagation delay time,
Iow-to-hlgh-input level
tpHL
Propagation delay time
high-to-Iow-Input level
tpLH
Propagation delay time,
low-to-high-input level
tpHL
Propagation delay time,
high-to-Iow-Input level
tPLH
Propagation delay time,
low-to-high-input level
tpHL
Propagation delay time,
hlgh-to-Iow-Input level
tpHL
Propagation delay time,
low-to-hlgh-Input level
tpLH
Propagation delay time,
hlgh-to-Iow-Input level
An
CS
T/R
Bn
Bn
Bn
TEST CONDI11ONS
CSatO.8V,
VL=2V,
RL2=5000,
See Figure 2
T/Rat2V,
RL1=180,
CL=SOpF,
An and T/R at 2 V,
RL1=180,
CL=SOpF,
. VL=2V,
RL2=5000,
See Figure 2
CSatO.8V
RLl = 180,
CL=SOpF,
VL=2V,
RL2=5000,
See Figure 3
TAt
MIN
TYP*
10
Full range
40
25°C
12
Full range
15
25°C
18
Full range
30
25°C
20
Full range
22
25°C
18
Full range
37
25°C
18
Full range
An
Bn
CSatO.8V,
RLl = 18 0,
CL=SOpF,
See Figure 2
T/Rat2V,
RL2 = 5000,
VL=2V,
MAX
25°C
UNIT
ns
ns
ns
21
25°C
1
Full range
1
25°C
1
Full range
1
3
8
33
3
10
ns
13
SN75ALS056 driver
PARAMETER
tpLH
Propagation delay time,
Iow-to-high-output level
tpHL
Propagation delay time
hlgh-to-Iow-output level
tpLH
Propagation delay time,
low-to-hlgh-output level
tpHL
Propagation delay time,
high-!o-Iow-output level
tpLH
Propagation delay time,
low-to-high-output level
tpHL
Propagation delay time,
hlgh-to-Iow-output level
ITLH
Transition time,
low-to-hlgh-Ievel output
ITHL
Transition time,
high-to-Iow-Ievel output
FROM
(INPUl)
TO
(OUTPUT)
An
Bn
CS
T/R
An
Bn
Bn
Bn
TEST CONDI110NS
TYP§
MAX
CS at 0.8 V,
VL=2V,
RL2 not connected,
See Figure 2
T/Rat2V,
RLl = 180;
CL=30pF,
19
An and T/R at 2 V,
RLl = 18 0,
RL2 not connected,
VL=2V,
CL=30pF,
See Figure 2
24
VI (An) =SV,
RLI = 180,
RL2 not connected,
See Figure 3
CS at 0.8 V,
CL=30pF,
VL=2V,
25
CSat 0.8 V,
VL=2\1,
RL1=180,
See Figure 2
T/Rat2V,
CL=30pF,
RL2 not connected,
t Full range Is -55°C to 125°C.
:I: Typical values are at VCC = 5 V.
§ All typical values are at VCC = 5 V, TA = 25°C.
1ExAs ."
, INSIRUMENTS
2-112
MIN
POST OFFICE BOX 655303 • DAUAS,. TEXAS 75265
UNIT
ns
18
ns
20
ns
35
1
3
11
1
3
6
ns
SN75ALS056
TRAPEZOIDAL-WAVEFORM INTERFACE BUS TRANCEIVER
SLl.S0280 - D3025, AUGUST 1987 - REVISED MARCH 1993
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature
SN55ALS056 receiver
PARAMETER
tpLH
Propagation delay time,
low-to-high-level Oulpul
tPHL
Propagation delay time,
high-to-Iow-level oulpul
tPL2
Oulpul disable time
from low level
tpZL
Outpul enable time
to low level
tpHZ
Outpul disable time
from high level
FROM
(INPUT)
Bn
CS
CS
tpZH
Oulpul enable time
to high level
tPL2
Oulpul disable time
from low level
tpZL
Oulpul enable time
to low level
TfFi
tpHZ
tw(NR)
An
An
An
An
Outpul enable time
to high level
Receiver noise rejection
pulse duration
Bn
TEST CONDInONS
CS at 0.8 V,
RL1 =5000,
CL=50pF,
T/RatO.8V,
RL2=5000,
See Figure 4
Bnat2V,
RL1 =5000,
CL=50pF,
See FigureS
T/RatO.8V,
RL2 = 500 0,
VL=5V,
Bn at 0.8 V,
VL=O,
RL1 = RL2 = 500 0,
T/'R'atO.8V,
CL=50pF,
See Figure 5
Bn at 0.8 V,
RL 1 not connected,
CL=50pF,
T/R at 0.8 V,
RL2= 5000,
See Figure 5
TAt
MIN
MAX
25°C
20
Full range
22
25°C
18
Full range
20
25°C
20
Full range
22
25°C
13
Full range
14
25°C
12
Full range
13
25°C
14
Full range
22
An
UNIT
ns
ns
ns
An
Oulpul disable time
from high level
T/R
tpZH
TO
(OUTPUT)
Bnat2V,
VL=5V,
RL2 = 500 g,
See Figure 3
CSat 0.8 V,
RL1 =5000,
CL=50pF,
Bn at 0.8 V,
VL=O,
RL2=5000,
See Figure 3
CS at 0.8 V,
RL1 =5000,
CL=50pF,
Bn at 0.8 V,
RL10pen,
CL=50pF,
CSat 0.8 V,
RL2= 500 0,
See Figure 3
VL=5V,
RL2= 500 0,
See Figure 6
RL1 =5000,
CL=50pF,
25°C
17
Full range
20
25°C
25
Full range
40
25°C
12
Full range
13
25°C
15
Full range
22
25°C
4
Full range
2
ns
ns
ns
t Full range Is -55°C to 125°C.
1ExAs
~
INSIRlJMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2-113
SN75ALS056
TRAPEZOIDAL-WAVEFORM INTERFACE BUS TRANCEIVER
SLLS028D - 03025, AUGUST 1987 - REVISED MARCH 1993
switching· characteristics over recommended ranges of supply voltage and operating free-air
temperature
SN75ALS056 receiver
PARAMETER
tpLH
Propagation delay time,
low-to-hlgh-Ievel output
FROM
(INPUl)
TO
(OUTPUl)
Bn
An
TEST CONDITIONS
CSatO.8V;
RL2= 1.6kO,
tpHL
Propagation delay time,
high-to-I6w-level output
tpLZ
Output disable time
from low level
CS
tpZL
Output enable time
to low level
CS
tpHZ
Output disable time
from high level
CS
tpZH
Output enable time
to high level
CS
An
Bn at 0.8 V,
VL=O,
RL2 = 1;6 kO
tpLZ
Output disable time
from low level
T/R
An
tpZL
Output enable time
to low level
TIR
tpHZ
Output disable time
from high level
tPZH
Iw(NR)
T/Rat 0.8 V;
CL=30pF,
CL=5pF,
An
Bnat2V,
VL=5V;
See Figure 5
CL=30pF,
RL2 = 1.6 kO,
An
Bn at 0.8 V,
T/R at 0.8 V;
RL1 =3900,
VL=O,
RL2 not connected,
MAX
UNIT
·18
RL1 =3900,
See Figure 4
Bnat2V,
T/R at 0.8 V;
VL=5V,
RL1 =3900,
RL2 not connected,
ns
18
18
ns
15
ns
8
ns
T/R at 0.8 V;
CL=30pF,
RL 1 not connected,
See Figure 5
17
ns
CSatO.8V,
RL1 =3900,
CL=15pF,
VI(Bn) =2V,
VL=5 V,
RL2 not connected,
See Figure 3
20
ns
An
CSatO.8V,
RL1 =3900,
CL=30pF,
VI(Bn) =2V,
RL2 = 1.6 kO,
See Figure 3
40
ns
T/R
An
CS at 0.8 V;
RL1 = 390 C,
CL= 15pF,
VL=O,
VI(Bn) =0,
RL2 not connected,
See Figure 3
17
ns
Output enable time
to high level
T/R
An
CS at 0.8 V,
VI(Bn) = 0,
RL 1 not connected,
See Figure 3
CL= 30 pF,
VL=O,
FiL2 = 1.6 kO,
15
ns
Receiver noise re)ectlon
pulse duration
Bn
An
CS at 0.8 V;
RL2= 1.6kO,
See Figure 6
RL1 =3900,
VL=5V,
An
1ExAs
TIR at 0.8 V;
RL1 = 390 0,
T/Rat 0.8 V;
CL=30pF,
..If
INSIRUMENIS
2-114
MIN
POST OFFICE BOX 655303 • DAllAS, TEXAS 75265
See Figure 5
CL=5pF,
See Figure 5
VL= 5V;
3
ns
SN55ALS057,SN75ALS057
TRAPEZOIDAL-WAVEFORM INTERFACE BUS TRANSCEIVERS
SLlS0280 - D3025, AUGUST 1987 - REVIseD MARCH 1993
switching characteristics over recommended ranges of supply voltages and operating free-air
temperature
SN55ALS057 driver
PARAMETER
tpLH
Propagation delay time.
low-to-hlgh-Ievel output
tpHL
Propagation delay time.
high-to-Iow-Ievel output
tpLH
Propagation delay time.
low-to-high-Ievel output
tpHL
Propagation delay time.
high-to-Iow-Ieveloutput
ITLH
Transition time.
low-IO-hlgh-Ievel output
ITHL
Transition time.
hlgh-to-Iow-level output
FROM
(INPUT)
TO
TEST CONDITIONS
(OUTPUT)
Dnor En
TE at 0.8 V.
VL=2V,
RL2= 500C.
See Figure 2
Bn
On or En
REat2V,
RL'=180,
CL=50pF.
On. En. RE at 2 V,
VL=2V,
RL'=18C.
RL2= 500 C.
CL=50pF.
See Figure 2
Bn
TE
TAt
REat2V,
RL' = 18 C.
CL=50pF.
Bn
VL=2V.
RL2 = 500 C.
See Figure 2
MIN
TYP*
MAX
25°C
10
Full range
27
25°C
12
Full range
15
25°C
10
Full range
27
25°C
17
Full range
UNIT
ns
ns
19
25°C
1
Full range
1
25°C
1
Full range
1
3
8
ns
33
3
10
ns
13
t Full range is -55°C to 125°C.
:I: Typical values are at VCC = 5 V. TA = 25°C.
SN75ALS057 driver
PARAMETER
tpLH
Propagation delay time.
low-to-high-Ievel output
tpHL
Propagation delay time.
high-to-Iow-Ievel output
tpLH
Propagation delay time.
low-to-high-Ievel output
tpHL
Propagation delay time.
hlgh-to-Iow-level output
ITLH
Transition time.
low-to-high-Ievel output
ITHL
Transition time.
high-to-Iow-Ievel output
FROM
(INPUT)
TO
(OUTPUT)
On or En
Bn
TE
On or En
Bn
Bn
TEST CONDITIONS
MIN
TYpt
MAX
TEatO.8 V,
VL=2V,
RL2 not connected.
See Figure 2
REat2V,
RL' = 180.
CL=30pF.
19
On. En. RE at 2 V.
RL2 not connected.
See Figure 2
VL=2V.
RL' = 18C.
CL=30pF.
24
REat2V.
TE at 0.8 V.
RL2 not connected.
See Figure 2
VL=2V.
RLI = 18 0.
CL=30 pF.
UNIT
ns
18
ns
20
1
3
11
1
3
6
ns
t All typical values are at VCC = 5 V, TA = 25°C.
1ExAs ."
INSIRUMENTS
POST OFFICE BOX 655303 • DAUAS. TEXAS 75265
2-115
SN55ALS057,SN75ALS057
.
TRAPEZOIDAL-WAVEFORM INTERFACE BUS TRANSCEIVERS'
Su.s028D -D3025,AUGUST 1987 - REVISED MARCH 1993
switching characteristics over recommended ranges of supply voltages and operating free-air
temperature (continued)
SN55ALS057 receiver
PARAMETER
tpLH
Propagation delay time,
low-to-high-Ievel output
tpHL
Propagation delay time,
high-to-Iow-Ievel output
tpLZ
Output disable time from
low level
tpZL
Output enable time to
low level
tpHZ
FROM
(INPUl)
Bn
RE
tw(NR)
Rn
Rn
Output disable time from
high level
RE
tpZH
TO
(OUTPUl)
Rn
Output enable time to
high level
Receiver noise rejection
pulse duration
Bn
Rn
TEST CONDITIONS
REatO.8V,
VL= Sv,
RL2 =500 0.
See Figure 4
Bnat2V,
VL= sv,
RL2 = 500 0.
See Figure 5
TAt
TEat2V,
RL1 =5000.
CL=5OpF,
TEat2V,
RL1 =SooQ,
CL=SOpF,
Bn at 0.8 V,
VL=OV,
RL2 =500 0.
See Figures
TEat2V,
RL1 = 500 Q,
CL=5OpF,
Bn at 0.8 V,
RL1 not connected
CL=SOpF, '
TEat2V,
RL2 = 500 Q,
See FigureS
VL=S V,
RL1 =SooQ,
CL=SOpF,
~!';I:~~.
MIN
MAX
25°C
20
Full range
22
25°C
18
Full range
20
25°C
15
Full range
17
25°C
13
Full range
14
25°C
12
Full range
13
25°C
14
Full range
UNIT
ns
ns
ns
15
25°C
4
Full range
2
ns
t Full range Is -55°C to 125°C.
SN75ALS057 receiver
PARAMETER
tpLH
Propagation delay time,
low-to-hlgh-Ievel output
FROM
(INPUl)
TO
(OUTPUl)
Bn
Rn
TEST CONDITIONS
RE at 0.8 V,
RL1 = 390 0.
See Figure 4
TE at 2V,
RL2= 1.6kQ,
MIN
Propagation delay time,
high-to-Iow-level output
Output disable time
from low level
RE
Rn
Bnat2V,
TEat2V,
RL1 =390Q,
CL=SpF,
RL2 not connected, See Figure 5
VL= SV,
tpLZ
tpZL
Output enable time
to low level
RE
Rn
Bnat2V,
CL=30pF,
See FigureS
VL=SV,
RL2= 1.6kQ,
tpHZ
Output disable time
from high level
RE
Rn
BnatO.8V,
TEat2V,
CL=SpF,
RL1 = 390Q"
RL2 not connected, See Figure 5
tpZH
Output enable time
to high level
RE
Rn
BnatO.8V,
CL=30pF,
RL2= 1.6 kQ,
TEat2V,
VL=O,
RL 1 not connected,
See FigureS
tw(NR)
Receiver noise
rejection pulse duration
Bn
Rn
TEat2V,
RL1 = 390 Q,
See Figure 6
RE at 0.8 V,
RL2= 1.6kQ,
2-116
UNIT
18
VL= sv,
CL=30pF,
tpHL
MAX
ns
18
TEat2V,
RL1 = 390 Q,
POST OFFICE BOX 655303 • DALlAS, TEXAS 75:!65
18
ns
15
ns
17
ns
17
ns
VL=O,
VL=O,
CL=30pF,
3
ns
SN55ALS056,SN55ALS057,SN75ALS056,SN75ALS057
TRAPEZOIDAL-WAVEFORM INTERFACE BUS TRANSCEIVERS
SllS0280 - 03025, AUGUST 1987 - REVISED MARCH 1993
switching characteristics over recommended ranges of supply voltages and operating free-air
temperature (continued)
SN55ALS057 driver plus receiver
FROM
(INPUl)
PARAMETER
tpLH
Propagation delay time,
low-to-hlgh-Ievel output
tpHL
Propagation delay time,
hlgh-to-Iow-Ievel output
TO
(OUTPUl)
On
Rn
TEST CONDITIONS
REatO.BV,
VL=2\1.
RL2 =5000,
See Figure 7
TAt
TEat O.BV,
RLI =5000,
CL=50pF,
MIN
MAX
25°C
25
Full range
35
25°C
25
Full range
44
UNIT
ns
t Full range Is -55°C to 125°C.
SN75ALS057 driver plus receiver
PARAMETER
tpLH
Propagation delay time,
low-tcrhlgh-Ievel output
tpHL
Propagation delay time,
hlgh-to-Iow-Ievel output
FROM
(lNPUl)
TO
(OUTPUl)
On
Rn
TEST CONDITIONS
REatO.BV,
RL2 = 1.6 kO,
TEatO.BV,
CL=30pF,
RLI =3900,
See Figure 7
MIN
MAX
UNIT
40
ns
40
PARAMETER MEASUREMENT INFORMATION
'ALS056
or
'AlSOS7
I--_..__-VO
(8n)
Figure 1. Driver Low-Level-Output-Voltage Test Circuit
1ExAs ,If
INSIRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
2-117
SN55ALS056,SN55ALS057,SN75ALS056,SN75ALS057
TRAPEZOIDAL-WAVEFORM INTERFACE BUS TRANSCEIVERS
SLlS028D - D3025, AUGUST 1987 - REVISED MARCH 1993
PARAMETER MEASUREMENT INFORMATION
'ALS0S6
or
'ALS067
VI(CS, TE, An,Dn, En
Vo
~--.-~----__
T
CL (includes Jig capacitance)
TEST CIRCUIT
3V
CI,TE
-----"1.5V
OV
tpLH
VI
3V
(An, On, En)
ov
VOH
VO(Bn)
VOL
-.! ~
tpHL
--+I ~
tpHL
~V\
____
tpLH
1.5V\
--+I ~
90% !\.
I
I
--+I i+- tTLH,
tTHL-+,
VOLTAGE WAVEFORMS
NOTE: tr
=tf ~ 5 ns from 10% to 90%
Figure 2. Driver Test Circuit and Voltage Waveforms
1ExAs
..If
INSIRUMENfS '
2-118
~
I
I
I
I
1.5Vj
I
I
I
-------],90% '
1.55 V
10%
-.!
POST OFFICE BOX 6S53OO • DALLAS. TEXAS 75265
1.55 V
10%
*-
SN55ALS056,SN55ALS057,SN75ALS056,SN75ALS057
TRAPEZOIDAL·WAVEFORM INTERFACE BUS TRANSCEIVERS
SLLS0280 - 03025. AUGUST 1987 - REVISED MARCH 1993
PARAMETER MEASUREMENT INFORMATION
VI{TIR)
-~-r----'
VI(An, Bn)
"""t~~---.J
Vo
1-----.-4f----4....
CL (Includes Ilg capacitance)
TEST CIRCUIT
VI{T/R) 3 V
OV
tpHL
VO(Bn)
11..
fI'I-_ _""'\
- - - - -"1.;v1
1_.
S_V _ _ __
jj
-.t
j4-
tpLH
-----....1,""',
',\'1.SSV
-.t
,T1.SSV
I
'~j
tpLZ
VO(An)
-.t
"
VO(An)
1I>zL -.t j4-
-----+l'F t
tpHZ ~
,
j4-
~I
j
oJ
-
j4-
, 11_----
-
!
1
"-----'1.SV
O.S V
-+I
SV
,'+- fO'tpZH
'+-
3r-
-------.,~-1
S1 Closed
S20pen
,
-- - 1.SV
S10pen
S2Closed
VOLTAGE WAVEFORMS
NOTE: Ir =If " 5 ns from 10% 10 90%
Figure 3. Propagation Delay From T/A'to An or Bn Test Circuit and Voltage Waveforms
SV
'ALS056
or
'ALS0S7
VI(Bn)
.....- Vo
T
I -____-.~t--
L..-_ _ _........I
(An,Rn)
RL2
CL (includes lig capacitance)
TEST CIRCUIT
2V
VI(Bn)
1 V ___
________
r-
~~~1'__
tpLH -./
VO(An,Rn) VOH
,-------
1_.SS.....Jvt
------1~_;'
~
r-
tpHL
1.SV "
VOL'
1...- - - -
VOLTAGE WAVEFORMS
NOTE: Ir = If " 10 ns from 10% 10 90%
Figure 4. Receiver Test Circuit and Voltage Waveforms
1ExAs ",
INSIRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
2-119
SN55ALS056, SN55ALS057, SN75ALS056, SN75ALS057
TRAPEZOIDAL-WAVEFORM INTERFACE BUS TRANSCEIVERS
SI.1.S028D - D3025, AUGUST 1987 - REVISED MARCH 1993
PARAMETER MEASUREMENT INFORMATION
'ALS056
or
'ALS057
-.---41..-....-
1-____
(An,Rn)
T
RL2
Vo
CL (Includes Ilg capacitance)
.".
TEST CIRCUIT
3V
OV
--~--~s-;
f
1
tpHZ~
\1.5V
f
~
:ltc=f
--+! ~
______~~=~
tpLZ
VO(An, An)
1"----
O.s V ~ j+-:. tPZH
J}
O.S V
1.SV
--.! ~ tpZL
~~l.S_V_ __
VOLTAGE WAVEFORMS
NOTE: tr '= If" 5 ns from 10% 10 90%
Figure 5. Propagation Delay From CS to An or RE to Rn Test Circuit and Voltage Waveforms
SV
RLl
SN75ALS056
or
SN75ALS057
(An,Rn)
RL2
t
Vo
CL (Includes Ilg capacitance)
TEST CIRCUIT
1.85 V
1.1 V
Bus Logic
Law Level
Bus Logic
High Level
-;55~l '}"-__
1
~"-_.....J'-~~V_
1
t----t.~:-
1.
o i.
I I :.
, . . - - 2V
1
tw(NR)
tw Is Increased until the output voltage fall
Just reachss 2 V.
:...
~
tw(NR)
tw Is increased until the output voltage rise
Just resches 0.8 V.
VOLTAGE WAVEFORMS
NOTE: Ir
=tf" 2 ns from 10% 10 90%
Figure 6. Receiver Noise Immunity Test Circuit and Voltage Waveforms
2-120
1.25V
1
POST OFFICE BOX 655303 • DAUAS. TEXAS 75265
SN55ALS056,SN55ALS057,SN75ALS056,SN75ALS057
TRAPEZOIDAL-WAVEFORM INTERFACE BUS TRANSCEIVERS
Su.s028D - 03025. AUGUST 1987 - REVISED MARCH 1993
PARAMETER MEASUREMENT INFORMATION
2V
SN55ALS057
(Bn)
50pF
5V
VI(Dn)
I - -___-~_+- Vo
(Rn)
RL2
T
T
CL (Includesllg capacitance)
"::"
TEST CIRCUIT
::-----~.;-vJ(
VI(Dn)
~1.5V
~tpLH
~tPHL
Ir-----------------~I
1
VO(Rn)
1.5 V
\""1_.S_V_ _ _ _ __
VOLTAGE WAVEFORMS
2V
SV
VI(Dn)
18Q
(Bn)
30 PF
SN75ALS057
I - -___-~_+- Vo
(Rn)
T
RL2
T
CL (Includesllg capacitance)
TEST CIRCUIT
VI(Dn)
I
3V
-----1~;
OV
.
~1.SV
I
~tPLH
VO(Rn)
~tPHL
I
1
\1.SV
1.SV
VOLTAGE WAVEFORMS
NOTE: Ir = If '" 5 ns from 10% 10 90%
Figure 7. Driver Plus Receiver Delay Times Test Circuits and Voltage Waveforms
1ExAs
~
INSIRUMENIS
POST OFFICE BOX 655303 • DAllAS. TEXAS 75265
2-121
2-122
SN75061
DRIVER/RECEIVER PAIR WITH SQUELCH
SLl.S026C-
JANUARY 1987 - REVISED JULY 1990
NPACKAGE
(TOP VIEW)
• IEEE 802.3 1BASES Driver and Receiver
• On-Chlp Receiver Squelch With Adjustable
Threshold
• Adjustable Squelch Delay
• Direct TIL-Level Squelch Output
• Squelch Circuit Allows for External Noise
Filtering
• Two Driver-Enable Options
• On-Chip Start-of-Idle Detection and Disable
• Driver Provides 2 V Minimum Into a 50-0
Differential Load to Allow for Use With
Doubly-Terminated Lines and Multipoint
Architectures
• On-Chip Driver Slew-Rate Control for Very
Closely Matched Output Rise and Fall
Times
vcc
OROLAJ
ORO +
OROSOOLAJ
RXI+
RXISOTHAJ
GNO
DATEN
ORI
OLEN
AXO
sao
6
9
SOOU
SORXO
Function Tables
RECEIVER§
DRIVER
INPUTS
OUTPUTS
DRI
DATEN OLEN ORO + DROL
L
X
L
H
H
L
X
H
L
X
H
H
Z
Z
Ht
Lt
H
H
L
L:I:
Hi
L
H
L
CONDITION
No active signal 11
Active signal 11
INPUTS
RXI +
RXI-
X
L
H
X
H
L
OUTPUTS
RXO
sao
H
H
L
L
H
L
tThls condition is valid during the time period set by DRDLAJ following a rising transition on DRI. Following this, if no
subsequent positive transition occurs on DRI, the outputs will go to the high-Impedance state.
:I: This condition is valid if it occurs within the enable time set by DRDLAJ after a rising transition on DRI. Otherwise, the
outputs will be In the high-impedance state.
§ Pins 9 and 10 are tied together.
11 An active signal Is one that has an amplitude greater than the threshold level set by SQTHAJ.
Copyright © 1990, Texas Instruments Incorporated
1ExAs .."
INSlRUMENTS
POST OFFICE BOX 655303 • DALlAS. TEXAS 75265
2-123
SN75061
DRIVER/RECEIVER PAIR WITH SQUELCH
SLLS026C - 02959. JANUARY 1987 - REVISED JULY 1990
logic diagram (positive logic)
Vcc
Slew Control
W
- 1 - 6 - - - -..,v
2
DRO+
14
DRI
-------.--------------------f
~_+--1 ~_-~3'- DRO-
DATEN~15~--~------------~r_~
>-----'-----<..-'-'
RXO
X ) - - - - " ' - ' - SQO
SQTHAJ ..:.7.....~.;v..,.
10
SQDLAJ
SQDU
lExAs.Jf
2-124
INSIRUMENTS
POST OFFICE BOX 855303 • DALLAS. TExAs 75265
SN75061
DRIVER/RECEIVER PAIR WITH SQUELCH
SLLS026C - 02959, JANUARY 1987 - REVISED JULY 1990
logic symbol t
DRI
t>
14
.n.
&
13
DRDLAJ
-
"
1
15
.. 1
V
>
2
DRO+
EN
V
[ADJDEL)
3
DRO-
"
1
RXI+
5
}
}
1
Z1
2
RXI-
6
1
Z2
2
SQTHAJ
saRXO
7
12
RXO
1
[ADJTHRES)
9
...IT
SQDU
3
.. 1
10
11
.n.
V3
sao
CI>
SaDLAJ
4
[ADJDEL)
t This symbol is in accordance with ANSI/IEEE Std 91-1984 and lEe Publication 617-12.
description
The SN75061 is a single-channel driver/receiver pair designed for use in IEEE 802.3, 1BASE5 applications as
well as other general data communications circuits. The SN75061 offers the system designer both a driver and
a receiver that are easily configured for use with a variety of controllers and data encoder/decoders.
The receiver features a full analog squelch circuit with an adjustable threshold and a programmable squelch
delay. Internal nodes of the squelch circuitry are brought out to external connections to allow for the insertion
of noise filtering circuitry of the designer'S choice.
As with the receiver, the driver offers a variety of implementation options. Driver enabling may be controlled
directly by an external logic input or by use of an on-Chip one-shot that is retriggered as long as data is being
sent to the driver. The driver will then automatically go to the high-impedance state when end-of-packet occurs.
The driver features internal slew-rate control for optimal matching of rise and tall times allowing for reduction
of driver-induced jitter.
1ExAs
.If
INSIRUMENTS
POST OFFICE BOX fl55303 • DAllAS. TEXAS 75265
2-125
SN75061
DRIVER/RECEIVER PAIR WITH SQUELCH
SLlS026C - D2959, JANUARY 1987 - REVISED JULY 1990
receiver
The SN75061 receiver implements full analog squelch functions by integrating both a separate, parallel squelch
receiver with an externally programmable threshold, and a programmable one-shot. The output of the squelch
receiver and the input to the high-level dc-triggered one-shot are brought out to external connections. These
pins can be shorted for direct implementation or used for the insertion of noise-filtering circuitry of the
implementer's design. The receiver one-shot can be effectively bypassed by applying a high logic level to
SQDU. The squelch threshold may be set externally by applying an external voltage setto a levelthat is-2 times
the desired threshold voltage. If SQTHAJ is left open, the squelch receiver will default to its internal preset value
of -600 mV. The receiver also outputs a high logic squelch signal when there is no active data present at the
receiver inputs. When no data is present on the transmission line, the receiver output assumes a high level. The
unsquelch duration is set externally with an R-C cOmbination at SQDLAJ.
driver
The driver offers a variety of implementation options. Driver enabling may be controlled directly by an active-low
external logic input on DATEN or by use of another on-Chip one-shot that retriggers with positive-going
transitions on the driver input line. If no positive transition occurs within the pulse duration set by an external
R-C combination, the one-shot times out and the driver is automatically put into a high-impedance state. When
operating in the delay-enable mode, the 2-bit-time high-level start-of-idle pulse prescribed by IEEE 802.3
1BASES causes the one-shot to time out and automatically place the driver outputs in the high-impedance state.
This delay time is also adjustable for use in other applications. The driver implements an output slew-rate control
that is internally set for nominally 40 mV/ns. (This is roughly a 100-ns peak-to-peak differential transition time.)
The driver outputs are capable of driving a 50-0 differential load with a minimum output level of 2 V. Short-circuit
output current is greater than 100 rnA.
Terminal Functions
PIN
DESCRIPTION
NAME
NO.
DATEN
15
Driver data enable. When low, driver outputs are In an active state. When high, the driver outputs are In a high-impedance
state if i5[Ejij Is also high.
OLEN
13
Driver delay enable. When this signal is low and DATEN is high, the driver outputs are active for a period of time set by
OROLAJ after a posHlve-going transition on ORI. Ifthere is no active data on ORI, the outputs are in a high-Impedance state.
1
Driver delay adjust is a connection for the external R-C combination that determines the duration of the driver output active
state after a positive transition on ORI when OLEN is low and DATEN is high.
OROLAJ
ORI
14
Driver data Input
ORO+
2
Noninverting driver output
ORO-
3
Inverting driver output
GNO
8
Ground. Common for ali voHages
RXI+
5
Nonlnverting receiver input
AXI-
6
Inverting receiver input
AXO
12
SaOlAJ
4
Main receiver input
Squelch delay adjust is a connection for an external R-C combination that determines the duration of the
receiver unsquelch after a negative-going transition on saou.
saou
10
Squelch delay Input Is the Input to the one-shot that controls the duration of the receiver unsquelch period. The main
receiver output remains unsquelched as long as saou is held high. llming ofthe unsquelch period begins on the high-tolow transition of saou.
sao
11
Squelch output is high while the receiver Is squelched.
SQAXO
9
Squelch receiver output Is high only when the differential receiver input exceeds the threshold set by SaTHAJ.
SaTHAJ
7
Squelch receiver threshold adjust. The voltage at this Input determines the threshold of the squelch receiver In a ratio of
-2, SaTHAJ to threshold. If left open, the squelch receiver threshold defauHs to -600 mV.
VCC
16
Supply-voHage input
1ExAs ."
2-126
INSIRUMENTS
POST OFFICE BOX 655303 • DAUAS, TEXAS 75265
SN75061
DRIVER/RECEIVER PAIR WITH SQUELCH
SLLS026C - 02959, JANUARY 1987 - REVISED JULY 1990
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee ........................................................................ 7 V
Input voltage (any logic input) ................................................................ 7 V
Receiver differential input voltage .......................................................... ±25 V
Receiver input voltage .................................................................... ± 15 V
Driver output voltage .............................................................. -0.5 V to 15 V
Continuous total dissipation at (or below) 25°e free-air temperature (see Note 1) .............. 1150 mW
Operating free-air temperature range ..................................................
to 70 0
Storage temperature range ....................................................... -65°C to 1500 e
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds ............................... 260 0 e
ooe
e
NOTE 1: For operation above 25·C free-air temperature, derate to 736 mW at 70·C at the rate of 9.2 mW/"C.
recommended operating conditions
Supply voltage, VCC
Driver high-level input voltage, VIH
MIN
NOM
MAX
UNIT
4.75
5
5.25
V
0.8
V
V
2
Driver low-level input voltage, VIL
Receiver common-mode input voltage, VIC (see Note 2)
-2.5
5
Driver high-level output current, 10H
mA
Driver low-level output current, 10L
Extemal timing resistance,
Rext
V
-150
5
Extemal timing capacitance, Cext
No restriction
Operating free-air temperature, TA
0
150
mA
260
kC
70
·C
NOTE2: The algebr8lc convention, in which the less-positive (more negative) limit is designated as minimum, is used In thiS data sheet for
common-mode input voltage VIC and threshold levels VT+ and VT-
electrical characteristics over recommended operating free-air and supply voltage range (unless
~therwise noted)
driver
PARAMETER
VIK
TEST CONDITIONS
Input clamp voltage
Differential-output voltage
dVOD
Change in differential-output voltage for a change in
logic Input state
TYpt
IIH
High-level input current
VI=24V
Low-level input current
VI =0.5V
lOS
Short-circuit output current
2.4
MAX
UNIT
-1.5
V
3.3
3.65
RL=115C
IlL
High-impedance output current
2
RL=50C
VOD
10Z
MIN
11=-18mA
±100
VI = 0.8 V or 2.5 V
Vo = 0 or6V:
,
VCC = 5.25 V
Ivoc= 10V
Ivoc=O
V
50
mV
20
-35
r.tA
r.tA
±300
mA
100
-100
r.tA
t All typical values are at VCC = 5 V, TA = 25·C.
1ExAs
~
INSIRUMENIS
POST OFFICE BOX 855303 • OAUAS. TEXAS 75265
2-127
SN75061
DRIVER/RECEIVER PAIR WITH SQUELCH
SLLS026C - D2959, JANUARY 1987 - REVISED JULY 1990
electrical characteristics over recommended operating free-air and supply voltage range (unless
otherwise noted) (continued)
'receiver
TEST CONDITIONS
PARAMETER
VIK
Input clamp voltage, squelch delay
II =-18mA
Vr+
Posltive-golng threshold voltage
VO=2.7V,
10=-0.4mA
Vr-
Nagatlve-going threshold voltage
Vo = 0.5 V,
10= 16mA
Vhys
Hysteresis (VT+ - Vr -l
VIC
Common-mode input voltage
High-level output voltage
SQO
High-level input curreht
IlL
Lew-level input curreht
lOS
Short-circuit oUtput current
SQO
10H = -20 1lA,
SQDLAJopen
SQDU
SQO
VCC=4.75V,
VID(RXI) = 50 mV
Ratio of SQTHAJ Input voltage to
actual squelch threshold vo.age
mV
2.7
3.5
2.7
4.65
0.45
0.5
IOL=16mA
0.35
0.5
IOL=8mA
0.45
IOL=16mA
0.5
20
VI=0.5V
-35
-15
-85
-15
-tOO
VCC = 5.25 V,
VO=O
VCC=5V,
VO=O
-0.8
-1
VIC = 1.5 Vto 3.5 V
-525
-600
VIC =-2.5 Vto 1.5 V
or 3.5 Vto 5V
V
IlA
IlA
mA
-1.2
10
SQTHAJ at 200 mV t6 4 V
V
V
VI=2.4V
VCC=5V,
SQTHAJopen
V
mV
2.7
Input resistance
Squelch preset threshold voltage
UNIT
mV
-50*
IOL=8mA
SQRXO
Vr-(sq)
50
IOL=8mA
RXO
~
, 10H = -400 IlA
VCC=4.75V,
VID(RXI) = -0.7 V,
VCC = 4.75 V,
SQDLAJat2V
SQRXO
IIH
-1.5
VCC=4.75V,
SQDLAI at 0.8 V
RXO
Lew-level outpUt voltage
MAX
5
SQRXO
VOL
TYpt
50
RXO
VOH
MIN
kC
-675
mV
-500
-700
mV
-1.9
-2.1
driver and receiver
ICC
Supply current
VCC = 5.25 V,
No load
Driver outputs disabled,
70
t All typical values are at VCC = 5 V, TA = 25°C.
* The algebraic convention, in which the less positive (more negative) limit Is designated as minimum, is used in this data sheet for common-mode
input voltage VIC and threshold levels Vr + and Vr _
1ExAs
~
INSIRUMENIS
2-128
POST OFFICE BOX 6S5303 • DAUAS, TEXAS 75265
SN75061
DRIVER/RECEIVER PAIR WITH SQUELCH
SLLS026C - 02959, JANUARY 1987 - REVISED JULY 1990
switching characteristics, VCC
= 5 V, TA = 25°C
driver
PARAMETER
TEST CONDITIONS
SR
Differential-output slew rate
VO=-2Vto2\1,
RL =100 0 (differential),
tdD
Differential-output delay time
(tdD+ and tdD-)
Cl = 15pF,
RL =100 0 (differentlaQ,
See Figure 2
tdD+-tdD-
Differential-output delay time difference
RL =100 0 (differentlaQ,
See Figure 2
tpHZ
tpLZ
tpHZ
tpLZ
tpZH
tw(en)
See Figure 1
MIN
TYP
MAX
UNIT
2S
40
52
mV/ns
160
ns
5
ns
220
ns
Disabled time from DATEN
See Figure 3, 4, and 5
Enable time from DATEN
Enable time from OLEN
Enable pulse duration time (wHh OLEN low)
Cext = 100 pF,
See Figure 6
Rext =62 kO,
300
ns
220
ns
290
ns
250
ns
J.IS
2
2.5
3
MIN
TYP
MAX
receiver
PARAMETER
TEST CONDITIONS
UNIT
ns
ten (RX)
Receiver enable time
Squelch off,
See Figure 7
117
tpLH
Propagation delay time, low-to high level output
Squelch off,
See FigureS
20
35
ns
tpHL
Propagation delay time, high-to-Iow level output
Squelch off,
See FigureS
22
35
ns
1.2
1.45
J.IS
lS0
ns
td(unsq)
Cext= 50pF,
See Figure 9
Rext = 51 kO,
Cext = 15pF,
See Figure 9
Rext = 6.S kO,
1
Unsquelch delay time
PARAMETER MEASUREMENT INFORMATION
5V
Rext=62kO
3V
;F
Cext = 100 pF
Input
/
OV
----J
OLEN at3 V - - - - - - - - ,
1-....- - - - - - . , . - DRO+
Output
P-<__.-----1- DRO-
-..;~~t-
OutP_ut_ _
DATEN at 0.5 V
tr
~
TEST CIRCUIT
1+
------~
+j 1+
_ 4V
SR - tr or ~
OV
-2V
tf
VOLTAGE WAVEFORMS
NOTE A: The input pulse is supplied by a generator having the following characteristics: PRR " 1 MHz, duty cycle" 50%, tr " 6 ns, tf" 6 ns,
ZO=500.
Figure 1. Driver Slew Rate Test Circuit and Voltage Waveforms
1ExAs~
1NSIRUMENTS
POST OFFICE BOX 655303 • DAUAS, TEXAS 75265
2-129
SN75061
c
DRIVER/RECEIVER PAIR WITH SQUELCH
SUS026C - 02959, JANUARY 1987 - REVISED JULY 1990
PARAMETER· MEASUREMENT INFORMATION
SV
~
OROLAJ
, Rext =62 kO
~
3V
Cext= 100pF
OLEN at 3 V - - - - - - - - ,
~j2
RL=1000
Oenerator
(see Note A)
f4
II
DATEN at o,s V
1
1
Output
I
ov
i+-tclo-t
_----~I_--- Vo+
RL=1000
Output
---o----C
S2
Input
3
VO-
-=-
t S1 end S2 open
PE-64352
or Equivalent
(saeNoteD)
CL=1SpF
(sae Note B)
VOLTAOE WAVEFORMS
TEST CIRCUIT
Figure 2. Driver Differential Delay Times Test Circuit and Voltage Waveforms
SV
Rext=62kO
OROLAJ
OLEN at 3 V - - - - - . . . ,
T
-=-
Cext = 100 pF
Output
~
Input
I
ORII!t 0 V or 3 V - - - - - - I
I ..
tPZH ~
CL=50pF
(see Note B)
tPZH -i4+j
+
~I
~-- VOH
RL=100Q
Output
-=-
3V
.SV1'SV. I
- , - - - OV
,
I I O.SV
.
I
-2.3V
-
I
Oenerator
(aee Note C)
VOLTAOE WAVEFORMS
TEST CIRCUIT
Figure 3. Driver El)able and .Dlsable Time Test Circuit and Voltage Waveforms
NOTES: A. The Input pulse is supplied by a generalor having Ihe following characteristics: PRR s 1 MHz, duty cycle s 50%, Ir s 6 ns, If s 6 ns,
~=50n·
.
B. CL includes.probe and Jig capackance.
C. The inpul pulse Is supplied by a generalor having Ihe following characteristics: PRR s 500 kHz, duty cycle s 50%, Ir s 6 ns, If s 6 ns,
ZO=50n
D. Whim. measuring differenlial-outpul delay lime difference, swHches S1 and 82 are closed. (Isolation Iransformer from Pulse
Engineering PIN PE-64352).
1ExAs
~
INSIRUMENTS
2-130
POST OFFICE BOX e553O:J. DAUAS, TEXAS 75265
SN75061
DRIVER/RECEIVER PAIR WITH SQUELCH
SLlS026C-02959, JANUARY 1987-REVISEOJULY 1990
PARAMETER MEASUREMENT INFORMATION
5V
Rext=62kO
T
~
-
Cext=1oopF 5V
3V
Input
OLEN at 3 V - - - - - - - ,
1
1
RL=1OO0
ORIatOVor3V - - - - I
Lr~--
__-
tPZL -+J
Output
I+-
1
1--1
IPZL -+1
OV
I+-
1I
Output~
- 2,3 V
CL=50pF
(_Note B)
-5V
--VOL
Generator
(see Note A)
+
0,5 V
500
VOLTAGE WAVEFORMS
TEST CIRCUIT
Figure 4. Driver Enable and Disable Time Test Circuit and Voltage Waveforms
5V
Rext=62kO
OROLAJ
T
~
-1,5V
\\
---3V
eext = 100 pF
Input
I
OLEN at 3 V - - - - - - - ,
'---
OV
tPZH-k--.J
\ ) - -......GENERATOR
(see Note C)
~
I
Output
Output
1
- 2.3 V
----VOH
,
, ' -___ 0 V
RL= 1000
TEST CIRCUIT
VOLTAGE WAVEFORMS
Figure 5. Enable Times From Delay Ena.ble Test Circuit and Voltage Waveforms
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR '" 200 kHz, duty cycle", 50%, tr '" 6 ns, tf '" 6 ns,
ZO=50o.
B. CL Includes probe and jig capac~ance.
.
C. The input pulse Is supplied by a generator having the following characteristics: PRR s 1 MHz, duty cycle s 50%, tr'" 6 ns, tf'" 6 ns,
ZO=50o.
.
1ExAs ~
INSIRUMENTS
POST OFFICE BOX 655303 • DAUAS. TEXAS 75265
2-131
SN75061
DRIVER/RECEIVER PAIR WITH SQUELCH
SLl.S026C - D2959, JANUARY 1987 - REVISED JULY 1990
PARAMETER MEASUREMENT INFORMATION
5V
Rext=62 kg
~ Cext = 100 pF
OLEN at 0.5 V - - - - - - - ,
Generator
-::r:-
(eeeNoteA)
-=-
-=-
CL
=50 pF
(S88 Note B)
)
TEST CIRCUIT
Inpu~
, , - - - - ::
I+---- tw(en~
1
1- 2.3V
0,5 V .
__ VOH
of.
-,
OV
VOLTAGE WAVEFORMS
Figure 6. Enable Pulse Duration With Delay Enable Low Test Circuit and Voltage Waveforms
5V
Rext=51 kg
SQOLAJ
Generator
(S88 Note C)
-::r:-
~
- 1.5 V 1.5 V -
Input
Cext = 50 pF
i
.....
1.GV
RXO
RXISQRXO
SQOU
---
CL= 15pF
(see Note B)
ov
I+- ten(RX)
~
1I
output
Output
Open SQTHAJ
3V
1•3V
1.3V
VOH
----'VOL
VOLTAGE WAVEFORMS
TEST CIRCUIT
Figure 7. Receiver Enable (Unsquelch) Time Test Circuit and VoHage Waveforms
NOTES: D. The input pulse is supplied by a generalor having Ihe following characteristics: PRR $ 200 kHz, duty cycle $ 50%, tr $ 6 ns, tf $ 6 ns,
ZO=50g.
E. CL includes probe and jig capacftance.
F. The Input pulse is supplied by a generator having the following characteristics: PRR $ 500 kHz, duty cycle $ 50%, tr $6 ns, tf $ 6 ns,
ZO=50a.
1ExAs
2-132
..If
INSIRUMENTS
POST O.FFICE BOX 655303 • DAUAS, TEXAS 75265
SN75061
DRIVER/RECEIVER PAIR WITH SQUELCH
SLLS026C - 02959, JANUARY 1997 - REVISED JULY 1990
PARAMETER MEASUREMENT INFORMATION
5V
saOLAJ
Rext =51 kO
---3V
~
-1,5 V 1.5 V -
Generator
(see Note A)
Input
T
,
,
,
Cext=50pF
tpLH -+I
'OV
I+-
t4-
..... ,
,
Output
tpHL
' - - _ . VOH
.. ~-=--'
-.7f""'v
Output
I.'" V " ' - - - -
T
3V
CL=15pF
(see Note B)
VOL
VOLTAGE WAVEFORMS
TEST CIRCUIT
Figure 8. Receiver Propagation Delay Time Test Circuit and Voltage Waveforms
5V
SaOLAJ
Rext=51 kO
Generator
(see Note C)
T
Cext=50pF
Inp~-l,5V
II
1 . 5 V - r - 3V
~L __ -ov
I
tcI(unsq) .....,
Output
Output
~-1.3V
t4,
1.3V
~
VOH
~---VOL
VOLTAGE WAVEFORMS
TEST CIRCUIT
Figure 9. Unsquelch Duration Time Test Circuit and Voltage Waveforms
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR " 1 MHz, duty cycle" 50%, t r -" 6 ns, tf" 6 ns,
ZO=500.
B. CL includes probe and jig capackance.
C. The input pulse is supplied by a generator having the following characteristics: PRR " 100kHz, duty cycle" 50%, tr " 6 ns, tf" 6 ns,
ZO=500.
POST OFFICE BOX 655303 • DAUAS, TEXAS 75265
2-133
2-134
SN65076B,SN75076B
DIFFERENTIAL BUS TRANSCEIVERS
JANUARY 1990
o OR P PACKAGE
• Bidirectional Transceiver
• Designed for Multipoint Transmission In
Noisy Environments Such as Automotive
Applications
R08
{TOP VIEW)
• 3-State Driver and Receiver Outputs
• Individual Driver and Receiver Enables
• Wide Positive and Negative Input/Output
Bus Voltage Ranges
RE
2
7
Vee
A
o
3
6
B
GND
4
5
GND
logic symbol t
• Driver Output Capability .•. ± 10 mA Max
• Thermal Shutdown Protection
• Driver Positive and Negative Current
Limiting
r---------~
RE 2
7
I - _..........-A
6
p..--+.......-B
t-----::-I
R---'9
3
0----1
• Receiver Input Impedance •.. 12 kg Min
• Receiver Input Sensitivity •.. ±200 mV
• Receiver Input Hysteresis ... SO mV Typ
• Operates From Single S·V Supply
• Low Power Requirements
t This symbol is in accordance with ANSI/IEEE Std 91-1984 and
lEe Publication 617-12.
logic diagram (positive logic)
description
The SN65076B and SN75076B differential bus
transceivers are monolithic integrated circuits
designed for bidirectional data communication on
multipoint bus transmission lines. They are
designed for noisy environments, where a
low-impedance termination to ground is required.
0
~
3
R: =2=====_~ : :
: : } BUS
The SN65076B and SN75076B combine a differential line driver and a differential input line receiver, both of
which operate from a single 5-V power supply. The receiver has an active-low enable. The driver differential
outputs and the receiver differential inputs are connected internally to form differential input/output (110) bus
ports that are designed to offer minimum loading to the bus whenever the driver is disabled or
Vee = O. These ports feature wide positive and negative common-mode voltage ranges making the device
suitable for party-line applications.
Function Tables
DRIVER
INPUT
RECEIVER
0
OUTPUTS
A
B
H
L
H
Lt
L
Ht
t These levels assume that the
open-collector outputs (A) and
the open-emitter outputs (6) are
connected to a pullup and
pulldown resistor. respectively.
DIFFERENTIAL INPUTS
A-B
ENABLE
RE
OUTPUT
R
VI02:0.2V
L
L
-0.2 V < VIO< 0.2V
VIO" -0.2 V
L
L
H
?
X
H
Z
H =high level. L =low level. ? =indeterminate;
X = irrelevant. Z = high impedance (oft)
Copyright © 1990. Texas Instruments Incorporated
1ExAs'"
INSIRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
2-135
SN65076B,SN75076B
DIFFERENTIAL BUS TRANSCEIVERS
SLLS061 - 03407. JANUARY 1990
description (continued)
The driver is designed to handle loads up to 10 mA of sink and sOurce current. The driver features positive- and
negative-current limiting and thermal shutdown for protection from line fault conditions. Thermal shutdown is
designed to occur at a junction temperfiture of approximately 150°C in the P package and 170°C in the D
package. The receiver features a minimum input impedance of 12 kO, an input sensitivity of :t200 mY, and a
typical input hysteresis of 50 mY.
.
.
The SN65076B is characterized for operation from -40°C to 105°C and the SN75076B is characterized for
operation from O°C to 70°C.
EQUIVALENT OF EACH INPUT
TYPICAL OF A I/O PORT
V C C - - - - -......
.... - - vcc
--._-~...---~
Input
--*-+_--4...--....--4.... - Driver Input: Req = 3 kg NOM
TYPICAL OF RECEIVER OUTPUT
TYPICAL OF B I/O PORT
- - - - - - . . - -...... - - VCC
---~~-VCC
85Q
NOM
Output
--~+_--4-._--41--
-
GND
1ExAs ."
2-136
INSIRUMENIS
POST OFFICE BOX 655303 • DALLAB. TEXAS 75265
GND
SN65076B, SN75076B
DIFFERENTIAL BUS TRANSCEIVERS
SUS061-D3407, JANUARY 1990
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) ............................................................. 7 V
Voltage range at any bus terminal ................................................... -10 V to 15 V
Enable input voltage ....................................................................... 5.5 V
Continuous total power dissipation ..................................... See Dissipation Rating Table
Operating free-air temperature range: SN650768 .................................. -40°C to 105°C
SN750768 ...................................... O°C to 70°C
Storage temperature range ....................................................... -65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from the case for 10 seconds ............................ 260°C
NOTE 1: All voltage values, except differential input/output bus voltage, are with respect to network ground terminal.
DISSIPATION RATING TABLE
PACKAGE
TA" 25°C
POWER RATING
D
P
DERATING FACTOR
ABOVE TA = 25°C
TA 70°C
POWER RATING
=
TA 105°C
POWER RATING
=
725mW
5.8mWrC
464mW
261 mW
1100mW
8.8mWrC
702mW
396mW
recommended operating conditions
Supply voltage, VCC
MIN
NOM
MAX
UNIT
4.75
5
5.25
V
12
Voltage at any bus terminal (separately or common mode), VI or VIC
High-level Input voltage, VIH
Dand RE
Low-level Input voltage, VIL
Dand RE
-7
Low-level output current, IOL
V
2
0.8
V
%12
V
Driver (A)
-10
mA
Receiver
-400
Driver (B)
10
Receiver
8
Differential input voltage, VID (see Note 2)
High-level output current, IOH
V
.
ISN65076B
Operating free-air temperature, TA I
SN75076B
-40
105
0
70
"'"
mA
°c
NOTE 2: Differential-Input/output bus voltage is measured at the noninverting terminal A with respect to the inverting terminal B.
POST OFFICE BOX 655303 • DAUAS, TEXAS 75265
2-137
SN65076B, SN75076B
DIFFERENTIAL BUS TRANSCEIVERS
SLLS061 - 03407. JANUARY 1990
DRIVER SECTION
electrical characteristics over recommended ranges of supply voltage and operating free-air
.
temperature
PARAMETER
TEST CONDInONS
VIK
Input clamp voltage
II =-18mA
Vo
Output voltage
VI=2V.
VOD1
Differential output voltage
10=0
VOD2
Differential output voltage
See Figure 1
MIN
V
6
V
1.5
6
V
1.5
5
V
IVO=12V
1
I VO=-7V
-0.8
10
Output current
VI=0.8V
IIH
High-level Input current
VI=2.4V
20
IlL
Low-level Input current
VI=0.4V
-400
VO=-7V
-250
VO=O
-150
lOS
Short-circuit output current
ICC
Supply current (total package)
switching characteristics, Vee
PARAMETER
Ion
Differential-output turn-on time
toff
Differential-output turn-off time
VO=VCC
250
VO=12V
250
30
No load
mA
tIA
tIA
mA
mA
=5 V, TA =25°C
TEST CONDITIONS
See Figure 3
1ExAs . "
INSIRUMENTS
2-138
UNIT
-1.5
0
10=0
MAX
POST OFF1CE BOX 6155303 • DAUAS. TEXAS 75265
MIN
TYP
MAX
60
90
UNIT
lIS
75
110
lIS
SN65076B,SN75076B
DIFFERENTIAL BUS TRANSCEIVERS
SUS061 - 03407, JANUARY 1990
RECEIVER SECTION
electrical characteristics over recommended ranges of common-mode input voltage, supply
voltage, and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYpt
MAX
0.2
UNIT
Vr+
Vr-
PosHIve-golng Input threshold voltage
VO=2.7V,
10=-0.4mA
Negative-going Input threshold voltage
VO=0.5V,
10=8mA
Vhvs
Hysteresis (\IT+- VT...)
VIK
Enable-Input clamp voltage
11=-18mA
VOH
High-level output voltage
VID = -200 mV,
See Figure 2
10H =-400 lOA,
VOL
loW-level output voltage
VIO = -200 mV,
See Figure 2
IOL=8 rnA,
10Z
High-Impedance-state output current
Vo = 0.4 Vto 2.4 V
II
Une input current
Other input = 0 V,
VI =-7V,
IIH
High-level enable-input current
VIH=2.7V
20
IlL
Low-level enable-input current
VIL=0.4V
-100
lOA
lOA
-85
rnA
30
rnA
-0.2:1:
V
mV
50
ri
Input resistance
lOS
Short-circuit output current
ICC
Supply current (total package)
V
-1.5
2.7
V
V
VI=12V,
See Note 3
0.45
V
",20
lOA
1
-0.8
rnA
kQ
12
-15
No load
t All typical values are at VCC = 5 V. TA = 25"C.
:I: The algebraic convention, In which the less-positive (more-negative) limit is deSignated minimum, is used in this data sheet for threshold voltage
levels only.
NOTE 3: This applies for both power on and power off.
switching characteristics,
Vee =5 V, CL =15 pF, TA =25°C
PARAMETER
TEST CONDITIONS
tpLH
Propagation delay time, low-to-high level output
tpHL
. Propagation delay time, high-to-Iow level output
tpZH
Output enable time to high level
tpZL
Output enable time to low level
tpHZ
Output disable time from high level
tpLZ
Output disable time from low level
VIO = Oto 3 V.
See Figure 4
See Figure 5
See Figure 5
MIN
UNIT
TYP
MAX
21
35
23
35
ns
10
20
ns
ns
12
20
ns
20
35
ns
17
25
ns
TEXAS'~
INSIRlJMENIS
POST OFFICE BOX 655303 • DALlAS, TEXAS 75265
2-139
SN65076B,SN75076B
DIFFERENTIAL BUS TRANSCEIVERS
SLLS061 - 03407, JANUARY 1990
PARAMETER MEASUREMENT INFORMATION
BV
9100
4500
..........t-----'-+-- B
P-....1-~
9100
Figure 1. Driver VOD2
Figure 2. Receiver VOH and VOL
5V
Input
9100
Generator
500
(see Note A)
9100
~
\~5~
!1.5V
I
A
ton
B
CL=50pF
Input
(see Note B)
ov
i-I- toff
50%~
--l-i
!
3.5 V
50%
.
TEST CIRCUIT
3V
I
' ' - - -lV
VOLTAGE WAVEFORMS
Figure 3. Driver Differential-Output Delay Times
Input
Generator
(see Note A)
".5V
I
I
510
tpLH~
1.BV
.
OV _ _- - I
Output
~.;v--
3V
ov
I
I
~tpHL
~~~.-VOH
~1.3V
~
.VOL
TEST CIRCUIT
VOLTAGE WAVEFORMS
Figure 4. Receiver Test Circuit and Voltage Waveforms Propagation Delay Times
NOTES: A The input pulse is supplied by a generator having the following characteristics: PRR s 500 kHz, 50% duty cycle, tr s 6 ns, tf S 6 ns,
ZO=50n
B. CL includes probe and jig capacftance.
1ExAs
2-140
,If
INSIRUMENrS
POST OFFICE SOX 6StI303 • DAllAS, TEXAS 75265
SN65076B, SN75076B
DIFFERENTIAL BUS TRANSCEIVERS
Su.s061 - 03407, JANUARY 1990
PARAMETER MEASUREMENT INFORMATION
_~",-S1
1.5V
-1.5V
---0
>--.----~~
I
Generator
(see Note A)
CL=15pF
(see Note B)
2 kO
S.,3-O---5V
__~~~~-if
1N916 or Equivalent
5kQ
500
TEST CIRCUIT
Input
S1t01.5V
S20pen
S3Closed
1.5V
1
1 '---tPZH-l l+-
S1to-1.5V
S2Closed
S30pen
OV
ov
. 1
Output
~
1-
VOH
-----OV
S1 to 1.5V
S2Closed
S3Closed
OV
Input
1
1
Output
1
1
1
T--
VOL
tpLZ~
1
....z...~1
0.5 V
-4.5 V
3V
S1 to-1.5V
S2Closed
S3Closed
' - - - OV
Input
tPHZ~
Output
;---i~::.
----.l
L
1.5V
VOH
I
Output
1
1
-1.3V
VOLTAGE WAVEFORMS
Figure 5. Receiver Output Enable and Disable Times
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR :s 500 kHz, 50% duty cycle, tr:S 6 ns, tf:S 6 ns,
ZO=500.
B. CL includes probe and jig capacitance.
TEXAS'"
INSIRUMENTS
POST OFFICE BOX 655300 • DAUAS, TEXAS 75265
2-141
SN65076B, SN75076B
DIFFERENTIAL BUS TRANSCEIVERS
SUS061- 03407, JANUAR'I1990
.TYPICAL CHARACTERISTICS
RECEIVER HIGH-LEVEL OUTPUTt
RECEIVER HIGH-LEVEL OUTPUT VOLTAGE
va
vs
HIGH-LEVEL OUTPUT CURRENT
FREE-AIR TEMPERATURE
5
,
>
II
I
I
I
VID=0.2V
TA=25·C
,
>
II
~
3
~~
~ ~V
0
2
~.
,
.p
r-
IOH=-~.,A
-w
3
r-
0
VCC=5.25V
I
]
I
V VCC =5V
-~
-~
2
.c
at
:i:
,
:J:
.p
~~
o
VCC=5V
VIO=200mV
5
~~
~~
VCC = 4.75 V
:J:
o
~
5a.
I~ ~
.c
:J:
4
I
r-
I
"'~"~
I.!
!
-
4
at
i
5
-~
o
-~
-~
-~
IOH - High-Level Output Current - mA
0
~
~
60
80
100
TA - Free-Air Temperature _·c
Figure 6
Figure 7
RECEIVER LOW-LEVEL OUTPUT VOLTAGE
,
>
0.5
va
RECEIVER LOW-LEVEL OUTPUT CURRENT
FREE-AIR TEMPERATURE
I
-
VCC=5V
TA=25·C
CD
OJ
II
~
0.4
5
g-
O
0.3
I,
0.2
.p
0.1
oJ
o
RECEIVER LOW-LEVEL OUTPUT VOLTAGEt
vs
0.6
./
/
o
/
V
V'
V
/
0.6
V
,
>
i
~
_·1
_I_
I
VCC=5V
VIO=-200mV
0.5 f- IOL=8mA
0.4
i -
I
/
0.3
0.2
'oJ
.p
5
10
15
~
25
~
0.1
o
-~
-~
IOL - Low Level Output Current - mA
0
~
~
60
80
TA - Free-Air Temperature _·C
Figure 8
Figure 9
t Only the O·C to 70·C portion of the curve applies for the SN7~76B.
.1ExAs ~
.INSIRUMENfS
2-142
1~
POST OFFICE BOX 6S5303 • DAllAS. TEXAS 75265
100
1~
SN65076B,SN75076B
DIFFERENTIAL BUS TRANSCEIVERS
SLl.S061-D3407, JANUARY 1990
TYPICAL CHARACTERISTICS
RECEIVER OUTPUT VOLTAGE
RECEIVER OUTPUT VOLTAGE
va
va
ENABLE VOLTAGE
ENABLE VOLTAGE
6
5
>
r4 r-
VIO = 0.2 V
Load = 8 kg to GNO
TA = 25°C
II
I
i
~
I
I
--
>
fJ" Vce=4.75V
.
0.5
Vee = 4.75 V
i
4
i
o
3
~
2
I
~
o
1.5
2.5
2
VIO=-0.2V
Load = 1 kg to Vee
TA=25"C
~
-
I
VCC=5V
~
2
o
.l
5
-
I
Vee = 5 V""'"
3
.t
I
Vce=5.25V
I
VCC=5.25V
3
o
o
0.5
VI- Enable Voltage - V
1.5
2
2.5
3
VI- Enable Voltage - V
Figure 10
Figure 11
APPLICATION INFORMATION
Vee
Vce
Figure 12. Typical Application Circuit
1ExAs
-If
INSIRUMENTS
POST OFFICE BOX 655303 • DAU.AS, TEXAS 75265
2-143
2-144
SN75ALS085
LAN ACCESS UNIT INTERFACE DUAL DRIVER/RECEIVER
R~SEDFEBRUARY1~
ow OR NT PACKAGE
• Compatible With lOS 8802.3:1989 and
ANSI/IEEE Std 802.3-1988
• Interdevlce loop-Back Paths for Systetri
Testing
• Squelch Function Implemented on the
Receiver Inputs
• Drivers Will Drive a Balanced 78-0 load
• Transformer Coupling Not Required In
System
• Power-Up/Power-Down Protection (Glitch
Free)
• Isolated Ground Pins for Reduced Noise
Coupling
• Fault-Condltlon Protection Built Into the
Device
• Driver Inputs Are level-Shifted ECl
Compatible
(TOP VIEW)
TXI1
TX01
TX01
Vee
RXEN1
RX01
RXEN2
GND
LOOP2
TXEN2
TXI2
RXI1
RXI1
GND
GND
RXI2
RXI2
Vee
TX02
TX02
description
The SN75ALS085 is a monolithic, high-speed, advanced low-power Schottky, dual-channel driver/receiver
device designed for use in the AUI of ANSI/IEEE Std 802.3-1988. The two drivers on the device drive a 78-0
balanced, terminated twisted-pair transmission line up to a maximum length of 50 meters. In the off (idle) state,
the drivers maintain minimal differential output voltage on the twisted-pair line and, at the same time, remain
within the required output common-mode range.
With the driver enable (TXEN) high, upon receiving the first falling edge into the driver input, the differential
outputs will rise to full-amplitude output levels within 25 ns. The output amplitude is maintained for the remainder
of the packet. After the last positive packet edge is transmitted into the driver, the driver will maintain a minimum
of 70% full differential output for a minimum of 200 ns, then decay down to a minimum level for the reset (idle)
condition within 8 lIS. Disabling the driver by taking the driver enable low will also force the output into the idle
condition after the normalS-lIS timeout. While operating, the driver is able to withstand a set of fault conditions
and not suffer damage due to the faults being applied. The drivers power up in the idle state to ensure that no
activity is placed on the twisted-pair cable that could be interpreted as network traffic.
The line receiver squelch function interfaces to a differential twisted-pair line terminated external to the device.
The receiver squelch circuit allows differential receive signals to pass through as long as the input amplitude
and pulse duration are greater than the minimum squelch threshold. This ensures a good signal-to-noise ratio
while the data path is active and prevents system noise from causing false data transitions during line shutdown
and line-idle conditions. The AXO outputs default to a high level and the RXEN outputs default to a low level
while the squelch function is blocking the data path through the receiver (idle). The line receiver squelch will
become active within 50 ns when the input squelch threshold is exceeded. RXEN will be driven high when the
squelch circuit is allowing data to pass through the receiver. The receiver squelch circuit can also withstand a
set of fault conditions while operating without causing permanent damage to the device.
~"'"
Copyright © 1993, Texas Instruments Incorporated
INSIRUMENTS
POST OFFICE BOX 85530G • DALlAS. TEXAS 75265
2-145
SN75ALS085
LAN ACCESS UNIT INTERFACE DUAL DRIVER/RECEIVER
SlLS054A- 03279. APRIL 1989 - REVISED FEBRUARY 1993
description (continued)
The purpose of the loop functio.ns is to provide a means bywhich system data path verification can be done to
isolate faulty interfaces and assist in network diagnosis. The LOOP pins are TTL compatible and must beheld
high for normal operation. When LOOP1 is taken low, the output of driver 1 (TX01) immediately goes into the
idle state. Also, the input to receiver 1 is ignored and a path from TXI1 toRX01 is established. When LOOP1
is taken back high, driver 1 and receiver 1 revert back to their normal operation. When LOOP2 is taken low, a
similar data path is established between TXI1 and RX02. TXEN1 must be high for the loop functions to operate.
and TXEN1 can be used to gate the loop function if desired. During loop operation, the respective receiver
enable output (RXEN) will reflect the status of TXEN1.
.
Function Tables
RECEIVER - LOOP
=H
OUTPUTS
PREVIOUS RXEN
RXEN
RXO
tw<25ns
L
L
H
tw>50ns
X
H
L
tw< 142ns
H
H
H
tw> 187ns
X
L
H
RXI
=1315 mVt6-175 mY.
VID =-275 mVto -1315 mY.
VIO =318 mVto 1315 mY.
VIO =318 mVto 1315 mV,
VIO
DRIVER -
LOOP =H
TXI
TXEN
PREVIOUS TXO
OUTPUTTXO
L
L
Idle
Idle
H
L
Idle
Idle
~
H
Idle
L
L
H
Active
L
H<260jts
H
Active
H
H>8jtS
H
Active
Idle
L
L>8jtS
Active
Idle
H<260ns
L>8jtS
Active
Idle
H<260ns
L<260ns
Active
H
H>8jtS
L<260ns
Active
Idle
L
L<260ns
Active
L
H =VI"' VT max. L =VIs VT min
LOOP
OUTPUTS
INPUTS
LOOP1
LOOP2
TXl1
TXEN1
RXl1
RXl2
RX01
RX02
RXEN1
RXEN2
TX01
L
L
L
H
L
H
H
. Idle
L
L
H
H
H
H
H
H
X
L
X
X
X
L
L
H
H
L
L
Idle
Idle
L
H
H
H
L
X
X
X
X
X
X
L
Normal
Normal
Normal
H
H
L
Normal
Normal
Normal
Idle
Idle
Idle
L
H
Normal
H
Idle
Normal
Normal
L
H
Normal
H
Normal
H
Idle
L
Normal
Normal
Normal
Normal
Normal
H
Normal
Normal
Normal
L
Normal
Idle
Normal
L
H
L
L
L
H
H
H
L
L
H
H
L
H
X
H
Normal
H
H
X
Normal
Normal
Normal
X
X
X
Normal
H
H
Normal
=hIgh level. L =low level. X =don't care
lExAs.Jf
INSIRUMENTS
2-146
POST OFFICE BOX 655303 • DAllAS; TEXAS 75265
SN75ALS085
LAN ACCESS UNIT INTERFACE DUAL DRIVER/RECEIVER
Sll.S054A- 03279. APRIL 1989 - REVISED FEBRUARY 1993
logic diagram (positive logic)
RX11
RX11
RXEN1
RX01
LOOP1
TX01
TX01
TXI1
TXEN1
LOOP2
RX02
RXI2 ~I+-'Wv----r.....
RXl2 ...!..:j.........WIr-f-t-a...-
RXEN2
b-.-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
TXl2
'--_--'
~
.....
~--~~TX02
o-........-+--'=-
TX02
TXEN2 - - - ' - ' - - - - - - - - - l - J
1ExAs..lf
INSIRUMENrS
POST OFF1CE BOX 6S5303 • DALlAS. TEXAS 75265
2-147
SN75ALS085
LAN ACCESS UNIT INTERFACE DUAL DRIVER/RECEIVER
I
SLLS054A- 03279, APRIL 1989- REVISED FEBRUARY 1993
schematics of inputs and outputs
RXI AND RXIINPUTS
LOOP AND TXEN INPUTS
Vee
Vee
20 kg
LOOP
and -
.....-.-1
TXEN
TXlINPUTS
. RXO AND RXEN OUTPUTS
Vee
Vee
SOg
5kg
RXO
. - - . . - - and
RXEN
2-148
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN75ALS085
LAN ACCESS UNIT INTERFACE DUAL DRIVER/RECEIVER
Sll.S054A- 03279. APRIL 1989 - REVISED FEBRUARY 1993
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) ............................................................. 6 V
TXI and LOOP input voltage ................................................................ 5.5 V
TXO and TXO output voltage ............................................................... 16 V
RXI and RXI input voltage .................................................................. 16 V
RXO and RXEN output voltage ............................................................. 5.5 V
Continuous total power dissipation ..................................... See Dissipation Rating Table
Operating free-air temperature range .................................................. O·C to 70·C
Storage temperature range ...................................................... - 65°C to 150 ·C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds ............................... 260·C
NOTE 1: Voltage values are with respect to network ground terminal.
DISSIPATION RATING TABLE
DERATING FACTOR
ABOVE TA 25"C
TA=7O"C
POWER RATING
1350mW
10.BmW/"C
864mW
1250mW
10.0mW/"C
800mW
PACKAGE
TAs25"C
POWER RATING
OW
NT
=
recommended operating conditions
Supply voltage. VCC
Common-mode voltage at AXI inputs. VIC
Differential vo~age between AXI inputs. VID
High-level Input vo~ge. LOOP and lXEN. VIH
MIN
NOM
MAX
UNIT
4.75
5
5.25
V
1
4.2
",318
'" 1315
2
Low-level input voltage. LOOP and lXEN. Vil
V
0.8
High-level output current. AXO and AXEN. IOH
Low-level output voltage. AXO and AXEN. IOl
V
mV
V
-0.4
mA
16
mA
Setup time. driver mode. lXEN high before lXl ~. tsu1 (see Figure 8)
10
Setup time. loop mode. lOOP low beforeTXENt. tsu2 (see Figure 10)
15
Setup time. loop mode. lXEN high before lXll.\su3 (see Figure 10)
10
ns
ns
ns
Hold time. loop mode. lXEN high after lXl t. th1 (see Figure 9)
10
ns
Hold time. loop mode. LOOP low alter lXENl. th2 (see Figure 9)
15
Operating free-air temperature. TA
0
1ExAs
ns
70
"C
..If
INSIRUMENTS
POST OFFICE BOX 655303 • OAI.J..AS. TEXAS 75265
2-149
SN75ALS085
LAN ACCESS UNIT INTERFACE DUAL DRIVER/RECEIVER
SLlS054A- D3279, APRIL 1989 - REVISED FEBRUARY 1993
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
PARAMETER
VIK
II =-18mA
TA=O·C
VT
MIN
TEST CONDITIONS
Clamp voltage at al\ inputs
Driver Input (TXI) threshold voltage
TA=25·C
I
3,752
VCC=5V
3,389
3,998
VCC = 5.25 V
3.5n
4.244
VCC=4.75V
3.213
3.797
VCC=5V
3.400
4.043
VCC=5.25V
3.588
4.289
3.239
3.849
3.426
4.095
3.614
4.341
VCC=5V
,
VOC
VOD
Receiver differential Input threshold voltage
Driver output (TXO) common-mode voltage
Driver output (TXO) differential voltage
-275
Idle
TXEN at 0.8 V,
LOOP2at 2V,
LOOPl at2V,
See Figure 1
Active
TXENat2V,
LOOP2at 2V,
See Figure 1
Active
1
4.2
LOOP1 at2V,
TXI at 3.2 V,
1
4.2
TXENat2V,
LOOP2at 2V,
See Figure 1
LOOPl at2V,
TXI at4.4V.
1
4.2
Idle
TXEN at 0.8 V.
LOOP2at2V,
LOOP1 at2V.
See Figure 1
Active
TXENat2V,
LOOP2at2V.
See Figure 1
LOOP1 at2V.
TXI at 3.2 V,
-600
1315
Active
TXENat2V.
LOOP2at2V.
See Figure 1
LOOP1 at2V.
TXI at4.4V.
600
1315
VOH
High-level output voltage
RXO.RXEN
IOH=-D·4mA
VOL
Low-level output voltage
RXO.RXEN
IOL=16mA
TXEN.LOOP
VI=2V
IIH
High-level input current
TXI
VI=4.5V
RXI. RXI
VID=-0.5V.
TXEN. LOOP
IlL
100
lOS
ICC
Low-level Input current
Driver differential output current
Short-circuit output currentt
Supply current
100
4
VID =0.5V.
VIC = 1 Vto 4.2 V
Idle
TXEN at 0.8 V,
LOOP2at2V.
LOOP1 at 2 V.
See Figure 2
Vo at OV.
RXf at 3 V,
~lat2V
1ExAs
~
POST OFFICE BOX 655303 • DAUAS, TEXAS 75265
V
mV
V
!lA
-200
RXI,RXI
INSlRUMENTS
mV
1000
VIC = 1 Vt04.2V
VI =0.8V
LOOP2at2V,
TXI at 4.5 V,
V
20
400
VI=0.3V
RXO,RXEN
V
V
0.5
VI=3.1V
TXI
V
",40
2.4
TXENat2V.
Outputs open
t Not more than one output should be shorted at a time, and the duratton of the test should not exceed 1 second.
2-150
V
3,202
VCC=5.25V
VIDT
UNIT
-1,5
VCC = 4,75 V
VCC=4.75V
TA=70·C
MAX
10
mA
1000
-40
",4
mA
-150
mA
225
mA
SN75ALS085
LAN ACCESS UNIT INTERFACE DUAL DRIVER/RECEIVER
SLI.S054A- D3279, APRIL 1989 - REVISED FE;BRUARY 1993
electrical characteristics over recommended ranges of supply voltage and' operating free-air
temperature (unless otherwise noted) (continued)
PARAMETER
TEST CONDInONSt
TXO shorted to TXO,
Driver fauR condition current
Receiver fault condftion current
Current measured in short
MIN
MAX
UNIT
150
TXO at Ov,
TXO is open,
Current measured at TXO
150
TXOlsopen,
TXOatO,
Current measured at TXO
150
TXOatOV,
TXOatOV,
Current measured at TXO and 'iXO
150
TXOat16V,
'iXO is open,
Current measured at TXO
150
TXOisopen,
TXOat16V,
Current measured at TXO
150
TXOat 16V,
TXOat 16V,
Qurrent measured at TXO and 'iXO
150
AXI shorted to AXI,
Current measured in short
AXI atOV,
AXI is open,
Current measured at AXI
3
AXI Is open,
AXI atOv,
Current measured at AXI
3
AXlatOV,
RXI at Ov,
Current measured at AXI and RXf
AXlat 16V,
RXI atopen,
Current measured at AXI
10
AXlatopen,
RXI at 16V,
Current measured at AXI
10
AXlat 16V,
RXI at 16 V,
Current measured at AXI and AXI
10
mA
10
3
mA
t Fault conditions should be measured on only one channel at a time.
1ExAs . "
INSlRUMENIS
POST OFACE SOX 655303 • DAUAS, TEXAS 75265
2-151
SN75ALS085
LAN ACCESS UNIT INTERFACE DUAL DRIVER/RECEIVER
. Su.s054A- D~79, APRIL 1989 - REVISED FEBRUARY 1993
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature
driver
PARAMETER
FROM
(INPUT)
IpLH
Propagation delay time,
Iow-to-hlgh level output
TXI
TXO,
'i'XO
TXEN at2V,
See Figure 3
15
ns
tPHL
Propagation delay lime,
hlgh-to-Iow level output
TXI
TXO,
'i'XO
TXENaI2V,
See Figure 3
15
ns
IplL
Propagation delay time,
Idle-Io-Iow level output
TXI
TXO, 'i'XO
TXENaI2V,
See Figure 4
25
ns
IPIL
Propagation delay lime,
Idle-la-low level output
TXEN
TXO, TXO
TXla13.2V,
See Figure 5
25
ns'
Iw
Output pulse duration from lowlo-hlgh level 10 70% output level
TXO,
'i'XO
TXENaI2V,
See Figure 6
8000
ns
VOO(U)
Oriver output differential
undershoot voltage
TXI
TXO,
'iXO
TXENaI2V,
See Figure 6
-100
mV
Iskew
Oriver caused signal skew
IpLH-IPHL
TXI
TXO, TXO
TXENaI2V,
See Figure 3
%3
tr
Rise time, TXO, TXO
TXENat2V,
See Figure 3
1
5
ns
If
Fall time, TXO, 'iXO
TXENal2V,
See Figure 3
1
5
ns
MIN
MAX
TO
(OUTPUT)
TEST CONDITIONS
MAX
MIN
i
260
UNIT
ns
receiver
"ARAMETER
FROM
(INPUT)
TO
(OUTPUT)
IpLH
Propagation delay time,
low-to-high level output
AXI,RXI
AXO
V'C = 1 Vto 4.2 V, See Figure 11
15
ns
tpHL
Propagallon delay time,
high-Io-Iow level output
AXI,RXI
AXO
V'C = 1 Vto 4.2 V, See Figure 10
15
ns
IpLH
Start-up delay time,
low-to-high level output
AXI,RXI
AXEN
VIC = 1 Vto 4.2 V, V,O = -500 mV,
See Figure 12
55
ns
IpHL
Shutdown delay time,
high-IO-Iow level output
AXI,AXI
AXEN
V'C = 1 Vlo 4.2 V, V,O =500 mV,
See Figure 12
181
ns
'skew
Receiver caused signal
skew (tPLH - IpHU
AXI,AXI'
AXO
V'C = 1 Vlo 4.2 V, V,O = 500 mV,
See Figure 10
%3
os-
Iw
Pulse duration al AXI and AXI
(10 not activate squelch)
V'C = 1 Vlo 4.2 V, V,D=-175mV,
See Figure 11
Iw
Pulse duration al AXI and AXI
(10 activate squelch)
V'C = 1 Vlo 4.2 V, V,O = -275 mV,
See Figure 11
Irl
Rise time, AXO
V'C = 1 Vlo 4.2 V, V,O
See Figure 10
Ir2
Rise lime, AXEN
V'C 1 Vlo 4.2 V, V,O
See Figure 12
Ifl
Fall time, RXO .
V'C 1 Vlo 4.2 V, V,O = %500 mV,
See Figure 10
1f2
Fall lime, AXEN
V,C=2.5V,
See Figure 12
tvalid
AXO valid after RXEN high
See Figure 10
TEST CONDITIONS
=
1ExAs
2-152
..If
POST OFACE BOX 655303 • DAUAS, TEXAS 75265
ns
25
50
ns
=%500 mV,
1
8
ns
=%500 mV,
1
8
ns
1
8
ns
1
8
ns
-10
15
ns
=
INSIRlJMENTS
142
UNIT
V,O = %500 V,
SN75ALS085
LAN ACCESS UNIT INTERFACE DUAL DRIVER/RECEIVER
SLLS054A- D3279, APRIL 1989 - REVISED FEBRUARY 1993
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature
loop
TO
PARAMETER
FROM
(INPUT)
(OUTPUT)
IpLH
Propagation delay lime,
low-ta-high level output
TXI
RXO
LOOP at 0.8 V,
See Figure 13
TXEN at2V,
tpHL
Propagation delay time,
high-to-Iow level output
TXI
RXO
LOOP at 0.8 V,
See Figure 13
TXEN at2V,
tpLH
Propagation delay time,
low-la-high level output
TXEN
RXEN
LOOP at 0.8 V,
tpHL
Propagation delay time,
high-to-Iow level output
TXEN
RXEN
LOOP at 0.8 V,
TEST CONDITIONS
MIN
MAX
UNIT
30
ns
30
ns
See Figure 14
50
ns
See Figure 14
50
ns
PARAMETER MEASUREMENT INFORMATION
Vi'XO
390
TXI
390
VTXO
Voe
TXI
Figure 1
Figure 2
1ExAs . "
INSIRUMENI'S
POST OFFICE BOX 655303 • DAllAS, TEXAS 75266
2-153
SN75ALS085
LAN ACCESS UNIT INTERFACE DUAL DRIVERlRECEIVER
SU.8054A- 03279, APRIL 1989 - REVISED FEBRUARY 1993
PARAMETER MEASUREMENT INFORMATION
390
TXt
1!f1
VOD
0.011J,f
"±'
3kO
~-.----~~------~~ ~3kO
390
~25pF
.Jt
TEST CIRCUIT
TXI _ _ _ _
tpLH
TXO
60%
-.I I+-
~- - - - , - -
50%
--.I
I+-
tpLH
I
'
I ~---_!----- VOD
90%
90% !\-1ii%"-OV
+
OV-T~I
I
~
I+-tr
I
-+I
j+-tf
VOLTAGE WAVEFORMS
TRANSFORMER SPECIFICATIONS
Turns Ratio
Magnetizing Inductance
Winding Resistance
Rise lime 10% to 90%
Interwinding Capacitance
Leakage Inductance
Inductive Q
1:1
26t030"H
0.6 0 Max
5 ns Max
25 pF
0.25 "H Max
1250 Min
Figure 3. Test Circuit and Voltage Waveforms
2-154
:.:v
. 1ExAs'"
INSTRIJMENTS
POST OFFICE BOX 655303 • DAllAS, TEXAS 75265
VOD-
SN75ALS085
LAN ACCESS UNIT INTERFACE DUAL DRIVER/RECEIVER
SLLS054A- 03279. APRIL 1989 - REVISED FEBRUARY 1993
PARAMETER MEASUREMENT INFORMATION
Ilq'~
390
0.0111F
TXI
390
--::I:'
3kO
-=-
--::I:'
-=-
25 pF
-::-
t See Figure 3
TEST CIRCUIT
\~----:.:V
TXI
---x=
~,
,...
tPIL
-I---
TXO
IDLE
,
90%
VOD-
VOLTAGE WAVEFORMS
NOTE: Input Ir " 5 ns; If" 5 ns
Figure 4. Test Circuit and Voltage Waveforms
TXEN
390
IIN3kO
0.0111F
TXI
--::I:'
39 0
~-.----~.-------~~ ~ 3ko
--::I:'
25 pF
t See Figure 3
TEST CIRCUIT
2V
TXEN
./
---~4'+ -50% -
TXO
- - - O.B V
tPIL
...l_-- Idle
,
90%
VOD-
---x=
,...
.,
VOLTAGE WAVEFORMS
Figure 5. Test Circuit and Voltage Waveforms
1ExAs
..If
INSlRI)MENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
2-155
SN75ALS085
LAN ACCESS UNIT INTERFACE DUAL DRIVER/RECEIVER
SLLS054A- 03279, APRIL 1989 - REVISED FEBRUARY 1993
PARAMETER MEASUREMENT INFORMATION
390
IINSkO
VOD
TXI
--:::I:'
390
0.01 ",F
L-~-----e________~~ ~SkO
--:::I:' 2SpF
t See Figure 3
TEST CIRCUIT
- - VOH
TXO
500/0 [
-----1---~-=--:;@-VOL
/.- tw---+r
VOLTAGE WAVEFORMS
Figure 6. Test Circuit and Voltage Waveforms
2V
~_ _ _ _ _ _ _ O.BV
TXEN _ _ _ _(....,
14
~I
tsu1
'\~----
TXI
4.SV
.....- - - - S V
Figure 7
TXI__t....,~ __________ :.:V
~
"'1
t~------- 2V
TXEN
1
I
O.BV
j4-th2-+1
I
---JII'"'500/0-_-_
LOOP_ _ _ _ _ _ _
Figure 8
NOTE: Inpul Ir " 5 ns; If" 5 ns
1ExAs
~
INSIRUMENTS
2-156
POST OFFICE BOX 65i5303 • DAUAS. TEXAS 75265
:.:v
SN75ALS085
LAN ACCESS UNIT INTERFACE DUAL DRIVER/RECEIVER
Su.sOS4A- D3279. APRIL 1989 - REVISED FEBRUARY 1993
PARAMETER MEASUREMENT INFORMATION
~~--------
:.:V
~tau2
,.50%-_-_-_-_-_-_-_- :.: v
TXEN _ _ _ _....,f-yl
I+-
t su3-+/
I
- -_ _ _ _ _"""1
~:.:V
TXI
Figure 9
.----+----
RXEN
6kQ
20pF
>--+--.--
RXO
RXI
20pF
TEST CIRCUIT
----f--------~~~~~~ ~~V
RXI - - - - - - - \ '
I
I
I
I
4~--:---------J-----
RXEN
_ _ _ _ _ _ _01-
I
tvalid
RXO
-+' 14I
14+1-
tpLH
I
-+l1~
tpHL~
tr1
-----~'i:f
1.3V\
1.3V~n 90%
10%
~
I I_
-+i1-
IL
:OH
t f1
'Xb~/90%...~
10%
v
OH
VOL
VOLTAGE WAVEFORMS
Figure 10. Test Circuit and Voltage Waveforms
NOTE: Input Ir" 5 ns; If" 5 ns
..
TEXAS " ,
INSIRUMENIS
POST OFFICE BOX 655303 • DAUAS. TEXAS 75265
2-157
SN75ALS085
LAN ACCESS UNIT INTERFACE DUAL DRIVER/RECEIVER
I
SLLS054A- 03279, APRIL 1989 - REVISED FEBRUARY 1993
PARAMETER MEASUREMENT INFORMATION
,....--.....- -....6ke
RXEN
20pF
>------RXO
RXI
TEST CIRCUIT
~~~OV
1\'40mV
RXI
-1----- VIO
I .
I...
RXEN
jf-40mV
tw---+l
I
/,--_-_-_- :::
VOLTAGE WAVEFORMS
Figure 11. Test Circuit and Voltage Waveforms
,....--.....- -....6ke
RXEN
20pF
>------RXO
RXI
TEST CIRCUIT
1V
RXI~ -40mV
'-0"-- _ _ _ _ _ _ _
-1 V
t+- tpLH -+I
I
I+--
I
RXEN
10%):
90%
t PHL----:
~
I I
--.! 1+
90%
------"!I I
-.I
!+ tr2
tf2
VOLTAGE WAVEFORMS
Figure 12. Test Circuit and Voltage Waveforms
NOTE: Input tr :5 5 ns; If :5 5 ns
TEXAS ..,
INSIRUMENTS
2-158
POST OFFICE BOX 655303 • DAUAS, TEXAS 75265
SN75ALS085
LAN ACCESS UNIT INTERFACE DUAL DRIVER/RECEIVER
SLLS054A- 03279, APRIL 1989 - REVISED FEBRUARY 1993
PARAMETER MEASUREMENT INFORMATION
m
~50%
(~_ _ _ _ _ _ :.:V
I4---+r-
tpHL ~
----""'\1
RXO
tpLH
1
1_____
\1.3 V
1.3 V
VOH
VOL
Figure 13
--J{
TXEN ___
tpLH
RXEN
50%~
50%
~
-+I
-- --
14-
::V
tpHL
,..----\!.l-- - - VOH
1
__________--J!1.3V
1.3V"",-- VOL
Figure 14
NOTE: Input Ir '" 5 ns; If " 5 ns
TEXAS
..If
INSIruJMENfS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2-159
2-160
SN75LBC086
DIFFERENTIAL 1/0 DRIVER/RECEIVER PAIR
WITH SQUELCH, JABBER
AND COLLISION DETECTION
JUNE 1991 - REVISED SEPTEMBER 1991
•
Compliant With IEEE STD 802.31,
Type 10BASE-T
•
Differential (Twisted-Pair) VO
Driver/Receiver
•
•
•
•
High-Speed Receiver ••• tpd
OW PACKAGE
(TOP VIEW)
=50 ns Max
CLKOUT
X1
TXDATAA
X2
TXDATAB
TXEN
Receiver Squelch Circuit Integrity Improved
With Noise Filter
GND(L)
VCC(L)
GND(L)
Jabber Control Prevents Network lockup
3
4
5
6
•
Data link Integrity Monitored With Link
Test Pulse
•
Externally Addressable Test Register
Controls Signal Quality Error Testing
•
•
CMOS and Raised ECl Compatible
RXDATAB
RXEN
LOOP
LINK
TX+
TXGND(P)
VCC(P)
FULLD
RXDATAA
Collision Detection for Multiple-User
Networks
SQEEN
9
RX+
RXCTL
JABB
24-Pin, 300-mil Dual-In-Line Package
description
The SN75LBC086 is a single-channel differential driver/receiver interface device for the medium attachment
unit (MAU) used in 10-MHz twisted-pair Ethernet applications. The device uses a 5-V supply and is designed
to interface with two pairs of telephone-grade twisted-pair cables coupled through isolation transformers. The
functional components of the device include a differential receiver and driver, receiver squelch with noise filter,
jabber controls, collision detection, data link monitor, and signal quality error (SOE) testing. The LinBiCMOS™
process technology is used in the device design to ensure analog precision, low power, and high-speed
operation.
The device contains an elaborate receiver-squelch circuitt that provides an improved level of noise rejection
by qualifying the incoming Signal stream with three different criteria. First, the signal is compared to a set
threshold voltage level. Then, the pulse duration is compared to a set time window. Last, the signal must follow
a set pattern of positive and negative pulses before the circuit finally opens the receiver channel to the incoming
data packet.
The jabber control is designed to prevent a defective controller from locking up the network by limiting the data
packet transmission time to 20 to 30 ms. When a packet length exceeds 20 to 30 ms, the driver is turned off for
about 600 ms. The driver-enable input must be made inactive by the controller during this period before the
jabber control will release the driver. The JABB output is active (high) when a jabber condition exists.
Collision detection is used to arbitrate access to the multiuser network. This detection is done logically by
monitoring the receive line for a valid signal during a driver transmission. When a collision is detected, this device
informs the controller with an active-high CTL output. After a valid packet transm ission, the device also performs
a signal quality error test causing the CTL output to go active (high). This test is disabled when the SOEEN input
goes inactive (high).
The device tests data-link integrity during the idle state by periodically driving the driver line with a unipolar pulse
called a link-test pulse. The receiver looks for this link-test pulse on the receive line. A failed line link is indicated
by a high-impedance state at the LINK output. This output drives an LED for monitoring if needed.
t Embodies technology covered by one or more Digital Equipment Corporation Patents.
LinBiCMOS Is a trademark of Texas Instruments Incorporated.
1ExAs
,If
Copyright © 1991. Texas Instruments Incorporated
INSlRUMENJS
POST OFFICE BOX 655303 • DALlAS. TEXAS 75265
2-161
SN75LBC086
DIFFERENTIAL I/O DRIVER/RECEIVER PAIR
WITH SQUELCH, JABBER CONTROL, AND COLLISION DETECTION
SLLS120A- 03525, JUNE 1991 - REVISED SEPTEMBER 1991
description (continued)
An internal test register is externally controlled with inputs FULLD and LOOP to select the device testing mode.
When in the test mode, serial test-mode control patterns are clocked into the test register through input SQEEN.
These control patterns select various modes to test the internal circuits.
functional block diagram
18
VCC(P) -=6.;;......--...
VCC(L) -"-----+
FULLD 17
Crystal 1---._---:2::..:4 X1
Oscillstor
23 X2
....
~~---.1r;:;;;;F;;;;;,'
Test Register
and Device
LOOP ....:.1.:.,.1_-I
")_T--l~M:od=e:;:co:nt::r:ol~
TXEN ....:.4_--1
>------t-----'
1 CLKOUT
Driver and
Pre-Emphasis
Control
TXDATAB .,;:3_--1
Status
Linea
TXDATAA -=2'-----1
RX- 15
Receiver
Squelch
Circuit
11--I---t!L~~~
'------------'
RX+ 16
SQEEN -=22=---1
9 RXDATAB
~----~.......
Signal Quality
Error Teat
Circuit
1ExAs . "
2-162
INSIRUMENfS
POST OFFICE BOX 655303 • DAUAS, TEXAS 75265
8 RXDATAA
+-__--'-7
GND (L)
..._ _---:1"'-9 GND (P)
SN75LBC086
DIFFERENTIAL I/O DRIVER/RECEIVER PAIR
WITH SQUELCH, JABBER CONTROL, AND COLLISION DETECTION
SLLS12OA- 03525, JUNE 1991 - REVISED SEPTEMBER 1991
Terminal Functions
NAME
CLKOUT
CTL
FULLD
PIN
LEVEL
CMOS
CMOS
TTL
GND(L)
GROUND
5
7
GND(P)
GROUND
19
JABB
CMOS
13
0
LINK
CMOS
12
0
LOOP
TTL
11
I
AX+
AXAXEN
CMOS
16
15
10
I
I
0
AXDATAA
AXDATAB
CMOS
ECL
8
9
0
0
Received-data serial outputs. These provide a choice of logic levels and serial data either from the
differential receiver input (AX+ and AX-) or data from the controller (TXDATAA or TXDATAB) when in
the loop-back mode. When the receiver is idle, these output levels are normally high. These terminals
are held inactive (high) due to an internal pullup resistor.
SQEEN
TTL
22
I
Signal-qualityerror-test enable. In normal operating mode, this enables the SQEtestfunction performed
at the end of a data packet transmission. In the test mode, SQEEN is used (with XI clock) as a serial
data input port to load test patterns or selections into the test register. This terminal is held inactive (high)
due to an internal pullup resistor.
TTL
0
0
I
Differential driver outputs
TXEN
21
20
4
TXDATAA
TXDATAB
CMOS
ECL
SUPPLY
SUPPLY
CMOS
2
3
I
I
Transmit-data inputs. A choice of logic-level inputs provide Manchester-encoded serial data to the
driver. Internal pullup resistors are included.
I
0
VCC logic power supply. This provides power to the CMOS core logic.
VCC power supply. This provides power to the input and output buffers, drivers, and receivers.
Crystal input/output. XI provides an input from an external 10-MHz crystal or another external clock
source if the crystal is disconnected. X2 provides an oscillator output.
TX+
TX-
VCC(L)
VCC(P)
XI
X2
NO,
1
14
17
6
18
24
23
I/O
DESCRIPTION
0
0
I
Clock output. This 1Q-MHz buffered clock is provided for driving other Interface devices.
Control. In normal mode, CTL high indicates a collision. In test mode, status lines are muxed out.
Full-duplex mode. When active (low), the device is placed in the full-duplex operating mode for simple
point-to-point communication applications. In the full-duplex mode, the receiver and driver are both
active with collision detection disabled. After LOOP and FULLD go active Qow), In that order, a device
reset is initiated and while both are active Qow), test select data Is clocked into the test register using
a l00-ns clock at the XI Input. This terminal Is held Inactive (high) due to an Internal pullup resistor.
Logic grounds. These terminals provide a ground return for the CMOS core logic.
Power ground. This provides a ground return for the input and output buffers, driver (transmitter), and
receiver circuits.
Jabber control. When a jabber condition exists during normal mode operation, this signal goes active
(high) to report jabber-control status to the controller. In the test mode, this provides a multiplexed signal
for internal timer and counter functions.
Link status. This 3-state output indicates the status of the receiver and interface link. When driving an
LED (with anode to resistor to VCC) , a high-impedance level indicates a failed link and the LED Is off.
A momentary high level indicates the device is receiving valid data and the LED is blinking on and off.
A continuous low level indicates the device is receiving valid link pulses but no data, and the LED Is on.
Loop-back mode. When the device is in the normal operating mode (not test mode) and LOOP is active
(low), the driver (transmit) data is directed to the receive data path to put the device In the loop-back
modeand the driver Is turned off. After LOOP and FULLD go active Qow), in that order, a device reset
is initiated and while both are active (low), test select data Is clocked into the test register using a 100-ns
clock at the XI input. This terminal is held inactive (high) due to an internal pullup resistor.
Differential receiver inputs
Receiver squelch status. This provides squelch status information to the controller. When active (high),
this signal indicates that the data path is valid or open from the receive channel through the device. An
inactive Qow) indicates that the receive channel is squelched or closed. This signal is capable ofdrlvlng
an LED monitor.
Transmitter (driver) enable. When TXEN is active (high), serial data at the TXDATA inputs starts and
stops the driver. When TXEN is inactive (low), the driver begins transmitting an idle signal Independent
of the TXDATA inputs.
1ExAs
-If
INSIRUMENTS
POST OFFICE BOX 655303 • DAUAS, TEXAS 75265
2-163
SN75LBC086
DIFFERENTIAL I/O DRIVER/RECEIVER PAIR
WITH SQUELCH, JABBER CONTROL, AND COLLISION DETECTION
Sl.LS12OA-' 03525, JUNE 1991 - REVISED SEPTEMBER 1991
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, Vee (see Note 1) .............................................. -0.5 V to 7 V
Input voltage range at any input, V, ................................................. -'-0.5 V to 5.5 V
Output voltage range at any'output, Vo ............................................... -0.5 V to 7 V
Continuous total dissipation ........................................... See Dissipation Rating Table
Operating free-air temperature range, TA .............................................. O·C to 70·C
Storage temperature range ....................................................... -65·C to 150·C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds ............................... 260·C
NOTE 1: All voltages are wfth respect to device ground pins GNO(U and GNO(p) shorted together.
DISSIPATION RAllNG TABLE
PACKAGE
TA,,25°C
POWER RAllNG
DERAllNG FACTOR
ABOVE TA = 25"C
TA=70·C
POWER RAllNG
ow
1350mW
10.8mWrC
864mW
recommended operating conditions
Supply voltage, VCC
TXOATAA,X1
High-level output voltage, VIH
TXOATAB
(see Figure 1)
MIN
NOM
MAX
UNIT
4.75
5
5.25
V
3.15
TA=O·C
0.984VCC-0.922
0.984VCC-0.763
TA=25·C
0.984VCC-0.877
0.984VCC-0.727
TA=70·C
0.984VCC-0.825
0.984VCC-0.645
TXEN, LOOP,
FULLO, SaEEN
2
TXOATAA,X1
Low-level output voltage, VIH
TXOATAB
(see Figure 1)
V
0.8
TA=O·C
0.75VCC-0.590
0.750VCC-0.375
TA=25·C
0.75VCC-0.550
0.750VCC-0.350
TA=70·C
0.75VCC-0.531
0.750VCC-0.324
TXEN, LOOP,
FULLO, SaEEN
V
0.8
Olfferentlallnput voltage. VIO
0.586
2.8
V
Common-mode Input voltage, VIC
1.8
3.2
Operating free-airtemperature, TA
0
70
V
·C
1ExAs . "
INSfRUMENTS
2-164
POST OFFICE BOX 655303 • DAUAS, TEXAS 75265
SN75LBC086
DIFFERENTIAL VO DRIVER/RECEIVER PAIR
WITH SQUELCH, JABBER CONTROL, AND COLLISION DETECTION
SlLSI2OA-D3525,JUNE 1991-REVISEDSEPTEMBER 1991
electrical characteristics over recommended operating free-air temperature and supply voltage
range (unless otherwise noted)
drivers
PARAMETER
TEST CONDITIONS
CLKOUT, RXDATAA,
RXEN, JABB, CTL
VOH
High-level
output voltage
CLKOUT, RXDATAA,
RXEN, JABB, CTL
VOL
Low-level
output voltage
RXDATAB
LINK
VOD
VOD
TYP
MAX
UNIT
V
3.7
IOH=-12mA
TA=O·C
RXDATAB
MIN
0.984 VCC-0.922
0.984 VCC-0.763
See Figure 1 TA=25·C
0.984 VCC-0.8n
0.984 VCC-0.727
TA=70·C
0.984 VCC-0.825
0.984 VCC-O.645
V
0.5
IOL= 16mA
V
TA=O·C
See Figure 1 TA=25·C
0.750 VCC-0.590
0.750 VCC-0.550
0.750 VCC-0.375
0.750 VCC-0.350
TA=70·C
0.750 VCC-0.531
0.750 VCC-0.324
0.5
V
V
Differential-output voltage (peak)
IOL=12mA
See Figure 2
2.2
2.8
V
Differential-output voltage (step)
See Figure 2
1.53
1.982
V
8
C
Common-mode
driver impedance
TX+, TX-
2
5
receivers
PARAMETER
IIH
High-level Input current
TEST CONDITIONSt
TXDATAA, TXEN, LOOP,
FULLD, SQEEN
Low-level input current
TYP
MAX
100
IIA
400
VIH = MAX
TXDATAA, TXEN, LOOP,
FULLD, SQEEN
UNIT
20
VI = 5.25 V
XI
TXDATAB
IlL
MIN
-20
VI=O
XI
-100
TXDATAB
-400
VIL = MIN
t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
IIA
drivers and receivers
MIN
TYP
MAX
180
ICC
1ExAs ..,
INSIRUMENTS
POST OFFICE BOX 655303 • DAUAS, TEXAS 75265
2-165
SN75LBC086
DIFFERENTIAL 1/0 DRIVER/RECEIVER PAIR
WITH SQUELCH, JABBER CONTROL, AND COLLISION DETECTION
SLLS12OA-D3525. JUNE 1991-REVISEDSEPTEMBER 1991
switching characteristics
FROM
(INPUT)
PARAMETER
TEST
CONDITIONS
TO
(OUTPUT)
MIN
TYP
MAX
UNIT
tpdl
Propagation delay time
RX+.RX-
RXEN
See Figure 4
5 bit
times
tpd2
Propagation delay time at startup
RX+. RX-
RXDATAAor
RXDATAB high
See Figure 4
75
ns
tsk(o)
Output skew time
RXENhigh
RXDATAAor
RXDATAB I.ow
See Figure 4
,.10
ns
See Figure 4
50
ns
tpd3
Propagation delay time after startup
RX+.RX-
RXDATAAor
RXDATAB high
tsk(P)
Pulse skew time (~PLH4 - tPHL41)
RX+.RX-
RXDATAAor
RXDATAAB
See Figure 4
tDd4
Propagation delay time
RX+.RX-
RXENlow
See Figure 5
tpd5·
Propagation delay time
TXDATAor
TXDATAB
TX+. TX-
See Figure 6
tsk(P)
Pulse skew time (itpLH5 - tpHLSI)
TXDATAAor
TXDATAB
TX+. TX-
See Figure 6
tpd6
Propagation delay time In loop mode
TXDATAAor
TXDATAB
RXDATAA.
RXDATAB
See Figure 7
50
ns
tDd7
Propagation delay time In loop mode
TXEN high
RXENhigh
See Figure 7
50
ns
tDd8
Propagation delay time in loop mode
LCX)Plow
RXENlow
See Figure 7
30
ns
10010
tpdl1
Propagation delay time
TXENlow
RXENlow
See Figure 8
350
ns
Propagation delay time
TXENlow
TX+. TX- high
See Figure 8
50
ns
tpl
Precompensation pulse duration
TX+. TX-
See Figure 6
45
55
ns
tp2
Receiver link-beat minimum pulse
duration
See Figure 9
80
120
ns
lenl
Enable time
TXDATAAor
TXDATAB
TX+. TX-
See Figure 6
75
ns
Ien2
Enable time
TXEN
TX+. TX-
See Figure 6
75
ns
Idlsl
Disable time. caused by TXDATAA or
TXDATAB high or TXEN low .
TX+. TX-hlgh
TX+. TX-at
585-mV level
See Figure 8
tDd12
Propagation delay time to looped RXEN
TXEN high
RXENhigh
See Figure 6
100
ns
tpd13
Propagation delay time for looped back
data
TXDATAAor
TXDATAB
RXDATAA
RXDATAB
See Figure 6
75
ns
2
155
ns
250
ns
75
ns
2
ns
250
ns
timing requirements
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Setup time. test mode. SaEEN before Xl t. tsul
See Figure 10
30
Setup time. test mode. UJOP low before FULLD~. tsu2
See Figure 10
25
ns
Hold time. test mode. SOEEN after Xl t. Ihl
See Figure 10
25
ns
.
2-166
iExAs ~
INSlRUMENTS
POST OFFICE BOX 655303 • DAUAS. TEXAS 75265
ns
SN75LBC086
DIFFERENTIAL VO DRIVER/RECEIVER PAIR
WITH SQUELCH, JABBER CONTROL, AND COLLISION DETECTION
SLLS12OA-D3525. JUNE 1991-REVISED SEPTEMBER 1991
PARAMETER MEASUREMENT INFORMATION
Figure 1. ECl load Circuit
Figure 2. Differential Load Circuit
Figure 3. CMOS Load Circuit
RX+.RXOiff Input
~I
tpd1
50%1I
I
50%\I
RXEN
RXOATAA
I
I
I
I
I
I
~tpd2
:1
i;::f-tpd2
50%~
RXOATAB
I
I
I
I
I
I
tpd3~
\ --l+-----+-l
: 1
tpd3
I
\
\...
\...
tsk(O) ........
Figure 4. Receiver Startup Waveforms
RX+,RXOifflnput\
O%{
>300mV
1+14II--- t pd4 ---+1.1
RXEN
Figure 5. Receiver Shutdown Waveforms
1ExAs
,If
INSIRUMENTS
POST OFFICE BOX 655303 • DALlAS. TEXAS 75265
2-167
SN75LBC086
DIFFERENTIAL 1/0 DRIVER/RECEIVER PAIR
WITH SQUELCH, JABBER CONTROL, AND COLLISION DETECTION
Su.s12OA- 03525. JUNE 1991 - REVISED SEPTEMBER 1991
PARAMETER MEASUREMENT INFORMATION
i
:
tpd12-+j
I-~------------------------------------
RXEN
RXDATAA I
RXDACfAB-t---""'"\
Bit Type
TXDATAA
or
TXDATAB
(CMOS or ECl)
DlffTX+. TX-
Output
_-+---;
I
I
L
..
TXENJ~
.II
tan2
Figure 6. Driver Startup Waveforms
TXEN--------t~
_ _ _ _ _ _ _~I~
TXDA~
:
TXDATAB
I
I
RXDATAA (CMOS)
RXDATAB (ECl)
I
I.
I
\.
~
~
~tp~
I
•
~tpd6
.. . I
\~
.1
I
\\.-__....11
I
Ir-----~
f~
\'-____
tpd7
RXEN----~tL~_%_· _ _~/-~-------------I
1-
j+-tpdB-+j
lOOP~~~
_ _ _ _~_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
Figure 7. Propagation Delay Waveforms In Loop Mode
1ExAs
~
INSTRUMENTS
2-168
POST OFFICE BOX 655303 • DAu.AS. TEXAS 75265
SN75LBC086
DIFFERENTIAL VO DRIVER/RECEIVER PAIR
WITH SQUELCH, JABBER CONTROL, AND COLLISION DETECTION
SLlS12OA- 03525, JUNE 1991 - REVISED SEPTEMBER 1991
PARAMETER MEASUREMENT INFORMATION
Bit Type
111"
I
\
TXDATAA
(CMOS)
or
"0"
\ 50%~
I
50%/
\
I
I
TXOATAB (ECl) \
I
TX+. TXOlffOutput
--
l I+- tpd11
TXEN----------------------~i~5O%-------------------j4-- tpd10 ---.I
RXEN-----------------------------------~
\~50%
__
Figure 8. Driver Shutdown Waveforms
,tp2j
Olff Input RX+. RX-
________~~
~tp2-J
I
Oiff Output TX+. TX-
-~mV
o
I
_______----'~I
1Ii
i\... - ~mV
I
o
I
Figure 9. Link Beat Pulse Duration Waveform
1ExAs
~
INSIRUMENIS
POST OFFICE BOX 655303 • DAUAS, TEXAS 75265
2-169
SN75LBC086
DIFFERENTIAL 1/0 DRIVER/RECEIVER PAIR
WITH SQUELCH, JABBER CONTROL, AND COLLISION DETECTION
SLLS12OA- 03525, JUNE 1991 - REVISED SEPTEMBER 1991
PARAMETER MEASUREMENT INFORMATION
Xl
14
.1
I
I
I
I
I
SQEEN
___________~-J)I~
-
I
I
taul
~I
~
~
--+I i+- thl
I
-JJ1ri----------
LOOP~~__________________________
~
-l+-
t 8112
I
FUUD----~~~~____________________~J1r:--------I
Figure 10. Setup and Hold Time Waveforms
2-170
POST OFFICE BOX 655303 • DAUAS, TEXAS 75265
SN55107A,SN55107B, SN55108A, SN55108B
SN75107A, SN75107B, SN75108A, SN75108B
DUAL LINE RECEIVERS
SLl.S069A-
JANUARY 1977
SN55107A, SN55107B. SN55108A,
SN551OBB. •• J OR W PACKAGE
SN75107A, SN75107B. SN75108A,
SN751OBB ••• D. J. OR N PACKAGE
• High Speed
• Standard Supply Voltage
• Dual Channels
• High Common-Mode Rejection Ratio
(TOP VIEW)
• High Input Impedance
16
Vcc+
Vcc-
NC
2A
1A
• High Input Sensitivity
• Differential Common-Mode Input Voltage
Range of±3V
26
NC
• Strobe Inputs for Receiver Selection
• Gate Inputs for Logic Versatility
•
•
•
•
GND
TTL Drive Capability
High dc Noise Margin
'107A and '107B Have Totem-Pole Outputs
'108A and '108B Have Open-Collector
Outputs
SN55107A, SN55107B, SN55108A,
SN5510BB ••• FK PACKAGE
(TOP VIEW)
+ I
• B Versions Have Diode-Protected Input for
00
~~~~~
Power-Off Condition
description
NC
NC
These circuits are TTL-compatible high-speed
line receivers. Each is a monolithic dual circuit
featuring two independent channels. They are
designed for general use as well as such specific
applications as data comparators and balanced,
unbalanced, and party-line transmission systems.
These devices are unilaterally interchangeable
with and are replacements for the SN551 07.
SN551 08, SN751 07. and SN751 08. but offer
diode-clamped strobe inputs to simplify circuit
design.
1Y
NC
1G
4
5
6
7
8
1 2019
18
17
16
15
14
9 10 11 12 13
3 2
2A
NC
26
NC
NC
Cl)CO(!)>-
ZZC\IC\I
(!)
NC - No internal connection
THE SN75108B IS NOT
RECOMMENDED FOR NEW DESIGN
The essential difference between the A and B
versions can be seen in the schematics. Inputprotection diodes are in series with the collectors of the differential-input transistors of the B versions. These
diodes are useful in certain party-line systems that may have multiple VCC+ power supplies and may be operated
with some ofthe VCC + supplies turned off. In such a system, if a supply is turned off and allowed to go to ground,
the equivalent input circuit connected to that supply would be as follows:
Input
--I~~t!J""1--+---'1
Input
~II~
t!J 1
BVerslon
AVersion
This would be a problem in specific systems that might possibly have the transmission lines biased to some
potential greater than 1.4 V.
The SN55107A, SN55107B, SN55108A, and SN55108B are characterized for operation over the full military
temperature range of -55°C to 125°C. The SN75107A, SN75107B. SN75108A, and SN75108B are
characterized for operation from O°C to 70°C.
Copyright © 1993, Texas Instruments Incorporated
1ExAs . "
INSIRUMENIS
POST OFFICE BOX 655303 • DALlAS, TEXAS 75265
2-171
SN551 07A, SN55107B, SN55108A, SN55108B
SN75107A,SN75107B, SN75108A, SN75108B
DUAL LINE RECEIVERS
SLlS069A- 02304, JANUARY 1977.,- REVISED JANUARY 1993
logic symbols t
SN55107
SN75107
S
1A
1B
1G
2A
2B
2G
6
2
5
]
"
~ ~
S
4
&
1A
1Y
1B
,
1G
\
12
11
~
~N
1
SIII551 08
SN751 08
2A
9
"-
2B
8
2G
6
,..I
~N
1
2
"-
]
~ ~
11
"-
8
6
S -------,
1A
1Y
1G - - - - '
2G - - - - - ,
2A
2B
FUNCTION TABLE
VI02: 25 mV
-25 mV < VIO < 25 mV
STROBES
G
X
X
L
H
X
VIO ,,-25 mV
L
H
S
X
L
X
OUTPUT
V
H
H
H
H
L
Indeterminate
X
H
L
H
H = high level, L = low level, X = Irrelevant
1ExAs . "
INSIRUMENTS
2-172
4
12
logic diagram (positive logic)
DIFFERENTIAL INPUTS
A-B
~
5
t These symbols are In accordance with ANSI/IEEE Std 91-1984 and lEe Publication 617-12.
Pin numbers shown are for the 0, J, N, and W packages.
1B
&
POST OFFICE BOX 655303 • DAUAS, TEXAS 75265
H
9
1Y
SN55107A, SN551078, SN55108A, SN551088
SN75107A, SN751078, SN75108A, SN751088
DUAL LINE RECEIVERS
Su.s069A- 02304, JANUARY 1977 - REVISED JANUARY 1993
schematic (each receiver)
VCC+~1~4--e----e--------e---~--------e---------~---e__
400g
4kg
4,8 kg
OutputY
A 1 12
GND
Inputs
B 2,11
~____~____~__-+~5,~8 S~obeG
....._ _ _+-_--'1
3kg
1
3kg
-I
4,25 kg
I
Common
to Both
1Recelvere
VCC_~1~3~------e--------------------e--+-_I__- _
- __
--------e
1
1
1
1
1
____---+....:6~ Strobe S
~----------------------------~vr------------------------------JI
To Other Receiver
Pin numbers shown are for D, J, N, and W packages.
t R = 1 kg for '107A and '107B, 750 g for 'l08A and '108B.
NOTES: 1. Resistor values shown are nominal.
2. Components shown wHh dashed lines in the output circuitry are applicable to the '107A and '107B only. Diodes in series with the
collectors of the differential input transistors are short circuited on '107A and '10BA.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vcc+ (see Note 3) ............................................................ 7 V
Supply voltage, Vcc- ..................................................................... -7V
Differential input voltage (see Note 4) ........................................................ ±6 V
Common-mode input voltage (see Note 5) ............... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ±5 V
Strobe input voltage ....................................................................... 5.5 V
Continuous total dissipation ........................................... See Dissipation Rating Table
Operating free-air temperature range: SN55' ...................................... -55·C to 125·C
SN75' .......................................... O·C to 70·C
Storage temperature range ....................................................... -65·C to 150·C
Case temperature for 60 seconds: FK package .............................................. 260·C
Lead temperature 1.6 mm (1/16 inch) from case for 60 seconds: J package ..................... 300·C
Lead temperature 1.6 mm (1/16 inch) from case for 10 seconds: D, N, or W package ............. 260·C
NOTES: 3. All voHage values, except differential voHages, are with respect to network ground terminal.
4. Differential voHage values are at the non inverting (A) terminal with respect to the inverting (B) terminal.
5. Common-mode input voRage is the average of the voltages at the A and B inputs.
1ExA.s . "
INSIRUMENTS
POST OFFICE BOX
655303 • DAUAS, TEXAS 75265
2-173
SN55107A, SN551 078,SN551 OBA, SN5510B8
SN75107A, SN751078, SN75108A,SN7510BB
DUAL LINE RECEIVERS
Sll.S069A- 02304, JANUARY 1977 - REVISED JANUARY 1993
DISSIPATION RATING TABLE
TA",25°C
DERATING FACTOR
TA-70°C
POWER RATING
POWER RATING
ABOVE TA. 25°C
608mW
950mW
7.6mWrC
' 1375mW
880mW
11.0mWrC
1375mW
11.0mWrC
880mW
1025mW
8.2mWrC
656mW
736mW
1150mW
9.2mWrC
640mW
1000mW
8.0mWrC
PACKAGE
D
FK
J (SN5510_A.B)
J (SN7510_A.B)
N
W
TA-12S0C
POWER RATING
275mW
275mW
200mW
recommended operating conditions (see Note 6)
SN75107A. SN75107B
SN75108A, SN7S1 O8B
SN55107A, SN55107B
SNSS108A, SN5S108B
MIN
4.5
Supply voltage, VCC+
Supply voltage, VCCHigh-level input voltage between differential Inputs, VIDH (see Note 7)
-4.5
NOM
5
-5
UNIT
MAX
MIN
NOM
MAX
5.5
4.75
5
-5
5.25
V
-5.25
V
0.025
-5t
5
-0.025
V
V
V
-5.5 -4.75
0.025
-5t
-0.025
-3t
-5t
3
3
-3t
3
-5t
3
V
High-level input voltage at strobe inputs, VIH(S)
2
5.5
2
5.5
V
Low-level input voltage at strobe inputs, VILIS}
0
0.8
0
0.8
V
Low-level input voltage between differential inputs, VIOL (see Note 7)
Common-mode input voltage, VIC (see Notes 7 and 6)
Input voltage, any differential Input to GND (see Note 8)
5
-16
-16
mA
Low-level output current, IOL
Operating free-air temperature, TA
70
-55
125
0
°c
...
t The algebraic convention, in which the less POSitive (more negative) hmit IS designated as minimum, is used in this data sheet for Input voltage
levels only.
NOTES: 6. When using only one channel of the line receiver, the strobe G of the unused channel should be grounded and at least one of the
differantlal inputs of the unused receiver should be terminated at some voltage between -3 V and 3 V.
7. The recommended combinations of input voltages fall within the sheded area of the figure shown.
8. The common-mode voltage may be as low as -4 V provided that the more positive of the two inputs is not more negative than -3 V.
RECOMMENDED COMBINATIONS
OF INPUT VOLTAGES
>I
j
~
!i
"c.s
i
.5
-1
-4
-3 -2 -1
0
Input B to GND Voltege - V
1ExAs
2-174
2
,If
INSIRUMENTS
POST OFFICE BOX 86Ii303 • DAllAS, -rexAS 75265
3
SN55107A, SN55107B, SN55108A, SN55108B
SN751 07A, SN75107B, SN75108A, SN75108B
DUAL LINE RECEIVERS
SLLS069A- 02304, JANUARY 1977 - REVISED JANUARY 1993
electrical characteristics over recommended free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONSt
VOH
High-level output voltage
VCC±=MIN,
VIL(S) = 0.8 V,
VIOH=25mV,
10H = -400 !lA,
VIC = -3 Vto 3 V
VOL
Low-level output voltage
VCC±=MIN,
VIH(S) =2V,
VIOL = -25 mV, 10L= 16mA,
VIC =-3 Vto3V
IIH
High-level
Input current
B
IlL
Low-level
input current
B
IIH
High-level input current
into lG or 2G
IlL
Low-level input current
into lG or 2G
IIH
High-level input
current into S
IlL
A
A
VCC±=MAX
VCC±=MAX
'108A, '1088
'107A, '1078
MIN
TYp:j:
MAX
MIN.
TYp:j:
MAX
UNIT
V
2.4
0.4
0.4
VIO=5V
30
75
30
75
VIO=-5V
30
75
30
75
V
!lA
VIO =-5V
-10
-10
VIO =5V
-10
-10
40
40
!lA
1
1
mA
mA
!lA
VCC±=MAX,
VIH(G) = 2.4 V
VCC± = MAX,
VIH(G) = MAX VCC+
Vcc± = MAX,
VIL(G) = 0.4 V
-1.6
-1.6
VCC±=MAX,
VIHIS) = 2.4 V
80
80
!lA
VCC±= MAX,
VIH(S) = MAX VCC+
2
2
mA
Low-level input
current into S
VCC±=MAX,
VIL(S)= 0.4 V
-3.2
-3.2
mA
10H
High-level
output current
VCC±=MIN,
VOH = MAXVCC+
250
!lA
lOS
Short -circuit
output current§
VCC±=MAX
ICCH+
Supply current from
VCC+, outputs high
VCC± = MAX,
TA=25°C
18
30
18
30
rnA
ICCH-
Supply current from
VCC~ outputs high
VCC±=MAX,
TA=25°C
-8.4
-15
-8.4
-15
rnA
-70
-18
rnA
..
t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating condttlons .
:I: All typical values are at VCC + = 5 V, VCC- = -5 V, TA = 25°C.
§ Not more than one output should be shorted at a time.
switching characteristics, VCC±
=±5 V, TA =25°C, RL =390 Q (see Figure 1)
TEST
CONDITIONS
PARAMETER
tPLH(O)
Propagation delay time, low-to-high-Ievel output,
from differential inputs A and B
CL=50 pF
Propagation delay time, high-to-Iow-Ievel output,
from differential inputs A and 8
CL=50pF
tPHL(O)
tPLH(S)
Propagation delay time, low-to-high-Ievel output,
from strobe input G or S
CL=50pF
tpHL(S)
Propagation delay time, high-to-Iow-Ievel output,
from strobe input G or S
CL=50pF
'108A,1088
'107A,'1078
MIN
TYP
MAX
17
25
CL=15pF
17
8
MAX
19
25
19
25
13
20
13
20
15
CL=15pF
CL=15pF
TYP
25
CL=15pF
10
MIN
15
UNIT
ns
ns
ns
ns
1ExAs ."
INSIRUMENTS
POST OFFICE BOX 655303 • DALlAS. TEXAS 75265
2-175
SN551 07A, SN55107B, SN5510SA, SN5510SB
SN75107A, SN75107B, SN7510SA, SN7510SB
DUAL UNE RECEIVERS
SUS069A- 02304, JANUARY 1977 - REVISED JANUARY 1993
PARAMETER MEASUREMENT INFORMATION
Differential
Output
'107A, '107B
VCC-
____ 1_________ .,
Input
I
~----~~
1B
Pulse
Generator
(_NoteA)
";" (see Note D)
3900
Output
'108A, '1088
CL
Strobe
15pF
(see Note C)
";"
Input
(see Note B)
Pulse
Generator
(see Note A)
TEST CIRCUIT
Input A
;f100mv
_ _-I!+-
~~100
__m_v____r~,~(------~;1
1)
\
1
tP1 ~I
i..
---.....,..I-----tl----\''r-',- -.....\L.
Strobe Input
GorS
OutputY
1
1
tPLH(D) -+I 1+
1
1.
tPHL(D)
tPLH(S)
-+I
ov
tp2---+l~i
.
!'\.5V
1
-+I ~
--OlOmv
I~
3V
1.5'7!
. 1
1+
-.:
___-It"v ~'"_1._5_V r~/'r,------It..
___
1+
tpHL(S)
"vL
V
:
VOLTAGE WAVEFORMS
=
=
=
=
NOTES: A. The pulse generators have the following characteristics: Zo 50 0, tr 10 ,. 5 ns, tf 10 ,. 5 ns, tpd1 500 ns, PRR s 1 MHz,
tpd2 = 1 IJ.S, PRR s 500 kHz.
B. Strobe input pulse is applied to Strobe 1G when Inputs 1A·1B are being tested, to Strobe S when inputs 1A·1B or 2A-2B are being
tested, and to Strobe 2G when inputs 2A-2B are being tested.
C. CL includes probe and jig capackance.
D. All diodes are 1N916.
Figure 1. Test Circuit and Voltage Waveforms
TEXAS'"
INSIRUMENTS
2-176
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
SN55107A, SN55107B, SN55108A, SN55108B
SN75107A, SN75107B, SN75108A, SN75108B
DUAL LINE RECEIVERS
Sl.LS069A- 02304, JANUARY 19n - REVISED JANUARY 1993
TYPICAL CHARACTERISTICSt
OUTPUT VOLTAGE
HIGH-LEVEL INPUT CURRENT INTO 1A OR 2A
DIFFERENTIAL INPUT VOLTAGE
FREE-AIR TEMPERATURE
va
VS
6
I
, " I~nl~vertln~
&
i
Inverting
Inplt s
4
I;Pj
\
3
i
I
-?
c(
::!.
I
80
'E
I
1cr:A, '10~B_
J'
'\
J
I
VCC±=±5V
'1~'1~B
,/
5
>I
100
I
u
§
1
.5
60
!
40
~
......
.c
g
2
...........
J:
I
VCC±=±5V
RL=400Q
TA=25·C
I
J
o
-40
-30
-10
-20
~
0
10
20
30
20
o
-75
40
-50 -25
FREE-AIR TEMPERATURE
I
~
I
20
..
40
I
--
VCC±=±5V
.
.
35
c
30
E
25
i
20
i-
ICC+
""
Q
C
I
.-!PLH(D)
0
::s
10
15
e
10
IL
5
-75
I.
1-:-
tPHL(D)
8.
ICC-
o
RL=390Q
CL=50pF
I
II)
u
~
125
vs
25
~
100
FREE-AIR TEMPERATURE
VCC±=±5V
I
75
PROPAGATION DELAY TIME
(DIFFERENTIAL INPUTS)
30
~
Q.
50
SUPPPLY CURRENT, OUTPUTS HIGH
vs
15
25
-r---
Figure 3
Figure 2
~
u
0
I--
TA - Free-Air Temperature - DC
VID - Differential Input Voltage - mV
'E
r--.... ...........
-
~
-'
V
5
o
-50
-25
0
25
50
75 100
TA - Free-Alr Temperature - DC
125
~
~
Figure 4
~
0
25
50
~
100
TA - Free-Air Temperature - DC
125
Figure 5
t Values below ODC and above 70·C apply to SNSS' only.
POST OFFICE BOX 655303 • DALlAS, TEXAS 75265
2-177
SN551 07A, SN551 07B,SN551 OSA, SN55108B
SN75107A, SN75107B, SN75108A, SN75108B
DUAL LINE RECEIVERS
\
SLLS069A- 02304, JANUARY 1977 - REVISED JANUARY 1993
TYPICAL CHARACTERISTICSt
PROPAGATION TIME, LOW·TO·HIGH LEVEL
(DIFFERENTIAL INPUTS)
PROPAGATION TIME, LOW·TO·HIGH LEVEL
(DIFFERENTIAL INPUTS)
120
va
va
FREE·AIR TEMPERATURE
FREE·AIR TEMPERATURE
.
.'
40
VCC",=",5V
CL=15pF
!
••
!
100
~
JL=JoD
ic
80
i
re
80
RL=l950D
40
D.
•
~
J -'-
..:5
20 I - RL=390D
D.
o
~
~
~
.1
I
VCC",=",5V
35 I- CL=15pF
0
------
h---
--
~
~
~
."
•
II
E
30
~
'ii
c
c
~
1=
./
...~
~~
i
It
~
e
15
./
•
10
..:5
5
~
D.
~
TA - Free·Air Temperature -
i\
20
DI
/
D.
~
,
RL=390D.~
100
RL=l950 D
oJ
RL = 3900 D
o
1~
-75
-~
-~
°c
'108A,'l08B
PROPAGATION DELAY TIME (STROBE INPUTS)
.'
va
vs
FREE·AIR TEMPERATURE
FREE·AIR TEMPERATURE
!
CL=~pF
•E•
30
1=
ic
25
i
20
15
~
6
20
II
15
•
10
----
t!L(S)
D.
5
o
-75
t;LH(S)
~
iiDI
....-
Q.
•
10
'C
~
-
-- ..--
tPLH(S)
0
It
-25
0
~
~
75
100
1~
i-""'"
-'"
~
~
~
0
~
~
~
TA - Free-AIr Temperature -
TA - Free-Air Temperature - °C
Figure 9
Figure 8
t values below O°C and above 70°C apply to SN55' only.
1ExAs
/
V
./
tPHL(S)
5
o
-~
,
VCc",=",sv
35 I- RL = 390 n
CL=lSpF
30
~
'ii
c
re
,
40
,
VCC",=",5V
35 I- RL=390 D
~
INSIR.UMENTS
2-178
1~
Figure 7
1=
J
100
'108A, '1088
c
c
75
PROPAGATION DELAY TIME (STROBE INPUTS)
40
•E•
50
TA - Free·Alr Temperature - °C
Figure 6
II
~
0
...J
II'
POST OFFICE BOX 655303 • DALlAS. TEXAS 75265
100
°c
1~
SN55107A, SN55107B, SN55108A, SN55108B
SN75107A, SN75107B, SN75108A, SN75108B
DUAL LINE RECEIVERS
SLLS069A- 02304, JANUARY 1977 - REVISED JANUARY 1993
APPLICATION INFORMATION
basic balanced-line transmission system
The '107A, '1078, '108A, and '1088 dual line circuits are designed specifically for use in high-speed data
transmission systems that utilize balanced, terminated transmission lines such as twisted-pair lines. The system
operates in the balanced mode, so noise induced on one line is also induced on the other. The noise appears
common mode atthe receiver inputterminals where it is rejected. The ground connection between the line driver
and receiver is not part of the signal circuit so that system performance is not affected by circulating ground
currents.
The unique driver-output circuit allows terminated transmission lines to be driven at normal line impedances.
High-speed system operation is ensured since line reflections are virtually eliminated when terminated lines are
used. Crosstalk is minimized by low signal amplitudes and low line impedances.
The typical data delay in a system is approximately 30 + 1.3 L ns, where L is the distance in feet separating the
driver and receiver. This delay includes one gate delay in bOth the driver and receiver.
Data is impressed on the balanced-line system by unbalancing the line voltages with the driver output current.
The driven line is selected by appropriate driver-input logic levels. The voltage difference is approximately:
VDIFF -1/2I O(on) • Rr
High series line resistance will cause degradation of the signal. The receivers, however, will detect signals as
low as 25 mV (or less). For normal line resistances, data may be recovered from lines of several thousand feet
in length.
Line-termination resistors (Rr) are required only at the extreme ends of the line. For short lines, termination
resistors at the receiver only may prove adequate. The signal amplitude will then be approximately:
VDIFF - 10(on) • Rr
A
Data Input 8
Transmission Line Having
Characteristic Impedance Zo
1:)---- y
RpZ0i2
Inhibit
C
D
Driver
__-----L-----.·I
SN55109A, SN55110A,
SN75109A, SN75110A,
SN75112
Strobes
Receiver
'107A, '1078, '108A,
'1088
Figure 10. Typical Differential Data Une
data-bus or party-line system
The strobe feature of the receivers and the inhibit feature of the drivers allow these dual line circuits to be used
in data-bus or party-line systems. In these applications, several drivers and receivers may share a common
transmission line. An enabled driver transmits data to all enabled receivers on the line while other drivers and
receivers are disabled. Data is thus time multiplexed on the transmission line. The device specifications allow
widely varying thermal and electrical environments at the various driver and receiver locations. The data-bus
system offers maximum performance at minimum cost.
1ExAs ."
INSIRUMENTS
POST OFFICE BOX 655303 • DALl.AS. TEXAS 75265
2-179
SN55107A, SN55107B, SN5510SA, SN5510SB
SN75107A, SN75107B, SN7510SA, SN7510SB
DUAL LINE RECEIVERS
SLLS069A- 02304. JANUARY 1977 - REVISED JANUARY 1993
APPLICATION INFORMATION
Drivers
SN55109A, SN55110A,
SN75109A, SN75110A,
SN75112
Receiver 1
Receiver 2
Receiver 4
y
y
y
Strobes
Strobes
Strobes
RT
Location 2
':'
Driver 3
Driver 1
Driver 4
Data
A
A
Input
8
8
Receivers
'107A, '1078,
'108A, '1088
C
D
D
Figure 11. Typical Differential Party Line
unbalanced or single-line systems
These dual-line circuits may also be used in unbalanced or single-line systems. Although these systems do not
offer the same performance as balanced systems for long lines, they are adequate for very short lines where
environmental noise is not severe.
The receiver threshold level is established by applying a dc reference voltage to one receiver input terminal.
The signal from the transmission line is applied to the remaining input. The reference voltage should be
optimized so that signal swing is symmetrical about it for maximum noise margin. The reference voltage should
be in the range of -3 V to 3 V. It can be provided by a voltage supply or by a voltage divider from an available
supply voltage.
A single-ended output from a driver may be used in single-line systems. Coaxial or shielded line is preferred
for minimum noise and crosstalk problems. For large signal swings, the high output current (typically 27 mAl
of the SN75112 is recommended. Drivers may be paralleled for higher current. When using only one channel
of the line drivers, the other channel should be inhibited and/or have its outputs grounded.
SN55109A, SN55110A,
SN75109A, SN75110A,
SN75112
Input
A
B
Inhibit
Output
'107A, '107B,
'108A, '1088
Input
Vref
C
D - - - - - Output
Strobes
D
Figure 12. Single-Ended Operation
1ExAs ."
2-180
INSIRUMENTS
POST OFFICE BOX 655303 • DAUAS. TEXAS 75265
SN55107A, SN55107B, SN55108A, SN55108B
SN75107A,SN75107B,SN75108A,SN75108B
DUAL LINE RECEIVERS
SUS069A- D2304, JANUARY 1977 - REVISED JANUARY 1993
APPLICATION INFORMATION
'108A, '108B dot-AND output connections
'108A, '1088
The '108A, '108B line receivers feature an
open-collector-output circuit that can be
connected in the dot-AND logic configuration with
other similar open-collector outputs, This allows a
level of logic to be implemented without additional
logic delay.
Output
Dot-AND
SN5401/SN7401or
Connection
Equivalent
increasing common-mode input voltage range
of receiver
The common-mode voltage range or CMVR is
Figure 13. Dot-AND Connection
defined as -the range of voltage applied
simultaneously to both input terminals that if exceeded does not allow normal operation of the receiver.
The recommended operating CMVR is ±3 V, making it useful in all but the noisiest environments. In extremely
noisy environments, common-mode voltage can easily reach ± 10 V tO:t 15 V if some precautions are not taken
to reduce ground and power supply noise, as well as crosstalk problems. When the receiver must operate in
such conditions, input attenuators should be used to decrease the system common-mode noise to a tolerable
level at the receiver inputs. Differential noise is also reduced by the same ratio. These attenuators have been
intentionally omitted from the receiver inputterminals sothe designermayselect resistors that will be compatible
with his particular application or environment. Furthermore, the use of attenuators adversely affects the input
sensitivity, the propagation delay time, the power dissipation, and in some cases (depending on the selected
resistor values) the input impedance, therefore reducing the versatility of the receiver.
The ability of the receiver to operate with
approximately ± 15 V common-mode voltage at
the inputs has been checked using the circuit
shown in Figure 14. The resistors R1 and R2
provide a voltage divider network. Dividers with
three different values presenting a 5-to-1
attenuation were used so as to operate the
differential inputs at approximately ± 3 V commonmode voltage. Careful matching of the two
attenuators is needed so as to balance the
overdrive at the input stage. The resistors used
are shown in Table 1.
Table 2. Typical Propagation Delays for
Receiver WHh Attenuator Test Circuit
Shown In Figure 14
DEVICE
PARAMETERS
INPUT
ATTENUATOR
TYPICAL
1
2
3
1
2
3
1
2
3
1
2
3
20
32
tpLH
'1 07A,'l07B
tpHL
tpLH
Table 1
'1 08A,'lOSB
Attenuator 1:
Rl = 2 kg,
R2 = 0.5 kg
Attenuator 2:
Rl
=6 kg,
R2 =1.5 kg
Attenuator 3:
Rl
=12 kg,
R2 =3 kg
tpHL
(n8)
42
22
31
33
36
47
57
29
38
41
Table 2 shows some of the typical switching results obtained under such conditions.
1ExAs .."
INSIRUMENTS
POST OFFICE BOX 655303 • DAllAS, TEXAS 75265
2-181
SN55107A, SN55107B, SN55108A, SN55108B
SN75107A, SN75107B, SN75108A, SN75108B
DUAL LINE RECEIVERS
SLLS069A- D2304. JANUARY 1fT17 - REVISED JANUARY 1993
APPLICATION INFORMATION
5V
/r_
16V }
14 V
14V _ _ _. . . . J / .
Receiver
r-------....;,
One Attenuator
on Each Input
R1
I
R2
-16V---....J·
5V
15 V or -15 V -'I/'>I\r---tt--'
R1
R2
Figure 14. Common·Mode Circuit for Testing Input Attenuators With Results Shown In Table 2
Two methods of terminating a transmission line to reduce reflections are:
R1
~~l:~~~
R1
R1
R1 + R2'> Zo
R3=Zo12
R3=R1 +R2=Zo12
Figure 15. Termination Techniques
The first method uses the resistors as the attenuation network and line termination. The second method uses two
additional resistors for the line terminations.
1ExAs ."
2-182
INSIRUMENTS
POST OFFICE BOX _
• DAUAS, TEXAS 75265
SN551 07A, SN55107B, SN55108A, SN55108B
SN75107A, SN75107B, SN75108A, SN75108B
DUAL LINE RECEIVERS
SLLS069A- 02304, JANUARY 1977 - REVISED JANUARY 1993
APPLICATION INFORMATION
For party-line operation, method 2 should be used as follows:
It
Attenuation Network
Figure 16. Party-Line Termination Technique
To minimize the loading, the values of R1 and R2 should be fairly large. Examples of possible values are shown
in Table 1,
furnace control using the SN7510BA
The furnace control circuit in Figure 17 is an example ofthe possible use ofthe SN551 07A Series in areas other
than what would normally be considered electronic systems. Basically, the operation ofthis control is as follows.
When the room temperature is below the desired level, the resistance of the room temperature sensor is high
and channel 1 non inverting input is below (less positive than) the reference level set on the input differential
amplifier. This situation causes a low output, operating the heat on relay and turning on the heat. The channel 2
non inverting input is below the reference level when the bonnet temperature of the furnace reaches the desired
level. This causes a low output thus operating the blower relay. Normally the furnace is shut down when the room
temperature reaches the desired level and the channel 1 output goes high, turning the heat off. The blower
remains on as long as the bonnet temperature is high, even after the heat on relay is off, There is also a safety
switch in the bonnet that shuts the furnace down if the temperature there exceeds desired limitations, The types
of temperature-sensing devices and bias-resistor values used are determined by the particular operating
conditions encountered.
5V
Bonnet
Temp
Sensor
Bonnet Upper
Limit Switch
Room
Temp
Sensor
C>-----::L
- - - - , -=-
I
1Y1
I
I
I
.... _-----".-----_... 2vl
Blower on Control
L~ ____ ~!'!'!!!. ____
I
To Heaton
Relay Return
To Blower
Relay Return
J
Figure 17. Furnace Control Using SN75108A
ThxAs
..If
INSIRUMENlS
POST OFFICE BOX 655303 • DAUAS, TEXAS 75265
2-183
SN551 07A,SN55107B,SN551 OSA; SN5510SB
SN75107A, SN75107B, SN751OSA,SN751OSB
DUAL UNE RECEIVERS
"
SLLS069A- 02304, JANUARY 1977 - REVISED JANUARY 1993
APPLICATION INFORMATION
repeaters for long lines
In some cases, the driven line may be so long that the noise level on the line reaches the common-mode limits
or the attenuation becomes too large and results in poor reception. In such a case, a simple application of a
receiver and a driver as repeaters [shown in Figure 18(a)] restores the signal level and allows an adequate signal
level atthe receiving end. If multichannel operation is desired, then proper gating for each channel must be sent
through the repeater station using another repeater set as in Figure 18(b).
I~
Dataln--1
Driver
Repeaters
________
________
t:p
~A~
Receiver
11---.. . .1
Driver
~,
t:p
p
Receiver
1--
Data Out
p
(a) SINGLE-CHANNEL LINE
Data In
Receiver
Driver
Receiver
Driver
p
Clock In
p
(b) MULTICHANNEL UNE WIDTH WITH STROBE
FIgure 18. Receiver-Driver Repeaters
receiver as dual differential comparator
There are many applications for differential comparators, such as voltage comparison, threshold detection,
controlled Schmitt triggering, and pulse-width control.
As a differential comparator, a '107A or '108A may,be connected so as to compare the noninverting input
terminal with the inverting input as shown in Figure 19. Thus the output will be high or low resulting from the A
input being greater or less than the reference. The strobe inputs allow additional control over the circuit so that
either output or both may be inhibited.
Strobe 1
Referenca1
~I---
Output 1
Strobe 1,2
Referenca2
P-If--- Output 2
"x)--I-IL-J
Strobe 2
Figure 19. SN55107A Series Receiver as a Dual Differential Comparator
1ExAs ."
INSIRUMENTS
2-184
POST OFFICE BOX 655303 • DAUAS, TEXAS 75265
SN55107A,SN55107B, SN55108A, SN55108B
SN75107A, SN75107B, SN75108A, SN75108B
DUAL LINE RECEIVERS
SLLS069A- 02304, JANUARY 1!T77 - REVISED JANUARY 1993
APPLICATION INFORMATION
window detector
The window detector circuit in Figure 20 has a large number of applications in test equipment and in determining
upper limits, lower limits, or both at the same time - such as detecting whether a voltage or signal has exceeded
its limits or window, Illumination of the upper-limit (lower-limit) indicator shows that the input voltage is above
(below) the selected upper (lower) limit, A mode selector is provided for selecting the desired test. For window
detecting, the upper and lower limits test position is used,
5V
1 kg
1 kg
SOOg
Set
Upper
Limit
Input From
Test Point
Upper-Umlt
Indicator
5 kg
SOOg
- - - - +....- - - - i
Set
Lower
Umlt
Lower-Limit
Indicator
I
~ 1~4-0.::.32H
1
_ _ _ _ _ _ _4-,\'7Mkg
__
4,7 kg
4,7 kg
Mode
Selector
MODE SELECTOR LEGEND
POSITION
1
2
3
4
CONDITION
Off
Test for Upper Umit
Test for Lower Umit
Test for Upper and Lower Umits
Figure 20. Window Detector Using SN7510SA
1ExAs
..If
INSIRUMENTS
POST OFFICE BOX 655303 • DAUAS, TEXAS 75265
2-185
SN55107A,SN55107B,SN55108A,SN55108B
SN75107A, SN75107B, SN75108A, SN75108B
DUAL UNE RECEIVERS
SlLS069A- 02304. JANUARY 1977 - REVISED JANUARY 1993
APPLICATION INFORMATION
temperature controller with zero-voltage switching
The circuit in Figure 21 switches an electric-resistive heater on or off by providing negative-going pulses to the
gate of a triac during the time interval when the line voltage is passing through zero. The pulse generator is the
2N5447 and four diodes. This portion of the circuit provides negative-going pulses during the short time
(approximately 100 fAS) when the line voltage Is near zero. These pulses are fed to the inverting input of one
channel ofthe '1 08A. Ifthe room temperature is below the desired level, the resistance ofthe thermistor is high
and the noninverting input of channel 2 is above the reference level determined by the thermostat setting. This
provides a high-level output from channel 2. This output is ANDed with the positive-going pulses from the output
of channel 1, which are reinverted in the 2N5449.
SoN
Zener
120Vto
220 v, 60 Hz
Figure 21. zero-Voltage Switching Temperature Controller
1ExAs ...,
2-186
INSIRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
SN55109A, SN55110A
SN75109A, SN75110A, SN75112
DUAL LINE DRIVERS
DECEMBER 1975 - REVISED FEBRUARY 1993
SLl.S106A-
• Improved Stability Over Supply Voltage and
Temperature Ranges
SN55109A, SN55110A ••• J OR W PACKAGE
SN75109A, SN75110A, SN75112 ••• 0 OR N PACKAGE
(TOP VIEW)
• Constant-Current Outputs
•
•
•
•
High Speed
Standard Supply Voltages
High Output Impedance
High Common-Mode Output Voltage Range
-3Vto 10V
•
•
•
•
TTL-Input Compatibility
Inhibitor Available for Driver Selection
Glitch-Free During Power Up/Power Down
SN75112 Complies With Requirements of
CCITT Recommendation V.35
Vcc+
1Y
1Z
SN55109A, SN55110A ••• FK PACKAGE
(TOP VIEW)
description
The
SN55109A,
SN55110A,
SN75109A,
SN75110A, and SN75112 dual line drivers have
improved output current regulation with supply
voltage and temperature variations. In addition,
the higher current of the SN75112 (27 rnA) allows
data to be transmitted over longer lines. These
drivers offer optimum performance when used
with the SN55107A, SN55108A, SN75107A, and
SN75108A line receivers.
1C
NC
2C
NC
2A
4
3
1 2019
18
5
17
1Z
NC
6
7
16
VCC-
15
8
2
14
9 10 11 12 13
NC
0
re~~~~
(!)
NC - No internal connection
These drivers feature independent channels with
common voltage supply and ground terminals.
THE SN75109A IS NOT
The significant difference between the three
RECOMMENDED FOR NEW DESIGN
drivers is in the output current specification. The
driver circuits feature a constant output current that is switched to either of two output terminals by the
appropriate logic levels at the input terminals. The output current can be switched off (inhibited) by low logic
levels on the enable inputs. The output current is nominally 6 rnA for the '1 09A, 12 rnA for the '11 OA, and 27 rnA
for the SN75112.
The enable/inhibit feature is provided so the circuits can be used in party-line or data-bus applications. A strobe
or inhibitor (enable D), common to both drivers, is included for increased driver-logic versatility. The output
current in the inhibited mode, IO(o!f)' is specified so that minimum line loading is induced when the driver is used
in a party-line system with other drivers. The output impedance of the driver in the inhibited mode is very high.
The output impedance of a transistor is biased to cutoff.
AVAILABLE OPTIONS
PACKAGE
TA
0°Ct070°C
-55°C to 125°C
SMALL OUTUNE
(0)
CHIP CARRIER
(FK)
SN75109AD
SN75110AD
SN75112D
SN55109AFK
SN55110AFK
CERAMIC DIP
(J)
PLASTIC DIP
(N)
SN75109AJ
SN75110AJ
SN75112J
SN75109AN
SN75110AN
SN75112N
SN55109AJ
SN55110AJ
SN55109AJ
SN55110AJ
CERAMIC
FLATPACK
(W)
SN55109AW
SN55110AW
The D package IS available taped and reeled. Add the suffix R to the device type, (e.g., SN75109ADR).
TEXAS
..If
Copyright © 1993, Texas Instruments Incorporated
INSIRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2-187
SN55109A, SN55110A
SN75109A, SN75110A, SN75112
DUAL LINE DRIVERS
SLl.S106A- 02106, DECEMBER 1975 - REVISED FEBRUARY 1993
description (continued)
The driver outputs have a common-mode voltage range of -3 V to 10 V, allowing common-mode voltage on
the line without affecting driver performance.
All inputs are diode clamped and are designed to satisfy TTL-system requirements. The inputs are tested at
2 V for high-logic-level input conditions and 0.8 V for low-logic-level input conditions. These tests ensure
400-mV noise margin when interfaced with TTL Series 54f74.
The SN551 09A and SN5511 OA are characterized for operation over the full military temperature range of- 55°C
to 125°C. The SN751 09A, SN7511 OA, and SN75112 are characterized for operation from QOC to 70°C.
FUNCTION TABLE
(each driver)
LOGIC
INPUTS
A
X
X
ENABLE
INPUTS
B
C
0
X
L
OUTPUTSt
y
z
Off
Off
X
Off
Off
L
H
H
On
Off
X
On
L
H
H
Off
H
H
H
H
Off
On
H = high level, L = low level, X = irrelevant
t When using only one channel ofthe line drivers, the other
channel should be inhibited and/or have fts outputs
grounded.
X
X
X
L
1ExAs " ,
2-188
INSIRUMENTS
POST OFFICE BOX 655303 • DAUAS, TEXAS 75265
SN55109A, SN55110A
SN75109A, SN7511 OA, SN75112
DUAL LINE DRIVERS
SLL.S1 06A- D21 06, DECEMBER 1975 - REVISED FEBRUARY 1993
schematic (each driver)
VCC+~14~~----__- - - - - .
+
y
z
A 1,5
GND --!.--------------,
Ir---------------,
Common to Both Drivers
''---_ _ _ _ _ _ _"'''\ _ _ _ _ _ _ _ _- ' ,
-
L _______________
J
yTo Other Driver
Pin numbers shown are for 0, J, N, and W packages.
1ExAs . "
INSTRUMENTS
POST OFFICE BOX 655303 • DAUAS, TEXAS 75265
2-189
SN55109A, SNSSf10A
SN75109A, SN75110A, SN75112'
DUAL LINE DRIVERS
SLl.S1 06A- 02106, DECEMBER 1975 - REVISED FEBRUARY 1993
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
SN55109A
SN55110A
SN75109A
SN75110A
SN75112
UNIT
7
7
7
V
Supply voltage, VCC-
-7
-7
-7
V
Input voltage, VI
5.5
5.5
5.5
V
Supply voltage, VCC+ (see Note 1)
Output voltage range
-5to 12
Continuous total power dissipation (see Note 2)
-5 to 12
-5t012
V
See Dissipation Rating Table
Operating free-air temperature range
-55 to 125
Ot070
Ot070
·C
Storage temperature range
-65 to 150
-65 to 150
-65 to 150
·C
Case temperature for 60 seconds: FK package
·C
260
Lead temperature 1,6 mm (1/16 Inch) from case for 60 seconds
IJ or W package
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
ID
·C
300
or N package
260
·C
260
NOTES: 1. Voltage values are with respect to network ground terminal.
2. In the FK, J, orW package, SN55109A and SN55110Achips are either silver glass or alloy mounted, and SN75109A, SN75110A,
and SN75112 chips are glass mounted.
DISSIPATION RATING TABLE
PACKAGE
TAs25·C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
TA=70·C
POWER RATING
TA=125·C
POWER RATING
D
950mW
7.6mWrC
608mW
FK
1375mW
11.0mWrC
880mW
275mW
J
1375 mW
11.0mWrC
880mW
275mW
N
1150mW
9.2mWrC
736mW
W
1000 mW
8.0mWrC
640mW
200mW
recommended operating conditions (see Note 3)
SN75109A,
SN75110A,
SN75112
SN55109A,
SN55110A
MIN
NOM
MAX
MIN
NOM
UNIT
MAX
Supply voltage, VCC +
4.5
5
5.5
4.75
5
5.25
V
Supply voltage, VCC-
-4.5
-5
-5.5
-4.75
-5
-5.25
V
Positive common-mode output voltage
0
10
0
10
V
Negative common-mode output voltage
0
-3
0
-3
V
High-level Input voltage, VIH
2
V
2
0.8
V
0
70
-55
125
NOTE 3: When uSing only one channel of the line drivers, the other channel should be inhibited and/or have its outputs grounded.
·C
Low-level output current, VIL
0.8
Operating free-air temperature, TA
1ExAs
~
INSIRUMENTS
2-190
POST OFFICE BOX 655303 • DALlAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONOITIONSt
SN55109A,
SN75109A
MIN
VIK
Input clamp voltage
Vcc", = MIN,
IL=-12mA
Vcc", = MAX. VO=10V
On-state output current
10JQfll
Off-state output current
II
Input current at maximum
input voHage
g
IIH
High-level input current
~z
IlL
Low-level input current
fir
ICC + (on)
Supply current from VCC + wtth driver enabled
en
i
TYP*
MAX
-0.9
6
MIN
SN75112
MAX
-1.5
-0.9
-1.5
15
27
36
24
28
32
rnA
18
27
!lA
MAX
-1.5
-0.9
7
12
Vcc", = MIN,
VO=-3V
Vcc", = MIN,
VO=10V
3.5
6
6.5
A, B, or C inputs
D input
A, B, or C inputs
D input
Vcc", = MAX, VI = 5.5 V
VCC", = MAX, VI = 2.4 V
A, B, or C inputs
D input
ICC-(on)
Supply current from VCC- with driver enabled
ICC +(011)
Supply current from VCC- with driver inhibRed
ICC-(off)
Supply current from Vcc", with driver inhibited
VCC", = MAX, VI = 0.4 V
12
MIN
100
100
100
1
1
1
2
2
2
40
40
40
80
80
80
-3
-3
-3
-6
-6
-6
Vcc", = MAX,
A and B inputs at 0.4 V,
C and D inputs at 2 V
-18
Vcc", = MAX,
A, B, C, and 0 inputs at 0.4 V
18
21
30
-10
-17
-32
18
UNIT
TYP*
TYP*
VCC = MIN to MAX,
VO=-1 Vt01 V
10(on)
i~..t
SN55110A,
SN75110A
30
23
35
25
40
-34
-50
-65
-100
V
rnA
!lA
rnA
rnA
-30
t For conditions shown as MIN or MAX, use appropriate value specified under recommended operating conditions.
* All typical values are at VCC+ = 5 V, VCC- = -5 V, TA = 25°C.
rnA
~
j
I
_
~
~
c
m
en
~
0
C'l
!D
z
......
01
....
CD
~C}> en
!!lCenz
'!'»ZOl
:DI ...... 01
~I~O
CD
~i'ij~}>
U l - ....
IllC~
en
:D:;O en Z
~_ZOl
~
~
:D< ...... 01
---
Output Z
!..!__ .!!'2!!!!:E~er ___ J.
-------e
(see Note C)
50C
-=-
TEST CIRCUIT
Input A
I+-
Enable C
I
-L ~
or 0
\'--------------------------
"\,-'-.-----1\'!r-j
50%
___- J
or B ~
-+I
---li------I-i-----'lrl.lrrK--~~.~'"-5O%~~~~~_tW2_~===~=;y.:.~ ~
tpLH
OutputY
.
--I
tw1
14-
-+:
I+-
11-,50%
I,'-----I,!r-j
\ 50% ' " _ _ _ _ _
,
-.J ,
tpHL~
OutputZ
"
____ : :
-+! ~
* - , 5 0 % , \..~----
:.- tpLH --.j
tpHL
::
tpHL
,
off
on
,
~
~50%
i4- tpLH ~r-I
~
j
- 50%
"'------~'-f_------------------------ on
VOLTAGE WAVEFORMS
NOTES: A. The pulse generators have the foilowing characteristics: Zo = 50 C, tr = tf = 10 ± 5 ns, tw1 = 500 ns, PRR s 1 MHz, tw2 = 1 j.tS,
PRR '" 500 kHz.
B. CL includes probe and jig capac~ance.
C. For simplicity, only one channel and the enable connections are shown.
Figure 1. Test Circuit and Voltage Waveforms
1ExAs
,If
INSIRUMENfS
2-192
POST OFFICE BOX 655303 • DAUAS, TEXAS 75265
SN55109A, SN55110A
SN75109A, SN75110A, SN75112
DUAL LINE DRIVERS
SLL.S106A- 02106. DECEMBER 1975 - REVISED FEBRUARY 1993
TYPICAL CHARACTERISTICS
ON-5TATE OUTPUT CURRENT
va
NEGATIVE SUPPLY VOLTAGE
SN55110A, SN75110A
SN55109A, SN75109A
14
7
c(
E
6
I
C
§
5
~
4
0
I
0
I
eC
.9
(
3
o
-3
12 r-
C
~:::I
10
1;5
i
6
4
C
I
-4
I
c
I
e
.9
-5
-6
2
/
o
-7
/
-4
-5
-6
VCC- - Negative Supply Voltage - V
-3
VCC- - Negative Supply Voltage - V
r
/
I
8
!0
0
J
TA=25°C
(,)
2
1
1
VCC+=4.5V
VO=-3V
I
I
I
I
(,)
1;5
I.
I
VCC+ =4.SV
VO=-3V
TA=25°C
Figure 2
-7
Figure 3
SN75112
35
1
30
I
eII
I:::
:::I
I
VCC+=4.5V
VO=-3V
TA=25°C
~
25
II
(,)
1
1;5
0
i
20
15
I
c
0
I
eC
.9
10
5
o
-3
----
"I
/
/
-4
-5
-6
-7
VCC- - Negative Supply Voltage - V
Figure 4
ThxAs
,If
INSIRUMENfS
POST OFFICE BOX 655303 • DALlAS. TEXAS 75265
2-193
SN55109A,SN55110A
SN75109A, SN75110A, SN75112
DUAL LINE DRIVERS
SLLS106A- 02106. DECEMBER 1975 - REVISED FEBRUARY 1993
APPLICATION INFORMATION
special pulse-control circuit
Figure 5 shows a circuit that may be used as a pulse generator output or in many other testing applications.
INPUT
A
OUTPUTS
Y
Z
Off On
On Off
High
Low
5V
r------------I
I
vcc+ I
A
6
Y
Input ----l-~
r--!--~:_t==::::!....._I__+_--l
2.5 V -e---t--B=-t_..I
o
~~~~~
1~~~~A
I
I
I
I
I
I
I
\
\
\
\
2 \
3ir-~r_----r--_+~-~
4
O--+------1---t--'
vccj
L.!;__ ~~~~~ ___ J
I
-
To Other logic and
Strobe Inputs
Input Pulse
"
-.J
Switch
Position
L
' - - - - - Output
.
-5 V
OV
o-'on IL lS 11lS SL
2
3
4
Figure 5. Pulse-Control Circuit
2-194
POST OFFICE BOX 655303 • DAUAS. TEXAS 75265
5
6
0.
SN55109A, SN55110A
SN75109A, SN75110A, SN75112
DUAL LINE DRIVERS
SLLS106A- 02106, DECEMBER 1975 - REVISED FEBRUARY 1993
APPLICATION INFORMATION
using the SN75112 as a CCITT recommendation V.35 line driver
The SN75112 dual line driver, the SN75107A dual line receiver, and some external resistors can be used to
implement the data interchange circuit of CCITT recommendation V.35 (1976) modem specification. The circuit
of one channel is shown in Figure 1 and meets the requirement of the interface as specified by Appendix 11 of
CCITT V.35 and summarized in Table 1.
Table 1. CCITTV.35 Electrical Requirements
UNIT
MIN
MAX
50
150
0
135
440
165
660
MV
GENERATOR
Source impedance, Zsource
Resistance to ground, R
Differential output voltage, VOD
10% to 90% rise time, tr
40
0.01 x ui t
ns
0.6
V
90
110
0
135
165
0
or
Common-mode output voltage, VCC
0
-0.6
LOAD (RECEIVER)
Input impedance, ZI
Resistance to ground, R
..
..
t UI = Unit Interval or minimum signal element pulse width
SV
SV
SfR3
3900
Strobe
,..------,
1/2 SN75112
1
I
113
12
Data In
18
3
IL _ _ _ _ _ _
I
I
I
I
I
~
6
R1
1.3kO
1Y
-=-
1Z
14
RS
7S0
R7
+
R4
3900
SV
---,I
sao
21
1BI
1Y
S Data Out
'------+-1G
I
I
I
IL _ _ _ _ _ _ _ I
Enable
~
-=-
R2
1.3kO
1/2 SN75107A
All resistors are 5%, 1/4 W.
Figure 6. CCITT Recommendation V.35 Interface Using the SN75112 and SN75107A
1ExAs'"
INSIRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2-195
2-196
SN55113, SN75113
DUAL DIFFERENTIAL LINE DRIVERS
C!C:Dn:::".,C:D
1973 - REVISED FEBRUARY 1993
SN55113 ••• J OR W PACKAGE
SN75113 ••• 0 OR N PACKAGE
(TOP VIEW)
• Choice of Open-Collector, Open-Emitter, or
3-State Outputs
• High-Impedance Output State for
Party-Line Applications
• Single-Ended or Differential AND/NAND
Outputs
• Single 5-V Supply
• Dual Channel Operation
• Compatible With TTL
• Short-Circuit Protection
• High-Current Outputs
• Common and Individual Output Controls
• Clamp Diodes at Inputs and Outputs
• Easily Adaptable to SN55114 and SN75114
Applications
• Designed for Use With SN55115 and
SN75115
16 Vcc
15 2ZP
14 2ZS
13 2YS
12 2YP
11 2A
10 2C
9
CC
SN55113 ••• FK PACKAGE
(TOP VIEW)
1YS
description
1YP
5
6
7
NC
1A
17
2YS
16
NC
The SN55113 and SN75113 dual differential line
15 2YP
drivers with 3-state outputs are designed to
8
14 2A
1B
9 10 11 12 13
provide all the features of the SN55114 and
SN75114 line drivers with the added feature of
00000
driver output controls. Individual controls are
~zzOC\l
(!)
provided for each output pair, as well as a common
control for both output pairs. If any output is low,
NC - No internal connection
the associated output is in a high-impedance state
and the output can neither drive nor load the bus.
This permits many devices to be connected together on the same transmission line for party-line applications.
The output stages are similar to TIL totem-pole outputs, but with the sink outputs, YS and ZS, and the
corresponding active pullup terminals, YP and ZP, available on adjacent package pins.
The SN55113 is characterized for operation over the full military temperature range of -55°C to 125°C. The
SN75113 is characterized for operation over the temperature range of O°C to 70°C.
FUNCTION TABLE
OUTPUTS
INPUTS
OUTPUT
CONTROL
C
CC
A
Bt
Y
Z
L
X
X
L
H
H
H
X
X
X
X
X
Z
Z
L
L
H
Z
Z
H
H
L
H
H
H
=
=
DATA
L
X
H
AND
L
H
NAND
=
H high level, L low level, X IIrelevant,
Z = high impedance (off)
t B input and 4th line of function table are applicable only to
driver number 1.
Copyright © 1993, Texas Instruments Incorporated
1ExAs'"
INSIRUMENTS
POST OFFICE BOX 655303 • DAUAS, TEXAS 75265
2-197
SN55113, SN75113
DUAL DIFFERENTIAL LINE DRIVERS
SLLS070A- 01315, SEPTEMBER 1973 - REVISED FEBRUARY 1993
logic diagram (positive logic)
logic symbol t
&
7
1C
~
CC
10
2C
1C
EN1
&
1A
&1>
4
1~
3
1~
1
1~
6
1B
2
1~
I>
2A.
1YS
EN2
["
5
1YP
CC
12
2~
13
2~
11
15
2~
14
2~
2C
1ZP
1VP
1YS
1A
1ZP
1B
1ZS
2YP
1ZS
2YS
2YP
2A
2YS
2ZP
2ZP
2ZS
2ZS
t This symbol is in accordance with ANSI/IEEE Std 91-1984 and
lEe Publication 617-12.
Pin numbers shown are for the D, J, N, and W packages.
schematic
Input 1B
6
Input1A
5
r-~___. -____~______~____~__~__~_1__
6 VCC
9
-=--.. . . --=:......:.-1
lVP
AND 4
1 NAND
fi'Ilup
Pullup
100
NAND
2 Sink
Output
lZS
Common OutflUl.;.9----J"-............
Control CC 10
~=...:.7
Output Control 2C 11
Input2A " " ' - - -....
___
H
1C
W..·VCCbua
:I: These components are common to both drivers.
Resistor values shown are nominal and in ohms.
1ExAs ."
INSTRUMENfS
2-198
POST OFFICE SOX 655300 • DAUAS, TEXAS 75265
SN55113, SN75113
DUAL DIFFERENTIAL LINE DRIVERS
SLLS070A- 01315, SEPTEMBER 1973 - REVISED FEBRUARY 1993
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) ............................................................. 7 V
Input voltage ............................................................................. 5.5 V
Off-state voltage applied to open-collector outputs ............................................ 12 V
Continuous total power dissipation (see Note 2) .......................... See Dissipation Rating Table
Operating free-air temperature range: SN55113 .................................... -55·C to 125·C
SN75113 ........................................ O·C to 70·C
Storage temperature range ....................................................... -65·C to 150·C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: D or N package ................ 260·C
Case temperature for 60 seconds: FK package .............................................. 260·C
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: J or W package ................ 300·C
NOTES: 1. All voltage values are with respect to network ground terminal.
2. In the J, FK. and W packages, SN55113 chips are alloy mounted; SN75113 chips are glass mounted.
DISSIPATION RATING TABLE
PACKAGE
TA,,25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
TA=70°C
POWER RATING
TA=125°C
POWER RATING
D
950mW
7.6mWrC
608mW
NJA
FK
1375mW
11.0mWrC
880mW
275mW
275mW
J
1375mW
11.0mWrC
880mW
N
1150mW
9.2mWrC
736mW
NJA
W
1000 mW
8.0mWre
640mW
200mW
recommended operating conditions
SN55113
SN75113
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.75
5
5.25
Supply voltage, Vee
High-level Input voltage, VIH
Low-level Input-voltage, VIL
High-level output current, IOH
Low-level output current, IOL
0.8
0.8
-40
-40
40
mA
70
°e
40
Operating free-air temperature, TA
-55
1ExAs
V
V
2
2
UNIT
125
0
V
mA
~
INSIRUMENTS
POST OFFICE BOX 655303 • DAUAS, TEXAS 75265
2-199
SN55113, SN75113
DUAL DIFFERENTIAL LINE DRIVERS
Su.s07OA- 01315, SEPTEMBER 1973 - REVISED FEBRUARY 1993
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
VIK
Input clamp voltage
VOH
High-level output
voltage
Vee = MIN.
VIL=0.8V
VIH=2V.
VOL
Low-I!lVei output
voltage
Vee = MIN.
IOL=40mA
VIH=2V.
VOK
Output clamp voltage
Vee = MAX.
IO=-4OmA
Off-state open-collector
output current
Off-state
(hlgh-Impedance-state)
output current
Vee = MAX.
Output controls
at 0.8 V
-0.9
-1.5
A, B.C
High-I!lVel
input current
A, B.e
IIH
Low-I!lVel
Input current
A, B.e
IlL
lOS
ICC
II
Vee = MAX.
-0.9
-1.5
3.4
IOH=-4OmA
2
3.0
2
3.0
V
0.23
0.4
V
-1.1
-1.5
-1.1
-1.5
V
1
10
200
1
10
Vee = MAX.
VI =0.4V
Short-cIrcuit
output current§
Vee = MAX.
Vo=O
Supply current
(both drivers)
All inputs at 0 V, No load.
TA=25°e
ItA
20
TA = 70°C
,.10
,.10
-150
-20
VO=O.4V
,.80
,.20
VO=2.4V
,.80
,.20
80
20
Vo=O to Vee
1
1
2
2
ItA
mA
VI =5.5V
VI =2.4V
V
0.4
TA= 125°C
TA=MAX
UNIT
0.23
Vo=O
Vee = MAX.
ec
MAX
2.4
CC
ee
TYP*
3.4
Vo=Vee
Input current
at maximum
Input voltage
MIN
TA=25°e
VOH=5.25V
10Z
MAX
2.4
TA = 25°C
Vee = MAX
TA=25°e.
TYP*
IOH=-10mA
VIL=0.8V,
VOH=12V
IO(off)
MIN
11=-12mA
Vee = MIN.
SN75113
SN55113
TEST eONDITIONSt
TA = 25°C
-40
-90
40
40
80
80
-1.6
-1.6
-3.2
-3.2
-120
-40
-90
-120
Vee = MAX
47
65
47
65
Vce=7V
65
85
65
85
ItA
mA
mA
mA
t All parameters WIth the exception of off-state open-collector output current are measured with the active pullup connected to the sink output. For
conditions shown as MIN or MAX. use the appropriate value specified under recommended operating conditions.
:I: All typical values are at TA = 25°C and Vee = 5 V, with the exception of ICC at 7 V.
§ Only one output should be shorted at a time. and duration of the short-circuit should not exceed one second.
switching characteristics, Vee
=5 V, eL =30 pF, TA =25°e
PARAMETER
TEST CONDITIONS
tpLH
Propagation delay time. low-to-hlgh l!lVel output
tpHL
Propagation delay time. high-to-Iow-level output
tpZH
Output enable time to high level
RL = 180
tpZL
Output enable time to low level
RL = 250
tpHZ
Output disable time from high level
tpLZ
Output disable time from low level
SN55113
MIN
See Figure 1
a. See Figure 2
a. See Figure 3
RL = 180 a. See Figure 2
RL = 250 a. See Figure 3
1ExAs
..If
INSIRUMENTS
2-200
POST OFFICE BOX 655303 • OAUAS. TEXAS 75265
SN75113
TYP
MAX
13
12
MIN
UNIT
TYP
MAX
20
13
30
ns
20
12
30
ns
7
15
7
20
ns
14
30
14
40
ns
10
20
10
30
ns
17
35
17
35
ns
SN55113, SN75113
DUAL DIFFERENTIAL LINE DRIVERS
SLLS070A- 01315, SEPTEMBER 1973 - REVISED FEBRUARY 1993
PARAMETER MEASUREMENT INFORMATION
1 kg
AND
'-r---~~- Output
Input
CL.=30pF
(see Note B)
Pulse
Generator
(eeeNoteA)
50 g
1
NAND
1
'-11----..-- Output
1L _ _ _ _ _ _ _ _ _ _ _ J
CL.=30pF
T (sse
Note B)
TEST CIRCUIT
NAND
Output
VOL.TAGE WAVEFORMS
NOTES: A. The pulse generator has the fol/owing characteristics: Zo
B. CL includes probe and jig capac~ance.
=50 Q, PRR" 500 kHz, tw =100 ns.
Figure 1. Test Circuit and Voltage Waveforms tpLH and tpHL
1ExAs
~
INSIRUMENTS
POST OFFICE BOX 655303 • DALlAS, TEXAS 75265
2-201
SN55113, SN75113
DUAL DIFFERENTIAL LINE DRIVERS
SLlS07OA- 01315, SEPTEMBER 1973 - REVISED FEBRUARY 1993
PARAMETER MEASUREMENT INFORMATION
Input
-----------,
Pulse
Generator
(see Note A)
~
I
I
I
~_.--_r~~
_ _ _ _... 50g
5V
AND
~~--~--------_,Output
I
180g
CL,,30pF
(see Note B)
NAND
Output
1 kg
5V - - - - - '
I "0---41I
I
I
IL _ _ _ _ _ _ _ _ _ _ _ JI
I
I
CL=30pF
I
:::L (see Note B) I
I
I
---------------------------~
TEST CIRCUIT
I+s 5 ns ---.I
:1_~~_~~I.
s 5 ns -+I
I
Input
7sll
v1 -----
~I~5~
10%
I
I
I
-I
4
I 10%
I -----.-I
__
I
tPZH
y..v
I
Output
_ _ _- J .
l+I
i
.
t
~-Jv
3V
OV
VOH
tpHZ~ ~Voff-OV
VOLTAGE WAVEFORMS
NOTES: A. The pulse generator has the following characteristics: Zo = 50 g, PRR s 500 kHz, tw = 100 ns.
B. CL includes probe and jig capacKance.
Figure 2. Test Circuit and Voltage Waveforms tpZH and tpHZ
1ExAs
2-202
,If
INSIRlJMENTS
POST OFFICE BOX 655303 • OAUAS, TEXAS 75265
Output
SN55113, SN75113
DUAL DIFFERENTIAL LINE DRIVERS
SLLS07OA- 01315, SEPTEMBER 1973 - REVISED FEBRUARY 1993
PARAMETER MEASUREMENT INFORMATION
Input
Pulse
Generator
(8eeNoteA)
-----------,
~----~~~
I
I
I
s V -A,N\,--,
SV
2500
1 kO
CL=30pF
(see Note B)
I
I
I
I
CL=30pF
I
IL ___________I
I
L
_________________________
_
I
I
I
NAND
Output
Output
T~eN~~
TEST CIRCUIT
--1 '- "Sn8 -j
~
I
j+-"sns
1~~-~90~%~~-1-------3V
Input
1.SW:::-
10%
1
tPZL
It
1
10%
1 ~~-----OV
1
~I
1
____~ I
Output
1
1.S V
1
1
~i
14
tPL2
"'~s_V- _____~~'v
- -'r
VOL
VOLTAGE WAVEFORMS
NOTES: C. The pulse generator has the following characteristics: Zo =50 0, PRR " 500 kHz, tw =100 ns.
D. CL includes probe and jig capacitance.
Figure 3. Test Circuit and Voltage Waveforms, tpZL and tpLZ
1ExAs
,If
INSIRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2-203
SN55113, SN75113
DUAL DIFFERENTIAL LINE DRIVERS
SLLS07OA- 01315. SEPTEMBER 1973 - REVISED FEBRUARY 1993
TYPICAL CHARACTERISTICSt
OUTPUT VOLTAGE
OUTPUT VOLTAGE
vs
vs
DATA INPUT VOLTAGE
DATA INPUT VOLTAGE
6
6
No Load
TA=25°C
VCC=5V
No Load
5
>I
f
4
i
3
I
2
j
o
~
5
>
VCC=5V
t
4
i
3
I
2
I
~
VCC = 4.5 V
o
~
o
o
TA=125°C
~CC=5.5
2
3
/
It
\
o
o
4
2
VI - Data Input Voltage - V
Figure 4
Figure 5
OUTPUT VOLTAGE
vs
vs
OUTPUT CONTROL VOLTAGE
OUTPUT CONTROL VOLTAGE
6
6
VCC=5V
Load = 500 Q to GND
Load = 500 Q to GND
TA=25°C
5
t
4
J
3
~
I
~
5
>I
VCC=5.5~
III
TA=125°C
4
5
J
VCC=5V
~
VCC=4.5~
!5
Q.
!5
3
I
2
.It
\
~
Dlaabled
TA = 25°C ,
TA =- 55°C
0
2
o
o
4
3
VI - Data Input Voltage - V
OUTPUT VOLTAGE
>I
\A=25°C
TA =_55°C
Disabled
High
HigJ
o
2
3
VI-Input Voltage (Output Control) - V
4
o
2
3
4
VI -Input Voltage (Output Control) - V
Figure 6
Figure 7
t Data for temperatures below O°C and above 70°C and for supply voltages below 4.75 V and above 5.25 V are applicable to SN55113 circuHs
only. These parameters were measured with the active pullup connected to the sink output.
1ExAs
..If
INSIRUMENTS
2-204
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
SN55113, SN75113
DUAL DIFFERENTIAL LINE DRIVERS
SLLS070A- 0131 5. SEPTEMBER 1973 - REVISED FEBRUARY 1993
TYPICAL CHARACTERISTICSt
OUTPUT VOLTAGE
6
OUTPUT VOLTAGE
vs
vs
OUTPUT CONTROL VOLTAGE
OUTPUT CONTROL VOLTAGE
6
VCC=5.5V
Load = 500 Q to VCC
VCC=5V
Load = 500 Q to VCC
TA=25·C
VCC=5V
5
5
VCC=4.5V
>I
GI
>
I
4
t
i
o
CI
III
:t::
~
!i
CI.
!i
3
I
2
~
0
~
I
~
Disabled
4
/ ' TA=25·C
~
3
2
TA=125·C
Low
I
o
o
o
2
3
VI -Input Voltage (Output Control) - V
DI"bled~
2
3
4
VI-Input VOltage (Output Control) - V
Figure 9
HIGH-LEVEL OUTPUT VOLTAGE
va
OUTPUT CURRENT
OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
I
Low
o
4
Figure 8
4
TA=-SS·C
!
VCC=4.5V
3.6
3.2
>
I
2.8
GI
CI
!!
~
!i
CI.
!i
0
2.4
2
.----
VOH(IOH = -10 mA~
r-~
.L-
------I"""
i.---
>
I
t
~
VOH(IOH = - 40 rnA)
i
1.6
o
1.2
~
I
~
I
VCC=4.5V
0.8
VOL(IOL = 40 rnA)
0.4
o
-75
I
-so
o~--~--~~--~--~~~~--~
-25
0
25
50
75
100
,TA - Free-Air Temperature _·C
125
o
Figure 10
- 20
-100
-40
-60
-80
IOH - Output Current - rnA
-120
Figure 11
t Data for temperatures below O·C and above 70·C and for supply voltages below 4.75 V and above 5.25 V ale applicable to SN55113 circuits
only. These parameters were measured with the active pullup connected to the sink output.
1ExAs
..If
INSIRUMENIS
POST OFFICE BOX 655303 • DAUAS. TEXAS 7S265
2-205
SN55113, SN75113
DUAL DIFFERENTIAL LINE DRIVERS
SLl.S07OA- 01315, SEPTEMBER 1973 - REVISED FEBRUARY 1993
TYPICAL CHARACTERISTICSt
SUPPLY CURRENT
(BOTH DRIVERS)
LOW-LEVEL OUTPUT VOLTAGE
0.6
vs
vs
OUTPUT CURRENT
SUPPLY VOLTAGE
80
1.
TA=25°C
~
0.5
>
I
III
III
~!5
Q.
VCC=4.5V
0.4
,
0.3
!5
~
~
0
I
...J
0.2
-:?
0.1
o
/
'/
'A ~
1I
it:
~
r-
No Load
TA=25°C
A
60
Inputs Grounded ~
~
VCC=5.5V
,
40
8:
:::I
30
0
}}
20
III
I
~
40
50
100
80
120
o
V
o
Figure 13
SUPPLY CURRENT
(BOTH DRIVERS)
SUPPLY CURRENT
(BOTH DRIVERS)
vs
vs
. OUTPUT CURRENT
SUPPLY VOLTAGE
100
5&
E
I
52 I-
/
2
3
4
5
678
VCC - Supply Voltage - V
Figure 12
c(
~
./
IOL - Output Current - rnA
54 I-
~ ::rlnputs Open
~
10
20
~
50
:::I
0
V
o
70
VCC=5V
RL=co
CL=30pF
80 ,... Inputs: 3-V Square Wave
I- TA=25°C
70
VCC=5V
Inputs Grounded
NoLoed
90
50
I-
C
§
48
~
Q.
46
:::I
44
0
III
..........
..........
.........
42
,
40
........
30
40
20
38
10
36
-75 -50 -25
0
25
50
75
100
TA - Free·Alr Temperature - °c
~Figure
o
125
0.1
14
t Data for temperatures below ooe and above 70
/'
50
i'-.
I
0
}}
1/"
60
0.4
10
4
f - Frequency - MHz
40
100
Figure 15
e
0
and for supply voltages below 4.75 V and above 5.25 V are applicable to SN55113 circuits
only. These parameters were measured with the active pullup connected to the sink output.
TEXAS ,.,
INSIRUMENTS
2-206
POST OFFICE BOX 655303 • DALlAS, TEXAS 75265
SN55113, SN75113
DUAL DIFFERENTIAL LINE DRIVERS
SLLS070A- 01315, SEPTEMBER 1973 - REVISED FEBRUARY 1993
TYPICAL CHARACTERISTICSt
PROPAGATION DELAY TIMES
FROM DATA INPUTS
OUTPUT ENABLE AND DISABLE TIMES
vs
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
30
20
18
16
14
VCC=5V
CL=30pF
See Figure 1
..
12
-...
~
--
tpLH
tpHL
10
.....t...-"
~V
I!
VCC=5V
See Figures 2 and 3
.
25
OJ
20
I
II>
E
i=
:;s
'"
c
"
'"
:;s
II>
is
8
15
III
'c"
6
10
w
!;
Co
4
!;
0
2
o
-75 -SO -25
0
25
SO
75 100
TA - Free-Air Temperature _·C
125
5
V
./
~
- -- -tpZL
~
I
---
:.;:..- ~ ~
tpHZ
tPZH
o
-75 -SO -25
0
25
SO
75
100
TA - Free-Air Temperature _·C
Figure 16
125
Figure 17
t Data for temperatures below O·C and above 70·C and for supply voltages below 4.75 V and above 5.25 V are applicable to SN55113 circuits
only. These parameters were measured wRh the active pullup connected to the sink output.
APPLICATION INFORMATION
Location 2
=D=
=a::>-
Twisted
Pair
location 4
SN75113 Driver
SN75115 Receiver
t AT = Z00 A capacRor may be connected in series with AT to reduce power dissipation.
Figure 18. Basic Party-Line or Data-Bus Differential Data Transmission
1ExAs
.Jf
INSlR.UMENTS
POST OFFICE BOX 655303 • DAUAS, TEXAS 75265
2-207
2-208
SN55114, SN75114
DUAL DIFFERENTIAL LINE DRIVERS
SEPTEMBER 1973 - REVISED FEBRUARY 1993
SLlS071A-
•
Choice of Open-Collector, Open-Emitter, or
Totem-Pole Outputs
•
Single-Ended or Differential AND/NAND
Outputs
Vee
2ZP
2ZS
•
Single 5-V Supply
•
•
Dual-Channel Operation
TTL Compatible
•
Short-CIrcuit Protection
•
High-Current Outputs
•
Triple inputs
•
•
Clamp Diodes at Inputs and Outputs
•
SN55114 ••• J OR W PACKAGE
SN75114 ••• D OR N PACKAGE
(TOP VIEW)
2YS
2YP
2C
2B
SN55114 ••• FK PACKAGE
(TOP VIEW)
(l)Q.O°Q.
~~z$'~
Designed for Use With SN55115 and
SN75115 Differential Line Receivers
1YS
Designed to Be Interchangeable With
Fairchild 9614 Line Driver
1YP
NC
1A
description
1B
The SN55114 and SN75114 dual differential line
drivers are designed to provide differential output
Signals with the high-current capability for driving
balanced lines, such as twisted pair, at normal line
impedances without high power dissipation. The
output stages are similar to TTL totem-pole
outputs, but with the sink outputs, YS and ZS, and
the corresponding active pullup terminals, YP and
ZP, available on adjacent package pins. Since the
output stages provide, TTL-compatible output
levels, these devices may also be used as TTL
expanders or phase splitters.
4
5
6
7
8
3 2 1 20 19
18
17
16
15
14
9 10 11 12 13
2ZS
2YS
NC
2YP
2C
Ne - No internal connection
FUNCTION TABLE
INPUTS
A
B
OUTPUTS
C
H
H
L
All other inputs combinations
H
Y
z
H
L
L
H
=high level, L =low level
The SN55114 is characterized for operation over the full military temperature range of -55°C to 125°C. The
SN75114 is characterized for operation from O°C to 70°C.
'TExAs ..,
Copyright © 1993, Taxas Instruments Incorporated
INSIRUMENIS
POST OFFICE BOX 655303 • DAUAS, TEXAS 75265
2-209
SN55114, SN75114
DUAL DIFFERENTIAL LINE DRIVERS
SLLS071A- 01315. SEPTEMBER 1973 - REVISED FEBRUARY 1993
logic symbol t
1A
1B
1C
logic diagram (positive logic)
&t>
5
6
~
~
~
7
~
2A
2B
2C
9
4
3
1
1YS
1Y2
1B - - - I
1ZP
1ZP
1C
1ZS
12
'ZiP
15
11
1A
2
13
10
1YP
1YP
14
1ZS
'ZiP
'ZiS
2A
2ZP
2YS
2B - - - I
2ZS
2ZP
2C
t This symbol is In accordance with ANSVIEEE Sid 91-1984 and
2ZS
IEC Publication 617-12.
Pin numbers shown are for the D. J. N. and W packages.
schematic (each driver)
To
OIlIer IIt1wr
~
18
vcc
AND
Pullup
4,12
•
1.15 NAND Pullup
'----~-ZP
-'-+--4""':":-'---'
A:: 3_._13__--......
t-_--'f-_r..------=2~.14
Sink OUtput
YS
•
OND
:I: These components are common to both drivers. ReSistor values shown are nominal and in ohms.
Pin numbers shown are for the D. J. N. and W packages.
.Jf
1ExAs
INSTRUMENTS
2-210
POST OFFICE BOX 6S5303 • DAUAS. TEXAS 75265
::':-..put
SN55114, SN75114
DUAL DIFFERENTIAL LINE DRIVERS
SLlS071A- 01315, SEPTEMBER 1973 - REVISED FEBRUARY 1993
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
SN55114
UNIT
SN75114
7
7
V
5.5
5.5
V
Off-state voHage applied to open-collector outputs
12
12
V
Continuous total power dissipation
See Dissipation Rating Table
Supply voHage, VCC (see Note 1)
Input voltage
Operating free-air temperature range
-55 to 125
Ot070
·C
Storage temperature range
-65 to 150
-65 to 150
·C
Case temperature for 60 seconds: FK package
260
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: J or W package
300
·C
·C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: D or N package
·C
260
NOTE 1: Voltage values are with respect to network ground terminal.
DISSIPATION RATING TABLE
PACKAGE
TAs25·C
POWER RATING
DERATING FACTOR
ABOVE TA = 25·C
TA=70·C
POWER RATING
TA=125·C
POWER RATING
D
950mW
7.6mW/"C
608mW
FKt
1375mW
11.0mW/"C
880mW
275mW
Jt
1375mW
11.0mW/"C
880mW
275mW
N
1150mW
9.2mW/"C
736mW
wt
1000mW
8.0mW/"C
640mW
200MW
t In the FK, J, and W packages, SN55114 chips are either silver glass or alloy mounted.
recommended operating conditions
SN55114
SN75114
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.75
5
5.25
Supply VOltage, VCC
High-level input voltage, VIH
Low-level input voltage, VIL
High-level output current, IOH
Low-level output current, IOL
0.8
0.8
V
-40
-40
mA
40
mA
70
·C
40
Operating free-air temperature, TA
-55
1ExAs
V
V
2
2
UNIT
125
0
,If
INSIRUMENIS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
2-211
SN55114, SN75114
DUAL DIFFERENTIAL LINE DRIVERS
SLLS071A- 01315, SEPTEMBER 1973 - REVISED FEBRUARY 1993
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN55114
PARAMETER
TEST CONDITIONSt
MIN
SN75114
TYP:j:
MAX
-0.9
-1.5
MIN
TYp:j:
MAX
-0.9
-1.5
VIK
Input clamp voltage
VCC=MIN,
II =-12 mA
VOH
High-level output
voltage
VCC=MIN,
VIL= O.BV
VIH = 2V.
VOL
low-level output
voltage
VCC=MIN,
VIL=O'SV,
VIH = 2V.
IOL=4OmA
Output clamp voltage
VCC=5V,
10=40mA,
TA=25°C
6.1
6.5
6.1
6.5
VOK
VCC = MAX,
10 =-40 mA,
TA=25°C
-1.1
-1.5
-1.1
-1.5
TA=25°C
1
10(0ff)
Off-state open collector
output current
VOH = 12V
VCC = MAX
VOH = 5.25 V
II
Input current at
maximum input voltage
VCC = MAX,
VI = 5.5V
IIH
High-level input current
VCC = MAX,
VI=2.4V
IlL
Low-level input current
VCC = MAX,
VI = 0.4 V
lOS
Short-circuit
output current:j:
VCC = MAX,
VO=O,
ICC
Supply current
(both drivers)
All Inputs at 0 V, No load,
TA=25°C
IOH=-10 mA
2.4
3.4
2,4
3.4
IOH=-4OmA
2
3
2
3
0.2
0.4
0.2
V
V
0.45
V
V
100
200
TA= 125°C
UNIT
1
TA = 25°C
100
fAA
200
TA=70°C
1
1
40
fAA
-1.1
-1.6
mA
-90
-120
mA
40
-40
TA=25°C
-1.1
-1.6
-90
-120
-40
mA
Ivcc = MAX
37
50
37
50
VCC=7V
47
65
47
70
mA
t All parameters with the excepllon of off-state open-collector output current are measured with the active pullup connected to the sink output. For
conditions shown as MIN or MAX. use the appropriate value specified under recommended operating conditions.
:j: All typical values are at TA = 25°C and VCC = 5 V, with the exception of ICC at 7 V.
§ Only one output should be shorted at a time, and duration of the short circuit should not exceed one second.
switching characteristics,
Vee = 5 V, TA = 25°C
TEST
CONDITIONS
PARAMETER
tpLH
Propagation delay time, low-to-hlgh-Ievel output
tpHL
Propagation delay time, hlgh-to-Iow-Ievel output
2-212
SN75114
SN55114
MIN
CL=30pF,
See Figure 1
1ExAs'"
TYP
MIN
TYP
MAX
UNIT
15
20
15
30
ns
11
20
11
30
ns
INSTRUMENTS
POST OFFICE BOX 655303 • DAUAS, lEXAS 75265
MAX
,_
SN55114, SN75114
DUAL DIFFERENTIAL LINE DRIVERS
SLLS071A- 01315, SEPTEMBER 1973 - REVISED FEBRUARY 1993
PARAMETER MEASUREMENT INFORMATION
~
Input
1+-,,5ns
'
1.5~
~
:
1-----,
2kg
9O%~1_..lI-----3V
\
VCC=5V
1
Input
1
10%
,
y
AND Output
[ __ ...J
.I
CL=30pF
"::" (see Note B)
y
AND Output
1
1
1'--______ 1•
I
14
Y
Output
I+- ,,5ns
~
1.5V,
,
10%
tw ----.!.I
I
,.;",;=--- 0 V
114-4-_1- tPLH
14-14-~.11-
I
,I
tpHL
...J ___ VOH
,
,I
"
.I
CL=30pF
"::" (see Note B)
1.5 V
VOL
14
yVOH
1.57
TEST CIRCUIT
--VOL
VOLTAGE WAVEFORMS
NOTES: A The pulse generator has the following characteristics:
B. Cl includes probe and jig capacftanca.
Zo = 500 g,
PRR " 500 kHz, tw " 100 ns.
Figure 1. Test Circuit and Voltage Waveforms
TYPICAL CHARACTERISTICSt
OUTPU~ VOLTAGE
6
OUTPUT VOLTAGE
va
va
DATA INPUT VOLTAGE
DATA INPUT VOLTAGE
6
Nolosd
TA=25·C
VCC=5V
NoLoed
5
5
>
I
J
i
o
~
I
~
>I
VCC=5.5V
4
GI
CI
VCC=5V
It
3
0
I
2
~
o
o
2
VI -
4
3
oats Input Voltage -
'j
~
~
SQ.
S
VCC =4.5V
3
TA=1~C
4
2
o
o
V
Figure 2
\
TA=25·C
TA=-55·C
2
3
4
VI - Data Input Voltage - V
Figure 3
t Data for temperatures below O·C and above 70·C and for supply voltages below 4.75 Vand above 5.25 V are applicable to SN55114 circuits
only. These parameters were measured with the active pullup connected to the sink output.
POST OFFICE BOX 655303 • OAUAS, TEXAS 75265
2-213
SN55114, SN75114
DUAL DIFFERENTIAL LINE DRIVERS
SlJ.S071A- 01315. SEPTEMBER 1973 - REVISED FEBRUARY 1993
TYPICAL CHARACTERISTICSt
LOW-LEVEL OUTPUT VOLTAGE
HIGH-LEVEL OUTPUT VOLTAGE
VB
VB
OUTPUT CURRENT
OUTPUT ClIRRENT
5r---,----r--~----r---,---~
0.4
I I
I
TA =25°C
>I
>
...
...I
VCC=5.5V ~
0.3
I
I
~
!i
CL
!i
~
1
5
0.2
0
/
I
I
....I
VCC=4.5V
~
~
0.1
V
o
O~--~--~~--....I----....I~~~---....I
o
-20
-40
-60
-so
-100 -120
o
V
10
20
30
VB
FREE-AIR TEMPERATURE
f
!i
VOH(lOH = -10 mAl
2
!
1.6
~
1.2
~ r--
-~
~
----
.,c
~~
I
GI
VCC=5V
See Figure 1
30
E
I---- ~
1=
ic
VOH(IOH = -40 rnA)
c
./
20
iIi'
I
.-:~
CL
e
IL
V
~
-
10
tpHL
0.8
0.4
SO
40
.!
, 3.2
2.4
70
PROPAGATION DELAY TIMES
FREE-AIR TEMPERATURE
3.6
2.8
60
VB
Vcc =4.5V
...I
50
FigureS
OUTPUT VOLTAGE
>
40
IOL - Output Current - mA
Figure 4
I
~=4.5V
/
IOH - oUtput Current - mA
4
1/
~
I
V?L(lo~ = 40 mAl
I
o
-75 -50 -25
0
25
o
50
75
100
125
-75 -50 -25
TA - Free-Air Temperature - °c
0
25
50
75
100
125
TA - Free-Air Temperature:.. °c
Figure 6
Figure 7
t Data for tempen¢ures below ooe and above 7poe are applicable to SN55114 circuits only. These parameters were measured with the active
pullup connected to the sink output.
1ExAs
.Jf
INSIRUMENTS
2-214
POST OFFICE BOX 655303 • DALlAS. TEXAS 75265
SN55114, SN75114
DUAL DIFFERENTIAL LINE DRIVERS
SLLS071A- 01315, SEPTEMBER 1973 - REVISED FEBRUARY 1993
TYPICAL CHARACTERISTICSt
SUPPLY CURRENT
(BOTH DRIVERS)
SUPPLY CURRENT
(BOTH DRIVERS)
VS
va
SUPPLY VOLTAGE
FREE-AIR TEMPERATURE
80
70
42
r-
No Load
TA=25·C
VCC=5V
Inputs Grounded
OU1puta Open
40
~
60
~
C
SO
C
~::I
I
..
I
Inputs GrOunded.....
I:
::I
(J
......
~
::I
Ul
40
30
I
(J
E
20
10
o
./
o
/
I
V
V
~open
38
............
(J
36
......
~
-
~
::I
Ul
I
(J
34
E
32
"
~
30
2
3
4
5
6
7
-75
8
-SO -25
VCC - Supply Voltage - V
0
25
50
75
TA - Free-Air Temperature - DC
"
100
125
Figure 9
FigureS
SUPPLY CURRENT
(BOTH DRIVERS)
vs
FREQUENCY
100
JCCI=~~II
RL= co
c(
80 - CL=3OpF
InpU1s: 3-V Square Wave
TA=25·C
E
I
C
e
60
~I
~
(J
......
,,/
~
::I
Ul
40
I
(J
E
20
o
0.1
0.4
4
10
f - Frequency - MHz
40
100
Figure 10
t Data for temperatures below O·C and above 70·C are applicable to SN55114 circuits only. These parameters were measured with the active
pullup connected to the sink output.
TEXAS..If
INSIRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
2--215
SN55114, SN75114
DUAL DIFFERENTIAL LINE DRIVERS
Su.so71A- 01315, SEPTEMBER 1973 - REVISED FEBRUARY 1993
APPLICATION INFORMATIONt
1/2SN75114
Driver
@~f~<\~RTt
1/2SN75115
Receiver
Twieted Pair
t AT = ZOo A capac.or may be connected In series with AT to reduce power dissipation.
Figure 11. Basic Party-Line or Data-Bus Differential Data Transmission
1ExAs ...,
INSIRUMENTS
2-216
POST OFFICE BOX 655303 • OALLAS. TEXAS 75265
SN55115, SN75115
DUAL DIFFERENTIAL LINE RECEIVERS
SN55115 ••• J OR w PACKAGE
SN75115 ••• D OR N PACKAGE
• Choice of Open-Collector or Active Pullup
(Totem-Pole) Outputs
(TOP VIEW)
• Single 5-V Supply
• Differential Line Operation
1YS
1YP
1STRB
1RTC
1B
• Dual-Channel Operation
• TTL Compatible
• ± 15-V Common-Mode Input Voltage Range
• Optional-Use BulH-ln 130-Q LineTerminating Resistor
• Individual Frequency Response Controls
• Individual Channel Strobes
• Designed for Use With SN55113, SN75113,
SN55114, and SN75114 Drivers
The SN55115 and SN75115 dual differential line
receivers are designed to sense small differential
signals in the presence of large common-mode
noise. These devices give TTL-compatible output
signals as a function of the differential input
voltage. The open-collector output configuration
permits the wire-ANDing of similar TTL outputs
(such as SN5401/SN7401) or other SN55115/
SN75115 line receivers. This permits a level of
logic to be implemented without extra delay. The
output stages are similar to TTL totem-pole
outputs, but with sink outputs, 1YS and 2YS, and
the corresponding active pullup terminals, 1YP
and 2YP, available on adjacent package pins. The
frequency response and noise immunity may be
provided by a single external capacitor. A strobe
input is provided for each channel. With the strobe
in the low level, the receiver is disabled and the
outputs are forced to a high level.
Vee
2YS
2YP
2STRB
2RTC
2B
2RT
2A
SN55114 ••• FK PACKAGE
(TOP VIEW)
~~o8~
~ ~ Z> N
• Designed to Be interchangeable With
Fairchild 9615 Line Receivers
description
3
16
15
14
13
12
11
10
9
1STRB
1RTC
NC
1B
1RT
4
5
6
7
8
3 2 1 2019
18
17
16
15
14
9 10 11 1213
2YP
2STRB
NC
2RTC
2B
Ne - No internal connection
FUNCTION TABLE
DIFF
INPUT
STRB
(A AND B)
L
X
H
L
H
H
OUTPUT
(YP AND YS TIED TOGETHER)
..
H
H
L
H = VI " VIH min or VID more posftlve than VT + max
L =VI s VIL max or VIO more negative than
max
X =irrelevant
v-r _
The SN55115 is characterized for operation over the full military range of-55°C to 125°C. The SN75115 is
characterized for operation from O°C to 70°C.
Copyright @ 1993, Texas Instruments Incorporated
TEXAS . "
INSIRUMENIS
POST OFFICE BOX 655303 • DAUAS, TEXAS 75265
2-217
SN55115, SN75115
DUAL DIFFERENTIAL LINE RECEIVERS
SLLS072A- 01315, SEPTEMBER 1973 - REVISED FEBRUARY 1993
logic symbol t
1B
1A
1RT
1STRB
1RTC
2B
2A
2RT
2STRB
2RTC
]~
5
7
"-
6
&~
2
~
AT
3
4
11
9
logic diagram (positive logic)
1
~
1VP
1YS
RSP
14
"-
10
13
12
2YP
15
2YS
1B
1A
1RT
1RTC
1SRTB
2B
2A
2RT
2RTC
2SRTB
p~
~~
13
1YP(pullup)
1YS (SInk)
2YP (Pull up)
2YS (SInk)
'
t This symbol Is in accordance wRh ANSVIEEE Std 91-1984
and lEe Publication 617-12.
schematic (each receiver)
Strobe
3,13
1k
1.5k
Respon..
11me
Control
4,12
r---~--~--~~VCC
1k
1.Mk
20
L-__4-~---=2,~14P~UP
Ik
,!
+--____-f:=::j:=~:""-____.J
3k
In p 5.~11~____
....---_----'''''1 Sink
~-+~----,
130
Uk
~~
L-__-+__~------_+------~~--8~GND
Common to
Both R_lvere
~------,
I Uk
I
I
Y. I
I
I
I
I
I 150
I
IL..! _ _ _ _ _ _ I
Resistor values are nominal and in ohms.
Pin numbers shown are for 0, J, N, and W packages.
1ExAs ."
I}lfSIRUME'NTS
2-218
POST OFFICE BOX 655303 • DAUAS, TEXAS 75265
SN55115, SN75115
DUAL DIFFERENTIAL LINE RECEIVERS
SLLS072A- 01315, SEPTEMBER 1973 - REVISED FEBRUARY 1993
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
SN75115
SN55115
Supply voltage, VCC (see Note 1)
Input voltage at A. B, and
Rr
Input voltage at STRB
Off-state voRage applied to open-collector outputs
UNIT
7
7
",25
",25
V
5.5
5.5
V
14
14
V
Continuous total power dissipation (see Note 2)
V
See Dissipation Reting Table
Operating free-air temperature range
-55 to 125
Ot070
°c
Storage temperature range
-65 to 150
-65 to 150
°c
Case temperature for 60 seconds: FK package
260
°c
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: J or W package
300
°c
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: D or N package
°c
260
NOTE 1: All voltage values, except differential input voltage, are wfth respect to network ground terminal.
DISSIPATION RATING TABLE
PACKAGE
TA,,25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
TA=70°C
POWER RATING
TA = 125°C
POWER RATING
D
950mW
7.6mWrC
60BmW
FKt
1375mW
11.0mWrC
BBOmW
275mW
Jt
1375mW
11.0mWrC
BBOmW
275mW
N
1150mW
9.2mWrC
736mW
wt
l000mW
B.OmWrC
640mW
200mW
t In the FK, J, and W packages, SN55115 chips are either silver glass or alloy mounted. SN75115 chips are glass
mounted.
recommended operating conditions
SN75115
SN55115
MIN
NOM
MAX
MIN
NOM
MAX
Supply voRage, VCC
4.5
5
5.5
4.75
5
5.25
High-level input voltage at STRB, VIH
2.4
UNIT
V
V
2.4
Low-level input voltage at STRB, VIL
0.4
0.4
V
High-level output current, IOH
-5
-5
rnA
15
rnA
70
°c
Low-level output current, IOL
15
Operating free-air temperature, TA
-55
TEXAS
125
0
..If
INSIRUMENTS
POST OFFICE BOX 655303 • DALlAS, TEXAS 75265
2-219
SN55115, SN75115
DUAL DIFFERENTIAL LINE RECEIVERS
SLLS072A- 01315, SEPTEMBER 1973 - REVISED FEBRUARY 1993
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
SN55115
TEST CONDITIONSt
MIN
Vr+§
Positive-going
threshold voltage
VO=O .4 V,
10L= 1SmA,
VIC=O
Vr-§
Negative-going
threshold vqltage
VO=2.4V,
10H =-SmA,
VIC=O
VICR
Common-mode
input voltage range
VIO= ",1 V
VOH
High-level ouput
voltage
VCC=MIN,
10H=-SmA
TYP*
VOL
Low-level output
voltage
VCC = MIN,
10L= 1SmA
IlL
Low-level input
current
VI = 0.4 V,
VCC = MAX,
Other input at 5. S V
+24
to
-19
TA=MIN
2.2
TA=2S·C
2.4
VCC=MIN,
Vstrobe = 4.S V
VIO=-O.SV,
ISL
Low-level strobe
current
VCC = MAX,
Vstrobe = 0.4 V
VID= O.SV,
I(RTC)
ResponSe-timacontroi current
VCC=MAX,
VRC=O
VIO = O.SV,
VCC = MIN,
VIO=-4.SV
VOH= 12V,
VCC=MIN,
VIO=-4.7SV
VOH =S.2SV,
. Off-state open10(0f!) collector output
current
AT
Una-terminating
resistance
VCC=SV
lOS
Supply-circuit output current #
VCC=MAX,
VO=O
VID = -O.SV,
ICC
Supply current
(both receivers)
VCC = MAX,
VIC=O
VID = O.SV,
MAX
TA=MAX
2.4
SOO
+1S
to
-1S
mV
+24
to
-19
2.4
i
V
3.4
0.4
0.22
-0.9
-O.S
TA=2S·C
V
0.45
-O.S
-0.7
-0.7
TA=2S·C
2
S
TA=MAX
S
10
-1.1S
-1.2
-US
-1.2
TA=2S·C
100
TA=MAX
200
mA
-0.7
-2.4
-3.4
V
-0.9
-0.7
TA=MAX
TA=2S·C
mV
2.4
0.22
TA=2S·C
UNIT
2.4
3.4
TA=MIN
High-level strobe.
current
TYP*
-500'11
-SOO'
VIO=-O.SV,
ISH
MIN
500
+1S
to
-1S
VIO=-O.SV,
SN75115
MAX
-2.4
-3.4
I!A
mA
mA
TA=2S·C
100
TA=MAX
200
I!A
g
TA=2S·C
77
130
167
74
130
179
TA=2S·C
-1S
-40
-80
-14
-40
-100
rnA
32
SO
32
SO
mA
TA=2S·C
t Unless othel'Wlse noted, Vstrobe = 2.4 V, All parameters with the exception of off-state open-collector output current are measured With the active
pull-up connected to the sink output,
* All typical values are at VCC = S V, TA = 2S·C, and VIC = O. .
§ Oifferential vottages are at the B input terminal with respect to the A input terminal.
'II The algebraic convention, in which the less positive (more negative) limit is designated as minimum, Is used in this data sheet for threshold
vottages only.
# Only one output should be shorted to ground at a time, and duration of the short circuit should not exceed one second.
. 1ExAs'"
INSlRUMENTS
2-220
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN55115, SN75115
DUAL DIFFERENTIAL UNE RECEIVERS
SUS072A- 01315, SEPTEMBER' 1973 - REVISED FEBRUARY 1993
switching characteristics, VCC
=5 V, CL =30 pF, TA =25°C
PARAMETER
SN55115
TEST CONDmONS
MIN
SN75115
TYP
MAX
MIN
TYP
MAX
UNIT
Propagation delay time,
low-to-high level output
RL = 3.9 kg, See Figure 1
18
50
18
75
ns
Propagation delay time,
tpHL high-to-low level output
RL = 390 g, See Figure 1
20
50
20
75
ns
tpLH
PARAMETER MEASUREMENT INFORMATION
Open
Input----.
5V
2.4 V
!!:I'_--_.
!.~__I
Jt:k-!
'" 5 ns -.t ..-.t
Differential
-90%---90%-0
Input
OV
10% 'I
!yp
Pulse
Generator
(see Note A)
1P.~_---VO
ResPonse
Time Control
Open
I
-.t
CL=30pF
(S88 Note B)
"-1
1
Output
..- '" 5 ns
.,jv\l;-r--- - -
tpHL
1.5V
1
10%
-.r
"-1
3V
-3 V
tpLH
VOH
1.5V
'----_..I.
TEST CIRCUIT
VOLTAGE WAVEFORM
NOTES: A. The pulse generator has the following characteristics: Zo = 50 g, PRR '" 500 kHz,
B. CL includes probe and jig capacftance.
tw '" 100 ns, duty cycle = 50%.
Figure 1. Test Circuit and Voltage Waveforms
TYPICAL CHARACTERISTICS
INPUT CURRENT
vs
INPUT VOLTAGE
6
V~C=~V
I
I
I
I
Input Not Under Test at 0 V
4 - TA=25°C
cc
E
I
iI:
:J
0
!I
D.
.5
I
=
V
0
/
-2
/
-6
V
/
2
-4
/
V
/.
V
/
-25 -20-15-10 -5
0
5
10
15
20
25
VI -Input Voltage" V
Figure 2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2-221
SN55115, SN75115
DUAL DIFFERENTIAL LINE RECEIVERS
SLLS072A-: 01315. SEPTEMBER 1973 - REVISED FEBRUARY 1993
TYPICAL CHARACTERISTICSt
OUTPUT VOLTAGE
OUTPUT VOLTAGE
vs
vs
FREE-AIR TEMPERATURE
COMMON-MODE INPUT VOLTAGE
4
6
VCC=4.5V
3.4
I
>I
III
iii'
=
~
'Sa.
'S
0
I
J
I
.-- ---
3.2
No Load
TA=25°C
I
VOH (VIO = -0.5 V, IOH = -5 ~
2.8
2.4
5
VCC=5.5V
~
>I
!:!
i
3
I
2
~
2
1.6
VCC=5V
VCC=4.5V
..........
o
I
u
t
4
1.2
~
/'
I
I
I
j
VIO =-1 V
0.8
0.4 I-- VOL (VIO = 0.5 V, IOL = 15 rnA)
I
o
-75 -150 -25 . 0
25
50
75
100
'"
o
125
Vl
/
-25-20-15 -10 -5
TA - Free-Alr Temperature - ·C
r l'
1
0
5
10
15
20
25
VIC - Common-Mode Input Voltage - V
Figure 3
Figure 4
LOW-LEVEL OUTPUT VOLTAGE
HIGH·LEVEL OUTPUT VOLTAGE
vs
vs
OUTPUT CURRENT
OUTPUT CURRENT
0.4 .----r--T"""-"""T---r----,....---,
5r----,-----r----~--~r---~
VIO=-0.5V
TA=25·C
VIO=0.5V
TA=25·C
>I
i
0.3 I---+---i----+---I--~~--I
~
i
o
I
~
0.2 1---+---i-""2iP9---+-----1I----I
0.1
~
O~--~--L---~-~~-~
o
-10
-20
-30
o
-50
-40
L-_~_~~_~_~
o
IOH - High-Level Output Current - mA
5
10
15
__
20
~_~
25
30
IOL- Low-Level Output Current - mA
Figure 5
Figure 6
t Data for temperatures below o·e and above 70·e and for supply voHages below 4.75 V and above 5.25 V are applicable to SN55115 circuits
only. These parameters were measured with the active pullup connected to the sink output.
1ExAs ..,
2-222
INSIRUMENTS
POST OFFICE BOX 655303 • DAUAS. TEXAS 75265
SN55115, SN75115
DUAL DIFFERENTIAL LINE RECEIVERS
SLLS072A- 01315. SEPTEMBER 1973 - REVISED FEBRUARY 1993
TYPICAL CHARACTERISTICSt
OUTPUT VOLTAGE
OUTPUT VOLTAGE
vs
vs
DIFFERENTIAL INPUT VOLTAGE
DIFFERENTIAL INPUT VOLTAGE
6
6
_1-
VCC=5.5V
Vee=5V
Load = 2 kQ to Vee
,
5
15
Co
15
3
1
2
>1
III
~
5
Vee =4.5V
>1
TAi1250e
4
l
III
DO
:t::
4
~
3
•
TA=25 e - - ....
~
15
TA=-55°e
0
-?
Vee=5V
0
1
-?
o
-0.2
o
-0.1
0.1
2
Load = 2 kQ to Vee
TA=25"e
o
-0.2 -0.15 -0.1 -0.05
0.2
vs
vs
STROBE INPUT VOLTAGE
STROBE INPUT VOLTAGE
6
Ii
:t::
4
.....
\
3
1
2
0
-?
5
Vee=5.5V
~
15
Co
15
0.15
0.2
6
No Load
VID =0.5V
TA=25°e
5
III
0.1
OUTPUT VOLTAGE
OUTPUT VOLTAGE
1
0.5
Figure 8
Figure 7
>
0
VID - Differential Input Voltage - V
VIO - Differential Input Voltage - V
~
- ,
>
..
~
1
~
DO
•
.......
4
:t::
veei\~ \
~
15
3
1
2
,/'
5'
0
-?
Vee =4.5V
,
Vee=5V
No Load
VID=0.5V -
/
\
O
Tj=1j e
iA=-~oe
(
I
>- JA=JOe
0.5
1.5
2
2.5
3
3.5
4
o
o
Vatrobe - Strobe Input Voltage - V
0.5
1
1.5
2
2.5
3
3.5
Vatrobe - Strobe Input Voltage - V
4
Figure 10
Figure 9
t Data for temperatures below O°C and above 70°C and for supply voltages below 4.75 Vand above 5.25 V are applicable to SN55115 circuits
only. These parameters were measured with the active pullup connected to the sink output.
1ExAs ."
INSIRUMENTS
POST OFFICE BOX 655303 • DAUAS, TEXAS 75265
2-223
SN55115, SN75115
DUAL DIFFERENTIAL LINE RECEIVERS
SLLS072A- 01315, SEPTEMBER 1973 - REVISED FEBRUARY 1993
TYPICAL CHARACTERISTICSt
SUPPLY CURRENT
(BOTH RECEIVERS)
SUPPLY CURRENT
(BOTH RECEIVERS)
vs
vs
SUPPLY VOLTAGE
FREE-AIR TEMPERATURE
60
40
No load
TA=25"C
35'
50
DE 13
13
DE - - - - - - . - - - ,
4 DYP
DYS
EN
DA 14
DZP
DB 15
DZS
DYP(pullup)
DYS(slnk)
DA
DB - - , . _....... ~J'""1
&1>
RB 7
RA
DZP(pullup)
RYP
RT
RS
DZS (sink)
RYS
'116 Receiver
RESP
RTe
SN75118
&1>
DE 13
DZS
RB 7
SN75118 Receiver
I>
RA
RYP
AT
RE
4 DYP
3 DYS
1 DZP
EN
DA 14
DB 15
RT
RYP(pullup)
RYS (sink)
RE
:~
RYS
EN
RTe
RESP
EN
I>
DI
"V 1-_--.--..::;3 A
"V
2B
RY
r
SN75119
DE 7
DI
1
RE 5
EN
EN
I>
RYS (sink)
SN75117 Driver and Receiver
5
RS - - - - - - - - - - - - - ,
&
c
~en
mz
~ ::IJCI'I
mCl'l
~
I
~
p,
;;:
Z:::
-40)
»'0
~
'z
!!!
.......
'-CI'I.....
'":III Z
m .....
~
CJ>
m
-40)
::IJ-4
»::::t:
Z::IJ
..,mc enc:
omen .
~ _Z
....
~ <
mCl'l
III
:II
~
1ll
i'
j
cO
l!!
::IJ:::
en CO
SN55116,SN75116 THRUSN75119
DIFFERENTIAL LINE TRANSCEIVERS
SLlS073A- 02143. MAY 1976 - RI;VISEO FEBRUARY 1993
switching characteristics, VCC
=5 V, CL =30 pF, TA =25°C
receiver section
PARAMETER
TEST CONDITIONS
tpLH
Propagation delay time. low-to-high-Ievel output
tpHL
Propagation delay time. high-to-Iow-Ievel output
tpZH
Output enable time to high level
tPZL
Output enable time to low level
tPHZ
Output disable time from high level
tl'Ll
Output disable time from low level
SN75118and
SN75119 only
MIN
TYP
MAX
20
75
UNIT
ns
17
75
ns
ns
RL=400 O.
See Figure 16
RL=4800.
See Figure 14
9
20
RL=2500.
See Figure 15
16
35
ns
RL=4800.
See Figure 14
12
30
ns
RL= 250 O.
See Figure 15
17
35
ns
TYPICAL CHARACTERISTICS
DRIVER OUTPUT VOLTAGE
6
DRIVER OUTPUT VOLTAGE
va
vs
DRIVER INPUT VOLTAGE
DRIVER INPUT VOLTAGE
6
No Load
TA=25°C
VCC=5V
No Load
5
>I
..
5
VCC=5.5V
4
J
~
i
I
J'
>
I
VCct=5V
VCC=4.5V
t
4
i
o
3
~
3
2
~-
I
2
J'
TA=-55°C
-i
I
TA = 25°C
-f
I
TA=125°C
o
o
2
3
o
o
4
VI -Input Voltage - V
VI -Input Voltage - V
Figure 1
Figure 2
.Jf
lExAs ..
INSIRUMENTS
2~36
-f
2
POST OFFICE BOX 655303 • DAUAS. TEXAS 75265
I
3
4
SN55116, SN75116 THRU SN75119
DIFFERENTIAL LINE TRANSCEIVERS
SLLS073A- 02143, MAY 1976 - REVISED FEBRUARY 1993
TYPICAL CHARACTERISTICS
DRIVER HIGH-LEVEL OUTPUT VOLTAGE
DRIVER LOW-LEVEL OUTPUT VOLTAGE
vs
vs
HIGH-LEVEL OUTPUT CURRENT
LOW-LEVEL OUTPUT CURRENT
0.6
,
>I
>I
5
II
~
DI
~
GI
DI
VCC=4.5~
or
~
~
4
0.4
:;
'$
g
~
X
TA=~'C
0.5
Co
"5
0
3
Gi
0.3
~
...J
~
2
0.2
I
...J
I
.p
:J:
.p
0.1
o
V
V
L
o
20
IOH - High-Level Output Current - mA
/'
/
40
I
:l
E
1=
~
Gi
Q
c
0
ii
fl
Co
2
12
50
100
80
vs
FREE-AIR TEMPERATUREt
FREE-AIR TEMPERATUREt
30
tpHL
120
DRIVER OUTPUT ENABLE AND DISABLE TIMES
vs
20
c
VCC =5.5V
Figure 4
DRIVER PROPAGATION DELAY TIMES
II)
~"
IOL - Low-Level Output Current - mA
Figure 3
VCC=5V
18 -CL=3OpF
See Figure 13
16
tpLH
14
~
--
-
,.
I-"""
II)
c
I
II)
1
25
I
GI
-~
E
1=
tpLZ
II
20
..,c
15
2i
or
.!!!
1_
VCC=5V
See Note A
-~
./
l..---V
/
~
tpHZ _
Q
10
or
GI
8
6
2i
or
c
10
"5
9:::I
5
w
D.
4
0
tpZH
2
o
-75 -50
-25
0
25
50
75 100
TA - Free-Air Temperature -'C
125
o
-75 -50
-25
0
25
50
75
100
TA - Free-Air Temperature -'C
125
Figure 6
Figure 5
t Data for temperatures below o'e and above 70'e are applicable to SN55116.
NOTE A: For tpZH and tpHZ: RL = 180 Q, see Figure 14. For tpZL and tpLZ: RL = 250 Cl, see Figure 15.
1ExAs
~
INSIRUMENTS
POST OFFICE BOX 655303 • DAUAS. TEXAS 75265
2-237
SN55116, SN75116 THRU SN75119
DIFFERENTIAL LINE TRANSCEIVERS
SLLS073A- 02143, MAY 1976- REVISED FEBRUARY 1993
TYPICAL CHARACTERISTICS
RECEIVER OUTPUT VOLTAGE
6
va
DIFFERENTIAL INPUT VOLTAGE
DIFFERENTIAL INPUT VOLTAGEt
6
Vee = 5.5 V
Load = 2 kQ to Vee
TA=25°e
Vee=5V
5
RECEIVER OUTPUT VOLTAGE
va
Vee=6V
Load 2 kQ to Vee
=
5
Vee=4.5V
'>
I
>I
4
til
I
~
!S
t
i
o
~
3
t
0
I
~
I
2
~
\.
o
-0.2
o
-0.1
0.1
4
- - - TA = 1250C
"I
3
I
e- : - - TA=25°e
2
TA=-55°e - - t
o
-0.2
0.2
o
-0.1
Figure 7 '
II!
25
II
I
E
1=
~
Q
c
iIi
e-
20
15
.. ~
--
tP~
i.....-
va
FREE·AIR TEMPERATUREt
Vee=5V
See Note A
III
C
I
/'
V
RECEIVER OUTPUT ENABLE AND DISABLE TIMES
30
/
Vee=5V
RL=400Q
See Figure 16
81
,L
"..,..
E
1=
CD
I
Q
'0
tpHL
Iii
20
15
til
10
5
!S
a.
!S
w
o.
0
-75 -50 -25
0
25
50
75 100
TA - Free-Air Temperature - °e
/
25
81
ic
o
125
10
--
~
--
--
~I
tPZL
~
~HZ
--
5
o
-75 -50
-25
0
25
50
75
100
TA - Free-Air Temperature - °e
Figure 10
t Oata for temperatures below O°C and above 70°C are applicable to SN55116.
NOTE A: For tpZH and tpHZ :RL= 480 Q, see Figure 14. For tpZL and tpLZ: RL = 250 Q, see Figure 15.
1ExAs
tPI.Z~
/
tPZH
Figure 9
.Jf
INSIRUMENIS
2-238
0.2
FigureS
RECEIVER PROPAGATION DELAY TIMES
VB
FREE·AIR TEMPERATUREt
30
0.1
VIO - Olfferentlallnput VOltage - V
VIO - Oifferentlallnput Voltage - V
POST OFFice BOX 855303 • DAUAS, TEXAS 75265
125
SN55116, SN75116 THRU SN75119
DIFFERENTIAL LINE TRANSCEIVERS
SLLS073A- 02143, MAY 1976 - REVISED FEBRUARY 1993
TYPICAL CHARACTERISTICS
SUPPLY CURRENT (DRIVER AND RECEIVER)
SUPPLY CURRENT (DRIVER AND RECEIVER)
va
va
SUPPLY VOLTAGE
FREE-AIR TEMPERATUREt
BO
70
1
60
I
50
I-
50
No Load
TA=25·e
Vee=5V
45
V
I
u
~
Q.
::I
Ib
I
U
E
/
40
30
20
)
10
o
40
,I
/./
1
35
'E
30
u
25
I
§
V
~
Q.
::I
I
r-
20
U
E
15
10
5
o
2345678
Vee - Supply Voltage - V
-75 -50 -25
0
25
50
75 100
TA - Free-Air Temperature -·e
Figure 11
t
~
Ib
V
o
--
125
Figure 12
Data for temperatures below o·e and above 70·C are appDcable to SN55116.
POST OFACE BOX 655303 • DALlAS, TEXAS 75265
2-239
SN55116, SN75116 THRU SN75119
DIFFERENTIAL LINE TRANSCEIVERS
SLLS073A- 02143, MAY 1976 - REVISED FEBRUARY 1993
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
---1---
Test
Point
From Output
Under Test
CL=3OpF
(eee Note 8)
T
1
----.----1..--
CL=3OpF
(eee Note 8)
r-"Sn8
I~~
Input
1~ 1
~
I
I
LOAD CIRCUIT
tpLH
1\:10%
,
I
11.5
AND
Output
r---
Input
tPLH
!. l~s:___
V
--I
3V
OV
~I
I
I"
tpHL
r-"sns
----'
~tPZH
I
1
1.SV
.
_ _ _- J
Test
Point
--l:I---~~_'_Test
From Output
Under Test
CL = 30 pF Point
(eee Note 8)
J.
I-"sns
I
I.
I
VOH
I
0.5 VVoff = 0 V
' .. 1
tpHZ ~
~
CL=3OpF
(eee Note 8)
I
I
I _ 10%
I
I
-l
3V
0V
Jf=-
8 Input
(see Note E)
10%
tPLZ --,114-"-_~1
Output----""\1.SV
(see Note C)
I-"sns
1,~ ~V I
~I tpZL
t-~_II..--,
LOAD .CIRCUIT
i '-----
-1
SV
-..--_--Jo___..-__
LOAD CIRCUIT
10%
KJ=T!
Figure 14. tpZH and tpHZ
~ RL=250IJ
:;J;:
I
OV
VOLTAGE WAVEFORMS
SV
Input
._10%
VOL
Figure 13. tpLH and tpHL (drivers only)
-l
.
I
I
I
I
I
VOH
VOLTAGE WAVEFORMS
From Output
Under Test
"Sns
1~~I
I
VOL
t-
---,
r---3V
1.:C:-
I
Output
\~s~---
V
J
10%
VOH
'----*- tpHL
~I
'"
"Sns
~v~r------
\1.5
~~~ !
t-
---,
.
RL=480Q
T
LOAD CIRCUIT
--I
Test
Point
I
I
I - "Sns
I
--.j
-r-rVOff=SV
Output
,..- tpHL
~
-1
""'"
-
I - "Sns
~~."
I
-.I
-(see--Not-e-E) VH
10%
14- tpLH
I'
\\,,1,_S_V_ _ _ _--'.
~~___
V
L
VOH
VOL
-fVOL
VOLTAGE WAVEFORMS
VOLTAGE WAVEFORMS
Figure 15. tpZL and tpLZ
Figure 16. tpLH and tpHL (receivers only)
NOTES: A. Input pulses are supplied by generators having the following characteristics Zo = 50 IJ,' PRR " 500 kHz, tw = 100 ns.
B. CL includes probe and jig capac~ance.
C. All diodes are 1N3064 or equivalent.
D. When testing the '116 and SN75118 receiver sections, the response-time control and the termination resistor pins are left open.
E. For '116 and SN75118, VH = 3 V, VL = - 3 V. the A input is at 0 V.
forSN75117 and SN75119, VH = 3 V, VL 0, the A inputis at 1.5 V.
=
2-240
INSIRUMENIS
TEXAS ""
POST OFFICE BOX 655303 • DAUAS, TEXAS 75265
SN55121, SN75121
DUAL LINE DRIVERS
1993
SN55121 .•• J PACKAGE
SN75121 ..• 0 OR N PACKAGE
• Designed for Digital Data Transmission
Over 5().0 to 500-0 Coaxial Cable, Strip
Line, or Twisted Pair
(TOP VIEW)
• High Speed
tpd =20 ns Max at Cl = 15 pF
VCC
2F
2E
2D
2C
28
• TTL CQmpatlble With Single S-V Supply
• 2.4-V Output at IOH = -75 rnA
• Uncommitted Emitter-FOllower Output
Structure for Party-Line Operation
1Y
GND
• Short-CIrcuit Protection
• AND-OR logic Configuration
2A
SN55121 .•. FK PACKAGE
• Designed for Use With Triple Line
Receivers SN55122, SN75122
(TOP VIEW)
00
~~z:$'\!;;
• Designed to Be Interchangeable With
Signetics N8T13
1C
description
10
NC
1E
1F
The SN55121 and SN75121 dual line drivers are
designed for digital data transmission over lines
having impedances from 50 to 500 O. They are
also compatible with standard TTL logic and
supply voltage levels.
1 2019
18
17
16
15
14
8
9 10 11 12 13
4
5
6
7
3
2
2E
2D
NC
2C
28
~~~~CS
~
The low-impedance emitter-follower outputs of
the SN55121 and SN75121 will drive terminated
lines such as coaxial cable or twisted pairs.
Having the outputs uncommitted allows wired-OR
logic to be performed in party-line applications.
Output short-circuit protection is provided by an
internal clamping network that turns on when the
output voltage drops below approximately
1.5 V. All of the inputs are in conventional TTL
configuration and the gating can be used during
power-up and power-down sequences to ensure
that no noise is introduced to the line.
The SN55121 is characterized for operation over
the full military temperature range of -55°C to
125°C. The SN75121 is characterized for
operation from O°C to 70°C.
1ExAs
NC-No internal connection
THE SN75121 IS NOT
RECOMMENDED FOR NEW DESIGN
FUNCTION TABLE
A
B
H
X
H
X
INPUTS
C
0
H
X
H
X
OUTPUT
E
F
Y
X
H
X
H
H
H
L
All other input combinations
H = high level
..Jf
L = low level
X = irrelevant
Copyright © 1993, Texas Instruments Incorporated
INSIRlJMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2-241
SN55121, SN75121
DUAL LINE DRIVERS
Su.s074A- 01334, SEPTEMBER 1973 - REVISED FEBRUARY 1993
logic symbol t
1A
1B
1C
10
1E
1F
logic diagram (positive logic)
1
&
2
3
4
--;;-
5
~
2C
2E
2F
7
1Y
1E 5
1F 6
6
10
2A
11
2B
12
20
1A
1B 2
3
1C
10 4
.. 1 t>
9
13
2A ....:1.:,0_ _1-_......
2B ....:1,:..1_--1
2C ....:1::,2_--1
2D ...!1.=,3_---,r---
2Y
14
15
2E ...!1...!,4_-J
t This symbol is in accordance with ANSVIEEE Std 91-1984
and lEe Publication 617-12.
2F ....:1.:;,5_--1
Pin numbers shown are for the 0, J, and N packages.
schematic (each driver)
VCC---~--~--~---~-----~--._--~---._,
To Other
UneOrlver
4kO
150
4kO
A--...-r
B--+--+
C--t--H
0---+--++-+
''-----+---
E---+--+~--------+
F---+--+~------~r+
GNO
---~~~~-------~+-~~+--+-+-~~~+---~
To Other
UneOriver
All resistor values shown are nominal.
1ExAs
2-242
~
INSTRUMENTS
POST OFFICE BOX 655303 • OAUAS, TEXAS 75265
Y
SN55121, SN75121
DUAL LINE DRIVERS
SLLS074A- 01334, SEPTEMBER 1973 - REVISED FEBRUARY 1993
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
SN55121
SN75121
UNIT
Supply voltage, VCC (see Note 1)
6
6
V
Input voltage
6
6
V
Output voltage
6
6
V
See Dissipation Rating Table
Continuous total power dissipation
Operating free-air temperature range
-55 to 125
Ot070
·C
Storage temperature range
-6510150
-65 to 150
·C
300
·C
260
·C
Case temperature for 60 seconds: FK package
260
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: J package
300
·C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: 0 or N package
NOTE 1: All voltage values are With respect to both ground terminals connected together.
DISSIPATION RATING TABLE
PACKAGE
TA:<25·C
POWER RATING
DERATING FACTOR
ABOVE TA = 25·C
TA=70·C
POWER RATING
TA=125·C
POWER RATING
0
950mW
7.6mWrC
608mW
FKt
1375mW
11.0mWrC
880mW
275mW
Jt
1375mW
11.0 mWrC
880mW
275mW
N
1150mW
9.2mWrC
736mW
t In the FK and J packages, SN55121 chips are efther silver glass or alloy mounted.
recommended operating conditions
SN55121
Supply voltage, VCC
NOM
MAX
MIN
NOM
MAX
4.75
5
5.25
4.75
5
5.25
High-level input voltage, VtH
High-level output current, IOH
-55
UNIT
V
V
2
2
Low-level input voltage, VIL
Operating free-air temperature, TA
SN75121
MIN
0.8
0.8
V
-75
-75
mA
70
·C
125
0
1ExAs . "
INSIRUMENlS
POST OFFICE BOX 655303 • DAllAS, TEXAS 75265
2-243
SN55121,SN75121
DUAL LINE DRIVERS
SLLS074A- 01334, SEPTEMBER 1973 - REVISED FEBRUARY 1993
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
V,K
Input clamp voltage
VCC=SV,
1,=-12mA
V(BR)
Breakdown voltage
VCC=SV,
VOH
High-level output voltage
V,H=2V,
" = 10mA
IOH=-7SmA,
10H
High-level output current
VCC=SV,
TA=2SoC,
V,H =4.SV,
See Note 2
VOH=2V,
10L
Low-level output current
V'L=0.8V,
VOL = 0.4 V,
See Note 2
10(0ff)
Off-state output current
VCC=3V,
VO=3V
See Note 2
MAX
UNIT
-1.S
V
S.S
V
2.4
V
-100
-250
rnA
-800
40
!JA
!JA
!JA
-1.6
rnA
-30
rnA
Outputs open
28
rnA
Outputs open
60
rnA
500
IIH
High-level output current
VI =4.SV
'IlL
Low-level output current
VI =0.4V
lOS
Short-circuit output currentt
VCC = S V,
TA = 25°C
ICCH
Supply current, outputs high
VCC=S.2SV,
All inputs at 2 V,
ICCL
Supply current, outputs low
VCC = S.2SV,
All inputs at 0.8 V,
-0.1
t Not more than one output should be shorted at a time.
NOTE 2: The output voltage and current limits are valid for any appropriate combination of high and low inputs specified by the function table for
the desired output.
switching characteristics, VCC = 5 V, TA = 25°C
PARAMETER
TEST CONDITIONS
tpLH
Propagation delay time, low-to-high level output
tpHL
Propagation delay time, high-to-Iow level output
tpLH
Propagation delay time, low-to-high level output
tPHL
Propagation delay time, high-to-Iow level output
MIN
RL=37 C,
CL=1SpF,
See Figure 1
RL=37 C,
CL = 1000 pF,
See Figure 1
TYP
MAX
11
20
8
20
22
50
20
SO
UNIT
ns
ns
PARAMETER MEASUREMENT INFORMATION
3V
,.-__..., ...~r==.....Pulse
Generator
(see Note A)
::+
~1.~
-'I
1 Input
1
VCC
.L -,
,
10%
-+I~I+
~V
.
~I
CL
(see Note B)
1
!
OutPut _ _ _- '
:s:5ns
--1-----
1
tpLH 14
)-;-,.....-----.-OutPut
--r...J
:s:5ns
3V
1
1 ~10%~_ _ OV
1
tpHL-T14+--+t~1
1-1--~
1.5V
VOH
1.5V'L.
VOL
VOLTAGE WAVEFORMS
TEST CIRCUIT
NOTES: A. The pulse generators have the following characteristics:
B. CL includes probe and jig capacitance.
Zo -
50 C, tw = 200 ns, duty cycle", SO%, PRR :s: 500 kHz.
Figure 1. Test Circuit and Voltage Wav~forms
2-244
POST OfFICE BOX 655303 • DALLAS, TEXAS 75265
SN55121, SN75121
DUAL LINE DRIVERS
SLLS074A- 01334, SEPTEMBER 1973 - REVISED FEBRUARY 1993
TYPICAL CHARACTERISTICS
OUTPUT CURRENT vs OUTPUT VOLTAGE
-300
VCC=5V
VIH=2V
TA=25°C -
-250
1 -200
r\.
1
'\
i
:::I
U -150
'\.
!
1\
1 -100
1\
.P
-50
o
\
o
0.5
1 1.5
2 2.5
3 3.5
4 4.5
Vo - Output Voltage - V
5
Figure 2
APPLICATION INFORMATION
1~---------I
1/3 SN55122
1
1
1
1
1
11_ _ _ _ _ _ _ _ _ -'1
~---------t
75-0 Coaxial
75-0 Coaxial Cable
1/3 SN55122
• Cable
r------~CT--------~~~--~~--~ll
1
1
750~
1
1
750
-------~
1----------'1
1
1
1
L.:!!.2..!~.!.2.!.._J
-------~
1
r--------,1
1
I1
1
1
1/3SN55122
~~I--~~----~~H=~-r~--~ll
760
L_!L?,!N.!.5E!.. J1
-::-
-------,
I_ _ _ _ _ _ _ _ _ J
1
1
1
l....:!!!~~1~_J
Figure 3. Single-Ended Party Line Circuits
. 1ExAs..lf
INSIRUMENTS
POST OFFICE BOX 855303 • DAUAS, TEXAS 75265
2-245
2-246
SN75ALS121
DUAL LINE DRIVER
1987 - REVISED AUGUST 1989
•
•
•
•
•
•
•
•
•
•
•
Permits Digital Data Transmission Over
Coaxial Cable, Strip Line, or Twisted Pair
Operates With 50-0 to 500·0 Transmission
Lines
TTL Compatible With SOV Supply
2.4-V Output at IOH = -75 mA
Uncommitted Emitter·Follower Output
Structure for Party·Line Operation
IMPACT'M Low·Power Schottky Technology
Improved Replacement for the SN75121
and Signetics 8T13
Glltchless Power Up/Power Down
Short-CIrcuit Protection
AND·OR Logic Configuration
High Speed ••. Maximum Propagation
Delay Time of 14 ns at CL = 15 pF
description
The SN75ALS121 dual line driver is designed for
digital data transmission over lines having
impedances from 50 to 500 O. It is compatible with
standard TTL logic and supply voltage levels.
o OR N PACKAGE
(TOP VIEW)
Vee
2F
2E
20
2C
26
1F
1Y
GNO
2A
NOT RECOMMENDED FOR NEW DESIGN
FUNCTION TABLE
INPUTS
A
B
C
0
E
F
H
X
H
X
H
X
H
X
X
H
X
H
OUTPUT
y
All other input combinations
H
H
L
H = high level, L = low level. X = Irrelevant
The low-impedance emitter-follower outputs drive terminated lines such as coaxial cable, strip line, or twisted
pair. Having the outputs uncommitted allows wired-OR logic to be performed in party-line applications. Output
short-circuit protection is provided by an internal clamping network that turns on when the output voltage drops
below approximately 1.5 V. All inputs are in conventional TTL configuration. Gating can be used during power-up
and power-down sequences to ensure that no noise is introduced on the line.
The SN75ALS121 employs the IMPACT'" process to achieve fast switching speeds, low power dissipation, and
reduced input current requirements.
The SN75ALS121 is characterized for operation from O°C to 70°C.
IMPACT is a trademark of Texas Instruments Incorporated.
Copyright © 1989, Texas Instruments Incorporated
TEXAS . "
INSIRUMENTS
POST OFFICE BOX 655303 • DALlAS, TEXAS 75265
2-247
SN75ALS121
DUAL LINE DRIVER
SLLS03OA- 01334, SEPTEMBER 1987 - REVISED AUGUST 1989
logic symbol t
1A
logic diagram (positive logic)
1
&
.. 11>
1B 2
3
1C
10
1E
5
1F
6
2A
10
2B
2C
20
2E
2F
~
4
1A
1B
1C
7
10
1Y
1E
&
1F---....-,
11
12
9
13
2A
2B
2C
20
2Y
14
2E
15
2F---...._,
t This symbol is in accordance wHh ANSI/IEEE SId 91-1984 and
lEe Publication 617-12.
schematics of inputs and outputs
EQUIVALENT OF EACH INPUT
TYPICAL OF ALL OUTPUTS
VCC-------~~---
VCC
25kO
Input - - e -....- - - i
YOutput
- --- ----.....--~.--
GNO--e--~~-~~--
ThxAs
.Jf .
INSIRUMENfS
2-248
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
GNO
SN75ALS121
DUAL LINE DRIVER
SLLSOOOA- 01334, SEPTEMBER 1987 - REVISED AUGUST 1989
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) ............................................................. 6 V
Input voltage ............................................................................... 6 V
Output voltage .............................................................................. 6 V
Continuous total dissipation at (or below) 25°C free air temperature ........ See Dissipation Rating Table
Operating free-air temperature range .................................................. O°C to 70°C
Storage temperature range ....................................................... - 65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds ............................... 260°C
NOTE 1: All voltage values are with respect to network ground terminal.
DISSIPATION RATING TABLE
PACKAGE
TA s 25"C
POWER RATING
OPERATING FACTOR
ABOVE TA = 25°C
TA=70°C
POWER RATING
o
950 mW
7.6 mwre
60BmW
N
1150 mW
9.2 mwrC
736mW
recommended operating conditions
Supply voltage, Vec
MIN
NOM
MAX
UNIT
4.75
5
5.25
V
2
High-level input voltage, VIH
V
Low-level Input voltage, Vil
High-level output current, 10H
Operating free-air temperature range, TA
0
O.B
V
-75
mA
70
°e
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
VIK
Input clamp voltage
Vee=5V,
11=-12mA
VIBR) I
Input breakdown voltage
Vce =5V,
11=10mA
VOH
High-level output voltage
VIH=2V,
IOH=-75mA,
See Note 2
High-level output current
Vee =5\1,
TA=25°C,
VIH = 4.5 V,
See Note 2
VOH =2\1,
See Note 2
10H
10l
low-level output current
Vll=O.BV,
VOL = 0.4 V,
10/0ff)
Off-state output current
Vee=3V,
VO=3V
TYpt
MAX
-1.5
5.5
UNIT
V
V
2.4
3.2
-100
-200
V
-250
mA
-800
IIH
High-level input current
VI =4.5V
40
III
lOW-level input current
VI =0.4V
-250
JAA
JAA
JAA
JAA
lOS
Short-circuit output current
Vee=5V
-5
-30
mA
leCH
Supply current, outputs high
Vee = 5.25 V,
All inputs at 2 \I,
No load
9
14
mA
JCCl
Supply current, outputs low
Vee = 5.25 V,
All inputs at 0.8 V.
No load
13
30
mA
500
t All typical values are at Vee = 5 V and TA = 25°e.
NOTE 2: The output voltage and current limits are ensured for any appropriate combination of high and low inputs specified by the function table
for the desired output.
POST OFFICE BOX 655303 • DALlAS, TEXAS 75265
2-249
SN75ALS121
DUAL LINE DRIVER
SLLS03OA-D1334, SEPTEMBER 1987-REVISEDAUGUST1989
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature
PARAMETER
TEST CONDITIONS
tpLH
Propagation delay time, low-to-high-Ievel output
tPHL
Propagation delay time, high-to-Iow-Ievel output
tpLH
Propagation delay time, Iow-to-high-Ievel output
tPHL
Propagation delay time, hlgh-to-Iow-Ievel output
MIN
AL=37 Q,
CL=15pF,
See Figure 1
RL= 37 Q,
CL= 1000pF,
See Figure 1
t All typical values are at VCC = 5 V and TA = 25°C.
PARAMETER MEASUREMENT INFORMATION
3V
VCC
r------L--,
I
I
I
Pulse
Generator
(see Note A)
OUtput
I
RL
L-. _ _ _ _ _ _ _ _ JI
CL
(see Note B)
-=
-=
TEST CIRCUIT
-.!
,
Input
I .,
LI. 90% 90%;\"!
~ 1.5V
tpLH
Output
-.! I+-
~ s5ns
I .
I'..
1.5V
..I
----
i'- 10%
,
,
s5ns
,tpHL,..
3V
OV
c.
..,
--VOH
!1.5V
______-J.
1.SV .
VOL
VOLTAGE WAVEFORMS
NOTES: A. The pulse generator has the following characteristics:
B. CL includes probe and jig capacitance.
Zo = 60 Q, tw = 200 ns, duty cycle = 60%.
Figure 1. Test Circuit and Voltage Waveforms
1ExAs ."
INSIRUMENTS
2-250
POST OFFICE BOX 855303 • DAUAS, TEXAS 75265
TYP
MAX
6
14
UNIT
4
14
ns
ns
18
30
ns
29
50
ns
SN75ALS121
DUAL LINE DRIVER
SLLS03OA- 01334. SEPTEMBER 1987 - REVISED AUGUST 1989
TYPICAL CHARACTERISTICS
OUTPUT CURRENT
vs
OUTPUT VOLTAGE
-300
Vcc =5V
A1llnputa at 2 V
TA=25°C
-250
~
I
~
-200
'"
I
u -1SO
\
i
~ -100
9
1\
-so
o
o
\
2
3
4
5
Vo - Output Vohage - V
Figure 2
TEXAS . "
INSIRUMENfS
POST OFFICE BOX 655303 • DAUAS. TEXAS 75265
2-251
2-252
N8T14,SN55122,SN75122
TRIPLE UNE RECEIVERS
SEPTEMBER 1973-REVISED FEBRUARY 1993
SN55122 ••• JPACKAGE
N8T14, SN75122 ••• D OR N PACKAGE
(TOP VIEW)
• Designed for Digital Data Transmission
Over Coaxial Cable, Strip Line, or Twisted
Pair
• Designed for Operation With 50-0 to 500-0
Transmission Lines
1A
18
2R
28
• TTL Compatible
• Single S-V Supply
Vee
3
2A
• Built-Input Threshold Hysteresis
18
1R
1Y
3A
3S
• High-Speed ••. 'iYplcal Propagation Delay
Time =20ns
• Independent Channel Strobes
SN55122 ••• FK PACKAGE
• Input Gating Increases Application
Flexibility
(TOP VIEW)
00
~~z§tCfJ.
• Fanout to 10 Series 54/74 Standard Loads
• Can Be Used With Dual Line Drivers
SN55121 and SN75121
2R
28
• Interchangeable With Signetics N8T14
NC
2A
28
description
The N8T14, SN55122, and SN75122 are triple
line receivers that are designed for digital data .
transmission over lines having impedances from
50 0 to 500 O. They are also compatible with
standard TTL-logic and supply voltage levels.
4
5
6
7
8
1 2019
18
17
16
15
14
9 10 11 12 13
3 2
1R
1Y
NC
3A
3S
,
>-oo>-a:
C\lZZC')C')
Cl
NC-No internal connection
THE N8T14 AND SN75122 ARE NOT
RECOMMENDED FOR NEW DESIGN
The N8T14, SN55122, and SN75122 have receiver inputs with built-in hysteresis to provide increased noise
margin for single-ended systems. The high impedance of this input presents a minimum load to the driver and
allows termination of the transmission line in its characteristic impedance to minimize line reflection. An open
line will affect the receiver input as would a low-Iavel voltage. The receiver can withstand a level of -0.15 V with
power on or off. The other inputs are in TTL configuration. The S input must be high to enable the receiver input.
Two of the line receivers have A and B inputs ~hat, if both are high, will hold the output low. The third receiver
has only an A input that, if high, will hold the output low.
The SN55122 is characterized for operation over the full military temperature range of -55°C to 125·C. The
N8T14 and SN75122 are characterized for operation from O·C to 70·C.
1ExAs
~
copyright C> 1993. Texas Instruments Incorporated
INSTRUMENTS
POST OFFICE BOX 655303 • DAllAS, TEXAS 75285
2-253
N8T14, SN55122, SN75122
TRIPLE LINE RECEIVERS
Su.s075A- 01334, SEPTEMBER 1973 - REVISED FEBRUARY 1993
logic symbol t
1R
1S
1A
1B
2R
2S
2A
2B
3R
3S
3A
14
16
r-..
1
2
3
4
W&
&
logic diagram
~
='0
~7.,
~
.. 1
1R
13
15
::~
1Y
"
'Ow
2R
7
5
6
2B 6
10
11
12
" ~&
.. 1
9
3R
3S~
3Y
3A 12
tThis symbol Is In accordance with ANSI/IEEE Std 91-1984
and lEe Publication 617-12.
Pin numbars shown are for·the 0, J, and N packages.
FUNCTION TABLE
INPUTS
A
B~
R
H
H
X
L
X
X
X
L
OUTPUT
S
X
H
Y
L
L
H
X
H
L
X
X
L
H
L
X
H
X
H
X
L
X
L
H
:t: B Input and last two lines of the function table are
applicable to receivers 1 and 2 only.
H =high level, L =low level,
X =irrelevant
2-254
INSIRUMENfS
1ExAs "
POST OFFICE BOX 655303 • DAllAS. TEXAS 75Z65
93Y
N8T14, SN55122, SN75122
TRIPLE LINE RECEIVERS
Su.s075A- 01334, SEPTEMBER 1973 - REVISED FEBRUARY 1993
schematic diagram (each receiver)
vcc--~--~--~~----~--~--------4r----------'-~-----------'
580
To Other
Receiver
R-------j
13,7,9 Y
GND-~r+-~~
To Other
Receivers
'W ...
VCCbUB
t B input Is provided on receivers 1 and 2 only.
Resistor values shown are nominal.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) ............................................................. 6 V
Input voltage: R input ..................................................................... 6 V
A, B, or S input ............................................................ S.S V
Output voltage ............................................................................. 6 V
Output current .... '. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. :I: 100 rnA
Continuous total power dissipation (see Note 2) ........ :................ See Dissipation Rating Table
Operating free-air temperature range: SNSS122 .................................. -SS'C to 12S'C
N8T14, SN7S122 ............................... O'C to 70'C
Storage temperature range ....................................................... -6S'C to 1S0'C
Case temperature for 60 seconds: FK package .............................................. 260'C
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: J package ..................... 300·C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: D or N package ................ 260'C
NOTES: 1. VoHage values are with respect to network ground terminal.
2. The SN55122 chips are alloy mounted, and the SN75122 chips are glass mounted.
DISSIPATION RATING TABLE
PACKAGE
TA$25·C
POWER RATING
DERATING FACTOR
ABOVE TA = 25·C
TA=70·C
POWER RATING
TA=125·C
POWER RATING,
D
950mW
7.6mWrC
608mW
FK
1375mW
11.0 mW/"C
880mW
275mW
J
1375mW
11.0 mW/"C
880mW
275mW
N
1150mW
9.2mW/"C
736mW
1ExAs ...,
INSIRUMENIS
POST OFFICE BOX 655303 • DAUAS, TEXAS 75265
2-255
N8T14, SN55122, SN75122
TRIPLE LINE RECEIVERS
SUS075A- 01334. SEPTEMBER 1973 - REVISED FEBRUARY 1993
recommended operating conditions
UIN
-----..
4.75
Supply voltage. VCC
High-level input voltage. VIH
IA. B. R. orS
Low-level Input voltage. VIL
IA.B.R.orS
--- -- I UNIT
-----
NnU
.-----
U.II.Y
5
5.25
V
0.8
V
2
V
High-level output curre!ll. 10H
-500
JAA
Low-level output curre!ll. 10L
16
rnA
Operating free-air temperature. TA
ISN55122
-55
125
JSN75122
0
70
°c
electrical characteristics over recommended operating free-air temperature, Vee = 4.75 Vto
5.25 V (unless otherwise noted)
PARAMETER
TEST CONomONS
Vhvs
Hysteresis (VT+ - Vr"')
R
VCC=5V.
TA=25°C.
VIK
Input clamp voltage
A.~.orS
VCC=5V,
II =-12 rnA
VI (BR)
Input breakdown voltage
A.B.orS
VCC=5V.
11=10mA
VIH =2V.
VIL= 0.8 V,
VOH
High-level output voltage
VOL
Low-level output voltage
IIH
High-level input current
See Figures 2 and 4
VIL=0.8V,
VI(A) = o.
Vi(B) = o.
VI(R) = 1.45 V. 10L = 16mA.
TVPt
0.3
0.6
MAX
V
V
5.5
10H = -500 JAA
UNIT
V
-1.5
VI (A) =0.
VI (B) =0.
VI(S)=2V.
VI(R) = 1.45 V. 10H = -500 I'A. See Note 3
VIH=2V,
MIN
2.6
V
2.6
IOL=16mA
0.4
VI(S) =2V.
See Note 4
0.4
A.B.orS
Vi =4.5V
40
R
VI =3.8V
170
A.B.orS
V
JAA
IlL
Low-level input current
VI = 0.4 V.
VIR = 0.8V
-0.1
-1.6
rnA
10S*
Short-circuit output current
VCC=5V,
TA=25°C
-50
-100
rnA
ICCH
High-level supply current
VCC=MAX.
All inputs at 0.8 V.
72
rnA
>,,'100
rnA
TVP
MAX
UNIT
20
30
20
30
Outputs open
Low-level supply current
Outputs open
ICCL
Vcc = MAX. All inputs at 2 V.
t All typical values are at VCC = 5 V and TA = 25°C.
* Not more than one output should be shorted at a time. and duration of the short circuit should not exceed one second.
NOTES: 3. The receiver input is high immediately before being reduced to 1.45 V.
4. The receiver input is low immediately before being increased to 1.45 V.
switching characteristics, Vee
=5 V, TA =25°C
PARAMETER
TEST CONOInONS
IpLH
Propagation delay time. Iow-to-high-Ievel output from R input
tpHL
Propagation delay time. high-to-Iow-Ievel output from R input
1ExAs'"
See Figure 1
h.T
u~SIRlJMENTS
2-256
POST OFFICE BOX 855303 • DAUAS, TEXAS 75265
MIN
ns
N8T14,SN55122,SN75122
TRIPLE LINE RECEIVERS
SLLS075A- 01334, SEPTEMBER 1973 - REVISED FEBRUARY 1993
PARAMETER MEASUREMENT INFORMATION
-+1
2.6 V
VCC
I
1
akD
CL'"
30pF
I
~I tpLH
1l1li
~...--+--.-~
5 ne
90%11i----2.6V
I
1.5 V
:
10%
1N3064
t*-"
-.I
1
I
Input
Generator
(see Note A)
..s 118
;J(L1.~
84.5D
Pul8e
~
1
1
10%
OV
1
tpHL-III4I111--1.~1
1 ,-_ _ _ _ _"'.J __
".BV
~
TEST CIRCUIT
VOH
\:V
VOL
VOLTAGE WAVEFORMS
NOTES: A. The pulse generator has the following characteristics: Zo = 50 D, tw = 200 ns, duty cycle = 50%, PRR " 500 kHz.
B. CL Includes probe and jig capacitance.
Figure 1. Test Circuit and Voltage Waveforms
TYPICAL CHARACTERISTICS
OUTPUT VOLTAGE
va
INPUT VOLTAGE
4
,
>I
II
~
!i
c..
!i
0
I
I
I
I
VCC=5V
3.5 I- NoLoed.
TA = 25°C
3
2.5
2
VT-
VT+
1.5
~
0.5
o
o
0.4
0.8
1
1.4
1..
2
VI -lnputVoltsge-V
Figure 2
1ExAs.Jf
INSlRlJMENTS
POST OFFICE BOX _
• DAUAS, TEXAS 75265
2-257
N8T14, SN55122, SN75122
TRIPLE LINE RECEIVERS
SLLS075A- 01334, SEPTEMBER 1973 - REVISED FEBRUARY 1993
APPLICATION INFORMATION
r----------I
I
1/3 SN55122
I
I
I
75-0 Collldal
Cable
,..---------,
I
I
1/3 SN56122
I
I
I
I
I1_ _ _ _ _ _ - - _ ....I
r-----~~------_r~~--,=~--~O
?So
--------,
I
.
r---------,
I
I
7S-0 Collldal Cable
I
1/3 SN55122
>-~-4~~----~~~~_r~~--~O
1750
?SO I
I
I
I, , _ _ _ _ _ _ _ _ .JI
~_~~~~~J
Figure 3. Single-Ended Party Line Circuits
VIH
R
Input
VIL
I
L
Output
VOH
VOL
NOTE: The high gain and built-in hysteresis of the SN55122 and
SN75122 line receivers enable them to be used as Schmitt
triggers in squaring pulses.
Figure 4. Pulse Squaring
I
. 1ExAs . "
NSIRUMENTS
2-258
I
I
POST OFFICE BOX 655303 • DAUAS. TEXAs 75265
N8T13,N8T23,SN75123
DUAL LINE DRIVERS
SEPTEMBERI973-R~SEDJANUARY1~
•
Meets IBM System 360 input/Output
interface Specifications
•
•
•
•
Operates From Single 5-V Supply
•
•
•
•
o OR N PACKAGE
(TOP VIEW)
TTL Compatible
3.11-V Output at IOH
Vee
1A
16
1C
10
1E
1F
1Y
=-59.3 mA
Uncommitted Emitter-Follower Output
Structure for Party-Line Operation
2F
2E
20
2C
26
2A
GNO
Short-CIrcuit Protection
AND-OR Logic Configuration
FUNCTION TABLE
Designed for Use With Triple Line Receiver
SN75124
INPUTS
Designed to Be Interchangeable With
Signetics N8T13 and N8T23
OUTPUT
A
B
C
0
E
F
H
X
H
X
H
X
H
X
X
H
X
H
All other input combinations
H high level. L low level. X
=
description
The N8T13. N8T23. and SN75123 are dual line
drivers specifically
designed to meet the
input/output interface specifications for IBM
System 360. It is also compatible with standard
TTL logic and supply voltage levels.
The low-impedance emitter-follower outputs of
the N8T13, N8T23, and SN75123 will drive
terminated lines such as coaxial cable or twisted
pair. Having the outputs uncommitted allows
wired-OR logic to be performed in party-line
applications. Output short-circuit protection is
provided by an internal clamping network that
turns on when the output voltage drops belOW
approximately 1.5 V. All the inputs are in
conventional TTL configuration and the gating can
be used during power-up and power-down
sequences to ensure that no noise is introduced to
the line.
=
Y
H
H
L
=Irrelevant
logic symbol t
1A
1B 2
1C 3
10 4
1E
"
.. 1 t>
7 1y
Ji5~J--:,,:--I
1F 6
2A 10
2B
2C
20
2E
2F
tThis symbol is in accordance with ANSI/IEEE Std 91·1984 and
lEe Publication 617-12.
logic diagram (positive logic)
A_-+_. . .
B
C
The N8T13,
N8T23, and SN75123 are
characterized for operation from O°C to 70°C.
0--+-"
Y
E
F
Copyright © 1993. Texas Instruments Incorporated
TEXAS
,If
INSIRUME~
POST OFFICE BOX 655303 • DALlAS. TEXAS 75265
2-259
N8T13, N8T23, SN75123
DUAL LINE DRIVERS
Su.s086A- 01322, SEPTEMBER 1973 - REVISED JANUARY 1993
schematic (each driver)
vee __i~6-4r-____~____~____~__________~__~____~______~-'
To Other
Line Driver
A
B
e
D
E
F
GND
4kg
4kn
16g
360g
1,10
2, 11
3,12
4,13
6,14
6,16
,~__--t__+-,7:.!.'.;:;.9_
Y
8
To Other
Line Driver
Resistor values shown are nominal.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) ............................................................. 7 V
Input voltage, VI .............................................................. ,.......... 5.5 V
Output voltage, Vo ....................................................... I • • • • • • • • • • • • • • • •• 7 V
Continuous total dissipation at (or below) 25°C free-air temperature (see Note 2): 0 package .... 950 mW
N package ... 1150 mW
Operating free-air temperature range ..................................................
to 70°C
Storage temperature range ....................................................... - 65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds ............................... 260°C
oot
NOTES: 1. All voKage values, except differential input voKage, are with respect to network ground terminal.
2. For operation above 25·0 free-air temperature, derate the 0 package to 608 mW at 70·e at the rate of7.6 mwre and the N package
to 736 mW at 70·e at the rate of 9.2 mwro.
.
recommended operating conditions
Supply voltage, Vee
High-level input voHage, VIH
MIN
NOM
MAX
UNIT
4.75
5
5.25
V
2
Low-level input voltage, ¥IL
High-level output current, IOH
Operating free-air temperature, TA
0
1ExAs ."
INSIRUMENTS
2-260
V
0.8
POST OFFICE BOX 655303 • DAUAS. TEXAS 75265
¥
-100
mA
70
·0
N8T13,N8T23,SN75123
DUAL LINE DRIVERS
SLLS086A- 01322. SEPTEMBER 1973 - REVISED JANUARY 1993
Vee =4.75 V to 5.25 V, TA =ooe to 70°C (unless otherwise noted)
electrical characteristics,
TEST CONDITIONS
PARAMETER
MIN
VIK
Input clamp voltage
VCC =5\1,
11=-12mA
V(BR)
I
Input breakdown voltage
VCC =5\1,
11=10mA
VOH
High-level output voltage
VCC=5V.
10H = - 59.3 rnA.
VIH=2V.
See Note 3
VOL
low-level output voltage
VIL=0.8V.
10L = -240 !lA,
See Note 3
High-level output current
VCC =5\1,
TA=25°C,
VIH=4.5V,
See Note 3
VOH=2V,
10eoff)
Off-state output current
VCC =0,
VO=3V
IIH
High-level input current
VI =4.5V
IlL
Low-level input current
VI =0.4V
lOS
Short-circuit output currentt
Vee =5\1,
TA=25°C
ICCH
Supply current, outputs high
VCC = 5.25 V,
All Inputs at 2 V,
ICCL
Supply current, outputs low
VCC = 5.25 V,
All Inputs at 0.8 V,
10H
MAX
UNIT
-1.5
V
5.5
V
3.11
ITA=25°C
V
2.9
ITA = O°C to 70°C
0.15
V
-250
rnA
40
40
!IA
!IA
-1.6
rnA
-30
rnA
Outputs open
28
rnA
Outputs open
60
rnA
-100
-0.1
t Not more than one output should be shorted at a time.
NOTE 3: The output voltage and current limits are valid for any appropriate combination of high and low inputs specified by the function table for
the desired output.
switching characteristics,
Vee = 5 V, TA = 25°C
PARAMETER
TEST CONDITIONS
tpLH
Propagation delay time, low-to-high-Ievel output
tpHL
Propagation delay time, hlgh-to-Iow-Ievel output
tpLH
Propagation delay time, low-to-hlgh-Ievel output
tPHL
Propagation delay time, high-to-Iow-Ievel output
MIN
RL=50Q,
CL= 15 pF.
See Figure 1
RL=50Q,
CL= 100 pF,
See Figure 1
TYP
MAX
12
20
12
20
20
35
15
25
UNIT
ns
ns
PARAMETER MEASUREMENT INFORMATION
3V
---.f
,...-_ _.., ...-1-.....
__
- _-
,
..L -,
Pulse
Generator
(see Note A)
ns
1
tpLH
) - ; ; , . . - - - - - . - Output
- -r
10- ,. 5
10- ,. 5 ns
-tI
' ' 1~
' ' i ~~ ~v\r----
VCC
..J '-------.
-
CL
(see Note B)
01
,.
,
3V
OV
,
II"'"'--<~ot-
tpHL
~r~-'5-V----1-'5~V~---
VOH
Output
_ _ _..oJ.
TEST CIRCUIT
NOTES: A. The pulse generator has the following characteristics:
B. CL Includes probe and jig capacitance.
, _ 10%
'
" - - - VOL
VOLTAGE WAVEFORMS
Zo = 50 Q; tw = 200 ns. duty cycle = 50%.
Figure 1. Test Circuit and Voltage Waveforms
..If
1ExAs
INSIRUMENTS
POST OFACE BOX 655303 • DAUAS. TEXAS 75265
2-261
N8T13,N8T23,SN75123
DUAL LINE DRIVERS .
SLLS088A- D1322, SEPTEMBER 1973 - REVISED JANUARY 1993
TYPicAL CHARACTERISTICSOUTPUT CURRENT
VB
OUTPUT VOLTAGE
-300
VCC=5V
All Inputs at 2 V
!- TA = 25°C
~
I
-200
o
-1SO
I
-100
I
J
,
"\.
9
-so
o
~
1\
,
o
234
5
Vo - Output Voltage - V
Figure 2
APPLICATION INFORMATION
A---..-I---I-.....
8--;--1
c~;:J==l.~
D
r------1
>-~~-~,~-Q-~--a-lc-m_Tle~-~~~laIT
E -........- I
F
-+--t._.J
J
~----
95Q
95Q
1/2 '13, '23
1
Strobe
A
1
~ __ -2/~7~J
Figure 3. Unbalanced Une Communication Using '13, '23, and '124
1ExAs ."
INSIRUMENTS
2-262
I.
POST OFFICE BOX 8S5303 • DALLAS, TEXAEl75265
y
SN75ALS123
DUAL LINE DRIVER
SLLS031B-
•
•
•
•
•
•
•
•
•
•
•
SEPTEMBER 1987 - REVISED FEBRUARY 1993
DPACKAGE
(TOP VIEW)
Meets IBM 360 Input Interface
Specifications
Permits Digital Data Transmission Over
Coaxial Cable, Strip Line, or Twisted Pair
TTL Compatible With SOV Supply
3.11-V Output at IOH = - 59.3 rnA
Uncommitted Emitter-Follower Output
Structure for Party-Line Operation
IMPACT™ Low-Power Schottky Technology
Improved Replacement for the SN75123
and Signetics 8T13
Glltchless Power-Up/Power-Down
Protection
16
VCC
1B
1C
15
2F
2E
10
13
14
11
20
2C
2B
1Y
10
2A
GNO
9
2Y
12
NOT RECOMMENDED FOR NEW DESIGN
Short-CIrcuit Protection
AND-OR Logic Configuration
High Speed .•• Maximum Propagation
Delay Time of 14 ns at CL =15 pF
FUNCTION TABLE
OUTPUT
INPUTS
description
A
B
C
D
E
F
Y
H
H
H
H
X
X
H
H
H
X
X
X
H
All other input combinations
X
The SN75ALS123 dual line driver is specifically
designed to meet the input interface specifications
for the IBM System 360. It is compatible with
standard TTL logic and supply voltage levels. The
low-impedance, emitter-follower outputs drive
terminated lines such as coaxial cable, strip line,
or twisted pair. The uncommitted output allows
wired-OR logic to be performed in party-line
applications. Output short-circuit protection is
provided by an internal clamping network that
turns on when the output voltage drops below
approximately 1.5 V. All inputs are in conventional
TTL configuration. Gating can be used during
power-up and power-down sequences to ensure
that no noise is introduced on the line.
The SN75ALS123 employs the IMPACTTM
process to achieve fast switching speeds, low
power dissipation, and reduced input current
requirements.
The SN75ALS123 is characterized for operation
from O'C to 70·C.
H
=high level
I
L
=low level
X
L
=irrelevant
logic symbolt
1A
1
1B
2
1C
1D
1E
1F
2A
2B
2C
2D
2E
2F
&
.. 11>
3
~
4
5
7
1Y
&
6
10
11
12
9
13
14
15
tThis symbol is in accordance with ANSI/IEEE Std 91-1964 and
IEC Publication 617-12.
logic diagram, each driver (positive logic)
A
B
C
D
Y
E
F--'L_'
IMPACT is a trademark of Texas Instruments Incorporated.
Copyright@ 1993. Texas Instrumenls Incorporated
.1ExAs ,.,
INSIRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
2-263
SN75ALS123
DUAL LINE DRIVER
SLLS031 B - 01332, SEPTEMBER 1987 - REVISED FEBRUARY 1993
schematics of inputs and outputs
EQUIVALENT OF EACH INPUT
TYPICAL OF ALL OUTPUTS
VCC--------------~~----
VCC
25kn
YOutput
Input - - _ . - -....------/
GND--__----~~--~~----
-- -
.....-
-----~...--
GND
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) ............................................................. 7 V
Input voltage ............................................................................. 5.5 V
Output voltage .............................................................................. 6 V
Continuous total dissipation at (or below) 25°C free air temperature (see Note 2) ............... 950 mW
Operating free-air temperature range .................................................. O°C to 70°C
Storage temperature range ....................................................... - 65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds ............................... 260°C
NOTES: 1. All voltage values are with respect to network ground terminal.
2. For operation above 25·C free-air temperature, derate to 608 mW at 70,oC at the rate of 7.6 mW/"C.
recommended operating conditions
Supply voltage, Vee
High-level input voltage, VIH
MIN
NOM
MAX
UNIT
4.75
5
5.25
V
2
Low-level input voltage, VIL
High-level output current, IOH
Operating free-air temperature range, TA
0
1ExAs ",
INSIRUMENTS
2~64
V
0.8
POST OFFICE BOX 655303 • DAUAS. TEXAS 75265
V
-100
rnA
70
·C
SN75ALS123
DUAL LINE DRIVER
SlLS031B - 01332, SEPTEMBER 1987 - REVISED FEBRUARY 1993
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
PARAMETER
MIN
TEST CONDITIONS
VIK
Input clamp voltage
VCC=5V,
II =-12mA
V(BR)I
Inpul breakdown voltage
VCC=5V,
11=10mA
VCC =5\1,
See Note 3
VIH =2V,
10H = - 59.3 mA,
VCC=5V,
TA = 25°C,
VIH=2V,
See Note 3
10H = - 59.3 mA,
VOH
High-level output voltage
TYpt
MAX
UNIT
-1.5
V
5.5
VOL
Low-level output voltage
VIL=0.8V,
10L = -240 i'A,
See Note 3
10H
High-level output current
VCC = 5\1,
TA=25°C,
VIH=4.5V,
See Note 3
VOH=2V,
10loff)
Off-state output current
VCC=O,
VO=3V
IIH
High-level Input current
VI =4.5V
V
2.9
V
3.11
3.3
-100
-200
0.15
mA
40
i'A
i'A
i'A
40
IlL
Low-level Input current
VI =0.4V
lOS
Short-circuit output current
VCC=5V
ICCH
Supply current, outputs high
VCC = 5.25 V,
All inputs at 2 V,
No load
ICCL
Supply currenl, outputs low
VCC = 5.25 V,
All inputs at 0.8 \I,
No load
V
-250
-250
-5
-30
mA
9
14
mA
13
30
mA
..
NOTE 3: The output voltage and current hmlts are ensured for any appropriate combination of high and low inPuts specified by the funclion table
for the desired output.
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature
PARAMETER
TEST CONDITIONS
tpLH
Propagation delay time, low-to-high-Ievel output
tpHL
Propagation delay time, high-to-Iow-Ievel output
tpLH
Propagation delay time, low-to-high-Ievel output
tpHL
Propagation delay time, high-to-Iow-Ievel output
RL=50Q,
RL=50Q,
MIN
TYpt
MAX
4
14
5
14
ns
8
20
ns
8
20
ns
See Figure 1
CL= 15pF,
See Figure 1
CL= 100pF,
UNIT
ns
t All typical values are at VCC = 5 V and TA = 25°C.
PARAMETER MEASUREMENT INFORMATION
3V
Pulse
Generator
(aeeNoteA)
VCC
r------L -.I
I
I
>;I~--~--- O~p~
I RL
CL
(sae Note B)
I _ _ _ _ _ _ _ _ JI
-+I I+- 5Sn. -+I
I I
I
np~J 90%
10%
tpLH
O~p~
I'..
1.SV
~I,tpHL
1
I
_ _ _.....I.
TEST CIRCUIT
90%~'
1.SV
,
~ 5Sn.
,
1.sv
,
,
-----
3V
10%
....:.:.::::-_ _ 0 V
~._
,..
C-_
~,
1.SV
.
VOH
VOL
VOLTAGE WAVEFORMS
Figure 1. Test Circuit and Voltage Waveforms
The pulse generator has the following characteristics: Zo = 50 C, tw = 200 ns, duty cycle = 50%.
NOTES: A.
B. CL includes probe and jig capacitance.
1ExAs ."
INSIRUMENTS
POST OFFICE BOX 655303 • DALlAS, TEXAS 75265
2-265
SN75ALS123
DUAL LINE DRIVER
SLLS031 B - 01332, SEPTEMBER 1987 - REVISED FEBRUARY 1993
TYPICAl,. CHARACTERISTICS
OUTPUT CURRENT
vs
OUTPUT VOLTAGE
-300
Vee =5V
Allinput8 at 2 V
-250 TA=25°e
1
i
-200
(J
-150
I
~
'~
~.
\
i
~ -100
9
-50
o
o
\
234
Vo - Output Voltage - V
Figure 2
1ExAs
2-266
~
INSIRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
SN75124
TRIPLE LINE RECEIVER
-R~SEDJANUARY1~
•
Meets IBM System 360 Input/Output
Interface Specifications
•
Operates From Single 5-V Supply
•
TTL Compatible
•
•
Built-In Input Threshold Hysteresis
•
•
D OR N PACKAGE
(TOP VIEW)
2A
High Speed ••• Typical Propagation Delay
Time =20ns
28
2Y
GND
Independent Channel Strobes
16
15
14
13
12
11
10
Vee
18
1R
1Y
3A
38
3R
9 3Y
Input Gating Increases Application
Flexibility
•
Designed for Use With Dual Une Driver
SN75123
•
Designed to Be Interchangeable With
Signetics N8T24
description
The SN75124 triple line receiver is specifically designed to meet the input/output interface specifications for IBM
System 360. It is also compatible with standard TTL logic and supply voltage levels.
The SN75124 has receiver inputs with built-in hysteresis to provide increased noise margin for single-ended
systems. An open line will affect the receiver input as would a low-level input voltage and the receiver input can
withstand a level of -0.15 V with power on or off. The other inputs are in TTL configuration. The S input must
be high to enable the receiver input. Two ofthe .line receivers have A and B inputs that. if both are high. will hold
the output low. The third receiver has only an A input that. if high. will hold the output low.
The SN75124 is characterized for operation from O°C to 70°C.
FUNCTION TABLE
INPUTS
OUTPUT
A
Bt
R
s
y
H
H
X
X
L
X
X
X
X
L
H
L
H
X
H
X
L
H
L
H
X
H
L
L
X
X
L
X
L
H
t B Input and last two lines of the function table are
applicable to receivers 1 and 2 only.
TEXAS
..If
INSTRUMENTS
POST OFFICE BOX 655303 • DALlAS. TEXAS 75265
Copyright © 1993. Texas Instruments Incorporated
2-267
SN75124
TRIPLE LINE RECEIVER
SUS068A- 01322. SEPTEMBER 1973 - REVISED JANUARY 1993
logic symbol t
1R
1S
1A
18
2R
2S
2A
2B
3R
3S
3A
14
15
" .::.1&
2
4
Id
1R
13
&
1
3
logic diagram
~
15
~:~131Y
1Y
18
'"
7
5
6
10
11
" .::1&
a1
3R
9
3S
12
~
11
9 3y
3A 12
t This symbol is in accordance with ANSI/lEEE SId 91-1984
and IEC Publication 617-12.
schematic (each receiver)
To Other
Receivers
4kQ
8000
580
R 14310,
13,7,9 Y
GND -=8'---9-+_--41>---+
To Other
Receivers
W ...
A 1512
s:j:g&_--
VCCbua
:I: B input is provided on receivers 1 and 2 only.
Resistor values shown are nominal.
1ExAs ."
INSIRUMENTS
2-268
POST OFFICE eox 655303 • DALlAS. TEXAS 7S265
SN75124
TRIPLE LINE RECEIVER
SU-S058A- 01322, SEPTEMBER 1973 - REVISED JANUARY 1993
absolute maximum ratings over operating free.air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) , ............................................................ 7 V
Input voltage, W R input with Vee applied ................................................... 7 V
R input with Vee not applied ................................................ 6 V
A, B, or S input ......................................................... 5.5 V
Output voltage, Vo ......................................................................... 7 V
Output current, 10 ..................................................................... :t 100 mA
Continuous total dissipation ........................................... See Dissipation Rating Table
Operating free-air temperature range .................................................. o·e to 70·C
Storage temperature range ....................................................... -65·C to 150·e
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds ............................... 260·C
NOTE 1: Voltage values are with respect to network ground terminal.
DISSIPATION RATING TABLE
PACKAGE
TA s 25°C
POWER RATING
DERATING FACTOR
ABOVE TA 25°C
=
TA • 7O"C
POWER RATING
o
950 mW
7.6 mWre
608 mW
N
1150mW
9.2mWre
736MW
recommended operating conditions
Supply voltage, Vee
High-level input voHage, VIH
Low-level input voHage, VIL
A, B, orS
R
MIN
NOM
MAX
UNIT
4.75
5
5.25
V
2
1
V
1.7
A, B, orS
O.B
R
0.7
High-level output current, IOH
Low-level output current, IOL
Operating free-air temperature, TA
0
lExAs..Jf
INSIRUMENTS
POST OFFICE BOX 655303 • DAUAS, TEXAS 75265
V
-BOO
!lA
16
rnA
70
°C
2-269
SN75124
TRIPLE LINE RECEIVER
SlLS058A- 01322, SEPTEMBER 1973 - REVISED JANUARY 1993
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TVP
0.2
0.5
MAX
UNIT
Vhys
Hysteresis (\IT + - VT ...}
R
VCC=5V,
TA=25°C
VIK
Input clamp voltage
A,B,orS
VCC=5V,
11-12mA
V(BRII
Input breakdown voltage
A,B,orS
VCC=5V,
11=10mA
5.5
V
VOH
High-level output voltage
VIH= VIHmln,
IOH = -BOO 1lA,
VIL = VI Lmax,
See Note 2
2.6
V
VOL
Lew-level output voltage
VIH = VIHmin,
IOL=16mA,
VII. = VILmax,
See Note 2
II
Input current at maximum Input voltage
IIH
High-level input current
IlL
Lew-level Input current
lOS
Short-circuit output currentt
ICC
r
0.4
5
VI=7V
R
V
-1.5
VI=6V,
5
VCC=O
A,B,orS
VI =4.5V
40
R
VI=3.11V
170
A, B,orS
VI = 0.4 V,
VIR = 0.8 V
V
rnA
IlA
-0.1
-1.6
rnA
-50
-100
rnA
All inputs = 0.8 V
Supply current
V
72
All inputs = 2 V
100
rnA
t Not more than one output should be shorted at a time, and duration of the short circuit should not exceed one second.
NOTE 2: The output voltage and current limits are characterized for any appropriate combination of high and IQw inputs specified by the function
table for the desired output.
switching characteristics, Vee
=5 V, TA =25°C
TES~ CONDITIONS
PARAMETER
tpLH
Propagation delay time, low-to-high-Ievel output from R input
tPHL
Propagation delay time, high-to-Iow-Ievel output from R input
See Figure 1
1ExAs . "
2-270
INSIRUMENIS
POST OFFICE BOX 655303 • DAllAS, TEXAS 75265
MIN
TYP
MAX
20
30
20
30
UNIT
ns
SN75124
TRIPLE LINE RECEIVER
01322. SEPTEMBER 1973-REVISEO SEPTEMBER 1989
PARAMETER MEASUREMENT INFORMATION
---I
2.6 V
VCC
Input
~.....~_..-
:
10%
1N3064
Pulse
-.I
;Jr
84.50
Generator
(sesNoteA)
14- " 5 n8
j+-" 5 n8
l 1j,-----9O%-;{1..11- - - - 2.6 V
1.::
__
~;;""
I
I
I
III
Output
1.5V
I
I
-II
I
tpLH
f~v
OV
I
11 _~_I
tpHL-iII4-
.
TEST CIRCUIT
10%
t~:OH
\:VOL
VOLTAGE WAVEFORMS
NOTES: A. The pulse generator has the following characteristics: Zo - 50 O. PRR '" 5 MHz. duty cycle = 50%.
B. Cl includes probe and jig capacttance.
Figure 1. Test Circuit and Voltage Waveforms
TYPICAL CHARACTERISTICS
OUTPUT VOLTAGE
vs
RECEIVER INPUT VOLTAGE
4
VCC=5V
No Load
TA=25°C
3.5
,
>
3
I
•
2.5
~
!i
2
!0
I
VT-
VT+
1.5
?
0.5
o
o
0.2 0.4 0.6 0.8
1 1.2
1.4 1.6 1.8
2
VI-Input Voltage - V
Figure 2
POST OFFICE BOX 655303 • DAlLAS, TEXAS 75265
2-271
SN75124
TRIPLE LINE RECEIVER
SLl.S058A- 01322. SEPTEMBER 1973 - REVISED JANUARY 1993
APPLICATION INFORMATION
r---~~====I
A
B-'-+---I
I
I
c-..r......----.
iI
E-t---f
F
r-----------,I
~I~~~~--------~._~~~I~rr
D
--+I--L~
1I2SN75123 JI·
L ___ _____
95g
96g
~
I
I
I A
I
L:_____~~..!~~j
Figure 3. Unbalanced Line Communication Using SN75123 and SN75124
1ExAs ."
INSIRUMENIS
2-272
I
I
II
POST OFFICE BOX
-00 • DALU\S, TEXAS 75265
y
SN75125, SN75127
SEVEN·CHANNEL LINE RECEIVERS
1977 - REVISED FEBRUARY 1993
SN75125 ••• 0 OR N PACKAGE
•
•
•
•
•
•
•
Meets IBM 360/370 I/O Specification
Input Resistance •.. 7 kQ to 20 kQ
Output Compatible With TTL
Schottky-Clamped Transistors
Operates From Single S-V Supply
High Speed ••• Low Propagation Delay
Ratio Specification for Propagatlol1 Delay
Time, Low-to-HlghIHlgh-to-Low
• Seven Channels In One 16·Pln Package
• Standard Vcc and Ground Positioning on
SN75127
(TOP VIEW)
1A
1Y
2A
Vce
3Y
4Y
5Y
6Y
5A
6A
7A
7Y
2Y
GND
SN75127 ••• 0 OR N PACKAGE
(TOP VIEW)
description
The SN75125 and SN75127 are monolithic
seven-channel line receivers designed to satisfy
the requirements of the IBM System 360/370
input/output interface specifications. Special
low-power design and Schottky-clamped
transistors allow for low supply-current
requirements while maintaining fast switching
speeds and high-current TTL outputs.
The SN75125 and SN75127 are characterized for
operation from O·C to 70·C.
Vee
11
7A
10
1Y
2Y
3Y
4Y
5Y
6Y
9 7Y
GND
THE SN75125IS NOT
RECOMMENDED FOR NEW DESIGN
logic symbols t
SN75125
t>
1A
2A
3A
4A
SA
6A
7A
SN75127
16 1Y
1A 1
t>
15 1Y
2
9 2Y
2A2
14 2Y
3
14 3Y
4
13 4Y
12 4Y
5
12 5Y
3A 3
4A4
5
6
11 6Y
6A
6
10 6Y
7
10 7Y
7A
7
97Y
SA
13 3Y
11 5Y
t These symbols are in accordance wRh ANSVIEEE SId 91-1984 and lEe Publication 617-12.
I
1ExAs ~
INSIRI.JMENTS
POST OFFICE BOX 655303 • DAUAS, TEXAS 75265
Copyright © 1993, Texas Instruments Incorporated
2-273
SN75125, SN75127
SEVEN·CHANNEL LINE RECEIVERS
Sl.LS108A.., D238, JANUARY 1977 - REVISED FEBRUARY 1993
-
schematic (each receiver)
_........ ....,.-.. _... ,
------------'-a
,.__
. . ,...._.11...
"
VCC------~~~----------~~--------~----~--~_.--~~--~~~To~hw
Channels
1500
NOM
y
Output
12kO
NOM
GND~~----~----_+~----------~~--~----_+_r~~--~~----~~--.
~
________________________~__------------~_+--+To~w
Channels
L-o _ _ _ _ _ _ _ _ _ _ ..
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage. Vee (see Note 1) ............................................................. 7 V
Input voltage range: SN75125 .................................................... - 0.15 Vto 7V
SN75127 ....................................................... -2Vto7V
Continuous total power dissipation ..................................... See Dissipation Rating Table
Operating free-air temperature range .................................................. O°C to 70°C
Storage temperatllre range ....................................................... - 65°C to 150°C
Lead temperature 1.6 mm (1/16 inch) from case for 10 seconds ............................... 260°C
NOTES: 1. All voltage values are with respect to network ground terminal.
DISSIPATION RATING TABLE
PACKAGE
o
N
TA" 25°C
POWER RATING
950 mW
1050 mW
OPERATING FACTOR
ABOVE TA 25°C
7.6 mwrc
9.2 mwrc
=
1ExAs ."
INSIRUMENTS
2-274
POST OFFICE
sox 655303 •
DAUAS. TEXAS 75265
=
TA 70°C
POWER RATING
608 mW
736 mW
SN75125, SN75127
SEVEN·CHANNEL LINE RECEIVERS
SLLS108A- 0239. JANUARY 1977 - REVISED FEBRUARY 1993
recommended operating conditions
MIN
NOM
MAX
Supply voltage. Vee
4.5
5
5.5
V
High-level input voltage. VIH
1.7
0.7
V
V
Low-Iavel input voltage. VIL
High-Iavel output current. IOH
Low-Iavel output current. 10L
0
Operating free-alr temperature. TA
UNIT
-0.4
rnA
16
rnA
70
·e
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYpt
2.4
3.1
MAX
UNIT
VOH
High-level output voltage
Vee =4.5\1,
VIL=0.7\1,
10H =-0.4 rnA
VOL
Low-Iavel output voltage
Vee =4.5\1,
VIH = 1.7\1,
10L= 16 rnA
IIH
High-level input current
Vee =5.5\1,
VI=3.11V
IlL
Low-Ievel input current
Vee =5.5\1,
VI=0.15V
lOS
Short-circuit output current;
Vee = 5.5V.
Vo=O
~
Input resistance
Vee = 4.5 V. 0 V. or open.
AVI =0.15Vto4.15V
20
kg
Vee =5.5\1,
10H = -0.4 rnA.
All Inputs at 0.7 V
15
25
rnA
Vee = 5.5V.
10L= 16 rnA.
All Inputs at 4 V
28
47
rnA
ICC
Supply current
V
0.4
0.5
0.3
0.42
-18
7
V
rnA
30
!IA
-60
rnA
t All typical values are at Vee = 5 \I, TA = 25·e.
; Not more than one output should be shorted at a time.
switching characteristics, Vee = 5 V, TA = 25°C
MIN
TYP
MAX
tpLH
Propagation delay time. low-to-high-Ievel output
7
14
25
ns
tpHL
Propagation delay time. hlgh-to-Iow-Ievel output
10
18
30
ns
!f!.!::!
Ratio of propagation delay times
0.5
0.8
1.3
PARAMETER
tPHL
TEST CONDITIONS
RL = 400 g. eL = 50 pF.
See Figure 1
UNIT
trLH
Transition time. low-to-high-Ieveloutput
1
7
12
ns
trHL
Transition time. hlgh-to-Iow-Ievel output
1
3
12
ns
1ExAs ."
INSIRUMENTS
POST OFFICE BOX 655303 • DAllAS, TEXAS 75265
2-275
SN75125,SN75127
SEVEN-CHANNEL LINE RECEIVERS
SLLS1 OBA- 0239, JANUARY 1'iT17.., REVISED FEBRUARY 1993
PARAMETER MEASUREMENT INFORMATION
Vee
RL=400g
(see Note C)
Pulse
Generator
(see Note A)
CL=50pF
(S" Note B)
TEST CIRCUIT
I"
100ns
-i : ~ 10ns
Input
! ~.;o:
10%.0" u,
--.....;.~
to!
10ns - , :
~~T------------3V
v
I
I
I
I
---+I,
N,10%
I
I
~~:L~1
Output
j4-
---------OV
lilr"2--V~-----
I--tPLH
UV
1.2 V
~_O;;.;.8;;.V~_ _ _ _ _...;;;O';;;.8..;.V.:l!
I.-tTHL
I
- - 'I
I
'
.1. __ - - - - - - VOL
t..-tTLH
I
VOLTAGE WAVEFORMS
NOTES: A. The pulse generator has the following characteristics: Zo - 50 g, PRR '" 5 MHz.
B. CL Includes probe and jig capacitance.
C. All diodes are 1N3064 or equivalent.
Figure 1. Tests Circuit and Voltage Waveforms
1ExAs
2-276
~
INSIRUMENTS
POST OFFICE BOX 655303 • DAUAS, TEXAS 75265
VOH
SN75125, SN75127
SEVEN·CHANNEL LINE RECEIVERS
SUS108A- 0239. JANUARY 1977.,. REVISED FEBRUARY 1993
TYPICAL CHARACTERISTICS
VOLTAGE TRANSFER CHARACTERISTICS
VOLTAGE TRANSFER CHARACTERISTICS
5
5
VCC=5V
4
4
>
VCC=4.5V
>
;
3
o
2
I
I
i
Vec =5.5V
TA=70·C
,/
•
I I
3
i
f---
TA=O·C -
I
f
r-
TA=25·C
2
I
~
~
No Load
TA=25OC
j
I
VCC=5V
o
'OLjd
o
0.2 0.4
0.6 0.8 1 1.2 1.4 1.6 1.8
VI -Input Voltage - V
o
2
o
0.2 0.4
0.6 0.8 1. 1.2 1.4 1.6
VI - Input Voltage - V
Figure 2
c(
I
I
0
va
INPUT VOLTAGE
OUTPUT CURRENT
I
E
0.2
'S
Q.
05
10.1
o
/
o
/
LOW-LEVEL OUTPUT VOLTAGE
va
0.6
~
VCC=5V
NoLoed
0.3 _ TA=25·C
2
Figure 3
INPUT CURRENT
0.4
1.8
V
/
~
t
/
~
0.4
i
0.3
11
I
Vce=5V
0.5 f-- VI=5V
TA=25·C
~
/ ' ""
~
~
~
~
0.2
I
...I
~
0.1
o
2
3
VI -Input Voltage - V
4
5
o
Figure 4
15
5
10
10 - Output Current - mA
20
FigureS
1ExAs . "
INSTRUMENTS
POST OFFICE BOX 655303 • DAllAS, TEXAS 75266
2-277
SN75125, SN75127
SEVEN-CHANNEL LINE RECEIVERS
SLLS108A- 0239. JANUARY 1977 - REVISED FEBRUARY 1993
TYPICAL CHARACTERISTICS.
SUPPLY CURRENT
va
SUPPLY VOLTAGE
30
~II
,/
All Seven Channels
I
2S I- NoLoad
TA=2S°C
I
~
I
1:
20
A1llnputa-
~
at4V
::s
U
>-
15
III
I
10
~
U
9
o
o
V/ k"
I~
I::s
5
r--
V
Allinputa
at 0.7 V
L/V
2
3
4
5
VCC - Supply Voltage - V
Figure 6
.1ExAs,lf
INSIRUMENTS
2-278.
POST OFFICE BOX 655303 • DAllAS, TEXAS 75265
6
SN75126
QUADRUPLE LINE DRIVER
SLLS06OA-
•
Meets IBM 360/370 I/O Interface
Specification GA22-6974-3 (Also See
SN55ALS126 and SN75ALS126)
•
Minimum Output Voltage of 3.11 Vat
IOH = -59.3 mA
•
Fault-Flag Circuit Output Signals Driver
Output Fault
•
Fault-Detection Current-Limit Circuit
Minimizes Power Dissipation During a
Fault Condition
•
Dual Common Enable
•
•
Individual Fault Flags
FEBRUARY 1990- REVISED FEBRUARY 1993
o OR N PACKAGE
(TOP VIEW)
1Y I 1 U 16
15
1F I 2
14
1A I. 3
13
1,2G 4
12
2A I 5
11
2F 6
10
2Y 7
9
GND 8
Vee
4Y
4F
4A
3,4G
3A
3F
3Y
FUNCTION TABLE
INPUTS
G
Designed to Replace the MC3481
A
OUTPUTS
Y F
L
H
L
X
H
H
H
H
5
L
H
H
H = high level,
L =low level,
X = irrelevant,
5 shorted to ground
description
The SN75126 quadruple line driver is designed to
meet the IBM 360/370 I/O specification
=
A22-6974-3. The output voltage is 3.11 V
minimum (at IOH = -59.3 mA) over the recommended ranges of supply voltage (4.5 V to 5.95 V) and
temperature. Driver outputs use a fault-detection current-limit circuit to allow high drive current but still minimize
power dissipation when the output is shorted to ground. The SN75126 is compatible with standard TTL logic
and supply voltages.
Fault-flag circuitry is designed to sense and signai a line short on any Y line. Upon detecting an output fault
condition, the fault-flag circuit forces the driver output into a low state and signals a fault condition by causing
the fault-flag output to go low.
The SN75126 can drive a 50-Q load as required in the IBM GA22-6974-3 specification or a 90-Q load as used
in many I/O systems. Optimum performance can be achieved when the device is used with either the SN75125,
.
SN75127, SN75128, or SN75129 line receivers.
The SN75126 is characterized for operation from O°C to 70°C.
Copyright © 1993, Texas Instruments Incorporated
1ExAs . "
INSIRUMENTS
POST OFFICE BOX 655303 • OALLAS, TEXAS 75265
2-279
SN75126
QUADRUPLE LINE DRIVER
SLLS06OA- 03405, FEBRUARY 1990 - REVISED FEBRUARY 1993
, logic symbol t
logic diagram (positive logic)
.......
2
~
1A ..;;;3'--_--1
iF
!)
1A -=-3_---4.....4--1
01
1,20 ..:.4--'''-_'---1
1Y
2~
6
&C>
-
U-.....- - 1F
~~_ _ _ _- r___11Y
2F
[)-....._62i=
2A ::..5_1--4.....4--1
r-e-__~-~_7~
3Y
3A ::,11:----4.....4--1
4F
3,40,;.;12::"""'''-_'---1
~~_ _ _ _- r___9~
7
4~
2Y
10 3F
11
3A - - - - - I
9
3,40
14
15
D-.....~103F
r--;==:;:::=::;jlb~_14 4F
4Y
4A .:.;13=--1--4.....4--1
t This symbol is in accOrdance wHh ANSVIEEE Sid 91·1984
15
~~-----r---4Y
and lEe Publication 617·12.
schematics of inputs and outputs
EQUIVALENT OF EACH INPUT
Vec
TYPICAL OF F OUTPUTS
TYPICAL OF ALL Y OUTPUTS
---.------4~-
Vee
....---l~VCC
20 kg NOM
r--~-
Y Output
Input --._41--1
FOutput
GND-~~~-~---
---~~~---4~-GND
A Inputs: Req = 20 kg NOM
o Inputs: Req .. 10 kg NOM
...................-GND
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee .......... , ............................................................. 7 V
Input voltage, VI ............................................................................ 7 V
. Continuous total power dissipation ..................................... See Dissipation Rating Table
Operating free·air temperature range, TA ............'.................................. O·C to 70·C
Storage temperature range ....................................................... - 65·C to 150·C
Lead temperaJure 1,6 mm (1/16 inch) from case for 10 seconds ............................... 260·C
DISSIPATION RATING TABLE
PACKAGE
TAs25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
0
950mW
7.6mw/"e
608mW
N
1150mW
9.2mw/"e
736mW
1ExAs
-If
INSlRUMENTS
2-.280
TA=70°C
POWER RATING
POST OFFICE BOX 655303 • DAUAS, TEXAS 75265
SN75126
QUADRUPLE LINE DRIVER
SLLS06OA- 03405. FEBRUARY 1990 - REVISED FEBRUARY 1993
recommended operating conditions
Supply voltage. Vee
MIN
NOM
MAX
UNIT
4.5
5
5.95
V
2
High-level input voltage. VIH
V
0.8
Low-level input voltage. VIL
High-level output current. IOH
Operating free-air temperature. TA
0
V
-59.3
rnA
70
DC
electrical characteristics over recommended operating free-air temperature range
PARAMETER
VIK
VOH
VOL
Input clamp voltage
High-level output voltage
Low-level output voltage
TEST CONDITIONS
Vee=4.5V.
IOH = -59.3 rnA.
Y
Vee = 5.25 V,
F
Vee = 4.5 V,
Y
Vee = 5.5V.
10L = -240 iAA.
VIL=0.8V
0.15
Y
Vee=5.95V.
10L=-1 rnA.
ViL=0.8V
0.15
F
Vee=4.5V.
VIH=2V
10L= 8 rnA.
YatOV.
Y
Vee=4.5V.
VI=O.
VO=3.11 V
100
Y
Vee =0.
VI=O.
'VO=3.11V
200
Vee=4.5V,
VI;=5.5V
Vee = 4.5 V,
VI = 2.7V
Vee = 5.95 V,
VI =0.4V
Y
Vee = 5.5 V,
VO=O,
F
Vee = 5.5 V,
VO=O
Y
Vee = 5.95 V,
VO=O.
Input current
7
IIH
High-level input current
7
IlL
Low-jevel input current
7
A
A
A
F
Supply current, all outputs high
lee(L)
Supply current, Y outputs low
V
Y
II
lee(H)
UNIT
-1.5
il=-18rnA
OIf-state output current
Short-circuit output current
MAX
Vee=4.5V.
IO(off)
lOS
MIN
A.G
VIH=2V
3.11
IOH=-41 rnA.
VIH =2V
3.9
10H = -400 IlA.
ViH=2V
2.5
V
100
200
20
40
-250
-500
iAA
iAA
iAA
iAA
-5
VIH = 2.7V
-15
-100
-5
VIH=2.7V
-15
rnA
-110
Vee = 5.95 V,
VO=O
Vee = 5.5 V,
No load,
VIH=2V
70
Vee = 5.95 V,
No load,
VIH=2V
80
Vee=5.5V,
No load,
VIL=0.8V
55
Vee = 5.95 V,
Noioad,
VIL=0.8V
70
1ExAs
V
0.5
rnA
rnA
~
INSIRUMENI'S
POST OFFICE BOX 655303 • DAUAS. TEXAS 75265
2-281
SN75126
QUADRUPLE LINE DRIVER
Su.s06OA- 03405, FEBRUARY 1990 - REVISED FEBRUARY 1993
switching characteristics at TA = 25°C
PARAMETER
tpLH
Propagation delay time, Iow-to-hlgh-Ievel output
tpHL
Propagation delay time, hlgh-to-Iow-Ieveloutput
tpLH\
tpHL
Ratio of propagation delay times
tpLH
Propagation delay time, low-to-hlgh-Ievel output
rt'lVM
IV
(INPUl)
(OUTPU1)
Propagation delay time, hlgh-to-Iow-Ievel output
tPLH'
Propagation delay time, Iow-to-hlgh-Ievel output
VCC=5V,
CL= 15pF,
RL=2kO,
See Figures 1 and 2
F
A
tpHL
Vce = 5.25 Vto 5.95 V.
RL=900,
CL=50pF,
VH(re1) = U V.
See Figures 1 and 2
Y
A
tpHL
Vee = 4.5 V to 5.5 V,
RL=500,
CL=50pF,
VH(re1) = 3.11 V,
See Figures 1 and 2
Y
A
TEST CONomONS
Propagation delay time; hlgh-to-Iow-Ievel output
MIN
0.3
MAX
UNIT
40
ns
37
ns
3
45
ns
45
ns
60
ns
100
ns
PARAMETER MEASUREMENT INFORMATION
I- tr
k-I I
I I
-'
I I
I I
tr-j
_ _ _1_'3_V..I'i£.-
I
A Input
tpLH
YOutput
-1.---.1
1/
I
I
VH(ref)
-----11...1.
I
I
I-
FOutput
-~:~~
tpHL ~
___________
--,. I
C
I~I~
__- J
I~
I
I
tpHL
I\
r--
!
I X-
0.5 V
I
I
/
----
4V
OV
Normal Operation
VOH
VOL
_______
!-t
I ,..--_________
tpLH
uvv~~
VOH]
Driver Short-Circuit
Operation
VOL
NOTE: The input pulse Is supplied by a generator having the following characteristics: PRR s 1 MHz, duty cycle s 50%, tr s 6 ns, tf s 6 ns,
ZO-50Q·
Figure 1. Input and Output Voltage Waveforms
2-282
POST OFACE BOX 655303 • CALlAS, TEXAS 75265'
SN75126
QUADRUPLE LINE DRIVER
SLLS06OA- 03405. FEBRUARY 1990 - REVISED FEBRUARY 1993
PARAMETER MEASUREMENT INFORMATION
5V
YO~p~ ----~~--~~------~
I
CL=50pF
(see Note AI
--
1
--
Close for
TeetlngF
I_
CL=15pF
(see Note A)
NOTE A: CL includes probe and stray capacitance.
Figure 2. Switching Characteristics Load Circuits
1ExAs ..,
INSIRUMENTS
POST OFFICE sox 655303 • DAUJ\S. TEXAS 75265
2-283
2-284
SN75ALS126
QUADRUPLE LINE DRIVER
FEBRUARY 1986 - REVISED FEBRUARY 1993
•
•
•
•
•
•
•
•
Meets IBM 360/370 VO Interface
Specification GA22-6974-3 (Also See
SN75ALS130)
Minimum Output Voltage of 3.11 Vat
IOH =-60mA
Fault-Flag Circuit Output Signals D.rlver
Output Fault
Fault-Detection Current Umlt Circuit
Minimizes Power Dissipation During a
Fault Condition
Advanced Low-Power Schottky Circuitry
Dual Common Enable
Individual Fault Flags
Designed to Be an Improved Replacement
for the MC3481
o OR N PACKAGE
(TOP VIEW)
1Y
VCC
1F
4Y
41=
4A
3,4G
3A
1,2G
4
2A
2F
2Y
GND
FUNCTION TABLE
INPUTS
OUTPUTS
G
A
Y
F
L
L
X
H
H
H
H
H
H
H
S
L
H = high level, L = low level,
X =irrelevant,
S = shorted to GND
description
The SN75ALS126 quadruple line driver is
designed to meet the IBM 360/370 I/O
specification GA22-6974-3. The output voltage is
3.11 V minimum (at IOH
59.3 rnA) over the recommended ranges of supply voltage (4.5 V to 5.95 V) and
temperature. Driver outputs use a fault-detection current-limit circuit to allow high drive current but still minimize
power dissipation when the output is shorted to ground. The SN75ALS126 is compatible with standard TTL logic
and supply voltages
=-
The SN75ALS126 employs the I MPACT'M process to achieve fast switching speeds and low power dissipation.
Fault-flag Circuitry is designed to sense and signal a line short on any Y line. Upon detecting an output fault
condition, the fault-flag circuit forces the driver output into a low state and signals a fault condition by causing
the fault-flag output to go low.
The SN75ALS126 can drive a 50-0 load as required in the IBM GA22-6974-3 specification or a 90-0 load as
used in many VO systems. Optimum performance can be achieved when the device is used with either the
SN75127, SN75128, or SN75129 line receivers.
The SN75ALS126 is characterized for operation from O·C to 70·C.
IMPACT is a trademark of Texas Instruments Incorporated
TEXAS
~
Copyright © 1993, Texas Instruments Incorporated
INSIRUMENIS
POST OFFICE BOX 655303 • DALlAS. TEXAS 75265
2-285
SN75ALS126
QUADRUPLE LINE DRIVER
SGLS017B - 02299. FEBRUARY 1986- REVISED FEBRUARY 1993
logic symbol t
logic diagram (positive logic)
2
1A..;;3----t
2
iF
1A
1
:
1,20
6
1Y
6
7
10
9
14
7
'l1
10
'Zf
:#
11
9
3A ---:---tt-+---I
3,4G -'1,..,2.......-1
1Y
'l1
'Zf
:#
3Y
3Y
4F
14
4A 13
15
11'
4Y
4A
13
15
4F
4Y
tThis symbol is in accordance with ANSI/IEEE Std 91-1984
andlEC Publication 617-12.
schematics of inputs and outputs
EQUIVALENT OF EACH INPUT
VCC-------t~---
TYPICAL OF ALL Y OUTPUTS
-----1.----------411..-20
VCC
TYPICAL OF F OUTPUT
----1....-
....-
Vec
kg NOM
r-----t-- Y Output
Input
---e-ei-l
FOUTPUT
GND---e--~--t~---
- - - - -.....----1____..-- GND
A Inputs: Req = 20 kQ NOM
G Inputs: Req = 10 kQ NOM
----1___....- GND
1ExAs . "
INSIRUMENTS
2-286
POST OFFICE BOX 655303 • DAUAS. TEXAS 75265
SN75ALS126
QUADRUPLE LINE DRIVER
SGLS017B - 02299, FEBRUARY 1986 - REVISED FEBRUARY 1993
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee ........................................................................ 7 V
Input voltage ............................................................................... 7 V
Continuous total dissipation ........................................... See Dissipation Rating Table
Operating free-air temperature range .................................................. o·e to 70·e
Storage temperature range ....................................................... - 65·e to 150·e
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds .............................. 260·e
DISSIPATION RATING TABLE
PACKAGE
TA" 25°C
POWER RATING
DERATING FACTOR
ABOVE TA 25"C
=
=
TA 70°C
POWER RATING
D
950 mW
7.6 mwre
608 mW
N
1150 mW
9.2 mwre
736 mW
recommended operating conditions
Supply voltage, Vee
High-level Input voltage, VIH
MIN
NOM
MAX
UNIT
4.5
5
5.95
V
V
2
Low-level input voltage, VIL
0.8
High-level output current, IOH
Operating free-air temperature, TA
0
V
-59.3
mA
70
°e
1ExAs ."
INSIRUMENIS
POST OFRCE BOX _
• DALlAS. TEXAS 75265
2-287
SN75ALS126
QUADRUPLE UNE DRIVER
SGLSOl7B - 02299, FEBRUARY 1986 - REVISED FEBRUARY 1993
electrical characteristics over recommended operating free-air temperature range
,
,
PARAMETER
VIK
VOH
VOL
TEST CONDITIONS
Input clamp voKage
MIN
A,G
VCC=4.5V,
11=-18mA
Y
VCC=4.5V,
10H = - 59.3 rnA,
VIH=2V
3.11
Y
VCC = 5.25 V,
IOH=-41 rnA,
VIH=2V
3.9
F
VCC=4.5V,
10H = - 400
f.IA,
240 f.IA
VIH=2V
2.5
High-level output voltage
Low-level output voltage
MAX
UNIT
-1.5
V
V
Y
VCC=5.5V,
10L = -
VIL=0.8 V
0.15
Y
Vec = 5.95 V,
IOL=-1 rnA,'
VIL=0.8 V
0.15
F
VCC=4.5V,
IOL=8mA,
YatOV
Y
VCC=4.5V,
VIL=O,
VO=3.11V
100
Y
VCC=OV,
VIL=O,
Vo =3.11 V
200
VCC=4.5V,
VI=5.5V
VCC=4.5V,
VI=2.7V
10(011)
Off-state output curreitt
II
Input curren!
~
IIH
High-level Input current
~
IlL
Low-level input curren!
~
VCC = 5.95 V,
VI =0.4V
Y
VCC = 5.5 V,
VO=O,
F
VCC = 5.5 V,
VO=O
Y
VCC = 5;95 V,
VO=O,
F
VCC=5.95V,
VO=O
VCC = 5.5 V,
No load,
VIH = 2.7V
25
Vce= 5.95 V,
No load,
VIH=2.7V
27
VCC = 5.5 V,
No load,
VIL=0.4V
45
Vec = 5.95 V,
No load,
VIL=0.4 V
47
lOS
A
A
A
Short-circuit output
ICCH
Supply current, all outputs high
ICCL
Supply curren!, Y outputs low
V
0.5
100
400
20
80
-250
-1000
f.IA
f.IA
f.IA
f.IA
-5
VIH=2.7V
-15
-100
-5
VIH=2.7V
-15
rnA
-110
rnA
rnA
switching characteristics over recommended operating free-air temperature range
PARAMETER
tpLH
TO
(OUTPUT)
TEST CONDITIONS
Propagation delay time,
high-to-Iow-Ievel output
tpLH
tpHL
Ratio of propagation
delay times
tpLH
Propagation delay time,
low-to-high-Ievel output
tpHL
Propagation delay time,
high-to-Iow-Ievel output
tpLH
Propagation delay time,
low-to-hlgh-Ievel output
Propagation delay lime,
high-to-Iow-Ievel output
A
Y
Vec = 4.5 Vto 5.5 V,
RL=500,
See Figures 1 and 2
CL= 50 pF,
VH(rel) = 3.11 V,
0.3
A
A
Y
F
Vee = 5,25 Vto 5.95 V,
RL=90Q,
See Figures 1 and 2
eL=50pF,
VH(rel) = 3.9 V,
VCC=5V,
CL= 15pF,
RL=2kO,
See Figures 1 and 2
1ExAs ."
INSIRUMENTS
2-288
MIN
Propagation delay time,
low-to-high-Ievel output
tpHL
tpHL
FROM
(INPUT)
POST OFFICE BOX 655303 • DAUAS, TEXAS 75265
MAX
UNIT
30
r1S
28
ns
3
34
ns
34
ns
45
ns
75
ns
,
SN75ALS126
QUADRUPLE LINE DRIVER
SGLS017B - D2299. FEBRUARY 1986 - REVISED FEBRUARY 1993
PARAMETER MEASUREMENT INFORMATION
--.I:+I I
tr ~ 14-
I I
I I
11
1.3Vi
__ I I
"",.tJ;
i1.3V
9O%
1I10%
A Input _ _ _ _J
tf
I+-
tpLH ---.II
1___
10%
II '\",..;.;=---"'--
j+- tpHL
-.,I
I
I
I
4V
OV
Normal
Operation
.,
-Ii,.,! i\\,..::O.5::.V.:..-....I.r_ ::
VH...
YOutput _ _ _ _
I
I
F Output
I
I
~
~r-tp_LH_ _ _ _ _ VOH}
V
_ _ _ _ __ _
tP_H_L-+1",,\I
I
I
Driver Short-CIrcuit
~~~ _ _ _ _ _ _
1.3V
VOL
Operation
NOTE: The Input pulse is supplied by a generator having the following characteristics: PRR .. 1 MHz. duty cycle .. 50%. Ir .. 6 ns. If .. 6 ns.
ZO-50C.
Figure 1. Input and Output Voltage Waveforms
5V
Y Output - -.....;.---....- - - - - ,
T
CL =50pF
1
19
3
18
4
17
6
16
6
I>
2
15
7
14
8
13
9
12
1Y
1A
'Zf
2A
:N
3A
4Y
4A
5Y
SA
6Y
SA
7Y
7A
6Y
SA
1
11
2
1'-.
"
EN1
.,
EN2
r
I>
1
I>
2
3
4
5
6
19
1Y
18 'Zf
17
3Y
16
4Y
15
5Y
7
14
8
13
9
12
6Y
7Y
6Y
t These symbols are in accordance w.h ANSI/IEEE Sid 91-1984 and lEe Publication 617-12.
Copyright © 1993, Texas InstrUments Incorporated
1ExAs . "
INSIRUMENTS
POST OFFICE BOX 655300 • DALlAS, TEXAS 75265
2-291
SN75128, SN75129
EIGHT·CHANNELLINE RECEIVERS
Su.s076A- 02305. JANUARY 1977 - REVISED MARCH 1993
logic diagrams (positive logic)
5N75129
SN75128
15
1A
2A
3A
4A
schematic (each driver)
r----+----~----~-----1-~-g~~~
Vcc
NOM
A
Input '
12ka
NOM
S
Input
,---------------- 1
I
I
I
I
I
I
I
I
I
SN7S129 I
---1-
I
I
I
I
I
SN7S129
I
rI
I
'I
I
I
I
I
I
I
I
I
L___________ ~!...of_~ __ I
17ka
NOM
ToThree .......- - - - , v r - - - - ' /
Other
To Seven
Channels
Other Chennels
2~92
1ExAs'"
INSTRUMENTS
POST OFFICE BOX 85S!CXl • DAUAS. TEXAS 7526Ii
Output
y
SN75128, SN75129
EIGHT·CHANNEL LINE RECEIVERS
SLLS076A- 02305, JANUARY 19n - REVISED MARCH 1993
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) ............................................................. 7 V
Input voltage range, A, VI .......................................................... -0.15 V to 7 V
Input voltage, S, VI .......................................................................... 7 V
Continuous total power dissipation ..................................... See Dissipation Rating Table
Operating free-air temperature range .................................................. O°C to 70°C
Storage tern perature range ....................................................... -65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds ............................... 260°C
NOTE 1: All voHage values are wilh respect to network ground terminal.
DISSIPATION RATING TABLE
PACKAGE
TA'" 25·C
POWER RATING
DERATING FACTOR
ABOVE TA = 25"0
TA = 70°C
POWER RATING
N
1150 mW
9.2 mwre
736 mW
recommended operating conditions
Supply voltage, Vee
High-level input voHage, VIH
Low-level input voltage, VIL
MIN
NOM
MAX
4.5
5
5.5
A
1.7
S
2
V
V
A
0.7
S
0.7
High-level output current, 10H
Low-level output current, IOL
Operating free-air temperature. TA
UNIT
0
V
-0.4
mA
16
mA
70
·e
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
TEST CONDITIONS
PARAMETER
MIN
TYpt
2.4
3.1
MAX
VOH
High-level output voltage
Vee =4.5V.
VIL= 0.7 V,
IOH=-0.4mA
VOL
Low-level output voltage
Vee = 4.5 V,
VIH = 1.7 V.
IOL= 16mA
VIK
Input clamp voHage
S
Vee = 4.5 V,
11=-18mA
High-level input current
A
IIH
Vee = 5.5 V,
VI =3.11 V
S
Vee = 5.5 V,
VI=2.7V
A
IlL
Low-level input current
Vee = 5.5 V.
VI=0.15V
S
Vee = 5.5 V.
VI = 0.4 V
lOS
Short-circuit output current:(:
Vee = 5.5 V,
Vo=O
fj
Input resistance
Vee = 4.5 V,
OV or open,
AVI = 0.15 Vto 4.15 V
SN75128
Vee = 5.5 V,
Strobe at 2.4 V,
All A inpuis at 0.7 V
SN75129
Vee = 5.5 V,
Strobe at 0.4 V,
All A inputs at 0.7 V
19
31
SN75128
Vee = 5.5 V.
Strobe at 2.4 V,
All A inputs al4 V
32
53
SN75129
Vee = 5.5 V.
Strobe al 0.4 V,
All A inputs al 4 V
32
53
ICC
Supply current
0.4
0.3
UNIT
V
0.5
V
-1.5
V
0.42
mA
20
30
fAA
fAA
-0.4
mA
-18
-60
mA
7
20
kC
19
31
mA
t All typical values are at Vee = 5 V. TA = 25°e. '
:(: Not more than one output should be shorted at a time.
1ExAs
,If
INSIRlJMENTS
POST OFFICE BOX 655303 • DAU.AS, TEXAS 75265
2-293
SN75128, SN75129
EIGHT-CHANNEL LINE RECEIVERS
'-
SLLS076A- 02305, JANUARY 1ff77 - REVISED MARCH 1993
switching characteristics, VCC
=5 V, TA, =25°C,
PARAMETER
FROM
i
TEST
CONDITIONS
I
i
I
MIN
TYP
7
14
25
7
14
25
ns
10
18
30
10
18
30
ns
26
40
20
35
ns
22
35
16
30
ns
0.5
0.8
1.3
0.5
0.8
1.3
MAX
MIN
TYP
MAX
UNIT
tpLH
Propagation delay time, Iow-to-hlgh-Ievel output
tpHL
Propagation delay time, high-to-Iow-Ievel output
tpLH
Propagation delay time, Iow-to-high-Ievel output
tpHL
Propagation delay time, high-to-Iow-Ievel output
tPLH
tpHL
Ratio of propagation delay times
ITLH
Transition time, low-to-high-Ievel output
1
7
12
1
7
12
ns
ITHL
Transition time, high-to-Iow-Ievel output
1
3
12
1
3
12
ns
A
S
A
RL=4000,
. CL= 50 pF,
See Figure 1
PARAMETER MEASUREMENT INFORMATION
Output
I
Input
(aee Notes Vr ef1
A,D, sndE)
VCC
100na
I I
I j.- 10 na
4000
10 ns
_ _~
........ I
tpHL
From Output
Under Test
2V
:;f
(aee Note C)
60pF
I
I
Output
(sea Note B)
---l I
I I 10%
II""-
--l
4tPLH
I
I I
I
I
0,8 V
I
!'-=:..:....---::::::..:..~- i - -
fTLH-l-i
LOAD CIRCUIT
NOTES: A
B.
C.
D.
E.
VOLTAGE WAVEFORMS
Input pulses are supplied by a generator having the following characteristics: Zo = 50 0, PRR .. 5 MHz.
Includes probe and jig capacitance.
All diodes are 1N3064 or equivalent.
The strobe inputs of SN75129 are In phase with the output.
Vreft = 0.7 V and V ref2 = 1.7 V for testing data (A) inputs, Vref1 = Vref2 = 1.3 V for strobe inputs.
Figure 1. Load Circuit and Voltage Waveforms
2-,294
POST OFFICE BOX 655303 • DALlAS, TEXAS 75265
OV
VOH
SN75128, SN75129
EIGHT-CHANNEL LINE RECEIVERS
SLLS076A- 02305. JANUARY 1977 - REVISED MARCH 1993
TYPICAL CHARACTERISTICS
VOLTAGE TRANSFER CHARACTERISTICS
FROM A INPUTS
VOLTAGE TRANSFER CHARACTERISTICS
5
5
/
VCC=5.5V
TA = 70°C
VCC=5V
4
4
VCC=4.5V
>
>
I
I
t
3
i
2
:I!!
"
3
~
!i
Q.
!i
0
2
CJI
~
-
TA=25°C
J1
-
TA=O°C -
I
.J>
I
.J>
No Load
TA = 25°C
VCC=5V
No Load
o
I
o
I
0.2 0.4 0.6 0.8 1 1.2 1.4
VI -Input Voltage - V
1.6 1.8
o
o
2
I
I
0.2
0.4
0.6 0.8 1 1.2 1.4
VI -Input Voltage - V
Figure 2
LOW-LEVEL OUTPUT VOLTAGE
V8
OUTPUT CURRENT
vs
INPUT VOLTAGE
~
0.3
I
,/
I
'E
I!!
!:i 0.2
U
!i
Q.
.5
I
=
0.1
o
V
1/
o
0.6
~
VCC=5V
No Load
_ TA=25°C
2
Figure 3
INPUT CURRENT
0.4
1.6 1.8
>
I
0.5 -
"
Ii'
:I::
/
2
3
VI-Input Voltage - V
I
VCC=5V
VI=5V
TA=25°C
~
0.4
1
!i
0
§
~
0.3
/
0.2
...-
..",.
~
~
I
..J
.J>
4
5
0,1
o
o
Figure 4
10
15
5
10 - Output Current - rnA
20
Figure 5
1ExAs
..If
INSIRUMENfS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
2-295
2-296
SN75130
QUADRUPLE LINE DRIVER
SLLS077A-
•
Meets IBM 360{370 I/O Interface
Specification GA22-6974-3 (Also See
SN75ALS130)
•
Minimum Output Voltage of 3.11 V
at IOH = -59.3 mA
•
Fault-Flag Circuit Output Signals Driver
Output Fault
•
•
•
FEBRUARY 1990 - REVISED FEBRUARY 1993
D OR N PACKAGE
(TOP VIEW)
Vee
1Y
1W
1A
4Y
4W
4A
G
F
2W
2Y
Fault-Detection Current-Limit Circuit
Minimizes Power Dissipation During a
Fault Condition
GND
Common Enable and Common Fault Flag
3A
3W
6
7
8
FUNCTION TABLE
INPUTS
Designed to Be an Improved Replacement
for the MC3485
description
OUTPUTS
Gf
A
Y
F
W
L
X
H
H
X
L
H
H
L
L
H
H
H
H
L
H
H
L
H
S
The SN75130 quadruple line driver is designed to
meet the IBM 360/370 I/O specification
H =high level, L =low level, X =irrelevant,
S =shorted to ground
GA22-6974-3. The output voltage is 3.11 V
t GandF are common to the four drivers. If any of the
minimum (at IOH = -59.3 mAl over the
four Y outputs is shorted, the fauH flag will respond.
recommended ranges of supply voltage (4.5 V to
5.5 V) and temperature (O·C to 70·C). Driver
outputs use a fault-detection current-limit circuit to allow high drive current but still minimize power dissipation
when the output is shorted to ground. The SN75130 is compatible with standard TTL logic and supply voltages.
Fault-flag circuitry is designed to sense and Signal a line short on any Y line. Upon detecting an output fault
condition, the fault-flag circuit forces the driver output into the off (low) state and signals a fault condition by
causing the fault-flag output to go low.
The SN75130 can drive a 50-0 load as required in the IBM GA22-6974-3 specification or a 90-0 load as used
in many I/O systems. Optimum performance can be achieved when the device is used with either the SN75125,
SN75127, SN75128, or SN75129 line receivers.
The SN75130 is characterized for operation from O·C to 70·C.
1ExAs
..If
Copyright © 1993, Texas Instruments Incorporated
INSIRUMENfS
POST OFFICE Box 655303 • DALlAS, TEXAS 75265
2-297
SN75130
QUADRUPLE LINE DRIVER
SLLSOnA- 03406, FEBRUARY 1990 - REVISED FEBRUARY 1993
logic symbol t
o
4
13
01 23
33
43
,
1A
3
logic diagram (positive logic)
51
~
2A
011
1
I>
21EN22.%23
021
4A
11
13
I>
31E;N32.%33
031
1
320
31
-I>
41EN42,Z43
041
1
420
41
12
~
F
_ _ _1~8VCC
1A ...:3"---'--1"--'''''''
___......+----.:11Y
l1E~2.z13
1
220
21
3A
,
4
~
120
11
5
12
o
~_+--=21W
h
h
h
1 1Y
2 1W
~_+---=82W
7 ?!i
8
2W
3A ....:.11.:....&.......-__,....
___.......+---=9 3Y
9
3Y
10 3W
~_+-.....;1:..::03W
13
4A ....:.
=-..L.....-__,....
b
15
4Y
14 4W
c>o_ _....;1,-,-4 4W
t This symbol is In accordance with ANSI/lEEE Std 91-1984
and lEe Pubncation 617-12.
. . 1ExAs..lf
2-298
INSTRUMENfS
POST OFFICE BOX e55303
• DALLAS. TEXAS 75285
SN75130
QUADRUPLE LINE DRIVER
SLLSonA- D3406, FEBRUARY 1990 - REVISED FEBRUARY 1993
schematics of Inputs and outputs
EQUIVALENT OF EACH INPUT
VCC---------.-----
TYPICAL OF ALL Y OUTPUTS
---VCC
2OkONOM
Req
H~.._----
. - - - - ; - - Y Output
Input -
........---t
----.--+----- - - --
- .....--....-4t-- GND
GND - -......
A Inputs: Req - 20 kO NOM
G Inputs: Req -10 kO NOM
TYPICAL OF F OUTPUT
TYPICAL OF ALL W OUTPUTS
- - - - ......---e---- VCC
- - - - - . - - - - - - - VCC
FOutput
WOutput
- - - - ---...---11.......-- GND
- -
-
-
...........-41____ GND
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee ........................................................................ 7 V
Input voltage .............................................................................. 7 V
Continuous total dissipation .......................................... See Dissipation Rating Table
Operating free-air temperature range, TA .....................................•........ O°C to 70°C
Storage temperature range ....................................................... -65°C to 150°C
Lead temperature 1,6 mm (1/16 Inch) from case for 10 seconds .............................. ; 260°C
DISSIPATION RATING TABLE
PACKAGE
TA" 25°C
POWER RATING
OPERATING FACTOR
ABOVE TA 25°C
=
TA = 70°C
POWER RATING
o
950 mW
7.6 mWrC
608 mW
N
1150mW
9.2mW/"C
736mW
1ExAs
.If
INSIRUMENIS
POST OFFlCE BOX 655303 • DALLAS, TEXAS 75265
2-299
SN75130
QUADRUPLE LINE DRIVER
su.sonA- 03406, FEBRUARY 1990 - REVISED FEBRUARY 1993
recommended operating conditions
Supply voltage, Vce
YIN
......
Nnu
.._.0.
MAY
..-- --
4.5
5
5.95
2
High-level input voltage, VIH
UNIT
- - ---
V
V
Low-level Input voltage, Vil
0.8
High-level output current, 10H
Operating free-airtemperalure, TA
I
0
V
-59.3
rnA
70
·c
electrical characteristics over recommended operating free-air temperature range
PARAMETER
VIK
VOH
VOL
Input, clamp voltage
High-level output voltage
Low-level output voltage
10(oft)
Off-stale output current
10H
High-level output current
TEST CONDITIONS
MIN
A,G
11=-18mA
Y
VCC=4.5V,
10H = -59.3 rnA,
VIH=2V
3.11
VCC = 5.25 V,
IOH=-41 rnA,
VIH=2V
3.9
VCC = 4.5 V,
10H = -400 j.iA,
VIH='2V
2.5
Y
VCC = 5.5 V,
10l = -240 j.iA,
VIl=0.8V
0.15
Y
VCC=5.95V,
10l=-1 rnA,
Vll=0.8V
0.15
F
Vcc = 4.5 V,
10l= 8 rnA,
YatOV
0.5
W
Vcc = 4.5 V,
IOl=8mA
Y
Vcc = 4.5 V,
Vll=O,
VO=3.11 V
100
Y
VCC=O,
Vll=O,
VO=3.11 V
200
F
VCC=5.95V,
VOH=5.95V
A
~
IIH
High-level Input current
~
III
Low-level Input curren\
~
A
100
100
VCC=4.5V,
VIH=5.5V
VCC '" 4.5 V,
VIH =2.7V
VCC = 5.95 V,
Vll=0.4V
A
-W VCC = 5.5 V,
400
20
80
ICCl
Supply current, Y outputs low
j.iA
j.iA
j.iA
j.iA
j.iA
-5
VO=O
VO=O
-15
'-100
-15
"':110
VCC = 5.5 V,
VI=2V
75
VCC = 5.95 V,
VI=2V
85
VCC = 5.5 V,
VI =0.8V
55
VCC=5.95V,
VI =0.8V
70
1ExAs
~
INSIRUMENTS
2-300
V
250
-1000
-5
Y
-W VCC = 5.95 V,
Suppiy current, all outputs high
V
0.5
Y
ICCH
V
Y
Input current
Short-circuit output
UNIT
-1.5
W
II
lOS
MAX
POST OFFICE BOX 655303 • DAUAS, TEXAS 75265
rnA
rnA
rnA
SN75130
QUADRUPLE LINE DRIVER
Su.s077A- 03406, FEBRUARY 1990 - REVISED FEBRUARY 1993
switching characteristics over recommended operating free-air temperature range
PARAMETER
tpLH
Propagation delay time,
low-to-high-Ievel output
tpHL
Propagation delay time,
high-to-Iow-Ievel output
tpLH
tPHL
RatiO of propagation
delay times
tPLH
Propagation delay time,
low-to-high-Ievel output
FROM
(INPUT)
TO
(OUTPUT)
Propagation delay time,
high-to-Iow-Ieveloutput
tpLH
Propagation delay time,
low-to-high-Ievel output
tPHL
Propagation delay lime,
high-to-Iow-Ievel output
IpLH
Propagation delay time,
low-to-high-Ievel output
tpHL
VCC = 4.5 V to 5.5 V,
CL=50pF,
Input f = 1 MHz,
y
A
MIN
VH(ret) = 3.11 V,
RL=50D,
See Figures 1 and 2
0.3
y
A
tPHL
TEST CONDITIONS
A
W
Propagation delay time,
hlgh-Io-Iow-Ievel output
VH(ret) = 3.9 V,
RL=90D,
See Figures 1 and 2
VCC =5V,
CL=15pF,
RL=2kD,
See Figures 1 and 2
UNIT
40
ns
37
ns
3
45
ns
45
ns
45
ns
28
ns
60
ns
100
ns
RL= 2kQ,
See Figures 1 and 2
VCC=5V,
CL=15pF,
F
A
VCC = 5.25 V to 5.59 V.
CL=50pF,
Input f = 5 MHz,
MAX
PARAMETER MEASUREMENT INFORMATION
tr~~
~l4-tf
V
i I
I 90%
(see NoteA)_ _ _'_O%..-I1I 1.3V
A Input
90%
~III
1.3V
I
j4'OV
I ~ 10%
_ _ _ OV
I
~ tpHL
tpLH --,.-..:
..,!.,! ~,~ i~ ..
I·
r
YOutPut_ _ _ _
tpHL
WOutput
.1
1
I
I
uv\
.1
1
v
L::
tpLH
Juv \-
. .
F Output
1.3V
~
V
j+- tPHLi
=~
tpLH
VOH
VOL
5.0
]
_~3~ _ _ _ _ _ _ 0.4
Driver
Short-Circuit
Operation
NOTE A: The input pulse is supplied by a generator having the following characteristics: PRR = 1 MHz, duty cycle = 50%, tr s 6 ns, If S 6 ns,
ZO=50Q·
Figure 1. Input and Output Voltage Waveforms
1ExAs ."
INSIRUMENIS
POST OFFICE BOX 655303 • DAUAS. TEXAS 75265
2-301
SN75130
QUADRUPLE LINE DRIVER
SUS077A- D3406, FEBRUARY 1990 - REVISED FEBRUARY 1993
PARAMETER MEASUREMENT INFORMATION
sv
2kC
I
y Output
CL=1SpF
(see Note A)
~t------.------.,
I
CL=50pF
(_NoteA)
1
Cloeefor
Testing'
NOTE A: CL inclu~es probe and stray capacHanca.
Figure 2. Switching Characteristics Load Circuits
1ExAs . "
INSIRUMENTS
2~02
POST OFFICE BOX 655303 • DAUAS, TEXAS 75265
SN75ALS130
QUADRUPLE LINE DRIVER
FEBRUARY 1986- REVISED
SLLS024B-
•
•
•
•
Meets IBM 360/370 I/O Interface
Specification GA22·6974·3 (Also See
SN75ALS126)
Minimum Output Voltage of 3.11 Vat
IOH =-60mA
FauH·Flag Circuit Output Signals Driver
Output Fault
D OR N PACKAGE
(TOP VIEW)
1Y
4Y
4W
4A
F
FauH·Detectlon Current·Llmit Circuit
Minimizes Power Dissipation During a FauH
Condition
•
Advanced Low·Power Schottky Circuitry
•
Common Enable and Common Fault Flag
Designed to Be an Improved Replacement
for the MC3485
•
VCC
3A
3W
2W
NOT RECOMMENDED FOR NEW DESIGN
FUNCTION TABLE
description
INPUTS
The SN75ALS130 quadruple line driver is
designed to meet the IBM 360/370 I/O
specification GA22-6974-3. The output voltage is
3.11 V minimum (at IOH = - 59.3 mA) over the
recommended ranges of supply voltage (4.5 V to
5.95 V) and temperature. Driver outputs use a
fault-detection current-limit circuit to allow high
drive current but still minimize power dissipation
when the output is shorted to ground. The
SN75ALS130 is compatible with standard TTL
logic and supply voltages.
OUTPUTS
Gt
A
Y
Ft
W
L
X
X
L
H
H
L
L
H
H
H
H
L
H
H
L
H
H
H
=
S
=
H high level, L low level,
X = irrelevant, S = shorted to ground
t G and F are common to the four
drivers. If any of the four Y outputs is
shorted, the fault flag will respond.
The SN75ALS130 employs the IMPACT'" process to achieve fast switching speeds and low power dissipation.
Fault-flag c;;ircuitry is designed to sense and signal a line short on any Y line. Upon detecting an output fault
condition, the fault-flag circuit forces the driver output into a low state and signals a fault condition by causing
the fault-flag output to go low.
The SN75ALS130 can drive a 50-Q load as required in the IBM GA22-6974-3 specification or a 90-Q load as
used in many I/O systems. Optimum performance can be achieved when the devices are used with either the
SN75125, SN75127, SN75128, or SN75129 line receivers.
The SN75ALS130 is characterized for operation from O·C to 70·C.
IMPACT is a trademark of Texas instruments Incorporated
1ExAs
..Jf
Copyright © 1993, Texas Instruments Incorporated
INSIRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
2-303
SN75ALS130
QUADRUPLE LINE DRIVER
Sll.S024B - D2299, FEBRUARY 1986 - REVISED FEBRUARY 1993
logic symbol t
G
1A
2A
4
logic diagram (positive logic)
Q ..........
,
3
5
12j:
,,1
13
G1 23
33
43
___.+--...:.1 1Y
1l~12,z13
1
011
i2~
11
2i~N22,Z23
1
021
22~
21
SA
11
.-~~1~6VCC
12
3f~N32,Z33
1
031
32~
31
ht-....
1
1Y
2
1W
2A ..::,5--1---1".......JJ-'
___......+-_72'(
ht-....
7
6
h
t-....
9
10
h
t-....
15 4Y
14
2'(
2W
11'---J---I".......oO-'
SA...:.
av
___.+--...:.9
3W
av
I>
4A
13
1
41EN42,Z43
041
42~
41
4W
4A....;.13"--1---1".......JJ-'
___._=15 4Y
t This symbol is in accordance with ANSI/lEEE Sid 91-1984 and
lEe Publication 617-12.
1ExAs ."
INSIRUMENTS
2-304
POST OFFICE BOX 655303 • DAUAS. TEXAS 75265
SN75ALS130
QUADRUPLE LINE DRIVER
SUB024B - D2299. FEBRUARY 1986 - REVISED FEBRUARY 1993
schematics of Inputs and outputs
EQUIVALENT OF EACH INPUT
TYPICAL OF ALL Y OUTPUTS
VCC----~.----
- - + - - - - - 4 1 - - VCC
2OkO NOM
Req
.----+-- Y Output
Input -
_ _I---i
GND--e--+~._---
A Inputs: Req
G Inputs: Req
- - -....- e - - - 4 I - - GND
=20 kg NOM
=10 kg NOM
TYPICAL OF F OUTPUT
TYPICAL OF ALL W OUTPUTS
VCC
~------VCC
FOutput
WOutput
GND
~
__e-+-GND
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee ........................................................................ 7 V
Input voltage ............................................................................... 7 V
Continuous total dissipation ........................................... See Dissipation Rating Table
Operating free-air temperature range .................................................. O·C to 70·C
Storage temperature range ....................................................... - 65·C to 150·C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds ............................... 260·C
DISSIPATION RATING TABLE
PACKAGE
TAs25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 250C
TA = 7O"C
POWER RATING
0
950mW
7.6mWrC
608mW
N
1150mW
9.2mWrC
736mW
lExAs ~
INSIRUMENTS
POST OFFICE BOX 655303 • DAUAS. TEXAS 75265
2-305
SN75ALS130
QUADRUPLE LINE DRIVER
SUS0248 - 02299. FEBRUARY 1986 - REVISED FEBRUARY 1993
recommended operating conditions
Supply voltage. VCC
High-level input voltage. VIH
YIN
-----.
NOU
------
UAY..
.---
4.5
5
5.95
2
V
V
Low-level input voltage. VIL
0.8
High-level output current. 10H
Operating free-air temperature. TA
I IINIT
--_.-.
0
V
-59.3
rnA
70
·C
electrical characteristics over recommended operating free-air temperature range
PARAMETER
VIK
VOH
VOL
Input clamp voltage
High-level output voltage
Low-level output voltage
10(off)
Off-state output current
10H
High-level output current
TEST CONDITIONS
VCC=4.5V.
11=-IBmA
Y
VCC=4.5V.
10H = - 59.3 mAo
VIH=2V
3.11
10H =-41 mAo
VIH=2V
3.9
VCC=4.5V.
10H = - 400 !lA.
VIH=2V
2.5
Y
Vcc= 5.5V.
10L = - 240 !AA
VIL=0.8V
0.15
Y
VCC=5.95V,
10L=-1 mA.
VIL=0.8V
0.15
F
W
VCC=4.5V.
IOL=8mA.
YatOV
0.5
VCC=4.5V.
IOL=8mA
Y
VCC=4.5V.
VIL=O.
VO=3.11 V
100
Y
VCC=O.
VIL=O.
VO=3.11 V
200
F
VCC=5.95V,
VOH = 5.95 V
A
IIH
High-level input current
G
IlL
loW-level input current
G
Supply current. all outputs high
ICCL
Supply current. Y outputs low
A
A
V
VCC=4.5V.
VIH = 5.5V
VCC=4.5V,
VIH=2.7V
VCC=5.95V,
VIL=0.4 V
100
400
20
80
250
-1000
Y
VCC= 5.5V.
VO=O.
W
VCC= 5.5V.
VO=O
Y
VCC = 5.95 V,
VO=O.
W
VCC=5.95V.
VO=O
VCC=5.5V.
No load.
VIH=2.7V
30
VCC = 5.95 V,
No load.
VIH=2.7V
32
No load.
VIL=0.4V
45
No load.
VIL=0.4V
47
VCC
=5.5 V,
VCC= 5.95V.
1ExAs . "
POST OFFICE BOX 65530G • OAW\S. TEXAS 75265
V
0.5
100
INSIRUMENTS
2-306
V
VCC=5.25V.
G
ICCH
UNIT
-1.5
Y
II
Short-circuit output current
MAX
W
Input current
lOS
MIN
A.G
!lA
!lA
!lA
!lA
!lA
-5
VIH=2.7V
-15
-100
-5
VIH=2.7V
-15
mA
-110
mA
mA
SN75ALS130
QUADRUPLE LINE DRIVER
SUS024B - 02299, FEBRUARY 1986 - REVISED FEBRUARY 1993
switching characteristics over recommended operating free-air temperature range
PARAMETER
tpLH
TO
(OUTPUT)
TEST CONOmONS
MIN
Propagation delay time,
low-to-high-Ievel output
tpHL
Propagation delay time,
high-to-Iow-Ievel output
.!ali
tpHL
Ratio of propagation delay
times
tpLH
Propagation delay time,
low-to-high-Ievel output
tpHL
Propagation delay time,
high-to-Iow-Ievel output
tpLH
Propagation delay time,
low-to-high-Ievel output
tpHL
Propagation delay time,
high-to-Iow-Ievel output
tpLH
Propagation delay time,
low-to-high-Ievel output
tpHL
FROM
(INPUT)
Propagation delay time,
high-to-Iow-Ievei output
A
y
VCC = 4.5 Vto 5.5 V.
CL=50pF,
Input f = 1 MHz,
RL=50Q,
VH(ref) = 3.11 V.
See Figures 1 and 2
0.3
A
A
A
y
W
F
VCC = 5.25 Vto 5.95 V,
CL=50pF,
Input f = 5 MHz,
RL=90Q,
VH(ref) = 3.9 V.
See Figures 1 and 2
VCC=5V,
CL= 15pF,
RL=2kQ,
See Figures 1 and 2
VCC=5V,
CL= 15pF,
RL=2kQ,
See Figures 1 and 2
1ExAs
MAX
UNIT
30
ns
28
ns
3
34
ns
34
ns
34
ns
21
ns
45
ns
75
ns
~
INSIRUMENTS
POST OFFICE BOX 655303 • DAUAS, TEXAS 75265
2-307
SN75ALS130
QUADRUPLE LINE DRIVER
SLLS0248 - 02299, FEBRUARY 1986- REVISED FEBRUARY 1993
PARAMETER MEASUREMENT INFORMATION
Normal
Operation
YOUtput
WOutput
Driver
Short-CIrcuit
FOutput
Operation
NOTE A: The input pulse is supplied by a generator having the following characteristics: PRR " 1 MHz, duty cycle" 50%, tr " 6 ns, tf " 6 ns,
ZO-50a,
Figure 1. Input and Output Voltage Waveforms
1ExAs ."
2-308
INSlRlJMENTS
POST OFFICE BOX 655303 • DAllAS, TEXAS 75265
SN75ALS130
QUADRUPLE LINE DRIVER
SUS024B - D2299, FEBRUARY 1986 - REVISED FEBRUARY 1993
PARAMETER MEASUREMENT INFORMATION
5V
2kC
WOutput
/f' CL =15pF
..L (see Note A)
Y Output
----ef----e-------,
T
CL =50pF
(see Note A)
-
Y
Close for
TestlngF
5V
.
FOutput
~
2kC
---i
T
=
CL 15 pF
(see Note A)
NOTE A: CL Includes probe and stray capacitance.
Figure 2. Switching Characteristics Load Circuits
1ExAs
..If
INSIRUMENTS
POST OFFICE BOX 655303 • DAllAS, TEXAS 75265
2-309
2~10
SN75136
QUAD BUS TRANSCEIVER
WITH 3-STATE OUTPUT
JANUARY 1977 - REVISED
Su.s078A-
•
PNP Inputs for Minimal Input loading
(200 JlA Maximum)
•
•
High-Speed Schottky Circuitry
•
•
•
•
o OR N PACKAGE
(TOP VIEW)
RE
3-State Outputs for Driver and Receiver
Party-Line (Data-Bus) Operation
1
VCC
1R
DE
1B
4R
4B
10
40
Single 5-V Supply
3R
20
Driver Has 4O-mA Current Sink Capability
GNO
Designed to Be Functionally
Interchangeable With Signetics N8T26.
Also Called 8T26
logic symbol t
description
DE
The SN75136 is a quad transceiver utilizing
Schottky-diode-clamped transistors. Both the
driver and receiver have 3-state outputs. With pnp
inputs, the input loading is reduced to a maximum
input current of 200 !lA.
RE
10
1R
20
The SN75136 is characterized for operation from
O°C to 70°C.
2R
3D
Function Tables
3R
DRIVER
INPUTS
1993
40
0
DE
OUTPUT
B
L
H
H
H
H
L
X
L
Z
4R
15
1
4
EN1
1'0.
.,
EN2
r
I>
2
V2
1V
TA=125·C
VCC=s.SV
vcc=sv
5
vcc =4.SV
3.
~I--' TA=25·C
VCC=SV
VI(D)=2V
_
Load = 50 Q to VCC
1!!
~
!i
4
0
!
3
I,
2
VI(D) =2V
TA=25·C (
Load = 50 Q to VCC
-
B
~
TA=-55·C
o
.i
o
2
VCc';s.SV
3
4
o
o
VI(S)- Strobe Input Voltage - V
2
3.
VI(S)- Strobe Input Voltage - V
Figure 5
Figure 6
t Data for temperatures below O·C and above 70·C is applicable to SN55138 circuHs only.
1ExAs ..,
INSIRUMENTS
2-322
VCC=4.5V
POST OFFICE BOX 655303 • DAUAS, TEXAS 75265
4
SN55138, SN75138
QUAD BUS TRANSCEIVERS
SUS079A- 01663. SEPTEMBER 1973 - REVISED FEBRUARY 1993
TYPICAL CHARACTERISTICSt
RECEIVER TRANSFER CHARACTERISTICS
RECEIVER TRANSFER CHARACTERISTICS
15
15 r-----~----~--~--~-----,
VCC=15V
SV
TA -25OC
Load:
Load:
~
s ~-----r------~
4000
4000
R-_W....
,
4
J 3~~f~1
I
J
VCC -SoIlV
10kO
VCC=IIV
o
4
~
o
FigureS
HIGH-LEVEL OUTPUT VOLTAGE
HIGH-LEVEL OUTPUT VOLTAGE
va
va
OUTPUT CURRENT (RECEIVER)
I
OUTPUT CURRENT (RECEIVER)
5r-~--~--T-~--~---r---;--~
I
=
VCC=5V
VI(R)=0.8V
VI(R) 0.8 V
TA",25·C
?:;A=1~.C
>
I
~~TA=25·C
III
,
~
~
o
6
10
3 I-oo::-..pr,,~--il---I--+---I-+--f
~
io
TA=-SS·C\'
o
4
2
3
VI/R) - Receiver Input Voltage - V
Figure 7
s
-
" -
'" "
TA=125·C
2
3
VI/R) - Receiver Input Voltage - V
"
All Diodes
1N914
~
I
1
..... "
10kO
~
VCC=4.IIV~
TA =25OC
g
~
...
R
I----~--+-r__\~.--~---I
2
I
IIV
i\.
15
2
I
~
~
20
~
'25
30
315
40
IOH(R) - High-Level OutpU1 Current - mA
5
10
15
20
25
30
315
40
IOHtR)- Hlgh-Leval Output Current - mA
Figure 9
Figure 10
t Data for temperatures below O·C and above 70·C is applicable to SN55138 circuHs only.
lExAs' ."
INSIRUMENTS
POST OFFICE BOX 855300 • OAUAS. TEXAS 75265
2-323
SN55138, SN7S138
QUAD BUS TRANSCEIVERS
SLLS079A- 01663. SEPTEMBER 1973 ~ REVISED FEBRUARY 1993
TYPICAL CHARACTERISTICSt
LOW·LEVEL OUTPUT VOLTAGE
va
va
OUTPUT CURRENT (RECEIVER)
OUTPUT CURRENT (DRIVER OUTPU1)
1.2 ,..---,---r---I'T""---,r---..,.,---,
VCC=4.5V
VI(R) =,3.5 V t--t-t---i'----H---I
TA=-55°C
0.8 I--+--===--.-------II+--if--+-~
0.6 1--+--I--II--F'-----:llio>"":r-i---;
0.4 t---t---h~+--t--+-----I
I
~
~
'>I
i~,
1.2 ,..--"'T""---'--"'T'"Ir--""""'T--r"T"'l-""
VCC =4.5V
VI(D) =2V
1 VI(S) = 0.8 V - t - - - H
0.8
I
Ie:
t--+-
TA=-55"C
t--t--t--Jt----t
0.4 t--+-----,h~~"---II---i---t
I
oJ
~
0.2
0.2
o~-~--~-~-~~-~-~
10
20
30
40
50
IOLlR) - Low-Level Output Currant - mA
o
60
50
Figure 11
c(
1it:
va
I
.5
~
1i
1.6
I
~I
125°C, ~
TA = 1
1.2
TA=-55°C
::I
~
Is
0.6
I
0.4
c.
.5
•
1a:
a:
~
I
~
0.2
TA = 125°C.,
o
o
TA=~oC,-55°C- ~
2
3
4
5
VieR) - Receiver Input Voltage - V
VI(S) !2V
1.4 t- TA = 25"C
L
1.2
V
0
0.8
g
6
I
0.8
VCC=4.5V I
,I
VCC=5V -
0.6
0.4
-.l
0.2
o
r--
VCC=5.5V
o
Figure 13
IN~
POST OFFICE BOX 655303 • DALlAS. TEXAS 75265
-.l
1
2
3
4
5
VieR) - Receiver Input Voltage - V
Figure 14
t Data for temperatures below DOC and above 70°C is applicable to SN55138 circuftsonly.
2-324
300
~ECEIVER INPUT CURRENT
RECEIVER INPUT VOLTAGE
0
Sc.
250
RECEIVER INPUT VOLTAGE
E
I
200
va
VCC=5V
VI(S) =2V
1.4
150
Figure 12
RECEIVER INPUT CURRENT
1.6
100
IOLeC) - Low-Level Output Current - mA
6
SN55138, SN75138
QUAD BUS TRANSCEIVERS
SLLS079A- 01663. SEPTEMBER 1973-REVISEO FEBRUARY 1993
TYPICAL CHARACTERISTICSt
SUPPLY CURRENT
va
SUPPLY CURRENT
SUPPLY VOLTAGE
(ALL DRIVER OUTPUTS LOW)
SUPPLY VOLTAGE
va
eo
eo
VI(S)=O.BV
VI(D)=2V
Driver Loada = 1 k Q to 5 V
I
70
«
E
60
I
C
~::I
0
~
40
~
!J rJ
a.
a.
::I
1/1
30
I
0
E
~
TA =125oe
50
ke
# ~
10
o
o
.... ~
60
C
50
0
40
§
:,...-:;A = 1250C
V
~
a.
::I
1/1
4 Drlj Inputs 8t
0
E
4
5
6
7
J
20
o
8
I
24
V
o
E
F
~
Ii
Q
20
16
va
FREE·AIR TEMPERATURE
SUPPLY VOLTAGE
c
'-i
tpLH(~
tPLH(D-Dl-
0
'i
!2
a.
8
i
--
--
~
--~
-I-
tpHL(D-D) -
f-tPLH(R~~
12
I ......
30
tPHL(R-R)
I
I I I I I I
TA=25°e
Driver Load: eL = 50 pF. RL = 50 0, See Figure 1
Receiver Load: eL = 15 pF, RL. 400 Q, See Figure 2
tPHL(S-D)
40
I!
I
:I
E
F
f
Q
6
'i
I
-
20
I
-6 -40 -20 0 20 40 60 eo 100 120 140
TA - Free-Air Temperature - °e
I
tPLHlS-D)
tpLH(D-D)
15
t~H~-D)
10
tpHL(R-R)
IL
5
tjLH(j-R)
4
o
8
PROPAGATION DELAY TIMES
I I
1 -...
3
4
567
Vee - Supply Voltage - V
Figure 16
Vee = 5 V
I
I
I
I
I
Driver Load: eL = 50 pF. RL = 50 Q. See Figure 1
Receiver Load: eL = 15 pF. RL = 400 Q,
See Figure 2
tpHL(S-D)
-
2
va
~
:I
Inputs at 0.8 V
~
/
PROPAGATION DELAY TIMES
III
C
k% ~
~rlver
Figure 15
28
I
30
Vee - Supply Voltage - V
32
I
28t2V.28t0.8V.......,
10
3
h ~""
./
I
I
VJ
V
2
~
I
TA=-55°e
20
TA=25oe
VI(S) .. 0.8 V
Driver Loada = 1 kQ to 5 V
R Output Open I
I
70
o
4.5 4.6 4.7 4.8 4.9
Figure 17
5
5.1
-
5.2 5.3 5.4 5.5
Vee - Supply Voltage - V
Figure 18
t Data for temperatures below O·C and above 70°C is applicable to SN55138 Circuits only.
POST OFFICE BOX 655303 • DAllAS. TEXAS 75265
2-325
SN55138, SN75138
QUADRUPLE BUS TRANSCEIVERS
SLLS079 - 01663, SEPTEMBER 1973 - REVISED SEPTEMBER 1986
TYPICAL CHARACTERISTICS
ReceiveR PROPAGATION DELAY TIMES
DRrvER pROpAGATION DeLAY
va
vs
LOAD CAPACITANCE
LOAD CAPACITANCE
30
16
I
14
TA=25"C
."
c
."
c
I
I
III
I
irI'
a
E
1=
1=
irI'
11
Q
c
0
i
Ii'
r:t.
12
tPHL(~
10
IS
10
e
I
vcci =5V I
RL = 400 g, See Figure 2
8
'iat
6
~
0..
4
l:::::: ~
".....
;.......-
~
V
..........
::::::~.R)
."
VCC=5V
RL=50Q,
See Figure 1
TA =25"C
0..
5
2
o~~~--~~--~~~~~~~
o
~
o
~
50 ~ 1001~1~1501~~
CL- Load Capacitance - pF
o
ro
m 30 ~ 50 50
CL - Load Capacitance - pF
Figure 19
ro
~
Figure 20
APPLICATION INFORMATION
5V
5V
1-----1
I
I
I
I
P
-=
I@
I
50 ft Belden #8795
100·0 Telephone Cable
@I
>-I-@
L~4.!N~!..3S_!
!"!!~!!~~J
@
------------------oV
5V
4V
@---
2V
@
OV
TYPICAL VOLTAGE WAVEFORMS
Figure 21. Point·to·Point Communication Over 50 Feet of Twisted Pair at 5 MHz
1ExAs ..,
INSIRUMENTS
2--326
POST OFFICE BOX 655303 • OAUAS, TEXAS 75265
SN55138, SN75138
QUAD BUS TRANSCEIVERS
SLLS079A- 01663, SEPTEMBER 1973 - REVISED FEBRUARY 1993
APPLICATION INFORMATION
5V
5V
1000
1000
r_-+-+-_1_oo_ft_--+--+_1_oo_ft_-_"'~+II+'~~~~~~~_-+-250_ft_-_-_-_--:~ :
50ft
@
@
<-'I
I
I
I
>--1-L1_'4_SN_55_138 !
P
Belden #879S
Telephone Cable
or Equivalent
@
-
®
E
~
(~t::--f--t:f--f :~ @ \----E--1----£~~1:::
-
---
----
- OV
---....
---
OV
-4V
4V
-2V
2V
-OV®
OV
-4V
-2V
-OV
TYPICAL VOLTAGE WAVEFORMS
Figure 22. Party-Line Communication on 500 Feet of Twisted Pair at 1 MHz
5V
5V
1000
1000 ft RG.fi3
or Equivalent
>--i-+-@
@--f----t----F---i-==:~~
@ 1---t=---j---t-===-:!~
---1----_
" ---.
OV
----
_--_
- - - - . - - -..... 2V
--------------------OV
5V
----
4V
_ - " ' \ " - 3V
- - - - 2V
@-
. ' -_ _--L _ _ _ _ _ OV
-:----OV
TYPICAL VOLTAGE WAVEFORMS
Figure 23. Point-to-Point Communication Over 1000 Feet of Coax at 1 MHz
1ExAs
~
INSIRUMENTS
POST OFFICE BOX 656303 • DAUAS. TEXAS 75265
2-327
2-328
SN75140, SN75141
DUAL LINE RECEIVERS
Su.s08OA- D21
•
Single S-V Supply
•
± 1OO-mV Sensitivity
•
JANUARY 1977- REVISED FEBRUARY 1993
0, P, OR pst PACKAGE
(TOP VIEW)
1 0 U T D a Vee
cOMSTRB 2
7 20UT
1LINE
3
6 COM REF
For Application as:
Single-Ended Line Receiver
Gated Oscillator
Level Comparator
GND
4
5
2L1NE
t The PS package is only available left-ended taped and reeled
•
Adjustable Reference Voltage
•
TTL Outputs
•
TTL-Compatlble Strobe
•
Designed for Party-Line (Data-Bus)
Applications
•
Common Reference Pin
•
Common Strobe
•
SN7S141 Has Diode-Protected Input Stage
for Power-Off Condition
(order SN75140 PSlE).
SN7S141
NOT RECOMMENDED FOR NEW DESIGN
logic symbol;
COMSTRB
-=--,
2llNE
-=---,
description
Each of these devices consists of a dual
single-ended line receiver with TTL-compatible
strobes and outputs. The reference voltage
(switching threshold) is applied externally and can
be adjusted from 1.5 V to 3.5 V, making it possible
to optimize noise immunity for a given system
design. Due to their low input current (less than
100 !lA), they are ideally suited for party-line
(bus-organized) systems.
*
This symbol is in accordance wRhANSl/lEEE Std 91·1984
and lEe Publication 617-12.
logic diagram (positive logic)
The SN75140 has a common reference voltage
pin and a common strobe. The SN75141 is the
same as the SN75140 except that the input stage
is diode protected.
The SN75140 and SN75141 are characterized for
operation from O'C to 70'C.
COMSTRB~~--~--~~\~
1liNE -"'--I .....
COM REF 6
~-r~__~
2UNE -",,5_-i-'
FUNCTION TABLE
(each receiver)
liNE INPUT
STROBE
OUTPUT
s Vref-100 mV
l
'" Vref + 100 mV
X
X
H
H
l
l
H =high level.
TEXAS
..If
l
=low level.
X =irrelevant
Copyright© 1993. Texas Instruments Incorporated
INSIRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
2-329
SN75140, SN75141
DUAL UNE RECEIVERS
SLLS08OA- 02155, JANUARY 1ffT7 - REVISED FEBRUARY 1993
schematic (each receiver)
r--.--.-------~----~----.----.------~~------~~~--VCC
1500
750
To Other
Line Receiver
1500
UNE
COMREF .....-"M---'"-+----'
~--OUT
To Other
Line Receiver
L-----~~----~----~----+---~-----+~14r_+------GND
To Other Une Receiver
COMSTRB
LEGEND:
1111111111
1.-_ _ _ _ _ _ _
SN75140 device only
Resistor values shown are nominal and in ohms.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) ...................................................... '....... 7 V
Reference input voltage, Vref ............................................................... 5.5 V
Line input voltage range with respect to GND .......................................... - 2 V to 5.5 V
Line input voltage with respect to Vref .... ,................................................... :t5 V
Strobe input voltage ... ,................................................................... 5.5 V
Continuous total power dissipation ..................................... See Dissipation Rating Table
Operating free-air temperature range ...........•.....•................................ O°C to 70°C
Storage temperature range ....................................................... - 65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds ............................... 260°C
NOTE 1: Unless otherwise specified, voltage values are with respect to network ground tem1inal.
DISSIPATION RATING TABLE
PACKAGE
TA:s25°C
POWER RATING
DERATING FACTOR
ABOVE TA 25°C
=
=
TA 70°C
POWER RATING
0
725mW
5.8mWre
464mW
p
1000mW
8.0mWre
640mW
PS
450mW
3.6mWre
288mW
recommended operating conditions
UNIT
MIN
NOM
MAX
Supply voltage, Vee
4.5
5
5.5
V
Reference input voltage, Vref
1.5
3.5
V
Vref+ 0.1
0
Vee- 1
Vret-0.1
V
High-level strobe input voltage, VIH(Sl
2
5.5
V
Low-level strobe input voltage, VIL(S)
0
0.8
V
High-level line input voltage, VIHlU
low-level line input voltage, VIL(L)
1ExAs ."
INSTRUMENTS
2-330
POST OFFICE BOX 65530G • DALLAS. TEXAS 7526S
)
V
SN75140, SN75141
DUAL LINE RECEIVERS
SLlSOIIOA- 02156, JANUARY 1ff77 - REVISED FEBRUARY 1993
=
electrical characteristics over recommended operating free-airtemperature range, Vee 5 V :t1 0%,
Vref = 1.5 V to 3.5 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Strobe input clamp voHage
II(s)=-12mA
VOH
High-level output voHage
VIL(L) = Vref -100 mV,
10H = -400 ..,A
VIL(S) = 0.8 V.
VIL(S) = 0.8 V.
Low-level output voHage
VIH(L) = Vref + 100 mV,
10L= 16mA
VOL
VIL(L) = Vref -100 mV,
10L= 16mA
VIH(S) =2V,
VIK
II(S)
Strobe input current at
maximum input voHage
MIN
TYpt
V
0.4
0.4
Strobe
1
COMSTRB
VI(S) =5.5V
2
LINE
80
VI(L) = 3.5 V,
COMREF
Vref= 1.5V
Vref=3.5V
VI(L) =0,
35
100
35
100
70
Strobe
LINE
VI(S) = 0.4V
-3.2
VI(L) =0,
Vref= 1.5V
VI(L) = 1.5 V,
Vref
Reference
COMREF
lOS
Short-circuit output current:!:
ICCH
Supply current, output high
ICCL
Supply current, output low
..,A
200
-1.6
COMSTRB
Low-level Input current
rnA
40
VI(S)=2.4V
Reference
IlL
V
2.4
Strobe
High-level input current
UNIT
-1.5
V
COMSTRB
IIH
MAX
mA
-10
-10
=0
..,A
-20
-55
rnA
VIIS) =0,
VI(U =Vref-l00mV
-18
18
30
mA
VI(S) =0,
VI(U = Vref + 100 mV
20
35
rnA
TYP
MAX
22
35
22
30
12
22
8
15
VCC=5.5V
t All typical values are at VCC = 5 V. TA = 25°C.
:!: Only one output should be shorted at a time.
switching characteristics, Vee
=5 V, Vref =2.5 V, TA =25°C
PARAMETER
TEST CONOmONS
tPLH(L)
Propagation delay time, low-to-high-Ievel output from LINE
tpHLlU
Propagation delay time, high-to-Iow-Ievel output from LINE
tpLH(S)
Propagation delay time, low-to-hlgh-Ievel output from COMSTRB
tPHL(S)
Propagation delay time, hlgh-to-Iow-Ievel output from COMSTRB
1ExAs
CL=15 pF,
RL=400 kQ,
See Figure 1
MIN
UNIT
ns
ns
..If
INSIRUMENTS
POST OFFICE BOX 655303 • DAllAS, TEXAS 75265
2-331
SN75140, SN75141
DUAL UNE RECEIVERS
SlLS08OA- 02155, JANUARY 1977 - REVISED FEBRUARY 1993
PARAMETER MEASUREMENT INFORMATION
2.7 V
2.6 V
VCC
OUtput
,
,
,
,
I
------l
I s 10 ns--+J" 14-- --.,
14-- S
I .
I
--M---.j
I
UNE--+H
COMSTRB -+-....I!:...--I
(see Note B) L __
,
-
tpHL(L)
1
Output
TEST CIRCUIT (see Note A)
1.5Vf
1.5V\
..
~'
--
k,
,
-...I I.- tPLH(S)
I
1.5V\
: r - '
1.5V:;.
Figure 1. Test Circuit and Voltage Waveforms
TYPICAL CHARACTERISTICS
OUTPUT VOLTAGE
va
LINE INPUT VOLTAGE
I
Vcc=5V
Vref=2.5V
VI(S) =0
TA = 25°C
o
o
123
4
VI(L) - Une Input Voltage - V
Figure 2
1ExAs
~
INSIRUMENTS
POST OFFICE BOX 6553CX! • DALLAS, TEXAS 75265
-
5
VOH
'-._ _.Jl- __ VOL
Input pulses are supplied by generators having the following characteristics: PRR s 1 MHz, duty cycle s 50%, Zo = 50 n
Unused strobes are to be grounded.
CL includes probe and jig capacitance.
All diodes are 1N3064.
4
3.5V
1.5V
VOLTAGE WAVEFORMS
,
2-332
90%
10% 10%
10 ns
OV
'PI;IL(S)--/
tpLH(L)
1.--.1-,
,
"
NOTES: A.
B.
C.
D.
¥.
I
COMST.;.;R;;.B_'r-_ _-;.'_ _ _1_.5.V
-.I-_-'
,,
2.3 V
SN75140, SN75141
DUAL LINE RECEIVERS
SLLS08OA- 02155, JANUARY 1977 - REVISED FEBRUARY 1993
APPLICATION INFORMATION
----.
Strobe
5V
Twlsted·Pair Line
Data
I
I
Input -;---1
Strobil
OUT
I
I
I
I
Vret
1/2 SN75361 A
1/2 SN75140 /1/2 SN75141
Figure 3. Line Receiver
COMSTRB
Any
N=1
Series 54/74
Logic
1-'-".......:.......----+--1
1.5V
N =2 __----ll--~
N =74
SN75140/SN75141
_---1__--r-.
SN75140/SN75141
N = 75
t
t L..---I--t-I
Although most Series 54/74 circuits have a 2.4-Voutput at 400 jAA, they are typically capable of maintaining a 2.4-Voutput level under a load
of7.5 rnA.
Figure 4. High Fanout From Standard TTL Gate
INSlRUMENTS
1ExAs ""
POST OFFICE BOX 655303 • DALlAS, TEXAS 75265
2-333
SN75140, SN75141
DUAL LINE RECEIVERS
SLLS08OA- 02155, JANUARY 1977 - REVISED FEBRUARY 1993
APPLICATION INFORMATION
VCC=5V
5V
r-l------,
I
Data In
I
~L-.r-
AT (50 to 100 g
I
~TI~~~=-~-
__
depending
on line Impedance)
Data In Strobe -,,-----'"-------'
5V
Data Out
Vref = 1.5 Vto 3.5 V
Data Out Strobe - i - - - -..
I
I
I I
I
I
I I
II _ _ _ _ _ _ _ _ _ JI
1/2 SN75140 /1/2 SN75141
NOTE: Using this arrangement, as many as 100 transceivers can be connected to a single data bus. The adjustable reference voltage feature
allows the noise margin to be optimized for a given system. The complete dual bus transceiver, (SN75453B driver and SN75140 receiver)
can be assembled in approximately the same space required by a single 16-pin package and only one power supply is required (ll V).
Data In and Data Out terminals are TTL compatible.
Figure 5. Dual Bus Transceiver
VCC=5V
R1
Strobe
Signet - t - 4 - - I
Input
Figure 6: Schmitt Trigger
1ExAs ."
INSIRUMENTS
2--334
POST OFFICE BOX 65530G • OAUAS, TEXAS 75265
SN75140, SN75141
DUAL LINE RECEIVERS
SLLSOBOA- 02155, JANUARY 1977 - REVISED FEBRUARY 1993
APPLICATION INFORMATION
4
4
3.5
>I
3
I
2.5
•
I
>I
&
2
i
1.5
0
~
!5
12.
!5
0
3.5
I
R1 = 6.2 ka
R-r = 3.9 ka
RF=16ka
TA=25"C
!5
12.
!5
I
I
R1 =5.9kO
R-r=3.9 ka
RF = 5ka
TA=25"C
3
2.5
2
1.5
~
~
0.5
o
0.5
o
0.5
1
1.5
2
2.5
3
o
o
0.5
VI-Input Voltage - V
1.5
2
2.5
3
VI - Input Voltage - V
NOTE: Slowly changing input levels from data lines, optical detectors, and other types of transducers may be converted to standard TTL signals
wfth this Schmitt trigger circuit. R1 ' RF ,. and AT may be adjusted for the desired hysteresis and trigger levels.
Figure 7. Examples of Transfer Characteristics
COMSTRB
COMSTRB
):>-i-t-....- OUT
OUT
Vref
I
I
I
I
1--SN75140,isN75141IJ
R
Figure 8. Gated Oscillator
1ExAs ."
INSIRUMENTS
POST OFFICE BOX 655303 • DAUAS, TEXAS 75265
2-335
SN75140, SN75141
DUAL LINE RECEIVERS
'SUSOSOA- 02155, JANUARY 1977 - REVISED FEBRUARY 1993
APPLICATION INFORMATION
OSCILLATOR FREQUENCY
vs
RC TIME CONSTANT
40
20
~
~
I
I
...
I
10
-......
....
-...... I"I"- ....
7
I
I'--r-.
Vrllf=1.5V
-
I
l-
Vref = 2.5 V
4
RF = 15 kQ
tw =.!!:§
f
VCC=5V
TA=25°C
2
1
0.1
I I I II
0.2
0.4
0.7 1
2
4
RC Time Constant - f.III
Figure 9
1ExAs
,If
INSIRUMENrS
2-336
POST OFFICE BOX 655303 • DAUAS, TEXAS 75265
7
10
SN75146
DUAL DIFFERENTIAL LINE RECEIVER
FEBRUARY 1986- REVISED FEBRUARY 1993
SUS015A-
D8
D OR P PACKAGE
• Meets EIA Standards RS-422-A and
RS-423-A
(TOP VIEW)
• Meets EIA Standards RS-232 and CCITT
'1.28 With External Components
Vcc
10UT
20UT
GND
• Meets Federal Standards 1020 and 1030
• Built-In 5-MHz Low-Pass Filter
• Operates From Single 5-V Power Supply
• Wide Common-Mode Voltage Range
• High Input Impedance
• TTL-Compatlble Outputs
• 8-Pln Dual-In-Llne Package
7
6
5
lIN+
11N21N+
21N-
logic symbol t
11N+
• Pinout Compatible With the JAA9637 and
JAA9639
2
3
4
11N21N+
21N-
JJ'I>
8
7
6
5
description
"
"
]
V
2
10UT
3
20UT
t This symbol is in accordance with ANSVIEEE Std 91-1984and
IEC Publication 617-12.
The SN75146 is a dual differential line receiver
designed to meet EIA Standards RS-422-A and
logic diagram
RS-423-A. The receiver is designed to have a
constant impedance with inputvoltagesof:l:3 Vto
8
:1:25 V allowing it to meet the requirements of EIA
1IN+~
1OUT
7
JJ'
Standard RS-232-C and CCITT recommendation
11NV.28 with the addition of an external bias resistor.
6
This receiver is designed for low-speed operation
21N+~
20UT
5
.If
below 355 kHz and has a built-in 5-MHz lOW-pass
21Nfilter to attenuate high-frequency noise. The Inputs
are compatible with either a single-ended or a differential line system and the outputs are TTL compatible. This
device operates from a single 5-V power supply and is supplied in both the B-pin dual-in-line and small-outline
packages.
The SN75146 is characterized for operation from Q·C to 7Q·C.
Copyright @ 1993. Texaslnslrumenls Incorporated
1ExAs ."
INSIRUMENTS
POST OFFICE BOX 655303 • DALlAS. TEXAS 75265
2-337
SN75146
DUAL DIFFERENTIAL LINE RECEIVER
SLLSOl5A.., D2609. FEBRUARY 1986 - REVISED FEBRUARY 1993
schematics of Inputs and outputs
lYPlCAL OF ALL OUTPUTS
EQUIVALENT OF EACH INPUT
-,.-------<.--
VCC - - - -.....----t~- - - - - - -
R1
740 a NOM
Input
Vcc
soaNOM
7.41 A1
Output
7.4kaNOM
...--+-- -----740 a NOM
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, Vee (see Note 1) .............................................. -0.5 V to 7 V
Input voltage ............................................................................ :t25 V
Differential input voltage (see Note 2) .........................................•............. :t25 V
Output voltage range (see Note 1) ......................................... :-....... -0.5 V to 5.5 V
Low-level output current .................................................................. 50 rnA
Continuous total dissipation ............................................. See Dissipation Rating Table
Operating free-air temperature range .................................................. O°C to 70°C
Storage temperature range ....................................................... - 65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds .....................•......... 260°C
NOTES: 1. All voltage values. except differential Input voltage. are with respect to the network ground terminal.
2. Differential Input voltage Is measured at the noninverting input wfth respect to the corresponding Inverting Input.
DISSIPATION RATING TABLE
PACKAGE
o
p
=
TA" 25°C
POWER RATING
OPERATING FACTOR
ABOVE TA 25°C
TA 7O"C
POWER RATING
725 mW
1000 mW
5.8 mWrC
8.0 mWrC
464 mW
640 mW
=
recommended operating conditions
Supply voltage. VCC
MIN
NOM
MAX
UNIT
4.75
5
5.25
V
Common-mode input voltage. VIC
Operating free-air temperature. TA
0
1ExAs
..If
INSIRUMENfS
2-338
POST OFF1CE BOX 6515303 • DALLAS. TEXAS 75265
25
%7
V
70
°c
SN75146
DUAL DIFFERENTIAL LINE RECEIVER
SUSOl5A- 02609, FEBRUARY 1986 - REVISED FEBRUARY 1993
electrical characteristics over recommended ranges of supply voltage, common-mode Input
voltage, and operating free-air temperature (unless otherwise noted)
PARAMETER
v,-
Threshold voltage (VT + and
v,-...)
TYpt
MIN
TEST CONDITIONS
See Note 3
MAX
-0.2*
0.2
-0.4*
0.4
---1
(see
-
N;~ --],.5O%-----5O%-"'\1L.____
-o.5V--.J;
510
-
r..;;;.;-----,r---
~tpLH
fuv 1.,",
I
CL=30pF
3.92kO
~tpHL
Output
(eee Note A)
-----'.
VOH
' - - - - VOL
VOLTAGE WAVEFORMS
TEST CIRCUIT
NOTES: A. CL includes probe and jig capacitance.
S. The input pulse is suppUed by a generator having the following characteristics: tr 0; 5 ns, tf 0; 5 ns, PRR 0; 300 kHz, duty cycle = 50%.
Figure 1. Test Circuit and Voltage Waveforms
POST OFFICE BOX 655303 • DAUAS, TEXAS 75265
2-339
SN75146
DUAL DIFFERENTIAL LINE RECEIVER
SLLS015A- 02609, FEBRUARY 1.986 - REVISED FEBRUARY 1993
TYPICAL CHARACTERISTICS
OUTPUT VOLTAGE
4
vs
DIFFERENTIAL INPUT VOLTAGE
DIFFERENTIAL INPUT VOLTAGE
4
VCC=4.75V
TA=25°C
I
VIC=",7V
I
IVIC="'7V
I
I
I
I
I
V'f=O
I
-50
I
VIC =0
I
t
i
o
~
:
.I
3
>I
I
I
-100
VCC=5.25V
TA=25°C
I
I
o
OUTPUT VOLTAGE
vs
I
II
I
I
VIC =",7V I
I
2
VIC=",7V
I
~
I
I
I
I
VIC =1 0
I
o
:1
VIC=O
50
o
100
-100
VID - Differential Input Voltage - mV
-50
I
o
II
II
50
100
VID - Dlfferentlellnput Voltage - mV
Figure 2
Figure 3
APPLICATION INFORMATION
12V
5V
>----JL
1/2uA9636
-12V
(see Note A)
V
NOTE A: In order to meet the input-impedance and open-circuit-input voltage requirements of RS-232-C and CCITT V.28 and ensure
open-circuit-input fail-safe operation, R and V are selected to satisfy the following equations:
V - - 1.1 - 3.3
~
I
volts
R(rj)
3kDSR--S7kQ
+ rj
Figure 4. RS-232-C System Applications
1ExAs ."
INSIRUMENTS
2--'340
POST OFFICE. BOX 655303 • DAUAS. TEXAS 75265
SN75146
DUAL DIFFERENTIAL LINE RECEIVER
SUS015A- D2609, FEBRUARY 1986 - REVISED FEBRUARY 1993
APPLICATION INFORMATION
5V
1WIsted Pair
5V
1/2SN75148
5V
1/2SN75148
Figure 5. RS-422-A System Applications
1ExAs
..If
INSIRUMENTS
POST OFFICE BOX 655303 • DAUAS, TEXAS 75265
2-341
2-342
SN75150
DUAL LINE DRIVER
JANUARY 1971 - REVISED MARCH 1993
•
Satisfies Requirement of EIA Standard
RS-232-C
•
Withstands Sustained Output Short Circuit
to Any Low-Impedance Voltage Between
-25 V and 25V
•
S08
0, P, OR pst PACKAGE
(TOP VIEW)
2-1A8 Max Transition Time Through the 3-V
to -3-V Transition Region Under Full
25C1O-pF Load
•
Inputs Compatible With Most TTL Families
•
Common Strobe Input
•
Inverting Output
•
Slew Rate Can Be Controlled With an
External Capacitor at the Output
•
Standard Supply Voltages ... ± 12 V
1A
2A
GND
2
3
4
7
6
5
Vcc+
1Y
2Y
Vcc-
t The PS package Is only available left·end taped and reeled, i.e.,
order device SN75150PSLE.
logic symbol:!:
*
description
This symbol is in accordance wilh ANSI/IEEE Sid 91-1984
and IEC Publication 617-12.
The SN75150 is a monolithic dual line driver
designed to satisfy the requirements of the
standard interface be\Ween data terminal
equipment and data communication equipment as
defined by EIA Standard RS-232·C. A rate of
20000 bits per second can be transmitted with a
full 2500-pF load. Other applications are in
data-transmission systems using relatively short
single lines, in level translators, and for driving
MOS devices. The logic input is compatible with
most TTL families. Operation is from 12·V and
-12-V power supplies.
logic diagram (positive logic)
s
1A ,.,,2=---+--I
2A -"3=---_-1
The SN75150 is characterized for operation from
O·Cto 70·C.
1ExAs
,If
Copyright © 1993, Texas Instruments Incorporated
INSIRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
2-343
SN75150
DUAL LINE DRIVER
SUS081A- 0951. JANUARY 1971 - REVISED MARCH 1993
schematic (each line driver)
Vcc+---1~--'-------------------~~-----'--------------'
15kO
10kO
To Other
UneDriver
11 kO
InpulA --~-.
Strobe S --....-to. .~~-.t-l~.....-I
7kO
To Other
UneDrlver
15kO
4.5kO
GND - -. .------4~--~
To Other
UneDriver
To Other
UneDrlver
VCC----.-------------------------.--------~~--~~~
Resistor values shown are nominal.
1ExAs ."
INSIRUMENTS
2~44
POST OFFICE SOX 855303 • DAUAS. TEXAS 75265
OutputY
SN75150
DUAL LINE DRIVER
SUSOB1A- 0951, JANUARY 1971 - REVISED MARCH 1993
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vcc+ (see Note 1) .......................................................... 15 V
Supply voltage, Vcc- .................................................................... -15 V
Input voltage, VI .......................................................................... 15 V
Applied output voltage .................................................................... :t 25 V
Continuous total power dissipation ..................................... See Dissipation Rating Table
Operating free-air temperature range .................................................. O·C to 70·C
Storage temperature range ....................................................... -65·C to 150·C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds ............................... 260·C
NOTE 1: Voltage values are with respect to network ground terminal.
DISSIPATION RATING TABLE
PACKAGE
TAs25·C
POWER RATING
DERATING FACTOR
ABOVE TA = 25·C
TA=70·C
POWER RATING
0
725mW
5.8mwrc
464mW
P
1000mW
8.0mwrc
640mW
PS
450mW
3.6mwrc
288mW
recommended operating conditions
MIN
NOM
MAX
UNIT
Supply voltage, vcc+
10.8
12
13.2
V
Supply voltage, VCC-
-10.8
-12
-13.2
V
High-Ievet input voltage, VIH
2
5.5
V
Low-level input voltage, VIL
0
0.8
V
Applied output voltage, Vo
Operating free-air temperature, TA
0
POST OFFICE BOX 655303 • DAu.AS. TEXAS 75265
",15
V
70
·C
2-345
SN75150
DUAL LINE DRIVER
Su.s081A- 0951, JANUARY 1971 - REVISED MARCH 1993
electrical characteristics over recommended operating free-air temperature range. VCC:!: = ::1:13.2 V
(unless otherwise noted)
.
TEST CONDITIONS·
PARAMETER
VOH
High-level, output voltage
VCC+ = 10.8 V,
VIL=0.8V,
VOL
Low-Ievel output voltege (see Note 2)
VCC+ = 10.8 V,
VIH=2V,
IIH
High-level Input current
IlL
Low-level Input current
Data input
VCC- =-13.2V,
RL=3kO to7kO
VCC- =-10.8V,
RL=3kO to7kO
MIN
TYpt
5
8
-8
VI=2.4V
Strobe input
Data Input
VI=0.4V
Strobe input
ICCH+
Short-circuit output current*
Supply current from VCC+, high-level output
ICCH- . Supply current from VCC~ high-level output
ICCL+
Supply current from VCC +, low-level output
tCCL-
Supply current from VCC_ low-level output
VO=O,
VI=3V
VO=O,
VI=O
VI=O,
TA=25°C
RL=3kO,
VI=3V,
TA = 25°C
RL=3kO,
-5
1
10
2
20
-1
-1.6
-2
-3.2
2
8
-8
10
15
30
-10
-.15
-30
VO=-25V
UNIT
V
-3
VO=25V
lOS
MAX
10
22
-1
-10
8
17
-9
-20
V
IIA
mA
mA
mA
mA
t All typical values are at VCC+ = 12V, VCC_=-12V, TA = 25°C.
* Not more than one output should be shorted at a time.
NOTE 2: The algebraic corrvention, In which the less positive (more negative) limit is designated as minimum, is used In this data sheet for logic
levels only, e.g., when -5 V Is the maximum, the typical value Is a more negative voltage.
switching characteristics. Vcc+
=12 V. VCC- =-12 V. TA =25°C (see Figure 1)
PARAMETER
TEST CONDITIONS
ITLH
Transition time, low-to-high-Ievel output
ITHL
Transition time, hlgh,to-low-Ievel output
ITLH
Transition time, low-to-high-Ievel output
ITHL
tpLH
Transition time, hlgh-to-Iow-Ievel output
tPHL
Propagation delay time, high-to-Iow-Ievet output
2-346
Propagation delay time, low-to-high-level output
CL = 2500 pF,
RL=3kot07kO
CL=15 pF,
RL=7kO
CL=15 pF,
RL=7kO
IN~
POST OFFICE BOX 655303.· DALLAS, TEXAS 75265
MIN
TYP
MAX
0.2
1.4
2
0.2
1.5
2
",NIT
J.IS
J.IS
40
ns
20
ns
50
ns
45
ns
SN75150
DUAL LINE DRIVER
SllS081A-D951, JANUARY 1971-REVlSEDMARCH 1993 ,
PARAMETER MEASUREMENT INFORMATION
Pulse
Generator
(see Note A)
TEST CIRCUIT
~ ,,10
,,10 ns-,.----,
Input
ns
_..:1~0%:;:.,~"9O%"",","---9O%---5O%""~d~ l ~:- ---I"
50 fIS
-1
rOiI-tpHL
~I
~ tPLH ~
------3-V~~: ~
-3vK~
:,-3V
'THL -i4----J
::
tTLH
-l---.!
__
VOL
NOTES: A The pulse generator has the following characteristics: duty cycle" 50%, Zo - 50 Q.
B. CL includes probe and jig capacHance.
Figure 1. Test Circuit and Voltage Waveforms
1ExAs
,If
INSIRUMENIS
POST OFFICE BOX 655303 • DAUAS, TEXAS 75265
2-347
SN75150
DUAL LINE DRIVER
Su.soe1A- 0951, JANUARY 1971 - REVISED MARCH 1993
TYPICAL CHARACTERISTICS
OUTPUT CURRENT
va
APPLIED OUTPUT VOLTAGE
20
15
VCC + = 12V
VCC_=-12V
TA=25"C
10
VI=2.4V
r
I
!
~
U
i
o
-
5
0
~
-5
-
::::- :::"
~
...... .::::
t--
- RL=7ka
...... RL=3ka
I
.9
-10
)
-15
VI=0.4V
I
-20
-25 -20 -15 -10 -5 0
5
10 15
Vo - Applied Output Voltage - V
20
25
Figure 2
APPLICATION INFORMATION
Channel 1
Data Input
~-r_
Strobe
Channel 2 -.--..._
Data Input
_ MIL·STD·188C
Interfacee
Channel 2
Data Output
Hystereale - t - - - -..
Control
Channel 1
Data Output
Channel 1 Strobe
Figure 3. Dual-Channel Single-Ended Interface Circuit Meeting MIL-STD-188C, Paragraph 7.2.
'TExAs
.Jf.
INSIRUMENTS
2-348
POST OFFICE BOX 655303 • DAUAS, TEXAS 75265
SN75151, SN75153
QUAD DIFFERENTIAL LINE DRIVERS WITH 3·STATE OUTPUTS
1993
SN75151
OW OR N PACKAGE
(TOP VIEW)
•
Meets EIA Standard RS-422-A
•
High-Impedance Output State for
Party-Line Operation
•
High Output Impedance In Power.Qff
Condition
•
Low Input Current to Minimize loading
Vee
4A
4Y
4Z
4C
•
Single 5-V Supply
•
40-mA Slnk- and Source-Current Capability
•
High-Speed Schottky Circuitry
3C
3Z
3Y
•
Low Power Requirements
3A
S
description
SN75153
NPACKAGE
(TOP VIEW)
These line drivers are designed to provide
differential signals with high current capability on
balanced lines. These circuits provide strobe and
enable inputs to control all four drivers, and the
SN75151 provides an additional enable input for
each driver. The output circuits have active pullup
and pulldown and are capable of sinking or
sourcing 40 mA.
The SN75151 and SN75153 meet all
requirements of EIA Standard RS-422-A and
Federal Standard 1020. They are characterized
for operation from O°C to 70°C.
1 V 16
2
15
3
14
4
13
1A
1Y
1Z
CC
2Z
2Y
5
6
2A
GND
7
8
JVee
J 4A
4Y
4Z
12 S
11 3Z
10 3Y
9 3A
SN75153
NOT RECOMMENDED FOR NEW DESIGN
Function Tables
SN75151
SN75153
INPUTS
ENABLE
ENABLE
CC
C
OUTPUTS
STROBE
S
DATA
A
Y
Z
L
X
X
X
Z
Z
X
L
X
X
Z
H
H
H
H
L
X
L
Z
H
H
H
X
L
L
H
H
H
INPUTS
OUTPUTS
ENABLE
CC
STROBE
S
DATA
A
Y
Z
L
H
H
H
X
L
X
H
X
X
L
H
Z
L
L
H
Z
H
H
L
H
L
Copyright
e 1993, Texas Instruments Incorporated
1ExAs ."
INSIRUMENTS
POST OFFICE BOX 61515303 • DALlAS. TEXAS 75265
2-349
SN75151, SN75153
QUAD DIFFE.RENTIAlliNE DRIVERS WITH 3-STATE OUTPUTS
Sl.LS082A- 02453. DECEMBER '1978 - REVISED FEBRUARY 1993
logic symbols t
s
cc
1C
1A
2C
2A
3C
3A
4C
4A
15
5
4
1
6
SN75151
G1
,
s
CC
L,G2
2EN
1
I>
'il
'il
2
3
8
9
7
14
12
11
13
16
18
19
17
1Y'
1Z
'Z'f
2Z
3Y
3Z
4Y
4Z
,
1A
2A
3A
4A
12
4
1
7
9
15
1ExAs ~
INSIRUMENfS
2-350
POST OFFICE BOX 65S!03 • DAUAS. TEXAS 75265
I G1
L,EN
I>
1
V
'il
2
3
6
5
10
1Y
1Z
'Z'f
2Z
3Y
11
3Z
14
13
4Y
4Z
SN75151, SN75153
QUAD DIFFERENTIAL LINE DRIVERS WITH 3-STATE OUTPUTS
SLLS082A- 02453, DECEMBER 1978 - REVISED FEBRUARY 1993
schematic
To Three
Other Drivers
Strobe S
Input A
Common to One
Other Channel
r-"
VCC~--~~----~r---~r-----~~--~--~---r~+-----4r----~----~,
90
OutputZ
Resistor values shown are nominal.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) ............................................................. 7 V
Input voltage, VI .......................................................................... 5.5 V
Continuous total dissipation ............................................. See Dissipation Rating Table
Operating free-air temperature range .................................................. O·C to 70·C
Storage temperature range ....................................................... -65·C to 150·C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds ............................... 260·C
NOTES: 1. All voHage values, except differential output voHage VOD, are with respect to network ground 1erminal.
DISSIPATION RATING TABLE
PACKAGE
DW
N
TA s 25'C
POWER RATING
1125 mW
1150mW
OPERATING FACTOR
ABOVE TA 25'C
9.0 mWrC
9.2mWrC
=
TEXAS'"
INSIRUMENTS
POST OFFICE BOX 655303 • DAllAS, TEXAS 75265
TA =7O'C
POWER RATING
720 mW
736mW
2-351
SN75151, SN75153
QUAD DIFFERENTIAL LINE DRIVERS WITH 3-STATE OUTPUTS
Sl.LS082A- 02453, DECEMBER 1978 - REVISED FEBRUARY 1993
recommended operating conditions
Supply voltage, VCC
MIN
NOM
------
MAY
_.-.
4.75
5
5.25
-~
2
High-level Input voltage, VIH
V
V
Low-level Input voltage, Vil
-0.25
Common-mode output voltage, Voc
I liN'"
---..
O.B
V
6
V
High-level output current, 10H
-40
mA
Low-level output current, 10l
40
mA
70
·C
0
Operating free-alrtemperature, TA
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITlONSt
VIK
Input clamp voltage
VCC= MIN,
11=-12mA
VOH
High-level output voltage
VCC=MIN,
VIH= 2V
Vll= MAX,
VOL
Low-level output voltage
VCC=MIN,
IOl= 40 mA
Vll= MAX,
10=0
IV OD11
Differential output voltage
VCC=MAX,
1'10021
Differential output voltage
VCC=MIN
AlVoDI
Change In magnHude of differential
output voltage§
VCC=MIN
All others
-0.9
IOH=-20mA
2.5
IOH=-40mA
2.4
Vcc = MAX
AlVocl
Change In magnHude of commonmode output voltage§
VCC = MIN or MAX
10Z
Off-state (high-Impedance state)
output current
Vee = MAX,
3.4
.. 0.01
.. 0.4
1.B
3
1.6
3
.. 0.02
.. 0.4
-20
20
VO=VCC
20
0.1
100
-0.1
-100
Input current at maximum input
voltage
VCC=MAX,
VI =5.5V
IIH
High-level input current
VCC=MAX,
VI =2.4V
III
Low-level input current
VCC=MAX,
VI =0.4V
lOS
Short-circuH output current#
Vcc = MAX
ICC
*t
0.1
C(SN75151), A
20
ec,s
BO
e(SN75151), A
Supply current (both drivers)
Vcc = MAX,
-0.36
-1.6
CC,S
-50
No load
V
V
V
V,
V
V
J.iA
J.iA
.. 10O
Vo =-0.25 Vto 6 V
II
UNIT
V
VO=0.5V
VO=-0.25V
VCC=O
2VOD2
2.B
VO=2.5V
VO=6V
:
-1.5
0.5
VCC=MIN
Enable at O.B V
MAX
V
VIH=2V,
Rl= 100 0,
See Figure 1
Common-mode output voltage'll
Output current wHh power off
TYP*
-2
2
VOC
10
MIN
CC,S
-90
-150
Outputs disabled
30
60
Outputs enabled
60
60
mA
J.iA
mA
rnA
mA
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
All typical values are at TA = 25·C and Vce 5 V except for VOC, for which Vce is as stated under test conditions.
§ AlVoDI and AIVocl are the changes in magnitudes of VOD and Voe, respectively, that occur when the Input is changed from a high level to
a low level.
'II In EIA Standard RS-422-A, VOC, which Is the average of the two output voltages with respect to ground, Is called output offset voltage, VOS.
# Only one output should be shorted at a time, and duration of the short-circuit should not exceed one second.
=
1ExAs'" .
INSIRUMENIS .
2-352
POST OFFICE BOX 655303 • DALlAS, TEXAS 75265
SN75151, SN75153
QUAD DIFFERENTIAL LINE DRIVERS WITH 3·STATE OUTPUTS
SlLS082A- 02453, DECEMBER 1978 - REVISED FEBRUARY 1993
switching characteristics over recommended operating free-air temperature range, Vcc
(unless otherwise noted)
PARAMETER
n;ST cONDmoNS
tpLH
Propagation delay time, low-to-hlgh-level output
tpHL
Propagation delay time, high-to-Iow-Ievel output
tpLH
Propagation delay time, low-to-high-Ievel output
tpHL
Propagation delay time, high-to-Iow-Ievel output
trLH
Transition time, low-to-high-Ievel output
trHL
Transition time, high-to-low-Ievel output
TYpt
MAX
30
ns
ns
UNIT
CL=30pF,
See Figure 2,
RL= 1000,
Termination A
15
15
30
CL=30pF,
Termination B
See Figure 2,
13
25
ns
13
25
ns
CL=30pF,
See Figure 2,
RL= 1000,
Termination A
12
20
ns
12
20
ns
RL=600,
18
35
ns
20
35
ns
19
30
ns
13
30
ns
10
%
tpZH
Output enable time to high level
CL=30pF,
See Figure 3
tpZL
Output enable time to low level
CL=3OpF,
See Figure 4
RL= 1110,
tpHZ
Output disable time from high level
CL=3OpF,
See Figure 3
RL=600,
tpLZ
Output disable time from low level
CL=3OpF,
See Figure 4
RL= 1110,
RL=1000,
Termination C
See Figure 2,
Overshoot factor
MIN
=5 V
t All typical values are at TA = 25·C.
PARAMETER MEASUREMENT INFORMATION
i
500
VOD2
I
SOD
t
VOC
J-
Figure 1. Differential and Common·Mode Output Voltages
1ExAs ..,
INSIRUMENTS
POST OFFICE BOX 655303 • DAUAS, TEXAS 7526S
2-353
SN75151, SN75153
QUAD DIFFERENTIAL LINE DRIVERS WITH 3-STATE OUTPUTS
SLLS082A- 02453. DECEMBER 1978 - REVISED FEBRUARY 1993
PARAMETER MEASUREMENT INFORMATION
,...---,
1 kC
5 V ---'V\,f\r-....,
'--.----f-~-..L--
y Output
I-..-......----II----L_.A>-t--
Z Output
Pulse
Generator
(see Note A)
L ___
~
50C
y
y
Z
Z
TERMINATION B
TERMINATION A
TERMINATION C
TEST CIRCUITS
J+-25ns
~I
1
1
~ l!+---s5ns ~ 1
r-
s5ns
1 I I W + - - - - - 3V
~I
Input 1
IY Output
9O%~1
50%
1
90%
50%
110%
I
1 _10%
~I
tpLH
:1 50%)11 90%
110%
1
I
1
1
II!
1
~I
I-
tPHL
1
z Outp-ut--9O%-~-N. 50%
!\
1
---
k--
10%
1
l4-iTHL
OV
100%
tPHL
190%
VOH
1
I 50%
1 10%
1
1 I
VOL
1
l4--iTLH
--..
.
~I
101
1
I
I+- iTHL
1 ---+I
~I
I-
r
s:~
10%
tpLH
1
Iir1
--'
VOH
VOL
14-- iTLH
VOLTAGE WAVEFORMS
NOTES: A. The pulse generator has the following characteristics:
B. CL includes probe and jig capac~ance.
Zo =50 C. PRR s
10 MHz.
Figure 2. Test Circuits, Voltage Waveforms, and Overshoot Factor
1ExAs
~
INSIRUMENIS
2-354
POST OFFICE BOX 655303 • OAUAS. TEXAS 75265
SN75151, SN75153
QUAD DIFFERENTIAL LINE DRIVERS WITH 3-STATE OUTPUTS
SLLS082A- 02453, DECEMBER 1978 - REVISED FEBRUARY 1993
PARAMETER MEASUREMENT INFORMATION
Input
r-------,
Pulse
Generator
<_NoteA)
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
CL=30pF
(see Note S)
1\)---_.- Output
I
RL=60Q
'-~~~~----'-~-~I
CL=30pF
~ <_NoteS)
1
l ________________
1 kg
5V--...l
~
_____
1
1
~
TEST CIRCUIT
",5ns ~
:N+----
14--
,,5"& -.j
;it
1
l1 1 90%
Input
1
10%
50%
3V
1
90%
50%
1
1 10%
14--100ns-----.j ' - - - - OV
I4---*-tpZH
Iil
Output
14-
}
-----'.
1
1
1
1.5 V
-*
\--f.
VOH
I.! ~
tpHZ --l4--+I
Voff - 0 V
VOLTAGE WAVEFORMS
NOTES: A. The pulse generator has the following characteristics: Zo =50 g, PRR s 500 kHz.
B. CL includes probe and jig capacHance.
Figure 3. Test Circuit and Voltage Waveforms
1ExAs
~
INSIRUMENIS
POST OFFICE BOX 655303 • DAUAS, TEXAS 75265
2-355
SN75151, SN75153
QUAD DIFFERENTIAL LINE DRIVERS WITH 3-STATE OUTPUTS
Su.s082A- 02453, DECEMBER 1978 - REVISED FEBRUARY 1993
PARAMETER MEASUREMENT INFORMATION
Input
Pulse
Oenerator
(_Not.A)
5V
5V
RL=111 D
1 kD
·'1""0---.......1
Jt--!---~I------'
1
CL=30pF
1
1
1
li________________~~~~B~J
TEST CIRCUIT
14-- " 5 n.
1 1
~
--.!
Inp~ut::
10%
n.
9O%5O%~1---1
1+---100n.~
!
I+---+jtpZL
---~~I
Output
14- s 5
1 1
tpLZ
3V
10%
'----OV
~~I
1
1.5 V
.
5V
0,5 V
-'r
__L
\ o -_ _ _..J;...
VOL
VOLTAOE WAVEFORMS
NOTES: A The pulse generators have the. foUowing characteristics: Zo = 50 D, PRR s 500 kHz.
B. CL includes probe and jig capacitance.
Figure 4. Test Circuit and Voltage Waveforms
1ExAs
~
INSIRUMENTS
2-356
POST OFFICE BOX 6515303 • DAUAS. TEXAS 75265
Output
SN75151, SN75153
QUAD DIFFERENTIAL LINE DRIVERS WITH 3-STATE OUTPUTS
SLLS082A- 02453, DECEMBER 1978 - REVISED FEBRUARY 1993
TYPICAL CHARACTERISTICS
Y OUTPUT VOLTAGE
vs
DATA INPUT VOLTAGE
5
'I
No Load
TA=25°e
Vee=5.5V
4
Vee=5V
>
..
I
Vee=4.5V
co
~
3
5a.
5
2
~
0
I
~
o
o
2
VI - Data Input Voltaga - V
3
Figure 5
Y OR Z OUTPUT VOLTAGE
VS
ENABLE INPUT VOLTAGE
ENABLE INPUT VOLTAGE
4
Load = 470 Q to GND
TA=25°e
See Note A
>I
.
Y OR Z OUTPUT VOLTAGE
vs
3
6
Vee =5.5V
V~e=4.5V-
co
15a.
5
Vee=4.5V
>
..
co
Load 470 Q to Vee
TA=25°e
See Note A
Vee=5V
5
I
~
~
~
Vee=5.5V
V6e=5V
4
!!
;g
2
0
"5a.
5
3
I
2
0
I
~
~
o
o
2
VI - Enable Input Voltage - V
3
NOTE A: The A input is connected to Vee during the testing of the Y
outputs and to ground during testing of the Z outputs.
o
o
2
VI - Enable Input Voltage - V
3
NOTE A: The A input is connected to GND during the testing
ofthe Y outputs and to Vee during the testing ofthe
Zoutputs.
Figure 6
Figure 7
TEXAS ...,
INSIRUMENTS
POST OFFICE BOX 655303 • DAUAS, TEXAS 75265
2-357
SN75151, SN75153
QUAD DIFFERENTIAL LINE DRIVERS WITH 3-STATE OUTPUTS
SlLS082A- 02453. DECEMBER 1978 - REVISED FEBRUARY 1993
TYPICAL CHARACTERISTICS
HIGH-LEVEL OUTPUT VOLTAGE
HIGH-LEVEL OUTPUT VOLTAGE
vs
vs
FREE-AIR TEMPERATURE
OUTPUT CURRENT
4
6
>
I
VCC=5V
See Note A
>
5
I
8.
GI
I
~
~
~
.c01
X
3
~
4
5Q,
5
0
TA = 25°C
See Note A
IOH=-20mA
5Q,
5
IOH=-4OrnA
§
0
3
2
.c01
2
X
I
I
%
.p%
.p
o
o
10
20
30
40
50
60
70
TA - Free-Air Temperature _ °c
o ~~~~~~~~~--~~----~
o -10 -20 -30 -40 -50 -60 -70 -80 -90 -100
80
IOH - High-Level Output Current - rnA
FigureS
Figure 9
NOTE A: The A Input Is connected to Vee during the testing of the Y outputs and to ground during testing of the Z outputs.
LOW-LEVEL OUTPUT VOLTAGE
0.6
>I
t
~
i
o
)
LOW-LEVEL OUTPUT VOLTAGE
vs
vs
FREE-AIR TEMPERATURE
OUTPUT CURRENT
r---------,---r---,---r---,---,
VCC=5V
IOL= 40 rnA
0.5 I- See Note A -1---+---1----/----1---1
0.4
t--l----t---+---t----t---+----1f--I
0.3 t---I---+---I----/----I---+---II---I
0.2
1--1--+--+--1--+--+-----11--1
-!::~Z:~A
0.9
>I
GI
I
i
~
5Q,
5
0
~
0.8
1
0.7
0.6
VCC~4.~
0.5
0.4
~
0.3
0.1
t--l---t--+--t---t--+----1f--I
oJ
0.2
.p
~
~
A ~CC=5.5V
,~
I
oJ
.p
1.0
~
0.1
o ~~--~--~--~--~--~~~~
o
W
20
30
40
50
60
70
TA - Fr_Alr Temperature - °C
80
o
o
Figure 10
20
40
60
80
100
IOL - Low-Level Output Current - mA
Figure 11
NOTE A: The A Input Is connected to GND during the testing of the Y outputs and to Vee during the testing of the Z outputs.
1ExAs . "
INSIRUMENTS
2-358
POST OFFICE BOX 655303 • DAUAS. TEXAS 75265
120
SN75151, SN75153
QUAD DIFFERENTIAL LINE DRIVERS WITH 3-STATE OUTPUTS
SLLS062A- 02453, DECEMBER 1978 - REVISED FEBRUARY 1993
TYPICAL CHARACTERISTICS
SUPPLY CURRENT
SUPPLY CURRENT
vs
vs
SUPPLY VOLTAGE
SUPPLY VOLTAGE
80
80
A Inputs Grounde0
~
80
C
§
50
>ii.
Q.
40
::J
III
~
30
IV
U
20
2
C
50
u
40
§
>ii.
Q.
::J
III
I
I
J
Outputs Disabled
TA=25°e
/
30
h
I
U
E
No Load
Outputs Enabled TA=25°e
,/
o
~
60
l
d
:~n':;' Open or Grounded
I
I/'
II
10
o
V
~V A I~Puts Open
I
E
70 -
$
I
u
I
A
70
I
345
I
./
1/
V
2
3
20
V
V
10
I
678
o
./
o
4
5
6
7
8
Vee - Supply Voltage - V
Vee - Supply Voltage - V
Figure 12
Figure 13
1ExAs
~
INSIRUMENTS
POST OFFICE BOX 655303 • DAUAS, TEXAS 75265
2-359
2-360
SN75154
QUAD LINE RECEIVER
SLLS083A-
• Satisfies Requirements of EIA Standard
RS-232-C
• Input Resistance ••• 3 kC to 7 kC Over Full
RS-232-C Voltage Range
• Input Threshold Adjustable to Meet
Fail-Safe Requirements Without Using
External Components
• Built-In Hysteresis for Increased Noise
Immunity
• Inverting Output Compatible With TTL
• Output With Active Pullup for Symmetrical
Switching Speeds
• Standard Supply Voltages ••• 5 V or 12 V
NOVEMBER 1970-
0, N, OR NSt PACKAGE
(TOP VIEW)
3T
2T
1T
1A
2A
3A
4A
GND
1
V
2
3
4
5
6
~~
16
15
14
13
12
11
10
9
VCC2
VCC1
4T
1Y
2Y
3Y
4Y
Rfl:
t The NS package is only available left-end taped and reeled, I.e.,
order device SN75154NSLE.
:I: For function of R1, see schematiC
description
The SN75154 is a monolithic low-power Schottky line receiver designed to satisfy the requirements of the
standard interface between data terminal equipment and data communication equipment as defined by EIA
Standard RS-232-C. Other applications are for relatively short, single-line, point-to-point data transmission and
for level translators. Operation is normally from a single 5-V supply; however, a built-in option allows operation
from a 12-V supply without the use of additional components. The output is compatible with most TTL circuits
when either supply voltage is used.
In normal operation, the threshold-control terminals are connected to the VCC1 terminal, even if power is being
supplied via the alternate VCC2 terminal. This provides a wide hysteresis loop, which is the difference between
the positive-going and negative-going threshold voltages. See typical characteristics. In this mode of operation,
if the input voltage goes to zero, the output voltage will remain at the low or high level as determined by the
previous input.
For fail-safe operation, the threshold-control terminals are open. This reduces the hysteresis loop by causing
the negative-going threshold voltage to be above zero. The positive-going threshold voltage remains above zero
as it is unaffected by the disposition of the threshold terminals. In the fail-safe mode, if the input voltage goes
to zero or an open-circuit condition, the output will go to the high level regardless of the previous input condition.
The SN75154 is characterized for operation from O°C to 70°C.
logic symbol t
1A
1T
2A
2T
3A
3T
4A
4T
logic diagram
Jrt>
4
3
5
13
THRSADJ
2
6
1
7
14
12
11
10
1A
1Y
1T
2A
'Zf
2T
3A
3Y
3T
4A
4Y
4T
~
~
~
~
1Y
'Zf
3Y
4Y
14
t This symbol is in accordance with ANSVIEEE Sid 91-1984
and IEC Publication 617-12.
Copyright@ 1993, Texas Instruments Incorporated
1ExAs ."
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2-361
SN75154
QUAD LINE RECEIVER
SLLS083A- 0899. NOVEMBER 1970 - REVISED MARCH 1993
schematic
..-----------,I
Common to 4 Receiver•
VCC2t--------~-----.--__,
3.2kO
VCC1---------+-----.
R1----------t-~~_.
GND--------~~----r---_.
I
I
I
I
I
I
I
I
I
I
-------~
T11reahold
Control
1 of 4 Receiver.
-+__________-,
1.6kO
1.6kO
2000
Output
4.2kO
2.7kO
___________________________ J
Component values shown are nominal.
th ... Substrate
t When VCCl is used. VCC2 may be left open or shorted to VCC1. When VCC2 is used. VCCl must be left open or connected to the threshold
control pins.
1ExAs
~
INSIRUMENTS
2-362
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
SN75154
QUAD LINE RECEIVER
SLLS083A- 0899, NOVEMBER 1970- REVISED MARCH 1993
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Normal supply voltage, VCC1 (see Note 1) ..................................................... 7 V
Alternate supply voltage, VCC2 ............................................................. 14 V
Input voltage, VI ......................................................................... :t25 V
Continuous total power dissipation ..................................... See Dissipation Rating Table
Operating free-air temperature range .................................................. O°C to 70°C
Storage temperature range ....................................................... -65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds ............................... 260°C
NOTE 1: Voltage values are with respect to network GND terminal.
DISSIPATION RATING TABLE
PACKAGE
TAs25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
TA=70°C
POWER RATING
0
950mW
7.6mWrC
608mW
N
1150mW
9.2mWrC
736mW
NS
625mW
5.0mWrC
400mW
recommended operating conditions
Normal supply voltage, VCCl
Alternate supply voltage, VCC2
High-level input voltage, VIH (see Note 2)
Low-level input voltage, VIL (see Note 2)
MIN
NOM
MAX
4.5
5
5.5
V
10.8
12
13.2
V
3
15
V
-15
-3
V
High-level output current, IOH
Low-level output current, IOL
Operating free-air temperature, TA
..
.
..
..
UNIT
0
-400
IlA
16
mA
70
°c
NOTE 2: The algebr8lc convention, where the less posftlve (more negative) limit IS designated as minimUm, IS used In thiS data sheet for logic
and threshold levels only, e.g., when 0 V is the maximum, the minimum limit is a more negative voltage.
POST OFFICE BOX 655303 • DAUJ\S. TEXAS 75265
2-363
SN75154
QUAD LINE RECEIVER
SLLS083A- D899; NOVEMBER 1970-REVlSED MARCH 1993
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
TEST
FIGURE
PARAMETER
Normal operation
TEST CONDITIONS
Vr+
Posltlve-going threshold
voltage
Fall-safe operation
Vr-
Negative-going threshold
voltage
Fall-safe operation
Vhys
Hysteresis (\IT+- VT...)
VOH
High-level output voltage
1
10H = -400 !lA
VOL
Low-Ievel output voltage
1
10L= 16mA
rl
Normal operation
Normal operation
Fall-safe operation
Input resistance
Vl(open)
Open~lrcult
lOS
Short-circuit output current*
ICCI
Supply cU,rrent from VCCI
ICC2
Supply current from VCC2
1
1
1
2
input voltage
MIN
TYpt
MAX
0.8
2.2
3
0.8
2.2
3
-3
-1.1
0
0.8
1.4
3
0.8
3.3
6
0
0.8
2.2
2.4
3.5
V
V
V
V
0.29
0.4
7
AVI =-25Vto-14V
3
5
AVI=-14Vto-3V
3
5
7
AVI = -3 Vto 3 V
3
6
8
AVI=3VtoI4V
3
5
7
AVI = 14Vto25V
3
5
7
3
11=0
0
0.2
2
4
VCC1 =5.5V,
VI =-5V
-10
-20
-40
VCCI =5.5V.
TA = 25°C
20
35
VCC2 = 13.2 V.
TA=25°C
23
40
TYP
MAX
5
UNIT
V
kC
V
mA
mA
t All typical values are at VCCI = 5 V. TA = 25°C.
* Not more than one output should be shorted at a time.
switching characteristics, VCC1 = 5 V, TA = 25°C, N = 10
TEST
FIGURE
PARAMETER
TEST CONDITIONS
MIN
UNIT
tpLH
Propagation delay time. low-to-high-Ievel output
11
ns
tpHL
Propagation delay time. high-to-Jow-Ievel output
8
ns
ITLH
Transition time. low-to-high-Ievel output
7
ns
ITHL
Transition time. high-to-Iow-Ievel output
2.2
ns
2-364
6
CL=50pF.
IN~
POST OFFICE BOX 656303 • DAUAS. TEXAS 75265
RL=390C
SN75154
QUAD LINE RECEIVER
Su.s083A- 0899, NOVEMBER 1970- REVISED MARCH 1993
TYPICAL CHARACTERISTICS
OUTPUT VOLTAGE
vs
INPUT VOLTAGE
4
>I
VCC1 =5'{
TA=25D C
j
3
J
2
..
Normal .....
operatlj" _
..
See Note A
"
FIIlI-8afe ...
Operation
..
I
VT-
"
VT-
..
VT+
I
~
o
-25
-4
-3
-2
-1
o
VI -Input Voltage - V
2
3
4
25
NOTE A: For normal operation, the threshold controls are connected to VCC1. For fail-safe operation, the threshold controls are open.
Figure 1
1ExAs ."
INSlRUMENfS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2-365
SN75154
QUAD LINE RECEIVER
SLLS083A- 0899, NOVEMBER 1970 - REVISED MARCH 1993
PARAMETER MEASUREMENT INFORMATION
dc test circuitst
TEST TABLE
TEST
MEASURE
A
T
Y
VOH
Open
Open
IOH
VCC1
4.5V
VCC2
Open
VOH
Open
Open
IOH
Open
10.8V
VOH
0.8V
Open
IOH
5.5V
Open
VOH
0.8V
Open
IOH
Open
13.2V
VOH
Note A
VCC1
IOH
5.5 V and T
Open
VOH
Note A
VCC1
IOH
T
13.2V
VOH
-3V
VCC1
IOH
5.5 V and T
Open
VOH
-3V
IOH
T
13.2V
VOL
3V
VCC1
Open
IOL
4.5V
Open
VOL
3V
Open
IOL
Open
10.8V
VOL
3V
VCC1
IOL
4.5 V and T
Open
VOL
3V
VCC1
IOL
T
10.8V
VOL
NoteB
VCC1
IOL
5.5 VandT
Open
VOL
Note B
VCC1
IOL
T
13.2V
Open-circuit input (fail safe)
v,. + min, v,. _min (fail safe)
VT + min (normaO
VIL max, VT + min (normaQ
VIH min,
v,. + max, v,. _max (fail safe)
VIH min, VT + max (normaO
VT _ max (normal)
NOTES: A. Momentanly apply -5 V, then 0.8 V.
B. Momentarily apply 5 V, then GND.
t Arrows indicate actual direction of current flow. Current into a terminal is a positive value.
1ExAs .."
2...,'366
INSTRUMENTS
POST OFFICE BOX 655303 • DAUAS, TEXAS 75265
SN75154
QUAD LINE RECEIVER
SLLS083A- 0899, NOVEMBER 1970- REVISED MARCH 1993
PARAMETER MEASUREMENT INFORMATION
dc test circuitst (continued)
TEST TABLE
T
VCC1
SV
VCC2
Open
Open
GND
Open
Open
Open
Open
VCC1
TandSV
Open
Open
Open
~>---'--+-
Open
GND
GND
Open
Open
12V
Open
Open
GND
VCC1
T
12V
VCC1
T
GND
VCC1
T
Open
Figure 3. Input Resistance
5.
5V
TEST TABLE
1-jo--13.2V
T
VI (open)
_______Open
...1_,
VCC1
VCC2
R1 I
~
II >----~
~o_-y"--_+_- Open
l______ ~-----J
VCC1
S.SV
VCC2
Open
VCC1
S.SV
Open
Open
Open
13.2V
VCC1
T
13.2V
Open
Figure 4. Input Voltage (open)
5 . 5 V ] -lO--13.2V
ICC1
~
~ICC2
Open
Open
r- -- --- __1_.I
T
-5V
5V
Each output is tested separately.
VCC1
IA
VCC2
R1
Y
II
I
L _____
~ _____ J
Open
All four line receivers are tested simuttaneously.
Figure 5. Output Short-CIrcuit Current
Figure 6. Supply Current
t Arrows indicate actual direction of current flow. Current into a terminal is a positive value.
1ExAs'"
INSTRUMENTS
POST OFFICE BOX 655303 • DAUAS, TEXAS 75265
2-367
SN75154
QUAD LINE RECEIVER
SLLS083A- 0899, NOVEMBER 1970-REVISEO MARCH 1993
PARAMETER MEASUREMENT INFORMATION
Input
BV
Output
Open
Open
VCC2
Ri
__ l_L,
VCCi
(see Note C)
Pulse
G_ator
(see Note A)
L ___
GND _ _ _
I
J
--
::r
CL=50pF
(see Note B)
--
TEST CIRCUIT
~i0"2ne
~i0"2ns
,f
.Jt7:-~---13
Input
_ _ _ _i_O%_.
I
2V
~I
tnfL
tpLH
1/"":":2V~--- VOH
: . uv
:
j_ 0.8 V
Output
y
I
I....---I~....I -
1
tpHL!"
~=r-----------BV
---':-.i-::
---------::
tIl
i.5V
O.BV
I
+_______
~ 'TLH
-l.-J.
VOLTAGE WAVEFORMS
NOTES: A The pulse generator has the following characteristics: Zo = 50 Q, tw :s 200 ns, duty cycle :s 20%.
B. CL includes probe and jig capacitance.
C. All diodes are 1N3064.
Figure 6. Test Circuit and Voltage Waveforms
2~6B
1ExAs ."
INSTRUMENTS
POST OFFICE BOX 655303 • DAUAS. TEXAS 75265
VOL
SN75155
LINE DRIVER AND RECEIVER
MARCH 1993
• Meets EIA-Standard RS-232-C
• 10-mA Current Limited Output
• Wide Range of Supply Voltage
Vee = 4.5Vto 15V
• Low Power .•• 130 mW
• Built-In SOV Regulator
• Response Control Provides:
Input Threshold Shifting
Input Noise Filtering
• Power-off Output Resistance ••• 300 Q Typ
• Driver Input TTL Compatible
description
D OR P PACKAGE
TOP VIEW
vcc-Ds
vcc+
DA27DY
.RY
GND
6RTe
5 RA
logic symbol t
DA
RA
The SN75155 is a monolithic line driver and
receiver that is designed to satisfy the
requirements of the standard interface between
data terminal equipment and data communication
equipment as defined by EIA standard RS-232-C.
A response control input is provided for the
receiver. A resistor or a resistor and a bias voltage
can be connected between the response control
input and ground to provide noise filtering. The
driver used is similartothe SN75188. The receiver
used is similar to the SN75189A.
3
4
RTC
I>
2
5
1T
6
7
I>
3
RESP
DY
RY
t This symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12
logic diagram
The SN75155 is characterized for operation from
Q·C to 7Q·C.
Vcc-
S
VCC+ - - -.....--,
DA
---+--1
7
X ) - - DY
GND
RA - - - I .
3
RY
RTC _ _""":'...J
Copyright@ 1993. Texas Instruments Incorporated
1ExAs . "
INSIRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
2-369
SN75155
LINE DRIVER AND RECEIVER
SLLS017B - 02951. JULY 1986 - REVISED MARCH 1993
schematic
DA~2--------------------------------------,
VCC+~8~----~--~--------------------------~----.-~----,
600
7 DY
3000
RA
5
3.5kO
GND~4~----~--~~~--~~~+-~--~~~
RTC~6------------~
VCC_~1----------~~------~----+---------~~----+-----~
____________________________
~
~3
RV
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vcc+ (see Note 1) .......................................................... 15 V
Supply voltage, Vcc- (see Note 1) ......................................................... -15 V
Input voltage range: Driver. . .. . .. . .. . .. . .. .. . .. . . .. .. .. . .. . .. . . .. . .. .. .. . .. . .. . .. -15 V to 15 V
Receiver .................................................... -30 V to 30 V
Output voltage range (driver) ....................................................... -15 V to 15 V
Continuous total power dissipation ..................................... See Dissipation Rating Table
Operating free-air temperature range ..... :............................................ O·C to 70·C
Storage temperature range ....................................................... -65·C to 15O·C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds ............................... 260·C
NOTE 1: All voltage values are with respect to network ground terminal.
DISSIPATION RATING TABLE
PACKAGE
TAs25·C
POWER RATING
DERATING FACTOR
ABOVE TA = 25·C
0
725mW
5.8mwrc
464mW
P
1000mW
8.0mwrc
640mW
1ExAs . "
INSlR.UMENTS
2-370
TA=70·C
POWER RATING
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
SN75155
LINE DRIVER AND RECEIVER
SLLS017B - 02951, JULY 1986- REVISED MARCH 1993
recommended operating conditions
MIN
NOM
MAX
Supply voltage, VCC+
4.5
12
15
V
Supply voltage, VCC-
-4.5
-12
-15
V
Input voltage, driver, VICO)
-25
Input voltage, receiver, VI(B)
,.15
V
25
V
2
High-level input voltage, driver, VIH
V
Low-level voltage, driver, VIL
0.8
Response control current
Output current, receiver, IO(R)
Operating free-air temperature, TA
UNIT
0
V
,.5.5
mA
24
rnA
70
·C
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
total device
PARAMETER
ICCH+
ICCL+
High-level supply current
Low-level supply current
ICC+
Supply current
ICCH-
High-level supply current
ICCL-
Low-level supply current
TEST CONDITIONS
VCC+ = 5 V,
VCC_=-5V
VCC+=9V,
VCC_=-9V
VCC+ = 12V,
VCC_=-12V
VCC+=5V,
VCC_=-5V
VCC+=9V,
VCC_=-9V
VCC+ = 12V,
VCC_=-12V
VCC+=5V,
VCC-=O
VCC+ =9V,
VCC-=O
VCC+=5V,
VCC_=-5V
VCC+=9V,
VCC_=-9V
VCC+= 12V,
VCC_=-12V
VCC+=5V,
VCC_=-5V
VCC+=9V,
VCC_=-9V
VCC+ = 12V,
VCC_=-12V
MIN
VI(O) =2V,
VI(R) = 2.3 V,
Output open
VI(O) = 0.8 V,
VI(R) = 0.6 V,
Output open
VI(A) = 2.3 V,
VI (0) =0
VI(0)=2V,
VI(R) =2.3V
Output open
VI(O) = 0.8 V,
VI(R) = 0.6 V,
Output open
TYpt
MAX
6.3
8.1
9.1
11.9
10.4
14
2.5
3.4
3.7
5.1
4.1
5.6
4.8
6.4
6.7
9.1
-2.4
-3.1
-3.9
-4.9
-4.8
-6.1
-0.2
-0.35
-0.25
-0.4
-0.27
-0.45
UNIT
mA
mA
mA
mA
mA
t All typical values are at TA = 25·C.
1ExAs'"
INSTRl1MENIS
• DALlAS, TEXAS 7!!265
POST OFFICE BOX _
2-371
SN75155
LINE DRIVER AND RECEIVER
SLLS017B-D2951, JULY 1986- REVISED MARCfjl993
electrical characteristics over recommended operating free-air temperature range, VCC+
VCC- -12 V (unless otherwise noted)
.
=
=12 V,
driver section
PARAMETER
VOH
VOL
High-level output voltage
Low-level output vottage
(see Note 2)
MIN
TYpt
3.2
3.7
VCC_=-9V
6.S
7.2
VCC_=-12V
8.9
9.8
TEST CONDI110NS
VIL= 0.8 V, RL=3kQ
VIH =2\1,
RL=3kQ
MAX
UNIT
Vcc+ = S\l,
Vcc_=-SV
Vcc+ = 9\1,
VCC+= 12V,
Vcc+ = S\I,
VCC_=-SV
-3.6
-3.2
VCC+=9\1,
VCC-=-9V
-7.1
-6.4
VCC+=12\1,
VCC_=-12V
-9.7
-8.8
-0.73
-1.2
!lA
rnA
V
S
V
IIH
High-level input current
VI= 7 V
IlL
Low-level input current
VI=O
10S(Hl
High-level short-circuit
output current
VI =0.8V,
VO=O
-7
-12
-14.5
rnA
IOS(ll
low-level short-circuit
output current
VI=2V,
VO=O
6.5
11.5
15
rnA
ro
Output resistance
with power off
VO=-2Vto2V
Q
300
receiver section (see Figure 1)
MIN
TYpt
MAX
VT+
Positive-going threshhold voltage
1.2
1.9
2.. 3
V
VT-
Negative-going threshhold vottage
0.6
0.95
1.2
V
Vhys
Hystresis (VT+ - VT-l
4.1
4.5
PARAMETER
VO(H)
High-level output voltage
VOrL)
Low-level output vottage
IIH
High-level input current
IlL
Low-level input current
lOS
Short-circuit output current
TEST CONDI110NS
,
0.6
VCC-=-5V
3.7
V
VI = 0.6 V,
10H = 10!lA
VCC+=SV,
VCC+= 12\1,
VCC_=-12V
4.4
4.7
5.2
VI = 0.6\1,
10H = 0.4 rnA
VCC+ =5\1,
VCC-=-5V
3.1
3.4
3.8
VCC+ = 12\1,
VCC_=-12V
3.6
VI = 2.3\1,
IOL= 24 rnA
VI=25V
3.6
UNIT
V
4
4.5
0.2
0.3
V
6.7
10
rnA
VI= 3V
0.43
0.67
1
rnA
\Ii =-25V
-3.6
-6.7
-10
rnA
VI= -3V
-0.43
-0.67
-1
rnA
-2.8
-3.7
rnA
VI = 0.6V
t All typical values are at TA = 25"C.
NOTE 2: The algebraic limit system, in which the more positive Oess negative) limit is designated as maximum, is used in this data sheet for logic
voltage levels only, e.g., if-B.B Vis the maximum, the typical value is a more negative value.
2-372
POST OFFICE BOX 655303 • DAUAS. TEXAS 75265
SN75155
LINE DRIVER AND RECEIVER
SLLS017B-D2951, JULY 1986- REVIseD MARCH 1993
switching characteristics over recommended operating free-air temperature range, VCC+ = 5 V,
VCC- = -5 V, CL = 50 pF (unless otherwise noted)
driver section (see Figure 2)
PARAMETER
TEST CONDITIONS
tPLH
Propagation delay time, low-to-high level output
tpHL
Propagation delay time, hlgh-to-Iow level output
tr
Output rise time
tf
MIN
RL=3ka
RL=3ka
RL=3kato7ka,
CL=2500pF
RL=3ka
Output fall time
RL=3 kato7 ka,
CL=2500pF
TYpt
MAX
250
480
80
150
UNIT
ns
67
180
ns
2.4
3
j.I.8
48
160
ns
1.9
3
j.I.8
TYpt
MAX
175
245
37
100
receiver section (see Figure 3)
PARAMETER
TEST CONDITIONS
MIN
UNIT
tpLH
Propagation delay time, low-to-high level output
tpHL
Propagation delay time, high-to-Iow level output
tr
Output rise time
RL=400a
255
360
ns
tf
Output fall time
RL=400a
23
50
ns
RL = 400 a
ns
t All typical values are at TA = 25°C.
PARAMETER MEASUREMENT INFORMATION
VCC
{
vT,VI
!-IOH
Response
Control
i+IOL
VOH
1\
Open
Unless
Otherwise
Specified
1
ICC
VOL
fAc lAc
i::'-VC
'::'
.l +VC
'::'
1
'::'
1
'::'
'::'
Figure 1. Receiver Section Test Circuit (VT+. VT-. VOH. Vou
POST OFFICE BOX 655303 • DAUAS. TEXAS 75265
2--373
SN75155
LINE DRIVER AND RECEIVER
SLLS017B-D2951. JULY 1986-REVISED MARCH 1993
PARAMETER MEASUREMENT INFORMATION
1.5V
(see Note B)
Input
I
1.5 V
OV
,
,
I+-tpUf
I+-
CL=50pF
(aeeNoteA)
-1\s:.
,:i!:,
:
,
,
-toIt,
TEST CIRCUIT
VOH
VOL
~tfl4-
I+-
VOLTAGE WAVEFORMS
Figure 2. Driver Section Switching Test Circuit and Voltage Waveforms
Output
Reaponee
Control
5V
Input - - - ' 2 V
I (aeeNoteB)
Input
~;-----::
I
114-4--i_*-I- tPUf
tpHL-!
I
!I()%
, !I()%
I 1.~~
: I
10%
1.5'(
1- - -, -
~ tf 14TEST CIRCUIT
..- tr-.l
VOLTAGE WAVEFORMS
Figure 3. Receiver Section Switching Test Circuit and Voltage Waveforms
NOTES: A. CL includes probe and jig capacftance.
B. The input waveform is supplied by a generator with the following characteristics: Zo =50 C, tw
1ExAs ."
2-374
INSTRUMENTS
POST OFFICE BOX 655303 • DAUAS. TEXAS 75265
=1 lAS, tr "
VOH
10 ns, tf" 10 ns.
VOL
SN75155
LINE DRIVER AND RECEIVER
SLLS017B- 02951. JULY 1986- REVISED MARCH 1993
TYPICAL CHARACTERISTICS
(DRIVER)
OUTPUT CURRENT
vs
OUTPUT VOLTAGE
VOLTAGE TRANSFER CHARACTERISTICS
10
20
Vcc,.=,.12V
TA = 25°C
RL=3kO-
8
VCC,.=,.5V
-,-
r-IVCC~=.,tV
..
12
c(
E
!
4
U
0
!i
Do
!i -4
I
-8
-6
-12
-8
-16
-10
1.2
1.4
1.6
VI-Input Voltage - V
1.8
2
1
V
J _ ./
f
I
..,.,V
/
V
.......
3-kO
LoadUne -
I I
I I I
-20
-20 -16 -12 -8 -4 0
4
8
12
Vo - Output Voltage - V
16
20
SLEW RATE
va
vs
FREE·AIR TEMPERATURE
LOAD CAPACITANCE
1000
IJS(L)
c(
U
Ii
Figure 5
15
C
~
::I
I
II
J
Vec,. = ,.12V
I
SHORT-CIRCUIT OUTPUT CURRENT
I
II
.J. ~~
Figure 4
E
..., .......
1\ "
I
I
Ii I'---- ~
'f I....... L
V ""If
0
.9
IVI =0.8V
'I ....
VI=2V
::I
I
I
/'
If
8
I
VCC",=",5V
1
I I I
TA=25°C
16
10
VCC+ = 12V
VCC_=-12V
5 I- Vo=O
~
..........
400
h. Fall
-....:"
I"'~
r-Rlae
VCC+=12V
VCC_=-12V
TA=25°C
!i
Co
!i
0
.1::
0
::I
e
91:
-5
0
.c
1/1
~
4
IOS(H)
-10
VI=L
-15
o
10
20
30
40
50
60
TA - Free-Air Temperature - °c
70
1
10
100
1000
CL - Load Capacitance - pF
10000
Figure 7
Figure 6
1ExAs
~
INSIR.UMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
2-375
SN75155
LINE DRIVER AND RECEIVER
SLLS017B - D2951, JULY 1986- REVISED MARCH 1993
TYPICAL CHARACTERISTICS
(RECEIVER)
OUTPUT VOLTAGE
va
INPUT VOLTAGE
RC=3.9kO
VS=6V
5
RC=20kQ
VC=-6V
RJ=open
,
>I
i
i
I
_
4
VCC+=12V
VCC_=-12V
TA=25°C
3
VT+
2
~
VT+
VT-
o
-6
-4
Vr-
VT-
-3
-2
o
-1
VT+
2
3
5
4
VI -Input Voltage - V
Figure 8
OUTPUT VOLTAGE
va
INPUT VOLTAGE
Rc=10kO
VS .. 12V
5
>I
I
i
I
I- VCC+=12V
4
VCC_=-12V
TA=25°C
3
VT+
VT+
2
~
Vro
-5
-4
VT_
-3
-2
-1
o
Figure 9
1ExAs
~
IJII(SlRUMENTS
POST OFFICE BOX 656303 • DAUAS. TEXAS 75265
VT+
VT-
2
VI -Input Voltage - V
2-376
RC=20kQ
VC=-12V
RJ = Open
3
4
6
SN75155
LINE DRIVER AND RECEIVER
SLLS017B - 02951, JULY 1986- REVISED MARCH 1993
TYPICAL CHARACTERISTICS
(RECEIVER)
INPUT THRESHOLD VOLTAGE
INPUT CURRENT
vs
vs
FREE-AIR TEMPERATURE
INPUT VOLTAGE
3
I
10
I
VCC+=12V
VCC_=-12V _
2.5
..
CI
II
2
c(
I--
VT+
1.5
4
E
-
:t::
..,~
'0
.c
./
6
>
I
TA=25°C
VCC+=12V
VCC_=-12V
8
2
1:
!
::;
0
0
~
'S
.c
a.
.5
VT
I-
V
./
I
-2
I
'S
=
a.
.5
V
-4
-6
0.5
/
V
/
./
'"
V
-8
o
o
10
20
30
40
50
60
-10
-25 -20 -15 -10 -5
70
TA - Free-Air Temperature - °c
0
5
10
15
20
25
VI -Input Voltage - V
Figure 10
Figure 11
NOISE REJECTION
9
\\
8
>
.
7
\
I
CI
6
~
5
~
..,
'0
.c
I
4
'S
3
I-
a.
.5
\,
o
10
\
1\
\~
V
Cc = 1000 pF
Cc = 500 pF
Cc = 300 pF
Cc = 100pF
CC=10pF
)K
"- .......
100
I I IIIII
II
r'~
~
I IIIII
VCC+ = 12V
VCC_=-12V
TA=25°C
\ \
\
2
1\ ,
I
11111
,",
1000
10000
tw - Pulae Duration - na
Figure 12
ThxAs
~
INSIRUMENTS
POST OFFICE BOX 655303 • DAUAS, TEXAS 75265
2-!J77
2-378
SN75157
DUAL DIFFERENTIAL LINE RECEIVER
SEPlEMBER 1980- REVISED FEBRUARY 1993
• Meets EIA Standards RS-422-A and
RS-423-A
• Meets Federal Standards 1020 and 1030
• Operates From Single S-V Power Supply
• Wide Common-Mode Voltage Range
•
•
•
•
•
0, P OR pst PACKAGE
(TOP VIEW)
lIN+D8
2
7
lOUT
High Input Impedance
TTL-Compatlble Outputs
High-Speed Schottky Circuitry
8-Pln Dual-In-Llne Package
Similar to tJA9637AC Except for Corner Vee
and GND Positions
20UT
GND
6
5
l1N-
21N+
21N-
t The PS package is only available left-ended taped and reeled
(order SN75157PSLE).
logic symbol:!:
l1N+
l1N-
description
21N+
The SN75157 is a dual differential line receiver
designed to meet EIA Standards RS-422-A and
RS-423-A and Federal Standards 1020 and 1030.
It utilizes Schottky circuitry and has TTLcompatible outputs. The inputs are compatible
with either a single-ended or a differential-line
system. The device operates from· a single 5-V
power supply and is supplied in an a-pin
dual-in-line package and small outline package.
3
4
Vce
21N-
1
~J
7
1f1>
2
6
3
5
"
*
lOUT
20UT
This symbol is In accordance with ANSI/IEEE Std 91-1984
and lEe Publication 617-12.
logic diagram (positive logic)
The SN75157 is characterized for operation from
O·Cto 70·C.
liN +
l1N-
2IN +
21N-
~
~
7
.If
2 lOUT
5
.If
3 20UT
schematics of inputs and outputs
EQUIVALENT OF EACH INPUT
TYPICAL OF ALL OUTPUTS
Vcc
.-----.-~t--
Input
- ---
------------.----Vcc
sao NOM
--+---'I,NV--<.-.-------I
.........-~~----
Output
Current
Source
Copyright II:> 1993, Texas Instruments Incorporated
TEXAS . "
INSIRIJMENTS
POST OFFICE BOX 655303 • DALlAS. TEXAS 75265
2-379
SN75157
DUAL DIFFERENTIAL LINE RECEIVER
SlLS084A- D23OO, SEPTEMBER 1980 - REVISED FEBRUARY 1993
:
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, Vee (see Note 1) .............................................. -0.5 V to 7 V
Input voltage, VI ......................................................................... :!: 15 V
Differential input voltage (see Note 2) ....................................................... :!: 15 V
Output voltage range (see Note 1) ................................................. -0.5 V to 5.5 V
Low-level output current .................................................................. 50 mA
Continuous total dissipation ........................................... See Dissipation Rating Table
Operating free-air temperature range .................................................. O°C to 70°C
Storage temperature range ....................................................... -65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds ............................... 260°C
NOTES: 1. All voltage values, except differential Input voltage, are with respect to the network ground terminal.
2. Differential input voltage is measured at the noninverting input wfth respect to the corresponding Inverting input.
DISSIPATION RATING TABLE
TA .. 25°C
POWER RATING
OPERATING FACTOR
ABOVE TA = 25°C
D
725mW
5.8mWrC
464mW
P
1000mW
8.0mWrC
640mW
PS
450mW
3.6mWrC
288mW
PACKAGE
TA=70°C
POWER RATING
recommended operating conditions
Supply voltage, VCC
MIN
NOM
MAX
4.75
5
5.25
V
.,7
V
70
°C
Common-mode input voltage, VIC
Operating free-air temperature, TA
0
25
UNIT
electrical characteristics over recommended ranges of supply voltage, common-mode input
voltage, and operating free-air temperature (unless otherwise noted)t
PARAMETER
TEST CONDITIONS
MIN
Vr
Threshold voltage (VT + and Vr -l
Vhvs
Hysteresis
VOH
High-level output voltage
VID=0.2V,
10=-1 mA
VOL
loW-level output voltage
VID=-0.2V,
10~20
Input current
VCC =Oto5.5V,
See Note 4
II
See Note 3
TYP*
MAX
-0.2
0.2
-0.4
0.4
!VT + - Vr-l
70
2.5
mA
IVI=10V
IVI =-10V
lOS
Short-circuit output current§
VO=O,
VIC =0.2V
ICC
Supply current
VID =-0.5 V,
No load
-40
UNIT
V
mV
V
3.5
0.35
0.5
1.1
3.25
V
-1.6
-3.25
-75
-100
mA
35
50
mA
mA
.. (more-negative) limit..IS designated as minimum, IS used In thiS data sheet for threshold levels
t The algebraiC conventIOn, where the less-positive
only.
* All typical values are at VCC = 5 V, TA = 25°C.
§ Only one output should be shorted at a time and duration of the short cirCUit should not exceed one second.
NOTES: 3. The expanded threshold parameter is tested wfth a 500-0 resistor in series with each Input.
4. The input not under test Is grounded.
1ExAs
..If
INSIRUMENTS
2-380
POST OFFICE BOX 655303 • DAUAS, TEXAS 75265
SN75157
DUAL DIFFERENTIAL LINE RECEIVER
SLLS084A- 02300. SEPTEMBER 1980 - REVISED FEBRUARY 1993
switching characteristics, VCC
= 5 V, TA = 25°C
PARAMETER
MIN
TEST CONDITIONS
tpLH
Propagation delay time. low-to-high-Ievel output
tpHL
Propagation delay time. high-to-Iow-Ievel output
CL= 15 pF.
TYP
MAX
15
25
ns
13
25
ns
See Figure 1
UNIT
PARAMETER MEASUREMENT INFORMATION
VCC+
Output
VCC+
3920
Input
Input
(see Note B)
510
-1w. w.\
l..
~tPLH
CL = 15 pF
(see Note A)
-=-
3.92kO
Output
TEST CIRCUIT
- - - - O.SV
-0.5 V
I4---,.ItPHL
uv\
VOLTAGE WAVEFORMS
NOTES: A. CL includes probe and jig capac~ance.
B. The input pulse is supplied by a generator having the following characteristics: tr S 5 ns. tf S 5 ns. PRR S 5 MHz. duty cycle = 50%.
Figure 1. Test Circuit and Voltage Waveforms
TEXAS..If
INSlRUMENIS
POST OFFICE BOX 655303 • DALlAS. TEXAS 75265
2-381
SN75157
DUAL DIFFERENTIAL LINE RECEIVER
SLLS084A- D2300. SEPTEMBER 1980 - REVISED FEBRUARY 1993
TYPICAL CHARACTERISTICS
OUTPUT VOLTAGE
OUTPUT VOLTAGE
vs
vs
DIFFERENTIAL INPUT VOLTAGE
DIFFERENTIAL INPUT VOLTAGE
4
4
=
VCC = 4.75 V
TA = 25°C
VCC 5.25 V
TA= 25°C
1
>I
I
3
t
~
i
I
VIC=O
I
I
I
~
VIC=",7V
-100
-50
i
I
I
:
o
~
I VIC = ",7 V
VIC=O
VIC=O
i
II
2
VIC=",7V
~
:
o
I
I
I
I
IVIC .. ",7V
I
I
100
50
-100
U
vs
LOW-LEVEL OUTPUT CURRENT
0.6
4.5
;-
0
S
.c
CI
:f
I
:r::
~
4
>
0.5
t
0.4
I
3
;>
~
'"
2.5
2
1.5
"."\. I'\.
0.5
o
I
o
oi
~
"..
V
!
~
0.1
./
V
V
~
""
"
-10 -20 -30 -40 -50 -60 -70
IOH - High-Level Output Current - mA
-80
o
o
5
10
15
20
25
30
35
IOL - Low-Level Output Current - mA
Figure 4
Figure 5
. 1ExAs ~
2-382
V
./
0.3
0.2
I
VCC=5V
VIO=-0.2V
TA = 25°C
-
CD
......
100
LOW-LEVEL OUTPUT VOLTAGE
VCC=5V
VIO =O.2V
TA=25°C
3.5
50
Figure 3
5
II
0'
-50
VID - Olfferentlallnput Voltage - mV
HIGH-LEVEL OUTPUT VOLTAGE
VB
HIGH-LEVEL OUTPUT CURRENT
~
!i
I
I
II
Figure 2
:t::
VIC=O
I:
o
VIO - Oiffere!"iallnput Voltage - mV
>I
~
11
3
t
I
I
2
>I
1
INSIRUMENTS
POST OFACE BOX 6553~ • DALLAS. TEXAS 75265
40
SN75157
DUAL DIFFERENTIAL LINE RECEIVER
SLLS084A- 02300, SEPTEMBER 1980 - REVISED FEBRUARY 1993
TYPICAL CHARACTERISTICS
SUPPLY CURRENT
va
SUPPLY VOLTAGE
100
NoLoad I
90
c(
E
80
I
70
I
60
U
~
Q,
50
::I
40
U
30
Ul
I
InpulBOpen
TA=25"C
V
V
~
20
10
o
o
,.., / '
/'
/
234
5
6
7
8
VCC - Supply Voltage - V
Figure 6
APPLICATION INFORMATION
5V
TwIsted PaIr
5V
5V
Figure 7. RS-422-A System Applications
1ExAs
..If
INSIRUMENTS
POST OFFICE BOX 655303 • DAllAS, TEXAS 75265
2-383
2--384
SN75158
DUAL DIFFERENTIAL LINE DRIVER
JANUARY 19n - REVISED MARCH 1993
SLLS085A-
•
•
•
•
•
•
•
•
•
Meets EIA Standard RS-422·A
Single S·V Supply
Balanced·Llne Operation
TTLCompatlble
High Output Impedance In Power·Off
Condition
High-Current Actlve·Puliup Outputs
Short-CIrcuit Protection
Dual Channels
Input Clamp Diodes
D, pst, OR P PACKAGE
(TOP VIEW)
1zD8 Vcc
1Y
1A
GND
2
3
4
7
6
5
2Z
2Y
2A
t The PS package is only available left-end taped and reeled, I.e.,
order SN75158PSLE.
description
The SN75158 is a dual differential line driver designed to satisfy the requirements set by the EIA Standard
RS-422-A interface specifications. The outputs provide complementary signals with high-current capability for
driving balanced lines, such as twisted pair, at normal line impedance without high power dissipation. The output
stages are TTL totem-pole outputs providing a high-impedance state in the power-off condition.
The SN75158 is characterized for operation from Q·C to 7Q·C.
logic symbol t
logic diagram (positive logic)
2
1A
2A
3
1A
1Y
~1 1Z
2A
~7 2Z
6~
5
t This symbol is in accordance wRh ANSVIEEE SId
and IEC Publication 617-12.
91-1984
schematics of inputs and outputs
EQUIVALENT OF EACH INPUT
VCC --~~---.--
TYPICAL OF ALL OUTPUTS
---'---VCC
4kO
NOM
Input
GND
90NOM
'---Output
-~~----.--
---+---GND
TEXAS
~
Copyright@ 1993, Texas Instruments Incorporated
INSIRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2-385
SN75158
DUAL DIFFERENTIAL LINE DRIVER
SLLS085A~ D2292, JANUARY 1977 - REVISED MARCH 1993
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, vee (see Note 1) .........................................•................... 7 V
Input voltage, VI .......................................................................... 5.5 V
Continuous total power dissipation ..................................... See Dissipation Rating Table
Operating free-air temperature range .................................................. O·C to 70·C
Storage temperature range ....................................................... -65·C to 150·C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds ............................... 260·C
NOTE 1: All voltage values except differential output voltage VOO are with respect to network ground terminal. VOO is at the Y output with respect
to the Z output.
DISSIPATION RATING TABLE
PACKAGE
TA" 25°C
POWER RATING
DERATING FACTOR
ABOVE TA 25°C
=
=
TA 70°C
POWER RATING
o
725 mW
5.8 mwre
464 mW
p
1000mW
8.()mWre
640mW
450 mW
3.6 mwre
288 mW
PS
\
recommended operating conditions
Supply voltage, Vee
High-level Input voltage, VIH
MIN
NOM
MAX
UNIT
4.75
5
5.25
V
2
Low-level input voltage, VIL
High-level output current, IOH
Low-level output current, IOL
Operating free-air temperature, TA
0
1ExAs
~
INSIRUMENTS
·2-386
POST OFFICE BOX 655301! • DALLAS. TEXAS 75l!65
V
0.8
V
-40
mA
40
mA
70
°e
SN75158
DUAL DIFFERENTIAL LINE DRIVER
SLlS086A- D2292, JANUARY 1977 - REVISED MARCH 1993
electrical characteristics over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONSt
MIN
TVP:I:
MAX
UNIT
-0.9
-1.5
V
Input clamp voltage
VCC = MIN,
II =-12mA
VOH
High-level output voHage
Vee = MIN,
VIH=2V,
VIL = 0.8 V,
IOH =-40 mA
VOL
Low-level output voltage
VCC = MIN,
VIH =2V,
VIL=0.8V,
10L= 40mA
0.2
0.4
I VODll
Differential output voltage
VCC = MAX,
10=0
3.5
2VOD2
IV OD21
Differential output voltage
VCC=MIN
,WOD
Change in magnRude of differential output voltage!i
VCC=MIN
VIK
2
VCC = MAX
VOC
Common-mode output voHage~
I1VOC
Change in magnitude of common-mode output
voltage§
VCC=MIN
or MAX
10
Output current wHh power off
VCC=O
2.4
Vce=MIN
RL= 1000,
See Figure 1
VO=6V
VO=-0.25V
3
V
3
V
V
V
.,0.02
.,0.4
1.8
3
1.5
3
.,0.02
.,0.4
0.1
100
-0.1
-100
V
V
V
).IA
.,100
VO=-0.25to 6V
II
Input current at maximum input voltage
VCC = MAX,
VI =5.SV
1
IIH
High-level input current
VCC = MAX,
VI=2.4V
40
).IA
IlL
Low-level input current
VCC = MAX,
VI=0.4V
-1
-1.6
mA
lOS
Short-circuH output current#
VCC=MAX
-90
-150
mA
Supply current (both drivers)
VCC = MAX,
No load,
37
50
mA
ICC
-40
Inputs grounded,
TA=2S·C
mA
t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating condHions.
:I: All typical values are at VCC = 5 V and TA = 25·C except for VOC, for which Vec is as stated under test conditions.
§ 11 VOD and I1IVocl are the changes in magnHudes ofVOD andVoc, respectively, that occur when the input Is changed from a high level to a low
level.
11 In EIA Standard RS-422-A, VOC, which is the average of the two output voHages with respect to ground, Is called output offset voltage, VOS.
# Only one output should be shorted at a time, and duration of the short circuH should not exceed one second.
switching characteristics,
Vee =5 V, TA =25°C
PARAMETER
TEST CONDITIONS
tpLH
Propagation delay time, low-to-high-Ievel output
tpHL
Propagation delay time, high-to-Iow-Ievel output
tpLH
Propagation delay time,low-to-high-level output
tpHL
Propagation delay time, hlgh-to-Iow-Ievel output
ITLH
TransHlon time, low-to-high-Ievel output
ITLH
Transition time, high-to-Iow-Ievel output
Overshoot factor
See Figure 2, Termination A
See Figure 2, Termination B
See Figure 2, Termination A
See Figure 2, Termination C
1ExAs
MIN
UNIT
TVP
MAX
16
25
ns
10
20
ns
13
20
ns
9
15
ns
4
20
ns
20
ns
4
10%
-If
INSIRUMENIS
POST OFFICE BOX 655303 • DAllAS, TEXAS 75265
2-387
SN75158
DUAL DIFFERENTIAL LINE DRIVER
SLlS085A- 02292, JANUARY 1977 - REVISED MARCH 1993
PARAMETER MEASUREMENT INFORMATION
Figure 1. Differential and Common-Mode Output Voltages
Input
YOutput
Pulse
Generator
(see Note A)
I
Y ---------,
CL=15PF-.l
(see Note B)
Y
Z
CL=30pF
(see Note B)
1000
ZOutput
CL=15pF
(see Note B)
Z
l:::r::
TERMINATION B
TERMINATION A
TERMINATION C
TEST CIRCUIT
.. 5 ns -+I
-+'
I+-
1 1
LIt
1+- .. 5 ns
1 1
!1:;'-~90%=-~90~%~~""'!1- - - - - -
Inp~
1
50%
50%
:ifi
1 1 9O%
1 1
k-
.
t~-~
,~tPHL
tPLHn
tTLH - '
~~
'-fj .J~
OV
IX-10%
1
I
Differential
I 50%
OutP_ut_ _
10%.....,;j[
Overshoot
3V
90%1\1
1 50%
~10%
_ __
i
1 1
-+I I.- tTHL
Overshoot
VOLTAGE WAVEFORMS
NOTES: A. The pulse generator has the following characteristics: Zo = 50 0, tw = 25 ns, PRR .. 10 MHz.
B.. CL includes probe and jig capacitance.
Figure 2. Test Circuit and Voltage Waveforms
TEXAS
~
INSIRUMENTS
2-388
POST OFFICE eox 655303 • DAUAS, TEXAs 75265
SN75158
DUAL DIFFERENTIAL LINE DRIVER
Su.s085A - D2292, JANUARY 19IT - REVISED MARCH 1993
TYPICAL CHARACTERISTICS
OUTPUT VOLTAGE
OUTPUT VOLTAGE
va
va
DATA INPUT VOLTAGE
DATA INPUT VOLTAGE
6
6
No Load
TA=25°C
5
5
>
r
4
'S
Q.
3
~
I
f
VCC=5V
i
VCC =4.5V
'5
0
I
I
2
J'
o
J'
o
2
TA=125°C
/
>
VCC=5.5V
I
til
Vcc l=5V
No Load
3
4
~
3
Figure 4
LOW-LEVEL OUTPUT VOLTAGE
HIGH-LEVEL OUTPUT VOLTAGE
va
va
OUTPUT CURRENT
OUTPUT CURRENT
0.4
5
TA=25°C
til
---
4
3
0
)
TA=25°C
_I
~
~
'5
Q.
'5
I
>
VCC=5.5V
"""'-
-........ ..........
-.......... ...........
2
01
:i:
I
_1_
VCC=5.5V A
I
J V~C=5V
-"""'bZ..,
--....... ~,
til
01
1\1
0.3
~
'5
Q.
'5
r
r-.....'
VCC~4.5V \
0
~li
.9
I
I
::t:
...I
0.2
~
0.1
.p
J'
o
4
2
3
VI- Data Input Voltage - V
4
Figure 3
01
TA = 25°C
TA=-55°C
2
VI- Data Input Voltage - V
>I
~\
\
o
-40
-60
-80
A
,.
I
VCC=4.5V
V
V
~\
-20
/
V
/
V
~
-100
-120
o
o
10
IOH - Output Current - mA
20
30
40
50
60
70
80
IOL - Output Current - mA
Figure 6
Figure 5
1ExAs
,If
INSIRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
2--389
SN75158
DUAL DIFFERENTIAL LINE DRIVER
SLLS085A- 02292. JANUARY 1977 - REVISED MARCH 1993
TYPICAL CHARACTERISTICS
PROPAGATION DELAY TIMES
OUTPUT VOLTAGE
4
30
I I t
-
VOH(lOH = -20 mA)
I
~
CD
VOH(IOH
2.5
~ -40 mA)
!
25
Vee=5V
See Figure 2
Termination A
I
:!
e
F
20
~
11
~
!i
a.
!i
I
FREE-AIR TEMPERATURE
3
>
0
va
FREE-AIR TEMPERATURE
Ve~=5~
3.5
,
va
C
2
c
15
a.
10
iIi'
1.5
e
IL
~
tpLH
i--
~
tpHL
I
J
0.5
-75
5
-50 -25
0
25
75
50
100
o
125
-75
-50 -25
TA - Free-Air Temperature -·e
60
E
~
50
vs
vs
SUPPLY VOLTAGE
FREE-AIR TEMPERATURE
42
I
TA=25·e
:I
In
I
U
E
iit:
~
Inputs Grounded
.!
I
30
>-
1:
./
36
!1l
I
u
34
E
/
o
..............
:I
Inputs Open -
20
38
U
V Xr\
40
10
32
" ""
',I'
2
3
4
5
6
7
8
30
-75
-50
-25
0
25
50
75
TA - Free-Air Temperature -·e
Vee - Supply Voltage - V
Figure 9
Figure 10
1ExAs
~
INSIRUMENIS
2-{390
125
e
I
o
100
c:(
:I
i
I
Vee=6V
_ Input Grounded
40
Outputs Open
I
U
75
50
SUPPLY CURRENT
(BOTH DRIVERS)
80
NolLoad
25
Figure 8
SUPPLY CURRENT
(BOTH DRIVERS)
70
0
TA - Free-Air Temperature - ·e
Figure 7
e
~
VOL(IOL = 40 mA)
o
c:(
---
..........
V
POST OFFICE BOX 655303 • DAUAS. TEXAS 75265
"
100
125
SN75158
DUAL DIFFERENTIAL LINE DRIVER
SLLS085A- 02292, JANUARY 19n - REVISED MARCH 1993
TYPICAL CHARACTERISTICS
SUPPLY CURRENT
(BOTH DRIVERS)
va
FREQUENCY
100
,
1
VCC=5V
~ RL=
80
00
CL=30pF
Inputs: 3-V Square Wave
TA=25"C
I
60
::I
~
0
~
Q.
::I
1/1
I
V"
40
0
E
20
o
0.1
0.4
4
10
40
100
f - Frequency - MHz
Figure 11
1ExAs
..If
INSIRUMENfS
POST OFFICE BOX 655303 • DAUAS. TEXAS 75265
2-391
2-392
SN75159
DUAL DIFFERENTIAL LINE DRIVER
WITH 3-STATE OUTPUTS
JANUARY 1977 - REVISED FEBRUARY 1993
•
•
•
•
•
•
•
•
•
D OR N PACKAGE
Meets EIA Standard RS-422-A
Single S-V Supply
Balanced Line Operation
TTL Compatible
High-Impedance Output State for
Party-Line Applications
High-Current Actlve-Pullup Outputs
Short-Circuit Protection
Dual Channels
Clamp Diodes at Inputs
(TOP VIEW)
NC
1Z
Vcc
2Z
2Y
28
2A
2EN
NC-No internal connection
description
The SN75159 dual differential line driver with 3-state outputs is designed to provide all the features of the
SN75158 line driver with the added feature of driver output controls. There is an individual control for each driver.
When the output control is low, the associated outputs are in a high-im pedance state and the outputs can neither
drive nor load the bus. This permits many devices to be connected together on the same transmission line for
party-line applications.
The SN75159 is characterized for operation from O·C to 70·C.
logic symbol t
logic diagram (positive logic)
&1>
lEN 6
lA 4
18 5
2EN 9
2A 10
28 11
1EN
EN
'---~--Output
6V
1
I
I
kQ
' - - . -_ _ _---1
I
I
I
I
CL=30pF
(_Note B)
-=
I
1
I
fL-------------------J
TEST CIRCUIT
_
-.I
I
14-..s ns
I
~
I+- s5 ns
I
iL~
I
~Y'-r-----
1J~100nslX10%
OV
I
I
I
'I
j4-tpZL*
I
I
I
--
3'
I
\..
k-tPL2~
Y-T
.
5V
---f VOL
VOLTAGE WAVEFORMS
NOTES: A. The pulse generator has the following characteristics: Zo = 50 Q, PRR s 500 kHz.
B. CL includes probe and jig capacRance.
Figure 4. Test Circuit and Voltge Waveform
1ExAs
~
INSTRUMENTS
2-400
POST OFFICE BOX 655303 • DALlAS, TEXAS 75265
SN75159
DUAL DIFFERENTIAL LINE DRIVER
WITH 3-STATE OUTPUTS
SLLS088A- 02325, JANUARY 1977 - REVISED FEBRUARY 1993
TYPICAL CHARACTERISTICS
OUTPUT VOLTAGE
VB
DATA INPUT VOLTAGE
OUTPUT VOLTAGE
vs
DATA INPUT VOLTAGE
6
6
No load
TA = 25°C
VCC=5V
No Load
5
5
r
>
..
I
4
I
~
:;
Co
:;
I
I
'<;
3
I
\ ~VCCi5V
\
0
I
I
2
..?
o
..?
~ 4.75 V
\...- VCC
IrTA =70oe
>
VCC =5.25V
ti
4
"It
3
2
3
4
VCC=5V
VOH (IOH =
3.5
CI
.
~
~
4
Figure 6
HIGH-LEVEL OUTPUT VOLTAGE
va
HIGH-LEVEL OUTPUT CURRENT
5
2~mA)
TA=25"C
VOH(IOH= 4OmA)
4
>I
8.
2.5
~
3
i
2
~
2
Co
0
3
VI - Data Input Voltage - V
~
~
I~TA=Oo~
2
0
4
OUTPUT VOLTAGE
VB
FREE-AIR TEMPERATURE
..
I\...-TA = 25°e
~I
0
o
Figure 5
>I
"\
\
2
VI- Data Input Voltage - V
3
"
0
1.5
I
I
:t
.p
..?
0.5
o
VOL (IOl = 40 mAl
o
25
75
50
o'--_....L._--'_ _..J...._.....L........._ . L - _ . . . J
o
-20
-40
-60
-80
-100
-120
TA - Free·Air Temperature - C
IOH - Output Current - mA
FIgure 7
Figure 8
1ExAs ..,
INSIRUMENTS
POST OFFICE BOX 665303 • OAUAS, TEXAS 75285
2-401
SN75159
DUAL DIFFERENTIAL tiNE DRIVER
WITH 3-STATE OUTPUTS
Su.s088A- 02325, JANUARY 1977 - REVISED FEBRUARY 1993
TYPICAL CHARACTERISTICS
SUPPLY CURRENT
(BOTH DRIVERS)
LOW-LEVEL OUTPUT VOLTAGE
0.6
vs
vs
LOW-LEVEL OUTPUT CURRENT
SUPPLY VOLTAGE
80
I
~
TA=25·e
0.5
>I
I
'!5
~
Vee=4.7~
0.4
0.3
0
I
...I
~
..d-
0.2
0.1
o
V
o
/
~
#
~
~
N~Loadl
70 f- TA=25·e
~
60
C
~
:l
50
b
40
I
U
:l
1/1
I
V"
~
, ~Puts
..
~
30
Open
20
10
20
40
60
80
100
o
120
/'
o
I
C
I!!
!i
48
u
~
Q.
:l
1/1
I
U
E
5
678
Figure 9
Figure 10
SUPPLY CURRENT
(BOTH DRIVERS)
SUPPLY CURRENT
(BOTH DRIVERS)
vs
vs
FREE-AIR TEMPERATURE
FREQUENCY
100
Vec=5V
Inputs Grounded
NoLoed
52
50
I
Vec - Supply Voltage - V
56
~
/
234
IOL - Output Current - mA
54
A~
~~
\
8:
VCC=5.25V
A
Inputs
Grounded
80
~
I
vce=5V'1I1
RL=co
CL=3OpF
Input: 3-V Squere Wave
TA=25"C
I
C
I!
!i
----
46
44
42
I
60
/
u
bQ.
Q.
:l
1/1
I
U
40
E
40
20
38
36
o
25
75
50
o
0.1
TA - Free-Air Temperature - ·C
4
.10
f - Frequency - MHz
Figure 11
Figure 12
1ExAs,lf
INS1R.UMENfS
2-402
0.4
POST OFFICE BOX 655303 • DAUAS. TEXAS 75265
40
100
SN75159
DUAL DIFFERENTIAL LINE DRIVER
WITH 3-STATE OUTPUTS
SUSOS8A- 02325, JANUARY 1977 - REVISED FEBRUARY 1993
TYPICAL CHARACTERISTICS
PROPAGATION DELAY TIMES
FROM DATA INPUTS
.
c
I
!l
16
Q.
.5
II
1ii
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
20
18
tpLH
14
Q
E
...e
.
OUTPUT ENABLE AND DISABLE TIMES
vs
12
---
30
I!
I
E
1=
III
I
i
E
1=
~
'ii
Q
8
I
l!!
w
6
4
II.
2
o
i
VCC=5V
CL=30pF
RL=100Q
Q.
e
20
o
25
50
o
75
-
tpU
r-
15
tpZL
III
li
c
0
25
I
tpHL
10
I
VCC=5V
See Figures 3 and 4
tpHZ
10
tpZH
5
o
o
TA - Free-Air Temperature - ·C
25
50
75
TA - Free-Air Temperature _·C
Figure 13
Figure 14
TEXAS
,If
INSIRI.JMENfS
POST OFFICE BOX 655303 • DALlAS. TEXAS 75265
2-403
2-404
SN75160B
OCTAL GENERAL-PURPOSE
INTERFACE BUS TRANSCEIVER
SLl.SOO4A-
OCTOBERl985-R8nSEDFEBRUARY1~
MEETS IEEE STANDARD 488-1978 (GPIB)
•
•
•
•
•
•
•
•
•
8-Channel Bidirectional Transceiver
Power-Up/Power-Down Protection (Glitch
Free)
High-Speed. Low-Power Schottky Circuitry
Low-Power Dissipation ••• 72 mW Max Per
Channel
Fast Propagation Times .•• 22 ns Max
High-Impedance PNP Inputs
Receiver Hysteresis •.. 650 mV Typ
Open-Collector Driver Output Option
No Loading of Bus When Device Is
Powered Down (Vee = 0)
ow OR N PACKAGE
(TOP VIEW)
TE
vee
61
01
02
03
04
05
06
07
08
GPI6
I/O Ports
64
65
67
88
GNO
Terminal
I/O Ports
description
The SN75160B 8-channel general-purpose interface bus transceiver is a monolithic, high-speed, low-power
Schottky device designed for two-way data communications over single-ended transmission lines. It is designed
to meet the requirements of IEEE Standard 488-1978. The transceiver features driver outputs that can be
operated in either the passive-pullup or 3-state mode. If talk enable (TE) is high, these ports have the
characteristics of passive-pullup outputs when pullup enable (PE) is low, and of 3-state outputs when PE is high.
Taking TE low places these ports in the high-impedance state. The driver outputs are designed to handle loads
up to 48 mA of sink current.
Output glitches during power up and power down are eliminated by an internal circuit that disables both the bus
and receiver outputs. The outputs do not load the bus when Vee = O. When combined with the SN75161 B or
SN75162B management bus transceivers, the pair provides the complete 16-wire interface for the IEEE-488
bus.
The SN75160B is characterized for operation from QOG to 7QoG.
Function Tables
EACHORIVER
INPUTS
0
H
L
H
x
TE
PE
H
H
X
L
H
X
L
x
EACH RECEIVER
INPUTS
OUTPUT
B
B
TE
PE
0
H
L
L
H
L
L
H
X
X
X
L
H
Z
zt
Zt
,
X
OUTPUT
H =high level,
L =low level,
X =irrelevant,
Z =high-impedance state
t This is the high-impedance state of a normal 3-state output modified by the internal resistors to Vee
and GND.
Copyright ~ 1993. Texas Instruments Incorporated
1ExAs ."
INSIRUMENTS
POST OFFIGE BOX 655303 • DALLAS. TEXAS 75265
2--405
SN75160B
OCTALGENERA~PURPOSE
INTERFACE BUS TRANSCEIVER
Sl.LSOO4A- 02525, OCTOBER 1985 - REVISED FEBRUARY 1993
logic symbol t
PE 11
1
~
TE
logic diagram (positive logic)
......
TE .!...t>-
M1[3S]
PE 11
M2[OC]
EN3[XMTJ
l..r::. ,EN4[RCV]
19
01
18
02 17
D3
D4 16
OS 15
L
I>
r
3(1 V'12~)
V'4 1
JJ
01
~
07 13
DB 12
'f
I
2 B1
02
'f
I
03
05
tThis symbol is in accordance with ANSVIEEE Std 91-1984
and IEC Publication 617-12.
V' Designates 3-state outputs
~ Designates passive-pullup outputs
3
A.tl
4
, A.t 1
5
16
'f
~
15
'f
14
!os 1
13
"'f
1
T"
'1"
A.t 1
I
I
07
1
'f
I
D6
~
~
I
Terminal
VOPorta
2
17
I
D4
!os 1
...
18
3
B2
483
5 B4
6 B5
7 B6
8 B7
9 Be
D6 14
19
A.t
&
7
~
8
~
DB
12
'f
I
~l
9
~
schematics of inputs and outputs
EQUIVALENT OF ALL CONTROL INPUTS
EQUIVALENT OF ALL INPUT/OUTPUT PORTS
VCC------~~-----
91m
NOM
Input
GND~----~--~~
Input/Output Port
Driver output Req = 30 Q NOM
Receiver output Req = 110 Q NOM
Circuit Inside dashed lines Is on the driver outputs only.
2-406
1ExAs'"
INSTRUMENTS
POST OFFICE BOX _
• DAUAS. TEXAS 75265
SN75160B
OCTAL GENERAL-PURPOSE
INTERFACE BUS TRANSCEIVER
SLLSOO4A- 02525, OCTOBER 1985 - REVISED FEBRUARY 1993
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) ............................................................. 7 V
Input voltage ............................................................................. 5.5 V
Low-level driver output current ............................................................ 100 rnA
Continuous total power dissipation ..................................... See Dissipation Rating Table
Operating free-air temperature range .................................................. O°C to 70°C
Storage temperature range ....................................................... -65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds ............................... 260°C
NOTES: 1. All voltage values are with respect to network ground terminal.
DISSIPATION RATING TABLE
TA '" 25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
TA=70°C
POWER RATING
DW
1125mW
9.0mwre
720mW
N
1150 mW
9.2 mWre
736mW
PACKAGE
recommended operating conditions
Supply voltage, Vee
High-level Input voltage, VIH
MIN
NOM
MAX
UNIT
4.75
5
5.25
V
Low-Ievel input voltage, VIL
High-level output current, IOH
High-level output current, IOL
V
2
0.8
Bus ports with pullups active
-5.2
Terminal ports
-800
Bus ports
48
Terminal ports
16
Operating free-air temperature, TA
0
1ExAs
70
V
rnA
tAA
rnA
°e
..If
INSIRlJMENTS
POST OFFICE BOX 655300 • DALLAS, TEXAS 75265
2-407
SN75160B
OCTAL GENERAL-PURPOSE
INTERFACE BUS TRANSCEIVER
SLLSOO4A- 02525, OCTOBER 1985 - REVISED FEBRUARY 1993
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
PARAMETER
VIK
Input clamp voltage
Vhvs
Hysteresis (VT + -
Vr ...)
TEST CONDITIONS
Bus
See Figure 8
Terminal
IOH = -800 !-lA,
Bus
IOH = -5.2 mA,
Terminal
IOL= 16mA,
TEatO.8V
Bus
IOL= 48 mA,
TEat2V
Terminal
VI =5.5V
VOH
High-level output voltage
VOL
Low-level output voltage
II
Input current at.maxlmum
Input voltage
IIH
High-level input current
Terminal
VI=2.7V
IlL
Low-level Input current
Terminal
VI =0.5V
VVO(bus)
Voltage at bus port
Power off
2.7
3.5
PE and TE at2V
2.5
3.3
2.5
VCC=O,
V
V
0.3
0.5
0.35
0.5
0.2
100
!-IA
0.1
20
-10
-100
!-IA
!-IA
3.0
3.7
-1.5
2.5
-3.2
VICbus) = 3.7 Vto 5 V
0
VI (bus) = 5 Vto 5.5 V
0.7
2.5
-40
-15
-35
-75
Bus
-25
-50
-125
Supply current
No load
CVO(bus)
Bus-port capac~ance
VCC =Oto 5V,
f= 1 MHz
mA
2.5
Terminal
ICC
V
-3.2
0
Vl(bust = 0 to 2.5 V
Short-circu~
V
-1.3
VI(bus) = 2.5 Vto 3.7 V
lOS
output current
V
II (bus) = -12 mA
Driver disabled
Power on
UNIT
-1.5
TEatO.8V
VI (bus) = 0.4 V to 2.5 V
Current into bus port
MAX
-0.8
0.65
II(bus) = 0
Driver disabled
TYpt
0.4
VICbus) = -1.5 Vto 0.4 V
IVO(buS)
MIN
11=-18mA
Receivers low and enabled
70
90
Drivers low and enabled
85
110
VVO =Oto 2V,
30
mA
mA
pF
t All typical values are at VCC = 5 V, TA = 25°C.
switching characteristics, Vee
=5 V, CL =15 pF, TA =25°C (unless otherwise noted)
FROM
(INPUT)
PARAMETER
tpLH
Propation delay time, low-ta-high level output
tPHL
Propagation delay lime, high-Io-Iow level output
tpLH
Propagation delay time, low-to-hlgh level output
IpHL
Propagation delay time, hlgh-to-Iow level output
TO
(OUTPUT)
TEST CONDITIONS
Terminal
Bus
CL= 30 pF,
See Figure 1
Bus
Terminal
CL= 30 pF,
See Figure 2
MIN
TYP
MAX
14
20
14
20
10
20
15
22
35
tpZH
Output enable time to high level
25
tpHZ
Output disable time from high level
13
22
tpZL
Output enable time to low level
22
35
TE
BUS
See Figure 3
tpLZ
Output disable time from low level
22
32
tpZH
Output enable time to high level
20
30
tpHZ
Output disable time from high level
tpZL
Output enable time to low level
TE
Terminal
See Figure 4
12
20
23
32
30
tpLZ
Output disable lime from low level
19
len
Output pullup enable time
15
22
tdis
Output pullup disable time
13
20
PE
Bus
1ExAs
See Figure 5
..If
INSIRUMENTS
2-408
POST OFFICE SOX 655303 • DAUAS, TEXAS 75265
UNIT
ns
ns
ns
ns
ns
SN75160B
OCTAL GENERAl·PURPOSE
INTERFACE BUS TRANSCEIVER
SLl.SOO4A- 02525, OCTOBER 1985 - REVISED FEBRUARY 1993
PARAMETER MEASUREMENT INFORMATION
2000
~5~-- 3V
J 1.5 V
Dlnput
\.
---'L _.
I~
ov
tPLHi
tpHL~
B Output
1~;-.2-V----""\l- - - VOH
~ VOH
.
3V
TEST CIRCUIT
VOLTAGE WAVEFORMS
Figure 1. Termlnal-ta-Bus Test Circuit and VoHage Waveforms
~1.5V
B Input
2400
tPLH+"1
3kO
DOutput
!1.5V
TEST CIRCUIT
VOLTAGE WAVEFORMS
Figure 2. Bus-to-Terminal Test Circuit and Voltage Waveforms
T:o TE~1"
3V
S1
tPZH - '
Ie-
B~1~! !2V
.1
tPZL
~
\~~-r=
tpHz - - '
!~:::
tpLZ-W
~: 3.5 V
B Output
'\
S1 toGND1.0V
0.5 V
S2 Closed
'-. _ _ _ _ _.1 - -
TEST CIRCUIT
::
-
VOL
VOLTAGE WAVEFORMS
Figure 3. TE-to-Bus Test Circuit and VoHage Waveforms
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR " 1 MHz. 50% duty cycle, tr " 6 ns. tf .. ns,
ZO=500.
B. CL includes probe and jig capac~ance.
1ExAs .,If
INSIRUMENIS
POST OFFICE BOX 855303 • DAUAS. TEXAS 75266
2-409
SN75160B
OCTAL GENERAL·PURPOSE
INTERFACE BUS TRANSCEIVER
Su.sOO4A- 02525, OCTOBER 1985 - REVISED FEBRUARY 1993
PARAMETER MEASUREMENT INFORMATION
4.3 V
6
S2
~
~",1_.5_V
TE Input
rr
Jj~~ __
____
tPZH --I
D Output
S1 T03V
S20p'en
tp
~
I
I.
~
ZL-
D Output
S1toGND
S2CI08ed
tPHZ -.I
I
1.5V
'\
tpLZ
r.::
L9o%
--
3V
OV
VOH
I:;:::4V
J
~
OV
_
1-
I
1.0V
•
O.7L VOL
VOLTAGE WAVEFORMS
TEST CIRCUIT
Figure 4. TE-to-Termlnal Test Circuit and VoHage Waveforms
r-----'
Generator
(see Note A)
PEl
I
I
I
,_----""""\- ---- 3 V
1.5V
1.5V
1"'-_-
B
tells --.j
I
I
I
I
I
I
I
3V----~TE~~
I
L _ _ _ _ _ ...J
500
2V
VOL-O.BV
VOLTAGE WAVEFORMS
TEST CIRCUIT
Figure 5. PE-to-Bus Pullup Test ClrcuH and Voltage Waveforms
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR
ZO=500.
B. CL Includes probe and jig capacRance.
1ExAs . "
INSIRUMENTS
2-410
POST OFFICE BOX 655303 • DAUAS, TEXAS 75265
0;
1 MHz, 50% duty cycle, tr
0;
6 ns, tf
0;
ns,
SN75160B
OCTAL GENERAL-PURPOSE
INTERFACE BUS TRANSCEIVER
SLLSOO4A- 02525. OCTOBER 1985 - REVISED FEBRUARY 1993
TYPICAL CHARACTERISTICS
TERMINAL HIGH-LEVEL OUTPUT VOLTAGE
4
>
3.&
..........
1
III
I
3
!5
2.&
~
va
HIGH-LEVEL OUTPUT CURRENT
LOW-LEVEL OUTPUT CURRENT
~
1:
r
.1.
I.
VCC=&V
TA=25°C-
,
2
0.&
"\
-10
-1&
-20
-25
0.2
-35
/
/
/
V
/
V
0.1
i\.
-30
./
0.3
..J
.p
\.
.p
-&
0.4
1
/
TA=25°C
0.&
I
I\.
o
>1
}
1
:I:
o
I.
VCC=&V
I
'\
1.&
0.6
"aI
'r\.~
!
0
TERMINAL LOW-LEVEL OUTPUT VOLTAGE
va
o
-40
o
10
20
30
40
50
60
IOL - Low-Level Output Current - mA
IOH - High-Level Output Current - mA
Figure 6
Figure 7
TERMINAL OUTPUT VOLTAGE
va
BUS INPUT VOLTAGE
4
VCC=&IV
NoLoed
3.&
TA = 25°C
>
3
i"
2.&
!5
2
1
~
!
0
1
VT-
VT+
1.&
.p
0.&
o
o
0.2
0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
2
VI -Input Voltage - V
Figure 8
. 1ExAs,lf
INSIRUMENIS
POST OFFICE BOX 655303 • DAllAS. TEXAS 75265
2--411
SN75160B
OCTALGENERA~PURPOSE
INTERFACE BUS TRANSCEIVER
SLLSOO4A- 02525. OCTOBER 1985 - REVISED FEBRUARY 1993
TYPICAL CHARACTERISTICS
BUS HIGH,LEVEL OUTPUT VOLTAGE
va
HIGH·LEVEL OUTPUT CURRENT
LOW·LEVEL OUTPUT CURRENT
0
,
>
I
II
3
2
J:.
fI
:t
.p
o
TA,,25°C
~
~
0
0.6
VCC~5V
1
'S
]
BUS LOW-LEVEL OUTPUT VOLTAGE
va
o
-20
-40
l/
~ OA
i
V
0.3
I.. V
/
/
,/
,/
""
I
.I
-50
-30
o
-60
o
10
20
30
40
50
60
70
60
90 100
IOL - Low-Level Output Current - mA
Figure 9
Figure 10
BUS OUTPUT VOLTAGE
BUS CURRENT
va
va
THERMAL INPUT VOLTAGE
BUS VOLTAGE
VCC=&V
No Load
TA = 25°C
2
~
3 r-~---r--;---++-1---+--~~
I
I
0 ~~~~~~~~Y~n",,",,~~
I -1~~~~~71--~~~~~
&
t
'S 2
u
!I
r-~---r--;---~-1---+--~~
!
-2
~-t---\-;~r--t---t-~~~~
ID
i-3~-t-1~~~~~~~~~~
I
~
/
~ 0.1
IOH - High-Level Output Current - mA
>
./
0.&
t
1\
1\
1\
-10
=:-
I
J
VCC=5V
TA=2S°C
j-4
1 r-~---r--;---#--1---+--~~
-&
The Unshaded
Area Conforms to
Paragraph 3.&.3 of
IEEE Standard 488-1978
-6
OL-......_.....L.._.L....--L_..I-_......--I_....I
0.9
1.1
1.2 1.3 1.4 1.&
VI-Input Voltage - V
1.6
1.7
-7
-2
-1
3
4
0
2
Vl/o(Bus) - Bus Voltage - V
Figure 11
Figure 12
1ExAs ."
INSIRUMENfS
2-412
POST OFFICE BOX 855303 • DAUAS. TEXAS 75265
&
6
SN55ALS160, SN75ALS160
OCTAL GENERAL·PURPOSE INTERFACE BUS TRANSCEIVERS
SLLS018C-
JUNE 1986 - REVISED FEBRUARY 1993
SUITABLE FOR IEEE STANDARD 488-1978 {GPIB)t
•
•
•
•
•
•
•
•
•
a-Channel Bidirectional Transceiver
High-Speed Advanced Low-Power Schottky
Circuitry
Low Power Dissipation:
SN55ALS160 ••. 56 mW Max
Per Channel
SN75ALS160 ..• 46 mW Max
Per Channel
Fast Propagation Times ••• 20 ns Max
High-Impedance PNP Inputs
Receiver Hysteresis:
SN55ALS160 ••• 550 mV Typ
SN75ALS160 .•. 650 mVTyp
Open-Collector Driver Output Option
No Loading of Bus When Device Is
Powered Down (Vee = 0)
Power-Up/Power-Down Protection
(Glitch Free)
SN55ALS160 ••• J OR W PACKAGE
SN75ALS160 ••• OW OR N PACKAGE
(TOPVJEW)
VCC
B1
01
B2
B3
02
03
04
05
D6
07
GPIB
I/O Ports
B7
B8
GNO
9
_ _ _ _.T
Terminal
I/O Ports
OS
PE
SN55ALS160 ••• FK PACKAGE
(TOPVJEW)
o
C\I .....
W 0-
3 2
1 2019
18
CD CD I-::>C
B3
B4
B5
B6
B7
description
The SN55ALS160 and SN75ALS160 eightchannel
general-purpose
interface
bus
transceivers
are
monolithic,
high-speed,
advanced low-power Schottky devices designed
for two-way data communications over
single-ended transmission lines. They are
designed to meet the requirements of IEEE
Standard 488-1978. The transceivers feature
driver outputs that can be operated in either the
passive-pullup or 3-state mode. If talk enable (TE)
is high, these ports have the characteristics of
passive-pullup outputs when pullup enable (PE) is
low, and of 3-state outputs when PE is high. Taking
TE low places these ports in the high-impedance
state. The driver outputs are designed to handle
loads up to 48 mA of sink current.
TE
4
5
6
02
03
04
05
06
17
16
15
14
8
9 10 11 12 13
7
OOCWOO .....
CDZa..CC
G
Function Tables
EACH DRIVER
INPUTS
0
TE PE
H
H
H
L
H
X
H
X
L
X
H
Z
L
OUTPUT
= high level,
B
H
L
L
z*
z*
X
L
EACH RECEIVER
INPUTS
B TE PE
=low level,
=high-impedance state
H
L
L
X
H
X
X
X
X
OUTPUT
0
L
H
Z
=irrelevant,
*
This is the high-impedance state of a normal 30state output
An active turn-off feature has been incorporated
modified by the internal resistors to VCC and GND.
into the bus-terminating resistors so that the
device exhibits a high impedance to the bus when
Vee =O. When combined with the SN55ALS161 , SN75ALS161, or SN75ALS162 management bus transceiver,
the pair provides the complete 16-wire interface for the IEEE-488 bus.
The SN55ALS 160 is characterized for operation from -55°C to 125°C.The SN75ALS160 is characterized for
operation from O°C to 70°C.
t The transceivers are suitable for IEEE Standard 896 applications to the extent of the operating conditions and characteristics specified in this
data sheet. Certain IimHs contained in the IEEE specification are not met or cannot be tested over the entire military temperature range.
CopyrightC> 1993, Texas Instruments Incorporated
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75l!65
2-413
SN55ALS160, SN75ALS160
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVERS
Su.sOl8C - 02525. JUNE 1986 - REVISED FEBRUARY 1993
logic symbol t
11
PE
1
TE
L
L
logic diagram (positiveJogic)
Ma[OC]
18
02
03
04
05
06
07
08
TE
,
EN4[RCV]
01
r
2
t>
L-
11
EN3[XMT]
19
01
PE
M1 [3S]
3(1V/2~)
V4
1
Jf
2
~
3
17
4
16
6
15
6
14
7
13
8
12
9
D2
B1
3 B2
B2
03
B3
17
4
B4
B5
D4
B6
Terminal
B7
Ports
B8
VO
5 B4
05
GPIB
15
VO
6
and IEC Publication 617-12.
~
B3
16
t This symbol is in accordance with ANSI/IEEE Std 91-1984
V Designates 3-state outputs
B1
18
OS
Ports
B5
14
Designates open-collector outputs
7 B6
07
13
8
08
B7
12
9 B8
schematics of inputs and outputs
EQUIVALENT OF ALL CONTROL INPUTS
EQUIVALENT OF ALL INPUT/OUTPUT PORTS
VCC------~.---------
9ke
NOM
Input-e-.
GNO--__--~._----__-Input/Output Port
Driver output Req = 30 e NOM
Receiver output Req =110 e NOM
Circuit inside dashed lines is on the driver outputs only.
1ExAs ..,
INSIRUMENIS
2-414
POST OFFICE SOX 655303 • DAUAS. TEXAS 75265
SN55ALS160, SN75ALS160
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVERS
SLlSOl8C - 02525, JUNE 1986 - REVISED FEBRUARY 1993
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) .................... , ........................................ 7 V
Input voltage, VI .......................................................................... 5.5 V
Low-level driver output current ...... ,..................................................... 100 rnA
Continuous total dissipation ........................................... See Dissipation Rating Table
Operating free-air temperature range: SN55ALS160 ................................ -55·C to 125·C
SN75ALS160 .................................... O·C to 70·C
Storage temperature range ....................................................... -65·C to 150·C
Case temperature for 60 seconds: FK package .............................................. 260·C
Lead temperature 1,6 mm (1/16 inch) from the case for 10 seconds: DW or N package ........... 260·C
Lead temperature 1,6 mm (1/16 inch) from the case for 60 seconds: J or W package ............. 300·C
NOTES: 1. All voltage values are with respect to network ground terminal.
DISSIPATION RATING TABLE
PACKAGE
TA:s:25°C
POWER RATING
DERATING
FACTOR
TA = 70°C
POWER RATING
TA=125°C
POWER RATING
OW
1125mW
9.0mwrc
720mW
FK
1375mW
11.0mwre
8BOmW
275mW
J
1375mW
11.0 mWre
8BOmW
275mW
N
1150mW
9.2mWre
736mW
W
1000mW
8.0mWre
640mW
200mW
SN55ALS160 recommended operating conditions
Supply voHage, vee
TE and PE at TA = -55°C to 125°C
High-level input voltage, VIH
High-level output current, IOH
Low-level output current. IOL
NOM
MAX
UNIT
5
5.25
V
2
Bus and terminal at TA = 25°C to 125°C
Bus and terminal at TA = -55°C
Low-level input voltage, VIL
MIN
4.75
V
2
2.1
TE and PE at TA =-55°eto 125°C
0.8
Bus and terminal at TA = 25°C to -55°C
0.8
Bus and terminal at TA = 125°C
0.7
V
Bus ports with pUIiUps active (Vee = 5 V)
-5.2
mA
Terminal ports
-800
j.oA
Bus ports
48
Terminal ports
16
Operating free-air temperature, TA
-55
125
mA
°e
SN75ALS160 recommended operating conditions
Supply voHage, Vee
High-level input voltage, VIH
MIN
NOM
MAX
UNIT
4.75
5
5.25
V
0.8
V
Low-Ievet input voHage, VIL
High-level output current, IOH
Low-level output current, IOL
V
2
Bus ports with pUIiUps active
-5.2
mA
Terminal ports
-800
j.oA
Bus ports
48
Terminal ports
16
Operating free-air temperature, TA
0
1ExAs
70
mA
°e
~
INSIRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2-415
t
'"
electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless
otherwise noted)
PARAMETER
VIK
SN55ALSl60
TEST CONDITJONSt
Input clamp voltage
11=-lSmA,
MIN
VCC= MIN
SN75ALSl60
TYP*
MAX
-O.S
-1.5
0.4
Bus
Vhys
~
!Ii
;~4r
Hysteresis (\IT+ -
Vr-J
VOH§
High-level output voltage
VOL
Low-level output voltage
II
Input current at maximum
input voltage
IIH
High-level Input current
IlL
Low-level input current
VVO(bus)
-1.5
V
TA=125°C
Terminal
10H = - 800 JAA,
TEalO.SV,
VCC= MIN
2.7
3.5
2.7
3.5
Bus
10H = - 5.2 rnA,
PE and TE at 2 V,
VCC = MIN
2.5
3.3
2.5
3.3
Terminal
10L= 16 rnA,
TE alO.Sv,
VCC= MIN
0.3
0.5
0.3
0.5
Bus
10L= 48 rnA,
TEal2V,
VCC= MIN
0.35
0.5
0.35
0.5
Terminal
VI =5.5 V,
VCC= MAX
0.2
100
0.2
100
J.&A
Terminal,
PE,orTE
VI = 2.7 V,
VCC= MAX
0.1
20
0.1
20
VI = 0.5 V,
VCC= MAX
-30
-100
-10
-100
J.&A
J.&A
Driver disabled,
VCC = 5 V (SN551
II(bus) = 0
3
3.7
3
3.7
Power on
Driver disabled,
VCC = 5 V (SN551
0.55
0.25
2.5
2.5
-1.5
-1.3
V
-1.5
-3.2
0
V
2.5
-3.2
\
2.5
-3.2
0
2.5
0
2.5
VI (bus) = 5 Vto 5.5 V
0.7
2.5
0.7
2.5
40
40
Power off
VCC=O
Terminal
VCC= MAX
-15
-35
-75
-15
-35
-75
Bus
VCC= MAX
-25
-so
-125
-25
-50
-125
42
56
42
65
Supply current
No load,
VCC= MAX
Terminal outputs low and enabled
ICC
Bus outputs low and enabled
52
85
52
SO
CVO(bus)
Bus-port capacitance
VCC=Oto5V,
VI/O=Oto2V;
30
~c.n
~c.n
.-1>
Ci)~
mzg
m-
~~
...
i r.
"tJe!
i¥i
c:-
~ "tJ_
:xI~
~
I
~g
m
52
:xl
i iii
~
o
m
OJ
c:
-3.2
VI (bus) = 3.7Vto 5 V
VI (bus) = 0 to 2.5 V
oen
OZ
en
0
Short-circuit output current
are
V
-1.3
VI(bus) = 2.5 Vto 3.7 V
f= 1 MHz
j...
I
II(bus) =-12 rnA
t For condHions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
All typical values
atVcc = 5 V, TA = 25°C.
§ VOH applies to 3-state outputs only.
~I
c:
0.65
lOS
*
V
VCC=5V,
VI (bus) = 0.4 Vto 2.5 V
m
MAX
-O.S
TA =-55°C and 25°C
Voltage at bus port
Current into bus port
0.4
TYP*
VCC=5V,
Bus
VI (bus) = -1.5 Vto 0.4 V
IVO(bus)
MIN
UNIT
~
30
rnA
~
o
m
J.&A
rnA
rnA
pF
rii
:xl
en
SN55ALS160
OCTAL GENERAL·PURPOSE INTERFACE BUS TRANCEIVER
SLLS018C - 02525, JUNE 1986 - REVISED FEBRUARY 1993
switching characteristics at Vee = 4.75 V, 5 V, and 5.25 V, CL = 50 pF (unless otherwise noted)
PARAMETER
tpLH
Propagation delay time,
low-to-high-Ievel output
tpHL
Propagation delay time,
high-to-Iow-Ievel output
tpLH
Propagation delay time,
low-to-high-Ievel output
tpHL
Propagation delay time,
high-to-Iow-Ievel output
FROM
(INPUT)
See Figure 2
Output enable time to high level
Output pull up enable time
25°C
Bus
See Figure 3
14
8
15
8
15
24
30
18
41
9
14
16
28
16
Terminal
See Figure 4
24
15
Bus
See Figure 5
25°C
Output pullup disable time
Full range
ns
26
30
15
24
31
16
24
25
Full range
PE
18
23
Full range
25°C
36
50
10
Full range
25°C
19
24
Full range
25°C
ns
34
12
Full range
25°C
ns
18
Full range
25°C
ns
16
Full range
25°C
UNIT
17
10
Full range
25°C
MAX
20
Full range
25°C
Output enable time to low level
ten
10
Full range
TE
Output disable time from low level
25°C
25°C
Output disable time from high level
tpLZ
TYpt:
Full range
Output enable time to low level
tpZH
Idis
Terminal
Output disable time from high level
Output disable time from low level
tPZL
See Figure 1
Output enable time to high level
tpLZ
tpHZ
Bus
MIN
Full range
25°C
TE
tPZL
TAt
Full range
Bus
tpHZ
TEST
CONDITIONS
25°C
Terminal
tpZH
TO
(OUTPUT)
9
ns
16
20
t Full range IS -55°C to 125°C.
*
All typical values are at VCC = 5 V.
1ExAs
~
INSIRUMENTS
POST OFFICE BOX 655303 • DAllAS, TEXAS 75265
2-417
SN75ALS160·
OCTAL GENERAL·PURPOSE INTERFACE BUS TRANCEIVER
.SUSOl8C-02525, JUNE 1986-REVISEO FEBRUARY 1993
switching characteristics over recommended range of operating free-air temperature, Vee
PARAMETER
tpLH
Propagation delay time,
low-to-hlgh-Ievel output
tPHL
Propagation delay time,
high-to-Iow-Ievel output
tpLH
Propagation delay time,
low-to-high-Ievel output
tpHL
Propagation delay time,
hlgh-to-Iow-Ievel output
tPZH
Output enable time to high level
tpHZ
Output disable time from high level
tpZL
Output enable time to low level
tPLZ
Output disable time from low level
tpZH
Output enable time to high level
tpHZ
Output disable time from high level
tPZL
Output enable time to low level
tpLZ
Output disable time from low level
len
Output pullup enable time
!dis
Output pullup disable time
FROM
(INPUT)
TO
(OUTPUl)
TEST CONDInONS
Terminal
Bus
CL=30pF,
See Figure 1
Bus
TE
TE
PE
CL=30pF,
See Figure 2
Terminal
CL= 15pF,
See Figure 3
Bus
TYpt
MAX
7
20
B
20
7
14
9
14
19
30
ns
5
12
16
35
9
20
13
30
CL= 15 pF,
See Figure 4
12
20
12
20
11
20
Bus
CL= 15 pF,
See Figure 5
11
22
6
12
1ExAs
~
INSlRUMENlS
POST OFFICE SOX 655303 • DALlAS, TEXAS 75265
UNIT
ns
Terminal
t Typical values are at TA = 25°C.
2-418
MIN
=5 V
ns
ns
ns
SN55ALS160,SN75ALS160
OCTAL GENERAL·PURPOSE INTERFACE BUS TRANSCEIVERS
SLLSOl8C- 02525, JUNE 1986-REVISED FEBRUARY 1993
PARAMETER MEASUREMENT INFORMATION
sv
[7V]
D~UV
3V----I
Output
2000
[5000]
tpLH ~
I
3V
CL =30pF
[=50pF]
(saeNoteB)
B Output
~:V---::
tpHL--1+-+1
"2-.2-V---~=-""\1- -
/'
4800
[SOOO]
.
TEST CIRCUIT
-
VOH
\..!.LvOH
VOLTAGE WAVEFORMS
Figure 1. Termlnal·to-Bus Test Circuit and Voltage Waveforms
4.3 V
[7V]
Blnput
1•SV
..:........Ii
2400
>----.>--f.'=+-.----e
J
[500 0]
\1.~V---3V
~
--l.---.!
, ,.______
tpLH--!..i
tpHL
OV
- VOH
..,~~I
3kO
DOutput
!1.SV
1.SV
[SOOO].
VOL
VOLTAGE WAVEFORMS
Figure 2. Bus-to-Terminal Test Circuit and Voltage Waveforms
SV
3V
[7V]12OO0
Output
[5000]
~1 5 V
TE Input
S2
S1
,
tPZH~
T
CL =15pF
[=50pF]
(_NoteB)
BOutput'
480 0 S1 to 3 V ,
[500 0] S2 Open,
•
14I
tPZL
BOutput
S1 toGND
S2Closad
VOLTAGE WAVEFORMS
TEST CIRCUIT
Figure 3. TE-to-Bus Test Circuit and Voltage Waveforms
[] denotes the SN55ALS160 military test conditions.
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR s 1 MHz, 50% duty cycle, tr s 6 ns, If S 6 ns,
ZO=50o.
B. CL includes probe and jig capacitance.
.''lEXAS
,If
INSlRlJMENTS
POST OFFICE BOX 655303 • DAUAS, TEXAS 75265
\
2-419
SN55ALS160,SN75ALS160
OCTAL GENERAL·PURPOSE INTERFACE BUS TRANSCEIVERS
SLLS018C - 02525, JUNE 1986 - REVISED FEBRUARY 1993
PARAMETER MEASUREMENT INFORMATION
4.3 V
[7Vl
6 S2
~
tPZH---+I
2400
[SOOO)
I
3V~
f
oOutput
S1 to3V
S20pen
CL =15pF
3kO
[SOOO)
[=50pFl
(see Now B)
-=
fAY
~1'5V
I I
I
I
tpHZ~
1.SV
j+-
tpZL---+i
o Output
S1 toGNO
\1V
S2Cloaed
TEST CIRCUIT
3'
___ ov
OV
~
4V
kVOL
VOLTAGE WAVEFORMS
Figure 4. TE·to·Termlnal Test Circuit and Voltage Waveforms
>-.....'4~----+- Output
::i!
lnput
_
1.SV
ten-': I+-
RL = 480 0 B Output
[=SOOO)
.
I------~
I
TEST CIRCUIT
2V
VOLTAGE WAVEFORMS
Figure 5. PE·to·Bus Test Circuit and Voltage Waveforms
[I denotes the SN55ALS160 military test conditions.
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR s 1 MHz, 50% duty cycle, tr s 6 ns, tf S 6 ns,
ZO=50Q.
B. CL includes probe and jig capacitance.
2-420
1ExAs ..,
INSIRUMENTS
POST OFFICE BOX 655303" DAUAS, TEXAS 75265
SN55ALS160, SN75ALS160
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVERS
SLLS018C- 02525, JUNE 1986 - REVISED FEBRUARY 1993
TYPICAL CHARACTERISTICS
TERMINAL HIGH-LEVEL OUTPUT VOLTAGE
va
HIGH-LEVEL OUTPUT CURRENT
LOW-LEVEL OUTPUT CURRENT
4
>I
~
3.5
"""
3
'S
2.5
~
2
!
"'\
CI
I
l:
I
0.4
0
0.3
~
l\.
'"
!
0.2
~
0.1
I
oJ
'\
o
0.5
~
1'S
'\
0.5
o
,
>
1
VCC=5V
TA=25°C
III
I"
1.5
%
.p
0.6
.1
~.
VCC=5V
TA=25°C -
III
J
TERMINAL LOW-LEVEL OUTPUT VOLTAGE
va
i\.
o
-5 -10 -15 -20 -25 -30 -35 -40
IOH - High-Level Output Current - mA
/
/
/
/
10'
V
/
V
o
10
40
50
20
30
IOL - Low-Level Output Current - mA
Figure 6
60
Figure 7
TERMINAL OUTPUT VOLTAGE
va
BUS INPUT VOLTAGE
4
V~C=~V
No Load
TA=25°C
3.5
>I
3
III
I
2.5
'S
2
~
~
0
I
VT-
VT+
1.5
~
0.5
o
o
0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8
V, -Input Voltage - V
2
Figure 8
1ExAs ~
INSTRUMENrS
POST OFFICE BOX 655303 • DAllAS, TEXAS 75265
2-421
SN55ALS160,SN75ALS160
OCTAL GENERAL·PURPOSE INTERFACE BUS TRANSCEIVERS
SLLSOl8C - 02525, JUNE 1986 - REVISED FEBRUARY 1993
TYPICAl., CHARACTERISTICS
BUS HIGH-LEVEL OUTPUT VOLTAGE
BUS LOW-LEVEL OUTPUT VOLTAGE
vs
vs
BUS HIGH-LEVEL OUTPUT CURRENT
BUS LOW-LEVEL OUTPUT CURRENT
0.6
4
VCC=5V
TA=25"C
>
.
f
f
0
-10
-20
0.4
0.3
'ii
!
§
"~
-30
-40
0.2
!J
'\
o
,/"
./
!i
"\
o
V
./
0.5
I
"'"'~,
~
I
VCC=5V
TA=25"C
.J'
v
.,/
0.1
o
-50
V
~
,/
V
-60
o
10
20
30
40
50
60
70
IOL - Low-Level Output Current - mA
IOH - High-level Output Current - rnA
Figure 9
Figure 10
BUS OUTPUT VOLTAGE
BUS CURRENT
VB
BUS VOLTAGE
vs
TERMINAL INPUT VOLTAGE
VCC=5V
No load
TA=25"C
2
3r-~---+--~--+T~---+--~--;
~
I
i
a
!I
m
I
'ii'
:::I
e.
~
o
-1
-2
-3
-4
-5
-6
o~~--~--~--~~--~--~~
0.9
1.1
1.2
1.3
1.4
1.5
1.6
1.7
VI -Input Voltege - V
VVO(bus) - Bus Voltege - V
Figure 11
2-422
80
Figure 12
POST OFFICE BOX 655;303 • DALLAS. TEXAS 75265
90 100
SN75161B, SN75162B
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVERS
MEETS IEEE STANDARD 488-1978 (GPIB)
•
8-Channel Bidirectional Transceiver
•
Power-Up/Power-Down Protection
(GIHch Free)
•
Designed to Implement Control Bus
Interface
SN75161B ••• DW OR N PACKAGE
(TOP VIEW)
•
SN75161B Designed for Single Controller
•
SN75162B Designed for Multiple
Controllers
Vcc
GPIB
I/O Ports
•
•
High-Speed,Low-Power Schottky CircuHry
Low-Power Dissipation ..• 72 mW Max Per
Channel
•
•
Fast Propagation Times .•. 22 ns Max
High-impedance PNP Inputs
•
Receiver Hysteresis ..• 650 mV Typ
•
Bus-Terminating Resistors Provided on
Driver Outputs
•
No Loading of Bus When Device Is
Powered Down (Vee =0)
DAV
EOI
ATN
SRO
GND
6
..
....__
9
10
REN
IFC
NDAC
NRFD
DAV
EOI
ATN
SRO
DC
Terminal
I/O Ports
SN75162B •.• DW PACKAGE
(TOP VIEW)
description
The SN75161 Band SN75162B eight-channel,
general-purpose interface bus transceivers are
monolithic, high-speed, low-power Schottky
devices designed to meet the requirements of
IEEE Standard 488-1978. Each transceiver is
designed to provide the bus-management and
data-transfer signals between operating units of
a single- or multiple-controller instrumentation
system. When combined with the SN75160B octal
bus transceiver, the SN75161 B or SN75162B
provides the complete 16-wire interface for the
IEEE-488 bus.
The SN75161 Band SN75162B each features
eight driver-receiver pairs connected in a
front-to-back configuration to form input/output
(I/O) ports at both the bus and terminal sides. A
power-up/down disable circuit is included on all
bus and receiver outputs. This provides glitch-free
operation during VCC power up and power down.
The direction of data through these driver-receiver
pairs is determined by the DC, TE, and SC (on
SN75162B) enable signals. The SC input on the
SN75162B allows the REN and IFC transceivers
to be controlled independently.
GPIB
I/O Ports
.i
SC
TE
REN
IFC
NDAC
NRFD
DAV
EOI
ATN
SRO
NC
GND
VCC
3
4
5
6
9
NC
REN
IFC
NDAC
NRFD
DAV
EOI
ATN
SRO
NC
DC
Terminal
I/O Ports
SN75162B ••• N PACKAGE
(TOP VIEW)
GPIB
I/O Ports
SC
TE
REN
IFC
NDAC
NRFD
DAV
EOI
ATN
SRO
GND
VCC
NC
REN
IFC
NDAC
NRFD
DAV
EOI
ATN
SRO
DC
Terminal
I/O Ports
NC-No internal connection
Copyright © 1993, Texas Instruments Incorporated
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655303 • DALlAS, TEXAS 75265
2-423
SN75161B, SN75162B
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVERS
SUSOO5A- 02618, OCTOBER 1980- REVISED FEBRUARY 1993
description (continued)
The driver outputs (GPIB I/O ports) feature active bus-terminating resistor circuits designed to provide a high
impedance to the bus when supply voltage Vee is O. The drivers are designed to handle loads up to 48 rnA of
sink current. Each receiver features pnp transistor inputs for high input impedance and hysteresis of 400 mV
for increased noise immunity. All receivers have 3-state outputs to present a high impedance to the terminal
when disabled.
The SN75161 Band SN75162B are characterized for operation from O·C to 70·C.
CHANNEL IDENTIFICATION TABLE
NAME
2-424
IDENTITY
DC
Direction Control
TE
Talk Enable
SC
System Control (SN75162B only)
ATN
Attention
SRQ
Service Request
CLASS
Control
REN
Remote Enable
Bus
IFC
Interface Clear
Management
EOI
End of Identity
DAV
Data Valid
NDAC
Not Data Accepted
Data
NRFD
Not Ready for Data
Transfer
POST OFFICE BOX 855303 • DAUAS, TEXAS 7~
SN75161B
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVERS
SLl.SOO5A- 02618, OCTOBER 1980 - REVISED FEBRUARY 1993
logic symbol t
DC
TE
11
ATN
13
logic diagram (positive logic)
EN1/G4
EN2IG5
1
5
DC
EN3
TE
t>
EOI
14
1
SRQ
12
1
REN
IFC
DAV
NDAC
NRFD
19
18
15
17
16
t>
ATN
8 ATN
EOI
7 EOI
SRQ
9 SRQ
REN
2 REN
IFe
3 IFC
DAV
6 DAV
NDAC
4 NDAC
NRFD
5 NRFD
t>
1
t>
t>
t>
t>
t>
tThis symbol is in accordance with IEEE Std 91-1984 and
lEe Publication 617-12.
v Designates 3-state outputs
~ Designates passive-pullup outputs
1ExAs
..If
INSIRUMENTS
POST OFFICE BOX 855303 • DAUAS. TEXAS 75265
2-425
SN75162B
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVERS
SLLSOO5A- 02618. OCTOBER 1980 - REVISED FEBRUARY 1993
logic symbol t
DC
12
TE
SC 1
logic diagram (positive logic)
EN1/G4
EN2IG5
EN3
5
:.1
EN3
ATN 14
I>
EOI ~5
SAO 13
9
ATN
ATN
1
I>
EOI
EOI 15
1
I>
8
EOI
SRO
1
REN 20
I>
REN
SRO 13
10 SRO
1
IFC 19
I>
IFC
1
DAY 16
NDAC 18
I>
DAY
I>
NDAC
REN
IFC 19
1
NRFD 17
I>
20
REN
4
IFC
NRFD
tThls symbol Is in accordance with IEEE Sid 91-1984 and
lEe Publication 617-12.
v Designates 3-state outputs
~ Designates Passlve-pullup outputs
DAY 16
7
NDAC 18
5
NRFD 17
6
Pin numbers shown are for the N package.
1ExAs
~
INSIRUMENTS
2-426
3
POST OFFICE BOX _
• DAUAS. TEXAS 75265
DAY
NDAC
NRFD
SN75161 B, SN75162B
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVERS
SLLSOO5A- 02618, OCTOBER 1980 - REVISED FEBRUARY 1993
Function Tables
SN75161 B RECEIVElTRANSMIT
CONTROLS
DC
TE
DATA·TRANSFER CHANNELS
BUS-MANAGEMENT CHANNELS
ATNt
ATNt
SRQ
REN
IFC
EOI
DAV
H
H
H
H
H
L
L
L
L
L
H
H
L
L
H
L
X
X
R
T
R
R
T
R
T
T
R
T
R
R
T
R
T
T
NDAC
NRFD
(Controlled by TE)
(Controlled by DC)
T
T
R
R
R
T
T
R
R
T
T
T
T
R
R
R
R
T
SN751628 RECEIVElTRANSMIT
SC
DC
TE
DAV
NDAC
NRFD
(Controlled by TE)
T
R
R
H = high level, L = low level,
R = receive, T = transmit, X = irrelevant
Direction of data transmission is from the terminal side to the bus side, and the direction of data receiving is from the bus side to the terminal side.
Data transfer is noninvertlng in both directions.
t ATN is a normat transceiver channel that functions additionally as an internal direction control or talk enable for EOI whenever the DC and TE
inputs are in the same state. When DC and TE are In opposfte states, the ATN channel functions as an Independent transceiver only.
1ExAs
~
INSIRUMENTS
POST OFFICE BOX 655303 • DAUAS, TEXAS 75265
2-427
SN75161 B, SN75162B
.
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVERS
SLLSOOSA- 02618. OCTOBER 1980- REVISED FEBRUARY 1993
schematics of inputs and outputs
EQUIVALENT OF ALL CONTROL INPUTS
TYPICAL OF SRQ, NDAC, AND NRFD GPIB I/O PORT
~-------Hl__--""'------i~---~>-
vcc------~-------
VCC
Input
GND-4-----4----~-
Input/Output Port
CircuH inside dashed lines is on the driver outputs only.
TYPICAL OF ALL I/O PORTS EXCEPT SRQ, NDAC,
AND NRFD GPIB I/O PORTS
~.---~------~----~----~__--_.-VCC
----~--i~--~~~--~~----~--------GND
Input/Output Port
=
Driver output Req 30 g NOM
Receiver output Req 110 g NOM
Circuit inside dashed lines is on the driver outputs only.
=
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) ............................................................. 7 V
Input voltage ............................................................................. 5.5 V
Low-level driver output current ............................................................ 100 rnA
Continuous total power dissipation ..................................... See Dissipation Rating Table
Operating free-air temperature range .................................................. O·C to 70·C
Storage temperature range ....................................................... -65·C to 150·C
Lead temperature 1,6 mm (1/16) inch from the case for 10 seconds ............................ 260·C
NOTES: 1. All voltage values are with respect to network ground terminal.
2-428
POST OFFICE BOX 655303 • DAUAS. TEXAS 75265
SN75161 B, SN75162B
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVERS
Su.500SA- 02618, OCTOBER 1980 - REVISED FEBRUARY 1993
DISSIPATION RATING TABLE
PACKAGE
TA': 25·C
POWER RATING
DERATING FACTOR
ABOVE TA 25·C
=
TA=70·C
POWER RATING
OW (20 pin)
1125mW
9.0mWrC
OW (24 pin)
1350mW
10.BmWrC
720mW
864mW
N (20 pin)
1150mW
9.2mWrC
736mW
N (22 pin)
1700mW
13.6mWrC
l0B8mW
recommended operating conditions
Supply voltage, VCC
High-level Input voHage, VIH
MIN
NOM
MAX
UNIT
4.75
5
5.25
V
0.8
V
Low-level Input voltage, VIL
High-level output current, IOH
Low-level output current, IOL
V
2
Bus ports with 3-state outputs
-5.2
Terminal ports
-SOO
48
Bus ports
16
Terminal ports
Operating free-air temperature, TA
0
70
rnA
IIA
rnA
·C
1ExAs . "
INSIRUMENTS
POST OFFICE BOX _
• DAUAS, TEXAS 75265
2--429
SN75161 B, SN75162B
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVERS
SLLSOO5A- 02618, OCTOBER 1980 -
REV1S~O FEBRUARY 1993
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
TEST CONDI110NS
PARAMETER
VIK
Input clamp voltage
Vhys
Hysteresis (Vr + - VT -l
VOH*
High-level output voltage
VOL
Low-level oUtput voltage
II
Input current at maximum
input voltage
IIH
High-level Input current
IlL
Low-Ievellnput current
Vila (bus)
Voltage at bus port
Bus
See Figure 2
Terminal
10H = -800
Bus
tAA
2.7
3.5
IOH",-5.2mA
2.5
3.3
UNIT
V
V
V
IOL",16mA
0.3
0.5
Bus
10L=48mA
0.35
0.5
Terminal
VI ",5.5V
0.2
100
tAA
Terminal and
control Inputs
VI ",2.7 V
0.1
20
VI ",0.5 V
-10
-100
tAA
tAA
Driver disabled
II(bus) '" 0
Power on
Driver disabled
VCC",O,
2.5
3.0
3.7
-1.5
II/bus) ",-12mA
2.5
-3.2
0
VI (bus) '" 5 Vto 5.5 V
0.7
2.5
-40
Terminal
-15
-35
-75
Bus
-25
-50
-125
Supply current
No load,
Bus-port capacitance
VCC",5VtoO,
Vila '" Oto2V, f'" 1 MHz
TE, DE, and SC low
t All typical values are at Vcc '" 5 V. TA '" 25°C.
* VOH applies for 3-state outputs only.
POST OFFICE BOX 655303 • DAUAS, TEXAS 75265
mA
2.5
VI (bus) ",OVto2.5V
ICC
V
-3.2
0
VI(bus) '" 3.7 Vto 5 V
Short-circuit oUtput current
V
-1.3
VI (bus) =2.5 Vto 3.7 V
lOS
2-430
-1.5
Terminal
Power off
CIIO(bus)
MAX
-0.8
0.65
VI/bus) = 0.4 V to 2.5 V
Current into bus port
TYpt
0.4
VI(bus) ",-1.5VtoO.4V
1110 (bus)
MIN
11=-18mA
110
30
tAA
mA
mA
pF
SN75161 B, SN75162B
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVERS
SUSOOSA- 02618, OCTOBER 1980- REVISED FEBRUARY 1993
switching characteristics,
Vee = 5 V, CL = 15 pF, TA = 25°C (unless otherwise noted)
PARAMETER
tpLH
Propagation delay time, Iow-to-hlgh level output
tpHL
Propagation delay time, hlgh-to-Iow level output
tPLH
Propagation delay time, low-to-high level output
tPLH
Propagation delay time, low-to-high level output
tpHL
Propagation delay time, hlgh-to-Iow level output
tpZH
Output enable time to high level
tpHZ
Output disable time from high level
tpZL
Output enable time to low level
tpLZ
Output disable time from low level
tpZH
Output enable time to high level
tpHZ
Output disable time from high level
tpZL
Output enable time to low level
tPLZ
Output disable time from low level
FROM
(INPUT)
TO
(OUTPUT)
TEST
CONDITIONS
Terminal
Bus
CL=30 pF,
See Figure 1
Terminal
Bus
(SRO, NDAC
NRFD)
CL=30 pF,
See Figure 1
Bus
Terminal
CL=30 pF,
See Figure 2
TE,DC,
or
SC
Bus (ATN,
EOI, REN,
IFC, and
DAV)
MIN
TYP
MAX
14
20
14
20
29
35
10
20
15
22
UNIT
ns
ns
ns
60
See Figure 3
45
60
ns
55
55
TE,DC,
or
SC
Terminal
See Figure 4
50
45
ns
55
POST OFFICE BOX 655303 • DALlAS, TEXAS 75266
2-431
SN75161B, SN75162B
OCTAL GENERAL·PURPOSE INTERFACE BUS TRANSCEIVERS
SLLSOO5A- 02618. OCTOBER 1980 - REVISED FEBRUARY 1993
PARAMETER MEASUREMENT INFORMATION
5V
4.3 V
2400
From (Bus)
Output Under Test
From (Terminal)
Output Under --..----4~
Test
---4-....-- Test Point
........-
.....
CL=30pF
I
LOAD CIRCUIT
-'..&
Ten:::~
P
~'
tpLH
V
-J-.il
BUB
Output-:;:""'_J
CL=30pF
I
4800
(_Note A)
(eee Note A)
Test Point
3kO
LOAD CIRCUIT
~1-~--
1\
tPHL -J..-.I
(eee Note B)
3V
IB,:
OV
np
tPLH
Ir---....;.;~......,.-I--- VOH
2.2 V
I
~~&~--
-'..&V
--Ii'
-l-iI '
Terminel
Output _ _.1
VOLTAGE WAVEFORMS
(eee Note B)
1.&V
tpHL
1\
--!+--...;
T--
VOH
1.&V
VOLTAGE WAVEFORMS
Figure 1. Terminal·to·Bus
Load Circuit and Voltage Waveforms
3V
0V
VOL
Figure 2. Bus-to·Termlnal
Load Circuit and Voltage Waveforms
NOTES: A. CL includes probe and jig capacKance.
B. The Input pulse is supplied by a generator having the following characteristics: PRR " 1 MHz. 50% duty cycle. tr " 6 ns. tf " 6 ns,
ZO=500.
1ExAs
..If
INSIRUMENTS
2-432
POST OFFICE BOX 655303 • DAUAS. TEXAS 75265
SN75161B,SN75162B
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVERS
SLLSOO511.- 02618. OCTOBER 1980 - REVISED FEBRUARY 1993
PARAMETER MEASUREMENT INFORMATION
S1
0--
S1
SV
2400
From (Terminal)
Output Under --'--~----il"'-- Test Point
2000
From (Bus)
Output Under -
......- - . - -......-Test Point
Test
Test
I
CL=1SpF
(see Note A)
I
4800
Control
-l1.SV
ji-1.SV
Inp~_ _/I'_ _ ~!!"~!.!'L.J I \. _ _ _ _ 0 V
r-
- - - - VOH
90%
±--i
Bus
Output
S1 Closed
tpHZ -J
I
•
2V
"
I
I
tpLZ
3kO
--, r-------,/-----3V
--, r-------, r----
3V
Control ¥1.SV
i"1.SV
I~I~./I'_ _ ~II!!I~!.!'LJI\. _ _ _ _ 0 V
14-
CL=1SpF
(see Note A)
LOAD CIRCUIT
LOAD CIRCUIT
tpZH -J
Bus I
Output I
S1 Open
tpZL
0 - - 4.3V
OV
tpZH -J
Output
I
Terminal
I
S10pen
14-
tpZL-to!
fotI
-t--t
k
10V
:
VOLTAGE WAVEFORMS
I
3 SV
O~y"_ VOL
.
Terminal
Output
S1 Closed
tPHZ-J
I
1.S V
I-
""io% - -
I
I
tPLZ-.t
VOH
OV
4V
1.0V
" -_ _ _ _ _~O.:! 'L _ VOL
VOLTAGE WAVEFORMS
Figure 3. Bus Enable and Disable Times
Load Circuit and Voltage Waveforms
Figure 4. Terminal Enable and Disable Times
Load Circuit and Voltage Waveforms
NOTES: A. CL includes probe and jig capacHance.
B. The Input pulse is supplied '?Y a generator having the following characteristics: PRR " 1 MHz. 50% duty cycle. tr " 6 ns. tf " 6 ns.
ZO=50Q.
1ExAs
..If
INSIRUMENTS
POST OFFICE BOX 655303 • DAUAS. TEXAS 75265
2-433
SN75161B, SN75162B
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVERS·
SUSOO5A- 02618, OCTOBER 1980 - REVISED FEBRUARY 1993
TYPICAL CHARACTERISTICS
TERMINAL HIGH.LEVEL OUTPUT VOLTAGE
vs
HIGH·LEVEL OUTPUT CURRENT
LOW·LEVEL OUTPUT CURRENT
4
>I
•
f
~
1.5
a.
1.5
0
~
3,S
...........
3
TA=25°C-
>
t
1,5
:f
I
"" ,
I\.
O,S
o
-S
-10
~
0,4
6
0,3
!
0,2
1
'\
2
I
VCC=5V
TA=25°C
O,S
I
r\.
'\
2,S
o
0,6
~CC=~V
01
~
TERMINAL LOW·LEVEL OUTPUT VOLTAGE
VS
-20
-1S
-25
"
-30
1
I
..J
~
-35
./
/
V
V
o
-40
o
10
20
Figure 6
TERMINAL OUTPUT VOLTAGE
vs
BUS INPUT VOLTAGE
4
VCC=5V
3.S
r- NoLoed
TA=25°C
3
I
II
I
2.5
1.5
2
!
I
VT-
VT
1,5
~
O,S
o
o
0.2 0,4 0,6 0,8
1
1.2 1.4 1.6 1,8
VI-Input Voltage - V
Figure 7
2-434
30
40
60
IOL - Low·Level Output Current - mA
Figure 5
~
V
/
0.1
IOH - High·Level Output Current - mA
>
/
/
1ExAs'"
INSIRUMENTS
POST OFFICE BOX 655303 • DAUAS, TEXAS 75l!65
2
60
SN75161 B, SN75162B
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVERS
SLLSOOSA- 0261
a. OCTOBER 1980 - REVISED FEBRUARY 1993
TYPICAL CHARACTERISTICS
BUS HIGH-LEVEL OUTPUT VOLTAGE
va
HIGH-LEVEL OUTPUT CURRENT
LOW-LEVEL OUTPUT CURRENT
0
>
I
II
f
'SQ.
'S
0
3
0.6
VCC~5V
TA=25°C
~
2
]
.c
ell
:f
I
:z::
:9
o
BUS LOW-LEVEL OUTPUT VOLTAGE
va
o
=;- 0.5
f
1\
1\
1\
I
I
VCC=5V
TA=25°C
::>
J
/
0.4
/
0.3
~
~ 0.2
..J
I
..J
:9
-10
-20
-40
-30
-50
IOH - High-Level Output Current - mA
~
V
V
/'
~
/
./
V
0.1
o
-60
o
10
20 30 40 50 60 70 60 90 100
IOL - Low-Level Output Current - mA
Figure 8
Figure 9
BUS OUTPUT VOLTAGE
BUS CURRENT
vs
vs
THERMAL INPUT VOLTAGE
BUS VOLTAGE
VCC=5V
No Load
TA=25°C
2
~
I
0
!I
-2
1
-1
~~~~~"'I""-""""''''''''''---"ooIC---n.~,..e.;~
~~~~~t711-~~~~
~--+--+--"~-+----l--Ro!'~~~
III
I
ie
j
1.1
1.2 1.3 1.4 1.5
VI -Input Voltage - V
1.6
1.7
-3~-t-1Ti~~~~~~~~~
-4~-4~~~~~~~~~~~~
-5 ,",--+--f-+--+<'i~~ The Unshaded
Area Conforms to
-6 ~--+--L-+-~~1'<" Paragraph 3.5.3 of
IEEE Standard 486-1978
-7~~-~~~~------------~
~
~
0
234
5
6
Vuo(bua) - Bus Voltage - V
Figure 10
Figure 11
1ExAs ."
INSIRUMENfS
POST OFFICE BOX 655303 • DAUAS, TEXAS 75265
2-435
2-436
SN55ALS161, SN75ALS161
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVERS
19B6-REVISED
1993
SUITABLE FOR IEEE STANDARD 488-1978 (GPIB)t
•
•
•
•
•
•
•
•
•
•
•
a-Channel Bidirectional Transceiver
Designed to Implement Control Bus
Interface
Designed for Single Controller
High-Speed Advanced Low-Power Schottky
Circuitry
Low-Power Dissipation:
SN55ALS161 ••• 59 mW Max Per Channel
SN75ALS161 •.• 46 mW Max Per Channel
Fast Propagation Times:
SN55ALS161 ••• 25 ns Max
SN75ALS161 ••• 20 ns Max
High-Impedance PNP Inputs
Receiver Hysteresis:
SN55ALS161 ••• 550 mV Typ
SN75ALS161 •.• 650 mV Typ
Bus-Terminating Resistors Provided on
Driver Outputs
No Loading of Bus When Device Is
Powered Down (Vec = 0)
Power-Up/Power-Down Protection
(Glitch Free)
SN55ALS161 ••• J OR W PACKAGE
SN75ALS161 ••• DW OR N PACKAGE
(TOP VIEW)
TE
IFC
GPIB
I/O
Ports
NDAC
NDAC
NRFD
NRFD
DAV
6
DAV
EOI
ATN
SRo
7
8
9
GND
10
DC
ATN
Terminal
110 Ports
EOI
SRo
SN55ALS161 ••• FK PACKAGE
(TOP VIEW)
o
Z
Oz
!:!:It!I!:!?lt!
NDAC
NRFD
DAV
EOI
ATN
description
The SN55ALS161 and SN75ALS161 eightchannel
general-purpose
interface
bus
monolithic,
high-speed,
transceivers
are
advanced low-power Schottky process devices
deSigned to provide the bus-management and
data-transfer signals between operating units of a
single controller instrumentation system. When
SN55ALS160
and
combined
with
the
SN75ALS160 octal bus transceivers, the'ALS161
provides the complete 16-wire interface for the
IEEE 488 bus.
VCC
REN
3 2 1 20 19
18
17
5
16
6
4
7
8
15
14
9 10 11 12 13
IFC
NDAC
NRFD
DAV
EOI
CHANNEL IDENTIFICATION TABLE
NAME
DC
TE
ATN
SRO
REN
IFC
EOI
DAV
NDAC
NRFD
IDENTITY
Direction Control
Talk Enable
Attention
Service Request
Remote Enable
Interface Clear
End or Identify
DataYalId
Not Data Accepted
Not Ready for Data
CLASS
Control
Bus
Management
The SN55ALS161 and SN75ALS161 feature
Data
eight driver-receiver pairs connected in a front-toTransfer
back configuration to form input/output (I/O) ports
at both the bus and terminal sides. The direction
of data through these driver-receiver pairs is determined by the DC and TE enable signals.
The driver outputs (GPIB I/O ports) feature active bus-terminating resistor circuits designed to provide a high
impedance to the bus when VCC =O. The drivers are designed to handle loads up to 48 rnA of sink current. Each
receiver features pnp transistor inputs for high input impedance and hysteresis of 400 mV on the commercial
part, 250 mV on the military part minimum for increased noise immunity. All receivers have 3-state outputs to
present a high impedance to the terminal when disabled.
t The transceivers are sunable for I EEE Standard 488 applications to the extent of the operating condnions and characteristics specified in this
data sheet. Certain limns contained in the IEEE specification are not met or cannot be tested over the entire military temperature range.
Copyright@ 1993. Texas Instruments Incorporated
1ExAs ...,
INSIRUMENTS
POST OFFICE BOX
e55303 • DAllAS, TEXAS 75265
2-437
SN55ALS161, SN75ALS161
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVERS
SLLS019C - 02618, JUNE 1986 - REVISED FEBRUARY 1993
description (continued)
The SN5ALS161 is characterized for operation from -55°C to 125°C. The SN75ALS161 is characterized for
operation from O°C to 70°C.
logic symbol t
DC
11
TE
logic diagram (positive logic)
EN1/G4
EN2/G5
5 '" 1
ATN
EO!
SRQ
REN
IFC
DAV
NDAC
NRFD
13
8
14
7
12
9
19
2
18
3
15
6
17
4
16
5
ATN
ATN 13
8
ATN
EOI
SRQ
REN
EOl 14
7 'EOI
SRQ12
9
REN 19
2
IFC 18
3
DAV 15
6
NDAC 17
4
NRFD 16
5
SRQ
IFC
REN
DAV
NDAC
IFC
NRFD
DAV
t This symbol is in accordance with ANSI/IEEE Std 91-1984 and
lEe Publication 617-12.
V Designates 3-state outputs
~
Designates passlve-pullup outputs
2-438
NDAC
NRFD
SN55ALS161, SN75ALS161
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVERS
SUS019C - 02618, JUNE 1986 - REVISED FEBRUARY 1993
RECEIVE/TRANSMIT FUNCTION TABLE
CONTROLS
DC
TE
BUS-MANAGEMENT CHANNELS
ATNt
ATNt
SRQ
REN
DATA-TRANSFER CHANNELS
EOI
IFC
DAV
H
H
H
H
H
L
R
T
R
NDAC
NRFD
(controlled by TE)
(controlled by DC)
R
T
~
T
R
R
L
H
L
R
T
T
R
R
T
T
T
L
L
L
~
H
T
T
R
L
X
R
T
R
R
R
H
L
X
R
T
T
T
T
R
R
T
H =high level, L =low level, R =receive, T =transmH, X =Irrelevant
Direction of data transmission is from the terminal side to the bus side, and the direction of data receiving is from the bus side to the terminal side.
Data transfer is noninverting in both directions.
t ATN is a normal transceiver channel that functions additionally as an internal direction control or talk enable for EOI whenever the DC and TE
inputs are in the same state. When DC and TE are in opposHe states, the ATN channel functions as an independent transceiver only.
TEXAS
..If
INSIRUMENlS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2-439
SN55ALS161, SN75ALS161
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVERS
SLLSOl9C - D2618, JUNE 1986 - REVISED FEBRUARY 1993
schematics of Inputs and outputs
EQUIVALENT OF ALL CONTROL INPUTS
TYPICAL OF SRQ, NDAC, AND NRFD OPIB VO PORT
VCC-------.-------eka
NOM
10kO
NOM
Input
I _ _ _ _ .J
GND--.----*-----*--
Input/Output Port
Circuit inside dashed lines is on the driver outputs only.
TYPICAL OF ALL I/O PORTS EXCEPT SRQ, NDAC, NRFD OPIB VO PORTS
10kO
NOM
I _ _ _ _ .J
Input/Output Port
Driver output Req '" 30 0 NOM
Receiver output Req '" 110 g NOM
Circuit inside dashed lines is on the driver outputs only.
1ExAs ,.,
INSIRUMENTS
2-440
POST OFFICE BOX e55303 • DAUAS. TEXAS 75265
SN55ALS161, SN75ALS161
OCTAL GENERAL·PURPOSE INTERFACE BUS TRANSCEIVERS
SLLSOl9C - 02618, JUNE 1986 - REVISED FEBRUARY 1993
absolute maximum ratings over operating free·air temperature range (unless otherwise noted)
Supply voltage. Vee (see Note 1) ............................................................. 7 V
Input voltage ............................................................................. 5.5 V
Low-level driver output current ............................................................ 100 mA
Continuous total dissipation ........................................... See Dissipation Rating Table
Operating free-air temperature range: SN55ALS161. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -55°C to 125°C
SN75ALS161 ................................... DoC to 70°C
Storage temperature range ....................................................... - 65°C to 150°C
Case temperature for 60 seconds: FK package .............................................. 260°C
Lead temperature 1,6 mm (1/16 inch) from the case for 60 seconds: J or W package ............. 300°C
Lead temperature 1,6 mm (1/16 inch) from the case for 10 seconds: DWor N package ........... 260°C
NOTES: 1. All voltage values are with respect to network ground terminal.
DISSIPATION RATING TABLE
PACKAGE
TAs25°C
POWER RATING
=
OPERATING
FACTOR
TA 70°C
POWER RATING
720mW
=
TA 125°C
POWER RATING
OW
1125mW
9.0mWrC
FK
1375mW
11.0mWrC
aaOmW
275mW
J
1375mW
11.0mW/"C
SSOmW
275mW
N
1150mW
9.2mW/"C
736mW
W
1000mW
S.OmW/"C
640mW
200mW
SN55ALS161 recommended operating conditions
Supply voHage, VCC
TE and DC at TA = -55°C to 125°C
High-level input voHage, VIH
Bus and terminlll at TA
Bus and terminal at TA
Low-level input voHage, VIL
High-level output current, IOH
Low-level output current, IOL
=25°C to 125°C
=-55°C
MIN
NOM
MAX
UNIT
4.75
5
5.25
V
2
V
2
2.1
=-55°C to 125°C
=25°C to -55°C
Bus and terminal at TA =125°C
TE and DC at TA
O.B
Bus and terminal at TA
0.8
Bus ports with PUIIUPS active (VCC
= 5 V)
Terminal ports
-5.2
rnA
-SOO
I-IA
Bus ports
48
Terminal ports
16
-55
Operating free-air temperature, TA
V
0.7
125
rnA
°c
SN75ALS171 recommended operating conditions
Supply voHage, VCC
High-level input voHage, VIH
MIN
NOM
MAX
UNIT
4.75
5
5.25
V
Low-level input voHage, VIL
High-level output current, IOH
Low-level output current, IOL
V
2
0.8
Bus ports with PUIIUPS active
Terminal ports
rnA
-SOO
I-IA
Bus ports
48
Terminal ports
16
Operating free-air temperature, TA
0
1ExAs
V
-5.2
70
rnA
°c
~
INSIRUMENTS
POST OFFICE BOX 655303 • DAUAS, TEXAS 75265
2-441
I
electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise
noted)
PARAMETER
VIK
SN55Al.S161
TEST CONDITIONSt
Input clamp voltage
MIN
11=-18mA
SN75ALS161
TYp:l:
MAX
-0.8
-1.5
Bus
Vhys
VOH§
VOL
~
II~~r
Hysteresis (\IT+ -
\for....)
High-level output voltage
Low-level output voltage
II
Input current at maximum
input voltage
IIH
High-level input current
IlL
Low-level Input current
VVO{bus)
Terminal
0.4
Vee=5V,
TA = -55°C and 25°C
Vee=5V,
TA= 125°C
10H = - 800 IlA
2.7
Bus
IOH =-5.2mA.
Vee,;, 5 V (SN55,
IQl=16mA,
Vee= MIN
Bus
10L= 48 mA.
Vee= MIN
-0.8
-1.5
V
!I'
V
2.7
V
2.2
0.5
0.3
0.5
TA = -55°C and 25°C
(SN551
0.35
0.5
0.35
0.5
TA = 25"0 (SN551
0.35
0.5
0.35
0.5
V
Vee= MAX
0.2
100
0.2
100
IlA
Terminal
and control
Inputs
VI = 2.7 V,
Vee= MAX
0.1
20
0.1
20
IlA
VI =0.5 V,
Vee= MAX
-30
-100
-10
-100
IlA
2.5
Power on
Power off
Driver disabled,
Vee = 5 V (SN55'
Vee=O
3.7
2.5
3
-1.5
-1.3
j
3.7
-1.5
V
ZO)
rn,:A
~~
r;- ....
"U~
~
m
$"U_
Iii
III
."
(/)-
i
rn
i
00)
rn
Z
-I
::D
~
0
rn
m
c:
-I
~
Z
(/)
-3.2
0
C)1ii
rn-
(/)
-1.3
-3.2
0
0
VI(bus) = 3.7 Vto 5 V
0
2.5
0
2.5
rn
<:
rn
VI(bus) = 5 Vto 5.5 V
0.7
2.5
0.7
2.5
(/)
2.5
-3.2
VI{bus) = 2.5 Vto 3.7 V
Short-circuit output current
ICC
Supply current
No load,
TE and DC low,
eVO(btJs)
Bus-port capacitance
Vee=Ot05V,
VVO=Ot02V,
Vee= MAX
Vee = MAX
f= 1 MHz
t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating condHions.
:I: All typical va/uas are at Vee = 5 V, TA = 25°C.
2.5
-3.2
40
VI{blJ§} = 0 to 2.5 V
lOS
§VOH and lOS apply to 3-stale outputs only.
3
II/bus) =-12 mA
Terminal
Bus
z
m
c
VI = 5.5 V,
11(bus) =0
...c:
:D
3.5
Terminal
Driver disabled,
Vee = 5 V (SN551
~
I
3.5
O(/)
OZ
);!8I
'" .»
III
I
c
0.65
0.3
VI (bus) = 0.4 V to 2.5 V
Current into bus port
MAX
0.55
2.2
VI(bus) =-1.5VtoO.4 V
11/0{bus)
0.4
TYp:l:
~
g
UNIT
0.25
Terminal
Voltage at bus port
~ Ul4'
I
Bus
MIN
(J)
40
-15
-35
-75
-15
-35
-75
-25
-50
-125
-25
-so
-125
55
90
55
75
30
30
mA
::D
IlA
mA
mA
pF
SN55ALS161
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVER
SLLSOl98 - 02618, JUNE 1986 - REVISED FEBRUARY 1993
SN55ALS161 switching characteristics Vee = 4.75 V,
(unless otherwise noted)
PARAMETER
tpLH
Propagation delay time,
low-to-high-Ieveloutput
tpHL
Propagation delay time,
hlgh-to-Iow-Ievel output
tpLH
Propagation delay time,
low-to-high-Ievel output
tpHL
Propagation delay time,
high-to-Iow-Ieveloutput
tpLH
Propagation delay time,
low-to-high-Ievel output
tpHL
Propagation delay time,
high-to-Iow-Ievel output
tpZH
tpHZ
FROM
(INPUT)
TO
(OUTPUT)
Terminal
Bus (Except
SRO, NDAC,
andNRFD)
Terminal
Bus (NRFD,
SRO, NDAC)
See Figure 1
See Figure 2
Bus
Terminal
Output enable time to high level
tpHZ
Output disable time from high level
tpZL
Output enable time to low level,
tpLZ
Output disable time from low level
tpZH
Output enable time to high level
Output disable time from high level
tpZL
Output enable time to low level
10
25°C
See Figure 2
10
25°C
25
25°C
30
10
25°C
10
15
20
30
41
8
14
16
28
16
Bus (EOI)
See Figure 3
24
13
21
13
TEorDC
Terminal
See Figure 4
24
Output disable time from low level
Full range
36
20
33
20
34
13
24
ns
41
Full range
25°C
20
50
12
Full range
25°C
ns
27
Full range
25°C
35
43
Full range
25°C
19
25
Full range
25°C
30
48
Full range
25°C
19
24
Full range
25°C
ns
34
10
Full range
25°C
ns
18
Full range
25°C
ns
15
18
Full range
25°C
14
ns
16
10
Full range
25°C
See Figure 3
14
16
Full range
UNIT
17
20
Full range
Bus (ATN,
REN,IFC,
andDAV)
MAX
Full range
25°C
TEorDC
tpHZ
TYP*
Full range
Output enable time to low level
tpZH
MIN
Full range
25°C
Output disable time from high level
Output disable time from low level
TAt
Full range
Output enable time to high level
tpLZ
tpLZ
TEST
CONDITIONS
25°C
TEorDC
tpZL
Vee = 5 V, and Vee = 5.25 V and CL = 50 pF
35
t Full range is -55°C to 125°C.
All typical values are at VCC = 5 V.
*
1ExAs
~
INSIRUMENIS
POST OFFICE BOX 6S5303 • DAUAS, TEXAS 75265
2-443
SN55ALS161, SN75ALS161
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVERS
SLLS019B - 02618, JUNE 1986 - REVISED FEBRUARY 1993
SN75ALS161 switching characteristics over recommended range of operating free-air
temperature, VCC 5 V
=
PARAMETER
tpLH
Propagation delay time,
low-to-high-Ievel output
tpHL
Propagation delay time,
high-to-Iow-Ievel output
tpLH
Propagation delay time,
low-to-high-Ievel output
tpHL
Propagation delay time,
high-to-Iow-Ievel output
TO
FROM
(INPUT)
(OUTPUT)
Terminal
Bus
TEST
CONDITIONS
TYpt
MAX
10
20
12
20
5
10
7
14
CL=30pF,
See Figure 1
UNIT
ns
CL=30pF,
See Figure 2
Terminal
Bus
MIN
ns
30
tpZH
Output enable time to high level
tpHZ
Output disable time from high level
tPZL
tpLZ
Output enable time to low level
Output disable time from low level
20
tpZH
Output enable time to high level
30
tpHZ
Output disable time from high level
tpZL
Output enable time to low level
tpLZ
Output disable time from low level
TE or DC
TE or DC
Bus (ATN, EOI,
REN, IFC, and
DAV)
20
CL=15pF,
See Figure 3
45
25
CL=15pF,
See Figure 4
Terminal
30
ns
ns
25
t All typical values are at TA = 25°C,
PARAMETER MEASUREMENT INFORMATION
5V
[7 V]
4.3 V
[7 V]
2400
2000
[500 OJ
From (bus)
Ou1pu1 Under
Test
---411-----+-..-CL=30pF
• [50 pF]
(see Note A)
T
[500 OJ
Test Polm
From (terminal)
Ou1pu1 Under
Test
-_>-------4.--_~
T
4800
[500 OJ
L,.5V
--.II
----3V
\,.5V
(see Note B)
tPLH-l++!
Bus
Ou1pu1
luv
3kO
[SOOO]
LOAD CIRCUIT
LOAD CIRCUIT
Terminal
Inpu1
CL=30pF
= [50 pF]
(see Note A)
Test Polm
tpHL
I
~
0V
,~tVOH
---
~:t
~.SV
---'I
I·
tPHL~L
(see Note B)
tpLH ~
11 ,.sv
Terminal
Ou1pu1
\1.5V--
.
,.sv
\L - -
3V
0V
VOH
~
VOL
VOH
VOLTAGE WAVEFORMS
VOLTAGE WAVEFORMS
Figure 1. Termlnal-ta-Bus
Load Circuit and Voltage Waveforms
Figure 2. Bus-to-Terminal
Load Circuit and Voltage Waveforms
[I denotes the SN55ALS161 military test conditions.
NOTES: A. CL includes probe and jig capacitance.
B. The input pulse is supplied by a generator having the following characteristics: PRR s 1 MHz, 50% duty cycle, tr s 6 ns, tf S 6 ns,
ZQ=50C,
1ExAS ..If
INSIRUMENTS
2-444
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
SN55ALS161, SN75ALS161
OCTAL GENERAL·PURPOSE INTERFACE BUS TRANSCEIVERS
SLLS019B - 02618. JUNE 1986 - REVISED FEBRUARY 1993
PARAMETER MEASUREMENT INFORMATION
S1
S1
0--&V
[7 V]
2000
From (bus)
[500 0]
Output Under --.---.--+-- Test Point
Test
T
CL=1&pF
= [50 pF]
(see Note A)
From (terminal)
Output Under
Test
0--4.3V
[7 V]
2400
[500 0]
--.----*--+-- Test Point
4800
[5000]
T
CL=1&pF
= [50 pF]
(see Note A)
3kO
[5000]
LOAD CIRCUIT
LOAD CIRCUIT
- - , - - - - - - - , - - - - - 3V
Control
~
~
Input
"'\ 1.& V (see Note B)
1.& V
~
~
1.& V (see Note B)
1.& V
__ JI"'\_______
-JI1'\.....
- - - - ov
tPZH-+i i+tpHZ -+i I+V
Terminal
I 11
I ~90%
- - OH
S~~::
I
1.&V
I
I
OV
tPZL ::;i
tPL2 -+t
4V
1'\
__ JI _______ -J I ..... - - - tpZH-+i
i+tpHZ -+t I+-
Bus
Output
S10pen
~I
I
~
I
tpZL
s1gi::
I~so%--
I
I
2V
\
tpL2
4
1V
OV
V
OH
ov
k
-
3.& V
- - , _______,
r- _
i
51
ir -
'X
Terminal
VOL
_---- 3 V
Control
Input
g:
,
1V
lo.!."v__
VOL
VOLTAGE WAVEFORMS
VOLTAGE WAVEFORMS
Figure 3. Bus Load Circuit and
Voltage Waveforms
Figure 4. Terminal Load Circuit and
VoHage Waveforms
[1 denotes the SN55ALS161 military test conditions.
NOTES: A. CL includes probe and Jig capacitance.
B. The Input pulse is supplied by a generator having the following characteristics: PRR " 1 MHz. 50% duty cycle. Ir " 6 ns. If " 6 ns.
ZO=500.
1ExAs
,If
INSIRUMENTS
POST OFFICE BOX 655303 • OAlL\S. TEXAS 75265
2-445
SN55ALS161, SN75ALS161
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVERS
SLLSOl98 - 02618. JUNE 1986 - REVISED FEBRUARY 1993
TYPICAL CHARACTERISTICS
TERMINAL HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
LOW-LEVEL OUTPUT CURRENT
4
>I
3.5
f
3
•
~
g5
~
.c
.........
2.5
,
TA=25°C -
0.5
o
~
0.4
0
0.3
~
'"
:r
0.5
5Q.
5
'\.
1.5
>I
•
I
'\
2
o
0.6
V~C=~V
'\
lI
.p
TERMINAL LOW-LEVEL OUTPUT VOLTAGE
vs
~
VCC~5V
'\
'-
V
/
0.1
o
-5 -10 -15 -20 -25 -30 -35 -40
IOH - High-level Output Current - rnA
o
10
30
50
20
40
IOL - LOW-Level Output Current - rnA
Figure 5
Figure 6
TERMINAL OUTPUT VOLTAGE
vs
BUS INPUT VOLTAGE
4
I
1
VCC=5V
NoLoed
TA = 25°C
3.5
>
3
I
f
2.5
5
2
I
1.5
!
0
VT-
VT+
.p
0.5
o
o
0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8
VI-Input Voltage - V
Figure 7
1ExAs ."
INSIRUMENTS
2-446
/
/
..I
r\.
V
/
0.2
I
.p
/
TA=25°C
V
POST OFFICE BOX 655303 • DAUAS. TEXAS 75265
2
60
SN55ALS161, SN75ALS161
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVERS
SLlSOl9B - 02618. JUNE 1986 - REVISED FEBRUARY 1993
TYPICAL CHARACTERISTICS
BUS HIGH-LEVEL OUTPUT VOLTAGE
BUS LOW-LEVEL OUTPUT VOLTAGE
vs
vs
BUS HIGH-LEVEL OUTPUT CURRENT
BUS LOW-LEVEL OUTPUT CURRENT
0.6
4
VCC=5V
TA=25°C
>I
~
•
0.5
V~
CIt
J!I
'" '"
~
-10
-20
"
-30
,/
0
0.3
I
0.2
~
0.1
!..
'\
'"
-40
o~~~--~~--~~~~~~~
-50
o
-60
10
20
30
40
50
60
70
80
90 100
IOL - Low.l,evel Output Current - mA
Figure 9
BUS CURRENT
vs
vs
TERMINAL INPUT VOLTAGE
BUS VOLTAGE
VCC=5V
NoLoed
TA = 25°C
2
3r-~---r--;---~~---+--~~
~
I
•
f
1
V
/
BUS OUTPUT VOLTAGE
>I
,/
V"
V
./
IOH - High-Level Output Current - mA
Figure 8
/
/"
0.4
'S
CL
'S
'-
o
o
~
I
VCC=5V
TA=25°C
I
o
-1
U
!
2
'S
III
o
I
-2
-3
J8.-4
I
~
~
-6
o~~--~--~~--~--~~--~
0.9
1.1
1.2
1.3
1.4
1.5
1.6
1.7
VI-Input Voltage - V
VVO(bus) - Bus Voltage - V
Figure 10
Figure 11
TEXAS
..If
INSlRl.JMENTS
POST OFFICE BOX 655300 • DAllAS. TEXAS 75265
2-447
2-448
SN75ALS162
OCTAL GENERAL·PURPOSE INTERFACE BUS TRANSCEIVER
SUS020B
JUNE 1986 - REVISED AUGUST 1989
MEETS IEEE STANDARD 488-1978 (GPIB)
•
•
•
•
•
•
•
•
•
•
•
8-Channel Bidirectional Transceiver
Designed to Implement Control Bus
Interface
Designed for Multlcontrollers
High-Speed Advanced Low-Power Schottky
Circuitry
Low-Power Dissipation .•• 46 mW Max per
Channel
Fast Propagation Times •.. 20 ns Max
High-Impedance PNP Inputs
ow PACKAGE
(TOP VIEW)
GPIB
I/O Ports
Receiver Hysteresis .•• 650 mV lYP
Bus-Terminating Resistors Provided on
Driver Outputs
No Loading of Bus When Device Is
Powered Down (Vee = 0)
Power-Up/Power-Down Protection
(Glitch Free)
SC
TE
AEN 3
IFC 4
NDAC
NAFD
DAV
EOI
ATN 9
SAC
NC
GND
24
23
22
21
20
19
18
17
16
15
14
13
Vcc
NC
AEN
IFC
NDAC
NAFD
DAV
EOI
ATN
SAC
NC
DC
Terminal
I/O Ports
NPACKAGE
(TOP VIEW)
VCC
NC
AEN
IFC
NDAC
NRFD
DAV
EOI
ATN
SRC
description
The SN75ALS162 eight-channel generalpurpose interface bus transceiver is a monolithic,
high-speed, advanced low-power Schottky
process device designed to provide the busmanagement and data-transfer signals between
multiple-controller
operating
units of a
instrumentation system. When combined with the
SN75ALS160 octal bus transceiver, the
SN75ALS162 provides the complete 16-wire
interface for the IEEE 488 bus.
GPIB
I/O Ports
DAV
EOI
ATN
SRC
GND
11
Terminal
I/O Ports
DC
The SN75ALS162 features eight driver-receiver
NC-No internal connection
pairs connected in a front-to-back configuration to
form input/output (I/O) ports at both the bus and terminal sides. The direction of data through these
driver-receiver pairs is determined by the DC, TE, and SC enable signals. The SC input allows the REN and
IFC transceivers to be controlled independently.
The driver outputs (GPIB 110 ports) feature active bus-terminating resistor circuits designed to provide a high
impedance to the bus when VCC = O. The drivers are designed to handle loads up to 48 mA of sink current. Each
receiver features pnp transistor inputs for high input impedance and hysteresis of 400 mV minimum for
increased noise immunity. All receivers have 3-state outputs to present a high impedance to the terminal when
disabled.
The SN75ALS162 is characterized for operation from O·C to 70·C.
1ExAs
~
Copyright © 1989. Texas Instruments Incorporaled
INSIRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
2-449
SN75ALS162
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVER
SUS020B - 02618, JUNE 1986- REVISED AUGUST 1989
CHANNEL IDENTIFICATION TABLE
NAME
DC
IDENTITY
TE
Talk Enable
SC
System Control
Control
ATN
Attention
SRO
Service Request
REN
Remote Enable
IFC
Interface Clear
EOI
End or Identify
DAV
DatavaJld
NDAC
No Data Accepted
NRFD
Not Ready for Data
logic symbol t
EN1/G4
TE2
EN2IG5
SC
EN3
,,1
6
ATN 14
SRO
8
13
10
IFC 19
DAY 16
NRFD
9
15
REN 20
NDAC
Bus Management
Data Transfer
logic diagram (positive logic)
DC 12
EOI
CLASS
Direction Control
3
4
7
18
5
17
6
9 ATN
ATN
EOI 15
EOI
SRQ 13
10 SRQ
REN 20
3 REN
IFC 19
4 IFC
DAY 16
7 DAY
REN
IFC
DAY
NDAC
NRFD
NDAC 18
5 NDAC
NRFD 17
6 NRFD
Pin numbers shown are for the N package.
1ExAS
,If
INSIRUMENTS
2--450
EOI
SRO
t This symbol is in accordance wHh ANSI/IEEE SId 91-1984 and
IEC Publication 617-12.
V Designates 3-state outputs
~ Designates passlve-pullup outputs
8
POST OFFICE BOX 655303 • OAUAS, TEXAS 75265
SN75ALS162
OCTAL GENERAL·PURPOSE INTERFACE BUS TRANSCEIVER
SLLS020B - D261 S. JUNE 1986 - REVISED AUGUST 1989
RECEIVE/TRANSMIT FUNCTION TABLE
DAV
SC
NDAC
NRFD
(controlled by TE)
T
R
R
Direction of data transmission Is from the terminal side to the bus side, and the direction of data receiving is from the bus side to the terminal side.
Data transfer is noninverting in both directions.
t ATN is a normal transceiver channel that functions addHionaily as an internal direction control or talk enable for EOI whenever the DC and TE
inputs are in the same state. When DC and TE are in opposHe states, the ATN channel functions as an independent transceiver only.
schematics of inputs and outputs
EQUIVALENT OF ALL
CONTROL INPUTS
vcc------~-------9ke
NOM
TYPICAL OF SRQ, NDAC, AND NRFD
GPIBVOPORT
-..-----HI---~-i---.....--_.._- VCC
10ke
NOM
Input
GND--~-~--~-
--4--~-+~L~__
~
__
- __
- __
~~~~--~-------GND
Input/Output Port
Circuit inside dashed lines is on the driver outputs only.
TYPICAL OF ALL VO PORTS EXCEPT SRQ, NDAC, NRFD GPIB VO PORTS
- . - - -.....---~r.--_.;---~---~-VCC
--~~-_*~~~-~~~--~-------- GND
Input/Output Port
Driver output Req =30 g NOM
Receiver output Req = 110 g NOM
Circuit inside dashed lines is on the driver oul uts
1ExAs
~
INSIRUMENTS
POST OFFICE BOX 655303 • DAllAS, TEXAS 75265
2-451
SN75ALS162
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVER
SUS020B - 02618, JUNE 1986- REVISED AUGUST 1989
absplute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) ............................................................. 7V
Input voltage ,............................................................... : .........'.... 5.5 V
Low-level driver output current : .................................... !...................... 100 rnA
Continuous total dissipation ........................................... See Dissipation Rating Table
Operating free-air temperature range .................................................. O°C to 70°C
Storage temperature range ........................................ :.............. - 65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from the case for 10 seconds ..... '. . . . . . . . . . . . . . . . . . . . . .. 260°C
NOTES: 1. All voltage values are wRh respect to network ground terminal.
DISSIPATION RATING TABLE
PACKAGE
TA,,25"C
POWER RATING
OW
1350mW
10.8mwrC
864mW
N
1700mW
13.6mwrc
1088mW
DERATING FACTOR
TA=7O"C
POWER RATING
recommended operating conditions
Supply voltage, VCC
High-level input voltage, VIH
MIN
NOM
MAX
UNIT
4.75
5
5.25
V
0.8
V
Low level input voltage, VIL
High-level output current, IOH
loW-level output current, IOL
Bus ports with 3-state outputs
Terminal ports
-5.2
mA
-800
fAA
Bus ports
48
Terminal ports
16
Operating free-air temperature, TA
2-452
V
2
0
1ExAs'"
INSIRUMENTS
POST OFFICE BOX 655303 • DALlAS. TEXAS 75265
70
mA
·C
SN75ALS162
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVER
SLLS020B - 02618, JUNE 1986 - REVISED AUGUST 1989
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
MIN TYPt
MAX
UNIT
TEST CONDITIONS
PARAMETER
V,K
Input clamp voltage
Vhys
Hysteresis (\IT+ -
Vr"')
VOH*
High-level output voltage
VOL
low-level output voltage
"
Input current at
maximum Input voltage
'IH
High-level input current
"L
Low-level input current
V'/O(bus)
Voltage at bus port
-O.S
" =-lSmA
Bus
10H = -SOO IIA
2.7
3.S
Bus
'OH=-S.2mA
2.S
3.3
V
V
10L= 16 mA
0.3
O.S
'OL= 48 mA
0.35
O.S
Terminal
V,=S,SV
0.2
100
IIA
Terminal and
control inputs
V,=2.7V
0.1
20
V, =O.SV
-10
-100
IIA
IIA
Driver disabled
Power on
Power off
Short-circuH output
current
V
Bus
I'(bus) =0
2.S
3.0
Driver disabled
VCC=O,
3.7
-l.S
"(bus) =-12 mA
Current into bus port
-l.S
Terminal
V'(bus) = 0.4 V to 2.S V
lOS
0.65
Terminal
V, (bus) =-l.S Vto 0.4 V
'I/O(bus)
0.4
V
V
-1.3
-3.2
0
+2.5
-3.2
V, (bus) = 2.5 Vto 3.7 V
V, (bus) = 3.7 Vto 5 V
0
V, (bus) = 5 Vto 5.5 V
0.7
mA
2.5
2.5
-40
V, (bus) = 0 to 2.5 V
Terminal
-15
-35
-75
Bus
-25
-50
-125
75
ICC
Supply current
No load,
TE, DC, and SC low
55
CI/O(bus)
Bus-port capacitance
VCC=O to 5 \I,
VI/O = 0 to 2 V, f = 1 MHz
30
IIA
mA
mA
pF
t All typical values are at VCC = 5 V, TA = 25·C.
* VOH applies to 3-state outputs only.
lExAs . "
INSIRUMENTS
POST OFFICE BOX 655303 • DAUAS, TEXAS 75265
2-453
SN75ALS162
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVER
Su..s02OB - 02618, JUNE 1986- REVISED AUGUST 1989
switching characteristics over recommended range of operating free-air temperature, VCC = 5 V
PARAMETER
tpLH
Propagation delay time,
low-to-high-Iavel output
tpHL
Propagation delay time,
high-to-Iow-Ievel output
tPLH
Propagation delay time,
low-to-high-Iavel output
tpHL
Propagation delay time,
high-to-Iow-Iavel output
(OUTPUT)
Terminal
Bus
tpZH
Output enable time to high lavel
Output disable time from high level
tpZL
Output enable time to low level
tpLZ
Output di~ble time from low lavel
tPZH
Output enable time to high lavel
TE, DC, orSC
TEST
CONDITIONS
MIN
TYpt
MAX
10
20
12
20
5
10
7
14
CL=30pF,
Sae Figure 1
Bus
(ATN, EOI,
REN,IFC,
andDAV)
UNIT
ns
CL=30pF,
See Figure 2
Terminal
Bus
tpHZ
TO
FROM
(INPUT)
ns
30
20
CL=15pF,
See Figure 3
ns
45
20
30
tPHZ·
Output disable time from high lavel
tpZL
Output enable time to low lavel
tpLZ
Output disable time from low lavel
TE, DC, orSC
25
CL=15pF,
See Figure 4
Terminal
ns
30
25
t All typical values are at TA = 25·C.
PARAMETER MEASUREMENT INFORMATION
SV
4.3 V
2400
From (bus)
Output Under
---.------~--.-- TeRP~m
Teet
T
CL =30 pF
(see Note A)
From (terminal)
--_.--------4~_.>-- Test Polm
Output Under
Teet
T
4800
LOAD CIRCUIT
TermlnaJ,
Input
1.SV
I
I
(sse Note B)
tPLH-I++!1
Bue
Output
\ - - - - 3V
1.SV
luv
----'
ipHL
L--VOH
1.0~V
1.SV
I
tpLH
b~~~al
3kO
LOAD CIRCUIT
J
OV
--*+I
I
Bus
Input
CL=30pF
(see Note A)
(see Note B)
--f8t
OL
VOLTAGE WAVEFORMS
\
---3V
1.SV
I
OV
t
tpHL~
!1.SV
1.~V
VOH
VOL
VOLTAGE WAVEFORMS
Figure 1. Termlnal-to-Bus Load Circuit
and Voltage Waveforms
Figure 2. Bus-to-Terminal Load Circuit
and Voltage Waveforms
NOTES: A. CL includes probe and Jig capacftance.
B. The input pulse is supplied by a generator having the following characteristics: PRR s 1 MHz, 50% duty cycle, tr s 6 ns, tf S 6 ns,
ZO=500,
1ExAs ~
INSTRIJMENfS
2-454
POST OFFICE BOX 855303 • DALLAS. TEXAS 75265
SN75ALS162
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVER
SLl.S02OB - 02618. JUNE 1986 - REVISED AUGUST 1989
PARAMETER MEASUREMENT INFORMATION
S1
S1
o-SV
2000
From (bus)
Output Under
Teat
From (terminal)
Output Under
Teat
---.---*--+-- Teat Point
T
CL=1SpF
(see Note A)
2400
- - . - -.....- - . - - Teat Point
T
4800
LOAD CIRCUIT
J!
1
Output
S10pen
1
tpZI;
Bus
Output
S1 Closed
2V
,
1
CL=1SpF
(see Note A)
3kO
LOAD CIRCUIT
- - " \ - - - - - - - , - - - - - 3V
Control
~
Input
~ 1.5 V (see Note B)
~ 1.S V
- - J I - - - - - - - J I .... - - - - o V
fpZH-+I
i+tpHZ -+t I+-
.. it
o-4.3V
'~VOH
1
1
r.--
~
OV
tpLZ -----...---..,
'\1 V
I
O.S~ -
3 SV
.
VOL
- - " \ - - - - - - - , _ - - - - 3V
Control
~
Input
~ 1.5 V (see Note B)
~ 1.S V
- - J I - - - - - - - J I .... - - - - o V
tPZH-+I
i+tpHZ -+I I+.
Terminal
~eo%-- VOH
Output
1
I
S10pen
I
1.SV
I
J!
111
tpZL ~
~F81~:
VOLTAGE WAVEFORMS
i+\1V
1
tpLZ
---+I 1..-
ov
lC::~
VOLTAGE WAVEFORMS
Figure 3. Bus Load Circuit and
Voltage Waveforms
Figure 4. Terminal Load Circuit and
Voltage Waveforms
NOTES: A CL Includes probe and jig capacitance.
B. The input pulse is supplied by a generator having the following characteristics: PRR s 1 MHz. 50% duty cycle. tr s 6 ns. tf S 6 ns,
ZO=500.
1ExAs . "
INSIRUMENTS
POST OFACE BOX 655303 • DAllAS. TEXAS 75265
2-455
SN75ALS162
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVER
SLLS020B - 02618, JUNE 1986- REVISED AUGUST1989
TYPICAL CHARACTERISTICS
TERMINAL LOW-LEVEL OUTPUT VOLTAGE
TERMINAL HIGH-LEVEL OUTPUT VOLTAGE
VS
vs
HIGH-LEVEL OUTPUT CURRENT
LOW-LEVEL OUTPUT CURRENT
4
>I
3.5
...
Q
g
2.5
J
2
1:
1.&
S
"""'" i\.
3
II
:a::
~
!i
I
0.&
iii'
~
:a::
~
0.4
0
0.3
!i
Co
!i
'\
~
~
~~
",
.3
V
/
0.2
oJ
/'
0.1
'\
o
o
-5 -10 -15 -20 -25 -30 -35 -40
IOH - High-Level Output Current - mA
o
10
20
30
40
50
IOL - Low-Level Output Current - mA
Figure 5
Figure 6
TERMINAL OUTPUT VOLTAGE
vs
BUS INPUT VOLTAGE
4
I
1
VCC=&V
3.&
No load
TA=25°C
>I
GO
Q
II
3
:a::
2.5
!i
Co
!5
2
~
0
I
1
Vr-
VT+
1.&
~
0.6
o
o
0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8
VI -Input Voltage - V
Figure 7
1ExAs
2-45.6
L
V
/
~
V
I
.p
i\.
0.5
o
>I
vccL&v
TA=25°C
GO
J:
I
J:
.p
0.6
I
VCC=&V
TA=25°C -
~
INSIRUMENTS
POST OFFICE BOX 655303 • DAllAS. TEXAS 75265
2
60
SN75ALS162
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVER
SlLS020B - 0261 B. JUNE 1986 - REVISED AUGUST 1989
TYPICAL CHARACTERISTICS
BUS HIGH-LEVEL OUTPUT VOLTAGE
VB
BUS HIGH-LEVEL OUTPUT CURRENT
BUS LOW-LEVEL OUTPUT VOLTAGE
vs
BUS LOW-LEVEL OUTPUT CURRENT
0.6
4
VCC=5V
TA=25 D C
>
I
'-....
I
V
./
0.5
II
""
f
,
-10
'\
-20
0.4
'S
!0
~
""
-30
-40
V
0.3
I
0.2
:?
0.1
!..
'\
o
o
I
VCC=5V
TA=25D C
/
V
V"
/
o~~~--~~--~~~~~~~
-50
o
-60
10
20
30
40
60
60
70
80
90 100
IOL - Low-Level Output Current - mA
IOH - High-level Output Current - mA
Figure 8
V
/
Figure 9
BUS OUTPUT VOLTAGE
BUS CURRENT
vs
vs
TERMINAL INPUT VOLTAGE
BUS VOLTAGE
VCC=5V
No Load
TA=25D C
2
3r--+---r--~--~-1---+--1---1
I
o
i
-1
o
-2
~
!l
m
1-3
I-4
~
-5
o~~--~--~--~~~~--~~
0.9
1.1
1.2
1.3
1.4
1.5
1.6
1.7
VI -Input Voltage - V
VI/O/busl- Bus Voltage - V
Figure 10
Figure 11
1ExAs
,If
INSIRUMENTS
POST OFFICE BOX 655303 • DAUAS. TEXAS 75265
2-457
2-458
SN75163B
OCTAL GENERAL·PURPOSE INTERFACE BUS TRANSCEIVER
SLLSOO6A- 02611 OCTOBER 1985 - REVISED FEBRUARY 1993
DW OR N PACKAGE
(TOP VIEW)
• 8-Channel Bidirectional Transceivers
• Power·Up/Power.Down Protection
(Glitch Free)
• Hlgh·Speed Low·Power Schottky Circuitry
• Low Power Dissipation. • • 66 mW Max Per
Channel
TE
B1
B2
B3
B4
B5
GPIB
I/O Ports
• Hlgh·lmpedance PNP Inputs
• Receiver Hysteresis. • • 650 mV Typ
B6
• Open-Collector Driver Output Option
B7
B8
GNO
• No Loading of Bus When Device Is
Powered Down (Vee = 0)
vee
01
02
03
04
05
06
07
08
PE
3
6
7
8
9
10
Terminal
I/O Ports
description
The SN75163B octal general-purpose interface
NOT RECOMMENDED FOR NEW DESIGN
bus transceiver is a monolithic, high-speed, lowpower Schottky device. It is designed for two-way
data communications over single-ended transmission lines. The transceiver features driver outputs that can be
operated in either the open-collector or 3-state modes. If talk enable (TE) is high, these outputs have the
characteristics of open-collector outputs when pullup enable (PE) is low and of 3-state outputs when PE is high.
Taking TE low places the outputs in the high-impedance state. The driver outputs are designed to handle loads
of up to 48 mA of sink current. Each receiver features pnp transistor inputs for high input impedance and 400 mV
of hysteresis for increased noise immunity.
Output glitches during power up and power down are eliminated by an internal circuit that disables both the bus
and receiver outputs. The outputs do not load the bus when Vee =O.
The SN751638 is characterized for operation from O'C to 70'C.
Function Tables
EACH DRIVER
INPUTS
EACH RECEIVER
INPUTS
OUTPUT
D
TE
PE
B
H
H
H
H
H
H
L
L
B
L
H
H
X
X
H
L
L
Z
L
X
L
X
Z
H =high level,
TE
PE
OUTPUT
D
L
L
H
X
X
X
L
H
Z
L
L =low level,
X =irrelevant,
Z =high-impedance state
1ExAs
..If
Copyright © 1993, Texas Instruments Incorporated
INSIRUMENTS
POST OFFICE BOX 6515303 • DALLAS, TEXAS 75265
2-459
SN75163B
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVER
SLLSOO6A- 02611, OCTOBER 1985 - REVISED FEBRUARY 1993
logic symbol t
logic diagram (positive logic)
PE
PE
TE
01
02
03
04
05
06
07
08
11 ...
h
1
...
h
M1 (3S)
M2(OC)
EN3(XMT)
.,
EN4(RCV)
19
18
r
L
'i74
1
.IT
B1
3
B2
4
B3
02 18
I>
3(WI2~)
2
W
2 B1
3
17 ....
4
16
5
15
6
14
7
13
8
12 ....
9
03 17
B2
B3
B4
04 16
B5
B6
B7
Terminlll
I/O Ports
5 B4
GPIB
I/O
Ports
05 15
B8
t This symbol is in accordance wHh ANSI/IEEE Std 91-1984 and
lEe Publication 617-12.
'i7 Designates 3-state outputs
~ Designates open-collector outputs
6
B5
7
B6
8
B7
9
B8
06 ...!1::!.4_ _~_ _-I
07 ...!1",,3_ _~_ _-I
08...!1~2_ _~_ _-I~~
__~
schematics of inputs and outputs
EQUIVALENT OF ALL CONTROL INPUTS
EQUIVALENT OF ALL INPUT/OUTPUT PORTS
Vee
vee---~-----
9ka
NOM
Input
GNO~---~---~-
___ __
~
~_*-~_~~_~______
Input/Output Port
Driver output Req = 30 a NOM
Receiver output Re = 110 a NOM
2-460
POST OFFICE BOX 655300 • DALlAS, TEXAS 75265
GNO
SN75163B
OCTAL GENERAL·PURPOSE INTERFACE BUS TRANSCEIVER
SUSOO6A- 02611, OCTOBER 1985 - REVISED FEBRUARY 1993
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) ............................................................. 7 V
Input voltage ........................................................... , .•............... 5.5 V
Low-level driver output current .......................................... , .......•......... 100 mA
Continuous total power dissipation (see Note 2) .......................... See Dissipation Rating Table
Operating free-air temperature range ............................................ ,..... O°C to 70°C
Storage temperature range ....................................................... - 65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from the case for 10 seconds ............................ 260°C
NOTES: 1. All voltage values are with respect to network ground terminal.
DISSIPATION RATING TABLE
PACKAGE
TA" 25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
TA " 70°C
POWER RATING
OW
1125mW
9.0mwrc
720mW
N
1150mW
9.2mwrc
736mW
recommended operating conditions
Supply voltage, VCC
High-level input voltage, VIH
MIN
NOM
MAX
UNIT
4.75
5
5.25
V
2
Low-level input voltage, VIL
High-level output current, IOH
High-level output current, IOL
Bus ports with pullups active
Terminal ports
V
0.8
V
-10
mA
-800
!AA
Bus ports
48
Terminal ports
16
Operating free-air temperature, TA
0
POST OFFICE BOX 655303 • DALlAS, TEXAS 75265
70
mA
°c
2-461
SN75163B
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVER
SLlSOO6A- 02611, OCTOBER 1985- REVISED FEBRUARY 1993
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
I
PARAMETER
VIK
Input clamp voltage
Vhys
Hysteresis (Vr + - VT ~
VOH
High-level output voltage
VOL
Low-level output voRage
10H
MIN
TEST CONDITIONS
II =-18mA
TYpt
MAX
-0.8
-1.5
0.4
0.65
TEatO.8V
2.7
3.5
PEandTEat2V
2.5
3.3
UNIT
V
V
Bus
See Figure 8
Terminal
10H = -800 !lA.
Bus
IOH=-10mA.
Terminal
IOL=16mA,
TEatO.8V
0.3
0.5
Bus
10L=48mA,
PEandTEat2V
0.4
0.5
High-level output current
(open-collector mode)
Bus
Vo = 5.5 V,
DandTEat2V
PEatO.8V,
10Z
OIf-state output current
(3-state mode)
Bus
PEat2V,
TEat 0.8 V
II
Input current at maximum
Input voltage
Terminal
VI=5.5V
0.2
100
IlA
IIH
High-level Input current
Terminal
VI=2.7V
0.1
20
IlL
Low-level input current
Terminal
VI = 0.5 V
-10
-100
IlA
IlA
lOS
Short-circuit output current
IlL
Supply current
No load
CVO(bus)
Bus-port capacitance
VCC=5VtoO,
V
100
I Vo=2.7V
I Vo=0.4V
20
-20
Terminal
-15
-35
-75
Bus
-25
-so
-125
I Receivers jow and enabled
80
I Drivers low and enabled
VVO=Ot02V,
100
f= 1 MHz
V
IlA
IlA
rnA
rnA
pF
30
t All typical values are at VCC = 5, TA = 25·C.
switching characteristics,
Vee =5 V, CL =15 pF, TA =25°C (unless otherwise noted)
PARAMETER
tpLH
Propagation delay time, low-to-hlgh-Ievel output
tpHL
Propagation delay time, high-to-Iow-Ievel output
tpLH
Propagation delay time, low-to-hlgh-Ievel output
tpHL
Propagation delay time, hlgh-to-Iow-Ievel output
TO
FROM
(INPUT)
(OUTPUT)
TEST
CONDITIONS
Terminal
Bus
CL=30 pF,
See Figure 1
Bus
Terminal
CL=30 pF,
See Figure 2
MIN
TYP
MAX
14
20
14
20
10
20
15
22
tpZH
Output enable time to high level
25
35
tpHZ
Output disable time from high level
13
22
tpZL
Output enable time to low level
22
35
tpLZ
Output disable time from low level
22
32
tpZH
Output enable time to high lever
20
30
tpHZ
Output disable time from high level
12
20
tpZL
Output enable time to low level
23
32
tpLZ
Output disable time from low level
19
30
ten
Output pullup enable time
15
22
tdls
Output pullup disable time
13
20
TE
TE
PE
Bus
Terminal
Terminal
See Figure 3
See Figure 4
See Figure 5
1ExAs ."
INSIRUMENTS
2-462
POST OFFICE BOX 655303 • DAUAS, TEXAS 75265
UNIT
ns
ns
ns
ns
ns
SN75163B
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVER
SLLSOO6A- 02611, OCTOBER 1985 - REVISED FEBRUARY 1993
PARAMETER MEASUREMENT INFORMATION
3V
TEST CIRCUIT
VOLTAGE WAVEFORMS
Figure 1. Terminal-to-Bus Test Circuit and Voltage Waveforms
TEST CIRCUIT
VOLTAGE WAVEFORMS
Figure 2. Bus-to-Termlnal Test Circuit and Voltage Waveforms
sv
3V
2000
X
Output
S2
81
!
1 1•SV
TElnput
~
-..I Ie--
BOutput
S1 to3V
S20pen
I
\1.-:V---
1
t
;;:;:=tl~-.I-I
tPZL:
4
B Output
~~~D
S2Closed
--I
~
1 1- - - - VOH
1 \90%
I:J
I
ov
1•
tpZH tPHZ
3V
\1 r.1
2V
1
'L-
tpLZ -----l.--.I
"
1.0 V
O.BV
3.SV
1
~V
- - - VOL
TEST CIRCUIT
VOLTAGE WAVEFORMS
Figure 3. TE-to-Bus Test Circuit and Voltage Waveforms
NOTES: A The input pulse is supplied by a generator having the following characteristics: PRR
ZO=500.
B. CL includes probe and jig capac~ance.
5
1 MHz, 50% duty cycle, tr
5
6 ns, tf 5 6 ns,
TEXAS ~
INSIRUMENTS
POST OFFICE BOX 655303 • DALlAS, TEXAS 75265
2-463
SN75163B
OCTAL GENERAL·PURPOSE INTERFACE BUS TRANSCEIVER
Su.9006A- 02611. OCTOBER 1985- REVISED FEBRUARY 1993
PARAMETER MEASUREMENT INFORMATION
4.3 V
~
6
52
~
TElnput
tPZH -tI
i
1.5V
IF
D:1!: !luv
r
tpZL---.I
3V
1.SV ---OV
I".::
tpHZ - '
! ~:~
'y:-4V
~
tpLZ -I
DOutput
'\
S1 to GND
1.0 V
S2Closed.
.1
.•
o.7L
VOL
VOLTAGE WAVEFORMS
TEST CIRCUIT
Figure 4. TE·to·Termlnal Test Circuit and Voltage Waveforms
Generator
(see Note A)
uv
PElnputJ
D
>-~~------~Output
~
\~s~--3V
I.
OV
tdis ~ . ~--....;;.;.;.-.-~,--- VOH
len -..I ~
SOO
1
90%
2V
VOL. 0.8 V
3 V----4Hi-....J
VOLTAGE WAVEFORMS
TEST CIRCUIT
Figure 5. PE·to·Bus Pull up Test Circuit and Voltage Waveforms
NOTES: C. The input· pulse is supplied by a generator having the following characteristics: PRR s 1 MHz. 50% duty cycle. tr s 6 ns, tf S 6 ns.
ZO=500.
D. CL includes probe and jig capacHance.
1ExAs
..If
INSIRUMENTS
2-464
POST OFFICE BOX 655303 • DALlAS. TEXAS 75265
SN75163B
OCTAL GENERAL·PURPOSE INTERFACE BUS TRANSCEIVER
Su.8006A-D2611. OCTOBER 1985-REVISED FEBRUARY 1993
TYPICAL CHARACTERISTICS
TERMINAL HIGH-LEVEL OUTPUT VOLTAGE
va
HIGH-LEVEL OUTPUT CURRENT
LOW-LEVEL OUTPUT CURRENT
4
>1
_I.
3.5
........
III
iii'
=
~
!i
3
2.5
~
2
1.5
CI
:i:
1
J::
.p
i'\.
'\
o
>1
1-
VCC=5V
TA=25"C
0.5
./
III
iii'
j
0.4
1
6
~
~
"" ,
.p
-5 -10 -15 -20 -25 -30 -35
IOH - High-Level Output Current - rnA
/
0.3
0.2
1
..J
\.,
0.5
o
0.6
1
VCC=5V
TA = 25°C-
'\
~
0
TERMINAL LOW-LEVEL OUTPUT VOLTAGE
va
/
V
~
V
/
/
0.1
o
-40
o
10
20
30
40
50
IOL - Low-Level Output Current - rnA
Figure 6
60
Figure 7
TERMINAL OUTPUT VOLTAGE
va
BUS INPUT VOLTAGE
>
4
VC~=5IV
3.5
No Load
TA=25"C
3
1
III
I
~
!i
2.5
2
~
0
1
VT-
VT+
1.5
.p
0.5
o
o
0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8
VI-Input Voltage - V
2
Figure 8
TEXAS'"
INSTRUMENTS
POST OFFICE BOX 655303 • DAUAS. TEXAS 75265
2-465
SN75163B
.
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVER
SUSOO6A- 02611. OCTOBER 1985- REVISED FEBRUARY 1993
TYPICAL CHARACTERISTICS
BUS HIGH-LEVEL O.UTPUT VOLTAGE
va
HIGH-LEVEL OUTPUT CURRENT
LOW-LEVEL OUTPUT CURRENT
0
>
I
CD
J
3
!
O.B
VCC~5V
TA=25°C
--......
~
!i
t
0
BUS LOW-LEVEL OUTPUT VOLTAGE
va
::r
J
~
""""
"
2
.c
CD
5:
I
i
!
o
o
-10
-20
-40
-50
0.3
/'
V"
o
-60
o
10
20
30
--r--r-......,.-""T"'-T"""--'-"'"
4~......
VCC=5V
No Load
TA=25°C
>3t--+--t--+--t-f--t--+---I--I
I
~
2
o
I
1t--+--t--+---lIt--t--+---I--I
OL---L_....L.._..L....--L_....L.._..L....---I_.....J
1.1
1.2
1.3
1.4
1.5
1.6
VI-Input Voltage - V
Figure 11
1ExAs
~
INSIRUMENTS
2-466
50
60
Figure 10
va
0.9
40
70
SO
90 100
IOL - Low-Level Output Current - mA
THERMAL INPUT VOLTAGE
.p
/
/
BUS OUTPUT VOLTAGE
t
i
V
'/
0.1
IOH - High-Level Output Current - mA
Figure 9
V
V
I
'"
-30
./
0.4
....
.p
-'.
0.5
~ 0.2
"
:z::
.p
I
VCC=5V
TA=25°C
POST OFFICE BOX 665303 • DALlAS. TEXAS 75265
1.7
SN75ALS163
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVER
SLLS021D-
•
•
•
•
•
•
•
•
•
S-Channel Bidirectional Transceiver
High-Speed Advanced Low-Power Schottky
Circuitry
Low Power Dissipation ••• 46 mW Max per
Channel
Fast Propagation Times ••• 20 ns Max
High-Impedance PNP Inputs
Receiver Hysteresis ..• 650 mV Typ
Open-Collector Driver Output Option
No Loading of Bus When Device Is
Powered Down (Vee = 0)
Power-Up/Power-Down Protection
(Glitch Free)
JUNE 1986 - REVISED FEBRUARY 1993
OW OR N PACKAGE
(TOPVlEW)
TE
Vee
01
02
GPI8
I/O
Ports
84
85
86
87
88
GNO
03
04
05
06
07
08
PE
Terminal
I/O Ports
Function Tables
description
EACHORIVER
EACH RECEIVER
The SN75ALS163
octal
general-purpose
INPUTS
OUTPUT
INPUTS
OUTPUT
0 TE PE
B
B TE PE
0
interface bus transceiver is a monolithic, highH
L
X
H
H
H
L
L
speed, advanced low-power Schottky device. It is
L
X
L
H L
X
H
H
designed for two-way data communications over
H
X
L
Z
X H
X
Z
single-ended transmission lines. The transceiver
X
Z
X L
features driver outputs that can be operated in
H = high level.
L = low level.
x = irrelevant.
either the open-collector or 3-state mode. If talk
Z =high-impedance state
enable (TE) is high, these outputs have the
characteristics of open-collector outputs when pullup enable (PE) is low and of 3-state outputs when PE is high.
Taking TE low places the outputs in the high-impedance state. The driver outputs are designed to handle loads
of up to 48 mA of sink current. Each receiver features pnp transistor inputs for high input impedance and 400 mV
minimum of hysteresis for increased noise immunity.
Output glitches during power up and power down are eliminated by an internal circuit that disables both the bus
and receiver outputs. The outputs do not load the bus when Vee =O.
The SN75ALS163 is characterized for operation from
o·e to 70·e.
Copyright © 1993. Texas Instruments Incorporated
TEXAS . "
INSIRUMENIS
POST OFFICE BOX _
• DALlAS. TEXAS 75265
2--467
SN75ALS163
OCTAL GENERAL·PURPOSE INTERFACE BUS TRANSCEIVER
SlLS0210 - 02611. JUNE 1986 - REVISED FEBRUARY 1993
logic symbol t
PE
TE
01
02
03
04
05
06
07
08
11
1
L.
LA
logic diagram (positive logic)
M2[OC]
.,
EN4 [RCV]
01
3(1V/2~)
V4
1
19
r
2
I>
L
11
TE
EN3[XMT]
19
18
PE
M1 (3S]
lr
2
h---l
17
3
4
----
16
5
15
6
14
7
13
8
12
9
02
B1
B1
18
3 B2
B2
03
B3
17
4
B4
as
B6
B7
D4
Terminal
I/O
Ports
B8
B3
16
5 B4
05
GPIB
I/O
Ports
15
6 B5
t This symbol is in accordance with ANSI{IEEE SId 91-1984
and lEe Publication 617-12.
'il Designates 3-state outputs
~ Designates open-collector outputs
D6
14
7 B6 .
07
13
8
DB
B7
12
9 B8
schematics of inputs and outputs
EQUIVALENT OF ALL CONTROL INPUTS
VCC:--------.----------
EQUIVALENT OF ALL INPUT{OUTPUT PORTS
--~~--~~----------------~~----~~-
9kONOM
10kO
NOM
Req
Vec
Input --.--...
GNO--*-----~----~--
------.-~~--~---r--~----~~---------
InputfOutput Port
=
Driver output Req 30 0 NOM
Receiver output Req 110 0 NOM
=
1ExAs . "
INSlRUMENTS
2-468
POST OFFICE BOX 655303 • DALlAS. TEXAS 7S265
GNO
SN75ALS163
OCTAL GENERAL·PURPOSE INTERFACE BUS TRANSCEIVER
SLl.S021 D - D2611 , JUNE 1986 - REVISED FEBRUARY 1993
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) " " " " " , .................................................. 7 V
Input voltage, VI .......................................................................... 5.5 V
Low-level driver output current ............................................................ 100 mA
Continuous total dissipation ........................................... See Dissipation Rating Table
Operating free-air temperature range .................................................. O·C to 70·C
Storage temperature range ....................................................... - 65·C to 150·C
Lead temperature 1,6 mm (1/16 inch) from the case for 10 seconds ............................ 260·C
NOTE: 1. All voltage values are with respect to network ground terminal.
DISSIPATION RATING TABLE
PACKAGE
TAs25°C
POWER RATING
DERATING
FACTOR
TA=70°C
POWER RATING
OW
1125mW
9.0mW/"C
720mW
N
1150mW
9.2mW/"C
736mW
recommended operating conditions
Supply voltage, VCC
High-level Input voltage, VIH
MIN
NOM
MAX
4.75
5
5.25
High-level output current, IOH
Low-level output current, IOL
V
V
2
Low-level input voltage, VIL
UNIT
0.8
V
Bus ports with pullups active
-5.2
mA
Terminal ports
-800
I1A
Bus ports
48
Terminal ports
16
Operating free-air temperature, TA
0
1ExAs
70
mA
°c
.Jf
INSIRUMENIS
POST OFFICE BOX 655303 • DAUAS, TEXAS 75265
2-469
SN75ALS163
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVER
SLLS021 0 - 02611, JUNE 1986 - REVISED FEBRUARY 1 993
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
TEST CONDITIONS
PARAMETER
VIK
Input clamp voltage
Vhvs
Hysteresis (\IT+ -
Vr-l
MIN
11=-18mA
Bus
TYpt
MAX
UNIT
-0.8
-1.5
V
0.4
0.65
V
Terminal
10H = - BOO tJA,
TEatO.BV
2.7
3.5
Bus
10H = - 5.2 mA,
PEandTEat2V
2.5
3.3
Terminal
10L= 16mA,
TEat 0.8 V
Bus
10L= 48 mA,
TEat2V
VO=5.5V,
PE at 0.8 V,
DandTEat2V
PEat2V,
VO=2.7V
20
TEatO.8V
VO=0.5V
-100
VOH
High-level output voltage
VOL
Low-level output voltage
10H
High-level output current
(open-collector mode)
Bus
10Z
Off-state output current
(3-state mode)
Bus
II
Input current at
maximum Input voltage
Terminal
VI =5.5V
0.2
100
tJA
IIH
High-level Input current
VI =2.7V
0.1
20
IlL
Low-level input current
Terminal,
PE,orTE
VI =0.5V
-10
-100
tJA
tJA
lOS
Short-circuH output
current
ICC
Supply current
CI/O(bus)
V
0.3
0.5
0.35
0.5
100
Terminal
-15
-35
-75
Bus
-25
-50
-125
Terminal outputs low
and enabled
42
65
Bus outputs low and enabled
52
80
Bus-port capacitance
No load
VCC = Oto 5V,
VitO = Oto 2 V,
30
f = 1 MHz
V
tJA
tJA
mA
mA
pF
t All typical values are at VCC = 5 V, TA = 25°C.
switching characteristics over recommended range of operating free-air temperature (unless
otherwise noted), Vee = 5 V
PARAMETER
tpLH
Propagation delay time,
low-to-high-Ievel output
tPHL
Propagation delay time,
high-to-Iow-Ievel output
tpLH
Propagation delay time,
low-to-high-Ievel output
tpHL
Propagation delay time,
high-to-Iow-Ievel output
tPZH
Output enable time to high level
tpHZ
Output disable time from high level
tpZL
Output enable time to low level
tpLZ
Output disable time from low level
tpZH
Output enable time to high level
tPHZ
Output disable time from high level
tpZL
Output enable time to low level
tpLZ
Output disable time from low level
ten
Output pull-up enable time
tdis
Output pull-up disable time
FROM
(INPUT)
TO
(OUTPUT)
TEST CONDITIONS
Terminal
Bus
CL=30pF,
See Figure 1
Bus
TE
TE
PE
Terminal
Bus
CL=30pF,
See Figure 2
CL=15pF,
See Figure 3
Terminal
CL=15pF,
See Figure 4
Bus
CL= 15 pF,
See Figure 5
:I: TYPical values are at TA = 25°C.
1ExAs ..,
INSIRUMENIS
2-470
POST OFFICE BOX 655303 • DALlAS, TEXAS 75265
MIN
TYP*
MAX
7
20
8
20
7
14
9
14
19
30
UNIT
ns
ns
5
12
16
35
9
20
13
30
12
20
12
20
11
20
11
22
6
12
ns
ns
ns
SN75ALS163
OCTAL GENERAL·PURPOSE INTERFACE BUS TRANSCEIVER
SLLS021 0 - 02611, JUNE 1986 - REVISED FEBRUARY 1993
PARAMETER MEASUREMENT INFORMATION
5V
3V
D~.5V
----'~---1
Output
::
\.~v---
tPLH4 ~_ _ _ _
tp_H_L-l++i-..,.
T
~v
VOH
CL=30PF
(see Note B)
4800
B Output
/UV
OH
3V
TEST CIRCUIT
VOLTAGE WAVEFORMS
Figure 1. Terminal-to-Bus Test Circuit and Voltage Waveforms
4,3 V
B~.5V
tPLH
~.~---
--4.i
tpHL
~
I ,..-------,~rI,----
DOutput
::
f·5V
L
VOL
VOL
TEST CIRCUIT
VOLTAGE WAVEFORMS
Figure 2. Bus-to-Terminal Test Circuit and Voltage Waveforms
3V
S2
Sl
~.5V
tpZH -+I
BOutputl
I+I r-----~~~~
VOH
s1to3vl
S20pen
I
O.SV
tPZL
3.5 V
BOutput
Sl toGND
1V
S2Closed
VOH
TEST CIRCUIT
VOLTAGE WAVEFORMS
Figure 3. TE-to-Bus Test Circuit and Voltage Waveforms
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR " 1 MHz, 50% duty cycle, tr " 6 ns, tf " 6 ns,
ZO=500.
B. CL includes probe and jig capac~ance.
TEXAS ~
INSIRlJMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2-471
SN75ALS163
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVER
SlLS021D -D2G11. JUNE 1986- REVISED FEBRUARY 1993
PARAMETER MEASUREMENT INFORMATION
4.3 V
6 S2
~~1'_5_V
tPZH-+I
2400
I
CL=15pF
3ka
I
T(seeNoteB)
'::'
I
,-----_.1
D Output I
S1t03VI
. S20pen I
tPZL
________
j+I _----..:..:.::........;-.l
DOutput
S1toGND
I
I
1.5 V
.!+-
S2 Closed
~4
~1 V
tPL2 ~
r.
!+I
OV
4V
\..__________..J.~!..."- _ V
OL
VOLTAGE WAVEFORMS
TEST CIRCUIT
FIgure 4. TE-to-Termlnal Test CIrcuit and Voltage Waveforms
VOH
VOL-O.BV
VOLTAGE WAVEFORMS
TEST CIRCUIT
FIgure 5. PE-to-Bus Test CIrcuit and Voltage Waveforms
NOTES: A. The Input pulse Is supplied by a generator having the following characteristics: PRR s 1 MHz. 50% duty cycle. Ir " 6 ns. If " 6 ns.
Zo=500.
B. CL includes probe and jig capacttance.
2-472
1ExAs'"
INSTRI.JMENTS
POST OFFICE BOX _
• DALlAS. TEXAS 75265
SN75ALS163
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVER
SlLS0210- 02611. JUNE 1986-REVlSEO FEBRUARY 1993
TYPICAL CHARACTERISTICS
TERMINAL HIGH-LEVEL OUTPUT VOLTAGE
va
HIGH-LEVEL OUTPUT CURRENT
LOW-LEVEL OUTPUT CURRENT
4
>
..
.I
3.&
2.&
~
2
0
""""
3
'!5
Go
'!5
1.&
aI
I
J:
.
"'\
0.&
:I!!
~
'!5
0.4
0
0.3
t
"-
1
j
",
0.2
I
oJ
I\.
0.&
o
>I
I
VCC=&V
TA=25°C
aI
'\
:E
.J>
0.6
J.
VCC=&V
TA=25°C -
I
f
TERMINAL LOW-LEVEL OUTPUT VOLTAGE
VB
.J>
./
/
V
V
/
",
/
/
0.1
'\
o
o
-& -10 -1& -20 -25 -30 -35 -40
IOH - High-t.evel Output Current - mA
o
10
30
20
40
50
IOL - Low·Level Output Current - mA
Figure 6
50
Figure 7
TERMINAL OUTPUT VOLTAGE
VB
BUS INPUT VOLTAGE
4
V~C=~V
No Load
TA=25°C
3.5
>I
.
aI
:I!!
~
'!5
Go
'!5
0
I
3
2.5
2
VT-
VT+
1.5
.J>
0.5
o
o
0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8
VI -Input Voltage - V
2
Figure 8
1ExAs
~
INSIRUMENTS
POST OFFICE BOX 655303 • DAUAS. TEXAS 75266
2-473
SN75ALS163
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVER
SLLS021D - 02611'. JUNE 1986 - REVISED FEBRUARY 1993
TYPICAL CHARACTERISTICS
BUS LOW-LEVEL OUTPUT VOLTAGE
BUS HIGH-LEVEL OUTPUT VOLTAGE
va
va
BUS HIGH-LEVEL OUTPUT CURRENT
BUS LOW-LEVEL OUTPUT CURRENT
0.6
4
VCC!5V
TA = 25"C
~
r~•
-20
V~
0.4
V
5
!0
'\
-10
~/
0.5
I
"\,
o
o
VCC=5V
TA=25"C
>
'\.
-30
""\
-40
-50
,/
0.3
I
0.2
~
0.1
",
V
./
/
!..
o
-60
o
10
20
30
40
50
60
Figure 9
Figure 10
BUS OUTPUT VOLTAGE
va
TERMINAL INPUT VOLTAGE
VCC=5V
No Load
TA=25"C
3~-+--~--~-++-~--+-~--~
oL-~--~--~~--~--~~--~
0.9
70
BO
IOL - Low-Level Output Current - mA
IOH - High-Level Output Current - mA
1.1
1.2
1.3
1.4
1.5
VI -Input Voltage - V
Figure 11
1ExAs
2-474
./
~
INSIRUMENIS
POST OFFICE &OX 655303 • DAUAS, TEXAS 75265
1.6
1.7
90 100
SN75164B
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVER
SLLS011A-
OCTOBER 1985 - REVISED FEBRUARY 1993
• S-Channel Bidirectional Transceiver
NPACKAGE
(TOP VIEW)
• Power-Up/Power-Down Protection
(Glitch Free)
• ATN+EOI (OR Function) Output to Simplify
Board Layout
• Designed to Implement Control Bus
Interface for Multiple Controllers
• Low-Power Dissipation •.• 72 mW Max Per
Channel
GPIB
1/0 Ports
• Fast Propagation Times ... 22 ns Max
• High-impedance PNP Inputs
• Receiver Hysteresis .•• 650 mV Typ
• Bus-Terminating Resistors Provided on
Driver Outputs
SC
TE
REN
IFC
NDAC
NRFD
DAV
EOI
ATN
SRO
GND
VCC
ATN+ EOI
REN
IFC
NDAC
NRFD
DAV
EOI
ATN
SRO
DC
Terminal
I/O Ports
NC - No intemal connection
• No Loading of Bus When Device Is
Powered Down (Vee = 0)
NOT RECOMMENDED FOR NEW DESIGN
description
CHANNEL IDENTIFICATION TABLE
The SN75164B eight-channel general-purpose
interface bus transceiver is a monolithic,
high-speed, low-power Schottky device designed
to meet the requirements of IEEE Standard
488-1978. Each transceiver is designed to provide
the bus-management and data-transfer signals
between operating units of a multiple-controller
instrumentation system. When combined with the
SN75160B octal bus transceiver, the SN75164B
provides the complete 16-wire interface for the
IEEE-488 bus.
NAME
IDENTITY
DC
TE
SC
Direction Control
Talk Enable
System Control
ATN
SRQ
REN
IFC
EOI
Attention
Service Request
Remote Enable
Interface Clear
End or Identify
ATN+EOI
DAV
NDAC
NRFD
CLASS
Control
Bus
Management
ATN Logical or EOI
Logic
Data Valid
Not Data Accepted
Not Ready for Data
Data
Transfer
The SN75164B features eight driver-receiver
pairs connected in a front-to-back configuration to
form input/output (I/O) ports at both the bus and terminal sides. All outputs are disabled (at a high-impedance
state) during VCC power-up and power-down transitions for glitch-free operation. The direction of data flow
through these driver-receiver pairs is determined by the DC, TE, and SC enable signals. The SN75164B is
identical to the SN75162B with the addition of an OR gate to help simplify board layouts in several popular
applications. The ATN and EOI signals are ORed to pin 21, which is a standard totem-pole output.
Copyright © 1993, Texas Instruments Incorporated
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655303 • OAllAS. TEXAS 75265
2-475
SN75164B
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVER
SLlS011A - D2908, OCTOBER 1985- REVISED FEBRUARY 1993
description (continued)
The driver outputs (GPIB I/O ports) feature active bus-terminating resistor circuits designed to provide a high
impedance to the bus when supply voltage Vee is D. The drivers are designed to handle loads up to 48 mA of
sink current. Each receiver features pnp transistor inputs for high input impedance and an ensured hysteresis
of 400 mV for increased noise immunity. All receivers have 3-state outputs to present a high impedance to the
terminal when disabled.
The SN75164B is characterized for operation from D·C to 7D·C.
logic symbol t
DC 12
TE 2
sc
logic diagram (positive logic)
ENI/G4
EN2/G5
EN3
ATN 14
9 ATN
21
EOI 15
8
ATN+EOI
EOI
SRO 13
10 SRO
REN 20
3 REN
IFC 19
4 IFC
DAV 16
7
sc
ATN ..:.;14::"""_ _-HH--4,.......-f ~~_ _-+......:.9 ATN
21 ATN+EOI
EOI 15
8 EOI
sRO 13
10 SRO
REN 20
3 REN
IFC 19
4 IFC
DAV 16
7 DAV
DAV
NDAC 18
5 NDAC
NRFD 17
6 NRFD
t This symbol is in accordance with ANSI/IEEE Std 91-1984
and lEe Publication 617-12
NDAC 18
5 NDAC
NRFD 17
6 NRFD
1ExAs ."
INSIRUMENTS
2-476
POST OFFICE sox 6553G3 • DAUAS. TEXAS 75265
SN75164B
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVER
SLLSOllA-D2908, OCTOBER 19B5-REVISED FEBRUARY 1993
RECEIVE/TRANSMIT FUNCTION TABLE
H " high level, L " low level, R "receive, T " transmit, X" Irrelevant
Direction of data transmission is from the terminal side to the bus side, and the direction of data receiving is from the bus side to the
terminal side. Data Iransfer is noninverting In bolh directions.
t ATN is a normallranscelver channellhal functions additionally as an internal direction conlrol or talk enable for EOI whenever the DC
and TE inputs are in the same slale. When DC and TE are in opposite stales, Ihe ATN channel functions as an independent transceiver
only.
ATN + EOI FUNCTION TABLE
ATN
INPUTS
EOI
OUTPUT
ATN+EOI
H
X
H
X
H
H
L
L
L
POST OFFICE BOX 655303 • DAUAS, TEXAS 75265
2-477
SN75164B
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVER
SLLS011A- 02908, OCTOBER 1985 - REVISED FEBRUARY 1993
schematics of inputs and outputs
EOUIVALENT OF ALL CONTROL INPUTS
lYPICAL OF SRO, NDAC, AND NRFD GPIB I/O PORT
VCC------~~------
Input
GND~~--~~--~--
Input/Output Port
Circuit inside dashed lines Is on GPIB I/O ports only.
lYPlCAL OF ALL I/O PORTS
EXCEPT SRO, NDAC, AND NRFD GPIB I/O PORTS
--~----~----~~--~~----.-----~~ VCC
ATN+EOIOUTPUT
--~----------'--VCC
Bka
2000
Output
1.3ka
----~--~--*-~~--~~~--*--------- GND
Input/Output Port
------~------~--
GND
Driver output Req = 30 a NOM
Receiver output Req = 110 a NOM
Circuit inside dashed lines Is on GPIB I/O ports only.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) ............................................................. 7 V
Input voltage, VI .......................................................................... 5.5 V
Low-level driver output current ............................................................ 100 mA
Continuous total dissipation at (or below) 25°C free-air temperature (see Note 2) .............. 1700 mW
Operating free-air temperature range .................................................. O°C to 70·C
Storage temperature range ....................................................... -65·C to 150·C
Lead temperature 1,6 mm (1116 inch) from case for 10 seconds: OW or N package ............... 260·C
NOTES: 1. All voltage values are wHh respect to network ground terminal.
2. For operation above 25°C free-air temperature, derate the N package at the rate of 13.6 mWrC.
2-478
POST OFFICE BOX 655303 • DAUAS. TEXAS 75265
SN75164B
OCTAL GENERAL·PURPOSE INTERFACE BUS TRANSCEIVER
SLLS011A- D2908, OCTOBER 1985- REVISED FEBRUARY 1993
recommended operating conditions
Supply voltage, VCC
High-level Input voltage, VIH
MIN
NOM
MAX
4.75
5
5.25
2
low-level output current, IOL
V
V
Low-level Input voltage, VIL
High-level output current, IOH
UNIT
0.8
Bus ports with 3-state outputs
-5.2
Terminal ports
-800
ATN+EOI
-400
Bus ports
48
Terminal ports
16
ATN+EOI
V
rnA
pA
rnA
4
0
Operating free-air temperature, TA
70
·C
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
PARAMETER
VIK
Input clamp voRage
Vhys
Hysteresis (VT+ -VT-)
VOH:I:
VOL
High-level output voltage
Low-level output voltage
II
Input current at maximum
Input voltage
IIH
High-level input current
IlL
VI/O(bus)
Low-level Input current
TEST CONDITIONS
MIN
Bus
See Figure 8
0.4
Terminal
IOH =-800 pA
2.7
Bus
IOH=-5.2mA
2.5
ATN+EOI
IOH =-400 pA
2.7
V
V
IOL= 16mA
0.5
0.5
ATN+EOI
IOL=4mA
0.4
Terminal§
VI =5.5V
100
ATN+EOI
VI =5.5V
200
Terminal,
control
VI=2.7V
20
ATN, EOI
VI=2.7V
40
Terminal,
control
VI =0.5V
-100
ATN, EOI
VI =0.5V
-500
Driver disabled
3.7
2.5
II(bus) =0
-1.5
'I (bus) = -12 rnA
Power on
Power off
Short-circuit output current
V
10L= 48 rnA
VI(bus) = 0.4 Vto 2.5 V
lOS
UNIT
-1.5
Bus
VoRage at bus port
Current into bus port
MAX
Terminal
VILbus) =-1.5 Vto 0.4 V
IVO(buS)
TYpt
11=-18mA
Driver disabled
VCC =0,
+2.5
-3.2
VI (bus) = 3.7 V to 5 V
0
2.5
VI (bus) = 5 Vto 5.5 V
0.7
2.5
-40
VI (bus) = 0 Vto 2.5 V
-15
-75
Bus
-25
-125
ATN+EOI
-10
-100
No load,
TE, DE, and SC low
VI/0=Ot02V,
POST OFFICE BOX 655303 • DAUAS, TEXAS 75265
f= 1 MHz
pA
pA
V
-3.2
0
VI (bus) = 2.5 V to 3.7 V
VCC = 5VtoOV,
pA
-1.3
Terminal
Supply current
ICC
CVQ{bus) Bus-port capacitance
t All typIcal values are at VCC = 5 V. TA = 25·C.
:I: VOH applies for 3-state outputs only.
§ Except ATN and EOI terminal pins
V
120
30
rnA
pA
rnA
rnA
pF
2-479
SN75164B
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVER
SLLS011A- D2908, OCTOBER 1985- REVISED FEBRUARY 1993
switching characteristics, Vee
=5 V, CL =15 pF, TA =25°C (unless otherwise noted)
PARAMETER
TO
FROM
(lNPUl)
(OUTPUl)
TEST
CONDITIONS
Terminal
Bus
CL=30 pF,
See Figure 1
Terminal
Bus
(SRQ,NDAC
NRFD)
CL=30 pF,
See Figure 1
Bus
Terminal
CL=30 pF,
See Figure 2
10
20
15
22
MIN
TYP
MAX
14
20
14
20
29
35
UNIT
tpLH
Propagation delay time, Iow-ta-high level output
tpHL
Propagation delay time, high-to-Iow level output
tpLH
Propagation delay time, low-to-hlgh level output
tpLH
Propagation delay time, low-to-hlgh level output
tpHL
Propagation delay time, high-to-Iow level output
tpLH
Propagation delay time, low-to-high level output
Terminal ATN
or
Terminal EOI
ATN+EOI
See Figure 3
14
ns
tpHL
Propagation delay time, hlgh-to-Iow level output
Terminal ATN
or
Terminal EOI
ATN+EOI
See Figure 3
14
ns
tpZH
Output enable time to high level
tpHZ
OutPut disable time from high level
tpZL
Output enable time to low level
TE, DC,
orSC
tpLZ
Output disable time from low level
Bus
(ATN, EOI,
REN,IFC,
and DAV)
tpZH
Output enable time to high level
tpHZ
Output disable time from high level
tpZL
Output-enable time to low level
tpLZ
Output disable time from low level
ns
ns
60
See Figure 4
45
60
ns
55
55
TE,DC,
orSC
Terminal
See Figure 5
50
45
55
1ExAs ."
INSIRUMENIS
2-480
ns
POST OFFICE BOX 655303 • DAUAS, TEXAS 75265
ns
SN75164B
OCTAL GENERAL·PURPOSE INTERFACE BUS TRANSCEIVER
SlLS011A- D2908. OCTOBER 1985 - REVISED FEBRUARY 1993
PARAMETER MEASUREMENT INFORMATION
SV
4.3 V
2000
From (bus)
Output Under Teat
2400
From (terminal) _ ......_ _ _....~~ Teat Point
Output Under Teat
.....- - -....~t-- Teat Point
I
CL=30pF
4800
(see Note A)
I
':"
LOAD CIRCUIT
tpLH
--J.-.:
Bus
Output
\-1~; -
3V
I
(sae Note B)
tpHL
~ __
I
2.2 V
OV
VOH
----
VOLTAGE WAVEFORMS
3V
IBU~
-'..SV
~.SV
np - - "
(see Note B)
I '-___ 0 V
tpLH --J....i
tPHL~
VOH
I
---
Terminal
Output
1.0V
I
T--
1.SV
VOL
VOLTAGE WAVEFORMS
Figure 1. Termlnal-to-Bus
Load Circuit and Voltage Waveforms
Figure 2. Bus-to-Termlnal
Load Circuit and Voltage Waveforms
l~~~1.5V
VCC
Teat Point
3kO
LOAD CIRCUIT
TermlnaJ, 1.S V
Input
I
CL=30pF
(see Note A)
2kO
I
~:v---::
I
tpHL~
tpLH4
I
------"'\:-t---
ATN+EOI
VOH
1.SV
From
ATN+EOI
CL
I
VOLTAGE WAVEFORMS
(see Note C)
(see Note A)
LOAD CIRCUIT
Figure 3. ATN+EOI Load Circuit and Voltage Waveforms
NOTES: A. CL includes probe and jig capacRance.
B. The input pulse is supplied by a generator having the following characteristics: PRR " 1 MHz. 50% duty cycla.
tr " 6
ns. If " ns.
ZO=500.
C. All diodes are 1N916 or 1N3064.
1ExAs~
1NSIRUMENIS
POST OFFICE BOX 655303 • DALlAS. TEXAS 75265
2-481
SN75164B
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVER
SLLS011A- D2908. OCTOBER 1985 - REVISED FEBRUARY 1993
PARAMETER MEASUREMENT INFORMATION
S1
S1
o--SV
From (bua)
Output Undat
Teat
From (terminal)
Output Under Test
TestPoiM
CL=1SpF
(aee Note A)
I
I
4800
--, r-------,kr---I
14-
tpHZ --+I
I,
2V
I
I
~
- - - VOH
90%
OV
tp~
BuaOutput
S1 Closed
3kC
-=
LOAD CIRCUIT,
3V
CoMroi
41.5 V
1.5 V
Inp_~_'I\_ _ ~~~!!ILJI\. _ _ _ _ OV
I
CL=1SpF
(see Note A)
-=
':"
--+I
4.3V
' TestPoiM
LOAD CIRCUIT
tpZH
0--
2400
201)0
il
'--_____Jlto~Y._
-3.SV
VOL
--, r-------, ,-----
3V
1(1.S V
Inp~ _ _'I\_ _ ~~~!!ILJ I \. _ _ _ _ OV
CoMrol
.;{1.5 V
tPZH -+I
Terminal
I
Output
I
S10pen
141.S V
I
j490% - -
I
Termln~~ZL---+t ~
Output
S1 Cloaed
tpHZ --+I
I
tPLZ-+I
VOH
OV
~14-
4V
,,\.0 V
I
. - O ' : ! Y . . - - VOL
VOLTAGE WAVEFORMS
VOLTAGE WAVEFORMS
Figure 4. Bus Enable and Disable Times
Load Circuit and Voltage Waveforms
Figure 5. Terminal Enable and Disable Times
Load Circuit and Voltage Waveforms
NOTES: A. CL includes probe and jig capacitance.
B. The input pulse is supplied by a generator having the following characteristics: PRR s 1 MHz. 50% duty cycle.t r s 6 ns. tf S 6 ns.
ZO=500.
2-482
1ExAs'"
INSIRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
SN75164B
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVER
Su.s011A- D2908, OCTOBER 1985 - REVISED FEBRUARY 1993
TYPICAL CHARACTERISTICS
TERMINAL LOW-LEVEL OUTPUT VOLTAGE
TERMINAL HIGH-LEVEL OUTPUT VOLTAGE
VB
va
HIGH-LEVEL PUTPUT CURRENT
LOW-LEVEL OUTPUT CURRENT
4
>I
III
CI
~
3.5
...........
3
~ 2.5
!5
Q,
!5
0
~
:r
SQ,
'\
1.5
I
J:
0.5
o
0.4
!5
J
~
~
""
0.2
I
....I
~ 0.1
'r\.
o
-5
-10
-15
./
0.3
0
-20
-25
-30
-35
o
-40
V
o
/
y'
III
~
~
/
TA = 25°C
I
'\
2
VC~=5V I
0.5 f-
>
\.
'\
CI
~
0.6
I
I
VCC=5V
TA=25°C -
/
/
V
10
20
30
40
50
60
IOL - Low-Level Output Current - mA
IOH - High-Level Output Current - mA
Figure 6
Figure 7
TERMINAL OUTPUT VOLTAGE
VB
BUS INPUT VOLTAGE
4
_I
1_
VCC=5V
No Load
3.5
TA=25°C
>
I
I
3
I
III
CI
III
==
~
2.5
S
2
0
1.5
~
I
VT-
VT+
~
0.5
o
o
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
2
VI- Input Voltage - V
Figure 8
1ExAs
..If
INSIRUMENTS
POST OFFICE BOX 655303 • DAUAS. TEXAS 75265
2-483
SN75164B
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVER
SLlS011A- D29OB, OCTOBER 1985- REVISED FEBRUARY 1993
TYPICAL CHARACTERISTICS
BUS LOW-LEVEL OUTPUT VOLTAGE
BUS HIGH·LEVEL OUTPUT VOLTAGE
va
vs
HIGH-LEVEL OUTPUT CURRENT
LOW·LEVEL OUTPUT CURRENT
o
>I
I•
~
3
~
2
g
::E:
I
::E:
1
.p
o
o
-10
-20
-40
~
0.4
!
0.3
I
/
U
-I
-50
-60
V"
V
,;/
/
,;/
V
0.1
o
o
10
20
30
40
50
60
70
80
90 100
101 - LOW-Level Output Current - mA
10H - High-Level Output Current - mA
Figure 10
Figure 9
BUS OUTPUT VOLTAGE
BUS CURRENT
va
vs
THERMAL INPUT VOLTAGE
BUS VOLTAGE
VCC=5V
NoLoed
TA = 25°C
>
./
/
I
.p
-30
VCC=5V
TA=25°C
~ 0.5
t
1\
1\
1\
~
!
0.6
I
VCC=5V
TA=26°C
2
31---1---4---1--+-+-1--+-+--1
I
t
~
!.p
21---I---4---I--t+-I--+-+--I
I
O ......---'-......0.9
1.0
1.1
........-"'----l'--.......--'----'
1.2
1.3
1.4
1.5
1.6
1.7
VI-Input Voltage - V
3
Figure 12
Figure 11
2-484
2
4
VVO(bus) - Bus Voltage - V
POST OFFICE BOX 65S3Q3 • DALlAS, TEXAS 75265
5
6
SN75ALS164
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVER
SUS0228
•
•
•
•
•
•
•
•
•
•
•
8-Channel Bidirectional Transceiver
Designed to Implement Control Bus
Interface
Designed for Multlcontrollers
High-Speed Advanced Low-Power Schottky
Circuitry
Low-Power Dissipation ••• 46 mW Max Per
Channel
Fast Propagation Times ••• 20 ns Max
High-Impedance PNP Inputs
Receiver Hysteresis ••• 650 mV Typ
Bus-Terminating Resistors Provided on
Driver Outputs
No Loading of Bus When Device Is
Powered Down (Vee = 0)
Power-Up/Power-Down Protection
(Glitch Free)
DWPACKAGE
(TOP VIEW)
VO
NDAC
NRFD
DAV
EOI
ATN
SRQ
NC
GND
GPIB
Ports
VCC
ATN+ EOI
REN
IFC
NDAC
NRFD
Terminal
DAV
VO Ports
EOI
ATN
SRQ
NC
DC
NPACKAGE
{TOP VIEW)
SC
TE
REN
IFC
description
The SN75ALS164 eight-channel generalpurpose interface bus transceiver is a monolithic,
high-speed, advanced low-power Schottky device
designed to meet the requirements of IEEE
Standard 488-1978. Each transceiver is designed
to provide the bus-management and data-transfer
signals between operating units of a multiplecontroller
instrumentation system.
When
combined with the SN75ALS160 octal bus
transceiver, the SN75ALS164 provides the
complete 16-wire interface for the IEEE 488 bus.
24
23
22
21
20
19
18
17
16
15
14
13
SC
TE
REN
IFC
VCC
ATN+EOI
REN
IFC
NDAC
NRFD
DAV
EOI
ATN
GPIB
VOPorts
NDAC
NRFD
DAV
EOI
ATN
SRQ
GND
Terminal
VO Ports
SRO
DC
NC - No internal connection
The SN75ALS164 features eight driver-receiver
pairs connected in a front-to-back configuration to
form input/output (I/O) ports at both the bus and
terminal sides. All outputs are disabled (at a
high-impedance state) during VCC power-up and
power-down transitions for glitch-free operation.
The direction of data flow through these
driver-receiver pairs is determined by the DC, TE,
and SC enable signals. The SN75ALS164 is
identical to the SN75ALS162 with the addition of
an OR gate to help simplify board layouts in
several popular applications. The ATN and EOI
signals are ORed to provide the ATN + EOI output,
which is a standard totem-pole output.
NOT RECOMMENDED FOR NEW DESIGN
CHANNEL IDENTIFICATION TABLE
NAME
DC
TE
SC
ATN
SRQ
REN
IFC
EOI
ATN+EOI
DAV
NDAC
NRFD
IDENTITY
Direction Control
Talk Enable
CLASS
Control
~mControl
Attention
Service Request
Remote Enable
Interface Clear
End or Identify
ATN LDgical or EOI
Data valid
No Data Accepted
Not Ready for Data
Bus
Management
lDgic
Data
Transfer
Copyright © 1989. Texas Instruments Incorporated
POST OFFICE SOX 855303 • DAUAS. TEXAS 75265
2--485
SN75ALS164
OCTAL GENERAL·PURPOSEINTERFACE BUS TRANSCEIVER
SLLS022B - D29OB, JUNE 1986 - REVISED AUGUST 1989
description (continued)
The driver outputs (GPIB I/O ports) feature active bus-terminating resistor circuits designed to provide a high
impedance to the bus when supply voltage Vee is O. The drivers are designed to handle loads up to 48 mA of
sink current. Each receiver features pnp transistor inputs for high input impedance and hysteresis of 400 mV
minimum for increased noise immunity. All receivers have 3-state outputs to present a high impedance to the
terminal when disabled.
The SN75ALS164 is characterized for operation from O°C to 70°C.
logic symbol t
DC
TE
12
2
SC
logic diagram (positive logic)
EN1/G4
EN2IG5
EN3
,,1
5
ATN
14
9
9
21
EOI
SRQ
REN
IFC
DAV
NDAC
NRFD
ATN+EOI
21
15
8
13
10
20
3
19
4
16
7
18
5
17
6
EOI 15
8
SRQ 13
10
REN 20
3
IFC 19
4
DAV 16
7
NDAC 18
5
NRFD 17
6
EOI
SRQ
REN
IFC
SRQ
REN
DAV
NDAC
NRFD
Pin numbers shown are for the N package.
2-486
ATN+EOI
EOI
t This symbol is in accordance with ANSI/IEEE Std 91-19B4 and
lEe Publication 617-12.
V DeSignates 3-state outputs
~ Designates passlve-pullup outputs
ATN
ATN
INSIRUMENIS
1ExAs "
POST OFFICE BOX 655303 • DAUAS. TEXAS 75285
IFC
DAV
NDAC
NRFD
SN75ALS164
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVER
SLLS022B - 02908, JUNE 1986 - REVISED AUGUST 1989
RECEIVE/TRANSMIT FUNCTION TABLE
SC
DAV
T
H =high level, L
=
=
=
R
R
=
low level, R receive, T transmit, X irrelevant
Direction of data transmission is from the terminal side to the bus side, and the direction of data receiving is from the bus side to the terminal side.
Data transfer is noninverting in both directions.
t ATN is a normal transceiver channel that functions additionally as an internal direction control or talk enable for EOI whenever the DC and TE
inputs are in the same state. When DC and TE are in oppostte states, the ATN channel functions as an independent transceiver only.
ATN + EOI FUNCTION TABLE
INPUTS
ATN
EOI
OUTPUT
ATN+ EOI
H
X
X
H
H
H
L
L
L
ThxAs . "
INSIRUMENTS
POST OFFICE BOX 655303 • OALLAS, TEXAS 75265
2-487
SN75ALS164
OCTALGENERAL·PURPOSE INTERFACE BUS TRANSCEIVER
SU.8022B - 02908, JUNE 1986- REVISED AUGUST 1989
schematics of Inputs and outputs
EQUIVALENT OF ALL
CONTROL INPUTS
TYPICAL OF SRQ, NDAC, AND NRFD
GPIB 110 PORT
vcc-------.--------
Input
GND~~--~----~--
Input/Output Port
Circuft inside dashed lines is on the driver outputs only.
TYPICAL OF ALL I/O PORTS
EXCEPT SRQ, NDAC, AND NRFD GPIB 1/0 PORTS
ATN
+ EOI OUTPUT
~~--------~-vcc
8kQ
200kQ
Output
Driver output Req = 30 D NOM
Receiver Ol.tput Req = 110 D NOM
Clrcuft inside dashed lines is on the driver outputs only.,
------~----~-
GND
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) ............................................................. 7 V
Input voltage ............................................................................ 5.5 V
Low-level driver output current ............................................................ 100 rnA
Continuous total dissipation ........................................... See Dissipation Rating Table
Operating free-airtemperature range .................................................. O°C to 70°C
Storage temperature range ....................................................... - 65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from the case for 10 seconds ............................ 260°C
NOTES: 1. All voltage values are with respect to network ground terminal.
DISSIPATION RATING TABLE
TA,,25°C
POWER RATING
DERATING
FACTOR
OW
1350mW
10.8mwrc
864mW
N
1700mW
13.6mwrc
1088mW
1ExAs
..If
INSIRUMENTS
2-488
=
PACKAGE
POST OFFICE BOX 655303 • DAUAS. TEXAS '75265
TA 70°C
POWER RATING
SN75ALS164
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVER
SlL.S0228 - 02908, JUNE 1986- REVISED AUGUST 1989
recommended operating conditions
Supply voltage, VCC
High-level Input voltage, VIH
MIN
NOM
MAX
UNIT
4.75
5
5.25
V
0.8
V
2
V
Low-level input voltage, VIL
High-level output current, 10H
Low-level output current, IOL
Bus ports with 3-state outputs
-5.2
Terminal ports
-800
ATN+ EOI
-400
Bus ports
48
Terminal ports
16
mA
tAA
mA
4
ATN+ EOI
Operating free-air temperature, TA
70
0
·C
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
PARAMETER
VIK
Input clamp voltage
Vhys
Hysteresis
...aI1
:ll!
~
!i
Q.
!i
0
~
.c
_I
3.5
'\
2.5
'\
2
I'\.
1.5
::a::
,
0.5
~
!i
Q.
!i
0.4
0
0.3
§
!
~
0.2
1
oJ
.p
\.
0.5
'\
o
...1
>
"""I\.
3
o
0.6
1
VCC=5V
TA=25°C -
f1
.p
TERMINAL LOW-LEVEL OUTPUT VOLTAGE
va
I
VCC=5V
TA=25OC
V
/
/
/
/'
V
/
V
0.1
I'\.
o
-5 -10 -15 -20 -25 -30 -35 -40
IOH - High-Level Output Current - mA
o
10
20
30
40
50
IOL - Low-Level Output Current - mA
Figure 6
60
Figure 7
TERMINAL OUTPUT VOLTAGE
va
BUS INPUT VOLTAGE
4
I
3.5
>1
3
j
2.5
!i
2
I
1.5
...aI
.&
:::I
0
!
VCC=5V
No Load
TA=25°C
VT-
VT+
.p
0.5
o
o
0.2 0.4 0.6 O.B 1 1.2 1.4 1.6 1.B
VI -Input Voltage - V
2
Figure 8
TEXAS . "
INSTRUMENrS
POST OFFICE BOX 655303 • DAUAS, TEXAS 75265
2-493
SN75ALS164
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVER
SLlS022B - 02908. JUNE 1986 - REVISED AUGUST 1989
TYPICAL CHARACTERISTICS
BUS HIGH·LEVEL OUTPUT VOLTAGE
BUS LOW·LEVEL OUTPUT VOLTAGE
vs
vs
BUS HIGH·LEVEL OUTPUT CURRENT
BUS LOW·LEVEL OUTPUT CURRENT
0.6
4
VCC=5V
TA = 25°C
"
o
o
>I
..
0.5
~
0.4
I
""
-10
5Q.
5
I\.
0
1i
"
I'..'\
-20
-40
I
0.2
.p
0.1
-60
/
,/'
'"
,/'
V
./
V
o
10
20
30
40
50
60
70
80
90 100
IOL - Low-Level Output Current - mA
IOH - High-level Output Current - mA
Figure 9
. . .V
0.3
o
-50
-'
V
.!J
""
-30
I
VCC=5V
TA=25°C
Figure 10
BUS OUTPUT VOLTAGE
BUS CURRENT
vs
vs
TERMINAL INPUT VOLTAGE
BUS VOLTAGE
3
VCC=5V
No Load
TA=25°C
2
1
I
0
i
-1
c3!
..
f
III
I
-2
-3
::I
-4
-5
-6
o~~--~--~~--~--~~~~
0.9
1.1
1.2
1.3
1.4
1.5
1.6
1.7
-1
VI-Input Voltage - V
0
3
4
VI/O(bus) - Bus Voltege - V
Figure 11
Figure 12
1ExAs ."
INSIRUMENTS
2-494
2
POST OFFICE BOX 655303 • DAUAS. TEXAS 75265
5
6
SN75ALS165
OCTAL GENERAL·PURPOSE INTERFACE BUS TRANSCEIVER
Su.8023B-
MEETS IEEE STANDARD 488·1978 (GPIB)
•
8-Channel Bidirectional Transceiver
•
High-Speed Advanced Low-Power Schottky
Circuitry
•
Low Power Dissipation .•• 46 mW Max Per
Channel
•
•
•
Fast Propagation Times •.. 20 ns Max
•
No Loading of Bus When Device Is
Powered Down (Vee = 0)
•
Power-Up/Power-Down Protection
(Glitch Free)
•
Driver and Receiver Can Be Disabled
Simultaneously
ow OR N PACKAGE
(TOP VIEW)
GPIB
I/O Ports
High-Impedance PNP Inputs
Vee
TE
B1
Receiver Hysteresis •.. 650 mV Typ
B4
B5
B6
B7
B8
GNO
D1
02
03
04
7
8
9
10
14
13
12
11
05
06
07
08
PE
Terminal
I/O Ports
NOT RECOMMENDED FOR NEW DESIGN
Function Tables
EACH RECEIVER
EACHORIVER
INPUTS
INPUTS
OUTPUT
OUTPUT
B TE PE
0
0 TE PE
B
L
H
H
H
H
L
L
H
H L
H
H
L
H
X
L
zt
L
X
H
X
Z
H X
zt
X
X
L
Z
L
X
H = high level,
L =low level,
X =Irrelevant,
Z =high-impedance state
t This is the high-impedance state of a normal3-state output
modified by the internal resistors to Vee and GND.
description
The SN75ALS165 eight-channel generalpurpose interface bus transceiver is a monolithic,
high-speed, advanced low-power Schottky device
x
designed for two-way data communications over
single-ended transmission lines. It is designed to
meet tlie requirements of IEEE Standard
488-1978. The transceiver features driver outputs
that can be operated ineither the passive-pullup
or 3-state mode. If talk enable (TE) is high, these
ports have the characteristics of passive-pullup outputs when pullup enable (PE) is low and of 3-state outputs
when PE is high. Taking TE low places these ports in the high-impedance state. Taking TE and PE low places
both the drivers and receivers in the high-impedance state. The driver outputs are designed to handle loads up
to 48 mA of sink current.
An active turn-off feature is incorporated into the bus-terminating resistors so that the device exhibits a high
impedance to the bus when Vee =O. When combined with the SN75ALS161 or SN75ALS162 management bus
transceiver, the pair provides the complete 16-wire interface for the IEEE 488 bus.
The SN75ALS165 is manufactured in a 20-pin package and is characterized for operation from O°C to 70°C.
TEXAS
~
Copyright lID 1989, Texas Instruments Incorporated
INSIRUMENTS
POST OFFICE BOX 655303 • DALlAS. TEXAS 75265
2-495
SN75ALS165
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVER
SLLS023B- 03011, JUNE 1986- REVISED AUGUST 1989
logic symbol t
PE
TE
01
D2
D3
D4
05
06
07
11
~
1
L
logic diagram. (positive logic)
TE
M2[OC)
EN3(XMl1
.,
5EN4[RCV]
L
3(1V/2~
V4
1
17
16
01
11"
2
--.-J
3
4
....
5
15
6
14
7
13
8
12
9
OS
19
r
I>
19
18
PE
M1 [3S]1G5
'----<0I1-+t-- 81
81
02
18
82
'----<0I1-+t-- 82
83
03
17
04
16
05
15
06
14
07
13
08
12
84
85
86
87
88
t This symbol is in accordance wHh ANSI/IEEE Std 91-1984
Terminal
I/O Ports
'----<0I1-+t-- 84
and lEe Publication 617-12.
V Designates 3-state outputs
~ Designates passive-pullup outputs
GPI8
I/O Ports
'----<0I1-+t-- 85
'----<0I1-+t-- 86
L---zH --.I ~/4---_....J
DOmpm 1 I~----~~~~
I
I
l _ _ _ _ _ _ .JI
T
1
1
S1to3V
S20pen
CL=15pF
(see Note
3kQ
B)l
1
1
tpZL
:.....
1-
DOmpm
S1 toGND
S2Closed
TEST CIRCUIT
tPLZ--.II
,\1 1 V
r.
'-.________________.....J
~
1-
OV
4V
1
.J1·LV__
VOL
VOLTAGE WAVEFORMS
Figure 4. TE-to-Terminal Test Circuit and Voltage Waveforms
VOL-O.8V
VOLTAGE WAVEFORMS
TEST CIRCUIT
Figure 5. PE-to-Bus Test Circuit and Voltage Waveforms
NOTES: A The Input pulse is supplied by a generator having the following characteristics: PRR
ZO=50Q.
B. CL includes probe and jig capacHance.
1ExAs
oS
1 MHz, 50% duty cycle, tr ,. 6 ns, tf oS 6 ns,
..If
INSIRUMENTS
POST OFFICE BOX 655303 • DAUAS. TEXAS 75265
2-501
SN75ALS165
OCTAL GENERAL-PURPOSE INTERFACE BUS TRANSCEIVER
SLlS023B - 03011. JUNE 1986 - REVISED AUGUST 1989
TYPICAL CHARACTERISTICS
TERMINAL HIGH-LEVEL OUTPUT VOLTAGE
TERMINAL LOW-LEVEL OUTPUT VOLTAGE
va
va
HIGH-LEVEL OUTPUT CURRENT
LOW-LEVEL OUTPUT CURRENT
0.6
4
>I
3.5
•
J
~
VCC=5V
TA=25°C _
"""'\
3
'S
a.
'S
2.5
~
2
0
~
'\
1.5
I
:t:
I'
0.4
0
0.3
I
0.2
I
~
r\.
0.5
o
~
'S
~
~
01
"- \.
o
/
0.5
3.
'\
l:
.p
>I
r\.
VCC~5V
TA=25°C
./
V
/
V
o
10
20
30
40
50
IOL - Low-Level Output Current - mA
Figure 6
Figure 7
TERMINAL OUTPUT VOLTAGE
va
BUS INPUT VOLTAGE
4
!
1-
VCC=5V
3.5 I- NoLoed
TA = 25°C
>
3
•
~
2.5
i
2
I
01
,
~
I
VT-
VT+
1.5
.p
0.5
o
o 0.2 0.4 0.6 0.8 1
1.2 1.4 1.6 1.8
VI -Input Voltage - V
Figure 8
1ExAs . "
INSIRUMENTS
2-502
/
0.1
o
-5 -10 -15 -20 -25 -30 -35 -40
IOH - High-level Output Current - mA
V
V
POST OFFICE BOX 655303 • DAUAS. TEXAS 75265
2
60
SN75ALS165
OCTAL GENERAL·PURPOSE INTERFACE BUS TRANSCEIVER
Su.s023B - 03011, JUNE 1986 - REVISED AUGUST 1989
TYPICAL CHARACTERISTICS
BUS LOW-LEVEL OUTPUT VOLTAGE
BUS HIGH-LEVEL OUTPUT VOLTAGE
vs
vs
BUS LOW-LEVEL OUTPUT CURRENT
BUS HIGH-LEVEL OUTPUT CURRENT
4
VCC=5V
TA=25°C
>I
t
3
'-.....
~
'!i
Q.
'!i
..
0
o.6
I
I
2
~
"ig
:r
'"
o.5
i
0.4
~
I..
r\.
'\
I
.p
'" ~
!
!
0.2
.p
0.1
o
-10
-20
-30
-40
-50
IOH - High-Level Output Current - rnA
-60
"""V
V
0.3
!..
'\
:r
o
o
>I
T
VCC=5V
TA = 25°C
V
./
V
o
W
V
V
1/
ioo"""
20 30 40 50 60 ~ 60 ~ 100
IOL - Low-Level Output Current - rnA
Figure 9
Figure 10
BUS OUTPUT VOLTAGE
VB
TERMINAL INPUT VOLTAGE
4
VCC=5V
No Load
TA=25°C
..
3
io
2
>I
r
r
;g
I
~
o
0.9
1.1
1.2
1.3 1.4
1.5
VI -Input Voltage - V
1.6
1.7
Figure 11
TEXAS . "
INSIRUMENTS
POST OFFICE ecix 655303 • DAUAS. TEXAS 75265
2-503
2-504
SN75ALS170
TRIPLE DIFFERENTIAL BUS TRANSCEIVER
DWPACKAGE
(TOP VIEW)
•
Three Bidirectional Transceivers
•
Driver Meets EIA Standards RS-422A and
RS-485 and CCITT Recommendations V,11
and X.27 and ANSI Standard X3.131-1986
•
High-Speed Advanced Low-Power Schottky
Circuitry
•
Designed for 25-MBaud Operation In Both
Serial and Parallel Applications
•
Low Skew ••• 6 ns Max
•
Designed for Multipoint Transmission on
Long Bus Lines In Noisy Environments
•
Low Supply Current Requirements
90 mA Max
2B
20lA
2A
NC
3B
9
3A
NC
NC - No internal connection
JPACKAGE
(TOP VIEW)
Wide Positive and Negative Input/Output
Bus Voltage Ranges
•
Driver Output CapacRy ••• ±60 mA
•
Thermal Shutdown Protection
•
Driver Positive and Negative Current
Limiting
•
Receiver Input Impedances ••• 12 kQ Min
•
Receiver Input Sensitivity •.• ±300 mVMax
•
•
Receiver Input Hysteresis ••• 60 mV Typ
•
NC
NC
Vcc
3D
30lA
•
•
1B
1A
1B
1A
GNO
20
Vee
2B
2A
3B
Function Tables
EACH DRIVER
OUTPUTS
'INPUT
D
Operates From a Single 5-V Supply
GlitCh-Free Power-Up and Power-Down
Protection
H
Features Independent Direction Controls
for Each Channel
DIR
A
B
H
L
L
H
H
L
H
X
L
Z
Z
EACH RECEIVER
description
The SN75ALS170 triple differential bus transceiver is a monolithic integrated circuit designed for
bidirectional data communication on multipoint
bus transmission lines. It is designed for balanced
transmission lines and the driver meets EIA
Standards RS-422-A and RS-485 and CCITT
recommendations V.11 and X.27 and ANSI
Standard X3.131-1986.
TEXAS
DIFFERENTIAL INPUTS
A-B
DIR
OUTPUT
R
H
?
-0.3 V < VIO < 0.3 V
VIO'" -0.3V
L
L
L
X
H
L
Z
Open
L
H
VIO,,0.3V
H = high level, L = low level, ? = indeterminate;
X = irrelevant, Z = high impedance (off)
..If
Copyrighl© 1993, Texas Instruments Incorporated
INSTRUMENTS
POST OFFICE BOX 6553CX3 • DAUAS, TEXAS 75265
2-505
SN75ALS170
TRIPLE DIFFERENTIAL BUS TRANSCEIVER
Su..s055B - 03040, AUGUST 1987 - REVISED FEBRUARY 1993
description (continued)
The SN75ALS170 operates from a single SN power supply. The drivers and receivers have active-high and
active-low enables, respectively, which are internally connected together to function as a direction control. The
driver differential outputs and the receiver differential inputs are connected internally to form differential
input/output (I/O) bus ports that are designed to offer minimum loading to the bus when the driver is disabled
or Vee = O. These ports feature wide positive and negative common-mode voltage ranges making the device
suitable for party-line applications.
The SN7SALS170 is characterized for operation from O'C to 70·C.
logic diagram (positive logic)
10lR
..;;;2~.....--,
10...;1"'--411-+--1
2DIR ...;;7_.....--,
20
...:6~H--I
3DIR ...:1..;;.,0---4'-...,
3D
...:9~H--I
t This symbol is in accordance wHh ANSI/IEEE Std 91-1984 and
lEe Publication 617-12.
Pin numbers shown are for the OW package.
1ExAs
.If
INSIRUMENTS
2-506
POST OFFICE BOX 655303 • DAUAS. TEXAS 75265
1--_~1",-9 1A
o-.....-t-=20=
18
1--_~1..:..4 2A
0-.....+-'1.::.,5 28
1-_.-...:1::,2 3A
0-.....+-'1.::.,3 38
SN75ALS170
TRIPLE DIFFERENTIAL BUS TRANSCEIVER
Sl.LS055B - 03040. AUGUST 1987 - REVISED FEBRUARY 1993
schematics of inputs and outputs
EQUIVALENT OF EACH INPUT
Vee - - -.... - - - - -
TYPICAL OF RECEIVER OUTPUT
TYPICAL OF A AND B I/O PORTS
Vce
~H'-----""
Req
180kO
NOM
eonnected
onAPort
I
I
I
I
I
Input
3kg
NOM
AorB
18 kg
NOM
180 kg
=
Driver Input: Req 12 kg NOM
Enable Inputa: Req = 8 kg NOM
NOM
1.1 kg
Connected
NOM
on B Port
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) ............................................................. 7 V
Voltage range at any bus terminal ................................................... -10 V to 15 V
Enable input voltage ....................................................................... 5.5 V
Continuous total power dissipation ..................................... See Dissipation Rating Table
Operating free-air temperature range .................................................. O'C to 70'C
Storage temperature range ....................................................... -65'C to 150'C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: OW package .................. 260'C
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: J package ..................... 300'C
NOTE 1: All voltage values. except differential I/O bus voltage. are wHh respect to network ground terminal.
DISSIPATION RATING TABLE
=
PACKAGE
TAs25°C
POWER RATING
DERATING FACTOR
ABOVE TA 25°C
TA 7O"C
POWER RATING
OW
1125mW
9.0mW/"C
720mW
J
1025mW
8.2mW/"C
656mW
=
1ExAs
~
INSIRUMENTS
POST OFFICE BOX _
• DAUAS. TEXAS 75265
2-507
SN75ALS170
TRIPLE DIFFERENTIAL BUS TRANSCEIVER
,SLLS056B - D304O, AUGUST 1987 - REVISED FEBRUARY 1993
recommended operating conditions
Supply voltage, VCC
MIN
TYP
MAX
UNIT
4.75
5
5.25
V
12
Voltage at any bus terminal (separately or common mode), VI or VIC
-7
2
V
High-level input voltage, VIH
D,DIR
Low-level input voltage, VIL
D,DIR
O.B
",12
V
Driver
-60
mA
-400
pA
Differential input voltage, VID (see Note 2)
High-level output current, IOH
Low-level output current, IOL
Receiver
V
60
Driver
8
Receiver
0
Operating free-air temparature, TA
NOTE 2: Differential-Input/output bus voltage IS measured at the nonlnvertlng terminal A With respect to the Inverting terminal B.
1ExAs ."
INSIRUMENTS
2-508
POST OFFICE BOX 655300 • OAUAS. TEXAS 752115
70
V
mA
·C
SN75ALS170
TRIPLE DIFFERENTIAL BUS TRANSCEIVER
SLLS055B - 03040, AUGUST 1987 - REVISED FEBRUARY 1993
DRIVER SECTION
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
TEST CONDITIONSt
UNIT
MIN TYpt
PARAMETER
MAX
VIK
Input clamp voltage
II =-19mA
Vo
Output voltage
10=0
VOH
High-level output voltage
VCC = 4.75 V,
VIL=0.8V,
VIH=2V,
10H =-55 mA
VOL
Low-level output voltage
VCC = 4.75 V,
VIL=0.8V,
VIH=2V,
10L=55 mA
I V OD11
Differential output voltage
10=0
0
-1.5
V
6
V
2.7
V
1.5
RL= 1000,
See Figure 1
1I2VOl?1
or2
RL=540,
See Figure 1
1.5
Vtest =-7Vto 12V,
See Figure 2
1.5
1.7
V
6
V
V
I V OD21
Differential output voltage
VOD3
Differential output voltage
AIVODI
Change in magnitude of differential output
voltage§
VOC
Common-mode output voltage
AIVocl
Change in magnitude of common-mode
output voltage§
10
Output current
Output disabled,
See Note 3
IIH
High-level input current
VI=2.4V
20
IlL
LOW-level input current
VI =0.4V
-400
VO=-6V
-250
VO=OV
-150
lOS
Short-circuit output current1l
RL=54000r1000,
2.5
V
,00.2
V
-1
,00.2
IVo= 12V
1
I VO=-7V
-0.8
250
VO=VCC
Supply current
V
5
3
See Figure 1
V
V
mA
IJA
IJA
mA
250
VO=8V
ICC
5
I Outputs enabled
I Outputs disabled
No load
69
90
57
78
mA
t The power-off measurement In EIA Standard RS-422-A applies to disabled outputs only and is not applied to combined Inputs and outputs.
All typical values are at VCC = 5 V and TA = 25°C.
§ A IVOD I and A IVoc I are the changes in magnitude ofVOD and VOC respectively, that occur when the input is changed from a high level to a
low level.
11 Duration of the short-circuit current should not exceed one second.
#The minimum VOD2 with a 100-0 load is either 1/2 VOD1 or 2 V, whichever is greater.
NOTE 3: This applies for both power on and off; refer to EIA Standard RS-485 for exact conditions. The RS-422-A limit does not apply for a
combined driver and receiver terminal.
*
TEXAS
~
INSIRUMENTS
POST OFFICE BOX 655303 • DAUAS, TEXAS 75265
2-509
SN75ALS170
TRIPLE DIFFERENTIAL BUS TRANSCEIVER
Sl.LS055B - D304O, AUGUST 1987 - REVISED FEBRUARY 1993
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
PARAMETER
IcID
TEST CONDITIONS
Dlfferentlal-output delay time
Skew
I
~
3.5
!
0
'S
3
I
VCC=5V
TA=25"C
4.5
>I
4
GI
CI
r-............ ~
2.5
!
.c
CI
:f
r--... I--..
4
I
5
I
VCC=5V
TA=25"C
4.5
GI
DRIVER LOW-LEVEL OUTPUT VOLTAGE
va
2
1.6
i
-",
I
3.5
!
I
I
3
2.5
II
11
1
...I
2
1.5
:c
...I
.p
.p
0.5
o
./
0.5
o
-20
-40
-60
-80
-100
IOH - Hlgh-Leval Output Currant - mA
-120
o
o
20
40
60
80
100
IOL - Low-Level Output Currant - mA
Figure 7
FigureS
1ExAs
..If
INSIRUMENfS
2-514
-
~~
I
I
POST OFFICE BOX 655303 • DALlAS. TEXAS 75265
120
SN75ALS170
TRIPLE DIFFERENTIAL BUS TRANSCEIVER
Su.s055B - 03040, AUGUST 1987 - REVISED FEBRUARY 1993
TYPICAL CHARACTERISTICS
DRIVER DIFFERENTIAL OUTPUT VOLTAGE
va
DRIVER OUTPUT CURRENT
HIGH-LEVEL OUTPUT CURRENT
4
,.
>I
~
'S
3.5
3
VCC=5V
TA=25·C
i'.. .........
r-........
2.5
!
0
i
~
Q
5r------,------~-------r------,------,
J
I
......
RECEIVER HIGH-LEVEL OUTPUT VOLTAGE
va
"r-........ ......
2
'" ,
1.5
\
I
Q
1\
.p
0.5
o
o
10
20
30 40 50 60 70 80
10 - Output Current - mA
-10
-40
-20
-30
10H - High-Level Output Current - mA
90 100
Figure 9
Figure 10
RECEIVER HIGH-LEVEL OUTPUT VOLTAGE
RECEIVER LOW-LEVEL OUTPUT VOLTAGE
va
vs
FREE-AIR TEMPERATURE
RECEIVER LOW-LEVEL OUTPUT CURRENT
0.6
5
>I
.
DI
4
VCC=5V
VIO=300mV
10H = - 440 ,.A
>I
.
DI
'S
!
1-
s:.
~
0.4
N
0.3
'S
3
0
!
VCd=5V 1
TA=25·C
0.5 I- VIO=-300mV
:Ii!
II
:I:
~
§
2
DI
:E
~
0.2
~
0.1
!..a
I
$
o
-40 -20
-50
./
V
o
0
20
40
60
80
TA - Free-Air Temperature - ·C
100
120
o
/
V
~
V
/'
V
V
5
10
15
20
25
10L - Low-Level Output Current - mA
Figure 11
30
Figure 12
1ExAs ~
INSIRUMENIS
POST OFFICE BOX 6SS303 • DALLAS, TEXAS 75265
2-515
SN75ALS170
TRIPLE DIFFERENTIAL BUS TRANSCEIVER
SLLS055B - 03040. AUGUST 1987 - REVISED FEBRUARY 1993
TYPICAL CHARACTERISTICS
RECEIVER LOW-LEVEL OUTPUT VOLTAGE
RECEIVER OUTPUT VOLTAGE
v.
va
ENABLE VOLTAGE
FREE-AIR TEMPERATURE
0.6
>
I
t
~
1
§
0.5
I
5
I
_I_
Vee=5V
VIO=-300mA
IOL=8mA
4
>I
0.4
IlL
i
0.3
!
0.2
~
0.1
VIO = 0.3 V
1_
Load = 8 ko to GNO
TA=25°e
1
Vee = 5.25 V
3
i
t--- Vee = 4.75 V
'"'
r-.,
' - Vee=5V
2
I
~
I
..J
o
-40 -20
0
20
40
60
80
100
TA - Free-Air Temperature - °e
o
120
o
1.5
0.5
Figure 13
Figure 14
RECEIVER OUTPUT VOLTAGE
vs
ENABLE VOLTAGE
6
5
!
~
!i
Q.
!i
,.
Vee = 5.25 V
Vee = 4.75 V
I
I
GI
CI
]1
VIO = 0.3 V
Load=1 kO to Vee
TA = 25°C
>
4
Vee=5V ../
3
0
I
~
2
o
o
0.5
1.5
2
2.5
VI - Enable Voltage - V
Figure 15
1ExAs
~
INSIRUMENTS
2--516
2
VI - Enable Voltage - V
POST OFFICE BOX 655303 • DAUAS. TEXAS 75265
3
2.5
3
SN75ALS170
TRIPLE DIFFERENTIAL BUS TRANSCEIVER
SllS055B - 03040. AUGUST 1987 - REVISED FEBRUARY 1993
APPLICATION INFORMATION
1/3SN75ALS170
1/3SN75ALS170
(see Note A)
Up to 32
Transceivers
NOTE A: The line should be terminated at both ends in its characteristic impedance. Stub lengths off the main line should be kept as short as
possible.
Figure 16. Typical Application Circuit
4Vto5.25V
4Vt05.25V
330Q
330Q
150Q
150Q
330Q
330Q
Upto8
. ..
Transceivers
Figure 17. Typical Differential SCSI Application Circuit
1ExAs
~
INSIRUMENTS
POST OFFICE BOX 655303 • DAUAS. TEXAS 75265
2-517
SN75ALS170
TRIPLE DIFFERENTIAL BUS TRANSCEIVER
Sl1.S056B - D304O, AUGUST 1987 - REVISED FEBRUARY 1993
APPLICATION INFORMATION
Vee
r--
I.
r
=Ir.
_-=tBIN/OCT~r.
.......
::n
--;:--"'-'3L_ _ _~2....--fEEHN-:--:.;J----+~ 08(7)
1 · • ::.....1-.-.14 -oe(7)
5 L:;N 1.r[:tJ < 0
8
4
EN.: ~11 ~~
13
11
L: EN IlliJ
l:L ry~rt-. . .
F
;:U:::'
--+-6 .........
~
·
4lSOO
SN7 &
SN74LAI38, ~ti2;:§:1
~
F
~
~
~
,
I-'"
II
~
-
SN74iBoo
100
101
102
8
7'
EN.: ~ ~~)
'1::;;;N IlliJ
2
SN75ALSI70
EN
.~~08(4)
1
• • ~4-oe(4)
IT
S'1::;;;N Ill::tJ
0
4
EN.: ~ 11 .:~
7 '1::;;~ I l liJ
6
6
EN.
:~.:~
L:;N 1 Il:tJ
SN75ALS1~3
2
EN.: ~4 '!J;~)
EN 1 I[ iJ
5·
10 08(0)
4
EN.: :r;::11 -08(0)
L:;N 1 1[:tJ
1
To SCSI Bus
Controller
t.t:
A
TA
Y UT
VI
SE
1
To Reset logic
. :~~
11[:tJ
14
~ .: ~1~~~
{ ::::==::'---"-..J)Q~--;-I-:;.rtI[~~SN75ALS170
Figure 18. Typical Differential SCSI Bus Interface Implementation
1ExAs
..If
INSIRUMENTS
2-518
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN75ALS171
TRIPLE DIFFERENTIAL BUS TRANSCEIVER
Su.s056B
AUGUST 1987 - REVISED FEBRUARY 1993
OW OR .. PACKAGE
(TOP VIEW)
•
Three Bidirectional Transceivers
•
Driver Meets EIA Standards RS-422A and
RS-485 and CCITT Recommendations V.11
and X.27 and ANSI Standard X3.131-1986
1R
10E
•
High-Speed Advanced Low-Power Schottky
Circuitry
•
10
GNO
GNO
Designed for 25-MBaud Operation In Both
Serial and Parallel Applications
•
•
•
4
Vee
2R
20E
20
3R
30E
Low Skew ••• 6 ns Max
Designed for Multipoint Transmission on
Long Bus Lines In Noisy Environments
2B
2A
3B
3A
3D
Function Tables
Features Independent Driver Enables and
Combined Receiver Enables
EACH DRIVER
INPUT
•
Wide Positive and Negative Input/Output
Bus VoHages Ranges
•
Driver Output Capacity •.. ±60 mA
0
H
L
•
Thermal Shutdown Protection
x
•
Driver Positive and Negative Current
UmHlng
X
•
•
•
GIHch-Free Power-Up and Power-Down
Protection
•
Low Supply Current Requirements
90 mA Max
H
H
L
H
H
H
L
L
H
X
X
L
Z
Z
Z
Z
H
?
VlDiOO.3V
L
VIO"' -0.3 V
L
L
X
H
Z
L
H
Open
H
X
OUTPUT
R
-0.3 V < VIO < 0.3 V
Receiver Input Hysteresis ..• 60 mV Typ
Operates From a Single 5-V Supply
OUTPUTS
A
B
EACH RECEIVER
Receiver Input SensltlvHy •.. ±300 mV Max
•
ENABLE
DE
CDE
DIFFERENTIAL INPUTS ENABLE
RE
A-B
Receiver Input Impedances ••• 12 kQ Min
•
1B
1A
RE
eDE
=high level,
=irrelevant,
L
Z
L
=low level, ? =indeterminate;
=high impedance (off)
description
The SN75ALS171 triple differential bus transceiver is a monolithic integrated circuit designed for bidirectional
data communication on multipoint bus transmission lines. It is designed for balanced transmission lines, and
the driver meets EIA Standards RS-422-A and RS-485 and CCITT recommendations V.11 and X.27 and ANSI
Standard X3.131-1986.
The SN75ALS171 operates from a single 5-V power supply. The drivers and receivers have individual
active-high and active-low enables, respectively, which can be externally connected together to function as a
direction control. The driver differential output and the receiver differential input pairs are connected internally
to form differential input/output (I/O) bus ports that are designed to offer minimum loading to the bus when the
driver is disabled or Vee is at QV. These ports feature wide positive and negative common-mode voltage ranges
making the device suitable for party-line applications.
The SN75ALS171 is characterized for operation from Q·C to 7Q·C.
Copyright © 1993, Texas Instruments Incorporated
TEXAS . "
INSIRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
2-519
SN75ALS171
TRIPLE DIFFERENTIAL BUS TRANSCEIVER
SLLS056B - 03041, AUGUST 1987 - REVISED FEBRUARY 1993
logic diagram (positive logic)
logic symbol t
CDE
iDE
2DE
3DE
RE
10
17
2
7
10
18
2R
3D
3R
CDE
iDE
SEN2
9
Bus
12
}
0-....-1-'1""3:
Bus
1A
20
1B
2DE
2D
14
I>
2B
12
I>
7
8
2A
15
'i74
11
14
}
0-....-1-'1""5::
1R
19
I>
'i74
6
Bus
}
RE
EN4
8
o-....+-=20:..=.~:
19
10
SEN3
3
1R
2D
G5
5EN1
3A
13
2R 6
10
3DE 11
3D
3B
3R 9
'i74
t This symbol is In accordance with ANSI/IEEE SId 91-1984 and
lEe Publication 617-12.
schematics of Inputs and outputs
EQUIVALENT OF EACH INPUT
v C C - - -......
TYPICAL OF A AND B I/O PORTS
TYPICAL OF RECEIVER OUTPUT
VCC ~~t-------+
SS~ VCC
I
I
I
I
I
Input
NOM
1SOkO
NOM
Connected
onAPort
3kO
NOM
Output
1.1 kO
NOM
=
=
Driver Input: Req 12 kO NOM
Enable Inpule: Req 8 kO NOM
1ExAs
..If
INSIRUMENIS
2-520
POST OFFICE BOX 655303 • DAUAS, TEXAS 75265
SN75ALS171
TRIPLE DIFFERENTIAL BUS TRANSCEIVER
SUS066B - 03041, AUGUST 1987 - REVISED FEBRUARY 1993
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) ............................................................. 7V
Voltage range at any bus terminal ................................................... -10 V to 15 V
Enable input voltage ....................................................................... 5.5 V
Continuous total power dissipation ..................................... See Dissipation Rating Table
Operating free-air temperature range .................................................. O°C to 70°C
Storage temperature range ....................................................... -65°C to 150°C
Lead tem perature 1,6 mm (1/16 inch) from case for 10 seconds: OW package .................. 260°C
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: J package ..................... 300°C
NOTE 1: All voltage values, except differential 1/0 bus voltage, are with respect to network ground terminal.
DISSIPATION RATING TABLE
TAS2S"C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
TA=70°C
POWER RATING
OW
1125mW
9.0mWre
720mW
J
1025mW
8.2mWre
656mW
PACKAGE
recommended operating conditions
Supply voltage, Vee
Voltage at any bus terminal (separately or common mode), VI or VIC
High-level input voltage, VIH
Low-level input voltage, VIL
MIN
NOM
MAX
UNrr
4.75
5
5.25
V
12
V
-7
I 0, eDE, DE, and RE
I D, eDE, DE, and RE
0.8
",12
Differential input voltage, VID (see Note 2)
High-level output current, 10H
low-level output current, 10L
V
2
-60
-400
Driver
Receiver
60
Driver
Receiver
Operating free-air temperature, TA
8
0
70
V
V
mA
""
mA
°e
NOTE 2: Differential-Input/output bus voltage is measured at the noninverting terminal A with respect to the inverting terminal B.
POST OFFICE BOX 855303 • DAUAS, TEXAS 75265
2-621
SN75ALS171
TRIPLE. DIFFERENTIAL BUS TRANSCEIVER
SUS056B - 03041; AUGUST 1987 - REVISED FEBRUARY 1993
DRIVER SECTION
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
TEST CONomoNst
PARAMETER
VIK
Input clamp voltage
11=-18mA
Vo
Output voltage
10=0
VOH
High-level output voltage
VCC=4.75V,
VIL=0.8V,
VIH=2V,
IOH=-55mA
VOL
Low-level output voltage
VCC=4.75V,
VIL=0.8V
VIH=2V,
IOL=55mA
I V OD11
Differential output voltage
10=0
I V OD21
Differential output voltage
VOD3
Differential output voltage
AIVool
Change in mainltUde of differential
output voltage
VOC
Common-mode output voltage
AIVocl
Change In m~nitude of common-mode
output voltage
10
Output current
IIH
High-level enable-input current
IlL
Low-level enable-input current
lOS
Short-circuit output current'
MIN
TYP*
°
RL= 1000,
See Figure 1
RL=540,
See Figure 1
1.5
Vtest =-7Vto 12V,
See Figure 2
1.5
Dand DE
Dand DE
CDE
V
6
V
2.5
5
V
",0.2
V
-1
",0.2
VO=12V
1
VO=-7V
-0.8
V
V
mA
20
VIH=2.7V
60
-100
VIL=0.4V
IlA
-900
VO=-6V
-250
VO=O
-150
No load
V
5
3
See Figure 1
250
VO=VCC
Supply current
1.7
5
mA
250
VO=8V
ICC
V
2.5
/',
CDE
V
6
V
1.5
Output disabled,
See Note 3
UNIT
-1.5
2.7
1/2VOD1
or 2#
RL=5400r1000,
MAX
Outputs enabled
69
90
Outputs disabled
57
78
*t
mA
The power-off measurement In EIA Standard RS-422-A applies to disabled outputs only and IS not applied to combined Inputs and outputs.
All typical values are at VCC = 5 V and TA = 25°C.
§ A IVODI and I!J.IVoc I are the changes in magnitude ofVOD and VOC respectively, that occur when the input is changed from a high level to a low
level.
'II Duration of the short-Circuit current should not exceed one second.
# The minimum VOD2 with 1OO-W load is either 1/2 VOD2 or 2 V, whichever is greater.
NOTE 3: This applies for both power on and off; refer to EIA Standard RS-485 for exact conditions. The RS-422-A limit does not apply for a
combined driver and receiver terminal.
1E:xAs ."
INSIRUMENTS
2-522
POST OFFICE BOX 655303 • DAUAS. TEXAS 75285
SN75ALS171
TRIPLE DIFFERENTIAL BUS TRANSCEIVER
SLLS056B - 03041, AUGUST 1987 - REVISED FEBRUARY 1993
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
PARAMETER
tdD
TEST CONDITIONS
Differential-output delay time
Skew (1IdDH-IdDLil
ltD
Differential-output transition time
RL = 54 Q,
See Figure
CL=50pF,
RU = Rl3 = 1650,
CL=60 pF,
See Figure 6
RL2=750,
"TERM=5V,
RL=540,
See Figure 3
CL= 50 pF,
RL1 =Rl3=1650,
CL=60pF,
RL2 = 75 0,
See Figure 6
RL=540,
See Figure 3
CL=50pF,
RU = Rl3 = 165 0,
CL=60 pF,
See Figure 6
RL2=75 0,
"TERM=5V,
MIN
TYpt
MAX
3
8
13
3
8
13
1
6
1
6
3
8
13
3
8
13
UNIT
ns
ns
ns
tpZH
Output enable lime to high level
RL= 1100,
See Figure 4
30
50
tpZL
Output enable time to low level
RL= 1100,
See Figure 5
30
50
ns
tpHZ
Output disable time from high level
RL= 1100,
See Figure 4
8
13
ns
ns
3
ns
tPLZ
Output disable time from low level
RL=1100,
See Figure 5
3
8
13
tpDE
Differential-output enable time
30
45
ns
Differential-output disable time
RL2 = 75 0,
See Figure 7
8
tpDZ
RU = Rl3 = 165 0,
CL=60pF,
5
10
15
ns
t All typical values are at VCC = 5 V and TA = 25°C.
SYMBOL EQUIVALENTS
DATA SHEET PARAMETER
RS-422·A
R8-485
Vo
Voa,Vob
Voa,Vob
I V OD11
VO
VO
IVOD21
VI (RL = 100 0)
Vt (RL= 540)
Vt (Test Termination
Measurement 2)
I V OD31
VlSt
Vtest
dlVODI
IIVtHVtl1
IlVtHVtll
Voe
IVosl
IVosl
dlVocl
IVos -Vosl
IVos -Vosl
lOS
IIsal,lIsbl
10
Ilxal,lIxbl
TEXAS
lia, lib
~
INSIRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2-523
SN75ALS171
TRIPLE DIFFERENTIAL BUS TRANSCEIVER
SLl.S056B - 03041, AUGUST 1987 - REVISED FEBRUARY 1993
RECEIVER SECTION
electrical characteristics over recommended ranges of common-mode input voltage, supply
voltage, and operating free-air temperature (unless otherwise noted)
PARAMETER
Pos~lve-golng
TEST CONDITIONS
threshold voltage
Vo = 2.7 V,
10=-0.4mA
Vo = 0.5 V,
10=8mA
Vr+
Vr-
Negative-going threshold voltage
Vhys
Hysteresis (VT + -
VIK
Enable-input clamp voHage
11=-18mA
VOH
High-level output voHage
VID=300mV,
See Figure 8
10H = -400 )lA,
VOL
loW-level output voltage
VID = -300 mV,
See Figure 8
IOL=8mA
TYpt
MAX
0.3
-1.5
VO=0.4Vt02.4V
II
Une input current
Other input = 0 V,
See Note 4
IIH
High-level enable-Input current
VIH=2.7V
IlL
Low-level enable-input current
VIL=0.4V
rj
Input resistance
lOS
Short-circuit output current
0.45
V
±20
)lA
IVI=12V
1
IVI =-7V
-0.8
60
-300
Supply current
No load
mA
)lA
)lA
kCl
12
VO=O
V
V
2.7
,
VID =300 mV,
V
mV
60
High-impedance-state output current
UNIT
V
-0.3*
Vr --l
10Z
ICC
MIN
-15
-85
I Outputs enabled
69
90
I Outputs disabled
57
78
mA
mA
t All typical values are at Vce = 5 V and TA = 25°C.
:I: The algebraic convention, in which the less-positive (more-negative) limit Is designated minimum, Is used In this data sheet for common-mode
input voltage and threshold voltage levels only.
NOTE 4: This applies for both power on and off; refer to EIA Standard RS-485 for exact conditions.
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature range
PARAMETER
TEST CONDITIONS
MIN
TYpt
MAX
9
14
19
ns
9
14
19
ns
UNIT
tpLH
Propagation delay time, low-to-hlgh-Ievel output
tpHL
Propagation delay time, high-to-Iow-Ievel output
Skew (jtPLH-t PHLil
2
6
ns
tpZH
Output enable time to high level
7
14
ns
tPZL
Output enable time to low level
ns
tpHZ
Output disable time from high level
tpLZ
Output disable time from low level
VID =-1.5Vto 1.5 V,
See Figure 9
CL=15pF,
See Figure 10
CL=15pF,
See Figure 10
CL= 15 pF,
t All typical values are at VCC = 5 V and TA = 25°C.
1ExAs
.Jf
INSTRUMENTS
2-524
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
7
14
20
35
ns
8
17
ns
SN75ALS171
TRIPLE DIFFERENTIAL BUS TRANSCEIVER
SLLS056B - 03041, AUGUST 1987 - REVISED FEBRUARY 1993
PARAMETER MEASUREMENT INFORMATION
Voe
1Figure 1. Driver VOD and Voe
3750
600
Vtest
1-
3750
Figure 2. Driver VOD3
t1.5V
Input
I
I
Generator
(see Note A)
tclDH ~
500
Output
3V
10%
TEST CIRCUIT
1r
50%
ttD
j4-
-+I
I
I
90%
14-
\~~-3V
IOV
I
j+-
~
tclDL
9O%j\i-I
2.5 V
I
...
50%
10%__ 2.5 V
I+-
ttD
VOLTAGE WAVEFORMS
Figure 3. Driver Test Circuit and Voltage Waveforms
NOTES: A. The input pulse is supplied by a generalor having Ihe following characteristics: PRR .. 1 MHz, 50% duty cycle, Ir .. 6 ns, If .. 6 ns,
ZO=500.
B. CL Includes probe and jig capacttance.
1ExAs . "
INSIRUMENTS
POST OFACE BOX 655303 • OAUAS, TEXAS 75265
2-525
SN75ALS171
TRIPLE DIFFERENTIAL BUS TRANSCEIVER
Su.s056B - 03041. AUGUST 1987 - REVISED FEBRUARY 1993
PARAMETER MEASUREMENT INFORMATION
Output
Input
1
OVor3V
1
8)1
CL =60 pF
(see Note
Generator
(see Note A)
1.5V\---- 3V
1 .5V
i
Output
600
1
~ 'PZH
RL = 110 0
'
1
1
j:3V
lpHZ -.l
--TEST CIRCUIT
1
ov
0.5 V
LVOH
~-f
~ Voff*OV
VOLTAGE WAVEFORMS
Figure 4. Driver Test Circuit and Voltage Waveforms
SV
RL=1100
Output
1----0,. S1
tPZL
OVor3V - - - - I
CL=50pF
(see Note 8)
Generator
(see Note A)
Inpu:i1.sV
I
50 0
~
\",1_'S_V_ _ _ : :
.. I
1
i
\2.3
----~I
Output
4tPLZ
!~6V
V
1-£ 0.5 V
" ' - VOL
TEST CIRCUIT
VOLTAGE WAVEFORMS
Figure 5. Driver Test Circuit and Voltage Waveforms
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR '" 1 MHz, 50% duty cycle, Ir'" 6 ns, If'" 6 ns,
Zo=50C.
B. CL includes probe and jig capacttance.
2-526
1ExAs ~
INSTRUMENTS
POST OFFICE BOX 655303 • DAUAS, TEXAS 75265
SN75ALS171
TRIPLE DIFFERENTIAL BUS TRANSCEIVER
SLl.S056B- 03041. AUGUST 1987 - REVISED FEBRUARY 1993
PARAMETER MEASUREMENT INFORMATION
5VO
S1
OVO
RL1 =1650
Output
Generator
(see Note A)
soc
CL=60pF
RL3 = 165 01;:' (see Note B)
5V 0
OV
S2
TEST CIRCUIT
1.5V
1.5V
~
---3V
Input
I
tctOH
1
-.I
I
14-
I
-.I
_ _ _ 3V
~
1.5V
1.5V
Input
I
OV
tclOL
v,9O%
90%~
*2.9V
OV
OV
Output
ttl)
I
--! j4- --! i4-
S1to5V
S2toOV
10%*_2.9V
tctOH
Output
I.- ttl)
-.!
r.-
'to
OV
-.! i4-
tctOL
, lt9O% 90%~::;- *2.3V
1~VIl
VOLTAGE WAVEFORMS
I
S1toOV
S2to5V
-.I
14-
~ *-2.9V
-.I
I.- ttO
VOLTAGE WAVEFORMS
NOTES: A The input pulse is supplied by a generator having the following characteristics: PRR " 1 MHz. 50% duty cycle. tr " 6 ns. tf" 6 ns.
ZO=50n
B. CL Includes probe and jig capacftance.
Figure 6. Driver Test Circuit and Voltage Waveforms
With Double-Dlfferential-SCSI Termination for the Load
1ExAs ."
INSIRUMENTS
POST OFFICE sox 65S303 • DAL.1.AS. TEXAS 75265
2-527
SN75ALS171
TRIPLE DIFFERENTIAL BUS TRANSCEIVER
SLl.S056B - 03041, AUGUST 1987 - REVIseD FEBRUARY 1993
PARAMETER MEASUREMENT INFORMATION
SV
S2
OV 0
RL1 =.1650
Ompm
OV
Generator
(see Note A)
500
RL3
SV 0
OV
-=
--- 3V
1.SV
OV
1.SV
.
~
I
I
Input
I
tPZH ~ 14I
~pm
I
~
14- tPZL
,-1-- -2.3V
I
I
~
OV
S1to3V
S2toOV
S3toSV
OV
--1V
=165 g
*
....,.-,. CL=60pF
(8se Note B)
S3
___ 3V
S1toOV
OV
S2toSV
S3toOV
~
1.SV
1.SV
Input
I
I
tPZL .... 14I
Outpm
I
I
....
v
14-
I
~
OV
tPZH
-1V
- - --2.3V
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR s 1 MHz, 50% duty cycle, Ir s 6 ns, tf s 6 ns,
ZO=50D.
B. CL Includes probe and jig capacftance.
Figure 7. Driver Differential-Enable and Disable Times With a Double-SCI Termination
-= -=
,Figure 8. ReceiverVOH and VOL
1ExAs
~
INSIRUMENI'S
2-528
POST OFFICE BOX 85S303 • DAUAS, lEXAS 75265
SN75ALS171
TRIPLE DIFFERENTIAL BUS TRANSCEIVER
SLLS056B - 03041. AUGUST 1987 - REVISED FEBRUARY 1993
PARAMETER MEASUREMENT INFORMATION
~
---3V
Generator
(see Note A)
Input
51
1.5V
a
1.5V
I
1.5V
I
tPLH~
OV
~
tPHL
0---VOH
~
OV
Output
1.3V
1.3V
VOL
TEST CIRCUIT
VOLTAGE WAVEFORMS
Figure 9. Receiver Test Circuit and Voltage Waveforms
1.5V
--",,--
S1
2ka
-1.5V ----0
J
Generator
(see Note A)
1N916 or Equivalent
5ka
500
--Jk
Input
tpZH ~
S3
3V
--_3V
~
S1t01.5V
S2 Opsn
S3Closed
Input
- - - 1.5V
I
I
OV
14I
_I
~
I
1
TEST CIRCUIT
1.5 V
I
I
Output
CL=15pF
(see Note B)
___
tpZL ---..:
VOH
1.5V
S1 to-1.5 V
0 V S2 Closed
S30pen
14--
----,.:1I -- -4.5 V
Output
- - - - OV
VOL
Input
-C\---3V
~"~Y
tpHZ
S1t01.5V
S2Closed
S3Closed
"---OV
I
I
----j4----"j
=--F'C
I
nput
----
I
I
1.5V
S1 to-1.5V
3V S2Closed
0 V S3 Closed
tPHZ~
......&-",,1
i.--~
-1.3V
Output
VOL
VOLTAGE WAVEFORMS
Figure 10. Receiver Test Circuit and Voltage Waveforms
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR " 1 MHz. 50% duty cycle. tr " 6 ns. If" 6 ns.
ZO=500.
B. CL includes probe and jig capacitance.
1ExAs ..,
INSIRUMENIS
POST OFFICE BOX 655303 • DAu.AS. TEXAS 75265
2-529
SN75ALS171
TRIPLE DIFFERENTIAL BUS TRANSCEIVER
SLLS056B - 03041. AUGUST 1987 - REVISED FEBRUARY 1993
TYPICAL CHARACTERISTICS
DRIVER LOW-LEVEL OUTPUT VOLTAGE
DRIVER HIGH-LEVEL OUTPUT VOLTAGE
vs
VS
DRIVER HIGI;I-LEVEL OUTPUT CURRENT
DRIVER LOW-LEVEL OUTPUT CURRENT
5
>I
t
~
4.5
d
3.5
3
X
>
I
I
VCC=5V
TA = 25°C
4.5
4
at
-.......... .....
......
2
.i::.
_
III
2.5
§
!P
--.. ...........
4
i
5
I
VCC=5V
TA=25°C
i
",
'5
3
0
2.5
~
2
~
1.5
~
•
1.5
I
3.5
j
I
oJ
I
X
oJ'
~
oJ'
0.5
o
I--- V"
/
0.5
o
o
-20
-40
-60
-80
-100
10H - High-Level Output Current - mA
-120
o
60
80
100
20
40
10L - Low-Level Output Current - mA
Figure 11
Figure 12
DRIVER DIFFERENTIAL OUTPUT VOLTAGE
VS
DRIVER OUTPUT CURRENT
4
,
>I
3.5
III
~
'5
Q.
'5
0
~
i
3
II
.......
VCC=5V
TA=25"C
i'.
.........
2.5
2
i'.
......
i'. ~
"\
1.5
\
Q
I
Q
oJ'
0.5
o
o
\
W
20
~
40 60 60 ~ 80
10 - Output Current - mA
~
Figure 13
TEXAS . "
INSIRUMENTS
2-530
I
I
II
POST OFFICE BOX 655303 • DAUAS. TEXAS 75265
100
120
SN75ALS171
TRIPLE DIFFERENTIAL BUS TRANSCEIVER
SLLS056B - 03041. AUGUST 1987 - REVISED FEBRUARY 1993
TYPICAL CHARACTERISTICS
RECEIVER HIGH-LEVEL OUTPUT VOLTAGE
RECEIVER HIGH-LEVEL OUTPUT VOLTAGE
vs
va
HIGH-LEVEL OUTPUT CURRENT
FREE-AIR TEMPERATURE
5
>
I
II
I
~
1
!i
0
5
_1-
VIO=0.3V
TA=25·C
4.5
>
I
4
~
3
~1:.
2.5
s:I
1.5
'"
2
CII
~
VCC = 5.25 V
/
I
.,,~
"
3.5
~
s:
2.5
-
3
2
1.5
I
x:
~
~~
~
o
~
!i
a.
!i
VCC=5V
VIO=300 mV
IOH = - 440 JAA
CII
,~
0.5
o
4
0
VCC=5V
~~
VCC = 4.75 V
x:
~
II
I
3.5 ~
4.5
0.5
-10
-20
-30
-40
IOH - High-Level Output Current - mA
o
-50
-40 -20
0
20
40
60
80
TA - Free-Air Temperature _·C
Figure 14
>I
•
vs
RECEIVER LOW-LEVEL OUTPUT CURRENT
FREE-AIR TEMPERATURE
I
I
CII
~
~
!i
a.
!i
0
i
0.4
./
0.3
0.2
oJ
I
V
/
/'
0.6
V
.,/
V
>
I
V'
i
~
i
~
V
~
I
I
_I
VCC=5V
Vlo=-300mA
0.5 r- IOL=8mA
0.4
0.3
0.2
I
oJ
~
RECEIVER LOW-LEVEL OUTPUT VOLTAGE
vs
VCC=5V
TA=25·C
0.5 f- VIO = -300 mV
120
Figure 15
RECEIVER LOW-LEVEL OUTPUT VOLTAGE
0.6
100
oJ
~
0.1
o
o
0.1
o
5
10
15
20
25
IOL - Low-Level Output Current - mA
30
-40 -20
Figure 16
0
20
40
60
80
100
TA - Free-Air Temperature - ·C
120
Figure 17
1ExAs
~
INSIRUMENTS
POST OFFICE BOX 655303 • DAUAS. TEXAS 75265
2-531
SN75ALS171
TRIPLE DIFFERENTIAL BUS TRANSCEIVER
SlLS0568 - 03041. AUGUST 1987 - REVISED FEBRUARY 1993
TYPICAL CHARACTERISTICS
RECEIVER OUTPUT VOLTAGE
RECEIVER OUTPUT VOLTAGE
va
va
ENABLE VOLTAGE
ENABLE VOLTAGE
5
8
VIO = 0.3 V
Load 8 kQ to GNO
TA=25"C
VCC=6.25V
4
>I
J
=
4.5
3.6
....
6
I
J
2.5
I
3
2
~
1.5
~
2
III
I
3 ~ VCC=4.76V
"-
"'-
J_
VCC=5.25V
I
VCC=4.75V
VCC=5V.J
~
VCC=5V
I
I
I
0.5
o
.!
I
>I
4
•
~
VIO =O.3V
Load = 1 kQ to VCC
TA=25"C
o
0.5
1.6
2
2.5
o
3
o
0.5
1
1.5
2
2.6
3
VI- Enable Voltage - V
VI - Enable Voltage - V
Figure 18
Figure 19
APPLICATION INFORMATION
1/3 SN76ALS170
1/3 SN76ALS170
(see
NoteA)
Up to 32
Transceivers
. ..
NOTE A: The line should be terminated at both ends in its characteristic impedance. Stub lengths off the main line should be kept as short as
possible.
.
Figure 20. Typical Application Circuit
1ExAs ."
INSIRUMENfS
2-532
POST OFFICE eox 655303 • DAUAS, TEXAS 75285
SN75ALS171
TRIPLE DIFFERENTIAL BUS TRANSCEIVER
SUS056B - 03041, AUGUST 1987 - REVISED FEBRUARY 1993
APPLICATION INFORMATION
4Vto 5.25 V
4Vto5.25V
3300
3300
1500
1500
3300
3300
UptOB
Trancelvera
Figure 21. lYplcal Differential SCSI Application Circuit
POST OFFICE BOX 6S5303 • DALLAS, TEXAS 75265
2-533
SN75ALS171
TRIPLE DIFFERENTIAL BUS TRANSCEIVER
SI-lS056B - 03041, AUGUST 1987 - REVISED FEBRUARY 1993
APPLICATION INFORMATION
Vee
o.oc;:;~
• ---. 3jo
F.l~,r
~
F
.
100
101
102
1
1
~
1
s t ;N
•
•
13 08(7)
J..-14 -08(7)
1.r ~ .10
;N 1 ~8
7-r=
I
8
EN
4
11
~
&
er---;
2
3
8
to
11
08(6)
-08(6)
~
08(5)
-08(5)
:
JI
EN..
6
3
:
1"; ;N
~
~
~
"'"""SN74i:So
1JI ~
08(4)
~~~
EN. :
Ia- 14 -08(4)
2
1
s t ;N
4
,........,.....
7-r=
6
r--- I:>-i o
2
;OO:SQ4
1.1'[ ~
EN..
:
~N 1
11
EN..
a 08(3)
11
~8
:
.J..-S
;N 1.r ~
-r=
SN75ALS170
EN..
1
s1"; ;N
08(2)
-08(2)
3 08(1)
~4 -D8(1)
1sl l i l a
EN..
4
:
-08(3)
: ~i 08(0)
-08(0)
;N 1 ~
7-r=
EN..
:
6
1"; ;N 1 ~
--tt:- SN75ALS170
Jf
8
9
08(P)
-08(P)
.If
5
T;~N 111[t}
a
7L;
I :tT;::
INT
To SCSI Bus
Ccnlroller
.IT;
m
tt
I
1
~N 1
III
EN..
:
tIs
~
;N 1.rl Iil
SN75ALS1i:±~
EN..
II · ~N 111( tJ
-r=
4T.
EN.
EU
7
a
E N . : : r . . : = 11
4
BP
_13
EN..: :::r;:;;:::14 ACK
-ACK
1
_1~
vcct ;N
MSG
-MSG
C/O
-C/O
10
I/O
:~i -I/O
T;~N 111[t}
--n::- EN.
ATN
-ATN
8
: ~
1I[ tI
REQ
-REQ
SN75ALS170
+~~N1
SEN2
SEN3
EN4
I!
~
1
~
6
L.l.t.TOReeetLcs;C{
9
· : :tJ~
· s[: tJ
· ::tJ
1
II[
4
SEL
J;:"15 -8EL
1
12 RST
~3 -RST
1
III
SN75ALS170
Figure 22. Typical Differential SCSI Bus Interface Implementation
1ExAs ..,
INSIRUMENIS
2-534
POST OFFICE BOX 855303 • DALLAS. TEXAS 75265
BSY
-BSY
SN75172
QUAD DIFFERENTIAL LINE DRIVER
SLlS038A-
• Meets EIA Standards RS-422-A and RS-485
• Meets CCITT Recommendations V.11 and
X.27
• Designed for Multipoint Transmission on
Long Bus Lines In Noisy Environments
OCTOBER 1980 - REVISED FEBRUARY 1993
NPACKAGE
(TOP VIEW)
1A
1Y
• 3-5tate Outputs
• Common-Mode Output Voltage Range of
-7Vt012V
• Active-High and Active-Low Enables
2Z
2Y
16
9
• Thermal Shutdown Protection
• Posltlve- and Negative-Current Limiting
Vee
15 4A
14 4Y
13 4Z
12 G
11 3Z
10 3Y
3A
DWPACKAGE
(TOP VIEW)
• Operates From Single 5-V Supply
• Low Power Requirements
• Functionally Interchangeable With
AM26LS31
1A
Vee
4A
4Y
NC
4Z
description
The SN75172 is a monolithic quad differential line
driver with 3-state outputs. It is designed to meet
the requirements of EIA Standards RS-422-A and
RS-485 and CCITT Recommendations V.11 and
X.27. The device is optimized for balanced
multipoint bus transmission at rates of up to
4 megabaud. Eaeh driver features wide positive
and negative common-mode output voltage
ranges making it suitable for party-line
applications in noisy environments.
2Z
G
NC
3Z
NC
2Y
3Y
3A
Ne - No internal connection
The SN75172 provides positive- and negative-current limiting and thermal shutdown for protection from line
fault conditions on the transmission bus line. Shutdown occurs at a junction temperature of approximately
150'C. This device offers optimum performance when used with the SN75173 or SN75175 quadruple
differential line receivers.
The SN75172 is characterized for operation from O'C to 70'C.
FUNCTION TABLE
(each driver)
INPUT
A
ENABLES
OUTPUTS
y
Z
G
G
H
H
L
H
X
X
H
L
L
H
H
X
L
H
L
L
X
L
L
H
X
L
H
Z
Z
H =high level.
X =irrelevant,
L =low level,
Z =high impedance (off)
1ExAs
~
Copyright@ 1993, Texas Instruments Incorporated
INSIRUMENIS
POST OFFICE BOX 655303 • DAlLAS, TEXAS 75265
2-535
SN75172
QUAD DIFFERENTIAL LINE DRIVER
SLLS038A- 02596, OCTOBER 1980- REVISED FEBRUARY 1993
logic diagram (positive logic)
logic symbol t
..1
4
G
12
G
"
1
1A
G
EN
G
2
2
V
3
V
6
5
10
9
3A
11
14
15
4A
12
r
C>
7
2A
4
13
3
1A
1Y
1Y
1Z
1Z
Xi
2A
2Z
6
7
5
Xi
2Z
3Y
3Z
3A
4Y
10
9
11
3Y
3Z
4Z
t This symbol is in accordance with ANSVIEEE Sid 91-1984
4A
and IEC Publication 617-12.
Pin numbers shown are for the N package.
14
15
13
4Y
4Z
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage, Vee (see Note 1) ............................................................. 7 V
Input voltage, VI .......................................................................... 5.5 V
Continuous total dissipation ........................................... See Dissipation Rating Table
Operating free-air temperature range ........................•......................... O·C to 70·C
Storage temperature range ....................................................... -65·C to 150·C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds ............................... 260·C
NOTE 1: All voltage values are with respect to the network ground terminal.
DISSIPATION RATING TABLE
PACKAGE
TAs25"C
POWER RATING
DERATING FACTOR
ABOVE TA = 25"C
TA=70"C
POWER RATING
OW
1125mW
9.0mW/"C
720mW
N
1150mW
9.2mW/"C
736mW
recommended operating conditions
Supply voltage, VCC
MIN
NOM
MAX
UNIT
4.75
5
5.25
V
0.8
V
2
High-levellnputvoHage, VIH
Low-level input voltage, VIL
Common-mode output voltage, Voc
-7 to 12
High-level output current, IOH
Low-level output current, IOL
Operating free-air temperature, TA
0
1ExAs . "
2-536
V
INSIRUMENTS
POST OFFICE BOX 655303 • DAUAS. TEXAS 75265
V
-60
rnA
60
rnA
70
"C
SN75172
QUAD DIFFERENTIAL LINE DRIVER
SLLS038A- 02596, OCTOBER 1980 - REVISED FEBRUARY 1993
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
TYpt MAX UNIT
MIN
PARAMETER
TEST CONDITIONS
VIK
Input clamp voltage
11=-lBmA
Vo
Output voltage
10=0
VOH
High-level output vo~age
VIH =2V,
VIL=O.BV,
IOH=-33mA
3.7
V
VOL
Low-level output voltage
VIH = 2V,
VIL=0.8V,
IOH=33mA
1.1
V
IV ODll
Differential output voltage
10=0
0
1.5
RL= 100Q,
See Figure 1
RL=54Q,
See Figure 1
-1.5
V
6
V
6
1/2VODl
V
or2~
IV OD21
Differential output voltage
VOD3
Differential output voltage
AIVODI
Change in magnHude of
diferential output voltage:!:
VOC
Common-mode output voltage§
AIVocl
Change in magnitude of
common-mode output voltage:!:
10
Output current wHh power off
10Z
High-impedance-state
output current
IIH
High-level input current
IlL
Low-level input current
lOS
Short-circuit output current
VO= VCC
lBO
VO=12V
500
ICC
1.5
2.5
1.5
See Note 2
VO=-7Vto 12V
Supply current (all drivers)
V
5
V
%0.2
V
-1
VO=-7Vto12V
VCC=O,
5
+3
See Figure 1
RL=54QOrl00Q,
V
V
%0.2
V
%100
!lA
%100
!lA
VI=2.7V
20
!lA
VI =0.5V
-360
rnA
VO=-7V
-180
No load
I Outputs enabled
I Outputs disabled
38
60
18
40
rnA
rnA
t All typical values are aI VCC = 5 Vand TA = 25°C.
:!: AlVoDI and AIVocl are the changes in magnitude ~ VOD and Voe, respectively, that occur when the input is changed from a high level to a low
level.
§ In EIA Standard RS-422-A, VOC, which is the average ofthe two output voltages with respect to ground, is called output offset voltage, VOS.
, The minimum VOD2 wHh a 100-Q ioad is eHher 1/2 VODl or 2 V, whichever is greater.
NOTE 2: See Figure 3-5 of EIA Standard RS-485.
SYMBOL EQUIVALENTS
DATA SHEET PARAMETER
RS-422-A
RS-485
Vo
VOa,Vob
Voa, Vob
IVODll
Vo
Vo
IVOD21
VtlRL = 100 Q)
Vt (RL= 54 Q)
Vt (Test Terminalion)
Measurement 2)
IVOD21
£\IVODI
IlVtl-IVtll
VOC
1V0si
IVosl
AIVocl
IVes-Vosl
IVos-Vosl
lOS
Ilsal,llsbl
10
Ilxal,llxbl
TEXAS
IIVtl-IVtll
lia,lib
..If
INSIRUMENTS
POST OFFICE BOX 655303 • DAllAS. TEXAS 75265
2--537
SN75172
QUAD DIFFERENTIAL LINE DRIVER
SLLS038A- 02596, OCTOBER 1980 - REVISED FEBRUARY 1993
switching characteristics, VCC
= 5 V, TA = 25°C
PARAMETER
tclD
110
Differential-output delay time
IPZH
MIN
TEST CONDITIONS
TYP
MAX
45
65
ns
80
120
ns
ns
ns
ns
ns
RL=54Q.
See Figure 2
Output enable lime 10 high level
RL= 110g,
See Figure 3
80
120
IPZL
Outpul enable lime 10 low level
RL=110g,
See Figure 4
45
80
IpHZ
Outpul disable lime from high level
RL=110g,
See Figure 3
78
115
IpLZ
Output disable lime from low levet9
RL= 110g,
See Figure 3
18
30
Differential-output lransHlon time
UNIT
PARAMETER MEASUREMENT INFORMATION
Figure 1. Differential and Common·Mode Output Voltages
---3V
~
Input
1.&V
I
I,
Generator
(eeeNot.A)
1.&V
I
Ll
r
tdD ---,.,
OV
tdD
'~2.&V
I 90%
I
~
I
I &0%
Output &0%
110%
-I I
ttl) -;-j
3VorO
TEST CIRCUIT
I
I 1- ~2.&V
i+"*- tm
VOLTAGE WAVEFORMS
Figure 2. Differential.Qutput Test Circuit and Voltge Waveforms
NOTES: A. The input pulse Is supplied by a generator having lhe following characteristics: Ir " 5 ns, If " 5 ns, PRR " 1 MHz, duty cycle = 50%,
ZO=50Q.
B. CL includes probe and slray capacHance.
2-538
1ExAs ~
INSTRUMENTS
POST OFFICE BOX 85S3Cl3 • DALLAS, TEXAS 7S265
SN75172
QUAD DIFFERENTIAL LINE DRIVER
SLLS038A- 02596. OCTOBER 1980 - REVISED FEBRUARY 1993
PARAMETER MEASUREMENT INFORMATION
r-------,
OVto3V
,:':='
"Q
-::-
~----S1
Input
Output
~_____J
3V
(see Note C)
l'
CL=SOPFI
(see Note B)
_
1.5V
I
I
3V
1.5V
~!.
~i ~1~_::
t
tPZH
I
_
Output
RL -110 0
-::-
2.3 V
tpHZ
TEST CIRCUIT
I
I
I
I
--J..--.,.I
Voff - 0 V
VOLTAGE WAVEFORMS
Figure 3. Test Circuit and Voltage Waveforms
5V
RL=1100
OVto3V
Generator
(see Note A)
-~---I
soo
-::-
S1
"<>--.-_____
- Output
I
L ______ JI
3V
(see Note C)
J . \1.5
5V
I
I
J
tpZL.: I·
CL=SOpF
(see Note B)
output
I~-- OV
~i
~
'\:.3 V
.
TEST CIRCUIT
3V
V
tpLZ
.Y-E 5V
- -f-
VOL
VOLTAGE WAVEFORMS
Figure 4. Test Circuit and Voltage Waveforms
NOTES: C. The Input pulse is supplied by a generator having the following characteristics: PRR '" 1 MHz. duty cycle = SO%. tr '" 5 ns. tf'" 5 ns.
ZO=500.
D. CL Includes probe and stray capacitance.
E. To test the active-low enable G. ground G and apply an Inverted wave10rm to G.
1ExAs
.Jf
INSIRUMENTS
POST OFFICE BOX 655303 • DAUAS. TEXAS 75265
2-539
SN75172
QUAD DIFFERENTIAL LINE DRIVER
SLLS038A- 02596. OCTOBER 1980- REVISED FEBRUARY 1993
TYPICAL CHARACTERISTICS
LOW-LEVEL OUTPUT VOLTAGE
HIGH-LEVEL OUTPUT VOLTAGE
vs
vs
HIGH-LEVEL OUTPUT CURRENT
LOW-LEVEL OUTPUT CURRENT
5
5
, ---
VCC=5V
TA=25°C -
4.5
>
I
3.5
5CL
5
0
§
>
III
CI
""'-
............... "
3
..............
2.5
~
2
3.5
5CL
5
3
0
2.5
~
2
!
1.5
I
I
I
I
..-
...J
:t:
.p
"
0.5
0.5
o
o
o
-20
-60
-40
-80
-100
-
1.5
I
I
-J>
~
~
./:.
~
4
I
4
III
I
VCC=5V
TA = 25°C
4.5
-120
o
20
IOH - High-Level Output Current - rnA
........
I
I
~
5CL
5
0
iii
3
r--......
vs
OUTPUT CURRENT
OUTPUT VOLTAGE
2.5
.........
, ,
!!!
~
is
~
40
20
C
~
:::I
10
5CL
5
r'\
1.5
c(
I
I
0
.9
1\
I
1\
0.5
10
20
30
40
50
60
70
10 - Output Current - rnA
-10
80
-20
"'I'-
VCC = 5V
Ii
-40
90
-50
-25 -20 -15 -10 -5 0
5 10 15
Vo - Output Voltage - V
Figure 7
Figure 8
TEXAS
,If
INSlR.UMENTS
2--540
I
.,.
0
-30
\
o
I
TA = 25°C
I
o
I
t- Output Disabled
,VCC=OV
U
C
~
120
30
;I
c
50
I . I
I
VCC=5V
TA=25°C -
.......
2
100
OUTPUT CURRENT
VS
4
III
80
Figure 6
DIFFERENTIAL OUTPUT VOLTAGE
>
60
40
10L - Low-Level Output Current - rnA
Figure 5
3.5
../
POST OFFICE BOX 655303 • DAUAS. TEXAS 75265
i
20
25
SN75172
QUAD DIFFERENTIAL LINE DRIVER
SLLS038A- 02596, OCTOBER 1980 - REVISED FEBRUARY 1993
TYPICAL CHARACTERISTICS
SUPPLY CURRENT
SUPPLY CURRENT
100
c(
E
70
I
80
~
Q.
:I
UI
va
SUPPLY VOLTAGE
SUPPLY VOLTAGE
I
30
I
_ NoLoed
90
Outputs Enabled
80 _ TA=25°e
I
u
I
vs
50
I#'
A~
40
I
U
E
30
20
.,... ~
10
o
~
~
Inputs open~
o
2
~
3
5lI:
I
,
:I
15
~
Q.
Q.
/
:I
UI
10
I
u
o
678
V
/
/
/
V
/
E
5
5
I
20
U
Inputs
Groundecr-
~
4
I
~
I
NoLoed
Input Open
25 f-- Output Disabled
TA=2Soe
o
L
Vee - Supply Voltage - V
Figure 9
6
3
4
2
5
Vee - Supply Voltage - V
7
8
Figure 10
APPLICATION INFORMATION
1/4SN75173
Up to 32
Driver!Receiver Pairs
1/4SN75175
• • •
1/4SN75172
1/4 SN75173
1/4SN75173
1/4SN75174
NOTE: The line length should be terminated at both ends in its characteristic impedance. Stub lengths off the main line should be kept as short
as possible.
Figure 11
1ExAs
~
INSIRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2~41
2-542
SN65ALS172A, SN75ALS172A
QUAD DIFFERENTIAL LINE DRIVERS
SllS121B-
• Meets EIA Standards RS-422-A and RS-485
AUGUST 1990 - REVISED MARCH 1993
SN75ALS172A ••• N PACKAGE
(TOP VIEW)
• Meets CCITT Recommendations V.11
and )(,27
Vcc
• High-Speed Advanced Low-Power Schottky
Circuitry
4A
4Y
4Z
G
• Designed for 2D-MBaud Operation In Both
Serial and Parallel Applications
• Designed for Multipoint Transmission on
Long Bus Lines In Noisy Environments
3Z
• Low Supply Current Requirements
55 mA Max
2A
3Y
GND
3A
• Wide Positive and Negative Input/Output
Bus Voltages Ranges
DWPACKAGE
(TOP VIEW)
• Driver Output Capacity ••• :1:60 mA
• Thermal Shutdown Protection
• Driver Positive and Negative Current
Limiting
Vcc
1Y
NC
4A
4Y
NC
• Functionally Interchangeable With SN75172
4Z
G
3Z
description
2Y
The SN65ALS172A and SN75ALS172A are quad
line drivers with 3-state differential outputs. They
are designed to meet the requirements of EIA
Standards RS-422-A and RS-485 and CCITT
Recommendations V.11 and X.27. These devices
are optimized for balanced multipoint bus
transmission at rates of up to 20-Mbaud. Each
driver features wide positive and negative
common-mode output voltage ranges making
them suitable for party-line applications in noisy
environments.
The SN65ALS172A and SN75ALS172A provide
positive- and negative-current limiting and thermal
shutdown for protection from line fault conditions
on the transmission bus line. Shutdown occurs at
a junction temperature of approximately 150'C.
2A
GND
NC
9
10
3Y
11 3A
........
'---
NC-No internal connection
FUNCTION TABLE
(each driver)
INPUT
A
H
L
H
L
X
ENABLES
OUTPUTS
G
G
Z
H
H
X
X
L
L
Y
H
L
H
X
X
L
H
H =high level, L =low level,
Z =high impedance (off)
L
H
L
L
H
Z
Z
X
=Irrelevant,
The SN65ALS172A is characterized for operation
from -40'C to 85'C and the SN75ALS172A is
characterized for operation from O'C to 70'C.
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
Copyright@1993, Texas Instruments Incorporated
2-543
SN65ALS172A, SN75ALS172A
QUAD DIFFERENTIAL LINE DRIVERS
SLLS121 B - 03554, AUGUST 1990 - REVISED MARCH 1993
logic diagram (positive logic)
logic symbol t
GI
GI
G
G
2
1A
1Y
1A
3
1Z
6
2V
2A
2A
6
3A
10
11
2Z
3Y
3A
3Z
14
4Y
4A
4A
4Z
13
t This symbol Is in accordance with ANSI/lEEE Std 91-1984 and
lEe Publication 617-12.
Pin numbers shown are for the N package.
schematics of inputs and outputs
EQUIVALENT OF EACH INPUT
VCC---........
36kONOM
TYPICAL OF ALL OUTPUTS
-----...---vCC
Input
Output
GlND
1ExAs
2-544
~
INSIRUMENfS
POST OFFICE BOX 655303 • DAUAS, TEXAS 75265
1Y
1Z
2V
2Z
3Y
3Z
4Y
4Z
SN65ALS172A, SN75ALS172A
QUAD DIFFERENTIAL LINE DRIVERS
SLLS121B - 03654, AUGUST 1990- REVISED MARCH 1993
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) ............................................................. 7 V
Input voltage, VI ........................................•................................... 7 V
Output voltage range, Vo ........................................................... -9 V to 14 V
Continuous total dissipation ........................................... See Dissipation Rating Table
Operating free-air temperature range: SN65ALS172A ................................ -40°C to 85°C
SN75ALS172A .................................. O°C to 70°C
Storage temperature range ....................................................... -65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds ............................... 260°C
NOTE 1: All voRage values are with respect to network ground terminal.
DISSIPATION RATING TABLE
=
DERATING
FACTOR
TA=70°c
POWER RATING
TA 85°C
POWER RATING
1125mW
9mwrc
720mW
585mW
1150 mW
9.2mWrC
736mW
598mW
PACKAGE
TAS25°c
POWER RATING
OW
N
recommended operating conditions
Supply voltage, VCC
High-level input voltage, VIH
MIN
NOM
MAX
UNIT
4.75
5
5.25
V
V
2
Low-level input voHage, VIL
0.8
V
Common-mode output voltage, VOC
+12
-7
V
High-level output current, IOH
-60
mA
60
mA
Low-level output current, IOL
Operating free-air temperature, TA
I
SN65ALSI72A
-40
85
I
SN75ALSI72A
0
70
1ExAs
°c
,If
INSIRUMENTS
POST OFFICE BOX 656303 • DAllAS, TEXAS 71!265
2-545
SN65ALS172A, SN75ALS172A
QUAD DIFFERENTIAL LINE DRIVERS
SLLS121B - 03554, AUGUST 1990- REVISED MARCH 1993
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
PARAMETER
TEST CONDtnONS
VIK
Input clamp voltage
II =-18mA
Vo
Output voltage
10=0
IVOD11
Differential output voltage
10=0
IV OD21
Differential output voltage
VCC=5V,
RL= 1000
IVOD31
Differential output voltage
"'IVODI
Change In magnitude of
differential output voltage*
VOC
Common-mode output voltage§
"'IVocl
Change in magnitude of
common-mode output voltage*
TYpt
MIN
°
1.5
See Figure 1
UNIT
V
6
V
6
V
112VOD1
or 2'
RL=540
1.5
See Note 2
1.5
RL = 54 0 or 100 0,
MAX
-1.5
V
2.5
See Figure 1
5
5
V
.,0.2
V
+3
-1
V
.,0.2
V
.,100
10
Output current with power off
Vce=O,
10Z
High-impedance-state output current
VO= -7Vto 12V
IIH
High-level input current
VI=2.7V
20
IlL
Low-level input current
VI=0.4V
-100
IlA
IlA
IlA
IlA
lOS
Short-circuit output current
VO= -7Vto 12V
.,250
mA
ICC
Supply current (all drivers)
No load
VO= -7Vt012V
.,100
Outputs enabled
36
55
I Outputs disabled
15
30
mA
t All typical values are at VCC = 5 V and TA = 25°C.
* '" I VODI and'" I Voe I are the cI1anges In magnitude of VOD and VOC respectively, that occur when the Input Is changed from a high level to
a low level.
§ In EIA Standard RS-422-A, Voe, which Is the average of the two output voltages with respect to ground,ls called output offSat voltage, VOS.
'The minimum VOD2 with a 100-0 load is either 1/2 VOD1 or 2 V, whlchevsr Is greater.
NOTE 2: See EIA Standard RS-485, Figure 3-5, Test Termination Measurement 2.
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, CL =50 pF
MIN
TYpt
MAX
IdD
Differential-output delay time
RL=540,
See Figure 2
9
15
22
ns
tPZH
Output enable time to high level
RL=110Q,
See Figure 3
30
45
70
ns
tpZL
Output enable time to low level
RL=110Q,
See Figure 4
25
40
65
ns
tpHZ
Output disable time from high level
RL=110Q,
See Figure 3
10
20
35
ns
tpLZ
Output disable time from low level
RL=1100,
See Figure 4
10
30
45
ns
PARAMETER
TEST CONDITIONS
t All typical values are at Vce = 5 V and TA = 25°C.
1ExAs ,.,
INSIRUMENTS
2-546
POST OFFICE SOX 855303 • DAllAS, TEXAS 75265
UNIT
SN65ALS172A, SN75ALS172A
QUAD DIFFERENTIAL LINE DRIVERS
SLLS121B- D3554.AUGUST 1990- REVISED MARCH 1993
PARAMETER MEASUREMENT INFORMATION
Figure 1. Differential and Common-Mode Output Voltages
.----.-e---T"
Generator
(aeeNoteA)
500
3V--L....r--
T.".
CL=50pF
(see Note B)
3V - - -__- - - - _
Y
Input
Z
OutputZ
0'
--tI
1.8V
I+-IcIDH
1.SV
,-----tI *-IcIDL
~-----;t.
OutputY - - - ' ' - - - - - -
TEST CIRCUIT
VOLTAGE WAVEFORMS
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR = 1 MHz. Zo = 50 0. duty cycle = 50%. tf S 5 ns.
tr s5ns.
B. CL Includes probe and stray capacitance.
Figure 2. Differential Output Test Circuit and Voltage Waveforms
1ExAs
~
INSIRUMENTS
POST OFFICE BOX 6S5303 • DAUAS. TEXAS 75265
2-547
SN65ALS172A, SN75ALS172A
QUAD DIFFERENTIAL LINE DRIVERS
Su.s1218 - 03554, AUGUST 1990 - REVIseD MARCH 1993
PARAMETER MEASUREMENT INFORMATION
j------'
Output
3V
OVor3V
Generator
(888 Note A)
) . 1.5V
I
CL=50pF
,--7"----(888 Note B)
OV
T
3V
~ (see Note C)
~
RL=110g
I+-
tpZH
I
~
i
OutP_ut_ _J h.3 V
tpHZ
TEST CIRCUIT
I
I
I
--.I
VOLTAGE WAVEFORMS
Figure 3. Test Circuit and Voltage Waveforms, tpZH and tpHZ
5V
S1
Generator
(see Note A)
I
Output
CL=50pF
L_ _ _ _ _ _ _ (888
Note B)
3V
(see Note C)
T
~1.5-;---
Inp~1'5V
RL= 110 g
tpZL
Output
~
3V
OV
~I
I
~3V
I
i+---+II
~
tpl2
,lU,-
5V
VOL
0.5 V
TEST CIRCUIT
VOLTAGE WAVEFORMS
Figure 4. Test Circuit and Voltage Waveforms, tpZL and tPL2
NOTES: A. The input pulse is supplied by a generator having Ihe following characteristics: PRR = 1 MHz, Zo = 50 g, duty cycle = 50%, If s 5 ns,
\rs5ns.
B. CL Includes probe and stray capacilance.
C. To lesllhe active-low enable G, ground G and apply an inverted input waveform 10 G.
1ExAs
~
INSIRUMENTS
2-548
POST OFFICE BOX 655303 • 0AlJJ\S. TEXAS 7526~
SN55173, SN65173, SN75173
QUAD DIFFERENTIAL LINE RECEIVERS
SLLSl44A-
• Meets EIA Standards RS-422-A, RS-423-A,
and RS-485
OCTOBER 1980 - REVISED FEBRUARY 1993
0, J, OR N PACKAGE
(TOP VIEW)
• Meets CCITT Recommendations V.10, V.11,
X.26, and X.27
1B
1A
• Designed for Multipoint Bus Transmission
on Long Bus Lines in Noisy Environments
• 3-5tate Outputs
• Common-Mode Input VoHage Range of
-12Vto 12V
Vee
4B
4A
4Y
IT
2B
GND
• Input Sensitivity ••• :t200 mV
• Input Hysteresis •.• 50 mV Typ
• High Input Impedance ••• 12 kQ Min
3Y
3A
SN55173 ••• FK PACKAGE
{TOP VIEW)
• Operates From Single 5-V Supply
• Low Power Requirements
• Plug In Replacement for AM26LS32
description
1Y
17 4Y
G
5
The SN55173, SN65173, and SN75173 are
NC
16 NC
6
monolithic quad differential line receivers with
2Y
15 IT
7
3-state outputs. They are designed to meet the
8
14 3Y
2A
requirements of EIA Standards RS-422-A,
9 1011 1213
RS-423-A, RS-485, and several CCITT
recommendations. The devices are optimized for
IDCOID
3
V
6
7
...
5
...
11
...
13
10
9
14
15
lY
lA
lB
3
2A
5
2B
3Y
3A
4Y
11
3B
t This symbol is in accordance with ANSVIEEE SId 91-1984
4A
and lEe Publication 617-12.
Pin numbers shown are for the 0, J, and N packages.
48'
13
1Y
2Y
3Y
4Y
FUNCTION TABLE
(each receiver)
DIFFERENTIAL
A-B
VID~0.2V
ENABLES
G
G
H
X
X
L
H
-0.2 V < VII) < 0.2 V
X
VID" -0.2V
X
X
L
H =high level,
X = irrelevant,
H
OUTPUT
X
Y
H
H
L
?
?
X
L
L
L
H
Z
L =low level, ? =indeterminate,
Z = high impedance (off)
schematics of Inputs and outputs
EQUIVALENT OF EACH A OR B INPUT
Vce
-,------<.-----<.-
EQUIVALENT OF G OR G INPUT
Vcc---'"
TYPICAL OF ALL OUTPUTS
Vcc
lOCke
NOM
Input
16,ake
NOM
Input
Output
lOCke
NOM
1ExAs
~
INSIRUMENTS
2-550
POST OFFICE BOX 655300 • DAUAS, TEXAS 75265
SN55173, SN65173, SN75173
QUAD DIFFERENTIAL LINE RECEIVERS
SLLS144A- 02600, OCTOBER 1980 - REVISED FEBRUARY 1993
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) ............................................................. 7 V
Input voltage, A or B inputs ................................................................ ±25 V
Differential input voltage (see Note 2) ....................................................... ±25 V
Enable input voltage ......................................................................... 7 V
Low-level output current .................................................................. 50 rnA
Continuous total dissipation ........................................... See Dissipation Rating Table
Operating free-air temperature range, TA: SN55173 ................................ -55·C to 125·C
SN65173 .................................. -40·C to 85·C
SN75173 .................................... O·C to 70·C
Storage temperature range ....................................................... -65·C to 150·C
Case temperature for 60 seconds: FK package .............................................. 260·C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: D or N package ................ 260·C
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: J package ..................... 300·C
NOTES: 1. All voltage values, except differential input voltage, are with respect to network ground terminal.
2. Differential-input voltage is measured at the noninverting input with respect to the corresponding inverting input.
DISSIPATION RATING TABLE
PACKAGE
TA,,25°C
POWER RATING
DERATING
FACTOR
TA = 70°C
POWER RATING
TA=85°C
POWER RATING
TA=I25°C
POWER RATING
D
950mW
7.BmWrC
B08mW
494mW
FK
1375mW
11.0 mWrC
880mW
715mW
275mW
J
1375mW
11.0mWrC
880mW
715mW
275mW
N
1150mW
9.2mWrC
736mW
598mW
recommended operating conditions
Supply voltage, VCC
SN55173
SNB5173, SN75173
MIN
NOM
MAX
4.5
5
5.5
4.75
5
5.25
UNIT
V
Common-mode input voltage, VIC
,.12
V
Differential input voltage, VID
,.12
V
High-level enable-input voltage, VIH
Low-level enable-input voltage, VIL
0.8
High-level output current, IOH
Low-level output current, IOL
Operating free-air temperature, TA
V
2
V
-400
!AA
16
mA
SN55173
-55
125
SN65173
-40
85
SN75173
0
70
°c
1ExAs ."
INSIRUMENTS
POST OFFICE BOX 655303 • DAUAS. TEXAS 75265
2-551
SN55173, SN65173, SN75173
QUAD DIFFERENTIAL LINE RECEIVERS
SL.LS144A- 02600, OCTOBER 1980 - REVISED FEBRUARY 1993
electrical characteristics over recommended ranges of common-mode input voltage, supply
voltage, and operating free-air temperature
PARAMETER
TEST CONDITIONS
VT+
VT-
Positive-going input threshold voHage
VO= 2.7V,
10 =-0.4 rnA
Negative-going Input threshold voHage
VO= 0.5V,
10=16mA
Vhvs
Hysteresis (VT
+- VT~
See Figure 4
VIK
Enable-Input clamp voltage
11=-1BmA
MIN
TYpt
MAX
0.2
50
mV
-1.5
VOH
High-level output voltage
VID = 200 mV,
IOH = -400 j.tA
VOL
Low-level output voltage
VIO = -200 m\l,
See Figure 1
10Z
High-impedance-state output current
2.5
SN65173,
SN75173
2.7
IOL=8mA
0.45
IOL=16mA
0.5
,.20
VO= 0.4Vto2.4V
VI = 12V
1
VI =-7V
-0.8
Other Input at 0 V,
IIH
High-level enable-input current
VIH=2.7V
20
IlL
Low-level enable-input current
VIL=0.4V
-100
rl
Input resistance
lOS
Short-circuit output current§
ICC
Supply current
See Note 3
V
V
Line input current
II
V
V
-0.2*
SN55173
UNIT
V
j.tA
rnA
j.tA
j.tA
kg
12
-15
Outputs disabled
-85
rnA
70
rnA
t All typical values are at VCC = 5 \I, TA = 25"C.
:I: The algebraic conventlon,ln which the less positive (more negative) limit is designated as minimum, is used in this data sheetforthreshold voltage
levels only.
§ Not more than one output should be shorted at a time, and the duration of the short Circuit should not exceed one second.
NOTE 3: Refer to EIA Standards RS-422A and RS423-A for exact conditions.
switching characteristics, Vee
=5 V, TA =25°e
PARAMETER
TEST CONDITIONS
TYP
MAX
20
35
ns
22
35
ns
See Figure 2
17
22
ns
See Figure 3
20
25
ns
CL= 5 pF,
See Figure 2
21
30
ns
CL= 5 pF,
See Figure 3
30
40
ns
tpLH
Propagation delay time, low-to-high-Ievel output
VID = -1.5 Vto 1.5 \I,
tpHL
Propagation delay time, hlgh-to-Iow-Ievel output
See Figure 1
tPZH
Output enable time to high level
CL=15pF,
tPZL
Output enable time to low level
CL= 15pF,
tpHZ
Output disable time from high level
tpLZ
Output disable time from low level
CL= 15 pF,
1ExAs . "
INSIRUMENfS
2-552
POST OFFICE BOX 655303 • DAUAS, TEXAS 75265
MIN
UNIT
SN55173, SN65173, SN75173
QUAD DIFFERENTIAL LINE RECEIVERS
SUSl44A- D26OO. OCTOBER 1980 - REVISED FEBRUARY 1993
PARAMETER MEASUREMENT INFORMATION
Generator
(see Note A)
Ir
I~
~-;;;--1:.:V)
Input
>-~..- Output
~U"
tpLH -+I I+-
CL =15pF
(see Note B)
'I
~
1.3V
Output
V)
+---VOH
1.3V
VOL
.J
2V
j\::- -1.&V
-+I I+- tpHL [-2.&
VOLTAGE WAVEFORMS
TEST CIRCUIT
Figure 1. tpLH. tpHL Test Circuit and Voltage Waveforms
vcc
Input
E;;;S~ ~3~ -
~',""
tPZH
I
(eee Note C)
I
~
Output
S1 Open
2V
Generator
(see Note A) 1------(8-'ee Note D)
-
3V
~OV
-+I;+- tpHZ --.! l+-
_
O.&V
S
~-*--VOH
_
_
':3~ __ 0 V '" S1 ~~~:e:
VOLTAGE WAVEFORMS
SOO
TEST CIRCUIT
Figure 2. tpHZ. tpZH Test Circuit and Voltage Waveforms
[ ) represent voltages on the SN55173 only.
NOTES: A The input pulse is supplied by a generator having the following characteristics: PRR = 1 MHz. duty cycle = 50%. tr s 6 ns. tf S 6 ns.
ZO=50n
B. CL includes probe and jig capacitance.
C. All diodes are 1N916 or equivalent.
D. To test the active-low enable G. ground G and apply an inverted input waveform to G.
1ExAs
.Jf
INSIRUMENTS
POST OFFICE SOX 655303 • DAUAS. TEXAS 75265
2-553
SN55173, SN65173, SN75173
aUAD DIFFERENTIAL LINE .RECEIVERS
SLLSl44A- 02600. OCTOBER 1980- REVISED FEBRUARY 1993
PARAMETER MEASUREMENT INFORMATION
VCC
2kO
'T
, "::"
S~----3V
1.3V
1.3V
~
Input
I
Cl
(_NoteB)
6J(g
(_Note C)
tpZL -.: t4-S2 Open
I
.J
Generator
( - Note A)
I
-..:
OV
!.- tptz
I
I
S2 Closed
_1.4V
1.3V
_oL_
~~
Output
2V
1--...._(_.-1 Note D)
S
--...--
SOO
VOLTAGE WAVEFORMS
VOL
0.5 V
TEST CIRCUIT
Figure 3. tPZLo tpLZ Test ClrcuH and Voltage Waveforms
NOTES: A. The Input pulse is supplied by a genarator having the following characteristics: PRR = 1 MHz. duty cycle = 50%. tr " 6 ns. tf" 6 ns.
Zo =50 O.
B. CL Includes probe and jig capacftanca.
C. All diodes are 1N916 or equivalent.
D. To test the active-low enable G. ground G and apply an inverted Input waveform to G.
TYPICAL CHARACTERISTICS
OUTPUT VOLTAGE
HIGH·LEVEL OUTPUT VOLTAGE
VB
vs
DIFFERENnAL INPUT VOLTAGE
HIGH·LEVEL OUTPUT CURRENT
5
5
VCC=5V
10=0
I5
!
3.5
3
=
VIC
-12V
VT-
VT-
VT+
I
!,
VT+
4
i
.'
VIC =
VIC =
I-- 12V - f-0
I
I
2.5
2
4.5
>
4
>I
&
VID-0.2V
TA=25°C
TA = 2S"C
4.6
i
o
I
VTVT+
I
~ 1.5
3.5
~
3
.......
,
"," ,'" ~
',
VCC=5.5V
......
2.5
i
I,
.......
...... ~:'\
I
roo..........
:E:
~
o
-125 -100-75 -SO -25 0 25 SO 76 100 125
VID - DIfferet1tlat Input Voltage - mV
1
/.
VCC=4,6V
0.5
o
o
"2\
.
""
.......
FigureS
1ExAs
"l'\
-5 -10 -15 40 -a; -30 ~ -40 -46-SO
IOH - High-level Output Current - mA
Figure 4
.Jf
INSIRlJMENIS
2-654
/'
~
'~"
~
2
:E 1.5
0.5
VCC=5V
POST OFFICE BOX 655303 • oAUAS. TEXAS 75265
SN55173,SN65173,SN75173
QUAD DIFFERENTIAL LINE RECEIVERS
SLLS1~-D26OO,
OCTOBER 1980-REVISED FEBRUARY 1993
TYPICAL CHARACTERISTICS
LOW·LEVEL OUTPUT VOLTAGE
HIGH·LEVEL OUTPUT VOLTAGE
va
va
FREE-AIR TEMPERATURE
LOW·LEVEL OUTPUT CURRENT
0.6
5
,
>
I
II
~
!i
Do
!i
0
~
1:.
at
%
VCC=5V
4.5 - VIO=0.2V
IOH = -400 ..,A
4
>,
3.5
at
I
/
SN651730nly _
3
0.4
!i
~
2.5
0
)
2
1.5
I
%
~
0.5
II
-W' •
0.3
0.2
V
/
'/
~ 0.1
0.5
o
w
o
~
~
~
~
~
~
~
~
o
TA - Free-Air Temperature - ·C
5
~
25
30
OUTPUT VOLTAGE
va
vs
FREE-AIR TEMPERATURE
ENABLE G VOLTAGE
0.5
5
VCC=5V
VIO=-0.2V
IOL=8mA
VIO =O.2V
Load = 8 kg to GNO
TA=25·C
4.5
I
_I
VCC =5.5V
4
j
1.
15
Figure 7
LOW·LEVEL OUTPUT VOLTAGE
0.4
10
IOL - Low-Level Output Current - mA
Figure 6
I
~V
/
/"
L
loJ
o
>
V
I
VCC=5V
TA=25·C
>I
VCC=5V
3.5
I
II
,
)-
0.3
!i
o
'ii
1.~ 2.5
SN65173 Only
~ 0.2
..
VCC =4.5V
3
6
~
2
I
~ 1.5
oJ
I
5 0•1
1
::;;
0.5
o
o
10
~
~
~
~
~
~
~
~
o
o
0.5
TA - Free·Air Temperature - ·C
Figure 8
1.5
2
2.5
VI- Enable G Voltage - V
3
Figure 9
1ExAs ",
INSIRUMENTS
POST OFFICE BOX 655303 • DAu.AS. TEXAS 75285
2-555
SN55173,SN65173,SN75173
QUAD DIFFERENTIAL LINE RECEIVERS
SLLS144A- 02600. OCTOBER 1980 - REVISED FEBRUARY 1993
TYPICAL CHARACTERISTICS
INPUT CURRENT
OUTPUT VOLTAGE
V8
vs
ENABLE G VOLTAGE
INPUT VOLTAGE
6
I
I
VID=-0.2V
Load =1 kC to Vee
TA=25oe
Vee=5.5V
5
Vee=5V
0.75
Vee=4.5V
~
0.5
I
0.25
j
o
i
.!ii -0.25 1--+----1----::.,j£-+---:
I
-0.75
o
o
0.5
1.5
2
2.5
-6 -4 -2
3
VI- Enable G VoRage - V
0
2
4
6
8
10
12
VI -Input Voltage - V
Figure 10
Figure 11
APPLICATION INFORMATION
1/4SN65175
1/4SN75175
1/4SN76172
1/4SN75174
1/4SN65173
1/4SN75173
1/4 SN75172
1/4 SN65173
1/4SN75173
1/4 SN65173
1/4SN75173
1/4 SN75174
NOTE: The line should be tennlnated at both ends In Hs characteristic impedance. Stub lengths off the main line should be kept as short as
possible.
Figure 12. Typical Application Circuit
1ExAs
-If
INSJRUMENTS
2-556
POST OFFICE BOX 855303 • DAUAS. TEXAS 75265
SN75ALS173
QUAD DIFFERENTIAL LINE RECEIVER
SEPTEMBER 1991 - REVISED JANUARY 1993
Sl.lS132B-
•
•
Meets CCITT Recommendations V.10, V.11,
>C.26, and >C.27
•
Designed for Multipoint Bus Transmission
on Log Bus Unes In Noisy Environments
•
•
3-State Outputs
•
•
•
•
•
N OR Nst PACKAGE
Meets EIA Standards RS-422-A, RS-423-A,
and RS-485
(TOP VIEW)
18
1A
Vee
2Y
G
2A
3Y
3A
48
4A
4Y
Common-Mode Input Voltage Range of
-12Vt012V
Input Sensitivity ••• ±200 mV
t The NS package is only available left-end taped and
reeled (order device SN75AlS173 NSlE).
Input Hysteresis ••• 50 mV Typ
logic symbol:!:
High Input Impedance ••• 12 kQ Min
Operates From Single SOV Supply
G
Low Supply Current Requirement
27mAMax
G
4
12
2
,,]
1A
1
18
description
The SN75ALS173 is a monolithic quad differential
line receiver with 3-state outputs. It is designed to
meet the requirements of EIA Standards
RS-422-A, RS-423-A, and RS-485 and several
CCITT recommendations. Advanced low-power
Schottky technology provides high speed without
the usual power penalty. The four receivers have
an ORed pair of enables in common. Either G
being high or G being low enables all of the
receivers. The device features high input
impedance, input hystereSiS for increased noise
immunity, and input sensitivity of ±2DD mV over
a common-mode input voltage range of -12 V
to 12V.
2A
28
3A
38
4A
48
~1
"-
I
EN
JTI>
3
V
6
1Y
5
7
10
9
"
11
"-
14
15
*
13
"
3Y
4Y
This symbol is In accordance with ANSI/IEEE Std 91-1984 and
lEe Publication 617-12.
logic diagram (positive logic)
The SN75ALS173 is characterized for operation
from D·C to 7D·C.
G
G
1A
---""L-_
3
18
2A
28
3A
38
4A
4B
5
>--+-11
>--+-13
>----
1Y
2Y
3Y
4Y
Copyright © 1993, Texas Instruments Incorporated
1ExAs ."
INSIRUMENTS
POST OFFICE BOX 655303 • DALlAS, TEXAS 75265
2-557
SN75ALS173
(
QUAD DIFFERENT1AlliNERECEIVER
SllSl32B - D3886, SEPTEMBEFlI991 - FlEVlSED JANUAFlY 1993
FUNCTION TABLE
(each receiver)
DIFFERENTIAL INPUTS
A-B
VIO,"0.2V
ENABLES
G
G
H
X
X
L
OUTPUT
y
H
H
-0.2V-++-- Output
:........II
CL=1SpF
(see Note B)
tPLH
I":"
2.SV
I\=-- -2.S V
U Y
-+I I+-+I I+- tPHL
~:-~-:-VOH
Output ~1.3V
~
VOL
2V
TEST CIRCUIT
VOLTAGE WAVEFORMS
Figure 2. Test Circuit and VoHage Waveforms
J
VCC
Output
2kC
~~~____- .__~__~~.-~Sr1
Input
tPZH
SkC
(eee Note C)
{1.3V
-+I j+I
~~~--
tpHZ -.!
::
l+I
O.SV
L-*--VOH
_
_
o~
utput
S1 Open
1.3 V
----.OV
2V
'" S1 Closed
-1.4V
Generator
(see Note A) 1--......(-see...J Note D)
500
TEST CIRCUIT
VOLTAGE WAVEFORMS
Figure 3. Test Circuit and Voltage Waveforms
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR =1 MHz, duty cycle
ZO=500.
B. CL includes probe and jig capacitance.
=50%, tr s 6 ns, tf S 6 ns,
C. All diodes are 1N916 or equivalent.
D. To test the active-low enable G, ground G and apply an inverted input waveform to G.
1ExAs.Jf
INSTRUMENTS
POST OFACE BOX 655303 • DAUAS. TEXAS 75265
2-561
SN75ALS173
QUAD DIFFERENTIAL LINE RECEIVER
Su.sl32B - 03886, SEPTEMBER 1991 - REVISED JANUARY 1993 '
PARAMETER MEASUREMENT INFORMATION
VCC
2kO
Input
SkO
!1.3V
I
I
(see Note C)
tpzL ~ 14-
I
S2 Open
\-:;:~-I
II.
-+j
I
I
3V
ov
r-
tPLZ
S2 Closed
-1.4V
1.3V
_oL_
~
2V
Output
Generator
( - Note A) 1---.-(_-' Note D)
-T-
VOL
O.SV
500
TEST CIRCUIT
VOLTAGE WAVEFORMS
Figure 4. Test Circuit and Voltage Waveforms
NOTES: A. The Input pulse Is supplied by a generator having the following characteristics: PRR
=I
ZO=50D.
B. CL Includes probe and jig capacftance.
C. All diodes are 1N916 or equivalent.
D. To lest the active-low enable G, ground G and apply an Inverted input waveform 10 G.
1ExAs . "
INSIRUMENTS
2-562
POST OFFICE BOX 655303 • DAUAS, TEXAS 75265
MHz, duty cycle
=50%, tr " 6 ns, If" 6 ns,
SN75174
QUAD DIFFERENTIAL LINE DRIVER
• Meets EIA Standards RS-422-A and RS-48S
and CCITT Recommendations V.11 and X.27
• Designed for Multipoint Transmission on
Long Bus Lines In Noisy Environments
• 3-state Outputs
• Common-Mode Output Voltage Range of
-7Vt012V
• Active-High Enable
• Thermal Shutdown Protection
• Positive- and Negative-Current limiting
• Operates From Single S-V Supply
• Low Power Requirements
• Functionally Interchangeable With MC3487
NPACKAGE
(TOP VIEW)
1A
1Y
1Z
1,2EN
Vee
4A
4Y
4Z
3,4EN
2Z
2Y
3Z
2A
3Y
7
GND
3A
OW PACKAGE
(TOP VIEW)
Vee
description
4A
The SN75174 is a monolithic quad differential line
driver with 3-state outputs. It is designed to meet
the requirements of EIA Standards RS-422-A and
RS-485 and cCln Recommendations V.11 and
X.27. The device is optimized for balanced
multipoint bus transmission at rates up to
4 megabaud. Each driver features wide positive
and negative common-mode output voltage
ranges making it suitable for party-line
applications in noisy environments.
1,2EN
2Z
NC
2Y
2A
GND
logic symbol t
The SN75174 is characterized for operation from
Q·C to 7Q·C.
2A
INPUT
H
L
X
ENABLE
H
H
L
1A
Z
H
L
Z
H
3A
,.
~
lEN
l>
1
3A
'\l
'\l
2
3
6
7
5
~N
l>
OUTPUTS
L
4
12
9
'\l
10
11
14
4A
15
1Y
1Z
2Y
2Z
~
'\l
13
Z
H = TTL high level, X = irrelevant,
L TTL low level,
Z high impedance (off)
=
=
1,2EN
3,4EN
Y
7
Ne - No Internal connection
The SN75174 provides positive- and negativecurrent limiting and thermal shutdown for
protection from line fault conditions on the
transmission bus line. Shutdown occurs at a
junction temperature of approximately 15Q·C.
This device offers optimum performance when
used with the SN75173 or SN75175 quadruple
differential line receivers.
FUNCTION TABLE
(each driver)
4Y
NC
4Z
3,4EN
3Z
NC
3Y
3Y
3Z
4Y
4Z
t This symbol is in accordance wtth ANSVIEEE Sid 91-984
and lEe Publication 617-12.
Copyright © 1993, Texas Instruments Incorporated
1ExAs ."
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2-563
SN75174
QUAD DIFFERENTIAL LINE DRIVER
SLLS039A- 02601, OCTOBER 191/0- REVISED FEBRUARY 1993 .
logic diagram, each driver (positive logic)
y
A----I
Z
EN
schematics of inputs and outputs
EQUIVALENT OF EACH INPUT
TYPICAL OF ALL OUTPUTS
---~~--- VCC
VCC
Req
Input
-+-+------1
. - - - - Output
-.--~~----- GND
Data Inputs: Req = 3 kQ NOM
Enable Inputs: Req = 8 kQ NOM
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage, Vee (see Note 1) ,.,., ..................... , .................................. 7 V
Input voltage, V, ...... , .. " ............................................. , ................. 5.5 V
Continuous total dissipation .... ,...................................... See Dissipation Rating Table
Operating free-air temperature range .................................................. O°C to 70°C
Storage temperature range ....................................................... -65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds ............................... 260°C
NOTE 1: All voltage values are with respect to the network ground terminal.
DISSIPATION RAnNG TABLE
PACKAGE
TA.,25·C
POWERRAnNG
DERATING FACTOR
ABOVE TA = 25·C
TA=70·C
POWER RATING
OW
1125mW
1150mW
9.0mwrc
9.2mwrc
720mW
N
1ExAs ..,
INSIRUMENTS
2-564
POST OFFICE BOX 655303 • DAUAS. TEXAS 75265
736mW
SN75174
QUAD DIFFERENTIAL LINE DRIVER
SLLS039A- 02601, OCTOBER 1980- REVISED FEBRUARY 1993
recommended, operating conditions
Supply voltage, VCC
MIN
NOM
MAX
4,75
5
5.25
High-level input voltage, VIH
V
V
2
Low-level input vottage, VIL
Common-mode output vollage, VOC
UNIT
0.8
V
-7 to 12
V
High-level output current, 10H
-60
mA
Low-level output current, 10L
60
mA
Operating free-air temperature, TA
70
·C
°
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Input clamp voltage
11=-18mA
VOH
High-level output vottage
VIH =2V,
10H =-33mA
VIL=0.8V,
VOL
Low-level output voltage
VIH=2V,
IOL=33mA
VIL=0.8V,
Vo
Output vottage
10=0
IV OD11
Differential output voltage
10=0
VIK
IV OD21
Differential output vollage
VOD3
Differential output voltage
~IVODI
Change in magn~ude of differential
output voltage:!:
VOC
Common-mode output vottageli
~lVocl
Change in magnitude of common-mode
output voltage:!:
MIN
°
1.5
RL=1oo0,
See Figure 1
RL=540,
See Figure 1
See Note 2
TYpt
UNIT
-1.5
V
3.7
V
1.1
V
6
6
V
6
V
1/2VOD1
or2i
1.5
V
2.5
1.5
RL=540or1000,
MAX
See Figure 1
5
V
5
V
",0.2
V
+3
-1
V
",0.2
V
",100
f,IA
",100
f,IA
10
Output current with power off
VCC=O,
10Z
High-impedance-state output current
VO=-7Vt012V
IIH
High-level input current
VI =2.7V
20
f,IA
IlL
LOW-level input current
VI =0.5V
-360
f,IA
VO=-7V
-180
lOS
Short-circu~
ICC
output current
Supply current (all drivers)
VO=-7Vt012V
VO= VCC
180
VO= 12V
500
No load
I Outputs enabled
I Outputs disabled
38
60
18
40
,mA
mA
t All typical values are at Vee = 5 V and TA = 25·C.
:!: ~IVODI and ~IVocl are the changes in magnitude ofVOD and VOC, respectively, that occur when the input is changed from a high level to a low
level.
.
§ The minimum VOD2 with a 100-0 load is either 1/2 VOD1 or 2 V, whichever is greater.
NOTE 2: See Figure 3.5 of EIA Standard RS-485.
1ExAs ."
INSIRUMENfS
POST OFFICE BOX 655303 • DALlAS, TEXAS 75265
2-565
SN75174
QUAD DIFFERENTIAL LINE DRIVER
SI..LS039A- D2601. OCTOBER 1980 - REVISED FEBRUARY 1993
switching characteristics, VCC
= 5 V, TA = 25°C
PARAMETER
tdD
Dlfferential-outp!ll delay time
ttD
Differential-output transition time
tpZH
TEST CONDITIONS
MIN
TYP
MAX
45
65
UNIT
ns
80
120
ns
RL=540.
See Figure 2
Output enable time to high level
RL=1100.
See Figure 3
80
120
ns
tPZL
Output enable time to low level
RL=1100.
See Figure 4
55
80
ns
tpHZ
Output disable 'time from high level
RL=1100.
See Figure 3
75
115
ns
tpLZ
Output disable time from low level
RL= 1100.
See Figure 3
18
30
ns
SYMBOL EQUIVALENTS
DATA SHEET PARAMETER
R8-422-A
RS-485
Vo
VOa• Vob
Voa.Vob
IV OD11
VO
VO
IV OD21
VdRL= 1000)
Vt (RL= 54 0)
Vt (Test Termination)
Measurement 2)
IV OD31
AiVoDI
IIVIi-IVIiI
VOC
IVosl
IIVtI-IVtll
IVosl
AiVocl
IVos-Vosl
IVos-Vosl
lOS
Iisal.llsbi
10
Ilxal.llxbl
Ila.lib
PARAMETER MEASUREMENT INFORMATION
Figure 1. Differential and Common-Mode Output Voltages
---3V
~
Input
Generator
(see Note A)
..r,.
I . -_ _ _
1.5V
1.5V
I
I,
I
~
!do ,.-,
SOO
r
90%
~I··
OV
!do
~
50%
I
I
3V
Output
I
_I
TEST CIRCUIT
Ito
I
T---2.5V
I
10%
~
. I
1-
i-t-
_
2.5 V
ttO
VOLTAGE WAVEFORMS
NOTES: A. The Input pulse is supplied by a generator having the following characteristics: tr '" 5 ns. tf '" 5 ns. PRR '" 1 MHz. duty cycle = 50%.
ZQ=500.
B. CL includes probe and stray capacitance.
Figure 2. Differential-Output Test Circuit and Voltage Waveforms
1ExAs . "
INSIRUMENTS
2--566
POST OFFICE BOX SS5303 • DAUAS. TEXAS 75265
SN75174
QUAD DIFFERENTIAL LINE DRIVER
SLLS039A- 02601, OCTOBER 1980 - REVISED FEBRUARY 1993
PARAMETER MEASUREMENT INFORMATION
Input
3VtoOV
Generator
(eeeNoteA)
1
I
L _____1CL =50 pF
RL=110g
~
·~tpZH
I
I
I
I
OV
O.S V
~
-=
(see Note B)
50 g
~~~---3V
--J': .'~;
"'o-_~~- Output
Output
2.3V
-.:t-VOH
I -t-I
~
Voff -OV
tpHZ~
TEST CIRCUIT
VOLTAGE WAVEFORMS
Figure 3. Test Circuit and Voltage Waveforms
SV
RL= 110g
OVto3V
Generator
(eee Note A)
50 g
Input
1
Output
I
L- - - - -
=
T
B1
CL 50 pF
(see Note
~.SV
\
----"! .
tpZL:
~
--~
Output
0V
I
.,
~
I
\.3 V
.
TEST CIRCUIT
!.~V--- 3V
i\
tpLZ SV
~
--t-
VOL
VOLTAGE WAVEFORMS
Figure 4. Test Circuit and Voltage Waveforms
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR " 1 MHz, duty cycle
ZO=50n
B. CL includes probe and stray capacitance.
=50%, tr" 5 ns, tf" 5 ns,
1ExAs " ,
INSIRUMENTS
POST OFFICE BOX 655303 • DAUAS. TEXAS 75265
2-567
SN75174
QUAD DIFFERENTIAL LINE DRIVER
Su.s039A- 02601, OCTOBER 1980- REVISED FEBRUARY 1993
TYPICAL CHARACTERISTICS
HIGH-LEVEL OUTPUT VOLTAGE
LOW-LEVEL OUTPUT VOLTAGE
vs
va
HIGH-LEVEL OUTPUT CURRENT
LOW-LEVEL OUTPUT CURRENT
5
6
VCC=5V
TA=25°C -
4.5
>I
j
3.6
'S
3
!
0
!
j
:I:
r--. r--
4
VCC!5V
TA 25°C
4.5
>
•
=
4
I
I
all
~
............
2.5
i
3.5
0
2.5
~~
2
1
'S
.........
2
1.5
.3
I
3
I
I
1.S
oJ
:I:
oJ'
.p
0.5
o
"".
-20
-40
-60
-80
-100
".-
0.5
o
o
-120
o
40
20
10H - High-Level Output Current - rnA
all
I
i
0
ii
I
~
.......
3
vs
OUTPUT CURRENT
OUTPUT VOLTAGE
,
"'" i'-
......
2
,
C
~;:,
......
0
'S
!0
I
.9
\
0.6
I
f-
I
I
20
30 40 50 60 70 80
10 - Output Current - rnA
10
,\VCC=OV
0
-10
-20
) ".
~r-- VCC =5V
J
-40
90
-50
-25 -20 -15 -10 -S
0
5
10
Vo - Output Voltage - V
Figure 7
Figure 8
TEXAS ."
2~68
I
Output Disabled
TA=25°C
20
-30
\
10
40
c(
::!.
I
"\
1.5
o
120
30
2.5
o
50
I
I
I
VCC=SV
TA=25°C -
C
I
~
100
OUTPUT CURRENT
va
4
3.5
80
Figure 6
DIFFERENTIAL OUTPUT VOLTAGE
•
60
IOL - Low·Level Output Current - mA
Figures
>I
../
~
I
I
INSIRUMENTS
POST OFFICE BOX 65~03 • DAu.AS. TEXAS 75265
15
20
25
SN75174
QUAD DIFFERENTIAL LINE DRIVER
SU.8039A- 02601, OCTOBER 1980 - REVISED FEBRUARY 1993
TYPICAL CHARACTERISTICS
SUPPLY CURRENT
SUPPLY CURRENT
vs
vs
SUPPLY VOLTAGE
SUPPLY VOLTAGE
30
100
II
I
NoLoad
Outputs Enablad
80 I- TA=25°e
90
c(
E
I
70
!
60
u
~
Q.
25 c(
E
40
I
U
30
~
A,
E
20
10
o
I
~
Inputa opan~
50
::I
III
l
r-
o
---
~
l/
~
~
~
/
20
::I
U
>'ii.
Q.
::I
III
Inputs
I
15
/
10
E
5
7
o
8
/
/
,
/
V
/"
U
Grounded
3
4
5
6
Vee - Supply Voltage - V
2
1it:
I
NJLoad
Input Open
Output Dlaabled
TA=25°e
o
/
2
3
4
5
6
7
8
Vee - Supply Voltage - V
Figure 10
Figure 9
APPLICATION INFORMATION
1/4SN76173
Upto 32
Driver/Receiver Paira
1/4SN75175
• • •
1/4SN75172
1/4 SN75173
1/4SN75173
1/4SN75174
NOTE: The line length should be terminated at both ends in its characteristic impedance. Stub lengths off the main line should be kept as short
as possible.
Figure 11. Typical Application Circuit
TEXAS ~
INSlRl.JMENTS
POST OFFICE BOX 655303 • DAU..AS. TEXAS 75265
2-569
2-570
SN65ALS174A,SN75ALS174A
QUAD DIFFERENTIAL LINE DRIVERS
JULY 1991 - REVISED MARCH 1993
SLLS122B-
• Meets EIA Standards RS-422-A and RS-485
• Meets CCITT Recommendations V.11
andX.27
• High-Speed Advanced Low-Power Schottky
Circuitry
SN75ALS17~ ••• N PACKAGE
(TOP VIEW)
1A
1Y
1Z
1,2EN
2Z
• Designed for 2o-MBaud Operation In Both
Serial and Parallel Applications
• Designed for Multipoint Transmission on
Long Bus Lines In Noisy Environments
• Low Supply Current Requirements
55mAMax
• Wide Positive and Negative Input/Output
Bus Voltages Ranges
• Driver Output Capacity ••• ±60 mA
• Thermal Shutdown Protection
• Driver Positive and Negative Current
Limiting
Vee
4A
4Y
4Z
3,4EN
3Z
3
ow PACKAGE
SN65ALS174A, SN75ALS174A •••
(TOP VIEW)
NC
1A
• Functionally Interchangeable With SN75174
Vee
Vcc
4A
4Y
4Z
3,4EN
3Z
3Y
3A
NC
1,2EN
2Z
description
2Y
2A
GND
GND
The SN65ALS174A and SN75ALS174A are quad
line drivers with 3-state differential outputs. They
are designed to meet the requirements of EIA
Standards RS-422-A and RS-485 and CCITT
RecommendationsV.11 andX.27. These devices
are optimized for balanced multipoint bus
transmission at rates of up to 20 Mbaud. Each
driver features wide positive and negative
common-mode output voltage ranges making
them suitable for party-line applications in noisy
environments.
6
9
NC-No internal connection
FUNCTION TABLE
(each driver)
INPUT
A
H
L
The SN65ALS174A and SN75ALS174A provide
positive- and negative-current limiting and thermal
shutdown for protection from line fault conditions
on the transmission bus line. Shutdown occurs at
a junction temperature of approximately 150°C.
X
ENABLES
H
H
L
H =high level. L =low level,
Z = high impedance (off)
OUTPUTS
Y
Z
H
L
Z
X
L
H
Z
=irrelevant,
The SN65ALS174A is characterized for operation
from -40°C to 85°C and the SN75ALS174A is
characterized for operation from O°C to 70°C.
1ExAs
..If
INSIRUMENTS
POST OFFICE BOX 655303 • DALlAS. TEXAS 75285
Copyright © 1993, Texas Instruments Incorporated
2-571
SN65ALS174A, SN75ALS17.4A
QUAD DIFFERENTIAL LINE DRIVERS
SLLSl228 - 03865, JULY 1991 - REVIseD MARCH 1993
logic diagram (positive logic)
logic symbol t
1,2EN
1,2EN
2
1Y
1A
3
1A
1Z
~
2A
6
2Z
5
2A
1Y
1Z
~
2Z
3,4EN
3,4EN
:w
3A
10
3Z
4Y
4A
11
3A
14
4Z
13
4A
t This symbol is in accordance with ANSI/iEEE Std 91-1984 and
lEe Publication 617-12.
Pin numbers shown are for the N package.
schematics of inputs and outputs
EQUIVALENT OF EACH INPUT
TYPICAL OF ALL OUTPUTS
----..--- Vce
vCC--~~
35 kO NOM
Input
Output
GND
~~
INSIRUMENTS
2-572
POST OFFICE BOX 85S303 • DAUAS, TEXAS 75265
3Y
3Z
4Y
4Z
SN65ALS174A,SN75ALS174A
QUAD DIFFERENTIAL LINE DRIVERS
SlJ..Sl22B - 03865. JULY 1991 - REVISED MARCH 1993
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) ............................................................. 7 V
Input voltage, VI ............................................................................ 7 V
Output voltage range, Vo ........................................................... -9 V to 14 V
Continuous total dissipation ........................................... See Dissipation Rating Table
Operating free-air temperature range: SN65ALS174A ................................ -40°C to 85°C
SN75ALS174A .................................. OOG to 700G
Storage temperature range ....................................................... -65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds ............................... 260°C
NOTE 1: All voltage values are with respect to network ground terminal.
DISSIPATION RATING TABLE
DERATING
FACTOR
TA = 7O·C
POWER RATING
TA = as·c
POWER RATING
1125mW
9mWrC
720mW
585mW
1150mW
9.2mwrC
736mW
598mW
PACKAGE
TA s 25·C
POWER RATING
OW
N
recommended operating conditions
Supply voltage, Vee
High-level input vo~age, VIH
MIN
NOM
MAX
UNIT
4.75
5
5.25
V
V
2
Low-level input VOltage, VIL
0.8
V
Common-mode output voltage, VOC
12
-7
V
-60
mA
60
mA
High-level output current, IOH
Low-level output current. IOL
Operating free-air temperature, TA
L
I
SN65ALS174A
-40
85
SN75ALS174A
0
70
·C
1ExAs ."
INSIRUMENIS
POST OFFICE BOX 655303 • DALlAS. TEXAS 75265
2-673
SN65ALS174A, SN75ALS174A
QUAD· DIFFERENTIAL LINE DRIVERS
SLLSl22B - D3865, JULY 1991- REVISED MARCH 1993
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VIK
Input clamp voltage
11--18mA
Va
Output voltage
10=0
I V ODll
Differential output voltage
10=0
RL= 1000
Differential output voltage
I V OD21
I V OD31
Differential output voltage
61 V ODI
Change In magnitude of
differential output voltage:l:
VOC
Common-mode output voltage§
61 V oci
See Figure 1
TYPT
MIN
MAX
UNIT
1.5
V
0
6
V
1.5
6
V
1/2VODl
or 2'11
V
2.5
1.5
RL=540
See Note 2
1.5
5
5
V
",0.2
V
3
-1
V
Change in magnitude of
common-mode output voltage:!:
",0.2
V
10
Output current with power off
VCC=O,
",100
10Z
High-Impedance-state output current
VO= -7Vto 12V
IIH
High-level input current
VI =2.7V
20
IlL
low-level Input current
VI =0.4V
-100
IlA
IlA
IlA
IlA
lOS
Short-circuit output current
VO= -7Vto 12V
",250
mA
ICC
RL = 54
Supply current (all drivers)
°or 100 0,
See Figure 1
VO= -7Vto12V
No load
",100
Outputs enabled
36,
55
I Outputs disabled
16
30
mA
t All typical vatues are at VCC = 5 V and TA = 25·C.
:I: 61 VODI and 61 VOC I are the changes in magnitude of VOD and VOC respectively, that occur when the input is changed from a high level to
a low level.
§ In EIA Standard RS-422-A, VOC, which is the average of the two output voltages with respect to ground, is called output offset voltage, Vas.
'liThe minimum VOD2with a 100-0 load is either 1/2VODl or 2 V whichever Is greater.
NOTE 2: See EIA Standard RS-4B5, Figure 3-5, Test Termination Measurement 2.
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, CL 50 pF
=
MIN
TYPT
MAX
IdD
tpZH
Differential-output delay time
RL=540,
See Figure 2
9
15
22
ns
Output enable time to high level
RL= 1100,
See Figure 3
30
45
70
ns
PARAMETER
TEST CONDITIONS
UNIT
tpZL
Output enable time to low level
RL=110Q,
See Figure 4
25
40
65
ns
tpHZ
Output disable time from high level
RL=1100,
See Figure 3
10
20
35
ns
tpLZ
Output disable time from low level
RL=1100,
See Figure 4
10
30
45
ns
t All typical values are at VCC = 5 V and TA = 25·C.
1ExAs..lf
INSIRUMENTS
2-574
POST OFFICE BOX 655303 • DALlAS, TEXAS 75265
SN65ALS174A,SN75ALS174A
QUAD DIFFERENTIAL LINE DRIVERS
SLLSl22B - 03865, JULY 1991 - REVISED MARCH 1993
PARAMETER MEASUREMENT INFORMATION
RL
VOC
1
2
Figure 1. Differential and Common-Mode Output Voltages
r - - -..........>---,..- y
Generator
(see Note A)
Input
3V - - - _ - - - - - ' ' \ .
1.SV
o
RL=
540
500
' - - _..........>--_...J.... Z
3V
T"::"
CL=50pF
(see Note B)
I
-.I
i+- tdOH
1.SV
I
--'
~ 1dOL
OutPutZ~----------~
OutputY
TEST CIRCUIT
VOLTAGE WAVEFORMS
NOTES: A. The input pulse Is supplied by a generator having the following characteristics: PRR
t r ",5 ns.
B. CL includes probe and stray capac Hance.
=1 MHz, Zo =50 0, duty cycle =50%, tf" 5 ns,
Figure 2. Differential-output Test Circuit and Voltage Waveforms Delay and Transition Times
1ExAs
..If
INSIRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2-575
SN65ALS174A, SN'75ALS174A
QUAD DIFFERENTIAL LINE DRIVERS
SL.LS122B - 03865, JULY 1991 - REVISED MARCH 1993
PARAMETER MEASUREMENT INFORMATION
~
OVor3V
Generator
(saeNotaA)
Output
i
I·
CL=50pF
(sea Note B)
500
'i~~--
Input-4'1.s V
3V
OV
I
RL=
1100
14-
-+I
Output
tpZH
J4.3V
":"
I
I
I
I
I
O.sv
-*K!~
tPHZ-+I
TEST CIRCUIT
VOH
Voff- O
VOLTAGE WAVEFORMS
Figure 3. Test Circuit and Voltage Waveforms, tPZH and tpHZ
5V
RL=
1100
51
Generator
(saeNoteA)
I
I1.,; _ _ _ _ _
CL=50pF
(sea
Note B)
Output
~;:-5~---
Inp~1.sv
tpZL
I
Output
~
3V
OV
~I
I
I
i+-+I--
~~V
tPLZ
I
ta-,-
sV
VOL
O.SV
TEST CIRCUIT
VOLTAGE WAVEFORMS
Figure 4. Test Circuit and Voltage Waveforms, tpZL and tpLZ
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR = 1 MHz, Zo = 50 0, duty cycle = 50%, tf" 5 ns,
trs 5 ns.
B. CL Includes probe and stray capacitance.
TEXAS
2-576
,If
INSIRUMENfS
. POST OFFICE BOX 655303 • DAUAS, TEXAS 75265
SN65175, SN75175
QUAD DIFFERENTIAL LINE RECEIVERS
OCTOBER 1990 - REVISED FEBRUARY 1993
• Meets EIA Standards RS-422-A, RS-423-A,
and RS-485
D OR N PACKAGE
(TOP VIEW)
• Meets CCITT Recommendations V.10, V.11,
)(,26, and )(,27
1B
1
4A
4Y
• 3-State Outputs
• Common-Mode Input Voltage Range
-12Vto 12V
2B
GND
• Input Sensitivity ..• :1:200 mV
• Input Hysteresis .•• 50 mV Typ
3,4EN
3Y
3A
8
FUNCTION TABLE
(each receiver)
• High Input Impedance ••• 12 kQ Min
• Operates From Single 5-V Supply
DIFFERENTIAL INPUTS
A-B
• Low-Power Requirements
VIO",O.2V
-O.2V
3
V
6
7
"
2Y
~
~N
~
]
Jrt>
3
1B
2A
10
5
2B
11
V
1Y
2Y
3Y
3,4EN
14
15
1Y
1A
5
12
9
1,2EN
13
"
4Y
3A
tThls symbol is in accordancewilh ANSI/IEEE Sid 91-1984
and IEC Publication 617-12.
11
3Y
3B
4A
4B
13
4Y
schematics of inputs and outputs
EQUIVALENT OF EACH A OR B INPUT
VCC-----~.---~._
16.8krl
NOM
EQUIVALENT OF EACH ENABLE INPUT
VCC
VCC
Input
Input ----'VI/\,....---e
Output
1ExAs ."
. INSIRUMENTS
2--578
TYPICAL OF ALL OUTPUTS
POST OFFICE BOX 655303 • DAUAS, TEXAS 75265
SN65175, SN75175
QUAD DIFFERENTIAL LINE RECEIVERS
SLLS145A- D2602, OCTOBER 1990 - REVISED FEBRUARY 1993
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) ............................................................. 7 V
Input voltage, A or B inputs ................................................................ :t:25 V
Differential input voltage (see Note 2) ....................................................... :t:25 V
Enable input voltage ......................................................................... 7 V
Low-level output current .................................................................. 50 rnA
Continuous total dissipation ........................................... See Dissipation Rating Table
Operating free-air temperature range, TA: SN65175 .................................. -40°C to 85°C
SN75175 .................................... O°C to 70°C
Storage temperature range ....................................................... -65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds .............................. -260°C
NOTES: 1. All voHage values, except differential input voHage, are with respect to network ground terminal.
2. Differential-input voHage Is measured at the noninverting input with respect to the corresponding inverting input.
DISSIPATION RATING TABLE
PACKAGE
TAs25°C
POWER RATING
DERATING
FACTOR
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
D
950mW
7.6mW/"C
608mW
494mW
N
1150mW
9.2mW/"C
736mW
598mW
recommended operating conditions
MIN
NOM
MAX
UNIT
4.75
5
5.25
V
Common-mode input voHage, VIC
",12
V
Differential input voHage, VID
",12
V
Supply voHage, VCC
High-level enable-input voHage, VIH
2
Low-level enable-input voHage, VIL
V
0.8
High-level output current, IOH
Low-level output current, IOL
I SN65175
Operating free-air temperature, TA
I
SN75175
V
-400
!lA
16
rnA
-40
85
0
70
°C
1ExAs ..,
INSIRUMENTS
POST OFFICE BOX 655303 • DAllAS, TEXAS 75265
2-579
SN65175, SN75175
QUAD DIFFERENTIAL LINE RECEIVERS
SUS145A- D2602, OCTOBER 1990- REVISED FEBRUARY 1993
electrical characteristics over recommended ranges of common-mode input voltage, supply
voltage and operating free-air temperature
PARAMETER
TEST CONDITIONS
"1"+
"1"-
P08ltlve-golng Input threshold voltage
VO= 2.7V,
10=-0.4mA
Negative-going Input threshold voltage
VO= 0.5 V,
10=16mA
VI1Ys
See Figure 4
VIK
Hysteresis (Vr+- "1"-J
Enable-input clamp voltage
VOH
High-level output voltage
Vlo=200mV,
MIN
TYpt
MAX
0.2
mV
50
-1.5
11=-18mA
VOL
Low-level output voltage
VIO = -200 mV,
10Z
Hlgh-impedance-state output current
Vo = 0.4 Vto 2.4 V
See Figure 1
See Figure 1
2.7
V
V
IIOL=8mA
0.45
IIOL=16mA
0.5
",20
IVI = 12V
1
IVI =-7V
-0.8
II
Une Input current
Other Input at 0 V,
IIH
High-level enable-Input current
VIH=2.7V
20
IlL
Low-level enable-input current
VIL=0.4V
-100
q
Input resistance
See Note 3
V
V
-0.2*
10H = -400 ,.A,
UNIT
12
V
,.A
mA
,.A
,.A
kQ
Short-cIrcuit output current§
-15
-85
mA
lOS
Supply current
Outputs disabled
70
mA
ICC
t All typical values are at VCC = 5 V, TA = 25°C.
* The algebraic convention, In which the less positive (more negative) limit is designated as minimum, is used in this data sheat for threshold voltage
levels only.
§ Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second.
NOTE 3: Refer to EIA Standards RS-422A, RS423-A, and RS-485 for exact conditions.
switching characteristics, Vee
=5 V, CL =15 pF, TA =25°e
PARAMETER
TEST CONDITIONS
tpLH
Propagation delay time, low-to-hlgh-Ievel output
tPHL
Propagation delay time, high-to-low-Ievel output
tPZH
Output enable time to high level
tpZL
Output enable time to low level
tpHZ
Output disable time from high level
tpLZ
Output disable time from low level
See Figure 2
See Figure 3
See Figure 3
1ExAs
2-580
,If
INSIRUMENTS
POST OFFICE BOX 65S303 • OAUAS. TEXAS 75265
MIN
TYP
MAX
22
35
UNIT
ns
25
35
ns
13
30
ns
19
30
ns
26
35
ns
25
35
ns
SN65175, SN75175
QUAD DIFFERENTIAL LINE RECEIVERS
SLlS145A- D2602, OCTOBER 1990 - REVISED FEBRUARY 199C3
PARAMETER MEASUREMENT INFORMATION
Figure 1. VOH. VOL
Generator
(saeNoteA)
~~;--
InpLrt - - J U V
tpLH ~
-l4--+I
r---.
. . . +-vi
tpHL
I
OLrtpLrt
TEST CIRCUIT
1.3
::
VOH
1.3 V " - VOL
VOLTAGE WAVEFORMS
Figure 2. Test Circuit and Voltage Waveforms
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR s 1 MHz, duty cycle
Zo = 50 C.
B. CL includes probe and stray capacitance.
=50%, tr s 6 ns, tf s 6 ns,
1ExAs " ,
INSIRUMENTS
POST OFACE BOX 655303 • DAUAS, TEXAS 75265
2-581
SN65175, SN75175
QUAD DIFFERENTIAL LINE RECEIVERS
SLLS145A- 02602, OCTOBER 1990- REVISED FEBRUARY 1993
PARAMETER MEASUREMENT INFORMATION
Output
2kO
SW2
....---+-__--.------II\II,---------~
5V
(see Note C) ,
TEST CIRCUIT
Input
"
.r.-:;;-
~~5~_
+--1_..
tp
Output
~
ZH
---r-j
J/.;;v
'-----L. '::"-
3V "
Input
3V
.r.-:;;-
~~5~_
+--- OV SW1 to-1,5V
tPZL ~
SW2 Closed
I +
SW30pen
~-:p-4.5V
OV
SW1to1,5V
SW2 Open
VOH
Closed
sm
OutPut~
0V
tpZL
tPZH
Input
~
1,5V
I
r--r-
L _.
Output
~V
VOL
----
tpHZ
0.5 V
~
3V~.p.,
3V
Input
OV SW1 to1.5V
SW2 Closed
SW3 Closed
VOH
---1.4V
~3V
~ __ _
I
tpLZ ~
I
----
OV
I
~--1.4V
Output ~ 0.5V
SW1 to-1.5V
SW2 Closed
SW3 Closed
'VOL
VOLTAGE WAVEFORMS
Figure 3. Test Circuit and Voltage Waveforms
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR s 1 MHz, duty cycle = 50%, tf s 6 ns, tr s 6 ns,
ZO=50D.
B. CL includes probe and stray capacitance.
C. All diodes are 1N916 or equivalent.
2-582
POST OFFICE SOX 655303 • DALlAS. TEXAS 75265
SN65175, SN75175
QUAD DIFFERENTIAL LINE RECEIVERS
SLlS145A- 02602, OCTOBER 1990- REVISED FEBRUARY 1993
TYPICAL CHARACTERISTICS
HIGH-LEVEL OUTPUT VOLTAGE
OUTPUT VOLTAGE
va
vs
DifFERENTIAL INPUT VOLTAGE
HIGH-LEVEL OUTPUT CURRENT
5
VCC=5V
10=0
5
TA=25 DC
4.5
>
.
I
I
VIC =
-12V
3.5
CIt
!
~
!i
Go
!i
0
,.
>
4
I
I
3
VIC =
VIC =
1- 12V 0
VT-
VT-
r--
~
!i
I
!
0
VT-
2.5
Vr+
2
VT+
]
VT+
CIt
1.5
:i:
3.5 ~
~~
VCC=5.25V
~ ~ ""/ I I
VCC=5V
~~ 7
~~
3
2.5
2
1.5
I
:z:
r--
.p
0.5
0.5
o
o
-125 -100 -75 -50 -25 0 25 50 75 100 125
VIO - Oifferentlallnput VoHage - mV
VIO=0.2V
TA=25DC
4
.c
I
.p
r-
4.5
~
VCC=4.75V
1 "I
~~
o
-5 -10 -15 -~ -25 -~ -35 -@ -45-50
10H - High-Level Output Current - mA
FigureS
Figure 4
HIGH-LEVEL OUTPUT VOLTAGE
5
>
.
I
~
!i
Go
!i
vs
FREE-AIR TEMPERATURE
LOW-LEVEL OUTPUT CURRENT
VCC=~V
~
I
0.5 -
.
I
I
VCC=5V
TA=25 DC
vIO=-0.2V
CIt
!
0.4
0
0.3
5
0.2
~
!i
Go
!i
SN651Vs"onIY -
3
2
>
-4 -
3.5
2.5
~
0.6
I
4.5 - VIO=0.2V
IOH = -400 IlA
4
0
:z:
I
:z:
LOW-LEVEL OUTPUT VOLTAGE
va
aI
!
1
~~
~~
~
1.5
/
/
/
/
V
./
/'
,/
I
oJ
.p
.p
0.1
0.5
o
o w
o
~
~
@
50 ~ ~
TA - Free-Alr Temperature - DC
~
~
o
5
10
15
~
25
~
10L - Low-Level Output Current - mA
Figure 6
Figure 7
1ExAs
..If
INSIRUMENTS
POST OFACE BOX 656303 • DAUAS. TEXAS 75265
2-583
SN65175, SN75175
QUAD DIFFERENTIAL LINE RECEIVERS
Su.sl45A-
D2602. OCTOBER 1990- REVISED FEBRUARY 1993
TYPICAL CHARACTERISTICS
OUTPUT VOLTAGE
LOW-LEVEL OUTPUT VOLTAGE
0.5
>I
j
i
o
I
va
va
FREE-AIR TEMPERATURE
ENABLE VOLTAGE
5
VC~=5V
VIO=0.2V
Load = 8 kg to GNO
TA = 25"C
VIO=-O.2V
IOL=8mA
0.4
0.3
V
i
.
~
io
SN65175 Only
0.2
~
7
/'
3
Vee = 4.75 V
VCC=5V -
2
~
0.1
o
1
o
o ro
~
~
~
~
~
~
~
~
o
0.5
1.5
2
Enable G Voltage - V
TA - Free-Air Temperature - °e
va
va
ENABLE VOLTAGE
SUPPLY VOLTAGE
.!
I
Vce .. 5•25V
5
100
I
I
VIO=-o·2V
Load = 1 kg to Vee
~
TA=jOC
~
'E"
Vec=4.75V
' - Vce=5V
I
~
C
~
::I
~
CJ
t
Q.
::I
III
I
CJ
CJ
f-
N~Loadl
InputaOpen
f- TA=25°C
h
~
~
t?
~
10
o
0.5
1.5
2
Enable G Voltage - V
2.5
/
Outputs OISBbied
;
~
o
3
SUPPLY CURRENT (ALL RECEIVERS)
OUTPUT VOLTAGE
6
2.5
Figure 9
FigureS
3
V/
/. V
~Outputs Enabled -
},'1
..
~~
2
3
456
Vee - Supply Voltage - V
Figure 11
Figure 10
2-584
-
I
I
..J
1-Vee = 5.25
1 V
4
>I
1ExAs'"
INSIRUMENTS
POST OFFICE BOX 855303 • DAUAS. TEXAS 75265
7
8
SN65175, SN75175
QUAD DIFFERENTIAL LINE RECEIVERS
SLLS145A- 02602, OCTOBER 1990 - REVISED FEBRUARY 1993
TYPICAL CHARACTERISTICS
INPUT CURRENT
va
INPUT VOLTAGE
0.75
c(
0.5
E
!
0.25
d
0
I
!5
Q.
.5 - 0.25 1---+--+--::;""",,"-+--..,
I
- 0.5 l---oo'F--+----:
-0.75
-6 -4 -2
0
2
4
6
8
10
12
VI -Input Voltage - V
Figure 12
APPLICATION INFORMATION
1/4SN75172
1/4 SN75174
1/4SN65173
1/4SN75173
1/4SN65175
1/4SN75175
1/4 SN75172
1/4 SN65173
1/4SN75173
1/4 SN65173
1/4SN75173
1/4 SN75174
Figure 13. 'TYpical Application Circuit
NOTE: The line should be tenninated at both ends in its characteristic impedance. Stub lengths off the main line should be kept as short as
possible.
1ExAs
.Jf
INSIRUMENIS
POST OFFICE BOX 655303 • DAUAS. TEXAS 75265
2-585
2-586
SN75ALS175
QUAD DIFFERENTIAL LINE RECEIVER
SLLS131B-
•
Meets EIA Standards RS-422-A, RS-423-A,
and RS-485
•
Meets CCITT Recommendations V.10, V.11,
)(,26, and )(,27
•
Designed for Multipoint Bus Transmission
on Long Bus Lines In Noisy Environments
•
Low Supply Current Requirement
27 mA Max
•
Common-Mode Input Voltage Range of
-12Vto 12V
•
•
•
•
Input Sensitivity ••• :t:200 mV
SEPlEMBER 1991 - REVISED JANUARY 1993
N OR NSt PACKAGE
(TOP VIEW)
18
1A
VCC
48
4A
1,2EN
2Y
4Y
3,4EN
3Y
2A
3A
38
t The NS package is only available left-ende taped and reeled
(order device SN75ALS175NSLE).
Input Hysteresis ••• 50 mV Typ
FUNCTION TABLE (EACH RECEIVER)
High Input Impedance ••• 12 kQ Min
DIFFERENTIAL INPUTS
A-B
ENABLE
EN
OUTPUT
Y
VID,,0.2V
H
H
H
L
H
H
Operates From Single SOV Supply
-0.2V< VID< 0.2 V
description
VID" -0.2 V
X
The SN75ALS175 is a monolithic quadruple
differential line receiver with 3-state outputs. It is
designed to meet the requirements of EIA
Standards RS-422-A, RS-423-A, and RS-485 and
several celn recommendations. Advanced
low-power Schottky technology provides high
speed without the usual power penalty. Each of
the two pairs of receivers has a common
active-high enable. The device features high input
impedance, input hysteresis for increased noise
immunity, and input sensitivity of :t:200 mVover a
common-mode input voltage range of -12 V to
12V.
The SN75ALS175 is characterized for operation
from ooe to 70·e.
Open CircuH
=
?
L
Z
H
=
H =high level. L low level, ? indeterminate;
X irrelevant, Z = high impedance (oft)
=
logic symbol:J:
1,2EN
1A
1B
2A
2B
3,4EN
4
1
"-
3B
4A
4B
]
.ITt>
3
"V
6
7
5
"-
12
~N
10
3A
,J
~N
2
9
"-
14
15
]
2Y
.-J
.ITt>
11
"V
13
"
1Y
3Y
4Y
:I: This symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
Copyright © 1993. Texas Instruments Incorporated
1ExAs ."
INSIRUMENrS
POST OFFICE
eox 655303 •
DALlAS. TEXAS 75265
2-587
SN75ALS175
QUAD DIFFERENTIAL LINE RECEIVER
SLLS131 B -;- 03910. SEPTEMBER 1991 - REVISED JANUARY 1993
logic diagram (positive logic)
1,2EN
3
1A
1B
2A
5
~--
1Y
2Y
2B
3,4EN
3A
3B
4A
4B
11
>--+-13
>---
3Y
4Y
schematics of inputs and outputs
EaUIVALANT OF EACH A OR B INPUT
VCC--------~~-----e-
17kC
NOM
Input -
1.7kC
NOM
EaUIVALANT OF EACH ENABLE INPUT
VCC
-------
TYPICAL OF ALL OUTPUTS
- - - . _ - VCC
EN
Input
....-'l/Vv-~
Output
288kC
NOM
Vcc(A)
or
GND(B)
GND - ....--e-..-~....
---......-+-
GND----~~-.---.-
1ExAs
~
INSTRUMENTS
2--5B8
POST OFFICE BOX 655303 • DAUAS. TEXAS 75265
GND
SN75ALS175
QUAD DIFFERENTIAL LINE RECEIVER
Su..s131B-D3910, SEPTEMBER 1991-REVlSEDJANUARY 1993
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) ............................................................. 7 V
Input voltage, A or B inputs .....................................•.......................... ± 14 V
Differential input voltage (see Note 2) ....................................................... ± 14 V
Enable input voltage ......................................................................... 7 V
Low-level output current .................................................................. 50 mA
Continuous total dissipation ........................................... See Dissipation Rating Table
Operating free-air temperature range, TA .............................................. O°C to 70°C
Storage temperature range ....................................................... -65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds ............................... 260°C
NOTES: 1. All voltage values, except differential input voltage, are wHh respect to network ground terminal.
2. Differential-input voltage is measured at the noninverting input wHh respect to the corresponding inverting input.
DISSIPATION RATING TABLE
PACKAGE
N
NS
TA,,25°C
POWER RATING
=
DERATING FACTOR
ABOVE TA 25°C
TA 70°C
POWER RATING
1150mW
9.2mWrC
736mW
625mW
5.0mWrC
400mW
=
recommended operating conditions
Supply voltage, VCC
MIN
NOM
MAX
UNIT
4.75
5
5.25
",12
V
",12
V
O.B
V
Common-mode input voltage, VIC
Differential input voltage, VID
High-level enable-input voltage, VIH
2
Low-level enable-input voltage, VIL
High-level output current, IOH
Low-level output current, IOL
Operating free-airtemperature, TA
0
1ExAs
V
V
-400
..,A
B
mA
70
·C
~
INSIRUMENfS
POST OFFICE BOX 656303 • DAllAS, TEXAS 75265
2-589
SN75ALS175
QUAD DIFFERENTIAL LINE RECEIVER
SLLS131 B - 03910, SEPTEMBER 1991 - REVISED JANUARY 1993
electrical characteristics over recommended ranges of common-mode input voltage, supply
voltage and operating free-air temperature (unless otherwise noted) (see Note 3)
TEST CONDITIONS
PARAMETER
MIN
Vr+
Vr-
Positive-going threshold voltage
Vhys
Hysteresis (\IT +-
VIK
Enable-input clamp voltage
11=-18mA
VOH
High-level output voltage
VIO =200 mV,
10H = -400 !-LA.
See Figure 1
IOL=8mA,
See Figure 1
Negative-going threshold voltage
'TYpt
MAX.
UNIT
200
mV
mV
-200*
Vr -l
mV
50
-1.5
2.7
V
V
VOL
Low-level output voltage
VIO = -200 mV,
10Z
High-impedance-state output current
VO= 0.4Vt02.4V
II
Une input current
Other input at 0 V,
IIH
High-level enable-input current
VIH(E) = 2.7 V
20
IlL
Low-level enable-input current
VIL(E) = 0.4 V
-100
IlA
IlA
-85
rnA
rj
Input resistance
lOS
Short-circuit output current
ICC
Suply current (total package)
See Note 3
0.45
V
..20
IlA
IVI=12V
1
IVI=-7V
-0.8
rnA
kQ
12
-15
VO= 0,
See Note 4
No load,
Outputs enabled
16
24
No load,
Outputs disabled
18
27
rnA
t All typical values are at VCC = 5 V, TA = 25"C.
* The algebraic convention, in which the less positive (more negative) limit is designated as minimum, is used in this data sheet forthreshold voltage
levels only.
NOTES: 3. Refer to EIA Standards RS-485 for exact conditions.
4. ' Not more than one output should be shorted at a time, and the duration of the short-circuit should not exceed one second.
switching characteristics,
Vee = 5 V, TA = 25°C
PARAMETER
TEST CONDITIONS
tPHL
Propagation delay time, high-to-Iow-Ievel output
VIO = -2.5 V to 2.5 V,
tpLH
Propagation delay time, Iow-to-high-Ievel output
CL=15pF,
tPZH
Output enable time to high level
tpZL
Output enable time to low level
tpHZ
Output disable time from high level
tpLZ
Output disable time from low level
CL=15pF,
CL=15pF,
See Figure 2
See Figure 3
See Figure 3
t All typical values are at VCC = 5 V, TA = 25"C.
1ExAs
~
INSIR.UMENfS
2-590
POST OFFICE BOX 655303 • DAUAS, TEXAS 75265
MIN
'TYpt
MAX
9
18
27
9
18
27
ns
4
12
18
ns
UNIT
ns
6
13
21
ns
10
21
27
ns
8
15
25
ns
SN75ALS175
QUAD DIFFERENTIAL LINE RECEIVER
Su.s131B-D3910. SEPTEMBER 1991- REVISED JANUARY 1993
PARAMETER MEASUREMENT INFORMATION
{ij
lL _
VI
H
~IOL
(+)
-
+IOH
(-)
_
-
-
Figure 1. VOH. VOL
Generator
(see Note A)
~.5V
~.5~--
tpLH ~
r---.. .+--
Inpm
I
Ompm
1.3V!
::
tpHL~
VOH
1.3V \.....
VOL
VOLTAGE WAVEFORMS
TEST CIRCUIT
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR = 1 MHz. duty cycle = 50%. tr = tf = 6 ns.
B. CL includes probe and jig capacitance.
Figure 2. Propagation Delay Times
1ExAs
..If
INSIRUMENIS
POST OFFICE BOX 655303 • DAUAS. TEXAS 75265
2-Q91
SN75ALS175
QUAD DIFFERENTIAL LINE RECEIVER
SLLS131B-D3910, SEPTEMBER 1991 -REVISED JANUARY 1993
PARAMETER MEASUREMENT INFORMATION
Output
2kQ
(see Note C)
TEST CIRCUIT
Input
~
--t---I. ..
tpZH ~
Output
~-
3V
1.5V
OV SW1to1.5V
SW20pen
SW3 Closed
VOH
1.5 V
- - OV
3V"
~
Input
~=== 1.5V
OV SW1 to-1.5V
tpZL ~
SW2 Closed
I
SW30pen
- - 4.5V
Output
- 1.5 V
VOL
t---;--
~
tpZH
Input
~
1.5 V
I
----
3V
L •.
~ tpHZ
Output
0.5 V
~
3V~3V
Input
OV
SW1 t01.5V
SW2 Closed
SW3 Closed
tpZL
VOH
Output
- - 1.4V
1.5V
I
----
OV
---l+--+i
I
I
v:::::---'\: - - - f 0.5 V
""-
1.4 V
SW1 to-1.5V
SW2 Closed
SW3 Closed
VOL
VOLTAGE WAVEFORMS
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR = 1 MHz, duty cycle = 50%, tr = tf = 6 ns.
B. CL includes probe and jig capacHance.
C. All diodes are 1N916 or equivalent.
Figure 3. Enable and Disable Times
1ExAs . "
INSlRUMENTS
2-592
POST OFFICE BOX 655303 • DAll.AS, TEXAS 75265
SN75176A
DIFFERENTIAL BUS TRANSCEIVER
1989
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Bidirectional Transceiver
Meets EIA Standards RS-422-A and CCITT
Recommendations V.11 and X.27
Designed for Multipoint Transmission on
Long Bus Lines in Noisy Environments
3-State Driver and Receiver Outputs
Individual Driver and Receiver Enables
Wide Positive and Negative Input/Output
Bus Voltage Ranges
Driver Output Capability ... ±60 mA Max
Thermal Shutdown Protection
Driver Positive and Negative Current
Limiting
Receiver Input Impedance ..• 12 kQ Min
Receiver Input Sensitivity ... ±200 mV
Receiver Input Hysteresis •.. 50 mV Typ
Operates From Single 5-V Supply
Low Power Requirements
description
D OR P PACKAGE
(TOP VIEW)
RDa
RE
2
7
Vee
B
DE 3
6 A
D4sGND
logic symbol t
DE
RE
6 A
1---tl1--........,:;..
7 B
....c...
P--+-......
tThis symb'Ol is in accordance w~h ANSI/IEEE SId 91-1984
and lEe Publication 617-12.
logic diagram (positive logic)
The SN75176A differential bus transceiver is a
monolithic integrated circuit designed for
bidirectional data communication on multipoint
bus transmission lines. It is designed for balanced
transmission lines and meet EIA Standard
RS-422-A and CCITT Recommendations V.11
and X.27.
DE-4.:.....----,
D 3
RE...:2~_ _-,
R
....:...---<,~J-ilI--
. .,....:...: : }
.~
The SN75176A com bines a 3-state differential line driver and a differential input line receiver, both of which
operate from a single 5-V power supply. The driver and receiver have active-high and active-low enables,
respectively, that can be externally connected together to function as a direction control. The driver differential
outputs and the receiver differential inputs are connected internally to form differential input/output (I/O) bus
ports that are designed to offer minimum loading to the bus whenever the driver is disabled or Vee = O. These
ports feature wide positive and negative com mon-mode voltage ranges making the device suitable for party-line
applications.
Function Tables
DRIVER
INPUT
D
ENABLE
DE
H
L
H
H
L
X
RECEIVER
OUTPUTS
A
B
H
L
Z
DIFFERENTIAL INPUTS
A-B
ENABLE
RE
OUTPUT
R
VIO",0.2V
-0.2V---VCC
TYPICAL OF RECEIVER OUTPUT
---~--VCC
86g
Req
.-_~NOM
Input
Output
----'...,.--+-_---'i>-- - GND
=
=
Driver Input: Req 3 kg NOM
Enable Inpule: Req 8 kg NOM
ThxAs ."
INSIRUMENTS
2-594
POST OFFICE BOX 861530G • DAUAS, TEXAS 75265
SN75176A
DIFFERENTIAL BUS TRANSCEIVER
SLL.S100 - 02619, JUNE 1984 - REVISED AUGUST 1989
absolute maximum ratings over operating free-air temperature range {unless otherwise noted}
Supply voltage, Vee (see Note 1) ............................................................. 7 V
Voltage range at any bus terminal ................................................... -10 V to 15 V
Enable input voltage ....................................................................... 5.5 V
Continuous total power dissipation ..................................... See Dissipation Rating Table
Operating free-air temperature range .................................................. O·C to 70·C
Storage temperature range ....................................................... - 65·C to 150·C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds ............................... 260·C
NOTE 1: All voHage values, except differential Input/output bus voltage, are wfth respect to network ground terminal.
DISSIPATION RATING TABLE
PACKAGE
TA s 25"C
POWER RATING
DERATING FACTOR
ABOVE TA = 25"C
TA = 7O"C
POWER RATING
TA = 105"C
POWER RATING
o
725mW
5.8mWrC
464mW
261 mW
p
ll00mW
8.8mWrC
702mW
396mW
recommended operating conditions
Supply voltage, Vee
Voltage at any bus terminal (separately or common mode), VI or VIC
High-level input voltage, VIH
D,DE,andRE
Low-level input voltage, VIL
D,DE,andRE
MIN
TYP
MAX
UNIT
4.75
5
5.25
V
12
V
-7
0.8
Differential Input voltage, VID (see Note 2)
High-level output current, IOH
Low-level output current, IOL
V
2
Driver
Receiver
V
-60
rnA
-400
flA
Driver
60
8
Receiver
Operating free-air temperature, TA
V
,.12
0
70
rnA
"C
NOTE 2: Differential-Input/output bus voltage IS measured at the noninverting terminal A with respect to the Inverting terminal B.
1ExAs
~
INSIRUMENTS
POST OFFICE BOX 655303 • DAUAS. TEXAS 75265
2-595
SN75176A
DIFFERENTIAL BUS TRANSCEIVER
Su.s100 - 02619, JUNE 1984 - REVISED AUGUST 1989
DRIVER S.EeTIO~
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
TEST CONDITIONS
PARAMETER
Input clamp voltage
11=-18mA
VOH
High-level output voltage
VIH =2V;
IOH=-33mA
VIL=0.8V;
VOL
Low-level output voltage
VIH =2V;
10H=33mA
VIL = 0.8 V;
1V0Dli
Differential output voltage
10=0
VIK
MIN
TYpt
MAX
UNIT
-1.5
V
3.7
V
1.1
V
2VOD2
RL=loog,
See Figure 1
2
2.7
RL= 54 0,
See Figure 1
1.5
2.4
V·
IVOD21
Differential output voltage
AlVoDI
Change In magnitude of differential
output voltage:!:
VOC
Common-mode output voltage§
AlVocl
Change in magnitude of common-mode
output voltage:!:
10
Output current
Output disabled,
See Note 3
IIH
High-level input current
VI=2.4V
20
IlL
Low-level input current
VI =0.4V
-400
VO=-7V
-250
lOS
Short-Circuit output current
VO= VCC
250
VO=12V
500
ICC
Supply current (total package)
See Figure 1
RL = 54 0 or 100 g,
No load
I VO=12V
.. 0.2
V
3
V
.. 0.2
V
1
Iva =-7V
-0.8
I Outputs enabled
I Outputs disabled
V
35
50
26
40
rnA
f.IA
f.IA
rnA
rnA
t All typical values are at VCC = 5 V and TA = 25°C.
:!: AIVODI and AIVocl are the changes In magnitude of VOD and VOC respectively, that occur when the input Is changed from a high level to a
low level.
§ In EIA Standard RS-422A, VOC, which is the average of the two output voltages with respect to GND, Is called output offset voltage, VOS.
NOTE 3: This applies for both power on and off; refer to EIA Standard R5-422A for exact conditions.
switching characteristics, Vee = 5 V, TA = 25°e
PARAMETER
tdD
Differential-output delay time
ttD
Differential-output transition time
tpZH
tpZL
TEST CONDITIONS
MIN
UNIT
TYP
MAX
40
60
ns
65
95
ns
RL=600,
See Figure 3
Output enable time to high level
RL= 1100,
See Figure 4
55
.90
ns
Output enable time to low level
RL= 110g,
See Figure 5
30
50
ns
tpHZ
Output disable time from high level
RL=1100,
See Figure 4
85
130
ns
tpLZ
Output disable time from low level
RL=1100,
See Figure 5
20
40
ns
1ExAs ."
INSIRUMENTS
2-596
POST OFFICE BOX 655303 • DALlAS, TEXAS 75265
SN75176A
DIFFERENTIAL BUS TRANSCEIVER
SLLS100- 02619, JUNE 1984 - REVISED AUGUST 1989
RECEIVER SECTION
electrical characteristics over recommended ranges of common-mode input voltage, supply
voltage, and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYpt
MAX
UNIT
VT+
VT-
Positive-going input threshold voltage
VO=2.7V,
10 =-0.4 mA
Negative-going input threshold voHage
Vo = 0.5 V,
10=8mA
Vhys
Input hysteresis (\IT
VIK
Enable clamp voltage
11=-18mA
VOH
High-level output voltage
VIO=2oomV,
See Figure 2
10H = -400
VOL
Low-level output voltage
VIO = -200 mV,
See Figure 2
IOL=8mA,
10Z
High-impedance-state output current
Vo = 0.4 Vto 2.4 V
II
Une input current
Other input = 0 V,
See Note 3
IIH
High-level enable input current
VIH=2.7V
20
IlL
Low-level enable input current
VIL=0.4V
-100
ItA
ItA
-85
mA
0.2
+- VT-J
ri
Input resistance
lOS
Short-circuit output current
ICC
Supply current (total package)
V
V
-0.2*
50
mV
-1.5
ItA,
V
V
2.7
0.45
V
",20
ItA
IVI=12V
1
IVI=-7V
-0.8
mA
kQ
12
-15
No load
I Outputs enabled
35
50
I Outputs disabled
26
40
mA
t All typical values are at VCC = 5 V, TA = 25 D C.
* The algebraic convention, in which the less-positive (more-negative) limit Is designated minimum, is used In this data sheet for common-mode
Input voltage and threshold voltage levels only.
NOTE 3: This applies for both power on and power off. Refer to EIA Standard RS-422A for exact conditions.
switching characteristics, Vee
=5 V, CL =15 pF, TA =25°C
PARAMETER
TEST CONDI110NS
tPLH
Propagation delay time, low-to-high-Ievel output
tpHL
Propagation delay time, high-to-Iow-Ievel output
tpZH
Output enable time to high level
tpZL
Output enable time to low level
tpHZ
Output disable time from high level
tpLZ
Output disable time from low level
VIO=-1.5Vto 1.5V,
See Figure 6
See Figure 7
See Figure 7
POST OFFICE BOX 655303 • DAUAS, TEXAS 75265
MIN
UNIT
TYP
MAX
21
35
ns
23
35
ns
10
30
ns
12
30
ns
20
35
ns
17
25
ns
2-597
SN75176A
DIFFERENTIAL BUS TRANSCEIVER
SUS100- 02619, JUNE 1984- REVISEOAUGUSTI989
PARAMETER MEASUREMENT INFORMATION
RL
2
~~!t':L~-~
VOC
-4:Figure 1. Driver VOD and Voe
Figure 2. Receiver VOH and VOL
Input
Generator
(see Note A)
-i
tcio
50 {)
\1~~--::
-! j+- tcio
1.5V
r-
-!
re...
~-==--
Output ~ : :
.J 1
10% 1
t
"no<
to -....
TEST CIRCUIT
~
1.0
-+i..--
t
-2.5 V
to
--2.5V
VOLTAGE WAVEFORMS
Figure 3. Driver Test Circuit and Voltage Waveforms
Output
~--
Input
~l"'Y
OVor3V
-.I
500
le- tPZH
1
1/
1
t
Output
----'
TEST CIRCUIT
3V
~OV
I
I
Generator
(see Note A)
1 ...
0.5 V
J
\.-i
1 _! ~
1
2.3 V
tpHZ"""'"
VOH
Voff - 0 V
VOLTAGE WAVEFORMS
Figure 4. Driver Test Circuit and Voltage Waveforms
5V
Input J1.5V
3VorOV
t PZL
+-,
\~5~--::
:
1
Generator
(see Note A)
1--1- tpLZ
----..1
50 0
Output
TEST CIRCUIT
' \ 2.3 V
lr 5V
I I - 0.5 V
r-
VOL
VOLTAGE WAVEFORMS
Figure 5. Driver Test Circuit and Voltage Waveforms
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR = 1 MHz, 50% duty cycle,
ZO=500.
B. CL includes probe and jig capacHance.
1ExAs
~
INSIRUMENlS
2-598
POST OFFICE BOX 655303 • DAllAS, TEXAS 75265
Ir s 6 ns, If s 6 ns, -
SN75176A
DIFFERENTIAL BUS TRANSCEIVER
SLLS100- 02619, JUNE 1984 - REVISED AUGUST 1989
PARAMETER MEASUREMENT INFORMATION
~-;-:v--
Input
Generator
(see Note A)
JI""Y
510
1.5V-...."...r
I
I
tpLH ~
OV - - - - - '
Output
I
.....,- tpHL
~-~.~V-
~'.3V
TEST CIRCUIT
3V
~OV
~
VOH
VOL
VOLTAGE WAVEFORMS
Figure 6. Receiver Test Circuit and Voltage Waveforms
1.5V
S1
I
Generator
(see Note A)
S2
2kO
-1.5V - - 0
CL= 15pF
(see Note B)
0 - - 5V
1N916 or Equivalent
5kO
500
l
TEST CIRCUIT
Inp~-~~~~.:v
I
tpZH -.I if-
S1t01.5V
OV S20pen
S3 Closed
~~~::
Input~~~~~.:v
S1 to-1.5V
i
I
0 V S2 Closed
tpZL-.I '-'
S3 Open
, I
1--_4.5V
Output
S1 t01.5V
S2Closed
S3Closed
S3
~
1.5V
£'C-I
Input
VOL
3V
1.5V
I
I
S1to-1.5V
S2Closed
S3Closed
OV
tpLZ~
~--VOH
_ _ _ _..1_ _ _ _ _
lut
~---
OutP~O.5V
-1.3V
~
-1.3V
VOL
VOLTAGE WAVEFORMS
Figure 7. Receiver Test Circuit and Voltage Waveforms
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR
ZO=500.
=1 MHz, 50% duty cycle,tr S 6 ns, tf S 6 ns,
B. CL includes probe and jig capacHance.
1ExAs
,If
INSIRUMENTS
POST OFFICE BOX 655303· DALLAS, TEXAS 75265
2-599
SN75176A
DIFFERENTIAL BUS TRANSCEIVER·
SLLS100- 02619. JUNE 1984- REVISED AUGUST 1989
TYPICAL CHARACTERISTICS
DRIVER HIGH-LEVEL OUTPUT VOLTAGE
DRIVER LOW-LEVEL OUTPUT VOLTAGE
V$
V$
DRIVER HIGH-LEVEL OUTPUT CURRENT
DRIVER LOW-LEVEL OUTPUT CURRENT
5
>I
t
~
4.5
4
!
r-- r---
3.5
i~
0
5
VCC .. 5V
4.5 r-TA=25°C
VCC=5V
TA=25°C -
3
~
4
I
3.5
~
3
0
1i
2.5
•
~t-.,
~
.........
2.5
I'.....
,
2
~
J
~
J:
I
J:
>I
1.5
I
I
/
'/
2
1.5
I
....I
.p
..........
.p
0.5
o
0.5
o
-20
-40
-60
-80
-100
-
60
80
100
20
40
IOL - Low-Level Output Current - mA
-120
10H - High-Level Output Current - mA
Figure 8
V$
DRIVER OUTPUT CURRENT
RECEIVER LOW-LEVEL OUTPUT CURRENT
•co
3
!
I
........
Q.
i'.
2.5
......
~I!!
~
0
]
\
0.5
~
\
30
40
60
60
70
80
0.3
0.2
I
....I
\
20
0.4
~
I
10
I
0
"'\
1.5
o0
0.5
~
i'. .......
2
90 100
10 - Output Current - mA
V
/
V
~V
/
V
./
I
\
0.1
o
o
5
10
15
20
25
IOL - Low Level Output Current - mA
Figure 10
Figure 11
1ExAs
~
INSIR.UMENIS
2-600
V
VCC=5V
TA=25OC
>I
•co
0
.p
-
i"-t-.,
~
0
0.6
I
VCC=5V
TA = 25°C
~
~
RECEIVER LOW-LEVEL OUTPUT VOLTAGE
va
4
3.5
120
Figure 9
DRIVER DIFFERENTIAL OUTPUT VOLTAGE
>I
--"
~
POST OFFICE BOX 655303 • DAllAS. TEXAS 75265
30
SN75176A
DIFFERENTIAL BUS TRANSCEIVER
SLLS100-D2619. JUNE 1984- REVISED AUGUST 1989
TYPICAL CHARACTERISTICS
RECEIVER LOW-LEVEL OUTPUT VOLTAGE
RECEIVER OUTPUT VOLTAGE
VB
ENABLE VOLTAGE
va
FREE-AIR TEMPERATURE
0.5
>I
t
0.4
!
0.3
4
f
J
V"""
I--- VCC = 4.75 V -
2
I
~
.3I
~
I
VCC=5V
3
!
0.2
.1
VCC=5.25V -
I
'-
~
....I
VIO=0.2V
Load = 8 kc to GNO
TA=25·C
>
~
)
5
VCC=5V
VIO=-0.2V
IOL=8mA
0.1
o
o
ro
~
~
~
~
~
ro
o
M
o
1.5
2
VI - Enable Voltage - V
0.5
TA - Free-Air Temperature _·C
2.5
3
Figure 13
Figure 12
RECEIVER OUTPUT VOLTAGE
va
ENABLE VOLTAGE
6
II.
VCC=5.25V
5
II
CII
I
I
VCC=4.75V
>
I
I
VIO=O.2V
Load = 1 kCtoVCC
TA=25·C
I'VCC=5V
4
!
~
'Sa.
'S
3
I
2
0
~
o
o
0.5
1.5
2
VI - Enable Voltage - V
2.5
3
Figure 14
POST OFFICE BOX 655303 • DAllAS. TEXAS 75265
2--601
SN75176A
DIFFERENTIAL BUS TRANSCEIVER
SLLS100-D2619, JUNE 1984-REVISEDAUGUSTl989
APPLICATION INFORMATION
SN75176A
SN75176A
Up to 32
Transceivers
•••
Figure 15. Typical Application Circuit
NOTE: The line should be terminated at both ends in its characteristic impedance. Stub lengths off the main line should be kept as short as
possible.
1ExAs
..If
INSIRUMENTS
2~02
POST OFFICE BOX 655303 • DAUAS. TEXAS 75265
SN65176B,SN75176B
DIFFERENTIAL BUS TRANSCEIVERS
D OR P PACKAGE
(TOP VIEW)
•
•
Bidirectional Transceiver
Meets EIA Standards RS-422-A and RS-485
and CCITT Recommendations V.11 and X.27
•
Designed for MuHlpolnt Transmission on
Long Bus Unes in Noisy Environments
FiE
3-State Driver and Receiver Outputs
Individual Driver and Receiver Enables
Wide Positive and Negative Input/Output
Bus Voltage Ranges
D
•
•
•
•
Driver Output Capability ••• ~60 mA Max
•
•
Thermal Shutdown Protection
Driver Positive and Negative Current
Umltlng
Receiver Input Impedance ••• 12 kQ Min
Receiver Input Sensitivity ••• ~200 mV
Receiver Input Hysteresis ••• 50 mV Typ
Operates From Single S-V Supply
Low Power Requirements
•
•
•
•
•
ROe
2
3
4
DE
7
6
Vee
B
A
5 GND
logic symbol t
SA
7B
tThIs symbol Is In accordance with ANSI/IEEE Std 91-1984
and lEe Publication 617-12.
description
logic diagram (positive logic)
DE _4"--_ _.,
The SN65176B and SN75176B differential bus
transceivers are monolithic integrated circuits
designed for bidirectional data communication on
multipoint bus transmission lines. They are
designed for balanced transmission lines and
meet EIA Standard RS-422-A and RS-485 and
CCITT Recommendations V.11 and X.27.
D 3
RE~2~--.,
R
-'---~:~::~::::: :
}
Bu.
The SN65176B and SN75176B combine a 3-state differential line driver and a differential input line receiver,
both of which operate from a single 5-V power supply. The driver and receiver have active-high and active-low
enables, respectively, that can be externally connected together to function as a direction control. The driver
differential outputs and the receiver differential inputs are connected internally to form differential input/output
(I/O) bus ports that are designed to offer minimum loading to the bus whenever the driver is disabled or
Vee = O. These ports feature wide positive and negative common-mode voltage ranges making the device
suitable for party-line applicetions.
Function Tables
DRIVER
INPUT
D
H
L
X
ENABLE
DE
H
H
H = high level.
L
RECEIVER
OUTPUTS
A
B
L
H
L
H
Z
Z
L .. low level.
DIFFERENTIAL INPUTS
A-B
ENABLE
RE
OUTPUT
R
VIDa:0.2V
-0.2 V < VID < 0.2 V
VID,,-0.2V
X
Open
L
L
L
H
H
Z
H
? = indeterminate.
X -Irrelevant.
L
?
L
Z .. high impedance (off)
CopyrIght @ 1989. Texas Instruments Incorporated
1ExAs . "
INSIRUMENTS
POST OFFICE BOX _
• DAI..I.AS. TEXAS 7 _
SN65176B, SN75176B
DIFFERENTIAL BUS TRANSCEIVERS
SLLS101 - 02819, JULY 1986 - REVISED SEPTEMBER 1989
description (continued)
The driver is designed to handle loads up to 60 mA of sink or source current. The driver features positive- and
negative-current limiting and thermal shutdown for protection from line fault conditions, Thermal shutdown is
designed to occur at B junction temperature of approximately 150·C. The receiver features a minimum input
impedance of 12 kg, an Input sensitivity of :t200 mY, and a typical input hysteresis of 50 mY.
The SN65176B and SN75176B can be used in transmission line applications employing the SN75172 and
SN75174 quadruple differential line drivers and SN75173 and SN75175 quadruple differential line receivers.
The SN65176B characterized for operation from -40·C to 105·C and the SN75176B is characterized for
operation from O·C to 70·C.
schematics of Inputs and outputs
EQUIVALENT OF EACH INPUT
TYPICAL OF A AND B I/O PORTS
VCC--.......-
--P---...--~t---Vcc
TYPICAL OF RECEIVER OUTPUT
---~--VCC
SSg
" ___- -.... NOM
Input
Output
-~>-+-"""'''''''''''''''---GND
Driver Input: Req =3 lin NOM
Enable Inpula: Req .. 8 lin NOM
TEXAS ...,
2-604
INSIRUMENTS
POST OFFICE BOX _
• DAU..AS, TEXAS 7&265
SN65176B, SN75176B
DIFFERENTIAL BUS TRANSCEIVERS
SLLS10l - 02619, JULY 1985 - REVISED SEPTEMBER 1989
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) ............ , ..... , ............................ , .. , ..... , .... 7V
Voltage at any bus terminal .... .. . . . . . .. . . . . . .. . . . . . . . . . . . . . . . . . . .. . . . .. . . . . . . . .. .. -10 V to 15 V
Enable input voltage ......................................................................• 5.5 V
Continuous total power dissipation .........•........................... See Dissipation Rating Table
Operating free-air temperature range: SN65176B .................................. -40°C to 105°C
SN75176B ...................................... O°C to 70°C
Storage temperature range ....................................................... - 65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds ............................... 260°C
NOTE 1: All voltage values, except differential Input/output bus voltage, are with respect to network ground terminal.
DISSIPATION RATING TABLE
TA,,25·C
POWER RATING
DERATING FACTOR
ABOVE TA 25·C
D
725mW
5.8mWre
464mW
261 mW
P
1100mW
8.8mWre
702mW
396mW
PACKAGE
=
TA=70·C
POWER RATING
TA=105·C
POWER RATING
recommended operating conditions
Supply voltage, vee
MIN
TYP
MAX
UNIT
4.75
5
5.25
V
12
Voltage at any bus terminal (separately or common mode), VI or VIC
High-level input voltage, VIH
D, DE,andRE
Low-level input voltage. Vil
D, DE, and RE
-7
2
High-level output current, IOH
Low-level output current, IOL
Operating free-air temperature, TA
V
0.8
Differential Input voltage, VID (see Note 2)
Driver
Receiver
V
V
:012
V
-60
mA
-400
(.tA
60
Driver
Receiver
8
SN65176B
-40
105
SN75176B
0
70
mA
·e
NOTE 2: Differential-Input/output bus voltage IS measured at the nomnvertlng terminal A With respect to the Inverting terminal B.
1ExAs
,If
INSIRUMENTS
POST OFFICE SOX 665303 • DAL1.AS, TEXAS 75265
2-605
SN65176B, SN75176B
DIFFERENTIAL BUS TRANSCEIVERS
SLl.S101 - 02619, JULY 1985 - REVISED SEPTEMBER 1989
DRIVER SECTION
electrical characteristics over recommended ranges of supply voltage and operating free-alr
temperature (unless otherwise noted)
TEST CONDITIONSt
PARAMETER
Input clamp voltage
MIN
-1.5
Output voltage
10=0
0
IVOD11
Differential output voltage
10=0
1.5
1"0021
Differential output voltage
VOD3
Differential output voltage
AIVODI
Change in magnitude of differential output
voItage§
Voc
Common-mode output voltage
AIVocl
Change In m!inltUde of common-mode
output voltage
10
Output current
Output disabled,
See Note 5
IIH
High-level input current
VI-2.4V
IlL
Low-level Input current
VI =0.4V
VO .. -7V
lOS
ICC
Short-circuit output current
Supply current (total pilckage)
MAX
TYP*
11=-18mA
VIK
Vo
RL c 100Q,
See Figure 1
RL=54Q,
See Note 4
See Figure 1
1/2V~1
' or2
1.5
8
8
V
8
V
V
2.5
1.5
RL" 54 Q or 100 Q,
See Figure 1
I VO=12V
I VO=-7V
5
V
5
V
:1:0.2
V
+3
-1
V
:1:0.2
V
1
-0.8
20
-400
mA
tJA
tJA'
-250
VO .. O
150
VO" VCC
VO=12V
250
No load
UNIT
V
mA
250
I Outputs enabled
I Outputs disabled
42
70
28
35
mA
t The power.ofl measurement II) EIA Standard RS-422-A applies to disabled outputs only and Is not applied to combined Inputs and outputs.
* All typical values are at Vee = 5 V and TA = 25°C.
'
§ AIVODI and AlVoel are the changes In magnitude of VOD and Voe, respectively, that occur when the Input Is changed from a high level to a
low level.
11 The minimum VOD2 with a 10().Q load Is either 1/2 VOD1 or 2 V, whichever Is greater.
NOTES: 1. See EIA Standard RS-485 Figure 3.5, Test Termination Measurement 2.
2. This applies for both power on and off; refer to EIA Standard RS-485 for exact conditions. The RS-422-A limit does not apply for a
combined driver and recalver terminal.
switching characteristics, Vee
PARAMETER
=5 V, RL =110 kQ, TA =25°C (unless otherwise noted)
TEST CONDITIONS
MIN
TYP
MAX
15
20
ns
20
30
120
80
250
30
ns
!dD
Dlfferential-output delay time
Ito
Differential-output transition time
tpZH
Output enable time to high level
See Figure 4
85
tpZL
Output enable time to low level
See Figure 5
40
tpHZ
tpLZ
Output disable time from high level
See Figure 4
150
Output disable time from low level
See Figure 5
20
RL" 54 _e Figure 3
1ExAs' . "
INS1R.UMENfS
2-608
POST OFFICE BOX 665303 • DAU.AS, TEXAS 75266
UNIT
ns
ns
ns
ns
SN65176B, SN75176B
DIFFERENTIAL BUS TRANSCEIVERS
SLLS101 - 02619, JULY 1985 - REVISED SEPTEMBER 1989
SYMBOL EQUIVALENTS
DATA SHEET PARAMETER
RS-422-A
RS-485
Vo
Voa Vob
Voa Vob
IVOD11
Vo
Vo
IVOD21
VdRL = 100 0)
VdRL" 54 C)
Vt (Test Termination
Measurement 2)
IVOD31
AlVoDI
IIVtl-IVtll
VOC
IVasl
IVasl
AIVoe!
lVas-Vasl
IVas-Vasl
lOS
Ilsal,llsbl
10
Ilxal,llxbl
IIVt-lVtll
lia' lib
RECEIVER SECTION
electrical characteristics over recommended ranges of common-mode Input voltage, supply
voltage, and operating free-alr temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYpt
MAX
0.2
UNIT
V
VT+
Posltive-golng input threshold voltage
VO=2.7V,
10=-0.4mA
VT-
Negative-going input threshold voltage
VO=0.5V,
10=8mA
Vhvs
Input hysteresis (VT + - Vy -l
V,K
Enable clamp voltage
1,=-18mA
VOH
High-level output voltage
V,D=200mV,
See Figure 2
'OH,,-400j.&A,
VOL
Low-level output voltage
V,D " -200 mY,
See Figure 2
'OL=8mA,
10Z
High-impedance-slate output current
Vo = 0.4 Vto 2.4 V
I,
Une input current
Other input = 0 V,
See Note 5
IIH
High-level enable input current
V,H =2.7V
20
IlL
Low-level enable input current
V'L-0.4V
-100
IIA
IIA
fj
Input resistance
V, = 12V
lOS
Short-circuit output current
-85
mA
ICC
Supply current (total package)
V
-0.2*
mV
50
-1.5
V
2.7
IV,=12V
IV,=-7V
0.45
V
",20
IIA
1
-0.8
mA
kQ
12
-15
No load
V
I Outputs enabled
42
55
I Outputs disabled
26
35
mA
t All typical values are at VCC = 5 V, TA = 25°C.
* The algebraic convention, in which the less-positive (more-negative) limit is designated minimum, is used in this data sheet for common-mode
Input voltage and threshold voltage levels only.
NOTE 3: This applies for both power on and power off. Refer to EIA Standard RS-485 for exact conditions.
1ExAs ."
INSIRUMENTS
POST OFFICE BOX 65S303 • DALLAS, TEXAS 75266
2--607
SN65176B,. SN75176B
.
DIFFERENTIAL BUS TRANSCEIVERS
SLLS101-D2619, JULY 11186- REVISED SEPTEMBER 19811
switching characteristics, Vee =5 V, CL =15 pF, TA =25°C
TEST CONDITIONS
PARAMETER
IpHL
Propagation delay time, low-lo-high-level output
Propagation delay time, hlgh-to-Iow-level output
tPZH
Output enable time to high level
IpZL
Output enable time to low level
IpHZ
IpLZ
Output disable time from high level
Output disable time from low level
IpLH
VIO
=0 to 3 V,
See Figure 6
See Figure 7
See Figure 7
1ExAs ."
2-608
INSIRUMENIS
POST OFFICE BOX 86S303 • DAllAS, TEXAS 76266
MIN
TYP
MAX
21
23
35
ns
35
ne
10
20
ns
12
20
ns
20
35
17
25
ne
ne
UNIT
SN651768, SN751768
DIFFERENTIAL BUS TRANSCEIVERS
SLLS10l - 02619. JULY 1985 - REVISED SEPlEMBER 1969
PARAMETER MEASUREMENT INFORMATION
RL
2
$t>-{~t +101
-b
VOL
-:!:- ':"
':" ':"
Figure 2. Receiver VOH and VOL
Figure 1. DriverVOD and Voe
\1~~-::
Input --11.5 V
Generator
(see Note A)
+-IOH
VOH
VOC
fclD
50 D
-..!
""OL
~
::
•
!.- 10%-! '- ltD ~ - 2.5 V
ltD --.I
TEST CIRCUIT
j- fclD
~=:::-- ~25V
Output~
3V
-..!
j--
VOLTAGE WAVEFORMS
Figure 3. Driver Test Circuit and Voltage Waveforms
r;:;-:;;s:
-l,D'I\...-ov
Output
Input
~l.DV
OVor3V
It- tPZH
~
50D
Output
1
V
t2.3V
tpHZ
_ _.J
TEST CIRCUIT
1
I
I
Generetor
(see Note A)
3V
0.5 V
J_v,
1 \.-.
1 J~
...-.t
OH
Voff ~ 0 V
VOLTAGE WAVEFORMS
Figure 4. Driver Test Circuit and Voltage Waveforms
5V
RL=110D
Output
3VorOV---I
Input
J1.5V
\~5~--::
tPZL~
1
Generetor
(_NoteA)
--"",I
50 D
Output
TEST CIRCUIT
' \ 2.3 V
i
~tpLZ
!r
6V
0.5 V
f'-VOL
iI-
VOLTAGE WAVEFORMS
Figure 5. Driver Test Circuit and Voltage Waveforms
NOTES: A. The Input pulse is supplied by a generator having the following characteristics: PRR .. 1 MHz. 50% duty cycle.1r '" 6 ns. tf'" 6 ns,
Zo=50Q.
B. CL Includes probe and jig capacitance.
INSIRUMENI'S
1ExAs "
POST OFFICE BOX 8&5303 • DAI.1.AS. lECAS 752M
2-609
SN65176B, SN75176B
DIFFERENTIAL BUS TRANSCEIVERS
SLLS101-D2819, JULY 1985- REVISED SEPTEMBER 1989
PARAMETER MEASUREMENT INFORMATION
Input
Generator
(SHNoteA)
I
I
I
tpLH~
Output
-
3V
~OV
- - " " " " ..
1.5V--u.-y
OV----'
-;.~-
;;;;--'\
51 g
I
~tpHL
---VOH
~
I 1.3V
1.3V
VOL
VOLTAGE WAVEFORMS
TEST CIRCUIT
FIgure 6. Receiver Test Circuit and Voltage Waveforms
1,SV
-1.5V
aka
--0
I
CL=1SpF
-::- (IHNot.B)
sa
1N915 or Equlval.nt
Skg
L....-_ _...
Generator
(He Note A)
soc
TEST CIRCUIT
Inp~t
-~~~~,:V
I
tPZH -.! \4I
Output
51 to1.SV
OV 52 Open
53 Clos.d
~
Input~~~~~.:v
I
tpZL-.!
o
VOH
1.6 V
- - - - - OV
Output
S1 to 1.SV.
S2Clos.d
S3Clos.d
'I
S1 to-1.6V
0 V S2 Cloaed
S3 Open
r--vd-~S~
---1
LVOL
I
~
--
Input
3V
S1to-1.SV
sa Cloa.d
1.5 V
I
I
-4.SV
S3Clos.d
OV
tpLZ~
out
• ~--- -1.3V
outp~ O.SV
"---
,----VOH
---..1.----- -1.3V
VOL
VOLTAGE WAVEFORMS
Figure 7. Receiver Test Circuit and Voltage Waveforms
NOTES: A. The input pulse il supplied by a generator having the following characteristics: PRR ,,1 MHz, SO% duty cycle, 1,0 " 6 nl, tf " 6 ns,
Zo-SOC,
B. CL includes probe and jig capacitance.
1ExAs ."
INSIRUMENrS
2-el0
POST OFFICE BOX _
• DALlAS, TEXAS 75265
SN65176B, SN75176B
DIFFERENTIAL BUS TRANSCEIVERS
SLLS10l - 02619. JULY 1985 - REVISED SEPTEMBER 1989
TYPICAL CHARACTERISTICS
DRIVER LOW-LEVEL OUTPUT VOLTAGE
DRIVER HIGH-LEVEL OUTPUT VOLTAGE
va
va
DRIVER HIGH-LEVEL OUTPUT CURRENT
DRIVER LOW·LEVEL OUTPUT CURRENT
&
>I
•
f
!i
f
0
!...
lI
&
VCC=5V
4.5 '-TA = 25°C
VCC=5V
TA=25°C -
4.5
>I
r-- ...........
4
3.&
J•
~~
3
..........
2.5
~
!i
,
f
~
0
I
2
1.&
4
I
3.5
I
I
II
3
2.5
2
1.5
,.. ,.
I
%
%
.p
:9
0.5
o
0.5
o
-20
-40
-&0
-&0
-100
IOH - High-level Output Current - rnA
-
~
-'
20
40
&0
&0
100
10L - Low-Level Output Current - rnA
-120
Figure 8
120
Figure 9
DRIVER DIFFERENTIAL OUTPUT VOLTAGE
va
DRIVER OUTPUT CURRENT
4
>I
3.5
•
aI
3
!i
2.5
I
f
0
ii
.......
t'-...
......
~
I
-
......... ......
I'.. r-......
2
1\
i!
I!
V~C.5V
TA=25°C
1.5
\
CI
I
CI
.p
\
0.5
o0
\
10
20
30 40 50 &0 70 &0
10 - Output Current - mA
90 100
Figure 10
1ExAs ."
INSlRUMENTS
POST OFFICE BOX _
• DALI.AS. TEXAS 75265
~11
SN65176B, SN75176B
DIFFERENTIAL BUS TRANSCEIVERS
SLLS101 - 02619. JULY 1995 -
REVISED SEPTEMBER 1989
TYPICAL CHARACTERISTICS
RECEIVER HIGH-LEVEL OUTPUT VOLTAGE
RECEIVER HIGH·LEVEL OUTPUT VOLTAGE
va
va
FREE·AIR TEMPERATUREt
HIGH·LEVEL OUTPUT CURRENT
5
.1
4.5
>I
4.5
>
I
t-....
CII
3.5
~~
!0 2.5
~~
~ ~ V VCC =5.25V
2
V VCC=5V
.c
~~
g 1.5
VCC=4.75V
:z:
I
~~
:z:
:9 0.5
~~
~~
o
~
'S
!
~
I
:z:
:9
0.5
o
-40 -20
-5 -10 -15 -20 -25 -30 -35 -40 -45 -50
0
Figure 11
~
0.4
va
VCC=&V
TA=2&·C
'Sc:L
'S
0.2
I
..J
~
/
0.3
/
/
V
/
'"
/
>
.
0.&
~
0.4
I
I
'S
!
0
V
S
!.!J
~
o
&
10
15
20
25
30
VCC·I5V
VIO--200mV
IOL=8mA
.....
0.3
0.2
0.1
o
-40 -20
IOL - Low-Level Output Current - mA
Figure 13
0
20
40
. 1ExAs'"
INSTRUMENTS
POST OFFICE BOX 656300 • DAUAS. TEXAS 715286
60
80
TA - Free·Alr Tempereture _·C
Figure 14
t Only the O·C to 70·C portion of the curve applies to the SN75176B.
2-612
120 '
0.6
/'
0.1
o
100
RECEIVER LOW·LEVEL OUTPUT VOLTAGE
FREE·AlR TEMPERATURE
!
)
80
RECEIVER .LOW·LEVEL OUTPUT CURRENT
CII
0
60
va
0.6
0.5
40
Figure 12
RECEIVER LOW·LEVEL OUTPUT VOLTAGE
.
20
TA - Free·Alr Temperature - ·C
IOH - Hlgh·Level Output Current - mA
>I
I
J 2.:
I ,~
3
o
V~C .5V
r-- VIO .. 200 mV
4 I - JoH" -440 I4A
I ~&
4
•
!
15
_I
VIO=0.2V
TA,,25·C
100
120
SN65176B, SN75176B
DIFFERENTIAL BUS TRANSCEIVERS
SLLS101 - 02619. JULY 1985 - REVISED SEPTEMBER 1989
TYPICAL CHARACTERISTICS
RECEIVER OUTPUT VOLTAGE
RECEIVER OUTPUT VOLTAGE
VB
VB
ENABLE VOLTAGE
ENABLE VOLTAGE
5
,I
8
VIO-0.2V
Load = 8 kg to GNO
TA .. 25·C
4
I
>I
VCC=5V
3
,I
J
J
VCC=5.25V-
J
>I
I
VCC=4.75V_
2
I
I
~
~
o
o
1.5
2
VI- Enabla Voltaga - V
2.5
3
~
VIO--0.2V
Load .. 1 kg to VCC
TA-25·C
5
VCC:a4.75V
I
I'VCC=5V
4
3
2
o
0.5
I
VCC .. 5.25V
o
0.5
1.5
2
2.5
3
VI- Enabla Voltaga - V
Figure 15
Figure 16
APPLICATION INFORMATION
SN85178B
SN75178B
SN85178B
SN75178B
Up to 32
Transcelvara
•••
Figure 17.1Yplcal Application Circuit
NOTE: The line should be tenninated at both ends in its characteristic impedance. Stub lengths off the main line should be kept as short as
possible.
1ExAs
~
INSlRUMENTS
POST OFFICE BOX 655303 • DAUAS. TEXAS '75266
2-613
2-$14
SN95176B
DIFFERENTIAL BUS TRANSCEIVER
SGLS026-
•
•
•
•
•
•
•
•
•
•
•
•
•
MARCH 1989
JGPACKAGE
Bidirectional Transceiver
Suitable for Most EIA Standards RS·422·A
and RS-485 Applications
Designed for Multipoint Transmission on
Long Bus Lines In Noisy Environments
3·State Driver and Receiver Outputs
Individual Driver and Receiver Enables
Wide Positive and Negative Input/Output
Bus Voltage Ranges
Driver Output Capability ... ±60 mA Max
Thermal Shutdown Protection
Driver Positive and Negative Current
Limiting
Receiver Input Sensitivity •.• ±200 mV
Receiver Input Hysteresis ... 50 mV Typ
Operates From Single 5·V Supply
Low Power Requirements
(TOP VIEW)
~D8 Vee
RE
DE
D
2
3
7
6
4
5
B
A
GND
WPACKAGE
(TOP VIEW)
R
Vec
NC
NC
DE
NC
FKPACKAGE
(TOP VIEW)
description
The SN95176B differential bus transceiver is a
monolithic integrated Circuit designed for bidirectional data communication on multipoint bus
transmission lines. The transceiver is suitable for
most RS-422-A and RS-485 applications to the
extent of the specified data sheet characteristics
and operating conditions.
NC
RE
NC
DE
NC
5
6
7
8
17
B
16
15
NC
A
NC
9 10 11 12 13
The SN95176B combines a 3-state differential
line driver and a differential input line receiver,
00000
both of which operate from a single 5-V power
z
zzz
(!)
supply. The driver and receiver have active-high
NC - No internal connection
and active-low enables, respectively, that can be
externally connected together to function as a
direction control. The driver differential outputs and the receiver differential inputs are connected internally to
form differential input/output (I/O) bus port!? that are designed to offer minimum loading to the bus whenever the
driver is disabled or VCC =O. These ports feature wide positive and negative common-mode voltage ranges
making the device suitable for party-line applications.
'
14
The driver is designed to handle loads up to 60 rnA of sink or source current. The driver features positive- and
negative-current limiting and thermal shutdown for protection from line fault conditions. Thermal shutdown is
designed to occur at a junction temperature of approximately 150°C. The receiver features a minimum input
impedance of 12 kQ, an input sensitivity of ±200 mV, and a typical input hysteresis of 50 mY.
The SN95176B is characterized for operation from -40°C to 110°C.
Copyright@) 1989, Texas Instruments Incorporated
TEXAS . "
INSIRUMENTS
POST OFFICE BOX 655303 • DAUAS. TEXAS 75265
2-615
SN95176B
DIFFERENTIAL BUS TRANSCEIVER
SGLS026 - 03272, MARCH 1989
Function Tables
DRIVER
INPUT
0
H
L
X
ENABLE
DE
H
H
L
RECEIVER
OUTPUTS
A
B
H
L
L
H
Z
DIFFERENTIAL INPUTS
A-B
ENABLE
RE
OUTPUT
R
VID"' 0.2 V
-0.2VI
t
~
!i
Do
!i
0
ii
4.5
3.5
>
.
i'-.... ......
3
:t:
1.5
I
4
I
3.5
~
...........
2.5
!s:
VCC=5V
4.5 I-TA = 25°C
r-- r-...
4
2
aI
5
VCC=5V
TA=25°C -
~
,
...........
!i
0
j
I
I
I
I
3
2.5
2
1.5
I
J:
.,
J:
.p
.p
0.5
o
i"""
0.5
o
o
-20
-40
-60
-80
-100 -120
'OH - High-level Output Current - mA
o
---
II
..-/
40
80
100
20
60
10L - Low-Level Output Current - mA
Figure 8
120
Figure 9
DRIVER DIFFERENTIAL OUTPUT VOLTAGE
va
DRIVER OUTPUT CURRENT
>
.
4
V~C=5V
I
3.5
TA=25°C
-
I
aI
~
3
~
2.5
0
ii
2
!!
1.5
.........
i'. ,
~
"'- ......
I'. ~
!i
r"\
'E
~I
~
1
Q
.p
0.5
o0
\
10
20
30
40
50
60
70
80
90 100
10 - Output Current - mA
Figure 10
'TExAs
,If
INSIRUMENTS
POST OFFICE BOX 655303 • DAlLAS. TEXAS 75265
2-623
SN95176B
DIFFERENTIAL BUS TRANSCEIVER
SGLS026- D3272, MARCH 1989
TYPICAL CHARACTERISTICS
RECEIVER HIGH-LEVEL OUTPUT VOLTAGE
RECEIVER HIGH"LEVEL OUTPUT VOLTAGE
vs
va
HIGH-LEVEL OUTPUT CURRENT
FREE-AIR TEMPERATUREt
5
I
>I
&
4
I
3.5
0
2.&
1
5
3
!
2
.c
!P 1.5
J:
I
J:
oJ'
4.5
_I
-'
I
0
20
VCC=&V
f-- VIO = 200 mV
f- IOH = -440 !1A
r-....
R~
~
~~
~ ~ V Vcc =&.25V
V VCC=5V
~
~
'- VCC = 4.75 V
~~
.~
0.&
o
5
J
VIO=0.2V
TA=25°C
4.5
~
~~
o
o
-40 -20
-5 -10 -15 -20 -25 -30 -35 -40 -45 -50
Figure 11
vs
FREE-AIR TEMPERATURE
VCC=5V
TA = 25°C
/
0.5
l!I
0
0.3
i
I
0.2
I
/
/
V '"
V
/
,
>I
'"
VCC=5V
VIO =-200 mV
IOL=8mA
0.5
GI
~
0.4
0
0.3
5a.
5
I
I--
0.2
I
/
..J
oJ'
0.1
o
o
5
10
15
20
25
30
0.1
o
-40 -20
0
20
40
60
80
TA - Free-Air Temperature - DC
IOL - Low-Level Output Current - mA
Figure 13
Figure 14
1ExAs
..If
INSIRUMENTS
2-624
120
0.6
V
..J
oJ'
100
RECEIVER LOW-LEVEL OUTPUT VOLTAGE
RECEIVER LOW-LEVEL OUTPUT CURRENT
3.
0.4
80
vs
0.6
~
60
Figure 12
RECEIVER LOW-LEVEL OUTPUT VOLTAGE
>I
40
TA - Free-Air Temperature - °c
IOH - High-level Output Current - mA
POST OFFICE BOX 655303 • DAUAS. TEXAS 75265
100
120
SN95176B
DIFFERENTIAL BUS TRANSCENER
SGLS026 - 03272. MARCH 1989
TYPICAL CHARACTERISTICS
RECEIVER OUTPUT VOLTAGE
RECEIVER OUTPUT VOLTAGE
vs
vs
ENABLE VOLTAGE
ENABLE VOLTAGE
5
6
VIO = 0.2 V
Load 8 kO to GNO
TA=25°e
I I
=
I
>
I
i
J
Vee=5V
3
I
~
II
J
Vee = 4.75 V _
I
I
~
~
2
I
o
0.5
Vee = 4.75 V
>
~
o
2.5
3
VIO=-0.2V
Loael: 1 kO to Vee
TA=25"e
I
I'vee =I5V
4
3
2
o
1.5
2
VI- Enable Voltage - V
I
5
Vee = 5.25 V -
4
I
Vee.= 5.25 V
o
0.5
2
2.5
3
VI - Enable Voltage - V
Figure 15
Figure 16
APPLICATION INFORMATION
SN95176B
SN95176B
Up to 32
Tl'anscelvera
•••
Figure 17. Typical Application Circuit
NOTE: The line should be terminated at both ends in its characteristic impedance. Stub lengths off the main line should be kept as short as
possible.
(lExAs
,If
INSTRIJMENTS
POST OFFICE BOX 655303 • DAllAS. TEXAS 75266
2--625
2-626
SN65ALS176, SN75ALS176, SN75ALS176A, SN75ALS176B
DIFFERENTIAL BUS TRANSCEIVERS
AUGUST 1987 - REVISED AUGUST 1991
SLLS040D-
•
Meets EIA Standards RS-422A and RS-485
and CCITT Recommendations V.11 and X.27
•
Designed and Tested for Data Rates up to
35MBaud
~D8
•
SN65ALS176 Operating Temperature -40·C
to 85·C
•
Three Skew Limits Available:
'ALS176 ••• 10 ns
'ALS176A ••• 7.5 ns
'ALS176B ... 5 ns
2
7
Vee
B
3
4
6
5
A
GND
DRIVER
Designed for Multipoint Transmission on
Long Bus Lines in Noisy Environments
•
Low Supply Current Requirements
30 mA Max
•
Wide Positive and Negative Input/Output
Bus Voltage Ranges
•
Thermal Shutdown Protection
•
Driver Positive and Negative Current
Limiting
•
RE
DE
D
Function Tables
•
•
•
D OR P PACKAGE
(TOP VIEW)
INPUT
D
H
L
X
ENABLE
DE
H
H
L
OUTPUTS
B
A
H
L
H
L
Z
Z
RECEIVER
DIFFERENTIAL INPUTS
A-B
VIO,,0.2V
-0.2 V < VIO< 0.2V
VlDs-O.2V
X
Inputs open
H =high level, L
X irrelevant, Z
Receiver Input Hysteresis
=
Glitch-Free Power-Up and Power-Down
Protection
ENABLE
RE
L
L
L
H
L
OUTPUT
R
H
?
L
Z
H
=low level, ? =Indeterminate,
=high impedance (off)
AVAILABLE OPTIONS
PACKAGE
Receiver Open-Circuit Fail-Safe Design
tsk(LIM)*
SMALL OUTLINE
(O)t
PLASTICOIP
(P)
ooe
10
SN75ALS1760
to
70 0 e
_40 oe
7.5
5
SN75ALS176P
SN75ALS176AP
to
10
TA
description
The SN65ALS176 and SN75ALS176 series
differential bus transceivers are monolithic
integrated circuits designed for bidirectional data
communication on multipoint bus transmission
lines. They are designed for balanced transmission lines and meet EIA Standards RS-422-A
and RS-485 and CCITT recommendations V.11
and X.27.
SN75ALS176AO
SN75ALS176BO
SN65ALS1760
SN75ALS176BP
SN65ALS176P
B5°e
t The 0 package is available taped and reeled. Add the suffix R to
the device type, (e.g., SN75ALS1760R).
:I: tsk(LlM) is the greater of 1) the difference between the maximum
and minimum specified values of tpLH (or tdOH), and 2) the
The SN65ALS176 and SN75ALS176 series
difference between the maximum and minimum specified values
combine a 3-state differential line driver and a
of tpHL (or tdoLl. This is the maximum range that the driver or
differential input line receiver, both of which
receiver delay time will vary over temperature, Vee, and device to
operate from a Single 5-V power supply. The driver
device.
and receiver have active-high and active-low enables, respectively, which can be externally connected together
to function as a direction control. The driver differential outputs and the receiver differential inputs are connected
internally to form a differential input/output (I/O bus port that is designed to offer minimum loading to the bus
whenever the driver is disabled or Vee =O. This port features wide positive and negative com mon-mode voltage
ranges making the device suitable for party-line applications.
The SN65ALS176 is characterized for operation from -40·C to 85·C, and the SN75ALS176 series is
characterized for operation from O·C to 70·C.
1ExAs
~
Copyright © 1991, Texas Instruments Incorporated
INSIRUMENTS
POST OFFICE BOX 6S5300 • DALLAS, TEXAS 75265
2-627
SN65ALS176,SN75ALS176,SN75ALS176A,SN75ALS176B
DIFFERENTIAL BUS TRANSCEIVERS
SLLS040D- 03042, AUGUST 1987 - REVISED AUGUST 1991
logic symbol t
logic diagram (positive logic)
3
DE
RE _2_--Uf
DE ...,:3=----_-,
6
4
D ---I
7
D
~~~~--rt+'~B
R
4
A
RE ...;2,,--_-,
--'-1
R
-'--c
........_+-.....~~6_
J}-+-_~.-:-7_
......
}
:
Bus
t This symbol Is In accordance with ANSVIEEE SId 91-1984
and IEC Publication 617-12.
schematics of inputs and outputs
EQUIVALENT OF EACH INPUT
Vec--~~----
TYPICAL OF A AND B I/O PORTS
TYPICAL OF RECEIVER OUTPUT
Vee ............- - - - - - - 4...
850 Vee
180kO
NOM
Req
...... NOM
.--
I Connected
I
Input
I
I
I
Driver Input: Req = 3 kO NOM
Enable Inputs: Req 8 kO NOM
=
onA Port
AorB
18kO
NOM
I
I
I
I
I 180kO
NOM
Connected
on B Port
. 1ExAs'"
3kO
NOM
Output
1.1 kO
NOM
INSIRUMENTS
2~28
POST OFFICE BOX 655303 • OAUAS, TEXAS 75265
SN65ALS176,SN75ALS176,SN75ALS176A,SN75ALS176B
DIFFERENTIAL BUS TRANSCEIVERS
SLLS040D - D3042, AUGUST 1987 - REVISED AUGUST 1991
absolute maximum ratings over operating free-alr temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) , .... , •... " .. " .......•....•................................ 7 V
Voltage range at any bus terminal ............... ,., ...... , ....... ,................... -7 V to 12 V
Enable input voltage ....................................................................... 5.5 V
Continuous total power dissipation ... , .•.....• ,., ......••... ,.......... See Dissipation Rating Table
Operating free-air temperature range, TA: SN65ALS 176 ...•.. , ...... " ...•.••.•..• ,',. -40°C to 85°C
SN75ALS176 series ..... , ..... , ....... ,....... O°C to 70°C
Storage temperature range " ..... , ......................... , ............ " ..... ,' -65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds ." ........ ,................... 260°C
NOTE 1: All voltage values, except differential I/O bus voltage, are with respect to network ground teoninal.
DISSIPATION RATING TABLE
PACKAGE
D
p
TA",2S'C
POWER RATING
72SmW
1000mW
DERATING FACTOR
ABOVE TA = 25'C
5.8mWrC
8.0mWrC
TA=70'C
POWER RATING
464mW
640mW
TA=8S'C
POWER RATING
377mW
520mW
recommended operating conditions
Supply voltage, VCC
MIN
NOM
MAX
UNIT
4.75
5
S.25
V
12
Input voltage at any bus terminal (separately or common mode), VI or VIC
-7
Hlgh-Ieval input voltage, VIH
D, DE,and RE
Low-level input voltage, VIL
D, DE,and RE
2
High-level output current, IOH
Low-level output current, IOL
Operating free-air temperature, TA
V
0.8
Differential input voltaga, VID (see Nota 2)
Driver
Receiver
Driver
V
-60
mA
-400
!.LA
8
SN65ALS176
-40
V
:t:12
60
Receiver
V
85
mA
DC
SN75ALS176
0
70
NOTE 2: Differential-Input/output bus voltage is measured at the noninverting terminal A with respect to the inverting terminal B.
1ExAs
~
INSlRUMENTS
POST OFFICE BOX 6SS3OO • DAU..AS, TEXAS 75285
2-629
SN65ALS176, SN75ALS176, SN75ALS176A; SN75ALS176B
DIFFERENTIAL BUS TRANSCEIVERS
SLlS040D - 03042, AUGUST 1987 - REVISED AUGUST 1991
DRIVER SECTION
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature range (unless otherwise noted)
PARAMETER
TEST CONDITlONSt
VIK
Input clamp voltage
11=-18mA
Vo
Output voltage
10=0
I V ODll
Differential output voltage
10=0
MIN
TYP*
°
1.5
RL=1000,
See Figure 1
1/2VO~1
or2
RL=540,
See Figure 1
1.5
Vtest =-7Vto 12V.
See Figure 2
1.5
MAX
V
6
V
6
V
V
I V OD21
Differential output voltage
VOD3
Differential output voltage
AIVODI
Change in magnitude of differential
output voltage §
VOC
Common-mode output voltage
AIVocl
Change in magnitude of
common-mode output voltage§
10
Output current
Outputs disabled,
See Note 3
IIH
High-level input current
VI=2.4V
20
IlL
Low-level input current
VI =0.4V
-400
lOS
Short-circuit output current
RL = 540 or 100 0,
2.5
See Figure 1
5
V
5
V
",0.2
V
3
-1
V
",0.2
V
IVo= 12V
1
I VO=-7V
-0.8
VO=-4V
I SN65ALS176
VO=-6V
I SN75ALS176
UNIT
-1.5
mA
t.oA
t.oA
-250
-150
VO=O
VO=VCC
mA
250
VO=8V
ICC
Supply current
No load
I Outputs enabled
23
30
I Outputs disabled
19
26
mA
t The power-off measurement in EIA Standard RS-422-A applies to disabled outputs only and is not applied to combined inputs and outputs.
'" All typical values are at VCC = 5 V and TA = 25°C.
§ A I VOD I and A I VOC I are the changes in magnitude of VOD and VOC, respectively, that occur when the input Is changed from one logic state
to the other.
'I The minimum VOD2 with a 100-0 load is either 1/2 VODl or 2 V, whichever is greater.
NOTE 3: This applies for both power on and power off; refer to EIA standard R8-485 for exact conditions. The RS-422-A limit does not apply for
a combined driver and receiver terminal.
1ExAs ."
INSIRlJMENTS
2-630
f'OST OFFICE BOX 6515303 • DAUAS, TEXAS 75265
SN65ALS176,SN75ALS176,SN75ALS176A,SN75ALS176B
DIFFERENTIAL BUS TRANSCEIVERS
SLLS040D - 03042. AUGUST 1987 - REVISED AUGUST 1991
switching characteristics over recommended ranges of supply voltage and operating free-air
'
temperature
SN65ALS176
PARAMETER
TEST CONDITIONS
IdO
Differential outpul delay time
tskCDI
Pulse skew
ttO
Differential outpul transition time
tpZH
Oulpul enable time to high level
RL= 1100.
CL=50pF.
tpZL
Oulpul enable time to low level
RL= 1100.
tpHZ
Oulput disable time from high level
RL= 1100.
tpLZ
Oulput disable time from low level
RL=1100.
(I idOL - tdOH I )
TYPT
MAX
UNIT
15
ns
2
ns
See Figure 4
80
ns
CL=50pF.
See Figure 5
30
ns
CL=50pF.
See Figure 4
50
ns
CL= 50 pF.
See Figure 5
30
ns
CL=50pF.
RL=540.
MIN
See Figure 3
0
8
ns
SN75ALS176, SN75ALS176A, SN75ALS176B
PARAMETER
TEST CONDITIONS
MIN
TYPT
MAX
3
8
13
4
7
11.5
5
8
10
0
2
ns
50
ns
ns
'ALS176
tdO
Differential oulput delay time
'ALS176A
'ALS1768
(I idOL -
RL=540.
CL = 50 pF.
See Figure 3
tdOH I )
UNIT
ns
tsk(p)
Pulse skew
tTD
Differential oulput transition time
tpZH
Oulput enable time to high level
RL=1100.
CL=50pF.
See Figure 4
tpZL
Oulput enable time to low level
RL=1100.
CL= 50 pF.
See Figure 5
14
20
tPHZ
Oulput disable time from high level
RL=1100.
eL = 50 pF.
See Figure 4
20
35
ns
tpLZ
Oulpul disable time from low level
RL= 110 O.
CL=50pF.
See Figure 5
8
17
ns
8
23
ns
t All typical values are at Vee = 5 V. TA = 25°e.
SYMBOL EQUIVALENTS
DATA SHEET PARAMETER
R8-422-A
RS-485
Vo
Voa.Vob
Voa.Vob
I V OOll
Vo
Vo
I V o021
VtlRL = 100 0)
Vt (RL=540)
Vt (Test Termination
Measurement 2)
I V o031
dlVool
II Vt
1-1 Vtli
IIVt 1-IVtll
VOC
IVos I
IVosl
dlVocl
IVos-Vos I
IVos-Vos I
lOS
lisa I. I Isb I
10
llxa I. Ilxb I
lia.l·b
TEXAS'" ,
INSIRUMENTS
POST OFFICE BOX 655303 • DAUAS. TEXAS 75265
2-631
SN65ALS176,SN75ALS176,SN75ALS176A,SN75ALS176B
DIFFERENTIAL BUS TRANSCEIVERS
SLLS040D - D3042, AUGUST 1987 - REVISED AUGUST 1991
RECEIVER SECTION
electrical characteristics over recommended ranges of common-mode input voltage, supply
voltage, and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYpt
MAX
UNIT
Vr+
Vr-
Posftive-golng threshold voltage
Vo = 2.7 V,
IO=-0.4mA
Negative-going threshold voltage
Vo = 0.5 V,
10=8mA
Vhys
Hysteresis (Vr + -
VIK
Enable-Input clamp voltage
11=-18mA
VOH
High-level output voltage
VIO=200mV,
See Figure 6
IOH = -400 ,.A.
VOL
Low-level output voltage
VIO = -200 mV,
See Figure 6
IOL=8mA,
10Z
Hlgh-impedance-state output current
VO=0.4Vt02.4V
VI
Una input current
Other input = 0 V, I VI = 12 V
See Note 4
IVI=-7V
IIH
High-level-enable input current
VIH=2.7V
20
IlL
Low-level-enable Input current
VIL=0.4V
-100
JAA
JAA
-85
mA
0.2
-0.2'1'
Vr -l
60
Ii
Input resistance
lOS
Short-circuit output current
VIO=200mV,
ICC
Supply current
No load
mV
-1.5
2.7
0.45
1
-0.8
12
V
V
.,20
VO",O
V
V
JAA
mA
kQ
20
-15
V
I Outputs enabled
23
30
I Outputs disabled
19
26
mA
t All typical values are at VCC = 5 V, TA = 25°C.
*
The algebraic convention, in which the less-positive (more negalive) limit Is designated minimum, is used In this data sheet for common-mode
input voltage and threshold voltage levels only.
NOTE 4: This applies for both powar on and power off. Refer to EIA Standard RS-485 for exact conditions.
switching characteristics over recommended ranges of supply voHage and operating free-air
temperature
SN65ALS176
PARAMETER
TEST CONOITIONS
tpd
Propagation time
tskJI>L
Pulse skew
tpZH
tpZL
tpHZ
Output disable time from high level
tpLZ
Output disable time from low level
MIN
TYpt
MAX
UNIT
25
ns
0
2
ns
Output enable time to high level
11
18
ns
Output enable time to low level
11
18
ns
50
ns
30
ns
(I tpHL -tPLH I)
VIO =-1.5 Vto 1.5 V, CL = 15 pF, See Figure 7
See Figure 8
CL=15pF,
SN75ALS176, SN75ALS176A, SN75ALS176B
PARAMETER
TEST CONOITIONS
'ALS176
tpd
Propagation time
'ALS176A
'ALS176B
t
(I tpHL -
VIO =-1.5 Vto 1.5 V, CL = 15 pF,
See Figure 7
1)
MIN
TYpt
MAX
9
14
19
10.5
14
18
11.5
13
16.5
UNIT
ns
laklp)
Pulse skew
0
2
tpZH
Output enable time to high level
7
14
ns
tpZL
Output enable time to low level
20
35
ns
tpHZ
Output disable time from high level
20
35
ns
tpLZ
Output disable time from low level
8
17
ns
tpLH
CL=15pF,
See Figure 8
All typical values are at Vec = 5 V, TA = 25°C.
1ExAs
.Jf
INSIRUMENIS
24>32
POST OFFICE BOX 655303 • DAUAS, TEXAS 75265
ns
SN65ALS176,SN75ALS176,SN75ALS176A,SN75ALS176B
DIFFERENTIAL BUS TRANSCEIVERS
SLLS0400 - 03042, AUGUST 1987 - REVISED AUGUST 1991
PARAMETER MEASUREMENT INFORMATION
Figure 1. Driver VOD2 and Voe
3750
600
Vtest
3750
1
Figure 2. Driver VOD3
--3V
~
1.5V
1.5V
Input
1
1
Generator
(eeeNoteA)
tdOH
soo
-+i
j4-
1
1
~
ov
I+-
tdOl
190% 90%~- ~2.5V
Output
SO% 1
1 50%
10%/:
1
ttO
14-..
ttO
3V
-.I
TEST CIRCUIT
10%~_2.5V
14-
VOLTAGE WAVEFORMS
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR s 1 MHz, 50% duty cycle, tr s 6 ns, tf
Zo =500.
B. CL includes probe and jig capacttance.
C. !do = tdOH or tdOL
S
6 ns,
Figure 3. Driver Test Circuit and Voltage Waveforms
1ExAs
..If
INSIRUMENTS
POST OFFICE BOX 655303 • DALlAS, TEXAS 75265
2-633
SN65ALS176, SN75ALS176, SN75ALS176A, SN75ALS176B
DIFFERENTIAL BUS TRANSCEIVERS
SLLS0400 - 03042, AUGUST1987 - REVISED AUGUST 1991
PARAMETER MEASUREMENT INFORMATION
Output
Input
OVor3V - - - ' I
CL=SOpF
(see Note B)
General!)!,
(_NoteA)
1
1•5V
1 , 5 V " - - - - 3V
I
T
I
~
V
Output
j"2.3V
_ _-.oJ.
TEST CIRCUIT
tpZH
I
I
:
tpHZ"'"
ov
i.
~I-I"
14-
T
VOH
Voff ~ 0 V
VOLTAGE WAVEFORMS
Figure 4. Driver Test Circuit and Voltage Waeforms
5V
RL=1100
1---0... S1
Output
OVor3V - - - - I
Generator
(see Note A)
CL=SOpF
(see Note B)
T
SOO
TEST CIRCUIT
VOLTAGE WAVEFORMS
Figure 5. Driver Test Circuit and Voltage Waveforms
NOTES: A. The input pulse Is supplied by a generator having the following characteristics: PRR" 1 MHz, 50% duty cycle, Ir " 6 ns, If" 6 ns,
Zo =500.
B. CL includes probe and jig capacitance.
$:[>-{
ff"of ~ L~
Figure 6. Receiver VOH and VOL Test Circuit
1ExAs
2-634
.If
INSIRUMENTS
POST OFACE BOX 655303 • DAUAS, 1EXAS 75265
SN65ALS176,SN75ALS176,SN75ALS176A,SN75ALS176B
DIFFERENTIAL BUS TRANSCEIVERS
SUS040D - 03042, AUGUST 1987 - REVISED AUGUST 1991
PARAMETER MEASUREMENT INFORMATION
~
---3V
Input
Generator
(see Note A)
1.5V
1.5V
I
510
1.5V
I
~-~-l
OV
OV
~I
J.......
tpLH
~,:~~y:
1 1.3V
Output
tpHL
1.3V
VOL
VOLTAGE WAVEFORMS
TEST CIRCUIT
Figure 7. Receiver Test Circuit and Voltage Waveforms
1.5V ~~,-",,---S1
"""0------1
2kO
-1.5V - - 0
T
CL= 15pF
(see Note B)
Generator
(see Note A)
1N916 or Equivalent
5kO
500
~TCIRCUIT
~
---
3V
1
tpZH ~
14-
S2 Open
S3Closed
~
I
r-\..____-_31~5V
=---./
~
Input
OV
I
Output
S1to1.5V
1 1.5 V
Input.
___
1
.
tPZL
---.I 14-
VOH
1.5V
0V
S1 to-1.5V
S2 Closed
S3 Open
1
,----.,,':1" - - - 4.5 V
Output
- - - - OV
VOL
Input
-Cv\---3V
~l'~Y
"---OV
S1 to1.5V
S2Closed
S3Closed
I
~---
nput
1
1
1.5V
3V S1to-1.5V
S2Closed
OV S3Closed
1
tpHZ~
tpHZ~
1
i.--~·
--"""I
' _ _ _...J._ _ _ _ -1.3V
-1.3V
Output
VOLTAGE WAVEFORMS
Figure 8. Receiver Test Circuit and Voltage Waveforms
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR " 1 MHz. 50% duty cycle. tr " 6 ns, tf " 6 ns.
ZO=500.
B. CL includes probe and jig capacitance.
C. tpd = tpLH or tpHL
POST OFFICE BOX 655303 • DAUAS, TEXAS 75265
2-635
SN65ALS176, SN75ALS176, SN75ALS176A, SN75ALS176B
DIFFERENTIAL BUS TRANSCEIVERS
Su..s04OO - 03042. AUGUST 1987 - REVISED AUGUST 1991
TYPICAL CHARACTERISTICS
DRIVER HIGH-LEVEL OUTPUT VOLTAGE
va
DRIVER HIGH-LEVEL. OUTPUT CURRENT
DRIVER LOW-LEVEL OUTPUT CURRENT
5
>I
f
'Q.
!5
'!5
0
~
3.5
3
~
2.5
2
:E
1.5
CI
r--- r-....
4
~
.r:.
5
I
VCC=5V
TA=25°C
4.5
•
DRIVER LOW-LEVEL OUTPUT VOLTAGE
vs
"'"
..........
>I
•
f
'",,
~
'!5
t
0
4
J
3.5
I
I
3
2.5
§
~
I
VCC=5V
TA=25°C
4.5
I
2
-
1.5
:..--- :.,........'
I
..J
I
J:
.p
.p
0.5
o
/'
0.5
o
-20
-40
-60
-SO
-100
10H - High-Level Output Current - mA
o
-120
o
20
SO
100
40
60
IOL - Low-Level Output Current - mA
Figure 9
Figure 10
DRIVER DIFFERENTIAL OUTPUT VOLTAGE
va
DRIVER OUTPUT CURRENT
4
>I
•
J
~
'Q.
!5
'!5
0
iii
I
3.5
3
It
......
VCC=5V
TA=25°C
"-
.........
2.5
2
"-
.......
~ ......
~
1.5
1\
Q
I
\\
Q
.p
0.5
o
o
10
20
30 40 60 60 70 SO
10 - Output Current - mA
Figure 11
1ExA.s . "
INSIRUMENTS
2-636
POST OFFICE BOX 855303 • DAUAS. TEXAS 75265
90 100
120
SN65ALS176,SN75ALS176,SN75ALS176A,SN75ALS176B
DIFFERENTIAL BUS TRANSCEIVERS
SLLS0400 - 03042, AUGUST 1987 - REVISED AUGUST 1991
TYPICAL CHARACTERISTICS
RECEIVER HIGH-LEVEL OUTPUT VOLTAGE
RECEIVER HIGH-LEVEL OUTPUT VOLTAGE
VS
VS
HIGH-LEVEL OUTPUT CURRENT
FREE-AIR TEMPERATURE
5
>
I
III
Ii
=
~
!i
Q.
'S
~
2.5
co
X
>
I
4
3.5
0
5
VIO=0.3V
TA=25·C
4.5
III
co
t-...
...:::: ~
3
VCC=5.25V
'\ ~
1'\ ~
2
1.5
/
I
J:
/1
I
Q.
'S
I
0
~
VCC=5V
)\ ~
VCC=4.75V
-:?
J:.
co
X
'\: ~
3.5
3
2.5
--
2
1.5
I
-:?
0.5
~~
o
4
J:
~~
0.5
o
i'S
VCC=5V
VIO=300mV
IOH = - 440 IlA
4.5
o
-5 -10 -15 -20 -25 -30-35 -40 -45-50
IOH - High-Level Output Current - mA
-40 -20
0
20
40
60
80
100 120
TA - Free-Air Temperature - ·C
Figure 12
Figure 13
RECEIVER LOW-LEVEL OUTPUT VOLTAGE
vs
RECEIVER LOW-LEVEL OUTPUT CURRENT
FREE-AIR TEMPERATURE
0.6
>
I
III
co
I
I
VCC=5V
TA=25·C
0.5 I- VIO =-300 mV
!!
~
'S
Q.
'S
0
i
0.4
V
0.2
-:?
0.1
I
..J
o
0.6
V
./
/
>I
/'
t
~
'S
~
o
./
0.3
l
RECEIVER LOW-LEVEL OUTPUT VOLTAGE
vs
/
/
V
)
I
0.4
0.3
r--
-
0.2
I
..J
-:?
o
~
I
VCC=5V
VIO=-300mA
0.5 IOl=8mA
5
10
15
20
25
tOl - Low-Level Output Current - mA
30
0.1
o
-40 -20
Figure 14
0
20
40
60
80
100
TA - Free-Air Temperature - ·C
120
Figure 15
1ExAs . "
INSIRUMENTS
POST OFFICE BOX 655303 • 0AllAS. TEXAS 75265
2-637
SN65ALS176, SN75ALS176, SN75ALS176A, SN75ALS176B
DIFFERENTIAL BUS TRANSCEIVERS
SLLS040D - D3OO!. AUGUST 1987 - REVISED AUGUST 1991
TYPICAL CHARACTERISTICS
RECEIVER OUTPUT VOLTAGE
RECEIVER OUTPUT VOLTAGE
vs
vs
ENABLE VOLTAGE
ENABLE VOLTAGE
5
6
VID-0.3V
- Load =8 kg to GND I
TA 25°C
VCC .. 5.25V
4
=
>I
3 -
i
2
~
5
VCC .. 4.75V
t....
,.
VCC=4.75V
J
4
i
3
~
2
VCC=5V
-J
~
'--VCC=5V
I
I
~
o
~I
VCC=5.25V
>I
.....
t
!
I
VID=0.3V
Load = 1 kOto VCC
TA = 25°C
o
0.5
1.5
2
VI- Enable Voltage - V
2.5
o
3
,
o
0.5
Figure 16
1.5
2
VI- Enable Voltage - V
2.5
3
Figure 17
APPLICATION INFORMATION
Up to 53
Transceivers
NOTE: The line should be terminated at both ends in its characteristic impedance. Stub lengths off the main line should be kept as short as
possible.
Figure 18. Typical Application Circuit
1ExAs
~
INSIRUMENTS
2-638
POST OFFICE BOX 6515303 • DAllAS. TEXAS 75265
SN55LBC176, SN65LBC176, SN75LBC176
DIFFERENTIAL BUS TRANSCEIVERS
AUGUST 1990- REVISED FEBRUARY 1993
•
•
Bidirectional Transceiver
D, JG, OR P PACKAGE
(TOP VIEW)
Meets EIA Standard RS-485 and
ISO 8482:1987(E)
•
High-Speed Low-Power LlnBICMOS™
Circuitry
•
Designed for High-Speed Operation In Both
.Serial and Parallel Applications
•
Low Skew
•
Designed for Multipoint Transmission on
Long Bus Lines In Noisy Environments
~D8
RE.2
DE 3
D 4
7
6
VCC
B
5
GND
A
Function Tables
•
Very Low Disabled Supply Current
Requirements .•• 200 JA.A Maximum
•
Wide Positive and Negative Input/Output
Bus Voltage Ranges
•
Driver Output Capacity ••• ±60 mA
•
Thermal Shutdown Protection
•
Driver Positive and Negative Current
Limiting
•
•
•
Open-Clrcult Fail-Safe Receiver Design
•
Operates From a Single SoV Supply
•
Glitch-Free Power-Up and Power-Down
Protection
Receiver Input Sensitivity ••• ±200 mV Max
DRIVER
INPUT
D
H
L
X
ENABLE
DE
H
H
L
OUTPUTS
A
B
H
L
H
L
Z
Z
RECEIVER
DIFFERENTIAL INPUTS
A-B
VIO"O.2V
-O.2V
tpLH
Propagation time. low-to-high-Ievel
single-ended output
tpHL
Propagation time. high-to-Iow-Ievel
single-ended output
MIN
MAX
MIN
8
31
8
6
RL=540,
See Figure 3
SN65LBC176
SN75LBC176
eL =50pF.
TYpt
UNIT
MAX
6
ns
ns
26
ns
26
ns
25
0
tPZH
Output enable time to high level
RL= 1100.
See Figure 4
65
60
ns
tpZL
Output enable time to low level
RL= 1100.
See FigureS
65
60
ns
tpHZ
Output disable time from high level
RL= 1100.
See Figure 4
105
60
ns
tpLZ
Output disable time from low level
RL= 1100.
See FigureS
105
60
ns
t All typical values are at Vee = 5 V. TA = 25°e.
SYMBOL EQUIVALENTS
DATA SHEET PARAMETER
RS-485
Vo
Vea. Vob
I Voo11
Vo
I VOD21
Vt (RL= 54 a)
I V OD31
Vt (Test Termination
Measurement 2)
alVODI
II Vt
1-1 Vt II
Voe
IVosl
alVoel
IVos-Vos I
lOS
10
lia, lib
ThxAs " ,
INSIRUMENTS
POST OFFICE BOX 655303 • DAUAS. TEXAS 75265
2~43
SN55LBC176, SN65LBC176, SN75LBC176
DIFFERENTIAL BUS TRANSCEIVERS
SU.8067B - 03502, AUGUST 1990 - REVISED FEBRUARY 1993
RECEIVER SECTION
electrical characteristics over recommended ranges of common-mode input voltage, supply
voltage, and operating free-air temperature (unless otherwise noted)
MIN TYPt
PARAMETER
UNIT
TEST CONDITIONS
MAX
0.2
V
VO=2.7V,
10 =-0.4 rnA
Vr+ Positive-going threshold voRage
V
VO=0.5V,
10=8mA
-0.2*
Vr- Negative-going threshold voltage
Hysteresis (V-r +- Vr -l
50
mV
Vhys
(see Figure 4)
VIK
Enable-input clamp voltage
11=-18mA
VOH
High-level output voltage
VIO=200mV,
See Figure 6
10H = -4OO,.A.
VOL
Low-level output voltage
Vlo=200mV,
See Figure 6
10l= 8 rnA,
10Z
High-impedance-state output
current
VO= 0.4Vt02.4 V
II
Une Input current
Other input = 0 V,
See Note 5
-1.5
2.7
V
0.45
V
,.20
!AA
VI=12V
1
VI=-7V
-0.8
IIH
High-level enable-input current
VIH=2.7V
20
IlL
Low-level enable-input current
VIL=0.4V
-100
ri
Input resistance
ICC
Supply current
3.9
SN55lBC176
Receiver and
driver disabled
rnA
!AA
!AA
kO
12
Receiver enabled
and driver disabled
VI=OorVCC,
No load
V
rnA
0.25
SN65LBC176
0.2
SN75lBC176
rnA
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, CL 15 pF
=
PARAMETER
tplH
tpHl
TEST CONOITIONS
SN55LBC176
Propagation time, low-to-high-Ievel
Single-ended output
Propagation time, high-to-Iow-Ievel
slngle-ended output
VIO =-1.5 Vto 1.5 V,
See Figure 7
SN65LBC176
SN75LBC176
TYpt
UNIT
MIN
MAX
MIN
MAX
20
37
20
30
ns
20
55
28
45
ns
tSIill»
Pulse skew (I !dOH -!dOL Il
22
18
ns
tpZH
Output enable time to high level
34
30
ns
tpZl
Output enable time to low level
34
30
ns
tpHZ
Output disable time from high level
34
30
ns
tpLZ
Output disable time from low level
34
30
ns
See Figure 8
See Figure 8
10
t All typIcal values are at VCC = 5 V, TA = 25°C.
* The algebraic convention, in which the less-positive (more-negative) limit is designated minimum, is used in this data sheet for common-mode
input voltage and threshold voltage levels only.
NOTE 5: This applies for both power on and power off. Refer to EIA Standard RS-485 for exact conditions.
1ExAs
.Jf
INSIRUMENIS
2~44
POST OFFICE BOX 655303 • DAl.IJ
EN
5
}r
"V
6
"V
A
Y
B
A
B
T
3
8
7
2
8
Y
7
Z
Z
T
"V
SN75178B
SN75178B
EN
3
EN
t>
"- EN
5
}r
"
"V
y
6
Y
Z
Z
"V
...
A
B
T
t These symbols are in accordance with ANSI/IEEE SId 91-1984 and
lEe Publication 617-12.
schematics of inputs and outputs
TYPICAL OF ALL DRIVER OUTPUTS
EQUIVALENT OF EACH INPUT
VCC----
- - - - - - - _ - - VCC
Req
Input
Output
Driver Input: Req
=3 kQ NOM
-
-
- - ....- -.....- - GND
Enable inputs: Req = 8 kc NOM
EQUIVALENT OF EACH RECEIVER INPUT
TYPICAL OF RECEIVER OUTPUT
VCC ---------+-
500
1.5V---u.~
CL=15pF
(see Note B)
I
Input
Output
~
1.5V
1.5V
I
I
tpLH ~
I
I
OV
r---t-
tpHL
~
1.3V
1.3V
I---VOH
Output
VOL
TEST CIRCUIT
VOLTAGE WAVEFORMS
Figure 6. Receiver Propagation Delay Times
Output
1.5V
-1.5V--o
Tt CL= 15 pF
+
(see Note C)
5kO
(see Note B)
Generator
(see NomA)
=x
(SN75177B)
500
TEST CIRCUIT
L___X]
Input
(SN75178B)
1.5 V
-
S3 Closed
I
~
'------'-
~
1.5 V
(SN7517BB)
OV
~~ -
0.5 V
-f--
S2 Closed
S3 Open
OV
r---V -:_-: -
4.5 V
Output
~ VOL
---.l
- 0V
(SN75177B)
Input
52 Closed
O~ Closed
:J(
1.5 V
(SN7517BB)
~ 3S~to_l'5V
: '--_ _....
S2 Closed
:~ Closed
I
tpHZ~
Output
1.5 V
tpZL
~ 3S~tOl'5V
: ~___
I
I
L ~~tO-l'5V
'---- I
-! r
~VOH
Output
Input
J(
Input
(SN7517BB)
-I I-
tPZH
(SN75177B)
(SN75177B)
Sl:O~'5V
S2 Open
tpLZ~
~---
,..---VOH
Output - - - ' " " 0.5V
-1.3V
-1.3V
""VOL
VOLTAGE WAVEFORMS
Figure 7. Receiver Output Enable and Disable Times
NOTES: A. The input pulse is supplied by a generalor having Ihe following characteristics: PRR '" 1 MHz, 50% duty cycle, Ir '" 6 ns, If S 6 ns,
ZO=50n
B. CL includes probe and jig capacitance.
C. All diodes are 1N916 or eq\livalent.
1ExAs
~
INSlRUMENI'S
POST OFFICE BOX 655303 • DAU.AS, TEXAS 75265
:HI55
SN75177B, SN75178B
DIFFERENTIAL BUS REPEATERS
Su.sOO2C- D2606. JULY 1985 - REVISED FEBRUARY 1993
TYPICAL CHARACTERISTIPS
DRIVER HIGH-LEVEL OUTPUT VOLTAGE
DRIVER LOW-LEVEL OUTPUT VOLTAGE
va
va
HIGH-LEVEL OUTPUT CURRENT
LOW-LEVEL OUTPUT CURRENT
5
5
VCC=5V
TA=25"C -
4.5
>I
J
~
1
5
0
---
4
II
3.5
3
!
I
~~
...........
:f
1.5
r-.....
,
.c
CI
>
4
II
""-.
2.5
2
VCC=5V
4.5 r-TA=25°C
f
1
5
0
~
2
:J:
I
:J:
:J:
.p
1.5
,........
.p
0.5
o
0.5
o
-20
-40
-60
-80
"';'100
o
-120
10H - High-Level Output Current - RIA
o
---
20
40
I
5
~
'iii
J
va
5
I
VCC=5V
VCC=5V
TA = 25°C
r--....
.........
>I
t
i
o
~
~ .........
"
1.5
I
\
i3
I
9
": 111111111\
10
20
30
40
50
60
70
80
TA=25°C
VIC =
OV
VIC =
12V
II
90 100
~
4
VIC =
-12V
3
I
VTVT+
VT-
I
II
I
I
I
I
I
VTVT+
2
I
VT+
I
:11111111111111
-125 -100 -75 -50 -25
10 - Output Current - RIA
Figure 10
2--656
10=0
-
........ ~
2
120
RECEIVER OUTPUT VOLTAGE
DIFFERENTIAL INPUT VOLTAGE
2.5
o
100
DRIVER OUTPUT CURRENT
I
3
80
va
4
.........
60
Figure 9
DRIVER DIFFERENTIAL OUTPUT VOLTAGE
3.5
--"
10H - LOW-Level Output Current - rnA
Figures
~
I
I
II
3
2.5
!iP
I
I
3.5
0
25
Figure 11
POST OFFICE BOX 655303 • DAUAS, TEXAS 75265
50
75 100 125
VIO - Oifferentiallnput Voltage - mV
SN75177B, SN75178B
DIFFERENTIAL BUS REPEATERS
SLLSOO2C - 02606. JULY 1985 - REV1SED FEBRUARY 1993
TYPICAL CHARACTERISTICS
RECEIVER HIGH-LEVEL OUTPUT VOLTAGE
>
I
t
RECEIVER HIGH-LEVEL OUTPUT VOLTAGE
VB
VB
HIGH-LEVEL OUTPUT CURRENT
FREE-AIR TEMPERATURE
5 ~----~--~~--~----~-----,
VIO=O.2V
TA=25·C
4 ~----~--~~---4-----+-----1
5
,
>I
III
~
i
~
5Q,
5
3
3
-
0
2
I----+-N~
~
2
ao
:f
I
4
~
ao
:r
~
VCC=5V
VIO=200mV
IOH = -440 r.tA
:f
I
:r
~
1~----,~--~--';~nf-----+-----1
-10
-20
-30
-40
o
-SO
o
10
20
Figure 12
VS
./
V
II
0
0.3
5Q,
5
I
I
oJ
~
0.2
/
V
/
>
I
""'"
VCC=5V
VIO=-200mV
0.5 I-IOL=8mA
III
ao
/'
/
:!
~
5Q,
5
0.4
0
0.3
~~
0.2
i--
.3
I
oJ
~
o
80
0.6
/'
0.1
o
70
RECEIVER LOW-LEVEL OUTPUT VOLTAGE
FREE-AIR TEMPERATURE
0.5
0.4
60
LOW-LEVEL OUTPUT CURRENT
VCC=5V
TA=25·C
f
SO
VB
0.6
I
40
Figure 13
RECEIVER LOW-LEVEL OUTPUT VOLTAGE
>
30
TA - Free-Air Temperature _·C
IOH - High-Level Output Current - mA
5
10
15
20
25
30
0.1
o
-40 -20
IOL - Low-Level Output Current - mA
Figure 14
0
20
40
60
80
100
120
TA - Free-Air Temperature _·C
Figure 15
POST OFFICE BOX 655303 • DAUAS. TEXAS 75265
2-657
SN75177B, SN75178B
DIFFERENTIAL BUS REPEATERS
SL1.S002C-D2606, JULY 1985-REVISED FEBRUARY 1993
APPLICATION INFORMATION
1/2 SN75179B
1/2 SN75179B
SN75176B
SN75176B
RT
SN75178B
SN75176B
NOTE: The line should be terminated at both ends In Its characteristic impedance. Stub lengths off the main line should be kept as short as
possible.
Figure 16. Typical Application Circuit
1ExAs
..If
INSIRUMENIS
2~58
POST OFFICE BOX 655303 • DAUAS, TEXAS 75265
SN75179A
DIFFERENTIAL DRIVER AND RECEIVER PAIR
SUSl238 -
• Meets EIA Standards RS-422A, RS423A,
and CCITT Recommendations Y.11 and X.27
•
•
•
•
•
Bus Voltage Range .•. -7 Vto 12 V
Positive and Negative Current Umltlng
Driver Output Capability .•• 60 mA Max
Driver Thermal Shutdown Protection
Receiver Input Impedance ... 12 kQ Min
•
•
•
•
Receiver Input Sensitivity ••• ±200 mV
Receiver Input Hysteresis ••• 50 mV Typ
Operates From Single SOV Supply
Low Power Requirements
- REVISED FEBRUARY 1993
0 OR P PACKAGE
(TOP VIEW)
VCC[JB A
R
2
7
B
D
GND
3
6
4
5
Z
Y
NOT RECOMMENDED FOR NEW DESIGN
logic symbol
description
The SN75179A driver and bus receiver circuit is a
monolithic integrated device deSigned for
balanced transmission line applications, and
meets EIA Standards RS-422A, RS-423A, and
CCITT Recommendations V.11 and X.27. It is
deSigned to Improve the performance of data
communications over long bus lines.
R
o
<3
2
E[
8
.....,
6
I>
3
7
5
A
a
z
y
logic diagram
The SN75179A features positive- and negativecurrent limiting for the driver and receiver. The
receiver features high input impedance, input
hysteresis for increased noise immunity, and input
sensitivity of ±200 mVover a common-mode input
voltage range of -12 Vto 12 V.
R
0
~ za
~
A
y
The driver provides thermal shutdown for
protection from line fault conditions. Thermal
shutdown is designed to occur at a junction
temperature of approximately 150·C. The device
is designed to drive current loads of up to 60 mA
maximum.
The SN75179A is characterized for operation
from O·C to 70·C.
Function Tables
RECEIVER
DRIVER
INPUT
OUTPUTS
,0
Y
Z
H
H
L
L
L
H
H = high level,
L = low level,
DIFFERENTIAL INPUTS
A-a
OUTPUT
R
VID20.2V
-0.2 V < VID < 0.2 v
VIO" -0.2V
H
?
L
? = indeterminate
Copyright © 1993, Texas Instruments Incorporated
TEXAS . "
INSJRUMENJS
POST OFFICE BOX 655303 • DAUAS, TEXAS 75265
2-Q;9
SN75179A
DIFFERENTIAL DRIVER AND .RECEIVER PAIR
SL1.S123B -02845. JUNE 1984 - REVISED FEBRUARY 1993
schematics of inputs and outputs
EQUIVALENT DRIVER OR ENABLE INPUT
TYPICAL OF ALL DRIVER OUTPUTS
VCC---.-
- - - - ---.---VCC
Input
Output
=
- - - - -+--_-- GND
Driver Input: Req 3 kg NOM
Enable Inputs: Req 8 kg NOM
=
EQUIVALENT OF EACH RECEIVER INPUT
VCC _ _ _ _ _ _>----..t__-- _ _
TYPICAL OF ALL RECEIVER OUTPUTS
--~--VCC
asg
~/_ _...
NOM
960g
NOM
Input-:;-;;~;::--1-_-I-_ _ _ _
_
Output
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) ................................•............................ 7 V
Voltage range at any bus terminal ................................................... -1 D V to 15 V
Differential input voltage (see Note 2) ....................................................... :t:25 V
Continuous total dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. See Dissipation Rating Table
Operating free-air temperature range .................................................. DOC to 7DoC
NOTES: 1. All voltage values. except differential input vn!tage, are wtth respect to' net'l''!ork ground terminal.
2. Differential-input voltage is measured at the noninverting input with respect to the corresponding inverting input.
DISSIPATION RATING TABLE
TAS25·C
POWER RATING
DERATING FACTOR
ABOVE TA 25·C
o
725mW
5.8mwrc
464mW
p
1000mW
8.0mWrC
640mW
PACKAGE
=
. 1ExAs'"
2~60
INSIRUMENTS
POST OFFiCE BOX 655303 • OAUAS. TEXAS 75265
TA=70·C
POWER RATING
SN75179A
DIFFERENTIAL DRIVER AND RECEIVER PAIR
SLLS123B - 02845. JUNE 1984 - REVISED FEBRUARY 1993
recommended operating conditions
Supply voltage. VCC
High-level input voltage. VIH
Driver
Low-level input voltage. VIL
Driver
MIN
NOM
MAX
UNIT
4.5
5
5.25
V
2
V
-7t
Common-mode input voltage. VIC
Differential input voltage. VID
Driver
High-level output current. 10H
Receiver
Receiver
Operating free-air temperature. TA
V
12
V
",12
V
-60
rnA
-400
jJA
60
Driver
Low-level output current. 10L
0.8
8
. ..
70
0
..
rnA
·C
t The algebrBlc convention. where the less-positIVe (more-negative) hmit IS designated minimum. IS used In this data sheet for common-mode Input
voltage and threshold voltage.
DRIVER SECTION
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Input clamp voHage
11=-18mA
VOH
High-level output voHage
VIH=2V.
IOH=-33mA
VIL=0.8 V.
VOL
Low-level output voltage
VIH =2V.
10H =33mA
VIL= 0.8V.
1'10011
Differential output voltage
10=0
VIK
IV OD21
Differential output voltage
AiVoDI
Change In magnitude of differential
output voHage§
MIN
TYP*
MAX
UNIT
-1.5
V
3.7
V
1.1
V
2VOD2
RL=100Q.
See Figure 13
2
2.7
RL= 54 0-
See Figure 13
1.5
2.4
V
V
",0.2
V
3
V
",0.2
V
VOC
Common-mode output voltage 1l
AIVoci
Change in magnitude of
common-mode output voltage§
10
Output current with power off
VCC=O.
",100
jJA
IIH
High-level input current
VI =2.4V
20
jJA
IlL
Low-level input current
VI =0.4V
-400
jJA
VO=-7V
-250
lOS
ICC
Short-circuit output current
Supply current (total package)
See Figure 13
RL = 54 Qor 100 Q.
VO=-7Vt012V
VO=VCC
250
VO=12V
500
No load
50
rnA
rnA
* All typical values are at VCC = 5 V and TA = 25·C.
§ AIVODI and AIVocl are the changes in magnitude of VOD and VOC. respectively. that occur when the input Is changed from a high level to a
low level.
11 In EIA Standard RS-422A. Voc. which is the average of the two output voHages with respect to ground. is called output offset voHage. VOS.
switching characteristics, Vee
=5 V, TA =25°C
PARAMETER
tdD
Differential-output delay time
ttD
Differential-output transition time
TEST CONDITIONS
RL=60Q.
1ExAs
See Figure 3
MIN
TYP
MAX
40
60
UNIT
ns
65
95
ns
~
INSIRUMENTS
POST OFFICE
eox 655303 •
DAUAS. TEXAS 75265
2-661
SN75179A
DIFFERENTIAL DRIVER AND RECEIVER PAIR
SLLSl23B - 02845, JUNE 1984 - REVISED FEBRUARY 1993
RECEIVER SECTION
electrical characteristics over recommended ranges of common-mode Input voltage, supply
voltage, and operating free-alr temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
VT+
VT-
Positive-going threshold voltage
VO=2.7V,
10=-0.4mA
Negative-going threshold voltage
VO=0.5V,
10·SmA
Vhys
HystereSiS (VT+ -
VOH
High-level output voltage
VIO= 200mV,
See Figure 2
10H = -400 1lA,
VOL
Low-level output voltage
VIO = -200 mV,
10L",SmA,
Une input current
Other Input at 0 V, I VI = 12 V
See Note 3
IVI=-7V
II
Vr-->
r;
Input resistance
lOS
Short-circuit output current
ICC
Supply current ( total package)
TVPt
MAX
0.2
V
V
-0.2*
See Figure 9
UNIT
mV
50
2.7
V
See Figure 2
0.45
1
-O.S
V
mA
kg
12
-15
No load
-85
mA
50
mA
t All typical values are at VCC • 5 V, TA = 25°C.
* The algebraic convention, where the less-positive (more-negative) limit Is designated minimum, is used in this data sheet for common-mode input
voltage and threshold voltage levels only.
NOTE 3: Refer to EIA Standard RS-422A for exact conditions.
switching characteristics, Vee =5 V, TA =25°C
PARAMETER
TEST CONOITIONS
tPLH
Propagation delay time, low-to-hlgh-Ievel output
tpHL
Propagation delay time, high-to-Iow-Ievel output
VIO =-1.5 Vto 1.5 V,
See Figure 5
CL= 15pF,
1ExAs . "
INSIRUMENTS
POST OFFICE BOX 855303 • DAI..LAS, TEXAS 75266
MIN
TVP
MAX
26
35
UNIT
ns
27
35
ns
SN75179A
DIFFERENTIAL DRIVER AND RECEIVER PAIR
SLLSl23B - 02845, JUNE 1984 - REVISED FEBRUARY 1993
PARAMETER MEASUREMENT INFORMATION
RL
2
~t1t
·:r ~
VOC
JFigure 1. Driver VOD and Voe
j
-IOH
Figure 2. Receiver VOH and VOL
Input
\1~~ 3V
/,1.5 V
1
Generator
(see Note A)
50 0
ov
1
---.l...
tdO ..... -I
I,
~!do
-~2'5V
:r
~
50%
SO%
Output
CL=15pF
(see Note 8)
1
ttO -./ -
TEST CIRCUIT
10%
-
1
~-2.5V
~ttO
VOLTAGE WAVEFORMS
Figure 3. Driver Differential-Output Delay and Transition Times
2.3 V
RL=~O
Output
Generator
(see Note A)
500
TEST CIRCUIT
VOLTAGE WAVEFORMS
Figure 4. Driver Test Circuit and Voltage Waveforms
Input
Generator
(see Note A)
/,1.5
1
Output
500
1.5V
---.l...
tpLH
r -I
V
\1~ ~ 3 V
ov
1
I,
~ tPHL
~
1.3 V
1.3 V
j--VOH
Output
VOL
TEST CIRCUIT
VOLTAGE WAVEFORMS
Figure 5. Receiver Test Circuit and Voltage Waveforms
NOTES: A. The input pulse is supplied by a generator having Ihe following characteristics: PRR = 1 MHz, 50% duty cycle, Ir 0; 6 ns, If 0; 6 ns,
ZO=50n
B. CL includes probe and jig capacHance.
TEXAS
,If
INSIRUMENTS
POST OFFICE BOX 655303 • DALlAS, TEXAS 75265
2--e63
SN75179A
DIFFERENTIAL DRIVER AND RECEIVER PAIR
Su.s123B - 02845. JUNE 1984 - REVISED FEBRUARY 1993
TYPICAL CHARACTERISTICS
DRIVER HIGH-LEVEL OUTPUT VOLTAGE
DRIVER LOW-LEVEL OUTPUT VOLTAGE
va
va
DRIVER HIGH-LEVEL OUTPUT CURRENT
DRIVER LOW-LEVEL OUTPUT CURRENT
5
,
>I
4.5
til
4
S!
3.5
~
3
5
0
1i
2.5
'J.
2
~
~
l:
I
l:
5
VCC=5V
TA=25°C -
VCC=5V
4.5
>
I
r--.; ............
t- TA=25"C
4
til
at
!
3.5
5
3
S!
....................
.........
g
,
r-........
~
§
1.5
I
I
I
II
2.5
2
1.5
I
.p
,...i"'"
oJ
.p
0.5
o
0.5
o
-20
-40
-60
-80
-100
o
-120
o
10H - High-Level Output Current - mA
20
-
r--
........
I
til
S!
5
g
3
VB
DRIVER OUTPUT CURRENT
DIFFERENTIAL INPUT VOLTAGE
........
2.5
iii
~
~
2
,
I
I
VCC=5V
TA = 25°C
'"
r-....
........
........
1.5
5
>I
,
i
I
I
~ ~IIIIIIIII\II
10
20
30
40
50
60
70
80
TA=25°C
VIC =
-12V
VIC =
OV
VIC =
12V
Vr-
Vr-
90 100
I
,..
4
3
vT+
Vr,..
r-
vTVT+
2
~
1
o
-125 -100 -75
10 - Output Current - mA
-Q)
-45
0
25
60
75 100 125
VIO - Oifferentlallnput Voltage - mV
Figure 8
Figure 9
1ExAs ."
INSIRUMENTS
2~64
10=0
VCC=5V
r-
\
o
120
RECEIVER OUTPUT VOLTAGE
VB
4
,
100
80
Figure 7
DRIVER DIFFERENTIAL OUTPUT VOLTAGE
3.5
60
40
10H - Low-Level Output Current - mA
Figure 6
>
--"
POST OFFICE BOX 655303 • DAUAS. TEXAS 75265
SN75179A
DIFFERENTIAL DRIVER AND RECEIVER PAIR
SLLS 123B - 02845. JUNE 1984 - REVISED FEBRUARY 1993
TYPICAL CHARACTERISTICS
RECEIVER HIGH-LEVEL OUTPUT VOLTAGE
VB
HIGH-LEVEL OUTPUT CURRENT
RECEIVER HIGH-LEVEL OUTPUT VOLTAGE
VB
FREE-AIR TEMPERATURE
5
>
I
til
VIO=0.2V
TA=2S·C
4
~--r--~r---;---+---i
I
4
'$
I---I-~~t----
!
I
5:
2
2
.c
01
5:
I
J:
J:
.Jl
.Jl
-20
-10
o
-30
-40
o
-50
10
Figure 10
RECEIVER LOW-LEVEL OUTPUT CURRENT
0.6
0.5
til
0.4
0.3
j
~
0.2
.Jl
0.1
loJ
V
/
V
L
/
/
60
70
80
RECEIVER LOW-LEVEL OUTPUT VOLTAGE
VB
FREE-AIR TEMPERATURE
vs
01
50
Figure 11
RECEIVER LOW-LEVEL OUTPUT VOLTAGE
VCC=5V
TA=2S·C
40
TA - Free-Air Temperature _·C
IOH - High-Level Output Current - rnA
'$
0
a;
30
3
0
01
~
'$
a.
20
1!!
~
'$
a.
I
1!!
I
01
~
>I
-'
til
I
~
>
,I
VCC=5V
VIO=0.2V
IOH = -440 !lA
/
V"
0.6
V
>I
VCC=5V
VIO=-200mV
IOL=8mA
0.5
til
01
as
=
~
'$
a.
'$
0.4
~
0
0.3
I
0.2
.Jl
0.1
loJ
o
o
5
10
15
20
2S
30
o
o
IOL - Low-Level Output Current - rnA
Figure 12
10
20
30
40
50
60
70
TA - Free-Air Temperature _·C
80
Figure 13
TEXAS'"
INSIRUMENTS
POST OFFICE BOX 655303 • DALlAS. TEXAS 75265
2~65
2--{l66
SN65179B, SN75179B
DIFFERENTIAL DRIVER AND RECEIVER PAIR
SLLS123B-
•
Meets EIA Standards RS-422-A, RS-48S and
CCITT Recommendations V.11 and X.27
•
•
•
•
•
•
•
Bus Voltage Range ... -7 V to 12 V
OCTOBER 1985 - REVISED FEBRUARY 1993
D OR P PACKAGE
(TOP VIEW)
VCC(J8 A
Positive and Negative Current Limiting
Driver Output Capability ... 60 mA Max
R
2
7
B
o
3
6
Z
GND
4
5
Y
Driver Thermal Shutdown Protection
Function Tables
Receiver Input Impedance ... 12 kQ Min
DRIVER
Receiver Input Sensitivity ... ±200 mV
INPUT
D
H
L
Receiver Input Hysteresis ••• SO mV Typ
•
Operates From Single S-V Supply
•
Low Power Requirements
OUTPUTS
Y
Z
H
L
L
H
RECEIVER
DIFFERENTIAL INPUTS
A-a
VIO",0.2V
-0.2 V < VID < 0.2 V
VID,,-0.2V
description
The SN65179B and SN75179B differential driver
and receiver pair are monolithic integrated
devices designed for balanced transmission line
applications and meet EIA Standards RS-422-A
and RS-485 and eelTT Recommendations V.11
and X.27. They are designed to improve the
performance of full·duplex data communications
over long bus lines.
The SN65179B and SN75179B driver outputs
provide limiting for both positive and negative
currents. The receiver features high input
impedance, input hysteresis for increased noise
immunity, and input sensitivity of ±200 mVover a
common-mode input voltage range of -7 V to
12 V. The driver provides thermal shutdown for
protection from line fault conditions. Thermal
shutdown is designed to occur at a junction
temperature of approximately 150·e. The
SN65179B and SN75179B are designed to drive
current loads of up to 60 mA maximum.
OUTPUT
R
H
?
L
H =high level. L =low level.
? = indeterminate
logic symbol t
8
:~ Er
5
A
a
Z
Y
tThis symbol is in accordance with ANSI/IEEE SId 91-1984
and IEC Publication 617-12.
logic diagram (positive logic)
The SN65179B is characterized for operation
from -40·e to 85·e. The SN75179B is
characterized for operation from o·e to 70·e.
R
.IT
~
o
3
5
~
8A
2
7
a
6Z
Y
Copyright © 1993. Texas Instruments Incorporated
TEXAS . "
INSIRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
2-667
SN65179B, SN751798
DIFFERENTIAL DRIVER AND RECEIVER PAIR
SLLS123B - 02845, OCTPBER 1985 - REVISED FEBRUARY 1993
schematics of inputs and outputs
EQUIVALENT OF DRIVER INPUT
VCC
Input
TYPICAL OF ALL OUTPUTS
-----+--
- -.......--VCC
~_~--i
Output
......-
.....- - GND
Driver Input: Req = 3 kO NOM
EQUIVALENT OF EACH RECEIVER INPUT
TYPICAL OF ALL RECEIVER OUTPUTS
VCC-----~--.-
9600
NOM
Input
--::'~--1--+16.8kO
NOM
9600
NOM
absolute maximuM ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) ............................................................. 7 V
Voltage range at any bus terminal ................................................... -10 V to 15 V
Differential input voltage (see Note 2) ....................................................... ±25 V
Continuous total dissipation ........................................... See Dissipation Rating Table
Operating free-air temperature range: SN65179B ..................................... -40°C to 85°C
SN751798 ....................................... Cae to 70°C
Storage temperature range ....................................................... -65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds ............................... 260°C
NOTES: 1. All voHage values, except differential input voltage, are with respect to network ground terminal.
2. Differential-input voltage is measured at the noninverting input wHh respect to the corresponding inverting input.
DISSIPATION RATING TABLE
PACKAGE
D
p
TA:s25°C
POWER RATING
DERATING
FACTOR
TA=70°C
POWER RATING
TA = 85°C
POWER RATING
725mW
5.8mWrC
464mW
377mW
1000mW
8.0mWrC
640mW
520mW
1ExAs
..If
INSIRUMENTS
2~68
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
SN65179B, SN75179B
DIFFERENTIAL DRIVER AND RECEIVER PAIR
SLLS123B - 02845, OCTOBER 1985 - REVISED FEBRUARY 1993
recommended operating conditions
Supply voltage, VCC
High-level Input voHage, VIH
Driver
Low-level input voHage, VIL
Driver
MIN
NOM
MAX
UNIT
4.75
5
5.25
V
V
2
-7t
Common-mode input voHage, VIC
Differential input voltage, VID
Driver
High-level output current, 10H
Receiver
Driver
Low-level output current, 10L
V
12
V
",12
V
-60
rnA
-400
JlA
60
Receiver
Operating free-air temperature, TA
0.8
8
SN65179B
-40
85
SN75179B
0
70
rnA
·C
..
..
..
t The algebraiC convention, where the less-posllive (more-negative) limit IS designated minimUm, IS used In this data sheetfor common-mode Input
voHage and threshold voHage.
DRIVER SECTION
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
,
PARAMETER
TEST CONDITIONS
MIN
VIK
Input ciamp voHage
Vo
Output voltage
10=0
0
I V ODll
Differential output voHage
10=0
1.5
I VOD2 I
low-level output voltage
I VOD3 I
Differential output voltage
AIVODI
Change in ma~nitude of common-mode
output voltage
VOC
Common-mode output voltage
AIVocl
Change in ma~nitUde of common-mode
output voltage
RL= 1000,
See Figure 1
RL= 540,
See Figure 1
See Note 3
Output current
VCC =0,
IIH
High-level input current
VI=2.4V
IlL
Low-level input current
lOS
Short-circuit output current
ICC
Supply current (total package)
,MAX
UNIT
-1.5
V
6
V
6
V
1/2Vo,pl
or2
1.5
V
2.5
1.5
RL=5400rl000,
10
*
TYpt
11=-18mA
See Figure 1
VO=-7Vto12V
5
V
5
V
",0.2
V
3
-1
V
",0.2
V
",100
JlA
JlA
JlA
20
VI =0.4V
-200
VO=-7V
-250
250
Vo=VCCor12V
57
No load
70
rnA
rnA
Ail tyPiCal values are at VCC = 5 V and TA = 25·C.
§ AIVODI and AIVocl are the changes in magnitude of VOD and VOC, respeciively, that occur when the input is changed from a high level to a
low level.
.
11 The minimum VOD2 with 100-0 load is either 1/2 VOD2 or 2 V, whichever is greater.
NOTE 3: See EIA Standard RS-485, Figure 3.5, Test Termination Measurement 2.
switching characteristics,
Vee = 5 V, TA = 25°C
PARAMETER
!do
Differential-output delay time
ttD
Differentlal-output transition time
TEST CONDITIONS
See Figure 3
RL=540,
1ExAs
MIN
TYP
MAX
15
22
20
30
UNIT
ns
ns
,If
INSIRUMENTS
POST OFFICE BOX 655303 • DALlAS. TEXAS 75265
2-669
SN65179B, SN75179B
DIFFERENTIAL DRIVER AND RECEIVER PAIR
SUSl23B - 02845. OCTOBER 1985 - REVISED FEBRUARY 1993
Symbol Equivalents
DATA SHEET PARAMETER
RS-422-A
RS-485
Vo
Voa.Vob
Voa.Vob
IVOD11
IVOD21
VO
VdRL= 100 g)
VO
VdRL=54 g)
Vt (Test Termination Measurement 2)
IVOD31
AIVool
IIVt I-IV! II
IIVt I-IV! II
VOC
IVosl
IVosl
AIVocl
IVos-Vosl
IVos-Vosl
lOS
llsal.l lsbl
10
llxal.l lxbl
lia.lib
RECEIVER SECTION
electrical characteristics over recommended ranges of common-mode input voltage, supply
voltage, and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
Vr+
Vr-
PosHive-going Input threshold voltage
VO=2.7V.
10=-0.4mA
Negative-going input threshold voltage
VO=0.5V.
10=8mA
Vhys
Hysteresis (\IT + -
VOH
High-level output voltage
VID=200mV.
10H = -400 flA.
See Figure 2
VOL
Low-level output voltage
VID = -200 mV.
IOL=8mA.
See Figure 2
II
Other Input at 0 V,
Input resistance
Short-circuit output current
ICC
Supply current (total package)
See Note 4
V
mV
2.7
V
0.45
IVI = 12V
1
IVI =-7V
-0.8
V
m~
kg
12
-15
No load
UNIT
V
-0.2*
50
Une input current
lOS
MAX
0.2
Vr~
I'j
TYpt
57
-85
mA
70
mA
t All typical values are at VCC = 5 V, TA = 25°C.
* The algebraic convention. where the less-positive (more-negative) IimH is designated minimum. is used in this data sheet for common-mode Input
voltage and threshold voltage levels only.
NOTE 4: Refer to EIA Standard RS-422A for exact condHions.
switching characteristics, Vee
=5 V, TA =25°C
PARAMETER
TEST CONDITIONS
I-t.:,.P..,L!-I
....-:P~ro.;.;p;.;.ag;:;.at;.;·;.;.lo;.;.n~de;.;.la;;;'!.....tl;.;m;.;.e;.;.l~ow;.;.-.:.:to.....h.;;;ig::;.h;.;.-lev;;.;..;;e;.;1o;.;ut.;;;p..;;.ut~_ _ _-i V:o = -1.5 V to 1.5 V.
tpHL Propagation delay time. high-to-Iow-Ievel output
CL = 15 pF.
See Figure 4
1ExAs ."
INSTRUMENTS
2-670
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
MIN
TYP
MAX
19
35
UNIT
ns
30
40
ns
SN65179B, SN75179B
DIFFERENTIAL DRIVER AND RECEIVER PAIR
SLL.S123B - 02845. OCTOBER 1985 - REVISED FEBRUARY 1993
PARAMETER MEASUREMENT INFORMATION
Figure 1. Driver Voo and Voe
Figure 2. Receiver VOH and VOL
---3V
1.5 V
1.5 V
~
Input
CL=50pF
(_Note B)
Output
Generator
(see Note A)
I
I·
-+! l+- -+! I+-
tcso
ov
tcso
1;f----2.5V
Output
50% "
_ _..J
II
90%
10%
}
iF
50%
-_2.5V
ttO -+i ~
-+i ~ lt~
VOLTAGE WAVEFORMS
TEST CIRCUIT
Figure 3. Driver Test Circuit and Voltage Waveforms
Input
Generator
(see Note A)
/1.5 V
I
Output
500
tpLH
Output
--.II 1-I
!1.3V
----'.
'~5~-
3V
I
OV
-.II
I14- tpHL
~--VOH
1.3V
VOL
VOLTAGE WAVEFORMS
TEST CIRCUIT
Figure 4. Receiver Test Circuit and Voltage Waveforms
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR :5 1 MHz. 50% duty cycle, Ir :5 6 ns,
=
If:56 ns, Zo 50 O.
B. CL includes probe and jig capacitance.
POST OFFICE BOX 655303 • DAUAS, TEXAS 75265
2~71
SN65179B, SN75179B
DIFFERENTIAL DRIVER AND RECEIVER PAIR
SLLS123B - 02845. OCTOBER 1985 - REVISED FEBRUARY 1993
TYPICAL CHARACTERISTICS
DRIVER HIGH·LEVEL OUTPUT VOLTAGE
VB
HIGH·LEVEL OUTPUT CURRENT
5
>I
4
~
3.5
I
~
'$
0
!
.c
~
:J:
VB
LOW·LEVEL OUTPUT CURRENT
5
I
VCC=5V
4.5 f- fA =25"C
GI
DRIVER LOW·LEVEL OUTPUT VOLTAGE
r--..
3
>
--
I
GI
I
~
...........
2.5
~
,
2
1.5
I
4
~
3.5
'$
Q.
'$
3
0
I
VCC=5V
TA = 25°C
4.5
L
1
I
2.5
I
2
I
.J
.p:J:
o
~
,.
.p
0.5
-
1.5
0.5
o
-20
-40
-60
-80
-100
o
-120
o
10H - High-t.evel Output Current - mA
40
60
80
100
20
10L - Low-Level Output Current - mA
DRIVER DIFFERENTIAL OUTPUT VOLTAGE
RECEIVER OUTPUT VOLTAGE
VB
DIFFERENTIAL INPUT VOLTAGE
VB
OUTPUT CURRENT
>
.....
I
f
>
2.5
~
2
~
-
VCC=5V
10=0
TA = 25°C
4.5
t--.....
3
~
5
VCC=5V
TA = 25°C
3.5
120
Figure 6
Figure 5
4
-
I
4
f'
'"
>
I
.......
~
~
i
"
~
'$
~
~
3.5
3
VIC =
-12V
J
vT-
VIC =
j
vT-
VIC =
t-- 12V - t-Vy
~
VT+
"
jVT
YIt
1~IIIIIIII ~\ II 1~IIIIIIIIIIIIII
o
10
20
30 40 40 60 70 eo
10 - Output Current - mA
90 100
-125 -100 -75 -50 -25 0 25 50 75 100 125
VID - Differential Input Voltage - mV
Figure 7
Figure 8
1ExAs ."
2-672
INSIRUMENIS
POST OFFICE BOX 655303 • DALlAS. TEXAS 75265
SN65179B, SN75179B
DIFFERENTIAL DRIVER AND RECEIVER PAIR
SLL.Sl23B - 02845. OCTOBER 1985 - REVISED FEBRUARY 1993
TYPICAL CHARACTERISTICS
HIGH·LEVEL OUTPUT VOLTAGE
HIGH·LEVEL OUTPUT VOLTAGE
vs
vs
FREE·AIR TEMPERATURE
HIGH·LEVEL OUTPUT CURRENT
5
>
VIO=0.2V
4.5 I- TA=25°C
I
4
~
3.5
i
~
i
~
3.5
:I::
~
~~
VCC=5.25V
3
./ I
I
~~
o 2.5
VCC=5V
~~ V
2
.c
~~
rI 1.5
~~
l: 1 I-- VCC =.(,.5 V
~
,
", ,
~~
0.5
~~
o
=
i
1:~~~~-+~~1=~-1--1
3~_+--+_-+--4-~~~--~_+~
!
2.51--+-1f----I----f--I--+-+--+--I
fiI
:f
1.5 ~_+--+_-+--4-~r--~--~_+~
!
!
o
VCC=5V
4.5 - VIO=0.2V
4
IOH=-440IlA
2~4--+--I--+-~-4--~4-~
I
l:
~
0.5 ~_+--+_-+--4-~~~--~_+~
OL-~--~~--~~--~--~~~
o
-5 -10 -15 -20 -25 -30 -35 -40 -45-50
IOH - Hlgh·Levei Output Current - rnA
10
20 30 40 50 60 70
TA - Free-Air Temperature - °c
Figure 9
RECEIVER LOW·LEVEL OUTPUT VOLTAGE
vs
vs
LOW·LEVEL OUTPUT CURRENT
.
0.5
f=
0.4
0
0.3
~
0.2
=
I
VCC=5V
TA = 25°C
>
Q.
~
I.J
/
/
/
./
~V
90
Figure 10
RECEIVER LOW·LEVEL OUTPUT VOLTAGE
0.6
80
/'
FREE·AIR TEMPERATURE
/'
VCC=5V
VIO=-0.2V
~ 0.4 ~IO=.:L'i-=_8_rnA.---+__4-~__~__~_+~
V
t
~
1
0.31=9=+-+---+-~-I==t--+-I
8
I"'
I
5 0.1 ~_+--+_-+--4-~--~--~_+--I
~ 0.1
>'
o
o
O~-L
5
10
15
20
25
30
o
10
IOL - Low-Level Output Current - rnA
__~-L__~-L__~-L__~~
20 30 40 50 60 70 80 90
TA - Free·Alr Temperature - °c
Figure 11
Figure 12
1ExAs
~
INSlRlJMENTS
POST OFFICE BOX 655303 • DALlAS. TEXAS 75265
2~73
2~74
SN65ALS180,SN75ALS180
DIFFERENTIAL DRIVER AND RECEIVER PAIRS
AUGUST 1987 - REVISED FEBRUARY 1992
•
Meets EIA Standards RS-422A and RS-485t
and CCITT Recommendations Y.11 and X.27
•
High-Speed Advanced Low-Power Schottky
Circuitry
•
Designed for 25-MBaud Operation In Both
Serial and Parallel Applications
•
•
Low Skew Between Devices •.• 6 ns Max
•
Individual Driver and Receiver I/O Pins With
Dual Vee and Dual GND
•
Wide Positive and Negative Input/Output
Bus Voltage Ranges
•
Driver Output Capacity ... ±60 mA
•
Thermal Shutdown Protection
•
Driver Positive and Negative Current
Limiting
•
•
•
•
•
D OR N PACKAGE
(TOP VIEW)
NC
vcc
R
VCC
0
A
B
Z
GND
GND
Low Supply Current Requirements
30 mA Max
Y
NC
7
NC-No internal connection
Function Tables
DRIVER
INPUT
D
ENABLE
DE
H
L
H
H
X
L
OUTPUTS
Y
Z
H
L
L
Z
H
Z
RECEIVER
Receiver Input Impedances ... 12 kQ Min
Receiver Input SensltlvHy ... ±200 mV Max
DIFFERENTIAL INPUTS
A-B
VIO .. 0.2V
-0.2 V < VIO < 0.2 V
Vlos-0.2V
ENABLE
RE
OUTPUT
R
L
L
L
H
X
H
Open
L
Z
H
Receiver Input Hysteresis ... 60 mV Typ
H =high level, L =low level, ?
Operates From a Single 5-V Supply
Z
GlitCh-Free Power-Up and Power-Down
Protection
=high impedance (off)
?
L
=indeterminate, X =irrelevant,
logic symbol:!:
4
description
EN1
DE
The SN65ALS180 and SN75ALS180 differential
driver and receiver pairs are monolithic integrated
circuits designed for bidirectional data
communication on multipoint bus transmission
lines. They are designed for balanced
transmission lines and meet EIA Standards
RS-422-A
and
RS-485
and
CCITT
recommendations V.11 and X.27.
D
RE
R
!>
5
3
2
9
1"7
10
1"7
..f'..
EN2
"72
12
I
II
OJ
4.5
3.5
!5
Q.
!5
3
~
0
'Ii
2.5
!ill
1.5
~
J:
I
J:
--..
4
!!
5
I
VCC=5V
TA=25"C
--
_
>
I
..
II
OJ
............. ......
2::
.......
~
!5
,
~
I'-..
0
'Ii
~
~
oJ
2
I
VCC=5V
TA=25"C
4.5
4
I
3.5
I
3
2
---
1.5
I
oJ
~
~
0.5
o
/'
0.5
o
-20
-40
-60
-so -100
IOH - High-level Output Current - rnA
I
I
2.5
o
-120
--"
40
60
so
100
20
10L - Low-Level Output Current - mA
o
Figure 9
120
Figure 10
DRIVER DIFFERENTIAL OUTPUT VOLTAGE
va
DRIVER OUTPUT CURRENT
4
>I
II
OJ
3.5
!!
3
!5
Q.
!5
2.5
~
0
~
i
It
.......
VCC=5V
TA=25"C
'"
2
1.5
..........
"-
.......
'"
.......
1'\
\
C
I
\
C
~
0.5
o
o
\
10
20
30 40 50 60 70
10 - Output Current - rnA
so
90
100
Figure 11
1ExAs
.Jf
INSIRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
2-683
SN65ALS180, SN75ALS180
DIFFERENTIAL DRIVER AND
R~CEIVER
PAIRS
SLLS052C - 03043. AUGUST 1987 - REVISED FEBRUARY 1992
TYPICAL CHARACTERISTICS
RECEIVER HIGH-LEVEL OUTPUT VOLTAGE
RECEIVER HIGH-LEVEL OUTPUT VOLTAGE
va
va
HIGH-LEVEL OUTPUT CURRENT
FREE-AIR TEMPERATURE
5~--~----~----~----~--~
VIO =o.2V
TA=25·C
5
VCC=5V
VIO=2OOmV·
IOH = - 440 i.tA
>
I
f
4
~
i
o
3
I
2
-
s:I
J:
~
-10·
-20
-30
-40
IOH - High-Level Output Current - mA
o
-40 -20
-50
0
20
40
60
80
TA - Free-Air Temperature _·C
Figure 12
>
I
J
~
~
S
o
~!i:
i
RECEIVER LOW-LEVEL OUTPUT VOLTAGE
va
va
RECEIVER LOW-LEVEL OUTPUT CURRENT
FREE-AIR TEMPERATURE
I
0.5 -
I
VCC=5V
TA=25·C
VIO = -200 mV
V
0.4
/'
0.3
I
o
/
V
0.6
V
/'
IIII
~
0.4
i
o
~
,/
I
25
5
10
15
20
IOL - Low-Level Output Current - mA
I
30
I
>I
t
/'
.~
I
VCC=5V
VIO=-2OOmA
0.5 - IOL=.8mA
0.3
---
! :]
,
IIIII111
-40 -20
Figure 14
0
20
40
60
80
100
TA - Free-Air Temperature _·C
Figure 15
1ExAs
~
INSIR.UMENTS
2-684
120
Figure 13
RECEIVER LOW-LEVEL OUTPUT VOLTAGE
0.6
100
POST OFFICE BOX 655303 • DAUAS. TEXAS 75265
120
SN65ALS180,SN75ALS180
DIFFERENTIAL DRIVER AND RECEIVER PAIRS
SLLS052C - D3043. AUGUST 1987 - REVISED FEBRUARY 1992
TYPICAL CHARACTERISTICS
RECEIVER OUTPUT VOLTAGE
vs
ENABLE VOLTAGE
ENABLE VOLTAGE
J
5
>I
~
!
6
V'O=0.2V
Load = 8 kO to GNO
TA = 25°C
I
Vee = 5.25 V
4
f
RECEIVER OUTPUT VOLTAGE
vs
~
5
>
I
I
~
3
_
Vee = 4.75 V
r-..
'--
io
3
~
2
.!
,.
J
Vee = 5.25 V
Vee = 4.75 V
VCC=5V..J
~
VCC=5V
2
I
I
~
o
f
4
I
V,O = 0.2 V
Loach1 kotoVCC
TA = 25°C
o
0.5
1.5
2
V,- Enable Voltage - V
2.5
o
3
o
0.5
Figure 16
1.5
2
V, - Enable Voltage - V
2.5
3
Figure 17
APPLICATION INFORMATION
SN65ALS180
SN75ALS180
SN65ALS180
SN75ALS180
Up to 32
Transceivers
NOTE: The line should be terminated at both ends in Hs characteristic impedance. Stub lengths off the main line should be kept as short as
possible.
Figure 18. Typical Application Circuit
1ExAs ..,
INSIRUMENTS
POST OFFICE BOX 655303 • DAu.AS. TEXAS 75265
2-685
2-686
SN75ALS181
DIFFERENTIAL DRIVER AND RECEIVER PAIR
•
•
•
•
•
•
•
•
•
•
•
Meets EIA Standards RS-422-A, RS-485,
and CCITI Recommendations V.11 and X.27
Low Supply Current Requirements
30mAMax
Driver Output Capacity ••• ±60 mA
Thermal Shutdown Protection
Driver Common-Mode Output Voltage
Range of -7Vto 12 V
Receiver Input Impedance .•. 12 kQ Min
Receiver Input Sensitivity ••• ±200 mV
Receiver Input Hysteresis •.• 60 mV Typ
Receiver Common-Mode Input Voltage
Range of ±12 V
Operates From Single S-V Supply
GlitCh-Free Power-Up and Power-Down
Protection
NOR Nst PACKAGE
(TOP VIEW)
NC
R
RE
DE
D
GND
A
NC - No internal connection
t The NS package is only available In left-end taped
and reeled (order device SN75ALS181 NSLE).
Function Tables
EACH DRIVER
ENABLE
DE
INPUT
D
H
L
X
description
The SN75ALS181 differential driver and receiver
pair are monolithic integrated circuits designed for
bidirectional data communication on multipoint
bus transmission lines. The design provides for
balanced transmission lines and meets EIA
Standards RS-422-A and RS-485, and eelTI
recommendations V.1 0, V.11, X.26, and X.27.
Vcc
VCC
H
H
L
OUTPUTS
V
Z
H
L
Z
L
H
Z
EACH RECEIVER
DIFFERENTIAL INPUTS ENABLE OUTPUT
A-B
RE
R
VID",O.2V
L
H
-O.2V
5
3
2
1
9
'V
1"1
"
EN2
"12
ZZ=>IOC,!)
00:
frequency response of each channel may be
~
(\1(\1
NC - No internal connection
easily controlled by a single external capacitor to
provide immunity to differential noise spikes. The
output goes to a high level when the inputs are open circuited. A strobe input is provided which, when in
the low level, disables the receiver and forces the output to a high level.
The receiver is of monolithic single-chip construction, and both halves of the dual circuits use common power
supply and ground terminals.
The SN55182 is characterized for operation over the full military temperature range of -55°C to 125·C. The
DS8820A and SN75182 are characterized for operation from O°C to 70·C.
logic symbol t
logic diagram (positive logic)
1IN+1T~
1~:~....:b---f--1OOns
I
I
II..
-=
I
I
I
~ >1oons /I
I
I
I
I
~tw~
>1oone
~I
I
r-
-2.5 V
~I
1.3V~------
1.3V
!+--t-
OV
"
tPLH(D)
t1.3V
'/;
I 1.3 V
I
I •
I \1.3V
I I
tPHL(S) -J.-..j
I
VOLTAGE WAVEFORMS
NOTES: A. The pulse generators have the following characteristics: Zo
B. CL includes probe and jig capac~ance.
C. All diodes are 1N3064 or equivalent.
=50 O. tr "
,
2.6 V
ov
I
I
!4~3~
VOH
___
VOL
....! j4- tPLH(S)
10 ns. tf" 10 ns. tw
I ,
=0.5
'" 0.1 JUl. PRR" 1 MHz.
Figure 1. Test Circuit and Voltage Waveforms
1ExAs
~
INSIRUMENTS
POST OFFICE BOX 655303 • DAUAS. TEXAS 75265
2-699
DS8820A, SN55182, SN75182
DUAL DIFFERENTIAL LINE RECEIVERS
SLi..s092A- 01292. OCTOBER 1972- REVISED MARCH 1993
TYPICAL CHARACTERISTICSt
DIFFERENTIAL INPUT THRESHOLD VOLTAGE
DIFFERENTIAL INPUT THRESHOLD VOLTAGE
>I
t
vs
vs
SUPPLY VOLTAGE
COMMON-MODE INPUT VOLTAGE
0.3
0.5
>I
&
VIC=O
TA=25·C
•
0.2
!!
,g
0.1
!'1
~
0
Vo = 2.5 V, 10 = -400 .,A
-
-0.1
I
-0.2
i
a
~
.c
~
0.2
SQ.
0
I
.5 -0.1
a;
Vo=0.4V,lo=16mA _
l!
-0.2
D
-0.3
j
r--- r--
9
I
I I
I
I
I
- ----
I
Vo =0.4 V,lo=16 mA
1--_
-
-0.4
>
5
5.5
VCC - Supply Voltage - V
-10 -5
o
5
10
15
VIC - Common-Mode Input Voltage - V
-0.5_ 20 -15
6
Figure 3
Figure 2
DIFFERENTIAL INPUT THRESHOLD VOLTAGE
va
FREE-AIR TEMPERATURE
100
>I
III
CI
~
.. N 0 = 2.5 V, 10 = -4OO.,A
............
SO
.........
~
'U
'0
.c
r-.......
0
VCC=5V
VIC=O
r-.......
ftJ
I!!
................
.c
l-
SQ. -SO
.5
. ~ I'-.....
VO=0.4V,IO=16mA
I
""""'-
I
I
I
I
Illlitu
-SO
-25
0
25
SO
75 100
TA - Free·Alr Temperature _·C
Figure 4
t Data for temperatures below o·e and above 70·e are applicable to SN55182 circuits only.
1E:xAs
2-700
I
I
">
-0.3
4.5
Vo = 2.5 V, 10 = -400 .,A
0.1
. t=
"I
.5
a;
l!
0.3
~
~
Vcd=5V I
TA=25·C
0.4
,If
INSIRUMENIS
POST OFFICE BOX 655303 • DAUAS. TEXAS 75265
125
20
DS8820A,SN55182,SN75182
DUAL DIFFERENTIAL LINE RECEIVERS
SLLS092A- 01292, OCTOBER 1972 - REVISED MARCH 1993
TYPICAL CHARACTERISTICSt
OUTPUT VOLTAGE
vs
VOLTAGE TRANSFER CHARACTERISTICS
FREE-AIR TEMPERATURE
5
I
-
VCC=5V
-
4
>I
t
~
!i
~
o
5
VCC=5V
VIC=O
>I
VIC = 0.5 V, 10 = -400 j.tA
...
co
~
3
3
~
'!;
0..
!i
2
0
I
I
~
~
2
VIC = -0.5 V, 10L = 16 rnA
I
I
I
I
o~~
o
-75
0
-~
-50
50
~
100
~
__
~~~~~~
-0.5 -0.4 -0.3-0.2 -0.1
1~
TA - Free-Air Temperature _·C
TERMINATING RESISTANCE
vs
INPUT VOLTAGE
FREE·AIR TEMPERATURE
VCC=5V
VIC =Oto",2OV
TA=~·C
6
/
'!;
0..
.5
I
.:
/
2
IN0
-2
V
-4
~
-6
V
-8
c:
""
./
./
............. ~
./
V
....., ~
.........
190
I
/
4
I
:::I
~~
200
8 -
U
__
0.3 0.4 0.5
vs
10
E
~
~~
Figure 6
INPUT CURRENT
E
__
0.1 0.2
VIC - Cifferentiallnput Voltage - V
Figure 5
«
0
".,....
...u
c
il
1ia:
"
180
co
c
~
i!c
E
~
170
Ii
160
I
IN+
I
.......
~
/'
V
/
V
/
V
-10
-20
150
-15
-10 -5
0
5
10
VI -Input Voltage - V
15
20
~
~~
Figure 7
0
~
50
~
100
TA - Free-AIr Temperature - ·C
1~
FigureS
t Cata for temperatures below O·C and above 70·e are applicable to SN55182 circuits only.
1ExAs
,If
INSIRUMENfS
POST OFFICE BOX 655303 • DALlAS. TEXAS 75265
2-701
DS8820A, SN55182, SN75182
DUAL DIFFERENTIAL LINE RECEIVERS
SLlS092A- 01292, OCTOBER 1972 - REVISED MARCH 1993
TYPICAL CHARACTERISTICSt
SUPPLY CURRENT
(AVERAGE PER RECEIVER)
POWER DISSIPATION
(AVERAGE PER RECEIVER)
vs
vs
COMMON-MODE INPUT VOLTAGE
COMMON-MODE INPUT VOLTAGE
12
10
1I
C
2!
!i
(,)
~
r::L
8
6
300
......
VCC=5V
No Load
TA=25°C
,
""-
'"""........
.........
::J
rn
I
4
250
~
E
I
c
~IO=-lV
i
~I'....
"
9
1\
~
r::L
VIO=~ ~
(,)
200
j
'"
...............
2
150
is
o
i
0
11.
I
-0
11.
..........
~
-20 -15 -10 -5
0
5
10
15
VIC - Common-Mode Input Voltage - V
VCC~5V
\
VIO j-1 V
/
o
l~OC 1
l!L
~
\~ TA=25°C
"-
100
50
Max Rated Po at TA =
~
TA = 125°C
J J
h
~
I'..
~'
"
I~ r--:
r-- V
-20 -15 -10 -5
0
5
10
15
VIC - Common-Mode Input Voltage - V
20
Figure 9
20
Figure 10
NOISE PULSE DURATION
VB
RESPONSE TIME-CONTROL CAPACITANCE
1000
I!
700
15
~::J
400
I
o
J
•
'0
z
200
I.;'
100
I
~
~
2.5 V
70
-2.5V
E
3
c:
I
VCC=5V
TA=25°C
See Note A
3--t--I I
•
f-"
•
OV
tw
INPUT PULSE
20
10
10
40
100
400
1000
4000
10000
Reeponse Time Control Capacitance - pF
NOTE A: Figure 11 shows the maximum duration of the Illustrated pulse that can be applied differently without the output changing from the low
to high level.
Figure 11
t Data for temperatures below ooe and above 70
0
e are applicable to SN55182 circuits only.
1ExAs
2-702
-If
INSIRUMENTS
POST OFFICE BOX 855303 • DALlAS, TEXAS 75265
DS8820A,SN55182,SN75182
DUAL DIFFERENTIAL LINE RECEIVERS
SLLS092A- 01292, OCTOBER 1972 - REVISED MARCH 1993
TYPICAL CHARACTERISTICSt
PROPAGATION DELAY TIMES FROM
DIFFERENTIAL INPUT
38
36
VB
VB
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
20
VCC=5V
S88 Figure 1
34
tPHL(O)
32
II
C
I
i
.5
i
26
~
Q
22
,.,....
16
14
-75
Ie i
"
~
€
L
..if:
/
0
25
50
100
125
€
:5
.e:
/
.5 12
IUi
.,/
14
tPLH(S
10
8
l:i
75
I
_V
...........
...I
....-r-50 -25
I
tPHL(S)
g !
tpLH(O) ~ ~
./
See Figure 1
16
,../"
20
VCC=5V
".-
'E
!! 24
18
18
i",....---"
, /~
30
28
PROPAGATION DELAY TIMES FROM
STROBE INPUT
.-'
6
4
-75
,../"
-50 -25
TA - Free-Air Temperature _·C
~
0
V
25
~
50
...V
75
./
100
125
TA - Free-Alr Temperature _·C
Figure 12
Figure 13
t Data for temperatures below O·C and above 70·C are applicable to SN55182 circuits only.
1ExAs . "
INSlRUMENTS
POST OFFICE BOX 655303 • DAllAS, TEXAS 75265
2-703
DS8820A,SN55182,SN75182
DUAL DIFFERENTIAL LINE RECEIVERS
SI-lS092A- 01292, OCTOBER 1972 - REVISED MARCH 1993
APPLICATION INFORMATION
VCC=5V
VCC=5V
1---,
r---I
I
1/2'182
1/2'183
~-----
I
Iz
IN-
I
I
I
I
I
I
O·OO2I1 F
(see Note A)
Iy
I
I
I
I
I
I
L1
l00pF
I
:f (see Note B)
TwIsted
Pelr
'-----J--.J
GND
GND
NOTES: A When the inputs are open circuHed, the output will be high. A capacitor may be used for dc isolation of the line-terminating resistor.
At the frequency of operation, the impedance of the capacitor should be relatively small.
Example: let
f
=5 MHz
C =0.00211F
Zc=~c
... "
2K (5
1
x 106) (0.002 x 10 6j
Zc - 160
B. Use of a capacitor to control response time is optional.
Figure 14. Transmission of Digital Data Over Twlsted·Palr Line
1ExAs . "
INSIRUMENTS
2-704
POST OFFICE BOX 655303 • DAUAS, TEXAS 75265
DS8830, SN55183, SN75183
DUAL DIFFERENTIAL LINE DRIVERS
SLLS093A- 01
•
•
•
•
•
•
•
•
•
•
•
OCTOBER 1972- REVISED MARCH 1993
SN5S183 ••• J OR W PACKAGE
0S8830, SN75183 ••• 0 OR N PACKAGE
Single SoV Supply
Differential Line Operation
Dual Channels
TTL Compatibility
Short-Circuit Protection of Outputs
Output Clamp Diodes to Terminate Line
Transients
High-Current Outputs
Quad Inputs
Single-Ended or Differential AND/NAND
Outputs
Designed for Use With Dual Differential
Drivers SN55182 and SN75182
Designed to Be Interchangeable With
National Semiconductor DS7830 and
DS8830
(TOP VIEW)
VCC
2D
2C
28
2A
1Z
GND
2Y
2Z
SN5S183 ••• FK PACKAGE
(l'OPVIEW)
C,)C,)
~~z$'~
3
1C
NC
description
The DS8830, SN55183, and SN75183 dual
differential line drivers are designed to provide
differential output signals with high-current
capability for driving balanced lines, such as
twisted-pair, at normal line impedances without
high power dissipation. These devices may be
used as TTL expander/phase splitters, as the
output stages are similar to TTL totem-pole
outputs.
4
1 2019
1B
5
17
2
10
6
16
NC
1Y
7
15
8
14
9 1011 1213
2C
NC
28
NC
2A
~~~~~
(!)
NC - No internal connection
The driver is of monOlithic single-chip construction, and both halves of the dual circuits use common power
supply and ground terminals.
The SN55183 is characterized for operation over the fuii military temperature range of -55°C to 125°C. The
DS8830 and SN75183 are characterized for operation from O°C to 70°C.
logic symbol t
1
1A
18
1C
2
2A
28
1A
5
1Z
2
18
3
1C
4
10
2Y
2A
1Y
6
10
11
9
28
12
2C
20
&t>
3
4
10
logic diagram (positive logic)
13
8
2C
2Z
20
tThis symbol is in accordance with ANSI/IEEE Std 91-1984
and IEC Publication 617-12.
Pin numbers shown are for the D, J, N, and W packages.
10
11
12
13
!tug::::
!tug:::
posHive logic: Y
=ABCD, Z =ABCD
Copyright © 1993, Texas Instruments Incorporated
1ExAs . "
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2-705
DS8830, SN55183, SN75183
DUAL DIFFERENTIAL LINE DRIVERS
SLLS093A- 01292. OCTOBER 1972 - REVISED MARCH 1993
schematic (each driver)
r-~______________- .__~____-.~~___
14_
vee
545tl
2ktl
3ktl
gtl
6,8
Z
A 1,10
B 2, 11
545tl
e 3,12
4ktl
3ktl
3.2 ktl
gtl
D 4,13
5, 9
7
Resistor values shown are nominal.
Pin numbers shown are for the D, N, J, and W packages.
1ExAs
2-706
..If.
INSIRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
y.
GND
DS8830, SN55183, SN75183
DUAL DIFFERENTIAL LINE DRIVERS
SLLS093A- D1292, OCTOBER 1972 - REVISED MARCH 1993
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
DS8B30
SN55183
7
7
V
5.5
5.5
V
1
1
s
Supply voltage, VCC (see Note 1)
Input voltage
UNIT
SN75183
Duration of output short circuit (see Note 2)
See Dissipation Rating Table
Continuous total power dissipation
Operating free-air temperature range
-55 to 125
Ot070
·C
Storage temperature range
-65 to 150
-65 to 150
·C
260
·C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: D or N package
Case temperature for 60 seconds: FK package
260
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: J package
300
·C
·C
300
NOTES: 1. All voltage values, except differential voltages, are with respect to network ground terminal.
2. Not more than one output should be shorted to ground at a time.
DISSIPATION RATING TABLE
PACKAGE
TA,,25·C
POWER RATING
DERATING FACTOR
ABOVE TA = 25·C
TA=70·C
POWER RATING
TA = 125·C
POWER RATING
D
950mW
7.6mWrC
606mW
FKt
Jt
1375mW
880mW
275mW
1375mW
11.0mWrC
11.0mWrC
860mW
275mW
N
1150mW
9.2mWrC
736mW
W
l000mW
8.0mWrC
640mW
200mW
t In the FK and J packages, SN55163 chips are alloy mounted and SN75163 chips are glass mounted.
recommended operating conditions
DS8B30, SN75183
SN55183
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.75
5
5.25
Supply voltage, VCC
High-level Input voltage, V,H
2
Low-level input voltage, V,L
High-level output current, IOH
Low-level output current, IOL
Operating free-air temperature, TA
V
V
2
0.6
0.6
V
-40
-40
rnA
40
rnA
70
·C
40
-55
UNIT
125
0
1ExAs ."
INSIRUMENTS
POST OFFICE BOX 655303 • DAUAS. TEXAS 75265
2-707
DS883O, SN55183, SN75183
DUAL DIFFERENTIAL LINE DRIVERS
SUB093A- 01292, OCTOBER 1972- REVISED MARCH 1993
electrical characteristics over recommended ranges of Vee and operating free-air temperature
(unless otherwise noted)
PARAMETER
VOH
High-level output voltage
VOL
Low-level output voltage
VOH
High-level output voltage
VOL
Low-level output voltage
TEST CONDITIONS
V (AND)
output
Z(NAND)
output
MIN
VIH=2V,
IOH=-0.8mA
2.4
VIH =2 V,
IOH=-40mA
1.8
TYpt
MAX
V
3.3
VIL = 0.8 V,
10L= 32 rnA
0.2
VIL=0.8V,
10L= 40 rnA
0.22
VIL =0.8 V,
10H =-0.8 rnA
2.4
VIL=0.8V,
10H=-40mA
1.8
VIH =2V,
10L= 32 rnA
0.2
VIH=2V,
10L= 40 rnA
0.22
UNIT
0.4
V
V
3.3
0.4
V
IIH
High-level input current
VIH =2.4V
120
IJA
II
Input current at maximum input voltage
VIH =5.5V
2
rnA
IlL
Low-level Input current
VIL=0.4V
lOS
Short-circuit output current*
VCC =5V,
TA=125"C
Supply current (average per driver)
VCC=5V,
No load
All inputs at 5 V,
ICC
-40
-4.8
rnA
-100
-120
rnA
10
18
rnA
t All typical values are atVcc = 5 V, TA = 25"C.
* Not more than one output should be shorted to ground at a time, and duration of the short circuit should not exceed one second.
switching characteristics, Vee = 5 V, TA = 25°C
PARAMETER
TEST CONDITIONS
tPLH
Propagation delay time, low-to-high-Ievel V output
tpHL
Propagation delay time, hlgh-to-Iow-Ievel V output
tPLH
Propagation delay lime, low-to-high-Ievel Z output
tpHL
Propagation delay time, high-to-Iow-Ievel Z output
tpLH
Propagation delay time, low-to-high-Ievel differential output
tpHL
Propagation delay time, high-to-Iow-Ievel differential output
AND gates
CL= 15 pF,
See Figure 1(a)
NAND
gates
V output
wIIh respect
toZ output
ZL = 100 Q in series
with 5000 pF,
See Figure 1 (b)
1ExAs ."
INSIRlJMENTS
2-708
POST OFFICE BOX 655303 • DALlAS, TEXAS 75265
MIN
TYP
MAX
8
12
UNIT
ns
12
18
ns
6
12
6
8
9
16
ns
8
16
ns
ns
DS8830,SN55183,SN75183
DUAL DIFFERENTIAL LINE DRIVERS
SLLS093A- Dl292, OCTOBER 1972 - REVISED MARCH 1993
PARAMETER MEASUREMENT INFORMATION
Input
Pulse
Generator
(see Note A)
VCC=",5V
y
Output
I
I
I
II
'-___ -=___
I
IT
J -=
Z
CL = 15 pF Output
(see Note B)
TEST CIRCUIT
VOLTAGE WAVEFORMS
(a) OUTPUTS Y AND Z
VCC=5V
Input ,J1.5V
Y
J1PLH~
Output
-'10
SOOOpF
Z
Output
Differential _ _ _
Output
.
Voltage
TEST CIRCUIT
V
VOLTAGE WAVEFORMS
(b) DIFFERENTIAL OUTPUT
=
NOTES: A. The pulse generators have the following characteristics: Zo 50 C, tr s 10 ns, tf s 10 ns, tw
B. CL includes probe and jig capacftance.
C. Waveforms are monHored on an oscilloscope wHh Rin ., 1 MO.
=0.5 !tS, PRR s 1 MHz.
Figure 1. Test Circuits and Voltage Waveforms
1ExAs
..If
INSIRUMENTS
POST OFFICE BOX 655303 • DAUAS, TEXAS 75265
2-709
DS8830, SN55183, SN75183
DUAL DIFFERENTIAL LINE DRIVERS
SLLS093A- 01282, OCTOBER 1972 - REVISED MARCH 1993
TYPICAL CHARACTERISTICSt
THRESHOLD VOLTAGE
HIGH-LEVEL OUTPUT VOLTAGE
va
vs
FREE-AIR TEMPERATURE
HIGH-LEVEL OUTPUT CURRENT
2.4
2.2
>I
•
!
f
1••
f
I
1.2
~
>
VIHmln
2
1.8
~
.c
4~-r-I-r-I-~I~--~-~J~J~
VCC·5V
VO=1.5V
1.4
.. ~ t:--....
ANDGa;~ :::::::-- I-.....
..........
I
t
J
NAND Gate
...:::::: t:--
VILmax
1
t
of
I
0••
:I:
~
0.6
0.4 I...---I._....._
-75 -50 -25
25
50
75 100
TA - Free-Air Temperature - ·C
i:::::'1 ':::::f... 50-0 Load
3
r'f:.~
I' IJ'......... ~l\ r 2~·C
!, /
~'Tl=-~·c
2.5
TA =
2 I--IH--7f---t--t-'Nr--If--t-ri---i
1.5 I-+++-I--+---t--I-+--f-I-'M~-r--i
/1 /
,
I,';/
O~ m7-t--+--t-~+--rt-~-ri---i
TA=125·C
~,
o .....---'_-'-_-'---'u............'----"'--......._
o -20 -40 -50 -80 -100 -120 -140
........_..I..---I'----I._.....L..---I
0
~ 200-0 Load
VCC = 5 V
3.5 k:-'''''dI-- 1OG-0 Load t--t--t--+---I
125
...
-150
IOH - High-level Output Current - mA
Figure 2
Figure 3
DIFFERENTIAL OUTPUT VOLTAGE
LOW-LEVEL OUTPUT VOLTAGE
va
vs
DIFFERENTIAL OUTPUT CURRENT
LOW-LEVEL OUTPUT CURRENT
4r--~---r--.---,,---,
3
I
VCC=5V
I
VCC=5V
>I
>
i
J
I
I
V
2
'!S
21---I---+~P-.d----t----I
I
/
V
"
"
{
/
I
lillftt1jt I
TA,,25·C
!
/
TA=-55·C
j
I
I
I
40
50
II
I
I
..J
Q
~
~
o
75
125
020
100 - Differential Output Current - mA
Figure 4
FigureS
t Data for temperatures below o·e and above 70·e are applicable to SN55183 circuits only.
1ExAs
..If
INSTRUMENTS
2-710
80 100120140150180200
IOL - Low-Level Output Current - mA
POST OFFICE BOX 855303 • DALlAS, TEXAS 75285
DS8830, SN55183, SN75183
DUAL DIFFERENTIAL LINE DRIVERS
SLLS093A - 01292, OCTOBER 1972 - REVISED MARCH 1993
TYPICAL CHARACTERISTICSt
PROPAGATION DELAY TIME OF
DIFFERENTIAL OUTPUT
VB
FREE-AIR TEMPERATURE
TOTAL POWER DISSIPATION
(BOTH DRIVERS)
VB
FREQUENCY
20
240
VCC=5V
See Figure 1(b)
220
!
~
I
III
E
1=
>II
'ii
Q
c
0
ilCII
...
II
£
I
"
.....
c
0
10
200
I
15
..
-
tpLH
is
Iii
~
"""" ~
tPHI:-- ~
...
'i
j
~
.-' ~
100
I
V
140
120
R
/
160
~
{!.
5
180
!
Q,
Vcc=5VIIIII
No Load
Input: 3N Square Wave
TA=25·C
1..-- ....
80
60
o
-75 -50 -25
0
25
50
75
100
125
40
0.1
TA - Free-Air Temperature _·C
0.4
4
10
40
100
f - Frequency - MHz
Figure 6
Figure 7
t Data for temperatures below O·C and above 70·C are applicable to SN55183 circuits only.
TEXAS
,If
INSIRUMENTS
POST OFFICE BOX 655303 • DAUAS. TEXAS 75265
2-711
DS8830,SN55183,SN75183
DUAL DIFFERENTIAL LINE DRIVERS
SIl.S093A- 01292. OCTOBER 1972- REVISED MARCH 1993
APPLICATION INFORMATION
Vee =5 V
Vee
r----1--,
1/2 '183
I
Inputs
{
1/2 '182
~-----
I
AI
g+~t+=t_Y-;:;'=Z--''--__
I
I
=5 V
L1
Inverting
II
ut-i-1--o- RY1
The SN65C185 and SN75C185 are low-power
BI-MOS devices containing three independent
drivers and five receivers that are used to interface
data terminal equipment (DTE) with data
circuit-terminating equipment (DeE). The
SN65C185 and SN75C185 will typically replace
one SN75188 and two SN75189 devices. These
devices have been designed to conform to
Standards
ANSI/EIA-232-D-1986,
which
supersedes RS-232-C. The three drivers and five
receivers of the SN65C185 and SN75C185 are
sim liar to those ofthe SN75C188 quad drivers and
SN75C189A quad receivers, respectively. The
drivers have a controlled output slew rate that is
limited to a maximum of 30 V/JAS and the receivers
have filters that reject input noise pulses that are
shorter than 1 flS. Both these features eliminate
the need for external components.
The SN65C185 and SN75C185 have been
designed using low-power techniques in a
BI-MOS technology. In most applications, the
receivers contained in these devices will interface
to single inputs of peripheral devices such as
ACEs, UARTS, or microprocessors. By using
sampling, such peripheral devices are usually
insensitive to the transition times of the input
signals. If this is not the case, or for other uses, it
is recommended that the SN65C185 and
SN75C185 receiver outputs be buffered by single
Schmitt input gates or single gates ofthe HCMOS,
ALS, or 74F logic families.
RA2--B>o- RY2
RA3--B>o- RY3
DY1---o<]--- DA1
DY2---o<]--- DA2
RA4--B>o- RY4
DY3---o<]--- DA3
RAS--B>o- RY5
logic symbol t
RA1
RA2
RA3
DY1
DY2
AM
DY3
RAS
2
3
4
5
6
7
8
9
19
11.
18
"D..
17
"D..
v
~
NC - No internal connection
Function Tables
LOOPBACK
LB
The SN75186 is characterized for operation from
0·Ct070·C.
H
H
L
L
EACH RECEIVER
INPUTS
Bt
A
X
H
X
L
H
OUTPUT
Z
L
H
L
H
L
X
X
EACH DRIVER
LOOPBACK
LB
INPUT
OUTPUT
A
vt
H
H
L
H
L
L
H
L
X
t Voltages are RS-232-C, EIA-232-D, and
V,28levels
H = high level, L = low level, X = irrelevant
=~r:.=:''''';~':':=::::''~~
ltancllrd Wlrranty. Prodllodon proceulnl dOlI nCII neceuarlly Include
..../ng 01111
p.""n-..
Copyright © 1993, Texas Instruments Incorporated
1ExAs ."
INSIRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2-721
SN75186
QUAD DRIVER/RECEIVER WITH LOOPBACK
SLLS068B - 03389, FEBRUARY 1990 - REVISED MARCH 1993
logic symbol t
21
24
3
01
02
03
6
1A
1Z'
2A
2Z
3A
3Z
4A
4Z
19
,
04
...
20
22
1
6
...
2
4
~
UI"
16
15
14
2
2V6
~
13
2J1"
I>
12
3
3V7
~
7
...
6
1
iV5 -
I>
.....
23
r
I>
11
3J1"
I>
10
4
1Y
1B
2Y
2B
3Y
3B
4Y
4V6
~
8
9
4J1"
4B
tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and lEe Publication 617-12.
Pin numbsrs shown are for the OW package.
logic diagram, each driver/receiver pair (positive logic)
A------t
Y
LB
Z
-----+--~
L_-=-
\.
I
IR.ce~.r ~ J
1ExAs
2-722
--,
..A
..If
INSIRUMENTS
POST OFFICE BOX 86630G • DALLAS, TEXAS 75266
B
SN75186
QUAD DRIVER/RECEIVER WITH LOOPBACK
SLl.S0688 - 03389. FEBRUARY 1990 - REVISED MARCH 1993
schematics of inputs and outputs
EQUIVALENT RECEIVER INPUT
EQUIVALENT RECEIVER OUTPUT
--.~---...- - - VCC2
ESD Protection
8V
4kO
GND
B Input
ZOutput
8V
ESD Protection
ESD Protection
1.2 x VBE
GND
-------+-
G N D - - 4 - - - - -__~~__-~__~--
VEE---e---
EQUIVALENT DRIVER AND LOOPBACK INPUT
EQUIVALENT DRIVER OUTPUT
VCC1
VCC1 -------~.------300
8V
8V
ESD
Protection
GND
A Input ----<_____-I
, Internal
1.4-V Retto GND
Output
3pF
D1
8V
ESD Protection
GND--'-
GND
ESD Protection
VEE----.----.~---e--
All component values shown are nominal.
1ExAs ."
INSIRUMENIS
POST OFFICE BOX 655303 • DAUAS. TEXAS 75265
2-723
SN75186
QUAD DRIVER/RECEIVER WITH LOOPBACK
SLLS068B - 03389, FEBRUARY 1990- REVISED MARCH 1993
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC1 (see Note 1) .......................................................... 15 V
Supply voltage, VCC2 ....................................................................... 7 V
Supply voltage, VEE ...................................................................... -15 V
Receiver input voHage range .........................•............................. -30 V to 30 V
Driver input voHage range .................................................... (VEE + 2 V) to VCC1
Loopback input voHl!lge range .......................................................... 0 V to 7 V
Driver output voHage range ........................................................ -30 V to 30 V
Continuous total power dissipation ..................................... See Dissipation Rating Table
Operating free-air temperature range, TA ......................•....................... O·C to 70·C
Storage temperature range ....•...•.........................•....••.•..•......... -65·C to 150·C
Case temperature for .10 seconds: FN package .............................................. 260·C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: DW package ................... 260·C
NOTE 1: All voltages are with respect to the network ground terminal.
DISSIPATION RATING TABLE
=
PACKAGE
TA,,25°C
POWER RATING
DERATING FACTOR
ABOVE TA 250C
TA 70°C
POWER RATING
OW
1350mW
10.8mWrC
864mW
FN
1400mW
11.2mWrC
896mW
=
recommended operating conditions
MIN
NOM
MAX
UNIT
Supply voltage, VCCl
10.8
12
13.2
V
Supply voltage, VCC2
4.5
5
5.5
V
-10.8
-12
-13.2
V
VCC2
V
:t30
V
Supply voltage, VEE
Input voltage, VI
Driver and loopback
Input voltage, VI (see Note 2)
Receiver
High-level Input voltage, VIH
Driver and loopback
Low-level Input voltage, VIL
Driverandloopback
Output voltage powered on or off, Vo
Driver
High-level output current, IOH
Receiver
Low-level output current, IOL
Receiver
Operating free-airtemperature, TA
0
V
2
0.8
0
V
",30
V
-4
rnA
4
rnA
70
°c
NOTE 2: If all receIVer Inputs are held at :t30 V, the thermal diSSipation limit of the package may be exceeded. The thermal shutdown may not
protect the device, as this dissipation occurs In the receiver input resistors.
1ExAs . "
2-724
INSIRUMENTS
POST OFFICE BOX 655303 • DAUAS. TEXAS 75265
SN75186
QUAD DRIVER/RECEIVER WITH LOOPBACK
SLlS068B - 03389, FEBRUARY 1990 - REVISED MARCH 1993
DRIVER SECTION
electrical characteristics over full recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYpt
MAX
UNIT
VOH
High-level output vottage
RL=3kg,
VIL= O.BV,
See Figure 1
VOL
Low-level output voltage*
RL= 3 kg,
VIH=2V,
See Figure 1
-7
V
VOH(LB)
High-level output vottage In loopback modeU'll
RL= 3 kg,
LBat O.BV,
VIL= O.BV
-7
V
IIH
High-level input current (driver and loopback
inpuls)#
VI=5V,
See Figure 2
100
IIA
IlL
Low-level input current (driver and loopback
inputs)#
-100
IIA
VOS(H)
High-level short-circu~ output current
VI = O.B V,
VO=O,
See Note 3 and Figure 1
-10
-20
--$
rnA
VOS(L)
Low-level short-circuit output current
VI=2V,
VO=O,
See Note 3 and Figure 1
10
20
35
rnA
ICCl
Supply current from VCCl
No load
ICC1(LB)
Supply current from VCCl with loopback on
No load,
2.5
LBatO.BV
lEE
Supply current from VEE
No load
IEE(LB)
Supply current from VEE wnh loopback on
No load,
LBatO.BV
ICC2
Supply current from VCC2
No load,
VI=O,
See Note 5
Supply current from VCC2 with loopback on
No load,
See Note 5
LB at O.B V,
VI=O,
ICC2(LB)
V
7
See Note 4
0.3
rnA
rnA
-4
rnA
-10
rnA
-10
-100
IIA
-10
-100
IIA
--2.5
VCel = VEE = VCC2 = 0,
VO=-2Vt02V,
4
10
5
kg
t All typical values are at TA = 25°C.
* The algebraic convention, where the more positive (less negative) limit is designated as maximum, is used In this data sheet for logic levelS only.
§ This is the most positive level that the driver output will rise to when the device Is in the loopback mode and the driver input is at a low level.
'II The loopback mode should be entered only when the driver output is in the low (marking) state.
# Unused driver inputs should be tied to 0 V or VCC2; unused loopback inputs should be tied to VCC2.
NOTES: 3. Minimum lOS (H) and IOS(L) are specified at ~O = 0, as this more accurately describes the output current needed to dynamically drive
capacitive lines. A minimum ohl0 rnA is sufficlenllo drive 2500 pF in parallel with 3 kg at a slew rate of 4 VltJ.s (In accordance with
EIA-232-D and V.28).
4. Test conditions are those specified by EIA-232-D.
5. Without a load and VI = 0, the worst-case conditions, VCC2 sources a small current originating from VCCl giving ICC2 supply current
a negative sign. When a receiver has an output load, VCC2 Sinks static and dynamic supply currents to meet load requirements.
1ExAs
..If
INSIRUMENI'S
POST OFFICE BOX 655303 • DALlAS, TEXAS 75265
2-725
SN75186
QUAD DRIVER/RECEIVER WITH LOOPBACK
SLLS068B - 03389, FEBRUARY 1990 - REVISED MARCH 1993
switching characteristics over full recommended ranges of supply voltages and operating free-air
temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
tpLH
Propagation delay time, low-to-high level
output
tpHL
Propagation delay time, high-to-Iow-Ievel
output
I tpLH -
RL=3kCt07kC,
See Figure 3
tPHL I
MIN
CL= 15 pF,
iskew
SR
RL=3kCt07kC,
CL = 15 pF to 2500 pF
Output slew rate
RL=3kCt07kC,
CL = 15 pFto 2500 pF
tpd(ILB)
Propagation delay time going Into loopback
mode:!:
RL=3kCt07kC,
See Note 6 and Figure 7
tpd(OLB)
Propagation delay time going out of
loopback mode §
RL=3kCt07kC,
tpd(LB)
Propagation delay time In loopback mode'll
RL=3kCt07kC,
tskew
Skew time in loopback mode
RL=3kCt07kC,
TYpt
MAX
0.6
5
lIS
0.8
5
lIS
0.2
1
UNIT
lIS
30
VIlIS
3
50
lIS
See Note 6 and Figure 7
3
50
lIS
See Note 6 and Figure 8
3
15
lIS
See Note 6
4
10
lIS
4
t All typical values are at TA = 25°C.
:j: This is the delay between entering the loopback mode and when the data on the receiver output becomes valid.
§ This is the worst-case (rising or falling edges) total propagation delay between driver input and receiver output when in the loopback mode.
'Ii This is the magnitude of the difference between the propagation delay time of the rising and falling edges of tpd (LB).
NOTE 6: Skew time Is the magnitude of the difference between tPHL and tPLH and is measured with a 0 to 3-V Input pulse.
1ExAs
~
INSIRUMENTS
2-726
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN75186
QUAD DRIVER/RECEIVER WITH LOOPBACK
SLLS0688 - 03389, FEBRUARY 1990- REVISED MARCH 1893
RECEIVER SECTION
electrical characteristics over full recommended ranges of supply voltages and operating free-air
temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYpt
MAX
UNIT
VT+
PosHive-going threshold vo~age
See Figure 5
1.3
2
2.5
V
VT-
Negative-going threshold vo~age
See Figure 5
0.5
1
1.7
V
Vhvs
Input hysteresis (VT+ - VT-)
0.5
1
1.5
V
VOH
High-level output voltage
VOL
Low-level output voltage
VI = -3 V or inputs open,
IOH=-4mA,
IOH = -20 ""
See Note 7 and Figure 5
IOL=4mA,
See Figure 5
VI=3V,
IOS(H)
Short-circuit output current at high level
VOH=O,
See Figure 4
IOSlLl
Short-circuit output current at low level
VOL=VCC2,
See Figure 4
fin
V
2.4
-20
20
0.4
V
-60
mA
60
mA
3
IVI! ,,25V
Input resistance
3.5
7
IVII =3Vt025V
kQ
NOTE 7: If the Inputs are left unconnected, the receiver Interprets thiS as a low Input and the receiver outputs will remam In the high state.
switching characteristics over full recommended ranges of supply voltages and operating free-air
temperature (unless otherwise noted)
PARAMETER
UNIT
TEST CONDITIONS
MIN TYpt
MAX
2
6
I's
2
6
I's
200
300
ns
tpLH
Propagation delay time, low-to-high level output
tpHL
Propagation delay time, high-to-Iow-Ievel output
ITLH
Transition time, low-to-high level output*
ITHL
Transition time, high-to-low level output*
50·
tskew
ItpLH - tpHL I
tw
Maximum pulse duration assumed to be noise§
See Figure 6
CL= 50 pF,
See Figure 6
Pulse amplHude = 5 V
1
300
ns
0.1
1
ftS
2
4
ftS
t Aillypical values are at TA = 25·C.
* Transttion times are measured between 10% and 90% points on output waveform.
§ The receiver will ignore any positive- or negative-going pulse whose duration is less than the minimum value of tw and accept any positive- or
negative-going pulse whose duration is greater than the maximum value of tw.
TEXAS ~
INSIRUMENTS
POST OFFICE BOX 655303 • DALlAS. TEXAS 75265
2-727
SN75186
QUAD DRIVER/RECEIVER WITH LOOPBACK
SUS0688 - 03389. FEBRUARY 1990 - REVISED MARCH 1993
PARAMETER MEASUREMENT INFORMATION
IOS(l)
~
- ( ] ) - VCC1 or GND .
VCC1 VCC2
IoS(H)
--+
- ( ] ) - VEE or GND
Figure 2. Driver and Loopback
Test Circuit. IlL. IIH
Figure 1. Driver Test Circuit.
VOH. VOL. IOS(L). IOS(H)
VCC1 VCC2
. Input A
Input
Pulse
Generator
(see Note A)
J,I
tpHL
OutputY
-=-
1.5V \ .- - - - - 3V
I
I
~
--J+-tl
3
V~ 50%
; l;.;;-::::3...:;V_ _
tf
VEE
;.5V
-.l
;4--
50%
OV
tpLH
j(3"v- VOH
.=-~3v~of-=-i'~ __
tr -+i ~-
DRIVER VOLTAGE WAVEFORMS
(see Note C)
DRIVER TEST CIRCUIT
Figure 3. Driver Test Circuit and Voltage Waveforms
VCC1 VCC2
IOS(l)
+-- ( ] ) - VCC2
Figure 4. Receiver Test Circuit. IOS(H). IOS(L)
NOTES: A The pulse generator has the following characteristics:
B. CL includes probe and jig capacftance.
C. Slew rate
_
Figure 5. Receiver Test Circuit. YT. YOLo VOH
lw =25 lAS. PRR =20 kHz. Zo =50 O.
...2.JL
tr or t f
lExAs· ..,
INSlRUMENrS
2-728
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
SN75186
QUAD DRIVER/RECEIVER WITH LOOPBACK
SUS068B - 03389. FEBRUARY 1990 - REVISED MARCH 1993
PARAMETER MEASUREMENT INFORMATION
Input B
--1f
I
~
Output Z
VEE
::v
1.5V.FVOH
I
10%
::;r~- VOL
-.! !4=
TEST CIRCUIT
-----
*-4- tpLH
tpHL
--::90%~.~~15;;'
lTHL
-=-
2V \
2V
I
Pulse
Generator
(see Note A)
lTLH
"
VOLTAGE WAVEFORMS
Figure 6. Receiver Propagation and Transition Times
Input
y
Pulse
Generator
(see Note A)
~}
Loopback
Input LB
tpd(ILB)
/1
1.5 V
..._ _ _..J.
~
Receiver
OutputZ
B =High - - - - I
I.
I
I
1.5V
1.5 V
/1
~ tpd(OLB)
~
1.5V ' ' - -
VOLTAGE WAVEFORMS
TEST CIRCUIT
Figure 7. Loopback Entry and Exit Propagation Times
Input
Pulse
Generator
(see Note A)
LB
=Low
Drlver.L
InputA
1.5V
.-Ii
y
tpd(LB)
----~...-o-RY5
VDD
Vss
VCC
SwitchedCapacitor
.. .::.:.sKUtDOWNO.; : ... ::..Clrcult .....
GND
.,
"
..... -.
t This symbol is in accordance wHh ANSI/IEEE Std. 91-1984 and
IEC Publication 617-12.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, Vee (see Note 1) ............................................... 0.3 V to 6 V
Positive output supply voltage range, Voo ...................................... Vee -0.3 V to 15 V
Negative output supply voltage range, V ss ........................................... 0.3 V to -15 V
Input voltage range: RA .................................................................. ±30 V
All other inputs ........................................... -0.3 V to Vee + 3 V
Output voltage range: DY .......................................... -2 Vee + 1.2 V to 2 Vee - 1.2 V
All other outputs ......................................... -0.3 V to Vee + 3 V
Continuous total power dissipation ..................................... See Dissipation Rating Table
Operating free-air temperature range, TA .............................................. O°C to 70°C
Storage temperature range ....................... " .. '" ........ '" . .. .... ... .. .. -65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds ............................... 260°C
NOTE 1: All voHages are with respect to the network ground terminal.
DISSIPATION RATING TABLE
PACKAGE
TA,,25·C
POWER RATING
DERATING FACTOR
ABOVE TA = 25·C
TA=70·C
POWER RATING
DB
1025mW
8.2mW/"C
656mW
TEXAS . "
2-732
INSIRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
SN75LBC187
MULTICHANNEL EIA-232 DRIVER/RECEIVER
WITH CHARGE PUMP
SLLS1308 - 03881, SEPTEMBER 1991 - REVISED JANUARY 1993
recommended operating conditions
Supply voltage, VCC
DA
High-level input voltage, VIH
NOM
MAX
4.5
5
5.5
UNIT
V
2
RA, SHUTDOWN
Low-level input voltage, VIL
MIN
V
2.4
RA, DA, SHUTDOWN
Receiver input voltage, VI
-25
0.8
V
25
V
High-level output current, 10H
RY
-1
mA
Low-level output current, 10L
RY
3.2
mA
VDD
.,10
jlA
VSS
.,10
Output current, 10
Cl, C2, C3, C4 charge pump capacitors
0.1
Operating free-air temperature, TA
jlA
0.47
f.'F
·C
70
0
electrical characteristics over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Receiver
10=-1 mA
Driver
RL=3 kOto GND
Receiver
10 = 3.2mA
Driver
RL= 3 kOto GND
VOH
High-level output voltage
VOL
LOw-level output vciHage.
Vr+
Vr-
Receiver posHive-going input voltage threshold
Vhvs
Receiver input hystereSiS (\IT+Receiver input resistance
5
0.8
Vr-J
VCC =5\1,
TA=25·C
3
VO=.,2V
300
ro
Driver output resistance
VCC=O,
Input current (DA, SHUTDOWN)
VI =OtoVCC
lOS
Driver output short-circuit current
VO=O
All outputs open, SHUTDOWN at 0.1 V
UNIT
V
7
-7
-5
1.7
2.4
1.2
V
V
V
0.5
1
V
5
7
kO
.,50
jlA
a
.,10
All outputs open, SHUTDOWN at 2.4 V
Supply current
MAX
0.4
II
ICC
TYpt
3.5
Receiver negative-going input voltage threshold
I'j
MIN
mA
15
30
mA
10
jlA
t All typical values are at VCC = 5 Vand TA = 25·C.
1ExAs
,If
INSIRUMENI'S
POST OFFICE BOX 655303 • DAUAS, TEXAS 75265
2-733
SN75LBC187
MULTICHANNEL EIA·232 DRIVER/RECEIVER
WITH CHARGE PUMP
Su.sl30B - 03881, SEPTEMBER 1991 - REVISED JANUARY 1993
switching characteristics over recommended operating conditions, TA = 25°C (unless otherwise
noted)
,
PARAMETER
TEST CONDITIONS
i
tpLH
tpHL
tr
tf
Propagation delay time, low-to-hlgh-Ievel output
RL= 5 kCl,
Receiver
See Figure 1
Driver
RL = 3 kCl,
See Figure 2
CL= 12oopF,
Receiver
RL = 5 kCl,
See Figure 1
CL= 50 pF,
Driver
RL = 3 kCl,
See Figure 2
CL= 1200 pF,
RL = 3 kCl,
Vo =-3Vto 3V,
CL= 50 pF,
See Note 2
RL = 3 kCl,
Vo = -3.3 V to 3.3 V.
CL=25OOpF,
See Note 3
RL = 3 kCl,
Vo = 3 Vto-3 V
CL=:50 pF,
RL = 3 kCl,
Vo = 3.3 Vto -3.3 V
CL=25OOpF,
Propagation delay time, hlgh-to-Iow-Ievel output
Rise time, driver output
MIN
CL=50pF,
MAX
UNIT
1.25
lIS
1.25
lIS
1.25
lIS
1.25
lIS
200
ns
1.5
200
lIS
ns
Fall time, driver output
1,5
lIS'
NOTES: 2. The 200 ns for the output to change from -3 V to 3 V (or vice versa) corresponds to the 30 VIlIS maximum slew rate of EIA/TIA-232-E,
EIA/TIA-562, and CCITT v.2B.
3. The more stringent requirement for transHion times comes from the EIA/TIA-562, which requires the rise and falltimes to be measured
from 3.3 V.
1ExAs . "
INSIRUMENfS
2-734
POST OFFICE BOX 655303 • DAUAS, TEXAS 75265
SN75LBC187
MULTICHANNEL EIA·232 DRIVER/RECEIVER
WITH CHARGE PUMP
SLl.Sl30B - 03881, SEPTEMBER 1991 - REVISED JANUARY 1993
PARAMETER MEASUREMENT INFORMATION
Vee
Vee
1.SkQ
~
Input
VT,VI
r
-=-
Input
Output
eL=50pF
...,.... (see Note A)
SkQ
i
Vo
~--- VIH
(seeNoteB) - - - . /
i
- 3 V ' t - - VIL
~
I
tpHL
'\.~ 10%
Output
'\
!...-...tpLH
1- - i
9O%/VOH
. ---VOL
Figure 1. Receiver Test Circuit and Waveforms
r-
vee
M. .
tf?-~~r
VT, VI
iI
-=-.
3 kQ
t
eL = 1200 pF
(see Note A)
Output
IVo
Input
Output
Figure 2. Driver Test Circuit and Waveforms
NOTES: A. CL includes probe and jig capacRance.
B. The pulse generator has the following characteristics: tw
=8.33 J!s, PRR =60 kHz, tr = tf ,. 50 ns.
1ExAs
,If
INSIRUMENTS
POST OFFICE BOX 655303 • DAllAS. TEXAS 75265
2-735
SN75LBC187
MULTICHANNEL EIA·232 DRIVER/RECEIVER
WITH CHARGE PUMP
.
SLLS1308 - 03881. SEPTEMBER 1991 - REVISED JANUARY 1993
APPLICATION INFORMATION
Cl
0.1 J.lF
10V
II
1\
121
TL16C550
-r:10
ACE
Ai
20
DTR
22
CTS
6
SO
7
RTS
26
SI
-
DSR
DCD
5V
.1T
+
CS
5
8
11
Cl+
GND
J
114
ClVDD
RY5
RAS
DA3
DV3
RY4
RA4
DA2
DV2
SN75LBCl87
DAl
DVl
RY3
RA3
RY2
RA2
RYl
RAl
VCC
VSS
SHUTDOWN
C5
4.7J.tF
6.3 V
,
C2-
C2+
25
15
1
II
1
lC3
O•1 J.lF
13
16V
1
18 Rl
1
9
DTR
23 CTS
3
TX
2
RTS
27
RX
4
DSR
9
DCD
EIA-232-D
DB9S
Connector
r
nT
6
~
17
16
C4
O.lJ.lF
16V
1\
C2
0.1 J.lF
10V
NOTE: C1. C2. C3. and C4 are Z5U-type ceramic-chip capacitors.
Figure 3_ Typical SN75LBC187 Connection
.1ExAs ~
INSIRUMENIS
2-736
~
POST OFFICE BOX 655303 • DAUAS. TEXAS 75265
MC1488, SN55188, SN75188
QUAD LINE DRIVERS
SEPTEMBER 1983-
SLLS094A-
•
•
Meets Specifications of EIA RS-232-C
SN55188 ••• J OR W PACKAGE
MC1488, SN75188 ••• 0 OR N PACKAGE
Designed to Be Interchangeable With
Motorola MC1488
(TOP VIEW)
•
•
•
•
Current-Limited Output: 10 mA Typ
VCC+
Power-Off Output Impedance: 300 Q Min
4A
4Y
•
Input Compatible With Most TTL Circuits
4B
Slew Rate Control by Load Capacitor
2B
2Y
Flexible Supply Voltage Range
GND
description
(TOP VIEW)
The and SN55188 is characterized for operation
over the full military temperature range of -55°C
to 125°C. The MC1488 and SN75188 are
characterized for operation from QOC to 70°C.
1Y
4
1 2019
18
NC
2A
NC
2B
5
17
NC
6
16
4Y
7
15
8
14
9 1011 1213
NC
3B
3 2
H
X
A
B
H
H
L
L
X
H
X
L
H
>-00>-<
(!J
NC - No internal connection
Y
=high level, L =low level,
=irrelevant
logic symbol t
2B
3A
3B
4A
4B
4A
(\IZZC')C')
FUNCTION TABLE
(drivers 2 through 4)
2A
7
SN55188 ••• FK PACKAGE
The MC1488, SN55188, and SN75188 are
monolithic quad line drivers designed to interface
data terminal equipment with data communications equipment in conformance with EIA
Standard RS-232-C using a diode in series with
each supply-voltage terminal as shown under
typical applications.
1A
3B
3A
logic diagram (positive logic)
2
~
4
&~
3
6
5
9
8
10
12
13
11
1A~1Y
2Y
1Y
:~2Y
3Y
3A~
3B~3Y
4Y
4A~12
11 4Y
4B
t This symbol is in accordance with ANSIIIEEE Std 91-1984
13
and IEC Publication 617-12.
Positive logic
Y = A (driver 1)
Y AB or Pi +B (drivers 2 thru 4)
=
Pin numbers shown are for the 0 and N packages.
1ExAs
..If
Copyright © 1993, Texas Instruments Incorporated
INSIRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2-737
MC1488, SN55188, SN75188
QUAD LINE DRIVERS
SLI..S094A- 01323, SEPTEMBER 1983 - REVISED MARCH 1983
schematic (each driver)
To Other
Drive...
8.2kQ
Input(s) { : __ , . . . _
300Q
......--+-......---<.--J\i'V\r~ Output
GND
To
Other
Drlva ...
3.7kQ
70n
VCC----.---~-~~----~--~~-~
Reelstor vsluee shown
are nominal.
To Oth.r
Drive...
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
SN55188
MC1488
SN7S188
Supply voltage, VCC +, at (or below) 25·C free-alr temperature (see Notes 1 and 2)
15
15
Supply voltage, VCC-, at (or below) 25·C fre&-alr temperature (eee Notes 1 and 2)
-15
-15
.Input voltage range
-15to 7
-15to 7
Output voltage range
-15 to 15
-15 to 15
ContInuous total power dissipation (see Note 2)
UNIT
V
V
V
V
See Dissipation Rating Table
Operating free-alr temperature range
-55 to 125
Oto70
·C
Storage temperature range
-65 to 150
-65 to 150
·C
Lead temperature 1,6 mm (1/16 Inch) from case for 10 eeconde
D or N package
260
Case temperature for 60 seconds
FKpackage
260
Lead temperature 1,6 mm (1/16 Inch) from case for 60 seconde
J or W package
300
·C
·C
NOTES: 1. All voltage values are WIth respect to the network ground terminal.
2. For operation above 25·C free-alr temperature, refer to the maximum supply voltage cuIVe, FIgure 6. In the FK and J packages,
SN551 es chips are aney mounted.
DISSIPATION RATING TABLE
PACKAGE
TA,,25·C
POWER RATING
DERATING FACTOR
ABOVE TA 25·C
=
TA-70·C
POWER RATING
0
950mW
7.6mWrC
608mW
FK
1375mW
11.0mWrC
880mW
275mW
J
1375mW
11.0mWrC
860mW
275mW
N
1150mW
9.2mWrC
736mW
W
1000mW
8.0mWrC
640mW
1ExAs
..If
INSIRUMENTS
2-738
TA=12S·C
POWER RATING
POST OFFICE BOX _
• DAUAB, TEXAS 7628IS
200mW
MC1488, SN55188, SN75188
QUAD LINE DRIVERS
SLLS094A- 01323. SEPTEMBER 1983 - REVISED MARCH 1993
recommended operating conditions
SN55188
MIN
NOM
MC1488, SN75188
MAX
MIN
NOM
MAX
UNIT
Supply voltage. VCC +
7.5
9
15
7.5
9
15
V
Supply voltage. VCC-
-7.5
-9
-15
-7.5
-9
-15
V
0.8
V
70
°C
1.9
High-level input voltage. VIH
1.9
V
0.8
Low-level input voltage. VIL
Operating free-air temperature. TA
-55
125
0
electrical characteristics over operating free-air temperature range, Vcc± =±9 V (unless otherwise
noted)
PARAMETER
VOH
VOL
High-level output voltage
Low-level output voltage
TEST CONDITIONS
V'L=0.8V.
RL= 3kO
TYpt
VCC+=9V.
VCC-=-9V
6
VCC+ = 13.2 V.
VCC_=-13.2V
9
MIN
TYpt
7
6
7
10.5
9
10.5
MAX
MAX
UNIT
V
VCC+=9V.
VCC_=-9V
V,H = 1.9V.
RL=3kO
MC1488, SN75188
SN55188
MIN
-7+
-6
-7
-6
-10.5+
-9
-10.5
-9
10
iAA
-1
-1.6
-1
-1.6
rnA
V
VCC+=13.2V.
VCC_=-13.2V
'IH
High-level input current
VI=5V
',L
Low-level input current
V, =0
IOS(H)
Short-circuit output
current at high level§
V, =0.8V.
VO=O
-4.6
-9
-13.5
-6
-9
-12
rnA
IOS(Ll
Short-circuit output
current at low level§
V, = 1.9V.
VO=O
4.6
9
13.5
6
9
12
rnA
ro
Output resistance.
power off
VCC+ =0.
VO=-2Vto2V
VCC-=O.
10
ICC+
ICC-
PD
VCC+
Supply current from ICC-
Total power dissipation
a
300
All inputs at 1.9 V
15
20
15
All inputs at 0.8 V
4.5
6
4.5
6
VCC+ = 12V.
No load
All inputs at 1.9 V
19
25
19
25
All inputs at 0.8 V
5.5
7
5.5
7
VCC+ = 15 V,
No load. TA = 25°9
All inputs at 1.9 V
34
All inputs at 0.8 V
12
VCC_=-9V.
No load
All inputs at 1.9 V
VCC_=-12V.
No load
All inputs at 1.9 V
VCC-=-15V,
No load. TA = 25°C
All inputs at 1.9 V
-34
-34
All inputs at 0.8 V
-2.5
-2.5
VCC+ =9V.
No load
VCC-=-9V.
333
333
VCC+= 12V.
No load
VCC_=-12V.
576
576
VCC+ = 9V.
No load
Supply current from
300
-13
-17
-18
All inputs at 0.8 V
-23
-0.5
rnA
34
12
-13
-17
-0.Q15
-0.5
All inputs at 0.8 V
20
-18
-23
-0.Q15
rnA
mW
t All typical values are at TA = 25°C.
:I: The algebraic convention in which the less posttive (more negative) limit is deSignated as minimum. is used in this data sheet for logic voltage
levels only. e.g .• if -6 V is a maximum. the typical value is a more negative voltage.
§ Not more than one output should be shorted at a time.
TEXAS
~
INSIRUMENTS
POST OFFICE BOX 655303 • DAUAS. TEXAS 75265
2-739
MC1488, SN55188, SN75188
QUAD LINE DRIVERS
SLLS094A- Dl323, SEPTEMBER 1983-REVISED MARCH 1993
switching characteristics, Vec:t =:1:9 V, TA = 25°C
TYP
MAX
tpLH
Propagation delay time, low-to-hlgh-Ievel output
PARAMETER
TEST CONDITIONS
220
350
ns
tpHL
Propagation delay time, hlgh-to-Iow-Ievel output
100
175
ns
tnH
Trans~lon time, low-to-high-Ievel outputt
55
100
ns
lTHL
Transkion time, hlgh-to-low-Ievel outputt
45
75
lTLH
Transkion time, low-to-hlgh-Ievel output*
lTHL
Transllon time, hlgh-to-Iow-Ievel output*
RL=3kC,
See Figure 1
MIN
CL=15 pF,
RL=3kCt07kC,
See Figure 1
CL=2500pF,
UNIT
ns
2.5
f'S
3.0
f'S
t Measured between 10% and 90% POints of output waveform.
* Measured between 3 Vand -3 V points on the output waveform (EIA R6-232-C condRlons).
PARAMETER MEASUREMENT INFORMATION
Input
Input
J1.5V
Pulse
Generator
(see Note A)
tpHL
»----.....- ......-- OUtput
T
H
14---+1 tpLH
---=~ I
I
90%1\~ 1:"l:~ ____
Output
(see
CL NoteS)
I
lTHL --..
TEST CIRCUIT
!
Figure 1. Test Circuit and Voltage Waveforms
1ExAs . "
INSIRUMENTS
POST OFFICE BOX 655303 • DALlAS, TEXAS 75265
I I
14--.. 14- lTLH
VOLTAGE WAVEFORMS
NOTES: A. The pulse generator has the following characteristics: tw = 0.5 f'S, PRR s 1 MHz, Zo = 50 C.
B. CL includes probe and jig capacttance.
2-740
\'1.5V - - - - - - 3V
~
=---.II
OV
VOH
VOL
MC1488, SN55188, SN75188
QUAD LINE DRIVERS
SLLS094A-D1323, SEPTEMBER 1983-REVISED MARCH 1993
TYPICAL CHARACTERISTICSt
OUPUT CURRENT
vs
VOLTAGE TRANSFER CHARACTERISTICS
12
OUTPUT VOLTAGE
20
Vcc+ = 12V, VCC_=-12V
vcc+ =9V, VCC_=-9V
I
6
OIl
CI
III
3 I-vcc+ =6V, VCC_=-6V
~
!i
Q.
!i
0
0
-3
0
I
I
I
I
I
~
~
8
C
~::I
4
I
~
I
!i
Q.
!i
I
.9
-6
-12
~
o
I
-/ r- - -'7V
V
0
-4
-8
/
;-
-20
2
.1_
/
/
-16
0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8
VI -Input Voltage - V
.1
/
-12
RL=3kQ
TA=25·C
-9
_t
VOL(VI = 1.9 V)
12
>
0
Vcc+ =9V
VCC_=-9V
TA=25·C
16
9
-16
--
/
I
~-
V
T3-kQ
Loaaune
I-YoH(V1 = 0.8 V)
-12
Figure 2
-8
-4
0
4
8
Vo - Output Voltage - V
12
16
Figure 3
SHORT·CIRCUT OUTPUT CURRENT
SLEW RATE
vs
vs
FREE·AIR TEMPERATURE
LOAD CAPACITANCE.\
12
1000
VCC+=9V
Vcc-= 9V
RL= 00
TA=25·C
9
IOS(L) (VI = 1.9 V)
6
fIJ
::!.
>I
;
3
100
II:
o
~
VCC+=9V
_ VCC_=-9V
-3
VO=O
-6
iii
I
II:
II)
10
I
!
IOS(H) (VI = 0.8 V)
-9
-12
-100 -75 -50 -25
1
0
25
50
75 100 125 150
10
TA - Free-Air Temperature _·c
100
1000
10000
CL - Load Capacitance - pF
Figure 4
FigureS
t Data for temperatures below O·C and above 70·C are applicable to SN55188 circuit only.
1ExAs
~
INSIRUMENTS
POST OFFICE BOX 655303 • DAUAS, TEXAS 75265
2-741
MC1488, SN55188, SN75188
QUAD LINE DRIVERS .
Su.s094A- 01323, SEPTEMBER 1983 - REVISED MARCH 1993
THERMAL INFORMATIONt
MAXIMUM SUPPLY VOLTAGE
vs
FREE-AIR TEMPERATURE
16
...........
14
,
>
I
-
............
12
r-.....
III
10
~
~
8:
::J
1/1
I
8
6
0
~
4
2
.
RL" 3 kQ (from each output to GND)
o
~
~
,
~
0
~
~
~
100
TA - Free-Air Temperature - OC
1~
Figure 6
t Data for temperatures below O'C and above 70·C are applicable to SN55188 circuit only.
APPLICATION INFORMATION
Diodes placed in series with the VCC+ and VCC- leads will
protect the SN55188/SN75188 In the fault condition In which
the device outputs are shorted to '" 15 V and the power supplies
are at low and provide low-impedance paths to ground.
Vcc+ = 12V
VCC_=-12V
Output to RTL
-0.7 V to 3.7 V
Output to DTL
-0.7V,to 5.7 V
-,.--.
~
OutputtoHNIL
-0.7Vt010V
1/4SN55188
orSN75188
Output to MOS
-10VtoOV
10kQ
-12V
Figure 7. Logic Translator Applications
Figure 8. Power Supply Protection to Meet
Power-Off Fault Conditions of
EIA Standard R8-232-C
1ExAs
2-742
..If
INSIRUMENIS
POST OFFICE BOX _
• DAUAS, TEXAS 75265
SN65C188,SN75C188
QUAD LOW-POWER LINE DRIVERS
SUS033D-
• BI-MOS Technology With TTL and CMOS
Compatibility
• Meets Standard EIA-232-D (Revision of
RS-232-C)
• Very Low Quiescent Current ••• 95 J.tA Typ
VCC± =:t12V
• Current-Umlted Output ••• 10 mA Typ
• CMOS-and TTL-Compatible Inputs
• On-Chip Slew Rate Umlted to 30 VIlAS max
• Flexible Supply Voltage Range
• Characterized at VCC ± of :t4.5 V and :t 15 V
• Functionally Interchangeable With Texas
Instruments SN75188, Motorola MC1488,
and National Semiconductor DS14C88
• ESD Protection Exceeds 1000 V Per
MIL-Std-883C Method 3015
JANUARY 1988 - REVISED
0, DBt, OR N PACKAGE
(TOP VIEW)
Vcc1A
VCC+
4B
4A
4Y
3B
2B
2Y
GND
3A
3Y
7
t The DB package Is only avalable left-end taped and reeled, I.e.,
order device SN75Cl88DBLE.
Function Tables
DRIVER 1
Lffij
description
The SN65C188 and SN75C188 are monolithic,
low· power, quad line drivers that interface data
terminal equipment with data communications
equipment. These devices are designed to
conform to Standard ANSI/EIA-232-D-1986,
which supercedes RS-232-C.
DRIVERS 2 THRU 4
y
A
B
H
L
H
H
L
H
L
X
X
L
Y
L
H
H
H =high level, L =low level, X =don't care
An external diode in series with each supply-voltage terminal is needed to protect the SN65C188 and
SN75C188 under certain fault conditions to comply with EIA-232-D (refer to Application Information).
The SN65C188 is characterized for operation from -40°C to 85°C. The SN75C188 is characterized for
operation from O°C to 70°C.
logic symbolt
1A
2A
2B
3A
3B
4A
4B
2
4
logic diagram (positive logic)
I>
3
~
1A ~ 1Y
&1>
5
2A~2Y
6
2B~
9
10
12
13
8
11
9
3A~3Y
3B~
4Y
4A
4B
t This symbol Is In accordance wHh ANSI/IEEE Sid 91-1984
and IEC Publlcatlon 617-12.
~12
11
13
4Y
posHive logic
Y = A (driver 1)
Y = AB or A+ B (drivers 21hru 4)
Copyright @ 1993, Texas Instrumenls Incorporated
TEXAS . "
INSTRUMENTS
POST OFACE BOX 655303 • DALlAS, TEXAS 75265
2-743
SN65C188, SN75C188
QUAD LOW-POWER LINE DRIVERS
SLLS0330 - 03075, JANUARY 1988- REVISED MARCH 1993
schematics of inputs and outputs
EACH OUTPuTt
EACH INPUT
--~----~._----e_-----------VCC+
vcc+----------~------
Internal
1.4-V Ref
toGND
Input A
InputB--(drivers 2, 3
(driver 1 only)
snd 4 only)
160Q
Output
GND~
,hGND
VCC-------~------~
VCC-
t All resistor values shown are nominal.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vcc+ (see Note 1) "........................................................ 15 V
Supply voltage, Vcc_(see Note 1) ......................................................... -15V
Input voltage range, VI ............................................................ VCC- to VCC+
Output voltage range, Vo ................................................ Vcc- -6 V to Vcc+ +6 V
Continuous total power dissipation ..................................... See Dissipation Rating Table
Operating free-air temperature range, TA: SN65C188 .................................. -40·C to 85·C
SN75C188 ................................... O·C to 70·C
Storage temperature range.. .. ....... ................ . .... .. .... ................. -65·C to 150·C
Lead temperature 1,6 mm (1/16 in.) from case for 10 seconds ................................. 260·C
NOTE 1: All voRage values are with respect to the network ground terminal.
DISSIPATION RATING TABLE
PACKAGE
TA,,25°C
POWER RATING
DERATING FACtOR
ABOVE TA = 25°C
TA = 70°C
POWER RATING
TA=86°C
POWER RATING
0
DB
N
950mW
525mW
1150mW
7.SmW/"C
4.2mW/"C
9.2mW/"C
S08mW
336mW
736mW
494mW
273mW
598mW
1ExAs ."
2-744
INSIRUMENTS
POST OFFICE BOX 655300 • DALLAS. TEXAS 75265
SN65C188, SN75C188
QUAD LOW-POWER LINE DRIVERS
SLlS033D - 03075, JANUARY 1988- REVISED MARCH 1993
recommended operating conditions
MIN
NOM
MAX
Supply voltage, VCC+
4,5
12
15
Supply voltage, VCC-
-4,5
-12
-15
V
VCC+
V
Input voltage, VI
VCC-+2
High-level Input voltage, VIH
0.8
ISN65C188
-40
85
I SN75C188
0
70
electrical characteristics over operating free-air temperature range, Vcc+
(unless otherwise noted)
PARAMETER
VOH
VOL
High-level output voltage
TEST CONDITIONS
VCC+=SV,
VCC_=-5V
VIL= 0.8 V,
Low-level output voltage
(see Note 2)
VIH =2V,
MIN
MAX
UNIT
V
10
VCC+=SV,
VCC-=-SV
-4
VCC+= 12\1,
VCC_=-12V
-10
V
High-level input current
VI =5V
IlL
Low-level Input current
VI =0
IOS(H)
High-level short-circuH
output current:!:
VI = 0.8\1,
Vo=Oor VCC-
-S.S
IOS(L)
Low-level short-circuH
output current:!:
VI =2\1,
Vo=Oor VCC+
5.5
IlL
Output resistance, power off
VCC+=O\l,
VCC-=O,
VCC+=5\1,
No load
VCC-=-5\1,
VCC+ = 12 \I,
No load
VCC_=-12V,
VCC+=5\1,
No load
VCC-=-5V,
VCC+=12\1,
No load
VCC-=-12V,
ICC-
°c
4
IIH
ICC+
TYpt
RL=3kO
-10
t.tA
t.tA
-10
-19.S
mA
10
19.5
mA
10
VI =-2Vt02V
V
=12 V, VCC- =-12 V
RL=3kC
VCC+= 12\1,
VCC_=-12V
V
V
2
Low-level Input voltage, VIL
Operating free-air temperature, TA
UNIT
C
300
All Inputs at 2 V or 0.8 V
90
160
All inputs at 2 V or 0.8 V
95
160
All Inputs at 2 V or 0.8 V
-90
-160
All inputs at 2 V or 0.8 V
-95
-160
t.tA
Supply current from VCC +
t.tA
Supply current from VCC-
t All tyPIcal values are at TA = 25°C.
:!: Not more than one output should be shorted at one time.
NOTE 2: The algebraic convention, in which the more positive ~ess negative) limit is designated as maximum, is used In this data sheel for logic
levels only, e.g., if a -4 V Is a maximum, the typical value Is a more negative voltage.
1ExAs ,.,
INSIRUMENTS
POST OFFICE BOX 655303 • DAllAS, TEXAS 75266
2-745
SN65C188, SN75C188
QUAD LOW-POWER LINE DRIVERS
SLLS033D - 03075. JANUARY 1988 - REVISED MARCH 1993
switching characteristics, Vcc+
=12 V, VCC- =-12 V, TA =25°C
PARAMETER
TEST CONDITIONS
tpLH
Propagation delay time, low-to-high-Ievel outputt
tpHL
Propagation delay time, high-to-Iow-Ievel oulputt
ITLH
Transition time, low-to-hlgh-Ievel output:!:
ITHL
Transition time, high-to-Iow-Ievel output:!:
ITLH
Transition time, low-to-hlgh-Ievel output§
ITHL
SR
Transition time, high-to-Iow-Ievel output§
RL=3kg,
See Figure 1
MIN
TYP
RL= 3 kg to 7 kg,
See Figure 1
MAX
3
UNIT
3.5
!.IS
!.IS
0.53
3.2
!.IS
0.53
3.2
!.IS
CL=15 pF,
CL=2500 pF,
1.5
3
1.5
3
Output slew rate§
15
30
RL=3kgt07kO,
6
CL=15 pF
t Measured at the 50% level
Measured between the 10% and 90% points on the output waveform
§ Measured between the 3 V and -3 V points on the output waveform (EIA-232-D conditions), all unused inputs tied either high or low.
!.IS
!.IS
VI!.IS
*
PARAMETER MEASUREMENT INFORMATION
Input
Input~
Pulse
Generator
(see Note A)
\~;v-----
."
r
~tpHL~ tpLH
Output
CL
(see Note B)
Output
----~~~
60%
:X
,
t-rHL...,I *-
TEST CIRCUIT
ill'
60%
_ 10% 1
LI _____
...,I *-ITLH
VOLTAGE WAVEFORMS
NOTES: A The pulse generator has the following characteristics: tw = 25 !.IS, PRR = 20 kHZ, Zo = 50 g, tr = tf '" 50 ns.
B. CL includes probe and jig capacitance.
Figure 1. Test Circuit and Voltage Waveforms
1ExAs
..If
INSTRUMENTS
2-746
POST OFFICE BOX 655303 • DAUAS. TEXAS 75265
3V
OV
VOH
VOL
SN65C188,SN75C188
QUAD LOW·POWER LINE DRIVERS
SLLS033D - 03075, JANUARY 1988- REVISED MARCH 1993
TYPICAL CHARACTERISTICS
OUTPUT CURRENT
VS
VOLTAGE TRANSFER CHARACTERISTICS
1S
20
Vee", = ",1SV
"'"
"'"
12 f- Vee",=",12V
>
I
9 f- Vee",=",9V
.~
I
_I,
6 f- Vee",="'SV
co
!i
Q.
!i
0
16
0
I
I
U
!i
Vcc",="'SV-
-3
I
~
!.Vee",I = ",9! V,_
-6
-9
-
RL=3kQ
TA=25·e
I
o
I
I
~
0
I
.9
0
-8
-12
Vee", = ",SV-
-16
I
I
-20
-16
1.2 1.4 1.6 1.8 2
/
4
-4
/
L
I
-12
-- ---..
!
VOH (VI = 0.8 V)
-8
-4
C
~::I
u
~
0
s::
.c
III
I
III
9
/
8
12
16
OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATUREt
FREE-AIR TEMPERATUREt
- -----
I
12
I
10 f- IOS(L)
VI=2V
Vo=oorVee+
S
I
I
I
I
VOH (Vee", = ",12 V, VI = 0.8 V)
8
...
I
I
RL=3kQ
>I
&
4 I- VOH (Vee", = ",S V, VI = 0.8 V)
~
0
!!
0
i
~
~0
4
-...L
vs
Vee",=",12V
'S
/
V
Figure 3
SHORT-CIRCUIT OUTPUT CURRENT
I
0
"
Vo - Output Voltage - V
Figure 2
~
I
~Loadune
VI -Input Voltage - V
1S
h
V) -
I
8
Vee", = ",12V
I
0.2 0.4 0.6 0.8 1
J.VOL = I(VI = 1
2
12
"""
3
Vee", =",12V
TA=25·e
c(
E
011
II
s::
~
OUTPUT VOLTAGE
::I
0
-S
I
IOS(H)
-10 ,.... VI,. 0.8 V _
--
I--
~
-
-4 _ VOL(Vee", = ",sv, VI =2Vl
-8
VOL (Vee", = ",12V,VI =2V:
Vo=OorVee_
-1S
-40 -20
0
20
40
60
80
100
120
-12
-40
I
-20
TA - Free-Air Temperature -·e
0
20
40
60
80
100
120
TA - Free-Air Temperature -·e
Figure 4
FigureS
t Only the O·C to 70·C portion of the curves applies to the SN75C188,
1ExAs
..If
INSIRUMENTS
POST OFACE BOX 655303 • 0AllAS, TEXAS 75265
2-747
SN65C188, SN75C188
QUAD LOW-POWER LINE DRIVERS
J
SUS033D - 03075, JANUARY 1988 - REVISED MARCH 1993
TYPICAL CHARACTERISTICS
POWER-OFF OUTPUT RESISTANCE
INPUT CURRENT
120
100
vs
vs
FREE-AIR TEMPERATUREt
FREE-AIR TEMPERATUREt
500
1\
'\
80
~
I'...
CI
........
450
I
20
=
0
I
~
::I
40
C
l:
U
I
475
!>
Q,
.5
..
60
I
VCC+=VCC-= 0
Ii
I
I
VCC",=",12V
IIH VI=5V
o
I
V
--.:::; ::.
=-2V~
425
I"-VO=2V
400
375
350
In.. VI = 0
-20
325
V'
-40
300
-40 -20
0
20
40
60
100
80
TA - Free-Air Temperature
120
-20
-40
_·c
0
20
Figure 6
vs
FREE-AIR TEMPERATUREt
V~C",="'12VI~
VCC",=",12V
u
~
RL= 00
VI =O,8Vor2V
>'
I
S
40
I
-40
~
iii
io
z
i
-80
I
8"
10
Slew Rate
Negative
I
II:
I
I
VCC",=",5V
I
UI
ICC-
..........
-120
-40 -20
o
VCC", = ",12V
20
40
60
80
100
120
:111111111
-40
-20
0
20
40
60
80
TA - Free-Air Temperature _·C
TA - Free-Air Temperature - ·C
Figure 8
Figure 9
t Only the O·C to 70·C portion of the curves applies to the SN75C188,
1ExAs
~
INSIRUMENTS
2-748
CL=15pF
25
80 ICC+'- VCC",=",5V
o
120
OUTPUT SLEW RATE
Slew Rate
j
100
FREE-AIR TEMPERATUREt
120
JJ
80
vs
,
~
Q,
60
Figure 7
SUPPLY CURRENT
I
40
TA - Free-Air Temperature - ·C
POST OFFI.CE BOX 655303 • DAUAS, TEXAS 75265
100
120
SN65C188,SN75C188
QUAD LOW-POWER LINE DRIVERS
SlLS0330 - 03075, JANUARY 1988 - REVISED MARCH 1993
TYPICAL CHARACTERISTICS
PROPAGATION DELAY TIME
vs
FREE-AIR TEMPERATUREt
FREE-AIR TEMPERATUREt
2
..
.
RL=3 kC
1.5
CL=15 pF
,
~
c
-tpL
0
ii01
0.
I--
S
i
..
..
L -RL=7kC
~
1.25
1=
i
III
1.5
I
J -RL=3kC
Q
I
I
~
i
V
I
I
VCC±=±12V
1=
£
I
I
VCC+ = 12V
1.75 I-VCC_=-12V
RL=3kCto7kC
~I
I
I
2
..-RL=7 kC
tpHL
~
E
OUTPUT TRANSITION TIME
vs
~
~
tni~-
trLH
tnil-
~L=2500PF
C =15 F
tn.H
0.75
I
0.5
0.5
..0.
0.25
o
-40
-20
0
20
40
60
80 100
TA - Free-Air Temperature _·C
o
120
-40
-20
0
20
40
60
80
100
120
TA - Free-Air Temperature - ·C
Figure 10
Figure 11
t Only the O·C to 70·C portion of the curves applies to the SN75C188.
--9TT
--9TT
--VT
APPLICATION INFORMATION
___
OutputtoRTL
-0.7
Vto 3.7 V
1/4 'Cl88
-=
3V
___
Input From
TTL, DTL,
or CMOS
OutputtoDTL
-0.7VtoS.7V
1/4 'Cl88
-=
SV
___
1/4'Cl88
OutputtoHNILor
l()'VCMOS
-0.7Vtol0V
--~
--1/4 'Cl88
VCC,.=±12V
1 kC
-=
OutputtoMOS
-10VtoOV
10 kC
-12V
Figure 12. Logic Translator Applications
1ExAs
~
INSIRUMENTS
POST OFFICE BOX 655303 • DAllAS, TEXAS 75265
2-749
SN65C188,SN75C188
QUAD LOW·POWER LINE DRIVERS
SlLS033D - 03075, JANUARY 1988 - REVISED MARCH 1993
APPLICATION INFORMATION
--
T
.,15V
T Vcc+
Output
SN75C188
........
__ 1
1 Vcc-
v~C+
..L
-
SN75C188
_-....J
..... 1
I
Vcc-
..l
NOTE: Extemal diodes placed in series with the VCC+ and VCC_leads will protect the SN75C188 in thefaull condition where the device outputs
are shorted to., 15 V and the power supplies are at low voltage and provide low-Impedance paths to GND.
Figure 13. Power Supply Protection to Meet Power·Off
Fault Conditions of Standard EIA·232·D
1ExAs
..If
INSIRUMENIS
2-750
POST OFFICE
sox 655303 •
DALLAS.
'fEl 1993, Texas Instruments IncO 0 - - Open
Response Control Open
ICC Is tested for all four receivers Simultaneously,
Figure 2. IIH , IlL, Icc
VCC
Response
Control
Open
Figure 3. los
t Arrows indicate actual direction of current flow. Current into a terminal is a positive value.
1ExAs
2-754
.Jf
INSIRUMENTS
POST OFFICE BOX 655303 • DAUAS. TEXAS 75265
--
MC1489, MC1489A, SN55189, SN55189A, SN75189, SN75189A
QUAD LINE RECEIVERS
SLLS095A - 01619, SEPTEMBER 1973 - REVISED MARCH 1993
PARAMETER MEASUREMENT INFORMATION
VCC
Pulse
Generator
(see Note A)
(see Note C)
Reeponee
Control
Open
TEST CIRCUIT
r--"
14~I
I rl
________
..,:
,,10 ns ---'
Input
1~J(~
---.;~
Output
10 ns
~~~~--------4
I
I
.... tpHI.~
14- tPI.H-4
~I
-----.. . .1'. :1
90%
trHI.
V
I 50%
I 1~
I I
ov
I 90%
_ _ _ .....1 ___
I
I
50%
1~
VOH
VOl.
14- trl.H ~
--J 14-
VOI.TAGE WAVEFORMS
NOTES: A. The pulse generator has the following characteristics: Zo = 50
B. CI. includes probe and jig capacitances.
C. All diodes are 1N3064 or equivalent.
Q,
tw = 500 ns.
Figure 4. Test Circuit and Voltage Waveforms
TEXAS ...,
INSIRUMENTS
POST OFFICE BOX 655303 • DAllAS. TEXAS 75265
2-755
MC1489, MC1489A, SN55189, SN55189A, SN75189, SN75189A
QUAD LINE RECEIVERS
Su.s095A- 01619. SEPTEMBER 1973 - REVISED MARCH 1993
TYPICAL CHARACTERISTICS
OUTPUT VOLTAGE
vs
INPUT VOLTAGE
6
RC=SkQ
VC=SV
VT-
o
RC=13kQ
VC=SV
VT+
VT-
VT-
VT+
.... ....
'--
-3
-2
-1
RC=11 kQ
VC=-SV
RC = co
VT+
VT-
VT+
'--
'---
2
0
VI-Input Voltage - V
VCC=SV
TA = 25°C
See Figure 1
....
3
4
S
FigureS
OUTPUT VOLTAGE
vs
INPUT VOLTAGE
6
RC=SkQ
VC=SV
VT-
o
-3
VT-
VT+
-2
-1
VT-
VT+
o
2
VI -Input VoHage - V
Figure 6
2-756
RC=11 kQ
VC=-SV
RC= co
VCC=SV
TA=25°C
See Figure 1
VT+
3
4
5
MC1489, MC1489A, SN55189, SN55189A, SN75189, SN75189A
QUAD LINE RECEIVERS
SUS095A- 01619. SEPTEMBER 1973 - REVISED MARCH 1993
TYPICAL CHARACTERISTICSt ,
INPUT THRESHOLD VOLTAGE
INPUT THRESHOLD VOLTAGE
vs
vs
FREE-AIR TEMPERATURE
SUPPLY VOLTAGE
2.4
2
2.2
2
>
I
...co
f"".. ..........
.......... ~89AVT+
1.8
~
'a
'0
1
s:.
1.6
r---.. ..... ~I+
1.4
r-:: ~
1.2
I-
'SQ.
.5
>I
I ' ........
II
~
,~~
0.8
I I
0.6
' 89A r+
1.8
...
1.4
~
1.2
I
I'
1.6
1
'89VT_
'89VT+
:!!
0
...........
1
~
...........
'SQ.
::::: :---........ --.:
'89AVT_
0.8
0.6
.5
0.4
0.2
0.4
-100 -75 -50 -25 0 25 50 75 100 125 150
TA - Free-Air Temperature _ ·e
o
2
3
4
5
6
7
8
VCC - Supply Voltage - V
Figure 7
Figure 8
SN75189
SN75189A
NOISE REJECTION
NOISE REJECTION
6
5
>
4
I
I
/
2
CC=10pF
10
I
I 1111
>I
Ce = 500 pF
-8
j
) ~\
~
/
I-- -
o
I "" I
~ ~,
\
3
5
Ce = 300 pF
i5.
~
6
Vec .. 5V
TA=25·C
See Note A
\\
4
\
\
~
1\
3
I 111111
,
e~ = lac:ol ~~
\
Cc =500pF
t>< ~~
.... '"
CC=12 PF I
2
vec =sV
TA=25·e
See Note A
\
\
i5.
~
:::::.. r--.
'r--.
10
9
~
1.Hi
I IIIII
"-
I'
I
CC=1oopF
ee=1oopF
II "III
40
100
400 1000
4000 10000
o
10
tw - Pulse Duration - ns
40
100
400
1000
4000 10000
tw - Pulse Duration - ns
Figure 9
Figure 10
t Data for free-air temperatures below o·e and above 70·e are applicable to SN55189 and SN55189A circuKs only.
NOTE A: This figure shows the maximum amplitude of a positive-going pulse that, starting from 0 V. will not cause a change of the output level.
1ExAs
-If
INSIRUMENIS
POST OFFICE BOX 655303 • DAUAS. TEXAS 75265
2-757
MC1489, MC1489A, SN55189 j SN55189Aj SN75189, SN75189A
QUAD LINE RECEIVERS
SLLS095A- 01619, SEPTEMBER 1973 - REVISED MARCH 1993
TYPICAL CHARACTERISTICS
INPUT CURRENT
va
INPUT VOLTAGE
10
8
6
CC
E
4
I
2
vch=~v
I
Control Opel'!
TA 25°C
=
/
./
/'
I
0
'!i
Go
.5
I
=
/
0
V
-2
/~
-4
-6
-8
V"
/
"
-10
-25 -20 -15 -10 -5 0
5 10
VI -Input Voltage - V
15
Figure 11
2-758
1ExAs'"
INSIRUMENTS
POST OFFICE BOX 655303 • DAUAS, TEXAS 75265
20
25
SN65C189,SN65C189A,SN75C189,SN75C189A
QUAD LOW-POWER LINE RECEIVERS
SLLS041C - 031
• Meets Standard EIA-232-D (Revision of
RS-232-C)
OCTOBER 1988 - REVISED MARCH 1993
0, OBt, N, OR NSt PACKAGE
(TOP VIEW)
• Low Supply Current .•• 420 !AA Typ
• Preset On-Chip Input Noise Filter
Vee
• Built-In Input Hysteresis
• Response and Threshold Control Inputs
4A
4CONT
4Y
3A
3CONT
3Y
1Y
2A
• Push-Pull Outputs
• ESD Protection Exceeds 500 V Per
MIL-STD-883C, Method 3015
2Y
GND
t The DB and NS packages are only available left-end taped and
• Functionally Interchangeable and Pin
Compatible WHh Texas Instruments
SN75189/SN75189A, Motorola
MC1489/MC1489A, and National
Semiconductor DS14C88A
reeled, i.e., order SN_5CI89AOBLE or SN_5CI89ANSLE.
logic symbol:!:
description
2
1 CONT
The SN65C189, SN65C189A, SN75C189, and
SN75C189A are low-power bipolar quad line
receivers that are used to interface data terminal
equipment (DTE) with data circuit-terminating
equipment (DCE). These devices have been
designed to conform with Standard ANSI!
EIA-232-D-1986, which supersedes RS-232"C.
The SN65C189 and SN75C189 have a 0.33 V
typical hysteresis compared with 0.97 V for the
SN65C189A and SN75C189A. Each receiver has
provision for adjustment of the overall input
threshold levels. This is achieved by choosing
external series resistors and voltages to provide
bias levels for the response control pins. The
output is in the high logic state if the input is left
open circuited or shorted to ground.
2A
2CONT
3A
3CONT
4A
4CONT
.D'
1
lA
3
THRESHOLD
ADJUST
4
6
5
10
8
9
13
11
12
1Y
2V
3V
4V
:I: This symbol is in accordance with ANSVIEEE SId 91-1984 and
IEC Publication 617-12.
logic diagram (each receiver)
A
Response
Control
----D>o-v
~
These devices have an on-chip filter that rejects input pulses of shorter than 1-1lS minimum duration. An external
capaCitor may be connected from the control pins to ground to provide further input noise filtering for each
receiver.
The SN65C189, SN75C189, SN65C189A, and SN75C189A have been designed using low-power techniques
in a bipolar technology. In most applications, these receivers will interface to single inputs of peripheral devices
such as UARTs, ACEs, or microprocessors. By using sampling, such peripheral devices are usually insensitive
to the transition times of the input signals. If this is not the case or for other uses, it is recommended that the
SN65C189, SN75C189, SN65C189A, and SN75C189A outputs be buffered by single Schmitt input gates or
single gates of the HCMOS, ALS, or 74F logic families.
The SN65C189 and SN65C189A are characterized for operation from-40·C to 85·C. The SN75C189 and
SN75C189A are characterized for operation from O·C to 70·C.
Copyright © 1993, Texas Instruments Incorporated
TEXAS .."
INSIRUMENfS
POST OFFICE BOX 655303 • DAUAS, TEXAS 75265
2-759
SN65C189,SN65C189A,SN75C189,SN75C189A
QUAD LOW-POWER LINE RECEIVERS
SLLS041C-D3144, OCTOBER 1988-REVISED MARCH 1993
schematic of inputs and outputs
EQUIVALENT OF EACH INPUTt
EQUIVALENT OF EACH OUTPUT
Input
- - - - - - - - -......- - - VCC
Response_......_-I
Control
"'--4_-
Output
t All resistor values shown are nominal.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) ............................................................. 7 V
Input voltage range, VI ............................................................. -30 V to 30 V
Output voltage range ....................................................... -0.3 Vto Vee + 0.3 V
Continuous total dissipation ........................................... See Dissipation Rating Table
Operating free-air temperature range: SN65C189, SN65C189A ......................... -40°C to 85°C
SN75C189, SN75C189A ........................... O°C to 70°C
Storage temperature range ....................................................... -65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds ............................... 260 0 e
NOTE 1: All voltages are with respect to the network ground terminal.
DISSIPATION RATING TABLE
TA=25·C
POWER RATING
DERATING FACTOR
ABOVE TA. 25·C
TA=70·C
POWER RATING
TA=85·C
POWER RATING
D
DB
950mW
608mW
494mW
N
1150 mW
NS
500mW
7.6mwrC
4.2mwrc
9.2mWrC
4.0mWrC
PACKAGE
525mW
336mW
273mW
736mW
596mW
320mW
260mW
recommended operating conditions
I
Supply voltage, VCC
Input voltage, VI (see Note 2)
MIN
NOM
MAX
4.5
5
6
-25
25
UNIT
V
V
High-level output current, IOH
-3.2
mA
Low-level output current, IOl
3.2
",1
mA
Response control current
Operating free-air temperature, TA
I SN65C189, SN65C189A
I SN75C189, SN75C189A
-40
85
0
70
rnA
·C
NOTE 2: The algebraiC convention, where the more positive (less negative) limit Is designated as maximum, IS used In thiS data sheet for logiC
levels only, e.g., 1f-10 Vis a maximum, the typical value is a more negative voltage.
2-760
POST OFFICE BOX 655lI03 • DAlLAS. TEXAS 75265
SN65C189,SN65C189A,SN75C189,SN75C189A
QUAD LOW-POWER LINE RECEIVERS
SLLS041C- 03144, OCTOBER 1988-REVISED MARCH 1993
electrical characteristics over recommended free-air temperature range, Vee = 5 V :1:10% (unless
otherwise noted) (see Note 3)
PARAMETER
Vr+
Positive-going threshold voltage
Vr-
Negative-going threshold voltage
Vhys
Input hysteresis
VOH
High-level output voltage
TEST CONDITIONS
'C189
'C189A
'C189
'C189A
'C189
'C189A
See Figure 1
VCC = 4.5 Vlo 6 V,
10H =-20 tAA
VI = 0.75 V,
VI = 0.75 V,
IOH=-3.2mA
VI= 3V,
VCC = 4.5Vt06V,
10L = 3.2 rnA
IIH
High-level input current
See Figure 2
IlL
Low-level input current
lOS
Short-Circuit output current
See Figure 3
Supply current
VI = 5V,
See Figure 2
ICC
See Figure 2
MAX
1.5
1.6
2.25
1.25
0.75
See Figure 1
loW-level output voltage
TYpt
1
0.75
See Figure 1
VOL
MIN
1
0.15
0.33
0.65
0.97
1.25
3.5
V
V
2.5
0.4
3.6
8.3
1
VI =-25V
-3.6
-8.3
VI=-3V
-0.43
-1
VI=3V
V
V
0.43
VI=25V
UNIT
No load,
420
V
rnA
rnA
-35
rnA
700
..,A
t All typical values are at TA = 25·C.
NOTE 3: All characteristics are measured with response control terminal open.
switching characteristics, Vee
=5 V :1:10%, TA =25°e
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tpLH
Propagation delay time, low-to-high-Ievel output
6
lIS
tpHL
Propagation delay time, high-to-Iow-Ievel output
6
ITLH
Transition time, low-to-high-Ievel output*
500
lIS
ns
ITHL
Transition time, high-to-Iow-Ievel output*
300
ns
tw(N)
Duration of longest pulse rejected as noise§
6
lIS
*
RL=5kC,
CL=50pF,
See Figure 4
1
Measured between 10% and 90% points of output waveform.
§ The intent of this specification Is that any input pulse of less than 1 lIS will have no effect on the output, and any pulse duration of greater than
6 lIS will cause the output to change state twice. Reaction to a pulse duration between 1 lIS and 6 lIS Is uncertain.
'lExAs . "
INSIRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2-761
SN65C189,SN65C189A,SN75C189,SN75C189A
QUAD LOW·POWER LINE RECEIVERS
SLL.S041C-D3144, OCTOBER 1988-REVISED MARCH 1993
PARAMETER MEASUREMENT INFORMATIONt
VCC
Response
VOL
Control
,~
__________
--JA~
__________
1
~
Open
Unl_
Otherwise
Specified
I-VC
.I.
+Vc
Figure 1, VT+. VT_. VOH. VOL
X)--
Open
Reeponse
Control
Open
Figure 2, IIH • IlL. Icc
VCC
+-108
Response
Control
Open
FIgura 3, los
t Arrows Indicate actuai direction of current flow. Current into.a terminal is a positive value.
1ExAs
..If
INSIRUMENTS
2-762
POST OFFICE BOX 655303 • DAUAS, TEXAS 75265
lOLl
SN65C189,SN65C189A,SN75C189,SN75C189A
QUAD LOW-POWER LINE RECEIVERS
SLLS041C-D3144. OCTOBER 1988-REVISED MARCH 1993
PARAMETER MEASUREMENT INFORMATION
Vee
Pulse
Generator
(see Note A)
' > O - - -.......--1~ Output
I
_
Response
Control
Open
CL=50pF
(see Note 8)
-=
TEST CIRCUIT
Input
~"1-.5-V--1-.5"""'V~-- - - - - - - - - 1
tpHL
1
~I
14
----"""'1\1
1+14--~~1- tPLH
1
1:1 =,,:----1
90
r::::
VOH
1
1
10%
10%
1
1 I\....:.::.:;...~:.:::JI-I------- VOL
90" 1
Output
::
lTHL -+I
1.5V
I+-
1.5V
---.I 14- lTLH
VOLTAGE WAVEFORMS
Figure 4. Test Circuit and Voltage Waveforms
NOTES: A. The pulse generator has the following characteristics: Zo =50 O.lw =25 iJ8.
B. CL includes probe and jig capacitances.
1ExAs
~
INSJRUMENTS
POST OFFICE BOX fl66303 • DALLAS. TEXAS 75265
2-763
SN65C189, SN65C189A, SN75C189, SN75C189A
QUAD LOW-POWER LINE RECEIVERS
SLLS041C - 03144, OCTOBER 1988 - REVISED MARCH 1993
TYPICAL CHARACTERISTICS
SN75C189
POSITIVE-GOING THRESHOLD VOLTAGE
SN75C189A
POSITIVE-GOING THRESHOLD VOLTAGE
va
FREE-AIR TEMPERATUREt
va
FREE-AIR TEMPERATUREt
1.5
2.4
J L
VCC=5.5V
I
I
VCC=5.5V
2.2
>I
•
>
1A
I
III
"
.c
I
- ---
I
15
•
1.3
~
f=
r--
"
1.B
I
1.6
If=
I
t
2
~
r--~
,:!:
1.2
>
1.4
1.1
-40
1.2
-20
20
0
40
60
80
-40
100
-20
0
Figure 5
40
60
80
100
Figure 6
SN7SC189A
NEGATIVE-GOING THRESHOLD VOLTAGE
SN7SC189
NEGATIVE-GOING THRESHOLD VOLTAGE
1.2
20
TA - Free-Air Temperature - ·C
TA - Free-Air Temperature _·C
va
va
FREE-AIR TEMPERATUREt
FREE-AIR TEMPERATUREt
., ,
1,15
-' J
VCC=5.5V
VCC=5V
1.1
>I
•
>I
1.1
•
III
•
~
!!
I
~
I
tl
>
I
- -- ---
1.05
,
~
.c
~
1----
I
0.95
-=-
~
~
f.-- ...-
tl
0.9
>
0.9
0.8
~~
~
020
40
60
80
100
0.85
-40
-20
20
Figure 8
Figure 7.
t Only the O·C to 70·C portion of the curves applies to the SN75'.
1ExAs . "
2-764
0
40
60
TA - Free-Alr Temperature _·c
TA - Free-Air Temperature - ·C
INSIRUMENTS
POST OFFICE BOX 655303 • DAUAS, TEXAS 75265
so
100
SN65C189,SN65C189A,SN75C189,SN75C189A
QUAD LOW·POWER LINE RECEIVERS
SLLS041 C - 03144. OCTOBER 1988 - REVISED MARCH 1993
TYPICAL CHARACTERISTICS
SN75C189A
INPUT HYSTERESIS
SN75C189
INPUT HYSTERESIS
va
va
FREE-AIR TEMPERATUREt
FREE-AIR TEMPERATUREt
0.40
1.2
.1 1
0.38 I-- VCC = 5V
1.1
r-
I
VCC=5V
0.36
>I
1
0.34
--
0.32
>I
r-.....
.
0.9
i
0.8
'S
0.7
.!II
~
0.30
'S
0.28
:z:
0.26
'"
.5
'"
.5
0.5
0.22
0.20
-60 -40 -20
0
20
40
60
60
0.4
-40
100 120
-20
TA - Free-Air Temperature _·c
20
40
60
80
0
TA - Free-AIr Tempereture _·c
Figure 9
.
I
COl
va
FREE-AIR TEMPERATUREt
FREE-AIR TEMPERATUREt
3.8
VCC=4.5V
3.6 I-- IOH = -3.2 mA
V,=0.75V
~
3.4
'S
'S
3.2
3.6
>I
~
'"
LOW-LEVEL OUTPUT VOLTAGE
va
.I.
I
t--
--
..
QI
3.4
~
3.2
0
3
-
'S
-S'"
3
.c
!P
2.8
]
2.8
I
2.6
!
2.6
~
:z:
:z:
I
r-
J.
VCC=4.5V
IOH = -3.2 mA
VI=3V
~
0
'ii
_i"""
100
Figure 10
HIGH-LEVEL OUTPUT VOLTAGE
>
,
0.6
0.24
3.8
.......
I!!
S
~
........ r--....
.p
--
--
~
..J
.p
2.4
2.2
-40
-20
0
20
40
60
80
2.4
2.2
-40
100
-20
TA - Free-Air Temperature - ·C
0
20
40
60
80
100
TA - Free-Air Temperature - ·C
Figure 11
Figure 12
t Only the O·C to 70·C portion of the curves applies to the SN7S·.
TEXAS
..If
INSIRUMENTS
POST OFFICE SOX 655303 • DAll.AS.
b
75265
2-765
SN65C189, SN65C189A, SN75C189, SN75C189A
, QUAD LOW-POWER LINE RECEIVERS
SUS041C-D3144. OCTOBER 1988-REVISED MARCH 1993
TYPICAL CHARACTERISTICS
SN75C189
HIGH-LEVEL INPUT CURRENT
0.7
~
SN75C189A
HIGH-LEVEL INPUT CURRENT
va
va
FREE-AIR TEMPERATUREt
FREE-AIR TEMPERATUREt
0.65
1.
I
VCC=4.SV
VI=3V
~
0.65
C
~
0.6
:I
u
S
-
-......
0.55
1
~
0.6
I
1
I
'S
a.
VCC = 4.5 V
VI=3V
"
......
" --.......
0.5
J:
I
~ 0.45
0.4
-40
....
0.55
1
S
0.5
~
CI
0.45
~
0.4
s:I
-20
0
20
40
60
SO
TA - Free-AJr Temperature - ·C
.............
~
'0.35
-40
100
~ r-.......
-20
0
vs
va
FREE-AIR TEMPERATUREt
FREE-AIR TEMPERATUREt
-0.2
vcb=4.st
_ VI=3V
i
E -0.3
I
-0.4
---
-0.5
-0.6
I
~ -0.7
- 0.8
-40
-20
'0
V
20
§
--
-0.4
U
'Sa.
S -0.5
!ii
~
~
-
....-
-0.6
, I
40
60
SO
100
-0.8
-40
~
,-
-------
'i
-20
0
20
40
60
TA - Free-Air Temperature -'C
Figure 15
. Figure 16
Only the O·C to 70'C portion of the curves applies to the SN7S·.
1ExAs ."
2-766
",--
~ -0.7
TA - Free-Air Temperature _·c
t
J.
I
C
U
i&
100
VCC=4.5V
_ VI=3V
c(
I
1
S
SO
SN75C189A
LOW-LEVEL INPUT CURRENT
-b.2
I
60
Figure 14
SN75C189
LOW-LEVEL INPUT CURRENT
E -0.3
40
TA - Free-Air Temperature - ·C
Figure 13
c(
20
'"
INSIRUMENTS
POST OFFICE BOX 655303 • DAUAS. TEXAS 75265
SO
100
SN65C189,SN65C189A,SN75C189,SN75C189A
QUAD LOW-POWER LINE RECEIVERS
SUS041 C - 03144, OCTOBER 1988 - REVISED MARCH 1993
TYPICAL CHARACTERISTICS
LOW-LEVEL SHORT-CIRCUT OUTPUT CURRENT
VB
FREE-AIR TEMPERATUREt
HIGH-LEVEL SHORT-CIRCUT OUTPUT CURRENT
VB
FREE-AIR TEMPERATUREt
~
o
1
i
g
1
~s::
I
In
~ ~r---r---~--.---.---'---'---,
I
J
J
I
i1
VCC = 5.5 V
-2 f-- VO=O
§
o
VCC=5.5V
25 I - VI
=0
-t--I--II--I---+----1
g 2O~-r_-+---+--+---+_-~-~
-4
-6
i1
--
-8
-10
In
i
-12
.3
:c
1
-14
j
-16
-40
15
101--r---+--+--+---+--~-,
51--r---+--+---+--+--~-,
1
°
::J'
-20
02040
60
80
9
100
o~--~--~--~--~--~--~--~
-40
-20
0
Figure 17
700
c(
I
r-
5
J
af
E
10
:I.
1=1
I
500
GiS
]!o
400
r---...... r-
:I
In
1
300
~
200
t=' &.
~o
0-
-
-
-40
4.5
I
r-
I
VCC=4.5V
CL=50pF
4
10
1;; ~ 3.5
li~
r--
c:a..c
o 01
Q:X
1 S
:5
~
f;...1
3
I----~
r2.5
100
o
100
VB
I
c:a.
c:a.
80
FREE-AIR TEMPERATUREt
VCC=5.5V
VI=5V
0
60
PROPAGATION DELAY TIME,
LOW-TO-HIGH LEVEL OUTPUT
600
:I.
40
Figure 18
SUPPLY CURRENT
VB
FREE-AIR TEMPERATUREt
800
20
TA - Free-Air Temperature - ·C
TA - Free-Alr Temperature - ·C
-20
0
20
40
60
80
100
2
-40
-20
TA - Free-Air Temperature - ·C
Figure 19
0
20
40
60
80
TA - Free-Air Temperature _·C
100
Figure 20
t Only the O·C to 70·C portion of the curves applies to the SN75'.
TEXAS . "
INSIRUMENfS
POST OFFICE
BOX 655303 •
DAUAS. TEXAS 75265
2-767
SN65C189, SN65C189A, SN75C189, SN75C189A
QUAD LOW-POWER LINE RECEIVERS
SLJ.S041C-D3144, OCTOBER 1988-REVlSED MARCH 1993
TYPICAL CHARACTERISTICS
TRANSITION TIME,
LOW-TO-HIGH-LEVEL
PROPAGATION DELAY TIME,
HIGH-TQ..LOW-LEVEL OUTPUT
va
va
FREE-AIR TEMPERATUREt
FREE-AIR TEMPERATUREt
..
4
I
I
VCC-4.5V
3,9 I-- CL=50pF
::I.
I
~.c
400
I
I
VCC=4.5V
350 f-- CL=50pF
9J
l
300
ai
250
~
....-
E
.......
1=
c
r--~
~
~
I
~
-20
200
I!II
3.3
3
-40
./
0
20
40
60
80
TA - Free-Alr Temperature - ·C
100
V
""""
--
V
100
-40
-20
0
20
40
60
80
TA - Free-Air Temperature - ·e
Figure 22
TRANSITION TIME,
HIGH-TO-LOW-LEVEL OUTPUT
::I.
vs
FREE-AIR TEMPERATUREt
200
I
S
I
9J
180 -
I
I
Vee =4.5V
CL=50pF
160
140
:c
ai
E
1=
c
0
i!
I!II
120
80
..
80
j!:
,......
100
~
I
oJ
40
-40
_I-
/
-20
0
20
40
60
80
TA - Free-Alr Temperature - ·C
Figure 23
t Only the o·e to 70·e portion of the curves applies to the SN75'.
1ExAs
.Jf
INSTRUMENTS
2-768
/'
150
Figure 21
.
V
POST OFFICE BOX 655303 • DAUAS. TEXAS 75265
100
100
SN75ALS191
DUAL DIFFERENTIAL LINE DRIVER
1987 - REVISED AUGUST 1989
•
•
•
•
•
•
o OR P PACKAGE
Meets EIA Standard RS-422-A
High Speed, Low-Power ALS Design
TTL-and CMOS-Input Compatibility
Single 5-V Supply Operation
Output Short-Circuit Protection
Improved Replacement for the uA9638
(TOP VIEW)
VCC
1A ( 2J 8 1
7 Y
1Z
2A 3
6 2Y
GND
4
5 2Z
description
FUNCTION TABLE
The SN7SALS191 is a dual high-speed differential
line driver designed to meet EIA Standard
RS-422-A. The inputs are TIL- and CMOScompatible and have input clamp diodes.
Schottky-diode-clamped transistors are used to
minimize propagation delay time. This device
operates from a Single S-V power supply and is
supplied in 8-pin packages.
The SN7SALS191 is characterized for operation
from Q·C to 7Q·C.
(each driver)
INPUT
logic symbol t
1A
2A
2
3
~
1Y
7
1Z
6
'ZY
5
2Z
Y
Z
H
H
L
L
L
H
logic diagram (positive logic)
1A
8
OUTPUTS
A
2
t>d
1Y
1Z
6
2
2A
l>t=i:
tThis symbol is in accordance with ANSI/lEEE SId 91-1984
and IEC Publication 617-12.
Copyright © 1989. Texas Instruments Incorporated
TEXAS . "
INSIRUMENTS
POST OFFICE BOX 655303 • DAlLAS. TEXAS 75265
2-769
SN75ALS191
DUAL DIFFERENTIAL LINE DRIVER
SLLS032A- 03068, DECEMBER 1987 - REVISED AUGUST 1989
schematics of inputs and outputs
EQUIVALENT OF EACH INPUT
TYPICAL OF ALL OUTPUTS
VCC
VCC--------------.---~~--
4OkO NOM
Input ---4t_~~t_--+____l
100
Output
GND
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) ............................................................. 7 V
Input voltage, VI ............................................................................ 7 V
Continuous total dissipation ........................................... See Dissipation Rating Table
Operating free-air temperature range .................................................. O°C to 70°C
Storage temperature range ....................................................... - 65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds ............................... 260°C
NOTES: 1. All voltage values except differential output voltage VOD are with respect to network ground terminal.
DISSIPATION RATING TABLE
PACKAGE
TA:s:25"C
POWER RATING
DERATING FACTOR
ABOVE TA 25"C
=
D
725mW
5.8mWrC
464mW
p
1000mW
8.0mWrC
640mW
ThxAs
..If
INSIRUMENTS
2-770
TA=70°C
POWER RATING
POST OFFICE BOX 655303 • DAu.AS, TEXAS 75265
SN75ALS191
DUAL DIFFERENTIAL LINE DRIVER
SLLS032A- D3068. DECEMBER 1987 - REVISED AUGUST 1989
recommended operating conditions
Supply voltage. VCC
MIN
NOM
MAX
4.75
5
5.25
High-level input vottage. VIH
UNIT
V
V
2
Low-level input voltage, VIL
0.8
V
-50
rnA
Low-level output current, 10L
50
rnA
Operating free-air temperature, TA
70
·C
High-level output current, 10H
°
electrical characteristics over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYPt
MAX
U~IT
Input clamp voltage
VCC=4.75V,
11=-18mA
High-level output voltage
VCC=4.75V,
VIL = 0.8V
VIH = 2\1,
VOL
low-level output voltage
Vce = 4.75 V,
10L = 40 rnA
VIH =2V.
IV OD11
Differential output voRage
VCC=5.25V.
10=0
IV OD21
Differential output voltage
A IVODI
Change in magnitude of
differential output voltage :I:
VOC
Common-mode output voltage§
A 1V0ei
Change in magnitude of
common-mode output vottage:l:
10
Output current with power off
VIK
VOH
-1
IIOH=-10mA
2.5
10H =-40mA
2
-1.2
V
0.5
V
3.3
ViL= 0.8V,
2VOD2
VCC = 4.75 V to 5.25 V,
See Figure 1
",0.4
V
3
V
",0.4
V
RL= 1000,
VO=6V
VO=-0.25V
Vec=O
V
V
2
0.1
100
-0.1
-100
JlA
",100
VO=-0.25Vt06V
II
Input current
Vec= 5.25V.
VI =5.5V
50
IIH
High-level input current
Vcc = 5.25 V,
VI =2.7V
25
IlL
Low-level input current
Vcc = 5.25 V,
VI =O.5V
lOS
Short-circuH output current"
VCC=5.25V.
VO=O
ICC
Supply current (all drivers)
Vcc = 5.25 V,
No load,
-50
All inputs at 0 V
32
200
JlA
JlA
JlA
-150
rnA
40
rnA
t All typical values are at Vce = 5 V and TA = 25·C.
:j: I VOD I and I VOC I are the changes in magnitude ofVOD and VOC. respectively, that occur when the input is changed from a high level to a
low level.
§ In EIA Standard RS-422-A. Voe, which is the average of the two output voltages wHh respect to ground. is called output offset voltage, VOS.
,. Only one output at a time should be shorted, and duration of the short circuit should not exceed one second.
switching characteristics over recommended range of operating free-air temperature, Vee
PARAMETER
tdD
Differential-output delay time
ttD
Differential-output transHion time
TEST CONDITIONS
eL=15pF.
RL= 1000,
See Figure 2
Skew
MIN
=5 V
TYP#
MAX
3.5
7
3.5
7
ns
1.5
4
ns
UNIT
ns
# Typical values are at TA = 25·C.
ThxAs
~
INSIRUMENTS
POST OFFICE BOX 655303 • DAl.lAS. TEXAS 75265
2-771
SN75ALS191
DUAL DIFFERENTIAL LINE DRIVER
SU.8032A- D3068, DECEMBER 1987 - REVISED AUGUST1989
PARAMETER MEASUREMENT INFORMATION
i
Input
50C
VOD2
50C
I
Voc
Figure 1. Differential and Common-Mode Output Voltages
t·
Input
YOutput
1.5V\ - - - - 3V
5V
RL=100C
Generator
(aeeNoteA)
Differential
Output
10%
CL=15pF
(..e Note B)
-=
V:
~
ZOutput
1
-+I
I+-
fdo -+I
90%
I+-
ttO
,,50%
YOutput
Skew~
ZOutput
TEST CIRCUIT
~
9O%k
ttO
14- tcIo
-+1 I+-
50%
NOTES: A. The input pulse generator has the following characteristics: Zo = 50 C, PRR " 500 kHz, tw = 100 ns, tr = " 5 ns.
B. CL includes probe and jig capackance.
2-772
POST OFFICE BOX 655303 • DAUAS. TEXAS 75265
I+-
5O%r
VOLTAGE WAVEFORMS
Figure 2. Test Circuit and Voltage Waveforms
- - VOH
~VOL
Skew-+!
\50%
ov
-
VOH
VOL
SN55ALS192, SN75ALS192
QUAD DIFFERENTIAL LINE DRIVERS
SLLSOO7B-
•
•
•
•
•
•
•
Meets EIA Standard RS-422-A
High-Speed, Low-Power ALS Design
3-State TTL Compatible
Single S-V Supply Operation
High Output Impedance in Power-Off
Condition
Complementary Output Enable Inputs
Improved Replacement for the AM26LS31
SN55ALS192 ••• J OR W PACKAGE
SN75ALS192 ••• D OR N PACKAGE
(TOP VIEW)
Vcc
1A
4A
4Y
4Z
G
2Z
2Y
6
3Z
2A
description
GND
These quad differential line drivers are designed
for data transmission over. twisted-pair or
parallel-wire transmission lines. They meet the
requirements of EIA Standard RS-422-A and are
compatible with 3-state TTL circuits. Advanced
low-power Schottky technology provides high
speed without the usual power penalties. Standby
supply current is typically only 26 mA, while typical
propagation delay time is less than 10 ns.
SN55ALS192 ••• FK PACKAGE
(TOP VIEW)
o
~:n~;>$
1Z
G
NC
2Z
High-impedance inputs maintain input currents
low, less than 1 fAA for a high level and less than
100 fAA for a low level. Complementary enable
inputs, G and G, allow these devices to be enabled
at either a high input level or low input level. The
SN75ALS192 is capable of data rates in excess of
20 megabits per second and is designed to
operate with the SN75ALS193 quad line receiver.
The SN55ALS192 is also capable of data rates in
excess of 20 megabits per second and designed
to operate with the SN55ALS193; however, it may
be limited to a lower bit rate based on the
temperature. Reference should be made to the
Dissipation Rating Table and Figure 15.
2Y
3 2 1 2019
18
17
16
15
14
9 10 11 12 13
4Y
4Z
NC
G
3Z
~~~~~
Cl
NC - No internal connection
FUNCTION TABLE
(each driver)
ENABLES
OUTPUTS
A
G
G
Y
H
L
H
L
X
H
H
X
X
L
X
X
H
L
H
L
Z
INPUT
The SN55ALS192 is characterized for operation
over the full military temperature range of -55°C
to 125°C. The SN75ALS192 is characterized for
operation from O°C to 70°C.
H
Z
1ExAs
4
5
6
7
8
L
L
H
= high level.
=high impedance (off).
..If
L
X
Z
L
H
L
H
Z
=low level.
=irrelevant
Copyright @ 1993. Texas Instruments Incorporated
INSIRUMENTS
POST OFFICE BOX 85530Ct • OAUAS. TEXAS 75265
2-773
SN55ALS192, SN75ALS192
QUAD DIFFERENTIAL LINE DRIVERS
SIiSOO7B-D2904, JULY 1985-REVISED MARCH 1993
logic symbol t
logic diagram (positive logic)
:.1
G
G
G
4
"
V
1
2
4A
7
3
7
2Y
5
10
3A 10
2Z
10
11
14
15
2A
1Z
5
9
6
1Y
6
3A
3
r-
V
2A
2
1A
EN
12
t>
1A
G
11
3Y
3Z
4Y
13
4A 15
4Z
1Y
1Z
2Y
2Z
3Y
3Z
14
4Y
13
4Z
t This symbol is In accordance with ANSVIEEE Sid 91-1984 and
lEe Publication 617-12.
Pin numbers shown are for Ihe 0, J, N, and W packages.
schematics of inputs and outputs
EQUIVALENT OF EACH
DATA (A) INPUT
EQUIVALENT OF EACH
ENABLE INPUT
EQUIVALENT OF EACH
OUTPUT
- - - - . - - - - - - - . - - VCC
Input --i...-+-l
Input --41'--"
Output
m m
177
III
III
1ExAs
2-774
..If
INSIRUMENTS
POST OFFICE BOX 655303 • DAUAS, TEXAS 75265
SN55ALS192, SN75ALS192
QUAD DIFFERENTIAL LINE DRIVERS
SLLSOO7B - 02904, JULY 1985 - REVISED MARCH 1993
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) ............................................................. 7 V
Input voltage, V, ............................................................................ 7 V
Off-state output voltage ...................................................................... 6 V
Continuous total dissipation ........................................... See Dissipation Rating Table
Operating free-air temperature range: SN55ALS192 ................................ - 55·C to 125·C
SN75ALS192 .................................... O·C to 70·C
Storage temperature range ....................................................... - 65·C to 150·C
Case temperature for 60 seconds: FK package .............................................. 260·C
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: J package ..................... 300·C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: D, N, or W package ............. 260·C
NOTE 1: All voltage values except differential output voltage VOO are with respect to network ground terminal.
DISSIPATION RATING TABLE
PACKAGE
TAs25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
TA = 70°C
POWER RATING
TA =125OC
POWER RATING
0
950mW
7.6mWre
608mW
N/A
FK
Jt
1375 mW
11.0 mwre
880mW
275mW
1375mW
11.0mWre
880mW
275mW
N
1150mW
9.2mWre
736mW
N/A
W
1000mW.
8.0mWre
640mW
200mW
t In the J package, the SN55ALS192 chips are either alloy or silver glass mounted.
recommended operating conditions
SN55ALS192
MIN
Supply voltage, Vee
4.5
High level input voltage, VIH
SN75ALS192
MAX
NOM
5
5.5
2
Low-level input voltage, VIL
High-level output current, IOH
Low-level output current, IOL
Operating free-air temperature, TA
-55
1ExAs
MIN
4.75
MAX
NOM
5
5.25
UNIT
V
V
2
V
0.8
0.8
-20
20
-20
mA
20
mA
70
°e
125
0
..If
INSIRUMENTS
POST OFFICE BOX 655303 • DALlAS. TEXAS 75265
2-775
SN55ALS192, SN75ALS192
QUAD DIFFERENTIAL LINE DRIVERS
SllSOO7B - 02904. JULY 1985- REVISED MARCH 1993
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
I
PARAMETER
TEST CONDITIONSt
VIK
Input clamp voltage
Vcc = MIN.
II =-18mA
VOH
High-level output voRage
VCC=MIN.
IOH=-20mA
VOL
Low-level output voltage
VCC=MIN.
IOL=20mA
Vo
Output voltage
VCC=MAX,
10=0
1'10011
Differential output voltage
VCC=MIN.
10=0
1'10021
Differential output voltage
RL= 1000.
See Figure 1
AIVool
Change in magnitude of
differential output voRage'V
VOC
Common-mode output
voltage#
AlVocl
Change in magnitude of
common-mode output
voltage"
10
Output current with power off VCC=O
10Z
Off.state {hilih-lRIpedance:.::, ~
VCC';'MAX
state) output current
II
Input current at maxlmum
input voltage
VCC=MAX,
VI=7V
IIH
High-level input current
VCC=MAX.
VI =2.7V
IlL
Low-level input current
VCC = MAX,
VI =O.4V
lOS
Short-circuit output current II
VCC = MAX
Supply current (all drivers)
VCC = MAX.
All outputs disabled
ICC
SN55ALS192
MIN
TYP*
SN75ALS192
MAX
TYP*
-1.5
2.4
MAX
-1.5
2.5
°
1.5
UNIT
V
V
0.5
0.5
V
6
6
V
6
°
1.5
1/2VOOl
1/2VOfl
or2§
or2
See Figure 1
RL= 1000.
MIN
6
V
V
",0.2
",0.2
V
",3
",3
V
",0.2
",0.2
V
100
100
-100
-100
VO=Q.5V
-20
-20
VO=2.5V
20
20
100
100
I1A
20
20
-200
-200
I1A
I1A
-150
rnA
45
rnA
VO=6V
VO=-0.25V
-30
-150
26
-30
26
45
I1A
I1A
t For conditions shown as MIN or MAX. use the appropriate value specified under recommended operating conditions.
*
All typical values are at VCC = 5 V and TA = 25°C.
§ The minimum V002 with a 100-0 load is either 1/2 VOOl or 2 V. whichever Is greater.
'II VOO I and I VOC I are the changes in magnitude of VOO and VOC. respectively. that occur when the input is changed from a high level to a
low level.
# In EIA Standard RS-422A. Voc. which is the average of the two output voltages with respect to ground. is called output offset voltage. VOS.
II Not more than one output should be shorted at a time. and duration of the short circuit should not exceed one second.
switching characteristics, Vee = 5 V, TA = 25°C (see Figure 2)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tpLH
Propagation delay time. low-to-high-Ievel output
tpHL
Propagation delay time. high-to-Iow-Ievel output
3
6
ns
ns
ns
tPZH
Output enable time to high level
Sl open and S2 closed
11
15
ns
tpZL
Output enable time to low level
51 closed and 52 open
16
20
ns
tpHZ
Output disable time from high level
51 open and 52 closed. CL=10pF
8
15
ns
tpLZ
OutpUt disable time from low level
51 and S2 closed.
18
20
ns
Sl and 52 open.
CL=30pF
Output-to-output skew
1ExAs ...,
INSIRUMENTS
2-776
POST OFFICE BOX 655303 • DAUAS. TEXAS75265
CL=10pF
6
13
9
14
SN55ALS192,SN75ALS192
QUAD DIFFERENTIAL LINE DRIVERS
SLLS007B - 02904, JULY 1985 - REVISED MARCH 1993
PARAMETER MEASUREMENT INFORMATION
t
50g
VOD2
sag
I
Voc
Figure 1. Differential and Common-Mode Output Voltages
--f
Input A
tPLH
N
A)
(see ote
OutputY
1.
1.3 V
~I
-;.;V- - -
~I
"., tPHL
_,,-_"\.-l..
- - VOH
I 1.5 V
I
I
1.5V
VOL
Skew +j 14- I Skew -.!
tPHL~
I
OutputZ
Enable G
Enable G
::
\ , 1.5V
~ tpLH
-.l_u
1.5V
T
---VUV '(.;;;Not;'B)'1;VV-
Waveform 1
(aae Note C)
r.:~'!t':~)
.'
1
ff-: .
I
J __ -45V I I 0.5 V
I
)l15V'
I
I S1 Closed I' .
1 ; -~S20pen
tpZH
VOH
~
tPZL
3V
Ii'----- 0 V
tpLZ --l.-..4 S1 Closed
1- -j S2 Closed
--..Ij\.:::
L
.~
1.5V
VOL
T
---r
~~'g,:~91.~~ os.· ····¢··~~V
r
;:'
I
•j
tpHZ
- - -OV
VOL
0.5 V
S1 Closed
S2Closed
ENABLE AND DISABLE TIMES
PROPAGATION DELAY TIMES AND SKEW
VOLTAGE WAVEFORMS
Test
Point
VCC
From Output _ -4t--....-4t----<:r--S
Under Teet
J
180 g
S2
TEST CIRCUIT
NOTES: A. When measuring propagation delay times and skew, switches 51 and 52 are open.
B. Each enable Is tested separately.
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 21s for an output with internal conditions such that the output is high except when disabled by the output control.
D. CL includes probe and jig capacitance.
E. All input pulses are supplied by generators having the following characteristics: PRR " 1 MHz, Zo - 50 Q, tr " 15 ns, and tf" 6 ns.
Figure 2. Test Circuit and Voltage Waveforms
1ExAs
..If
INSTRUMENTS
POST OFFICE BOX 6S5303 • DAUAS, TEXAS 75265
2-777
SN55ALS19~,
SN75ALS192
QUAD DIFFERENTIAL LINE DRIVERS
SlJ..SOO7B - 02904, JULY 1985- REVISED MARCH 1993
TYPICAL CHARACTERISTICSt
Y OUTPUT VOLTAGE
Y OUTPUT VOLTAGE
5
,
3,5
1.5
II
DATA INPUT VOLTAGE
5
Vcc=5V
4.5 - Outputs Enabled
I
4
Vcc=5.5V -
>
I
at
Vcc=4.5V -
2.5
i5
2.5
2
0
2
0
I
~
I
~
1.5
0.5
TA = 125°C
3.5
II
3
NOL~
4
Vcc=5V -
~
~
VB
DATA INPUT VOLTAGE
NoLoild
Outputs Enabled
TA = 25"C
4.5
>I
vs
~
3
TA=70~
o
0.5
1.5
2.5
2
o
o
3
0.5
VB
ENABLE G INPUT VOLTAGE
I
3.5
I
Vcc=5V
1-
3
I
>
I
Vcc=4.5V
f
2.5
i
2
o
.."
p
I
~
VI=2V
RL = 470 g to GND
See Note A
TA=25°c
0.5
o
o
0.5
1.5
2
2.5
3
5
Vcc=5V
4.5 _ VI=2V
RL = 470 g to GND
4 _SeeNoteA
TA=125"C
3.5
'''It
3
I-- TA = 25°C
2.5
VTA = O°c
TA=700~
2
~I
o
VI- Enable G Input Voltage - V
!
r---.'
~
Ta =-!)5"C
I rr I
0.5
1111
1.5
2
2.5
VI - Enable G Input Voltage - V
Figure 5
Figure 6
t Data for temperatures below ooe and above 70°C and below 4.75 V and above 5.25 V, are applicable to SN55ALS192 circufts only.
NOTE A: The A input is connected to Vee during the testing of the Y outputs and to ground during the testing of the Z outputs.
1ExAs
2-778
3
Y OUTPUT VOLTAGE
ENABLE G INPUT VOLTAGE
II
~
2.5
vs
Vcc=5.5V
•
2
Figure 4
4
i
"",TA=-55°c
1.5
Y OUTPUT VOLTAGE
0
TA=O°c
VI- Data Input Voltage - V
Figure 3
~
V
I'll
1.5
VI - Data Input Voltage - V
,
TA=25°c
0.5
o
>I
V
~
INSIRUMENTS
POST OFFICE BOX 655303 • DAUAS, TEXAS 75265
I
3
SN55ALS192, SN75ALS192
QUAD DIFFERENTIAL LINE DRIVERS
SLLSOO7B - D2904, JULY i985 - REVISED MARCH 1993
TYPICAL CHARACTERISTICSt
Z OUTPUT VOLTAGE
Z OUTPUT VOLTAGE
vs
va
ENABLE G INPUT VOLTAGE
ENABLE G INPUT VOLTAGE
6
6
RL = 470 otoVCC
VCC=5.5V
VCC=5V
RL =470 oto VCC
See NoteB
See Note A
Vce=5V
5
>I
j
i
TA=25°e
5
Vec=4.5V
>I
j
4
!:i
3
o
I
~
vLl-
4
~
o
3
~
2
ol__-L__~-=c==±==±=~
o
0.5
1.5
2.5
2
.....-
o
0.5
VI- Enable G Input Voltage - V
1.5
2
2.5
va
FREE-AIR TEMPERATURE
OUTPUT CURRENT
VCC=5V
IOH = -20 mA
See Note A
3
5
>
4.5
CD
4
See Nota A
TA=25°e
I
4~--~-4---+---+--~--4---+-~
r-:t:::t:~::::1==r==r===t==1
3r---r-~---+---+---r--~--+---i
2.5 ~--~-4---+---+--~--4---+-~
2~~~-4---+---+--~--4---+-~
1.5 r---Ir-~---+---+---r--~--+---i
f
~
!:i
Q,
!:i
3.5
~
2.5
.'\.
.....
. / Vce =5.5V
..... '\. I\.
'\. 1\.' ~ /Vec=5V
1\.' ~ " VCC=4.5V
~ '"\
'\ '\ .~
3
0
co
X
I
,
2
1.5
J:
~
0.5 r---Ir-~---+---+---r-~-+---i
o~~~~--~--~--~--~--~~
-50 -25
-
HIGH-LEVEL OUTPUT VOLTAGE
vs
5r--,---,---,---.--,---,---.--.
-75
TA=-ssoe
~
FigureS
HIGH-LEVEL OUTPUT VOLTAGE
3.5
-
VI - Enable G Input Voltage - V
Figure 7
4.5
TA=25°e
k' jII/ VTA=ooe
o
3
TA=70oe
/"
/"
I
2
1-'/ V
0
25
50
75
100
125
'\
0.5
o
o
TA - Free-Air Temperature - °C
I,
I
-'
."""
I\.
r\.
-100
-20
-40
-60
-80
IOH - High-Level Output Current - mA
Figure 9
Figure 10
t Data for temperatures below Doe and above 7Doe, and below 4.75 V and above 5.25 V, are applicable to SN55ALS192 circuHs only.
NOTES: A. The A input is connected to Vee during the testing of the Y outputs and to ground during the testing of the Z outputs.
B. The A input is connected to GND during the testing of the Y outputs and to Vee during the testing of the Z outputs.
1ExAs
.Jf
INSIRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
2-779
SN55ALS192, SN75ALS192
QUAD DIFFERENTIAL LINE DRIVERS
SLLSOO78 - 02904. JULY 1985 - REVISED MARCH 1993
TYPICAL CHARACTERISTICSt
LOW-LEVEL OUTPUT VOLTAGE
0.5
>I
t
~
'S
Q.
'S
0
I
~
I
..J
~
0.45
LOW-LEVEL OUTPUT VOLTAGE
va
vs
FREE-AIR TEMPERATURE
LOW-OUTPUT CURRENT
VCC=5V
IOl=-2OmA
See Note A
>I
0.4
CD
CII
=
~
VCC =4.5V
0.8
J
l I
lb ~ "
II
0.35
0.3
'-
0.25
0.2
0.15
--- - --
i'S
0
r--
~~
....
0.1
0.05
0.7
VCC= 5V
0.6
0.5
0.4
.3
0.3
~
0.2
I
..J
0.1
o
-75
-50 -25
0
25
50
75
100
125
o
~~
o
10
vs
SUPPLY CURRENT
25
0
40
A Inputs Open or Grounded
Outputs Disabled
Noloed
TA=25·C
20
Inputs Open
15
30
I
0
~
w~
10
90 100
~
"
6
I
':1
l.--"
2
4
5
3
VCC - Supply VOltage - V
7
8
/
/'1'
/
Inputs Grounded
20
80
40
50
o
70
SUPPLY VOLTAGE
C
o
60
SUPPLY CURRENT
ou~Puts Enabl~
Q.
Q.
50
va
1I
.E
40
SUPPLY CURRENT
30
::J
30
Figure 12
60
I/)
20
Figure 11
35
~
VCC=5.5V
IOl - lOW-level Output Current - mA
70 f- Noloed
TA=25·C
~
.....d ~
~~
A
P"
/
TA - Free-Air Temperature _·C
80
,
See Note A
TA=25·C
0.9
o
tJzJ
/
V
I
IIII
2345678
Vec - Supply Voltage - V
Figure 13
Figure 14
t Data for temperatures below O·C and above 70·C. and below 4.75 V and above 5.25 V. are applicable 10 SN55ALS192 circuits only.
NOTE A: The A input is conneeted 10 GND during Ihe lesling ofthe Y outputs and 10 VCC during the testing of the Z outputs.
lExAs ."
INSIRUMENTS
2-780
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
SN55ALS192, SN75ALS192
QUAD DIFFERENTIAL LINE DRIVERS
SLLSOO7B-D2904, JULY 1985- REVISED MARCH 1993
TYPICAL CHARACTERISTICS
SUPPLY CURRENT
VS
FREQUENCY
60
"'
VCC=s'"
Input = Ot03 V
50 ;- Duty Cycle = 50%
CL = 30 pF to All Outputs
~
I
C
1/
40
§
u
~
30
t:L
t:L
::I
fII
I
!.,,;
20
.... ~
U
.!!
10
o
10k
100 k
1M
10M
100M
f - Frequency - Hz
Figure 15
TEXAS
.Jf
INSTRUMENTS
POST OFFICE BOX 655303 • DAllAS, TEXAS 75265
2-781
2-782
SN75ALS193
QUAD DIFFERENTIAL LINE RECEIVER
WITH 3-STATE OUTPUTS
susooac -
•
Meets EIA Standards RS-422-A and
RS-423-A
•
Meets CCITT Recommendations Y.10, V.11,
X.26, and X.27
Designed for Multipoint Bus Transmission
on Long Bus Lines In Noisy Environments
•
•
•
•
•
•
•
•
•
02931 JUNE 1986 - REVISED MARCH 1993
SN75ALS193 ••• J PACKAGEt
{TOP VIEW)
Vee
46
4A
4Y
3-State Outputs
2Y
Common-Mode Input Voltage Range
-7Vto 7V
26
GND
Input Sensitivity ••• ±200 mV
G
3Y
3A
36
Input Hysteresis ••• 120 mV Typ
t For surface-mount package, see the SN75ALS197.
High Input Impedance ••. 12 kQ Min
Operates from Single SOV Supply
Low Supply Current ~~qulrement
35mAMax
Improved Speed and Power Consumption
Compared to AM26LS32A
description
The SN75ALS193 is a monolithic quad line receiver with 3-state outputs designed using advanced low-power
Schottky technology. This technology provides combined improvements in bar design, tooling production, and
wafer fabrication. This, in turn, provides significantly less power requirements and permits much higher data
throughput than other designs. These devices meet the specifications of EIA Standards RS-422-A and
RS-423-A. It features 3-state outputs that permit direct connection to a bus-organized system with a fail-safe
design that ensures the outputs will always be high if the inputs are open.
The device is optimized for balanced multipoint bus transmission at rates up to 20 megabits per second. The
input features high Input impedance, input hysteresis for increased noise immunity, and an input sensitivity of
± 200 mV over a common-mode input voltage range of - 7 to 7 V. It also features active-high and active-low
enable functions that are common to the four channels. The SN75ALS193 is designed for optimum performance
when used with the ALS192 quad differential line driver.
The SN75ALS193 is characterized for operation from O°C to 70°C.
FUNCTION TABLE
(each receiver)
DIFFERENTIAL INPUTS
ENABLES
OUTPUT
A-B
G
G
y
VIO>:O.2V
H
X
X
L
H
H
-O.2V < VID < O.2V
H
X
X
Vlos-O.2V
H
X
X
?
?
L
L
L
L
X
L
H
Z
Open
H
X
X
H
H
H " high level,
L " low level,
X " irrelevant,
L
? " indeterminate
Z" high impedance (off)
Copyright@ 1993, Texas Instruments Incorporaled
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2-783
SN75ALS193
QUAD DIFFERENTIAL LINE RECEIVER
~~~!!~Tu~EqJ!~~~!~D MARCH 1993
logic symbol t
G
G
logic diagram (positive logic)
4
Q
.,1
G
EN
....
12
r
1A
1B
2A
2B
3A
3B
4A
4B
1A
EI>
2
1
"-
]
V
6
....
7
10
3
5
11
9
"-
14
15
....
13
4
12
2
3
1Y
1B
1Y
2A
6
2Y
2B
7
3Y
3A
3B
4Y
5
2Y
10
11
9
4A
14
4B
15
13
3Y
4Y
tThis symbol is in accordance with ANSI/IEEE SId 91-1984 and lEe Publication 617-12.
schematics of inputs and outputs
EQUIVALENT OF EACH A OR B INPUT
Vcc
-------.--~~--
EQUIVALENT OF G OR G INPUTS
Vcc--------.-~.---
EQUIVALENT OF ALL OUTPUTS
----------~~-
SOkO
NOM
18kO
NOM
Input ...-wIrlll......-1
Input ~"-+-l
VCC(A}
or
GND(B)
GND
--+-__-------
GND __
1 1 --I
1ExAs . "
INSIRUMENTS
2-784
POST OFFICE BOX 655303 • DAUAS. TEXAS 75265
Vce
SN75ALS193
QUAD DIFFERENTIAL LINE RECEIVER
WITH 3-STATE OUTPUTS
SLLSOO8C - D2931, JUNE 1986 - REVISED MARCH 1993
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) ............................................................. 7 V
Input voltage, A or B, VI ................................................................... ±15 V
Differential input voltage (see Note 2) ....................................................... ± 15 V
Enable input voltage ......................................................................... 7 V
Low-level output current .................................................................. 50 mA
Continuous total dissipation ........................................... See Dissipation Rating Table
Operating free-air temperature range .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. O°C to 70°C
Storage temperature range ....................................................... - .65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds ............................... 300°C
t Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditons is not implied.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voitage values, except differential input voltage, are with respect to network ground terminal.
2. Differential-input voltage is measured at the noninverting input with respect to the, corresponding inverting input.
DISSIPATION RATING TABLE
=
=
PACKAGE
TA,,25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
TA 70°C
POWER RATING
TA 12S°C
POWER RATING
J
1025mW
8.2mWrC
656mW
N/A
recommended operating conditions
Supply voltage, VCC
MIN
NOM
MAX
UNIT
4.75
5
5.25
V
Common-mode input voltage, VIC
Differential Input voltage, VID
High-level input voltage, VIH
±7
V
±12
V
V
2
0.8
loW-level input voltage, VIL
High-level output current, IOH
Low-level output current, IOL
Operating free-air temperature, TA
0
V
-400
!lA
16
mA
70
°c
TEXAS ~
INSIRUMENfS
POST OFFICE BOX 655303 • DAllAS, TEXAS 75265
2-785
SN75ALS193
QUAD DIFFERENTIAL LINE RECEIVER
WITH 3-STATE OUTPUTS
SLLSOO8C - 02931, JUNE 1986 - REVISED MARCH 1993
electrical characteristics over recommended range of common-mode input voltage, supply
voHage, and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONSt
MIN
TYP*
MAX
UNIT
200
mV
"T+
"T-
Positive-going threshold voltage
V~
Hysteresis (\IT+ -VT...)
VIK
Enable-input clamp voltage
VCC"MIN,
11,,-18mA
VOH
High-level output voltage
VCC"MIN,
10H " - 400 iAA,
VID,,200mV,
See Figure 1
0.45
Low-level output voltage
VCC"MIN,
VIO " - 200 mV,
See Figure 1
IOL,,8mA
VOL
IOL,,16mA
0.5
10Z
II
IIH
IlL
:-200§
Negatlve-going threshold voltage
mV
120
High-impedance-state output current
VCC"MAX
Line input current
Other input at
See Note 3
High-level enable-input current
2.5 .
3.6
V
V
V
°
V,
VCC" MAX
Low-level enable-Input current
mV
-1.5
VO,,2.4V
20
VO,,0.4V
. -20
VCC"MIN,
VI,,15V
0.7
1.2
VCC"MIN,
VI,,-15V
-1.0
-1.7
rnA
VIH,,2.7V
20
VIH"MAX
100
-100
VIL"O.4V
VCC " MAX,
Input resistance
lOS
Short-circuit output current
VCC " MAX,
VO"O,
VIO,,3V,
See Note 4
ICC
Supply current
VCC" MAX,
Outputs disabled
iAA
iAA
iAA
kQ
12
18
-15
-78
_130
.mA
22
35
rnA
..
t For conditions shown as MIN or MAX, use the appropriate values speCified under recommended operating conditions ..
:I: All typical values are at VCC ,,5 V, TA" 25°C.
•
§ The algebraic convention, in which the less positive limit is designated minimum, is used in this data sheet for threshold voltage levels only.
NOTES: 3. Refer to EIA Standard RS-422-A and RS-423-A for exact conditions. .
.
4. Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second.
switching characteristics, Vee = 5 V, TA = 25°e
PARAMETER
TEST CONDITIONS
tPLH
Propagation delay time, low-to-high-Ievel output
tpHL
Propagation delay time, high-to-Iow-Ievel output
tPZH
Output enable time to high level
tpZL
Output enable time to low level
tPHZ
Output disable time from high level
tpLZ
Output disable time from low level
VIO " -2.5 V to 2.5 V,
See Figure 2
CL" 15 pF,
CL,,15pF,
See Figure 3
CL"SpF,
See Figure;;
1ExAs
~
INS1RUMENTS
2-786
POST OFFICE BOX 655303 • DAllAS, TEXAS 75265
MIN
lYP
MAX
15
22
15
22
13
25
11
25
13
25
15
22
UNIT
ns
SN75ALS193
QUAD DIFFERENTIAL LINE RECEIVER
WITH 3-STATE OUTPUTS
SLLSOOSC-02931. JUNE 1986-REVISEO MARCH 1993
PARAMETER MEASUREMENT INFORMATION
..
IIOH
(-)
Figure 1. VOH. VOL
_ - -......... - - - - - - 2.5V
>-+---4t-- Output
IT
I
I
_J
~
CL=15pF
(see Note 8)
' - - - - -2.5V
r4- tpHL
---~t---
Output
TEST CIRCUIT
VOH
VOLTAGE WAVEFORMS
NOTES: A. The Input pulse is supplied by a generator having the following characteristics: PRR
tr s 6 ns. tfs 6 ns.
B. CL includes probe and jig capac~ance.
S
1 MHz. duty cycle s 50%,
Zo = 50
Q.
Figure 2. Test Circuit and Voltage Waveforms
1ExAs ."
INSIRUMENIS
POST OFFICE BOX 655303 • DALlAS. TEXAS 75265
2-787
SN75ALS193
QUAD DIFFERENTIAL LINE RECEIVER
WITH 3-STATE OUTPUTS
SLLSOOBC':' 02931, JUNE 1986 - REVISED MARCH 1993
PARAMETER MEASUREMENT INFORMATION
Test
Point
From Output
Under Test
-+----4I...--+----i__- ....
(see Note B)
CLI
SkO
(see Note A)
LOAD CIRCUIT
-+I I.... "Sns
JF
-'1 I+- "Sns
I
,.------3V
I I
Enable
G
10%
Enable
G
I I
III
~V I
I
I
10%
_ _ _ OV
II~
~I
!!
(see Note C)
!! I
1.3V
10%
81 Open
52 Closed
.'
I
I
10%
tPZH
I
.1
- .I-
~ 1.4 V
(see Note C)
I
I'10%
14 _"\•.I
__
Output
S20pen
81 Closed
81 Closed
S2C!osed
VOlTAGE WAVEFORMS FOR tpHZ, tpZH
I
10%
tpZL
CL
Figure 3. Load Circuit and Voltage Waveforms
1ExAs ",
INSIRIJMENTS
POST OFFICE BOX 655303 • DAUAS, TEXAS 75265
OV
~I:11"1~:--_ 3 V
90%
1.3 V
----Closed
,' 8 1
S2 Closed
,... ..I
is:
'1/"7
OV
~1.4V
L..t.-=..-!-_ VOL
-t.:: O.SV
VOLTAGE WAVEFORMS FOR tpLZ. tpZL
NOTES: A.
Includes probe and jig capacHance.
B. All diodes are 1N3064 or equivalent.
C. Enable G is tested with G high; G is tested wHh Glow.
2-788
I
I 10%
II-p;----
~
Ensble 90%
G 1.3V
~-LVOH
t4
II
II
I ::
- - - - - - OV
I
r- O.SV
I
I
-'1
'F:
:1~ ~:vl
Enable
G
10%
3V
90%
1.3V
I
14
Output
1~
-+I I.... .,Sns
SN75ALS193
QUAD DIFFERENTIAL LINE RECEIVER
WITH 3-STATE OUTPUTS
SLLSOOSC - 02931. JUNE 1986 - REVISED MARCH 1993
TYPICAL CHARACTERISTICS
OUTPUT VOLTAGE
OUTPUT VOLTAGE
vs
vs
ENABLE VOLTAGE
ENABLE VOLTAGE
5
4
VIO=200mV
VIC=O
RL=8kOtoGNO
TA=25°C
4.5
>
I
GI
at
4
5c:a.
5
2.5
0
I
~
3
at
VCC=4.5V
3
TA = 25°C
TA=O°C
III
II
~
>I
VCC=5V
3.5
:t::
TA=~OC- -.
3.5
VCC=5.5V
II
:t::
2.5
5c:a.
5
2
~
0
2
I
1.5
~
1.5
0.5
0.5
o
o
0.5
1.5
2
2.5
o
o
3
0.5
Enable Voltage - V
Enable Voltage - V
Figure 4
Figure 5
OUTPUT VOLTAGE
6
VS
ENABLE VOLTAGE
ENABLE VOLTAGE
I
VCC=5V
VCC=4.5V
I
6
.1.
VIO=-200mV
vlC=o
RL = 1 kOto Vec
TA = 25°C
5
t
!
OUTPUT VOLTAGE
vs
VCC=5.5V
>
-
5
>
I
III
4
at
~
~
5
~
5c:a.
'S
3
_ _ TA=O°C
4
~TA=25°C -
f.---
TA = 70°C
3
0
I
~
1.5
VCC=5V
VIO = 200 mV
VIC=O
RL=8kOtoGNO
I
I
2.5
3
2
I
2
~
2
VCC=5V
VIO =-200 mV
VIC=O
RL=1 kOtoVCC
o
o
0.5
1.5
2
2.5
3
o
o
0.5
1.5
2
Enable Voltage - V
Enable Voltage - V
Figure 6
Figure 7
2.5
3
1ExAs ."
INSIRUMENfS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
2-789
SN75ALS193
QUAD DIFFERENTIAL LINE RECEIVER
WITH 3-STATE OUTPUTS
su.sooec - 02931. JUNE 1986 - REVISED MARCH 1993
TYPICAL CHARACTERISTICS
HIGH-LEVEL OUTPUT VOLTAGE
OUTPUT VOLTAGE
5
,
3.5
5
2.5
0
2
~.
!
•
~
vs
DIFFERENTIAL INPUT VOLTAGE
FREE-AIR TEMPERATURE
VCC=5V
VIC =-12Vto 12V
10=0
TA=25·C
4.5
>
•
GI
vs
4
,
3.5
5
9:::I
2.5
>
•
GI
~
3
4
10H=0
~
3
VT-
~.c
VT+
V
DO
2
1.5
:f
•:z:
~
VCC=5V
VIO=2OOmV
VIC=o
0.5
0.5
o
-200-150 -100 -50
0
50
100
150
o
200
-75 -50 -25
0
25
50
75 100
TA - Free-Air Temperature _·C
VIO - Olfferentlallnput Voltage - mV
Figure 8
vs
HIGH-LEVEL OUTPUT CURRENT
HIGH-LEVEL OUTPUT CURRENT
VIO=2OOmV
VIC=O
TA=25·C
4.5
.......
3.5
.......
2
HIGH-LEVEL OUTPUT VOLTAGE
vs
5
4
"
i".. "........
i".. "-
5
-
GI
4
•
=
~
5Q.
5
./ VCC=5.5V
~ "VCC=5V
' -'~ ~/,.!.VCC=4.5V
,
" """ ""-
>
4.5
i
I I
"
VCC=5V
VIO=2OOmV VIC =0
...
3.5
~
3
0
•
~lllllWll
o -10 -20 -30 -40 -50 -60 -70 -80-90-100
~
g
:z:
•
:z:
~
2.5
2
1.5
0.5
o
~
/1
~~
TA=25·C
"./ ~ ~ . ./?'
TA ;=70°C
~~
~~
~ r\.
\~
TA=o·C
o -10 -20 -30 -40 -50 -60-70 -80 -90-100
10H - High-Level Output Current - mA
10H - High-Level Output Current - mA
Figure 10
Figure 11
1ExAs . "
2-790
125
Figure 9
HIGH-LEVEL OUTPUT VOLTAGE
2.5
~ "-I~H = -:.00 ~
0
1.5
3
-k:::
INSIRUMENTS
POST OFFICE BOX 655303 • DAUAS,'TEXAS 75265
SN75ALS193
QUAD DIFFERENTIAL LINE RECEIVER
WITH 3-STATE OUTPUTS
SLLSooac - 02931. JUNE 1986 - REVISED MARCH 1993
TYPICAL CHARACTERISTICS
LOW-LEVEL OUTPUT VOLTAGE
VS
FREE-AIR TEMPERATURE
0.4
I
VCC=5V
0.35 _ VIO=-200mV
VIC=O
>I
II
DI
II
""~
0.3
'!i
Q.
'!i
0.25
0
a;
~
"'r---...
0.2
1
0.15
!...
0.1
0
oJ
.... 1'0...
--
10=0..........
:9
10=8mA
"-
i--I--
0.05
o
-75 -50 -25
0
25
50
-- -
75
100
125
TA - Free-Air Temperature - ·C
Figure 12
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
LOW-LEVEL OUTPUT CURRENT
0.8
>
)
0.7
I
VCC=4.5V.'-...
VCC=5V
""'VCC=5.5V"-.,
II
f
'!i
Q.
'!i
0
iii
1
I
oJ
0.6
r--
0.3
0.1
o
V
..I: ~
0.4
~
J
r;b Ij
0.5
0.2
LOW-LEVEL OUTPUT VOLTAGE
vs
~
~
~~
"
o
VIO =-200mV
VIC=O
TA=25·C
ro
~
~
~
50
50
ro
0.11<--+--+-+--t--I--+--+---I
O~~-~-~-~-.J_~-~~
50
o
10L - Low-Level Output Current - mA
10
~
~
~
50
50
ro
80
10L - Low-Level Output Current - mA
Figure 13
Figure 14
1ExAs
.Jf
INSlRUMENTS
POST OFFICE BOX 655303 • DAUAS, TEXAS 75265
2-791
SN75ALS193
QUAD DIFFERENTIAL LINE RECEIVER
WITH 3-STATE OUTPUTS
su.sooac - 02931, JUNE 1986 -
REVISED MARCH 1993
TYPICAL CHARACTERISTICS
SUPPLY CURRENT
50
4S
~
40
i
35
I
:::I
va
SUPPLY VOLTAGE
FREE-AIR TEMPERATURE
30
VIO=-2OOmV
VIC=O
10=0
TA=25"C
>-
30
lisabled ~
25
»
I
c(
20
15
~
10
~
6
o
o
25
E
VCC=5V
I
Ii
§
20
r-
VCC =4.5V
U
~
Q,
if' Enabled
:::I
11)
,
J
I
VCC=5,5V
/L
U
8:
SUPPLY CURRENT
va
15
:::I
11)
l/
I
U
.9
~
10
5 I- VIO = -200 mV
Outputs Enabled
10=0
_/
o
2345678
-75
I
I
I
-50
-25
0
va
vs
DIFFERENTIAL INPUT VOLTAGE
FREQUENCY
30
,
.35
~
VCC=5V
20
VCC=4,5V
u
Q,
Q,
40
I I
VCC=5,5V
25
I
~
15
:::I
I
30
I
25
i
20
I
/
'"
:::I
I
U
10
5
o
15
.9
10
10=0
Outputs Enebled
VIC =0
TA=25°C
-200-150 -100 -50
5
0
50
100 150
200
o
10k
100k
1M
Figure 18
Figure 17
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 6515303 • DALLAS, TEXAS 75265
'--
10M
f - Frequency - Hz
VIO - Olfferentlallnput Voltage - mV
2-792
125
11)
I
U
100
,,,n
VCC=5V'
VI = ± 1,5-V Square Wave
CL=15pF
Four Channels Oriven
TA = 25°C
u
11)
.9
75
SUPPLY CURRENT
SUPPLY CURRENT
I
50
Figure 16
Figure 15
~
25
TA - Frea-Alr Temperature - °c
VCC - Supply Voltage - V
100M
SN75ALS193
QUAD DIFFERENTIAL LINE RECEIVER
WITH 3-STATE OUTPUTS
SLLSOO8C - 02931, JUNE 1986 - REVISED MARCH 1993
TYPICAL CHARACTERISTICS
INPUT RESISTANCE
INPUT CURRENT
vs
va
FREE-AIR TEMPERATURE
INPUT VOLTAGE TO GND
3
30
TA=25·e
2
25
c:
V
I
8c
j
'!'i
Q.
.E
I
.::-
20
15
~
"..
-
I
~~
-
C
!!
~
0
0
'!'i
Q.
.E
I
10
.:
."........
-1
/
-2
5
o
-75 -SO
-25
0
25
SO
75
100
-3
-20 -15 -10
125
Figure 19
va
FREE-AIR TEMPERATURE
SUPPLY VOLTAGE
25
18
I!!
--;---+-~~-+
I
16
II
20 t----I---'----+---;--
j
E
1=
14
'ii
12
~
:E
01
Q
::e~etE1--;
tpZH
10
15
20
PROPAGATION DELAY TIME
20
C
5
vs
Vee=5V
eL=15pF
1=
0
Figure 20
SWITCHING CHARACTERISTICS
I
-5
VI -Input Voltage to GND - V
TA - Free·Alr Temperature -·e
I!!
-"
V
"./
/
tpHZ
c
0
ii01
8
DI
6
..
'1:/
Q.
-
I
tp~L
tPLH
10
II
Q.
e
eL=15pF
TA=25·e
4
2
o
4.5 4,6 4.7 4.8 4.9
TA - Free-Air Temperature _ ·e
5
5. 1 5.2 5.3 5.4 5.5
Vee - Supply Voltage - V
Figure 21
Figure 22
1ExAs
..If
INSIRUMENTS
POST OFFICE BOX 655303 • DAUAS, TEXAS 75265
2-793
2-794
SN55ALS194, SN75ALS194
QUAD DIFFERENTIAL LINE DRIVERS
WITH 3-STATE OUTPUTS
Sl..I..SOO9C-
•
•
•
•
•
•
•
OCTOBER 1985 - REVISED MARCH 1993
SN55ALS194 ••• J OR W PACKAGE
SN75ALS194 ••• D OR N PACKAGE
Meets EIA Standard RS-422-A
High-Speed ALS Design
(TOP VIEW)
3-State TTL-Compatible Outputs
Single SOV Supply Operation
High Output Impedance In Power-Off
Condition
Vee
1A
1Y
4A
2Z
4Y
4Z
3,4EN
2Y
3Z
2A
3Y
l,2EN
Two Pairs of Drivers Independently
Enabled
Designed as a Replacement for the MC3487
With Improvements: IcC 50% Lower,
Switching Speed 30% Faster,
Full-Temperature-Range Version
3A
description
SN55ALS194 ••• FK PACKAGE
(TOP VIEW)
These quad differential line drivers are designed
for data transmission over twisted-pair or
parallel-wire transmission lines. They meet the
requirements of EIA Standard RS-422-A and are
compatible with 3-state TTL circuits. Advanced
low-power Schottky technology provides high
speed without the usual power penalty. Standby
supply current is typically only 26 mA, while typical
propagation delay time is less than 10 ns and
enable/disable times are typically less than 16 ns.
High-impedance inputs keep input currents low,
less than 1 J.tA for a high level and less than
100 J.tA for a low level. The driver circuits can be
enabled in pairs by separate active-high enable
inputs. The SN55ALS194 and SN75ALS194 are
capable of data rates in excess of 10 megabits per
second and are designed to operate with the
SN55ALS195 and SN75ALS195 quadruple line
receivers.
°
>-O<
"I"
~~
1Z
l,2EN
NC
2Z
2Y
4
5
6
7
8
3 2 1 2019
18
17
16
15
14
9 10 11 12 13
4Y
4Z
NC
3,4EN
3Z
<00<>C\lZZMM
(!)
NC - No internal connection
The SN55ALS194 is characterized for operation
over the full military temperature range of - 55°C
to 125°C. The SN75ALS194 is characterized for
operation from O°C to 70°C.
FUNCTION TABLE
(each driver)
INPUT
A
OUTPUT
EN
H
L
H
H
L
X
H = high level, L = low level,
Z high impedance
=
OUTPUTS
Y
Z
H
L
Z
L
H
Z
X = irrelevant,
Copyright © 1993, Texas Instruments Incorporated
TEXAS . "
INSIRUMENIS
POST OFFICE BOX 655303 • DAllAS, TEXAS 75265
2-795
SN5SALS194~
SN75ALS194
QUAD DIFFERENTIAL LINE DRIVERS
WITH 3-STATE OUTPUTS
Su.9009C - 02917, OCTOBER 1985 - REVISED MARCH 1993
logic symbol t
1,2EN
4
logic diagram (positive logic)
..,
,J
EN
I>
1A
2
V
1
3
V
6
2A
7
5
1Y
2
1Z
3
3,4EN
,t!iN
8
2Z
3A
10
V
11
V
4A
2Y
2Z
,J
I>
9
1Z
2Y
5
12
1Y
14
13
15
3Y
3Z
10
4Y
11
3Y
3Z
4Z
14
13
4Y
4Z
t This symbol is in accordance wHh ANSI/lEEE SId 91-1984
and IEC Publication 617-12.
Pin numbers shown are for the D, J, N, and W packages.
schematics of inputs and outputs
EQUIVALENT OF EACH
DATA (A) INPUT
EQUIVALENT OF EACH
ENABLE INPUT
EQUIVALENT OF EACH
OUTPUT
VCC
Input
Input
~
__..-l
11]]
I
1ExAs
..If
INSIRUMENTS
2-796
POST OFFICE
eox 655303 •
OAUAS, lEXAS 75265
w.
-11')
Ouiput
I
SN55ALS194, SN75ALS194
QUAD DIFFERENTIAL LINE DRIVERS
WITH 3-STATE OUTPUTS
SLLSOO9C - 02917, OCTOBER 1985 - REVISED MARCH 1993
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) ............................................................. 7 V
Input voltage, VI .......................................................................... 5.5 V
Continuous total dissipation ........................................... See Dissipation Rating Table
Operating free-air temperature range: SN55ALS194 ................................ - 55°C to 125°C
SN75ALS194 .................................... O°C to 70°C
Storage temperature range ....................................................... - 65°C to 150°C
Case temperature for 60 seconds: FK package .............................................. 260°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: D, N, or W package ............. 260°C
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: J package ..................... 300°C
NOTE 1: All voltage values are with respect to network ground terminal.
DISSIPATION RATING TABLE
PACKAGE
TA",25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
TA=70°C
POWER RATING
TA=125°C
POWER RATING
D
950mW
7.6mW/"e
608mW
N/A
FK
1375mW
11.0mW/"e
880mW
275mW
275m"{'J
J
1375mW
11.0 mw/"e
880mW
N
1150mW
9.2mW/"e
736mW
N/A
W
1000mW
8.0mW/"e
640mW
200mW
recommended operating conditionst
SN55ALS194
Supply voltage, Vee
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.75
5
5.25
All inputs, TA = 25°C
High-level Input voltage, V,H
2
A inputs, TA = Full range
EN inputs, TA = Full range
2
2
2
loW-level input voltage, VIL
Operating free-air temperature, TA
V
V
0.8
0.8
-20
-20
TA = 25°C
48
48
TA = Full range
20
48
-55
UNIT
2
2.1
High-level output current, IOH
Low-level output current, IOL
SN75ALS194
MIN
125
0
70
V
rnA
rnA
°e
t Full range IS TA = - 55°C to 125°C for SN55ALS194 and TA = ooe to 70°C for SN75ALS194.
TEXAS . "
INSIRUMENTS
POST OFFICE BOX 655303 • DAUAS, TEXAS 75265
2-797
SN55ALS194,SN75ALS194
QUAD DIFFERENTIAL LINE DRIVERS
WITH 3-STATE OUTPUTS
SllSOO9C- 02917, OCTOBER 1985- REVISED MARCH 1993
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature range (unless otherwise noted) .
TEST CONDITIONSt
PARAMETER
Input clamp voltage
MIN
TYP*
MAX
UNIT
-1.5
V
VCC=MIN,
11=-18mA
High-level output voltage
VCC=MIN,
IOH=-20mA
SN55ALS194
2.4
SN75ALSI94
2.5
VOL
Low-Ievel output voltage
VCC=MIN,
10L=MAX
0.5
V
Vo
Output voltage
10=0
0
6
V
"'0011
Differential output voltage
10=0
1.5
6
V
VIK
VOH
"'0021
Differential output voltage
A"'ool
Change in magnitude of
differential output voltage'll
VOC
V
112 VOOI
or2§
V
",0.4
V
Common-mode output voltage
",3
V
A"'ocl
Change In magnitude of
common-mode output voltage'
",0.4
V
10
Output current with power off
10Z
RL= 1000,
100
VO=6V
VCC=O
-100
VO=-0.25V
VCC= MAX,
Output enables at 0.8 V
High-Impedance state output current
See Figure 1
VO=2.7V
100
VO=0.5V
-100
JIA
-200
JIA
JIA
JIA
-140
rnA
II
Input current at maximum input voltage
Vce= MAX,
VI =5.5V
100
IIH
High-level input current
Vec = MAX,
VI =2.7V
50
IlL
Low-level input current
Vee = MAX,
VI =0.5V
lOS
Short-Circuit output current#
VCC=MAX,
VI=2V
-40
JIA
26
45
rnA
All outputs disabled
Supply current (all drivers)
Vee = MAX,
ICC
t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
All typical values are at VCC = 5 V. TA = 25°C.
§lhe minimum VOD2with a 100-0 load is either 1/2VOOI or2V, whichever Is greater.
, AI VOD I and AI VOC I are the changes In magnitude of VOD and Voe, respectively, that occur when the input is changed from a high level to
a low level.
# Not more than one output should be shorted at a time, and duration of the short circuit should not exceed one second.
*
switching characteristics,
Vee =5 V, TA =25°C
TEST
CONDITIONS
PARAMETER
tpLH
Propagation delay time, low-to-high-Ievel output
tpHL
Propagation delay time, hlgh-to-Iow-Ievel output
SN55ALSI94
MIN
eL=15pF,
See Figure 2
Output-to-output skew
ttD
Differential-output transition time
tPZH
Output enable time to high level
tpZL
Output enable time to low level
tpHZ
Output disable time from high level
tPLZ
Output disable time from low level
eL= 15 pF,
See Figure 3
eL=15pF,
See Figure 4
1ExAs
..If
INSIRUMENTS
2-798
POST OFACE BOX 655303 • DAUAS. TEXAS 75265
TYP
SN75ALSI94
MAX
MIN
TYP
MAX
UNIT
6
13
6
13
9
14
9
14
ns
ns
3.5
6
3.5
6
ns
8
14
8
14
ns
ns
9
12
9
12
12
20
12
20
ns
9
15
9
14
12
15
12
15
ns
ns
SN55ALS194,SN75ALS194
QUAD DIFFERENTIAL LINE DRIVERS
WITH 3-STATE OUTPUTS
SLLSOO9C - 02917, OCTOBER 1985 - REVISED MARCH 1993
SYMBOL EQUIVALENTS
DATA SHEET PARAMETER
RS-422·A
Va
Voa,Vob
I VOD11
I VOD21
Vt (RL = 100 0)
AIVODI
I IVtl-IVtl I
VOC
I Vas I
AIVocl
I Vas-Vas I
lOS
Ilsal,llsbl
10
Ilxal,llxbl
VA
RL
'--_ _.... 2
VOC
~
Figure 1. DriverVOD and Voe
PARAMETER MEASUREMENT INFORMATION
Inp: j 1 . 5 V
5V
2000
f---i---{~S1
Generator
(see Note A)
_
-
I
tpLH
YOutPut:
~
ICL = 15 pF
ksee Note B)
I
3V IL _ _ _ _ _ .JI
(see Note C)
1.5V\ - - - - - - - : :
~
I
104
1'5V~I-
:
Skew~
'i\
l1.5V
Skew~
~ tPHL--!
-=
~tpHL
I:
ZOutput
- - - - VOH
VOL
14- tpLH -+i
\1.5V
1 . 5 V L . . VOH
VOL
VOLTAGE WAVEFORM
TEST CIRCUIT
Figure 2. Test Circuit and Voltage Waveform
-3V
~
Input
OV
Generator
(see Note A)
Output
ttD
-tj i!= =!i
~
if"'9O%\ i
~ 10% \..
ttD
Output
CL =15 pF
(see Note B)
TEST CIRCUIT
VOLTAGE WAVEFORM
Figure 3. Differential-Output Test Circuit and Voltage Waveform
NOTES: A. The input pulse is supplied by a generator having the following characteristics: tr '" 5 ns, tf'" 5 ns, PRR '" 1 MHz, duty cycle", 50%,
ZO-500.
B. CL includes probe and stray capacitance.
C. All diodes are 1N916 or 1N3064.
TEXAS
..If
INSIRUMENIS
POST OFFICE BOX 655303 • DALlAS, TEXAS 75265
2-799
SN55ALS194, SN75ALS194 .
QUAD DIFFERENTIAL LINE DRIVERS
WITH 3-STATE OUTPUTS
Sll.SOO9C - 02917. OCTOBER 1985 - REVISED MARCH 1993
PARAMETER MEASUREMENT INFORMATION
sv
Output
r-;-...--v....o-~HHH4III-~...--o-S1 J
200 C
(see Note C)
Generator
(eeeNoteA)
TEST CIRCUIT
Output
Enable
Input
-----
Enable
Input
1.SV\
tpHZ ~
Output
81 Closed
S2Closed
~v-I
-
VOH
I
-1.SV
14-
~
1.SV
_
ov
OV
14-
tPLZ ~
Output
81 Closed
S2Closed
Output
3V
Output
81 Closed
82 Open
I
1PZL ~
Output
S10pen
S2Closed
VOL
3V
14-
II~
1.SV
tpZH ~
-1.SV
-
~.~V_ _
~
1.SV
14-
VOL
VOH
y,.SV
VOLTAGE WAVEFORMS
NOTES: A The input pulse Is supplied by a generator having the following characteristics: tr " 5 ns. tf " 5 ns. PRR " 1 MHz. duty cycle" 50%.
Zo-50C.
B. CL includes probe and stray capacitance.
C. All diodes are 1N916 or 1N3064.
Figure 4. Driver Test Circuit and Voltage Waveforms
1ExAs
~
INSlRUMENTS
2-800
POST OFFICE BOX 655303 • DAUAS. TEXAS 75265
SN55ALS194, SN75ALS194
QUAD DIFFERENTIAL LINE DRIVERS
WITH 3-STATE OUTPUTS
SLLSOO9C-D2917. OCTOBER 1985-REVISED MARCH 1993
TYPICAL CHARACTERISTICSt
Y OUTPUT VOLTAGE
5
GI
f
5
VCC=5.5VVCC=5V-
3
I
2
VCC=5V
Outputs Enabled
No Load
4.5
3.5
2.5
~
DATA INPUT VOLTAGE
4
~
!i
!0
vs
DATA INPUT VOLTAGE
NoLoed
Outputs Enabled
TA=25·C
4.5
>1
Y OUTPUT VOLTAGE
vs
VCC=4.5V-
>
I
GI
TA=125;C
3.5
'lI
01
.:!
~
!i
Q.
!i
0
1
~
1.5
4
0.5
3
,,/ TA=25·C
2.5
,,/ TA=O·C
TA=70~
2
r--..
1.5
0.5
o
o
o
0.5
1.5
2
2.5
o
3
0.5
1.5
VI - Data Input Voltage - V
vs
ENABLE G INPUT VOLTAGE
ENABLE G INPUT VOLTAGE
VCC=5.5V
3.5
Vec=5V
I"
I
3
i'
~
!i
Q.
!i
>
1
GI
GI
Vee=4.5V
2
0
1
1.5
~
~
VI=2V
RL = 470 ctoGND _
See Note A
TA=25·e
0.&
o
o
0.5
1.5
2
2.5
5
Vee=5V
4.5 _VI=2V
RL .. 470 C to GND
4 - See Note A
3.5
TA=125~e
~
i
.:
~
!i
Q.
!i
2.5
0
I
3
Y OUTPUT VOLTAGE
vs
4
.:
2.5
Figure 6
Y OUTPUT VOLTAGE
1
2
VI- Data Input Voltage - V
Figure 5
>
/ ' TA=-55·C
3
VTA= 25·e
2.5
TA=7O·~
2
""'lII
1.5
-
V
TA=o·e
./ TA=-55·e
0.5
3
o
o
VI- Enable G Input Voltage - V
Figure 7
0.5
1.5
2
2.5
3
VI - Enable G Input Voltage - V
Figure 8
t Dale for temperatures below o·e and above 70·e are applicable to SN55ALS194 circuits only.
NOTE A: The A input is connected to Vee during the testing of the Y outputs and to GND during the testing of the Z outputs.
POST OFFICE BOX 655303 • DAUAS. TEXAS 75265
2~01
SN55ALS194, SN75ALS194
QUAD DIFFERENTIAL LINE DRIVERS
WITH 3-STATE OUTPUTS
SLLSOO9C - 02917. OCTOBER 1985 - REVISED MARCH 1993
TYPICAL CHARACTERISTICSt
Z OUTPUT VOLTAGE
va
ENABLE G INPUT VOLTAGE
ENABLE G INPUT VOLTAGE
6
VCC=5V
g
t
4
4
V
~
i
3
/' V
V
3
......
I
2
o
~
o
0.5
1.5
2.5
2
2
o
3
o
0.5
VI - Enable G Input Voltage - V
~
g
I
:E
I
:r
~
va
FREE-AIR TEMPERATURE
HIGH-LEVEL OUTPUT CUR,=,ENT
>I
.
CI
III
.=
~
5
-
2.5
2
~IIIIIIIII
-50 -25
0
25
4
....
3.5
.......
§
3
!
2.5
50
75
100
125
:i:
I
,,
-""
~
/VCC=6.6V
~'\ ~
"~'\ ~
2
'\
1.5
0.5
/VCC=5V
I.
1
...
.... VCC=4.5V
~ "\
"
:r
~
l"I"
'\
'\ l'\ ~
o
r\. '\.
o -10 -20-30-40-50-60-70-60-90-100
TA - Free-Air Temperature _·C
IOH - High-level Output Current - mA
Figure 11
Figure 12
t Data for temperatures below O·C and above 70·C are applicable to the SN55ALS194 circuits only.
NOTES: A. The A input is connected to VCC during the testing of the Y outputs and to GND during the testing of the Z outputs.
B. The A input is connected to ground during the testing of the Y outputs and to VCC during the testing of the Z outputs.
1ExAs ."
INSIRUMENTS
2~02
3
5
TA=25·C
4.5 _ See Note A
CI
-76
2.5
2
HIGH-LEVEL OUTPUT VOLTAGE
4
3
TA=-SS·C _
vs
VCC=5V
IOH =-20 mA
See Note A
3.5
-
-
TA=OOC
Figure 10
5
J
TA=70·C
VI- Enable G Input Voltage - V
HIGH-LEVEL OUTPUT VOLTAGE
>I
TA=125·C TA=25·C
1.5
Figure 9
4.5
/'
~ ~/' V
o
I
~
I I
>I
I
f
VCC=6V
RL = 470 CtoVCC
See Note B
5
VCC=4.5V
>
..
6
RL=470CtoVCC
TA=25·C
See Note A
VCC=5.5V
5
Z OUTPUT VOLTAGE
vs
, POST OFFICE BOX 655303 • DALlAS. TEXAS 75265
SN55ALS194, SN75ALS194
QUAD DIFFERENTIAL LINE DRIVERS
WITH 3-STATE OUTPUTS
SLlSOO9C - 02917, OCTOBER 1985 - REVISED MARCH 1993 .
TYPICAL CHARACTERISTICS
LOW-LEVEL OUTPUT VOLTAGE
LOW-LEVEL OUTPUT VOLTAGE
va
va
FREE-AIR TEMPERATURE
LOW-LEVEL OUTPUT CURRENT
0.5
VCC=5V
IOL=-2OmA
See Note A
0.45
>
I
>
I
0.4
II
f
0.35
~
5Q.
5
0.3
0
!
0.25
oJ
0.15
r-- roo-
0.2
~
I
-
-
"--..
oJ
~
0.8
~
0.7
5Q.
5
--
0
~
~
I
0.6
0.5
o
-50 -25
0
25
50
75
~
0.3
0.2
100
o
125
~
o
10
60
vs
SUPPLY VOLTAGE
40
Outputs Enabled
No Load
TA=25·C
A Inputs o~en
0; Grou~ded
35 t-0utputs Dlaabled
>-
40
No Load
TA=25·C
30
V
E
I
~
0
Inputs Grounded
C5.
Q.
~
Q.
InputaOpen
:::I
30
I
JM
20
.... ~ "
10
o
o
70
SUPPLY VOLTAGE
1:
2!
0
50
SUPPLY CURRENT
50
9
40
va
I
:::I
30
SUPPLY CURRENT
1:
2!
(J)
20
Figure 14
c(
~
0
VCC=5.5V
Figure 13
60
E
P""
(J)
~
25
20
/
15
I
0
9
I
10
90 100
o
7
8
/
,/
L
V
/
5
-"
2
3
4
5
6
VCC - Supply Voltage - V
80
IOL - Low-Level Output Current - mA
80
c(
tJIfi'
~
1/
TA - Free-Air Temperature _·C
70 t-
~V
A
0.4
0.1
0.05
-75
II
1 I
lb ~ V-
VCC=5V
oJ
~
0.1
J
VCC=4.5V
II
CI
~
I
TA =25·C
See Note A
0.9
./
o
2
3
4
5
6
7
8
VCC - Supply Voltage - V
Figure 15
Figure 16
t Data for temperatures below O·C and above 70·C are applicable to the SN55ALS194 circuits only.
NOTE A: The A input is connected to GND during the testing of the Y outputs and to VCC during the testing of the Z outputs.
1ExAs . "
INSIRUMENIS
POST OFFICE BOX 655303 • DAllAS, TEXAS 75265
2-803
SN55ALS194,SN75ALS194
QUAD DIFFERENTIAL LINE DRIVERS
WITH 3-STATE OUTPUTS
SLLSOO9C-D2917, OCTOBER 1985-REVISED MARCH 1993
TYPICAL CHARACTERISTICS
SUPPLY CURRENT
va
FREQUENCY
60
""
VCC=s'v
,
Input: 0 to 3 V
50 - Duty Cycle = 50'!(,
CL = 30 pF to All Outputs
/
CC
E
I
C
40
§
0
30
i
~",
::I
f/)
I
20
0
.E
10
o
10k
100k
1M
10M
f - Frequency - Hz
Figure 17
1ExAs
,If
INSIRUMENTS
2-804
POST OFFICE BOX 655303 • DALlAS, TEXAS 75265
100M
SN55ALS195, SN75ALS195
QUAD DIFFERENTIAL LINE RECEIVERS
WITH 3-STATE OUTPUTS
SLLS01OC-
•
•
•
•
•
•
•
•
•
JUNE 1986 - REVISED MARCH 1993
SN5GALSl95 ••• J OR W PACKAGE
SN75ALSl95 ••• J PACKAGE
Meets EIA Standards RS-422-A and
RS-423-A
Meets CCITT Recommendations V.10, V.11,
x'26, and X,27
-7 V to 7 V Common-Mode Input Voltage
Range With 200-mV Sensitivity
3-State TTL-Compatlble Outputs
High Input Impedance ••• 12 kQ Min
Input Hysteresis ••• 120 mV Typ
Single SOV Supply Operation
Low Supply Current Requirement
35 mA Max
Improved Speed and Power Consumption
Compared to MC3486
(TOP VIEW)
16
1A
1Y
1,2EN
2Y
2A
26
GND
1 U 16
Vee
2
3
4
5
6
46
!7
I
8
15
14
13
12
11
10
9
4A
4Y
3,4EN
3Y
3A
36
SN55ALSl95 ••• FK PACKAGE
(TOP VIEW)
description
The SN55ALS195 and SN75ALS195 are
monolithic quad line receivers with 3-state
outputs designed using advanced low-power
Schottky technology. This technology provides
combined improvements in die design, tooling
production, and wafer fabrication, which in turn,
provide lower power consumption and permit
much higher data throughput than other
designs. The devices meet the specifications of
EIA Standards RS-422-A and RS-423-A. The
3-state outputs permit direct connection to a
bus-organized system with a fail-safe design
that ensures the outputs will always be high if
the inputs are open.
1Y
1,2EN
NC
2Y
2A
4
5
6
7
8
3 2 1 2019
18
17
16
15
14
9 10 11 12 13
4A
4Y
NC
3,4EN
3Y
CDCOCD<
NZZC'?C'?
0
NC - No internal connection
The devices are optimized for balanced multipoint bus transmission at rates up to 20 megabits per second. The
input features high input impedance, input hysteresis for increased noise immunity, and an input sensitivity of
± 200 mV over a common-mode input voltage range of ± 7 V. The devices also feature an active-high enable
function for each of two receiver pairs. The SN55ALS195 and SN75ALS195 are designed for optimum
performance when used with the SN55ALS194 and SN75ALS194 quad differential line drivers.
The SN55ALS195 is characterized for operation over the full military temperature range of - 55°C to 125°C. The
SN75ALS195 is characterized for operation from O°C to 70°C.
TEXAS
..If
Copyright @ 1993. Texas Instruments Incorporaled
INSIRUMENIS
POST oFFICE BOX 655303 • DALLAS, TEXAS 75265
2-805
SN55ALS195, SN75ALS195
QUAD DIFFERENTIAL LINE RECEIVERS
WITH 3-STATE OUTPUTS
SLLS010C - 02928, JUNE 1988 - REVISED MARCH 1993
logic symbol t
1,2EN
1A
1B
2A
2B
3,4EN
3A
3B
4A
4B
4
,
~
EN
2
1
logic diagram
"-
]
1,2EN
Et>
3
V
6
,
2A
~
EN
10
"-
]
>--+_...:3,--- 1Y
Et>
8
>-___5_
7
2B
3Y
13
12
3,4EN
4Y
"
3A
3B
tThls symbolls In accordance with ANSI/IEEE Std 91-1984
and lEe Publication 611-12.
4A
4B
10
11
9
>--+---
3Y
14
>-___1_3_
4Y
15
Pin numbers shown are for the J and W packages.
FUNCTION TABLE
(each receive.,
DIFFERENTIAL INPUTS
A-B
ENABLE
EN
OUTPUT
VID:tO.2V
H
H
-O.2V < VID < O.2V
H
?
VIDs-O.2V
H
L
X
L
Z
Open
H
H =high level, L =low level, X = Irrelevant, ?
Z high impedance (off)
=
1ExAs
Y
H
=Indeterminate,
..If
INSIRUMENIS
2-808
2Y
11
V
14
15
2
2Y
"-
12
9
1A
1B
8
7
1Y
4
POST OFFICE BOX 855303 • DALlAS. TEXAS 75286
SN55ALS195,SN75ALS195
QUAD DIFFERENTIAL LINE RECEIVERS
WITH 3-STATE OUTPUTS
SLLS010C - 02928, JUNE 1986 - REVISED MARCH 1993
schematics of inputs and outputs
EQUIVALENT OF EACH A OR B INPUT
Vee
------~.---~--
EQUIVALENT OF EN INPUTS
EQUIVALENT OF ALL OUTPUTS
Vee--------~--~--
VCC
3kO
NOM
5OkO
NOM
18kO
NOM
Input _-'VVIr-.......---1
Output
Input
3OOkO
NOM
VCC(A)
or
GND(B)
2kO
NOM
GND --'--,-~---
GND------__~~~--
GND
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage, Vee (see Note 1) .. , , ........................................................ 7 V
Input voltage, A orB inputs, VI ............................................................. :1:15 V
Differential input voltage (see Note 2) ....................................................... :1:15 V
Enable input voltage ......................................................................... 7 V
Low-level output current .................................................................. 50 mA
Continuous total dissipation ........................................... See Dissipation Rating Table
Operating free-air temperature range: SN55ALS195 ................................ - 55°C to 125°C
SN75ALS195 .................................... O°C to 70°C
Storage temperature range ....................................................... - 65·C to 150·C
Case temperature for 60 seconds: FK package .............................................. 260°C
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: J or W package ................ 300°C
t Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and
functional operalion of the device at these or any other conditions beyond those indicated under recommended operating condHons is not implied.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values, except differential input voltage, are with respect to network ground terminal.
2. Differenlial-input voltage is measured at the noninverting input with respect to the corresponding inverting input.
DISSIPATION RATING TABLE
PACKAGE
TAs25°C
POWER RATING
DERATING FACTOR
ABOVE TA 25°C
=
=
=
70°C
TA
POWER RATING
TA
125°C
POWER RATING
FK
1375mW
11.0mWrC
880mW
275mW
J (SN55ALS195)
J (SN75ALS195)
1375mW
11.0mWrC
880mW
275mW
1025mW
8.2mWrC
656mW
N/A
W
1000mW
8.0mWrC
690mW
200mW
1ExAs
'If
INSIRUMENIS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
2-807
SN55ALS195,SN75ALS195
QUAD DIFFERENTIAL LINE RECEIVERS
WITH 3-STATE OUTPUTS
SLLS010C - 02928. JUNE 1986 - REVISED MARCH 1993
recommended operating conditions
SN~ALS195
SN75ALS195
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.75
5
5.25
Supply voltage. Vee
Common-mode Input voltage. VIC
Olfferential input voltage. VIO
High-level input voltage. VIH
High-level output current. 10H
",7
V
",12
",12
V
2
V
0.8
0.8
-400
-400
ItA
16
rnA
70
·e
16
Low-level output current. 10L
Operating free-alr temperature. TA
-55
V
",7
2
Low-level Input voltage. VIL
UNIT
125
0
V
electrical characteristics over recommended ranges of common-mode input voltage, supply
voltage, and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONOITIONSt
VT+
VT-
Positive-going threshold voltage
Vhys
Hysteresis (VT
VIK
Enable-input clamp voltage
Vee = MIN.
11= -18mA
VOH
High-level output voltage
Vee = MIN.
See Figure 1
VID=200mV.
VOL
Low-level output voltage
Vee=MIN.
VIO = - 200 mY.
See Figure 1
10Z
II
MIN
-200§
+- VT -l
Line input current
IIH
High-level enable-Input current
IlL
Low-level enable-input current
Short-circuit output current
2.5
3.6
IOL=8mA
0.45
IOL=16mA
0.5
V
VIL= 0.8V.
VIO=-3V.
Vee = MAX.
VO=0.5V
VIL=0.8V.
VID=3V.
Other input at 0 V.
See Note 3
Vee = MIN.
VI=15V
0.7
1.2
Vee = MAX.
VI =-15V
-1
-1.7
Vee = MAX.
Vee = MAX.
See Note 4
V
V
Vee = MAX.
VO=2.7V
Vee = MAX
mV
mV
-1.5
10H = - 400 ItA.
UNIT
mV
120
20
ItA
-20
VIH =2.7V
20
VIH = 5.25 V
100
-100
VIL=0.4V
Input resistance
los
MAX
200
Negative-going threshold voltage
High-impedance state
output current
TYp:j:
VIO=3V.
Vo=O.
12
18
-15
-78
rnA
ItA
ItA
kQ
130
rnA
Supply current
Outputs disabled
22
35
rnA
Vee = MAX.
.~
"
t For conditions shown as MIN or MAX. use the appropriate values speCified under recommended operating conditions.
:I: All typical values are at Vee = 5 V. TA = 25·e.
§ The algebraic convention. in which the less positive limit is designated minimum. is used in this data sheet for threshold voltage levels only.
NOTES: 3. Refer to EIA Standards RS-422-A and RS-423-A for exact conditions.
4. Not more than one output should be shorted at a time. and the duration of the short circuit should not exceed one second.
1E:xAs . "
INSIRUMENIS
2~08
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
SN55ALS195, SN75ALS195
QUAD DIFFERENTIAL LINE RECEIVERS
WITH 3-STATE OUTPUTS
SLLS010C - 02928. JUNE 1986 - REVISED MARCH 1993
switching characteristics, VCC
=5 V, CL =15 pF, TA =25°C
PARAMETER
TEST CONDITIONS
tpLH
Propagation delay time. low-to-high-Ievel output
tpHL
Propagation delay time. hlgh-to-Iow-Ievel output
tpZH
Output enable time to high level
tPZL
Output enable time to low level
tpHZ
Output disable time from high level
tpLZ
Output disable time from low level
MIN
VID=OVtoSV. See Figure 2
See FigureS
See FigureS
TYP
MAX
UNIT
15
22
ns
15
22
ns
1S
25
10
25
19
25
17
22
ns
ns
PARAMETER MEASUREMENT INFORMATION
IIOH
t(-)
2V----'
Figure 1. VOH, VOL
SOg
~~~---::
InP:d
1.SV
I
I
tpLH - .
-.!
t+- tpHL
_--~I----YOH
1.SY
1.SY
Output
VOL
2Y-------'
TEST CIRCUIT
VOLTAGE WAYEFORMS
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR " 1 MHz. duty cycle" 50%. Zo = 50 g.
tr " 6 ns. tf" 6 ns.
B. CL Includes probe and jig capac~ance.
Figure 2. Test Circuit and Voltage Waveforms
1ExAs . "
INSIRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
2-a09
SN55ALS195,SN75ALS195
QUAD DIFFERENTIAL LINE RECEIVERS
WITH 3-STATE OUTPUTS
SUS01OC-D2928, JUNE 1986- REVISED MARCH 1993
PARAMETER MEASUREMENT INFORMATION
SW1
Output
2.5 V
-2.5V ---0
2kQ
SW2
o-5V
5kO
(see Note C)
CL =15pF
'I' (see Note 8)
Generator
(see Note A)
510
TEST CIRCUIT
tpZL
tPZH
SW1 to 2.5 V
SW20pen
SW3Closed
Input
I
--
'----~'-r
tPZH
--+t
~
OV
1.5V
Input
I
'------I.-II
,
!---1.5V
....
,-----
SW1 to-2.5V
SW2Closed
SW30pen
l+I
~--4.5V
I , - - - - VOH
\.
0V
tpZL ~
I
----.
Output
3V
3V
Output
--OV
---f
L
1.5V
VOL
3V
SW1 to 2.5 V
SW2Closed
SW3Closed
SW1 to-2.5V
SW2Closed
SW3Closed
~
I
VOH
Output _ _ _
J~5V
1.4V
VOL
1.4V
VOLTAGE WAVEFORMS
NOTES: A The input pulse is supplied by a generator having the following characteristics: PRR '" 1 MHz, duty cycle", 50%, Zo = 50 0,
tr '" 6 ns, tf'" 6 ns.
B. CL includes probe and jig capacftance.
C. All diodes are 1N3064 or equivalent.
Figure 3. Test Circuit and Voltage Waveforms
2-810
POST OFFICE BOX 655303 • DAUAS, TEXAS 75265
SN55ALS195,SN75ALS195
QUAD DIFFERENTIAL LINE RECEIVERS
WITH 3-STATE OUTPUTS
SLLS010C - 02928, JUNE 1986 - REVISED MARCH 1993
TYPICAL CHARACTERISTICSt
OUTPUT VOLTAGE
OUTPUT VOLTAGE
va
va
ENABLE VOLTAGE
ENABLE VOLTAGE
5
4
>I
1
VCC=5.5V
>
VCC=5V
.
3
.1TA = 125"C
TA = 70°C TA = 25°C
_TA= O°C
3
0
2
t
g
~
!i
I
I
~
~
o
o
TA=-55°C
2
VCC=5V
VIO=200mV
VIC=O
RL=8kOtoGNO
0.5
1.5
2
2.5
o
o
3
0.5
Figure 4
va
ENABLE VOLTAGE
ENABLE VOLTAGE
VCC=5V
5
VCC=4.5V
I
I
5
>
.
4
I
~
~
3
!i
r::a.
!i
0
2
I
~
....... ~TA=O°C
4
~TA=25°C
r-r-- ~ TA=70°C
3
.... f-
~
2
~
o
o
0.5
1.5
2
2.5
3
I
~- TA=-55°C
CI
~
0
3
6
II
Vlo=-200mV
VIC=O
RL=1 kQtoVcc TA=25°C
VCC=5.5V
2.5
OUTPUT VOLTAGE
va
6
~
!i
r::a.
!i
2
Figure 5
OUTPUT VOLTAGE
II
CI
1.5
Enable Voltage - V
Enable Voltage - V
>I
--
I
VCC=4.5V
I
~
!i
r::a.
!i
4
I
VIO=200mV
VIC =0
RL= 8kOto GNO
TA = 25"C
-
!--- TA = 125°C -
II II
VCC=5V
Vlo=-200mV
VIC =0
RL= 1 kOto Vcc
o
o
Enable Voltage - V
0.5
1.5
2
2.5
3
Enable Voltage - V
Figure 6
Figure 7
t Data for temperatures below QOC and above 7QoC. and below 4.75 V and above 5.25 V. are applicable to SN55ALS195 circuits only.
1ExAs'"
INSIRUMENTS
POST OFFICE BOX 655303 • DAUAS, TEXAS 75265
2-811
SN55ALS195,SN75ALS195
QUAD DIFFERENTIAL LINE RECEIVERS
WITH 3-STATE OUTPUTS
SLLS010C - D2928, JUNE 1986 - REVISED MARCH 1893
'TYPICAL CHARACTERISTICSt
OUTPUT VOLTAGE
5
VS
DIFFERENTIAL INPUT VOLTAGE
FREE-AIR TEMPERATURE
4
VCC=5V
VIC =-12Vto 12V
10=0
TA=25·C
4.5
,
HIGH-LEVEL OUTPUT VOLTAGE
vs
4
10H=0
>
..
1
>
.
1
~
15
3.5
I
3
3
5
2.5
0
2
~
~
2.5
0
~
2
1
vT-
~
3.5
VT+
1.5
~
V
~
~
........ Io'tt = -~!lA
1.5
CII
:f
1
J:
~
0.5
o
-200 -150 -100 -50
0
50
100
150
VCC=5V
VIO=200 mV
VIC=O
0.5
o
200
-75 -50 -25
Figure 8
t
;e
5c:a.
5
0
~J::.
CII
!f
3.5
3
2.5
2
1.5
1
J:
~
0.5
o
.......
100
vs
HIGH-LEVEL OUTPUT CURRENT
'"'"I"" "-("
'" " "-"-V<
~
5
>1
ell
CII
!
~
,."VCC=5.5V
!,
1
!.
1
VCC=5V
VIO=2OOmV
VIC=O
4.5
/VCC=5V
I,
0
2.5
I
VCC=4.5V
~
'",
.c
.2'
J:
1
J:
"' " "'\
"' ..".'\. r\.
-?
"
l..
--.
3.5
3
~
..
4
5
-
~~
TA=-SS·C
.,.'
l/~ ~
2
TA ='70·C
1.5
~ TA=25·C
"~"\~~~
I~ ~
o -10 -20 -30 -40 -50 -60 -70-80 -80-100
10H - High-Level Output Current - mA
10H - High-Level Output Current - mA
Figure 10
Figure 11
t Data for temperatures below O·C and above 70·C. and below 4.75 V and above 5.25 V. are applicable to SN55ALS195 circuits only.
ThxAs
-
./
~~~
TA;'125·C
0.5
I'
~TA=O·~
o
o -10 -20 -30 -40 -50 -60 -70 -80-90-100
,If
INSIRUMENIS
2-812
125
HIGH-LEVEL OUTPUT VOLTAGE
VIO=2OOmV
VIC =0
TA=25·C
.......
75
HIGH-LEVEL OUTPUT CURRENT
5
.......
50
vs
,4.5
4
25
Figure 9
HIGH-LEVEL OUTPUT VOLTAGE
>1
0
TA - Free-Air Temperature - ·C
VIO - Olfferentlallnput Voltage - mV
POST OFFICE BOX 655303 • DAUAS. TEXAS 75265
SN55ALS195, SN75ALS195
QUAD DIFFERENTIAL LINE RECEIVERS
WITH 3-STATE OUTPUTS
SLLS010C - 02928. JUNE 1986- REVISED MARCH 1993
TYPICAL CHARACTERISTICSt
LOW-LEVEL OUTPUT VOLTAGE
VS
FREE-AIR TEMPERATURE
0.40
0.35
>
I
VCC=5V
V'O =-200mV
V'C=O
GI
I
0.30
~
:i
0.25
0
0.20
~
~
0.15
~
...
I"--..
..... r-...
.......
'0=0
I
oJ
-...........
0.10
~
0.05
o
-75 -50 -25
-
'O=8mA
-- --
0
25
50
-
r--
75
100
125
TA - Free-A'r Temperature _·C
Figure 12
LOW-LEVEL OUTPUT VOLTAGE
VS
LOW-LEVEL OUTPUT CURRENT
LOW-LEVEL OUTPUT CURRENT
0.8
>
0.7
I
~
:i
Q.
:i
0
~
~
I
0.6 I - -
~
~
0.4
0.2
oJ
~
~
~~
t
~
~
I
I
I
II'"
oJ
~
V'O=-200mV
V'C=O
TA=25·C
0.1
o
>I
'bVJ
0.5
0.3
JJ
J /
VCC=4.5V~..........
VCC=5V
........
VCC=5.5V,
I
GI
LOW-LEVEL OUTPUT VOLTAGE
VB
0.1
~-4--+--I--+--1I--+--+--I
o~~-~-~--~~~~--~~
o
10
20
30
40
50
60
70
80
o
'OL - Low-Leve' Output Current - mA
10
20
30
40
50
60
70
80
'OL - Low-Leve' Output Current - mA
Figure 13
Figure 14
t Data for temperatures below O·C and above 70·C. and below 4.75 V and above 5.25 V. are applicable to SN55Al.S195 circuits only.
1ExAs
~
INSIRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
2-813
SN55ALS195, SN75ALS195
QUAD DIFFERENTIAL LINE RECEIVERS
WITH 3-STATE OUTPUTS
SLLS010C - 02928. JUNE 1986 - REVISED MARCH 1993
TYPICAL CHARACTERISTICSt
SUPPLY CURRENT
SUPPLY CURRENT
va
va
SUPPLY VOLTAGE
FREE-AIR TEMPERATURE
50
40
~
30
V,D =-200 mV
V,C=O
10=0
TA=25·C
46
25
35
0
~
a.
:s
30
DIsabled ~
J.'
if
25
20
II)
I
0
.9
15
~
I
C
-
5
0
~
Enabled
o
2
3
15
II)
I
0
10
.9
5
,/
o
4
VCC =4.5V
8:
:s
~
~
20 r---
§
~
10
VCC=5V
~
//
I
C
~:s
II
VCC=6.5V
5
7
6
o
8
V,D =-200 mV
Outputs Enabled
10=0
I
I
I
-75 -50 -25
Figure 15
va
DIFFERENTIAL INPUT VOLTAGE
FREQUENCY
I
.l
I
I
35
c(
E
VCC=5V
20
VCC=4.5V
:s
0
a.
a.
I
I
30
C
~:s
25
~
15
10
5
a.
a.
:s
20
I
15
(
"..,
0
.9
10
10=0
Outputs Enabled
V,C=O
TA=25·C
o
-200
-100
5
o
100
200
o
10 k
VID - DIfferential Input Voltage - mV
100k
1M
10M
f - Frequency - Hz
Figure 17
Figure 18
t Data for temperatures below O·C and above 70·C. and below 4.75 V and above 5.25 V. are applicable to SN55ALS195 circuits only.
1ExAs
..If
INSIRUMENTS
2-814
125
II)
I
.9
100
~
VCC=5V'
V, = '" 1.5-V Square Wave
CL=15pF
Four Channels Driven
TA=25·C
0
01
0
.....
40
VCC=5.5V
25
75
SUPPLY CURRENT
va
30
~
50
Figure 16
SUPPLY CURRENT
!
25
TA - Free-Air Temperature _·C
VCC - Supply Voltage - V
~
0
POST OFFICE BOX 655303 • DAUAS. TEXAS 75265
100M
SN55ALS195, SN75ALS195
QUAD DIFFERENTIAL LINE RECEIVERS
WITH 3·STATE OUTPUTS
SLLS010C - 02928. JUNE 1986 - REVISED MARCH 1993
TYPICAL CHARACTERISTICSt
INPUT CURRENT
INPUT RESISTANCE
vs
vs
FREE-AIR TEMPERATURE
INPUT VOLTAGE TO GND
3
30
TA'=25·d
25
2
a
--
.:0:
I
~
I
16
-
II:
5Q,
.5
"
- ---
20
V
~
I
C
f
!s
u
0
5Q,
,
.5
10
I
,...".
-1
V
.....-
/
V
./
.:
-:
6
r-~---+--~--+---r-~---+--~
-2
o
~~
__~__~__~__L-~__~__~.
-3
-75 -50
-25
0
25
50
75
100
-20 -15 -10
125
TA - Free-Alr Temperature - ·C
-5
6
0
10
15
20
VI -Input Vohage to GND - V
Figure 19
Figure 20
SWITCHING CHARACTERISTICS
PROPAGATION DELAY TIME
VS
vs
FREE-AIR TEMPERATURE
SUPPLY VOLTAGE
20
VCC=5V
CL=15pF
...
,
25r-~r--+---+--~--+---+
c
16
III
E
1=
~
Gi
Q
c
i
5r-~~-+---+--~--+-~r-~---;
I
....
tpHL
14
tPLH
12
10
:il'
Q,
8
,
6
J.
4
e
a..
CL= 15pF
TA=25'C
18
2
0L-~__~__~__~__~~~~__~
-75 -50
-25
0
25
50
75
100
TA - Free·Alr Temperature -'C
125
o
4.5 4.6 4.7 4.8 4.9
6
5. 1 5.2 5.3 5A 5.6
Vec - Supply Vohege - V
Figure 22
Figure 21
t Data for temperatures below O'C and above 70·C. and below 4.75 V and above 5.25 V. are applicable to SN55ALS195 circuits only.
1ExAs..lf
INSTRUMENIS
POST OFFICE BOX 655303 • DAUAS. TEXAS 75265
2~15
2--a16
SN75ALS197
QUAD DIFFERENTIAL LINE RECEIVER
WITH 3·STATE OUTPUTS
JANUARY 1989 - REVISED MARCH 1993
•
•
•
•
•
•
•
•
•
•
Meets CCITT Recommendations V.10, V.11,
><'26, and ><'27
Designed for Multipoint Bus Transmission
on Long Bus Lines in Noisy Environments
3-State Outputs
Common-Mode Input Voltage Range
-7Vt07V
Input Sensitivity .•. ± 300 mV
Input Hysteresis .•• 120 mV Typ
High Input Impedance •.. 12 kQ Min
Operates from Single SOV Supply
Low Supply Current Requirement
35 mA Max
Improved Speed and Power Consumption
Compared to AM26LS32A
o OR N PACKAGE
(TOP VIEW)
Vee
1B
4B
4A
4Y
G
2Y
2A
3Y
3A
28
GND
logic symbol t
G
G
4
.. 1
12
EN
....
0r-
description
The SN75ALSI97 is a monolithic quad line
receiver with 3-state outputs designed using
advanced low-power Schottky technology. This
technology provides combined improvements in
bar design, tooling production, and wafer
fabrication. This, in turn, provides significantly less
power requirements and permits much higher
data throughput than other designs. The device
meets
the
specifications
of
CCITT
Recommendations V.1 0, V.11, X.26, and X.27. It
features 3-state outputs that permit direct
connection to a bus-organized system with a
fail-safe design that ensures the outputs will
always be high if the inputs are open.
1A
18
2A
28
3A
38
4A
48
t
2
1
"'"
]
r
.lrl>
3
V
6
7
5
'","
10
11
9
1Y
2Y
3Y
"'"
14
15
13
'"
4Y
This symbol is in accordance wHh ANSI/IEEE Std 91-1984 and
lEe Publication 617-12.
logic diagram (positive logic)
The device is optimized for balanced multipoint
bus transmission at rates up to 10 megabits per
second. The input features high input impedance,
input hysteresis for increased noise immunity, and
an input sensitivity of ±300 mV over a
common-mode input voltage range of -7 V to 7 V.
It also features active-high and active-low enable
functions that are common to the four channels.
The SN75ALS197 is designed for optimum
performance when used with the SN75ALS192
quad differential line driver.
G
G
1A
3
1Y
1B
2A
2B
3A
The SN75ALS197 is characterized for operation
from O·C to 70·C.
TEXAS
2
3B
6
5 2Y
7
10
11 3Y
9
4A
14
4B
15
,If
13 4Y
Copyright © 1993. Texas Instruments Incorporated
INSTRUMENTS
POST OFFICE BOX 655303 • OALLAS, TEXAS 75265
2-817
SN75AlS197 .
QUAD DIFFERENTIAL liNE RECEIVER
WITH3-STATE OUTPUTS
SlLS045A- 03203, JANUARY 1989 - REVISED MARCH 1993
FUNCTION TABLE
(each receiver)
DIFFERENTIAL INPUTS
A-B
VID",O.3V
ENABLES
G
G
H
X
X
L
-O.3V--+--e--
I
I
I
_J
I
~
' __ _ _ -2,5V
Output
~tpHL
---..... t---
CL=15pF
(see Note B)
VOH
Output
VOL
VOLTAGE WAVEFORMS
TEST CIRCUIT
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR s 1 MHz, duty cycle s 50%, Zo
tr s 6 ns, tf " 6 ns.
B. CL includes probe and jig capac~ance.
=50 Q,
Figure 2. tpLH. tpHL Test Circuit and Voltage Waveforms
1ExAs~
INSIRUMENTS
POST OFFICE BOX 656303 • DAUAS. TEXAS 75265
2-821
SN75ALS197
QUAD DIFFERENTIAL LINE RECEIVER
WITH 3-STATE OUTPUTS
SUS045A- 03203, JANUARY 1989 - REVISED MARCH 1993
PARAMETER MEASUREMENT INFORMATION
Test
Point
S1
...........t -....- i...-
From Output Under Test
..
See Note B
LOAD CIRCUIT
I
I
I
-.l 1'-" 5 na
F
I I
Enable
G
10%
I I
II
I
1~
Output
I
I"
S10pen
S2 Closed
I
r.::
I
10%
.'
II
I
lpzJi
F:
:1~
10%
II~---OV
3V
Enable
G
10%
I
I
I"
I
- .I -
VOH
-1.4 V
.1
1.3V
Output
Sl Closed
S20pen
S1 Closed
S2Cloaed
VOLTAGE WAVEFORMS FOR tpHZ, tpZH
I
-+1 k-
~V
SeeNoteC
I
10%
I
I"
.'
_..;..._..,.1
------OV
I
~ 0.5 V
L
~
'll
G
iR1:-
II
I
Enable 90%
I
I
-.l 1'-" 5 na
I
r-----3V
~V I
T~i "'N~C
"k
.3V
I
-+1 1+-" 5 na
r - - - - - 3V
I I
I
10%
II~---OV
~111r1=~_3V
I
90%
1.3V
10%
tpZL
II
i'
L..
-----OV
S1 Cloaed
S2 Closed
.1
'1./7""
VOLTAGE WAVEFORMS FOR tpLZ. tpZL
Figure 3. tPHZ, tpZH. tpLZ. tpZL Load Circuit and Voltage Waveforms
1ExAs ."
INSTRUMENTS
POST OFFICE BOX 655303 • DAUAS, TEXAS 75265
-1.4V
L_t:~"-!-: VOL
-L O•5V
NOTES: A. CL Includes probe and jig capacftance,
B, All diodes are 1N3064 or equivalent.
C, Enable G is tested with G high; G is tested wfth Glow,
2-822
"sna
I
SN75ALS197
QUAD DIFFERENTIAL LINE RECEIVER
WITH 3-STATE OUTPUTS
SLLS045A- 03203, JANUARY 1989- REVISED MARCH 1993
TYPICAL CHARACTERISTICS
OUTPUT VOLTAGE
5
I
>I
GI
DI
•
=
~
"5a.
"5
0
I
~
VB
ENABLE VOLTAGE
ENABLE VOLTAGE
4
I
VIO=300mV
VIC=O
RL=8kOtoGNO
TA = 25°C
4.5
4
OUTPUT VOLTAGE
VB
J
TA=70°C TA = 25°C
TA=O°C
3.5
VCC=5.5V
>I
VCC=5V
3.5
3
GI
i
VCC=4.5V
3
1::
2.5
2.5
"5
a.
!i
2
~
0
2
I
1.5
~
1.5
VCC=5V
VIO=300mV
VIC=O
RL=8kOtoGNO
0.5
0.5
o
o
0.5
1.5
2
2.5
o
o
3
0.5
Figure 4
Figure 5
VB
ENABLE VOLTAGE
ENABLE VOLTAGE
I
VCC=5V
VCC=4.5V
I
~
!i
a.
!i
5
>
..i
I
4
=
~
"5
a.
!i
3
0
___ TA=O°C
4
I--- TA = 25°C
-
L.--- TA = 70°C
3
0
I
~
3
6
...
VIO =-300 mV
VIC =0
RL=1 kOtoVcC TA=25°C
5
2.5
OUTPUT VOLTAGE
VB
VCC=5.5V
CD
2
Enable Voltage - V
6
>
1.5
Enable Voltage - V
OUTPUT VOLTAGE
,
.....
I
2
~
2
VCC=5V
VIO =-300 mV
VIC=O
RL=1 kOto VCC
o
o
0.5
1.5
2
2.5
3
o
o
Enable Voltage - V
0.5
1.5
2
2.5
3
Enable Vohage - V
Figure 6
Figure 7
1ExAs
~
INSIRUMENTS
POST OFFICE BOX 655303 • DAUAS. TEXAS 75265
2-823
SN75ALS197
QUAD DIFFERENTIAL LINE RECEIVER
WITH 3-STATE OUTPUTS
Sll.S045A- 03203. JANUARY 1989 - REVISED MARCH 1993
TYPICAL CHARACTERISTICS
OUTPUT VOLTAGE
HIGH-LEVEL OUTPUT VOLTAGE
va
va
DIFFERENTIAL INPUT VOLTAGE
FREE-AIR TEMPERATURE
5
>1
•
I
3
i
2.5
1
~
10H=0
>1
•
f
3.5
~
0
4
VCC"I5V
4.5 VIC=-12Vto12V
10=0
4 TA=25"C
i
S
3.6
~
_1-
10H = - 400 JAA
3
2.6
0
2
VT_
J:.
CII
:i:
Vy+
1.5
2
1.6
1
:c
~
VCC=5V
VIO=300mV
VIC=o
0.5
0.5
o
-200 -150 -100 -50
0
50
100
150
o
200
o
ro
20
30
40
50
60
70
TA - Free-Air Temperature _·C
VIO - Oifferentlallnput Voltage - mV
Figures
Figure 9
HIGH-LEVEL OUTPUT VOLTAGE
4.5
i
4
~
!i
va
HIGH-LEVEL OUTPUT CURRENT
HIGH-LEVEL OUTPUT CURRENT
!
0
~~
1
5
=
VIO 300 mV
VIC=O
TA=25·C
........
3.6
........
3
.......
2.5
2
~
i'..
~
0.6
>
4.6
•
4
1
VCC=5V
Vlo=300mV
VIC=O
"'"'
'" ".r
.....
~
~
~
!i
."VCC=5.5V
!CC=5V
VCC=4.5V
'\
3
~
2.5
1
1.5
~
:c
'\ '\
'\ .'\ .'\.
~
~
2
0.5
.",-
V
~ ~ I---'
TA=O·C
I
I
TA=25·C
I
I
TA=70·C
,~
o
0-10 -20-30 -40 -50-60-70 -80-90-100
o -10 -20-30 -40 -50
10H - High-Level Output Current - mA
-«> -70
-80 -90-100
10H - High-level Output Current - mA
Figure 10
Figure 11
1ExAs
~
INSIRUMENTS
lHl24
~
~k
~~
~ '-
~
'\l\. \.
o
3.5
!
0
-
...
:t:
'\
~
-
CII
II
.....
1.5
HIGH-LEVEL OUTPUT VOLTAGE
va
5
>1
80
POST OFACE BOX 6S5303 • DAUM. TEXAS 75265
SN75ALS197
QUAD DIFFERENTIAL LINE RECEIVER
WITH 3·STATE OUTPUTS
Su..s045A- 03203, JANUARY 1989 - REVISED MARCH 1993
TYPICAL CHARACTERISTICS
LOW-LEVEL OUTPUT VOLTAGE
va
FREE-AIR TEMPERATURE
0.4
>
I
I
I
I
VCC=5V
0.35 ,... VID =-300 mV
VIC=O
0.3
0.25
IO=8mA
0.2
I -0.15
I
..I
~
10=0
0.1
0.05
o
o
10
20
30
40
50
60
70
80
TA - Free-Air Temperature _·C
Figure 12
LOW-LEVEL OUTPUT VOLTAGE
LOW-LEVEL OUTPUT VOLTAGE
va
vs
LOW-LEVEL OUTPUT CURRENT
LOW-LEVEL OUTPUT CURRENT
>I
>
i
8-
I
i
0.6..--t--
i
0.5
.3
I
I
..I
..I
~
j
~
I
~
VID",-3OOmV
0.1 1 - - + - + - + - - 4 - VIC 0
TA=25·C
=
O~~-~--~~--~--~~~~
o
ro
20
30
40
50
60
70
80
0.7 t--+--T-''--.--f'''''c":;-II-H+---ll---I
0.41---+--t----::11500"'~--+---f-__if___1
0.31---+--..q,,-+--+--+---f-__if___I
0.21-7~~+-+--t--I--+---l1---I
VCC=5V
0.1 f - - t - - I - - + - - i - VIO = -300 mV
VIC =0
OL-~--~-~--'-~-~-~~
o
10
IOL - Low-LeveI OUtput Current - mA
20
30
40
50
60
70
80
10L - Low-Level Output Current - mA
Figure 13
Figure 14
1ExAs'"
INSTRUMENTS
POST OFFICE BOX 855303 • DAlLAS, TEXAS 75265
2--a25
SN75ALS197
QUAD DIFFERENTIAL LINE RECEIVER
WITH 3-STATE OUTPUTS
SUS045A- 03203, JANUARY 1989 - Ri'MSED MARCH 1993
TYPICAL CHARACTERISTICS
SUPPLY CURRENT
VB
SUPPLY VOLTAGE
50
45
~
40
'E
35
I
§
(J
>-
ii
Q.
30
,
30
I
,
C
E
I
~
10
-V
5
o
o
Vee=5V
r--
20
Vee=4.5V
(J
J:o
Q.
Q.
'Enabled
15
25
I
25
20
II
Vee=5,5V
//
Disabled ~
(J
2
VB
FREE-AIR TEMPERATURE
VID=-300mV
Vle=O
10=0
TA=25°e
:::I
II)
SUPPLY CURRENT
15
:::I
II)
I
1/
(J
2
IP'
~
10
VID=-300mV
Outputs Enabled
10=0
5
o
o
2345678
I
I
I
W
20
30
Figure 15
I
VB
I
J:o
Q.
Q.
35
Vee=5.5V
~
I
Vee=5V
20
Vee=4.5V
(J
15
:::I
30
I
25
~
Q.
20
/
..,
:::I
I
10
5
o
(J
15
2
10
10=0
Outputs Enabled
Vle=O
TA=25°C
-200
-100
5
o
100
"" VID - Differential Input Voltage - mV
200
o
10k
Figure 17
2-826
I
II)
I
2
I
.....
VCC=5'V'
VI = '" 1.5-V Square Wave
CL=15pF
Four Channels Driven
TA=25°C
(J
II)
(J
50
FREQUENCY
40
I
~
50
.SUPPLY CURRENT
30
25
50
Figure 16
SUPPLY CURRENT
VB
DIFFERENTIAL INPUT VOLTAGE
~
40
TA - Free-Air Temperature - °C
Vee - Supply Voltage - V
100k
1M
f - Frequency - Hz
Figure 18
POST OFFICE BOX 655303 • DAUAS. TEXAS 75265
10M
100M
SN75ALS197
QUAD DIFFERENTIAL LINE RECEIVER
WITH 3-STATE OUTPUTS
SLlS045A- D3203, JANUARY 1989- REVISED MARCH 1993
TYPICAL CHARACTERISTICS
INPUT CURRENT
INPUT RESISTANCE
va
va
FREE-AIR TEMPERATURE
INPUT VOLTAGE TO GND
30
3
TA I=25°C
2
25
...c:I
3c
--
20
II
il
1a:
!i
c:\.
.5
I
15
~
f
0
!5
0
!i
c:\.
.5 -1
I
10
..,.,....,.V
-2
5
o
-3
o
10
20
30
40
SO
60
70
80
-20
-15
TA - Free-Air Temperature _ °e
III
~
!
10
PROPAGATION DELAY TIME
va
va
FREE-AIR TEMPERATURE
SUPPLY VOLTAGE
(tpZH
~
---:
eL=15pF
18 i- TA=25°e
~
.-- ~ =--f f--;;H'rf
-
.~
tPZL
tPHZJ
15
20
20
I
tPLH,
tpHZ_
15
10
5
VI-Input VoHage to GND - V
tPlz,
c
0
SWITCHING CHARACTERISTICS
20
:E
1=
-5
Figure 20
Vee=5V
eL=15pF
25
-10
Figure 19
30
I
V
.:
.=-
r!
V
.,.,V
I
1:
~
tpHL-
14
tpLH-
V
12
"-
10
l
I
16
8
6
4
5
2
o
o
o
10
20
30
40
so
60
70
80
4.5 4.6 4.7 4.8 4.9
TA - Free-Air Temperature - °e
5 5.1
5.2 5.3 5.4
5.5
Vee - Supply VoHage - V
Figure 22
Figure 21
1ExAs
..If
INSIRIJMENTS
POST OFFICE BOX 655303 • DAUAS. TEXAS 7526S
2-627
2-828
SN65C198, SN75C198
QUAD LOW·POWER LINE DRIVERS
SLLS051A-
JULY 1990 - REVISED MARCH 1993
o OR N PACKAGE
• Meets EIA-232-D (Revision of RS-232-C)
(TOP VIEW)
• Very Low Supply Current
• Sleep Mode:
3-State Outputs In High-Impedance State
Ultra-Low Supply Current ... 17 t-tA Typ
Vcc+
8M
4A
4Y
• Improved Functional Replacement for:
SN75188,
Motorola MC1488,
National Semiconductor DS14C88, and
D51488
2B
2Y
GND
•
•
•
•
CMOS- and TTL-Compatible Data Inputs
On-Chip Slew-Rate Limit ..• 30 VIlAS
Output Current Limit ... 10 mA Typ
Wide Supply Voltage Range. .. ±4.5 V
to ±15V
• E5D Protection Exceeds 500 V Per
MIL-STD-883C, Method 3015.2
3B
7
logic symbol t
13
lEN
~'
lA
2A
description
2B
The SN65C198 and SN75C198 are monolithic
low-power· BI-MOS quad low-power line drivers
designed to interface data terminal equipment
(DTE) with data circuit-terminating equipment
(DCE) in conformance with the specifications of
ANSI/EIA-232-D-1986.
The sleep-mode input, SM, can be used to switch
the outputs to high impedance, which avoids the
transmission of corrupted data during power up
and allows significant system power savings
during data-off periods.
3A
3B
4A
I>
2
V
4
&1>
V
5
9
&1>
10
V
I>
12
V
X
L
X
=
11
3Y
4Y
logic diagram (positive logic)
8M 13
2
lA--I---i
x>--
1Y
4
5
FUNCTION TABLE
A
8
2Y
and IEC Publication 617-12.
2A--I--r-~
INPUTS
6
1Y
t This symbol is in accordance with ANSVIEEE SId 91-1984
The SN65C198 is characterized for operation
from -4DoC to 85°C. The SN75C198 is
characterized for operation from DOC to 7DoC.
8M
H
H
H
3
2B--+-L-~
2Y
OUTPUT
B
9
Y
H
H
L
L
X
L
H
H
X
Z
3A--I--r-~
10
3B--+-L~
12
4A----I
=
3Y
4Y
H high level,
L low level,
X = irrelevant,
Z = high impedance
Copyright© 1993, Texas Instruments Incorporated
TEXAS . "
INSIRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2-£29
SN65C198, SN75C198
QUAD LOW-POWER LINE DRIVERS
SLLS051A- 03472, JULY 1990 - REVISED MARCH 1993
schematics of inputs and outputs
EQUIVALENT OF SLEEP MODE INPUT
EQUIVALENT OF A AND B INPUTS
Vee+--~------~~--------
Input A
Internal
1.4-V
Reference
toGND
SM
Input
InputB - (Drivers 2
and 3 Only)
Vee _
--+4H~---+----------<
__- Vec---~--~--~~---4~---
TYPICAL OF Y OUTPUTS
1600
....."""'I\rl.-'VV'IrlII~- Output
740
720
----------------<.---~~--------~-- Vee-
All resistor values shown are nominal.
TEXAS
..If
INSIRUMENTS
2-a30
POST OFFICE BOX 655303 • DAUAS, TEXAS 75265
Internal
1.4-V
Referenca
toGND
SN65C198, SN75C198
QUAD LOW-POWER LINE DRIVERS
SLlS051A- 03472, JULY 1990- REVISED MARCH 1993
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vcc+ (see Note 1) .......................................................... 15 V
Supply voltage, Vcc- .................................................................... -15 V
Input voltage range ............................................................... -15 V to 15 V
Output voltage range ................................................... Vcc- -6 V to Vcc + + 6 V
Continuous total power dissipation ..................................... See Dissipation Rating Table
Operating free-air temperature range: SN65C198 ..................................... -40°C to 85°C
SN75C198 ....................................... O°C to 70°C
Storage temperature range ....................................................... -65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds ............................... 260°C
NOTE 1: All voltages are with respect to the network ground terminal.
DISSIPATION RATING TABLE
TA,,25·C
POWER RATING
DERATING FACTOR
ABOVE TA = 25·C
D
950mW
7.6mW/"C
494mW
N
1150mW
9.2mW/"C
598mW
PACKAGE
TA=85·C
POWER RATING
recommended operating conditions
MIN
NOM
MAX
Supply voltage, VCC +
4.5
12
15
V
Supply voltage, VCC-
-4.5
-12
-15
V
VCC+
V
Input voltage, VI (see Figure 2)
VCC-+2
High-level input voltage, VIH
Low-level input voltage, VIL
V
2
IA and B inputs
0.8
I SM input
0.6
Operating free-air temperature, TA
I SN65Cl98
-40
85
I SN75Cl98
0
70
1ExAs
UNIT
V
·C
..If
INSIRUMENfS
POST OFFICE BOX 655303 • OAUAS. TEXAS 75265
2-831
SN65C198,SN75C198
QUAD LOW-POWER LINE DRIVERS
SLLS051A-D3472,JULY 1990-REVISED MARCH 1993
electrical characteristics over recommended operating free-air temperature range, Vee:l:
SM at 2 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
VCC,.=,.5V
4
VCC,.=,.12V
10
TYpt
=:1:12 V,
MAX
UNIT
V
VOH
High-level output voltage
VIH=0.8V,
RL=3kg
VOL
Low-level output voltage (see Note 2)
VIH=2V,
RL=3kg
IIH
High-level input current
VI =5V
10
IlL
Low-Ievellnput current
VI =OV
-10
IOZ
High-Impedance-state output current
SMatO.6V
VCC,.=,.5V
-4
VCC,.=,.12V
-10
VO=12V,
VCC,.=,.12V
100
VO=-12V,
VCC", .. ",12V
-100
V
iAA
iAA
iAA
IOS(H)
High-level short-circuit output current*
VI = 0.8 V,
VO=oorVCC_
-4.5
-10
-19.5
rnA
IOS(L)
Low-level short-cIrcuit output current*
VI=2V,
Vo=OorVcc+
4.5
10
19.5
ro
Output resiStance
Vcc", = 0,
Vo =-2Vto2V
rnA
g
ICC +
ICC-
300
A and B Inputs at 0.8 V or 2 V,
No load
VCC,.=",5V
90
160
VCC",=,.12V
95
160
A and B inputs at 0.8 V or 2 V,
SMatO.6V
RL=3kg,
VCC",=",5V
17
40
40
A and B inputs at 0.8 V or 2 V,
No load
VCC",=",5V
-90
-160
VCC,.=,.12V
-95
-160
A and B Inputs at 0.8 V or 2 V,
RL=3kg,
SM atO.6V
VCC,."",5V
-17
VCC",=",12V
-17
-40
-40
Supply current from VCC +
Supply current from VCC-
17
VCC,.=",12V
iAA
iAA
t All typical values are at TA = 25°C.
* Not more than one output should be shorted at a time.
NOTE 2: The algebraic convention, where the more positive (less negative) limit Is designated as maximum, Is used In this data sheet for logic
levels only, e.g., if -1 0 V Is a maximum, the typical value Is a more negative voltage.
switching characteristics over recommended operating free-alr temperature range, Vee:l: = :1:12 V
(unless otherwise noted)
PARAMETER
tpLH
TEST CONDITIONS
MIN
TYpt
Propagation delay time, Iow-to-high-Ievel output§
tpHL
Propagation delay time, high-to-Iow-Ievel outputS
MAX
3
RL=3kQto7kQ,
See Figure 1
CL=15 pF,
RL=3kgto7kg,
See Figure 2
CL=2500 pF,
RL=3kgto7kg,
See Figure 3
CL=15 pF,
CL= 15 pF,
CL=15 pF
ITLH
Transition time, low-to-high-level output'
trHL
Transition time, hlgh-tD-Iow-level output'
ITLH
Transition time, low-to-high-level output#
trHL
Transition time, high-tD-low-level output#
tpZH
Output enable time to high level
tPHZ
Output disable time from high level
tpZL
Output enable time to low level
tPLZ
SR
Output disable time from low level
RL=3kgt07kg,
See Figure 4
Output slew rate'
RL=3kgto7kg,
0.53
30
VI",
1
3.2
1
3.2
1.5
1.5
50
10
t All typical values are at TA = 25°C.
§ tPHL and tpLH include the additional time due to on-chip slew rate and are measured at the 50% points.
, Measured between 10% and 90% points of output waveform
• Measured between 3-V and -3-V points of output waveform
1ExAs'lf
INSTRUMENTS
POST OFFICE BOX _
10
'"
'"
'"'"
'"
'"'"
'"'"
3.5
0.53
• DAU.AS. TEXAS 75266
15
6
15
UNIT
'"
SN65C198, SN75C198
QUAD LOW·POWER LINE DRIVERS
SLlS051A- D3472, JULY 1990- REVISED MARCH 1993
PARAMETER MEASUREMENT INFORMATION
Input
Pulse
Generator
(see Note A)
0-.....- - - . - Output
T
CL
(see Note B)
TEST CIRCUIT
VOLTAGE WAVEFORMS
Figure 1. Test Circuit and VoHage Waveforms, Propagation and Transition Times
Input
Input~
Pulse
Generator
(see Note A)
-------
\
ov
Output
3V1\. -3V
II
output
RL
-=
T
CL
(see Note B)
trHL
TEST CIRCUIT
~
3V
-3V~
r---
--I ~
I+-
VOH
VOL
trLH
VOLTAGE WAVEFORMS
Figure 2. Test Circuit and VoHage Waveforms, Transition Times
Input
3V
Pulse
Generator
(see Note A)
In01.5V
I
T
CL
(see Note B)
tPZH
~
yvo~
Output
OV
I
1.5V\
Output
I
I
I
I
I
ov
0.5 V
~
~
tpHZ~
TEST CIRCUIT
VOH
Voff -OV
VOLTAGE WAVEFORMS
Figure 3. Driver Test ClrcuH and Voltage Waveforms
...-_ _ _.., Input
In01.5V
Pulse
Generator
(see Nate A)
tPZLJ-.
.. - ~I
3V
D--'--~J-
___~I
Output
T
CL
(see Note B)
Output
TEST CIRCUIT
I'
~;---
3V
OV
I
1011-...
..
~-tpLZ
\ ......_V_O_L_'_2_ _
-
~ V~.Oy
L~_.i'_ 0.5 V
-,-
VOL
VOLTAGE WAVEFORMS
Figure 4. Driver Test Circuit and Voltage Waveforms
The pulse generator has the following characteristics: Iw = 25 j.IS, PRR = 20 kHz, Zo = 50 C, tr = tf" 50 ns.
NOTES: A
B. CL includes probe and jig capacitance.
1ExAs
~
INSIRUMENTS
POST OFFICE BOX 655303 • OAUAS, TEXAS 75265
2-833
SN65C198,SN75C198
QUAD LOW·POWER LINE DRIVERS
SUS051A-D3472, JULY 1990-REVISED MARCH 1993
TYPICAL CHARACTERISTICS
OUTPUT CURRENT
vs
VOLTAGE TRANSFER CHARACTERISTICS
15
Vee", .. ",15V
12 -
Vce",=",12V
20
6 -
0
0
-3
t
-?
C
II
4
U
0
'S
Q.
'S
-9
RL=3kC
TA=25·e
I
9
Vee", = ",15V
-16
0.2 0.4 0.6 0.&
1
1.2 1.4 1.6 1.&
-20
2
~-
J
J
-&
-12
I
I
,-
. /
-4
Vee"," ",12V
-16
-12
.
C
§
U
~
0
-&
-4
i:
0
E
&
12
16
OUTPUT VOLTAGE
I
12
I
Vee", = ",12V
VOH (Vee", = '" 12 V, VI = 0.& V)
&
t-- r-- to-
>I
&
II
5
I
I
RL=3kC -
4 t--VOH (Vee",='" 5V, VI = 0.& V)
:::
~
0
'S
Q.
'S
0
0
I
-5
-10
r-
IOS(H)
VI=0.8V_ _
I--
-?
...
-4
r---VOL(Vec", =",5V, VI =2V)
-&
f.-oo-
VOL (Vee", ='" 12V, VI =2V)
Vo=oorVee_
-15
-40 -20
0
20
40
60
60
100
120
-12
-40
~
-20
TA - Free-Air Temperature - ·e
0
20
~
40
60
80
TA - Free-Air Temperature _·c
Figure 7
FigureS
t Only the O·C to 70·C portion of the curves applies to the SN75C198.
1ExAs ."
INSIRUMENTS
2-834
4
vs
.c
II)
I
0
Figure 6
:::I
!:!
U
V
-i.
FREE-AIR TEMPERATUREt
-
1
Vo - Output Voltage - V
'S
:t=
-"'-. L
FREE-AIR TEMPERATUREt
IOS(L)
VI=2V
Vo=OorVee+
1
1
vs
15
r-
~
VOH (VI = 0.& V)
SHORT-CIRCUIT OUTPUT CURRENT
10
~
J
.!,-kC Load Une
Figure 5
I
J
I
VI -Input Voltage - V
~
.l
VOL(VI=2V)
0
!Vee",=",9V
I !
-6
o
&
§
Vee",="'5V
I-
~
I
I
I
12
""
3
~
'S
,
-......
I
J
Vee", .. ",5V
.~
II
I
I
Vee"," ",12V
TA=25·e
16
......
9 -Vee",=",9V
>I
OUTPUT VOLTAGE
POST OFFICE BOX 655300 • DAUAS, TEXAS 75265
100
120
SN65C198, SN75C198
QUAD LOW-POWER LINE DRIVERS
SLLS051A-D3472. JULY 1990-REVISED MARCH 1993
TYPICAL CHARACTERISTICS
POWER-OFF OUTPUT RESISTANCE
INPUT CURRENT
120
100
I
C
,.~
0
'S
Q.
.5
60
vs
FREE-AIR TEMPERATUREt
FREE-AIR TEMPERATUREt
500
1\
r--
475
"' ....
c: 450
40
20
o
"'-- VO=2V
375
I
~
0
-
t:::;:::::;;;.
VO=-2V -....
Ii :
IIH (VI = S V)
I
=
I
I
Vee", = 0
Vee",=",12V
'\
80
~
vs
350
IlL (VI = 0)
-20
"
-40
-40
325
-20
0
20
40
60
eo
TA - Free-Air Temperature
100
300
120
-40
-20
-·e
0
20
Figure 9
120
vee"'i"'12y
I
eo
lee+
't
_n
.
~
RL= NoLoed
VI =0.8Vor2V
~
>-I
8:
40
!II:
ii'
o
iii
,jl
~
i
z
'tI.e
.~
!
Do
I
o
-40
I
II:
III
Ve~",="'sv
S~-1---+---+--~--4---+---~-1
-80 I- lee-
fI
8
120
FREE-AIR TEMPERATUREt
Vee",="'SV
o
100
-·e
vs
FREE-AIR TEMPERATUREt
I
eo
OUTPUT SLEW RATE
vs
~
60
Figure 10
SUPP.LY CURRENT
c(
40
TA - Free-Air Temperature
~ I-
-120
-40
-20
0
20
Vee",=",12V
40
60
O~~--~--~--~--~--~--~~
eo
TA - Free-Air Temperature
100
120
-40
-20
-·e
0
20
40
60
TA - Free-Air Temperature
Figure 11
80
100
120
-·e
Figure 12
t Only the D·C to 7D·C portion of the curves applies to the SN75C198.
1ExAs
~
INSJRUMENIS
POST OFFICE BOX 655303 • DAUAS. TEXAS 75265
2-835
SN65C198,SN75C198
,
QUAD LOW-POWER LINE DRIVERS
SUS051A- 03472, JULY 1990 - REVISED MARCH 1993
TYPICAL CHARACTERISTICS
PROPAGATION DELAY TIME
va
FREE-AIR TEMPERATUREt
FREE-AIR TEMPERATUREt
2
.
1.75
or-
_
OUTPUT TRANSITION TIME
va
2
!="" roo
tPHL_ t-- RL=3 kC
::i.
1
~
1.5
~
1.25
1=
I--
~
1.5
.-!111'
1
'ii
I
t - tpLH
0
.e
0.75
I
0.5
0.
.
::i.
c
c
'ill01
I
I
I
VCC.,=.,12V
1.75 f- RL =3 kC to 7 kC
RL=7 kC
II.
'a
..
0.
l
..
RL=3kC
..
i
1
1
-20
1
1
~z:
l
S
•E
..
0.5
0.25
0
20
40
60
80 100
TA - Free-Air Temperature _·C
o
120
20
va
FREE-AIR TEMPERATUREt
FREE-AIR TEMPERATUREt
0.8
---
1
1
0.6
r
0.5
0.4
5
0.3
..
120
VCC.,=.,12V
RL=3 kC
0.7 -CL",15pF
10
1
100
OUTPUT DISABLE TIME FROM HIGH LEVEL
w
i
80
va
15
o
60
Figure 14
1=
t
40
TA - Free-Alr Temperature - ·C
I
I
VCC.,=.,12V
RL=3 kC
25 -CL=15pF
.--
trLH
I
30
20
I-
~ trHL
i= 0.75
,I
I- RL=7kC
OUTPUT ENABLE TIME TO HIGH LEVEL
::i.
trL~
(
Figure 13
.
trH~-
."..,,;. = 2500 pF
CL=15pF
f----
0'
VCC.,=.,12V
CL=15pF
-40
1.25
c
..
0.25
o
-
•E
~,
......-......-
,..,... ...-
/
V
~
~
o
-40
-20
o
20
40
60
80
100
TA - Free-Air Temperature - ·C
120
0.2
-40
-20
Figure 15
Figure 16
t Only the O·C to 70·C portion of the curves applies to the SN75C198.
1ExAs
..If
INSIRUMENTS
2-a36
o 20 40 60 80 100
TA - Free-Air Temperature _·C
POST OFACE BOX 6155303 • OAUAS. TEXAS 75265
120
SN65C198, SN75C198
QUAD LOW-POWER LINE DRIVERS
SLLS051A-D3472, JULY 1990- REVISED MARCH 1993
TYPICAL CHARACTERISTICS
OUTPUT ENABLE TIME TO LOW LEVEL
8
"=-I
I
vs
FREE-AIR TEMPERATUREt
FREE-AIR TEMPERATUREt
I
"
'ii
VCC===12V
7 f-- RL=3 kg
CL=15pF
...J
6
~
!s
~
4
c
3
II
w
5
9::I
=-I
~
!
£
~
.
5
..
:a
j::
OUTPUT DISABLE TIME FROM LOW LEVEL
vs
2
-
1=
l
o
..~
I
I
~
..
o
-40
-20
0
20
40
60
80 100
TA - Free-Air Temperature _·C
120
I
VCC===12V
RL=3 kg
2.5 ~ CL=15pF
2
1.5
Ii3
0
I
3
0.5
-
-
o
-40
t--
-20
Figure 17
-
--
I-
0
20
40
60
80 100
TA - Free-Air Temperature - ·C
120
Figure 18
t Only the O·C to 70·C portion of the curves applies to the SN75C19B.
TEXAS . "
INSIRUMENTS
POST OFFICE BOX 655303 • OAUAS, TEXAS 75265
2-837
2-:838
SN75ALS199
QUAD DIFFERENTIAL LINE RECEIVER
WITH 3-STATE OUTPUTS
JANUARY 1989 - REVISED MARCH 1993
SLlS046B
•
•
•
•
•
•
•
•
Meets CCITT Recommendations V.10, V.11,
X.26, and X.27
-7 V to 7 V Common-Mode Input Voltage
Range With 300-mV Sensitivity
3-State TTL-Compatible Outputs
High Input Impedance ••• 12 kQ Min
Input Hysteresis ••• 120 mV lYP
Single S-V Supply Operation
Low Supply Current Requirement
35mAMax
Improved Speed and Power Consumption
Compared to MC3486
description
D OR N PACKAGE
(TOP VIEW)
1A
1Y
1,2EN
2A
28
GND
The SN75ALS199 features 3-state outputs that
permit direct connection to a bus-organized
system with a fail-safe design that ensures the
ouptuts will always be high if the inputs are open.
The device is optimized for balanced multipoint
bus transmission at rates up to 10 megabits per
second. The input features high input impedance,
input hysteresis for increased noise immunity, and
an input sensitivity of :t300 mVover a commonmode input voltage range of :t 7 V. It also features
an active-high enable function for each of two
receiver pairs. The SN75ALS199 is designed for
optimum performance when used with the
SN75ALS194 quadruple differential line driver.
The SN75ALS199 is characterized for operation
from O'C to 70·C.
Vee
48
4A
4Y
3,4EN
3Y
3A
38
logic symbol t
1,2EN
The SN75ALS199 is a monolithic quad line
receiver with 3-state outputs designed using
advanced low-power Schottky technology. This
technology provides combined improvements in
bar design, tooling production, and wafer
fabrication, providing significantly less power
consumption and permitting much higher data
throughput than other designs. The device meets
the specification of CCITT Recommendation
V.10, V.11, X.26 and X.27.
4
2Y
16
15
14
13
12
11
10
9
1A
18
2A
2B
3,4EN
3A
3B
4A
4B
4
2
3 1Y
1
6
5
7
12
10
9
14
]
11 3Y
v
13
15
4V
tThis symbol is in accordance with ANSVIEEE SId 91-1984
and IEC Publication 617-12.
logic diagram
1,2EN
.1A
18
2A
2B
>--+---,3~ 1Y
>-_---'5~ 2V
3,4EN
3A
38
4A
48
11
3Y
>-_ _.:.:13=- 4V
Copyright 1Cl1993, Texas Instruments Incorporated
POST OFFICE BOX 655303 • DAUAS. TEXAS 75265
24!39
SN75ALS199
QUAD DIFFERENTIAL LINE RECEIVER
WITH 3-STATE OUTPUTS
SUSD46B - D3204, JANUARY 1989 - REVISED MARCH 1993
FUNCTION TABLE
(each receiver)
DIFFERENTIAL INPUTS
A-B
EN
VIO,"0.3V
H
H
V < VIO < 0.3 V
H
?
~.3
V
Vlos~.3V
H
L
X
L
Z
H
H
Open
H
OUTPUT
=high level,
=
=
L low level,
X Irrelevant,
? = Indeterminate, Z = high Impedance (of\)
schematics of inputs and outputs
EQUIVALENT OF EACH A OR B INPUT
EQUIVALENT OF EACH ENABLE INPUT
VCC--------.-~~-
VCC
TYPICAL OF ALL OUTPUTS
----------~~-
VCC
soc
5kC
18kC
kO
--r
Input ......-Wlrll....
Output
Input
VCC(A)
or
GND (B)
~~*-l
150kO
2kC
50C
1ExAs
2-840
..If
INSIRUMENIS
POST OFFICE BOX 655303 • DAUAS. 1EXAS 75265
SN75ALS199
QUAD DIFFERENTIAL LINE RECEIVER
WITH 3-STATE OUTPUTS
SLlS046B - 03204. JANUARY 1989- REVISED MARCH 1993
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) ....................................................... " ... 7 V
Input voltage, A or B inputs, VI ............................................................ ±15 V
Differential input voltage (see Note 2) ....................................................... ±15 V
Enable input voltage ......................................................................... 7 V
Low-level output current ............................................... :.................. 50 rnA
Continuous total dissipation ........................................... See Dissipation Rating Table
Operating free-air temperature range .................................................. O·C to 70·C
Storage temperature range ....................................................... - 65·C to 150·C
Lead temperat~re 1,6 mm (1/16 inch) from case for 10 seconds ............................... 260·C
NOTES: 1. All voltage values. except differential input voltage. are with respect to network ground terminal.
2. Differential-input voltage is measured at the noninverting Input with respect to the corresponding inverting input.
DISSIPATION RAnNG TABLE
PACKAGE
TAs2SD C
POWER RATING
D
N
DERATING
FACTOR
TA=70D C
POWER RATING
950mW
7.6mW/"C
60SmW
1150mW
9.2mW/"C
736mW
recommended operating conditions
Supply voltage. VCC
MIN
NOM
MAX
UNIT
4.75
5
5.25
V
=7
V
=12
V
Common·mode input voltage. V'C
Differential input voHage. V,D
High-level input voltage, V,H
2
Low-level input voltage. V,L
V
O.S
High-level output current. IOH
Low-level output current. IOL
Operating free-air temperature. TA
0
V
-400
,..A
16
mA
70
DC
1ExAs ."
INSIRUMENTS
POST OFFICE BOX 655303 • OALlAS. TEXAS 75265
2-841
SN75ALS199
QUAD DIFFERENTIAL LINE RECEIVER
WITH 3-STATE OUTPUTS
SLLS046B - 03204. JANUARY 1989 - REVISED MARCH 1993
electrical characteristics over recommended ranges of common-mode input voltage, supply
voltage, and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Vr+
Vr-
PosHlve-golng threshold voltage
Vhvs
Hysteresis {vT+- VT...J
VIK
Enable-input clamp voltage
11=-18mA
VOH
High-level output voltage
VIO= SOOmV.
Negative-going threshold voltage
VOL
Low-level output voltage
10Z
Hlgh-impedance-state output current
II
Line input current
IIH
High-level enable-Input current
IlL
MIN
TYpt
UNIT
SOO
mV
mV
-300*
120
mV
-1.5
10H = - 400 IlA
VIO=-300mV
2.7
S.6
0.45
IOL=16mA
0.5
VIL= 0.8 V,
VIO=-3V,
VO=2.7V
20
VIL=0.8V,
VIO=SV.
VO=0.5V
-20
Other input at 0 V.
See Note S
VI = 15V
0.7
1.2
VI=-15V
-1
-1.7
20
VIH = 2.7V
100
-100
VIL=0.4V
Input resistance
lOS
Short-circuit output current§
VID=3V.
ICC
Supply current
Outputs disabled
VO=O
V
V
IOL=8mA
VIH =5.25V
LOW-level enable-input current
MAX
V
IlA
rnA
IlA
IlA
kQ
12
18
-15
-78
-ISO
rnA
22
35
rnA
t All typIcal values are at VCC = 5 V. TA = 25°C.
* The algebraic convention. in which the less positive limit is designated minimum. is used in this data sheet for threshold voltage levels only.
§ Not more than one output should be shorted at a time. and the duration of the short circuit should not exceed one second.
NOTE 3: Refer to CCITT Recommendations V.l 0 and V,11 for exact conditions.
switching characteristics, Vee = 5 V, TA = 25°C
PARAMETER
TEST CONDITIONS
tpLH
Propagation delay time. low-to-high-Ievel output
tpHL
Propagation delay time. high-to-Iow-Ievel output
tpZH
Output enable time to high level
tPZL
Output enable time to low level
tpHZ
Output disable time from high level
tpLZ
Output disabll! time from low level
VID=OVt03V.
See Figure 2
CL=15pF.
CL= 15 pF.
See Figure S
CL = 15pF.
See Figure 3
1ExAs
..If
INSIRUMENTS
2-842
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
MIN
TYP
MAX
15
22
15
22
13
25
11
25
13
25
15
22
UNIT
ns
ns
ns
SN75ALS199
QUAD DIFFERENTIAL LINE RECEIVER
WITH 3-STATE OUTPUTS
SLLS046B - 03204. JANUARY 1989 - REVISED MARCH 1993
PARAMETER MEASUREMENT INFORMATION
1[
2V - - - - - '
YOH
Rt~l
-
--
--
Figure 1. VOH. VOL Test Circuit
~~---::
In~d
50C
I
I
tpLH - .
1.SV
-+i
!4- tpHL
_ - -__ ~---VOH
Output
1.3V
2V--------'
TEST CIRCUIT
VOLTAGE WAVEFORMS
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR '" 1 MHz. duty cycle", 50%. Zo = 50 C.
tr",Sns.tf",Sns.
B. CL includes probe and Jig capacHance.
Figure 2. Test Circuit and Voltage Waveforms
TEXAS
,If
INSIRUMENTS
POST OFFICE BOX 655303 • DAUAS. TEXAS 75265
2-S43
SN75ALS199
QUAD DIFFERENTIAL LINE RECEIVER
WITH 3-STATE OUTPUTS
SLlS046B - 03204. JANUARY 1989 - REVISED MARCH 1993
PARAMETER MEASUREMENT INFORMATION
SWl
2.5V
Output
-2.5V---O
2kn
{see Note C)
Generator
{see Note A)
T
51 g
CL =15pF
(see Note B)
TEST CIRCUIT
tpZH
Input
SWl to 2.5 V
---1.5V SW20pen
I
SW3Closed
---....II'-t--- OV
tPZH ~ l+-
I
--~
Output
\
I
__
r---
~
Input
I
'-----'-r- ov
I
tpZL ~
j4-
1.5V
SWl to-2.5V
SW2Closed
SW30pen
I
VOH
~--4.5V
Output
/ - - 1.5V
---011~
tpZL
3V--_
3V
0V
--.I
"'C 1.5V
VOL
3V
3V
SWl to 2.5 V
SW2Closed
SW3Closed
SWl to-2.5V
SW2CI08ed
SW3Closed
t'4-
I
VOH
Output _____
J~5V
1.4V
VOLTAGE WAVEFORMS
NOTES: A. The Input pulse is supplied by a generator having the following characteristics: PRR .. 1 MHz. duty cycle .. 50%. Zo
tr .. 6 ns. tf" 6 ns.
B. CL includes probe and jig capac~ance.
C. All diodes are 1N3064 or equivalent.
Figure 3. Test Circuit and Voltage Waveforms
IExAs ~
INSIRUMENTS
200644
POST OFFICE BOX 655303 • DAUAS. TEXAS 75265
=50 O.
SN75ALS199
QUAD DIFFERENTIAL LINE RECEIVER
WITH 3-STATE OUTPUTS
SLLS0468 - 03204. JANUARY 1989- REVISED MARCH 1993
TYPICAL CHARACTERISTICS
OUTPUT VOLTAGE
vs
ENABLE VOLTAGE
5
>
I
4
3.5
~
'c.
!5
'!5
3
0
I
~
I
TA=70°C - r-.
TA = 25°C
TA=O°C
3.5
VCC=5.5V
>
VCC=5V
II
DI
4l!
vs
ENABLE VOLTAGE
4
VIO=300mV
VIC=o
RL=BketoGNO
TA = 25°C
4.5
OUTPUT VOLTAGE
I
3
II
DI
VCC=4.5V
4l!
~
'!c.5
'!5
2.5
2.5
2
0
2
I
1.5
~
1.5
VCC=5V
VIO=300mV
VIC=O
RL=B keto GNO
0.5
0.5
o
o
0.5
1.5
2
2.5
o
o
3
0.5
Enable Voltage - V
Figure 4
VCC=5V
VCC=4.5V
>
I
CD
!
vs
6
5
-
>
I
CD
4
!
~
'c.
!5
'!5
....--TA=O°C
4
~TA=25°C -
~
'c.
!5
'!5
3
0
,..--- TA = 70°C
3
0
I
~
3
ENABLE VOLTAGE
VIO =
mv i
VIC=o
RL=1 keto VCC
TA=25°C
5
2.5
OUTPUT VOLTAGE
~300
VCC=5.5V
2
Figure 5
OUTPUT VOLTAGE
vs
ENABLE VOLTAGE
6
1.5
Enable Voltage - V
I
2
~
2
VCC=5V
Vlc=-300mV
VIC=O
RL= 1 ketoVcc
o
o
0.5
1.5
2
2.5
3
o
o
Enable Voltage - V
0.5
1.5
2
2.5
3
Enable Voltage - V
Figure 6
Figure 7
1ExAs
.Jf
INSIRUMENIS
POST OFFICE SOX 655303 • DALLAS. TEXAS 75265
2-845
SN75ALS199
QUAD DIFFERENTIAL LINE RECEIVER
WITH 3·STATE OUTPUTS
SlJ.S046B - 03204. JANUARY 1989 - REVISED MARCH 1993
TYPICAL CHARACTERISTICS
OUTPUT VOLTAGE
HIGH-LEVEL OUTPUT VOLTAGE
vs
vs
DIFFERENTIAL INPUT VOLTAGE
FREE·AIR TEMPERATURE
5
>I
t
4
~
3
o
2
i
I
4
VCC=5V
VIC=-12Vto12V
10=0
TA=25·C
10H=0
>
~I
I
til
10H = - 400 J.tA
aI
i5
3
~
0
~T-
~
!
2
4:!
VT
g
J:
I
J:
~
o
-200
-1~
-100
-~
~
0
1~
100
VCC=5V
VID=300mV
VIC=O
o
200
w
o
~
Figure 8
til
at
i5
VS
3
~
2.5
at
5:
I
J:
........
i'.
........
i'-...
"~
2
1.5
~
-I
'"'" "'
'"
1
-
>I
til
o
o
4
~
3.5
~
3
~
2.5
. / VCC=5.5V
5
./ VCC=5V
0
('""'
.......
~
"- ~
VCC=4.5V
" "" "'\.
.'" ~ ~
g
J:
I
"
VCC=5V
VID=300mV VIC=O
4.5
at
!
...-..
~
2
1.5
~
V
~
./
I
I
I
I
- - -
,
"~
~
o
-10-~~~ -~-~ -60-70-~-9O-100
TA=O·C
TA=25·C
~~
K TA=ro·C
~
~ t\..
0.5
o
-10-~ -~ -~ -~
10H - High-level Output Current - mA
-60 -ro -~ -90-100
10H - High-Level Output Current - mA
Figure 10
Figure 11
ThxAs ."
INSIRUMENTS
2-846
~
V
J:
'\
0.5
~
HIGH-LEVEL OUTPUT VOLTAGE
5
3.5
ro
HIGH-LEVEL OUTPUT CURRENT
VID=300 mV
VIC=O
TA=25·C
4
~
HIGH-LEVEL OUTPUT CURRENT
4.5
~
0
Ii
~
vs
5
I
~
Figure 9
HIGH-LEVEL OUTPUT VOLTAGE
>
~
TA - Free-Air Temperature _·C
VID - Differential Input Voltage - mV
POST OFFICE BOX 655303 • DAUAS. TEXAS 75265
SN75ALS199
QUAD DIFFERENTIAL LINE RECEIVER
WITH 3-STATE OUTPUTS
SLLS046B - 03204. JANUARY 1989 - REVISED MARCH 1993
TYPICAL CHARACTERISTICS
LOW-LEVEL OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
0.4
>I
VCC=5V
V,O=-300mV
V,C=o
0.35
II
I
0.3
"!5
Q.
"!5
0.25
~
10=&mA
0
~
0.2
!
0.15
I
...I
~
0.1
10=0
r--
0.05
o
o
10
20
30
40
50
70
60
&0
TA - Free-Air Temperature _·C
Figure 12
LOW-LEVEL OUTPUT VOLTAGE
,
>I
vs
LOW-LEVEL OUTPUT CURRENT
LOW-LEVEL OUTPUT CURRENT
0.&
I J
VCC=4.5V
0.7 I - -
I
II
~
"!5
Q.
"!5
I
~
0.6 I - -
I
VCC=5.5V ........
0.4
0.3
I
~
0.2
,
~
~
~
~
~
o
>
V
I
CII
~
20
a;
0.4
1
0.3
~
I
40
ITA=~·C ~ J.
0.6
0.5
...I
30
0.7
~
"!5
Q.
"!5
I
~~
L. ~
0
V,O =-300 mV
V,C=O
TA=25·C
ro
I
TA=70·C ...
II
~
0.1
o
)
rA II/
I
0.5
...I
...I
['.I
0.&
}
J
VCC=5V ...
0
~
LOW-LEVEL OUTPUT VOLTAGE
vs
I
I
I
50
60
ro
10L - Low-Level Output Current - mA
~
~
V
0.2
0.1
o
"
o
t:::,
TA=O·C
I-' ~
VCC=5V
v,o=-300mV
V,C=O
10
20
30
40
I
I
I
50
60
ro
-
~
10L - Low-Level Output Current - mA
Figure 13
Figure 14
1ExAs ",
INSIRUMENTS
POST OFFICE BOX 655303 • DALlAS. TEXAS 75265
2~47
SN75ALS199
QUAD DIFFERENTIAL LINE RECEIVER
WITH3-STATE OUTPUTS
SLlS046B - 03204, JANUARY 1989 - REVISED MARCH 1993
TYPICAL CHARACTERISTICS
SUPPLY CURRENT
SUPPLY CURRENT
vs
vs
SUPPLY VOLTAGE
FREE-AIR TEMPERATURE
50
45 -
~
I
il:
~
(,)
i
40 -
30
VIO=-300mV
VIC=O
10=0
TA=25·C
35
30
OI88bled~
I
C
VI
i
~
Q.
Q.
~
5
o
o
(,)
.9
~
10
-
~
".
3.
-
VCC=4.5V
15
10
5 f- VIO=-300mV
Outputs Enabled
10=0
../
2
20
1/1
I
1/
15
VCC=5V
(,)
'Enabled
20
25
I
25
(,)
.9
~
//
~
1/1
I
I
VCC=5.5V
4
5
6
7
o
o
8
I
I
I
ro
20
30
va
vs
DIFFERENTIAL INPUT VOLTAGE
FREQUENCY
30
40
I
25
E
VCC=5V
20
VCC =4.5V
~
Q.
Q.
cC
I
(,)
~
35
VCC=5.5V
I
I
30
i
25
~
15
.
~
~
Q.
Q.
~
1/1
I
(,)
10
o
I
/
".
20
15
10
.
5
I
-100
o
100
200
o
10 k
100k
1M
f - Frequency - Hz
VIO - Oifferentiallnput Voltage - mV
Figure 17
Figure 18
1ExAs ",
2~48
00
.9
10=0
5 I- Outputs Enabled
VIC=O
TA=25"C
-200
'"''
VCC=5'';;'
VI = '" 1.5-V Square Wave
CL= 15pF
Four Channels Orlven
TA=25·C
(,)
1/1
I
.?
~
50
SUPPLY CURRENT
SUPPLY CURRENT
il:
50
Figure 16
Figure 15
~
40
TA - Free-Air Temperature - ·C
VCC - Supply Voltage - V
INSTRIJMENTS
POST OFFICE BOX 655303 • DAUAS, TEXAS 75265
10M
100M
SN75ALS199
QUAD DIFFERENTIAL LINE RECEIVER
WITH 3-STATE OUTPUTS
SLLS046B - 03204. JANUARY 1989 - REVISED MARCH 1993
TYPICAL CHARACTERISTICS
INPUT RESISTANCE
INPUT CURRENT
VS
vs
FREE-AIR TEMPERATURE
INPUT VOLTAGE TO GND
30
3
TA'=25·C
25
2
c::
.101
I
tl
20
'S
c.
.5
I
I
15
I
a
10
i
;
1
a:
1
-'--""
c
I
0
,.....,.. V
."..,..,
V
-"'"
V
-1
.::
-2
5
o
-3
o
10
20
30
40
50
50
TA - Free-Air Temperature -
70
eo
-20 -15 -10
·c
10
vs
FREE-AIR TEMPERATURE
SUPPLY VOLTAGE
18
I '\
I!!
tPHZ
tpLH-
14
12
~
10
or--
I:
T
I
. tpHL-
~
tPZL
CL=15pF
TA=25"C
16
i
--
f4
I
r-
~
tPHZ,
~V
..,
::;..--
I
tPLZ,
~
20
20
I
tpLH
CL-15pF
,tpZH
15
PROPAGATION DELAY TIME
VS
V~C=5V
-.-
5
Figure 20
SWITCHING CHARACTERISTICS
25
0
VI -Input Voltage to GND - V
Figure 19
30
-5
g
~HtV
:tPZtl
I
J.
5
4
2
o
o
W
20
30
40
50
50
70
eo
o
4.5 4.6 4.7 4.8 4.9
5 5.1
5.2 5.3 5.4
TA - Free-Air Temperature _·c
VCC - Supply Voltage - V
Figure 21
Figure 22
5.5
1ExAs ."
INSIRUMENTS
POST OFFICE BOX 855303 • DALlAS. TEXAS 75265
2-849
2-4350
SN75207, SN75207B
DUAL SENSE AMPLIFIER FOR MOS MEMORIES
OR DUAL HIGH·SENSITIVITY LINE RECEIVERS
• Plug·ln Replacement for SN75107A and
SN751 078 With Improved Characteristics
• :t10·mV Input Sensitivity
• TTL Compatible
• Standard Supply Voltages ••• :t5 V
• Differential Input Common·Mode Voltage
Range of :t3 V
• Strobe Inputs for Channel Selection
• Totem·Pole Outputs
• SN752078 Has Dlode·Protected Input Stage
for Power·Off Condition
• Sense Amplifier for MOS Memories
• Dual Comparator
• High·Sensltlvlty Line Receiver
D OR N PACKAGE
(TOP VIEW)
VCC+
VCC2A
28
NC
NC - No internal connection
description
The SN75207 and SN752078 are pin-for-pin replacements for the SN751 07A and SN751 078, respectively. The
improved input sensitivity makes them more suitable for MOS memory sense amplifiers and can result in faster
memory cycles. Improved sensitivity also makes them more useful in line receiver applications by allowing use
of longer transmission line lengths. The '207 and '2078 each features a TTL-compatible active-pullup output.
The essential difference between the SN75207 and SN752078 can be seen in the schematics. Input protection
diodes are in series with the collectors of the differential-input transistors of the SN752078. These diodes are
useful in certain party-line systems that may have multiple Vcc+ power supplies and may be operated with
some ofthe VCC+ supplies turned off. In such a system, if a supply is turned off and allowed to go to ground,
the equivalent input circuit connected to that supply would be as follows:
Input
~I
Input
SN75207
SN75207B
This would be a problem in specific systems that might have the transmission lines biased to some potential
greater than 1.4 V.
These devices are characterized for operation from O°C to 70°C.
FUNCTION TABLE
DIFFERENTIAL INPUTS
A-B
STROBES
G
X
X
VIO",10mV
-10 mV I
..
2
aI
!
~
"c
e'"
cg
0
-1
~ -2
I
~a.
-3
.5 -4
-4 -3 -2 -1 0
2
3
Inputs - B-to-Ground Voltage - V
1ExAs
-If
INSIRUMENTS
2-854
POST OFFICE BOX 665303 • DAUAS, TEXAS 75265
SN75207, SN75207B
DUAL SENSE AMPLIFIER FOR MOS MEMORIES
OR DUAL HIGH-SENSITIVITY LINE RECEIVERS
SLl.S069A- 01314, JULY 1973- REVISED JANUARY 1993
electrical characteristics over recommended free-air temperature range (unless otherwise noted)
PARAMETER
TVPT
MAX
VID=5V
30
75
VIO=-5V
30
75
TEST CONDITIONS
IIH
'207
High-level input current
1'207B
Vee", = '" 5.25 V
IlL
Low-level input current
'207
1'2076
Vee", = '" 5.25 V
IIH
High-level Input current
into 1G or 2G
VCC", = '" 5.25 V,
VCC", = ± 5.25 V,
IlL
Low-level input current
into 1Gor 2G
VCC± = '" 5.25 V,
VCC± = ± 5.25 V,
VCC± = ± 5.25 V,
VIH(S) = '" 5.25 V
MIN
VIO=-5V
-10
VIO=5V
-10
40
VIH(S) = 2.4 V
UNIT
IlA
IlA
IlA
1
rnA
VIL(S) = 0.4 V
-1.6
rnA
VIH(S) = 2.4 V
80
IlA
2
rnA
-3.2
rnA
VIH(S}= '" 5.25 V
IIH
High-level input current into S
IlL
Low-level input current into S
VCC", = ± 5.25 V,
VIL(S) = 0.4 V
VOH
High-level output voltage
VCC", = ± 4.75 V,
IOH = -400 1lA,
VIL(S) = 0.8 V,
VIC=-3Vto3V
VIOH= 10mV,
VOL
Low-level output voltage
VCC.. = ± 4.75 V
IOL=16mA,
VIH(S) =2V,
VIC=-3Vto3V
VIOL=-10mV,
10H
High-level output current
VCC", = '" 4.75 V,
VOH = ±5.25 V
lOS
Short-cIrcuit output current*
VCC.. = '" 5.25 V
ICCH+
Supply current from VCC +,
outputs high
VCC.. = ± 5.25 V,
TA=25°C
ICCH-
Supply current from VCC-,
outputs high
VCC.. = .. 5.25 V,
TA = 25°C
V
2.4
0.4
V
400
IlA
-70
rnA
18
30
rnA
-8.4
-15
rnA
MIN
MAX
UNIT
-18
t All typical values are at VCC+ = 5 V, VCC- = -5 V, TA = 25°C.
* Not more than one output should be shorted at a time.
switching characteristics, VCC+
=5 V, VCC- =-5 V, TA =25°C
TEST
CONDITIONS
PARAMETER
tpLH(O)
Propagation delay time, low-to-high level output, from differential inputs A and B
tPHL(O)
Propagation delay time, high-to-Iow level output, from differential inputs A and B
tpLH(S)
Propagation delay time, low-to-high level output, from strobe input G or S
IPHLISI
Propagation delay lime, high-Io-Iow level oulput, from strobe input G or S
1ExAs
RL=470 C,
CL=50 pF,
See Figure 1
35
ns
20
ns
17
ns
17
ns
,If
INSIRUMENTS
POST OFFICE BOX 655:lO3 • DALU\S, TEXAS 75265
2-a55
SN75207, SN75207B
DUAL SENSE AMPLIFIER FOR MOS MEMORIES
OR DUAL HIGH-SENSITIVITY LINE RECEIVERS
Su..s069A- 01314. JULY 1973- REVISED JANUARY 1993
PARAMETER MEASUREMENT INFORMATION
VCC-
Differential
r------L ------.,I
Input
1A
1'0----.....:=.....
, --I
Pulse
Genenrtor
Output
11Y
~--.
50pF
(see Note A)
(see Note C)
-=- (see Note D)
4700
TEST CIRCUIT
~------------ 40mV
B
10mV
10mV
I
OV
I
~tw1--1
II
3V
I
GorS
tpHL(D)~
VOH
y
tw2
I
~I
---I
I
I
1.SV
I-tPLH(D)
I
I
I
I
I
I
tPLH(S)
--I
3V
1.SV
tpHL(S)
~--I
--I
OV
...f=- - VOH
I
VOL
VOLTAGE WAVEFORMS
NOTES: A. The pulse generators have the following characteristics: Zo = 50 C. tr s; 5 ns. If s; 5 ns.lw1 = 500 ns with PRR = 1 MHz.lw2 = 1 JIS
with PRR 500 kHz.
B. Strobe input pulse Is applied to Strobe 1G when inputs 1A-1B are being tested. to Strobe S when inputs 1A-1B or 2A-2B are being
tested. and to Strobe 2G when Inputs 2A-2B are being tested.
C. CL Includes probe and jig capacitance.
D. All diodes are 1N916.
=
Figure 1. Test Circuit and Voltage Waveforms
1ExAs ."
2-856
INSIRUMENTS
POST OFFICE BOX 655303 • DAUAS. TEXAS 75265
SN75207, SN75207B
DUAL SENSE AMPLIFIER FOR MOS MEMORIES
OR DUAL HIGH·SENSITIVITY LINE RECEIVERS
SLlS069A- 01314, JULY 1973 - REVISED JANUARY 1993
APPLICATION INFORMATION
Strobes
,...---- - -----1
100Q
Input
From
TTL
SN75361 A
or
SN75452B
MOSMemory
I
I
r-------~--~I--i'
To ~~~~~I
~
I -q/
Dummy
Line
100 Q
Vref
Adjustment
Drive
I
I
I
Output
to TTL
II
I
I
I
1/2 '207 or '207B
I
I
I
IL__________ .JI
~~------~V~-------JI
Memory
Sense
Figure 2. Mos Memory Sense Amplifier
Receiver 4
Receiver 2
y
y
Strobes
Driver 1
Strobes
Transmission Une Having
Characteristics Impedance Zo
Location 2
Driver 3
Strobes
RT
-=
Driver 4
Datalnput A
B---t.._
Inhibit C
D---t.._
Location 1
Location 3
Location 4
Receivers are '207 or '207B; drivers are SN55109A, SN75109A, SN55110A, SN75110A, or SN75112.
Figure 3. Data-Bus or Parity-Line System
PRECAUTIONS: When only one receiver in a package is being used, at least one of the differential inputs of the
unused receiver should be terminated at some voltage between -3 V and 3 V, preferably at GND. Failure to do so
will cause improper operation of the unit being used because of common bias circuitry for the current sources ofthe
two receivers. Strobe G of the unused channel should be grounded.
TEXAS
,If
INSIR.UMENTS
POST OFFICE BOX 655303 • DAUAS, TEXAS 75265
2-857
2~58
SN75LBC241
LOW-POWER LinBiCMOS™ MULTIPLE DRIVERS AND RECEIVERS
SLLS137C-
•
•
Operates With Single 5-V Power Supply
•
Improved Performance Replacement for
MAX241
•
ESD Protection on EIA/TIA-232 Pins
Exceeds 6 kV ESD Per MIL-STD-883C,
Method 3015
MAY 1992 - REVISED APRIL 1993
ow PACKAGE
(TOP VIEW)
Meets EIA/TIA-232-E, 1991 Specifications
(Revision of EIA-232-D and CCITT V.28)
TOUT3
TOUT1
TOUT4
RIN3
ROUT3
SHUTDOWN
EN
•
Operates at Data Rates Up to 100 kb/s Over
a 3-Meter Cable
•
•
•
•
Low Power Shutdown Mode: s1
±30-V Input Levels
•
3-State TTUCMOS Receiver Outputs
•
•
±9-V Output Swing With a 5-V Supply
!!A Typ
RIN4
ROUT4
TIN4
TIN3
ROUT5
RIN5
TIN1
ROUT1
RIN1
GND
Vcc
LinBICMOS™ Process Technology
4 Drivers and 5 Receivers
11
C1+
Vss
Voo
C2C2+
C1-
Applications
EIA-232 Interface
Battery-Powered Systems
Terminals
Modems
Computers
description
The SN75LBC241 t is a low-power LinBiCMOS™ line interface device containing four independent drivers and
five receivers. It is designed to provide a plug-in replacement for the Maxim MAX241 with improved ESD
protection and other key performance specifications. The SN75LBC241 provides a capacitive Charge-pump
voltage generator to produce EINTIA-232 voltage levels from a 5-V supply. The charge-pump oscillator
frequency is 20 kHz. Each receiver converts EIAITIA-232 inputs to 5-VTTL/CMOS levels. The receivers have
a typical threshold of 1.2 V and a typical hysteresis of 0.5 V, and can accept ±30-V inputs. Each driver converts
TIL/CMOS input levels into EIA/TIA-232 levels.
"-
The SN75LBC241 includes a receiver 3-state control line and a low-power shutdown control line. Whenever,
the EN line is high, the receiver outputs are placed in a high-impedance state. When EN is low, normal operation
is enabled.
The shutdown mode reduces power dissipation to less than 51lW typical. In this mode, receiver outputs are high
impedance, driver outputs are turned off, and the charge-pump circuit is turned off. When the SHUTDOWN line
is high, the shutdown mode is enabled. When the SHUTDOWN line is low, normal operation is enabled.
This device has been designed to conform to standard EIA/TIA-232-E, 1991 and CCITI V.28 specifications.
The SN75LBC241 has been designed using LinBiCMOS™ technology and cells contained in the Texas
Instruments LinASIC™ library. Use of LinBiCMOS™ circuitry increases latch-up immunity in this device over an
all-CMOS design. The SN75LBC241 is characterized for operation from O°C to 70°C.
t Patent pending
LinBiCMOS and UnASIC are trademarks of Texas Instruments Incorporated.
Copyright © 1993, Texas Instruments Incorporated
1ExAs ."
INSIRUMENfS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2-859
SN75LBC241
LOW-POWER LinBiCMOS™ MULTIPLE DRIVERS AND RECEIVERS
SLLS137C - 04027, MAY 1992 - REVISED APRIL 1993
logic symbol t
logic diagram (positive logic)
vcc
EN
RIN1
11
SHUTDOWN
25
EN2
DRV/RCV
ROUT1
TOUT1
TIN1
EN
C1+
RIN2
C1C2+
ROUT2
TOUT2
TIN2
C2RIN1
RIN3
ROUT3
RIN2
TOUT3
RIN3
TIN3
RIN4
RIN5
RIN4
ROUT4
TOUT1
TOUT2
TOUT4
TIN4
TOUT3
TOUT4
RIN5
ROUT5
10
GND
t This symbol is In accordance with ANSI/IEEE Std. 91-1,984 and IEC Publication 617-12.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Input supply voltage range, Vee (see Note 1) .......................................... -0.3 V to 6 V
Positive output supply voltage range, Voo ...................................... Vee - 0.3 V to 15 V
Negative output supply voltage range, VSS .......................................... 0.3 V to -15 V
Input voltage range: Driver ................................................ .-0.3 V to Vee + 0.3 V
Receiver ............................................................. ± 30 V
Output voltage range: TOUT ........................................... Vss - 0.3 V to Voo + 0.3 V
ROUT ................................................ -0.3 V to Vee + 0.3 V
Short-circuit duration: TOUT ............................................................ unlimited
Continuous total dissipation ........................................... See Dissipation Rating Table
Operating free-air temperature range, TA .............................................. O°C to 70°C
Storage temperature range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds ............................... 260°C
NOTE 1: All voltage values are w~h respect to the network ground terminal.
DISSIPATION RATING TABLE
PACKAGE
TA s 25·C
POWER RATING
OPERATING FACTOR
ABOVE TA = 25·C
TA = 70·C
POWER RATING
ow
1348 mW
10.8 mwrc
863 mW
1ExAs . "
INSIRUMENTS
2-a60
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
SN75LBC241
LOW-POWER UnBiCMOS™ MULTIPLE DRIVERS AND RECEIVERS
SUS137C-D4027, MAY 1992-REVISEDAPRll1993
recommended operating conditions
Supply voltage, VCC
EN, SHUTDOWN
Low-level Input voltage, VIL
NOM
MAX
4.5
5
5.5
2
TIN
High-level input voHage, VIH
MIN
TIN, EN, SHUTDOWN
External charge-pump capacnor
External charge-pump capacnor voHage rating
V
V
2.4
0.8
Cl, C2 (see Figure 1)
UNIT
V
1
C3, C4 (see Figure 1)
1
Cl, C3 (see Figure 1)
6.3
C2, C4 (see Figure 1)
16
""
V
Receiver input voHage, RIN
Operating free-air temperature, TA
0
",30
V
70
°c
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature range (unless otherwise noted)
PARAMETER
VOH
High-level output voHage
VOL
Low-level output voHage
Vr+
VrVhys
Input hysteresis
I"j
TEST CONDITIONS
TOUT
RL= 3 kOto GND,
ROUT
10H=-1 rnA
See Note 2
MIN
TYpt
5
9
-9:1:
RL= 3 kOto GND,
ROUT
10L = 3.2 rnA
Receiver positive-going input threshold voHage
RIN
VCC =5V,
TA = 25°C
Receiver negative-going Input threshold voHage
RIN
VCC =5V,
TA=25°C
RIN
VCC=5V
Receiver input resistance
RIN
VCC =5V,
TA=25°C
3
ro
Output resistance
TOUT
VDD =VSS =VCC =0,
VO=",2V
300
lOS
Short circun output current§
TOUT
VCC = 5.5 V,
VO=O
liS
Short circuH input current
TIN
VI=O
ICC
Supply current
=
See Note 3
UNIT
V
3.5
TOUT
CVr + - Vr -l
MAX
-5
V
0.4
VCC = 5.5 V,
All output open
TA = 25°C,
All outputs open,
Shutdown pin high
TA
=25°C,
1.7
0.8
2.4
1.2
V
V
0.5
1
V
5
7
kg
g
",10
rnA
200
j.tA
4
8
rnA
1
10
j.rA
=
t All typical values are at VCC 5 V, TA 25°C.
:I: The algebraic convention, In which the least posHive (most negative) value Is designated minimum, Is used in this data sheet for logic vottage
levels only.
§ Not more than one output should be shorted at one time.
NOTES: 2. TotaiiOH drawn from TOUT1, TOUT2, TOUT3, TOUT4 and VDD pins should not exceed 12 rnA.
3. TotalloL drawn from TOUT1, TOUT2, TOUT3, TOUT4 and VSS pins should not exceed -12 rnA.
switching characteristics, Vee = 5 V, TA = 25°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tpLHIRl
Receiver propagation delay time, low-to-hlgh-Ievel output
See Figure 2
500
tpHLIRl
Receiver propagation delay time, hlgh-to-Iow-Ievel output
See Figure 2
500
ns
ns
tpZH
Receiver output enable time to high level
See Figure 5
100
ns
tpZL
Receiver output enable time to low level
See Figure 5
100
ns
tpHZ
Receiver output disable time from high level
See Figure 5
50
ns
tpLZ
Receiver output disable time from low level
See Figure 5
50
SR
Driver slew rate
RL=3kgt07kO,
See Figure 4
SR(tr)
Driver transition region slew rate
CL = 2500 pF,
See Figure 4
1ExAs
ns
30
4
6
V/IJS
VlIJS
~
INSIRUMENTS
POST OFFICE BOX 655303 • DAUAS, TEXAS 75265
2-861
SN75LBC241
LOW-POWER LinBiCMOS™ MULTIPLE DRIVERS AND RECEIVERS
SlJ..S137C-D4027, MAY 1992-REVISEDAPRIL 1993
APPLICATION INFORMATION
5-Vlnput
11
C1
11'F
6.3 V
12
C1+
VCC
13
5-Vto 10-V
C1- Voltage Doubler
C3
1..,.
+ 6,3V
VDD
15
C2+
C2
11'F
16V
C2-
5-Vto10-V
Voltage Inverter
17
VSS
C4
1..,.
T+ 16V
VCC
TlN1
TlN2
7
2
6
3
TOUT1
TOUT2
EIAITIA-232
Outputs
TTL/CMOS
Inputs
TIN3
TlN4
ROUT1
20
TOUT3
21
28
9
8
TOUT4
RIN1
5kQ
ROUT2
5
4
RIN2
5kQ
TTL/CMOS
Outputs
ROUT3
27
26
RIN3
EIA/TIA-232
Inputs
5kQ
ROUT4
22
23
RIN4
5kQ
ROUT5
19
18
5kQ
EN
25
'::'
GND
10
'::'
Figure 1. Typical Operating Circuit
1ExAs
~
INSIRUMENTS
2-862
POST OFFICE BOX 655303 • DALlAS, TEXAS 75265
RIN5
SHUTDOWN
SN75LBC241
LOW-POWER LinBiCMOS™ MULTIPLE DRIVERS AND RECEIVERS
SL1.S137C- 04027, MAY 1992- REVISED APRIL 1993
PARAMETER MEASUREMENT INFORMATION
"10ns~
ir-
VCC
I
~
I
Input
I
I
~ ,,10ns
50%
~+90%---
3V
10%
OV
50%
10%
Generator t-_R_IN-I1lI
(see Note A)
;,o--'---I4HH~~__f---,
T
I+-I
~
tpHL
(see Note C)
CL=50pF
(see Note B)
500 ns
~I
I
Output
-+I
I
;+-+tI
1.5X
TEST CIRCUIT
tpLH
1.5VL :::
VOLTAGE WAVEFORMS
Figure 2. Receiver Test Circuit and Waveforms for tpHL and tpLH Measurement
,,10ns
Input
---..LJ......
--'1-r
%I
~
I
Generator t---_T_IN_I
(sesNotsA)
EIA/TlA-232
Output
50%
I
10%
1+--51ll1~1
tpHL--;....:
CL=10pF
(sse Note B)
T
~+90%---
50%
10%
I
I
~ ,,10ns
ITHL
~
I
~ 14-
-+\
~
Output
3V
OV
tpLH
I+- ITLH
~:::
VOLTAGE WAVEFORMS
TEST CIRCUIT
Figure 3. Driver Test Circuit and Waveforms for tpHL and tpLH Measurement (5-I-lS Input)
,,10ns
---..LJ......
'I r
90%i
Generator
(see Note A)
Input
EIA/TIA-232
Output
I
I
~ ,,10ns
l+9O%--~
J.
~1.5V
1.5V
10%
3V
OV
~20IllI-.I
-+I J+-
ITHL
Output
3V'\
~
-3V'k
-1 i
Jrav-
tTLH
¥-=~.L_
VOH
VOL
TEST CIRCUIT
6V
SR =--:::=-==-::::--:-:ITHL orlTLH
VOLTAGE WAVEFORMS
Figure 4. Test Circuit and Waveforms for tTHL and tTLH Measurement (20-l-ls Input)
NOTES: A. The pulse generator has the following characteristics: Zo = 50
B. CL includes probe and jig capacHance.
C. All diodes are 1N3064 or equivalent.
Q,
TEXAS
duty cycle" 50%.
~
INSIRUMENTS
POST OFFICE BOX 655303 • DALlAS, TEXAS 75265
2-863
SN75LBC241
LOW-POWER LinBiCMOS™ MULTIPLE DRIVERS AND RECEIVERS
SLLS137C - 04027, MAY 1992 - REVISED APRIL 1993
PARAMETER MEASUREMENT INFORMATION
---
3V
OV
~
ROUT
CL=150pF
' - - tPZL or tpZH
I
---.:::~
0.8 V
~
~f----3V
*-
---..,J~
~;;;;,,,::
VOH-0.1V
2.5 V
- - - - - " r T VOL + 0.1 V
Figure 5. Receiver Output Enable and Disable Timing
TEXAS
2-864
,If
INSIRUMENTS
POST OFFICE BOX 655303 • DAUAS, TEXAS 75265
SN75LBC976
9-CHANNEL DIFFERENTIAL TRANSCEIVER
FEBRUARY 1993
Su.s133B
•
DLPACKAGE
9 Differential Channels for the Data and
Control Paths of the Differential Small
Computer Systems Interface (SCSI) and
Intelligent Peripheral Interface (lPI-2)
•
Each Transceiver Meets EIA-RS-485 and
ISO 8482:1987(E) Standards
•
Packaged In Shrink Small-Outline Package
With 250m II Terminal Pitch
•
Designed to Operate at 10 MIllion Transfers
Per Second
•
Low Disabled Supply Current
1.4 mA Typical
•
Thermal Shutdown Protection
•
Power-Up/Power-Down Glitch Protection
•
•
(TOP VIEW)
GND
BSR
CRE
1A
1DE/RE
2A
2DE/RE
3A
3DE/RE
4A
4DE/RE
5
8
CDE2
CDE1
CDEO
9B+
9B8B+
8B7B+
7B6B+
6B-
Vec
Vec
Positive and Negative Output Current
Umlting
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Open-Circuit Fall-Safe Receiver Design
Vcc
Vcc
SA
SDE/RE
6A
6DE/RE
7A
7DEJRE
8A
8DE/RE
9A
9DE/RE
SB+
SB4B+
4B3B+
3B2B+
2B1B+
1B-
description
The SN75LBC976 is a nine-channel differential
transceiver based on the 75LBC176 UnASIC™
cell. Use of Texas Instruments' UnBiCMOS ... t
process technology allows the power reduction
necessary to
integrate nine differential
transceivers. On-Chip enabling logic makes this
device applicable for the data path (eight data bits
plus parity) and the control path (nine bits) for
both the Small Computer Systems Interface
(SCSI) and the Intelligent Peripheral Interface
(IPI-2) standard data interfaces. This part is ESO
Class 1 (A) and Class 2 (B) per MIL-STO-883,
Method 3015.
Pins 13 through 17 and 40 through 44
are connected together to the package
lead frame and signal ground.
The SN75LBC976 is packaged in a shrink small-outline package (OL) with improved thermal characteristics
using heat sink pins. This package is ideal for low-profile, space-restricted applications such as hard disk drives.
The switching speed and testing of the SN75LBC976 is sufficient to transfer data over the data bus at 10m iIIion
transfers per second. Each of the nine channels conforms to the requirements of the EIA-RS-485 and ISO
8482:1987(E) standards referenced by ANSI X3.129-1986 (I PI), ANSI X3.131-1986 (SCSI-1), and the proposed
SCSI-2 and SCSI-3 standards.
The SN75LBC976 is characterized for operation from O·C to 70·C.
t Patent pending
UnASIC and UnBiCMOS are trademarks of Texas Instruments Incorporated.
Copyright Ii:) 1993, Texas Instruments Incorporated
POST OFACE BOX 655303 • DAlLAS. TEXAS 75265
2-865
SN75LBC976
9-CHANNEL DIFFERENTIAL TRANSCEIVER
Su.sl33B - 04042. AUGUST 1992 - REVISED FEBRUARY 1993
logic diagram (positive logic)t
COEO~M~
____________________~
COE1 ~55=--______--,
BSR
--------------------- ......
1A ~4__~--~~--------__I___I_~_.--------------------~~
10EJRE 5
t-.....__if--->·30.,. 1B +
D---1-~!---=29",- 1 B-
r"\-_-'
I
2A ~--
-----
I
I
I
I
I
I
I
---------------------"l---.32 2B+
-
20EJR:!
~ ~---------------~~~I.:---------------_t=; :::
30EJRE
4A
40EJRE
.!LI.....__
~o ~---------------~~~I2.---------------J-!!
3B~4B+
________
__~~~I~ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ~ 4B-
COEO
COE2 .>!56!!.-_+--+-+---1_~
--------------------- .....
SA ~1~9~----;_~----__if__f__r_~._--------------------_.~
50EJRE
-""'--t-----++----__it-t-I-I----L.~
I
SA ~--
60~;
70~
----
D---1-~!---=:r7,,- 5B-
".•..1:)-----'
I
I
I
I
I
I
I
---------------------~ 6B+
-
=~--------~------~~~1.:---------------1
:
9A 27
:: ~::
~------------------.:~~n~~------------------1 ~ ~::
BOEJRE ~__
BSR
____
BSR
__~~~I.:
"'-__
CAE
_______________
COEO
t For additional logic diagrams. see Application Information.
2--666
f__....__if--->3B.,. 5B +
INSIRUMENTS
1ExAs ""
POST OFFICE BOX 655303 • DAUAS. TEXAS 75265
~ BB-
53 9B +
D--I-__-..:S=2 9B-
SN75LBC976
9·CHANNEL DIFFERENTIAL TRANSCEIVER
SLLS133B - 04042, AUGUST 1992 - REVISED FEBRUARY 1993
schematics of inputs and outputs
ALL INPUTS EXCEPT CDEO, CDE1, AND CDE2
INPUTS CDEO, CDE1, AND CDE2
VCC
Input
- - VCC
Input -
___....-'V'I/Ir......_.....- .
B+ AND B-I/O PORTS
RECEIVER OUTPUT
100kO
B+Only
3kO
1B ko
Receiver
Driver
100kO
B-Only
12kO
1 kO
B+orB-
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage range, Vee (see Note 1) ............................................. -0.3 V to 7 V
Bus voltage range ................................................................ -10 V to 15 V
Data I/O and control (A-side) voltage range ........................................... -0.3 V to 7 V
Continuous power dissipation .......................... . . . . . . . . . . . . . . . . . . . . . . . . .. internally limited
Operating free-air temperature range .................................................. O°C to 70°C
Storage temperature range ....................................................... -65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds ............................... 260°C
t Stresses beyond those listed under 'absolute maximum ratings' may cause permanent damage to the device. These are stress ratings only. and
functional operation of the device at these or any other conditions beyond those indicated under 'recommended operating condHions' is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values and with respect to the GND terminal.
1ExAs
~
INSIRUMENIS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
2-£67
SN75LBC976
9-CHANNEL DIFFERENTIAL TRANSCEIVER
Su.s133B - 04042, AUGUST 1992 - REVISED FEBRUARY 1993
recommended operating conditions
Supply voltage, VCC
Voltage at any bus terminal (separately or common-mode), VO, VI, or VIC
MIN
NOM
MAX
UNIT
4.75
5
5.25
V
12
B+ orB-
High-level input voltage, VIH
All except B+ and B-
Low-level input voltage, VIL
All except B+ and B-
-7
2
V
0.8
V
-60
mA
A
-8
mA
B+ or B-
60
mA
8
mA
70
°c
B+ or B-
High-level output current, 10H
Low-level output current, 10L
A
Operating free-air temperature, TA
0
device electrical characteristics over recommended ranges of operating conditions
PARAMETER
TEST CONDITIONS
MIN TYpt
IIH
High-level input current
IlL
Low-level input current
ICC
Co
Cpd
Supply current
BSR, A, DE/RE, and CRE
CDEO, CDE1, and CDE2
BSR, A, DE/RE, and CRE
V
VIH=5V
UNIT
50
IlA
IlA
JAA
JAA
100
See Figure 3
-200
VIL=OV
CDEO, CDE1, and CDE2
MAX
-100
-50
All drivers and receivers
disabled
BSR and CDEO at 5 V.
Other inputs at 0 V
1.4
3
mA
All receivers enabled
No load,
VID=5V,
All other inputs at 0 V
29
45
mA
All drivers enabled
BSRatOV,
No load,
All other Inputs at 5 V
4.8
10
mA
Bus port capacitance
Power dissipation capacltance*
B+orBOne driver
One receiver
16
pF
460
pF
50
pF
t All typical values are at VCC = 5 V, TA = 25°C.
:I: Cpd determines the no-load dynamic current consumption, IS = Cpd VCC f + ICC.
driver electrical characteristics over recommended ranges of operating conditions (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
IVODI
Differential output voltage
Vtest=-7Vto 12V,
lOS
Output short-circuit current
See Figure 1
IOZ
High-impedance state output current
TYP
1
2
See receiver input current
1ExAs " ,
INSIRUMENIS
2-868
MIN
See Figure 2
POST OFFICE BOX 655303 • DAu.AS, TEXAS 75265
MAX
UNIT
",250
mA
V
SN75LBC976
9-CHANNEL DIFFERENTIAL TRANSCEIVER
SUSl33B - 04042, AUGUST 1992 - REVISED FEBRUARY 1993
receiver electrical characteristics over recommended ranges of operating conditions (unless
otherwise noted)
PARAMETER
TEST CONDmONS
High-level output voltage
VIO = 200 mV,
See Figure 3
IOH=-8mA,
VOL
Low-level output voltage
VIO = -200 mV,
See Figure 3
IOL=8mA,
Vr+
VrVhys
Positive-going threshold voltage
IOH=-8mA,
See Figure 3
Negative-going threshold voltage
IOL=8mA,
See Figure 3
VOH
II
IOZ
MIN
TYPT
MAX
2.S
V
0.8
V
0.2
V
-0.2
Receiver input hysteresis (\IT + - Vr..J
V
rnV
45
Receiver input current, B+ and B-
High-impedance-state output current
UNIT
VI = 12V,
Other input at 0 V,
VCC=Sv,
See Figure 3
0.7
1
rnA
VI=12V,
Other input at 0 V,
VCC=Ov,
See Figure 3
0.8
1
rnA
VI=-7V,
Other input at 0 V,
VCC=Sv,
See Figure 3
-0.5
-0.8
rnA
VI =-7V,
Other input at 0 V,
VCC=Ov,
See Figure 3
-0.4
-0.8
mA
See Figure 3
IVO=GNO
-100
JVO=VCC
SO
IlA
driver switching characteristics over recommended operating conditions (see Figure 4) (unless
otherwise noted)
PARAMETER
Ic:to
'skOim)
TEST CONDITIONS
Oifferential delay time, high-to-Iow-Jevel output (lc:toH> or
low·to-high-Ievel output (lc:tou
Skew limit, the maximum difference in propagation delay times
between any two drivers on any two devices
'skIp)
Pulse skew (lIc:tOL - tdOH Il
tt
Transistion time (tr or ItI
MIN
TYpt
MAX
7.6
19.6
VCC=Sv,
TA=2S"C
9.1
17.1
VCC = Sv,
TA=70"C
11.S
19.5
VCC=sv,
See Note 2
12
8
0
10
6
UNIT
lIS
ns
ns
ns
t Ali typical values are at VCC = 5 V, TA = 2S"C.
NOTE 2: This specification applies 10 any S"C band within the operating temperature range.
1ExAs ."
INSIRUMENTS
POST OFFICE BOX B55303 • DAllAS, TEXAS 75265
2-869
SN75LBC976
9·CHANNEL DIFFERENTIAL TRANSCEIVER
SLLSl33B - 04042, AUGUST 1992 - REVISED FEBRUARY 1993
receiver switching characteristics over recommended operating conditions (see Figure 5) (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
Propagation delay time, high-to-Iow-Ievel output (tpLH) or
low-to-hlgh-Ievel output (tpHU
tpd
TYpt
MAX
33
VCC=5v,
TA = 25°C
22.6
31.6
VCC=5v,
TA = 70°C
23.4
32.4
VCC=5V,
See Note 2
12
Skew IimH, the maximum difference In propagation delay times
between any two drivers on any two devices
tsk~im)
MIN
21.5
9
tsk(p)
Pulse skew (\ tpHL - tpLHil
2
tl
TransHion time (tr or tf)
3
6
UNIT
ns
ns
ns
ns
t All typical values are at VCC = 5 V, TA = 25°C.
NOTE 2: This specification applies to any 5°C band within the operating temperature range.
transceiver switching characteristics over recommended operating conditions
MAX
UNIT
tenRX(L)
Enable time, transmH-to-receive to lOW-level output
TEST CONDITIONS
150
tenRX(H)
Enable time, transmit-to-receive to high-level output
150
80
ns
ns
ns
80
ns
PARAMETER
tenTX(L)
Enable time, receive-to-transmit to low-level output
tenTXIHI
Enable time, receive-to-transmit to high-level output
tsu
Setup time, CDEO, CDE1, CDE2, BSR, or CAE to active input(s) or output(s)
MIN
See Figure 6
150
ns
thermal characteristics
. PARAMETER
RaJA
Junction-to-free-air thermal resistance
ReJC
Junction-to-case thermal resistance
TEST CONDITIONS
Board mounted,
MIN
No airflow
PARAMETER MEASUREMENT INFORMATION
: : I V O D } n -IOH,
vo
I -IOLCDEO at 5 V,
VO~,
~ -lOS,
DElRE at 5 V,
or
or
BSR at 0 V
VOL
-=- -IOZ
Others Open
(see Note A)
r-"--....._-..,
1
NOTE A: For the 10Z test, the BSR input is at 5 V and all others are at 0
v.
Figure 1. Driver Test and Input Conditions
1ExAs ."
INSIR.UMENTS
2-870
POST OFFICE BOX·655303 • DAUAS, TEXAS 75265
TYP
MAX
UNIT
50
°C/W
12
°C/W
SN75LBC976
9-CHANNEL DIFFERENTIAL TRANSCEIVER
SLLS133B - 04042, AUGUST 1992 - REVISED FEBRUARY.1993
PARAMETER MEASUREMENT INFORMATION
Vtest
R1 =165Q
r - - -___~t------r-
o V or 3 V _ _ _..:.A.:...t
RL=7SQ
B+
VOD
~~L-~--~~----~BR2=165Q
Vtest
Figure 2. Driver Voe Test Circuit
COEO, COE1, CDE2,
CRE, and BSR st 0 V,
Others Open,
(see Note A)
A --r----,
or
VOL
1..
NOTE A: For the 10Z measurement, BSR is at 5 V and COEO, COE1, and COE2 are at 0
v.
Figure 3. Receiver Test Circuit and Input Conditions
1ExAs
~
INSIRUMENTS
POST OFFICE BOX 655303 • DALlAS, TEXAS 75265
2--871
SN75LBC976
9-CHANNEL DIFFERENTIAL TRANSCEIVER
SLLS133B - 04042, AUGUST 1992 - REVISED FEBRUARY'1993
PARAMETER MEASUREMENT INFORMATION
GNO
R1 =1650
r-----~~.------e------------~---B+
Input _ _ _-=:A'-J
Output
(see Note A)
L-----~~~----_+--------~---L---B-
R2=1650
T
5V
50pFt
TEST CIRCUIT
t Includes probe and jig capacitance.
..J,(----- ---~-- - - ---== ~.5
- - - - - - - - - 3V
Input _ _ _
I
Output
V
I
!+-1dOH -+i
i+-1dOL -+i
I
I
lr-~----~-t---i
1',.
_ _1;.;;0%~.(
tr
10%
I I
---+c J4-
tf
0
I I
---+c ..-
VOLTAGE WAVEFORMS
V. PAR of 1 MHz, 50% duty cycle, tr and tf < 6 ns, and Zo =50 O.
Figure 4. Driver Test Circuit and Voltage Waveforms
NOTE A: The input is provided by a pulse generator with an output of 0 to 3
TEXAS
~
INSIRUMENIS
2-872
POST OFFICE BOX 655303 • DAU.A!l, TEXAS 75265
SN75LBC976
9·CHANNEL DIFFERENTIAL TRANSCEIVER
SLLSl33B - 04042, AUGUST 1992 - REVISED FEBRUARY 1993
PARAMETER MEASUREMENT INFORMATION
COEO, COE1, COE2,
CRE, and BSR at 0 V,
All Others Open
Input
(see Note A) - - B +
1.5V-- B-
t
Includes probe and jig capacHance.
TEST CIRCUIT
--------3V
Input
i--------~-------- 1.5V
-----'. I
I
I·
I
I+- tpLH ~
---
I+- tpHL ~
I
Output
I
k---:1;';:;0%.;;:ifot
tt --.I
0
~~
!(~----~ 11
14-
---
1 0%--
tt --toI
VOH
~~~
~
VOLTAGE WAVEFORMS
NOTE A: The input is provided by a pulse generator with an outpul of 0 10 3 V. PRR of 1 MHz. 50% duty cycle, tr and If < 6 ns, and Zo = 50 Q.
Figure 5. Receiver Test Circuit and Voltage Waveforms
TEXAS ~
INSIRUMENfS
POST OFFICE BOX 655303 • DALlAS. TEXAS 75265
2-873
SN75LBC976
9·CHANNEL DIFFERENTIAL TRANSCEIVER
SUSl33B - D4042,AUGUST 1992 - REVISED FEBRUARY 1993
PARAMETI:R MEASUREMENT INFORMATION
o
3V
6
S3
74HC241
B+
A
B-
Input
DElRE
(see Note A) -~'---'-+--f
CDEOat 5V,
CDE1, CDE2, BSR,
end CRE at 0 V,
All Others Open
1.5
vii
\
----'.
:;:-5-;--------3V
I.
:
*- tenRX(L) ~
VA ...-_ _...,!~/r------
---
. . .\.. ----
1:.4--+l~1I
I
VOD _ _ _ _ _ _
0
1.4V
Sl toO
S2to5V
S3t03V
tenTX(H)
J1-,..----------\c----
0
}~5~--------:V
Input _ _l_.5_VJt
:
i4- fenRX(H) -.!
i\'1.______
---nl
VA
0-0
TEST CIRCUIT
t Includes probe and jig capacitance.
Input
S2
Ir-_-
....Jr-----1.4V
4f---i.~1-
1oI!
fenTX(L)
51 tosV
S2toO
S3toO
\---~--~---- 0
VOD - - - -.....
VOLTAGE WAVEFORMS
apulse generator with an output
of 0 to 3 V. PRR of 1 MHz, 50% duty cycle, tr and tf < 6 ns, and Zo = 50 n
Figure 6. Enable and Disable Test Circuit and Voltage Waveforms
NOTE A: The input is provided by
1ExAs
2-874
.Jf
INSIRUMENTS
POST OFFICE BOX 855303 • DAUAS. TEXAS 75265
SN75LBC976
9-CHANNEL DIFFERENTIAL TRANSCEIVER
SUSl33B - 04042, AUGUST 1992 - REVISED FEBRUARY 1993
TYPICAL CHARACTERISTICS
AVERAGE SUPPLY CURRENT
INPUT CURRENT
va
va
FREQUENCY
INPUT VOLTAGE
o
1000
400
I
::I
~
Go
U
I
/
::s.
I -20
40 -
-
9 Unloaded Receivers
I
~
U-30
V
::I
III
I
I
c(
100
!;
U
I
=
-10 -
~
C
I
VCC=4.75V
TA 25°C
A, DE/RE, CRE, BSR
i
I -40
.:
10
9
4
--==
9 Unloaded Drivers
-50
11 Jill
1
0.001
II 1111
0.004 0.01
0.04
2
4
--
/
~
/
/
J
V
/'
-60
o
10
0.5
1
1.5
2
2.5
3
3.5
4
4.5
VI-Input Voltage - V
r - Frequency - MHz
Figure 7
Figure 8
INPUT CURRENT
va
INPUT VOLTAGE
5
I
I
I
B+ and B-
4
3
~
2
I
I
U
0
5
~ -1
I
_ -2
1("".....
II
----
.....-
~~
./
-3
-4
-5
-20 -16 -12 -8 -4
0
4
8
VI -Input Voltage - V
12
16
20
Figure 9
TEXAS'"
INSTRUMENTS
POST OFFICE BOX 655303 • DALl.AS. TEXAS 75265
2-875
SN75LBC976
9-CHANNEL DIFFERENTIAL TRANSCEIVER
SU$133B - D4042.AUGUST 1992- REVISED FEBRUARY 1993
TYPICAL CHARACTERISTICS
DRIVER LOW-LEVEL OUTPUT VOLTAGE
2.1
>
I
va
LOW-LEVEL OUTPUT CURRENT
HIGH-LEVEL OUTPUT CURRENT
I
I
,1.8
o
1.6
•
>'
1.3
1.2
1.1
'5
V
1/
V
I
4.25
4
!
3.75
.c
co
l:
V
4.5
~
0
/
I
5
i
V
1.4
I
4.75 I- B+andB-
I
II
co
V
1.... 1.5
.3
~
V
1.9
1.7
5
V
VCC=SV
2 I- B+ and B-
i
HIGH-LEVEL OUTPUT VOLTAGE
vs
I
~
~
r---. ........ ............
3.5 ~
3
2.5
~
~
~
~
~
M ~ ~ 100
IOL - Low-Level Output Current - mA
......... r--.....,.
VCC=4.75V
J
o
FIgure 11
DRIVER DIFFERENTIAL OUTPUT VOLTAGE
vs
OUTPUT CURRENT
>I
t
;i
I
I
TA = 25°C
4
J ~~t:::
3
'ii
J
2
......
c
I
~
1
~
VCC=5V
'" """F::: r-.. t"-t'!=:::'",
V-
VCC = 5.25 V
~ ""'t""t:---.
I""- r-::::
VCC=4.75V
o
o
10
~
~
~
50 ~ M
10 -Input Current - mA
~
FIgure 12
.1ExAs . "
2-876
I
I
......
r---.....
-"'1"--
......
r---.....
-10 -~ -30 -~ -~ -~ -M -80-~
IOH - High-Level Output Current - mA
FIgure 10
5
VCC=5V -
..........
r---..... ~ -.......... ....J!
r---.
-....
............
.........
r---.....
3.25
2.75
o ro
,V
~ r---..... ~cc=5.25V
INSIRUMENTS
POST OFFICE BOX 855303 • DAllAS. TEXAS 7S265
~
100
SN75LBC976
9·CHANNEL DIFFERENTIAL TRANSCEIVER
SLLS133B- D4042, AUGUST 1992 - REVISED FEBRUARY 1993
TYPICAL CHARACTERISTICS
DRIVER HIGH-LEVEL OUTPUT CURRENT
DRIVER LOW-LEVEL OUTPUT CURRENT
vs
vs
SUPPLY VOLTAGE
SUPPLY VOLTAGE
0
~r-~J--~l--~~~--~~
Eli
I
~
I
~
~
oS
I
I
6O~~---I---+---,.-I-....,.:t=~:t===I
C
2! -20
!i
U
50 I - - - t - - t - - t - - t - t - - t - - t - - - I
40 I - - - t - - t - - t - - f - t - - t - - t - - - I
30 I---t--t--t-~t--t--t---I
'S
-30
Q,
'S
0
!
-40
......
-50
...........
CI
:i:
20 I - - - t - - t - - t - + - t - - t - - t - - - I
:§
101---t--t--t-+-t--t--t---I
O~
2
__L-__L-__
2.5
L-L-~
__
~
__
3
3.5
4
4.5
VCC - Supply Voltage - V
I
:J:
.9
-70
~--.J
5
-~
2
5.5
2.5
..
CI
!::
~
'S
~
0
!
CI
:f
I
:J:
~
5.5
RECEIVER LOW-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
LOW-LEVEL OUTPUT CURRENT
~
~
........
~
~ ........
..........
~ ....... VCC=5.25V
4
~ .......
3.5
f
I
4.5
"
3
"
2.5
1.5
-10
-20
-30
-40
i
I
r\.
~'"
'\ r\.'\
0.5
1.51--+---+--+-~~~-f---I
o
",' ~
VCC=4.75V
o
VCC =5V _
,~
2
o
'"
5
vs
5.5
5
3
3.5
4
4.5
VCC - Supply Voltage - V
Figure 14
RECEIVER HIGH-LEVEL OUTPUT VOLTAGE
GI
..........
-60
Figure 13
>I
I
E -10 f- B+ and B-
:::I
u
I
c(
70 r- B+ and B-
I
oJ
\ ~
1\ \ \
\ \
-50
-60
IOH - High-Level Output Current - mA
~
-70
10
20
30
40
50
IOL - Low-Level Output Current - mA
Figure 15
60
Figure 16
POST OFFICE BOX 655303 • DALlAS, TEXAS 75265
2-877
SN75LBC976
9·CHANNEL DIFFERENTIAL TRANSCEIVER
SLlS133B - 04042, AUGUST 1992 - REVISED FEBRUARY 1993
TYPICAL CHARACTERISTICS
DRIVER DIFFERENTIAL OUTPUT VOLTAGE
,
I
GO
~
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
--....
>
0.8
~
i
~
0.6
I
GI
E
1=
~
c
~
30
'ii
Vee = 4.75 V -
:::: ~I
c
c
0
iC/I
Ii
\
Vee = 5.25 V
25
2
IL
0.4
I
::J:
oJ
!
C
I
35
!
B+and B-
j
'!&:L5
'!5
0
RECEIVER PROPAGATION DELAY
VS
..
..
IL
o
160
20
15
0.2
oJ
::J:
IL
165
o
175
170
TA - Free-Air Temperature _·e
o
25
50
75
TA - Free-Air Temperature _·e
-25
Figure 17
Figure 18
DRIVER PROPAGATION DELAY
vs
FREE-AIR TEMPERATURE
25
I)
c
I
GO
E
20
1=
~
'ii
c
c
0
i
Vee=4.75~
15
r2
IL
I
..X
~
~
Vee = 5.25 V
10
o
-25
o
25
50
75
TA - Free·Air Temperature _·e
Figure 19
1ExAs . "
INSIRUMENIS
2-878
POST OFFICE BOX 655303 • DAUAS, TEXAS 75265
100
100
SN75LBC976
9-CHANNEL DIFFERENTIAL TRANSCEIVER
SLLSl33B - 04042, AUGUST 1992 - REVISED FEBRUARY 1993
APPLICATION INFORMATION
Table 1, Typical Signal and Pin Assignments
SIGNAL
PIN
CDEO
54
SCSI DATA
DIFFSENSE
SCSI CONTROL
IPIDATA
DIFFSENSE
VCC
GND
IPICONTROL
SLAVE/MASTER
CDEI
55
GND
GND
VCC
XMTA,XMTB
CDE2
56
GND
GND
XMTA,XMTB
BSR
2
GND
GND
GND, BSR
GND
CAE
3
GND
GND
GND
AD7, BD7
VCC
NOT USED
lA
4
DBO, DB8
ATN
lDE/RE
5
DBEO, DBE8
INITEN
GND
GND
2A
6
DB1, DB9
BSY
AD6, BD6
NOT USED
2DE/RE
7
DBE1, DBE9
BSYEN
GND
GND
3A
8
DB2, DB10
ACK
AD5, BD5
SYNC IN
9
GND
3DE/RE
DBE2, DBE10
INITEN
GND
4A
10
DB3, DBII
RST
AD4, BD4
SLAVE IN
4DE/RE
11
DBE3, DBEll
GND
GND
GND
5A
19
DB4, DB12
MSG
AD3, BD3
NOT USED
5DE/RE
20
DBE4, DBE12
TARGEN
GND
GND
6A
21
D85, D813
SEL
AD2, BD2
SYNC OUT
6DE/RE
22
DBE5, DBE13
SELEN
GND
GND
7A
23
DB6, DB14
C/D
AD1, BDI
MASTER OUT
7DE/RE
24
DBE6, DBE14
TARGEN
GND
GND
SA
25
DB7, DB15
REO
ADO, BDO
SELECT OUT
8DE/RE
26
DBE7, DBE15
TARG EN
GND
GND
9A
27
DBPO, DBPI
I/O
AP,BP
ATTENTION IN
28
DBPEO, DBPEI
9DE/RE
TARG EN
XMTA,XMTB
Vec
ABBREVIATIONS:
DBn, data bit n, where n = {O,I, ... ,15}
DBEn, data M n enable, where n = {O,I, .•. ,15}
DBPO, parity bit for data bits 0 through 7 or IPI bus A
DBPEO, parity bit enable for PO
PI, parity bit for data bits 8 through 15 or IPI bus B
PEl, parity M enable for PI
ADn or BDn, IPI Bus A- Btt n (ADn) or Bus B- Bit n (BDn), where n ={O,I, ... ,7}
AP or BP, I PI parRy bit for bus A or bus B
XMTA or XMTB, transmtt enable for IPI bus A or B
BSR, bit significant response
INIT EN, common enable for SCSI initiator mode
TARG EN, common enable for SCSI target mode
NOTE: Signal inputs are shown as active high. If only active-low inputs are available, logic inversion is
accomplished by reversing the B + and B- connecter pin assignments.
TEXAS'"
INSIRUMENIS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75266
2-879
SN75LBC976
9·CHANNEL DIFFERENTIAL TRANSCEIVER
SLLS133B - D4042.AUGUST 1992 - REVISED FEBRUARY 1993
APPLICATION INFORMATION
Function Tables
RECEIVER
DRIVER
A~B+
~BINPUTS
B-t
B+t
L
H
H
L
A - - . N - B+
B-
---vb-
OUTPUT
A
INPUT
A
L
H
L
H
DRIVER WITH ENABLE
TRANSCEIVER
1--_.-- B+
A-4I~-f
0--+....- B-
DElRE
INPUTS
A B+t
L
- H
L
H
-
-
-
B-T
H
L
-
A
L
H
INPUTS
DElRE
L
L
H
H
OUTPUTS
BB+
-
-
=G>b=
A
DElRE-t--..
DElRE
L
L
H
H
OUTPUTS
B+ BL
H
H
L
-
-
L
H
H
L
-
A
L
H
L
H
B+'
B-
OUTPUTS
BB+
Z
Z
Z
Z
L
H
H
L
TWO-ENABLE INPUT DRIVER
WIRED-OR DRIVER
A-"'-I
A~t-----I
B+
B+
B-
BDElRE
INPUT
A
L
H
OUTPUTS
BB+
Z
Z
H
L
---,lL~
INPUTS
DElRE A
L
L
L
H
L
H
H
H
OUTPUTS
BB+
Z
Z
H
L
L
H
H
L
H = high level. L = low level. X = irrelevant. Z = high impedance (011)
tAnH in this column represents a voltage 200 mV higher than the other bus input. An L represents a voltage 200 mV lower than the other bus
input. Any voltage less than 200 mV results in an indeterminate receiver output.
1ExAs
,If
INSIRUMENTS
2~80
POST OFFICE BOX 655303 • DAllAS. TEXAS _
SN75LBC976
9·CHANNEL DIFFERENTIAL TRANSCEIVER
SLl.Sl33B - 04042, AUGUST 1992- REVISED FEBRUARY 1993
APPLICATION INFORMATION
VCC
SCSI
Connector
I
+
1/01-....--.-1
EN I--=-.=i-___.
EN 1---:::-==+-4
(d) SEPARATE ACTIVE·HIGH INPUT, OUTPUT,
AND ENABLE
VCC
SCSI
(8) ACTIVE·HIGH BIDIRECTIONAL I/O
WITH SEPARATE ENABLE
VCC
SCSI
Connector
5600t
~
i
0* 1-.....----4.--i
ito I -.....- - - i . - - i
+
EN 1---.=+-___.
+
EN 1----,=1-___.
(b) ACTIVE·LOW BIDIRECTIONAL I/O
(e) SEPARATE ACTIVE·LOW INPUT AND
OUTPUT AND ACTlVE·HIGH ENABLE
WITH SEPARATE ENABLE
VCC
+
0*1-....--.-1
VCC
SCSI
SCSI
~ 5600t
Connector
+
Connector
nA
+
OH.------==+-......
o H~-t--n=D=E/ER;:Et--..
5600
(c) WlRED-OR DRIVER AND ACTIVE·HIGH INPUT
(f) WlRED-OR DRIVER AND ACTIVE·LOW INPUT
*t
If 0 is open drain
Must be open-drain or 3-state output
NOTE: The BSR, CRE, A, and DElRE inputs have internal pullups. CD EO, CDE1, and CDE2 have internal pUlidowns.
Figure 20. Typical SCSI Transceiver Connections
1ExAs ."
INSIRUMENIS
POST OFFICE BOX 655303 • DAUAS, TEXAS 75265
2-881
SN75LBC976
9-CHANNEL DIFFERENTIAL TRANSCEIVER
SLLS133B - 04042, AUGUST 1992 - REVISED FEBRUARY 1993
APPLICATION INFORMATION
channel logic configurations with control input logic
The following logic diagrams show the positive logic representation for all combinations of control inputs. The
control inputs are from MSB to LSB; BSR, CDEO, CDE1, CDE2, and CRE, and are shown below the diagrams.
Channel 1 is at the top and channel 9 at the bottom of the logic diagrams.
.
~
~
~
~
~
~
~
~
~
~
~
~
~
----b=
----I>b=
----I>b=
----I>b=
----I>b=
----I>b=
----I>b=
----I>b=
Figure 21. 00000
Figure 22. 00001
-JVV\r-
Hi-Z
-JVV\r-
HI-Z
-JVV\r-
Hi.z
-JVV\r-
~
~
~
HI-Z
-JVV\r-
Figure 23.00010
1ExAs
Hi.z
-JVV\r-
Figure 24.00011
,If
INSIRUMENTS
2-882
POST OFFICE BOX 655303 • DALlAS, TEXAS 75265
----I>b=
----I>b=
----I>b=
----I>b=
~
~
~
~
~
Figure 25.00100
SN75LBC976
9·CHANNEL DIFFERENTIAL TRANSCEIVER
SLLSl33B - D4042, AUGUST 1992 - REVISED FEBRUARY 1993
APPLICATION INFORMATION
-t>b=
-t>b=
-t>b=
-t>b=
Hl-Z
-'I/IIIr-
HI-Z
-'I/IIIr-
Hi-Z
-'I/IIIr-
Hl-Z
-'I/IIIr-
-t>b=
-t>b=
-t>b=
-t>b=
-t>b=
-t>b=
-t>b=
-t>b=
-t>b=
-t>b=
-t>b=
-t>b=
-t>b=
-t>b=
-t>b=
-t>b=
-'I/IIIr-
---<€t=
-'I/IIIr-
Figure 26. 00101
Figure 27.00110
Figure 28.00111
Hl-Z
Hl-Z
Figure 30. 01001
Figure 29. 01000
TEXAS
..If
INSIRUMENfS
POST OFFICE BOX 655303 • DAUAS. TEXAS 75265
2-883
SN75LBC976
9-CHANNEL DIFFERENTIAL TRANSCEIVER '
SLLSl33B ~ D4042,AUGUST 1992 - REVISED FEBRUARY 1993
APPLICATION INFORMATION
Figure 34. 01101
Figure 31. 01010
Figure 32.01011
Figure 35. 01110
Figure 33. 01100
)
1ExAs
2-884
.Jf
INSIRUMEN1S
POST OFFICE BOX 655303 • DAUAS, TEXAS 75265
SN75LBC976
9-CHANNEL DIFFERENTIAL TRANSCEIVER
SLLSl33B
D4042, AUGUST 1992 - REVISED FEBRUARY 1993
APPLICATION INFORMATION
-Dt=
-Dt=
-Dt=
-Dt=
-Dt=
-Dt=
-Dt=
-Dt=
~
Figure 36. 01111
HI-Z
-'VIIV-
HI·Z
-'VIIV-
HI-Z
-'VIIV-
HI-Z
-'VIIV-
HI-Z
-'VIIV-
HI-Z
-'VIIV-
HI·Z
HI·Z
~~
-'VIIV-
HI·Z
-'VIIV-
HI·Z
-'VIIV-
~~~
~
~
~
~ ~~
-'VIIV-
HI·Z
-'VIIV-
Hi·Z
-'VIIV-
Figure 37.
10000
and 10001
~
~
...
Hi·Z
-'VIIV-
Figure 38.10010
~
Figure 39.10100
~-
and 10011
and 10101
~
Hi·Z
-'VIIV-
...
HI·Z
-'VIIV-
~
Hi-Z
-'VIIV-
Figure 40. 10110
and 10111
1ExAs'"
INSIRUMENTS
POST OFACE BOX 655303 • DAllAS, TEXAS 75265
2-a85
SN75LBC976 .
9.;CHANNEL DIFFERENTIAL TRANSCEIVER
SLLS133B - D4042;AUGUST 1992 - REVISED FEBRUARY 1993
APPLICATION INFORMATION
=&t=
~ ~
~~~
~~~
~~~
-D-J=&t=~
HI-Z
-'IMr-
Figure 41.11000
and 11001
~=&t=~
~~~
~
Figure 42.11010
and 11011
~
Figure 43.11100
and 11101
~
HI-Z
-'IMr-
Figure 44. 11110
and 11111
2-886
POST OFFICE BOX 65S3(IG • DALlAS. TEXAS 75265
SN75LBC978
9-CHANNEL DIFFERENTIAL TRANSCEIVER
SLLS134B-
•
•
Each Transceiver Meets EIA-RS-485 and
ISO 8482:1987(E) Standards
•
Packaged In Shrink Smail-Outline Package
With 25-mll Terminal Pitch
•
•
DLPACKAGE
9 Differential Channels for the Data and
Control Paths of the Differential Small
Computer Systems Interface (SCSI)
Designed to Operate at 10 Million Transfers
PerSec.ond
Low Disabled Supply Current
1.4 mA Typ
•
Thermal Shutdown Protection
•
Power Up/Down Glitch Protection
•
PosHlve and Negative Output Current
Limiting
•
Open-Circuit Fall-Safe Receiver Design
(TOP VIEW)
46
NC
NC
CE
98+
98S8+
S87B+
7B6B+
6B-
VCC
45
VCC
GND
GND
GND
GND
GND
44
NC
WRAP2
WRAP1
1A
1Dem=
2A
2DE/RE
56
55
54
53
6
50
3A
49
3DE/RE
4A
4Dem=
48
47
11
The SN75LBC978 is a nine-channel differential
transceiver based on the 75LBC176 LinASIC™
cell. Use of the Texas Instruments LinBiCMOS™
process technology allows the power reduction
necessary to integrate nine differential balanced
transceiverst . On-chip enabling logic makes this
device applicable for the data path (eight data bits
plus parity) and the control path (nine bits) for the
Small Computer Systems Interface (SCSI)
standard. The WRAP function allows in-circuit
testing and wired-OR channels for the BSY, RST,
and SEL signals of the SCSI bus.
40
GND
GND
GND
GND
GND
39
Vcc
5B+
584B+
4B3B+
3B28+
2B18+
1B-
43
42
41
Vce
description
52
51
5A
5DE/RE
19
38
20
37
6A
21
36
6DE/RE
7A
7DE/RE
SA
8DE/RE
9A
9Dem=
22
35
23
34
24
33
25
32
26
31
27
30
28
29
Pins 13 through 17 and 40 through 44 are
connected together to the package lead
frame and signal ground.
The SN75LBC978 is packaged in a shrink small-outline package (OL) with improved thermal characteristics
using heat sink pins. This package is ideal for low-profile, space-restricted applications such as hard disk drives.
The switching speed of the SN75LBC978 is sufficient to transfer data over the data bus at 10 million transfers
per second. Each of the nine identical channels conforms to the requirements of the EIA-RS-485 and
ISO 8482:1987(E) standards referenced by ANSI X3.131-1986 (SCSI-1) and the proposed SCSI-2 standards.
This device conforms to ESO Class 1 (A) and Class 2 (B) per MIL-STO-883, Method 3015.
The SN75LBC978 is characterized for operation from C·C to 70·C.
t Patent Pending
UnASIC and UnBICMOS are trademarks of Texas Instruments Incorporated.
Copyright iC) 1993. Texas Instruments Incorporaled
POsT OFFICE BOX 655303 • DALlAS, TEXAS 75285
2-887
SN75LBC978
9-CHANNEL DIFFERENTIAL TRANSCEIVER
Su.s1348 - 04088, APRIL 1992 - REVISED FEBRUARY 1993
logic diagram (positive logic)
~--------------------,
1A--~------~~--'
WRAP1--~-~---~
I--...--+--
18+
D--t-.-+--
18-
1DE/RE --+--+-+-----+--1
I
I
I
I
I .--t------'
-----------------L-.I
r_t--------------------'--I
I
2A-f
-I
2DE./RE
3A
3DEIRE
-I
4A - .
-I
SA
~--I.
SA
6DE/RE
7A
2838+
Channel 3
Channel 4
ChimnelS
t----
38-
48+
4858+
58-
~-~------------------~
ChannelS
r-- 68+.
--I
l-- 68~
~ -------------------~
......r>-~t_+II
7DEIRE --;-H-t----t--(-~
1--_-'
I
I
I
I
I
I
I
I
I
I
I
I
I
SA
t
-----------------.
-.
ChannelS
.SDE/RE - I
I-WRAP2 --t-t--.----:--t-i._'"
t--------------------,
9A--.
I
Channel 9
1ExAs ."
INSIRUMENfS
POST OFFICE BOX 855303 • DALlAS, 1EXAS 7526«5
78+
78-
S8+
S8-
. - - 98+
I
I-~--------------------~
9DE./RE ----I
2-888
28+
Channel 2
t--------------------,It-t--------------------,rt--
4DE/RE
SDE./RE
I
I
I
I
I
I
I
I
98-
SN75LBC978
9-CHANNEL DIFFERENTIAL TRANSCEIVER
SLlS1348 - 04088, APRIL 1992- REVISED FEBRUARY 1993
I
schematics of inputs and outputs
INPUTCE
ALL INPUTS EXCEPT CE
VCC
VCC
Input -
........."""-1\,--<...>--.........
Input
----e+.J\IIo/Ir-.....----4t-.
RECEIVER OUTPUT
B+ AND B-I/O PORTS
100kO
B+Only
3kO
l8kO
Receiver
Driver
l00kO
B-Only
12kO
B+orB-
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage range, Vee (see Note 1) ............................................. -0.3 V to 7 V
Bus voltage range ................................................................ -10 V to 15 V
Data I/O and control (A-side) voltage range ........................................... -0.3 V to 7 V
Continuous power dissipation ............................. '. . . . . . . . . . . . . . . . . . . . . .. internally limited
Operating free-air temperature range, TA .............................................. O·C to 70·C
Storage temperature range ....................................................... -65·C to 150·C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds ............................... 260·C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only. and
functional operation of the device at these or any other conditions beyond those Indicated under "recommended operating conditions" Is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are dc and with respect to the GND terminal.
1ExAs
~
INSTRUMENTS
POST OFFICE BOX 655303 • DAUAS, TEXAS 75265
2-889
SN75LBC978
9-CHANNEL DIFFERENTIAL TRANSCEIVER
Sll.Sl348 -04088. APRil 1992- REVISED FEBRUARY 1993
recommended operating conditions
Supply voltage. VCC
Voltage at any bus terminal (separately or common-mode), YO. VI. or VIC
MIN
NOM
MAX
UNIT
4.75
5
5.25
V
12
B+ or B-
-7
High-level input voltage, VIH
All except B+ and B-
Low-level input voltage, VIL
All except B+ and B-
2
V
0.8
V
-60
mA
A
-S
mA
B+ or B-
60
mA
8
mA
70
·C
B+ or B-
High-level output current, 10H
Low-level output current, 10L
V
A
Operating free-air temperature, TA
0
driver electrical characteristics over recommended ranges of operating conditions (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
IVODI
Differential output voltage
Vtest =-7Vto 12V,
lOS
Output short-circu~ current
See Figure 1
10Z
High-Impedance state output current
MIN
TYP
1
2
See Figure 2
MAX
UNIT
",250
mA
V
See receiver input current
receiver electrical characteristics over recommended ranges of operating conditions (unless
otherwise noted) (see Figure 3)
PARAMETER
TEST CONDITIONS
MIN TYPt MAX
UNIT
High-level output voltage
VOH
VOL . Low-level output voltage
VID =200 mV,
10H =-SmA
VID = -200 mV,
IOL=8mA
Vr+
Differential-input high-level threshold voltage
10H=-SmA
Vr-
Differential-input lOW-level threshold voltage
10L=SmA
Vhys
Receiver input hysteresis (\IT+ - VT-l
II
10Z
Receiver input current
V
O.S
0.2
-0.2
B+and B-
High-impedance state output current
VCC=5V,
VI = 12V,
Other input at 0 V
VCC=OV,
VI=-7V,
Other Input at 0 V
VCC=5V,
VI=-7V.
Other input at 0 V
VCC=OV,
POST OFFICE
0.7
1
rnA
O.S
1
mA
-0.5
-O.S
mA
-0.4
-0.8
mA
-100
VO=VCC
50
1ExAs
,If
eox 655303 •
OAU.AS, TEXAS 75265
V
mV
VO=GND
INSIRUMENTS
V
V
45
VI = 12V,
Other input at 0 V
t All typical values are at VCC = 5 V, TA = 25·C.
2-890
2.5
IlA
SN75LBC978
9-CHANNEL DIFFERENTIAL TRANSCEIVER
SLLS1348 - 04088, APRIL 1992 - REVISED FEBRUARY 1993
device electrical characteristics over recommended ranges of operating conditions
PARAMETER
IIH
High-level input current
IlL
Low-level input current
ICC
Supply current
Co
Cpd
TEST CONDITIONS
A. WRAP, DElRE
MIN
TYpt
MAX
UNIT
-100
SO
IlA
IlA
IlA
IlA
1.4
3
mA
29
4S
mA
7
10
mA
VIH=SV
CE
SO
See Figure 3
A. WRAP, DElRE
-200
VIL=OV
CE
-SO
All drivers and receivers
disabled
CE at OV
All receivers enabled
No load,
CEatS\/,
All drivers enabled
No load,
CE and DElRE at S \/,
WRAPatOV
Bus port capacitance
VID=SV,
WRAP and DElRE at 0 V
B+or BOne driver
Power dissipation capacHance*
One receiver
19
pF
460
pF
40
pF
driver switching characteristics over recommended operating conditions (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
MIN
TYpt
11.8
!do
tskQim)
Differential delay time, high-ta-Iow-Ievel output (tdDH> or
low-to-high-Ievel output (tdDU
Skew limit, the maximum difference in propagation delay
times between any two drivers on any two devices
tsk(p)
Pulse skew (~dDL -tdDHI)
tt
Transition time (lr or tf)
MAX
UNIT
26.4
VCC = 5 \/,
TA=25"C
14
18
22
VCC =S\/,
TA=70"C
18
22
26
VCC =S\/,
See Note 2
15
8
0
6
ns
ns
ns
ns
10
t All typical values are at VCC = 5 V, TA = 25"C.
*
Cpd determines the no-load dynamic current consumption, IS = Cpd VCC f + ICC.
NOTE 2: This specification applies to any S"C band wHhin the operating temperature range.
transceiver switching characteristics over recommended operating conditions
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
len(TU
Transmit-ta-receive enable time to low-level output
80
ns
ien(TH)
Transmit-ta-receive enable lime to high-level output
80
tenlRU
Receive-to-transmit enable time to low-level output
ns
ns
ns
ns
See Figure 6
ten(RH)
Receive-to-transmit enable time to high-level output
tsu
Setup time, WRAPl or WRAP2 before active input(s) or output(s)
lS0
150
lS0
thermal characteristics
PARAMETER
TEST CONDITIONS
RaJA
Junction-ta-free-alr thermal resistance
RaJc
Junction-ta-case thermal resistance
Board mounted,
No airflow
MIN
TYP
MAX
UNIT
SO
"C/W
12
"C/W
TEXAS . "
INSlR.UMENIS
POST OFFICE BOX 65S303 • DALLAS, TEXAS 75265
2~91
SN75LBC978
9-CHANNEL DIFFERENTIAL TRANSCEIVER
Su.sl34B - D4OB8, APRIL 1992- REVISED FEBRUARY 1993
receiver switching characteristics over recommended operating conditions (unless otherwise
,
noted)
PARAMETER
TEST CONOI11ONS
MIN
TYpt
19.5
tpd
Propagation delay time, hlgh-to-Iow-Ievel output (tPHU or
low-to-hlgh-Ieveloutput (tpLHl
tskOim)
Skew limit, the maximum difference in propagation delay
times between any two drivers on any two devices
tsk(p)
Pulse skew (~PHL - tpLHD
VCC=5V,
TA=25°C
20.2
24.7
29.2
TA=70°C
21.1
25.6
30.1
VCC=5V,
See Note 2
12
9
2
3
NOTE 2: This specification applies to any 5°C band within the operating temperature range.
PARAMETER
MEASUREMENT INFORMATION
/
:~ I
voo} -~--..,
-IOH. -IOL. -lOS.
or
-IOZ
CEand
DE/REat2V,
WRAP1and
WRAP2 at 0.8 V
(see Nota A)
NOTE A: For the 10Z test, the CE input is at 0.8 v.
Figure 1. Driver Test and Input Conditions
Vlest
R1 =165Q
B+
OVor3V _ _ _..:.;A=-I
BR2=165r.l
CEand
OC/REat2V.
WRAP1and
WRAP2 at 0.8 V
Vlest
figure 2. Driver VOD Test Circuit
ThxAs . "
2~92
INSlRUMENTs
POST OFFICE BOX 655303
~
OAUAS, TEXAS 75265
UNIT
30.7
VCC =5V,
Transition time (tr or ttl
It
t All typical values are at VCC = 5 V, TA = 25°C.
,.-----r-- { A
MAX
6
ns
ns
ns
ns
SN75LBC978
9·CHANNEL DIFFERENTIAL TRANSCEIVER
SUS1348 - 04088, APRIL 1992 - REVISED FEBRUARY 1993
PARAMETER MEASUREMENT INFORMATION
ATIOH
or
-IOH.-IOLo
...
or
VOL
.1
-IOZ
-::-
1
NOTe k. For the 10Z measurement, ce is at 0.8 v.
Figure 3. Receiver Test and Input Conditions
GNO
R1 =1650
r---'-~~--~~-----,.--B+
Input _ _ _..::A'-J
(see Note A)
Output
L---'-~~---4---~~~-R2=1650
T SOpFt
5V
CEand
OE/REBtVCC
B-
t Includes probe and jig capacitance.
- - - - - - - - - 3V
Input_ _ _J , {- - - - - - -
-~-- ---~--= ~.~v
I
!.- tcI0H ~
I
Output
I
i+- tcI0L ~
I
10%.Ir-~----!!Q.%f\1ci%--
-....:.:~I I
tr
-+I I+-
OV
I I
tf
-+I I+-
NOTe k. The input is provided by a pulse generator with an output of a to 3 V. PRR of 1 MHz, 50% duty cycle,
tr and tf < 6 ns, and Zo =50 c.
Figure 4. Driver Propagation Delay Time Test Circuit and Waveforms
ThxAs
..If
INSIRUMENTS
POST OFFICE BOX 655303 • DAllAS, TEXAS 752.65
2-893
SN75LBC978
9·CHANNEL DIFFERENTIAL TRANSCEIVER
SLLS134B - 04088, APRIL 1992 - REVISED FEBRUARY 1993
PARAMETER MEASUREMENT INFORMATION
CEatVcc,
DElRE, WRAP1 and
WRAP2at GND
Input
(see Note A) - - B+
1.5V--B-
-------3V
..1,(--------~--------= ~.~V
Input _ _ _
I
Output
I
I+-IdDH -+i
i+-IdDL -+i
I
I
-----1:.:0%..::::.r-,lf-"!!'----~i\~~== ~?
t,~ I+-
tf - . .
~
t Includes probe and jig capacitance.
NOTE A: The input is provided by a pulse generator with an output of 0 to 3 V. PRR of 1 MHz, 50% duty cycle,
tr and tf < 6 ns, and Zo = 50 0.
Figure 5. Receiver Propagation Delay Time Test Circuit and Waveforms
1ExAs
2-894
,If
INSIRUMENTS
POST OFFICE BOX 655303 • DALlAS. TEXAS 75265
SN75LBC978
9-CHANNEL DIFFERENTIAL TRANSCEIVER
SLlSl34B - D4088, APRIL 1992 - REVISED FEBRUARY 1993
PARAMETER MEASUREMENT INFORMATION
o
3V
6
S3
74HC241
B+
A
750
Voo
B-
Input
(see Note A)
CEatVcc,
EIR
_--4t-;;:.O;;:.:..:E~_--I WRAP1 and WRAP2
at GNO
52
Input
--~t
~-------~~~::
:
VA
:
0-0
!+- ten(RL) ...,
;r--------"'\___
--1.4 V
----TJj
51 toO
S2to5V
S3to3V
I4j
..- -..
~j- ten(TH)
,
I
.Jl-,..----------"'-~----
VOO _ _ _ _ _ _
0V
---------- ::
ir---""\~
Input _ _ _
:
VA
-----f'\!\
!..- ten(RH) -+I
fr----------
1.4 V
51 to5V
S2toO
S3toO
!...----1...:- ten(TL)
VOO
----'""'\------r------
OV
t Includes probe and jig capacitance.
NOTE A: The input is provided by a pulse generator with an output 01 0 to 3 V. PRR of 1 MHz, 50% duty cycle. Ir and If < 6 ns, and Zo
=50 O.
Figure 6. Enable and Disable Time Measurements
1ExAs
..If
INSIRUMENTS
POST OFFICE BOX 655303 • DAllAS, TEXAS 75265
2-895
SN75LBC978
9·CHANNEL DIFFERENTIAL TRANSCEIVER
Su.8134B - D4068, APRIL 1992 - REVISED FEBRUARY 1993
APPLICATION INFORMATION
Truth Tables for Possible Channel Functions
Table 1
Table 2
CElshlgh
CE Is high
WRAP1 or WRAP2ls low
WRAP1 or WRAP2 is high
/
DElRE -
A-.--I
O-+-.-
Emitter Follower
.....--1
B-
DElRE-f--"
A-+--< ""-I:r-. .-
B+
B-
Open Collector
INPUTS
DElRE
L
L
H
H
OUTPUTS
INPUTS
A
B+t
B-T
A
B+
B-
X
X
L
H
L
H
X
X
H
L
X
X
L
H
Z
Z
Z
Z
Z
Z
L
H
H
L
DElRE
L
L
H
H
OUTPUTS
B+
B-
A
B+
B-
L
H
X
X
H
L
X
X
L
H
H
H
Z
Z
Z
Z
H
H
L
L
H =high level, L =low level, X =Irrelevant Z =high impedance
tAn H in this column represents a voHage 200 mV higher than the other bus input. An L represents a voHage 200 mV lower than
the other bus input. Any voHage less than 200 mV results in an indeterminate receiver output.
1ExAs ..,
INSIRUMENTS
2-896
POST OFFICE BOX 665303 • DAUAS, TEXAS 75265
SN75LBC978
9-CHANNEL DIFFERENTIAL TRANSCEIVER
SUSl348 - D4088, APRil 1992 - REVISED FEBRUARY 1993
TYPICAL CHARACTERISTICS
AVERAGE SUPPLY CURRENT
INPUT CURRENT
vs
vs
FREQUENCY
INPUT VOLTAGE
1000
0
400
-10 -
~
I
1:
~
::I
0
~
Q.
0
E
L
/
c(
:1I
100
40 t-- 9 Unloaded Receiver.
1:
~
::I
~
t--
-20
-30
0
./
5Q.
::I
1/1
I
I
I
I
I
I
VCC=4.75V
TA=25°C
A, DElRE, WRAP1, WRAP2
.E
10
-40
I
=
r-=
4 t-- 9 Unloaded Drivers
-50
II 1111
1
0.001
II 1111
0.004 0.01
2
0.04
4
-
-
./
o
V
V V
-60
10
/
V
1.5
0.5
2
2.5
3
3.5
4
4.5
VI-Input Voltage - V
,- Frequency - MHz
Figure 8
Figure 7
INPUT CURRENT
vs
INPUT VOLTAGE
5
4
I
I
I
B+andB-
3
~
2
./
I
1:
~
::I
0
~
Q.
.E
I
=
0
-1
-2
..- ..-
...-
:,.......- ~
~
-3
-4
"
-5
-20 -16 -12 -8 -4 0
4
8
VI -Input Voltage - V
12
16
20
Figure 9
POST OFACE BOX 65530G • DALLAS. TEXAS 75266
2-a97
SN75LBC978
g..CHANNEL DIFFERENTIAL TRANSCEIVER
SLLS134B - D4088, APRIL 1992 - REVISED FEBRUARY 1993
TYPICAL CHARACTERISTICS
DRIVER LOW·LEVEL OUTPUT VOLTAGE
2.1
va
LOW·LEVEL OUTPUT CURRENT
HIGH·LEVEL OUTPUT CURRENT
1
.1
I
•
2 I- B+and B-
I
1.8
1.4
I
1.2
1/
V
V
4.75
4.5
aI
I
4.25
0
3.75
!...
3.5
3.2&
:I:
I
:I:
3
1
!i
/
1.5
>'
I
•
/
1.6
~ 1.3
:s
V
!i 1.7
I0
B+and B-
V
1.9
aI
I
&
/
VCc=&V
>
HIGH·LEVEL OUTPUT VOLTAGE
va
V
9
oj'
1.1
\...
4
........VCC = &.25 V
~ ..........
.......... ........
'-
..........
""""'"
.......... ..... ............ .....(
""""'. "
2.75
10
20
30
40
&0
60
70
80
80 100
o
10
20
Figure 10
30
va
OUTPUT CURRENT
>1
f
I
I
~1
CI
~
VCC=4.75V
o~~~--~~~--~~~--~~
10
20
.........
I
I
40
&0
Figure 11
DRIVER DIFFERENTIAL OUTPUT VOLTAGE
30 40 &0 60 70 80
10 - Output Current - mA
Figure 12
1ExAs . "
2-898
.........
VCc=&V -
..........
..........
...........
60
70
.......
.......
INSlRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
90 100
..........
i'-..........
60
10H - Hlgh·Level Output Current - mA
IOl - Low-Level Output Current - mA
o
..........
VCC·4.75V
2.5
o
r.........
80
SN75LBC978
9-CHANNEL DIFFERENTIAL TRANSCEIVER
SlLS134B - 04088, APRIL 1992-REVISED FEBRUARY 1993
TYPICAL CHARACTERISTICS
DRIVER HIGH-LEVEL OUTPUT CURRENT
DRIVER LOW-LEVEL OUTPUT CURRENT
VB
SUPPLY VOLTAGE
va
SUPPLY VOLTAGE
o
~r---r-~~~--~--~---r--~
B+~ndB-
1
1
70
.....~=:t=:::::::j
6O~-I~--+---+'---.4-
I
-10
I
C -20
!
a
!'S
40 1--+--+-4---f-+----lf---+--I
I
I
I-so
:r---I-_4~-4_4~--_+--~---I 7
5
10r-~~_4---4~-+--_+--~--_I
60~--~~~~--~---+--~--~
I
B+andB-
§
U
i
-30
-40
"'-
-60
§
o~~~~--~~~--~---L--~
2
2.5
3
3.5
4
4.5
5
-70
"' r-..... "'i'......
-80
5.5
2
~
3
U
4
U
5
~
VCC - Supply Voltage - V
VCC - Supply Voltage - V
Figure 14
Figure 13
RECEIVER LOW-LEVEL OUTPUT VOLTAGE
RECEIVER HIGH-LEVEL OUTPUT VOLTAGE
va
va
HIGH-LEVEL OUTPUT CURRENT
LOW-LEVEL OUTPUT CURRENT
5.5
......
~ I'-...
4.5
~ 'VCC=5.25V
4
~
3.5
5
>I
...at
III
~
'5
Q.
'S
0
~
.~
J:
"""
3
"
"
2.5
2
""""
,~
,,,- ,
~~
'\ \'\
\
\\ \
\ \
1.5
VCC=4.75V
I
J:
~
VCC=5V _
0.5
o
o
-10
-20
-30
-40
-so
-60
-70
IOH - High-level Output Current - mA
IOL - LowoLevel Output Current - mA
Figure 15
Figure 16
1ExAs
..If
INSIRUMENlS
POST OFFICE BOX _
• DAllAS, TEXAS 75285
2-899
SN75LBC978
9·CHANNEL DIFFERENTIAL TRANSCEIVER
SL.LSl34B - 04088, APRIL 1992 - REVISED FEBRUARY 1993·
TYPICAL CHARACTERISTICS
DRIVER DIFFERENTIAL OUTPUT VOLTAGE
J
va
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
--......
>I
0.8
~
~
'S 0.6
0
ii
RECEIVER PROPAGATION DELAY
va
211.5
'"\,
B+ and B-
!!
•E
I~
2! 0.4
i
~
'C
Q,
160
V V
-
25
[
e
..
24.5
'I
165
170
TA - Free-Air Temperature - "C
-
V
k-- V
24 0
175
10
20
va
23
f&
/
/ V/
22
21
VCC=4.75V/
20
/' V/
19
/ ~
11
r
It
40
Figure 18
FREE-AIR TEMPERATURE
18
I
17
J.
16
V/ V"
"
V ~C"5.25V
~V
I""
15 0
10
,.
20
30
40
110
60
TA - Free-Air Temperature _·C
Figure 19
1ExAs
~
INSIRUMENTS
POST OFFiCe BOX _
• DAUAII, 1EXAS _
I
70
V
",
30
DRIVER PROPAGATION DELAY TIME
1=
V
60
TA - Free-Air Temperature _·c
Figure 17
•cI
•E
V
L
/'
VCC .. I5.25~
I
0.2
o
25.5
S
IlD
~
VCC=4.75~
1=
E
D
I
D
211
I
60
70
I
SN65C1154, SN75C1154
QUAD LOW·POWER DRIVERS/RECEIVERS
DECEMBER 1988- REVISED MARCH 1993
SUS151A-
ow OR N PACKAGE
• Meets Standard EIA-232-D (Revision of
RS-232-C)
• Very Low Power Consumption
5mWTyp
• Wide Driver Supply Voltage ... :1:4.5 V
to :!:15V
• Driver Output Slew Rate Limited to 30 V/fJS
Max
• Receiver Input Hysteresis .•• 1000 mV Typ
• Push-Pull Receiver Outputs
• On-Chip Receiver 1-!JS Noise Filter
description
The SN65C1154 and SN75C1154 are low-power
BI-MOS devices containing four independent
drivers and receivers that are used to interface
data terminal equipment (DTE) with data circuitterminating equipment (DCE). This device has
been designed to conform to Standards ANSII
EIA-232-D-1986 (which supersedes RS-232-C).
The drivers and receivers of the SN65C1154 and
SN75C1154 are similar to those of the SN75C188
quadruple driver and SN75C189A quadruple
receiver, respectively. The drivers have a
controlled output slew rate that is limited to a
maxim urn of 30 V/fJS and the receivers have filters
that reject input noise pulses of shorter than 1 fJS.
Both these features eliminate the need for
external components.
(TOP VIEW)
Vee
lRY
1DA
2RY
2DA
3RY
3DA
4RY
4DA
3RA
3DY
4RA
8
11
Vss
GND
logic symbol t
1RA
2RA
3RA
4RA
1DY
2DY
3DY
4DY
19
2
IT
4
17
6
15
8
13
3
15
14
1V
13
1V
1R
20
3
lr
V2
t>
9
4[
2
1
A
10
1V
11
1v
2R
lr
5
v2
6
~[ L-1
7
RE
1V
14
1Z
10
13
1A
2
1B
1R
2Y
10E
10
1R
2DE
20
2R
4
15
EN
t>
14
V
13
V
3
12
9
lr
EN
t>
4[
2
1
L-1
10
V
11
V
5
lr
4[
6
7
A
2D
2A
11
2B
6
7
1V
101(:
1A
10
1B
2Y
1R
2Z
2A
2DE
2B
20
2R
.
EQUIVALENT OF DRIVER ENABLE INPUT
Input -'V\I\r____
~
14
-;-b
10
~
13
...
11
6
7
EQUIVALENT OF A OR B INPUT
Input --+--llJVIr__
288kQ
NOM
GNO----~_---.----
or
GNO(B)
__- - - GNO
1ExAs ..,
INSIRUMENIS
2-910
2B
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
1V
1Z
1A
1B
vee---------.-------.---
I\N~
2A
4
schematics of inputs
Vee
2Y
2Z
'1168
1Z
t These symbols are in accordance with ANSI/IEEE SId 91·1984
and IEC Publication 617·12.
1Z
1A
1B
10
2Z
2R
'1168
1V
It-----ir---
2Y
2Z
2A
2B
SN65C1167, SN65C1168, SN75C1167, SN75C1168
DUAL DIFFERENTIAL DRIVERS AND RECEIVERS
SLL.S159 - 04062, MARCH 1993
schematics of outputs
TYPICAL OF EACH DRIVER OUTPUTS
TYPICAL OF EACH RECEIVER OUTPUTS
---~.---e----
VCC
Vcc
Output
---~
:==~.ND
---~.--.--e----- GND
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, Vee (see Note 1) .............................................. -0.5 V to 7 V
Input voltage range, VI ...................................................... -0.5 V to Vee + 0.5 V
Input voltage range, A or B, Receiver ................................................ -11 Vto 14 V
Differential input voltage range, VID, Receiver (see Note 2) ............................. -14 V to 14 V
Output voltage range, VO, Driver ...................................................... -5 V to 7 V
Clamp current range, 11K or 10K, Driver ................................................... ±20 mA
Output current range, 10, Driver ......................................................... ± 150 mA
Supply current, ICC ..................................................................... 200 mA
GND current ......................................................................... -200 mA
Output current range, 10, Receiver ...................................................... :1:25 mA
Continuous total power dissipation ..................................... See Dissipation Rating Table
Operating free-air temperature range, TA: SN75C1167, SN75C1168 ...................... O·C to 70·C
SN65C1167, SN65C1168 .................... -40·C to 85·C
Storage temperature range ....................................................... -65·C to 150·C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds ............................... 260·C
NOTES: 1. All voltage values, except differential input voltage, are with respect to the network ground terminal.
2. Differential input voltage is measured at the noninverting terminal with respect to the inverting terminal.
DISSIPATION RATING TABLE
TAs25°C
POWER RATING
OPERATING FACTOR
ABOVE TA = 25°C
DB
781 mW
6.2mW/"C
502mW
409mW
N
1250mW
10mWrC
736mW
650mW
NS
625mW
5mWrC
445mW
325mW
PACKAGE
TA=70°C
POWER RATING
TA = 85°C
POWER RATING
1ExAs ",
INSIRUMENTS
POST OFFICE BOX 655303 • DAUAS, TEXAS 75265
2-911
SN65C1167, SN65C1168, SN75C1167, SN75C1168
DUAL DIFFERENTIAL DRIVERS AND RECEIVERS
SL.LS159 - 04062, MARCH 1993
recommended operating conditions
PARAMETER
Supply voltage, VCC
Common-mode Input voltage. VIC (see Note 3)
Receiver
MIN
NOM
MAX
4.5
5
5.5
V
z7
V
z7
V
Differential Input voltage, VID
Receiver
High-level input voRage, VIH
Except A, B
Low-Ievellnput voltage, VIL
ExceptA,B
0.8
Receiver
-6
High-level output current, IOH
Low-level output current, IOL
Operating free-air temperature, TA
V
-20
Driver
Receiver
6
20
Driver
SN65C1167 and SN65C1168
-40
85
SN75C1167 and SN75C1168
0
70
NOTE 3: Refer to EIA standards RS-422-A for exact conditions.
2~12
2
1ExAs'"
INSTRUMENfS
POST OFFICE BOX 655300 • DAUAS, TEXAS 75265
UNIT
V
rnA
rnA
·C
SN65C1167, SN65C1168, SN75C1167, SN75C1168
DUAL DIFFERENTIAL DRIVERS AND RECEIVERS
SLLS159-D4062, MARCH 1993
DRIVER SECTION
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
Input clamp voltage
11=-18mA
VOH
High-level output voltage
VIH=2V,
VIL=0.8V,
10H=-20mA
VOL
loW-level output voltage
VIH=2\1,
VIL=0.8V,
IOL=20mA
IV OD11
Differential output voltage
10=OmA
IV OD21
Differential output voltage
dlVODI
Change in magnHude of differential
output voltage
2.4
VOC
Common-mode output voltage
dlVoci
Change in magnHude of common-mode
output voltage
MAX
3.4
0.2
2
2
RL= 100 0,
TYpt
-1.5
VIK
0.4
3.1
I Vo=6v
V
V
6
See Figure 1 and Note 3
UNIT
V
V
V
",0.4
V
",3
V
",0.4
V
100
!AA
!AA
10(OFF)
Output current with power off (see Note 3)
10Z
High-impedance-state output current
IIH
High-level input current
VI = VCC or VIH
1
IlL
Low-level input current
VI = GNDorVIL
-1
!AA
!AA
lOS
Short-circuit output currerit
Vo = VCC or GND,
-150
rnA
Supply current (total package)
No load,
Enabled
ICC
VCC=OV
-100
Ivo =-0.25V
20
VO=2.5V
-20
VO=5V
-30
See Note 4
IVI =VCCor GND
J VI = 2.4 or 0.5 V,
See Note 5
4
6
5
9
!AA
rnA
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
tPHL
Propagation delay time, high-to-Iow-Ievel output
tpLH
Propagation delay time, low-to-high-Ievel output
tsk(p)
Pulse skew
tr
Rise time
tf
Fall time
tpZH
Output enable time to high level
tpzL
Output enable time to low level
tpHZ
Output disable time from low level
tpLZ
Output disable time from high level
Ci
Input capacHance
MIN
a.
R1 =R2 =500,
C1 =C2 =C3=40pF,
See Figure 2
R3 = 500
S1 is open,
R1 = R2 =500,
C1 = C2 = C3 = 40 pF,
See Figure 3
R3 =5000,
S1 is open,
R1 = R2 =500,
C1 = C2 = C3 = 40 pF,
See Figure 4
R3 =5000,
S1 is closed,
R1 =R2 =500,
C1 = C2 = C3 = 40 pF,
See Figure 4
\
R3 =5000,
S1 is closed,
TYpt
MAX
7
12
ns
7
12
0.5
4
ns
ns
5
10
ns
5
10
ns
10
19
ns
10
19
ns
7
16
ns
7
16
ns
6
UNIT
pF
t All typical values are at VCC = 5 V and TA = 25°C.
NOTES: 3. Refer to EIA standards RS-422-A for exact conditions.
4. Not more than one output should be shorted at a time, and the duration of the short clrcuH should not exceed one second.
5. Measured per input while the other inputs are at VCC or GND.
. 1ExAs'"
INSIRUMENTS
POST OFACE SOX 655303 • DAUAS, TEXAS 75265
2-913
SN65C1167, SN65C1168, SN75C1167, SN75C1168
DUAL DIFFERENTIAL DRIVERS AND RECEIVERS
SLLS159- 04062, MARCH 1993
RECEIVER SECTION
electrical characteristics over recommended ranges of coml11on-mode Input voltage, supply
voltage, and operating free-alr temperature (unless otherwise noted)
PARAMETER
TEST CONomONS
VT+
VT-
Positlvli-going threshold voltage, differential input
Vhvs
VIK
Input hysteresis (VT
Input clamp voltage, RE
VOH
High-level outpUt voltage
VOL
IOZ
Low-level output voltage
High-impedance-state output current
II
Une input current
MIN
TYPt
MAX
0.2
Negatlve-going threshold voltage, differential input
mV
80
!'1167
-l.S
II ",-18mA
VIO-2OOmV,
VIO .. -200 mV,
!'1187
IOH=-8mA
3.8
IOL=8mA
Vo - Vee or GNO
Other Input at 0 V
4.2
V
0.3
V
.. O.S
.. S
!AA
VI,,10V
1.S
-2.S
.. 1
VI =-10V
II
Enable input current, RE
Input resistance
VIC=-7Vto7V,
Other input at 0 V
VI=VCCor GNO
4
6
lee
Supply current (total package)
No load, Enabled
VIH" 2.4 V or O.S V,
See NoteS
S
9
VI = VCC or GND
4
V
0.1
'1
!'1187
V
V
-0.2*
+- VT.J
UNIT
mA
!AA
kg
17
mA
switching characteristics over recommended ranges of supply voltage and operating free-alr
temperature (unless otherwise noted)
tpLH
tPHL
lTLH
PARAMETER
Propagation delay time, low-to-high-level output
Propagation delay time, high-to-Iow-level output
Transition time, Iow-to-high-Ievel output
lTHL
tpZH
Transition time, high-to-Iow-Ievel output
Output enable time to high level
'1187
tpZL
Output enable time to low level
'1187
tpHZ
Output disable time from high level
'1187
TEST CONomONS
See Figure S
VIC·OV,
RL-lkg,
See Figure S
See Figure 8
MIN
TYPt
MAX
9
9
17
17
27
27
4
9
ns
ns
UNIT
ns
4
9
ns
13
22
ns
13
22
22
ns
ns
13
RL-l kD, See Figure 8
'1167
13
22
ns
tpLZ Output disable time from low level
tAIl typlcal values are at VCC S V and TA 2SoC.
* The algebraic convention, where the less positive (more negative) limit Is deSignated as minimum, is used In this data sheet for common-mode
input voltage and threshold voltage levels only.
NOTE S: Measured per input while the other inputs are at Vee or GNO.
=
=
PARAMETER MEASUREMENT INFORMATION
Figure 1. Driver Test Circuit, VOD and Voe
1ExAs ."
2-914
INSlRUMENTS
POST OFFICE BOX 856303 • DAllAS, TEXAS 711285
SN65C1167, SN65C1168, SN75C1167, SN75C1168
DUAL DIFFERENTIAL DRIVERS AND RECEIVERS
SUS159-D4062. MARCH 1993
PARAMETER MEASUREMENT INFORMATION
1.3V\------ ::
(see~:~ J,.3V
r-~---'~--~-
OutputY
tpLH
R1
R3
IlL"~----;"",~ ~
1
0 - 15V
Sl
.
1•
1 1
il l+-
t8k
1'\.5O%1!.::.3~V::....
1
OutputZ
-:;
Output Z
1
tpHL
TEST CIRCUIT
~
-
--
1 "1.3V
fh3v
: 1 I+-
R2
(see Note A)
---l l+" tpHL
--{.-.I
OutputY
1
VOH
VOL
tsk
1
VOH
~.¥150%3V
1 (-:.....--- VOL
_ _+-1
-.I 14--
tPLH
VOLTAGE WAVEFORMS
Figure 2. Driver Test Circuit and Voltage Waveforms
R1
\------
Input'-!"
(8ee Note B)
::
R3
0 - 1.5V
S1
Differentia~
R2
(see Note A)
Output
1
1
10%
..!
-=-
14-1,
VOLTAGE WAVEFORMS
TEST CIRCUIT
Figure 3. Driver Test Circuit and Voltage Waveforms
~
~..:,1::::.3,,:,V_ _ _--'l6~,,-
Input DE
R1
OV
R3
tPL2
0-1.5V
Sl
R2
*-
~
3VOL+O.3V
I
tpHZ
(8ee Note A)
-+1
1 1
._-.._-w'r---O---
~
" ' VOL-O.3V
TEST CIRCUIT
OV
_ __
1.5V
,O.BV
I+--t-' - - - I~v__ _
VOL
tpZH
~
-=-
3V
i+- tpZL
: ~_
I
____
VOH
1.5V
VOLTAGE WAVEFORMS
Figure 4. Driver Test Circuit and Voltage Waveforms
NOTES: A. C1 - C3 includes probe and jig capacHance.
B. The input pulse is supplied by a generator having the following characteristics: PRR
1ExAs
=1 MHz, duty cycle =50%, tr =tf:< 6 ns.
,If
INSTRUMENTS
POST OFFICE BOX 655303 • DAUAS. TEXAS 75265
2-915
SN65C1167, SN65C1168, SN75C1167, SN75C1168
DUAL DIFFERENTIAL DRIVERS AND RECEIVERS
Su.s159-D4062,MARCH 1993
PARAMETER MEASUREMENT INFORMATION
VCC
S1
A Input
Device
Under
Blnput
Teet
T
CL=50pF
(see Note A)
VOLTAGE WAVEFORMS
TEST CIRCUIT
Figure 5. Receiver Test Circuit and Voltage Waveforms
Vcc
S1
RElnput
~1.3V
tpL2
RE Input -~......I.-...
VID=-2.5V{
or 2.5 V
Device
Under
Test
Output
~
UV\ - - - - - - -
I,.
0.5V
......,.-...... T
Output
J
14"1
tpZH
I
5O'l(,
1
,- ~I
~=+=
Y
...., -T+----~J·
0.5 V
lpzL. tPL2 Meesurement: S1 to VCC
tpZH. tpHZ Measurement: S1 to GND
VOLTAGE WAVEFORMS
TEST CIRCUIT
Figure 6. Receiver Test Circuit and Voltage Waveforms
NOTES: A. CL Includes probe and jig capackance.
B. The pulse a generator has the following characterislics: PRR " 1 MHz, 50% duty cycle, Ir
2-916
tpZL
I k""'"t----+-I-"""'lm--
-tp-HZ-~+-I
..J1 -f*-.CL=50pF
(see Note A)
~
1ExAs,lf
INSTRUMENTS
POST OFFICE BOX 655303 • DAUAS, TEXAS 75265
=tf" 6 ns.
::
VCC
VOL
VOH
--
GND
SN751177, SN751178
DUAL DIFFERENTIAL DRIVERS AND RECEIVERS
SLLS059A- 03381 FEBRUARY 1990 - REVISED JANUARY 1993
•
•
•
•
Meets CCITT Recommendations V.10, V.11,
X.26,X.27
Designed for Multipoint Bus Transmission
on Long Bus Lines in Noise Environments
16
Vcc
1A
10
1R
1Y
1Z
Driver Common-Mode Output Voltage
Range of-7Vto 12 V
•
Driver Positlve- and Negative-Current
Limiting
•
•
Thermal Shutdown Protection
•
Receiver Common-Mode Input Voltage
Range of -12 V to 12 V
•
•
•
Receiver Input Sensitivity •.• ±200 mV
•
Receiver 3-State Outputs Active-Low
Enable for SN751177 Only
•
SN751177 ••. N PACKAGE
(TOP VIEW)
Meets EIA Standards RS-422-A, RS485
DE
2Z
2Y
20
SN751178 ••• N OR Nst PACKAGE
(TOP VIEW)
Driver 3-State Outputs Active-High Enable
Vcc
10
1Y
1Z
20E
2Z
2Y
20
lOE
2R
Receiver Hysteresis ••. 50 mV Typ
Receiver High-Input-Impedance
12kQ Min
26
GNO
t The NS package is only available left-end taped and
reeled (order device SN751177NSLE).
Operates From Single 5-V Supply
Function Tables
description
The SN751177 and SN751178 dual differential
drivers and receivers are monolithic integrated
circuits that are designed for balanced multipoint
bus transmission at rates up to 10 Mbits per
second. They are designed to improve the
performance of full-duplex data communications
over long bus lines and meet EIA standards
RS-422-A, RS-485 and several CCITT
recommendations.
The SN751177 and SN751178 driver outputs
provide limiting for both positive and negative
currents and thermal shutdown protection from
line fault conditions on the transmission bus line.
SN751177, SN75117B
EACH DRIVER
ENABLE
DE
H
L
X
OUTPUTS
Y
Z
L
H
L
L
H
X
Z
Z
SN751177
EACH RECEIVER
DIFFERENTIAL INPUTS
A-B
VIO",0.2V
-0.2 V < VID < 0.2V
VIO",-0.2V
ENABLE
RE
H
OUTPUT
R
H
L
X
L
X
H
L
Z
H
X
Open
The receiver features high input impedance of
12 kQ, an input sensitivity of ±200 mV over a
common-mode input voltage range of -12 V to
12 V and typical input hysteresis of 50 mY.
Fail-safe design ensures that if the receiver inputs
are open, the receiver outputs will always be high.
The SN751177 and SN751178 are characterized
for operation from -20·C to 85·C.
INPUT
D
H
SN75117B
EACH RECEIVER
DIFFERENTIAL INPUTS
A-B
VID ",0.2V
-0.2 V < VID <0.2V
VIO",-0.2V
OUTPUT
R
H
?
L
H = high level. L = low level, ? = indeterminate,
X = irrelevant, Z = high impedance (off)
Copyright © 1993, Texas Instruments Incorporated
1ExAs ."
INSIRUMENTS
POST OFFICE BOX 655303 • PALLAS. TEXAS 75265
2-917
SN751177, SN751178
DUAL DIFFERENTIAL DRIVERS AND RECEIVERS
SLLS059A- 03381. FEBRUARY 1990 - REVISED JANUARY 1993
logic symbols t
logic diagrams (positive logic)
SN751177
DE
RE
12
,.
SN751177
ENl
4
I'-
DE
EN2
15
l>
10
1R
2D
14
1"7
13
1"7
§
3
"72
l>
9
10
2Z
2D
2A
Jf
12
EN
9
l>
14
"7
13
--..------41---1~----
15
14
1V
13
1V
1R
2D
1T
3
V2
t>
9
4[
2
A
10
1V
11
1v
2R
1T
5
V2
4[
1
6
A
7
1Y
14
1Z
1D
1A
2
1B
1R
2Y
1DE
1D
1R
2DE
2D
2R
EN
15
t>
V
13
V
3
1T
12
EN
9
t>
4[
2
A
10
V
11
V
5
1T
4[
1
6
A
7
6
2B
7
1Y
SN75ALS1178
4
1Z
1DE -~--"'I-
1A
1D
1B
14
~>--_ _1_3_
2
2Y
1R
2Z
2A
2DE
2B
2D
2R
~_ __
9
N....I-
EQUIVALENT OF DRIVER OR ENABLE INPUT
~>--_ _1_1_
6
EQUIVALENT OF RECEIVER INPUT
1.7kQ
NOM
17kQ
NOM
Input -~t-JV'o.IIr----'
288 kQ
NOM
--1-.7-k-Q--+-NOM
VCC(A)
or
GND(B)
G N D - - - - - -__-~-~
1ExAs
..If
INSIRUMENTS
POST OFFICE BOX 655303 • DAUAS, TEXAS 7526~
1Z
1A
1B
:
~___7_:
VCC------.---~.-
Input
1Y
10
equivalent schematics
2-926
1A
11
2D
2A
tThese symbols are in accordance with ANSI/IEEE SId 91-1984
and lEe Publication 617-12.
VCC - - - - . , - -
1Z
1B
2R
14
1Y
10
2Z
SN75ALS1178
4
13
SN7SALS1177, SN1SALS1178
DUAL DIFFERENTIAL DRIVERS AND RECEIVERS
SUS154-D4061, MARCH 1993
schematics of outputs
TYPICAL OF DRIVER OUTPUTS
TYPICAL OF RECEIVER OUTPUTS
Vcc
Output
GND
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vc~see Note 1) ............................................................. 7 V
Input voltage, DE, RE, and D inputs ........................................................... 7 V
Output voltage range, Driver ........................................................ -9 V to 14 V
Input voltage range, Receiver ...................................................... -14 V to 14 V
Receiver differential input voltage range (see Note 2) .................................. -14 V to 14 V
Receiver low-level output current .......................................................... 50 rnA
Continuous total power dissipation ..................................... See Dissipation Rating Table
Operating free-air temperature range, TA .............................................. O'C to 70'C
Storage temperature range ....................................................... -65'C to 150'C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds ............................... 260'C
NOTES: 1. All vottage values, excepi differential input voltage, are with respect to the network ground terminal.
2. Differential input voltage Is measured at the noninverting terminal with respect to the Inverting terminal.
DISSIPATION RATING TABLE
PACKAGE
TA ,. 25°C
POWER RATING
OPERATING FACTOR
ABOVE TA =25·C
TA = 70·C
POWER RATING
N
1150 mW
9.2 mWrc
736 mW
NS
625 mW
4.0 mwrc
445 mW
. TEXAS,If
INSIRUMENI'S
POST OFFICE BOX 655303 • DAUAS. TEXAS 75265
2-927
SN75ALS1177, SN75ALS1178
DUAL DIFFERENTIAL DRIVERS AND RECEIVERS
SLLSl54-D4061, MARCH 1993
recommended operating conditions
Supply voltage, VCC
>
Differential input voltage, VID
Receiver
Common-mode output voltage, Voc
Driver
Common-mode Input voltage, VIC
Receiver
High-level Input voltage, VIH
DE,RE,D
Low-level input voltage, VIL
DE, RE,D
High-level output current, IOH
Low-level output current, IOL
MIN
NOM
MAX
UNIT
4.75
5
5.25
",12
V
12
",12
V
-7t
Receiver
Receiver
rnA
-400
t!A
8
Operating free-alr temperature, TA
0
V
0.8
-60
60
Driver
V
V
2
Driver
V
70
rnA
·C
.. (more negative) limit Is designated as minimum, Is used In thIS data sheet for common-mode
t The algebraiC convention, where the less posRlve
output and threshold voltage level only.
1ExAs
~
INSIRlJMENTS
2-928
POST OFFICE BOX 6515303 • DALlAS, TEXAS 75265
SN75ALS1177, SN75ALS1178
DUAL DIFFERENTIAL DRIVERS AND RECEIVERS
SLLS154-D4061, MARCH 1993
DRIVER SECTION
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
PARAMETER
TYpt
MIN
TEST CONDITIONS
VIK
Input clamp voltage
11=-18mA
VOH
High-level output vo~age
VIH =2V,
VIL= 0.8 V,
IOH=-33mA
3.3
VOL
Low-level output voltage
VIH=2V,
VIL=0.8V,
10L= 33 rnA
1.1
IV ODll
Differential output voltage
10=0
Differential output voltage
VCC=5V,
RL= 1000
IV OD21
JVOD31
Differential output vo~age
lI.JVoDI
Change In magnitude of differential
output voltage (see Note 4)
1.5
MAX
UNIT
-1.5
V
V
V
6
See Figure 1
2
V
RL=540
1.5
5
See Note 3
1.5
5
V
,00.2
V
VOC
Common-mode output voltage
lI.lVocl
Change in magnitude of common-mode
output voltage (see Note 4)
10(OFF)
Output current with power off
VCC=O,
10Z
High-impedance-state output current
VO=-7Vto12V
IIH
High-level input current
VIH=2.7V
100
IlL
Low-level input current
VIL=0.4V
-100
VO=-7V
-250
VO=VCC
250
VO= 12V
250
lOS
Short-circuit output current
RL=5400rl000,
See Figure 1
-1*
VO=-7Vto 12V
Supply current (total package)
No load
3
V
,00.2
V
,0100
t1A
t1A
t1A
t1A
,0100
rnA
150
VO=OV
ICC
V
1/2VODl
Outputs enabled
35
50
Outputs disabled
20
50
rnA
t All typical values are at VCC = 5 V and TA = 25'C.
:I; The algebraic convention, where the less positive (more negative) limit is designated as minimum, is used in this data sheet for common-mode
output and threshold vo~age levels only.
NOTES: 3. See EIA Standard RS-485 Figure 3.5, test termination measurement 2.
4. lI.lVODI and lI.JVocl are the changes in magnitude ofVOD and VOC, respectively, that occur when the input is changed from a high
level to a low level.
switching characteristics at Vee
=5 V, TA =25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
9
15
22
ns
9
15
22
\ ns
2
8
ns
35
50
ns
15
25
ns
7
15
30
ns
7
15
30
ns
tpLH
Propagation delay time, high-to-Iow-Ieveloutput
tpHL
Propagation delay time, low-to-high-Ievel output
tsk
Output-to-output skew
0
tpZH
Output enable time to high level
CL= 100pF,
See Figure 4
30
tpZL
Output enable time to low level
CL= 100pF,
See Figure 5
5
tpHZ
Output disable time from high level
CL= 15 pF,
See Figure 4
tpLZ
Output disable time from low level
CL = 15 pF,
See Figure 5
RL=600,
See Figure 3
1ExAs
CLl
=CL2
= 100 pF,
UNIT
~
INSIRUMENIS
POST OFFICE BOX 855303 • DALLAS, TEXAS 7 _
2-929
SN75ALS1177, SN75ALS1178
DUAL DIFFERENTIAL DRIVERS AND RECEIVERS
SLLS154-D4061. MARCH 1993
RECEIVER SECTION
electrical characteristics over recommended ranges of common-mode input voltage, supply
voltage, and operating free-air temperature (unless otherwise noted)
TEST CONDITIONS
PARAMETER
Vr+
Vr-
Positive-going threshold voltage
VO=2.7V,
10 =-0.4 mA
Negative-going threshold voltage
Vo = 0.5 V,
10=8mA
Vhys
Input hysteresis (\IT+ -
VIK
Enable input clamp voltage
MIN
TYpt
MAX
0.2
-0.2:1:
Vr~
VOH
High-level output voltage
VOL
Low-level output voltage
VID = 200 mV,
See Figure 2
10Z
High-impedance-state output current
, SN75ALS1177
mV
-1.5
II =-18 mA
VID = 200 mV,
See Figure 2
10H = -400 !lA.
IOL=8mA.
V
V
50
I SN75ALS1177
UNIT
2.7
V
V
Vo = 0.4 Vto 2.4 V
0.45
V
.. 20
!lA
1
IVI = 12V
Other input at 0 V ,.
VI=-7V
mA
II
Un" input current (see Note 5)
IIH
High-level Input current, RE
1SN75ALS1177
VIH=2.7V
20
j.iA
IlL
Low-level input current, RE
, SN75ALS1177
VIL=0.4V
-100
!lA
-85
mA
50
mA
Ii
Input resistance
lOS
Short-circuit output current
VO=OV,
See Note 6
ICC
Supply current (total package)
No load,
Outputs enabled
-0.8
kQ
12
-15
35
tAil typtcal values are at VCC = 5 V and TA = 25°C.
'
:I: The algebraic convention, where the less positive (more negative) limit Is designated as minimum, Is used In this data sheet for common-mode
output and threshold voltage levels only.
NOTES: 5. Refer to EIA standards RS-422-A, RS-423-A, RS-485-A for exact conditions.
6. Not more than one output should be shorted at a time.
switching characteristics at Vee
=5 V, TA =25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
tpLH
Propagation delay time, low-to-hlgh-Ievel output
tpHL
Propagation delay time, hlgh-to-Iow-Ievel output
tpZH
Output enable time to high level
MIN
TYP
MAX
15
25
37
UNIT
15
25
37
ns
ns
CL=15pF.
See Figure 6
SN75ALS1177
CL=100pF,
See Figure 7
10
20
30
ns
tpZL
Output enable time to low level
SN75ALS1177
CL= 100pF,
See Figure 7
10
20
30
ns
tpHZ
Output disable time from high level
SN75ALS1177
CL=15pF,
See Figure 7
5
12
16
ns
tpLZ
Output disable time from low level
SN75ALS1177
CL=15pF,
See Figure 7
5
12
16
ns
2-$30
POST OFFICE BOX 8S5303 • DALlAS. TEXAS 75265
SN75ALS1177, SN75ALS1178
DUAL DIFFERENTIAL DRIVERS AND RECEIVERS
SLLSl54-D4061, MARCH 1993
PARAMETER MEASUREMENT INFORMATION
Figure 1. Driver Test Circuit, Voo and
Voe
Figure 2. Receiver Test Circuit, VOH and VOL
CL1 = 100 pF
(see Note B)
Generator
(see Note A)
CL2= l00pF
(see Note B)
DRIVER TEST CIRCUIT
DRIVER VOLTAGE WAVEFORMS
Figure 3. Driver Propagation Delay Times
Output
Sl
3VorOV
Generator
(see Note A)
DRIVER VOLTAGE WAVEFORMS
DRIVER TEST CIRCUIT
Figure 4. Driver Enable and Disable Times
NOTES: A. The pulse generalor has the following characteristics: PRR s 1 MHz, 50% duly cycle, Ir s 10 ns, If s 10 ns.
B. CL includes probe and jig capacHance.
1ExAs
~
INSIRlJMENTS
POST OFFICE BOX 655303 • DAUAS, TEXAS 75265
2-931
SN75ALS1177, SN75ALS1178
DUAL DIFFERENTIAL DRIVERS AND RECEIVERS
SLLSl54-D4061. MARCH 1993
PARAMETER MEASUREMENT INFORMATION
VCC
tpZL ~
CL
(see Note B)
Generator
(see Note A)
}~5~---- ::
Input-Juv
S1
T
I
~
/+I
14- tpLZ
I
O,SV
Output,-;.;V-----t--- j
.
. ---f
DRIVER VOLTAGE WAVEFORMS
DRIVER TEST CIRCUIT
Figure 5, Driver Enable and Disable Times
Generator
(see Note A)
1 kD
Vec
1N916 or
Equivalent
oV (SN75ALS1177 only)
RECEIVER TEST CIRCUIT
~
Input
~-------- ~5V
~
},-O_V________,.,( "_ _ _ _ _
tpHL ~
Output
14--""'\ I
\
1,5V
~
14I
r--11'~__
-2.5 V
tpLH
VOH
VOL
DRIVER VOLTAGE WAVEFORMS
Figure 6, Receiver Propagation Delay Times
NOTES: A. The pulse generator has Ihe following characteristics: PRR s 1 MHz. 50% duty cycle. Irs 10 ns. Ifs 10 ns.
B. CL Includes probe and jig capacitance.
1ExAs,lf
INSlRUMENTS
2-932
POST OFFICE BOX 655303 • DALlAS. TEXAS 75265
- ov
VOL
SN75ALS1177, SN75ALS1178
DUAL DIFFERENTIAL DRIVERS AND RECEIVERS
SLLS154-D4061, MARCH 1993
PARAMETER MEASUREMENT INFORMATION
Sl
Output
1.5V
52.
lN916or
Equivalent
Generator
(see Note A)
RECEIVER TEST CIRCUIT
----~
Input
3V
1.5_V..,t_ _ _ _ _ _ _ _ 0 V
1.5 V )."'_______________
Sl to-l.5V
1
S2 Cloaed tpZL ~
S3 Closed
1
Sl to-l.5V
S2 Closed
S3 Closed
i+1
1
tpLZ ~
1
*-1
05 V
',_
i '{l~;--------Tt------L-
Output
S1tol.5V
1
S2 Open tpZH ~
S3Closed
1
1
-----f--
VOL
j+1
1
I
___ .I _ _ _
VOH
11.5
--------'.
5V
1
V
--
1 .~---=.Sltol.5V _ _ _
52 Open tpHZ ~
j+S3 Cloaed
0.5 V
+_1 ___ ; ____ ov
RECEIVER VOLTAGE WAVEFORMS
NOTES: A. The pulse generator has the foliowing characteristics: PRR" 1 MHz, 50% duty cycle, tr" 10 ns, tf" 10 ns.
B. CL Includes probe and jig capacHance.
Figure 7. Receiver Output Enable and Disable Times
1ExAs
~
INSIRUMENTS
POST OFFICE BOX 655303 • DAUAS, TEXAS 75265
2-a33
2-$34
SN65C1406,SN75C1406
TRIPLE LOW-POWER DRIVERS/RECEIVERS
• Meets Standard EIA-232-D (Revision of
RS-232-C)
D, DW, OR N PACKAGE
(TOP VIEW)
• Very Low Power Consumption ••• 5 mW
Typ
Voo ~
• Receiver Input Hysteresis ••• 1000 mV Typ
1RA[
1DY~
2RA
2DY
3RA
3DY
• PUSh-Pull Receiver Outputs
Vss
• Wide Driver Supply Voltage. • .z4.5 V
to:t15V
• Driver Output Slew Rate Umlted to 30 VIlIS
Max
• On-Chlp Receiver 1-11S Noise Filter
• Functionally Interchangeable With Motorola
MC145406
The SN65C1406 and SN75C1406 are low-power
BI-MOS devices containing three independent
drivers and receivers that are used to interface
data terminal equipment (DTE) with data
circuit-terminating equipment (DCE). This device
is designed to conform to Standards ANSII
EIA-232-D-1986 (which supersedes RS-232-C).
The drivers and receivers of the SN65C1406 and
SN75C1406 are similar to those of the SN75C188
quadruple driver and SN75C189A quadruple
receiver, respectively. The drivers have a
controlled output slew rate that is limited to a
maximum of 30 VlIJ$ and the receivers have filters
that reject input noise pulses of shorter than 1 IJ$.
Both these features eliminate the need for
external components.
U
5
6
7
8
16
15
14
13
12
11
10
9
Vee
1RY
1DA
2RY
2DA
3RY
3DA
GND
logic eymbol t
1RA 2
description
1
2
3
4
2RA
3RA
1RY
2RY
11
3RY
14
1DA
13
4
8
1DY 3
2DY 5
3DY
15
.IT
V4
1R
1A
1B
19 1A}
20
Bus
.....r:H"'--1B
2DE
1
2D
C>
15
2A
2B
2R
: : 2A} Bue
~"""'--2B
V4
12
11
9
20
14
8
6
RE
EN4
3
1R
2D
G5
5EN1
C>
13
3DE
3A
3D
3B
V4
3R
~
......-_::_::} Bus
t This symbol Is In accordance with ANSVIEEE Std 91-1984 and
lEO Publication 617-12.
schematics of inputs and outputs
EQUIVALENT OF EACH INPUT
V C C - - -....
TYPICAL OF A AND B
VO PORTS
TYPICAL OF RECEIVER OUTPUT
--~-------.--~~-VCC
VCC
700
Input
17kO
288kQ
1.7kO
1.7kO
--~----+--~-~~~- GND
Input/Output Port
All values are nominal.
2--944
1ExAs"
INSIRUMENTS
POST OFFICE BOX 6&5303 • DAUAS. TEXAS 7S265
Output
SN75ALS1711
TRIPLE DIFFERENTIAL BUS TRANSCEIVER
SLLS117A-D3848,APRIL 1991-REVISED FEBRUARY 1993
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, Vee (see Note 1) .............................................. -0.5 Vto 7 V
Enable input voltage range .................................................. -0.5 V to Vee + 0.5 V
Input voltage range, VI: Driver ............................................... -0.5 V to Vee + 0.5 V
Receiver .................................................... -9 V to 14 V
Output voltage range, VO: Driver .................................................... -9 V to 14 V
Receiver .......................................... -0.5 V to Vee + 0.5 V
Continuous total power dissipation ..................................... See Dissipation Rating Table
Operating free-air temperature range .................................................. O·C to 70·C
Storage temperature range ....................................................... -65·C to 150·C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds ............................... 260·C
NOTE 1: All voltage values, except differential input/output bus voltage, are with respect to network ground terminal.
DISSIPATION RATING TABLE
PACKAGE
TA,,25°C
POWERRAnNG
OW
N
=
DERATING FACTOR
ABOVE TA 25°C
TA 70°C
POWER RATING
1125mW
9.0mWrC
720mW
1150mW
9.2mWrC
736mW
=
recommended operating conditions
UNIT
MIN
TYP
MAX
Supply voltage, VCC
4.75
5
5.25
V
Common-mode Input voltage at any bus terminal, VIC (see Note 2)
-7t
12
V
High-level Input voltage, VIH
0, DE, RE, CDE
Low-level input voltage, V,L
0, DE, RE, COE
High-level output current, IOH
Low-level output current, IOl
Driver
Receiver
0.8
V
-60
rnA
-400
tJA
60
Driver
8
Receiver
Operating free-alr temperature, TA
V
2
0
70
rnA
°c
t
The algebraic convention, in which the less-positive (more-negative) limit is designated minimum, is used in this data sheet for common-mode
input voltage and threshold voltage levels only.
NOTE 2: DiffI!rential-inpul/output bus voltage is measured at the noninverting terminal A with respect to the inverting terminal B.
TEXAS ~
INSIRUMENTS
POST OFFICE BOX 655303 • DALlAS, TEXAS 75265
2-945
SN75AL$1711
TRIPLE DIFFERENTIAL BUS TRANSCEIVER
S1..LS117A- D3848,APRILl991- REVISED FEBRUARY 1993
DRIVER SECTION
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYPt
MAX
UNIT
-1.5
V
6
V
1.5
5
V
1.5
5
V
1.5
5
V
See Figure 1
",0.2
V
RL=54Q,
See Figure 1
3
-1
V
Change In magnitude of common-mode output
voltage*
RL=54Q,
See Figure 1
",0.2
V
10Z
High-impedance state output current
Output disabled,
Vee = 5.25 V
VIK
Input clamp voltage
11=-18mA
Vo
Output voltage
10=0
VODl
Differential output voltage
10=0
VOD2
Differential output voltage
RL=54Q,
VOD3
Differential output voltage
See Note 3 and Figure 2
AIVODI
Change In magnitude of differential output voltage*
RL=54Q,
VOC
Common-mode output voltage
AIVocl
°
See Figure 1
IVO=12V
1
I VO=7V
-0.8
IIH
High-level input current, DE, EN, CDE
VIH=2.4V
20
IlL
Low-level Input current, DE, EN, CDE
VIL=0.4V
-200
Short-cIrcuit output current
VO=12V
-250
lOS
ICC
Supply current
250
VO=7V
No load
I Outputs enabled
48
72
I Outputs disabled
30
48
rnA
JlA
JlA
rnA
rnA
t All typical values are at VCC = 5 V and TA = 25°e.
* A IV 001 and A IV oci are the changes In magnitude ofVOD and Voe, respectively, that occur when the Input Is changed from a high level to a low
level.
NOTE 3: This applies for both power on and off; refer to EIA Standard RS-485 for exact conditions.
switching characteristics, Vee
=5 V ±5%, TA =25°C
PARAMETER
TEST CONDITIONS
IpLH
Differential propagation delay time, low-Io-hlgh level output
IpHL
Differential propagation delay time, high-Io-Iow level output
IpZH
Output enable time to high level
tpHZ
Output disable time from high level
tPZL
Output enable time to low level
tpLZ
Output disable time from low level
RL=54Q,
See Figure 3
RL=110a.
See Figure 4
1ExAs
.Jf
INSTRUMENTS
2-946
POST OFACE BOX 655303 • DAUAS, TEXAS 75265
MIN
TYP
MAX
8
13
22
8
15
22
Slopen,
S2closed
30
50
60
4
16
30
Sl closed,
S20pen
16
26
45
4
8
20
CL= 100 pF,
UNit
ns
ns
SN75ALS1711
TRIPLE DIFFERENTIAL BUS TRANSCEIVER
SLLSl17A- 03848, APRIL 1991 - REVISED FEBRUARY 1993
RECEIVER SECTION
electrical characteristics over recommended ranges of common-mode input voltage, supply
voltage, and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VT+
Positive-going threshold voltage
Vo = 2.7 V,
10 =-0.4 rnA
Vr-
Negative-going threshold voltage
Vo = 0.5 V,
10=4mA
Vhys
Hysteresis (\IT + -
VIK
Input clamp voltage, RE
11=18mA
VOH
High-level output voltage
IOH=-0.4mA
VOL
loW-level output voltage
IOL=4mA
10Z
High-impedance-state output current
Vee = 5.25 V,
II
Une Input current
MIN
TYPT
MAX
0.2
50
Other Input at 0 V,
See Note 3
mV
-1.5
V
0.5
V
V
2.4
",20
VO=0.4Vt02.4V
IVI
=12V
1
-0.8
IVI=7V
IIH
High-level input current, RE
VIH =2.4V
20
IlL
Low-level input current, RE
VIL=0.4V
-200
rJ
Input resistance
lOS
Short-circuit output current§
ICC
Supply current
-15
No load
J.&A
rnA
J.&A
J.&A
kQ
12
VO=O
V
V
-0.2*
Vr. . )
UNIT
-130
I Outputs enabled
48
72
I Outputs disabled
30
48
rnA
rnA
t All typical values are at Vee = 5 V and TA = 25°C.
:I: The algebraic convention, in which the less-positive (more-negative) limit is designated minimum, is used In this data sheet for common-mode
input voltage and threshold voltage levels only.
§ Not more than one output should be shorted at one time.
NOTE 3: This applies for both power on and off; refer to EIA Standard RS-485 for exact conditions.
switching characteristics, Vee = 5 V ±5%, TA = 25~C
PARAMETER
TEST CONDITIONS
tpLH
Propagation delay time, low-to-high-Ievel output
tPHL
Propagation delay time, high-to-Iow-Ievel output
tpZH
Output enable time to high level
tPHZ
Output disable time from high level
tPZL
Output enable time to low level
tpZL
Output enable time to low level
See Figures 5 and 6
See Figures 5 amd 7
MIN
TYP
MAX
13
20
37
13
20
37
Sl to 1.5V,
S20pen,
S3closed
3
9
20
8
15
22
Sl to-l.5V,
S2 closed,
S30pen
5
10
20
5
9
16
UNIT
ns
ns
1ExAs . "
INSIRUMENTS
POST OFFICE BOX 655303 • DAlLAS, TEXAS 75265
2~47
SN75ALS1711
TRIPLE DIFFERENTIAL BUS TRANSCEIVER
SLLS117A-D3848,APRIL 1991-REVISED FEBRUARY 1993
PARAMETER MEASUREMENT INFORMATION
37SD
Figure 1. DriverVOD and Voe
Figure 2. Driver VOD3
--3V
Input
~
1.5 V
1.5V
tpLH
-+!
I+-
_V~
I
Generator
<_NoteA)
Output B
VOOM
Output A
*i_V-
--+I
OV
14- tpHL
VOH
-
VOL
Figure 3. Driver Propagation Delay Times
Input
(_NoteaAandC)J.1.SV
3V
1 . 5 V ) , - - - - - - OV
It- tpZL --'
From Output
Under Teet
CL=50pF
<_Note B)
RL .110 D
T_
O=~~
(a..
Outputz
(_ Note D)
tpLZ
I S1 Cloeed I
I S2 Open I
I t - - - .SV
I
\,UV
j.. tpZH -tt
S10pen
S2 Cloaed ,
I
tpHZ
2.3 V .0 V
~
1-
I
I
I
- 'I
S1 Cloaed
S2 Open
Ir-r-
f-.=-_~
VOL
1f--!-~
VOH
~0.5 V f" 0.5 V
S10pen
S2 Closed
FIgure 4. Driver Enable/Dlsable Times
NOTES: A.
B.
C.
D.
All Input pulses are supplied by generators having the following characteristics: PRR 0: 1 MHz, Zo. 50 Do tr 0: 10 ns, If 0: 10 ns.
CL Includes probe and Jig capacitance.
Each enable Is tested separately.
Output 1 and output 2 are outputs with intemal conditions such thatthe output is low or high except when disabled by the output control.
1ExAs
..If
INSIRUMENTS
2-948
POST OFFICE BOX _
• DAIJ.AS, TEXAS 711286
SN75ALS1711
TRIPLE DIFFERENTIAL BUS TRANSCEIVER
Su.sl17A-D3848.APRIL 1991-REVISED FEBRUARY 1993
PARAMETER MEASUREMENT INFORMATION
--3V
~
1.SV
1.SV
2kO
Generator
(saeNoteA)
Input
I
CL=1SpF
(see Note B)
T
tpLH
1N916 or
Equivalent
SkO
output
'--_ _"
-.I
I
14I
-.I
0
14- tpHL
I
+-VOH
1.3 V
VOL
1.3 V
~
Figure 5. Receiver Propagation Delay Times
1.SV
51
S2
2kO
0 - - SV
-1.SV ---0
-:
Generator
(.eeNoteA)
CL,,1SpF
, (see Note B)
T
1N916or
Equivalent
SkO
500
1~
-:
Input~ 1.SV
1.SV
:;:~S~
tpL2~1
~~~I
Output --+--":'_"'t- - - - S V
Output
~,.:_-_-_-:_-_-_-_
I
. 1.5 V
14- 'PZH ~
51 at1.SV I
I
I
51at-1.5V
I ~g~
I
-V
r--.
OL
0.5 V L 0.5 V
I
520pen ~
53CIOSedl.2·!.V_ -OV
:V
.i
\["_~--
V
~
OH
51 at1.5V
S20pen
S3Closed
Figure 6. Receiver Enable/Disable nmes
NOTES: A. All Input pulses are supplied by generators having the following characteristics: PRR" 1 MHz, Zo
B. CL includes probe and jig capacKance.
1ExAs
=50 0, tr " 10 ns, tf" 10 ns.
..If
INSIRUMENfS
POST OFFICE BOX 655303 • DAlLAS. TEXAS 75265
2-949
2-950
SN751730
TRIPLE LINE DRIVER/RECEIVER
1991
•
•
•
•
•
•
•
Meets IBM 360/370 Input/Output Interface
Specification for 4.5 Mb/s Operation
Single 5-V Supply
Uncommited Emmitter-Follower Output
Structure for Party-Line Operation
Driver Output Short-Circuit Protection
Driver Input/Receiver Output Compatible
With TTL
Receiver Input Resistance •.• 7.4 kQ
to 20 kQ
Ratio Specification for Propagation Delay
Time, Low-to-Hlgh/Hlgh-to-Low
o OR N PACKAGE
(TOP VIEW)
vee
OE1
RI1
ROl
RI2
R02
RI3
R03
GNO
001
011
002
012
003
013
OE2
6
9
Function Tables
EACH DRIVER
description
INPUTS
The SN751730 triple line driver/receiver is
specifically deSigned to meet the input/output
interface specifications for IBM System 360/370.
It is also compatible with standard TTL logiC and
supply voltage levels.
01
All the driver inputs and receiver outputs are in
conventional TTL configuration and the gating can
be used during power-up and power-down
sequences to ensure that no noise is introduced to
the line, by pulling either DE1 or DE2 to a low level.
L
X
X
0E2
X
X
L
L
L
L
H
H
H
H
EACH RECEIVER
The low-impedance emitter-follower driver
outputs of the SN751730 will drive terminated
lines such as coaxial cable or twisted pair. Having
the outputs uncommitted allows wired-OR logiC to
be performed in party-line applications. Output
short-circuit protection is provided by an internal
clamping network that turns on when the output
voltage drops below approximately 2.5 V.
An open line will affect the receiver input as would
a low-level input voltage.
OUTPUT
DO
DEl
X
L
X
INPUT OUTPUT
RI
RO
H
L
H
L
Open
H
H =high level. L
=low level.
X =irrelevant
logic symbols t
DRIVER
DEl
OE2
Do~
011
012
013
15
12
13
10
11
001
002
003
RECEIVER
RI1
2
RI2
RI3
Do
4
ROl
R02
6
R03
t These symbols are in accordance with ANSI/lEE SId 91-1984
and lEe Publication 617-12.
Copyright © 1991. Texas Instruments Incorporated
TEXAS'"
INSIRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2-951
SN751730
TRIPLE LINE DRIVER/RECEIVER
SUS062A- D3494, MAY 1990- REVISED JANUARY 1991
logic diagrams (positive logic)
RECEIVER
DRIVER
DE1
DI1 14
D01
DI2 12
D02
DI3 10
003
DE2
RI1
RI2
RI3
9
~
~
~
R01
R02
R03
equivalent schematics of driver and receivert
DRIVER
Vee
2.50
DO
DI
DE1
DE2--t-l-"
RECEIVER
VCC
6kO
RO
RI
14kO
t All resistor values are nominal.
2-952
1ExAs'"
INSlRUMENTS
POST OFFice BOX 855303 • DAUAS, TexAS 75265
SN751730
TRIPLE LINE DRIVER/RECEIVER
sL.LS~-
03494, MAY 1990-REVISED JANUARY 1991
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) ............................................................. 7 V
Input voltage range, VI: Driver ....................................................... -0.5 V to 7 V
Receiver ..................................................... -0.5 V to 7 V
Output voltage range, Va: Driver ..................................................... -0.5 V to 7 V
Enable input voltage range .......................................................... -0.5 V to 7 V
Continuous total power dissipation ..................................... See Dissipation Rating Table
Operating free-air temperature range, TA .............................................. O°C to 70°C
Storage temperature range ....................................................... -65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds ............................... 260°C
NOTE 1: All voRage values are with respect to network ground terminal.
DISSIPATION RATING TABLE
PACKAGE
D
N
TA",25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
TA=70°C
POWER RATING
950mV
7.6mwre
60SmW
1150mV
9.2mWre
736mW
recommended operating conditions
Supply voltage, Vee
High-level input voltage, VIH
Low-Ievei input voltage, VIL
Driver, Enable
MIN
NOM
'MAX
UNIT
4.75
5
5.25
V
2
Receiver
V
1.55
Driver, Enable
O.S
Receiver
1.15
Operating free-air temperature, TA
0
TEXAS
70
V
·C
~
INSIRUMENIS
POST OFFICE BOX 6S5303 • DAllAS, TEXAS 75265
2-953
SN751730
TRIPLE LINE DRIVER/RECEIVER
Su.s062A- D3494, MAY 1990- REVISED JANUARY 1991
DRIVER SECTION
electrical characteristics over recommended ranges of supply voltage and operating free air
temperature (unless otherwise noted)
PARAMETER
VIK
VOH
VODH
VOL
TEST CONOmONS
Input clamp voltage
High-level output voltage
VCC = 4.75 V,
IIL=-18mA
VCC = 4.75 V,
10H = -59.3 mA
VIH=2V,
TA=25°C
VCC = 5.25 V,
IOH=-78.1 mA
VIH=2V,
VCC = 4.75 V,
RL=51.4Q
VIH=2V,
VCC = 5.25 V,
RL=56.9Q
VIH=2V,
MIN
MAX
UNIT
-1.5
V
3.11
4.10
V
3.05
4.20
Differential high-level output voltage
RL = 46.3 Q or 56.9 Q
10L = -0.24 rnA
0.15
Low-level output voltage
VCC=5.25V,
VIL=0.8V,
VIH=4.5V
RL=56.9Q
0.15
VCC = 5.25 V,
VIH=2.7V
VCC = 5.25 V,
VIH=0.4V
VCC=4.75V,
VOH=5V
VIL=O
100
VIH=4.5V
100
VIH=4.5V
-30
IIH
High-level input current
IlL
Low-level Input current
IOH
High-level output current
lOS
Short-circuit output currentt
01
DE
01
DE
VCC=5.25V
ICCH
VCC=5.25V,
No load
Supply current (total package)
ICCL
0.50
V
V
20
60
-400
-1200
VI(D) = 4.5 V,
VI(R)=0
47
VI (D) =0,
VI(R) =4.5V
80
fAA
fAA
fAA
mA
mA
t No more than one output should be shorted at a time, and duration of the short circuit should not exceed one second.
switching characteristics, Vce = 5 V:t5%, TA = 25°C
PARAMETER
TEST CONomONS
tPLH
Propagation delay time, iow-to-high level output
tPHL
Propagation delay time, high-to-low level output
AIpd
Differential propagation delay time:!:
It-
Output rise time
tf
Output fall time
SR
Slew rate
See Figure 1
VCC=5V,
RL=47.5Q,
See Figure 1
Vo = 0.15 Vto 3.05 V.
CL = 10.2 pF,
Vo = 1 V to 3 V average,
RL=47.5Q,
CL= 10.2pF,
See Figure 1
1ExAs
.Jf
INSIRUMENIS
2'-S54
,
RL=47.5Q,
POST OFFICE sox 665303 • DAUAS, TEXAS 7526S
MIN
TYP
MAX
UNIT
6.5
12
18.5
6.5
12
18.5
os
os
10
ns
5
10
os
5
13
ns
0.65
V/ns
SN751730
TRIPLE LINE DRIVER/RECEIVER
SLLS062A- 03494, MAY 1990 - REVISED JANUARY 1991
RECEIVER SECTION
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MAX
VOH
High-level output voltage
Low-level output voltage
VCC=4.75V,
VIH = 1.55V
IOL=8mA
0.5
VOL
IOL=4mA
0.4
I'j
Input resistance
VCC=O,
VI =0.15Vto 3.9V
IIH
High-level input current
VCC = 4.75 V,
VIH =3.11 V
IlL
Low-level input current
VCC = 5.25 V,
VIL=0.15V
lost
Short-clrcuH output current
VCC = 5.25 V,
VIL=O
ICCH
VCC = 5.25 V,
No load
I - - - Supply current (total package)
ICCL
VI=1.15V,
MIN
VCC = 4.75 V,
IOH = -400 JAA
2.7
7.4
UNIT
V
V
20
kg
0.42
mA
-0.24
0.04
mA
-20
-100
mA
VI(D) = 4.5 V.
VI(R) =0
47
VI(D) =0,
VI(R) =4.5V
80
mA
t Only one output should be shorted at a time, and duration of the short circuit should not exceed one second.
switching characteristics, Vee
=5 V ±5%, TA =25°C
PARAMETER
TEST CONDITIONS
tpLH
Propagation delay time, low-to-hlgh level output
tpHL
Propagation delay time, high-te-Iow level output
Atpd*
Differential propagation delay time
RL=2kg,
CL=15pF,
TEXAS
See Figure 2
UNIT
MIN
TYP
MAX
7.5
12
19.5
ns
7.5
12
19.5
ns
10
ns
~
INSIRlJMENTS
POST OFFICE BOX 855303 • DAlLAS, TEXAS 75265
2-955
SN751730
TRIPLE LINE DRIVER/RECEIVER
SLLS062A- 03494, MAY 1990 - REVISED JANUARY 1991
PARAMETER MEASUREMENT INFORMATION
VCC-SV
Input
~,3V
J~
tpLH
Pulae
Generator
(aeeNoaA)
~
I
~,~V---tw
l---tt-
::
tpHL
I
I---~ 13,05V-- VOH
Output
TEST CIRCUIT
VOLTAGE WAVEFORMS
NOTES: A. The pulse generator has the following characteristics: Zo - 50 0, tw " 500 ns, PRR " 1 MHz, t, " 6 ns, tr " 15 ns.
B. CL includes probe and jig capacitanca.
Figure 1. Driver Test Circuit and Voltage Waveforms
VCC=5V
RL=2kO
Output
Pulae
Generator
(aaeNomA)
\1.4V---
~~
I
tpLH
1N3064X2
I
Output
TEST CIRCUIT
1.3V
VOLTAGE WAVEFORMS
NOTES: A. The pulse generator has the following characteristics: Zo - 50 0, tw " 500 ns, PRR " 1 MHz, tf " 10 ns, tr " 10 ns.
B. CL Includes probe and Jig capacitance.
Figure 2. Receiver Test Circuit and Voltge Waveforms
1ExAs
..If
INSIRUMENTS
2-Q56
POST OFFICE aox _
• DALlAS, TEXAS 7S26&
3V
ov
VOH
SN75LV4735
3.3-V MULTICHANNEL RS232 LINE DRIVER/RECEIVER
FEBRUARY 1992-REVISEDAPRIL 1993
SlLS135B-
•
Meets ANSI/EIA-232-D, 1986 Specifications
(Revision of EIA Standard RS-232-C)
DB PACKAGE
(TOP VIEW)
•
•
Operates With Single 3.3-V Power Supply
LinBICMOS™ Process Technology
C2+
•
Three Drivers and Five Receivers
VCC
•
•
±3G-V Input Levels (Receiver)
Voo
C2-
1
C3+
GND
C3-
4
Vss
6
7
8
9
10
11
12
13
14
STBY
C1C1+
DIN1
DIN2
DIN3
ROUT1
ROUT2
ROUT3
ROUT4
ROUT5
ESD Protection on RS-232 Lines Exceeds
6 kV Per MIL-STD-883C, Method 3015
•
Applications
EIA-232 Interface
Battery-Powered Systems
Notebook PC
Computers
Terminals
Modems
•
VoHage Converter Operates With Low
Capacitance ..• 0.47 !J.F Min
DOUT1
DOUT2
DOUT3
RIN1
RIN2
RIN3
RIN4
RIN5
description
The SN75LV4735t is a low-power 3.3·V multichannel RS232 line driver/receiver. It includes three independent
RS232 drivers and five independent RS232 receivers. It is designed to operate off of a single 3.3-V supply and
has an internal switched-capacitor voltage converter to generate the RS232 output levels. The SN75LV4735
provides a single integrated circuit and single 3.3-V supply interface between the asynchronous
communications element (ACE or UARl) and the serial port connector of the data terminal equipment (DTE).
This device has been designed to conform to standard ANSI/EIA-232-D-1986.
The switched-capacitor voltage converter of the SN75LV4735 uses four small external capacitors to generate
the positive and negative voltages required by EIA-232 line drivers from a single 3.3-V input. The drivers feature
output slew-rate limiting to eliminate the need for external filter capacitors. The receivers can accept ±30 V
without damage.
The device also features a reduced power or standby mode that cuts the quiescent power to the integrated
circuits when not transmitting data between the CPU and peripheral equipment. The STBY input is driven high
for standby (reduced power) mode and driven low for normal operating mode. When in the standby mode, all
driver outputs (DIN1-3) and receiver outputs (ROUT1-3) are in a high-impedance state. If the standby feature
is not used in an application, STBY should be tied to GND.
The SN75LV4735 has been designed using LinBiCMOS™ technology and cells contained in the Texas
Instruments LinASIC™ library. The SN75LV4735 is characterized for operation from Q·C to 70·C.
t Patent pending design
LinBICMOS and UnASIC are trademarks of Texas Instruments Incorporated.
Copyright © 1993, Texas Instruments Incorporated
TEXAS . "
INSIRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2-957
SN75LV4735
3.3-V MULTICHANNEL RS232 LINE DRIVER/RECEIVER
SUSl35B-D4072, FEBRUARY 1992-REVlSEDAPRIL 1993
logic symbol t
logic diagram (positive logic)
Vcc
RIN1
3
STBY
23
[pWRDOWN]
RIN2
C1+
C1-
RIN3
C2+
C2-
RIN4
C3+
C3RINS
RIN1
DIN1
RIN2
RIN3
DIN2
RIN4
RINS
DIN3
DIN1
--B>o--B>o--B>o--B>o-
+-
~
-[>0-[>0-
DIN2
VDD
DIN3
GND
t This symbol Is in accordance with ANSVIEEE Std. 91-1984 and
lEe Publication 617-12.
1ExAs ..,
INSTRUMENTS
2-958
POST OFACE BOX 855303 • DAU.AS, TEXAS 75265
ROUT1
ROUT2
ROUT3
ROUT4
ROUTS
DOUT1
DOUT2
DOUT3
VSS
VCC
Swltched-
STBY
Capacitor
Circuit
SN75LV4735
3.3-V MULTICHANNEL RS232 LINE DRIVER/RECEIVER
SLlS1358 - 04072, FEBRUARY 1992 - REVISED APRIL 1993
schematics of inputs and outputs
EQUIVALENT OF STBY INPUT
EQUIVALENT OF RECEIVER INPUT
r---~~---'------VCC
Vcc
VSS
GND
EQUIVALENT OF DRIVER INPUT
~--~--~----~--~~--___ GND
TYPICAL OF ALL DRIVER OUTPUTS
--VCC
--VDD
-,
Input
=l
- - - GND
--IJ --
}--
DOUT
3000
VSS
TYPICAL OF ALL RECEIVER OUTPUTS
---h1 __
- - VSS
VCC
RECOUT
GND
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee ........................................................................ 4 V
Positive output supply voltage, Voo (see Note 1) .............................................. 15 V
Negative output supply voltage, V ss ....................................................... -15 V
Input voltage range,VI: DIN1-DIN3, STBY ............................................. -0.3 to 7 V
RIN1-RIN5 ................................................ -30 V to 30 V
Output voltage range,Vo: DOUT1-DOUT3 .............................. Vss - 0.3 V to Voo + 0.3 V
ROUT1-ROUT5 ........................................... -0.3 V to 7 V
Continuous total power dissipation ..................................... See Dissipation Rating Table
Operating free-air temperature range, TA .............................................. O°C to 70°C
Storage temperature range ....................................................... -65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds ............................... 260°C
NOTE 1: All voltages are with respect to the network ground terminal.
DISSIPATION RATING TABLE
=
PACKAGE
TAs25°C
POWER RATING
DERATING FACTOR
ABOVE TA ;. 25°C
TA 70°C
POWER RATING
DB
665mW
5.3mWrC
430mW
1ExAs
~
INSIRUMENfS
POST OFFICE BOX 655303 • OALU\S. TEXAS 75265
2-959
SN75LV4735
3.3-V MULTICHANNEL RS232 LINE DRIVER/RECEIVER
SLLS135B - 04072, FEBRUARY 1992 - REVISED APRIL 1993
recommended operating conditions
MIN
NOM
MAX
Supply vottage, VCC
3
3.3
3.6
PosHlve output supply vottage, VOO
S
10
-7
-s
Negative output supply voRage, Vss
Input voltage, VI (see Note 2)
High-level Input voRage, VIH
Low-level input voRage, VIL
High-level output current, IOH
Low-level output current, IOL
OIN1-3, STBY
0
V
,.30
2
OIN1-3, STBY
O.S
-1
RIN1-S
3.2
0.47
Extemal capacitor
Operating free-air temperature, TA
1
0
..
V
V
VCC
RIN1-5
UNIT
V
V
mA
I'F
70
·C
NOTE 2: The algebraic convention, where the more positive Qess negative) limit IS deSignated as m8XImum, IS used In thiS data sheet for logic
levels only, e.g., If -10 V Is a maximum, the typical value Is a more negative voltage.
supply currents
PARAMETER
TEST CONDITIONS
=
ICC
Supply current from VCC
(normal operating mode)
No load,
Vcc 3.3 V,
All other inputs open
ICC
Supply current (standby mode)
Vcc
=3.3 V,
No load,
1ExAs
STBY
=low-level input,
STBY
=high-level input
~
INSIRUMENTS
2-960
POST OFFICE BOX 655303 • OAU.AS: TEXAS 75265
MIN
TVP
MAX
S.S
20
UNIT
mA
10
i>A
SN75LV4735
3.3-V MULTICHANNEL RS232 LINE DRIVER/RECEIVER
SLLS1358 - 04072, FEBRUARY 1992 - REVISED APRIL 1993
DRIVER SECTION
electrical characteristics over operating free-air temperature range,
otherwise noted)
Vee
=3.3 V ±10% (unless
MIN
TYpt
VOH
High-level output voltage
RL=3ke
5.5
7
VOL
Low-level output voltage (see Note 2)
RL=3ke
-5
-5.5
II
Input current, STBY
PARAMETER
TEST CONDITIONS
MAX
UNIT
V
V
,.1
IIH
High-level Input current
1
IlL
loW-level input current
-1
IIA
IIA
IIA
IOS(H)
High-level short-circuit output current (see Note 3)
VCC=3.6V,
VO=O
-10
-20
rnA
IOSCL.)
Low-level short-cIrcuit output current (see Note 3)
VCC = 3.6 V,
VO=O
10
20
rnA
Output resistance
VCC =VDD =VSS =0,
See Note 4
VO=-2Vt02V,
ro
a
300
t All typical values are at TA = 25°C.
NOTES: 2. The algebraic convention, where the more positive (less negative) limit is designated as maximum, is used in this data sheet for logic
levels only.
3. Not more than one output should be shorted at one time.
4. Test conditions are those specified by EIA-232-D.
switching characteristics, Vee =3.3 V ±10%, TA =25°C
PARAMETER
TEST CONDITIONS
tpLH
Propagation delay time, low-to-high-Ievel output
tpHL
Propagation delay time, high-to-Iow-Ievel output
tpZL
Output enable time to low level (see Note 5)
tpZH
Output enable time to high level (see Note 5)
tpHZ
Output disable time from high level (see Note 5)
tpLZ
Output disable time from low level (see Note 5)
SR
Output slew rate (see Note 6)
RL = 3 keto 7 ke,
See Figure 2
CL=50pF,
SR(tr)
Transition region slew rate
RL = 3 keto GND,
See Figure 4
CL = 2500 pF,
RL= 3 kOto GND,
See Figure 2
RL= 3 kOto GND,
See Figure 3
CL=50 pF,
MIN
TYP
MAX
UNIT
200
400
600
ns
100
200
350
ns
3
7
ms
CL=50 pF,
1
5
ms
1
3
0.5
3
IJ.S
IJ.S
30
V/IJ.S
3
3
V/IJ.S
NOTES: 5. Output enable occurs when STBY IS driven low. Output disable occurs when STBY IS driven high.
6. Measured between 3-Vand -3-V points of output waveform (EIA-232-D conditions), all unused inputs tied either high or low.
POST OFFICE BOX 855303 • DALlAS, TEXAS 75265
2-961
SN75LV4735
3.3-V MULTICHANNEL RS232 LINE DRIVER,lRECEIVER
SLLS135B-D4072, FEBRUARY 1992-REVISEDAPRIL 1993
RECEIVER SECTION
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYpt
MAX
2.2
2.6
V
1.8
mV
0.4
V
Vr+
Vr-
Positive-going threshold voltage
Negative-going threshold voltage
0.6
1
Vhys
Input hysteresis (VT+- VT~
0.5
1.2
VOH
High-level output voltage
IOH=-2mA.
VOL
Low-level output voltage
IOL=2mA
IIH
High-level input current
IlL
Low-level input current
ri
Input resistance
See Note 7
2.4
V
V
2.6
0.2
VI=3V
0.43
0.55
1
VI=25V
3.6
4.6
8.3
VI=-3V
-0.43
-0.55
-1
-3.6
-5
-8.3
3
5
7
VI =-25V
VI =",3Vto",25 V
UNIT
mA
mA
kC
t All typical values are at TA = 25·C.
NOTE 7: If the inputs are left unconnected. the receiver Interprets this as an input low. and the receiver outputs will remain In the high state.
switching characteristics over recommended supply voltage range, TA
PARAMETER
TEST CONDITIONS
tPLH
Propagation delay time. low-to-high-Ievel output
tpHL
Propagation delay time. high-to-low-Ievel output
tpZL
Output enable time to low level (see Note 5)
tpZH
Output enable time to high level (see Note 5)
tpHZ
Output disable time from high level (see Note 5)
tpLZ
Output disable time from low level (see Note 5)
RL = 3 kC to GND.
See Figure 5
CL=50pF.
RL= 3kCto GND.
See Figure 6
CL=50pF.
=25°C
MIN
TYP
MAX
45
80
130
ns
70
100
170
ns
160
250
ns
4
10
300
500
f.IS
ns
140
200
ns
NOTE 5: Output enable occurs when STBY is driven low. Output disable occurs when STBY Input Is driven high.
1ExAs
~
INSIRUMENTS
2-s62
POST OFFICE BOX 655303 • DAUAS. TEXAS 75a15
UNIT
SN75 LV4735
3.3-V MULTICHANNEL RS232 LINE DRIVER/RECEIVER
SLLS135B - D4072, FEBRUARY 1992 - REVISED APRIL 1993
APPLICATION INFORMATION
+
1 VDD
C3+
2 C2+
GND
3 VCC
C3-
4
5
-::-
C1
6
28
25
C2-
VSS
GND
C1STBY
C1+
+
C5
24
23
VCC
TTL In
TTL In
TTL In
TTL Out
TTL Out
TTL Out
TTL Out
TTL Out
7
22
8
21
EIA-232Out
EIA-232Out
9
20
10
19
11
18
12
17
13
16
14
15
EIA-232Out
EIA-232In
EIA-232In
EIA-232In
EIA-232In
EIA-232In
-::-
Figure 1. Typical Operating Circuit
1ExAs ."
INSIRUMENIS
POST OFFICE BOX 655303 • DAUAS, TEXAS 75265
2-963
SN75LV4735
3.3-V MULTICHANNEL RS232 LINE DRIVER/RECEIVER
Su..sl35B-D------..180kC
I
I
I
I
I
Input
TYPICAL OF RECEIVER OUTPUT
Vcc
NOM
Connected
on A Port
AorB
3kC
NOM
18kC
NOM
=
=
Driver Input: Raq 3 kC NOM
Enable Inputs: Raq 8 kg NOM
Output
1.1 kC
NOM
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) ............................................................. 7 V
Voltage range at any bus terminal ................................................... -10 V to 15 V
Enable input voltage ....................................................................... 5.5 V
Continuous total power dissipation ..................................... See Dissipation Rating Table
Operating free-air temperature range, TA .............................................. O·C to 70·C
Storage temperature range ....................................................... -65·C to 150·C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds ............................... 260·C
NOTE 1: All voRage values, except differential VO bus voltage, are with respect to network ground terminal.
DISSIPATION RATING TABLE
PACKAGE
o
p
DERATING FACTOR
ABOVE TA = 25·C
TA 70·C
POWER RATING
725mW
1000mW
5.8 mwrc
8.0 mwrc
464 mW
640 mW
TEXAS'"
INSIRUMENfS
2-968
=
TAs25°C
POWER RATING
POST OFFICE BOX 855303 • DAUAS. TEXAS 75265
TL3695
DIFFERENTIAL BUS TRANSCEIVER
SLLS044B - 03408, NOVEMBER 1988 - REVISED FEBRUARY 1993
recommended operating conditions
Supply voltage, VCC
MIN
NOM
MAX
UNIT
4.75
5
5.25
V
12
Voltage at any bus terminal (separately or common mode), VI or VIC
High-level Input voltage, VIH
D, DE, and RE
Low-level Input voltage, VI L
D, DE, and RE
-7
2
V
0.8
Driver
Receiver
",12
V
rnA
-400
iAA
60
Driver
Low-level output current, 10L
Receiver
8
Operating free-air temperature, TA
V
-60
Differential input voltage, VID (see Note 2)
High-level output current, 10H
V
70
0
rnA
·C
NOTE 2: Differentlal-inpu!/output bus voltage IS measured at the nomvertlng terminal A wHh respect to the inverting terminal B.
DRIVER SECTION
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONSt
VIK
Input clamp voltage
11=-18mA
Vo
Output voltage
10=0
iVODll
Differential output voltage
10=0
IV OD21
Differential output voltage
VOD3
Differential output voltage
A
IVODI
Change in magnftude of differential output
voltage§
VOC
Common-mode output voltage
A
Change in magnitude of common-mode
output voltage§
IVocl
MIN
MAX
V
0
6
V
1.5
5
V
1/2VODl
or 211
See Figure 1
RL=540,
See Figure 1
1.5
Vtest =-7Vto 12V,
See Figure 2
1.5
V
2.5
See Figure 1
IVO=12V
IVO=-7V
5
V
5
V
",0.2
V
3
V
",0.2
V
1
10
Output current
Output disabled,
See Note 3
IIH
High-level input current
VI=2.4V
20
IlL
Low-level input current
VI =0.4V
-200
VO=-6V
-250
VO=O
-150
lOS
Short-circuit output current
-0.8
250
VO=VCC
Supply current
No load
mA
iAA
iAA
mA
250
VO=8V
ICC
UNIT
-1.5
RL=1000,
RL = 54 0,
TYp:j:
LOutputs enabled
23
50
I Outputs disabled
19
3S
mA
t The power-off measurement In EIA Standard RS-422-A applies to disabled outputs only and IS not applied to combined Inputs and outputs.
:I: All typical values are at VCC = 5 V and TA = 2S·C.
§ A IVODI and AIVocl are the changes in magnitude ofVOD and VOC respectively, that occur when the input is changed from a high level to a
low level.
11 The minimum VOD2wfth a 100-0 load is efther 1/2VODl or 2 V whichever is greater.
NOTE 3: This applies for both power on and off; refer to EIA Standard RS-485 for exact conditions. The RS-422-A limit does not apply for a
combined driver and receiver terminal.
1ExAs
,If
INSIRUMENTS
POST OFFICE BOX 655303 • DAllAS, TEXAS 75265
2-969
TL3695
DIFFERENTIAL BUS TRANSCEIVER
SLLS044B - 03408, NOVEMBER 1988 - REVISED FEBRUARY 1993
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature
PARAMETER
TEST CONDITIONS
MIN
TYpt
MAX
8
22
1
8
UNIT
ttD
Differential output transition time
18
ns
ns
ns
tPZH
Output enable time to high level
CL = 100 pF,
RL=5000,
See Figure 4
50
ns
tPZL
Output enable time to low level
CL= 100 pF,
RL= 500 Q,
See Figure 5
50
tpHZ
Output disable time from high level
CL=15pF,
RL=500 0,
See Figure 4
8
30
ns
ns
tpLZ
Output disable time from low level
CL= 15 pF,
RL=500 0,
See Figure 5
8
30
ns
Ic!D
Dlfferentlal-output delay time
Skew OIc!DH-Ic!DLD
CL1 =CL2=100pF,
RL=600,
See Figure 3
8
t All typical values are at VCC = 5 V and TA = 25"C.
SYMBOL EQUIVALENTS
DATA SHEET PARAMETER
RS-422·A
RS-485
Vo
Voa,Vob
Voa,Vob
IVOD11
Vo
Vo
IVOD21
Vt (RL = 1000)
VtlRL= 54 0)
Vt (Test Termination
Measurement 2)
IVOD31
Vtest
dlVODI
Vlst
I IVtI-1Vt1 I
VOC
IVosl
"!Vosl
dlVocl
IVos-Vos I
IVos-Vos I
lOS
lisa I, Iisb I
10
Ilxal,llxbl
1ExAs
,If
INSIRUMENTS
2-S70
IIVtI-lVtll
POST OFFICE BOX 655303 • OAUAS, TEXAS 75265
Ila,lib
TL3695
DIFFERENTIAL BUS TRANSCEIVER
SUS044B - D3408, NOVEMBER 1988- REVISED FEBRUARY 1993
RECEIVER SECTION
electrical characteristics over recommended ranges of common-mode input voltage, supply
voltage, and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYpt
MAX
Posltlve-golng Input threshold voltage
Vo =2.7 V,
10 =-0.4 mA
Negative-going input threshold voltage
VO=0.5V,
10=SmA
Vhys
Hysteresis
VIK
Enable-input clamp voltage
11=-ISmA
VOH
High-level output voltage
VIC = 200 mV or Inputs open,
See FigureS
10H = -400 !U\
VOL
Low-level output voltage
VIC = -200 mV,
See FigureS
10Z
Hlgh-lmpedance-state output current
Vo = 0.4 Vto 2.4 V
II
Une input current
Other Input = 0 V,
See Note 4
IIH
High-level enable-input current
VIH=2.7V
20
IlL
Low-level enable-input current
VIL=0.4V
-100
r.IA
r.IA
-S5
rnA
IVT+-Vr"')
0.2
UNIT
Vr+
Vr-
70
VOC=O
I'j
Input resistance
lOS
Short-circuit output current
VO=O
ICC
Supply current
No load
V
V
-0.2*
mV
-1.5
V
V
2.4
0.5
1i0L=lSmA
0.45
II0L=SmA
.,20
IVI =12V
1
IVI =-7V
-O.S
V
r.IA
mA
kQ
12
-15
I Outputs enabled
23
50
I Outputs disabled
19
35
mA
t All tyPIcal values are at VCC = 5 V and TA = 25·C.
* The algebraic convention, in which the less-positive (more-negative) limit Is designated minimum, Is used In thls data sheet for common-mode
input voltage and threshold voltage levels only.
NOTE 4: This applies for both power on and power off. Refer to EIA Standard RS-485 for exact conditions.
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, CL = 15 pF
PARAMETER
TEST CONDITIONS
tpLH
Propagation delay time, low-to-high-Ievel output
tpHL
Propagation delay time, high-to-Iow-Ievel output
tpZH
Output enable time to high level
tPZL
Output enable time to low level
tpHZ
Output disable time from high level
tpLZ
Output disable time from low level
VIC =-1.5 Vto 1.5 V,
See Figure 7
See FigureS
See FigureS
MIN
TYpt
MAX
14
37
ns
14
37
ns
7
20
ns
7
20
ns
7
16
S
16
ns
ns
UNIT
t All typical values are at VCC = 5 V and TA = 25·C.
1ExAs . "
INSTRUMENTS
POST OFFICE BOX 655303 • OAUAS, TEXAS 75265
2-971
TL3695
DIFFERENTIAL BUS TRANSCEIVER
SLLS044B - D3408, NOVEMBER 1988- REVISED FEBRUARY 1993
PARAMETER MEASUREMENT INFORMATION
Figure 1. Driver VOD and Voe
3750
600
Vtest
.1
3750
Figure 2. Driver VOD3
CL1=100 PF
(see Note B)
RL=600
Generator
(see Note A)
500
8
Input
~-:;:~-3V
---1r .,~
CL2=100pF
(see Note B)
1C..:- 0 V
y
1
Output
1
tdDH~
~ldDL
, 1
1
O%
-::
Output
50%
50%
~
--2,5V
1 10% 1
---2,5V
ttD ~
i4-- ttO
VOLTAGE WAVEFORMS
-.I
i4-
TEST CIRCUIT
NOTES: A The input pulse is supplied by a generator having Ihe following characteristics: PRR " 1 MHz, 50% duty cycle, t r " 6 ns, If" 6 ns,
ZO=500.
B. CL includes probe and jig capacHance.
Figure 3. Driver Differential-Output Test Circuit and Voltage Waveforms
Output
S1
___
~
OVto3V - - - - f
Generator
(see Note A)
500
(see NoteCL
B)
T
Input
----1r 1.5 V
1
~tPZH'
_
1/
Output
T
_ _-oJ
TEST CIRCUIT
3V
1.5 V ~
I
I
I
.1
2.3 V
tPHZ--!
OV
0.5 V
-*- vOH
K:!,14-=
Voff- OV
VOLTAGE WAVEFORMS
NOTES: A The input pulse is supplied by a generator having the following characteristics: PRR " 1 MHz, 50% duty cycle, tr" 10 ns, tf" 10 ns,
ZO=500.
B. CL includes probe and jig capacitance (see switching characteristics - tesl conditions).
Figure 4. Driver Test Circuit and VOltage Waveforms
TEXAS
,If
INSIRUMENTS
2-672
POST OFFICE BOX 655303 • DAUAS, TEXAS 75265
TL3695
DIFFERENTIAL BUS TRANSCEIVER
SLLS044B - 03408. NOVEMBER 1988 - REVISED FEBRUARY 1993
PARAMETER MEASUREMENT INFORMATION
5V
RL=SOOO
Output
Input
~1.5V
3VorOV - - - - - f
Generator
(eeeNoteA)
I
CLI
I
I
I
tpZL ----IIII141--~~
I
I
(see Note B)
SOO
\1.~---::
~tpLZ
,\2.3
Output
~~~
V
.
TEST CIRCUIT
-",-VOL
VOLTAGE WAVEFORMS
I
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR s 1 MHz. 50% duty cycle. tr s 10 ns. tf S 10 ns.
ZO=500..
B. CL includes probe and jig capacitance (see switching characteristics - test conditions).
Figure 5. Driver Test Circuit and Voltage Waveforms
Figure 6. Receiver VOH and VOL
5V
Input~ov
1 kO
Generator
(see Note A)
1N916
or
Equivalent
I
tpLH
Output
OV
TEST CIRCUIT
~
I
)11.5 V
\ . ov - - - 2.5V
1\......___ -2.5 V
I
~tpHL
I
v-:-_-:-:-
VOH
~ VOL
VOLTAGE WAVEFORMS
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR S 1 MHz. 50% duty cycle. tr S 10 ns, tf S 10 ns,
ZO=500.
B. CL includes probe and jig capacitance.
Figure 7. Receiver Test Circuit and Voltage Waveforms
1ExAs ."
INSIRUMENTS
POST OFFICE BOX 6S5303 • DAUAS, TEXAS 75265
2-973
TL3695~
DIFFERENTIAL BUS TRANSCEIVER
\
SLLS044B - 03408. NOVEMBER 1988 - REVISED FEBRUARY 1993
PARAMETER MEASUREMENT INFORMATION
1.6V
S1
1 kC
-1.6V---O
T
CL = 16pF
(eee Note B)
Generator
(eeeNoteA)
1 kC
1N916 or Equivalent
60C
TEST CIRCUIT
~-=--=3V
:
Input----./'
S1 to1.6V
~1.6V S20pen
I
Input~~.:v
I
I
S3Closed
ov
tpZH --./ : . -
~
Output
Input
tpZL~
I
~
I
I
VOH
'----.£-': "-- °V
~---3V
----1r I."
y
"--- 0
V
Output
S1 to 1.6V
S20pen
S3Closed
--!.--.I
'6V I
~
~
1.5V
-_4.5V
VOL
Input~3V
I
I
ov
S1 to-1.6V
S2Closed
S30pen
I
tpHZ
Output
ov
S1 to-1.5V
S2Closed
S30pen
tpLZ
1__ •
~
I
VOH
-...--
Outp_ut_ _ _.J(O.6 V
- - - -1.3V
VOLTAGE WAVEFORMS
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR '" 1 MHz. 50% duty cycle. tr " IOns. tf" 10 ns.
ZO=50C.
B. CL includes probe and jig capackance.
Figure 8. Receiver Test Circuit and Voltage Waveforms
TEXAS . "
INSTRUMENTS
2-e74
POST OFFICE BOX 655303 • DAUAS. TEXAS 75265
TL3695
DIFFERENTIAL BUS TRANSCEIVER
SLLS044B- 03408, NOVEMBER 1988- REVISED FEBRUARY 1993
TYPICAL CHARACTERISTICS
DRIVER HIGH-LEVEL OUTPUT VOLTAGE
DRIVER LOW-LEVEL OUTPUT VOLTAGE
vs
vs
DRIVER HIGH-LEVEL OUTPUT CURRENT
DRIVER LOW-LEVEL OUTPUT CURRENT
5
5
VCC=5V
TA = 25°C
4.5
>I
..
CI
!
~
5a.
3.5
2.5
!
2
0
..............
.............
CI
3.5
0
2.5
~;i:
2
.9
1.5
I
I
I
3
II
_.... --
1.5
!...
I
~
J:
0
>
~
Sa.
S
.........
.c
:i:
4
CI
3
S
>I
.
--.. ""'-
4
VCC=5V
TA = 25°C
4.5
0.5
o
0.5
o
o
-20
-40
-60
-80
-100
-120
o
20
IOH - High-level Output Current - mA
~
40
I---'
60
80
100
120
10L - Low·Level Output Current - mA
Figure 9
Figure 10
DRIVER DIFFERENTIAL OUTPUT VOLTAGE
vs
DRIVER OUTPUT CURRENT
4
>I
...
CI
3.5
3
VCC=5V
TA = 25°C
.......
r'-.....
..........
.:t::
~
Sa.
"S
0
2.5
i'-
2
........
i'- ......
"\
:!i
1:
I!!
1.5
£!
1\
Q
I
Q
~
0.5
o
o
\
10
20
30
40
50
60
70 80
90 100
10 - Output Current - mA
Figure 11
TEXAS . "
INSIRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2-975
TL3695
DIFFERENTIAL BUS TRANSCEIVER
SLLS0448 - 03408, NOVEMBER 1988 - REVISED FEBRUARY 1993
TYPICAL CHARACTERISTICS
RECEIVER HIGH·LEVEL OUTPUT
va
FREE-AIR TEMPERATURE
RECEIVER HIGH·LEVEL OUTPUT VOLTAGE
va
HIGH·LEVEL OUTPUT CURRENT
5
5r----,----~----~----~----,
VIO=O.2V
TA=25"C
>I
>I
!l
4
...aI
t
~
VCC=5V
VIO=200mV
IOH = -440 j.tA
~!l
3t-~~.------+-----+----+-----f
!
I"""
3
Q.
!l
0
~ 21---+~y#-___---I---+---I
!
i.
:i:
2
s::.
aI
X
I
I
~
J:
0
>
o~--~----~----~~~~--~
o
-10
-20
-30
-40
o
-SO
-40 -20
IoH - Hlgh·Level Output Current - mA
0
Figure 12
0.6
VCC-SV
TA = 25"C
0.5
~!l
0.4
0
0.3
~
!
0.2
~
0.1
...aI
~
I
oJ
o
./
~/
V
/
/ '"
15
i
~
0.4t--I--+--t--+----if---+--+--I
1
0.31--t-f"'--jr---=-F===:i:::-1---t---1
I
25
=
0.5
I
0
20
VCC=5V
VIO=-200mV
IOL 8 mA
30
t--I---+---t--+---I
"I---+--If---+---f-+---+-+--I
0.1 t--I--+--t--+----if---+--+--I
O~~--~--~--~~~~--~~
-40 -20
0
20
40
60
80
100 120
TA - Free-Alr Temperature - ·C
IOL - Low·Level Output Current - mA
Figure 15
Figure 14
1ExAs
..If
INSIR.UMENTS
24176
100 120
>
~
10
80
0.6 r----.---r--"T""--.,.....--,.-.....,..--""T"---.
/
V
5
60
RECEIVER LOW·LEVEL OUTPUT VOLTAGE
va
FREE-AIR TEMPERATURE
~
o
40
Figure 13
RECEIVER LOW·LEVEL OUTPUT VOLTAGE
va
RECEIVER LOW·LEVEL OUTPUT CURRENT
>I
20
TA - Free·Alr Temperature - ·C
POST OFFICE BOX 855303 • DAUAS. TEXAS 75265
T13695
DIFFERENTIAL BUS TRANSCEIVER
Su.s0448 - 03408, NOVEMBER 1988- REVISED FEBRUARY 1993
TYPICAL CHARACTERISTICS
RECEIVER OUTPUT VOLTAGE
RECEIVER OUTPUT VOLTAGE
va
va
ENABLE VOLTAGE
ENABLE VOLTAGE
5
6
VIO=0,2V
Load = 8 kg to GNO
TA=25°e
4 f - - - Vee = 5.25 V
5
>
~
f - - - Vee = 4.75 V
I
I
"- Vee=5V
)
VIO=-O.2V
Load = 1 kQ to Vee
TA=25°e
I
4
_1-
Vee = 5.25 V
/
Vee = 4.75 V
Vee .. 5V
3
!5
~
o
I
2
~
o
o
0.5
1
1.5
2
2.5
o
3
o
0.5
VI - Enable Voltage - V
1
1.5
2
2.5
VI- Enable Voltage - V
Figure 16
3
Figure 17
APPLICATION INFORMATION
TL..3695
TL.3695
Upt032
Transceivers
•••
NOTE: The line should be terminated at both ends in its characteristic impedance. Stub lengths off the main line should be kept as short as
possible.
Figure 18. Typical Application Circuit
1ExAs ~ .
INSTRl.JMENfS
POST OFFICE eox ~ • DAUAS, TEXAS 75265
2-978
uA9636AC
DUAL LINE DRIVER WITH ADJUSTABLE SLEW RATE
SLLS110A-
•
Meets EIA Standards RS-423-A and
RS-232-C and Federal Standard 1030
•
Slew Rate Control
•
Output Short-Clrcuit-Current Limiting
•
Wide Supply Voltage Range
•
•
8-Pln Package
OCTOBER 1980 - REVISED MARCH 1993
D OR P PACKAGE
(TOP VIEW)
W-S[]8
7
Vcc+
1Y
3
6
2Y
4
5
Vcc-
1A
2
2A
GND
logic symbol t
Designed to Be Interchangeable With
Fairchild 9636A
description
The uA9636AC is a dual single-ended line driver
designed to meet EIA Standards RS-423-A and
RS-232-C and Federal Standard 1030. The slew
rates of both amplifiers are controlled by a single
external resistor, Rws, connected between the
wave-shape-control (W-S) terminal and GND.
Output current limiting is provided. Inputs are
compatible with TTL and CMOS and are diode
protected against negative transients. This device
operates from ± 12 V and is supplied in an 8-pin
package.
t This symbol is in accordance with ANSI/IEEE SId 91-1984 and
IEC Publication 617-12.
logic diagram
1A~71Y
W-S
2A 3
6 2y
The uA9636AC is characterized for operation
from O·C to 70·C.
schematics of inputs and outputs
EQUIVALENT OF EACH INPUT
TYPICAL OF ALL OUTPUTS
Current
Source
---------~----
Input
Output
------......--~----
VCC-
VCC- - - -.....- - - - - - -
TEXAS
~
Copyright © 1993, Texas Instruments Incorporated
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
2-979
uA9636AC
DUAL LINE DRIVER WITH ADJUSTABLE SLEW RATE
SLLS11QA- 02608, OCTOBER 1980- REVISED MARCH 1993
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Positive supply voltage range, V cc+ (see Note 1) ...................................... V cc- to 15 V
Negative supply voltage range, V cc- ....... :...................................... 0.5 V to -15 V
Output voltage ........................................................................... :t 15 V
Output current .............................,........................................... :t 150 mA
Continuous total power dissipation ..................................... See Dissipation Rating Table
Operating free-air temperature range .................................................. O·C to 70·C
Storage temperature range ....................................................... -65·C to 150·C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds ............................... 260·C
NOTE 1: All voltage values are with respect to the network ground terminal.
DISSIPATION RATING TABLE
=
TAs25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
D
725mW
5.8mwrc
464mW
P
1000mW
8.0mWrC
640mW
PACKAGE
TA 70°C
POWER RATING
recommended operating conditions
PosHive supply voltage, VCC+
Negative ,supply voltage, VCC":'
High-level Input voltage, VIH
MIN
NOM
MAX
UNIT
10.8
12
13.2
V
-10.8
-12
-13.2
Low-level input voltage, VIL
Wave-shaping resistor,
0.8
Rws
Operating free-air temperature, TA
lExAs
..If
INSIRUMENTS
2-980
POST OFFICE BOX 655303 • DAUAS, TEXAS 75265
V
V
2
V
10
1000
kg
0
70
°c
uA9636AC
DUAL LINE DRIVER WITH ADJUSTABLE SLEW RATE
SUS110A- D2608, OCTOBER 1980 - REVISED MARCH 1993
electrical characteristics over recommended range of free-air temperature, supply voltage, and
wave-shaping resistance (unless otherwise noted)
PARAMETER
VIK
TEST CONDITIONS
Input clamp voRage
5
RL=co
VOH
VOL
MIN
11=-15mA
High-level output voltage
VI =0.8V
L.ow-\evel output voRage
VI=2V
TYpt
MAX
UNIT
-1.1
-1.5
V
5.6
6
RL=3 kOto GND
5
5.6
6
RL= 450 oto GND
4
5.4
6
RL='"
-6*
-5.7
-5
RL= 3 kOto GND
-s*
-5.S
-5
RL= 4500to GND
-6*
-5.4
-4
VI =2.4V
10
VI=5.5V
100
IIH
High-level Input current
IlL
Low-level Input current
VI=0.4V
10
Output current (power 011)
VCC", = 0,
-20
VO=",SV
VI=2V
V
V
,.A
-80
,.A
",100
,.A
15
25
150
-15
-40
-150
lOS
Short-clrcut output currenl§
ro
Output resistance
RL=4500
25
50
0
ICC+
Positive supply current
VCC=",12V,
RWS= 100ke,
VI =0,
Output open
13
18
rnA
ICC-
Negative supply current
VCC=",12V,
Rws = 100 kO,
VI =0,
Output open
-13
-18
rnA
VI=O
rnA
t Alltyplca\ values are atVcc = ",12V, TA = 25"C.
* The algebraic convention, In which the less-positive (more-negative) limit Is designated as minimum, Is used In this data sheet for logic vottage
levels, e.g., when -5 V Is the maximum, the minimum is a more-negative Voltage.
§ Not more than one output should be shorted 10 ground at a time.
switching characteristics, VCC±
=±12 V, TA =25°C (see Figure 1)
PARAMETER
TEST CONDITIONS
Rws=10ke
ITLH
ITHL
Transition time, low-to-high-Ievel output
Transition time, high-to-Iow-Ieve\ output
RL=450kO,
RL=450ke,
CL=30pF
CL=30pF
MIN
TYP
MAX
0.8
1.1
1.4
Rws=1OOke
8
11
14
Rws = 500 ke
40
55
70
RwS=1 Me
80
110
140
RwS=10ke
0.8
1.1
1.4
Rws = 100 ko
8
11
14
Rws =500 ko
40
55
70
RwS=1 MO
80
110
140
UNIT
I'll
I'll
1ExAs ..,
INSIRUMENTS
POST OFFICE BOX 655303 • DAllAS, TEXAS 75265
2-981
uA9636AC
DUAL LINE DRIVER WITH ADJUSTABLE SLEW RATE
Su.s110p'- D2608, OCTOBER 1980- REVISED MARCH 1993
PARAMETER MEASUREMENT INFORMATION
Input
(see Note B)
OV
Input -4,,""""--;
soo
CL=30pF
(see Note A)
VCCTEST CIRCUIT
VOLTAGE WAVEFORMS
NOTES: A CL Includes probe and jig capacftance.
B. The Input pulse Is supplied by a generator having Ihe following characlerlstlcs:
duty cycle = 50%.
Ir s
10 ns, If s 10 ns, Zo = 50 Q, PRR s 1 kHz,
Figure 1. Test Circuit and Voltage Waveforms
TYPICAL CHARACTERISTICS
INPUT CURRENT
OUTPUT VOLTAGE
va
va
INPUT VOLTAGE
INPUT VOLTAGE
12
250
VCC .. =:t:12V
Rws=100kQ
RL 450 0
10
=
8
>I
6
::I.
~
'S
!0
4
I
TA=70·C
o
2
i
TA=O·C
0
TA,,25·C -
I
~
/'
TA=O·C
h
TA=25·C -
r-.....
TA=70·C
~
50
0
-50
I
-2
-4
-150
-6
-200
V
TA=O·C
~
TA=25·C
TA,,70·C
o
-250
0.4
0.8'
1.2
VI-Input Voltage-V
1,6
~
2
~
0
2
3
4
5
VI-Input Voltage-V
Figure 2
Figure 3
ThxAs
,If
INSIRUMENTS
2-982
I
100
.:: -100
-8
I
I
GI
I
I
200 f- VCC .. = .,12V
Rws= 100 kQ
150
POST OFFICE BOX 665303 • 0AllAS, TEXAS 75265
6
7
8
uA9636AC
DUAL LINE DRIVER WITH ADJUSTABLE SLEW RATE
SLL.S110A- D2608. OCTOBER 1980 - REVISED MARCH 1993
TYPICAL CHARACTERISTICS
OUTPUT CURRENT
OUTPUT CURRENT
vs
vs
OUTPUT VOLTAGE
(POWER ON)
OUTPUT VOLTAGE
(POWER OFF)
50
40
30
~
I
100
I- VCC", = ",12 V
Rws = 100 kO
I- TA=25DC
I'"
20
10
0
0
::I
'a.
!5
'!5
0
I
9
-50
-10 -8
40
20
I
I
J
0
'!a.5
'!5 -20
f
0
-20
-40
I
1:
~
::I
0
-10
-30
'"
::I.
\"VI=2V
1:
~
I
_ VCC:I:=O
VI=O
60 - TA=25DC
80
r.
I
I
9
VI=O
-60
J
Ii
-40
-80
-6 -4
-2
0
2
4
6
8
I
-100
-10 -8
10
-6 -4 -2
0
2
4
6
8
10
Vo - Output Voltage - V
Vo - Output Voltage - V
Figure 4
Figure 5
TRANSITION TIMES
vs
WAVE-5HAPING RESISTANCE
1000
700
III
::I.
I
:l
200
1=
c
100
70
ic
40
~
I
20
..:5
10
7
E
0
.
I-
~
.I~~~~DC
400
/
/
~A=70DC
V
/
4
2
V
1
0.01
V
0.04
0.1
0.4
4
10
RWS - Wave-Shaping Resistance - MO
Figure 6
1ExAs ."
INSIRUMENTS
POST OFFICE BOX 656303 • DALLAS. TEXAS 75265
2-983
uA9636AC
DUAL UNE DRIVER WITH ADJUSTABLE SLEW RATE
Sl.LSllOA- D2808, OCTOBER 1980 - REVISED MARCH 1993
APPLICATION INFORMATION
12V
TwIsted Pair
or
5V
! FlatCable
uA9637A
-12V
Figure 7. RS-423-A System Application
1ExAs
~
INSIRUMENI'S
POST OFFICE BOX 865303 • DAL.LAS, lEXAS 75286
uA9637AC
DUAL DIFFERENTIAL LINE RECEIVER
1980- REVISED FEBRUARY 1993
•
uA9637C ... 0 OR P PACKAGE
Meets EIA Standards RS-422-A and
RS-423-A
(TOP VIEW)
•
Meets Federal Standards 1020 and 1030
•
Operates From Single S-V Power Supply
•
Wide Common-Mode Voltage Range
•
High Input Impedance
•
TTL-Compatlble Outputs
•
High-Speed Schottky Circuitry
VCC[]8
10UT 2
7
20UT 3
6
GND 4
5
logic symbol t
11N+
•
11N+
11N21N+
21N-
S-Pin Dual-In-Line and Small-Outline
Packages
11N21N+
•
Similar to SN75157 Except for Corner Vee
and Ground Pin Positions
•
Designed to Be Interchangeable With
Fairchild tJA9637A
21N-
8
"]
7
6
lrl>
2
3
5
"
1OUT
20UT
t This symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
logic diagram
description
8
1IN+~
7
lr
The uA9637AC is a dual differential line receiver
designed to meet EIA standards RS-422-A and
RS-423-A and Federal Standards 1020 and 1030.
They utilize Schottky circuitry and have TTLcompatible outputs. The inputs are compatible
with either a single-ended or a differential-line
system. This device operates from a single 5-V
power supply and is supplied in an 8-pin
dual-in-line package and small-outline package.
11N-
2IN+~
5
lr
21N-
10UT
6
20UT
The uA9637AC is characterized for operation
from O°C to 70°C.
schematics of inputs and outputs
TYPICAL OF ALL OUTPUTS
EQUIVALENT OF EACH INPUT
-----..-VCC
VCC
500 NOM
Output
Current
Source
TEXAS
~
Copyright © 1993. Texas Instruments Incorporated
INSIRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
2-985
uA9637AC
DUAL DIFFERENTIAL LINE RECEIVER
SlLS111A-D2609, SEPTEMBER 1980- REVISED FEBRUARY 1993
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) .................................................... -0.5 V to 7 V
I nput voltage, VI .............................. ,.......................................... :I: 15 V
Differential input voltage (see Note 2) ....................................................... :!: 15 V
Output voltage, Vo (see Note 1) ................................................... -0.5 Vto 5.5 V
Low-level output current, IOL .............................................................. 50 mA
Continuous total dissipation ........................................... See Dissipation Rating Table
Operating free-air temperature range .................................................. O°C to 70°C
Storage temperature range ....................................................... -65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds ............................... 260°C
NOTES: 1. All voltage values, except differential input voRage, are with respect to the network ground terminal.
2. Oifferential input vOltage is measured at the noninverting input with respect to the corresponding inverting Input.
DISSIPATION RATING TABLE
PACKAGE
TA ,,25°C
POWER RATING
OPERATING FACTOR
ABOVE TA = 25°C
TA = 70°C
POWER RATING
o
725 mW
5.8 mWrC
464 mW
p
1000 mW
8.0 mWrC
640 mW
TA = 125°C
POWER RATING
recommended operating conditions
Supply voltage, VCC
MIN
NOM
MAX
4.75
5
5.25
V
±7
V
70
°c
Common-mode input voltage, VIC
Operating free-air temperature, TA
0
UNIT
electrical characteristics over recommended ranges of supply voltage, common-mode input
voltage, and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYpt
UNIT
MAX
0.2
'11'+
Pos~ive-going
'11'-
Negative-going input threshold voRage
Vhvs
Hysteresis (Vr+-VT-)
VOH
High-level output voRage
VIO= 0.2 V,
10=-1 mA
VOL
Low-level output VOltage
VIO=-0.2V,
10=20mA
II
Input current
VCC =Oto 5.5 V,
See Note 5
input threshold voltage
See Note 4
0.4
-0.2
See Note 4
V
-0.4*
70
2.5
IVI = 10V
lOS
Short-circuit output current§
VO=O,
VIO=0.2V
ICC
Supply current
VIO=-0.5V,
No load
t All typical values are at VCC = 5 V. TA = 25°C.
-40
mV
3.5
0.35
IVI=-10V
V
V
0.5
V
1.1
3.25
-1.6
-3.25
-75
-100
mA
35
50
mA
mA
* The algebraic convention, in which the less pos~ive (more negative) limit is designated as minimum, is used in this data sheet for threshold levels
only.
§ Only one output should be shorted at a time, and duration of the short circuit should not exceed one second.
NOTES: 3. The expanded threshold parameter is tested w~h a 500-0 resistor in series with each input.
4. The input not under test is grounded.
1ExAs . "
INSIRUMENTS
2-a86
POST OFFICE BOX 655303 • DAUAS, TEXAS 75265
uA9637AC
DUAL DIFFERENTIAL LINE RECEIVER
SLl.S111A- 02609. SEPTEMBER 1980 - REVISED FEBRUARY 1993
=5 V, TA =25~C
switching characteristics, VCC
PARAMETER
MIN
TEST CONOITIONS
tpLH
Propagation delay time. low-to-hlgh-level output
tpHL
Propagation delay time. high-to-Iow-level output
See Figure 1
CL= 30 pF.
TYP
MAX
15
25
ns
13
25
ns
UNIT
PARAMETER MEASUREMENT INFORMATION
Output
0.5 V
----r----_
3920
Input
-0.5 V
I
I
~tpLH
510
Out_Put
____
~tpHL
-J~r.5-V----1~.5~~~
TEST CIRCUIT
___
VOLTAGE WAVEFORM
NOTES: A. CL includes probe and jig capecRance.
. B. The input pulse is supplied by a generator having the following characteristics: tr '" 5 ns. If '" 5 ns. PRR '" 5 MHz. duty cycle = 50%.
Figure 1. Test Circuit and Voltage Waveform
TYPICAL CHARACTERISTICS
OUTPUT VOLTAGE
OUTPUT VOLTAGE
4
3.5
>
va
va
DIFFERENTIAL INPUT VOLTAGE
DIFFERENTIAL INPUT VOLTAGE
I
01
2.5
~
2
~
S
0
I
VIC=",7V
~
i
-100 -75
-50 -25
>
VIC=O
I
I
0
25
III
3
I
i
VIC .. ",7V
I
2.5
!
!
1.5
~
1
I
VIC"",7V
0.5
50
75
100
vIC=",7V
I
I
I
2
o
II
I
I
VIC=O
I
~
I
I i
I
VCC=5.25V
TA=25OC
II
!
I
I
0.5
o
!
Ii
i
VIC"O
I
I
1.5
I
3.5
!
3
I
II
~
4
I
VCC=4.75V
TA = 25°C
o
-100 -75
VIO - Olfferentlallnput Voltage - mV
!
I
I
VICfO
!
I
J
-50 -25
0
25
50
75
VIO - Olfferentlallnput Voltage - mV
100
Figure 3
Figure 2
POST OFFICE BOX 655303 • OAUAS. TEXAS 75265
2-987
uA9637AC
DUAL DIFFERENTIAL LINE RECEIVER
SLlS111A- 02609. SEPTEMBER 1980- REVISED FEBRUARY 1993
TYPICAL CHARACTERISTICS
LOW-LEVEL OUTPUT VOLTAGE
HIGH-LEVEL OUTPUT VOLTAGE
va,
va
HIGH-LEVEL OUTPUT CURRENT
LOW-LEVEL OUTPUT CURRENT
0.6
5
VCC .. SV
VIO=O.2V TA=2S°C
4.5
=r
t
3.6
5
3
5
2.5
~
Q,
!a
2
s:
1.5
I
:J:
1
~
>
4
0.6 -
I
""
I
""
~
V
./
'""'
-30 -40
0.3
I··
~
-10 -20
0.4
5
0.5
o
o
.!
.1
VCC=5V
VIO=-O.2V
TA=25°C
./
/
I
I\..
"
-50 -60
o
o
-70 -80
6
10
va
SUPPLY VOLTAGE
100
No Load
Inpu18 Open
TA-25°C
80
~
70
i
80
I
U
60
t
40
Q,
~
u
9
20
Figure 5
SUPPLY CURRENT
Ib
I
16
~
V
/
30
V
20
10
o
o
V
~
25
30
35
IOL - Low·LeveI Output Current - mA
Figure 4
90
V
~ 0.1
IoH - High-level OUtput Current - mA
~
~
V
V
2345678
VCC - Supply Voltage - V
Figure 6
lExAs
~
INSIRUMENfS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
40
uA9637AC
DUAL DIFFERENTIAL LINE RECEIVER
SLL.S111A- 02609, SEPTEMBER 1990 - REVISED FEBRUARY 1993
APPLICATION INFORMATION
5V
Twisted Pair
5V
1/2 uA9638AC
Figure 7. RS-A System Applications
1ExAs
..If
INSIRUMENTS
POST OFFICE BOX 655303 • DAu.AS, TEXAS 75265
2-S89
2-990
uA9638C
DUAL HIGH·SPEED DIFFERENTIAL LINE DRIVER
SLLSll2A- 0261
OCTOBER 1980- REVISED MARCH 1993
o OR P PACKAGE
•
Meets EIA Standard RS-422·A
•
Operates From a Single 5-V Supply
(TOP VIEW)
•
TTL-and CMOS-Input Compatibility
•
•
Output Short-Circuit Protection
•
Designed to Be Interchangeable With
Fairchild 9638
V C C [ ] 8 1Y
Schottky Circuitry
1A
2
7
1Z
2A
GND
3
4
6
5
2Y
2Z
logic symbol t
description
The uA9638C is a dual high-speed differential line
driver designed to meet EIA Standard RS-422-A.
The inputs are TTL- and CMOS-compatible and
have input clamp diodes. Schottky-diodeclamped transistors are used to minimize
propagation delay time. This device operates from
a single 5~V power supply and is supplied in an
8-pin package.
1A
2A
t>
2
3
~
8
7
6
5
1Y
1Z
2Y
2Z
t This symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
logic diagram
The uA9638C is characterized for operation from
Q·C to 7Q·C.
1A~1Y
~1Z
2A-4>P:
schematics of inputs and outputs
EQUIVALENT OF EACH INPUT
TYPICAL OF ALL OUTPUTS
Vce
VCC
4kQNOM
Input
9.6 Q NOM
Output
GND
Copyright © 1993. Texas Instruments Incorporated
TEXAS . "
INSIRUMENTS
POST OFFICE BOX 655303 • DALlAS. TEXAS 75265
2--$91
uA9638C
DUAL HIGH-SPEED DIFFERENTIAL LINE DRIVER
Su.9112A-D2612, OCTOBER 198Q-REVISED MARCH 1993
absolute maximum ratings over operating free-air temperature range
(unles~
otherwise noted)
Supply voltage range, Vee (see Note 1) .............................................. -0.5 V to 7 V
Input voltage range, VI .............................................................. -0.5 V to 7 V
Continuous total power dissipation ..................................... See Dissipation Rating Table
Operating free-air temperature range .................................................. O°C to 70°C
Storage temperature range ....................................................... -65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from 10 seconds ...................................... 260°C
NOTE 1: Voltage values except differential output voltages are with respect to network ground terminal.
DISSIPATION RATING TABLE
=
TA =25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
TA 70°C
POWER RATING
o
725mW
5.8mwrc
464mW
P
1000 mW
8.0mWre
640mW
PACKAGE
i
recommen d ed operat ng con d"Itons
Supply voltage, Vee
MIN
NOM
MAX
4.75
5
5.25
2
High-level input voltage, VIH
Low-level Input voltage, VIL
High-level output current, IOH
low-level output current, IOL
Operating free-air temperature, TA
0
TEXAS ~
INSIRUMENTS
2-S92
POST OFFICE BOX 655303 • DAUAS, TEXAS 75265
UNIT
V
V
0.8
V
-50
mA
50
mA
70
°e
uA9638C
DUAL HIGH-SPEED DIFFERENTIAL LINE DRIVER
Sll.S112A-D2612, OCTOBER 1980-REVISED MARCH 1993
electrical characteristics over operating free-air temperature range (unless otherwise noted)
TEST CONDITIONS
PARAMETER
Input clamp voltage
Vee = 4.75 V,
11=-18mA
VOH
High-level output voftage
Vee = 4.75 V,
VIL=0.8V
VIH = 2V,
VOL
Low-level output voltage
Vee = 4.75 V,
10L= 40 rnA
VIH = 0.2 V,
IV OD11
Differential output voftage
Vee = 5.25 V,
10=0
IV OD21
Differential output voltage
aIVoDI
Change in magnitude of
diferential outp:rt voftage*
Voe
Common-mode output voftage§
alVoel
Change In magnitude of
common-mode output voltage*
10
Output current with power off
VIK
MIN
IOH=-10mA
2.5
10H =-40 rnA
2
TYpt
MAX
UNIT
-1
-1.2
V
3.5
VIL=0.8V,
V
0.5
2VOD2
RL= 1000,
VO=6V
VO=-0.25V
Vee=O
V
V
2
Vee = 4.75 Vto 5.25 V,
See Figure 1
V
",0.4
V
3
V
",0.4
V
0.1
100
-0.1
-100
t1A
",100
VO=-0.25Vt06V
-200
t1A
t1A
t1A
-150
rnA
II
Input current
Vee = 5.25 V,
VI =5.5V
50
IIH
High-level Input current
Vee = 5.25 V,
VI =2.7V
25
IlL
Low-level Input current
Vee = 5.25 V,
VI =0.5 V
lOS
Short-circuit output current'll
Vee = 5.25 V,
Vo=O
-50
All inputs at 0 V
45
65
rnA
Supply current (both drivers)
Vee = 5.25 V, No load,
ICC
t All typical values are at Vee = 5 V and TA = 25°C.
* a I VOD I and a I Voe I are the changes in magnitude of VOD and VOC, respectively, that occur when the input is changed from a high level to
a low level.
§ In EIA Standard R8-422-A, Voe, which is the average of the two output voftages wRh respect to ground, is called output offset voftage, Vas.
'II Only one output at a time should be shorted, and duration of the short circuR should not exceed one second.
switching characteristics, Vee
=5 V, TA =25°e
PARAMETER
idD
Differential-output delay time
ttD
Differential-output transition time
Skew
TEST CONDITIONS
CL= 15 pF,
RL= 1000,
See Figure 2
See Figure 2
TEXAS
MIN
TYP
MAX
10
15
ns
10
15
ns
1
UNIT
ns
~
INSIRUMENIS
POST OFFICE BOX 655303 • DAUAS, TEXAS 75265
2-993
uA9638C
DUAL HIGH·SPEED DIFFERENTIAL LINE DRIVER
SUS112A- 02612, OCTOBER 1980- REVISED MARCH 1!193
PARAMETER MEASUREMENT INFORMATION
Figure 1. Differential and Common-Mode Output Voltages
3V
1.Sv\----
InputJ1.SV
YOutput
R1
-J..-.I
fcID
I
1,1
Differential
Output
10%
OV
fcID
90%
1
Generator
2
3
5
"
1OUT
20UT
This symbol is in accordance with ANSI/IEEE Sid 91-1984
and IEC Publication 617-12.
logic diagram
a
1IN+~
7
lr
11N-
2IN+~
5
lr
21N-
10UT
6
20UT
The uA9639C is characterized for operation from
0·Cto70·C.
schematics of Inputs and outputs
TYPICAL OF ALL OUTPUTS
EQUIVALENT OF EACH INPUT
- - - - - - - i l I - - - VCC
VCC
Input
50 a NOM
aka
Output
Current
Source
Copyright © 1993, Texas Inslrum'llnts Inccrporaled
1ExAs ."
INSIRUMENTS
POST OFFICE BOX 655303
• DALlAS, TEXAS 75265
2-995
uA9639C
DUAL DIFFERENTIAL LINE RECEIVER
SLlS113A- D3OO9. OCTOBER 1986 - REVISED FEBRUARY 1993
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, Vee (see Note 1) .................................•........ . . .. -0.5 V to 7 V
Input voltage,VI ....................................................•..•.................. :t 15 V
Differential input voltage (see Note 2) ....................................................... :t 15 V
Output voltage range (see Note 1) ................................................. -0.5 V to 5.5 V
Low-level output current ...............................................•.................. 50 rnA
Operating free-air temperature range .................................................. o·e to 70·C
Storage temperature range ....................................................... -65·e to 150·e
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds ............................... 260·e
NOTES: 1. All voltage values. except differential inpUt voltage, are with raspect to the network ground terminal.
2. Oifferentlallnput voltage Is measured at the nonlnverting input with respect to the corresponding Inverting Input.
DISSIPATION RATING TABLE
TAs25°C
POWER RATING
OPERATING FACTOR
ABOVE TA 25·C
TA=70·C
POWER RATING
0
725mW
P
1000mW
5.8mWrC
8.0mWrC
464mW
'640mW
PACKAGE
=
recommended operating conditions
Supply voltage. VCC
MIN
NOM
MAX
UNIT
4.75
5
5.25
V
~
Common-mode input voltage, VIC
0
Operating free-air temperature, TA
",7
V
70
·C
electrical characteristics over recommended ranges of supply voltage,common-mode input
voltage, and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TYpt
MIN
MAX
0.2
v,-+
Positlveiloing input threshold voltage
See Note 3
v,--
Negative-going input threshold voltage
See Note 3
Vhys
Hysteresis (\IT+-VT-)
VOH
High-level output voltage
VIO = 0.2 V,
10=-1 mA
VOL
Low-level output voltage
VIO=-0.2V,
10=20mA
II
Input current
0.4
-0.2
0.35
IVI =-10V
lOS
Short-circuij output current§
VO=O.
VIO=0.2V
Supply current
VIO=-0.5V.
No load
mV
V
3.5
2.5
VCC=Ot05.5V, IVI=10V
ICC
V
V
-0.4*
70
See Note 5
UNIT
-40
0.5
V
1.1
3.25
-1.6
-3.25
-75
-100
mA
35
50
mA
mA
t All typical values are at Vce = 5 V. TA = 25°e.
*
The algebraic convention. in which the less positive (more negative) limit is designated as minimum, is used in this data sheet for threshold levels
only.
.
§ Only one output should be shorted at a time. and duration of the short circuij should not exceed one second.
NOTES: 3. The expanded threshold parameter is tasted with a 500-0 resistor in series with each input.
4. The input not under test is grounded.
switching characteristics, Vee
= 5 V, TA = o·e to 70·e
PARAMETER
TEST CONDITIONS
Propagation delay time, low-to-high-Ievel output
See Figure 1
Propagation delay time. high-to-Iow-Ievel output
2-S96
1ExAs'"
INSIRUMENTS
•
POST OFFICE sox _
DAllAS. TEXAS 75265
I
1
I
MIN
MAX I UNIT
851
ns
I
1
uA9639C
DUAL DIFFERENTIAL LINE RECEIVER
SLLSll3A- 03009, OCTOBER 1986 - REVISED FEBRUARY 1993
PARAMETER MEASUREMENT INFORMATION
VCC+
VCC+
Output
0,5V - - Input
(see Note B)
3920
Input
-0,5 V
50%
I
1,.
I
~tpLH
510
Output
CL=30pF
(see Note A)
TEST CIRCUIT
~tpHL
,.~
V
VOLTAGE WAVEFORMS
NOTES: A. CL includes probe and jig capacttance,
B. The input pulse is supplied by a generalor having Ihe following characteristics: Ir s 5 ns, If S 5 ns, PRR S 5 MHz, duty cycle = 50%.
Figure 1. Test Circuit and Voltage Waveforms
TYPICAL CHARACTERISTICS
OUTPUT VOLTAGE
OUTPUT VOLTAGE
VS
vs
DIFFERENTIAL INPUT VOLTAGE
DIFFERENTIAL INPUT VOLTAGE
4
4
I
3,5
>I
3
CI
2,5
..
!
~
~
~
0
'-
VCC=4.75V
TA =25"C
I
VIC=,.7V
0.5
o
I
i
!!
I
ii
i
VIC=,.7V
I Ii
I
I
!
CI
2.5
~
2
0
1.5
~
I
VCC=5.25V
TA=25"C ,I
III
I
100
II
I
I
VIC=O
II
0.5
-100 -75 -50 -25
0
25
50
75
VID - Differential Input Voltage - mV
1
II
VIC=,.7V
~
I
I
3
~
!
I
VIC=O
>I
.
i
VIC =0
i
1.5
~
!
I
2
I
3.5
o
I
I!
I
I
II
I!
VIC=,.7V
VIC=O
I
I
I
I
1
-100 -75 -50 -25
0
25
50
75
VID - Differential Input Voltage - mV
Figure 2
100
Figure 3
TEXAS
,If
INSIRUMENTS
POST OFFICE BOX 655303 • DAllAS, TEXAS 75265
2-a97
uA9639C
DUAL DIFFERENTIAL LINE RECEIVER
Sli.Sll3A- 03009. OCTOBER 1986 - REVISED FEBRUARY 1993
TYPICAL CHARACTERISTICS
LOW-LEVEL OUTPUT VOLTAGE
HIGH-LEVEL OUTPUT VOLTAGE
vs
vs
HIGH-LEVEL OUTPUT CURRENT
LOW-LEVEL OUTPUT CURRENT
0.6
5
VCC=5V
VIO=0.2V
TA = 25°C
4.5
>I
IlL
II
~
~
GI
3.5
!5
Q.
3
5
2.5
~
CII
X
~
~
I'~
'" "'-
2
1.5
0.5
o
o
-10
-20
0.4
~
!5
Q.
!5
" ",
-30
-40
-50
/
./
0.3
0
I
0.2
~
0.1
!..
"
-70
-60
o
o
-80
5
10
vs
SUPPLY VOLTAGE
100
80
f- NoLoed
Inputs Open
_ TA=25°C
70
I
U
a
Q.
:::I
III
I
u
9
60
./
50
/V
40
V
30
/
20
10
o
o
v
--'
2
V
3
4
5
6
7
VCC - Supply Voltage - V
Figure 6
2-$98
20
Figures
SUPPLY CURRENT
C
~:::I
15
25
30
35
IOL - Low-Level Output Current- mA
Figure 4
90
V
V
/
IOH - Low-Level Output Current - mA
~
V
V
oJ
I\...
I
:r
~
0.5
>I
4
VCC=5V
VIO=-O.2V
TA=25°C
1ExAs ~
INSIR.UMENTS
POST OFFICE BOX 655303 • DAU.AS. TEXAS 75265
8
40
uA9639C
DUAL DIFFERENTIAL LINE RECENER
SLLS113A- 03009, OCTOBER 1986- REVISED FEBRUARY 1993
APPLICATION INFORMATION
5V
5V
Twisted Pair
1/2 uA9638AC
Figure 7. RS-422-A System Applications
ThxAs
,If
INSIRUMENTS
POST OFFICE BOX 655303 • DAllAS, TEXAS 75265
2-S99
2-1000
3-1
3-2
TL16C450
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS037A-
•
Full Double Buffering Eliminates the Need
for Precise Synchronization
•
Adds or Deletes Standard Asynchronous
Communication Bits (Start, Stop, and
Parity) to or From the Serial Data Stream
•
•
•
•
•
•
•
•
NPACKAGE
(Top VIEW)
Programmable Baud Rate Generator Allows
Division of Any Input Reference Clock by 1
to (216 -1) and Generates an Internal 16 X
Clock
•
MARCH 1988
Vce
RI
000
OSR
CTS
MR
OUTl
OTR
RTS
OUT2
INTRPT
NC
AC
Al
04
05
06
07
Independent Receiver Clock Input
RCLK
SIN
SOUT
CSO
CS1
CS2
BAUOOUT
XTALl
XTAL2
OOSTR
OOSTR
Independently Controlled Transmit,
Receive, Line Status, and Data Set
Interrupts
Fully Programmable Serial Interface
Characteristics:
5-,6-,7-, or 8-Bit Characters
Even-, Odd-, or No-Parity Bit
Generation and Detection
1-, 1 1/2-, or 2-Stop Bit Generation
Baud Generation (dc to 256 kb/s
Per Second)
9
11
A2
ADS
CSOUT
OOIS
OISTR
OISTR
Vss
False Start Bit Detection
FNPACKAGE
(TOP VIEW)
Complete Status Reporting Capabilities
'I"(,)C\J~O{) o_8ffi~
of; III: Cl Cl ()
3-State TTL Drive Capabilities for
Bidirectional Data Bus and Control Bus
Cl Cl Cl Cl Cl Z
Line Break Generation and Detection
05
Internal Diagnostic Capabilities:
Loopback Controls for Communications
Link Fault Isolation
Break, Parity, Overrun, Framing Error
Simulation
•
•
Fully-Prioritized Interrupt System Controls
•
Easily Interfaces to Most Popular
Microprocessors
•
Faster Plug-In Replacement for National
Semiconductor NS16C450
Modem Control Functions (CTS, RTS, DSR,
DTR, RI, and DCD)
06
07
RCLK
SIN
NC
SOUT
CSO
CSl
CS2
BAUOOUT
6 5 4 3 2 1 44 434241 40
7
39
8
38
9
37
10
36
11
35
12
34
13
33
14
32
15
31
16
30
17
29
181920 2122232425262728
~ ~
III: II:
INTRPT
III: II: en I- en
~~~~~Z~~25~
xxgg
ee ~
CI) ()
NC - No internal connection
description
The TL16C450 is a CMOS version of an asynchronous communications element (ACE). It typically functions
in a microcomputer system as a serial input/output interface.
The TL16C450 performs serial-to-parallel conversion on data received from a peripheral device or modem and
parallel-to-serial conversion on data received from its CPU. The CPU can read and report on the status of the
Copyright © 1989, Texas Instruments Incorporated
TEXAS ...,
INSIR.UMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
·TL16C450
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS037A- D3096. MARCH 1988- REVISED APRIL 1989
description (continued)
ACE at any point in the ACE's operation. Reported status information includes: the type of transfer operation
in progress, the status of the operation, and any erro~ conditions encountered.
The TL16C450 ACE includes a programmable, on-board, baud rate generator. This generator is capable of
dividing a reference clock input by divisors from 1 to (216 -1) and producing a 16 X clock for driving the internal
transmitter logic. Provisions are also included to use this 16 X clock to drive the receiver logic. Also included
in the ACE is a complete modem control capability and a processor interrupt system that may be software
tailored to the user's requirements to minimize the computing required to handle the communications link.
block diagram
Internal
Data Bus
D7-DO
~
Data
Bus
Buffer
I
Receiver
Buffer
Register
~
~
~
Une
Control
Register
.--
t--
Receiver
Shift
Register
~
SIN
Receiver
Timing and
Control
f+L
RCLK
Divisor
Latch (LS)
Baud
Generstor
15
BAUDOU1
DIvisor
Latch (MS)
AO ~
~
A2 ~
A1
CSO
Select
and
Control
Lagle
I
DOSTR ---1L
DOSTR -.!L
CSOUT
~
.rr-
VSS
~
Transmitter
Holding
Register
~
Modem
Control
Register
~
XTAL1 ~
XTAL2
VCC
~
•
-1L..
-1L
CS1
CS2 --1L
ADS ~
MR ~
DISTR -ADISTR ~
DDIS
Transmitter
Timing and
Control
Une
Status
Register
40
20
}
Power
Supply
......
*i
Transmitter
Shift
Register
~
~
Modem
Control
logic
Modem
Status
Register
Interrupt
Enabla
Register
I/O
~
I--
I
Interrupt
Control
Logic
I
Pin numbers shown are for the N package.
1ExAs ."
INSIRUMENTS
POST OFFICE BOX 655303 • DAllAS. TEXAS 75265
SOUT
RTS
C'fS
DTR
DSR
DCD
~
~ Ri
~
~
Interrupt
Register
r-1L-
30
OUT 1
OUT 2
INTRPT
TL16C450
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SUS037A-D3096, MARCH 1988-REVISEDAPRIL 1989
Terminal Functions
PIN
NAME
AO
AI
A2
NO.t
28
27
26
I/O
DESCRIPTION
I
Register select. Three inputs used during read and write operations to select the ACE register to read from
or write to. Refer to Table 1 for register addresses. also refer to the address strobe (ADS) signal description.
Address strobe. When ADS Is active (low). the register select signals (AO, AI, and A2) and chip select
signals (OSO, CS I, CS2) drive the internal select logic directly; when high, the register select and chip select
signals are held in the state they were In when the low-to-high transition of ADS occurred.
Baud out. 16 X clock signal for the transmitter section of the ACE. The clock rate is established by the
reference oscillator frequency divided by a divisor specified by the baud generator divisor latches.
BAUDOUT may also be used for the receiver section by tying this output to the RCLK input.
ADS
25
I
BAUDO
UT
15
0
CSO
CSI
CS2
I
Chip select. When active (high and low, respectively). these three inputs select the ACE. Refer to the ADS
signal description.
CSOUT
12
13
14
24
0
CTS
36
I
Chip select out. When CSOUT is high, it indicates that the ACE has been selected by the chip select Inputs
(CSO, CSI. and CS2). CSOUT is low when the chip is deselected.
Clear to send. CTS is a modem status Signal whose condition can be checked by reading bit 4 (CTS) of the
modem status register. Bit 0 (DCTS) of the modem status register indicates that this signal has changed
state since the last read from the modem status register. Ifthe modem status interrupt Is enabled when CTS
changes state, an interrupt is generated.
DO
01
02
03
04
05
06
07
VO
Data bus. Eight 3-state data lines provide a bidirectionat path for data, control. and status information
between the ACE and the CPU.
OeD
I
2
3
4
5
6
7
8
38
I
Data carrier detect. DCD is a modem status signal whose condition can be checked by reading bit 7 (DCD)
of the modem status register. Bit 3 (ODeD) of the modem status register indicates that this signal has
changed state since the last read from the modem status register. Iflhe modem status interrupt Is enabled
when the OeD changes state, an interrupt is generated.
DDIS
23
0
DISTR
DISTR
22
21
I
Driver disable. This output is active (high) when the CPU is not reading data. When active, this output can
be used to disable an external transceiver.
Data input strobes. When either input Is active (high or low, respectively) while the ACE is selected, the CPU
is allowed to read status information or data from a selected ACE register. Only one of these inputs is
required for the transfer of data during a read operation; the other Input should be tied in Its Inactive state
(i.e., DISTR tied low or DISTR tied high).
DOSTR
DOSTR
19
18
I
Data output strobes. When either input is active (high or low. respectively), while the ACE Is selected, the
CPU is allowed to write control words or data into a selected ACE register. Only one of these inputs is
required to transfer data during a write operation; the other input should be tied in Its inactive state O.e.,
DOSTR tied low or DOSTR tied high).
DSR
37
I
Data set ready. DSR Is a modem status signal whose condition can be checked by reading bit 5 (DSR) of
the modem status register. Bit 1 (DDSR) oflhe modem status register indicates that this signal has changed
state since the last read from the modem status register. If the modem status Interrupt is enabled when the
DSR changes state, an' interrupt is generated.
DTR
33
0
Data terminal ready. When active Oow), DTR informs a modem or data set that the ACE is ready to establish
communication. DTR Is placed in the active state by setting the DTR bit of the modem control register to a
high level. DTR is placed in the inactive state either as a result of a master reset or during loOP mode
operation or resetting bit 0 (DTR) of the modem control register.
t Pin numbers shown are for the N package.
1ExAs ."
INSIRUMENTS
POST OFFICE sex 655303 • DAUAS. TEXAS 75265
3-5
TL16C450
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SUS037A- 03096, MARCH 1988- REVISEOAPRIL 1989
Terminal Functions (continued)
PIN
NAME
INTRPT
NO.t
30
VO
DESCRIPTION
0
Interrupt. When active (high), INTRPT informs the CPU that the ACE has an interrupt to be serviced. Four
conditions that cause an interrupt 10 be issued are: a receiver error, received data is available, the transmitter
holding register is empty, and an enabled modem status interrupt. The INTRPT output Is reset ~nactivated)
either when the interrupt is serviced or as a result of a master reset.
Master reset. When active (high), MR clears most ACE registers and sets the state of various output signals.
Refer to Table 2.
Outputs 1 and 2. User-designated output pins that are set to their active states by setting their respective
modem control register bits (OUT 1 and OUT2) high. OUT 1 and OUT2 are set to their inactive (high) states
as a result of master reset or during loop mode operations or by resetting bit 2 (OUT 1) or bit 3 (OUT 2) of
theMCR.
MR
35
I
OUT1
OUT2
34
31
0
RCLK
9
39
I
RI
RTS
32
0
Request to send. When active, informs the modem or data set that the ACE is ready to transmit data RTS
is set to its active state by setting the RTS modem control register bit and is set to its inactive (high) state
either as a result of a master reset or during loop mode operations or by resetting bit 1 (RTS) of the MCR.
SIN
SOUT
10
11
I
0
Serial input. Serial data input from a connected communications device.
Serial output. Composite serial data output to a connected communication device. SOUT is set to the
marking (logiC 1) state as a result of MR.
5-V supply voltage
Supply common
External clock. Connects the ACE to the main timing reference (clock or crystaQ.
I
Receiver clock. The 16 X baud rate clock for the receiver section of the ACE.
Ring indicator. RI is a modem status signal whose condition can be checked by reading bit 6 (RI) of the
modem status register. Bit 2 (TERI) of the modem status register indicates that the Ai'lnput has transltloned
from a low to a high state since the last read from the modem status register. Ifthe modem status Interrupt
is enabled when this transition occurs, an interrupt is generated.
40
VCC
20
VSS
XTAL1
16
VO
XTAL2
17
t Pin numbers shown are for the N package.
absolute maximum ratings over free-air temperature range (unless otherwise noted)
Supply voltage range, Vee (see Note 1) .............................................. -0.5 V to 7 V
Input voltage range at any input, VI .... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.5 V to 7 V
Output voltage range, Vo ........................................................... -0.5 V to 7 V
Continuous total dissipation at (or below) 70·C free-air temperature: FN package. .. ..... . .... 1100 mW
N package ............... 800 mW
Operating free-air temperature range .................................................. O·C to 70·C
Storage temperature range ....................................................... -65°C to 150°C
Case temperature for 10 seconds: FN package .............................................. 260·C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: N package ..................... 260·C
NOTE 1: All voltage values are with respect to VSS.
recommended operating conditions
MIN
4.75
2
-0.5
0
Supply voitage, VCC
High-level Input voltage, VIH
Low-level input voltage, VIL
Operating free-air temperature, TA
1ExAs ."
INSIRUMENIS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
NOM
5
MAX
5.25
VCC
0.8
70
UNIT
V
V
V
·C
TL16C450
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS037A- 03096, MARCH 1988 - REVISED APRIL 1989
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
MAX
UNIT
PARAMETER
TEST CONDITIONS
MIN TYpt
VOH*
High-level output voltage
IOH=-l rnA
VOL*
Low-level output voltage
IOL= 1.SmA
Ilkg
Input leakage current
VCC = 5.25 V,
VI = 0 to 5.25 V,
VCC = 5.25 V,
Va = 0 Vto 5.25 V,
IOZ
High-Impedance output current
ICC
Supply current
V
2.4
0.4
V
VSS=O,
All other pins floating
.,10
JlA.
VSS=O,
Chip selected, write mode,
or chip deselected
.,20
JlA.
10
rnA
VCC = 5.25 V,
TA = 25°C,
SIN, DSR, DCD, CTS, and RI at 2 V,
XTAL1 at 4 MHz,
All other inputs at o.a V,
No load on outputs,
Baud rate = 50 kbls
CXTAL1
Clock input capacitance
CXTAl2
Clock output capac Hance
CI
Input capacitance
Co
Output capacitance
VCC=O,
f= 1 MHz,
All other pins grounded
VSS=O,
TA = 25°C,
15
20
pF
20
30
pF
S
10
pF
10
20
pF
t All tyPIcal values are at VCC = 5 V. TA = 25°C.
:j: These parameters apply for all outputs except XTAl2.
system timing requirements over recommended ranges of supply voltage and operating free-air
temperature
PARAMETER
FIGURE
Cycle time, read (tw 7 + tda
MIN
MAX
UNIT
lew
+ td9)
Cycle time, wrHe (tws + td5 + Ids)
tW5
Pulse duration, address strobe low
2,3
15
ns
twa
Pulse duration, wrHe strobe
2
ao
ns
tw7
Pulse duration, read strobe
3
aD
ns
twMR
Pulse duration, master reset
tsul
Setup time, address
IeR
175
ns
175
ns
1000
ns
2,3
15
ns
2,3
15
ns
2
15
ns
ns
ns
tsu2
Setup time, chip select
lsu3
Setup time, data
thl
Hold time, address
2,3
0
th2
Hold time, chip select
2,3
0
1h3
Hold time, wrHe to chip select
2
20
ns
1h4
Hold time, wrHe to address
2
20
ns
1h5
Hold time, data
2
15
ns
ths
Hold time, read to chip select
3
20
ns
th7
Hold time, read to address
3
20
ns
td4§
Delay time, select to write
2
15
ns
1d5§
Delay time, address to write
2
15
ns
Ids
td7§
Delay time, wrHe cycle
2
ao
ns
Delay time, chip select to read
3
15
ns
Ida§
Delay time, address to read
3
15
ns
3
ao
ns
Delay time, read cycle
1d9
§ Only applies when ADS is low.
INSIRUMENTS
1ExAs ""
POST OFFICE BOX 655303 • DALlAS, TEXAS 75265
3-7
TL16C450
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS037A-D3096, MARCH 1988-REVISEDAPRIL 1988
system switching characteristics· over recommended ranges of supply voltage and operating
free-air temperature
FIGURE
TEST CONDITIONS
MIN
twl
Pulse duration, clock high
1
f = 9 MHz·maximum
50
tw2
Pulse duration, clock low
1
f = 9 MHz maximum
50
PARAMETER
id3
Delay time, select to CS output
2,3
CL= 100 pF
idl0
Delay time, read to data
3
CL= 100 pF
idll
Delay time, read to floating data
3
CL= 100 pF
tdis(R)
Read tei driver disable
3
CL= 100 pF
MAX
UNIT
ns
ns
ns
ns
ns
ns
70
60
0
60
60
baud generator switching requirements over recommended ranges of supply voltage and
operating free-air temperature
PARAMETER
FIGURE
TEST CONDITIONS
CLK+l,
CLK+l,
MIN
MAX
UNIT
twa
Pulse duration, BAUDOUT low
1
f=6.25 MHz,
CL= lOOpF
tw4
Pulse duration, BAUDOUT high
1
f= 6.25 MHz,
CL= lOOpF
idl
Delay time, BAUDOUT low to high
1
CL-l00pF
125
ns
id2
Delay time, BAUDOUT high to low
1
CL=100pF
125
ns
80
ns
80
ns
receiver switching characteristics over recommended ranges of supply voltage and operating
free-air temperature
PARAMETER
td12
FIGURE
Delay time, RCLK 10 sample
TEST CONDITIONS
MIN
id13
Delay time, stop to set Interrupt
4
id14
Delay time, read RBRlLSR to reset Interrupt
4
MAX
UNIT
ns
100
4
1
RCLK
cycles
1
140
CL=lOOpF
ns
transmitter switching characteristics over recommended ranges of supply voltage and operating
free-air temperature
MIN
MAX
5
8
24
baudout
cycles
5
8
8
baudoul
cycles
PARAMETER
FIGURE
id15
Delay time, Initial write THR to transmit start
id16
Delay time, stop to Interrupt
id17
Delay time, write THR to reset interrupt
TEST CONDITIONS
UNIT
\
5
id18
Delay time, initial write to Interrupt (THRE)
5
id19
Delay lime, read IIR to reset Interrupt (THRE)
5
CL= 100pF
16
CL= lOOpF
140
ns
32
baudout
cycles
140
ns
modem control switching characteristics over recommended ranges of supply voltage and
operating free-air temperature
PARAMETER
MIN
MAX
FIGURE
TEST CONDITIONS
id20
Delay time, write MCR to output
6
CL=loopF
100
id21
Delay time, modem Input to set Interrupt
6
CL= lOOpF
170
lid22
Delay time, read MSR to reset interrupt
-
.
6
1ExAs
140
..If
INSIRUMENTS
POST OFFICE BOX 665303 • DALLAS, TEXAS 75265
UNIT
ns
ns
I
ns
TL16C450
ASYNCHRONOUS COMMUNICATIONS ELEMENT
Su.s037A- 03096, MARCH 1988 - REVISED APRIL 1989
PARAMETER MEASUREMENT INFORMATION
~tw1
2XTAL1
or
RCLK
(9 MHz Max)
I
I
~2V
~
r-
'\....J O.BV
I
I
~tw2
.------ N
-------~~
XTAL1
__JLJ-
BAUDOUT
(1/1)
BAUDOUT
(1/2)
BAUDOUT
(1/3)
BAUDOUT
(1/N)
(N)3)
1-,.,. ,
Cycles ~
~
I
~ (N~)XTAL1~
Cycles
Figure 1. Baud Generator Timing
TEXAS'"
INSIRUMENTS
POST OFFICE BOX 655303 • OAUAS, TEXAS 75265
TL16C450
ASYNCHRONOUS COMMUNICATIONS ELEMENT
Su.s037A-D3096, MARCH 1988-REVISEDAPRIL 1989 )
PARAMETER MEASUREMENT INFORMATION
AO-A2
CSO, CS1, CS2
CSOUT
OOSTR,
OOSTR
00-07
t Applicable only when ADS is tied low.
Figure 2. Write Cycle Timing
. 'TExAs'"
INSIRUMENTS
3-10
POST OFFICE BOX 655303 • DAUAS, TEXAS 75265
TL16C450
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS037A- 03096, MARCH 1989- REVISED APRIL 1989
PARAMETER MEASUREMENT INFORMATION
j4- tsu1---.1
-.j !4= th1
I
AO-A2
=>¢
Valid
~tsu2
1l1li
I
CSO,CS1,CS2
(~
I
CSOUT
~~~
Valldt
lh6 -+--i
I
I
~ tw7-J
I I)
tel7t~
I{
I '---
14-- tel9 ------.~
X X
telIS(R)
DDIS
,
~td3t
j4- th7t~
14- td6 t---.l
_ _ _ _ _J
I
X X'-:---
Valid
~td3t
---+1I . . .14-vI
I
-tt ~lh2
I
--.....J,.IV
X"'-y,-a-lId-t-X=
I
Active
I
~----
h
~
II \l II JI
telis(R)
I
I
i+ tel10~ j+-- td11----1
00-07
---------c(
Valid Data
j-.-
t Applicable only when ADS is tied low.
Figure 3. Read Cycle Timing
1ExAs
~
INSIRUMENTS
POST OFFICE BOX 655303 • OAUAS, TEXAS 75265
3-11
TL16C450
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLl.S037A-D3096, MARCH 1988-REVISEDAPRIL 1989
PARAMETER MEASUREMENT INFORMATION
RClK
n
n
Jl
I
r_
I
~ j4-1d12
BClKs
r-L
SAMPLE
CLOCK
SIN
\ , Start
;-o:~:~
Parity
7
Stop
"--J
SAMPLE
CLOCK _ _-'--_--1._
INTRPT
(RDRILSI)
I
I:
td13
__________________~r-~~
,
X
DISTR, DISTR
(RD RBR/LSR) _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _- J
I
td14~
Active
>k
rA-
Figure 4. Receiver Timing
1d19~
DISTR (RD IIR)
_ _ _ _ _1~'--Figure 5. Transmitter Timing
1ExAs
..If
INSlRUMENfS
3,-12.
I
14-
POST OFFICE BOX 655303 • DAllAS, TEXAS 75265
TL16C45.0
ASYNCHRONOUS COMMUNICATIONS ELEMENt
SLLS037A - 03096, MARCH 1988 - REVISED APRIL 1!189
PARAMETER MEASUREMENT INFORMATION
DOSTR (WR MeR)
~1ct!o
I
RTS,DTR
OUT1,OUT2
\
0
1ct!1 -tltfI
INTRPT
(MODEM)
~
I
I
I
i414----I~~ 1ct!2
I
DISTR (AD MSR)
/
'\
l
I
I
I
I
--------"\. . ._____---J)I<>t- ...,
Figure 6. Modem Control Timing
'.
1ExAs
"
~
INSIRUMENTS
POST OFFICE BOX 655303 • DALlAS, TEXAS 75265
3'-13
TL16C450
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS037A-D3096, MARCH 1988-REVlSEDAPRIL 1989
APPLICATION INFORMATION
P"'""
07-00
"-
RTS
OTR
INTRPT
RESET
OSR
MR
AO
A1
A1
P
A2
A2
B
u
a
-
ADS
..--
DOSTR
L
CTS
TL16C450
(ACE)
Ai
XTAL1
1
!
<
?-
DISTR
CS
CS2
XTAL2
CS1
BAUDOUT
CSO
RCLK
-r
0
3.072
MHz
T
L..c::
Figure 7. Basic TL16C450 Configuration
Receiver
Disable
- - - - - , WR
~~-----'------~~--------------~DOSTR
Microcomputer
System
Data Bus
TL16C450
(ACE)
Oats Bus
07-00
8-Blt
Bus Transceiver
L..-------4-------~
OOIS
Driver
Dlssble
Figure 8. Typical Interface for a Hlgh-Capacity Data Bus
3-14
>
OCD
AO
H
EIA232-D
Drivers
and
Receivers
DOSTR
INTR
U
SIN
OISTR
MEMWorl/ON
C
SOUT
07-00
MEMRor VOR
POST OFFICE sox 655303 • DAUAS, TEXAS 75265
;;::::;
":"
TL16C450
ASYNCHRONOUS COMMUNICATIONS ELEMENT
Su.s037A- 03096, MARCH 1988- REVISED APRIL 1988
APPLICATION INFORMATION
TL16C450
XTAL1
A16-A23I======:::::;--;::::~~
Alternate
Xtal Control
16
A16-A23
XTAL2
12
CSO
BAUDOUT
13
Address
Decoder
15
RCLI< 9
CS1
14
17
CS2
20
CPU
25
ADS I---+------------~ ADS
OUT1
35
OUT2
MR
AO-A2
Ai
DO-D7
DCD
PHI1 PHI2
DSR
CTS
PHI1 PHI2
ADS
34
31
39
5V
38
8
37
6
36
5
RSTO
21
RO
DISTR
TCU
18
WR
SOUT 11
DOSTR
SI.N
ADO-AD15
INTRPT
CSOUT
22
2
DDIS
DISTR
NC
DOSTR
-::-
40
GND
(VSS)
10
3
30
24
23
7
29
-::-
EIA·232·D
Connector
5V
(VCC)
Figure 9. Typical TL16C450 Connection to a CPU
TEXAS . "
INSIRUMENfS
POST OFFICE BOX 65S303 • DAUAS, TEXAS 75265
3-15
TL16C450
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS037A-03096, MARCH 1988-REVISEDAPRIL 1989
PRINCIPLES OF OPERATION
Table 1. Register Selection
DLABt
A2
A1
AO
0
L
L
L
Receiver buffer (read), transmitter holding register (wrfte)
REGISTER
0
L
L
H
Interrupt enable
X
L
H
L
Interrupt identification (read only)
X
L
H
H
Une control
X
H
L
L
Modem control
X
H
L
H
Unestatus
X
H
H
L
Modem status
X
H
H
H
Scratch
1
L
L
L
DMsor latch (LSB)
DMsor latch (MSB)
1
L
L
H
t The divisor latch access bit (DLAB) is the most significant bit of the line control register. The DLAB signal is controlled
by writing to this bit location (see Table 3).
Table 2. ACE Reset Functions
REGISTERISIGNAL
RESET
CONTROL
RESET STATE
Interrupt Enable Register
Master Reset
All bHs low (0,-3 forced and 4-7 permanent)
Interrupt Identification Register
Master Reset
Bit 0 is high, bits 1 and 2 are low, and bfts 3 -7 are
permanently low
Une Control Register
All bits low
Modem Control Register
Master Reset
All bits low
Une Status Register
Master Reset
Bits 5 and 6 are high, all other bits are low
Modem Status Register
Master Reset
Bits 0-3 are low, bits 4-7 are input signals
SOUT
Master Reset
High
INTRPT (receiver error flag)
Read LSR/MR
Low
INTRPT (received data available)
Read RBR/MR
Low
INTRPT (transmitter holding register empty)
Read IIR/Write
THR/MR
Low
INTRPT (modem status changes)
Read MSR/MR
Low
OUT 2
Master Reset
High
RTS
Master Reset
High
DTR
Master Reset
High
OUT 1
Master Reset
High
Scratch Register
Master Reset
No effect
Divisor Latch (LSB and MSB) Register
Master Reset
No effect
Receiver Buffer Register
Master Reset
No effect
Transmitter Holding Register
Master Reset
No effect
1ExAs . "
INSIRUMENIS
3-16
POST OFFICE BOX 655303 • DALlAS, TEXAS 75265
TL16C450
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SUS037A-03096. MARCH 1988-REVISEOAPRIL 1989
PRINCIPLES OF OPERATION
accessible registers
The system programmer, via the CPU, has access to and control over any of the ACE registers that are
summarized in Table 3. These registers are used to control ACE operations, receive data, and transmit data.
Descriptions of these registers follow Table 3.
Table 3. Summary of Accessible Registers
REGISTER ADDRESS
Bit
No.
0
1
ODLAB.O
ODLAB.O
Rcelver
Burrer
Regl...,
(Reed
Only)
Tr.,.mltt.,
RBR
DataB~o*
OataBft 1
1 DLAB.O
2
Interrupt
Enable
Register
IER
Interrupt
Ident.
Reglat.,
(Reed
Only)
THR
IER
IIR
Data Bit 0
Enable
Received
Data
Available
Interrupt
(ERBF)
VII
Interrupt
Pending
Enable
Transmitter
Holding
Register
Empty
Interrupt
(ETBE)
Interrupt
10
8ft (0)
Holding
Register
(Write
Only)
OataB~
1
Enable
Receiver
2
Data Bft 2
DataBR2
UneStatus
Irterrupt
3
U,.
5
4
•
7
ODLAB=1
1
DLAB
=0
Scratch
Regl"'r
Divisor
latch
(LSB)
latch
(MSB)
Control
Reg....r
LCR
IIocIIIm
Una
Control
Reglat.,
Stetu.
Regl. . .
Modem
Statue
Reglat.
LCR
MCR
LSR
MSR
SCR
DLL
DLM
Data
Terminal
Ready
(OTA)
Data
Ready
(OR)
Oefta
Clear
to Send
(OCTS)
BftO
BftO
Bft8
Overrun
Error
(OE)
.Defta ..
Data
Set
Ready
(ODSR)
Bft1
Bft1
Bft9
Out 1
Parity
Erra(PE)
Trailing
EdgeRlng
Indicata(TERI)
Bft2
Bft2
Bft10
Delta
Data
Carrier
Detect
(OOCO)
Bft3
Bft3
Bit 11
W g a:W0~
z
I
~ ~
9 8 7 6 5 4 3 2 1 68 67 66 65 64 83 62 61
SOUT1
DTR1
RTS1
CTS1
DBO
DB1
DB2
DB3
DB4
DBS
DB6
DB7
GND
10
11
12
13
14
15
16
17
18
19
20
21
Vee
23
60
58 SUN
57 INIT
56 AFD
55 STB
54 GND
53 PDO
52 PD1
51 PD2
50 PD3
49 PD4
48 PDS
47 PD6
46 PD7
45 INTO
44 BDO
22
R'fSo 24
DTRO 25
SOUTO 26
V~~~~~M~~~D~~~~~~
ri
oooooO~~Or~NrOOOO
O
< 0~~
W0 ~ z z
~b~
00
a: 0
~
u:
1ExAs ~
INSTRUMENTS
3-28
INT1
59 INT2
POST OFFICE BOX 655303 • DAllAS, TEXAS 75265
TL16C451, TL16C452
ASYNCHRONOUS COMMUNICATIONS ELEMENTS
SUS053A.- D3284, MAY 1989 - REVISED JANUARY 1990
functional block diagrams
TL16C451
CTSO
....Q§BO
RLS...IlO
RIO
BTIi.O
ACE
1
DTRO
SOUTO
INTO
IHriO
CSO
B/
DBO-DB7
AO~
I.QW
/
~/
:7:
Select
and
Control
RE~~ -CLK
-
logic
BDO
/
/..!.
ERROR
SLCT
BUSY
B/
/
nit
Parallal
Port
--.fi
LP~g~
fI2Q-PD7
IN!I.
AFD
SUN
INT2
CS2
TL16C452
ACE
1
.kr§O
~O
RTSO
DTRO
SOUTO
INTO
RLS...IlO
RIO
~:
8/
DBO-DB7
/
,
~v
CTS1
DSR1
RUU21
RI1
SIN1
CS1
AO-A2
lOW
:z::
RESET
CLK
--
lOR -
ERROR
SLCT
BUSY
PE
Salect
and
Control
logic
,
ACE
2
8m1
DTR1
SOUT1
INTI
.
BDO
)~
t:::
R/
/
Parallel
Port
~
CS2
POST OFFICE BOX 655303 • DALlAS, TEXAS 75265
PDO-PD7
:t~
~m~
INT2
~9
TL16C451, TL16C452
ASYNCHRONOUS COMMUNICATIONS ELEMENTS
Su.s053A- D3284, MAY 1989- REVISED JANUARY 1990
Terminal Functions
PIN
NAMEt
AO
A1
A2
NO.
35
34
33
I/O
DESCRIPTION
I
Register select. Three Inputs used during read and write operations to select the register to read from
or write to. Refer to Table 1 for register addresses, also refer to the chip select signals (CSO. CS1. CS2).
ACK
68
I
Une printer acknowledge. This input goes low to Indicate a successful data transfer has taken place.
It generates a printer-port interrupt during its positive transition.
AFD
56
I/O
BOO
44
0
BUSY
66
I
CLK
COO
CS1 [VCC]
CS2
4
32
3
38
I/O
Une printer autofeed. This open-drain line provides the line printer with a low signal when
continuous-form paper is to be autofed to the printer. An internal pullup is provided.
Bus buffer output. This output Is active (high) when the CPU is reading data. When active. this output
can be used to disable an external transceiver.
Une printer busy. This is an input line from the line printer that goes high when the line printer is not ready
to accept data.
External clock. Connects the ACE to the main timing reference.
Chip selects. Each chip select enables read and write operations to Its respective channel. CSO and
CS1 select serial channels 0 and 1. respectively. and CS2 selects the parallel port.
CTSO
'C'ffi1
[GND]
28
13
I
Clear to send. CTS is an active-low modem status signal whose state can be checked by reading bit
4 (CTS) of the modem status register. Bit 0 (DCTS) of the modem status register indicates that this signal
has changed state since the last read from ·the modem status register. If the modem status interrupt is
enabled when CTS changes state. an interrupt is generated.
DBO
DB1
DB2
DB3
DB4
DB5
DBS
DB7
DSRO
DSR1
[GND]
14
15
16
17
18
19
20
21
31
5
I/O
Data bus. Eight 3-state data lines provide a bidirectional path for data, control. and status Information
between the TL16C451{TL16C452 and the CPU. DBO is the least significant bit (LSB).
I
Data set ready. DSR is an active-low modem status signal whose state can be checked by reading
bit 5 (DSR) ofthe modem status register. Bit 1 (DDSR) of the modem status register Indicates that this
Signal has changed state since the last read from the modem status register. If the modem status
Interrupt is enabled when the DSR changes state. an interrupt Is generated.
DTRO
DTR1 [NC]
25
11
0
Data terminal ready. When active Oow), DTR Informs a modem or data set that the ACE is ready to
establish communication. DTR is placed in the active state by setting the DTR bit of the modem control
register to a high level. DTR is placed in the Inactive state either as a result of a reset or during loop mode
operation or resetting bit 0 (DTA) of the modem control register.
ERROR
63
I
INIT
57
I/O
INTO
INT1 [NC]
45
60
0
INT2
59
0
Une printer error. This is an input line from the line printer. The line printer reports an error by holding
this line low during the error condition.
Une printer initialize. This open-drain line provides the line printer with a signal that allows the line printer
initialization routine to be started. An internal pullup is provided.
Interrupt. INTn is an active-high 3-state output that is enabled by bit 3 of the MCR. When active. INTn
Informs the CPU that the ACE has an Interrupt to. be serviced. Four conditions that cause an Interrupt
to be issued are: a receiver error, received data Is available. the transmitter holding register is empty,
and an enabled modem status interrupt. The INTn output is reset Oow) either when the Interrupt Is
serviced or as a result of a reset.
Printer port interrupt. This signal is an active-high 3-state output generated by the positive transition of
ACK. It Is enabled by bit 4 of the write control register.
lOR
37
I
RYW
66
I
I
Data read strobe. When lOR input is active Oow) while the ACE is selected. the CPU Is allowed to read
status Information or data from a selected ACE register.
Data write strobe. When lOW input is active Oow) while the ACE is selected. the CPU Is allowed to write
control words or data into a selected ACE register.
t Names shown In brackets are for the TL16C451.
1ExAs
,If
INSIRUMENTS
3-30
POST OFFICE BOX 655303 • DAUAS. lEXAS 75265
TL16C451, TL16C452
ASYNCHRONOUS COMMUNICATIONS ELEMENTS
SLLS053A- 03284, MAY 1989 - REVISED JANUARY 1990
Terminal Functions (continued)
PIN
VO
DESCRIPTION
1
I
Parallel data output enable. When low, this signal enables the write data register to the PDD-PD7Iines.
A high puts the PDO-PD7Iines in the high-impedance state allowing them to be used as inputs. LPTOE
is usually tied low for line printer operation.
53-46
1/0
PE
67
I
RESET
39
I
RIO
FU1 [GND)
30
6
I
RLSDO
RLSD1
[GND)
29
8
I
RTSO
RTS1 [NC)
24
12
0
Parallel data bits (0-7). These eight lines provide a byte-wide input or output port to the system. The
eight lines are held in a high-impedance state when LPTOE is high.
Line printer paper empty. This is an input line from the line printer that goes high when the printer runs
out of paper.
Reset. When active 60w), RESET clears most ACE registers and sets the state of various output
signals. Refer to Table 2.
Ring indicator. RI is an active-low modem status signal whose state can be checked by reading bit 6
(RI) of the modem status register. Bit 2 (TERI) of the modem status register indicates that the RI input
has transftioned from a low to a high state since the last read from the modem status register. If the
modem status interrupt is enabled when this transition occurs, an interrupt is generated.
Receive line signal detect. RLSDO is an active-low modem status signal whose state can be checked
by reading bit 7 ofthe modem status register. Bit 3 (DRLSD) ofthe modem status register indicates that
this signal has changed state since the last read from the modem status register. If the modem status
interrupt is enabled when RLSDO changes state, an interrupt is generated. This bit is low when a data
carrier is detected.
Request to send. When active (low), this signal informs the modem or data set that the ACE is ready
to transmit data. RTS is set to Its active state by setting the RTS modem control register bit and is set
to its inactive (high) state either as a result of a reset or during loop mode operations or by resetting bit
1 (RTS) of the modem control register.
SINO
SIN1
[GND)
SLCT
41
I
Serial input. Serial data input from a connected communications device.
65
I
58
VO
Line printer selected. This Is an input line from the line printer that goes high when the line printer has
been selected.
Une printer select. This open-drain line selects the printer when it is active (low). An internal pullup is
provided.
26
10
I
Serial output. Composite serial data output to a connected communication device. SOUT is set to the
marking Oogic 1) state as a result of reset.
STB
55
VO
Line printer strobe. This open-drain line provides communication synchronization between the
TL16C451/TL16C452 and the line printer. When it is active (low), it provides the line printer with a signal
to latch the data currently on the parallel port. An internal pullup is provided.
VCC
23,40,
64
2,7,9
22,27,42,
43,54,61
NAMEt
LPTOE
PDO-PD7
I SUN
SOUTO
soun
NO,
[NC)
GND
5-V supply voltage
Supply common
t Names shown In brackets are for the TL16C451.
POST OFFICE BOX 655303 • DALlAS, TEXAS 75268
TL16C451,TL16C452
ASYNCHRONOUS COMMUNICATIONS ELEMENTS
SLLS053A- 03284, MAY 1989 - REVISED JANUARY 1990
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, Vee (see Note'1) .............................................. -0.5 V to 7 V
Input voltage range at any input, VI ..................................... ,............ -0.5 V to 7 V
Output voltage range, Vo .......................................................... -0.5 V to 7 V
Continuous total power dissipation ...................................................... 1100 mW
Operating free-air temperature range ................................................. o·e to 70·e
Storage temperature range ....................................................... -65·e to 150·e
Case temperature for 10 seconds .......................................................... 260·C
NOTE 1: All voHage values are with respect to GND.
recommended operating conditions
MIN
4.75
2
-0.5
0
Supply voHage, VCC
High-level Input voHage, VIH
Low-level Input voltage, Vil
Operating free-air temperature, TA
NOM
5
MAX
5.25
VCC
0.8
70
UNIT
V
V
V
·C
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYpt
MAX
UNIT
IOH = -0.4 rnA on DBO-DB7
VOH
High-level output voHage
IOH = -2 rnA to 4 rnA on PDO-PD7
IOH = -0.2 rnA on INIT, AFD, STB. and 'SiJN
V
2.4
IOH = -0.2 rnA on all other outputs·
IOl = 4 rnA on DBO-DB7
VOL
low-level output voHage
IOl = 12 rnA on PDO-PD7
IOl = 10 rnA on INIT. AFD, STB, and SLiN (see Note 2)
0.4
V
.. 10
!IA
.. 20
!IA
10
rnA
IOl = 2 rnA on all other outputs
VI = 0 to 5.25 V.
Input leakage current
VCC=5.25V,
VSS=O,
All other pins floating
High-Impedance output current
Vo = Oto 5.25 V,
VCC=5.25V,
VSS=O,
Chip selected and wrHe mode, or chip deselected
ICC
Supply current
VCC = 5.25 V,
~S = 0,
SIN, DSR, i!iLSi5, CTS, and Ai at 2 V,
All other Inputs at 0.8 V.
XTAl1 at 4 MHz,
No load on outputs, Baud rate = 50 kilobits per second
CXTAl1
Clock input capacitance
15
20
pF
CXTAL2
Ci
Clock output capacHance
20
30
pF
6
10
pF
Ilkg
Input capac Hance
VCC=O,
TA=25·C,
VSS=O,
f= 1 MHz"
All others pins groul1!led
Output capacHance
20
pF
10
Co
t All typical values are at VCC = 5 V, TA = 25·C.
NOTE 2: INIT, AFD,S'i'B, and 'SiJN are open-collector output pins that each have an internal pullup to VCC. This will generate a maximum of
2 rnA of InternallOl per pin. In addition to this internal current, each pin will sink at least 10 mA while maintaining the VOL specification
of 0.4 V Max.
1ExAs..lf
INS1RI.JMENTS
3-32
POST OFFICE BOX fl65303 • OAUAS, TEXAS 75285
TL16C451, TL16C452
ASYNCHRONOUS COMMUNICATIONS ELEMENTS
SLLS053A- 03284, MAY 1989 - REVISED JANUARY 1990
system timing requirements over recommended ranges of supply voltage and operating free-air
temperature
FIGURE
PARAMETER
MIN
MAX
UNIT
tcR
Cycle time, read
i!-w7 + tdS + tdS)
175
tcw
Cycle time, write (twa + td5 + tds)
175
ns
ns
tw1
Pulse duration, clock high
1
50
ns
tw2
Pulse duration, clock low
1
50
tw5
Pulse duration, write strobe
2
80
twa
Pulse duration, read strobe
3
twRST
Pulse duration, reset
tsu1
Setup time, address
2,3
15
tsu2
Setup time, chip select
2,3
15
tsu3
Setup time, data
th1
2
15
Hold time, address
2,3
20
th2
Hold time, chip select
2,3
20
th3
Hold time, data
2
15
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
td3
Delay time, wrRe cycle
2
80
ns
1d4
Delay time, read cycle
3
80
ns
80
1000
system switching characteristics over recommended ranges of supply voltage and operating
free-air temperature
FIGURE
TEST CONDITIONS
td5
Delay time, read to data
PARAMETER
3
CL=100pF
1d6
Delay time, read to floating data
3
CL=100pF
ldis(R)
Read to driver disable
3
CL= 100pF
MIN
0
MAX
UNIT
60
ns
60
ns
ns
60
receiver switching characteristics over recommended ranges of supply voltage and operating
free-air temperature
PARAMETER
1d7
FIGURE
Delay time, RCLI< to sample
TEST CONDITIONS
MIN
4
td8
Delay time, stop to set interrupt
4
tdS
Delay time, read RBR/LSR to reset interrupt
4
MAX
100
1
1
140
CL=100pF
UNIT
ns
RCLI<
cycles
ns
transmitter switching characteristics over recommended ranges of supply voltage and operating
free-air temperature
PARAMETER
FIGURE
TEST CONDITIONS
MIN
MAX
UNIT
td10
Delay time, initial wrRe THR to transmit start
5
8
24
baudout
cycles
1d11
Delay time, stop to interrupt
5
8
8
baudout
cycles
1d12
Delay time, write THR to reset interrupt
5
1d13
Delay time, initial write to interrupt (THRE)
5
1d14
Delay time, read II R to reset interrupt (THRE)
5
1ExAs
CL= 100 pF
16
CL=100pF
140
ns
32
baudout
cycles
140
ns
..If
INSIRUMENTS
POST OFFICE BOX 655303 • OAUAS, TEXAS 75265
3-33
TL16C451, TL16C452
ASYNCHRONOUS COMMUNICATIONS ELEMENTS
SlLS053A-D3284, MAY 1989-REVlSEDJANUARY 1990
modem control switching characteristics over recommended ranges of supply voltage and
operating free-air temperature
FIGURE
TEST CONDITIONS
MAX
UNIT
id15
Delay time, write MCR to output
6
CL= 100pF
100
ns
td16
Delay time, modem input to set interrupt
6
CL= 100pF
170
ns
id17
Delay time, read MSR to reset Interrupt
6
CL=100pF
140
ns
PARAMETER
MIN
parallel port switching characteristics over recommended ranges of supply voltage and operating
free-air temperature
FIGURE
TEST CONDITIONS
td18
Delay time, write parallel port control to output
7
CL=l00pF
60
ns
td19
Delay time, write parallel port data to output
7
CL=100pF
60
ns
td20
Delay time, output enable to data
7
CL= 100 pF
60
ns
id21
Delay time, ACK to INT2
7
CL=l00pF
100
ns
PARAMETER
PARAMETER MEASUREMENT INFORMATION
~twl
I
CLK
I
r-
r-'\ 2V
~ 0.8 V
(9 MHz Max) . - - /
I
I
!4-tr-tw2
__JLt-
CLK
BAUDOUT
(1/1)
(see Note A)
BAUDOUT
(1/2)
BAUDOUT
(1/3)
BAUDOUT
(lIN)
(N)3)
II-------!
_
2Clock _
r
Cycles
-~
I
-I
L
1-
(N-2) Clock---!
Cyclee
-I
NOTE A: BAUDOUT is an internally generated signal used in the receiver and transmitter circuits to synchronize data.
Figure 1. Baud Generator Timing
1ExAs ."
INSIRUMENTS
3-34
POST OFFICE BOX _
• DALlAS. TEXAS 75265
MIN
MAX
UNIT
TL16C451, TL16C452
.ASYNCHRONOUS COMMUNICATIONS ELEMENTS
SLlS053A- D3284, MAY 1989 - REVISED JANUARY 1990
PARAMETER MEASUREMENT INFORMATION
AO-A2
~_________~_al_ld________~)<~_____ !
I
I
I
I
--~x:
I
I
I
I
I
I
I
I
X
Valid
th2
I 4
l+-tW5~
I..
I
I
I
I
I
I
I
I
I
tsu3
-./+-
I
J
-I
V
\l
------------«
I
td3
I
I+I
I
(+- th1~
taU2
J4- tau1 +1
DO-D7
I
~
I"
I
I
I
'--
th3-+i
Valid Data
I
)>-------------
Figure 2. Write Cycle Timing
1ExAs~
1NSIRUMENfS
POST OFFICE BOX 655303 • DAllAS, TEXAS 75265
3-35
TL16C451,TL16C452
ASYNCHRONOUS COMMUNICATIONS ELEMENTS
SLJ..S053A- 03284, MAY 1989- REVISED JANUARY 1990
PARAMETER MEASUREMENT INFORMATION
AO-A2
~;,....._ _ _"'_81_ld_ _ _ _~X,____~I
~I
~
CSO, CS1, CS2
__
_____
X'r-_____
Valid
i
th2~ i
I !+ Ieu2 +i Iw6 -.114- +'
1
r--¥
th1
j4- tau1 -+j
ldle(R)
~-.!
14- j4---+I-
---_ _ _ _-1,.1 1
1
Ix I
BOO
-J+----.l
00-07 ---------«
tcs
leu
----+!
ldls(R)
\...
1 -------
Y~
r4-
fcl6
Valid oats
">--
Figure 3. Read Cycle Timing
RCLK
(Internal elgnal only
same ae BAUOOUT)
---~
------.;.; j.-ld7
Sample Clock
(internal Signal Only)
SIN
\
-------------~~
G~I~~
7 ~
Parity
Start
Stop
I!
Sample
Clock
td8~
INTRPT
(RORJLSI)
-----~
ld9~
Lv-
iOR
(RO RBRJLSR)
Figure 4. Receiver Timing
1ExAs ..,
INSIRUMENfS
3--36
I
POST OFFICE BOX 655300 • DALlAS, TEXAS 7526S
TL16C451, TL16C452
ASYNCHRONOUS COMMUNICATIONS ELEMENTS
SUS053A- D3284. MAY 1989 - REVISED JANUARY 1990
PARAMETER MEASUREMENT INFORMATION
SOUT
\
tci10
INTRPT~
~R~
~
tci12
IOW(WRTHR)
Start
;--o:;;~~
-+I I.:
7
Stop
tci11
A
~
t--1
~~~.__________________~I~~
b--~
~ 1 ~ tci13
1 i+- 1
~
Parity
I~I
1
1_
~
V'
1
tci12
1
tci14
lOR (RD IIR)
~ 1+
--------------------------~~
Figure 5. Transmitter Timing
iOW(WRMCR)
1
1
1
~tci15
RTS,DTR
CTS, DSR,RLSD
tci15
~
\
X
\-j
/
\J
~
\
I
r
1
td16~
INTRPT
(MODEM)
td17
lOR (RDMSR)
14
1
~I
1
1
1
1
14-
Ai
td16
Figure 6. Modem Control Timing
1ExAs ."
INSIRUMENTS
POST OFFICE BOX 655303 • DAUAS. TEXAS 75265
3-37
TL16C451 , TL16C452
ASYNCHRONOUS COMMUNICATIONS ELEMENTS
SLLS053A- 03284, MAY 1989-REVISED JANUARY 1990
PARAMETER MEASUREMENT INFORMATION
lOW
\
~18
SUN,AFD,
S'fii, iNi'i'
If
~
X
\ '___--J/I
~I
1l1li
tcI19
POO_PD7 ________~~~----------------------------~){ri-----------1l1li
~I
fcI20
~ ~~------------------------------------------------A
\
\
JI
tcl21
1l1li
I
~I
INT2
Figure 7. Parallel Port Timing
1ExAs ."
INSIRUMENTS
3-38
POST OFFICE BOX 655303 • DAUAS, TEXAS 75265
I
1l1li
~
tcl21
TL16C451, TL16C452
ASYNCHRONOUS COMMUNICATIONS ELEMENTS
SLl.S053A- 03284. MAY 1989 - REVISED JANUARY 1990
APPLICATION INFORMATION
Data BUB
"/
<../
"
,/
ACE and
Printer
Port
/
"
AddrBBBBuB
~
Serial
Channel 0
Buffers
"'-
/
"
Control Bus
,/
)
/
Y
Option
Jumpers
g.Pln
D
Conn
25-Pln
Parallel
Port
RIC Net
I---
o
Conn
........
I---
Figure 8. TL16C451
Data Bus
<./
"
,/
"
)
Dual
ACE and
Printer
Port
/
9-Pln
o
Conn
........
,/
"
~
AddreBBBuB
Serial
Channel 0
Buffers
Serial
Channel 1
Buffers
/
9-Pln
D
Conn
........
"
~
Control Bus
,/
/
---i
Option
Jumpers
25-Pin
Psrallel
Port
RIC Net
~
o
Conn
........
Figure 9. TL16C452
1ExAs ..,
INSIRUMENTS
POST OFFICE BOX 655303 • DAUAS. TEXAS 75265
3-39
TL16C451,TL16C452
ASYNCHRONOUS COMMUNICATIONS ELEMENTS
Su.s053A- 03284, MAY 1989 - REVISED JANUARY 1990
PRINCIPLES OF OPERATION
Table 1. Register Selection
DLABt
A2
A1
AO
0
L
L
L
Receiver buffllr (read), transmitter holding register (write)
0
L
L
H
Interrupt enable
X
X
X
X
X
X
L
H
L
Interrupt identification (read only)
L
H
H
Line control
H
L
L
Modem control
H
L
H
Unestatus
H
H
L
Modem status
H
H
H
Scratch
REGISTER
1
L
L
L
Divisor latch (LSB)
1
L
L
H
Divisor latch (MSB)
t The divisor latch access bit (DLAB) is the most significant bit ofthe line control register. The DLAB signal
is controlled by writing to this bit location (see Table 3).
Table 2. ACE Reset Functions
RESET
CONTROL
REGISTER/SIGNAL
RESET STATE
Interrupt Enable Register
Reset
All bits low (0-3 forced and 4-7 permanent)
Interrupt Identification Register
Reset
Bit 0 is high, bits 1 and 2 are low, and bits 3-7 are
permanently low
Une Control Register
Reset
All bits low
Modem Control Register
Reset
All bits low
Line Status Register
Reset
Bits 5 and 6 are high, all other bits are low
Modem Status Register
Reset
Bits 0-3 are low, bits 4-7 are input signals
SOUT
Reset
High
INTRPT (receiver error flag)
Read LSR/Reset
Low
INTRPT (received data available)
Read RBR//Reset
Low
Read IIRlWrite
THR/Reset
Low
INTRPT (transmitter holding register empty)
INTRPT (modem status changes)
Read MSR/Reset
Low
OUT 2 (interrupt enable)
Reset
High
RTS
Reset
High
DTR
Reset
High
OUT 1
Reset
High
Scratch Register
Reset
No effect
DMsor Latch (LSB and MSB) Registers
Reset
No effect
Receiver Buffer Registers
Reset
No effect
Transmitter Holding Registers
Reset
No effect
1ExAs ."
INSTRUMENTS
POST OFFICE BOX 655303 • DAUAS, TEXAS 75265
TL16C451, TL16C452
ASYNCHRONOUS COMMUNICATIONS ELEMENTS
SLLS053A- 03284, MAY 1989- REVISED JANUARY 1990
PRINCIPLES OF OPERATION
accessible registers
The system programmer, via the CPU, has access to and control over any of the ACE registers that are
summarized in Table 3. These registers are used tQ control ACE operations, receive data, and transmit data.
Descriptions of these registers follow Table 3.
Table 3. Summary of Accessible Registers
REGISTER ADDRESS
BIt
No.
0
1
2
ODlAB .0
ODLAB.O
Recelv...
Regl_
(Read
Only)
Transmitter
Holding
Regl.er
(WrH.
Only)
RBR
Buffer
DataBftOt
DataBft1
Data Bit 2
1 DLABzO
2
3
4
5
8
7
Interrupt
Enabl.
Regl••r
Inte"upt
Ident.
Regl••r
(Read
Only)
Une
Control
Reglat...
Modem
Control
Reglater
Une
SIatua
Reglat...
Modem
Statue
Regl_
Scratch
Reglat.r
THR
IER
IIR
LCR
MCR
LSR
MSR
SCR
DLL
DLM
Data Bit 0
Enable
Received
Data
Available
Inlerrupt
(ERBF)
"crll
Interrupl
Pending
Word
Length
Select
BftO
(WLSO)
Data
Terminal
Reedy
(DTA)
Data
Ready
(DR)
Delta
Clear
10 Send
(DCTS)
BftO
Bit 0
BI18
DataBH 1
Enable
Transmitter
Holding
Register
Empty
Interrupt
(ETBE)
Interrupt
10
BR(O)
Word
Length
Select
BH1
(WLS1)
Request
to Send
(RTS)
Overrun
Error
(OE)
Delta
Data
Set
Ready
(DDSR)
Bft1
BH1
BitS
DataBR2
Enable
Receiver
LineStaius
Inlerrupt
(ELSI)
Interrupt
10
BH(1)
Number of
StopBfts
(STB)
Out 1
Parity
Error
(PE)
Trailing
EdgeRing
Indicator
(TERI)
BH2
BH2
Btt10
0
Parity
Enable
(PEN)
Out 2
(Inlerrupt
Enable)
Framing
Error
(FE)
Datta
Receive
Une
Signal
Dalect
(DRLSD)
Bft3
Bit3
Bft11
0
Even
Parity
Select
(EPS)
Loop
Break
Interrupt
(BI)
Clear
to
Send
(CTS)
Bft4
Bit 4
BR12
0
Transmftler
Holding
Register
(THRE)
Data
Sal
Ready
'(DSR)
BftS
BilS
Bft13
0
Ring
Indicator
(RI)
Bfta
Bit 6
Bit 14
Receive
Une
Signal
Dalect
(ALSO)
Bft?
Bft7
Bit1S
3
DataBft3
Data Bit3
Enable
Modem
Status
Interrupt
(EDSSI)
4
DataBR4
DataBH
0
S
Data BII S
DataBitS
0
0
Stick
Parity
6
DataBtt6
Data Bit 6
0
0
Sal
Breek
Transmitter
Empty
(TEMl)
7
DataBH7
Data Bit 7
0
0
Divisor
Latch
Access
Bft
(DLAS)
0
0
ODLABz1
Divisor
latCh
(LSB)
1 DLAB=O
Latch
(MSB)
t BH 0 IS the least significant bit. It IS the first bit serially transmitted or received.
TEXAS . "
INSIRUMENTS
POST OFFICE BOX 655303 • DAllAS. TEXAS 75265
3-41
TL16C451,TL16C452
ASYNCHRONOUS COMMUNICATIONS ELEMENTS
SLLS053A- 03284, MAY 1989- REVISED JANUARY 1990
PRINCIPLES OF OPERATION
receiver buffer register (RBR)
The ACE receiver section consists of a receiver shift register and a receiver buffer register. Timing is supplied
by the 16 X receiver clock (RCLK). Receiver section cohtrol is a function of the ACE line control register.
The ACE receiver shift register receives serial data from the serial input (SIN) pin. The receiver shift register
then converts the data to a parallel form and loads it into the receiver buffer register. When a character is placed
in the receiver buffer register and the received data available interrupt is enabled, an interrupt is generated. This
interrupt is cleared when the data is read out of the receiver buffer register.
transmitter holding register (THR)
The ACE transmitter section consists of a transmitter holding register and a transmitter shift register. Timing is
supplied by the baud out (BAUOQUT) clock Signal. Transmitter section control is a function of the ACE line
control register.
.
The ACE transmitter holding register receives data off the internal data bus and, when the shift register is idle,
moves it into the transmitter shift register. The transmitter shift register serializes the data and outputs it at the
serial output (SOUl). If the transmitter holding register is empty and the transmitter holding register empty
(THRI:) interrupt is enabled, an interrupt is generated. This interrupt is cleared when a character is loaded into
the register.
interrupt enable register (IER)
The interrupt enable register enables each ofthe four types of interrupts (refer to Table 4) and the INTRPT output
signal in response to an interrupt generation. The interrupt enable register can also be used to disable the
interrupt system by setting bits 0 through 3 to logic O. The contents of this register are summarized in Table 3
and are described below.
Bit O. This bit, when set to logic 1, enables the received data available interrupt.
Bit 1. This bit, when set to logic 1, enables the transmitter holding register empty interrupt.
Bit 2. This bit, when set to logic 1, enables the receiver line status interrupt.
Bit 3. This bit, when set to logic 1, enables the modem status interrupt.
Bits 4 thru 7. Bits 4 through 7 in the interrupt enable register are not used and are always set to logic O.
TEXAS'"
INSIRUMENTS
POST OFFICE BOX 655303 • DAllAS, TEXAS 75265
TL16C451, TL16C452
ASYNCHRONOUS COMMUNICATIONS ELEMENTS
SLLS053A - 03284, MAY 1989 - REVISED JANUARY 1990
PRINCIPLES OF OPERATION
interrupt identification register (IIR)
The ACE has an on-Chip interrupt generation and prioritization capability that permits a flexible interface with
most microprocessors.
The ACE provides four prioritized levels of interrupts:
Priority 1 Priority 2 Priority 3 Priority 4 -
Receiver line status (highest priority)
Receiver data ready
Transmitter holding register empty
Modem status (lowest priority)
When an interrupt is generated, the interrupt identification register indicates that an interrupt is pending and the
type of that interrupt in its three least significant bits (bits 0, 1, and 2). The contents of this register are
summarized in Table 3 and described in Table 4.
Bit O. This bit can be used either in a hardwire prioritized or polled interrupt system. If this bit is a logic 0, an
interrupt is pending. When bit 0 is a logic 1, no interrupt is pending.
Bits 1 and 2. These two bits are used to identify the highest priority interrupt pending as indicated in Table 4.
Bits 3 thru 7. Bits 3 through 7 in the interrupt idendtification register are not used and are always set at logic O.
Table 4 • Interrupt Control Functions
INTERRUPT
IDENTIFICATION
REGISTER
BIT 2
BIT 1
BIT 0
0
0
1
PRIORITY
LEVEL
INTERRUPT TYPE
None
None
INTERRUPT SOURCE
None
INTERRUPT RESET
METHOD
-
1
1
0
1
Receiver line status
Overrun error, parity error,
framing error or break
interrupt
1
0
0
2
Received data available
Receiver data available
Reading the receiver buffer
register
Transmitter holding register
empty
Reading the interrupt
Identification register (If
source of interrupt) or writing
into the transmitter holding
register
Clear to send, data set
ready, ring indicator, or data
carrier detect
Reading the modem status
register
0
1
0
3
Transmitter holding register
empty
0
0
0
4
Modem status
1ExAs
Reading the line status
register
..If
INSIRUMENTS
POST OFFICE BOX _
• DALLAS. TEXAS 75265
3-43
TL16C451, TL16C452
ASYNCHRONOUS COMMUNICATIONS ELEMENTS
SLLS053A- 03284, MAY 1989- REVISED JANUARY 1990
PRINCIPLES OF OPERATION
line control register (LCR)
The system programmer controls the format of the asynchronous data communication exchange through the
line control register. In addition, the programmer is able to retrieve, inspect, and modify the contents ofthe line
control register; this eliminates the need for separate storage of the line characteristics in system memory. The
contents of this register are summarized in Table 3 and are described below.
Bits 0 and 1. These two bits specify the number of bits in each transmitted or received serial character. These
bits are encoded as follows:
Bit 1
Bit 0
0
0
1
1
0
1
0
1
Word Length
5 Bits
6 Bits
7 Bits
8 Bits
Bit 2. This bit specifies either one, one and one-half, or two stop bits in each transmitted character. If bit 2 is a
logic 0, one stop bit is generated in the data. If bit 2 is a logic 1, the number of stop bits generated is dependent
on the word length selected with bits 0 and 1. The number of stop bits generated, in relation to word length and
bit 2, is as follows:
Number of Stop
Bits Generated
Bit 2
Word Length Selected
by Bits 1 and 2
0
1
1
1
1
Any word length
1
5bns
1 1/2
2
6bns
7Ms
8 bns
2
2
Bit 3. This bit is the parity enable bit. When bit 3 is a logic 1, a parity bit is generated in transmitted data between
the last data word bit and the firSt stop bit. In received data, if bit 3 is a logic 1, parity is checked. When bit 3 is
a logic 0, no parity is generated or checked.
Bit 4. Bit 4 is the even parity select bit. When parity is enabled by bit 3: a logic 1 in bit 4 produces even parity
(an even number of logic is in the data and parity bits) and a logic 0 in bit 4 produces odd parity (an'odd number
of logic 1s).
Bit 5. This is the stick parity bit. When bits 3, 4, and 5 are logic 1s, the parity bit is transmitted and checked as
a logic O. When bits 3 and 5 are logic 1s and bit 4 is a logic 0, the parity bit is transmitted and checked as a logic 1,
Bit 6. This bit is the break control bit. Bit 6 is set to a logic 1 to force a break condition, i.e, a condition where
the serial output (SOUT) pin is forced to the spacing (logic 0) state. When bit 6 is set to a logic 0, the break
condition is disabled. The break condition has no effect on the transmitter logic, it only effects the serial output.
Bit 7. This bit is the divisor latch access bit (OLAB). Bit 7 must be set to a logic 1 to access the divisor latches
of the baud generator during a read or write. Bit 7 must be set to a logic 0 during a read or write to access the
receiver buffer, the transmitter holding register, or the interrupt enable register.
1ExAs ."
INSIRUMENfS
3-44
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL16C451, TL16C452
ASYNCHRONOUS COMMUNICATIONS ELEMENTS
SLLS053A- 03284, MAY 1989- REVISED JANUARY 1990
PRINCIPLES OF OPERATION
modem control register (MCR)
The modem control register is an 8-bit register that controls an interface with a modem, data set, or peripheral
device that is emulating a modem. The contents of this register are summarized in Table 3 and are described
below.
Bit O. Bit 0 (OTR) controls the data terminal ready (OTR) output. Setting this bitto a logic 1 forces the OTR output
to its active state (low). When bit 0 is set to a logic 0, OTR goes high.
Bit 1. Bit 1 (RTS) controls the request to send (RTS) output in a manner identical to Bit O's control over the OTR
output.
Bit 2. Bit 2 (OUT 1) is a reserved location used only in the loopback mode.
Bit 3. Bit 3 (OUT 2) controls the output enable for the interrupt signal. When set to a logic 1, the interrupt is
enabled. When bit 3 is set to a logic 0, the interrupt is disabled.
Bit 4. Bit 4 provides a localloopback feature for diagnostic testing of the ACE. When this bit is set to a logic high,
the following occurs:
1.
2.
3.
4.
5.
The transmitter serial output (SOUT) is set high.
The receiver serial input (SIN) is disconnected.
The output of the transmitter shift register is looped back into the receiver shift register input.
The four modem status inputs (CTS, OSR, RLSO, andAi') are disconnected.
The modem control register bits (OTR, RTS, OUT1, and OUT2) are connected to the modem status
register bits (OSR, CTS, RI, and RLSO), respectively.
6. The four modem control output pins are forced to their inactive states (high).
In the diagnostic mode, data that is transmitted is immediately received. This allows the processor to verify the
transmit- and receive-data paths to the ACE. The receiver and transmitter interrupts are fully operational. The
modem control interrupts are also operational but the modem control interrupt sources are now the lower four
bits of the modem control register instead of the four modem control inputs. All interrupts are still controlled by
the interrupt enable register.
Bit 5 through 7. These bits are set to logic O.
line status register (LSR)t
The line status register provides information to the CPU concerning the status of data transfers. The contents
of this register are summarized in Table 3 and are described below.
Bit O. Bit 0 is the data ready (DR) indicator for the receiver. This bit is set to a logic 1 condition whenever a
complete incoming character has been received and transferred into the receiver buffer register and is reset
to logic 0 by reading the receiver buffer register.
Bit 1*. Bit 1 is the overrun error (OE) indicator. When this bit is set to logic 1, it indicates that before the character
in the receiver buffer register was read, it was overwritten by the next character transferred into the register. The
OE indicator is reset every time the CPU reads the contents of the line status register.
Bit 2*. Bit 2 is the parity error (PE) indicator. When this bit is setto logic 1, it indicatesthatthe parity ofthe received
data character does not match the parity selected in the line control register (bit 4). The PE bit is reset every
time the CPU reads the contents of the line status register.
Bit 3*. Bit 3 is the framing error (FE) indicator. When this bit is set to logic 1, it indicates that the received character
did not have a valid (logic 1) Stop bit. The FE bit is reset every time the CPU reads the contents of the line status
register.
t The line status register is intended for read operations only; writing to this register is not recommended outside of a factory testing environment.
*Bns 1 through 4 are the error conditions that produce a receiver line status interrupt.
1ExAs . "
INSIRUMENTS
POST OFFICE BOX 655303 • DAllAS, TEXAS 75265
3-45
TL16C451,TL16C452
ASYNCHRONOUS COMMUNICATIONS ELEMENTS
SIl.S053A- D3284. MAY 1989- REVISED JANUARY 1990
PRINCIPLES OF OPERATION
line status register {LSR)t (continued)
Bit 4*. Bit 4 is the break interrupt (BI) indicator. When this bit is set to logic 1, it indicates that the received data
input was held in the logic 0 state for longer than a full-word transmission time. A full-word transmission time
is defined as the total time of the start, data, parity, and stop bits. The BI bit is reset every time the CPU reads
the contents of the line status register.
Bit S. Bit S is the transmitter holding register empty (THRE) indicator. This bit is set to a logic 1 condition when
the transmitter holding register is empty, indicating that the ACE is ready to accept a new character. If the THRE
interrupt is enabled when the THRE bit is a logic 1, then an interrupt is generated. THRE is set to a logic 1 when
the contents of the transmitter holding register are transferred to the transmitted shift register. This bit is reset
to logic 0 concurrent with the loading of the transmitter holding register by the CPU.
Bit 6. Bit 6 is the transmitter empty (TEMl) indicator, This bit is set to a logic 1 when the transmitter holding
register and the transmitter shift register are both empty. When either the transmitter holding register or the
transmitter shift register contains a data character, the TEMT bit is reset to logic O.
Bit 7. This bit is always reset to logic O.
t The line status register is intended for read operations only; writing to this register is not recommended outside of a factory testing environment.
*
Bits 1 through 4 are the error conditions that produce a receiver line status interrupt.
modem status register (MSR)
The modem status register is an 8-bit register that provides information about the current state of the control
lines from the modem, data set, or peripheral device to the CPU. Additionally, four bits of this register provides
change information; when a control input from the modem changes state the appropriate bit is set to logic 1.
All four bits are reset to logic 0 when the CPU reads the modem status register. The contents of this register
are summarized in Table 3 and are described below.
Bit O. Bit 0 is the delta clear to send (DCTS) indicator. This bit indicates that the CTS input has changed state
since the last time it was read by the CPU. When this bit is a logiC 1 and the modem status Interrupt is enabled,
a modem status interrupt is generated.
Bit 1. Bit 1 is the delta data set ready (DDSR) indicator. This bit indicates that the DSR input has changed state
since the last time it was read by the CPU. When this bit is a logiC 1 and the modem status Interrupt is enabled,
a modem status interrupt is generated.
Bit 2. Bit 2 is the trailing edge of ring indicator (TERI) detector. This bit indicates that the RI input to the chip has
changed from a low to a high state. When this bit is a logiC 1 and the modem status Interrupt is enabled, a modem
status interrupt is generated.
Bit 3. Bit 3 is the delta receive line signal detect (DRLSD) indicator. This bit indicates that the RLSD input to the
chip has changed state since the last time it was read by the CPU. When this bit is a logic 1 and the modem
status interrupt is enabled, a modem status interrupt is generated.
Bit 4. Bit 4 is the complement of the clear to send (CTS) input, If Bit 4 (loop) of the modem control register is
set to a logic 1, this bit is equivalent to the modem control register bit 1 (RTS).
BitS. Bit S is the complement of the data set ready (DSR) input. If Bit 4 (loop) of the modem control register is
set to a logic 1, this bit is equivalent to the modem control register bit 0 (DTR).
Bit 6. Bit 6 is the complement of the ring indicator (RI) input. If Bit 4 (loop) of the modem control register is set
to a logic 1, this bit is equivalent to the modem control registers bit 2 (OUT 1).
Bit 7. Bit 7 is the complement of the receive line signal detect (RLSD) input. If Bit 4 (loop) of the modem control
register is set to a logic 1, this bit is equivalent to the modem control registers bit 3 (OUT 2).
1ExAs
,If
INSIRUMENTS
3-46
POST OFFICE BOX 655303 • DAUAS. TEXAS 75265
TL16C451,TL16C452
ASYNCHRONOUS COMMUNICATIONS ELEMENTS
SLLS053A- 03284. MAY 1989- REVISED JANUARY 1990
PRINCIPLES OF OPERATION
scratch register (SCR)
The scratch register is an a-bit register that is intended for programmer use as a scratchpad, in the sense that
it will temporarily hold programmer data without affecting any other ACE operation.
programmable baud generator
The ACE contains a programmable baud generator that takes a clock input in the range between dc and 9 MHz
and divides it by a divisor in the range between 1 and 2 16-1. The output frequency of the baud generator is
sixteen times (16 X) the baud rate. The formula for the divisor is:
divisor #
=ClK frequency input + (desired baud rate X 16)
Two a-bit registers, called divisor latches, are used to store the divisor in a 16-bit binary format. These divisor
latches must be loaded during initialization of the ACE in order to ensure desired operation of the baud
generator. When either of the divisor latches is loaded, a 16-bit baud counter is also loaded to prevent long
counts on initial load. For baud rates of 38.4 kilobits per second and below, the error obtained is very small. The
accuracy of the selected baud rate is dependent on the selected crystal frequency.
interrupt control logic
The interrupt control logic is shown in Figure 10.
DR (LSR bltO)--------f--·~
ERBFI (IER b l t O ) - - - - - - - - - l _ J
THRE (LSR bit
5)--------r-,
ETBEI (IER b l t 1 ) - - - - - - - - L _ j
OE (LSR bit 1)
PE (LSR bit 2)
Interrupt
Output
-;::=::::)
FE (LSR bit 3)
BI (LSR bit 4)
ELSI (IER bit 1) - - - - - - '
DCTS (MSR bit 0)
TERI (MSR bit 2)
DRLSD (MSR bit 3)
EDSSI (IER bit 3) _ _ _ _ _---l
INTERRUPT ENABLE (MCR bit 3)
Figure 10. Interrupt Control logic
1ExAs . "
INSIRUMENIS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
3-47
TL16C451,TL16C452
ASYNCHRONOUS COMMUNICATIONS ELEMENTS
SLl.S053A- 03284, MAY 1989- REVISED JANUARY 1990
PRINCIPLES OF OPERATION
parallel port registers
The parallel port registers interface either device to a Centronix-style printer, When chip select 2 (CS2) is low.
the parallel port is selected, Tables 5 and 6 show the registers aSsociated with this parallel port, The read or write
function of the register is controlled by the state. or the read (lOR) and write (lOW) pin as shown, The read data
register allows the microprocessor to read the information on the parallel bus,
The read status register allows the microprocessor to read the status of the printer in the five most significant
bits, The status bits are printer busy (BUSy). acknowledge (ACK) which is a handshake function. paper em pty
(PE). printer selected (SLCl). and error (ERROR), The read control register allows the state ofthe control lines
to be read, The write control register sets the state of the control lines. which are interrupt enable (IRQ ENB).
select In (SLlN). initialize the printer (INIl). autofeed the paper (AFO). and strobe (STB). which informs the
printer of the presence of a valid byte on the parallel bus, These signals are set to 0 when a reset occurs, The
write data register allows the microprocessor to write a byte to the parallel bus, The parallel port is completely
compatible with the parallel port implementation used in the .IBM seriaVparaliel adaptor,
Table 5. Parallel Port Registers
REGISTER BITS
REGISTER
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT 1
BIT 0
PD7
PD6
PD5
PD4
PD3
PD2
POl
PDO
Read Status
BUSY
ACK
PE
SLCT
ERROR
1
1
1
Read Control
1
1
1
IRQENB
SUN
iNif
AFD
STB
PD7
PD6
PD5
PD4
PD3
PD2
POl
PDO
1
1
1
IRQENB
SUN
INIT
AFD
STB
Read Data
Wr~eData
Wr~e
Control
Table 6. Parallel Port Register Select
CONTROL PINS
REGISTER SELECTED
lOR
lOW
CS2
A1
L
H
L
L
L
Read Data
L
H
L
L
H
Read Status
L
H
L
H
L
Read control
L
H
L
H
H
Invalid
H
L
L
L
L
Write Data
H
L
L
L
H
Invalid
H
L
L
H
L
Wr~e
H
L
L
H
H
Invalid
AO
1ExAs
..If
INSIRUMENTS
3-48
POST OFFICE BOX 65530<3 • DAUAS, TEXAS 75265
Control
TL16C550A
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS057B-
•
Capable of Running With All Existing
TL16C450 Software
•
After Reset, All Registers Are Identical to
the TL16C450 Register Set
•
In the FIFO Mode, Transmitter and Receiver
Are Each Buffered With 16-Byte FIFOs to
Reduce the Number of Interrupts to the
CPU
.
•
In the TL16C450 Mode, Holding and Shift
Registers Eliminate the Need for Precise
Synchronization Between the CPU and
Serial Data
•
Programmable Baud Rate Generator Allows
Division of Any Input Reference Clock by 1
to (216 -1) and Generates an Internal 16 X
Clock
•
Adds or Deletes Standard Asynchronous
Communication Bits (Start, Stop, and
Parity) to or From the Serial Data Stream
•
Independent Receiver Clock Input
•
Independently Controlled Transmit,
Receive, Line Status, and Data Set
Interrupts
•
Fully Programmable Serial Interface
Characteristics:
5-, 6-, 7-, or 8-Blt Characters
Even-, Odd-, or No-Parity Bit Generation
and Detection
1-,1 1/2-, or 2-Stop Bit Generation
Baud Generation (dc to 256 Kilobits Per
Second)
•
False-Start Bit Detection
•
Complete Status Reporting Capabilities
•
3-State TTL Drive Capabilities for
Bidirectional Data Bus and Control Bus
•
Line Break Generation and Detection
•
Internal Diagnostic Capabilities:
Loopback Controls for Communications
Link Fault Isolation
Break, Parity, Overrun, Framing Error
Simulation
•
Full Prioritized Interrupt System Controls
•
Modem Control Functions (CTS, RTS, DSR,
DTR, RI, and DCD)
•
Faster Plug-In Replacement for National
Semiconductor NS16550A
NPACKAGE
FNPACKAGE
(TOP VIEW)
(TOP VIEW)
Vee
RI
OCO
OSR
CTS
01
05
06
MR
07
8
RCLK
SIN
SOUT
9
CSO
CSl
CS2
BAUOOUT
XIN
XOUT
WRl
WR2
Vss
AUGUST 1989- REVISED MARCH 1993
OUT 1
OTR
RTS
QUT2
INTRP
RXROY
AO
Al
A2
AOS
TXROY
OOIS
R02
.... C?
N ~
0000
6 5 4
7
3
m
8 z>a:ooo
0 o
0 1- lOla:
0 m 1I2
1 44 43 42 41 40
39
8
38
9
10
37
36
35
11
12
34
13
33
32
14
15
31
16
30
17
29
1819202122232425262728
MR
OUT 1
OTR
RTS
QUT2
NC
INTRPT
RXROY
AO
Al
AS
I- ~ N m
0 ~ N m
I>-Im
xZ 0:>;:=
::J ,I$: a: >m z 10 0 i5 0 0
a:a:oa:3)
IL...-_--'
---,
r----------------.
ItfI
L
I---
2 XlN Cyeles -+j
1
I
I
'41---....
(N-2) XIN Cyelee ---~.I
Figure 1. Baud Generator Timing
POST OFFICE BOX 6553CCI • DAUAS. TEXAS 75265
UNIT
TL16C550A
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLl.S057B - 03128, AUGUST 1989 - REVISED MARCH 1993
PARAMETER MEASUREMENT INFORMATION
tws
14---I~-
=:x:
: . - teu1
,
AO-A2
,
,
CSO, CS1, CSZ
~I4-+!,
Valid
,\4
,
--....J.:'""'0
1i11
-x=
X'---V-al-Id-t
~I
-+I
Voa.
,
tsu2
,
X-' {<'-.l..:- - *-th2
,
,
1i13rl'
'!.- id4t ~I4-tws +ij4- th4t ~,
,
I
!4- idst
_,WR2
-+,
,i...,
tsu3
00-07
----+t
X.....~. ._____
,4
rill
(
Valid Data
td6
~
~
thS
j~---
t Applicable only when ADS is tied low.
Figure 2. Write Cycle Timing
1ExAs . "
INSIRUMENIS
POST OFFICE BOX 655303 • DAUAS. TEXAS 75265
3-57
T.L16C550A
ASYNCHRONOUS COMMUNICAT.IONS ELEMENT.
Sl.LS057B - 03128, AUGUST 1989 - REVISED MARCH 1993
PARAMETER MEASUREMENT INFORMATION
: . - tau1 -+I
,
i+.}- th1
...... ---...." """ X"".,
- / l' I14
I 1
CSO, CS1, CS2--""';'",,\X
.' tau2
I
--.I i4- th2
v..
,
"?C=,
I:
I,
X..... (< :
1
th6~,
1
M- t w7-.1
l_
l4-tcf7t~
I
,
'4
i
'
fd9 - - . ,
,..,X _w ~. .-----
RD1, RD2 _ _ _ _ _ _
tdls(R)
DDIS
I
~
,
f'I.1
! It
------~!~
I
fd10
00-07
JIll
~
________--«
,
,
I
14
Valid Data
t Applicable only when ADS is tied low.
Figure 3. Read Cycle Timing
TEXAS- ."
INSIR.UMENTS
3-58
POST OFFICE BOX 655303 • DAUAS, TEXAS 75265
i
'
1
I4-th7t~
14-- tclat --+I
,
fdis(R)
TL16C550A
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLlSOS78 - 03128, AUGUST 1989 - REVISED MARCH 1993
PARAMETER MEASUREMENT INFORMATION
RCLK
---fl""'""------'n~
---.fL
14~I
I
tcI12
144------8CIOCks-------.~11
Sample Clock
______________
n
~IL-
TL16C450Mode:
I
Parity
Stop
"--J
I
Sample Clock
_ _......._
..&1_-
--;-1_ _---_ _
......._ _ _ _ _ .....1._ _............
I
1
INTRPT
(Data Ready)
I
I
14
.1
1
tcI13
INTRPT
(RCVError)
l'L
1
1
tcI14 ~
'-I
)
-------
I
I
~~~R~~~ _____________________________________________r:-~
tcI14
--j4--+I
\~~
RD1,RD2
(Read LSR) ___________________________________~
Figure 4. Receiver Timing
ThxAs
..If
INSIRUMENIS
POST OFFICE SOX 655303 • DAlLAS, TEXAS 75265
3-59
TL16C550A
ASYNCHRONOUS COMMUNICATIONS ELEMENT
Su.s057B - 03128, AUGUST 1989 - REVlSeO MARCH 1993
PARAMETER MEASUREMENT INFORMATION
SIN
\.\"_"""",G
___D_at~a~_B_lt8_5-8
_ _-,
Sample Clock
r
If
IJ
Trigger-Level
Interrupt
(FCR6,7 = 0, 0)
Il
-------------::11
----'
-----"":11:'--L
't-'
j
I
I
td13
I 14(see Note A » )
LSllnt8rrupt _ _ _ _ _ _ _ _ _ _ _---J
1d14
I
I
---!4--+1
I
(FIFOatorAbove
Trigger Level)
(FIFO Below
Trigger Level)
\- :
14 .1
1d14
I
I
I
RD1 -------------~,A~we!/
(RD LSR)
I:
\........:¥
tr-
RD1
(RD RBR)
Figure 5. Receiver FIFO First Byte (Sets DR Bit)
SIN
r
Sample Clock
Time Out or
Trigger Level
Interrupt
l
I
_ _ _ _ _ _.....;
I
I
~I
td13
(see Note A) --.;
LSI Interrupt
''t---------~--j
1\
14-
-------,
1d14
t"
i" -
(FIFOatorAbove
Trigger Level)
(FIFO Below
I
Trigger Level)
~
I
________ ~~~..2:~~.:c:"~~:\~....1.:----I
I I
1l1li
I
1d13
1d14 ~I
.,
I
RD1, RD2
(RDLSR)
---'--:"""""x
RD1,RD2
(RDRBR)
___
I
I
X\.----r-j-
I
I
J)(~-A~-I-ve~:>(\"_ _ _ _ _ _ _--J~r-A-~-'V-e~~
Previous Byte
Read From FIFO
Figure 6. Receiver FIFO Bytes Other Than the First Byte (DR Internal Bit Already Set)
NOTE A: For a timeout interrupt, td13 = 8 RCLKs.
1ExAs
~
INSIRUMENJ'S
:H)O
POST OFFICE BOX 655303 • DAUAS, TEXAS 75265
TL16C550A
ASYNCHRONOUS COMMUNICATIONS ELEMENT
Su.s057B - 03128, AUGUST 1989 - REVISED MARCH 1993
PARAMETER MEASUREMENT INFORMATION
RO
(RORBR)
/,1-'- - - - - . . \ Active
SIN
(first byte)
r
~
: (seeNoteA)
-------" Stop
,
"-----------
I
Sample Clock
I
I
~13
(S88 Note B)
,
:
,
,
,
14
RXROY
i
~_1_4_r-...Jj~____
.11'-'_ _ _......"I-_ _ _
l
N
Figure 7. Receiver Ready (RXRDy). FCRO = 0 or FCRO = 1 and FCR3 = 0 (mode 0)
II
It
RO
(RORBR)
\
I
,
,
,
,
,
,
I
I
~13'
(see Note B)
--;+-+,
I
X'
RXROY
r
: (see Note A)
SIN~
(first byte that reaches
the trigger level)
Sample Clock
Active
II"----~U
"'/---
Figure 8. Receiver Ready (RXRDy). FCR = 1 or FCR3 = 1 (mode 1)
NOTES: A. This is the reading of the last byte In the FIFO.
B. For a timeout interrupt,id13 8 RCLKs.
=
1ExAs
,If
INSIRUMENTS
POST OFFICE BOX B56303 • DAllAS, TEXAS 75265
3-61
TL16C550A
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLl.S057B - D3128.AUGUST 1989 - REVISED MARCH 1993
PARAMETER MEASUREMENT INFORMATION
SOUT
\
tcl15
Start
;=Dat;;lts~ =X_P_Ir_lty-.J!
-i'IIf--~.1
tcl16
INTRPT
(THRE)
"
tcl17
WRTHR
Stop
-+,
k:
~
\::/
,
~
14I
,
,
,
,
~'Il4- tcl17
~ j4-'
,
~
~__-.JI
"
,
\~--------------~itcl19
RDIIR
,
,"---------------"
-+i l--
--------------------~~
Figure 9. Transmitter Timing
WR
(WRTHR)
SOUT
Byte.1
\
------
(,.--------f~l-l'
,
D_at__
a ....,.:_..IX'__p_a_rity_~
_____
td2()
~
td21
-JJ'
nm~ ___________
\
WFi
SOUT
~
~'__
Figure 10. Transmitter Ready (TXRDV). FCRO
(WRTHR)
Start ; -
____
=0 or FCRO =1 and FCR3 =0 (mode 0)
Byte #16 (
,
D_at_a____~:)C'-_p_a_rlty-
________
tcl20~
_____________~/r------~
•
Figure 11. Transmitter Ready (TXRDV). FCRO
FIFO Full
=1 and FCR3 =1 (mode 1)
1ExAs'"
INSIRUMENTS
POST OFFICE BOX _
• DAUAS. TEXAS 75265
TL16C550A
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS0578 - 03128, AUGUST 1989 - REVISED MARCH 1993
PARAMETER MEASUREMENT INFORMATION
WR
(WRMCR)
I
td22
---+I~I--_~~I
t(\22
--Io_ _
~~
\ _____________~)r\~-------------I
1d23-1++i
(~~~~~1
________..Jlr-----""'~~-..J(
td24
j+-+I
,I
~1d23
\
R02 _ _ _ _ _ _ _ _ _...1/
(RO MSR)
\~
I
I
__--II"'-----
Figure 12. Modem Control Timing
P'"
SOUT
07-00
07-00
MEMRor VOR
MEMWor I/ON
INTR
C
P
U
RESET
AD
u
•
...c
RTS
OTR
INTRPT
OSR
MR
OCO
A1
A2
TL16C550A CTS
(ACE)
AI
EIA
232-0 Driver.
and Receivera
W
.
A2
_L£
cs
R01
WR1
AD
A1
B
SIN
ADS
XIN
~l
WR2
=
-,
ROO
CS2
XOUT
CS1
BAUOOUT
H - C CSO
RCLK
tJ
T-=
Figure 13. Basic TL16C550A Configuration
1ExAs ...,
INSIRUMENIS
POST OFFICE BOX 6i56303 • DAlLAS, TEXAS 75265
3.072 MHz
I
TL16C550A
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS057B - 03128, AUGUST 1989 - REVISED MARCH 1993
APPLICATION INFORMATION
Receiver Dissble
WR
Microcomputer
Syatem
DstaBus
8-8lt
~
WR1
TL16C55OA
(ACE)
Data Bus
07-00
DDIS
Bus Transceiver
Driver Disable
Figure 14. Typical Interface for a High-Capacity Data Bus
1ExAs
~
INSIRUMENfS
3-64
POST OFFICE BOX 655303 • DALlAS, TEXAS 75265
TL16C550A
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS057B - 03128, AUGUST 1989 - REVISED MARCH 1993
APPLICATION INFORMATION
TL16C550A
Alternate
XTAL Control
~N~1~6~____~__~__~
=
A16-A23
A16-A23I-_ _ _ _ _ _--,
XOUT~1~7__~~-4__~__~
12
~------~C~
Address
13
Decoder 1------...;..;;".-1 CS1
14
CPU
BAUDOUT
15
9
RCLK
CS2
20
DTR
ADS~__------------~~ADS
RSVABT~~--.-~~
~r---------~~~MR
RTS J....:.:::.....------I
OUT 1
OUT2
ADO- AD15 1'r--r-__-r-__.,.,
PHI1
T
Ai
31
39
PHI2
37
DSR l-=-=-------~
PHI1
ADS
PHI2
RSTO
RD
21
1--------1
TCU
WRI------I
CTS
J.:36~-n~
SOUT
t-..:...:.---I
RD1
1--___1_B-JWR1
SIN
INTRPT
ADO-AD1S
TXRDY
11
10
I-----n.c
3
30
24
RD2
DDIS
23
19 WR2
RXRDY
29
22
2
":" EIA-232·D
40
5V
(VCC)
Figure 15. Typical TL16C550A Connection to a CPU
1ExAs
..If
INSIRUMENrS
POST OFFICE BOX 655303 • DAUAS, TEXAS 75265
Connector
Tl16C550A
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS057B - 03128, AUGUST 1989 - REVISED MARCH 1993
PRINCIPLES OF OPERATION
Table 1. Register Selection
DLABt
A1
AO
REGISTER
A2
Receiver buffer (read), transmitter holding register (write)
0
L
L
L
0
Interrupt enable
L
L
H
Interrupt identificalion (read only)
X
L
H
L
FIFO control (write)
X
H
L
L
X
L
H
H
Une control
Modem control
X
H
L
L
X
H
L
H
Unestalus
Modem status
L
X
H
H
Scralch
X
H
H
H
Divisor Ialch (LSB)
1
L
L
L
Divisor latch (MSB)
1
L
L
H
t The divisor Ialch access bit (DLAB) IS the most Significant bit ofthe line control register. The DLAB signal
is controlled t>Y writing to this bit location (see Table 3).
Table 2. Ace Reset Functions
REGISTER/SIGNAL
Interrupt Enable Register
interrupt Identification Register
FIFO Control Register
Une Control Register
Modem Control Register
Une Slalus Register
Modem Stalus Register
SOUT
INTRPT (receiver error flag)
INTRPT (received dais available)
INTRPT (transmitter holding register empty)
INTRPT (modem status changes)
OUT 2
RT-S
DTR
OUT 1
Scralch Register
Divisor Latch (LSB and MSB) Registers
Receiver Buffer Registers
Transmitter Holding Registers
RCVRFIFO
XMITFIFO
RESET
CONTROL
Master Reset
Master Reset
Master Reset
Master Reset
Master Reset
Master Reset
Master Reset
Master Reset
RESET STATE
All bits low (0-3 forced and 4-7 permanent)
Bit 0 is high, bits 1-3 are low, and bits 4-7 are permanently low
All bits low
Ali bits low
All bits low (5-7 permanent)
Bits 5 and 6 are high, all other bits are low
Bits 0-3 are low, bits 4-7 are input signals
High
ReadLSR/MR
Read RBR/MR
Read IR/Write
THR/MR
Low
Low
Read MSR/MR
Master Reset
Master Reset
Master Reset
Master Reset
Low
High
High
High
High
Master Reset
Master Reset
Master Reset
Master Reset
MR/FCR1-FCROI
AFCRO
MR/FCR2-FCROI
AFCRO
Low
No effect
No effect
No effect
No effect
Ali bits low
All bits low
1ExAs
~
INSIR.UMENTS
3-66
POST OFFICE BOX 6S53CX! • DAUAS, TEXAS 75265
TL16C550A
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS057B - 03128, AUGUST 1989- REVISED MARCH 1993
PRINCIPLES OF OPERATION
accessible registers
The system programmer, via the CPU, has access to and control over any of the ACE registers that are
summarized in Table 3. These registers are used to control ACE operations, receive data, and transmit data.
Descriptions of these registers follow Table 3.
Table 3, Summary of Accessible Registers
BIt
No.
-
Control
Une
Control
Control
Reg-
Reglol.
Reg-
Only)
Regl(WrIte
Only)
_.
HR
FeR
LeR
MeR
LSR
REGISTER ADDRESS
ODLAB=O
ODLAB=O
_wer
Tr....mltter
RogIOIer
(ClnIy)
RBR
1 DLAB=O
2
2
FIFO
Holding
Reg(WrIte
Only)
Interrupt
Enablo
Interrupt
Idont.
Regl-
Reg-
(Read
THR
IER
Enable
Received
o
DelaB~ot
Data~O
Data
Available
Interrupt
(ERS)
'fT K
InIorrupt
Pending
Enable
Tranamltler
1
Deta8ft1
DataB~1
Holding
Regi_
Empty
Interrupt
--
Interrupt
lD
~o
FIFO
EnoIlIo
-FIFO
Rooet
3
WOld
Leng1h
Select
BftO
(WLSO)
WOld
Leng1h
Select
Bft1
(WLS1)
4
Modem
Data
Terminal
Reedy
(OTA)
I
Une
Data
Reedy
(DR)
•
7
Mod...
_uo
RogIeter
Scratch
Reg-
MSR
seR
DLL
DLM
B~O
~O
BbB
Bft1
BlI1
Bft9
Bft2
Bil2
~10
Bft3 '
BU
~11
Bft4
BlI4
BlI12
BftS
BlI5
Bil13
Bfta
~a
BlI14
~7
BlI7
~1S
ODLAB.1
Dlvloor
UIch
(LSB)
1DLAB=1
U1ch
(MSB)
Delta
cto Send
(4CTS)
Delta
Requeot
Overrun
Data
to Send
Errcr
(CE)
Reedy
(RTS)
Set
(4DSR)
(ETBE~
Enable
2
3
4
5
a
7
DetaB~2
Deta~3
DetaBil4
Data~S
Data~a
Deta~7
Data~2
DetaBft3
Data~4
Data~S
Deta~a
Deta~7
Una Sta\uo
Intarrupl
(ELSI)
Enable
Modem
Stlllus
IntenupI
(EDSSI)
a
a
a
a
10
Trenam_
FIFO
8ft (1)
Rooet
Interrupt
Interrupt
10
~(2)
(NoIe4)
a
a
FIFO.
Enabled
(_4)
FIFO.
Enabled
(_4)
OMA
Mode
Select
--
---Trigger
(LSS)
Receiver
Trigger
(MSS)
Trailing
Number
01
StopBlta
(STS)
Parity
Enable
(PEN)
Even
Parity
Select
Out 1
Out 2
Loop
Parity
Errcr
(PE)
Framing
Errcr
(FE)
-
IntenupI
(B~
(EPS)
Transmitter
Slick
Parity
B_
Set
-
a
a
Divisor
latch
a
Bli
(DlAB)
Edge ling
I~
(TEAl)
Delta
Data
Cerrior
Do\eot
(4DCO)
ato
Send
(CTS)
Data
HokIng
Set
Regi-
Ready
(THRE)
(DSR)
Tranomillar
Empty
Ring
IndI'-
(TEM!)
(R~
Errcrin
Data
CerrIor
RCVR
FIFO
(Noto4)
Do\eot
(DCO)
t Bit 0 IS the leest significant bit. It is the first bit serially transmitted or received.
NOTE 4: These bits are aloways 0 in the TL 16C450 mode.
1ExAs ..,
INSIRUMENIS
POST OFFICE BOX 6S5303 • DAUAS. TEXAS 75265
3-67
TL16C550A
ASYNCHRONOUS COMMUNICATIONS ELEMENT
Su.8057B - 03128, AUGUST 1989 - REVISED MARCH 1993
PRINCIPLES OF OPERATION
receiver buffer register (RBR)
The ACEs receiver section consists of a receiver shift register (RSR) and a receiver buffer register (RBR), The
RBR is actually a 16-byte FIFO, liming is supplied by the 16 X Receiver Clock (RCLK). Receiver section control
is a function of the ACEs line control register.
The ACEs RSR receives serial data from the serial input (SIN) pin. The RSR then deserializes the data and
moves it into the RBR FIFO. In the TL16C450 mode, when a character is placed in the receiver buffer register
and the received data available interrupt is enabled, an interrupt is generated. This interrupt is cleared when
the data is read out of the receiver buffer register. in the FI FO mode, the interrupts are generated based on the
control setup in the FIFO control register.
.
transmitter holding register (THR)
The ACEs transmitter section consists of a transmitter holding register (THR) and a transmitter shift register
(TSR). The THR is actually a 16-byte FIFO. liming is suppled by the baud out (BAUDOUT) clock signal.
Transmitter section control is a function of the ACE's line control register.
The ACE THR receives data off the internal data bus and, when the shift register is idle, moves it into the TSR.
The TSR serializes the data and outputs it at the serial output (SOUT). In the TL16C450 mode, if the THR is
empty and the transmitter holding register empty (THRE) interrupt is enabled, an interrupt is generated. This
interrupt is cleared when a character is loaded into the register. In the FIFO mode, the interrupts are generated
based on the control setup in the FIFO control register.
interrupt enable register (IER)
The Interrupt enable register enables each ofthe five types of interrupts (refer to Table 4) and the I NTRPT output
signal in response to an interrupt generation. The interrupt enable register can also be used to disable the
interrupt system by setting bits 0 through 3 to logic O. The contents of this register are summarized in Table3
and are described below.
Bit O. This bit, when set to logic 1, enables the received data available interrupt.
Bit 1. This bit, when set to logic 1, enables the transmitter holding register empty interrupt.
Bit 2. This bit, when set to logic 1, enables the receiver line status interrupt.
Bit 3. This bit, when set to logic 1, enables the modem status interrupt.
Bits 4 thru 7. Bits 4 through 7 in the interrupt enable register are not used and are always set to logic O.
FIFO control register
The FIFO control register (FCR) is a write-only register at the same location as the !lR, which is a read-only
register. The FCR is used to enable the FIFOs, clear the FIFOs, set the receiver FIFO trigger level, and select
the type of DMA signalling.
Bit O. FCRO, when set to logic 1, enables the transmit and receive FIFOs. This bit must be a 1 when other FCR
bits are written to or they will not be programmed. Changing this bit clears the FIFOs.
Bit 1. FCR1, when set to logic 1, clears all bytes in the receiver FIFO and resets its counter logic to O. The shift
register is not cleared .. The 1 that is written to this bit position is self clearing.
Bit 2. FCR2, when setto logic 1, clears all bytes in the transmit FIFO and resets its counter to O. The shift register
is not cleared. The 1 that is written to this bit position is self clearing.
Bit 3. if FCRO is a 1, setting FCR3 to a i causes the RXRDY and T)(RDY to change from mode 0 to mode 1.
1ExAs
..If
INSIRUMENTS
34>8
POST OFFICE BOX 65Ii303 • DAllAS, TEXAS 75265
TL16C550A
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS0578 - 03128, AUGUST 1989 - REVISED MARCH 1993
PRINCIPLES OF OPERATION
Bits 4 and 5. FCR4 and FCR5 are reserved for future use.
Bits 6 and 7. FCR6 and FCR7 are used to set the trigger level for the receiver FIFO interrupt.
BIT 7
BIT 6
RECEIVER FIFO
TRIGGER LEVEL (BYTES)
0
0
0
1
01
04
1
1
0
1
08
14
interrupt identification register (IIR)
The ACE has an on-chip interrupt generation and prioritization capability that permits a flexible interface with
most popular microprocessors.
The ACE provides four prioritized levels of interrupts:
Priority 1-Receiver line status (highest priority)
Priority 2-Receiver data ready or receiver character timeout
Priority 3-Transmitter holding register empty
Priority 4-Modem status (lowest priority)
When an interrupt is generated, the interrupt identification register indicates that an interrupt is pending and
the type of that interrupt in its three least significant bits (bits 0, 1, and 2). The contents of this register are
summarized in Table 3 and described in Table 4. Detail on each bit are as follows:
Bit O. This bit can be used either in a hardwire-prioritized, or polled interrupt system. If this bit is a logic 0, an
interrupt is pending. When bit 0 is a logic 1, no interrupt is pending.
Bits 1 and 2. These two bits are used to identify the highest priority interrupt pending, as indicated in Table 4.
Bit 3. This bit is always 0 in the TL16C450 mode. In FIFO mode, this bit is set with bit 2 to indicate that a timeout
interrupt is pending.
Bits 4 thru 5. These two bits are not used and are always set at logic
o.
Bits 6 and 7. These two bits are always 0 in the TL16C450 mode. They are set when bit 0 ofthe FIFO control
register is equal to 1.
1ExAs
~
INSIRUMENTS
POST OFFICE BOX 655303 • DAU.AS. TEXAS 75265
:H>9
TL16C550A
ASYNCHRONOUS COMMUNICATIONS ELEMENT
Su.s057B - 03128, AUGUST 1988 - REVISED MARCH 1993
PRINCIPLES OF OPERATION
Table 4. Interrupt Control FunctIons
INTERRUPT
IDENllFICAnoN
REGISTER
BIT 3 BIT 2 I BIT 1 ..TO
()
0
0
1
PRIORITY
LEVEL
None
INTERRUPT TYPE
INTERRUPT SOURCE
None
None
Overrun error, parity error,
framing error or break Interrrupt
Receiver data available In the
TL16C450 mode or trigger level
reached In the FIFO mode.
No characters have been
removed from or input to the
receiver FIFO during the last
four character times and there
is at least one character in it
during this time
INTERRUPT RESET
METHOD
Reading the line status register
0
1
1
0
1
Receiver line status
0
1
0
0
2
Received data available
1
1
0
0
2
Character timeout
Indication
0
0
1
0
3
Transmitter holding
register empty
Transmitter holding register
empty
Reading the Interrupt
Identification register (If source
of Interrupt) or writing Into the
transmitter holding register
0
0
0
0
4
Modem status
Clear to send, data set ready,
ring Indicator, or data carrier
detect
Reading the modem status
register
Reading the receiver buffer
register
Reading the receiver buffer
register
line control register (LCR)
The system programmer controls the format of the asynchronous data communication exchange through the
line control register. In addition, the programmer is able to retrieve, inspect, and modify the contents of the line
control register; this eliminates the need for separate storage of the line characteristics in system memory. The
contents of this register are summarized in Table 3 and described below.
Bits 0 and 1. These two bits specify the number of bits in each transmitted or received serial character. These
bits are encoded as follows:
Bit 1
0
0
1
1
Bit 0
0
1
0
1
Word Length
5 Bits
6Bils
7 Bits
SBils
1ExAs
~
INSIRUMENTS
3-70
POST OFFICE BOX 655303 • DAUAS. TEXAS 75265
TL16C550A
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS057B - 03128, AUGUST 1989 - REVISED MARCH 1993
PRINCIPLES OF OPERATION
Bit 2. This bit specifies either one, one and one-half, or two stop bits in each transmitted character. If bit 2 is a
logic 0, one stop bit is generated in the data. If bit 2 is a logic 1, the number of stop bits generated is dependent
on the word length selected with bits 0 and 1. The receive clocks the first stop bit only, regardless of the number
of stop bits selected. The number of stop bits generated, in relation to word length and bit 2, is shown in the
following.
Bit 2
Word Length Selected
by Bite 1 end 2
Number of Stop
Bite Generated
0
1
1
1
1
Any word length
5 bits
6 bits
7 bits
8 bits
1
11/2
2
2
2
Bit 3. This bit is the parity enable bit. When bit 3 is a logic 1, a parity bit is generated in transmitted data between
the last data word bit and the first stop bit. In received data, if bit 3 is a logic 1, parity is checked. When bit 3 is
a logiC 0, no parity is generated or checked.
Bit 4. Bit 4 is the even parity select bit. When parity is enabled by bit 3: a logic 1 in bit 4 produces even parity
(an even number of logic 1's in the data and parity bits) and a logic 0 in bit 4 produces odd parity (an odd number
of logic 1's).
Bit 5. This is the stick parity bit. When bits 3, 4, and 5 are logic 1s, the parity bit is transmitted and checked as
a logic O. When bits 3 and 5 are logic 1's and bit 4 is a logic 0, the parity bit is transm itted and checked as a logic 1.
If bit 5 is a logiC 0, stick parity is disabled.
Bit 6. This bit is the break control bit. Bit 6 is set to a logic 1 to force a break condition, i.e., a condition where
the serial output (SOUT) pin is forced to the spacing (logic 0) state. When bit 6 is set to a logic 0, the break
condition is disabled. The break condition has no effect on the transmitter logic; it only effects the serial output.
Bit 7. This bit is the divisor latch access bit (OLAB). Bit 7 must be set to Ii logic 1 to access the divisor latches
of the baud generator during a read or write. Bit 7 must be set to a logic 0 during a read or write to access the
receiver buffer, the transmitter holding register, or the interrupt enable register.
TEXAS ",
INSIRUMENTS
POST OFFICE BOX 655303 • DAllAS, TEXAS 75266
3-71
TL16C550A
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS057B - 03128. AUGUST 1989 - REVISED MARCH 1993
PRINCIPLES OF OPERATION
modem control register (MCR)
The modem control register is an a-bit register that controls an interface with a modem, data set, or peripheral
device that is emulating a modem. The contents of this register are summarized in Table 3 and are described
below.
Bit O. Bit 0 (DTR) controls the data terminal ready (DTR) output. Setting this bit to a logic 1 forces the DTR output
to its low state. When bit 0 is set to a logic 0, DTR goes high.
Bit 1. Bit 1 (RTS) controls the request to send (RTS) output in a manner identical to Bit O's control over the DTR
output.
Bit 2. Bit 2 (OUT 1) controls the output 1 (OUT 1) Signal, a user-designated output Signal, in a manner identical
to bit O's control over the DTR output.
Bit 3. Bit 3 (OUT 2) controls the uutput 2 (OUT 2) Signal, a user-designated output Signal, in a manner identical
to bit O's control over the DTR output.
Bit 4. Bit 4 provides a localloopback feature for diagnostic testing ofthe ACE. When this bit is set to a logic high,
the following occurs:
1.
2.
3.
4.
5.
The transmitter serial output (SOUT) is set high.
The receiver serial input (SIN) is disconnected.
The output of the transmitter shift register is looped back into the receiver shift register input.
The four modem control inputs (CTS, DSR, DCD, and RI) are disconnected.
The four modem control outputs (DTR, RTS, OUT 1, and OUT 2) are internally connected to the four
modem control inputs.
'
6. The four modem control output pins are forced to their inactive states (high).
In the diagnostic mode, data that is transmitted is immediately received. This allows the processor to verify the
transmit- and receive-data paths to the ACE. The receiver and transmitter interrupts are fully operational. The
modem control interrupts are also operational but the modem control interrupt's sources are now the lower four
bits of the modem control register instead of the four modem control inputs. All interrupts are still controlled by
the interrupt enable register.
Bit 5 through 7. These bits are permanently set to logic O.
line status register (LSR)t
The line status r~gister provides information to the CPU concerning the status of data transfers. The contents
of this register are described below and summarized in Table 3.
Bit O. Bit 0 is the data ready (DR) indicator for the receiver. This bit is set to a logic 1 condition whenever a
complete incoming character has been received and transferred into the receiver buffer register orthe FIFO and
is reset to logic 0 by reading all of the data in the receiver buffer register or the FIFO.
Bit 1:t. Bit 1 is the overrun error (OE) indicator. When this bit issetto logic 1, it indicates that before the character
in the receiver buffer register was read, it was overwritten by the next character transferred into the register. The
OE indicator is reset every time the CPU reads the contents of the line status register. If the FIFO mode data
continues to fill the FIFO beyond the trigger level, an overrun error will occur only after the FIFO is full and the
next character has been completely received in the shift register. OE is indicated to the CPU as soon as it
happens. The character in the shift register is overwritten but is not transferred to the FIFO.
T The nne :t.ltus ;'sgistar Is intandad fCi iead op6iations anty; wiiting to this iiigisttii is not recoffllnenu&u outside uf iil iCl(;iury iesiing environmeni
; Bits 1 through 4 are the error conditions that produce a receiver line status Interrupt.
1ExAs ..,
3-72
INSIRUMENfS
POST OFFICE BOX 655303 • DAUAS. TEXAS 75265
TL16C550A
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS057B - 03128, AUGUST 1989 - REVISED MARCH 1993
PRINCIPLES OF OPERATION
line status register (LSR) (continued)
Bit 2*·. Bit 2 is the parity error (PE) indicator. When this bit is set to logic 1, it indicates that the parity of the
received data character does not match the parity selected in the line control register (bit 4). The PE bit is reset
every time the CPU reads the contents of the line status register. In the FI FO mode, this error is associated with
the particular character in the FIFO to which it applies. This error is revealed to the CPU when its associated
character is at the top ofthe FIFO.
Bit 3*. Bit 3 is the framing error (FE) indicator. When this bit is set to logic 1, it indicates that the received character
did not have a valid (logic 1) stop bit. The FE bit is reset every time the CPU reads the contents ofthe line status
register. In the FIFO mode, this error is associated with the particular character in the FIFO to which it applies.
This error is revealed to the CPU when its associated character is at the top of the FI FO. The ACE will try to
resynchronize after a framing error. To accomplish this, it is assumed that the framing error is due to the next
start bit. The ACE then samples this start bit twice and then accepts the input data.
\
Bit 4*. Bit 4 is the break interrupt (BI) indicator. When this bit is set to logic 1, it indicates that the received data
input was held in the logic 0 state for longer than a full-word transmission time. A full-word transmission time
is defined as the total time of the start, data, parity, and Stop bits. The B1 bit is reset every time the CPU reads
the contents of the line status register. In the FIFO mode, this error is associated with the particular character
in the FIFO to which it applies. This error is revealed to the CPU when its associated character is at the top of
the FIFO. When break occurs, only on 0 character is loaded into the FIFO. The next character transfer is enabled
after SIN goes to the marking state and receives the next valid start bit.
Bit 5. Bit 5 is the transmitter holding register empty (THRE) indicator. This bit is set to logic 1 when the transmitter
holding register is empty, indicating that the ACE is ready to accept a new character. If the THRE interrupt is
enabled when the THRE bit is a logic 1, then an interrupt is generated. THRE is set to a logic 1 when the contents
of the transmitter holding register are transferred to the transmitted shift register. This bit is reset to logic 0
concurrent with the loading of the transmitter holding register by the CPU. In the FIFO mode, this bit is set when
the transmit FIFO is empty; it is cleared when at least 1 byte is written to the transmit FIFO.
Bit 6. Bit 6 is the transmitter empty (TEMT) indicator. This bit is set to a logic 1 when the transmitter holding
register and the transmitter shift register are both empty. When either the transmitter holding register or the
transmitter shift register contains a data character, the TEMT bit is reset to logic O. In the FIFO mode, this bit
is set to a 1 when the transmitter FIFO and shift register are both empty.
Bit 7. In the TL16C550A, this bit is always reset to logic O. In the TL16C450 mode, this bit is always a O. In the
FIFO mode, LSR7 is set when there is at least one parity, framing, or break error in the FIFO. It is cleared when
the microprocessor reads the LSR and there are no subsequent errors in the FIFO.
modem status register (MSR)
The modem status register is an 8-bit register that provides information about the current state of the control
lines from the modem, data set, or peripheral device to the CPU. Additionally, four bits of this register provides
change information; when a control input from the modem changes state, the appropriate bit is set to logic 1.
All four bits are reset to logic 0 when the CPU reads the modem status register. The contents of this register
are summarized in Table 3 and are described below.
Bit O. Bit 0 is the change in clear to send (DCTS) indicator. This bit indicates that the CTS input has changed
state since the last time it was read by the CPU. When this 'bit is a logic 1 and the modem status interrupt is
enabled, a modem status interrupt is generated.
; Bits 1 through 4 are the error condHions that produce a receiver line status interrupt.
1ExAs ."
INSIRUMENTS
POST OFFICE BOX 6SI5303 • DALlAS, TEXAS 75265
3-73
TL16C550A
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SlLS0578 - 03128. AUGUST 1989 - REVISED MARCH 1993
PRINCIPLES OF OPERATION
modem status register (MSR) (continued)
Bit 1. Bit 1 is the change in data set ready (DDSR) indicator. This bit indicates that the DSR input has changed
state since the last time it was read by the CPU. When this bit is a logic 1 and the modem status interrupt is
enabled, a modem status interrupt is generated.
Bit 2. Bit 2 is the trailing edge of ring indicator (TERI) detector. This bit indicates that the RI input to the chip has
changed from a low to a high state. When this bit is a logic 1 and the modem status interrupt is enabled, a modem
status interrupt is generated.
Bit 3. Bit 3 is the change in data carrier detect (DDCD) indicator. This bit indicates that the DCD input to the chip
has changed state since the last time it was read by the CPU. When this bit is a logic 1 and the modem status
interrupt is enabled, a modem status interrupt is generated.
Bit 4. Bit 4 is the compliment of the clear to send (CTS) input. If bit 4 (loop) of the modem control register is set
to a logic 1, this bit is equivalent to the modem control register bit 1 (RTS).
Bit 5. Bit 5 is the compliment of the data set ready (DSR) input. If bit 4 (loop) of the modem control register is
set to a logic 1, this bit is equivalent to the modem control register bit 1 (DTR).
Bit 6. Bit 6 is the com pliment of the ring indicator (RI) input. If bit 4 (loop) of the modem control register is set
to a logic 1, this bit is equivalent to the modem control registers bit 2 (OUT 1).
Bit 7. Bit 7 is the compliment of the data carrier detect (DCD) input. If bit 4 (loop) otthe modem control register
is set to a logic 1, this bit is equivalent to the modem control registers bit 3 (OUT 2).
scratch register (SCR)
The scratch register is an 8-bit register that is intended for the programmer's use as a scratch pad in the sense
that it will temporarily hold the programmer's data without affecting any other ACE operation.
programmable baud generator
The ACE contains a programmable baud generator that takes a clock input in the range between dc and 8 MHz
and divides it by a divisor in the range between 1 and 216-1. The output frequency of the baud generator is
sixteen times (16 X) the baud rate. The formula for the divisor is:
divisor # = XIN frequency input + (desired baud rate X 16)
Two 8-bit registers, called divisor latches, are used to store the divisor in a 16-bit binary format. These divisor
latches must be loaded during initialization of the ACE in order to ensure desired operation of the baud
generator. When either of the divisor latches is loaded, a 16-bit baud counter is also loaded to prevent long
counts on initial load.
Tables 5 and 6, which follow, illustrate the use ofthe baud generator with crystal frequencies of 1.8432 MHz and
3.072 MHz, respectively. For baud rates of 38.4 kilobits per second and below, the error obtained is very small.
The accuracy of the selected baud rate is dependent on the selected crystal frequency.
Refer to Figure 10 for examples of typical clock circuits.
1ExAs ."
INSIRUMENTS
3-74
POST OFFICE BOX 8S5303 • DAUAS. TEXAS 75265
TL16C550A
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS0578 - 03128, AUGUST 1989- REVISED MARCH 1993
PRINCIPLES OF OPERATION
FIFO Interrupt-mode operation
When the receiver FIFO and receiver interrupts are enabled (FCRO = 1,IERO = 1) receiver interrupts will occur
as follows:
1. The receive data available interrupt will be issued to the microprocesspr when the FI FO has reached its
programmed trigger level. It will be cleared as soon as the FIFO drops below its programmed trigger
level.
2. The IIR receive data available indication also occurs when the FIFO trigger level is reached, and,likethe
interrupt, it is cleared when the FIFO drops below the trigger level.
3. The receiver line status interrupt (IIR = 06), as before, has higher priority than the received data
available (IIR = 04) interrupt.
4. The data ready bit (LSRO) is set as soon as a character is transferred from the shift register to the
receiver FIFO. It is reset when the FIFO is empty.
When the receiver FIFO and receiver interrupts are enabled, receiver FIFO timeout interrupts will occur as
follows:
1. FIFO timeout interrupt will occur if the following conditions exist:
a. At least one character is in the FIFO.
b. The most recent serial character received was longer than 4 continuous character times ago (if 2
stop bits are programmed, the second one is included in this time delay).
c. The most recent microprocessor read of the FIFO was longer than 4 continuous character times
ago. This will cause a maximum character received to interrupt issued delay of 160 ms at 300 baud
with 12-bit character.
2. Character times are calculated by using the RCLK input for a clock signal (this makes the delay
proportional to the baud rate).
3. When a timeout interrupt has occurred, it is cleared and the timer reset when the microprocessor reads
one character from the receiver FIFO.
4. When a timeout interrupt has not occurred, the timeout timer is reset after a new character is received or
after the microprocessor reads the receiver FIFO.
When the transmit FIFO and transmitter interrupts are enabled (FCRO =1, IER1 =1), transmit interrupts will
occur as follows:
1. The transmitter holding register interrupt (02) occurs when the transmit FIFO is empty. It is cleared as
soon as the transmitter holding register is written to (1 to 16 characters may be written to the transmit
FIFO while servicing this interrupt) or the IIR is read.
2. The transmit FIFO empty indications will be delayed 1 character time minus the last stop bit time when
the following occurs: THRE = 1 and there have not been at least two bytes at the same time in the
transmit FIFO since the last THRE = 1. The first transmitter interrupt after changing FCRO will be
immediate, if it is enabled.
Character timeout and receiver FIFO trigger level interrupts have the same priority as the current received data
available interrupt; transmit FIFO empty has the same priority as the current transmitter holding register empty
interrupt.
FIFO polled-mode operation
With FCRO =1, resetting IERO, IER1, IER2, IER3, or all four to 0 puts the ACE in the FIFO polled mode of
operation. Since the receiver and transmitter are controlled separately, either one or both can be in the polled
mode of operation.
1ExAs ."
INSIRUMENIS
POST OFFICE BOX 655300 • DAUAS. TEXAS 75265
3-75
TL16C550A
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS057B - 03128. AUGUST 1989 - REVISED MARCH 1993
PRINCIPLES OF OPERATION
FIFO polled-mode operation (contin"ued)
In this mode, the user program will check receiver and transmitter status via the LSR. As stated previously:
1. LSRO will be set as long as there is one byte in the receiver FIFO.
2. LSR1 through LSR4 will specify which error(s) have occurred. Character error status is handled the
same way as when in the interrupt mode, the IIR is not affected since IER2 = O.
3. LSR5 will indicate when the transmit FIFO is empty.
4. LSR6 will indicate that both the transmit FIFO and shift registers are empty.
5. LSR7 will indicate whether there are any errors in the receiver FIFO.
There is no trigger level reached or timeout conditions indicated in the FI FO polled mode. However, the receiver
and transmit FIFO,s are still fully capable of holding characters.
Table 5. Baud Rates Using A 1.8432-MHz Crystal
DESIRED
BAUD RATE
DIVISOR USED
TO GENERATE
16 X CLOCK
PERCENT ERROR
DIFFERENCE BETWEEN
DESIRED AND ACTUAL
50
2304
75
1536
110
1047
0.026
134.5
857
0.058
150
768
300
384
600
192
1200
96
1800
64
2000
58
2400
48
3600
32
4800
24
7200
16
9600
12
19200
6
38400
3
56000
2
0.69
2.86
1ExAs ..,
INSIRUMENfS
3-76
POST OFFICE BOX _
• DALLAS. TEXAS 75265
TL16C550A
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SUS0678 - 03128, AUGUST 1989 - REVISED MARCH 1993
PRINCIPLES OF OPERATION
Table 6. Baud Rates Using A 3.072·MHz Crystal
DESIRED
BAUD RATE
DIVISOR USED
TO GENERATE
16 X CLOCK
PERCENT ERROR
DIFFERENCE BETWEEN
DESIRED AND ACTUAL
50
3840
75
2560
110
1745
0.026
134.5
1428
0.034
150
1280
3DO
640
600
320
1200
180
1800
107
2000
96
2400
80
3600
53
4800
40
7200
27
9600
20
19200
10
38400
5
0.312
0.628
1.23
VCC
Driver
XlN
External
Clock
lC1
T
~
Rp
Clock
Output
Driver
RX2
Oecillator Clock
XOUT
~
_'--Crystal
Optional
Optional
I~
J~
':'
~--~------~+-wB~d
Generator Logic
XOUT
Oecillator Clock
to Baud
Generator Logic
lC2
T
TYPICAL CRYSTAL OSCILLATOR NETWORK
CRYSTAL
Rp
RX2
3.1 MHz
1 MC
1.5kC
C1
10-30pF '
4O-60pF
1.8 MHz
1 MC
1.5kC
10-30pF
4O-60pF
C2
Figure 16. Typical Clock Circuits
1ExAs
..If
INSIR.UMENTS
POST OFFICE BOX 6!55303 • DAUAS. TEXAS 75265
3-77
3-78
TL16C552
DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
DECEMBER 1990- REVISED MARCH 1993
•
IBM PC/AT Compatible
•
Two TL16C550 ACEs
•
Enhanced Bidirectional Line Printer Port
•
16-Byte FIFOs Reduce CPU Interrupts
•
Independent Control of Transmit, Receive,
Line Status, and Data Set Interrupts on
Each Channel
•
Individual Modem Control Signals for Each
Channel
•
Programmable Serial Interface
Characteristics for Each Channel:
5-,6-,7-, or 8-blt Characters
Even-, Odd-, or No-Parity Bit Generation
and Detection
1-,1 1/2-, or 2-Stop Bit Generation
•
3-State TTL Drive for the Data and Control
Bus on Each Channel
•
Hardware and Software Compatible With
TL16C452
FNPACKAGE
(TOP VIEW)
i.~ ~ ~ ~ d~ ~ ~ I~ ~ ~ ~ ~ ~ -~
~
0
~_:E~
o
1;;1-
~
a:~a:
Iffi
SOUT1
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
10
60
11
59
58
12
13
57
14
56
55
15
54
16
17
53
18
52
19
51
20
50
21
49
48
22
23
24
25
26
47
46
45
44
V~~~~~~M$$~$~~~~~
INT1
INT2
SUN
INIT
AFD
STB
GND
PDO
PD1
PD2
PD3
P04
P05
P06
P07
INTO
BOO
°1°[,121°[,
~og
~o ~ ~ ~F~INr
_-o~ 0°1-1
w~ffi
z~Oa:a:w
ooww~~>a:
description
The TL16C552 is an enhanced dual-channel version of the popular TL16C550 asynchronous communications
element (ACE). The device serves two serial inpuVoutput Interfaces simultaneously in microcomputer or
microprocessor-based systems. Each channel performs serial-to-parallel conversion on data characters
received from peripheral devices or modems and parallel-to-serial conversion on data characters transmitted
by the CPU. The complete status of each channel of the dual ACE can be read at any time during functional
operation by the CPU. The information obtained includes the type and condition of the transfer operations being
performed and the error conditions.
Copyrlght@ 1993, Texas Instruments Incorporated
1ExAs'"
INSIRUMENTS
POST OFFICE BOX 65530G • DALLAS, TEXAS 7S26S
3-79
TL16C552
DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
Su.s102A-D3647.DECEMBER 1990-REVlSEDMARCH 1993 .
description (continued)
In addition to its dual communications interface capabilities,. the TL16CS52 provides the user with a fully
bidirectional parallel data port that fully supports the parallel Centronics-type printer. The parallel port and the
two serial ports provide IBM PC/AT-compatible computers with a single device to serve the three system ports.
A programmable baud rate generator is included that can divide the timing reference clock input by a divisor
between 1 and (216 _1).
The TL16C552 is housed in a 68-pin plastic leaded chip carrier.
functional block diagram
CTSO
DSRO
DCOO
mo
SINO
CSO
DB-DB7
r---
28
24
31
25
29
26
ACE
#1
30
41
32
14-21
45
9
22
RTSO
DTRO
SOUTO
INTO
RXRDYO
TXRDYO
8
'""--
8,
r---
CTS1 13
DSR1 5
11
DCD1 8
10
ACE
112
RI1 6
AO-A2
R5W
36
RESET
CLK
39
60
SIN1 62
61
CS1 3
42
'
Select
and
Control
Logic
4
44
DTR1
SOUT1
INT1
RXRDY1
TXRDY1
BDO
,
8
8
-+--
53-46
57
ERR 63
56
SLCT 65
65
BUSY 56
Parallel
Port
PE 67
58
59
ACi(68
PEMD 1
CS2 38
ENIRQ 43
1ExAs
..If
INSTRUMENTS
3-80
RTS1
...-.-'""--
35-33-
. 37
iC)Fi
12
POST OFFICE BOX _
• DAUAS. TEXAS 75265
PDO-PD7
INIT
AFD
STB
SUN
INT2
TL16C552
DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS102A- 03647, DECEMBER 1990- REVISED MARCH 1993
Terminal Functions
PIN
NAME
I/O
DESCRIPTION
I
Une printer acknowledge. This input goes low to indicate a successful data transfer has taken
place. It generates a printer port interrupt during its positive transition.
Une printer autofeed. This open-drain line provides the Une printer with an active-low signal when
continuous form paper Is to be autofed to the printer. This pin has an internal pullup resistor to Voo
of approximately 10 kg.
ACK
NO.
68
AFD
56
I/O
35,34,33
I
Address lines AO-A2. The address lines select the internal registers during CPU bus operations.
See Table 1 for the decode of the serial channels and Table 11 for the decode of the perallelline
printer port.
BOO
44
0
Bus buffer output. This active-high output is asserted when either serial channel or the parallel port
is read. This output can be used to control the system bus driver (74LS245).
BUSY
66
I
4
32,3,38
I
I
CTSO,CTS1
28,13
I
oBO-oB7
14-21
I/O
Une printer busy. This is an input line from the line printer that goes high when the line printer is
not ready to accept data.
Clock Input. The external clock input to the baud rate dMsor of each ACE.
Chip selects. Each input acts as an enable for the write and read signals for the serial channels
1 (CSO) and 2 (CS1). CS2 enables the signals to the line printer port.
Clear to send inputs. The logical state of each CiS pin is reflected in the CTS bit of the (MSR)
modem status register (CTS is bit 4 of the MSR, written MSR (4» of each ACE. A change of state
in either CTS pin since the previous reading of the associated MSR causes the setting of oCTS
(MSR(O» of eac;h modem status register.
~ata bits oBO-oB7. The data bus provides eight three-state I/O lines for the transfer of data,
control, and status information between the TL16C552 and the CPU. These lines are normally in
a high-impedance state except during read operations. DO is the least significant bit (LSB) and is
the first serial data bit to be received or transmitted.
oCoO,oC01
29,8
I
Data carrier detect. o-C-D is a modem input whose condition can be tested by the CPU by reading
MSR(7) (oCo) of the modem status registers. MSR(3} (OOCO) of the modem status register
indicates whether the DCi5 input has changed since the previous reading of the MSR. DCo has no
effect on the receiver.
oSRO, oSR1
31,5
I
oTRO,oTR1
25,11
0
Data set ready inputs. The logical state of the DSR pins Is reflected in MSR(5) of Its associated
modem status register. ooSR (MSR(1» indicates whether the associated oSR pin has changed
state since the previous reading of the MSR.
Data terminal ready lines. Each oTR pin can be set (low) by writing a logic 1 to MCR(O}, modem
control register bit 0 of its associated ACE. This signal is cleared (high) by writing a logic 0 to the
oTR bit (MCR(O)} or whenever a reset occurs. When active ~ow}, the oTR pin indicates that its ACE
is ready to receive data
ENiRQ
43
I
Parallel port interrupt source mode selection. When low, the AT mode of interrupts is enabled. In
this mode, the INT2 output is internally connected to the ACKinput. If the ENIRQ input is tied high,
the INT2 output is internally tied to the PRI NT signal in the line printer status register. INT2 is latched
high on rising edge of ACK.
ERR
63
I
Une printer error. This is an input line from the line printer. The line printer reports an error by
holding this line low during the error condition.
GNo
INIT
7,27,54
57
I/O
lOR
37
I
Inpul/output read strobe. This Is an active-low input that enables the selected channel to output
data to the data bus (oBO-oB7). The data output depends upon the register selected by the
address inputs AO, A1,A2, and chip select. Chip select 0 (CSO) selects ACE #1 , chip select 1 (CS1)
selects ACE #2, and chip select 2 (~ selects the line printer port.
lOW
36
I
Inpul/output write strobe. This is an active-low input causing data from the data bus to be Input to
either ACE ortothe parallel port. The destination depends upon the register selected by the address
inputs AO, A1, A2, and chip selects CSO, CS1, and C§2.
AO,A1,A2
CLK
CSO, ~S1, CS2
Ground (0 V). All pins must be tied to ground for proper operation.
Une printer intiallze. This open-drain line provides the line printer with an active-low signal that
allows the line printer initialization routine to be started. This pin has an internal pullup resistor to
Voo of approximately 10 kg.
1ExAs
~
INSIRUMENlS
POST OFFICE BOX 855303 • DAU.AS, TEXAS 75265
3-81
TL16C552
DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS102A- 03647, DECEMBER 1990 - REVISED MARCH 1993
Terminal Functions (continued)
PIN
NAME
INTO,lNTl
NO,
45,60
I/O
DESCRIPnON
0
Serial channel Interrupts. Each 3-state serial channel Interrupt output (enabled by bit 3 of the MCR)
goes active (high) when one of the following interrupts has an active (high) condition and Is enabled
by the interrupt enable register of Its associated channel: receiver error flag, received data available,
transmitter holding register empty, and modem status. The interrupt Is reset low upon appropriate
service. Upon reset, the interrupt output will be in the high-impedance state.
Printer port interrupt. This signal is an active-high, three-state output, generated by the positive
transition of ACK. It is enabled by bit 4 of the write control register. Upon a reset, the interrupt output
will be in the high-Impedance state. Its mode is also controlled by'ENiRQ.
59
0
53-46
67
I/O
I
PEMD
1
I
RESET
39
I
RTSO,RTSl
24,12
0
RXRDYO,
RXRDYl
9,61
0
INT2
PDO-PD7
PE
Parallel data bits (0-7). These eight lines provide a byte-wide Input or output port to the system.
Line printer paper empty. This Is an Input line from the line printer that goes high when the printer runs
out of paper.
Printer enhancement mode. When low, this signal enables the write data register to the PDO-PD7
lines. A high on this signal allows direction control of the PDO-7 port by the DIR bit in the control
register. PEMD Is usually tied low for the printer operation.
Reset. When low, the reset Input forces the TL16C552 into an idle mode in which all serial data
activities are suspended. The modem control register (MCR) along with Its associated outputs are
cleared. The line status register (LSR) Is cleared except for the THREand TEMT bits, which are set.
All functions of the device remain in an idle state until programmed to resume serial data activities. This
input has a hysteresis level of typically 400 mV.
Requestto send outputs. An RTS pin Is set low by writing a logic 1 to MCR(l) bit 1 of lis UARTs modem
control register. Both RTS pins are reset high by RESET. A low on the R'i'S pin indicates that its ACE
has data ready to transmit. In half-duplex operations, R'i'S is used to control the direction of the line.
Receiver ready. Receiver DMA signaling is also· available through this pin. One of two types of DMA
signaling cen be selected via FCR3 when operating In the FIFO mode. Only DMA mode 0 II! allowed
when operating in the TL16C450 mode. For signal transfer DMA (a transfer is made between CPU bus
cycles), mode 0 Is used: Multiple transfers that are made continuously until the RCVR FIFO has been
emptied are supported by mode 1.
Mode O. RXRDY will be active (low) when In the FIFO mode (FCRO=l, FCR3=O) or when In the
TL16C450 mode (FCRO=O) and the RCVR FIFO or RCVR holding register contain at least one
character. When there are no more characters In the FIFO or holding register, the RXRDY pin will go
inactive (high).
Mode 1. RXRDY will go active (low) in the FIFO mode (FCRO=l) when FCR3=1 and the timeout or
trigger levels have been reached. It will go inactive (high) when the FIFO or holding register is empty.
RIO,Rll
30,6
I
Ring indicator inputs. The RI signal is a modem control Input whose condition is tested by reading
MSR(6) (RI) of each ACE. The modem status register output TERI (MSR(2» Indicates whather the Ai
Input has changed from high to low since the previous reading of the MSR.
SINO, SINl
41,62
I
SLCT
65
I
SLIN
58
1/0
26, 10
0
55
I/O
Serial data inputs. The serial data inputs move information from the communication line or modem to
the TL16C552 receiver circuits. A mark (1) is high and a space (0) is low. Data on serial data inputs
is disabled when operating in the loop mode.
Line printer selected. This is an input line from the line printer that goes high when the line printer has
been selected.
Line printer select. This open-drain selects the printer when It Is active Oow). This pin has an internal
pullup resistor to VDD of approximately 10 kg.
Serial data outputs. These lines are the serial data outputs from the ACEs transmitter circuitry. A mark
is a logic 1 (hIgh) and a space Is a logic 0 oow). Each SOUT Is held in the mark condition when the
transmitter is disabled, RESET Is true Oow), the transmitter register is empty, or when in the loop mode.
Une printer strobe. This open-drain line provides communication between the TL16C552 and the line
printer. When it is active Oow), It provides the line priner with a Signal to latch the data currently on the
parallel port. This pin has an internal pullup resistor to VDD of approximately 10 kg.
SOUTO, SOUTl
STe
1ExAs ."
INSIRUMENTS
3-82
POST OFFICE BOX 655303 • DAUAS, TEXAS 75265
TL16C552
DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
Su.s102A- 03647, DECEMBER 1990- REVISED MARCH 1993
Terminal Functions (continued)
PIN
I/O
DESCRIPTION
2
I
3-state control. This pin Is used to control the 3-state control of all I/O and output pins. When this pin
is asserted, all I/O and outputs become high Impedance, allowing board level testers to drive the
outputs wfthout overdrMng internal buffers. This pin is level sensitive. This pin is pulled down wfth an
internal resistor that is approximately 5 kQ and Is a CMOS Input.
22,42
0
Transmitter ready. Two types of OMA signaling are available. Either can be selected via FCR3 when
operating in the FIFO mode. Only OMA mode 0 is allowed when operating in the TL 16C450 mode.
Single-transfer OMA (a transfer is made between CPU bus cycles) is supported by mode O. Multiply
transfers that are made continuously until the XMIT FIFO has been filled are supported by mode 1.
NAME
NO.
TRI
TXROYO,
TXROY1
Mode O. When in the FIFO mode (FCRO=l, FCR3=0) or in the TL16C450 mode (FCRO=O) and there
are no characters intheXMIT holding register or XMIT FIFO, TXROYwlll be active Oow). Once TXROY
Is activated (low), It will go Inactive after the first character is loaded into the holding register of XMIT
FIFO.
Mode 1. TXROY will go active (low) if in the FIFO mode (FCRO=l) when FCR3=1 and there are no
characters in the XMIT FIFO. When the XMIT FIFO is completely full, TXROY will go Inactive (high).
VOO
23,40,64
Power supply. The power supply requirement Is 5 V .. 5%.
detailed description
Three types of information are stored in the internal registers used in the ACE: control, status, and data.
Mnemonic abbreviations are shown in the table below for the registers.
CONTROL
MNEMONIC
STATUS
DATA
MNEMONIC
MNEMONIC
Une control register
LCR
Una status register
LSR
Receiver buffer register
RBR
FIFO control register
FCR
Modem status register
MSR
Transmitter holding register
THR
Modem control register
MCR
Divisor latch LSB
OLL
OMsor latch MSB
OLM
Interrupt enable register
IER
The address, read, and write inputs are used with the divisor latch access bit (OLAB) in the line-control register
(bit 7) to select the register to be written or read (see Table 1).
Table 1. Serial Channel Internal Registers
DLAB
A2
A1
AD
MNEMONIC
L
L
L
L
RBR
Receiver buffer register (read only)
REGISTER
L
L
L
L
THR
Transmitter holding register (write only)
L
L
L
H
IER
Interrupt enable register
X
L
H
L
IIR
Interrupt Identification register (read only)
X
L
H
L
FCR
FI FO control register (write only)
X
L
H
H
LCR
Une control register
X
H
L
L
MCR
Modem control register
X
H
L
H
LSR
Line status register
X
H
H
L
MSR
Modem status register
X
H
H
H
SCR
Scratch register
H
L
L
L
OLL
Divisor latch (LSB)
H
L
L
H
OLM.
OMsor latch (MSB)
X = Irrelevant, L = low level, H = high level
NOTE: The serial channel Is accessed when either ~ or CSf is low.
TEXAS'"
INSIRUMENTS
POST OFFICE BOX 65S303 • DAUAS, TEXAS 75265
3-83
TL16C552
DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS1 02A- 03647, DECEMBER 1990- REVISED MARCH 1993
detailed description (continued)
Individual bits within the registers are referred to by the register mnemonic and the bit number in parenthesis.
As an example, LCR (7) refers to line control register bit 7.
The transmitter buffer register and receiver buffer register are data registers that hold from five to eight bits of
data. If less than eight data bits are transmitted, data is right justified to the LSB. Bit 0 of a data word is always
the first serial data bit received and transmitted. The ACE data registers are double buffered so that read and
write operations may be performed when the ACE is performing the parallel-to-serial or serial-to-parallel
conversion.
line-control register
The format of the data character is controlled by the line-control register. The LCR may be read. Its contents
are described below and shown in Figure 1.
LCR(O) and LCR(1) word length select bit 1:
The number of bits in each serial character is programmed as shown in Figure 1.
LCR(2) stop bit select bit 2:
LCR(2) specifies the number of stop bits in each transmitted character as shown in Figure 1. The receiver
always checks for one stop bit.
LCR(3) parity enable bit 3:
When LCR(3) is high, a parity bit between the last data word bit and stop bit is generated and checked.
LCR(4) even parity select bit 4:
When enabled, a logic one selects even parity.
LCR(5) stick parity bit 5:
When parity is enabled (LCR(3)=1). LCR(5)=1 causes the transmission and reception of a parity bit to be in
the opposite state from the value of LCR(4). This forces parity to a known state and allows the receiver to
check the parity bit in a known state.
1ExAs'" ,
INSIRUMENTS
3-84
POST OFFICE BOX 6S5303 • DAUAS, TEXAS 75265
TL16C552
DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS102A- 03647. DECEMBER 1990- REVISED MARCH 1993
Word Length
Select
Stop Bit
Select
Parity Enable
Even Parity
Select
o
o
1
1
0 = 5 Data Bits
1 6 Data Bits
0 7 Data Bits
1 8 Data Bits
=
=
=
o =1 Stop Bits
1 = 1.5 Stop Bits If 5 Data Bits Selected
2 Stop Bits if 6, 7, 8 Data Bits Selected
o = Parity Disabled
1
=Parity Enabled
o =Odd Parity
1
=Even Parity
Stick Parity
o = Stick Parity Disabled
1 = Stick Parity Enabled
Break Control
o
1
DIvisor Latch
AcceeaBit
=Break Disabled
=Break Enabled
o =Access Receiver Buffer
1
=Access Divisor Latches
Figure 1. Line Control Register Contents
line-control register (continued)
LCR(6) break control bit 6:
When LCR(6) is set to a logic 1, the serial output (SOUT1/S0UTO) is forced to the spacing state (low). The
break control bit acts only on the serial output and does not affect the transmitter logic. If the following
sequence is used. no invalid characters will be transmitted because of the break:
Step 1 Load a zero byte in response to the transmitter holding register empty (THRE) status indication.
Step 2 Set the break in response to the next THRE status indication.
Step 3 Wait for the transmitter to be idle when transmitter empty status signal is set high (TEMT=1). Then
clear the break when the normal transmission has to be restored.
LCR(7) divisor latch access bit (DLAB) bit 7:
Bit 7 must be set high (logic 1) to access the divisor latches DLLand DLM ofthe baud rate generator during a
read or write operation. LCR(7) must be input low (logic 0) to access the receiver buffer register, the
transmitter holding register or the interrupt enable register.
TEXAS'"
INSIRUMENTS
POST OFFICE BOX 655303 • DAUAS. TEXAS 75265
3-85
TL16C552
DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SlLS102A~ 03647.
DECEMBER 1990- REVISED MARCH 1993
line status register
The line status register (LSR) is a single register that provides status indications. The line status register shown
in Table 2 is described below:
LSR(O) data ready (DR) bit 0:
Data ready is set high when an incoming character has been received and transferred into the receiver
buffer register or the FI FO. LSR(O) is reset low by a CPU read of the data in the receiver buffer register or the
FIFO.
LSR(1) overrun error (OE) bit 1:
Overrun error indicates that data in the receiver buffer register was not read by the CPU before the next
character was transferred into the receiver buffer register overwriting the previous character. The OE
indicator is reset whenever the CPU reads the contents ofthe line status register. An overrun error will occur
in the FIFO mode after the FIFO is full and the next character is completely received. The overrun error is
detected by the CPU on the first LSR read after it happens. The character in the shift register is not
transferred to the FIFO but it is overwritten.
LSR(2) parity error (PE) bit 2:
Parity error indicates thatthe received data character does not have the correct parity as selected by LCR(3)
and LCR(4). The PE bit is set high upon detection of a parity error and is reset low when the CPU reads the
contents ofthe LSR. In the FIFO mode, the parity error is associated with a particular character in the FIFO.
LSR(2) reflects the error when the character is at the top of the FIFO.
LSR(3) framing error (FE) bit 3:
Framing error indicates that the received character did not have a valid stop bit. LSR(3) is set high when the
stop bit following the last data bit or parity bit is detected as a zero bit (spacing level). The FE indicator is reset
low when the CPU reads the contents of the LSR.lnthe FIFO mode, the framing error is associated with a
particular character in the FIFO. LSR(3) reflects the error when the character is at the top of the FIFO.
Table 2. Une Status Register Bits
LSRBITS
1
0
Ready
Not ready
LSR(l) overrun error (OE)
Error
No error
LSR(2) parity error (PE)
Error
No error
LSR(3) framing error (FE)
Error
No error
LSR(4) break interrupt (81)
Break
No break
LSR(5) transmitter holding register empty (THRE)
Empty
Not empty
LSR(6) transmitter empty (TEM1)
Empty
Not empty
Error in FIFO
No error in FIFO
LSR(O) data ready (DR)
LSR(7) RCVR FIFO error
LSR(4) break interrupt (BI) bit 4:
Break interrupt is set high when the received data input is held in the spacing (logic 0) state for longer than a
full word transmission time (start bit + data bits + parity + stop bits). The BI indicator is reset when the CPU
reads the contents ofthe line status register. In the FIFO mode, this is associated with a particular character
in the FI FO. LSR(2) reflects the BI when the break character is atthe top ofthe FI FO. The error is detected by
the CPU when its associated character is at the top of the FIFO during the first LSR read. Only one zero
character is loaded into the FIFO when BI occurs.
LSR(1) - LSR(4) are the error conditions that produce a receiver line status interrupt (priority 1 interrupt in
the interrupt identification register (IIR)) when any ofthe conditions are detected. This interrupt is enabled by
setting IER(2)=1 in the interrupt enable register.
TEXAS . "
INSIRUMENTS
3-86
POST OFFICE BOX 655303 • DAUAS. TEXAS 75265
TL16C552
DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS102A- 03647, DECEMBER 1990- REVISED MARCH 1993
line status register (continued)
LSR(5) transmitter holding register empty (THRE) bit 5:
THRE indicates that the ACE is ready to accept a new character for transmission. The THRE bit is set high
when a character is transferred from the transmitter holding register into the transmitter shift register. LSR(5)
is reset low by the loading ofthetransmitter holding register by the CPU. LSR(5) is not reset by a CPU read of
the LSR. In the FIFO mode when the XMIT FIFO is empty, this bit is set. It is cleared when one byte is written
to the XMIT FIFO. When the THRE interrupt is enabled by IER(1), THRE causes a priority 3 interrupt in the
IIR.lfTHRE is the interrupt source indicated in IIR, INTRPT is cleared by a read ofthe IIR.
LSR(6) transmitter empty (TEMT) bit 6:
TEMT is set high when the transmitter holding register (THR) and the transmitter shift register (TSR) are
both empty. LSR(6) is reset low when a character is loaded into the THR and remains low until the character
is transferred out of SOUT. TEMT is not reset low by a CPU read of the LSR.ln the FI FO mode, when both the
transmitter FIFO and shift register are empty, this bit is set to one.
LSR(7) RCVR FIFO error bit 7:
The LSR(7) bit is always 0 in the TL16C450 mode. In FIFO mode, it is set when at least one ofthe following
data errors is in the FIFO: parity error, framing error, or break interrupt indication. It is cleared when the CPU
reads the LSR if there are no subsequent errors in the FIFO.
NOTE: The line status register may be written. However, this function is intended only for factory test. It
should be considered as read only by applications software.
FIFO-control register
This write-only register is at the same location as the II R. It is used to enable and clear the FIFOs, set the trigger
level of the RCVR FIFO, and select the type of DMA signaling.
FCR(O) enables both the XMIT and RCVR FIFOs. All bytes in both FIFOs can be cleared by resetting FCR(O).
Data is cleared automatically from the FIFOs when changing from the FI FO mode to the TL16C450 mode and
vice versa. Programming of other FCR bits is enabled by setting FCR(O) =1.
FCR(1) =1 clears all bytes in the RCVR FIFO and resets the counter logic to O. This does not clear the shift
register.
FCR(2) =1 clears all bytes in the XMIT FI FO and resets the counter logic to O. This does not clear the shift
register.
FCR(3) =1 will change the RXRDYand TXRDY pins from mode 0 to mode 1 if FCR(O) =1.
FCR(4) - FCR(5): These two bits are reserved for future use.
FCR(6) - FCR(7): These two bits are used for setting the trigger level for the RCVR FIFO interrupt as follows:
BIT
RCVRFIFO
TRIGGER LEVEL (BYTES)
7
0
6
0
01
0
1
04
1
0
08
1
1
14
1ExAs . "
INSIRUMENTS
POST OFFICE BOX 6515303 • DAlLAS, TEXAS 75266
3-87
TL16C552
DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS102A- 03647, DECEMBER 1990- REVISED MARCH 1993
modem-control register
The modem-control register (MCR) controls the interface with the modem or data set as described in Figure 2.
MCR can be written and read. The RTS and DTR outputs are directly controlled by their control bits in this
register. A high input asserts a low (true) at the output pins. MCR bits 0, 1, 2, 3, and 4 are shown as follows:
MCR(O): When MCR(O) is set high, the DTR output is forced low. When MCR(O) is reset low, the DTR output
is forced high. The DTR output of the serial channel may be input into an inverting line driver in order to obtain
the proper polarity input at the modem or data set.
MCR(1): When MCR£) is set high, the RTS output is forced low. When MCR(1) is reset low, the RTS output
Is forced high. The RT output of the serial channel may be input into an inverting line driver to obtain the proper
polarity input at the modem or data set.
MCR(2): When MCR(2) is set high, OUT1 is forced low.
MCR(3): When MCR(3) is set high, the OUT2 output is forced low.
MCR(4): MCR(4) provides a localloopback feature for diagnostic testing ofthe channel. When MCR(4) is set
high, serial output (SOUT) is set to the marking (logiC 1) state, and the receiver data input serial input (SI N) is
disconnected. The output ofthe transmitter shift register is looped back into the receiver shift register input. The
four modem control inputs (CTS, DSR, DCD, and RI) are disconnected. The modem-control outputs (DTR, RTS,
OIUT1 , and OUT2) are internally connected to the four modem control inputs. The modem-control output pins
are forced to. their inactive state (high) on the TL16C552. In the diagnostic mode, data transmitted is immediately
received. This allows the processor to verify the transmit and receive data paths of the selected serial channel.
Interrupt control is fully operational. However, interrupts are generated by controlling the lower four MCR bits
internally. Interrupts are not generated by activity on the external pins represented by those four bits.
MCR(5) - MCR(7) are permanently set to logic O.
MODEU-CONTROL REGISTER
Data Terminal.
Ready
o = DTR Output High (Inactive)
1 DTR Output Low (active)
Request
to Send
o = RTS Output High (Inactive)
1 RTS Output Low (active)
Out 1
o = OUT1 Output High
1 OUT1 Output Low
Out 2
o
1
=OUT2 Output High
=OUT2 Output Low
Loop
o
1
=Loop Disabled
=Loop Enabled
=
=
=
Bite are Set to logic 0
Figure 2. Modem-Control Register Contents
TEXAS
~
INSIRUMENTS
:HIS
POST OFFICE BOX 655303 • DALlAS, 1EXAS 75265
TL16C552
DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS102A- 03647, DECEMBER 1990- REVISED MARCH 1993
modem-status register
The MSR provides the CPU with status of the modem input lines from the modem or peripheral devices. The
MSR allows the CPU to read the serial channel modem signal inputs by accessing the data bus interface of the
ACE in addition to the current status of four bits of the MSR that indicate whether the modem inputs have
changed since the last reading of the MSR. The delta status bits are set high when a control input from the
modem changes state and reset low when the CPU reads the MSR.
The modem input lines are CTS, DSR, RI, and DCD. MSR(4) - MSR(7) are status indications of these lines.
A status bit = 1 indicates the input is a low. A status bit = 0 indicates the input is high. Ifthe modem-status interrupt
in the interrupt enable register is enabled (IER(3)), an interrupt is generated whenever MSR(O) - MSR(3) is set
to a one. The MSR is a priority 4 interrupt. The contents of the modem-status register are described in Table 3.
MSR(O) delta clear to send (DCTS) bit 0:
DCTS displays that the CTS input to the serial channel has changed state since it was last read by the CPU.
MSR(1) delta data set ready (DDSR) bit 1:
DDSR indicates that the DSR input to the serial channel has changed state since the last time it was read by
the CPU.
MSR(2) trailing edge of ring indicator (TERI) bit 2:
TERI indicates that the RI input to the serial channel has changed state from low to high since the last time it
was read by the CPU. High-to-Iow transitions on RI do not activate TERI.
MSR(3) delta data carrier detect (DDCD) bit 3:
DDCD indicates that the DCD input to the serial channel has changed state since the last time it was read by
the CPU.
MSR(4) clear to send (CTS) bit 4:
CTS is the complement of the CTS input from the modem indicating to the serial channel that the modem is
ready to receive data from the serial channel's transmitter output (SOUT). Ifthe serial channel is in the loop
mode ((MCR(4)=1), MSR(4) reflects the value of RTS in the MCR.
MSR(5) data set ready (DSR) bit 5:
DSR is the complement of the DSR input from the modem to the serial channel that indicates that the
modem is ready to provide received data to the serial channel receiver circuitry. Ifthe channel is in the loop
mode (MCR(4)=1), MSR(5) reflects the value of DTR in the MCR.
Table 3. Modem-Status Register Bits
MSRBIT
MNEMONIC
MSR(O)
DCTS
DESCRIPTION
MSR(1)
DDSR
Delta data set ready
MSR(2)
TERI
Trailing edge of ring indicator
MSR(3)
DDCD
Delta data-carrier detect
MSR(4)
CTS
Clear to send
MSR(5)
DSR
Data set ready
MSR(6)
RI
Ring indicator
MSR(7)
DCD
Delta clear to send
Data-carrier detect
TEXAS . "
INSIRUMENIS
POST OFFICE BOX 655303 • OALlAS, TEXAS 75265
3-89
TL16C552
DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
Su.s102A- 03647, DECEM'BER 1990- REVISED MARCH 1993
modem-status register (continued)
MSR(6) ring indicator (RI) bit 6:
RI is the complement of the RI input, If the channel is in the loop mode (MCR(4)=1), MSR(6) reflects the
value of rnJT1 in the MCR.
MSR(7) data carrier detect (DCD) bit 7:
Data carrier detect indicates the status of the data carrier detect (OeD) input. If the channel is in the loop
mode (MCR(4)=1), MSR(7) reflects the value of OUT2 in the MCR.
Reading the MSR register clears the delta modem status indications but has no effect on the other status
bits. For LSR and MSR, the setting of status bits is inhibited during status register read operations. If a status
condition is generated during a read lOR operation, the status bit is not set until the trailing edge ofthe read.
If a status bit is set during a read operation, and the same status condition occurs, that status bit will be
cleared at the trailing edge of the read instead of ,being set again. In the loop-back mode, when modem
status interrupts are enabled, the CTS, DSR, RI and DCD Input pins are ignored. However, a modem-status
Interrupt may still be generated by writing to MCR3-MCRO. Applications software should not write to the
modem-status register.
divisor latches
The ACE serial channel contains a programmable baud-rate generator (BRG) that divides the clock (dc to
8 MHz) by any divisor from 1 to 216- 1 (see also BRG description). The output frequency ofthe baud generator
is 16X the data rate (divisor # = clock + (baud rate x 16» referred to in this document as RCLK. Two 8-bit divisor
latch registers store the divisor in a 16-bit binary format. These divisor latch registers must be loaded during
initialization. Upon loading either of the divisor latches, a 16-bit baud counter is immediately loaded. This
prevents long counts on initial load. The BRG can use any of three different popular frequencies to provide
standard baud rates. These frequencies are 1.8432 MHz, 3.072 MHz, and 8 MHz. With these frequencies,
standard bit rates from 50 to 512K bps are available. Tables 5, 6, and 7 illustrate the divisors needed to obtain
standard rates using these three frequencies.
scratch pad register
The scratch pad register is an 8-bit read/write register that has no effect on either channel in the ACE. It is
intended to be used by the programmer to hold data temporarily.
interrupt identification register
In order to minimize software overhead during data character transfers, the serial channel prioritizes interrupts
into four levels. The four levels of interrupt conditions are as follows:
1. Receiver line status (priority 1)
2. Received data ready (priority 2) or character timeout
3. Transmitter holding register empty (priority 3)
4.
Modem status (priority 4)
Information indicating that a prioritized interrupt is pending and the type of interrupt is stored in the interrupt
identification register (IIR). The IIR indicates the highest priority interrupt pending. The contents of the IIR are
indicated in Table 4.
3-90
POST OFFICE BOX 655303 • DALlAS. TEXAS 75265
TL16C552
DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLlS102A- 03647. DECEMBER 1990- REVISED MARCH 1993
Table 4. Interupt Identification Register
FIFO
MODE
ONLY
INTERRUPT
IDENTIFICATION
REGISTER
BITO
INTERRUPT SET AND RESET FUNCTIONS
PRIORITY
LEVEL
BIT 3
BIT 2
BIT 1
0
0
0
1
-
0
1
1
0
First
0
1
0
0
1
1
0
0
0
0
0
INTERRUPT SOURCE!
INTERRUPT TYPE
INTERRUPT RESET
CONTROL
-
None
None
Receiver line status
OE. PE. FE. or BI
LSRread
Second
Received data available
Receiver data available or trigger level
reached
RBR read until FIFO
drops below the
trigger level
0
Second
Character timeout
indication
No characters have been removed from
or input to the receiver FIFO during the
last four character times and li1ere is at
least one character in it during this time.
RBRread
1
0
Third
THRE
THRE
JlR read if THRE is
the interrupt source
or THR write
0
0
Fourth
Modem status
CTS. 'i5SR. RI. or DCD
MSRread
interrupt identification register (continued)
IIR(O) can be used to indicate whether an interrupt is pending. When IIR(O) is low, an interrupt is pending.
IIR(1) and IIR(2) are used to identify the highest priority interrupt pending as indicated in Table 4.
IIR(3): This bit is always logic 0 when in the TL16C450 mode. This bit is set along with bit 2 when in the FIFO
mode and a trigger change level interrupt is pending.
IIR(4) - IIR(5): These two bits are always set to logic O.
IIR(6) - IIR(7): FCR(O)=1 sets these two bits.
interrupt enable register
The interrupt enable register (IER) is used to independently enable the four serial channel interrupt sources
that activate the interrupt (INTO or INT1) output. All interrupts are disabled by resetting IER(O) -IER(3) of the
interrupt enable register. Interrupts are enabled by setting the appropriate bits of the IER high. Disabling the
interrupt system inhibits the interrupt identification register and the active (high) interrupt output. All other system
functions operate in their normal manner, including the setting of the line status and modem status registers.
The contents of the interrupt enable register are described in Table 9 and below.
IER(O). When set to one, IER(O) enables the received data available interrupt and the timeout interrupts in the
FIFO mode.
IER(1). When set to one, IER(1) enables the transmitter holding register empty interrupt.
IER(2). When set to one IER(2) enables the receiver line status interrupt.
IER(3). When set to one, IER(3) enables the modem status interrupt.
IER(4) -IER(7). These four bits ofthe IER are logic O.
1ExAs
~
INSIRUMENIS
POST OFACE BOX 655303 • DAUAS. TEXAS 75265
TL16C552
DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS102A-D3647. DECEMBER 1990-REVlSED MARCH 1993
receiver
Serial asynchronous data is input into the SIN pin. The ACE continually searches for a high-to-Iow transition
from the idle state. When the transition is detected, a counter is reset, and counts the 16X clock to 7 1/2, which
is the center ofthe start bit. The start bit is valid if the SIN is still low. Verifying the start bits prevents the receiver
from assembling a false data character due to a low-going noise spike on the SIN input.
The line-control register determines the number of data bits in a character [LCR(O), LCR(1)). If parity is used
LCR(3) and the polarity of parity LCR(4) are needed. Status for the receiver is provided in the line status register.
When a full character is received, including parity and stop bits, the data received indication in LSR(O) is set high.
The CPU reads the receiver buffer register, which resets LSR(O). If the character Is not read prior to a new
character transfer from the RSR to the RBR, the overrun error status Indication is setin LSR(1). Ifthere is a parity
error, the parity error is set in LSR(2). If a stop bit is not detected, a framing error indication is set in LSR(3).
If the data into SIN is a symmetrical square wave, the center of the data celis will occur within :1:3.125% of the
actual center, providing an error margin of 46.875%. The start bit can begin as much as one 16X clock cycie
prior to being detected.
master reset
After power up, the ACE RESET input should be held low for one microsecond to reset the ACE circuits to an
idle mode until initialization. A low on RESET causes the following:
1. Intializes the transmitter and receiver clock counters.
2. Clears the line status register (LSR) , exceptfortransmitter shift register empty (TEMl) and transmit holding
register empty (THRE) , which are set. The modem control register (MCR) is also cleared. All of the discrete
lines, memory elements, and miscellaneous logic associated with these register bits are also cleared or
turned off. The line control register (LCR), divisor latches, receiver buffer register, and transmitter buffer
register are not affected.
Following the removal of the reset condition (RESET high), the ACE remains in the idle mode until programmed.
A hardware reset of the ACE sets the THRE and TEMT status bit in the LSR. When interrupts are subsequently
enabled, an interrupt occurs due to THRE.
A summary of the effect of a reset on the ACE is given in Table 8.
programming
The serial channel ofthe ACE is programmed by the control registers: LCR, IER, DLL, DLM, MCR, and FCR.
These control words define the character length, number of stop bits, parity, baud rate, and modem interface.
While the control registers can be written in any order, the IER should be written last because it controls the
interrupt enables. Once the serial channel is programmed and operational, these registers can be updated any
time the ACE serial channel is not transmitting or receiving data.
1ExAs
..If
INSIRUMENfS
3-92
POST OFFICE BOX _
• DAUAS. TEXAS 75265
TL16C552
DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLlS102A-D3647. DECEMBER 1990-REVISED MARCH 1993
FIFO-interrupt-mode operation
The following RCVR status occurs when the RCVR FIFO and receiver interrupts are enabled:
1. LSR(O) is set when a character is transferred from the shift register to the RCVR FIFO. When the FIFO is
empty, it is reset.
2. IIR = 06 receiver line status interrupt has higher priority than the received data available interrupt IIR = 04.
3. Receive data available interrupt will be issued to the CPU when the programmed trigger level is reached
by the FIFO. As soon as the FIFO drops below its programmed trigger level, it will be cleared.
4.
IIR = 04 (receive data available indication) also occurs when the FIFO reaches its trigger leveL It is cleared
when the FIFO drops below the programmed trigger level.
The following RCVR FIFO character timeout status occurs when RCVR FIFO and receiver interrupts are
enabled.
1. If the following conditions exist, a FI FO character timeout interrupt occurs.
Minimum of one character in FIFO
Last received serial character was longer than 4 continuous previous character times ago (if two stop bits
are programmed, the second one is included in the time delay).
The last CPU read ofthe FIFO was more than 4 continuous character times earlier. At 300 baud and 12-bit
characters, the FIFO timeout interrupt causes a latency of 160 ms maximum from received character to
interrupt issued.
2.
By using the RCLK input for a clock Signal, the character times can be calculated. (The delay is proportional
to the baud rate.)
3. The timeout timer is reset after the CPU reads the RCVR FIFO or after a new character is received, when
there has been no timeout interrupt.
4. A timeout interrupt is cleared and the timer is reset when the CPU reads a character from the RCVR FIFO.
XMIT interrupts occur as follows when the transmitter and XMIT FIFO interrupts are enabled (FCRO
IER = 1).
= 1,
1. When the transmitter FIFO is empty, the transmitter holding register interrupt (IIR = 02) occurs. The interrupt
is cleared as soon as the transm itter holding register is written to or the II R is read. One to sixteen characters
may be written to the transmit FIFO when servicing this interrupt.
2. The XMIT FIFO empty indications will be delayed one character time minus the last stop bit time whenever
the following occurs:
THRE = 1 and there has not been a minimum of two bytes at the same time in XMIT FIFO, since the last
THRE =1. The first transmitter interrupt after changing FCRO will be immediate, however, assuming it is
enabled.
RCVR FI FO trigger level and character timeout interrupts have the same priority as the received data available
interrupt. The transmitter holding register empty interrupt has the same priority as the transmitter FIFO empty
interrupt.
1ExAs ."
INSIRlJMENTS
POST OFFICE BOX 6S5303 • DAUAS. TEXAS 75265
3-93
TL16C552
DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
Su.s102A- 03647. DECEMBER 1990 - REVISED MARCH 1993
FIFO polled mode operation
.Resetting IERO, IER1, IER2, IER3, or all to zero, with FCRO = 1, puts the ACE into the FIFO polled mode. RCVR
and XMITER are controlled separately. Therefore, either or both can be in the polled mode.
In the FIFO pOlled mode, there is no timeout condition indicated or trigger level reached. However, the RCVR
and XMIT FIFOs still have the capability of holding characters. The LSR must be read to determine the ACE
status.
Table 5. Baud. Rates (1.8432-MHz clock)
BAUD RATE
DESIRED
50
75
110
134.5
150
300
600
1200
1800
2000
2400
3600
4800
7200
9600
19200
38400
56000
DIVISOR (N) USED TO
GENERATE 16 X CLOCK
PERCENT ERROR DIFFERENCE
BETWEEN DESIRED AND ACTUAL
2304
1536
1047
857
768
384
192
96
0.026
0.058
64
-
58
0.690
-
48
32
24
16
12
6
3
2
-
-
2.860
Table 6. Baud Rates (3.072-MHz clock)
BAUD RATE
DESIRED
50
75
110
134.5
150
300
600
1200
1800
2000
2400
3600
4800
7200
9600
19200
38400
DIVISOR (N) USED TO
GENERATE 16 X CLOCK
PERCENT ERROR DIFFERENCE
BETWEEN DESIRED AND ACTUAL
3840
2560
1745
1428
1280
640
320
160
107
96
80
63
0.026
0.034
-
-
-
0.312
-
0.628
40
-
27
1.230
20
10
5
--
1ExAs ..,
INSIRUMENTS
H4
--
POST OFFICE BOX 655303 • DAUAS. TEXAS 75265
-
TL16C552
DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
Su..s102A- 03647, DECEMBER 1990- REVISED MARCH 1993
Table 7. Baud Rates (S.192-MHz clock)
BAUD RATE
DESIRED
50
75
110
134.5
150
300
600
1200
1800
2000
2400
3600
4BOO
7200
9600
19200
3B400
56000
128000
256000
512000
DIVISOR (N) USED TO
GENERATE 16 X CLOCK
PERCENT ERROR DIFFERENCE
BElWEEN DESIRED AND ACTUAL
-
1000
6667
4545
3717
3333
1667
833
417
277
250
208
139
104
69
52
26
13
9
4
2
1
0.005
0.010
0.013
0.010
0.020
0.040
0.080
O.OBO
-
0.160
O.OBO
0.160
0.644
0.160
0.160
0.160
0.790
2.344
2.344
2.400
Table S. RESET
REGISTER/SIGNAL
RESET CONTROL
RESET
Interrupt enable register
Reset
All bits low (0-3 forced and 4-7 pennanent)
Interrupt identification
register
Reset
Bit 0 is high. bits 1. 2. 3. 6, and 7 low
Bits 4-5 are pennanently low
Une control register
Reset
All bHs low
Modem control register
Reset
All bits low
FIFO control register
Reset
All bits low
Une status register
Reset
All bits low, except bHs 5 and 6 are high
Modem status register
Reset
Bits 0-3 low, bits 4-7 input signal
SOUT
Reset
High
Interrupt (RCVR errs)
Read LSRlReset
Low
Interrupt (RCVR data ready)
Read RBRIReset
Low
Read lIR/WrHe THRIReset
Low
Interrupt (THRE)
Interrupt (modem status changes)
Read MSRlReset
Low
OUT2
Reset
High
RTS
Reset
High
OTR
Reset
High
OUT1
Reset
High
1ExAs ."
INSTRUMENTS
POST OFFICE BOX 655303 • DAUAS, TEXAS 75265
3-95
TL16C552
DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS102A-D3647, DECEMBEA 1990- AEVISED MARCH 1993
Table 9. Serial Channel Accessible Registers
ADDRESS
0
REGISTER BIT NUMBER
REGISTER
MNEMONIC
ABA
(read only)
BIT 7
BITS
BITS
BIT 4
BIT a
BIT 2
BIT 1
BIT 0
Data
Data
Data
Data
B~7
B~6
B~5
B~4
Data
Btt3
Data
Btt2
Data
Bft1
Data
Bit 0
(LSB)
(MSB)
0
THA
(write only)
Data
Data
Data
Data
B~5
B~4
Data
Bit 2
Data
B~6
Data
BRa
Data
B~7
B~1
B~O
OT
OLL
B~7
B~6
B~5
Btt4
BH3
BH2
B~1
B~O
1t
OLM
B~15
B~14
B~13
Bft12
B~11
B~10
BU
B~8
1
lEA
0
0
0
0
(EDSSI)
Enable
modem
(EALSJ)
Enable
receiver
line
(ETBEI)
Enable
transmitter
holding
register
(ERBFI)
Enable
received
data
available
interrupt
status
interrupt
status
Interrupt
empty
interrupt
2
FCR
(writeonty)
RCVR
Trigger
(MSB)
RCVR
Trigger
(LSB)
Resarvad
Aeserved
DMA
mode
select
XMIT
FIFO
reset
ACVR
FIFO
rasa!
FIFO
Enable
2
IIR
(rasdonty)
FIFOs
Enabled*
FIFOs
Enabled*
0
0
Interrupt 10
BH(2)*
Interrupt 10
BH(1)
Interrupt 10
Bft(O)
Olf
interrupt
pending
3
LCA
(DLAB)
Divisor latch
access bit
Set
break
Stick
perRy
(EPS)
Evanpaity
select
(PEN)
Parity
enable
(STB)
Numbsrof
atopbHs
(WlSB1)
Wordlenglh
select bit 1
(WLSBO)
Word length
select bft 0
0
0
0
Loop
Enable
external
Interrupt
(INTO or
INn)
OUT1
(an unused
Internal
signal)
(RTS)
Request
'to sand
(PE)
Parity
error
(OE)
Overrun
error
ready
data carrier
detect
(TERI)
Trailing
edgaring
Indicator
(DDSR)
Datta
dataset
ready
(DCTS)
Delta
cl_
to sand
B~3
BH2
Bft1
Bit 0
4
S
6
7
MCR
LSR
MSR
Error In
RCVR
AFO*
(TEMn
Transmitter
empty
(THAE)
Transmitter
holding
register
ampty
(81)
Break
interrupt
(FE)
Framing
(DCO)
Data carrier
detect
(AI)
Ring
indicator
(DSR)
Dataset
reedy
(CTS)
Clear
to sand
(DDCD)
BH7
BHS
BitS
Bit 4
SCR
error
Datta
I
(DTR)
Data
terminal
ready
(DR)
Data
t DI.AB = 1
:I: These bits are always 0 when FIFOs are disabled.
parallel port registers
The TL16C552's parallel port can be used to interface the device to a Centronics-style printer. When chip select
2 (CS2) is low, the parallel port is selected. Table 11 shows the registers associated with this parallel port. The
read or write function of the register is controlled by the state of the read (lOR) and write (lOW) pin as shown.
The read data register allows the microprocessor to read the information on the parallel bus.
The read status register allows the microprocessor to read the status of the printer in the six most significant
bits. The status bits are printer busy BSY. acknowledge (ACK) which is a handshake function. paper empty (PE).
printer selected (SLCT) •.error (ERR) and printer interrupt (PRINT). The read control register allows the state
of the control lines to be read. The write control register sets the state of the control lines. They are direction
(OIR). interrupt enable (INT2 EN). select in (SLlN). initialize the printer (INIT). autofeed the paper (AFO). and
strobe (STB). which informs the printer ofthe presence of a valid byte on the parallel bus. The write data register
allows the microprocessor to write a byte to the parallel bus. The parallel port is completely compatible with the
parallel port implementation used in the IBM serial parallel adaptor.
1ExAs ."
INSIR.UMENTS
3-96
POST OFFICE
eox _
• DALLAS, TEXAS 75265
TL16C552
DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS1 02A- 03647, DECEMBER 1990 - REVISED MARCH 1993
Table 10. Parallel Port Registers
REGISTER
REGISTER BITS
BIT 7
BIT6
BIT 5
BIT4
BIT 3
BIT 2
BIT 1
BITO
Read Data
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD~
Read Status
BSY
ACK
PE
SLCT
ERR
PRINT
1
1
Read Control
0
0
DIR
INT2EN
SLIN
INIT
AFD
STB
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD~
0
0
DIR
INT2EN
SLIN
INIT
AFD
STB
Write Data
Write Control
Table 11. Parallel Port Register Select
CONTROL PINS
REGISTER SELECTED
lOR
lOW
CS2
A1
L
H
L
L
L
Read data
L
H
L
L
H
Read status
L
H
L
Read control
H
L
H
H
L
L
H
Invalid
Write data
AO
H
L
L
L
L
H
L
L
L
H
Invalid
H
H
L
L
L
Write control
L
L
H
H
H
Invalid
line printer port
The line printer port contains the functionality of the port included in the TL16C452, but offers a hardware
programmable extended mode controlled by the printer enhancement mode (PEMD) pin. This enhancement
is the addition of a direction control bit, and an interrupt status bit.
register 0 line printer data register
The line printer (LPD) port is either output only or bidirectional, depending on the state of the extended mode
pin and data direction control bits.
Compatibility mode (PEMD pin
=0)
Reads to the LPD register return the last data that was written to the port. Write operations immediately
output data to the PDO-PD7 pins.
Extended mode (PEMD pin
=1)
Read operations return either the data last written to the LPT data register if the direction bit is set to write
(low), or the data that is present on PDO- PD7 if the direction is set to read (high). Writes to the LPD register
latch data into the output register, but only drive the LPT port when the direction bit is set to write (low).
The table below summarizes the possible combinations of extended mode and the direction-control bit. In
either case, the bits of the LPD register are defined as follows:
PEMD
DIR
PDO-PD7 FUNCTION
L
X
PC/AT mode - output
H
H
0
PS/2 mode - output
1
PS/2 mode - input
1ExAs
~
INSIRUMENIS
POST OFFICE BOX 656303 • DALlAS, TEXAS 75265
3-97
TL16C552
DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS1 02A- 03647, DECEMBER 1990 - REVISED MARCH 1993
register 1 read line printer status register
The line printer status (LPS) register is a read-only register that contains interrupt and printer status of the LPT
connector pins. In the table below (in the default column), are the values of each bit after reset in the case of
the printer being disconnected from the port. The bits are described as follows:
BIT
DESCRIPTION
DEFAULT
0
Reserved
1
1
Reserved
1
2
PRINT
1
3
ERR
4
SLCT
t
t
t
t
t
5
PE
6
ACK
7
BSY
t Outputs are dependent upon device Inputs.
Bits 0 and 1 - Reserved. Read as ones.
Bit 2 - Printer interrupt (PRI NT, active low) status bit. When set (low) indicates that the printer has acknowledged
the previous transfer with an ACK handshake (bit if 4 of the control register is set to 1). The bit is set to zero on
the active to inactive transition of the ACK signal. This bit is set to a one after a read of the status port.
Bit 3 - Error (ERR, active low) status bit corresponds to ERR input.
Bit 4 - Select (SLCT) status bit corresponds to SLCT input.
Bit 5 - Paper empty (PE) status bit corresponds to PE input.
Bit 6 - Acknowledge (ACK, active low) status bit corresponds to ACK input.
Bit 7 - Busy (BSY, active low) status bit corresponds to BUSY input (active high).
I
register 2 IIne-prlnter-control register
The line-printer-control (LPC) register is read/write port that is used to control the PDO- PD7 direction and drive
the printer-control lines. Write operations set or reset these bits, while read operations return the state of the
last write operation to this register. The bits In this register are defined as follows:
BIT
DESCRIPTION
0
STB
1
AFD
2
INIT
3
SUN
4
INT2 EN
5
DIR
6
Reserved (0)
7
Reserved (0)
Bit 0 - Printer strobe (STB) control bit; when 1, the STB signal is asserted on the LPT interface; when 0, the
signal is negated.
Bit 1 - Auto feed (AFD) control bit; when 1, the AFD signal will be asserted on the LPT interface; when 0, the
Signal is negated.
Bit 2 - Initialize printer (INIT) control bit; when 1, the INITsignal is negated; when 0, the INITsignal is asserted
on the LPT interface.
1ExAs
~
INSIRUMENTS
3-98
POST OFFICE BOX 655303 • DALlAS, TEXAS 75265
TL16C552
DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS102A- 03647, DECEMBER 1990- REVISED MARCH 1993
register 2 IIne-prlnter-control register (continued)
Bit 3 - Select input (SUN) control bit; when 1, the SLCT signal is asserted on the LPT interface; when 0, the
signal is negated.
Bit 4 - I nterrupt request enable (I NT2 EN) control bit; when 1, enables interrupts from the LPT port whenever
the ACK signal is released; when 0, disables interrupts and places INT2 signal in 3-state,
Bit S - Direction (DIR) control bit (only used when PEMD is high); when 1, the output buffers in the LPD port
are disabled allowing data driven from external sources to be read from the LPD port. When DIR is low,
the LPD port is in output mode.
absolute maximum ratings over operating free-air temperature range {unless otherwise noted)t
Supply voltage range, Voo (see Note 1) .......... ,........................... -O.S V to Voo + 0.3 V
Input voltage range, VI .............................................................. -O.S V to 7 V
Output voltage range, Vo ................................................... -O.S V to Voo + 0.3 V
Continuous total power dissipation ....................................................... SOO mW
Operating free-air temperature range ................................................ -1 O'C to 70'C
Storage temperature range ....................................................... -6S'C to 150'C
t Stresses beyond those listed under "absolute maximum ratings' may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions' is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: Ali voltage levels are with respect to ground (Vssl.
recommended operating conditions
Supply voltage, VOO
MIN
NOM
MAX
UNIT
4.75
5
5.25
V
VOO
0.8
V
VOO
0.8
V
2
Clock high-level input voRage, VIHICLK)
-0.5
Clock low-level input voltage, VIL(CLK)
High-level inpui voRage, VIH
2
Low-level input voRage, VIL
-0.5
8
Clock frequency, fclock
Operating free-air temperature range, TA
0
1ExAs
70
V
V
MHz
·C
~
INSlRUMENIS
POST OfFICE BOX 65S303 • DAUAS. TEXAS 75265
3-99
TL16C552
DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SUS102A-D3647. DECEMBER 1990-REVISED MARCH 1993
electrical characteristics over recommended range~ of operating free-air temperature and supply
voltage
TEST CONDITIONS
PARAMETER
VOH
High-level output voltage
IOH = -0.4 mA for OBO-OB7.
IOH = -2 mA for POO-P07,
IOH= -0.4 mA for INIT, AFO. STB, and SUN (see Note 2).
IOH = -0.4 rnA for all other outputs
VOL
Low-level output voltage
IOL =4 mA for OBO-OB7.
IOL = 12 mA for POO-P07.
IOL =10 mA for INIT, AFO. STB. and SLiN (see Note 2).
IOL = 2 mA for all other outputs
II
Input current
VOO=5.25V,
II(CLK)
Clock Input current
VI =Oto 5.25 V
IOZ
Off-state output current
Va 0 with chip deselected. or
VOO=5.25V,
Va = 5.25 V with chip and write mode selected
100
Supply current
VOO 5.25 V,
No loads on outputs.
SINO, SIN1. OSRO. DSR1. OCDO. OC01.~. CTSf.
Other inputs at 0.8 V.
RIO and RI1 at 2 V,
Baud rate = 66 kb/s
Baud rate generator fclock = 8 MHz,
MIN
MAX
V
2.4
All other pins are floating
=
UNIT
0.4
V
",10
",10
IlA
IlA
",20
IlA
50
mA
=
clock timing requirements over recommended ranges of operating free-air temperature and supply
voltage
MIN
MAX
UNIT
tw1
Pulse duration. CLK high (external clock. 8 MHz max) (see Figure 3)
55
ns
tw2
Pulse duration. CLK low (external clock. 8 MHz max) (see Figure 3)
55
ns
Iw3
Pulse duration. master reset (see Figure 18)
1000
ns
read cycle timing requirements over recommended ranges of operating free-air temperature and
supply voltage (see Figure 6)
MIN
MAX
UNIT
tw4
Pulse duration. lOR low
80
ns
tsu1
Setup time, chip select valid before lOR low (see Note 3)
15
ns
isu2
Setup time. A2-AO valid before lOR low (see Note 3)
15
ns
1h1
th2
Hold time. A2-AO valid after lOR high (see Note 3)
20
ns
20
ns
id1
Delay time, isu2 + tw4 + id2 (see Note 4)
Delay time, lOR high to lOR or lOW low
175
80
ns
Hold time. chip select valid after lOR high (see Note 3)
id2
NOTES: 2. These four pins contain an internal pullup resistor to VOO of approximately 10 kg.
3. The Internal address strobe is always acllve.
4. In the FIFO mode. td1 425 ns (min) between reads of the receiver FIFO and the status registers (IIR and LSR).
=
1ExAs
3-100
-II
INSIRlJMENTS
POST OFFICE BOX 665303 • DAllAS, TEXAS 75265
ns
TL16C552
DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS102A- 03647, DECEMBER 1990 - REVISED MARCH 1993
write cycle timing requirements over recommended ranges of operating free-air temperature and
supply voltage (see Figure 7)
MIN
MAX
UNIT
1w5
Pulse duration, iOW low
ao
ns
tsu4
Setup time, chip select valid before lOW low (see Note 3)
15
ns
tsu5
Setup time, A2.-AO valid before lOW low (see Note 3)
15
ns
tsu6
th3
Setup time, 00-07 valid before lOW high
15
ns
Hold time, A2.-AO valid after lOW high (see Note 3)
20
ns
1J14
Hold time, chip select valid after lOW high (see Note 3)
20
ns
IJ1s
Hold time, 00-07 valid after lOW high
lS
ns
1e13
Delay time, tsus + Iws + 1e14
Delay time, iOW high to lOW or lOR low
1e14
NOTE 3: The Internal address strobe Is always active.
175
ns
ao
ns
read cycle switching characteristics over recommended ranges of operating free-air temperature
and supply voltage (see Figure 6)
PARAMETER
TEST CONDITIONS
Propagation delay time from lOR high to BOO high or from lOR low to
BDOlow
CL = 100 pF,
See NoteS
Enable time from lOR low to DO-07vaJid
CL = 100 pF,
fen
Disable time from lOR high to 00-07 released
CL = 100 pF,
IeIls
NOTE 5: VOL and VOH (and the external loading) determine the charge and discharge time.
See NoteS
tpdl
See NoteS
MIN
0
MAX
UNIT
60
ns
60
ns
60
ns
transmitter switching characteristics over recommended ranges of operating free-air temperature
and supply voltage (see Figures 8, 9, and 10)
PARAMETER
TEST CONDITIONS
MAX
UNIT
8
24
RCLK
cycles
MIN
leis
Delay time, Interrupt THRE low to SOUT low at start
1e16
Delay time, SOUT low at start to Interrupt THRE high
See Note a
a
8
RCLK
cycles
1e17
Delay time, iOW (WR THR) high to interrupt THRE high
See Note 8
16
32
RCLK
cycles
lela
Delay time, SOUT low at start to TXROY low
CL=100pF
a
RCLK
cycles
Propagation delay time from lOW (WR THR) low to interrupt THRE low
140
CL=100pF
tDd2
140
CL=100pF
~d4' Propagation delay time from lOR (RO IIR) high to interrupt THRE low
19S
Propagation delay time from lOW (WR THR) high to TXROY high
CL=100pF
tDdS
NOTE 6: If the transmitter Interrupt delay is active, this delay will be lengthened by one character time minus the lest stop bit time.
1ExAs
ns
ns
ns
~
INSIRUMENTS
POST OFFICE BOX 655303 • DAU.AS, TEXAS 75265
3-101
TL16C552
DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS102A- 03647, DECEMBER 1990- REVISED MARCH 1993
receiver switching characteristics over recommended ranges of operating free-air temperature
and supply voltage (see Figures 11, 12, 13, 14 and 15)
TEST CONDITIONS
PARAMETER
MIN
See Note 7
I or <3
A buffer or element with more than usual output capability (symbol is oriented in the direction of
signal flow).
.cr
Schmitt trigger; element with hysteresis
X/Y
Coder, code converter, level converter
The following are examples of subsets of this general class of qualifying symbol used in this book.
BCD/7·SEG
BCD to 7 -segment display driver
TTL/MOS
TTL to MOS level converter
CMOS/PLASMA DISP
Plasma-display driver with CMOS-compatible inputs
MOS/LED
Light-emitting-diode driver with MOS-compatible inputs
CMOSIVAC FLUOR DISP
Vacuum-fluorescent display driver with CMOS-compatible
CMOS/EL DISP
Electroluminescent display driver with CMOS-compatible
inputs
inputs
TTL/GAS DISCH DISPLAY
SRGm
3.2
Gas-discharge display driver with TTL-compatible inputs
Shift register. m = number of bits.
Qualifying Symbols for Inputs and Outputs
Qualifying symbols for inputs and outputs are shown in Table 2 and many will be familiar to most users,
a likely exception being the logic polarity symbol for directly indicating active-low inputs and outputs.
The older logic negation indicator means that the external 0 state produces the internal 1 state. The
internal 1 state means the active state. Logic negation may be used in pure logic diagrams; in order
to tie the external 1 and 0 logic states to the levels H (high) and L (low), a statement of whether positive
logic (1 = H, 0 = L) or negative logic (1 = L,O = H) is being used is required or must be assumed.
Logic polarity indicators eliminate the need for calling out the logic convention and are used in this data
book in the symbology for actual devices. The presence of the triangle polarity indicator indicates that
the L logic level will produce the internal 1 state (the active state) or that, in the case of an output,
the internal 1 state will produce the external L level. Note how the active direction of transition for a
dynamic input is indicated in positive logic, negative logic, and with polarity indication.
When nonstandardized information is shown inside an outline, it is usually enclosed in square brackets
[like thesel. The square brackets are omitted when associated with a nonlogic input, which is indicated
by an X superimposed on the connection line outside the symbol.
4-6
Table 2. Qualifying Symbols for Inputs and Outputs
------q
P---
Logic negation at input. External
° produces internal 1.
Logic negation at output. Internal 1 produces external 0.
~
--ci in positive logic
Active-low output. Equivalent to t:r- in positive logic
~
Active-low input in the case of right-to-Ieft signal flow
~
Active-low output in the case of right-to-Ieft signal flow
--+-
Signal flow from right to left. If not otherwise indicated. signal flow is from left to right.
-++-
Bidirectional signal flow
---..t::=.j
Active-low input. Equivalent to
POSITIVE
LOGIC
room;'!
inputs
active
on
indicated
transition
3.3
1Lo
not used
OS1
NEGATIVE
LOGIC
POLARITY
INDICATION
15°
not used
not used
°L1
H~L
H
LJ
~
Nonlogic connection. A label inside the symbol will usually define the nature of this pin.
~
Input for analog signals (on a digital symbol) (see Figure 11)
~
-I
Input for digital signals (on an analog symbol) (see Figure 11)
Symbols Inside the Outline
Table 3 shows some symbols used inside the outline. Note particularly that open-collector (open-drain),
open-emitter (open-source), and three-state outputs have distinctive symbols. Also note that an EN input
affects all of the outputs of the element and has no effect on inputs. An EN input affects all the external
outputs of the element in which it is placed, plus the external outputs of any elements shown to be
influenced by that element. It has no effect on inputs. When an enable input affects only certain outputs,
affects outputs located outside the indicated influence of the element in which the enable input is placed,
and/or affects one or more inputs, a form of dependency notation will indicate this (see 4.9). The effects
of the EN input on the various types of outputs are shown.
It is particularly important to note that a D input is always the data input of a storage element. At its
internal 1 state, the D input sets the storage element to its 1 state, and at its internal 0 state it resets
the storage element to its 0 state.
The binary grouping symbol will be explained more fully in Section 6.11. Binary-weighted inputs are
arranged in order and the binary weights of the least significant and the most significant lines are indicated
by numbers. In this document weights of input and output lines will be represented by powers of two
usually only when the binary grouping symbol is used, otherwise decimal numbers will be used. The
grouped inputs generate an internal number on which a mathematical function can be performed or that
can be an identifying number for dependency notation. This number is the sum of the weights
(1, 2, 4 ... 2n) of those input standing at their 1 states. A frequent use is in addresses for memories.
Reversed in direction, the binary grouping symbol can be used with outputs. The concept is analogous
to that for the inputs and the weighted outputs will indicate the internal number assumed to be developed
within the circuit.
4-7
Table 3. Symbols Inside the Outline
Bithreshold input (input with hysteresis)
N-P-N open-collector or similar output that can supply a relatively lowimpedance L level when not turned off. Requires external
pUll-Up. Capable of positive-logic wired-AND connection.
Pass'ive-pull-up output is similar to N-P-N open-collector output but is
supplemented with a built-in passive pull-up.
+
f-
N-P-N open-emitter or similar output that can supply a relatively lowimpedance H level when not turned off. Requires external pull-down.
Capable of positive-logic wired-OR connection.
Passive-pull-down output is similar to N-P-N open-emitter output but is
supplemented with a built-in passive pull-down.
v~
3-state output
[>~
Output with more than usual output capability (symbol is oriented in the direction of signal flow).
-i EN
Enable input
When at its internal 1-state, all outputs are enabled.
When at its internal O-state, open-collector, open-emitter outputs, and three-state outputs at
external high-impedance state, and all other outputs (i.e., totem-poles) are at the internal O-state.
J, K, R, S, T
Usual meanings associated with flip-flops (e.g., R
Data input to a storage element equivalent to:
Shift right (left) inputs, m = 1, 2, 3, etc. If m
= reset,
T
= toggle)
-,-j
Lq SR
1, it is usually not shown.
Binary grouping. m is highest power of 2. Produces a number equal to the sum of the weights
of the active inputs
Input line grouping ... indicates two or more terminals used to implement a single logic input.
e.g., differential inputs.
3.4
Combinations of Outlines and Internal Connections
When a circuit has one or more inputs that are common to more than one element of the circuit, the
common-control block may be used. This is the only distinctively shaped outline used in the lEe system.
Figure 2 shows that unless otherwise qualified by dependency notation, an input to the common-control
block is an input to each of the elements below the common-control block.
COMMON·CONTROL BLOCK
a
a
b--I---I
b
I--I
C __
C
d
d----i
Figure 2. Common-Control Block
4-8
The outlines of elements may be embedded within one another or abutted to form complex elements,
in which case the following rules apply. There is no logic connection between elements when the line
common to their outlines is in the direction of signal flow. There is at least one logic connection when
the line common to two outlines is perpendicular to the direction of signal flow. If no indications are
shown on either side of the common line, it is assumed that there is only one logic connection. If more
than one internal connection exists between adjacent elements, the number of connections will be clarified
by the use of one or more of the internal connection symbols from Table 4 and/or appropriate qualifying
symbols or dependency notation.
Table 4. Symbols for Internal Connections
--~-E--
---A---
Internal connection. 1 state on left produces 1 state on right.
___'t__ _
Negated internal connection. 1 state on left produces 0 state on right.
----y.;::;;:-
Dynamic internal connection. Transition from 0 to 1 on left produces transitory 1 state on
___ 1-__
right.
--r+:,:-
Dynamic internal connection. Transition from 1 to 0 on left produces transitory 1 state on
--~--
right.
Table 4 shows symbols that are used to represent internal connection with specific characteristics. The
first is a simple noninverting connection, the second is inverting, the third is dynamic. As with this symbol
and an external input line, the transition from 0 to 1 on the left produces a momentary l-state on the
right. The fourth symbol is similar except that the active transition on the left is from 1 to O.
Only logic states, not levels, exist inside symbols. The negation symbol (
direct polarity indication (
) is used externally.
) is used internally even when
In an array of elements, if the same general qualifying symbol and the same qualifying symbols associated
with inputs and outputs would appear inside each of the elements of the array, these qualifying symbols
are usually shown only in the first element. This is done to reduce clutter and to save time in recognition.
Similarly, large identical elements that are subdivided into smaller elements may each be represented
by an unsubdivided outline. The SN75163B symbol (see 6.5) illustrates this principle.
4
Dependency Notation
Some readers will find it more to their liking to skip this section and proceed to the explanation of the
symbols for a few actual devices in 6.0. Reference will be made there to various parts of this section
as it is needed. If this procedure is followed, it is recommended that 5.0 be read after 6.0 and then
all of 4.0 be reread.
4.1
General Explanation
Dependency notation is the powerful tool that sets the lEe symbols apart from previous systems and
makes compact, meaningful, symbols possible. It provides the means of denoting the relationship
between inputs, outputs, or inputs and outputs without actually showing all the elements and
interconnections involved. The information provided by dependency notation supplements that provided
by the qualifying symbols for an element's function.
In the convention for the dependency notation, use will be made of the terms "affecting" and "affected."
In cases where it is not evident which inputs must be considered as being the affecting or the affected
ones (e.g., if they stand in an AND relationship), the choice may be made in any convenient way.
4-9
So far, eleven types of dependency have been defined but only the eight used in this book are explained.
They are listed below in the order in which they are presented a/1ld are summarized in Table 5 following
4.10.2.
Section
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9
4.10
4.2
Dependency Type or Other Subject
G,AND
General Rules for Dependency Notation
V,OR
N, Negate (Exclusive"OR)
Z, Interconnection
X, Transmission
C, Control
EN, Enable
M, Mode
G (AND) Dependency
A common relationship between two signals il, to have them ANDed together. This has traditionally
been shown by explicitly drawing an AND gate with the signals connected to the inputs of the gate.
The 1972 IEC publication and the 1973 IEEE/ANSI standard showed several ways to show this AND
relationship using dependency notation. While ten other forms of dependency have since been defined,
the ways to invoke AND dependency are now reduced to one.
In Figure 3 input b is AN Oed with input a and the complement of b is ANDed with c. The letter G has
been chosen to iridicate AND relationships and is placed at input b, inside the symbol. A number
considered appropriate by the symbol designer (1 has been used here) is placed after the letter G and
also at each affected input. Note the bar over the 1 at input c.
a
b
c
=t--
=~--
1
~1
1
c~
=
Figure 3. G Dependency Between Inputs
In Figure 4, output b affects input a with an AND relationship. The lower example shows that it is the
internal logic state of b, unaffected by the negation sign, that is ANDed. Figure 5 shows input a to be
ANDed with a dynamic input b.
·-E~]--b
Figure 4. G Dependency Between Outputs and Inputs
.--f&f--
b---t{ __
Figure 5. G Dependency with a Dynamic Input
4-10
The rules for G dependency can be summarized thus:
When a Gm input or output (m is a number) stands at its internal 1 state, all inputs and outputs affected
by Gm stand at their normally defined internal logic states. When the Gm input or output stands at
its 0 state, all inputs and outputs a~fected by Gm stand at their internal 0 states.
4.3
Conventions for the Application of Dependency Notation in General
The rules for applying dependency relationships in general follow the same pattern as was illustrated
for G dependency.
Application of dependency notation is accomplished by:
1.
2.
Labeling the input (or output) affecting other inputs or outputs with the letter symbol indicating
the relationship involved (e.g., G for AND) followed by an identifying number, appropriately
chosen, and
Labeling each input or output affected by that affecting input (or output) with that same number.
If it is the complement of the internal logic state of the affecting input or output that does the affecting,
then a bar is placed over the identifying numbers at the affected inputs or outputs (Figure 3).
If two affecting inputs or outputs have the same letter and same identifying number, they stand in an
OR relationship to each other (Figure 6).
a~G1-
b
c
a~1
G1
b
1
c
&
Figure 6. ORed Affecting Inputs
If the affected input or output requires a label to denote its function (e.g., "0"), this label will be prefixed
by the identifying number of the affecting input (Figure 12).
If an input or output is affected by more than one affecting input, the identifying numbers of each of
the affecting inputs will appear in the label of the affected one, separated by commas. The normal reading
order of these numbers is the same as the sequence of the affecting relationships (Figure 12).
4.4
V (OR) Dependency
The symbol denoting OR dependency is the letter V (Figure 7).
When a Vm input or output stands at its internal 1 state, all inputs and outputs affected by Vm stand
at their internal 1 states. When the Vm input or output stands at its internal 0 state, all inputs and outputs
affected by Vm stand at their normally defined internal logic states.
a-f~3-b
==
[=l-R b
.~
[~h
a~b
1=: - 3fi: - ~:
Figure 7. V (OR) Dependency
4-11
4.5
N (Negate) (Exclusive-OR) Dependency
The symbol denoting negate dependency is the letter N (Figure 8). Each input or output affected by
an Nm input or output stands in an Exclusive-OR relationship with the Nm input or output.
When an Nm input or output stands at its internal 1 state, the internal logic state of each input and
each output affected by Nm is the complement of what it would otherwise be. When an Nm input or
output stands at its internal 0 state, all inputs and outputs affected by Nm stand at their normally defined
internal logic states.
If a = 0, then c = b
Ita = 1, then c = b
Figure 8, N (Negate) (Exclusive-OR) Dependency
4.6
Z (Interconnection) Dependency
The symbol denoting interconnection dependency is the letter Z.
Interconnection dependency is used to indicate the existence of internal logic connections between inputs,
outputs, internal inputs, and/or internal outputs.
The internal logic state of an input or output affected by a Zm input or output will be the same as the
internal logic state of the Zm input or output, unless modified by additional dependency notation (Figure 9).
where
where
a---1G 1 ;Lc
----l!z1. J
b
Figure 9. Z (Interconnection) Dependency
4-12
4.7
X (Transmission) Dependency
The symbol denoting transmission dependency is the letter X.
Transmission dependency is used to indicate controlled bidirectional connections between affected
input/output ports (Figure 10).
When an Xm input or output stands at its internal 1 state, all input-output ports affected by this Xm
input or output are bidirectionally connected together and stand at the same internal logic state or analog
signal level. When an Xm input or output stands at its internal 0 state, the connection associated with
this set of dependency notation does not exist.
If a = 1, there is a bidirectional
connection between band c.
If a = 0, there is a bidirectional
connection between c and d.
Figure 10. X (Transmission) Dependency
Although the transmission paths represented by X dependency are inherently bidirectional, use is not
always made of this property. This is analogous to a piece of wire, which may be constrained to carry
current in only one direction. If this is the case in a particular application, then the directional arrows
shown in Figures 10 and 11 would be omitted.
#
#
n
MUXDMUX
O} X0
1
3
0
0/1/2/3
1
2
3
n
n
n
n
Figure 11. Analog Data Selector (Multiplexer/Demultiplexer)
4.8
C (Control) Dependency
The symbol denoting control dependency is the letter C.
Control inputs are usually used to enable or disable the data (0, J, K, R, or S) inputs of storage elements.
They may take on their internal 1 states (be active) either statically or dynamically. In the latter case
the dynamic input symbol is used as shown in the second example of Figure 12.
When a Cm input or output stands at its internal 1 state, the inputs affected by Cm have their normally
defined effect on the function of the element, i.e., these inputs are enabled. When a Cm input or output
stands at its internal 0 state, the inputs affected by Cm are disabled and have no effect on the function
of the element.
4-13
a-fc-;-
b-t D
a--t-~1
b-eD
al;b
c
==
C2
1~
_a.'
a~G7
b
1C2 = b
c
2£.
C
&
s-
& R
_
/
Note AND relationship of a and b
Figure 12. C (Control) Dependency
4.9
EN (Enable) Dependency
The symbol denoting enable dependency is the combination of letters EN.
An ENm input has the same effect on outputs as an EN input, see 3.3, but it affects only those outputs
labeled with the identifying number m. It also affects those inputs labeled with the identifying number
m. By contrast, an EN input affects all outputs and no inputs. The effect of an ENm input on an affected
input is identical to that of a em input (Figure 13).
b
1V
c
a _~-----fEN1
e
If a = O. input b and output c are disabled and e = d
If a =1. output d is disabled and e =c
d
Figure 13. 'EN (Enable) Dependency
When an ENm input stands at its internal 1 state, the inputs affected by ENm have their normally defined
effect on the function of the element and the outputs affected by this input stand at their normally defined
internal logic states, i.e., these inputs and outputs are enabled.
When an ENm input stands at its internal () state, the inputs affected by ENm are disabled and have
no effect on the function of the element, and the outputs affected by ENm are also disabled. Opencollector outputs are turned off, three-state outputs stand at their high-impedance state, and all other
outputs (e.g., totem-pole outputs) stand at their internal 0 states.
4.10
M (MODE) Dependency
The symbol denoting mode dependency is the letter M.
Mode dependency is used to indicate that the effects of particular inputs and outputs of an element
depend on the mode in which the element is operating.
If an input or output has the same effect in different modes of operation, the identifying numbers of
the relevant affecting Mm inputs will appear in the label of that affected input or output between
parentheses and separated by soiidi, e.g., (li2jCT=O 55 "iCT=O/2CT=O where 1 and 2 refer to Ml
and M2.
4-14
4.10.1 M Dependency Affecting Inputs
M dependency affects inputs the same as C dependency. When an Mm input or Mm output stands at
its internal 1 state, the inputs affected by this Mm input or Mm output have their normally defined effect
on the function of the element, i.e., the inputs are enabled.
When an Mm input or Mm output stands at its internal 0 state, the inputs affected by this Mm input
or Mm output have no effect on the function of the element. When an affected input has several sets
of labels separated by solidi (e.g., C4/2-/3 +), any set in which the identifying number of the Mm input
or Mm output appears has no effect and is to be ignored. This represents disabling of some of the functions
of a multifunction input.
The circuit in Figure 14 has two inputs, band c, that control which one of four modes (0, 1, 2, or 3)
will exist at any time. Inputs d, e, and fare D inputs subject to dynamic control (clocking) by the a
input. The numbers 1 and 2 are in the series chosen to indicate the modes so inputs e and f are only
enabled in mode 1 (for parallel loading) and input d is only enabled in mode 2 (for serial loading). Note
that input a has three functions. It is the clock for entering data. In mode 2, it causes right shifting
of data, which means a shift away from the control block. In mode 3, it causes the contents of the
register to be incremented by one count.
Note that all operations are synchronous.
In MODE 0 (b = O. c = 01. the outputs
remain at their existing states as none
of the inputs has an effect.
b
c
In MODE 1 (b = 1. c = 01. parallel loading
takes place thru inputs e and f.
d
e
1,40
In MODE 2 (b = O. c = 11. shifting down
and serial loading thru input d take place.
In MODE 3 (b = c = 11. counting up by
increment of 1 per clock pulse takes place.
Figure 14. M (Mode) Dependency Affecting Inputs
4.10.2 M Dependency Affecting Outputs
When an Mm input or Mm output stands at its internal 1 state, the affected outputs stand at their normally
defined internal logic states, i.e., the outputs are enabled.
When an Mm input or Mm output stands at its internal 0 state, at each affected output any set of labels
containing the identifying number of that Mm input or Mm output has no effect and is to be ignored.
When an output has several different sets of labels separated by solidi (e.g., 2,4/3,5), only those sets
in which the identifying number of this Mm input or Mm output appears are to be ignored.
Figure 1 5 shows a symbol for a device whose output
can behave like either a 3-state output or an opencollector output depending on the signal applied to
input a. Mode 1 exists when input a stands at its
internal 1 state and, in that case, the three-state
symbol applies and the open-element symbol has no
effect. When a = 0, mode 1 does not exist so the
three-state symbol has no effect and the openelement symbol applies.
C>
M1
b
c
EN
1
'\l/10
d
Figure 15. Type of Output
Determined by Mode
4-15
Table 5. Summary of Dependency Notation
TYPE OF
LETTER
AFFECTING INPUT
DEPENDENCY
SYMBOL*
AT ITS 1-STATE
Control
AFFECTING INPUT
AT ITS O-STATE
Permits action
Prevents action
EN
Permits action
o outputs turned off
AND
G
Permits action
Imposes 0 state
Mode
M
Permits action (mode selected)
Prevents action (mode not selected)
C
Prevents action of inputs
Enable
\l outputs at external high impedance
Other outputs at internal 0 state
Negate (Ex-NOR)
N
Complements state
No effect
OR
Transmission
V
Imposes 1 state
Permits action
X
Bidirectional connection exists
Bidirectional connection does not exist
Interconnection
Z
Imposes 1 stat!!
Imposes 0 state
• These letter symbols appear at the AFFECTING input (or output) and are followed by a number. Each input (or output)
AFFECTED by that input is labeled with that same number.
5
Bistable Elements
The dynamic input symbol and dependency notation provide the tools to identify different types of bistable
elements and make synchronous and asynchronous inputs easily recognizable (Figure 16).
c~
0---Uc~
0---U-
Ri}C
C1
o
10
S
S
FillC
C1
o
10
S
S
Transparent latch with true and complement outputs
Edge-triggered flip-flop. 0 input enabled momentarily
as C goes from 1 to 0
Edge-triggered flip-flop. 0 input enabled momentarily
as C goes from low to high_ Asynchronous active-low
set and reset inputs. Active-low output
Same flip-flop shown in positive logic
Figure 16. Latches and Flip-Flops
Transparent latches have a level-operated control input. The D input is active as long as the C input
is at its internal 1 state. The outputs respond immediately. Edge-triggered elements accept data from
D, J, K, R, or 5 inputs on the active transition of C.
Notice that synchronous inputs can be readily recognized by their dependency labels (a number preceding
the functional label, 1 D in these examples) compared to the asynchronous inputs (5 and R), which are
not dependent on the C inputs. Of course if the set and reset inputs were dependent on the C inputs,
their labels would be similarly modified le.g., 15, 1 Ri.
4-16
6
Examples of Actual Device Symbols
The symbols explained in this section include some of the most complex in this book. These were chosen,
not to discourage the reader, but to illustrate the amount of information that can be conveyed. It is
likely that if one reads these explanations and follows them reasonably well, most of the other symbols
will seem simple indeed. The explanations are intended to be independent of each other so they may
seem somewhat repetitious. However each illustrates new principles. They are arranged more or less
in the order of complexity.
6.1
SN75437 A Quadruple Peripheral Driver
There are four identical sections. The symbology is
complete for the first element; the absence of any
symbology for the other elements indicates they are
identical. The top two elements share a common
output clamp, pin 2. This is shown to be a non logic
connection by the superimposed X on the line. The
function for this type of connection is indicated
briefly and not necessarily exactly by a small amount
of text within the symbol. The bottom two elements
likewise share a common clamp.
Each element is shown to be an inverter with
amplification (indicated by 1». Taking TTL as a
reference, this means that either the input is
sensitive to lower level signals, or the output has
greater drive capability than usual. The latter applies
in this case. The output is shown by Q to be open
collector.
All the outputs share a common EN input, pin 14. See Figure 2 for an explanation of the common control
block. When EN = 0 (pin 14 is low), the outputs, being open-collector types, are turned off and would
be pulled high by an external pullup resistor.
6.2
SN75128 8-Channel Line Receiver
1S
2S
1A
2A
3A
4A
SA
6A
7A
SA
1Y
There are eight identical sections. The symbology is
complete for the first element; the absence of any
symbology for the next three elements indicates they
are identical. Likewise the symbology is complete for
the fifth element; the absence of any symbology for
the next three elements indicates they are identical
to the fifth.
Each element is shown to be an inverter with
amplification (indicated by 1». Taking TTL as a
reference, this means that either the input is
sensitive to lower level signals, or the output has
greater drive capability than usual. The former
applies in this case. Since neither the symbol for
open-collector ( Q ) or 3-state ( \1 ) outputs is
shown, the outputs are of the totem-pole type.
The top four outputs are shown to be affected by affecting input number 1, which is EN 1, meaning
they will be enabled if EN1 = 1 (pin 1 is high). See 4.9 for an explanation of EN dependency. If pin
1 is low, EN1 = 0 and the affected outputs will go to their inactive (high) levels. Similarly, the lower
four outputs are controlled by pin 11.
4-17
6.3
SN75122 Triple Line Receivers
There are two identical sections. The symbology is
complete for the first section; the absence of any
symbology for the next section indicates it is
identical. Likewise the symbology is complete for the
third section, which is similar, but not identical, to
the first and second.
1R
1S
lA
1B
The top section may be considered to be an OR
element (~1) with two embedded ANDs (&), one of
which has an active-low amplified input ( I> ) with
hysteresis ( .D' ), pin 14. This is ANDed with pin 1 5
and the result is ORed with the AND of pins 1 and
2. The output of the OR, pin 13, is active-low.
2R
2S
2A
2B
3R
The third section is identical to the first except that
pin 12 has no input ANDed with it. Since neither the
symbol for open-collector ( Q ) or 3-state ( 'V )
outputs is shown, the outputs are of the totem-pole
type.
3S
3A
6.4
SN75113 Differential Line Drivers with Split 3-State Outputs
1C
171
There are two similar elements in the array. The first
is a 2-input AND element (indicated by &); the
second has only a single input. Both elements are
shown to have special amplification (indicated
by 1». Taking TTL as a reference, this means that
either the input is sensitive to lower level signals, or
the output has greater drive capability than usual.
The latter applies in this case.
&
EN 1
CC
2C
lYP
1YS
1ZP
1ZS
Each element has four outputs. Pins 4 and 3 are a
pair consisting of one open-emitter output ( ~ ) and
one open-collector output ( Q ). Relative to the AND
1B
function, both are active high. Pins 1 and 2 are a
similar pair but relative to the AND function, both are
2YP
active low. All outputs of a single, unsubdivided
2YS
element always have identical internal logic states
2ZP
2ZS
determined by the function of the element except
when otherwise indicated by an associated symbol
or label inside the element. Here there is no such
contrary indication. All four outputs are shown to be
affected by affecting input number 1·, which is EN1,
meaning they will all be enabled if EN1 = 1. See 4.9 for an explanation of EN dependency. If EN1 = 0,
all the affected outputs will be turned off. EN1 is the output of an AND gate (indicated by &) whose
active-high inputs are pins 7 and 9. Both pins 7 and 9 must be high to enable the outputs of the top
element. Assuming they are enabled and that pins 5 and 6 are both high, the internal state of all four
outputs will be a 1 . Pins 4 and 3 will both be high, pins 1 and 2 will both be low. The part is designed
so that pins 3 and 4 may be connected together creating an active-high 3-state output. Likewise pins
1 and 2 may be connected together to create an active-low 3-state output.
1A
All that has been said about the first element regarding its outputs and their enable inputs also applies
to the second element. Pins 9 and 10 are the enable inputs in this case.
4--18
6.5
SN75163B Octal General-Purpose Interface Bus Transceiver
There are eight 110 ports on each side, pins 2 through
9 and 12 through 19. There are eight identical
channels. The symbology is complete for the first
channel; the absence of any symbology for the other
channels indicates they are identical. The eight
bidirectional channels each have amplification from
left to right, that is, the outputs on the right have
increased drive capability (indicated by 1>1. and the
inputs on the right all have hysteresis (indicated
by.O').
84
The outputs on the left are shown to be 3-state
outputs by the ~. They are also shown to be
affected by affecting input number 4, which is EN4,
meaning they will be enabled if EN4 = 1 (pin 1 is
low). See 4.9 for an explanation of EN dependency.
If EN4 = 0 (pin 1 is high), the affected outputs will
go to their high-impedance (off) states.
The labeling at pin 2, which applies to all the outputs on the right, is unusual because the outputs
themselves have an unusual feature. The label includes both the symbol for a 3-state output ( ~ ) and
for an open-collector output (Q), separated by a slash indicating that these are alternatives.
The symbol for the 3-state output is shown to be affected by affecting input number 1, which is M 1,
meaning the \llabel is valid when M1 = 1 (pin 11 is high), but is to be ignored when M1 = 0 (pin
11 is low). See 4.10 for an explanation of M (mode) dependency. Likewise the symbol for the opencollector output is shown to be affected by affecting input number 2, which is M2, meaning the ~
label is valid when M2 = 1 (pin 11 is low), but is to be ignored when M2 = 0 (pin 11 is high). These
labels are enclosed in parentheses (used as in algebra); the numeral 3 indicates that in either case the
output is affected by EN3. Thus the right-hand outputs will be off if pin 1 is low. It can now be seen
that pin 1 is the direction control and pin 11 is used to determine whether the outputs are of the 3-state
or open-collector variety.
4-19
6.6
SN75161B Octal IEEE Std 488 Interface Bus Transceiver
DC (11)
TE
(1)
EN1/G4
EN2/G5
5 ;;'1
ATN
EOI
There are eight I/O ports on each side, pins 2 through
,9 and 12 through 19. Pin 13 is not only an I/O port;
the line running into the common-control block (see
Figure 2) indicates that it also has control functions.
Pins 1 and 11 are also controls. The eight
bidirectional channels each have amplification from
left to right, that is, the outputs on the right have
increased drive capability (indicated by C», and the
inputs on the right all have hysteresis (indicated
by.D1. All of the outputs are shown to be of the
3-state type by the 'V symbol except for the outputs
at pins 9, 4, and 5, which are shown to have passive
pull ups by the ~ symbol.
Starting with a typical I/O port, pin 18, the output
portion is identified by an arrow indicating rig'ht-toleft signal flow and the three-state output symbol
NDAC
( 'V). This output is shown to be affected by
affecting input number 1, which is EN 1, meaning it
NRFD
will be enabled as an output if EN1 = 1 (pin 11 is
high). See 4.9 for an explanation of EN dependency.
If pin 11 is low, EN 1 = 0 and the output at pin 18
will be in its high-impedance (off) state. This also applies to the 3-state outputs at pins 13 and 19 and
to the passive-pull up output at pin 9. On the other hand, the outputs at pins 8, 2, 3, and 12 all are
affected by the complement of EN1. This is indicated by the bar over the 1 at each of those outputs.
They are enabled only when pin 11 is low. Thus one function of pin 11 is to serve as direction control
for the first, third, fourth, and fifth channels.
DAV
Similarly it can be seen that pin 1 serves as direction control for the sixth, seventh, and eighth channels.
If pin 1 is high, transmission will be from left to right in the sixth channel, right to left in the seventh
and eighth. These transmissions are reversed if pin 1 is low.
The direction control for the second channel, EN3, is more complex. EN3 is the output of an OR (~ 1)
function. One of the inputs to this OR is the active-high signal on pin 13. This signal is shown to be
affected at the input to the OR gate by affecting input number 5, which is G5, meaning that pin 13
is ANDed with pin 1 before entering the OR gate. See 4.2 for an explanation of G (AND) dependency.
The other input to the OR is the active-low signal on pin 13. This signal is ANDed with the complement
of pin 11 before entering the OR gate. This is indicated by the G4 at pin 1 and the 4 with a bar over
it at pin 13. Thus for EN3 to stand at the 1 state, which would enable transmission from pin 14 to pin 7,
both pins 13 and 1 must be high or both pins 13 and 11 must be low.
4-20
6.7
SN75500E AC Plasma Display Driver with CMOS-Compatible Inputs
CMOS/PLASMA DISP
141 101
Z2
Z3
Z4
ZS
·Z6
Z7
8.11
1.12
8.12
1.13
8.13
1.14
1111 108
1121 201
t>
t>
1191 208
1291 301
t>
t>
1221 308
1371 401
t>
t>
The heart of this device and its symbol is an 8-bit
shift register. It has a single D input, pin 2, which
is shown to be affected by affecting input number 9,
which is C9, meaning it will be enabled if C9 = 1.
See 4.8 for an explanation of C dependency and 5.0
for a discussion of bistable elements. Since the C
input is dynamic, the storage elements are edgetriggered flip-flops. While C9 = 1, which in this case
will occur on the transition of pin 3 from low to high,
the state of the D input will be stored. Pin 2 is shown
to be active low so to store a 1, pin 2 must be low.
In addition to controlling the D input, pin 3 is shown
by /- to have an additional function. As pin 3 goes
from low to high, data stored in the shift register is
shifted one position. The right-pointing arrow means
that the data is shifted away from the control block
(down).
On the right side of the symbol an abbreviation
technique has been used that is practical only when
the internal labels and the pin numbers are both consecutive. Thus it should be clear that the input of
the element whose output is pin 5 is affected by affecting input number 2, just as the input of the element
whose output is pin 4 is affected by affecting input number 1. Affecting inputs 1 through 8 are Z inputs
(Zl through Z8), which means their signals are tranferred directly to the output elements. See 4.6 for
an explanation of Z dependency.
Z8
8.14
1301 408
t>
The inputs of the 32 implicitly shown output elements are also shown to be affected by affecting inputs
numbers 11, 12, 13, and 14 in four blocks of eight each. These inputs will be found in the common
control block preceded by a letter G and a brace. The brace is called the binary grouping symbol. It
is equivalent to a decoder with outputs in this case driving four G inputs (G11, G12, G13, and G14).
The weights of the inputs to the coder are shown to be 20 and 21 for pins 1 and 39, respectively. The
decoder has four outputs corresponding to the four possible sums of the weights of the activated decoder
inputs. If pins 1 and 39 are both low, the sum of the weights = 0 and G11 = 1. If pin 1 is low while
pin 39 is high, the sum = 2 and G13 = 1 and so forth. G indicates AND dependency, see 4.2. Only
one of the four affecting G inputs at a time can take on the 1 state. The block of eight output elements
affected by that G input are enabled; the 0 state is imposed on the other 24 output elements and externally
those output pins are low.
I
Because of their high-current, high-voltage characteristics, the outputs are labeled with the amplification
symbol!> . All the outputs share a common EN input, pin 38. See Figure 2 for an explanation of the
common control block. When EN = 0 (pin 38 is high\. the outputs take on their internal 0 states. Being
active high, that means they are forced low.
4-21
6.8
SN75551 Electroluminescent Row Driver with CMOS-Compatible Inputs
CMOS/EL DISP
SUBSTRATE 1211
COMMON
STROBE 1231
[0.
SOURCE SUPPLY[
2.3
2.3
2.3
2.3
C>
C>
The heart of this device and its symbol is a
32-bit shift register. It has a single D input,
pin 24, which is shown to be affected by
affecting input number 1, which ,is C1,
meaning it will be enabled if C 1 = 1. See 4.8
for an explanation of C dependency and 5.0
for a discussion of bistable elements. Since
the C input is dynamic, the storage elements
are edge-triggered flip-flops. While C1 = 1,
which in this case will occur on the transition
of pin 20 from high to low, the state of the
D input will be stored. Pin 24 is shown to be
active high so to store a 1, pin 24 must be
high.
C>
C>
In addition to controlling the D input, pin 20
is shown by {-+ to have an additional function.
As pin 20 goes from high to low, data stored
in the shift register is shifted one position. The
right-pointing arrow means that the data is shifted away from the control block (down). The internal
inputs of the output buffers are all shown to be affected by affecting inputs 2 and 3. Affecting input
2 is G2, meaning that pin 19 is ANDed with each of the internal register outputs, which are the buffer
inputs. If pin 19 is high, the affected buffer inputs are enabled. If pin 19 is low, the 0 state is imposed
on the affected buffer inputs. See 4.2 for an explanation of G (AND) dependency. Affecting input 3
is V3, meaning that pin 23 (active low) is ORed with each of the internal register outputs. If pin 23
is high, V3 = 0 and the affected buffer inputs are enabled. If pin 23 is low, V3 = 1 and the 1 state
is imposed on the affected buffer inputs. See 4.4 for an explanation of V (OR) dependency. The effect
of V3 is taken into account after that of G2 because of the order in Which the labels appear. This means
that the imposition of the 1 state on the internal buffer inputs by pin 23 would take precedence over
the imposition of the 0 state by pin 19 in case both inputs were active. Pin 18 is shown to be an output
directly from the thirty-second stage of the shift register. Pins 19 and 23 do not affect this output.
2.3
An abbreviation technique has been used for the shift register elements and associated the output lines.
This technique is practical only when the pin numbers and pin names are both consecutive.
The symbol 0 designates an n-p-n open-collector or similar output. In this device, the outputs are actually
open-drain n-channel field-effect transistors. Instead of being grounded, the sources of these transistors
are all connected to pin 21. This pin is used as an input to control the output voltage.
('
4-22
5-1
»
"C
"C
-- .
...o_.
()
S»
::s
en
5-2
Contents
Section 5.
1.
Introduction ........................................................................................................................... 5-7
1.1.
1.2.
1.3.
1.4.
1.5.
Data Transmission .................................................................................................. 5-7
1.1.1.
The Need for Transmission Standards ................................................... 5-8
1.1.2.
Speda list Technologies ......................................................................... 5-8
1.1.3.
About This Section ................................................................................ 5-9
Overview of the Interface Standards ..................................................................... 5-10
1.2.1.
EIAffIA-232 ....................................................................................... 5-10
1.2.2.
RS-485 ................................................................................................ 5-11
1.2.3.
Small Computer Systems Interface (SCSI) .......................................... 5-11
1.2.4.
Summary of ETA Interface Standards .................................................. 5-12
System Influences ................................................................................................ 5-13
1.3.1.
Signal Attenuation ............................................................................... 5-13
1.3.2.
Signal Distortion ................................................................................. 5-15
1.3.3.
Noise ................................................................................................... 5-16
Eye patterns .......................................................................................................... 5-16
1.4.1.
Setting up the eye pattern .................................................................... 5-17
1.4.2.
Taking Measurements from Eye Pattems ............................................. 5-17
Line Termination .................................................................................................. 5-19
1.5.1.
Transmission Line Test ....................................................................... 5-19
5-3
1.6.
1.7.
1.5.2.
Transmission Line Considerations & Effects ....................................... 5-19
1.5.3.
Transmission Line Retlections ............................................................ 5-20
1.5.4.
Using Eye Patterns to Determine Zo ................................................... 5-21
Noise Intluences ................................................................................................... 5-21
1.6.1.
Single Ended Line Considerations ....................................................... 5-21
1.6.2.
Differential Line Cons.iderations ......................................................... 5-23
Network Topology ............................................................................................... 5-24
1.7.1.
2.
Interface Circuits for EIA-232 ............................................................................................ 5-29
2.1.
General Infonnation ............................................................................................. 5-29
2.1.1.
Reliability Data ................................................................................... 5-29
2.2.
EIA!TIA-232-E Industry Standard for Data Transmission .................................... 5-30
2.3.
EIA-232 Specification .......................................................................................... 5-31
2.4.
2.5.
2.3:1.
EIA-232-E Electrical Specifications .................................................... 5-32
2.3.2.
Calculating maximum line length ........................................................ 5-35
2.3.3.
The DB9S Connector .......................................................................... 5-36
SN75C185: Optimised PC Iuterface ..................................................................... 5-38
2.4.1.
Low Power as Well .................... :........................................................ 5-39
2.4.2.
SN75C185; Power Considerations ....................................................... .5-40
2.4.3.
Interface Power Consumption Calculations ......................................... 5-40
2.4.4.
On Chip Slew Rate Limiting ............................................................... 5-44
2.4.5.
Internal Noise Filtering ....................................................................... 5-44
SN75LBC187; Optimised for Portables ................................................................ 5-46
2.5.1.
SN75LBCI87; 116 kbps operation ...................................................... 5-48
2.5.2.
Conformance to EIA-562 .................................................................... 5-49
2.6.
SN75LV4735; 3 Volt EIA-232 PC Interface ......................................................... 5-49
2.7.
ACEs (UARTs) From Texas Instruments ............................................................. 5-50
2.8.
5-4
How Short is Short? ........................................................................... 5-25
2.7.1.
The FIFO (First-In-First Out) .............................................................. 5-51
2.7.2.
Forward-Looking Perfonnance With Backward Compatibility ............ 5-52
2.7.3.
Interfacing Between the TL16C550B and the SN75CI85 .................... 5-53
EIA-232 Products SUlnmary ................................................................................. 5-55
2.9.
3.
Interface Circuits for RS-485 .............................................................................................. 5-58
3.1.
The Need for Balanced Transmission Line Standards ........................................... 5-58
3.1.1.
Application Areas ................................................................................ 5-58
3.1.2.
EIA RS-485 ......................................................................................... 5-59
3.1.3.
RS-485 Driver features ........................................................................ 5-60
3.1.4.
RS-485 Receiver features .................................................................... 5-60
3.2.
Process Control Design Example .......................................................................... 5-60
3.3.
Line Loading ........................................................................................................ 5-61
,3.4.
4.
EIA-232 Selection Guide ...................................................................................... 5-56
3.3.1.
Signal Attenuation ............................................................................... 5-64
3.3.2.
Signal Distortion Vs Data Rate ............................................................ 5-65
3.3.3.
Fault Protection and Fail Safe Operation ............................................. 5-65
3.3.4.
Galvanic Isolation ............................................................................... 5-70
SN75LBCI76; Ultra Low Power .......................................................................... 5-73
3.4.1.
Improve MTBF ................................................................................... 5-73
3.4.2.
Full Duplex and High Speed RS-485 ................................................... 5-74
3.4.3.
RS-485 Selection Guide ...................................................................... 5-75
Interface Circuits for SCSI .....•••..•....•••.•....•••••••••••...•••••••••••.•••••....••••.•.•••••.•••••••.•••••••••••••..•• 5-78
4.1.
SCSI Overview..................................................................................................... 5-78
4.1.1.
4.2.
4.3.
4.4.
SCSI Physical Layer ............................................................................ 5-79
Single Ended SCSI ............................................................................................... 5-79
4.2.1.
Temlination of Single Ended Bus ........................................................ 5-79
4.2.2.
Signal Transitions ................................................................................ 5-79
4.2.3.
Passive and Active SCSI Termination ................................................. 5-81
4.2.4.
Current Source Tennination Using the TL2218 ................................... 5-83
4.2.5.
Power Considerations .......................................................................... 5-84
Differential SCSI .................................................................................................. 5-85
4.3.1.
SN75LBC976DL; Two Chip Differential SCSI ................................... 5-85
4.3.2.
SCSI and IPI Skew Considerations ...................................................... 5-87
4.3.3.
SN75LBC976 Channel Power Dissipation Considerations ................... 5-89
4.3.4.
Junction Temperature and Layout Considerations ................................ 5-91
Driving the 'Wired-Or' SCSI Lines with the SN75LBC976 ................................... 5-93
5-5
5. Summary and Further Information ................................................................................... 5-96
5.1.
EIA Standards ...................................................................................................... 5-96
5.2.
References ........................................................................................................... 5-96
5.3.
Texas Instruments - Completing the Picture ......................................................... 5-96
Data Transmission
1. Introduction
1.1.Data Transmission
It may seem strange that TIs 'Data transmission' products are included within the Linear seminar.
Data Transmission as part of TI's Linear Products portfolio is concerned with the standards involving
transmitting data at relatively high speeds down long line lengths, the considerations for which are
Data Transmission
lIP
SOURCE
LOAD
SIGNAL
CONDITIONING
DIGITAL
PROCESSING
OUTPUT
SECTION
DIGITAL
PROCESSING
,,, ,,,
POWER SUPPLY
Figure 5.1 • Data Transmission
5-7
1993 Linear Design Seminar
primarily of an analog more than a digital nature. Likewise the design of data transmission ICs
requires experienCed analog engineers to implement functions such as slew rate limiting, receiver
filtering and common-mode protection.
In this year's seminar we will concentrate on two verY popular transmission standards, RS-232 or as
it is now known EIAfI'IA-232-E, and the multi-point, half duplex RS-485 standard. The last section
covers the physical layer of the increasingly popular Small Computer Systems Interface Standard
(SCSI).
.
1.1.1. The Need for Transmission Standards
Data transmission standards evolved for two main reasons: From the need to transmit data reliably
over long distances, and to provide a standard interface to facilitate communication between
equipment from different suppliers. Although TfLILogic Signal levels and products can be used,
they generally lack the power handling capabilities, robus1lless and noise margins required for
reliable transmission. Indeed for backplane equipment, TIL is no longer specified for the newer high
speed standards, such as Futurebus+ which uses BTL transceivers. In general the standards
concerned with transmitting data over long distances incorporate wider voltage swings, increased
robuS1lless and higher power outputs than can be delivered using conventional 'Logic' products.
Similarly the sub-micron technologies used in the fabrication of today's logic devices cannot provide
the power handling and robUS1lless necessary for successful long distance transmission.
1.1.2. Specialist Technologies
This leads to the need for specialist ICs, and technologies, to meet the exacting requirements of these
transmission standards. The traditional technological answer has been to utilise the inherent
robus1lless afforded by bipolar technologies, however the additional need for low power consumption
and high levels of integration no longer makes this attractive. SC manufacturers are now baving to
develop their technologies to accommodate these requirements. TI has introduced its proprietary
LinBiCMOSTM technology cOmbining the robus1lless of bipolar together with the power consumption
and integration afforded by CMOS. Other manufacturers are using pure CMOS and integrating
shottky diodes to the same end. The result is very specialised and reliable products that are able to
withstand the harsh environment unique to data transmission products.
Texas Instruments has been a leading supplier of data transmission products for many years, and is
continually innovating new fields. Although the following sections are limited to the more common
interface standards, TI is actively involved in many new emerging standards and markets, for
example Futurebus+, a backplane standard with virtually no ceiling on data rate, the high speed
serial data link evolving from the P1394 committee and multiplex wiring systems such as ABUS,
CAN and VAN. The reader is advised to contact a TI representative for information on these
product areas.
With the considerable expertise in design, product definition and range of technologies Texas
Instruments is the ideal choice for supplying your data transmission product requirements.
5-8
Data Transmission
1.1.3. About This Section
This Section is split into four distinct sections eacb of which provides a practical rather than
theoretical approach to in an attempt to give the reader an insight into three popular data
transmission standards, EIAITIA-232, RS-485 and the SCSI standard. The Section is split as follows:
Data Transmission
Objective
Introduction
1. Update You on Tl's New Interface
Products.
2. Discuss Application Ideas and
Design Considerations.
-Data Transmission
-System Considerations
EIA-232
-The Standard
-Increasing the Data Rate
-PC Interface
RS-485
-The Standard
-Data Rate And Line Length
-Industrial Application
SCSI
-The Standard
- Single Ended SCSI
- Differential SCSI
Figure 5.2 • Data Transmission Agenda
1.
Introduction: An overview of the various factors that affect any data transmission system. Under
discussion is the line length versus data rate trade-off, noise sources, correct line termination and
network topology in addition to explaining the use of eye patterns as a tool to measure
transmission quality.
2.
EIA-232: A discussion of the standard with particular attention paid to the changes made in the
'E' revision. Also covered is the use of '232' at higher data rates, up to 116 kbps (kilo bits per
second) and an application focus on the popular DB9 PC interface. Particular attention is paid to
TI's new products throughout the section. The generic '232' standard will be referred to in this
book as EIA-232, where a parameter is unique to a specific revision the EIA-232 reference will
be used.
3.
RS-485: An overview of the RS-485 specification followed by a design example. We use an
industrial control application to understand the factors that need to be taken into account when
5-9
1993 Linear De§ign Seminar .
designing an RS-485 system. Highlighted throughout the section will be TI's
compliant with this standard.
ne~
products
Interface Standards
EIA-232
• Single Ended Point to
Point
• 20 kbps Data Rate
• • 15 Metres Line Length
RS-485
•
•
•
~ 10M
8.
Wide SCSI
i;;;;;;;;;;;:=: .
Differential SCSI
Single Ended
1M
(I)
1;;1ook
Differential Multi- Point
> 10 Mbps Max Data Rate
1.2 km Max Line Length
SCSI
•
•
•
-
1G
100M
a:as
1;;
C
10k
1k
100
Single Ended or Differential
10 MTps Max Data Rate
25 Metres Max Line
Length
0.1
1.0
10
100
1k
Line Length (m)
Figure 5.3 -Interface Standards
4.
SCSI: We will consider the pbysicallayer of this standard that concern both single ended and
differential transmission. For single ended transmission we will look specifically at optimising
the line termination to achieve maximum transmission rate over the 6 metre distance as specified
in the standard. The differential SCSI system increases the line length to 25 metres and uses the
RS-485 standard to acbieve this. We will look at TJ's new nine channel RS-485 transceiver
which minimises the problems caused by the 18 line wide bus as dermed by the standard.
1.2.0verview of the Interface Standards
Referring to Figure 5.3 we can see the relationship of each transmission standard wben comparing
data rate and line length.
1.2.1. EIAlTIA-232
EIA-232 or 'Recommended Standard' 232 is dermed in the ANSI (Americau National Standard
Institution) .specification as "The Interface Between Data Terminal Equipment and Data Circuit-
5-10
Data Transmission
Terminating Equipment Employing Senru Binary Data Intercbange". The standard employs a single
ended serial transmission scheme and outlines the set of rules for exchanging data between computer
equipment, originally this being a Computer Terminal (DTE) and a modem (DeE). The standard has
evolved over the years with the latest 'E' revision released in July 1991. The standard is now known
as EIAfTIA-232-E, with EIA standing for the Electronic Industries Association and TIA for the
Telecommunications Industry Association.
As with previous revisions of the standard the maximum data rate is defmed as 20 k bits per second
(kbps) although there are now a number of software applications that now push this data rate up to
116 kbps, well outside the standard. The 'C' revision defined the maximum line length as 15 metres
however this failed to comprehend the type of cable used and consequently the load capacitance on
the line driver. Both the D' and 'E' revisions addressed this by more correctly defining the line length
in terms of load capacitance. The maximum load capacitance is specified as 2500 pF that translates
using standard cables to between 15 and 20 metres. Line length and data rate are limited as the
standard employs single ended communication which is prone to external factors. For longer line
lengths and higher data rates a differential balanced line communication link is essential.
1.2.2. RS-485
RS-485 was primarily an upgrade to the EIA RS-422-A standard utilising the same signal levels but
facilitating half duplex multi-point communication. The standard is less complex than the ElA-232
standard as it only specifies the physical layer of the transmission scheme. Hardware such as the
connector is left to the user to define. The standard specifies a balanced transmission line whose
maximum line length is undefmed but is nominally 1.2 km for 24 AWG cable based on 6 dB signal
attenuation. The maximum data rate is also undefined but is specified by the relationship of signal
rise time to bit time which is influenced both by the line driver and the line length and the line
loading. In the majority of applications it is the line length that is the limiting factor on data rate due
to signal dispersion. This is discussed in later sections.
1.2.3. Small Computer Systems Interface (SCSI)
SCSI is an industry-standard interface, defined by the ANSI, for the interchange of data between
computer and computer peripherals. Standard SCSI is a byte wide parallel interface for high speed
data transfer over relatively short distances. The SCSI bus is bi-directional and is terminated at both
ends of the cable to reduce reflections. For the single ended interface the standard specifies a
maximum line length of 6 metres. The maximum data rate is not specified but at present 5 Million
Transfers per second (MTps) is achievable using active termination. This can be increased up to
10 MTps using innovative termination as we will discuss later. For longer line length applications, up
to 25 metres, the SCSI standard dermes the interface using the RS-485 standard as the physical layer.
This pushes the data rate to 10 MTps over the full 25 metres which equates to 80 Mbps. A further
development of SCSI is 'Wide' SCSI which increases the data bus to 16 bits wide. Using the
10 MTps differential interface this increases the bit rate to 160 Mbps.
p-11
1993 Linear Design Seminar
1.2.4. Sum:mary of EIA Interface Standards
5-12
Data Transmission
1.3.System Influences
Noise, distortion and attenuation are always present in data transmission systems and strictly limit
performance. We will consider each one of these in turn although there is some overlap i.e. noise can
cause distortion.
System Influences
• Signal Attenuation
• Signal Distortion
• Noise
Figure 5.4· System Influences
1.3.1. Signal Attenuation
Any data transmission over wire experiences losses and distortion due to distributed constants
present along the cable: distributed series inductance, distributed shunt capacitance, distributed series
resistance and distributed shunt conductance. Attenuation of the signal in a cable is affected by each
of the these components. The series resistance, R, is frequency dependent and is a result of the DC
resistance of the cable and the skin effect. Skin effect is a term which refers to the tendency of
electrons to travel to the surface of a conductor at higher frequencies, thereby reducing the overall
cross sectional area and increasing the resistance. The series inductance, L, represents the opposition
to change in current levels caused by the collapsing and expanding magnetic fields created due to
fluctuating current levels. The shunt capacitance, C ,is created by the two conductors in close
proximity and separated by a dielectric. As the signal frequency increases the capacitive reactance
5-13
1993 Linear Design Seminar
decreases, consequently reducing the opposition to current flow. The final component, shunt
transconductance or G, is a function of the dielecbic loss of the insulation around each conductor
w~ch allows some leakage current to pass between conductors. In modem dielecbics this is often
assumed to be negligible.
The overall effect of these disbibuted constants is called the characteristic impedance of the line, Zo,
and is expressed as:
z _
0-
Where:
R+j27tfL
G+j21tfC
m
L is henries/unit length
R is in ohms/unit length
C is in farads/unit length
G is on siemens/unit length
The current/voltage relationship of an incident wave travelling down a transmission line in the
direction of the load will be determined by this equation. Equally a reflected wave travelling from
the direction of the load will also be dependent on this relationship. We will revisit this equation
when we discuss transmission line termination in section 1.5. The signal velocity along the
transmission line and the attenuation depends upon the propagation constant '1 of the line. The
propagation constant, when separated into its real and imaginary parts, is symbolised by a + J(3
where a is known as the attenuation constant and (3 as the phase constant. a determines the rate of
attenuation and has units of nepers per unit length, and Pdetermines the phase velocity, where:
Phase velocity,
Q)
Vp=-
J3
Where Cl) is the angular velocity.
Additionally, the propagation constant,
'1 =0.+ jJ3 =.J(R+ jO>L)(G+ jmC)
In practice the attenuation of a particular cable can be determined from manufacturers data where
usually a curve of bit rate or frequency is plotted against dB, usually quoted per 100 ft or 30 metres.
The attenuation constant, p, can be converted to dBs by multiplying by 8.686.
The maximum attenuation allowable will be dependent on the system configuration but a figure of
6 dBV maximum
is a good guide. Actual curves are discussed later in the RS-485 section.
I
5-14
Data Transmission
Signal Distortion Using Eye Patterns
Formation of Eye Pattern
Clock Input
Non Return Zero Random
Code
'1' to '0' Transition
+
'0' to '1' Transition
x
Eye Pattern
=
Driver Input
~
x
><
=
K
Receiver Input
Figure 5.5 • Signal Distortion Using Eye Patterns
1.3.2. Signal Distortion
One of the primary causes of signal distortion is the effect known as frequency dispersion. As
discussed in 1.3.1. phase velocity and attenuation are both frequency dependent and whose effect is
to distort and delay the signal pulse. The high frequency components contained in the leading and
lagging edges of a pulse experience minimum delay but experience maximum attenuation. The pulse
top and low frequency components are subjected to increased delays. The result is that various parts
of the pulse arrive at the receiving end at different times and at differing levels causing distortion of
the original signal. It follows the longer the line length the more the bit rate must be reduced. In
many transmission systems it is this factor alone which determines the maximum signalling rate.
Once again cable manufacturers sometimes specify a bit rate versus line length curve but a better
way to check signal distortion of your system is by the use of eye patterns or eye diagrams. Indeed
cable manufacturers generate their bit rate/distance curves using eye pattern measurements. Eye
patterns allow you to visibly see and measure signal distortion as a function of data rate. See later
sections on how to implement Eye Patterns.
5-15
1993 Linear Design Seminar
1.3.3. Noise
Noise is generated from a variety of sources and can strongly influence how you implement your
data transmission system. All extraneous signals appearing at the receiving end of the transmission
circuit that are not due to the input signal are considered as noise. The two most likely sources of
noise that will affecting data transmission systems in the context of this Section are common-mode
voltages and cross talk. We will discuss both these types of noise and how the relate to the type of
transmission system in section 1.6.
NRZ Random Code Generator
cc-sv
1.
'4
: ~ ~:
.. ~ 11
:i
7
!0t-t-t--'
(T = R1'C1*1n2)
8
C1
ov
EXCLUSIVE· OR GATES = SN74HC74
Figure 5.5.1 - NRZ Random Code Generator
1.4.Eye patterns
To determine the effects of signal distortion, noise etc. on Intersymbol interference (lSI) in a data
transmission system the eye pattern is used, lSI is the effect of neighbouring pulses in a pulse train
spilling over into adjacent pulses and forces a reduction in the allowable permitted pulse rate for a
given line length in order to maintain adequate distinction between adjacent pulses. The eye pattern
is displayed on an oscilloscope with the term 'Eye' coming from the appearance of the trace on the
CRT.
5-16
Data Transmission
1.4.1. Setting up the eye pattern
The eye pattern is obtained by applying a random non return zero (NRZ) code down the transmission
line under test This represents all possible pulse combinations. The signal at the receiving end of the
line is connected to the vertical amplifier of an oscilloscope, with the 'scope triggered using the
synchronisation clock to the NRZ code generator on a separate trace. See Figure 5.5 Over anyone
unit interval the random code generator should produce a combination of signals. The resulting
signals can then be viewed on the oscilloscope over one unit interval, each unit interval should
resemble an eye, similar to Figure 5.6. For differential transmission both signals at the end of the
transmission line should be applied to separate amplifiers on the oscilloscope and then summed using
the summation facility on the oscilloscope.
Figure 5.5.1 shows a circuit to generate the NRZ code. In this case we have used it to test the RS-485
SN75176 type transceiver.
Eye Pattern Oscilloscope Trace
TRACE 1
Clock Input to Random
NRZ Code Generator
TRACE 2
Output at Receiver End
of Transmission Line
Trigger on Clock Input
For Differential Signals
use Invert and Trace Add
Function on Inverting and
Non Inverting Signals
Figure 5.6 - Eye Pattern Oscilloscope Trace
1.4.2. Taking Measurements from Eye Patterns
Before considering actual measurements the first key indicator on the performance of the
transmission system can be seen by simply looking at the eye pattern. The 'openness' of the eye is an
5-17
1993 Linear Design Seminar
indication of the 'quality' of the transmitted signal and is an indication of the noise and distortion
tolerance of the system.
Measuring Signal Transmission Quality
~,
~ Unit Interval
Receiver
Threshold ,,-==~~----=:;~~=:------
!
---f---: : : -~,~===-----L:=.=======------------
Threshold Crossing :.
Skew
"
% J'tt
I
~
- Threshold Crossing Skew X 100%
er Unit Interval
..
Design With No
More than 5% Jitter
Figure 5.7 - Measuring Signal Transmission Quality
For actual measurements the decision points of the transceiver should be superimposed upon the eye
pattern. The vertical distance between the decision points and the signal trace is an approximate
indication of the noise margin of the system. The horizontal appearance of the eye can be used to
determine the maximum jitter tolerance of the system. A good guide, and one that is used by cable
manufacturers to determine data rate versus line length curves, is to design with no more than 5%
jitter. Where % jitter is defined as the ratio of Threshold crossing Skew to unit interval as shown in
Figure 5.7. Jitter is caused by a number of factors including, signal frequency, noise and cross talk.
(Noise frequency can modulate the transmitted signal, for example 50 Hz hum or from other low
frequency sources). It should also be noted at this point the effect of threshold misalignment which
can cause severe problems with the received signal, reducing the detected pulse width considerably.
5-18
Data Transmission
I.S.Line Termination
The behaviour of the transmitted signal and the integrity of the data at the receiving end depends
upon the data rate and line length of the cable. There are two behavioural models; of a transmission
cable:
I.
Lumped parameter model (Short wire) •
H.
DIstributed parameter model (Transmission Hne)
As discussed in section 1.3.1 the distributed parameter model models the connecting circuit in terms
of distributed parameters (inductance, capacitance, resistance, conductance), rather than as an
equivalent lumped load on the line. The transmission line can be considered in terms of an infinite
number of small filter sections and as a result the transmission line is said to have a characteristic
impedance, Zoo Zo is independent of distance along the line and represents the voltage and current
relationship for an incident wave at any point as it travels along the line.
1.5.1. Transmission Line Test
Classifying as a Lumped or Distributed Parameter Model
All cables can be thought of as transmission lines; but the term, transmission line, is used with
differing meanings.
Consider a signal propagating down a simple data link comprising two wires. When the signal starts
to change at the transmitter output the effect of this change will eventually be seen at the other end
of the line. A reflection of the signal will occur, which will eventually return back to the transmitter
terminals.
If this happens before the original transmitted signal has risen to its peak value then the line will
normally be treated as a lumped parameter system rather than as a true transmission line. This is
because the line itself does not greatly influence the performance of the system.
A general rule of thumb for determining if a system should be treated as a true transmission line can
be formulated; If the rise time , tr. of the signal is much less than the round trip propagation delay,
2f.pd, of the signal from transmitter to receiver and back to transmitter, then the cable can be treated
as a transmission line and not as a lumped parameter model. A better model is given in Figure 5.8
where a safety margin is built in to the propagation delay/rise time relationship.
1.5.2. Transmission Line Considerations & Effects
When the cable is operating like a transmission line, extra loads in the form of transmitters and
receivers can be added, providing that they do not cause too great a shunting effect on the line. These
extra loads, if they are evenly distributed along the line, can be treated as an extra distributed
capacitance along the line adding to the effect of the line capacitance and inductance. This extra load
decreases the line impedance and reduces the speed of the signal along the line.
In the case of the lumped parameter model the line represents a pure fixed load to the transmitter
device. For example, the capacitance of the line will be modelled as a fixed value which effectively
5-19
1993 Linear Design SemlDar
limits the output voltage slew rate of the transmitter (assuming it can supply a finite amount of
current to the line).
To Terminate or Not to Terminate?
!III tpd
Eye Patterns
Use Eye Patterns to Determine
Correct Termination Resistance
Transition Time
Figure 5.8 - To Terminate or Not to Terminate?
1.5.3. Transmission Line Reflections
Consider a driver circuit driving the line. When the driver output voltage changes state, the driver
appears to see the effective characteristic impedance of the line, Zo. This will cause the voltage at
the output of the driver circuit to reduce as a result of the potential divider action formed by Zo and
the driver circuit output impedance, ZD'
At any point along the line the ideal source impedance will appear as Zo and the ideal load
impedance will also appear as Zoo This gives the impression that the line is being driven by a voltage
source of twice the magnitude of the line voltage.
When the si~al reaches the receiving end of the line it sees a terminating impedance equal to the
impedance (Zo) of the line that it is already travelling on. It interprets this as a continuation of the
line. The voltage on the line will not alter and the current flowing along the line will flow through
the termination resistor and baCk to the driver via either ground or the other line in the system.
Operation of the circuit as just described would result in optimum data transmission efficiency, with
little or no signal reflections. However, circuit operation in the real world is not always so perfect.
5-20
Data Transmission
If the termination impedance is dis-similar to the characteristic impedance of the line itself, the
voltage at the termination point will alter. The voltage at the termination point is dependent on the
relative size of the termination impedance to the line impedance. If the termination impedance is
bigher than the line impedance, the line voltage will increase causing a positive voltage reflection of
the signal. Wben the termination impedance is lower than the line impedance, the line voltage will
decrease leading to a negative reflection. The same effect will occur at the driver output terminals
due to impedance mismatcbes between driver and line.
Reflections at each end of the line will eventually settle and leave a constant dc voltage on the line.
The value of this voltage is equal to the ideal open circuit output voltage multiplied by the
termination impedance divided by the sum of the driver output impedance and termination
impedance.
Reflections as described can cause problems when driving lines at high frequencies. False receiver
triggering can occur and repeated signal reflections will cause signal wave distortion.
1.5.4. Using Eye Patterns to Determine Zo
Referring back to eye patterns, these can also be used to fmd the characteristic impedance of a
transmission line. Figure 5.8 shows three sets of eye patterns, Zr > Zo' Zr < Zo' and Zr =Zo, wbere
Zr is 200 n, 50 n, and 100 n, respectively. Where Zr > Zo the signal is larger with multiple traces,
while with Zr < Zo the signal is similar but much reduced in amplitude and could cause signal to
noise ratio problems at the receiver. With Zr Zo, the signal is very clear with a near perfect eye
pattern. In practice it is possible to use a variable resistance and the eye pattern to determine the
correct termination impedance for zero reflections.
=
1.6.Noise Influences
There are two main classification of transmission scheme, single ended or differential. Each are
affected by noise influences in differing ways - the next two section describe each transmission
scbeme paying particular attention to the affects of noise. Figure 5.9 details both types of
transmission scheme.
1.6.1. Single Ended Line Considerations
Single ended data transmission systems consist of a signal line on which data is sent down, and a
ground line through which the current returns. A direct result of this is that the ground line forms part
of the transmission line, which can be of benefit in some circumstances but not in others.
One of the major benefits, and most obvious, is that a single ended system is the lowest cost solution
in terms of cabling costs. In general terms it requires only half the cable of a differential system. It is
also relatively simple to install and operate.
The main disadvantage of the single ended solution is its poor noise inununity. Because the ground
wire forms part of the system, any transient voltage or shifts in voltage potential may be induced
(from nearby high frequency logic or high current power circuits), leading to signal degradation
ultimately leading to false receiver triggering. For example, a shift in the ground potential at the
5-21
1993 Linear Dt'S1gn Seminar
receiver end of the system can lead to an apparent change in the input switching threshold of the
receiver device, thus increasing susceptibility to noise.
Cross talk is also a major concern especially at high frequenCies. Cross talk is generated from bo~
capacitive and inductive coupling. Capacitive coupling tends to be more severe at higher signal
frequencies as capacitive reactance deCreases. The impedance and termination of the coupled line
Noise Influences
Single Ended Line
EMI,-",
~
.J.,.:----------------------e-:L
-=- ~ -=Differential Line
.L - - - - -
--
-:~ ~Q- -- --- --~
-V
--
Figure 5.9 - Noise Influences
determines whether the electric or the magnetic coupling is dominant If the impedance of the line is
high the capacitive pickup is large. Alternatively, if the line impedance is low, the series impedance
as seen by the induced voltage is low, allowing large induced currents to flow.
These problems will normally limit the distance and speed of reliable operation for a single ended
link.
Cross talk can be reduced by;
5-22
i.
Limiting th4,l slew-rate of signals so that they do not cause cross talk to be
induced onto other lint'S
Ii.
Limiting the line length.
Data Transmission
iii.
Shielding the signal conductor.
While the common-mode noise could be reduced by:i.
Isolating the signal ground from power conductors (e.g. keep signal grounds
separated as far as possible from power grounds).
U.
Ground wires should be as low as impedance as possible.
iii. Using star ground system configurations.
Some of these techniques are used in systems such as EIA-232 e.g. MaXimum slew rate of EIA-232
is defined as 30 V/fJS while Futurebus+, an emerging high speed backplane standard, uses trapezoidal
waveforms to limit cross talk
1.6.2. Differential Line Considerations
A differential communication system involves the use of two signal carrying wires between
transmitter and receiver, such that the signal current flows in opposite directions in each wire. The
net effect of this is the receiver is only concerned with the difference in voltage between the two
wires. The absolute value of the de common mode voltage of the two wires is not important In
practice, transmitters and receivers have a finite common mode voltage range in which they can
operate.
The use of a differential communications interface allows transmission at higher data rates over
longer distances to be accomplished. This is because the effects of external noise sources and cross
talk are much less pronounced on the data signal. Any external noise source coupling onto the
differential lines will appear as an extra common mode voltage which the receiver is insensitive to.
The difference between the signal levels on the two lines will therefore remain the same. By the
.same argument, a change in the local ground potential at one end of the line will appear as just
another change in the common mode voltage level of the signals. The differential output to the line
will also provide a doubling of the driver's single-ended output signal. Twisted pair cable is
commonly used for differential communications since its twisted nature tends to cause cancellation
of the magnetic fields generated by the current flowing through each wire, thus reducing the
effective inductance of the pair.
The main disadvantage of a differential system lies in the fact that two cables are reqnired for each
communication link. This increases system cost but provides superior performance when data is
transmitted at high rates over long distances.
The RS-485 and RS-422-A standards both use differential type transmission.
5-23
1993 Linear Design Seminar
Network Topology
Star Connection
.• Driver 'Sees' Many Transmission
Lines
• Terminating Multiple Stations in RT
can Cause excessive Line Loading
• Driver 'Sees' One Transmission Line
• Far End Terminated Only (simplex)
Figure 5.1,0- Network Topology
1.7.Network Topology
In addition to considering signal attenuation, the effects of noise, sigDat distortion and correct line
termination, we must also consider the way in which stations are connected to the line. Furthermore
the position of the line termination resistor and device positioning must be considered. There are two
basic methods of connection, see Figure 5.10;
.
i. The star connection
U. The daisy chain connection
Considering the star connection, the transition edge from the driver will be loaded by a group of
separate transmission lines, rather than one. Each transmission line boundary will cause a change in
impedance resulting in reflections.
Another situation to avoid is the termination of multiple stations, since this could excessively load
the driver. Termination at the extreme ends for RS-485 (half duplex) and far end only for RS-422 is
recommended and is accounted for in each standard. Normally stubs (taps of the main line) should
be kept as short as possible so not to appear as transmission lines themselves.
5-24
Data Transmission
Star Versus Daisy Chain Topology
• Measurement Information
V
t
=
2 V/div
50 nS/div
• Cable Specification
- Flat Ribbon Cable with Parallel Copper Wire - U.L.2651
- CapaCitance Between Adjacent Lines =49.2 pF/m
- Line Length 2 m From End to End
- Characteristic Impedance (Zo) = 105 Q
---.t
Figure 5.11- Star Versus Daisy eluzin Topology
The recommended method is to use the daisy chain, a configuration where the transmission line
continues from one receiver to the next and only the last receiver on the chain is terminated. This
means that the transmission line and hence the driver will see one continuous transmission line with
only one termination resistor. Each tap-off will in effect be a stub, but in this case they will not be all
grouped together and will be kept very short to reduce their effect.
The Figure 5.11 shown further confirms the need to keep stub lengths short and the use of correct
termination techniques by comparing the effect on signal quality for the daisy chain and star method
of connection.
In both instances exactly the same application scenario was used as was the same cable specification.
The cable used was a flat ribbon cable with parallel copper wire conforming to U.L. specification
2651. Connections were made as shown in the previous figure and the total cable length from source
to destination was 2 m.
1.7.1. How Short is Short?
It has been described earlier that a pair of cables will act as a transmission line if the round trip
delay, tpd ,is more than 5 times the transition times of the driver, tT. The converse is true
propagatio~
5-25
1993 Linear Design Seminar
if the line is not to operate as a transmission line but as a lumped parameter model. This forms the
basis of the stub length calculation given below.
The rule of thumb states that the transition time of the pulse sent down the line should take ten times
the time taken for the pulse to propagate to the end of the stub. As a result, any reflections will be
incorporated into the transition edge.
From this basis, the length of a stub can be calculated using the cable and driver parameters.
The pulse speed down 'the line, U, equals the reciprocal of the product of the line impedance and line
capacitance, both of which are normally specified for the cables used. The propagation delay down
the stub should be at the most one tenth of the transition time of the pulse. These facts can be
brought together to give the length of the stub, Ls , as;
L =ttD
S
10
Using the SN75ALS180 and its transition time of 13 ns, a cable with a characteristic impedance of
780 and line capacitance of 65pF,:
Using: Zo
=~Lo , as an approximation of the equation shown in section 1.3.1. (In practical
Co
situations jmL»R and JmC»G, therefore Rand G can be assumed to be negligible although the R
component must be considered for long line lengths.)
And: V p
=~
1
as an approximation of the phase velocity equation in 1.3.1,
LoxC o
Substitution gives: Vp
1
=--ZoxC o
Using the values given earlier: Vp
1
=78x65xlO12 =198xl06 Jm-1
Now, using our rule of thumb described earlier: tpd
= tID
10
13xl0-9
Gives tpd
5-26
=
10
and therefore Ls
and
Ls
=tpdxVp
=1. 3xlO-9 x198x106 =257mm =lOinches
Data Transmission
This means the length of each stub should be no more than 257 lDDl. Under this length the stub can
be considered as a lumped load and will not cause any unwanted reflections. The main effect of each
stub in this case will be a slight increase in the capacitance loading of the line.
5-27
1993 Linear Design Seminar
5-28
Data Transmission
2. Interface Circuits for EIA-232
2.1.General Information
This section on EIAfflA-232, or RS-232 as it bas been known in the past, will discuss the electrical
aspects of the standard, i.e. the physical layer. Initially we will discuss the latest developments of the
'E' revision upgrade and then cover TIs latest products conforming to this standard. However the
reader should note the products under discussion in this section are application specific to the 9-pin
DB9 Personal Computer DTE serial interface which is effectively a sub-set of the full EIA-232
standard. As a semiconductor manufacturer we find the majority of EIA-232 applications are moving
to this interface. Due to the nature of the signals i.e. 5 receive and 3 transmit lines the older
established EIA-232 products no longer provide an optimum solution. This interface is now driving
the need for single chip EIA-232 solutions. Additional features such as single supply operation,
increased ESD protection, power down modes have moved from the desirable features to the
essential features of today's interface. In the later half of this section we will discuss the DB9
interface and TI's products designed specifically for this application.
Looking at the DB9 interface one step back into the digital system, there is in most cases a UART or
ACE (asynchronous communication element). The ACE provides the parallel to serial conversion
and the necessary start/stop bits, parity bit generation and checking for error free data transmission.
TI manufactures a number of ACEs, the most advanced being the TLl6C552. This integrates two
serial ports with FIFO buffers together with a PC parallel port. Although not specifically covered in
this section a selection guide on ACEs is included towards the rear of this section.
2.1.1. Reliability Data
System designers have long been aware the mean-time-between-failure (MTBF) for most systems is
limited by the reliability of the line interface circuitry. This is mainly due to the shear power
dissipation of such line circuits. The older devices such as the SN75188 quad'driver ran at quite high
temperatures with obvious degradation on reliability. For today's products the use of low power
bipolar and more recently BiCMOS technologies significantly reduces operating temperatures while
maintaining the robustness associated with bipolar designs providing for a more reliable interface.
This is show by reliability data collected on TI's products.
5-29
1993 Linear Design SemInar
Life test data collected on a range of EIA-232 devices yielded a failure rate of 1.65 FITS (failures
per 1()9 device hours). This was at an ambient temperature of 55°C (to an upper confidence level of
60% and assumes an activation energy of 0.96 eV).
2.2.EIAlTIA-232-E Industry Standard for Data
Transmission
EIA-232E Industry Standard for
Data Transmission
Scope of Standard
DTE
•
•
•
•
Electrical and Signal Characteristics
Mechanical Interface Characteristics
Functional Description of Interchange Circuits
Standard Interface for Selected
Sytem Configurations
~
Q)
EIA-232 Link
Flat Ribbon or Multlcore Cable
typically Less Than 15 Metres
E
Q)
oC ....
Q.cn
.- >.
"""t:...._ _ _ _ _ _ _ _ _J -
mOO
c..
Figure 5.12 - EIA-232-E Industry Standard/or Data Transmission
The Electronic fudustries Association (EIA) introduced the RS-232 standard in 1962 in an attempt to
standardise the interface between Data Terminal Equipment (DTE) and Data Communication
Equipment (DCE). The DTE comprises the data source, data sink or both. The DCE provides the
functions to establiSh, maintain and terminate a connection, and to code/decode the signals between
the DTE and the data channel. Although emphasis was then placed on interfacing between a modem
unit and data terminal equipment, other applications were quick to adopt the EIA-232 standard. The
growing use of the PC (personal computer) quickly ensured that EIA-232 became the industry
standard for all low-cost serial interfaces between the DTE and peripberal. The mouse, plotter,
printer, scanner, digitiser, and tracker-ball, in addition to the external modem unit, are all examples
5-30
Data Transmission
of peripherals that connect to an ElA-232 port Using a common standard allows widespread
compatibility plus a reliable method for interconnecting a PC to peripheral functions.
EIA - 232E Electrical Specifications
Single Interface Une (1 of 25 Maximum)
Interchange Signal
+5V
+12V
+5 Vto 15V
TI~
TI~
CMOS'~~~--~--~~~CMOS
I
_
-
Reference
Common
• Receiver Input Impedance,
RT = 3 kQ to 7 kQ
• Driver Power-off Impedance,
RS > 3000
I I
~:j+-
• Tx Rise/Time Fall within Transition
Region;
1 ms
Below 40 bps
4% of Unit Interval 40 to 20 kbps
• Load Capacitance < 2500 pF •
Includes Receiver Input
Slew Rate: 30 VIps max
Figure 5.13 - EIA-232-E Electrical Specifications
The EIA RS-232-C standard, revised in 1969, was superseded by EIA-232-D (1986), and recently
bas been once again superseded by EINI'IA-232-E which brings it in-line with
V24, V.28
and ISO IS2110. (TIA refers to the Telecommunication Industry Association). The latest revision
includes an update on the rise time to unit interval ratio and reverses the changes made by the D'
revision, see Figure 5.14. Although an older standard, with problems like high-noise susceptibility,
low data rates and very limited transmission length, ElA-232 fulfils a vital need as a low cost
communication system. Consequently new products are being developed at a faster rate than ever.
ccrn
2.3.EIA-232 Specification
The standard sets out to ensure:
i.
Compatible voltage and signal levels
Ii.
Common pin wiring configurations
iii.
A minimum amount of control information between the DTE and DCE.
5-31
1993 Linear Design Seminar
It accomplishes this by incorporating the following areas in the standard:
Electrical and Signal Characteristics
Electrical and signal characteristics of the transmitted data in terms of signal voltage levels,
impedance's, and mtes of change.
Mechanical Interface Characteristics
Mechanical interface characteristics defined as a 25-way "D" connector, with dimensions and pin
assignments specified in the standard. Although the standard only specifies a 25-pin D-type
connector, most laptop and desktop PCs, today use a 9-pin nDB9S" conn~tor shown in Figure 5.17.
The reader should note the DCE equipment connector is male for the connector housing and female
for the connection pins. Like wise the DTE connector is a female housing with male connection pins.
Handshake Information
A functional description of the interchange circuit enables a fully interlocked handshake exchange of
data between equipment's at opposite ends of the communication channel. However, V24 defines
many more signal functions than RS-232, but those that are common are compatible. Twenty two of
the twenty five connector pins have designated functions, although few, if any, practical
implementations use all of them. The most commonly used signals are also shown in Figure 5.17.
It is worth noting that for applications which use the 25-pin D-type connector there is often a
problem in commnnication due to different handshaking signals employed by each system.
2.3.1. EIA-232-E Electrical Specifications
All EIA-232 circuits carry bipolar voltage signals with the voltage at the connector pins not to
exceed ±25 V. Any pin must be able to withstand short circuit to any other pin without sustaining
permanent damage. Each line should have a minimum load of 3 kll and maximum load of 7 kll
which is usually part of the receiver circuit. A logic '0' is represent by a driven voltage of between
+5 V and +15 V and a logic '1' ofbetween-5 V and -15 V. At the receiving end a voltage of between
+3 V and +15 V represents a '0' and a voltage of between -3 V and -15 V represents a '1'. Voltages
between ±3 V are undefined and lie in the transition region. This effectively gives a 2 volt minimum
, noise margin at the receiver.
The maximum cable length was originally defined in RS-232C as 15 metres, however this has been
revised in EIA-232-D and EIAffIA-232-E and is now more correctly specified as a maximum
capacitive load of 2500 pF. This equates to around 15 to 20 metres line length depending on cable
capacitance.
As mentioned in an earlier section, EIA-232 specifies a maximum slew mte of the signal at the
output of the driver to be 30 V I~. This limitation is concerned with the problem of cross talk
between conductors in a multiconductor cable. The faster the transition edge the greater the cross
talk. This restriction together with the fact of the driver and receiver using a common signal ground
and the associated noise introduced by the ground current severely limits the maximum data
'throughput.
5-32
Data Transmission
'RS-232' Transition Time versus Data Rate
Unit Interval (ms)
100
10
0.01
0.1
0.001
~o .------,------~----_,_r----,_._--,
:
CD
i=
/f R5-232C;
I ~ ~¥ ! 4% UMIT
~
.§.
E
i EIA-232E i I
0.1
j
0
c:
e
I-
I
I
I
I
I
I
-·r·--··-----~···--·-r----·---·
0.006
~
0.06
I
0.6
~
i EI~-232D I
c:
:e
rn
;:
+-----.=·~···t·---·-·········---··+ ElA-232D i ····-r······-·-·····-·····t··---r·-···-·_--··
'0'
0.0006
-~..,..-+i 5
0.01
I
Umlt -t!---L----i
i
it
8
0.001
..!!.
3OV/p.s UMIT
0.0001
60
10
100
1K
10K20K
100K200K 1M
Data Rate (Bits/Sec)
Figure 5.14· 'RS·232' Transition Time versus Data Rate
For this reason the EIA-232 standard specifies a maximum data rate of 20 kbps. The standard also
specifies the relationship between unit interval and rise time through the transition region (+3 V to 3 V) or lor. This is the main difference between the 'E' and the 'D' revision. This is showu more
clearly in Figure 5.14. EIA-232-D up to 8 kbps specified the relationship between transition time and
unit interval or bit time 11, to be 4% maximum. Above 8 kbps this was relaxed to 5 ~s maximum
independent of the data rate. Both the 'C' and the 'E' revision specify the ratio of tr/lb to be 4% all the
way up to 20 kbps. One can extrapolate this further, using the 4% figure and with the maximum slew
rate of 30 V IIJS, the maximum achievable data rate is 200 kbps however practically this is limited to
around 120 kbps. A number of software programs operate at transfer rates of 116 kbps. Furthermore
over longer line lengths the maximum drive current or short circuit current of the line driver becomes
the dominant feature on data rate as against the 30 V IIJS slew rate. As the line length increases the
load capacitance also increases requiring more current to maintain the same transition time. The
curves showu in Figure 5.15 indicate the drive current required to maintain the 4% relationship at
different data rates. In today's low power systems, this level of output current is not sustainable at
above say 20 kbps. In practice the line length is usually limited to around 4 metres for the higher data
rates. Most drivers can handle the higher transmission rates over this line length without seriously
compromising supply current.
1993 Linear Design SemInar
EIA-232E Driver Output Current versus CL
45
35
EIA-232E
.........-..-.--..-.......-........ TX Rise TIme
i
=4% 01·-····-··············-··-···········+-···············-......
--....... --
Unit Interval
25
15
20kbps
.__.....__.__..._-_. __..._._....
i
··---·---···-···-·j-""·--·--·----·10 kbps ..
5
o
500
1000
1500
2000
2500
Load Capacitance (PF)
Figure 5.15 • EIA·232·EDriver Output Current versus CL
The curves shown in Figure 5.15 were generated using the following equation which is .an
approximate equation relating transition time tr. line capacitance Cl, receiver input impedance~,
driver short circuit current 10 , and the initial and final line voltage (-3 V and +3 V) of the transition
region, Vi and Vfrespectively,
.
tT
_
C In[IR j X1ol+IVfl]
-Rjx
IX IRjx10 I_IVj I
Turning this equation around with respect to Cl , and cancelling ~, Viand Vf we get:
5-34
Data Transmission
The voltage levels, Vf and Vi, used in this equation are the extremes of the transition region.
Assuming a typical driver short circuit current of 20 mA and a receiver input resistance of 5 ill, the
typical time taken to pass through the transition region would be :-
seconds.
This equation can be manipulated further to gain a relationship of unit interval with line length in
terms of load capacitance and short circuit driver current. The equation in Figure 5.16 assumes
conformance to the 4% rule.
Calculating Line Length and Data Rate
Common
Conductorrlllll--------------1IIiIIII
Signal
Conductor
Une Length Calculation
Maximum Capacitance
Receiver lIP Capacitance
Maximum Une Capacitance
= 2500 pF
<20 pF
= 2480pF
Total Une Capacitance/m
Mutual Capacitance of Cable/m
Stray Capacitance/m
Cc =CM +Cs
CM
Cs
Maximum Line Length
= 2480
Standard Cable CM
Max Line Length Shielded
= 40 pF/m
Shield
Data Rate Calculation
Unit -1
0.04
Interval-la C c In(lo + 1 \
10 - 1 ')
10 = Short Circuit Current of Driver
Ccis in nF
CO
= 20 Metres
Cs =2XCM For Shielded Cable
. . Cs = O.5x C For Unshielded Cable
M
Figure 5.16 - Calculating Line Length and Data Rate
2.3.2. Calculating maximum line length
So far we have discussed line length in terms of load capacitance. For practical purposes we must
now consider turning this value for load capacitance into true line length. The standard states a
maximum line capacitance of 2500 pF. The input capacitance of a receiver is say 20 pF which leaves
2480 pF as the maximum line capacitance.
We must now consider the type of cable to be used. Standard EIA-232 cable as supplied by a number
of manufacturers has a mutual capacitance of approximately 40 pF per metre. In addition to this we
must add the stray capacitance. Stray capacitance varies considerably on whether the line is shielded.
5-35
1993 Linear Design Seminar
For non shielded cable the stray capacitance is approximately half the mutual capacitance, for
shielded cable it is double the mutual capacitance. As can be seen from Figure 5.16, for shielded
cable the maximum line length is 20 metres, with unshielded cable it is over 40 metres.
2.3.3. The DB9S Connector
As mentioned earlier today's notebook and laptop PCs, with their quest for reduced size, no longer
use the standard 25-way D-type connector detailed in the standard but have substituted it for a 9-way
D-type. This is commonly known as the DB9S connector. Like the 25-way, the DCE equipment
connector is a male outer casing with female connection pins, and the DTE is a female outer casing
with male connecting pins.
As the interface is now made up of only nine pins the handshaking lines have been reduced
accordingly but still are sufficient for most applications. Figure 5.17 shows the pins assignments for
the interconnect cable into the DTE connector. An explanation of the function of each signal is given
below:
EIA-232 DB9S Interface
Data Set Ready
Receive Data Line
Request To Send
DB9S CONNECTOR
Transmit Data Une
Clear To Send
Data Terminal ready
Ring Indicator
Figure 5.17 - EIA-232 DI!9S Interface
5-36
Data Transmission
Data Carrier Detect (DCD) " Received Line Signal Detector
The ON condition on this signal line as sent by the DCE informs the DTE that it is receiving a carrier
signal which meets its suitability criteria from the remote OCE. In modems, this circuit is held on as
long as it is receiving a signal that can be recognised as a carrier. On half duplex channels, OCD is
held off when RTS is in the on condition.
Data Set Ready (DSR)
This is a signal turned on by the DCE to indicate to the DTE that it is connected to the line.
Receive Data Line (RD)
The signals on the RD line are in serial form . When the OCD signal is in the off condition the RD
line must be held in the Mark state.
Request to Send (RTS)
This signal is turned on by the DTE to indicate it is now ready to transmit data. The DCE must then
prepare to receive data. In half duplex operation, it also inhibits the receive mode. After some delay
the DCE will turn the CTS line on to inform the DTE it is ready to receive data. Once
communication is over and no more data is transmitted by the DTE, RTS is then turned from on to
off by the DTE. After a brief time delay to ensure all data has been received that was transmitted, the
OCE turns CTS off.
Transmit Data Line (TD)
The signals on this circuit are transmitted serially from DTE to OCE. When no data is being
transmitted the signal line is held in the Mark state. For data to be transmitted, DSR. DTR, RTS and
CTS must all be in the on state.
Clear to Send (CTS)
This signal is turned on by the DCE to indicate to the DTE that it is ready to receive data. CTS is
turned on in response to simultaneous on condition of the RTS, DSR and DTR signals.
Data tenninal Ready (DTR)
This in conjunction with DSR indicate equipment readiness. DTR is turned on by the DTE to
indicate to the DCE it is ready to receive or transmit data. DTE must be in the on condition before
the DCE can turn on DSR. When DTR is turned off by the DTE, the I>CE is removed from the
commuuication channel following the completion of transmission.
Ring Indicator (RI)
The ring indicator is turned on by the DCE while ringing is being received and is a term left over
from the use of the standard in telephone line modem applications. Primarily used in auto-answer
systems.
Signal Ground (pin 5)
This is the ground which provides the common groUnd reference for all the interchange circuits and
is separate from the protective ground. The protective ground is electrically bonded to the equipment
frame and is usually directly connected to the external ground. Any static discharges are then routed
directly to ground without affecting the signal lines.
5-37
1993 Linear Design Seminar
While all these pins are assigned, once again not all equipment uses every pin. Consider the mouse
which can use as few as 4 lines, Signal ground, RI, TD and RD. Most equipment does however
utilise a minimum ofRTS, D1R, TD, RD, CTS and DSR.
Also of note is the usage of the DTE interface. The majority of equipment uses this interface and
makes use of the null modem as a means of communication between DTEs. The null modem makes
use of feeding back the RTS signal to the CTS line on each interface, Figure 5.17.1 details the
connections for implementing a full null modem for the DB9S connector.
EIA-232 Null Modem
DCD 1
RD 2
TO 3
DTR 4
GND 5
DSR 6
RTS 7
CTS 8
RI 9
DCD
2 RD
3 TO
4 DTR
5 GND
6 DSR
7 RTS
8 CTS
9 RI
1
Figure 5.17.1 • EIA·232 NuU Modem
2.4.SN75C185: Optimised PC Interface
If we study the DB9S DTE intetface further we see there are 3 transmit lines and 5 receive lines.
This is an awkward combination for the standard EIA-232 IC configurations in use today. Consider
the ubiquitous SN75188 and SN75189 quad drivers and receivers. To implement this interface would
require 3 ICs, one '188 and two '189s. Equal combinations of drivers such as the triple driver/receiver
of the SN75Cl406 still requires two chips to implement the interface.
For this reason TI has developed the SN75C185. By providing the exact combinations of driving and
receiving elements, along with the necessary passive components, a highly optimised Solution can be
Data Transmission
provided - the SN75C185 is just that. The SN75C185 integrates three drivers and five receivers and
includes the necessary capacitors for driver slew-rate limit (30 VIps) and receiver filter
implementation, all in a single 20-pin package
The designer's dilemma is eased further by the use of a flow-through pin out architecture, see Figure
5.18. By aligning one side of the SN75C185 with the pins of the DB9S connector and the other to
industry standard ACEs or UARTs, printed circuit board (PCB) layout can be greatly simplified.
SN75C185; Optimised PC Interface
EIA-232
Port
DCD
a:
• Contains Five Receivers and
Three Drivers
DSR
~z
AX
RTS
z
o
TX
CJ)
en
CTS
DTR
C
AI
u
III
• Less than 8 mW Power Consumption
• Easy Interface Between ACE and
Serial Port Connector (Flow Through Pin
Out)
• Available in 20-Pin DW and N
Packages
• Available in O°C to 70°C and -40°C to
+85°C Temperature Ranges
.One SN75C185 Replaces;
2 X SN75189 (5 Cells)
1 XSN75188 (3 Cells)
=>35% Saving
in Board Space
8 - 12 Capacitors
Figure 5.18 • SN75CI85; Optimised PC Interface
2.4.1. Low Power as Well
In common with all of Texas Instruments BiMOS products, these devices combine the benefits of
Bipolar's drive capability and robustness along with the low-power consumption of CMOS. This
power saving, when compared to the alternatives is calculated in the following pages and is
illustrated graphically in Figure 5.19.
Available in either a single 20-pin, wide-bodied SO pack or DIP pack, the SN75C185 offers
designers greater than 25% saving in board space, compared to alternate solutions.
5-39
1993 Linear Dt)Sign Seminar
Power Supply Considerations
Current Row
SN75C185 vs '188'189
VDD (12 V)
SN75188x1
Device
Total 188/189
SN75C185*1
600
900
Power Dissipation - Pdis (mW)
• Basic Equation
~is
= Pq + nFrs + mPos
• Chip Temperature Will Rise By;
-74°C For SN7S188 & 2SoC Each Receiver
-22°C Only For SN7SC185
Figure 5.19 - Power Supply Considerations
2.4.2. SN7SC18S; Power Considerations
System power consumption is often considered very late in the design cycle. Of even more concern
is that the power consumption of the interface circuitry, being the least attractive circuit to design, is
often totally overlooked. The consequences of this can be catastrophic especially when using devices
in confined spaces. These areas will normally have very poor air circulation, causing the ambient
temperature of the whole system to increase.
These types of problems are particularly difficult to diagnose as failure can often be intermittent as
devices pass into and out of thermal shutdown.
For these reasons, low quiescent-power devices are becoming a necessity for modern applications.
As digital technologies advance, their power consumption decreases, making the interface circuits
the limiting factor as far as system power consumption is concerned.
2.4.3. Interface Power Consumption Calculations
Before the availability of the SN75C185 common implementations of EIA-232 require one quaddriver package and two quad-receiver packages; in the driver chip, one device is redundant while in
Data Transmission
the receiver chips, three devices are redundant. These devices would, however, still be taking their
quiescent current and hence wasting power. In order to provide the interface signals, three integrated
circuits were required while only two-thirds of the capability was being used. The calculations below
demonstrate this difference.
When comparing the 'C185 solution to that provided by the SN75188 and SN75189 devices, the
power saving is enormous.
Both implementations require three supply voltages; a 5 V and ±12 V supplies. The power
dissipated, Pdis, within each device is the quiescent power of the device, Pq , plus the power
dissipated in the input stage, Pis, and the power dissipated in the output stage, Pos, (when it is
driving the line).
Hence,
Pdis
= Pq + nPis + mPos
Where n is the number of active input stages and m is the number of active output stages.
SN7S1881SN7S189 Combination
Using an SN75188 for the driver, the quiescent power consumption would be 576 mW. In addition
to this the power dissipated in the input stage, Pisd:Pisd
= VCC * IlL
= 12 * 1.6mW
= 19.2mW.
This is multiplied by four to take into account all four drivers, putting the fourth driver into a defined
state so as to reduce any noise problems that could be introduced by leaving the input floating.
The power dissipated in the output stage, Posd, is:
Posd
= (VCC - VOH)* V~H
9
=(12-9) *3" mW
=9mW.
This figure will be multiplied by three to take into account the active three drivers driving the
interface line. These sum up to give a total power dissipation of
Pdis
= 576+4x 19.2+3 x 9
mW
=680mW.
The junction temperature of a DIP device would have risen by 74OC.
Using the SN75189 receivers, a quiescent power of 130 mW would be dissipated by each package.
This would be multiplied by two to take into account both chips.
5--41
1993 Linear Design Seminar
The power dissipated in the output stage has a similar equation to that of the driver.
Posr
== VOL * IoL
=0.45 x 10 mW
= 4.5mW
This power dissipated is multiplied by five to take into account the five receivers being used. The
input stage can also dissipate some power, but this power is not supplied by this part of the interface
system. The power dissipated within the IC will however cause the junction temperature to rise.
.
Pisr
_ VOH(d)2
RL
92
="3
mW
=27mW
This power dissipation is then multiplied by five. The remaining receivers will require tying to a
state where they will not be susceptible to noise. Tying them to the 5 V supply increases the power
dissipation by a further 8.3 mW per receiver.
Assuming three receivers in one SN75189 are being used and two receivers in the other, the power
dissipated for the first receiver is:
Pdis
= 130 + 4 x 27 + 3 x 4.5
mW
=233mW.
The power dissipated in the second receiver is:Pdis
= 130+4x27 +2x4.5
mW
= 21OmW.
This raises the tempemture of the rlfst and second receiver by 250C and 23OC, respectively.
The total power dissipated by the SN751881189 combination is the sum of these three powers,
equalling J...U.llL
Using the SN75C185
The power dissipation of the SN75C185 can be calculated in a similar manner. The quiescentpower consumption of the SN75C185 is equal to:Pq
=VDD * IDD + VSS
* Iss + VCC x;Icc
= 12 * 200 + -12 x -200 + 5 x 750
= 8.55mW
The power dissipated in the input stage of the driver is:Pisd
= VDD x IlL
= 12x 1 JlW
5-42
JlW
Data Transmission
= 121lW.
This is multiplied by three to take into account all of the drivers.
The power dissipated in the output stage of the driver, Posd, is:
= (12 - 10)
X
10
3"
mW
=6.67mW.
This is multiplied by three to take into account the three drivers driving the interface line, giving a
power dissipation of 20 mW.
The power dissipated in the output stage of the receiver has a similar equation to that of the driver,
so:
Posr
= VOL x IoL
= 0.4 x 3.2 mW
= 1.28mW
This value is multiplied by five giving a total of 6.4 mW of power dissipated in the receiver's output
stages. The input stage will also dissipate some power, but this power will not be supplied by this
part of the interface system. The power dissipated within the chip will however cause the junction
temperature to rise.
The power dissipated in the input stage, Pisr, equals:
Pisr
_ VOH(jI)2
RL
102
=""3
mW
=33.3 mW
This power dissipation will also require multiplying by five. Giving a total input power dissipation
of 167mW.
Summing all the power contributors the total power dissipation is given by;
Pdis = Pq + 3Pisd + 3Posd + 5Pisr + 5Posr
= 8.55 + 3 x 12 x 10-3 + 3 x 6.67 + 5 x 33.3 + 5 x 1.28
mW
=201mW.
The total power dissipated by the SN75C185 is 201
mW
5-43
1993 Linear Design Seminar
This is represents a tremendous power saving. especially when considering that the line is still being
driven. The temperature rise within .the SN75C185 would only be 22OC. enabling it to operate more
reliably and with higher ambient temperatures.
2.4.4. On Chip Slew Rate Limiting
The EIA-232-E standard specifies a maximum slew rate through the transition region of 30 VIps.
Relating this to capacitance and current only 100 JiA of output current into 30 pF load capacitance is
needed to exceed the slew-rate limit. All devices are capable of supplying more than 5 mAo
Therefore if the slew rate limit is not. to. be exceeded, the switching speed of the driver's output stage
needs to be reduced. An eStablished solution is to place loading capacitors on the output of the
driver. The value of the loading capacitor required will depend upon the line length. but it is
generally in the order of 330 pF. The effect of this capacitor is to cause the output transistors to
saturate. causing it to short circuit current limit, thus preventing fast switching edges.
There are some major problems with this established process; one being the variance in current at
which the output short-circuit current limit operates. especially when taking temperature changes
into consideration. Again the value of capacitance placed on the line will depend upon the driver's
output short-circuit capability as well as line length. For example a device capable of sourcing
10 mA will need a total capacitance of 330 pF placed on its output to meet the 30 V 1J.lS slew rate
limit, while placing this value across a device capable of sourcing 4 mA will have its slew rate
limited to less than 12 V/J.lS.
Another problem encountered is the increase in power dissipation through the output stage. The
output voltage of the driver will normally be close to one supply rail. so when it tries to switch to the
other. the active transistor will have almost all of the supply voltages across it. The extra external
capacitor will clamp the driver's voltage close to the supply voltage causing the output transistor to
source large amounts of current. The combination of a large source current and large voltage Cause
it to dissipate large amounts of power. Operating at these prolonged bursts of high current will
ultimately increase the chip temperature which in turn can affect the long-term life of the device.
Bipolar technologies are normally much better able to withstand such effects
A better solution. and that employed by the drivers in the SN75CI85. is to place the slew-rate
limiting within the chip its:elf. Using similar techniques to those employed for slew-rate-limited
operational amplifiers. the slew rate of line drivers can also be limited. Using the Miller capacitance
multiplying effect, the slew rate of the driver can be slowed down. The on-chip capacitors are
normally in the order of 5 pF. while the currents driving the on-chip capacitor are the order of micro
amperes. thus reducing power consumption within the device. The biasing current to the output
transistors is unaffected by this technique and will be more than sufficient to drive the 3 leO load as
offered by the receiver.
2.4.5. Internal Noise Filtering
The standard states a maximum line cable capacitance of 2500 pF. which corresponds to an
approximate line length of 20 metres. As the interface line gets longer. it becomes more susceptible
to noise pick-up from the sUrrounaing environment. This pick-up is due in part to the inductive
nature of the line. As the signal switches. a rapidly changing magnetic field induces noise currents
5-44
Data Trarulmission
into the line, thereby corrupting signal data. The level and cause of this noise will dictate the nature
of solutions or precautions that should be taken.
For operation at high data rates, the use of a differential line might be the best solution. If however,
a low cost and simple single-ended solution is required then standard EIA-232 devices can be
modified to give noise protection. This is achieved by slowing down the response of the receiver's
input stage, making them too slow to respond to fast switching noise pulses. Even small levels of
input noise can falsely trigger the receiver. The maximum data rate specified in the standard is
20 kbps, corresponding to a minimum pulse period of 100 j.IS. Therefore in normal applications,
most devices are far faster than the specification requires.
To slow down older bipolar receivers such as SN75189s, a capacitor, Cc , needed to be placed on
each of its response control pins. This means an additional four capacitors per device, which can be
awkward and costly. The effect of this response control capacitor is to set up a low-pass filter on the
receiver's input In order to provide large pulse rejection, the capacitor needs to be quite large.
Furthermore, the filter response is asymmetric, affording protection against positive noise voltage
spikes only, negative spikes are unaffected, and will tend to attenuate rather than reject short noise
pulses.
Receivers in the SN75C185 integrate on-chip filtering which reject fast transient noise pulses. The
on-chip filters are more precise than filters implemented using external passives. Consequently the
receiver response is unaffected. These filters are totally symmetrical, offering protection against both
positive and negative noise pulses and with the ability to reject rather than attenuate short noise
pulses. To approach the level of filtering offered by the 'C185 receivers the standard '188 type
receivers require much larger capacitors and even then fall well short of filtering requirements.
5-45
1993 Linear Design Seminar
SN75LBC187; Optimised for Portables
5V
....
.9
0
CD
c::
c::
0
()
U)
Ol
!D
CJ
TO
UART
C\I
C')
C\I
<
jjj
cs
• Switched Capacitor Converter
- Generates +/- 8.SV Supplies off sv.
- Only 0.2 JiF External Capacitors
• Shutdown Mode
-Icc = 10 JiA (Max)
• High Data Rate Capability
- > 116 kbps with 2S00 pF Load
• Robust Bipolar I/O Structures
- ±30 V Receiver Input Range
- 6 KV ESD Protection
• SSOP Packaging
Figure 5.20 - SN75LBC187; Optimised for portables
2.5.SN75LBC187; Optimised for Portables
The SN75C185 is the ideal choice for computer applications where the bipolar supplies required by
EIA-232 are available within a computer system. Most desk top computers generate ±12 volt
supplies for powering the internal disk drive. However for portable equipment, e.g. laptops,
notebooks, hand held measuring equipment, the EIA-232 interface may be the sole user of a negative
supply. The cost of implementing a switch mode supply, using inductive switching regulators, to
generate the negative supply can make this option unattractive. Switch mode supplies also have the
draw back of increasing the EM! emissions, a factor becoming an increasingly important design
constraint Integrating a switch mode power supply on silicon would reduce the emissions, and has
been the dream of semiconductor manufacturers, but thus far no one has yet managed to integrate the
inductor.
An alternative way, and the basis of modem technology charge pumps, is to make switching
regulators using capacitors. In essence they operate by applying charge to a capacitor via an input
voltage and then adding, subtracting or inverting the voltage on the positive or negative voltage
terminals. This charge is trausferred into a holding reservoir capacitor that is then used to supply the
5-46
Data Transmission
output voltages. Furthermore such a scheme can be integrated into silicon. Using a network of
capacitors both voltage doublers and invertors can be made.
The SN75LBC187 integrates the charge pump on the same IC as the EIA-232 drivers and receivers.
It is fabricated in TI's proprietary LinBiCMOS technology and contains three independent drivers
and 5 independent receivers together with the switched-capacitor voltage converter. The
SN75LBC187 provides a single 5 V supply interface between the asyuchronous communications
element (ACE or UART) and the serial port connector of the data terminal equipment (D1E). This
device has been designed to conform to standards EIAITIA-232-E-1986 and EIAfI1A-562 and
CCnT recommendation V.28.
The switched-capacitor voltage converter of the SN75LBC187 uses four small (0.2 J.1F) external
capacitors to generate the positive and negative voltages required by EIA-232 line drivers from a
single 5 V logic supply input Like the SN75C185 the drivers feature output slew-rate limiting to
eliminate the need for external filter capacitors. The receivers can accept ±30 V without sustaining
damage. Furthermore the 'LBC187 is guaranteed to withstand up to 6KV ESD on any of its pins
making it TI's most rugged EIA-232 product
The device also features a reduced power or shutdown mode that virtually eliminates the quiescent
power supply when the IC is not active.
The primary application for the 'LBC187 is for battery operated, portable equipment where power
consumption is a key factor. A separate consideration, and one that usually goes hand in hand with
these factors, is that of shear physical size. With the 'LBC187, TI has used the latest SSOP packaging
to reduce board area to an absolute minimum. The new SSOP package reduces board space to 43%
of the standard 28-pin SOIC package Couple this with the small 0.2 ¢1 and you have the ideal single
supply solution for space restricted applications.
5-47
1993 Linear Design Seminar
RS-232 116k Bits Per Second Operation
Figure 5.21 - RS-232 116k Bits Per Second Operation
2.5.1. SN75LBCI87; 116 kbps operation
As discussed in section 2.3.1 the limitation on data mte is one of short circuit output current and the
actual load capacitance. With the LBC187 the driver short circuit current, los, is higher than say the
SN75C185 and is therefore able to drive longer line lengths at higher data mtes. Figure 5.21
illustmtes this. The 400 pF load in the top half of the figure represents a cable approximately 3
metres long. As the 'scope tmces show, the 'C185 produces a perfectly acceptable output tmce at
116 kbps. Similarly with the 'LBC187 tmce.
If the line length is now upped to 20 metres or 2500 pF load, we can see how the short circuit current
limit now limits the slew mte. With the LBC187 the tmce is still acceptable and will provide reliable
data tmnsmission. With the 'C185, the data will still be tmnsmitted but the probability of error is now
increased. Most software programs that opemte 116 kbps, e.g. LaplinkTM (Laplink is a trademark of
Travelling Software Inc.) provide the interconnect cable as part of the system. In most cases this
cable is less than 3 metres in line length so either the 'C185 or LBC187 would be able to tmnsmit
data reliably. It is interesting to note that both devices would meet EIA-232-D if the rise time to unit
interval relationship was extmpolated, however both would fail EIA-232-E. Of course conformance
to EIA-232 is not relevant above 20 kbps.
5-48
Data Transmission
2.5.2. Conformance to EIA-562
A new standard has recently been introduced in an attempt to provide a low power standard for 5 volt
systems and also to increase the data rate over EIA-232. Known as EIA-562, the standard increase
the maximum data rate from 20 kbps to 64 kbps and facilitates lower driver voltages. The downside
is the reduced noise margin at the receiver. The specification also details the rise time and ripple
conditions of the driver. The SN75LBC187 is fully conformant to this standard.
SN75LV4735; 3.3V EIA-232 PC Interface
Figure 5.22 • SN75LV4735; 3.3V EIA·232·E PC Interface
2.6.SN75LV4735; 3 Volt EIA-232 PC Interface
Continuing the move to lower power systems the obvious choice is to reduce the supply voltage of
the system. Assuming supply current remains constant power dissipation is instantly reduced. The
driving force behind this reduction is once again the notebook type PC equipment To facilitate the
move to 3 Volts, TI has introduced the SN75LV4735. From 3 volts the device is still capable of
producing the required VOH and VOL for conformance with EIA-232.
Once again the device is designed specifically for the DB9S PC DTE interface containing 3 drivers
and 5 receivers for a single package solution.
5-49
1993 Linear Design Seminar
The device is packaged in the TSSOP package with a board area of only 22 mm2 and a maximum
package height of 1 mm.
2.7.ACEs (UARTs) From Texas Instruments
Most EIA-232 systems use dedicated communication controllers. Termed ACEs (Asynchronous
Communication Elements) or UARTs (Universal Asynchronous Receiver Transmitter), these devices
are responsible for controlling the exchange of information over the ElA-232 interface.
The ACE
The ACE is a dedicated asynchronous communications controller designed to off load most of the
communication activities from the CPU, thus freeing the CPU for other activities. It has the ability to
add or delete start and stop bits and provide odd/even parity code generation and detection. Industry
standard devices such as the TL16C450 family contain many extra features as listed below:
•
Programmable bps-rate generator
•
Adds and deletes standard asynchronous communication bit
•
Fully programmable serlalinterface characteristics
•
Data communication diagnostic capabUity
•
Modem-control functions
•
Simple interface to microprocessors
• Maximum data rate of 256 k bits per second
All devices are designed using Texas instruments EPICTM CMOS process and operate from a single
5 V supply. The TL16C4S0 is the most common choice for standard PC applications as well as many
other asynchronous serial applications. The TI..16C450, boused in a 4O-pin package, contains all the
necessary facilities for implementing a single asynchronous serial port The CPU within the system
can read and report on the status of the ACE at any point in the ACEs operation. Reported status
information includes the type of transfer operation in progress, the status of the operation, and any
error conditions encountered, parity, overrun etc.
The TI..16C450 ACE includes a programmable, on-board, bps-rate generator. This generator is
capable of dividing a reference clock input by divisors from 1 to (216 -1) and producing a 16 x clock
for dividing the internal transmitter logic. Provisions are included to use this 16 x clock to drive the
receiver logic. Also included in ~e ACE is a complete modem control capability and a processor
interrupt system that may be software tailored to the user's requirements to minimise the computing
required to handle the communications ~. The TL16C451 is similar to TI..16C450 with the single
serial port, but also contains a Centronix parallel printer port The mM PC ATIXT sets the standard
for this parallel printer interface that all "compatible" manufactures have to follow. Tn.-level
signals are presented on a 25-pin D-type socket Apart from the choice of connector, this parallel
printer port is directly compatible with the "Centronix" standard printer interface. The TL16C452
has two serial ports plus a parallel Centronix printer port Using this ACE together with two
SN75C185s provides a simple three chip complete solution for the two EIA-232 ports plus a printer
port that is common on basic PC configurations.
5-60
Data Transmission
EPIC is a trademark of Texas Instruments Incorporated
The ACE Family from Texas Instruments
Aysnchronous Communications
Elements
•
•
•
•
•
TL16C450
TL16C451
TL16C452
TL16C550B
TL16C552
SeriaI/Parallel Conversion
Buffering
Baud Rate Generation·
Handshaking
Start/Stop Bits
Single Serial Pori
Single Serial Port WIth Centronix Parallel Printer Port
Dual Serial Pori With Centronlx Parallel Printer Port
Single Serial Pori With Two 16-Byte 1/0 FIFOs
Dual Serial Pori With Two 16-Byte FIFOs and Centronix Parallel
Printer Pori
Figure 5.22.1 - The ACE Family from Texas Instruments
2.7.1. The FIFO (First-In-First Out)
The CPU can send data at much faster rates than a normal ACE can handle. This is particularly true
for today's multitasking applications that demand high performance microprocessors. This can be
expensive in CPU overheads as the'CPU will be tied to the speed of the serial interface, i.e., data will
be transferred over the interface through the ACE and onto the CPU bus. This is true also when the
data is exchanged from the CPU to interface via the ACE.
Devices like the TL16C550B and TL16C552 alleviate this problem by including buffer registers and
FIFOs in series with the ACE's transmitter and receiver. These are quick access registers that hold
data until the CPU can be freed. The CPU can then execute a block read or write.
The ACE is, in effect, isolated from the slow communications channel.
The 1L16C550B is similar to the 1L16C450, but two 16-byte FIFOs are included to buffer the
transceiver and receiver data stream, further reducing the number of interrupts from the
microprocessor.
5-51
1993 Linear Design Semlnar
2.7.2. Forward-Looking Performance With Backward Compatibility
By allowing two modes of operation, the TI..16C550B allows users to maintain software
compatibility with earlier industry standard ACEs such as the TI..16C450. In addition to the
TI..16C450 mode, the TI..16C550B can operate in the FIFO mode. In FIFO mode, two 16-byte FIFOs
(First-In-First-Out) are enabled to relieve the CPU of excessive software overheads. The independent
receive and ttansmit FIFOs act as buffers, vastly reducing the number of interrupts required.
Furthermore two dedicated pins serve as handsbaking lines to a DMA (Direct Memory Access)
controller, thus allowing the FIFOs to load and unload data without direct intervention from the
CPU.
The flagship of the range is the TI..16C552, which is similar to the TI..16C452 in structure but with
the added advantage of input/output FIFOs as in the TI..16C550B
This device serves two serial input/output interfaces simultaneously in either microcomputer or
microprocessor-based systems. In addition to its dual asynchronous serial communication
capabilities, the TI..16C552 provides a fully bi-directional parallel data port that fully supports the
parallel Centronix-type printer. The parallel port and the two serial ports provide mM PC/AT
compatible computers with a single low-power device to serve the three-port system. Like the
TI..16C550B, the TI..16C552 contains 16-byte receive and transmit FIFOs that act as buffers to
reduce the number of interrupts on the CPU. Also in common with the TI..16C550B, the device
contains two pins for each ACE that serve as handshaking lines for DMA control. The TI..16C552 is
housed in a 68-pin plastic-leaded chip carrier, PLCC.
Integration of FIFO and DMA signalling circuitry onto a single chip makes the TL16CSSOB
and TLI6CSS2 one of the most efficient solutions for higher performance multitasking
systems.
Data Transmission
TL16C550B; Interfacing to the SN75C185
Alternate
XTAL Control
............_It--i XOIJT
en
~~I-+-~~----~~~~~ ~
III
I~I~I~---+----------~~--
~
I-----+--------~~~-- ~
TL16C550B
Figure 5.22.2 - TLI6C550B; Interfacing to the SN75CI85
2.7.3. Interfacing Between the TL16CS50B and the SN75C185
The circuit shown demonstrates the simplicity, in hardware terms, in implementing an asynchronous
serial interface with the SN75C185 driver/receiver and the communications controller 1L16C550B.
When interfacing between the 1L16C550B ACE and the Intel CPU bus, minimal glue logic is
required. Namely an 'LS245 Octal bus transceiver is used to provide drive current to an 'off-card'
CPU, and programmable array logic (pAL) to decode address lines and generate a chip select signal.
While an exhaustive description of this interface is beyond the scope of this section, a discussion of
key interface lines can be useful.
XinlXout:
External clock. Connects the ACE to the main timing reference (clock or crystal).
baudout ,RCLK:
The transmitter reference clock is available externally via the baudout pin. In this application
bpsout is fed into the receiver clock to provide a timing reference for the receiver circuitry. Clock
5-53
1993 Linear Design Seminar
rate is established by the reference oscillator clock frequency (xio) and divided by a driver specified
by the bps generator divisor latches.
TXRDY:
Transmitter Ready Output. This pin is used during DMA signalling.
RXRDY:
Receiver Ready Output. This pin is also used during DMA signalling.
DO to D7:
Databus. Eight 3-state data lines provide the bi-directional path for data, control, and status
information between the ACE and CPU bus.
RDl,RD2:
Read inputs. When either input is active (high or low respectively) during ACE selection, the CPU is
allowed to read status information from the selected ACE register. Since only one of these inputs is
required for the transfer of data during the read operation, RD2 is tied to its inactive state, i.e., low.
DCD, DSR, SIN, RTS, SOUT, CTS, DTR, RI:
These signals are the EIA-232 compatible modem control lines. Devices such as the SN75C185 are
employed to convert the TILlCMOS level signals from the ACE to EIA-232 compatible bipolar
voltages of between ±5 V to :I:15 V. The signal can then be transmitted over distances of up to 15 m.
The advantages of the SN75C185 can be clearly seen by the simplicity of the interface connections.
For example. driving/receiving combinations precisely match the interface requirement, plus the pinout is aligned directly to the DB9S connector.
WRl, WR2:
Write inputs. A logic applied to WRI, during ACE selection allows the CPU to write either control
words or data into a selected ACE registers. WR2 is tied in active, i.e.: logic low.
INTERRUP'f:
When active (high) the interrupt pin informs the CPU that the ACE has an interrupt to be serviced.
This interrupt could occur for one of four reasons;
•
Receiver error
•
Received data available or time-out (FIFO mode only)
•
Transmitter holding register empty
• Enable modem status Interrupt
The interrupt is reset (deactivated) either when the interrupt has been serviced or by a master reset
(MR).
MR:
Master reset. When active (high), MR clears most ACE registers and sets the states of various
outputs (i.e. interrupt).
5-54
Data Transmission
CSO, CSt, CS2:
Chip Select An active low on the CS2 pin selects the ACE. CSO and CSI must be tied active
(high) to ensure proper functioning of the CS2 chip select. A logic high on CS2 will de-select the
ACE.
AOtoA2:
Register Select These three inputs are used during read or write operations to select the appropriate
ACE registers. For example, providing the correct write/read operation had taken place at logic 0 at
A2, AI, and AO would cause the receiver buffer (read) or the transmitter buffer to write.
ADS:
Address strobe. An active low on ADS, the register select signals (AO TO A2) and chip-select
signal (CS2) drive the intemallogic directly.
2.S.EIA-232 Products Summary
In this section we have discussed devices which are concerned primarily with the DB9S connector.
TI also has a wide range of other EIA-232 ICs which offer differing combinations of drivefS and
receivers which can offer the optimum solution for your system. The reader is advised to consult the
current edition of Interface Circuits Data Book (Reference SLYDO(6) which contains a complete
selection guide ofEIA-232 products.
,
5-55
1993 Linear Design Seminar
2.9.EIA-232 Selection Guide
Data Transmission Circuits
Line
Driver
Line
Receiver
Continued Over••••••
5-66
4
4
SN75154
SN55189
SN75189
SN55189A
SN75189A
SN65C189
SN65C189A
SN75C189
SN75C189A
Indu~ standard
-55°C to 125°C temperature ranJ!;e
Industry standard
-55°C to 125°C temperature ran~e
-55°C to 125°C temperature range
-40°C to 85°C tem~ure ranjte
-40°C to 85°C temperature range
Low-power BiMOS
Low-power BiMOS
nata Transmission
Data Transmission Circuits (Continued)
Control Circuits
Notes
+ ACE: Asynchronous Communications Element.
§ FIFO: First In First Out
¥ Product currently under development, con1act TI representative for further details.
5--57
1993 Linear Design Seminar
3. Interface Circuits for RS-485
3.1. The Need for Balanced Transmission Line Standards
This section focuses on industry's most widely used balanced transmission line standard, the EIA
RS-485. After reviewing key aspects of the standard, the reader will be introduced to the
practicalities of implementing a differential transmission scheme based on a factory automation
example. Finally, new additions to Texas Instruments EIA product range will be discussed along
with their application, where appropriate.
Data transmission between computer system components and peripherals over long distances and
under high noise conditions, usually proves to be very difficult if not impossible with single-ended
drivers and receivers. Recommended EIA standards for balanced digital voltage interfacing provide
the design engineer with a universal solution for long line system requirements.
RS·48S is a balanced (differential) digital transmission line interface developed to incorporate and
improve upon the advantages of the current-loop interface and improve on the EIA-232 limitations.
The advantages are;
•
Data rate· to 10 Mbps and beyond
•
Longer Une length. up to 1200 metres
•
Differential transmission· less noise sensitive
3.1.1. Application Areas
RS-485 is an upgraded version of RS-422-A extending the numberofperipherais and terminals that a
computer can interface to, particularly where longer line length or increased data rates are called for.
Additionally, RS-485 allows for bi-directional multi-point party line communication and can
effectively be used for "mini-LAN" applications, such as data transmission between a central
computer and remote intelligent stations. For example, between point of sales terminals and a central
computer for automatic stock debiting.
As a result of its versatility an increasing number of standard's committees are embracing the RS-485
as the physical layer specification of their standard. Examples include the ANSI (American
Nationals Standards Institute) Small Computer Systems Interface (SCSI) which we will discuss in
section 4, the Profibus standard, the DIN Measurement Bus.
5-58
Data Transmhlsion
3.1.2. EIA RS-485
The balanced transmission line standard EIA RS-485 was developed in 1983 to interface a host
computer's data, timing or control lines to its peripherals. The standard specifies the physical layer
only. Protocols, timing, serial or parallel data, connector choice are all left to be defined by the user
RS-485 Specification Highlights
RS -485
1200
1200
•
Up to 32 Unit Loads (typ)
•
Half Duplex communication
• Protocol Not Included in Spec.
Maximum Common Mode Voltage
Receiver Input Resistance
-7Vto + 12V
12 k.Q
Driver Load
SOO
Driver Output Short Circuit Limit
150mAtoGND
250 mA to -7 Vor 12 V
Figure 5.23 • RS·485 Specification Highlights
RS-485 was originally defmed as an upgrade and more flexible version of RS-422-A. Where RS-422
facilitates simplex communication only, RS-485 allows for multiple drivers and receivers on a single
line facilitating half-duplex communication. Like RS-422 the maximum line length is not specified
but, based on 24 AWG cable, is nominally around 1.2 km. Maximum data rate is unlimited and is set
by the ratio of rise time to bit time, similar to EIA-232. In many cases it is the line length of the
cable which limits the data rate more than the drivers due to transmission line effects. see section 1.
The differences between the RS-485 standard and the RS-422 standard lie primarily in the features
that allow reliable multi-point communications.
5-59
1993 Linear Design Seminar
3.1.3. RS-485 Driver features
i.
One driver can drive as many as 32 unit loads (one unit load is typically one passive
driver and one receiver).
ii. The driver output, off-state, leakage current should be 100 pA or less with any line
voltage from -7 V to +12 V.
iii. The driver should be capable of providing a differential output voltage of 1.5 V to 5 V
with common-mode line voltages from -7 V to 12 V.
iv. Drivers must have self protection against contention (multiple drivers contending for
the transmission line at the same time).
3.1.4. RS-485 Receiver features
i.
High receiver input resistance, 12 ill minimum.
ii.
A receiver input common-mode range of -7 V to 12 V.
iii.
Differential input sensitivity of ±200 mV over a common-mode range of -7 V to
12V.
3.2.Process Control Design Example
To fully understand the considerations of designing an RS-485 system it is advantageous to take a
specific design example. In this case we will consider a factory automation system with a host
controller and several out-stations. Each out-station is capable of transmitting as well as receiving
data.
The general system specification is shown in Figure 5.24 and comprises:
i.
Furthest out-station is 500 m from the host controller.
Ii.
We require up to 31 out-stations on the line. With the host controller this totals 32
stations in total.
iii.
System data rate will be 500 kilobits per second.
Iv.
Only one cable will be used for data transmission operating in half duplex mode.
With this system specification the main design consideration are:
I.
Line Loading including termination.
II.
Cable choice
iii.
Signal Attenuation and distortion
Iv.
Fault Protection including fail safe operation
Consider each one of these points:
5-60
Data TransnUssion
Process Control Design Example
HOST
SYSTEM
,
""
"
II
II
Station
One
Station
Two
",
II
Station
.. n
System Spec:
Considerations:
• Signal Attenuation
• 500 m Furthest Station
• Line Loading
• 32 Stations
• Cable Choice
• 500 kbps
• Fault Protection
• Asynchronous Half Duplex
Communication
Figure 5.24 - Process Control Design Example
3.3.Line Loading
The RS-485 standard takes into account the need for line termination and the subsequent loading on
the transmission line. The decision on whether to terminate or not will be system dependent and will
be affected by the choice of line driver and the maximum line length.
Line Termination
As we discussed in section 1 the test for whether a transmission line is to be considered as a
distributed parameter model or a lumped parameter model is dependent upon the relationship of
signal rise time, tr. at the receiving end and the propagation time of the signal down the cable. The
threshold between the two types of transmission line is given by the following equation:
2tpd
=tT
If we build a margin of error into this equation a better test is to determine the relationship of twice
the rise time to 5 times the propagation delay:
5-61
1993 Linear Design Seminar
If the relationship
2 tpd ;::: 5tT is true then the transmission line must be treated as a distributed
t
parameter model and terminated accordingly. If the converse i.e. 2 tpd;::: ; is true. the transmission
line can be treated as a lumped parameter model and termination is not necessary.
The Unit Load Concept
RS-485 Standard
•
Specifes up to 32 Unit Loads
Doubly Terminated with 120 a
•
Unit Load =Load which Allows
1 rnA of Current Flowing Under a
Maximum Common Mode Voltage
Stress of 12 V & -7 V
DE -------,
DUT
Example
'ALS176B
SN75ALS176B .............. (30 Mbps Transceiver)
RE
IL
-----"-I
= 1 rnA @ 1 2 V (worst case)
Receiver Enabled
UL =...:1-= 1 UL
1
i.e 32 = 32 Transceivers/Transmission Line
Figure 5.25 - The Unit wad Concept
To determine tr tests must be carried out on the transmission cable. For the purposes of this example
we chose a low cost non shielded, twisted pair cable - 500 m of a Belden type 8205 cable as supplied
by RS Components Ltd of the UK, reference number 360-964. On the driving and receiving ends we
connected a SN75ALS176 single channel transceiver. The rise time at the receiver end measured :
tr =0.9 ~ to the 10% and 90% points.
Assuming a propagation delay down the line of 5 ns/m, the time tpd = 500 x 5 = 2500 ns or 2.5 ~.
so in this case:
5 tr = 4.5 Jls and 21pd = 5 Jls, so 2 tpd > 5 tr and therefore the transmission line should be
considered as baving a distributed parameter model and consequently must be terminated in its
5-62
Data Transmission
characteristic impedance. In this case as we are using half duplex transmission the line must be
terminated at the furthest ends.
To determine the characteristic impedance of the cable we used the technique described in
section 1.5.4. Zo in this case measured at 100 O.
The Unit Load Concept
The maximum number of drivers and receivers that can be placed on a single RS-485
communication bus depends upon their loading characteristics relative to the definition of a unit load
(U.L). RS-485 recommends a maximum of 32 unit loads per line.
Signal Attenuation
Attenuation In 24 AWG Twisted
Pair Cable
• DC Resistance Plus Skin Effect
• Non Linearity Due to Proximity
and Radiation Loss
• Details Normally Provided by
Cable Manufacturers
en
i
~
o
~
0.1
m
"0
I
-.L
_
Maximum Allowable
Attenuation
5
ti::J
c:::
0.01
G)
~
6 dBV Measured at Receiver
(Half Driver Output Voltage)
0.001
1K
10K
100K
1M
10M
Frequency
Figure 5.26 - Signal Attenuation
One UL (at worst case ) is defined as a load that allows 1 rnA of current under a maximum
common-mode voltage stress of 12 V. The loads may consist of drivers and/or receivers but does not
include the termination resistors, which may present additional loads as low as 500 total for doubly
terminated lines.
The example in Figure 5.25 shows a unit load calculation for the SN75ALS176B. Since this device is
internally connected as a transceiver, i.e. driver output and receiver input connected to the same bus,
it is difficult to obtain separate driver leakage and receiver input currents. For this calculation
5-63
1993 Linear Design Seminar
reference is made to the receiver input"resistance, 12 ill, giving a transceiver current of 1 mA. This
can be taken to represent 1 U.L. which will allow up to 32 devices to be connected to the line.
Obviously it may be possible to connect more devices than the RS-485 recommendation, but this is
at the designer's risk.
3.3.1. Signal Attenuation
Section 1.3 discusses attenuation in more detail but a sufficient rule of thumb is where the
attenuation of the line reduces the driven signal by no more than 6 dBV. Attenuation figures are
usually supplied by cable manufacturers. The curve in Figure 5.26 shows the attenuation curve
versus frequency for 24 AWG cable. For 500 metres of cable and using the 6 dBV figure, the
maximum attenuation we can tolerate is 0.35 dBV/30 metres. In this case the 500 kbps data rate
attenuation is well within this limit. The attenuation of the fundamental frequency and higher
frequency components of the signal up to 10 Mbps will still be detectable at the receiver. This effect
coupled with the the variation of signal velocity with frequency (termed dispersion) results in
distortion of the pulse at the receiving end of the line.
RS-485 Signal Distortion vs Data Rate
receiving end
500ns/Div
200 "ns/Div
0% Jitter
5% Jitter
TEST CONDITIONS
• 20 AWG Non shielded twisted pair
cable. (Belden reference type 8205) .
• 500 Metres
100 ns/Div
• Doubly terminated with 100 n
• SN751768 type transceiver at both ends.
50% Jitter
Figure 5.27 - RS-485 Signal Distortion
VI
Data Rate
Da~
Transmission
3.3.2. Signal Distortion Vs Data Rate
The simplest way to determine the effects of random noise, jitter, attenuation, dispersion, on the inter
symbol interference is by the use of eye patterns. For information on how to set up eye patterns, refer
to section 1.4 of this Section. Figure 5.27 shows the distortion of the signal at the receiving end of
500 metres of 20 AWG twisted pair cable at different data rates. Using the system constraint of
500 kbps, we see the distortion is limited to the rounding of the signal pulse. If the data rate is
increased further, the effects of jitter then become noticeable. In this case at 1 Mbps we begin to
observe 5% jitter. At 3.5 Mbps we start to loose the signal completely and the quality of transmission
is severely degraded. The maximum. allowable jitter in a system should be limited to 5%. The causes
of jitter are discussed in more detail in section 1.4.2.
Input Protection for Noisy Environments
Ar
SN75ALS176
A
D
Z1
ArDRo
12V
R
Z3
4
1200
Ai .. R2 = PTC Resistor
Z1 =Z2= BZX85 Rated@12V
DE
Z3 = Z4 = BZX 85 Rated @ 6.8 V
Figure 5.28 • Input Protection for Noisy Environments
3.3.3. Fault Protection and Fail Safe Operation
Fault Protection
Factory control applications generally require protection against excessive noise voltages. The noise
immunity afforded by the differential transmission scheme, and in particular the wide common mode
voltage range of RS-485 can be insufficient Protection can be accomplished in a number of ways,
5-65
1993 Linear Design Seminar
the most effective being tbrough galvanic isolation which we will discuss later. Galvanic isolation
provides system level protection .but does not necessarily limit the voltages indcued on the
transmission lines with respect to the RS-485 driver/receiver grounds. This can be accomplished by
the use of protection diodes.
Figure 5.28 shows how external diodes offer transient spike protection for the SN75ALS176 RS-485
transceiver.
RT is the usual termination resistance and is equivalent in value to the characteristic impedance of
the line. Positive Temperature Coefficient resistors, R 1 and R2, provide current limiters for the
diode chain. Provided their ambient temperature resistance is kept below 50n they will be
transparent during normal usage and will not alter the termination value or attenuate the driver
output voltage.
ZI and Z2 are chosen to protect the input from positive spikes greater than 12 V whilst Z3 and Z4
protect the device from negative going spikes greater than -6.8 V.
Fail Safe Operation
The feature of fail safe protection is also a requirement in many RS-485 applications, however its
usefulness needs to be considered and understood at an application level.
The Need For Fail Safe Protection
In any party line interface system, with multiple driver/receivers, there will be long periods of time
when the driving devices are in-active. This state known as line idle and occurs when the drivers
place their outputs into a high impedance state. During line idle, the voltage along the line is left
floating, i.e. indeterminate - neither logic high or logic low. As a result the receiver could be falsely
triggered into either a logic high or logic low state, depending upon the presence of noise and the
polarity of the floating lines. This is obviously undesirable as the circuitry following the receiver
could interpret this as valid information. The receiver should be able to detect sucb a situation and
place its outputs into a known, and pre-determined state. The name given to methods which ensure
this condition is called fail safe. An Additional feature wbicb a fail safe should provide is to protect
the receiver from sborted line conditions whicb can again cause erroneous processing of dataandlor
receiver damage.
There are several ways implement a fail safe, including a hard-wired fail safe using line bias
resistors or protocols. Protocols, although complicated to implement, are the preferred method.
However since most system designers, hardware designers in this case, prefer to implement such
functions in hardware a bard-wired fail safe is often implemented.
A bard wired fail safe should provide a defined voltage across the receiver's input regardless of
wbether the line is shorted to either supply rail or is left open circuited. The fail safe should also be
incorporated into the line termination if present wben at the extremes of the line.
Internal Fail safe
Manufacturers have gone part way to facilitating fail safe design by including some form of open
line fail safe circuitry within the integrated circuits. Unfortunately, due to power consumption
constraints, the extra circuitry has proved of little use. The extra circuitry is quite often just a large
pull-up resistor on the non-inverting receiver input, and a large pull-down resistor on the inverting
5-66
Data Transmission
input of the receiver. These resistors are normally in the range of 100 ill, and so when used in
conjunction with line termination resistors to form a potential divider, only a few millivolts are
generated. As a result this voltage (receiver threshold voltage) is insufficient to switch the receiver.
To use these internal resistors effectively means no line termination resistors can be used, which
reduces the allowed reliable data rate enormously.
Short/Open Circuit Fail Safe
SN75ALS180 With Short Circuit
and Open Circuit Fail Safe
As Seen By Driver Output
vee
As Seen at Receiver Input
•
Cannot Implement Short Circuit
Fail Safe With SN75176 Type
Transceiver
Figure 5.29 - Short/Open Circuit Fail Safe
External Fail safe-Open Line Conditions
A more reliable way of offering open line fail safe is to use external pull-up and pull-down resistors.
There two basic ways of doing thiS; one way is to polarise the line with the pull-up/pull-down
resistors and use these resistors to match the line impedance. Another way is to use larger polarising
resistors while using an extra resistor to terminate the line. The first idea has one advantage in that it
provides a low impedance path to an
ground, so that any currents induced on to the line have a
low impedance path to ground. However a problem is encountered with this method because the
driver output now has to drive very much lower impedance's. If the driver output current capability
is poor the device could easily go into output short circuit current limit. The second way, although
requiring an extra resistor will not load the driver's output to such an excess.
ac.
Placing external pull-up and pull-down resistors R 1 on the non-inverting and inverting inputs of the
receiver will produce open circuit fail safe. Terminating the transmission line with its characteristic
5-67
1993 Linear Design Seminar
impedance, Zo, produces a potential divider between 2R1 and
line, V oc, equals
Zo.
The voltage formed across the
Devices meeting the RS-485 receiver threshold voltage specifications require Voc to be greater than
200 m V. From this the relationship of R 1 to Zo can be derived:-
With V cc = 5V, Voc = 200mV and Zo = 100 n, yields Rl =·1.2 W.
Biasing the receiver in this way will only provide open line fail safe, it will not provide shorted line
fail safe. However, when using transceivers, like the SN75ALS176, it is not possible to provide
shorted line fail safe configurations, since the driver and receiver share the same
pins. Hence for
devices like the SN75ALS176 this open line configuration is the optimum fail safe available.
Ie.
External Fail safe-Shorted Line Conditions
To implement protection from the shorted line condition, further resistors are required. When the
line is shorted the transmission line's impedance goes to zero and the termination resistors will also
be shorted. Putting extra resistors in series with the input to the receiver can provide shorted line fail
safe protection.
The extra resistors, R3 in Figure 5.29, can only be added when using devices with separate driver
outputs and receiver inputs. So intemally wired transceivers cannot be used to offer shorted line fail
safe. If this fonn of protection is required then a device such as the SN75ALSI80, with its separate
driver outputs and receiver inputs, should be used. If a transceiver type device was used then the
extra resistors R3 would cause extra attenuation of the output signal. The 'ALS180 will have its
driver outputs fed directly to the line, bypassing resistors R3.
Calculating the Resistor Values
If the line became shorted then R2 would be removed leaving a voltage across the receiver inputs
of:-
For RS-485 applications the standard specifies Vrx to be greater than 200 m V. So
Data Transmission
Vex = Vth = 200 mV.
Using this figure, along with the minimum permissible supply voltage for the devices gives a
relationship between Rl and R3.
When the line goes into a high impedance state the receiver will see the two R3 in series with R2
plus the two R 1's pulling up and down on either input. The receiver input voltage will now be:
Relating this new Vex to the minimum specified in the standard, V th, gives:
=
=
Where
ex is the ratio of
The transmission line will see an effective line termination resistance of R2 in parallel with twice the
sum of Rl and R3. This should match the transmission line's characteristic impedance, .Zo.
therefore
Zo
-2R
Rl + R3
- 2X2Rl +R2+ 2R3
( )
e
Combining equations (a), (b) and (e) yields the following equations for RI' R2 and R3:-
Rl
=
=
Zo
x
5-69
1993 Linear Design Seminar
=
In this application assuming the supply voltage is 4.5 V and Vth 200 mV with an a value IX of 1.5
and driving a line with characteristic impedance of 120 n yields the following values:-
R1
=
2.2kn
=
1200
=
1100
The values of R1, R2, and R3 only apply for receivers at the extreme of the line; if there are more
receivers on the line then fail safe can be accomplished by multiplying the values of R1 and R3 by
half of the number of receivers on the line. This is done by assuming the input stages of all the
receivers are the same, all R1 resistors are the same, and that all R3 resistors are the same Since all
of R1 and all of R3 resistors will be in parallel, their overall resistance will be divided by half the
number of receivers. If there is a large number of receivers on the line there is a danger of R3
becoming too large and forming a large potential divider with the input resistance of the receiver,
normally around 12 ill.
3.3.4. Galvanic Isolation
In the previous sections the need for line termination, receiver fail safe and noise protection was
highlighted. All these elements can be found in an industrial process control and data collection
application, which is shown in Figure 5.30.
The capability of meeting toughened noise legislation is a key requirement for many new end
products and appli'1ltions. Computer and industrial serial interfacing are areas where noise can
seriously affect the integrity of data transfer, and a proven route to improved noise performance for
any interface system is galvanic isolation.
Such isolation in data communication systems is achieved without direct galvanic connection or
wires between drivers and receivers. Magnetic linkage from transformers provide the power for the
system, and optical linkage provides the data connection. Galvanic isolation removes the ground
loop currents from data lines and hence the impressed noise voltages which affect the signal are also
eliminated. Common mode noise effects can be completely removed and many forms of radiated
noise can be reduced to negligible limits using this technique.
For example consider the case in a process control system where the interface node, shown in Figure
5.30, connects between a data logger and host computer via the RS-485 link:. When an adjacent
electric motor is started up, a momentary difference in ground potentials at the data logger and the
computer may occur due to a surge in current. If no isolation scheme is employed for the data
communication path, data may be lost during the surge interval and in the worst case damage to the
computer could occur.
Circuit Description
The schematic shown forms an interface, one node, for a "distributed controlling, regulation and
supervision (DCRS) system". Such a scheme could be used in a process control type application.
Transmission takes place via a 2-wire bus, formed by a twisted-pair, shielded cable connected in a
ring circuit.
5-70
Data Transmission
capability. Low power is crucial in this type of application since many remote outstations will either
be battery operated or require battery back-up capability.
Transceiver protection circuitry is formed by Zl, q, Z3 and Z4 along with current limiters PTCl
and PTC2 (see previous example). Line termination is formed by a combination of RT> Rl and R2'
The values of which can be calculated as follows;
Rl =R2 < 0.5 xZox [1 + VcdVTH]
and
RT =Zo [1 + V THNcc1
The bus driver used is the SN75LBC176, chosen for its low power consumption and high data rate
Using a cable with a characteristic impedance of Zo = 120 0 and a desired VTH of 200 mY,
requires R 1 =R2 to be around 1.6 leO in value. The terminating resistor, RT would be in the order of
1240.
Process Control with SN75LBC176
Vee -
1XD
.....-::-:-:-=:::=~~=~====4i=i::--.,.- ISaVee
ISOVcc - Galvanically Isolated
Supply.
Vee
= System Supply
RXD
]
Figure 5.30 Process Control SN75LBC176
The inclusion of R 1 = R2 provides a receiver fail safe to open line conditions by biasing the polarity
of the line to a logic '1' ~nder line idle conditions. The values of R 1 = R2 are best kept as low as
5-71
1993 Linear Design Seminar
possible to increase the noise rejection when the line is left floating, but they will place some loading
onto the driver.
Galvanic isolation is afforded by means of three optocouplerslopto isolators. The 6N136 is chosen
for its high data rate capability, tp 75 ns (max), and its high voltage isolation.
=
The 6N136 is designed for use in high speed digital interfacing applications that require high voltage
isolation between the input and output. Its use is highly recommended in extremely high ground
noise and induced noise environments.
The 6N136 consists of a GaAsP light emitting diode and integrated light detector, composed of a
photo diode, a high gain amplifier and a Shottky clamped open collector output transistor. An input
diode forward current of 5mA will switch the output transistor low, providing an on state drive
current of 13 mA (eight 1.6 mA TTL loads). A TTL input is provided for applications that require
output transistor gating.
SN75LBC176; Low Power RS-485
3kO
Nom
l00kO
Nom B Port
Only
1.1 kO
Nom
• Fully Meets EIA Standards RS-485
II Differential-Output Delay time. Too (ns)
II Power Consumption. no load (mW)
TM
• Fabricated Using 2 /..I UnBiCMOS
• High Speed•.••..• >10Mbps
Figure 5.31 • SN7LBC176; Ultra Low Power
Housed in a single 8-pin dUal-in-line plastic package the 6N136 is characterised for operation over
the temperature range of O°C to 70°C. The internal Faraday shield provides a guaranteed common
mode transient immunity of 1000 Vl1s.
A 0.1
5-72
J.lF capacit0r has been connected between Vcc and ground to improve switching performance.
Data Transmission
3.4.SN75LBC176; Ultra Low Power
The key feature of the SN75LBC176 is the very low power consumption, 1 mW. Compare this to the
consumption of the older generation SN75176A, where the quiescent power is as high as 200 mW.
Normally low power consumption signifies a reduction in ac performance. In the case of the
'LBC176 the ac performance is improved over the SN75176A. Data rates of greater than 10 Mbps are
achievable while still being conformant to RS-485. The low power consumption has further benefits
than simply reducing supply current:
3.4.1. Improve MTBF
Although not representing the most glamorous end of the semiconductor design spectrum, reliable
line interface circuits are crucial if the overall system mean time between failure (MTBF) is to be
minimised. System designers have long been aware that often the weak link in ensuing system
reliability has been line interface circuits. This vulnerability is due in part to the circuits close
proximity to the outside world via the edge connector. Consequently interface circuits are
particularly susceptible to failure from high external voltages caused by noise, ESD or incorrect
insertion of cables. For this reason the technology of choice for many Texas Instmments emerging
interface products is LinBiCMOS.
LinBiCMOS, the Technology of Choice
LinBiCMOS is based on TI's highly successful LinCMOS process. LinCMOS is a 3 IJ.Dl pure CMOS
technology with 16 V capability, making it ideal for the design of low power analog products such as
op-amps and analog-to-digital converters (many examples of which are discussed elsewhere in this
book). By shrinking the geometry to 2 IJ.Dl and adding a high performance 30 V bipolar structure, a
new analog merged bipolar/CMOS technology has been produced.
Probably LinBiCMOS's greatest attribute is its modularity. When generating a new technology it is
difficult to achieve a balance between performance and cost, as many "nice to have" features can
make a process too expensive to address a wide range of opportunities.
By making LinBiCMOS modUlar, only the process modules needed to address a particular
application need be used, making it very cost effective. Modules available for LinBiCMOS
include high speed NPNs (with an t;. of 30Hz compared with 500MHz for the standard transistor),
double level metal for better logic integration and current handling, isolated high value polysilicon
resistors and shottky diodes for clamping.
The Applications
With its high voltage capability and excellent switching speed LinBiCMOS is ideal to address
standards such as EIA-232 and RS-485. For example the RS-485 standard, demands that driver
outputs can be shorted to +12V and -7V without damage. This is particularly difficult to implement
as RS-485 devices are designed to operate from a single 5 V supply, meaning that parts of the chip
must be designed to operate well outside its supply rails. Further more the "party line" nature of the
standard requires devices that must be able to withstand contention (multiple drivers accessing the
bus simultaneous) without failure. For this reason short circuit protection and thermal shutdown are
built into the Chip.
5-73
1993 Linear Design Seminar
The standard SN75LBC176 is cbaraterised for commercial temperature range applications. For more
extreme conditions the SN65LBC176 extends the operating range to -40°C to +85°C.
High Speed Full or Half Duplex RS-485
Half Duplex - SN75ALS176B
Full Duplex - SN75ALS180
OE(3)
OE(4)
o
o
(4)
RE(2)
(5)
RE(3)
(6) A
R (2)
R (1)
1
-------'
~--i
(9) Y
(10) Z
=t=2.0 V
First Step Volltage; Vs= Vol + Zoll
Une Impedance Varies With ;
Cable Impedance
Line Loading
1.0
Une Current;
Depends upon termination Scheme
<48mA
100
lime (ns)
200
Figure 5.34 - Single Ended SCSI Termination
4.2.3. Passive and Active SCSI Termination
SCSI termination has traditionally been carried out using passive termination networks. As illustrated
in Figure 5.34 these consist of 2 resistors per signal line ; a 220 n pull up resistor connected to the
termination power source (Termpwr), and a 330 n pull down resistor connected to ground. The
Shottky diode is needed by all termination schemes to protect the power source from reverse
currents.
This type of termination typically results in a maximum line current of around 17 mAo Assuming the
terminator is on a heavily loaded bus, signified by an impedance of approximately 75 n, then the
above equation gives a rust step value of 1.76 V - well short of the desired 2.0 V level.
In addition to this limited current capability and the power consumption penalty imposed by the
resistor dividers, passive terminators also suffer from an unregulated line bias voltage. As a result the
1993 Linear Design Seminar
line voltage will fluctuate with variations in the load current and Termpwr, leading to smaller noise
margins, lower line currents, and reduced data rates.
The most common alternative to passive termination replaces the resistive network with a voltage
regulator in series with a single 110 n resistor per line (fig 4.34). This method, known as Active,
Boulay, or Alternative 2 termination, was developed to overcome two of the main shortcomings of
passive terminatiOB.
TL2218-285 - Current Source Terminator
T12218-285 Enables Single Ended Data Rates of 10 MHz
SCSI I-V CHARACTERISTICS
• 23 rnA Applied at First High-Level Step
• Very Low Output Capacitance, Typically 6 pF
• No External pomponents Required
• Compatible with Active Negation
Ol..-..I-..-i---I..--J'--..I-..-i-.....
-10 5 0
5 10 15
Terminator Current - rnA
20 25
• Thin Shrink Small Outline Package {TSSOP}
4.35 TU2I8-285 Current Source Termination
The 110 n resistors increase the typical line current available on de-assertion to 21 mA, which, from
a transmission line viewpoint, is equivalent to a 35% increase in line impedance. The line current
and the high-level noise margins are also more stable since Termpwr is no longer used to set the bias
voltage directly. Instead it is used to form the input to the voltage regulator, which then provides a
regulated bias voltage.
The 1L-SCSI285 and 'IL2217-285 low dropout regulators from Texas Instruments are specifically
designed for active SCSI termination. With an overall accuracy of 2· % and a maximum dropout
voltage of 0.6V the 1L-SCSI285 is the highest performance dropout regulator available for SCSI
active termination.
5-82
Data Transmission
4.2.4. Current Source Termination Using the TL2218
Although active termination brings a number of advantages to SCSI termination these can be further
improved upon. The TI..2218-285 from Texas Instruments is a completely new type of SCSI
terminator which does just that.
During de-assertion the TI..2218-285 operates as a 23.5 rnA current source which is able to maintain
this current level until the signal reaches the correct SCSI open circuit voltage. At this point the
TI..2218-285 becomes a voltage source of 2.85 V.
The additional current supplied by the TI..2218-285 reduces the low-to-high transition time by
ensuring that each voltage step is consistently the largest possible. The effect of this can be seen in
Figure 5.36, which shows the signal wave forms obtained after using a TI..2218-285, a commercially
available active terminator, and a passive termination network to terminate a 50 n cable (the
equivalent of a heavily loaded bus). Even at 10 MHz the first step voltage of the TI..2218-285
terminated system still exceeds the desired 2.0 V level.
Another feature of the TI..2218-285 is the inclusion of a disable function which allows the terminator
output to be shut down. This is particularly useful for a peripheral which finds itself somewhere other
than the physical end of the bus, and needs some way of easily 'removing' its terminator.
If disabled the TI..2218-285 consumes just 500 J.1A. of current, and maintains an output capacitance of
6 pF. Allowing for the 15 - 16 pF typical output capacitance of a peripherals transceivers, this will
give a total node capacitance well within the 25 pF SCSI limit. An active terminator, on the other
hand, will normally maintain a disabled output capacitance of 10 pF, often leaving the system to
operate outside of the SCSI specification.
Use of the TI..2218-285 also removes two possible causes of system failure or driver damage
associated with active termination .. Firstly the 2% output tolerance of the TI..2218-285 ensures it
does not supply more current than allowed by the driver protecting SCSI limit. The tolerances of the
voltage regulator and the 110 n resistors used in active termination, however, can result in the
terminator supplying in excess of the maximum 24 mAo
The other potentially damaging situation arises when active negation drivers are being used. These
devices sense bus voltages and source sufficient additional current to ensure that first step voltages
reaches the minimum SCSI level. Despite this attractive feature their relatively high cost has limited
their use to ultra fast changing control lines such as ACK and REQ.
To be compatible with active negation drivers it is clear that any terminator connected to the bus
must be able to sink current. Again this is a problem with active termination but not with either the
TI..2218-285 or a passive terminator. The voltage regulator of an active terminator will shutdown
when any driver voltage exceeds 2.85 V. This allows the line voltage to rise and any driver which
then pulls low may sink more than their 48 rnA limit.
5-83
1993 Linear Design Seminar
First High Level Step Comparisons
4
4
Passiv~ T~nn!inatiOn
a
~ JHZ!
2
o
Ii
,-.-
a
2
~
A
o
100nS/div -
3 Metre, 500
3 Metl8,500
4r-1""'""'!--r--r-r-r-....,-.,.-,....,
al-HH-+-+--t-++-+-::l
2 Hi-fI-
TL2218-285
~
o
2
0
1-I-~-1-F+-+-+-!-i
Figure 5.36 - First High Level Step Comparisons
4.2.5. Power Considerations
As well as enabling increased data rates, termination will also increase the power consumption of a
SCSI system. As SCSI has found increased usage in portable or battery powered systems this has
become more important Exactly how much depends upon the method of termination, but not quite
as obviously as might at first be thought.
During data on periods, the power dissipation of each of the SCSI termination methods is very
similar. For an 8 bit bus with all the data lines asserted the power dissipation in each case will be
around 1 W.
During data off periods the position is signifIcantly changed. The resistor dividers of a passive
terminator will still draw around 750 mW of power. Both the TL2218-285 and active terminators,
however, require a total quiescent current of less than 10 mA, providing a 30x saving in power
consumption.
For a single TL2218-285 it is possible to calculate a worst case dynamic power dissipation of
493 mW. This assumes that all nine lines in the package are asserted simultaneously and experience
a 50% duty cycle. In some systems it may be desirable to avoid any single device dissipating this
much power. This can be achieved by partitioning the SCSI bus lines in an appropriate manner. One
5-84
Data Transmission
such method is to split the data lines between the two devices (for an 8 bit system) and also assign
the REQ and ACK lines to separate packages.
Battery powered systems will also benefit from the extended Termpwr range of the 1L2218-285.
Compared to competing solutions which require a minimum Termpwr of 4 volts, the 3.5 V to 5.5 V
range of the 1L2218-285 greatly increases the potential for prolonged operation.
4.3.Differential SCSI
4.3.1. SN7SLBC976DL; Two Chip Differential SCSI
Much debate has taken place on differential versus single ended SCSI for data rates above 5 million
transfers per second (MTps). It is clear however, that for data rates approaching 10 MTps and at line
lengths in excess of 6 metres, differential SCSI is essential.
As we discussed earlier, the standard 8-bit interface is made up of 8 data lines, one parity bit, and 9
control lines, making 18 channels in total. The only differential transceivers capable of transmitting
at 10 MTps data rate have utilised the LS and ALS technologies. Using these technologies and
considering the 18 transceivers per interface the power consumption is quite considerable, 2.4 W
with all drivers disabled. Turn the drivers on and the power consumption rises to nearly 4 W.
From a designers viewpoint, 2.4 watts is a considerable amount of heat to remove from a system.
This is evident in the case of compact hard disk drives where shear equipment size is the limiting
element. A further factor is board area, using one discrete transceiver per channel, i.e. 18 8-pin SO
packages, is unacceptable for many applications.
From a semiconductor designers viewpoint integrating a number of transceivers is of course possible
however the limiting factor once again is power dissipation. The SN75LBC976 is designed to
overcome both the problems of power dissipation and integration. The device incorporates on a
single IC, nine RS-485 configurable transceivers each capable of transmitting at 10 MTps. This is
made possible using LinBiCMOS technology. With all drivers disabled the quiescent power
consumption of the 'LBC976 is a mere 1.5 mW, with all drivers enabled the quiescent consumption
rises to 45 mW, a considerable saving over LS and ALS parts. The package size has also been
reduced to a minimum using the 0.635 mm pitch 56 pin SSOP package which reduces board area
significantly compared with alternate packages such as PLCC. The reader should note that
irrespective of the device power, there is still the relatively high line current The SSOP package has
been thermally enhanced to handle this level of power dissipation. We will cover this point later as
we look at the thermal characteristics of the package.
5-85
1993 Linear Design Seminar
SN75LBC976: Two Chip Differential SCSI
CHANNEL1
~
_
DElRE
I
B+
B-
Implements 'SN75176
Type 'Transceiver
Function for Data
and Control Lines
Implements 'WIred Or'
for Busy, Reset and
Select lines.
• Thermal & Current limit Protection
• >10 Million Transfers Per Second (MT/s)
High Impedance State
for Data bus Driving
• Space Efficient Package (11 X 16 mm Footprint)
• 1.4 rnA Standby Supply Current
Figure 5.37 - SN75LBC976: Two Chip Differential SCSI
The SN75LBC976 is fully coofigurable to facilitate connection to any type of SCSI system
arrangement The 9 channels can be arranged into seven possible channel functions using the BSR,
CDEO, CDEl, CDE2, CRE control pins.
The 7 channel configurations are:
5-86
1.
Transparent, permanently enabled Receiver.
2.
Transparent, permanently enabled Driver.
3.
Bi-directionailransceiver with direction control.
4.
Driver with enable control.
5.
Open ended driver for Wired OR control lines.
6.
7.
Driver with ORed data and enable lines.
Permanent high impedance state.
Data Transmission
Foil
~
"2
~
••
~1-3 Fast Transfer Skew ~~~..
-,.:
:
a:
0
5
I
~:E
~~~
()
1-"
c:
~
'.
'.
•
•
0
~
~
...----.......--""'l1lI
Timing Definitions
DATA
REO!
ACK
JL
J,......-...J
t TXCHIP.SEI1J' I""t
t'
DBn
REO or ACK
:
:
I
•
I
~-o" :~~
m~;;J;
~
0
•
0
:
I: J :
~
0
t-
,
~:~ ~
() Co
~
E
o
DB1
0
I
....
0
~
•
•
:
•
•
"'IJ
SCSI-3 Standard Requirement
tTXCHIP_SETUP· tsK_DRVR. tSK_FOIL = tTXCONNECTOR_SETUP
~ 23 ns
t TXCHIP_HOLD JSK_DRVR.t SK_FOIL = tTXCONNECTOR_HOLD
~ 33 ns
I
~I'D.IJ
tRXCONNECTOR_SETUP=tRXCHIP_SETUP.tSK_RCVR.tSK_FOIL
~ 15 ns
t RXCONNECTOR_HOLD = t RXCHIP_SETUP.t SK_RCVR·t SK_FOIL
~ 25 ns
Figure 5.38 • SCSI·3 Fast Transfer Skew Budget
4.3.2. SCSI and IPI Skew Considerations
SCSI as we have discussed is a parallel data bus. This is also the case with IPI. IPI, an acronym for
Intelligent Peripheral Interface, is similar to SCSI in that it is a high speed peripheral bus with the
same high speed differential interface requirements. By the parallel nature of the interface, both
standards transfer data over the cable more than one bit at a time. SCSI and IPI allow 8·bit (one
Byte) or a 16-bit (one word) data width and transfers as often as once every 100 ns or 10 million
transfers per second.
Since the logical state of anyone bit can change every 100 ns, this defines a period during which the
logical state should be valid across the bus. This is the unit Interval (UI). The voltage transitions
which define the start and end of the VI can propagate along the bus at different velocities due to the
physical differences along each electrical path. So the original UI at the start will be different at the
destination.
Time variation of the defining voltage transitions is typically called skew. The limit for skew,
designated tak(lim) , is the fastest minus the slowest propagation delays along any part of the bus.
This, in effect, will reduce the UI by tak(lim) establishing a minimum unit interval, DImm, that can be
transmitted with a particular data bus.
5-87
1993 Linear Design Semluar
The proposed SCSI-3 standard for fast transfers (10 MTps), defines U1uuD in terms of set-up and hold
times at the SCSI connector for inter-operability with any other SCSI device. At the time this
document is being written the requirements are as shown in Figure 5.38.
The budget behind the conneetor is left to the designer imd depends upon the SCSI controller,
transceivers, and layout being used. The table shows some skew budget examples with various
controller chips that would comply with the requirements at the SCSI connector. The column under
'Ree' (for recommended) is data for the worst case number for SCSI controllers surveyed by the SCSI
SPI Working Group and budgets 8 ns for the extemal driver and 9 ns for the eXtemal receiver. This
is the origin of the t"k(lim) specifications in the SN75LBC976 data sheet
Parameter
Vendor
B
35
Vendor
C
35
Units
=
32
Vendor
A
30
min Tx_controller_hold =
42
42
45
45
ns
min Rx30ntrollecsetup =
5
0
5
0
ns
min Rx_controller_hold =
15
20
15
10
ns
t"Letcb=
maxt"Ldvr=
maxt"Iuvc=
1
1
1
1
ns
8
6
11
11
ns
9
4
9
14
ns
min Tx_controllerJetup
Rec
ns
Transceiver Skew Budgets/or Various SCSI Controllers
The time it takes one transceiver of the 'LBC976 to change logic states is called the propagation
delay time. For a driver this is designated as ~D and for a receiver too and does not differentiate
whether the logical transition is from high-to-low or low-to-high level. The t"k(lim) parameter for the
transceiver is nothing more than the maximum difference of the propagation delay times between
any two drivers or any two receivers on any two devices. Compliance to the t"kQim) specifications of
the data sheet and the recommendation of the SCSI standard is assured by measuring the propagation
delay time of each channel of each 'LBC976 and accepting only those devices within the t"k(lim)
band. To keep the production costs of the 'LBC976 reasonable, this testing is done at 25°C and at
70°C ambient temperatures at a Vcc of 5 volts.,
Admittedly, the die temperatures and supply voltage are all the same (or nearly the same) during TI's
production testing and not necessarily the same would be seen in actual use. However the sensitivity
of the propagation delay times to these factors is the same and repeatable from device to device. In
other words, as long as the operating environment of all of the channels of the SCSI interface is
similar, the change in propagation delay times from the data sheet conditions will be the same. This
will maintain the t"kQim) even though the actual propagation delay times may change.
It is nearly impossible to predict the instantaneous die temperatures of these devices in actual use.
Due to the non-deterministic nature of the state of any one channel and the averaging affect of nine
channels and of the package thermal time constant, the die temperature must be considered using the
mean power dissipation. It is also reasonable to assume the mean power dissipation of separate
5-88
Data Transmission
devices on the same printed circuit board to be close to each other and the temperature of the air
around them will not have a large «5°C) gradient between the two. Even if there was an air
temperature gradient of 45°C, there would be only about a 2 ns difference in the driver propagation
delay times and, from recent data, little or no difference in the receiver propagation delay times. If
such a temperature gradient actually existed across a board, it' is likely that skew budgets are not
going to be the problem with the equipment!
In summary:
1.
The designer should detennine the transceiver skew requirements based upon his controller
and board design.
2.
The current specification and testing of 1sk(lim) of the 'LBC976 is, the best compromise for a
cost effective solution.
3.
We have application information from our experience gained through numerous users with no
inter-operability problems detected at the time of writing.
4.3.3. SN75LBC976 Channel Power Dissipation Considerations
Channel Power Dissipation
To understand the SN75LBC976 power dissipation when connected to a SCSI bus and the
subsequent heat sinking requirements, we must develop a realistic model for the power consumption
under working conditions. We must consider the power dissipation within the silicon. There are three
primary sources, the de quiescent power, the ac or switching power, and the de or resistive losses in
the output drivers.
The current necessary to bias the circuits of a single enabled 'LBC976 differential driver is typically
0.53 mA and a maximum of 1.1 rnA. A single enabled receiver circuit requires 3.22 mA typically
and 5.00 mA maximum. The typical values have been measured on 94 SN75LBC976DLs from three
different wafer lots. The maximums have been verified over temperature on the same samples.
It follows the driver quiescent power consumption, Pocc is:
Pocc =lccxYcc
=0.53 mA x 5.00 V =2.65 mW/Channel average
=1.11 mA x 5.25 Y =5.83 mW/Channel maximum
And the receiver quiescent power, PRCC is:
PRCC =lccxYcc
= 3.22 mA x 5.00 Y = 16.10 mW/Channel average
= 5.00 mA x 5.25 Y =26.25 mW/Channel maximum
The average Icc of a representative sampling of the SN75LBC976 has been measured to be 9.77 mA
for nine unloaded drivers switching at 5 MHz (10 Mbps), a 50% duty cycle, and at a 'yCC of 5 Y.
Nine receivers at the same frequency and duty cycle and unloaded outputs consumed 36.0 mA
average. Since both measurements include PDCC or P RCCt they are subtracted below:
5-89
1993 Linear Design SeJDinaJ?
Driver switching losses, POAO at 5 MHz:
POAC + POCC(average)
P OAC
=(lCC(averagef-»
=(ICC(averagef-»
xVCC
x V CC - POCC(average)
=(97.719) x 5.0 - 2.65
=51.6 mW/Cbannel
Receiver switching losses, P RAC' at 5 MHz:
P RAC + PRCC(average)
P RAC
=(ICC(average)l9) x V CC
=(Icc (averagef-» xVCC - PRCC(average)
=(36.0 mAl9) x 5.0 V - 16.10
=3.9 mW/Cbannel .
The output stage losses vary with the magnitude of the output voltages or the output transistor
saturation voltages and with the load conditions. The following is based upon the solution of the
equivalent circuit of a differential SCSI bus and no further proof is included in this analysis.
For the differential driver, the worst case condition is with a driver asserting the line with SCSI bus
tennination and a differential output voltage of about 2 V. Under these conditions there would be
144 mW dissipated in the output transistors when asserted and 71 mW when negated. The average
output voltage of the SN75LBC976 driver is 2 V. As such, the average power dissipated in the output
transistors is also a worst case condition.
Driver output dc losses, POOH is given by:
POOH
=144.0 mW/Cbannel
The same circuit but with the line negated:
POOL
=71.0 mW/Channel
The receiver output stage is rated for sinking 8.0 mA at a maximum low-level output voltage of
0.8V.
Receiver output de losses, PRO' is given by:
PRO
= 8.0 mA x 0.8 V = 6.4 mW/Channel maximum
Since P occ + P OAC = P oo » P RCC + P RAC + PRO' the worst case power dissipation in a data
channel occurs when the driver is enabled and transmittiug data. This case will be used to analyse the
device power dissipation.
Device Power Dissipation
Assuming the probability that anyone bit on the bus is asserted is equal to the probability of being
negated, the state of the output is non-deterministic, and the thermal time constant of the device is
long with respect to the data transfer period, the mean die temperature will be determined by the
mean power dissipation. In the driver output this is the mean of the asserted and negated values:
Mean device output de losses: .
5-90
Data Transmission
= (POOH + PooU/2 x 9 Cbannels
= (144 mW/Ch + 71 mW/Cb)/2 x 9 Channels
=967.5mW
From the assumptions above and the probability that the driver output will change state on the next
cycle is equal to the probability that it will not, the mean power dissipated due to driver switching is
one-half P OAC which was measured with the switching loss occurring every cycle.
Mean device switching losses:
POAC(DEV)
= PoAd2 x 9 Channels
= (51.6mW/Cb)/2 x 9 Channels
= 232.2 mW
Total Device quiescent power:
POCC(DEV)
= POCC(average) x 9 Cbannels
= 2.65 mW/Ch x 9 Channels
=23.85mW
The total mean power dissipated in 9 enabled drivers transmitting over a SCSI bus for several
package thermal time constants is then
PO(DEV)
= Poo(DEV) + POAC(DEV) + POCC(DEV)
= 967.5 mW + 232.2 mW + 23.85 mW
= 1223.6mW
4.3.4. Junction Temperature and Layout Considerations
Measurements of the thermally enhanced 56-pin SSOP package and lead frame used on the
SN75LBC976DL were performed on a 130 mm by 98 mm six layer printed circuit board with the
ground and heat sinking pins soldered to a common solder pad and connected to a second layer
ground plane through one via interconnect, see Figure 5.39. The ground plane was 0.254 mm below
the surface of the board and was a 1 oz copper layer. The results of two tests resulted in 9JA s of 52.9
and 46.6°CIW with zero air flow.
The mean junction temperature rise above ambient when all drivers are enabled and transmitting data
over the SCSI bus for several package thermal time constants can then be calculated.
5-91
1993 Linear Design SemiDar
Thermally Enhanced 56-Pin SSOP Package
•
•
6 Layer PCB
Ground and heat sinking pins
soldered to a common solder pad to the
ground plane O.25mm below
surface
•
Ground plane 1 OZ copper/sqft.
1.3W
t
TJ=150'C
Figure 5.39 - ThermaUy Enhanced 56-pin SSOP Package
Junction temperature rise above ambient:
T 1 - TA = alA x PD(DEV)
=(52.9°C/W + 46.61C/W)/2 x 1233.6"mW xl W/l000 mW
=60.8°C
Most designs require two junction temperature conditions to be met. The junction operating
temperature should not exceed 150°C under worst case operating conditions and the average
operating junction temperature should be no more than 110°C.
Since the worst case condition of all nine channels transmitting data was used for analysis, the
maximum ambient air temperature, TA' with no air flow should be:
TA(maximum)
=150°C - 6O.8°C
= 89.2°C
When evaluating the average operating junction temperature the effects of transmit/receive duty
cycle communication port activity must be taken into account.
5-92
Data Transmission
4.4.Driving the 'Wired-Or' SCSI Lines with the
SN7SLBC976
The control lines of the SCSI bus have three Wired-Or'lines, these are BSY (busy), RST (reset), and
SEL (select). These lines are wired-or in that the line drivers connected to these lines drive in one
direction (assertion) only and are tri-stated (high impedance) when negated. This allows numerous
drivers to be active at the same time without affecting the logic state of the line and requires that all
drivers be released or off before the logical state can change. When tri-stated the bus tennination
network passively negates the signal.
The technique used for wired-or operation with differential transceivers is to input the signal into the
driver enable pin and connect the driver input to a fixed logic level input When the input signal to
the driver enable is active (high), the driver becomes enabled and the outputs drive the SCSI bus to
the state of the driver input. When the input signal at the driver enable pin goes low, the driver turns
off and allows the bus termination to negate the signal on the bus after all other drivers on the bus are
also shut off.
Typical SCSI Transceiver Connections
r
560
If 0 is open-drain
SCSI Connector
+
Active High Bi-Dlrectlonal VO With Separate Enable
r
560
If 0 is open-drain
SCSI Connector
+
Active Low Bi-Dlrect/onal VO With Separate Enable
+
Wired-Or Driver And Active High Input
Wired-OR Driver And Active Low Input
Figure 5.40 - Typical SCSI Transceiver Connections
5-93
1993 Linear Design Seminar
Many communications controllers used for differential SCSI have separate inputs and outputs for
these signals. When used with the SN75176 type RS-485 transceiver. these controller IIOs can be
directly connected to separate driver enable inputs or receiver outputs. The SN75LBC976 device
does not have a separate driver input and receiver input. these are tied together internally to save
pins.
Controllers with separate IIOs can still be used with the 'LBC976 using the connections shown in
Figure 5.40. The controller output will go high and enable the driver and disable the receiver. Upon
disabling the receiver. the external pull-up or pull-down resistor will drive pin A of the 'LBC976 to
the proper level for bus assertion and the driver will assert the SCSI signal line. When the controller
output goes low. the driver disables and allows the termination to negate the bus signal. After a short
delay. the receiver outputs are enabled and will reflect the logical state of the bus Signal.
5-94
Data Transmission
5-95
1993 Linear Design Seminar
5. Summary and Further
Information
S.t.EIA Standards
For copies of the EIA standards please contact the Electronic Industries Association. For details and
a copy of the Catalog of EIA & Jedec Standards & Engineering Publications contact the EIA
Standard Sales office at the following address and telephone number:
EIA Standard Sales Office
2001 Pennsylvania Avenue, N.W.
Washington, D.C. 20006
United States
Telephone Number + 1 (202) 457-4966
5.2. References
The following books were invaluable in producing the Section on data transmission:
1.
Digital, Analog, and Data Communication - William Sinnema & Tom McGovern - PrenticeHall International- ISBN 0-835-91313-9.
2.
Data Transmission - D. Togal and O. Togal- McGraw Hill- 1980
5.3. Texas Instruments - Completing the Picture
The range of products discussed throughout this section demonstrate the commitment made by Texas
Instruments to the field of peripheral interfacing. Use of leadership technologies has enabled the
production of high performance, reliable line drive/receive functions and highly integrated
controllers.
Obviously in a seminar this short it is impossible to cover all TIs data transmission products. The
reader is encouraged to contact a TI representative to obtain the latest data books on transmission
ICs. As a minimum the designer should posses a copy of the Interface Circnits Data Book.
5-96
Data Transmission
Finally, although we have discussed the older standards such as EIA-232 and RS-485 11 is
continuing to work and participate in the various standard defmition committees to ensure new and
emerging standards gain the full support of TI's semiconductor experience. Testimony to this fact has
been the SN75LBC976 RS-485 transceiver, the specifications for which were closely aligned with
the outcome of the work done by the SCSI-3 standards group.
Over the next 12 months 11 will be releasing products in support of Futurebus+, and is actively
supporting the P1394 high speed serial bus Working Group among others.
Texas Instruments Data Transmission
Completing the Picture
Figure 5.41 - Texas Instruments Data Transmission - Completing the Picture
5-97
5-98
6-1
Contents
Page
Ordering Instructions ........................... ~ ......................... 6-3
Mechanical Data ........................................................... 6-5
s::
CD
()
::r
I»
_.
::J
()
-
I»
C
...
I»
I»
6-2
ORDERING INSTRUCTIONS
Electrical characteristics presented in this data book, unless otherwise noted, apply for the circuit type(s) listed in the
page heading regardless of package. The availability of a circuit function in a particular package is denoted by an
alphabetical reference above the pin-connection diagram(s). These alphabetical references refer to mechanical
outline drawings shown in this section.
Factory orders for circuits described in this data book should include a four-part type number as shown in the following
example.
Example:
SN
75189
N
-00
Prefix - - - - - - - - - - - - - - - - - - - - - '
MUST CONTAIN TWO, THREE, OR FOUR lETTERS
SN .......... TI Special Functions or Interface Products
Tl ............................... TI Linear Products
STANDARD SECOND-SOURCE PREFIXES
AM ......................... Advanced Micro Devices
DP or DS .................................. National
IT ............................... Linear Technology
MAX ..................... Maxim Integrated Products
MC ....................................... Motorola
N8T ....................................... Signetics
uA ................................ Fairchild/National
Unique Circuit Description
MUST CONTAIN THREE TO EIGHT CHARACTERS
(From Individual Data Sheets)
Examples:
232
3695
75115
75160B
75C1154
75AlS180
Package
MUST CONTAIN ONE OR TWO lETTERS
D, DB, DW, FK, FN, J, JD, JG, ~I, NT, NS, P, PS, W
(From Pin-Connection Diagrams on Individual Data Sheet)
Instructions (Dash No.)
MUST CONTAIN TWO NUMBERS
-00 No special instructions
-10 Solder-dipped leads (N, NT packages only)
Circuits are shipped in one of the carriers below. Unless a specific method of shipment is specified by the customer
(with possible additional costs), circuits will be shipped via the most practical carrier.
Dual-In-Line (D, DB, Dl, DW, J, JD, JG, N, NT, P )
- Slide Magazines
- A-Channel Plastic Tubing
- Sectioned cardboard box
- Individual Cardboard Box
Chip Carriers (FK, FN, Fl)
- Anti-Static Plastic Tubing
Flat CN)
- Wells Carrier
Dual-In-Line Surface Mount (DR, DBlE, DlR, DWR, NSlE, PSlE)
- Taped and Reeled
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655303 • DAllAS, TEXAS 75265
ORDERING INSTRUCTIONS
Military Data Transmission Nomenclature
Example:
SNJ
55
109A
J
Prefix _ _ _ _ _ _ _ _ _ _ _ _ _ _--',
SN = Standard
SNJ = Class B Processing
Second-9ource Prefix
AM = AMD
MC = Motorola
Operating Temperature Range _ _ _ _ _ _ _ _ _--'
55
95
Military
-55°C to 125°C
= Nonstandard
Unique Circuit Description _ _ _ _ _ _ _ _ _ _ _ _ _--'
Possibly with A or B in Last Positiion
Package Designation _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _--'
FK
J
JG
W
= LCC
C-DIP
= S-Pin C-DIP
Flatpack
TEXAS
..If
INSIRUMENlS
POST OFFICE BOX 855303 • DAUAS, TEXAS 75265
MECHANICAL DATA
0008, 0014, and 0016
plastic small-outline packages
Each of these small-outline packages consists of a circuit mounted on a lead frame and encapsulated within
a plastic compound. The compound will withstand soldering temperature with no deformation, and circuit
performance characteristics will remain stable when operated in high-humidity conditions. Leads require no
additional cleaning or processing when used in soldered assembly.
0008, 0014, and 0016
(16-pin package ueed for lIIustrstlon)
Designation per JEDEC Std 30:
PDSO-GS
PDSO-G14
PDSO-G16
4,00 (0.157)
3,81 (0.150)
9
8
5,21 (0.205)
4,60 (0.181)
0,50 (0.020)
0,25 (0.010)
7°NOM
4Placea
r+-
0,229 (0.0090)
x 45° NOM
0,79 (0.031)
0,28 (0.011)
,
-14-----...
Pin Spacing
0,190 (0.0075)
Jl ~b·
1,12 (0.044)
0,51 (0.020)
1,27 (0.050) (sae Note A)
DIM
~
8
14
18
AMIN
4,80
(0.189)
8,55
(0.337)
9,80
(0.386)
A MAX
5,00
(0.197)
8,74
(0.344)
10,00
(0.394)
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
NOTES: A
B.
C.
D.
Leads are wHhin 0,25 (0.010) radius of true position at maximum material condHion.
Body dimensions do not include mold flash or protrusion.
Mold flash or protrusion shall not exceed 0,15 (0.006).
Lead tips to be planar wHhin ",0,051 (0.002) exclusive of solder.
TEXAS
.If
INSIRUMENTS
POST OFFICE BOX 6S5303 • DAUAS, TEXAS 75265
6-5
MECHANICAL DATA
08008, 08014, 08016, 08020, 08024, 08028, 08030
plastic shrink small-outline packages
These shrink small-outline packages consist of a circuit mounted on a lead frame and encapsulated within a
plastic compound. The compound will withstand soldering temperature with no deformation, and circuit
performance characteristics will remain stable when operated in high-humidity conditions. Leads require no
additional cleaning or processing when used in soldered assemilly.
DBOOB, DB014, D8016, DB02O, DB024, DB028, DB030
Designstlon per JEDEC Std 30:
(24111n package used for Illustration)
POSO-G8
POSo-G14
POSO-G16
POSo-G20
POSo-G24
POSo-G28
POSO-G30
j+-----A------.r
f
2.00-Lt_AX----...0,05 MIN
~
h=:;::::;:::;:::;::;:::;:::;::;;:::;::IQJlAAAP
j L~ Iwl 0.13®1
~~~=====~k
~cJ
~
0,10
~
IJ~
100MAX
0,55
Pin Spacing
ioHoI----
0,65 NOM
(aeeNoteA)
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS
NOTES: A
B.
C;
D.
E.
Leads are within 0,25 mm radius of true position at maximum material condition.
Body dimensions do not include mold flash or protrusion.
Mold or flash end protrusion shall not exceed 0,15 mm.
Interlead flash shall be controlled by TI statistical process control (additional information available through TI field office).
Lead tips to be planar within ,.0,05 mm exclusive of solder.
TEXAS
.If
INSTRUMENTS
POST OFFICE BOX 655303 • DAUAS. TEXAS 75265
MECHANICAL DATA
DL028. DL048. and DLOSS
plastic shrink smail-outline packages
Each of these shrink small-outline packages consists of a circuit mounted on a lead frame and encapsulated
within a plastic compound. The compound will withstand soldering temperature with no deformation, and circuit
performance characteristics will remain stable when operated in high-humidity conditions. Leads require no
additional cleaning or processing when used in soldered assembly.
Designation JEDEC
per
DL028, DL048, II/ld DL066
(48-pln package used for Illustration)
I+-----A------+J
10,67 (0.420)
10,06 (0.396)
I
48
25
P_ ~\o-0,355 (0.014)
0.203 (0.008)
,,,J,"Y!H
,--J.---.I
Pin Spacing 2,54 (0.100) T.P.
(ses Note A)
~~
~ Y~F="""
1,78 to.07O)
MAX
~~
(see Notes B and C)
0,533 to.021)
,
0,381 ,0.015)
22 Places
(see Notes B and C)
ALL UNEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
NOTES: A. Each pin centerline is located within 0.25 (0.010) of itS true longitudinal pOSition.
B. This dimension does not apply for solder-dipped leads.
C. When soIder-dipped leads are specified. dipped area ofthe lead extends from the lead tipto at least 0,51 (0.020) above seating plane.
TEXAS -If
INSlRUMENlS
6-18
POST OFFICE BOX 855303 • DAllAS, TEXAS 75265
MECHANICAL DATA
N028
6OD-mll plastic dual-in-line package
This dual-in-line package consists of a circuit mounted on a lead frame and encapsulated within a plastic
compound. The compound will withstand soldering temperature with no deformation and circuit performance
characteristics will remain stable when operated in high-humidity conditions. This package is intended for
insertion in mounting-hole rows on 15,24 (0.600) centers (see Note A). Once the leads are compressed and
inserted, sufficient tension Is provided to secure the package in the board during soldering. Leads require no
additional cleaning or processing when used in soldered assembly.
N028
Designation per JEDEC Std 30:
PDIP-T28
I"
28
36,6 (1.441) MAX
1
15
==-:E::::::::::::: li~
14
~'r
0,36 (0.014)
0,20 (0.008)
28Placea
(see Notes B and C)
0,533 (0.021)
0,381 (0.015)
28Placea
(see Notes B and C)
1,78 (0.070)
0,76 (0.030)
4 Places
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
NOTES: A Each pin centerline Is located within 0,25 (0.010) of its true longitudinal position.
B. This dimension does not apply for solder-dipped leads.
C. When solder-dipped leads are specified, dipped area of the lead extends from the lead tip to at least 0.51 (0.020) above sealing plane.
TEXAS -If
INSIRUMENIS
POST OFFICE.BOX 855303 • DALLAS. TEXAS 7S265
6-19
MECHANICAL DATA
NS016
plastic package
This package consists of a circuit mounted on a lead frame and encapsulated within a plastic compound. The
compound withstands soldering temperature with no deformation, and circuit performance characteristics
remain stable when operated in high-humidity conditions. Leads require no additional cleaning or processing
when used in soldered assembly.
NS016
Designation per JEDEC Std 30:
PDFP-G16
l~
:r
,
10,5 (0.413)
9,9 (0.390)
UUI
---.j
~~
1,39 (0.055) .
1,15 (0.045)
0,45 (0.018)
0,35 (0.014)
E. .. . ."3L.:l
."".."
5,6(0.220)
2,0 (0.079) MAX
I
0,95(0.037)
0,55 (0.021)
.df
~ .~" .t.
...
8,2(0.323)
7,4 (0.291)
ALL UNEAR DIMENSIONS ARE IN MILUMETERS AND PARENTHETICALLY IN INCHES
TEXAS ..If
6-20
r
0,13 (0.005)
INSlRUMEN'TS
POST OFFICE BOX 655303 • DALlAS, TEXAS 75265
MECHANICAL DATA
NT024
300-mll plastic dual-in-line packages
This package consists of a circuit mounted on a lead frame and encapsulated within a plastic compound. The
compound will withstand soldering temperature with no deformation and circuit performance characteristics will
remain stable when operated in high-humidity conditions. This package is intended for insertion in
mounting-hole rows on 7,62 (0.300) centers. Once the leads are compressed and inserted, sufficient tension
is provided to secure the package in the board during soldering. Leads require no additional cleaning or
processing when used in soldered assembly.
NOTE: For all except 24-pln package, the letter N is used by itself since the 24-pln package may be available in more than one row-spacing. For
the 24-pln package, the 7,62 (0.300) version is designated NT; the 15,24 (0.600) version is designated NW. If no second letter or
row-spaclng Is specified, the package is essumed to have 15,24 (0.600) row-spacing.
Designation per JEDEC Std 30:
NT024
PDIP·T24
1l1li
12
7,37 (0.290)
0,38 (0.015)
14-----111+--7,1 (0.280) MAX
MIN
2,0 (0.080) NOM
t:: 0,25 (0.010) NOM
\\ _ _ _ _ _ SeBling
Plane
(see Notes B and C)
-1 r--~:~fg:g:~
24Places
~K~
~
;
t
4,06 (0.160)
3,17 (0.125)
0,36 (0.014)
0,25 (0.010)
24P1acea
~I
.
~==~~*:::::::::: I
14-----.1- 7,m (0.310)
"=:;-~I:f i
31,8 (1.250)
28,6(1.125)
2, 16 (0.085)
0,71 (0.028)
4 Places
~J ~
0,533(0.021)
0,381
(0.015)
(saa Notes B and C)
-.ll.-J
l
1,14 (0.045) MIN
Pin Spacing 2,54 (0,100) NOM
(saeNoteA)
ALL UNEAR DIMENSIONS ARE IN MILUMETERS AND PARENTHETICALLY IN INCHES
NOTES: A Each pin centerline is located within 0,25 (0.010) of its true longitudinal position.
B. This dimension does not apply for solder-dipped leads.
C. When SOlder-dipped leads are speclfied, dipped area of the lead extends from the lead tip to at least 0,51 (0.020) above seating plane.
TEXAS ..If
INSIRUMENTS
POST OFFICE BOX 655303 • DALlAS, TEXAS 75265
6-21
MECHANICAL DATA
POOS
plastic dual-In-line package
This package consists of a circuit mounted 'on an S-pin lead frame and encapsulated within a plastic
compound.The compound will withstand soldering temperature with no deformation, and circuit performance
characteristics will remain, stable when operated in high-tiumidity conditions. The package is intended for
insertion in mounting-hole rows on 7,62 (0.300) centers. Once the leads are compressed and inserted, sufficient
tension is provided to secure the package in the board during soldering. Solder-plated lead require no additional
cleaning or processing when used in soldered assembly.
POO8
Designation per JEDEC Std 30:
I.
PDIP--TB
10,2 (0.400) MAX
8
j
5
Index Dot
I+----+f- 7,fl7 (0.310)
7,37 (0.290)
8,60 (0.260)
6,10 (0.240)
1,78 (0.070) MAX
8 Places
..
5,08 (0.200)
MAX
Seating Plane
~ Gauge Plane
~ L ~::~~:~~
~\.- 0,36 (0.014)
3,17 (0.125)
MIN
0,20 (0.008)
(see Note B and C)
-.II.2,54 (0.100) T. P.
6 Places
(see Note A)
0,533 (0.021)
0,381 (0.015)
(see Note B and C)
ALL LINEAR DIMENSIONS ARE IN MILUMETERS AND PARENTHETICALLY IN INCHES
NOTES: A Each pin centerline Is located within 0,25 (0.010) of Its true longitudinal position.
B. This dimension does not apply for solder-dipped leads.
C. When solder-dipped leads are spacilied. dipped area of the lead extends from the lead tip to at least 0,51 (0.020) above seating plane.
TEXAS ."
6-22
INSIRUMENlS
POST OFFICE BOX 855303 • DALLAS, TEXAS 75265
MECHANICAL DATA
PS
plastic dual-in-line package
This package consists of a circuit mounted on a lead frame and encapsulated within a plastic compound. The
compound withstands soldering temperature with no deformation, and circuit performance characteristics
remain stable when operated in high-humidity conditions. Leads require no additional cleaning or processing
when used in soldered assembly.
PSOOS
8
5
2,0 MAX
ALL LINEAR DIMENSIONS ARE IN MILUMETERS
TEXAS .If.
INSJRUMENlS
POST OFFICE BOX 855303 • DAUAS, TEXAS 75265
6-23
MECHANICAL DATA
W014
ceramic flat package
This hermetically sealed flat package consists of an electrically nonconductive ceramic base and cap and a lead
frame. Hermetic sealing is accomplished with glass. Leads require no additional cleaning or processing when
used in soldered assembly.
W014
0,152(0.006)
0,076 (0.003)
14 Leads
1r
0,483 (0.019)
0,381 (0.015)
14 Leads
1r
Deslgmitlon per JEDEC Std 30:
GDFP·F14
Base And
Seating
Plane
oooL
-:]~
j4- 1,27 (0.050) NOM
~
-----,r
12 Places
(seeNoteA)
~
M14
1
-
-
.-
I-
f8
(aee Note C)
(0.265)
(0.235)
"-. )
~
2,03 (0.080)
1,27 (0.050)
1,02 (0.040)
0,51 (0.020)
-~I:-
-
7
-
.-
1-
"'r
~ of- 0,25 (0.010)
---+
4 Places
0,64 (0.025)
8,89 (0.350)
8,56 (0.337)
Fall within JEDEC MO-oo4AA dimensions
All UNEAR DIMENSIONS ARE IN MilliMETERS AND PARENTHETICALLY IN INCHES
NOTES: A. Leads ar!! within 0,13 (0.005) radius of true position (T.P.) at maximum material condition.
B. This dimension determines a zon!! within which all body and lead irregularities lie.
C. Index point is provided on cap for termlnalld!!ntificaiion only.
TEXAS~
Eh24
INSIRUMENlS
POST OFFICE BOX 855303 • DAllAS. TEXAS 75265
MECHANICAL DATA
W016
ceramic flat package
This hermetically sealed flat package consists of an electrically nonconductive ceram ic base and cap and a lead
frame. Hermetic sealing is accomplished with glass. Leads require no additional cleaning or processing when
used in soldered assembly.
W016
0,483 (0.019)
0,381 (0.016)
16Leada
0,152 (0.006)
0,076 (0.003)
16Leada
i
I
---1--- ___L___
1,27 (0.050) NOM
14 Places
(aeaNoteA)
~
8,89 (0.350)
7,87 (0.310)
Base And
Seating
Plane
..
7,62 (0.300)
(aeeNote B)
I
~~J_:
24,38 (0.960)
2,03 (0.080)
1,27 (0.050)
r(_Note~
7,24 (0.285)
(0.247)
*--1---
f-
- .-
-
I-
16
f9
~
1
r-
-
,-
8
-
,-
8,89 (0.350)
7~T'
1,02 (0.040)
0,51 (0.020)
10,16 (0.400)
~
0,64 (0.025)
4- 0,25 (0.010)
4Placea
Fall wHhin JEDEC MO-OO4AA dimensions
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
NOTES: A. Leads are within 0,13 (0.005) radius of true posHion (T.P.) at maximum material condition.
B. This dimension determines a zone within which all body and lead Irregularities lie.
C. Index point is provided on cap for terminal identification only.
TEXAS
~
INSIRUMENTS
POST OFFICE BOX 655303 • DALlAS, TEXAS 75265
6-25
6-26
MICHIGAN: DeIraIt: AtrowiSchwebar (31~:lta:x';
Hall-Mark (313) 418-6800; Marahall (313)
:
Newark (313)967-0800.
MINNESOTA: Anthem (612) 844-5454; AtrowlSchwobar
(612) 841-5280; Hall-Mark (612) 681-2800; MarohaII (612)
SSB-l!211.
MISSOURI: AtrowlSchweber (314)587-6688; Hall-Mark
(314)281-5350; Marahall (314)291-4650.
NEW JERSEY: Anthom (2011227-7880; Atrow_
201)227-7880, t8Oll) SBHOOO; Hall-Mark (201) 516-3000,
8011)236-1800; Manihall (201)662-0320, (tIo8):!34-8100.
NEW MEXICO: Alilanco (505) 282-3380.
NEW YORK: !..Dna lellnd: Antham (5181 S84-68OO;
Arrow/S_ (5161231-1000: Hall-Mark (5161
737-0800: MarohaII (518) 273-2424: Zouo (814) tl37-74DO;
Rcch_r: Arrow/Schwobar (718) 427-0300; HaII-Mark
(718) 425-3300; Marohall (7181 236-7620;
Syrac..... MarohaII (807) 765-2345.
TI North
TI Authorized
American Sales North American
Offices
Distributors
1
ALABAMA: H_11e: (206) 837-7530
ARIZONA: _
(602) 8115-1007
CAUFORNIA: 1rvI""~ 1180-1200
::n":=l~~l~
_oncI HII:: ~18)704-81oo
COLORADO: - . (303)38&-8000
CONNEc:nc:trn w.IIIngfanl: (203)28Il-0074
~~~sc:a':J407)260-2118
_pa: (813) 885-'75811
GEORGIA: _
(404)1182-7887
ILUNOlS: Allington HelgIrIII: (708) 640-3000
INDIANA: c:.rmoI: (317) 573-8400
fori w.yne: (218) _ _7
KANSAS: _ n d PIIk: (813)461-4611
MARYLAND: COlumbia: (410) Il84-2OO3
MASSACHUSETTS: W.l1hom: (817) 886-11100
MICHIGAN: Ftlnnlngton HUIe: (313)1563-1581
MINNESOTA: EcIon Prolflr. (612) 828-8300
MISSOURI: 8t- Louie: (314)621-6400
NEW JERSEY: IMIln: (808) 750-1050
NEW MEXICO: Albuq_ (505) 346-2866
NEW YORK: _
~ (315) 483-8281
Flohklll: (814) 897-2lIOo
MalYi lie: (516) 464-88CO
PI\IIfOrd: (7181 365-6770
::'::~?~~ (704)II27-Q110O
~a=.,,,,=, ~~~~721i8
OREGON: _
(!03)1143-6758
PENNSYLVANIA: PIymouIh _ng: (215) 825-8500
PUERTO RICO: Halo Roy: (808) 75IHl7OO
=:(~:':7~1~250-6789
Houoton: (713) n8-6582
Mldloncl: (815) 581-7137
UTAH: SolI ....... City: (801) 468-8872
WISCONSIN: w._: (414) 7811-1001
CANADA: N._~1=187O
RIchmond Hili: 141 864-9181
SL Laurent: (514)
::,"=~_' Inc. (military producI only)
Anthem EloctronIcI
Atrow/S_or
Future ElectroniCS (Conoda)
GRS Electronics Co., Inc.·
Hall-Mark EIoc\ronIcs
Marahallindustriea
Newark EloctronlCB*
;c~==CS,Inc. ( - producIonIy)
ZOtla Componenla
*Not _
lor TI mllHary producll
TI Distributors
ALABAMA: AtrowlSchwebar (2051837-6858: HaI~Mark
(205)837-8700; Marshall (205) 881_
ARIZONA: Anthom (602) 888-6800; Atrow_ (602)
437-0750: Hall-Mark (802) 431-0030: MarohaII (802)
486-0280; WyI8 (802)437-2088.
CAUFORNIA: Loe AngolOO/O..ngo County: Anthom
~~~1~j~~1J=~~owr,~~,8),14)
~14)458-5301; ~Ie
727-6000; garahall (618) 8711-7000,
(818)88().8000, (714)883-8863; Zouo (714)821-8000,
(8181 S88-3836:
~!r.A:n~l~l:t~~~~~~;
Bon DI_: Anthem tSll1l463-8006: Atrow/Schwobar
tSl11) 585-4800: Hall-Mark (619)268-1201: Marahal11619)
827-4140; Wylo (818) S8S-8171;Zouo (618)2n-8881;
Bon Franclocc Boy _ : Anthem (408) 463-1200;
Arrew/SchwabarC)441-87oo,~510) 480-84n:
~~~I~-2S00~,,=~~~-4800;
COLORADO: Anthem (3031;78O-45OO;-/Schwobar
(303)799-02S8; Hall-Mark 303 780-1662; Marshall (303)
45HI383; Wylo (303) 457
•
CONNECTICUT: Anthem (203)575-1575; Atrow/Schwabor
(203)285-n41; HaII-Mark (203)271-2644: Marsholl (203)
265-3622.
FLORIDA: fori Lauderdal.: ArrewlSchwebar (305)
429-8200; HaI"-Mark (305) 871-11280; Marshall· (305)
977-4680;
==;==~W~=U~~,"=I~
TIImpa: HaI~Mork (813)541-7440; Morahall (813)
TI Regional
Technology
Centers
CAUFORNIA: irvine: (714) 650-6140
Sonta CI...: (408) 746-2222
GEORGIA: _
(404) 662-7846
IWNOIS: ArlIngton Halghla: (708) 640-2909
INDIANA: lndI_pelle: (317) 573-6400
MASSACHUSETTS: WoI1hom: (617) 895-8188
573-1389.
:l~~~~~.ir~~I~:m::l32:
OHIO: Cleveland: Arrow/Schwobor (2181 246-39110;
Hall-Mark (218) 3411-4632; Manlhall (216) 246-1788;
COIumbuo: HaI~Mark (814)888-3313;
~~=~143S-6S83;-(513)
OKLAHOMA: Arrow/Schwobar (818) 252-7537; Hall-Mark
(818)254-8110.
~~?::=~I~~,,<=m~
PENNSYLVANIA: Anthem (2151443-5150:
Arrow/Schweber /2151 928-1800; GRS (215) 822-7037;
(8081 __ 6580; liarshall (412)766-0441.
'TEXAS: Aurin: Atrow/Schweber 1512) 835-4180;
Hall-Mark (512) 258-8846; Marohall (612) 837-1681; WyIe
(512) 346-1165:1:
Doll.., Anthom (214) 238-7100; Atrow/ScIrwobar (214)
360-6464: Hall-Mark (214) 553-4300; Marahall12141
233-5200; Wyla (214) 23S-6853; Zouo (214)763-70'10;
H _ : Atrow/SchWabar (713)531>4700; HoI~Mark
(713)781-6100; Manlhall (713)467-1666; Wyle (713)
879-6853.
UTAH: Anthom (801) 873-6SS8; ArrowlSchwabar (801)
973-6813; HaII-Mark (801)289-0418; Marshall (801)
873-2288; WyI8 (801) 874-8863.
WASHINGTON: Almaol_ (208) 643-8892; Anthem
(208)483-1700; Marshall (208)466-6747; Wyle (208)
861-1150.
~~F~~~~~=~~~~:Ol50;HCANADA: Calgary: Fu1ure (403) 235-6325;
Ed...-: Future (403) 436-2868;
Me_: Atrow/Schwobor (514) 421-7411; Future (514)
894-nl0; Marshall (514) 894-6142;
0t1II.... Arrow/Schwobar (613)226-6803; FuIuro (813)
820-8313;
au...... Fu1ure (4181887-6868;
~:::r:r~1=~~uJ:1:I1 ~n~
Von_: AtrowIS_or (804) 421-2333;
Future (804)284-1168.
~~:r~~~~HaI-Mark
IWNOIS: Anthom~884-0200: Atrow/Schwobor (708)
25O-OSDO; Hall-Ma
) 850-3800; Marshall (708)
49().()1 SS; Nawark (3 2)784-5100.
~~~=~&r~~.o=.l; Half.Mark
IOWA: AtrowlSchwebar (318) 385-7230.
~~)~~~I1;:;'~~'1M~:~i~; HoI~Mark
MARY\.AND: Anthem (301198S-6840; AtrowlSchweber
1301) 596-7800: Hall-Mark 301) 886-88CO; MarohaII (301)
822-1118; Zouo (301) 887-1118.
TI Die Processors
Chip Supply
Elmo Semiconductor
Minco Technology labs
(407) 298-7100
(818) 768-7400
(512) 834-2022
::!'~,!!!~~~.Jo~!1.~~
~~~~ ~~~~) 858-0810; Wylo (617) 272-7300;
MEXICO: MIOldco City: 481-70634
MINNESOTA: Min_pelle: (812) 828-83CO
'TEXAS: 00II..: (214)817-3661
CANADA: N _ : (613)726-1870
Customer
Response Center
TOLL FREE:
OUTSIDE USA:
(800) 336-S236
(214) 995-6611
(8:00 a.m. - 5:00 p.m. CST)
iCl1993 Texas Instruments Incorporated
~ThxAs
INSTRUMENTS
00293
TI Worldwide
Sales Offices
ALABAMA: Huntnllle: 4980 Corporate Drive,
Suite 150, HunIBVIUe, AL 35805, (205) 837-7530.
ARIZONA: Phoenix: 8825 N. 23rd Avenue,
Suite 100, Phoenix, AZ 85021, (802) l1li5-1007.
CAUFORNIA: Irvine: 1920 Main Street, SuIte
BOO, Irvine, CA92714, (7'14) 850-1200;
Sen Diego: 5825 Rufftn Road, Suite 100,
Sen Dlalio, CA 92123, (619) 276-9600;
Santa Cl.,.: 5353 Bel8\' ROsa Drive,
=1~"'~:~(~~Sulte7oo,
Woodland Hille, CA 91367, (816) 704-a1oo.
COLORADO: Aurora: 1400 S. Potomac Street,
Suite 101, Aurora, CO 80012, (303) 366-8000.
CONNECTICtrn Wailinafonl: II Bamaa IndUSlrlai
Park So., W81l1ngford, Cf 06492, (203) 269'()()74.
FLORIDA: AItIImonte Springe: 370 S. North Lake
Boulevard, Suite 1008, Altanionle Springe,
FL32701, (407)260-2118;
Fort Lauderdale: 2950 N.W. B2nd Street,
Suite 100, Fort Lauderdale, FL33309,
(305) 973-8502·
1lImpa: 4803 George Road, Suite 390,
Tempa, FL 33834-8234, (813) 885-7588.
GEORGIA: Norcroea: 5615 Spalding Drive,
Norcross, GA3OOIl2-2580, (404) 882-7987.
ILUNOIS: Arlington H.lghta: 515 Wast
Algonquin, ArIIngIDn HeightS, IL BOOO5,
(708) 840-2826.
INDIANA: Carmel: 550 Cong....lonal DrIve,
Suite 100, Cannel, IN 48032, ~(317)673-6400;
Fort Wayne: 103 AIrport North Office Park.,
Fort Wayne, IN 4B1125, (219) 489-4697.
KANSAS: OverIlnd Pirie 7300 ColI!llle
Boulevard, L1ahlon Plaza, SuIte 150, OVerland
Park, KS 88210, (913) 451-4511.
MARYLAND: Columbia: 8515 Centre Park DiMI,
Suite 100, Columbia, MD21046, (410) 964-2003.
MASSACHUSE1TS: Wanham: Bay Colony
Corporate Center, 1150 WInter Straa!, Suite 2800,
Waltham, MA02154, (817) 885-8100.
MICHIGAN: Farmington Hili.: 33737 W. 12 Mile
Road, FarmlngIDn Hlrls, MI48018, (313) 563-1581;
MINNESOTA: Eden Prairie: 11000 W. 78th Street,
Suite 100, Eden PraIrie, MN 56344, (612)
828-Il300.
MISSOURI: 8t. Lou..: 12412 Powerscourt Drive,
Suite 125, St. Louis, MO 83131, (314) 821-8400.
NEW JERSEY: IMlln: M8\rOP011ten Coroorate
Plaza. 485 Bldg. E. U.S. 1 SoUth, iselin, NJ OB83O,
(908) 750-1050.
NEW MEXICO: Albuquerque: 27011 J. Pan
American Freeway NE, AlbUquarque, NM 87101,
(505) 345-2556.
NEW YORK: Ea8t Sync.e: .8365 CoIlamar
Drlva, East SyrlICUS8, NY 13057, (315) 483-9281;
Fishkill: 300 Wastage Buslnaea Center, Suite 140,
Fishkill, NY 12524, (914\ 887-2800;
Melville: 48 South Service Road, Suite 100,
MeMlle, NY 11747, (518) 454-8501;
Pittsford: 2851 CloVer Street, PItIs1ord, NY 14534,
(716) 385-8770.
NORTH CAROUNA: Charlotte: 8 Woodlawn
Green, Suite 100, Charlotte, NC 28217, (704)
527.()930;
Raleigh: 2809 HIGhwood. Boulevard, Suite 100,
Raleigh, NC 27825, (819) 876-2725.
OHIO: Beachwood: 23775 Commerce Park Road,
Beachwood, OH 44122-8675, (216) 785-7526;
Beavercreek: 4200 Colonel Grenn Highway,
Suite 800, Beavercreek, OH 45431,
(513) 427-8200.
OREGON: BeaverlOn: 8700 S.W. 105th Straa!,
Suite 110, Beaverton, OR 97005, (503) 843-8758.
PENNSYLVANIA: PIJmouIh -.,g, 800_
Gerntar-. PIke, _
200, ~ MoeIIng, PA , _ ,
(215)_
PUERTO RICO: Hato Rey:: 815 Mercentli Plaza
Building, Suite 505, Halo Ray, PR 00919,
(809) 753-8700.
TEXAS: Awtln: 12501 Raaearch Boulevard,
Austin, TX 78758, (51g) 250-8788;
Dalla.: 7839 ChurchlU Way, Dallas, TX 715251,
(214) 917-1264;
Houston:' 9301 Southwest F_y, Commerce
Park, Suite 380, Houston, TX 77074,
(713) 778-8592;
Midland: FM 1788 & 1-20, Midland, TX
79711-0448, (915) 581-7137.
UTAH: Salt Lake City: 2180 SouIh 1300 East.
Suite 335, Salt Lake CIty, UT 541 08,
(801) 485-8912WISCONSIN: Waukesha: 20825 SWenson Drive,
Suite BOO, WaukaehaWI53188, (414) 7lIB-1oo1.
CANADA: Napaen: 301 Moodle Drive, Suite 102,
Mailom Cantni, Nepean, Ontario, Canada K2H
9C4, (813) 726-1970;
.
Richmond Hili: 280 Centre Straet East. Richmond
HIli, Onterlo, Canada l4C 1Bl, (418\ 884-9181;
8t. Laurent: 9480 Trans Canada Highway,
st. Laurent, Quebec, Canada H4S lR7, (514)
335-8392.
AUSTRAUA (& NEW ZEALAND): TPP
Inatrumen1S AuS1ralla Ud., 8-10 18Iavera Road,
North Ryde (Sydney), New South Walaa,
AuS1ralle21i3,2-818-9000: 14th Floor, 380 Street,
K11da Road, MaIboume, VIctorIa, Auslralia 3000,
3-886-1211.
BELGIUM: TPP Inslruments Belalum S.A./N.V.,
Avenue Julaa Bordetlaan 11, 1140 lINM8Ia,
Belgium, (02) 242 30 80.
BRAZIL: Texas lnatrumentoa EIecIronIco8 do
Brasil Ude., Av. Eng.luIz Cerlos Barrlnl, 1481-110.
andar, 04571, Sao Paulo, Sp, BrazIl, 11-835-8133.
DENMARK: Texas Inslrumen1S AIS, BorupVang
20, DK-2750 Ballerup, Denmark, (44) 88 74 00:
FINLAND: TPP Instruman1S OY, Ahertelantle 3,
P.O. Box 88,02321 Espoo, Finland. (0) 802 8517.
FRANCE: TPP Instrumenta France, 8-10
Avenue Morane-Saulnlar, B.P. 87, 78141 VaIIzyVllleooublay Cadex, France, (1) 30 70 1003.
GERMANY: Texas Instruments Deutachland
GmbH., H~~ 1, 8050 Frelslng, (08161)
ao-o: KurIO
amm 185-198, 1000 Berlin 15,
(030) 8 82 73 85; DOssaidoffar S1rejIe 40, B23B
eschbom 1, (081116) 80 70i_Hollaatr'ejla 3, 4300
Essen 1, (0201) 23 85 4O:~Nrchhoratar StrBjle 2,
3000 Hannover51, (0511 6458-0;
dam 2 (NeUlngen),
Maybechstrajle II, 7302
(0711) 3003267.
HOlLAND: Texaslnalruments Holland B.V.,
Hogehllweg 19, PosIbua 128115, 1100 PoZ.
Amstardam-ZUldoost, Holland, (020) 5802811.
HONG KONG: Texaslnalruments Hong Kong Ud.,
8th FI_, World Shipping Centre, 7 Canton Road,
Kowloon, Hong Kong, 737..()338.
HUNGARY: TPP lnalruments Rapreaentatlon,
Buda6rs1 u.42, H-1112 Budapest, Hungary,
1888817.
IRELAND: Texas Instrumen1S Ireland Ud.,
7/8 Harcourt Street, Dublin 2, Ireland,
(01) 756233.
rrALY: Texas Instruments Halla S.p.A., Centro
DlrezIonaIe CoIlaonl, Palazzo Perseo-Vla
Paracal80 12, 20041 Agrate BrIanza (MI), Italy,
(039) 83221; Vie Castello della Magllan&, 38,
00148 Roml, ItIIJy (8) 857 2851.
m
~TEXAS
INSTRUMENTS
©1993 Texas Instrumanla Incorporated
Prlnlad In U.SA
JAPAN: Texas Instruments Japan Ud., Aoyama
Fuji Building 3-6-12 KIta-Aoyama Mlneto-ku, Tokyo,
JllP!ln 107 03-488-2111; MS Shlbeurs
Building 9F, 4-13-23 Shlbeura, Mlnelo-ku, Tokyo,
Japan 108, 03-788-8700; Nissho-lwal Building 5F,
2-8-8 Imabeshl, Chuou-ku, Osaka, Japan 54 f,
08-204-1881; DaI-nl Toyola Building Nlshl-ken 7F,
4-10-27 Maleld, Nekemurs-ku, Nagoya, Japan 450,
052-583-8691; Kanazawe Oyarne-cho Dalfchl
Selmel Building 6F, 3-10 Oyema-cho,
Kanazawa-shl, Ishikawa, Japan 920,
0782-23-5471; Matsumoto Showa Building SF,
1-2-11 Fukeshl, Matsumoto-shl, Nagano, Japan
390,0283-33-1080: Dallchl Olympic Techlkawa
Building 6F, 1-25-12, AkebonCHlho, Techikawa-shl,
Tokyo, oIepan 190, 0425-27-8760; Yokohama
Buslnaaa Park East Tower 10F, 134 GOUdCHlho,
Hodogeye-ku, Yokohema-shl, Kanegawa, Japan
240, 045-338-1220; Nlhon Selinel ~~oto Yasake
Building 5F, 843-2, Higeahl Shlokoh -cho,
Hlgashl-lru, Nlshlnotofi-ln, Shlokohll-dorl,
Shlmogyo-ku, Kyoto, Japan 600, 075-341-7713;
Sumltomo Selma« Kumagaye Building 8F, 2-44
YavoI, Kumagaya-shl, Salt8ma, Japan 380,
0485-22-2440; 2597-1, Aza Harud8l, Oaza Yasake,
Kltsuld-shl, OIIa, Japan 873, 09786-3-3211.
KOREA: Texas Instruments Korea Ud., 28th Floor,
Trade Tower, 159-1, Semsung-Dong, Kangnam-ku
Seoul, Korea, 2-561-2800.
MALAYSIA: Texas Instrumen1S, Malaysia, Sdn.
Bhd., Asia Pacific, Lot 38.1 I/Box 93, Menars
Maybank, 100 Jalan Tun Persk, 50050 Kuala
Lumpur, Malayala, 3-230-8001.
MEXICO: Texas Instruman1S de Mexico SA de
C.V., Alfonso Reyaal15, Col. HiPOdromo Condesa,
Mexico, D.F., 08170, 5-515-808f.
NORWAY: Texas Instrumen1S Norge AIS, B.P. 108,
Refslad (Slnsanvelen 53), 0513 Oslo 5, Norway,
(02P56 090.
PEOPLE'S REPUBLIC OF CHINA: Texas
Instrumen1S China Inc., Beijing Representative
OIIica, 7-05 CITIC Building, 19 Jlanguomenwal
Dajla, Beijing, China, 500-2255, Ext. 3750.
PHIUPPINES: Texas Instruments AsIa Ud.,
:~:~~:S':~:l~i.I'~~::=~
Philippines, 2-817-8031.
PORTUGAL: Texaslnstrumen1S Equlpamento
Electronlco (Portugal) LOA., Ing. Frederico Ulrlcho,
2650 Moreira Da Mafa, 4470 Mala, Portugal
(2) 948 1003.
SINGAPORE (& INDIA, INDONESIA, THAILAND):
~=c~'1"crtH~:"!~~'::!~~,LfJln~1a
Square, Singapore 1130, 350-8100.
SPAIN: Texaslnalrumen1S Espa/ia SA, C/Gobalas
43, Urbanlzaslon La FlorIde, 28023, Madrid, Spain,
(91) 372 8051; Q/Dlputaclon, 279-3-8, 08007
9aicalona, Spain, (93) 317 91 80.
SWEDEN: Texas Instrumenls International Trade
Corporation (Sverlgefillalen), BoxSO, 8-164 93
K1sta, Sweden, (08) 752 58 00.
SWIlZERLAND: Texas Instruments Switzerland
AGj Rledstrasae 6, CH-8953 Dletlkon, Switzerland,
(01 7442811.
TAIWAN: Texas Instrumen1S Taiwan Umlted, Taipei
Branch, 10th Floor, Bank Tower, 205 Tung Hua N.
Road, Taipei, Taiwan, 10592, Republic of China,
(02) 713 9311.
UNITED KINGDOM: Texas Instrumen1S Ud.,
Manton Lane, Bedford, England, MK41 7PA,
(0234) 270 111.
~lExAs
INSJRUMENTS
Printed in U.S.A.
0593-CP-50
SLLD001
Source Exif Data:
File Type : PDF File Type Extension : pdf MIME Type : application/pdf PDF Version : 1.3 Linearized : No XMP Toolkit : Adobe XMP Core 4.2.1-c041 52.342996, 2008/05/07-21:37:19 Create Date : 2017:08:10 19:49:16-08:00 Modify Date : 2017:08:10 20:42:53-07:00 Metadata Date : 2017:08:10 20:42:53-07:00 Producer : Adobe Acrobat 9.0 Paper Capture Plug-in Format : application/pdf Document ID : uuid:d8c67599-f54b-504b-b18c-69f61fc1f3f2 Instance ID : uuid:e12e6729-c5e4-7948-8c5f-9167982d54f6 Page Layout : SinglePage Page Mode : UseNone Page Count : 1282EXIF Metadata provided by EXIF.tools