1993_TI_MOS_Memory_Data_Book 1993 TI MOS Memory Data Book
User Manual: 1993_TI_MOS_Memory_Data_Book
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~TEXAS
INSTRUMENTS
MOSMemory
Commercia' and Mi'itary Specifications
1993
1993
"MOS Memory
Data Book
Commercia' and Mi'itary
Specifications
~TEXAS
INSTRUMENTS
IMPORTANT NOTICE
Texas Instruments Incorporated (TI) reserves the right to make changes to its products or to discontinue
any semiconductor product or service without notice, and advises its customers to obtain the latest
version of relevant information to verify, before placing orders, that the information being relied on is
current.
TI warrants performance of its semiconductor products and related software to current specifications
in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to
the extentTl deems necessary to support this warranty. Specific testing of all parameters of each device
is not necessarily performed, except those mandated by government requirements.
Please be aware that TI products are not intended for use in life-support appliances, devices, or systems.
Use of TI product in such applications requires the written approval of the appropriate TI officer. Certain
applications using semiconductor devices may involve potential risks of personal injury, property
damage, or loss of life. In order to minimize these risks, adequate design and operating safeguards
should be provided by the customerto minimize inherent or procedural hazards. Inclusion ofTl products
in such applications is understood to be fully at the risk of the customer using TI devices or systems.
TI assumes no liability for applications assistance, customer product deSign, software performance, or
infringement of patents or services described herein. Nor does TI warrant or represent that any license,
either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right ofTl covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used.
Copyright © 1993, Texas Instruments Incorporated
INTRODUCTION
The 1993 MOS Memory Data Book from Texas Instruments includes complete detailed specifications on the
expanding MOS Memory product line including Dynamic Random Access Memories (DRAMs), Single-In-Line
Memory Modules (SIMMs), Erasable Programmable Read-Only Memories (EPROMs), One-Time
Programmable Read-Only Memories (OTP PROMs), Electrically Erasable Programmable Read-Only
Memories (Flash Memories), Video RAMs (VRAMs), Field Memories (FMEMs), and Memory Cards. Also
included are military specifications for DRAMs, EPROMs, and VRAMs.
The data book is divided into 13 chapters. Below you will find a brief description of each chapter.
Chapter 1. General Information -Includes an alphanumeric index for quickly finding device numbers and a part
number guide with ordering information.
Chapter 2. Selection Guide - An easy-to-use reference guide that includes specific device information. Page
numbers are also shown for easy access to the detailed specifications.
Chapter 3. Glossarymming
throughout the data book.
Conventions/Data Sheet Structure -
Defines terms and standards used
Chapter 4-9. Product specifications for over 100 devices can be found in these sections.
Chapter 10. Logic Symbols -
Includes an explanation and examples of the IEEE standard.
Chapter 11. Quality and Reliability - Details selected processes and the philosophies of Texas Instruments that
are used to ensure high quality standards.
Chapter 12. Electrostatic Discharge Guidelines handling guidelines are included.
Because all MOS Memory devices are ESD-sensitive,
Chapter 13. Mechanical Data- Detailed package drawings and specifications are shown in this section.
For ordering information or further assistance, please contact your nearest Texas Instruments Sales Office or
Distributor as listed in the back of this book.
Contents
CHAPTER 1.
GENERAL INFORMATION
Alphanumeric Index ..............................................................................
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DRAMNRAM/FMEM ........................................................................ ,
DRAM Module ..............................................................................
Nonvolatile .................................................................................
CHAPTER 2.
1-3
1-5
1-5
1-7
1-9
SELECTION GUIDE
DRAM .......................................................................................... 2-3
DRAM Module ...... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-8
EPROM ........................................................................................ 2-11
Flash Memory .................................................................................. 2-13
One-Time Programmable (OTP) PROM ............................................................ 2-14
Video Rams/Field Memories ..................................................................... 2-15
Memory Card ..... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-16
CHAPTER 3.
DEFINITION OF TERMSrrlMING CONVENTIONS
General Concepts and Types of Memories .......................................................... 3-3
Operating Conditions and Characteristics ........................................................... 3-7
Timing Diagram Conventions ...................................................................... 3-8
CHAPTER 4.
TMS44100
TMS44100P
TMS44400
TMS44400P
TMS46100
TMS46100P
TMS46400
DYNAMIC RAMS
4 194 304-bit
4 194 304-bit
4 194 304-bit
4 194 304-bit
4 194 304-bit
4 194 304-bit
4 194 304-bit
4 194 304-bit
4 194 304-bit
4 194 304-bit
4 194 304-bit
TMS46400P
TMS44800
TMS44800P
TMS44165
TMS44165P
TMS45160
TMS45160P
TMS45165
TMS45165P
4
4
4
4
4
TMS416100
TMS416400
16777 216-bit
16777 216-bit
194 304-bit
194 304-bit
194 304-bit
194 304-bit
194 304-bit
(4096K x 1) Enhanced Page Mode ................................ 4-5
(4096K x 1) Low Power .......................................... 4-5
(1 024K x 4) Enhanced Page mode .............................. , 4-27
(1 024K x 4) Low Power. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-27
(4096K x 1) Low Voltage ........................................ 4-49
(4096K x 1) Extended Refresh .................................. 4-49
((1 024K x 4) Low Voltage ....................................... 4-71
(1 024K x 4) Extended Refresh .................................. 4-71
(512K x 8) Enhanced Page Mode ................................ 4-93
(512K x 8) Low Power .......................................... 4-93
(256K x 16) Enhanced Page Mode ............................ " 4-115
(256K x 16) Low Power. . . . . . . .. . .. . .. . . . . . . . . . . . . . . . . . .. . . . . .. 4-115
(256K x 16) Enhanced Page Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-137
(256K x 16) Low Power. . . . .. .. . .. .. .. . . . . . . . . . . . . . . .. . .. . . . . .. 4-137
(256K x 16) Enhanced Page Mode ............................ " 4-159
(256K x 16) Low Power ................... : .................. " 4-159
(16 385K x 1) Enhanced Page Mode ...................... 4-181, 4-249
(4096K x 4) Enhanced Page Mode ........................ 4-203, 4-249
vii
TMS417400
16-Meg Shrink
TMS416160
TMS416160P
TMS426160
TMS426160P
TMS418160
TMS418160P
TMS428160
TMS428160P
TMS416800
TMS416800P
TMS417800
TMS417800P
TMS426100
TMS426100P
TMS426400
TMS426400P
TMS427400
TMS427400P
TMS426800
TMS426800P
TMS427800
TMS427800P
SDRAM
viii
16 777 216-bit
16777 216-bit
16 777 216-bit
16 777 216-bit
16 777 216-bit
16777 216-bit
16777216-bit
16777216-bit
16777216-bit
16 777 216-bit
16 777 216-bit
16 777 216-bit
16 777 216-bit
16777216-bit
16 777 216-bit
16 777 216-bit
16 777 216-bit
16 777 216-bit
16 777 216-bit
16777216-bit
16777 216-bit
16777216-bit
16 777 216-bit
16 777 216-bit
16 778 240-bit
(4096K x 4) Enhanced Page Mode ........................ 4-227,
(16 385K x 1 and 4096K x 4) Product Preview.. . . . .. . . .. . .. . . . . ..
(1 024K x 16) Enhanced Page Mode ............................
(1 024K x 16) Low Power ......................................
(1024K x 16) Low Voltage .....................................
(1 024K x 16) Low Voltage, Low Power ..........................
(1 024K x 16) Enhanced Page Mode ............................
(1 024K x 16) Low Power ......................................
(1 024K x 16) Low Voltage .....................................
(1 024K x 16) Low Voltage, Low Power ..........................
(2048K x 8) Enhanced Page Mode ..............................
(2048K x 8) Low Power. . .. .. . .. . . . .. . . . . . . . . .. . . . .. . .. . . .. ....
(2048K x 8) Enhanced Page Mode ..............................
(2048K x 8) Low Power ........................................
(16K x 1) Low Voltage .........................................
(16K x 1) Low Voltage, Low Power ..............................
(4096K x 4) Low Voltage .......................................
(4096K x 4) Low Voltage, Low Power ...........................
(4096K x ,4) Low Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
(4096K x 4) Low Voltage, Low Power ...........................
(2048K x 8) Low Voltage .......................................
(2048K x 8) Low Voltage, Low Power ...........................
(2048K x 8) Low Voltage .......................................
(2048K x 8) Low Voltage, Low Power ...........................
(1 024K x 2) Synchronous DRAM ...............................
4-249
4-249
4-253
4-253
4-275
4-275
4-297
4-297
4-319
4-319
4-341
4-341
4-363
4-363
4-385
4-385
4-409
4-409
4-433
4-433
4-457
4-457
4-479
4-479
4-501
CHAPTER 5.
TM124EU9B
TM124EU9C
TM497EAD9B
TM497MBK36A
TM497MBK36Q
TM124BBK32
TM124BBK32S
TM248CBK32
TM248CBK32S
TM124MBK36
TM124MBK36Q
TM124MBK36B
TM124MBK36R
TM248NBK36B
TM248NBK36R
TM124MBK36C
TM124MBK36S
TM248NBK36C
TM248NBK36S
TM4100EAD9
TM4100GAD8
TM497GAD8A
TM16100GBD8
TM16100EBD9
TM497BBK32
TM497BBK32S
TM893CBK32
TM893CBK32S
TM497TBM40
TM497TBM40S
TM893VBM40
TM893VBM40S
TM496TBM40
TM496TBM40S
TM892VBM40
TM892VBM40S
TM124TBK40
TM124TBK40S
TM248VBK40
TM248VBK40S
CHAPTER 6.
TMS27C128
TMS27PC128
DYNAMIC RAM MODULES
9437184·bit
9437 184·bit
33 554 432-bit
150 994 944-bit
150 994 944-bit
33554 432-bit
33554 432-bit
67 543 040-bit
67 543 040-bit
37748 736-bit
37748 736-bit
37748 736-bit
37748 736-bit
75 497 472-bit
75 497 472-bit
37748 736-bit
37748 736-bit
75 497 472-bit
75 497 472-bit
37748 736-bit
33 554 432-bit
33 554 432-bit
134217 728-bit
150994 944-bit
134217 728-bit
134 217 728-bit
268 435 456-bit
268 435 456-bit
167 772 160-bit
167 772 160-bit
335 544 320-bit
335 544 320-bit
167 772 160-bit
167 772 160-bit
335 544 320-bit
335 544 320-bit
41 943040-bit
41 943040-bit
83 886 080-bit
83 886 080-bit
(1 024K x 9) Single-Sided ........................................ 5-5
(1 024K x 9) Single-Sided ........................................ 5-5
(4096K x 9) Single-Sided ...................................... , 5·13
(4096K x 36) Double-Sided (gold-tabbed) ........................ , 5-21
(4096K x 36) Double-Sided (solder-tabbed) ....................... 5-21
(1024K x 32) Single-Sided (gold-tabbed) ......................... 5-29
(1024K x 32) Single-Sided (solder-tabbed) ........................ 5-29
(2048K x 32) Double-Sided (gold-tabbed) ........................ , 5-29
(2048K x 32) Double-Sided (solder-tabbed) ....................... 5-29
(1024K x 36) Double-Sided (gold-tabbed) . . . . . . . . . . . . . . . . . . . . . . . .. 5·39
(1024K x 36) Double-Sided (solder-tabbed) ....................... 5-39
(1024K x 36) Single-Sided (gold-tabbed) ......................... 5-47
(1024K x 36) Single-Sided (solder-tabbed) ............... " ....... 5-47
(2048K x 36) Double-Sided (gold-tabbed) ., ...................... , 5-47
(2048K x 36) Double-Sided (solder-tabbed) ....................... 5-47
(1 024K x 36) Single-Sided (gold-tabbed) ......................... 5-57
(1 024K x 36) Single-Sided (solder-tabbed) ....................... , 5-57
(2048K x 36) Double-Sided (gold-tabbed) ........................ , 5-57
(2048K x 36) Double-Sided (solder-tabbed) ....................... 5-57
(4096K x9) Single-Sided ....................................... 5-67
(4096K x 8) Single-Sided ...................................... , 5-75
(4096K x 8) Single-Sided ....................................... 5-83
(16 384K x 8) Double-Sided .................................... , 5-91
(16 384K x 9) Double-Sided.. . . . . . . . . . .. . .. . . .. . .. . . .. . .. .. . . ... 5-99
(4096K x 32) Double-Sided (gold-tabbed) ...... '" ............... 5-105
(4096K x 32) Double-Sided (solder-tabbed) ...................... 5-105
(8192K x 32) Double-Sided (gold-tabbed) ........................ 5-105
(8192K x 32) Double-Sided (solder-tabbed) ...................... 5-105
(4096K x 40) Double-Sided (gold-tabbed) ........................ 5-115
(4096K x 40) Double-Sided (solder-tabbed) ...................... 5-115
(8192K x 40) Double-Sided (gold-tabbed) ........................ 5-115
(8192K x 40) Double-Sided (solder-tabbed) ...................... 5-115
(4096K x 40) Double-Sided (gold-tabbed) ........................ 5-125
(4096K x 40) Double-Sided (solder-tabbed) ...................... 5-125
(8192K x 40) Double-Sided (gold-tabbed) ........................ 5-125
(8192K x 40) Double-Sided (solder-tabbed) ...................... 5-125
(1 024K x 40) Single-Sided (gold-tabbed) ........................ 5-137
(1 024K x 40) Single-Sided (solder-tabbed) ... . . . . . . . . . . . . . . . . . . .. 5-137
(2048K x 40) Double-Sided (gold-tabbed) ........................ 5-137
(2048K x 40) Double-Sided (solder-tabbed) ...................... 5-137
EPROMS/OTP PROMS/FLASH EEPROMS
131 072-bit
131 072-bit
(16K x 8) CMOS EPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6-2
(16K x 8) CMOS OTP PROM .................................... 6-2
ix
TMS27C256
TMS27PC256
TMS27C510
TMS27PC510
TMS27C512
TMS27PC512
TMS27C010A
TMS27PC010A
TMS27C210A
TMS27PC210A
TMS27C020
TMS27PC020
TMS27C040
TMS27PC040
TMS27C240
TMS27PC240
TMS27C400
TMS27PC400
TMS29F816
TMS28F010
TMS28F512
TMS28F210
TMS28F040
TMS27LV010A
x
262144-bit
262144-bit
524288-bit
524288-bit
524288-bit
524288-bit
1 048 576-bit
1 048 576-bit
1 048 576-bit
1 048 576-bit
2 097 152-bit
2 097 152-bit
4 194 304-bit
4 194 304-bit
4 194 304-bit
4 194 304-bit
4 194 304-bit
4 194 304-bit
16384-bit
1 048 576-bit
524288-bit
1 048 576-bit
4 194 304-bit
1 048 576-bit
(32K x 8) CMOS EPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6-3
(32K x 8) CMOS OTP PROM ................... ,................ 6-3
(64K x 8) CMOS EPROM .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6-15
(64K x 8) CMOS OTP PROM ................................... 6-15
(64K x 8) CMOS EPROM ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6-27
(64K x 8) CMOS OTP PROM ................................... 6-27
(128K x 8) CMOS EPROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6·39
(128K x 8) CMOS OTP PROM .................................. 6-39
(64K x 16) CMOS EPROM ...................................... 6-51
(64K x 16) CMOS OTP PROM .................................. 6-51
(256K x 8) CMOS EPROM ...................................... 6-61
(256K x 8) CMOS OTP PROM .................................. 6-61
(512K x 8) CMOS EPROM ...................................... 6-71
(512K x 8) CMOS OTP PROM .................................. 6-71
(256K x 16) CMOS EPROM ..................................... 6-81
(256K x 16) CMOS OTP PROM ................................. 6-81
(256K x 16) CMOS EPROM. . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6-91
(256K x 16) CMOS OTP PROM ................................. 6-91
(2K x 9) 5-V Flash EEPROM Serial JTAG Bus .................... 6-101
(128K x 8) 12-V Flash EEPROM ................................ 6-145
(64K x 8) 12-V Flash EEPROM ................................. 6-145
(64K x 16) 12-V Flash EEPROM ................................ 6-165
(512K x 8) 12-V Flash EEPROM ................................ 6-185
(128K x 8) Low Voltage EPROM/OTP PROM ..................... 6-203
CHAPTER 7.
TMS55160
TMS55165
TMS4C1050B
TMS4C1060B
TMS4C1070B
CHAPTER 8.
VIDEO RAMS/FIELD MEMORIES
4 194 304-bit
4 194 304-bit
1 048 576-bit
1 048 576-bit
1 048 576-bit
(256Kx 16) Multiport Video RAM ................................. 7-3
(256K x 16) Multiport Video RAM ................................ 7-57
(256K x 4) Multiport Video RAM ................................ 7-109
(256K x 4) Multiport Video RAM ................................ 7-121
(256K x 4) Multiport Video RAM ................................ 7-133
MEMORY CARDS
CMS405
CMS406
CMS407
CMS408
CMS409
CMS410
CMSB8D8MB36
CMS88D4MB36
CMS68P256
4 194 304-bit
4 194 304-bit
2 097 152-bit
2 097 152-bit
8 388 608-bit
8 388 608-bit
B 388 608-bit
4 194 304-bit
262 144,bit
(2048K x 18) DRAM Memory Card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 8-3
(2048K x 16) DRAM Memory Card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. B-3
(1 024K x 18) DRAM Memory Card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 8-3
(1024 x 16) DRAM Memory Card ................................. 8-3
(4096K x 18) DRAM Memory Card ............................... 8-17
(4096K x 16) DRAM Memory Card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 8-17
(2048K x 36) DRAM Memory Card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 8-27
(1 024K x 36) DRAM Memory Card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 8-27
(256K x 8 or 128K x 16)
OTP PROM Memory Card ...................................... 8-35
CMS68P256N
262 144-bit
CMS68P512
524288-bit
g~~~R~~ ~~~~~ 1J~d
&i-~KpR~~ ~~~~~ 191rd
CMS68P512N
524288-bit
CMS68P1 MB
1 048 576-bit
CMS68P1 MBN
1 048576-bit
CMS68F256
CMS68F512
CMS6BF1 MB
CMS68F2MB
CMS209
CMS210
CMS213
CMS214
CMS216
262 144-bit
524 288-bit
1 048576-bit
2097 152-bit
1 048 576-bit
2 097 152-bit
524 288-bit
1 048 576-bit
2 097 152-bit
...................................... 8-35
...................................... 8-35
(512K x 8 or 256K x 16)
OTP PROM Memory Card ...................................... 8-35
g$~4~ROto~~~:r; d:~d
g$~~\o~O~~~:r; d:~d
...................................... 8-35
......................................
(256K x 8 or 128K x 16) Flash Memory Card ......................
(512K x 8 or 256K x 16) Flash Memory Card ......................
(1024K x 8 or 512K x 16) Flash Memory Card .....................
(2048K x 80r 1024K x 16) Flash Memory Card ....................
(64K x 16) OTP PROM Memory Card ............................
(128K x 16) OTP PROM Memory Card ...........................
(64K x 8) OTP PROM Memory Card .............................
(128K x 8) OTP PROM Memory Card ............................
(256K x 8) OTP PROM Memory Card ............................
8-35
8-45
8-45
8-45
8-45
8-65
8-65
8-65
8-65
8-65
xi
CHAPTER 9.
MILITARY PRODUCTS
Military Introduction ............................................................................... 9-3
DYNAMIC RAMS
SMJ44C256
SMJ4C1024
SMJ44100
SMJ44400
SMJ416100
SMJ416400
SMJ417100
SMJ417400
SMJ417400
1 048 576-bit
1 048576-bit
4 197 304-bit
4 197 304-bit
16777 216-bit
16 777 216-bit
16777 216-bit
16777 216-bit
16777 216-bit
(256K x 4) Enhanced Page Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 9-5
(1 024K xi) Enhanced Page Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 9-27
(4096K x 1) Enhanced Page Mode ............................... 9-47
(1 024K x 4) Enhanced Page Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 9-67
(16 385K xi) Enhanced Page Mode ............................. 9-87
(4096K x 4) Enhanced Page Mode .............................. 9-105
(16 385K xi) Enhanced Page Mode ............................ 9-125
(4096K x 4) Enhanced Page Mode .............................. 9-143
(4096K x 4) Enhanced Page Mode .............................. 9-143
1 048 576-bit
1 048576-bit
4 194 304-bit
4194304-bit
(256K x
(256K x
(256K x
(256K x
4) Multipart Video RAM ................................
4) Multiport Video RAM ................................
16) Multiport Video RAM ...............................
16) Multiport Video RAM ...............................
9-161
9-199
9-239
9-241
131 072-bit
262 144-bit
524288-bit
4 194 304-bit
16384-bit
(16K x 8) CMOS EPROM ......................................
(32K x 8) CMOS EPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
(64K x 8) CMOS EPROM ......................................
(512K x 8) CMOS EPROM .....................................
(2K x 9) 5-V Flash EEPROM Serial JTAG Bus ....................
9-243
9-253
9-263
9-275
9-285
VIDEO RAMS
SMJ44C250
SMJ44C251
SMJ55160
SMJ55165
EPROMS
SMJ27C128
SMJ27C256
SMJ27C512
SMJ27C040
SMJ29F816
CHAPTER 10.
LOGIC SYMBOLS
Explanation of IEEE/IEC Logic Symbols for Memories ............................................... 10-3
CHAPTER 11.
QUALITY AND RELIABILITY
MOS Memory Products Division Quality and Reliability Information
CHAPTER 12.
11-3
ELECTROSTATIC DISCHARGE GUIDELINES
Guidelines for Handling Electrostatic-Discharge Devices and Assemblies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 12-3
CHAPTER 13.
MECHANICAL DATA
MOS Memory Products - Commercial ............................................................. 13-5
MOS Memory Products - Military. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 13-35
xii
General Information
1-1
1·2
General Information
Alphanumeric Index
CMS209 ..............
CMS210 ..............
CMS213 ..............
CMS214 ..............
CMS216 ..............
CMS405 ..............
CMS406 ..............
CMS407 ..............
CMS408 ..............
CMS409 ..............
CMS410 ..............
CMS68F1MB ..........
CMS68F2MB ..........
CMS68F256 ...........
CMS68F512 ...........
CMS68P1MB ..........
CMS68P1MBN ........
CMS68P256 ...........
CMS68P256N .........
CMS68P512 ...........
CMS68P512N .........
CMS88D4MB36 ........
CMS88D8MB36 ........
SMJ27C040 ...........
SMJ27C128 ...........
SMJ27C256 ...........
SMJ27C512 ...........
SMJ29F816 ...........
SMJ4C1024 ...........
SMJ416100 ...........
SMJ416400 ...........
SMJ417100 ...........
SMJ417400 ...........
SMJ44C250 ...........
SMJ44C251 ...........
SMJ44C256 ...........
SMJ44100 ............
SMJ44400 ............
SMJ55160 ............
SMJ55165 ............
8-65
8-65
8-65
8-65
8-65
8-3
8-3
8-3
8-3
8-17
8-17
8-45
8-45
8-45
8-45
8-35
8-35
8-35
8-35
8-35
8-35
8-27
8-27
9-275
9-243
9-253
9-263
9-285
9-27
9-87
9-105
9-125
9-143
9-161
9-199
9-5
9-47
9-67
9-239
9-241
Synchronous DRAM ....
TM124BBK32 ..........
TM124BBK32S . .......
TM124EU9B ...........
TM124EU9C . .........
TM124MBK36 . ........
TM124MBK36B ........
TM124MBK36C ........
TM124MBK36Q ........
TM124MBK36R ........
TM124MBK36S ........
TM124TBK40 ..........
TM124TBK40S ........
TM16100EBD9 . . . . . . .
TM16100GBD8 ........
TM248CBK32 .........
TM248CBK32S . .......
TM248NBK36B ........
TM248NBK36C ........
TM248NBK36R ........
TM248NBK36S . .......
TM248VBK40 ..........
TM248VBK40S ........
TM4100EAD9 .........
TM4100GAD8 .........
TM496TBM40 .........
TM496TBM40S ........
TM497BBK32 ..........
TM497BBK32S ........
TM497EAD9B . ........
TM497GAD8A .........
TM497MBK36A ........
TM497MBK36Q ........
TM497TBM40 .........
TM497TBM40S ........
TM893CBK32S ........
TM893VBM40 . ........
TM893VBM40 . ........
TM893VBM40S ........
TMS27C010A . ........
.
TEXAS
4-501
5-29
5-29
5-5
5-5
5-39
5-47
5-57
5-39
5-47
5-57
5-137
5-137
5-99
5-91
5-29
5-29
5-47
5-57
5-47
5-57
5-137
5-137
5-67
5-75
5-125
5-125
5-105
5-105
5-13
5-83
5-21
5-21
5-115
5-115
5-105
5-115
5-115
5-115
6-39
TMS27C020 .......
TMS27C040 .......
TMS27C128 .......
TMS27C210A ......
TMS27C240 .......
TMS27C256 .......
TMS27C400 .......
TMS27C510 .......
TMS27C512 .......
TMS27LV010A .....
TMS27PC010A ....
TMS27PC020 ......
TMS27PC040 ......
TMS27PC128 ......
TMS27PC210A ....
TMS27PC240 ......
TMS27PC256 ......
TMS27PC400 ......
TMS27PC510 ......
TMS27PC512 ......
TMS28F010 .......
TMS28F040 .......
TMS28F210 .......
TMS28F512 .......
TMS29F816 .......
TMS4C1050B ......
TMS4C1060B ......
TMS4C1070B ......
TMS416100 .......
TMS416160 .......
TMS416160P ......
TMS416400 .......
TMS416800 · ......
TMS416800P ......
TMS417400 · ......
TMS417800 · ......
TMS417800P ......
6-61
6-71
6-2
6-51
6-81
6-3
6-91
6-15
6-27
6-203
6-39
6-61
6-71
6-2
6-51
6-81
6-3
6-91
6-15
6-27
6-125
6-185
6-165
6-145
6-101
7-109
7-121
7-133
4-385
4-249
4-253
4-253
4-203
4-249
4-341
4-341
4-227
4-249
4-363
4-363
~
INSIRUMENlS
POST OFFICE BOX 1443
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1-3
General Information
TMS418160 ...........
TMS418160P ..........
TMS426100 ...........
TMS426100P ..........
TMS426160 .......... .
TMS426160P ..........
TMS426400 ...........
TMS426400P ..........
TMS426800 ...........
TMS426800P ..........
TMS427400 , ......... .
TMS427400P ..........
TMS427800 ...........
TMS427800P ..........
TMS428160 ., "' ........
TMS428160P ..........
TMS44100 ........... .
TMS44100P ...........
TMS44165 ........... .
TMS44165P ...........
TMS44400 ............
TMS44400P ...........
TMS44800 ........... .
TMS44800P ...........
TMS45160 ............
TMS45160P ............
TMS45165 ............
TMS45165P ...........
TMS46100 ............
TMS46100P ...........
TMS46400 ............
TMS46400P ...........
TMS55160 ............
TMS55165 ............
4-297
4-297
4-385
4-385
4-275
4-275
4-409
4-409
4-457
4-457
4-433
4-433
4-479
4-479
4-319
4-319
4-5
4-5
4-115
4-115
4-27
4-27
4-93
4-93
4-137
4-137
4-159
4-159
4-49
4-49
4-71
4-71
7-3
7-57
TEXAS ~
INSlRUMENlS
1-4
POST OFFICE BOX 1443
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HOUSTON, TEXAS 77001
General Information
DRAMNRAM/FMEM Ordering Information
Factory orders for 1 Meg DRAMs, VRAMs, and FMEMs described in this book should include an eight-part type
number as explained in the following example:
TMS
1. Prefix:
TMS
SMJ
4
I
4
C
256
-10
DJ
Commerical MOS
Military MOS
2. Product Family: - - - - - - - - - - - - - - - - '
4
DRAMNRAM/FMEM
3. Word Width:
Blank
Blank
4
8
16
x 1
x 4 (FMEM only)
x4
x8
x16
4. Technology:
C
CMOS
5. Density: - - - - - - - - - - - - - - - - - - - - - - - - - - '
121
1 Meg VRAM (,48C121)
1 Meg DRAM ('4C1024)
1024
128
1 Meg DRAM (,48C128)
1025
1 Meg DRAM ('4C1025)
138
1 Meg DRAM ('48C138)
1027
1 Meg DRAM (,4C1027)
251A 1 Meg VRAM (,44C251A)
1050
1 Meg FMEM (,4C1050B)
256
1 Meg DRAM (,44C256)
1060
1 Meg FMEM (,4C1060B)
260
1 Meg Parity DRAM (,44C260)
1070
1 Meg FMEM (,4C1070B)
6. Speed Designator: - - - - - - - - - - - - - - - - - - - - - - - - - '
DRAMsNRAMs
FMEMs
- 60
60 ns
-30
25 ns
- 70
70 ns
-40
30 ns
- 80
80 ns
-6050ns
-10100ns
-12
120ns
-15
150 ns
- 20
200 ns
7. Package: - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - '
Commercial (Plastic)
Military (Ceramic)
DJ
Small-Outline J-lead (SOJ)
FQ
Small-Outline leadless Chip Carrier (SOlCC)
DN
Thin Small-Outline J-Lead (ThinSOJ)
FV
Leadless Chip Carrier (CLCC)
DZ
Small-Outline J-Lead (SOJ)
HJ
Small-Outline J-Lead (SOJ)
SD
Zig-Zag In-Line (ZIP)
HK
Flatpack
N
Dual-In-Line (DIP)
HL
Low Profile Leadless Surface Mount
JD
Dual-In-Line (DIP)
SV
Zig-Zag In-Line (ZIP)
8. Temperature Range: - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - '
Commerical
Military
L
O°C to 70°C (VRAMs/FMEMs)
M
- 55°C to 125°C
Blank O°C to 70°C (DRAMs)
TEXAS
lJ1
INSTRUMENTS
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1-5
General Information
DRAM Ordering Information
Factory orders for the 4 Meg and 16 Meg DRAMs described in this book should include an eight-part type number
as explained in the following example:
TMS
4
4
I. Prefix: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _--.J!
I
TMS Commercial MOS
SMJ Military MOS
2. Product Family: - - - - - - - - - - - - - - - - - - - '
4 DRAM
.
3. Density- Refresh: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _--.J
I
00
-80
DM
2 2 Meg I K Refresh
4 4 Meg I K Refresh
5 4 Meg 512 Cycle Refresh
6 4 Meg I K Refresh 3.3 V
7 4Meg 512 Cycle Refresh 3.3V
16 16 Meg 4K Refresh 5 V
17 16 Meg 2K Refresh 5 V
18 16 Meg lK Refresh 5 V
26 16 Meg 4K Refresh 3.3 V
27 16 Meg 2K Refresh 3.3 V
28 16 Meg I K Refresh 3.3 V
4. Organization -I/O: - - - - - - - - - - - - - - - - - - - - - - - - - '
10 x I
Std
90 x9
Std
26 x 2
Quad-CAS
91 x9
WPB
40 x 4
Std
16 x 16 Std
41 x4
WPB
17 x 16 WPB
46 x 4
Quad-CAS
18 xl8 Std
80 x8
Std
19 x 18 WPB
81 x8
WPB
5. Functional Mode/Options: - - - - - - - - - - - - - - - - - - - - - - - - - - '
o Enhanced Page Mode
2 SCD 2 CAS (x16 and xl8 Devices)
o Enhanced Page Mode
3 Serial Mode
2 CAS (x16 and xl8 Devices)
5 Enhanced Page Mode
o Enhanced Page Mode
2 WE (x16 and xl8 Devices)
4 CAS (Quad-CAS Devices)
6 Burst Mode
I Nibble Mode
7 SCD With Burst Mode
2 Static Column Decode Mode (SCD)
8 SCD 2 WE (x16 and xl8 Devices)
6. S p e e d D e s i g n a t o r : - - - - - - - - - - - - ' - - - - - - - - - - - - - - - - - - - - '
- 60 60 ns
-10 lOOns
- 70 70 ns
-12 120ns
-8080ns
-15 150ns
7.Package:---------------------~---------------~
Commercial (Plastic)
Military (Ceramic)
DGA 300-mil Thin Small Outline (TSOP) (26-lead)
HM Small-Outline leadless Chip Carrier (SOlCC)
DGB 300-mil Reverse lead Thin Small Outline (TSOP)
HJ Small-Outline J-lead (SOJ)
(26-lead)
HR Flatpack
DGC 400-mil Thin Small Outline (TSOP) (28-lead)
JD Side-Brazed Dual-In-Line
DGD 400-mil Reverse lead Thin Small Outline (TSOP)
(28-lead)
DGE 400-mil Thin Small Outline (TSOP) (44-lead)
DGF 400-mil Reverse lead Thin Small Outline (TSOP)
(44-lead)
DC 400-mil Thin Small Outline (TSOP) (50/44-lead)
0.8 mm pitch
DE 400-mil Thin Small Outline (TSOP) (32-lead)
1.27 mm pitch
DJ 300-mil Small Outline J-lead (SOJ) (26/24-lead)
DM 350-mil Small Outline J-lead (SOJ)
DN Thin Small Outline J-lead (SOJ)
DZ 400-mil Small Outline J-Lead (SOJ)
RE 400-mil Small Outline J-lead (SOJ) (50-mil pitch)
SD Zig-Zag In-Line (ZIP)
RVA Vertical Package (VPAK)
8. Temperature Range: - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - '
Commercial
Military
M - 55°C to 125°C
Blank O°C to 70°C
TEXAS .J!}
INSIRUMENlS
1-6
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
General Information
Standard DRAM Module Ordering Information
Factory orders for the standard DRAM Modules described in this book should include a seven-part type number as
explained in the following example:
TM
1. Prefix: _ _ _ _ _ _ _ _ _ _ _ _ _ _1
024
E
AD
9
-10
TM
Commerical TI MOS Module
2. Memory Device: _ _ _ _ _ _ _ _ _ _ _ _ _ _- '
024
4100
16100
1 Meg DRAM, Enhanced Page Mode
4 Meg DRAM, Enhanced Page Mode
16 Meg DRAM, Enhanced Page Mode
3. Pinout Configuration: - - - - - - - - - - - - - - -....
E
G
4. Board Dimensions: - - - - - - - - - - - - - - - - - - - '
AD
BD
5. Word Width Output: - - - - - - - - - - - - - - - - - - - - - - '
8
x8
9
x9
6. Speed Designator: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _---1
-6
60 ns
-70
70 ns
-8080ns
-10
100ns
7. Temperature Range: - - - - - - - - - - - - - - - - - - - - - - - - - - - - '
Blank O'C to 70'C
L
O'C to 70'C (1 Meg only)
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
1-7
General Information
Differentiated DRAM Module Ordering Information
Factory orders for the mixed DRAM Modules described in this book should include an eight-part type number as
explained in the following example:
TM
1. Prefix: _ _ _ _ _ _ _ _ _ _ _---'1
TM
124
E
AO
9
B
-Z
-10
Commerical TI MOS Module
2. Density:
256
496
256K
4 Meg
512K
512
497
4 Meg - 2K Refresh
124
8 Meg
1 Meg
892
248
8 Meg - 2K Refresh
2 Meg
893
3. Pinout Configuration: - - - - - - - - - - - - - - - '
B
G
M
C
K
T
E
L
V
4. Board Dimensions: _ _ _ _ _ _ _ _
~
_ _ _ _ _ _ _...J
U
AD
BK
BM
5. Word Width Output: - - - - - - - - - - - - - - - - - - - - '
8
9
x8
x9
32
x 32
36
x 36
40
x 40
6. Devices U s e d : - - - - - - - - - - - - - - - - - - - - - - - - l
Blank 8 - '44C256s ('256BBK32)
Blank 16 - '44C256s (,512CBK32)
Blank 8 - '44400s ('124BBK32)
Blank 10- '44400s ('124TBK40)
Blank 20 - '44400s (,248VBK40)
Blank 10 - '416400s (,496TBM40)
Blank 10 - '417400s (,497TBM40)
Blank 20 - '416400s ('892VBM40)
Blank 20 - '417400s ('893VBM40)
A
2 - '44400s ('124GU8A)
A
8 - '44400s + 4 '4Cl024s ('124MBK38A)
B
2 - '44400s + 1 '4Cl024 ('124EAD9B/'EAD9BZ)
B
8 - '44C256s + 1 '44C260 (,256KBK36B)
B
16 - '44C256s + 2 '44C260s ('512LBK36B)
B
8 - '44400s + 1 '44460 (,124MBK36B)
B
16 - '44400s + 2 '44460s (,248NBK36B)
C
2 - '44C256s + 1 '4Cl024 ('256GU9C)
C
2 - '44400s + 1 '44100 (,124EAD9C/'EAD9CZ)
C
2 - '44400s + 1 '44100 ('124EU9C/,EU9CZ)
C
8 - '44C256s + 2 '44C260s ('256KBK36C)
C
16 - '44C256s + 4 '44C260s ('512LBK36C)
7. Relaxed Thickness T o l e r a n c e : - - - - - - - - - - - - - - - - - - - - - - - '
Blank
Standard
Z
Relaxed Board Thickness
8. Speed D e s i g n a t o r : - - - - - - - - - - - - - - - - - - - - - - - - - - - - '
VCC ±5%
VCC±10%
-6
60 ns
-6060ns
-7
70 ns
-7070ns
-8
80 ns
-8080ns
-100 100 ns
-10
lOOns
9. Temperature Range: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _..J
Blank O°C to 70°C
TEXAS ~
INSTRUMENTS
1-8
POST OFFICE BOX 1443
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HOUSTON. TEXAS 77001
General Information
Nonvolatile Ordering Information
Factory orders for EPRDMs, DIPs, and Flash Memories described in this book should include a nine-part type
number as explained in the following example:
TMS
1. Prefix:
TMS
SMJ
27
P
C
512
-10
FM
L
4
I
Commerica IMOS
MilitaryMO S
2. Product Family: ""7'".- 27
EPROM/OTP
28
12-V Flash EPROM
29
5-V Flash EEPROM
3. Erasability: - - - - P
Non-erasable (One-Time Programmable)
Blank
Erasable
4. Technology: - - - CMOS
C
CMOS Flas h EEPROM
F
LV
LowVoltag e
5. Density: - - - - 010A
816
16K
128
210A
128K
020
256
256K
257
040
256K
510
240
512K
512
400
512K
6. Speed Designator:
80 ns
- 8, - 80
-10,-100
lOOns
120 ns
- 12, - 120
150ns
-1,-15,-1 50
1 Meg
1 Meg
2 Meg
4 Meg
4Meg
4 Meg
170 ns
200 ns
250 ns
300 ns
-1,-17,-170
- 2, - 20, - 200
Blank, - 25, - 250
- 30, - 300
7. Package: - - - - DD
Plastic Thin Small-Outline (TSOP)
DU
Plastic Thin Small-Outline (TSOP, Reverse Form)
FM
Plastic Chip Carrier (32-Pin) Rectangular
FN
Plastic Chip Carrier (44-Pin) Square
J
Ceramic Du al-In-Line (DIP)
N
Plastic DuaI-In-Line (DIP)
PM
Square Quad Flat Package (SQFP)
8. Temperature Range: Commerical
L
O'C to 70'C
E
- 40'C to 85'C
Q
- 40'C to 125'C
T
- 40'C to 110'C
9. 168 Hour Burn-in Option:
Commerical
4
168 Hour Burn-in
Blank No Burn-in
Military
M
- 55'C to 125'C
Military
Blank
5004 Processing
TEXAS ~
INSIRUMENTS
POST OFFICE BOX 1443
•
HOUSTON. TEXAS 77001
1-9
General Information
VRAM Ordering Information
Factory orders for 4 Meg VRAMs described in this book should include an eight-part type number as explained in the
following example:
TMS
1. Prefix:
TMS
SMJ
5
5
5
-80
DGH
Commerical MOS
Military MOS
2. Product Family: - - - - - - - - ' - - - '
5
VRAM
3. Density
4
5
16
17
16
I
Refresh:
4 Meg
4 Meg
16 Meg
16 Meg
I
lK Refresh
512 Cycle Refresh
4K Refresh
2K Refresh
4. Organization
Features:
40
x 4
Standard
41
x 4
Enhanced Page Mode
80
x 8
Standard
81
x 8
Enhanced Page Mode
16
x16
Standard
17
x16
Enhanced Page Mode
5. Functional Mode Options: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _--1
o
1
5
6
Enhanced Page Mode
Hyper Page Mode
Enhanced Page Mode
Hyper Page Mode
2 CAS
2 CAS
2 WE
2 WE
6. Speed Designator: - - - - - - - - - - - - - - - - - - - - - - - - '
-60
60 ns
-70
70 ns
-80
80 ns
-10
100 ns
7. Package: - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - '
DGH
Super Small-Outline (SSOP)
8. Temperature Range: - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - '
Commerical
Military
O·C to 70·C
Blank
M
- 55·C to 125·C
TEXAS ~
INSTRUMENTS
1-10
POST OFFICE BOX 1443
•
HOUSTON. TEXAS 77001
General Information
Memory Card Ordering Information t
Factory orders for memory cards (excluding CMS401-CMS41 0 and CMS209-CMS216 OTP PROM memory cards)
described in this book should include a nine-part type number as explained in the following example:
eMS
68
1 MB
F
I
1. Prefix:
CMS
Card Module Standard
CMP
Prototype Card Module
2. Number of Pins: - - - - - - - '
60
68
88
3. Memory Type: - - - - - - - - - - - - '
D
DRAM
F
Flash EPROM
P
OTPPROM
SRAM
S
4. Total Density: - - - - - - - - - - - - - - - '
256
256K Byte
512
512KByte
1 MB
1 M Byte
2 MB
2 M Byte
4 MB
4 M Byte
8 MB
8 M Byte
5. Width: - - - - - - - - - - - - - - - - - - - - - '
Blank
User Selectable (x 8/x 16)
x 8
8
x 9
9
16
x16
18
x18
32
x32
36
x36
N
-250
6. Power: - - - - - - - - - - - - - - - - - - - - - - - - - '
Blank
Standard
L
Low Power
Super-Low Power
S
7. Differentiator: - - - - - - - - - - - - - - - - - - - - - - - - - - '
A, B, C, etc.
Alpha characters will be used when necessary
to differentiate between similar card types.
8. Attribute Memory: - - - - - - - - - - - - - - - - - - - - - - - - - - - - '
Blank
Attribute Memory
N
No Attribute Memory
9.Speed:-----------------------------------'
-70
70 ns
-80
80 ns
-200
200 ns
-250
250 ns
t This is the new memory card part numbering system. This system excludes existing DRAM memory cards CMS401-CMS410 and OTP PROM
memory cards CMS209-CMS216.
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443
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HOUSTON. TEXAS 77001
1-11
General Information
TEXAS ~
INSIRUMENTS
1-12
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
Selection Guide
2-1
2-2
Selection Guide
DRAM
DENSITY
ORGANIZATION
(WORDS x BITS)
DEVICE NUMBER
MAX
ACCESS
TIME
(ns)
POWER
SUPPLY
(V)
MAX POWER
DISSIPATION
ACTIVE
STANDBY
(mW)
(mW)
PINS
PACKAGEt
NOTES
PAGE
1024K)( 1
SMJ4Cl024-80
SMJ4Cl024-10
SMJ4Cl024-12
SMJ4Cl024-15
80
100
120
150
5± 10%
413
385
330
303
17
18,20,
26
Fa, HJ,
HK, HL,
JD,SV
Military
CMOS
Enhanced
Page Mode
9-27
256K x 4
SMJ44C256-80
SMJ44C256-10
SMJ44C256-12
SMJ44C256-15
80
100
120
150
5±10%
440
385
330
303
17
20,26
Fa, HJ,
HK, HL,
JD,SV
Military
CMOS
Enhanced
Page Mode
9-5
TMS441 00-60
TMS441 00-70
TMS441 00-80
60
70
80
5 ± 10%
523
468
413
11
20,26
DGA
DGB, DJ,
SD
CMOS
Enhanced
Page Mode
4-5
TMS44100P-60
TMS44100P-70
TMS44100P-80
60
70
80
5± 10%
523
468
413
11
20,26
DGA
DGB, DJ,
So.
CMOS
Enhanced
Page Mode
Low Power
4-5
SMJ44100-80
SMJ441 00-1 0
SMJ44100-12
80
100
120
5± 10%
468
440
385
22
18,20,
26
HM, HR,
JD
Military
CMOS
Enhanced
Page Mode
9-47
TMS461 00-70*
TMS461 00-80*
TMS461 00-1 0*
70
80
100
3.3 ± 10%
216
180
144
3.6
20,26
o.GA,
DGB, DJ,
SD
CMOS
Enhanced
Page Mode
LowVoHage
4-49
TMS46100P-70*
TMS46100P-80*
TMS461OOP-l0*
70
80
100
3.3 ± 10%
216
180
144
3.6
20,26
o.GA,
DGB, DJ,
So.
CMOS
Enhanced
Page Mode
Low Voltage
Extended
Refresh
4-49
TMS46400-70*
TMS46400-80*
TMS46400-10*
70
80
100
3.3 ± 10%
252
216
180
7.2
20,26
o.GA,
o.GB, DJ,
So.
CMOS
Enhanced
Page Mode
Low Voltage
4-71
TMS46400P-70*
TMS46400P-80*
TMS46400P-l0*
70
80
100
3.3± 10%
252
216
180
20,26
DGA,
o.GB, o.J,
SD
CMOS
Enhanced
Page Mode
Low Voltage
Extended
Refresh
4-71
1024K
4096Kx 1
4096K
1024K x 4
7.2
t DGA Plastic Small-Outllne-Package (SOP)
o.GB
o.J
DN
Fa
HJ
HK
HL
HM
HR
JD
N
SD
SV
Plastic Small-Outline Reverse Form Package (SOP)
Plastic Small-Outline J-Lead (SOJ)
Plastic Thin Small-Outline J-Lead (ThinSOJ)
Small-Outline Leadless Ceramic Chip Carrier (Military) (SOLCC)
Leaded Ceramic Chip Carrier (Military)
Flatpack (Military)
Small-Outline Leadless Ceramic Chip Carrier (Military)
Small-Outline Leadless Ceramic Chip Carrier (Military) (SOLCC)
Flatpack (Military)
Ceramic Sidebrazed Dual In-Line Package (Military) (DIP)
Plastic Dual In-Line Package (DIP)
Plastic Zig-Zag In-Line Package (ZIP)
Ceramic Zig-Zag-In-Line Package (Military)
* Advance Information for product under development by TI
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443
•
HOUSTON. TEXAS 77001
2-3
Selection Guide
DRAM
DENSITY
ORGANIZATION
(WORDS x BITS)
512K x 6
256K x 16
4096K
1024K x 4
DEVICE NUMBER
163B4Kx 1
and
16384Kx4
POWER
SUPPLY
M
MAX POWER
DISSIPATION
ACTIVE
(mW)
STANDBY
(mW)
PACKAGEt
NOTES
PAGE
60
70
80
100
5",10%
660
605
550
495
11
28
DZ, DGC
CMOS
Enhanced
Page Mode
4-93
TMS44800P-60
TMS44800P-70
TMS44800P-80
TMS44800P-l0
60
70
80
100
5",10%
660
605
550
495
11
28
DZ, DGC
CMOS
Enhanced
Page Mode
low Power
4-93
TMS44165-70:l:
TMS44165-80:l:
TMS44165-10*
70
80
100
5",10%
660
578
523
11
40,44
DZ, DGE
CMOS
Enhanced
Page Mode
4-115
TMS44165P-70:l:
TMS44165P-80*
TMS44165P-l0:l:
70
80
100
5",10%
660
578
523
11
40,44
DZ, DGE
CMOS
Enhanced
Page Mode
Low Power
4-115
TMS45160-70
TMS45160-80
TMS45160-10
70
80
100
5% 10%
880
770
660
11
40,44
DZ, DGE
CMOS
Enhanced
Page Mode
4-137
TMS45160P-70
TMS45160P-BO
TMS45160P-l0
70
BO
100
5",10%
880
770
660
11
40,44
DZ, DGE
CMOS
Enhanced
Page Mode
low Power
4-137
TMS45165-70*
TMS45165-80:l:
TMS45165-10*
70
BO
100
5",10%
880
770
660
11
40,44
DZ, DGE
CMOS
Enhanced
Page Mode
4-159
TMS45165P-70*
TMS45165P-80:l:
TMS45165P-l0*
70
BO
100
5",10%
880
770
660
11
40,44
DZ, DGE
CMOS
Enhanced
Page Mode
low Power
4-159
TMS44400-60
TMS44400-70
TMS44400-80
60
70
BO
5", 10%
550
495
440
11
20,26,
20,26,
20
DJ, DGA,
DGB, SD
CMOS
Enhanced
Page Mode
4-27
TMS44400P-60
TMS44400P-70
TMS44400P-BO
60
70
80
5",10%
550
495
440
11
20,26,
20,26,
20
DJ, DGA,
DGB, SD
CMOS
Enhanced
Page Mode
Low Power
4-27
80
100
120
5% 10%
22
20,20,
20,20
JD, HM,
HR
Military
CMOS
Enhanced
Page Mode
9-67
-
24,26
DJ, DGA,
DGB
CMOS
Enhanced
Page Mode
4-249
Product Preview:
TMS416100,
TMS416400, and
TMS417400
60
70
80
5± 10%
468
440
358
440
385
330
t DGA Plastic Smail-Outline-Package (SOP)
DGB Plastic Small-Outline Reverse Form Package (SOP)
DGC Plastic Thin Small-Outline Package
DGE Plastic Surface Mount Thin Small-Outline Package (TSOP)
DJ
Plastic Small-Outline J-lead (SOJ)
DZ Plastic Small-Outline J-lead (SOJ)
HM Small-Outline Leadless Ceramic Chip Carrier (Military) (SOlCC)
HR Flatpack (Military)
JD Ceramic Sidebrazed Dual In-Line Package (Military) (DIP)
SD Plastic Zig-Zag In-Line Package (ZIP)
* Advance Information for product under development by TI
TEXAS ~
INSTRUMENTS
2-4
PINS
TMS44800-60
TMS44800-70
TMS44800-80
TMS44800-10
SMJ44400-80
SMJ44400-10
SMJ44400-12
16384K
MAX
ACCESS
TIME
(no)
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
Selection Guide
DRAM
DENSITY
ORGANIZATION
(WORDS x BITS)
DEVICE NUMBER
MAX
ACCESS
TIME
(ns)
16384Kx 1
16384K
4096K x 4
POWER
SUPPLY
M
ACTIVE
(mW)
STANDBY
(mW)
PINS
PACKAGEt
NOTES
PAGE
TMS4161 00-60
TMS4161 00-70
TMS4161 00-80
60
70
80
5 ± 10%
495
440
385
11
24,28
DGC,
DGD, DZ
CMOS
Enhanced
Page Mode
4-385
SMJ4161 00-60
SMJ4161 00-70
SMJ4161 00-80
SMJ4161 00-1 0
60
70
80
100
5± 10%
495
440
385
330
11
24,28
FNC,HKB
Military
Enhanced
Page Mode
9-87
SMJ4171 00-60
SMJ4171 00-70
SMJ4171 00-80
SMJ417100-10
60
70
80
100
5±10%
605
550
495
440
11
24,28
FNC, HKB
Military
Enhanced
Page Mode
9-125
TMS416400-60
TMS416400-70
TMS416400-80
60
70
80
5± 10%
495
440
385
11
24,28
DGC,
DGD, DZ
CMOS
Enhanced
Page Mode
4-203
SMJ416400-60
SMJ416400-70
SMJ416400-80
SMJ416400-10
60
70
80
100
5 ± 10%
495
440
385
330
11
24,28
FNC, HKB
Military
Enhanced
Page Mode
9-105
TMS417400-60
TMS417400-70
TMS417400-80
60
70
80
5 ± 10%
495
440
385
11
24,28
DGC,
DGD, DZ
CMOS
Enhanced
Page Mode
4-227
SMJ417400-60
SMJ417400-70
SMJ417400-80
SMJ417400-10
60
70
80
100
5±10%
605
550
495
440
11
24,28
FNC, HKB
Military
Enhanced
Page Mode
9-143
TMS426400-60§
TMS426400-70§
TMS426400-80§
TMS426400-10§
60
70
80
100
3.3 ± 10%
252
216
180
144
3.6
24,26
DGA,
DGB, DJ
CMOS
Enhanced
Page Mode
low Voltage
4-409
TMS426400P-60§
TMS426400P-70§
TMS426400P-80§
TMS426400P-l0§
60
70
80
100
3.3 ± 10%
252
216
180
144
3.6
24,26
DGA,
DGB, DJ
CMOS
Enhan0ed
Page Mode
low Voltage
low Power
4-409
TMS427400-60§
TMS427400-70§
TMS427400-80§
TMS427400-10§
60
70
80
100
3.3 ± 10%
252
216
180
144
3.6
24,26
DGA,
DGB, DJ
CMOS
Enhanced
Page Mode
low Voltage
4-433
t DGA
Plastic Small-Outline-Package (SOP)
DGB Plastic Small-Outline Reverse Form Package (SOP)
DGC Plastic Thin Small-Outline Package (TSOP)
DGD Plastic Thin Small-Outline Reverse Form Package (TSOP)
DGE Plastic Surface Mount Thin Smail-Outline Package (TSOP)
DJ
Plastic Small-Outline J-lead (SOJ)
DZ Plastic Small-Outline J-lead (SOJ)
FNC Small-Outline Leadless Chip Carrier (Military) (SOlCC)
HKB Flatpack (Military)
HJ Ceramic Small-Outline leadless J-lead (Military) (SOlCC)
HM Small-Outline Leadless Ceramic Chip Carrier (Military) (SOlCC)
HR Flatpack (Military)
JD Ceramic Sidebrazed Dual In-Line Package (Military) (DIP)
SD Plastic Zig-Zag In-Line Package (ZIP)
Advance Information for product under development by TI
§ Product preview documents contain information on products in the formative or design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
*
TEXAS ~
INsrRUMENTS
POST OFFICE BOX 1443
•
HOUSTON. TEXAS 77001
2-5
Selection Guide
DRAM
DENSITY
ORGANIZATION
(WORDS x BITS)
16384K
2048Kx 8
1024Kx16
MAX POWER
DISSIPATION
POWER
SUPPLY
PAGE
DGA,
DGB, DJ
CMOS
Enhanced
Page Mode
Low Voltage
Low Power
4-433
28,
32
DE,DZ
CMOS
Enhanced
Page Mode
4-341
11
28,
32
DE,DZ
CMOS
Enhanced
Page Mode
Low Power
4-341
688
633
578
11
28,
32
DE,DZ
CMOS
Enhanced
Page Mode
4-363
5",10%
688
633
578
11
28,
32
DE,DZ
CMOS
Enhanced
Page Mode
Low Power
4-363
3.3", 10%
288
252
3.6
28,
32
DE,DZ
CMOS
Enhanced
Page Mode
Low Voltage
4-457
70
80
3.3", 10%
288
252
3.6
28,
32
DE,DZ
CMOS
Enhanced
Page Mode
Low Voltage
Low Power
4-457
TMS427800-70i
TMS427800-BOi
70
80
3.3",10%
414
378
3.6
28,
32
DE,DZ
CMOS
Enhanced
Page Mode
Low Voltage
4-479
TMS427800P-70i
TMS417800P-80i
70
80
3.3 ± 10%
414
378
3.6
28,
32
DE,DZ
CMOS
Enhanced
Page Mode
Low Voltage
Low Power
4-479
TMS416160'60i
TMS416160-7ot
TMS416160-8ot
60
70
80
5",10%
495
440
385
11
42,
44,
50
DC,RE
CMOS
Enhanced
Page Mode
4-253
TMS416160P-60i
TMS416160P-70i
TMS416160P-80i
60
70
80
5",10%
495
440
385
11
42,
44,
50
DC, RE
CMOS
Enhanced
Page Mode
Low Power
4-253
STANDBY
(mW)
PINS
M
ACTIVE
(mW)
60
70
80
100
3.3 ± 10%
252
216
180
144
3.6
24,
26
TMS416800-60i
TMS416800-70i
TMS416800-80i
60
70
80
5 ± 10%
495
440
385
11
TMS416800P-60i
TMS416800P-70i
TMS416800P-80i
60
70
5",10%
80
495
440
385
TMS417800-60i
TMS417800-70i
TMS417800-80i
60
70
80
5",10%
TMS417800P-60i
TMS417800P-70i
TMS417800P-80i
60
70
80
TMS426800-70i
TMS426800-80i
70
80
TMS426800P-7ot
TMS426800P-80i
TMS427400P-60§
TMS427400P-70§
TMS427400P-80§
TMS427400P-l0§
4096Kx 4
MAX
ACCESS
TIME
(n8)
NOTES
DEVICE NUMBER
t DGA
PACKAGEt
Plastic Smail-Outline-Package (SOP)
DGB Plastic Small-Outline Reverse Form Package (SOP)
DC Plastic Surface Mount Thin Small-Outline Package (TSOP)
DE Plastic Surface Mount Thin Small-Outline Package (TSOP)
DJ Plastic Small-Outline J-Lead (SOJ)
DZ Plastic Small-Outline J-Lead (SOJ)
RE Plastic Surface Mount Small-Outline J-Lead Package (SOJ)
i Advance Information for product under development by TI
§ Product preview documents contain information on products in the formative or design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
TEXAS ~
INSTRUMENTS
2-6
POST OFFICE BOX 1443 •
HOUSTON. TEXAS nOOl
Selection Guide
DRAM (concluded)
DENSITY
ORGANIZATION
(WORDS x BITS)
MAX
ACCESS
TIME
DEVICE NUMBER
(ns)
(V)
ACTIVE
STANDBY
(mW)
(mW)
PINS
PACKAGEt
NOTES
PAGE
TMS418160-601:
TMS418160-701:
TMS418160-801:
60
70
80
5±10%
990
880
770
11
42,
44,50
DC,RE
CMOS
Enhanced
Page Mode
4-297
TMS418160P-601:
TMS418160P-701:
TMS418160P-801:
60
70
80
5± 10%
990
880
770
11
42,
44,50
DC,RE
CMOS
Enhanced
Page Mode
Low Power
4-297
TMS426160-701:
TMS426160-801:
70
80
3.3 ± 10%
288
252
3.6
42,
44,50
DC, RE
CMOS
Enhanced
Page Mode
Low Voltage
4-275
TMS426160P-701:
TMS426160P-801:
70
80
3.3 ± 10%
288
252
3.6
42,
44,50
DC, RE
CMOS
Enhanced
Page Mode
Low Voltage
Low Power
4-275
TMS428160-701:
TMS428160-801:
70
80
3.3 ± 10%
TBD
3.6
42,
44,50
DC,RE
CMOS
Enhanced
Page Mode
Low Voltage
4-319
TMS428160P-701:
TMS428160P-801:
70
80
3.3 ± 10%
TBD
3.6
42,
44,50
DC,RE
CMOS
Enhanced
Page Mode
Low Voltage
Low Power
4-319
TMS4261 00-601:
TMS4261 00-701:
TMS4261 00-80*
TMS4261 00-1 01:
60
70
80
100
3.3 ± 10%
252
216
180
144
3.6
24,26
DGA,
DGB, DJ
CMOS
Enhanced
Page Mode
Low Voltage
4-385
16Kx 1
TMS426100p-eo1:
TMS426100P-70*
TMS426100P-801:
TMS426100P-101:
eo
70
80
100
3.3 ± 10%
252
216
180
144
3.6
24,26
DGA,
DGB, DJ
CMOS
Enhanced
Page Mode
Low Voltage
Low Power
4-385
1M Byte x 2
SDRAM-6§
SDRAM-8§
SDRAM-10§
N/A
3.3 ± 10%
TBD
TBD
44
DGE
Synchronous
DRAM
4-501
1024K x 16
16384K
16385K
MAX POWER
DISSIPATION
POWER
SUPPLY
t Advance InformatIOn for product under development by TI
t DC
Plastic Surface Mount Thin Small-Outline Package (TSOP)
DGA Plastic Small-Outline-Package (SOP)
DGB Plastic Small-Outline Reverse Form Package (SOP)
DGE Plastic Surface Mount Thin Small-Outline Package (TSOP)
DJ
Plastic Small-Outline J-Lead (SOJ)
RE Plastic Surface Mount Small-Outline J-Lead Package (SOJ)
* Advance Information for product under development by TI
§ Product preview documents contain information on products in the formative or design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
TEXAS ~
INsrRUMENTS
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
2-7
Selection Guide
DRAM Module
DENSITY
9216K
ORGANIZATION
(WORDS. BITS)
1024K x 9
4096K x 9
4096K x 8
32768K
1024K x 32
4096Kx 9
MAX
ACCESS
TIME
(ns)
DEVICE NUMBER
1024K x 36
40 960K
1024K x 40
M
MAX POWER
DISSIPATION
ACTIVE
(mW)
STANDBY
(mW)
PACKAGE
PAGE
60
70
80
100
5±5%
5± 10%
5± 10%
5 ± 10%
1496
1403
1238
1073
32
33
33
33
30
Single-Sided
Socketable
5-5
TMI24EU9C-6
TM124EU9C-70
TM 124EU9C-80
TM124EU9C-10
60
70
80
100
5±5%
5± 10%
5±10%
5±10%
1496
1403
1238
1073
32
33
33
33
30
Single-Sided
Socketable
5-5
TM497EAD9B-60t
TM497EAD9B-70t
TM497EAD9B-80t
TM497EAD9B-10t
60
70
80
100
5±10%
1843
1678
1513
1348
17
30
Single-Sided
Socketable
5-13
TM497GAD8A-SOt
TM497GAD8A-70t
TM497GAD8A-80t
TM497GAD8A-10t
60
70
80
100
5 ± 10%
1320
1210
1100
990
22
30
Single-Sided
Socketable
5-83
TM4100GAD8-S0
TM4100GAD8-70
TM4100GAD8-80
60
70
80
5 ± 10%
3990
3740
3300
88
30
Single-Sided
Socketable
5-75
TM 124BBK32-60
TM124BBK32-70
TM124BBK32-80
60
70
80
5± 10%
4620
3960
3520
88
72
Single-Sided,
Socketable
5-29
TM 124BBK32S-S0
TM124BBK32S-70
TM124BBK32S-80
60
70
80
5± 10%
4620
3960
3520
88
72
Single-Sided
Socketable
Solder-Tabbed
5-29
TM4100EAD9-60
TM4100EAD9-70
TM4100EAD9-80
60
70
80
5±10%
5198
4455
3960
99
30
Single-Sided
Socketable
5-67
TMI24MBK3S-6
5±5%
5± 10%
5±10%
6405
5720
5170
126
132
132
72
Double-Sided
Socketable
5-39
TM124MBK36-80
60
70
80
TM124MBK36Q-6
TM124MBK36Q-70
TM124MBK36Q-80
60
70
80
5±5%
5± 10%
5± 10%
6405
5720
5170
126
132
132
72
Double-Sided
Socketable
Solder-Tabbed
5-39
TM124MBK36B-60t
TM124MBK36B-70t
TM124MBK36B-80t
60
70
80
5±10%
5198
4455
3960
99
72
Single-Sided
Socketable
Gold-Tabbed
5-47
TM124MBK36R-60t
TM124MBK36R-70t
TM124MBK3SR-80t
60
70
80
5±10%
5198
4455
3960
99
72
Single-Sided
Socketable
Solder-Tabbed
5-47
TM124MBK36C-60
TMI24MBK3SC-70
TM124MBK36C-80
60
70
80
5± 10%
5775
4950
4400.
110
72
Single-Sided
Socketable
Gold-Tabbed
5-57
TM124MBK36S-60
TM124MBK36S-70
TM124MBK36S-80
60
70
80
5± 10%
5775
4950
4400
110
72
Single-Sided
Socketable
Solder-Tabbed
5-57
TM124TBK40-60t
TMI24TBK40-70t
TMI24TBK40-80t
60
70
80
5±10%
5225
4675
4125
220
72
Single-Sided
Socketable
5-137
t Advance Information for product under development by TI
TEXAS ~
INSTRUMENTS
2-8
PINS
TM124EU9B-6
TM124EU9B-70
TM124EU9B-60
TM124EU9B-l0
TM124MBK36~70
36864K
POWER
SUPPLY
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
Selection Guide
DRAM Module
DENSITY
65536K
73728K
81920K
ORGANIZATION
(WORDS x BITS)
POWER
SUPPLY
M
MAX POWER
DISSIPATION
ACTIVE
STANDBY
(mW)
(mW)
PINS
PACKAGE
PAGE
TM248CBK32-60
TM24BCBK32-70
TM248CBK32-80
60
70
80
5± 10%
4708
4048
3608
176
72
Double-Sided
Socketable
Gold-Tabbed
5-29
TM248CBK32S-60
TM24BCBK32S-70
TM248CBK32S-80
60
70
80
5±10%
4708
4048
3608
176
72
Double-Sided
Socketable
Solder-Tabbed
5-29
TM248NBK36B-60t
TM24BNBK36B-70t
TM248NBK36B-80t
60
70
80
5± 10%
5297
4554
4059
198
72
Double-Sided
Socketable
Gold-Tabbed
5-47
TM248NBK36R-60t
TM248NBK36R-70t
TM248NBK36R-80t
60
70
80
5±10%
5297
4554
4059
198
72
Double-Sided
Socketable
Solder-Tabbed
5-47
TM24BNBK36C-60
TM24BNBK36C-70
TM248NBK36C-80
60
70
80
5±10%
58B5
5060
4510
220
72
Double-Sided
Socketable
Gold-Tabbed
5-57
TM248NBK36S-60
TM248NBK36S-70
TM248NBK36S-80
60
70
80
5 ± 10%
5885
5060
4510
220
72
Double-Sided
Socketable
Solder-Tabbed
5-57
2048K x 40
TM248VBK40-60t
TM248VBK40-70t
TM248VBK40-80t
60
70
80
5± 10%
5335
4785
4235
220
72
Double-Sided
Socketable
5-137
4096K x 32
TM497BBK32-60t
TM497BBK32-70t
TM497BBK32-80t
60
70
80
5± 10%
5280
4840
4400
88
72
Double-Sided
Socketable
5-105
16384Kx8
TM16100GBD8-60t
TM16100GBD8-70t
TM16100GBD8-80t
TM16100GBD8-10t
60
70
80
100
5± 10%
3960
3520
3080
2640
88
30
Double-Sided
Socketable
5-91
16 384K x 9
TM16100EBD9-60t
TM16100EBD9-70t
TM16100EBD9-80t
TM16100EBD9-10t
60
70
80
100
5± 10%
4455
3960
3465
2970
99
30
Double-Sided
Socketable
5-99
TM497MBK36A-60t
TM497MBK36A-70t
TM497MBK36A-80t
60
70
80
5± 10%
8140
6820
6160
132
72
Double-Sided
Socketable
5-21
TM497MBK36Q-60t
TM497MBK36Q-70t
TM497MBK36Q-80t
60
70
80
5± 10%
8140
6820
6160
132
72
Double-Sided
Socketable
Solder-Tabbed
5-21
TM496TBM40-60t
TM496TBM40-70t
TM496TBM40-80t
60
70
80
5 ± 10%
4950
4400
3850
110
72
Double-Sided
Socketable
Gold-Tabbed
5-125
TM496TBM40S-60t
TM496TBM40S-70t
TM496TBM40S-80t
60
70
80
5 ± 10%
4950
4400
3850
110
72
Double-Sided
Socketable
Solder-Tabbed
5-125
TM497TBM40-60t
TM497TBM40-70t
TM497TBM40-80t
60
70
80
5 ± 10%
6600
6050
5500
110
72
Double-Sided
Socketable
Gold-Tabbed
5-115
TM497TBM40S-60t
TM497TBM40S-70t
TM497TBM40S-80t
60
70
80
5 ± 10%
6600
6050
5500
110
72
Double-Sided
Socketable
Solder-Tabbed
5-115
204BK x 32
2048K x 36
131 072K
147456K
4096Kx 36
163840K
MAX
ACCESS
TIME
(ns)
DEVICE NUMBER
4096K x 40
t Advance Information for product under development by TI
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
2-9
Selection Guide
DRAM Module (concluded)
DENSITY
ORGANIZATION
(WORDS x BITS)
MAX
ACCESS
TIME
DEVICE NUMBER
POWER
SUPPLY
M
(ns)
262144K
327680K
8192K x 32
8192K x 40
MAX POWER
DISSIPATION
ACTIVE
STANDBY
(mW)
(mW)
PACKAGE
PAGE
TM893CBK32-60t
TM893CBK32-70t
TM893CBK32-80t
60
70
80
5 ± 10%
5368
4928
4488
176
72
Double-Sided
Socketable
5-105
TM892VBM40-60t
TM892VBM40-70t
TM892VBM40-80t
60
70
80
5 ± 10%
5060
4510
3960
220
72
Double-Sided
Socketable
Gold-Tabbed
5-125
TM892VBM40S-60t
TM892VBM40S-70t
TM892VBM40S-80t
60
70
80
5± 10%
6710
6160
5610
220
72
Dou"ble-Sided
Socketable
Solder-Tabbed
5-125
TM893VBM40-60t
TM893VBM40-70t
TM893VBM40-80t
60
70
80
5± 10%
5060
4510
3960
220
72
Double-Sided
Socketable
Gold-Tabbed
5-115
TM893VBM40S-60t
TM893VBM40S-70t
TM893VBM40S-80t
60
70
80
5 ± 10%
5060
4510
3960
220
72
Double-Sided
Socketable
Solder-Tabbed
5-115
t Advance Information for product under development by TI
.
TEXAS ~
INsrRUMENTS
2-10
PINS
POST OFFICE BOX 1~43
•
HOUSTON, TEXAS 77001
Selection Guide
EPROM
DENSITY
ORGANIZATION
(WORDS x BITS)
DEVICE NUMBER
TMS27C128-12
TMS27C128-15
TMS27C128-20
TMS27C128-25
128K
256K
512K
16Kx 8
32Kx8
64K x 8
128K x 8
1024K
64K x 16
2048K
256K x 8
MAX
ACCESS
TIME
(ns)
120
150
200
250
POWER
SUPPLY
MAX POWER
DISSIPATION
PINS
PACKAGEt
NOTES
PAGE
ACTIVE
STANDBY
(mW)
(mW)
165
1.4
28
J
CMOS
6-2
131
220
220
220
220
220
1.6
1.7
1.7
1.7
1.7
1.7
28
J
Military
CMOS
9-81
5", 10%
165
1.4
28
J
CMOS
6-3
5 ± 10%
220
1.7
28
J
Military
CMOS
9-253
M
5",10%
SMJ27C128-12
SMJ27C128-15
SMJ27C128-H
SMJ27C128-20
SMJ27C128-25
SMJ27C128-30
HO
200
250
300
TMS27C256-10
TMS27C256-12
TMS27C256-15
TMS27C256-17
TMS27C256-20
TMS27C256-25
100
120
150
170
200
250
SMJ27C256-15
SMJ27C256-17
SMJ27C256-20
SMJ27C256-25
SMJ27C256-30
170
200
250
TMS27C510-12
TMS27C510-15
TMS27C510-17
TMS27C51 0-20
TMS27C51 0-25
120
150
170
200
250
5±10%
165
1.4
32
J
CMOS
6-15
TMS27C512-10
TMS27C512-12
TMS27C512-15
TMS27C512-20
TMS27C512-25
100
120
150
200
250
5", 10%
165
1.4
28
J
CMOS
6-27
SMJ27C512-20
SMJ27C512-25
SMJ27C512-30
200
250
300
5", 10%
263
1.8
28
J
Military
CMOS
9-263
TMS27C010A-l0
TMS27C010A-12
TMS27C010A-15
TMS27C010A-20
100
120
150
200
5±10%
165
0.55
32
J
CMOS
6-39
TMS27LV010A-20+
TMS27LV010A-25+
TMS27LV010A-30+
200
250
300
3.3",10%
54
.09
32
J
CMOS
Low
Voltage
6-203
5", 10%
165
0.55
40
J
CMOS
6-51
5",10%
165
0.55
32
FM,J
CMOS
6-61
120
150
5",5%
5",10%
5", 10%
5", 10%
5",10%
5",10%
150
300
TMS27C210A-l0
TMS27C210A-12
TMS27C210A-15
TMS27C210A-20
TMS27C210A-25
100
200
250
TMS27C020-12
TMS27C020-15
TMS27C020-20
TMS27C020-25
120
150
200
250
120
150
t FM
Plastic Leaded Chip Carner
J
Ceramic Dual In-Line Package (DIP)
+ Product preview documents contain information on products in the formative or design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
2-11
Selection Guide
EPROM (concluded)
DENSITY
ORGANIZATION
(WORDS x BITS)
512K x 8
4096K
256K x 16
DEVICE NUMBER
MAX
ACCESS
TIME
(ns)
POWER
SUPPLY
M
MAX POWER
DISSIPATION
ACTIVE
(mW)
STANDBY
(mW)
PACKAGEt
NOTES
PAGE
TMS27C040-10
TMS27C040-12
TMS27C040-15
100
120
150
5%10%
275
0.55
32
J
CMOS
6-71
SMJ27C040-10
SMJ27C040-12
SMJ27C040-15
100
120
150
5 % 10%
330
0.55
32
J
Military
CMOS
9-275
TMS27C240-10
TMS27C240-12
TMS27C240-15
100
120
150
5%10%
275
0.55
40
J
CMOS
6-81
TMS27C400-10;
TMS27C400-12;
TMS27C400-15;
100
120
150
5% 10%
275
0.55
40
J
CMOS
6-91
tJ
Ceramic Dual In-Line Package (DIP)
; Advance Information for product under development by TI
TEXAS ~
INSTRUMENTS
2-12
PINS
POST OFFICE BOX 1443
•
HOUSTON. TEXAS 77001
Selection Guide
Flash EEPROM
DENSITY
ORGANIZATION
(WORDS x BITS)
DEVICE NUMBER
MAX
ACCESS
TIME
(ns)
16K
512K
(V)
ACTIVE
STANDBY
(mW)
(mW)
PINS
PACKAGEt
NOTES
PAGE
TMS29F816-06
N/A
5 ± 10%
110
N/A
18
FM
CMOS
5-V Flash
Serial
JTAG Bus
6-101
SMJ29F816-06t
N/A
5± 10%
110
N/A
18
FM
CMOS
5-V Flash
Serial
JTAG Bus
9-285
64K x 8
TMS28F512-10t
TMS28F512-12t
TMS28F512-15t
TMS28F512-17t
100
120
150
170
5 ± 10%
165
.55
32
DD, DU,
FM,N
CMOS
Flash
EEPROM
6-145
128K x 8
TMS28F010-l0*
TMS28F010-12t
TMS28F010-15*
TMS28F010-17t
100
120
150
170
5±10%
165
.55
32
DD, DU,
FM,N
CMOS
Flash
EEPROM
6-145
64K x 16
TMS28F21 0-1 O§
TMS28F210-12§
TMS28F210-15§
TMS28F210-17§
100
120
150
170
5± 10%
275
.55
40,44
FN, J
CMOS
Flash
EEPROM
6-165
512K x 8
TMS28F040-80*
80
5 ± 10%
165
0.55
32,40
DD,DU,N
CMOS
Flash
EEPROM
6-185
2Kx8
1024K
4096K
MAX POWER
DISSIPATION
POWER
SUPPLY
t DD
Plastic Thin Smail-Outline Package
DU Plastic Thin Small-Outline Reverse Form Package
FM Plastic Leaded Chip Carrier
FN Plastic Leaded Chip Carrier
J
Ceramic Dual In-Line Package (DIP)
N
Plastic Dual In-Line Package (DIP)
t Advance Information for product under development by TI
§ Product preview documents contain information on products in the formative or design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443
•
HOUSTON, TEXAS 77001
2-13
Selection Guide
One-Time Programmable (OTP) PROM
DENSITY
128K
256K
512K
ORGANIZATION
(WORDS x BITS)
MAX
ACCESS
TIME
(ns)
POWER
SUPPLY
M
MAX POWER
DISSIPATION
ACTIVE
(mW)
STANDBY
(mW)
PACKAGEt
NOTES
PAGE
TMS27PC128-15
TMS27PC128-20
TMS27PC128-25
150
200
250
5% 10%
165
1.4
28,32
FM,N
CMOS
6-2
32Kx8
TMS27PC256-10
TMS27PC256-15
TMS27PC256-17
TMS27PC256-20
TMS27PC256-25
100
150
170
200
250
5% 10%
165
1.4
28,32
FM,N
CMOS
6-3
TMS27PC510-15
TMS27PC51 0-17
TMS27PC51 0-20
TMS27PC51 0-25
150
170
200
250
5%10%
165
1.4
32
FM,N
CMOS
6-15
TMS27PC512-10
TMS27PC512-12
TMS27PC512-15
TMS27PC512-20
TMS27PC512-25
100
120
150
200
250
5% 10%
165
1.4
28,32
DD, DU,
FM,N
CMOS
6-27
TMS27PC010A-12
TMS27PC010A-15
TMS27PC010A-20
120
150
200
5 %10%
165
0,55
32
DD, DU,
FM,N
CMOS
6-39
TMS27LV010A-20:l:
TMS27LV010A-25:j:
TMS27LV010A-30:j:
200
250
300
3.3 ± 10%
54
0.09
32
FM
CMOS
Low
Voltage
6-203
64K x 16
TMS27PC210A-12
TMS27PC210A-15
TMS27PC210A-20
TMS27PC210A-25
120
150
200
250
5 %10%
165
0.55
44
FN
CMOS
6-51
256Kx 8
TMS27PC020-12
TMS27PC020-15
TMS27PC020-20
TMS27PC020-25
120
150
200
250
5± 10%
165
0.55
32
FM
CMOS
6-61
512K x 8
TMS27PC040-10
TMS27PC040-12
TMS27PC040-15
100
120
150
5± 10%
275
0.55
32
FM
CMOS
6-71
TMS27PC240-10
TMS27PC240-12
TMS27PC240-15
100
120
150
5± 10%
275
0.55
44
FN
CMOS
6-81
TMS27PC400-10:l:
TMS27PC400-12:1:
TMS27PC400-15:1:
100
120
150
5% 10%
275
0.55
44
N
CMOS
6-91
64Kx8
1024K
4096K
256K x 16
t DD
Plastic Thin Small-Outline Package
DU Plastic Thin Small-Outline Reverse Form Package
FM Plastic Leaded Chip Carrier
FN Plastic Leaded Chip Carrier
N
Plastic Dual In-Line Package (DIP)
:I: Advance Information for product under development by TI
TEXAS
~
INSTRUMENTS
2-14
PINS
16Kx 8
128K x 8
2048K
DEVICE NUMBER
POST OFFICE BOX 1443
•
HOUSTON. TEXAS 77001
Selection Guide
Video RAMs/Field Memories
DENSITY
ORGANIZATION
(WORDS. BITS)
DEVICE NUMBER
MAX
ACCESS
TIME
(V)
(ns)
1024K
4096K
256Kx 4
MAX POWER
DISSIPATION
POWER
SUPPLY
ACTIVE
STANDBY
(mW)
(mW)
PINS
PACKAGEt
NOTES
PAGE
SMJ44C250- to
SMJ44C250-12
100
120
5± 10%
635
550
90
83
28
HJ, JD
Military
CMOS
Multiport
Video RAM
9-161
SMJ44C251-10
SMJ44C251-12
100
120
5± 10%
550
495
83
28
HJ, JD
Military
CMOS
Multiport
Video RAM
9-199
TMS4Cl0508-30
TMS4Cl0508-40
TMS4Cl0508-60
30
40
60
5±10%
275
248
193
55
16,
20,26
DJ, N, SD
CMOS
Field
Memory
7-109
TMS4Cl0608-30
TMS4Cl0608-40
TMS4Cl0608-60
3040
60
5± 10%
275
248
193
55
16,
20,26
DJ, N, SD
CMOS
Field
Memory
7-121
TMS4Cl0708-30*
TMS4Cl0708-40*
TMS4Cl0708-60*
30
40
60
5±10%
275
248
193
55
18
N
CMOS
Field
Memory
7-133
TMS55160-70
TMS55160-80
70
80
5± 10%
908
880
28
64
DGH
CMOS
Multiport
Video RAM
7-3
TMS55165-70
TMS55165-80
70
80
5± 10%
908
880
28
64
DGH
CMOS
Multiport
Video RAM
7-57
256K .16
t DGH PlastiC Super Small-Outline Package (SSOP)
DJ
Plastic Small-Outline J-Lead (SOJ)
HJ Ceramic Small-Outline J-Lead (Military) (SOJ)
JD Ceramic Sidebrazed Dual In-Line Package (Military) (DIP)
N
Plastic Dual In-Line (DIP)
SD Plastic Zig-Zag In-Line Package (ZIP)
* Advance Information for product under development by TI
TEXAS ~
INSTRUMENTS
POST OFfiCE BOX 1443
•
HOUSTON, TEXAS 77001
2-15
Selection Guide
Memory Card
DENSITY
ORGANIZATION
(WORDS x BITS)
DEVICE NUMBER
MAX
ACCESS
TIME
POWER
SUPPLY
M
(ns)
256K
512K
ACTIVE
STANDBY
(mW)
(mW)
PINS
NOTES
PAGE
256Kx 8
or
128K x16
CMS68F256-250t
250
5±5%
420
131
68
PCMCIA Standard
Flash EEPROM
Memory Card
8-45
256K x 8
or
128Kx 16
CMS68P256-200
200
5±5%
1050
52.5
68
PCMCIA Standard
OTP PROM Memory
Card
Includes Attribute
Memory
8-35
256Kx 8
or
128Kx 16
CMS68P256N-200
200
5±5%
1050
52.5
68
PCMCIA Standard
OTP PROM Memory
Card
8-35
512Kx8
or
256Kx 16
CMS68F512-250t
250
5±5%
420
131
68
PCMCIA Standard
Flash EEPROM
Memory Card
8-45
512K x 8
or
256Kx 16
CMS68P512-200*
200
5±5%
1050
52.5
68
PCMCIA Standard
OTP PROM Memory
Card
Includes Attribute
Memory
8-35
512Kx8
or
256K x 16
CMS68P512N-200
200
5±5%
1050
52.5
68
PCMCIA Standard
OTP PROM Memory
Card
8-35
CMS213-200
CMS213-250
200
250
5±5%
263
21
60
OTP PROM Memory
Card
8-65
1024K x 8
or
512Kx16
CMS68F1 MB-250t
250
5±5%
420
131
68
PCMCIA Standard
Flash EEPROM
Memory Card
8-45
1024K x 8
or
512Kx16
CMS68Pl MB-200
200
5±5%
1050
52.5
68
PCMCIA Standard
OTP PROM Memory
Card
Includes Attribute
Memory
8-35
1024K x 8
or
512Kx16
CMS68Pl MBN-200
200
5±5%
1050
52.5
68
PCMCIA Standard
OTP PROM Memory
Card
8-35
64K x 16
CMS209-200
CMS209-250
200
250
5±5%
525
42
60
OTP PROM Memory
Card
8-65
128K x 8
CMS214-200
CMS214-250
200
250
5±5%
263
42
60
OTP PROM Memory
Card
8-65
64K x 8
1024K
MAX POWER
DISSIPATION
. .
..
t Product preview documents contain Informalion on products In the formative or design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
TEXAS •
INSTRUMENTS
2-16
POST OFFICE BOX 1443
•
HOUSTON. TEXAS 77001
Selection Guide
Memory Card (concluded)
DENSITY
2048K
ORGANIZATION
(WORDS x BITS)
DEVICE NUMBER
2048K x 8
or
1024K x 16
CMS68F2MB-250*
1024K x 18
MAX
ACCESS
TIME
(ns)
POWER
SUPPLY
M
MAX POWER
DISSIPATION
ACTIVE
(mW)
STANDBY
(mW)
PINS
NOTES
PAGE
250
5±5%
420
131
68
PCMCIA Standard
Flash EEPROM
Memory Card
8-45
CMS407-7
CMS407-8
70
80
5±5%
3098
2783
68
60
DRAM Memory
Card
8-3
1024K x 16
CMS408-7
CMS408-8
70
80
5±5%
2153
1943
47
60
DRAM Memory
Card
8-3
128K x 16
CMS21 0-200
CMS21 0-250
200
250
5±5%
525
84
60
OTP PROM Memory
Card
8-65
256Kx 8
CMS216-200
CMS216-250
200
250
5±5%
263
84
60
OTP PROM Memory
Card
8-65
2048K x 18
CMS405-7
CMS405-8
70
80
5±5%
3161
2846
131
60
DRAM Memory
Card
8-3
2048K x 16
CMS406-7
CMS406-8
70
80
5±5%
2195
1985
89
60
DRAM Memory
Card
8-3
1024K x 36
CMS88D4MB36-7t
CMS88D4MB36-8t
70
80
5±5%
4988
4463
58
88
DRAM Memory
Card
8-27
4096K x 18
CMS409-7
CMS409-8
70
80
5±5%
8768
7823
194
60
DRAM Memory
Card
8-17
4096K x 16
CMS410-7
CMS41 0-8
70
80
5±5%
7823
6983
173
60
DRAM Memory
Card
8-17
2048K x 36
CMS88D8MB36-7t
CMS88D8MB36-8t
70
80
5±5%
5045
4520
110
88
DRAM Memory
Card
8-27
4096K
8192K
t Advance Information for product under development by TI
* Product preview documents contain information on products in the formative or design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
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Selection Guide
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Definition of TermsfTiming Conventions
3-1
3-2
Definition of Terrns/Tirning Conventions
GENERAL CONCEPTS AND TYPES OF MEMORIES
Address - Any given memory location in which data can be stored or from which it can be retrieved.
Automatic Chip-Select/Power Down - see Chip Enable Input.
Bit-Contraction of BinarydigitLe., a 1 or aD. In electrical terms, the value of a bit maybe represented by the presence
or absence of charge, voltage, or current.
Byte - A word of 8 bits (see Word).
C of C - Certification of Conformance.
CDIP - Ceramic Dual In-Line Package.
CERPAC - CERamic flat PACk (hermetic).
CMOS - A complementary MOS technology that uses transistors with electron (N-channel) and hole (P-channel) conduction.
Chip Enable Input - A control input to an integrated circuit that, when active, permits operation of the integrated circuit for input, internal transfer, manipulation, refreshing, and/or output of data and, when inactive, causes the integrated circuit to be in a reduced-power standby mode.
Chip Select Input - Chip select inputs are gating inputs that control the input to and output from the memory. They
may be of two kinds:
1.
Synchronous - Clocked/latched with the memory clock. Affects the inputs and outputs for the duration
of that memory cycle.
2.
Asynchronous - Has direct asynchronous control of inputs and outputs. In the read mode, an asynchronous chip select functions like an output enable.
Column Address Strobe (CAS) - A clock used in dynamic RAMs to control the input of column addresses. It can
be active high (CAS) or active low (CAS).
Data - Any information stored or retrieved from a memory device.
Die - Unpackaged semiconductor.
DIP - Dual In-line Package.
DESC - Defense Electronics Supply Center.
Dynamic (Read/Write) Memory (DRAM) - A read/write memory in which the cells require the repetitive application
of control signals in order to retain the stored data.
NOTES:
1. The words "read/write" may be omitted from the term when no misunderstanding will result.
2.
Such repetitive application of the control signals is normally called a refresh operation.
3.
A dynamic memory may use static addressing or sensing circuits.
4.
This definition applies whether the control signals are generated inside or outside the integrated circuit.
Electrically Erasable Programmable Read-Only Memory (EEPROM) - A nonvolatile memory that can be fieldprogrammed like an OTP PROM or EPROM but that can be electrically erased by a combination of electrical signals at its inputs.
EPIC - Enhanced Performance Implanted CMOS.
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Definition of Terms/Timing Conventions
Erasable and Programmable Read-Only Memory (EPROM) - A field-programmable read-only memory that can
have the data content of each memory cell altered more than once.
Erase - Typically associated with EPROMs and EEPROMs. The procedure whereby programmed data is removed
and the device returns to its unprogrammed state.
ESD - Electrostatic Discharge.
Field Memory (FMEM) - A serial-access memory that performs high-speed, asynchronous read/write operations.
(Used mainly for fields of digital TVNTR that require higher speed operation, lower power consumption, and larger
capacity.)
Field-Programmable Read-Only Memory - See One-lime Programmable Read-Only Memory.
FIFO - First-In, First-Out.
Fit - Originally stood for Failures-In-lime. Currently means a failure rate of one failure in one billion hours.
Fixed Memory-A common term for ROMs, EPROMs, EEPROMs, etc., containing data that is not normally changed.
A more precise term for EPROMs and EEPROMs is nonvolatile since their data may be easily changed.
Flash EEPROM FRAM - First-in first-out pseudo-static RAM or Field RAM.
Fully Static RAM -In a fully static RAM, the periphery as well as the memory array is fully static. The periphery is
thus always active and ready to respond to input changes without the need of clocks. There is no precharge
required for static periphery.
GENERIC DATA - Group A, S, C, & D Quality Conformance Data.
JAN - Joint Army Navy. Specifically, a JM3851 0 qualified device.
JANB - Class S screened JAN device.
JANS - Class S screened JAN device.
JEDEC - Joint Electronic Device Engineering Council.
JTAG - Joint Testability Action Group.
K - When used in the context of specifying a given number of bits of information, 1 K
64K 64 x 1024 65 536 bits.
=
=
= 2 10 = 1024 bits. Thus,
Mask-Programmed Read-Only Memory - A read-only memory in which the data content of each cell is determined
during manufacture by the use of a mask, the data content thereafter being unalterable.
Memory - A medium capable of storing information that can be retrieved.
Memory Card - A pocket-size memory storage system.
Memory Cell - The smallest subdivision of a memory into which a unit of data has been or can be entered in which
it is or can be stored, and from which it can be retrieved.
Metal-Oxide Semiconductor (MOS) - The technology involving photolithographic layering of metal and oxide to produce a semiconductor device.
MIL-M-38S10 - A military controlling specification pertaining mainly to JAN qualified devices (microcircuits).
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Definition of TermsfTiming Conventions
MIL-STD-883 - A military controlling specification containing detailed descriptions of the screening processes pertaining to Class B and Class S devices (microcircuits).
NMOS - A type of MaS technology in which the basic conduction mechanism is governed by electrons. (Short for
N-channel MOS.)
Nonvolatile Memory - A memory in which the data content is maintained whether the power supply is connected
or not.
OTP - One-Time Programmable.
One-Time Programmable (OTP) Read-Only Memory - A read-only memory that, after being manufactured, can
have the data content of each memory cell altered once. Also referred to as OTP.
Output Enable - A control input that, when true, permits data to appear at the memory output, and when false, causes
the output to assume a high-impedance state. (See also chip select.)
PCMCIA - Personal Computer Memory Card International Association
PDIP - Plastic Dual-ln-Iine Package.
PLCC - Plastic Leaded Chip Carrier.
PMOS - A type of MaS technology in which the basic conduction mechanism is governed by holes. (Short for
P-channel MOS.)
Parallel Access - A feature of a memory by which all the bits of a byte or word are entered simultaneously at several
inputs or retrieved simultaneously from several outputs.
Power Down - A mode of a memory during which the device is operating in a low-power or standby mode. Normally
read or write operations of the memory are not possible under this condition.
Program - Typically associated with EPROM and OTP memories, the procedure whereby logical Os (or 1s) are stored.
into various desired locations in a previously erased device.
Program Enable - An input signal that, when true, puts a programmable memory device into the program mode.
Programmable Read-Only Memory (PROM) - See One-Time Programmable (OTP) Read-Only Memory.
Printed Wiring Board (PWB) - A substrate of epoxy glass, clad material, or other material upon which a pattern of
conductive traces is formed to interconnect the components that will be mounted upon it.
Read - A memory operation whereby data is output from a desired address location.
Read-Only Memory (ROM) -A memory in which the contents are not intended to be altered during normal operation.
NOTE: Unless otherwise qualified, the term "read-only memory" implies that the contents are determined by its
structure and are unalterable.
Read/Write Memory - A memory in which each cell may be selected by applying appropriate electrical input signals
and the stored data may be either (a) sensed at appropriate output terminals, or (b) changed in response to other
similar electrical input signals.
Row Address Strobe (RAS) - A clock used in dynamic RAMs to control the input of the row addresses. It can be
active high (RAS) or active low (RAS).
SCD - Source Control Drawings.
Scaled-MOS (SMOS) - MaS technology under which the device is scaled down in size in three dimensions and in
operating voltages allowing improved performance.
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Definition of Terms!fiming Conventions
SDRAM - Synchronous Dynamic Random Access Memory.
Semi-Static (Quasi-Static, Pseudo-Static) RAM - In a semi-static RAM, the periphery is clock-activated (Le.,
dynamic). Thus the periphery is inactive until clocked, and only one memory cycle is permitted per clock. The peripheral circuitry must be allowed to reset after each active memory cycle for a minimum precharge time. No refresh is required.
Serial Access - A feature of a memory by which all the bits are entered sequentially at a single input or retrieved
sequentially from a single output.
SIP - Single In-line Package.
Small Outline Integrated Circuit (SOIC) - A package in which an integrated circuit chip can be mounted to form
a surface-mounted component. It is made of a plastic material that can withstand high temperatures and has leads
formed in a gull-wing shape along its two longer sides for connection to a PWB footprint.
SMD - Standard Military Drawing.
SOLCC - Small Outline Leadless ceramic Chip Carrier.
SOJ - Small Outline J-Iead package.
SOP - Small Outline Package.
SQFP - Small Quad Flat Pack.
Static RAM (SRAM) - A read/write random-access device within which information is stored as latched voltage levels. The memory cell is a static latch that retains data as long as power is applied to the memory array. No refresh
is required. The type of periphery circuitry sub-categorizes static RAMs.
ThinSOJ - (TSOJ) Thin Small-Outline J-Lead package.
ThinSOP - (TSOP) Thin Small-Outline package.
Very-Large-Scale Integration (VLSI) - The description of an IC technology that is much more complex than largescale integration (LSI) and involves a much higher equivalent gate count. At this time an exact definition including
a minimum gate count has not been standardized by JEDEC or the IEEE.
Video RAM (VRAM) - A dual-port dynamic random-access memory with a on-chip serial data register.
Volatile Memory - A memory in which the data content is lost when the power supply is disconnected.
Word - A series of one or more bits that occupy a given address location and then can be stored and retrieved in
parallel.
Write - A memory operation whereby data is written into a desired address location.
Write Enable - A control signal that when true causes the memory to assume the write mode, and when false causes
it to assume the read mode.
ZIP - Zig-zag In-line Package.
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Definition of Terms{Timing Conventions
OPERATING CONDITIONS AND CHARACTERISTICS (INCLUDING LEITER SYMBOLS)
Capacitance
The inherent capacitance on every pin, which can vary with various inputs and outputs.
Example symbology:
Ci
Input capacitance
Co
Output capacitance
Ci(D)
Input capacitance, data input
Current
High-level Input current, IIH
The current into an input when a high-level voltage is applied to that input.
High-level output current, 10H
The current into* an output with input conditions applied that according to the product specification will establish
a high level at the output.
Low-level input current, IlL
The current into an input when a low-level voltage is applied to that input.
Low-level output current, 10L
The current into* an output with input conditions applied that according to the product specification will establish
a low level at the output.
Off-state (high-impedance state) output current (of a three-state output,) loz
The current into* an output having three-state capability with input conditions applied that according to the product
specification will establish the high-impedance state at the output.
Short-circuit output current, lOS
The cLlrrent into* an output when the output is short-circuited to ground (or other specified potential) with input
conditions applied to establish the output logic level farthest from ground potential (or other specified potential).
Supply current, IBB, Icc, 100, Ipp
The current into, respectively, the VBB, Vee, VDO, Vpp supply terminals.
*Current out of a terminal is given as a negative value.
Operating Free-Air Temperature
The temperature
(TN range over which the device will operate and meet the specified electrical characteristics.
Voltage
High-level Input voltage, VIH
An input voltage within the more positive (less negative) of the two ranges of values used to represent the binary
variables.
NOTE:
A minimum is specified that is the least positive value of high-level input voltage for which operation
of the logic element within specification limits is guaranteed.
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Definition of Terms(Timing Conventions
High-level output voltage, VOH
The voltage at an output terminal with input conditions applied that according to the product specification will
establish a high level at the output.
Low-level Input voltage, VIL
An input voltage level within the less positive (more negative) of the two ranges of values used to represent the
binary variables.
A maximum is specified that is the most positive value of low-level input voltage for which operation
of the logic element within specification limits is guaranteed.
NOTE:
Low-level output voltage, VOL
The voltage at an output terminal with input conditions applied that according to the product specification will
establish a low level at the output.
Supply voltages, VBB, Vee, Voo, Vpp
The voltages supplied to the corresponding voltage pins that are required for the device to function. From one
to four of these supplies may be necessary, along with ground Vss.
Time Intervals
New or revised data sheets in this book use letter symbols in accordance with standards recently adopted by
JEDEC, the IEEE, and the IEC. Two basic forms are used. The first form is usually used in this book when intervals
can easily be classified as access, cycle, disable, enable, hold, refresh, setup, transition, or valid times and for
pulse durations. The second form can be used generally but in this book primarily for time intervals not easily
classifiable. The second (unclassified) form will be described first. Since some manufacturers use this form for
all time intervals, symbols in the un-classified form are given with the examples for most of the classified time
interVals.
Unclassified time intervals
Generalized letter symbols can be used to identify almost any time interval without classifying it using traditional
or contrived definitions. Symbols for unclassified time intervals identify two signal events listed in from-to
sequence using the format:
tAB·CD
Subscripts A and C indicate the names of the signals for which changes of state or level or establishment of state
or level constitute signal events assumed to occur first and last, respectively, that is, at the beginning and end
of the time interval. E~ effort is made to keep the A and C subscript length down to one letter, if possible (e.g.,
R for RAS and C for CAS).
Subscripts 8 and D indicate the direction of the transitions a.nd/or the final states or levels of the .signals
represented by A and C, respectively. One or two of the following is used:
H = high or transition to high
L
=low or transition to low
V = a valid steady-state level
X = unknown, changing, or "don't care" level
Z = high-impedance (off) state
The hyphen between the 8 and C subscripts is omitted when no confusion is likely to occur.
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Definition of Terms/Timing Conventions
Classified time intervals (general comments, specific times follow)
Because of the information contained in the definitions, frequently the identification of one or both ofthe two signal
events that begin and end the intervals can be significantly shortened compared to the unclassified forms. For
example, it is not necessary to indicate in the symbol that an access time ends with valid data at the output. However, if both signals are named (e.g., in a hold time). the from-to sequence is maintained.
Access time
The time interval between the application of a specific input pulse and the availability of valid signals at an output.
Example symbology:
Classified
ta(A)
ta(S), ta(CS)
Cycle time
Description
Access time from address
Access time from chip select (low)
Unclassified
tAVQV
tSLQV
The time interval between the start and end of a cycle.
NOTE:
The cycle time is the actual time interval between two signal events and is determined by the system
in which the digital circuit operates. A minimum value is specified that is the shortest interval that must
be allowed for the digital circuit to perform a specified function (e.g., read, write, etc.) correctly.
Example symbology:
Classified
Unclassified
Description
Read cycle time
tc(R), tc(rd)
tAVAV(R)
Write cycle time
tc(W)
tAVAV(W)
NOTE: R is usually used as the abbreviation for "read"; however, in the case of dynamic memories, "rd" is used
to permit R to stand for RAS.
Disable time (of a three-state output)
The time interval between the specified reference points on the input and output voltage waveforms, with the
three-state output changing from either of the defined active levels (high or low) to a high-impedance (off) state.
Example symbology:
Classified
tdis(S)
tdis(W)
Unclassified
Description
Ou~put disable time after chip select (high)
tSHQZ
tWLQZ
Output disable time after write enable (low)
These symbols supersede the older forms tpvz or tpxz.
Enable time (of a three-state output)
The time interval between the specified reference points on the input and output voltage waveforms, with the
three-state output changing from a high-impedance (off) state to either of the defined active levels (high or low).
NOTE:
For memories these intervals are often classified as access times.
Example symbology:
Classified
Unclassified
Description
Output enable time after chip select low
ten(SL)
tSLQV
These symbols supersede the older from tpZV.
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Definition of Terms!Timing Conventions
Hold time
The time interval during which a signal is retained at a specified input terminal after an active transition occurs
at another specified input terminal.
NOTES: 1. The hold time is the actual time interval between two signal events and is determined by the system
in which the di~ital circuit operates. A minimum value is specified that is the shortest interval for which
correct operalion of the digital circuit is guaranteed.
.
2. The hold time may have a negative value in which case the minimum limit defines the longest interval
(between the release of the signal and the active transition) for which correct operation of the digital
circuit is guaranteed.
Example symbology:
Classified
th(D)
Unclassified
Description
Data hold time (after write high)
tWHDX
~~H~
~HWH
~~H~
~HWH
th(CLCA)
tCL-CAX
th(RLCA)
tRL-CAX
th(RA)
tRL-RAX
These last three symbols supersede the older forms:
NEW FORM
Read (write enable high) hold time after RAS high
Read (write enable high) hold time after CAS high
Column address hold time after CAS low
Column address hold time after RAS low
Row address hold time (after RAS low)
OLD FORM
th(CLCA)
th(AC)
th(RLCA)
th(ARL)
th(RA)
th(AR)
NOTE: The from-to sequence in the order of subscripts in the unclassified form is maintained in the classified
form. In the case of hold times, this causes the order to seem reversed from what would be suggested
by the terms.
Pulse duration (width)
The time interval between the specified reference pOints on the leading and trailing edges of the pulse waveform.
Example symbology:
Classified
tw(W)
tw(RL)
Refresh time interval
Unclassified
Description
Write pulse duration
tWLWH
Pulse duration, RAS low
tRLRH
The time interval between the beginnings of successive signals that are intended to restore the level in a dynamic
memory celf to its original level.
NOTE:
The refresh time interval is the actual time interval between two refresh operations and is determined
by the system in which the digital circuit operates. A maximum value is specified that is the longest
interval for which correct operation of the digital circuit is guaranteed.
Example symbology:
Classified
Unclassified
Description
Refresh time interval
trf
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Definition of Terms/Timing Conventions
Setup time
The time interval between the application of a signal at a specified input terminal and a subsequent active
transition at another specified input terminal.
NOTES: 1. The setup time is the actual time interval between two signal events and is determined by the system
in which the digital circuit operates. A minimum value is specified that is the shortest interval for which
correct operation of the digital circuit is guaranteed.
2. The setup time may have a negative value in which case the minimum limit defines the longest interval (between the active transition and the application of the other signal) for which correct operation
of the digital circuit is guaranteed.
Example symbology:
Classified
tsu(D)
Description
Data setup time (before write high)
Column address setup time (before CAS low)
Row address setup time (before RAS low)
Unclassified
tDVWH
tsu(CA)
tCAV:CL
tsu(RA)
tRAV-RL
Transition times (also called rise and fall times)
The time interval between two reference points (10% and 90% unless otherwise specified) on the same waveform
that is changing from the defined low level to the defined high level (rise time) or from the defined high level to
the defined low level (fall t i m e ) . '
Example symbology:
Classified
Unclassified
Description
Transition time (general)
Low-to-high transition time of CAS
CAS rise time
CAS fall time
tt
tt(CH)
tCHCH
tr(C)
tCHCH
tCLCL
tf(C)
Valid time'
(a)
(b)
General
The time interval during which a signal is (or should be) valid.
Output data-valid time
The time interval in which output data continues to be valid following a change of input conditions that could
cause the output data to change at the end of the interval.
Example symbology:
Classified
Unclassified
Description
Output data valid time after change of address
tv (A)
tAXQX
This supersedes the older form tpVX'
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Definition of Terms!Timing Conventions
TIMING DIAGRAMS CONVENTIONS
Meaning
Timing Diagram Symbol
'\\\\
II/II
Input Forcing Functions
Output Response Functions
Must be steady high or low
Will be steady high or low
High-to-Iow changes permitted
Will be changing from high to low sometime·
during designated intervals
Low-to-high changes permitted
Will be changing from low to high sometime
during designated intervals
Don't care
State unknown or changing
(Does not apply)
Centerline represents high-impedance
(off) state.
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Dynamic RAMs
4-1
Contents
CHAPTER 4.
DYNAMIC RAMS
TMS44100
4 194 304-bit
(4096K x 1) Enhanced Page Mode .... , ........................... 4-5
TMS44100P
4 194 304-bit
(4096K x 1) Low Power .......................................... 4-5
TMS44400
4 194 304-bit
(1 024K x 4) Enhanced Page mode ............................ ; .. 4-27
TMS44400P
4 194 304-bit
(1 024K x 4) Low Power ......................................... 4-27
TMS46100
4 194 304-bit
(4096K x 1) Low Voltage ............................ , ........... 4-49
TMS46100P
4 194 304-bit
(4096K x 1) Extended Refresh .................................. 4-49
TMS46400
4 194 304-bit
((1 024K x 4) Low Voltage ....................................... 4-71
TMS46400P
4 194 304-bit
(1 024K x 4) Extended Refresh .................................. 4-71
TMS44800
4 194 304-bit
(512K x 8) Enhanced Page Mode ..... , . , ...... , ..... , ........... 4-93
TMS44800P
4 194 304-bit
(512K x 8) Low Power .................. , ....................... 4-93
TMS44165
4 194 304-bit
(256K x 16) Enhanced Page Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-115
TMS44165P
4 194 304-bit
(256K x 16) Low Power. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-115
TMS45160
4 194 304-bit
(256K x 16) Enhanced Page Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-137
TMS45160P
4 194 304-bit
(256K x 16) Low Power. . . . .. .. . . . . . . . . . . . . . . .. . . .. . . . . . . . . . . .. 4-1 ~7
TMS45165
4 194 304-bit
(256K x 16) Enhanced Page Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-159
TMS45165P
4 194 304-bit
(256K x 16) Low Power ..................... , ...... , ........... 4-159
TMS416100
16777 216-bit
(16 385K xi) Enhanced Page Mode ...................... 4-181, 4-249
TMS416400
16 777 216-bit
(4096K x 4) Enhanced Page Mode ........................ 4-203, 4-249
TMS417400
16 777 216-bit
(4096K x 4) Enhanced Page Mode ........................ 4-227, 4-249
16-Meg Shrink
16 777 216-bit
(16 385K x 1 and 4096K x 4) Product Preview .................... 4-249
TMS416160
16777 216-bit
(1 024K x 16) Enhanced Page Mode ............................ 4-253
TMS416160P
16777 216-bit
(1 024K x 16) Low Power ...................................... 4-253
TMS426160
16 777 216-bit
(1 024K x 16) Low Voltage ...................................... 4-275
TMS426160P
16 777 216-bit
(1 024K x 16) Low Voltage, Low Power .......................... 4-275
TMS418160
16 777 216-bit
(1 024K x 16) Enhanced Page Mode ........................ ,... 4-297
TMS418160P
16 777 216-bit
(1 024K x 16) Low Power ...................................... 4-297
TMS428160
16 777 216-bit
(1 024K x 16) Low Voltage ..................................... 4-319
TMS428160P
16777 216-bit
(1 024K x 16) Low Voltage, Low Power .......................... 4-319
TMS416800
16 777 216-bit
(2048K x 8) Enhanced Page Mode ........... , ................ " 4-341
TMS416800P
16 777 216-bit
(2048K x 8) Low Power ....... , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-341
4-2
TMS417800
16 777 216-bit
(2048K x 8) Enhanced Page Mode. . . . . . . . . . . . . . . .. . . . .. . . .. .. .. 4-363
TMS417800P
16 777 216-bit
(2048K x 8) Low Power ....................................... , 4-363
TMS426100
16 777 216-bit
(16K x 1) Low Voltage ........................................ , 4-385
TMS426100P
16 777 216-bit
(16K x 1) Low Voltage, Low Power ............................. , 4-385
TMS426400
16 777 216-bit
(4096K x 4) Low Voltage ....................................... 4-409
TMS426400P
16 777 216-bit
(4096K x 4) Low Voltage, Low Power ........................... 4-409
TMS427400
16 777 216-bit
(4096K x 4) Low Voltage ....................................... 4-433
TMS427400P
16 777 216-bit
(4096K x 4) Low Voltage, Low Power ........................... 4-433
TMS426800
16 777 216-bit
(2048K x 8) Low Voltage. .. . . .. . . . .. . . . .. . . . . . . . . . . . . . . . . . . . . .. 4-457
TMS426800P
16777 216-bit
(2048K x 8) Low Voltage, Low Power ........................... 4-457
TMS427800
16777 216-bit
(2048K x 8) Low Voltage ....................................... 4-479
TMS427800P
16 777 216-bit
(2048K x 8) Low Voltage, Low Power ........................... 4-479
SDRAM
16 778 240-bit
(1 024K x 2) Synchronous DRAM ............................... 4-501
4-3
4-4
TMS441 00, TMS44100P
4194304-81T
DYNAMIC RANDOM-ACCESS MEMORY
SMHS41 OF-5EPTEMBER 19S9-REVISED DECEMBER 1992
•
•
•
Organization ... 4194304 x 1
Single 5-V Power Supply (±10% Tolerance)
Performance Ranges:
ACCESS ACCESS ACCESS
READ
TIME
TIME
TIME OR WRITE
•
•
•
•
•
•
•
•
DJ PACKAGEt
(TOP VIEW)
SDPACKAGEt
(TOP VIEW)
D
VSS
Q
CAS
RAS
CAS
VSS
w
(tRAC)
(MAX)
TMS44100/P-60 60ns
(tCAC)
(MAX)
15ns
(IAAl
(MAX)
30ns
CYCLE
(MIN)
110ns
NC
NC
A10
A9
TMS44100/P-70 70 ns
TMS44100/P-80 80 ns
18 ns
20 ns
35 ns
40 ns
130 ns
150 ns
AO
A1
AS
A7
A2
A6
A3
A5
CAS-Before-RAS Refresh
Long Refresh Period .•.
- 1024-Cycle Refresh in 16 ms (Max)
- 128 ms for Low Power, Self-Refresh
Version (TMS44100P)
Vcc
Vii
A10
NC
A1
A3
A4
A6
L...-_"';;';"=:I
A4
DGA PACKAGEt
(TOP VIEW)
3-State Unlatched Output
Low Power Dissipation
Texas Instruments EPIC ™ CMOS Process
All Inputs/Outputs and Clocks are TTL
Compatible
High-Reliability Plastic 300-Mil 20/26-Lead
Surface Mount (SOJ) Package, 20-Pin
Zig-Zag In-line (Zip) Package, 20/26-Lead
Thin Small Outline (TSOP) Package, and
Reverse Thin Small Outline Package
Operating Free-Air Temperature Range
O°C to 70°C
D
Vii
RAS
A8
DGB PACKAGEt
(TOP VIEW)
VSS
Q
VSS
Q
D
Vii
RAS
CAS
CAS
NC
NC
NC
NC
A10
A9
A9
A10
AO
A1
A8
A7
A8
A7
AO
A1
A2
A6
A6
A2
A3
A5
A5
A3
A4
A4 --.. _ _ _..r- VCC
VCC
-..._ _---Ir-
t The packages shown are for pinout reference only.
description
PIN NOMENCLATURE
The TMS44100
series are high-speed
4 194 304-bit dynamic random-access memories, organized as 4 194 304 words of one bit
each. They employ state-of-the-art EPIC™
(Enhanced Performance Implanted CMOS) technology for high performance, reliability, and low
power at a low cost.
AD-A 10
CAS
D
NC
Q
RAS
W
VCC
VSS
The TMS44100P series are high-speep, low
power, .self-refresh 4 194 304-bit dynamic random-access
memories
organized
as
4 194 304-words of one bit each.
Address Inputs
Column-Address Strobe
Data In
No Connection
Data Out
Row-Address Strobe
Write Enable
5-V Supply
Ground
These devices feature maximum RAS access times of 60 ns, 70 ns, and 80 ns. Maximum power consumption
is as low as 385 mW operating and 6 mW standby.
All inputs and outputs, including clocks, are compatible with Series 74 TTL. All addresses and data-in lines are
latched on-chip to simplify system design. Data out is unlatched to allow greater system flexibility.
EPIC is a trademark of Texas Instruments Incorporated.
;~o~~:~~:to~:1: .;~~~~:~."pe~~!n: ~f Ia~::~~~o~m~~~
Ilandard warranty. Production proceulng doe. not "ecl... rlty Include
telling of all parameters.
TEXAS
~
Copyright © 1992, Texas Instruments Incorporated
INsrRUMENTS
POST OFFICE BOX 1443· HOUSTON, TEXAS 77001
4-5
TMS441 00, TMS44100P
4194304·81T
DYNAMIC RANDOM·ACCESS MEMORY
SMHS410F-5EPTEMBER 1989-REVISED DECEMBER 1992
(continued)
The TMS441 00 and TMS441 OOP are offered in a 300-mil 20/26-lead plastic surface mount SOJ package (OJ
suffix), a 20-pin zig-zag in-line package (SO suffix), a 20/26-lead plastic small outline package (DGA suffix), and
a 20/26-lead plastic small outline package reverse form (DGS suffix). All packages are characterized for
operation from O°C to 70°C.
operation
enhanced page mode
Enhanced page-mode operation allows faster memory access by keeping the same row address while selecting
random column addresses. The time for row-address setup and hold and address multiplex is thus eliminated.
The maximum number of columns that may be accessed is determined by the maximum RAS low time and the
CAS page cycle time used.
Unlike conventional page-mode DRAMs, the column-address buffers in this device are activated on the falling
edge of RAS. The buffers act as transparent or flow-through latches while CAS is high. The falling edge of CAS
latches the column addresses. This feature allows the TMS441 00 to operate at a higher data bandwidth than
conventional page-mode parts, since data retrieval begins as soon as the column address is valid rather than
when CAS transitions low. This performance improvement is referred to as enhanced page mode. Valid column
address may be presented immediately after row address hold time has been satisfied, usually well in advance
of the falling edge of CAS. In this case, data is obtained aftertCAC max (access time from CAS low), iftAA max
(access time from column address) has been satisfied. In the event that column addresses for the next cycle
are valid at the time CAS goes high, access time for the next cycle is determined by the later occurrence of tCAC
or tCPA (access time from rising edge of CAS).
address (AO through A 10)
Twenty two address bits are required to decode 1 of 4 194 304 storage cell locations. Eleven row-address bits
are set up on inputs AO through A 10 and latched onto the chip by the row-address strobe (RAS). The eleven
column-address bits are set up on pins AO through A 10 and latched onto the chip by the column-address strobe
(CAS). All addresses must be stable on or before the falling edges of RAS and CAS. RAS is similar to a chip
enable in that it activates the sense amplifiers as well as the row decoder. CAS is used as a chip select activating
the output buffer, as well as latching the address bits into the column-address buffer.
write enable (W)
The read or write mode is selected through the write-enable 0N) input. A logic high on the W input selects the
read mode and a logic low selects the write mode. The write-enable terminal can be driven from standard TTL
circuits without a pull-up resistor. The data input is disabled when the read mode is selected. When W goes low
prior to CAS (early write), data out will remain in the high-impedance state for the entire cycle, permitting
common I/O operation.
data in (D)
Data is written during a write or read-write cycle. Depending on the mode of operation, the falling edge of CAS
or W strobes data into the on-Chip data latch. In an early write cycle, W is brought low prior to CAS and the data
is strobed in by CAS with setup and hold times referenced to this signal. In a delayed-write or read-write cycle,
CAS will already be low, thus the data will be strobed in by W with setup and hold times referenced to this signal.
data out (0)
The three-state output buffer provides direct TTL compatibility (no pull up resistor required) with a fanout of two
Series 74 TTL loads. Data out is the same polarity as data in. The output is in the high-impedance (floating) state
until CAS is brought low. In a read cycle the output becomes valid after the access time interval tCAC that begins
TEXAS ~
INSTRUMENTS
4-6
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
TMS441 00, TMS44100P
4 194 304-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SMHS41 OF-8EPTEMBER 1989-REVISED DECEMBER 1992
with the negative transition of CAS as long as tRA~d tAA are satisfied. The output becomes valid after the
access time has elapsed and remains valid while CAS is low; CAS going high returns it to a high-impedance
state. In a delayed-write or read-write cycle, the output will follow the sequence for the read cycle.
refresh
A refresh operation must be performed at least once every sixteen milliseconds to retain data. This can be
achieved by strobing each of the 1024 rows (AO-A9). A normal read or write cycle will refresh all bits in each
row that is selected. A RAS-only operation can be used by holding CAS at the high (inactive) level, thus
conserving power as the output buffer remains in the high-impedance state. Externally generated addresses
must be used for a RAS-only refresh. Hidden refresh may be performed while maintaining valid data at the output
pin. This is accomplished by holding CAS at VIL after a read operation and cycling RAS after a specified
precharge period, similar to a RAS-only refresh cycle. The external address is ignored during the hidden refresh
cycles.
CAS-before-RAS refresh
CAS-before-RAS refresh is utilized by bringing CAS low earlier than RAS [see parameter ~l and holding it
low after RAS falls [see parameter tCHR1. For successive CAS-before-RAS refresh cycles, CAS can remain low
while cycling RAS. The external address is ignored and the refresh address is generated internally.
A low-power battery-backup refresh mode that requires less than 500 !lA refresh current is available on the
TMS441 OOP. Data integrity is maintained using CAS-before-RAS refresh with a period of 125 ms while holding
RAS low for less than 1 ~s. To minimize current consumption, all input levels need to be at CMOS levels
(VIL:S; 0.2 V, VIH ;" Vee - 0.2 V).
power-up
To achieve proper device operation, an initial pause of 200 ~s followed by a minimum of eight initialization cycles
is required after full Vee level is achieved. These eight initialization cycles need to include at least one refresh
(RAS-only or CAS-before-RAS) cycle.
test mode
An industry standard Design For Test (DFT) mode is incorporated in the TMS441 00. A CAS-before-RAS cycle
with W low (WCSR) cycle is used to enter test mode. In the test mode, data is written into and read from eight
sections of the array in parallel. Data is compared upon reading and if all bits are equal, the data out pin will go
high. If anyone bit is different, the data out pin will go low. Any combination of read, write, read-write, or
page-mode can be used in the test mode. The test mode function reduces test times by enabling the 4 meg
DRAM to be tested as if it were a 512K DRAM, where row address 10, column address 10, and also column
address 0 are not used. A RAS-only or CSR refresh cycle is used to exit the DFT mode.
.
self refresh (TMS44100P)
The self-refresh mode is entered by dropping CAS low prior to RAS going low. Then CAS and RAS are both
held low for a minimum of 100 ~s. The chip is then refreshed by an on-board oscillator. No external address is
required since the CSR counter is used to keep track of the address. To exit the self-refresh mode, both RAS
and CAS are brought high to satisfy teHS' Upon exiting the self-refresh mode, a burst refresh (refresh a full set
of row addresses) must be executed before continuing with normal operation. This will ensure the DRAM is fully
refreshed.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443· HOUSTON. TEXAS 77001
4-7
TMS441 00, TMS44100P
4194304·BIT
DYNAMIC RANDOM·ACCESS MEMORY
SMHS41 OF-SEPTEMBER 1989-'REVISED DECEMBER 1992
logic symbol t
RAM4096Kx1
AO
A1
A2
A3
A4
AS
A6
A7
A8
A9
A10
9
10
30011{21 DO
11
12
14
15
0
>A 4194 303
16
17
18
22
5
31021/21010
I'--
3
~
"-
24
w
o
2
1
!-----;::
~
C30 [ROW]
G33 [REFRESH ROW]
34 [PWR OWN]
C31 [COL]
G34
&
P. 33C32
34 EN
33310
A,320
25
AV
Q
tThis symboUs in accordance with ANSI/IEEE Std 91·1984 and lEe Publication 617·12.
The pin numbers shown are for the 20/26 pin SOJ package.
,,,
functional block diagram
I
,.
AO
A1
A10
Timing and Control
16
8
I
•
•
•
Column
Address
Buffers
3
•
-
•
'---
Sense Amplifiers
-I-
12BKArray
12BKArray
L
•
Column Decode
16<
Row
Address
Buffers
•
•
12BKArray
R
0
12BKArray
•
••
w
•
r-.+
0
e
1Q
c
I
0
r-1f--
11-128KArray
1Q
I
TEXAS
~
INSTRUMENTS
4·8
16
I/O
Buffers
1 of 16
Selection
3 __
d
e
12BKArray
,x
POST OFFICE BOX 1443· HOUSTON. TEXAS 77001
~
In
Reg.
4
~
Out
Reg.
o
Q
TMS441 00, TMS44100P
4 194 304·BIT
DYNAMIC RANDOM·ACCESS MEMORY
SMHS410F-SEPTEMBER
198~REVISED
DECEMBER 1992
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Voltage range on any pin (see Note 1) ................................................. - 1 V to 7 V
Voltage range on Vee ............................................................... -1 V to 7 V
Short circuit output current ................................................................ 50 mA
Power dissipation .......................................................................... 1 W
Operating free-air temperature range .................................................. ooe to 70°C
Storage temperature range ....................................................... - 55°C to 150°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. This is a stress rating only. and
functional operation of the device at these or any other conditions beyond those indicated in the "recommended operating conditions" section of
this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values in this data sheet are with respect to VSS.
recommended operating conditions
MIN
NOM
MAX
VCC
Supply voltage
4.5
5
5.5
V
V,H
High-level input voltage
2.4
6.5
V
V,L
LOW-level input voltage (see Note 2)
-1
0.8
V
TA
Operating free-air temperature
0
70
'c
UNIT
NOTE 2: The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used in this data sheet for logic
voltage levels only.
TEXAS ~
INSfRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
4-9
TMS441 00, TMS44100P
4194304·81T
DYNAMIC RANDOM·ACCESS MEMORY
SMHS41 OF-SEPTEMBER 1989-REVISED DECEMBER 1992
electrical characteristics over full ranges of recommended operating conditions (unless otherwise
noted)
PARAMETER
TMS441 00-60
TMS44100P-60
TEST
CONDITIONS
VOH
High-level output voltage
10H =-5 mA
VOL
Low-level output voltage
IOL=4.2mA
II
Input current (leakage)
10
Output current (leakage)
ICClt
Read or write cycle
current (see Note 3)
MIN
MAX
2.4
Standby current
MIN
MAX
2.4
TMS441 00-80
TMS44100P-80
MIN
UNIT
MAX
2.4
V
0.4
0.4
0.4
V
VI = 0 to 6.5 V, VCC = 5.5 V,
All other pins = 0 V to VCC
±10
±10
±10
!lA
Vo = OtoVCC,
VCC = 5.5 V, CAS high
",10
",10
",10
!lA
105
90
80
mA
2
2
2
mA
'44100
1
1
1
mA
'44100P
500
500
500
!,A
Minimum cycle, VCC = 5.5 V
After 1 memory cycle,
RAS and CAS high,
VIH = 2.4V (TTL)
ICC2
TMS441 00-70
TMS44100P-70
After 1 memory
cycle, RAS and
CAS high,
VIH = VCC-0.2 V
(CMOS)
ICC3
Average refresh current
(RAS-only or CBR)
(see Note 3)
Minimum cycle, VCC = 5.5 V,
RAS cycling,
CAS high (RAS-only),
RAS low after CAS low (CBR)
105
90
80
mA
ICC4 t
Average page current
(see Note 4)
tpc = minimum, VCC = 5.5 V,
RAS low, CAS cycling
90
80
70
mA
ICC6 t *
Self-refresh current
CAS" 0.2 V, RAS < 0.2 V,
measured after tRASS min
500
500
500
!lA
ICC7t
Stand by current
RAS = VIH, CAS = VIL,
Data out = Enabled
5
5
5
mA
ICClO*
Battery backup operating
current (equivalent
refresh time is 256 ms)
CBR only
tRC = 125 ms, tRAS " 1 ms,
VCC-0.2V "VIH" 6.5 V,
o V" VIL" 0.2 V,
Wand OE = VIH,
Address and Data stable
500
500
500
!,A
t Measured with outputs open.
* For TMS441 OOP only.
NOTES: 3. Measured with a maximum of one address change while RAS = VIL.
4. Measured with a maximum of one address change while CAS = VIH.
TEXAS
~
INSTRUMENTS
4-10
POST OFFICE BOX 1443· HOUSTON. TEXAS 77001
TMS441 00, TMS44100P
4 194 304·BIT
DYNAMIC RANDOM·ACCESS MEMORY
SMHS410F-SEPTEMBER 1989-REVISED DECEMBER 1992
capacitance over recommended ranges of supply voltage and operating free-air temperature,
f = 1 MHz (see Note 5)
PARAMETER
MIN
TYP
MAX
UNIT
Ci(A)
Input capacitance, address inputs
5
pF
Ci(D)
Input capacitance, data input
5
pF
Ci(RC)
Input capacitance, strobe inputs
7
pF
Ci(W)
Input capacitance, write-enable input
7
pF
Co
Output capacitance
7
pF
NOTE 5: VCC equal to 5 V
±
0.5 V and the bias on pinS under test IS 0 V.
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature
TMS441 00-60
TMS44100P-60
PARAMETER
MIN
MAX
TMS441 00-70
TMS44100P-70
MIN
MAX
TMS441 00-80
TMS44100P-80
MIN
UNIT
MAX
tAA
Access time from column-address
30
35
40
ns
tCAC
Access time from CAS low
15
18
20
ns
tCPA
Access time from column precharge
35
40
45
ns
tRAC
Access time from RAS low
60
70
80
ns
tCLZ
CAS to output in low Z
0
tOFF
Output disable time after CAS high (see Note 6)
0
0
15
0
ns
0
18
0
20
ns
NOTE 6: tOFF is specified when the output is no longer driven.
TEXAS
~
INsrRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
4-11
TMS441 00, TMS44100P
4 194 304-81T
DYNAMIC RANDOM-ACCESS MEMORY
SMHS410F-SEPTEMBER 1989-REVISED DECEMBER 1992
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
TMS441 00-60
TMS44100P-60
TMS441 00-70
TMS44100P-70
TMS441 00-80
TMS44100P-80
MIN
MIN
MIN
MAX
MAX
UNIT
MAX
tRC
Random read or write cycle (see Note 7)
110
130
150
ns
tRWC
Read-write cycle time
130
153
175
ns
tpc
Page-mode read or write cycle time. (see Note 8)
40
45
50
ns
tpRWC
Page-mode read-write cycle time
60
68
75
tRASP
Page-mode pulse duration, RAS low (see Note 9)
60
100000
70
100000
80
100000
ns
tRAS
Non-page-mode pulse duration, RAS low (see Note 9)
60
10 000
70
10 000
80
10000
ns
tCAS
Pulse duration, CAS low (see Note 10)
15
10000
18
10000
20
10 000
ns
tcp
Pulse duration, CAS high
10
10
10
ns
tRP
Pulse duration, RAS high (precharge)
40
50
60
ns
twp
Write pulse duration
15
15
15
ns
tASC
Column-address setup time before CAS low
0
0
0
ns
tASR
Row-address setup time before RAS low
0
0
0
ns
tDS
Data setup time (see Note 11)
0
0
0
ns
tRCS
Read setup time before CAS low
0
0
0
ns
tCWL
W-Iow setup time before CAS high
15
18
20
ns
tRWL
W-Iow setup time before RAS high
15
18
20
ns
twcs
W-Iow setup time before CAS low (Early write operation only)
0
0
0
ns
twSR
W-high setup time (CAS-before-RAS refresh only)
10
10
10
ns
twTs
W-Iow setup time (test mode only)
10
10
10
ns
tCAH
Column-address hold time after CAS low
10
15
15
ns
tDHR
Data hold time after RAS low (see Note 13)
50
55
60
ns
tDH
Data hold time (see Note 11)
10
15
15
ns
tAR
Column-address hold time after RAS low (see Note 13)
50
55
60
ns
tRAH
Row-address hold time after RAS low
10
10
10
ns
tRCH
Read hold time after CAS high (see Note 12)
0
0
0
ns
tRRH
Read hold time after RAS high (see Note 12)
0
0
0
ns
twCH
Write hold time after CAS low (Early write operation only)
15
15
15
ns
twCR
Write hold time after RAS low (see Note 13)
50
55
60
ns
twHR
W-high hold time (CAS-before-RAS refresh only)
10
10
10
ns
twTH
W-Iow hold time (test mode only)
10
10
10
ns
tAWD
Delay time, column address to W low
(Read-write operation only)
30
35
40
ns
tCHR
Delay time, RAS low to CAS high
(CAS-before-RAS refresh only)
15
15
20
ns
tCRP
Delay time, CAS high to RAS low
0
0
0
ns
tCSH
Delay time, RAS low to CAS high
60
70
80
ns
Continued next page.
NOTES: 7. All cycle times assume IT = 5 ns.
8. To assure tpc min, tAse should be greater than or equal to 5 ns.
9. In a read-write cycle, tRWD and tRWL must be observed.
10. In a read-write cycle, tCWD and tCWL must be observed.
11. Referenced to the later of CAS or IN in write operations.
12. Either tRRH or tRCH must be satisfied for a read cycle.
13. The minimum value is measured when tRCD is set to tRCD min as a reference.
TEXAS
~
INSTRUMENTS
4-12
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
ns
TMS441 00, TMS44100P
4 194 304·BIT
DYNAMIC RANDOM·ACCESS MEMORY
SMHS41 OF-SEPTEMBER
198~REVISED
DECEMBER 1992
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (concluded)
TMS441 00-60
TMS44100P-60
TMS441 00-70
TMS44100P-70
TMS441 00-80
TMS44100P-80
MIN
MIN
MIN
MAX
MAX
UNIT
MAX
tCSR
Delay time, CAS low to RAS low
(CAS-before-RAS refresh only)
10
10
10
ns
tCWD
Delay time, CAS low to W low
(Read-write operation only)
15
18
20
ns
tRAD
Delay time, RAS low to column-address (see Note 14)
15
tRAL
Delay time, column-address to RAS high
30
35
40
ns
tCAL
Delay time, column address to CAS high
30
35
40
ns
tRCD
Delay time, RAS low to CAS low
(see Note 14)
20
tRPC
Delay time, RAS high to CAS low (CBR only)
0
0
0
ns
tRSH
Delay time, CAS low to RAS high
15
18
20
ns
tRWD
Delay time, RAS low to W low
(Read-write operation only)
60
70
80
ns
ns
30
45
15
35
20
52
15
20
40
60
ns
ns
tcps
CAS precharge before self-refresh
0
0
0
tRPS
RAS precharge after self-refresh
110
130
150
ns
tRASS
Self-refresh entry from RAS low
100
100
100
ms
tCHS
CAS .low hold time after RAS high (self-refresh)
-50
-50
-50
ns
ITAA
Access time from address (test mode)
35
40
45
ns
ITCPA
Access time from column precharge (test mode)
40
45
50
ns
ITRAC
Access time from RAS (test mode)
65
75
85
tREF
Refresh time interval
IT
Transition time
I
16
16
'44100
I '44100P
128
128
2
50
2
50
2
ns
16
ms
128
ms
50
ns
NOTE 14: The maximum value is specified only to assure access time.
PARAMETER MEASUREMENT INFORMATION
Vcc =5V
1.31 V
~
Output Under Test
RL = 218 Q
~
CL= 100pF
Output Under Test - -...- -....
T
CL = 100 pF
(a) Load Circuit
(b) Alternate Load Circuit
Figure 1. Load Circuits for Timing Parameters
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
4-13
TMS441 00, TMS44100P
4 194 304·81T
DYNAMIC RANDOM·ACCESS MEMORY
SMHS41 OF-SEPTEMBER 1989-REVISED DECEMBER 1992
PARAMETER MEASUREMENT INFORMATION
NOTE A: Output may go from three-state to an invalid data state prior to the specified access time.
Figure 2. Read Cycle Timing
TEXAS ~
INsrRUMENTS
4-14
POST OFFICE BOX 1443· HOUSTON. TEXAS 77001
TMS441 00, TMS44100P
4 194 304·BIT
DYNAMIC RANDOM·ACCESS MEMORY
SMHS41 OF-8EPTEMBER 1989-REVISED DECEMBER 1992
PARAMETER MEASUREMENT INFORMATION
Q---------------HI·Z--------------VOL
Figure 3. Early Write Cycle Timing
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
4·15
TMS441 00, TMS44100P
4 194 304·81T
DYNAMIC RANDOM·ACCESS MEMORY
SMHS41 OF--SEPTEMBER 1989-REVISED DECEMBER 1992
PARAMETER MEASUREMENT INFORMATION
Figure 4. Write Cycle Timing
TEXAS ~
INSTRUMENTS
4-16
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
TMS441 00, TMS44100P
4194304-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SMHS41 OF-SEPTEMBER 1989-REVISED DECEMBER 1992
PARAMETER MEASUREMENT INFORMATION
NOTE A: Output may go from three-state to an invalid data state prior to the specified access time.
Figure 5. Read-Write Cycle Timing
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443' HOUSTON, TEXAS 77001
4-17
TMS441 00, TMS44100P
4 194 304-81T
DYNAMIC RANDOM-ACCESS MEMORY
SMHS410F--SEPTEMBER 1989-REVISED DECEMBER 1992
PARAMETER MEASUREMENT INFORMATION
Column
AO-A10
~---tAr'
t
-~I
W
tRCS
1
I
~
1
'i::£i£I/ ~ tRAD ~
1
~w¥~~~~~ VIL
I
1
wn
I..
"'..11-+-1-
I..
(see Note B)
.1
tAA
.1
tRAC
tCLl
1
1
1
1
ffiV'H
'\(i VIL
I~
..- - - - tCPA ---+I-.~I
1
I I * - - tcAC --+!
1
tRRH-+!
I+--i-- tRCH --.I
i i
W
1
1
tAA ---I-~
(see Note B)
1l0iii
..- - - -
1+---1-1 tOFF ~
.: Iv,/v,r..
Q---------:---=-=-~-:--{XXXX)(:X
(see Note A)
-I
I
1
VOH
Vslld
Out
VOL
NOTES: A. Output may go from three-state to an invalid data state prior to the specified access time.
B. Access time is tCPA or tAA dependent.
Figure 6. Enhanced Page-Mode Read Cycle Timing
TEXAS ~
INSTRUMENTS
4-18
POST OFFICE BOX 1443' HOUSTON. TEXAS 77001
TMS441 00, TMS44100P
4 194 304·81T
DYNAMIC RANDOM·ACCESS MEMORY
SMHS410F-SEPTEMBER 19S9-REVISED DECEMBER 1992
PARAMETER MEASUREMENT INFORMATION
VOH
Q
- - - - - - - - - - - - - - - - HI-Z - - - - - - - - - - - - - - - -
VOL
NOTES: A. Referenced to CAS or W, whichever occurs last.
B. A read cycle or a read-write cycle can be intermixed with write cycle as long as read and read-write timing specifications are not
violated.
Figure 7. Enhanced Page-Mode Write Cycle Timing
TEXAS ~
INSfRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
4-19
TMS441 00, TMS44100P
4 194 304·BIT
DYNAMIC RANDOM·ACCESS MEMORY
SMHS41 OF--SEPTEMBER 1989-REVISED DECEMBER 1992
PARAMETER MEASUREMENT INFORMATION
tRP~
I..
RAS
~I
tRASP
~
I
~!
Y i 'I - I I VIH
I!~11'-------------------------'_ I
VIL
~I
I I
I..
tpRWC
I I"
tCSH :
~I I"
I ~ tRCO ----T+!
I I
I ~tcAs4
I:
I I
I I"
-.I
14+ tASR
i -41
I
~
I 1.. 1
~I
'+
tRAO I
tASC +I
I
tRhH
I
tAR
AO-A10~
_
I
I
I -
I
I
I..
I
W
I
I
*- tCAH --.I
~i
I I
~
-.i
~I
I
.i
itRWO
I
I
i
*
-411
I
I I
I..
_f0·~
I
I
I"
i
tCLZ~
I
I
I I I
~
VIL
~~.,m-,.~~~~t~}i*~.~~:::
Column
14- tCWL ~I II II
i+- tRWL ---1+1
+I
twp
~I
~I'
I
I
VIH
1 - V I L
tos
~I
Vo'.
tAA .
tRA
I
I
I
I
tOH
I
I
I
~
~I
I
I
I"
------------{:XX:XXx.
I
I
I
I
1-.1
tCLZ~
tCPA
i
(see Note A)
I
I
I
+. r-)~$HR*~:::
~Hf.1X
~ tCAC ~
I
I"
i
~tcwo
.i ~I,'N
Ie
tCRP
!tit-I+!- - - - - - V I H
I
>@<:
~I
I ~ tRSH -41
I
I
I
I
I
I
I
~ tAWO ~!.-
I RCS
I.. I
I I
tcp
u--\l
cHmn
I
I4---r t
~i
iii
~~
11'
:i
Q
I
I
I
~i
~tOFF
I
I
i
I
(see Note A)
VOH
Valid Out
NOTES: A. Output may ~o from three-state to an invalid data state prior to the specified access time.
B. A read or write cycle can be intermixed with read-write cycles as long as the read and write timing specifications are not violated.
Figure 8. Enhanced Page-Mode Read-Write Cycle Timing
TEXAS
~
INSTRUMENTS
4-20
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
TMS441 00, TMS44100P
4 194 304·81T
DYNAMIC RANDOM·ACCESS MEMORY
SMHS410F-SEPTEMBER 1989--REVISED DECEMBER 1992
PARAMETER MEASUREMENT INFORMATION
(see Note A)
a--------------------------------------------------------------NOTE A:
VOH
VOL
Al0 is a don't care.
Figure 9. RAS·Only Refresh Timing
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
4·21
TMS441 00, TMS44100P
4 194 304·81T
DYNAMIC RANDOM·ACCESS MEMORY
SMHS410F-8EPTEMBER 1989-REVISED DECEMBER 1992
PARAMETER MEASUREMENT INFORMATION
1~~---------------------tRC------------------~
·1
I+- tRP ~ ~1~f---------tRAS _ _ _ _--,-_~
.1
RAS
N
I
JfI
_I
tRPC CAS
1
1 1
I I
1
Y
I~----------------------~
j+- tcSR -+i I
~
I
14~----tcHR
~rtr
VIH
••
w~
·1
VIL
.1
y
twSR~I'III~= lrtl..~--:---------::A
'i
VIH
twHR
.
VIL
V
IH
VIL
D~tifK~aX{~V'H
VIL
Q---------------HI-Z--------------NOTE A: Al0isadon'Icare,
Figure 10_ Automatic (CAS-before-RAS) Refresh Cycle Timing
TEXAS ~
INSTRUMENTS
4-22
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
VOH
TMS441 00, TMS44100P
4 194 304·81T
DYNAMIC RANDOM·ACCESS MEMORY
SMHS41 OF-SEPTEMBER 198~REVISED DECEMBER 1992
PARAMETER MEASUREMENT INFORMATION
I+--
Memory Cycle
I.~
1
1 I.
1 1
RAS
~ Refresh Cycle
---+j
.1 1 tRAS
1 1
J1
~
1 1
I
I
tAR ..........__-t-~
1
1
I·
N
I
I
I
I
I
tRP
: :
I I
r
----+i
~I
I.
.: 1 tRAS
Y
Refresh Cycle ~
1
1
tRP
7\
I
&____
tCHR
: :
tCAS I 1
(
j
I
~~tCAH
1 ~ ~ tASC
:
AO-A10
1
j4- "',.
I ~ ~"'_
W" Ii.'
: :: V
.Wlllll/.
,'RCS
W
II
I
,.,
I'"
I
1
I
I
VIL
.1
}~
1:1
--'I
VIH
VIL
I
1
:
1
I
'WHR
-xx>A
1
16
17
18
5
I"'-.
~
4
~
23
W
2
24
OQ2
DQ3
DQ4
C20[ROW)
G23/IREFRESH ROW)
24[PWR OWN)
C21[COLUMN)
~
> 23C22
&
24,25EN
23210
G25
,....
r
"l
1
OQ1
20019/2109
r-... G24
3
22
OE
04~575
l.-
A,22D
'i7 26
A,Z26
25
tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and lEe Publication 617-12.
The pin numbers shown are for the 20/26 pin SOJ packages.
functional block diagram
,
AO
A1
A9
Column
Address
Buffera
1
~
16
•
•
Column Decode
Z
128KArray
128KArray
•
16
Row
Address
Buffera
••
128KArray
R
0
w
1Q
/
128KArray
10
~
128KArray
•
••
D
e
c
0
d
e
'--
-
W
Sense Ampllflera
f-+-
L
•
t
Timing and Control
/
•
•
•
t
t
j-
I
:> 16
2.f-128KArray
of
/
TEXAS
~
INsrRUMENTS
4-30
I/O
Buffera
40f16
Selection
POST OFFICE BOX 1443' HOUSTON. TEXAS 77001
~
~
In
Reg.
Out
Reg.
OQ1-OQ4
TMS44400, TMS44400P
1 048 576·WORD BY 4·BIT
DYNAMIC RANDOM·ACCESS MEMORY
SMHS440F-OCTOBER
198~EVISEDAPRIL 1993
absolute maximum ratings over operating free·alr temperature range (unless otherwise noted)t
Voltage range on any pin (see Note 1) ................................................. -1 V to 7 V
Voltage range on Vee ............................................................... -1 V to 7 V
Short circuit output current ................................................................ 50 rnA
Power dissipation .......................................................................... 1 W
Operating free-air temperature range .................................................. O°C to 70°C
Storage temperature range ....................................................... - 55°C to 150°C
t Stresses beyond those listed under "absolute maximum ratings· may cause permanent damage to the device. This is a stress rating only, and
functional operation of the device at these or any other conditions beyond those indicated In the "recommended operating conditions' section of
this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values in this data sheet are with respect to VSS.
recommended operating conditions
UNIT
MIN
NOM
MAX
Vee
Supply voltage
4.5
5
5.5
V
VIH
High-level input voltage
2.4
6.5
V
VIL
Low-level input vo~age (see Note 2)
-1
0.8
V
TA
Operating free-air temperature
0
70
·C
NOTE 2: The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used in this data sheet for logic
voltage levels only.
TEXAS
~
INSIRUMENTS
POST OFFICE BOX 1443· HOUSTON, TEXAS 77001
4-31
TMS44400,· TMS44400P
1 048 576-WORD BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SMHS440F-OCTOBER 1989-REVISED APRIL 1993
electrical characteristics over full ranges of recommended operating conditions (unless otherwise
noted)
PARAMETER
TMS44400-60
TMS44400P-60
TEST CONDITIONS
MIN
VOH
High-level output
voltage
VOL
Low-level output
voltage
IOL=4.2mA
II
Input current
(leakage)
VI = Oto 6.5 V, VCC = 5.5 V,
All other pins = 0 to V CC
10
Output current
(leakage)
Vo = 0 to Vce, VCC
leel t
Read or write cycle
current (see Note 3)
Minimum cycle, VCC = 5.5 V
MAX
2.4
IOH=-5mA
= 5.5 V, CAS high
Standby current
After 1 memory cycle,
RAS and CAS high,
VIH = VCC -0.05 V (CMOS)
ICC3
Average refresh
current (RAS-only
or CBR) (see Note 3)
Minimum cycle, VCC = 5.5 V,
RAS cycling, CAS high (RAS-only),
RAS low after CAS low (CBR)
ICC4 t
Average page
current (see Note 4)
tpc = minimum, VCC = 5.5 V RAS low,
CAS cycling
ICCS t
Self-refresh current
CAS, RAS < 0.2 V,
measured after tRASS min.
ICC7 t
Standby current
RAS = VIH, CAS = VIL,
Data out = Enabled
ICC10
Battery backup
operating current
(equivalent refresh
time is 128 ms)
CBRonly
tRC = 125 J.ls, tRAS :< 1 ms,
VCC - 0.2 V :< VIti:' 6.5 ~
OV ",VIL:<0.2V, Wand OE =VIH,
Address and Data stable
MIN
UNIT
MAX
2.4
V
0.4
0.4
,010
,010
,010
!IA
,010
,010
,010
!IA
105
90
80
mA
2
2
2
mA
1
1
1
mA
500
500
500
!IA
105
90
80
mA
90
80
70
mA
500
500
500
!IA
5
5
5
mA
500
500
500
!IA
I
'44400P
t Measured with outputs open.
NOTES: 3. Measured with a maximum of one address change while RAS = VIL.
4. Measured with a maximum of one address change while CAS = VIH.
~
INSTRUMENTS
4-32
MAX
TMS44400-S0
TMS44400P-S0
0.4
1'44400
TEXAS
MIN
2.4
After 1 memory cycle, RAS and CAS high,
VIH = 2.4 V (TTL)
ICC2
TMS4440D-70
TMS44400P·70
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
V
TMS44400, TMS44400P
1 048 576·WORD BY 4·BIT
DYNAMIC RANDOM·ACCESS MEMORY
SMHS440F-OCTOBER 1989-REVISEDAPRIL 1993
capacitance over recommended ranges of supply voltage and operating free-air temperature,
f = 1 MHz (see Note 5)
PARAMETER
MIN
TYP
MAX
UNIT
Ci(A)
Input capacitance, address inputs
5
pF
CilRC)
Input capacitance, strobe inputs
7
pF
CUW)
Input capacitance, write-enable input
7
pF
Co
Output capacitance
7
pF
NOTE 5: VCC equal to 5 V
±
0.5 V and the bias on pinS under test IS 0 V.
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature
TMS44400-60
TMS44400P-60
PARAMETER
MIN
MAX
TMS44400-70
TMS44400P-70
MIN
MAX
TMS44400-BO
TMS44400P-BO
MIN
UNIT
MAX
tM
Access time from column-address
30
35
40
ns
tCAC
Access time from CAS low
15
18
20
ns
tCPA
Access time from column precharge
35
40
45
ns
tRAC
Access time from RAS low
60
70
80
ns
tOEA
Access time from OE low
20
ns
tCLZ
CAS to output in low Z
0
tOFF
Output disable time after CAS high (see Note 6)
0
15
0
18
0
20
ns
tOEZ
Output disable time after OE high (see Note 6)
0
15
0
18
0
20
ns
15
18
0
ns
0
NOTE 6: toFF and tOEZ are specified when the outp'ut is no longer driven.
TEXAS
~
INSfRUMENTS
POST OFFICE BOX 1443· HOUSTON. TEXAS 77001
4-33
TMS44400, TMS44400P
1 048 576-WORD BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SMHS440F-OCTOBER 1989-REVISED APRIL 1993
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
TMS44400-60
TMS44400P-60
MAX
MIN
TMS44400-70
TMS44400P-70
MIN
MAX
TMS44400-80
TMS44400P-S0
MIN
UNIT
MAX
tRC
Random read or write cycle (see Note 7)
110
130
150
ns
tRWC
Read-write cycle time
155
181
205
ns
tpc
Page-mode read or write cycle time (see Note 8)
40
45
50
ns
tPRWC
Page-mode read-write cycle time
85
96
105
tRASP
Page-mode pulse duration, RAS low (see Note 9)
60
100 000
70
100 000
80
100 000
ns
tRAS
Non-page-mode pulse duration, RAS low (see Note 9)
60
10 000
70
10000
80
10 000
ns
tCAS
Pulse duration, CAS low (see Note 10)
15
10 000
18
10000
20
10000
ns
tcp
Pulse duration, CAS high
10
10
10
ns
tRP
Pulse duration, RAS high (precharge)
40
50
60
ns
twp
Write pulse duration
15
15
15
ns
tASC
Column-address setup time before CAS low
0
0
0
ns
tASR
Row-address setup time before RAS low
0
0
0
ns
ns
tDS
Data setup time (see Note 11)
0
0
0
ns
tRCS
Read setup time before CAS low
0
0
0
ns
tCWL
W-Iow setup time before CAS high
15
18
20
ns
tRWL
W-Iow setup time before RAS high
15
18
20
ns
twcs
W-Iow setup time before CAS low (Early write operation only)
0
0
0
ns
twSR
W-high setup time (CAS-before-RAS refresh only)
10
10
10
ns
twTs
W-Iow setup time (test mode only)
10
10
10
ns
tCAH
Column-address hold time after CAS low
10
15
15
ns
tDHR
Data hold time after RAS low (see Note 12)
50
55
60
ns
tDH
Data hold time (see Note 11)
10
15
15
ns
tAR
Column-address hold time after RAS low (see Note 12)
50
55
60
ns
tRAH
Row-address hold time after RAS low
10
10
10
ns
tRCH
Read hold time after CAS high (see Note 13)
0
0
0
ns
tRRH
Read hold time after RAS high (see Note 13)
0
0
0
ns
twCH
Write hold time after CAS low (Early write operation only)
15
15
15
ns
twCR
Write hold time after RAS low (see Note 12)
50
55
60
ns
twHR
W-high hold time (CAS-before-RASr efresh only)
10
10
10
ns
twTH
W-Iow hold time (test mode only)
10
10
10
ns
tAWD
Delay time, column address to W low
(Read-write operation only)
55
63
70
ns
Continued next page.
NOTES: 7. All cycle times assume IT 5 ns.
8. To assure tpc min, tASC should be greater than or equal to 5 ns.
9. In a read-write cycle, tRWD and tRWL must be Observed.
10. In a read-write cycle, tCW~d tCWLmust be Observed.
11. Referenced to the later of CAS or W. in write operations.
12. Etther tRRH or tRCH must be satisfied for a read cycle.
13. The minimum value is measured when tRCD is set to tRCD min as a reference.
=
TEXAS ~
INSTRUMENTS
4-34
POST OFFICE BOX'443 • HOUSTON, TEXAS
noo,
TMS44400, TMS44400P
1 048 576·WORD BY 4·BIT
DYNAMIC RANDOM·ACCESS MEMORY
SMHS440F-OCTOBER 1989-REVISED APRIL 1993
timing requirements over recommended ranges of supply voltage and operating free·air
temperature (concluded)
TMS44400-60
TMS44400P~O
MIN
tcHR
Delay time, RAS low to CAS high
(CAS-before-RAS refresh only)
MAX
15
TMS44400-70
TMS44400P-70
MIN
MAX
15
TMS44400-80
TMS44400P-BO
MIN
UNIT
MAX
20
ns
tCRP
Delay time, CAS high to RAS low
0
0
0
ns
tCSH
Delay time, RAS low to CAS high
60
70
80
ns
tCSR
Delay time, CAS low to RAS low
(CAS-before-RAS refresh only)
10
10
10
ns
tCWD
Delay time, CAS low to W low (Read-write operation only)
40
46
50
ns
toEH
DE command hold time
15
18
20
ns
tOED
DE to data delay
15
18
20
ns
tROH
RAS hold time referenced to DE
10
10
10
tRAD
Delay time, RAS low to column-address (see Note 14)
15
tRAL
Delay time, column-address to RAS high
30
35
40
tCAl
Delay time, column address to CAS high
30
35
40
tRCD
Delay time, RAS low to CAS low (see Note 14)
20
tRPC
Delay time, RAS high to CAS low (CBR only)
tRSH
30
45
15
20
35
52
15
20
ns
40
ns
ns
ns
60
ns
0
0
0
ns
Delay time, CAS low to RAS high
15
18
20
ns
tRWD
Delay time, RAS low to W low (Read-write operation only)
85
98
110
ns
trAA
Access time from address (test mode)
35
40
45
ns
trCPA
Access time from column precharge (test mode)
40
45
50
ns
trRAC
Access time from RAS (test mode)
65
75
85
ns
tcps
CAS precharge before self-refresh
0
0
0
ns
tRPS
RAS precharge after self-refresh
110
130
150
ns
tRASS
Self-refresh entry from RAS low
100
100
100
~s
tCHS
CAS low hold time after RAS high (self-refresh)
-50
-50
-50
ns
tREF
Refresh time interval
tr
Transition time
1'44400
I '44400P
2
16
16
16
ms
128
128
128
ms
50
ns
50
2
50
2
NOTE 14: The maximum value IS specified only to assure access time.
1ExAs . "
INsrRUMENTS
POST OFFICE SOX 1443 • HOUSTON. TEXAS 77001
4-35
TMS44400, TMS44400P
1 048 576·WORD BY 4·BIT
DYNAMIC RANDOM·ACCESS MEMORY
SMHS440F-OCTOBER
198~REVISED
APRIL 1993
PARAMETER MEASUREMENT INFORMATION
1.31 V
VCC=5V
-lT
RL -2180
Output Under Test
Output Under Test - - . - - - - - .
CL = 100 pF
CL=100pF
(b) Alternate Load Circuit
(a) Load Circuit
Figure 1. Load Circuits for Timing Parameters
NOTE A: Output may go from three-state to an invalid data state prior to the specified access time.
Figure 2. Read Cycle Timing
TEXAS
~
INSTRUMENTS
4-36
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
TMS44400, TMS44400P
1 048 576-WORD BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SMHS440F-OCTOBER 19S5-REVISED APRIL 1993
PARAMETER MEASUREMENT INFORMATION
Figure 3. Early Write Cycle Timing
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
4-37
TMS44400, TMS44400P
1 048 576·WORD BY 4·BIT
DYNAMIC RANDOM·ACCESS MEMORY
SMHS440F--OCTOBER 1989-REVISED APRIL 1993
PARAMETER MEASUREMENT INFORMATION
Figure 4. Write Cycle Timing
TEXAS ~
INSI'RUMENTS
4·38
POST OFFICE BOX 1443 • HOUSTON, TEXAS nOO1
TMS44400, TMS44400P
1 048 576·WORD BY 4·BIT
DYNAMIC RANDOM·ACCESS MEMORY
SMHS440F-OCTOBER 1989-REVISED APRIL 1993
PARAMETER MEASUREMENT INFORMATION
1~4--------------------tRWC--------------------~~1
RAS
--.l~I
CAS
11:
~.---------------tRAS
1
1
1_
...
1
1 I..
!4-"1
f4--2
i
tRCD
1_;
1
..,-- tASR.
~tRAH
trAD +I
1+
--+t
N'144-------tcAS
~I"--_ _ _ VIH
~
tRP
VIL
1 tCRP----+I
...ytlli4i-
...
1 '
I
1 ~------------"I ~ tcp
1 I
III
:i4-:-sc--t~~i tcAH
~
*t
IT
Jr--....I.--":" L7===~~~~~~ I , . . . . . - - - - - - - V I H
AO--A9
NOTE A:
Figure 5. Read-write Cycle Timing
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
4·39
TMS44400, TMS44400P
1 048 576·WORD BY 4·BIT
DYNAMIC RANDOM·ACCESS MEMORY
SMHS440F-OCTOBER
198~REVISEDAPRIL 1993
PARAMETER MEASUREMENT INFORMATION
AG-A9
_ Xf.Xf.XIT I
W
I
~ I+--- tRAD ---+i
I
I
I
I,.
I
I
I
I
I
I
I
.~ VIL
1~
..----tCPA---tI---i~~1
I
1,.--1 !cAC
tAA
tRAC
~
(see Note B)
.1
~I
~t
I
!.II
_
OFF
I
DQ1-DQ4--------~-~~~{XXXXXXI Valid I}----<:XXXXXX
(see Note A)
Out
I
I
I"-- tOEA ---.I
I --+j *- toEZ
OE~~*X~~~tOEA~ ~
NOTES: A. Output may go from three-state to an invalid data state prior to the specified access time.
B. Access time is tePA or tAA dependent.
Figure 6. Enhanced Page-Mode Read Cycle Timing
TEXAS .."
INSTRUMENTS
4-40
-ffi VIH
::
W
",-I..f--+-.-
tCLZ
~
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
- I
I
VOH
I
VOL
Valid
Out
jill
~I
~VIH
tOEZ
VIL
TMS44400, TMS44400P
1 048 576·WORD BY 4·BIT
DYNAMIC RANDOM·ACCESS MEMORY
SMHS440F-OCTOBER 1989--REVISED APRIL 1993
PARAMETER MEASUREMENT INFORMATION
~
tRP
'l\r
tRASP
i\
~I I~
l(:SH
1 I
I
I 14-- tRCO - . .
. I
I I
~tCAS+J
i1
1 I
I
I
J+
I~
I I
14--~~I-1
I
tASC
tRAH
tASR
~h
1
~
V,H
I "--- V,L
{
i+-tCRP~
~ tRSH ~I
I
N
1
J.-
1 I
I 1
1 I
I
I
1 ItAR I I
1
' I I
1 I
I ~ tCAH ~
I I
I
I
+1
~I
tpc
I
I
I
Vi
~\l
~I
/;""-'1-1-----
1
l(:p
--.I
I~
tRAL
I
l..---tCAL
1
I
I
I
I
~I
I
I
V,H
V,L
AO-A9
j+-tRAO -+j
twCR -+-t-~
I~
I~
I
I
I~
I
I
I
W vvvV',,,,,
I
I
~tOH~
101
...
i4~---- tos __--c-~
tOH
(see Note
A)
~I
I
I
~ tOEH ~
V,L
i+-tOEH
I
OQ1-0Q4~============v=al=ld=o=a:ta='n============~~
_
I
~tRWL~
14+-+--+1- twp
tOED
-+'
-+I
Vf~'d ~o~i~aX~
~
I
I
V,H
V,L
NOTES: A. Referenced to CAS or W, whichever occurs last.
B. A read cycle or a read-write cycle can be intermixed with write cycle as long as read and read-write timing specifications are not
violated.
Figure 7. Enhanced Page-Mode Write Cycle Timing
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
4-41
TMS44400, TMS44400P
1 048 576·WORD 8Y 4·81T
DYNAMIC RANDOM·ACCESS MEMORY
SMHS440F-OCTOBER 1989-REVISEDAPRIL 1993
PARAMETER MEASUREMENT INFORMATION
RAS
tRP~
~
1
: \....
~ ~t----------tRASP -----------~I ~
I
!'i-
,~-----------------------',
, 14,10lIl---- tcSH ----~~,
~
i"'I'OIIII----- tRSH ----1~~,
, ,
1'II,..f---- tPRWC'
~I
tcRP ~ ,
~
'1 0lIl
:~I
,
1 ~~
tRCD
~
iV-tCAS
tASR' ,
VIH
VIL
I
~I
l;.-tl_ _ _ VIH
tcP
II
\{
,
"VIL
,
,
,
,
~~tASC'
j4---i-t--i----+.- tAR
I
,
Column
AO-A9
''II rL
~~~~~r='u.p.~~~
tcWD
,..
~fOIII
W 'IIII
, " ",
- I
I.,
,
.... '~tRCS
,
,.. ' ~,
I.,.- tRAC 'I-+r
I
tAA
_
~,1'1,
twP
,,!,
~I
-.....j;iI~~
~ tCPA ---+j
~, t D H ,
"
~!
,
tDS'
I"
-.l t.~
~lId'
I
~
~tOEA~ I ,
~ I+- tOEZ looiI"I---"'~'!-: tOEH
I
!
OEXXXX"x"x)!..
-
/
~ VIL
~,
,
,
,Valid Out
,(see Note A)
,
,
In
lOut,
~VIH
,
f+:+t tcAC i T ,
DQ1-DQ41--------L,~ Valid ~ V~~ld
tCLZ
,
,
1'-,
,..
tcWL
VIL
,
f4-- tRWL--.I
~'l
,I,: tRWD
,II I'
_
,
r
i
---+j
~ tAWD ~,
,
--.I
,0lIl
~
,
"
"
tOEH
)>rl______ V'HNOH
VILJVOL
tOED
,
,
\.Jit------,"\XXXXXXXXXXXX~~~~ VIH
~
.
"'""'"~~"""""''''"'''''''''VIL
NOTES: A. Output may go from three-state to an Invalid data state prior to the specified access time.
B. A read or wrne cycle can be Intermixed with read-write cycles as long as the read and write timing specifications are not violated.
Figure 8. Enhanced Page-mode Read-write Cycle Timing
ThxAs
4-42
~
INSlRUMENTS
POST OFFICE BOX 1443 •
HOUSTON~
TEXAS 77001
TMS44400, TMS44400P
1 048 576·WORD BY 4·BIT
DYNAMIC RANDOM·ACCESS MEMORY
SMHS440F-OCTOBER 1989-REVISEO APRIL 1993
PARAMETER MEASUREMENT INFORMATION
Figure 9. RAS·Only Refresh Timing
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
4·43
TMS44400, TMS44400P
1 048 576-WORD BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SMHS440F-OCTOBER 1989-REVISED APRIL 1993
PARAMETER MEASUREMENT INFORMATION
.,
,~4-------------------tRC------------------~
14-- tRP ~
,
RAS
If
,
• I
tRPC CAS
~14------ tRAS ____________~
·1 '
1 1
N
Y
1
'
1 ~I------------------------~
j+- tCSR -+i
~
1 114
4 - - - - - - - tCHR -------~.I
\J..
twSR
1'11
1
W~
Y
i I ~I ~
•
~ ____""*_
.,
twHR
VIH
VIL
VIH
~
V
IH
VIL
A~A9~~o~g*i~VIH
VIL
OE~2*22H~V'H
VIL
VIH
DQ1-DQ4---------------HI-Z - - - - - - - - - - - - - -
Figure 10. Automatic (CAS-Before-RAS) Refresh Cycle Timing
TEXAS
~
INSTRUMENTS
4-44
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
TMS44400, TMS44400P
1 048 576·WORD BY 4·BIT
DYNAMIC RANDOM·ACCESS MEMORY
SMHS440F-OCTOBER 1989-REVISED APRIL 1993
PARAMETER MEASUREMENT INFORMATION
Figure 11. Hidden Refresh Cycle (Read)
TEXAS ..I!rJ
INsrRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS nOO1
4-45
TMS44400, TMS44400P
1 048 576-WORD BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SMHS440F-OCTOBER 198~EVISED APRIL 1993
PARAMETER MEASUREMENT INFORMATION
Figure 12. Hidden Refresh Cycle (Write)
TEXAS ~
INsrRUMENTS
4-46
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
TMS44400, TMS44400P
1 048 576-WORD BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SMHS440F~CTOBER
1989-REVISEDAPRIL 1993
PARAMETER MEASUREMENT INFORMATION
,'~~-----tRASS ----+I.,,
N
fi
---' I
,
tRPC I~
tcSR
.,
~
~
_ _ _ _ _ _ _ _ _.J I
,
~
J+ tRPS +i
,
-++i J+-
,
~ l+-~t~CH~S~~~
I I
~r-,-~N
~
,
I
J+- tCPR --+t
AD-A9
QQ$§§Q§zQ§0ZQ§§§mH£~
w~mf~
oE~HHf~
~
OQ1-DQ4
i+-toFF
~_--
_ _ _ _ _ _ HI.Z _ _ _ _- - - - - - -
Figure 13. Self Refresh Timing
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS nOO1
4·47
TMS44400, TMS44400P
1 048 576·WORD BY 4·BIT
DYNAMIC RANDOM·ACCESS MEMORY
SMHS440F-OCTOBER 1989-REVISED APRIL 1993
PARAMETER MEASUREMENT INFORMATION
I~
·1
tRC
tRAS
·1 1
11
Y
VIH
VIL
AO-A9~oH~*~~VIH
VIL
OE@Q§00Q0@§§00Q§000§~J*HH~V'H
VIL
VIH
OQ1-DQ4 - - - - - - - - - - - - . _ _ - - - H I · Z - - - - - - - - - - - - - - -
Figure 14. Test Mode Entry Cycle
device symbolization
PTMS44400
W B
~
~
Speed (-60, -70, -80)
PtfJ¥:
Package Code
Lot Traceability Code
Month Code
Year Code
I
Aasembly Site Code
Ole Revision Code
Wafer Fab Code
TEXAS
~
INSIRUMENTS
4·48
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
TMS461 00, TMS46100P
4194 304·WORD BY 1·BIT
LOW·VOLTAGE DYNAMIC RANDOM·ACCESS MEMORIES
SMHS461-DECEMBER 1992
•
•
Organization ... 4194304 x
•
Low Power Dissipation (TMS46100P)
- 200 !lA CMOS Standby
- 200!lA Self-Refresh
- 300!lA Extended Refresh Battery Backup
•
DJ PACKAGEt
{TOP VIEW)
Single 3.3-V Power Supply
(±0.3-V Tolerance)
0
(tCAC)
(MAX)
(tAAl
(MAX)
TMS46100/P-80
70 ns
80 ns
18 ns
20 ns
35 ns
40 ns
TMS461OO/P-l0
100 ns
25 ns
50 ns
TMS46100/P-70
•
•
•
•
•
•
CAS
Q
RAS
NC
VSS
CAS
NC
A9
A1D
W
A1D
NC
Al
A3
A4
A6
A8
Performance Ranges:
(tRAC)
(MAX)
•
VSS
Vii
AD
Al
ACCESS ACCESS ACCESS
READ
TIME
TIME
TIME OR WRITE
•
SDPACKAGEt
{TOP VIEW)
CYCLE
(MIN)
130 ns
A8
A7
A6
A5
A4
A2
A3
VCC
150 ns
180 ns
Enhanced Page Mode Opration for Faster
Memory Access
- Higher Data Bandwidth Than
Conventional Page-Mode Parts
- Random Single-Bit Access Within a Row
With a Column Address
DGA PACKAGEt
{TOP VIEW)
0
VSS
Vii
Q
RAS
NC
CAS
NC
A9
A1D
CAS-Before-RAS Refresh
Long Refresh Period ...
- 1024-Cycle Refresh in 16 ms
- 128 ms (Max) for Extended-Refresh
Version (TMS46100P)
AD
Al
A8
A7
A6
A5
A4
A2
A3
3-State Unlatched Output
Vcc
Texas Instruments EPIC ™ CMOS Process
DGB PACKAGEt
{TOP VIEW)
VSS
D
Q
Vii
CAS
NC
A9
RAS
NC
High-Reliability Plastic 300-Mil 20/26-Lead
Surface Mount (SOJ) Packages,
20-Pin Zig-Zag In-line (ZIP) Package,
20/26-Lead Thin Small Outline Package,
and Reverse Thin Small Outline Package
Operating Free-Air Temperature Range
O°C to 70°C
AO-Al0
CAS
D
NC
Q
RAS
W
VCC
vss
description
:i:
A8
A7
A6
A5
AD
Al
A2
A3
0
A4
Vcc
W
C
The read or write mode is selected through the write-enable (W) input. A logic high on the W input selects the
read mode and a logic low selects the write mode. The write-enable terminal can be driven from standard TTL
circuits without a pull-up resistor. The data input is disabled when the read mode is selected. When W goes low
prior to CAS (early write), data out will remain in the high-impedance state for the entire cycle, permitting
common I/O operation.
data in (0)
Data is written during a write or read-write cycle. Depending on the mode of operation, the falling edge of CAS
or W strobes data into the on-chip data latch. In an early write cycle, W is brought low prior to CAS and the data
is strobed in by CAS with setup and hold times referenced to this signal. In a delayed-write or read-write cycle,
CAS will already be low, thus the data will be strobed in by W with setup and hold times referenced to this signal.
TEXAS ~
INSfRUMENTS
4-50
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
TMS461 00, TMS46100P
4194 304·WORD BY 1·BIT
LOW·VOLTAGE DYNAMIC RANDOM·ACCESS MEMORIES
SMHS461-DECEMBER 1992
data out (Q)
The three-state output buffer provides direct TIL compatibility (no pull up resistor required) with a fanout of two
Series 74 TIL loads. Data out is the same polarity as data in. The output is in the high-impedance (floating) state
until CAS is brought low. In a read cycle the output becomes valid after the access time interval tCAC
(which begins with the negative transition of CAS) as long as tRAC and tAA are satisfied. The output becomes
valid after the access time has elapsed and remains valid while CAS is low; CAS going high returns it to a
high-impedance state. In a delayed-write or read-write cycle, the output will follow the sequence for the read
cycle.
refresh
A refresh operation must be performed at least once every 16 ms (128 ms for TMS461 OOP) to retain data. This
can be achieved by strobing each of the 1024 rows (AO-A9). A normal read or write cycle will refresh all bits in
each row that is selected. A RAS-only operation can be used by holding CAS at the high (inactive) level, thus
conserving power as the output buffer remains in the high-impedance state. Externally generated addresses
must be used for a RAS-only refresh. Hidden refresh may be performed while maintaining valid data atthe output
pin. This is accomplished by holding CAS at VIL after a read operation and cycling RAS after a specified
precharge period, similar to a RAS-only refresh cycle. The external address is ignored during the hidden refresh
cycles.
CAS-before-RAS refresh
CAS-before-RAS refresh is utilized by bringing CAS low earlier than RAS [see parameter .!c.s.Bl and holding it
low after RAS falls (see parameter tCHR)' For successive CAS-before-RAS refresh cycles, CAS can remain low
while cycling RAS. The external address is ignored and the refresh address is generated internally.
A low-power battery-backup refresh mode that requires less than 300 rtA refresh current is available on the
TMS461 OOP. Data integrity is maintained using CAS-before-RAS refresh with a period of 125 [!S, while holding
RAS low for less than 1 [!s. To minimize current consumption, all input levels need to be at CMOS levels
(VIL:S 0.2 V, VIH" VCC - 0.2 V).
self refresh
The self-refresh mode is entered by dropping CAS low prior to RAS going low. Then CAS and RAS are both
held low for a minimum of 100 [!s. The chip is then refreshed by an on-board oscillator. No external address is
required since the CBR counter is used to keep track of the address. To exit the self-refresh mode, both RAS
and CAS are brought high to satisfy tCHS' Upon exiting the self-refresh mode, a burst refresh (refresh a full set
of row addresses) must be ex-ecuted before continuing with normal operation. This will ensure the DRAM is fully
refreshed.
power-up
To achieve proper device operation, an initial pause of 200 [!S followed by a minimum of eight initialization cycles
is required after full VCC level is achieved. These eight initialization cycles need to include at least one refresh
(RAS-only or CAS-before-RAS) cycle.
test mode
An industry standard Design For Test (DFT) mode is incorporated in the TMS46100 and TMS46100P. A
CAS-before-RAS cycle with W low (WCBR) cycle is used to enter test mode. In the test mode, data is written
into and read from eight sections of the array in parallel. Data is compared upon reading and if all bits are equal,
the data out pin will go high. If anyone bit is different, the data out pin will go low. Any combination of read, write,
read-write, or page-mode can be used in the test mode. The test mode function reduces test times by enabling
the 4 meg DRAM to be tested as if it were a 512K DRAM, where row address 10, column address 10, and also
column address 0 are not used. A RAS-only or CBR refresh cycle is used to exit the DFT mode.
TEXAS
~
INsrRUMENTS
POST OFFICE BOX 1443 • HOUSTO~. TEXAS 77001
4-51
z
o
~
:!:
a:
ou.
z
w
o
z
~
c
33C32
25
AV
Q
tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
The pin numbers shown are for the 20/26 pin SOJ package (DJ suffix).
,,,
." functional block diagram
o
::D
s:
~
oz
34 EN
3331D
A,32D
I
't
AO
A1
Al0
Timing and Control
1
8
16
/
•
•
•
Column
Address
Buffers
3
•
~
128KArray
128KArray
R
128KArray
16
Row
Address
Buffers
•
••
0
10
I
0
r-11-'
128KArray
•
••
w
D
e
c
'--
W
Sense Amplifiers
+-
L
•
•
Column Decode
10
128KArray
"I
/
TEXAS
~
INSTRUMENTS
4-52
16
I/O
Buffers
1 of 16
Selection
31--
d
e
128KArray
-±
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
1.--
~
~
In
Reg.
Out
Reg.
D
Q
TMS461 00, TMS46100P
4194 304·WORD BY 1·BIT
LOW·VOLTAGE DYNAMIC RANDOM·ACCESS MEMORIES
SMHS461-DECEMBER 1992
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Voltage range on any pin (see Note 1) .............................................. - 0.5 V to 4.6 V
Voltage range on Vee ............................................................ - 0.5 V to 4.6 V
Short circuit output current ................................................................ 50 rnA
Power dissipation .......................................................................... 1 W
to 70°C
Operating free-air temperature range ..................................................
Storage temperature range ....................................................... - 55°C to 150°C
ooe
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. This is a stress rating only, and
functional operation of the device at these or any other conditions beyond those indicated in the "recommended operating conditions" section of
this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values in this data sheet are with respect to VSS.
recommended operating conditions
MIN
NOM
MAX
Vee
Supply voltage
3.0
3.3
3.6
V
VIH
High-level input voltage
2.0
Vee +0.3
V
VIL
Low-level input voltage (see Note 2)
-0.3
0.8
V
TA
Operating free-air temperature
0
70
'e
UNIT
NOTE 2: The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used in this data sheet for logic
voltage levels only.
z
E;;
o
......
:E
a:
o
LL
Z
W
o
Z
~
c
1000 ms
200
200
200
I'A
ICCIOt
Battery backup
(with CBR)
tRC = 1251's, tRAS " I ms,
VCC-0.2V" VIH" 3.9 V,
o V " VIL ,,0.2 V,
Vii and OE = VIH,
Address and Data stable
300
300
300
I!A
:xl
3:
TMS461 00-80
TMS46100P-70
After I memory cycle,
RAS and CAS high,
VIH = 2.0 V (LVTTL)
'11
o
TMS461 00-70
0.2
l>
c
TEST
CONDITIONS
t For TMS461 OOP only.
NOTES: 3. Measured with a maximum of one address change while RAS = VIL.
4. Measured with a maximum of one address change while CAS = VIH.
TEXAS ~
INSTRUMENTS
4-54
POST OFFICE BOX 1443· HOUSTON, TEXAS 77001
TMS461 00, TMS46100P
4194 304-WORD BY 1-BIT
LOW-VOLTAGE DYNAMIC RANDOM-ACCESS MEMORIES
SMHS461-DECEMBER 1992
capacitance over recommended ranges of supply voltage and operating free-air temperature,
f = 1 MHz (see Note 5)
PARAMETER
MIN
TYP
MAX
UNIT
Ci(A)
Input capacitance, address inputs
5
Ci(RC)
Input capacitance, strobe inputs
7
pF
Ci(W)
Input capacitance, write-enable input
7
pF
Co
Output capacitance
7
pF
pF
NOTE 5: VCC equal to 3.3 V ± 0.3 V and the bias on pins under test is 0 V.
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature
TMS461 00-70
TMS46100P-70
PARAMETER
MIN
MAX
TMS461 00-80
TMS46100P-80
MIN
MAX
TMS461 00-1 0
TMS461 OOP-l 0
MIN
UNIT
MAX
tAA
Access time from column-address
35
40
45
ns
tCAC
Access time from CAS low
18
20
25
ns
tCPA
Access time from column precharge
40
45
50
ns
tRAC
Access time from RAS low
100
ns
tCLZ
CAS to output in low Z
0
tOFF
Output disable time after CAS high (see Note 6)
0
70
80
0
18
0
ns
0
20
0
25
ns
NOTE 6: tOFF is specified when the output is no longer driven.
z
o
~
:E
a:
oLL
Z
W
U
Z
~
c
«
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
4-55
TMS461 00, TMS46100P
4194 304·WORD BY 1·BIT
LOW·VOLTAGE DYNAMIC RANDOM·ACCESS MEMORIES
SMHS461-DECEMBER 1992
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
TMS461 00-70
TMS46100P-70
MAX
MIN
»
c
~
z
o
m
-z
"T1
o:JJ
s:
~
o
z
TMS461 00-80
TMS46100P-80
MIN
MAX
TMS461 00-1 0
TMS46100P-l0
MIN
UNIT
MAX
tRC
Random read or write cycle (see Note 7)
130
150
180
ns
tRWC
Read-write cycle time
153
175
210
ns
tpc
Page-mode read or write cycle time (see Note 8)
45
50
55
ns
tpRWC
Page-mode read-write cycle time
68
75
85
tRASP
Page-mode pulse duration, RAS low (see Note 9)
70
100000
70
10 000
tRAS
Non-page-mode pulse duration, RAS low (see Note 9)
tRASS
Self-refresh, RAS low time
tCAS
Pulse duration, CAS low (see Note 10)
100
18
100000
100
100000
ns
80
10000
100
10 000
ns
10 000
ns
100
10 000
ns
80
20
100
10000
25
ns
tcp
Pulse duration, CAS high
10
10
10
tRP
Pulse duration, RAS high (precharge)
50
60
70
ns
tRPS
Self-refresh, RAS high (precharge)
130
150
180
ns
twp
Write pulse duration
15
15
20
ns
tASC
Column-address setup time before CAS low
0
0
0
ns
tASR
Row-address setup time before RAS low
0
0
0
ns
ns
tDS
Data setup time (see Note 11)
0
0
0
ns
tRCS
Read setup time before CAS low
0
0
0
ns
tCWL
W-Iow setup time before CAS high
18
20
25
ns
tRWL
W-Iow setup time before RAS high
18
20
25
ns
twcs
W-Iow setup time before CAS low (Early write operation only)
0
0
0
ns
twSR
W-high setup time (CAS-before-RAS refresh only)
10
10
10
ns
twTs
W-Iow setup time (test mode only)
10
10
10
ns
tCAH
Column-address hold time after CAS low
15
15
20
ns
tDHR
Data hold time after RAS low (see Note 13)
55
60
75
ns
tDH
Data hold time (see Note 10)
15
15
20
ns
tAR
Column address hold time after RAS low (see Note 13)
55
60
75
ns
tRAH
Row-address hold time after RAS low
10
10
15
ns
tRCH
Read hold time after CAS high (see Note 12)
0
0
0
ns
tRRH
Read hold time after RAS high (see Note 12)
0
0
0
ns
twCH
Write hold time after CAS low (Early write operation only)
15
15
20
ns
twCR
Write hold time after RAS low (see Note 13)
55
60
75
ns
twHR
W-high hold time (CAS-before-RAS refresh only)
10
10
10
ns
twTH
W-Iow hold time (test mode only)
10
10
10
ns
tAWD
Delay time, column address to W low
(Read-write operation only)
35
40
45
ns
tCHR
Delay time, RAS low to CAS high
(CAS-before-RAS refresh only)
15
20
20
ns
tCRP
Delay time, CAS high to RAS low
0
0
0
ns
tCSH
Delay time, RAS low to CAS high
70
80
100
ns
NOTES:
7.
8.
9.
10.
11.
12.
13.
All cycle times assume tT = 5 ns.
To assure tpc min, tASC should be greater than or equal to 5 ns.
In a read-write cycle, tRWD and tRWL must be observed.
In a read-write cycle, tCWD and tCWL must be observed.
Referenced to the later of CAS or W in write operations.
Either tRRH or tRCH must be satisfied for a read cyele.
The minimum value is measured when tRCD is set to tRCD min as a reference.
TEXAS ~
INSTRUMENTS
4-56
POST OFFICE BOX' 443 • HOUSTON, TEXAS 7700'
TMS461 00, TMS46100P
4194 304-WORD BY 1-BIT
LOW-VOLTAGE DYNAMIC RANDOM-ACCESS MEMORIES
SMHS461-DECEMBER 1992
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (concluded)
TMS461 00-60
TMS46100P-60
MIN
MAX
TMS461 00-70
TMS46100P-70
MIN
TMS461 00-80
TMS46100P-80
MAX
MIN
UNIT
MAX
tCSR
Delay time, CAS low to RAS low
(CAS-before-RAS refresh only)
tCHS
Self-refresh, CAS low hold time after RAS high
tCWD
Delay time, CAS low to W low
(Read-write operation only)
tRAD
Delay time, RAS low to column-address (see Note 14)
15
tRAl
Delay time, column-address to RAS high
35
40
45
ns
tCAl
Delay time, column address to CAS high
35
40
45
ns
tRCD
Delay time, RAS low to CAS low
(see Note 14)
20
tRPC
Delay time, RAS high to CAS Idw
0
tRSH
Delay time, CAS low to RAS high
18
tRWD
Delay time, RAS low to W low
(Read-write operation only)
70
10
10
10
ns
-50
-50
-50
ns
18
20
25
ns
35
52
40
15
60
20
50
20
25
75
ns
ns
0
ns
20
25
ns
80
100
ns
0
trAA
Access time from address (test mode)
40
45
50
ns
trCPA
Access time from column precharge (test mode)
45
50
55
ns
trRAC
Access time from RAS (test mode)
tREF
Refresh time inteNal
tr
Transition time
75
85
I '46100P
16
128
2
50
ns
105
16
1'46100
128
50
2
2
16
ms
128
ms
50
ns
z
o
~
~
a:
oLL
Z
W
o
NOTE 14: The maximum value is specified only to assure access time.
Z
~
PARAMETER MEASUREMENT INFORMATION
1.4V
~
Output Under Test
«
VCC =3.3V
Rl
= 500
R 1 =11780
0
~
Cl=l00pF
c
Output Under Test - -.....- - - .
T
Cl = 100 pF
(b) Alternate Load Circuit
(a) Load Circuit
Figure 1. Load Circuits for Timing Parameters
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
4-57
TMS461 00, TMS46100P
4194 304·WORD BY 1·BIT
LOW·VOLTAGE DYNAMIC RANDOM·ACCESS MEMORIES
SMHS461-DECEMBER 1992
PARAMETER MEASUREMENT INFORMATION
»
c
z~
o
m
-z
o"
:xJ
3:
~
o
-
NOTE A: Output may go from three-state to an invalid data state prior to the specified access time.
Figure 2. Read Cycle Timing
Z
TEXAS ~
INSTRUMENTS
4-58
POST OFFICE BOX 1443· HOUSTON. TEXAS 77001
TMS46100, TMS46100P
4194 304~WORD BY 1·BIT
LOW·VOLTAGE DYNAMIC RANDOM·ACCESS MEMORIES
SMHS461-DECEMBER 1992
PARAMETER MEASUREMENT INFORMATION
~--------------------tRc--------------------~·1
1+------------- tRAS
------------~.:
:
V!
~--------------......I
I"
tRSH
.1
~--- tRCO ----~.I
14-----------
,"
tcSH
tRP
VIL
.1I
rr--------~
If:
~
I 11
1
I
I
-I4-----.;·I~
~ tCAH
11
14-----rI-fI-
I ~I
..------- tcp --------~.I
.1
I
t?AL
..........____+1...1
1IRAL
CoI"T":
VIH
VIL
1 ·1
~222RE§$2X,---__ : : oz
-
IIICWL
.,
I+-----ilr----r--I-- tRWL
I ~ tWCH---.I
I
.1
I
I I
'4--a·*"11 FCS
I
::
I 14- tOH -+j
~--~I--twp
.1
I~
.. - -
.1 ~I
.. - I--tcRP--~.1
.1 I 1
tCAS
N
1 4 - - - tos
~
I '----
1
1
1
~
.1
:E
v
~R~it~*~·v::
z
I
~
w
1
1
1 4 - - - - - tOHR
a:
ou.
--------~.I
VOH
Q--------------HI-Z---------------
Figure 3. Early Write Cycle Timing
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
4-59
o
z
~
c
«
TMS46100, TMS46100P
4 194 304·WORD BY 1·BIT
LOW·VOLTAGE DYNAMIC RANDOM·ACCESS MEMORIES
SMHS461-DECEMBER 1992
PARAMETER MEASUREMENT INFORMATION
»
c
~
z
o
m
-z
"'T1
o
:IJ
:s::
~
o
z
Figure 4. Write Cycle Timing
TEXAs ."
INSrRUMENTS
4-60
POST OFFICE BOX 1443· HOUSTON, TEXAS 77001
TMS461 00, TMS46100P
4194 304·WORD BY 1·BIT
LOW·VOLTAGE DYNAMIC RANDOM·ACCESS MEMORIES
SMHS461-DECEMBER 1992
PARAMETER MEASUREMENT INFORMATION
z
o-
~
~
a:
o
11.
Z
W
(.)
Z
~
c
c
~
z
o
m
-z
"T1
olJ
3:
~
o
z
NOTES: A. Output may go from three-state to an invalid data state prior to the specified access time.
B. A read or write cycle can be intermixed with read-write cycles as long as the read and write timing specifications are not violated.
Figure 8. Enhanced Page-Mode Read-Write Cycle Timing
TEXAS ~
INSTRUMENTS
4-64
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
TMS461 00, TMS46100P
4194 304-WORD BY 1-BIT
LOW-VOLTAGE DYNAMIC RANDOM-ACCESS MEMORIES
SMHS461-DECEMBER 1992
PARAMETER MEASUREMENT INFORMATION
z
o
~
:E
a:
a------------------------------------------------------------NOTE A:
VOH
VOL
A10 is a don't care.
o
u..
z
w
o
z
c~
Figure 9. RAS·Only Refresh Timing
«
TEXAS ~
INsrRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
4-65
TMS461 00, TMS46100P
4194 304-WORD BY 1-BIT
LOW-VOLTAGE DYNAMIC RANDOM-ACCESS MEMORIES
SMHS461-DECEMBER 1992
PARAMETER MEASUREMENT INFORMATION
~1~-------------------tRC------------------~
·1
I+-- tRP ~ 141~------- tRAS _ _ _ _ _ _---.!
.1
N
;1
RAS
tRPC CAS
Y
1 ~I------------------------~
1
_I
1
1 1
1 1
1
!+-tCSR~
~
1
r-
14~------- tCHR
w~
-
VIL
.1
i
tr
y
tWSR~I;I'II==t.tl""t~----------~
~
1
VIH
VIH
VIL
·1 twHR
V
~IH
~VIL
»
c
~
z
o
VOH
m
-Z
Q--------------HI-Z--------------VOL
NOTE A: A10 is a don't care.
'T1
Figure 10. Automatic (CAS-Before-RAS) Refresh Cycle Timing
o:0
s:
!ioz
TEXAS ~
INsrRUMENTS
4-66
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
TMS461 00, TMS46100P
4194 304·WORD BY 1·BIT
LOW·VOLTAGE DYNAMIC RANDOM·ACCESS MEMORIES
SMHS461-OECEMBER 1992
PARAMETER MEASUREMENT INFORMATION
~I~------'.r-I tRPS
t
~ RP~ 141~------tRASS------~.1 I
)-
J
N
RAS/I
1
_I
tRPC CAS
{,
-0
L
1
I I
!+- tCSR ~
~
I
1 I
I
I
I I
tCHS
I~
VIH
VIL
.1
}Ir..
"\i~
~ II·~ ~
Jr
~;==:;r~t-----------------tWSR - I'll
• 1....--+1·1 twHR
w~
VIH
VIL
V
IH
VIL
z
VOH
a--------------HI-Z--------------
Figure 11. Self Refresh Cycle Timing
o
~
~
a:
o
u.
z
w
o
z
~
c
<3:
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
4-67
TMS461 00, TMS46100P
4194 304·WORD BY 1·BIT
LOW·VOLTAGE DYNAMIC RANDOM·ACCESS MEMORIES
SMHS461-DECEMBER 1992
PARAMETER MEASUREMENT INFORMATION
»
c
~
z
o
m
-z
"T1
o
:D
s::
-o~
z
Figure 12. Hidden Refresh Cycle (Read)
TEXAS ~
INSTRUMENTS
4·68
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
TMS461 00, TMS46100P
4194 304·WORD BY 1·BIT
LOW·VOLTAGE DYNAMIC RANDOM·ACCESS MEMORIES
SMHS461-DECEMBER 1992
PARAMETER MEASUREMENT INFORMATION
z
o
~
:?1
~VIH
VIL
a::
ou.
Z
LU
(,)
Z
~
Q
- - - - - - - - - - - HI-Z ----------~',''r-)- - - - - - -
VOH
Figure 13. Hidden Refresh Cycle (Write) Timing
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
4-69
o
16
17
18
5
r--..
4
~
r--..
»
c
23
~
o
m
-z
."
W
z
o
lJ
s:
~
OE
OQ1
OQ2
OQ3
OQ4
0
A 1 048575
3
22
~
~
C20 [ROW]
G23/[REFRESH ROW)
24 [PWR OWN)
C21[COLUMN)
G24
&
23210
I>
23C22
24,25 EN
"- G25
r
~
1
2
24
25
20019/2109
4-
A,22D
\726
A,Z26 -f-
tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and lEG Publication 617-12.
The pin numbers shown are for the 20/26 pin SOJ package (DJ suffix).
o
z
TEXAS
~
INSTRUMENTS
4-74
POST OFFICE BOX 1443' HOUSTON. TEXAS 77001
TMS46400, TMS46400P
1 048 576-WORD BY 4-BIT
LOW-VOLTAGE DYNAMIC RANDOM-ACCESS MEMORIES
SMHS464-JANUARY 1993
functional block diagram
I
..
AO
Al
~
•
Al0
Column
Address
Buffers
•
~
1
16
Column Decode
2
~
Sense Amplifiers
~
128KArray
128KArray
16 <
Row
Address
Buffers
~
8
L
•
•
OE
Timing and Control
/
•
•
~
W
•
•
•
128KArray
R
0
w
D
e
c
10
/
128KArray
•
••
0
128KArray
'--
10
/
16
I/O
Buffers
1 of 16
Selection
2.v
d
e
-
L±
~
In
Reg.
~
Out
Reg.
128KArray
z
DQ1-OQ4
'1
o
~
~
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Voltage range on any pin (see Note 1) .............................................. - 0.5 V to 4.6 V
Voltage range on Vee ............................................................ - 0.5 V to 4.6 V
Short circuit output current ................................................................ 50 mA
Power disSipation •......................................................................... 1 W
Operating free-air temperature range .................................................. O°C to 70°C
Storage temperature range ....................................................... - 55°C to 150°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. This is a stress rating only, and
functional operation olthe device at these or an~·other conditions beyond those indicated in the "recommended operating conditions" section of
this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values in this data sheet are with respect to VSS.
recommended operating conditions
MIN
NOM
MAX
Vee
Supply voltage
3.0
3.3
3.6
V
VIH
High-level input voltage
2.0
Vee+ 0.3
V
VIL
LOW-level input voltage (see Note 2)
-0.3
0.8
V
TA
Operating free-air temperature
0
70
'e
UNIT
NOTE 2: The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used in this data sheet for logic
voltage levels only.
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443· HOUSTON, TEXAS 77001
4-75
a::
o
u..
z
w
o
z
~
c
1000 ms
200
200
200
!lA
ICC10t
Battery backup
(withCBR)
tRC = 125 ~s, tRAS s 1 ~s,
VCC - 0.2 V s VIH s 3.9 V,
o V "VIL s 0.2 V,
IN and OE = VIH,
Add ress and Data stable
300
300
300
!lA
lJ
3:
2.4
After 1 memory cycle,
RAS and CAS high,
VIH = 2 V (LVTTL)
»
c
~
z
o
m
z"o
MAX
TMS46400·S0
TMS46400P·SO
t For TMS46400P only.
NOTES: 3. Measured with a maximum of one address change while RAS = VIL.
4. Measured with a maximum of one address change while CAS = VIH.
capacitance over recommended ranges of supply voltage and operating free-air temperature,
f = 1 MHz (see Note 5)
PARAMETER
MIN
TYP
MAX
UNIT
Ci(A)
Input capacitance, address inputs
5
pF
Ci(RC)
Input capacitance, strobe inputs
7
pF
Ci(W)
Input capacitance, write-enable input
7
pF
Co
Output capacitance
7
pF
NOTE 5: VCC equal to 3.3 V ± 0.3 V and the bias on pins under test is 0 V.
TEXAS . "
INSTRUMENTS
4-76
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
TMS46400, TMS46400P
1 048 576·WORD BY 4·BIT
LOW·VOLTAGE DYNAMIC RANDOM·ACCESS MEMORIES
SMHS464-JANUARY 1993
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature
TMS46400-70
TMS46400P-70
PARAMETER
MIN
MAX
TMS46400-80
TMS46400P-80
MIN
MAX
TMS46400-10
TMS46400P-l0
MIN
UNIT
MAX
tAA
Access time from column-address
35
40
45
ns
tCAC
Access time from CAS low
18
20
25
ns
ns
tCPA
Access time from column precharge
40
45
50
tRAC
Access time from RAS low
70
80
100
ns
tOEA
Access time from OE low
18
20
25
ns
leLZ
CAS to output in low Z
0
tOFF
Output disable time after CAS high (see Note 6)
0
18
0
20
0
25
ns
tOEZ
Output disable time after OE high (see Note 6)
0
18
0
20
0
25
ns
..
NOTE 6: tOFF and tOEZ are specified when the output
IS
0
0
ns
no longer dnven .
z
o
~
~
a:
oLL
Z
W
o
Z
~
c
«
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
4-77
TMS46400, TMS46400P
1 048 576·WORD BY 4·BIT
LOW·VOLTAGE DYNAMIC RANDOM·ACCESS MEMORIES
SMHS464-JANUARY 1993
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
TMS46400-70
TMS46400P-70
MIN
MAX
TMS46400-80
TMS46400P-80
MIN
MAX
TMS46400-10
TMS46400P-10
MIN
UNIT
MAX
tRC
Random read or write cycle (see Note 7)
130
150
180
ns
tRWC
Read-write cycle time
181
205
245
ns
tpc
Page-mode read or write cycle time (see Note 8)
45
50
55
ns
tPRWC
Page-mode read-write cycle time
96
105
120
ns
tRASP
Page-mode pulse duration, RAS low (see Note 9)
70
100000
80
100000
100
100000
ns
tRAS
Non-page-mode pulse duration, RAS low (see Note 9)
70
10000
80
10000
100
10 000
ns
tRASS
Self-refresh, RAS low time
tCAS
Pulse duration, CAS low (see Note 10)
100
18
10 000
100
20
10 000
25
100
I'S
10000
ns
tcp
Pulse duration, CAS high
10
10
10
ns
tRP
Pulse duration, RAS high (precharge)
50
60
70
ns
tRPS
RAS precharge after self-refresh
130
150
180
ns
twp
Write pulse duration
15
15
20
ns
~
z
o
tASC
Column-address setup time before CAS low
Row-address setup time before RAS low
a
a
tDS
Data setup time (see Note 11)
0
ns
tRCS
Read setup time before CAS low
a
a
a
a
ns
tASR
a
a
a
a
a
ns
-z
tCWL
W low setup time before CAS high
18
20
25
ns
tRWL
W low setup time before RAS high
18
20
25
ns
twcs
W low setup time before CAS low (Early write operation only)
a
a
a
ns
twSR
W high setup time (CAS-before-RAS refresh only)
10
10
10
ns
twTs
W low setup time (test mode only)
10
10
10
ns
leAH
Column-address hold time after CAS low
15
15
20
ns
tDHR
Data hold time after RAS low (see Note 12)
55
60
75
ns
»
c
m
"T1
o
::c
3:
-o~
z
ns
tDH
Data hold time (see Note 11)
15
15
20
ns
tAR
Column-address hold time after RAS low (see Note 12)
55
60
75
ns
tRAH
Row-address hold time after RAS low
10
10
15
ns
tRCH
Read hold time after CAS high (see Note 13)
a
a
0
ns
tRRH
Read hold time after RAS high (see Note 13)
0
0
0
ns
twCH
Write hold time after CAS low (Early write operation only)
15
15
20
ns
twCR
Write hold time after RAS low (see Note 12)
55
60
75
ns
twHR
W high hold time (CAS-before-RAS refresh only)
10
10
10
ns
twTH
W low hold time (test mode only)
10
10
10
ns
tAWD
Delay time, column address to W low
(Read-write operation only)
63
70
80
ns
tCHR
Delay time, RAS low to CAS high
(CAS-before-RAS refresh only)
15
20
20
ns
Continued next page.
NOTES: 7. All cycle times assume IT = 5 ns.
8. To assure tpc min, tASC should be greater than or equal to tcP.
9. In a read-write cycle, tRWD and tRWL must be observed.
10. In a read-write cycle, tCWD and tCWL must be o.bserved.
11. Referenced to the later of CAS or W in write operations.
12. The minimum value is measured when tRCD is set to tRCD min as a reference.
13. Either tRRH or tRCH must be satisfied for a read cycle.
TEXAS ~
INSTRUMENTS
4-78
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
TMS46400, TMS46400P
1 048 576-WORD BY 4-BIT
LOW-VOLTAGE DYNAMIC RANDOM-ACCESS MEMORIES
SMHS464-JANUARY 1993
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (concluded)
TMS46400-70
TMS46400P-70
MIN
MAX
TMS46400-80
TMS46400P-80
MIN
MAX
TMS46400-10
TMS46400P-l0
MIN
UNIT
MAX
tCRP
Delay time, CAS high to RAS low
0
0
0
ns
tCSH
Delay time, RAS low to CAS high
70
80
100
ns
tcSR
Delay time, CAS low to RAS low (CAS-before-RAS refresh only)
10
10
10
ns
tCHS
CAS low hold time after RAS high (self-refresh)
-50
-50
-50
ns
tCWD
Delay time, CAS low to W low (Read-write operation only)
46
50
60
ns
tOEH
OE command hold time
18
20
25
ns
tOED
OE to data delay
18
20
25
ns
tROH
RAS hold time referenced to OE
10
10
10
tRAD
Delay time, RAS low to column-address (see Note 14)
15
tRAl
Delay time, column-address to RAS high
35
40
45
tCAl
Delay time, column address to CAS high
35
40
45
tRCD
Delay time, RAS low to CAS low (see Note 14)
20
35
52
15
20
40
20
60
25
ns
50
ns
ns
ns
75
ns
tRPC
Delay time, RAS high to CAS low
0
0
0
ns
tRSH
Delay time, CAS low to RAS high
18
20
25
ns
tRWD
Delay time, RAS low to W low (Read-write operation only)
98
110
135
ns
iTAA
Access time from address (test mode)
40
45
50
ns
iTCPA
Access time from column precharge (test mode)
45
50
55
ns
iTRAC
Access time from RAS (test mode)
75
85
105
tREF
16
1'46400
Refresh time interval
I '46400P
Transition time
iT
NOTE 14: The maximum value is specified only to assure access time.
16
128
2
50
128
2
50
2
ns
16
ms
128
ms
50
ns
1.4V
Output Under Test
= 500
~
CL=l00pF
c
1
~
»
z
_~,-=
1
1
1
I..
I
I
RCSi
I
t
I
I
~"T'-l~~~~
I..
~
*-- tCAC ----.J
I..
::
ffiV'H
1
I
~ VIL
1
I
I~
..- - - - tCPA ---tl-.~I
I
VIL
tAA - - ' - - - . J
tRRH -.I
(see Note B)
~ tRCH - - . I
W
1~
..-+-I-tAA
tRAc
tCLZ
(see Note B)
~I. t O F F -
.1
.1
-I
I
I
.1
1
DQ1-DQ4.---------:---::-:-:--:-:--(XXXXXX' Valid I}----k
-0'1
I I
~tCSR~
"--
tCHS
><::.-
tWSR
VIL
I
~
- I I _ _ _ _ _ _ _ _ _ _ _ _ _ _ ~I
\l :::::;i==.rITI
r ~I l... ~I
~
VIH
i4- tT
~I I·
14
y - I I .VIH
~
....JI
VIL
tWHR
w~
VIH
VIL
AO-A9~&H*X~~VIH
VIL
oE~JniaR~V'H
VIL
O Q 1 - 0 Q 4 - - - - - - - - - - - - - - HI-Z - - - - - - - - - - - - - -
VIH
z
o
~
:E
a::
o
LL
Figure 11. Self Refresh Cycle Timing
Z
W
o
z
c~
«
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
4-89
TMS46400, TMS46400P
1 048 576·WORD BY 4·BIT
LOW·VOLTAGE DYNAMIC RANDOM·ACCESS MEMORIES
SMHS464-JANUARY 1993
PARAMETER MEASUREMENT INFORMATION
~ Memory Cycle
4
~ Refresh Cycle
I".I
I
I 14
.1 I tRAS
I I ·
RAS
~I I
11
I
I
I
I
I
tAR
tRAH
~
~
~
»
~
•
tRCS
14
I .1
:D
3:
/3--/ :::
~I I
y
i
I
I
I
tRP
I
tCAS
I
tCHR
I
(
)
I
~ tWHR
~ ~ tWSR
io4-
i
V
. I
-.!
~
I• I
I
~
~
I+- tWSR
_~
tAA
I"...:-tCAC
_;......._ _ _ _ _ _ _ _ _
Va_lId_D_a_ta_ _ _
-I~~
It
JJ
Figure 12. Hidden Refresh Cycle (Read) Timing
Z
TEXAS
~
INSTRUMENTS
4-90
r-
J:I
!I II
I
I
I
I
I
n
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
VIH
VIL
I
I
i
I
I
HR
I~
I".- tWSR
:::
I
~:::
-+j ~
tOFF
OE~
o
.1
}
~ ~"HR ~,
1041''--I·~1 tOEA
~
I I"
I I
I
I
I
I
I
-.I~'~I
----~.
tClZ
.1
----+t
I
I
~
tRFH
~
DQ1-DQ4
I
Refresh Cycle
:---+tCAH
tASC
w§W ~~tRA6~
Z
~I I
14
.lltRAS
I II I
!o4t't R' I I I
14
ti
II"
r
Io4rt
1"11041
AO-.,.
m
_
CS
I
I I
I r+I
tRP
--+i
I
~
.,
:::
TMS46400, TMS46400P
1 048 576-WORD BY 4-BIT
LOW-VOLTAGE DYNAMIC RANDOM-ACCESS MEMORIES
SMHS464-JANUARY 1993
PARAMETER MEASUREMENT INFORMATION
Figure 13. Hidden Refresh Cycle (Write) Timing
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
4-91
TMS46400, TMS46400P
1 048 576-WORD BY 4-BIT
LOW-VOLTAGE DYNAMIC RANDOM-ACCESS MEMORIES
SMHS464-JANUARY 1993
PARAMETER MEASUREMENT INFORMATION
»
c
~
z
o
m
-z
DQ1-DQ4 - - - - - - - - - - - - - - - HI-Z - - - - - - - - - - - - - - -
Figure 14. Test Mode Entry Cycle
-n
~
device symbolization
3:
-o~
J
z
TT-ss
TMS46400
W
Speed (-70, -80, -10)
Power/Refresh Designator (Blank or P)
~
B
P
Package Code
T¥
Lot Traceability Code
Month Code
Assembly Site Code
Die Revision Code
Wafer Fab Code
TEXAS
~
INSTRUMENTS
4-92
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
TMS44800, TMS44800P
524 288·WORD BY 8·BIT
DYNAMIC RANDOM·ACCESS MEMORIES
SMHS480B-AUGUST 1992-REVISED DECEMBER 1992
This data sheet is applicable to all
TMS44800/Ps symbolized with Revision"B"
and subsequent revisions as described on
page 22.
• Organization ... 524 288 x 8
• Single 5-V Power Supply (±10% Tolerance)
DZ AND DGC PACKAGESt
(TOP VIEW)
• Per10rmance Ranges:
'44800/P-60
'44800/P-70
'44800/P-80
'44800/P-l0
ACCESS ACCESS ACCESS READ
TIME
TIME
TIME OR WRITE
(tRAC) (tCAC)
(tAA)
CYCLE
(MAX)
(MAX)
(MAX)
(MIN)
15 ns
30 ns
lIOns
60 ns
70 ns
80 ns
100 ns
20 ns
20 ns
25 ns
35 ns
40 ns
45 ns
VCC
DOO
Vss
D07
DOl
D02
D03
D06
D05
D04
Iii
OE
RAS
NC
A8
A7
A9
AO
130 ns
150 ns
180 ns
AI
A2
• Enhanced Page Mode Operation With
CAS-Before-RAS Refresh
A3
VCC
• Long Refresh Period ...
1024-Cycle Refresh in 16 ms (Max)
128 ms for Low Power With Self-Refresh
Version (TMS44800P)
D04
CAS
A6
A5
A4
Vss
t The package shown is for pinout reference only.
PIN NOMENCLATURE
• 3-State Unlatched Output
AO-A9
CAS
DOO-D07
NC
OE
RAS
• Low Power Dissipation
• Texas Instruments EPIC ™ CMOS Process
• All Inputs/Outputs and Clocks are TTL
Compatible
• High-Reliability Plastic 28-Lead
400-Mil-Wide Sur1ace Mount (SOJ)
Package, and 28-Lead Thin Small Outline
Package (TSOP)
W
VCC
VSS
Address Inputs
Column-Address Strobe
Data In/Data Out
No Internal Connection
Output Enable
Row-Address Strobe
Write Enable
5-V Supply
Ground
• Operating Free-Air Temperature Range
O°C to 70°C
• Low-Power With Self-Refresh Version
description
The TMS44800 series are high-speed 4 194 304-bit dynamic random-access memories, organized as 524288
words of eight bits each.
The TMS44800P series are high-speed, low-power with self-refresh, 4 194 304-bit dynamic random-access
memories, organized as 524 288 words of eight bits each.
They employ state-of-the-art EPIC'· (Enhanced Performance Implanted CMOS) technology for high
performance, reliability, and low power at a low cost.
These devices feature maximum RAS access times of 60 ns, 70 ns, 80 ns, and 100 ns. Maximum power
dissipation is as low as 495 mW operating and 11 mW standby on 1OO-ns devices.
All inputs and outputs, including clocks, are compatible with Series 74 TTL. All addresses and data-in lines are
latched on-chip to simplify system design. Data out is unlatched to allow greater system flexibility.
EPIC is a trademark of Texas Instruments Incorporated.
~~~~~~~:~1: .~::'::."pt~~~:~~~ ~f !.~:!I~~~~m~~~
standard warranty. Production proceuln; doe. not nece... rtlv Include
tilting of III paramlt,rs.
TEXAS
~
Copyright © 1992. Texas Instruments Incorporated
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
4-93
TMS44800, TMS44800P
524 288·WORD BY 8·BIT
DYNAMIC RANDOM·ACCESS MEMORIES
SMHS480B-AUGUST 1992-REVISED DECEMBER 1992
The TMS44800 and TMS44800P series are offered in a 400-mil 28-lead plastic surface mount SOJ package
(DZ suffix) and a 28-lead plastic surface mount TSOP package (DGC suffix). These packages are characterized
for operation from O°C to 70°C.
operation
enhanced page mode
Enhanced page-mode operation allows faster memory access by keeping the same row address while selecting
random column addresses. The time for row-address setup and hold and address multiplex is thus eliminated.
The maximum number of columns that may be accessed is determined by the maximum RAS low time and the
CAS page cycle time used. With minimum CAS page cycle time, all512 columns specified by column addresses
AO through A8 can be accessed without intervening RAS cycles.
Unlike conventional page-mode DRAMs, the column-address buffers in this device are activated on the falling
edge of RAS. The buffers act as transparent or flow-through latches while CAS is high. The falling edge of CAS
latches the column addresses. This feature allows the TMS44800 and TMS44800P to operate at a higher data
bandwidth than conventional page-mode parts, since data retrieval begins as soon as the column address is
valid rather than when CAS transitions low. This performance improvement is referred to as enhanced page
mode. Valid column address may be presented immediately after row address hold time has been satisfied,
usually well in advance of the falling edge of CAS. In this case, data is obtained after tCAC max (access time
from CAS low), if tAA max (access time from column address) has been satisfied. In the event that column
addresses for the next cycle are valid at the time CAS goes high, access time for the next cycle is determined
by the later occurrence of tCAC or tCPA (access time from rising edge of CAS).
address (AO-A9)
Nineteen address bits are required to decode 1 of 524288 storage cell locations. Ten row-address bits are set
up on inputs AO through A9 and latched onto the chip by the row-address strobe (RAS). The nine
column-address bits are set up on pins AO through A8 and latched onto the chip by the column-address strobe
(CAS). All addresses must be stable on or before the falling edges of RAS and CAS. RAS is similar to a chip
enable in that it activates the sense amplifiers as well as the row decoder. CAS is used as a chip select activating
the output buffer, as well as latching the address bits into the column-address buffer.
write enable
cW>
The read or write mode is selected through the write-enable (W) input. A logic high on the Vii input selects the
read mode and a logic low selects the write mode. The write-enable terminal can be driven from standard TTL
circuits without a pullup resistor. The data input is disabled when the read mode is selected. When Vii goes low
prior to CAS (early write), data out will remain in the high-impedance state for the entire cycle permitting a write
operation independent of the state of OE. This permits early write operation to be completed with OE grounded.
data in/out (OQO-OQ7)
The three-state output buffer provides direct TTL compatibility (no pullup resistor required) with a fanout of two
Series 74 TTL loads. Data out is the same polarity as data in. The output is in the high-impedance (floating) state
until CAS and OE are brought low. In a read cycle the output becomes valid after all access times are satisfied.
The output remains valid while CAS and OE are low. CAS or OE going high returns it to a high-impedance state.
output enable (OE)
OE controls the impedance of the output buffers. When OE is high, the buffers will remain in the high-impedance
state. Bringing OE low during a normal cycle will activate the output buffers putting them in the low-impedance
state. It is necessary for both RAS and CAS to be brought lowforthe output buffers to go into the low-impedance
state. They will remain in the low-impedance state until either OE or CAS is brought high.
TEXAS ~
INSTRUMENTS
4-94
POST OFFICE BOX 1443· HOUSTON. TEXAS 77001
TMS44800, TMS44800P
524 288-WORD BY 8-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS4BOB-AUGUST 1992-REVISED DECEMBER 1992
refresh
A refresh operation must be performed at least once every 16 ms (128 ms for TMS44800P) to retain data. This
can be achieved by strobing each of the1 024 rows (AO-A9). A normal read or write cycle will refresh all bits in
each row that is selected. A RAS-only operation can be used by holding CAS at the high (inactive) level, thus
conserving power as the output buffer remains in the high-impedance state. Externally generated addresses
must be used for a RAS-only refresh.
hidden refresh
Hidden refresh may be performed while maintaining valid data at the output pin. This is accomplished by holding
CAS at VIL after a read operation and cycling RAS after a specified precharge period, similar to a RAS-only
refresh cycle.
CAS-before-RAS refresh
CAS-before-RAS (CBR) refresh is utilized by bringing CAS low earlier than RAS (see parameter tCSR) and
holding it low after RAS falls (see parameter tCHR)' For successive CAS-before-RAS refresh cycles, CAS
can remain low while cycling RAS. The external address is ignored and the refresh address is generated
internally.
A low-power battery-backup refresh mode that requires less than 300 ~ refresh current is available on the
TMS44800P. Data integrity is maintained using CAS-before-RAS refresh with a period of 125 ~s holding RAS
low for less than 1 ~s. To minimize current consumption, all input levels must be at CMOS levels (VIL S 0.2 V,
VIH" VCC - 0.2 V).
self refresh (TMS44800P)
The self refresh mode is entered by dropping CAS low prior to RAS going low. Then CAS and RAS are both held
low for a minimum of 100 ~s. The chip is then refreshed by an on-board oscillator. No external address is required
since the CBR counter is used to keep track of the address. To exit the self refresh mode, both RAS and CAS
are brought high to satisfy tCHS'
power up
To achieve proper device operation, an initial pause of 200
required after power-up to the full VCC level.
~s
followed by a minimum of eight RAS cycles is
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
4-95
TMS44800, TMS44800P
524 288·WORD BY 8·BIT
DYNAMIC RANDOM·ACCESS MEMORIES
SMHS480B-AUGUST 1992-REVISED DECEMBER 1992
logic symbol t
RAM512Kx8
AO 10
A1 11
2009/2100 "-
A2 12
A3 13
A4 16
A5 17
0
A 524287
A6 18
A7 19
A8 20
A9 9
8
23
w
20017/2108
20018
~
> C20[ROW]
f
>
22
OQO
G23/[REFRESH ROW]
24[PWROWN]
C21[COL]
G24
&
1
7
.-
23,210
>
23C22
24,25EN
r--. G25
-i
2
4-
OQ1 3
OQ2 4
OQ3 5
OQ4 24
r.
A,220
V26
..
OQ5 25
OQ6 26
OQ7 27
t This symbol is in accordance with ANSI/IEEE Std 91-19B4 and lEe Publication 617-12.
lExAs .. "
INSTRUMENTS
4-96
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
A,Z26-
TMS44800, TMS44800P
524 288·WORD BY 8·BIT
DYNAMIC RANDOM·ACCESS MEMORIES
SMHS480B-AUGUST1992-REVISED DECEMBER 1992
functional block diagram
w
I
T
AO
A1
·•
•
A8
Timing and Control
16
8
/
Column Decode
Column
Address
Buffers
128KArray
128KArray
16 <
Row
Address
Buffers
~
1
Sense Amplifiers
L
•
•
•
+ + + +
•
••
128K Array
..
"..
0
u
0
-±
128K Array
•
••
:> 16
~
In
Reg.
161/0
Buffers
~
Out
Reg.
~
0
10
a:
/
-
128K Array
'---
A9
10
/
128K Array
DOO-DO?
I
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage range on any pin (see Note 1) .......................................... - 1 V to 7 V
Supply voltage range on Vee ......................................................... - 1 V to 7 V
Short circuit output current ................................................................ 50 mA
Power dissipation .......................................................................... 1 W
to 70°C
Operating free-air temperature range ..................................................
Storage temperature range ....................................................... - 55°C to 150°C
ooe
t Stresses beyond those' listed under "absolute maximum ratings" may cause permanent damage to the device. This is a stress rating only, and
functional operation of the device at these or any other conditions beyond those indicated in the "recommended operating conditions" section
of this specification is not implied. Exposure to absolute-maxi mum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values in this data sheet are with respect to VSS.
recommended operating conditions
MIN
NOM
MAX
Vee
Supply voltage
4.5
5
5.5
V
VIH
High-level input voltage
2.4
6.5
V
VIL
Low-level input voltage (see Note 2)
-1
0.8
V
0
70
°e
TA
Operating free-air temperature
UNIT
NOTE 2: The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used in this data sheet for logic
voltage levels only.
TEXAS ~
INsrRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
4-97
TMS44800, TMS44800P
524 288·WORD BY 8·BIT
DYNAMIC RANDOM·ACCESS MEMORIES
SMHS480B-AUGUST1992-REVISED DECEMBER 1992
electrical characteristics over full ranges of recommended operating conditions (unless otherwise
noted)
'44800-60
'44800P-60
TEST CONDITIONS
PARAMETER
'44800-70
'44800P-70
MIN ' MAX
VOH
High-level output
voltage
10H =-5mA
VOL
Low-level output
voltage
IOL=4,2 mA
II
Input current
(leakage)
10
ICClt
2A
MAX
2A
MIN
'44800-10
'44800P-10
MAX
2A
MIN
UNIT
MAX
2A
V
OA
OA
OA
OA
V
VCC = 5.5 V, VI = 0 to 6.5 V,
All other pins = 0 to V CC
±10
±10
±10
± 10
Il A
Output current
(leakage)
VCC = 5.5 V, Vo = 0 to VCC,
CAS high
±10
±10
±
10
±10
IlA
Read or write
cycle current
(see Note 3)
VCC = 5.5 V, Minimum cycle
120
110
100
90
mA
2
2
2
2
mA
1
1
1
1
mA
200
200
200
200
I1A
VIH = 2A V (TTL),
After 1 memory cycle,
RAS and CAS high
ICC2
MIN
'44800-80
'44800P-80
Standby current
VIH = VCC - 0.2 V
(CMOS), After 1
memory cycle, RAS
and CAS high
'44800
'44800P
ICC3
Average refresh
current (RAS-only
orCBR)
(see Note 3)
VCC = 5.5 V, Minimum cycle,
RAS cycling, CAS high
(RAS-only); RAS low
after CAS low (CBR)
120
110
100
90
mA
ICC4t
Average page
current
(see Note 4)
VCC = 5.5 V, tpc = minimum,
RAS low, CAS cycling
120
110
100
90
mA
ICC5*
Battery backup
operating current
(equivalent refresh
time is 128 ms),
CBR only
tRC = 125 I1S, tRAS " 1 I1s,
VCC - 0.2 V" VIH ,,6.5 V,
V" VIL" 0.2 V,
Wand OE = VIH,
Address and Data stable
o
300
300
300
300
I1A
ICC6t:1:
Self refresh
current
CAS" 0.2 V, RAS < 0.2 V,
Measured after tRASS minimum
200
200
200
200
IlA
t Measured with outputs open.
* For TMS44800P only.
NOTES: 3. Measured with a maximum of one address change while RAS = VIL.
4. Measured with a maximum of one address change while CAS = VIH.
TEXAS ~
INSTRUMENTS
4-98
POST OFFICE BOX 1443· HOUSTON. TEXAS 77001
TMS44800, TMS44800P
524 288·WORD BY 8·BIT
DYNAMIC RANDOM·ACCESS MEMORIES
SMHS480B-AUGUST 1992-REVISED DECEMBER 1992
capacitance over recommended ranges of supply voltage and operating free-air temperature,
f = 1 MHz (see Note 5)
PARAMETER
MIN
TYP
MAX
UNIT
Ci(A)
Input capacitance, address inputs
5
pF
Ci(OE)
Input capacitance, output enable
7
pF
Ci(RC)
Input capacitance, strobe inputs
7
pF
Ci(W)
Input capacitance, write-enable input
7
pF
Co
Output capacitance
7
pF
NOTE 5: VCC equal to 5 V ± 0.5 V and the bias on PinS under test IS 0 V.
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature
'44800-60
'44800P-80
PARAMETER
MIN
'44800-70
'44800P-70
MAX
MIN
'44800-80
'44800P-80
MAX
MIN
'44800-10
'44800P-10
MAX
MIN
UNIT
MAX
tAA
Access time from column-address
30
35
40
45
ns
tCAC
Access time from CAS low
15
20
20
25
ns
tCPA
Access time from column precharge
35
40
45
50
ns
tRAC
Access time from RAS low
60
70
80
100
ns
tOEA
Access time from OE low
15
20
20
25
ns
tCLZ
CAS to output in low Z
0
tOFF
Output disable time after CAS high (see Note 6)
0
15
0
20
0
20
0
25
ns
tOEZ
Output disable time after OE high (see Note 6)
0
15
0
20
0
20
0
25
ns
..
0
0
0
ns
NOTE 6: tOFF and tOEZ are specified when the output IS no longer dnven.
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
4-99
TMS44800, TMS44800P
524 288-WORD BY 8-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS480B-AUGUST1992-REVISED DECEMBER 1992
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
'44800-60
'44800P-60
MIN
MAX
'44800-70
'44800P-70
MIN
MAX
'44800-80
'44800P-80
MIN
MAX
'44800-10
'44800P-10
MIN
UNIT
MAX
tRC
Random read or write cycle (see Note 7)
110
130
150
180
ns
tRWC
Read-modify-write cycle time
155
185
205
245
ns
tpc
Page-mode read or write cycle time
(see Note 8)
40
45
50
55
ns
tpRWC
Page-mode read-modify-write cycle time
85
90
105
120
ns
tRASP
Page-mode pulse duration, RAS low
(see Note 9)
60
100000
70
100000
80
100000
100
100000
ns
tRAS
Non-page-mode pulse duration, RAS low
(see Note 9)
60
10000
70
10000
80
10000
100
10000
ns
tCAS
Pulse duration, CAS low (see Note 10)
15
10000
20
10000
20
10000
25
10000
ns
tcp
Pulse duration, CAS high
10
10
10
10
ns
tRP
Pulse duration, RAS high (precharge)
40
50
60
70
ns
twp
Write pulse duration
15
15
15
20
ns
tASC
Column-address setup time before CAS low
0
0
0
0
ns
tASR
Row-address setup time before RAS low
0
0
0
0
ns
tDS
Data setup time (see Note 11)
0
0
0
0
ns
tRCS
Read setup time before CAS low
0
0
0
0
ns
tCWL
W low setup time before CAS high
15
20
20
25
ns
tRWL
W low setup time before RAS high
15
20
20
25
ns
twcs
W low setup time before CAS low (Early
write operation only)
0
0
0
0
ns
Continued next page.
NOTES: 7. All cycle times assume tT ; 5 ns.
8. To assure tpc min, tASC should be greater than or equal to tcp.
9. In a read-modify-write cycle, tRWD and tRWL must be observed. Depending on the user'stransition times, this may require additional
RAS low time (tRAS).
10. In a read-modify-write cycle, tCWD and tCWL must be observed. Depending on the user's transition times. this may require additional
CAS low time (tCAS).
11. Referenced to the later of CAS or Vii in write operations.
TEXAS •
INsrRUMENTS
4-100
POST OFFICE BOX 1443' HOUSTON. TEXAS 77001
TMS44800, TMS44800P
524 288-WORD BY 8-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS480B-AUGUST1992-REVISED DECEMBER 1992
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (continued)
'44800-60
'44800P-60
MIN
'44800·70
'44800P·70
MAX
MIN
MAX
'44800·80
'44800P·80
MIN
MAX
'44800·10
'44800P·10
MIN
UNIT
MAX
tCAH
Column·address hold time after CAS low
10
15
15
20
ns
tDHR
Data hold time after RAS low (see Note 12)
30
35
35
45
ns
tDH
Data hold time (see Note 11)
10
15
15
20
ns
tAR
Column-address hold time after RAS low
(see Note 12)
30
35
35
45
ns
tRAH
Row-address hold time after RAS low
10
10
10
15
ns
tRCH
Read hold time after CAS high (see Note 13)
0
0
0
0
ns
tRRH
Read hold time after RAS high (see Note 13)
0
0
0
0
ns
twCH
Write hold time after CAS low
(Early write operation only)
10
15
15
20
ns
twCR
Write hold time after RAS low (see Note 12)
30
35
35
45
ns
tAWD
Delay time, column address to W low
(Read-modify-write operation only)
55
65
70
80
ns
tCHR
Delay time, RAS low to CAS high
(CAS-before-RAS refresh only)
15
15
20
20
ns
tCRP
Delay time, CAS high to RAS low
0
0
0
0
ns
tCSH
Delay time, RAS low to CAS high
60
70
80
100
ns
tCSR
Delay time, CAS low to RAS low
(CAS-before-RAS refresh only)
10
10
10
10
ns
tCWD
Delay time, CAS low to W low
(Read-modify-write operation only)
40
50
50
60
ns
tOEH
OE command hold time
15
20
20
25
ns
tOED
OE to data delay
15
20
20
25
ns
tROH
RAS hold time referenced to OE
10
10
10
10
ns
tRAD
Delay time, RAS low to column-address
(see Note 14)
15
tRAl
Delay time, column-address to RAS high
30
tCAl
Delay time, column address to CAS high
30
tRCD
Delay time, RAS low to CAS low (see Note 14)
20
tRPC
Delay time, RAS high to CAS low
0
0
0
0
ns
tRSH
Delay time, CAS low to RAS high
15
20
20
25
ns
tRWD
Delay time, RAS low to W low
(Read-modify-write operation only)
85
100
110
135
ns
NOTES: 11.
12.
13.
14.
30
15
35
15
40
20
35
40
45
35
40
45
45
20
50
20
60
25
50
ns
ns
ns
75
ns
Referenced to the later of CAS or W in write operations.
The minimum value is measured when tRCD is set to tRCD min as a reference.
Either tRRH or TRCH must be satisfied for a read cycle,
The maximum value is specified only to assure access time.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
4-101
TMS44800, TMS44800P
524 288·WORD BY 8·BIT
DYNAMIC RANDOM·ACCESS MEMORIES
SMHS480B-AUGUST 1992-REVISED DECEMBER 1992
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (concluded)
'44BOO-60
'44BOOP-60
MIN
'44BOO-70
'44BOOP-70
MAX
MIN
MAX
'44BOO-80
'44BOOP-BO
MIN
'44BOO-l0
'44800P-l0
MAX
MIN
UNIT
MAX
tCPR
CAS precharge before self refresh
0
0
0
0
tRAS
RAS precharge after self refresh
110
130
150
lBO
ns
tRASS
Self refresh entry from RAS low
100
100
100
100
I'S
tCHS
CAS low hold time after RAS high
tREF
Refresh time interval (TMS44BOO only)
-50
-50
16
tREF
Refresh time interval, Low power (TMS44800P only)
IT
Transition time
128
2
-50
16
2
-50
ns
16
ms
128
ms
50
ns
16
128
50
ns
128
50
2
50
2
PARAMETER MEASUREMENT INFORMATION
vcc =5V
1.31 V
Output Under Test -_1"----1
Output Under Test
CL = 100 pF
CL=100pF
T
(a) Load Circuit
T
(b) Alternate Load Circuit
Figure 1. Load Circuits for Timing Parameters
TEXAS
~
INBrRUMENTS
4-102
R2 = 295
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
Q
TMS44800, TMS44800P
524 288-WORD BY 8-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS480B-AUGUST 1992-REVISED DECEMBER 1992
PARAMETER MEASUREMENT INFORMATION
I"
IRC
-----.iN
11
1
RAS
IRAS
-':~tr
r
I
1
I
:
ICSH
I 14
I *--IRCD~
1 :
I..
1 I
I
1
1
IASR
I..
1
--.I
I
r
11
"I
1
~\...
II
I
I 14---- IRP ~
I:
:
!
I
I ~ ICRP ----.r
"I
I
IRSH
----+----.J
~~ICAS---{.;;" I :
:X
(: I I
"I IRAD I !
1 ,..1r-rl-:-I_r-..t IASC
I I" I I
ICp
t
I
RAi..
I
I"
I
_______
i\
1
\.....- - -
..I
1I11
ICAl
"I I I I
1.. 1 I
AO-A9
NOTE A: Output may go from a high-impedance state to an invalid data state prior to the specified access time.
Figure 2_ Read Cycle Timing
TEXAS ~
INsrRUMENTS
POST OFFICE BOX 1443· HOUSTON, TEXAS 77001
4-103
TMS44800, TMS44800P
524 288·WORD BY 8·BIT
DYNAMIC RANDOM·ACCESS MEMORIES
SMHS480B-AUGUST 1992-REVISED DECEMBER 1992
PARAMETER MEASUREMENT INFORMATION
Figure 3. Early Write Cycle Timing
TEXAS ."
INSTRUMENTS
4-104
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
TMS44800, TMS44800P
524 288-WORD BY 8-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS480B-AUGUST 1992-REVISED DECEMBER 1992
PARAMETER MEASUREMENT INFORMATION
NOTE A: Referenced to the later of CAS or W in write operations.
Figure 4. Write Cycle Timing
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
4-105
TMS44800, TMS44800P
524 288·WORD BY 8·BIT
DYNAMIC RANDOM·ACCESS MEMORIES
SMHS480B-AUGUST 1992-REVISED DECEMBER 1992
PARAMETER MEASUREMENT INFORMATION
CAS
-.I
I
I
I
I
AO-A9~
D Q O - D Q 7 - - - - + - - - - - - - - - - < P < XX
I
(see Note A)
f - - - - - tRAC ----~.I
I
j+- tOEA -.I
1.
ooI
.
1
I
OE~H~~i~
Data
Out
*"
I
tOEZ
I
I
I
~ tOEH
tOED--r~===~·_1_ _ _ _~I~~~~~~~~~~
-+i
I
~H2~im
I
NOTE A: Output may go from a high-impedance state to an invalid data state prior to the specified access time.
Figure 5_ Read-Modify-Write Cycle Timing
1ExAs
~
INsrRUMENTS
4-106
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
TMS44800, TMS44800P
524 288-WORD BY 8-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS480B-AUGUST1992-REVISED DECEMBER 1992
PARAMETER MEASUREMENT INFORMATION
Column
AO-A9
I
t-
+
-W'i:£££i/
XXf.YX!/ 14I
I
tRAD ~
I
I
I
I~
I I~
tAR
tRCS
I
I
I~
I
wn
W
:1
~ tCAC
tCLZt~C
:1
tRRH -+I
tRCH ~
w~
I
114~----- tCPA ----tl-~~I
I
I
tAA -----'-I-~~I
(see Note A)
tAA
-+I
(see Note B)
~I
~I
DQO-DQ7---------------------------4~>(X:~XX
(see Note A)
I
I
I.--l-I tOFF ~
I
I
Valid
Out
tOEZ
I~
I
~I
~
NOTES: A. Output may go from a high-impedance state to an invalid data state prior to the specified access time.
B. Access time is tCPA or tAA dependent.
C. A write cycle or read-modify-write cycle can be mixed with the read cycles as long as the write and read-modify-write timing
specifications are not violated.
Figure 6. Enhanced Page-Mode Read Cycle Timing
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
4-107
TMS44800, TMS44800P
524 288-WORD BY 8-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS480B-AUGUST 1992-REVISED DECEMBER 1992
PARAMETER MEASUREMENT INFORMATION
'N'
!
II
I
I
I
I
foil
IRP
"'AS'
I~
•
.1
~I~
I
I
.1 I,.
IpC
I I
~ ICRP --.J
_I I
- - IRSH -!----.II
I~ IRCD - - . Ifoil- ICAS ~
1I
I
. ~:
I
I
;:--1""1----I
IASC~\.
I
I
I I
I
I
I
I
.. IRAH ....I I
I I
I I
1_
I
I I
I ~ ICp ----.I
:
ICSH
0N
: :..
~-j."I-1
I
,IAR I
I
1·1
I..
I ~ ICAH --1+11
I I
IASR
/
IRAL
.1
I
I
I..--ICAL
~"""""V'V"::'?'V'V~
AO-A9
~ IRAD
I"
I
I,.
~ ICWL ~
-+J
tWCR
I I
:.. 1 I
--t IOHR
.1
.1
I
tCWL
~
I
twp
I
~tRWL~
.1
I
w~~S~aZ{~ i ~~~~~ ~*fj~2£~
:I~~I
: -.I
I"
1.1
1
~ tOEH
tDS
1
DQO-DQ7~
(see Note A)
1
I
~
Valid Data In
I
~ tOEH -.I
OE
(see Note B)
tOED ~
~*g.RaX{r
I
~
I
V~~ld ~~~~~~o<:"l~~X~~~~~~',-:2S~
~
I
~i0kZ2
NOTES: A. Referenced to CAS or VIi, whichever occurs last.
B. A read cycle or a read-modify-write cycle can be intermixed with the write cycles as long as the read and read-modify-write timing
specifications are not violated.
Figure 7. Enhanced Page-Mode Write Cycle Timing
TEXAS .".
INSTRUMENTS
4-108
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
TMS44800, TMS44800P
524 288·WORD BY 8·BIT
DYNAMIC RANDOM·ACCESS MEMORIES
SMHS480B-AUGUST 1992-REVISED DECEMBER 1992
PARAMETER MEASUREMENT INFORMATION
tRP~
RAS ~
tRASP
I I
I"
I :
I"
r:IV---
I I"
CAS
:
-+j
I
I
.1
tCSH
:
I
tpRWC
tRCD
:
tCAS
I:
:1 I
-i'II--.~
.r-~
.1
1"111
. .
-
~
~
~ tASR I I
I
-.r~tASC
'X
-
-
-
tRSH
I
I
-t-C-R-P--I:~:
~
tcp
I
I
;;..+:---
I
I
I
tAR~
tCAH ~
r+-
------------~
I
I
I
I
I
I
Column
AG-A9
I
II
II
r--
I.
rr---
tCWD
I
I
-.r
tAWD --+j I..
~I twp
II ,tRWD~ I
II
III
I
I
I
I
_
Will:
1i02W
III
I :,-.--_I-"""""'~
I I
I
tCPA ---.I
I
I"
N
I
I
-.r Ir.+
I.. I
.1
r.-- tRAC ~
tCAC
(see Note A)
r.-
I ~ tDH ~
tRCS
tAA
~
I I
:.+-
I
IDS
I
I
I
I
I (see Note B) I
Valid Out
(see Note A)
DQG-DQ7--------------~~
I
--.I
I.-i
tCLZ
I
[4-- tOEA ~ I
I
tOEZ -.j 14-
OE~
I
r.-
+l
II"II"-~- tOED
I
I
I
I
I
I~------~~;.--.------~~~~~~
tOEH
NOTES: A. Output may go from a high-impedance state to an invalid data state prior to the specified access time.
B. A read or write cycle can be intermixed with read-modify-write cycles as long as the read and write timing specifications are not
violated.
Figure 8. Enhanced Page-Mode Read-Modify-Write Cycle Timing
TEXAS ~
INsrRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
4-109
TMS44800, TMS44800P
524 288·WORD BY 8·BIT
DYNAMIC RANDOM·ACCESS MEMORIES
SMHS480B-AUGUST 1992-REVISED DECEMBER 1992
PARAMETER MEASUREMENT INFORMATION
DQO-DQ7 - - - - - - - - - - - - - - HI-Z - - - - - - - - - -_ _ __
Figure 9. RAS-Only Refresh Timing
TEXAS ~
INSTRUMENTS
4-110
POST OFFICE BOX 1443· HOUSTON, TEXAS 77001
TMS44800, TMS44800P
524 288·WORD BY 8·BIT
DYNAMIC RANDOM·ACCESS MEMORIES
SMHS480B-AUGUST 1992-REVISED DECEMBER 1992
PARAMETER MEASUREMENT INFORMATION
~1~--------------------tRC--------------------~~1
~ tRP ~ ~1~-------------tRAS ------------~~I I
I
I Iit:-_ _ __
ANY
RAS
I
tRPC
CAS
I I
--+I
~tCSR -.:
~
\i
I
I "'i~I------- tCHR --------~~I
Y
~~tT
w
A~A9~~*H*~~
OE~R*2RXX~
DQ~DQ7----------------HI-Z - - - - - - - - - - - - - - -
Figure 10. Automatic (CAS-Before-RAS) Refresh Cycle Timing
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
4·111
TMS44800, TMS44800P
524 288·WORD BY 8·BIT
DYNAMIC RANDOM·ACCESS MEMORIES
SMHS480B-AUGUST 1992-REVISED DECEMBER 1992
PARAMETER MEASUREMENT INFORMATION
!4-- Refresh Cycle ~I
!+-- Memory Cycle ~
1
l
~I
1 1_
1
I
tRAS
RASN1 1
1
J..
\i
y
i\lI~I
1
I:"
1
~
1 1
tRP
l<1li- tRP
1 J+ tRAS -.: 1
1
~r
:!
!4-- Refresh Cycle
~I
I'"
1
1
1
~
Y
1
/~
\
tCHR
tAR
1
1
1
:
1 1
1
1
~III
wili
1
~
1
~ ~tCAC
: :
11"1.ltAA
1_
~~~
OQG-OQ7
OE
~~l-
-----~
tCLZ
Valid Data Out
---.I i C20[ROW)
~
..--.D G23/[REFRESH ROW]
RAS
~1> -
24[PWROWN)
---'-'"
&
~
»
C
+
G29
..--.D Z31
..--.D I> C21 [COL)
..--.D G24
~
Z
CAS
0
m
LW
28
12
-z
."
0
UW
J]
s:
OE
-0~
13
27
.1'-
r
001 3
002 4
Z
003 5
004 7
005 8
9
006
10
007
31
008
009
0010
0011
0012
0013
0014
0015
32
23C22
23,210
r
+
31 &
23,210
.,
29,25EN26
23C32
+
29,25EN27 .
"- G25
2
000
&
r
4-
A,220
V26
A, Z26
4-
A,320
V27
A,Z27
33
34
36
37
38
39
t This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown correspond to the DZ package.
TEXAS ~
INsrRUMENTS
4-118
POST OFFICE BOX 1443· HOUSTON, TEXAS 77001
t-
TMS44165, TMS44165P
262144·WORD BY 16·BIT HIGH·SPEED
DYNAMIC RANDOM·ACCESS MEMORIES
SMHS166A-5EPTEMBER 1991-REVISED DECEMBER 1992
functional block diagram
,
AO
Timing and Control
1
16
9
/
A1
•
•
A8
•• • ••
I
•
Column
Address
Buffers
r-
·•
128KArray
R
128KArray
•
••
16
Row
Address
Buffers
W
Sense Amplifiers
128KArray
L
•
Column Decode
0
~
128KArray
•
••
w
0
;>16
~
In
Reg.
161/0
Buffers
~
Data
Out
Reg.
e
c
!J
/
0
d
e
-
9
I
z
128KArray
128KArray
'---
DOD-0015
""I
o-
~
absolute maximum ratings over operating free-air temperature range (unless otherwise noted}t
Supply voltage range on any pin (see Note 1) .......................................... - 1 V to 7 V
Supply voltage range on Vee ......................................................... - 1 V to 7 V
Short circuit output current ................................................................ 50 mA
Power dissipation .......................................................................... 1 W
Operating free-air temperature range .................................................. ooe to 70°C
Storage temperature range ....................................................... - 55°C to 150°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. This is a stress rating only, and
functional operation of the device at these or any other conditions beyond those indicated in the "recommended operating conditions" section of
this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values in this data sheet are with respect to VSS.
:e
a::
ou..
z
w
(.)
z
~
c
«
recommended operating conditions
MIN
NOM
MAX
4.5
5
5.5
UNIT
Vee
Supply voltage
VSS
Supply voltage
VIH
High-level input voltage
2.4
6.5
V
VIL
Low-level input vo~age (see Note 2)
-1
0.8
V
70
°e
a
Operating free-air temperature
TA
..
..
. .
NOTE 2: The algebraiC convenllOn, where the more negative (less pOSItive) limit IS designated as minimUm,
logic voltage levels only.
TEXAS
a
IS
used
In
V
V
this data sheet for
~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
4-119
TMS44165, TMS44165P
262144·WORD BY 16·BIT HIGH·SPEED
DYNAMIC RANDOM·ACCESS MEMORIES
SMHS166A--5EPTEMBER 1991-REVISED DECEMBER 1992
electrical characteristics over full ranges of recommended operating conditions (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
'44165-70
'44165P-70
MIN
VOH
High-level output voltage
10H --5mA
VOL
Low-level output voltage
IOL=4.2mA
II
Input current (leakage)
10
ICClt
ICC2
»
c
~
z
o
m
-z
o
"
:II
3:
~
o
z
'44165-80
'44165P-S0
MAX
2.4
MIN
'44165-10
'44165P-l0
MAX
2.4
MIN
UNIT
MAX
2.4
V
0.4
0.4
0.4
V
VCC = 5.5 V, VI = 0 to 6.5 V,
All other pins = 0 V to VCC
±10
±10
±10
i!A
Output current (leakage)
VCC = 5.5 V,
Vo = 0 to VCC, CAS high
±10
±10
±10
i!A
Read or write cycle current
(see Note 3)
VCC = 5.5 V, Minimum cycle
120
105
95
rnA
2
2
2
rnA
1
1
1
rnA
Standby current
VIH = 2.4 V (TTL)
After 1 memory cycle,
RAS and CAS high
VIH = VCC-0.2V (CMOS) 1'44165
After 1 memory cycle,
RAS and CAS high
'44165P
I
200
200
200
Il A
120
105
95
rnA
ICC3
Average refresh current
(RAS-only or CBR)
(see Note 3)
VCC = 5.5 V, Minimum cycle,
(RAS-only), RAS cycling,
CAS high (CBR only)
RAS low after CAS low
ICC4t
Average page current
(see Note 4)
VCC = 5.5 V, tpc = minimum,
RAS low, CAS cycling
120
105
95
rnA
ICC5;
Battery backup operating
current (equivalent refresh
time is 64 ms) (CBR only)
tRC = 125 1lS, tRAS " 1 IlS,
VCC-0.2V "VIH" 6.5 V,
OV "VIL" 0.2 V, UW, LWand
OE=VIH, Address and Data stable
300
300
300
i!A
ICC6H
Self refresh current
CAS < 0.2 V, RAS < 0.2 V,
Measured after tRASS minimum
200
200
200
i!A
t Measured with outputs open.
:I: For TMS44165P only.
NOTES:
3. Measured with a maximum of one address change while RAS = VIL.
4. Measured with a maximum of one address change while CAS = VIH.
capacitance over recommended ranges of supply voltage and operating free-air temperature,
f = 1 MHz (see Note 5)
PARAMETER
MIN
TYP
MAX
UNIT
Ci(A)
Input capacitance, address inputs
5
pF
Ci(OE)
Input capacitance, output enable
7
pF
Ci(RC)
Input capacitance, strobe inputs
7
pF
Ci(W)
Input capacitance, write-enable input
7
pF
Co
Output capacitance
7
pF
NOTE 5: VCC equal to 5 V ± 0.5 V and the bias on pins under test is 0 V.
TEXAS ."
IN5rRUMENTS
4-120
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
TMS44165, TMS44165P
262144-WORD BY 16-BIT HIGH-SPEED
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS166A-SEPTEMBER 1991-REVISED DECEMBER 1992
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature
'44165-70
'44165P-70
PARAMETER
MIN
'44165-80
'44165P-80
MAX
MIN
'44165-10
'44165P-10
MAX
MIN
UNIT
MAX
tCAC
Access time from CAS low
20
20
25
ns
tAA
Access time from column address
35
40
45
ns
ns
tRAC
Access time from RAS low
70
80
100
tOEA
Access time from OE low
20
20
25
ns
tCPA
Access time from column precharge
40
45
50
ns
tCLZ
CAS low to output in low Z
0
tOFF
Output disable time after CAS high (see Note 6)
0
20
0
20
0
25
ns
tOEZ
Output disable time after OE high (see Note 6)
0
20
0
20
0
25
ns
..
NOTE 6: tOFF and tOEZ are specified when the output
IS
0
0
ns
no longer driven .
z
o
~
:a:
a:
o
u..
Z
W
o
Z
~
C
~
TEXAS
~
INSlRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
4-121
TMS44165, TMS44165P
262144·WORD BY 16·BIT HIGH·SPEED
DYNAMIC RANDOM·ACCESS MEMORIES
SMHS166A-SEPTEMBER 1991-REVISED DECEMBER 1992
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (see Note 7)
'44165-70
'44165P-70
PARAMETER
MAX
MIN
»
C.
~
Z
o
m
-z
."
o
II
:s:
~
o
z
'44165-80
'44165P-80
MIN
'44165-10
'44165P-10
MAX
MIN
UNIT
MAX
tRC
Read cycle time (see Note 8)
130
150
180
ns
twc
Write cycle time
130
150
180
ns
tRWC
Read-modify-write cycle time
185
205
245
ns
tpc
Page-mode read or write cycle time (see Note 9)
45
50
55
ns
tpRWC
Page-mode read-modify-write cycle time
90
tRASP
Page-mode pulse duration, RAS low (see Note 11)
70
100 000
80
100 000
100
100 000
ns
tRAS
Non-page-mode pulse duration, RAS low (see Note 11)
70
10 000
80
10 000
100
10 000
ns
tCAS
Pulse duration, CAS low (see Note 10)
20
10 000
20
10 000
25
10 000
ns
tcp
Pulse duration, CAS high
10
10
10
ns
tRP
Pulse duration, RAS high (precharge)
50
60
70
ns
twp
Write pulse duration
15
15
20
ns
tASC
Column-address setup time before CAS low
0
0
0
ns
tASR
Row-address setup time before RAS low
0
0
a
ns
tos
Data setup time before xW low (see Note 12)
0
0
0
ns
tRCS
Read setup time before CAS low
0
0
a
ns
tCWL
xW-low setup time before CAS high
20
20
25
ns
20
20
25
ns
a
a
0
ns
ns
105
120
ns
tRWL
xW-low setup time before RAS high
twcs
xW-low setup time before CAS low (see Note 13)
tCAH
Column-address hold time after CAS low (see Note 12)
15
15
20
tOHR
Data hold time after RAS low (see Note 15)
35
35
45
ns
tOH
Data hold time after CAS low (see Note 12)
15
15
20
ns
tAR
Column-address hold time after RAS low (see Note 15)
35
35
45
ns
tRAH
Row-address hold time after RAS low
10
10
15
ns
a
a
a
ns
0
ns
tRCH
Read hold time after CAS high (see Note 16)
0
tRRH
Read hold time after RAS high (see Note 16)
a
NOTES:
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
Timing measurements are referenced to VIL max and VIH min.
All cycle times assume IT = 5 ns.
tpc > tcp min + tCAS min + 2\T.
In a read-modify-wrHe cycle, tcwo and tCWL must be observed. Depending on the user's transition times, this may require additional
CAS low time (tCAS).
In a read-modify-wrHe cycle, tRWO and tRWL must be observed. Depending on the user's transition times, this may require additional
RAS low time (tRAS).
Later of CAS or xW in write operations.
Early write operation only.
CAS-before-RAS refresh only.
The minimum value is measured when tRCO is set to tRCO min as a reference.
Either tRRH or tRCH must be satisfied for a read cycle.
TEXAS
~
INSTRUMENTS
4-122
POST OFFICE BOX 1443· HOUSTON, TEXAS 77001
TMS44165, TMS44165P
262144·WORD BY 16·BIT HIGH·SPEED
DYNAMIC RANDOM·ACCESS MEMORIES
SMHSI66A-8EPTEMBER 1991-REVISED DECEMBER 1992
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (see Note 7) (concluded)
'44165-70
'44165P-70
PARAMETER
MIN
'44165-80
'44165P-80
MAX
MIN
MAX
'44165-10
'44165P-10
MIN
UNIT
MAX
twCH
Write hold time after CAS low (see Note 13)
15
15
20
ns
twCR
Write hold time after RAS low (see Note 15)
35
35
45
ns
tAWD
Delay time, column address to xW low (see Note 17)
65
70
80
ns
tCHR
Delay time, RAS low 10 CAS high (see Nole 14)
15
20
20
ns
tCRP
Delay time, CAS high to RAS low
0
0
0
ns
tCSH
Delay time, RAS low 10 CAS high
70
80
100
ns
tCSR
Delay lime, CAS low to RAS low (see Note 14)
10
10
10
ns
tCWD
Delay time, CAS low to xW low (see Nole 17)
50
50
60
ns
tOEH
OE command hold time
20
20
25
ns
tOED
Delay time, OE high before data at DQ
20
20
25
ns
10
tROH
Delay time, OE low to RAS high
10
tRAD
Delay time, RAS low to column address (see Note 18)
15
tRAL
Delay time, column address to RAS high
35
ICAL
Delay time, column address to CAS high
35
IRCD
Delay time, RAS low to CAS low (see Nole 18)
20
tRPC
Delay time, RAS high to CAS low (see Note 14)
0
0
0
ns
IRSH
Delay time, CAS low to RAS high
20
20
25
ns
IRWD
Delay time, RAS low to xW low (see Note 17)
100
110
135
ns
ICPR
CAS precharge before self refresh
0
0
0
ns
IRPS
RAS precharge after self refresh
130
150
180
ns
IRASS
Self-refresh entry from RAS low
100
tREF
Refresh time interval (TMS44165)
Refresh time interval, low power (TMS44165P only)
tcHS
CAS low hold time after RAS high
IT
Transition time
7.
13.
14.
15.
17.
18.
15
20
25
128
-50
2
ns
75
2
ns
I-'S
16
ms
128
ms
-50
50
ns
ns
100
16
128
ns
55
45
60
100
50
20
45
40
50
-50
2
40
40
16
tREF
NOTES:
10
35
ns
50
ns
Timing measurements are referenced to VIL max and VIH min.
Early write operalion only.
CAS-before-RAS refresh only
The minimum value is measured when IRCD is sel 10 tRCD min as a reference.
Read-modify-write operation only.
Maximum value specified only 10 assure access time.
:2:
a:
oLL.
Z
W
U
Z
~
c
c
~
z
o
m
-z
"oJJ
s:
-o~
z
t Either UW or LW may be brought low and the user can write into eight DO locations, or UW and LW may be brought low at the same time and
all 16 DQ locations will be written into.
t All DO pins remain in the HI-Z state for an early write cycle.
Figure 3. Early Write Cycle Timing
TEXAS ~
INSTRUMENTS
4-126
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
TMS44165, TMS44165P
262144·WORD BY 16·BIT HIGH·SPEED
DYNAMIC RANDOM·ACCESS MEMORIES
SMHS166A-SEPTEMBER 1991-REVISED DECEMBER 1992
PARAMETER MEASUREMENT INFORMATION
z
o
-
!d:
~
a:
ou.
z
UJ
o
Z
~
t Either UW or LW may be brought low and the user can write into eight DO locations, or UW and LW may be brought low at the same time and
all 16 DO locations will be written into.
:j: All DO pins remain in the HI-Z state while OE is high.
NOTE A: Later of CAS or xW in write operations.
Figure 4. Write Cycle Timing
TEXAS ~
INsrRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
4-127
C
cd:
TMS44165, TMS44165P
262144·WORD BY 16·BIT HIGH·SPEED
DYNAMIC RANDOM·ACCESS MEMORIES
SMHS166A-SEPTEMBER 1991-REVISED DECEMBER 1992
PARAMETER MEASUREMENT INFORMATION
»
c
~
z
o
m
UW,Lwt
-Z
-n
o
DQO-DQ1S* AA."A'''' Don't Care
tOEA
3:
~
Valid Out
I
:D
o
z
\/VVV",,,,,,,,:'
-+i
I+---
I
Valid In
:',.vvvvv"'v,,
I
.~--"'.t-I
tOED
~~~~!~------------------
t Either UW or LW may be brought low and the user can write into eight DO locations. or UW and LW may be brought low at the same time and
all 16 DO locations will be written into,
i All DO pins remain in the HI-Z state for an early write cycle,
Figure 5. Read-Modify-Write Cycle Timing
TEXAS ~
INSTRUMENTS
4·128
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
TMS44165, TMS44165P
262144·WORD BY 16·BIT HIGH·SPEED
DYNAMIC RANDOM·ACCESS MEMORIES
SMHS166A-5EPTEMBER 1991-REVISED DECEMBER 1992
PARAMETER MEASUREMENT INFORMATION
t4
tRASP
I
I
I
~
RASN
I
I
I ~
I I
tCSH
Ii
tAR
I_
I I
I.
I
*: C~lumn
tASR
~
~ ~
_
tRAH ---+I I
I
AO-A8~
~
~tCAS-1
N
I 114
I~!.. tASC
,.,.
Row
~
--~
UW, lW
I
I
I
I
r
~
I
I
14
I.
t
..
-I
I
~
r4
tClZ
Vi
f~~~;~~~~~:N
tRAl
tAA - - . :
I
--+---.!
~
I
V:?~~~!:¥,~~~::&
~tRCH~
~
Column
I
tRRH
IIWI
I
I
I
~tOFF
I
J,...- tAA ----+i
I
14
tCPA
~
I
CAC~
I
I
I
I
I
j4-- tCAl ----.I
~
I
I
-l4-----+i
Ii
~
tCAH I
I
I I
I
tRSH
\{
I
I
z
~
o
~
(see Note C)
'>-..,.-~..,._~
I
I
I
c
~
z
o
m
-z
o
"
:c
s:
-o~
z
I
I
I
I
14
:
OQ8-DQ15~
, ( s e e Note A)
Jill
tOH
14
"!
tOHR
tos
(U.N,..
~
~
~
,
~
~:~~~~~§f£~
Valid Data In
I
DQo-DC7
~§2ij&222§§222m;,1:~:B:~
--: 14- tOED
j4-- tOEH -+I
VoII' I,
~ i+- tOED
I+- tOEH --:
(see Note B)
~Ei~Ki:s&2
NOTES: A. Later of CAS or xW in write operations.
B. A read cycle or read-modify-write cycle can be mixed with the write cycles as long as the read and read-modify-write timing
specifications are not violated.
Figure 7. Enhanced Page-Mode Write Cycle Timing
TEXAS ~
INsrRUMENTS
4-130
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
TMS44165, TMS44165P
262 144·WORD BY 16·BIT HIGH·SPEED
DYNAMIC RANDOM·ACCESS MEMORIES
SMHS166A-5EPTEMBER 1991-REVISED DECEMBER 1992
PARAMETER MEASUREMENT INFORMATION
tRP--+J
RAS~
I ~I------------------------------------------~I
I 1'<..11- - - - tCSH --------~.I
"I l'1..li11 - - - - - tRSH -------+1.1
I
I I
1'..I I1f-------- tPRWC'
....
I
I I"
tcp
~tRCO
-+i
I
~
tRAsP----------------------~~
1 ~~
~I
i~
i tASR ,I \I ( - tCASI
I
t~AO I:
-+j~tASC
.: 1 I
I
tCAH
-!i
tAR
tCRP~i
~
lo.-_ _ _ _ _ _ _ _ _ _ _ _-'!I
I
iI
I
I
I
I
I
I
I
I
I
.'
Column
AD-AS
I
II
II
I
I"
III
,tRWO-.i
1..
I~tAA
1__
I
~
I I
I~ tCPA ~I
I I
~
~
I ,...
.. --..;-1 tOH
1
I II
I
I
RAC I - I
~!.,.-j- tos
I~ tCAC I
I
z
~ tRWL --+I
I
i~
:
1 II I
. I II -,
--pi
~ tRCS
1
!.,.-t
jtCWL
J. ~r--"-rr~,
11-.I'~tw~P~-~\.!I
I I
_
UW'LW~::
1
-.I
:'--tCWD~:
~ tAWO ----+i
I
I
1
I (see Note C) I
'S.
~
~
I
I..
ou.
Valid Out
z
w
1
r-OEB
--.I I.-l
I
I I
tOEA
~ I..--
I
Valid
Out
tOEZ
1
1'..I I1f----..- tOED
i
I~..- -••II- tOEH 1
:
\Jl<------.~~~~~
NOTES: A. Output may go from high impedance to an invalid data state prior to the specified access time.
B. Access time is tCPA or tM dependent.
C. A read or write cycle can be intermixed with read-modify-write cycles as long as the read and write cycle timing specifications are
not violated.
Figure 8. Enhanced Page-Mode Read-Modify-Write Cycle Timing
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443· HOUSTON. TEXAS 77001
~
::!:
a:
tOEH
(see Nole A)
OOD-001s-.....;.--.....;.-.....o.c~XX
tCLZ
o
4-131
CJ
Z
~
c
A 2620143
20017/2108
~
I> C20[ROW]
.~
I>
G23/[REFRESH ROW)
24[PWR OWN)
C21
G24
&
23C22
31
2
r
r.,
3
4-
A,22D
4-
A,32D
V 36,37
I> C21
G34
28
&
Z31
W
OE
13
27
OQO
OQ1
23,210
"-
23C32
31
t
24,25EN27
34,25EN37
G25
r
V 26,27
A,Z26
OQ2 4
OQ3 5
004 7
8
005
OQ6 9
007
008
OQ9
OQ10
OQ11
OQ12
OQ13
0014
OQ15
10
31
32
A,Z36
33
34
36
37
38
39
tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and lEG Publication 617-12.
The pin numbers shown correspond to the DZ package.
TEXAS ~
INSJRUMENlS
POST OFFICE BOX 1443' HOUSTON. TEXAS 77001
4-141
TMS45160, TMS45160P
262144·WORD BY 16·BIT HIGH·SPEED
DYNAMIC RANDOM·ACCESS MEMORIES
SMHS160S-AUGUST1992-REVISED DECEMBER 1992
functional block diagram
9
AO
A1
Column Decode
•
Column
Address
Buffers
Sense Amplifiers
128KArray
128KArray
A8
•
16
••
•
128KArray
R
0
w
0
e
128KArray
•
••
C
Row
Address
Buffers
0
d
e
128KArray
OQO-OQ15
128KArray
9
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage range on any pin (see Note 1) .......................................... - 1 V to 7 V
Supply voltage range on Vee ......................................................... - 1 V to 7 V
Short circuit output current ................................................................ 50 mA
Power dissipation .......................................................................... 1 W
Operating free-air temperature range .................................................. O°C to 70°C
Storage temperature range ....................................................... - 55°C to 150°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. This is a stress rating only, and
functional operation of the device at these or any other conditions beyond those indicated in the "recommended operating conditions" section
of this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values in this data sheet are with respect to VSS.
recommended operating conditions
MIN
NOM
MAX
4.5
5
5.5
UNIT
Vee
Supply voltage
VSS
Supply voltage
V
VIH
High-level input voltage
2.4
6.5
VIL
Low-level input voltage (see Note 2)
-1
0.8
V
TA
Operating free-air temperature
0
70
·e
V
0
V
NOTE 2: The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used in this data sheet for
logic voltage levels only.
TEXAS ."
4-142
INSIRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
TMS45160, TMS45160P
262144·WORD BY 16·BIT HIGH·SPEED
DYNAMIC RANDOM·ACCESS MEMORIES
SMHS160B-AUGUST1992-REVISED DECEMBER 1992
electrical characteristics over full ranges of recommended operating conditions (unless otherwise
noted)
PARAMETER
TMS45160·70
TMS45160P·70
TEST CONDITIONS
MIN
VOH
High-Ieveloulput
voltage
Low-level output
VOL
voltage
MAX
2.4
IOH=-5mA
10L= 4.2 rnA
TMS45160·80
TMS45160P-BO
MIN
MAX
2.4
TMS4516o-10
TMS45160P·l0
MIN
UNIT
MAX
2.4
V
0.4
0.4
0.4
V
II
Inpul current
(leakage)
VCC = 5.5 V, VI = 0 to 6.5 V,
All other pins = 0 V to VCC
±10
±10
±10
ItA
10
Output current
(leakage)
VCC = 5.5 V, Vo = 0 to VCC, CAS high
±10
±10
±10
ItA
ICCl t §
Read or write cycle
current
VCC = 5.5 V, Minimum cycle
160
140
120
rnA
2
2
2
rnA
1
1
1
rnA
200
200
200
ItA
160
140
120
rnA
VCC = 5.5 V, tpc = minimum,
RAS low, CAS cycling
160
140
120
rnA
tRC = 125!J.S, tRAS" 1 !J.S,
VCC-0.2V "VIH ,,6.5 V,
V "VIL ,,0.2 V, IN and OE = VIH,
Address and Data stable
300
300
300
ItA
200
200
200
ItA
VIH = 2.4 V (TTL),
After 1 memory cycle,
RAS and CAS high
ICC2
ICC3*
Standby current
VIH = VCC - 0.2 V (CMOS),
After 1 memory cycle,
RAS and CAS high
Average refresh
current (RAS-only
orCBR)
ICC4 t §
ICC511
Average page
current
Battery back-up
operating current
(equivalent refesh
time is 64 ms).
CBRonly.
ICC6 t1l
Self refresh
'45160
'45160P
VCC = 5.5 V, Minimum cycle,
(RAS-only),
RAS cycling, CAS high (CBR only),
RAS low after CAS low
o
CAS < 0.2 V,HAS < 0.2 V,
tRAS and tCAS > 1000 ms
t
Measured with outputs open.
* Measured with a maximum of one address change while RAS = VIL.
§ Measured wnh a maximum of one address change while, xCAS = VIH.
11 For TMS45160P only.
capacitance over recommended ranges of supply voltage and operating free·air temperature,
f = 1 MHZ# (see Note 3)
PARAMETER
MIN
TYP
MAX
UNIT
CiIA)
Input capacitance, address inputs
5
pF
Ci(OE)
Input capacitance, output enable
7
pF
Cj(RC)
Input capacitance, strobe inputs
7
pF
Ci(Wj
Input capacitance, write-enable input
7
pF
Co
Output capacitance
7
pF
# Capacitance measurements are made on a sample basIs only.
NOTE 3: VCC equal to 5 V ± 0.5 V and the bias on pins under test is 0 V.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443· HOUSTON. TEXAS 77001
4-143
TMS45160, TMS45160P
262144·WORDBY 16·BIT HIGH·SPEED
DYNAMIC RANDOM·ACCESS MEMORIES
SMHS160B-AUGUST1992-REVISED DECEMBER 1992
switching characteristics over recommended ranges of supply voltage and operating free·air
temperature
TMS45160-70
TMS45160P-70
PARAMETER
MIN
MAX
TMS45160-80
TMS45160P-80
MIN
MAX
TMS45160-10
TMS45160P-10
MIN
UNIT
MAX
tCAC
Access time from xCAS low
20
20
25
tAA
Access time from column address
35
40
45
ns
tRAC
Access time from RAS low
70
80
100
ns
tOEA
Access time from OE low
20
20
25
ns
tCPA
Access time from column precharge
40
45
50
tCLZ
Delay time, xCAS low to output in low Z
0
tOFF
Output disable time after xCAS high (see Note 4)
0
20
0
20
0
25
ns
toEZ
Output disable time after OE high (see Note 4)
0
20
0
20
0
25
ns
0
0
ns
ns
ns
NOTE 4: tOFF and tOEZ are specified when the output is no longer driven.
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (see Note 5)
TMS45160-70
TMS45160P-70
PARAMETER
MIN
MAX
TMS45160-80
TMS45160P-80
MIN
MAX
TMS45160-10
TMS45160P-10
MIN
UNIT
MAX
tRC
Read cycle time (see Note 6)
130
150
180
ns
twc
Write cycle time
130
150
180
ns
tRWC
Read-write/read-modify-write cycle time
185
205
245
ns
tpc
Page-mode read or write cycle time (see Note 7)
45
50
55
ns
tPRWC
Page-mode read-modify-write cycle time
90
105
120
ns
tRASP
Page-mode pulse duration, RAS low (see Note 8)
70
100000
80
100000
100
100000
ns
tRAS
Non-page-mode pulse duration, RAS low (see Note 8)
70
10000
80
10000
100
10000
ns
teAS
Pulse duration, xCAS low (see Note 9)
20
10000
20
10000
25
10000
ns
tcp
Pulse duration, xCAS high
10
10
10
ns
tRP
Pulse duration, RAS high (precharge)
50
60
70
ns
twp
Write pulse duration
15
15
20
ns
tASC
Column-address setup time before xCAS low
0
0
0
ns
tASR
Row-address setup time before RAS low
0
0
0
ns
tDS
Data setup time before W low (see Note 10)
0
0
0
ns
tRCS
Read setup time before xCAS .low
0
0
0
ns
tCWL
W-Iow setup time before xCAS high
20
20
25
ns
Continued next page.
NOTES: 5. liming measurements are referenced to VIL max and VIH min.
6. All cycle times assume IT = 5 ns.
7. tpc > tcp min + tCAS min + 2\r.
8. In a read-modify-write cycle, tRWD and tRWL must be observed. Depending on the user's transition times, this may require additional
RAS low time (tRAS).
9. In a read-modify-write cycle, tCWD and tCWL must be observed. Depending on the user's transition times, this may require additional
xCAS low time (tCAS).
10. Later of CAS or VIi in write operations.
TEXAS
4-144
~
INS1RUMENTS
POST OFFICE BOX 1443' HOUSTON. TEXAS 77001
TMS45160, TMS45160P
262144-WORD BY 16-BIT HIGH-SPEED
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS160B--AUGUST 1992-REVISED DECEMBER 1992
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (continued) (see Note 5)
TMS45160-70
TMS45160P-70
MIN
MAX
TMS45160-80
TMS45160P-80
MIN
MAX
TMS45160-10
TMS45160P-10
MIN
UNIT
MAX
tRWl
W-Iow setup time before RAS high
20
20
25
ns
twcs
W-Iow setup time before xCAS low
(see Note (2)
0
0
0
ns
tCAH
Column-address hold time after xCAS low
(see Note (0)
15
15
20
ns
tDHR
Data hold time after RAS low (see Note (3)
35
35
45
ns
tDH
Data hold time after xCAS low (see Note (0)
15
15
20
ns
tAR
Column-address hold time after RAS low
(see Note (3)
35
35
45
ns
tRAH
Row-address hold time after RAS low
10
ns
Read hold time after xCAS high (see Note (4)
0
10
0
15
tRCH
0
ns
tRRH
Read hold time after RAS high (see Note 14)
0
0
0
ns
twCH
Write hold time after xCAS low (see Note 12)
15
15
20
ns
twCR
Write hold time after RAS low (see Note 13)
35
35
45
ns
tClCH
Hold time, xCAS low to CAS high
ns
Delay time, column address to W low (see Note 15)
5
70
5
tAWD
5
65
80
ns
tCHR
Delay time, RAS low to CAS high
(see Note 11)
15
20
20
ns
tCRP
Delay time, xCAS high to RAS low
0
0
0
ns
tCSH
Delay time, RAS low to xCAS high
70
80
100
ns
tCSR
Delay time, xCAS low to RAS low (see Note 11)
10
10
10
ns
tCWD
Delay time, xCAS low to W low (see Note 15)
50
50
60
ns
tOEH
OE command hold time
20
20
25
ns
tOED
Delay time, OE high before data at DQ
20
20
25
ns
tROH
Delay time, OE low to RAS high
10
10
10
ns
tRAD
Delay time, RAS low to column address
(see Note (6)
15
tRAl
Delay time, column address to RAS high
35
40
45
tCAl
Delay time, column address to xCAS high
35
40
45
tRCD
Delay time, RAS low to xCAS low (see Note (6)
20
tRPC
Delay time, RAS high to xCAS low
(see Note (1)
35
50
0
15
20
0
40
60
20
25
0
55
ns
ns
ns
75
ns
ns
Continued next page.
NOTES: 5. 1iming measurements are referenced to Vil max and VIH min.
10. Later of xCAS or Vi in write operations.
11. xCAS-before-RAS refresh only.
12. Early write operation only.
13. The minimum value is measured when tRCD is set to tRCD min as a reference.
14. Either tRRH or tRCH must be satisfied for a read cycle.
15. Read-modify-write operation only.
16. Maximum value specified only to assure access time.
TEXAS ~
INSlRUMENlS
POST OFFICE BOX 1443· HOUSTON. TEXAS 77001
4-145
TMS45160, TMS45160P
262144·WORD BY 16·BIT HIGH·SPEED
DYNAMIC RANDOM·ACCESS MEMORIES
SMHS160B-AUGUST 1992-REVISED DECEMBER 1992
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (concluded) (see Note 5)
TMS45160-70
TMS45160P-7
MIN
tRSH
Delay time, xCAS low to RAS high
tRWD
Delay time, RAS low to W low (see Note 15)
tCPR
xCAS precharge before self refresh
tRPS
TMS45160-S0
TMS45160P-80
MAX
MIN
MAX
TMS44160-10
TMS45160P-10
MIN
UNIT
MAX
20
20
25
ns
100
110
135
ns
0
0
0
ns
RAS precharge after self refresh
130
150
180
ns
tRASS
Self refresh entry from RAS low
100
100
100
I'S
tREF
Refresh time interval (TMS45160 only)
tREF
Refresh time interval, low poWer (TMS45160P only)
tCHS
xCAS low hold time after RAS high
IT
Transition time
8
8
8
ms
64
64
64
ms
-50
-50
2
50
2
-50
50
2
NOTES: 5. Timing measurements are referenced to VIL max and VIH min.
15. Read-modify-wrne operation only.
PARAMETER MEASUREMENT INFORMATION
1.31 V
VCC=5V
RL= 218 Q
R1 ,,828 Q
Output Under Test --..1"-----;
Output Under Test
R2,,295Q
CL" 100 pF
I
(a) Load Circuit
(b) Alternate Load Clrcuil
Figure 1. Load Circuits for Timing Parameters
TEXAS
4-146
-IJ1
INSTRUMENTS
POST OFFICE BOX 1443' HOUSTON. TEXAS 77001
ns
50
ns
TMS45160, TMS45160P
262144·WORD BY 16·BIT HIGH·SPEED
DYNAMIC RANDOM~ACCESS MEMORIES
SMHS160B-AUGUST 1992-REVISED DECEMBER 1992
PARAMETER MEASUREMENT INFORMATION
:..
RAS
r:
tRC
~
tRAS
tr ~I J+--- tRCO ---+i
:!
jt-
,
'
.
I
:, t~
,
I
tCAS
tCLCH
i :tCSH
, ,
I
,J+-tRAO--,
!
~
~
\l
Ii
{
'01
tRSH
I I
~
I
I
I ~ tCAH
J+- tRP
---.J
"
i
1,1
I
I
'I
I,
~ I
tCAL tRAL
__
i'L
I
i: "" --+:--~~
I
tCRP
,
::
~,
" ,
ItASC~'
I
:
,
"
,i...-!",
, I~ -: tRAH I I '
tASR~ ~:
I\~
1_'
I'·N .... ~)
:!
:~
--r
I
~
,
II
I,
I,
I I
- X R; ~ ~+~~*i~.,---I
I
tRCS
~
"ioI~
H
:
tRCH
-.J
tRRH
OQO-OQ15
NOTES: A.
B.
C.
D.
In order to hold the address latched by the first xCAS going low. the parameter tCLCH must be met.
tCAC is measured from xCAS to its corresponding OQx.
xCAS order is arbitrary.
Output may go from high-impedance to an invalid data state prior to the specified access time.
Figure 2. Read Cycle
TEXAS
lJ1
INSIRUMENlS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
4-147
TMS45160, TMS45160P
262 144-WORD BY 16-BIT HIGH-SPEED
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS160B-AUGUST 1992-REVISED DECEMBER 1992
PARAMETER MEASUREMENT INFORMATION
NOTES: A. In order to hold the address latched by the first xCAS going low, the parameter tCLCH must be met.
B. Later of xCAS or IN in write operations
C. xCAS order is arbitrary.
Figure 3. Write Cycle
TEXAS ~
4-148
INSlRUMENlS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
TMS45160, TMS45160P
262144·WORD BY 16·BIT HIGH·SPEED
DYNAMIC RANDOM·ACCESS MEMORIES
SMHS160B-AUGUST1992-REVISED DECEMBER 1992
PARAMETER MEASUREMENT INFORMATION
________~~~---------------~C----------------~~
IT
i't-------t
i
!4--- tRCD ~
i
'N"- -.1(1
;I
I
I
I
I
I
I
1+ tASR ~
I
I
I
I
I
-----------1Y:
tl~SH
I :..
i t4---f
I:
ICAS
I
I
I
I
I
I 1
1 IRSH
I i4
I ICLCH ~
:
1
1
1
(see Nole A ) :
I
*IRAD ~
I
I
ii
I I
I 1
I
I ~
\.
~II
II
1
I
I
I
i I.
\. i
1
1
1
~IRAHI
II
~I
I I IASC~ I
II
~IIICAL
I
.1
~
IRAL
I
I
I
~
I
I
I
I
I
I
I
I
I
1""""-----
*- tRP ~
ICRP
---.l
~
I
I
I
,cp---~~i
~I
11~~--~~~~~~~~~~~~~~~7
Col.
I
AD-AS
w
RAS
Address
L
I
,..
IARJ
twcs
~
I
14
1
1
I
~
II'"
Don'l Care .. "-",A/\.AAAAAA.rvv
I
h'CAH
I
1
I
I
I
~
:r-"CH~""'~"""""'~"""""'=""""""''''''''''''''''''''''''''''''''''''''
~~__--I-I_lfL-W_L_ IRWL J
tWCR ----~
...
IWp
~
~
DQO-DQ15
1
~IDHR 1
14-1III--t~1I- IDH
~
i4- IDS-.I
NOTES: A In order to hold the address latched by the first xCAS going low, the parameter tCLCH must be met
B. xCAS order is arbitrary.
Figure 4. Early Write Cycle Timing
TEXAS ~
INSTRUMENlS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
4-149
TMS45160, TMS45160P
262144·WORD BY 16·BIT HIGH·SPEED
DYNAMIC RANDOM·ACCESS MEMORIES
SMHS160B-AUGUST 1992-REVISED DECEMBER 1992
PARAMETER MEASUREMENT INFORMATION
NOTES: A. In order to hold the address latched by the first xCAS going low, the parameter tCLCH must be met.
B. xCAS order is arbitrary.
C. Output may go from high-impedance to an invalid data state prior to the specified access time.
Figure 5. Read-Modify-Write Cycle
TEXAS ~
INSlRUMENlS
4-150
POST OFFICE BOX 1443· HOUSTON. TEXAS 77001
TMS45160, TMS45160P
262144-WORD BY 16-BIT HIGH-SPEED
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS160B-AUGUST1992-REVISED DECEMBER 1992
PARAMETER MEASUREMENT INFORMATION
I I
I I
I I
\{'
II
I
tCSH
I 14
LCAS
' I I
/
~
,
II
I I
~leAL---+i I
I
I I
I
\~:II______~/,~------~I~I--------~
I !
I i
,iii
r---*
1-
!j4~====~~tR~A~L~~~~~~~~~~
leAH
I I
AO-AB
Column
I
w~ i
tRCS
,
14
Don't Care
:: ~tCAC~~
~
I+I-t- tAA
I
I
14
~
Iltpc
j4
~ ~ tcp ~ I
------~I~I----'~l
Vi
tt SR
!~ tCAS ~
I
j4- tAR +----I
I tRAH ~
i I I
I
I ~ j4-r tASC
I
!
,'
I tRSH ~ I
j4
1'----'
.
~ I
,tRAC
tCLZ
14
I
,I
"I
1
I
I
I
I4-+jtOFF
~~I
lid
008-0015 - - - - - - - - - - - _
a
I
~%~~~t~
:
I
--------i-....;;.;..;....--------.I !.-
Out 1
tCPA
-.I
14-- tAA ~
I 1-
i
tOEZ
I
DO~07 -------------~~ ~~~ 2~--------
I+-- tOEA
1
"I
':.----------
~~I_ _ _ _~_ _ _ _ _ _~I
NOTES: A.
B.
C.
D.
E.
In order to hold the address latched by the first xCAS going low, the parameter tCLCH must be met.
tCAC is measured from xCAS to its corresponding OQx.
xCAS order is arbitrary.
Output may go from high-impedance to an invalid data state prior to the specified access time.
A write cycle or read-modify-write cycle can be mixed with the read cycles as long as the write and read-modify-write timing
specifications are not violated.
F. Access time is tCPA or tAA dependent.
Figure 6. Enhanced Page-Mode Read Cycle Timing
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443· HOUSTON. TEXAS 77001
4-151
TMS45160, TMS45160P
262144·WORD BY 16·BIT HIGH·SPEED
DYNAMIC RANDOM·ACCESS MEMORIES
SMHS160B-AUGUST 1992-REVISED DECEMBER 1992
PARAMETER MEASUREMENT INFORMATION
tRP~
i'r.-------------------tRASP------------------~~
1 ~I-----------------------------14------t-R-SH-~--~
ii
i
1
1
~
\
1
j4- tCLCH
14- tRCD -+i
~
tASR
1414---------
~
14
~tAR I I
1
1
1
1
1 tASC -+1
:,1_ _"",14- tRAH 1
I
14+
.1
~
tCAH
r
,
1
1
1
1
I
(see Note E)
:
:
1
1
14
tDS~
I
W
D~"
---i
~
DQO--DQ7
--------i
~
Column
I+---
tCWL
.1
1
~gd~~g"""""'~ia""""'~
1
tRAL
atDHR~
1
twCH
I
1
1
.1
~"""'''''"'?bo:~?bo:~~~~~~
"",,,''0./\/\/''',,,,,, Don't Care vVV'V'"''''''
tCWL
----.t
twP~
1
twCR - + i i 4
1 4 - - - - tRWL
I'll
1
1 1
:
1
_I
14
1
-+:_____
(
~tCAL--~Pj
1
!
.,..1
\
1
.
~~ tCRP -+i
----+l
tcp
AO--A8
1
tpc ______
1
1
:
__
1
!'t-tCAS-Y
1
-oJ/
!
~
: tCSH
J:
1
1
1
\l. . .
(
:
1
1
~
1
1
~H{t}!*:~
~I""}
<. . .
_"_a_lId_ln_..J)>-----------
14-- t D H ' (see Note D)
Valid In
J
(~__"_al_ld_l_n_..1)>-------------
I.-tOED
OEJ
NOTES: A. In order to hold the address latched by the first xCAS going low, the parameter tCLCH must be met.
B. xCAS order is arbitrary.
C. A read cycle or read-modify-write cycle can be mixed with the write cycles as long as the read and read-modify-write timing
specifications are not violated.
D, Referenced to xCAS or W, whichever occurs last.
Figure 7. Enhanced Page-Mode Write Cycle Timing
TEXAS .J!I
INSTRUMENTS
4-152
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
TMS45160, TMS45160P
262144·WORD BY 16·BIT HIGH·SPEED
DYNAMIC RANDOM·ACCESS MEMORIES
SMHS160B-AUGUST1992-REVISED DECEMBER 1992
PARAMETER MEASUREMENT INFORMATION
tOEH
DQO-DQ15
i+I
I
OE
~
Valid Out
tOEA -----+j
~I
-+I
tOEZ
tOEH
I
~I______~I
I
r----1~
tOED
.I
I
I
I
I~________~~~~~~
i ".
III
.
l
\\......---JI
~
In order to hold the address latched by the first xCAS going low, the parameter tCLCH must be met.
tCAC is measured from xCAS to its corresponding DQx.
xCAS order is arbitrary.
Output may go from high-impedance to an invalid data state prior to the specified access time.
E. A read or write cycle can be intermixed with read-modify-write cycles as long as the read and write cycle timing specifications are
not violated.
NOTES: A.
B.
C.
D.
Figure 8. Enhanced Page-Mode Read-Modify-Write Cycle Timing
. TEXAS'"
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
4-153
TMS45160, TMS45160P
262144·WORD BY 16·BIT HIGH·SPEED
DYNAMIC RANDOM·ACCESS MEMORIES
SMHS160B-AUGUST 1992-REVISED DECEMBER 1992
PARAMETER MEASUREMENT INFORMATION
OQO-OQ15 - - - - - - - - - - - - - HI-Z - - - - - - - - - - - - - -
NOTE A: All xCAS must be high.
Figure 9. RAS-Only Refresh Timing
TEXAS .JJ}
INSlRUMENlS
4-154
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
TMS45160, TMS45160P
262144·WORD BY 16·BIT HIGH·SPEED
DYNAMIC RANDOM·ACCESS MEMORIES
SMHS160B-AUGUST1992-REVISED DECEMBER 1992
PARAMETER MEASUREMENT INFORMATION
14--
Memory Cycle
/4
~
I 1
tRP
tRAS'
RAS~
I
II
xCAS
;:
~14-t
14-----.I
tRAS:
0I
... ~
N
I
~
~
I
I
!X
I
r
tASR
1
tRAH ~!+-i.
Refresh Cycle
~
----+I
14--
~
Y \
loll
Refresh Cycle
tRP
----.I
I
!~
I
tCHR
tCAS
14
~
~
JI!
II
1
I
JJ
I ,
I
I
~!4-tASC
A~A8~
IRO~ CO/ ~gHK~J~~~
11-'
tRCS
'14- tCAH
~
1
1
1
~
14-
I
tRRH
~III~gg~h~ar; ~~
Wii7!
1 1-./ 14- tCAC
I ~ tAA
DQO-DQ15-----<~
-+i
OE
tOFF
~
tRACioII
Valid Data
~~
-.I
14I
}-
I~------------------------------~))T------------~I
14- tOEA
1 4 - tOEZ - - + I
~~------------------~)~
Figure 10. Hidden Refresh Cycle
TEXAS ~
INSlRUMENlS
POST OFFICE BOX 1443· HOUSTON, TEXAS 77001
4-155
TMS45160, TMS45160P
262144·WORD BY 16·BIT HIGH·SPEED
DYNAMIC RANDOM·ACCESS MEMORIES
SMHS160B-AUGUST 1992-REVISED DECEMBER 1992
PARAMETER MEASUREMENT INFORMATION
~1~--------------------tRC------------------~~1
14-- tRP ~ 141~----------- tRAS -------------.t~1 I
I
RAS
I Iit--_ __
Y
AI i~~~
tRPC -
xCAS
I I
.1
j+-tCSR~ I
~I '41~------- tcHR
~I
~~I____~
____
~
__~
________________~~
Vi
OQO-OQ15--------------HI·Z - - - - - - - - - - - - - - - NOTES: A. Any xCAS may be used.
B. 512 CBR cycles must be used for CBR counter test.
Figure 11. Automatic (CAS-Before-RAS) Refresh Cycle Timing
TEXAS •
INSlRUMENTS
4·156
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
TMS45160, TMS45160P
262144·WORD BY 16·BIT HIGH·SPEED
DYNAMIC RANDOM·ACCESS MEMORIES
SMHS160B-AUGUST1992-REVISED DECEMBER 1992
.
PARAMETER MEASUREMENT INFORMATION
·- - - - - t R A S S -------~
1
RAS _ _---,/1
1
1
1
N,~
j
1""'-------"\
/1
1-
tCSR
~
1\
-.J
I+- tRPS
II
-.1 I+- tCHS
1
~ tRPC -.1 1
r-----~I 1
xCAs1
~
1
~
--1~tCPR--~1 ~------------------"----------~~~~
AO-A8
DQO-DQ15~--------HI-Z-------------
NOTE A: Any xCAS may be used.
Figure 12. Self Refresh Timing
TEXAS -1!1
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
4-157
TMS45160, TMS45160P
262144·WORD BY 16·BIT HIGH·SPEED
DYNAMIC RANDOM~ACCESS MEMORIES
SMHSI60B-AUGUST 1992-REVISED DECEMBER 1992
device symbolization
TI
=:)
1~
TMS45160 ~
W
~
P
T
Speed Code
Low Power/Self-Refresh Code
Package Code
~
Lot Traceability Code
Month Code
Assembly Site Code
Ole Revision Code
Wafer Fab Code
TEXAS ~
4-158
INSIRUMENlS
POST OFFICE BOX 1443 • HOUSTON,TEXAS 77001
TMS45165, TMS45165P
262144·WORD BY 16·BIT HIGH·SPEED
DYNAMIC RANDOM·ACCESS MEMORIES
SMHS165B-OCTOBER 1992-REVISED DECEMBER 1992
•
•
•
This data sheet is applicable to al/
TMS45165/Ps symbolized with Revision "8"
and subsequent revisions as described on
page 23.
Organization ... 262 144 x 16
Single 5·V Supply (±10% Tolerance)
Performance Ranges:
'45165/P·70
'45165{P·80
'45165{P-l0
ACCESS ACCESS ACCESS READ OR
TIME
TIME
TIME
WRITE
tAA
CYCLE
tRAC
tCAC
MAX
MAX
MAX
MIN
70 ns
20 ns
35 ns
130 ns
80 ns
20 ns
40 ns
150 ns
100 ns
25 ns
45 ns
180 ns
•
Enhanced Page Mode Operation With
CAS·Before·RAS Refresh
•
Long Refresh Period ...
512·Cycle Refresh in 8 ms (Max)
64 ms for Low Power With Self·Refresh
Version (TMS45165P)
•
•
•
DZPACKAGE
(TOP VIEW)
1
2
3
4
5
VCC 6
D04 7
D05 8
D06 9
DO? 10
NC 11
LW 12
UW 13
RAS 14
NC 15
AO 16
Al 17
A2 18
A3 19
VCC 20
DGEPACKAGE
(TOP VIEW)
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
VCC
DOO
DOl
D02
D03
VSS
VCC
D015
D014
D013
D012
DOO
DOl
D02
D03
VSS
VCC
DOll
DOlO
DOg
D08
D04
D05
D06
DO?
NC
NC
CAS
NC
OE
LW
A8
A?
A6
A5
A4
VSS
UW
RAS
NC
AO
Al
A2
A3
3·State Unlatched Output
Vcc
Lower Power Dissipation
Texas Instruments EPIC ™ CMOS Process
•
All Inputs, Outputs and Clocks are TTL
Compatible
•
High·Reliability Plastic 40·Lead
400·MII·Wide Surface Mount (SOJ)
Package, and 40/44·Lead Thin Small
Outline Package (TSOP)
1
2
3
4
5
6
7
8
9
10
44
43
42
41
40
39
38
37
36
35
13
14
15
16
17
18
19
20
21
22
32
31
30
29
28
27
26
25
24
23
VSS
D015
D014
D013
D012
VSS
DOll
DOlO
DOg
D08
NC
NC
CAS
OE
A8
A?
A6
A5
A4
VSS
•
Operating Free·Alr Temperature Range
-O°C to 70°C
•
Low·Power With Self·Refresh
•
Upper and Lower Byte Control During Write
Operations
VCC
VSS
a:
Address Inputs
Column-Address Strobe
Data In/Data Out
Output Enable
Lower Write Enable
Upper Write Enable
Row-Address Strobe
No Internal Connection
5-V Supply
Ground
z
w
(,)
z
c~
A
20017/2108
----t:,
RAS
.1L...
f>
C20[ROW]
~ G23/[REFRESH ROW]
>-- 24[PWR OWN]
-=
l>
+
&
----t:,
C
2620143
~
Z31
~
I> C21
G29
[COL]
~ G24
~
Z
CAS
0
m
LW
-z
28
12
."
0
UW
:c
s:
~
OE
13
27
"-
r
r
OQ1 3
OQ2 4
0
Z
23C22
23,210
+
31 &
23,210
.,
29,25EN26
23C32
+
29,25EN27
"- G25
2
OQO
&
4-
r
A,220
'0726
A,Z26
OQ3 5
OQ4 7
8
OQ5
9
OQ6
10
OQ7
31
OQ8
32
A,320
4- '0727
A,Z27
OQ9
33
OQ10
34
OQ11
36
OQ12
37
OQ13
38
OQ14
39
OQ15
t This symbol is in accordance with ANSI/IEEE Std 91-1984 and lEe Publication 617-12,
Pin numbers shown correspond to the DZ package,
TEXAS ~
INsrRUMENTS
4-162
POST OFFICE BOX 1443· HOUSTON, TEXAS 77001
TMS45165, TMS45165P
262144-WORD BY 16-BIT HIGH-SPEED
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS165B-OCTOBER 1992-REVISED DECEMBER 1992
functional block diagram
t t t ++
I
T
16
9
AO
/
A1
A8
Timing and Control
•
•
•
Column Decode
Column
Address
Buffers
Sense Amplifiers
128KArray
-i--
•
128KArray
R
128KArray
L
•
•
16<
Row
Address
Buffers
fr-,L
•
••
0
w
0
e
c
II
/
~
128KArray
•
••
>16
~
~
In
Reg.
161/0
Buffers
Data
Out
Reg.
0
d
e
'--
-
128KArray
9
.,
128KArray
000-0015
z
o
-
!;:
/
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage range on any pin (see Note 1) .......................................... - 1 V to 7 V
Supply voltage range on Vee ......................................................... - 1 V to 7 V
Short circuit output current ................................................................ 50 mA
Power dissipation .......................................................................... 1 W
Operating free-air temperature range ............................................ ,..... O°C to 70°C
Storage temperature range ....................................................... - 55°C to 150°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. This is a stress rating only, and
functional operation of the device at these or any other conditions beyond those indicated in the "recommended operating conditions" section of
this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values in this data sheet are with respect to VSS.
~
a:
ou.
z
w
(.)
z
c~
«
recommended operating conditions
MIN
NOM
MAX
4.5
5
5.5
UNIT
Vee
Supply voltage
VSS
Supply voltage
VIH
High-level input voltage
2.4
6.5
VIL
Low-level input voltage (see Note 2)
-1
0.8
V
TA
Operating free-air temperature
0
70
°e
V
V
0
V
NOTE 2: The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used in this data sheet for
logic vo~age levels only.
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443· HOUSTON. TEXAS 77001
4-163
TMS45165, TMS45165P
262144·WORD BY 16·BIT HIGH·SPEED
DYNAMIC RANDOM·ACCESS MEMORIES
SMHS165B--OCTOBER 1992-REVISED DECEMBER 1992
electrical characteristics over full ranges of recommended operating conditions (unless otherwise
noted)
PARAMETER
MIN
VOH
High-level output voltage
IOH =-5 rnA
VOL
Low-level output voltage
IOL=4.2mA
II
~
z
o
m
-z
o"
::D
s:
~
o
z
MAX
MIN
'45165-10
'45165P-l0
MAX
2.4
2.4
MIN
UNIT
MAX
V
2.4
0.4
0.4
0.4
V
Input current (leakage)
VCC = 5.5 V, VI = 0 to 6.5 V,
All other pins = 0 V to VCC
±10
±10
±10
~
10
Output current (leakage)
VCC = 5.5 V,
Vo = 0 to VCC, CAS high
±10
±10
±10
~
ICCl t
Read or write cycle current
(see Note 3)
VCC = 5.5 V, Minimum cycle
160
140
120
rnA
2
2
2
rnA
1
1
1
rnA
VIH = 2.4 V (TTL)
After 1 memory cycle.
RAS and CAS high
»
c
'45165-80
'45165P-80
'45165-70
'45165P-70
TEST CONDITIONS
ICC2
Standby current
VIH = VCC-O.2V (CMOS)
After 1 memory cycle,
RAS and CAS high
'45165
'45165P
200
200
200
~
160
140
120
rnA
ICC3
Average refresh current
(RAS-only or CBR)
(see Note 3)
VCC = 5.5 V, Minimum cycle,
(RAS-only), RAS cycling,
CAS high (CBR only)
RAS low after CAS low
ICC4 t
Average page current
(see Note 4)
VCC = 5.5 V, tpc = minimum,
RAS low, CAS cycling
160
140
120
rnA
ICC5'*
Battery backup operating
current (equivalent refresh
time is 64 ms) (CBR only)
tRC = 125 itS, tRAS " 1 itS,
VCC - 0.2 V s VIH " 6.5 V,
OV" VIL" 0.2 V, UW, LWand
OE=VIH, Address and Data stable
300
300
300
itA
ICC6 H
Self refresh current
CAS < 0.2 V, RAS < 0.2 V,
Measured after tRASS minimum
200
200
200
itA
t Measured With outputs open.
'* For TMS45165P only.
NOTES: 3. Measured with a maximum of one address change while RAS = VIL.
4. Measured with a maximum of one address change while CAS = VIH.
capacitance over recommended ranges of supply voltage and operating free-air temperature,
f = 1 MHz (see Note 5)
MIN
PARAMETER
TYP
MAX
UNIT
Ci(A)
Input capacitance, address inputs
5
Ci(OE)
Input capacitance, output enable
7
pF
Ci(RC)
Input capacitance, strobe inputs
7
pF
Ci(W)
Input capacitance, write-enable input
7
pF
Co
Output capacitance
7
pF
NOTE 5: VCC equal to 5 V ± 0.5 V and the bias on pins under test is 0 V.
TEXAS
~
INSTRUMENTS
4-164
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
pF
TMS45165, TMS45165P
262144·WORD BY 16·BIT HIGH·SPEED
DYNAMIC RANDOM·ACCESS MEMORIES
SMHS165B-OCTOBER 1992-REVISED DECEMBER 1992
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature
'45165-70
'46165P-70
PARAMETER
MIN
'45165-80
'46165P-80
MAX
MIN
'45165-10
'46165P-l0
MAX
MIN
UNIT
MAX
tCAC
Access time from CAS low
20
20
25
ns
tAA
Accr.ss time from column address
35
40
45
ns
tRAC
Access time from RAS low
70
80
100
ns
tOEA
Access time from OE low
20
20
25
ns
tCPA
Access time from column precharge
40
45
50
ns
tCLZ
CAS low to output in low Z
0
tOFF
Output disable time after CAS high (see Note 6)
0
20
0
20
0
25
ns
tOEZ
Output disable time after OE high (see Note 6)
0
20
0
20
0
25
ns
..
NOTE 6: tOFF and tOEZ are specified when the output
IS
0
0
ns
no longer driven .
z
o
~
:2:
0:
ou.
z
w
o
z
;;c
tcp min + tCAS min + 2IT.
In a read-modify-write cycle, tCWD and tCWL must be observed. Depending on the user's transition times, this may require additional
CAS low time (tCAS).
In a read-modify-write cycle, tRWD and tRWL must be observed. Depending on the user's transition times, this may require additional
RAS low time (tRAS).
Later of CAS or xW in write operations.
Early write operation only.
CAS-before-RAS refresh only.
The minimum value is measured when tRCD is set to tRCD min as a reference.
Either tRRH or tRCH must be satisfied for a read cycle.
1ExAs
~
INsrRUMENTS
4-166
ns
POST OFFICE BOX 1443' HOUSTON. TEXAS 77001
TMS45165, TMS45165P
262144·WORD BY 16·BIT HIGH·SPEED
DYNAMIC RANDOM·ACCESS MEMORIES
SMHS185B-OCTOBER 1992-REVISED DECEMBER 1992
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (see Note 7) (concluded)
'45165-70
'45165P-70
PARAMETER
MIN
'45165-80
'45165P-80
MAX
MIN
'45165-10
'45165P-10
MAX
MIN
UNIT
MAX
twCH
Write hold time after CAS low (see Note 13)
15
15
20
ns
twCR
Write hold time after RAS low (see Note 15)
35
35
45
ns
tAWD
Delay time, column address to xW low (see Note 17)
65
70
80
ns
tCHR
Delay time, RAS low to CAS high (see Note 14)
15
20
20
ns
tCRP
Delay time,
CAS high to RAS low
0
0
0
ns
tCSH
Delay time, RAS low to CAS high
70
80
100
ns
tCSR
Delay time, CAS low to RAS low (see Note 14)
10
10
10
ns
tCWD
Delay time, CAS low to xW low (see Note 17)
50
50
60
ns
tOEH
OE command hold time
20
20
25
ns
tOED
Delay time, OE high before data at DQ
20
20
25
ns
tROH
Delay time, OE low to RAS high
10
10
10
tRAD
Delay time, RAS low to column address (see Note 18)
15
tRAL
Delay time, column address to RAS high
35
tCAL
Delay time, column address to CAS high
35
tRCD
Delay time, RAS low to CAS low (see Note 18)
20
tRPC
Delay time, RAS high to CAS low (see Note 14)
tRSH
Delay time, CAS low to RAS high
tRWD
Delay time, RAS low to xW low (see Note 17)
tCPR
CAS precharge before self refresh
tRPS
35
15
40
40
0
20
ns
55
45
40
50
20
ns
45
60
0
25
ns
ns
75
ns
0
ns
20
20
25
ns
100
110
135
ns
0
0
0
ns
RAS precharge after self refresh
130
150
180
ns
tRASS
Self-refresh entry from RAS low
100
tREF
Refresh time interval (TMS45165 only)
tREF
Refresh time interval, low power (TMS45165P only)
tCHS
CAS low hold time after RAS high
IT
Transition time
NOTES:
7.
13.
14.
15.
17.
18.
8
64
64
-50
2
100
100
8
-50
50
2
f!S
8
ms
64
ms
-50
50
2
ns
50
ns
Timing measurements are referenced to VIL max and VIH mm.
Early wr~e operation only.
CAS-before-RAS refresh only
The minimum value is measured when tRCD is set to tRCD min as a reference.
Read-modify-wr~e operation only.
Maximum value specified only to assure access time.
.
~
~
ex:
oLL
Z
W
U
Z
~
c
<>Q,
~2222222222[~;$~~]Z§l8888&l888&0~
~ 14- tOED
14- tOEH
-+\
j4-- IOEH
Vol" I,
~ i+- tOED
~
(aee Note 8)
~~*J2K£88&
NOTES: A. Later of CAS or xW in write operations.
B. A read cycle or read-modify-write cycle can be mixed with the write cycles as long as the read and read-modify-write timing
specifications are not violated.
Figure 7. Enhanced Page-Mode Write Cycle Timing
1ExAs
~
INSfRUMENTS
4-174
POST OFFICE BOX 1443· HOUSTON. TEXAS no01
TMS45165, TMS45165P
262144·WORD BY 16·BIT HIGH·SPEED
DYNAMIC RANDOM·ACCESS MEMORIES
SMHS165B-OCTOBER 1992-REVISED DECEMBER 1992
PARAMETER MEASUREMENT INFORMATION
tRP~
RAS ~
tRASP
I I
I
I !41..- - - - tCSH ----~.I
I
hi i"..IIl- - - - tRSH ----1.~1
I I
li"II
..- - - - tpRWC
I
.. I
I" I
I I"
tRCO
: ~~ tcp
tCRP
I I
I:I+t-
--+i
I
I:
I
I
tRAO
rr
i~tCAS--"'~
tASR I I
-+!l+i-tASC
II I
.,
I
.1
tCAH ~
'X
I
I
.1
/:
I
I
I
tAR
~
------------~
I
I
I
I
I
I
Column
AO-AS
I
I:
i+-
G4Ii
I
,..
tcwo
tAWO
,tRWO
~
I
.1
I
~ :~r--1~1'I11
~tw~P~--"""'\....
II I
I
1
L
-
~~
II ,
- I II -
I
..-r tRCS
I..
i..--
~:
UW'LW~:' I
_
~ tCWL ---.I
!
·ltAA
tRAC l-+i
~
~ tCAC I
~
I I
1tCP,A
~I
I I
~
.... -...,
I !4"--'.1-1 tOH
I
I:
I
I
*+- t o s '
I
, (see Note B)
,
l,
X
tRWL
~
~
~
I
I..
o
u..
z
Valid Out
I
(see Note A)
rOE_
-+' 1..-4
I
tOEA
I
I
w
Valid
lOut
tOEZ
~ i..-
~
:!E
a:
tOEH
000-0015-"";'--"";'-....1.;,[XX
tCLZ
z
o
I
1"11-1"-"- tOED
1----..1-1 tOEH I
i0
.
0 i.
1
:
:
\J;.--------:i~C=~~~
NOTES: A. Output may go from high impedance to an invalid data state prior to the specified access time,
a, A read or write cycle can be intermixed with read-modify-write cycles as long as the read and write cycle timing specifications are
not violated,
C, Access time is tCPA or tM dependent.
Figure 8. Enhanced Page-Mode Read-Modify-Write Cycle Timing
TEXAS ~
INsrRUMENTS
POST OFFICE BOX 1443· HOUSTON, TEXAS 77001
4-175
o
z
~
o
«
TMS45165, TMS45165P
262144·WORD BY 16·81T HIGH·SPEED
DYNAMIC RANDOM·ACCESS MEMORIES
SMHS165B-OCTOBER 1992-REVISED DECEMBER 1992
PARAMETER MEASUREMENT INFORMATION
j4
RAS
tCRP
j4
1
tRC
RAS - ,
~ I
----I
~
m
~
Figure 9. RAS-Only Refresh Timing
-z
"T1
o
lJ
s:
~
o
z
TEXAS . "
INsrRUMENTS
4·176
1
~
14-IT
»
c
~
z
o
.1
tt JX
----------~N
1
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
tRP
tRPC
--.I " - - - - -
TMS45165, TMS45165P
262144·WORD BY 16·BIT HIGH·SPEED
DYNAMIC RANDOM·ACCESS MEMORIES
SMHS16SB-
-Z
."
RAS
_ _ _ _ _ _~~:
--4 I~ tr
yr____
: ~1IiI--------teHR ~---~~
Y
tesR ...,
AD-AS
c
~
z
o
m
14t4------t
OQD-OQ15 - - - - - - - - - - - - - - H I - Z - - - - - - - - - - - - - NOTE A: 512 CSR cycles must be used for CSR counter test.
o
Figure 11. Automatic (CAS-Before-RAS) Refresh Cycle Timing
:D
3:
~
o
Z
TEXAS ~
INSTRUMENTS
4-178
POST OFFICE BOX 144~ • HOUSTON, TEXAS 77001
TMS45165, TMS45165P
262144·WORD BY 16·BIT HIGH·SPEED
DYNAMIC RANDOM·ACCESS MEMORIES
SMHS165B-OCTOBER 1992-REVISED DECEMBER 1992
PARAMETER MEASUREMENT INFORMATION
~£H*~
~H~*~
OE~m*~
AD-AS
z
o
UW,LW
~
OOD-0015
~
~
a:
ou.
i.t-tOFF
~---
z
_ _ _ _ _ _ HI-Z _ _ _ _- - - - - - -
w
Figure 12_ Self Refresh Timing
o
z
~
c
«
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
4-179
TMS45165, TMS45165P
262144·WORD BY 16·BIT HIGH·SPEED
DYNAMIC RANDOM·ACCESS MEMORIES
SMHS165B-OCTOBER 1992-REVISED DECEMBER 1992
device symbolization
t~
TI
~ TMS45165~
W
~
P
T !:fh
Speed Code
Power/Self-Refresh Code
Package Code
Lot Traceability Code
Month Code
Assembly Site Code
Ole Revision Code
Wafer Fab Code
TEXAS ~
INSTRUMENTS
4-180
POST OFFICE BOX 1443· HOUSTON, TEXAS 77001
TMS416100
16 777 216·81T
DYNAMIC RANDOM·ACCESS MEMORY
SMKS61 OB-NOVEMBER 199O-REVISED JANUARY 1993
DZ PACKAGEt
This data sheet is applicable to all TMS4161 ODs
symbolized with Revision ':,4" and subsequent
revisions as described on page 22.
(TOP VIEW)
• Organization ... 16 777 216 x 1
• Single 5-V Power Supply (10% Tolerance)
• Performance Ranges:
ACCESS ACCESS ACCESS
READ
TIME
TIME
TIME OR WRITE
CYCLE
(tAAl
(tRAC) (tCAC)
(MAX)
(MAX)
(MAX)
(MIN)
TMS416100-60 60 ns
15 ns
30 ns
110 ns
TMS416100-70 70 ns
18 ns
35 ns
130 ns
TMS416100-80 80 ns
20 ns
40 ns
150 ns
• Enhanced Page Mode Operation for Faster
Memory Access
• CAS-Before-RAS Refresh
• Long Refresh Period ... 4096 Cycle
Refresh in 64 ms
• 3-State Unlatched Output
• Low Power Dissipation
• All Inputs, Outputs and Clocks are TTL
Compatible
• Operating Free-Air Temperature Range
O°C to 70°C
description
VCC
D
VSS
Q
NC
W
RAS
All
NC
CAS
NC
A9
Al0
AS
A7
A6
A5
A4
AO
Al
A2
A3
VCC
Vss
DGC PACKAGEt
(TOP VIEW)
VCC
DGD PACKAGEt
(TOP VIEW)
VSS
Q
VSS
Q
VCC
D
NC
W
RAS
All
NC
CAS
NC
A9
NC
CAS
NC
A9
NC
W
RAS
All
The TMS416100 series are high-speed,
16 777 216-bit dynamic random-access memories, organized as 16 777 216 words of one bit
each. They employ state-of-the-art EPIC'"
(Enhanced Performance Implanted CMOS)
technology for high performance, reliability, and
low power at a low cost.
AS
A7
A6
A5
A4
VSS
These devices feature maximum RAS access
times of 60 ns, 70 ns, and SO ns.
D
AS
A7
A6
A5
A4
VSS
t The packages shown are for pinout reference only.
All inputs, outputs, and clocks are compatible with
Series 74 TTL. All addresses and data-in lines are
latched on-chip to simplify system design. Data
out is unlatched to allow greater system flexibility.
PIN NOMENCLATURE
AO--A 11
CAS
D
The TMS416100 is offered in 400-mil 24/2S-pin
surface mount SOJ (DZ suffix) and 400-mil
24/2S-pin surface mountthin SOP (DGC and DGD
suffixes) packages. This device is characterized
for operation from O°C to 70°C.
Q
NC
RAS
Vii
VCC
VSS
Address Inputs
Column-Address Strobe
Data In
Data Out
No Connection
Row-Address Strobe
Write Enable
5-V Supply
Ground
EPIC is a trademark of Texas Instruments Incorporated.
TEXAS
~
Copyright © 1993. Texas Instruments Incorporated
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
4-181
TMS416100
16777216·8IT
DYNAMIC RANDOM·ACCESS MEMORY
SMKS610B-NOVEMBER 199()-REVISEO JANUARY 1993
operation
enhanced page mode
Enhanced page-mode operation allows effectively faster memory access by keeping the same row address and
strobing random column addresses onto the chip. Thus, the time required to set up and strobe row addresses
for the same page is eliminated. The maximum number of columns that can be addressed is determined bytRAS,
the maximum RAS-Iow width.
The column address buffers in this CMOS device are activated on the falling edge of RAS. They act as a
transparent or flow-through latch, while CAS is high. The falling edge of CAS latches the addresses into these
buffers and also serves as an output enable.
This feature allows the TMS4161 00 to operate at a higher data bandwidth than conventional page-mode parts
since retrieval begins as soon as the column address is valid, rather than when CAS transitions low. The
performance improvement is referred to as enhanced page mode. Valid column address may be presented
immediately after row address hold time has been satisfied, usually well in advance of the falling edge of CAS.
In this case, data is obtained after tCAC max (access time from CAS low), if tAA max (access time from column
address) and tRAC have been satisfied. In the event that the column address for the next cycle is valid at the
time CAS goes high, access time is determined by the later occurrence of tCPA or tCAC'
address (AO-A11)
Twenty-four address bits are required to decode 1 of 16 777 216 storage cell locations. Twelve row-address bits
are set up on inputs AO through A 11 and latched during a normal access and during RAS-only refresh as the
device requires 4096 refresh cycles. Twelve column-address bits are set on inputs AO-A 11 and latched onto
the chip by CAS. All addresses must be stable on or before the falling edges of RAS and CAS. RAS is similar
to a chip enable in that it activates the sense amplifiers as well as the row decoder. CAS is used as a chip select,
activating the output buffer, as well as latching the address bits into the column buffer.
write enable ~
The read or write mode is selected through the write-enable 0N) input. A logic high on the W input selects the
read mode and a logic low selects the write mode. The write-enable terminal can be driven from standard TTL
circuits without a pullup resistor. The data input is disabled when the read mode is selected. When W goes low
prior to CAS (early write), data out will remain in the high-impedance state for the entire cycle, permitting
common I/O operation.
data in (D)
Data is written during a write or read-modify-write cycle. Depending on the mode of operation, the faliling edge
of CAS or W strobes data into the on-chip data latch. In an early write cycle, W is brought low prior to CAS and
the data is strobed in by CAS with setup and hold times referenced to this signal. In a delayed-write or
read-modify-write cycle, CAS will already be low, thus the data will be strobed in by W with setup and hold times
referenced to this signal.
data out (Q)
The three-state output buffer provides direct TTL compatibility (no pullup resistor required) with a fanout of two
Series 74 TTL loads. The output is in the high-impedance (floating) state until CAS is brought low. In a read cycle,
the output becomes valid at the latest occurrence of tRAC, tAA, tCAC, or tCPA and remains valid while CAS is low.
CAS going high returns it to a high-impedance state. In a delayed-write or read-modify-write cycle, the output
does not change, but retains the state just read.
TEXAS
~
INSTRUMENTS
4-182
POST OFFICE BOX 1443· HOUSTON. TEXAS 77001
TMS416100
16 777 216-81T
DYNAMIC RANDOM-ACCESS MEMORY
SMKS610B-NOVEMBER 1990-REVISED JANUARY 1993
refresh
A refresh operation must be performed at least once every 64 ms to retain data. This can be achieved by strobing
each of the 4096 rows (AO-A 11). A normal read or write cycle will refresh all bits in each row that is selected.
A RAS-only operation can be used by holding CAS at the high (inactive) level, thus conserving power since the
output buffer remains in the high-impedance state. Externally generated addresses must be used for a RAS-only
refresh. Hidden refresh may be performed by holding CAS at VIL after a read operation and cycling RAS after
a specified precharge period, similar to a RAS-only refresh cycle except with CAS held low. Valid data is
maintained at the output throughout the hidden refresh cycle. An internal address provides the refresh address
during hidden refresh.
CAS-before-RAS refresh
CAS-before-RAS refresh is utilized by bringing CAS low earlier than RAS (see parameter tCSR) and holding it
low after RAS falls (see parameter tCHR). For successive CAS-before-RAS refresh cycles, CAS can remain low
while cycling RAS. For this mode of refresh, the external addresses are ignored and the refresh address is
generated internally.
power up
To achieve proper device operation, an initial pause of 200 I-ts·followed by a minimum of eight initialization cycles
is required after full VCC level is achieved. These eight initialization cycles need to include at least one refresh
(RAS-only or CAS-before-RAS) cycle.
test mode
The test mode is initiated with a CAS-before-RAS refresh cycle while simultaneously holding the W input low
(WCBR). The initiate cycle performs an internal refresh cycle while internally setting the device to perform
parallel read or write on subsequent cycles. While in test mode, any desired data sequence can be performed
on the device. The device exits the test mode if a CAS-before-RAS (CBR) refresh cycle with W input held high,
or a RAS-only refresh (ROR) cycle is performed.
Test mode causes the part to be internally reconfigured into a 1024K x 16 bit device with 16-bit parallel read
and write data path. Column addresses CAO, CA 1, CA10, and CA 11 are not used. During a read cycle all 16
bits of the internal data bus are compared. If all bits are the same data state, the output pin will go high. If one
or more bits disagree, the output pin will go low. Test time in test mode can thus be reduced by a factor of 16,
compared to normal memory mode.
I+-
I
I
I
I
Entry
Cycle
---.I
~
.I
14--
Test Mode Cycle
I
I
I
I
Exit
Cycle
--.I
14- Normal - .
I
Mode
VIH
RAS
NIL
VIH
CAS
VIL
W~
/
~~
I
11\
VIH
VIL
t The states of W. Data-in, and Address are defined by the type of cycle used during test mode.
Figure 1. Test Mode Cyelet
TEXAS .."
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
4-183
TMS416100
16 777 216·81T
DYNAMIC RANDOM·ACCESS MEMORY
SMKS610B-NOVEMBER 199~EVISED JANUARY 1993
logicsymbol t
RAM 16 384K x 1
AO
A1
A2
A3
A4
AS
A6
A7
A8
A9
A10
A11
10
30012/2100
11
12
13
16
17
0
A 16 383K
18
19
20
23
9
6
31023/21011
I"-
5
~
I'-.
25
w
o
4
2
~
C30[ROW]
G33 [REFRESH ROW]
34 [PWR OWN]
C311COL]
G34
&
> 33C32
~ 33,310
34 EN
2 70
AV
A, 320
tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
The pin numbers shown are for the 24/28 pin SOJ package (DZ suffix) and the 24/28-pin thin SOP package (DGC suffix).
functional block diagram
8
AO
A1
Column Oecode
Sense Amplifiers
256KArray
256KArray
256KArray
A11
256KArray
•
•
••
0
G>
"
Q
0
~
0
a:
4
256KArray
TEXAS
~
INSTRUMENTS
4-184
0
•
G>
."
POST OFFICE BOX 1443 • HOUSTON. TEXAS 17001
TMS416100
16777216-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SMKS610B-NOVEMBER 1990--REVISED JANUARY 1993
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Voltage range on any pin (see Note1) ................................................. -1 V to 7 V
Voltage range, Vee ................................................................. -1 V to 7 V
Short circuit output current ...................... ~ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 50 mA
Power dissipation .......................................................................... 1 W
Operating free-air temperature range .................................................. ooe to 70°C
Storage temperature range ....................................................... - 55°C to 125°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. This is a stress rating only, and
functional operation of the device at these or any other conditions beyond those indicated in the "recommended operating conditions" section
of this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values in this data sheet are with respect to VSS.
recommended operating conditions
MIN
NOM
MAX
VCC
Supply voltage
4.5
5
5.5
V
VIH
High-level input voltage
2.4
6.5
V
VIL
Low-level input voltage (see Note 2)
-1
0.8
V
TA
Operating free-air temperature
0
70
'c
..
..
..
UNIT
NOTE 2: The algebraic convention, where the more negative (less pOSItive) limit IS designated as minimUm, IS used In thiS data sheet for logic
voltage levels only.
electrical characteristics over full ranges of recommended operating conditions (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
VOH
High-level output voltage
10H =-5 mA
VOL
Low-level output voltage
IOL=4.2 mA
II
Input current (leakage)
10
ICC1
ICC2
TMS416100-60
MIN
MAX
2.4
TMS4161 00-70
MIN
MAX
2.4
TMS4161 00-80
MIN
MAX
2.4
UNIT
V
0.4
0.4
0.4
V
VI = 0 to 6.5 V,
All other pins = 0 V to VCC
±10
±10
±10
flA
Output current (leakage)
VO=OtoVCC,
CAS high
±10
±10
±10
flA
Read or write cycle current
(see Notes 3 and 5)
Minimum cycle,
VCC =5.5V
90
80
70
mA
After 1 memory cycle,
RAS and CAS high,
VIH = 2.4 V (TTL)
2
2
2
mA
After 1 memory cycle,
RAS and CAS high,
VIH = VCC -0.2 V (CMOS)
1
1
1
mA
Standby current
ICC3
Average refresh current
(RAS-only or CBR)
(see Notes 3 and 5):1:
RAS cycling, CAS high
(RAS-only); RAS low after
CAS low (CBR)
90
80
70
mA
ICC4
Average page current
(see Notes 4 and 5):1:
RAS low, CAS cycling
70
60
50
mA
ICC7
Standby current
output enable (see Note 5):1:
RAS = VIH, CAS = VIL,
Data out = enabled
5
5
5
mA
:I: Minimum cycle, VCC = 5.5 V.
NOTES:
3. Measured with a maximum of one address change while RAS = VIL.
4. Measured with a maximum of one address change while CAS = VIH.
5. Measured with no load connected.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS ~7001
4-185
TMS416100
16 777 216-61T
DYNAMIC RANDOM-ACCESS MEMORY
SMKS61 OB-NOVEMBER 199G-REVISED JANUARY 1993
capacitance over recommended ranges of supply voltage and operating free-air temperature,
f 1 MHz (see Note 6)
=
PARAMETER
MIN
TYP
MAX
UNIT
Cl{/l}
Input capacitance, address inputs
5
pF
Ci(D)
Input capacitance, data inputs
5
pF
Ci(RC)
Input capacitance, strobe inputs
7
pF
C.i(W)
Input capacitance, write-enable input
7
pF
Co
Output capacitance
7
pF
NOTE 6: VCC equal to 5 V ± 0,5 V and the bias on pins undertest
IS
0 V.
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature
TMS4161 00-60
PARAMETER
MIN
MAX
TMS4161 00-70
MIN
MAX
TMS4161 00-80
MIN
MAX
UNIT
tM
Access time from column-address
30
35
40
ns
tCAC
Access time from CAS low
15
18
20
ns
tCPA
Access time from column precharge
35
40
45
ns
tRAC
Access time from RAS low
60
70
80
ns
tCLZ
CAS to output in low Z
0
0
0
tOH
Output disable start of CAS high
3
3
3
toFF
Output disable time after CAS high
(see Note 7)
0
15
NOTE 7: tOFF is specified when the output is no longer driven.
TEXAS ~
INSTRUMENTS
4-186
POST OFFICE BOX 1443· HOUSTON. TEXAS 77001
0
18
0
ns
ns
20
ns
TMS416100
16 777 216·81T
DYNAMIC RANDOM·ACCESS MEMORY
SMKS61 OB-NOVEMBER 1990-REVISED JANUARY 1993
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
TMS416100-60
MIN
MAX
TMS4161 00-70
TMS4161 00-80
MIN
MIN
MAX
MAX
UNIT
tRC
Random read or write cycle (see Note 8)
110
130
150
ns
tRWC
Read-write cycle time
130
153
175
ns
tpc
Page-mode read or write cycle time (see Note 9)
40
45
50
ns
tpRWC
Page-mode read-write cycle time
60
68
75
tRASP
Page-mode pulse duration, RAS low (see Note 10)
60
100 000
70
100 000
80
100 000
ns
tRAS
Non-page-mode pulse duration, RAS low (see Note 10)
60
10 000
70
10000
80
10 000
ns
tCAS
Pulse duration, CAS low (see Note 11)
15
10 000
18
10 000
20
10 000
ns
tcp
Pulse duration, CAS high
10
10
10
ns
tRP
Pulse duration, RAS high (precharge)
40
50
60
ns
twp
Write pulse duration
15
15
15
ns
tASC
Column-address setup time before CAS low
Row-address setup time before RAS low
tos
Data setup time (see Note 12)
tRCS
Read setup time before CAS low
0
a
a
a
a
a
a
a
a
ns
tASR
a
a
a
leWL
W low setup time before CAS high
15
18
20
ns
tRWL
W low setup time before RAS high
15
18
20
ns
twcs
W low setup time before CAS low (Early write operation only)
a
a
a
ns
twSR
W high setup time (CAS-before-RAS refresh only)
10
10
10
ns
twrs
W low setup time (test mode only)
10
10
10
ns
leAH
Column-address hold time after CAS low
10
15
15
ns
tOH
Data hold time (see Note 11)
10
15
15
ns
tRAH
Row-address hold time after RAS low
10
10
10
ns
tRCH
Read hold time after CAS high (see Note 13)
a
0
a
ns
tRRH
Read hold time after RAS high (see Note 13)
5
5
5
ns
twCH
Write hold time after CAS low (Early write operation only)
15
15
15
ns
twHR
W high hold time (CAS-before-RAS refresh only)
10
10
10
ns
twrH
W low hold time (test mode only)
10
10
10
ns
ns
ns
ns
ns
Continued next page.
NOTES: 8. All cycle times assume tT = 5 ns.
9. To assure tpc min, tASC should be greater than or equal to tcp·
10. In a read-write cycle, tRWO and tRWL must be observed.
11. In a read-write cycle, tcwo and tCWL must be observed.
12. Referenced to the later of CAS or IN in write operations.
13. EHher tRRH or tRCH must be satisfied for a read cycle.
TEXAS
~
INBrRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
4-187
TMS416100
16777 216-81T
DYNAMIC RANDOM-ACCESS MEMORY
SMKS610B-NOVEMBER 199O-REVISED JANUARY 1993
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (continued)
TMS4161 00-60
MIN
MAX
TMS416100-70
TMS4161 00-80
MIN
MIN
MAX
MAX
UNIT
tAWD
Delay time, column address to W low
(Read-write operation only)
30
35
40
ns
tCHR
~ time, RAS low to CAS high
(CAS-before-RAS refresh only)
20
20
20
ns
tcRP
Delay time, CAS high to RAS low
5
5
5
ns
tCSH
Delay time, RAS low to CAS high
60
70
80
ns
tcSR
time, CAS low to RAS low
(CAS-before-RAS refresh only)
to
10
10
ns
~
tCWD
Delay time, CAS low to W low (Read-write operation only)
15
tRAD
Delay time, RAS low to column-address (see Note 14)
15
tRAl
Delay lime, column-address to RAS high
30
35
40
ICAl
Delay lime, column address 10 CAS high
30
35
40
tRCD
Delay lime, RAS low 10 CAS low (see Note 14)
20
tRPC
Delay lime, RAS high to CAS low
0
0
0
ns
IRSH
Delay time, CAS low to RAS high
15
18
20
ns
18
30
45
15
20
20
35
52
15
20
ns
40
ns
ns
ns
60
ns
tRWD
Delay lime, RAS low to W low (Read-write operation only)
60
70
80
ns
tcPRH
RAS hold lime form CAS precharge
35
40
45
ns
tcpw
Delay time, W from CAS precharge
35
40
45
ns
trAA
Access time from address (lest mode)
35
40
45
ns
trCPA
Access time from column precharge (test mode)
40
45
50
ns
trRAC
Access time from RAS (test mode)
65
75
85
tREF
Refresh time Interval
tr
Transition time
NOTE 14: The maximum value
64
3
IS
30
64
3
30
3
ns
64
ms
30
ns
specified only to assure access time.
PARAMETER MEASUREMENT INFORMATION
1.31 V
~
Output Under Test
VCC=5V
~
CL=100pF
R1 = 828 Q
RL=218Q
Output Under Test - -.....- -.....
T
(a) Load Circuit
(b) Alternate Load Clrcul,t
Figure 2. Load Circuits for Timing Parameters
TEXAS
~
INSIRUMENTS
4-188
POST OFFICE BOX 1443 • HOUSTON. TEXAS nCOl
TMS416100
16777216·8IT
DYNAMIC RANDOM·ACCESS MEMORY
SMKS61 OB-NOVEMBER 199Q-REVISED JANUARY 1993
PARAMETER MEASUREMENT INFORMATION
NOTE A: Output may go from three-state to an invalid data state prior to the specified access time.
Figure 3. Read Cycle Timing
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
4-189
TMS416100
16 777 216·81T
DYNAMIC RANDOM·ACCESS MEMORY
SMKS61 OS-NOVEMBER 199Q-REVISED JANUARY 1993
PARAMETER MEASUREMENT INFORMATION
·1
1
1
tRP
tCRP
~1
VIH
VIL
.1
~VIH
tcp
J
VIL
Q ----------------HI-Z ---------------
VOL
Figure 4. Early Write Cycle Timing
TEXAS
~
INSTRUMENTS
4-190
POST OFFICE BOX 1443· HOUSTON, TEXAS 77001
1MS416100
16 777 216·811
DYNAMIC RANDOM·ACCESS MEMORY
SMKS61 DB-NOVEMBER 1990-REVISED JANUARY 1993
PARAMETER MEASUREMENT INFORMATION
.-----------------------tRc----------------------~~
1
~------------tRAS--------------.~1
1
1
1
l\O------------------~11.~--tRP
------.t~I....--14104------ tRSH ------..
~
:
i4---
tRCO - -..
~I
~
11404+1_____ tCRP ____---I~~I
1
~I I 1
~I I
tCAS
14------------ tCSH
-+I
1
1
I
I
_t---~~
n:~:i===~~~~t-c-P----....~ :::
-+-,- tCAL
~1 1 1
I+-----i-I
III
~/7WW7
tCWL
::~
~~t~~'-______ :::
Column
:04
104
W~~2RE_*-1
tRWL
1 1I
1 I~I
~~1~:::
--+J
*-tOH -.!
1 1
1 1
1
1 1
I.-!--
twp
I
va:"doata
tCLZ 104
~I
11
Q
1 11
1 1~I
1 11
1 - tRAL
!4-----+1-I1 1
1 ~tCAH
:
:::
-------------------<~
~*gX*Z~VIH
1
VIL
1
1 ro4~ tOFF
I0Il:--
Not Valid
tOH
Jr-- - - - - - - - - -
VOH
VOL
Figure 5. Write Cycle Timing
TEXAS ~
INsrRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
4-191
TMS416100
16777216·8IT
DYNAMIC RANDOM·ACCESS MEMORY
SMKS61 OB-NOVEMBER 1990-REVISED JANUARY 1993
PARAMETER MEASUREMENT INFORMATION
NOTE A: Output may go from three-state to an invalid data state prior to the specified access time.
Figure 6. Read-Write Cycle Timing
TEXAS ~
INSTRUMENTS
4-192
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1MS416100
16777216-BI1
DYNAMIC RANDOM-ACCESS MEMORY
SMKS610B-NOVEMBER 1990-REVISED JANUARY 1993
PARAMETER MEASUREMENT INFORMATION
AD-A11
- 'fXI.XXI/ I
I
W ~ *-tRAD~
I
I
I
L.
_
Q
:1
WXI
wy
::
W
I
I
VIH
'(iVIL
I
I
..
04'----- tCPA ---+I----i.~1
I
tCAC ~
(see Note B)
I
I
..
104f---+-!-tAA
.1
~I tOFF~
tRAC
.1
tCLZ".I~
I
I
*--
_ _ _ _ _ _ _ _ _ _-:-:---:-::---'.
(see Note A)
I
Valid
Out
I.
~
~
voaulltd
~ VOH
/
VOL
NOTES: A. Output may go from three-state to an invalid data state prior to the specified access time.
B. Access time is tCPA or tAA dependent.
Figure 7. Enhanced Page-Mode Read Cycle Timing
TEXAS ~
INSTRUMENTS
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4-193
TMS416100
16 777 216·81T
DYNAMIC RANDOM·ACCESS MEMORY
SMKS61 OS-NOVEMBER 199Q-REVISED JANUARY 1993
PARAMETER MEASUREMENT INFORMATION
tRP
~
I
I"II
I I
14
I
.1
tCSH
I ~ tRCD ------..
I
I
I
I
I
I
I
Vi
I
j4- tRAH
I
I
1+---1.~I-11
AD-All
!
tASC~\
:\.
+1
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I!;
Don't Care
.1
tpc
I
_I
___ t
..I
I~
I
VIL
+------+I
/1
RSH
N
I
YT
I
I
I
~tCRP-+I
I
I
I.- tcp -.!
I
--t-I-----VIH
I
I
VIL
I
I-
I I
I+- tCAH ~I
_--.:.....---.;. _. . . . . ._--...1......
tASR
~
tCPRH
I
14- tCAS ~ I
I
I
I
I
I0Il
I
I
~fi\-I
.
VIH
tRASP
14
tRAL
I
l.--tCAL
.1
I
J'.~="=~~~VIH
IV\./V'VV".
~~~~(S~e~e*No~t~e¥~~~~~~-~~~~~~~~~~L--~~~~~~~~~VIL
I
I
1OII14f--- tDS ----.!.I
~~----tDS---~
I
(see Note A)
o
~~--~--v~a-lid-Da-t-a-In-~----~
Q
-----------------HI-Z ----------------
VOH
VOL
NOTES: A. Referenced to CAS or W, whichever occurs last.
B. A read cycle or a read-write cycle can be intermixed with write cycles as long as read and read-write timing specifications are not
violated.
Figure 8. Enhanced Page-Mode Write Cycle Timing
TEXAS
~
INSTRUMENTS
4-194
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TMS416100
16 777 216·BIT
DYNAMIC RANDOM·ACCESS MEMORY
SMKS61 OB-NOVEMBER 199G--REVISED JANUARY 1993
PARAMETER MEASUREMENT INFORMATION
VIH
AD-All
VIH
o
I
I
j+tCAC
~tAA I
..----
i~
tRAC:
(see Note A)
tCLZ~
+i
.1
.1
i+--_...J.:-1+
VIL
tCPA - - - + I
tcLZ
1
-.1
1
(see Note A)
~-........+-I-
tOFF
:
VOH
Q
VOL
NOTES: A. Output may go from three-state to an invalid data state prior to the specified access time.
B. A read or write cycle can be intermixed with read-write cycles as long as the read and write timing specifications are not violated.
Figure 9. Enhanced Page-Mode Read-Write Cycle Timing
TEXAS ~
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4-195
TMS416100
16 777 216-81T
DYNAMIC RANDOM-ACCESS MEMORY
SMKS61 OS-NOVEMBER 199O-REVISED JANUARY 1993
PARAMETER MEASUREMENT INFORMATION
Q--------------------------------------------------------------------------------------Figure 10. RAS·Only Refresh Timing
TEXAS ~
INsrRUMENTS
4-196
POST OFFICE BOX 1443' HOUSTON, TEXAS 77001
VOH
TMS416100
16 777 216·BIT
DYNAMIC RANDOM·ACCESS MEMORY
SMKS610B-NOVEMBER 199O-REVISED JANUARY 1993
PARAMETER MEASUREMENT INFORMATION
1~~---------------------tRC------------------~
·1
I+-- tRP ~ 1~~-----------tRAS ____________~
·1
1
RAS
AI
tRPC -
CAS
_I
1
1 1
1 1
N
1
Y
I~----------------------~
j+-tCSR~ 1
~
1 1 4 4 - - - - tCHR
~rtr
••
W~
....
·1
VIL
.1
y
twSR~I'III;:::= ltil_:---:-------~
'i
VIH
twHR
VIH
VIL
V
IH
VIL
D
~:e~1::~aX~:~V'H
VIL
Q ---------------HI·Z---------------
VOH
VOL
Figure 11. Automatic (CAS·Before·RAS) Refresh Cycle TIming
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
4·197
TMS416100
16 777 216·81T
DYNAMIC RANDOM·ACCESS MEMORY
SMKS61 OB-NOVEMBER 199O-AEVISED JANUARY 1993
PARAMETER MEASUREMENT INFORMATION
Figure 12. Hidden Refresh Cycle (Read) Timing
TEXAS ~
INsrRUMENTS
4-198
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TMS416100
16777 216·81T
DYNAMIC RANDOM·ACCESS MEMORY
SMKS61 OB-NOVEMBER 1990--REVISED JANUARY 1993
PARAMETER MEASUREMENT INFORMATION
~VIH
V,L
Q - - - - - - - - - - - HI-Z
-------------'l'/i-,- - - - - - - -
VOH
VOL
Figure 13. Hidden Refresh Cycle (Write) Timing
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
4-199
TMS416100
16 777 216-81T
DYNAMIC RANDOM·ACCESS MEMORY
SMKS610B-NOVEMBER 199O-REVISEDJANUARY 1993
PARAMETER MEASUREMENT INFORMATION
D~:~~~;~~*i~VIH
VIL
VOH
Q ---------------- HI-Z---------------
VOL
Figure 14. Test Mode Entry Cycle
VIL
VIL
AO-A11
Q
AAAAA~
c.\JDon'teare
- - - - - - - - - - - - HI-Z
)( )( V \/__ .
Figure 15. Test Mode Exit Cycle (CAS-Before-RAS Refresh Cycle)
TEXAS .."
INsrRUMENTS
4·200
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
VIL
TMS416100
16 777 216·BIT
DYNAMIC RANDOM·ACCESS MEMORY
SMKS61 OB-NOVEMBER 1990-REVISED JANUARY 1993
device symbolization
~
TI
P
TMS416100
'If-
A
P
T
-bf-
~
Speed
(~O,
-70, -80, -10)
Package Code
Lot Traceability Code
Month Code
Assembly Site Code
Ole Revision Code
Wafer Fab Code
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
4-201
TMS416100
16777216·81T
DYNAMIC RANDOM·ACCESS MEMORY
SMKS610B-NOVEMBER 199Q--REVISED JANUARY 1993
TEXAS ~
INSTRUMENTS
4·202
POST OFFICE BOX 1443· HOUSTON, TEXAS 77001
TMS416400
4 194 304·WORD BY 4·BIT
DYNAMIC RANDOM·ACCESS MEMORY
SMKS640B-NOVEMBER 1990-REVISED JANUARY 1993
This data sheet is applicable to al/ TMS416400s
symbolized with Revision '~" and subsequent
revisions as described on page 25.
•
•
•
DZPACKAGEt
(TOP VIEW)
Organization ... 4 194 304 x 4
Single S-V Power Supply (10% Tolerance)
•
•
VSS
DQ4
DQ3
CAS
W
Performance Ranges:
RAS
All
ACCESS ACCESS ACCESS READ
TIME
TIME
TIME OR WRITE
tRAC
tCAC
tAA
CYCLE
(MAX)
(MAX)
(MAX)
(MIN)
TMS416400-60
60ns
15ns
30ns
110ns
70ns
18ns
35ns
130ns
TMS416400-70
80 ns
20 ns
40 ns
150 ns
TMS416400-80
•
Vee
DQl
DQ2
A2
A3
Vee
Long Refresh Period ... 4096 Cycles
Refresh in 64 ms
3-State Unlatched Output
•
•
Low Power Dissipation
All Inputs, Outputs, and Clocks are'
TTL Compatible
•
Operating Free-Air Temperature Range
O°C to 70°C
AS
A7
A6
A5
A4
Al0
AO
Al
Enhanced Page Mode Operation for Faster
Memory Access
CAS-before-RAS Refresh
•
OE
A9
VSS
DGC PACKAGEt
(TOP VIEW)
DGD PACKAGEt
(TOP VIEW)
Vee
Vss
Vss
Vee
DQl
DQ2
DQ4
DQ3
CAS
DQ4
DQ3
CAS
DQl
DQ2
W
RAS
All
OE
OE
A9
A9
Al0
AO
Al
A2
A3
AS
A7
A6
A5
AS
A7
A6
A5
Vee
VSS
W
RAS
All
description
The TMS416400 series are high-speed
16 777 216-bit dynamic random-access memories, organized as 4 194 304-bit words by four bits
each. They employ state-of-the-art EPIC'·
(Enhanced Performance Implanted CMOS) technology for high performance, reliability, and low
power at a low cost.
These devices feature maximum RAS access
times of 60 ns, 70 ns, and 80 ns.
A4
A4
Al0
AO
Al
A2
A3
Vss
Vee
t The packages shown are for pinout reference only.
All inputs, outputs, and clocks, are compatible with
Series 74 TTL. All addresses and data-in lines are
latched on-chip to simplify system design. Data
out is unlatched to allow greater system flexibility.
The TMS416400 is offered in 400-mil 24/28-pin
surface mount SOJ (DZ suffix) and 400-mil
28/24-pin surface mount thin SOP (DGC and DGD
suffixes) packages. This device is characterized
for operation from O°C to 70°C.
PIN NOMENCLATURE
AD-All
eAS
DQ1-DQ4
OE
RAS
W
Vee
vss
"TEXAS ~
INsrRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
Address Inputs
Column-Address Strobe
Data In/Data Out
Output Enable
Row-Address Strobe
Write Enable
5-V Supply
Ground
Copyright © 1993. Texas Instruments Incorporated
4-203
TMS416400
4194 304·WORD BY 4·BIT
DYNAMIC RANDOM·ACCESS MEMORY
SMKS640B-NOVEMBER 199O--REVISED JANUARY 1993
operation
enhanced page mode
Page mode operation allows effectively faster memory access by keeping the same row address and strobing
random column addresses onto the chip. Thus, the time required to set up and strobe row addresses for the
same page is eliminated. The maximum number of columns that can be addressed is determined by tRAS, the
maximum RAS low width.
The Column Address Buffers in this CMOS device are activated on the falling edge of RAS. They act as a
transparent or flow-through latch, while CAS is high. The falling edge of CAS latches the addresses into these
buffers and also serves as an output enable.
This feature allows the TMS416400 to operate at a higher data bandwidth than conventional page-mode parts,
since retrieval begins as soon as the column address is valid, rather than when CAS transitions low. The
performance improvement is referred to as enhanced page mode. Valid column address may be presented
immediately after row address hold time has been satisfied, usually well in advance of the falling edge of CAS.
In this case, data is obtained after tCAC max (access time from CAS low), if tAA max (access time from column
address) and tRAS have been satisfied. In the event that the column address for the next cycle is valid at the
time CAS goes high, access time is determined by the later occurrence of tCPA or tCAC'
address (AO-A11)
Twenty-two address bits are required to decode 1 of 4 194 304 storage cell locations. Twelve row-address bits
are set on inputs AO through A 11 and latched onto the chip by the Row Address Strobe RAS. Ten
column-address bits are set on AO through A9. CA 10 and CA 11 are not used. Row address A 11 is required
during a normal access and during RAS only refresh as the device requires 4096 refresh cycles. All addresses
must be stable on or before the falling edges of RAS and CAS. RAS is similar to a chip enable in that it activates
the sense amplifiers as well as the row decoder. CAS is used as a chip select, activating the output buffer, as
well as latching the address bits into the coluliTln buffer.
write enable
rN>
The read or write mode is selected through the write-enable W input. A logic high on the W input selects the
read mode and a logic low selects the write mode. The write-enable terminal can be driven from standard TIL
circuits without a pullup resistor. The data input is disabled when the read mode is selected. When W goes low
prior to CAS (early write), data out will remain in the high-impedance state for the entire cycle permitting a write
operation independent of the state of OE: This permits early write operation to be completed with OE grounded.
data-in/data-out (OQ1-0Q4)
Data is written during a write or read-modify-write cycle. Depending on the mode of operation, the falling of CAS
or W strobes data into the on-Chip data latch. In the early-write cycle, W is brought low prior to CAS and data
is strobed in by CAS with setup and hold times referenced to this signal. In a delayed write or read-modify write
cycle, CAS will already be low, thus data will be strobed in by W with setup and hold times referenced to this
signal.
The three-state output buffer provides direct TIL compatibility (no pullup resistor required) with a fan-out of two
Series 74 TIL loads. The output is in the high-impedance (floating) state until CAS is brought low. In a read cycle
the output becomes valid at the latest occurrence of tRAC, tAA, tCAC, or tCPA and remains valid while CAS is low.
CAS going high returns it to a high-impedance state. In a delayed-write or read-modify-write cycle, the output
does not change, but retains the state just read.
TEXAS
~
INSTRUMENTS
4-204
POST OFFICE BOX 1443· HOUSTON. TEXAS 77001
TMS416400
4194 304·WORD BY 4·BIT
DYNAMIC RANDOM·ACCESS MEMORY
SMKS640B-NOVEMBER 1990-REVISED JANUARY 1993
output enable (OE)
DE controls the impedance of the output buffers. When DE is high, the buffers will remain in the high-impedance
state. Bringing DE low during a normal cycle will activate the output buffers putting them in the low-impedance
state. It is necessary for both RAS and CAS to be brought low for the output buffers to go into the low-impedance
state. Once in the low-impedance state, they will remain for the low-impedance state until either OE or CAS is
brought high.
refresh
A refresh operation must be performed at least once every sixty-four milliseconds to retain data. This can be
achieved by strobing each of the 4096 rows (AO--A 11). A normal read or write cycle will refresh all bits in each
row that is selected. A RAS-only operation can be used by holding CAS at a high (inactive) level, thus conserving
power since the output buffer remains in the high-impedance state. Externally generated addresses must be
used for a RAS-only refresh. Hidden refresh may be performed by holding CAS at VIL after a read operation
and cycling RAS after the specified precharge period, similar to a RAS-only refresh cycle except with CAS held
low. Valid data is maintained at the output throughout the hidden refresh cycle. An internal refresh address
provides the refresh address during hidden refresh.
CAS-before-RAS refresh
CAS-before-RAS refresh is utilized by bringing CAS low earlier than RAS (see parameter teSR) and holding it
low after RAS falls (see parameter teHR)' For successive CAS-before-RAS refresh cycles, CAS can remain low
while cycling RAS. For this mode of refresh, the external addresses are ignored and the refresh address is
generated internally.
power up
To achieve proper device operation, an initial pause of 200 !-Is followed by a minimum of eight initialization cycles
is required after full Vee level is achieved. These eight initialization cycles need to include at least one refresh
(RAS-only or CAS-before-RAS) cycle.
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
4-205
TMS416400
4194 304-WORD BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SMKS640B-NOVEMBER 199O-REVISED JANUARY 1993
test mode
The test mode is initiated with a CAS-before-RAS refresh cycle while simultaneously holding the W input low
(WCBR). The initiate cycle performs an internal refresh cycle while internally setting the device to perform
parallel read or write on subsequent cycles. While in test mode, any desired data sequence can be performed
on the device. The device exits test mode if a CAS-before-RAS (CBR) refresh cycle, with W input held high, or
a RAS-only refresh (ROR) cycle is performed.
The part is configured as 1024K x 4 x 4 bit device in test mode, where each DO pin has a separate 4-bit
parallel read and write data bus where CAO and CA 1 are ignored. During a read cycle, the 4 internal bits are
compared for each DQ pin separately. If the 4 bits agree, the DO pin will go high, if not, the DO pin will go low.
All 4 bits are written to the state of their respective DO pin during a parallel write. Thus, each DO pin is
independent of the other and any data pattern desired maybe written on each DO pin. Test time is thus reduced
by a factor of 4 for this series.
1<1114---~~1f- Entry Cycle
Exit Cycle ~141-----~~1
...
4,.------ Test Mode Cycle -------.!~I
1
1
1
1
1
i+- Normal
I
1
Mode
VIH
VIL
VIH
/
t The states of W, Data-in, and Address are defined by the type of cycle used during test mode.
Figure 1. Test Mode eyelet
TEXAS . "
INsrRUMENTS
4-206
POST OFFICE BOX 1443' HOUSTON. TEXAS 77001
TMS416400
4 194 304·WORD BY 4·BIT
DYNAMIC RANDOM·ACCESS MEMORY
SMKS640B-NOVEMBER 1990-REVISED JANUARY 1993
logic symbol t
AO
Al
A2
A3
A4
AS
A6
A7
A8
A9
Al0
All
RAM 4096Kx 4
10
20010/2100
11
12
13
16
17
18
19
20
0
A4194303
23
20019/2109
20020
9
6
20021
~
5
r--.
25
W
OE
001
D02
D03
D04
4
24
~
1
r---
2
3
26
27
4-
> C20[ROW]
G23/[fIEFRESH ROW]
24[PWR OWN]
C21[COLUMN]
G24
&
23,210
G25
> 23C22
24,25EN
r
I
A,220
'V 26
A,Z26
tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers are for the DZ package.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
4-207
TMS416400
4 194 304·WORD BY 4·BIT
DYNAMIC RANDOM·ACCESS MEMORY
SMKS640B--NOVEMBER 199o-REVISED JANUARY 1993
functional block diagram
I
,
AO
,,,,
Timing and Control
1
~
32,
/
A1
•
•
•
A11
Column
Address
Bufferst
2,
•
•
-
'--
256KArray
256KArray
••
•
32<
Row
Address
Buffers
/
11-"
t Column Address 10 and Column Address 11
256KArray
R
0
w
0
e
c
0
d
e
11
r--
~
Sense Amplifiers
~
L
•
Column Decode
256KArray
~
256KArray
••
•
> 32
2-256KArray
11
/
are not used.
TEXAS ~
INSfRUMENTS
4-208
I/O
Buffers
40f32
Selection
POST OFFICE BOX 1443· HOUSTON. TEXAS 77001
11-"
~
In
Reg.
~
Out
Reg.
OQ1 -OQ4
TMS416400
4194 304-WORD BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SMKS640B-NOVEMBER 1990-REVISED JANUARY 1993
absolute maximum ratings over operating free-air temperature t
Voltage on any pin (see Note 1) ....................................................... - 1 V to 7 V
Voltage range on Vee . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 1 V to 7 V
Short circuit output current ................................................................ 50 mA
Power dissipation .......................................................................... 1 W
Operating free-air temperature range .................................................. O°C to 70°C
Storage temperature range ....................................................... - 55°C to 125°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maxim urn-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values in this data sheet are with respect to VSS.
recommended operating conditions
MIN
NOM
MAX
VCC
Supply voltage
4.5
5
5.5
UNIT
V
VIH
High-level input voltage
2.4
6.5
V
VIL
Low-level input vo~age (see Note 2)
-1
O.B
V
TA
Operating free-air temperature
0
70
°c
NOTE 2: Then algebraic convention, where the more negative (less positive) limit is designated as minimum, is used in this data sheet for logic
voltage levels only.
electrical characteristics over full ranges of recommended operating conditions (unless otherwise
noted)
PARAMETER
TEST
CONDITIONS
VOH
High-level output voltage
10H =-5 rnA
VOL
Low-level output voltage
IOL=4.2 rnA
II
TMS416400-60
MIN
MAX
2.4
TMS416400-70
MIN
MAX
2.4
TMS416400-BO
MIN
MAX
2.4
UNIT
V
0.4
0.4
0.4
Input current (Ieakage)*
VI = 0 to 6.5 V,
All other pins = 0 V to
VCC
V
±10
±10
±10
~A
10
Output current (Ieakage)*
Va = Oto VCC,
CAS high
±10
±10
±10
~
ICCl
Read or write cycle current
(see Notes 3 and 5)
Minimum cycle,
VCC =5.5V
90
BO
70
rnA
After 1 memory cycle,
RAS and CAS high,
VIH 2.4 V (TTL)
2
2
2
mA
After 1 memory cycle,
RAS and CAS high,
VIH VCC - 0.05 V
(CMOS)
1
1
1
rnA
=
ICC2
Standby current
=
ICC3
Average refresh current (RAS-only or
CBR) (see Notes 3 and 5)*
RAS cycling CAS high
(RAS-only), RAS low
after CAS low (CBR)
90
80
70
mA
ICC4
Average page current
(see Notes 4 and 5)*
RAS low, CAS cycling
70
60
50
mA
ICC7
Standby current output enable*
(see Note 5)
RAS VIH, CAS VIL,
Data out = enabled
5
5
5
mA
=
=
* Minimum cycle, VCC = 5.5 V.
NOTES: 3. Measured with a maximum of one address change while RAS = VIL.
4. Measured with a maximum of one adddress change while CAS = VIH.
5. Measured with no load connected.
TEXAS ~
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POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
4-209
TMS416400
4 194 304·WORD BY 4·BIT
DYNAMIC RANDOM·ACCESS MEMORY
SMKS640B--NOVEMBER 199Q-REVISED JANUARY 1993
.
capacitance over recommended ranges of supply voltage and operating free-air temperature,
f = 1 MHz (see Note 6)
PARAMETER
MIN
TYP
MAX
UNIT
Ci(A)
Input capacitance, address inputs
5
Ci(RC)
Input capacitance, strobe inputs
7
pF
pF
Ci(OE)
Input capacitance, output enable
7
pF
Ci(W)
Input capacitance, write-enable input
7
pF
Co
Output capacitance
7
pF
NOTE 6: VCC equal to 5.0 V
±
0.5 V and the bias on pins under test is 0 V.
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature
PARAMETER
TMS416400-60
TMS416400-70
TMS416400-80
MIN
MIN
MIN
MAX
MAX
MAX
UNIT
tAA
Access time from column-address
30
35
40
ns
tCAC
Access time from CAS low
15
18
20
ns
tCPA
Access time from column precharge
35
40
45
ns
tRAC
Access time from RAS low
60
70
80
ns
toEA
Access time from OE low
tCLZ
CAS to output in low Z
20
18
15
0
0
ns
0
ns
ns
toH
Output disable start of CAS high
3
3
3
tOHO
Output disable time start of OE high
3
3
3
tOFF
Output disable time after CAS high
(see Note 7)
0
15
0
18
0
20
ns
tOEZ
Output disable time after OE high
(see Note 7)
0
15
0
18
0
20
ns
NOTE 7: tOFF is specified when the output is no longer driven.
TEXAS ~
INsrRUMENTS
4-210
POST OFFICE BOX 1443· HOUSTON, TEXAS 77001
ns
TMS416400
4194 304·WORD BY 4·BIT
DYNAMIC RANDOM·ACCESS MEMORY
SMKS640B-NOVEMBER 199Q-REVISED JANUARY 1993
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
TMS416400-60
MIN
MAX
TMS416400·70
TMS416400·80
MIN
MIN
MAX
MAX
UNIT
tRC
Random read or write cycle (see Note 8)
110
130
150
ns
tRWC
Read-write cycle time
155
181
205
ns
tpc
Page-mode read or write cycle time (see Note 9)
40
45
50
ns
tPRWC
Page-mode read-write cycle time
85
96
105
tRASP
Page-mode pulse duration, RAS low (see Note 10)
60
100000
70
100000
80
100000
tRAS
Non-page-mode pulse duration, RAS low (see Note 10)
60
10000
70
10 000
80
10 000
ns
tCAS
Pulse duration, CAS low (see Note 11)
15
10000
18
10000
20
10 000
ns
tcp
Pulse duration, CAS high
10
10
10
ns
tRP
Pulse duration, RAS high (precharge)
40
50
60
ns
twP
Write pulse duration
15
15
15
ns
tASC
Column-address setup time before CAS low
0
0
0
ns
tASR
Row-address setup time before RAS low
0
0
0
ns
tDS
Data setup time (see Note 12)
0
0
0
ns
tRCS
Read setup before CAS low
0
0
0
ns
ns
ns
tCWL
W low setup time before CAS high
15
18
20
ns
tRWL
W low setup time before RAS high
15
18
20
ns
twcs
W low setup time before CAS low
(Early write operation only)
0
0
0
ns
twSR
W high setup time (CAS-before-RAS refresh only)
10
10
10
ns
twTs
W low setup time (test-mode only)
10
10
10
ns
tCAH
Column-address hold time after CAS low
10
15
15
ns
tDH
Data hold time (see Note 12)
10
15
15
ns
tRAH
Row-address hold time after RAS low
10
10
10
ns
tRCH
Read hold time after CAS high (see Note 13)
0
0
0
ns
tRRH
Read hold time after RAS high (see Note 13)
5
5
5
ns
tWCH
Write hold time after CAS low (Early write operation only)
15
15
15
ns
twHR
W high hold time (CAS-before-RAS refresh only)
10
10
10
ns
twTH
W low hold time (test mode only)
10
10
10
ns
Continued next page,
NOTES: 8, All cycle times assume IT = 5 ns.
9. To assure tpc min, tASC should be greater than or equal to tcP.
10, In a read-write cycle, tRWD and tRWL must be observed.
11. In a read-write cycle, tCWD and tCWL must be observed.
12, Referenced to the later of CAS or Win write operations.
13. Either tRRH or tRCH must be satisfied for a read cycle.
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443· HOUSTON. TEXAS 77001
4-211
TMS416400
4194 304·WORD BY 4·BIT
DYNAMIC RANDOM·ACCESS MEMORY
SMKS640B-NOVEMBER 1990-REVISED JANUARY 1993
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (concluded)
TMS416400-60
MIN
MAX
TMS416400-70
MIN
MAX
TMS416400-80
MIN
MAX
UNIT
tAWD
Delay time, column address to W low
(Read-write operation only)
55
63
70
ns
tCHR
Delay time, RAS low to CAS high
(CAS-before-RAS refresh only)
20
20
20
ns
tCRP
Delay time, CAS high to RAS low
5
5
5
ns
tCSH
Delay time, RAS low to CAS high
60
70
80
ns
tCSR
Delay time, CAS low to RAS low
(CAS-before-RAS refresh only)
10
10
10
ns
tCWD
Delay time, CAS low to W low (Read-write operation only)
40
46
50
ns
tOEH
OE command hold time
15
18
20
ns
tOED
OE to data delay
15
18
20
ns
tROH
RAS hold time referenced to OE
10
10
10
tRAD
Delay time, RAS low to column-address (see Note 14)
15
tRAl
Delay time, column-address to RAS high
30
35
40
tCAl
Delay time, column-address to CAS high
30
35
40
tRCD
Delay time, RAS low to CAS low (see Note 14)
20
tRPC
Delay time, RAS high to CAS low
0
0
0
ns
tRSH
Delay time, CAS low to RAS high
15
18
20
ns
tRWD
Delay time, RAS low to W low (Read-write operation only)
85
98
110
ns
tCPRH
RAS hold time from CAS precharge
35
40
45
ns
30
45
15
20
35
52
15
20
ns
40"
ns
ns
ns
60
ns
tcpw
Delay time, W from CAS precharge
60
68
75
ns
ITAA
Access time from add ress (test mode)
35
40
45
ns
ITCPA
Access time from column precharge (test mode)
40
45
50
ns
ITRAC
Access time from RAS{ test mode)
65
75
85
tREF
Refresh time interval
IT
Transition time
3
30
NOTE 14: The maximum value is specified only to assure access time.
TEXAS ~
INSTRUMENTS
4-212
64
64
POST OFFICE BOX 1443· HOUSTON, TEXAS 77001
3
30
3
ns
64
ms
30
ns
TMS416400
4 194 304·WORD BY 4·BIT
DYNAMIC RANDOM·ACCESS MEMORY
SMKS640B-NOVEMBER 1990-REVISED JANUARY 1993
PARAMETER MEASUREMENT INFORMATION
1.31 V
~
VCC =5V
= 21B Q
Rl
~
Output Under Test
Cl=100pF
Output Under Test - - . . . - - - .
T
Cl=100pF
(a) load Circuit
(b) Alternate load Circuit
Figure 2. Load Circuits for Timing Parameters
I"
.1
tRC
: 1-4.
N
~ J.'
~
.!r ~ tRP ---.! ,
tRAS
~ ~1OIII--lT----------~'
,
,
,..
,
,
,..
,
1
'
~
1
,
,
1
."
,
*---tRCD~
,~
,I
,
tCAS
I_
'..
-.I
., tRAD
t
1
'
,
I
tOIII~
I
'
i
, '------- Vil
:
"
,
tRSH~!
Ni~
tASR
I
I'
1
tCSH
~¥11~,! I
\
.
i
------t~ , ' - - - - ,
1 ,
tCAl
I..
1I
t
'
tcp
tASC
RAIjI..
~tCRP--"
1
'
,
'
1 , ,
,
,
,
,
1 ,
,
.,
,
VIH
Vil
1.1 ,
AO~"~ ~ CoI'~": ~~~}~'---____ ~::
,_:
, tRCS
~
11
U
.1 1 1
--!j
~tCAH
1 I i+' !+- tRRH
I 1"1 ~
NOTE A: Output may go from three-state to an invalid data state prior to the specified access time.
Figure 3. Read Cycle Timing
TEXAS
~
INSTRUMENTS
POST OFfiCE BOX 1443 • HOUSTON, TEXAS 77001
4-213
TMS416400
4194 304·WORD BY 4·BIT
DYNAMIC RANDOM·ACCESS MEMORY
SMKS640B-NOVEMBER 1990--f!EVISED JANUARY 1993
PARAMETER MEASUREMENT INFORMATION
Figure 4. Early Write Cycle Timing
TEXAS ~
INSTRUMENTS
4-214
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
TMS416400
4194 304-WORD BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SMKS640B-NOVEMBER 199O-REVISED JANUARY 1993
PARAMETER MEASUREMENT INFORMATION
Figure 5. Write Cycle Timing
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
4-215
TMS416400
4 194 304~WORD BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SMKS640B-NOVEMBER 199O-REVISED JANUARY 1993
PARAMETER MEASUREMENT INFORMATION
CAS
~
I
I
I
I
AO-A11ID{
NOTE A: Output may go from three-state to an invalid data state prior to the specified access time.
Figure 6. Read-Write Cycle Timing
TEXAS
~
INSfRUMENTS
4-216
POST OFFICE BOX 1443· HOUSTON. TEXAS nOO1
TMS416400
4194 304-WORD BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SMKS640B-NOVEMBER 1990-REVISED JANUARY 1993
PARAMETER MEASUREMENT INFORMATION
A0-11
- XXf.XX!/ I
W'i:£££i/
I
*- tRAD -+i
I
1
1
I
I
I..
:1
1
I.,.
w:n
W
1oiIL.r------ tRAc
(see Note B)
tAA·1
.1
1_
tCLZ~
1
tCPA
~tCAC~
1
I
1 ~I
I 1 I
I ~H
_~_ _~~
DQ1-DQ4---------(-Se-e-N-ot-e-A-)
I
VIH
VIL
i.. '~ : tOFF~
.l~~
I
w~
::
filii--*- tOHO
~ I+- tOEZ
~I
~~~
tOHo
~
1 tOEzl
OE~~*2~~~tOEA~ ~tOEA~
~
>-
.1
~
VOH
VOL
~VIH
VIL
NOTES: A. Output may go from three-state to an invalid data state prior to the specified access time.
B. Access time is tCPA or tAA dependent.
Figure 7. Enhanced Page-Mode Read Cycle Timing
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
4-217
TMS416400
4 194 304-WORD BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SMKS640B-NOVEMBER 199G-REVISED JANUARY 1993
PARAMETER MEASUREMENT INFORMATION
tRP
Ii
1'4
:
~
~I
tCSH
I 14--- tRCD -----.
~ tCAS
I I
tASC~\l
:I
I 1+
I I
tRAH
I:I--I·~I-I tASR
+i I
1 I
1 I
I"
tCPRH
:;
tpC·
J1 II
0
~
~I
~~I
1
VIH
tRASP
~I
.1
~
I
.I
~ tR~H:" ~fCRP -------.I
~ tCAL
:N
VI:
VIL
;.-1_..,.1_ _ _ _ __
I I I * - tcp I--.,!
I
1 1
1 1
I..
tRAL
~I
1 j:I- tCAH
zl_ _ _ _ _"--""
VIH
VIL
AO-A11
NOTES: A. Referenced to CAS or W, whichever occurs last.
B. A read cycle or a read·write cycle can be intermixed with write cycle as long,as read and read·write timing specifications are not
violated.
Figure 8. Enhanced Page-Mode Write Cycle Timing
TEXAS
~
IN8rRUMENTS
4·218
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
TMS416400
4194 304·WORD BY 4·BIT
DYNAMIC RANDOM·ACCESS MEMORY
SMKS640B-NOVEMBER 1990-REVISED JANUARY 1993
PARAMETER MEASUREMENT INFORMATION
tRP~
RAS ~
~
tRAsP-----------.~ VIH
_
----=~
_=__=__=_-_-_-_-_-~
...:-:II.I....-=====-;:t::::-::=====
;jl
...
I
VIL
II l:1
66<)[. .
1""- tOHO
~
~~~~~=VIL
I II I
. I I.,
~ I ~ tRCS
I~ I .1 tAA
tRAC I,~
t.-
--.
*--
~
--.I I.-l
:
-'y! /l1'i-------.i\.J"-
\XXXXXXXXXXXX
NOTES: A. Output may go from three-state to an invalid data state prior to the specified access time.
B. A read or write cycle can be intermixed with read-write cycles as long as the read and write timing specifications are not violated.
Figure 9. Enhanced Page-Mode Read-Write Cycle Timing
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
4-219
TMS416400
4194 304·WORD BY 4·BIT
DYNAMIC RANDOM·ACCESS MEMORY
SMKS640B-NOVEMBER 1990-REVISED JANUARY 1993
PARAMETER MEASUREMENT INFORMATION
Figure 10. RAS-Only Refresh Timing
TEXAS
"tJ
INsrRUMENTS
4-220
POST OFFICE BOX 1443· HOUSTON, TEXAS nOOl
TMS416400
4 194 304·WORD BY 4·BIT
DYNAMIC RANDOM·ACCESS MEMORY
SMKS640B-NOVEMBER 1990-REVISED JANUARY 1993
~14~-------------------tRC------------------~
I
-J;1
~~I____________________________~
RAS ____
I
tRPC -
.1
·1
I
1
i"'II4----------- tRAS _ _ _ _ _ _ _~
·1
1 1
1
I+-- tRP -----+!
Y
1 1
!+-tCSR~ 1
\{ ir
~
1
VIH
VIL
.1
1 4 4 - - - - tCHR
JI
twsR~I4~=:;.rltL..-=--=--=--=-::--------------..,;jI
1
w~
VIH
tr
·1
VIL
V
twHR
IH
VIL
VIH
O Q 1 - 0 Q 4 - - - - - - - - - - - - - - - - HI-Z - - - - - - - - - - - - - - - -
Figure 11. Automatic (CAS-before-RAS) Refresh Cycle Timing
1ExAs
~
INSTRUMENTS
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4-221
TMS416400
4 194 304·WORD BY 4·BIT
DYNAMIC RANDOM·ACCESS MEMORY
SMKS640B-NOVEMBER 1 99o-REVISED JANUARY 1993
PARAMETER MEASUREMENT INFORMATION
Figure 12. Hidden Refresh Cycle (Read)
TEXAS ~
INsrRUMENTS
4-222
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
TMS416400
4194 304·WORD BY 4·BIT
DYNAMIC RANDOM·ACCESS MEMORY
SMKS640B-NOVEMBER 1990-REVISED JANUARY 1993
PARAMETER MEASUREMENT INFORMATION
~VIH
VIL
DQ1-DQ4~
Figure 13. Hidden Refresh Cycle (Write)
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
4-223
TMS416400
4 194 304-WORD BY 4·BIT
DYNAMIC RANDOM·ACCESS MEMORY
SMKS640B-NOVEMBER 19~EVISED JANUARY 1993
PARAMETER MEASUREMENT INFORMATION
A~A11~oH~~~~VIH
VIL
OE~~*Jg*!~VIH
VIL
VIH
OQ1-0Q4 ---------------HI-Z - - - - - - - - - - - - - Figure 14. Test Mode Entry Cycle
1ExAs
..tJra
INSTRUMENTS
4-224
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
TMS416400
4194 304·WORD BY 4·BIT
DYNAMIC RANDOM·ACCESS MEMORY
SMKS640B-NOVEMBER 1990-REVISED JANUARY 1993
PARAMETER MEASUREMENT INFORMATION
Q
~------------HI'Z----------- :::
Figure 15. Test Mode Exit Cycle (CAS·before-RAS Refresh Cycle)
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
4·225
TMS416400·
4 194 304·WORD BY 4·BIT
DYNAMIC RANDOM·ACCESS MEMORY
SMKS640B-NOVEMBER 199D-REVISED JANUARY 1993
device symbolization
-~
TI
:=J TMS416400
W
~
PT
Jt-
-¥
Speed (-60, -70, -80)
Package Code
Lot Traceability Code
Month Code
Assembly Site Code
Ole Revision Code
Wafer Fab Code
TEXAS ~
INsrRUMENTS
4-226
POST OFFICE BOX 1443· HOUSTON, TEXAS 77001
TMS417400
4 194 304-WORD BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORY
1991-REVISED DECEMBER 1992
This data sheet is applicable to all TMS417400s
symbolized with Revision '1'\" and subsequent
revisions as described on page 23.
•
•
•
Organization •.. 4 194 304
x
DZPACKAGEt
(TOP VIEW)
4
Single 5-V Power Supply (10% Tolerance)
Performance Ranges:
ACCESS ACCESS ACCESS READ
TIME
TIME
TIME OR WRITE
tRAC
tCAC
tAA
CYCLE
(MAX)
(MAX)
(MAX)
(MIN)
TMS416400-60
60ns
15ns
30ns
110ns
TMS416400-70
70 ns
18 ns
35 ns
130 ns
TMS416400-80
80 ns
20 ns
40 ns
150 ns
•
•
Enhanced Page Mode Operation for Faster
Memory Access
CAS-before-RAS Refresh
•
Long Refresh Period ... 2048 Cycles
Refresh In 32 ms
•
•
•
3-State Unlatched Output
•
Vcc
VSS
DOl
D02
IN
RAS
NC
D04
D03
CAS
OE
A9
Al0
AO
Al
A2
A3
AS
A7
A6
A5
Vcc
VSS
A4
DGD PACKAGEt
(TOP VIEW)
DGC PACKAGEt
(TOP VIEW)
Low Power Dissipation
All Inputs, Outputs, and Clocks are
TTL Compatible
Operating Free-Air Temperature Range
O°C to 70°C
Vcc
VSS
VSS
Vcc
DOl
D02
IN
RAS
NC
D04
D03
CAS
D04
D03
CAS
DOl
D02
IN
RAS
NC
OE
OE
A9
A9
Al0
AO
Al
A2
A3
AS
A7
A6
A5
AS
A7
A6
A5
Vcc
VSS
description
The TMS417400 series are high-speed
16 777 216-bit dynamic random-access memories, organized as 4 194 304-bit words by four bits
each. They employ state-of-the-art EPIC'·
(Enhanced Performance Implanted CMOS) technology for high performance, reliability, and low
power at a low cost.
These devices feature maximum RAS access
times of 60 ns, 70 ns, and 80 ns.
A4
VSS
Vcc
t The packages shown are for pinout reference only.
PIN NOMENCLATURE
All inputs, outputs, and clocks, are compatible with
Series 74 TTL. All addresses and data-in lines are
latched on-chip to simplify system design. Data
out is unlatched to allow greater system flexibility.
AO-A10
CAS
D01-D04
NC
OE
RAS
The TMS417400 is offered in 400-mil 28/24-pin
surface mount SOJ (DZ suffix) and 400-mil
28/24-pin surface mount thin SOP (DGC and DGD
suffixes) packages. This device is characterized
for operation from O°C to 70°C.
TEXAS
A4
Al0
AO
Al
A2
A3
W
VCC
VSS
~
Address Inputs
Column-Address Strobe
Data In/Data Out
No Internal Connection
Output Enable
Row-Address Strobe
Write Enable
5-V Supply
Ground
Copyright © 1992, Texas Instruments Incorporated
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
4-227
TMS417400
4194 304-WORD BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SMKS740A-JULY 1991-REVISED DECEMBER 1992
operation
enhanced page mode
Page mode operation allows effectively faster memory access by keeping the same row address and strobing
random column addresses onto the chip. Thus, the time required to set up and strobe row addresses for the
same page is eliminated. The maximum number of columns that can be addressed is determined by tRAS, the
maximum RAS low width.
The Column Address Buffers in this CMOS device are activated on the falling edge of RAS. They act as a
transparent or flow-through latch, while CAS is high. The falling edge of CAS latches the addresses into these
buffers and also serves as an output enable.
This feature allows the TMS417400 to operate at a higher data bandwidth than conventional page-mode parts,
since retrieval begins as soon as the column address is valid, rather than when CAS transitions low. The
performance improvement is referred to as enhanced page mode. Valid column address may be presented
immediately after row address hold time has been satisfied, usually well in advance of the falling edge of CAS.
In this case, data is obtained aftertCAC max (access time from CAS low), if tAA max (access time from column
address) and tRAS have been satisfied. In the event that the column address for the next cycle is valid at the
time CAS goes high, access time is determined by the later occurrence of tCPA or tCAC'
address (AO-A10)
Twenty-two address bits are required to decode 1 of 4 194 304 storage cell locations. Twelve row-address bits
are set on inputs AO through A10 and latched onto the chip by the Row Address Strobe RAS. Eleven
column-address bits are set on AO through A 10. All addresses must be stable on or before the falling edges of
RAS and CAS. RAS is similar to a chip enable in that it activates the sense amplifiers as well as the row decoder.
CAS is used as a chip select, activating the output buffer, as well as latching the address bits into the column
buffer.
write enable (W)
The read or write mode is selected through the write-enable W input. A logic high on the W input selects the
read mode and a logic low selects the write mode. The write-enable terminal can be driven from standard TIL
circuits without a pullup resistor. The data input is disabled when the read mode is selected. When W goes low
prior to CAS (early write), data out will remain in the high-impedance state for the entire cycle permitting a write
operation independent of the state of OE. This permits early write operation to be completed with OE grounded.
data-in/data-out (OQ1-0Q4)
Data is written during a write or read-modify-write cxcle. Depending on the mode of operation, the falling of CAS
or W strobes data into the on-Chip data latch. In the early-write cycle, W is brought low prior to CAS and data
is strobed in by CAS with setup and hold times referenced to this signal. In a delayed write or read-modify write
cycle, CAS will already be low, thus data will be strobed in by W with setup and hold times referenced to this
signal.
The three-state output buffer provides direct TIL compatibility (no pullup resistor required) with a fan-out of two
Series 74 TIL loads. The output is in the high-impedance (floating) state until CAS is brought low. In a read cycle
the output becomes valid at the latest occurrence of tRAC, tAA, tCAC, or tCPA and remains valid while CAS is low.
CAS going high returns it to a high-impedance state. In a delayed-write or read-modify-write cycle, the output
does not change, but retains the state just read.
output enable (OE)
OE controls the impedance ofthe output buffers. When OE is high, the buffers will remain in the high-impedance
state. Bringing OE low during a normal cycle will activate the output buffers putting them in the low-impedance
state. It is necessary for both RAS and CAS to be brought low for the output buffers to go into the low-impedance
state. Once in the low-impedance state, they will remain for the low-impedance state until either OE or CAS is
brought high.
TEXAS ~
INSTRUMENTS
4-228
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
TMS417400
4194 304·WORD BY 4·BIT
DYNAMIC RANDOM-ACCESS MEMORY
SMKS740A-JULY 1991-REVISED DECEMBER 1992
refresh
A refresh operation must be performed at least once every thirty-two milliseconds to retain data. This can be
achieved by strobing each of the 2048 rows (AO-A 10). A normal read or write cycle will refresh all bits in each
row that is selected. A RAS-only operation can be used by holding CAS at a high (inactive) level, thus conserving
power since the output buffer remains in the high-impedance state. Externally generated addresses must be
used for a RAS-only refresh. Hidden refresh may be performed by holding CAS at VIL after a read operation
and cycling RAS after the specified precharge period, similar to a RAS-only refresh cycle except with CAS held
low. Valid data is maintained at the output throughout the hidden refresh cycle. An internal refresh address
provides the refresh address during hidden refresh.
CAS-before-RAS refresh
CAS-before-RAS refresh is utilized by bringing CAS low earlier than RAS (see parameter tCSR) and holding it
low after RAS falls (see parameter tCHR)' For successive CAS-before-RAS refresh cycles, CAS can remain low
while cycling RAS. For this mode of refresh, the external addresses are ignored and the refresh address is
generated internally.
power up
To achieve proper device operation, an initial pause of 200 f.ts followed by a minimum of eight initialization cycles
is required after full V CC level is achieved. These eight initialization cycles need to include at least one refresh
(RAS-only or CAS-before-RAS) cycle.
TEXAS ~
INsrRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
4-229
TMS417400
4 194 304·WORD BY 4"BIT
DYNAMIC RANDOM·ACCESS MEMORY
SMKS740A~ULY
1991-REVISED DECEMBER 1992
test mode
The test mode is initiated with a CAS-before-RAS refresh cycle while simultaneously holding the W input low
(WCBR). The initiate cycle performs an internal refresh cycle while internally setting the device to perform
parallel read or write on subsequent cycles. While in test mode, any desired data sequence can be performed
on the device. The device exits test mode if a CAS-before-RAS (CBR) refresh cycle, with W input held high, or
a RAS-only refresh (ROR) cycle is performed.
The part is configured as 1024K x 4 x 4 bit device in test mode, where each DO pin has a separate 4-bit
parallel read and write data bus where CAO and CA1 are ignored. During a read cycle, the 4 internal bits are
compared for each DO pin separately. If the 4 bits agree, the DO pin will go high, if not, the DO pin will go low.
All 4 bits are written to the state of their respective DO pin during a parallel write. Thus, each DO pin is
independent of the other and any data pattern desired may be written on each DO pin. Test time is thus reduced
by a factor of 4 for this series.
1 + - - - -••+- Entry Cycle
Exit Cycle
---lA 4194303
18
19
20
23
9
25
W
20011/2100
12
5
OE
RAM 4096K x 4
10
11
4
24
20021/21010
~
~
~
> C20[ROW]
G23/[REFRESH ROW]
24[PWROWN]
> C21 [COLUMN]
G24
&
23,210
> 23C22
24,25EN
r-- G2S
"l
2
3
26
4-
A,220
V' 26
r
A,Z26
27
t This symbol is in accordance with ANSI/IEEE Std 91-1984 and lEe Publication 617-12.
The pin numbers shown correspond to the DZ package.
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
4-231
TMS417400
4194 304-WORD BY 4·BIT
DYNAMICRANDOM·ACCESS MEMORY
SMKS740A-JULY 1991-REVISED DECEMBER 1992
,,,,
functional block diagram
L
,
Timing and Control
~
9
AO
/
A1
•
•
•
A10
Column
Address
Buffers
2,
'---
256KArray
256KArray
32<
Row
Address
Buffers
••
•
1Q
/
1 __
f.-+
Sense Amplifiers
--I-
L
•
•
•
Column Decode
256KArray
R
0
w
D
e
c
0
d
e
256KArray
10
/
L±
256KArray
•
••
>- 32
2f256KArray
-r
· TEXAS ~
INSTRUMENTS
4·232
I/O
Buffers
40f32
Selection
POST OFFICE BOX 1443· HOUSTON, TEXAS 77001
1--
~
In
Reg.
~
Out
Reg.
DQ1 -DQ4
TMS417400
4194 304·WORD BY 4·BIT
DYNAMIC RANDOM·ACCESS MEMORY
SMKS740A-JULY 1991-REVISED DECEMBER 1992
absolute maximum ratings over operating free-air temperature t
Voltage on any pin (see Note 1) ....................................................... - 1 V to 7 V
Voltage range on Vee . . . . . . . . .. .. . . . . . . . . . . . . .. .. . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . .. - 1 V to 7 V
Short circuit output current ................................................................ 50 mA
Power dissipation .......................................................................... 1 W
Operating free-air temperature range .................................................. ooe to 70°C
Storage temperature range ....................................................... - 55°C to 125°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values in this data sheet are with respect to VSS.
recommended operating conditions
MIN
NOM
MAX
VCC
Supply voltage
4.5
5
5.5
VIH
High-level input voltage
2.4
6.5
V
VIL
LOW-level input voltage (see Note 2)
-1
0.8
V
70
"C
Operating free-air temperature
0
TA
..
..
..
NOTE 2: Then algebraiC convention, where the more negative (less positive) limit IS deSignated as minimUm, IS used
voltage levels only.
In
UNIT
V
thiS data sheet for logiC
electrical characteristics over full ranges of recommended operating conditions (unless otherwise
noted)
PARAMETER
TEST
CONDITIONS
VOH
High-level output voltage
10H =-5 mA
VOL
LOW-level output voltage
IOL=4.2mA
II
TMS417400-60
MIN
MAX
TMS417400-70
MIN
MAX
MIN
MAX
2.4
2.4
2.4
TMS417400-80
UNIT
V
V
0.4
0.4
0.4
Input current (Ieakage)*
VI = 0 to 6.5 V,
All other pins = 0 V to
VCC
±10
±10
±10
~A
10
Output current (Ieakage)*
VO=OtoVCC,
CAS high
±10
±10
±10
~A
ICCl
Read or write cycle current
(see Notes 3 and 5)
Minimum cycle,
VCC =5.5V
120
110
100
mA
After 1 memory cycle,
RAS and CAS high,
VIH = 2.4 V (TTL)
2
2
2
mA
After 1 memory cycle,
RAS and CAS high,
VIH = VCC-O.2V
(CMOS)
1
1
1
rnA
ICC2
Standby current
ICC3
Average refresh current (RAS-only or
CBR) (see Notes 3 and 5):1:
RAS cycling CAS high
(RAS-only). RAS low
after CAS low (CBR)
120
110
100
mA
ICC4
Average page current
(see Notes 4 and 5)*
RAS low, CAS cycling
70
60
50
mA
ICC7
Standby current output enable
(see Note 5)*
RAS = VIH, CAS = VIL,
Data out = enabled
5
5
5
mA
..
* M,nimum cycle, VCC = 5.5 V.
NOTES:
3. Measured with a maximum of one address change while RAS = VIL.
4. Measured with a maximum of one adddress change while CAS = VIH.
5. ICC MAX is specified with no load connected.
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443· HOUSTON. TEXAS 77001
4-233
TMS417400
4 194 304·WORD BY 4·BIT
DYNAMIC RANDOM·ACCESS MEMORY
SMKS740A-JULY 1991-REVISED DECEMBER 1992
capacitance over recommended ranges of supply voltage and operating free-air temperature,
f = 1 MHz (see Note 6)
PARAMETER
MIN
TYP
MAX
UNIT
Ci(A)
Input capacitance, address inputs
5
pF
Ci(RC)
Input capacitance, strobe inputs
7
pF
Ci(OE)
Input capacitance, output enable
7
pF
Ci(W)
Input capacitance, write-enable input
7
pF
Co
Output capac~ance
7
pF
NOTE 6: VCC equal to 5.0 V '" 0.5 V and the bias on pins under test is 0 V.
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature
PARAMETER
TMS417400-60
TMS417400-70
MIN
MIN
MAX
MAX
TMS417400-80
MIN
MAX
UNIT
tM
Access time from column-address
30
35
40
ns
tCAC
Access time from CAS low
15
18
20
ns
tePA
Access time from column precharge
35
40
45
ns
tRAC
Access time from RAS low
60
70
80
ns
20
ns
18
toEA
Access time from OE low
tCLZ
CAS to output in low Z
0
15
0
0
ns
toH
Output disable start of CAS high
3
3
3
ns
tOHO
Output disable time start of OE high
3
3
3
ns
tOFF
Output disable time after CAS high
(see Note 7)
0
15
0
18
0
20
ns
tOEZ
Output disable time after OE high
(see Note 7)
0
15
0
18
0
20
ns
NOTE 7: tOFF is specified when the output is n? longer driven.
TEXAS
~
INSTRUMENTS
4-234
POST OFFICE BOX 1443· HOUSTON, TEXAS 77001
TMS417400
4194 304·WORD BY 4·BIT
DYNAMIC RANDOM·ACCESS MEMORY
SMKS740A--JULY 1991-REVISED DECEMBER 1992
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
TMS417400-60
MIN
MAX
TMS417400-70
MIN
MAX
TMS417400-80
MIN
MAX
UNIT
tRC
Random read or write cycle (see Note 8)
110
130
150
tRWC
Read-write cycle time
155
181
205
ns
ns
tpc
Page-mode read or write cycle time (see Note 9)
40
45
50
ns
tpRWC
Page-mode read-write cycle time
85
tRASP
Page-mode pulse duration, RAS low (see Note 10)
60
100000
70
100000
80
100000
ns
tRAS
Non-page-mode pulse duration, RAS low (see Note 10)
60
10000
70
10000
80
10 000
ns
tCAS
Pulse duration,
CAS low (see Note 11)
15
10 000
18
10 000
20
10 000
ns
tcp
Pulse duration, CAS high
10
10
10
ns
tRP
Pulse duration, RAS high (precharge)
40
50
60
ns
twp
Write pulse duration
15
15
15
ns
tASC
Column-address setup time before CAS low
0
0
0
ns
tASR
Row-address setup time before RAS low
0
0
0
ns
tDS
Data setup time (see Note 12)
0
0
0
ns
tRCS
Read setup before CAS low
0
0
0
ns
tcWL
W-Iow setup time before CAS high
15
18
20
ns
tRWL
W-Iow setup time before RAS high
15
18
20
ns
twcs
W-Iow setup time before CAS low
(Early write operation only)
0
0
0
ns
twSR
W-high setup time (CAS-before-RAS refresh only)
10
10
10
ns
twTs
W-Iow setup time (test-mode only)
10
10
10
ns
tCAH
Column-address hold time after CAS low
10
15
15
ns
tDH
Data hold time (see Note 12)
10
15
15
ns
tRAH
,Row-address hold time after RAS low
10
10
10
ns
tRCH
Read hold time after CAS high (see Note 13)
0
0
0
ns
ns
105
96
ns
tRRH
Read hold time after RAS high (see Note 13)
5
5
5
twCH
Write hold time after CAS low (Early write operation only)
15
15
15
ns
twHR
W-high hold time (CAS-before-RAS refresh only)
10
10
10
ns
twTH
W-Iow hold time (test mode only)
10
10
10
ns
Continued next page,
NOTES: 8, All cycle times assume IT = :; ns.
g, To guarantee tpc min, tASC should be greater than or equal to tcp,
10, In a read-write cycle, tRWD and tRWL must be observed,
11, In a read-write cycle, tCWD and tCWL must be observed,
12, Referenced to the later of CAS or Win write operations.
13, Either tRRH or tRCH must be satisfied for a read cycle,
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
4-235
TMS417400
4194304·WORD BY 4·BIT
DYNAMIC RANDOM·ACCESS MEMORY
SMKS740A-JULY 1991-REVISED DECEMBER 1992
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (concluded)
TMS417400-60
TMS417400-70
MIN
MIN
MAX
MAX
TMS417400-80
MIN
UNIT
MAX
lAWD
Delay time, column address to W low
(Read-write operation only)
55
63
70
ns
tCHR
Delay time, RAS low to CAS high
(CAS-bafore-RAS refresh only)
20
20
20
ns
tCRP
Delay time, CAS high to RAS low
5
5
5
ns
tCSH
Delay time, RAS low to CAS high
60
70
80
ns
10
10
10
ns
tCSR
~ time, CAS low to RAS low
(CAS-before-RAS refresh only)
tCWD
Delay time, CAS low to W low (Read-write operation only)
40
46
50
ns
tOEH
OE command hold time
15
18
20
ns
tOED
OE to data delay
15
18
20
ns
tROH
RAS hold time referenced to OE
10
10
10
tRAD
Delay time, RAS low to column-address (see Note 14)
15
tRAL
Delay time, column-address to RAS high
30
35
40
tCAL
Delay time, column-address to CAS high
30
35
40
tRCD
Delay time, RAS low to CAS low (see Note 14)
20
tRPC
Delay time, RAS high to CAS low
0
0
0
ns
tRSH
Delay time, CAS low to RAS high
15
18
20
ns
tRWD
Delay time, RAS low to W low (Read-write operation only)
85
98
110
ns
tCPRH
RAS hold time from CAS precharge
35
40
45
ns
30
45
15
20
35
52
15
20
ns
40
ns
ns
ns
60
ns
tcpw
Delay time, W from CAS precharge
60
68
75
ns
lTAA
Access time from address (test mode)
35
40
45
ns
lTCPA
Access time from column precharge (test mode)
40
45
50
ns
lTRAC
Access time from RAS( test mode)
65
75
85
tREF
Refresh time interval
IT
Transition time
3
30
NOTE 14: The maximum value is specified only to assure access time.
.
TEXAS ~
INSTRUMENTS
4-236
32
32
POST OFFICE BOX 1443· HOUSTON. TEXAS 77001
3
30
3
ns
32
ms
30
ns
TMS417400
4 194 304·WORD BY 4·BIT
DYNAMIC RANDOM·ACCESS MEMORY
SMKS740A-JULY 1991-REVISED DECEMBER 1992
PARAMETER MEASUREMENT INFORMATION
1.31 V
~
Output Under Test
RL
--l
CL= 1OOPF
VCC =5V
= 218
Q
Output Under Test - - . - - - - - - .
T
CL = 100 pF
(a) Load Circuit
(b) Alternate Load Circuit
Figure 2. Load Circuits for Timing Parameters
1l1li
: l~.
N
~
~ I.
\
y
~ tRP ----+! \.
~"--tr-------------"!I I
I "'------tRAS
I
I
I
I
~,,~
~I
1l1li
I
--.I
I"
j4- tRAH
tRAO
I
I 1
1
I
I I
I
I ~I I
I
I ~tCRP~
tRSH
Ni
~
I-
tASR
I'
tCAS
~ X! 1 " 1 \
¥ ~I
!
:
tcp
I I I I
1111
I I I I
~I I I I
~tASC
I '
I I
VIL
~I
I 1l1li
tCSH
~ I I+-----tRCO~
I I
1l1li
I
I
~
~I
tRC
VIH
---_.J \.. . ---- VIL
,_: kJ' c.,~": _~~~.r-,---_-_-_-_-_-_-_-_-_-_:::
I
I
~
'III
t RCS
:1
U
~
I
tCAL
~tCAH
W~~*2~arlW::
~~~~I~~
*I
!
OQ1-0Q4 - - - -...
1-- HI-Z
I
1l1li
1l1li
I
I
1
i+- tRRH
~
:~*2~~r~
I I I
tCAC~ I 1"1
:tAA
(see Note A)
tcLZ iIIII
tRAC
I I -[+I
I 1"1
I
;;;0,.
1l1li
~
~I
tOFF
1 "alltedoHata Out
y,
I
~I
~tOEA-.I
I
I
OEWWHi~*~~tRoH~
VIH
VIL
.1
~,
VOH
.;1)-.- - - - - - -
I
I"
~
teHO
I
I
I ~tOEZ
VOL
1w~~~~o~~~2~~e~~ VIH
VIL
NOTE A: Output may go from three-state to an invalid data state prior to the specified access time.
Figure 3. Read Cycle Timing
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
4-237
TMS417400
4 194 304·WORD BY 4·BIT
DYNAMIC RANDOM·ACCESS MEMORY
SMKS740A-.JULY 1991-REVISED DECEMBER 1992
PARAMETER MEASUREMENT INFORMATION
Figure 4. Early Write Cycle Timing
TEXAS ,.,
INSfRUMENTS
4-238
POST OFFICE BOX 1443· HOUSTON, TEXAS 77001
TMS417400
4 194 304·WORD BY 4·BIT
DYNAMIC RANDOM·ACCESS MEMORY
SMKS740A-JULY 1991-REVISED DECEMBER 1992
PARAMETER MEASUREMENT INFORMATION
Figure 5. Write Cycle Timing
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443· HOUSTON, TEXAS 77001
4-239
TMS417400
4194 304·WORD BY 4·BIT
DYNAMIC RANDOM·ACCESS MEMORY
SMKS740A-JULY 1991-REVISED DECEMBER 1992
PARAMETER MEASUREMENT INFORMATION
NOTE A: Output may go from three-state to an invalid data state prior to the specified access time.
Figure 6. Read-Write Cycle Timing
TEXAS ~
INSTRUMENTS
4-240
POST OFFICE BOX 1443' HOUSTON. TEXAS 77001
TMS417400
4194 304-WORD BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SMKS740A-JULY 1991-REVISED DECEMBER 1992
PARAMETER MEASUREMENT INFORMATION
AO--A10
- XXf.)<)<:!7
W
I
I
~ l+-- tRAD ---+I
I
I
I
I".
I
:1
i:
WXI
W
ffl VIH
\{i VIL
I
I
I
1..114----- tCPA - - - 11-+-1-~~I
~tCAC~
(see Note B) I I
I
I
141
.. - - + I - t A A . 1
tRAC
~I
tCLZ 1..1
.1
:..
.1
VOH
Out
I 104~ tOHO
I ~ I+- tOE~
OE~~o~X~~~tOEA~
: tOFF~
I tOH
DQ1-DQ4---------~~~~{XXX:X):XI Valid I
(see Note A)
1..
lm1
Valid
Out
tOHO
loiii
I tOEzl ~
tOEA~
~I
VOL
.1
~VIH
VIL
NOTES: A. Output may go from three-state to an invalid data state prior to the specified access time.
B. Access time is tePA or tAA dependent.
Figure 7. Enhanced Page-Mode Read Cycle Timing
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
4-241
TMS417400
4 194 304·WORD BY 4·BIT
DYNAMIC RANDOM·ACCESS MEMORY
SMKS740A-JULY 1991-REVISED DECEMBER 1992
PARAMETER MEASUREMENT INFORMATION
NOTES: A. Referenced to CAS or IN, whichever occurs last.
B. A read cycle or a read-write cycle can be intermixed with write cycle as long as read and read-write timing specifications are not
violated.
Figure 8. Enhanced Page-Mode Write Cycle Timing
TEXAS ~
INsrRUMENTS
4-242
POST OFFICE BOX 1443· HOUSTON, TEXAS 77001
TMS417400
4 194 304-WORD BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SMKS740A-JULY 1991-REVISED DECEMBER 1992
PARAMETER MEASUREMENT INFORMATION
tRP~
r+-
rx:I "- VIH
1
:'i ====-t:C:S:-:H-=-=-=-=-=-=-=-"'--~.:I!.I-=====7,tC:;;P;;;R::H-=====:::;.~I
~ f'IIII..-----------tRASP ------------.~I
RAS
I
I
I
:
CAS
-+i
I
t..l
I
I
I'"
:
1'4
~ tRCD
*t- tASR
I
I
tRAD
,V-
I I
-+i~tASC
II I
tpRWC
'X
I
I
I
I
!'II
I
I
~~~~~~~:::..c...:::..c...~VIL
:~ i'--tCWD~:
.
/:.-+:
"-----------":1
Column
I
I
r
i
VIL
I
..I
...
---VIH
I
VIL
I
I
i"Il..I-----tRSH ---~.I
.1 I
.. I
1 ~-t tcp
tCRP
I
~
tCAS
tCAH~
AO-A10
...
I I
I
tAWD ----+i
I
III: tRWD
.1
_
I I
w~::i
I II I
r-
L
rtCWL~
:
I
tcpw ~ ~ tRWL --.I
I I
nww
~~~r ::ll
twP
~
I 1!<-----1I~
~~
~ill"-----I.~~~~~~.Q.VvIIHL
't. ~
I
- 1 1I I
~ tCPA ~
I" .1 tOEH
~ I ~ tRCS
I ~"--+.t-I tDH
I
I
I
I.. ! .1 tAA
I:
I
I
.
I
I,.-- tRAC I~ _
L..; tDS
I
I
Valid Out
I
~I ~
I
I
(see Note A)
I
~tCAC I_...I..I___...,~
VIHNOH
DQ1-DQ4
I ~~c
valid:
I
Valid T'"I_ _ _ _ __
I
_
In
_
In
I
-.I L.. I I
I
I
I
VIl.NOL
tCLZ
"""I I Valid Outl
_1
I
~I
04-I"
~
tOED
I
r 1- tOEZ!,.
j+- tOEA ---+I II
~---.~r-tOEH:.-1_ _ _ _ _"I~~~~~~
OE~
--.y;.r.:'---tO-H-O---"""\J
~ VIH
~~~~~.Q.VIL
I
I
NOTES: A. Output may go from three-state to an invalid data state prior to the specified access time.
B. A read or write cycle can be intermixed with read-write cycles as long as the read and write timing specifications are not violated.
Figure 9. Enhanced Page-Mode Read-Write Cycle Timing
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443· HOUSTON, TEXAS 77001
4-243
1MS417400
4 194 304·WORD BY 4·B11
DYNAMIC RANDOM·ACCESS MEMORY
SMKS740A-JULY 1991-REVISED DECEMBER 1992
~~~~VIH
OQ1-0Q4
VIL
Figure 10. RAS-Only Refresh Timing
~14----------------------tRC--------------------~·1
~tRP~ ~14~-----------tRAS--------------~.1 I
I
RAS
I I
tRPC -
.1
I
I
~tCSR~
~
\{
twSR
i
1"11
1
1
I
_ _ _ _ _ _ _ _ _ _ _ _ _ _---J:
r
~I
Ir-_ _ __
Y
.N
A
----' I
I
y..---------
VIH
VIL
~4---- tCHR -----+1.1
~
• L..:--••11- tWHR
VIH
~
OE~R*)RH~V'H
VIL
VIH
OQ1-0Q4 - - - - - - - - - - - - - - - - - - - - HI-Z - - - - - - - - - - - - - - -
Figure 11. Automatic (CAS-Before-RAS) Refresh Cycle Timing
TEXAS ~
INsrRUMENTS
4-244
POS, OFFICE BOX 1443· HOUSTON, TEXAS 77001
TMS417400
4194 304·WORD BY 4·BIT
DYNAMIC RANDOM·ACCESS MEMORY
SMKS740A-JULY 1991-REVISED DECEMBER 1992
PARAMETER MEASUREMENT INFORMATION
~ Refresh Cycle ~
~ Memory Cycle ~
~ Refresh Cycle ~
I"
I
I I"
I I
RAS
.1
I
N-
~I
1 tRAS
lX
ri
N
II i i I
-
CAS
I
I
III
I
i I
tRP
I..
I 1
I
I I"
~I
~I I tRAS I
Y
i~
N'
I,,!!I
I i i
tCAH
Ii
tRAH~r:;I,:t~sc
II
Il:Ji-4I
I
I
tRP
rlr-----{
1\
/!L-I
tCHR i I..
~
i I
tCAS
i:
!I
i
II
II
((
II
~~~il
ItRRI1 -+j
w~i i·~:tRCS
~'I I~
I I
I '"
I
j+--
i
j+- tWHR
~~tw~
r-VI
I ~
I!'i
tCAC
:::
i!iI 1
} r1v
VIH
I
II
II
II
I
I
I
I
IL
VIH
~~X~~~VIL
AO-A10
I
r
~
-J+i
l
I"-tWHR
Wxxn0W-
. - tw
~{;I
tAA
~
j+- t;tiHR
l.-tw_,SR VIH
VIL
I
tOFF --.,
1'-
~-~
I~
DQ1-DQ4 -----~,...---------v.-al-Id-D-at-a-O-ut---~~'T~------~
} VOL
~~~
~~~~ r-~
tOEA
tOEZ
OE88888888ol
II',
-+1
~
~
VIH
VIL
Figure 12. Hidden Refresh Cycle (Read)
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443· HOUSTON, TEXAS 77001
4-245
TMS417400
4194 304·WORD BY4·BIT
DYNAMIC RANDOM·ACCESSMEMORY
SMKS740A-JULY 1991-REVISED DECEMBER 1992
PARAMETER MEASUREMENT INFORMATION
~VIH
VIL
DQ1-DQ4~
Figure 13. Hidden Refresh Cycle (Write)
TEXAS .."
INsrRuMENTS
4-246
POST OFFICE BOX 1443· HOUSTON, TEXAS 77001
TMS417400
4194 304·WORD BY 4·BIT
DYNAMIC RANDOM·ACCESS MEMORY
SMKS740A-JULY 1991-REVISED DECEMBER 1992
PARAMETER MEASUREMENT INFORMATION
AG-A10~o~g~i~VIH
VIL
OE~~*HH~VIH
VIL
VIH
DQ1-DQ4 - - - - - - - - - - - - - - - - HI·Z - - - - - - - - - - - - - - -
Figure 14. Test Mode Entry Cycle
Q
~------------HI.Z----------- :::
Figure 15. Test Mode Exit Cycle (CAS-before-RAS Refresh Cycle)
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
4·247
TMS417400
4 194 304·WORD BY 4·BIT
DYNAMIC RANDOM·ACCESS MEMORY
SMKS740A--JULY 1991-REVISED DECEMBER 1992
device symbolization
TI
)
W
A
P
~
r
!??
TMS417400
Speed (-60, -70, -80)
Package Code
!¥
Lot Traceability Code
Month Code
Assembly Site Code
Ole Revision Code
Wafer Fab Code
TEXAS ~
INSTRUMENTS
4-248
POST OFFICE BOX 1443· HOUSTON, TEXAS 77001
TMS416100 16777 216·BIT
TMS416400 4194 304·WORD BY 4·BIT
TMS417400 4194 304·WORD BY 4·BIT DYNAMIC RANDOM ACCESS MEMORIES
SMKS003-DECEMBER 1992
•
•
•
This Product Preview is Applicable to
All
TMS416100/P,
TMS416400/P,
and
TMS417400/P Devices Symbolized With
Revision "8" and Subsequent Revisions as
Described on Page 4.
Organization:
16777216 x 1 TMS416100, TMS416100P
4194304 x 4 TMS416400 , TMS416400P
4194304 x 4 TMS417400, TMS417400P
High Reliability Plastic 300-Mil 24/26-Lead
Surface Mount (SOJ) Package, 24/26-Lead
Thin Small Outline Package, and Reverse
Thin Small Outline Package
Low Power Dissipation
- 500!lA CMOS Standby Current
(TMS416100P, TMS416400P,
TMS417400P)
- 500!lA Self-Refresh Current
(TMS416100P, TMS416400P,
TMS417400P)
- 500!lA Extended Refresh Battery Backup
Current (TMS416100P, TMS416400P,
TMS417400P)
• 3-State Unlatched Output
• All Inputs, Outputs, and Clocks Are TTL
Compatible
• Enhanced Page Mode Operation for Faster
Memory Access
• Long Refresh Period
- 4096-Cycle Refresh in 64 ms
(TMS4161 00, TMS416400)
- 2048-Cycle Refresh in 32 ms
(TMS417400)
- 256 ms for Extended Refresh Version
(TMS416100P, TMS416400P,
TMS417400P)
• Single 5 V Power Supply (10% Tolerance)
• CAS-Before-RAS Refresh
• Operating Free-Air Temperature Range
ooe to 70°C
IJJ
==
>
IJJ
a:
• Performance Ranges:
ACCESS
ACCESS
ACCESS
READ
TIME
tRAC
(MAX)
TIME
tCAC
(MAX)
TIME
tAA
(MAX)
TMS416100/P-60
TMS416100/P-70
TMS416100/P-SO
60 ns
70 ns
SO ns
15 ns
lS ns
20 ns
TMS416400/P-60
TMS416400/P-70
TMS416400/P-80
60 ns
70 ns
80 ns
TMS417400/P-60
TMS417400/P-70
TMS417400/P-80
60 ns
70 ns
80 ns
D.
OR WRITE
CYCLE
(MIN)
ICC1
OPERATING
CURRENT
(MIN)
ICC3
REFRESH
CURRENT
(MIN)
30 ns
35 ns
40 ns
110 ns
130 ns
150 ns
SOmA
70 rnA
60 rnA
SOmA
70 rnA
60 rnA
15 ns
18 ns
20 ns
30 ns
35 ns
40 ns
110 ns
130 ns
150 ns
SOmA
70mA
60 rnA
SOmA
70 rnA
60 rnA
15 ns
18 ns
20 ns
30 ns
35 ns
40 ns
110 ns
130 ns
150 ns
110mA
100 rnA
90 rnA
110 rnA
100 rnA
90 rnA
t-
O
:::l
o
oa:
D.
description
The TMS416100, TMS416400, TMS417400 series are high-speed, 16777 216-bit dynamic random-access
memories, organized as either 16 777 216 words of one bit each (TMS4161 00) or 4 194 304 words of four bits
each (TMS416400, TMS417400).
The TMS4161 OOP, TMS416400P, and TMS417 400P series are high-speed, self-refresh and extended-refresh,
16777 216-bit DRAMS, organized as either 16777216 words of one bit each (TMS416100P) or 4194304
words of four bits each (TMS416400P, TMS417400P).
The TMS4161 OO/P, TMS416400/P, and TMS417 400/P are offered in a 300-mil24/26-lead plastic surface mount
SOJ package (DJ suffix), a 24/26-lead plastic small outline package (DGA suffix), and a 24/26-lead plastic small
outline package, reverse form (DGB suffix). All packages are characterized for operation from O°C to 70°C.
e
PRODUCT PRE'IIEW information .....m. produmln tllllorm.IIv, or
n ph... of development Charaet.rlltlc. dill and oth,r
catlOlllI,. dnlgn 110111. TlXlllnllrumentl NArv•• the light to
ng. or dllconUnu. th... producta wtthout nutlet.
TEXAS
~
Copyright © 1992, Texas Instruments Incorporated
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
4-249
TMS416100 16777 216·BIT
TMS4164004 194 304·WORD BY 4·BIT
TMS417400 4194 304·WORD BY 4·BIT DYNAMIC RANDOM ACCESS MEMORIES
SMKSOO3-DECEMBER 1992
TMS416100
OJ, DGA PACKAGESt
(TOP VIEW)
DGB PACKAGEt
(TOP VIEW)
26
o
Vee
25
NC
24
D
NC
CAS
23
NC
A9
22
AS
A7
A6
19
18
A5
16
VSS
W
RAS
All
21
15
Al0
AO
Al
A2
A3
14
Vee
17
A4
VSS
VSS
L -_ _- '
PIN NOMENCLATURE
AO-A11
CAS
D
NC
Q
RAS
Address Inputs
Column-Address Strobe
Data In
No Internal Connection
Data Out
Row-Address Strobe .
Write Enable
5-V Supply
Ground
Vii
VCC
VSS
TMS416400
, OJ, DGA PACKAGESt
(TOP VIEW)
"C
Jl
o
DGB PACKAGEt
(TOP VIEW)
Vee
VSS
Vee
DOl
D02
W
D04
D03
CAS
All
A9
DOl
D02
W
RAS
All
Jl
Al0
AO
Al
AS
A7
A6
Al0
AO
Al
A2
A5
A2
:e
A3
A4
A3
C
c:
(")
OE
-I
"C
m
:S
m
Vee
--.....--....- VSS
PIN NOMENCLATURE
AD-A 11
CAS
DQ1-DQ4
OE
RAS
Vii
VCC
VSS
Address Inputs
Column-Address Strobe
Data In/Data Out
Output Enable
Row-Address Strobe
Write Enable
5-V Supply
Ground
Vee
TMS417400
OJ, DGA PACKAGESt
(TOP VIEW)
DGB PACKAGEt
(TOP VIEW)
Vee
VSS
VCC
DOl
D02
D04
D03
CAS
DOl
D02
OE
RAS
A9
NC
Al0
AO
Al
AS
A7
A6
Al0
AO
Al
A2
A5
A2
A3
A4
W
Vee
VSS
A3
VSS
14
13
L . . . - _......
VCC
t The packages shown are for pinout reference only,
TEXAS ~
INSTRUMENTS
4-250
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
PIN NOMENCLATURE
AD-A10
CAS
DQ1-DQ4
NC
OE
RAS
Vii
VCC
VSS
Address Inputs
Column-Address Strobe
Data In/Data Out
No Internal Connection
Output Enable
Row-Address Strobe
Write Enable
5-V Supply
Ground
TMS416100 16 777 216-BIT
TMS416400 4194 304-WORD BY 4-BIT
TMS417400 4194 304-WORD BY 4-BIT DYNAMIC RANDOM ACCESS MEMORIES
SMKSOO3-DECEMBER 1992
device symbolization
t~
TMS41xxxx :ifTI
)
Speed (-60, -70, -80)
Power/Self-Refresh Code
Package Code
Y! ~-t- ~ b¥=
I
I
Lot Traceability Code
Date Code
Assembly Site Code
Ole Revision Code
Wafer Fab Code
3=
w
5>
w
a::
c..
....
o
:J
C
o
a::
c..
TEXAS ~
INsrRUMENTS
POST OFFICE BOX 1443' HOUSTON, TEXAS 77001
4·251
TMS416100 16777 216·BIT
TMS416400 4194 304·WORD BY 4·BIT
TMS417400 4194 304·WORD BY 4·BIT DYNAMIC RANDOM ACCESS MEMORIES
SMKSOO3-DECEMBER 1992
TEXAS ."
INsrRUMENTS
4-252
POST OFFICE BOX 1443· HOUSTON, TEXAS 77001
TMS416160, TMS416160P
1048 576·WORD BY 16·BIT HIGH·SPEED
DYNAMIC RANDOM·ACCESS MEMORIES
SMKS66(}--OECEMBER 1992
•
Organization ... 1 048 576 x 16
•
•
Single 5-V Supply (10% Tolerance)
Performance Ranges:
'4161SO/P·60
'416160/P-70
'416160/P-80
ACCESS ACCESS ACCESS READ OR
TIME
TIME
TIME
WRITE
IRAC
ICAC
lAA
CYCLE
MAX
MAX
MAX
MIN
SOns
15ns
30ns
lIOns
35 ns
130 ns
70ns
lBns
80 ns
20 ns
40 ns
150 ns
•
Enhanced Page Mode Operation With
CAS-Before-RAS Refresh
•
Long Refresh Period ...
4096-Cycle Refresh In 64 ms (Max)
512 ms Max for Low-Power, Self-Refresh
Version (TMS416160P)
•
3-State Unlatched Output
•
Low Power Dissipation
DC PACKAGEt
(TOP VIEW)
REPACKAGEt
(TOP VIEW)
•
Self-Refresh with Low Power
•
All Inputs, Outputs, and Clocks are TTL
Compatible
•
High-Reliability Plastic 42-Lead
400-Mil-Wlde Surface Mount (SOJ)
Package, and 44/50-Lead Thin Small
Outline Package (TSOP)
•
Operating Free-Air Temperature Range
O°C to 70°C
•
Texas Instruments EPIC ™ CMOS Process
Vee
DOO
DOl
D03
VSS
D015
D014
D013
D012
D03
Vec
D04
D05
D06
DO?
VSS
DOll
D010
D09
DOS
VCC
D04
D05
D06
DO?
NC
LCAS
UCAS
NC
9
NC
NC
Vii
RAS
All
Al0
AO
AI
A2
A3
A9
AS
A?
A6
A5
VCC
VSS
VCC
DOO
VSS
D015
D014
D013
D012
2
41
40
Vss
DOll
DOlO
D09
DOS
NC
OE
A4
NC
LCAS
UCAS
NC
NC
Vii
OE
RAS
All
Al0
AO
Al
A2
A3
20
21
22
23
24
VCC
25
31
A9
AS
A?
A6
A5
A4
VSS
t Packages are shown for pinout reference only.
description
The TMS416160 series are high-speed,
16 777 216-bit
dynamic
random-access
memories organized as 1 048 576 words of
sixteen bits each.
W
VCC
VSS
They employ state-of-the-art EPIC'· (Enhanced Performance Implanted CMOS) technology for high
performance, reliability, ?nd low power at low cost.
These devices feature maximum RAS access times of 60 ns, 70 ns, and 80 ns. Maximum power dissipation is
as low as 385 mW operating and 11 mW standby on 80 ns devices.
All inputs and outputs, including clocks, are compatible with Series 74 TTL. All addresses and data-in lines are
latched on-chip to simplify system design. Data out is unlatched to allow greater system flexibility.
EPIC is a trademark of Texas Instruments Incorporated.
TEXAS
~
Copyright © 1992, Texas Instruments Incorporated
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
a:
a...
I-
o
::J
C
a...
Address Inputs
Data In/Data Out
Lower Column-Address Strobe
Upper Column-Address Strobe
No Internal Connection
Output Enable
Row-Address Strobe
Write Enable
5-V Supply
Ground
The TMS416160P series are high-speed, low-power, self-refresh, 16 777 216-bit dynamic random-access
memories organized as 1 048 576 words of sixteen bits each.
PRODUCT PREVIEW In.....otIon .....ma produeta In 1III .......1ve or
dellan phi.. of dlVttopmtnt. Chlrlcterlltlc d.1I .nd other
epeclne.Uont .... dttIgn 10111. Tuu In"rumen.. ,...rvt. the right 10
Gh.nga or dlicontinul thllt productl without noIlct.
:>
w
oa:
PIN NOMENCLATURE
AO-A11
DOO-D015
LCAS
UCAS
Ne
OE
RAS
~
w
4-253
TMS416160, TMS416160P
1 048 576·WORD BY 16·BIT HIGH·SPEED
DYNAMIC RANDOM·ACCESS MEMORIES
SMKS66G-OECEMBER 1992
The TMS416160 and TMS416160P are each offered in a 42-lead plastic surface mount SOJ (RE suffix)
package, and a 44/50-lead plastic surface mount TSOP (DC suffix). These packages are characterized for
operation from O°C to 70°C.
operation
dual CAS
Two CAS pins (LCA8-UCAS) are provided to give independent control of the sixteen data I/O pins
(000-0015), with LCAS corresponding to 000-007 and UCAS corresponding to 008-0015. For read or
write cycles, the column address is latched on the first xCAS falling edge. Each xCAS pin going low enables
its corresponding DO pin with data coming from the column address to be latched on the first falling xCAS edge.
All address setup and hold parameters are referenced to the first falling xCAS edge.The delay time from xCAS
low to valid data out (see parameter tCAd is measured from each individual CAS to its corresponding OOx pin.
In order to latch in a new column address, all xCAS pins must be brought high. The column precharge time (see
parameter tcp) is measured from the last xCAS rising edge to the first falling xCAS edge of the new cycle.
Keeping a column address valid while toggling xCAS requires a minimum setup time, tCLCH' During tCLCH, at
least one xCAS must be brought low before the other xCAS is taken high.
For early write cycles, the data is latched on the first falling xCAS edge. Only the DOs that have the
corresponding xCAS low will be written into. Each xCAS will have to meet tCAS minimum in order to ensure
writing into the storage cell. In order to latch a new address and new data, all xCAS pins need to come
high and meet tcp-
"tJ
:0
o
C
enhanced page mode
C
o
Page-mode operation allows faster memory access by keeping the same row address while selecting random
column addresses. The time for row-address setup and hold and address multiplex is thus eliminated. The
maximum number of columns that may be accessed is determined by the maximum RAS low time and the xCAS
page-mode cycle time used. With minimum xCAS page cycle time, all 256 columns specified by column
addresses AO through A7 can be accessed without intervening RAS cycles.
-I
"tJ
:0
m
~
m
Unlike conventional page-mode DRAMs, the column-address buffers in this device are activated on the falling
edge of RAS. The buffers act as transparent or flow-through latches while xCAS is high. The falling edge of the
first xCAS latches the column addresses. This feature allows the devices to operate at a higher data bandwidth
than conventional page-mode parts, because data retrieval begins as soon as column address is valid rather
than when xCAS transitions low. This performance improvement is referred to as enhanced page mode. Valid
column address may be presented immediately after tRAH (row address hold time) has been satisfied, usually
well in advance ofthefalling edge of xC AS. In this case, data is obtained aftertCAC max (access time from xCAS
low) if tAA max (access time from column address) has been satisfied. In the event that column addresses for
the next page cycle are valid at the time xCAS goes high, minimum access time for the next cycle is determined
by tCPA (access time from rising edge of the last xCAS).
:E
address (AO-A11)
Twenty address bits are required to decode 1 of 1 048 576 storage cell locations. Twelve row-address bits are
set up on pins AO through A 11 and latched onto the chip by RAS. Then, eight column-address bits are set up
on pins AO through A7 and latched onto the chip by the first xCAS. All addresses must be stable on or before
the falling edge of RAS and xCAS. RAS is similar to a chip enable in that it activates the sense amplifiers as
well as the row decoder. xCAS is used as a chip select, activating its corresponding output buffer and latching
the address bits into the column-address buffers.
TEXAS
~
INsrRUMENTS
4-254
POST OFFICE BOX 1443· HOUSTON, TEXAS 77001
TMS416160, TMS416160P
1 048 576-WORD BY 16-BIT HIGH-SPEED
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS660-DECEMBER 1992
write enable (W)
The read or write mode is selected through the W input. A logic high on the W input selects the read mode and
a logic low selects the write mode. The write-enable terminal can be driven from the standard TIL circuits without
a pull up resistor. The data inputs are disabled when the read mode is selected. When W goes low prior to xCAS
(early write), data out will remain in the high-impedance state for the entire cycle permitting a write operation
.
with OE grounded.
data In (OQO-OQ15)
Data is written during a write or read-modify-write cycle. Depending on the mode of operation, the falling edge
of xCAS or W strobes data into the on-Chip data latch. In an early-write cycle, W is brought low prior to xCAS
and the data is strobed in by the first occurring xCAS with setup and hold times referenced to this signal. In a
delayed-write or read-modify-write cycle, xCAS will already be low, thus the data will be strobed in by W with
setup and hold times referenced to this signal. In a delayed-write or read-modify-write cycle, OE must be high
to bring the output buffers to high impedance prior to impressing data on the I/O lines.
data out (OQO-OQ15)
The three-state output buffer provides direct TIL compatibility (no pull up resistor required) with a fanout of two
Series 74 TILioads. Data outis the same polarity as data in. The output is in the high-impedance (floating) state
until xCAS and OE are brought low. In a read cycle, the output becomes valid after the access time interval tCAC
(which begins with the negative transition of xCAS) as long as tRAC and tAA are satisfied.
output enable (OE)
OE controls the impedance ofthe output buffers. When OE is high, the buffers will remain in the high-impedance
state. Bringing OE low during a normal cycle will activate the output buffers, putting them in the low-impedance
state. It is necessary for both RAS and xCAS to be brought low for the output buffers to go into low-impedance
state, they will remain in the low-impedance state until either OE or xCAS is brought high.
RAS-only refresh
A refresh operation must be performed at least once every sixty-four milliseconds (512 ms for TMS416160P)
to retain data. This can be achieved by strobing each of the 4096 rows (AO-A 11). A normal read or write cycle
will refresh all bits in each row that is selected. A RAS-only operation can be used by holding all xCAS at the
high (inactive) level, thus conserving power as the output buffers remain in the high-impedance state. Externally
generated addresses must be used for a RAS-only refresh.
hidden refresh
Hidden refresh may be performed while maintaining valid data at the output pin. This is accomplished by holding
xCAS at VIL after a read operation and cycling RAS after a specified precharge period, similar to a RAS-only
refresh cycle.
xCAS-before-RAS refresh
xCAS-before-RAS refresh is utilized by bringing at .least one xCAS low earlier than RAS (see parameter tCSR)
and holding it low after RAS falls (see parameter tCHR). For successive xCAS-before-RAS refresh cycles,
xCAS can remain low while cycling RAS. The external address is ignored and the refresh address is generated
internally. The external address is also ignored during the hidden refresh option.
A low-power battery-backup refresh mode that requires less than 500 ~ refresh current is available on the
TMS416160P. Data integrity is maintained using xCAS-before-RAS refresh with a period of 125 !ls while holding
RAS low for less than 1 !ls. To minimize current consumption, all input levels need to be at CMOS levels
(VIL < 0.2 V, VIH > VCC - 0.2 V).
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
4-255
3:
w
:>w
a:
a..
....
o
:::J
C
oa:
a..
TMS416160, TMS416160P
1048 576·WORD BY 16·BIT HIGH·SPEED
DYNAMIC RANDOM·ACCESS MEMORIES
SMKS660-DECEMBER 1992
self refresh (TMS416160P)
The self-refresh mode is entered by dropping xCAS low prior to RAS going low. Then xCAS and RAS are both
held low for a minimum of 100 IJS. The chip is then refreshed internally by an on-board oscillator. No external
address is required since the CBR counter is used to keep track of the address. To exit the self-refresh mode
both RAS and xCAS are brought high to satisfy tCHS' Upon exiting self-refresh mode, a burst refresh (refresh
a full set of row addresses) must be executed before continuing with normal operation. The burst refresh
ensures the DRAM is fully refreshed.
power up
To achieve proper device operation, an initial pause of 200 f.ts followed by a minimum of eight RAS cycles is
required after power up to the full VCC level.
."
JJ
o
C
C
o
-I
."
JJ
m
S
m
==
TEXAS ~
INSTRUMENTS
4-256
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
TMS416160, TMS416160P
1048 576·WORD BY 16·BIT HIGH·SPEED
DYNAMIC RANDOM·ACCESS MEMORIES
SMKS660-DECEMBER 1992
logic symbol t
RAM1Mx16
17
18
A1
19
A2
20
A3
23
A4
24
A5
25
A6
26
A7
27
A8
28
A9
16
A10
15
A11
AO
14
31
2008/21DO '
0
A 1 048575
p:
p:
20015/2107
20016
20017
20018
20019
I> C20[ROW)
G23/[REFRESH ROW)
24[PWR OWN)
I>
C21
G24
&
;:
W
:;
23C22
31
30
~
I>
&
r.,
31
Z31
W
13
OE 29
000
2
001 3
002 4
003
004
005
006
007
008
009
0010
0011
0012
0013
5
7
8
9
10
33
23,210
I'-
w
a:
C21
G34
a.
23C32
....
o
+
~,25EN27
::J
o
o
34,25EN37
25
r
A,220
L.- \,26,27
a:
a.
A,Z26
.
A,320
\'36,37
L
34
35
A,Z36
36
38
39
40
0014
41
0015
t This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
The pin numbers shown correspond to the RE package.
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
4-257
TMS416160, TMS416160P
1048 576·WORD BY 16·BIT HIGH·SPEED
DYNAMIC RANDOM·ACCESS MEMORIES
SMKS66G-DECEMBER 1992
functional block diagram
-t t + J +
I
I
AO
A1
A7
t
11
I
7
/
•
•
•
•
Column
Address
Buffers
•
•
-
"
ABA11
256KArray
~
32<
•
••
256KArray
R
0
L±
256KArray
•
••
w
0
e
> 32
1/0
Buffers
16 of 32
Selection
C
12
0
/
d
e
256KArray
'-
12
.,
~
In
, Reg.
~
Data
Out
Reg.
OQOOQ15
256KArray
I
Supply voltage range on any pin (see Note 1) .......................................... - 1 V to 7 V
Supply voltage range on Vee ......................................................... - 1 V to 7 V
Short circuit output current ............................................................... , 50 mA
Power dissipation .......................................................................... 1 W
Operating free-air temperature range .................................................. O°C to 70°C
Storage temperature range ....................................................... - 55°C to 125°C
:c
m
=E
1
absolute maximum ratings over operating free-air temperature range (unless otherwise noted}t
-I
"m
\-I-
Sense Amplifiers
256KArray
Row
Address
Buffers
.~
Column Decode
L
:c
o
c
c
(')
Timing and Control
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. This is a stress rating only, and
functional operation of the device at these or any other conditions beyond those indicated in the "recommended operating conditions" section
of this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values in this data sheet are with respect to VSS.
recommended operating conditions
MIN
NOM
MAX
4.5
5
5.5
UNIT
V
Vee
Supply voltage
VSS
Supply voltage
VIH
High-level input voltage
2.4
6.5
VIL
Low-level input voltage (see Note 2)
-1
0.8
V
TA
Operating free-air temperature
0
70
·e
V
0
V
NOTE 2: The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used in this data sheet for
logic voHage levels only.
TEXAS
~
INSfRUMENTS
4-258
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
TMS416160, TMS416160P
1048 576·WORD BY 16·BIT HIGH·SPEED
DYNAMIC RANDOM·ACCESS MEMORIES
SMKS66(}-DECEMBER 1992
electrical characteristics over full ranges of recommended operating conditions (unless otherwise
noted)
PARAMETER
MIN
VOH
High-level output
voltage
10H =-5mA
VOL
Low-level output
voltage
IOL=4.2 rnA
II
Input current
(leakage)
10
ICC1 H
MAX
2.4
MIN
'416160-80
'416160P-80
MAX
2.4
MIN
UNIT
MAX
2.4
V
0.4
0.4
0.4
V
VCC = 5.5 V, VI = 0 to 6.5 V,
All other pins = 0 V to VCC
±10
±10
±10
flA
Output current
(leakage)
VCC = 5.5 V, Vo = 0 to VCC, xCAS high
±10
±10
±10
flA
Read or write cycle
current
VCC = 5.5 V, Minimum cycle
90
80
70
rnA
2
2
2
rnA
1
1
1
rnA
500
500
500
'f!A
VIH = 2.4 V (TTL),
After 1 memory cycle,
RAS and xCAS high
ICC2
'416160-70
'416160P-70
'416160-60
'416160P-60
TEST CONDITIONS
Standby current
VIH = VCC - 0.2 V (CMOS),
After 1 memory cycle,
RAS and xCAS high
'416160
'4161S0P
ICC3*
Average refresh
current (RAS-only
orCBR)
VCC = 5.5 V, Minimum cycle,
RAS cycling, xCAS high (RAS only)
RAS low after xCAS low (CBR)
90
80
70
rnA
ICC4 t §
Average page current
VCC = 5.5 V, tpc = minimum,
RAS low, xCAS cycling
90
80
70
rnA
ICCSII
Self refresh
CAS < 0.2 V, RAS < 0.2 V,
Measured after tRASS minimum
500
500
500
f!A
ICC7 t
Standby current,
outputs enabled
RAS = VIH, xCAS = VIL,
Data out = enabled
5
5
5
rnA
ICC10 11
Battery back-up
operating current
(equivalent refresh
time is 512 ms).
CBRonly.
tRC = 125 fls, tRAS S 1 Ils,
VCC-0.2V S VIH S 6.5 V,
V ",VIL'" 0.2 V, Wand OE = VIH,
Address and Data stable
500
500
5'00
flA
o
a.
l-
t.)
::J
C
o
a:
t Measured with outputs open.
* Measured with a maximum of one address change while RAS = VIL.
§ Measured with a maximum of one address change while xCAS = VIH.
II For TMS416160P only.
TEXAS ~
INSI'RUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
3:
->w
w
a:
4-259
a.
TMS416160, TMS416160P
1048 576·WORD BY 16·BIT HIGH·SPEED
DYNAMIC RANDOM·ACCESS MEMORIES
SMKS661H>ECEMBER 1992
capacitance over recommended ranges of supply voltage and operating free-air temperature,
f = 1 MHz (see Note 3)
PARAMETER
MIN
TYP
MAX
UNIT
Ci(A)
Input capacitance, address inputs
5
pF
Ci(OE)
Input capacitance, output enable
7
pF
Ci(RC)
Input capacitance, strobe inputs
7
pF
Ci(W)
Input capacitance, write-enable Input
7
pF
Co
Output capacitance
7
pF
NOTE 3: VCC equal to 5 V:t: 0.5 V and the bias on pins under test IS 0 V.
"tJ
l]
oc
c
o
-I
"tJ
l]
m
S
m
:e
TEXAS ~
INSTRUMENTS
4-260
POST OFFICE BOX 1443 • HOUSTON, TEXAS nOO1
TMS416160, TMS416160P
1048 576-WORD BY 16-BIT HIGH-SPEED
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS66(}-DECEMBER 1992
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature
'416160-60
' 416160P-60
PARAMETER
MIN
'416160-70
'416160P-70
MAX
MIN
MAX
'416160-80
'416160P-80
MIN
UNIT
MAX
tCAC
Access time from xCAS low
15
18
20
ns
tAA
Access time from column address
30
35
40
ns
tRAC
Access time from RAS low
60
70
80
ns
toEA
Access time from OE low
15
18
20
ns
tCPA
Access time from column precharge
35
40
45
ns
leLZ
Delay time, xCAS low to output in low Z
0
0
0
ns
toH
Output data hold time (from xCAS)
3
3
3
ns
toHO
Output data hold time (from OE)
3
3
3
tOFF
Output disable time after xCAS high (see Note 4)
0
15
0
18
0
20
ns
toEZ
Output disable time after OE high (see Note 4)
0
15
0
18
0
20
ns
ns
NOTE 4: tOFF and tOEZ are specified when the output is no longer driven.
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (see Note 5)
'416160-60
'416160P-60
MIN
MAX
'416160-70
'416160P-70
MIN
MAX
'416160-80
'416160P-80
MIN
UNIT
MAX
tRC
Read cycle time (see Note 6)
110
130
150
ns
\wc
Write cycle time
110
130
150
ns
tRWC
Read-write/read-modify-write cycle time
155
181
205
ns
tPRWC
Page-mode read-modify-write cycle time
85
96
105
ns
tRASP
Page-mode pulse duration, RAS low (see Note 8)
60
100000
70
100000
80
100000
ns
tRAS
Non-page-mode pulse duration, RAS low (see Note 8)
60
10000
70
10000
80
10000
ns
tCAS
Pulse duration, xCAS low (see Note 9)
15
10000
18
10000
20
10000
ns
lep
Pulse duration, xCAS high (precharge)
10
10
10
ns
tRP
Pulse duration, RAS high (precharge)
40
50
60
ns
\wP
Write pulse duration
15
15
15
ns
tASC
Column-address setup time before xCAS low
0
0
0
ns
tASR
Row-address setup time before RAS low
0
0
0
ns
tDS
Data setup time before W low (see Note 10)
0
0
0
ns
tRCS
Read setup time before xCAS low
0
0
0
ns
tCWL
W-Iow setup time before xCAS high
15
18
20
ns
NOTES:
5. Timing measurements are referenced to VIL max and VIH min.
6. All cycle times assume IT = 5 ns.
7. tpc > tcp min + tCAS min + 2tr.
8. In a read-modify-wr~ecycle, tRWD and tRWL must be observed. Depending on the user's transition times, this may require additional
RAS low time (tRAS).
9. In a read-modify-write cycle, tCWD and tCWL must be observed. Depending on the user's transition times, this may require additional
xCAS low time (tCAS).
10. Reference to the first xCAS or W, whichever occurs last.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
4-261
3:
->w
w
a:
a.
.....
U
~
C
o
a:
a.
TMS416160, TMS416160P
1 048 576·WORD BY 16·BIT HIGH·SPEED
DYNAMIC RANDOM·ACCESS MEMORIES
SMKS66G-DECEMBER 1992
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (continued) (see Note 5)
'416160-60
'416160P-60
MIN
MAX
'416160-70
'416160P-70
MIN
MAX
'416160-80
'416160P-60
MIN
UNIT
MAX
tRWL
W-Iow setup time before RAS high
15
18
20
ns
twcs
W-Iow setup time before xCAS low
0
0
0
ns
tCAH
Column-address hold time after xCAS low
10
15
15
ns
tDH
Data hold time after xCAS low (see Note 10)
10
15
15
ns
tRAH
Row-address hold time after RAS low
10
10
10
ns
tRCH
Read hold time after xCAS high (see Note 13)
0
0
0
ns
tRRH
Read hold time after RAS high (see Note 13)
5
5
5
ns
twCH
Write hold time after xCAS low (see Note 12)
15
15
15
ns
tCLCH
Hold time, xCAS low to xCAS high
5
5
5
ns
tAWD
Delay time, column address to W low (see Note 14)
55
63
70
ns
tCHR
Delay time, RAS low to xCAS high (see Note 11)
20
20
20
ns
tCRP
Delay time, xCAS high to RAS low
5
5
5
ns
"tJ
tCSH
Delay time, RAS low to xCAS high
60
70
80
ns
o
tCSR
Delay time, xCAS low to RAS low (see Note 11)
10
10
10
ns
tCWD
Delay time, xCAS low to W low (see Note 14)
40
46
50
ns
tOEH
OE command hold time
15
18
20
ns
tOED
Delay time, OE high before data at DQ
15
18
20
ns
tROH
Delay time, OE low to RAS high
.10
10
10
tRAD
Delay time, RAS low to column address (see Note 15)
15
tRAL
Delay time, column address to RAS high
30
35
40
tCAL
Delay time, column address to xCAS high
30
35
40
tRCD
Delay time, RAS low to xCAS low (see Note 15)
20
tRPC
Delay time, RAS high to xCAS low
tRSH
Delay time, xCAS low to RAS high
15
tRWD
Delay time, RAS low to W low (see Note 14)
85
tcpw
Delay time, W from xCAS precharge
60
tcPRH
RAS hold time from xCAS precharge
tCPR
xCAS precharge before self refresh
tRPS
RAS precharge after self refresh
:::c
c
c
o
-f
"tJ
:::c
m
S
m
=:
NOTES:
5.
10.
11.
12.
13.
14.
IS.
45
15
20
35
52
15
20
ns
40
ns
ns
ns
60
ns
0
ns
18
20
ns
98
110
ns
68
75
ns
35
40
45
ns
0
0
0
ns
110
130
150
ns
0
Timmg measurements are referenced to VIL max and VIH mm.
Reference to the first xCAS or W, whichever occurs last
xCAS-before-RAS refresh only.
Early write operation only.
Either tRRH or tRCH must be satisfied for a read cycle.
Read-modify-write operation only.
Maximum value specified only to assure access time.
TEXAS ~
INSTRUMENTS
4-262
30
POST OFFICE BOX 1443· HOUSTON. TEXAS 77001
0
TMS416160, TMS416160P
1 048 576·WORD BY 16·BIT HIGH·SPEED
DYNAMIC RANDOM·ACCESS MEMORIES
SMKS66D-OECEMBER 1992
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (concluded) (see Note 5)
'416160-60
'416160P-60
MIN
tRASS
Self refresh entry from RAS low
tCHS
xCAS low hold time after RAS high (self refresh)
tREF
Refresh time interval (TMS416160)
'416160-70
'416160P-70
MAX
MIN
tREF
Refresh time interval, low power (TMS416160P only)
Transition time
MAX
MIN
100
100
100
-50
-50
-50
64
IT
'416160-80
'416160P-80
64
512
512
3
30
3
30
3
UNIT
MAX
!,s
ns
64
ms
512
ms
30
ns
NOTES: 5. Timing measurements are referenced to VIL max and VIH min.
PARAMETER MEASUREMENT INFORMATION
VCC = 5V
1.31 V
~
w
:>w
a:
a..
Output Under Test - - - . - - - - .
Output Under Test
CL = 100 pF
I
T
t-
(b) Alternate Load Circuit
(a) Load Circuit
O
::l
Figure 1. Load Circuits for Timing Parameters
C
o
a:
a..
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
4-263
TMS416160, TMS416160P
1048 576·WORD BY 16·BIT HIGH·SPEED
DYNAMIC RANDOM·ACCESS MEMORIES
SMKS66G-DECEMBER 1992
PARAMETER MEASUREMENT INFORMATION
"tJ
JJ
o
C
c:
o
-I
"tJ
w
I
I
JJ
m
S
m
=E
~tCAC-.l
I (see Note B)
I
I ~
I
I
~tAA--+j
tCLZ~
DQO-DQ15
NOTES: A.
B.
C.
D.
(see Note D)
I
-.I
I
I+-- tOH--+I
I
z-------------~--~
Valid Data Out
In order to hold the address latched by the first xCAS going low, the parameter tCLCH must be met.
tCAC is measured from xCAS to its corresponding DQx.
xCAS order is arbitrary.
Output may go from high-impedance to an invalid data state prior to the specified access time.
Figure 2. Read Cycle Timing
TEXAS ~
INSTRUMENTS
4-264
I
tOFF
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
TMS416160, TMS416160P
1 048 576-WORD BY 16-BIT HIGH-SPEED
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS660-DECEMBER 1992
PARAMETER MEASUREMENT INFORMATION
LCAS
-.I
I
I
I
I
I
I
AD-A11
~
3:
w
:>w
a::
0..
IU
::>
C
oa::
DQD-DQ15
I
I
I+-- toED -+t
I
0..
"'-.,..."""""""." Don't Care
Valid Data-In
,......-.t--+- tDS (see Note C)
I
14
tOEH
----'~
NOTES: A. In order to hold the address latched by the first xCAS going low, the parameter tCLCH must be met.
B. xCAS order is arbitrary.
C. Reference to the first xCAS or 'ii, whichever occurs last.
Figure 3. Write Cycle Timing
TEXAS ~
INsrRUMENTS
POST OFFICE BOX 1443· HOUSTON. TEXAS 77001
4-265
TMS416160, TMS416160P
1048 576·WORD BY 16·BIT HIGH·SPEED
DYNAMIC RANDOM·ACCESS MEMORIES
SMKS660-0ECEMBER 1992
PARAMETER MEASUREMENT INFORMATION
"'C
:0
o
AO-A11
C
C
o
-t
w
"'C
:0
m
:S
m
OQO-OQ15
:E
NOTES: A. In order to hold the address latched by the first xCAS going low, the parameter tCLCH must be met.
B. xCAS order is arbitrary.
.
Figure 4. Early Write Cycle Timing
TEXAS ~
INsrRUMENTS
4·266
POST OFFICE BOX 1443' HOUSTON. TEXAS 77001
· TMS416160, TMS416160P
1048 576·WORD BY 16·BIT HIGH·SPEED
DYNAMIC RANDOM·ACCESS MEMORIES
SMKS66(}-OECEMBER 1992
PARAMETER MEASUREMENT INFORMATION
3:
w
AO-A11
:>w
a:
c.
I(J
::J
C
o
~
I
~
tOHO
i
a:
c.
~tDH
II
I
.~tDS
I ~tOEZ
I
I I
I
I
~~
~
iI tOED
I I
(see Note D)
DQO-DQ7
NOTES: A.
B.
C.
D.
In order to hold the address latched by the first xCAS going low. the parameter tCLCH must be met.
xCAS order is arbitrary.
tCAC in measured from xCAS to its corresponding DQx.
Output might go from a high-impedance state to an invalid data state prior to the specified access time.
Figure 5. Read-Modify-Write Cycle Timing
TEXAS ~
INSfRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
4-267
TMS416160, TMS416160P
1048 576·WORD BY 16·BIT HIGH·SPEED
DYNAMIC RANDOM·ACCESS MEMORIES
SMKS66Q-OECEMBER 1992
PARAMETER MEASUREMENT INFORMATION
'N
I
I
I
I
I
I
~tCR~ ~
I
~
I
~
I
I
I
I
I
tCLCH
(aee Not~ A)
~
I
~
tCPRH!
"'I
~
.1
~
tCSH~
I
I
"'
I
:rJ
o
II
AO-A11
C
VVVVVVVVVV
t
C
RAD
~
1-
"I 1 1
L
o
w ~I
NEYOi
i1
::
I I
"tJ
I
I
I
1
I I I
-t
::D
m
<
-m
:E
II
r--
"0
tRCS
Ir-:I
i4
(aee Note D)
I"
tCAC
:I
~ I
' tRAC
~
I
1
j+H--tAA
tCLZ
DQ8-DQ15
--1~
'0':
111
II
I~
1
I
1
~
1
~I:
tCPA
1
(see Note F)
~
I:
~
I
alld
Don't Care
'V\./V'dV\/\/\/
i4-+t- tRRH
14-- tRCH - - - . ,
~
Out
I
I I
II
jill I
I
~%~~~~
_ ...... -
.1
tOH
1
~I II ::
I:
1
I ~
tOFF
I
____ I
I 4>1 L tOEZ
I
I 1-
-!-I_ _-;._ _ _ _ _ _ _ _ __
~
tAA --+i
: I
~---'-...,;
alld
.
Valid ~
(aee Note D)
DQO-DQ7
'Out
I
I
I
tO~A
C
I"
I
J1 I+-t
OE
I
I
I I
I I
I I
I I
II
tRSH
,tpc
I
I
I
I
I
I
I
tCAS~
~I
I
I
:
I
I
I ~tcp~
I
-----~---+--!oiA-S-R-----+11""""\.1
: /1
"' I
I
I
I
'L-....II
\,
II
I tRAH ~
I
I
1~I I
I I
I
I -41 ~ tASC
I
tCAL ~ I
I I
I
I I I I ~ tCAH
1
JII l
tRAL
~ I
1 ~~~~7\. .1o--~ ~~~~~~~~~~~
1
1 1.101...I...I.i"~
~
LCAS
.1
~
tRASP
14- tRCD ~
________~I----~ I
UCAS
,j4
tRP
§§2~:~'r~aI~~~tOEA ~
I
l120l
.:
tOHO
Out.
'/>----------
~
r -;1-"-- tOHO
I
~~*~~~~~
NOTES: A.
B.
C.
D.
E.
In order to hold the address latched by the first xCAS going low, the parameter tCLCH must be met.
tCAC is measured from xCAS to its corresponding DOx.
xCAS order is arbitrary.
Output may go from high·impedance to an invalid data state prior to the specified access time.
A write cycle or read-modify-write cycle can be mixed with the read cycles as long as the write and read-modify-write timing
specifications are not violated.
F. Access time is tCPA or tAA dependent.
Figure 6. Enhanced Page-Mode Read Cycle Timing
.
TEXAS ~
INSTRUMENTS
4-268
POST OFFICE BOX 1443· HOUSTON. TEXAS 77001
TMS416160, TMS416160P
1048 576·WORD BY 16·BIT HIGH·SPEED
DYNAMIC RANDOM·ACCESS MEMORIES
SMKS660-0ECEMBER 1992
PARAMETER MEASUREMENT INFORMATION
tRP~
NI"-~f--_-_-_-_~-_-_~~-_-_-_-_-_-_-_-_-_-=-_tR_A_SP_-------_-_-_-_-_-_-_-_-_~~~-=--=--IfI\_
I I
::
I I
:
I
I
I
~
\
(
I
I+- IClCH -----..,I
14-- IRCD ~ (see NOle A) :
~
I
I
:
~
I
CSH
I
t ASC ....:
-+I i+- tRAH I
$1_ _"i.,1
I
~
.1
I
I
r~
r
Y
N
I 'j4--tCAS~
I -,
1I
~14-~rl tASR
:
I
I
I
tCAH
14-t:
1
I I
~~*g~~iru
I
~
tCPRH
tpc
tcp
.1
H
-1 :
,X
I
I
i :I
I
tCRP
I
I
I
I
.1
~ tCAl --~~
14
IRAl
I
I
I
/
-----"!'I
I
lO;._
~
:
~"""''''''''~~~~'''''''~-=
I
I
tDS~
VI
:
I
I
14
I tcWl
I
j+-- IWp ---.!
I
~
.:
----+j
:
AO-All
(see Note D)
IRSH
1"'1
Column
~ ICWl ~
I
:5=
w
I
I
:.;
w
a:
I4jo11--- IRWl ---.l~
twCH
:
I
0..
I
0§ZgHb*re~~
....
o
I
::J
C
o
a:
0..
NOTES: A. In order to hold the address latched by the first xCAS going low, the parameter tCLCH must be met.
B. xCAS order is arbitrary.
C. A read cycle or read-modify-write cycle can be mixed with the write cycles as long as the read and read-modify-write timing
specifications are not violated.
D. Referenced 10 the first xCAS or \N, whichever occurs last.
Figure 7. Enhanced Page-Mode Write Cycle Timing
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
4-269
TMS416160, TMS416160P
1 048 576·WORD BY 16·BIT HIGH·SPEED
DYNAMIC RANDOM·ACCESS MEMORIES
SMKS660-0ECEMBER 1992
PARAMETER MEASUREMENT INFORMATION
"tJ
:IJ
o
C
C
(")
tOEH
-I
"tJ
:IJ
m
:S
m
DQO-DQ15
--------o<:>r.
Valid Out
i+- tOEA ~
1
-+I
:E
1
OE . .
tOEZ
.1
1
tOEH
1
1
1
~1,4---+!.1-
1
1
tOED
1
/io---....."j\___. _...J/io----"""'~...,~~.....
I
1
NOTES: A.
B.
C.
D.
E.
In order to hold the address latched by the first xCAS going low, the parameter tCLCH must be met.
tCAC is measured from xCAS to its corresponding DQx.
xCAS order is arbitrary.
Output may go from high-impedance to an invalid data state prior to the specified access time.
A read or write cycle can be intermixed with read-modify-write cycles as long as the read and write cycle timing specifications are
not violated.
F. Access time is tCPA or tAA dependent.
Figure 8. Enhanced Page-Mode Read-Modify-Write Cycle Timing
TEXAS ."
INsrRUMENTS
4-270
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
TMS416160, TMS416160P
1048 576·WORD BY 16·BIT HIGH·SPEED
DYNAMIC RANDOM·ACCESS MEMORIES
SMKS66(}-OECEMBER 1992
PARAMETER MEASUREMENT INFORMATION
3:
w
OQO-OQ15 - - - - - - - - - - - - - HI-Z - - - - - - - - - - - - - - -
:>
w
a:
a.
NOTE A: All xCAS must be high.
I(J
Figure 9_ RAS·Only Refresh Timing
::J
C
o
a:
a.
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
4-271
TMS416160, TMS416160P
1048 576·WORD BY 16·BIT HIGH·SPEED
DYNAMIC RANDOM·ACCESS MEMORIES
SMKS660-DECEMBER 1992
PARAMETER MEASUREMENT INFORMATION
"'C
:l]
o
c
o
c
-I
"'C
:l]
m
<
m
=E
Figure 10. Hidden Refresh Cycle Timing
-
TEXAS ~
INsrRUMENTS
4-272
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
TMS416160, TMS416160P
1048 576·WORD BY 16·BIT HIGH·SPEED
DYNAMIC RANDOM·ACCESS MEMORIES
SMKS66(}-OECEMBER 1992
PARAMETER MEASUREMENT INFORMATION
~~-------------------lRC----------------~·1
I+-- tRP ~
I
I
Irl----
A
NY
I
I I
RM
tRPC
xCAS
114
4- - - - - - - - - - - tRAS ____________~.I
II
-+I
~ tcSR
\l
i :4--..
~
lCHR
--------~.I
Y
j+- tr
;:
w
OQO-OQ15;--------------HI·Z - - - - - - - - - - - - - NOTES: A. Any xCAS may be used.
:>
w
a:
a.
...o
Figure 11. Automatic (CAS-Before-RAS) Refresh Cycle Timing
::)
c
o
a:
a.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
4-273
TMS416160, TMS416160P
1048 576·WORD BY 16·BIT HIGH·SPEED
DYNAMIC RANDOM·ACCESS MEMORIES
SMKS660-0ECEMBER 1992
PARAMETER MEASUREMENT INFORMATION
1'..I 1f - - - - - I
1
~
~
1
1 ~---------..::I 1
tRPC -I+----+j
tCSR
~ tRPS ~
1
+.i ~
1
xCAS
----+1.1
N
A
_ _....J
tRASS
1
1
:
~
I
Jir,---~N
1+
tCHS
~If!'.~~~~
1
I
~ tCPR ~
AO-AI1
w~*m*:~
."
oE~*;mi':~
::D
o
C
i+--
-+J
c
o-I
~*;i~*:~
DQO-DQ15
toFF
WS----------
HI-Z - - - - - - - - - - - -
."
::D
m
S
m
=E
Figure 12. Self Refresh Timing
device symbolization
t~
TI
~ TMS416160~
W
A
Speed (-60, -70, -80)
Low Power/Refresh Option
Package Code
~T
!:fh
Lot Traceability Code
Date Code
Assembly Site Code
Ole Revision Code
Wafer Fab Code
TEXAS
~
INsrRUMENTS
4-274
POST OFFICE BOX 1443· HOUSTON, TEXAS 77001
TMS426160, TMS426160P
1048 576·WORD BY 16·BIT HIGH·SPEED
LOW VOLTAGE DYNAMIC RANDOM·ACCESS MEMORIES
SMKS266-DECEMBER 1992
•
•
•
Single 3.3-V Supply (± 0.3 V Tolerance)
Performance Ranges:
'426160/P-70
'4261601P-80
ACCESS ACCESS ACCESS READ OR
TIME
TIME
TIME
WRITE
tRAC
tCAC
tAA
CYCLE
MAX
MAX
MAX
MIN
70ns
l8ns
130 ns
35 ns
80 ns
20 ns
40 ns
150 ns
•
Enhanced Page Mode Operation With
CAS-Before-RAS _Refresh
•
Long Refresh Period ...
4096-Cycle Refresh in 64 ms (Max)
512 ms Max for Low-Power, Self-Refresh
Version (TMS426160P)
•
•
•
All Inputs, Outputs, and Clocks are TTL
Compatible
•
High-Reliability Plastic 42-Lead
400-Mil-Wide Surface Mount (SOJ)
Package, and 44/50-Lead Thin Small
Outline Package (TSOP)
•
•
1
003
VCC
004
005
Vii
Low Power Dissipation
- 100 j.lA CMOS Standby
- 100 j.tA Extended Refresh Battery Backup
Self-Refresh with Low Power
VCC
000
001
0Q7
NC
NC
3-State Unlatched Output
•
DCPACKAGEt
(TOP VIEW)
RE PACKAGEt
(TOP VIEW)
Organization ... 1 048576 x 16
RAS
A11
A10
AO
A1
A2
A3
VCC
Vss
0015
0014
0013
0012
Vss
0011
0010
009
008
NC
LCAS
UCAS
VCC
000
001
003
VCC
004
005
D06
DO?
NC
9
Vss
0015
0014
0013
0012
Vss
0011
0010
009
D08
NC
OE
A9
A8
A?
A6
A5
A4
Vss
NC
NC
Vii
RAS
A11
A10
AO
A1
A2
A3
VCC
NC
LCAS
UCAS
OE
A9
A8
A?
AS
A5
A4
VSS
t Packages are shown for pinout reference only.
Operating Free-Air Temperature Range
O°C to 70°C
Texas Instruments EPIC ™ CMOS Process
description
The TMS426160 series are high-speed, low
voltage, 16 777 216-bit dynamic random-access
memories organized as 1 048 576 words of
sixteen bits each.
DQO-DQ15
LCAS
UCAS
NC
OE
RAS
IN
VCC
VSS
These devices feature maximum RAS access times of 70 ns and 80 ns. Maximum power dissipation is as low
as 0.36 mW standby and battery backup on 80-ns devices.
All inputs and outputs, including clocks, are compatible with Series 74 TTL. All addresses and data-in lines are
latched on-chip to simplify system design. Data out is unlatched to allow greater system flexibility.
EPIC is a trademark of Texas Instruments Incorporated.
TEXAS
~
Copyright © 1992. Texas Instruments Incorporated
INsrRUMENTS
POST OFFICE BOX 1443· HOUSTON. TEXAS 77001
D.
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They employ state-of-the-art EPIC'" (Enhanced Performance Implanted CMOS) technology for high
performance, reliability, and low power at low cost.
Ghlng. or diltontinul th... prochu;tt whhout notice.
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D.
Address Inputs
Data In/Data Out
Lower Column-Address Strobe
Upper Column-Address Strobe
No Internal Connection
Output Enable
Row-Address Strobe
Write Enable
3.3-V Supply
Ground
The TMS426160P series are high-speed, low voltage, low-power, self-refresh, 16 777 216-bit dynamic
random-access memories organized as 1 048 576 words of sixteen bits each.
PRODUCT PREVIEW information concern. producllin thl formlUvt 01
design ph... of development Char.ct,rlltlc dall and other
'pectfieatJont are d..lgn g011l. TUllln.trument. reurv•• the right 1o
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0
PIN NOMENCLATURE
AO-A11
3:
W
4-275
TMS426160, TMS426160P
1048 576·WORD BY 16·BIT HIGH·SPEED
LOW VOLTAGE DYNAMIC RANDOM-ACCESS MEMORIES
SMKS266-DECEMBER 1992
The TMS426160 and TMS426160P are each offered in a 42-lead plastic surface mount SOJ (RE suffix)
package, and a 44/S0-lead plastic surface mount TSOP (DC suffix). These packages are characterized for
operation from O°C to 70°C.
operation
dual CAS
Two CAS pins (LCAS-UCAS) are provided to give independent control of the sixteen data I/O pins
(000--001S), with LCAS corresponding to 000--007 and UCAS corresponding to 008--001S. For read or
write cycles, the column address is latched on the first xCAS falling edge. Each xCAS pin going low enables
its corresponding DO pin with data coming from the column address to be latched on the first falling xCAS edge.
All address setup and hold parameters are referenced to the first falling xCASedge.The delay time from xCAS
low to valid data out (see parameter tCAd is measured from each individual CAS to its corresponding OOx pin.
In order to latch in a new column address, all xCAS pins must be brought high. The column precharge time (see
parameter tcp) is measured from the last xCAS rising edge to the first falling xCAS edge of the new cycle.
Keeping a column address valid while toggling xCAS requires a minimum setup time, tClCH' During tClCH, at
least one xCAS must be brought low before the other xCAS is taken high.
For early write cycles, the data is latched on the first falling xCAS edge. Only the ~Os that have the
corresponding xCAS low will be written into. Each xCAS will have to meet tCAS minimum in order to ensure
writing into the storage cell. In order to latch a new address and new data, all xCAS pins need to come
high and meet tCp.
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page mode
Page-mode operation allows faster memory access by keeping the same row address while selecting random
column addresses. The time for row-address setup and hold and address multiplex is thus eliminated. The
maximum number of columns that may be accessed is determined by the maximum RAS low time and the xCAS
page-mode cycle time used. With minimum xCAS page cycle time, all 256 columns specified by column
addresses AO through A7 can be accessed without intervening RAS cycles.
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Unlike conventional page-mode DRAMs, the column-address buffers in this device are activated on the falling
edge of RAS. The buffers act as transparent or flow-through latches while xCAS is high. The falling edge of the
first xCAS latches the column addresses. This feature allows the devices to operate at a higher data bandwidth
than conventional page-mode parts, because data retrieval begins as soon as column address is valid rather
than when xCAS transitions low. This performance improvement is referred to as enhanced page mode. Valid
column address may be presented immediately after tRAH (row address hold time) has been satisfied, usually
well in advance ofthe falling edge of xCAS. In this case, data is obtained after tCAC max (access time from xCAS
low) if tAA max (access time from column address) has been satisfied. In the event that column addresses for
the next page cycle are valid at the time xCAS goes high, minimum access time for the next cycle is determined
by tePA (access time from rising edge of the last xCAS).
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address (AD-A11)
Twenty address bits are required to decode 1 of 1 048 576 storage cell locations. Twelve row-address bits are
set up on pins AO through A 11 and latched onto the chip by RAS. Then, eight column-address bits are set up
on pins AO through A7 and latched onto the chip by the first xCAS. All addresses must be stable on or before
the falling edge of RAS and xCAS. RAS is similar to a chip enable in that it activates the sense amplifiers as
well as the row decoder. xCAS is used as a chip select, activating its corresponding output buffer and latching
the address bits into the column-address buffers.
TEXAS ."
INSTRUMENTS
4-276
POST OFFICE BOX 1443· HOUSTON, TEXAS 77001
TMS426160, TMS426160P
1 048 576·WORD BY 16·BIT HIGH·SPEED
LOW VOLTAGE DYNAMIC RANDOM·ACCESS MEMORIES
SMKS266-DECEMBER 1992
write enable (W)
The read or write mode is selected through the W input. A logic high on the W input selects the read mode and
a logic low selects the write mode. The write-enable terminal can be driven from the standard TTL circuits without
a pullup resistor. The data inputs are disabled when the read mode is selected. When W goes low prior to xCAS
(early write), data out will remain in the high-impedance state for the entire cycle permitting a write operation
with OE grounded.
data In (OQO-OQ15)
Data is written during a write or read-modify-write cycle. Depending on the mode of operation, the falling edge
of xCAS or W strobes data into the on-chip data latch. In an early-write cycle, W is brought low prior to xCAS
and the data is strobed in by the first occurring xCAS with setup and hold times referenced to this signal. In a
delayed-write or read-modify-write cycle, xCAS will already be low, thus the data will be strobed in by W with
setup and hold times referenced to this signal. In a delayed-write or read-modify-write cycle, OE must be high
to bring the output buffers to high impedance prior to impressing data on the I/O lines.
data out (OQO-OQ15)
The three-state output buffer provides direct TTL compatibility (no pullup resistor required) with a fanout of two
Series 74 TTL loads. Data out is the same polarity as data in. The output is in the high-impedance (floating) state
until xCAS and OE are brought low. In a read cycle, the output becomes valid after the access time interval tCAC
(which begins with the negative transition of xCAS) as long as tRAC and tAA are satisfied.
output enable (OE)
OE controls the impedance of the output buffers. When OE is high, the buffers will remain in the high-impedance
state. Bringing OE low during a normal cycle will activate the output buffers, putting them in the low-impedance
state. It is necessary for both RAS and xCAS to be brought low for the output buffers to go into low-impedance
state, they will remain in the low-impedance state until either OE or xCAS is brought high.
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RAS-only refresh
A refresh operation must be performed at least once every sixty-four milliseconds (512 ms for TMS426160P)
to retain data. This can be achieved by strobing each of the 4096 rows (AO-A 11). A normal read or write cycle
will refresh all bits in each row that is selected. A RAS-only operation can be used by holding all xCAS at the
high (inactive) level, thus conserving power as the output buffers remain in the high-impedance state. Externally
generated addresses must be used for a RAS-only refresh.
hidden refresh
Hidden refresh may be performed while maintaining valid data at the output pin. This is accomplished by holding
xCAS at VIL after a read operation and cycling RAS after a specified precharge period, similar to a RAS-only
refresh cycle.
xCAS-before-RAS refresh
xCAS-before-RAS refresh is utilized by bringing at least one xCAS low earlier than RAS (see parameter tCSR)
and holding it low after RAS falls (see parameter tCHR)' For successive xCAS-before-RAS refresh cycles,
xCAS can remain low while cycling RAS. The external address is ignored and the refresh address is generated
internally. The external address is also ignored during the hidden refresh option.
A low-power battery-backup refresh mode that requires less than 100 ~ refresh current is available on the
TMS426160P. Data integrity is maintained using xCAS-before-RAS refresh with a period of 125 ~s while holding
RAS low for less than 1 ~s. To minimize current consumption, all input levels need to be at CMOS levels
(VIL < 0.2 V, VIH > Vec - 0.2 V).
.
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
4-277
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TMS426160, TMS426160P
1048 576-WORD BY 16-BIT HIGH-SPEED
LOW VOLTAGE DYNAMIC RANDOM-ACCESS MEMORIES
SMKS266-DECEMBER 1992
self refresh (TMS426160P)
The self-refresh mode is entered by dropping xCAS low prior to RAS going low. Then xCAS and RAS are both
held low for a minimum of 100 !-Is. The chip is then refreshed internally by an on-board oscillator. No external
address is required since the CSR counter is used to keep track of the address. To exit the self-refresh mode
both RAS and xCAS are brought high to satisfy tCHS' Upon exiting self-refresh mode, a burst refresh (refresh
a full set of row addresses) must be executed before continuing with normal operation. The burst refresh
ensures the DRAM is fully refreshed.
power up
To achieve proper device operation, an initial pause of 200 !-IS followed by a minimum of eight RAS cycles is
required after power up to the full VCC level.
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TEXAS ~
INSTRUMENTS
4-278
POST OFFICE BOX 1443· HOUSTON, TEXAS 77001
TMS426160, TMS426160P
1048 576·WORD BY 16·BIT HIGH·SPEED
LOW VOLTAGE DYNAMIC RANDOM·ACCESS MEMORIES
SMKS266--DECEMBER 1992
logic symbol t
RAM1Mx16
17
AO
18
A1
19
A2
20
A3
23
A4
24
A5
25
A6
26
A7
27
A8
28
A9
16
A10
15
A11
2008/2100
> A 1 04~ 575
20015/2107
20016
20017
20018
,
20019
I> C20[ROW]
14
31
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G23/[REFRESH ROW]
24[PWROWNI
C21
G24
&
31
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w
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23C22
I> C21
30
F
G34
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&
31
Z31
W
13
OE 29
OQO
2
OQ1 3
OQ2 4
OQ3 5
OQ4 7
OQ5 8
OQ6 9
OQ7 10
33
OQ8
OQ9
OQ10
OQ11
OQ12
OQ13
OQ14
OQ15
34
35
36
38
39
40
41
23,210
23C32
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V26,27
A,Z26
L
A,320
V36,37
A,Z36
a..
tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
The pin numbers shown correspond to the RE package.
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
4-279
TMS426160, TMS426160P
1048 576·WORD BY 16·BIT HIGH·SPEED
LOW VOLTAGE DYNAMIC RANDOM"ACCESS MEMORIES
SMKS266-DECEMBER 1992
functional block diagram
RAS UCAS LCAS
*~
It
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AD
AI
A7
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A8All
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Sense Amplifiers
256KArray
256KArray
32
•
•
•
256KArray
R
0
•
•
w
•
0
e
c
12
-±
256KArray
32
I/O
Buffers
16 of 32
Selection
0
/
d
e
~
~
In
Reg.
Data
Out
Reg.
0000015
'--
256KArray
12
/
256KArray
1
Supply voltage range on any pin (see Note 1) ....................................... - 0.5 V to 4.6 V
Supply voltage range on Vee ...................................................... - 0.5 V to 4.6 V
Short circuit output current ................................................................ 50 mA
Power dissipation .......................................................................... 1 W
Operating free-air temperature range .................................................. O°C to 70°C
Storage temperature range ....................................................... - 55°C to 125°C
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absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
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Column Decode
Column
Address
Buffers
Row
Address
Buffers
t tI
I
7
L
•
•
•
OE
Timing a;d Control
/
•
•
•
W
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. This is a stress rating only, and
functional operation of the device at these or any other conditions beyond those indicated in the "recommended operating conditions" section
of this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values in this data sheet are with respect to VSS.
recommended operating conditions
vee
Supply voltage
VSS
Supply voltage
VIH
High-level input voltage
VIL
LOW-level input vo~age (see Note 2)
TA
Operating free-air temperature
NOM
MAX
3.0
3.3
3.6
0
..
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
UNIT
V
V
V
2.0
Vee+0.3
-0.3
O.B
V
0
70
'e
..IS deSignated as minimum,
..
NOTE 2: The algebraiC convenllOn, where the more negative (less positive) limit
logic voltage levels only.
4-280
MIN
IS
used
In
this data sheet for
TMS426160, TMS426160P
1 048 576·WORD BY 16·BIT HIGH·SPEED
LOW VOLTAGE DYNAMIC RANDOM·ACCESS MEMORIES
SMKS266-DECEMBER 1992
electrical characteristics over full ranges of recommended operating conditions (unless otherwise
noted)
PARAMETER
'426160-70
'426160P-70
TEST CONDITIONS
MIN
VOH
High-level output
voltage
10H =-2 mA
VOL
Low-level output voltage
IOL=2 mA
VOH
Option
VOL
Option
I!A
10L = 100 I!A
MIN
UNIT
MAX
2.4
0.4
IOH = -100
V
0.4
V
V
VCc-O· 2
VCc-O· 2
0.2
0.2
V
VCC = 3.6 V, VI = Oto 3.9 V,
All other pins = 0 V to VCC
±10
±10
flA
±10
±10
flA
80
70
mA
1
1
mA
'426160
300
300
I!A
'426160P
100
100
IlA
Input current (leakage)
10
Output current (leakage)
VCC = 3.6 V, Vo = 0 to VCC, xCAS high
ICCl t ;
Read or write cycle current
VCC = 3.6 V, Minimum cycle
VIH = 2 V (LVTTL),
After 1 memory cycle,
RAS and xCAS high
Standby current
MAX
2.4
II
ICC2
'426160-80
'426160P-80
VIH = VCC - 0.2 V (LVCMOS),
After 1 memory cycle,
RAS and xCAS high
ICC3;
Average refresh current (RAS-only
orCBR)
VCC = 3.6 V, Minimum cycle,
RAS cycling, xCAS high (RAS only)
RAS low after xCAS low (CBR)
80
70
mA
ICC4 t §
Average page current
VCC = 3.6 V, tpc = minimum,
RAS low, xCAS cycling
80
70
mA
ICC6~
Self refresh
CAS < 0.2 V, RAS < 0.2 V,
Measured after tRASS minimum
100
100
I!A
ICC7t
Standby current, outputs enabled
RAS = VIH, xCAS = VIL,
Data out = enabled
5
5
mA
ICC10~
Battery back-up operating current
(equivalent refresh time is 512 ms).
CBRonly.
tRC = 125 flS, tRAS '" 1 IlS,
VCC-0.2V ",VIH '" 3.9 V,
OV ",VIL" 0.2 V, 'Wand OE = VIH,
Address and Data stable
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100
100
IlA
t Measured with outputs open.
Measured with a maximum of one address change while RAS = VIL.
§ Measured with a maximum of one address change while xCAS = VIH.
~ For TMS426160P only.
*
TEXAS ~
INSfRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
3:
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4-281
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TMS426160, TMS426160P
1048 576·WORD BY 16·BIT HIGH·SPEED
LOW VOLTAGE DYNAMIC RANDOM·ACCESS MEMORIES
SMKS266-DECEMBER 1992
capacitance over recommended ranges of supply voltage and operating free-air temperature,
f = 1 MHz (see Note 3)
PARAMETER
MIN
TYP
MAX
UNIT
Ci(A)
Input capacitance, address inputs
5
pF
Ci(OE)
Input capacitance, output enable
7
pF
Ci(RC)
Input capacitance, strobe inputs
7
pF
Ci(W)
Input capacitance, write-enable input
7
pF
Co
Output capacitance
7
pF
NOTE 3: VCC equal to 3.3 V:l: 0.3 V and the bias on pins under test
IS
0 V.
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TEXAS ~
INSTRUMENTS
4-282
POST OFFICE BOX 1443' HOUSTON. TEXAS 77001
TMS426160, TMS426160P
1048 576·WORD BY 16·BIT HIGH·SPEED
LOW VOLTAGE DYNAMIC RANDOM·ACCESS MEMORIES
SMKS266--0ECEMBER 1992
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature
'426160-70
'426160P-70
PARAMETER
MIN
MAX
'426160-80
'426160P-80
MIN
UNIT
MAX
tCAC
Access time from xCAS low
18
20
ns
tM
Access time from column address
35
40
ns
tRAC
Access time from RAS low
70
80
ns
tOEA
Access time from OE low
18
20
ns
tCPA
Access time from column precharge
40
45
tCLZ
Delay time, xCAS low to output in low l
a
0
ns
tOH
Output data hold time (from xCAS)
3
3
ns
tOHO
Output data hold time (from OE)
3
3
tOFF
Output disable time after xCAS high (see Note 4)
tOEl
Output disable time after OE high (see Note 4)
a
a
ns
a
a
18
18
ns
20
ns
20
ns
NOTE 4: tOFF and tOEl are specified when the output is no longer driven.
timing requirements over recommended ranges of supply voltage and operating free-air
temperature {see Note 5}
'426160-70
'426160P-70
MIN
MAX
'426160-80
'426160P-80
MIN
UNIT
MAX
W
==
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a:
a.
150
ns
130
150
ns
181
205
ns
Page-mode read-modify-write cycle time
96
105
ns
t)
tRASP
Page-mode pulse duration, RAS low (see Note 8)
70
100 000
80
100 000
ns
tRAS
Non-page-mode pulse duration, RAS low (see Note 8)
70
10 000
80
10 000
ns
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C
tCAS
Pulse duration, xCAS low (see Note 9)
18
10 000
20
10 000
ns
tcp
Pulse duration, xCAS high (precharge)
10
10
ns
tRP
Pulse duration, RAS high (precharge)
50
60
ns
twP
Write pulse duration
15
15
ns
tASC
Column-address setup time before xCAS low
Row-address setup time before RAS low
tDS
Data setup time before W low (see Note 10)
tRCS
Read setup time before xCAS low
a
a
a
a
a
a
a
a
ns
tASR
tCWL
W-Iow setup time before xCAS high
18
20
ns
tRC
Read cycle time (see Note 6)
130
twc
Write cycle time
tRWC
Read-write/read-modify-write cycle time
tpRWC
NOTES:
ns
ns
ns
5.
6.
7.
8.
Timing measurements are referenced to VIL max and VIH min.
All cycle times assume tT = 5 ns.
tpc > tcp min + tCAS min + 2tT
In a read-modify-write cycle, tRWD and tRWL must be observed. Depending on the user's transition times, this may require additional
RAS low time (tRAS).
9. In a read-modify-write cycle, tCWD and tCWL must be observed. Depending on the user's transition times, this may require additional
xCAS low time (tCAS).
10. Reference to the first xCAS or 'N, whichever occurs last.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
4-283
l-
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a.
TMS426160, TMS426160P
1048 576-WORD BY 16-BIT HIGH-SPEED
LOW VOLTAGE DYNAMIC RANDOM-ACCESS MEMORIES
SMKS266-DECEMBEA 1992
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (continued) (see Note 5)
'426160-70
'426160P-70
MIN
MAX
'426160-80
'426160P-80
MIN
UNIT
MAX
tRWl
W-Iow setup time before RAS high
18
20
ns
twcs
W-Iow setup time before xCAS low
0
0
ns
tCAH
Column-address hold time after xCAS low
15
15
ns
tDH
Data hold time after xCAS low (see Note 10)
15
15
ns
tRAH
Row-address hold time after RAS low
10
10
ns
tRCH
Read hold time after xCAS high (see Note 13)
0
0
ns
tRRH
Read hold time after RAS high (see Note 13)
5
5
ns
twCH
Write hold time after xCAS low (see Note 12)
15
15
ns
tClCH
Hold time, xCAS low to xCAS high
5
5
ns
tAWD
Delay time, column address to W low (see Note 14)
63
70
ns
tCHR
Delay time, RAS low to xCAS high (see Note 11)
20
20
ns
tCRP
Delay time, xCAS high to RAS low
5
5
ns
tCSH
Delay time, RAS low to xCAS high
70
80
ns
tCSR
Delay time, xCAS low to RAS low (see Note 11)
10
10
ns
tCWD
Delay time, xCAS low to W low (see Note 14)
46
50
ns
tOEH
OE command hold time
18
20
ns
tOED
Delay time, OE high before data at DQ
18
20
ns
tROH
Delay time, OE low to RAS high
10
10
tRAD
Delay time, RAS low to column address (see Note 15)
15
"'C
tRAl
Delay time, column address to RAS high
35
40
m
S
m
=E
tCAl
Delay time, column address to xCAS high
35
40
tRCD
Delay time, RAS low to xCAS low (see Note 15)
20
tRPC
Delay time, RAS high to xCAS low
0
0
ns
tRSH
Delay time, xCAS low to RAS high
18
20
ns
tRWD
Delay time, RAS low to W low (see Note 14)
98
110
ns
tcpw
Delay time, W from xCAS precharge
68
75
ns
tePRH
RAS hold time from xCAS precharge
40
45
ns
tePR
xCAS precharge before self refresh
0
0
ns
tRPS
RAS precharge after self refresh
130
150
ns
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NOTES:
5. Timing measurements are referenced to Vil max and VIH min.
10. Reference to the first xCAS or W, whichever occurs last.
11. xCAS-before-RAS refresh only.
12. Early write operation only.
13. Either tRRH or tRCH must be satisfied for a read cycle.
14. Read-modify-write operation only.
15. Maximum value specified only to assure access time .
. TEXAS ~
INSTRUMENTS
4-284
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
35
52
15
20
ns
40
ns
ns
ns
60
ns
TMS426160, TMS426160P
1048 576·WORD BY 16·BIT HIGH·SPEED
LOW VOLTAGE DYNAMIC RANDOM·ACCESS MEMORIES
SMKS266--DECEMBER 1992
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (concluded) (see Note 5)
'426160-70
'426160P-70
MIN
tRASS
Self refresh entry from RAS low
tCHS
xCAS low hold time after RAS high (self refresh)
tREF.
Refresh time interval (TMS426160)
tREF
Refresh time interval, low power (TMS426160P only)
IT
Transition time
MAX
'426160-80
'426160P-80
MIN
UNIT
MAX
100
100
~s
-50
-50
ns
3
64
64
ms
512
512
ms
30
ns
30
3
NOTE 5: Timing measurements are referenced to VIL max and VIH min.
PARAMETER MEASUREMENT INFORMATION
1.4 V
VCC.= 3.3 V
R1
=1178 Q
R2
= 868
3=
w
>
w
Output Under Test - - . - - - .
Output Under Test
CL = 100 pF
T
T
Q
a::
a.
IU
(b) Alternate Load Circuit
(a) Load Circuit
::>
Figure 1. Load Circuits for Timing Parameters
C
o
a::
a.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
4-285
TMS426160, .TMS426160P
1048 576·WORD BY 16·BITHIGH·SPEED
LOW VOLTAGE DYNAMIC RANDOM·ACCESS MEMORIES
SMKS266-DECEMBER 1992
PARAMETER MEASUREMENT INFORMATION
14
tRC
RAS~'
IT
tASR ~
"tI
:D
o
AO-A"
C
C
N\
i:
LCAS
~
II
I
I
I I
I I
I I
: I
I I
I I
I I
tCS,H I
I i4
I I
I I
I I+- tRAD ---+i
I I
I~
III
1- .; tRAH I
I I
I I
ItASC~ I
I
I
14
+n
i+-l ~ /\J\7\.':
o
-I
tRCS
Vi
"tI
m
-;1
ii
:
I~
II
I
I I
I
I
J1
tCLCH
~
tcp
I (see Note A)
I
j"
I
- I
I I
I ·1
I I
I I
~tRSHI I
.1 I
I I
I I
II
II
I I
I I
1 I
I I
tCAL
•
tRAL _ _r-I-i-I_~_+il
I
I
\.
Ir-t t~RP
I I
I 101
~
I I
I
I
I I+--t tRCH ~
I
I
~ tCAC -.I
I (see Note
I
I
I ~ tOFF ~
I
I
I
14-- tOH
B)i
--1
I
(see Note D)
Valid Data Out
:E
NOTES: A.
B.
C.
D.
In order to hold the address latched by the first xCAS going low, the parameter tCLCH must be met.
tCAC is measured from xCAS to its corresponding DQx.
xCAS order is arbitrary.
Output may go from high-impedance to an invalid data state prior to the specified access time.
Figure 2. Read Cycle Timing
TEXAS
~
INSTRUMENTS
4-286
i"I
~
~
ci+ J@W;~~d~~:~,---_
tCLZ ~
DQO-DQ15
-I
J
I4--j- tAA ~
:D
m
:$
tCAS
1
14
I
11
~
I ~ tRP ~ ' - - - ,-_ _ _ _ _IYI_ _ _-;._ _""I
I ~ tCAH
~ I
I
i
1
1
0
tRAS
-to!I 14e--- tRCD ---.II
UCAS
~
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
tRRH
TMS426160, TMS426160P
1048 576·WORD BY 16·BIT HIGH·SPEED
LOW VOLTAGE DYNAMIC RANDOM·ACCESS MEMORIES
SMKS266-DECEMBER 1992
PARAMETER MEASUREMENT INFORMATION
LCAS
-.I
I
I
I
I
I
I
AO-A11
~
3:
UJ
-Gj
a:
Q.
IU
::J
C
o
a:
DQO-DQ15
Don't Care "A," A IV'
I
I
~tOED~
I
I
14
Q.
"","".'V'''''A/\.A Don't Care ",,'V""'vvv
Valid Data·ln
tDS (see Note C)
tOEH--~~
NOTES: A. In order to hold the address latched by the first xCAS going low, the parameter tCLCH must be met.
B. xCAS order is arbitrary.
C. Reference to the first xCAS or W, whichever occurs last.
Figure 3. Write Cycle Timing
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
4-287
TMS426160, TMS426160P
1 048 576·WORD BY 16·BIT HIGH·SPEED
LOW VOLTAGE DYNAMIC RANDOM·ACCESS MEMORIES
SMKS266-DECEMBER 1992
PARAMETER MEASUREMENT INFORMATION
~
!wc
---~rt;
tTi
Y:
tRAS
~tRCO~
I 14
~I tCRP ~
.1
N~tCAS~y
I
I
~
"'C
J]
o
c
c
AO-A11
1"'11
I
I
I
~ft7'V\.~
~
Row
~
--------'
n
twcs
-I
w
"'C
J]
14
~
1
I
Column
tRAL
i
.~
~h{tf:fz~
I 1
I
I
I
I ~tCAH
I
I
~ I
I
I
: ~twcH1~.m,.~~~~~~~~~~
~II~
OQO-OQ15
NOTES: A. In order to hold the address latched by the first xCAS going low, the parameter tCLCH must be met.
B, xCAS order is arbitrary,
Figure 4. Early Write Cycle Timing
TEXAS ~
INSTRUMENTS
4-288
j
'\~ ~
m
S
m
::E
~
I
I !
I4-j--tRSH
:
I I
I tCLCH ~
I
I
I 1
(see N,ote A)
I
I I
I II\. i
/(r--t-l-----+jI ~tRAO~ I I
\.
I~
I
tcP---~~
14
~ I
I I I
I
I
~tRAHI
II
I
I
I
~J I
I
I
I tASC~ I
I
I I
~ I I tCAL
~
I
i
tASR
i',---
114-tRPi
tCSH
i!
~
POST OFFICE BOX 1443' HOUSTON, TEXAS 77001
TMS426160, TMS426160P
1048 576·WORD BY 16·BIT HIGH·SPEED
LOW VOLTAGE DYNAMIC RANDOM·ACCESS MEMORIES
SMKS266-DECEMBER 1992
PARAMETER MEASUREMENT INFORMATION
~
~
IT
--lI
~
tRWC
I
I
I
I
j4--- tRCD ~
"N--
I :
tCAS ~V
I j_.'
I I
I 14
tCSH
~
I I
I
~
I I
I
I
I I
I
~
I,
I I+- tRAD ---+I
I I
'.
I I I
I I
I ~ tRAH ~.J I
~
I
AO-A11
I
I
I
N
iL
I
II
I
~tcp~
tRSH
-----:ll;:::::::~~~----
I
I
II
I
I
I
I
:
I
~tASC
I
I"': tASR
~ tRP --:
14'---1 tCRP ~
tCLCH
(see Note A)
\l
-.:
~
yT
tRAS
14-
2M "7 )@( +::}I
hi
w
a:
twp
rJ
a.
IU
::J
C
o
DQ8-DQ15
a:
I
14
I
I
~
tOHO:
I
I
I 14--*
I I
I4-*-
tDS
tOEZ
I
il'
}I.14
a.
~tDH
I
~
I tOED
+
I I
(see Note D)
DQO-DQ7 - - - - - - - - - - - - {
NOTES: A.
S,
C,
D.
In order to hold the address latched by the first xCAS going low, the parameter tCLCH must be met.
xCAS order is arbitrary.
tCAC in measured from xCAS to its corresponding DQx.
Output might go from a high·impedance state to an invalid data state prior to the specified access time,
Figure 5. Read-Modify-Write Cycle Timing
TEXAS ~
INsrRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 7'7001
4·289
TMS426160, TMS426160P
1048 576·WORD BY 16·BIT HIGH·SPEED
LOW VOLTAGE DYNAMIC RANDOM·ACCESS MEMORIES
SMKS266-DECEMBER 1992
PARAMETER MEASUREMENT INFORMATION
tRP
r'
~
~~-----------------tRASP----------------~~
I I+- tRCD ~
II
I
:i
I~I
~I
I..
~
tCSH
I
~~SR
i
o
~
I
I
"tJ
::D
i
I
tRAH
I
I
I
~
tCAS14
I
J
I
i
,I
I
,tpc
I
I
i/
: - - - tCAl
I
(')
Vi
-t
I
I I I
I
~tAA
I
I I
[
I I
tRCS --fr"----I---.,.I I
"tJ
::D
m
S
m
14---'tRAC
~
tCLZ
(see Note D)
DQ8-DQ15
I
I
I
~ tRRH
I4--tRCH~
--~~
I
I :
I I
I'll ~
[ I
I I
tCPA _ -....1
I I
I
[(see Note F)
--i4~----~~
[:
J
J~r
:
[
~~~~~t&
.... -
tOH
:
I: I
I
~ tOFF
I
~
-----------~
~
tRAl
ft7\,rb'W~i'V'V""'~i'V'V""':7'V\:~
I
II
1.[
II
['III
I
i
:
Column
:I iI irtCAC~'(f:
i~~
NE'»i
~l
r
II
~
1'1
I [ [
I
I~------~i~---------
I
J
i
i
I
[
I
i
\..
:
[
[
I
'I
"---1'[
tASC
I I I ~ tCAH
[ I
1""'1
--,..t-_.~I
C
~
~
~
I
I
[
I
~I
I ~ ttp
AO-A11
C
I
[
.:
/14-14--------- tCPRH
[14
tRSH
tClCH;_
(see Not~ A) [I
[I
: :
I
I'
'\
I [
[I
I [
:
I
~tCR~~
I------!-I---r---------I -.I !.- tOEZ
I
1
I
I'
t4-- tAA ~
: I
(see Note D)
~~val~id\
DQO-DQ7 ------------~~ Out.
';>----------
I
I
I
I4-f- tOHO
~~:~r*l~mx~tOEA ~ ~
~
OE
tO~A 1'1
I
~
~t
r i "1 OHO
[
00:W:~*1~E~
NOTES: A.
B.
C.
D.
E.
In order to hold the address latched by the first xCAS going low, the parameter tClCH must be met.
tCAC is measured from xCAS to its corresponding DQx.
xCAS order is arbitrary.
Output may go from high-impedance to an invalid data stale prior to the specified access time.
A write cycle or read-modify-write cycle can be mixed with the read cycles as long as the write and read-modify-write timing
specifications are not violated.
F. Access time is tCPA or tAA dependent.
Figure 6. Enhanced Page-Mode Read Cycle Timing
TEXAS
~
INSfRUMENTS
4-290
POST OFFICE BOX 1443· HOUSTON. TEXAS 77001
TMS426160, TMS426160P
1 048 576·WORD BY 16·BIT HIGH·SPEED
LOW VOLTAGE DYNAMIC RANDOM·ACCESS MEMORIES
SMKS266-DECEMBER 1992
PARAMETER MEASUREMENT INFORMATION
tRP~
NI'-~f-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-=-_tR_A_SP_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-~~
, ,
J4
(
\
::
,,
~
, ~
..::
:
:
I
,
,
tASR
I
tASC
L
~
.. I
~ ~:
I
1
I
,
tCAH
,
.. I
I.
,
~,
tCPRH
I0Il
:
~ tPc
t
I
CP
"L, :'tCRP ~
~-I
I
~
N--tCAS-Y
-.II+. tRAH I
.:rl _ _....'
AI}-A11
(see Note A)
, tCSH
------+j
:
::
I
,
J4-- tClCH ~
: '
,14-, tRCD -+I,
tRSH
:
J+--
I
J..
tCAl
i
1
I
I
..I
--~~
tRAl
:
/<:7<:7'V'V~~~~7'V'Vm7'~~
1
I
(
Column
IV'VVVVVVV'v
Don't Care
vv'vv'vV'V'
3:
w
:>
w
CC
a.
IU
::J
C
o
CC
a.
NOTES: A. In order to hold the address latched by the first xCAS going low, the parameter tClCH must be met.
B. xCAS order is arbitrary.
C. A read cycle or read-modify-write cycle can be mixed with the write cycles as long as the read and read-modify-write timing
specifications are not violated.
D. Referenced to the first xCAS or W, whichever occurs last.
Figure 7. Enhanced Page-Mode Write Cycle Timing
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
4-291
TMS426160, TMS426160P
1048 576·WORD BY 16·BIT HIGH·SPEED
LOW VOLTAGE DYNAMIC RANDOM·ACCESS MEMORIES
SMKS266-DECEMBER 1992
PARAMETER MEASUREMENT INFORMATION
"'C
:D
o
C
c:
o
-t
"'C
:D
m
S
m
=E
Valid Out
i+- tOEA ----+J
OE
1
-+I
1
I
~
tOEZ
.1
1
I:
tOEH
1
r---.f.I-
1<
.
4.
1
1
1
tOED
1
1
lio----.i.\"-_-JIr-----~'=~~<:7':?
NOTES: A.
B.
C.
D.
E.
In order to hold the address latched by the first xCAS going low, the parameter tCLCH must be met.
tCAC is measured from xCAS to its corresponding DQx.
xCAS order is arbitrary.
Output may go from high-impedance to an invalid data state prior to the specified access time.
A read or write cycle can be intermixed with read-modify-write cycles as long as the read and write cycle timing specifications are
not violated.
F. Access time is tCPA or tM dependent.
Figure 8. Enhanced Page-Mode Read-Modify-Write Cycle Timing
1ExAs
~
INSTRUMENTS
4-292
POST OFFICE BOX 1443· HOUSTON. TEXAS 77001
TMS426160, TMS426160P
1 048 576·WORD BY 16·BIT HIGH·SPEED
LOW VOLTAGE DYNAMIC RANDOM·ACCESS MEMORIES
SMKS26EHJECEMBER 1992
PARAMETER MEASUREMENT INFORMATION
w
==
:>
w
O Q O - O Q 1 5 - - - - - - - - - - - - HI-Z - - - - - - - - - - - - -
a:
D..
....
NOTE A: All xCAS must be high.
(J
Figure 9. RAS-Only Refresh Timing
::J
C
oa:
D..
TEXAS ~
INsrRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
4-293
TMS426160, TMS426160P
1048 576·WORDBY 16·BIT HIGH·SPEED
LOW VOLTAGE DYNAMIC RANDOM·ACCESS MEMORIES
SMKS266-DECEMBER 1992
PARAMETER MEASUREMENT INFORMATION
"o:D
C
DQO-DQ15
C
o
-I
":Dm
Figure 10. Hidden Refresh Cycle Timing
S
m
:e
TEXAS ~
INSrRUMENTS
4-294
POST OFFICE BOX 1443· HOUSTON, TEXAS 77001
TMS426160, TMS426160P
1048 576·WORD BY 16·BIT HIGH·SPEED
LOW VOLTAGE DYNAMIC RANDOM·ACCESS MEMORIES
SMKS266-DECEMBER 1992
PARAMETER MEASUREMENT INFORMATION
1~4-------------------tRC----------------~·1
14-- tRP ~ ~14----------- tRAS -----------~
..I I
I
RM
ANY
-+i ~
i ~:4--I
tRPC
xCAS
I ---Iit:-
II
I I
\J..
tcSR
tCHR --------+1.1
Y
~ ~ tr
w~:e~~'::€~~~:~
AO-AII~~~E*E~
oE~:ef~X~aE~
OQO-OQI5--------------
HI·Z - - - - - - - - - - - - - - -
NOTES: A. Any xCAS may be used.
;:
UJ
:>
UJ
0:
Q.
Figure 11. Automatic (CAS-Before-RAS) Refresh Cycle Timing
t-
O
:::l
C
o
0:
Q.
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
4·295
TMS426160P
1048 576-WORD BY 16·BIT HIGH·SPEED
LOW VOLTAGE DYNAMIC RANDOM·ACCESS MEMORIES
SMKS266-DECEMBER 1992
PARAMETER MEASUREMENT INFORMATION
1OOIII1.f----I
N
fiI
I
I
_ _-.J
tRPC
-l4----+I
tCSR
-
xCAS
:l]
o
-I
."
-
~
I
~ tRPS ~
~ j+I I
I
~
~ tCHS
I ~~~.
~
!I '\......- - - - - - - - - - - -.................
.~
'""""'""-"=-><~
--.-/!I
tCPR-+!
~;;!~::~
i+-
~
tOFF
DQ~Q15 ~_--------- HI-Z - - - - - - - - - - - -
:l]
m
<
m
~I
----------~
W~~~!E~
OE~*;!E~
."
o
c
c:
----+1.1
I
Tr---~"\!
j+-
AO-Al1
tRASS
Figure 12. Self Refresh Timing
device symbolization
t-~
TI
==
P TMS426160~
'If-
_A
J>
T
Speed ( -70, -80)
Low Power/Refresh Option
Package Code
~
Lot Traceability Code
Date Code
Assembly Site Code
Ole Revision Code
Wafer Fab Code
. TEXAS ~
INSTRUMENTS
4-296
POST OFFICE BOX 1443· HOUSTON, TEXAS 77001
TMS418160, TMS418160P
1048 576·WORD BY 16·BIT HIGH·SPEED
DYNAMIC RANDOM·ACCESS MEMORIES
SMKS860-DECEMBER 1992
•
Organization ... 1 048 S76 x 16
•
•
Single S-V Supply (10% Tolerance)
REPACKAGEt
(TOP VIEW)
Performance Ranges:
'418160/P-60
'418160/P-70
'418160/P-80
ACCESS ACCESS ACCESS READ OR
TIME
TIME
TIME
WRITE
tRAC
tCAC
tAA
CYCLE
MAX
MAX
MAX
MIN
60ns
15ns
30ns
lIOns
70ns
18ns
35 ns
130 ns
80 ns
20 ns
40 ns
150 ns
•
Enhanced Page Mode Operation With
CAS-Before-RAS Refresh
•
Long Refresh Period ...
1024-Cycle Refresh In 16 ms (Max)
128 ms Max for Low-Power, Self-Refresh
Version (TMS418160P)
•
3-State Unlatched Output
•
Low Power Dissipation
•
•
•
•
•
VSS
0015
0014
0013
0012
VCC
000
001
002
003
VSS
0011
VCC
004
VSS
0011
005
DOlO
009
DOS
NC
RAS
NC
NC
AO
AI
A2
A3
0010
009
DOS
NC
LCAS
UCAS
OE
A9
AS
A?
A6
A5
A4
VCC
VSS
VCC
000
001
002
003
I
005
006
DO?
NC
NC
Vii
Self-Refresh With Low Power
All Inputs, Outputs, and Clocks are TTL
Compatible
DCPACKAGEt
(TOP VIEW)
High-Reliability Plastic 42-Lead
400-Mil-Wlde Surface Mount (SOJ)
Package, and 44/S0-Lead Thin Small
.Outline Package (TSOP)
Operating Free-Air Temperature Range
O°C to 70°C
2
DO?
NC
NC
NC
VSS
0015
0014
0013
0012
RAS
NC
NC
AO
AI
A2
A3
NC
LCAS
UCAS
OE
A9
AS
A?
A6
A5
A4
VCC
VSS
Vii
description
The TMS418160 series are high-speed,
16 777 216-bit
dynamic
random-access
memories organized as 1 048 576 words of
sixteen bits each.
The TMS418160P series are high-speed, lowpower, self-refresh, 16 777 216-bit dynamic
as
random-access
memories
organized
1 048576 words of sixteen bits each.
W
VCC
VSS
All inputs and outputs, including clocks, are compatible with Series 74 TTL. All addresses and data-in lines are
latched on-chip to simplify system design. Data out is unlatched to allow greater system flexibility.
EPIC is a trademark of Texas Instruments Incorporated.
~
Copyright © 1992. Texas Instruments Incorporated
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
()
~
Q.
These devices feature maximum RAS access times of 60 ns, 70 ns, and 80 ns. Maximum power dissipation is
as low as 11 mW standby on 80 ns devices.
TEXAS
Q.
I-
a:
Address Inputs
Data In/Data Out
Lower Column-Address Strobe
Upper Column-Address Strobe
No Internal Connection
Output Enable
Row-Address Strobe
Write Enable
5-V Supply
Ground
They employ state-of-the-art EPIC'· (Enhanced Performance Implanted CMOS) technology for high
performance, reliability, and low power at low cost.
PRODUCT PREVIEW Informltlo......... prod.CIII. Ih,
Iann_ or d..lg. pili. of dIYllop...'" ChlllCl'rIItIc
data Ind other, aplClflcItIont Ire d....n goa... Telll
Inltrumenlil'lltrYM till right to ching. eM' dilcontlnu.
III... prod_ wllllout .otlet.
a:
0
PIN NOMENCLATURE
AO-A9
DOO-DOl5
LCAS
UCAS
NC
OE
RAS
:>
W
C
t Packages are shown for pinout reference only
Texas Instruments EPIC ™ CMOS Process
3:
W
4-297
TMS418160, TMS418160P
1048 576·WORD BY 16·BIT HIGH·SPEED
DYNAMIC RANDOM·ACCESS MEMORIES
SMKS86G-DECEMBER 1992
The TMS418160 and TMS418160P are each offered in a 42-lead plastic surface mount SOJ (RE suffix)
package, and a 44/50-lead plastic surface mount TSOP (DC suffix). These packages are characterized for
operation from O°C to 70°C.
operation
dual CAS
Two CAS pins (LCAS-UCAS) are provided to give independent control of the sixteen data I/O pins
(DO(}-D015), with LCAS corresponding to DO(}-D07 and UCAS corresponding to D08-D015. For read or
write cycles, the column address is latched on the first xCAS falling edge. Each xCAS pin going low enables
its corresponding DO pin with data coming from the column address to be latched on the first falling xCAS edge.
All address setup and hold parameters are referenced to the first falling xCAS edge. The delay time from xCAS
low to valid data out (see parameter tCAd is measured from each individual CAS to its corresponding DOx pin.
In order to latch in a new column address, all xCAS pins must be brought high. The column prechargetime (see
parameter tcp) is measured from the last xCAS rising edge to the first falling xCAS edge of the new cycle.
Keeping a column address valid while toggling xCAS requires a minimum setup time, tCLCH' During tCLCH, at
least one xCAS must be brought low before the other xCAS is taken high.
For early write cycles, the data is latched on the first falling xCAS edge. Only the DOs that have the
corresponding xCAS low will be written into. Each xCAS will have to meet tCAS minimum in order to ensure
writing into the storage cell. In order to latch a new address and new data, all xCAS pins need to come
high and meet tcp-
"tJ
:xJ
o
C
C
enhanced page mode
o-I
Page-mode operation allows faster memory access by keeping the same row address while selecting random
column addresses. The time for row-address setup and hold and address multiplex is thus eliminated. The
maximum number of columns that may be accessed is determined by the maximum RAS low time and the xCAS
page-mode cycle time used. With minimum xCAS page cycle time, all 1024 columns specified by column
addresses AO through A9 can be accessed without intervening RAS cycles.
"tJ
:xJ
m
~
m
Unlike conventional page-mode DRAMs, the column-address buffers in this device are activated on the falling
edge of RAS. The buffers act as transparent or flow-through latches while xCAS is high. The falling edge of the
first xCAS latches the column addresses. This feature allows the devices to operate at a higher data bandwidth
than conventional page-mode parts, because data retrieval begins as soon as column address is valid rather
than when xCAS transitions low. This performance improvement is referred to as enhanced page mode. Valid
column address may be presented immediately after tRAH (row address hold time) has been satisfied, usually
well in advance ofthe falling edge of xC AS. In this case, data is obtained aftertCAC max (access time from xCAS
low) if tAA max (access time from column address) has been satisfied. In the event that column addresses for
the next page cycle are valid at the time xCAS goes high, minimum access time for the next cycle is determined
by tCPA (access time from rising edge of the last xCAS).
:E
address (AD-A9)
Twenty address bits are required to decode 1 of 1 048 576 storage cell locations. Ten row-address bits are set
up on pins AO through A9 and latched onto the chip by RAS. Then, ten column-address bits are set up on pins
AO through A9 and latched onto the chip by the first xCAS. All addresses must be stable on or before the falling
edge of RAS and xCAS. RAS is similar to a chip enable in that it activates the sense amplifiers as well as the
row decoder. xCAS is used as a chip select, activating its corresponding output buffer and latching the address
bits into the column-address buffers.
TEXAS
~
INSTRUMENTS
4-298
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
TMS418160, TMS418160P
1 048 576·WORD BY 16·BIT HIGH·SPEED
DYNAMIC RANDOM·ACCESS MEMORIES
SMKS860-0ECEMBER 1992
write enable
(W)
The read or write mode is selected through the W input. A logic high on the W input selects the read mode and
a logic low selects the write mode. The write-enable terminal can be driven from the standard TTL circuits without
a pullup resistor. The data inputs are disabled when the read mode is selected. When W goes low prior to xCAS
(early write), data out will remain in the high-impedance state for the entire cycle permitting a write operation
with OE grounded.
data In (DQO-DQ15)
Data is written during a write or read-modify-write cycle. Depending on the mode of operation, the falling edge
otxCAS or W strobes data into the on-chip data latch. In an early-write cycle, W is brought low prior to xCAS
and the data is strobed in by the first occurring xCAS with setup and hold times referenced to this signal. In a
delayed-write or read-mOdify-write cycle, xCAS will already be low, thus the data will be strobed in by W with
setup and hold times referenced to this signal. In a delayed-write or read-modify-write cycle, OE must be high
to bring the output buffers to high impedance prior to impressil'lg data on the I/O lines.
data out (DQO-DQ15)
The three-state output buffer provides direct TTL compatibility (no pullup resistor required) with a fanout of two
Series 74 TTL loads. Data out is the same polarity as data in. The output is in the high-impedance (floating) state
until xCAS and OE are brought low. In a read cycle, the output becomes valid after the access time interval tCAC
(which begins with the negative transition of xCAS) as long as tRAC and tAA are satisfied.
output enable (OE)
OE controls the impedance of the output buffers. When OE is high, the buffers will remain in the high-impedance
state. Bringing OE low during a normal cycle will activate the output buffers, putting them in the low-impedance
state. It is necessary for both RAS and xCAS to be brought low for the output buffers to go into low-impedance
state, they will remain in the low-impedance state until either OE or xCAS is brought high.
3:
->w
w
ex:
a..
....
U
RAS-only refresh
A refresh operation must be performed at least once every sixteen milliseconds (128 ms for TMS418160P) to
retain data. This can be achieved by strobing each of the 1024 rows (AQ-A9). A normal read or write cycle will
refresh all bits in each row that is selected. A RAS-only operation can be used by holding all xCAS at the high
(inactive) level, thus conserving power as the output buffers remain in the high-impedance state. Externally
generated addresses must be used for a RAS-only refresh.
hidden refresh
Hidden refresh may be performed while maintaining valid data at the output pin. This is accomplished by holding
xCAS at Vil after a read operation and cycling RAS after a specified precharge period, similar to a RAS-only
refresh cycle.
xCAS-before-RAS refresh
xCAS-before-RAS refresh is utilized by bringing at least one xCAS low earlier than RAS (see parameter tCSR)
and holding it low after RAS falls (see parameter tCHR)' For successive xCAS-.before-RAS refresh cycles,
xCAS can remain low while cycling RAS. The external address is ignored and the refresh address is generated
internally. The external address is also ignored during the hidden refresh option.
A low-power battery-backup refresh mode that requires less than 500 ~A refresh current is available on the
TMS418160P. Data integrity is maintained using xCAS-before-RAS refresh with a period of 125 ~s while holding
RAS low for less than 1 ~s. To minimize current consumption, all input levels need to be at CMOS levels
(Vil < 0.2 V, VIH > VCC - 0.2 V).
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
4-299
::l
C
o
ex:
a..
TMS418160, TMS418160P
1 048 576·WORD BY 16·BIT HIGH·SPEED
DYNAMIC RANDOM·ACCESS MEMORIES
SMKS86(}-OECEMBER 1992
self refresh (TMS418160P)
The self-refresh mode is entered by dropping xCAS low prior to RAS going low. Then xCAS and RAS are both
held low for a minimum of 100 1lS. The chip is then refreshed internally by an on-board oscillator. No external
address is required since the CBR counter is used to keep track of the address. To exit the self-refresh mode
both RAS and xCAS are brought high to satisfy tCHS' Upon exiting self-refresh mode, a burst refresh (refresh
a full set of row addresses) must be executed before continuing with normal operation. The burst refresh
ensures the DRAM is fully refreshed.
power up
To achieve proper device operation, an initial pause of 200 itS followed by a minimum of eight RAS cycles is
required after power-up to the full VCC level.
"'tI
:c
o
c
o
c
-I
"'tI
:c
m
S
m
==
TEXAS ~
INsrRUMENTS
4-300
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
TMS418160, TMS418160P
1048 576·WORD BY 16·BIT HIGH·SPEED
DYNAMIC RANDOM·ACCESS MEMORIES
SMKS860-DECEMBER 1992
logic symbol t
RAM1Mx16
AO 17
A1
A2
A3
A4
A5
A6
A7
A8
A9
20010/2100
18
19
20
23
24
25
26
27
28
>
0
A 1 048575
20019/2109
> C20(ROW]
14
31
~
>
~
G23/(REFRESH ROW]
24(PWR OWN)
C21
G24
&
23C22
31
3:
w
> C21
30
F
r,
&
31
Z31
W 13
OE 29
000
001
002
003
004
005
006
007
008
009
0010
0011
0012
0013
0014
0015
2
3
4
5
7
8
9
10
33
:>
w
G34
23,210
23C32
a:
+
0..
~,25EN27
I-
o
34,25EN37
"- 25
...
4-
::J
r
A,220
V26,27
C
o
A,Z26
a:
0..
..
.
L
34
35
36
38
39
40
41
A,320
V36,37
A,Z36
.
t This symbol is in accordance with ANSI/IEEE Std 91-1984 and lEe Publication 617-12.
The pin numbers shown correspond to the RE package.
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
4-301
TMS418160, TMS418160P
1048 576·WORD BY 16·BIT HIGH·SPEED
DYNAMIC RANDOM·ACCESS MEMORIES
SMKS86Q-OECEMBER 1992
functional block diagram
! t_ J l
I
t
AO
1
/
9
/
A1
•
·•
A9
•
•
1
Sense Amplifiers
256KArray
256KArray
32<
Row
Address
Buffers
3~
W
Column Decode
Column
Address
Buffers
L
•
j
Timing and Control
•
••
256KArray
R
0
••
•
0
e
10
c
/
d
e
~
256KArray
w
>32
I/O
Buffers
16 of 32
Selection
0
~
~
In
Reg.
Data
Out
Reg.
OQO-OQ15
'--
256KArray
-
"tJ
10
:D
/
o
C
c:
o
absolute maximum ratings over operating free-air temperature range {unless otherwise noted)t
Supply voltage range on any pin (see Note 1) .......................................... - 1 V to 7 V
Supply voltage range on Vee ......................................................... - 1 V to 7 V
Short circuit output current ................................................................ 50 mA
Power dissipation ........................................................................... 1 W
Operating free-air temperature range .................................................. O°C to 70°C
Storage temperature range ....................................................... - 55°C to 125°C
-I
"tJ
:D
m
S
m
~
256KArray
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. This is a stress rating only, and
functional operation of the device at these or any other conditions beyond those indicated in the "recommended operating conditions" section
of this specification is not implied. Exposure to absolute·maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values in this data sheet are with respect to VSS.
recommended operating conditions
vee
Supply voltage
VSS
Supply voltage
MIN
NOM
MAX
4.5
5
5.5
0
UNIT
V
V
VIH
High·level input voltage
2.4
6.5
VIL
LOW-level input voltage (see Note 2)
-1
0.8
V
TA
Operating free·air temperature
0
70
·e
..
..
..
V
NOTE 2: The algebraiC convention, where the more negative (less positive) limit IS designated as minimUm, IS used In thiS data sheet for
logic voltage levels only.
TEXAS . "
INSTRUMENTS
4·302
POST OFFICE BOX 1443' HOUSTON, TEXAS 77001
TMS418160, TMS418160P
1048 576-WORD BY 16-BIT HIGH-SPEED
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS86(H)ECEMBER 1992
electrical characteristics over full ranges of recommended operating conditions (unless otherwise
noted)
PARAMETER
'418160-60
'418160P-60
TEST CONDITIONS
MIN
VOH
High-level output
voltage
10H =-5 rnA
VOL
Low-level output
voltage
10L= 4.2 rnA
II
Input current
(leakage)
10
ICC1H
'418160-70
'418160P-70
MAX
2.4
MIN
'418160-80
'418160P-80
MAX
2.4
MIN
UNIT
MAX
2.4
V
0.4
0.4
0.4
V
VCC = 5.5 V, VI = 0 to 6.5 V,
All other pins = 0 V to VCC
.. 10
±10
.. 10
I-lA
Output current
(leakage)
VCC = 5.5 V, Vo = 0 to VCC, xCAS high
.. 10
±10
.. 10
I-lA
Read or write cycle
current
VCC = 5.5 V, Minimum cycle
TBD
TBD
TBD
rnA
2
2
2
rnA
1
1
1
rnA
500
500
500
I-lA
TBD
TBD
TBD
rnA
TBD
TBD
TBD
rnA
500
500
500
I-lA
5
5
5
rnA
500
500
500
I-lA
VIH = 2.4 V (TTL),
After 1 memory cycle,
RAS and xCAS high
ICC2
Standby current
VIH = VCC - 0.2 V (CMOS) ,
After 1 memory cycle,
RAS and xCAS high
'418160
'418160P
Average refresh
current (RAS-only
VCC = 5.5 V, Minimum cycle,
RAS cycling, xCAS high (RAS only)
orCBR)
RAS low after xCAS low (CBR)
ICC4 t §
Average page current
VCC = 5.5 V, tpc = minimum,
RAS low, xCAS cycling
ICC61!
Self refresh
ICC3:t
ICC7 t
Standby current,
outputs enabled
Battery back-up
operating current
ICC101!
(equivalent refresh
time is 128 ms).
CBR only.
xCAS < 0.2 V, RAS < 0.2 V,
Measured after tRASS minimum
RAS = VIH, xCAS = VIL,
Data out = enabled
tRC = 125 !'S, tRAS '" 1 "s,
VCC-0.2V", VIH" 6.5 V,
OV ",VIL'" 0.2 V, Wand OE =VIH,
Address and Data stable
t
Measured with outputs open.
:t Measured wHh a maximum of one address change while RAS = VIL.
§ Measured wHh a maximum of one address change while xCAS = VIH.
I! ForTMS418160P only.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
4-303
w
==
:>
w
a:
a.
IU
:::)
C
o
a:
a.
TMS418160, TMS418160P
1 048 576·WORD BY 16·BIT HIGH·SPEED
DYNAMIC RANDOM·ACCESS MEMORIES
SMKS860-DECEMBER 1992
capacitance over recommended ranges of supply voltage and operating free-air temperature,
.
f 1 MHz (see Note 3)
=
PARAMETER
MIN
TYP
MAX
UNIT
Ci(A)
Input capacitance, address inputs
5
pF
Ci(OE\
Input capacitance, output enable
7
pF
Ci(RC)
Input capacitance, strobe inputs
7
pF
Ci(W)
Input capacitance, write-enable input
7
pF
C~
Output capacitance
7
pF
NOTE 3: VCC equal to 5 V ± 0.5 V and the bias on pins under test is 0 V.
"tJ
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c:
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-I
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m
m
=E
<
-
TEXAS~
INSfRUMENTS
4-304
POST OFFICE BOX 1443· HOUSTON, TEXAS 77001
TMS418160, TMS418160P
1048 576·WORD BY 16·BIT HIGH·SPEED
DYNAMIC RANDOM·ACCESS MEMORIES
SMKS8SQ-DECEMBER 1992
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature
'418160-60
'418160P-60
PARAMETER
'418160-70
'418160P-70
MAX
MIN
MIN
MAX
'418160-80
'418160P-80
MIN
UNIT
MAX
tCAC
Access time from xCAS low
15
18
20
tAA
Access time from column address
30
35
40
ns
tRAC
Access time from RAS low
60
70
80
ns
tOEA
Access time from OE low
15
18
20
ns
tCPA
Access time from column precharge
35
40
45
tCLZ
Delay time, xCAS low to output in low Z
0
0
toH
Output data hold time (from xCAS)
3
tOHO
Output data hold time (from OE)
3
toFF
Output disable time after xCAS high (see Note 4)
0
15
0
18
0
20
ns
tOEZ
Output disable time after OE high (see Note 4)
0
15
0
18
0
20
ns
ns
ns
0
ns
3
3
ns
3
3
ns
NOTE 4: tOFF and tOEZ are specified when the output is no longer driven.
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (see Note 5)
'418160-60
'418160P-60
MIN
MAX
'418160-70
'418160P-70
MIN
lJO
130
Write cycle time
110
Read-write!read-modify-write cycle time
155
40
tRC
Read cycle time (see Note 6)
!wc
tRWC
tpc
Page-mode read or write cycle time (see Note 7)
MAX
'418160-80
'418160P-80
MIN
UNIT
MAX
150
ns
130
150
ns
181
205
ns
45
50
ns
tPRWC
Page-mode read-modify-write cycle time
85
tRASP
Page-mode pulse duration, RAS low (see Note 8)
60
100000
70
100000
80
100000
ns
tRAS
Non-page-mode pulse duration, RAS low (see Note 8)
60
10 000
70
10 000
80
10 000
ns
tCAS
Pulse duration, xCAS low (see Note 9)
15
10 000
18
10000
20
10 000
ns
tcp
Pulse duration, xCAS high (precharge)
10
10
10
ns
tRP
pulse duration, RAS high (precharge)
40
50
60
ns
!wP
Write pulse duration
15
15
15
ns
tASC
Column-address setup time before xCAS low
0
0
0
ns
tASR
Row-address setup time before RAS low
0
0
0
ns
tDS
Data setup time before W low (see Note 10)
0
0
0
ns
tRCS
Read setup time before xCAS low
0
0
0
ns
15
18
20
ns
tCWL
NOTES:
W-Iow setup time before xCAS high
96
105
ns
5.
6.
7.
8.
Timing measurements are referenced to VIL max and VIH min.
All cycle times assume IT = 5 ns.
tpc > tcp min + tCAS min + 2tT·
In aread-modify-write cycle, tRWD and tRWL must be observed. Depending on the user's transition times, this may require additional
RAS low time (tRAS).
9. In a read-modify-write cycle, tCWD and tCWL must be observed. Depending onthe user's transition times, this may require additional
xCAS low time (tCAS).
10. Reference to the first xCAS or W, whichever occurs last.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
4-305
;:
W
:;
w
a:
a.
IU
::J
C
o
a:
a.
TMS418160, TMS418160P
1 048 576-WORD BY 16-BIT HIGH-SPEED
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS66()-OECEMBER 1992
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (continued) (see Note 5)
'418160~0
'418160P-60
MIN
"tJ
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C
C
o
-I
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:xJ
m
<
m
:e
MAX
'418160-70
'418160P-70
MIN
MAX
'418160-80
'418160P-80
MIN
UNIT
MAX
tRWL
W-Iow setup time before RAS high
twcs
W-Iow setup time before xCAS low (see Note 12)
15
18
20
0
0
0
tCAH
Column-address hold time after icCAS low
ns
10
15
15
ns
tDH
Data hold time after xCAS low (see Note 10)
10
15
15
ns
tRAH
Row-address hold time after RAS low
10
10
10
ns
ns
tRCH
Read hold time after xCAS high (see Note 13)
0
0
0
ns
tRRH
Read hold time after RAS high (see Note 13)
5
5
5
ns
twCH
Write hold time after xCAS low (see Note 12)
15
15
15
ns
tCLCH
Hold time, xCAS low to xCAS high
5
5
5
ns
IAWD
Delay time, column address to W low (see Note 14)
55
63
70
ns
20
20
20
ns
tCHR
Delay time, RAS low to xCAS high (see Note 11)
tCRP
Delay time, xCAS high to RAS low
5
5
5
ns
tCSH
Delay time, RAS low to xCAS high
60
70
80
ns
tCSR
Delay time, xCAS low to RAS low (see Note 11)
10
10
10
ns
tCWD
Delay time, xCAS low to W low (see Note 14)
40
46
50
ns
tOEH
OE command hold time
15
18
20
ns
tOED
Delay time, OE high before data at DQ
15
18
20
ns
tROH
Delay time, OE low to RAS high
10
10
10
tRAD
Delay time, RAS low to column address (see Note 15)
15
tRAL
Delay time, column address to RAS high
30
35
40
tCAL
Delay time, column address to xCAS high
30
35
40
tRCD
Delay time, RAS low to xCAS low (see Note 15)
20
tRPC
Delay time, RAS high to xCAS low
a
a
a
ns
tRSH
Delay time, xCAS low to RAS high
15
18
20
ns
tRWD
Delay time, RAS low to W low (see Note 14)
85
98
110
ns
tcpw
Delay time, W from xCAS precharge
60
68
75
ns
tCPRH
RAS hold time from xCAS precharge
35
40
45
ns
tCPR
xCAS precharge before self refresh
0
0
a
ns
110
130
150
ns
tRPS
NOTES:
RAS precharge after self refresh
5.
10.
11.
12.
13.
14.
15.
Timing measurements are referenced to VIL max and VIH min.
Reference to the first xCAS or \N, whichever occurs last.
xCAS-before-RAS refresh only.
Early write operation only.
Either tRRH or tRCH must be satisfied for a read cycle.
Read-modify-write operation only.
Maximum value specified only to assure access time.
TEXAS ~
INSTRUMENTS
4-306
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
30
45
15
20
35
52
15
20
ns
40
ns
ns
ns
60
ns
TMS418160, TMS418160P
1048 576-WORD BY 16-BIT HIGH-SPEED
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS86Q-DECEMBER 1992
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (concluded) (see Note 5)
'418160-60
'418160P-60
MIN
IRASS
Self refresh enlry from RAS low
ICHS
xCAS low hold lime after RAS high (self refresh)
tREF
Refresh time interval (TMS418160 only)
MAX
MIN
tREF
Refresh time interval, low power (TM.S418160P only)
Transition time
'418160-80
'418160P-80
MAX
MIN
100
100
100
-50
-50
-50
16
IT
NOTES:
'418160-70
'418160P-70
I-'S
ns
16
128
3
128
30
3
30
UNIT
MAX
16
ms
128
ms
30
ns
3
5. Timing measurements are referenced 10 V,L max and V,H min.
PARAMETER MEASUREMENT INFORMATION
1.31 V
VCC
= 5V
3:
->w
Rl = 828 Q
w
Output Under Test
Output Under Test
T
T
(a) Load Circuit
R2
a:
= 295 Q
a..
o....
:J
C
(b) Alternate Load Circuit
Figure 1. Load Circuits for Timing Parameters
o
a:
a..
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443· HOUSTON, TExAs 77001
4-307
TMS418160, TMS418160P
1 048 576-WORD BY 16-BIT HIGH-SPEED
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS86(}-OECEMBER 1992
PARAMETER MEASUREMENT INFORMATION
I"
RAS
~
IT
-.!
I
tASR
::c
o
c
c
o
AO-A9
e::
tRCD
::c
m
<
m
I
----.r
I 1<1- tRP 4
~ICAS;/
IClCH
(see Nole A)
~
i~ 1
'il
~
I I
I
~
I I
I'
I I
I
- I
I'll
I ItCSH~
I I
I'll
IRSHI I
I
I I
I
w
a:
0...
....
o
:::l
C
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a:
DQO-OQ15
D.
Valid Data-In
I
I
I4-tOED~
I
I
14
tDS (see Note C)
tOEH--~~
NOTES: A. In order to hold the address latched by the first xCAS going low, the parameter tCLCH must be met.
B. xCAS order is arbitrary.
C. Reference to the first xCAS or VIi, whichever occurs last.
Figure 3. Write Cycle Timing
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
4-309
TMS418160, TMS418160P
1048 576-WORD BY 16-BIT HIGH-SPEED
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS860-DECEMBER 1992
PARAMETER MEASUREMENT INFORMATION
"tJ
:D
o
AO-A9
C
C
o
~
w
"tJ
:D
m
S
m
==
DQO-DQ15
NOTES: A. In order to hold the address latched by the first xCAS going low, the parameter tCLCH must be met.
B. xCAS order is arbitrary.
Figure 4. Early Write Cycle Timing
TEXAS ~
INsrRUMENTS
4-310
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
TMS418160, TMS418160P
1048 576-WORD BY 16-BI1 HIGH-SPEED
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS860-DECEMBER 1992
PARAMETER MEASUREMENT INFORMATION
~
AD-A9
w
:>
w
a:
a.
I-
o
::l
C
o
a:
OQ8-0Q15
I
I'll
~
I
I
I
I
I i+-+I-I I
Y7
I'll
tOHO I
a.
~tOH
I
~tos
I
I
tOEZ
I
~
I
I
I I
tOED
(see Note D)
OQD-OQ7
NOTES: A.
B.
C.
D.
-----------{X:x:X
In order to hold the adaress latched by the first xCAS going low, the parameter tCLCH must be met.
xCAS order is arbitrary.
tCAC in measured from xCAS to its corresponding DQx.
Output might go from a high-impedance state to an invalid data state prior to the specified access time.
Figure 5. Read-Modify-Write Cycle Timing
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
4-311
TMS418160, TMS418160P
1048 576·WORD BY 16-81T HIGH·SPEED
DYNAMIC RANDOM·ACCESS MEMORIES
SMKS86(}-OECEMBER 1992
PARAMETER MEASUREMENT INFORMATION
I"
tRP
~
UCAS
----+-:~:--""'7'\
I I
I I
I I
I I
ill
I 1II
I I
I I
!
I
I
tCLCH
(see Note A)
'I
I
14---- tCR~ ~
~
I
I
I
I
II
tCPRH
'"
I
~!,.
I
I '
I tCSH ~
I
-,
,I
~
!.
.t
tRSH
~
I
I
II
I
II
,tpc
I
I
~I
I
I
I
I
I
I I"- tcp ~ I
I
I
I I
I
I
I
e-----I-I~---~ tASR
I I \ I
i /'
" ~
/"
I
I·
I
I I '---../1
\
/1
I
I I
I
I4--t
---.I I
I
I tRAH....J4..-+I
I
1-4I~t
I
I
CAL
,I
I
I
I I I I ~t
I
I"
tRAL
~
I
I I I
j"'"'1 CAH
I
.
"'C
:c
o
c
c
o-I
~
tRASP
I I+- tRCD ~
I
I I
~
tCAS!,.
I
,
AG-A9
t
RAD
~
1-
w ~;
x>E0Of:I
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:c
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-
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-I I I
:I II L
I
I
I
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:
I
~ I
r':
I"
:E
' tRAC
tCLZ
(see Note D)
DQ8-DQ15
~
I :
I I
I" I ~
I I
1
I
I
I~
~II
: :
~tRRH
I4--tRCH~
~~
1
1'0';
I
~tAA
~~~~~~~~~~~
Don't Care 'V\/V'o,/vvvv
A/\,/\/\,/\/\,/\/\V\/\
I
I
tCAC
Column
I
tCPA
(see Note F)
~
.'::
I
I
I
I:
(see Note D)
!.-
alld
, Out
I
C
I tO~A 14
I
:. I
~ ~tOHO
OE
:
I --.I
,
I
I II"-tAA
~
: I
~
Out I
DQG-DQ7
tOH
I
I
~ tOFF
~
I
I
I alld _----~I---;.----------
~
I
I
~%~~;&
_ ..... -
~~:~~~a~~mx~toEA~
1i0>l
tOEZ
1>----------
Valid "\
Out.
~...J..l
r i ., tOHO
I
~~*~~£i:&m
NOTES: A.
B.
C.
D.
E.
In order to hold the address latched by the first xCAS going low, the parameter tCLCH must be met.
tCAC is measured from xCAS to its corresponding DQx.
xCAS order is arbitrary.
Output may go from high·impedance to an invalid data state prior to the specified access time.
A wr~e cycle or read·modify·write cycle can be mixed with the read cycles as long as the write and read-modify-write timing
specifications are not violated.
F. Access time is tCPA or tAA dependent.
Figure 6. Enhanced Page-Mode Read Cycle Timing
TEXAS
~
INSfRUMENTS
4-312
POST OFFICE BOX 1443· HOUSTON. TEXAS 77001
TMS418160, TMS418160P
1048 576-WORD BY 16-BIT HIGH-SPEED
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS860-DECEMBER 1992
PARAMETER MEASUREMENT INFORMATION
tRP~
N
II
II
\
(
.
,.
I I
: I
14
I I
j4- tCLCH --.I
1
I'll
I I+-- tRCD ---+I (see Note A) :
I.
I t
~
_ I
I CSH
~ I
N--tCAS~/
I tASR I f
I
I ~ ~I tCAH
1
ItASC-'I~
1
1
1"1
I
I
I
r
j
jill
:
I
I
-+li+-tRAH
i'l--""i..1
rl'-
tRASP
I
1
I
1
~tRSH~
I
I tCPRH
.
tcp
-+I
~
tpc
I
tCRP
~
/
'I
1
-
I
~I
H ~
,.-+------
I
I
I
I
I
I
I
I
I
I
I
I
~I
1
1
II
I
I
I
~
~~~bo=~~~~~~
AO-A9
3:
w
:>
w
a:
0.
....
o
::J
C
oa:
0.
NOTES: A. In order to hold the address latched by the first xCAS going low, the parameter tCLCH must be met.
B. xCAS order is arbitrary.
C. A read cycle or read-modify-write cycle can be mixed with the write cycles as long as the read and read-modify-write timing
specifications are not violated.
D. Referenced to the first xCAS or W, whichever occurs last.
Figure 7. Enhanced Page-Mode Write Cycle Timing
TEXAS ~
INsrRUMENTS
POST OFFICE BOX 1443· HOUSTON, TEXAS 77001
4-313
TMS418160, TMS418160P
1048 576·WORD BY 16·BIT HIGH·SPEED
DYNAMIC RANDOM·ACCESS MEMORIES
SMKS860-DECEMBER 1992
PARAMETER MEASUREMENT INFORMATION
~
tRP
I"
tRASP
~
----------+l~: I I
RAS~I~. .
iF}
il~~~======~tCC!S~H~======~~~I----------~~~t:R:SH~::--=-=-=~~; , ' - - - - I i+ tRCD ---.!
I
I
~ !.- tCRP
I I
J.."fI'
tPRWC
'::~I
I
/
11
-+I
i
AO-A9
: :
~~
II
I I
I I
II
I I
I I
I I
I I '\
tCAS
---to~
I
I+-- tCLCH ---+j
I
(see Note A)
ROw_
"o
lJ
C
W
C
o-4
I
~~2&~Vil
I
tCAH
I
tAA· I.. I
I
I
~I
H
DQO-DQ1S - - - - - - - - & : ) ( .
m
14-- tOEA ~
I+--- tRAC I
tCLZ
:$;
~
::E
-7.
II
II
II
~
Column
II
tCWL
twp
~
I+i
I
I
I"
lOIII
I
~I
~1,--_~~22~~~~~
I I
-+l1OIIIt
I I
~
~II
j"
I I
~:
tAA
~I
tDS
~I
I
J<-"---~
Valid Out
I
I
OE . .
'X1:--__ 1
I
~tcAcll
"m
lJ
II
::
I ;.-----
I
I
I I I (see Note B) I
II
tR~S ~
11
i
_ _
14- ~
.
I
I
Il!OIII-t
CWO
~I
tAWD --.j
i+--~I-i- tRWO ~
tRAH ~
I
I
If
~tASR : I
t~sc -.I ~
tR~D.1-II ~~I l"
~i
~
~olumn
i\
~tcpl
~I
tOH
(see
Note D)
:
I
114-"--~-
I
tOEH
tOEH
tCPA
(see Note F)
Valid Out
I
I
:
II
w
a:
c..
....
NOTE A: All xCAS must be high.
(J
Figure 9. RAS-Only Refresh Timing
::J
C
oa:
c..
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
4·315
TMS418160, TMS418160P
1048 576·WORD BY 16·BIT HIGH·SPEED
DYNAMIC RANDOM·ACCESS MEMORIES
SMKS860-DECEMBER 1992
PARAMETER MEASUREMENT INFORMATION
AO-A9
"tJ
:c
oc
c:
DQO-DQ15
o
-I
"tJ
((~
tOEA
Jj
:c
m
<
-
Figure 10. Hidden Refresh Cycle Timing
m
::e
TEXAS
~
INSfRUMENTS
4-316
POST OFFICE BOX 1443' HOUSTON, TEXAS 77001
TMS418160, TMS418160P
1048 576·WORD BY 16·BIT HIGH·SPEED
DYNAMIC RANDOM·ACCESS MEMORIES
SMKS860-DECEMBER 1992
PARAMETER MEASUREMENT INFORMATION
~,4--------------------tRC------------------~~'
/4----- tRP ~ ~14----------- tRAS ___________-.l~1 ,
'II
Ir'----
ANY
RAS
,
tRPC xCAS
.1
I I
I ~4------- tCHR -----~~I
~tCSR~ I
~
'i
Y
~ ~ IT
w~:e~i::€a:~:~
AO-A9~}~~r~a!~~
~
w
O Q O - O Q 1 5 - - - - - - - - - - - - - - - - HI-Z - - - - - - - - - - - - - -
:>
w
a:
a..
NOTES: A. Any xCAS may be used.
Figure 11. Automatic (CAS-Before-RAS) Refresh Cycle Timing
I(.J
::J
C
oa:
a..
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
4-317
TMS418160, TMS418160P
1 048 576·WORD BY 16·BIT HIGH·SPEED
DYNAMIC RANDOM·ACCESS MEMORIES
SMKS860--DECEMBER 1992
PARAMETER MEASUREMENT INFORMATION
144----- IRASS ----~.I
1
1
~I
N
A
-----' 1
I "'--_ _ _ _ _ _ _ _ _J
tRPC ~
tCSR
~ tRPS ~
I
+.i i+
I
~
--.I!----.:N
I
I
~ tCPR ~
"tJ
:D
o
C
c
o
-I
"tJ
m
<
m
=E
-
Figure 12. Self Refresh Timing
device symbolization
t~
TI
:=)
TMS418160 ~
W
~
P
T¥
Speed (-60, -70, -80)
Low Power/Refresh Option
Package Code
Lot Traceability Code
Date Code
Assembly Site Code
Ole Revision Code
Wafer Fab Code
TEXAS ~.
INSTRUMENTS
4·318
~ tCHS
: ~~~~.
~~
I I
:D
I
~
POST OFFICE BOX 1443' HOUSTON, TEXAS 77001
TMS428160, TMS428160P
1048 576·WORD BY 16·BIT HIGH·SPEED
LOW VOLTAGE DYNAMIC RANDOM·ACCESS MEMORIES
SMKS286--DECEMBER 1992
•
•
•
RE PACKAGEt
(TOP VIEW)
Organization ... 1 048 576 x 16
Single 3.3-V Supply (±0.3V Tolerance)
ACCESS ACCESS ACCESS READ OR
TIME
TIME
TIME
WRITE
tAA
CYCLE
tRAC
tCAC
MAX
MAX
MAX
MIN
70ns
18ns
35 ns
130 ns
80 ns
20 ns
40ns
150ns
•
Enhanced Page Mode Operation With
CAS-Before-RAS Refresh
•
Long Refresh Period ...
1024-Cycle Refresh In 16 ms (Max)
128 ms Max for Low-Power, Self-Refresh
Version (TMS428160P)
•
3-State Unlatched Output
•
Low Power Dissipation
- 100!AA CMOS Standby
- 100!AA Extended Refresh Battery Backup
•
Vss
VCC
DOO
D01
D02
D03
2
D02
D03
D015
D014
D013
D012
D015
D014
D013
D012
VCC
Vss
VCC
6
VSS
D04
D05
D011
D010
D09
DOS
NC
LCAS
UCAS
D04
D05
Performance Ranges:
'428160/P-70
'428160/P-80
•
•
DCPACKAGEt
(TOP VIEW)
Self-Refresh With Low Power
DO?
NC
NC
IN
RAS
NC
NC
AO
A1
A2
A3
High-Reliability Plastic 42-Lead
400-MII-Wlde Surface Mount (SOJ)
Package, and 44/50-Lead Thin Small
Outline Package (TSOP)
•
Operating Free-Air Temperature Range
O°C to 70°C
•
Texas Instruments EPIC ™ CMOS Process
DO?
NC
D011
D010
D09
DOS
NC
OE
A9
AS
A?
A6
A5
A4
VCC
All Inputs, Outputs, and Clocks are TTL
Compatible
Vss
Vss
NC
NC
IN
RAS
NC
NC
AO
A1
A2
A3
VCC
NC
LCAS
UCAS
OE
A9
AS
A?
A6
A5
A4
VSS
The TMS428160 series are high-speed, low
voltage, 16 777 216-bit dynamic random-access
memories organized as 1 048 576 words of
sixteen bits each.
The TMS428160P series are high-speed, low
voltage, low-power, self-refresh, 16 777 216-bit
dynamic random-access memories organized as
1 048576 words of sixteen bits each.
W
VCC
VSS
EPIC is a trademark of Texas Instruments Incorporated.
Ih... procl_wllhoutnollcl.
TEXAS
~
Copyright © 1992, Texas Instruments Incorporated
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
I0
::l
a..
Address Inputs
Data In/Data Out
Lower Column-Address Strobe
Upper Column-Address Strobe
No Internal Connection
Output Enable
Row-Address Strobe
Write Enable
3.3-V Supply
Ground
These devices feature maximum RAS access times of 70 ns and 80 ns. Maximum power dissipation is as low
as 0.36 mW standby and battery backup on 80-ns devices.
dill Ind othll' epecfflCltlona art dllign goa... T'XlI
Instruments. res'fve. the right ID chang. or dticonUnul
a..
a:
They employ state-of-the-art EPIC'" (Enhanced Performance Implanted CMOS) technology for high
performance, reliability, and low power at low cost.
PRODUCT PREVIEW info_Ion ......m. prodocllin Ih.
formattv, or dulgn phi. 01 dlYtlopm.nt. Characteristic
a:
0
PIN NOMENCLATURE
description
:>
W
C
t Packages are shown for pinout reference only
AD-A9
DOD-DOI5
LCAS
UCAS
NC
OE
RAS
3:
W
4-319
TMS428160, TMS428160P
1 ()48 576-WORD BY 16-BIT HIGH-SPEED
LOW VOLTAGE DYNAMIC RANDOM-ACCESS MEMORIES
SMKS286-DECEMBER 1992
All inputs and outputs, including clocks, are compatible with Series 74 TTL. All addresses and data-in lines are
latched on-chip to simplify system design. Data out is unlatched to allow greater system flexibility.
The TMS428160 and TMS428160P are each offered in a 42-lead plastic surface mount SOJ (RE suffix)
package, and a 44/50-lead plastic surface mount TSOP (DC suffix). These packages are characterized for
operation from O°C to 70°C.
operation
dual CAS
Two CAS pins (LCAS-UCAS) are provided to give independent control of the sixteen, data 110 pins
(000-0015), with LCAS corresponding to 000-007 and UCAS corresponding to 008-0015. For read or
write cycles, the column address is latched on the first xCAS falling edge. Each xCAS pin going low enables
its corresponding DO pin with data coming from the column address to be latched on the first falling xCAS edge.
All address setup and hold parameters are referenced to the first falling xCAS edge.The delay time from xCAS
low to valid data out (see parameter tCAC) is measured from each individual CAS to its corresponding OOx pin.
In order to latch in a new column address, all xCAS pins must be brought high. The column prechargetime (see
parameter tcp) is measured from the last xCAS rising edge to the first falling xCAS edge of the new cycle.
Keeping a column address valid while toggling xCAS requires a minimum setup time, tCLCH' During tCLCH, at
least one xCAS must be brought low before the other xCAS is taken high.
"tJ
J]
o
For early write cycles, the data is latched on the first falling xCAS edge. Only the DOs that have the
corresponding xCAS low will be written into. Each xCAS will have to meet tCAS minimum in order to ensure
writing into the storage cell. In order to latch a new address and new data, all xCAS pins need to come
high and meet tcp
c
c
(')
-I
"tJ
enhanced page mode
Page-mode operation allows faster memory access by keeping the same row address while selecting random
column addresses. The time for row-address setup and hold and address multiplex is thus eliminated. The
maximum number of columns that may be accessed is determined by the maximum RAS low time and the xCAS
page-mode cycle time used. With minimum xCAS page cycle time, all 1024 columns specified by column
addresses AO through A9 can be accessed without intervening RAS cycles.
J]
m
m
<
-
:e
Unlike conventional page-mode DRAMs, the column-address buffers in this device are activated on the falling
edge of RAS. The buffers act as transparent or flow-through latches while xCAS is high. The falling edge of the
first xCAS latches the column addresses. This feature allows the devices to operate at a higher data bandwidth
than conventional page-mode parts, because data retrieval begins as soon as column address is valid rather
than when xCAS transitions low. This performance improvement is referred to as enhanced page mode. Valid
column address may be presented immediately after tRAH (row address hold time) has been satisfied, usually
well in advance ofthe falling edge of xCAS. In this case, data is obtained aftertcAc max (access time from xCAS
low) if tAA max (access time from column address) has been satisfied. In the event that column addresses for
the next page cycle are valid at the time xCAS goes high, minimum access time for the next cycle is determined
by tCPA (access time from rising edge of the last xCAS).
address (AO-A9)
Twenty address bits are required to decode 1 of 1 048 576 storage cell locations. Ten row-address bits are set
up on pins AO through A9 and latched onto the chip by RAS. Then, ten column-address bits are set up on pins
AO through A9 and latched onto the chip by the first xCAS. All addresses must be stable on or before the falling
edge of RAS and xCAS. RAS is similar to a chip enable in that it activates the sense amplifiers as well as the
row decoder. xCAS is used as a chip select, activating its corresponding output buffer and latching the address
bits into the column-address buffers.
TEXAS ~
INsrRUMENTS
4-320
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
TMS428160, TMS428160P
1048 576·WORD BY 16·BIT HIGH·SPEED
LOW VOLTAGE DYNAMIC RANDOM·ACCESS MEMORIES
SMKS286-DECEMBER 1992
write enable (W)
The read or write mode is selected through the W input. A logic high on the W input selects the read mode and
a logic low selects the write mode. The write-enable terminal can be driven from the standard TTL circuits without
a pull up resistor. The data inputs are disabled when the read mode is selected. When W goes low prior to xCAS
(early write), data out will remain in the high-impedance state for the entire cycle permitting a write operation
with OE grounded.
data in (DQO-DQ15)
Data is written during a write or read-modify-write cycle. Depending on the mode of operation, the falling edge
of xCAS or W strobes data into the on-Chip data latch. In an early-write cycle, W is brought low prior to xCAS
and the data is strobed in by the first occurring xCAS with setup and hold times referenced to this signal. In a
delayed-write or read-modify-write cycle, xCAS will already be low, thus the data will be strobed in by W with
setup and hold times referenced to this signal. In a delayed-write or read-modify-write cycle, OE must be high
to bring the output buffers to high impedance prior to impressing data on the 1(0 lines.
data out (DQO-DQ15)
The three-state output buffer provides direct TTL compatibility (no pullup resistor required) with a fanout of two
Series 74 TTL loads. Data out is the same polarity as data in. The output is in the high-impedance (floating) state
until xCAS and OE are brought low. In a read cycle, the output becomes valid after the access time interval tCAC
(which begins with the negative transition of xCAS) as long as tRAC and tAA are satisfied.
output enable (OE)
OE controls the impedance ofthe output buffers. When OE is high, the buffers will remain in the high-impedance
state. Bringing OE low during a normal cycle will activate the output buffers, putting them in the low-impedance
state. It is necessary for both RAS and xCAS to be brought low for the output buffers to go into low-impedance
state, they will remain in the low-impedance state until either OE or xCAS is brought high.
3:
w
:>
w
a:
c..
I(J
RAS-only refresh
A refresh operation must be performed at least once every sixteen milliseconds (128 ms for TMS428160P) to
retain data. This can be achieved by strobing each of the 1024 rows (AO-A9). A normal read or write cycle will
refresh all bits in each row that is selected. A RAS-only operation can be used by holding all xCAS at the high
(inactive) level, thus conserving power as the output buffers remain in the high-impedance state. Externally
generated addresses must be used for a RAS-only refresh.
hidden refresh
Hidden refresh may be performed while maintaining valid data at the output pin. This is accomplished by holding
xCAS at VIL after a read operation and cycling RAS after a specified precharge period, similar to a RAS-only
refresh cycle.
xCAS-before-RAS refresh
xCAS-before-RAS refresh is utilized by bringing at least one xCAS low earlier than RAS (see parameter tCSR)
and holding it low after RAS falls (see parameter tCHR)' For successive xCAS-before-RAS refresh cycles,
xCAS can remain low while cycling RAS. The external address is ignored and the refresh address is generated
internally. The external address is also ignored during the hidden refresh option.
A low-power battery-backup refresh mode that requires less than 100 ~ refresh current is available on the
TMS428160P. Data integrity is maintained using xCAS-before-RAS refresh with a period of 1251ls while holding·
RAS low for less than 1 Ils. To minimize current consumption, all input levels need to be at CMOS levels
(VIL < 0.2 V, VIH > Vec - 0.2 V).
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
4-321
~
C
o
a:
c..
TMS428160, TMS428160P
1048 576·WORD BY 16·BIT HIGH·SPEED
LOW VOLTAGE DYNAMIC RANDOM·ACCESS MEMORIES
SMKS286-DECEMBER 1992
self refresh (TMS428160P)
The self-refresh mode is entered by dropping xCAS low prior to RAS going low. Then xCAS and RAS are both
held low for a minimum of 100 !-IS. The chip is then refreshed internally by an on-board oscillator. No external
address is required since the CBR counter is used to keep track of the address. To exit the self-refresh mode
both RAS and xCAS are brought high to satisfy tCHS' Upon exiting self-refresh mode, a burst refresh (refresh
a full set of row addresses) must be executed before continuing with normal operation. The burst refresh
ensures the DRAM is fully refreshed.
power up
To achieve proper device operation, an initial pause of 200 !-IS followed by a minimum of eight RAS cycles is
required after power-up to the full Vee level.
"tJ
J]
o
c
o
c
-I
"tJ
J]
m
S
m
=E
TEXAS ~
INSTRUMENTS
4-322
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
TMS428160, TMS428160P
1 048 576-WORD BY 16-BIT HIGH-SPEED
LOW VOLTAGE DYNAMIC RANDOM-ACCESS MEMORIES
SMKS286-DECEMBER 1992
logic symbol t
RAM1Mx16
AO
A1
A2
A3
A4
AS
A6
A7
A8
A9
17
18
19
20
23
24
25
26
27
28
14
31
20010/2100
0
A 1 048575
20019/2109
~
.~
:> C20[ROW]
G23/[REFRESH ROW]
24[PWROWN)
:> C21
G24
&
31
30
W 13
OE 29
000
001
002
003
004
005
006
007
008
009
0010
0011
0012
0013
0014
0015
2
3
4
5
7
8
9
10
33
~
...
UJ
G34
&
31
Z31
23,210
5>
UJ
23C32
a:
+
a.
~,25EN27
tO
34,25EN37
25
A,220
::J
r
"1
4- V26,27
C
o
A,Z26
a:
..
..
L
34
35
36
38
39
40
41
3:
> C21
r
'"
23C22
a.
A,320
V36,37
A,Z36
tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and lEe Publication 617-12.
The pin numbers shown correspond to the RE package.
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
4-323
TMS428160, TMS428160P
1048 576·WORD BY 16·BIT HIGH·SPEED
LOW VOLTAGE DYNAMIC RANDOM·ACCESS MEMORIES
SMKS2B6--DECEMBER 1992
functional block diagram
t t t t t
l
A1
A9
1
t
AO
Timing and Control
/
9
/
•
•
•
Column
Address
Buffers
1
256KArray
256KArray
256KArray
•
32<
Row
Address
Buffers
W
Sense Amplifiers
L
•
•
•
~
Column Decode
R
0
w
••
0
e
c
10
L±
256KArray
•
••
32
I/O
Buffers
16 of 32
Selection
0
1
d
e
~
~
In
Reg.
Data
Out
Reg.
000-0015
'--
256K Array
'---
"'C
10
JJ
C
o
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage range on any pin (see Note 1) ...................................... - 0.5 V to 4.6 V
Supply voltage range on Vee ...................................................... - 0.5 V to 4.6 V
Short circuit output current ................................................................ 50 mA
Power dissipation .......................................................................... 1 W
Operating free-air temperature range .................................................. DoC to 70°C
Storage temperature range ....................................................... - 55°C to 125°C
-I
"'C
JJ
m
m
S
:i:E
l'
/
o
C
256KArray
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. This is a stress rating only, and
functional operation of the device at these or any other conditions beyond those indicated in the "recommended operating conditions" section
of this specification is not implied. Exposure to absolute-maximum-rated conditions lor extended periods may affect device reliability.
NOTE 1: All voltage values in this data sheet are with respect to VSS.
recommended operating conditions
Vee
Supply voltage
VSS
Supply voltage
VIH
High-level input voltage
VIL
Low-level input voltage (see Note 2)
rA
Operating free-air temperature
MIN
NOM
MAX
3.0
3.3
3.6
0
..
UNIT
V
V
V
2.0
Vee+0.3
-0.3
0.8
V
0
70
°e
NOTE 2: The algebraic convention, where the more negative (less positive) limit is designated as minimUm, IS used In thiS data sheet for
logic voltage levels only.
TEXAS •
INSTRUMENTS
4-324
POST OFFICE BOX 1443· HOUSTON. TEXAS 77001
TMS428160, TMS428160P
1048 576·WORD BY 16·BIT HIGH·SPEED
LOW VOLTAGE DYNAMIC RANDOM·ACCESS MEMORIES
SMKS286-DECEMBER 1992
electrical characteristics overfull ranges of recommended operating conditions (unless otherwise
noted)
PARAMETER
'428160-70
' 428160P-70
TEST CONDITIONS
MIN
'428160-80
'428160P-80
MAX
MIN
UNIT
MAX
VOH
High-level output vo~age
10H =-2 rnA
VOL
Low-level output voltage
10L= 2 rnA
VOH
Option
10H = - 100!lA
VOL
Option
10L = 100!lA
II
Input current (leakage)
VCC = 3.6 V, VI = 0 to 3.9 V,
All other pins = 0 V to VCC
10
Output current (leakage)
VCC = 3.6 V, Va = 0 to VCC, xCAS high
±10
±10
I'A
ICC1H
Read or write cycle current
VCC = 3.6 V, Minimum cycle
TBD
TBD
rnA
1
1
rnA
'428160
300
300
!lA
'428160P
100
100
!lA
Average refresh current (RAS-only
orCBR)
VCC = 3.6 V, Minimum cycle,
RAS cycling, xCAS high (RAS only)
RAS low after xCAS low (CBR)
TBD
TBD
rnA
ICC4 t §
Average page current
VCC = 3.6 V, tpc = minimum,
RAS low, xCAS cycling
TBD
TBD
rnA
ICC61!
Self refresh
xCAS < 0.2 V, RAS < 0.2 V,
Measured after tRASS minimum
100
100
!lA
ICC7t
Standby current, outputs enabled
RAS = VIH, xCAS = VIL,
Data out = enabled
5
5
rnA
Battery back-up operating current
(equivalent refresh time is 128 ms).
CBRonly.
IRC = 1251's, tRAS s 1 I's,
VCC-0.2V sVIH s 3.9 V,
a V s VIL s 0.2 V, Wand OE = VIH,
Address and Data stable
2.4
VCC-0.2
VIH = 2 V (LVTTL),
After 1 memory cycle,
RAS and xCAS high
ICC2
ICC3;
ICClOlI
Standby current
2.4
V
0.4
VIH = VCC - 0.2 V (LVCMOS) ,
After 1 memory cycle,
RAS and xCAS high
0.4
V
V
VCC-0.2
0.2
0.2
V
±10
±10
!lA
:>
w
a:
0..
I-
o
::J
C
100
100
!lA
oa:
0..
t Measured with outputs open.
Measured with a maximum of one address change while RAS = VIL.
§ Measured with a maximum of one address change while xCAS = VIH.
11 For TMS428160P only.
*
TEXAS ~
IN8rRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
3=
w
4-325
TMS428160, TMS428160P
1048 576·WORD BY 16·BIT HIGH·SPEED
LOW VOLTAGE DYNAMIC RANDOM·ACCESS MEMORIES
SMKS286-DECEMBER 1992
capacitance over recommended ranges of supply voltage and operating free-air temperature,
f = 1 MHz (see Note 3)
PARAMETER
MIN
TYP
MAX
UNIT
Ci(A)
Input capacitance, address inputs
5
Ci(OE)
Input capacitance, output enable
7
pF
Ci(RC)
Input capacitance, strobe inputs
7
pF
Ci(W)
Input capacitance, write-enable input
7
pF
Co
Output capacitance
7
pF
NOTE 3: VCC equal to 3.3 V ± 0.3 V and the bias on pins under test is 0 V.
'"C
:xl
o
C
C
o
-I
'"C
:xl
m
:S
m
:e
TEXAS ~
INsrRUMENTS
4-326
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
pF
TMS428160, TMS428160P
1 048 576-WORD BY 16·BIT HIGH-SPEED
LOW VOLTAGE DYNAMIC RANDOM·ACCESS MEMORIES
SMKS286-DECEMBER 1992
switching characteristics over recommended ranges of supply voltage and operating free·air
temperature
'428160-70
'428160P-70
PARAMETER
MIN
MAX
'428160-80
'428160P-80
MIN
UNIT
MAX
tCAC
Access time from xCAS low
18
20
ns
tM
Access time from column address
35
40
ns
tRAC
Access time from RAS low
70
80
ns
tOEA
Access time from OE low
18
20
ns
tCPA
Access time from column precharge
40
45
ns
tCLZ
Delay time, xCAS low to output in low Z
0
0
ns
!oH
Output data hold time (from xCAS)
3
3
ns
tOHO
Output data hold time (from OE)
3
!oFF
Output disable time after xCAS high (see Note 4)
0
18
0
20
ns
0
18
0
20
ns
tOEZ Output disable time after OE high (see Note 4)
"
NOTE 4: tOFF and tOEZ are specified
when the output
IS
3
ns
no longer driven.
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (see Note 5)
'428160-70
'428160P-70
MIN
MAX
'428160-80
'428160P-80
MIN
~
>
W
UNIT
MAX
>
w
a:
tRC
Read cycle time (see Note 6)
130
150
ns
twc
Write cycle time
130
150
ns
tRWC
Read-write!read-modify-write cycle time
181
205
ns
tpc
Page-mode read or write cycle time (see Note 7)
45
50
ns
tpRWC
Page-mode read-modify-write cycle time
96
ns
::l
tRASP
Page-mode pulse duration, RAS low (see Note 8)
70
100 000
80
100 000
ns
tRAS
Non-page-mode pulse duration, RAS low (see Note 8)
70
10 000
80
10000
ns
o
tCAS
Pulse duration, xCAS low (see Note 9)
18
10000
20
10 000
ns
tcp
Pulse duration, xCAS high (precharge)
10
10
ns
tRP
Pulse duration, RAS high (precharge)
50
60
ns
twp
Write pulse duration
15
15
ns
tASC
Column-address setup time before xCAS low
Row-address setup time before RAS low
tDS
Data setup time before W low (see Note 10)
tRCS
Read setup time before xCAS low
a
a
a
a
ns
tASR
a
a
a
a
18
20
ns
tCWL
NOTES:
W-Iow setup time before xCAS high
105
ns
ns
ns
5.
6.
7.
8.
Timing measurements are referenced to VIL max and VIH min.
All cycle times assume IT = 5 ns.
tpc > tcp min + tCAS min + 2tT.
In a read-modify-write cycle, tRWD and tRWLmust be observed. Depending onthe user'stransitiontimes, this may require additional
RAS low time (tRAS).
9. In a read-modify-writecycle, tCWD and tCWL must be observed. Depending on the user's transition times, this may require additional
xCAS low time (tCAS).
10. Reference to the first xCAS or \N, whichever occurs last.
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443· HOUSTON. TEXAS 77001
4-327
a..
t-
O
C
a:
a..
TMS428160, TMS428160P
1 048 576·WORD BY 16·BIT HIGH·SPEED
LOW VOLTAGE DYNAMIC RANDOM·ACCESS MEMORIES
SMKS286-0ECEMBER 1992
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (continued) (see Note 5)
'428160-70
'428160P-70
MIN
"tJ
:IJ
o
C
c:
o
~
"tJ
:IJ
m
:S
m
=E
MAX
'428160-80
'428160P-S0
MIN
UNIT
MAX
18
20
ns
0
0
ns
Column-address hold time after xCAS low
15
15
ns
tDH
Data hold time after xCAS low (see Note 10)
15
15
ns
tRAH
Row-address hold time after RAS low
10
10
ns
tRCH
Read hold time after xCAS high (see Note 13)
0
0
ns
tRWl
W-Iow setup time before RAS high
twcs
W-Iow setup time before xCAS low (see Note 12)
tCAH
tRRH
Read hold time after RAS high (see Note 13)
5
5
ns
twCH
Write hold time after xCAS low (see Note 12)
15
15
ns
tClCH
Hold time, xCAS low to xCAS high
5
5
ns
tAWD
Delay time, column address to W low (see Note 14)
63
70
ns
tCHR
Delay time, RAS low to xCAS high (see Note 11)
20
20
ns
tCRP
Delay time, xCAS high to RAS low
5
5
ns
teSH
Delay time, RAS low to xCAS high
70
80
ns
tCSR
Delay time, xCAS low to RAS low (see Note 11)
10
10
ns
tCWD
Delay time, xCAS low to W low (see Note 14)
46
50
ns
tOEH
OE command hold time
18
20
ns
tOED
Delay time, OE high before data at DQ
18
20
ns
tROH
Delay time, OE low to RAS high
10
tRAD
Delay time, RAS low to column address (see Note 15)
15
tRAl
Delay time, column address to RAS high
35
40
tCAl
Delay time, column address to xCAS high
35
40
tRCD
Delay time, RAS low to xCAS low (see Note 15)
20
tRPC
Delay time, RAS high to xCAS low
0
0
ns
tRSH
Delay time, xCAS low to RAS high
18
20
ns
ns
10
35
52
15
20
ns
40
ns
ns
ns
60
ns
tRWD
Delay time, RAS low to W low (see Note 14)
98
110
tepw
Delay time, W from xCAS precharge
68
75
ns
tCPRH
RAS hold time from xCAS precharge
40
45
ns
tePR
xCAS precharge before self refresh
0
0
ns
tRPS
RAS precharge after self refresh
130
150
ns
NOTES:
5.
10.
11.
12.
13.
14.
15.
Timing measurements are referenced to Vil max and VIH min.
Reference to the first xCAS or W, whichever occurs las1.
xCAS-before-RAS refresh only.
Early write operation only.
Either tRRH or tRCH must be satisfied for a read cycle.
Read-modify-write operation only.
Maximum value specified only to assure access time.
TEXAS ~
INSTRUMENTS
4-328
POST OFFICE BOX 1443.· HOUSTON. TEXAS 77001
TMS428160, TMS428160P
1048 576-WORD BY 16-BIT HIGH-SPEED
LOW VOLTAGE DYNAMIC RANDOM-ACCESS MEMORIES
SMKS286-DECEMBER 1992
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (concluded) (see Note 5)
'428160-70
'428160P-70
MIN
tRASS
Self refresh entry from RAS low
tcHS
xCAS low hold time after RAS high (self refresh)
tREF
Refresh time interval (TMS428160 only)
MAX
'428160-80
' 428160P-80
MIN
100
100
-50
-50
~s
ns
16
ms
128
ms
30
ns
16
tREF
Refresh time interval, low power (TMS428160P only)
tr
Transition time
128
3
30
UNIT
MAX
3
NOTE 5: Timing measurements are referenced to VIL max and VIH min.
PARAMETER MEASUREMENT INFORMATION
VCC = 3.3V
1.4V
RL
= 500 0
3:
w
>
w
Rl =11780
Output Under Test - - . - - - .
Output Under Test
T
T
R2
a:
c..
=868 0
...
(J
-=-
(a) Load Circuit
:::>
(b) Alternate Load Circuit
c
o
Figure 1. Load Circuits for Timing Parameters
a:
c..
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443· HOUSTON. TEXAS 77001
4-329
TMS428160, TMS428160P
1048 576·WORD BY 16·BIT HIGH·SPEED
LOW VOLTAGE DYNAMIC RANDOM·ACCESS MEMORIES
SMKS286-DECEMBER 1992
PARAMETER MEASUREMENT INFORMATION
I'll
RAS
Nt-r ~ ~
lCAS
'Y!'I
tRAS
IL.o
UCAS
~
IRC
1'---I j4-'- tRP ~
~----.......
I -+1---...,....-......
--.I
I
t:=::tRCD
:
:
I
I
I
I
I
I
I
I
I
I
I
I
I
I
~tCAS-r
I
j4-'-tRAD~
i~ 1
r
I I
I
I I
I
I
I
I tCSH ~
I
I'll
I
/:
- I
I I
tRSHI I
I I
I I
I I
~ I
I I
I:
::
J..
'il
~
lH-tRAHi:
IltASC~.
: I
"tJ
tASR
:c
o
c
c:
o
AO-AO
~ i+l- ~ I\JV'\. E
~
.;.
1
1
-I
"tJ
~
I I
I
tRCS
tCAl tRAl
1
1
~I ~
W
·1
~ tCAH
I
i
~ tCAC --.I
I (see Note 8)
I
(see Note D)
~
I
I
-----+I
~J
W
I
i
I
tCLZ
I 1414--
I
tRCH --.:
I
tOFF
I
~
I 14
I
tOH
---+I
I
~
Valid Data Out
:E
NOTES: A.
B.
C.
D.
In order to hold the address latched by the first xCAS going low, the parameter tCLCH must be met.
tCAC is measured from xCAS to its corresponding DQx.
xCAS order is arbitrary.
Output may go from high-impedance to an invalid data state prior to the specified access time.
Figure 2. Read Cycle Timing
TEXAS ~
INSTRUMENTS
4-330
I
~
I I
I I
I4----f- tAA ~
DQO-DQ15
tCRP
tcp
~
m +~" ~g:~~~~,---_
:c
m
I
. I
: :
~
I I
I I
I I
tClCH
(see Note A)
j4
~
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
tRRH
TMS428160, TMS428160P
1048 576·WORD BY 16·BIT HIGH·SPEED
LOW VOLTAGE DYNAMIC RANDOM·ACCESS MEMORIES
SMKS286-DECEMBER 1992
PARAMETER MEASUREMENT INFORMATION
LCAS
~
I
I
I
I
I
I
AO-A9~
W
==
~
a:
c..
I-
U
::J
C
oa:
c..
Valid Data-In
DQO-DQ15
I
I
14-- tOED -+i
I
I
l1li
tDS (see Note C)
tOEH--~~
NOTES: A. In order to hold the address latched by the first xCAS going low, the parameter tCLCH must be met.
B. xCAS order is arbitrary.
C. Reference to the first xCAS or W, whichever occurs last.
Figure 3. Write Cycle Timing
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
4-331
TMS428160, TMS428160P
1048 576·WORD BY 16·BIT HIGH·SPEED
LOW VOLTAGE DYNAMIC RANDOM·ACCESS MEMORIES
SMKS286-0ECEMBER 1992
PARAMETER MEASUREMENT INFORMATION
"tJ
:IJ
o
AO-A9
C
C
o
-I
"tJ
w
:IJ
m
S
m
OQO-DQ1S
~
i4
I,
:..
1 1 twp
tRWL
I
~
.1
§§*::~~~;!:~E~:~ valld~at;ln ~~~~~gH~'\%a~~~~~~.
~
:
:,..~
tOH
I+--- tos -.!
NOTES: A. In order to hold the address latched by the first xCAS going low, the parameter tCLCH must be met.
B. xCAS order is arbitrary.
Figure 4. Early Write Cycle Timing
TEXAS ."
INSfRUMENTS
4-332
POST OFFICE BOX 1443· HOUSTON, TEXAS nOOl
TMS428160, TMS428160P
1048 576·WORD BY 16·BIT HIGH·SPEED
LOW VOLTAGE DYNAMIC RANDOM·ACCESS MEMORIES
SMKS286--DECEMBER 1992
PARAMETER MEASUREMENT INFORMATION
3:
w
AO-A9
:>
w
ex:
0-
t-
O
:::J
C
o
I
1'1
~
I
I
I
I
I ~
I I
~i4
ex:
0-
I 1++1- tDH
I
I
1'1-*- tDS
tOEZ
I
I
I
tOHO
~
i
I
I I
tOED
(see Note D)
DQO-OQ7 - - - - - - - - - - - { X
NOTES: A.
B.
C.
D.
In order to hold the address latched by the first xCAS going low, the parameter tCLCH must be met.
xCAS order is arbitrary.
tCAC in measured from xCAS to its corresponding DQx.
Output might go from a high-impedance state to an invalid data state prior to the specified access time.
Figure 5. Read-Modify-Write Cycle Timing
TEXAS ~
INsrRUMENTS
POST OFFICE BOX 1443· HOUSTON. TEXAS 77001
4-333
TMS428160, TMS428160P
1048 576·WORD BY 16·BIT HIGH·SPEED
LOW VOLTAGE DYNAMIC RANDOM·ACCESS MEMORIES
SMKS286--DECEMBER 1992
PARAMETER MEASUREMENT INFORMATION
tRP
}.(
1
UCAS
"'C
lJ
o
~
: :
1 I
I I
(see
I I
I I
I 14
II
I I
I I
~ tASR
I
I
I tRAH ++I
I
I -41
I
I
I I
I
I
I I
I
I
! I
I
C
~
o-I
~
RAD
~
1-
'I
I
tCPRH!
!
tRSH
.1 :
~
I
tCLCH
I
~
I I
Note A) I
1
,tpc
I
I I
I
I
:
I
I
I I
t?SH ~
I
I
I
I I
tCAsI4
~I
I
I
II
I I
I
I 14- tcp
I
I
I I
~---_I..I _ _ _ _1 I
I
I
I
I I \.1
I
7"
I I
I I
L-JI
'\.
II
I I
I I
I
I~
~I 1
I I
1++ tASC
I
~tCAL~ I
I I
I ' - - tCAH
I
JIll
tRAL
~ I
~
-.I
i)'"
I'"l
"'\
I I
~'*'"~~~~~~~~o::'J"I:'?
I
I
t
I
14--- tCR~ ~
I:i.I
~
AO-A9
C
.,
~
tRASP
14- tRCD ~
_ _ _-+1....1_ _.....
14
I
Column
""'V\J'V\J'V\J'V\J
I
Don't Care
VV'oJ\/\./\/\/V\
~tRRH
14-- tRCH ---+i
"'C
lJ
m
S
m
=E
NOTES: A
B.
C.
D.
E.
In order to hold the address latched by the first xCAS going low, the parameter tCLCH must be met.
tCAC is measured from xCAS to its corresponding DOx.
xCAS order is arbitrary.
Output may go from high-impedance to an invalid data state prior to the specified access time.
A write cycle or read-modify-write cycle can be mixed with the read cycles as long as the write and read-modify-write timing
specifications are not violated.
F. Access time is tCPA or tAA dependent.
Figure 6. Enhanced Page-Mode Read Cycle Timing
TEXAS ~
INSTRUMENTS
4-334
POST OFFICE BOX 1443' HOUSTON, TEXAS 77001
TMS428160, TMS428160P
1 048 576·WORD BY 16·BIT HIGH·SPEED
LOW VOLTAGE DYNAMIC RANDOM·ACCESS MEMORIES
SMKS286-DECEMBER 1992
PARAMETER MEASUREMENT INFORMATION
tRP~
N
j+--IRSH~
I I
II
I I
\
(
.,
,
14- tCLCH ----'
I 14-- tRCD ~ (see Note A) i
II
~
I I.
I
I CSH
~
~
: -,-: tASR :
~14____~of-I
ICAS
-.r-- f
I
I
I
I
IASC ....I
-.l~~
$:_ _
Af}-A9
~
tRAH
i
~I
I
I
I
I:
I
ICAH
'"
I ICPRH
IpC
r
I
I
~
1.. 1
I
:.
ICp ---.:
~
,,~
I
~ tCAL
~
hi
"I
ICRP
~
r--+I-----I
I
/
'1
1_
I
~:
I
I
H
I
I
'\
~/
I
I
I
I
I
I
i:
:
I
fi\-
tRASP
I
I
I
~'V~WV'\7l:7'V\7'::i'\:7\:7\:'\7I
"IR;o<::Ai'\:L7\:7\:",*,1
Column
3:
w
:>
w
0:
a.
t-
O
::J
C
o
0:
a.
NOTES: A. In order to hold the address latched by the first xCAS going low, the parameter tCLCH must be met.
B, xCAS order is arbitrary,
C, A read cycle or read-modify-write cycle can be mixed with the write cycles as long as the read and read-modify-write timing
specifications are not violated,
D, Referenced to the first xCAS or W, whichever occurs last.
Figure 7. Enhanced Page-Mode Write Cycle Timing
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
4-335
TMS428160, TMS428160P
1048 576·WORD BY 16·BIT HIGH·SPEED
LOW VOLTAGE DYNAMIC RANDOM·ACCESS MEMORIES
SMKS286-DECEMBER 1992
PARAMETER MEASUREMENT INFORMATION
:.
tRASP
-----------.t.:
f1\tRP ~ j+1 1
RASN
: ~~=t=R=Co=-+I==Tctc~S~H====~.I-----:~:::tR::S:H:---=-.~
}l
I I
I
I
II
I I
I I
I;
-+I
i
tRAP
~
I :
II
I I
I I
A.1.
l
tpRWC
~
teAS
I
I+-- tCLCH ~
I
(see Note A)
~ tASR : I
t~sc --.l ~
.1
.11.
1011
1
~tcpl
I
~'~1~7. ~I;
"oJJ
tRAH ~
I
i+-
IJ
I·
CWO
~I
twp
I I
~tAWO~
14---.J....
w
a::
c.
NOTES: A. Any xCAS may be used.
Figure 11. Automatic (CAS-Before-RAS) Refresh Cycle Timing
IU
::J
C
oa:
c.
TEXAS ~.
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
4-339
TMS428160P
1048 576-WORD BY 16-BIT HIGH-SPEED
LOW VOLTAGE DYNAMIC RANDOM-ACCESS MEMORIES
SMKS286-DECEMBER 1992
PARAMETER MEASUREMENT INFORMATION
i-AO
Vt
I ........_ _ _ _ _ _ _ _ _..J I
tRPC ~
-xCAS
I
N
fi
I
_ _..J
Figure 12. Self Refresh Timing
device symbolization
:E
t
TI
P
TMS428160
-~
~
Speed ( -70, --80)
Low Power/Refresh Option
Package Code
W-AJ'f
1fb
Lot Traceability Code
Date Code
Assembly Site Code
Die Revision Code
Wafer Fab Code
TEXAS
~
INsrRUMENTS
4-340
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
TMS416800, TMS416800P
2097152 WORD BY 8·BIT
DYNAMIC RANDOM·ACCESS MEMORIES
SMKS680-DECEMBER 1992
• Organization ... 2 097 152 x 8
• Single 5-V Power Supply (±10% Tolerance)
• Performance Ranges:
ACCESS ACCESS ACCESS READ
TIME
TIME
TIME OR WRITE
(IRAC) (ICAC)
(IAA)
CYCLE
(MIN)
(MAX)
(MAX)
(MAX)
'416800/P·60
'416800/P·70
'416800/P-80
60 ns
70 ns
80 ns
15 ns
18 ns
20 ns
30 ns
35 ns
40 ns
110 ns
130 ns
150 ns
• Enhanced Page Mode Operation With
CAS-Before-RAS Refresh
• Long Refresh Period ...
- 4096-Cycle Refresh in 64 ms (Max)
- 512 ms for Low Power, Self-Refresh
Version (TMS416800P)
• 3-State Unlatched Output
• Low Power Dissipation
• Self-Refresh With Low-Power
• All Inputs/Outputs and Clocks are TTL
Compatible
• High-Reliability Plastic 28-Pin, J-Lead
400-Mil-Wide Surface Mount (SOJ)
Package, and 32-Pln, Plastic Thin Small
Outline Package (TSOP)
• Operating Free-Air Temperature Range
O°C to 70°C
• Texas Instruments EPIC ™ CMOS Process
DE PACKAGET
(TOP VIEW)
DZPACKAGET
(TOP VIEW)
VCC
VSS
DOO
D01 3
DO?
D06
D05
D04
CAS
IN
RAS
OE
NC
NC
NC
A11
A10
AD
A1
A9
AS
A?
A6
A5
A2
A3
VCC
VSS
DOO
DOl
D02
D03
IN
RAS
A11
A10
AO
A1
A2
A3
DO?
D06
D05
D04
CAS
VCC
OE
A9
AS
A?
A6
A5
A4
VSS
A4
VCC
VSS
3:
w
t Packages are shown for pinout reference only.
:>
w
PIN NOMENCLATURE
A~Al1
CAS
DQ~DQ7
NC
RAS
W
VCC
VSS
description
a:
c..
Address Inputs
Column-Address Strobe
Data In/Data Out
No Internal Connection
Output Enable
Row-Address Strobe
Write-Enable
5-V Supply
Ground
o....
::J
C
o
a:
c..
The TMS416800 series are high-speed 16777 216-bit dynamic random-access memories, organized as
2 097 152 words of eight bits each.
The TMS416800P series are high-speed, low-power, self-refresh, 16 777 216-bit dynamic random-access
memories, organized as 2 097 152 words of eight bits each.
They employ state-of-the-art EPIC™ (Enhanced Performance Implanted CMOS) technology for high
performance, reliability, and low power at a low cost.
These devices feature maximum RAS access times of 60 ns, 70 ns, and 80 ns. Maximum power dissipation is
as low as 385 mW operating and 11 mW standby for 80 ns devices.
All inputs and outputs, including clocks, are compatible with Series 74 TTL. All addresses and data-in lines are
latched on-chip to simplify system design. Data out is unlatched to allow greater system flexibility.
The TMS416800 and TMS416800P series are offered in a 400-mil 28-lead plastic surface mount SOJ package
(DZ suffix) and a 32-lead plastic surface mount TSOP package (DE suffix). These packages are characterized
for operation from O°C to 70°C.
EPIC is a trademark of Texas Instruments Incorporated.
PRODUCT PREVIEW lnIonnotlon ...,""" procIucllln Iho form.llv. or
dellan phi.. of development. ChI,.clerilUc dill Ind other
.peclftClllons .... dulan DOlIa. TUlllnlll1lmtnll reHrves the right to
ching. or dllconUnu,1h... products wtlhout notice.
TEXAS
~
Copyright © 1992, Texas Instruments Incorporated
INSTRUMENTS
POST OFFICE BOX 144,'3 • HOUSTON, TEXAS 77001
4-341
TMS416800, TMS416800P
2097152 WORD BY 8-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS6So-0ECEMBER 1992
operation
enhanced page mode
Enhanced page-mode operation allows faster memory access by keeping the same row address while selecting
random column addresses. The time for row-address setup and hold and address multiplex is thus eliminated.
The maximum number of columns that may be accessed is determined by the maximum RAS low time and the
CAS page cycle time used. With minimum CAS page cycle time, all 512 columns specified by column addresses
AO through A8 can be accessed without intervening RAS cycles.
Unlike conventional page-mode DRAMs, the column-address buffers in this device are activated on the falling
edge of RAS. The buffers act as transparent or flow-through latches while CAS is high. The falling edge of CAS
latches the column addresses. This feature allows the TMS416800 and TMS416800P to operate at a higher
data bandwidth than conventional page-mode parts, since data retrieval begins as soon as the column address
is valid rather than when CAS transitions low. This performance improvement is referred to as enhanced page
mode. Valid column address may be presented immediately after row address hold time has been satisfied,
usually well in advance of the falling edge of CAS. In this case, data is obtained after tCAC max (access time
from CAS low), if tAA max (access time from column address) has been satisfied. In the event that column
addresses for the next cycle are valid at the time CAS goes high, access time for the next cycle is determined
by the later occurrence of tCAC or tCPA (access time from rising edge of CAS).
""C
:c
o
c
address (AD-A11)
Twenty-one address bits are required to decode 1 of 2097 152 storage cell locations. Twelve row-address bits
are set up on inputs AO through A11 and latched onto the chip by the row-address strobe (RAS). The nine
column-address bits are set up on pins AO through A8 and latched onto the chip by the column-address strobe
(CAS). All addresses must be stable on or before the falling edges of RAS and CAS. RAS is similar to a chip
enable in that it activates the sense amplifiers as well as the row decoder. CAS is used as a chip select activating
the output buffer, as well as latching the address bits into the column-address buffer.
c
o
-I
""C
:c
write enable (W)
m
:S
m
=E
The read or write mode is.selected through the write-enable (W) input. A logic high on the W input selects the
read mode and a logic low selects the write mode. The write-enable terminal can be driven from standard TTL
circuits without a pullup resistor. The data input is disabled when the read mode is selected. When W goes low
prior to CAS (early write), data out will remain in the high-impedance state for the entire cycle permitting a write
operation independent of the state of OE. This permits early write operation to be completed with OE grounded.
data In/out (DQD-DQ7)
The three-state output buffer provides direct TTL compatibility (no pullup resistor required) with a fanout of two
Series 74 TTL loads. Data out is the same polarity as data in. The output is in the high-impedance (floating) state
until CAS and OE are brought low. In a read cycle the output becomes valid after all access times are satisfied.
The output remains valid while CAS and OE are low. CAS or OE going high returns it to a high-impedance state.
This is accomplished by bringing OE high prior to applying data, thus satisfying tOED'
TEXAS ~
INSTRUMENTS
4-342
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
TMS416800, TMS416800P
2097152 WORD BY 8-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS681}-OECEMBER 1992
output enable (OE)
OE controls the impedance of the output buffers. When OE is high, the buffers will remain in the high-impedance
state. Bringing OE low during a normal cycle will activate the output buffers putting them in the low-impedance
state. It is necessary for both RAS and CAS to be brought low for the output buffers to go into the low-impedance
state, they will remain in the low-impedance state until either OE or CAS is brought high.
refresh
A refresh operation must be performed at least once every 64 milliseconds (512 ms for TMS416800P) to retain
data. This can be achieved by strobing each of the 4096 rows (AO-A 11). A normal read or write cycle will refresh
all bits in each row that is selected. A RAS-only operation can be used by holding CAS at the high (inactive) level,
thus conserving power as the output buffer remains in the high-impedance state. Externally generated
addresses must be used for a RAS-only refresh.
hidden refresh
Hidden refresh may be performed while maintaining valid data at the output pin. This is accomplished by holding
CAS at VIL after a read operation and cycling RAS after a specified precharge period, similar to a RAS-only
refresh cycle.
CAS-before-RAS refresh
CAS-before-RAS (CBR) refresh is utilized by bringing CAS low earlier than RAS (see parameter t<&B2. and
holding it low after RAS falls (see parameter tCHR)' For successive CAS-before-RAS refresh cycles, CAS can
remain low while cycling RAS. The external address is ignored and the refresh address is generated internally.
A low-power battery-backup refresh mode that requires less than 500 ~ refresh current is available on the
TMS416800P. Data integrity is maintained using CAS-before-RAS refresh with a period of 125 IJS while holding
RAS low for less than 1 ~s. To minimize current consumption, all input levels need to be at CMOS levels
(VIL:S: 0.2 V, VIH .. VCC - 0.2 V).
self refresh (TMS416800P)
The self-refresh mode is entered by dropping CAS low prior to RAS going low. Then CAS and RAS are both
held low for a minimum of 100 ~s. The chip is then refreshed by an on-board oscillator. No external address is
required since the CBR counter is used to keep track of the address. To exit the self-refresh mode, both RAS
and CAS are brought high to satiSfy tCHS' Upon exiting self-refresh mode, a burst refresh (refresh a full set of
row addresses) must be executed before continuing with normal operation. The burst refresh ensures the
DRAM is fully refreshed.
power up
To achieve proper device operation, an initial pause of 200 IJS followed by a minimum of eight RAS cycles is
required after power-up to the full VCC level.
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 1443' HOUSTON, TEXAS 77001
4-343
3:
w
:>
w
a:
D.
I-
o
~
c
o
a:
D.
TMS416800, TMS416800P
2 097 152 WORD BY 8·BIT
DYNAMIC RANDOM·ACCESS MEMORIES
SMKS68~ECEMBER
1992
logic symbol t
RAM2Mx8
AO 10
A1 11
2009/2100 "
A2 12
A3 13
A4 16
A5 17
>
A6 18
A7 19
A8 20
A9 21
A10 9
20018
20019
0
C
CAS 23
0
w
1
"'C
:XJ
OE
:XJ
C
~
m
:S
m
7
6
22
r-...
> C20[ROW)
G23/[REFRESH ROW)
24[PWR OWN)
>
C21[COL)
G24
&
23,210
> 23C22
> 24,25EN
G25
.,
OQO 2
:e
/
20020
p:
f
RAS
09~ 151
20017/2108
A11 8
"'C
A 2
4..
OQ1 3
OQ2 4
OQ3 5
OQ4 24
r
A,220
V26
~
OQ5 25
OQ6 26
OQ7 27
t This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
The pin numbers shown correspond to the DZ package.
TEXAS ~
INsrRUMENTS
4-344
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
A,Z26-
TMS416800, TMS416800P
2097 152 WORD BY 8·BIT
DYNAMIC RANDOM·ACCESS MEMORIES
functional block diagram
,
AO
A1
2
I
,,,,
Timing and Control
32
7
Column Decode
•
•
•
AS
A9, A10, A11
I
Column
Address
Buffers
Sense Amplifiers
L
-
-
•
•
•
32
Row
Address
Buffers
SMKS68o-DECEMBER 1992
256KArray
256KArray
256KArray
256KArray
•
••
II
'8
¥
Q
~
•
••
~
12
2
!t
32
I/O
Buffers
80f32
Selection
0
a:
256KArray
12
rW
In
Reg.
~
Out
Reg.
256K Array
DOD-007
l'
==
w
absolute maximum ratings over operating free·alr temperature range (unless otherwise noted)t
Supply voltage range on any pin (see Note 1) .......................................... - 1 V to 7 V
Supply voltage range on Vee ......................................................... - 1 V to 7 V
Short circuit output current ................................................................ 50 mA
Power dissipation .......................................................................... 1 W
Operating free-air temperature range .................................................. O°C to 70°C
Storage temperature range ....................................................... - 55°C to 125°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. This is a stress rating only, and
functional operation of the device at these or any other conditions beyond those indicated in the "recommended operating conditions" section of
this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values in this data sheet are with respect to VSS.
recommended operating conditions
MIN
NOM
MAX
Vee
Supply voltage
4.5
5
5.5
UNIT
V
VIH
High-level input voltage
2.4
6.5
V
VIL
Low-level input voltage (see Note 2)
-1
0.8
V
TA
Operating free-air temperature
0
70
'e
NOTE 2: The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used in this data sheet for logic
voltage levels only.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443· HOUSTON. TEXAS 77001
4-345
:>
w
[t
c.
~
o
::J
C
o
[t
c.
TMS416800, TMS416800P
2 097 152 WORD BY 8·BIT
DYNAMIC RANDOM·ACCESS MEMORIES
SMKS68o-0ECEMBER 1992
electrical characteristics over full ranges of recommended operating conditions (unless otherwise
noted)
TEST CONDITIONS
PARAMETER
TMS416800-60
TMS416800P-60
MIN
VOH
High-level output
voltage
10H =-5 mA
VOL
Low-level output
voltage
IOL=4.2mA
II
Input current (leakage)
10
ICC1 t
MAX
2.4
TMS416800-70
TMS416800P-70
MIN
MAX
2.4
TMS416800-80
TMS416800P-80
MIN
UNIT
MAX
2.4
V
0.4
0.4
0.4
V
VCC = 5.5 V, VI = 0 to 6.5 V,
All other pins = 0 to VCC
,,10
,,10
,,10
IlA
Output current
(leakage)
VCC = 5.5 V, Vo = 0 to Vcc,
CAS high
,,10
,,10
,,10
IlA
Read or write cycle
current (see Note 3)
VCC = 5.5 V, Minimum cycle
90
80
70
mA
2
2
2
mA
1
1
1
mA
500
500
500
IlA
90
80
70
mA
90
80
70
mA
After 1 memory cycle,
RAS and CAS high,
VIH = 2.4 V (TTL)
"'C
ICC2
Standby current
::D
o
C
C
VIH =VCC-0.2 V
(CMOS),
After 1 memory cycle,
RAS and CAS high
'416800
'416800P
o
ICC3
Average refresh
current (RAS-only or
CBR) (see Note 3)
VCC = 5.5 V, Minimum cycle,
RAS cycling, CAS high,
(RAS-only); RAS low
after CAS low (CBR)
"'C
ICC4t
Average page current
(see Note 4)
VCC = 5.5 V, tpc = Minimum,
RAS low, CAS cycling
ICC10;
Battery backup
operating current
(equivalent refresh
time is 512 ms)
CBR only
tRC = 125 ~s, tRAS s 1 ~s,
VCC - 0.2 V s VIH s 6.5 V,
V s VIL s 0.2 V,
IN and OE = VIH,
Address and Data stable
o
500
500
500
~A
ICC6;
Self refresh current
CAS s 0.2 V, RAS < 0.2 V,
Measured after tRASS minimum
500
500
500
IlA
ICC7t
Standby current,
outputs enabled
RAS = VIH, CAS = VIL
Data out = Enabled
5
5
5
mA
-I
::D
m
:sm
:e
t Measured with outputs open.
; For TMS416800P only.
NOTES: 3. Measured with a maximum of one address change while RAS = VIL.
. 4. Measured with a maximum of one address change while CAS = VIH .
. TEXAS ~
INSTRUMENTS
4-346
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
TMS416800, TMS416800P
2097152 WORD BY 8·BIT
DYNAMIC RANDOM·ACCESS MEMORIES
SMKS680-DECEMBER 1992
capacitance over recommended ranges of supply voltage and operating free-air temperature,
f = 1 MHz (see Note 5)
PARAMETER
MIN
TYP
MAX
UNIT
Ci(A)
Input capacitance, address inputs
5
Ci{OE)
Input capacitance, output enable
7
pF
pF
Ci(RC)
Input capacitance, strobe inputs
7
pF
Ci(W)
Input capacitance, write-enable input
7
pF
Co
Output capacitance
7
pF
NOTE 5: VCC equal to 5 V '" 0.5 V and the bias on pins under test is
a v.
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature
TMS416800·60
TMS416800P-SO
PARAMETER
MIN
MAX
TMS416800·70
TMS416800P·70
MIN
MAX
TMS416800·80
TMS416800P-SO
MIN
UNIT
MAX
tAA
Access time from column-address
30
35
40
ns
!cAC
Access time from CAS low
15
18
20
ns
tCPA
Access time from colum n precharge
35
40
45
ns
tRAC
Access time from RAS low
60
70
80
ns
tOEA
Access time from OE low
15
18
20
ns
tCLZ
CAS to output in low l
a
a
a
ns
tOH
Output disable time, start of CAS high
3
3
3
ns
tOHO
Output disable time, start of OE high
3
3
3
tOFF
Output disable time after CAS high (see Note 6)
tOEl
Output disable time after OE high (see Note 6)
a
a
..
NOTE 6: toFF and tOEl are specified when the output
IS
15
15
a
a
18
18
a
a
ns
20
ns
20
ns
no longer driven .
w
==
:>w
r:t
c..
I-
U
::J
C
or:t
c..
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443· HOUSTON. TEXAS 77001
4-347
TMS416800, TMS416800P
2 097 152 WORD BY 8·BIT
DYNAMIC RANDOM·ACCESS MEMORIES
SMKS680--DECEMBER 1992
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
TMS416800-60
TMS416800P-60
PARAMETER
MIN
"'C
:x:J
MAX
MIN
UNIT
MAX
Random read or write cycle (see Note 7)
110
130
150
ns
Read-modify-write cycle time
155
181
205
ns
Page-mode read or write cycle time (see Note 8)
40
45
50
tpRWC
85
ns
ns
60
100000
96
70
105
tRASP
Page-mode read-modify-write cycle time
Page-mode pulse duration, RAS low (see Note 9)
100000
80
100000
ns
tRAS
Non-page-mode pulse duration, RAS low (see Note 9)
60
10000
70
10000
80
10000
ns
tCAS
tcp
Pulse duration, CAS low (see Note 10)
15
10000
18
10000
20
10000
ns
Pulse duration, CAS high (CAS precharge)
10
10
10
ns
tRP
Pulse duration, RAS high (RAS precharge)
40
50
60
ns
twp
Write pullile duration
15
15
15
ns
tASC
Column-address setup time before CAS low
0
0
0
ns
tASR
tDS
Row-address setup time before RAS low
0
0
0
ns
Data setup time (see Note 11)
Read setup time before CAS low
0
0
0
ns
0
0
0
ns
W,low setup time before CAS high
15
18
20
W-Iow setup time before RAS high
15
18
20
ns
ns
tRCS
C
twcs
-t
MIN
tRWC
tpc
o
o
MAX
TMS416800-80
TMS416800P-80
tRC
tcWL
tRWL
C
TMS416800-70
TMS416800P-70
NOTES: 7.
8.
9.
"'C
:x:J
10.
:e
11.
m
<
m
W-Iow setup time before CAS low
0
0
0
ns
(Early write operation only)
All cycle times assume IT = 5 ns.
To assure tpc min, tASC should be greater than or equal to tCp.
In a read-modify-write cycle, tRWD and tRWLmust be observed. Depending on the user's transition times, this may require additional
RAS low time (tRAS).
In a read-modify-write cycle, tCWD and tCWL must be observed. Depending on the user's transition times, this may require additional
CAS low time (tCAS)'
Referenced to the later of CAS or Win write operations.
TEXAS ~
INSTRUMENTS
4-348
POST OFFICE BOX 1443· HOUSTON. TEXAS 77001
TMS416800, TMS416800P
2097152 WORD BY 8·BIT
DYNAMIC RANDOM·ACCESS MEMORIES
SMKS6SD--DECEMBER 1992
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (continued)
TMS416800-60
TMS416800P-60
PARAMETER
MIN
MAX
TMS416800-70
TMS416800P-70
MIN
MAX
TMS416800-80
TMS416800P-80
MIN
UNIT
MAX
tCAH
Column-address hold time after CAS low
10
15
15
ns
tDH
Data hold time (see Note 11)
10
15
15
ns
tRAH
Row-address hold time after RAS low
10
10
10
ns
tRCH
Read hold time after CAS high (see'Note 12)
0
0
0
ns
tRRH
Read hold time after RAS high (see Note 12)
5
5
5
ns
twCH
Write hold time after CAS low
(Early write operation only)
15
15
15
ns
tAWD
Delay time, column address to W low
(Read-modify-write operation only)
55
63
70
ns
tCHR
Delay time, RAS low to CAS high
(CAS-before-RAS refresh only)
20
20
20
ns
tCRP
Delay time, CAS high to RAS low
5
5
5
ns
tCSH
Delay time, RAS low to CAS high
60
70
80
ns
tCSR
Delay time, CAS low to RAS low
(CAS-before-RAS refresh only)
10
10
10
ns
tcWD
Delay time, CAS low to W low
(Read-modify-write operation only)
40
46
50
ns
tOEH
OE command hold time
15
18
20
ns
tOED
OE to data delay
15
18
20
ns
tROH
RAS hold time referenced to OE
10
10
10
ns
tRAD
Delay time, RAS low to column-address (see Note 13)
15
tRAl
Delay time, column-address to RAS high
30
tCAl
Delay time, column address to CAS high
30
tRCD
Delay time, RAS low to CAS low (see Note 13)
20
tRPC
Delay time, RAS high to CAS low
0
0
0
ns
tRSH
Delay time, CAS low to RAS high
15
18
20
ns
tRWD
Delay time, RAS low to W low
(Read-modify-write operation only)
85
98
110
ns
30
15
35
35
45
20
15
40
40
35
ns
40
52
20
ns
ns
60
ns
tcpw
Delay time, W from CAS precharge
60
68
75
ns
tcPRH
Hold time, RAS from CAS precharge
35
40
45
ns
NOTES: II, Referenced to the later of CAS or W in write operations,
12. E~her tRRH or T RCH must be satisfied for a read cycle.
13. The maximum value is specified only to assure access time.
TEXAS ~
INSTRUMEN1S
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
4-349
~
w
>
w
a:
a.
....
o
::l
o
o
a:
a.
TMS416800, TMS416800P
2 097 152 WORD BY 8·BIT
DYNAMIC RANDOM·ACCESS MEMORIES
SMKS68G-DECEMBER 1992
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (concluded)
TMS416800-60
TMS416800P-60
PARAMETER
MIN
MAX
TMS416800-70
TMS416800P-70
MIN
MAX
TMS416800-80
TMS416800P-80
MIN
UNIT
MAX
tCPR
CAS precharge before self refresh
a
a
0
tRPS
RAS precharge after self refresh
110
130
150
ns
tRASS
Self refresh entry from RAS low
100
100
100
I'S
tCHS
CAS low hold time after RAS high (self-refresh)
tREF
Refresh time interval (TMS416800 only)
-50
tREF
Refresh time interval Low power (TMS416800P only)
IT
Transition time
-50
-50
64
64
512
512
3
30
3
30
3
PARAMETER MEASUREMENT INFORMATION
1.31 V
VCC =5V
"tI
::D
o
C
C
Output Under Test - - - -.....
Output Under Test
o
-I
CL= 100 pF
"tI
::D
m
I
(b) Alternate Load Circuit
(a) Load Circuit
S
m
Figure 1. Load Circuits for Timing Parameters
:e
TEXAS·~
INsrRUMENTS
4-350
POST OFFICE BOX 1443' HOUSTON, TEXAS 77001
ns
ns
64
ms
512
ms
30
ns
TMS416800, TMS416800P
2097152 WORD BY 8·BIT
DYNAMIC RANDOM·ACCESS MEMORIES
SMKS680-DECEMBER 1992
PARAMETER MEASUREMENT INFORMATION
AO-A11
I
I
I
II
II
I
I
I
I
I
:.- tCAH
I
3:
UJ
I+-tRRH
I
.1
:>UJ
tRCH
a:
c.
t-
O
:::)
C
o
a:
c.
NOTE A: Output may go from a high-impedance state to an invalid data state prior to the specified access time.
Figure 2_ Read Cycle Timing
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443· HOUSTON. TEXAS 77001
4-351
TMS416800, TMS416800P
2 097 152 WORD BY 8-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS680-DECEMBER 1992
PARAMETER MEASUREMENT INFORMATION
"'C
:rJ
o
C
c:
o
-I
"'C
:rJ
m
:S
m
:e
Figure 3. Early Write Cycle Timing
TEXAS ~
INSTRUMENTS
4-352
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
TMS416800, TMS416800P
2 097 152 WORD BY 8·BIT
DYNAMIC RANDOM·ACCESS MEMORIES
SMKS680-DECEMBER 1992
PARAMETER MEASUREMENT INFORMATION
~I"~----------------------IRC----------------------~~I
1
1
I"
KI4~--,RP
RAS--""':N
IT ---..: 14-
1
1
I..
I..
CAS
-.I
1
1
1
IASC
NI
:
I..
1
1
1 IRAL
1
~ICAH
1
1
-,,~ "~ ~
i
1
1 1
}t"F~+:I--------~}
i..
~
1
__
:f ;..tt-----ICP -----t~ L
~::
I..~
1
IRAH-+i
~~'--
~I 1 1
::
1
~I
ICAS
1
ICSH
loiii
~ IASR
~I
IRSH
____
~I1 . . 11oIII..ft-I---ICRP
1
1
-----+t~1
IRCD
1 1
1
I1
~I
IRAS
tCAL
1 ~
1 1
1 1
~dz~,------
ICWL~I"~-----~~~ ~
C.I,m,
1
I+- IRAD ---.I
1
a::
1
I"
IRWL
W~~~*R~~~
;=.
w
5>
w
~I
c.
~~~"""'B"""'~**"("7'('7'V*~~~ Io
::J
~I,.--- IWp ----+i
IDS -+i
(see Note A)
1
1
i+L
1
C
(see Note A)
~: tDH-':
DQG-DQ7~R~n~RK;~ vaUdData ~*lK*EZ2~
tOED~
1
I+-
1
I~"----IOEH--------~~I
NOTE A: Referenced to the later of CAS or Win write operations.
Figure 4. Write Cycle Timing
TEXAS ~
INsrRUMENTS
POST OFFICE BOX 1443· HOUSTON. TEXAS 77001
4-353
o
a::
c.
TMS416800, TMS416800P
2 097 152 WORD BY 8-BIT
DYNAMIC .RANDOM-ACCESS MEMORIES
SMKS68o-0EOEMBER 1992
PARAMETER MEASUREMENT INFORMATION
"tJ
lJ
o
C
c:
o
-I
"tJ
lJ
m
:S
m
=E
NOTE A: Output may go from a high-impedance state to an invalid data state prior to the specified access time.
Figure 5. Read-Modify-Write Cycle TiMing
TEXAS ",
INsrRUMENTS
4-354
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
TMS416800, TMS416800P
2097152 WORD BY 8-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS6SO--DECEMBER 1992
PARAMETER MEASUREMENT INFORMATION
tRP
14-------tCPRH
~I
I"
____________________~~
I
I
----J~~
~----------------------~--------~------------,
I
I
-.I
----1~~1+-- tCRP
1
~,------- tRAL --j--+----1~
Column
AO-A11
14-----tAA ---~-~
(see Note A)
w
1
1
1
1
I..
I
1
1 : ' - - tCAC --------.I
~I.._J......;- tAA
~I
tRAC
~I
~tRAO~
1
1
1
I..
tCLZ
i"
~I
tCPA
(see Note A)
I
-~
~ "J~r
OQO-OQ7------------------(S-e-e-N-ot-e-B-)
tOHO
1
I
I 14 ~I
1 1
1
I
1 I
1 1
1 ~I
I 1 I
I.. : I tOH
~I
~ tOFF - - - . :
I
I
I
tOHO
14
i+--tOEA~!
~ I.-- tOEZ
OE~~~X~~~tOEA~ ~
tOEZ
==
W
:;
2I
a:
a.
I-
~I
o
i
~
::J
C
~ o
NOTES: A. Access time is tCPA or tM dependent.
B. Output may go from a high-impedance state to an invalid data state prior to the specified access time.
C. A write cycle or read-modify-write cycle can be intermixed with the read cycles as long as the write and read-modify-write timing
specifications are not violated.
Figure 6. Enhanced Page-Mode Read Cycle Timing
TEXAS ~
INsrRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
w
4-355
a:
a.
TMS416800, TMS416800P
2 097 152 WORD BY 8·BIT
DYNAMIC RANDOM·ACCESS MEMORIES
SMKS680-DECEMBER 1992
PARAMETER MEASUREMENT INFORMATION
AO-A11
I I
tCWL~
I
~tCWL~
""C
:c
o
c
I I I
1"1 I
I
1
~tRWL~
1
I
.1 twp
w~o~S~aJ~ !! ~~@~~
c
II~~
(')
-I
f - - - - - tDS
1.
< i I.
1
I
""C
:c DQO-DQ7~
m
S
m
=E
(see Note A)
Valid
i .1
I
Da~a
(see Note A)
i
~ tOEH -.I
I
I
I
~ Vf~d .~J~~@
In
~ tOEH ---.I
tOED
~
~*H~aXW
14-
I
~t(*~~
NOTES: A. Referenced to the later of CAS or Win write operations.
B. A read cycle or a read-modify-write cycle can be intermixed with the write cycles as long as the read and read-modify-write timing
specifications are not violated.
Figure 7. Enhanced Page-Mode Write Cycle Timing
TEXAS ~
INSTRUMENTS
4-356
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
TMS416800, TMS416800P
2097152 WORD BY 8·BIT
DYNAMIC RANDOM·ACCESS MEMORIES
SMKS68o-DECEMBER 1992
PARAMETER MEASUREMENT INFORMATION
Column
AO-A11
:: i+I
I~
tCWD
~III
w~::
I
I
~
--.!
~ tAWD ---+i I~
Ii itRWD~ I
:
---.J: I~
twp
.1
~ tePA -----.I
I :
I
tAA
*- tDH -.I
---.I:'+-
tCAC~
I
(see Note A)
I
DQO-DQ7............................~)~
tos
r-
tCWL ---.I
:
I
I
I ~tRWL~
II
\l
3:
~1':7~~=7<::7
:~
>
w
a:
tOEH
oI-
Valid Out
I
I
::J
C
o
I~~-~ tOED
a:
I
a.
:
I
I
. . . . . . . . ~~~----~~~~~~
V~
NOTES: A. Output may go from a high-impedance state to an invalid data state prior to the specified access time.
B. A read or write cycle can be intermixed with read-modify-write cycles as long as the read and write timing specifications are not
violated.
Figure 8_ Enhanced Page-Mode Read-Modify-Write Cycle Timing
TEXAS
w
a.
:
I
tCLZ -+i ~ I
I
~tOEA--.I I
I
tOEZ -.I ~:
I
I
II
I
tOHO ~ I ~
~ tOEH -.:
I
OE~
----.I
N:.k02W
~ tRAC f---+i
I
tcpw
III1
tRCS
I~ I
~III
~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
4-357
TMS416800, TMS416800P
2 097 152 WORD BY 8·BIT
DYNAMIC RANDOM·ACCESS MEMORIES
SMKS680-DECEMBER 1992
PARAMETER MEASUREMENT INFORMATION
CAS
AD-A11
~*gX*X~
i:
tASR~ ~RAH
t
~gX~X~
Row
W
~~h*z:ID<
Row
W~~£~~£~
-a
:II
o
OQD-OQ7 - - - - - - - - - - - - - - HI-Z - - - - - - - - - - - - - -
C
c:
o
-I
Figure 9. RAS-Only Refresh Timing
-a
:II
m
m
<
==
TEXAS ~
INSTRUMENTS
4-358
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
TMS416800, TMS416800P
2 097 152 WORD BY 8~BIT
DYNAMIC RANDOM·ACCESS MEMORIES
SMKS68Q-OECEMBER 1992
PARAMETER MEASUREMENT INFORMATION
~1·-------------------tRC------------------~·1
~ tRP ~ 14.------------tRAS ____________~~I 1
1
fi
RAS
1
tRPC
CAS
---.I
Y
I ---Iit:-
II
N
~tCSR-':
~
\{
I
1 ~:.----tCHR ---~.I
~
j+-
JI
IT
w~~oiH*~~
A~A11~O~H*K~
3:
w
DQ~DQ7--------------
HI-Z - - - - - - - - - - - - - - -
Figure 10. Automatic (CAS-Before-RAS) Refresh Cycle Timing
:>
w
a:
c.
I-
o
::l
C
o
a:
c.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
4-359
TMS416800, TMS416800P
2097 152 WORD BY 8·BIT
DYNAMIC RANDOM·ACCESS MEMORIES
SMKS68Cf-OECEMBER 1992
PARAMETER MEASUREMENT INFORMATION
~
I
I
I
!+-- Refresh Cycle ~I
~I
1_
, tRAS }
RAS~
I :
I
I
I
j..
I
tRP
!+tRAS+j
I
I
I
II ~
Ii
I 1
~I l+-tCAH
tCAS
I I
I I
I I
I
II
: I-+i ~tASC
I
I I
tRAH--}.i~111
1
I
I
I
I+-tRP+i
Ni Y \
Y
I I
I I
!+-- Refresh Cycle ~
Memory Cycle ~
!"II~
!~
I I..
.1
:i y!
tCHR
',',
tASR~~~~
-a
tRCS
o
I
I" I
I
I
I
I
I
II
I
1 I I
I
c:
I
I
1.1
~III
w
w
a:
0..
t-
U
~I
:
OQQ-OQ7
NOTE
:::J
C
tOH
(see Note A)
~--Val-Id-Oa-ta-In---"~~*dgH.~
OE~RHt}H~~
A: Referenced to the later of CAS or Win write operations.
Figure 12. Hidden Refresh Cycle (Write)
TEXAS ~
INsrRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
4-361
oa:
0..
TMS416800, TMS416800P
2097 152 WORD BY 8·BIT
DYNAMIC RANDOM·ACCESS MEMORIES
SMKS6SG-OECEMBER 1992
PARAMETER MEASUREMENT INFORMATION
I~"------'-- tRASS ----~~I
I
~I
I"
tCSR-#i
r:----~I
~I
~
N
A
---' 1
tRPC
I
1
N
~
1
J+-tCPR
~
I ......._ _ _ _ _ _ _ _ _..J I
I
I
j+ tRPS -.j
~
I
~ l+-,..t;,.;CH,o.;S......,.........,.
-.r
~HH~
"~HSf~
AO-A11
"C
oE~·HH:~
:c
o
c
c
~
o
DQO-DQ7
-I
J..-tOFF
~_---
"C
Figure 13_ Self Refresh Timing
:c
m
S
m
:E
_ _ _ _ _ _ HI-Z _ _ _ _- - - - - - - -
device symbolization
t-~
TI
o
TMS416800
W
J¥
A
P
T¥
Speed (-60, -70, -80)
Low Power/Refresh Option
Package Code
Lot Traceability Code
Date Code
Assembly Site Code
Ole Revision Code
Wafer Fab Code
TEXAS
~
INSTRUMENTS
4-362
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
TMS417800, TMS417800P
2097152 WORD BY 8-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS780--DECEMBER 1992
• Organization ... 2 097 152 x 8
DE PACKAGEt
(TOP VIEW)
• Single 5-V Power Supply (±10% Tolerance)
DZPACKAGEt
(TOP VIEW)
• Performance Ranges:
'417BOO/P-60
'417BOO/P-70
'417BOO/P-BO
ACCESS ACCESS ACCESS READ
TIME
TIME
TIME OR WRITE
(tRAC) (tCAC)
(tAA)
CYCLE
(MAX)
(MAX)
(MAX)
(MIN)
60 ns
15 ns
30 ns
110 ns
70 ns
lB ns
35 ns
130 ns
BO ns
20 ns
40 ns
150 ns
• Enhanced Page Mode Operation With
CAS-Before-RAS Refresh
• Long Refresh Period ...
- 2048-Cycle Refresh in 32 ms (Max)
- 256 ms for Low Power, Self-Refresh
Version (TMS417800P)
VCC
DOO
D01
VSS
D07
D02
D03
DOS
D04
NC
CAS
Vii
OE
RAS
NC
NC
NC
• 3-State Unlatched Output
• Low Power Dissipation
D06
NC
9
A9
A8
A1
A7
A6
A2
AS
A3
A4
VCC
• Self-Refresh With Low-Power
• All Inputs/Outputs and Clocks are TTL
Compatible
VCC
DOO
VSS
D07
D01
D06
D02
D03
DOS
D04
Vii
CAS
RAS
OE
NC
A10
A9
A8
A7
AO
A1
A2
A3
Vee
A6
A5
A4
Vss
VSS
3:
w
t Packages are shown for pinout reference only.
• High-Reliability Plastic 28-Pin, J-Lead
400-Mil-Wide Surface Mount Package
(SOJ), and 32-Pin, Plastic Thin Small
Outline Package (TSOP)
:>w
PIN NOMENCLATURE
AD-A 10
CAS
DQD-DQ7
NC
OE
RAS
• Operating Free-Air Temperature Range
O°C to 70°C
• Texas Instruments EPIC ™ CMOS Process
IN
Vec
VSS
a:
Address Inputs
Column-Address Strobe
Data In/Data Out
No Internal Connection
. Output Enable
Row-Address Strobe
Write-Enable
5-V Supply
Ground
c..
I(J
::J
C
o
a:
c..
description
The TMS417800 series are high-speed 16777 216-bit dynamic random-access memories, organized as
2097152 words of eight bits each.
The TMS417800P series are high-speed, low-power, self-refresh, 16 777 216-bit dynamic random-access
memories, organized as 2 097 152 words of eight bits each.
They employ state-of-the-art EPIC™ (Enhanced Performance Implanted CMOS) technology for high
performance, reliability, and low power at low cost.
These devices feature maximum RAS access times of 60 ns, 70 ns, and 80 ns. Maximum power dissipation is
as low as 578 mW operating and 11 mW standby for 80 ns devices.
All inputs and outputs, including clocks, are compatible with Series 74 TIL. All addresses and data-in lines are
latched on-chip to simplify system design. Data out is unlatched to allow greater system flexibility.
The TMS417800 and TMS417800P series are offered in a 400-mil 28-lead plastic surface mount SOJ package
(DZ suffix) and a 32-lead plastiC surface mount TSOP package (DE suffix). These packages are characterized
for operation from aoc to 70°C.
EPIC is a trademark of Texas Instruments Incorporated.
PRODUCT PREVIEW information concerns produCIIln the formallv, 01
design phi.. of dlYlloplMnL Cflancleriltlc dlta and other
'peclflcatlont .... dtlign 80111. TUlI Inllrumlnt, rtltl'Ytl thl right to
chang. or dilconHnu,lh... productl wtthoul nolla
TEXAS
~
Copyright © 1992, Texas Instruments Incorporated
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
4-363
TMS417800, TMS417800P
2 097 152 WORD BY 8·BIT
DYNAMIC RANDOM·ACCESS MEMORIES
SMKS78G-OECEMBER 1992
operation
enhanced page mode
Enhanced page-mode operation allows faster memory access by keeping the same row address while selecting
random column addresses. The time for row-address setup and hold and address multiplex is thus eliminated.
The maximum number of columns that may be accessed is determined by the maximum RAS low time and the
CAS page cycle time used. With minimum CAS page cycle time, all 1024 columns specified by column
addresses AO through A9 can be accessed without intervening RAS cycles.
Unlike conventional page-mode DRAMs, the column-address buffers in this device are activated on the falling
edge of RAS. The buffers act as transparent or flow-through latches while CAS is high. The falling edge of CAS
latches the column addresses. This feature allows the TMS417800 and TMS417800P to operate at a higher
data bandwidth than conventional page-mode parts, since data retrieval begins as soon as the column address
is valid rather than when CAS transitions low. This performance improvement is referred to as enhanced page
mode. Valid column address may be presented immediately after row address hold time has been satisfied,
usually well in advance of the falling edge of CAS. In this case, data is obtained after tCAC max (access time
from CAS low), if tAA max (access time from column address) has been satisfied. In the event that column
addresses for the next cycle are valid at the time CAS goes high, access time for the next cycle is determined
by the later occurrence of tCAC or tePA (access time from rising edge of CAS).
"'tJ
:c
address (AO-A10)
o
c
c
o
-I
"'tJ
:c
Twenty-one address bits are required to decode 1 of 2097 152 storage cell locations. Eleven row-address bits
are set up on inputs AO through A 10 and latched onto the chip by the row-address strobe (RAS). The ten
column-address bits are set up on pins AO through A9 and latched onto the chip by the column-address strobe
(CAS). All addresses must be stable on or before the falling edges of RAS and CAS. RAS is similar to a chip
enable in that it activates the sense amplifiers as well as the row decoder. CAS is used as a chip select activating
the output buffer, as well as latching the address bits into the column-address buffer.
write enable (iii)
m
S
m
The read or write mode is selected through the write-enable (W) input. A logic high on the W input selects the
read mode and a logic low selects the write mode. The write-enable terminal can be driven from standard TIL
circuits without a pullup resistor. The data input is disabled when the read mode is selected. When W goes low
prior to CAS (early write), data out will remain in the high-impedance state for the entire cycle permitting a write
operation independent of the state of OE. This permits early write operation to be completed with OE grounded.
:E
data in/out (DOO-DO?)
The three-state output buffer provides direct TIL compatibility (no pullup resistor required) with a fanout of two
Series 74 TIL loads. Data out is the same polarity as data in. The output is in the high-impedance (floating) state
until CAS and OE are brought low. In a read cycle the output becomes valid after all access times are satisfied.
The output remains valid while CAS and OE are low. CAS or OE going high returns it to a high-impedance state.
This is accomplished by bringing OE high prior to applying data, thus satisfying tOED.
TEXAS
~
INsrRUMENTS
4-364
POST OFFICE BOX 1443· HOUSTON. TEXAS 77001
TMS417800, TMS417800P
2097152 WORD BY 8·BIT
DYNAMIC RANDOM·ACCESS MEMORIES
SMKS78~DECEMBER
1992
output enable (OE)
OE controls the impedance of the output buffers. When OE is high, the buffers will remain in the high-impedance
state. Bringing OE low during a normal cycle will activate the output buffers putting them in the low-impedance
state. It is necessary for both RAS and CASto be brought low for the output buffers to go into the low-impedance
state, they will remain in the low-impedance state until either OE or CAS is brought high.
refresh
A refresh operation must be performed at least once every thirty-two milliseconds (256 ms for TMS417800P)
to retain data. This can be achieved by strobing each of the 2048 rows (AO-A 10). A normal read or write cycle
will refresh all bits in each row that is selected. A RAS-only operation can be used by holding CAS at the high
(inactive) level, thus conserving power as the output buffer remains in the high-impedance state. Externally
generated addresses must be used for a RAS-only refresh.
hidden refresh
Hidden refresh may be performed while maintaining valid data at the output pin. This is accomplished by holding
CAS at VIL after a read operation and cycling RAS after a specified precharge period, similar to a RAS-only
refresh cycle.
CAS-before-RAS refresh
CAS-before-RAS (CBR) refresh is utilized by bringing CAS low earlier than RAS (see parameter teSR) and
holding it low after RAS falls (see parameter tCHR)' For successive CAS-before-RAS refresh cycles,
CAS can remain low while cycling RAS. The external address is ignored and the refresh address is generated
internally.
A low-power battery-backup refresh mode that requires less than 500 !-IA refresh current is available on the
TMS417800P. Data integrity is maintained using CAS-before-RAS refresh with a period of 125 !-Is while holding
RAS low for less than 1 !-Is. To minimize current consumption, all input levels need to be at CMOS levels
(VIL" 0.2 V, VIH "" Vce - 0.2 V).
self refresh (TMS417800P)
The self-refresh mode is entered by dropping CAS low prior to RAS going low. Then CAS and RAS are both
held low for a minimum of 100 !-Is. The chip is then refreshed by an on-board oscillator. No external address is
required since the CBR counter is used to keep track of the address. To exit the self-refresh mode, both RAS
and CAS are brought high to satisfy teHS' Upon exiting self-refresh mode, a burst refresh (refresh a full set of
row addresses) must be executed before continuing with normal operation. The burst refresh ensures the
DRAM is fully refreshed.
power up
To achieve proper device operation, an initial pause of 200 !-Is followed by a minimum of eight RAS cycles is
required after power-up to the full Vee level.
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
4-365
3:
W
:>
W
a:
C.
I-
(.)
::l
C
0
a:
C.
TMS417800, TMS417800P
2 097 152 WORD BY 8·BIT
DYNAMIC RANDOM·ACCESS MEMORIES
SMKS78()-OECEMBER 1992
logic symbol t
RAM2MxS
AO 10
Al 11
20010/2100
A2 12
A3 13
A4 16
17
A5
A6 18
A7 19
>A
AS 20
21
A9
Al0 9
20019/2109
20020,
.-
~
I> C20[ROW]
CAS 23
f
f>
c:
w
~
-I
OE
RAS
7
"'C
:c
0
C
0
"'C
6
22
000 2
:c
m
:5
m
=E
G23/[REFRESH ROW]
24[PWR OWN]
C21[COL]
G24
&
"
L.-
001 3
002 4
0
2 097 151
23,210
> 23C22
> 24,25EN
.,
G25
1"'
A,220
V26
003 5
004 24
005 25
D06 26
007 27
t This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12,
The pin numbers shown correspond to the DZ package,
TEXAS ~
INsrRUMENTS
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POST OFFICE BOX 1443· HOUSTON, TEXAS 77001
A,Z26-r
TMS417800, TMS417800P
2097152 WORD BY 8·BIT
DYNAMIC RANDOM·ACCESS MEMORIES
SMKS780-DECEMBER 1992
functional block diagram
w
I
+
AD
AI
•
•
•
A9
t J !
Timing and Control
2/
I
8
32
/
Column Decode
Column
Address
Buffere
256KArray
256KArray
•
•
2
11
256KArray
..
32
256K Array
•
••
."
..
·
32
Row
Address
Buffers
~
Sense Amplifiers
L
•
•
•
t
0
()
c
~
32
~
0
I/O
Buffers
80f32
Selection
II:
/
~
~
In
Reg .
Out
Reg.
~
256KArray
AID
11
/
256K Array
DOD- D07
il
3:
w
~
absolute maximum ratings over operating free-air temperature range (unless otherwise noted}t
Supply voltage range on any pin (see Note 1) .......................................... - 1 V to 7 V
Supply voltage range on Vee ......................................................... - 1 V to 7 V
Short circuit output current ................................................................ 50 mA
Power dissipation .......................................................................... 1 W
Operating free-air temperature range .................................................. O°C to 70°C
Storage temperature range ....................................................... - 55°C to 125°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. This is a stress rating only, and
functional operation of the device at these or any other conditions beyond those indicated in the "recommended operating conditions" section of
this specification is not implied. Exposure to absolute-maxim urn-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values in this data sheet are with respect to VSS.
recommended operating conditions
MIN
NOM
MAX
VCC
Supply voltage
4.5
5
5.5
UNIT
VIH
High-level input voltage
2.4
6.5
V
VIL
Low-level input voltage (see Note 2)
-1
0.8
V
TA
Operating free-air temperature
0
70
'c
V
NOTE 2: The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used in this data sheet for logic
voltage levels only.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
4-367
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Q.
oI-
:::J
C
o
a:
Q.
TMS417800, TMS417800P
2097152 WORD BY 8·BIT
DYNAMIC RANDOM·ACCESS MEMORIES
SMKS78Q-OECEMBER 1992
electrical characteristics over full ranges of recommended operating conditions (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
TMS417800-60
TMS417800P-60
MIN
VOH
High-level output
voltage
10H =-5 rnA
VOL
Low-level-output
voltage
IOL=4.2mA
II
Input current (leakage)
10
ICClt
2.4
ICC2
UNIT
MAX
2.4
V
V
Vee = 5.5 V, VI = 0 to 6.5 V,
All other pins = 0 to VCC
±10
±10
±10
J.tA
Output current
(leakage)
VCC = 5.5 V, Vo = 0 to VCC,
CAS high
±10
±10
±10
IlA
Read or write cycle
current (see Note 3)
VCC = 5.5 V, Minimum cycle
125
115
105
rnA
2
2
2
rnA
1
1
1
rnA
500
500
500
IlA
125
115
105
rnA
Standby current
VIH = VCC-0.2 V
(CMOS),
After 1 memory cycle,
RAS and CAS high
'417800
'417800P
ICC3
Average refresh
current (RAS-only or
CBR) (see Note 3)
VCC = 5.5V, Minimum cycle,
RAS cycling, CAS high,
(RAS-only); RAS low
after CAS low (CBR)
ICC4t
Average page current
(see Note 4)
VCC = 5.5 V, tpc = Minimum,
RAS low, CAS cycling
125
115
105
rnA
ICC10t
Battery backup
operating current
(equivalent refresh
time is 256 ms)
CBRonly
tRC = 125 lIS, tRAS S 1 lIs,
VCC - 0.2 V s VIH s 6.5 V,
o V s VIL s 0.2 V,
IN and OE = VIH,
Address and Data stable
500
500
500
!,A
ICC6*
Self refresh current
CAS s 0.2 V, RAS < 0.2 V,
Measured after tRASS minimum
500
500
500
IlA
ICC7t
Standby current,
outputs enabled
RAS = VIH, CAS = VIL
Data out = Enabled
5
5
5
rnA
l]
m
.~
m
=E
2.4
MIN
0.4
o
-t
'"D
MAX
0.4
l]
c
c
o
MIN
TMS417800-80
TMS417800P-BO
0.4
After 1 memory cycle,
RAS and CAS high,
VIH = 2.4 V (TTL)
'"D
MAX
TMS417800-70
TMS417800P-70
t Measured With outputs open.
*For TMS417800P only.
NOTES:
3. Measured with a maximum of one address change while RAS = VIL.
4. Measured with a maximum of one address change while CAS = VIH.
TEXAS ~
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capacitance over recommended ranges of supply voltage and operating free-air temperature,
f = 1 MHz t (see Note 5)
PARAMETER
MIN
TYP
MAX
UNIT
Ci(A)
Input capacitance, address inputs
5
pF
Ci(OE)
Input capacitance, output enable
7
pF
Ci(RC)
Input capacitance, strobe inputs
7
pF
Ci(W)
Input capacitance, write-enable input
7
pF
Co
Output capacitance
7
pF
NOTE 5: VCC equal to 5 V ± 0.5 V and the bias on pins under test is 0 V.
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature
TMS417800-60
TMS417800P-60
PARAMETER
MIN
MAX
TMS417800-70
TMS417800P·70
MIN
MAX
TMS417800-80
TMS417800P-80
MIN
UNIT
MAX
tAA
Access time from column-address
30
35
40
ns
tCAC
Access time from CAS low
15
18
20
ns
tCPA
Access time from column precharge
35
40
45
ns
tRAC
Access time from RAS low
60
70
80
ns
tOEA
Access time from OE low
15
18
20
ns
tCLZ
CAS to output in low Z
0
0
0
ns
tOH
Output disable time, start of CAS high
3
3
3
ns
tOHO
Output disable time, start of OE high
3
3
3
tOFF
Output disable time after CAS high (see Note 6)
0
15
0
18
0
20
ns
tOEZ
Output disable time after OE high (see Note 6)
0
15
0
18
0
20
ns
..
NOTE 6: tOFF and tOEZ are specified when the output
IS
ns
no longer driven .
~
w
:>
w
a:
D..
....
(.)
::l
C
o
a:
D..
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443· HOUSTON. TEXAS 77001
4-369
TMS417800, TMS417800P
2 097 152 WORD BY 8-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS780-DECEMBER 1992
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
TMS417800-60
TMS417800P-60
PARAMETER
MIN
"tJ
:c
o
c
c
(')
TMS417800-70
TMS417800P-70
MAX
MIN
MAX
TMS417800-80
TMS417800P-SO
MIN
UNIT
MAX
tRC
Random read or write cycle (see Note 7)
110
130
150
ns
tRWC
Read-modify-write cycle time
155
181
205
ns
tpc
Page-mode read or write cycle time (see Note 8)
40
45
50
ns
tpRWC
Page-mode read-modify-write cycle time
85
96
105
tRASP
Page-mode pulse duration, RAS low (see Note 9)
60
100000
70
100000
80
100000
ns
tRAS
Non-page-mode pulse duration, RAS low (see Note 9)
60
10000
70
10000
80
10000
ns
tCAS
Pulse duration, CAS low (see Note 10)
15
10 000
18
10000
20
10000
ns
tcp
Pulse duration, CAS high (CAS precharge)
10
10
10
ns
tRP
Pulse duration, RAS high (RAS precharge)
40
50
60
ns
twp
Write pulse duration
15
15
15
ns
tASC
Column-address setup time before CAS low
0
0
0
ns
tASR
Row-address setup time before RAS low
0
0
0
ns
tDS
Data setup time (see Note 11)
0
0
0
ns
tRCS
Read setup time before CAS low
0
0
0
ns
tCWL
W-Iow setup time before CAS high
15
18
20
ns
tRWL
W-Iow setup time before RAS high
15
18
20
ns
twcs
W-Iow setup time before CAS low
(Early wr~e operation only)
0
0
0
ns.
NOTES:
-I
"tJ
:c
m
S
m
=E
7. All cycle times assume IT = 5 ns.
8. To assure tpc min, tASC should be gr\later than or equal to tcp.
9. In a read-modify-write cycle, tRWD and tRWL must be observed. Depending on the user's transition times, this may require additional
RAS low time (tRAS).
10. In a read-modify-write cycle, tCWD and tCWL must be observed. Depending on the user's transition times, this may require additional
CAS low time (tCAS)'
11. Referenced to the later of CAS or IN in write operations.
TEXAS
~
INsrRUMENTS
4-370
ns
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
TMS417800, TMS417800P
2 097 152 WORD BY 8·BIT
DYNAMIC RANDOM·ACCESS MEMORIES
SMKS780-DECEMBER 1992
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (continued)
TMS417S00-60
TMS417S00P-60
PARAMETER
MIN
MAX
TMS417S00-70
TMS417S00P-70
MIN
MAX
TMS417S00-S0
TMS417S00P-80
MIN
UNIT
MAX
tCAH
Column-address hold time after CAS low
10
15
15
ns
tDH
Data hold time (see Note 11)
10
15
15
ns
tRAH
Row-address hold time after RAS low
10
10
10
ns
tRCH
Read hold time after CAS high (see Note 12)
0
0
0
ns
tRRH
Read hold time after RAS high (see Note 12)
5
5
5
ns
twCH
Write hold time after CAS low
(Early write operation only)
15
15
15
ns
tAWD
Delay time, column address to W low
(Read-modify-write operation only)
55
63
70
ns
tCHR
Delay time, RAS low to CAS high
(CAS-before-RAS refresh only)
20
20
20
ns
tCRP
Delay time, CAS high to RAS low
5
5
5
ns
tCSH
Delay time, RAS low to CAS high
60
70
80
ns
tCSR
Delay time, CAS low to RAS low
(CAS-before-RAS refresh only)
10
10
10
ns
tCWD
Delay time, CAS low to W low
(Read-modify-write operation only)
40
46
50
ns
tOEH
OE command hold time
15
18
20
ns
tOED
OE to data delay
15
18
20
ns
tROH
RAS hold time referenced to OE
10
10
10
ns
tRAD
Delay time, RAS low to column-address (see Note 13)
15
tRAl
Delay time, column-address to RAS high
30
35
40
ns
tCAl
Delay time, column address to CAS high
30
35
40
ns
tRCD
Delay time, RAS low to CAS low (see Note 13)
20
tRPC
Delay time, RAS high to CAS low
30
45
15
20
35
52
15
20
40
60
ns
ns
0
0
0
ns
tRSH
Delay time, CAS low to RAS high
15
18
20
ns
tRWD
Delay time, RAS low to W low
(Read-modify-write operation only)
85
98
110
ns
tcpw
Delay time, W from CAS precharge
60
68
75
ns
tCPRH
Hold time, RAS from CAS precharge
35
40
45
ns
NOTES: 11. Referenced to the later of CAS or 'iN in write operations.
12. Either tRRH or TRCH must be satisfied for a read cycle.
13. The maximum value is specified only to assure access time.
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443· HOUSTON, TEXAS 77001
4-371
~
w
:>
w
a:
a.
I-
o
:l
C
o
a:
a.
TMS417800, TMS417800P
2 097 152 WORD BY 8-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS7BO--DECEMBER 1992
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (concluded)
TMS417800-60
TMS417800P-60
PARAMETER
MIN
MAX
TMS417800-70
TMS417800P-70
MIN
MAX
TMS417800-80
TMS417800P-80
MIN
UNIT
MAX
tCPR
CAS precharge before self refresh
0
0
0
tRPS
RAS precharge after self refresh
110
130
150
ns
tRASS
Self refresh entry from RAS low
100
100
100
f.'S
tCHS
CAS low hold time after RAS high (self-refresh)
tREF
Refresh time interval (TMS417800)
-50
-50
32
tREF
Refresh time interval Low power (TMS417800P only)
IT
Transition time
30
-50
ns
32
256
256
3
ns
3
32
ms
256
ms
30
ns
3
30
PARAMETER MEASUREMENT INFORMATION
1.31 V
"C
l:J
o
VCC = 5V
RL = 218
C
C
Output Under Test - - - - - .
Output Under Test
o
-t
CL=100pF
"C
l:J
m
:S
m
=E
Rl = 828
Q
CL = 100 pF
I
(a) Load Circuit
T
(b) Alternate Load Circuit
Figure 1. Load Circuits for Timing Parameters
TEXAS •
IN5rRUMENTS
4-372
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
Q
TMS417800, TMS417800P
2097152 WORD BY 8·BIT
DYNAMIC RANDOM·ACCESS MEMORIES
SMKS780-DECEMBER 1992
PARAMETER MEASUREMENT INFORMATION
I"
IRC
----.iN
RAS
-J-I
,
,
IRAS
~ IT
ICSH
,I
,.
,,
Nr-'
'..
,I 'r
"
'--.l
1
1
1
~,
,_
IRAD
I!
,..~
I'
RAj..
I"
,
1
, '-------
,~IRP~
~', '
,
"
,
*--IRCD~
, 1
,
1\
, '
,..
~ IASR
~I
Y!
1
IRSH~ !
I ~ICRP---.j
ICAS } I . ' ,
;/! ,
IASC
,
," ,
1\
1
, ..
I .,..'-+-__
ICp
'-----
.1
III
ICAL
.,
,
,
1 1.1
AD-Al0
3:
w
:>
w
a:
a...
I-
o::)
c
o
a:
a...
NOTE A: Output may go from a high-impedance state to an invalid data state prior to the specified access time.
Figure 2. Read Cycle Timing
TEXAS ~
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4-373
TMS417800, TMS417800P
2097152 WORD BY 8-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS78()-OECEMBER 1992
PARAMETER MEASUREMENT INFORMATION
"'C
;JJ
o
c
c:
o-I
"'C
;JJ
m
S
m
=E
Figure 3. Early Write Cycle Timing
TEXAS ~
INsrRUMENTS
4-374
POST OFFICE BOX 1443· HOUSTON, TEXAS 77001
TMS417800, TMS417800P
2 097 152 WORD BY 8·BIT
DYNAMIC RANDOM·ACCESS MEMORIES
SMKS780-DECEMBER 1992
PARAMETER MEASUREMENT INFORMATION
~
w
5>
w
a::
a...
IU
::J
o
o
a::
a...
NOTE A: Referenced to the later of CAS or W in write operations.
Figure 4. Write Cycle Timing
TEXAS ~
INBrRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
4·375
TMS417800, TMS417800P
2 097 152 WORD BY 8·BIT
DYNAMIC RANDOM·ACCESS MEMOIlIES
SMKS78(}-OECEMBER 1992
PARAMETER MEASUREMENT INFORMATION
"'C
lJ
o
C
c:
(")
-I
"'C
lJ
m
m
:S
:e
NOTE A: Output
may go from a high-impedance state to an invalid data state prior to the specified access time.
Figure 5. Read-Modify-Write Cycle Timing
TEXAS ~
INsrRUMENTS
4-376
POST OFFICE BOX 1443· HOUSTON. TEXAS 77001
TMS417800, TMS417800P
2 097 152 WORD BY 8·BIT
DYNAMIC RANDOM·ACCESS MEMORIES
SMKS780-DECEMBER 1992
PARAMETER MEASUREMENT INFORMATION
I~
tRP
_ _ _ _ _ _ _ _ _ _~.j
.1
II
~-------tCPRH------~~~
~----------------------+---------~~~------~,
I
I
1
--------'.~~ tCRP
I
-.I
~---tCAL--~
~------tRAL---T-r~~
Column
AO-A10
~-------tAA----~--~
(see Note A)
w
1
I
j+-tRAD~
1
1
1
1
1
I~
I.-
w
==
:>
w
a:
a.
~
(J
::l
C
NOTES: A. Access time is tCPA or tM dependent.
B. Output may go from a high-impedance state to an invalid data state prior to the specified access time.
C. A wrne cycle or read-modify-write cycle can be intermixed with the read cycles as long as the write and read-modify-write timing
specifications are not violated.
Figure 6. Enhanced Page-Mode Read Cycle Timing
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443' HOUSTON. TEXAS 77001
4-377
oa:
a.
TMS417800, TMS417800P
2 097 152 WORD BY 8·BIT
DYNAMIC RANDOM·ACCESS MEMORIES
SMKS780-DECEMBER 1992
PARAMETER MEASUREMENT INFORMATION
""D
:xJ
o
C
C
o
-I
""D
:xJ
m
m
=E
S
NOTES: A. Referenced to CAS or Vii, whichever occurs last.
B. A read cycle or a read-modify-write cycle can be intermixed with the write cycles as long as the read and read-modify-write timing
specifications are not violated.
Figure 7. Enhanced Page-Mode Write Cycle Timing
TEXAS ~
INSTRUMENTS
4-378
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
TMS417800, TMS417800P
2097152 WORD BY 8-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS780-0ECEMBER 1992
PARAMETER MEASUREMENT INFORMATION
RAS
CAS
tRP-+J
--U
--.I
I
I
tRASP
---------------~
~10II----- tCPRH ----~~II
i
I
I
I
I
I
I
loll
oil
~I I
I I
I
tCSH
loll
~
tPRWC
tRCO
}
~I
--.I ~ tASC
II I
~II I
I
I
I
loll
loll
~
t
tcp
CRP
I
I
I
:
~I
I
loll I
.,!
1Or-+1_ __
tRSH
I
~~
~tASR ~tCAS~
~
II :I
I
I
I
I
--.I
:
Column
AO-A10
::
~
tcwo
Ii
loll
loll
~III
I
III1
tAWO
~III
Ni
w~J::i
I
I
1-
-
~
--+i
r-+-,tRWO~
-1
I
~
i14 tRCS
loll I
~I tAA
~
tRAC :
~I
tCAC ~
(see Note A)
I
I
-.I
I
tcpw
~
I
tCWL
I ~tRWL~
II,...,..,..,...,.,.,....,.,..,...,.,..,,,,,,,,,,
twp
i~
~ tCPA -+I
I 1+ tOH +i
II
I
~ tos
r-
I
\l ~
:011
tOEH
I-
I
(.)
:::J
I I I
--+i i+i I
~tOEA-.J I
tOEZ -.! ~
I
I
II
I
tOHO ~ I~
OE~
a:
Q.
Valid Out
I
OQO-OQ7-------~)~
tCLZ
3:
w
>
w
I
I
1~0II-.r- tOED
I
i
:
I
~tOEH
I
I
+l
C
oa:
Q.
yr-----~~~----~~~~~~
NOTES: A. Output may go from a high-impedance state to an invalid data state prior to the specified access time.
B. A read or write cycle can be intermixed with read-modify-write cycles as long as the read and write timing specifications are not
violated.
Figure 8. Enhanced Page-Mode Read-Modify-Write Cycle Timing
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS .77001
4-379
TMS417800, TMS417800P
2 097 152 WORD BY 8·BIT
DYNAMIC RANDOM·ACCESS MEMORIES
SMKS780-DECEMBER 1992
PARAMETER MEASUREMENT INFORMATION
CAS
AG-A10
~ogX~X~
i
1
t
tASR~ ~RAH
~gX*X~
Row
W
~}*:ID<
Row
W~~£~~f~
"tJ
:IJ
o
OQG-OQ7 - - - - - - - - - - - - - - H I - Z - - - - - - - - - - - - - -
C
C
o-I
Figure 9. RAS·Only Refresh Timing
"tJ
:IJ
m
<
-m
:E
TEXAS ~
INSfRUMENTS
4-380
POST OFFICE BOX 1443' HOUSTON, TEXAS 77001
TMS417800, TMS417800P
2097152 WORD BY 8·BIT
DYNAMIC RANDOM·ACCESS MEMORIES
SMKS7SD-DECEMBER 1992
PARAMETER MEASUREMENT INFORMATION
~1~-------------------tRC------------------~~1
~ tRP ~ ~1~---------tRAS ------------~~I I
I
II
II~----
ANY
RAS
tRPC
CAS
I
-.I
~tCSR -.:
~
\l
I
I ~I~-------- tCHR --------~~I
Y
~~tT
w§§§2§§§§222§202§§202§2§§§02~1*1g*~~
AO-A10~~*H*~~
OQO-OQ7---------------HI-Z - - - - - - - - - - - - - -
3:
->w
w
a:
a..
Figure 10. Automatic (CAS-Before-RAS) Refresh Cycle Timing
.....
U
:::)
C
oa:
a..
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
4-381
TMS417800, TMS417800P
2097 152 WORD BY 8-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS780-DECEMBER 1992
PARAMETER MEASUREMENT INFORMATION
~
~ Memory Cycle ~
I
I~
I 1_
~I I
I jtRAS},Ie
~I
Ii
Y
tCHR
tCAS
11
I I
I I
AG-A10
tRCS
o
~
~
m
~
:e
(see Note A)
tCLZ
1
\
1
I
\
1
~
~
~~*)gH~~
I _
~
Valid Data Out
---+I ~
~~
~~r
}-
~---tO-E-Z-~--'r~
OE~~~""""""""~tOEA
','T-j_ _ _
NOTE A: Output may go from a high-.impedance state to an invalid data state prior to the specified access time.
Figure 11. Hidden Refresh Cycle (Read)
.
TEXAS ~
INSTRUMENTS
4-382
~
II
1
1
1
~~~
DQO-DQ7
.
II
I ~ !+-tCAC
I 14 1 .1 tAA
(')
~I
I
I
~0X~~
\111
14 \ 1.\ \
~III
Wili
I\ I I
cC
1.1
((
I I
tRAH~~ \ I I I i
tAs~~A~
"'C
/~
\
I I
I I
-rJ1 ~tCAH
I r+I ~tASC
:xJ
I
I
I
I Ii
I I
I
~ Refresh Cycle ~
I
tRP
j{
Y
11:f
i
II
~I
I
!+-tRP-+i
I j+tRAS+J I
I
RASN
I
Refresh Cycle
POST OFFICE BOX 1443· HOUSTON. TEXAS n001
--£~~~
TMS417800, TMS417800P
2097152 WORD BY 8·BIT
DYNAMIC RANDOM·ACCESS MEMORIES
SMKS78CH)ECEMBER 1992
PARAMETER MEASUREMENT INFORMATION
LU
==
:>
LU
a:
a.
tO
::J
C
DQG-DQ7~
Valid Data In
~~*HH.~
OE~H{t}!*~~
NOTE A: Referenced to the later of CAS or Win write operations.
Figure 12. Hidden Refresh Cycle (Write)
TEXAS ,.,
INSTRUMENTS
POST OFFICE BOX 1443· HOUSTON, TEXAS 77001
4-383
o
a:
a.
TMS417800, TMS417800P
2 097 152 WORD BY 8-BIT
DYNAMIC RANDOM~-ACCESS MEMORIES
SMKS7SQ-OECEMBER 1992
PARAMETER MEASUREMENT INFORMATION
~gHf~
w~mf~
OE~mE~
AD-A10
"tJ
l:J
o
C
~
C
o
DQD-DQ7
-I
"tJ
l:J
m
S
i.-tOFF
mm~-----
____
HI-Z _ _ _ _- - - - - - - -
Figure 13. Self Refresh Timing
device symbolization
m
:E
t -¥
TI
:=J TMS417800~
'If-
A
Speed (~O, -70, -80)
Low Power/Refresh Option
Package Code
PT'
bfh
Lot Traceability Code
Date Code
Assembly Site Code
Ole Revision Code
Wafer Fab Code
TEXAS ~
INSTRUMENTS
4-384
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
TMS4261 00, TMS426100P
16 777 216-BIT
LOW-VOLTAGE DYNAMIC RANDOM-ACCESS MEMORY
SMKS261--JANUARY 1993
• Organization ... 16 777 216 x 1
• Single 3.3-V Power Supply
(±0.3-V Tolerance)
• Low Power Dissipation (TMS426100P Only)
- 100!.tA CMOS Standby
- 100!.tA Self Refresh
- 100!.tA Extended Refresh Battery
Backup
• Performance Ranges:
OJ PACKAGEt
(TOP VIEW)
VCC
Vss
D
Q
NC
NC
Vi
CAS
RAS
NC
All
A9
ACCESS ACCESS ACCESS
READ
A10
A8
TIME
TIME
TIME
AO
A7
tCAC
(MAX)
tAA
(MAX)
Al
AS
A2
A5
'426100/P-60
tRAC
(MAX)
60 ns
OR WRITE
CYCLE
(MIN)
15 ns
30 ns
110 ns
A3
'426100/P-70
'426100/P-80
70 ns
80 ns
18 ns
20 ns
35 ns
40 ns
130 ns
150 ns
VCC
'426100/P-l0
100 ns
25 ns
50 ns
180 ns
• Enhanced Page Mode Operation for Faster
Memory Access
• CAS-Before-RAS Refresh
• Long Refresh Period ...
- 4096 Cycle Refresh in 64 ms (Max)
- 512 ms Max for Low-Power, Self Refresh
Version (TMS426100P)
• 3-State Unlatched Output
• All Inputs/Outputs and Clocks are TTL
Compatible
• Operating Free-Air Temperature Range
O°C to 70°C
description
The TMS426100 series are high-speed,
low-voltage 16 777 216-bit dynamic randomaccess memories, organized as 16777 216
words by one bit each.
A4
Vss
DGA PACKAGEt
DGB PACKAGEt
(TOP VIEW)
(TOP VIEW)
VCC
D
NC
Vi
VSS
Q
VSS
Q
VSS
NC
NC
NC
CAS
CAS
D
Vi
RAS
NC
NC
RAS
All
A9
A9
All
A10
A8
A8
A10
AO
A7
A7
AO
Al
AS
AS
Al
A2
A2
A5
A5
A3
A4
A4
VCC
VSS
VSS
A3
VCC
t The packages shown are for pinout reference only.
The
TMS426100P
series
are
highspeed, low-voltage low-power, self-refresh,
16 777 216-bit
dynamic
random-access
memories organized as 16 777 216 words by one
bit each.
PIN NOMENCLATURE
AD-All
CAS
D
NC
They employ state-of-the-art EPIC'" (Enhanced
Performance Implanted CMOS) technology for
high performance, reliability, and low voltage at
low cost.
Q
IN
VCC
VSS
Address Inputs
Column-Address Strobe
Data In
No Connection
Data Out
Row-Address Strobe
Write Enable
3.3-V Supply
Ground
EPIC is a trademark of Texas Instruments Incorporated.
PRODUCT PREVIEW information concern. productl tn Ih. formative or
dtllan ph... 01 developmenL Charicterlilic dIll and other
lpecHICItlonl 1ft dllign goall. TIXU Inllrumen•• ,...rvll Ih. right to
ching. or dliconUn.,. th... produclt without nollee.
TEXAS
~
Copyright© 1993, Texas Instruments Incorporated
INsrRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
4-385
->==W
w
c.
a::
t-
O
::l
C
o
a::
c.
TMS4261 00, TMS426100P
16 777 216·81T
LOW·VOLTAGE DYNAMIC RANDOM·ACCESS MEMORY
SMKS261~ANUARY
1993
These devices feature maximum RAS access times of 60 ns, 70 ns, 80 ns. Maximum power dissipation is as
low as 180 mW operating, 0.36 mW standby, and battery backup for an 80-ns device..
All inputs and outputs, and clocks are compatible with Series 74 TTL. All addresses and data-in lines are latched
on-Chip to simplify system design. Data out is unlatched to allow greater system flexibility.
The TMS4261 00, TMS426100P is offered in a 300-mil 24/26-lead plastic surface mount SOJ package
(DJ suffix), a 24/26-lead plastic small outline package (DGA suffix), and a 24/26-lead plastic small outline
package, reverse form (DGB suffix). All packages are characterized for operation from O°C to 70°C.
operation
enhanced page mode
Enhanced page-mode operation allows effectively faster memory access by keeping the same row address and
strobing random column addresses onto the chip. Thus, the time required to set up and strobe row addresses
for the same page is eliminated. The maximum number of columns that may be addressed is determined by
. tRAs,the maximum RAS-Iow width.
The column address buffers in this CMOS device are activated on the falling edge of RAS. They act as a
transparent or flow-through latch, while CAS is high. The falling edge of CAS latches the addresses into these
buffers and also serves as an output enable.
"'D
JJ
o
This feature allows the TMS4261 00 family to operate at a higher data bandwidth than conventional page-mode
parts, since retrieval begins as soon as the column address is valid, rather than when CAS transitions low. The
performance improvement is referred to as enhanced page mode. Valid column address may be presented
immediately after row address hold time has been satisfied, usually well in advance of the falling edge of CAS.
In this case, data is obtained after tCAC max (access time from CAS low), if tAA max (access time from column
address) and tRAC have been satisfied. In the event that the column address for the next cycle is valid at the
time CAS goes high, access time is determined by the later occurrence of tCPA or tCAC'
C
C
o
-I
"'D
JJ
m
S
m
address (AO-A11)
Twenty-four address bits are required to decode 1 of 16 777 216 storage cell locations. Twelve row-address
bits are set up on inputs AD-A 11 and latched during a normal access and during RAS-only refresh as the device
requires 4096 refresh cycles. All addresses must be stable on or before the falling edges of RAS and CAS. RAS
is similar to a chip enable in that it activates the sense amplifiers as well as the row decoder. CAS is used as
a chip select, activating the output buffer, as well as latching the address bits into the column buffer.
~
write enable
(W)
The read or write mode is selected through the write-enable W input. A logic high on the W input selects the
read mode and a logic low selects the write mode. The write-enable terminal can be driven from standard TTL
circuits without a pullup resistor. The data input is disabled when the read mode is selected. When W goes low
prior to CAS (early write), data out will remain in the high-impedance state for the entire cycle, permitting
common I/O operation.
data in (0)
Data is written during a write or read-write cycle. Depending on the mode of operation, the faliling of CAS or W
strobes data into the on-chip data latch. In an early write cycle, W is brought low prior to CAS and the data is
strobed in by CAS with setup and hold times referenced to this signal. In a delayed-write or read-modify-write
cycle, CAS will already be low, thus the data will be strobed in by W with setup and hold times referenced to this
signal.
TEXAS
~
INSTRUMENTS
4-386
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
TMS426100, TMS426100P
16 777 216·81T
LOW·VOLTAGE DYNAMIC RANDOM·ACCESS MEMORY
SMKS261-JANUARY 1993
data out (Q)
The three-state output buffer provides direct TIL compatibility (no pullup resistor required) with a fan-out of two
Series 74 TIL loads. The output is in the high-impedance (floating) state until CAS is brought low. In a read cycle
the output becomes valid at the latest occurrence of tRAC, tAA, tCAC, or tCPA and remains valid while CAS is
low. CAS going high returns it to a high-impedance state. In a delayed-write or read-modify-write cycle, the
output does not change, but retains the state just read.
refresh
A refresh operation must be performed at least once every 64 ms (512 ms for TMS4261 OOP) to retain data. This
can be achieved by strobing each of the 4096 rows (AQ-A11). A normal read or write cycle will refresh all bits
in each row that is selected. A RAS-only operation can be used by holding CAS at a high (inactive) level, thus
conserving power since the output buffer remains in the high-impedance state. Externally generated addresses
must be used for a RAS-only refresh. Hidden refresh may be performed by holding CAS at VIL after a read
operation and cycling RAS after the specified precharge period, similar to a RAS-only refresh cycle except with
CAS held low. Valid data is maintained at the output throughout the hidden refresh cycle. An internal refresh
address provides the refresh address during hidden refresh.
CAS-before-RAS refresh
CAS-before-RAS refresh is utilized by bringing CAS low earlier than RAS (see parameter tCSR) and holding it
low after RAS falls (see parameter tCHR)' For successive CAS-before-RAS refresh cycles, CAS can
remain low while cycling RAS. For this mode of refresh, the external addresses are ignored and the refresh
address is generated internally.
A low-power battery-backup refresh mode that requires less than 100 fAA refresh current is available on the
TMS426100P. Data integrity is maintained using CAS-before-RAS refresh with a period of 125 !-IS, while holding
RAS low for less than 1 !-Is. To minimize current consumption, all input levels need to be at CMOS levels
(VIL:S 0.2 V, VIH .. VCC -0.2 V).
~
w
:>
w
a:
c..
IU
::J
self-refresh
The self-refresh mode is entered by dropping CAS low prior to RAS going low. Then CAS and RAS are both
held low for a minimum of 100 !-Is. The chip is then refreshed internally by an on-board oscillator. No external
address is required since the CSR counter is used to keep track of the address. To exit the self-refresh mode,
both RAS and CAS are brought high to satisfy tCHS'
Upon exiting the self-refresh mode, a burst refresh (refresh a full set of row addresses) must be executed before
continuing with normal operation. This will ensure the DRAM is fully refreshed.
power up
To achieve proper device operation, an initial pause of 200 !-IS followed by a minimum of eight initialization cycles
is required after full VCC level is achieved. These eight initialization cycles need to include at least one refresh
(RAS-only or CAS-before-RAS) cycle.
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
4-387
C
o
a:
c..
TM$4261 00, TMS4261 OOP
16 777 216-BIT
LOW-VOLTAGE DYNAMIC RANDOM-ACCESS MEMORY
SMKS261-JANUARY 1993
test mode
The test mode is initiated with a CAS-before-RAS refresh cycle while simultaneously holding the W input low
(WCBR). The initiate cycle performs an internal refresh cycle while internally setting the device to perform
parallel read or write on subsequent cycles. While in test mode, any desired data sequence can be performed
on the device. The device exits the test mode if a CAS-before-RAS (CBR) refresh cycle with W input held high,
or a RAS-only refresh (ROR) cycle is performed.
Test mode causes the part to be internally reconfigured into a 1M x 16 bit device with 16-bit parallel read and
write data path. Column addressess CAO, CA 1, CA 10, and CA11 are not used. During a read cycle all
16 bits of the internal data bus are compared. If all bits are the same data state, the output pin will go high. If
one or more bits disagree, the output pin will go low. Test time in test mode can thus be reduced by a factor of
16, compared to normal memory mode.
I+-
1
1
1
1
Entry ----'
Cycle
I..!
.1
I+1
1
Test Mode Cycle
I
I
I
Exit
Cycle
-----.I
14- Normal - .
1
Mode
VIH
"tJ
RAS
VIL
Jl
o
C
VIH
CAS
VIL
c:
o
-I
"tJ
Jl
W~
:~
/
11\
t The states of \N, Data·in, and Address are defined by the type of cycle used during test mode.
m
:S
m
Figure 1. Test Mode eycle t
==
TEXAS
~
INsrRUMENTS
4·388
I
POST OFFICE BOX 1443· HOUSTON, TEXAS 77001
VIH
VIL
TMS4261 00, TMS426100P
16777216·BIT
LOW·VOLTAGE DYNAMIC RANDOM·ACCESS MEMORY
SMKS2S1-JANUARY 1993
logic symbol t
AO
A1
A2
A3
A4
AS
A6
A7
A8
A9
A10
A11
RAM 16 384K x 1
10
11
12
13
16
17
18
19
20
30012/21 DO '
0
A 16 383K
23
9
6
31023/21011
I"-
5
~
I'---
25
w
4
o
2
~
~
C30[ROW]
G33 [REFRESH ROW]
34 [PWR OWN]
C31 [COL]
G34
&
3:
w
> 33C32
:;
34 EN
33,310
AV
A,320
w
270
a::
c..
tThis symbol is in accordance with ANSI/IEEE Sid 91-1984 and lEe Publication 617-12.
The pin numbers shown are for the 20/26 pin SOJ package (DJ suffix).
I-
o
functional block diagram
::J
C
o
a::
c..
8
32
AO
A1
Column Decode
Sense Amplifiers
256KArray
256KArray
A11
•
•
•
•
••
256KArray
..,..0
256KArray
•
..
u
0
Row
Address
Buffers
0
~
II:
256KArray
0
••
256KArray
11
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
4-389
TMS4261 00, TMS426100P
16 777 216·BIT
LOW-VOLTAGE DYNAMIC RANDOM·ACCESS MEMORY
SMKS261-JANUARY 1993
absolute maximum ratings over operating free-air temperature range {unless otherwise noted)t
Supply voltage range on any pin, Vss (see Note1) ................................... - 0.5 V to 4.6 V
Supply voltage range, Vee ................................... '.' ................... - 0.5 V to 4.6 V
Short circuit output current ................................................................ 50 mA
Power dissipation .......................................................................... 1 W
Operating free-air temperature range .........•........................................ ooe to 70°C
Storage temperature range ....................................................... - 55°C to 150°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. This is a stress rating only, and
functional operation of the device at these or any other conditions beyond those indicated in the "recommended operating conditions" section
of this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values in this data sheet are with respect to VSS.
recommended operating conditions
"
:c
o
UNIT
MIN
NOM
MAX
VCC
Supply voltage
3.0
3.3
3.6
V
VIH
High-level input voltage
2.0
V
VIL
Low-level input voltage (see Note 2)
VCC+ 0.3
0.8
-0.3
V
Operating free-air temperature
0
70
TA
'c
NOTE 2: The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used in this data sheet for logic
voltage levels only.
C
C
o-I
":cm
<
-
m
==
TEXAS ~
INSfRUMENTS
4-390
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
TMS4261 00, TMS426100P
16 777 216·BIT
LOW·VOLTAGE DYNAMIC RANDOM·ACCESS MEMORY
SMKS261-.JANUARY 1993
electrical characteristics over full ranges of recommended operating conditions (unless otherwise
noted)
PARAMETER
'426100-60
'426100P-60
TEST CONDITIONS
MIN
VOH
High-level output
voltage
IOH =-2 mA
VOL
Low-level output
voltage
IOL= + 2 mA
VOH
Option
IOH=-1OO !lA
VOL
Option
10L= +1OO IAA
II
Input current
(Ieakage)t
10
ICC 1
MAX
2.4
'426100-80
'426100P-80
MIN
MIN
MAX
2.4
VCC-0.2
'426100-10
'4261 OOP-1 0
MAX
2.4
0.4
UNIT
MAX
2.4
0.4
VCC-0.2
MIN
V
0.4
VCC-0.2
0.4
VCC-0.2
V
V
0.2
0.2
0.2
0.2
VI = 0 to 3.9 V,
All other pins = 0 to VCC
±10
±10
±10
±10
IlA
Output current.
(Ieakage)t
Vo = Oto VCC,
CAS high
±10
±10
±10
±10
IlA
Read or write
cycle current
(see Note 3)
VCC =3.6V
70
60
50
40
mA
1
1
1
1
mA
'426100
300
300
300
300
IlA
'426100P
100
100
100
100
!lA
70
60
50
40
mA
60
50
40
35
mA
o
100
100
100
100
!lA
a.
5
5
5
5
rnA
100
100
100
100
!lA
Minimum cycle,
After 1 memory cycle,
RAS and CAS high,
VIH = 2 V (LVTTL)
ICC2
'426100-70
'426100P-70
Standby current
After 1 memory
cycle, RAS and
CAS high, VIH=
VCC-0.2V
(CMOS)
RAS cycling,
ICC3
Average refresh
current (RAS-only or
CSR) (see Note 3):1=
ICC4
Average page current
(see Note 4):1=
ICC6:1=
Self-refresh
ICC7
Standby current
output enable:l=
RAS = VIH, CAS = VIL,
Data out = enabled
Battery backup
(with CSR)
tRC = 125 !lS, tRAS " 1 !ls,
VCC-0.2V "VIH" 3.9 V, 0
V" VIL " 0.2 V,
Wand OE = VIH,
Address and Data stable
ICC 10:1=
CAS high (RAS-only).
RAS low after CAS low
(CSR)
;:
->W
w
a:
a.
t-
(J
::)
C
RAS low, CAS cycling
CAS < 0.2 V, RAS < 0.2 V,
tRAS and tCAS > 1000 ms
..
t MInimum cycle, VCC = 3.6
:1= For TMS4261 OOP only
NOTES: 3. Measured with a maximum of one address change while RAS = VIL.
4. Measured with a maximum of one address change while CAS = VIH.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443· HOUSTON, TEXAS 77001
4-391
a:
TMS4261 00, TMS426100P
16 777 216·81T
LOW·VOLTAGE DYNAMIC RANDOM·ACCESS MEMORY
SMKS261-JANUARY 1993
capacitance over recommended ranges of supply voltage and operating free·alr temperature,
f = 1 MHz (see Note 5)
PARAMETER
MIN
TYP
MAX
UNIT
Ci(A)
Input capacitance. address inputs
5
pF
CI(D)
Input capacitance. data input
5
pF
Ci(RC)
Input capacitance. strobe inputs
7
pF
Ci(W)
Input capacitance. write-enable input
7
pF
Co
Output capacitance
7
pF
NOTE 5: VCC equal to 3.3 V ± 0.3 V and the bias on pins under test is 0 V.
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature
PARAMETER
TMS4261 00-60
TMS426100P-60
MIN
"o
lJ
C
C
o-f
MAX
TMS426100-70
TMS426100P-70
MIN
MAX
TMS426100-aO
TMS426100P-SO
MIN
MAX
TMS4261 00-1 0
TMS4261OOP-l0
MIN
UNIT
MAX
tAA
Access time from column-address
30
35
40
45
ns
tCAC
Access time from CAS low
15
18
20
25
ns
tCPA
Access time from column precharge
35
40
45
50
ns
tRAC
Access time from RAS low
60
70
80
100
ns
tCLZ
CAS to output in low Z
0
0
0
0
ns
tOH
Output disable start of CAS high
3
3
3
3
ns
toFF
Output disable time after CAS high
(see Note 6)
0
15
0
18
NOTE 6: tOFF is specified when the output is no longer driven.
"lJm
<
-
m
~
TEXAS
~
INSIRUMENTS
4-392
POST OFFICE BOX 1443' HOUSTON, TEXAS 77001
0
25
0
25
ns
TMS4261 00, TMS426100P
16 777 216·BIT
LOW·VOLTAGE DYNAMIC RANDOM·ACCESS MEMORY
SMKS2S1-JANUARY 1993
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
TMS4261 00-60
TMS426100P-60
MIN
MAX
TMS4261 00-70
TMS426100P-70
MIN
MAX
TMS4261 00-80
TMS426100P-80
MIN
MAX
TMS426100-10
TMS426100P-10
MIN
UNIT
MAX
tRC
Random read or write cycle (see Note 7)
110
130
150
180
ns
tRWC
Read-write cycle time
130
153
175
210
ns
tpc
Page-mode read or write cycle time
(see Note 8)
40
45
50
55
ns
tpRWC
Page-mode read-write cycle time
60
68
75
85
ns
tRASP
Page-mode pulse duration, RAS low
(see Note 9)
60
100000
70
100000
80
100000
100
100000
ns
tRAS
Non-page-mode pulse duration,
RAS low (see Note 9)
60
10000
70
10000
80
10000
100
10000
ns
100
!AS
10 000
18
10000
20
10 000
25
10000
ns
tRASS
Self-refresh, RAS low time
tCAS
Pulse duration, CAS low (see Note 10)
15
tcp
Pulse duration, CAS high
10
10
10
10
ns
tRP
Pulse duration, RAS high (precharge)
40
50
60
70
ns
110
130
150
180
ns
15
15
15
15
ns
100
100
100
tRPS
RAS precharge after self-refresh
twp
Write pulse duration
tASC
Column-address setup time
before CAS low
0
0
0
0
ns
tASR
Row-address setup time before RAS low
0
0
0
0
ns
tDS
Data setup time (see Note 11)
0
0
0
0
ns
tRCS
Read setup time before CAS low
0
0
0
0
ns
~
w
:>
w
0:::
D.
~
o
tCWL
W low setup time before CAS high
15
25
ns
W low setup time before RAS high
15
18
. 18
20
tRWL
20
25
ns
twcs
W low setup time before CAS low
(Early write operation only)
0
0
0
0
ns
twSR
W high setup time (CAS-before-RAS
refresh only)
10
10
10
10
ns
o
twTs
W low setup time (test mode only)
10
10
10
10
ns
D.
Continued next page.
NOTES: 7. All cycle times assume IT = 5 ns.
8. To assure tpc min, tASC should be greater than or equal to tcp.
9. In a read-write cycle, tRWD and tRWL must be observed.
10. In a read-write cycle, leWD and tCWL must be observed.
11. Referenced to the later of CAS or VI in write operatiolls.
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
4-393
::l
C
0:::
TMS426100, TMS426100P
16 777 216-81T
LOW-VOLTAGE DYNAMIC RANDOM-ACCESS MEMORY
SMKS261...JANUARV 1993
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (continued)
'426100-60
'4261OOP-60
MIN
lJ
o
C
c:
MAX
MIN
MAX
'426100-80
'426100P-80
MIN
MAX
'426100-10
'4261 00P-1 0
MIN
UNIT
MAX
tcAH
Column-address hold time after CAS low
10
15
15
15
ns
tDH
Data hold time (see Note 10)
10
15
15
15
ns
tRAH
Row-address hold time after RAS low
10
10
10
10
ns
tRCH
Read hold time after CAS high (see Note 12)
0
0
0
0
ns
tRRH
Read hold time after RAS high (see Note 12)
5
5
5
5
ns
twCH
Write hold time after CAS low
(Early write operation only)
15
15
15
15
ns
twHR
W high hold time (CAS-before-RAS refresh only)
10
10
10
10
ns
twrH
W low hold time (test mode only)
10
10
10
10
ns
tAWD
Delay time, column address to W low
(Read-write operation only)
30
35
40
45
ns
time, RAS low to CAS high
(CAS-before-RAS refresh only)
20
20
20
20
ns
tCRP
Delay time, CAS high to RAS low
5
5
5
5
ns
tcSH
Delay time, RAS low to CAS high
60
70
80
100
ns
10
10
10
10
ns
tcHR
-c
'426100-70
'426100P-70
tcSR
~
~
time, CAS low to RAS low
(CAS-before-RAS refresh only)
tCHS
CAS low hold time after RAS high (Self-refresh)
-50
-50
-50
-50
ns
-I
tcWD
Delay time, CAS low to W low
(Read-write operation only)
15
18
20
25
ns
'"'C
tRAD
Delay time, RAS low to column-address
(see Note 13)
15
m
S
m
tRAl
Delay time, column-address to RAS high
30
35
40
45
tCAl
Delay time, column address to CAS high
30
35
40
45
tRCD
Delay time, RAS low to CAS low (see Note 13)
20
tRPC
Delay time, RAS high to CAS low
0
0
0
0
ns
tRSH
Delay time, CAS low to RAS high
15
18
20
25
ns
tRWD
Delay time, RAS low to W low
(Read-write operation only)
60
70
80
100
ns
o
lJ
:e
30
45
15
20
35
52
15
20
40
60
15
20
55
ns
ns
ns
75
ns
tCPRH
RAS hold time from CAS precharge
35
40
45
50
ns
tcpw
Delay time, W from CAS precharge
35
40
45
50
ns
trAA
Access time from address (test mode)
35
40
45
50
ns
trCPA
Access time from column precharge (test mode)
40
45
50
55
ns
trRAC
Access time from RAS (test mode)
65
75
85
105
tREF
Refresh time interval
tr
Transition time
64
1'426100
64
512
1'426100P
3
30
512
3
NOTES: 10. In a read-write cycle, tCWD and tCWl must be observed.
12. Enher tRRH or tRCH must be satisfied for a read cycle.
13. The maximum value is specified only to insure access time.
TEXAS
~
INSTRUMENTS
4-394
64
POST OFFICE BOX 1443· HOUSTON. TEXAS 77001
30
512
3
30
3
ns
64
ms
512
ms
30
ns
TMS4261 00, TMS426100P
16 177 216·81T
LOW·VOLTAGE DYNAMIC RANDOM·ACCESS MEMORY
SMKS261-JANUARY 1993
PARAMETER MEASUREMENT INFORMATION
1.4V
~
Output Under Test
VCC =3.3V
RL=500Q
~
Output Under Test - - t - - -........
I
CL=100pF
CL=100pF
(a) Load Circuit
(b) Alternate Load Circuit
Figure 2. Load Circuits for Timing Parameters
I"
tRC
l :...
Ni
~
.
I :
I I
rJ- ~ASR
I..
I
.1
j+-tRAIi
II
~
:11
Row
I
I
N~
tRAD
I"
W
,~~
I
I
I
I
II
II
II
I
I
I
I
:
tCAS
!
I
I
I"
- - - - - ! - I - - HI.Z
II
I..
:
I
I
I
I+f--t- tCRP ~
....
o
~\
...._ _ _ _ :::
C
~IIII
J~~
COlu~n ~gi~af~'----------
Q.
::ltRAL
~I
I
I
I I
I
I I
I
~
I I
I I"
II
--.J I+- tCAH
I
:::
-tRRH
I-
I
~I
::
VIH
tRCH
~
WX\XJXYli~~~~~!m
*--t
_I I
I
CAC
-, I I+--- tOFF ---~~I
~.I
~)I,'-______
I tAA
I"
tOH
I
~
Valid Data Out
,..
(see
Note
A
)
.
tCLZ ~
~I
1_________...7
tRAC
:J
oIX:
I I I I
I I I I
I I I I
I I
II.tCAL
:>w
IX:
-+:--tcp - - -....
tASC
~
w
Q.
-Y~.L:
W~~*2~HWI:
Q
I:
I I
tRSH~
I..
I
I"~
--.I
I
~
Jt I~tRP-.!I \.1.------- VIL
~I
tCSH
I+-- tRCD - - + j
AO-A11
l
""14--lT--------------'!1
I I..
I
I
I
I
I
~I
~ /,
tRAS
v
IL
VOH
':'OL
~I
NOTE A: Output may go from three·state to an invalid data state prior to the specified access time.
Figure 3. Read Cycle Timing
TEXAS ~
INSfRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
4·395
TMS4261 00; TMS4261 OOP
16777 216·81T
LOW·VOLTAGE DYNAMIC RANDOM·ACCESS MEMORY
SMKS261-JANUARY 1993
PARAMETER MEASUREMENT INFORMATION
"'C
:xJ
o
C
c:
o
-I
"'C
:xJ
m
m
==
<
-
Q
---------------HI-Z-------------Figure 4_ Early Write Cycle Timing
TEXAS ~
INsrRUMENTS
4-396
POST OFFICE BOX 1443· HOUSTON, TEXAS 77001
TMS426100, TMS426100P
16 777 216·81T
LOW·VOLTAGE DYNAMIC RANDOM·ACCESS MEMORY
SMKS261-JANUARY 1993
PARAMETER MEASUREMENT INFORMATION
3:
w
:>w
a::
D.
I-
o
::J
C
o
a::
D.
Figure 5. Write Cycle Timing
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
4-397
TMS4261 00, TMS426100P
16 777 216·81T
LOW·VOLTAGE DYNAMIC RANDOM·ACCESS MEMORY
SMKS261-JANUARY 1993
PARAMETER MEASUREMENT INFORMATION
"'C
:D
o
C
C
o-I
"'C
:n
~
m
:E
NOTE A: Output may go from three-state to an invalid data state prior to the specified access time.
Figure 6. Read-Write Cycle Timing
TEXAS ~
INSTRUMENTS
4-398
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
TMS426100, TMS426100P
16 777 216-BIT
LOW-VOLTAGE DYNAMIC RANDOM-ACCESS MEMORY
SMKS261-JANUARY 1993
PARAMETER MEASUREMENT INFORMATION
AG--A11
1
1
I..
VIL
tAA
(see Note B)
VIH
W
VVV'v'VI
1
1
k-tRAD-+I
1
1
1
1
J,.14----- tCPA
1
1
~ tCAC ~
(see Note B)
1
I... I
tAA
~I
~I,.;------ tRAC
.1
1
1
tCLZ
1
--IWW
a:
a.
I-
U
Figure 7. Enhanced Page-Mode Read Cycle Timing
::l
C
0
a:
a.
TEXAS~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
4-399
TMS426100, TMS426100P
16 777 216·81T
LOW·VOLTAGE DYNAMIC RANDOM·ACCESS MEMORY
SMKS261-JANUARY 1993
PARAMETER MEASUREMENT INFORMATION
tRP
N
tRASP
I '
:
tCPRH
14,4
I~
.1 ,;
I
I 14-- tRCD - . .
. I I
I I
I4-tCAS~
:I
;
tpc
I
I
N
.0
tASC~\l
I
I
I
I
I
I
.-,
.1
VIL
I+- tCRP -+I
~ tRSH -1---+'1
I
I
I
;1<-""""1-1- - - - - V I H
I I
I
I
VIL
I.- tcp --+l
I
tCSH
I I
I I
I i+ tRAH +1 I
I I
I I
I I
I
14--l.~I-1 tASR
I I
I
I I
1<11
+~I'
,
VIH
I
I
I"
I
I I
I+- tCAH --t-+I
I
14
I
tRAL
l.-tCAL
.1
I
AO-A11
"'CJ
::D
o
C
~~~~~~~~~~~~--~~~~~~~~~L---~~~~~~~~~VIL
C
o
I+--tDH~
14
I""
-I
"'CJ
; 4 + - - tDH
---~
toIIj4I----tDS
I
(see Note A)
(see Note A)
•
I
I
::D
D
~------------va-II-d-D-at-a-In------------~~
:E
Q
- - - - - - - - - - - - - - - - - - - - - - - - - - - - HI-Z - - - - - - - - - - - - - - - - - - - - - - - - - - -
m
S
m
VOH
NOTES: A. Referenced to CAS or VIi, whichever occurs last.
B. A read cycle or a read-write cycle can be intermixed with write cycle as long as read and read-write timing specifications are not
violated.
Figure 8. Enhanced Page-Mode Write Cycle Timing
TEXAS ",
INSTRUMENTS
4-400
POST OFFICE BOX 1443' HOUSTON. TEXAS 77001
TMS4261 00, TMS426100P
16 777 216·81T
LOW·VOLTAGE DYNAMIC RANDOM·ACCESS MEMORY
SMKS261~ANUARY
1993
PARAMETER MEASUREMENT INFORMATION
~
tRP ---.I
~---------------------tRAsP----------------------~.1 1
1
I
1
VIH
I
I
I
~I
VL
(l\-
~tCPRH:
I
I
I
~I I+--- tRSH ~
~II: tcp
10lil I
1 I
14------------ tCSH
~I
10lil
tpRWC I
1+----- tRCO ----+1~~I
I ,0lil
~tCAS~,
tCRP
: '
Ii t :
1'--_..J~
{i I
tASR
-.!
I
I
:
1
~
AD-A11
.1
~+
10lil
1
~
I .:1
1
t~wo
:
I
I
tOst:
tCAH
I I I
1I I
1 I I
I I I
~:
I
~
I
I
I
I
I
j+J I4-tcwo
~oIIItRCS~1-l
I
W
I I
I 10lil
I I
10lil
., twp
tl
Co'"m,
I
I
I
I I I
~
I
I,~
~tOH
: . - - tRWL ~
1
II
'1
I
I
I~~~~~::: a:
a.
....
: I
I4+-tOH ~
I
o
~tCAC~
*--tAA
14-------- tRAC
1
i
tCLZ~
~I
+----.+- tOFF
~I
I
(see Note A)
(see Note A)
Q
NOTES: A. Output may go from a high impedance state to an invalid data state prior to the specified access time.
B. A read or write cycle can be intermixed with read-write cycles as long as the read and write timing specifications are not violated.
Figure 9. Enhanced Page-Mode Read-Write Cycle Timing
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443· HOUSTON. TEXAS 77001
3:
w
:>
w
r--tCWL~ I I
~
I
~;$~i~::
4-401
o
:::>
o
o
a:
a.
TMS426100, TMS426100P
16777 216·81T
LOW·VOLTAGE DYNAMIC RANDOM·ACCESS MEMORY
SMKS261-JANUARY 1993
PARAMETER MEASUREMENT INFORMATION
I"
tRC
I ~tRAS~
_ _ _ _ _ _ _ _ _ _ _ _ _ _~I I
RAS
I
tCRP-j+-.J"\{
I --+I
:.-
tr
~I
.
I
I.
VIH
~t.-tRP~\'-----VIL
tRPC ~ -.:
~ tCRP
cAs~~~~~~~*~~nX~*~~~~~~~..........,i......:---'-----'--W~~--V'H
tASR ~
14---+1- tRAH
AG-A11 ~:~o~r~%~~ Row
VIL
~:~~~~~:~"___ROW_VIH
VIL
W~:;~~~~~VIH
VIL
"'C
:c
o
D~:*YK*~~VIH
VIL
c
Q--------------~------------------------------------
c
o
~
VOH
VOL
Figure 10. RAS-Only Refresh Timing
"'C
:c
m
S
m
:E
AG-A11 ~:~*~~*~~VIH
VIL
o
~:~~ag~~:~VIH
.
VIL
Q
----------------------------- HI-Z -------------------------Figure 11. Self Refresh Cycle Timing
TEXAS
~
INSTRUMENTS
4-402
POST OFFICE BOX 1443' HOUSTON, TEXAS 77001
vOH
TMS4261 00, TMS426100P
16777216·BIT
LOW·VOLTAGE DYNAMIC RANDOM·ACCESS MEMORY
SMKS261-JANUARY 1993
PARAMETER MEASUREMENT INFORMATION
~14-------------------tRC------------------~~1
14--- tRP ---+i 1~4-------tRAS -----------~~I
I
1
ANY
RAS
1
tRPC CAS
1
1 ;,..1- - - - - V I H
1
.1
I I
14"""~tCSR-+iI
\L
~
w~
twSR
i
I
~
1144------- tCHR
~I ~
----~~I
y,...---------VIH
~
t..----....~'l_I-tWHR
VIH
VIL
o
§00§02§22022222222§*2§§{e~£::*E~ VIL
VIH
VOH
Q
--------------HI·Z--------------VOL
Figure 12. Automatic (CAS-Before-RAS) Refresh Cycle Timing
~
>
w
W
a:
c..
I-
o
::J
C
o
a:
c..
TEXAS
~
INSIRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
4·403
TMS4261 00, TMS426100P
16777216·8IT
LOW·VOLTAGE DYNAMIC RANDOM·ACCESS MEMORY
SMKS261-JANUARY 1993
PARAMETER MEASUREMENT INFORMATION
"'D
J:J
o
C
C
o
-I
"'D
J:J
m
S
m
=E
Figure 13. Hidden Refresh Cycle (Read)
TEXAS ~
INSTRUMENTS
4-404
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
TMS4261 00, TMS426100P
16 777 216·BIT
LOW·VOLTAGE DYNAMIC RANDOM·ACCESS MEMORY
SMKS261-JANUARY 1993
PARAMETER MEASUREMENT INFORMATION
3:
w
>
w
a:
c.
.....
o
::J
Q - - - - - - - - - - HI-Z
-----------\',1-',- - - - - - -
VOH
VOL
Figure 14. Hidden Refresh Cycle (Write)
TEXAS ~
INsrRUMENTS
POST OFFICE BOX 1443· HOUSTON, TEXAS 77001
4-405
C
o
a:
c.
TMS4261 00, TMS4261 OOP
16 777 216·81T
LOW·VOLTAGE DYNAMIC RANDOM·ACCESS MEMORY
SMKS261-JANUARY 1993
PARAMETER MEASUREMENT INFORMATION
1111
.,
tRC
tRAS
·11 ,'
VIH
Y
VIL
"tJ
l:J
o
C
VOH
C
Q ---------------- HI-Z---------------
-I
Figure 15. Test Mode Entry Cycle
o
VOL
"tJ
l:J
m
~11II----------------tRC----------------~·1
S
m
=E
~ tRP ---+j '~111---- tRAS ----~.,
-'1:
RAS _ _ _ _
tCSR ,III
tRPC ~
,
Tl~~~~--~1 ,
CAS~
"'{
I
:
y~---- :::
~
, '~111----1.~1 tCHR
, I
~
r-t-r
I I
tWSR....--.I
yI , - - - - - - - - - - - - -
I
Figure 16. Test Mode Exit Cycle (CAS·Before·RAS Refresh Cycle)
TEXAS
~
INSTRUMENTS
4-406
POST OFFICE BOX 1443' HOUSTON, TEXAS 77001
VIH
TMS426100, TMS426100P
16 777 216·BIT
LOW·VOLTAGE DYNAMIC RANDOM·ACCESS MEMORY
SMKS261-JANUARY 1993
device symbolization
-ss
TI
=:J
TMS426100
DZ
T
Vf-
_A
P
TT
T
Speed (- 60, - 70, - 80, -10)
Power/Refresh Code (blank or P)
Package Code
If-
Lot Traceability Code
Month Code
Assembly SIte Code
DIe RevIsIon Code
Wafer Fab Code
~
->W
w
ex:
a.
....
(J
::J
C
o
ex:
a.
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
4-407
TMS4261 00, TMS426100P
16 777 216·BIT
LOW·VOLTAGE DYNAMIC RANDOM·ACCESS MEMORY
SMKS261-JANUARV 1993
TEXAS ."
IN5rRUMENTS
4-408
POST OFFICE BOX 1443· HOUSTON, TEXAS 77001
TMS426400, TMS426400P
4194 304-WORD BY 4-BIT
LOW-VOLTAGE DYNAMIC RANDOM-ACCESS MEMORIES
SMKS264--JANUARY 1993
•
Organization ... 4 194 304 x 4
•
Single 3.3-V Power Supply (± 0.3 V
Tolerance)
OJ PACKAGEt
(TOP VIEW)
•
Low Power Dissipation (TMS426400P)
- 100!lA CMOS Standby
- 100 !lA Self-Refresh
- 100!lA Extended Refresh Battery Backup
•
Performance Ranges:
'426400/P-60
'426400/P-70
'426400/P-80
'426400/P-l0
ACCESS ACCESS ACCESS READ
TIME
TIME
TIME OR WRITE
tAA
CYCLE
tRAC
tCAC
(MAX)
(MAX)
(MAX)
(MIN)
60ns
15ns
30ns
lIOns
70 ns
18 ns
35 ns
130 ns
80 ns
20 ns
40 ns
150 ns
100 ns
25 ns
45 ns
180 ns
VCC
VSS
DOl
D02
W
RAS
All
DQ4
D03
CAS
OE
A9
A10
AO
Al
A2
A3
AS
A7
A6
A5
A4
VCC
VSS
•
Enhanced Page Mode Operation for Faster
Memory Access
•
•
CAS-Before-RAS Refresh
VCC
VSS
VSS
VCC
Long Refresh Period
- 4096 Cycle Refresh in 64 ms
- 512 ms Max for Low-Power, Self-Refresh
Version (TMS426400P)
DOl
D02
W
RAS
All
D04
D03
CAS
OE
A9
D04
D03
CAS
OE
A9
DOl
DQ2
W
RAS
All
Al0
AO
Al
A2
A3
AS
A7
AS
A5
AS
A7
A6
A5
A4
A10
AO
Al
VCC
VSS
VSS
Vee
•
•
•
3-State Unlatched Output
All Inputs, Outputs, and Clocks are
TTL Compatible
Operating Free-Air Temperature Range
O°C to 70°C
description
The TMS426400 series are high-speed, lowvoltage 16 777 216-bit dynamic random-access
memories, organized as 4 194 304-bit words by
four bits each. The TMS426400P series are highspeed, low-voltage, low-power, self-refresh,
16 777 216-bit dynamic random-access
memories organized as 4 194 304-bit words of
four bits each. They employ state-of-the-art
EPIC'M (Enhanced Performance Implanted
CMOS) technology for high performance,
reliability, and low voltage at a low cost.
DGA PACKAGEt
(TOP VIEW)
DGB PACKAGEt
(TOP VIEW)
A4
A2
A3
t Packages shown are for pinout reference only.
PIN NOMENCLATURE
AD-All
CAS
DQ1-DQ4
OE
w
VCC
VSS
Address Inputs
Column-Address Strobe
Data In/Data Out
Output Enable
Row-Address Strobe
Write Enable
3.3-V Supply
Ground
These devices feature maximum RAS access times of 60 ns, 70 ns, 80 ns, and -1 00 ns. Maximum power
dissipation is as low as 180 mW operating, 0.36 mW standby and battery backup for an 80-ns device.
All inputs, outputs, and clocks, are compatible with Series 74 TTL. All addresses and data-in lines are latched
on-chip to simplify system design. Data out is unlatched to allow greater system flexibility.
EPIC is a trademark of Texas Instruments Incorporated.
PRODUCT PRE'IIEW _aUon ........ prod.eta In Iha formative or
dolan phi.. of dmloprnenL Chlllcl"IIUC dill Ind othtl
aptclflCllloMUI d..lgn gOiIa. Tmllnstrument, I'tIIf'YtI the right to
ching. or dlsconUnu, th... Pfoducta without notice.
Copyright © 1993, Texas Instruments Incorporated
TEXAS . "
INSfRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
4-409
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TMS426400, TMS426400P
4194 304-WORD BY 4-BIT
LOW-VOLTAGE DYNAMIC RANDOM-ACCESS MEMORIES
SMKS264-JANUARY 1993
The TMS426400 family is offered in a 300-mil 24/26-lead plastic surface mount SOJ package (OJ suffix), a
24/26-lead plastic small outline package (DGA suffix), and a 24/26-lead plastic small outline package, reverse
form (DGB suffix). These packages are characterized for operation from O°C to 70°C.
operation
enhanced page mode
Page mode operation allows effectively faster memory access by keeping the same row address and strobing
random column addresses onto the Chip. Thus, the time required to set up and strobe row addresses for the
same page is eliminated. The maximum number of columns that can be addressed is determined by tRAS, the
maximum RAS low width.
The column address buffers in this CMOS device are activated on the falling edge of RAS. They act as a
transparent or flow-through latch while CAS is high. The falling edge of CAS latches the addresses into these
buffers and also serves as an output enable.
This feature allows the TMS426400 family to operate at a higher data bandwidth than conventional page-mode
parts, since retrieval begins as soon as the column address is valid, rather than when CAS transitions low. The
performance improvement is referred to as eAhanced page mode. Valid column address may be presented
immediately after row address hold time has been satisfied, usually well in advance of the falling edge of CAS.
In this case, data is obtained after tCAC max (access time from CAS low), if tAA max (access time from column
address) and tRAS have been satisfied. In the event that the column address for the next cycle is valid at the
time CAS goes high, access time is determined by the later occurrence of tCPA or tCAC'
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address (AO-A11)
o
Twenty-two address bits are required to decode 1 of 4 194 304 storage cell locations. Twelve row-address bits
are set on inputs AO through A11 and latched onto the chip by the row address strobe, RAS. Ten column-address
bits are set on AO through A9. Column addresses A10 and A 11 are not used. Row address A 11 is required during
a normal access and during RAS-only refresh, as the device requires 4096 refresh cycles. All addresses must
be stable on or before the falling edges of RAS and CAS. RAS is similar to a chip enable in that it activates the
sense amplifiers as well as the row decoder. CAS is used as a chip select, activating the output buffer, as well
as latching the address bits into the column buffer.
-I
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write enable (W)
The read or write mode is selected through the write-enable input, W. A logic high on W selects the read mode
and a logic low selects the write mode. The write-enable terminal can be driven from standard TIL circuits
without a pullup resistor. The data input is disabled when the read mode is selected. When W goes low prior
to CAS (early write), data out will remain in the high-impedance state for the entire cycle, permitting a write
operation independent ofthe state of OE. This permits early write operation to be completed with OE grounded.
==
data-in/data-out (OQ1-0Q4)
Data is written during a write or read-modify-write cycle. Depending on the mode of operation, the falling of CAS
or W strobes data into the on-Chip data latch. In the early-write cycle, W is brought low prior to CAS and data
is strobed in by CAS with setup and hold times referenced to this Signal. In a delayed write or read-modify write
cycle, CAS will already be low, thus data will be strobed in by W with setup and hold times referenced to this
signal.
The three-state output buffer provides direct TIL compatibility (no pullup resistor required) with a fan-out of two
Series 74 TIL 10ads.The output is in the high-impedance (floating) state until CAS is brought low. In a read cycle
the outP!Jt becomes valid at the latest occurrence oftRAC, tAA, tCAC, or tCPA and remains valid while CAS is low.
CAS going high returns it to a high-impedance state. In a delayed-write or read-modify-write cycle, the output
does not change, but retains the state just read.
TEXAS
~
INSTRUMENTS
4-410
POST OFFICE BOX 1443' HOUSTON. TEXAS 77001
TMS426400, TMS426400P
4 194 304·WORD BY 4·BIT
LOW·VOLTAGE DYNAMIC RANDOM·ACCESS MEMORIES
SMKS26
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self-refresh
The self-refresh mode is entered by dropping CAS low prior to RAS going low. Then CAS and RAS are both
held low for a minimum of 100 ~s. The chip is then refreshed internally by an on-board oscillator. No external
address is required since the CBR counter is used to keep track of the address. To exit the self-refresh mode,
. both RAS and CAS are brought high to satisfy tCHS'
Upon exiting the self-refresh mode, a burst refresh (refresh a full set of row addresses) must be executed before
continuing with normal operation. This will ensure the DRAM is fully refreshed.
power up
To achieve proper device operation, an initial pause of 200 ~s followed by a minimum of eight initialization cycles
is required after full Vec level is achieved. These eight initialization cycles need to include at least one refresh
(RAS-only or CAS-before-RAS) cycle.
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443· HOUSTON, TEXAS 77001
4-411
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TMS426400, TMS426400P
4 194 304-WORD BY 4-BIT
LOW-VOLTAGE DYNAMIC RANDOM·ACCESS MEMORIES
SMKS264-JANUARY 1993
test mode
The test mode is initiated with a CAS-.before-RAS refresh cycle while simultaneously holding the W input low
(WCSR). The initiate cycle performs an internal refresh cycle while internally setting the device to perform
parallel read or write on subsequent cycles. While in test mode, any desired data sequence can be performed
on the device. The device exits test mode if a CAS-before-RAS (CSR) refresh cycle with W input held high, or
a RAS-only refresh (ROR) cycle is performed.
The part is configured as 1024K x 4 x 4 bit device in test mode, where each DO pin has a separate 4-bit
parallel read and write data bus where column addresses AO and A1 are ignored. During a read cycle, the four
internal bits are compared for each DO pin separately. If the four bits agree, the DO pin will go high; if not, the
DO pin will go low. All four bits are written to the state of their respective DO pin during a parallel write. Thus,
each DO pin is independent of the others, and any data pattern desired may be written on each DO pin. Test
time is thus reduced by a factor of 4 for this series.
1 4 - - -......
~.....
1 Entry Cycle
Exit Cycle -+oII1.1-----~~1
, . ' . - - - - - Test Mode Cycle
I
-----~~I
I
r.Normal
I
Mode
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t The states of 'ii, Data-in, and Address are defined by the type of cycle used during test mode.
Figure 1. Test Mode eyelet
:e
TEXAS ."
INSTRUMENTS
4-412
POST OFFICE BOX 1443' HOUSTON. TEXAS 77001
TMS426400, TMS426400P
4194 304·WORD BY 4·BIT
LOW·VOLTAGE DYNAMIC RANDOM·ACCESS MEMORIES
SMKS264-,JANUARY 1993
logic symbol t
RAM4096Kx4
AO
A1
A2
A3
A4
AS
A6
A7
A8
A9
A10
A11
10
20010/2100
11
12
13
16
17
0
A 4194303
18
19
20
23
9
6
20019/2109
20020
20021
J'-.-
RAS
~
5
I'-.
CAS
Vi
OE
OQ1
OQ2
OQ3
OQ4
25
4
24
2
h
~
I'-.
C20[ROW]
G23/[REFRESH ROW]
24[PWROWN]
C21 [COLUMN]
G24
&
23,210
G25
W
:;:
24,25EN
..,"
A,220
3
26
27
~
> 23C22
4- 'V 26
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A,Z26
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tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and lEe Publication 617-12.
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TEXAS ."
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTCN. TEXAS 71001
4-413
TMS426400, TMS426400P
4 194 304-WORD BY 4-BIT
LOW-VOLTAGE DYNAMIC RANDOM-ACCESS MEMO.RIES
SMKS264-JANUARY 1993
functional block diagram
I
T
AO
•
•
•
1
~
8
Column
Address
Bufferst
•
•
'----
Column Decode
2,
256KArray
256KArray
••
0
e
c
0
d
e
11
j
1 __
256KArray
11
256KArray
R
0
w
•
32<
Row
Address
Buffers
fr-t-
Sense Amplifiers
-I-
L
•
"'C
JJ
Timing and Control
/
Al
All
,,,,
.,
256KArray
•
••
.--±
>- 32
1 __
2f.256KArray
/
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t Column Address 10 and Column Address 11 are not used.
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TEXAS ."
INSTRUMENTS
4-414
I/O
Buffers
40f32
Selection
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
~I
~
In
Reg.
Out
Reg.
001 -004
TMS426400, TMS426400P
4194 304-WORD BY 4-BIT
LOW-VOLTAGE DYNAMIC RANDOM-ACCESS MEMORIES
SMKS264-JANUARY 1993
absolute maximum ratings over operating free-air temperature t
Voltage on any pin (see Note 1) .................................................... - 0.5 V to 4.6 V
Voltage range on Vee ........................................................... - 0.5 V to 4.6 V
Short circuit output current ................................................................ 50 rnA
Power dissipation .......................................................................... 1 W
Operating free-air temperature range .................................................. ooe to 70°C
Storage temperature range ....................................................... - 55°C to 125°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. This is a stress rating only, and
functional operation olthe device at these or any other conditions beyond those indicated in the "recommended operating conditions" section of
this specification Is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values in this data sheet are with respect to VSS.
recommended operating conditions
Vee
V,H
Supply voltage
High-level input voltage
VIL
Low-level input voltage (see Note 2)
TA
Operating free-air temperature
..
..
..
MIN
NOM
MAX
3.0
2
-0.3
3.3
3.6
Vee + 0.3
0.8
V
70
°e
0
NOTE 2: The algebraic convention, where the more negative (less pOSItive) limit IS deSignated as minimUm, IS used
voltage levels only.
In
UNIT
V
V
thiS data sheet for logiC
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TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
4-415
TMS426400, TMS426400P
'4194 304·WORD BY 4·BIT
LOW·VOLTAGE DYNAMIC RANDOM·ACCESS MEMORIES
SMKS264-JANUARY 1993
electrical characteristics over full ranges of recommended operating conditions (unless otherwise
noted)
PARAMETER
TMS426400-60
TMS426400P-60
TEST
CONDITIONS
MIN
VOH
High·level
output vo~age
10H =-2mA
VOL
Low-level
output voltage
IOL=2 rnA
VOH
Option
IOH = -100
VOL
Option
10L = + 100 J!A
II
Input current
(leakage) *
10
leel
"tI
ICC2
-I
"tI
Vee- O.2
UNIT
MAX
2,4
0,4
0,4
Vee- 0.2
MIN
V
0,4
Vee- 0.2
V
V
0,2
VI = 0 to 3.9 V,
All other pins = 0 V to Vee
±10
±10
±10
±10
J!A
Outputcurrent
(Ieakage)*
Vo=OtoYee,
Vee = 3,6 V, CAS high
±10
±10
±10
±10
J!A.
Read or write
cycle current
(see Notes 3
&5)
Minimum cycle,
Vee = 3,6V
70
60
50
40
rnA
1
1
1
1
rnA
'426400
300
300
300
300
'426400P
100
100
100
100
Standby
current
After 1
memory cycle,
RASand CAS
high, VIH =
VCC-O,2V
(LVCMOS)
I-'A
ICC3
Average
refresh
current
(RAS-only or
CBR) (see
Notes 3 & 5)t
RAS cycling, CAS high
(RAS-only): RAS low
after CAS low (CBR)
70
60
50
40
rnA
ICC4
Average page
current (see
Notes 4 & 5)t
RAS low, CAS cycling
60
50
40
35
rnA
ICC6*
Self-refresh
CAS < 0,2 V,
RAS <0,2V,
tRAS and tCAS > 1000 ms
100
100
100
100
I-'A
ICC7
Standby
current output
enable
(see Note 5) t
RAS=VIH,
CAS =VIL,
Data out = enabled
5
5
5
5
rnA
ICClO*
Battery
backup
(with CBR)
tRC = 1251-'s,
tRASs 11-'s, VCC -0,2 Vs
VIH s 3,9 V, a V s VIL s
0,2 V, Wand OE = VIH,
Address and Data stable
100
100
100
100
I-'A
:D
::e
MAX
0,2
After 1 memory cycle,
RAS and CAS high,
VIH = 2,0 V (LVTTL)
o
m
S
m
Vee- 0,2
MIN
2,4
2,4
0,4
J!A
MAX
TMS426400·10
TMS426400P·10
0,2
o
C
2,4
MIN
TMS426400·S0
TMS426400P-B0
0,2
:D
C
MAX
TMS426400·70
TMS426400P·70
,
,
t Minimum cycle, VCC = 3,6 V
* For TMS426400P only.
NOTES: 3, Measured with a maximum of one address change while RAS = VIL.
4, Measured with a maximum of one adddress change while CAS = VIH,
5, ICC max is specified with no load connected,
TEXAS . "
INSTRUMENTS
4-416
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
TMS426400, TMS426400P
4194 304·WORD BY 4·BIT
LOW·VOLTAGE DYNAMIC RANDOM·ACCESS MEMORIES
SMKS264-JANUARY 1993
capacitance over recommended ranges of supply voltage and operating free-air temperature,
f = 1 MHz (see Note 6)
PARAMETER
MIN
TYP
MAX
UNIT
Ci(A)
Input capacitance, address inputs
5
pF
Ci(RC)
Input capacitance, strobe inputs
7
pF
Ci(OE)
Input capacitance, output enable
7
pF
Ci(W)
Input capacitance, write-enable input
7
pF
Co
Output capacitance
7
pF
NOTE 6: VCC equal to 3.3 V
±
0.3 V and the bias on pins under test is 0 V.
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature
PARAMETER
TMS426400-60
TMS426400P-60
MIN
MAX
TMS426400-70
TMS426400P-70
MIN
MAX
TMS426400-BO
TMS426400P-S0
MIN
MAX
TMS426400-10
TMS426400P-10
MIN
UNIT
MAX
tM
Access time from column-address
30
35
40
45
ns
!cAC
Access time from CAS low
15
18
20
25
ns
tCPA
Access time from column precharge
35
40
45
50
ns
tRAC
Access time from RAS low
60
70
80
100
ns
25
ns
tOEA
Access time from OE low
tCLZ
CAS to output in low Z
15
tOH
Output disable start of CAS high
tOHO
Output disable time start of OE high
tOFF
Output disable time after CAS high
(see Note 7)
0
15
0
18
0
20
0
25
ns
tOEZ
Output disable time after OE high
(see Note 7)
0
15
0
18
0
20
0
25
ns
0
18
20
0
0
0
ns
3
3
3
3
ns
3
3
3
3
ns
NOTE 7: tOFF Is specified when the output is no longer driven.
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TEXAS
~
INSfRUMENTS
POST OFFICE BOX 1443· HOUSTON. TEXAS 77001
4-417
TMS426400, TMS426400P
4194 304-WORDBY 4-BIT
LOW-VOLTAGE DYNAMIC RANDOM-ACCESS MEMORIES
SMKS26
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TMS426400, TMS426400P
4 194 304-WORD BY 4-BIT
LOW-VOLTAGE DYNAMIC RANDOM-ACCESS MEMORIES
SMKS264-JANUARY 1993
PARAMETER MEASUREMENT INFORMATION
1.4V
~
Output Under Test
VCC
---±T
RL
= 500 0
R1 = 11780
Output Under Test - - . - - - .
CL = 100 pF
CL=100pF
(a) Load Circuit
(b) Alternate Load Circuit
Figure 2. Load Circuits for Timing Parameters
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NOTE A: Output may go from three·state to an invalid data state prior to the specified access time.
Figure 3. Read Cycle Timing
TEXAS
~
INsrRUMENTS
4·420
=3.3V
POST OFFICE BOX 1443· HOUSTON. TEXAS 77001
TMS426400, TMS426400P
4194 304·WORD BY 4·BIT
LOW·VOLTAGE DYNAMIC RANDOM·ACCESS MEMORIES
SMKS264-JANUARY 1993
PARAMETER MEASUREMENT INFORMATION
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Figure 4. Early Write Cycle Timing
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TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443· HOUSTON, TEXAS 77001
4-421
TMS426400, TMS426400P
4 194 304·WORD BY 4·BIT
LOW·VOLTAGE DYNAMIC RANDOM·ACCESS MEMORIES
SMKS260hJANUARY 1993
PARAMETER MEASUREMENT INFORMATION
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Figure 5. Write Cycle Timing
TEXAS ."
INSTRUMENTS
4·422
POST OFFICE BOX 1443· HOUSTON, TEXAS 77001
TMS426400, TMS426400P
4194 304·WORD BY 4·BIT
LOW·VOLTAGE DYNAMIC RANDOM·ACCESS MEMORIES
SMKS264--JANUARY 1993
PARAMETER MEASUREMENT INFORMATION
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NOTE A: Output may go from three-state to an invalid data state prior to the specified access time.
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Figure 6. Read-Write Cycle Timing
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TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
4-423
TMS426400, TMS426400P
4194 304-WORD BY 4-BIT
LOW-VOLTAGE DYNAMIC RANDOM-ACCESS MEMORIES
SMKS264-JANUARY 1993
PARAMETER MEASUREMENT INFORMATION
Column
A0-11
t
I
I
tRCS
I
~
I 1"111
~I----- tAA
I
(see Note B)
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m
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NOTES: A. Output may golrom three-state to an invalid data state prior to the specified access time.
B. Access time is tePA or tM dependent.
Figure 7. Enhanced Page-Mode Read Cycle Timing
TEXAS ~
INsrRUMENTS
4-424
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
~"¥-lLloLlLloLlLloLl~
----I--l-~
~
tRRH -.J
tRCH ------..I
VIL
TMS426400, TMS426400P
4 194 304-WORD BY 4-BIT
LOW-VOLTAGE DYNAMIC RANDOM-ACCESS MEMORIES
SMKS264-JANUARY 1993
PARAMETER MEASUREMENT INFORMATION
N
~
tRASP
I'"
: I;
.1 !I;
tCSH
1 14- tRAH
1 1
~1~---i.~I-1 tASR
+i
I
1
1
VIH
1
1
VIL
~ tRSH +------.l
~tCAL~
I
1
J/It---i------VIH
*- tcp ~
1 I
1 I
1
I
I
~I
j+-tCRP-+i
0' : N
tASC~~
::
.1
tpc
14
~I
tCPRH
1 14--- tRCO -----.
1 1
1 1
~tCAS+l 1
f
VIL
1.,.14--- tRAL -+----.1
1
.i-------'----.,.
Column
Row
AO-A11
.Vi'-I
I
tRP
~I
i
I
1.1
I.
I
.1
I I 1
~
tcwLI
1
~tRWL ~
twp
1
I
3:
w
W~o~*~~~I i!I I+--~~1~@~~
(see Note A)
I.
I~.
tos
tos
tOH ~
.1 I~ 1
1'1
1
...
tOH
I
(see Note A)
OQ1-0Q4~""------v-al-ld-o-a.l..ta-ln------"""~
1
tOEH -14.---.~i
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w
I
14-- tOEH --.J
.1
tOED ~
V~~ld
I
~
I
~o~X~~{2S
I
I
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IH
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NOTES: A. Referenced to CAS or 'N, whichever occurs last.
B. A read cycle or a read-write cycle can be intermixed with write cycles as long as read and read-write timing specifications are not
violated.
Figure 8. Enhanced Page-Mode Write Cycle Timing
TEXAS
~
IN5rRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
4-425
a:
c..
TMS426400, TMS426400P
4194304·WORD BY 4·BIT
LOW·VOLTAGE DYNAMIC RANDOM·ACCESS MEMORIES
SMKS264-JANUARY 1993
PARAMETER MEASUREMENT INFORMATION
tRP~
RAS
~
IY
1
I tl~====-t::C:S::H-::::=-=-=-=-~.:II:I...-=====t;tC:;;P:;R::H-=====:;.~I
I I
I I"
CAS
I:
rr
I"
tRCO
tpRWC
:orl " " " T " " - _ - J
II
o
C
C
o-t
"'C
II
m
m
S
=e
I 1
.1 1
1 ~~ tcp
VIH
:
VIL
I
1"11 I
.1
1:.-+1_ _ _ VIH
tCRP
I:
I
I
I
I
I
I
VIL
Column
~~~~
tAWO ----+J
I
III ,tRWO
.1
_
I I
W~::I
III I
R
'{
I
I
I
II i+--tcwo~
I
I"
:"-.
t"I..I - - - - - t SH -----1.~1
1
Column
Ao-A11
."
I
YI
iV-tCAS
i+i-tASR I I
1
I
~~tASC
I
II jOIIII-tCAH ---.I
tRAO
I
~
j+-
tRASP --------------~I T)..
.
1
l'1li
' - - _ _ _.J
,,~~~~~~~~;),Q.VIL
: itCWL~
I
I
tcpw - - . ! ~ tRWL ----.I
I I
j4III
L
!'~~X ~II~
~
~"__;II_..r;,~~~~~~~VVIIHL
~ ~
twP
I ~I_-IIiC><
.. ~<:>I
1
. I II. I
I 1
tCPA ~
1 ..
.1 tOEH
I
..... ~ tRCS
I ""-~.t-I tOH
I
I
I
I.. ! .1 tAA
I:
I
I
I
i+-- tRAC I~ _ 1_; tos I
I
Valid Out
I
~
~I ~
I
I
(see Note A)
I
I~'
-ltCAC L I
~I
VIHNOH
OQ1-0Q4,-------'<11
I
c
V~~ld:
I
V~~d ~I- - - - - I
VIUVOL
tCLZ ----.I I...-f : Valid Out I
I
I
~I j4III- toEZ l41li
I"
~tOEO
I
J+- tOEA -+I II
14------~t-tOE~;._1------.i:I~~~~~~
-J/iw
a:
a.
IU
:J
Figure 13. Hidden Refresh Cycle (Read)
C
o
a:
a.
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443· HOUSTON, TEXAS 77001
4-429
TMS426400, TMS426400P
4194 304-WORD BY 4-BIT
LOW-VOLTAGE DYNAMIC RANDOM-ACCESS MEMORIES
SMKS264-JANUARY 1993
PARAMETER MEASUREMENT INFORMATION
"tJ
:c
o
c
c:
o
-t
"tJ
:c
m
S
m
=E
Figure 14. Hidden Refresh Cycle (Write)
TEXAS ~
INsrRUMENTS
4·430
POST OFFICE BOX 1443· HOUSTON, TEXAS 77001
TMS426400, TMS426400P
4194 304·WORD BY 4·BIT
LOW·VOLTAGE DYNAMIC RANDOM·ACCESS MEMORIES
SMKS264-JANUARY 1993
PARAMETER MEASUREMENT INFORMATION
Figure 15. Test Mode Entry Cycle
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443· HOUSTON, TEXAS 77001
4·431
TMS426400, TMS426400P
4194 304·WORD BY 4·BIT
LOW·VOLTAGE DYNAMICRANDOM·ACCESS MEMORIES
SMKS264-JANUARY 1993
PARAMETER MEASUREMENT INFORMATION
"'C
:rJ
o
C
C
o
DQ1-DQ4
~W------------HI-Z ----------- :::
-I
"'C
:rJ
m
<
-
m
=E
Figure 16. Test Mode Exit Cycle (CAS-before-RAS Refresh Cycle)
device symbolization
TI
)
T~
TMS426400
Speed (-60, -70, -80, -10)
Power/Refresh Code (Blank, P)
!¥
Package Code
WAPT~
Lot Traceability Code
I
Month Code
Assembly Site Code
Ole Revision Code
Wafer Fab Code
TEXAS
~
INSTRUMENTS
4-432
POST OFFICE BOX 1443· HOUSTON, TEXAS 77001
TMS427400, TMS427400P
4194 304-WORD BY 4-BIT
LOW-VOLTAGE DYNAMIC RANDOM-ACCESS MEMORIES
SMKS274-JANUARY 1993
•
•
•
•
OJ PACKAGEt
(TOP VIEW)
Organization ••• 4 194 304 x 4
Single 3.3-V Power Supply (± 0.3 V
Tolerance)
Low Power Dissipation (TMS427400P)
- 100 IlA CMOS Standby
- 100 IlA Self-Refresh
- 100 IlA Extended Refresh Battery Backup
Vss
D04
D03
W
CAS
RAS
OE
NC
A9
Performance Ranges:
'427400/P-60
'427400/P-70
'427400/P-80
'427400/P-l0
ACCESS ACCESS ACCESS READ
TIME
TIME
TIME OR WRITE
CYCLE
tAA
tRAC
tcAC
(MAX)
(MIN)
(MAX)
(MAX)
15 ns
30 ns
110 ns
60 ns
70 ns
18 ns
35 ns
130 ns
80ns
20 ns
40 ns
150 ns
100 ns
25 ns
45 ns
180 ns
•
CAS-Before-RAS Refresh
Vee
•
Long Refresh Period
- 2048 Cycle Refresh in 32 ms
- 256 ms Max for Low-Power, Self-Refresh
Version (TMS427400P)
3-State Unlatched Output
•
All Inputs, Outputs, and Clocks are
TTL Compatible
A7
Al
A6
A2
A5
A4
Vss
DGA PACKAGEt
(TOP VIEW)
DGB PACKAGEt
(TOP VIEW)
Vss
Vss
Vee
DOl
D04
D02
D03
D04
D03
DOl
D02
CAS
CAS
W
W
OE
RAS
A9
NC
C.
I0
Al0
AB
AB
Al0
AO
Al
A7
A7
AO
A6
A6
Al
A2
A5
A5
A2
A3
A4
A4
A3
Vee
Vss
Vss
Vee
t Packages shown are for pinout reference only.
PIN NOMENCLATURE
AO-All
DQ1-DQ4
OE
RAS
W
Vee
Vss
Address Inputs
Column-Address Strobe
Data In/Data Out
Output Enable
Row-Address Strobe
Write Enable
3.3-V Supply
Ground
All inputs, outputs, and clocks, are compatible with Series 74 TTL. All addresses and data-in lines are latched
on-chip to simplify system design. Data out is unlatched to allow greater system flexibility.
EPIC is a trademark of Texas Instruments Incorporated.
_lop......
a:
OE
A9
These devices feature maximum RAS access times of 60 ns, 70 ns, 80 ns, and 100 ns. Maximum power
dissipation is as low as 288 mW operating, 0.36 mW standby and battery backup for an 80-ns device.
:=
:>
W
NC
The TMS427400 series are high-speed, lowvoltage 16 777 216-bit dynamic random-access
memories, organized as 4 194 304-bit words by
four bits each. The TMS427400P series are highspeed, low-voltage, low-power, self-refresh,
16 777 216-bit dynamiC random-access
memories organized as 4 194 304-bit words of
four bits each. They employ state-of-the-art
EPIC'M (Enhanced Performance Implanted
CMOS) technology for high performance,
reliability, and low voltage at a low cost.
PRODUCT PREVIEW _ a n ........ productlln .... _
or
phi.. II
ChlractorIIUo dall ,041 oIhor
caUona In lillian QOIIL Tuulnstrumentl rllIIVM the rtght to
ngl or dIIcofttinuIlh. . producta wttboul nonce.
~
W
RAS
Operating Free-Air Temperature Range
O°C to 70·C
description
A8
AO
Vee
Enhanced Page Mode Operation for Faster
Memory Access
•
Al0
A3
•
•
Vee
DOl
D02
TEXAS
~
Copyright © 1993, Texas Instruments Incorporated
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
4-433
:l
C
0
a:
C.
TMS427400, TMS427400P
4194 304-WORD BY 4-BIT
LOW-VOLTAGE DYNAMIC RANDOM-ACCESS MEMORIES
SMKS274-JANUARY 1993
The TMS427400 family is offered in a 300-mil 24/26-lead plastic surface mount SOJ package (OJ suffix), a
24/26-lead plastic small outline package (DGA suffix), and a 24/26-lead plastic small outline package, reverse
form (DGS suffix). These packages are characterized for operation from O°C to 70°C.
operation
enhanced page mode
Page mode operation allows effectively faster memory access by keeping the same row address and strobing
random column addresses onto the chip. Thus, the time required to set up and strobe row addresses for the
same page is eliminated. The maximum number of columns that can be addressed is determined by tRAS, the
maximum RAS low width.
The column address buffers in this CMOS device are activated on the falling edge of RAS. They act as a
transparent or flow-through latch while CAS is high. The falling edge of CAS latches the addresses into these
buffers and also serves as an output enable.
This feature allows the TMS427400 family to operate at a higher data bandwidth than conventional page-mode
parts, since retrieval begins as soon as the column address is valid, rather than when CAS transitions low. The
performance improvement is referred to as enhanced page mode. Valid column address may be presented
immediately after row address hold time has been satisfied, usually well in advance of the falling edge of CAS.
In this case, data is obtained aftertcAc max (access time from CAS low), iftAA max (access time from column
address) and tRAS have been satisfied. In the event that the column address for the next cycle is valid at the
time CAS goes high, access time is determined by the later occurrence of tCPA or tCAC'
-a
lJ
oC
c:
address (AO-A11)
o-I
Twenty-two address bits are required to decode 1 of 4 194 304 storage cell locations. Eleven row-address bits
are set on inputs AO through A10 and latched onto the chip by the row address strobe, RAS. Eleven
column-address bits are set on AO through A 10. All addresses must be stable on or before the falling edges of
RAS and CAS. RAS is similar to a chip enable in that it activates the sense amplifiers as well as the row decoder.
CAS is used as a chip select, activating the output buffer, as well as latching the address bits into the column
buffer.
-a
lJ
m
m
<
-
write enable (W)
The read or write mode is selected through the write-enable input, W. A logic high on W selects the read mode
and a logic low selects the write mode. The write-enable terminal can be driven from standard TTL circuits
without a pull up resistor. The data input is disabled when the read mode is selected. When W goes low prior
to CAS (early write), data out will remain in the high-impedance state for the entire cycle, permitting a write
operation independent of the state of OE. This permits early write operation to be completed with OE grounded.
~
data-in/data-out (DQ1-DQ4)
Data is written during a write or read-modify-write cycle. Depending on the mode of operation, the falling of CAS
or W strobes data into the on-chip data latch. In the early-write cycle, W is brought low prior to CAS and data
is strobed in by CAS with setup and hold times referenced to this signal. In a delayed write or read-modify write
cycle, CAS will already be low, thus data will be strobed in by W with setup and hold times referenced to this.
signal.
The three-state output buffer provides direct TTL compatibility (no pullup resistor required) with a fan-out of two
Series 74 TTL loads. The output is in the high-impedance (floating) state until CAS is brought low. In a read cycle
the output becomes valid at the latest occurrence of tRAC, tAA, tCAC, or tCPA and remains valid while CAS is low.
CAS going high returns it to a high-impedance state. In a delayed-write or read-modify-write cycle, the output
does not change, but retains the state just read.
TEXAS ~
INSTRUMENTS
4-434
POST OFFICE BOX 1443' HOUSTON. TEXAS 77001
TMS427400, TMS427400P
4194 304-WORD BY 4-BIT
LOW-VOLTAGE DYNAMIC RANDOM-ACCESS MEMORIES
SMKS274-JANUARY 1993
output enable (OE)
OE controls the impedance of the output buffers. When OE is high, the buffers will remain in the high-impedance
state. Bringing OE low during a normal cycle will activate the output buffers, putting them in the lowcimpedance
state. It is necessary for both RAS and CAS to be brought low for the output buffers to go into the low-impedance
state. Once in the low-impedance state, they will remain for the low-impedance state until either OE or CAS is
brought high.
refresh
A refresh operation must be performed at least once every 32 ms (256 ms for TMS427 400P) to retain data. This
can be achieved by strobing each of the 2048 rows (AO-A 10). A normal read or write cycle will refresh all bits
in each row that is selected. A RAS-only operation can be used by holding CAS at a high (inactive) level, thus
conserving power since the output buffer remains in the high-impedance state. Externally generated addresses
must be used for a RAS-only refresh. Hidden refresh may be performed by holding CAS at VIL after a read
operation and cycling RAS after the specified precharge period, similar to a RAS-only refresh cycle except with
CAS held low. Valid data is maintained at the output throughout the hidden refresh cycle. An internal refresh
address provides the refresh address during hidden refresh.
CAS-before-RAS refresh
CAS-before-RAS refresh is utilized by bringing CAS low earlier than RAS (see parameter tCSR) and holding it
low after RAS falls (see parameter tCHR). For successive CAS-before-RAS refresh cycles, CAS can remain low
while cycling RAS. For this mode of refresh, the external addresses are ignored and the refresh address is
generated internally.
A low-power battery-backup refresh mode that requires less than 100 ~ refresh current is available on the
TMS427400P. Data integrity is maintained using CAS-before-RAS refresh with a period of 125 J.lS while holding
RAS low for less than 1 J.ls. To minimize current consumption, all input levels need to be at CMOS levels
(VIL:S 0.2 V, VIH '" VCC - 0.2 V).
self-refresh
The self-refresh mode is entered by dropping CAS low prior to RAS going low. Then CAS and RAS are both
held low for a minimum of 100 J.ls. The chip is then refreshed internally by an on-board oscillator. No external
address is required since the CBR counter is used to keep track of the address. To exit the self-refresh mode,
both RAS and CAS are brought high to satisfy tCHS.
Upon exiting the self-refresh mode, a burst refresh (refresh a full set of row addresses) must be executed before
continuing with normal operation. This will ensure the DRAM is fully refreshed.
power up
To achieve proper device operation, an initial pause of 200 J.lS followed by a minimum of eight initialization cycles
is required after full V CC level is achieved. These eight initialization cycles need to include at least one refresh
(RAS-only or CAS-before-RAS) cycle.
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
4-435
~
W
:;
w
a:
c..
I-
o
::J
C
o
a:
c..
TMS427400,TMS427400P
4 194 304-WORD BY 4-BIT
LOW-VOLTAGE DYNAMIC RANDOM-ACCESS MEMORIES
SMKS274-JANUARY 1993
test mode
The test mode is initiated with a CAS-before-RAS refresh cycle while simultaneously holding the W input loW
(WCBR). The initiate cycle performs an internal refresh cycle while internally setting the device to perform
parallel read or write on subsequent cycles. While in test mode, any desired data sequence can be performed
on the device. The device exits test mode if a CAS-before-RAS (CBR) refresh cycle with W input held high, or
a RAS-only refresh (ROR) cycle is performed.
The part is configured as 1M x 4 x 4 bit device in test mode, where each DO pin has a separate 4-bit parallel
read and write data bus where column addresses AO and A1 are ignored. During a read cycle, the four internal
bits are compared for each DO pin separately. If the four bits agree, the DO pin will go high; if not, the DO pin
will go low. All four bits are written to the state of their respective DO pin during a parallel write. Thus, each DO
pin is independent of the others, and any data pattern desired may be written on each DO pin. Test time is thus
reduced by a factor of 4 for this series.
14---~~+-1
ExIt Cycle --l
w
24,25EN
G25
~.
r
A,220
'i7 26
a::
0-
A,Z26
....
O.
27
:::>
c
o
tThis symbol is in accordance with ANSI/IEEE Std 91 ·1984 and lEG Publication 617·12.
a::
0-
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
4·437
TMS427400, TMS427400P
4194 304-WORD BY 4-BIT
LOW-VOLTAGE DYNAMIC RANDOM-ACCESS MEMORIES
SMKS274-JANUARY 1993
functional block diagram
I
T
AO
•
·•
A10
Column
Address
Buffers
•
•
•
'--
-
g
Column Decode
2
Sense Amplifiers
---I-
256KArray
32<
•
••
/
-
~
256KArray
R
0
w
!t
256KArray
••
•
D
e
c
0
d
10
1--
o
t
1
256KArray
Row
Address
Buffers
t
9
L
:JJ
t
Timing and Control
/
A1
."
t
>32
2--
1v
~
~
In
Reg.
Out
Reg.
e
256KArray
256KArray
10
/
C
C
o
-I
."
:JJ
m
m
:$
:e
TEXAS
~
IN5rRUMENTS
4-438
I/O
Buffers
40f32
Selection
POST OFFICE BOX 1443· HOUSTON, TEXAS 77001
DQ1 -DQ4
TMS427400, TMS427400P
4 194 304·WORD BY 4·BIT
LOW·VOLTAGE DYNAMIC RANDOM·ACCESS MEMORIES
SMKS274--JANUARY 1993
absolute maximum ratings over operating free-air temperature t
Voltage on any pin (see Note 1) .................................................... - 0.5 V to 4.6 V
Voltage range on Vee ........................................................... - 0.5 V to 4.6 V
Short circuit output current ................................................................ 50 rnA
Power dissipation .......................................................................... 1 W
Operating free-air temperature range .................................................. DoC to 70°C
Storage temperature range ....................................................... - 55°C to 125°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. This is a stress rating only, and
functional operation ofthe device at these or any other conditions beyond those indicated in the "recommended operating conditions" section of
this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values in this data sheet are with respect to VSS.
recommended operating conditions
Vee
VIH
VIL
TA
Supply voltage
High-level input voltage
Low-level input voltage (see Note 2)
Operating free-air temperature
..
..
..
MIN
NOM
MAX
3.0
2
-0.3
3.3
3.6
0
UNIT
Vee + 0.3
0.8
V
V
V
70
·e
NOTE 2: The algebraic convention, where the more negative (less pOSItive) limit IS deSignated as minimUm, IS used In this data sheet for logiC
voltage levels only.
3:
w
:>
w
a:
c..
I-
o
::J
C
o
a:
c..
TEXAS ~
INsrRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
4-439
TMS427400, TMS427400P
4194 304·WORDBY 4·BIT
LOW·VOLTAGE DYNAMIC RANDOM·ACCESS MEMORIES
SMKS274-JANUARY 1993
electrical characteristics overfull ranges of recommended operating conditions (unless otherwise
noted)
PARAMETER
TMS427400-60
TMS427400P-60
TEST
CONDITIONS
MIN
VOH
High-level
output voltage
10H =-2mA
VOL
Low-level
output voltage
10L = 2 mA
VOH
Option
10H =-100~
VOL
Option
10L = + 100 ~
II
Input current
(Ieakage)*
VI = 0 to 3.9 V,
All other pins = 0 V to VCC
10
Output current
(Ieakage)*
VO=OtoVc~
ICCl
Read or write
cycle current
(see Notes 3
&5)
.
"C
o
C
C
ICC2
o
Standby
current
-I
"C
MAX
0.4
MAX
TMS427400-10
TMS427400P-l0
MIN
0.4
UNIT
MAX
2.4
VCC-O.2
VCC-0.2
VCC-0.2
MIN
2.4
2.4
0.4
V
0.4
VCC-0.2
V
V
0.2
0.2
0.2
0.2
±10
±10
±10
±10
~
:010
±10
±10
±10
I'A
100
90
80
70
mA
1
1
1
1
mA
'427400
300
300
300
300
'427400P
100
100
100
100
VCC = 3.6 V, CAS high
Minimum cycle,
VCC = 3.6V
After 1
memory cycle,
RAS and CAS
high, VIH =
VCC-0.2V
(LVCMOS)
MIN
TMS427400-80
TMS427400P-80
~
ICC3
Average
refresh
current
(RAS-only or
CBR) (see
Notes 3 & 5)t
RAS cycling, CAS high
(RAS-only); RAS low
after CAS low (CBR)
100
90
80
70
mA
ICC4
Average page
current (see
Notes 4 & 5)t
RAS low, CAS cycling
60
50
40
35
mA
ICC6*
Self-refresh
100
100
100
100
~
ICC7
Standby
current output
enable
(see Note 5) t
RAS=VIH,
CAS=VIL,
Data out ='enabled
5
5
5
5
rnA
ICC10*
Battery
backup
(withCBR)
tRC = 125 !!S,
tRASs 11'S, VCC - 0.2 Vs
VIH s 3.9 V, a V s VIL S
0.2 V, Wand OE = VIH,
Address and Data stable
100
100
100
100
~
::0
~
m
2.4
After 1 memory cycle,
RAS and CAS high,
VIH = 2.0 V (LVTTL)
::0
MAX
TMS427400-70
TMS427400P-70
=E
..
CAS <0.2V,
RAS < 0.2 V,
. tRAS and tCAS > 1000 ms
t MInimum cycle, VCC = 3.6 V.
* For TMS427400P only.
NOTES: 3. Measured with a maximum of one address change while RAS = VIL.
4. Measured with a maximum of one adddress change while CAS = VIH.
5. ICC max is specified with no load connected.
TEXAS ",
INSTRUMENTS
4-440
POST OFFICE BOX 1443· HOUSTON. TEXAS 77001
TMS427400, TMS427400P
4194 304-WORD BY 4-BIT
LOW-VOLTAGE DYNAMIC RANDOM-ACCESS MEMORIES
SMKS274--JANUARY 1993
capacitance over recommended ranges of supply voltage and operating free-air temperature,
f = 1 MHz (see Note 6)
PARAMETER
MIN
TVP
MAX
UNIT
Ci(A)
Input capacitance, address inputs
5
pF
Ci(RC)
Input capacitance, strobe inputs
7
pF
Ci(OE)
Input capacitance, output enable
7
pF
Ci(W)
Input capacitance, write-enable input
7
pF
Co
Output capacitance
7
pF
NOTE 6: VCC equal to 3.3 V ± 0.3 V and the bias on pins under test is 0 V.
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature
PARAMETER
TMS427400-60
TMS427400P-60
MIN
MAX
TMS427400·70
TMS427400P·70
MIN
MAX
TMS427400-80
TMS427400P-80
MIN
MAX
TMS427400·10
TMS427400P·10
MIN
UNIT
MAX
tM
Access time from column-address
30
35
40
45
ns
teAC
Access time from CAS low
15
18
20
25
ns
tCPA
Access time from column precharge
35
40
45
50
ns
tRAC
Access time from RAS low
60
70
80
100
ns
tOEA
Access time from OE low
25
ns
teLZ
CAS to output in low Z
0
0
0'
0
ns
tOH
Output disable start of CAS high
3
3
3
3
ns
toHO
Output disable time start of OE high
3
3
3
3
ns
tOFF
Output disable time after CAS high
(see Note 7)
0
tOEZ
Output disable time after OE high
(see Note 7)
0
15
15
18
0
18
20
0
20
0
25
ns
;:
W
:;
w
a:
c.
t-
O
15
0
18
0
20
0
25
ns
~
C
NOTE 7: tOFF is specified when the output is no longer driven.
oa:
c.
TEXAS
~
INSIRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
4-441
TMS427400, TMS427400P
4 194 304·WORD BY 4·BIT
LOW·VOLTAGE DYNAMIC RANDOM·ACCESS MEMORIES
SMKS274-JANUARY 1993
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
TMS427400-60
TMS427400P-60
MIN
MAX
TMS427400-70
TMS427400P-70
MIN
MAX
TMS427400-80
TMS427400P-BO
MIN
MAX
TMS427400-10
TMS427400P-10
MIN
UNIT
MAX
tRC
Random read or write cycle (see Note 8)
110
130
150
180
ns
tRWC
Read-write cycle time
155
181
205
245
ns
tpc
Page-mode read or write cycle time
(see Note 9)
40
45
50
55
ns
tpRWC
Page-mode read-write cycle time
85
96
105
120
ns
tRASP
Page-mode pulse duration, RAS low
(see Note 10)
60
100 000
70
100 000
80
100 000
100
100 000
ns
tRAS
Non-page-mode pulse duration, RAS low
(see Note 10)
60
10 000
70
10 000
80
10000
100
10000
ns
tRASS
Self-refresh, RAS low time
100
lAS
teAS
Pulse duration, CAS low (see Note 11)
15
10 000
18
10 000
20
10 000
25
10 000
ns
tcp
Pulse duration, CAS high
10
10
10
10
ns
tRP
Pulse duration, RAS high (precharge)
40
50
60
70
ns
tRPS
RAS precharge after self-refresh
110
130
150
180
ns
twp
Write pulse duration
15
15
15
15
ns
C
tASC
Column-address setup time
before CAS low
a
a
a
a
ns
o
tASR
Row-address setup time before RAS low
0
0
Data setup time (see Note 12)
tRCS
Read setup before CAS low
a
a
a
a
a
a
a
a
a
a
ns
tDS
tCWL
W-Iow setup time before· CAS high
15
18
20
25
ns
tRWL
W-Iow setup time before RAS high
15
18
20
25
ns
twcs
W-Iow setup time before CAS low
(Early write operation only)
0
0
0
a
ns
twSR
W-high setup time (CAS-before-RAS
refresh only)
10
10
10
10
ns
"tI
:IJ
o
c:
-I
"tI
:IJ
m
m
<
-
:e
100
100
100
ns
ns
twTs
W-Iow setup time (test-mode only)
10
10
10
10
ns
tCAH
Column-address hold time after CAS low
10
15
15
15
ns
tDH
Data hold time (see Note 12)
10
15
15
15
ns
tRAH
Row-address hold time after RAS low
10
10
10
10
ns
tRCH
Read hold time after CAS high
(see Note 13)
0
0
0
a
ns
tRRH
Read hold time after RAS high
(see Note 13)
5
5
5
5
ns
Conllnued next page.
NOTES: 8. All cycle times assume IT = 5 ns.
9. To assure tpc min, tASC should be greater than or equal to tep.
10. In a read-write cycle, tRWD and tRWL must be observed.
11. In a read-write cycle, tCWD and tCWL must be observed.
12. Referenced to the later of CAS or Win write operations.
13. E~her tRRH or tRCH must be satisfied for a read cycle.
TEXAS ~
INSTRUMENTS
4-442
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
TMS427400, TMS427400P
4194 304-WORD BY 4-BIT
LOW-VOLTAGE DYNAMIC RANDOM-ACCESS MEMORIES
SMKS274-JANUARY 1993
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (concluded)
TMS427400-60
TMS427400P-60
MIN
MAX
TMS427400-70
TMS427400P-70
MIN
MAX
TMS427400-80
TMS427400P-80
MIN
MAX
TMS427400-10
TMS427400P-1O
MIN
UNIT
MAX
twCH
Write hold time after CAS low
(Early write operation only)
15
15
15
15
ns
twHR
W-high hold time (CAS-before-RAS
refresh only)
10
10
10
10
ns
twTH
W-Iow hold time (test mode only)
10
10
10
10
ns
tAWD
Delay time, column address to W low
(Read-write operation only)
55
63
70
80
ns
leHR
Delay time, RAS low to CAS high
(CAS-before-RAS refresh only)
20
20
20
20
ns
leRP
Delay time, CAS high to RASlow
5
5
5
5
ns
tCSH
Delay time, RAS low to CAS high
60
70
80
100
ns
tCSR
Delay time, CAS low to RAS low
(CAS-before-RAS refresh only)
10
10
10
10
ns
tCHS
CAS low hold time after RAS high
(self-refresh)
-50
-50
-50
-50
ns
tCWD
Delay time, CAS low to W low
(Read-write operation only)
40
46
50
60
ns
tOEH
OE command hold time
15
18
20
25
ns
3=
->w
w
a:
tOED
OE to data delay
15
18
20
25
ns
tROH
RAS hold time referenced to OE
10
10
10
10
ns
tRAD
Delay time, RAS low to column-address
(see Note 14)
15
tRAl
Delay time, column-address to RAS high
30
35
40
45
ns
::J
tCAl
Delay time, column-address to CAS high
30
35
40
45
ns
tRCD
Delay time, RAS low to CAS low
(see Note 14)
20
o
tRPC
Delay time, RAS high to CAS low
0
0
0
0
ns
tRSH
Delay time, CAS low to RAS high
15
18
20
25
ns
tRWD
Delay time, RAS low to W low
(Read-write operation only)
85
98
110
135
ns
30
45
15
20
35
52
15
20
40
60
15
20
55
75
ns
ns
tCPRH
RAS hold time from CAS precharge
35
40
45
50
ns
tcpw
Delay time, W from CAS precharge
60
68
75
85
ns
!TM
Access time from add ress (test mode)
35
40
45
50
ns
!TCPA
Access time from column precharge
(test mode)
40
45
50
55
ns
!TRAC
Access time from RAS
(test mode)
65
75
85
105
ns
tREF
Refresh time interval rrMS427400)
tREF
Refresh time internal rrMS427400P)
!T
Transition time
3
32
32
32
32
ms
256
256
256
256
ms
30
ns
30
3
30
3
30
3
NOTE 14: The maximum value is specified only to assure access time.
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
4-443
0.
tO
C
a:
0.
TMS427400, TMS427400P
4 194 304-WORD BY 4-BIT
LOW-VOLTAGE DYNAMIC RANDOM-ACCESS MEMORIES
SMKS274-JANUARY 1993
PARAMETER MEASUREMENT INFORMATION
-1
VCC = 3.3V
1.4V
Output Under Test
CL=100pF
RL =500Q
R1
Output Under Test
,
I
11780
-----<.----.
CL=100pF
(b) Alternate Load Circuit
(a) Load Circuit
Figure 2. Load Circuits for Timing Parameters
"tJ
l:I
o
C
C
o
-I
"tJ
l:I
m
:$
m
:e
NOTE A: Output may go from three-state to an invalid data state prior to the specified access time.
Figure 3_ Read Cycle Timing
TEXAS
~
INSTRUMENTS
4-444
=
POST OFFICE BOX 1443· HOUSTON, TEXAS 77001
TMS427400, TMS427400P
A 1QA 'lnA_tAlnDn DV A_DIT
""T
I""
vv"'- ••
V"I# ....
.,.-., • •
LOW·VOLTAGE DYNAMIC RANDOM·ACCESS MEMORIES
SMKS274-JANUARY 1993
PARAMETER MEASUREMENT INFORMATION
~
W
DQ1-DQ4~,--_ _ _ _v_a_lId_D_a_ta_ _ _ _.J~X~Z~VIH
-
VIL
~
a::
Q.
IU
::J
C
o
a::
Figure 4. Early Write Cycle Timing
Q.
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
4·445
TMS427400, TMS427400P
4194 304·WORD BY 4·BIT
LOW·VOLTAGE DYNAMIC RANDOM·ACCESS MEMORIES
SMKS274-JANUARY 1993
, PARAMETER MEASUREMENT INFORMATION
"'D
:II
o
C
C
o
"""i
"'D
:II
m
m
:$
:e
Figure 5. Write Cycle Timing
TEXAS ~
INSTRUMENTS
4-446
POST OFFICE BOX 1443· HOUSTON, TEXAS 77001
TMS427400, TMS427400P
4194 304·WORD BY 4·BIT
LOW·VOLTAGE DYNAMIC RANDOM·ACCESS MEMORIES
SMKS274-JANUARY 1993
PARAMETER MEASUREMENT INFORMATION
3:
w
iiia:
D.
I-
o
:::l
C
NOTE A: Output may go from three-state to an invalid data state prior to the specified access time.
oa:
Figure 6. Read-Write Cycle Timing
D.
1ExAs
~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
4-447
TMS427400, TMS427400P
4194 304·WORD BY 4·BIT
LOW·VOLTAGE DYNAMIC RANDOM·ACCESS MEMORIES
SMKS274-JANUARY 1993
PARAMETER MEASUREMENT INFORMATION
A0-10
- XJQj
OH
Valid
~
Out
f4~ tOHO
tOHO'"
~ ~tOE~
1 tOEZ'. ~
I
'OEmm~okx~~~tOEA~ ~
tOEA~
I VOH
~
T
~
VOL
.,
~VIH
VIL
NOTES: A. Output may go from three-state to an invalid data state prior to the specified access time.
B. Access time is tCPA or tAA dependent.
Figure 7. Enhanced Page-Mode Read Cycle Timing
:e
TEXAS
~
INSfRUMENTS
4-448
POST OFFICE BOX 1443· HOUSTON, TEXAS n001
TMS427400, TMS427400P
4194 304-WORD BY 4-BIT
LOW-VOLTAGE DYNAMIC RANDOM-ACCESS MEMORIES
SMKS274-JANUARY 1993
PARAMETER MEASUREMENT INFORMATION
::w
:>
w
a:
c..
I-
o
::l
C
NOTES: A. Referenced to CAS or W. whichever occurs last.
B. A read cycle or a read-write cycle can be intermixed with write cycles as long as read and read-write timing specifications are not
violated.
Figure 8. Enhanced Page-Mode Write Cycle Timing
TEXAS ~
INSTRUMENlS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
4-449
o
a:
c..
TMS427400, TMS427400P
4 194 304·WORD BY 4·BIT
LOW·VOLTAGE DYNAMIC RANDOM·ACCESS MEMORIES
SMKS274-JANUARY 1993
PARAMETER MEASUREMENT INFORMATION
"C
:x:J
o
C
c:
o
-I
"C
:x:J
m
S
m
=E
NOTES: A. Output may go from three-state to an invalid data state prior to the specified access time.
B. A read or write cycle can be intermixed with read-write cycles as long as the read and write timing specifications are not violated.
Figure 9. Enhanced Page-Mode Read-Write Cycle Timing
TEXAS~
INSIRUMENTS
4-450
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
TMS427400, TMS427400P
4194 304·WORD BY 4·BIT
LOW·VOLTAGE DYNAMIC RANDOM·ACCESS MEMORIES
SMKS274-JANUARY 1993
PARAMETER MEASUREMENT INFORMATION
OQ1-0Q4
i[~~VIH ~
VIL :;
OE""""'~"""""""'''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''~~1''''''''''t~£'''''''''r~''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''~VIH ~
VIL
a.
I-
Figure 10. RAS-Only Refresh Timing
o
::J
C
o
a:
a.
TEXAS ~
INsrRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
4·451
TMS427400, TMS427400P
4 194 304·WORD BY 4·BIT
LOW·VOLTAGE DYNAMIC RANDOM·ACCESS MEMORIES
SMKS274-JANUARY 1993
PARAMETER MEASUREMENT INFORMATION
.,
~1~~-----------------tAC------------------~
~ tAP ~ 1~~-----------tAAS ----~______-+I
I
AAS
,IN
A,
>.1
tAPC -"-PI
CAS
·1 '
1 I
1 1
VIH
JI
I~------------------------~
~tCSA~ 1
~
1 I~~------- tCHA
VIL
.1
\{~I- _____~_+14~1---tT----------------~~
,
twSA
11'11
VIH
~
lo.-----.r·1 twHA
•
w~
V
IH
VIL
A~A10~~*~~*~~VIH
VIL
"tJ
OE~2*2RH~V'H
lJ
o
VIL
C
C
o
VIH
OQ1-0Q4 - - - - - - - - - - - - - - - - - - - - - - - - - - - - HI-Z - - - - - - - - - - - - - -
-I
Figure 11. Automatic (CAS-Sefore-RAS) Refresh Cycle Timing
"tJ
lJ
!+--- tAP ~ ~I~----------_ tAASS ____________+1.1 I~
m
S
m
AAS
:e
1
N
,
I I
A
.1
tAPCCAS
1 1
1 1
\ {~
I
~
r •
'41~----__.'!_1-
tWHA
Figure 12. Self Refresh Cycle Timing
TEXAS . "
INsrRUMENTS
4-452
VIL
yl, - - - VIH
IT
~.-:;;=====-t:-rl-:-~r,''r-)- - - - - - - - - - - - - - - - - - - - - - - -
twSA
VIH
tCHS~
I I
~ I
~
tAPS
---"i"'--.
11r-i
~tCSA~
~
.1
1
POST OFFICE BOX 1443· HOUSTON, TEXAS 77001
VIL
TMS427400, TMS427400P
4 194 304·WORD BY 4·BIT
LOW·VOLTAGE DYNAMIC RANDOM·ACCESS MEMORIES
SMKS274-JANUARY 1993
PARAMETER MEASUREMENT INFORMATION
~ Refresh Cycle
~ Memory Cycle ~
I
N
I'"
.1
I
I"
1I
1
tRAS
V!
1 I
N
I
1
I 1
I
I
. .
II
I I
'
I I
tASR
W!
I
tR~H
I
-+,
~ Refresh Cycle
I"
.1 1 tRAS
11
foI-
i1
tRP
h
tCAS
tt1 1
II
I I
foI- tWHR
--+i
1
1
1
/~VIH
I 1
i~ iRCS v~tw~
I
I 101
1
.1
1
I
Ii
I Ii)'
II Il:Jlohl
r-tCAC
~t/
IL
I+-tw~:::
~
3:
w
tAA
tOFF ~ I+~tRAG~~__________________________~,__________~1
VOH
DQ1-DQ4
I .1
----~
tCLZ
Valid Data o u t : :
-.1 ~
tOEZ
~~~~ J"II~tOEA
OE~
II')
:>w
} - VOL
~I
a:
a..
I...-VIH
~VIL
I-
o
::J
C
Figure 13. Hidden Refresh Cycle (Read)
o
a:
a..
TEXAS ."
INsrRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
4-453
TMS427400, TMS427400P
4 194 304-WORD BY 4-BIT
LOW-VOLTAGE DYNAMIC RANDOM-ACCESS MEMORIES
SMKS274-JANUARY 1993
PARAMETER MEASUREMENT INFORMATION
~ Memory Cycle
-1
Refresh Cycle
~
f4-- Refresh Cycle ~I
I
I
I !+- tRAS +i !+-- tRP -+j !+- tRAS ~ !+-- tRP -+j
I I
I I
. I I
I I
I
RAS
I i 11
I I
:i
tRAH
AG-A10
f{
I
r1
i
-I
"Jl
DQ1-DQ4
-m~
'L-/
((
~
VIL
.1
~y-
VVIIHL
))
I I
I I
I I
I Row I I Col
l1li
I
I I~
tOSttI
o
tCAS
1
~iRr ~I ~ ~
I I.: twc~
-+J
w~tw~~/V
C
/
I I
,
C
\
tCHR
:i
I I
~]4-1 tCAH
I f--+I ~ tASC
~~ I I I i
I
I I II I
i.--+t~s II I
rSl-----{rVIH
~
l~ogH*{~~VIH
~
~
twcs
"oJl
Y
I I
I
I
~
.l...1
....1
'L
I~
Valid Data
r-
~ twSR
.
twHR
~
tWCH
)@22§§220§§2§~J*HH~~ :::
OE~H{t}l*_~:::
=E
Figure 14. Hidden Refresh Cycle (Write)
TEXAS .."
INSTRUMENTS
4·454
POST OFFICE BOX 1443· HOUSTON, TEXAS 77001
TMS427400, TMS427400P
4194 304-WORD BY 4-BIT
LOW-VOLTAGE DYNAMIC RANDOM-ACCESS MEMORIES
SMKS274-JANUARY 1993
PARAMETER MEASUREMENT INFORMATION
Figure 15. Test Mode Entry Cycle
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
4·455
TMS427400,TMS427400P
4194 304·WORDBY 4·BIT
LOW·VOLTAGE DYNAMIC RANDOM·ACCESS MEMORIES
SMKS274-JANUARY 1993
device symbolization
TI
D
I
~
TMS427400
!¥
WAPT!,f
I
Speed (-60, -70, -SO, -10)
Power/Refresh Code (Blank, P)
Package Code
Lot Traceability Code
Month Code
Assembly Site Code
Ole Revision Code
Wafer Fab Code
"oJJ
C
c:
o
-I
"m
JJ
S
m
:E
TEXAS ."
iNSI'RUMENTS
4-456
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
TMS426800, TMS426800P
2 097 152 WORD BY 8·BIT
LOW VOLTAGE DYNAMIC RANDOM·ACCESS MEMORIES
SMKS268-JANUARY 1993
• Organization ... 2 097 152 x 8
• Single 3.3-V Power Supply (±0.3 V
Tolerance)
DE PACKAGEt
(TOP VIEW)
• Performance Ranges:
ACCESS ACCESS ACCESS READ
TIME
TIME
TIME OR WRITE
(tRAC) (tcAC)
(tAA)
CYCLE
(MAX)
(MAX)
(MAX)
(MIN)
'426800/P-70
70 ns
18 ns
35 ns
130 ns
'426800/P-80
80 ns
20 ns
40 ns
150 ns
• Enhanced Page Mode Operation With
CAS-Before-RAS Refresh
• Long Refresh Period ..•
- 4096-Cycle Refresh in 64 ms (Max)
- 512 ms for Low Power, Self-Refresh
Version (TMS426800P)
• 3-State Unlatched Output
• Low Power Dissipation
- 100 ~ CMOS Standby
- 100 ~ Extended Refresh Battery Backup
• Self-Refresh With Low-Power
• All Inputs/Outputs and Clocks are TTL
Compatible
• High-Reliability Plastic 28-Pin, J-Lead
400-Mil-Wlde Surface Mount (SOJ)
Package, and 32-Pin, Plastic Thin Small
Outline Package (TSOP)
• Operating Free-Air Temperature Range
O°C to 70°C
• Texas Instruments EPIC ™ CMOS Process
VCC
DOO
W
DZPACKAGEt
(TOP VIEW)
VSS
DO?
D06
D05
D04
CAS
VCC
DOO
DOl
D02
D03
DE
RAS
All
Al0
AO
Al
A2
A3
A9
AS
A?
A6
A5
A4
VCC
VSS
RAS
NC
All
Al0
AO
Al
A2
A3
NC
NC
A9
AS
A?
A6
A5
A4
VCC
VSS
W
VSS
DO?
D06
D05
D04
CAS
DE
:=w
t Packages are shown for pinout reference only.
:>
w
PIN NOMENCLATURE
AO--A11
CAS
DOO--D07
NC
OE
RAS
w
VCC
VSS
~
0.
Address Inputs
Column-Address Strobe
Data In/Data Out
No Internal Connection
Output Enable
Row-Address Strobe
Write-Enable
3.3-V Supply
Ground
....
t.)
::J
C
o
~
0.
description
The TMS426800 series are high-speed, low voltage 16777 216-bit dynamic random-access memories,
organized as 2 097 152 words of eight bits each.
The TMS426800P series are high-speed, low voltage, low-power, self-refresh, 16 777 216-bit dynamic
random-access memories, organized as 2 097 152 words of eight bits each.
They employ state-of-the-art EPIC™ (Enhanced Performance Implanted CMOS) technology for high
performance, reliability, and low power at a low cost.
These devices feature maximum RAS access times of 70 ns and 80 ns. Maximum power dissipation is as low
as 252 mW operating, and 0.36 mW standby and battery backup for 80 ns devices.
All inputs and outputs, including clocks, are compatible with Series 74 TTL. All addresses and data-in lines are
latched on-chip to simplify system design. Data out is unlatched to allow greater system flexibility.
The TMS426800 and TMS426800P series are offered in a 400-mil 28-lead plastic surface mount SOJ package
(DZ suffix) and a 32-lead plastic surface mount TSOP package (DE suffix). These packages are characterized
for operation from O°C to 70°C.
EPIC is a trademark of Texas Instruments Incorporated.
PRODUCT PREVIEW InIormaUon ...,..... plOd.etaln Iht IormollY. or
d"~ ph... of devtlopll'tlnL Chlracttrtstlc data and oth,r
:r.:,,::~=~~=;ol.U: =~rn:::",,"lh' right to
TEXAS
~
Copyright © 1993. Texas Instruments Incorporated
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
4-457
TMS426800, TMS426800P
2 097 152 WORD BY 8·BIT
LOW VOLTAGE DYNAMIC RANDOM·ACCESS MEMORIES
SMKS268-JANUARY 1993
operation
enhanced page mode
Enhanced page-mode operation allows faster memory access by keeping the same row address while selecting
random column addresses. The time for row-address. setup and hold and address multiplex is thus eliminated.
The maximum number of columns that may be accessed is determined by the maximum RAS low time and the
CAS page cycle time used. With minimum CAS page cycle time, all512 columns specified by column addresses
AO through AS can be accessed without intervening RAS cycles.
Unlike conventional page-mode DRAMs, the column-address buffers in this device are activated on the falling
edge of RAS. The buffers act as transparent or flow-through latches while CAS is high. The falling edge of CAS
latches the column addresses. This feature allows the TMS426800 and TMS426800P to operate at a.higher
data bandwidth than conventional page-mode parts, since data retrieval begins as soon as the column address
is valid rather than when CAS transitions low. This performance improvement is referred to as enhanced page
mode. Valid column address may be presented immediately after row address hold time has been satisfied,
usually well in advance of the falling edge of CAS. In this case, data is obtained after tCAC max (access time
from CAS low), if tAA max (access time from column address) has been satisfied. In the event that column
addresses for the next cycle are valid at the time CAS goes high, access time for the next cycle is determined
by the later occurrence of tCAC or tCPA (access time from rising edge of CAS).
"o
:D
address (AO-A11)
Twenty-one address bits are required to decode 1 of 2097 152 storage cell locations. Twelve row-address bits
are set up on inputs AO through A11 and latched onto the chip by the row-address strobe (RAS). The nine
column-address bits are set up on pins AO through A8 and latched onto the chip by the column-address strobe
(CAS). All addresses must be stable on.or before the falling edges of RAS and CAS. RAS is similar to a chip
enable in that it activates the sense amplifiers as well as the row decoder. CAS is used as a chip select activating
the output buffer, as well as latching the address bits into the column-address buffer.
C
C
o
-I
":Dm
write enable (W)
The read or write mode is selected through the write-enable (W) input. A logic high on the W input selects the
read mode and a logic low selects the write mode. The write-enable terminal can be driven from standard TTL
circuits without a pullup resistor. The data input is disabled when the read mode is selected .. When W goes low
prior to CAS (early write), data out will remain in the high-impedance state for the entire cycle permitting a write
operation independent ofthe state of OE. This permits early write operation to be completed with OE grounded.
S
m
:e
data in/out (DQO-DQ7)
The three-state output buffer provides direct TTL compatibility (no pullup resistor required) with a fanout of two
Series 74 TTL loads. Data out is the same polarity as data in. The output is in the high-impedance (floating) state
until CAS and OE are brought low. In a read cycle the output becomes valid after all access times are satisfied.
The output remains valid while CAS and OE are low. CAS or OE going high returns it to a high-impedance state.
This is accomplished by bringing OE high prior to applying data, thus satisfying tOED'
TEXAS
~
INSTRUMENTS
4-458
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
TMS426800, TMS426800P
2097152 WORD BY 8·BIT
LOW VOLTAGE DYNAMIC RANDOM·ACCESS MEMORIES
SMKS268-JANUARY 1993
output enable (OE)
OE controls the impedance of the output buffers. When OE is high, the buffers will remain in the high-impedance
state. Bringing OE low during a normal cycle will activate the output buffers putting them in the low-impedance
state. It is necessary for both RAS and CASto be brought low for the output buffers to go into the low-impedance
state, they will remain in the low-impedance state until either OE or CAS is brought high.
refresh
A refresh operation must be performed at least once every 64 milliseconds (512 ms for TMS426800P) to retain
data. This can be achieved by strobing each of the 4096 rows (AO-A 11). A normal read or write cycle will refresh
all bits in each row that is selected. A RAS-only operation can be used by holding CAS at the high (inactive) level,
thus conserving power as the output buffer remains in the high-impedance state. Externally generated
addresses must be used for a RAS-only refresh.
hidden refresh
Hidden refresh may be performed while maintaining valid data at the output pin. This is accomplished by holding
CAS at VIL after a read operation and cycling RAS after a specified precharge period, similar to a RAS-only
refresh cycle.
CAS·before·RAS refresh
CAS-before-RAS (CBR) refresh is utilized by bringing CAS low earlier than RAS (see parameter tc.s..sL and
holding it low after RAS falls (see parameter tCHR)' For successive CAS-before-RAS refresh cycles, CAS can
remain low while cycling RAS. The external address is ignored and the refresh address is generated internally.
A low-power battery-backup refresh mode that requires less than 100 !AA refresh current is available on the
TMS426800P. Data integrity is maintained using CAS-before-RAS refresh with a period of 125 I-Is, while holding
RAS low for less than 1 I-Is. To minimize current consumption, all input levels need to be at CMOS levels
(VIL'; 0.2 V, VIH "VCC - 0.2 V).
self refresh (TMS426800P)
The self-refresh mode is entered by dropping CAS low prior to RAS going low. Then CAS and RAS are both
held low for a minimum of 100 I-Is. The chip is then refreshed by an on-board oscillator. No external address is
required since the CBR counter is used to keep track of the address. To exit the self-refresh mode, both RAS
and CAS are brought high to satisfy tCHS' Upon exiting self-refresh mode, a burst refresh (refresh a full set of
row addresses) must be executed before continuing with normal operation. The burst refresh ensures the
DRAM is fully refreshed.
power up
To achieve proper device operation, an initial pause of 200 I-Is followed by a minimum of eight RAS cycles is
required after power-up to the full VCC level.
TEXAS ~
INsrRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
4-459
~
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TMS426800, TMS426800P
2097152 WORD BY 8·BIT
LOW VOLTAGE DYNAMIC RANDOM·ACCESS MEMORIES
SMKS26lhJANUARY 1993
logic symbol t
RAM2Mx8
AO 10
A1 11
2009/2100 '
A2 12
A3 13
A4
A5
16
17
0
A 2 097 151
A6 18
A7 19
A8 20
A9 21
20017/2108
20018
A10 9
A11 8
"'C
II
0
C
RAS
0
w
"'C
OE
20019
7
CAS 23
C
-I
II
m
-<
000
m
6
~
> C20[ROW)
f
>
r
22
G23/[REFRESH ROW)
24[PWROWN)
C21[COL)
G24
&
23,210
I>
23C22
i>
24,25EN
r--. G25
,
2
r
A,220
4- V26
001 3
002 4
:E
~
20020
003 5
004 24
~
DOS 25
006 26
007 27
tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and lEG Publication 617-12.
The pin numbers shown correspond to the DZ package.
TEXAS ~
INSTRUMENTS
4-460
POST OFFICE BOX 1443' HOUSTON. TEXAS 77001
A,Z26-
TMS426800, TMS426800P
2 097 152 WORD BY 8·BIT
LOW VOLTAGE DYNAMIC RANDOM·ACCESS MEMORIES
SMKS268-JANUARY 1993
functional block diagram
I
+
AO
Al
•
•
•
AS
I
32
7
/
Column
Address
Buffers
Column Decode
~
2
Sense Amplifiers
256KArray
256K Array
..
"...
..
256KArray
32
Row
Address
Buffers
Timing and Control
2
L
•
•
•
+ + + +
•
••
256K Array
•
••
0
c
L±
32
~
0
12
I/O
Buffers
S of 32
Selection
a:
'-'---
256KArray
A9, Al0, All
12
/
~
In
Reg.
~
Out
Reg.
256K Array
000-007
l'
==
w
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
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Supply voltage range on any pin (see Note 1) ....................................... - 0.5 V to 4.6 V
Supply voltage range on Vee ...................................................... - 0.5 V to 4.6 V
Short circuit output current ................................................................ 50 mA
Power dissipation .......................................................................... 1 W
Operating free-air temperature range ........................................... ,...... O·C to 70·C
Storage temperature range ....................................................... - 55·C to 125·C
o
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. This is a stress rating only, and
a:
functional operation ofthe device atthese or any other conditions beyond those indicated in the "recommended operating conditions" section of
this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values in this data sheet are with respect to VSS.
recommended operating conditions
MIN
NOM
MAX
Vee
Supply voltage
3
3.3
3.6
V
VIH
High-level input voltage
2
Vee+ 0.3
V
VIL
Low-level input voltage (see Note 2)
-0.3
0.8
V
TA
Operating free-air temperature
a
70
'e
..
..
..
NOTE 2: The algebraic convention, where the more negative (less positive) limit IS designated as minimUm, IS used
voltage levels only.
TEXAS
In
UNIT
thiS data sheet for logic
~
IN5rRUMENTS
POST OFFICE BOX 1443· HOUSTON. TEXAS 77001
4-461
I-
:J
C
o
c..
TMS426800, TMS426800P
2097 152 WORD BY 8·BIT
LOW VOLTAGE DYNAMIC RANDOM·ACCESS MEMORIES
SMKS268-JANUARY 1993
electrical characteristics over full ranges of recommended operating conditions (unless otherwise
noted) .
PARAMETER
TEST CONDITIONS
TMS426800-70
TMS426800P-70
MIN
VOH
High-level output
voltage
IOH=-2mA
VOL
Low-level output
voltage
IOL=2mA
MAX
TMS426800-80
TMS426800P-S0
MIN
2.4
2.4
0.4
!!A
!!A
VOH
Option
10H = -100
VOL
Option
10L = +100
II
Input current (leakage)
VCC-0.2
UNIT
MAX
V
0.4
V
V
VCC-0.2
0.2
0.2
V
VCC = 3.6 V, VI = 0 to 3.9 V,
All other pins = 0 to VCC
±10
±10
!!A
10
Output current
(leakage)
VCC = 3.6 V, Vo = 0 to VCC,
CAS high
±10
±10
!!A
ICCl t
Read or write cycle
current (see Note 3)
VCC = 3.6 V, Minimum cycle
80
70
mA
1
1
mA
After 1 memory cycle,
RAS and CAS high,
"tJ
:c
o
VIH = 2 V (LVTTL)
ICC2
Standby current
c
c::
o
-I
"tJ
:c
m
S
m
:e
VIH =VCC-O.2 V
(LVCMOS),
'426800
300
300
After 1 memory cycle,
RAS and CAS high
'426800P
100
100
!!A
ICC3
Average refresh
current (RAS-only or
CBR) (see Note 3)
VCC = 3.6 V, Minimum cycle,
RAS cycling, CAS high,
(RAS-only); RAS low
after CAS low (CSR)
80
70
mA
ICC4 t
Average page current
(see Note 4)
VCC = 3.6 V, tpc = Minimum,
RAS low, CAS cycling
80
70
mA
ICC6*
Self refresh current
CAS" 0.2 V, RAS < 0.2 V,
Measured after tRASS minimum
100
100
!!A
ICC7 t
Standby current,
outputs enabled
RAS = VIH, CAS = VIL
Data out = Enabled
5
5
mA
Battery backup
operating current
tRC = 125 ~s, tRAS " 1 ~s,
VCC-0.2V "VIH ,,3.9V,
(equivalent refresh
time is 512 ms)
CSR only
V "VIL" 0.2 V,
Wand OE = VIH,
Address and Data stable
100
100
I'A
ICC10*
o
t Measured with outputs open.
*
For TMS426800P only.
NOTES: 3. Measured with a maximum of one address change while RAS = VIL.
4. Measured with a maximum of one address change while CAS = VIH.
TEXAS ~
INSTRUMENTS
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TMS426800, TMS426800P
2 097 152 WORD BY 8·BIT
LOW VOLTAGE DYNAMIC RANDOM·ACCESS MEMORIES
SMKS26lhJANUARY 1993
capacitance over recommended ranges of supply voltage and operating free-air temperature,
f = 1 MHz (see Note 5)
MIN
PARAMETER
TVP
MAX
UNIT
Ci(A)
Input capacitance, address inputs
5
Ci(OE)
Input capacitance, output enable
7
pF
pF
Ci(RC)
Input capacitance, strobe inputs
7
pF
Ci(W)
Input capacitance, write-enable input
7
pF
Co
Output capacnance
7
pF
NOTE 5: VCC equal to 3.3 V ± 0.3 V and the bias on pins under test is 0 V.
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature
TMS426800-70
TMS426800P·70
PARAMETER
MIN
MAX
TMS42680O-S0
TMS426800P-S0
MIN
UNIT
MAX
tM
Access time from column-address
35
40
ns
tCAC
Access time from CAS low
18
20
ns
tCPA
Access time from column precharge
40
45
ns
tRAC
Access time from RAS low
70
80
ns
tOEA
Access time from OE low
20
ns
tCLZ
CAS to output in low Z
18
0
0
ns
tOH
Output disable time, start of CAS high
3
3
ns
tOHO
Output disable time, start of OE high
3
3
ns
tOFF
Output disable time after CAS high (see Note 6)
0
18
0
20
ns
tOEZ
Output disable time after OE high (see Note 6)
0
18
0
20
ns
NOTE 6:
..
tOFF and tOEZ are specified when the output IS no longer dnven.
3:
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TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
4-463
TMS426800, TMS426800P
2 097 152 WORD BY 8·BIT
LOW VOLTAGE DYNAMIC RANDOM·ACCESS MEMORIES
SMKS268-JANUARY 1993
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
TMS426800-70
TMS426800P-70
PARAMETER
MIN
"'C
:0
o
C
c:
o
-I
MAX
TMS426800-S0
TMS426800P-S0
MIN
UNIT
MAX
tRC
Random read or write cycle (see Note 7)
130
150
tRWC
Read-modify-write cycle time
181
205
ns
tpc
Page-mode read or write cycle time (see Note 8)
45
50
ns
tpRWC
Page-mode read-modify-write cycle time
96
tRASP
Page-mode pulse duration, RAS low (see Note 9)
70
'100000
80
100000
ns
tRAS
Non-page-mode pulse duration, RAS low (see Note 9)
70
10 000
80
10000
ns
tCAS
Pulse duration, CAS low (see Note 10)
18
10 000
20
10000
ns
tcp
Pulse duration, CAS high (CAS precharge)
10
10
ns
tRP
Pulse duration, RAS high (RAS precharge)
50
60
ns
twp
Write pulse du ration
15
15
ns
tASC
Column-address setup time before CAS low
0
0
ns
tASR
Row-address setup time before RAS low
0
0
ns
tDS
Data setup time (see Note 11)
0
0
ns
tRCS
Read setup time before CAS low
0
0
ns
tCWL
W low setup time before CAS high
18
20
ns
tRWL
W low setup time before RAS high
18
20
ns
twcs
W low setup time before 9AS low
(Early write operation only)
0
0
ns
NOTES:
"'C
:0
m
::s;
m
105
ns
7. All cycle times assume IT = 5 ns.
8. To assure tpc min, tASC should be greater than or equal to tcp.
9. In a read-modify-write cycle, tRWD and tRWL must be observed. Depending on the user's transition times, this may require additional
RAS low time (tRAS)'
10. In a read-modify-write cycle, tCWD and tCWL must be observed. Depending on the user's transition times, this may require additional
CAS low time (tCAS)'
11. Referenced to the later of CAS or IN in write operations.
~
TEXAS ~
INSTRUMENTS
4-464
ns
POST OFFICE BOX 1443· HOUSTON. TEXAS 77001
TMS426800, TMS426800P
2 097 152 WORD BY 8-BIT
LOW VOLTAGE DYNAMIC RANDOM-ACCESS MEMORIES
SMKS268-JANUARY 1993
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (continued)
TMS426800-70
TMS426800P-70
PARAMETER
MIN
MAX
TMS426800-80
TMS426800P-B0
MIN
UNIT
MAX
leAH
Column-address hold time after CAS low
15
15
ns
tDH
Data hold time (see Note 11)
15
15
ns
tRAH
Row-address hold time after RAS low
10
10
ns
tRCH
Read hold time after CAS high (see Note 12)
0
0
ns
tRRH
Read hold time after RAS high (see Note 12)
5
5
ns
twCH
Write hold time after CAS low
(Early write operation only)
15
15
ns
tAWD
Delay time, column address to W low
(Read-modify-write operation only)
63
70
ns
leHR
Delay time, RAS low to CAS high
(CAS-before-RAS refresh only)
20
20
ns
leRP
Delay time, CAS high to RAS low
5
5
ns
tCSH
Delay time, RAS low to CAS high
70
80
ns
tCSR
~ time, CAS low to RAS low
(CAS-before-RAS refresh only)
10
10
ns
leWD
Delay time, CAS low to W low
(Read-modify-write operation only)
46
50
ns
toEH
OE command hold time
18
20
ns
toED
OE to data delay
18
20
ns
tROH
RAS hold time referenced to OE
10
10
tRAD
Delay time, RAS low to column-address (see Note 13)
15
tRAl
Delay time, column-address to RAS high
35
40
ns
tCAl
Delay time, column address to CAS high
35
40
ns
tRCD
Delay time, RAS low to CAS low (see Note 13)
20
tRPC
Delay time, RAS high to CAS low
0
0
ns
tRSH
Delay time, CAS low to RAS high
18
20
ns
tRWD
Delay time, RAS low to W low
(Read-modify-write operation only)
98
110
ns
tcpw
Delay time, W from CAS precharge
68
75
ns
tCPRH
Hold time, RAS from CAS precharge
40
45
ns
35
52
15
20
ns
40
60
ns
ns
NOTES: 11. Referenced to the later of CAS or W In wnte operations.
12. Either tRRH or tRCH must be satisfied for a read cycle.
13. The maximum value is specified only to assure access time.
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
4-465
~
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a.
TMS426800, TMS426800P
2 097 152 WORD BY 8·BIT
LOW VOLTAGE DYNAMIC RANDOM·ACCESS MEMORIES
SMKS268--JANUARY 1993
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (concluded)
TMS426800·70
TMS426800P·70
PARAMETER
MIN
MAX
TMS426800·80
TMS426800P-80
MIN
UNIT
MAX
tCPR
CAS precharge before self refresh
0
0
ns
tRPS
RAS precharge after self refresh
130
150
ns
tRASS
Self refresh entry from RAS low
100
100
~
tCHS
CAS low hold time after RAS high (self-refresh)
-50
-50
ns
tREF
Refresh time interval (TMS426800 only)
tREF
Refresh time interval Low power (TMS426800P only)
IT
Transition time
3
64
64
ms
512
512
ms
30
ns
30
3
PARAMETER MEASUREMENT INFORMATION
1.4V
VCC=3.3V
"tJ
:D
o
RL = 500
C
C
Output Under Test
Output Under Test
o
Rl = 1178Q
Q
CL = 100 pF
-I
"tJ
T
:D
m
:S
m
(a) Load Circuit
T
(b) Alternate Load Circuit
Figure 1. Load Circuits for Timing Parameters
=e
TEXAS . "
INSTRUMENTS
4-466
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
TMS426800, TMS426800P
2097152 WORD BY 8·BIT
LOW VOLTAGE DYNAMIC RANDOM·ACCESS MEMORIES
SMKS26s-JANUARY 1993
PARAMETER MEASUREMENT INFORMATION
!\
1
'-----
.1
AO-A11
->==W
w
a:
c..
IU
::J
C
o
a:
c..
NOTE A: Output may go from a high-impedance state to an invalid data state prior to the specified access time.
Figure 2. Read Cycle Timing
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
4-467
TMS426800, TMS426800P
2097 152 WORD BY 8·BIT
LOW VOLTAGE DYNAMIC RANDOM·ACCESS MEMORIES
SMKS268-JANUARY 1993
PARAMETER MEASUREMENT INFORMATION
"C
JJ
o
C
c:
o
-I
"C
JJ
m
m
:S
:E
Figure 3. Early Write Cycle Timing
ThxAs . "
INSTRUMENTS
4·468
POST OFFICE BOX 1443· HOUSTON, TEXAS 77001
TMS426800, TMS426800P
2097152 WORD BY 8·BIT
LOW VOLTAGE DYNAMIC RANDOM·ACCESS MEMORIES
SMKS268--JANUARY 1993
PARAMETER MEASUREMENT INFORMATION
3:
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oa:
c.
NOTE A: Referenced to the later of CAS or W in write operations.
Figure 4. Write Cycle Timing
TEXAS ~
INSTRUMENTS
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4-469
TMS426800, TMS426800P
2 097 152 WORD BY 8-BIT
LOW VOLTAGE DYNAMIC RANDOM-ACCESS MEMORIES
SMK5268-JANUARY 1993
PARAMETER MEASUREMENT INFORMATION
"'C
:rJ
o
C
c:
o
-f
"'C
:rJ
m
S
m
:e
NOTE A: Output may go from a high-impedance state to an invalid data state prior to the specified access time.
Figure 5. Read-Modify-Write Cycle Timing
TEXAS ~
INSTRUMENTS
4-470
POST OFFICE BOX 1443· HOUSTON. TEXAS 77001
TMS426800, TMS426800P
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LOW VOLTAGE DYNAMIC RANDOM·ACCESS MEMORIES
SMKS26!hJANUARY 1993
PARAMETER MEASUREMENT INFORMATION
tRP
I"
-------------------~~I 1
1 + - - - - - tCPRH
~I
1
-------lI~
~--------------------~--------~~~--------, 1
: 4 - - - - tpc
~I+-- tCRP
I
1
---+i
I
Column
AO-A11
~ tRCS
+
I
1
:
I I..
tAA
(see Note A)
r-+
tRRH -+I
tRCH --+I
3:
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a:
a.
tO
:J
C
NOTES: A. Access time is tCPA or tM dependent.
B. Output may go from a high-impedance state to an invalid data state prior to the specified access time.
C. A write cycle or read-modify-write cycle can be intermixed with the read cycles as long as the write and read-modify-write timing
specifications are not violated.
Figure 6. Enhanced Page-Mode Read Cycle Timing
TEXAS ~
INSTRUMENTS
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4-471
o
a:
a.
TMS426800, TMS426800P
2 097 '152 WORD BY 8·BIT
LOW VOLTAGE DYNAMIC RANDOM·ACCESS MEMORIES
SMKS268-JANUARY 1993
PARAMETER MEASUREMENT INFORMATION
AO-A11
I I
tCWL~
I
"'C
i+-J---..j tcwL ---+I
I
o
~I twp
I
I I I
I~ I I
lJ
w~o~~~aZ~ I! ~£@~~
C
C
o
-I
"'C
lJ
~
m
I
~tRwL~
I
II~~
114~--- tos
:
I
I
OQO-DQ7~
(see Note A)
~I
Valid oa:a In
I+- tOEH
-+:
:
'"-- tOEH -.I
I
I
(see Note A)
.
I
~ Vf~d .o~X~~~
tOED
~
14-
I
~
NOTES: A. Referenced to the later of CAS or Vii in write operations.
B. A read cycle or a read-modify-write cycle can be intermixed with the write cycles as long as the read and read-modify-write timing
specifications are not violated.
Figure 7_ Enhanced Page-Mode Write Cycle Timing
TEXAS ~
INsrRUMENTS
4-472
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
TMS426800, TMS426800P
2 097 152 WORD BY 8·BIT
LOW VOLTAGE DYNAMIC RANDOM·ACCESS MEMORIES
SMKS26s-"JANUARY 1993
PARAMETER MEASUREMENT INFORMATION
tRP~
RAS ~
II I
....f - - - - - - tCPRH _ _ _ _ _..
~I
I
I
I I
I I"
tCSH
~I I
~..- - - - tRSH ----~~I
I"
tpRWC
I I
~I I
I" I
I I
n
: I"
CAS
-+l
I
t~AD
4
I
I,..
I
j+-
tRASP------------.~
tASR
.r-........
tRCD
}
~f
~ teAS ----;Ii
-+I~tASC
~II I
II I
I
t
tCRP
~
....
1 +1_ __
/ :
I
I
I
-'
CAH
~
tcp
I
I
I
I
I
I
I
I
I
"'"I
AD-A11
3:
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c.
....
o
I
I
I
tCLZ ~ i+i I
~ tOEA ----.I I
I
I
I
OE~
tOEZ~~
II
tOHO -+i I i+"
1---+1- tOED
1<111
..
I
I
1+ tOEH
+l
::J
C
I
I
I
:
:
I
I
I
I
o
a:
c.
y~------~~~----~~~~~~
NOTES: A. Output may go from a high-impedance state to an invalid data state prior to the specified access time.
B. A read or write cycle can be intermixed with read-modify-write cycles as long as the read and write timing specifications are not
violated.
Figure 8. Enhanced Page-Mode Read-Modify-Write Cycle Timing
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
4-473
TMS426800, TMS426800P
2 097 152 WORD BY 8-BIT
LOW VOLTAGE DYNAMIC RANDOM-ACCESS MEMORIES
SMKS26lhJANUARY 1993
PARAMETER MEASUREMENT INFORMATION
"tJ
:IJ
o
DOO-D07 - - - - - - - - - - - - - - HI-Z - - - - - - - - - - - - - -
C
C
o
-t
Figure 9. RAS-Only Refresh Timing
"tJ
:IJ
m
:S
m
:e
TEXAS
~
INsrRUMENTS
4-474
POST OFFICE BOX 1443' HOUSTON, TEXAS 77001
TMS426800, TMS426800P
2097152 WORD BY 8-BIT
LOW VOLTAGE DYNAMIC RANDOM-ACCESS MEMORIES
SMKS268-JANUARY 1993
PARAMETER MEASUREMENT INFORMATION
1~~------------------tRC------------------~~1
~ IRP ~ ~I~------------IRAS ------J>I~I 1
1
I I
I 1;...-_ _ __
RAS
ANY
1
_I
IRPC_
CAS
I I
I
I "~----ICHR
!+- ICSR ~
~
~I
\{~I_____~___~___~________________~}I
w~§§0§*022§§§0§9~1*H*~~
A~A11~~*H*i~
~
w
DQ~DQ7 - - - - - - - - - - - - - - - - - - - - - - - - - - - HI-Z - - - - - _ - - - - - - -
Figure 10. Automatic (CAS-Before-RAS) Refresh Cycle Timing
:>
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c.
t-
O
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oex:
c.
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443· HOUSTON, TEXAS 77001
4·475
TMS426800, TMS426800P
2 097 152 WORD BY 8-BIT
LOW VOLTAGE DYNAMIC RANDOM-ACCESS MEMORIES
SMKS26lhJANUARY 1993
PARAMETER MEASUREMENT INFORMATION
~ Memory Cycle
I
,
I
t+- Refresh Cycle -+1
,..
~I
1_
.1
,
I
tRP
J
j+tRAS'" "
Y
N
::I
l\l !
:i
Jr
, '
I
I
I
I+- tRP -+I
,
~tRAS}.):
RAS~
t+- Refresh Cycle ---+i
---+i
\
/~
" '
"
1 ,-
~
"
,
i+-tcAH
tCHR
'I',
i
"
: H H+t
ASC
I
:a
iJ110li
c
c
Vi
o
OQO-OQ7
m
:
,
::
,
,
'-+j' J+- tCAC
'4 , .1 tAA
(see Note A)
"
'~§0Q20§0§§§§2QQ~J*i*!~~
:
tCLZ
.
I
~
Valid Data Out
~:
--.I *-1
OE~tOEA
~
m
:e
,
~
~~~
-I
"'C
.1
....11~_~;'t;;.'~pH*x-:~
__
, ,,,
,
o
:a
:vr-,
I
"
tASR~J4R~
"'C
I
'
: :
tRAHt\J+iI,1
14
iI
tCAS
((
n
NOTE A: Output may go from a high-impedance state to an invalid data state prior to the specified access time.
Figure 11. Hidden Refresh Cycle (Read)
TEXAS ."
INSTRUMENTS
4-476
POST OFFICE BOX 1443· HOUSTON. TEXAS nOOl
~~
TMS426800, TMS426800P
2097152 WORD BY 8·BIT
LOW VOLTAGE DYNAMIC RANDOM·ACCESS MEMORIES
SMKS268-JANUARY 1993
PARAMETER MEASUREMENT INFORMATION
~
w
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w
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a..
I-
o
~I
:
:::J
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tDH
(see Note A)
DaD-Da7 ~""--va-lid-Da-ta-ln-"ll~~*HH.~
OE~H{t}H_~
NOTE A: Referenced to the later of CAS or IN in write operations.
Figure 12. Hidden Refresh Cycle (Write)
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443· HOUSTON. TEXAS 77001
4-477
oa:
a..
TMS426800, TMS426800P
2097152 WORD BY 8-BIT
LOW VOLTAGE DYNAMIC RANDOM-ACCESS MEMORIES
SMKS268-JANUARY 1993
PARAMETER MEASUREMENT INFORMATION
1414----- tRASS ----+f.1
_ _J
1
N
A
1
tRPC
1
14
tCSR
1
~
1
~
_ _ _ _ _ _ _ _ _.J 1
.1
1
--J...!
t+ tRPS +i
[4-
1
--11-1---N
1
1
~
~
1
~tCHS
~~~"1'1:"?
1
t+-tCPR~
Ao-A11
~H*~
w~~IT-r~
"'tJ
o'~m*~
:D
o
C
~
C
O·
-I
DQ~Q7
*-tOFF
~----------HI-Z
"'tJ
Figure 13. Self Refresh Timing
:D
m
<
-
_ _ _ _- - - - - - - -
device symbolization
m
:e.
t-¥
TI
P
TMS426BOO
W
A
~
~
T JJF
Speed ( -70, -80)
Low Power/Refresh Option
Package Code
Lot Traceability Code
Date Code
Assembly Site Code
Ole Revision Code
Wafer Fab Code
TEXAS
~
INsrRUMENTS
4-478
POST OFFICE BOX 1443· HOUSTON, TEXAS 77001
TMS427800, TMS427800P
2 097 152 WORD BY 8·BIT
LOW VOLTAGE DYNAMIC RANDOM·ACCESS MEMORIES
SMKS278-JANUARY 1993
DE PACKAGEt
(TOP VIEW)
• Organization ... 2 097 152 x S
• Single 3.3-V Power Supply (±0.3 V
Tolerance)
• Performance Ranges:
ACCESS
TIME
(IRAC)
(MAX)
'427800/P-70
70 ns
'427800/P-80
80 ns
ACCESS
TIME
(ICAC)
(MAX)
18 ns
20 ns
ACCESS READ
TIME OR WRITE
(IAAl
CYCLE
(MAX)
(MIN)
35 ns
130 ns
40 ns
150 ns
• Enhanced Page Mode Operation With
CAS-Before-RAS Refresh
• Long Refresh Period ...
- 204S-Cycle Refresh in 32 ms (Max)
- 256 ms for Low Power, Self-Refresh
Version (TMS427S00P)
• 3-State Unlatched Output
• Low Power Dissipation
- 100 ItA CMOS Standby
- 100 ItA Extended Refresh Battery Backup
• Self-Refresh With Low-Power
VCC
DOO
D01
RAS
NC
NC
A10
AO
A1
A2
A3
VSS
D07
D06
D05
D04
CAS
OE
NC
NC
A9
A8
A7
A6
A5
A4
Vcc
Vss
D03
NC
IN
• Operating Free-Air Temperature Range
O°C to 70°C
• Texas Instruments EPIC ™ CMOS Process
Vec
DOO
D01
D02
D03
IN
RAS
NC
A10
AO
A1
A2
A3
Vec
Vss
D07
D06
D05
D04
CAS
OE
A9
A8
A7
A6
A5
A4
Vss
3:
w
>
w
t Packages are shown for pinout reference only.
• All Inputs/Outputs and Clocks are TTL
Compatible
• High-Reliability Plastic 2S-Pin, J-Lead
400-Mil-Wide Surface Mount (SOJ)
Package, and 32-Pin, Plastic Thin Small
Outline Package (TSOP)
DZPACKAGEt
(TOP VIEW)
PIN NOMENCLATURE
AO-A1O
DOD-D07
NC
IN
VCC
VSS
a:
Address Inputs
Column-Address Strobe
Data In/Data Out
No Internal Connection
Output Enable
Row-Address Strobe
Write-Enable
3.3-V Supply
Ground
Q.
....
o
:::J
C
o
a:
Q.
description
The TMS427800 series are high-speed, low voltage 16 777 216-bit dynamic random-access memories,
organized as 2 097 152 words of eight bits each.
The TMS427800P series are high-speed, low voltage, low-power, self-refresh, 16 777 216-bit dynamic
random-access memories, organized as 2 097 152 words of eight bits each.
They employ state-of-the-art EPIC™ (Enhanced Performance Implanted CMOS) technology for high
performance, reliability, and low power at a low cost.
These devices feature maximum RAS access times of 70 ns and 80 ns. Maximum power dissipation is as low
as 378 mW operating, and 0.36 mW standby and battery backup for 80-ns devices.
All inputs and outputs, including clocks, are compatible with Series 74 TTL. All addresses and data-in lines are
latched on-Chip to simplify system design. Data out is unlatched to allow greater system flexibility.
The TMS427800 and TMS427800P series are offered in a 400-mil 28-lead plastic surface mount SOJ package
(OZ suffix) and a 32-lead plastic surface mount TSOP package (DE suffix). These packages are characterized
for operation from O°C to 70°C.
EPIC is a trademark of Texas Instruments Incorporated.
Copyright © 1993, Texas Instruments Incorporated
PRODUCT PREVIEW Information cOnetrM producta In th. form.Uv, or
dellgn ph... of development. Char.cterl,tlc dill and other
lpeclflcatlonl are de.lan QOIII. Taxn Inmum.nil rellrves the right 10
ching' or dllcontlnue th... producta without notlc•.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
4-479
TMS427800, TMS427800P
2097152 WORD BY 8-BIT
LOW VOLTAGE DYNAMIC RANDOM-ACCESS MEMORIES
SMKS278-JANUARY 1993
operation
enhanced page mode
Enhanced page-mode operation allows faster memory access by keeping the same row address while selecting
random column addresses. The time for row-address setup and hold and address multiplex is thus eliminated.
The maximum number of columns that may be accessed is determined by the maximum RAS low time and the
CAS page cycle time used. With minimum CAS page cycle time, all 1024 columns specified by column
addresses AO through A9 can be accessed without intervening RAS cycles.
Unlike conventional page-mode DRAMs, the column-address buffers in this device are activated on the falling
edge of RAS. The buffers act as transparent or flow-through latches while CAS is high. The falling edge of CAS
latches the column addresses. This feature allows the TMS427800 and TMS427800P to operate at a higher
data bandwidth than conventional page-mode parts, since data retrieval begins as soon as the column address
is valid rather than when CAS transitions low. This performance improvement is referred to as enhanced page
mode. Valid column address may be presented immediately after row address hold time has been satisfied,
usually well in advance of the falling edge of CAS. In this case, data is obtained after tCAC max (access time
from CAS low), if tAA max (access time from column address) has been satisfied. In the event that column
addresses for the next cycle are valid at the time CAS goes high, access time for the next cycle is determined
by the later occurrence of tCAC or tCPA (access time from rising edge of CAS).
"'C
:xJ
address (AG-A 10)
o
Twenty-one address bits are required to decode 1 of 2097 152 storage cell locations. Eleven row-address bits
are set up on inputs AO through A 10 and latched onto the chip by the row-address strobe (RAS). The ten
column-address bits are set up on pins AO through A9 and latched onto the chip by the column-address strobe
(CAS). All addresses must be stable on or before the falling edges of RAS and CAS. RAS is similar to a chip
enable in that it activates the sense amplifiers as well as the row decoder. CAS is used as a chip select activating
the output buffer, as well as latching the address bits into the column-address buffer. .
C
C
o
-I
"'C
:xJ
write enable (W)
m
S
m
The read or write mode is selected through the write-enable 0N) input. A logic high on the W input selects the
read mode and a logic low selects the write mode. The write-enable terminal can be driven from standard TIL
circuits without a pullup resistor. The data input is disabled when the read mode is selected. When W goes low
prior to CAS (early write), data out will remain in the high-impedance state for the entire cycle permitting a write
operation independent of the state of OE. This permits early write operation to be completed with OE grounded.
:E
data In/out (DOG-DO?)
The three-state output buffer provides direct TIL compatibility (no pull up resistor required) with a fanout of two
Series 74 TIL loads. Data out is the same polarity as data in. The outputis in the high-impedance (floating) state
until CAS and OE are brought low. In a read cycle the output becomes valid after all access times are satisfied.
The output remains valid while CAS and OE are low. CAS pr OE going high returns it to a high-impedance state.
This is accomplished by bringing OE high prior to applying data, thus satisfying tOED,
TEXAS
~
INSTRUMENTS
4-480
POST OFFICE BOX 1443· HOUSTON, TEXAS 77001
TMS427800, TMS427800P
2097152 WORD BY 8·BIT
LOW VOLTAGE DYNAMIC RANDOM·ACCESS MEMORIES
SMKS278-JANUARY 1993
output enable (OE)
OE controls the impedance ofthe output buffers. When OE is high, the buffers will remain in the high-impedance
state. Bringing OE low during a normal cycle will activate the output buffers putting them in the low-impedance
state. It is necessary for both RAS and CAS to be brought low for the output buffers to go into the low-impedance
state, they will remain in the low-impedance state until either OE or CAS is brought high.
refresh
A refresh operation must be performed at least once every 32 milliseconds (256 ms for TMS427800P) to retain
data. This can be achieved by strobing each of the 4096 rows (AO--A 10). A normal read or write cycle will refresh
all bits in each row that is selected. A RAS-only operation can be used by holding CAS atthe high (inactive) level,
thus conserving power as the output buffer remains in the high-impedance state. Externally generated
addresses must be used for a RAS-only refresh.
hidden refresh
Hidden refresh may be performed while maintaining valid data at the output pin. This is accomplished by holding
CAS at VIL after a read operation and cycling RAS after a specified precharge period, similar to a RAS-only
refresh cycle.
CAS-before-RAS refresh
CAS-before-RAS (CBR) refresh is utilized by bringing CAS low earlier than RAS (see parameter teSR) and
holding it low after RAS falls (see parameter tCHR)' For successive CAS-before-RAS refresh cycles,
CAS can remain low while cycling HAS. The external address is ignored and the refresh address is generated
internally.
A low-power battery-backup refresh mode that requires less than 100 ~ refresh current is available on the
TMS427800P. Data integrity is maintained using CAS-before-RAS refresh with a period of 125 (.!S, while holding
RAS low for less than 1 (.!S. To minimize current consumption, all input levels need to be at CMOS levels
(VIL s 0.2 V, VIH .. Vce - 0.2 V).
self refresh (TMS427800P)
The self-refresh mode is entered by dropping CAS low prior to RAS going low. Then CAS and RAS are both
held low for a minimum of 100 (.!S. The chip is then refreshed by an on-board oscillator. No external address is
required since the CBR counter is used to keep track of the address. To exit the self-refresh mode, both RAS
and CAS are brought high to satisfy tCHS' Upon exiting self-refresh mode, a burst refresh (refresh a full set of
row addresses) must be executed before continuing with normal operation. The burst refresh ensures the
DRAM is fully refreshed.
power up
To achieve proper device operation, an initial pause of 200
required after power-up to the full VCC level.
(.!S
followed by a minimum of eight RAS cycles is
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
4-481
->==
W
w
c..
a::
t-
O
::J
C
o
a::
c..
TMS427800, TMS427800P
2 097 152 WORD BY 8·BIT
LOW VOLTAGE DYNAMIC RANDOM·ACCESS MEMORIES
SMKS278-JANUARY 1993
logic symbol t
RAM2Mx8
AO 10
AI 11
A2 12
20010/2100
A3 13
A4 16
A5
17
0
;> A 2 097 151
A6 18
A7 19
A8 20
21
A9
Al0 9
"tI
RAS
lJ
7
0
C
C
CAS 23
(")
w
-t
"tI
OE
lJ
6
20019/2109
20020
~
f> C20[ROW]
f
f>
G23/[REFRESH ROW]
24[PWROWN]
C21[COL]
G24
&
r
22
/
23,210
"-
I>
23C22
i>
24,25EN
G25
..,
m
m
2
:$
OQO
~
OQl 3
OQ2 4
4-
OQ3 5
OQ4 24
OQ5 25
OQ6 26
r
A,220
V26
.....
...
.....
~
~
OQ7 27
t This symbol is in accordance with ANSI/IEEE Std 91·1984 and lEe Publication 617·12.
The pin numbers shown correspond to the DZ package.
TEXAS ~
INSTRUMENTS
4·482
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
A,Z26-
TMS427800, TMS427800P
2097152 WORD BY 8·BIT
LOW VOLTAGE DYNAMIC RANDOM·ACCESS MEMORIES
functional block diagram
I
t
AO
2
I
,,,,
Timing and Control
8
32
Column Decode
A1
•
•
•
A9
Column
Address
Buffers
256KArray
•
•
2
256K Array
256KArray
32
Row
Address
Buffers
\-/-
Sense Amplifiers
L
•
SMKS276-JANUARY 1993
•
•
·
256KArray
II
'8u
II
Q
~
11
•
•
·
!C
32
I/O
Buffers
80132
Selection
a:
'-'--
256KArray
A10
11
/
~
~
In
Reg.
Out
Reg.
256K Array
000-007
I
~
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage range on any pin (see Note 1) ....................................... - O.S V to 4.6 V
Supply voltage range on Vee ...................................................... - O.S V to 4.6 V
Short circuit output current ................................................................ SO mA
Power dissipation .......................................................................... 1 W
Operating free-air temperature range .................................................. O°C to 70·C
Storage temperature range ....................................................... - SS·C to 12S·C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. This is a stress rating only, and
functional operation of the device at these or any other conditions beyond those indicated in the "recommended operating conditions" section of
this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values in this data sheet are with respect to VSS.
recommended operating conditions
MIN
NOM
MAX
Vee
Supply voltage
3
3.3
3.6
UNIT
V
VIH
High-level input voltage
2
Vee+ O.3
V
VIL
LOW-level input voltage (see Note 2)
-0.3
0.8
V
TA
Operating free-air temperature
0
70
·e
NOTE 2: The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used in this data sheet for logic
voHage levels only.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
4-483
w
5>
w
a:
a.
I-
o
:::J
C
o
a:
a.
TMS427800, TMS427800P
2097152 WORD BY 8·BIT
LOW VOLTAGE DYNAMIC RANDOM·ACCESS MEMORIES
SMKS278-JANUARY 1993
electrical characteristics over full ranges of recommended operating conditions (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
,
VOH
High-level output
voltage
10H :-2 mA
VOL
Low-level output
voltage
IOL:2 mA
VOH
Option
10H :-100 ~A
VOL
Option
10L = +100!,A '.
II
Input current (leakage)
2.4
0.4
UNIT
MAX
V
0.2
V
Vce = 3.6 V, VI = 0 to 3.9 V,
All other pins = a to VCC
±10
±10
!!A
10
Output current
(leakage)
VCC = 3.6 V, Va = a to VCC,
CAS high
±10
±10
!!A
ICCl t
Read or write cycle
current (see Note 3)
VCC : 3.6 V, Minimum cycle
115
105
mA
1
1
mA
'427800
300
300
!!A
'427800P
100
100
!!A
VCC-0.2
After 1 memory cycle,
RAS and CAS high,
VIH = 2 V (LVTTL)
ICC2
Standby current
c:
o-I
VIH = VCC-0.2 V
(CMOS),
After 1 memory cycle,
RAS and CAS high
V
VCC-0.2
ICC3
Average refresh
current (RAS-only or
CBR) (see Note 3)
VCC = 3.6 V, Minimum cycle,
RAS cycling, CAS high,
(RAS-only); RAS low
after CAS low (CBR)
115
105
mA
ICC4 t
Average page current
(see Note 4)
VCC = 3.6 V, tpc = Minimum,
RAS low, CAS cycling
115
105
mA
ICC6:j:
Self refresh current
CAS" 0.2 V, RAS < 0.2 V,
Measured after tRASS minimum
100
100
!,A
ICC7 t
Standby current,
outputs enabled
RAS = VIH, CAS = VIL
Data out = Enabled
5
5
mA
ICCIO:j:
Battery backup
operating current
(equivalent refresh
time is 256 ms)
CBR only
tRC = 125 !'S, tRAS " 1 !,S,
VCC-0.2 V" VIH" 3.9 V,
a V " VIL" 0.2 V,
Vii and OE : VIH,
Address and Data stable
100
100
!!A
JJ
~
2.4
MIN
0.2
C
m
:S
m
MAX
V
JJ
"'C
MIN
TMS427800-80
TMS427800P-80
0.4
"'C
o
TMS427800-70
TMS427800P-70
t Measured with outputs open.
:j: For TMS427800P only.
NOTES: 3. Measured with a maximum of one address change while RAS = VIL.
4. Measured with a maximum of one address change while CAS = VIH.
TEXAS .",
INSTRUMENTS
4-484
POST OFFICE BOX 1443· HOUSTON. TEXAS 77001
TMS427800, TMS427800P
2 097 152 WORD BY 8·BIT
LOW VOLTAGE DYNAMIC RANDOM·ACCESS MEMORIES
SMKS278-JANUARY 1993
capacitance over recommended ranges of supply voltage and operating free-air temperature,
f = 1 MHz (see Note 5)
,
PARAMETER
MIN
TYP
MAX
UNIT
Ci(A)
Input capacitance, address inputs
5
Ci(OE)
Input capacitance, output enable
7
pF
pF
Ci(RC)
Input capacitance, strobe inputs
7
pF
Ci(W)
Input capacitance, write-enable input
7
pF
Co
Output capacitance
7
pF
NOTE 5: VCC equal to 3,3 V ± 0,3 V and the bias on pins under test is 0 V,
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature
TMS427800·70
TMS427800P·70
PARAMETER
MIN
tM
Access time from column-address
MAX
TMS427800·80
TMS427800P-80
MIN
UNIT
MAX
35
40
ns
ns
tCAC
Access time from CAS low
18
20
tCPA
Access time from column precharge
40
45
ns
tRAC
Access time from RAS low
70
80
ns
tOEA
Access time from OE low
20
ns
tCLZ
CAS to output in low Z
0
0
ns
tOH
Output disable time, start of CAS high
3
3
ns
18
3
ns
tOHO
Output disable time, start of OE high
3
tOFF
Output disable time after CAS high (see Note 6)
0
18
0
20
ns
tOEZ
Output disable time after OE high (see Note 6)
0
18
0
20
ns
w
==
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w
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D.
t-
O
:J
C
NOTE 6: toFF and tOEZ are specified when the output is no longer driven.
o
a:
D.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443· HOUSTON, TEXAS 77001
4-485
TMS427800, TMS427800P
2 097 152 WORD BY 8·BIT
LOW VOLTAGE DYNAMIC RANDOM·ACCESS MEMORIES
SMKS278-JANUARY 1993
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
TMS427800-70
TMS427800P-70
PARAMETER
MIN
"o
:rJ
C
c:
o
-f
"m
:rJ
MAX
TMS427800-B0
TMS427800P-B0
MIN
UNIT
MAX
tRC
Random read or write cycle (see Note 7)
130
150
ns
tRWC
Read-modify-write cycle time
181
205
ns
tpc
Page-mode read or write cycle time (see Note 8)
45
50
ns
tPRWC
Page-mode read-modify-write cycle time
96
105
tRASP
Page-mode pulse duration, RAS low (see Note 9)
70
100000
80
100000
ns
tRAS
Non-page-mode pulse duration, RAS low (see Note 9)
70
10000
80
10000
ns
tCAS
Pulse duration, CAS low (see Note 10)
18
10000
20
10000
ns
tcp
Pulse duration, CAS high (CAS precharge)
10
10
ns
tRP
Pulse duration, RAS high (RAS precharge)
50
60
ns
twp
Write pulse duration
15
15
ns
tASC
Column-address setup time before CAS low
0
0
ns
tASR
Row-address setup time before RAS low
0
0
ns
ns
tDS
Data setup time (see Note 11)
0
0
ns
tRCS
Read setup time before CAS low
0
0
ns
tcWL
W low setup time before CAS high
18
20
ns
tRWL
W low setup time before RAS high
18
20
ns
twcs
W low setup time before CAS low
(Early wrne operation only)
0
0
ns
NOTES:
S
m
:e
=
7. All cycle times assume IT 5 ns.
8. To assure tpc min, tASC should be greater than or equal to tcp.
9. In a read-modify-write cycle, tRWD and tRWL must be observed. Depending on the user's transition times, this may require additional
RAS low time (tRAS).
10. In a read-modify-write cycle, tCWD and tCWL must be observed. Depending on the user's transition times, this may require additional
CAS low time (tCAS).
11. Referenced to the later of CAS or Win write operations.
TEXAS ."
INSTRUMENTS
4-486
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
TMS427800, TMS427800P
2097152 WORD BY 8·BIT
LOW VOLTAGE DYNAMIC RANDOM·ACCESS MEMORIES
SMKS278-JANUARY 1993
timing requirements over recommended ranges of supply voltage and operating free·air
temperature (continued)
TMS427800-70
TMS427800P-70
PARAMETER
MIN
MAX
TMS427800-80
TMS427800P-S0
MIN
UNIT
MAX
tCAH
Column-address hold time after CAS low
15
15
ns
tDH
Data hold time (see Note 11)
15
15
ns
tRAH
Row-address hold time after RAS low
10
10
ns
tRCH
Read hold time after CAS high (see Note 12)
0
0
ns
tRRH
Read hold time after RAS high (see Note 12)
5
5
ns
twCH
Write hold time after CAS low
(Early write operation only)
15
15
ns
tAWD
Delay time, column address to W low
(Read-modify-write operation only)
63
70
ns
tCHR
Delay time, RAS low to CAS high
(CAS-before-RAS refresh only)
20
20
ns
tCRP
Delay time, CAS high to RAS low
5
5
ns
tCSH
Delay time, RAS low to CAS high
70
80
ns
tCSR
Delay time, CAS low to RAS low
(CAS-before-RAS refresh only)
10
10
ns
tCWD
Delay time, CAS low to W low
(Read-modify-write operation only)
46
50
ns
tOEH
OE command hold time
18
20
ns
tOED
OE to data delay
18
20
ns
tROH
RAS hold time referenced to OE
10
10
ns
tRAD
Delay time, RAS low to column-address (see Note 13)
15
tRAl
Delay time, column-address to RAS high
35
tCAl
Delay time, column address to CAS high
35
tRCD
Delay time, RAS low to CAS low (see Note 13)
20
tRPC
Delay time, RAS high to CAS low
0
0
ns
tRSH
Delay time, CAS low to RAS high
18
20
ns
tRWD
Delay time, RAS low to W low
(Read-modify-write operation only)
98
110
ns
tcpw
Delay time, W from CAS precharge
68
75
ns
tCPRH
Hold time, RAS from CAS precharge
40
45
ns
35
15
40
40
ns
40
52
20
ns
ns
60
ns
NOTES: 11. Referenced to the later of CAS or W in write operations.
12. Either tRRH or tRCH must be satisfied for a read cycle.
13. The maximum value is specified only to assure access time.
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443· HOUSTON. TEXAS 77001
4-487
::w
:>
w
a:
a.
I-
U
::J
C
o
a:
a.
TMS427800, TMS427800P
2 097 152 WORD BY 8·BIT
LOW VOLTAGE DYNAMIC RANDOM·ACCESS MEMORIES
SMKS276-JANUARY 1993
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (concluded)
TMS427S00-70
TMS427S00P-70
PARAMETER
MIN
MAX
TMS427S00-S0
TMS427S00P-80
MIN
UNIT
MAX
tcPR
CAS precharge before self refresh
0
0
ns
tRPS
RAS precharge after self refresh
130
150
ns
tRASS
Self refresh entry from RAS low
100
100
~s
tcHS
CAS low hold time after RAS high (self-refresh)
-50
-50
ns
tREF
Refresh time interval (TMS427800)
tREF
Refresh time interval Low power (TMS427800P only)
IT
Transition time
3
32
32
ms
256
256
ms
30
ns
30
3
PARAMETER MEASUREMENT INFORMATION
1.4V
"tJ
VCC = 3.3V
:c
o
RL
c
o
c:
= 500 Q
R1 = 1178 Q
Output Under Test - - - -....
Output Under Test
CL=100pF
-I
"tJ
:c
m
S
m
(b) Alternate Load Circuit
(a) Load Circuit
Figure 1. Load Circuits for Timing Parameters
~
TEXAS . "
iNsrRUMENTS
4-488
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
TMS427800, TMS427800P
2 097 152 WORD BY 8·BIT
LOW VOLTAGE DYNAMIC RANDOM·ACCESS MEMORIES
SMKS278--JANUARY 1993
PARAMETER MEASUREMENT INFORMATION
~
~C
---.i.N
-J
RAS
~
'!\I
YT
I
IRAS
I
I I
1...-_ _ _ __
I I4-IRP~
I I...
ICSH
.1
I I
I
I ~IRCO~
I
I
I
I :
I...
IRSH~ !
I
I I
I
I ~ ICRP ----+I
I I
N~'CAS41. I
1\1
~IASR
I.
1! I
!\
I
I...
.1 IRAO [ !
I 1.....,1-:----- ICp _ _ _
I
I
I"'~ IASC
11I
I -.I
I
1
I 1I
RAi'"
1 ICAL
.1 1 I
I
I
:
I I
I'"
1
1 1.1
~....
·1
"
-.!.: '-----
i
s:w
AO-A10
1
I
I
I
1
II
II
I
1
i+-
ICAH
I
I
I+-IRRH
I
.1
:>w
IRCH
c:::
0.
....
o
::J
C
o
c:::
0.
NOTE A: Output may go from a high·impedance state to an invalid data state prior to the specified access time.
Figure 2. Read Cycle Timing
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
4·489
TMS427800, TMS427800P
2 097 152 WORD BY 8·BIT
LOW VOLTAGE DYNAMIC RANDOM·ACCESS MEMORIES
SMKS276-JANUARY 1993
PARAMETER MEASUREMENT INFORMATION
"'C
JJ
o
C
C
o-I
"'C
JJ
m
m
<
~
Figure 3. Early Write Cycle Timing
TEXAS ~
INSTRUMENTS
4-490
POST OFFICE BOX 1443· HOUSTON, TEXAS 77001
TMS427800, TMS427800P
2097152 WORD BY 8·BIT
LOW VOLTAGE DYNAMIC RANDOM·ACCESS MEMORIES
SMKS278-JANUARY 1993
PARAMETER MEASUREMENT INFORMATION
~1"r-----------------------tRC----------------------~.1
I
I
RAS
1
I"
tRAS
--~N
ltf-----tRP
t,. ~ 141 ~
1 1
11
1 14
CAS
--+I
1
I"
.1
I..
tRCD
1
I..
~
1
I..
1
1
::
1 1
tRAH~
1 1
~
i..
} ;r~II"+!I--------~~
f ;...~--- tcp ------t~
r
tCAl.
• :
1 tRAl.
1
~tCAH
A
w
..
1
~tRAD -.I
I
a:
1
I"
tRWl.
W~~~*Rf~~
.1
. ~~~"""""""k~n"""""""t~"""""""'*~"""""""''''''''''
~i+-tDS~
1
DQO-DQ7~R~*RX!~
tOED~
I
tWP-+i
~
(see Note A l i i
..........
~tDH--':
~*g'0r~
1
~1"-------tOEH--------~·1
NOTE A: Referenced to the later of CAS or VIi in write operations.
Figure 4. Write Cycle Timing
TEXAS ~
INSTRUMENTS .
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
t-
O
:::J
C
(see Note Al
vailidData
0..
4-491
oa:
0..
TMS427800, TMS427800P
2 097 152 WORD BY 8·BIT
LOW VOLTAGE DYNAMIC RANDOM·ACCESS MEMORIES
SMKS276-JANUARY 1993
PARAMETER MEASUREMENT INFORMATION
CAS
-.I
I
I
I
I
AO-A10229(
"'C
JJ
o
C
C
o
-I
"'C
JJ
m
S
m
~
NOTE A: Output may go from a high-impedance state to an invalid data state prior to the specified access time.
Figure 5. Read-Modify-Write Cycle Timing
TEXAS ~
INSTRUMENTS
4-492
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
TMS427800, TMS427800P
2 097 152 WORD BY 8·BIT
LOW VOLTAGE DYNAMIC RANDOM·ACCESS MEMORIES
SMKS278-JANUARY 1993
PARAMETER MEASUREMENT INFORMATION
tRP
__________________~~
14
I
.1
I
~-------tCPRH-------4~
~--------------------~--------~~~-------I I
-------.~I+__ tCRP
I
I
---+I
I
1 4 - - - tCAl - - - . ,
~------tRAl--~~--~
m-."'!"-",.,..,...,..,..,,..,...,..,.
Column
AO-A10
&
+
I
tRCS
I
:
I 14
tAA
(see Note A)
tRRH
-+I
~ tRCH -----.I
3:
w
5>
w
a:
c.
t-
O
::l
C
o
NOTES: A. Access time is tCPA or 1M dependent.
B. Output may go from a high-impedance state to an invalid data slate prior to the specified access time.
C. A write cycle or read-modify-write cycle can be intermixed with the read cycles as long as the write and read-modify-write timing
specifications are not violated.
Figure 6. Enhanced Page-Mode Read Cycle Timing
TEXAS ~.
INSTRUMENTS
POST OFFICE BOX 1443· HOUSTON. TEXAS 77001
4-493
a:
c.
TMS427800, TMS427800P
2097152 WORD BY 8·BIT
LOW VOLTAGE DYNAMIC RANDOM·ACCESS MEMORIES
SMKS278-JANUARY 1993
PARAMETER MEASUREMENT INFORMATION
loiii
tRP
I'll
T\i~
I"
: 1;I
.1
tCSH
I 14---1 tRCD ---..I
14- tCAS
tASC~\l
-.! I I I
:
I
r+
I
~I
tRASP
tRAH
I
1+--+1-1 tASR
II
I I
I
I I
I I
I '--
i+- tCRP ---.!
~ tRSH ~
;.-1_ - tl _ _ _ __
I
I:
N
.0
I
I
[4-tcp--.j
r.- tCAH -l+I
..ko----ii.-..---1
f
.I
tpc
...r
I
I
II
I
I
I I
I
!;
I
~~
tCPRH
I I
I
I I
.1
I..
I
I I
I
.1
I
tRAL
l....-tCAL
AO-A10
I I
I I I
1"1 I
:xJ
o
o
-I
:xJ
m
m
,..
I
DQO-DQ7~
S
:e
I
.1
I
~ tRWL
I
----.r
I
twp
,,~m·-!I I i ~2MJ~
~~4mi2l8
I
i
C
C
"'CJ
tCWL~
,
~tCWL-.j
"'0
tDS
: .1
r.-tDH
(see Note A)
.........:
*- tOEH ~
I
~ V~~ld _~J~~~2S
Valid Data In
I+- tOEH
OE
I
I
-.r
tOED -+I
~H*XeW
I+-
I
~~t0f222
NOTES: A. Referenced to the later of CAS or IN in write operations.
B. A read cycle or a read-modify-write cycle can be intermixed with the write cycles as long as the read and read-modify-write timing
specifications are not violated.
Figure 7. Enhanced Page-Mode Write Cycle Timing
TEXAS ~
INSfRUMENTS
4-494
POST OFFICE BOX 1443· HOUSTON. TEXAS 77001
TMS427800, TMS427800P
2097152 WORD BY 8·BIT
LOW VOLTAGE DYNAMIC RANDOM·ACCESS MEMORIES
SMKS278--JANUARY 1993
PARAMETER MEASUREMENT INFORMATION
tRP--+J
RAS ~
I I
II I..
I
~
I
t~AD
!
1
I
I"
0
I I"
tPRWC
tRCD
4- --.t N--t.+
tASR
I
I..
I
.,.1..f - - - - - - t C P R H
.1 1
tCSH
I I
CAS
~
tRASP------------~
z...-.......
tCAS
1
I
tcp
CRP
'{
----..I
I
I
I
..t
I" I
....
1 +1___
t
I
I
I
.11 I
t
I
141
..- - - - tRSH -----.t.1
~~
~
tASC
II I
I
.1
_ _ _ _ _...1
II :I
I
I
I
I
CAH"I
AO-A10
3:
UJ
:>
UJ
a:
Il.
t-
O
::J
C
DQO-DQ7--------------~)~
I I. 1
tCLZ ---+i ~
I
~ tOEA ---.I I
I
I
tOEZ~I+-:
I
II
I
I
tOHO ~ I j+/4- tOEH
OE~
o
a:
I......-~ tOED
I
Il.
:
+l
I
I
y~------~~~----~~~~~~
NOTES: A. Output may go from a high-impedance state to an invalid data state prior to the specified access time.
B. A read or write cycle can be intermixed with read-modify-write cycles as long as the read and write timing specifications are not
violated.
Figure 8. Enhanced Page-Mode Read-Modify-Write Cycle Timing
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
4-495
TMS427800, TMS427800P
2 097 152 WORD BY 8·BIT
LOW VOLTAGE DYNAMIC RANDOM·ACCESS MEMORIES
SMKS278-JANUARY 1993
PARAMETER MEASUREMENT INFORMATION
"'C
:IJ
o
OQO-OQ7 - - - - - - - - - - - - - - H I - Z - - - - - - - - - - - - - -
C
c:
o
-t
Figure 9. RAS-Only Refresh Timing
"'C
:IJ
m
m
<
-
:e
TEXAS ~
INsrRUMENTS
4-496
POST OFFICE BOX 1443' HOUSTON, TEXAS nOOl
TMS427800, TMS427800P
2097152 WORD BY 8·BIT
LOW VOLTAGE DYNAMIC RANDOM·ACCESS MEMORIES
SMKS27!hJANUARY 1993
PARAMETER MEASUREMENT INFORMATION
~1~-------------------tRC------------------~~1
~ tRP ~ ~I"____________ tRAS ------------~~I 1
1
I I
I ;,-1_ _ __
ANY
RAS
1
tRPC
CAS
-.I
J+- tCSR -.:
~
\J..
I
I ~:
.. - - - - t C H R ---~.I
~ ~
Y
tT
3:
w
0 0 0 - 0 0 7 - - - - - - - - - - - - - - HI-Z - - - - - - - - - - - - -
:>w
a:
a.
Figure 10. Automatic (CAS-Before-RAS) Refresh Cycle Timing
lt)
::J
C
o
a:
a.
TEXAS ~
INsrRUMENTS
POST OFFICE BOX 1443' HOUSTON, TEXAS 77001,
4-497
TMS427800, TMS427800P
2 097 152 WORD BY 8·BIT
LOW VOLTAGE DYNAMIC RANDOM·ACCESS MEMORIES
SMKS27&-JANUARY 1993
PARAMETER MEASUREMENT INFORMATION
t+-- Refresh Cycle -+1
t+-- Refresh Cycle ~
i+-- Memory Cycle ~
I
1
I~
~I
~I
I....
1
I+- tRP -+I
I j+tRAS+J1
I
I
1 itRAS},Ie
RAS~
I :
l\ J!
Y
::
I
1 I
II
~li'4I-tCAH
: i-+I ~tASC
I I I I
tRAHtij'41 III
1
I
1
/~
I 14
~I
\
I :
~
::
tRP
I
((:!:vri
tCHR
tCAS
I I
II
I I
I
II
1
jJ
tASR:~~~
"'CJ
tRCS
I I I
1.1 I
II
I
I
I
~
~~*)2%~~~
I I~
I+-tCAC
I 14 I .1 tAA
1 _
~~~
OQG-OQ7
(see Note A)
tClZ
m
<
m
~
Valid Data
out~:
--.I ~
'/,
NOTE A: Output may go from a high-impedance state to an invalid data state prior to the specified access time.
Figure 11. Hidden Refresh Cycle (Read)
TEXAS
~
INSfRUMENTS
4-498
~~r
}-
I----t-OE-Z-~--'!~
OE"l':~~~~r---*-tOEA
-
:E
I
14 I
~III
wiii
: ::
"""'i
"'CJ
I
I
I
I
I
--" ~~iXWXYXi)6&iXiXwXYX'JHR·X.~~
:a
o
c
c:
o
:a
I
II
I I
I
II
POST OFFICE BOX 1443· HOUSTON. TEXAS 77001
~
TMS427800, TMS427800P
2 097 152 WORD BY 8-BIT
LOW VOLTAGE DYNAMIC RANDOM-ACCESS MEMORIES
SMKS27lhJANUARY 1993
PARAMETER MEASUREMENT INFORMATION
~
w
:>
w
a::
c..
tO
~
C
o
a::
c..
NOTE A: Referenced to the later of CAS or Win write operations.
Figure 12. Hidden Refresh Cycle (Write)
TEXAS ~
INsrRUMENTS
POST OFFICE BOX 1443· HOUSTON. TEXAS 77001
4·499
TMS427800, TMS427800P
2 097 152 WORD BY 8-BIT
LOW VOLTAGE DYNAMIC RANDOM-ACCESS MEMORIES
SMKS278-JANUARY 1993
PARAMETER MEASUREMENT INFORMATION
141
..- - - - - tRASS - - - - + 1
.. 1
1
N
fi
_ _- - J
1
tRPC
I"
1
"I
tcsR
~
1
~
j+ tRPS ~
1
~
--I+i
1
~
I
1
--.A~I-~N
1
1
~
_ _ _ _ _ _ _ _ _.J 1
~tCHS
~~~~
1
j+-tCPR ~
AG-A10
W~*m~
"oJl
0'
C
~2§QmQ0mm~
*~~-----+i
C
~
"Sm
~:grr£~
DQG-DQ7
tOFF
_ _ _ _ _ _ HI-Z _ _ _ _- - - - - - - -
Figure 13. Self Refresh Timing
Jl
device symbolization
m
:e
t~
TI
P
TMS427BOO
W
~
A
P
Speed ( -70, -BO)
Low Power/Refresh Option
Package Code
T
!:!f=
Lot Traceability Code
Date Code
Aasembly Site Code
Ole Revision Code
Wafer Fab Code
TEXAS ~
INsrRUMENTS
4-500
POST OFFICE BOX 1443· HOUSTON, TEXAS 77001
16777216 BIT SYNCHRONOUS
DYNAMIC RANDOM-ACCESS MEMORY
SMOS682-JANUARY 1993
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Organization ... 1M x 8 x 2 Banks
3.3 V-Power Supply (10% Tolerance)
Two Banks For On-Chip Interleaving
(Gapless Accesses)
High Bandwidth - Up to 100-MHz Data
Rates
Burst Length Programmable to 1, 2, 4, or 8
Programmable Output Sequence - Serial or
Interleave
Chip Select and Clock Enable For
Enhanced System Interfacing
Cycle-By-Cycle DQ Bus Mask Capability
Programmable Read Latency From Column
Address
Self-Refresh Capability
High-Speed, Low-Noise LVTTL and GTL
Interfaces (SPICE Models Available)
Interface Type (LVTTL or GTL)
Automatically Sensed and Provided
Power-Down Mode
Compatible With JEDEC Standards
4K Refresh (Total For Both Banks)
Performance Ranges:
DGE PACKAGEt
(TOP VIEW)
VCC
DOO
Vsso
D01
VccoNsso*
D02
Vsso
D03
VccoNsso*
NC
NC
IN
VSS
DO?
Vsso
D06
VccoNsso*
D05
Vsso
D04
VccoNsso*
NCNREF*
NC
DOM
CAS
ClK
RAS
CKE
CS
NC
A11
A9
A10
A8
AO
A?
A1
A6
A2
A5
A3
A4
Vcc
3:
w
:>w
a:
a.
Vss
ACTV
SYNCHRONOUS
COMMAND TO
CLOCK CYCLE
READORWRT
REFRESH
TIME
TIME
COMMAND
INTERVAL
ICK
(MIN)
IRCD
(MIN)
IREF
(MAX)
SDRAM-10
10
ns
30 ns
64 ms
SDRAM-12
12.5 ns
35 ns
64 ms
SDRAM-15
15
40 ns
64 ms
ns
t Package is shown for pinout reference only.
* Pins 5, 9,36, and 40 must be connected to VCCO and pin 35 must
remain open (unconnected) for lVTTl Interface Operation.
Pins 5,9, 36, and 40 must be connected to VSSO and pin 35 must
be connected to VREF for GTl Interface Operation.
PIN NOMENCLATURE
ClK
CS
CKE
description
The Texas Instruments synchronous DRAM
devices are high-speed 16 777 216-bit
synchronous dynamic random-access memories,
each organized as 2 banks of 1 048 576-words
with 8-bits per word. The synchronous DRAM
employs state-of-the-art EPIC'· (Enhanced
Performance Implanted CMOS) technology for
high performance, reliability, and low power at low
cost.
All inputs and outputs are synchronized with the
ClK input to simplify system design and enhance
use with high-speed microprocessors and
caches.
The synchronous DRAM series is
DaM
A11
AD-A10
RAS
CAS
IN
DOO-DO?
VCC
VSS
VCCO
VSSO
VREF
NC
System Clock
Chip Select
Clock Enable
Data/Output Enable
Bank Select
Address Inputs
AD-A10 Row Addresses
AD-A8 Column Addresses
A 10 Automatic Precharge Select
Row Address Strobe
Column Address Strobe
Write Enable
SDRAM Data Inputs/Outputs
Power Supply (3.3 V Typ)
Ground
Power Supply for Output Drivers
(3.3 V Typ)
Ground for Output Drivers
GTL Reference Voltage
No External Connect
EPIC is a trademark of Texas Instruments Incorporated.
PRODUCT PREVIEW Information concern. products in the form,lIve or
d"lgn ph... of development Ch.'lct.rllUc data Ind other
lpecJflCltlonl Ire desIGn g011i. Texa.ln,trumentl flArYtI th, rtght to
ch.nge 01 dllconllnuelh,.. prodUN without notice.
TEXAS
~
Copyright © 1993. Texas Instruments Incorporated
INSTRUMENTS
POST OFFICE BOX 1443' HOUSTON. TEXAS neel
4-501
Io::J
C
0
a:
a.
16777 216 BIT SYNCHRONOUS
DYNAMIC RANDOM-ACCESS MEMORY
SMOS682-JANUARY 1993
compatible with both low Voltage TTL (lVTTl) and Gunning Tranceiver logic (GTl) input/output levels, by
automatically sensing the interface arrangement and internally enabling the corresponding set of I/O drivers.
These synchronous DRAMs are available in a variety of frequency performance ranges.
The synchronous DRAMs are available in a 400-mil. 44-pin surface mount TSOP II package (DGE suffix).
operation
All inputs of the synchronous DRAM are latched on the rising edge of the system (synchronous) clock. The
synchronous DRAM outputs, DQO-DQ7, are also referenced to the rising edge of ClK. The synchronous
DRAM has two banks which are accessed independently. A bank must be activated before it can be accessed
(read from or written to). Refresh cycles will refresh both banks alternately.
Five
-
basic commands or functions control most operations of the synchronous DRAM:
Bank activate/row address entry
Column address entry/write operation
Column address entry/read operation
Bank deactivate
CAS-before RAS / self-refresh entry
Additionally, operation of the synchronous DRAM may be controlled by three methods: using chip select (CS)
to select/deselect the device; using DQM to enable/mask the DQ signals on a cycle-by-cycle basis; or using CKE
to suspend (or gate) the ClK input. The device contains a mode register that must be programmed for proper
operation. Refer to the following truth tables (Tables 1 through 3).
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~
TEXAS ~
IN5rRUMENTS
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POST OFFICE BOX 1443· HOUSTON, TEXAS nOOl
16777216 BIT SYNCHRONOUS
DYNAMIC RANDOM·ACCESS MEMORY
SMOS682-JANUARY 1993
Table 1. Basic Command Truth Tablet
COMMAND
STATE OF
BANK(S)
CS
RAS
CAS
W
A11
A1D
A9-AD
MNEMONIC
MRS
MRR
Mode register set
t = deac
b = deac
L
L
L
L
X
X
A9=X
A8=0
A7=0
A6=A5=X
Mode register read
t = deac
b = deac
L
L
L
L
X
X
A9=X
A8=1
A7=0
A6=A5=X
Bank deactivate (precharge)
X
L
L
H
L
BS
L
X
DEAC
Deactivate all banks
X
L
L
H
L
X
H
X
DCAB
Bank activate/row address entry
SB = deac
L
L
H
H
BS
V
V
ACTV
Column address entry/write operation
SB = actv
L
H
L
L
BS
L
V
WRT
Column address entry/write operation
with auto-deactivate
SB = actv
L
H
L
L
BS
H
V
WRT-P
Column address entry/read operation
SB = actv
L
H
L
H
BS
L
V
READ
Column address entry/read operation
with auto-deactivate
SB = actv
L
H
L
H
BS
H
V
READ-P
Burst stop
-
L
H
H
L
X
X
X
STOP
No operation
X
L
H
H
H
X
X
X
NOOP
Control input inhibit/No operation
X
H
X
X
X
X
X
X
DESL
3:
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:;:
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t For execution of these commands on cycle n, CKE (n-1) must be high and CKE (n) and DaM (n) are don't cares.
a::
L = Logic low
H = Logic high
X = Don't care
V=Valid
t = Bank t
b = Bank b
actv = Activated
deac = Deactivated
BS = Logic high to select bank t; logic low to select bank b
SB = Bank selected by A 11 at cycle n
a...
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1993
Table 2. CKE·Use Command Truth Tablet
COMMAND
C
c:
o
-t
"'C
CS
(n)
RAS
(n)
CAS
(n)
(n)
MNEMONIC
X
L
L
X
X
X
X
-
H
L
L
l
L
H
SLFR
Power-down entry
t =b = no access§
operation
H
L
L
H
H
H
PDE
H
L
H
X
X
X
PDE
t =b = self·refresh!
power-down
L
H
L
H
H
H
-
L
H
H
X
X
X
-
ClK suspend at n+ I
t or b = access§
operation
H
L
X
X
X
X
HOLD
CLK suspend exit at n+ I
t or b = access§
operation
L
H
X
X
X
X
-
t=b=deac
H
H
L
L
L
H
REFR
CBR refresh:!:
o
W
CKE
(n)
t=b=deac
Self-refresh!power-down exit
"'C
CKE
(n-l)
Self-refresh entry:!:
Continue current operation
:D
STATE OF
BANK(S)
t For execution of these commands, AD-All (n) and DaM (n) are don't cares.
:!: CBR or self refresh entry requires that all banks be deactivated, or in an idle state prior to the command entry.
n = CLK cycle number
L= Logic low
H = logic high
X = Don't care
V=Valid
t = Bank t
b = Bank b
actv = Activated
deae = Deactivated
burst = Data-in or data out cycle in progress at cycle n+ I
§ An access operation refers to any READ (-P) or WRT (-P) command in progress at cycle n. Access operations include the cycle upon which
the READ (-P) or WRT (-P) command is entered and all subsequent cycles through the completion of the access burst.
:D
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TEXAS
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Table 3. DQM-Use Command Truth Tablet
STATE OF
BANK(S)
OQM
(n)
00-07
(n)
QO-Q7
(n+2)
MNEMONIC
-
t = deae
and
b = deac
X
N/A
HI-Z
-
-
t = actv
and
b = actv
(no bursts)
X
N/A
HI-Z
-
Data-in enable
t = write
or
b=write
l
V
N/A
ENBl
Data-i n mask
t=write
or
b=write
H
M
N/A
MASK
Data-out enable
t = read
or
b = read
l
N/A
V
ENBl
Data-out mask
t = read
or
b = read
H
N/A
HI-Z
MASK
COMMAND
t For execution of these commands, CKE (n-1) must be high and CKE (n) must be high. CS
(n). RAS (n), CAS (n), W (n). and AO-A11 (n) are
don't cares.
n = ClK cycle number
l = logic low
H = logic high
X = Don't care
V= Valid
M = Masked input data
N/A = Not applicable
t = Bank t
b = Bank b
actv = Activated with no read or write operation in progress.
deac = Deactivated
write = Activated and accepting data-in on cycle n
read = activated and delivering data-out on cycle n+2
3:
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TEXAS .."
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burst sequence
All data for the SDRAM is written or read in a burst fashion. That is, a single starting address is entered into the
device and then the SDRAM internally accesses a sequence of locations based on that starting address. Some
of the subsequent accesses after the first may be at preceding as well as succeeding column addresses
depending on the starting address entered. This sequence can be programmed to follow either a serial burst
or an interleave burst. Refer to the following tables. The length of the burst sequence can be user-programmed
to be either 1, 2, 4, or 8 accesses. After a read burst is completed (as determined by the programmed burst
length) the outputs will be placed in a high-impedance state (see note below) until the next read access is
initiated. Refer to the examples following the timing requirements and characteristics description (Figures 9
through 15).
NOTE: When using terminated DO buses for GTL interfacing. turning off the output buffers at the device will result in the DO lines pulling up to
the terminating voltage, Vn.
Table 4. 2-Bit Burst Sequences
INTERNAL COLUMN ADDRESS AD
DECIMAL
"'D
Serial
:a
o
c
Interleave
BINARY
START
2ND
START
0
1
1
0
0
. 1
2ND
0
1
0
1
1
0
1
0
1
0
c
n
Table 5. 4-Bit Burst Sequences
-I
INTERNAL COLUMN ADDRESS A 1 AD
"'D
DECIMAL
:a
m
<
-m
:E
Serial
Interleave
BINARY
START
2ND
3RD
4TH
START
2ND
3RD
0
1
2
3
00
01
10
11
1
2
3
0
01
10
11
00
2
3
0
1
10
11
00
01
3
0
1
2
11
00
01
10
0
1
2
3
00
01.
10
11
1
0
3
2
01
00
11
10
2
3
0
1
10
11
00
01
3
2
1
0
11
10
01
00
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Table 6. 8-Bit Burst Sequences
INTERNAL COLUMN ADDRESS A2 A1 AO
DECIMAL
BINARY
START
2ND
3RD
4TH
5TH
6TH
7TH
8TH
START
2ND
3RD
4TH
5TH
6TH
7TH
0
1
2
3
4
5
6
7
000
001
010
011
100
101
110
111
1
2
3
4
5
6
7
0
001
010
011
100
101
110
111
000
Serial
Interleave
8TH
2
3
4
5
6
7
0
1
010
011
100
101
110
111
000
001
3
4
5
6
7
0
1
2
011
100
101
110
111
000
001
010
4
5
6
7
0
1
2
3
100
101
110
111
000
001
010
011
5
6
7
0
1
2
3
4
101
110
111
000
001
010
011
100
6
7
0
1
2
3
4
5
110
111
000
001
010
011
100
101
7
0
1
2
3
4
5
6
111
000
001
010
011
100
101
110
0
1
2
3
4
5
6
7
000
001
010
011
100
101
110
111
1
0
3
2
5
4
7
6
001
000
011
010
101
100
111
110
101
2
3
0
1
6
7
4
5
010
011
000
001
110
111
100
3
2
1
0
7
6
5
4
011
010
001
000
111
110
101
100
4
5
6
7
0
1
2
3
100
101
110
111
000
001
010
011
5
4
7
6
1
0
3
2
101
100
111
110
001
000
011
010
6
7
4
5
2
3
0
1
110
111
100
101
010
011
000
001
7
6
5
4
3
2
1
0
111
110
101
100
011
010
001
000
:=w
->
w
a:
latency
The beginning data output cycle of a read burst may be be programmed to occur 1, 2, or 3 ClK cycles after the
read command. Refer to the set mode register description. This feature allows the user to adjust the
synchronous DRAM to operate in accordance with the system's capability to latch the data output from the
synchronous DRAM. The delay between the READ command and the beginning of the output burst is known
as read latency (also known as CAS latency). As described previously, after the initial output cycle has
commenced, the data burst will occur at the ClK frequency without any intervening gaps. Use of minimum read
latencies are restricted based on the particular maximum frequency rating of the synchronous DRAM.
There is no latency for data-in cycles (write latency). The first data-in cycle of a write burst is entered at the same
rising edge of ClK on which the WRT command is entered. Note that the write latency is fixed and not
determined by the mode register contents.
two-bank operation
The synchronous DRAM contains two independent banks, which can be accessed individually or in an
interleaved fashion. Each bank must be activated with a row address before it can be accessed. Each bank
must. then be deactivated before it can be activated again with a new row address. The bank activate/row
address entry command (ACTV) is entered by holding RAS low, CAS high, W high, and A11 valid on the rising
edge of ClK. A bank may be deactivated either automatically during a READ or a WRT command (READ-P
or WRT-P) or by use of the deactivate banks (DEAC) command. Both banks may be deactivated at once by use
of the DCAB command. Refer to Table 1 and the following bank deactivation description.
The availability of two banks allows enhanced performance and a wider variety of possible combinations and
methods of data access for the user to choose from, based on the system needs.
TEXAS ~
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D..
t-
O
::l
C
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a:
D..
16777 216 BIT SYNCHRONOUS
DYNAMIC RANDOM-ACCESS MEMORY
SMOS682-JANUARY 1993
two-bank row access operation
The two-bank feature allows the user to access information on random rows at a higher rate of operation than
is possible with a standard DRAM. This may be accomplished by activating one bank with a row address as
described previously. Then, while the data stream is being accessed to/from that bank, the second bank can
be activated with another row address. When the data stream to/from the first bank is complete, the data stream
to/from the second bank can commence without interruption. After the second bank is activated, the first bank
could be deactivated to allow the entry of of new row address for the next round of accesses. In this manner,
operation could continue on in an interleaved "ping-pong" fashion. Refer to the examples following the timing
requirements and characteristics description. (Refer Figures 9 through 15.)
two-bank column access operation
The availability of two banks also allows the user to access data from random starting columns between banks
at a higher rate of operation. After activating each bank with a row address (ACTV command), the user can use
A 11 to alternate READ or WRT commands between the banks to provide gapless accesses at the ClK
frequency, provided all specified timing requirements are met. Refer to the examples following the timing
requirements and characteristics description. (Refer Figures 9 through 15.)
bank deactivation (precharge)
."
Both banks may be simultaneously deactivated (placed in precharge) by use ofthe DCAB command. The DCAB
command is entered by holding RAS low, CAS high, W low, and A 10 high on the rising edge of ClK. A single
bank may be deactivated by use ofthe DEAC command. The DEAC command is entered identically to the DCAB
command except that A 10 must be low and A 11 will select the bank to be precharged. A bank may also be
deactivated automatically by use of A 10 during a READ or WRT command. If A 10 is held high during the entry
of a READ or WRT command, then the accessed bank (selected by A 11) will automatically be deactivated upon
completion of the access burst. If A 10 is held low during READ or WRT command entry then that bank will remain
active following the burst. The READ and WRT commands with automatic deactivation are denoted READ-P
and WRT-P. Refer to Table 1 .
lJ
o
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C
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m
S
m
chip select
CS, or chip select, can be used to select or deselect the synchronous DRAM for command entry, such as might
be required for multiple memory device decoding. If CS is held high on the riSing edge of ClK, (DESl command)
the device will not respond to RAS, CAS, or W input until the device is selected again. Device select is
accomplished by holding CS low on the rising edge of ClK. Any other valid command may be entered
simultaneously on the same rising ClK edge of the select operation. The device may be selected/deselected
on a cycle-by-cycle basis. (Refer to Table 1 and Table 2.) Note that use of CS will not affect an access burst that
is in progress; the DESl command can only restrict RAS, CAS, and W input to the SDRAM.
:e
data/output mask
Masking of individual data cycles within a burst sequence may be accomplished by use of the MASK..command
(see Table 3). During a write burst, if DOM is held high on the rising edge of ClK, then the incident (referenced
to the same rising edge of ClK) data word on DOD-DO? will be ignored. For a read burst, if DOM is held high
on the rising edge of ClK, then DOD-DO? referenced to the second next rising edge of ClK will be placed in
HI-Z (see note below). Therefore, the application of DOM to data output cycles (READ burst) involves a latency
of 2 ClK cycles, while the application of DOM to data-in cycles (WRITE burst) has no latency. Also note that
the MASK command (or its opposite, the ENBl command) is performed on a cycle-by-cycle basis, allowing the
user to gate any individual data cycle or cycles within either a read or a write burst sequence. Refer to Figure
11 and the examples following the timing requirements and characteristics description.
NOTE: When using terminated DO buses for GTL interfacing, turning off the output buffers at the device will result in the DO lines pulling up to
the terminating voltage, Vn.
TEXAS ~
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elK suspend/power-down mode
For normal device operation, CKE should be held high to enable ClK. If CKE is made low during the execution
of a READ (or READ-P) or WRT (or WRT-P) operation, then the state of the DO bus occurring at the immediate
next rising edge of ClK will be "frozen" at its current state and no further inputs will be accepted until CKE is
returned high. This is known as a ClK suspend operation and its execution is denoted as a HOLD command.
The device will resume operation from the point at which it was placed in suspension beginning with the second
rising edge of ClK after CKE is returned high.
If CKE is brought low when no READ (or READ-P) or WRT (or WRT-P) command is in progress, then the device
will enter power-down mode. If both banks are deactivated when power-down mode is entered, then power
consumption will be reduced to the minimum. Power-down mode may be used during row active or CBR refresh
periods to reduce input buffer power. After power-down mode has been entered, no further inputs will be
accepted until CKE is returned high. When exiting power-down mode, new commands may be entered on the
first ClK edge after CKE is returned high, provided that tCESP is satisfied. If tCESP > tCK, then NOOP or DESl
commands must be entered until tCESP is met. Note that ClK must be active and stable (if ClK was turned off
for power-down) before CKE is returned high. Refer to Table 2 and Figure 14. Also see the self-refresh
description.
mode register set
The synchronous DRAM contains a mode register, which should be programmed by the user with the read
latency length, the burst type, and the burst length. This is accomplished by executing a MRS command with
the information being entered on the address lines AD-AS. Bits A9-A 11 are reserved for later, or manufacturer's
use. A logic 0 should always be entered on A7 and AS, but A9-A 11 are don't care entries for the synchronous
DRAM. (Refer to Figure 1.)
I
A11
I---
I
A10
I
Reserved
A9
I
--+-
AS
I
I
A7
I
AS
AS
I
I
A4
0 +0
A3
I
A2
I
I
A1
AO
I
AS
AS
A4
0
0
1
1
0
1
0
2
0
1
1
3
t All
other combinations are
reserved.
; Refer to timing requirements for
minimum valid Read Latencies
based on maximum frequency
rating.
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a.
REGISTER
BITS§
BURST LATENCY;
A2
A1
AO
0
0
0
0
0
0
1
1
0
1
0
1
1
2
4
8
§ All other combinations are reserved.
Figure 1. Mode Register Programming
The MRS command is executed by holding RAS low, CAS low, W low, and the input mode word valid on AO-AS
on the rising edge of ClK (refer to Table 1). The MRS command can be executed only following the deactivation
of both banks.
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a.
I-
I
READ
LATENCY;
w
a:
o
0= Serial
1 = Interleave
(Burst Type)
REGISTER
BITSt
W
==
:;
4-509
16777216 BIT SYNCHRONOUS
DYNAMIC RANDOM·ACCESS MEMORY
SMOS682-JANUARY 1993
mode register read
To read back the contents of the mode register, a MRR command can be entered, which is identical to the MRS
command described previously, except that AS should be held high instead of low. The DO bus will enter the
low impedance state on the first ClK edge after the M RR command is entered (refer to parameter tL,Z). The lower
nibble of the mode register, bits 0, 1, 2, 3, will be available on the D01, D03, D04, and D06 outputs,
correspondingly, at the fourth ClK edge after the MRR command is entered. The output data will be held for
the time specified bytOH after the fourth ClKedge. Bits 4,5,6 of the mode register will be available on the D01,
D03, and D04 outputs, correspondingly, at the sixth ClK edge after the MRR command is entered. The output
data will be held for the time specified by tOH after the sixth ClK edge. A new command can be entered on or
after the eighth ClK edge occurring after entry of the MRR command. Refer to Figure 2.
MRRCommand
New Command
1
ClK
tLZ
OQ
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:tJ
---14--~~1
C
tHZ
OQ1,3,4
Register
Bits 4-6
Figure 2. Mode Register Read
refresh
The synchronous DRAM must be refreshed at intervals not exceeding tREF (refer to the parameter timing
requirements), or data may not be retained. Refresh can be accomplished by performing a read or write access
to every row in both banks, or by performing 4096 CAS-before-RAS (REFR) commands, or by placing the device
in self-refresh. Regardless of the method used, refresh must be accomplished before tREF has expired.
:tJ
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'---t-
1.----+ tOH
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~
OQ1,3,4,6 .
Register
Bits 0-3
o
o
tAC
CAS·before·RAS (CBR) refresh
Before performing a CAS-before-RAS refresh, both banks must be deactivated (placed in precharge). To enter
a REFR command, RAS must be low, CAS must be low, and W must be high upon the rising edge of ClK (refer
to Table 2). The refresh address is generated internally such that after 4096 REFR commands, both banks of
the SDRAM will have been refreshed. The external address and bank select (A 11) are ignored. Note that
execution of a REFR command will automatically deactivate both banks upon completion of the internal CBR
cycle. This allows consecutive REFR-only commands to be executed, if desired, without any intervening DEAC
commands. The REFR commands do not necessarily have to be consecutive, but all 4096 must be completed
before tREF expires.
self·refresh
To enter self-refresh, both banks of the synchronous DRAM must first be deactivated. Following this, a SlFR
command should be executed (refer to Table 2). The SlFR command is identical to the REFR command
decribed previously, except that CKE is low. Note that for proper entry of the SlFR command, CKE should be
brought low only for the same rising edge of ClKthat RAS and CAS are brought low and W is brought high.
(Otherwise the device would enter power-down mode.) In the self-refresh mode, all refreshing signals are
generated internally for both banks, with all external signals (except CKE) being ignored. Data can be retained
by the device automatically for an indefinite period as long as power is maintained (consumption is reduced to
a minimum). To exit self-refresh mode, CKE should be returned high. Following this, new commands can then
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be issued after tRC has expired. Note that if ClK is made inactive during self-refresh, it must be returned to an
active and stable condition before CKE is brought high to exit self-refresh. Referto Figure 15 following the timing
requirements and electrical characteristics description.
Interrupted bursts
A read or write may be interrupted before the burst sequence has been completed with no adverse performance,
by entering certain superseding commands and providing that all timing requirements are met (refer to timing
requirements and electrical characteristics). Note that the command interrupting either a read or a write burst
should be entered only on an even number of cycles from the initial burst command (nCCD). Note also that
interruption of READ-P and WRT-P operations is not supported.
Table 7. Read Burst Interruption
INTERRUPTING COMMAND
EFFECT OR NOTE ON USE DURING READ BURST
DEAC, DCAB
Note thai the DO bus will be placed in high-impedance state when nHZP is satisfied or upon completion of
the read burst, whichever occurs first. (Refer to Figure 16.)
WRT, WRT-P
The WRT command immediately supersedes the read burst in progress, but note that DOM must be made
high nDOD ClK cycles previous to the WRT (or WRT-P) command entry to avoid DO bus
contention. (Refer to Figure 4.)
READ, READ-P
Current output cycles will continue until the programmed latency from the superseding READ (or READ-P)
command has been met, after which the new output cycles will begin. (Refer to Figure 3.)
STOP
The DO bus will be placed in high-impedance state two clock cycles after the stop command is entered or
upon completion of the read burst, whichever occurs first. The bank will remain active.
ClK
14-I
I
I
nCCD = 2 (even)
:;
w
a:
---+I
I
I
c..
I
Read Command
Interrupting
for Column Address CO
Read Command
(see Note A)~OrColumn Address C1.
;
(see N~te A)
....
I
I
I
U
h
:::)
C
I
o
~~~
I
DQO-DQ7
3:
w
CO
a:
CO + 1
c..
NOTE A: For the purposes of this example Read latency = 2, and Burst length> 2.
Figure 3. Read Burst Interrupted By Read Command
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
4-511
16777216 BIT SYNCHRONOUS
DYNAMIC RANDOM-ACCESS MEMORY
SMOS682-JANUARY 1993
nCCD = 4 (even)
CLK
I
I
Read Command
for Column Address CO
(see r e
Interrupting
Write Command
for Column Address C1
(see Note A)
A)~ ~.....I._",
DQ~Q7--~-------------<
I
I
I
I
104
DQM
nDOD
A
~
I
I
I
NOTE A: For the purposes of this example Read Latency = 2, and Burst Length> 2.
"'C
:a
c
c
o
Figure 4. Read Burst Interrupted By Write Command
o
-I
"'C
:a
m
S
m
=E
TEXAS
~
INsrRUMENTS
4-512
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
16777216 BIT SYNCHRONOUS
DYNAMIC RANDOM·ACCESS MEMORY
SMOS682-JANUARY 1993
Table 8. Write Burst Interruption
INTERRUPTING COMMAND
EFFECT OR NOTE ON USE DURING WRITE BURST
DEAC.DCAB
The DEAC/DCAB command immediately supersedes the write burst in progress. Note that DaM must be
used to mask the DO bus such that the wr~e recovery specification (tRWU is not violated by the
interrupt. (Refer to Figure 6.)
WRT,WRT-P
The new WRT (or WRT-P) command and data-in immediately supersede the write burst in progress.
READ, READ-P
Data-in on previous cycle will be written. No further data-in will be accepted. (Refer to Figure 5.)
STOP
The data on the input pins at the time of the burst STOP command will not be written, and no further data
will be accepted. The bank will remain active.
14-I
ClK
nCCO
= 2 (even)
~
I
I
WRTCo~mand
READ Command
(see Note A)
(see Note A)
I
OQO-OQ7
(
I
I
00-07
X
NOTE A: For the purposes of this example, Read Latency
00-07
)
(
QO-Q7
E
~
w
:>
w
=2, Burst Length> 2, and tCK =tRWL.
a:
Figure 5. Write Burst Interrupted By Read Command
j4--
nCCO
....
o
=2 (even)
::l
I
ClK
I
I
I
I
I
WRT Command
(see Note A)
OQO-OQ7
a.
----«
I
I
00-07
C
o
a:
OEAC or OtAB Command
(see Note A)
a.
I
X D~ X"';" ) > - - - - - r+- tRWl ~
.
OQM _ _ _ _ _ _ _ _- - ' / , . . . -......
~,.,...==.,..,..
.,...,....,.=~===
NOTE A: For the purposes of this example, Read Latency
=2, Burst Length> 2, and tCK =tRWL.
Figure 6. Write Burst Interrupted By DEAC/DCAB Command
power up
After power up to the full Vee level, a 200-lAs pause should be allowed (no input except ClK), after which both
banks of the device must be deactivated (placed in precharge) and the mode register should be set. Eight REFR
commands should then be performed to complete the device initialization. (Refer to Tables 1 and 2, and the set
mode register description.)
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
4-513
16777216 BIT SYNCHRONOUS
DYNAMIC RANDOM-ACCESS MEMORY
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functional block diagram
ClK
CKE
Array Bank "T"
cs------------~
DOM----------~~
RAS-------------.~
DO
Control
DOO-D07
Buffer
CAS------------~
W-------------.~
AO-A11
Array Bank "B"
-------------,/
absolute maximum ratings over operating free-air temperature t
"'C
Voltage on any pin (see Note 1)
.................................................... - 0.5 to 4.6 V
Voltage range on Vee ............................................................. - 0.5 to 4.6 V
Short-circuit output current ................................. '. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 50 mA
Power dissipation .. : ......................................................... ,............. 1 W
Operating free-air temperature range .................................................. O°C to 70°C
Storage temperature range ....................................................... - 55°C to 150°C
lJ
o
C
C
o
-f
"'C
lJ
m
S
m
::E
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values in this datasheet are with respect to VSS.
recommended operating conditions
PARAMETER
lVTTL INTERFACING
GTl INTERFACING
MIN
NOM
MAX
MIN
NOM
MAX
3
3.3
3.6
3
3.3
3.6
VCC
Supply voltage
VSS
Supply voltage
Vn
GTL terminator voltage
VREF
GTL reference voltage
VIH
High-level input voltage
2
VCC+O.3
VIL
Low-level input voltage
-0.3
0.8
TA
Operating free-air temperature
0
70
0
0
1.08
2Vn/3-2% 0.8
VREF+O.OS:l:
0
TEXAS ~
INsrRUMENTS
POST OFFICE BOX 1443· HOUSTON. TEXAS 77001
V
V
1.32
2Vn/3+2%
1.2
0.4
:I: VIH and VIL levels are only for DC testmg. For AC timing, VIH of 1.2 V and VIL of 0.4 V should be used.
4-514
1.2
UNIT
V
V
V
VREF--O·OS:l:
70
V
'c
electrical characteristics over full ranges of recommended operating conditions (unless otherwise noted) (see Note 2)
PARAMETER
IOH~-2mA
LVTTL
2.4
MIN
NOM
SDRAM-15
MAX
2.4
MIN
NOM
MAX
2.4
UNIT
Low-level
output voltage
IOL~ 2mA
LVTTL
0.4
0.4
0.4
VOL
IOL ~ 32 mA
GTL
0.4
0.4
0.4
II
Input current
(leakage)
o V" VI "Vcc + 0.3 V, All other pins ~ OVtoVCC
±10
±10
±10
J.LA
10
Output cu rrent
(leakage)
o V "VO " VCC + 0.3 V, Output disabled
±10
±10
±10
J.LA
Average read or
write current
90
80
70
mA
ICCI
tRc~min
160
150
125
mA
J.LA
GTL
1 bank active
2 banks active
CKE~VIH
~z
Both banks deactivated
ICC2
Standby current
CKE~VIL
CKE~OV
(CMOS)
5~
§rr1
One or both banks
active
£~
~
SDRAM-12
MAX
IIOHI ,,10
-<
~ a1..t
NOM
High-level output
voltage
0_
(J)
MIN
VOH
g
i~~d
SDRAM-10
TEST CONDITIONS
ICC3
Consecutive CBR
commands
tRC ~ min
ICC4
Burst currenl,
gapless burst
tCK~
ICC6
Self-refresh
current
CKE ~VIL
CKE - 0 V (CMOS)
1.2
Vn-0.05
1.2
Vn-0.05
V
1.2
LVTTL
16
16
16
GTL
20
20
20
LVTTL
2
2
2
GTL
3
3
3
LVTTL
1
1
1
V
mA
LVTTL
4
4
4
GTL
5
5
5
90
80
70
mA
120
100
80
mA
LVTTL
2
2
2
mA
GTL
3
3
3
mA
LVTTL
1
1
1
mA
min
CKE~VIL
Vn- 0.05
z~
l>
~
C~
00)
3:m
NOTE 2: All specifications apply to the device after power-up initialization.
0-<
8l
(1)0
oen
i
~
~
~
'"'"
'"
U1
PRODUCT PREVIEW
>=i
0(1)
s:
en
f"
...
00)
:::z:I-..!
l>-..!
Z-..!
mZ
(I):::z::
3::::z:I
mo
3:Z
00
:::z:IC:
-<(I)
16777 216 BIT SYNCHRONOUS
DYNAMIC RANDOM·ACCESS MEMORY
SMOS682-.JANUARY 1993
capacitance over recommended ranges of supply voltage and operating free·air temperature,
f = 1 MHz (see Note 3)
MIN
NOM
MAX
UNT
Ci(S)
Input capacitance, ClK input
7
pF
Ci(AC)
Input capacitance, address and control inputs: AD-A 11, CS, DOM, RAS, CAS, W
5
pF
Ci(~
Input capacitance, CKE input
5
pF
Co
Output capacitance
10
pF
NOTE 3: VCC = 3.3
±
0.3 V and bias on pins under test is 0 V.
"'D
II
o
C
C
n
-I
"'D
II
m
S
m
=E
TEXAS ."
INSTRUMENTS
4-516
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
16777 216 BIT SYNCHRONOUS
DYNAMIC RANDOM-ACCESS MEMORY
SMOS682-JANUARY 1993
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
PARAMETERt
tCK
ClK (system clock) cycle
time
SDRAM-l0
SDRAM-12
MIN
MIN
MAX
SDRAM-15
MAX
MIN
Read latency = 1
30
35
40
Read latency = 2
15
17.5
20
Read latency = 3
10
12.5
15
MAX
UNIT
ns
tCKH
ClK (system clock) high pulse duration
3
3.5
4
ns
tCKl
ClK (system clock) low pulse duration
3
3.5
4
ns
Read latency = 1
28
33
38
tAC
Data-out access from ClK
(see Note 4)
Read latency = 2
13
15
18
Read latency = 3
8
10
12
ns
tOH
Data-out hold from ClK
2
2
2
tLZ
ClKto DO lO-Z (see Note 5)
0
0
0
tHZ
ClK to DO HI-Z (see Note 6)
tDS
Data-in setup time
2
2
2
ns
tAS
Address setup time
2
2
2
ns
tcs
Control input (CS, RAS, CAS, W, DOM) setup time
2
2
2
ns
tCES
CKE setup time (suspend entry/exit, power-down entry)
2
2
2
ns
tCESP
CKE setup time (power-down exit) (see Note 7)
8
10
12
ns
tDH
Data-in hold time
2
3
4
ns
tAH
Address hold time
2
3
4
ns
tCH
Control input (CS, RAS, CAS, W, DOM) hold time
2
3
4
ns
tCEH
CKE hold time
2
3
4
ns
tRC
REFR command to ACTV, MRS, or REFR command;
Self-refresh exit to ACTV, MRS, or REFR command
100
110
130
ns
tRAS
ACTV command to DEAC or DCAB command
60
tRCD
ACTV command to READ or WRT command
30
35
40
ns
tRP
DEAC or DCAB command to ACTV, MRS, or REFR command
40
40
50
ns
tAPR
Final data-out of READ-P operation to ACTV, MRS,
or REFR command
7
7
100000
70
100000
tRP + (nEP * tcKl
ns
ns
7
80
100000
ns
ns
ns
t A command, data-in, or data-out is referenced at the rising transition of ClK.
Setup and hold times are referenced to the rising transition of ClK.
The reference level used for timing measurements is 1.4 V for lVTTl, and 0.8 V for GTL.
AC measurements assume tT = 1 ns.
All specifications referring to READ commands are also valid for READ-P commands unless otherwise noted.
All specifications referring to WRT commands are also valid for WRT-P commands unless otherwise noted.
All specifications referring to consecutive commands are specified as consecutive commands for the same bank, unless otherwise noted.
Note that a ClK cycle can be considered as contributing to a timing requirement for those parameters defined in cycle units only when not gated
by CKE (those ClK cycles occurring during a HOLD operation).
NOTES: 4. tAC is referenced from the rising transition of ClK that is previous to the data-out cycle. For example, the first data-out tAC is
referenced from the rising transition of ClK that is Read latency - 1 cycles after the READ command.
5. tLZ is measured from the rising transition of ClK that is Read latency - 1 cycles after the READ command.
6. tHZ (max) defines the time at which the outputs are no longer driven and is not referenced to output voltage levels.
7. IftCESP > tCK, then NOOP or DESl commands must be entered until tCESP is met. Note that elK must be active and stable (if ClK
was turned off for power-down) before CKE is returned high.
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
4-517
:=w
->
w
a:
c..
I-
o::)
c
o
a:
c..
16777 216 BIT SYNCHRONOUS
DYNAMIC RANDOM·ACCESS MEMORY
SMOS682-JANUARY 1993
timing requirements over recommended ranges of supply voltage and operating free·air
temperature (continued)
SCRAM-l0
PARAMETERt
tAPW
Final data-in of WRT-P operation to ACTV, MRS, or REFR
command
60
SCRAM-12
MAX
MIN
SCRAM-IS
MAX
MIN
ns
ns
Final data-in to DEAC or DCAB command
20
20
30
ACTV command for one bank to ACTV command for the other bank
20
25
30
IT
Transition time, all inputs (see Note 7)
tREF
Refresh interval
nHZP
lJ
oC
nCCD
n
5
1
64
5
1
64
Burst Length> I, Read Latency = 1
0
0
0
Burst Length> I, Read Latency = 2
-1
-1
-1
Final data-out to DEAC or Burst Length> I, Read Latency = 3
DCAB command
Burst Length = I, Read Latency = 1
-2
-2
-2
1
1
1
DEAC or DCAB interrupt of
data-out burst to DQ HI-Z
(see Note 8)
= I, Read Latency =2
= I, Read Latency =3
Read Latency = 1
Read Latency =2
Read Latency =3
Burst Length
0
0
0
Burst Length
-1
-1
-1
READ orWRTcommand to interrupting STOP, READ, WRT, DEAC,
or DCAB command (i = I, 2, 3, ... ) (see Note 9)
UNIT
80
tRWL
1
MAX
60
tRRD
nEP
'tJ
MIN
1
1
1
2
2
2
3
3
3
2i
2i
2i
ns
5
ns
64
ms
cycles
cycles
cycles
c:
nCWL
Final data-in to READ command in either bank
1
nWCD
WRT command to first data-in
0
0
0
0
0
0
cycles
-I
nDID
ENBL or MASK command to data-in
0
0
0
0
0
0
cycles
'tJ
nDOD
ENBL or MASK command to data-out
2
2
2
2
2
2
cycles
m
:S
m
nCLE
HOLD command to suspended CLK edge;
HOLD operation exit to entry of any command
1
1
1
1
1
1
cycles
nRSA
MRS command to ACTV command
2
lJ
==
1
2
cycles
1
2
cycles
0 cycles
0
0
0
0
0
nCDD DESL command to control input inhibit
t A command, data-in, or data-out is referenced at the rising transition of ClK.
Setup and hold times are referenced to the rising transition of CLK.
The reference level used for timing measurements is 1.4 V for LVTTL, and 0.8 V for GTL.
AC measurements assume IT = 1 ns.
All specifications referring to READ commands are also valid for READ-P commands unless otherwise noted.
All specifications referring to WRT commands are also valid for WRT-P commands unless otherwise rioted.
All specifications referring to consecutive commands are specified as consecutive commands for the same bank, unless otherwise noted.
Note that a CLK cycle can be considered as contributing to a timing requirement for those parameters defined in cycle units only when not gated
by CKE (those CLK cycles occurring during the time when CKE is asserted low).
NOTES: 8. Transition time, IT, is measured between VIH and VIL.
9. A data-out burst may be interrupted only on an even number of clock cycles after the initial READ command is entered (refer to
nCCD). Note that interruption of READ-P and WRT-P operations is not supported.
10. A read or write burst can only be interrupted at even number cycle intervals after entry of the initial READ or WRT command. The
nCCD specification applies only for the interruption of read or write bursts.
TEXAS ~
INsrRUMENTS
4-518
POST OFFICE BOX 1443' HOUSTON, TEXAS 77001
16777 216 BIT SYNCHRONOUS
DYNAMIC RANDOM·ACCESS MEMORY
SMOS682-JANUARY 1993
Table 9. Number of Cycles Required to Meet Minimum Specification for Key Timing Parameters
SDRAM·l0
Operating frequency
tCK
ClK (system clock) cycle time
SDRAM·12
SDRAM·1S
UNITS
100
80
66
50
33
80
66
50
33
66
50
33
MHz
10
12.5
15
20
30
12.5
15
20
30
15
20
30
ns
NUMBER OF CYCLES REQUIRED
KEY PARAMETER
Read latency, min programmed value
3
3
2
2
1
3
3
2
2
3
2
2
cycles
tRCD
ACTV command to READ or WRT
command
3
3
2
2
1
3
3
2
2
3
2
2
cycles
tRAS
ACTV command to DEAC or DCAB
command
6
5
4
3
2
6
5
4
3
6
4
3
cycles
tRP
DEAC or DCAB command to ACTV,
MODE, or REFR command
4
4
3
2
2
4
3
2
2
4
3
2
cycles
tRC
REFR command to ACTV, mode, or
REFR command: self-refresh exit to
ACTV, MODE, or REFR command
10
8
7
5
4
9
8
6
4
9
7
5
cycles
tRWl
Final Data-in to DEAC or DCAB
command
2
2
2
1
1
2
2
1
1
2
2
1
cycles
tRRD
ACTV command for one bank to ACTV
command for the other bank
2
2
2
1
1
2
2
2
1
2
2
1
cycles
Read Latency = 3
2
2
1
0
0
2
1
0
0
2
1
0
cycles
tAPR
Final data-out of
READ-P operation
to ACTV, MRS, or
REFR command
Read latency = 2
-
-
2
1
1
-
-
1
1
1
cycles
-
-
-
-
2
-
-
-
-
-
2
Read latency = 1
-
-
cycles
6
5
4
3
2
5
4
3
2
6
4
3
cycles
tAPW
Final data-in of WRT-P operation to
ACTV, MODE or REFR command
3:
w
:>
w
a:
a..
t-
O
::J
C
o
a:
a..
TEXAS
~
INsrRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
4-519
16777 216 BIT SYNCHRONOUS
DYNAMIC RANDOM-ACCESS MEMORY
SMOS682-JANUARY 1993
PARAMETER MEASUREMENT INFORMATION
-1
1.4V
Output
Under Test
I
VTT=1.2V
3.3V
RL=500Q
RT=50~·
R1 = 1180 Q
RT=50Q
Output
Under Test
Output
Under
Test
CL=50pF
(a) LVTTL Load Circuit
VTT=1.2V
ZO =50Q
CL=50pF
(b) LVTTL Alternate Load Circuit
(c) GTL Load Circuit
Figure 7. Synchronous DRAM Load Circuits
nEP
"'D
:xJ
CLK
o
C
I
DEAC/DCAB Command
c:
o
-I
"'D
DQO-OQ7
:xJ
m
m
---JXI---..JXI---..JX
X
I
»,----~
Final Output of Burst7 -
-<
Figure 8. nEP (Assume Read Latency = 3)
:e
Figure 9. Output Parameters
TEXAS
~
IN5rRUMENTS
4-520
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
I
16777 216 BIT SYNCHRONOUS
DYNAMIC RANDOM·ACCESS MEMORY
SMOS682-JANUARY 1993
PARAMETER MEASUREMENT INFORMATION
-----.!~
ACTV
~104---
ACTV
14
4 - - - - tRCD
1
DEAC, DCAB
1
.1
DEAC, DCAB
114-4----
~ ACTV, MRS, REFR
REFR
14104----
ACTV
1
14
4----
READ, WRT
1
1
1
~ ACTV, MRS, REFR
ACTV
1
'4~----
SELF·REFRESH EXIT
14104----
ACTV
MRS
READ, WRT
CLK
- - - - - . . . : ACTV, MRS, REFR
~ ACTV, DEAC, READ, WRT
14~----
nRSA
-----.,~
'4~----
nCCD
~
-¥-
DESL
Command
Disable
tRC
tRRD
(see Note A)
nCCD
ACTV
STOP, READ, WRT, DEAC, DCAB
1
1
1
1
1
~r----T\-
;:
->W
w
NOTE A: tRRD is specified for command execution in one bank to command execution in the other bank.
a:
Figure 10. Command to Command Parameters
a..
....
o
~tCK~
tCKH~
II
CLK
::J
C
:
I
oa:
1
_ _ _ _ _JI
1
1
1
a..
1
tCKL~
1
tDS, tAS, tcs, tCES
-114-4--~~~
1
---,;~.
:'
tT~:'-
-.!
I
~
T
~,W,DOM,CKE
1
~ tOH,
I
I
1
Y
~~7,AO-A11,CS,RAS,
:
1
tos, tAS, tcs, tCES, tCESP ~141-----.!~
J!I
N
l4-i----Ir]~1
tAH, tCH, tCEH
1
I
\1.
OOO-~7,AO-A11,CS,RAS,
CAS,W,OOM,CKE
tT
Figure 11. Input Attribute Parameters
TEXAS
~
IN8rRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
4-521
16777216 BIT SYNCHRONOUS
DYNAMIC RANDOM-ACCESS MEMORY
SMOS682-JANUARY 1993
PARAMETER MEASUREMENT INFORMATION
~ Read Latency = 2
(see Note A)
1
II..
CLK
--.I
1
14-
~
nDOD
1
1
1
DQO-DQ7
I
1
1
1
1
"'C
:D
DQM
o
C
C
o
~I
nDOD
1
1
1
1
1
------------'----
NOTE A: For purposes of this example the Burst length = 2.
Figure 14. Write Automatic Deactivate (Autoprecharge)
~ nClE
I+- nClE
I
ClK
DQO-DQ7
-< Q~Q7
---+i
~
1
1
I
1
1
(a_S_su_m...,~;lnal
X,--_Q_0-_Q_7_ _
3:
w
:>w
1
a:
a...
)>--
data-out of burst)
t-
O
I
~tCES
~tCES
::J
C
I,--------
1
CKE " " \..... _ _ _ _ _ _ _ _,I/'r,_______
o
a:
a...
Figure 15. Figure 12. eLK Suspend Operation
No READ(-P) or
WRT(-P)
In Progress ~
Exit Power Down
(New Command) ~
ClK
1
14-14-
CKE
~!- tCES
....
114-4- . -
tCESP
\'-------~\~1--~1
Figure 16. Power-Down Operation
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
4-523
16777216 BIT SYNCHRONOUS
DYNAMIC RANDOM-ACCESS MEMORY
SMOS682-JANUARY 1993
PARAMETER MEASUREMENT INFORMATION
CLK Is "Don't Care"
For This Interval
-"j"
~
\.JI
I
I
I
I
I
tCEH
~
I
I
CLK Must Be Active
and Stable Before
Returning CKE High
I
~
tRC ~
I~
~~~40-.J
SLFR c~mmand
I
CKE
I
~
CLK
14I
--j;I4I------~
tCESP
Self.Refresh
Exit
I
I
-r---.:
ACTV, MRS,
OR REFR
Command
I
tCES
--'J.
/_-1',')
,~.----~\'~)--------~
NOTE: Assume both banks are previously deactivated.
Figure 17. Self·Refresh Entry/Exit
"tJ
J]
o
c
c
o
-I
~nCWL~
"tJ
CLK~I
J]
m
:S
m
=E
Final Input of
Write Burst ~
L.
I
I
I
DEAC/DCAB
Command
I
I
00-07
X
I
00-07
X X
00-07
= 2 and burst length =8.
Figure 18. Write Burst Followed By DEAC/DCAB-Interrupted Read
TEXAS ~
INSTRUMENTS
4-524
~
nHZP
I
Read
Command
DOO-D07~'r)-1~----------~(
NOTE: Assume read latency
~
nCCD = 4 (Even)
POST OFFICE BOX 1443' HOUSTON, TEXAS 77001
00-07
)
ACTVT
D~CT
READT
ClK
DQ
------------~----------------------~-----------------~~-------,
DQM
•
CAS
I
Vi
'
,
RAS
"0
:~
\...J
~'
.;'
,
'
U>
--i
~
Z
;f!4
~~~
5~
_~ ~
Al0
I
~@..t
I
~
I
~
:
~~
,
,
All
~.~ ~ ~ ~--:--~
~
z
U>
:r>
AO-A9
CS
CKE
~:~:~:~
Rl
::1:11 .....
:r> .....
z .....
c~
'Iff
Oc:n
3:m
BURST CYCLE
iBURST
TYPE
(D/Q)
BANK
(8fT)
ROW
ADDR
a
b
c
d
Q
T
RO
cot
CO+ 1
CO+2
CO+3
t Column address sequence depends on programmed burst type and CO. (Refer to Table 5.)
....
!:
.....
Oc:n
NOTE: This example illustrates minimum tRCD and nCl for the SDRAM-l0 at 100 MHz, the SDRAM-12 at 80 MHz, and the SDRAM-15 at 66 Ml;lz.
Figure 19. Read Burst (Read Latency = 3, Burst Length =4)
01
PRODUCT PREVIEW
'"o;::
g:
r
~
c
:>
~
~
>=i
Oen
0-<
mZ
enO
en:::z:
3:::1:11
3:Z
00
mo
::I:IIC:
-naO~d
....
ACTVT
,
&.
WRTT
,
DEACT
I\)
0>
en
en
;::
o
0)
CLK
f
z
c
DO
~
{
DOM~:
~
\jJ
RAS
I
~r
I
.. ,
I
A11
~
trJ
3:1\)
n;;
::::a::J
m
:r>Z .....
ccn
0-<
Z
3:
• 0
:r>:::t:
\if
s:
o
0::::a::J
mZ
cn o
cnc:
3:cn
\..J
~
,'
w
,
~:~:~
~:~:
AO-A9
CS~:~:
CKE
Z ......
:r>::::t
00
:
~..t_
-<0)
\if
CAS
2'
~
C-"
:~
Iff
BURST
TYPE
BURST CYCLE
(D/Q)
BANK
(BfT)
ROW
ADDR
a
b
c
d
e
D
T
RO
cot
CO+ 1
CO+2
CO+3
CO+4
CO+5
9
h
CO+6
CO+7
t Column address sequence depends on programmed burst type and CO. (Refer to Table 6.)
Figure 20. Write Burst (Burst Length
=8)
m
~
W~TB
AC1"B
R~DB
O~CT
CLK
OQ
OQM
~:~~
"----J
,
RAS
'
I
i
I
I
~~d
I
Al0
I
A11
I
Ao-A9
~Z
\~~
5 ~
&itr1
en
I
I
i
I
I
,
,
,
,
~
,
,
w
£2!
S(jj4r
I
'
,
,
CAS
~
0_
"----J
I
I
~::~
~:~:~:~:~
~
Z
~
CS
CKE
BURST
TYPE
(D/Q)
D
a
~:~:~:~:~
W
Z ....
C~
Oen
3:m
BURST CYCLE
BANK
(BfT)
ROW
AODR
B
B
RO
RO
):,.=i
a
b
cot
CO+ 1
c
d
!
C1*
C1_ + 1
I
en
'"
....
'"
* Column address sequence depends on programmed burst type and C1. (Refer to Table 4.)
NOTE: This example illustrates minimum tRCD and nCL for the SDRAM-1 0 at 100 MHz, the SDRAM-12 at 80 MHz, and the SDRAM-15 at 66 MHz.
Figure 21. Write-Read Burst (Read Latency
=3,
Burst Length
PRODUCT PREVIEW
=2)
0(1)
s:
0<
~
(1)0
g
t Column address sequence depends on programmed burst type and CO. (Refer to Table 4.)
...
:I>
~ ....
Oen
::D ....
:1> ....
§;
~
naOHd
:1:
a
b
c
d
e
f
9
h
cot
CO+1
CO+2
CO+3
CO+4
CO+5
CO+6
CO+7
i
j
k
I
m
n
0
p
Cl
C1+1
Cl+2
C1+3
Cl+4
C1+5
C1+6
Cl+7
§@4r
t Column address sequence depends on programmed burst type and CO. (Refer to Table 6.)
~
l Column address sequence depends on programmed burst type and Cl.( Refer to Table 6.)
NOTE: This example illustrates minimum tRCD and nCL for the SDRAM-l0 at 100 MHz, the SDRAM-12 at 80 MHz, and the SDRAM-15 at 66 MHz.
--_._-
Figure 22. Read-Write Burst With Automatic Deactivate (Read Latency
=3,
Burst Length
=8)
AC1"B
REJl.DB
AC1"T
REJl.DB
RE4DT
REJl.D B
ClK
DQ
{
DaM
'0J
-\.i..j
RAS
,..--...
CAS
w
Z
~d
~~
~
aj..t
Al0
All
~ Illllltlllll! : ~
:
:~:~:~:~:Illlt
: Itl!llI : ~ : Itl!llI ; ~ : Ilm
AG-A9
CS~ :~
CKE
~ ~ ~
:
~
:
~
:
~
:
Illlt
c
-<
z
:I>
'W'
BURST
TYPE
(0/0)
Q
Q
Q
:
~ ......
nen
::c . . . .
:1> .......
BURST CYCLE
BANK
(BIT)
ROW
ADDR
B
T
RO
Rl
RO
a
b
cot
CO+ 1
c
d
Cl*
Cl + 1
Z .......
e
C~
Oen
I
:S::m
>=i
t Column address sequence depends on programmed burst type and CO. (Refer to Table 4.)
~
nen
n-<
mZ
enn
en
* Column address sequence depends on programmed burst type and Cl. (Refer to Table 4.)
§ Column address sequence depends on programmed burst type and C2. (Refer to Table 4.)
NOTE: This example illustrates minimum tRCD and nCL for the SDRAM-10 at 100 MHz, the SDRAM-12 at 80 MHz, and the SDRAM-15 at 66 MHz.
z
mo
B
C2§
C2+ 1
(J)
so
o
(J)
f'
'"'"
Figure 23. Two-Bank Column Interleaving (Read Latency = 3,
Burst Length = 2)
~
c
~
:S::Z
00
<0
<0
-naO~d
ACTVB
f'
~
o
READ-P B
READ-PT
ClK
""
"",
'\J'
""'
""
'*'
""
00
"".
'"'
'-'
'-'I
'-'
ACTVB
'-'
""
'-'
'-'I
READ-P B
ACTVT
""
a
~
DQM~
~,
\..0
~
'+-"
\.;.J
CAS
\..0
~
~
~
AO-A9
o
~Z
CSmm.
~:~'~:~,~'~
~~
~a!.
~
~ ~!!!
Z-t
<0
12
C~
Am
l>:::c
O::EJ
00
mZ
tnO
tnc:
i:tn
m
i:
~
~.,
g~~
i: N
n;;
o
VYji
W
:;:00
~~~
z~
l>:::::I
=::0
A10~~~~
A11mm.:~'~: _ _ '~:~ ~:~
CKE
~;;
oz
W
g....
,
Cf)
s:
Cf)
BURST
TYPE
(D/Q)
BANK
(BfT)
ROW
ADDR
BURST CYCLE
Q
Q
Q
B
T
B
RO
R1
R2
a
cot
b
c
d
e
9
k
h
m
n
0
p
s
q
CO+1 CO+2 CO+3 CO+4 CO+5 CO+6 CO+7
Cft:
C1+1 C1+2 C1+3 C1+4 C1+5 C1+6 C1+7
C2§
C2+1 C2+2
t Column address sequence depends on programmed burst type ",nd CO. (Refer to Table 6.)
:j: Column address sequence depends on porgrammed burst type and C1.( Refer to Table 6.)
§ Column address sequence depends on porgrammed burst type and C2.( Refer to Table 6.)
NOTE: This example illustrates minimum tRCD and nCL for the SDRAM-1 0 at 100 MHz, the SDRAM-12 at 80 MHz, and the SDRAM-15 at 66 MHz.
Figure 24. Two-Bank Row Interleaving With Automatic Deactivate (Read Latency
=3, Burst Length =8)
ACTVT
ACTVB
ClK
DO
DOM
RAS
READB
_:
":J
:,:
:,.J
\
Vi
WRTT
DEACT
:~:~
J
,:
.~
CAS
."
DEACB
/
'
~
,
\....;:
:
J~
r-
I
'
~
----~,----~~:----~~
j
~~--------~
0
en
-i
0_
~2!
I
j~r
All
I
~~ . .
-
en
I
~
:::
@ -.
~:~i_
~ : ~ : I . ~: 1lllltl/l/IlII!: ~ : ~
I
I
,
I
I
AO-A9
g~
.z
Al0
CS
CKE
§
~~
~~~Illh
W
BURST
TYPE
c
~
:~
l>
~ .....
Om
:a .....
l> .....
BURST CYCLE
(D/Q)
BANK
(Bm
ROW
ADDR
Q
D
B
T
RO
R1
a
b
c
d
cot
CO+1
CO+2
CO+3
z .....
e
C1*
C1+1
9
h
C1+2
C1+3
c~
Om
:S:m
:i>=i
t Column address sequence depends on programmed burst type and CO. (Refer to Table 5.)
* Column address sequence depends on programmed burst type and C1. (Refer to Table 5.)
NOTE: This example illustrates minimum tRCD and nCL for the SDRAM-10 at 100 MHz, the SDRAM-12 at 80 MHz, and the SDRAM·15 at 66 MHz.
Figure 25. Read Burst Bank B, Write Burst Bank T (Read Latency
..,.
~
=3,
Burst Length = 4)
C/)
;::
o
C/)
~
enO
en::J:
:s::a
~
:S:Z
00
~
~
PRODUCT PREVIEW
Oen
0<
mZ
mo
:ac:
:::t
3:
N
- ....
°en
::am
:1>Z .....
0(1)
0-<
~'--~------------~----------------
,
0 ....
,
3: Z
·0
:1>:3:
O::a
00
mz
(1)0
CAS
(l)e:
3:(1)
~
"--J
w
o
~~
i~~
g~&j
~~
~@4r
~
m
:s:
o
A10~~'~
A"W:~:1l!l!iI
~
~
AG--A9
I
I
I
I
CSS&.~~~~~~~~
I
I
I
I
~W
~
BURST CYCLE
BURST
TYPE
(D/Q)
BANK
(BIT)
ROW
ADDR
D
T
Q
B
RO
RI
a
b
c
d
cot
CO+I
CO+2
CO+3
e
Cit
CI+I
9
h
CI+2
CI+3
t Column address sequence depends on programmed burst type and CO. (Refer to Table 5.)
:j: Column address sequence depends on programmed burst type and CI. (Refer to Table 5.)
NOTE: This example illustrates minimum tRCD and nCL for the SDRAM·IO at 100 MHz, the SDRAM·12 at 80 MHz, and the SDRAM-I 5 at 66 MHz.
Figure 26. Write Burst Bank T, Read Burst Bank B With Automatic Deactivate (Read Latency
=3,
Burst Length
=4)
~
ACTVB
READT
ACTVT
WRTB
DCAB
CLK
DQ
DQM
RAS
CAS
Vi
Z
~d
~~
~4r
Al0~
All
'-~'
~
'@
~:~-:-\:-:I
,
I
I
Ao-A9
CS~:~:
eKE
:_:~:
#h
z~
W
»
=:
BURST
TYPE
(D/Q)
BANK
(BfT)
ROW
ADDR
Q
D
T
B
RO
Rl
- ....
0=
BURST CYCLE
a
b
c
d
cot
CO+l
CO+2
CO+3
e
9
h
Cl+2
Cl+3
:a ......
»
z ........ .
c~
Cl*
Cl+l
0=
=:m
l>=i
t Column address sequence depends on programmed burst type and CO. (Refer to Table 5.)
:t: Column address sequence depends on programmed burst type and Cl. (Refer to Table 5.)
NOTE: This example illustrates minimum tRCD and nCL for the SDRAM-15 at 50 MHz.
Figure 27. Use Of DaM For Output and Data-In Cycle Masking (Read Burst Bank T,
Write Burst Bank B, Deactivate All Banks) (Read Latency =2, Burst Length =4)
0-<
mZ
~
=::a
CIJ
CIJ
§i
~
f'
~
t3
'"
PRODUCT PREVIEW
Oen
o
;;::
enO
en:::c
mo
=:Z
00
:ac:
-naOl:td
REFR
-!"
'"""
....
•
REFR
ACTVT
READT
DEACT
REFR
ClK
DQ
----~------------------~------------------------~--~~~----
en
;::
en
c
-:::1
15:1\)
m
~ :::U
>Z .....
DQM
~
RAS
C~
Oz
15:
CAS
0
3>::1:
O:::u
W
00
mZ
(1)0
(l)c:
15:(1)
m
15:
Z
~d
~~
~
aJ..t
o
~
CKErr
~
;~
BURST CYCLE
BURST
TYPE
(D/Q)
BANK
(BfT)
ROW
ADDR
a
b
c
d
e
f
g
h
Q
T
RO
cot
CO+1
CO+2
CO+3
CO+4
CO+5
CO+6
CO+7
t Column address sequence depends on programmed burst type and CO. (Refer to Table 6.)
NOTE: This example illustrates minimum tRCD and nCL for the SDRAM-12 at 50 MHz.
Figure 28. Refresh Cycles (Refreshes Followed By Read Burst Followed By Refresh)
(Read Latency = 2, Burst Length =8)
OC,AB
MqOE
AC\VB
WRI-P B
CLK
~
OQ
OQM
:
~
RAS
,---_\..J
CAS
~
~Z
o
i~
~~~
g~51
~~
~ aJ..t
::j
~
\.U
W
A10~'
A"~~~~O)@2W: ~
,::
:~'
_(~-B)-'
ttttttA:
c
,~,~~:
-~
cs
<
~
!!!ll: .....
nen
::a ......
:J> ......
CKE(jf
Z ......
C~
BURST CYCLE
BURST
TYPE
(O/Q)
BANK
(BfT)
ROW
AOOR
a
b
c
d
D
B
RO
cot
CO+1
CO+2
CO+3
Oen
S:m
l>=i
C/)
;::
....
t Column address sequence depends on programmed burst type and CO. (Refer to Table 5.)
oC/)
NOTES: A. This example illustrates minimum tRCD for the SDRAM-15 at 66 MHz.
B. Refer to Figure 1, Mode Register Programming, on page 9.
'"
Figure 29. Mode Register Programming (Deactivate All, Mode Program, Read Burst With Automatic Deactivate)
(Read Latency =2, Burst Length =4)
0,
~ s:::a
mo
S:Z
~ 0
0
::ac:
z
CD
~
'"
01
PRODUCT PREVIEW
nen
n<
mZ
enn
en::J:
I
ACTVT
READ-PT
HOLD
ACTVB
WRT-PB
POE
ClK
DQ
DQM
RAS
~::-:
~:
o
CAS
Vi
Z
~d
~
~~
~
~4r
I
Al0
All
I
AO-A9
I
CS
CKE
~
:
:
:
0
~
~
~
~
~
~:.:
~:'@§§Y.:_:~~_
,
'
,
~:~:-:~:-
~
./
BURST
TYPE
(DrQ)
Q
D
~
BURST CYCLE
BANK
(BfT)
ROW
ADDR
T
B
RO
Rl
a
b
c
d
cot
CO+l
CO+2
CO+3
e
Cl:j:
Cl+l
9
h
Cl+2
Cl+3
t Column address sequence depends on programmed burst type and CO. (Refer to Table 5.)
:j: Column address sequence depends on programmed burst type and Cl. (Refer to Table 5.)
NOTE: This example illustrates minimum tRCD and nCL for the SDRAM-15 at 50 MHz.
Figure 30. Use Of CKE For Clock Gating (Hold) And Standby Mode
(Read Burst Bank T With Hold, Write Burst Bank B, Standby Mode)
(Read Latency 2, Burst Length 4)
=
=
c ....
-£
O':D
00
mz
cno
cnc:
is:cn
m
is:
o
~
Dynamic RAM Modules
5-1
Contents
CHAPTER 5.
DYNAMIC RAM MODULES
TM124EU9B
9 437 184-bit
(1 024K x 9) Single-Sided ................................... 5-5
TM124EU9C
9 437 184-bit
(1 024K x 9) Single-Sided ................................... 5-5
TM497EAD9B
33 554 432-bit
(4096K x 9) Single-Sided .................................. 5-13
TM497MBK36A
150 994 944-bit
(4096K x 36) Double-Sided (gold-tabbed) .................... 5-21
TM497MBK36Q
150 994 944-bit
(4096K x 36) Double-Sided (solder-tabbed) .................. 5-21
TM124BBK32
33 554 432-bit
(1 024K x 32) Single-Sided (gold-tabbed) . . . . . . . . . . . . . . . . . . . .. 5-29
TM124BBK32S
33 554 432-bit
(1 024K x 32) Single-Sided (solder-tabbed) ................... 5-29
TM248CBK32
67 543 040-bit
(2048K x 32) Double-Sided (gold-tabbed) .................... 5-29
TM248CBK32S
67 543 040-bit
(2048K x 32) Double-Sided (solder-tabbed) .................. 5-29
TM124MBK36
37 748 736-bit
(1 024K x 36) Double-Sided (gold-tabbed) .................... 5-39
TM124MBK36Q
37 748 736-bit
(1 024K x 36) Double-Sided (solder-tabbed) .................. 5-39
TM124MBK36B
37 748 736-bit
(1024K x 36) Single-Sided (gold-tabbed) ..................... 5-47
TM124MBK36R
37748736-bit
(1 024K x 36) Single-Sided (solder-tabbed) ................... 5-47
TM248NBK36B
75497472-bit
(2048K x 36) Double-Sided (gold-tabbed) .................... 5-47
TM248NBK36R
75497472-bit
(2048K x 36) Double-Sided (solder-tabbed) .................. 5-47
TM124MBK36C
37 748 736-bit
(1 024K x 36) Single-Sided (gold-tabbed) . . . . . . . . . . . . . . . . . . . .. 5-57
TM124MBK36S
37 748 736-bit
(1 024K x 36) Single-Sided (solder-tabbed) ................... 5-57
TM248NBK36C
75 497 472-bit
(2048K x 36) Double-Sided (gold-tabbed) .................... 5-57
TM248NBK36S
75497472-bit
(2048K x 36) Double-Sided (solder-tabbed) .................. 5-57
TM4100EAD9
37748736-bit
(4096K x 9) Single-Sided .................................. 5-67
TM4100GAD8
33 554 432-bit
(4096K x 8) Single-Sided .................................. 5-75
TM497GAD8A
33 554 432-bit
(4096K x 8) Single-Sided .................................. 5-83
TM16100GBD8
134 217 728-bit
(16 384K x 8) Double-Sided .. . . . . . . . . . . . . . . . . . . . .. . .. . .. . .. 5-91
TM16100EBD9
150 994 944-bit
(16 384K x 9) Double-Sided . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-99
TM497BBK32
134 217 728-bit
(4096K x 32) Double-Sided (gold-tabbed) ................... 5-105
TM497BBK32S
134217728-bit
(4096K x 32) Double-Sided (solder-tabbed) ................. 5-105
TM893CBK32
268 435 456-bit
(8192K x 32) Double-Sided (gold-tabbed) ................... 5-105
TM893CBK32S
268 435 456-bit
(8192K x 32) Double-Sided (solder-tabbed) ................. 5-105
TM497TBM40
167 772 160-bit
(4096K x 40) Double-Sided (gold-tabbed) ................... 5-115
5-2
TM497TBM40S
167 772 160-bit
(4096K x 40) Double-Sided (solder-tabbed) ................. 5-115
TM893VBM40
335 544 320-bit
(8192Kx 40) Double-Sided (gold-tabbed) ................... 5-115
TM893VBM40S
335 544 320-bit
(8192K x 40) Double-Sided (solder-tabbed) ................. 5-115
TM496TBM40
167 772 160-bit
(4096K x 40) Double-Sided (gold-tabbed) ................... 5-125
TM496TBM40S
167 772 160-bit
(4096K x 40) Double-Sided (solder-tabbed) ................. 5-125
TM892VBM40
335 544 320-bit
(8192K x 40) Double-Sided (gold-tabbed) ................... 5-125
TM892VBM40S
335 544 320-bit
(8192K x 40) Double-Sided (solder-tabbed) ................. 5-125
TM124TBK40
41 943 040-bit
(1 024K x 40) Single-Sided (gold-tabbed) .................... 5-137
TM124TBK40S
41 943 040-bit
(1 024K x 40) Single-Sided (solder-tabbed) .................. 5-137
TM248VBK40
83 886 080-bit
(2048K x 40) Double-Sided (gold-tabbed) ................... 5-137
TM248VBK40S
83 886 080-bit
(2048K x 40) Double-Sided (solder-tabbed) ................. 5-137
5-3
5-4
TM124EU9B,TM124EU9C
1 048 576·WORD BY 9·BIT DYNAMIC RANDOM·ACCESS MEMORY MODULE
SMMS191D-JANUARY 1991-REVISED JANUARY 1993
•
Organization ... 1 048 576 x 9
•
•
•
Single 5-V Power Supply
•
SINGLE IN-LINE MEMORY MODULEt
(TOP VIEW)
30-Pin Single In-Line Memory Module
TM124EU9C •.. Utilizes Three 4-Megabit
Dynamic RAMs in Plastic Small-Outline
J-Lead Packages (SOJs)
•
Long Refresh Period. .. 16 ms
(1024 Cycles)
•
All Inputs, Outputs, Clocks Fully TTL
Compatible
•
•
3-State Outputs
•
TIME
TIME
(tRAC)
(tAA)
(MAX)
'124EU9B/C-6 60 ns
'124EU9B/C-70 70 ns
(MAX)
30 ns
'124EU9B/C-80 80 ns
40 ns
35 ns
OR
VCC
TOLERANCE
WRITE
CYCLE
(MIN)
110 ns
130 ns
150 ns
VCC
CAS
D01
1
2
3
AO
4
A1
D02
A2
A3
VSS
D03
A4
A5
D04
A6
A7
D05
A8
A9
NC
D06
Performance Ranges:
ACCESS ACCESS READ
•
o
TM124EU9B •.. Utilizes Two 4-Megabit and
One 1-Megabit Dynamic RAMs in Plastic
Small-Outline J-Lead Packages (SOJs)
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
ViI
VSS
D07
NC
D08
09
RAS
CAS9
D9
VCC
±S%
±10%
±10%
Low Power Dissipation
Operating Free-Air Temperature Range
O°C to 70°C
description
The TM124EU9B and TM124EU9C are dynamic
random-access memory modules organized as
1048 576 x 9 (bit nine is generally used for parity)
in 30-pin lead less single in-line memory modules
(SIMMs).
D
D
D
o
t The package is shown for pinout reference only.
PIN NOMENCLATURE
AG-A9
CAS, CAS9
D01-D08
D9
NC
09
RAS
VCC
VSS
The TM124EU9B is composed of two TMS44400,
1048 576 x 4-bit dynamic RAMs in 20/26-lead
plastic small-outline J-Iead packages (SOJs), and
one TMS4C1024, 1048576 x1 bit dynamic RAM
in a 20/26-lead plastic small-outline J-Iead
package (SOJ), mounted on a substrate with
decoupling capacitors.
ViI
Address Inputs
Column-Address Strobe
Data In/Data Out
Data In
No Connect
Data Out
Row-Address Strobe
5-V Supply
Ground
Write Enable
The TM124EU9C is composed of two TMS44400, 1 048 576 x 4-bit dynamic RAMs in 20/26-lead plastic
small-outline J-Iead packages (SOJs), and one TMS44100, 4194304 x1 bit dynamic RAM in a 20/26-lead
plastic small-outline J-Iead package (SOJ), mounted on a substrate with decoupling capacitors.
The TM124EU9B and TM124EU9C each feature RAS access times of 60 ns, 70 ns, and 80 ns.
All inputs and outputs, including clocks, are compatible with Series 74 TTL. All address lines and data-in are
latched on-Chip to simplify system design. Data out is unlatched to allow greater system flexibility.
The TM124EU9B and TM124EU9C are characterized for operation from O°C to 70°C.
::
:~~~~~~o~:i: .~!~rrc:~:RlI~~~~!r~~ Ie~:~~~~~~md:~e~
.Iand,rd warranty. Production procelslng do.. not necessarily Include
luting of all plr.met.rI.
TEXAS
~
Copyright © 1993, Texas Instruments Incorporated
INSTRUMENTS
POST OFFICE BOX 1.443· HOUSTON, TEXAS 77001
5-5
TM124EU9B,TM124EU9C
1 048 576·WORD BY 9·BIT DYNAMIC RANDOM·ACCESS MEMORY MODULE
SMMS191 D-JANUARY 1991-REVISED JANUARY 1993
operation
The TM124EU9B operates as two TMS44400s and one TMS4C1024 connected as shown in the functional
block diagram.
The TM124EU9C operates as two TMS44400s and one TMS441 00 connected as shown in the functional block
diagram.
The common I/O features of the TM 124EU9B and TM 124EU9C dictate the use of early write cycles to prevent
contention on the DQ lines.
refresh
The refresh period is extended to 16 milliseconds and, during this period, each ofthe 1024 rows must be strobed
with RAS in order to retain data. CAS can remain high during the refresh sequence to conserve power. For the
TM124EU9B, the nine least significant row addresses (AO-AS) must be refreshed every S ms as required by
the TMS4C1024.
single in-line memory module and components
PC substrate: 1,27 mm (0.05 inch) nominal thickness on contact area
Bypass capacitors: Multilayer ceramic
Contact area for socketable devices: Nickel plate and solder plate over copper.
TEXAS . "
INSTRUMENTS
5-6
POST OFFICE BOX 1443· HOUSTON, TEXAS 77001
TM124EU9B,TM124EU9C
1 048 576·WORD BY 9·BIT DYNAMIC RANDOM·ACCESS MEMORY MODULE
SMMS191 [hJANUARY 1991-REVISED JANUARY 1993
functional block diagram (TM124EU98)
1024K x 4
001
002
003
004
10
AD-A9
RAS
AD-A9
RAS
CAS
Vi
Vi
001
002
003
004
r - OE
I
~ f-
AD-A9
RAS
CAS
Vi
DOS
DOS
006
007
006
007
Doa
Doa
OE
VSS
I
~
09
I
1024K x 4
I
1024K x 1
AD-A9
RAS
CAS
Vi
0
09
0
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
5-7
TM124EU9B, TM124EU9C
1 048 576·WORD BY 9·BIT DYNAMIC RANDOM·ACCESS MEMORY MODULE
SMMS191 D-JANUARY 1991-REVISED JANUARY 1993
functional block diagram (TM124EU9C)
AG-A9
RAS
CAS
1024K x
AG-A9
RAS
CAS
10
W
W
r--
1024K x
AG-A9
RAS
CAS
W
VSS
DQ1
DQ2
DQ3
DQ4
OE
I
10
4
DQ1
DQ2
DQ3
DQ4
I
4
DQ5
DQ6
DQ7
DQS
DQ5
DQ6
DQ7
DQS
OE
I
I
4096K x 1
1 0 - A10
AG-A9
RAS
CAS
W
D9
Q
D
TEXAS
~
INSTRUMENTS
5-8
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
Q9
TM124EU9B, TM124EU9C
1 048 576·WORD BY 9·BIT DYNAMIC RANDOM·ACCESS MEMORY MODULE
SMMS191 D--JANUARY 1991-REVISED JANUARY 1993
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage range on any pin (see Note 1) .......................................... - 1 V to 7 V
Voltage range on Vee ............................................................... - 1 V to 7 V
Short circuit output current ................................................................ 50 mA
Power dissipation .......................................................................... 3 W
Operating free-air temperature range .................................................. O°C to 70°C
Storage temperature range ....................................................... - 55°C to 125°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to VSS.
recommended operating conditions
MIN
NOM
MAX
4.75
5
5.75
V
4.5
5
5.5
V
2.4
6.5
V
-1
O.B
V
70
'c
VCC
Supply voltage (TMI24EU9S-6 and TM 124EU9C-6)
VCC
Supply voltage (TMI24EU9S-70/-BO and TMI24EU9C-70/-BO)
VIH
High-level input voltage
VIL
Low-level input voltage (see Note 2)
TA
Operating free-air temperature
0
..
..
..
NOTE 2: The algebraic convention, where the more negative (less positive) limit IS designated as minimUm,
voltage levels only.
IS
UNIT
used In this data sheet for logic
electrical characteristics over full ranges of recommended operating conditions (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
'124EU9B-6
'124EU9C-6
MIN
VOH
High-level output voltage
10H =-5mA
VOL
Low-level output voltage
10L= 4.2 rnA
II
Input current (leakage)
VI=O to 6.5 V, VCC = 5.5 V,
All other pins = 0 V to VCC
MAX
2.4
'124EU9B-70
'124EU9C-70
MIN
MAX
2.4
'124EU9B-80
'124EU9C-80
MIN
UNIT
MAX
2.4
V
0.4
0.4
0.4
V
±10
±10
±10
IlA
IlA
10
Output current (leakage)
Vo = 0 to VCC, VCC = 5.5 V, CAS high
±10
±10
±10
ICCI
Read or write cycle
current (see Note 3)
Minimum cycle, VCC = 5.5 V
315
270
240
rnA
After 1 memory cycle, RAS and CAS high,
VIH = 2.4 V (TTL)
6
6
6
rnA
After 1 memory cycle, RAS and CAS high,
VIH = VCC - 0.2 V (CMOS)
3
3
3
rnA
ICC2
Standby current
ICC3
Average refresh current
(RAS-only or CSR) (see
Note 3)
Minimum cycle, VCC = 5.5 V, RAS
cycling, CAS high (RAS-only), RAS low
after CAS low (CSR)
315
270
240
rnA
ICC4
Average page
current (see Note 4)
tpc = minimum, VCC = 5.5 V, RAS low,
CAS cycling
270
240
210
rnA
NOTES:
3. Measured with a maximum of one address change while RAS = VIL.
4. Measured with a maximum of one address change while CAS = VIH.
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
5-9
TM124EU9B,TM124EU9C
1 048 576·WORD BY 9·BIT DYNAMIC RANDOM·ACCESS MEMORY MODULE
SMMS191 D-JANUARY 1991-REVISED JANUARY 1993
capacitance over recommended ranges of supply voltage and operating free-air temperature,
f = 1 MHz (see Note 5)
'124EU9B
'124EU9C
PARAMETER
MIN
UNIT
MAX
Ci(A)
Input capacitance, address inputs
15
pF
Ci(W)
Input capacitance, W input
21
pF
Ci(R)
Input capacitance, RAS input
21
pF
Ci(C)
Input capacitance, CAS input
14
pF
pF
Ci(CAS9)
Input capacitance, CAS9 input
7
Ci(DO)
Input capacitance, data inputs/outputs
7
pF
Ci(D9)
Input capacitance, 09 input
5
pF
Co(09)
Output capacitance on 09 output
7
pF
NOTE 5: VCC equal to 5 V
±
0.5 V and the bias on pins under test is 0 V.
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature
'124EU9B-6
'124EU9C-6
PARAMETER
MIN
MAX
'124EU9B-70
'124EU9C-70
MIN
MAX
'124EU9B-80
'124EU9C-BO
MIN
UNIT
MAX
tAA
Access time from column-address
30
35
40
ns
tCAC
Access time from CAS low
15
18
20
ns
tCPA
Access time from column precharge
35
40
45
ns
tRAC
Access time from RAS low
60
70
80
ns
tCLZ
CAS to output in low Z
0
tOFF
Output disable time after CAS high (see Note 6)
0
NOTE 6: toFF
IS
..
specified when the output
IS
no longer dnven.
TEXAS
~
INSfRUMENTS
5-10
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
0
15
0
ns
0
18
0
20
ns
TM124EU98,TM124EU9C
1 048 576·WORD 8Y 9·81T DYNAMIC RANDOM·ACCESS MEMORY MODULE
SMMS191 D-JANUARY 1991-REVISED JANUARY 1993
timing requirements over recommended ranges of supply voltage and operating free·air
temperature
'124EU9B-6
'124EU9C-6
'124EU9B-7O
'124EU9C-7O
'124EU9B-80
'124EU9C-80
MIN
MIN
MIN
MAX
MAX
UNIT
MAX
tRC
Random read or write cycle (see Note 7)
110
130
150
tpc
Page-mode read or write cycle time (see Note 8)
40
45
50
tRASP
Page-mode pulse duration, RAS low
60
100 000
70
100 000
80
100 000
ns
tRAS
Non-page-mode pulse duration, RAS low
60
10 000
70
10 000
80
10 000
ns
tCAS
Pulse duration, CAS low
15
10 000
18
10 000
20
10 000
ns
tcp
Pulse duration, CAS high
10
10
10
ns
tRP
Pulse duration, RAS high (precharge)
40
50
60
ns
twp
Write pulse duration
15
15
15
ns
tASC
Column-address setup time before CAS low
ns
Row-address setup time before RAS low
0
ns
tDS
Data setup time
a
ns
tRCS
Read setup time before CAS low
a
a
a
a
a
tASR
a
a
a
a
0
ns
tCWL
W low setup time before CAS high
15
18
20
ns
tRWL
W low setup time before RAS high
15
18
20
ns
twcs
W low setup time before CAS low
a
a
a
ns
twSR
W high setup time (see Note 11)
10
10
10
ns
twTs
W low setup time (test mode only)
10
10
10
ns
tCAH
Column-address hold time after CAS low
10
15
15
ns
tDHR
Data hold time after RAS low (see Note 9)
50
55
60
ns
tDH
Data hold time
10
15
15
ns
tAR
Column-address hold time after RAS low (see Note 9)
50
55
60
ns
tRAH
Row-address hold time after RAS low
10
10
12
ns
tRCH
Read hold time after CAS high (see Note 10)
a
a
0
ns
tRRH
Read hold time after RAS high (see Note 10)
0
0
0
ns
twCH
Write hold time after CAS low
15
15
15
ns
twCR
Write hold time after RAS low (see Note 10)
50
55
60
ns
twHR
W high hold time (see Note 11)
10
10
10
ns
ns
ns
Continued next page.
NOTES: 7. All cycle times assume tT ~ 5 ns.
8. To assure tpc min, tASC should be greater than or equal to tcp.
9. The minimum value is measured when tRCD is set to tRCD min as a reference.
10. Either tRRH or tRCH must be satisfied for a read cycle.
11. CAS-before-RAS refresh only.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
5-11
TM124EU9B,TM124EU9C
1 048 576·WORD BY 9·BIT DYNAMIC RANDOM-ACCESS MEMORY MODULE
SMMS191 D-JANUARY 1991-REVISED JANUARY 1993
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (concluded)
'124EU9B-6
'124EU9C-6
MIN
MAX
'124EU9B-70
'124EU9C-70
MIN
MAX
'124EU9B-80
'124EU9C-80
MIN
UNIT
MAX
tCHR
Delay time, RAS low to CAS high (see Note 11)
15
15
20
tCRP
Delay time, CAS high to RAS low
0
0
0
ns
tCSH
Delay time, RAS low to CAS high
60
70
80
ns
tCSR
Delay time, CAS low to RAS low (see Note 11)
10
tRAD
Delay time, RAS low to column-address (see Note 12)
15
10
IRAL
Delay time, column-address 10 RAS high
30
35
40
ICAL
Delay time, column address 10 CAS high
30
35
40
tRCD
Delay time, RAS low to CAS low (Seil Note 12)
20
30
45
15
20
10
35
52
17
22
tRPC
Delay time, RAS high to CAS low
0
0
0
IRSH
Delay lime, CAS low 10 RAS high
15
18
20
IREF
Distributed refresh time inlerval
IT
Transition time
16
3
50
16
3
NOTES: 11. CAS-before-RAS refresh only..
12. The maximum value is specified only to assure access time.
device symbolization (on back side of module)
I
0
~
TM124EU9x
-SS
VYMMT
nnnnnnnnnnnnnnnnnnnnnnnnnnnnnn
VY
MM
T
-SS
Year Code
Month Code
Assembly Site Code
Speed Code
NOTE: Location of symbolization may vary.
TEXAS
~
INSTRUMENTS
5-12
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
ns
50
3
ns
40
ns
ns
ns
60
ns
ns
ns
16
ms
50
ns
TM497EAD9B
4194 304·WORD BY 9·BIT DYNAMIC RAM MODULE
SMMS479-DECEMBER 1992
•
•
Organization _.. 4 194 304 x 9
AD SINGLE-IN-LiNE PACKAGEt
(TOP VIEW)
30-Pin Single In-Line Memory Module
(SIMM) for Use With Sockets
•
Utilizes One 4-Megabit and Two 16-Megabit
Dynamic RAMs in Plastic Small-Outline
J-Lead Packages (SOJs)
•
Long Refresh Period. .. 32 ms
(2048 Cycles)
•
All Inputs, Outputs, and Clocks Fully TIL
Compatible
•
•
3-State Outputs
•
0
VCC
CAS
DOl
AO
Al
D02
A2
A3
VSS
D03
A4
A5
D04
A6
A7
D05
A8
A9
Al0
D06
Performance Ranges:
ACCESS
ACCESS
TIME
TIME
READ OR
WRITE
(tRAC)
(MAX)
(tAAl
(MAX)
CYCLE
(MIN)
TM497EAD9B-60
60 ns
15 ns
110 ns
TM497EAD9B-70
70 ns
18 ns
130 ns
TM497EAD9B-80
80 ns
20 ns
150 ns
TM497EAD9B-l0
100 ns
25 ns
180 ns
W
VSS
D07
NC
D08
09
RAS
CAS9
D9
VCC
Common CAS Control for Eight Common
Data-In and Data-Out Lines
•
Separate CAS Control for One Separate
Pair of Data-In and Data-Out Lines
•
•
Low Power Dissipation
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Z
0
-
~
:E
0
a:
0
11.
Z
W
0
Operating Free-Air Temperature Range
O°C to 70°C
0
Z
t The package shown is for pinout reference only.
description
~
C
PIN NOMENCLATURE
The TM497EA09B is a 36M dynamic
random-access memory module organized as
4 194 304 x 9 bits [bit nine (09, 09) is generally
used for parity and is controlled by CAS9] in a
30-pin leadless single in-line memory module
(SIMM).
This module is composed of two TMS417 4000Z,
4 194 304 x 4-bit dynamic RAMs in 24/28-lead
plastic small-outline J-Iead packages (SOJ), and
one TMS441000J, 4194304 x 1-bit dynamic
RAM in a 20/26-lead plastic small-outline J-Iead
package (SOJ), mounted on a substrate with
decoupling capacitors.
AO-Al0
c
~
z
o
m
-z
'497EAD9B-70
MAX
MIN
MAX
'497EAD9B-80
MIN
MAX
'497EAD9B-10
MIN
MAX
UNIT
tcHR
Delay time, RAS low to CAS high
(CAS-before-RAS refresh only)
tcRP
Delay time, CAS high to RAS low
5
5
tcSH
Delay time, RAS low to CAS high
60
70
tcSR
Delay time, CAS low to RAS low
(CAS-before-RAS refresh only)
10
10
10
tRAD
Delay time, RAS low to column-address
(see Note (2)
15
tRAL
Delay time, column-address to RAS high
30
35
40
45
ns
tCAL
Delay time, column address to CAS high
30
35
40
45
ns
tRCD
Delay time, RAS low to CAS low
(see Note (2)
20
tRPC
Delay time, RAS high to CAS low
0
0
0
0
ns
tRSH
Delay time, CAS low to RAS high
15
18
20
25
ns
35
tCPRH
RAS hold time from CAS precharge
tREF
Refresh time interval
IT
Transition time
NOTE 12: The maximum value
20
20
30
45
15
20
3
..
35
52
40
30
20
ns
5
5
ns
80
100
ns
10
ns
15
20
3
30
3
specified only to assure access time .
."
o
l::J
:s::
~
TM497EAD9B
-SS
VYMMT
o
=
VY
Year Code
MM = Month Code
T = Assembly Site Code
-SS = Speed
o
z
NOTE: The location of the part number may vary.
TEXAS
~
INSTRUMENTS
5-20
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
60
20
20
50
75
30
3
ns
ns
ns
50
32
device symbolization
o
40
45
32
32
IS
20
32
ms
30
ns
TM497MBK36A, TM497MBK36Q
4 194 304 BY 36·BIT
DYNAMIC RAM MODULE
SMMS446A-DECEMBER 1992-REVISED JANUARY 1993
•
Organization ... 4194 304 x 36
•
Single 5-V Power Supply (±10% Tolerance)
•
•
•
Performance Ranges:
ACCESS ACCESS ACCESS
TIME
TIME
OR
tRAC
tCAC
tAA
WRITE
(MAX)
(MAX)
(MAX)
(MIN)
TM497MBK36A-60
60 ns
15 ns
30 ns
110 ns
TM497MBK36A-70
70 ns
18 ns
35 ns
130 ns
TM497MBK36A-80
80 ns
20 ns
40 ns
150 ns
72-Pln Single In-Line Memory Module
(SIMM) for Use With Sockets
CYCLE
Utilizes Eight 16-Megablt Dynamic RAMs In
Plastic Smail-Outline J-Lead (SOJ)
Packages and Four 4-Megabit Dynamic
RAMs In Plastic Small-Outline J-Lead (SOJ)
Packages
•
Low Power Dissipation
•
Long Refresh Period ••. 32 ms
(2048 Cycles)
•
Operating Free-Air Temperature
Range ... O°C to 70°C
•
All Inputs, Outputs, Clocks Fully TTL
Compatible
•
Presence Detect
•
3-State Output
•
Gold-Tabbed Version Available: t
TM497MBK36A
•
Common CAS Control for Nine Common
Data-In and Data-Out Lines, in Four Blocks
Separate RAS Control for Eighteen Data-In
and Data-Out Lines, in Two Blocks
•
Tin-Lead (Solder) Tabbed Version
Available:
TM497MBK36Q
•
READ
TIME
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description
The TM497MBK36A is a 144M dynamic random-access memory organized as four times 4 194 304 x 9 (bit 9
is generally used for parity) in a 72-pin lead less single in-line memory module (SIMM). The SIMM is composed
of eight TMS417400DZ, 4194304 x 4-bit dynamic RAMs, each in 24/28-lead plastic small-outline J-Iead
packages (SOJs), and four TMS44100DJ, 1 048576 x 4-bit dynamic RAMs, each in 20/26-lead plastic
small-outline J-Iead packages (SOJs) mounted on a substrate with decoupling capaCitors. Each TMS417400DZ
and TMS44100DJ is described in the TMS417400 and TMS44100 data sheets (respectively).
The TM497MBK36A is available in a double-sided BK leadless module for use with sockets.
The TM497MBK36A features RAS access times of 60 ns, 70 ns, and 80 ns. This device is characterized for
operation from O°C to 70°C.
operation
The TM497MBK36A operates as eight TMS417400DZs and four TMS44100DJs connected as shown in the
functional block diagram and Table 1. Refer to the TMS417400 and TMS44100 data sheets for details of
operation. The common I/O feature dictates the use of early write cycles to prevent contention on 0 and Q.
specifications
The refresh period is extended to 32 milliseconds and, during this period, each of the 2048 rows must be strobed
with RAS in order to retain data. Address line A 10 must be used as most significant refresh address line (lowest
frequency) to assure correct refresh for both TMS417400 and TMS441 00. AD-A9 address lines must be
refreshed every 16 ms as required by the TMS441 00 DRAM. CAS can remain high during the refresh sequence
to conserve power.
t Part numbers in this data sheet refer only to the gold-tabbed version; the information applies to both gold-tabbed and solder-tabbed versions.
TEXAS
~
Copyright © 1993. Texas Instruments Incorporated
INSTRUMENTS
POST OFFICE BOX 1443' HOUSTON. TEXAS 77001
5-21
a:
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«
TM497MBK36A, TM497MBK36Q
4 194 304 BY 36·BIT
DYNAMIC RAM MODULE
SMMS446A-DECEMBER 1992-REVISED JANUARY 1993
BK SINGLE·IN·LINE PACKAGET
TM497MBK36AT
(TOP VIEW)
(SIDE VIEW)
vss c:::::>
c:::::>
0018 c:::::>
001
c:::::>
0019 c:::::>
002 c:::::>
0020 c:::::>
0Q3 c:::::>
0021
c:::::>
VCC c:::::>
NC c:::::>
AO c:::::>
A1
c:::::>
A2 c:::::>
A3 c:::::>
A4 c:::::>
AS c:::::>
A6 c:::::>
A10 c:::::>
0D4 c:::::>
0022 c:::::>
DOS c:::::>
0023 c:::::>
DOS c:::::>
0024 c:::::>
007 c:::::>
0025 c:::::>
A7 c:::::>
NC c:::::>
VCC c:::::>
A8 c:::::>
A9 c:::::>
NC c:::::>
RAS2 c:::::>
0026 c:::::>
oaa c:::::>
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
c:::::>
c:::::>
c:::::>
c:::::>
c:::::>
c:::::>
c:::::>
c:::::>
c:::::>
c:::::>
W c:::::>
NC c:::::>
oaa c:::::>
0027 c:::::>
0010 c:::::>
0028 c:::::>
0011
c:::::>
OQ29 c:::::>
0012 c:::::>
0030 c:::::>
0013 c:::::>
0031
c:::::>
VCC c:::::>
0032 c:::::>
0014 c:::::>
0033 c:::::>
0015 c:::::>
0034 c:::::>
0016 c:::::>
NC c:::::>
P01
c:::::>
P02 c:::::>
P03 c:::::>
P04 c:::::>
NC c:::::>
VSS c:::::>
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
58
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
DOC
»
C
~
Z
0
m
-Z
"0lJ
0017
0035
VSS
CASO
CAS2
CAS3
CAS1
RASO
NC
NC
3:
~
0
Z
e
D
D
D
D
D
D
D
D
e
PIN NOMENCLATURE
AO-A1D
CASO-CAS3
Address Inputs
Column·Address Strobe
000-007,009-0016,0018-0025,
0027-0034
Data In/Data Out
008, 0017, 0026, 0035
Parity
No Connection
Presence Detects
Row·Address Strobe
5-V Supply
Ground
Write Enable
NC
P01-P04
RASO, RAS2
VCC
VSS
W
PRESENCE DETECT
SIGNAL
(PIN)
TM497MBK36A
PD2
(68)
PD3
(69)
PD4
(70)
VSS
80 ns
VSS
NC
NC
70 ns
VSS
NC
VSS
NC
60 ns
VSS
NC
NC
NC
t The packages shown here are for pinout reference only and are not drawn to scale.
TEXAS ~
INSTRUMENTS
5-22
PD1
(67)
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
TM497MBK36A, TM497MBK36Q
4 194 304 BY 36·BIT
DYNAMIC RAM MODULE
SMMS446A-DECEMBER 1992-REVISED JANUARY 1993
Table 1. Connection Table
DATA BLOCK
RASx
CASx
RAse
CAse
009-0016
0017
RAse
CAS1
0018-0025
0026
RAS2
CAS2
0027-0034
0035
RAS2
CAS3
00Q-007
OOS
single in·line memory module and components
PC substrate: 1,27 ± 0,1 mm (0.05 inch) nominal thickness; 0.005 inch/inch maximum warpage
Bypass capacitors: Multilayer ceramic
Contact area for TM497MBK36A: Nickel plate and gold plate over copper
Contact area for TM497MBK36Q: Nickel plate and tin-lead over copper
z
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TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
5-23
NOIJ."I/\U:lO.:lNI 30N"AC"
~
cnC.I:oo ......
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t».1:00 eo
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o_oS:
functional block diagram
~o.l:oom
m
m:u
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m""" (.) 0)
~=-O)}>
11
AO-A
1llS:' ......
RA:
CA:
CAS1-
1-
4Mx4
~ AO-Al0
RAS
2l
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OQ1OQ4
a a::
~ft1
~
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~
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"-
OQ7
Q
~ OQl3-
"-
I
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OQ8
I
~
~
OE
OQ1OQ4
~
..1
4M xl
~ AO-Al0
RAS
4Mxl
~W
W
~ CAS
Q
OQ1OQ4 "'-OC 1DC 34
OQ22--=0Q25
~ AO-Al0
RAS
-=±
I
OQ17
1
------t:::,
Q
0
4Mx4
AO-Al0
RAS
W
" CAS
.....
OE
CAS
OQ16
~
-----;:: W
CAS
0
4Mx4
AO-Al0
RAS
-:!:-
4M xl
AO-Al0
RAS
~W
OQ1OQ4 4+-0C '7DC 30
-:!:-
~W
"-
OQ1OQ4
4M xl
AO-Al0
RAS
CAS
0
~
CAS
OE
CAS
...... OE
OQ1OQ4 .... OQl8OQ21
-.:!::-
4Mx4
AO-Al0
RAS
OQ1-~OQ4- -=OQ4
I
OE
~
±"
.... CAS
OE
~W
.... CAS
4Mx4
~ AO-Al0
RAS
w
±
CAS
OQ1.... OQ9OQ4
OQ12
.... w
~
4Mx4
~ AO-Al0
RAS
w
......
W
-:!:-
4Mx4
AO-Al0
OE
CAS3-
4Mx4
AO-Al0
RAS
OQ3
~~AS
~
CAS2-
~
~...... w
CAS
£j
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RAS2
I
OQ26
I
CAS
0
Q
I
OQ35
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TM497MBK36A, TM497MBK36Q
4 194 304 BY 36·BIT
DYNAMIC RAM MODULE
SMMS446A-OECEMBER 1992--REVISED JANUARY 1993
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Voltage range on any pin (see Note 1) ................................................. -1 V to 7 V
Voltage range on Vee (see Note 1) ................................................... - 1 V to 7 V
Short circuit output current ................................................................ 50 mA
Power dissipation ......................................................................... 12 W
Operating free-air temperature range .................................................. O°C to 70°C
Storage temperature range ....................................................... - 55°C to 125°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. This is a stress rating only, and
functional operation of the device at these or any other conditions beyond those indicated in the "recommended operating conditions· section of
this specification is not implied. Exposure to absolute-maxim urn-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to VSS.
recommended operating conditions
MIN
NOM
MAX
VCC
Supply voltage
4.5
5
5.5
VIH
High-level input voltage
2.4
6.5
V
VIL
LOW-level input voltage (see Note 2)
-1
0.8
V
TA
Operating free-air temperature
0
70
'c
NOTE 2:
UNIT
V
..
..
..
The algebraiC convention, where the more negative (less positive) limit IS deSignated as minimUm, IS used In thiS data sheet for logiC
~~~
electrical characteristics over full ranges of recommended operating conditions (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
VOH
High-level output voltage
IOH=-5mA
VOL
loW-level output voltage
IOL=4.2mA
II
Input current (leakage)
VI = 0 to 6.5 V, VCC = 5.5 V,
All other pins = 0 V to V CC
10
Output current (leakage)
ICCI
Read or write cycle current
(see Note 3)
ICC2
Standby current
'497MBK36A-60
MIN
MAX
2.4
'497MBK36A-70
MIN
MAX
'497MBK36A-80
MIN
MAX
V
2.4
2.4
UNIT
0.4
0.4
± 120
± 120
± 120
jlA
Vo =OtoVCC,
VCC = 5.5 V, CAS high
±10
±10
±10
jlA
Minimum cycle, VCC = 5.5 V
1480
1240
1120
rnA
After 1 memory cycle, RAS and
CAS high, VIH = 2.4 V (TTL)
24
24
24
rnA
After 1 memory cycle, RAS and
CAS high, VIH = VCC - 0.2 V
(CMOS)
12
12
12
rnA
V
Average refresh current
(RAS-only or CBR)
(see Note 3)
Minimum cycle, VCC = 5.5 V,
RAS cycling, CAS high
(RAS-only); RAS low after
CAS low (CBR)
1480
1240
1120
rnA
ICC4
Average page current
(see Note 4)
tpc = minimum, VCC = 5.5 V,
RAS low, CAS cycling
920
800
680
rnA
3. Measured with a maximum of one address change while RAS = VIL.
4. Measured with a maximum of one address change while CAS = VIH.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
-
~
:2:
a:
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0.4
ICC3
NOTES:
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5-25
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«
TM497MBK36A, TM497MBK36Q
4 194 304 BY 36·BIT
DYNAMIC RAM MODULE
SMMS446A-DECEMBER 1992-REVISED JANUARY 1993
capacitance over recommended ranges of supply voltage and operating free·alr temperature,
f = 1 MHz (see Note 5)
PARAMETER
MIN
TYP
MAX
UNIT
Ci(A)
Input capacitance, address inputs
60
Ci(C)
Input capacHance, CAS inputs
21
pF
pF
Ci(R)
Input capacHance, RAS inputs
42
pF
Ci(W)
Input capacitance, write-enable input
84
pF
Co(DO)
Output capacitance on DO pins
7
pF
Co(MP)
Output capacitance on MP pins
12
pF
NOTE 5: VCC equal to 5 V,. 0.5 V and the bias on pinS under test IS 0 V.
switching characteristics over recommended ranges of supply voltage and operating free·air
temperature
'497MBK36A~O
PARAMETER
»
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oz
MIN
MAX
'497MBK36A-70
MIN
MAX
'497MBK36A-80
MIN
MAX
UNIT
tAA
Access time from column-address
30
35
40
tCAC
Access time from CAS low
15
18
20
ns
tePA
Access time from column precharge
35
40
45
ns
tRAC
Access time from RAS low
80
ns
teLZ
CAS to output in low Z
0
0
0
ns
toH
Output disable; start of CAS high
3
3
3
ns
tOFF
Output disable time after CAS high (see Note 6)
0
70
60
15
0
18
0
20
ns
ns
NOTE 6: tOFF IS speCified when the output IS no longer driven.
timing requirements over recommended ranges of supply .voltage and operating free-air
temperature
'497MBK36A-60
'497MBK36A-70
MIN
MIN
MAX
MAX
' 497MBK36A-80
MIN
MAX
UNIT
tRC
Random read or write cycle (see Note 7)
110
130
150
tpc
Page-mode read or write cycle time (see Note 8)
40
45
50
tRASP
Page-mode pulse duration, RAS low
60
100000
70
100000
80
100000
ns
tRAS
Non-page-mode pulse duration, RAS low
60
10000
70
10 000
80
10000
ns
tCAS
Pulse duration, CAS low
15
10000
18
10000
20
10000
ns
tcp
Pulse duration, CAS high
10
10
10
tRP
Pulse duration, RAS high (precharge)
40
50
60
ns
twp
Write pulse duration
15
15
15
ns
ns
ns
ns
tASC
Column-address setup time before CAS low
0
0
0
ns
tASR
Row-address setup time before RAS low
0
0
0
ns
tDS
Data setup time
0
0
0
ns
tRCS
Read setup time before CAS low
0
0
0
ns
teWL
W-Iow setup time before CAS high
15
18
20
ns
tRWL
W-Iow setup time before RAS high
15
18
20
ns
twcs
W-Iow setup time before CAS low
0
0
0
ns
twSR
W-high setup time (CAS-before-RAS refresh only)
10
10
10
ns
NOTES:
=
7. All cycles assume IT 5 ns.
8. To guarantee tpc min, tASC should be greater than or equal to tep.
TEXAS
~
INsrRUMENTS
5-26
POST OFFICE BOX 1443 • HOUSTON. TEXAS nOO1
TM497MBK36A, TM497MBK36Q
4 194 304 BY 36·BIT
DYNAMIC RAM MODULE
SMMS446A-DECEMBER 1992-REVISED JANUARY 1993
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (concluded)
'497MBK36A-60
MIN
MAX
'497MBK36A·70
'497MBK36A·80
MIN
MIN
MAX
MAX
UNIT
tCAH
Column-address hold time after CAS low
15
15
15
ns
tDH
Data hold time
15
15
15
ns
tRAH
Row-address hold time after RAS low
10
10
10
ns
tRCH
Read hold time after CAS high (see Note 10)
0
0
0
ns
tRRH
Read hold time after RAS high (see Note 10)
5
5
5
ns
twCH
Write hold time after CAS low
15
15
15
ns
twHR
W-high hold time (CAS-before-RAS refresh only)
10
10
10
ns
tCHR
Delay time, RAS low to CAS high (CAS-before-RAS
refresh only)
20
20
20
ns
tCRP
Delay time, CAS high to RAS low
5
5
5
ns
tCSH
Delay time, RAS low to CAS high
60
70
80
ns
tCSR
Delay time, CAS low to RAS low (CAS-before-RAS
refresh only)
10
10
10
ns
tRAD
Delay time, RAS low to column-address (see Note 12)
15
tRAL
Delay time, column-address to RAS high
30
35
40
tCAL
Delay time, column-address to CAS high
30
35
40
tRCD
Delay time, RAS low to CAS low (see Note 12)
20
tRPC
Delay time, RAS high to CAS low
0
0
0
ns
tRSH
Delay time, CAS low to RAS high
15
18
20
ns
35
tCPRH
RAS hold time from CAS precharge
tREF
Refresh time interval
IT
Transition time
NOTES:
30
45
15
20
. .
52
40
32
3
35
30
15
20
30
3
ns
ns
ns
60
45
32
3
40
ns
ns
32
ms
30
ns
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9. Either tRRH or tRCH must be sallSfled for a read cycle .
10. The maximum value is specified only to guarantee access time.
«
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS nOOl
5-27
TM497MBK36A, TM497MBK36Q
4 194 304 BY 36·BIT
DYNAMIC RAM MODULE
SMMS446A-DECEMBER 1992--f1EVISED JANUARY 1993
device symbolization
0000000000
TM497MBK36A
YY
= Year Code
MM .. Month Code
T .. Assembly Slte,Code
- SS .. Speed Code
NOTE: location of symbolization may vary.
l>
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INSTRUMENTS
5-28
POST OFFICE BOX 1443 • HOUSTON. TEXAS nool
TM124BBK32, TM124BBK32S 1 048576 BY 32·BIT DYNAMIC RAM MODULE
TM248CBK32, TM248CBK32S 2 097 152 BY 32·BIT DYNAMIC RAM MODULE
SMMS132C-JANUARY 199.1-REVISED DECEMBER 1992
•
Organization
TM124BBK32 .•• 1048576 x 32
TM248CBK32 .•• 2 097 152 x 32
• Performance Ranges:
ACCESS
ACCESS
TIME
TIME
READ
OR
WRITE
•
Single 5-V Power Supply (±10 % Tolerance)
tRAC
tCAC
•
72-pln Single In-Line Memory Module
(SIMM) for Use With Sockets
(MAX)
(MAX)
(MIN)
TM124BBK32-60
60 ns
15 ns
110 ns
•
•
TM124BBK32-Utilizes Eight 4-Megabit
Dynamic RAMs In Plastic Small-Outline
J-Lead (SOJ) Packages
TM248CBK32-Utilizes Sixteen 4-Megabit
Dynamic RAMs in Plastic Small-Outline
J-Lead (SOJ) Packages
CYCLE
TM124BBK32-70
70 ns
18 ns
130 ns
TM124BBK32-80
80 ns
20 ns
150 ns
TM248CBK32-60
60 ns
15 ns
110 ns
TM248CBK32-70
70 ns
18 ns
130 ns
TM248CBK32-80
80 ns
20 ns
150 ns
• Low Power Dissipation
• Operating Free-Air-Temperature
Range ... O°C to 70°C
•
Distributed Refresh Period ... 16 ms
(1024 Cycles)
•
All Inputs, Outputs, Clocks Fully TTL
Compatible
•
3-State Output
•
Common CAS Control for Eight Common
Data-In and Data-Out Lines, In Four Blocks
• Gold-Tabbed Versions Available:t
- TM124BBK32
- TM248CBK32
• Tin-Lead (Solder) Tabbed Versions
Available:
- TM124BBK32S
- TM248CBK32S
• Presence Detect
description
TM124BBK32
The TM124BBK32 is a dynamic random-access memory organized as four times 1 048576 x 8 in a 72-pin
lead less single in-line memory module (SIMM). The SIMM is composed of eight TMS44400,
1 048576 x 4-bit dynamic RAMs, each in 20/26-lead plastic small-outline J-Iead packages (SOJs), mounted
on a substrate together with decoupling capacitors. Each TMS44400 is described in the TMS44400 data sheet.
The TM124BBK32 is available in the single-sided BK lead less module for use with sockets.
The TM124BBK32 features RAS access times of 60 ns, 70 ns and 80 ns. This device is rated for operation from
O°C to 70°C
TM248CBK32
The TM248CBK32 is a dynamic random-access memory organized as four times 2 097 152 x 8 in a 72-pin
leadless single in-line memory module (SIMM). The SIMM is composed of sixteen TMS44400,
1 048576 x 4-bit dynamic RAMs, each in 20/26-lead plastic small-outline J-Iead packages (SOJs), mounted
on a substrate together with decoupling capacitors. Each TMS44400 is described in the TMS44400 data sheet.
The TM248CBK32 is available in the double-sided BK leadless module for use with sockets.
The TM248CBK32 features RAS access times of 60 ns, 70 ns and 80 ns. This device is rated for operation from
O°C to 70°C
t Part numbers in this data sheet are for the gold-tabbed version; the information applies to both gold-tabbed and solder-tabbed versions.
::
~~o~~~~T~~o:1: .~!~::~~~.lIpe~~:~!r~~ Ie~~~~~~~~m~~~
atandard wananty. Production processing do.. not necellarlly Include
teltlng of ,II p.r.m.te....
TEXAS
~
Copyright © 1992, Texas Instruments Incorporated
INsrRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
5-29
TM124BBK32, TM124BBK32S 1 048576 BY 32·BIT DYNAMIC RAM MODULE
TM248CBK32, TM248CBK32S 2 097152 BY 32·BIT DYNAMIC RAM MODULE
SMMS132C--JANUARY 1991-REVISED DECEMBER 1992
operation
TM124BBK32
The TM124BBK32 operates as eight TMS44400DJs connected as shown in the functional block diagram. Refer
to the TMS44400 data sheet for details of operation. The common I/O feature of the TM 124BBK32 dictates the
use of early write cycles to prevent contention on D and Q.
TM248CBK32
The TM248CBK32 operates as sixteen TMS44400DJs connected as shown in the functional block diagram.
Refer to the TMS44400 data sheet for details of operation. The common I/O feature of the TM248CBK32
dictates the use of early write cycles to prevent contention on D and Q.
refresh
Refresh period is extended to 16 milliseconds and, during this period, each of the 1024 rows must be strobed
with RAS in order to retain data. AO-A9 address lines must be refreshed every 16 ms as required by the
TMS44400 DRAM. CAS can remain high during the refresh sequence to conserve power.
single in-line memory module and components
PC substrate: 1,27 ± 0,1 mm (0.05 inch) nominal thickness; 0.005 inch/inch maximum warpage
Bypass capacitors: Multilayer ceramic
Contact area for TM124BBK32 AND TM248CBK32: Nickel plate and gold plate over copper.
Contact area for TM124BBK32S AND TM248CBK32S: Nickel plate and tin-lead over copper.
TEXAS ~
INSTRUMENTS
5-30
POST OFFICE BOX 1443· HOUSTON. TEXAS 77001
TM124BBK32, TM124BBK325 1 048576 BY 32·BIT DYNAMIC RAM MODULE
TM248CBK32, TM248CBK325 2 097 152 BY 32·BIT DYNAMIC RAM MODULE
SMMS132C-JANUARY 1991-REVISED DECEMBER 1992
BK SINGLE IN-LINE MEMORY MODULE
TM124BBK32T
TM248CBK32T
(TOP VIEW)
(SIDE VIEW)
(SIDE VIEW)
G
vss
000
0016
001
0017
002
0018
003
0019
VCC
NC
AD
Al
L::)
L::)
L::)
L::)
L::)
L::)
L::)
L::)
L::)
L::)
L::)
L::)
1
2
3
4
5
6
7
8
9
10
11
12
§13
14
15
L::) 16
L::) 17
L::) 18
L::) 19
L::) 20
L::) 21
L::) 22
L::) 23
L::) 24
L::) 25
L::) 26
L::) 27
L::) 28
L::) 29
L::) 30
L::) 31
-.M. L::) 32
RAS3 L::) 33
RAS2 L::) 34
NC L::) 35
NC L::) 36
A2
A3
A4
AS
A6
NC
004
0020
005
0021
006
0022
007
0023
A7
NC
VCC
AS
NC
NC
Vss
CASO
CAS2
CAS3
CASl
RASO
RASl
fig
W
NC
008
0024
009
0025
0010
0026
0011
0027
0012
0028
VCC
0029
0013
0030
0014
0031
0015
NC
POl
P02
P03
P04
NC
VSS
L::)
L::)
L::)
L::)
L::)
L::)
L::)
L::)
L::)
L::)
§
37
38
39
40
41
42
43
44
45
46
47
48
49
L::) 50
L::) 51
L::) 52
L::) 53
L::) 54
L::) 55
L::) 56
L::) 57
L::) 58
L::) 59
L::) 60
L::) 61
L::) 62
L::) 63
L::) 64
L::) 65
L::) 66
L::) 67
L::) 68
L::),69
L::) 70
L::) 71
L::) 72
CJ
CJ
CJ
CJ
PIN NOMENCLATURE
CJ
CJ
CJ
CJ
G
Address Inputs
Column-Address Strobe
Data In/Data Out
No Connection
Presence Detects
Row-Address Strobe
5-V Supply
Ground
Write Enable
AO-A9
CASO-CAS3
DQO-DQ31
NC
PD1- PD4
RASO-RAS3
VCC
VSS
W
PRESENCE DETECT
SIGNAL
(PIN)
TM124BBK32
TM248CBK32
PD1
(67)
PD2
(68)
PD3
(69)
PD4
(70)
VSS
80 ns
VSS
VSS
NC
70 ns
VSS
VSS
VSS
NC
60 ns
VSS
VSS
NC
NC
80 ns
NC
NC
NC
VSS
70 ns
NC
NC
VSS
NC
60 ns
NC
NC
NC
NC
t The packages shown here are for pinout reference only and are not drawn to scale.
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
5-31
;:
;:
-f-f
~
om
mm
'"
functional block diagram (for TM124BBK32 and TM248CBK32, Side 1)
'"
("
N
!!?
'",.,
~
c
3:3:
N .....
~N
CD~
GG
~ _N_N
-f-f
1'" 3:3:
N .....
AG-A!- 10
<0
RAS2
RA
~1 -
~N
CD~
m
m
GG
III
m
cncn
co
N .....
00
'" om
mm
0
0
CAS3-
CAS2-
CAS1-
m
s;
m
0
1M x4
AO-A9
RAS
~ Vi
~
---;: Vi
Z
~d
.......
~
~i
~
~.... Vi
f..- OQO-
OQ1#OQ8OQ4
OQ11
-:!=-
OQ3
"-
.....
OE
OQ1OQ4 #OQ16OQ19
-J,-
JJ
~..... ViCAS
CAS
.... CAS
OE
OE
~
;:
1Mx4
AO-A9
RAS
<0
'"
OE
OQ1OQ4
-:!=-
OQ24OQ27
I
NN
CD
~
' " CD
.....
C11
C11
'"
NO)
mm
-<-<
..
(,,) (,,)
~
~ 1Mx4
1M x4
AO-A9
RAS
----.:.r::,.
L± Vi
~
~4r
---;:
CAS
OQ1OQ4
1M x4
AO-A9
RAS
1M x 4
AO-A9
RAS
~
~
OQ1- ...... OQ4OQ7
OQ4
AO-A9
~AS
"W
" CAS
-:!:-
~
10
b
OQ1-......
_
OQ4
0012- 0015
L-...r::,. ~AS
--DoW
" CAS
~
NN
1Mx4
AO-A9
RAS
~
~ Vi
CAS
AO-A9
-----1:::,.
CAS
OE
~ 1Mx4
~
OQ1- ...... I
_
OQ4
OQ20-OQ23
.......
mm
=i=i
cc
-<-<
OE
OQ1OQ4
OQ28OQ31
I
ZZ
»»
3:3:
00
::0::0
»»
3:3:
3:3:
00
cc
C:C:
II
mm
functional block diagram (for TM248CBK32, Side 2)
AO-A~10
RAS3
RA'
-i-i
3:3:
-
CA:
CAS1-
;~Z
i~
"-
~
~.~~d
g~
~
OQ1.... OQGOQ4
OQ3
~
~
"-
CAS
"-
OE
OQ1OQ4
1M x 4
AG-A9
RAS
~
~ Vi
~ Vi
CAS
OE.
1M x4
AG-A9
RAS
~008- ~
"- CAS
"- OE
OQ1OQ4
OOJ
OJ OJ
e.,)e.,)
,!') _N
-i-i
~ Vi
~OQl6-- f
3:3:
r- CAS
r- OE
OQ1- ...
OQ4
OQ19
0011
""
1M x4
AG-A9
RAS
N .....
"""N
0I),J:o.
OOJ
OJ OJ
OQ24OQ27
""
en en
e.,)e.,)
~
--=±
~
lMx4
~ AG-A9
-.J:::,. ~AS
alTJ
z2!
~ (j]4r
"-
CAS3-
CAS2-
~
~ Vi
"
g
....
o
1M x 4
AG-A9
RAS
N .....
,J:o.N
0I),J:o.
"w
"
~
CAS
OE
OQ1- "'OQ4OQ4
OQ7
J7
"
"-
~
~ Vi
1M x4
AG-A9
RAS
Vi
~
CAS
OE
OQ1- . . . 0012OQ4
OQ15
~
1M x4
AG-A9
RAS
~
CAS
OE
OQ1OQ4 .... OQ2G0Q23
~
NN
1M x4
AG-A9
RAS
N .....
~ Vi
~ CAS
OE
OQ1- ...
OQ4
00
CD ,J:o.
...... (1)
..... U1
U1 ......
Nen
OQ28OQ31
10>;::
;::
~
'"
N
~
»z
c
»
:5!
<0
<0
OJ OJ
-<-<
e.,) e.,)
..
NN
OJ OJ
:::::j:::::j
CC
-<-<
zz
:1>:1>
3:3:
1 00
~
(j;
m
0
0
m
0
m
;::
III
m
:IJ
'"
'"'"
<0
<0
N
::x:J::x:J
:1>:1>
3:3:
3:3:
00
CC
CC
II
mm
TM124BBK32, TM124CBK32S 1 048576 BY 32·BIT DYNAMIC RAM MODULE
TM248CBK32, TM248CBK32S 2 097152 BY 32·BIT DYNAMIC RAM MODULE
SMMSI32C-JANUARYI991-REVISED DECEMBER 1992
absolute maximum ratings over operating free·air temperature range (unless otherwise noted}t
Voltage range on any pin (see Note 1) ................................................. - 1 V to 7 V
Voltage range on Vee (see Note 1) ................................................... - 1 V to 7 V
Short circuit output current ................................................................ 50 rnA
Power dissipation ....................................................... " . . . . . . . . . . . . . . . . .. 8 W
Operating free-air temperature range .................................................. DoC to 70°C
Storage temperature range ....................................................... - 55°C to 125°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with .respect to VSS.
recommended operating conditions
MIN
NOM
MAX
VCC
Supply voltage
4.5
5
5.5
UNIT
V
VIH
High-level input voltage
2.4
6.5
V
VIL
Low-level input voltage (see Note 2)
-1
0.8
V
70
Operating free-air temperature
0
'c
TA
NOTE 2: The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used in this data sheet for logic
voltage levels only.
electrical characteristics over full ranges of recommended operating conditions (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
'124BBK32-60
MIN
MAX
2.4
'124BBK32-70
MIN
MAX
2.4
'124BBK32·80
MIN
MAX
2.4
UNIT
VOH
High-level output voltage
10H =-5 mA
VOL
Low-level output voltage
IOL=4.2 mA
0.4
0.4
0.4
V
V
II
Input current (leakage)
VI = 0 to 6.5 V, VCC = 5 V,
All other pins = 0 to VCC
±10
±10
±10
IJA
10
Output current (leakage)
Vo = 0 to VCC, VCC = 5.5 V,
CAS high
±10
±10
±10
IJA
ICCI
Read or write cycle current
(see Note 3)
Minimum cycle, VCC = 5.5 V
840
720
640
mA
16
16
16
8
8
8
840
720
640
mA
720
640
560
mA
After 1 memory cycle,
RAS and CAS high,
ICC2
Standby current
VIH=2.4 V (TTL)
mA
After 1 memory cycle,
RAS and CAS high,
VIH = VCC - 0.2 V (CMOS)
Minimum cycle, VCC = 5.5 V,
RAS cycling,
ICC3
Average refresh current
(RAS-only or CBR) (see Note 3)
CAS high (RAS-only),
ICC4
Average page current
(see Note 4)
tpc = minimum, VCC = 5.5 V,
RAS low, CAS cycling
RAS low after CAS low (CBR)
NOTES:
3. Measured With a maximum of one address change while RAS = VIL.
4. Measured with a maximum of one address chenge while CAS = VIH.
TEXAS
~
INSTRUMENTS
5-34
POST OFFICE BOX 1443· HOUSTON, TEXAS 77001
TM124BBK32, TM124CBK32S 1 048576 BY 32-BIT DYNAMIC RAM MODULE
TM248CBK32, TM248CBK32S 2 097 152 BY 32-BIT DYNAMIC RAM MODULE
SMMS132C-JANUARY 1991-REVISED DECEMBER 1992
electrical characteristics over full ranges of recommended operating conditions (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
'248CBK32-60
MIN
MAX
2.4
'248CBK32-70
MIN
MAX
2.4
'248CBK32-80
MIN
MAX
VOH
High-level output voltage
10H =-5 mA
VOL
Low-level output voltage
IOL=4.2 mA
0.4
0.4
0.4
V
II
Input current (leakage)
VI = 0 to 6.5 V, VCC = 5 V,
All other pins = 0 to VCC
±20
±20
±20
~
10
Output current (leakage)
Va = 0 to VCC, VCC = 5.5 V,
CAS high
±20
±20
±20
~
ICCI
Read or write cycle current
(see Note 3)
Minimum cycle, VCC = 5.5 V
856
736
656
mA
32
32
32
16
16
16
1680
1440
1280
mA
736
656
576
mA
After 1 memory cycle,
RAS and CAS high,
ICC2
Standby current
V
VIH=2.4 V (TTL)
mA
After 1 memory cycle,
RAS and CAS high,
VIH = VCC - 0.2 V (CMOS)
ICC3
Average refresh current
(RAS-only or CBR) (see Note 3)
Minimum cycle, VCC = 5.5 V,
RAS cycling,
CAS high (RAS-only),
RAS low after CAS low (CBR)
ICC4
Average page current
(see Note 4)
tpc = minimum, VCC = 5.5 V,
RAS low, CAS cycling
NOTES:
2.4
UNIT
3. Measured with a maximum of one address change while RAS = VIL.
4. Measured with a maximum of one address change while CAS = VIH.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
5-35
TM124BBK32, TM124CBK32S 1 048576 BY 32-BIT DYNAMIC RAM MODULE
TM248CBK32, TM248CBK32S 2 097 152 BY 32-BIT DYNAMIC RAM MODULE
SMMSI32G-JANUARY 1991-REVISED DECEMBER 1992
capacltanoe over recommended ranges of supply voltage and operating free-air temperature
f = 1 MHz (see Note 5)
'124BBK32
MIN
'248CBK32
MAX
MIN
MAX
UNIT
CilAl
Input capacitance, address inputs
40
80
pF
Ci(Rl
Input capacitance, RAS
28
28
pF
CiCCI
Input capacitance, CAS
14
28
pF
CilWl
Input capacitance, write-enable input
56
112
pF
Co (DO)
Output capacitance on DO pins
7
14'
pF
NOTE 5: VCC equal to 5 V '" 0.5 V and the bias on
PinS
under test
IS
0 V.
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature
'124BBK32-60
'248CBK32-60
PARAMETER
MIN
MAX
'124BBK32-70
'248CBK32-70
MIN
MAX
'124BBK32-80
'248CBK32-80
MIN
UNIT
MAX
tAA
Access time from column-address
30
35
40
ns
tCAC
Access time from CAS low
15
18
20
ns
tCPA
Access time from column precharge
35
40
45
ns
tRAC
Access time from RAS low
60
70
80
ns
tcLZ
CAS to output in low Z
0
toFF
Output disable time after CAS high (see Note 6)
0
NOTE 6: toFF
IS
"
specified
when the output
IS
0
15
no longer driven.
TEXAS
~
INSTRUMENTS
5-36
POST OFFICE BOX 1443· HOUSTON. TEXAS 77001
0
0
18
0
ns
20
ns
TM124BBK32, TM124CBK32S 1048576 BY 32·BIT DYNAMIC RAM MODULE
TM248CBK32, TM248CBK32S 2 097 152 BY 32·BIT DYNAMIC RAM MODULE
SMMS132C-JANUARY 1991-REVISED DECEMBER 1992
timing requirements over recommended range of supply voltage and operating free-air
temperature
'124BBK32-60
'24BCBK32-60
MAX
MIN
'124BBK32-70
'24BCBK32-70
MIN
MAX
'124BBK32-80
'24BCBK32-BO
MIN
UNIT
MAX
tRC
Random read or write cycle (see Note 7)
110
130
150
ns
tpc
Page-mode read or write cycle time (see Note 8)
40
45
50
ns
tcp
Pulse duration, CAS high
10
10
10
tCAS
Pulse duration, CAS low
15
tRP
Pulse duration, RAS high (precharge)
40
tRASP
Page-mode pulse duration, RAS low
60
100 000
70
100000
80
100 000
ns
tRAS
Non-page-mode pulse duration, RAS low
60
10 000
70
10000
80
10 000
ns
twp
Write pulse duration
15
15
15
ns
tASC
Column-address setup time before CAS low
ns
Row-address setup time before RAS low
0
ns
tDS
Data setup time
0
ns
tRCS
Read setup time before CAS low
0
ns
twcs
W-Iow setup time before CAS low
0
a
a
a
a
a
0
tASR
a
a
a
a
0
ns
twSR
W-high setup time (see Note 11)
10
10
10
ns
tCWL
W-Iow setup time before CAS high
15
18
20
ns
tRWL
W-Iow setup time before RAS high
15
18
20
ns
tCAH
Column-address hold time after CAS low
10
15
15
ns
tRAH
Row-address hold time after RAS low
10
10
10
ns
tAR
Column-address hold time after RAS low (see Note 9)
50
55
60
ns
tDHR
Data hold time after RAS low (see Note 9)
50
55
60
ns
tDH
Data hold time
10
15
15
ns
tRCH
Read hold time after CAS high (see Note 10)
ns
Read hold time after RAS high (see Note 10)
a
a
0
tRRH
a
a
0
ns
NOTES:
7.
8.
9.
10.
11.
10 000
18
10000
50
20
ns
10 000
60
ns
ns
=
All cycle times assume IT 5 ns.
To assure tpLmin, tASC should be greater than or equal to 5 ns.
The minimum value is measured when tRCD is set to tRCD min as a reference.
Either tRRH or tRCH must be satisfied for a read cycle.
CAS-before-RAS refresh only.
TEXAS ~
INsrRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
5-37
TM124BBK32, TM124CBK32S 1048576 BY 32·BIT DYNAMIC RAM MODULE
TM248CBK32, TM248CBK32S 2 097152 BY 32·BIT DYNAMIC RAM MODULE
SMMS132C-JANUARY 1991-REVISED DECEMBER 1992
timing requirements over recommended range of supply voltage and operating free·air
temperature (concluded)
'124BBK32-60
'248CBK32-60
MIN
MAX
'124BBK32-70
'248CBK32-70
MIN
MAX
'124BBK32-80
'248CBK32-80
MIN
UNIT
MAX
twCH
Write hold tillie after CAS low
15
15
15
ns
twHR
W-high hold time (see Note 11)
10
10
10
ns
twCR
Write hold time after RAS low
50
55
60
ns
tCSH
Delay time, RAS low to CAS high
60
70
80
ns
leRP
Delay time, CAS high to RAS low
0
0
0
tRCD
Delay time, RAS low to CAS low (see Note 12)
20
leHR
Delay time, RAS low to CAS high (see Note 11)
15
15
20
tCSR
Delay time, CAS low to RAS low (see Note 11)
10
10
10
tRAD
Delay time, RAS low to column-address (see Note 12)
15
tRAl
Delay time, column-address to RAS high
30
35
40
ns
tCAl
Delay time, column-address to CAS high
30
35
40
ns
tRPC
Delay time, RAS high to CAS low (see Note 11)
0
0
0
ns
tRSH
Delay time, CAS low to RAS high
15
18
20
ns
twTs
W-Iow setup time (test mode only)
10
10
10
ns
twTH
W-Iow hold time (test mode only)
10
10
10
ns
!TAA
Access time from address (test mode)
35
40
45
ns
!TRAC
Access time from RAS (test mode)
65
75
85
ns
!TCPA
Access time from column precharge (test mode)
40
45
50
ns
tREF
Refresh time interval
!T
Transition time
45
30
20
15
16
2
50
52
35
50
device symbolization (TM124BBK32 illustrated)
oDDDD DDDDo
YY
MM
T
-SS
Year Code
Month Code
Assembly Site Code
Speed Code
NOTE: location of symbolization may vary.
TEXAS ~
INSTRUMENTS
5-38
POST OFFICE BOX 1443· HOUSTON, TEXAS 77001
15
16
2
NOTES: 11. CAS-before-RAS refresh only.
12. Maximum value specified only to assure access time.
TM124BBK36B
20
2
ns
60
ns
ns
ns
40
ns
16
ms
50
ns
TM124MBK36, TM124MBK36Q
1 048 576 BY 36·BIT
DYNAMIC RAM MODULE
SMMS136A-JANUARY 1993
•
Organization ... 1 048 576 x 36
•
•
Single 5-V Power Supply
•
•
•
•
72-pln Single In-Line Memory Module
(SIMM) for Use With Sockets
Utilizes Eight 4-Megabit Dynamic RAMs in
Plastic Small-Outline J-Lead (SOJ)
Packages and Four 1-Megabit Dynamic
RAMs in Plastic Small-Outline J-Lead (SOJ)
Packages
Presence Detect
All Inputs, Outputs, Clocks Fully TTL
Compatible
•
Long Refresh Period
16 ms (1024 Cycles)
Low Power Dissipation
•
Common CAS Control for Nine Common
Data-In and Data-Out Lines, in Four Blocks
•
•
•
•
Separate RAS Control for Eighteen Data-In
and Data-Out Lines, In Two Blocks
•
•
Operating Free-Air Temperature
Range ... O°C to 70°C
3-State Output
Gold-Tabbed Version Available:t
TM124MBK36
Tin-Lead (Solder) Tabbed Version Available:
TM124MBK36Q
Performance Ranges:
ACCESS ACCESS ACCESS
READ
vec
OR
WRITE
TOLERANCE
TIME
tRAC
TIME
tCAC
TIME
tAA
·124MBK36·6 60 ns
15 ns
30 ns
110 ns
±5%
'124MBK36-70 70 ns
18 ns
35 ns
130 ns
±10%
'124MBK36-80 80 ns
20 ns
40 ns
150 ns
±10%
CYCLE
description
The TMi24MBK36 is a dynamic random-access memory organized as four times 1 048576 x 9
(bit 9 is generally used for parity) in a 72 pin ieadiess single in-line memory module (SIMM). The SIMM is
composed of eight TMS44400DJ, 1 048576 x 4-bit dynamic RAMs, each in 20/26-lead plastic small-outline
J-Iead packages (SOJs), and four TMS4Ci 024DJ, 1 048 576 x i-bit dynamic RAMs, each in 20/26-lead plastic
small-outline J-Iead packages (SOJs) mounted on a substrate with decoupling capacitors. Each TMS44400DJ
and TMS4Ci 024DJ is described in the TMS44400 and TMS4Ci 024 data sheets, respectively.
The TM124MBK36 is available in a double-sided BK leadless module for use with sockets.
The TM124MBK36 features RAS access times of 60 ns, 70 ns, and 80 ns. This device is rated for operation from
O°C to 70°C
operation
The TM124MBK36 operates as eight TMS44400DJs and four TMS4C1024DJs connected as shown in the
functional block diagram and Table 1. Refer to the TMS44400 and TMS4C1024 data sheets for details of
operation. The common I/O feature dictates the use of early write cycles to prevent contention on D and Q.
refresh
Refresh period is extended to 16 milliseconds and, during this period, each of the 1024 rows must be strobed
with RAS in order to retain data. Address line A9 must be used as most significant refresh address line (lowest
frequency) to assure correct refresh for both TMS44400 and TMS4C1024. AD-A8 address lines must be
refreshed every 8 ms as required by the TMS4C1 024 DRAM. CAS can remain high during the refresh sequence
to conserve power.
,
t
Part numbers in this data sheet are for the gold-tabbed version; the information applies to both gold-tabbed and solder-tabbed versions.
~~o~~~;~~~o:1: .~!~r;rc~~~~.l~~~:~!r~! :,f I.~:~~~~~~mde~~
atandard warranty. ProducUon proc... lng dOl' not n.cesllrlly Include
teltlng of ,II parameter•.
TEXAS
~
Copyright © 1993, Texas Instruments Incorporated
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
5-39
TM124MBK36, TM124MBK36Q
1 048 576 BY 36·BIT
DYNAMIC RAM MODULE
SMMS136A-JANUARY 1993
BK SINGLE IN-LINE MODULEt
(TOP VIEW)
Vss
000
0018
001
0019
002
DQ20
003
DQ21
VCC
NC
AO
A1
c:::)
c:::)
c:::)
c:::)
c:::)
c:::)
c:::)
c:::)
c:::)
c:::)
B
c:::)
A2 c:::)
A3 c:::)
A4 c:::)
AS c:::)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
28
27
28
29
30
31
32
33
34
35
36
RAS2
0026
008
c:::)
c:::)
c:::)
c:::)
c:::)
c:::)
c:::)
c:::)
c:::)
c:::)
c:::)
c:::)
c:::)
c:::)
c:::)
c:::)
c:::)
c:::)
c:::)
oou
c:::) 37
A6
NC
004
0022
005
0023
008
0024
007
0025
A7
NC
VCC
A8
AS
--'iQ
c:::)
c:::)
c:::)
c:::)
c:::)
c:::)
c:::)
c:::)
~ c:::)
W c:::)
0035
VSS
CASO
CAS2
CAS3
CAS 1
RASO
NC
B
38
39
40
41
42
c:::) 52
51
c:::)
DQ10
0028
0011
0029
0012
0030
0013
0031
VCC
0032
0014
0033
B
c:::)
c:::)
c:::)
c:::)
c:::)
c:::)
c:::)
c:::)
54
55
56
57
58
59
60
61
62
0015
OQ34
0016
NC
P01
P02
c:::)
c:::)
c:::)
c:::)
c:::)
c:::)
c:::)
c:::)
c:::)
63
64
65
66
67
68
69
70
71
72
NC
VSS
D
PIN NOMENCLATURE
43
44
45
46
47
NC
46
009
49
DQ27 c:::) 50
PD3
PD4
TM124MBK36t
(SIDE VIEW)
53
AO-A9
D
NC
Data In/Data Out
No Connection
PD1-PD4
Presence Detects
RASa, RAS2
Row-Address Strobe
5-V Supply
VCC
VSS
Ground
Write Enable
W
D
PRESENCE DETECT
SIGNAL PIN
G
TM124MBK36
POl
(67)
PD2
(68)
PD3
(69)
PD4
(70)
80 ns
VSS
VSS
NC
VSS
70 ns
VSS
VSS
VSS
NC
60 ns
VSS
VSS
NC
NC
t The package shown here is for pinout reference only and is not drawn to scale.
TEXAS ~
INSTRUMENTS
5-40
Address Inputs
Column-Address Strobe
CASO-CAS3
DQO-DQ35
POST OFFICE BOX 1443· HOUSTON, TEXAS 77001
TM124MBK36, TM124MBK36Q
1 048 576 BY 36·BIT
DYNAMIC RAM MODULE
SMMS136A-JANUARY 1993
Table 1. Connection Table
DATA BLOCK
RASx
CASx
DO-D07
OOS
RASO
CASO
009-0016
0017
RASO
CAS 1
0018-0025
0026
RAS2
CAS2
0027-0034
OQ35
RAS2
CAS3
single In-line memory module and components
PC substrate: 1,27 ± 0,1 mm (0.05 inch) nominal thickness; 0.005 inch/inch maximum warpage
Bypass capacitors: Multilayer ceramic
Contact area for TM124MBK36: Nickel plate and gold plate over copper.
Contact area for TM124MBK36Q: Nickel plate and tin-lead over copper.
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443· HOUSTON, TEXAS 77001
5-41
~
~C""'-I
;::-<0:::::
functional block diagram (TM124MBK36)
~Z""''''''
~» ()C) N
t:::::
"'"
>_ U1
..... :::::
zOO) IlJ
§;;:o
m"
'l!» -< c.l
~=-c.l~
"';::. 0)
~:::::. -I
10
AO-,
o!:!!~
c-IN
RAS2
RA
cr-
m
CA
CAS2-
CAS1-
1-
CAS3-
"'"
:::::
m
G
0)
o
1M x4
~
~Z
~W
o
~~
;:~c::
ftl~d
~
OQ1...-OQ9OQ4
OQ12
RAS
W
"-
CAS
OQ1- ...- OQ4OQ4
OQ7
~
"-
~
I
Q
DE
"-
~
RAS
~W
I
DOS
I
CAS
0
1M x4
~ AO-A9
RAS
l±
W
DE
OQ1OQ4 I..-OQ18OQ21
Q
..1
-=-
DO 30
1M x4
AO-A9
RAS
1M x4
~ AO-A9
RAS
~W
"- CAS
DE
f..-
"- OE
OQ22-
1M x 1
~~ 0017
OQ1OQ4 ...... 00 1DO 34
-:&-..
0025
1M x 1
~ AO-A9
RAS
~W
~ AO-A9
RAS
1
W
"- CAS
"- DE
OQ1OQ4 .... OQ 7-
CAS
001OQ4
1M x 1
"-
1M x 4
AO-A9
RAS
~W
CAS
CAS
~ AO-A9
1M x 1
AO-A9
RAS
CAS
0
~
OQ1- . . . OQ13OQ4
OQ16
~W
"-
~
1M x4
" DE
~
"
"
~ AO-A9
RAS
~W
1M x4
"-
±
" DE
~
~ AO-A9
i~4r
~
CAS
OQ1OQ4 ...-OQOOQ3
±
1M x4
AO-A9
RAS
~"- W
"- CAS
"- DE
g~
~trJ
~
~
~ AO-A9
RAS
L± W
~ CAS
1
~
0
0
I
OQ26
1
CAS
Q
0
I
OQ35
TM124MBK36, TM124MBK36Q
1 045 576 BY 36·BIT
DYNAMIC RAM MODULE
SMMSI36A-JANUARY 1993
absolute maximum ratings over operating free-air temperature range (unless otherwise noted}t
Voltage range on any pin (see Note 1) ................................................. - 1 V to 7 V
Voltage range on Vee (see Note 1) ................................................... -1 V to 7 V
Short circuit output current ................................................................ 50 rnA
Power dissipation ......................................................................... 12 W
Operating free-air temperature range .................................................. O°C to 70°C
Storage temperature range ....................................................... - 55°C to 125°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. This is a stress rating only, and
functional operation olthe device at these or any other conditions beyond those indicated in the "recommended operating conditions" section of
this specification is not implied. Exposure to absolute-maxi mum-rated conditions for extended periods may affect device reliability.
NOTE I: All voltage values are with respect to VSS.
recommended operating conditions
VCC
Supply voltage (TMI24MBK36-6)
VCC
Supply voltage (TMI24MBK36-70/-BO)
VIH
High-level input voltage
VIL
Low-level input voltage (see Note 2)
TA
Operating free-air temperature
MIN
NOM
MAX
4.75
5
5.25
V
4.5
5
5.5
V
2.4
6.5
V
-I
0.8
V
70
°c
a
UNIT
NOTE 2: The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used in this data sheet for logic
voltage levels only.
electrical characteristics over full ranges of recommended operating conditions (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
VOH
High-level output voltage
10H =-5mA
VOL
Low-level output voltage
IOL=4.2 mA
II
'I 24MBK36-6
MIN
MAX
'124MBK36-70
MIN
MAX
2.4
2.4
'124MBK36-80
MIN
MAX
2.4
UNIT
V
0.4
0.4
0.4
Input current (leakage)
VI = to 6.5 V, VCC = 5.5 V,
All other pins = V to VCC
",10
",10
",10
!!A
10
Output current (leakage)
VO=OtoVCC,
VCC = 5.5 V, CAS high
±IO
±IO
",10
!!A
ICCI
Read or write cycle current (see
Note 3)
Minimum cycle, VCC = 5.5 V
1220
1040
940
mA
After I memory cycle,
RAS and CAS high,
VIH = 2.4 V (TTL)
24
24
24
mA
After I memory cycle,
RAS and CAS high,
VIH = VCC - 0.2 V (CMOS)
12
12
12
mA
ICC2
Standby current
a
a
V
ICC3
Average refresh current (RASonly or CBR)
(see Note 3)
Minimum cycle,
VCC = 5.5 V, RAS cycling, CAS
high (RAS-only);
RAS low after CAS low (CBR)
1200
1040
920
mA
ICC4
Average page current
(see Note 4)
tpc = minimum, VCC = 5.5 V,
RAS low, CAS cycling
1000
880
760
mA
NOTES:
3. Measured with a maximum of one address change while RAS = VIL.
4. Measured with a maximum of one address change while CAS = VIH.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
5-43
TM124MBK36, TM124MBK36Q
1 045 576 BY 36-BIT
DYNAMIC RAM MODULE
SMMS136A-JANUARY 1993
capacitance over recommended ranges of supply voltage and operating free-air temperature,
f = 1 MHz (see Note 5)
P.o.RAMETER
MIN
TYP
MAX
UNIT
Ci(A)
Input capacitance, address inputs
60
pF
Ci(Cl
Input capacitance, CAS inputs
19
pF
Ci(R)
Input capacitance, RAS inputs
38
pF
Ci(W)
Input capacitance, write-enable input
76
pF
Co(OO)
Output capac~ance
1008,0017,0026,0035
I All other DO pins
NOTE 5: VCC equal to 5 V ,. 0.5 V and the bias on pins under test
IS
7
pF
12
pF
0 V.
switching characteristiCs over recommended ranges of supply voltage and operating free-air
temperature
'124MBK36-6
PARAMETER
MIN
'124MBK36-70
MAX
MIN
MAX
'124MBK36-80
MIN
MAX
UNIT
tM
Access time from column-address
30
35
40
ns
tCAC
Access time from CAS low
15
18
20
ns
tCPA
Access time from column precharge
35
40
45
ns
tRAC
Access time from RAS low
60
70
80
ns
tCLZ
CAS to output in low Z
0
toFF
Output disable time after CAS high (see Note 6)
0
NOTE 6: tOFF
IS
..
specified when the output
IS
0
15
0
18
0
0
ns
20
ns
no longer dnven .
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
'124MBK36-6
MIN
MAX
'124MBK36-70
MIN
MAX
'124MBK36-80
MIN
MAX
UNIT
tRC
Random read or write cycle (see Note 7)
110
130
150
tpc
Page-mode read or write cycle time (see Note 8)
40
45
50
tRASP
Page-mode pulse duration, RAS low
60
100000
70
100000
80
100000
tRAS
Non-page-mode pulse duration, RAS low
60
10000
70
10000
80
10000
ns
teAS
Pulse duration, CAS low
15
10000
18
10000
20
10000
ns
tcp
Pulse duration, CAS high
10
10
10
ns
tRP
Pulse duration, RAS high (precharge)
40
50
60
ns
twp
Write pulse duration
15
15
15
ns
tASC
Column-address setup time before CAS low
0
0
0
ns
tASR
Row-address setup time before RAS low
0
0
0
ns
tos
Data setup time
0
0
0
ns
tRCS
Read setup time before CAS low
0
0
0
ns
teWL
W low setup time before CAS high
15
18
20
ns
tRWL
W low setup time before RAS high
15
18
20
ns
twcs
W low setup time before CAS low
0
0
0
ns
twSR
W high setup time (see Note 9)
10
10
10
ns
NOTES:
7. All cycles assume IT = 5 ns.
8. To assure tpc min, tASC should be greater than or equal to tCp.
9. CAS-before-RAS refresh only.
TEXAS
~
INSTRUMENTS
5-44
POST OFFICE BOX 1443· HOUSTON, TEXAS 77001
ns
ns
ns
TM124MBK36, TM124MBK36Q
1 045 576 BY 36-BIT
DYNAMIC RAM MODULE
SMMS136A-JANUARY 1993
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (concluded)
'124MBK36-6
MIN
MAX
'124MBK36-70
MIN
MAX
'124MBK36-80
MIN
MAX
UNIT
teAH
Column-address hold time after CAS low
10
15
15
ns
tDHR
Data hold time after RAS low (see Note 10)
50
55
60
ns
tDH
Data hold time
10
15
15
ns
tAR
Column-address hold time after RAS low (see Note 10)
50
55
60
ns
tRAH
Row-address hold time after RAS low
10
10
12
ns
tRCH
Read hold time after CAS high (see Note II)
0
0
0
ns
tRRH
Read hold time after RAS high (see Note II)
0
0
0
ns
twCH
Write hold time after CAS low
15
15
15
ns
twCR
Write hold time after RAS low
50
55
60
ns
twHR
W-high hold time (see Note 9)
10
10
10
ns
tCHR
Delay time, RAS low to CAS high (see Note 9)
15
15
20
ns
tCRP
Delay time, CAS high to RAS low
0
0
0
ns
tCSH
Delay time, RAS low to CAS high
60
70
80
ns
teSR
Delay time, CAS low to RAS low (see Note 9)
10
10
10
tRAD
Delay time, RAS low to column-address (see Note 12)
15
tRAl
Delay time, column-address to RAS high
30
35
40
teAL
Delay time, column-address to CAS high
30
35
40
tRCD
Delay time, RAS low to CAS low (see Note 12)
20
tRPC
Delay time, RAS high to CAS low (see Note 9)
0
0
0
tRSH
Delay time, CAS low to RAS high
15
18
20
tREF
Refresh time interval
IT
NOTES:
Transition time
9.
10.
11.
12.
30
45
15
20
16
3
50
35
52
17
20
16
3
50
3
ns
40
ns
ns
ns
60
ns
ns
ns
16
ms
50
ns
CAS-before-RAS refresh only.
The minimum value is measured when tRCD is set to tRCD min as a reference.
Enher tRRH or tRCH must be satisfied for a read cycle.
The maximum value is specified only to assure access time.
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443' HOUSTON. TEXAS 77001
5-45
TM124MBK36, TM124MBK36Q
1 045 576 BY 36·BIT
DYNAMIC RAM MODULE
SMMS136A-JANUARY 1993
device symbolization
o
DDDDDDo
TM124MBK36
-SS
YY = Year Code
Month Code
T = Assembly Site Code
- SS = Speed Code
MM
=
NOTE: Location of symbolization may vary.
"TEXAS ~
INSfRUMENTS
5-46
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
TM124MBK36B, TM124MBK36R 1 048576 BY 36·BIT DYNAMIC RAM MODULE
TM248NBK36B, TM248NBK36R 2 097 152 BY 36·BIT DYNAMIC RAM MODULE
SMMS137D---JANUARY 1991-REVISED JANUARY 1993
•
Organization
TM124MBK36B",1 048576 x 36
TM248NBK36B, , , 2097152 x 36
•
Single 5-V Power Supply (:1:10% Tolerance)
TIME
TIME
TIME
OR
•
72-pin Leadless Single In-Line Memory
Module (SIMM) for Use With Sockets
TM124MBK36B-Utilizes Eight 4-Megabit
Dynamic RAMs In Plastic Smail-Outline
J-Lead (SOJ) Packages and One 4-Megablt
Quad-CAS Dynamic RAM In a Plastic
Smail-Outline J-Lead (SOJ) Package
tRAC
tAA
tCAC
WRITE
CYCLE
•
•
•
•
Presence Detect
Performance Ranges:
ACCESS
TM248NBK36B-Utilizes Sixteen 4-Megablt
Dynamic RAMs in Plastic Small-Outline
J-Lead (SOJ) Packages and Two 4-Megabit
Quad-CAS Dynamic RAMs in Plastic
Smail-Outline J-Lead (SOJ) Packages
•
Long Refresh Period, , , 16 ms
(1024 Cycles)
•
All Inputs, Outputs, Clocks Fully TTL
Compatible
•
•
3-State Output
Common CAS Control for Nine Common
Data-In and Data-Out Lines, In Four Blocks
•
Enhanced Page Mode Operation with CASBefore-RAS, RAS-Only, and Hidden Refresh
(MAX)
(MAX)
(MAX)
'124MBK36B-60 60 ns
30 ns
15 ns
(MIN)
110 ns
'124MBK36B-70 70 ns
'124MBK36B-BO BO ns
35 ns
40 ns
1B ns
20 ns
130 ns
150 ns
'24BNBK36B-60
60 ns
30 ns
15 ns
110 ns
'24BNBK36B-70
70 ns
BO ns
35 ns
40 ns
1B ns
20 ns
130 ns
150 ns
'24BNBK36B-BO
•
•
ACCESS ACCESS READ
Low Power Dissipation
Operating Free-Air Temperature
Range, , , O°C to 70°C
•
Gold-Tabbed Versions Available:t
- TM124MBK36B
- TM248NBK36B
•
Tin-Lead (Solder) Tabbed Versions
Available:
- TM124MBK36R
- TM248NBK36R
description
TM124MBK36B
The TM124MBK36B is a dynamic random-access memory organized as four times 1 048576 x 9
(bit 9 is generally used for parity) in a 72-pin lead less single in-line memory module (SIMM), The SIMM is
composed of eight TMS44400DJ, 1 048 576 x 4-bit dynamic RAMs, each in 20/26-lead plastic small-outline
J-Iead packages (SOJs), and one TMS44460DJ, 1 048576 x 4-bit Quad-CAS dynamic RAM in a 24/26-lead
plastic small-outline J-Iead package (SOJ) , mounted on a substrate with decoupling capacitors, Each
TMS44400DJ and TMS44460DJ is described in the TMS44400 or TMS44460 data sheet, respectively,
The TM124MBK36B is available in the single-sided BK leadless module for use with sockets,
The TM124MBK36B features RAS access times of 60 ns, 70 ns, and 80 ns, This device is rated for operation
from O°C to 70°C
TM248NBK36B
The TM248NBK36B is a dynamic random-access memory organized as four times 2097 152 x 9
(bit 9 is generally used for parity) in a 72-pin leadless single in-line memory module (SIMM), The SIMM is
composed of sixteen TMS44400DJ, 1 048 576 x 4-bit dynamic RAMs, each in 20/26-lead plastic small-outline
J-Iead packages (SOJs). and two TMS44460DJ, 1 048576 x 4-bit Quad-CAS dynamic RAMs, each in a
24/26-lead plastic small-outline J-Iead package (SOJ), mounted on a substrate with decoupling capacitors,
Each TMS44400DJ and TMS44460DJ is described in the TMS44400 and TMS44460 data sheet, respectively.
t Part numbers in this data sheet are for the gold-tabbed version; the information applies to both gold-tabbed and solder-tabbed versions.
=~o~~~~~~:'o~1: .1~:r~~~I~~.I;.~::~!r~~ ::!.~:!I~:~~m~~~i
It.ndard warranty. Production proc ... lng do.. not n.c....rll)' Include
t'ltlng of.1I parameter•.
TEXAS
~
Copyright © 1993, Texas Instruments Incorporated
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
5-47
TM124MBK36B, TM124MBK36R 1048576 BY 36·BIT DYNAMIC RAM MODULE
TM248NBK36B, TM248NBK36R 2097152 BY 36·BIT DYNAMIC RAM MODULE
SMMS137O-JANUARY 1991-REVISED JANUARY 1993
The TM124NBK36B is available in the double-sided BK leadless module for use with sockets.
The TM124NBK36B features RAS access times of 60 ns, 70 ns, and 80 ns. This device is rated for operation
from O°C to 70°C
operation
TM124MBK36B
The TM124MBK36B operates as eight TMS44400DJs and one TMS44460DJ connected as shown in the
functional block diagram and Table 1. The parity bits are provided by the TMS44460DJ and are controlled by
RAS2. To ensure proper parity bit operation all memory accesses should include a RAS2 pulse. Refer to the
TMS44400 and TM S44460 data sheets for details of operation. The common I/O feature dictates the use of early
write cycles to prevent contention on 0 and Q.
TM248NBK36B
The TM248NBK36B operates as sixteen TMS44400DJs and two TMS44460DJs connected as shown in the
functional block diagram and Table 1. The parity bits are provided by the TMS44460DJ and are controlled by
RAS2 on side 1 and RAS3 on side 2. To ensure proper parity bit operation, all memory accesses should include
a RAS2 or RAS3 pulse. Refer to the TMS44400 and TMS44460 data sheets for details of operation. The
common 110 feature dictates the use of early write cycles to prevent contention on 0 and Q.
TEXAS ~
INsrRUMENTS
5-48
POST OFFICE BOX 1443· HOUSTON. TEXAS 77001
TM124MBK36B, TM124MBK36R 1048576 BY 36·BIT DYNAMIC RAM MODULE
TM248NBK36B, TM248NBK36R 2 097152 BY 36·BIT DYNAMIC RAM MODULE
SMMS137D-,JANUARY 1991-REVISED JANUARY 1993
BK SINGLE IN·LlNE MEMORY MODULET
TM124MBK36BT
TM248NBK36BT
(TOP VIEW)
(SIDE VIEW)
{SIDE VIEW)
VSS
oao
oa18
oal
Da19
oa2
Da20
oa3
oa21
VCC
NC
AO
Al
A2
A3
A4
AS
A6
NC
oa4
oa22
oa5
oa23
oaa
oa24
oa7
Da25
A7
NO
VCC
A8
A9
RAS3
RAS2
oa26
oa8
e::>
e::>
e::>
e::>
e::>
e::>
e::>
e::>
e::>
e::>
e::>
e::>
e::>
e::>
e::>
e::>
e::>
e::>
e::>
e::>
e::>
e::>
e::>
e::>
e::>
e::>
e::>
e::>
e::>
e::>
e::>
e::>
e::>
e::>
e::>
e::>
e::>
e::>
e::>
e::>
e::>
e::>
e::>
RASO e::>
RASI
e::>
NC e::>
Vi e::>
NC e::>
oa9 e::>
oa27 e::>
oal0 e::>
oa28 e::>
0011
e::>
oa29 e::>
oa12 e::>
oa30 e::>
oa13 e::>
oa31
e::>
VCC e::>
oa32 e::>
oa14 e::>
oa33 e::>
oa15 e::>
oa34 e::>
oa16 e::>
NC e::>
POI
e::>
P02 e::>
P03 e::>
P04 e::>
NC e::>
Vss e::>
oa17
oa35
VSS
CASO
CAS2
CAS3
CASI
1
2
3
4
5
a
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
80
61
82
63
64
65
66
67
68
69
70
71
72
D
D
D
D
D
PIN NOMENCLATURE
D
D
D
D
Address Inputs
Column-Address Strobe
Data In/Data Out
No Connection
Presence Detects
Row-Address Strobe
5-V Supply
Ground
Write Enable
AO-A9
CASO-CAS3
DQO-DQ35
NC
PD1-PD4
RASO-RAS3
VCC
VSS
W
PRESENCE DETECT
SIGNAL
(PIN)
TM124MBK36B
TM248NBK36B
PD1
(67)
PD2
(68)
PD3
(69)
PD4
(70)
80 ns
VSS
VSS
NC
VSS
70 ns
VSS
VSS
VSS
NC
60 ns
VSS
VSS
NC
NC
80 ns
NC
NC
NC
VSS
70 ns
NC
NC
VSS
NC
60 ns
NC
NC
NC
NC
t The packages shown here are for pinout reference only and are not drawn to scale.
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
5-49
TM124MBK36B, TM124MBK36R 1 048576 BY 36·BIT DYNAMIC RAM MODULE
TM248NBK36B, TM248NBK36R 2097152 BY 36·BIT DYNAMIC RAM MODULE
SMMSI37D-JANUARY 1991-REVISED JANUARY 1993
Table 1. Connection Table
DATA BLOCK
RASx
CASx
SIDE 1
SIDE2t
DOS
RASO
RAS2
RASl
RAS3
CASO
CASO
009-0016
0017
RASO
RAS2
RASl
RAS3
CASl
CASl
0018-0025
0026
RAS2
RAS2
RAS3
RAS3
CAS2
CAS2
0027-0034
0035
RAS2
RAS2
RAS3
RAS3
CAS3
CAS3
00C-007
t Side 2 applies to the TM248NBK36B only.
single in-line memory module and components
PC substrate: 1,27 ± 0,1 mm (0.05 inch) nominal thickness; 0.005 inch/inch maximum warpage
Bypass capacitors: Multilayer ceramic
Contact area for TM124MBK36B and TM248NBK36B: Nickel plate and gold plate over copper
Contact area for TM124MBK36R and TM248NBK36R: Nickel plate and tin-lead over copper
TEXAS
~
INSTRUMENTS
5-50
POST OFFICE BOX 1443· HOUSTON. TEXAS 77001
functional block diagram (TM124MBK36B and TM248NBK36B, side 1)
AO-A'- 10
RA:
-f-f
RAS2
s:S:
N .....
~N
Q)~
CAS1-
CA 1 1Mx4
~ AO-A9
RAS
~W
"-
"-
i'
1
~d
~~
~4r
10
~
~
CAS
OE
001004 :"-000OQ3
CAS2-
~
"-
1M x4
AO-A9
RAS
~
1M x4
AO-A9
RAS
CAS
OE
001004 ...-009-0012
moo
~
~W
W
zS:
CAS3-
"-
CAS
"-
OE
~
001OQ4 "'-0018-0021
GG
1M x4
AO-A9
RAS
0)0)
-moo
-f-f
W
~ CAS
~
l'-
s:S:
N .....
OE
~N
001004 "'-1
1
Q)~
zs:
7-
moo
o
GG
0) 0)
~
~
"-
1-
"-
10
1Mx4
AO-A9
RAS
~
W
CAS
OE
001-...- 00 4004
007
f
~
1M x 4
AO-A9
RAS
~
W
"-
OE
~
~W
CAS
OQ1-~0013- ~
004
1M x4
AO-A9
RAS
0016
"CAS
"-
OE
001OQ4 ~00220025
1M x4
AO-A9
RAS
:0:0
N .....
00
<0 ~
~ WCAS
..... Q)
..... U1
U1 .....
"-
r-=-
"-
OE
001004
NO)
~I
11 34
(Jl
.::
10
~
1M x4
AO-A9
RAS
~W
CAS4
l'-
l'l'.b,
..1
-=-
.::
(Jl
c;;
CAS3
CAS2
CAS1
OE
004
003
002
001
(.) (.)
0) 0)
I
I
moo
... :::::;:::::;
~
0035
0026
0017
OOB
CC
»
z
c
»
-<-<
zz
.,
00
m
:0:0
m
S:S:
S:S:
'l!
~
l>
S:S:
l>l>
00
CC
C:C:
II
mm
functional block diagram (TM248NBK36B, side 2)
'{'
~
'"s:s:
'"....C;;
~z
c
~
10
AORA
co
co
RAS3
rJJ
,
m
<
iii
-
CA:
t!:~
-"
§
"-
o
~~
,l,-
~~~d
~c::
~
±
W
"-
CAS
OE
OQ1OQ4
~OQO- ~
~
"w
"
L-
OE
OQ1...-OQ9OQ4
OQ12
10
CAS
OE
OQ1- ...- OQ4OQ4
OQ7
J-=-
~
OE
OQ1- ...- OQl3OQ4
OQ16
"
OQ1OQ4 "'-OQ18OQ21
-.l
-=-
OE
OQ1OQ4 "'-OQ22OQ25
l!l
~
'"
7-
o
~N
oo~
Z3:
OJ OJ
GG
en en
::0::0
N ....
~
..... en
en ......
Nen
toto
=i=i
OE
OQ1OQ4 "-1
1-
OQ4
OQ3
OQ2
OQl
~~
Zz
3:3:
l>l>
00
~
~W
r-=-
3:3:
N -"
~~
1M x4
AO-A9
RAS
"
OJ,!»
-1-1
Ww
CAS
CAS4
CAS3
CAS2
"CASl
"OE
GG
en en
en en
1 34
~
Z3:
OJOl
......
~I
1M x4
b.,
~N
OO~
go
~ AO-A9
RAS
~W
~W
+
"- CAS
"- OE
OQ1OQ4
co
1
1M x4
"CAS
"-
:>-
~
~W
CAS
OE
z~
c
~ AO-A9
RAS
~ AO-A9
RAS
1M x 4
AO-A9
RAS
~W
CAS
"-
~
CAS
0
1M x4
~W
W
OQ3
lMx4
AO-A9
----1::::> ~AS
2:
"-
1M x 4
AO-A9
RAS
1M x4
AO-A9
RAS
m
CAS3-
CAS2-
~
~
~[T1
~ (jJ4r
1M x4
AO-A9
RAS
Lb
g~
_z
CAS1-
-1-1
3:3:
N ....
::0::0
l>l>
OQ35
OQ26
OQ17
OQ8
3:3:
3:3:
00
Cc
Cc
"mm
TM124MBK36B, TM124MBK36R 1 048576 BY a6·BIT DYNAMIC RAM MODULE
TM248NBK36B, TM248NBK36R 2 097152 BY 36·BIT DYNAMIC RAM MODULE
SMMS137~ANUARY
1991-REVISED JANUARY 1993
absolute maximum ratings over operating free·alr temperature range (unless otherwise noted)t
Voltage range on any pin (see Note 1) ................................................. - 1 V to 7 V
Voltage range on Vee (see Note 1) ................................................... -1 V to 7 V
Short circuit output current ................................................................ 50 mA
Power dissipation .......................................................................... 9 W
Operating free-air temperature range .................................................. O°C to 70°C
Storage temperature range ....................................................... - 55°C to 125°C
t Stresses beyond those listed under "absolute maximum ratings' may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions 'beyond those indicated under "recommended operating conditions' is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to VSS.
recommended operating conditions
UNIT
MIN
NOM
MAX
VCC
Supply voHage
4.5
5
5.5
V
VIH
High-level input voltage
2.4
6.5
V
VIL
Low-level input voltage (see Note 2)
-1
0.8
V
TA
Operating free-air temperature
0
70
·C
NOTE 2: The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used in this data sheet for logic
voltage levels only.
electrical characteristics over full ranges of recommended operating conditions (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
VOH
High-level output voltage
IOH ;-5 mA
VOL
Low-level output voltage
IOL=4.2 mA
II
'124MBK36B-60
MIN
MAX
'124MBK36B-70
MIN
MAX
2.4
2.4
'124MBK36B-80
MIN
MAX
2.4
UNIT
V
0.4
0.4
0.4
V
Input current (leakage)
VI ; 0 to 6.5 V, VCC = 5.5 V,
All other pins ; 0 V to VCC
:tl0
:tl0
:tl0
~
10
Output current (leakage)
Vo = Oto Vcc,
Vcc ; 5.5 V, CAS high
:tl0
:tl0
:tl0
~
ICCI
Read or write cycle
current (see Note 3)
Minimum cycle, VCC = 5.5 V
945
810
720
mA
18
18
18
mA
9
9
9
mA
ICC2
Standby current
After 1 memory cycle,
RAS and CAS high,
VIH = 2.4 V (TTL)
After 1 memory cycle,
RAS and CAS high,
VIH = VCC - 0.2 V (CMOS)
ICC3
Average refresh current
(RAS-only or CBR)
(see Note 3)
Minimum cycle, VCC =5.5 V,
RAS cycling, CAS high (RAS-only),
RAS low after CAS low (CBR)
945
810
720
mA
ICC4
Average page current
(see Note 4)
tpc = minimum, VCC =5.5 V
RAS low, CAS cycling
810
720
630
mA
NOTES: 3. Measured With a maximum of one address change while RAS = VIL.
4. Measured with a maximum of one address change while CAS = VIH.
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
5-53
TM124MBK36B, TM124MBK36R 1 048576 BY 36·BIT DYNAMIC RAM MODULE
TM248NBK36B, TM248NBK36R 2 097152 BY 36-BIT DYNAMIC RAM MODULE
SMMS137D-JANUARY 11l91--REVISED JANUARY 1993
electrical characteristics over full ranges of recommended operating conditions (unless otherwise
noted)
TEST CONDITIONS
PARAMETER
VOH
High-level output voltage
10H =-5mA
VOL
Low-level output voltage
IOL=4.2mA
II
Input current (leakage)
10
ICC1
ICC2
MIN
'248NBK36B-70
MIN
MAX
2.4
'248NBK36B-80
MAX
MIN
2.4
MAX
2.4
UNIT
V
0.4
0.4
0.4
V
VI = 0 to 6.5 V, VCC = 5.5 V,
All other pins = 0 V to VCC
%20
%20
%20
~
Output current (leakage)
Vo =OtoVCC,
VCC = 5.5 V, CAS high
%20
%20
%20
~
Read or write cycle
current (see Note 3)
Minimum cycle, VCC = 5.5 V
963
828
738
mA
After 1 memory cycle,
RAS and CAS high,
VIH = 2.4 V (TTL)
36
36
36
mA
After 1 memory cycle,
RAS and CAS high,
VIH = VCC - 0.2 V (CMOS)
18
18
18
mA
1890
1620
1440
mA
828
738
648
mA
Standby current
ICC3
Average refresh current
(RAS-only or CBR)
(see Note 3)
Minimum cycle, VCC = 5.5 V,
RAS cycling, CAS high (RAS-only),
RAS low after CAS low (CBR)
ICC4
Average page current
(see Note 4)
tpc = minimum, VCC = 5.5 V
RAS low, CAS cycling
NOTES:
'248NBK36B-60
3. Measured with a maximum of one address change while RAS = VIL.
4. Measured with a maximum of one address change while CAS VIH.
=
capacitance over recommended ranges of supply voltage and operating free-air temperature,
f = 1 MHz (see Note 5)
'124MBK36B
PARAMETER
MIN
TYP
'248NBK36B
MAX
MIN
TYP
MAX
UNIT
Ci(A)
Input capacitance, address inputs
45
90
pF
CirRI
Input capacitance, RAS inputs
35
35
pF
Ci(C)
Input capacitance, CAS inputs
21
42
pF
Ci(Wj
Input capacitance, write-enable input
63
126
pF
Co(OQ)
Output capacitance on OQ pins
7
14
pF
NOTE 5: VCC equal to 5 V %0.5 V and the bias on pinS under test IS 0 V.
TEXAS
~
IN5rRUMENTS
5-54
POST OFFICE BOX 1443,· HOUSTON. TEXAS 77001
TM124MBK36B, TM124MBK36R 1048576 BY 36-BIT DYNAMIC RAM MODULE
TM248NBK36B, TM248NBK36R 2 097 152 BY 36-BIT DYNAMIC RAM MODULE
SMMS137D-JANUARY 1991-REVISED JANUARY 1993
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature
'124MBK36B-60
'248NBK36B·60
PARAMETER
MIN
MAX
'124MBK36B·70
'248NBK36B·70
MIN
MAX
'124MBK36B-80
'248NBK36B·80
MIN
UNIT
MAX
tCAC
Access time from CAS low
15
18
20
ns
tAA
Access time from column-address
30
35
40
ns
tRAC
Access time from RAS low
60
70
80
ns
tCPA
Access time from column precharge
35
40
45
ns
tCLZ
CAS to output in low Z
0
tOFF
Output disable time after CAS high (see Note 6)
0
0
15
0
0
18
0
ns
20
ns
NOTE 6: tOFF is specified when the output is no longer driven.
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
'124MBK36B-60
'248NBK36B·60
MIN
MAX
'124MBK36B·70
'248NBK36B·70
MIN
MAX
'124MBK36B-80
'248NBK36B-80
MIN
UNIT
MAX
tRC
Random read or write cycle (see Note 7)
110
130
150
ns
tRWC
Read-write cycle time
130
153
175
ns
45
ns
tpc
Page-mode read or write cycle time (see Note 8)
40
tRASP
Page-mode pulse duration, RAS low
60
tRAS
Non-page-mode pulse duration, RAS low
tCAS
Pulse duration, CAS low
tcp
Pulse duration, CAS high
10
10
10
ns
tRP
Pulse duration, RAS high (precharge)
40
50
60
ns
twP
Write pulse duration
15
15
15
ns
tASC
Column-address setup time before CAS low
0
0
0
ns
tASR
Row-address setup time before RAS low
0
0
0
ns
100000
70
60
10000
15
10 000
50
100000
80
100000
ns
70
10 000
80
10000
ns
18
10000
20
10 000
ns
tDS
Data setup time
0
0
0
ns
tRCS
Read setup time before CAS low
0
0
0
ns
tCWL
W low setup time before CAS high
15
18
20
ns
tRWL
W low setup time before RAS high
15
18
20
ns
twcs
W low setup time before CAS low
twSR
W high setup time (see Note 9)
NOTES:
0
0
0
ns
10
10
10
ns
7. All cycles assume IT = 5 ns.
8. To assure tpc min, IASC should be greater than or equal to 5 ns.
9. CAS-before-RAS refresh only.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443' HOUSTON. TEXAS 77001
5-55
TM124MBK36B, TM124MBK36R 1048576 BY 36·BIT DYNAMIC RAM MODULE
TM248NBK36B, TM248NBK36R 2 097152 BY 36·BIT DYNAMIC RAM MODULE
SMMS137D-JANUARY 1991-REVISED JANUARY 1993
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (concluded)
'124MBK36B-60
'248NBK36B-60
MIN
MAX
'124MBK36B-70
'248NBK36B-70
MIN
MAX
'124MBK36B-80
'248NBK36B-80
MIN
UNIT
MAX
tcAH
Column-address hold time after CAS low
10
15
15
ns
tDHR
Data hold time after RAS low (see Note 10)
50
55
60
ns
tDH
Data hold time
10
15
15
ns
tAR
Column-address hold time after RAS low (see Note 10)
50
55
60
ns
tclCH
Hold time, CAS low to CAS high
5
5
5
ns
tRAH
Row-address hold time after RAS low
10
10
10
ns
tRCH
Read hold lime after CAS high (see Note 11)
0
0
0
ns
tRRH
Read hold time after RAS high (see Note 11)
0
0
0
ns
twCH
Write hold time after CAS low
15
15
15
ns
twCR
Write hold time after RAS low (see Note 10)
50
55
60
ns
twHR
W high hold time (see Note g)
10
10
10
ns
tcHR
Delay time, RAS low to CAS high (see Note 9)
15
15
20
ns
tcRP
Delay time, CAS high to RAS low
0
0
0
ns
tCSH
Delay time, RAS low to CAS high
60
70
80
ns
tCSR
Delay time, CAS low to RAS low (see Note 9)
10
10
10
tRAD
Delay time, RAS low to column-address (see Note 12)
15
tRAl
Delay time, column-address to RAS high
30
35
40
tCAl
Delay time, column-address to CAS high
30
35
40
tRCD
Delay time, RAS low to CAS low (see Note 12)
20
tRPC
Delay time, RAS high to CAS low (see Note 9)
0
tRSH
Delay time, CAS low to RAS high
tREF
Refresh time interval
IT
NOTES:
45
15
20
52
50
2
50
oDDDDD DDDDo
Year Code
Month Code
Assembly Site Code
Speed Code
NOTE: location of symbolization may vary.
TEXAS
~
INSTRUMENTS
5-56
POST OFFICE BOX 1443· HOUSTON. TEXAS 77001
ns
40
2
ns
ns
ns
60
ns
ns
20
device symbolization (TM124MBK36B illustrated)
YY
MM
T
-SS
20,
16
CAS-before-RAS refresh only.
The minimum value is measured when tRCD is set to tRCD min as a reference.
Either tRRH or tRCH must be satisfied for a read cycle.
The maximum value is specified only to assure access time.
TM124MBK36B
15
0
18
16
2
35
0
15
Transition time
9.
10.
11.
12.
30
ns
16
ms
50
ns
TM124MBK36C, TM124MBK36S 1 048576 BY 36·BIT DYNAMIC RAM MODULE
TM248NBK36C, TM248NBK36S 2 097152 BY 36·BIT DYNAMIC RAM MODULE
1992-REVISED JANUARY 1993
•
Organization
TM124MBK36C ... 1 048576 x 36
TM248NBK36C ... 2 097152 x 36
•
Enhanced Page Mode Operation With
CAS-Before-RAS, RAS-Only, and Hidden
Refresh
•
Single 5-V Power Supply (±10% Tolerance)
Presence Detect
•
72-pin Leadless Single In-Line Memory
Module (SIMM)
•
•
•
TM124MBK36C - Utilizes Eight 4-Megabit
Dynamic RAMs in Plastic Small-Outline
J-Lead (SOJ) Packages and Two 4-Megablt
Quad-CAS Dynamic RAM in Plastic
Small-Outline J-Lead (SOJ) Packages
•
TM248NBK36C - Utilizes Sixteen 4-Megabit
Dynamic RAMs In Plastic Small-Outline
J-Lead (SOJ) Packages and Four 4-Megabit
Quad-CAS Dynamic RAMs in Plastic
Small-Outline J-Lead (SOJ) Packages
•
Long Refresh Period •.• 16 ms
(1024 Cycles)
•
All Inputs, Outputs, Clocks Fully TTL
Compatible
•
3-State Output
•
Common CAS Control for Nine Common
Data-In and Data-Out Lines, in Four Blocks
Performance Ranges:
ACCESS
TIME
tRAC
ACCESS ACCESS READ
TIME
TIME
OR
WRITE
tAA
tCAC
(MAX)
30 ns
15 ns
110 ns
'124MBK36C-7o 70 ns
'124MBK36C-8o 80ns
'248NBK36C-6o 60 ns
'248NBK36C-7o 70 ns
35 ns
18 ns
130 ns
40 ns
30 ns
20 ns
15 ns
150 ns
110 ns
35 ns
40 ns
18 ns
20 ns
150 ns
'248NBK36C-8o 80 ns
(MAX)
CYCLE
(MIN)
(MAX)
'124MBK36C-6o 60 ns
•
•
Low Power Dissipation
•
Gold-Tabbed Versions Available:t
- TM124MBK36C
- TM248NBK36C
•
Tin-Lead (Solder) Tabbed Versions
- TM124MBK36S
- TM248NBK36S
130 ns
Operating Free-Air-Temperature
Range ... O°C to 70°C
description
TM124MBK36C
The TM124MBK36C is a dynamic random-access memory organized as four times 1 048576 x 9 (bit 9 is
generally used for parity) in a 72-pin leadless single in-line memory module (SIMM). The SIMM is composed
of eight TMS44400DJ, 1 048 576 x 4-bit dynamic RAMs, each in 20/26-lead plastic small-outline J-Iead
packages (SOJs), and two TMS44460DJ, 1 048576 x 4-bit Quad-CAS dynamic RAMs, in 24/26-lead plastic
small-outline J-Iead packages (SOJs) mounted on a substrate with decoupling capacitors. Each TMS44400DJ
and TMS44460DJ is described in the TMS44400 and TMS44460 data sheets, respectively.
The TM124MBK36C is available in the single-sided BK leadless module for use with sockets.
The TM124MBK36C features RAS access times of 60 ns, 70 ns, and 80 ns. This device is characterized for
operation from O°C to 70°C
t Part numbers in this data sheet are for the gold-tabbed version; the information applies to both gold-tabbed and solder-tabbed versions.
~~o~~~~~~~o~:i: .';!~rrc~:'~~"~8~~:~!r~~ :: Ie:~i~~~~mdea~:~
,tandard warranty. Produc:tion processing does not neceasarlly Include
teltlng of all par.matart.
TEXAS
~
Copyright© 1993. Texas Instruments Incorporated
INsrRUMENTS
POST OFFICE BOX 1443· HOUSTON. TEXAS 77001
5-57
TM124MBK36C, TM124MBK36S 1048576 BY 36·BIT DYNAMIC RAM MODULE
TM248NBK36C, TM248NBK36S 2 097152 BY 36·BIT DYNAMIC RAM MODULE
SMMS138A-MARCH 1992-REVISED JANUARY 1993
TM248NBK36C
The TM248NBK36C is a dynamic random-access memory organized as four times 2097 152 x 9 (bit 9 is
generally used for parity) in a 72-pin leadless single in-line memory module (SIMM). The SIMM is composed
of sixteen TMS44400DJ, 1 048 576 x 4-bit dynamic RAMs, each in 20/26-lead plastic small-outline J-Iead
packages (SOJs), and four TMS44460DJ, 1 048576 x 4-bit Quad-CAS dynamic RAMs, in 24/26-lead plastic
small- outline J-Iead packages (SOJs) mounted on a substrate with decoupling capacitors. Each TMS44400DJ
and TMS44460DJ is described in the TMS44400 orTMS44460 data sheet, respectively.
The TM248NBK36C is available in the double-sided BK leadles$ module for use with sockets.
The TM248NBK36C features RAS access times of 60 ns, 70 ns, and 80 ns. This device is rated for operation
from O°C to 70°C
operation
TM124MBK36C
The TM124MBK36C operates as eight TMS44400DJs and two TMS44460DJs connected as shown in the
functional block diagram and Table 1. The common I/O feature dictates the use of early write cycles to prevent
contention on 0 and Q.
TM248NBK36C
The TM248NBK36C operates as sixteen TMS44400DJs and four TMS44460DJs connected as shown in the
functional block diagram and Table 1. The common I/O feature dictates the use of early write cycles to prevent
contention on 0 and Q.
TEXAS ~
INBrRUMENTS
5-58
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
TM124MBK36C, TM124MBK36S 1048576 BY 36·BIT DYNAMIC RAM MODULE
TM248NBK36C, TM248NBK36S 2 097152 BY 36·BIT DYNAMIC RAM MODULE
SMMS138A-MARCH 1992-REVISED JANUARY 1993
vss
OCO
OC18
OCl
OC19
OC2
0020
OC3
0021
VCC
NC
AO
Al
A2
A3
A4
AS
A6
NC
004
0022
005
0023
OC6
0024
007
0025
A7
NC
VCC
AS
A9
RAS3
RAS2
0026
OC8
OC17
0035
VSS
CASO
CAS2
CAS3
CASl
RASO
RASl
NC
W
NC
OC9
OC27
OC10
OC28
0011
OC29
0012
OC30
0013
0031
VCC
OC32
OC14
OC33
0015
OC34
OC16
NC
POl
P02
P03
PD4
NC
VSS
BK SINGLE IN-LINE MODULEt
TM124MBK36Ct
TM248NBK36Ct
(TOP VIEW)
(SIDE VIEW)
(SIDE VIEW)
L:)
L:)
L:)
L:)
L:)
L:)
L:)
L:)
L:)
L:)
L:)
L:)
L:)
L:)
L:)
L:)
L:)
L:)
L:)
L:)
L:)
L:)
L:)
L:)
L:)
L:)
L:)
L:)
L:)
L:)
L:)
L:)
L:)
L:)
L:)
L:)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
L:)
L:)
L:)
L:)
L:)
L:)
L:)
L:)
L:)
L:)
L:)
L:)
L:)
L:)
L:)
L:)
L:)
L:)
L:)
L:)
L:)
L:)
L:)
L:)
L:)
L:)
L:)
L:)
L:)
L:)
L:)
L:)
L:)
L:)
L:)
L:)
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
54
65
66
67
68
69
70
71
72
8)
D
D
D
D
D
D
D
D
D
D
8)
PIN NOMENCLATURE
Address Inputs
Column-Address Strobe
Data In/Data Out
No Connection
Presence Detects
Row-Address Strobe
5-V Supply
Ground
Write Enable
AO-A9
CASO-CAS3
DQO-DQ35
NC
PD1-PD4
RASO-RAS3
VCC
VSS
W
PRESENCE DETECT
SIGNAL
(PIN)
TM124MBK36C
TM248NBK36C
PD1
(67)
PD2
(68)
PD3
(69)
PD4
(70)
80 ns
VSS
VSS
NC
VSS
70 ns
VSS
VSS
VSS
NC
60 ns
VSS
VSS
NC
NC
80 ns
NC
NC
NC
VSS
70 ns
NC
NC
VSS
NC
60 ns
NC
NC
NC
NC
t The packages shown here are for pinout reference only and are not drawn to scale.
TEXAS ~
IN8rRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
5-59
TM124MBK36C, TM124MBK36S 1048576 BY 36·BIT DYNAMIC RAM MODULE
TM248NBK36C, TM248NBK36S 2 097 152 BY 36·BIT DYNAMIC RAM MODULE
SMMS138A-MARCH 1992-REVISED JANUARY 1993
Table 1. Connection Table
DATA BLOCK
RASx
CASx
SIDE 1
SIDE2t
00D-0Q7
008
RASO
RASO
RAS1
RAS1
CASO
CASO
009-0016
0017
RASO
RASO
RAS1
RAS1
CAS1
CAS 1
0018-0025
0026
RAS2
RAS2
RAS3
RAS3
CAS2
CAS2
0027-0034
0035
RAS2
RAS2
RAS3
RAS3
CAS3
CAS3
t Side 2 applies to the TM248NBK36C only.
single In-line memory module and components
PC substrate: 1,27 ± 0,1 mm (0.05 inch) nominal thickness; 0.005 inch/inch maximum warpage
Bypass capacitors: Multilayer ceramic
Contact area for TM124MBK36C and TM248NBK36C: Nickel plate and gold plate over copper
Contact area for TM124MBK36S and TM248NBK36S: Nickel plate and tin-lead over copper
TEXAS
~
INSI'RUMENTS
5-60
POST OFf'ICE BOX 1443' HOUSTON. TEXAS 77001
functional block diagram (for TM124MBK36C and TM248NBK36C, Side 1)
AD-: - 10
~
RAS2
-1-1
-
CA:
CAS1-
CAS2-
==:==:
N .....
-,="N
CAS3-
Q)-'="
10
~
~
~
~Z
~
"-
1M x4
AD-A9
RAS
i~~
g~~
~tr1
i~~
~
CAS
OE
OQ1OQ4 ...-OQDOQ3
10
f
~
OE
~
CAS
OE
OQ1OQ4 ...-OQ9OQ12
~
~
OQ1-~OQ~ ~
DQ4
"-
10
1M x4
AD-A9
RAS
~
~ Vi
CAS
....
1M x4
AD-A9
RAS
~ Vi
Vi
o
~(JJ
10
OE
DQ1- .... OQl3OQ4
DQ16
10
W
"-
OE
~
~ Vi
~DQl8- ~
~
~
"-
CAS
OE
OQ1OQ4
~OQ22- ~
1M x4
"
"-
OQ27OQ30
I
N .....
00
OQ31OQ34
I
Co) Co)
0) 0)
~
mOl
;;::
~
=i=i
cc
-<-<
zz
»»
==:==:
m
::D::D
'"
CX>
:<
r
OQ26
OQ35
t
I~
I
00
0
»»
==:==:
:>z
c
00
<
Cii
m
c...
:>-
~
~
..
;;::
(J)
'":b
01
co
-'="
....... Q)
..... en
en
.......
NO)
~~
1M x4
AO-A9
RAS
DQl
OQ2
z==:
Co) Co)
0) 0)
~ Vi
CAS2
.,1.
Q)-'="
""
en en
OE
"- CASl
"- OE
==:==:
N .....
-,="N
mOl
1M x4
AO-A9
RAS
OQ1- ~
OQ4
~
r-.. CASl
OQl .... DQ8
OQ2 .... DQ17
OE
OQ1OQ4
DQ25
~~AS
-
""
-0
-0
-1-1
~ ViCAS
W
~CAS2
.,1.
"-
;
1M x4
AD-A9
RAS
~AD-A9
OE
mOl
Co) Co)
0)0)
"- CAS
CAS
OQ1OQ4
.~
Vi
r-.. CAS
~
z==:
lMx4
AD-A9
RAS
OQ21
1M x4
AD-A9
RAS
OQ7
~
~
1M x4
AD-A9
RAS
<0
<0
'"
==:==:
CC
CC
rr
mm
functional block diagram (for TM248NBK36C, Side 2)
~
(J)
;::
3:3:
N .....
f
co
"'"
Z3:
CD
AO-A,,10
;::
RA~
~
0
RAS3
::J:
;0
<0
~
~1 -
CAS1-
~
1ii
m
CAS3-
CAS2-
0
,10
101M x 4
~ AO-A9
~
~
..J::::,~AS
...... CAS
r-
~
o
~Z
i~
~@~
~
~
'" W
'" CAS
~
OE
.::L-
OQ1-~DQ4- -=DQ4
OE
"
~
DQ1OQ4 "-DQ18DQ21
c±
CAS
DQ1-~DQ13- ~
DQ4
""-
CAS
f
OQ16
10
Vi
"- CAS
"- OE
DQ1DQ4 "-DQ22DQ25
~
10 1M x4
AO-A9
RAS
.::L-
"
Vi
I'-
CAS2
OE
_
DQ1 ~OQ8
EQ2~OQ17
DQ27DQ30
I
.::L-
"
'"
Z3:
00
CO"'"
...... co
..... UI
UI ......
mm
~~
CAS
!!!m
OE
DQ31OQ34
I
-f=i
~~
Zz
»»
!i:3:
00
:::U:::u
»»
3:3:
CAS2
CAS1
DQ1 I<
DQ2 ~
CO"'"
-<-<
Ww
Vi
OE
3:3:
N .....
""'N
NQ)
~
~ Vi
.1'- CAS1
-f-f
CD
CD
1Mx4
AO-A9
RAS
DQ1- ~
DQ4
s>s>
~
1Mx4
AO-A9
RAS
~
~
~
~
"
mm
~~
Q)Q)
mm
~~
Q)Q)
'" (no
N .....
c
OE
DQ1OQ4
"'" N
»
~ ViCAS
Vi
OE
z~
1M x4
~ AO-A9.
RAS
1Mx4
Vi
OE
"-
1M x4
AO-A9
RAS
~ AO-A9
RAS
1M x4
AO-A9
RAS
DQ7
~
~
CAS
DQ1..-DQ9DQ4
DQ12
10
101M x 4
AO-A9
!!,.AS
~~~d
.
J.
"-
~
Vi
DQ1-..DQ4
DQO--=OQ3
~
L.t:"
:.:7'
g;:::...
~~
"- OE
1M x4
AO-A9
RAS
-f-f
'"
;;;
;::
DQ26
DQ35
I
3:3:
00
Cc
C:c:
"mm
TM124MBK36C, TM124MBK365 1048576 BY 36·BIT DYNAMIC RAM MODULE
TM248NBK36C, TM248NBK365 2 097152 BY 36·BIT DYNAMIC RAM MODULE
SMMS138A-MARCH 1992-REVISED JANUARY 1993
absolute maximum ratings over operating free·alr temperature range (unless otherwise noted)t
Supply voltage range on Vee (see Note 1) ............................................. - 1 V to 7 V
Supply voltage range on any pin (see Note 1) .......................................... - 1 V to 7 V
Short circuit output current ................................................................ 50 mA
Power dissipation ......................................................................... 10 W
to 70°C
Operating free-air temperature range ..................................................
Storage temperature range ....................................................... - 55°C to 125°C
ooe
t Stresses beyond those listed under "absolute maximum ratings· may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions· is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to VSS.
recommended operating conditions
MIN
NOM
MAX
VCC
Supply voltage
4.5
5
5.5
UNIT
VIH
High-level input voltage
2.4
6.5
V
VIL
LOW-level input voltage (see Note 2)
-1
O.S
V
TA
Operating free-air temperature
0
70
·C
V
NOTE 2: The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used in this data sheet for logic
voltage levels only.
electrical characteristics over full ranges of recommended operating conditions (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
VOH
High-level output voltage
10H =-5 mA
VOL
Low-level output voltage
IOL=4.2 mA
II
Input current (leakage)
VCC = 5.5 V, VI = 0 to 6.5 V,
All other pins = 0 V to VCC
10
Output current (leakage)
ICC1
Read or write cycle current
(see Note 3)
ICC2
Standby current
ICC3
Average refresh current
(RAS-only or CBR)
(see Note 3)
ICC4
Average page current
(see Note 4)
NOTES:
'124MBK36C-60
MIN
MAX
2.4
'124MBK36C-70
MIN
MAX
'124MBK36C-SO
MIN
MAX
V
2.4
2.4
UNIT
0.4
0.4
0.4
V
:t10
:t10
:t10
j.tA
:t10
:t10
:t10
j.tA
1050
900
SOO
mA
VIH = 2.4 V (TTL),
after 1 memory cycle,
RAS and CAS high
20
20
20
mA
VIH = VCC - 0.2 V (CMOS),
after 1 memory cycle,
RAS and CAS high
10
10
10
mA
1050
900
SOO
mA
900
SOO
700
mA
~=5.5V, Vo =OtoVCC,
CAS high
VCC = 5.5 V, Minimum cycle
VCC = 5.5 V, Minimum cycle,
RAS cycling,
CAS high (RAS-only),
RAS low after CAS low (CBR)
~ = 5.~PC = Minimum,
RAS low, CAS cycling
3. Measured with a maximum of one address change While RAS = VIL.
4. Measured with a maximum of one address change while CAS = VIH.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443· HOUSTON, TEXAS 77001
5-63
TM124MBK36C, TM124MBK365 1048576 BY 36·BIT DYNAMIC RAM MODULE
TM248NBK36C, TM248NBK365 2 097152 BY 36·BIT DYNAMIC RAM MODULE
SMMS138A-MARCH 1992-REVISED JANUARY 1993
electrical characteristics over full ranges of recommended operating conditions (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
VOH
High-level output voltage
IOH=-5mA
VOL
Low-level output voltage
10L = 4.2 rnA
II
'248NBK36C-60
'248NBK36C-70
MIN
MAX
MIN
2.4
'248NBK36C-80
MIN
MAX
2.4
MAX
2.4
UNIT
V
0.4
0.4
0.4
V
Input current (leakage)
VCC = 5.5 V, VI = 0 10 6.5 V,
All other pins = 0 V to VCC
±20
±20
± 20
I!A
10
Output current (leakage)
VCC = 5.5 V, Vo = 0 to VCC,
CAS high
±20
±20
±20
I!A
ICC1
Read or write cycle current
(see Note 3)
VCC = 5.5 V, Minimum cycle
1070
920
820
rnA
VIH = 2.4 V (TTL),
after 1 memory cycle,
RAS and CAS high
40
40
40
rnA
VIH = VCC - 0.2 V (CMOS),
after 1 memory cycle,
RAS and CAS high
20
20
20
rnA
Standby current
ICC2
ICC3
Average refresh current
(RAS-only or CBR)
(see Note 3)
VCC = 5.5 V, Minimum cycle,
RAS cycling,
CAS high (RAS-only),
RAS low after CAS low (CBR)
2100
1800
1600
rnA
ICC4
Average page current
(see Note 4)
VCC = 5.5 V, IpC = Minimum,
RAS low, CAS cycling
920
820
720
rnA
NOTES: 3. Measured with a maximum of one address change while RAS = VIL.
4. Measured with a maximum of one address change while CAS = VIH.
capacitance over recommended ranges of supply voltage and operating free-air temperature,
f = 1 MHz (see Note 5)
'124MBK36C
PARAMETER
MIN
TYP
'248NBK36C
MAX
MIN
TYP
MAX
UNIT
Ci(A)
Input capacitance, address inputs
50
100
pF
CiIR)
Input capacitance, RAS inputs
35
35
pF
Ci(C)
Input capacitance, CAS inputs
21
42
pF
Ci(W)
Input capacitance, write-enable input
70
140
pF
Co (DO)
Output capacitance on DO pins
7
14
pF
NOTE 5: VCC equal to 5 V ± 0.5 V and the bias on pins under testis 0 V.
TEXAS ",
INSTRUMENTS
5-64
POST OFFICE BOX 1443· HOUSTON, TEXAS 77001
TM124MBK36C, TM124MBK36S 1048576 BY 36-BIT DYNAMIC RAM MODULE
TM248NBK36C, TM248NBK36S 2 097152 BY 36-BIT DYNAMIC RAM MODULE
SMMS138A-MARCH 1992-REVISED JANUARY 1993
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature
'124MBK36C-60
'248NBK36C-60
PARAMETER
MIN
MAX
'124MBK36C-70
'248NBK36C-70
MIN
MAX
'124MBK36C-S0
'248NBK36C-SO
MIN
UNIT
MAX
tCAC
Access time from CAS low
15
18
20
ns
tM
Access time from column-address
30
35
40
ns
tRAC
Access time from RAS low
60
70
80
ns
tCPA
Access time from column precharge
35
40
45
ns
tCL2
CAS to output in low Z
0
tOFF
Output disable time after CAS high (see Note 6)
0
NOTE 6: tOFF
IS
0
15
0
0
18
0
ns
20
ns
specified when the output is no longer driven.
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
'124MBK36C-60
'248NBK36C-60
MIN
MAX
'124MBK36C-70
'248NBK36C-70
MIN
MAX
'124MBK36C-SO
'248NBK36C-S0
MIN
UNIT
MAX
tRC
Random read or write cycle (see Note 7)
110
130
150
ns
tRWC
Read-write cycle time
130
153
175
ns
tpc
Page-mode read or write cycle time (see Note 8)
40
tRASP
Page-mode pulse duration, RAS low
60
100000
70
100000
80
100000
ns
tRAS
Non-page-mode pulse duration, RAS low
60
10000
70
10000
80
10000
ns
tCAS
Pulse duration, CAS low
15
10000
18
10000
20
10000
ns
tcp
Pulse duration, CAS high
10
10
10
tRP
Pulse duration, RAS high (precharge)
40
50
60
ns
twp
Write pulse duration
15
15
15
ns
45
50
ns
ns
tASC
Column-address setup time before CAS low
0
0
0
ns
tASR
Row-address setup time before RAS low
0
0
0
ns
tDS
Data setup time
0
0
0
ns
tRCS
Read setup time before CAS low
0
0
0
ns
tCWL
W low setup time before CAS high
15
18
20
ns
tRWL
W low setup time before RAS high
15
18
20
ns
twcs
W low setup time before CAS low
0
0
0
ns
10
10
10
ns
twSR
NOTES:
W high setup time (see Note 9)
=
7. All cycles assume IT 5 ns.
8. To assure tpc min, tASC should be greater than or equal to 5 ns.
9. CAS-before-RAS refresh only.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
5-65
TM124MBK36C, TM124MBK36S 1 048576 BY 36·BIT DYNAMIC RAM MODULE
TM248NBK36C, TM248NBK36S 2 097152 BY 36·BIT DYNAMIC RAM MODULE
SMMS138A-MARCH 1992-REVISED JANUARY 1993
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (concluded)
'124MBK36C-60
'248NBK36C-60
MIN
MAX
'124MBK36C-70
'248NBK36C-70
MIN
MAX
'124MBK36C-80
'248NBK36C-80
MIN
UNIT
MAX
tCAH
Column-address hold time after CAS low
10
15
15
ns
tDHR
Data hold time after RAS low (see Note 10)
50
55
60
ns
tDH
Data hold time
10
15
15
ns
tAR
Column-address hold time after RAS low (see Note 10)
50
55
60
ns
tClCH
Hold time, CAS low to CAS high
5
5
5
ns
tRAH
Row-address hold time after RAS low
10
10
10
ns
tRCH
Read hold time after CAS high (see Note 11)
0
0
0
ns
tRRH
Read hold time after RAS high (see Note 11)
0
0
0
ns
twCH
Write hold time after CAS low
15
15
15
ns
twCR
Write hold time after RAS low (see Note 10)
50
55
60
ns
twHR
W-high hold time (see Note 9)
10
10
10
ns
tCHR
Delay time, RAS low to CAS high (see Note 9)
15
15
20
ns
tCRP
Delay time, CAS high to RAS low
0
0
0
ns
tCSH
Delay time, RAS low to CAS high
60
70
80
ns
tCSR
Delay time, CAS low to RAS low (see Note 9)
10
10
10
ns
tRAD
Delay time, RAS low to column-address (see Note 12)
15
tRAl
Delay time, column-address to RAS high
30
35
40
teAL
Delay time, column-address to CAS high
30
35
40
tRCD
Delay time, RAS low to CAS'low (see Note 12)
20
tRPC
Delay time, RAS high to CAS low (see Note 9)
0
0
0
tRSH
Delay time, CAS low to RAS high
15
18
20
tREF
Refresh time interval
IT
NOTES:
30
15
45
20
16
Transition time
2
35
52
2
50
50
10. The minimum value is measured when tRCD is set to tRCD min as a reference.
11. Either tRRH or tRCH must be satisfied for a read cycle.
12. The maximum value is specified only to assure access time.
device symbolization (TM124MBK36C illustrated)
00 DODD 0DDODo
-SS
YY
MM
T
-SS
Year Code
Month Code
Assembly Site Code
Speed Code
NOTE: Location of symbolization may vary.
TEXAS
.~
INsrRUMENTS
5-66
POST OFFICE BOX 1443' HOUSTON. TEXAS 77001
20
16
9. CAS-before-RAS refresh only.
TM124MBK36C
15
VYMMT
2
40
ns
ns
ns
60
ns
ns
ns
16
ms
50
ns
TM4100EAD9
4194304 BY 9·BIT DYNAMIC RAM MODULE
SMMS419A-NOVEMBER 1991-REVISED JANUARY 1993
•
•
•
•
Organization ... 4 194 304 x 9
SINGLE IN·LlNE MODULEt
(TOP VIEW)
Single 5-V Power Supply (±10% Tolerance)
30-Pin Single In-Line Memory Module
(SIMM) for Use With Sockets
0
Utilizes Nine 4-Megabit Dynamic RAMs in
Plastic Small-Outline J-Lead Packages
(SOJs)
•
Long Refresh Period. .. 16 ms
(1024 Cycles)
•
All Inputs, Outputs, and Clocks Fully TTL
Compatible
•
•
3-State Outputs
VCC
CAS
D01
1
2
AD
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
3
A1
D02
A2
A3
Vss
D03
A4
A5
DQ4
A6
A7
D05
A8
A9
A10
D06
Performance Ranges:
ACCESS
ACCESS
TIME
TIME
READ
OR
(tRAC)
(tAAl
WRITE
CYCLE
(MAX)
(MAX)
(MIN)
TM4100EAD9-60
60 ns
15 ns
110 ns
TM4100EAD9-70
70 ns
18 ns
130 ns
TM4100EAD9-80
80 ns
20 ns
150 ns
•
Common CAS Control for Eight Common
Data-In and Data-Out Lines
•
Separate CAS Control for One Separate
Pair of Data-In and Data-Out Lines
•
•
Low Power Dissipation
IN
Vss
D07
NC
D08
09
RAS
CAS9
D9
VCC
D
D
D
D
D
D
D
D
D
0
t The package shown is for pinout reference only.
Operating Free-Air Temperature Range
O°C to 70°C
PIN NOMENCLATURE
description
The TM4100EAD9 is a dynamic random-access
memory module organized as 4 194 304 x 9 [bit
nine (09, 09) is generally used for parity and is
controlled by CAS9] in a 30-pin lead less Single
in-line memory module (SIMM).
This module is composed of nine TMS44100DJ,
4 194 304 x 1-bit dynamiC RAMs each in a
20/26-lead plastic small-outline J-Iead package
(SOJ) mounted on a substrate with decoupling
capacitors.
AO--A10
Address Inputs
CAS, CAS9
Column-Address Strobe
D01-DQ8
Data In/Data Out
D9
Data In
NC
No Internal Connection
09
Data Out
RAS
Row-Address Strobe
VCC
5-V Supply
VSS
Ground
W
Write Enable
The TM41 00EAD9 is available in the AD single-sided, leadless module for use with sockets.
The TM41 00EAD9 is characterized for operation from O°C to 70°C.
~~o~~~T~~~o~I~ .1;!~I~~~I~~.I~e;~h:~!r!~ :: 1e~:!II~~~~m~~:~
standard warranty. Production procel.lng does not necessarily Include
teatlng of all parameter•.
TEXAS
~
Copyright © 1993. Texas Instruments Incorporated
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
5-67
TM4100EAD9
4194 3048Y 9·81T DYNAMIC RAM MODULE
SMMS419A-NOVEMBER 1991-REVISED JANUARY 1993
operation
The TM41 00EAD9 operates as nine TMS441 OODJs connected as shown in the functional block diagram. Refer
to the TMS441 00 data sheet for details of its operation. The common I/O feature of the TM41 00EAD9 dictates
the use of early write cycles to prevent contention on D and Q.
single In·llne memory module and components
PC substrate: 1,27 mm (0.05 inch) nominal thickness; 0.005 inch/inch maximum warpage
Bypass capacitors: Multilayer ceramic
Contact area for socketable devices: Nickel plate and solder plate over copper
TEXAS ~
INSTRUMENTS
5-68
POST OFFICE BOX 1443' HOUSTON. TEXAS 77001
TM4100EAD9
4194304 BY 9·BIT DYNAMIC RAM MODULE
SMMS419A-NOVEMBER 1991-REVISED JANUARY 1993
functional block diagram
AO-A10
RAS
CAS
W
~
.1'I'-
OQ1
VCC
~
"
"
"
I
""-
OQ3
""-
I
0
4096Kx 1
11<,,- AO·A10
RAS
I'- CAS
" w
0
VSS Q
OQS
I
l
~
l
OQ6
I
VCC
VSS Q
l
4096Kx 1
AO·A10
RAS
CAS
""- w
OQ7
l
0
I
Vcc
~
W
OQS
VCC
" w
0
~
4096K x 1
AO·A10
RAS
CAS
0
VSS Q l
4096K x 1
11(" AO·A10
RAS
CAS
W
VSS Q
VCC
'"
4096K x 1
AO·A10
RAS
CAS
Vcc
~
OQ4
W
0
I
VSS Q
4096Kx 1
AO·A10
RAS
CAS
VCC
~
~
W
0
I
OQ2
4096K x 1
AO·A10
RAS
CAS
VSS Q l
09
l
4096Kx 1
AO·A10
RAS
CAS
" w
'"
I
~
CAS9
VSS Q
'"
"
0
VCC
VSS Q
l
4096K x 1
AO·A10
RAS
CAS
W
0
VCC
VSS Q l
Q9
VCC
1
T
I
1
c .... c T
VSS
TEXAS
~
INsrRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
5·69
TM4100EAD9
4 194 304 BY 9-BIT DYNAMIC RAM MODULE
SMMS419A-NOVEMBER 1991-REVISED JANUARY 1993
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage range on any pin (see Note 1) .......................................... - 1 V to 7 V
Voltage range on Vee (see Note 1) ................................................... - 1 V to 7 V
Short circuit output current ................................................................ 50 mA
Power dissipation ..........................................................................9 W
Operating free-air temperature range .................................................. O°C to 70°C
Storage temperature range ....................................................... - 55°C to 125°C
t Stresses beyond those listed under 'absolute maximum ratings" may cause permanent damage to the device. This is a stress rating only, and
functional operation olthe device atthese or any other conditions beyond those Indicated in the ·recommended operating conditions· section of
this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to VSS.
recommended operating conditions
MIN
NOM
MAX
Vee
Supply voltage
4.5
5
5.5
V
VIH
High-level input vo~age
2.4
6.5
V
VIL
Low-level input voltage (see Note 2)
-1
0.8
V
TA
Operating free-air temperature
0
70
·C
..
..
..
NOTE 2: The algebraic convention, where the more negative (less posnlve) limit IS designated as minimUm,
vo~age levels only.
IS
used
10
UNIT
this data sheet for logiC
electrical characteristics over full ranges of recommended operating conditions (unless otherwise
noted)
PARAMETER
'4100EAD9-BO
'4100EAD9-70
'4100EAD9-80
MIN
MIN
MIN
UNIT
TEST CONDITIONS
MAX
MAX
MAX
VOH
High-level output vo~age
10H =-5mA
VOL
Low-level output voltage
10L= 4.2 mA
0.4
0.4
0.4
V
II
Input current Oeakage)
VI = 0 to 6.5 V, Vce = 5.5 V,
All other pins = 0 V to VCC
:tl0
:tl0
:tl0
f!A
10
Output current (leakage)
Vo = 0 to VCC, VCC = 5.5 V,
CAS high
:tl0
:tl0
:tl0
f!A
ICCl
Read or write cycle current
(see Note 3)
Minimum cycle, VCC = 5.5 V
945
810
720
rnA
18
18
18
2.4
2.4
V
2.4
Atter 1 memory cycle,
RAS and CAS high,
VIH = 2.4 V (TTL)
ICC2
mA
Standby current
Atter 1 memory cycle,
RAS and CAS high,
9
9
9
945
810
720
rnA
810
720
630
mA
VIH = VCC - 0.2 V (CMOS)
ICC3
Average refresh current
(RAS only or CBR)
(see Note 3)
Minimum cycle, VCC = 5.5 V,
RAS cycling,
CAS high (RAS only),
RAS low atter CAS low (CBR)
ICC4
NOTES:
Average page current
(see Note 4)
tpc = minimum, VCC = 5.5 V,
RASlow,
CAS cycling
3. Measured with a maximum of one address change while RAS = VIL.
4. Measured with a maximum of one address change while CAS = VIH.
1ExAs
..If
INSrRUMENTS
5-70
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
TM4100EAD9
4 194 304 BY 9-BIT DYNAMIC RAM MODULE
SMMS419A-NOVEMBER 1991-REVISED JANUARY 1993
capacitance over recommended ranges of supply voltage and operating free-air temperature,
f = 1 MHz (see Note 5)
PARAMETER
MIN
MAX
UNIT
Ci(A)
Input capacitance, address inputs
Ci(O)
Input capacitance, data input (pin 09)
Ci(RC)
Input capacitance, strobe inputs
63
pF
Ci(W)
Input capacitance, write-enable input
63
pF
Co(OO)
Output capacitance (pins 001-008)
12
pF
Co
Output capacitance (pin 09)
7
pF
NOTE 5: VCC equal to 5 V
±
0.5 V and the bias on pin under test
IS
45
pF
5
pF
0 V.
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature
PARAMETER
'4100EAD9-60
'4100EAD9-70
MIN
MIN
MAX
MAX
'4100EAD9-80
MIN
UNIT
MAX
tAA
Access time from column-address
30
35
40
ns
!cAC
Access time from CAS low
15
18
20
ns
tCPA
Access time from column precharge
35
40
45
ns
tRAC
Access time from RAS low
60
70
80
ns
tCLZ
CAS to output in low Z
0
tOFF
Output disable time after CAS high
(see Note 6)
0
NOTE 6: toFF
"
IS speCified
when the output
IS
15
0
ns
0
0
18
0
20
ns
no longer driven.
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443· HOUSTON. TEXAS 77001
5-71
TM4100EAD9
4194304 BY 9-BIT DYNAMIC RAM MODULE
SMMS419A-NOVEMBER 1991-REVISED JANUARY 1993
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
'4100EAD9-60
MIN
MAX
'4100EAD9-70
MIN
MAX
'4100EAD9-BO
MIN
MAX
UNIT
tRC
Random read or write cycle time (see Note 7)
110
130
150
tpc
Page-mode read or write cycle time (see Note 8)
40
45
50
tRASP
Page-mode pulse duration, RAS low (see Note 9)
60
100000
70
100000
80
100000
ns
tRAS
Non-page-mode pulse duration, RAS low (see Note 9)
60
10000
70
10000
80
10000
. ns
tCAS
Pulse duration, CAS low (see Note 10)
15
10 000
18
10000
20
10000
ns
tcP
Pulse duration, CAS high
10
10
10
ns
tRP
Pulse duration, RAS high (precharge)
40
50
60
ns
twP
Write pulse duration
15
15
15
ns
tASC
Column-address setup time before CAS low
0
0
0
ns
tASR
Row-address setup time before RAS low
0
0
0
ns
tDS
Data setup time (see Note 11)
0
0
0
ns
0
0
0
ns
ns
ns
tRCS
Read setup time before CAS low
tcWL
W low setup time before CAS high
15
18
20
ns
tRWL
W low setup time before RAS high
15
18
20
ns
twcs
W low setup time before CAS low (Early write operation only)
0
0
0
ns
twSR
W high setup time (CAS-before-RAS refresh only)
10
10
10
ns
twTs
W low setup time (test mode only)
10
10
10
ns
tCAH
Column-address hold time after CAS low
10
15
15
ns
tDHR
Data hold time after RAS low (see Note 12)
50
55
60
ns
tDH
Data hold time (see Note 10)
10
15
15
ns
tAR
Column-address hold time after RAS low (see Note 12)
50
55
60
ns
tRAH
Row-address hold time after RAS low
10
10
10
ns
tRCH
Read hold time after CAS high (see Note 13)
0
0
0
ns
tRRH
Read hold time after RAS high (see Note 13)
0
0
0
ns
twCH
Wr~e
15
15
15
ns
hold time after CAS low (Early write operation only)
twCR
Write hold time after RAS low (see Note 12)
50
55
60
ns
twHR
W high hold time (CAS-before-RAS refresh only)
10
10
10
ns
Conbnued next page.
NOTES: 7. All cycle times assume IT = 5 ns.
8. To assure tpc min, tASC should be greater than or equal to 5 ns.
9. In a read-write cycle, tRWD and tRWL must be observed.
10. In a read-write cycle, tCWD and tCWL must be observed.
11. Referenced to the later of CAS or 'iN in write operations.
12. The minimum value is measured when tRCD is set to tRCD min as a reference.
13. Either tRRH or tRCH must be satisfied for a read cycle.
TEXAS ~
INSTRUMENTS
5-72
POST OFFICE BOX 1443 • HOUSTON. TEXAS nOO1
TM4100EAD9
4194304 BY 9-BIT DYNAMIC RAM MODULE
SMMS419A-NOVEMBER 1991-REVISED JANUARY 1993
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (concluded)
'4100EAD9-60
MIN
MAX
'4100EAD9-70
MIN
MAX
'4100EAD9-80
MIN
UNIT
MAX
twrH
W low hold time (test mode only)
10
10
10
ns
tcHR
Delay time, RAS low to CAS high
(CAS-before-RAS refresh only)
15
15
20
ns
tCRP
Delay time, CAS high to RAS low
0
0
0
ns
tcSH
Delay time, RAS low to CAS high
60
70
80
ns
tCSR
Delay time, CAS low to RAS low (CAS-before-RAS refresh only)
10
10
10
tRAD
Delay time, RAS low to column-address (see Note 14)
15
tRAl
Delay time, column-address to RAS high
30
30
15
35
35
15
ns
40
40
ns
ns
tCAl
Delay time, column address to CAS high
30
tRCD
Delay time, RAS low to CAS low (see Note 14)
20
tRPC
Delay time, RAS high to CAS low
0
0
0
ns
tRSH
Delay time, CAS low to RAS high
15
18
20
ns
!TAA
Access time from address (test mode)
35
40
45
ns
!TCPA
Access time from column precharge (test mode)
40
45
50
ns
!TRAC
Access time from RAS (test mode)
65
75
85
tREF
Refresh time interval
!T
Transition time
20
2
50
52
20
16
16
..
40
35
45
2
50
2
ns
60
ns
ns
16
ms
50
ns
NOTE 14: The ma>(lmum value IS specified only to assure access time.
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS nOO1
5-73
TM4100EAD9
4194304 BY 9·BIT DYNAMIC RAM MODULE
SMMS419A-NOVEMBER 1991-REVISED JANUARY 1993
device symbolization
m"oo~oo
Io
-SS
YVMMT
000000000000000000000000000000
YV = Year Code
MM
= Month Code
T = Assembly Site Code
-SS
= Speed
NOTE: The location of symbolization may vary.
TEXAS ~
INSTRUMENTS
5-74
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
0~
TM4100GAD8
4194304 BY 8-BIT DYNAMIC RAM MODULE
SMMSS08A-MARCH 1992-REVISED JANUARY 1993
•
Organization. .. 4 194 304 x 8
•
•
Single 5-V Power Supply (±10% Tolerance)
SINGLE IN-LINE MODULEt
30-Pln Single In-Line Memory Module
(SIMM) for Use With Sockets
0
•
Utilizes Eight 4-Megabit Dynamic RAMs in
Plastic Small-Outline J-Lead Packages
(SOJs)
•
Long Refresh Period. .. 16 ms
(1024 Cycles)
•
All Inputs, Outputs, Clocks Fully
TIL Compatible
•
3-State Output
•
Performance Ranges:
ACCESS
'4100GAD8-60
'4100GAD8-70
'4100GAD8-80
•
•
•
(TOP VIEW)
ACCESS ACCESS
READ
TIME
TIME
TIME
OR
IRAC
lAA
ICAC
(MAX)
(MAX)
(MAX)
WRITE
CYCLE
(MIN)
60 ns
30 ns
35 ns
40 ns
15 ns
18 ns
70 ns
80 ns
20 ns
VCC
CAS
DOl
AO
Al
D02
A2
A3
Vss
D03
A4
A5
D04
AS
A7
D05
A8
A9
Al0
D06
W
Vss
D07
NC
D08
NC
RAS
NC
NC
VCC
110 ns
130 ns
150 ns
Common CAS Control for Eight Common
Data-In and Data-Out Lines
Low Power Dissipation
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
D
D
D
D
D
D
D
D
0
Operating Free-Air Temperature Range
O°C to 70°C
t The package shown is for pinout reference only.
description
The TM4100GAD8 is a dynamic random-access
memory module organized as 4 194 304 x 8-bits
in a 30-pin leadless single in-line memory module
(SIMM).
PIN NOMENCLATURE
AO-A 10
CAS
D01-D08
NC
RAS
VCC
VSS
The SIMM is composed of eight TMS44100DJ,
4 194 304 x 1-bit dynamic RAMs in 20/26-lead
plastic small-outline J-Iead packages (SOJ) ,
mounted on a substrate with decoupling capacitors.
W
Address Inputs
Column-Address Strobe
Data In/Data Out
No Internal Connection
Row-Address Strobe
5-V Supply
Ground
Write Enable
The TM4100GAD8 is available in the AD
single-sided, lead less module for use with
sockets.
The TM4100GAD8 is characterized for operation
from O°C to 70°C.
~~o~~:~~~o~l: .1~~:~~~~I~~':h:~!r: ::!.~:!II:~~m~~~
ltandard warranty. Production proc".lng do.. not nlce .. arlly Include
Intlng of all paramat,r..
TEXAS
~
Copyright © 1993, Texas Instruments Incorporated
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
5-75
TM4100GAD8
4194304 BY 8·BIT DYNAMIC RAM MODULE
SMMS508A-MARCH 1992-REVISED JANUARY 1993
operation
The TM41 00GAD8 operates as eight TMS441 OODJs connected as shown in the functional block diagram. Refer
to the TMS441 00 data sheet for details of its operation. The common I/O feature of the TM41 00GAD8 dictates
the use of early write cycles to prevent contention on D and Q.
single in·line memory module and components
PC substrate: 1,27 mm (0.05 inch) nominal thickness; 0.005 inch/inch maximum warpage
Bypass capacitors: Multilayer ceramic
Contact area for socketable devices: Nickel plate and solder plate over copper
TEXAS ~
INSTRUMENTS
5-76
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
TM4100GAD8
4194304 BY 8·BIT DYNAMIC RAM MODULE
SMMS50BA-MARCH 1992-REVISED JANUARY 1993
functional block diagram
AO-A10
RAS
CAS
Vi
~
f'.f'.-
DQ1
I
f'.-
I
f'.-
DQ3
DQ6
1
f'.f'.f'.-
VSS Q l
DQ7
VSS Q
l
VSS Q l
Vi
D
VCC
1
Vi
DQB
Vss Q n
1
Vcc
;;::
I
+
4096K x 1
AO-A10
RAS
CAS
D
I
"
"
Vi
VCC
VCC
VSS Q J
4096K x 1
, 1!(f'., AO-A10
RAS
CAS
f'.,
4096K x 1
AO-A10
RAS
CAS
Vcc
D
I
Vi
D
Vi
4096K x 1
, 1!f'., AO-A10
RAS
f'.,
CAS
4096K x 1
AO-A10
RAS
CAS
I
f'.,
"f'.,
Vi
D
Vcc
Vss Q
l
4096K x 1
AO-A10
RAS
CAS
Vi
D
Vcc
Vss Q l
I
r::
VSS
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
5-77
TM4100GAD8
4 194 304 BY 8·BIT DYNAMIC RAM MODULE
SMMS508A-MARCH 1992-REVISED JANUARY 1993
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage range on any pin (see Note 1) .......................................... - 1 V to 7 V
Supply voltage range on Vee ......................................................... - 1 V to 7 V
Short circuit output current ............................. ,.................................. 50 mA
Power dissipation .......................................................................... 8 W
Operating free-air temperature range, TA .............................................. O°C to 70°C
Storage temperature range ....................................................... - 55°C to 125°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. This is a stress rating only, and
functional operation of the device at these or any other conditions beyond those indicated in the "recommended operating conditions" section of
this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to VSS.
recommended operating conditions
MIN
NOM
MAX
VCC
Supply voltage
4.5
5
5.5
UNIT
V
VIH
High-level input voltage
2.4
6.5
V
VIL
Low-level input voltage (see Note 2)
-1
0.8
V
TA
Operating free-air temperature
0
70
·C
NOTE 2: The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used in this data sheet for logic
voltage levels only.
electrical characteristics over full ranges of recommended operating conditions (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
'4100GADB-60
MIN
VOH
High-level output voltage
VOL
Low-level output voltage
II
Input current (leakage)
10
Output current (leakage)
ICCl
Read or write cycle current
(see Note 3)
Standby current
ICC4
UNIT
MAX
2.4
V
IOL=4.2mA
0.4
0.4
V
VCC = 5.5 V, VI = 0 to 6.5 V,
All other pins = 0 V to V CC
±10
±10
±10
IlA
±10
±10
±10
I-iA
840
720
640
mA
16
16
16
mA
8
8
8
mA
840
720
640
mA
720
640
560
mA
Vo = Oto VCC,
VCC = 5.5 V, CAS high
VCC = 5.5 V, Minimum cycle
RAS and CAS high,
VIH = VCC - 0.2 V (CMOS),
Average refresh current
(RAS-only or CBR)
(see Note 3)
Average page current
(see Note 4)
VCC = 5.5 V,
Minimum cycle,
RAS cycling, CAS high
VCC = 5.5 V,
lc(p) = minimum,
RAS low, CAS cycling
NOTES: 3. Measured with a maximum of one address change while RAS = VIL.
4. Measured with a maximum of one address change while CAS = VIH.
TEXAS
~
INSTRUMENTS
5-78
'4100GAD8-80
MIN
MAX
0.4
After 1 memory cycle,
RAS and CAS high
ICC3
'4100GADB-70
MIN
2.4
2.4
10H =-5mA
VIH = 2.4 V (TTL),
After 1 memory cycle,
ICC2
MAX
POST OFFICE BOX 1443' HOUSTON, TEXAS 77001
TM4100GAD8
4194304 BY 8-BIT DYNAMIC RAM MODULE
SMMS508A-MARCH 1992-REVISED JANUARY 1993
capacitance over recommended. ranges of supply voltage and operating free-air temperature,
f = 1 MHz
PARAMETER
MIN
MAX
UNIT
Ci(A)
Input capacitance, address inputs
40
pF
Ci(RC)
Input capacitance, strobe inputs
56
pF
Ci(W)
Input capacitance, write-enable input
56
pF
Co
Output capacitance (pins 001-008)
12
pF
NOTE 5: VCC equal to 5 V ± 0.5 V and the bias on the pin under test is 0 V.
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature
PARAMETER
'4100GADB-60
'4100GADB-70
MIN
MIN
MAX
MAX
'4100GADB-80
MIN
UNIT
MAX
tAA
Access time from column-address
30
35
40
ns
tCAC
Access time from CAS low
15
18
20
ns
tePA
Access time from column precharge
35
40
45
ns
tRAC
Access time from RAS low
60
70
80
ns
tCLZ
CAS to output in low Z
0
toFF
Output disable time after CAS high (see Note 6)
0
NOTE 6: tOFF
IS
..
speCified when the output
IS
0
15
0
0
18
0
ns
20
ns
no longer driven.
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443' HOUSTON, TEXAS 77001
5-79
TM4100GAD8
4 194 304 BY 8-BIT DYNAMIC RAM MODULE
SMMS508A-MARCH 1992-REVISED JANUARY 1993
timing requirements over recommended ranges of supply. voltage and operating free-air
temperature
'4100GAD8-60
'41ooGAD8-70
'41ooGAD8-80
MIN
MIN
MIN
MAX
MAX
UNIT
MAX
tRC
Random read or write cycle (see Note 7)
110
130
150
tpc
Page-mode read or write cycle time (see Note 8)
40
45
ns
50
tRASP
Page-mode pulse duration, RAS low
60
100000
70
100000
tRAS
Non-page-mode pulse duration, RAS low
60
10000
70
10000
tCAS
Pulse duration, CAS low
15
10 000
18
10000
tcp
Pulse duration, CAS high
10
10
10
ns
tRP
Pulse duration, RAS high (precharge)
40
50
60
ns
twp
Write pulse duration
15
15
15
ns
tASC
Column-address setup lime before CAS low
0
0
0
ns
tASR
Row-address setup time before RAS low
0
0
0
ns
tDS
Data setup time
0
0
0
ns
tRCS
Read setup time before CAS low
0
0
0
ns
tCWL
W low setup time belore CAS high
15
18
20
ns
tRWL
W low setup time before RAS high
15
18
20
ns
twcs
W iow setup time before CAS low
0
0
0
ns
twSR
W high setup time (CAS-belore-RAS refresh only)
10
10
10
ns
twTs
W low setup time (test mode only)
10
10
10
ns
leAH
Column-address hold time after CAS low
10
15
15
ns
tDHR
Data hold time after RAS low (see Note 9)
50
55
60
ns
tDH
Data hold time
10
15
15
ns
tAR
Column-address hold time after RAS low (see Nole 9)
50
55
60
ns
ns
80
100000
ns
80
10000
ns
20
10000
ns
tRAH
Row-address hold time after RAS low
10
10
10
ns
tRCH
Read hold time after CAS high (see Note 10)
0
0
0
ns
tRRH
Read hold time after RAS high (see Note 10)
0
0
0
ns
twCH
Write hold time after CAS low
15
15
15
ns
twCR
Write hold time after RAS low (see Nole 9)
50
55
60
ns
twHR
W high hold time (CAS-before-RAS refresh only)
10
10
10
ns
twTH
W low hold time (test mode only)
10
10
10
ns
Cqntinued next page.
NOTES: 7. All cycle times assume IT = 5 ns.
8. To assure tpc min, tASC should be greater than or equal to tcp.
9. The minimum value is measured when tRCD is set to tRCD min as a reference.
10. Either tRRH or tRCH must be satislied lor a read cycle.
TEXAS . "
INSTRUMENTS
5-80
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
TM4100GAD8
4194304 BY 8·BIT DYNAMIC RAM MODULE
SMMS508A-MARCH 1992-REVISED JANUARY 1993
timing requirements over recommended ranges of supply voltage and operating free·air
temperature (concluded)
'4100GADS-60
MIN
MAX
'41 00GADS-70
MIN
MAX
'4100GADS-80
MIN
UINT
MAX
tCHR
Delay time, RAS low to CAS high
(CAS-before-RAS refresh only)
tCRP
Delay time, CAS high to RAS low
0
tCSH
Delay time, RAS low to CAS high
60
tcSR
Delay time, CAS low to RAS low
(CAS-before-RAS refresh only)
10
10
tRAD
Delay time, RAS low to column-address (see Note 11)
15
tRAl
Delay time, column-address to RAS high
30
35
40
tCAl
Delay time, column-address to CAS high
30
35
40
tRCD
Delay time, RAS low to CAS low (see Note 11)
20
tRPC
Delay time, RAS high to CAS low
0
a
a
tRSH
Delay time, CAS low to RAS high
15
18
20
ns
!TAA
Access time from address (test mode)
35
40
45
ns
!TCPA
Access time from column precharge (test mode)
40
45
50
ns
!TRAC
Access time from RAS (test mode)
65
75
85
ns
tREF
Refresh time interval
!T
Transition time
15
15
30
45
20
ns
0
0
ns
70
80
ns
10
ns
15
20
16
2
50
35
52
15
20
16
2
50
2
40
ns
ns
ns
60
ns
ns
16
ms
50
ns
NOTE 11: The maximum value is specified only to assure access time.
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
5-81
TM4100GAD8
4194304 BY 8·BIT DYNAMIC RAM MODULE
SMMS508A-MARCH 1992--f1EVISED JANUARY 1993
device symbolization
Io
~,,~~
-55
VYMMT
000000000000000000000000000000
=
=
VY
Year Code
MM
Month Code
T = Assembly Site Code
-SS = Speed
NOTE: The location of symbolization may vary.
TEXAS .,.,
INSTRUMENTS
5-82
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
0~
TM497GADSA
4194 304-WORD BY S-BIT DYNAMIC RAM MODULE
SMMS476-DECEMBER 1992
•
•
•
•
Organization, , , 4 194 304 x 8
SINGLE-IN-LINE PACKAGEt
(TOP VIEW)
Single S-V Power Supply
o
30-Pln Single In-Line Memory Module
(SIMM) for Use With Sockets
Utilizes Two 1S-Megablt Dynamic RAMs In
Plastic Small-Outline J-Lead Packages
(SOJs)
•
Long Refresh Period, " 32 ms
(2048 Cycles)
•
All Inputs, Outputs, Clocks Fully
TTL Compatible
•
3-State Output
•
Performance Ranges:
ACCESS
TIME
'497GAD8A-60
'497GAD8A-70
'497GAD8A-80
'497GAD8A-l0
ACCESS ACCESS
TIME
TIME
tRAC
tAA
tCAC
(MAX)
60 ns
70 ns
80 ns
100 ns
(MAX)
30ns
35 ns
40 ns
50 ns
(MAX)
15ns
18 ns
20 ns
25 ns
READ
OR
WRITE
CYCLE
(MIN)
110ns
130 ns
150 ns
180 ns
•
Common CAS Control for Eight Common
Data-In and Data-Out Lines
•
Low Power Dissipation
•
Operating Free-Air Temperature Range
O·C to 70·C
VCC
CAS
DQl
1
2
3
AO
4
Al
DQ2
A2
A3
5
6
7
8
Vss
9
DQ3
A4
AS
DQ4
A6
A7
DQ5
A8
A9
Al0
DQ6
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
IN
VSS
DQ7
NC
DQ8
NC
RAS
NC
NC
VCC
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c
«
description
PIN NOMENCLATURE
The TM497GADSA is a 32M dynamic
random-access memory module organized as
4 194 304 x S-bits in a 30-pin leadless single
in-line memory module (SIMM),
AO-Al0
CAS
DQ1-DQ8
NC
RAS
The SIMM is composed of two TMS417400DZ,
4 194 304 x 4-bit dynamic RAMs in 24/2S-lead
plastic small-outline J-Iead packages (SOJ),
mounted on a substrate with decoupling
capacitors,
VCC
VSS
IN
Address Inputs
Column-Address Strobe
Data In/Data Out
No Internal Connection
Row-Address Strobe
5-V Supply
Ground
Write Enable
The TM497GADSA is characterized for operation from O·C to 70·C.
TEXAS
~
Copyright © 1992, Texas Instruments Incorporated
INsrRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
5-83
TM497GAD8A
4194 304·WORD BY 8·BIT DYNAMIC RAM MODULE
SMMS476-0ECEMBER 1992
operation
The TM497GAD8A operates as two TMS417400DZs connected as shown in the functional block diagram.
Refer to the TMS417 400 data sheet for details of its operation. The common I/O feature of the TM497GAD8A
dictates the use of early write cycles to prevent contention on D and Q.
single in-line memory module and components
PC substrate: 1,27 mm (0.05 inch) nominal thickness; 0.005 inch/inch maximum warpage
Bypass capacitors: Multilayer ceramic
Contact area for socketable devices: Nickel plate and solder plate over copper
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TEXAS·~
INsrRUMENTS
5-84
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
TM497GAD8A
4 194 304·WORD BY 8·BIT DYNAMIC RAM MODULE
SMMS478--DECEMBER 1992
functional block diagram
4Mx4
11
AO-A10 -----+----'-;<1 AO-A10 DQ1
DQ2
RAS -----4H----'-"I RAS
DQ3
CAS ---+--f--+----'-"I CAS
DQ4
W ---+-+-1--+----'-"1 W
OE
11
4Mx4
AO-A10 DQ1
DQ2
RAS
DQ3
CAS
DQ4
W
OE
1
2
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQS
z
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c
«
TEXAS ~
INsrRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
5-85
TM497GAD8A
4 194 304·WORD BY 8·BIT DYNAMIC RAM MODULE
SMMS478-DECEMBER 1992
absolute maximum ratings over operating free·air temperature range (unless otherwise noted)t
Supply voltage range on any pin (see Note 1) .......................................... - 1 V to 7 V
Supply voltage range on Vee ......................................................... - 1 V to 7 V
Short circuit output current ................................................................ 50 mA
Power dissipation .......................................................................... 2 W
Operating free-air temperature range, TA .............................................. O°C to 70°C
Storage temperature range ....................................................... - 55°C to 125°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to VSS.
recommended operating conditions
»
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-z
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z
MIN
NOM
MAX
VCC
Supply voltage
4.5
5
5.5
V
VIH
High-level input voltage
2.4
6.5
V
VIL
Low-level input voltage (see Note 2)
-1
O.S
V
TA
Operating free-air temperature
0
70
·C
..
..
..
UNIT
NOTE 2: The algebraic convention, where the more negative (less positive) limit IS deSignated as minimum. IS used In thiS data sheet for logiC
voltage levels only.
electrical characteristics over full ranges of recommended operating conditions (unless otherwise
noted)
PARAMETER
'497GADSA-60
TEST CONDITIONS
VOH
High-level
output voltage
IOH=-5mA
VOL
Low-level
output voltage
IOL=4.2 mA
II
Input current
(leakage)
MIN
'497GADBA-70
MAX
MIN
2.4
MAX
'497GADBA-B0
MIN
MAX
2.4
2.4
'497GADBA-10
MIN
MAX
2.4
UNIT
V
0.4
0.4
0.4
0.4
V
VCC = 5 V, VI = 0 to 6.5 V.
All other pins = 0 V to VCC
%10
%10
%10
±10
IlA
10
Output current
(leakage)
VO=OtoVCC.
VCC = 5.5 V, CAS high
%10
%10
%10
%10
ItA
ICCl
Read or write
cycle current
(see Note 3)
VCC =5.5V.
Minimum cycle
240
220
200
180
mA
VIH = 2.4 V (TTL),
After 1 memory cycle.
RAS and CAS high
4
4
4
4
mA
VIH = VCC - 0.2 V (CMOS).
After 1 memory cycle,
RAS and CAS high
2
2
2
2
mA
ICC2
Standby current
ICC3
Average refresh
current (RAS-only
orCBR)
(see Note 3)
VCC =5.5V.
Minimum cycle,
RAS cycling, CAS high
240
220
200
180
mA
ICC4
Average page
current
(see Note 4)
VCC =5.5V,
tpc minimum,
RAS low, CAS cycling
140
120
100
90
mA
NOTES:
=
3. Measured with a maximum of one address change while RAS = VIL.
4. Measured with a maximum of one address change while CAS = VIH.
TEXAS
~
IN5rRUMENTS
5-86
POST OFFICE BOX 1443· HOUSTON, TEXAS 77001
TM497GAD8A
4 194 304·WORD BY 8·BIT DYNAMIC RAM MODULE
SMMS476-0ECEMBER 1992
capacitance over recommended ranges of supply voltage and operating free-air temperature,
f = 1 MHz
PARAMETER
MIN
MAX
UNIT
Ci~)
Input capacitance, address inputs
10
pF
Ci(RC)
Input capacitance, strobe inputs
14
pF
Ci(W)
Input capacitance, write-enable input
14
pF
Co
Output capacitance (pins 001-008)
7
pF
NOTE 5: VCC equal to 5 V ± 0.5 V and the bias on the Pin under test
IS
0 V.
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature
PARAMETER
'497GAD8A-60
MIN
MAX
'497GAD8A-70
MIN
MAX
'497GAD8A-80
MIN
MAX
'497GAD8A-l0
MIN
MAX
UNIT
tAA
Access time from column-address
30
35
40
45
ns
tCAC
Access time from CAS low
15
18
20
25
ns
tePA
Access time from column precharge
35
40
45
50
ns
tRAC
Access time from RAS low
60
70
80
100
ns
teLZ
CAS to output in low Z
0
0
0
0
tOH
Output disable; start of CAS high
3
3
3
3
toFF Output disable time after CAS high (see Note 6)
..
NOTE 6: tOFF IS specified when the output IS no longer driven.
0
15
0
18
0
20
0
ns
ns
25
ns
z
o-
~
==
a::
oLL
Z
W
(J
Z
~
c
«
TEXAS ~
INsrRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
5-87
TM497GAD8A
4 194 304-WORD BY 8-BIT DYNAMIC RAM MODULE
SMMS478-DECEMBER 1992
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
'497GAD8A-60
MIN
»
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~
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o
m
z
-
o"
:0
s:
~
o
z
'497GADBA-7O
MAX
MIN
MAX
'497GADBA-80
MIN
MAX
'497GADBA-10
MIN
MAX
UNIT
tRC
Random read or write cycle (see Note 7)
110
130
150
180
ns
tpc
Random read or write cycle time
(see Note 8)
40
45
50
55
ns
tRASP
Page-mode pulse duration, RAS low
60
100000
70
100000
80
100000
100
100000
ns
tRAS
Non-page-mode pulse duration, RAS low
60
10000
70
10000
80
10000
100
10000
ns
teAS
Pulse duration, CAS low
15
10000
18
10000
20
10000
25
10000
tcp
Pulse duration, CAS high
10
10
10
10
ns
tRP
Pulse duration, RAS high (precharge)
40
50
60
70
ns
twp
Write pulse duration
15
15
15
15
ns
tASC
Column-address setup time before CAS low
0
0
0
0
ns
tASR
Row-address setup time before RAS low
0
0
0
0
ns
tos
Data setup time
0
0
0
0
ns
tRCS
Read setup time before CAS low
0
0
0
0
ns
tCWL
W-Iow setup time before CAS high
15
18
20
25
ns
tRWL
W-Iow setup time before RAS high
15
18
20
25
ns
twcs
W-Iow setup time before CAS low
0
0
0
0
ns
twSR
W-high setup time (CAS-before-RAS
refresh only)
10
10
10
10
ns
tCAH
Column-addrllss hold time after CAS low
10
15
15
15
ns
tOH
Data hold time
10
15
15
15
ns
tRAH
Row-address hold time after RAS low
10
10
10
15
ns
tRCH
Read hold time after CAS high (see Note 9)
0
0
0
0
ns
tRRH
Read hold time after RAS high (see Note 9)
5
5
5
5
ns
twCH
Write hold time after CAS low
15
15
15
15
ns
twHR
W-high hold time (CAS-before-RAS refresh
only)
10
10
10
10
ns
Continued next page.
NOTES: 7. All cycle times assume IT = 5 ns.
8. To assure tpc min, tASC should be greater than or equal to tCp.
9. Either tRRH or tRCH must be satisfied for a read cycle.
TEXAS ~
IN5rRUMENTS
5-88
POST OFFICE BOX 1443· HOUSTON. TEXAS 77001
ns
TM497GAD8A
4 194 304·WORD BY 8·BIT DYNAMIC RAM MODULE
SMMS478-DECEMBER 1992
timing requirements over recommended ranges of supply voltage and operating free·air
temperature (concluded)
'497GAD8A-60
MIN
MAX
'497GAD8A-70
MIN
MAX
'497GAD8A-80
MIN
MAX
'497GAD8A-l0
MIN
MAX
UNIT
ICHR
Delay time, RAS low to CAS high
(CAS-before-RAS refresh only)
20
20
20
20
ns
ICRP
Delay lime, CAS high 10 RAS low
5
5
5
5
ns
ICSH
Delay lime, RAS low to CAS high
60
70
80
100
ns
tcSR
Delay lime, CAS low to RAS low
(CAS-before-RAS refresh only)
10
10
10
10
ns
tRAD
Delay time, RAS low to column-address
(see Note 10)
15
IRAl
Delay lime, column-address to RAS high
30
35
40
45
ns
ICAl
Delay time, column-address to CAS high
30
35
40
45
ns
tRCD
Delay lime, RAS low 10 CAS low
(see Note 10)
20
30
45
15
20
35
52
15
20
40
60
15
20
55
75
ns
ns
tRPC
Delay time, RAS high to CAS low
0
0
0
0
ns
IRSH
Delay lime, CAS low to RAS high
15
18
20
25
ns
tCPRH
RAS hold time from CAS precharge
35
tREF
Refresh lime interval
IT
Transition time
40
32
3
..
NOTE 10: The maximum value IS specified only to assure access time .
30
45
32
3
30
50
32
3
30
3
ns
32
ms
30
ns
z
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:!!
a:
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~
c
«
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443· HOUSTON. TEXAS 77001
5-89
TM497GAD8A
4194 304·WORD BY 8·BIT DYNAMIC RAM MODULE
SMMS478-DECEMBER 1992
device symbolization
o
I
----SS
VYMMT
000000000000000000000000000000
=
VY
Year Code
MM = Month Code
T = Assembly Site Code
-SS = Speed
NOTE: The location of the part number may vary.
TEXAS
~
INSIR.UMENTS
5-90
POST OFFICE BOX 1443· HOUSTON. TEXAS 77001
~
0
TM16100GBDa
16777216 BY a-BIT DYNAMIC RAM MODULE
SMMS608-DECEMBER 1992
•
Organization •.. 16777216 x 8
•
•
Single S-V Power Supply
•
•
BD SINGLE-IN-LiNE PACKAGEt
(TOP VIEW)
Utilizes Eight 16-Megabit Dynamic RAMs in
Plastic Small-Outline J-Lead Packages
(SOJs)
Long Refresh Period. •. 64 ms
(4096 Cycles)
All Inputs, Outputs, Clocks Fully TTL
Compatible
•
•
3-State Output
Performance Ranges:
ACCESS
TIME
tRAC
(MAX)
'16100GBD8-60 60 ns
'16100GBD8-70 70 ns
'16100GBD8-80 80 ns
'161 00GBD8-1 0 100 ns
•
•
•
ACCESS ACCESS
TIME
TIME
o
o
30-Pln Single In-Line Memory Module
(SIMM) for Use with Sockets
•
(BOTTOM VIEW)
READ
OR
tAA
tCAC
(MAX)
(MAX)
WRITE
CYCLE
(MIN)
30ns
35ns
40 ns
50 ns
15ns
18ns
20 ns
25 ns
110ns
130ns
150 ns
180 ns
Common CAS Control for Eight Common
Data-In and Data-Out Lines
VCC
CAS
DOl
AO
Al
D02
A2
A3
VSS
D03
A4
A5
D04
A6
A7
D05
A8
A9
Al0
D06
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
IN
VSS
D07
All
D08
NC
RAS
NC
NC
VCC
D
D
D
D
Low Power Dissipation
Operating Free-Air Temperature Range
O°C to 70°C
o
D
D
D
D
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
o
The SIMM is composed of eight TMS416100DZ,
16777216 x 1-bit dynamic RAMs in 24/28-lead
plastic small-outline J-Iead packages (SOJ),
mounted on a substrate with decoupling
capacitors.
vcc
vss
IN
Address Inputs
Column-Address Strobe
Data In/Data Out
No Connection
Row-Address Strobe
5-V Supply
Ground
Write Enable
The TM161 OOGBD8 is available in the BD double-sided, leadless module for use with sockets.
The TM161 OOGBD8 is characterized for operation from O°C to 70°C.
TEXAS
~
Copyright © 1992, Texas Instruments Incorporated
INSTRUMENTS
POST OFFICE BOX 1443' HOUSTON, TEXAS 77001
Z
W
«
PIN NOMENCLATURE
CAS
D01-D08
NC
RAS
a:
oLL
~
c
description
AD-All
~
:E
U
Z
t The package shown is for pinout reference only.
The TM16100GBD8 is a 128M (dynamic)
random-access memory module organized as
16 777 216 x 8 bits in a 30-pin leadless
single in-line memory module (SIMM).
z
o
5-91
TM16100GBDa
16 777 216 BY a-BIT DYNAMIC RAM MODULE
SMMS608-DECEMBER 1992
operation
The TM161 00GB08 operates as eight TMS4161 OOOZs connected as shown in the functional block diagram.
Refer to the TMS416100 data sheet for details of its operation. The common I/O feature of the TM16100GB08
dictates the use of early write cycles to prevent contention on 0 and Q ..
single in-line memory module and components
PC substrate: 1,27 mm (0.05 inch) nominal thickness; 0.005 inch/inch maximum warpage
Bypass capacitors: Multilayer ceramic
Contact area for socketable devices: Nickel plate and solder plate over copper
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INSTRUMENTS
5-92
POST OFFICE BOX 1443' HOUSTON. TEXAS 77001
TM16100GBD8
16 777 216 BY 8·BIT DYNAMIC RAM MODULE
SMMS608--DECEMBER 1992
functional block diagram
AO-A11
RAS
CAS
W
16M x 1
~ AO-A11
RAS
"-
"-
CAS
Q
"- W
DQ1
I
~
"-
~
"-
D
"-
l
DQS
16M x 1
AO-A11
RAS
CAS
I
~
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"- W
DQ2
I
D
"-
Ql
DQ6
16M x 1
AO-A11
~ RAS
"- CAS
"-
DQ3
DQ4
I
D
Ql
16M x 1
AO-A11
RAS
CAS
w
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o
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~
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AO-A11
~ RAS
"- CAS
"-
Ql
16M x 1
AO-A11
~ RAS
"- CAS
"- W
D
Qn
I
w
D
I
W
D
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AO-A11
RAS
CAS
DQ7
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~
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OQ1
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Q
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1
0
m
W
OQ5
l
"T1
OQ2
0
0
:s::
-~
0
"-
OQ3
Z
0
Qn
1
--E....
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RAS
CAS
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I
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16M x 1
AD-A11
RAS
CAS
"
" W
0
OQB
1
Qn
LE-,..,
CAS9
09
Q9
TEXAS ~
INSTRUMENTS
5-100
l
16M x 1
AD-A11
RAS
CAS
0
~
W
OQ4
W
W
OQ7
w
Q
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RAS
CAS
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CAS
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POST OFFICE BOX 1443· HOUSTON. TEXAS 77001
"-
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RAS
CAS
W
0
Qn
TM16100EBD9
16 777 216 BY 9-BIT DYNAMIC RAM MODULE
SMMS609--JANUARY 1993
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Voltage range on any pin (see Note 1) ................................................ - 1 V to 7 V
Voltage range on Vee (see Note 1) ................................................... - 1 V to 7 V
Short circuit output current ................................................................ 50 mA
Power dissipation: ......................................................................... 9 W
Operating free-air temperature range .................................................. O°C to 70°C
Storage temperature range ....................................................... - 55°C to 150°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions' is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values in this data sheet are with respect to VSS.
recommended operating conditions
MIN
NOM
MAX
Vee
Supply voltage
4.5
5
5.5
UNIT
V
VIH
High-level input voltage
2.4
6.5
V
Vil
low-level input voltage (see Note 2)
-1
0.8
V
TA
Operating free-air temperature
0
70
'e
NOTE 2: The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used in this data shellt for logic
~~~
electrical characteristics over full ranges of recommended operating conditions (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
VOH
High-level output
voltage
10H =-5mA
VOL
low-level output
voltage
10l= 4.2 mA
II
Input current
(leakage)
10
ICC1
ICC2
'16100EBD9-60
MIN
MAX
2.4
'16100EBD9-70
MIN
MAX
2.4
'16100EBD9-80
MIN
MAX
'161 00EBD9-1 0
MIN
MAX
2.4
2.4
UNIT
~
a::
oLL
Z
W
0.4
0.4
0.4
V
VI = 0 to 6.5 V, Vee = 5 V,
All other pins = 0 V to Vee
±10
±10
±10
±10
~
Output current
(leakage)
Vo = OVto VCC,
VCC = 5.5 V, CAS high
±10
±10
±10
±10
~
Read or write
cycle current
(see Note 3)
Minimum cycle, VCC = 5.5 V
810
720
630
540
mA
After 1 memory cycle, RAS
and CAS high,
VIH =2.4 V (TTl)
18
18
18
18
After 1 memory cycle, RAS
and CAS high,
VIH = VCC -0.2 V (CMOS)
9
9
9
9
mA
ICC3
Average refresh
current (RASonly or CBR)
(see Note 3)
Minimum cycle, VCC = 5.5 V,
RAS cycling, CAS high
(RAS-only), RAS low after
CAS low (CBR)
810
720
630
540
mA
ICC4
Average page
current
(see Note 4)
tpc = minimum, Vec = 5.5 V,
RAS low, CAS cycling
630
540
450
405
mA
NOTES:
ij
V
0.4
Standby
current
z
o
L:
3. Measured with a maximum of one address change while RAS = Vil.
4. Measured with a maximum of one address change while CAS = VIH.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443' HOUSTON, TEXAS 77001
5-101
o
Z
~
c
«
TM16100EBD9
16 777 216 BY 9-BIT DYNAMIC RAM MODULE
SMMS60IMJANUARY 1993
capacitance over recommended ranges of supply voltage and operating free-air temperature,
f = 1 MHz (see Note 5)
PARAMETER
MIN
MAX
UNIT
Ci(A)
Input capacitance, address inputs
Ci(O)
Input capacitance, data input (09 only)
Ci(RC)
Input capacitance, strobe inputs
63
pF
Ci(W)
Input capacitance, write-enable input
63
pF
Co(OO)
Output capacitance (001-008)
12
pF
Co
Output capacitance (09 only)
7
pF
NOTE 5: VCC equal to 5 V
±
45
pF
5
pF
0.5 V and the bias on pins under test is 0 V.
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature
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'16100EB09-60
PARAMETER
MIN
'16100EB09-70
MAX
MIN
MAX
'16100EB09-80
MIN
MAX
'16100EB09-10
MIN
MAX
UNIT
tAA
Access time from column-address
30
35
40
45
tCAC
Access time from CAS low
15
18
20
25
ns
tCPA
Access time from column precharge
35
40
45
50
ns
tRAC
Access time from RAS low
100
ns
tCLZ
CAS to output in low Z
0
0
0
0
ns
tOH
Output disable; from start of CAS high
3
3
3
3
ns
tOFF
Output disable time after CAS high
(see Note 5)
0
NOTE 6: toFF
IS
..
specified when the output
60
IS
15
70
0
18
no longer dnven .
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TEXAS
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INSTRUMENTS
5-102
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
80
0
20
0
25
ns
ns
TM16100EBD9
16 777 216 BY 9-BIT DYNAMIC RAM MODULE
SMMS609--JANUARY 1993
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
'16100EB09-60
MIN
MAX
110
'16100EB09-70
MIN
MAX
130
'16100EB09-80
MIN
MAX
150
'16100EB09-10
MIN
MAX
180
UNIT
tRC
Random read or write cycle (see Note 7)
tpc
Page-mode read or write cycle time
(see Note 8)
40
tRASP
Page-mode pulse duration, RAS low
60
100000
70
100000
80
100000
100
100000
ns
tRAS
Pulse duration, RAS low
60
10000
70
10000
80
10000
100
10000
ns
tCAS
Pulse duration, CAS low
15
10000
18
10000
20
10000
25
10000
ns
tcp
Pulse duration, CAS high
10
10
10
10
ns
tRP
Pulse duration, RAS high (precharge)
40
50
60
70
ns
twp
Write pulse duration
15
15
15
15
ns
tASC
Column-address setup time before CAS
low
0
0
0
0
ns
50
45
ns
55
ns
tASR
Row-address setup time before RAS low
0
0
0
0
ns
tos
Data setup time (see Note 9)
0
0
0
0
ns
tRCS
Read setup time before CAS low
0
0
0
0
ns
tCWL
W low setup time before CAS high
15
16
20
25
ns
tRWL
W low setup time before RAS high
15
16
20
25
ns
twcs
W-Iow setup time before CAS low
(Early write operation only)
0
0
0
0
ns
twSR
W high setup time (CAS-before-RAS
refresh only)
10
10
10
10
ns
tCAH
Column-address hold time after CAS low
10
15
15
15
ns
tDH
Data hold time
10
15
1.5
15
ns
tRAH
Row-address hold time after RAS low
10
10
10
10
ns
tRCH
Read hold time after CAS high
(see Note 10)
0
0
0
0
ns
tRRH
Read hold time after RAS high
(see Note 10)
5
5
5
5
ns
twCH
Write hold time after CAS low
(Early write operation only)
15
15
15
15
ns
twHR
W high hold time (CAS-before-RAS
refresh only)
10
10
10
10
ns
tcHR
~ time, RAS low to CAS high
(CAS-before-RAS refresh only)
20
20
20
20
ns
tCRP
Delay time, CAS high to RAS low
5
5
5
5
ns
Continued next page.
NOTES: 7. All cycle times assume IT = 5 ns.
6. To assure tpc min, tASC should be greater than or equal to tCp.
9. Referenced to the later of CAS or Win write operations.
10. Either tRRH or tRCH must be satisfied for a read cycle.
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
5-103
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~
INSTRUMENTS
5-108
POST OFFICE BOX 1443 • HOUSTON, TEXAS nOO1
functional block diagram (TM497BBK32 and TM893CBK32, side 1)
11
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~
RAS2
CJ\1 -
CAS1-
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4Mx4
A(}-'Al0
RAS
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CAS
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0015
001004
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J-=-
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0023
00240027
I
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OOJ
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NN
CAS
OE
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001004
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w....,
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:S::S:
4Mx4
A(}-'Al0
RAS
0019
~AS
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4Mx4
A(}-'Al0
RAS
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CAS
CAS
001004 "'0080011
CAS3-
~
~
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OE
4Mx4
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4Mx4
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ADVANCE INFORMATION
NOI~"WI::IO::lNI 3~N"Aa"
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(f)
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(f)
t;
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11
AO-A
RAS3
RA~
~, -
CAS1-
~
±:
~
4Mx4
AD-Al0
RAS
~
DQ1...-DaODQ4
DQ3
~
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Vi
"- CAS
"- OE
4Mx4
AO-Al0
RAS
"-
~
~
CAS
OE
DQ1...-DQS-DQ4
DQll
~
~
~
CAS3-
CAS2-
"-
4Mx4
AD-Al0
RAS
~
±
Vi
CAS
OE
DQ1DQ4 "'-DQ1&DQ19
.r-=-
<0
4Mx4
AD-Al0
RAS
~
(X) ~
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w .....
om
mm
00
,!'),!')
-1-1
:S:::S::
(X) ~
U) U)
Vi
"- CAS
"- OE
DQ1DQ4
-1-1
:S:::S::
w .....
om
mm
DQ24OQ27
I 00
en en
NN
(X) ~
~
(g
~"- Vi
"l
o
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i~id
5~
~rT1
i ~4t~
~
~
4Mx4
AD-Al0
RAS
~
~
CAS
OE
DQ1- ..... DQ4DQ4
DQ7
~
~
4Mx4
AD-Al0
RAS
OE
DQ1- ..... DQ12DQ4
DQ15
~
-=±
~ Vi
Vi
"CAS
"-
4Mx4
AD-Al0
RAS
"- CAS
~
"- OE
DQ1DQ4 ..... DQ2DDQ23
~
~
w .....
4Mx4
AD-Al0
RAS
(X) U)
(X) ~
cnw
Vi
00
(X) ~
CAS
OE
DQ1- ~
DQ4
DQ2S-DQ3l
I
~~
..
WW
NN
mm
::j::j
~~
zz
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00
:::u:::u
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:s:::s::
:s:::s::
00
cc
C:C:
II
mm
TM497BBK32, TM497BBK32S 4 194 304 BY 32-BIT DYNAMIC RAM MODULE
TM893CBK32, TM893CBK32S 8 388 608 BY 32-BIT DYNAMIC RAM MODULE
SMMS43:MJANUARY 1993
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage range on Vee (see Note 1) ............................................. - 1 V to 7 V
Supply voltage range on any pin (see Note 1) .......................................... - 1 V to 7 V
Short circuit output current ................................................................ 50 mA
Power dissipation (TM497BBK32) ............................................................ 8 W
(TM893CBK32) ........................................................... 16 W
Operating free·air temperature range .................................................. O°C to 70°C
Storage temperature range ....................................................... - 55°C to 125°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute·maximum·rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to VSS.
recommended operating conditions
UNIT
MIN
NOM
MAX
VCC
Supply voltage
4.5
5
5.5
VIH
High·level input voltage
2.4
6.5
V
VIL
Low·level input voltage (see Note 2)
-1
0.8
V
TA
Operating free·air temperature
0
70
·C
V
NOTE 2: The algebraic convenllOn, where the more negative (less positive) limit is designated as minimum, is used in this data sheet for logic
voltage levels only.
electrical characteristics over full ranges of recommended operating conditions (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
'497BBK32·60
MIN
MAX
'497BBK32·70
MIN
MAX
'497BBK32-80
MIN
MAX
UNIT
VOH
High·level output voltage
VOL
Low·level output voltage
IOL=4.2 mA
0.4
0.4
0.4
V
Input current (leakage)
VCC = 5.5 V, VI = 0 to 6.5 V,
All other pins = 0 V to VCC
±80
±80
± 80
~
10
Output current (leakage)
VCC = 5.5 V, Vo = 0 to Vcc,
CAS high
±10
±10
±10
~
ICCl
Read or write cycle current
(see Note 3)
VCC = 5.5 V, Minimum cycle
960
880
800
mA
16
16
16
mA
8
8
8
mA
II
ICC2
Standby current
2.4
10H =-5 mA
2.4
2.4
VIH = 2.4 V (TTL),
after 1 memory cycle,
RAS and CAS high
VIH = VCC - 0.2 V (CMOS),
after 1 memory cycle,
RAS and CAS high
V
ICC3
Average refresh current
(RAS·only or CSR) (see Note 3)
VCC = 5.5 V, Minimum cycle,
RAS cycling,
CAS high (RAS·only),
RAS low after CAS low (CSR)
960
880
800
mA
ICC4
Average page current (see Note 4)
VCC = 5.5 V, tpc = Minimum,
RAS low, CAS cycling
560
480
400
mA
NOTES:
3. Measured with a maximum of one address change while RAS = VIL.
4. Measured with a maximum of one address change while CAS = VIH.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
5·111
z
o
~
:E
a:
o
LL
Z
W
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«
TM497BBK32, TM497BBK32S 4 194 304 BY 32·BIT DYNAMIC RAM MODULE
TM893CBK32, TM893CBK32S 8388 608 BY 32·BIT DYNAMIC RAM MODULE
SMMS433-JANUARY 1993
electrical characteristics over full ranges of recommended operating conditions (unless otherwise
noted)
PARAMETER
VOH
High-level output voltage
IOH=-5mA
VOL
Low-level output voltage
10L= 4.2 mA
II
o
z
MIN
MAX
2.4
'S93CBK32-70
MIN
MAX
2.4
'S93CBK32-80
MIN
MAX
2.4
UNIT
V
0.4
0.4
Input current (leakage)
VCC = 5.5 V, VI = 0 to 6.5 V,
All other pins = 0 V to VCC
± 160
± 160
± 160
ItA
10
Output current (leakage)
VCC = 5.5 V, Vo = 0 to VCC,
CAS high
±20
±20
±20
ItA
ICC1
Read or write cycle current
(see Note 3)
VCC = 5.5 V, Minimum cycle
976
896
816
mA
VIH = 2.4 V (TTL),
after 1 memory cycle,
RAS and CAS high
32
32
32
mA
VIH = VCC - 0.2 V (CMOS),
after 1 memory cycle,
RAS and CAS high
16
16
16
mA
»
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~
'S93CBK32-60
0.4
ICC2
~
z
o
m
z"T1
TEST CONDITIONS
Standby current
V
ICC3
Average refresh current
(RAS-only or CBR)
(all 4 RAS active)
(see Note 3)
VCC = 5.5 V, Minimum cycle,
RAS cycling,
CAS high (RAS-only),
RAS low after CAS low (CBR)
1920
1760
1600
mA
ICC4
Average page current
(see NoteA)
VCC = 5.5 V, tpc = Minimum,
RAS low, CAS cycling
576
496
416
mA
NOTES:
3. Measured with a maximum of one address change while RAS = VIL.
4. Measured with a maximum of one address change while CAS = VIH.
capacitance over recommended ranges of supply voltage and operating free-air temperature,
f = 1 MHz (see Note 5)
'497BBK32
PARAMETER
MIN
TYP
'893CBK32
MAX
MIN
TYP
MAX
UNIT
Ci(AI
Input capacitance, address inputs
40
80
pF
CirRI
Input capacitance, RAS inputs
28
28
pF
CiiCl
Input capacitance, CAS inputs
14
28
pF
Ci(Wj
Input capacitance, write-enable input
56
112
pF
Co(DO)
Output capacitance on DO pins
7
14
pF
NOTE 5:. VCC equal to 5 V ± 0.5 V and the bias on pins under test is 0 V.
TEXAS
~
INSTRUMENTS
5-112
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
TM497BBK32, TM497BBK32S 4194 304 BY 32-BIT DYNAMIC RAM MODULE
TM893CBK32, TM893CBK32S 8 388 608 BY 32-BIT DYNAMIC RAM MODULE
SMMS433-JANUARY 1993
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature
'497BBK32-60
'893CBK32-60
PARAMETER
MIN
'497BBK32-70
'893CBK32-70
MAX
MIN
MAX
'497BBK32-80
'893CBK32-80
MIN
UNIT
MAX
tM
Access time from column-address
30
35
40
ns
tCAC
Access time from CAS low
15
18
20
ns
tRAC
Access time from RAS low
60
70
80
ns
tePA
Access time from column precharge
35
40
45
tCLZ
CAS to output in low Z
0
tOH
Output disable from start of CAS high
3
tOFF
Output disable time after CAS high (see Note 6)
0
NOTE 6: toFF
IS
..
specified when the output
IS
0
0
3
15
3
0
18
0
ns
ns
ns
20
ns
no longer driven.
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
'497BBK32-60
'893CBK32-60
MIN
tRC
Random read or write cycle (see Note 7)
tpc
Page-mode read or write cycle time (see Note 8)
MAX
'497BBK32-70
'893CBK32-70
MIN
MAX
'497BBK32-80
'893CBK32-80
MIN
UNIT
MAX
110
130
150
ns
40
45
50
ns
tRASP
Page-mode pulse duration, RAS low
60
100000
70
100000
80
100000
ns
tRAS
Non-page-mode pulse duration, RAS low
60
10 000
70
10000
80
10000
ns
teAS
Pulse duration, CAS low
15
10 000
18
10000
20
10 000
ns
tep
Pulse duration, CAS high
10
10
10
ns
tRP
Pulse duration, RAS high (precharge)
40
50
60
ns
twp
Write pulse duration
15
15
15
ns
tASC
Column-address setup time before CAS low
0
0
0
ns
tASR
Row-address setup time before RAS low
0
0
0
ns
tDS
Data setup time
0
0
a
ns
tRCS
Read setup time before CAS low
0
0
0
ns
tCWL
W low setup time before CAS high
15
18
20
ns
tRWL
W low setup time before RAS high
15
18
20
ns
twcs
W low setup time before CAS low
twSR
W high setup time (CAS-before-RAS refresh only)
NOTES:
a
a
0
ns
10
10
10
ns
7. All cycles assume IT = 5 ns.
8. To assure tpc min, tASC should be greater than or equal to tCp.
TEXAS
~
lNSfRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
5-113
z
o
~
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a:
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LL
Z
W
o
Z
c~
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-z
'T1
o
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~
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MAX
'496TBM40-70
'892VBM40-70
MIN
MAX
'496TBM40-80
'892VBM40-80
MIN
UNIT
MAX
tRCH
Read hold time after CAS high (see Note 12)
0
0
0
ns
tRRH
Read hold time after RAS high (see Note 12)
5
5
5
ns
twCH
Write hold time after CAS low
(Early write operation only)
15
15
15
ns
twHR
W-high hold time (CAS-before-RAS refresh only)
10
10
10
ns
tAWD
Delay time, column address to W low
(Read-write operation only)
55
63
70
ns
tCHR
Delay time, RAS low to CAS high
(CAS-before-RAS refresh only)
20
20
20
ns
tCRP
Delay time, CAS high to RAS low
5
5
5
ns
tcSH
Delay time, RAS low to CAS high
60
70
80
ns
tCSR
Delay time, CAS low to RAS low
(CAS-before-RAS refresh only)
10
10
10
ns
tCWD
Delay time, CAS low to W low
(Read-write operation only)
40
46
50
ns
toEH
OE command hold time
15
18
20
ns
tOED
OE to data delay
15
18
20
ns
tROH
RAS hold time referenced to OE
10
10
10
ns
tRAD
Delay time, RAS low to column-address
(see Note 13)
15
tRAl
Delay time, column-address to RAS high
30
35
40
ns
tCAl
Delay time, column-address to CAS high
30
35
40
ns
tRCD
Delay time, RAS low to CAS low
(see Note 13)
20
tRPC
Delay time, RAS high to CAS low
tRSH
Delay time, CAS low to RAS high
tRWD
30
45
15
20
35
52
15
20
60
ns
ns
0
0
0
ns
15
18
20
ns
Delay time, RAS low to W low
(Read-write operation only)
85
98
110
ns
ns
tCPRH
RAS hold time from CAS precharge
,35
40
45
tcpw
Delay time, W from CAS precharge
60
68
75
tREF
Refresh time interval
IT
Transition time
64
3
30
NOTES: 12. Either tRRH or tRCH must be satisfied for a read cycle.
13. The maximum value is specified only to guarantee access time.
TEXAS •
INSTRUMENTS
5-134
40
POST OFFICE BOX 1443· HOUSTON, TEXAS nOOl
64
3
30
3
ns
64
ms
30
ns
TM496TBM40, TM496TBM40S 4 194 304 BY 40·BIT DYNAMIC RAM MODULE
TM892VBM40, TM892VBM40S 8 388 608 BY 40·BIT DYNAMIC RAM MODULE
SMMS440A-OECEMBER 1992--REVISED JANUARY 1993
device symbolization (TM496TBM40 Illustrated)
00000
0000000
TM496TBM40
-SS
VY
MM
T
- SS
VYMMT
'" Vear Code
'" Month Code
'" Assembly Site Code
= Speed Code
NOTE: Location of symbolization may vary.
z
o-
t;:
:!:
a:
oLL
Z
W
o
Z
~
c
«
TEXAS
~
INSIRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS nOOl
5-135
TM496TBM40, TM496TBM40S 4 194 304 BY 40·BIT DYNAMIC RAM MODULE
TM892VBM40, TM892VBM40S 8 388 608 BY 40·BIT DYNAMIC RAM MODULE
SMMS440A-DECEMBER 1992-REVISED JANUARY 1993
TEXAS ~
INsrRUMENTS
5-136
POST OFFICE BOX 1443· HOUSTON, TEXAS 77001
TM124TBK40, TM124TBK40S 1048576 BY 40·BIT DYNAMIC RAM MODULE
TM248VBK40, TM248VBK40S 2 097 152 BY 40·BIT DYNAMIC RAM MODULE
SMMS14ChJANUARY 1993
•
•
•
Organization
TM124TBK40 ••. 1 048576 x 40
TM248VBK40 ... 2 097 152 x 40
Single 5·V Power Supply
72·Pln Single In·Llne Memory Module
(SIMM) for Use With Sockets
•
TM124TBK40 - Utilizes Ten 4·Megabit
Dynamic RAMs in Plastic Small·Outline
J·Lead (SOJ) Packages
•
TM248VBK40 - Utilizes Twenty 4·Megablt
Dynamic RAMs In Plastic Small·Outline
J·Lead Packages (SOJ)
Long Refresh Period .•• 16 ms
(1024 Cycles)
All Inputs, Outputs, Clocks Fully TTL
Compatible
•
•
•
Low Power Dissipation
•
Vee Tolerance:l: 10%
•
Performance Ranges:
ACCESS
TIME
ACCESS ACCESS READ
TIME
TIME
OR
tRAC
'124TBK40-60
'124TBK40-70
'124TBK40-80
'248VBK40-60
'248VBK40-70
'248VBK40-80
•
•
•
(MAX)
WRITE
CYCLE
(MIN)
60
70
80
60
70
80
110
130
150
110
130
150
ns
ns
ns
ns
ns
ns
40 ns
20 ns
ns
ns
ns
ns
ns
ns
Operating Free·Alr Temperature
Range ... O°C to 70°C
Gold·Tabbed Version Avallable: t
TM124TBK40
TM248VBK40
z
o
Tin·Lead (Solder) Tabbed Version
Available:
TM124TBK40S
TM248VBK40S
-
!;:
~
description
II:
TM124TBK40
The TM124TBK40 is a 40M dynamic random-access memory organized as 1 048576 x 40 in a 72-pin lead less
single in-line memory module (SIMM)_ The SIMM is composed of ten TMS44400DJ, 1 048 576 x 4-bit dynamic
RAMs, each in a 300-mil20/26-lead plastic small-outline J-Iead package (SOJ) mounted on a substrate together
with decoupling capacitors, Each TMS44400DJ is described in the TMS44400 data sheet.
The TM124TBK40 can be used in systems with fewer than 40 data bits. In those applications, it is recommended
that any unused DO pins be connected to either V 55 orV cc through a series resistor with a typical value between
5 kg and 10 kg.
The TM124TBK40 is rated for operation from O°C to 70°C. This device features RAS access times of
60 ns, 70 ns, and 80 ns.
TM248VBK40
The TM248VBK40 is a 80M dynamic random-access memory organized as 2 097 152 x 40 in a 72-pin single
in-line memory module (SIMM). The SIMM is composed of twenty TMS44400DJ,1 048576 x 4-bit dynamic
RAMs, each in a 300-mil 20/26-lead plastic small-outline J-Iead (SOJ) package mounted on a substrate with
decoupling capacitors. Each TMS44400DJ is described in the TMS44400 data sheet.
The TM248VBK40 can be used in systems with fewer than 40 data bits. In those applications, it is recommended
that any unused DO pins be connected to either V 55 orVcc through a series resistor with a typical value between
5 kg and 10 kg.
The TM248VTBK40 is available in the double-sided BK lead less module for use with sockets.
The TM248VTBK40 is rated for operation from O°C to 70°C. This device features RAS access times of
60 ns, 70 ns, and 80 ns.
Part numbers in this data sheet refer only to the gold-tabbed version; the information applies to both gold-tabbed and solder-tabbed
versions.
TEXAS
~
Copyright © 1993, Texas Instruments Incorporated
INSTRUMENTS
POST OFFICE BOX 1443· HOUSTON, TEXAS 77001
Z
W
o
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~
c
The TM124TBK40 is available in the single-sided BK lead less module for use with sockets.
t
oLL
5-137
«
TM124TBK40, TM124TBK40S 1 048576 BY 40·BIT DYNAMIC RAM MODULE
TM248VBK40, TM248VBK40S 2 097152 BY 40·BIT DYNAMIC RAM MODULE
SMMS14O-JANUARY 1993
operation
TM124TBK40
The TM124TBK40 operates as ten TMS44400DJs connected as shown in the functional block diagram. Refer
to the TMS44400 data sheet for details of operation.
TM248VBK40
The TM248VBK40 operates as twenty TMS44400DJs connected as shown in the functional block diagram.
Refer to the TMS44400 data sheet for details of operation.
single In·llne memory module and components
PC substrate: 1, 27 mm (0.05 inch) nominal thickness on contact area
Bypass capacitors: Multilayer ceramic
Contact area for TM 124TBK40 and TM248VBK40: Nickel plate and gold plate over copper.
Contact area for TM124TBK40S and TM248VBK40S: Nickel plate and tin-lead over copper.
»
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~
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-n
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:s:
-o~
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. TEXAS ~
INSTRUMENTS
5-138
POST OFFICE BOX 1443 • HOUSTON, TEXAS nOO1
TM124TBK40, TM124TBK40S 1048576 BY 40-BIT DYNAMIC RAM MODULE
TM248VBK40, TM248VBK40S 2 097 152 BY 40-BIT DYNAMIC RAM MODULE
SMMS140-JANUARY 1993
BK SINGLE-IN-LiNE PACKAGEt
TM124TBK40
BK SINGLE IN-LINE PACKAGEt
TM248VBK40
BK SINGLE IN-LINE PACKAGEt
(TOP VIEW)
(SIDE VIEW)
(SIDE VIEW)
c:::::l
c:::::l
c:::::l
c:::::l
c:::::l
c:::::l
DOS c:::::l
006 c:::::l
007 c:::::l
VCC c:::::l
NC c:::::l
AO c:::::l
A1 c:::::l
A2
c:::::l
A3 c:::::l
A4 c:::::l
A5 c:::::l
A6 c:::::l
OE c:::::l
008 c:::::l
009 c:::::l
0010 c:::::l
0011 c:::::l
0012 c:::::l
0013 c:::::l
D014 c:::::l
0015 c:::::l
A7 c:::::l
0016 c:::::l
VCC c:::::l
A8 c:::::l
A9 c:::::l
NC c:::::l
NC c:::::l
DQ17
c:::::l
0018 c:::::l
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
c:::::l
c:::::l
c:::::l
c:::::l
c:::::l
c:::::l
c:::::l
c:::::l
c:::::l
c:::::l
c:::::l
c:::::l
c:::::l
c:::::l
c:::::l
c:::::l
c:::::l
c:::::l
c:::::l
c:::::l
c:::::l
c:::::l
c:::::l
c:::::l
c:::::l
c:::::l
c:::::l
c:::::l
c:::::l
c:::::l
c:::::l
c:::::l
c:::::l
c:::::l
c:::::l
c:::::l
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
Vss
000
001
002
003
004
0019
0020
VSS
CASO
A10
~
CAS1
RASO
RAS1
0021
Vi
x40{VSS)
0022
0023
D024
D025
0026
0027
0028
0029
0030
0031
VCC
0032
0033
0034
0035
0036
0037
0038
PD1
PD2
PD3
P04
0039
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
z
o-
~
~
a:
oL1.
Z
W
o
PIN NOMENCLATURE
AO--A9
A10,A11
CASO, CAS1
RASO, RAS1
DOO--D039
W
NC
VCC
VSS
PD1-PD4
OE
Address Inputs
NC - Reserved for 4M/8M x 40
Column-Address Strobe
Row-Address Strobe
Data In/Data Out
Write Enable
No External Connection
5-V Supply
Ground
Presence Detects
Output Enable
Z
~
c
«
PRESENCE DETECT
SIGNAL
(PIN)
TM124TBK40
TM248VBK40
PD1
(67)
PD2
(68)
PD3
(69)
PD4
(70)
80 ns
VSS
VSS
VSS
VSS
70 ns
VSS
VSS
NC
VSS
60 ns
VSS
VSS
VSS
NC
80 ns
NC
NC
VSS
VSS
70 ns
NC
NC
NC
VSS
60 ns
NC
NC
VSS
NC
t The packages shown here are for pinout reference only and are not drawn to scale.
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443· HOUSTON, TEXAS 77001
5-139
TM124TBK40, TM124TBK40S 1048576 BY 40·BIT DYNAMIC RAM MODULE
TM248VBK40, TM248VBK40S 2 097152 BY 40·BIT DYNAMIC RAM MODULE
SMMS14O-JANUARY 1993
functional block diagram (TM124TBK40 and TM248VBK40, side 1)
AO-A9
RASO
CASO
W
OE
~
~~
'"
f'..
1M x4
AO-A9
RAS
CAS
W
001004
OE
~
~~
-DOD
-001
-002
-003
'"
f'..
1M x4
~ AO-A9
RAS
~~
f'..
f'..
l>
c
~
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-"T1z
CAS
W
OE
~~
o
f'..
CAS
W
'"
OE
~~
-004
-005
001- - 0 0 6
004 - 0 0 7
~
~~
:0
:s::
~
oz
'"
J'.,
.J'.,
'"
W
OE
W
'"
OE
~~
001004
W
'"
OE
~
~~
-0012
-0013
-0014
-0015
0024
0025
0026
0027
-
0028
0029
0030
0031
001- 004 -
-
0032
0033
0034
0035
1M x 4
AO-A9
RAS
CAS
-'" W
001- f'.. OE
004 -
0036
0037
0038
0039
~
~
-0016
-0017
001- -0018
004 -0019
TEXAS
CAS
f'..
1M x4
AO-A9
RAS
CAS
f'.. W
001..1'- OE
004
~
INSTRUMENTS
5-140
.1'-
-
-
1M x4
1M x4
~ AO-A9
RAS
~ CAS
CAS
~ AO-A9
RAS
-008
-009
001- -0010
004 -0011
1M x4
AO--A9
RAS
CAS
001W
OE
004
t - - 0020
t - - 0021
t - - 0022
t - - 0023
1M x4
~ AO-A9
RAS
1M x4
~ AO-A9
RAS
1M x4
AO-A9
RAS
CAS
DOlW
OE
004
POST OFFICE BOX 1443· HOUSTON, TEXAS 77001
TM124TBK40, TM124TBK40S 1048576 BY 40·BIT DYNAMIC RAM MODULE
TM248VBK40, TM248VBK40S 2 097152 BY 40·BIT DYNAMIC RAM MODULE
SMMS14O-JANUARY 1993
functional block diagram (TM248VBK40, side 2)
AO-A9
RASl
CASl
W
OE
J-
1M x4
AO-A9
RAS
"- CAS
r-.... W
OQ1"- OE
004
~
1M x4
~ AO-A9
RAS
I-~
f--OOO
f - - 001
f--OQ2
f--003
r-.... W
"- OE
1M x 4
~ AO-A9
RAS
I-~
CAS
r-.... W
"- OE
J-
~
"
~
J~
"
1M x 4
AO-A9
RAS
CAS
W
001"- OE
004
~
"
004
-
0020
0021
OQ22
0023
1M x4
I-~
CAS
r-.... W
"- OE
-
001- 004 -
f--OOB
f--009
f--0010
f - - 0011
1M x 4
AO-A9
I-~ RAS
CAS
r-.... W
001.1'-, OE
004
f--0012
f--0013
f--0014
f--0015
1M x 4
AO-A9
I-~ RAS
CAS
r-.... W
001- "- OE
004 -
~
-
0024
OQ25
OQ26
0027
Z
-
0
tc
:E
0028
0029
0030
0031
a:
0
LL
1M x 4
AO-A9
RAS
CAS
"- W
001004
OE
~
OQ1- -
~ AO-A9
RAS
f--004
f--005
001- f--006
004 f--007
1M x 4
AO-A9
RAS
"- CAS
"- W
001OE
004
CAS
~
1M x 4
AO-A9
RAS
CAS
"- W
001"- OE
004
~
~
f - - 0016
f--0017
f - - 0018
f - - 0019'
TEXAS
-
Z
W
0032
0033
0034
0035
(J
Z
~
C
«
0036
0037
0038
0039
~
INsrRUMENTS
POST OFFICE BOX 1443· HOUSTON, TEXAS 77001
5-141
TM124TBK40, TM124TBK40S 1 048576 BY 40-BIT DYNAMIC RAM MODULE
TM248VBK40, TM248VBK40S 2 097152 BY 40-BIT DYNAMIC RAM MODULE
SMMS14o-JANUARY 1993
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage range on any pin (see Note 1) .......................................... - 1 V to 7 V
Voltage range on Vee (see Note 1) ................................................... - 1 V to 7 V
Short circuit output current ................................................................ 50 mA
Power dissipation (TM124TBK40) ........................................................... 10 W
(TM248VBK40) ........................................................... 20 W
Operating free-air temperature range .................................................. O°C to 70°C
Storage temperature range ............... ;....................................... - 55°C to 125°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. This is a stress rating only, and
functional operation of the device at these or any other conditions beyond those indicated in the "recommended operating conditions" section of
this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to VSS.
recommended operating conditions
»
c
~
z
o
m
z
-
MIN
NOM
MAX
VCC
Supply voltage
4.5
5
5.5
VIH
High-level input voltage
2.4
6.5
V
VIL
Low-level input voltage (see Note 2)
-1
0.8
V
TA
Operating free-air temperature
70
'c
..
..
In
V
this data sheet for logiC
capacitance over recommended supply voltage range and operating free-air temperature range,
f = 1 MHz (see Note 3)
'TI
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0
..
NOTE 2: The algebraic convention, where the more negative (less positive) limit IS deSignated as minimUm, IS used
voltage levels only.
UNIT
'124TBK40
'248VBK40
MIN
MIN
MAX
MAX
UNIT
Ci(A)
Input capacitllnce, address inuts
50
100
pF
Ci(OE)
Input capacitance, OE input
70
140
pF
Ci(W)
Input capacitance, WE input
70
140
pF
Ci(RC)
Input capacitance, RAS, CAS inputs
70
70
pF
Co(DO)
Output capacitance, DO pins
7
14
pF
NOTE 3: VCC equal to 5 V ± 0.5 V and the bias on pins under test is 0 V.
TEXAS ~
INsrRUMENTS
5-142
POST OFFICE BOX 1443 • HOUSTON. TEXAS nOO1
TM124TBK40, TM124TBK40S 1048516 BY 40·BIT DYNAMIC RAM MODULE
TM248VBK40, TM248VBK40S 2 091152 BY 40·BIT DYNAMIC RAM MODULE
SMMS14lhJANUARV 1993
electrical characteristics over full ranges of recommended operating conditions (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
VOH
High-level output voltage
IOH =-5 mA
VOL
Low-level output voltage
IOL=4.2 mA
II
'124TBK40-60
MIN
MAX
'124TBK40-70
MIN
MAX
2.4
2.4
'124TBK40-80
MIN
MAX
2.4
UNIT
V
0.4
0.4
0.4
Input current (leakage)
VCC = 5.5 V, VI = 0 to 6.5 V,
All other pins = 0 V to VCC
:t 100
:t 100
:t 100
!IA
10
Output current (leakage)
VCC = 5.5 V, Vo = 0 to VCC.
CAS high
:t10
:t10
:t10
!IA
ICC1
Read or write cycle current
(see Note 4)
VCC = 5.5 V. Minimum cycle
1050
900
800
mA
After 1 memory cycle, RAS and
CAS high, VIH = 2.4 V (TTL)
20
20
20
mA
After 1 memory cycle. RAS and
CAS high, VIH = VCC - 0.2 V
(CMOS)
10
10
10
mA
ICC2
Standby current
V
z
ICC3
Average refresh current
(RAS-only or CBR)
(see Note 4)
VCC = 5.5 V, Minimum cycle,
RAS cycling, CAS high
(RAS-only), RAS low after
CAS low (CBR)
1050
900
800
mA
ICC4
Average page current
(see Note 5)
VCC = 5.5 V. tpc = Minimum.
RAS low. CAS cycling
900
800
700
mA
NOTES:
o
~
:!:
a:
oLL
4. Measured with a ma>(lmum of one address change while RAS = VIL.
5. Measured with a maximum of one address change while CAS = VIH.
Z
W
o
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~
c
0
A 32767
A'V
A'V
A'V
A'V
A'V
A'V
A'V
A'V
11
12
13
15
16
17
18
19
DOO
D01
D02
D03
D04
D05
D06
D07
14
20
G 22
EN
OTPPROM
32768x8
0
L..
"
[PWRDWNI
&
I
EN
t These symbols are in accordance with ANSI/IEEE Std 91-1984 and lEe Publication 617-12.
Pin numbers shown are for J and N packages.
absolute maximum ratings over operating free·air temperature range (unless otherwise noted}:!:
Supply voltage range, Vee (see Note 1) .............................................. -0.6 V to 7 V
Supply voltage range, Vpp ......................................................... -0.6 V to 14 V
Input voltage range (see Note 1): All inputs except A9 ............................ -0.6 V to Vee + 1 V
A9 ............................................... -0.6 V to 13.5 V
Output voltage range (see Note 1) ............................................. -0.6 V to Vee + 1 V
Operating free-air temperature range (,27C256-__JL and JL4, '27PC256-__ NL, NL4, FML,
and FML4) ...................................... 0° C to 70°C
Operating free-air temperature range ('27C256-__JE and JE4, '27PC256-__ NE, NE4, FME,
and FME4) .................................... - 40° C to 85°C
Storage temperature range ....................................................... -65°C to 150°C
:t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to GND.
TEXAS
~
INSTRUMENTS
6-8
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
TMS27C256262 144·BIT UV ERASABLE PROGRAMMABLE READ·ONLY MEMORY
TMS27PC256262 144·BIT PROGRAMMABLE READ·ONLY MEMORY
SMLS256F-SEPTEMBER 1984-REVISED JANUARY 1993
recommended operating conditions
Read mode (see Note 2)
VCC
Supply voltage
Vpp
Supply voltage
VIH
High-level dc input voltage
VIL
Low-level dc input voltage
TA
Operating free-air temperature
TA
Operating free-air temperature
NOTES:
SNAPI Pulse programming algorithm
Read mode
MIN
NOM
MAX
4.5
5
5.5
6.25
6.5
6.75
VCC-0.6
SNAPI Pulse programming algorithm
13
2
CMOS
V
VCC+0.6
12.75
TIL
UNIT
13.25
VCC+l
VCC-0.2
V
V
VCC+l
TIL
- 0.5
0.8
CMOS
-0.5
0.2
'27C256-__JL, JL4
'27PC256-__NL, NL4,
FML, FML4
0
70
'c
'27C256-__JE, JE4
'27PC256-__ NE, NE4,
FME, FME4
-40
85
'c
V
2. VCC must beapphed before oratthesametlmeas Vppand removed afieroratthe sametlmeas Vpp. The device must not bemserted
into or removed from the board when Vpp or VCC is applied.
electrical characteristics over full ranges of operating conditions
PARAMETER
VOH
High-level dc output voltage
VOL
Low-level dc output voltage
TEST CONDITIONS
10H = - 20
TYpt
MIN
MAX
3.5
10H =-2.5 mA
fAA
V
VCC-O.l
10L= 2.1 mA
0.4
10L = 20 flA
0.1
II
Input current (leakage)
VI'= 0 to 5.5 V
±1
10
Output current (leakage)
Vo =OtoVCC
±1
IpPl
Vpp supply current
Vpp = VCC = 5.5 V
IpP2
Vpp supply current (during program pulse)
Vpp = 13V
ICCI
V CC supply current (standby)
ITIL-input level
I CMOS-input level
V
fAA
fAA
1
10
flA
35
50
mA
VCC = 5.5 V, E = VIH
250
500
VCC = 5.5 V, E = VCC
100
250
15
30
VCC = 5.5 V, E = VIL,
leycle = minimum cycle time,
outputs open
ICC2 VCC supply current (active)
UNIT
flA
mA
tTYPlcal values are at TA = 25'C and nom mal voltages.
capacitance over recommended
temperature, f = 1 MHz:t:
ranges
PARAMETER
of
supply
voltage
TEST CONDITIONS
and
operating
MIN
TYpt
free-air
MAX
UNIT
Ci
Input capacitance
VI = 0, f = 1 MHz
6
10
pF
Co
Output capacitance
Vo = 0, f = 1 MHz
10
14
pF
tTypical values are at TA = 25'C and nominal voltages.
Capacitance measurements are made on a sample basis only.
*
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443· HOUSTON, TEXAS 77001
6-9
TMS27C256 262144-BITUV ERASABLE PROGRAMMABLE READ-ONLY MEMORY
TMS27PC256 262144-BIT PROGRAMMABLE READ-ONLY MEMORY
SMLS256F-SEPTEMBER 1984-REVISED JANUARY 1993
switching characteristics over full ranges of recommended operating conditions (see Notes 3
and 4)
TEST CONDITIONS
(SEE NOTES 3 AND 4)
PARAMETER
'27C256-10
'27PC256-10
MIN
'27C256-12
'27PC256-12
MAX
MIN
MAX
'27C256-15
'27PC256-15
MIN
UNIT
MAX
talA)
Access time from address
100
120
150
talE)
Access time from chip enable
100
120
150
ns
len (G)
Output enable time from G
55
55
75
ns
!dis
Output disable time from G or E,
whichever occurs firstt
60
ns
tv (A)
Output data valid time after change of
address, E, or G, whichever occurs firstt
=
CL 100 pF,
1 Series 74 TIL Load,
Input tr " 20 ns,
Input tf " 20 ns
Access time from address
talE)
Access time from chip enable
len (G)
Output enable time from G
!dis
Output disable time from G or E,
whichever occurs firstt
tv(A)
Output data valid time after change of
address, E, or G, whichever occurs firstt
CL = 100 pF,
1 Series 74 TIL Load,
Input tr " 20 ns,
Input tf " 20 ns
0
45
0
0
'27C256-17
'27PC256-17
MIN
talA)
45
0
TEST CONDITIONS
(SEE NOTES 3 AND 4)
PARAMETER
0
0
'27C256-20
'27PC256-20
MAX
0
ns
MIN
MAX
ns
'27C256-25
'27PC256-25
MIN
UNIT
MAX
170
200
250
ns
170
200
250
ns
75
75
100
ns
60
ns
60
0
0
60
0
0
0
ns
tValue calculated from 0.5 V delta to measured level. This parameter is only sampled and not 100% tested.
switching characteristics for programming: Vee = 6.50 V and Vpp = 13 V (SNAP! Pulse), TA = 25°C
(see Note 3)
PARAMETER
!dis(G)
Output disable time from G
len (G)
Output enable time from G
NOTES:
MIN
0
MAX
UNIT
130
ns
150
ns
3. For all switching characteristics the input pulse levels are 0.4 V to 2.4 V. Timing measurements are made at 2 V for logic high and
O.S V for logic lOw). (Reference page 9.)
4. Common test conditions apply for the tdis except during programming.
TEXAS . "
INSIRUMENTS
6-10
NOM
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
TMS27C256 262 144·BIT UV ERASABLE PROGRAMMABLE READ·ONLY MEMORY
TMS27PC256262 144·BIT PROGRAMMABLE READ·ONLY MEMORY
SMLS256F-SEPTEMBER 1984-REVISED JANUARY 1993
recommended timing requirements for programming: Vcc
TA = 25°C (see Note 3)
= 6.5
V and Vpp
MIN
NOM
MAX
95
100
105
= 13
UNIT
tw(IPGM)
Initial program pulse duration
tsu(A)
Address setup time
2
tJS
tsu(G)
G setup time
2
I-'S
tsu(E)
E setup time
2
I-'S
lsu(O)
Data setup time
2
I-'S
tsu(VPP)
Vpp setup time
2
tJS
tsu(VCC)
VCC setup time
2
I-'S
th(A)
Address hold time
0
I-'S
th(D)
Data hold time
2
tJS
NOTE 3:
V,
I-'s
For all sWitching characteristics the Input pulse levels are 0.4 V to 2.4 V. Timing measurements are made at 2 V for logic high and
0.8 V for logic lOw). (Reference page 9.)
PARAMETER MEASUREMENT INFORMATION
2.08 V
Output
Under Test
~
. r
RL=800Q
CL=100pF
Figure 2. AC Testing Output Load Circuit
AC testing input/output wave forms
2.4V---""v.
O.!~X,,"____
______I\- ~.~ v
0.4 V
A.C. testing inputs are driven at 2.4 V for logic high and 0.4 V for logic low. Timing measurements are made at
2 V for logic high and 0.8 V for logic low for both inputs and outputs.
TEXAS
~
INsrRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
6·11
TMS27C256262144·BIT UV ERASABLE PROGRAMMABLE READ·ONLY MEMORY
TMS27PC256 262 144·BIT PROGRAMMABLE READ·ONLY MEMORY
SMLS256F-SEPTEMBER 1984-REVISED JANUARY 1993
PARAMETER MEASUREMENT INFORMATION
AO-A14
~
Addresses Valid
1
\
1
1
1
I
I
OQO-OQ7
J!i
VIH
I
I
I
I
I4-- t a ( E ) 4
\ k-ten(G)~1
I
1
1
1
1
10IIII
G
VIH
VIL
I
I
1
E
X
tv(A)
~I
talA)
«<<<<<<
HI-Z
1
VIL
I
I
VIH
t~tdls~1
I
I~
VIL
~I
»»»>}-
Output Valid
VOH
HI-Z VOL
Figure 3. Read Cycle Timing
1~04---- Program
_ _~
AO-A14
X"-________
1
:
"T_.JX Ad~!~SS
A_d_d_re_ss_S.,.ta_b_le_ _ _ _ _ _
I
/+- tsu(A)
-+I
OQO-OQ7
04
----..'1..11 ---- Verify _ _~.I
C
---<~
:Oata In Stable
~ tsu(O)
--...A
r
I
1
/+- th(A) ~
1
HI-Z
-:---<
I :
Oata Out Valid
I
?>-----1
VIH
V
IL
VIH/VOH
VIL/VOH
tdis(G)t ~
I
~--I-----~I----+I--+---~I---------Vppt
VPP
I
I
1
:
I:
I
1
I
1
:
1
~ tsu(VPP)
Vcc
~r;-~:-----:r----~:-~:---~:-------vcct
~ tsu(VCC)
I
~ tSU(E)i~.-~.:- th(O)
E----""".!!\J
I
tw(IPGM)
+i
I
14-
I
I :
::
14!04-~.!f---
I
I
/+- tsu(G) -+I
I
1
1
I
G-------------~~~I
Vcc
1
I
VIH
1
ten(G)t :
VIL
1
____ I
I
*
Figure 4. Program Cycle Timing (SNAP! Pulse Programming)
TEXAS
VIH
J
t ldis(G) and ten (G) are characteristics of the device but must be accommodated by the programmer.
13-VVpp and 6.5-V Vee for SNAP! Pulse programming.
~
INSTRUMENTs
6-12
VCC
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
VIL
TMS27C256 262 144·BIT UV ERASABLE PROGRAMMABLE READ·ONLY MEMORY
TMS27PC256 262 144·BIT PROGRAMMABLE READ·ONLY MEMORY
SMLS256F-SEPTEMBER 1984-REVISED JANUARY 1993
device symbolization
This data sheet is applicable to all TI TMS27C256 CMOS EPROMs and TMS27PC256 CMOS OTP PROMs
with the data sheet revision code "S" as shown below.
0
B L X P
Data Sheet Revis Ion Code
Wafer Fab Code
Ole Revision Cod e
Assembly Site Co de
Year of Manufacture
Month of Manufa cture
.....
"-
TI FML
TMS27PC256
TMS
27C256
B L X p
YV'!!f!-
~
YV'!!Y:!..
Data Sheet Revis Ion Code
Wafer Fab Code
Ole Revision Cod e
Assembly Site Code
Year of Manufacture
Month of Manufa cture
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
6-13
TMS27C256262 144-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY
TMS27PC256 262144-81T PROGRAMMABLE READ·ONLY MEMORY
SMLS256F-SEPTEMBER 1984-REVISED JANUARY 1993
TYPICAL TMS27C/PC256 CHARACTERISTICS
C
~:::I
1.50
.?:
1.25
Q.Q."C
vs
FREE-AIR TEMPERATURE
SUPPLY VOLTAGE
~" ........
GI
~ ~
:g
STANDBY SUPPLY CURRENT
vs
c
E
lij ~
1...
u
1.00
~ ...........
8:i
~ .~
>- iii 1.00
"""'- r---
~
1III
0.75
...
25
50
75
TA - Free-Air Temperature -
4.5
'C
1.50
I!!
,
c;.
1.25
c..=6"
Q. GI
~ ~
.-~ ...E
ti
1.00
SUPPLY VOLTAGE
C
'",
0.50
-75 -50 -25
2: 'ii
::>ZZ
Latchup Immunity of 250 mA on All Input
and Output Lines
Low Power Dissipation (Vee = 5.5 V)
- Active . . . 165 mW Worst Case
- Standby . . . 1.4 mW Worst Case
(CMOS-Input Levels)
PEP4 Version Available With 168 Hour
Burn-In, and Choices of Operating
Temperature Range
512K EPRQM Available With MIL-STD-883C
Class B High Reliability Processing
(SMJ27C510)
4
3 2 1 3231 30
29
A7
A6
A5
7
A4
8
26
A3
A2
A1
AD
DOD
9
25
10
24
23
A14
A13
AS
A9
A11
G
A1D
12
22
E
13
21
D07
5
0
6
28
27
11
o~§i!8c8~
oO)j-
VIL
HI-Z - : : :
TMS27C510 524 288·BIT ERASABLE PROGRAMMABLE READ·ONLY MEMORY
TMS27PC510 524 288·BIT PROGRAMMABLE READ·ONLY MEMORY
SMLS51 OA-AUGUST 199(}-REVISEO JANUARY 1993
PARAMETER MEASUREMENT INFORMATION
AO-A15
~
~
1
1
o;ta In Stable
1
1
1
1
1
1
I
I
I
1
1
1
---I'f
1
~tsu(VPP)
---I'f :
1
I
~tsu(Vee)~
I
E
~ I.
tw(PGM)
G
:.-
1
1 1
~tsu(E)
I..
I
.1
I
.
I
1
1
I
oat~out
Valid
1
1
1
1
1
1
I
I
1
th(O) I
I
I
I
I
.1 1
I tsu(G)
I
I
I"
I
Address
N +1
VIH
VIL
I+- th(Al +i
}-H'-f-{
~tsu(O)
Vee
:x
Address Stable
I
Vpp
1
1
I
~t8u(A)
000-007
Verify -------.j
I"
~I
Program
I..
I
j
VIH/VOH
I
I
VIL/VOL
~tdls(G)t
1
1
1
1
1
1
1
1
I
1
I
I
I
1
1
Vpp:!:
Vee
Vee:!:
Vee
VIH
VIL
.1 ten(G)~
'{ II!
I
1
VIH
VIL
t tdis(G) and ten (G) are characteristics of the device but must be accommodated by the programmer.
:!: 13.0-V Vpp and 6.5-V Vee for SNAPI Pulse programming.
Figure 4. Program Cycle Timing
TEXAS
"f
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
6-23
TMS27C510 524 288·BIT ERASABLE PROGRAMMABLE READ·ONLY MEMORY
TMS27PC510 524 288·BIT PROGRAMMABLE READ·ONLY MEMORY
SMLS51 OA-AUGUST 199o-REVISED JANUARY 1993
device symbolization
0
L X
Wafer Fab Code
Ole RevIsIon Code
Assembly SIte Cod e
Year of Manufacture
Month of Man ufact ure
P
YV
-
~
TMS
27C510
L
WW
-
-r-
Wafer Fab Code
Ole RevIsIon Code
Assembly SIte Co de
Year of Manufactu re
Month of Manufacture
TEXAS
~
INSfRUMENTS
6-24
""
I'--..
TI FML
TMS27PC510
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
XPYVWW
- -
-
TMS27C510 524 288·BIT ERASABLE PROGRAMMABLE READ·ONLY MEMORY
TMS27PC510 524 288·BIT PROGRAMMABLE READ·ONLY MEMORY
SMLS51 OA-AUGUST 199G-REVISED JANUARY 1993
TYPICAL TMS27C/POC510 CHARACTERISTICS
STANDBY SUPPLY CURRENT
1.50
STANDBY SUPPLY CURRENT
vs
vs
FREE-AIR TEMPERATURE
SUPPLY VOLTAGE
1.50
Vee = 5.0V
TA=25°C
........
1.25
.......
...............
1.00
-------
...........
0.75
0.50
-75
-50
-25
0
25
50
75
100
,./
1.00
./'"
0.75
0.50
4.25
125
ACTIVE SUPPLY CURRENT
./
4.5
4.75 5.0 5.25 5.5
Vec-Supply Voltage-V
vs
FREE-AIR TEMPERATURE
SUPPLY VOLTAGE
1.50
TA = 25°e
f=MAX
Vee=5.0V
"' ....
.......
...............
.............
1.00
0.75
-50
-25
o
------
25
50
75
.,....... .--
1.25
1.00
r---
100
0.75
... /"
0.50
4.25
125
4.5
4.75
~i
1.25
8'"
1.00
=~
;1
~- 0.75
0.50
-75
5.25
5.5
Vec-Supply Voltage-V
ACCESS TIME
ACCESS TIME
vs
III
........... ~
..,.......V
-25
V
0
------
50
E~
1.25
=~
III'"
1.00
~-
0.75
I=i
~I
-----25
5.75
SUPPLY VOLTAGE
1.50
Vee = 5.0V
-50
5.0
TA-Free-Alr Temperatur&-°e
FREE-AIR TEMPERATURE
III
~
./"
vs
1.50
5.75
ACTIVE SUPPLY CURRENT
vs
1.50
0.50
-75
,/'
./
TA-Free-Alr Temperature-°e
1.25
V
1.25
75
100
TA = 25°e
...............
0.50
4.25
125
.......
TA-Free-Alr Temperature-°e
4.5
r--
4.75
5.0
5.25
5.5
5.75
Vec-Supply Voltag&-V
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
6·25
TMS27C510 524 288·81T ERASABLE PROGRAMMABLE READ·ONLY MEMORY
TMS27PC510 524 288·BIT PROGRAMMABLE READ·ONLY MEMORY
SMLS51 OA-AUGUST 199O--REVISED JANUARY 1993
TEXAS ~
INsrRUMENTS
6-26
POST OFFICE BOX 1443· HOUSTON, TEXAS 77001
TMS27C512 524 288-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY
TMS27PC512 524 288-BIT PROGRAMMABLE READ-ONLY MEMORY
SMLS512E-NOVEMBER 1985-REVISED DECEMBER 1992
J AND N PACKAGEst
This Data Sheet is Applicable to All
TMS27C512s and TMS27PC512s
Symbolized with Code "8" as Described
on Page 12.
(TOP VIEW)
A1S
A12
• Organization ... 64K x 8
• Single 5-V Power Supply
• Pin Compatible With Existing 512K MOS
ROMs, PROMs, and EPROMs
• All Inputs/Outputs Fully TTL Compatible
• Max Access/Min Cycle Time
Vee ± 10%
'27C/PC512-10
'27C/PC512-12
'27C/PC512-15
'27C/PC512-20
'27C/PC512-25
Vee
1
A14
A13
AS
A9
A11
27
26
25
24
23
AS
A4
A3
A2
G/Vpp
A10
E
AO
DOO
D01
D02
GND
100 ns
120 ns
150 ns
200 ns
250 ns
DO?
D06
DOS
D04
D03
• Power Saving CMOS Technology
• Very High-Speed SNAP! Pulse
Programming
FM PACKAGEt
(TOP VIEW)
• 3-State Output Buffers
• 400·mV Minimum DC Noise Immunity With
Standard TTL Loads
4
• Latchup Immunity of 250 mA on All Input
and Output Lines
A6
AS
A4
A3
A2
A1
AO
NC
DOO
• Low Power Dissipation (Vee = 5.25 V)
- Active ... 158 mW Worst Case
- Standby .•. 1.4 mW Worst Case
(CMOS Input Levels)
• PEP4 Version Available With 168-Hour
Burn-in, and Choices of Operating
Temperature Ranges
• 512K EPROM Available With MIL·STD-883C
Class B High Reliability Processing
(SMJ27C512)
3 2
5
AS
A9
A11
NC
o
6
7
8
9
10
11
12
21
13
1415 16 171819 20
G/Vpp
A10
E
DO?
D06
~C\J0:::::>"'---- HI-Z ---«
---«
II
~ tsu(O)
1
1
G / Vpp
--11'
1
1 10II I
11
+I
i
r--
:
E
1
.1
1
~
tsu(VPP)
1
1
1
1
1
I - .,
1
1
1----
~
1
10IIII-- th(O)
1
tr(PG)G
+--.:
1
Data Out Valid
VIL
tw(IPGM)
1
Vee;
VCC~
VCC
t ldis(Gl is a characteristic of the device but must be accommodated
by the programmer.
; 13-V G / Vpp and 6.5-V Vee for SNAP! Pulse programming.
Figure 4. Program Cycle Timing (SNAP! Pulse Programming)
TEXAS
~
IN8rRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
6-37
TMS27C512 524 288-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY
TMS27PC512 524 288-91T PROGRAMMABLE READ-ONLY MEMORY
SMLS512E-NOVEMBER 1985-REVISED DECEMBER 1992
device symbolization
This data sheet is applicable to all TI TMS27C512 CMOS EPROMs and TMS27PC512 CMOS OTP PROMs
with the data sheet revision code "S" as shown below.
0
B L X P
Data Sheet Revis Ion Code
Wafer Fab Code
Ole Revision Cod
Assembly Site Co d
Year of Manufacture
Week of Manufaclure
~
TMS
27C512
YV'!!'!!..
B
Data Sheet Revis 10nCodeWafer Fab Code
Dla Revision Cod e
Assembly Site Code
Year of Manufacture
Month of Manufacture
TEXAS
~
INSTRUMENTS
6·38
"'"
.........
TI FML
TMS27PC512
POST OFFICE BOX 1443' HOUSTON. TEXAS 77001
L
X
P
YV'J!'t!.
TMS27C010A 1048 576-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY
TMS27PC010A 1048 576-BIT PROGRAMMABLE READ-ONLY MEMORY
SMLS11 OA-NOVEMBER 1990--REVISED DECEMBER 1992
• Organization ... 128K x 8
J AND N PACKAGEst
(TOP VIEW)
• Single 5-V Power Supply
• Operationally Compatible With Existing
Megabit EPROMs
• Industry Standard 32-Pin Dual-In-line
Package, 32-Lead Plastic Leaded Chip
Carrier, and 32-Lead Thin Small-Outline
Package
Vpp
VCC
A16
PGM
A15
NC
A12
A14
• All Inputs/Outputs Fully TTL Compatible
• Max Access/Min Cycle Time
Vee
± 10%
'27C010A-10
'27C/PC010A·12
'27C/PC010A-15
'27C/PC010A-20
100
120
150
200
ns
ns
ns
ns
• 8-Blt Output For Use in
Microprocessor-Based Systems
A7
A13
A6
AB
A5
A9
A4
A11
A3
IT
A2
A10
A1
E
AO
D07
DOO
D06
D01
D05
D02
D04
GND
D03
• Very High-Speed SNAPI Pulse
Programming
FMPACKAGEt
(TOP VIEW)
• Power-Saving CMOS Technology
• 3-State Output Buffers
• 400-mV Minimum DC Noise Immunity With
Standard TTL Loads
4
• Latchup Immunity of 250 mA on All Input
and Output Pins
A7
5
3 2
1 3231 30
29
0
A6
6
28
27
26
• No Pullup Resistors Required
25
• Low Power Dissipation (Vee =5.5 V)
- Active . .. 165 mW Worst Case
- Standby . .. 0.55 mW Worst Case
(CMOS-Input Levels)
A2
10
24
A1
11
23
AO
12
22
DOO
• PEP4 Version Available With 168 Hour
Burn-In and Choices of Operating
Temperature Ranges
21
13
1415 16 171819 20
D07
c;~~8c8(3
DDC!JDDDD
t Packages are shown for pinout reference only,
description
The TMS27C010A series are 1 048 576-bit,
ultraviolet-light
erasable,
electrically
programmable read-only memories.
The TMS27PC010A series are 1 048 576-bit,
one-time electrically programmable read-only
memories.
PIN NOMENCLATURE
AO--A16
E
G
GND
NC
PGM
DOD-D07
VCC
Vpp
Address Inputs
Chip Enable
Output Enable
Ground
No Internal Connection
Program
Inputs {programming)/Outputs
5-V Supply
13-V Power Supply*
* Only in program mode.
~~~~~~o:.O:1: .:.c~I:'''PI:''':::' ~' !~:~:r~m~~~
standard wlrrlnty. Production proctIIlng dOlI not ntet...rily Include
Illiing .f .11 pllIm......
TEXAS ~
Copyright © 1992, Texas Instruments Incorporated
IN5rRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
6-39
TMS27C010A 1048 576·BIT UV ERASABLE PROGRAMMABLE READ·ONLY MEMORY
TMS27PC010A 1048 576·BIT PROGRAMMABLE READ·ONLY MEMORY
SMLS110A-NOVEMBER 199O-REVISEO DECEMBER 1992
TMS27PC010A ••• DO PACKAGEt
(TOP VIEW)
0
All
32
G
A9
2
31
Al0
A8
3
30
E
A13
4
29
D07
A14
5
28
D06
NC
PMG
6
27
D05
7
26
D04
Vee
Vpp
8
25
D03
9
24
Vss
A16
10
23
D02
A15
11
22
DOl
A12
12
21
DOO
A7
13
20
AO
A6
14
19
Al
A5
15
18
A2
A4
16
17
A3
TMS27PC010A ... DU PACKAGEt
REVERSE PINOUT
(TOP VIEW)
G
1
32
All
Al0
2
31
A9
E
3
30
A8
D07
4
29
A13
D06
5
28
A14
D05
6
27
D04
7
26
NC
PGM
D03
8
25
Vss
9
24
Vee
Vpp
D02
10
23
A16
DOl
11
22
A15
DOO
12
21
A12
AO
13
20
A7
Al
14
19
A6
A2
15
18
A5
A3
16
17
A4
\l
t The packages shown are for pinout reference only.
TEXAS ~
INSTRUMENTS
6-40
POST OFFICE BOX 1443' HOUSTON. TEXAS 77001
TMS27C010A 1048 576-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY
TMS27PC010A 1048 576-BIT PROGRAMMABLE READ-ONLY MEMORY
SMLS110A-NOVEMBER 199G-REVISED DECEMBER 1992
These devices are fabricated using power-saving CMOS technology for high speed and simple interface with
MOS and bipolar circuits. All inputs (including program data inputs) can be driven by Series 74 TTL circuits
without the the use of external pullup resistors. Each output can drive one Series 74 TTL circuit without external
resistors.
The TMS27C010A EPROM is offered in a dual-in-line ceramic package (J suffix) designed for insertion in
mounting hole rows on 15.2-mm (600-mil) centers. The TMS27C010A is also offered with two choices of
temperature ranges. O°C to 70°C (JL suffix) and -40°C to 85°C (JE suffix). The TMS27C01 OA is also offered
with 168 hour burn-in on both temperature ranges (JL4 and JE4 suffix). (See table below.)
The TMS27PC01 OA OTP PROM is offered in a dual-in-line plastic package (N suffix). a 32-pin. plastic leaded
chip carrier package using 1.25-mm (50-mil) lead spacing (FM suffix). and a 32-lead TSOP package (DO and
DU suffixes). The TMS27PC010A is offered with two choices of temperature ranges.
O°C to 70°C (NL. FML. DOL. and DUL suffixes) and - 40°C to 85°C (NE. FME. DOE. and DUE suffixes).
(See table below.)
EPROM
AND
OTPPROM
SUFFIX FOR OPERATING
TEMPERATURE RANGES
WITHOUT PEP4 BURN-IN
TMS27e01 OA-xxx .
TMS27pe010A-xxx
SUFFIX FOR PEP4
168 HOUR BURN-IN
VS TEMPERATURE RANGES
ooe 10 70 0 e
- 40 0 e 10 85°e
ooe 10 70 0 e
JL
JE
JL4
JE4
NL
NE
NL4
NE4
FML
FME
FML4
FME4
DDL
DDE
DUL
DUE
- 40 0 e 10 85°e
These EPROMs and OTP PROMs operate from a single 5-V supply (in the read mode). thus are ideal for use
in microprocessor-based systems. One other 13-V supply is needed for programming. All programming Signals
are TTL level. These devices are programmable using the SNAPI Pulse programming algorithm. The SNAPI
Pulse programming algorithm uses a Vpp of 13 V and a Vee of 6.5 V for a nominal programming time of thirteen
seconds. For programming outside the system. existing EPROM programmers can be used. Locations may be
programmed singly. in blocks. or at random.
operation
The seven modes of operation are listed in the following table. The read mode requires a single 5-V supply. All
inputs are TTL level except for Vpp during programming (13 V for SNAP! Pulse). and 12 V on A9 for signature
mode.
MODE
FUNCTION
READ
OUTPUT
DISABLE
STANDBY
PROGRAMMING
VERIFY
PROGRAM
INHIBIT
SIGNATURE MODE
E
VIL
VIL
VIH
VIL
VIL
VIH
VIL
G
VIL
VIH
xt
VIH
VIL
VIL
Vee
PGM
X
X
X
VIL
VIH
X
X
Vpp
Vee
Vee
Vee
Vpp
Vpp
Vpp
Vee
Vee
Vee
Vee
Vee
Vee
Vee
A9
x
X
x
x
x
AO
X
X
X
X
X
X
X
X
Vee
VH*
I
VH*
VIL
I
VIH
eODE
DOO-D07
Data Oul
HI-Z
HI-Z
Dala In
DalaOul
HI·Z
MFG
97
I DEVleE
I D6
t X can be VIL or VIH.
* VH = 12 V ± 0.5 V.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
6·41
TMS27C010A 1 048 576·BIT UV ERASABLE PROGRAMMABLE READ·ONLY MEMORY
TMS27PC010A 1048 576·BIT PROGRAMMABLE READ·ONLY MEMORY
SMLS11 OA-NOVEMBER 199D-REVISED DECEMBER 1992
read/output disable
When the outputs of two or more TMS27C01 OAs or TMS27PC01 OAs are connected in parallel on the same bus,
the output of any particular device in the circuit can be read with no interference from competing outputs of the
other devices. To read the output of a single device, a low-level signal is applied to the E and G pins. All other
devices in the circuit should have their outputs disabled by applying a high level signal to one of these pins.
latchup immunity
Latchup immunity on the TMS27C01 OA and TMS27PC01 OA is a minimum of 250 mA on all inputs and outputs.
This feature provides latchup immunity beyond any potential transients at the P.C. board level when the devices
are interfaced to industry standard TIL or MOS logic devices. The input/output layout approach controls latchup
without compromising performance or packing density.
power down
Active ICC supply current can be reduced from 30 mA to 500 !-IA by applying a high TIL input on E and to
100!-IA by applying a high CMOS input on E. In this mode all outputs are in the high-impedance state.
erasure (TMS27C010A)
Before programming, the TMS27C01 OA EPROM is erased by exposing the chip through the transparent lid to
a high intensity ultraviolet light (wavelength 2537 A). The recommended minimum exposure dose (UV intensity
x exposure time) is 15-Ws/cm2. A typical 12-mW/cm2, filterless UV lamp will erase the device in 21 minutes.
The lamp should be located about 2.5 cm above the chip during erasure. After erasure, all bits are in the high
state. It should be noted that normal ambient light contains the correct wavelength for erasure. Therefore, when
using the TMS27C01 OA, the window should be covered with an opaque label. After erasure (all bits in logic high
state), logic lows are programmed into the desired locations. A programmed low can be erased only by
ultraviolet light.
initializing (TMS27PC010A)
The one-time programmable TMS27PC01 OA PROM is provided with all bits in the logic high state, then logic
lows are programmed into the desired locations. Logic lows programmed into an OTP PROM cannot be erased.
SNAP! Pulse programming
The TMS27C010A and TMS27PC010A are programmed using the TI SNAP! Pulse programming algorithm
illustrated by the flowchart in Figure 1, which programs in a nominal time of thirteen seconds. Actual
programming time will vary as a function of the programmer used.
The SNAP! Pulse programming algorithm uses an initial pulse of 100 microseconds ([1s) followed by a byte
verification to determine when the addressed byte has been successfully programmed. Up to 10 (ten) 100-[1s
pulses per byte are provided before a failure is recognized.
=
=
=
=
The programming mode is achieved when Vpp 13 V, Vee 6.5 V, E VIL, G VIH' Data is presented in
parallel (eight bits) on pins 000 through 007. Once addresses and data are stable, PGM is pulsed low.
More than one device can be programmed when the devices are connected in parallel. Locations can be
programmed in any order. When the SNAP! Pulse programming routine is complete, all bits are verified with
Vee = Vpp = 5 V ± 10%.
program inhibit
Programming may be inhibited by maintaining a high level input on the E or PGM pins.
program verify
Programmed bits may be verified with Vpp
=13 V when G =VIL, E =VIL, and PGM =VIH'
TEXAS
~
INSTRUMENTS
6·42
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
TMS27C010A 1 048 576-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY
TMS27PC010A 1048 576-BIT PROGRAMMABLE READ-ONLY MEMORY
SMLSll0A-NOVEMBER 199a-REVISED DECEMBER 1992
l
Program
Mode
Increment Address
Increment
Address
Interactive
Mode
Final
Varlflcatlon
J
Figure 1. SNAP! Pulse Programming Flowchart
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
6-43
TMS27C010A 1048 576·BIT UV ERASABLE PROGRAMMABLE READ·ONLY MEMORY
TMS27PC010A 1048 576·BIT PROGRAMMABLE READ·ONLY MEMORY
SMLS110A-NOVEMBER 1990-REVISED DECEMBER 1992
signature mode
The signature mode provides access to a binary code identifying the manufacturer and type. This mode is
activated when A9 (pin 26) is forced to 12 V. Two identifier bytes are accessed by toggling AO. All addresses
must be held low. The signature code for these devices is 9706. AO low selects the manufacturer's code 97
(Hex). and AO high selects the device code 06 (Hex). as shown by the signature mode table below.
signature modet
PINS
IDENTIFIERt
AO
D07
DOS
DOS
DQ4
D03
DQ2
D01
DOO
MANUFACTURER CODE
VIL
1
0
0
1
0
1
1
1
97
DEVICE CODE
VIH
1
1
0
1
0
1
1
0
06
tEO = G = VIL, Al-AB = VIL, A9 = VH. A1D-A16 = VIL, Vpp = VCC.
logic symbol t
EPROM 131072 x 8
AO
A1
A2
A3
A4
AS
A6
A7
A8
A9
A10
A11
A12
A13
A14
A1S
A16
E
o "
12
11
10
9
8
7
S
5
27
26
23
25
4
28
29
3
2
>
16
22
Lb
24
0
A 131 071
AV
AV
AV
AV
AV
AV
AV
AV
I'--
[PWRDOWNI
&
I
EN
*This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
J package illustrated.
TEXAS
~
INSTRUMENTS
6-44
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
13
14
15
17
18
19
20
21
000
D01
D02
D03
D04
DOS
DOS
D07
HEX
TMS27C010A 1 048 576-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY
TMS27PC010A 1048 576-BIT PROGRAMMABLE READ-ONLY MEMORY
SMLS110A-NOVEMBER 1990-REVISED DECEMBER 1992
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage range, Vee (see Note 1) .............................................. -0.6 V to 7 V
Supply voltage range, Vpp ......................................................... -0.6 V to 14 V
Input voltage range, All inputs except A9 ........................................ -0.6 V to Vee + 1 V
A9 .......................................................... -0.6 V to 13.5 V
Output voltage range, with respect to V S8 (see Note 1) ........................... -0.6 V to Vee + 1 V
Operating free-air temperature range ('27C010A-__JL and JL4,
'27PC010A-__ NL, FML, DOL, and DUL) ............. O°C to 70°C
Operating free-air temperature range (,27C01 OA-__JE and JE4,
'27PC010A-__NE, FME, DOE, and DUE) .......... - 40°C to 85°C
Storage temperature range ....................................................... -65°C to 150°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to GND.
recommended operating conditions
'27C010A-10
'27C010A/PC010A-12
'27C010A/PC010A-15
'27C01 OA/PC01 OA-20
Vee Supply voltage
Vpp Supply voltage
Read mode (see Note 2)
SNAP! Pulse programming algorithm
Read mode (see Note 3)
VIH High-level dc input voltage
CMOS
5
5.5
V
6.25
6.5
6.75
V
Vee+ 0.5
-0.5
Operating free-air temperature
'27e010A-__JL,JL4
'27pe010A-__NL, FML, DDL, DUL
TA
Operating free-air temperature
'27e010A-__JE,JE4
'27pe010A-__ NE, FME, DDE, DUE
13.25
Vee+ 0.5
-0.5
TA
13
Vee+ 0.6
2.0
TTL
Low-level dc input voltage
Vee
Vee-0 .2
CMOS
VIL
NOTES:
TYP
4.5
12.75
TTL
MAX
MIN
Vee- 0.6
SNAP! Pulse programming algorithm
UNIT
0.8
GND+0.2
V
V
V
V
0
70
'e
-40
85
'e
2. Vee must be applied before or atthe sametimeasVppand removed afteroratthe sametimeas Vpp. The device mustnotbe inserted
into or removed from the board when Vpp or Vee is applied.
3. During programming, Vpp must be maintained at 13 V ± 0.25 V.
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443· HOUSTON. TEXAS 77001
6-45
TMS27C010A 1048 576·BIT UV ERASABLE PROGRAMMABLE READ·ONLY MEMORY
TMS27PC010A 1048 576·BIT PROGRAMMABLE READ·ONLY MEMORY
SMLSIIOA-NOVEMBER I 99(}'-REVISED DECEMBER 1992
electrical characteristics over full range of operating conditions
PARAMETER
VOH
High-level dc output voltage
VOL
loW-level dc output voltage
TEST CONDITIONS
MIN
10H = -20!iA
MAX
VCC-0.2
V
3.5
10H = -2.5mA
UNIT
IOL=2.1 mA
0.4
10L = 20!iA
0.1
V
~
II
Input current (leakage)
VI = Oto 5.5V
:tl
10
Output current (leakage)
Vo =OtoVCC
:tl
~
IpPI
Vpp supply current
Vpp =VCC = 5.5 V
10
I'A
IpP2
Vpp supply current (during program pulse)
50
mA
Vpp=13V
ITIL-input level
ICMOS-input level
ICC I
VCC supply current (standby)
ICC2
VCC supply current (active) (output open)
E = VIH, VCC = 5.5 V
500
E = VCC ",0.2 V, VCC = 5.5 V
100
!iA
E = VIL, VCC = 5.5 V,
30
leycle = minimum cycle timet,
mA
outputs open
t Minimum cycle time = maximum access time.
capacitance over recommended ranges of supply voltage and operating free·air temperature,
f = 1 MHz;
TYP§
MAX
Ci
Input capacitance
VI = 0, f = I MHz
4
8
pF
Co
Output capacitance
Vo = 0, f = I MHz
6
10
pF
PARAMETER
TEST CONDITIONS
MIN
UNIT
t CapaCItance measurements are made on sample baSIS only.
§ AU typical values are at TA = 25°C and nominal voltages.
switching characteristics overfull ranges of recommended operating conditions (see Notes 4 ahd 5)
PARAMETER
TEST
CONDITIONS
(SEE NOTES
4 &5)
'27C010A-10
MIN
MAX
'27C010A-12
'27PC010A·12
MIN
MAX
'27C010A·15
'27PC010A·15
MIN
MAX
'27C010A·20
'27PC010A·20
MIN
UNIT
MAX
ta(A)
Access time from address
100
120
150
200
ns
tatE)
Access time from chip
enable
100
120
150
200
ns
1en(G)
Output enable time from G
55
55
75
75
ns
lcJiS
Output disable time from G
or E, whichever occurs firstll
60
ns
tv(A)
Output data valid time after
change of address, E, or G,
whichever occurs first
CL = 100 pF,
1 Series 74
TIL load,
Input tr .: 20 ns,
Input tf " 20 ns
0
50
0
0
0
50
0
0
60
0
0
ns
II Value calculated from 0.5-V delta to measured output level.
NOTES: 4. For all switching characteristics the input pulse levels are 0.4 V to 2.4 V. Timing measurements are made at 2 V for logic high and
O.B V for logic low (reference AC testing waveform).
5. Common test conditions apply for tdis except during programming.
TEXAS
~
INSfRUMENTS
6-46
POST OFFICE BOX 1443· HOUSTON. TEXAS 77001
TMS27C010A 1048 576·BIT UV ERASABLE PROGRAMMABLE READ·ONLY MEMORY
TMS27PC010A 1048 576·BIT PROGRAMMABLE READ·ONLY MEMORY
SMLS110A-NOVEMBER 1990-REVISED DECEMBER 1992
switching characteristics for programming: Vee
(see Note 4)
=6.5 Vand Vpp =13 V (SNAP! Pulse), TA =25°C
PARAMETER
ldis(G)
Output disable time from G
len (G)
Output enable time from G
MIN
NOM
0
MAX
UNIT
130
ns
150
ns
recommended timing requirements for programming: Vee = 6.5 Vand Vpp = 13 V (SNAP! Pulse),
TA = 25°C, (see Note 4)
ISNAPI Pulse programming algorithm
MIN
TYP
MAX
UNIT
95
100
105
Ils
tw(PGM)
Program pulse duration
lsu(A)
Address setup time
2
IlS
tsu(E)
E setup time
2
I!S
tsu(G)
G setup time
2
I!S
tsu(D)
Data setup time
2
IlS
tsu(VPP)
Vpp setup time
2
IlS
tsu(VCC)
VCC setup time
2
Ils
theA)
Address hold time
0
IlS
th(D)
Data hold time
2
I!S
NOTE 4:
..
For all sWitching characteristics the Input pulse levels are 0.4 V to 2.4 V. Timing measurements are made at 2 V for logic high and .
0.8 V for logic low (reference AC testing waveform).
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
6-47
TMS27C010A 1048 576·BIT UV ERASABLE PROGRAMMABLE READ·ONLY MEMORY
TMS27PC010A 1048 576·BIT PROGRAMMABLE READ·ONLY MEMORY
SMLS110A-NOVEMBER 199O-REVISED DECEMBER 1992
PARAMETER MEASUREMENT INFORMATION
2.08 V
Output
Under Test
---4
T
RL = 800 Q
CL=100pF
Figure 2. AC Test Output Load Circuit
AC testing input/output wave forms
2.4 V'---""'V,
'___.J!\ ~.: v
0.4 V-
AC testing inputs are driven at 2.4 V for logic high and 0.4 V for logic low. Timing measurements are made at
2 V for logic high and 0.8 V for logic low for both inputs and outputs.
.JX,..I______A_d_dr_es_s_v_al_ld_ _ _ _ _....;1IX================= :::
AO-A16 _ _ _
I
1oIIII
13
14
15
17
18
19
20
21
DQO
DQl
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
17/
22
L.t:"
24
0
A262143
AV
AV
AV
AV
AV
AV
AV
AV
r--.
[PWRDOWNI
&
I
EN
t This symbol is in accordance w~h ANSI/IEEE Std 91-1984 and lEe Publication 617-12.
Pin numbers are for the J package.
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443· HOUSTON. TEXAS 77001
6-65
TMS27C020 2 097152 BIT UV ERASABLE PROGRAMMABLE READ·ONLY MEMORY
TMS27PC020 2 097152 BIT PROGRAMMABLE READ·ONLY MEMORY
SMLS020A-NOVEMBER 199O-REVISED JANUARY 1993
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage range, Vee (see Note 1) ..............•............................... -0.6 V to 7 V
Supply voltage range, Vpp ......................................................... -0.6 V to 14 V
Input voltage range (see Note 1), All inputs except A9 ............................ -0.6 V to Vee + 1 V
A9 .............................................. -0.6 V to 13.5 V
Output voltage range, with respect to V55 (see Note 1) ........................... -0.6 V to Vee + 1 V
Operating free-air temperature range (,27C020-__ JL and JL4) ........................... O°C to 70°C
Operating free-air temperature range ('27C020-__JE and JE4) ........................ - 40°C to 85°C
Storage temperature range ....................................................... -65°C to 150°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-ratedconditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to GND.
recommended operating conditions
TYP
MIN
VCC
Vpp
Supply voltage
Supply voltage
Read mode (see Note 2)
SNAPI Pulse programming algorithm
Read mode
SNAP! Pulse programming algorithm
TTL
VIH
High-level dc input voltage
VIL
LOW-level dc input voltage
TA
Operating free-air temperature
'27e020-
TA
Operating free-air temperature
CMOS
MAX
UNIT
4.5
5
5.5
V
6.25
6.5
6.75
V
VCC-0.6
VCC
VCC+0.6
V
12.75
13
13.25
V
2
VCC+0.5
Vee-0.2
Vec+0.5
V
TTL
-0.5
0.8
CMOS
-0.5
GND+0.2
JL, JL4
0
70
·C
'27C020-__JE, JE4
-40
85
·C
V
NOTE 2: Vee must be applied before or at the same time as VPP and removed after or at the same time as Vpp. The device must not be
inserted into or removed from the board when Vpp or Vee is applied.
TEXAS ~
INSTRUMENTS
6-66
POST OFFICE BOX 1443· HOUSTON, TEXAS 77001
TMS27C020 2 097152 BIT UV ERASABLE PROGRAMMABLE READ·ONLY MEMORY
TMS27PC020 2 097152 BIT PROGRAMMABLE READ·ONLY MEMORY
SMLS020A-NOVEMBER 1990-REVISED JANUARY 1993
electrical characteristics over full ranges of operating conditions
PARAMETER
VOH
High-level dc output voltage
VOL
Low-level dc output voltage
TEST CONDITIONS
MAX
MIN
IOH ; -20 j.iA
VCC-0.2
10H; -2 mA
2.4
UNIT
V
IOL; 2.1 mA
0.4
IOL; 20 j.iA
0.1
V
II
Input current (leakage)
VI; Oto 5.5 V
±1
~A
10
Output current (leakage)
Vo;OtoVCC
±1
j.iA
IpPl
Vpp supply current
Vpp ; VCC ; 5.5 V
10
j.iA
IpP2
Vpp supply current (during program pulse)
Vpp; 13V
50
mA
ICCl
VCC supply current (standby)
ICC2
VCC supply current (active)
IITTL-input
. level
CMOS-Input level
E; VIH, VCC; 5.5 V
500
E ; VCC ± 0.2 V, VCC ; 5.5 V
100
E ; VIL, VCC ; 5.5 V
!cycle; minimum cycle time,
outputs open t
30
j.iA
mA
t Minimum cycle time; maximum access time.
capacitance over recommended ranges of supply voltage and operating free-air temperature,
f = 1 MHzt
TYP§
MAX
Ci
Input capacitance
VI ; 0, f ; 1 MHz
4
8
pF
Co
Output capacitance
Vo ; 0, f ; 1 MHz
6
10
pF
PARAMETER
TEST CONDITIONS
MIN
UNIT
*Capacitance measurements are made on sample basIs only.
§ All typical values are at TA; 25°C and nominal voltages.
switching characteristics over full ranges of recommended operating conditions (see Notes 3
and 4)
PARAMETER
TEST
CONDITIONS
(SEE NOTES
3 & 4)
'27C020·12
'27PC020·12
MIN
'27C020·15
'27PC020·15
MAX
MIN
MAX
27C020·20
27PC020·20
MIN
MAX
'27C020·25
'27PC020·25
MIN
UNIT
MAX
ta(A)
Access time from address
120
150
200
250
ns
tatE)
Access time from chip enable
120
150
200
250
ns
len (G)
Output enable time from G
55
75
75
100
ns
lciis
Output disable time from G or E,
whichever occurs firstll
80
ns
tv(A)
Output data valid time after
change of address, E, or G,
whichever occurs first
CL; 100 pF,
1 Series 74
TTL load,
Input tr" 20 ns,
Input tf " 20 ns
a
50
a
a
a
60
a
a
60
a
a
ns
11 Value calculated from 0.5-V delta to measured output level. This parameter is sampled and not 100% tested.
NOTES: 3. For all switching characteristics the input pulse levels are 0.4 V to 2.4 V. Timing measurements are made at 2 V for logic high
and 0.8 V for logic low. (reference AC Testing Wave Form)
4. Common test conditions apply for tdis except during programming.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
6-67
TMS27C0202 097152 BIT UV ERASABLE PROGRAMMABLE READ·ONLY MEMORY
TMS27PC020 2 097152 BIT PROGRAMMABLE READ-ONLY MEMORY
SMLS020A-NOVEMBER 199O--REVISED JANUARY 1993
switching characteristics for programming: Vee = 6.5 V and Vpp = 13 V (SNAP! Pulse), TA = 25°C
(see Note 3)
PARAMETER
tdis(G)
Output disable time from G
1en(G)
Output enable time from G
MIN
NOM
0
MAX
UNIT
100
ns
150
ns
recommended timing requirements for programming: Vee = 6.5 V and Vpp = 13 V (SNAPI Pulse),
TA =25°C, (see Note 3)
ISNAPI Pulse programming algorithm
MIN
TYP
MAX
UNIT
95
100
105
1'5
tw(PGM)
Program pulse duration
tsu(A)
Address setup time
2
tsu(E)
E setup time
2
I!S
tsu(G)
G setup time
2
I!s
I!S
I!S
tsu(D)
Data setup time
2
tsuIVPP)
VPP setup time
2
I!S
tsuIVCC)
VCC setup time
2
I!s
th(Al
Address hold time
0
I!s
th(D)
Data hold time
2
I!S
NOTE 3: For all switching characteristics the input pulse levels are 0.4 V to 2.4 V. Timing measurements are made at 2 V for logic high
and 0.8 V for logic logic low. (reference AC Testing Wave Form)
TEXAS ~
INSfRUMENTS
6-68
POST OFFICE BOX 1443· HOUSTON. TEXAS 77001
TMS27C020 2097152 BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY
TMS27PC020' 2097 152 BIT PROGRAMMABLE READ-ONLY MEMORY
SMLS020A-NOVEMBER 199O-REVISED JANUARY 1993
PARAMETER MEASUREMENT INFORMATION
2.08 V
----lT
RL
Output
Under Test
= 800 Q
CL=loopF
Figure 2. AC Testing Output Load Circuit
AC testing input/output wave forms
2.4V
o.!~X,..._____
0.4V
AC testing inputs are driven at 2.4 V for logic high and 0.4 V for logic low. Timing measurements are made at
2 V for logic high and 0.8 V for logic low for both inputs and outputs.
AD-A17
~
Addresses Valid
i~
talA)
\
E
·1
1
1
1
1
I
\
I
OQD-OQ7
HI-Z
<~~~~
VIL
1
1
1
VIH
VIL
1 1
1 1
yt
1
1
1
1
~ten(G)~
X
jIi
~ta(E)~
G
VIH
VIH
1 ~tdls~
tv(A)
I~
Output Valid
.1
VIL
I
~~HI'Z-:::
Figure 3. Read Cycle Timing
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
6-69
TMS27C020 2097152 BIT UV ERASABLE PROGRAMMABLE READ·ONLY MEMORY
TMS27PC020 2097152 BIT PROGRAMMABLE READ·ONLY MEMORY
SMLS020A-NOVEMBER 199O-REVISED JANUARY 1993
PARAMETER MEASUREMENT INFORMATION
AGo-A17
14
.1
1
Program
I.I
=x
1
:x
Address Stable
.
I
~tsu{A)
~
OQG-DQ7
1
1
~I
1
1
1
Valid
1
1
1
I
1
1
1
1
1
1
1
1
1
I+---+t- tsu{VCC)
E
\
tsu{E)
PGM
1
1
1
1
I.-
1
-+I
·1
I
L/
tw(PGM)
14
1
.1
141
1
1
14
i
i
th{O)
1
1
1
1
1
.1 1tsu{G) 1
1 I..lten(G)tl
I 1
I
.\{
G
t !dis(G) and ten (G) are characteristics of the device but must be accommodated by the programmer.
* 13-V Vpp and 6.5-V Vee for SNAPI Pulse programming.
Figure 4_ Program Cycle Timing (SNAPI Pulse Programming)
TEXAS
~
INSTRUMENTS
6-70
VIL
VIHNoH
I
I
1
~1
VIH
VnjVoL
I+-------+t- tdls{G) t
14----+1-- tsu{VPP)
VCC
I
~ oat~out j
}
Data In Stable
I
Address
N+1
I+- th{Al ~
~tsu{O)
Vpp
----+I
Verify
POST OFFICE. BOX 1443' HOUSTON. TEXAS 77001
Vpp*
VCC
VCC*
VCC
VIH
VIL
VIH
VIL
VIH
VIL
TMS27C040 4194 304·BIT UV ERASABLE PROGRAMMABLE READ·ONLY MEMORY
TMS27PC040 4194 304·BIT PROGRAMMABLE READ·ONLY MEMORY
SMLS040D-NOVEMBER 1990-REVISED JANUARY 1993
•
•
•
•
•
•
TMS27C040
Organization ... 512K x 8
J PACKAGEt
(TOP VIEW)
Single 5·V Power Supply
Industry Standard 32·Pin Dual In·Line
Package and 32·Lead Plastic Leaded Chip
Carrier
Vpp
A16
A15
A12
A?
A6
A5
A4
A3
A2
A1
AO
DOO
D01
D02
GND
All Inputs/Outputs Fully TTL Compatible
Static Operation (No Clocks, No Refresh)
Max Access/Min Cycle Time
Vee
±
10%
'27C/PC040·10
'27C/PC040·12
'27C/PC040·15
100 ns
120 ns
150 ns
•
8·Bit Output For Use in
Microprocessor·Based Systems
•
•
•
Power·Saving CMOS Technology
10
Vee
A18
A1?
A14
A13
A8
A9
A11
G
A10
11
E
12
DO?
D06
D05
D04
D03
1
2
3
4
5
6
7
8
9
13
14
15
16
3·State Output Buffers
TMS27PC040
FM PACKAGEt
(TOP VIEW)
400·mV Assured DC Noise Immunity With
Standard TTL Loads
•
Latchup Immunity of 250 mA on All Input
and Output Pins
•
•
No Pullup Resistors Required
4 3 2
o
Low Power Dissipation (Vee =5.5 V)
- Active ... 275 mW Worst Case
- Standby ... 0.55 mW Worst Cas E
(CMOS·lnput Levels)
10
• PEP4 Version Available With 168·Hour
Burn·ln, and Choice of Two Operating
Temperature Ranges
12
13
1415 16 171819 20
description
The TMS27C040 series are 4 194 304-bit,
ultraviolet-light erasable, electrically programmable read-only memories.
The TMS27PC040 series are 4 194 304-bit,
one-time electrically programmable read-only
memories.
These devices are fabricated using CMOS
technology for high speed and simple interface
with MOS and bipolar circuits. All inputs (including
program data inputs) can be driven by Series 74
TTL circuits. Each output can drive one Series 74
DO?
t Packages are shown for pinout reference only.
PIN NOMENCLATURE
AO-A18
E
G
GND
DOO-D07
Vee
Vpp
Address Inputs
ehip Enable
Output Enable
Ground
Inputs {programming)/Outputs
5-V Supply
13-V Power Supply;
; Only in program mode.
TEXAS
~
Copyright © 1993, Texas Instruments Incorporated
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
6-71
TMS27C040 4194 304·B11 UV ERASABLE PROGRAMMABLE READ·ONLY MEMORY
TMS27PC040 4194 304·BIT PROGRAMMABLE READ·ONLY MEMORY
SMLS040D-NOVEMBER 199Q-REVISED JANUARY 1993
TTL circuit without external resistors. The data outputs are three-state for connecting multiple devices to a
common bus.
The TMS27C040 is offered in a 600-mil ceramic dual-in-line package (J suffix). The TMS27C040 is offered with
two choices of temperature ranges of O°C to 70°C (JL suffix) and - 40°C to 85°C (JE suffix). The TMS27C040
is also offered with 168 hour burn-in on both temperature ranges (JL4 and JE4 suffixes). (See table below.)
The TMS27PC040 is offered in a 32-lead plastic leaded chip carrier package (FM suffix). The TMS27PC040
is characterized for operation from O°C to 70°C (FML suffix).
FUNCTION
TMS27C040-XXX
TMS27PC040-XXX
SUFFIX FOR OPERATING
TEMPERATURE RANGES
WITHOUT PEP4 BURN-IN
O'CTO 70'C
-40 'C TO 85'C
JL
JE
FML
SUFFIX FOR OPERATING
TEMPERATURE RANGES WITH
PEP4168 HR. BURN-IN
O'CTO 70'C
-40 'C TO 85'C
JL4
JE4
These EPROMs and PROMS operate from a single 5-V supply (in the read mode), and they are ideal for use
in microprocessor-based systems. One other (13 V) supply is needed for programming. All programming signals
are TTL level. For programming outside the system, existing EPROM programmers can be used.
operation
The seven modes of operation are listed in the following table. The read mode requires a single 5-V supply. All
inputs are TTL level exceptfor Vpp during programming (13 V), and VH (12 V) on A9 for the signature mode.
Read
Output Disable
Standby
Programming
Program Inhibit
Verify
E
VIL
VIL
VIH
VIL
VIH
VIH
G
VIL
VIH
x
VIH
VIH
VIL
vPP
VCC
Vcc
Vcc
VPP
Vpp
Vpp
FUNCTION
A9
VCC
X
VCC
x
Vee
x
Vee
X
VCC
X
VCC
X
VCC
Signature Mode
VIL
VIL
VCC
Vec
MODE
VH
AO
X
x
x
X
X
X
VIL
VIH
DOO-D07
Data Out
HI-Z
HI-Z
Data In
HI-Z
Data Out
MFG Code 97
Device Code 50
t X can be VIL or VIH
*VH=12V±0.5V
read/output disable
When the outputs of two or more TMS27C040s or TMS27PC040s are connected in parallel on the same bus,
the output of any particular device in the circuit can be read with no interference from competing outputs of the
other devices. To read the output of a single device, a low level signal is applied to the E and G pins. All other
devices in the circuit should have their outputs disabled by applying a high level signal to one of these pins.
latchup immunity
Latchup immunity on the TMS27C040and TMS27PC040 is a minimum of 250 mA on all inputs and outputs.
This feature provides latchup immunity beyond any potential transients at the P.C. board level when the EPROM
is interfaced to industry standard TTL or MOS logic devices. The input/output layout approach controls latchup
without compromising performance or packing density.
TEXAS
6-72
~
INSTRUMENTS
POST OFFICE BOX 1443· HOUSTON. TEXAS 77001
TMS27C040 4194 304·BIT UV ERASABLE PROGRAMMABLE READ·ONLY MEMORY
TMS27PC040 4194 304·BIT PROGRAMMABLE READ·ONLY MEMORY
SMLS040D-NOVEMBER 199O-REVISED JANUARY 1993
power down
Active lee supply current can be reduced from 50 mA to 1 mA by applying a high TTL input on E and to
100 !AA by applying a high CMOS input on E. In this mode all outputs are in the high impedance state.
erasure (TMS27C040)
Before programming, the TMS27C040 EPROM is erased by exposing the chip through the transparent lid to
a high intensity ultraviolet-light (wavelength 2537 A). The recommended minimum exposure dose (UV intensity
x exposure time) is 15-W·s/cm2 . A typical 12-mW/cm2 , filterless UV lamp will erase the device in 21 minutes.
The lamp should be located about 2.5 cm above the chip during erasure. After erasure, all bits are in the high
state. It should be noted that normal ambient light contains the correct wavelength for erasure. Therefore, when
using the TMS27C040, the window should be covered with an opaque label. After erasure (all bits in logic high
state), logic lows are programmed into the desired locations. A programmed low can be erased only by
ultraviolet light.
Initializing (TMS27PC040)
The one-time programmable TMS27PC040 PROM is provided with all bits in logic high state, then logic lows
are programmed into the desired locations. Logic lows programmed into an OTP PROM cannot be erased.
SNAP! Pulse programming
The TMS27C040 and TMS27PC040 are programmed by using the SNAP! Pulse programming algorithm. The
programming sequence is shown in the SNAP! Pulse programming flow chart (Figure 1).
The initial setup is Vpp =13 V, Vee =6.5 V, E =VIH, and G =VIH' Once the initial location is selected, the data
is presented in parallel (eight bits) on pins 000 through 007. Once addresses and data are stable, the
programming mode is achieved when E is pulsed low (VII) with a pulse duration of tw(PGM)' Every location is
programmed only once before going to interactive mode.
Inthe interactive mode, the word is verified atVpp =13 V, Vee =6.5 V, E =VIH, and G =VIL.lfthe correct data
is not read, the programming is performed by pulling E low with a pulse duration of tw(PGM)' This sequence of
verification and programming is performed up to a maximum of 10 times. When the device is fully programmed,
. all bytes are verified with Vee =Vpp =5 V ± 10%.
program inhibit
Programming may be inhibited by maintaining high level inputs on the E and
G pins.
program verify
Programmed bits may be verified with Vpp
= 13 V when G =VIL. and E =VIH'
signature mode
The signature mode provides access to a binary code identifying the manufacturer and type. This mode is
activated when A9 (pin 26) is forced to 12 V. Two identifier bytes are accessed by toggling AO. All other
addresses must be held low. The signature code for the TMS27C040 is 9750. AO low selects the manufacturer's
code 97 (Hex), and AO high selects the device code 50 (Hex), as shown by the signature mode table below.
PINS
IDENTIFIERt
AD
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQD
MANUFACTURER CODE
VIL
1
0
0
1
0
1
1
1
97
DEVICE CODE
VIH
0
1
0
1
0
0
0
0
50
HEX
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
6·73
TMS27C040 4194 304-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY
TMS27PC040 4194 304-BIT PROGRAMMABLE READ-ONLY MEMORY
SMLS040D-NOVEMBER 199Q-REVISED JANUARY 1993
l
Program
Mode
Increment Address
Increment
Address
Interactive
Mode
Final
Verification
J
Figure 1. SNAPI Pulse Programming Flow Chart
TEXAS ~
INSfRUMENTS
6-74
POST OFFICE BOX 1443· HOUSTON, TEXAS 77001
TMS27C040 4194 304-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY
TMS27PC040 4194 304-BIT PROGRAMMABLE READ-ONLY MEMORY
SMLS040D-NOVEMBER 199O--REVISED JANUARY 1993
logic symbol t
12
0
AO 11
Al
A2
A3
A4
A5
A6
A7
A8
A9
Al0
All
A12
A13
A14
A15
A16
A17
A18
E
10
9
8
7
6
5
27
26
23
25
4
28
29
3
2
30
31
22
EPROM 524 288 x 8
0
A 524287
A'V
A'V
A'V
A'V
A'V
A'V
A'V
A'V
13
14
15
17
18
19
20
21
DOO
DOl
D02
D03
D04
D05
DOS
D07
18
T "-
24 ~
[PWRDWNI
~
EN
t This symbol is in accordance with ANSI/IEEE Std 91·1984 and IEC Publication 617·12.
Pin numbers are for the J package.
TEXAS
~
INBrRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
6·75
TMS27C040 4194 304·BIT UV ERASABLE PROGRAMMABLE READ·ONLY MEMORY
TMS27PC0404194 304·BIT PROGRAMMABLE READ·ONLY MEMORY
SMLS040D-NOVEMBER 1990-REVISED JANUARY 1993
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage range, Vee (see Note 1) .............................................. -0.6 V to 7 V
Supply voltage range, Vpp (see Note 1) ............................................. -0.6 V to 14 V
Input voltage range (see Note 1), All inputs except A9 ............................ -0.6 V to Vee + 1 V
A9 ................................................ -0.6 V to 13 V
Output voltage range, with respect to Vss (see Note 1) ........................... -0.6 V to Vee + 1 V
Operating free-air temperature range ('27C040·__JL and JL4;'27PC040-_ JML) .......... O°C to 70°C
Operating free-air temperature range (,27C040-__JE and JE4) ........................ - 40°C to 85°C
Storage temperature range ....................................................... -65°C to 125°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: Under absolute maximum ratings, voltage values are with respect to GND.
recommended operating conditions
Vee
VPP
Read mode (see Note 2)
Supply voltage
SNAPI Pulse programming algorithm
Read mode
Supply voltage
High-level dc input voltage
VIL
Low-level dc input voltage
TYP
MAX
4.5
5
5.5
6.25
6.5
6.75
Vee- 0.6
SNAPI Pulse programming algorithm
VIH
MIN
12.75
TIL
TA
Operating free-air temperature
'27e040-__JL and JL4
'27pe040-__ FML
TA
Operating free-air temperature
'27e040-
V
V
Vee + 0.6
V
13.25
V
Vee +0.5
V
13
2
UNIT
CMOS
Vee- 0.2
TIL
-0.5
0.8
V
CMOS
-0.5
0.2
V
0
70
'e
-40
85
'e
JE and JE4
Vee + 0.5
NOTE 2: Vee must be applied before or at the same time as VPP and removed after or at the same time as Vpp. The device must not be inserted
into or removed from the board when Vpp or Vee is applied.
electrical characteristics over full ranges of operating conditions
PARAMETER
VOH
High-level dc output voltage
VOL
Low-level dc output voltage
TEST CONDITIONS
MIN
IOH =-400J.lA
2.4
IOH =-20 J.lA
Vee- 0.1
IOL = 2.1 rnA
IOL = 20
J.tA
MAX
UNIT
V
0.4
0.1
V
II
Input current (leakage)
VI = 0 to 5.5 V
:1
10
Output current (leakage)
Vo=OtoVee
±1
IpP1
Vpp supply current
Vpp = Vee = 5.5 V
10
J.tA
J.tA
J.tA
IpP2
Vpp supply current (during program pulse)
Vpp = 12.75V
50
rnA
1
rnA
100
J.tA
50
rnA
lee1
lee2
Vee supply current (standby)
II TIL-Input level
CMOS-Input level
Vee supply current (active)
Vee = 5.5 V, E = VIH
Vee = 5.5V, E = Vee
E = VIL, Vee = 5.5 V
tcycl e = minimum cycle time,
outputs open*
.* Minimum cycle time = maximum access time.
,
TEXAS
~
INSTRUMENTS
6-76
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
TMS27C040 4194 304·BIT UV ERASABLE PROGRAMMABLE READ·ONLY MEMORY
TMS27PC040 4194 304·BIT PROGRAMMABLE READ·ONLY MEMORY
SMLS040D-NOVEMBER 1991HlEVISED JANUARY 1993
capacitance over recommended ranges of supply voltage and operating free-air temperature,
f = 1 MHzt
TYp:t
MAX
Ci
Input capacitance
VI =0
4
8
pF
Co
Output capacitance
VO=O
8
12
pF
PARAMETER
TEST CONDITIONS
MIN
UNIT
t Capacitance measurements are made on sample basIs only.
:t All typical values are at TA = 25'C and nominal voltages.
switching characteristics over full ranges of recommended operating conditions (see Notes 3
and 4)
PARAMETER
TEST CONDITIONS
(SEE NOTES 3 & 4)
'27C/PC040·10
MIN
MAX
'27C/PC040·12
MIN
'27CIPC040·15
MAX
MIN
UNIT
MAX
talA)
Access time from address
100
120
150
talE)
Access time from chip enable
100
120
150
ns
50
50
50
ns
50
ns
1en(G) Output enable time from G
Output disable time from
!dis
G or E, whichever occurs first§
tv(A)
Output data valid time after
change of address, E, or G,
whichever occurs first§
CL = 100 pF,
1 Series 74
TTL load,
Input tr " 20 ns,
Input tf " 20 ns
0
50
0
0
0
50
0
0
ns
ns
§ Value calculated from 0.5-V delta to measured output level.
NOTES: 3. For all switching characteristics the input pulse levels are 0.4 V to 2.4 V. Timing measurements are made at 2 V for logic high and
0.8 V for logic low. (reference AC Testing Wave Form)
4. Common test conditions apply for tdis except during programming.
switching characteristics for programming: Vee = 6.5 Vand Vpp = 13 V (SNAP! Pulse), TA = 25°C
(see Note 3)
PARAMETER
!dis (G)
Output disable time from G
ten (G)
Output enable time from G
MIN
NOM
0
MAX
UNIT
100
ns
150
ns
recommended timing requirements for programming: Vee = 6.5 Vand Vpp = 13 V (SNAP! Pulse),
TA = 25°C, (see Note 3)
tw(pGM)
Program pulse duration
lsu(A)
Address setup time
ISNAPI Pulse programming algorithm
MIN
TYP
MAX
95
100
105
UNIT
j.IS
2
j.IS
tsu(E)
E setup time
2
I-IS
lsu(G)
G setup time
2
j.IS
lsu(D)
Data setup time
2
j.IS
lsu(Vpp)
Vpp setup time
2
I-IS
tsu(VCC)
VCC setup time
2
I-IS
th(A)
Address hold time
0
I-Is
th(D)
Data hold time
2
I-IS
NOTE 3: For all switching characteristics the input pulse levels are 0.4 V to 2.4 V. Timing measurements are made at 2 V for logic high and
0.8 V for logic logic low. (reference AC Testing Wave Form)
TEXAS ~
IN5rRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
6-77
TMS27C040 4194 304·BIT UV ERASABLE PROGRAMMABLE READ·ONLY MEMORY
TMS27PC040 4194 304·BIT PROGRAMMABLE READ·ONLY MEMORY
SMLS0400-NOVEMBER 1990-REVISED JANUARY 1993
PARAMETER MEASUREMENT INFORMATION
2.08 V
Output
Under Test
---JI
RL = 800
Q
CL=100pF
Figure 2. AC Testing Output Load Circuit
AC testing input/output wave forms
2.4 V
0.4 V
-----""V
_____--JA ~.~v
O.!~XII;.._____
AC testing inputs are driven at 2.4 V for logic high and 0.4 V for logic low. liming measurements are made at
2 V for logic high and 0.8 V for logic low for both inputs and outputs.
AO-A18
J
ta(A)
1411
\
E
1
1
1
1
1
\
DQO-DQ7
HI-Z
1
1
«~~~
1
tv(A)
Output Valid
~
INSTRUMENTS
6-78
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
VIH
VIL
~ldls~
1<111
Figure 3. Read Cycle Timing
TEXAS
VIL
1
1
~
1
I
1
~ten(G)~
VIH
}Ii
1
I+--ta(E)~
G
VIL
I
I
~I
1
I
VIH
X
Addresses Valid
~I
I
~ll»-
HI-Z -
:::
TMS27C040 4194 304·BIT UV ERASABLE PROGRAMMABLE READ·ONLY MEMORY
TMS27PC040 4194 304·BIT PROGRAMMABLE READ·ONLY MEMORY
SMLS040D-NOVEMBER 1990-REVISED JANUARY 1993
PARAMETER MEASUREMENT INFORMATION
. .,+. . ,.
=x
1
AO-A18
I
t+---+I- tsu(A)
DQO-DQ7
~
D;ta In Stable
I
Vpp
----.A
1
1
~tsu(VPP)
1
Vee
~~tsU(E)1
1
tw(PGM)
1
1
~
1
X=
I
~
D8t1out
Stable
.1
1
I"
i
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
.1
1
1
1
1
1
~
G
j
I
.1 Iclls(G)
1
1
I..
.1
1
VIH
VIL
14-- th(A)--+1
l~th(D)
\J
1
I"
:
~tsu(Vee)i
E
ten(G)
1
1
1
HI -Z
1
1
1
t1
t+---+I- tsu(D)
Verify
I"
.1
Progrem
I..
1
tsu(G)
VIWVOH
VIIJVOL
vppt
Vee
vee t
Vee
VIH
VIL
1
I
1
VIH
VIL
t 13-V Vpp and 6.5-V Vee for SNAPI Pulse programming.
Figure 4. Program Cyele Timing (SNAP! Pulse Programming)
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443· HOUSTON. TEXAS 77001
6-79
TMS27C040 4194 304·BIT UV ERASABLE PROGRAMMABLE READ·ONLY MEMORY
TMS27PC040 4194 304·BIT PROGRAMMABLE READ·ONLY MEMORY
SMLS040D-NOVEMBER 199Q-REVISED JANUARY 1993
TEXAS ~
INsrRUMENTS
6-80
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
TMS27C240 4194 304·BIT UV ERASABLE PROGRAMMABLE READ·ONLY MEMORY
TMS27PC240 4194 304·BIT PROGRAMMABLE READ·ONLY MEMORY
SMLS240B-NOVEMBER 199G-REVISED JANUARY 1993
•
•
•
•
•
Single 5-V Power Supply
Vpp
All Inputs/Outputs Fully TTL Compatible
100 ns
120 ns
150 ns
16-Blt Output For Use In
Microprocessor-Based Systems
•
Very High Speed SNAP! Pulse
Programming
•
•
•
Power-Saving CMOS Technology
•
•
•
D015
D014
D013
D012
D011
D010
D09
D08
GND*
D07
D06
D05
D04
D03
D02
D01
DOD
Max Access/Min Cycle Time
Vee± 10%
•
1 U 40
E 2
Static Operations (No Clocks, No Refresh)
'27C/PC240-10
'27C/PC240-12
'27C/PC240-15
•
TMS27C240 J PACKAGEt
(TOP VIEW)
Wide·Word Organization ... 256K x 16
3-State Output Buffers
G
400-mV Minimum DC Noise Immunity With
Standard TTL Loads
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
VCC
A17
A16
A15
A14
A13
A12
A11
A10
A9
GND*
A8
A7
A6
A5
A4
A3
A2
A1
AD
TMS27PC240 FN PACKAGEt
(TOP VIEW)
Latchup Immunity of 250 mA on All Input
and Output Lines
"'-till
000
o
No Pull up Resistors Required
~()g~~~:!
> z> « « « «
8
38
9
37
10
36
11
35
12
34
13
33
14
32
15
31
16
30
17
29
18192021 22232425262728
D08
GND*
NC
D07
D06
D05
PEP4 Version Available With 168-Hour
Burn-In, and Choices of Operating
Temperature Ranges
OIW
76 5 4 3 2 1444342 41 4~9
D012
D011
Low Power DIssipation (Vee = 5.5 V)
- Active ... 275 mW Worst Case
- Standby ... 0.55 mW Worst Case
(CMOS-Input Levels)
0
description
80 0
~ 0 81~
00
The TMS27C240 series are 4 194 304-bit,
ultraviolet-light erasable, electrically programmable read-only memories.
~ ~
;;:
~ ~
A13
A12
A11
A10
A9
GND*
NC
A8
A7
A6
A5
:t
t The package shown is for pinout reference only.
The TMS27PC240 series are 4 194 304-bit,
one-time electrically programmable read-only
memories.
PIN NOMENCLATURE
AG-AI7
E
G
These devices are fabricated using power-saving
CMOS technology for high speed and simple
interface with MOS and bipolar circuits. All inputs
(including program data inputs) can be driven by
GND
NC
DOG-DOI5
vcc
vPP
Address Inputs
Chip Enable
Output Enable
Ground
No Connection
Inputs(programmingj/Oulputs
5·VSupply
13·V Power Supply§
* Pins 11 and 30 (J package) and pins 12 and 34 (FN package)
must be connected externally to ground.
§ Only in program mode.
TEXAS
~
Copyright © 1993. Texas Instruments Incorporated
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
6-81
TMS27C240 4194 304-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY
TMS27PC240 4194 304-BIT PROGRAMMABLE READ-ONLY MEMORY
SMLS240B-NOVEMBER 199G-REVISED JANUARY 1993
Series 74 TIL circuits without the use of external pull-up resistors. Each output can drive one Series 74 TIL
circuit without external resistors.
The TMS27C240 EPROM is offered in a dual-in-line ceramic package (J suffix) designed for insertion in
mounting hole rows on 1S,2-mm (600-mil) centers. The TMS27C240 is also offered· with two choices of
temperature ranges of O°C to 70°C (JLsuffix) and - 40°C to 8SoC (JE suffix). The TMS27C240 is also offered
with 168 hour burn-in on both temperature ranges (JL4 and JE4suffixes). (See table below.)
The TMS27PC240 OTP PROM is offered in a 44-lead plastic leaded chip carrier package using 1,2S-mm
(SO-mil) lead spacing (FN suffix). The TMS27PC240 is characterized for a temperature range of O°C to 70°C.
SUFFIX FOR OPERATING
TEMPERATURE RANGES
WITHOUT PEP4 BURN-IN
SUFFIX FOR PEP4
168 HR. BURN-IN
VS TEMPERATURE RANGES
O'CTO 70'C
- 40'C TO 85'C
O'C T070'C
- 40'C TO 85'C
TMS27C240-XXX
JL
JE
JL4
JE4
TMS27pe240-XXX
FNL
FNE
N/A
N/A
These EPROMs and OTP PROMs operate from a single S-V supply (in the read mode), and they are ideal for
use in microprocessor-based systems. One other (13 V) supply is needed for programming. All programming
signals are TIL level. For programming outside the system, existing EPROM programmers can be used.
operation
The eight modes of operation for the TMS27C240 and TMS27PC240 are listed in the following table. The read
mode requires a single 5-V supply. All inputs are TTL level except for Vpp during programming (13 V for SNAP!
Pulse), and 12VonA9forthe signature mode.
FUNCTION
E
Read
VIL
G
Vpp
VCC
A9
AD
I/O
Vce
x
X
000-007
008-0015
Vec
Vce
X
X
HI-Z
Vee
Vee
X
X
HI-Z
VIH
Vpp
Vee
X
X
Data In
Data Out
VIL
Output Disable
VIL
VIH
Standby
VIH
xt
Programming
VIL
Vee
Verify
VIH
vlL
Vpp
Vee
X
X
Program Inhibit
VIH
VIH
Vpp
Vee
X
X
HI-Z
Signature Mode (MIg)
VIL
VIL
Vee
Vcc
VH*
VIL
MIg Code
0097
Signature Mode (Device)
VIL
VIL
VCC
VCC
VH*
VIH
Device Code
0030
t X can be VIL or VIH.
*VH = 12V±0.5V.
read/output disable
When the outputs of two or more TMS27C240s or TMS27PC240s are connected in parallel on the same bus,
the output of any particular device in the circuit can be read with no interference from the competing outputs
of the other devices. To read the output of a single device, a lOW-level signal is applied to the E and G pins. All
other devices in the circuit should have their outputs disabled by applying a high-level signal to one of these pins.
TEXAS ~
INsrRUMENTS
6-82
POST OFFICE BOX 1443· HOUSTON, TEXAS 77001
TMS27C240 4194 304·BIT UV ERASABLE PROGRAMMABLE READ·ONLY MEMORY
TMS27PC240 4194 304·BIT PROGRAMMABLE READ·ONLY MEMORY
SMLS240B-NOVEMBER 199()'-REVISED JANUARY 1993
latchup immunity
Latchup immunity on the TMS27C240 and TMS27PC240 is a minimum of 250 mA on all inputs and outputs.
This feature provides latchup immunity beyond any potential transients at the P.C. board level when the devices
are interfaced to industry-standard TTL or MOS logic devices. Input-output layout approach controls latchup
without compromising performance or packing density.
power down
Active Icc supply current can be reduced from 50 mA to 1 mA by applying a high TTL input on E and to 100 ~
by applying a high CMOS input on E. In this mode all outputs are in the high-impedance state.
erasure (TMS27C240)
Before programming, the TMS27C240 is erased by exposing the chip through the transparent lid to a high
intensity ultraviolet light (wavelength 2537 A). The recommended minimum exposure dose (UV intenSity x
exposure time) is 15-W·s/cm2. A 12-mW/cm2, filterless UV lamp will erase the device in 21 minutes. The
lamp should be located about 2.5 cm above the chip during erasure. After erasure, all bits are in the high
state. It should be noted that normal ambient light contains the correct wavelength for erasure. Therefore,
when using the TMS27C240, the window should be covered with an opaque label.
initializing (TMS27PC240)
The one-time programmable TMS27PC240 PROM is provided with all bits in the logic high state, then logic lows
are programmed into the desired locations. Logic lows programmed into an OTP PROM cannot be erased.
SNAP! Pulse programming
The TMS27C240 and TMS27PC240 are programmed by using the SNAP! Pulse programming algorithm. The
programming sequence is shown in the SNAP! Pulse programming flow chart (Figure 1).
The initial setup is Vpp =13 V, Vee =6.5 V, E =VIH, and G =VIH. Once the initial location is selected, the data
is presented in parallel (eight bits) on pins DOO through D015. Once addresses and data are stable, the
programming mode is achieved when E is pulsed low (VIU with a pulse duration of tw(PGM)' Every location is
programmed only once before going to interactive mode.
In the interactive mode, the word is verified at Vpp = 13 V, Vee = 6.5 V, E = VIH, and G = VIL. If the
correct data is not read, the programming is performed by pulling E low with a pulse duration of
tw(PGM)' This sequence of verification and programming is performed up to a maximum of 10 times.
When the device is fully programmed, all bytes are verified with Vee = VPP = 5 V ± 10%.
program inhibit
Programming may be inhibited by maintaining a high level input on the E and G pins.
program verify
Programmed bits may be verified with Vpp
= 13 V when G =VIL and E =VIH.
TEXAS
~
INsrRUMENTS
POST OFFICE BOX 1443· HOUSTON, TEXAS 77001
6-83
TMS27C240 4194 304·BIT UV ERASABLE PROGRAMMABLE READ·ONLY MEMORY
TMS27PC240 4194 304·BIT PROGRAMMABLE READ·ONLY MEMORY
SMLS240B-NOVEMBER 199~EVISED JANUARY 1993
signature mode
The signature mode provides access to a binary code identifying the manufacturer and type. This mode
is activated when A9 (pin 31 for the J package) is forced to 12 V. Two identifier bytes are accessed by
toggling AO. DOD-D07 contain the valid codes. All other addresses must be held low. The signature code
for these devices is 9730. AO low selects the manufacturer's code 97 (hex). and AO high selects the device
code 30 (hex). as shown by the signature mode table below.
signature modet
IDENTIFIERt
PINS
AO
D07
D06
DOS
D04
D03
D02
D01
DOO
MANUFACTURER CODE
VIL
1
0
0
1
0
1
1
1
97
DEVICE CODE
VIH
0
0
1
1
0
0
0
0
30
t -E =-G =VIL. A9 =VH, A1-A8 =VIL, A10--A17 =VIL, Vpp =VCC, PGM = VIH or VIL.
1ExAs
~
INSTRUMENTS
6-84
POST OFFICE BOX 1443' HOUSTON, TEXAS 77001
HEX
TMS27C240 4194 304·BIT UV ERASABLE PROGRAMMABLE READ·ONLY MEMORY
TMS27PC240 4194 304·BIT PROGRAMMABLE READ·ONLY MEMORY
SMLS240B--NOVEMBER 1990-REVISED JANUARY 1993
Program
Mode
Increment Address
Increment
Address
Interactive
Mode
No
Yes
Device Failed
Fall
Final
Verification
~
Figure 1. SNAP! Pulse Programming Flowchart
TEXAS ~
INsrRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
6-85
TMS27C240 4194 304·BIT UV ERASABLE PROGRAMMABLE READ·ONLY MEMORY
TMS27PC240 4194 304·BIT PROGRAMMABLE READ·ONLY MEMORY
SMLS240B-NOVEMBER 199(}-REVISED JANUARY 1993
logic symbo!t
EPROM 256K x 16
AO
Al
A2
A3
A4
A5
A6
A7
A8
A9
Al0
All
A12
A13
A14
A15
A16
A17
21
22
23
24
25
26
27
28
29
31
32
33
34
35
36
37
38
39
0
>A
19
18
17
16
15
14
13
12
10
9
8
7
6
5
4
3
DOC
DOl
D02
D03
D04
D05
D06
D07
D08
D09
DOlO
D011
D012
D013
D014
D015
17
2
I
20
0
262143
AV
AV
AV
AV
AV
AV
AV
AV
AV
AV
AV
AV
AV
AV
AV
AV
[PWR DWN)
""-
&
EN
tThese symbols are in accordance with ANSI/IEEE Std 91-1984 and lEG Publication 617-12.
Pin numbers are for the J package.
absolute maximum ratings over operating free·air temperature range (unless otherwise noted):!:
Supply voltage range, Vee (see Note 1) .............................................. -0.6 V to 7 V
Supply voltage range, Vpp ......................................................... -0.6 V to 13 V
Input voltage range (see Note 1): All inputs except A9 ............................ -0.6 V to Vee + 1 V
A9 ............................................... -0.6 V to 13.5 V
Output voltage range (see Note 1) ............................................. -0.6 V to Vee + 1 V
Operating free-air temperature range ('27C240-__JL and JL4,
,
'27PC240-_ JNL) ................................ 0° C to 70 0 C
Operating free-air temperature range ('27C240-__JE and JE4) .. ,.................... - 40° C to 85° C
Storage temperature range .......... , ..... ,., ... , ...... ,', ........ ,.............. -65°C to 1500 C
*Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. This is a stress rating only, and
functional operation of the device at these or any other conditions beyond those indicated in the "recommended operating conditions" section
of this specification is not implied, Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to GND.
TEXAS ~
INSTRUMENTS
6-B6
POST OFFICE BOX 1443· HOUSTON, TEXAS 77001
TMS27C240 4194 304·BIT UV ERASABLE PROGRAMMABLE READ·ONLY MEMORY
TMS27PC240 4194 304·BIT PROGRAMMABLE READ·ONLY MEMORY
SMLS240B-NOVEMBER 199(}-REVISED JANUARY 1993
recommended operating conditions
Read mode (see Note 2)
VCC
Supply voltage
Vpp
Supply voltage
VIH
High-level dc input voltage
VIL
Low-level dc input voltage
TA
Operating free-air temperature
TA
Operating free-air temperature
SNAPI Pulse programming algorithm
Read mode
MIN
NOM
MAX
4.5
5
5.5
6.25
6.5
6.75
VCC- 0.6
SNAPI Pulse programming algorithm
TIL
V
VCC+0.6
12.75
13
2
CMOS
UNIT
13.25
VCC+0.5
VCC-0.2
V
V
VCC+0.5
TIL
-0.5
0.8
CMOS
-0.5
0.2
'27C240-__JL, JL4
'27PC240FNL
0
70
·C
'27C240- _JE,JE4
-40
85
·C
V
NOTE 2: VCC must be applied before or atthe same time as VPP and removed after or at the same time as Vpp. The device must not be inserted
into or removed from the board when Vpp or V CC is applied.
electrical characteristics over full ranges of operating conditions
PARAMETER
VOH
High-level dc output voltage
VOL
Low-level dc output voltage
TEST CONDITIONS
MIN
MAX
2.4
10H = - 400 j.tA
V
VCC-O.l
10H = - 20 j.tA
UNIT
IOL=2.1 mA
0.4
IOL=20 flA
0.1
V
II
Input current (leakage)
VI = Oto 5.5 V
±1
flA
10
Output current (leakage)
VO=OtoVCC
±1
j.tA
IpP1
Vpp supply current
Vpp = VCC = 5.5 V
10
flA
IpP2
Vpp supply current (during program pulse)
Vpp= 13V
50
mA
ICC1
VCC supply current (standby)
ITIL-input level
VCC = 5.5 V, E = VIH
I CMOS-input level
VCC=5.5V, E =VCC
1
mA
100
j.tA
50
mA
VCC = 5.5 V, E = VIL,
tcyele = minimum cycle lime,
outputs open
leC2 Vee supply current (active)
capacitance over recommended
temperature, f = 1 MHzt
ranges
of
supply
voltage
and
TYP;
free-air
MAX
UNIT
ei
Input capacitance
VI =0
4
8
pF
Co
Output capacitance
Vo =0
8
12
pF
PARAMETER
TEST CONDITIONS
MIN
operating
tCapacltance measurements are made on a sample basIs only.
; Typical values are at TA = 25'C and nominal voltages.
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
6-87
TMS27C240 4194 304·BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY
TMS27PC240 4194 304-BIT PROGRAMMABLE READ-ONLY MEMORY
SMLS240B-NOVEMBER 1990-REVISED JANUARY 1993
switching characteristics over full ranges of recommended operating conditions (see Notes 3
.
and 4)
PARAMETER
TEST CONDITIONS
(SEE NOTES 3 & 4)
'27C/PC240-10
MIN
MAX
'27C/PC240-12
MIN
MAX
'27C/PC240-15
MIN
MAX
UNIT
talA)
Access time from address
100
120
150
ns
talE)
Access time from chip enable
100
120
150
ns
50
50
50
ns
50
ns
len(G) Output enable time from G
Output disable time from G or
E, whichever occurs firstt
!dis
tv(A)
Output data valid time after
change of address, E, or G,
whichever occurs firstt
CL = 100 pF,
1 Series 74
TTL load,
Input tr " 20 ns,
Input tf " 20 ns
0
50
0
0
50
0
0
0
ns
tValue calculated from 0.5 V delta to measured level. ThiS parameter IS only sampled and not 100% tested.
NOTES: 3. For all switching characteristics the input pulse levels are 0.4 V to 2.4 V. Timing measurements are made at 2 V for logic high and
0.8 V for logic low. (reference AC Testing Wave Form)
4. Common test conditions apply for tdis except during programming.
switching characteristics for programming: Vee = 6.5 Vand Vpp = 13 V (SNAPI Pulse), TA = 25°C
(see Note 3)
PARAMETER
tdis(G)
Output disable time from G
ten (G)
Output enable time from G
MIN
NOM
0
recommended timing requirements for programming: Vee
TA = 25°C, (see Note 3)
MAX
UNIT
100
ns
150
ns
=6.5 V and Vpp =13 V (SNAP! Pulse),
1SNAP! Pulse programming algorithm
MIN
TYP
MAX
95
100
105
UNIT
tw(PGM)
Program pulse duration
tsu(A)
Address setup time
2
flS
tsu(E)
E setup time
2
fls
tsu(G)
G setup time
2
fls
tsu(D)
Data setup time
2
flS
tsu(VPP)
VPP setup time
2
flS
tsu(VCC)
VCC setup time
2
fls
th(A)
Address hold time
0
fls
Data hold time
2
fIS
th(D)
NOTE 3:
For all switching characteristics the input pulse levels are 0.4 V to 2.4 V. Timing measurements are made at 2 V for logiC high and
0.8 V for logic low. (reference AC Testing Wave Form)
TEXAS
~
INSTRUMENTS
6-88
flS
POST OFFICE BOX 1443· HOUSTON. TEXAS 77001
TMS27C240 4194 304·BIT UV ERASABLE PROGRAMMABLE READ·ONLY MEMORY
TMS27PC240 4194 304·BIT PROGRAMMABLE READ·ONLY MEMORY
SMLS240B-NOVEMBER 199(}-REVISED JANUARY 1993
PARAMETER MEASUREMENT INFORMATION
2.0SV
RL = SOO Q
Output
Under Test - - .
T
CL=100pF
Figure 2. AC Testing Output Load Circuit
AC testing input/output wave forms
2.4 V
0.40 v
-----""""'"'Vr'
_ _ _ _ _---JA
2V
O.S v
A.C. testing inputs are driven at 2.4 V for logic high and 0.4 V for logic low. Timing measurements are made at
2 V for logic high and 0.8 V for logic low for both inputs and outputs.
AO-A17
x
1
1
1
I
G
1
1
1
1
1
1
1
VIL
1
1
\,
.
,
talE)
1
1
1
.1
«««
VIL
1 1
1 1
1 1
--+i
\
HI-Z
VIH
YT
ten(G) :..
talA)
I..
OQO-OQ15
VIH
X
Address Valid
VIH
0
1
I
I"
VIL
I.. .1
·1
Output
Valid
.1 tdls
1 tv(A)
VOH
2t}-HI-ZVOL
Figure 3. Read Cycle Timing
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
6-89
TMS27C240 4194 304·BIT UV ERASABLE PROGRAMMABLE READ·ONLY MEMORY
TMS27PC240 4194 304·BIT PROGRAMMABLE READ·ONLY MEMORY
SMLS240B-NOVEMBER 1990-REVISED JANUARY 1993
PARAMETER MEASUREMENT INFORMATION
.,
Verify
14
Program
14
I
AD-A17
=x:
I
~tsu(A)
OQD-OQ15
~
o;ta In Stable
I
~tsu(O)
1
Vpp
----1'1'
1
1
1
~leu(VPP)
1
Vee
--.J~
1
~
E
k=
Address Stable
I
tsu(E)
J
1
tsu(Vee)1
\J
1
1
tw(PGM) ~
1
1
1
j-HI-Z 1
1
.1
I' ten(G) 14
1
1
1
1
I
1
1
1
1
1
1
1
1
1
1
1 th(O)
1
1
1
1
1
1
1
.1 1 tsu(G)
14
1 1
1
1 1
~
~
G
.1
1
I
oatj Out
Stsble
I
14
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
j
1
.1 lctls(G)
Figure 4. Programming Cycle Timing (SNAP! Pulse Programming)
..If
INSTRUMENTS
6-90
VIL
~th(A)--+1
t 13-V Vpp and 6.5-V Vee for SNAPI Pulse programming.
TEXAS
VIH
POST OFFICE BOX 1443· HOUSTON. TEXAS 77001
VUi/VOH
Vn'/VOL
vppt
Vee
Vee t
Vee
VIH
VIL
VIH
VIL
TMS27C400 4194 304-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY
TMS27PC400 4194 304-BIT PROGRAMMABLE READ-ONLY MEMORY
SMLS400A-OCTOBER 1992-REVISED JANUARY 1993
TMS27C400
• Word-Wide (256K x 16) or
Byte-Wide (512K x 8) Conflgurable
J AND N PACKAGES
(TOP VIEW)
• 4-Megablt Mask ROM Compatible
- 40-Lead CERDIP Package
- 40-Lead PDIP Package
•
•
•
•
A17
A7
Single 5-V Power Supply
All Inputs/Outputs Fully TTL Compatible
Static Operation (No Clocks, No Refresh)
Max Access/Min Cycle Time
Vee ± 10%
'27C/PC400-10
100 ns
'27C/PC400-12
120 ns
'27C/PC400-15
150 ns
• Very High Speed SNAPI Pulse
Programming
E
GND
G
DOO
D08
D01
D09
D02
D010
D03
D011
• Power-Saving CMOS Technology
• 3-State Output Buffers
• 400-mV Guaranteed DC Noise Immunity
With Standard TTL Loads
• Latchup Immunity of 250 mA on All Input
and Output Lines
• No Pullup Resistors Required
• Low Power Dissipation (Vee = 5.5 V)
- Active .•. 275 mW Worst Case
- Standby •.. 0.55 mW Worst Case
(CMOS-Input Levels)
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
A8
A9
A10
A11
A12
A13
A14
A15
A16
BYTE/Vpp
GND
D015/A-1
D07
D014
D06
D013
D05
D012
D04
z
o
-t(
:E
a::
Vee
o
LL
Z
PIN NOMENCLATURE
AO-A17
E
G
• PEP4 Version Available With 168-Hour
Burn-In, and Choices of Operating
Temperature Ranges
GND
DOO-D014
DOI5/A-l
BYTE
VCC
VPP
Address Inputs
Chip Enable
Output Enable
Ground
Inputs (Programming)/Outputs
Input (Programming). Output (Word-Wide
Read Mode), Byte Select (Byte-Wide Read
Mode)
Word/Byte Enable
5-V Supply
13-V Power Supply (Program Mode Only)
description
The TMS27C400 is a 4 194 304-bit ultraviolet-light erasable, electrically programmable read-only memory,
organized as 262 144 words of 16 bits each. A byte enable switch allows the device to be addressed as a
524 288 x 8-bit device. The TMS27C400 is pinout and functionally compatible with 40-pin 4-megabit Mask
ROMs.
.
The TMS27PC400 is a 4 194 304-bit, one-time electrically programmable (OTP) read-only memory, organized·
as 262 144 words of 16 bits each. A byte enable switch allows the device to be addressed as a 524 288 x 8-bit
device. The TMS27PC400 is pinout and functionally compatible with 4-megabit Mask ROMs in a 40-pin
dual-in-line plastic package (N suffix).
These devices are fabricated using power-saving CMOS technology for high speed and simple interface with
MaS and bipolar circuits. All inputs (including program data inputs) can be driven by Series 74 TTL circuits
without the use of external pull-up resistors. Each output can drive one Series 74 TTL circuit without external
resistors.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443· HOUSTON. TEXAS 77001
Copyright © 1993, Texas Instruments Incorporated
6-91
W
o
Z
c~
o
~
z
o
m
-z
"T1
ol:I
s:
~
o-z
1ExAs ."
INSTRUMENTS
6·94
POST OFFICE BOX 1443' HOUSTON, TEXAS 77001
TMS27C400 4194 304-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY
TMS27PC400 4194 304-BIT PROGRAMMABLE READ-ONLY MEMORY
SMLS400A-OCTOBER 1992-REVISED JANUARY 1993
l
Vee = 6.5 V, BYTE / Vpp = 13 V
Program One Pulse = tw = 100 I-IS
Program
Mode
Increment Address
No
z
o
~
==
a:
Increment
Address
ou.
Interectlve
Mode
z
w
o
z
~
c
c
z~
o
BYTE/Vpp
A-1
10
m
o
:xJ
s:
~
o
°
> A 262°143
A'il
A'il
A'il
A'il
A'il
A'il
A'il
A'il
A'il
A'il
A'il
A'il
A'il
A'il
A'il
A'il
13
15
17
19
22
24
26
28
14
16
18
20
23
25
27
29
DQO
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
17
[PWRDWNI
12~ M E N
-z
."
9
8
7
6
5
4
3
2
40
39
38
37
36
35
34
33
32
1
31
29
t This symbol is in accordance with ANSI/IEEE Std 91-1984 and lEe Publication 617-12.
Pin numbers shown are for the J package.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted):!:
Supply voltage range, Vee (see Note 1) ................... . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.6 V to 7 V
Supply voltage range, BYTE / Vpp .................................................. -0.6 V to 14 V
Input voltage range (see Note 1), All inputs except A9 ................................ -0.6 V to 6.5 V
A9 .............................................. -0.6 V to 13.5 V
Output voltage range (see Note 1) ............................................. -0.6 V to Vee + 1 V
Operating free-air temperature range ('27C400__JL and JL4,
'27PC400__NL and NL4) ........................ O°C to 70°C
Operating free-air temperature range ('27C400__JE and JE4,
'27PC400__NE and NE4) .................... - 40°C to 85°C
Storage temperature range ....................................................... -65°C to 125°C
z
*Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. This is a stress rating only, and
functional operation ofthe device at these or any other conditions beyond those indicated in the "recommended operating conditions" section of
this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to GND.
TEXAS
~
INSIRUMENTS
6-96
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
TMS27C400 4194 304-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY
TMS27PC400 4194 304-BIT PROGRAMMABLE READ-ONLY MEMORY
SMLS400A-OCTOBER 1992-REVISED JANUARY 1993
recommended operating conditions
TMS27C/PC400-10
TMS27C/PC400-12
TMS27C/PC400-15
MIN
Read mode (see Note 2)
Supply voltage
VCC
BYTE/Vpp
Supply voltage
High-level input voltage
VIL
Low-level input voltage
4.5
5
5.5
6.25
6.5
6.75
Read mode (WORD)
Read mode (BYTE)
(see Note 3)
VIH
-0.5
NOTES:
TIL
V
VCC + 0.5
VIL
12.75
VCC+0.5
VCC-0.2
V
13.25
13
2
CMOS
Operating free-air temperature
TA
UNIT
MAX
SNAP! Pulse Programming algorithm
SNAPI Pulse Programming algorithm
VIH
NOM
VCC+0.5
V
TIL
-0.5
0.8
CMOS
-0.5
0.2
'27C400__JL, JL4
'27PC400__ NL, NL4
0
70
°c
'27C400__JE, JE4
'27PC400__NE, NE4
-40
85
°c
V
2. VCC must be applied before or at the same time as BYTE/ Vpp and removed after or at the same time as BYTE / Vpp. The device
must not be inserted into or removed from the board when BYTE / Vpp or VCC is applied.
3. BYTE / Vpp can be connected to VCC directly (except in the program mode). VCC supply current in this case would be ICC + Ipp.
During programming BYTE / Vpp must be maintained at 13 V ± 0.25 V.
electrical characteristics over full ranges of operating conditions
PARAMETER
VOH
VOL
TEST CONDITIONS
MIN
10H ;-2.5 mA
High-level output voltage
10H ; - 20
Low-level output voltage
J.tA
MAX
2.4
UNIT
10L; 2.1 mA
0.4
10L; 20 I!A
0.1
V
IpPl
BYTE / Vpp operating current
BYTE /Vpp; VCC; 5.5 V
10
!!A
J.tA
!!A
IpP2
Vpp supply current (during program pulse)
BYTE / Vpp ; 13 V
50
mA
ICCI
VCC supply current (standby)
II
Input current (leakage)
VI; Oto 5;5 V
±1
10
Output current (leakage)
Vo;OtoVCC
±1
ICC2
I TIL-input level
VCC ; 5.5 V, E ; VIH
I CMOS-input level
VCC; 5.5 V, E ; VCC
VCC ; 5.5 V, E ; VIL
icycles ; 5 MHz
outputs open
VCC supply current (active)
1
mA
100
J.tA
50
mA
capacitance over recommended ranges of supply voltage and operating free-air temperature,
f = 1 MHzt
TYpt
MAX
Ci
Input capacitance
VI =0
4
8
pF
Co
Output capacitance
VO;O
8
12
pF
CBYTE/VPP
BYTE/ Vpp capacitance
BYTE /Vpp; 0
18
25
pF
PARAMETER
TEST CONDITIONS
MIN
UNIT
t Capacitance measurements are made on a sample basis only.
tTypical values are at TA = 25°C and nominal voltages.
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
~
~
a::
o
u.
z
w
V
VCC- 0.1
z
o
6-97
o
z
~
c
«
TMS27C400 4194 304·BIT UV ERASABLE PROGRAMMABLE READ·ONLY MEMORY
TMS27PC400 4194 304·BIT PROGRAMMABLE READ·ONLY MEMORY
SMLS400A-OCIOBER 1992--REVISED JANUARY 1993
switching characteristics over full ranges of recommended operating conditions (see Notes 4
and 5)
TEST
CONDITIONS
(SEE NOTES 4, 5, & 6)
»
c
z~
o
m
--nz
o
~
o
z
'27C/PC400·12
'27C/PC400·15
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
talA)
Access time from address
100
120
150
tatE)
Access time from chip enable
100
120
150
ns
len (G)
Output enable time from G
50
50
50
ns
idis
Output disable time from G or E,
whichever occurs firstt
50
ns
tv(A)
Output data valid time
after change of address, E, or G,
whichever occurs firstt
=
CL 100 pF,
1 Series 74
TIL load,
Input t( .. 20 ns,
Input tf .. 20 ns,
50
0
0
0
0
50
0
0
ns
ns
t Value calculated from 0.5 V delta to measured level. This parameter is only sampled and not 100% tested.
NOTES: 4. For all switching characteristics the input pulse levels are 0.4 V to 2.4 V. Timing measurements are made at 2 V for logic high and
0.8 V for logic low. (reference AC Testing Wave Form)
5. Common test conditions apply for tdis except during programming.
6. talA) includes access time from DOI5/A·l in Byte Wide Read Mode.
switching characteristics for programming: Vee
TA = 25°C (see Note 4)
=6.5 V and BYTENpp =13 V (SNAP! Pulse),
MIN
PARAMETER
lctis(G)
Output disable time from G
len (G)
Output enable time from G
NOM
0
MAX
UNIT
100
ns
150
ns
recommended timing requirements for programming: Vee = 6.5 V and BYTENpp = 13 V
(SNAP! Pulse), TA = 25°C (see Note 4)
::D
3:
'27C/PC400·10
PARAMETER
ISNAPI Pulse programming algorithm
MIN
TYP
MAX
95
100
105
UNIT
tw(PGM)
Program pulse duration
tsu(A)
Address setup time
2
tsu(E)
E setup time
2
I'S
lsu(G)
G setup time
2
I'S
tsu(D)
Data setup time
2
I'S
tsu(VPP)
BYTE / VPP setup time
2
I'S
tsu(VCC)
VCC setup time
2
I'S
th(A)
Address hold time
0
I's
th(D)
Data hold time
2
I's
. .
..
!AS
!AS
NOTE 4. For all sWitching charactensllCs the Input pulse levels are 0.4 V to 2.4 V. Timing measurements are made at 2 V for logic high and
0.8 V for logic low. (reference AC Testing Wave Form)
TEXAS
~
INSTRUMENTS
6-98
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
TMS27C400 4194 304·BIT UV ERASABLE PROGRAMMABLE READ·ONLY MEMORY
TMS27PC400 4194 304·BIT PROGRAMMABLE READ·ONLY MEMORY
SMLS400A-OCTOBER 1992-REVISED JANUARY 1993
PARAMETER MEASUREMENT INFORMATION
2.08 V
~
Output
Under Test
T
RL=800Q
eL=100pF
Figure 2. AC Testing Output Load Circuit
AC testing Input/output wave forms
2.4V
_____..;v
A ~.~
O.4V
D.! ~X""
V
_____
z
A.C. testing inputs are driven at 2.4 V for logic high and 0.4 V for logic low. Timing measurements are made at2Vfor logic high and O.BVfor logic
low for both inputs and outputs.
o
-
~
::!
[t
141.----- Verlfy ----.~I
:~.--- Program ----I.~I
I
AO-A17
~
Stable
- v . 1 ' - -_ _ _ _ _ _ _Address
_....,..!_
_________
I
,
,
J+---+I- tsu(A)
000-0014,
0015/A-1
_--<,t ~
---1::
o~ta In Stable
~ tau(O)
I
BVTE/Vpp
~ tsu(VPP)
I
--'~IAr-
I
I
Z
Vpp
o
z
~
c
w
14----- th(A) - ' 1
--<\
HI-Z
ten (G)
VVIILH
I
,,---'
T -+: 'I oSatta~bOleut
i :;>---:I
·1
,. .1
::
:
I'
,
o
LL
I,.
I
.
I
I
I
ldls(G)
Scope Diary
TMS29F816
Flash EEPROM
2K x8
TMS
TOI
TOOV
t This symbol is in accordance with ANSI/IEEE Std 91-1984 and lEe Publication 617-12-1991.
TEXAS
~
INsrRUMENTS
6-102
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
12
TOO
TMS29F816
16 384·BIT SCOPETM DIARY
JTAG ADDRESSABLE STORAGE DEVICE
SMJS816B-NOVEMBER 199Q-REVISED JANUARY 1993
functional block diagram
2Kx 8
Flash EEPROM
Memory Core
DOUT
ADDRESS
~~-;;T---Sequence
I
~e.!!c:!?!:..... ~
Lockblts
___ _
Page Programming Buffer
DLA
Device-Identification
Register
DLB
Bypass Register
TDI--~~--~~-----------------t
INSTRUCTION 8 ~----------------.-I
Instruction Register
TMS
TAP
TCK
Terminal Functions
PIN
NAME
PIN#
I/O
DESCRIPTION
TMS
3
I
Test Mode Select. Controls transition ofTAP finite state machine. This input is sampled on the rising edge
ofTCK.
TCK
4
I
Test Clock. Input clock to TAP finite state machine. All changes in state are synchronous to the test clock
TCK.
TDI
6
I
Test Data In. Data input to the internal register scan path. Data on this pin is sampled on the rising edge
of TCK.
TOO
12
0
Test Data Out. Data output from the internal register scan path. Data is updated on this pin on the falling
edge of TCK.
DLA
13
I
Disable Lock A. Controls lockbit functionality for memory array block O. When DLA =VIL, the state of lockbit 0 (LCKO) determines whether block 0 can be erased or programmed. When DLA =VIH, block 0 can
be erased or programmed regardless of the state of 10ckbitO. When DLA =VH (VH» VCC) , the SCOPE
Diary enters a special manufacturing test mode.
DLB
15
I
Disable Lock B. Controls lockbit functionality for memory blocks 1, 2, and 3. When DLB =VIL, the states
of lockbits 1,2, and 3 (LCK1, LCK2, LCK3) determine whether their respective blocks (1, 2, and 3) can
be erased or programmed. When DLB =VIH, blocks 1,2, and 3 can be erased or programmed, regardless
of the state of their associated lockbits.
VCC
GND
16
7
I
-5-V Power Supply. (± 10% operating power supply connection.)
I
Ground reference
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443· HOUSTON, TEXAS 77001
6-103
TMS29F816
16 384·BIT SCOPE™ DIARY
JTAG ADDRESSABLE STORAGE DEVICE
SMJS816B--NOVEMBER 1990-REVISED JANUARY 1993
Internal registers
Note that the most significant bit is farthest from the output (TDO) in all internal registers.
Instruction
The instruction register is an a-bit shift register with parallel inputs to monitor the SCOPE Diary status. The most
significant bit (7) is a parity bit. The SCOPE Diary status is loaded into the instruction register during the
Capture-IR controller state (see Figure 1). During the Shift-IR state, the status bits are shifted out as a new
SCOPE Diary instruction is scanned into the instruction register.
0
7
6
5
4
3
2
IRP
PlEBS
SSS
LMS
VMS
PIECES
0
R_1 t
R-o
R-o
tR = Read, -n = Value after reset
R-o
R-o
R-o
R-O
Bltl
I
Bit 0:
Always loaded with 1.
Bit 1:
Always loaded with 0
Bit 2:
R-1
PIECES - Program/Erase Contention Error Status
No error detected.
1 = Attempt to write to SCOPE Diary during busy state.
o=
Bit 3:
VMS - Verify Mode Status
= Normal operating mode.
1 = SCOPE Diary is in either program-verify or erase-verify mode.
Bit 4:
LMS - Lock Mode Status
o = Normal operating mode.
1 = SCOPE Diary is in lockbit mode.
Bit 5:
Bit 6:
Bit 7:
o
SSS - Software Sequence Status
Normal operating mode.
1 = Valid software sequence detected. The bit will be set within 2 fAs after the SCOPE Diary
detects a valid software sequence. The bit will remain set until one of the following occurs:
a) The sequence timer expires.
b) The active program or erase cycle is complete.
c) The CLRSWS command is issued.
o
PlEBS - Program/Erase Busy Status
Normal operating mode.
1 = Busy state. The SCOPE Diary is executing a self-timed program or erase operation. The bit
will be set within 2 fAs after the BEGOPS instruction is executed. This bit will remain set until
the operation is complete.
o
IRP - Instruction Register Parity
All valid commands to the instruction register are even parity.
Parity error detected in previously loaded instruction. The SCOPE Diary will automatically
place the BYPASS register into the data register scan path.
No parity error in previously loaded instruction.
o
Figure 1. Instruction Register Status
TEXAS
~
INSTRUMENTS
6-104
POST OFFICE BOX 1443· HOUSTON. TEXAS 77001
TMS29F816
16 384·BIT SCOPE™ DIARY
JTAG ADDRESSABLE STORAGE DEVICE
SMJS816B-NOVEMBER 1990--REVISED JANUARY 1993
boundary-scan
The boundary-scan register is a 2-bit register. Bit 0 of this register is connected to OLA; bit 1 is connected to
OLB. This register can only be used to sample the connected inputs; therefore, values stored in the
boundary-scan register during the Update-DR controller state will not be applied to the internal core logiC.
device-identification
The device identification register returns the following 32-bit code when interrogated with the 10COOE
command: 0000102Fh. The device 10 register is selected into the scan path during power-on reset or upon
entering the Test-Logie-Reset state.
bypass
The bypass register is a 1-bit register. It allows data to transfer from TOI to TOO in one TCK clock cycle. The
bypass register is selected into the scan path when a parity error is detected during the Shift-IR state.
memory-data
The memory-data register is an 8-bit register used to load data into the memory array during write operations.
This register is also used to sample data from the memory array during read operations. The parallel-scan load
path is connected to the memory core data outputs. The output of the register latch is connected to the data input
of the memory core. The operation of the register is shown in Table 1.
Table 1. Memory-Data Register Operation
Opcode
Capture-DR
Shift-DR
Update-DR
DMARD
Memory Data to Scan
Data Stream from Array
Scan to Register Latch
DMAWR
Memory Data to Scan
Data Stream to Array
Scan to Register Latch
BYTERD
Memory Data to Scan
Normal Shift Operation
Scan to Register Latch
BYTEWR
Memory Data to Scan
Normal Shift Operation
Scan to Register Latch
ISTEST
Register Latch to Scan
Normal Shift Operation
Scan to Register Latch
memory-address
The memory-address register is a 16-bit register used to address the Flash EEPROM array during read and
write operations. Bits 10 - 0 are used to address the Flash memory array. Bits 14 - 0 are used to address the
software sequence detector. The operation of the register is shown in Table 2.
Table 2. Memory-Address Register Operation
Opcode
Capture-DR
Shift-DR
Update-DR
LDADDR
Register Latch to Scan
Normal Operation
Scan to Register Latch
DMARD
Hold
Auto-Increment
Hold
DMAWR
Hold
Data Stream to Array
Hold
BYTERD
Register Latch to Scan
Normal Operation
Scan to Register Latch
BYTEWR
Register Latch to Scan
Normal Operation
Scan to Register Latch
ISTEST
Register Latch to Scan
Normal Operation
Scan to Register Latch
TEXAS
~
INSIRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
6-105
TMS29F816
16 384-BIT SCOPE™ DIARY
JTAG ADDRESSABLE STORAGE DEVICE
SMJS816B-NOVEMBER 199o-REVISED JANUARY 1993
page programming buffer
, The programming pages begin on 32-byte boundaries. Data being written to the SCOPE Diary is stored in the
32-byte page programming buffer until the memory-array programming cycle begins. The page buffer address
mechanism does not automatically recognize page programming buffer loads that cross a page boundary. Bits
10 - 5 of the last address presented to the page programming buffer will be used as the page pointer when the
memory array programming cycle begins. After an initial data value is loaded into the page programming buffer,
all remaining bytes within the page programming buffer are initialized to FFh.
erase-select
The erase-select register is a 4-bit register used to select the Flash memory block(s) that will be erased during
an erase cycle. Each bit in the register maps to one of the memory blocks (see Figure 2). To select a block for
erasure, set the block's corresponding memory-control bit to logic 1. The operation of the register is shown in
Table 3.
BIU r -_ _.......;3::...-_ _...,...._ _ _..:2=--_ _...,...._ _ _....:.._ _---,r-_ _......::O_ _ _.,
Block 3
Rw~t
t R =Read,
Bit 0:
Bit 1:
Bit 2:
Bit 3:
W
=Write,
-n
Block 2
Block 1
Block 0
RW~
RW~
RW~
=Value after reset
Block 0 Erase Enable (address 0000 - 007F)
o =Erase disable
1 =Erase enable
Block 1 Erase Enable (address 0080 - 01 FF)
o = Erase disable
1 =Erase enable
Block 2 Erase Enable (address 0200 - 03FF)
o = Erase disable
1 = Erase enable
Block 3 Erase Enable (address 0400 - 07FF)
o = Erase disable
1 =Erase enable
Figure 2. Erase-Select Register
Table 3. Erase-Select Register Operation
Opcode
Capture-DR
Update-DR
ERABLK
Register Latch to Scan
Scan to Register Latch
ISTEST
Register Latch to Scan
Scan to Register Latch
TEXAS
~
INSTRUMENTS
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TMS29F816
16 384-BIT SCOPE™ DIARY
JTAG ADDRESSABLE STORAGE DEVICE
SMJS816B--NOVEMBER 199o-REVISED JANUARY 1993
lockbits
The lockbit register contains four one-time-programmable, non-erasable bits. The lockbits map one-to-one to
the blocks in the array (bit 0 maps to block 0). The lockbit register is not located on the scan path; it is internal
to the memory core. It can be accessed using the memory-address and memory-data registers.
To prevent a block from being programmed or erased, program a logic 0 in the block's corresponding bit position.
Read and write operations to the lockbits are selected by the SETLOCK instruction. To program the lockbits,
execute the DMAWR or BYTEWR instruction sequences while in the lock mode. The lockbit register is shown
in Figure 3.
Bill
2
Block 3
Block 2
Block 1
Block 0
RW-1
RW-1
RW-1
RW-1
t R = Read,
Bit 0:
o
3
t
W = Write, -n = Initial value
Block 0 Lock Enable (address 0000 - 007F)
o =Block program and erase disable
1 =Block program and erase enable
Bit 1:
Bit 2:
Block 1 Lock Enable (address 0080 - 01 FF)
o =Block program and erase disable
1 =Block program and erase enable
Block 2 Lock Enable (address 0200 - 03FF)
o =Block program and erase disable
1 = Block program and erase enable
Bit 3:
Block 3 Lock Enable (address 0400 - 07FF)
o =Block program and erase disable
1 =Block program and erase enable
Figure 3. Lockbit Register
header
The header register is an 8-bit register used to control the mode of operation during a DMAWR instruction. The
register is cleared to zero on power up and upon entering the Test-Logie-Reset state. When the register is
cleared (all bits to logic 0), the SCOPE Diary uses a state-transition mode to synchronize the DMA write
operation. If the register is not cleared, the contents will be used as a shift data input pattern match to
synchronize the start of the DMA write operation.
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INSTRUMENTS
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TMS29F816
16 384-BITSCOPETM DIARY
JTAG ADDRESSABLE STORAGE DEVICE
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Test-Logic Reset
TMS=L
TMS=H
~----".
Run-Test/Idle
Figure 4. TAP State Diagram
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16 384-BIT SCOPE ™ DIARY
JTAG ADDRESSABLE STORAGE DEVICE
SMJS816B-NOVEMBER 1990-REVISED JANUARY 1993
TAP state diagram description (see Figure 4)
The SCOPE Diary TAP controller accepts TCK and TMS signals compatible with I EEE Standard 1149.1. There
are six stable states (indicated by a looping arrow) and ten transient states (indicated by two exiting arrows) in
the diagram. A stable state is defined as a state the TAP can retain for consecutive TCK cycles. Any other state
is a transient state.
There are two main paths through the state diagram; one accesses selected data registers, and one accesses
the instruction register.
Test-Loglc-Reset
In this state, the test logic is inactive, and an internal reset signal is applied to all registers in the SCOPE Diary.
During SCOPE Diary operation, the TAP returns to the Test-Logic-Resetstate in no more than five TCK cycles
ifTMS is high. The TMS pin has an internal pullupthatforces itto a high level when it is left unconnected or when
a board defect causes it to be open-circuited.
Run-Test/Idle
The TAP must pass through this state before executing any test operations. The TAP may retain this state
indefinitely. No registers are modified while the SCOPE Diary is in the Run-Test/Idle state.
Select-DR-Scan, Select-IR-Scan
No specific function is performed in these states. TAP exits them on the next TCK cycle.
Capture-DR
Selected data registers are placed in the scan path (between TDI and TDO). The current instruction determines
whether or not the data is loaded or captured into the scan path. The TAP exits the state on the rising edge of
TCK.
Shift-DR
In this state, data is shifted serially through the selected data registers, from TDI to TDO, on each TCK cycle.
The first shift occurs after the first TCK cycle after entering this state. (No shifting occurs during the TCK cycle
in which the TAP changes from Capture-DR to Shift-DR or from Exit2-DR to Shift-DR.)
In Shift-DR, on the falling edge of TCK, TDO goes from the high-impedance state to the active state. If the TAP
has not passed through the Test-Logie-Reset state since the last scan operation, TDO enables to the level
present before it was last disabled. If the TAP has passed through the Test-Logie-Reset state since the last
operation, TDO enables to a high level.
Exit1-DR, Exit2-DR
These are temporary states used to end the shifting process. It is possible to return to the Shift-DR state from
either Exit1-DR or Exit2-DR without recapturing the data registers. TDO changes from the active state to the
high-impedance state on the falling edge of TCK as the TAP changes from Shift-DR to Exit1-DR.
Pause-DR
The TAP can remain in this state indefinitely. The Pause-DR state allows you to suspend and resume shift
operations without losing data.
Update-DR
In the Update-DR state, the current instruction determines whether or not the latches in the selected data
registers are updated with data from the scan path.
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TAP state diagram description (continued)
Capture-IR
In the Capture-fR state, the instruction register is preloaded with the IR status word, and then it is placed in the
scan path. The TAP exits the state on the rising edge of TCK.
Shift-IR
In this state, data is shifted serially through the instruction register, from TOI to TOO, on each TCK cycle. The
first shift occurs after the first TCK cycle after entering this state. (No shifting occurs during the TCK cycle in
which the TAP changes from Capture-fRto ShifHR or from Exit2-fRto Shift-fR.) In Shift-fR, on the falling edge
of TCK, TOO goes from the high-impedance state to the active state.
Exit1-IR, Exit2-IR
These are temporary states used to end the shifting process. It is possible to return to the Shift-fR state from
either Exit1-fR or Exit2-fR without recapturing the instruction register. TOO changes from the active state to the
high-impedance state on the falling edge of TCK as the TAP changes from Shift-fRto Exit1-fR.
Pause-IR
The TAP can remain in this state indefinitely. The Pause-fR state allows you to suspend and resume shift
operations without losing data.
Update-IR
In the Update-fRstate, the instruction register latches are updated with the new instruction from the scan path.
instructions
standard SCOPE instructions
The SCOPE Diary supports a subset of the standard SCOPE instruction set. The defined instructions are shown
in Table 4. All other SCOPE instructions select the default BYPASS instruction.
Table 4. Standard SCOPE Instructions
Opcode
Code
BYPASS
FFh
Select Bypass Register
Description
External Boundary Test (see Note 1)
EXTEST
OOh
IDCODE
81h
ID Register Scan
SAMPLE
82h
Boundary Sample
NOTE 1: DUring operation. the EXTEST Instruction behaves Identically to the SAMPLE InstrucliOn.
SCOPE Diary-specific instructions
The SCOPE Diary supports specific instructions to control the operation of the Flash EEPROM array. The
defined instructions are shown in Table 5. All undefined opcodes select the BYPASS instruction.
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16 384-BIT SCOPETM DIARY
JTAG ADDRESSABLE STORAGE DEVICE
SMJS816B-NOVEMBER 1990--REVISED JANUARY 1993
Table 5. SCOPE Diary-Specific Instructions
Opcode
Code
BEGOPS
69h
Begin Operation in Progress
Description
Byte Read
BYTERD
63h
BYTEWR
E4h
Byte Write
CLRERR
6Ah
Clear Conflict Error Flag
CLRLOCK
66h
Exit Lock Mode
CLRSWS
EBh
Clear Software Sequence
DMARD
Elh
DMARead
DMAWR
E2h
DMAWrite
ERABLK
E7h
Erase Block Register Select
ISTEST
6Ch
Internal Self Test
LDADDR
60h
Load Address Register
LOADHDR
EBh
Header Register Select
SETLOCK
65h
Enter Lock Mode
BEGOPS
Begin Operation in Progress
Scan Path
TOI
--+
bypass
--+
TOO
Description The BEGOPS instruction is used to initiate a program, erase, or verify mode operation after the
appropriate software sequence has been issued. This instruction must be executed within 9 ms of the
last write operation, and the software sequence status bit in the instruction register must be set, or the
selected operation will not begin. If the time-out condition is not met, the software sequence commands
must be re-issued. Once the BEGOPS instruction is loaded, it is not executed until the diary is placed
in the Run-Test/Idle state.
BYPASS
Scan Path
Select Bypass Register
TOI --+ bypass --+ TOO
Description The BYPASS instruction conforms to the 1149.1 BYPASS instruction. The one-bit bypass register is
selected in the scan path. A logic 0 is loaded in the bypass register during the Update-DR state.
BYTERD
Byte Read
Scan Path
TOI
--+
memory-data
--+
memory-address
--+
TOO
Description The BYTERO instruction is used to read the value stored in a memory array location. Ouring the read
operation, the contents of the memory-address register point to the value. This value is captured in the
memory-data register during the Update-DR state.
BYTEWR
Byte Write
Scan Path
TOI
--+
memory-data
--+
memory-address
--+
TOO
Description The BYTEWR instruction performs two operations. It can write a-bit values into both the software
sequence detector and the page programming buffer. The contents ofthe memory-address register and
the contents of the memory-data register are presented to the memory core during the Update-DR
state. On the rising edge of TCK, upon leaving the Update-DR state, an internal write signal is applied
to either the software sequence detector orthe page programming buffer.
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CLRERR
Clear Conflict Error Flag
Scan Path
TOI
-+
bypass
-+
TOO
Description The CLRERR instruction is used to reset the program/erase conflict flag. The conflict flag (status bit 2
in the instruction register) will be set if any write operations are issued while the SCOPE Oiary is
programming or erasing. After the conflict flag is set, the SCOPE Oiary won't recognize any sequence
commands. The conflict flag will remain set until the CLRERR instruction is executed.
CLRLOCK
Exit Lock Mode
Scan Path
TOI
-+
bypass
-+
TOO
Description The CLRLOCK instruction is used to exit the lock mode. When the lock mode is disabled, all read and
programming operations are directed to the memory array. The normal mode is indicated when status
bit 4 is cleared in the instruction register.
CLRSWS
Clear Software Sequence
Scan Path
TOI
-+
bypass
-+
TOO
Description The CLRSWS instruction is used to clear software sequence operations. The instruction will reset or
cancel any software sequence up until the BEGOPS instruction is executed. The CLRSWS instruction
will also clear status bit 5 (valid software sequence detected) in the instruction register. The CLRSWS
instruction will not interrupt an erase or program operation once the operation has started.
DMARD
DMA Read
Scan Path
TOI
-+
(ignored) / memory-data
-+
TOO
Description The OMARO instruction is used to perform streaming data reads from the Flash EEPROM memory
array. Ouring the read operation, upon entering the Shift-DR state, the contents of the memory array
will be shifted out beginning with the currently addressed location. The memory-address register is
automatically incremented on each byte boundary while performing the OMARO operation. Input data
on the TOI pin is discarded and does not pass through to the TDO output pin.
DMAWR
DMAWrite
Scan Path
TDI
-+
memory-data
-+
memory-address
-+
TDO
Description The DMAWR instruction allows a streaming method of writing address/data pairs to the SCOPE Diary.
During the Shift-DR state, the SCOPE Oiary will automatically generate write strobes to the memory
core on each 24-bit address/data pair boundary. The SCOPE Diary supports two modes of
synchronizing the write operation with the incoming address/data pairs; state-transition mode and
stream-header mode. The contents of the header register determine the selected mode.
ERABLK
Erase Block Register Select
Scan Path
TDI
-+
erase-block
-+
TDO
Description The ERABLK instruction is used to access the erase-block select register. Oata loaded into the ERABLK
register is presented to the memory core during the Update-DR state.
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16 384-BIT SCOPE™ DIARY
JTAG ADDRESSABLE STORAGE DEVICE
SMJS816B-NOVEMBER 1990--REVISED JANUARY 1993
EXTEST
External Boundary Test
Scan Test
TDI
~
boundary-scan
~
TDO
Description The EXTEST instruction is used to check the board connectivity of the DLA and DLB input pins. During
an EXTEST operation, DLA and DLB inputs to the internal control logic can be sampled by the scan
path, but not driven.
IDCODE
ID Register Scan
Scan Path
TDI
~
id
~
TDO
Description The I DCODE instruction is used to read the device identification data. During the Capture-DR state, the
32-bit device identification code (00001 02Fh) is loaded into the ID register. The IDCODE instruction is
automatically loaded during SCOPE Diary power-on reset or upon entry to the Test-Log;c-Resetstate.
ISTEST
Internal Self Test
Scan Path
TDI
~
boundary-scan
~
erase-block
~
header
~
memory-data
~
memory-address
~
TDO
Description The ISTEST instruction is used to test scan path data registers. During the Capture-DR state, all of the
register latched values are transferred to the scan path (except the boundary scan register which
transfers the values of DLA and DLB to the scan path).
LDADDR
Load Address Register
Scan Path
TDI
~
memory-address
~
TDO
Description The LDADDR instruction is used to load the memory-address register. The 16-bit value loaded from the
scan path points to an address and is presented to the memory array during the Update-DR state.
LOADHDR
Header Register Select
Scan Path
TDI
~
header
~
TDO
Description The LOADHDR instruction is used to access the header register. Loading any value from 01 h to FFh
selects header mode synchronization during DMA write operations. Loading the header register with
OOh selects state-transition mode synchronization for DMA write operations. During the LOADHDR
operation, the header register is selected into the DR scan path.
SAMPLE
Boundary Sample
Scan Path
TDI
~
boundary-scan
~
TDO
Description The SAMPLE instruction is used to check the board connectivity of the DLA and DLB input pins. During
aSAMPLE operation, DLA and DLB inputs tothe internal control logic can be sampled by the scan path,
but not driven.
SETLOCK
Enter Lock Mode
Scan Path
TDI
~
bypass
~
TDO
Description The SETLOCK instruction is used to enable the lock mode. When the lock mode is enabled, read and
programming operations are directed to the lockbits. The lock mode operation is indicated when status
bit 4 is set in the instruction register. The SCOPE Diary will remain in the lock mode until the CLRLOCK
instruction is executed. While in the lock mode, all read operations capture the state of the lockbits in
the data-memory register. While reading the lockbits, the four most significant bits are set to logic 1 .
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operation
TAP state controller
Operation of the TAP state controller conforms to the IEEE 1149.1 Serial Test Bus standard. The state flow
diagram is shown in Figure 4 on page 8.
loading and executing Instructions
All bus sequences that load and execute instructions start with the TAP in the Run-Test/Idle state. To initialize
the TAP to Run-Test/Idle from any other state, apply the 6-cycle sequence shown in Table 6.
Table 6. TAP Reset Sequence
Cycle
1
2
3
4
5
6
TMS
1
1
1
1
1
0
TCK
J
J
J
J
J
J
TDft
X
X
X
X
X
X
TOO
(See Note 2)
HI-Z
HI-Z
HI-Z
HI-Z
HI-Z
TAP
State
Undefined
Undefined
Undefined
Undefined
TestLogic-Reset
RunTest/ldle
t X denotes a don't care.
NOTE 2: TOO will become high-impedance on falling edge of TCK.
sequence timing
The SCOPE Diary contains internal timing logic to simplify programming and erase operations. Once the host
initiates a programming or erasing operation, that operation will automatically continue to completion. The host
does not need to intervene until the operation is finished. To check the status of the operation, poll status bit 6
of the instruction register.
software sequence
The host initiates all of the SCOPE Diary's internal memory operations by issuing a sequence of address/data
pairs (forming a specific software sequence) to the SCOPE Diary. The correct address/data pairs must be
received in a specific order and within a specific time period to be recognized as a valid software sequence by
the SCOPE Diary. Once a sequence has begun, the SCOPE Diary starts an internal sequence timer. Each
consecutive address/data pair must be received within a 9 ms time period. After each address/data pair, the
timer is reset to receive the next sequence pair. If the time between consecutive address/data pairs exceeds
the timer limit, the internal state of the sequence detector will be reset, and the host must re-issue the software
sequence from the beginning. If the SCOPE Diary detects a valid software sequence, status bit 5 of the
instruction register will be set within 2 !-IS and will remain set as long as the SCOPE Diary is unlocked for the
operation. The host may terminate a software sequence at any point by either letting the internal time limit expire,
or by issuing a CLRSWS command. The software sequences recognized by the SCOPE Diary are shown in
Table 7.
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16 384·BIT SCOPE ™ DIARY
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SMJS816B-NOVEMBER 199Q-REVISED JANUARY 1993
Table 7. SCOPE Diary Software Sequences
Operation
Addresa/Data Pair Sequence
Programming
2AAAh/55h
5555h / AAh
5555h / AOh
5555h / AAh
2AAAh /55h
5555h /BOh
Erasing
5555h/ AAh
2AAAh /55h
5555h /10h
5555h / AAh
Program-Verify
2AAAh/55h
5555h / BOh
5555h/ AAh
Erase-Verify
2AAAh /55h
5555h / DOh
5555h / AAh
Exit-Verify
2AAAh/55h
5555h / FOh
page programming buffer
The page programming buffer is a 32-byte buffer that the host loads with the data to be programmed into the
memory array_ This buffer is internal to memory and can be accessed using the memory-address and
memory-data registers. The page programming buffer is automatically selected by internal control logic after
it detects a valid program software sequence. The contents of this buffer are automatically set to FFh, so any
bits not specifically cleared by the host will not be programmed. Up to 32 bytes can be programmed in one cycle.
Address/data pairs must be loaded into the page programming buffer within the same time constraints as the
software sequence. If the sequence timer is allowed to expire during a page programming buffer load, the
internal control logic will terminate the programming operation and clear the software sequence detector
(indicated by status bit 5 in the instruction register). During a programming operation, data that has been loaded
into the internal page programming buffer is automatically transferred into the memory array.
operation initiation
The SCOPE Diary differs from typical software sequence-controlled memory devices because the selected
programming or erasing operation does not automatically begin at the end of the internal sequence time out.
To initiate the selected operation, the host must issue the BEGOPS command to the SCOPE Diary and enter
the Run-Test/Idle state before the internal sequence timer expires. If the timer expires, the internal sequence
detector will be cleared, and the selected operation must be re-initiated from the beginning. Status bit 6 in the
instruction register indicates a successful program or erase operation. This bit will be set within 2 ~s after the
BEGOPS instruction is executed.
reset
The SCOPE Diary test bus logic is cleared either by internal circuitry at power-up, or by entry to the
Test-Logie-Reset state. All internal data scan path registers are set to logic 0, and the instruction register is
loaded with the IDCODE instruction. Entering the Test-Logie-Reset state will not clear a pending software
sequence or interrupt an executing self-timed program or erase cycle.
1ExAs . "
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erase-verify mode
The erase-verify mode allows the host to verify the adequacy of erasure. Once the SCOPE Diary has been
placed in the verify mode, it will remain in that state (indicated in the instruction register when status bit 3 is a
logical 1) until the exit-verify mode sequence has been issued. When in the erase-verify mode, the internal
voltage applied to the read select lines (wordlines) is reduced by a preset margin. To verify that the array has
been erased, the host reads the memory block and checks that all bits are set to logic 1.
program-verify mode
The program-verify mode allows the host to verify the adequacy of programming. Once the SCOPE Diary has
been placed in the program-verify mode, it will remain in this state (indicated in the instruction register when
status bit 3 is a logical 1 ) until the exit-verify mode sequence has been issued. When in the program-verify mode,
the internal voltage applied to the read-select lines (wordlines) is increased by a preset margin. To verify that
a programming operation was successful, the host reads the previously programmed locations and checks that
the data values are correct.
JTAG extensions
DMA read
The DMA read mode allows any number of sequential bits to be read from the SCOPE Diary while remaining
in the Shift-DR state. During a DMA read operation, the contents of the memory array will be shifted out
beginning with the address location contained in the memory-address register. Upon entry to the Shift-DRstate,
an internal modulo B counter is triggered. This counter is used to increment the contents of the memory-address
register on byte boundaries. After the data from the last byte in the memory array has been read, the next data
will be read from the byte at the beginning of the memory array.
DMAwrite
The DMA write mode simplifies data transfer to the SCOPE Diary. This mode allows data to be continuously
streamed into the SCOPE Diary while remaining in the Shift-DR state. Compared to normal modes of data
transfer, the DMA write extensions enable systems with a large number of devices in the scan path to realize
a significant reduction of clock cycles.
In the DMA write mode, an internal modulo 24 counter is used to automatically transfer address/data pairs to
the memory core while bypassing the Update-DRstate. To initiate a DMA write data transfer, the internal modulo
24 counter must be triggered (synchronized) when the first bit of an address/data pair is at the TDI input pin.
The SCOPE Diary supports two methods of DMA synchronization: state-transition mode and header mode. The
host determines which method of DMA synchronization is used.
state-transition mode
The host selects state-transition mode by clearing the header register (all bits to logic 0). When the
state-transition mode is selected, incoming scan path data is ignored during first entry to the Shift-DR state. The
first entry to Pause-DR indicates proper alignment at the TDI input pin of the first address/data pair. Re-entry
to the Shift-DR state triggers the modulo 24 counter and enables the address/data pair to be written to the
memory core. Address/data pairs can then be streamed continuously to the SCOPE Diary with internal transfers
occurring automatically on 24-bit boundaries.
header mode
The host selects the header mode by loading the header register with a value from 01 h to FFh. When the header
mode is selected, incoming scan path data is ignored until a byte (matching the contents of the header register)
arrives indicating the arrival of valid address/data pairs. When this header byte is detected, the internal modulo
24 counter is triggered. Address/data pairs can then be streamed continuously to the SCOPE Diary with internal
transfers occurring automatically on 24-bit boundaries.
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In either state-transition or header mode, the host places the SCOPE Diary in the Update-DRstate to end a DMA
write operation. Because placing the SCOPE Diary in the Update-DR state ends the operation, the host must
never place the SCOPE Diary in this state until the DMA write operation is complete. The host may place the
SCOPE Diary in the Pause-DR state at any time.
operation examples
Note that in this section, the letter "nn denotes a value from Oh to Fh, and the letter "x" denotes a don't care.
reading examples
reading using the byte mode
Step 1.
Load the BYTERD instruction.
Step 2.
Step 3.
Scan in 16-bit address = nnnn and a-bit data = xx.
Scan out 16-bit address = nnnn and a-bit data = nn.
reading using the DMA mode
Step 1.
Step 2.
Step 3.
Step 4.
Load the LDADDR instruction.
Scan in 16-bit address = nnnn.
Load the DMARD instruction.
Loop in Shift-DR to shift out a stream of a-bit memory data values, the address register is
automatically incremented on byte boundaries.
lockbit examples
reading lockbits using the byte mode
Step 1.
Step 2.
Step 3.
Step 4.
Step 5.
Load the SETLOCK instruction.
Load the BYTERD instruction.
Scan in 16-bit address =0000 and a-bit data = xx.
Scan out 16-bit address =0000 and a-bit data = Fn.
Load the CLRLOCK instruction.
reading lockbits using the DMA mode
Step 1.
Step 2.
Step 3.
Step 4.
Load the SETLOCK instruction.
Load the DMARD instruction.
Scan out the a-bit lock value =Fn.
Load the CLRLOCK instruction.
programming lockbits using the byte mode
Step 1.
Step 2.
Step 3.
Step 4.
Step 5.
Step 6.
Step 7.
Step a.
Load the SETLOCK instruction.
Load the BYTEWR instruction.
Scan in address = 5555 and data =AA, go to Run-Test/Idle.
Scan in address = 2AAA and data = 55; go to Run- Test/Idle.
Scan in address 5555 and data =AD; go to Run-Test/Idle.
Scan in address = 0000, and data = Fn; go to Run-Test/Idle.
Load the BEGOPS instruction; go to Run-Test/Idle.
Load the CLRLOCK instruction.
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programming lockbits using the DMA mode
Step 1.
Load the SETLOCK instruction.
Step 2.
Load the DMAWR instruction.
Step 3.
Synchronize SCOPE Diary using either state-transition mode or header mode.
Step 4.
Loop in Shift-DR to scan in address =5555 and data =AA.
Step 5.
Continue looping in Shift-DR to scan in address =2AAA and data =55.
Step 6.
Continue looping in Shift-DR to scan in address =5555 and data =AD.
Step 7.
Continue looping in Shift-DR to scan in address =0000 and data =Fn.
Step 8.
Load the BEGOPS instruction; go to Run-Test/Idle.
Step 9.
Load the CLRLOCK instruction.
flash erase examples
erasing a block using the byte mode
Step 1.
Load the ERABLK instruction.
Step 2.
Scan in the 4-bit erase-block-select value = n.
Step 3.
Load the BYTEWR instruction.
Step 4.
Scan in address = 5555 and data = AA; go to Run-Test/Idle.
Step 5.
Scan in address = 2AAA and data = 55; go to Run-Test/Idle.
Step 6.
Scan in address = 5555 and data = 80; go to Run- Test/Idle.
Step 7.
Scan in address = 5555 and data = AA; go to Run-Test/Idle.
Step 8.
Scan in address = 2AAA and data = 55; go to Run-Test/Idle.
Step 9.
Scan in address =5555 and data = 10; go to Run-Test/Idle.
Step 10. Poll the SCOPE Diary until valid sequence is detected.
Step 11. Load the BEGOPS instruction; go to Run-Test/Idle.
erasing a block using the DMA mode
Step 1.
Load the ERABLK instruction.
Step 2.
Scan in the 4-bit erase-block-select value = n.
Step 3.
Load the DMAWR instruction.
Step 4.
Synchronize the SCOPE Diary using either state-transition mode or header mode.
Step 5.
Loop in Shift-DR to scan in address = 5555 and data =AA.
Step 6.
Continue looping in Shift-DR to scan in address =2AAA and data =55.
Step 7.
Continue looping in Shift-DR to scan in address =5555 and data =80.
Step 8.
Continue looping in Shift-DR to scan in address =5555 and data =AA.
Step 9.
Continue looping in Shift-DR to scan in address =2AAA and data =55.
Step 10. Continue looping in Shift-DR to scan in address =5555 and data = 10.
Step 11. Poll SCOPE Diary until valid sequence is detected.
Step 12. Load the BEGOPS instruction; go to Run-Test/Idle.
verifying block erasure using the byte mode
select the erase-verify mode:
Step 1.
Step 2.
Step 3.
Step 4.
Load the BYTEWR instruction.
Scan in address =5555 and data =AA; go to Run-Test/Idle.
Scan in address =2AAA and data =55; go to Run- Test/Idle.
Scan in address = 5555 and data = DO; go to Run-Test/Idle.
INSTRUMENTS
TEXAS ' "
6-118
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
TMS29F816
16 384·BIT SCOPE™ DIARY
JTAG ADDRESSABLE STORAGE DEVICE
SMJS816S-NOVEMBER 1990-REVISED JANUARY 1993
read out the erased block:
Step 5.
Step 6.
Step 7.
Step 8.
Load the BYTERD instruction.
Scan in 16-bit address = nnnn and 8-bit data =xx.
Scan out 16-bitaddress =nnnnand 8-bitdata =FF; atthesametime, scan in 16-bitaddress =nnnn+1
and data = xx.
Repeat Step 7 until entire block is read. All bits will be a logic 1 if the block is properly erased.
exit the erase-verify mode:
Step 9.
Step 10.
Step 11.
Step 12.
Load the BYTEWR instruction.
Scan in address = 5555 and data = AA; go to Run-Test/Idle.
Scan in address = 2AAA and data = 55; go to Run-Test/Idle.
Scan in address = 5555 and data = FO; go to Run-Test/Idle.
verifying block erasure using the DMA mode
select the erase-verify mode:
Step 1.
Step 2.
Step 3.
Step 4.
Step 5.
Load the DMAWR instruction.
Synchronize the SCOPE Diary using either state-transition mode or header mode.
Loop in Shift-DR to scan in address =5555 and data =AA.
Continue looping in Shift-DR to scan in address = 2AAA and data = 55.
Continue looping in Shift-DR to scan in address =5555 and data = DO.
read out the erased block:
Step
Step
Step
Step
6.
7.
8.
9.
Load the LOAD DR instruction.
Scan in 16-bit data starting address = nnnn of the block you want to verify.
Load the DMARD instruction.
Loop in Shift-DR to shift out a stream of 8-bit memory data values from the addressed block. All bits
will be a logic 1 if the block is properly erased.
exit the erase-verify mode:
Step 10.
Step 11.
Step 12.
Step 13.
Step 14.
Load the DMAWR instruction.
Synchronize the SCOPE Diary using either state-transition mode or header mode.
Loop in Shift-DR to scan in address = 5555 and data = AA.
Continue looping in Shift-DR to scan in address =2MA. and data =55.
Continue looping in Shift-DR to scan in address = 5555 and data = FO.
verifying programming using the byte mode
select the program-verify mode:
Step 1.
Step 2.
Step 3.
Step 4.
Load the BYTEWR instruction.
Scan in address =5555 and data = AA; go to Run-Test/Idle.
Scan in address =2AAA and data =55; go to Run-Test/Idle.
Scan in address =5555 and data = BO; go to Run-Test/Idle.
read out the programmed data:
Step 5.
Step 6.
Step 7.
Step 8.
Load the BYTERD instruction.
Scan in 16-bit address = nnnn and 8-bit data =xx.
Scan out 16-bit address = nnnn and 8-bit data = nn; at the same time, scan in 16-bit
address=nnnn + 1 and data =xx.
Repeat Step 7 until desired memory locations are read and verified.
exit the program-verify mode
Step 9.
Step 10.
Step 11.
Step 12.
Load the BYTEWR instruction.
Scan in address =5555 and data =AA; go to Run-Test/Idle.
Scan in address =2AAA and data =55; go to Run-Test/Idle.
Scan in address =5555 and data = FO; go to Run-Test/Idle.
TEXAS
~
INsrRUMENTS
POST OFFICE BOX 1443' HOUSTON, TEXAS 77001
6-119
TMS29F816
16 384·BIT SCOPE™ DIARY
JTAG ADDRESSABLE STORAGE DEVICE
SMJS816B-NOVEMBER 199G-REVISED JANUARY 1993
verifying programming using the DMA mode
select the program·verlfy mode:
Step 1.
Step 2.
Step 3.
Step 4.
Step 5.
Load the DMAWR instruction.
Synchronize the SCOPE Diary using either state·transition mode or header mode.
Loop in Shift·DR to scan in address =5555 and data =AA.
Continue looping in Shift·DRto scan in address =2AAA and data =55.
Continue looping in Shift·DRto scan in address = 5555 and data = BO.
read out the programmed data:
Step 6.
Step 7.
Step 8.
Step 9.
Load the LDADDR instruction.
Scan in 16-bit starting address = nnnn of the data you want to verify.
Load the DMARD instruction.
Loop in Shift-DR to shift out a stream of 8-bit memory data values starting from the addressed
location. Verify that the output data stream matches the programmed data.
exit the program·verlfy mode:
Step
Step
Step
Step
Step
10.
11.
12.
13.
14.
Load the DMAWR instruction.
Synchronize the SCOPE Diary using either state-transition mode or header mode.
Loop in Shift-DR to scan in address = 5555 and data = AA.
Continue looping in Shift-DR to scan in address =2AAA and data =55.
Continue looping in Shift-DR to scan in address = 5555 and data = FO.
programming examples
programming a single byte using the byte mode
Step 1.
Load the BYTEWR instruction.
Step 2.
Scan in address = 5555 and data =AA; go to Run-Test/Idle.
Step 3.
Scan in address =2AAA and data = 55; go to Run-Test/Idle.
Step 4.
Scan in address = 5555 and data =AO; go to Run-Test/Idle.
Step 5.
Scan in address = nnnn and data = nn; go to Run-Test/Idle.
Step 6.
Load the BEGOPS instruction; go to Run-Test/Idle.
programming a single byte using the DMA mode
Step 7.
Load the DMAWR instruction.
Step 8.
Synchronize the SCOPE Diary using either state-transition mode or header mode.
Step 9.
Loop in Shift-DR to scan in address = 5555 and data =AA'
Step 10. Continue looping in Shift-DR to scan in address = 2AAA and data = 55.
Step 11. Continue looping in Shift-DR to scan in address = 5555 and data = AO.
Step 12. Continue looping in Shift-DR to scan in address = nnnn and data = nn.
Step 13. Load the BEGOPS instruction; go to Run-Test/Idle.
programming a page using the byte mode
Step 1.
Load the BYTEWR instruction.
Step 2.
Scan in address =5555 and data =AA; go to Run-Test/Idle.
Step 3.
Scan in address =2AAA and data = 55; go to Run-Test/Idle.
Step 4.
Scan in address = 5555 and data = AO; go to Run-Test/Idle.
Step 5.
Scan in address = nnnn and data = nn; go to Run-Test/Idle.
Step 6.
Go to Step 5 while there are address/data pairs to load within the 32-byte page.
Step 7.
Load the BEGOPS instruction, go to Run-Test/Idle.
TEXAS
~
INSTRUMENTS
6·120
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
TMS29F816
16 384·BIT SCOPE™ DIARY
JTAG ADDRESSABLE STORAGE DEVICE
SMJS816B-NOVEMBER 1990-REVISED JANUARY 1993
programming a page using the DMA mode
Step 1.
Load the DMAWR instruction.
Step 2.
Synchronize the SCOPE Diary using either state-transition mode or header mode.
Loop in Shift-DR to scan in address =5555 and data =AA.
Step 3.
Continue looping in Shift-DR to scan in address =2AAA and data =55.
Step 4.
Step 5.
Continue looping in Shift-DR to scan in address = 5555 and data = AO.
Step 6.
Continue looping in Shift-DR to scan in address = nnnn and data =nn.
Step 7.
Go to Step 6 while there are address/data pairs to load within the 32-byte page.
Step 8.
Load the BEGOPS instruction; go to Run-Test/Idle.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage, Vee (see Note 3) ................................................... - 0.6 V to 7 V
Input voltage range: All except DLA (see Note 3) ..................................... - 0.6 V to 6.5V
Input voltage range: DLA (see Note 3) .............................................. - 0.6 V to 15 V
Output voltage (see Note 3) ................................................. - 0.6 V to Vee + 0.6V
Operating free-air temperature range .................................................. O°C to 70°C
Storage temperature range ....................................................... - 65°C to 125°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 3: Voltage values are with respect to GND (substrate).
recommended operating conditions
VCC
Supply voltage
VIH
High-level input voltage
VIL
Low-level input vottage
TA
Operating free-air temprature
TIL
MIN
NOM
MAX
4.5
5
5.5
2
CMOS
VCC-O.2
TIL
-0.5
CMOS
GND-0.2
0
Endurance cycles
VCC+ 1
V
V
VCC + 0.2
0.8
GND+0.2
70
10000
TEXAS
UNIT
V
·C
Cycles
~
INSTRUMENTS
POST OFFICE BOX 1443' HOUSTON. TEXAS 77001
6-121
TMS29F816
16 384·BIT SCOPETM DIARY
JTAG ADDRESSABLE STORAGE DEVICE
SMJS816B-NOVEMBER 199O-REVISED JANUARY 1993
electrical characteristics over full ranges of recommended operating conditions (unless otherwise
noted)
TEST CONDITIONS
VOH
High-level output voltage
10H =-2.0mA
VOL
Low-level output voltage
IOL=2.1 mA
DLA, DLB
VI =-2.4 V
DLA, DLB
VI=OV
TDI, TMS, TCK
VI=0.4
MIN
TYpt
MAX
2.4
UNIT
V
0.4
75
V
150
±10
II
Input current (leakage)
VI = VCC = 5.5 V
±10
10
Output current (leakage)
VO=O.1 toVCC
±10
ItA
ICCI
VCC average supply current (active read)
tcvcl e = 160 ns, outputs open
20
mA
ICC2
VCC average supply current (active write)
tcvcle = 15 ms
15
mA
TDI, TMS, TCK
-10
-50
ItA
t TYPical values are at TA = 25°C and nominal voltages.
capacitance over recommended ranges of supply voltage and operating free-air temperature,
f = 1 MHz*
TYpt
MAX
CI
Input capacitance
VI = 0, f = 1 MHz
4
7
pF
Co
Output capacitance
Vo = 0, f = 1 MHz
8
12
pF
PARAMETER
TEST CONDITIONS
MIN
UNIT
*t
TYPical values are at TA = 25°C and nominal voltages ..
Capacitance measurements are made on sample basis only.
switching characteristics overfull ranges of recommended operating conditions
PARAMETER
MIN
MAX
UNIT
tDA
TDO valid from falling edge of TCK
74
ns
tDZ
TDO disable time from falling edge of TCK
35
ns
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
MIN
tCYC
TCK cycle time
MAX
UNIT
160
ns
tw(TCKH)
Pulse duration, TCK high
50
ns
tw(TCKL)
Pulse duration, TCK low
70
ns
tSU(TMS)
TMS input setup time
15
ns
tIH(TMS)
TMS input hold time
5
ns
tSU(TDI)
TDI input setup time
6
ns
tlHITDIl
TDI input hold time
15
ns
TEXAS ~
INSTRUMENTS
6-122
POST OFFICE BOX 1443· HOUSTON, TEXAS 77001
TMS29F816
16 384·BIT SCOPE ™ DIARY
JTAG ADDRESSABLE STORAGE DEVICE
SMJS816B-NOVEMBER 1990-REVISED JANUARY 1993
Internal timing requirements
PARAMETER
MIN
MAX
tsss
Software sequence status bit valid from software sequence
2
tpEBS
Program erase busy status bit valid from BEGOPS execution
2
tST
Sequence timer limit
9
UNIT
lAS
lAS
ms
PARAMETER MEASUREMENT INFORMATION
2.08 V
Output
Under Test
T
CL=30pF
Figure 5. AC Test Output Load Circuit
AC testing Input/output wave forms
2.4 V
-----..X ~.~v
O.~ ~ X'-----
_ _ _ _oJ
0.4 V
AC testing inputs are driven at 2.4 V for logic high and 0.4 for logic low. liming measurements are made at 2 V for
logic 1 and 0.8 V for logic 0 for both inputs and outputs. Each device should have a 0.1-!lF ceramic capacitor
connected between Vee and GND as close as possible to the device pins.
TCK
14
A
i\
~~~/-------
I '----~I
I
tw(TCKH)
14
I
I
I I
I
14
i
INPUT
TOO
I
I
~
X:
i4
---r----':
I
I
j4- toz ~
~I
tCYC
~I
tw(TCKL)
X'-r---:- - -
~ tsut
i
I
I
t4-- tlH* -+j
I
I
~I
~r--~"ic-- tOA
----~)~--------~(==============
t tsu represents TOI input setup time and TMS input setup time.
* tlH represents TDI input hold time and TMS input hold time.
Figure 6. Timing Diagram
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
6-123
TMS29F816
16384-BIT SCOPE™ DIARY
JTAG ADDRESSABLE STORAGE DEVICE
SMJS816B-NOVEMBER 199O-REVISED JANUARY 1993
TEXAS ~
INSIRUMENTS
6·124
POST OFFICE BOX 1443 • HOUSTON, TEXAS nCOl
TMS28F010
1 048 576·BIT FLASH
ELECTRICALLY ERASABLE PROGRAMMABLE READ·ONLY MEMORY
SMJS011A-DECEMBER 1
•
•
•
•
•
•
•
•
•
•
Organization .•. 128K x 8·Bit Flash Memory
Pin Compatible with Existing 1-Megabit
EPROMs
All Inputs/Outputs TTL Compatible
Maximum Access/Minimum Cycle Time
Vee ± 10%
MARCH 1993
NPACKAGEt
(TOP VIEW)
'28F010-10
100 ns
'28F010-12
120 ns
'28F010-15
150 ns
'28F010-17
170 ns
Industry-Standard Programming Algorithm
PEP4 Version Available With 168-Hour
Burn-In, and Choice of Operating
Temperature Ranges
Chip Erase Before Reprogramming
10000,1 000, and 100 Program/Erase Cycle
Versions Available
Low Power Dissipation (Vee = 5.50 V)
- Active Write ... 55 mW
- Active Read ... 165 mW
- Electrical Erase ..• 82.5 mW
- Standby ... 0.55 mW
(CMOS-Input Levels)
Automotive Temperature
Range: - 40°C to + 125°C
Vpp
1
VCC
A16
A15
A12
A?
A6
A5
2
Vii
3
NC
4
A4
8
A3
9
A2
10
A14
A13
AS
A9
All
G
Al0
11
E
12
13
DO?
D06
D05
D04
D03
5
6
7
Al
AO
DOO
DOl
D02
14
15
16
VSS
17
z
o
~
FM PACKAGEt
:!E
a:
(TOP VIEW)
C\I
It)
(0
c..
U
:::C:::C:::C g-~I:l:
4
description
o
u.
U
z
Z
3 2
0
W
o
The TMS28F01 0 is a 1048 576-bit, programmable
read-only memory that can be electrically
bulk-erased and reprogrammed.
Z
~
The TMS28F010 is available in 10 000, 1 000,
and 100 program/erase endurance cycle versions.
The TMS28F010 Flash EEPROM is offered in a
dual in-line plastic package (N suffix) designed for
insertion in mounting-hole rows on 15,2 mm
(600-mil) centers, a 32-lead plastic leaded-chip
carrier package using 1,25 mm (50-mil) lead
spacing (FM suffix), a 32-lead thin small outline
package (DD suffix), and a reverse pinout TSOP
package (DU suffix).
The TMS28F010 is offered with three choices of
temperature ranges of ooe to 70°C (NL, FML,
DDL, and DULsuffixes), -40 o to 85°C (NE, FME,
DDE, and DUE suffixes), and -40 o to 125°C
(NO, FMO, DDO, and DUO suffixes). All package
types are offered with 168 hour burn-in (4 suffix).
e
e
TEXAS
c
C
~
0
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Z
G
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
Vss
DQ2
DQ1
DQO
AO
A1
A2
A3
DUPACKAGEt
REVERSE PINOUT
0
m
-Z
0"
:D
{TOP VIEW)
G
A10
E
3:
DQ7
DQ6
DQ5
DQ4
DQ3
~
0
Z
Vss
DQ2
DQ1
DQO
AO
A1
A2
A3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
'V
t The packages shown are for pinout reference only.
lExAs . "
6-126
INSIRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS nOO1
All
A9
AS
A13
A14
NC
W
Vee
Vpp
A16
A15
A12
A7
A6
A5
A4
TMS28F010
1 048 576·BIT FLASH
ELECTRICALLY ERASABLE PROGRAMMABLE READ·ONLY MEMORY
SMJS011A-DECEMBER 1992-REVISED MARCH 1993
device symbol nomenclature
TMS28F010
-12
C4
FM
L=
L
4
PEP4 Burn-In
4 = 168 Hour Burn-In
(Blank If no burn-In)
Temperature Range Dealgnator
L =
O'C to 70'C
E = - 40'C to 85'C
Q = -40'C to 125'C
' - - - - - - - - - - Package Designator
Plastic Dual-In-Llne Package
N
FM = Plastic Leaded Chip Carrier
DO = Thin Small Outline Package
DU = Thin Small Outline Package,
Reverse Pinout
=
z
o
' - - - - - - - - - - - - Program/Erase Endurance
C4 = 10,000 Cycles
C3 = 1,000 Cycles
C2 = 100 Cycles
~
' - - - - - - - - - - - - - Speed Designator
-10 = 100 ns
-12 = 120 ns
-15 = 150 ns
-17 = 170 ns
:E
a:
o
LL
Z
W
o
Z
c~
«
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443· HOUSTON, TEXAS 77001
6-127
TMS28F010
1 048 576·BIT FLASH
ELECTRICALLY ERASABLE PROGRAMMABLE READ·ONLY MEMORY
SMJS011A-DECEMBER 1992-REVISED MARCH 1993
functional block diagram
DQG-DQ7
Vcc ----+-
VSS ----+Vpp - - - - - - . - - - - - - - < H H
Erase Voltage Switch
L..-~--__,_---'
w--.......
State Control
Program/Erase
Stop Timer
Command Register 1--+-1
STB
E-->------+-----------t---t~
»
c
G-----~---------~-~
~
z
o
m
-z
-n
Chip Enable
Output Enable
Logic
STB
A
d
d
Column-Decoder
Column-Gating
Row-Decoder
1 048 576-Blt
Array Matrix
r
Ao-A16
e
s
s
o
L
3:
h
a
::D
t
c
~
o-z
TEXAS ~
INsrRUMENTS
6-128
POST OFFICE BOX 1443· HOUSTON, TEXAS 77001
TMS28F010
1 048 576·BIT FLASH
ELECTRICALLY ERASABLE PROGRAMMABLE READ·ONLY MEMORY
SMJS011A-DECEMBER 1992-REVISED MARCH 1993
Table 1. Operation Modes
FUNCTION
MODEt
Read
E
(22)
G
(24)
AO
(12)
A9
(26)
W
DQ~Q7
(31)
(13-15,17-21)
Read
VpPL
VIL
VIL
xt
X
VIH
Data Out
Output Disable
VpPL
VIL
VIH
X
X
VIH
HI-Z
Standby and Write Inhibit
VpPL
VIH
X
X
X
X
Signature Mode
Read/Wrlte
Vpp§
(1)
HI-Z
MFG Code97h
VIL
VH+
VIH
X
X
VIH
Data Out
VIH
X
X
VIH
HI-Z
VIH
X
X
X
X
HI-Z
VIL
VIH
X
X
VIL
Data In
VPPL
VIL
VIL
Read
VPPH
VIL
VIL
Output Disable
VpPH
VIL
Standby and Write Inhibit
VpPH
Write
VpPH
VIH
Device Code 75h
t X can be VIL or VIH
11 .5 V < VH < 13.0 V
§ VpPL " VCC + 2 V; VpPH is the programming vottage specified for the device. For more details, refer to the recommended operating conditions.
*
operation
read/output disable
When the outputs of two or more TMS28F01 Os are connected in parallel on the same bus, the output of any
particular device in the circuit can be read with no interference from the competing outputs of other devices.
To read the output of the TMS28F01 0, a low-level signal is applied to the E and G pins. All other devices in the
circuit should have their outputs disabled by applying a high-level signal to one of these pins.
standby and write inhibit
Active ICC current can be reduced from 30 mA to 1 mA by applying a high TTL level on E or to 100 ~ with a
high CMOS level on E. In this mode, all outputs are in the high-impedance state. The TMS28F01 0 draws active
current when it is deselected during programming, erasure, or program/erase verification. It will continue to draw
active current until the operation is terminated.
signature mode
The signature mode provides access to a binary code identifying the manufacturer and device type. This mode
is activated when A9 (pin 26) is forced to VH' Two identifier bytes are accessed by toggling AO. All other
addresses must be held low. AO low selects the manufacturer's code 97h, and AD high selects the device code
75h, as shown in the signature mode table below:
IDENTIFIERt
PINS
HEX
AO
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQl
DQO
Manufacturer Code
VIL
1
0
0
1
0
1
1
1
97
Device Code
VIH
0
1
1
1
0
1
0
1
75
t E =G =VIL, AI-AS =VIL, A9 =VH, A10-A16 =VIL, Vpp =VPPL.
programming and erasure
In the erased state, all bits are at a logic 1. Before erasing the device, all memory bits must be programmed to
a logic O. Afterwards, the entire chip is erased. At this point, the bits, now logic 1's, may be programmed
accordingly. Refer to the Fastwrite and Fasterase algorithms for further detail.
TEXAS " ,
INsrRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
6-129
z
o
~
:!:
a:
o
u.
z
w
o
z
~
c
c
~
z
o
m
-z
."
Maximum erase timing is controlled by the internal stop timer. When the stop timer terminates the erase
operation, the device enters an inactive state and remains inactive until a valid erase verify, read, or reset
command is received.
erase-verify command
All bytes must be verified following an erase operation. After the erase operation is complete, an erased byte
can be verified by writing the erase-verify command, AOh, into the command register. This command causes
the device to exit the erase mode on the rising edge of W. The address of the byte to be verified is latched on
the falling edge of W. The erase-verify operation remains enabled until a valid command is written to the
command register.
o
:IJ
:s:
To determine whether or not all the bytes have been erased, the TMS28F01 0 applies a margin voltage to each
byte. If FFh is read from the byte, then all bits in the designated byte have been erased. The erase-verify
operation continues until all of the bytes have been verified. If FFh is not read from a byte, then an additional
erase operation needs to be executed. Figure 2 shows the combination of commands and bus operations for
electrically erasing the TMS28F01 O.
-o~
z
set-up program/program commands
The programming algorithm initiates with E =VIL, W =VIL, G =VIH, Vpp = 12 V, and Vee = 5 V. To enter the
programming mode, write the set-up program command, 40h, into the command register. The programming
operation will be invoked by the next write-enable pulse. Addresses are latched internally on the falling edge
of W, and data is latched internally on the rising edge of W. The programming operation begins on the rising
edge of Wand ends on the rising edge of the next W pulse. The program operation requires 10 J.lS for completion
before the program-verify command, COh, can be loaded.
Maximum program timing is controlled by the internal stop timer. When the stop timer terminates the program
operation, the device enters an inactive state and remains inactive until a valid program verify, read, or reset
command is received.
TEXAS ~
INSTRUMENTS
6-132
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
TMS28F010
1 048 576-BIT FLASH
ELECTRICALLY ERASABLE PROGRAMMABLE READ-ONLY MEMORY
SMJS011A-OECEMBER 1992-REVISEO MARCH 1993
program-verify command
The TMS28F01 0 can be programmed sequentially or randomly because it is programmed one byte at a time.
Each byte must be verified after it is programmed.
The program-verify operation prepares the device to verify the most recently programmed byte. To invoke the
program-verify operation, COh must be written into the command register. The program-verify operation will end
on the rising edge of W.
While verifying a byte, the TMS28F01 0 applies an internal margin voltage to the designated byte. If the true data
and programmed data match, programming can continue to the next designated byte location; otherwise, the
byte must be reprogrammed. Figure 1 shows how commands and bus operations are combined for byte
programming.
reset command
To reset the TMS28F01 0 after set-up erase command or set-up program command operations without changing
the contents in memory, write FFh into the command register two consecutive times. After executing the reset
command, a valid command must be written into the command register to change to a new state.
z
Fastwrite algorithm
The TMS28F010 is programmed using the Texas Instruments Fastwrite algorithm shown in Figure 1. This
algorithm programs in a nominal time of two seconds.
o-
~
:E
Fasterase algorithm
The TMS28F01 0 is erased using the Texas Instruments Fasterase algorithm shown in Figure 2. The memory
array needs to be completely programmed (using the Fastwrite algorithm) before erasure begins. Erasure
typically occurs in one second.
parallel erasure
a::
o
LL
Z
W
To reduce total erase time, several devices may be erased in parallel. Since each Flash EEPROM may erase
at a different rate, every device must be verified separately after each erase pulse. After a given device has been
successfully erased, the erase command should not be issued to this device again. All devices that complete
erasure should be masked until the parallel erasure process is finished. See Figure 3, Parallel Erase Flow
Diagram.
Examples of how to mask a device during parallel erase include driving the device's E pin high, writing the read
command (OOh) to the device when the others receive a setup erase or erase command, or disconnecting it from
all electrical signals with relays or other types of switches.
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
6-133
o
Z
~
c
c
z~
o
m
-z
."
o
MAX
MIN
'28F010-12
'28F010-15
MIN
MIN
MAX
MAX
'28F010-17
MIN
MAX
UNIT
Access time from
address
tAVOV
100
120
150
170
ns
ta(E)
Access time from
chip enable
tELOV
100
120
150
170
ns
ten (G)
Access time from
output enable
tGLOV
45
50
55
60
ns
Ic(R)
Read cycle time
tAVAV
100
120
150
170
ns
Id(E)
Delay time, chip
enable low to low-Z
output
tELOX
0
0
0
0
ns
td(G)
Delay time, output
enable low to low-Z
output
tGLOX
0
0
0
0
ns
tdis(E)
Chip disable to hi-Z
output
tEHOZ
0
55
0
55
0
55
0
55
ns
tdis(G)
Hold time, output
enable to hi-Z output
tGHOZ
0
30
0
30
0
35
0
35
ns
th(D)
Hold time, data valid
from address, E, or
tAXOX
0
0
0
0
ns
Write recovery time
before read
twHGL
6
6
6
6
IlS
twr(W)
CL=100pF
1 Series 74
TTL Load
Inputtr s 20 ns
Input tf S 20 ns
G"t
t Whichever occurs first.
AC characteristics-write/erase/program operations
s:
z
'28F010-l0
ta(A)
J]
-o~
ALTERNATE
SYMBOL
DESCRIPTION
ALTERNATE
SYMBOL
'28FOI 0-1 0
'28F010-12
'28F010-15
MIN
MIN
'28F010-17
UNIT
MIN
TYP
TYP
TYP
MIN
TYP
tc(W)
Write cycle time
tAVAV
100
120
150
170
ns
tsu(A)
Address setup time
tAVWL
0
0
0
0
ns
th(A)
Address hold time
twLAX
55
60
60
70
ns
tsu(D)
Data setup time
tDVWH
50
50
50
50
ns
thw(D)
Data hold time
twHDX
10
10
10
10
ns
twr(W)
Write recovery time before read
tWHGL
6
6
6
6
I!S
trr(VV]
Read recovery time before write
tGHWL
0
0
0
0
I!S
tsu(E)
Chip enable setup time before write
tELWL
20
20
20
20
ns
th(E)
Chip enable hold time
twHEH
0
0
0
0
ns
tw(W)
Write pulse duration (see Note 8)
twLWH
60
60
60
60
ns
twh(W)
Write pulse duration high
tWHWL
20
20
20
20
ns
tc(W)B
Duration of programming operation
tWHWHl
10
10
10
10
Ic(E)B
Duration of erase operation
tWHWH2
9.5
tsu(P)E
Vpp setup time to chip enable low
tyPEL
1.0
1.0
1.0
1.0
IlS
tsu(E)P
Chip enable, setup time to VPP ramp
tEHVP
100
100
100
100
ns
ts(P)R
VPP rise time
tyPPR
1
1
1
1
I!S
ts(P)F
Vppfall time
tyPPF
1
1
1
1
IlS
NOTE 8: Rlse/fall time
S
10
9.5
IOns.
TEXAS . "
INSTRUMENTS
6-140
POST OFFICE BOX 1443· HOUSTON. TEXAS 77001
10
9.5
10
9.5
IlS
10
ms
TMS28F010
1048 576·BIT FLASH
ELECTRICALLY ERASABLE PROGRAMMABLE READ·ONLY MEMORY
SMJSOllA-DECEMBER 1992-REVISED MARCH 1993
alternative CE-controlled writes
DESCRIPTION
'28F010-10
ALTERNATE
SYMBOL
MIN
'28F010-12
'28F010-15
'28F010-17
UNIT
MAX
MIN
MAX
MIN
MAX
MIN
MAX
lc(W)
Write cycle time
tAVAV
100
120
150
170
ns
tsu(A)
Address setup time
tAVEL
0
0
0
0
ns
thE (A)
Address hold time
tELAX
75
80
80
90
ns
tsu(D)
Data setup time
tDVEH
50
50
50
50
ns
thE(D)
Data hold time
tEHDX
10
10
10
10
ns
twr(E)
Write recovery time before read
tEHGL
6
6
6
6
1'5
trr(E)
Read recovery time before write
tGHEL
0
0
0
0
I'S
tsu(W)
Write enable setup time before
chip enable
twLEL
0
0
0
0
ns
th(W)
Write enable hold time
tEHWH
0
0
0
0
ns
tw(E)
Write pulse duration
tELEH
70
70
70
80
ns
twh(E)
Write pulse duration high
tEHEL
20
20
20
20
ns
tsu(P)E
Vpp setup time to chip enable low
tyPEL
1.0
1.0
1.0
1.0
I'S
lc(W)B
Duration of programming
operation
tEHEH
10
10
10
10
I'S
z
o-
~
~
a:
ou.
PARAMETER MEASUREMENT INFORMATION
~IOII------- tc(R) ------~_I
A~A16
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- - - - - ' ~I
w
U
Z
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talA)
OIl
------__
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I
~~______~I--------~~I
E
I 1
I
I 1 - - talE) ~
G - - - - - - - + - 1- \ .
I
~ twr(W)
I
I'
w----./
DQ~DQ7
z
I
I
td(E)
HI-Z
I!\-
-+--.I
I
I 14-- tdis(E) -+i
:I.'
I
-(
I
I I
I
I
I
I I
I
II·
I
I I+-- tdis(G) ~
I.- th(D) ~
I
I
I
I ~ ten (G) ~
I
I
I
I
I
I
14- td(G) I
I -+1
lOl
_I
I
~««<<{
m...~
I-- tc{R) ---r.l
1c(W) --+I
-.I
Standby!
~~
j+
i
I I
I I
tsu{E)
I
:1+14-_~1r-I
-.II+-
trr{W)
~
zC')
Erase
~ic c_m~~
1c(W)
»
c
Eraae
Verify
Erase
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
j4-- Is(P)F
TMS28F512
524 288·BIT FLASH
ELECTRICALLY ERASABLE PROGRAMMABLE READ·ONLY MEMORY
SMJS513A-DECEMBER 1992-REVISED MARCH 1993
•
•
•
•
•
•
•
•
•
Organization ... 64K x 8-Bit Flash Memory
All Inputs/Outputs TTL Compatible
Maximum Access/Minimum Cycle Time:
Vee ± 10%
N PACKAGEt
(TOP VIEW)
'28F512-10
100 ns
'28F512-12
120 ns
150 ns
'28F512-15
170 ns
'28F512-17
Industry-Standard Programming Algorithm
PEP4 Version Available With 168-Hour
Burn-In, and Choice of Operating
Temperature Ranges
Chip Erase Before Reprogramming
10 000, 1 000 and 100 Program/Erase Cycle
Versions
Low Power Dissipation (Vee = 5.50 V)
- Active Write ..• 55 mW
- Active Read ... 165 mW
- Electrical Erase ... 82.5 mW
- Standby ... 0.55 mW
(CMOS-Input Levels)
Automotive Temperature
Range: - 40°C to + 125°C
U
Vpp
1
NC
2
31
J VCC
JW
A15
3
30
NC
A12
4
29
A?
5
32
J A14
28 J A13
27 J AS
A6
6
A5
7
26
A4
8
25
A3
9
24
A2
10
23
A1
11
22
12
21
J DO?
13
20
D06
D01
14
19
D05
D02
15
18
D04
VSS
16
17
D03
z
o
~
FMPACKAGEt
:E
a:
(TOP VIEW)
C\lLOOQ..O
4
The TMS28F512 is a 524 288-bit, programmable
read-only memory that can be electrically
bulk-erased and reprogrammed.
g- $'13:
oLL
0
z
Z
3 2
o
W
o
7
8
The TMS28F512 is available in 10000, 1 000,
and 100 program/erase endurance cycle versions.
Z
9
c~
10
11
12
A65535
15
z
"
~
G1
[PWRDWNI
G2
1, 2 EN (READ)
~ 1C3 (WRITE)
o
.,
4-
A,3D
V4
~
=:
a:
I'"
A,Z4--
o
LL
Z
W
o
Z
~
tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and lEe Publication 617-12.
Pin numbers shown are for the N package.
c
«
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
6-151
TMS28F512
524 288·BIT FLASH
ELECTRICALLY ERASABLE PROGRAMMABLE READ·ONLY MEMORY
SMJS513A-DECEMBER 1992-REVISED MARCH 1993
command definitions
read command
Memory contents can be accessed while Vpp is high or low. When Vpp is high, writing OOh into the command
register invokes the read operation. Also, when the device is powered up, the default contents of the command
register are OOh and the read operation is enabled. The read operation remains enabled until a different, valid
command is written to the command register.
signature mode command
The signature mode is activated by writing 90h into the command register. The manufacturer's code (97h) is
identified by the value read from address location OOOOh, and the device code (73h) is identified by the value
read from address location 0001 h.
set-up erase/erase commands
The erase algorithm initiates with E =VIL, W = VIL, G = VIH, Vpp = 12V, and Vee = 5 V. To enter the erase mode,
write the set-up erase command, 20h, into the command register. After the TMS28F512 is in the erase mode,
writing a second erase command, 20h, into the command register invokes the erase operation. The erase
operation begins on the rising edge of Wand ends on the rising edge ofthe next W. The erase operation requires
10 ms to complete before the erase-verify command, AOh, can be loaded.
.
»
c
~
z
o
m
Maximum erase timing is controlled by the internal stop timer. When the stop timer terminates the erase
operation, the device enters an inactive state and remains inactive until a valid erase verify, read, or reset
command is received.
erase-verify command
-z
All bytes must be verified following an erase operation. After the erase operation is complete, an erased byte
can be verified by writing the erase-verify command, AOh, into the command register. This command causes
the device to exit the erase mode on the rising edge of W. The address of the byte to be verified is latched on
the falling edge of W. The erase-verify operation remains enabled until a valid command is written to the
command register.
-n
o
::D
3:
To determine whether or not all the bytes have been erased, the TMS28F512 applies a margin voltage to each
byte. If FFh is read from the byte, then all bits in the deSignated byte have been erased. The erase-verify
operation continues until all of the bytes have been verified. If FFh is not read from a byte, then an additional
erase operation needs to be executed. Figure 2 shows the combination of commands and bus operations for
electrically erasing the TMS28F512.
-o~
z
set-up program/program commands
The programming algorithm initiates with E = VIL, W = VIL, G = VIH, Vpp = 12 V, and Vee = 5 V. To enter the
programming mode, write the set-up program command, 40h, into the command register. The programming
operation will be invoked by the next write-enable pulse. Addresses are latched internally on the falling edge
of W, and data is latched internally on the rising edge of W. The programming operation begins on the riSing
edge of Wand ends on the rising edge of the next W pulse. The program operation requires 10 lAs for completion
before the program-verify command, COh, can be loaded.
Maximum program timing is controlled by the internal stop timer. When the stop timer terminates the program
operation, the device enters an inactive state and remains inactive until a valid program verify, read, or reset
command is received.
TEXAS
~
INSTRUMENTS
6-152
POST OFFICE BOX 1443' HOUSTON. TEXAS 77001
TMS28F512
524 288·BIT FLASH
ELECTRICALLY ERASABLE PROGRAMMABLE READ·ONLY MEMORY
SMJS513A-DECEMBER 1992-REVISED MARCH 1993
program-verify command
The TMS28F512 can be programmed sequentially or randomly because it is programmed one byte at a time.
Each byte must be verified after it is programmed.
The program-verify operation prepares the device to verify the most recently programmed byte. To invoke the
program-verify operation, COh must be written into the command register. The program-verify operation will end
on the rising edge of W.
While verifying a byte, the TMS28F512 applies an internal margin voltage to the designated byte. If the true data
and programmed data match, programming can continue to the next designated byte location; otherwise, the
byte must be reprogrammed. Figure 1 shows how commands and bus operations are combined for byte
programming.
reset command
To resetthe TMS28F512 after set-up erase command or set-up program command operations without changing
the contents in memory, write FFh into the command register two consecutive times. After executing the reset
command, a valid command must be written into the command register to change to a new state.
Fastwrite algorithm
The TMS28F512 is programmed using the Texas Instruments Fastwrite algorithm shown in Figure 1. This
algorithm programs in a nominal time of two seconds.
z
o
~
~
Fasterase algorithm
The TMS28F512 is erased using the Texas Instruments Fasterase algorithm shown in Figure 2. The memory
array needs to be completely programmed (using the Fastwrite algorithm) before erasure begins. Erasure
typically occurs in one second.
parallel erasure
a:
o
u.
Z
W
To reduce total erase time, several devices may be erased in parallel. Since each Flash EEPROM may eras~
at a different rate, every device must be verified separately after each erase pulse. After a given device has been
successfully erased, the erase command should not be issued to this device again. All devices that complete
erasure should be masked until the parallel erasure process is finished. See Figure 3, Parallel Erase Flow
Diagram.
Examples of how to mask a device during parallel erase include driving the device's E pin high, writing the read
command (OOh) to the device when the others receive asetup erase or erase command, or disconnecting it from
all electrical signals with relays or other types of switches.
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
6-153
o
Z
~
c
c
z~
o
Give Erase
Command To
All Unmasked
Devices
m
--n
Z
o:D
No
3:
-~
o
z
Give Read
Give Read
Command To
Command To
All Devices
All Devices
NOTE: n = number of devices being erased.
Figure 3. Parallel-Erase Flow Diagram
TEXAS~
INsrRUMENTS
6-156
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
TMS28F512
524 288·BIT FLASH
ELECTRICALLY ERASABLE PROGRAMMABLE READ·ONLY MEMORY
SMJS513A-DECEMBER 1992-REVISED MARCH 1993
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage range, Vee (see Note 4) .............................................. -0.6 V to 7 V
Supply voltage range, Vpp ......................................................... -0.6 V to 14 V
Input voltage range (see Note 5): All inputs except A9 ............................ -0.6 V to Vee + 1 V
A9 (see Note 5) ................................... -0.6 V to 13.5 V
Output voltage range (see Note 6) ............................................. -0.6 V to Vee + 1 V
Operating free-air temperature range during read/erase/program
(NL, FML, DDL, DUL) .................................. DoC to 70°C
Operating free-air temperature range during read/erase/program
(NE, FME, DDE, DUE) .............................. - 40°C to 85°C
Operating free-air temperature range during read/erase/program
(NO, FMO, DDO, DUO) ............................ - 40° C to 125°C
Storage temperature range ........................................................ -65°C to 150°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for ex1ended periods may affect device reliability.
NOTES: 4. All voltage values are with respect to GND.
5. The voltage on any input pin may undershoot to -2.0 V for periods less than 20 ns.
6. The voltage on any output pin may overshoot to 7.0 V for periods less than 20 ns.
z
o
~
:5
a:
o
LL
Z
W
o
Z
~
c
-
HI-Z -
Figure 5. Read Cycle Timing
TEXAS
~
INSlRUMENTS
POST OFFICE BOX 1443· HOUSTON. TEXAS 77001
6-161
TMS28F512
524 288·BIT FLASH
ELECTRICALLY ERASABLE PROGRAMMABLE READ·ONLY MEMORY
SMJS513A-DECEMBER 1992-REVISED MARCH 1993
PARAMETER MEASUREMENT INFORMATION
Power-Up
and
AO-A15
Program
Command
Latch
Address
Set-Up
Program
__ "dDiiiit comm~~
te(W) 14
~ I
1_I
~
z
o
m
-z
i1
~r(W) ~ ~
I
lr--
tw(W) -+I
I
tsu(D)
HI-t'
I
I
o
12V
I
VPP
VpPL
f-.I i'I-
r-
I+-
l
I
I
--rI
yI
,
-+-fi1
1-.:
1+
I+-
r-
14- t
I
1+
twr~
tw(W)
I
--.L!....J
TI
tw(W)
I.
14-
thw(D)
-+i I+- I
I
I
Data In = COh
'J
i~
~ tdIS(~
\.
III
\....
I II I
~ I+t th(D)
•
_I
t
I I I 1 - - : - ,en(G)
I I ~ td(G) I
I I
I I
I141I
td(E)
talE) 14
'/,
'/;
'I';
'/,
'-
I I
II
I I
1"1
I I
I
I+- t' u(D) ~SU(D)
I+-
')---{I'
I I
-++1 H
I
hw(D)
~
'J7
"
IJ
«iI
1
.1
.1
It
I~
~
\Valid Oats Out
tsu(P)E
it---
~ J-ts(P)F
ts(P)R
tsu(E)P
Figure 6. Write Cycle Timing
TEXAS ~
INSTRUMENTS
6·162
I
i ~ I-
14- th(E)
Data In
I+-
-+j
...I
1
I
I
I
1
D
:
Data In = 40h
i
-..I
1
I I
:
~J
.
I
I
I
~
I
th(E)
t~h(W)
14
I
,
VCc 5V
OV
~ I+-
II
~
tsu(A)
-+I ~ tsu(E) i
1_'/Jte(W)B
,
,I
thw(D)
DQO-DQ7
-+I r- tSU(~)
1
I
3:
z
S~(E) +114-
vom....'
Standby!
~~
I
I
~
V
ol:J
~
~ J+"
i+---f-
Program
~ te(R) ---t.l
4
ter>
~ 14- th(A)
I
~
th(A) -.:
tau(E)
---.l .t--
tc~
.:.tsu(A)
»
c
Program
VerIfy
POST OFFICE BOX 1443' HOUSTON, TEXAS 77001
TMS28F512
524 288·BI1 FLASH
ELECTRICALLY ERASABLE PROGRAMMABLE READ·ONLY MEMORY
SMJS513A-DECEMBER 1992-REVISED MARCH 1993
PARAMETER MEASUREMENT INFORMATION
Program
Command
L.atch
Program
Address
Verify
and Data Programming Command
Power-Up
Set-Up
and
Program
Standby Command
AO-A15
~~~~~
I
I
I.-L
-k----+I
tsu(A)
i~
th(W)
-LI__.JA;
I
I
I
tw(E)
Vpp 12V
VPPL.
tsu(W)
II
-+I 14-
i
:
:-~~(W)B D
i":tIi I+-
-t.i I+-
r-
I
I
I
14-
-+I
tsu(D)
Data In
I
I
H-1.Jr'
:
I
~
...II
I
I
I
I
I
I
II
I
\...
-H :-
j+ tsu(W) I
I -+i 1+ t~~
tdls(G)
!~
~i
j
I
1"-
1I I
thE(D)
f--t+I
I
r-
tw(E)
I.-
I
I
t
=40h
I.-
I
~
I
thE(D)
w(E)-+l11
~SU(D).
I
I
I
I
j
I
-+t
thC'fl
~
f~'-
J+I
I
thE(A)
I
-.I r-
JT-HI-Z
-./1
oV
~
I
tSU(DI
I
I
I
VCC
I+-
-+I
I
14--- tc(R)
4
Standby/
Power-Down
\....
~~l ·t~~,~~~! PI~:
It! I
I
hElD)
5V
cr'l
~t
U',
I s(A)
...-! 14-
I
t
I
I
__---r
tsu(W) -.
·~
I
-.II 14-I
thE(A)
w
I
1
tc(W) ---+I
~~
""(W) 14
DQO-DQ7
Program
Verification
I
I
"
i+-!-
II
I I
Data In
Data In
=COh
td(E) ~ I
ta(E)
I
~I
'/.
'/;
'/;
Valid Data Out
'L11_
-r
I
ts(P)F
j+- tsu(E)P
Figure 7. Write Cycle (Alternative CE-Contro"ed Writes) Timing
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
a:
o
u.
z
w
o
\... z
~
tsu(P)E
ts(P)R
~
~
toIJI It~
\
-j.----.I
',';
14
I II I
-+t
th(D)
I II
te~(G)
I I~ td(G) I
II'
,I
I I
~~
z
o-
6-163
C
th(E)
1
I
I
j+ tsu(E) 1
tsu(E)
I
I
I
I
I
i+
I
~14I -+I i.114-4---1.0+-: tw~(W)
POST OFFICE BOX 1443· HOUSTON, TEXAS 77001
ts(P)F
TMS28F210
1 048 576-BIT FLASH
ELECTRICALLY ERASABLE PROGRAMMABLE READ-ONLY MEMORY
SMJS210-DECEMBER 1992
•
•
•
•
•
•
•
•
•
•
N PACKAGEt
(TOP VIEW)
Organization ... 64K x 16 Flash Memory
Pin Compatible with Existing 1-Megabit
EPROMs
All Inputs/Outputs TTL Compatible
Maximum Access/Minimum Cycle Time:
Vee ± 10%
Vpp
E
D015
D014
D013 l
D012 l
DOll
D010
D09
DOB
'28F210-10
100 ns
'28F21 0-12
120 ns
'28F210-15
150 ns
'28F21 0-17
170 ns
Industry-Standard Programming Algorithm
PEP4 Version Available With 168-Hour
Burn-In, and Choice of Operating
Temperature Ranges
Chip Erase Before Reprogramming
10000,1 000, and 100 Program/Erase
Cycles
Low Power Dissipation (Vee = 5.50 V)
- Active Write ... 55 mW
- Active Read ... 165 mW
- Electrical Erase ... 82.5 mW
- Standby ... 0.55 mW
(CMOS-Input Levels)
Automotive Temperature
Range: - 40°C to + 125°C
Vss
DO?
D06
D05
D04
D03
D02
DOl [
r
DOO
G
1 V
40
VCC
2
3
4
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
W
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
The TMS28F21 a Flash EEPROM is offered in a
dual in-line plastic package (N suffix) designed for
insertion in mounting-hole rows on 15,2 mm
(600-mil) center and a 44-lead plastic leaded-chip
carrier package using 1 ,25 mm (50-mil) lead
spacing (FN suffix). The TMS28F210 is offered
with three choices of temperature ranges of
O°C to 70°C (NL and FNL suffixes), -40°C to 85°C
(NE and FNE suffixes), and -40°C to 125°C (NO
and FNO suffixes). All packages are offered with
168-hour burn-in.
Vss
AS
A7
A6
A5
A4
A3
A2
Al
AD
;:
w
:>
w
a:
(TOP VIEW)
6 5 4 3
The TMS28F21 a is available in 10 000, 1 000, and
100 program/erase endurance cycle versions.
Al0
A9
FN PACKAGEt
description
The TMS28F21 a is a 1048 576-bit, programmable
read-only memory that can be electrically
bulk-erased and reprogrammed.
NC
A15
A14
A13
A12
All
c..
Vss
NC
D06
D05
::>
~
7
DOll
D010
D09
DOS
IU
2 1 44 43 42 41 40
8
C
o
a:
9
10
11
c..
12
13
14
31
15
16
17
29
18 19 20 21 22 232425262728
80 0
~ 0 8 It!) ~ a: : :(
00
~
:;e ::!:
t The packages are shown for pinout reference only.
PIN NOMENCLATURE
AG-A15
Address Inputs
E
Chip Enable
Output Enable
G
Ground
VSS
NC
No Connection
Program
W
DOG-D015 Inputs (programming)/Outputs
5·V Supply
VCC
12·V Power Supply;
Vpp
; Only in program mode.
PRODUCT PREVIEW Informilion conClI'ftI produCtlIn thl form,llve or
design ph... of developmenL Chll'lctetililc dill Ind other
lpeclflcallonl In dllign gOiIi. T'Xlllnltnlmlntll'llll'V1I the right 10
chlnga or dllcontinul th... producll wtthout noUce.
TEXAS
~
Copyright © 1992. Texas Instruments Incorporated
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
6-165
TMS28F210
1 048 576·81T FLASH
ELECTRICALLY ERASABLE PROGRAMMABLE READ·ONLY MEMORY
SMJS210-DECEMBER 1992
device symbol nomenclature
TMS28F210
-12
C4
FN
L=
L
4
PEP4Bum-ln
4 168-Hour Burn-In
(Blank If no burn-In)
=
Temperature Range DesIgnator
L
O'C to 70'C
E = - 40'C to 85'C
Q = - 40'C to 125'C
=
' - - - - - - - - - - Package DesIgnator
PlastIc Dual-In-Une Package
N
FN
PlastIc Leaded ChIp CarrIer
=
=
L -_ _ _ _ _ _ _ _ _ _
"'D
Program/Erase Endurance
C4 = 10,000 Cycles
C3 = 1,000 Cycles
C2 = 100 Cycles
' - - - - - - - - - - - - - Speed DesIgnator
-10 = 100 ns
-12 = 120 ns
-15 = 150 ns
-17 = 170 ns
:a
o
c
c:
o
-I
"'D
:a
m
<
m
=E
TEXAS
~
INsrRUMENTS
6-166
POST OFFICE BOX 1443· HOUSTON, TEXAS 77001
TMS28F210
1 048 576·BIT FLASH
ELECTRICALLY ERASABLE PROGRAMMABLE READ·ONLY MEMORY
SMJS21 O-DECEMBER 1992
functional block diagram
Vcc - . VSS - . Vpp -----~~--____+1
'--..,------,---'
I j j - -.......
Program/Erase
Stop Timer
Command Register I---~
STB
E------~r---------_r-~
G-----~r---------~-~
Chip Enable
Output Enable
Logic
3:
UJ
Column-Gating
~a:
1 048 576-Blt
Array Matrix
tO
::l
C
STB
A
d
Column-Decoder
d
r
c..
e
AO-A15
B
B
L
a
Row-Decoder
t
c
o
a:
h
c..
TEXAS
~
INsrRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
6-167
TMS28F210
1 048 576·BIT FLASH
ELECTRICALLY ERASABLE PROGRAMMABLE READ·ONLY MEMORY
SMJS21G--DECEMBER 1992
Table 1. Operation Modes
FUNCTION
MOOEt
Vpp§
E
G
AD
A9
W
OQD-OQI5
1
2
20
21
31
39
3-10,12-19
NPACKAGE
FNPACKAGE
Read
Read!
Write
2
3
22
24
35
43
21-14,11-4
Read
VPPL
VIL
VIL
xt
X
VIH
Data Out
Output Disable
VpPL
VIL
VIH
HI-Z
VpPL
VIH
X
X
X
VIH
Standby and Write Inhibit
X
X
X
HI-Z
Signature
VPPL
VIL
VIL
VH+
VIH
Read
VPPH
VIL
VIL
Output Disable
VPPH
VIL
VIH
Standby and Write Inhibit
VpPH
VIH
X
Write
VPPH
VIL
VIH
VIL
VIH
X
X
X
X
X
X
X
X
MFG Code 0097h
Device Code 00E5h
VIH
Data Out
VIH
HI-Z
X
HI-Z
VIL
Data In
t X can be VIL or VIH
;11.5V
w
a:
c..
I-
NOTE 1: Modes of operation are defmed In Table 1.
t Description of Terms
EA
Address of memory location to be read during erase verify.
RA
Address of memory location to be read.
PA
Address of memory location to be programmed. Address is latched on the falling edge of W.
RD
Data read from location RA during the read operation.
EVD Data read from location EA during erase verify.
PO
Data to be programmed at location PA. Data is latched on the rising edge of W.
PVD Data read from location PA during program verify.
U
~
C
o
a:
c..
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS nOO1
3:
6-169
TMS28F210
1 048 576-BIT FLASH
ELECTRICALLY ERASABLE PROGRAMMABLE READ-ONLY MEMORY
SMJS21 G-OECEMBER 1992
logic symbol t
AO
A1
A2
A3
A4
AS
A6
A7
A8
A9
A10
All
A12
A13
A14
A15
"tJ
E
2
G
20
39
Vi
:D
o
C
OQO
c:
o
OQl
OQ2
OQ3
OQ4
OQ5
OQ6
OQ7
OQ8
OQ9
OQ10
OQ11
OQ12
OQ13
OQ14
OQ15
-I
"tJ
:D
m
S
m
=E
21
22
23
24
25
26
27
28
29
31
32
33
34
35
36
37
0
> A65~
15
,...
Gl
[PWROWNI
~ G2
l.b
19
1-.18
17
16
15
14
13
12
10
9
8
7
6
5
4
3
FLASH
EEPROM
65536 x 16
1,2 EN (READ)
lC3 (WRITE)
,
A,30
V4
I'"
A,Z4- -
.....
~
.
~::
.....
t This symbol is in accordance with ANSI/IEEE Std 91-1984 and
lEe Publication 617-12.
Pin numbers shown are for the N package.
TEXAS . "
INSTRUMENTS
6-170
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
TMS28F210
1 048 576·BIT FLASH
ELECTRICALLY ERASABLE PROGRAMMABLE READ·ONLY MEMORY
SMJS210-DECEMBER 1992
command definitions
read command
Memory contents can be accessed while Vpp is high or low. When Vpp is high, writing OOOOh into the command
register invokes the read operation. Also, when the device is powered up, the default contents of the command
register are OOOOh and the read operation is enabled. The read operation remains enabled until a different, valid
command is written to the command register.
signature mode command
The signature mode is activated by writing 0090h into the command register. The manufacturer's code (97h)
is identified by the value read from address location OOOOh, and the device code (00E5h) is identified by the value
read from address location 0001 h.
set-up erase/erase commands
The erase algorithm initiates with E = VIL, iN =VIL, G = VIH, Vpp = 12V, and Vee = 5V. To enter the erase mode,
write the set-up erase command, 0020h, into the command register. After the TMS28F21 0 is in the erase mode,
writing a second erase command, 0020h, into the command register invokes the erase operation. The erase
operation begins on the rising edge of Wand ends on the rising edge of the next iN. The erase operation requires
10 ms to complete before the erase-verify command, OOAOh, can be loaded.
.
Maximum erase timing is controlled by the internal stop timer. When the stop timer terminates the erase
operation, the device enters an inactive state and remains inactive until a valid erase verify, read, or reset
command is received.
~
->
W
w
erase-verify command
All words must be verified following an erase operation. After the erase operation is complete, an erased word
can be verified by writing the erase-verify command, OOAOh, into the command register. This command causes
the device to exit the erase mode on the rising edge of W. The address of the word to be verified is latched on
the falling edge of W. The erase-verify operation remains enabled until a valid command is written to the
command register.
To determine whether or not all the words have been erased, the TMS28F21 0 applies a margin voltage to each
word. If FFFFh is read from the word, then all bits in the designated word have been erased. The erase-verify
operation continues until all of the words have been verified. If FFFFh is not read from a word, then an additional
erase operation needs to be executed. Figure 2 shows the combination of commands and bus operations for
electrically erasing the TMS28F21 O.
set-up program/program commands
The programming algorithm initiates with E = VIL, W = VIL, G = VIH, Vpp = 12 V, and Vee = 5 V. To enter the
programming mode, write the set-up program command, 0040h, into the command register. The programming
operation will be invoked by the next write-enable pulse. Addresses are latched internally on the falling edge
of W, and data is latched internally on the rising edge of W. The programming operation begins on the rising
edge ofW and ends on the rising edge of the nextW pulse. The program operation requires 10 [ls for completion
before the program-verify command, OOCOh, can be loaded.
Maximum program timing is controlled by the internal stop timer. When the stop timer terminates the program
operation, the device enters an inactive state and remains inactive until a valid program verify, read, or reset
command is received.
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443· HOUSTON, TEXAS 77001
6-171
a:
a..
....
o
::J
C
o
a:
a..
TMS28F210
1 048 576·BIT FLASH
ELECTRICALLY ERASABLE PROGRAMMABLE READ·ONLY MEMORY
SMJS21 D-OECEMBER 1992
program-verify command
The TMS28F21 0 can be programmed sequentially or randomly because it is programmed one word at a time.
Each word must be verified after it is programmed.
The program-verify operation prepares the device to verify the most recently programmed word. To invoke the
program-verify operation, OOCOh must be written into the command register. The program-verify operation will
end on the rising edge of W.
While verifying a word, the TMS28F21 0 applies an internal margin voltage to the designated word. If the true
data and programmed data match, programming can continue to the next designated word location; otherwise,
the word must be reprogrammed. Figure 1 shows how commands and bus operations are combined for word
programming.
reset command
To reset the TMS28F21 0 after set-up erase command or set-up program command operations without changing
the contents in memory, write OOFFh into the command register two consecutive times. After executing the reset
command, a valid command must be written into the command register to change to a new state.
Fastwrite algorithm
"tJ
:c
o
c
c
o
The TMS28F210 is programmed using the Texas Instruments Fastwrite algorithm shown in Figure 1. This
algorithm programs in a nominal time of two seconds.
Fasterase algorithm
The TMS28F210 is erased using the Texas Instruments Fasterase algorithm shown in Figure 2. The memory
array needs to be completely programmed (using the Fastwrite algorithm) before erasure begins. Erasure
typically occurs in one second.
-t
"tJ
:c
m
<
m
parallel erasure
To reduce total erase time, several devices may be erased in parallel. Since each Flash EEPROM may erase
at a different rate, every device must be verified separately after each erase pulse. After a given device has been
successfully erased, the erase command should not be issued to this device again. All devices that complete
erasure should be masked until the parallel erasure process is finished. See Figure 3, Parallel Erase Flow
Diagram.
:e
Examples of how to mask a device during parallel erase include driving the device's E pin high, writing the read
command (OOOOh) to the device when the others receive a setup erase or erase command, or disconnecting
it from all electrical signals with relays or other types of switches.
TEXAS ~
INSTRUMENTS
6·172
POST OFFICE BOX 1443· HOUSTON. TEXAS 77001
TMS28F210
1 048 576·BIT FLASH
ELECTRICALLY ERASABLE PROGRAMMABLE READ·ONLY MEMORY
SMJS21 O-OECEMBER 1992
-T
Bus
Operation
Comments
Command
Inltlallza
Address
Standby
Walt for Vpp to Ramp to
VpPH (see Note 2)
Setup
Initialize Pulse Count
=0040h
Write
SetUp
Program
Write
Data
Write
Write Data
Valid Address/Data
Standby
Write
Walt
ProgramVerify
=10 ItS
~
=
Data OOCOh; Ends
Program Operation
w
:>w
=61-'s
Standby
Walt
Read
Read Word to Verify
Programming; Compare
Output to Expected Output
0::
Interactive
Mode
a..
I-
o
~
c
o
0::
a.
Write
Read
Power
Down
1
NOTES:
Standby
=
Data OOOOh; Resets
Register for Read
Operations
Walt for Vpp to Ramp to
VPPL (see Note 3)
2. Refer to the recommended operating conditions for the value of VPPH.
3. Refer to the recommended operating conditions for the value of VpPL.
Figure 1. Programming Flowchart: Fastwrite Algorithm
TEXAS ~
INSIRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
6-173
TMS28F210
1 048 576·BIT FLASH
ELECTRICALLY ERASABLE PROGRAMMABLE READ·ONLY MEMORY
SMJS21 O-DECEMBER 1992
Bus
Operation
Command
Comments
Entire Memory Must = OOOOh
Before Erasure
Use Fastwrlte
Programming Algorithm
Initialize Addresses
Standby
Walt for Vpp to Ramp to
VPPH (see Note 2)
Setup
"'C
Initialize Pulse Count
Write
SetUp
Erase
Data = 0020h
Write
Erase
Data = 0020h
:II
o
Standby
C
Interactive
Mode
c:
o-I
"'C
Write
Walt = 10ms
Erase
Verify
Addr = Word to Verify;
Data = OOAOh; Ends the
Erase Operation
:II
Standby
Walt = 6 itS
S
Read
Read Word to Verify Erasure;
Compare Output to FFFFh
m
m
~
Write
Power
Down
NOTES:
Read
Standby
2 Refer to the recommended operating conditions for the value of VPPH.
3 Refer to the recommended operating conditions for the value of VPPL.
Figure 2. Flash-Erase Flowchart: Fasterase Algorithm
TEXAS ~
INSTRUMENTS
6-174
POST OFFICE BOX 1443· HOUSTON. TEXAS 77001
Data = OOOOh; Resets
Reglater for Read Operations
Walt for Vpp to Ramp to
VpPL (see Note 3)
TMS28F210
1 048 576·BIT FLASH
ELECTRICALLY ERASABLE PROGRAMMABLE READ-ONLY MEMORY
SMJS21(H)ECEMBER 1992
w
==
:>
w
Give Erase
Command To
All Unmasked
Devices
a::
fl.
I-
o
No
::l
C
o
a::
fl.
Give Read
Command To
All Devices
Give Read
Command To
All Devices
NOTE: n = number of devices being erased.
Figure 3. Parallel-Erase Flow Diagram
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS nOO1
6-175
TMS28F210
1 048 576-BIT FLASH
ELECTRICALLY ERASABLE PROGRAMMABLE READ-ONLY MEMORY
SMJS21 O-DECEMBER 1992
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage range, Vee (see Note 4) .............................................. -0.6 V to 7 V
Supply voltage range, Vpp ......................................................... -0.6 V to 14 V
Input voltage range (see Note 5): All inputs except A9 ............................ -0.6 V to Vee + 1 V
A9 (see Note 5) ................................... -0.6 V to 13.5 V
Output voltage range (see Note 6) ............................................. -0.6 V to Vee + 1 V
Operating free-air temperature range during read/erase/program
(NL, FNL) ............................................
to 70 0
Operating free-air temperature range during read/erase/program
(NE, FNE) ......................................... - 40 0 e to 85°e
Operating free-air temperature range during read/erase/program
(NQ, FNQ) ....................................... - 40° e to 125°e
Storage temperature range ....................................................... -65°e to 1500 e
ooe
e
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 4. All voltage values are with respect to GND.
5. The voltage on any input pin may undershoot to -2.0 V for periods less than 20 ns.
6. The voltage on any output pin may overshoot to 7.0 V for periods less than 20 ns.
"'C
:xJ
recommended operating conditions
o
'28F210-10
'28F21 0-12
'28F21 0-15
'2BF21 0-17
C
C
o-I
"'C
:xJ
m
:S
m
=E
Vee
Vpp
Supply voltage
Supply voltage
During write/read/flash erase
During read only (Vppu
High-level dc input voltage
VIL
Low-level dc input voltage
5
11.4
TTL
CMOS
TTL
CMOS
TEXAS
~
INSTRUMENTS
6-176
TYP
4.5
a
During write/read/flash erase (VPPH)
VIH
MIN
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
2
Vee- a.5
-0.5
GND-0.2
12
UNIT
MAX
5.5
V
Vee+ 2
V
12.6
V
Vee+0.5
V
Vee+0.5
O.B
GND+0.2
V
TMS28F210
1 048 576·BIT FLASH
ELECTRICALLY ERASABLE PROGRAMMABLE READ·ONLY MEMORY
SMJS21o-DECEMBER 1992
electrical characteristics over full ranges of operating conditions
PARAMETER
VOH
High-level output voltage
VOL
Low-level output voltage
II
Input current (leakage)
10
Output current (leakage)
IpP1
VPP supply current (read/standby)
TEST CONDITIONS
MIN
TYP
10H =-2.5 mA
2.4
10H =-100~
Vee- O.4
MAX
UNIT
V
IOL=5.8 mA
0.45
IOL= 100~
0.1
V
IAll except A9
VI =Ot05.5V
±1
IA9
VI =Oto 13V
±200
~
Vo=OtoVee
±10
~
VPP = VpPH. read mode
200
~
VPP =VpPL
±10
~
IpP2
VPP supply current (during program pulse)
(see Note 7)
VPP =VpPH
50
mA
IpP3
VPP supply current (during flash erase)
(see Note 7)
VPP =VPPH
50
mA
IpP4
VPP supply current (during program/erase verify)
(see Note 7)
VPP =VPPH
5.0
mA
1
mA
100
~
ITTL-Input level
Vee = 5.5 V. E = VIH
I CMOS-Input level
Vee = 5.5 V. E = Vee
~
Ices
Vee supply current (standby)
lee1
Vee supply current (active read)
Vee = 5.5 V. E = VIL. f = 6 MHz.
outputs open
50
mA
lee2
Vee average supply current (active write)
(see Note 7)
Vee = 5.5 V. E = VIL. programming
in progress
10
mA
:>
w
lee3
Vee average supply current (flash erase)
(see Note 7)
Vee = 5.5 V. E = VIL. erasure in
progress
15
mA
a.
lee4
Vee average supply current (program/erase verify)
(see Note 7)
Vee = 5.5 V. E = VIL. VPP = VpPH.
program/erase-verify in progress
15
mA
NOTE 7: Not 100% tested; characterization data available.
w
0:::
I-
o
:::>
c
o0:::
a.
TEXAS ~
INSfRUMENTS
POST OFFICE BOX 1443· HOUSTON. TEXAS 77001
6-177
TMS28F210
1 048 576·BIT FLASH
ELECTRICALLY ERASABLE PROGRAMMABLE READ·ONLY MEMORY
SMJS21 ()-OECEMBER 1992
capacitance over recommended ranges of supply voltage and operating free-air temperature,
= 1 MHzt
f
PARAMETER
Ci
Input capacitance
Co
Output capacnance
TEST CONDITIONS
MIN
=0 , f =1MHz
Vo =0 , f =1 MHz
VI
TYP
MAX
UNIT
6
pF
12
pF
t Capacitance measurements are made on sample basis only.
PARAMETER MEASUREMENT INFORMATION
2.08 V
Output
Under Test
---1
RL = SOD Q
T
CL
= 100 pF
"'C
::IJ
Figure 4. AC Test Output Load Circuit
o
C
C
AC testing Input/output wave forms
o
2. 4V
-I
O.4SV
"'C
::IJ
=X
2V
O.BV
O.!~
X,-__
AC testing inputs are driven at 2.4 V for logic high and 0.45 V for logic low. liming measurements are made at
2 V for logic high and 0.8 V for logic low on both inputs and outputs. Each device should have a 0.1-J.!F ceramic
capacitor connected between Vee and Vss as close as possible to the device pins.
m
~
m
:e
TEXAS
~
INSTRUMENTS
6-178
POST OFFICE BOX 1443' HOUSTON. TEXAS 77001
TMS28F210
1 048 576·BIT FLASH
ELECTRICALLY ERASABLE PROGRAMMABLE READ·ONLY MEMORY
SMJS21(H)ECEMBER 1992
switching characteristics over full ranges of recommended operating conditions
DESCRIPTION
TEST
CONDITIONS
ALTERNATE
SYMBOL
'28F21D-12
'28F21D-10
MIN
MAX
MIN
'28F21D-15
MAX
MIN
MAX
'28F21 0-17
MIN
MAX
UNIT
ta(A)
Access time from
address
tAVQV
100
120
150
170
ns
tatE)
Access time from
chip enable
tELQV
100
120
150
170
ns
len (G)
Access time from
output enable
tGLQV
45
50
55
60
ns
leeR)
Read cycle time
Id(E)
Delay time, chip
enable low to low-Z
output
Id(G)
Delay time, output
enable low to low-Z
output
ldis(E)
tAVAV
100
120
150
170
ns
tELQX
0
0
0
0
ns
tGLQX
0
0
0
0
ns
Chip disable to hi-Z
output
tEHQZ
0
55
0
55
0
55
0
55
ns
ldis(G)
Hold time, output
enable to hi-Z output
tGHQZ
0
30
0
30
0
35
0
35
ns
th(D)
Hold time, data valid
from address, E, or
tAXQX
0
0
0
0
ns
Write recovery time
before read
twHGL
6
6
6
6
jlS
twr(W)
CL= 100pF
1 Series 74
TTL Load
Input tr " 20 ns
Input tf " 20 ns
Gt
3:
w
~
a:
t Whichever occurs first.
a.
AC characterlstlcs-wrlte/erase/program operations
I-
DESCRIPTION
ALTERNATE
SYMBOL
'28F21D-10
'28F21 0-12
'28F21 0-15
'28F21 0-17
UNIT
MIN
TYP
MIN
TYP
MIN
TYP
MIN
TYP
1e(W)
WrHe cycle time
tAVAV
100
120
150
170
ns
lsu(A)
Address setup time
tAVWL
0
0
0
0
ns
theA)
Address hold time
twLAX
55
60
60
70
ns
tsu(D)
Data setup time
tDVWH
50
50
50
50
ns
thw(D)
Data hold time
twHDX
10
10
10
10
ns
twr(W)
WrHe recovery time before read
twHGL
6
6
6
6
~s
trr(W)
Read recovery time before wrHe
tGHWL
0
0
0
0
~s
lsu(E)
Chip enable setup time before write
tELWL
20
20
20
20
ns
theE)
Chip enable hold time
twHEH
0
0
0
0
ns
tw(W)
Write pulse duration (see Note 8)
twLWH
60
60
60
60
ns
twh(W)
Write pulse duration high
twHWL
20
20
20
20
ns
Ie(W)B
Duration of programming operation
tWHWHl
10
10
10
10
Ie(E)B
Duration of erase operation
twHWH2
9.5
10
9.5
10
9.5
10
9.5
~s
10
ms
lsu(P)E
VPP setup time to chip enable low
tyPEL
1.0
1.0
1.0
1.0
~s
tsu(E)P
Chip enable, setup time to VPP ramp
tEHVP
100
100
100
100
ns
Is(P)R
VPP rise time
tyPPR
1
1
1
1
~s
Is(PlF
Vppfalltlme
tyPPF
1
1
1
1
~s
NOTE 8: Rise/fall time" 10 ns.
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 1443· HOUSTON. TEXAS 77001
6-179
o
::>
c
o
a:
a.
TMS28F210
1 048 576·BIT FLASH
ELECTRICALLY ERASABLE PROGRAMMABLE READ·ONLY MEMORY
SMJS21 O-DECEMBER 1992
alternative CE-controlled writes
DESCRIPTION
"'D
:c
o
c
c
o
MIN
'28F01D-12
'28F010-15
'28F010-17
UNIT
MAX
MIN
MAX
MIN
MAX
MIN
MAX
tc(W)
Write cycle time
tAVAV
100
120
150
170
ns
lsu(A)
Address setup time
tAVEL
0
0
0
0
ns
thECA)
Address hold time
tELAX
75
80
80
90
ns
lsu(D)
Data setup time
tDVEH
50
50
50
50
ns
thE(D)
Data hold time
tEHDX
10
10
10
10
ns
twr(E)
Write recovery time before read
tEHGL
6
6
6
6
1'8
trr(E)
Read recovery time before write
tGHEL
0
0
0
0
1'8
lsu(W)
Write enable setup time before
chip enable
twLEL
0
0
0
0
ns
th(W)
Write enable hold time
tEHWH
0
0
0
0
ns
tw(E)
Write pulse duration
tELEH
70
70
70
80
ns
twh(E)
Write pulse duration high
tEHEL
20
20
20
20
ns
tsu(P)E
VPP setup time to chip enable low
tyPEL
1.0
1.0
1.0
1.0
1'8
tc(W)8
Duration of programming
operation
tEHEH
10
10
10
10
its
PARAMETER MEASUREMENT INFORMATION
-I
"'D
:c
m
<
-
'28F01D-10
ALTERNATE
SYMBOL
1 + 1 4 - - - - - - - tc (R)
-------+1.1
I
AQ.-A15
m
A_d_dr_e_ss_v_a_lId__________
_ _ _ _. . J _
14
:e
1
>t~1___________
.1
la(A)
~~~I-----------------I
I
E------~~~____~:~----~~I
I 1
I
I 1 - - la(E) ~
--------+1-""'"
I
G
I ~
I
w - - Iwr(W) --+--I I
I
I"
I
I j+- tan(G) -+j
I"
I
I
I
w----./
I
I
I
~ Id(G) I
I +1
td(E)
DQQ.-DQ15
HI-Z
14
.1
I
I
?1I I
I
I I
II
I I+----- Idls(G)
I+- th(D) -+t
I
(««@
OuputValid
Figure 5. Read Cycle Timing
TEXAS
~
INSTRUMENTS
6-180
i+--lcIls(E)----+i
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
I
I
I
I
I
I
~
I
}»»»}-
HI-Z-
TMS28F210
1 048 576·BIT FLASH
ELECTRICALLY ERASABLE PROGRAMMABLE READ·ONLY MEMORY
SMJS21 ()-OECEMBER 1992
PARAMETER MEASUREMENT INFORMATION
Power-Up
and
Program
Set-Up
Program
Program
Verification
Standby!
AO-A15
V
',.11
,..!+-
I
~14-----tol--
I I
w
,
thw(O)
Vee
5V
OV
12V
Vpp
VpPL
-.i
I
tsu(O)
I
3:
w
_---{.
,
tw~
OQOOQ15
I
~-'T'"""I<
I
I
f+I 1"1~I 1
~
a:
1
I.-
c.
-r-HI-~
t;
I
1
I
I
I
I -+j
I
~ tsu(P)E
1
-V:
I -.J I..
I
-+i
',\
'/;
I'A
I I
:::J
C
'/j
'/J
rr-
----+j
ts(P)R
14- ts(P)F
1
1-
tsu(E)P
Figure 6. Write Cycle Timing
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
6-181
o
a:
c.
TMS28F210
1 048 576·BIT FLASH
ELECTRICALLY ERASABLE PROGRAMMABLE READ·ONLY MEMORY
SMJS21O-0ECEMBER 1992
PARAMETER MEASUREMENT INFORMATION
Program
Command
Latch
Program
Address
Verify
and Data Programming Command
Power-Up
Set-Up
and
Program
Standby Command
AO-A15
~-~~~
I
.1+-----+j
+-
I
tc(W)
I
..,(W) I~
tsu(A) ~
thEtA)
Iii
I
I
I
th(W)
c:
o
-f
DQODQ15
"
:c
m
S
m
:E
~[~ trr(E)
~;
-Y I'M.J;
I
I
I
I
I
c
VCC
12V
VpPL
I
: -,
tau(DI
I,r-HI-Z
--,
I
I
I
I
I
I
1 -+I
I
-+I
r-
II
I
I
I
I+-
tsu(W)
-+i
-+II+- thl'fll
1
~'J";'
1 _ tc(w)B
I
\l:twh(E)
I
I!
-+I ,...
I
I+-
I
II
I
j+- thEtA)
I
\...
j+ tsu(W) 1
tdls(G)
I -+I 1+ thJ~11
I
1
'
I
~
I
I
I
1
---' I
' . I I. b
I
I-tw~!!
!h(E)
7i :-
~,\l..L.Y._i
1I
I II I.
14
.
I+- thE(D)
1
[
tIW(E)
I
1
I ;.J
Data In
I.-
thE(D)
I"" I
tw(E) -+I l.- I
~SU(D)
I.-
I
Data In = 0040h
~
f~'-
~t
'J
I au tAl
I
thEiD)'
I£..
I
I~ r
tW(E)"': II.-- I
:: -Y
Vpp
-+I I+-
'I
ill. I
V
I
E
1
..,~
1
I
Data In =OOCOh
I
'J
I
I
I
I
I
I
II
I, I
I'--+t-, tel (G), I
IJ
I~
I
!t~
I
I I
\Valid Data Out
I .1
i
«i
td(E) ~
t:_.J
alE) .,..------...
\...
!
~ tau(P)E
'/;
'h
I
I
I'"
"---111
1
i -.:
ts(P)F ~
ta(P)R
j+-- tsu(E)P
Figure 7. Write Cycle (Alternative CE-Controlled Writes) Timing
1ExAs
~
INSTRUMENTS
6-182
o . . _. \ . . .
-+j
th(D)
~ ten(G)
'/;
',';
I
I
-+I
Standby!
Power-Down
I
14-- tc(R) ~
' - - +-
1
-+I
-.II I+-
:--'--rf
i tsu(W) -~ ~
"o:c
Program
Verification
POST OFFICE BOX 1443· HOUSTON, TEXAS 77001
TMS28F210
1 048 576·BIT FLASH
ELECTRICALLY ERASABLE PROGRAMMABLE READ·ONLY MEMORY
SMJS21 O-DECEMBER 1992
PARAMETER MEASUREMENT INFORMATION
Power-Up
and
AO--A15
I.
e(W)
I
: tsu(E)
I
if
rl trr(W)
I
~I
14--
~~
i+
I
-+II+-
I
I
/II
I
I
tw(W)
I
!r-
Vpp
12V
VpPl
+.i
I.-
-+j ~
:A
I
Erase
i--4-
I+-
I
I.-
~ ;..
-+i
theE)
»
I.- theA)
I
lsu(A)
I
~ tsu(E)
~
I
1
I
14-
1
:
I
I(W)
theE)
,
r---'>'
I
V I
~I+-t
III
..: I I hw(O)
I t.! I+- thw(O)
~ tw(W)
t
(W)
...I
I.- II
I
w
,>---<
tsu(O)
~sU(O)
~I.-
I
I
Data In = 0020h
Data In
I I
I I
I I
~
~ I
I II
I II I
j4- tdls(G)
I III
rl
\.
I II I
~ j+l th(O) \...
IIII
,I
I : I I i te~(~)
II I I.----.I-!" -, I td(G) I
I I
I
I
n
I
=OOAOh
'/J
j4- tdls(E)
')~
j4-- twr(W)
r - Ic(E)B ~
=0020h
'.'~
Yo....
~~
tsu(E)
-.jl.
Data In
Standby!
l-- te(R) ~
----.t
1c(W)
-+I
~
I
I
I
:: ---Y :
I
-+i
1:---
~
1+14--I~"": tw~
HI-IZ
I
I
Vee
I
I
III
tsu(O)
-----1
I
tc(W)
I ~
I theE)
thW(O)'
OQO-OQ15
Erase
Verify
Erase
~~ c.mm~~
t
w
Set-Up
Erase
I I
I I
Id(E) ~
talE) I.
~I
»p}-~
::w
:>
w
a:
a..
....
()
,/,
::J
C
tsu(P)l
'I',
I I I
I -..J I+- ts(P)l
I I
-+J !4- tsu(E)P
~
I I
ts(P)F
-J
j4-
Figure 8. Flash-Erase Cycle Timing
TEXAS ~
INSfRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
6-183
o
a::
a..
TMS28F210
1 048 576·BIT FLASH
ELECTRICALLY ERASABLE PROGRAMMABLE READ·ONLY MEMORY
SMJS210-DECEMBER 1992
TEXAS ."
INsrRUMENTS
6-184
POST OFFICE BOX 1443' HOUSTON, TEXAS 77001
TMS28F040
4194 304·BIT FLASH ELECTRICALLY ERASABLE
PROGRAMMABLE READ·ONLY MEMORY
SMJS04o-0ECEMBER 1992
•
•
•
•
•
•
•
•
•
•
•
•
Organization ... 512K x 8
Separately Erasable 32K Byte Blocks
Two Power Supplies (5 V and 12 V)
100% TTL-Level Control Inputs
Fully Automated On-Chip Erase and Byte
Program Operations
RAM-Like Write Setup/Read Timings for
Standard Processor Interface
10000,1000, and 100 Program/Erase Cycle
Versions
Automotive Temperature Range:
- 40°C to 125°C
Low Power Dissipation (Vee =5.50 V)
- Active Write .•• 55 mW
- Active Read ••. 165 mW
- Electrical Erase ... 82.5 mW
- Standby ... 0.55 mW
(CMOS-Input Levels)
Pin Compatible With Existing 4-Megabit
EPROMS
All Inputs/Outputs TTL Compatible
Chip Erase Before Reprogramming
NPACKAGEt
(TOP VIEW)
Vpp
A16
A5
A9
A4
A3
A2
A1
A11
G
A10
E
AO
OQ7
OQ6
OQ5
OQ4
OQ3
OQO
OQ1
OQ2
VSS
3:
w
>
w
a:
t The package is shown for pinout reference only.
PIN NOMENCLATURE
AO-A18
E
description
VCC
A18
A17
A14
A13
A8
Address Inputs
Chip Enable
Output Enable
Data InlData Out
No Internal Connection
12-V Power Supply
5-V Power Supply
Ground
G
DOO-D07
The TMS28F040 is a 4 194304 bit, programmable
NC
read-only memory that can be electrically erased
Vpp
blOCk-erased)
and
(bulk-erased
and
VCC
re-programmed. This device is offered in 32-pin
VSS
plastic DIP and 40-pin TSOP packages. The
TMS28F040 is organized as 16 independent 32K byte blocks. Blocks may be dynamically marked read-only
by configuring soft protection registers with command sequences. Embedded byte write and chip/block erase
functions are fully automated by an on-chip write state machine (WSM), thus releasing the system processor
for other tasks. A suspend/resume feature allows access to unaltered memory blocks during erase operations.
The TMS28F040 Flash EEPROM is offered in a dual in-line plastic package (N suffix) designed for insertion in
mounting-hole rows on 15,2 mm (600-mil) centers, a 40-lead thin small outline package (DD suffix), and reverse
pinout TSOP package (DU suffix). The TMS28F040 is offered with two choices of temperature ranges of
O°C to 70°C (NL, DDL, and DUL suffixes) and - 40°C to 125°C (NO, DDO, and DUO suffixes).
operation
Device operations are selected by writing JEDEC standard commands with conventional microprocessor
timings into a command register through the I/O pins (DOO-D07) while Vpp VPPH. The device is always in
the read-only mode when Vpp =VPPL. The content of the command register acts as input to an on-Chip state
machine. The command register latches commands as issued by system software and is not altered by write
state machine (WSM) actions. It defaults to read array mode upon initial power-up. With an appropriate
command written to the command register, standard processor accesses output stored data, device/mfg codes,
or output status of program/erase operations for validation. The functions associated with altering memory
contents are program, erase, protection, and status. These functions are accessed via the command register
and validated through the status register. The signature register may be accessed while Vpp s VpPH by applying
A9 VIO' High voltage (VPPH) on Vpp enables device erasure and programming.
=
=
PRODUCT PREVIEW information .....rna producllin IhI fonnatlvt or
phi. of dlYllopmtnl. Chiraclerllilc dill and other
d"~
:C:nll:-:=I::'~'1::=:J=
:,.-::r:::stm1lht rtoht
to
.
TEXAS ~
Copyright © 1992, Texas Instruments Incorporated
INSTRUMENTS
POST OFFICE BOX 1443· HOUSTON, TEXAS 77001
6-185
c..
tO
:J
o
oa:
c..
TMS28F040
4 194 304·BIT FLASH ELECTRICALLY ERASABLE
PROGRAMMABLE READ·ONLY MEMORY
SMJS040--DECEMBER 1992
DDPACKAGEt
(TOP VIEW)
NC
NC
A11
A9
A8
A13
A14
A17
A18
Vee
Vpp
J:J
A16
A15
A12
A7
A6
A5
A4
C
NC
NC
"'C
0
C
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
0
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
0
-I
DU PACKAGEt
REVERSE PINOUT
"'C
(TOP VIEW)
NC
NC
G
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
Vss
DQ2
DQ1
DQO
AO
A1
A2
A3
NC
NC
J:J
m
:S
m
=E
NC
NC
G
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
Vss
DQ2
DQ1
DQO
AO
A1
1
2
3
4
5
6
7
8
9
10
11
14
15
16
A2
17
A3
18
19
20
NC
NC
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
\l
t The package shown is for pinout reference only.
TEXAS~
INSTRUMENTS
6·186
POST OFFICE BOX 1443· HOUSTON. TEXAS 77001
NC
NC
A11
A9
A8
A13
A14
A17
A18
Vee
Vpp
A16
A15
A12
A7
A6
A5
A4
NC
NC
TMS28F040
4194 304·BIT FLASH ELECTRICALLY ERASABLE
PROGRAMMABLE READ·ONLY MEMORY
SMJS040-0ECEMBER 1992
device symbol nomenclature
TMS28F040
-L=
L
4
PEP4 Burn-In
4 = 168-Hour Burn-In
(Blank If no burn-In)
Temperature Range Designator
O'C to
70'C
L =
E = - 40'C to
85'C
Q = - 40'C to 125'C
' - - - - - - - - - - - Package Designator
N = Plastic Dual-In-Llne Package
DD = Thin Small Outline Package
DU = Thin Small Outline Package,
Reverse Pinout
' - - - - - - - - - - - - - Program/Erase Endurance
C4 = 10,000 Cycles
C3 = 1,000 Cycles
C2 = 100 Cycles
3:
w
:>
w
' - - - - - - - - - - - - - Speed Designator
-10 = 100 ns
-12 = 120 ns
-15 = 150 ns
-17 = 170 ns
a:
a..
I-
o
:::J
C
oa::
a..
TEXAS ~
INSfRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
6-187
TMS28F040
4 194 304·BIT FLASH ELECTRICALLY ERASABLE
PROGRAMMABLE READ·ONLY MEMORY
SMJS04Q--OECEMBER 1992
functional block diagram
l
Vpp
VCC---+VSS---+-
Vpp Switch
I
Vpp HlghNCC Low
Detect
r----;:....
'"
A15-A1B
/
B
I
o
c
k
d
d
r
e
s
s
'---
"o:r:J
WrIte State
Machlne(
Timers
C
o
-I
"m
:r:J
+t
<
-
Status(
Command
Register
m
=E
/
s
'"
AO-A14
C
....
r-+---<
s
B
u
f
f
e
r
s
)
2
0
4
B
512 Col
A
d
d
r
e
s
s
r--A
d
d
r
e
32Kx8
)
32Kx8
32Kx8
32Kx8
512 Col
512 Col
32Kx8
32KxB
0
w
L
a
t
c
h
e
s
0
e
c
32KxB
512 Col
2
0
4
8
512 Col
32KxB
32KxB
w
0
e
c
0
0
d
e
r
s
512 Col
512 Col
32Kx8
32Kx8
Sensing
{\
I
Data Latches
/\
E
G
Chip Enable
Output Enable
Write Control Logic
I
I
,,/
'\
InputfOutput Buffers
0
OQO-OQ7
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POST OFFICE BOX 1443· HOUSTON, TEXAS 77001
512 Col
32KxB
512 Col
32KxB
'---
K
32Kx8
0
512 Col
d
e
r
s
32Kx8
512 Col
R
R
512 Col
32Kx8
TMS28F040
4194 304·BIT FLASH ELECTRICALLY ERASABLE
PROGRAMMABLE READ·ONLY MEMORY
SMJS04o-DECEMBER 1992
Table 1. Operation Modes
E
G
Read-Only
MODE
VIL
VIL
Vpp
A9
AD
X
X
VIL
VpPL
X
Read
VIL
Output Disable
VIL
DQO-DQ7
X
X
DOUT
VpPL
X
X
X
High-Z
DOUT
Standby
VIH
VIH
X
X
X
High-Z
Signature (Mfr)
VIL
VIL
X
VID
VIL
97h
Signature (Device)
VIL
VIL
X
79h
VIL
VIH
VPPH
VID
X
VIH
Write
X
DIN
NOTES: 1. X can be VIL or VIH for control pins or addresses, and VpPL or VpPH for Vpp.
2. Write/Erase operations will continue during standby until completed.
3. Block erase, chip erase, and byte programming commands are assured only when VPP = VpPH.
access modes
The TMS28F040 is configured as read-only while Vpp = VpPL' Commands to initiate status reads and
program/erase operation are possible with Vpp = VpPH' The memory address space consists of sixteen
32K x 8-bit blocks indexed by address inputs A 15-A18.
read access
While Vpp = VPPL, the TMS28F040 is configured for read-only access; program and erase operations are not
available. When Vpp = VpPH, a read cycle must assert G low with E = VIL' Hardware signature read is always
available.
write access
Write acc~ss is available when Vpp = VPP'i.:.-Commands, data, ~nd addresses are latched by the TMS28F040
using the E input. A write cycle is defined as E switching low with G high and Vpp = VPPH. Command or program
data are latched on the rising edge of E. Addresses are latched on the falling edge of E. Software signature,
status, polling, suspend/resume, and program/erase commands are functional during write access.
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read modes
The TMS28F040 always operates in one of three read modes. The read mode is latched by writing an initiation
command and remains latched regardless of subsequent program and erase operations. Only the read memory
mode is available when VPP=VPPL.
read memory data/poll bits
Upon initial power up, the device defaults to the read memory mode. This mode can also be set at any time by
writing either of the commands FFh or OOh. The mode remains latched until one of the other two read modes
is initiated. The read array commands are functional when VPP=VpPL or VPPH.
The data available while in the read memory mode, when VpP=VPPH, is dependent on the state ofthe write state
machine. If the WSM is not performing a program or erase operation, the standard processor read cycles simply
retrieve the array data. Ifthe WSM is busy, the system processor may read the data poll bit (007) and the toggle
bit (006) to test for operation progress and completion. The behavior of these bits is described in a later section.
read status register
The device contains a status register than can be read to determine the status of the automated program/erase
operations. This register is read by writing the command 70h. Following the write command 70h, all subsequent
read cycles output data from the status register until one of the other two read modes is initiated. The status
register is updated automatically by the write state machine. The purpose and behavior of the bits of the status
register are described in a separate section. The read status register command is functional when VPP=VPPH'
TEXAS
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TMS28F040
4194 304·BIT FLASH ELECTRICALLY ERASABLE
PROGRAMMABLE READ·ONLY MEMORY
SMJS040-DECEMBER 1992
read signature mode
The signature operation outputs the manufacturer code (97h) and device code (79h). This mode can be entered
through either a hardware or software operation.
The read signature mode may be latched through software by writing the command 90h. Upon latching 90h,
asserting AO = VIL outputs the manufacturer code, while setting AO = VIH produces the device code. This mode
remains effective until one of the other two read modes is initiated. The read signature command is functional
when VpP=VPPH and is accessible from any operating mode.
Alternatively, the hardware implementation is achieved by setting E=G=VIL, A9=VID and AO = VIL orVIH' When
AO = VIL, the output represents the manufacturer code. The device code is output when AO = VIH' The
hardware signature access is not latched. Once A9 returns to VIL or VIH, the device returns to the previously
latched read mode.
standby mode
When E = VIH, the device is in standby mode where much of the circuitry is disabled resulting in lower power
consumption. In this mode, the output pins (DOo-D07) are placed in high-impedance state irrespective of G.
An erase/program operation will continue during standby until completed.
output disable
""D
When G = VIH or E = VIH, the device outputs are disabled and the output pins (000-007) are placed in
high-impedance state.
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write/erase modes
C
The TMS28F040 offers fully automated block erase, chip erase, and byte program operating modes. All pulse
generation, preconditioning, and verification is handled by the on-chip write state machine. Upon initial
power-up, the device defaults to reading memory data. Program and erase operations require two command
cycles to initiate. Program and erase operations are accepted when Vpp = VPPH' Attempting to initiate a
program or erase operation while Vpp = VpPL will leave the array contents unaltered. Additionally, if Vpp drops
sufficiently below VPPH during a program or erase operation, the operation will be aborted. If Vee drops below
VLKO, any operation in progress will be aborted, new operations will be locked out, and the device will return
to the read array mode. If any operation is in progress or suspended, write/erase mode commands will be
ignored until the operation in progress completes.
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block erase
Block erase will initialize the contents of a single unprotected block to all 1s. Block erase is initiated by the
command sequence: block erase setup(20h) followed by block erase confirm(OOh). This command sequence
is to ensure that memory contents are not accidentally erased. These commands are associated with a block
address to be erased (A15-A18). Addresses are latched during the confirm command on the falling edge of E.
Command data is latched on the rising edge of E. Block preconditioning, erase, and verify are handled by the
write state machine, invisible to the system. Block erasure takes place when Vpp = VpPH and Vee> VLKO. If
the addressed block has been protected, the operation will abort with the erase status register flag SR.5 = VIH'
chip erase
Chip erase is initiated by the command sequence: chip erase setup(30h) followed by chip erase confirm (30h).
This command sequence is to ensure that memory contents are not accidentally erased. Command data is
latched on the riSing edge of E. Chip erase is handled by the write state machine, invisible to the system. The
chip erasure takes place only when VpP=VpPH and Vee> VLKO' Chip erase will set the memory contents of
all unprotected blocks to 1s in a single erase operation. Individual blocks may be excluded from erasure by
configuring the soft protection registers.
TEXAS ~
INSTRUMENTS
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TMS28F040
4194 304-BIT FLASH ELECTRICALLY ERASABLE
PROGRAMMABLE READ-ONLY MEMORY
SMJS040-0ECEMBER 1992
erase suspend/resume
The erase suspend command (Bah) allows interruption of a block erase operation in order to read data from
an unaltered block of memory. Once the erase sequence is started, the erase suspend command (Bah) requests
the write state machine to suspend the erase operation at predetermined breakpoints in the erase algorithm.
The device operation status must be monitored to determine when the suspend has been executed (see related
monitoring operation status section). After suspend has been granted, the read command should be written with
appropriate address to read data from another block. Vpp is required to remain at VPPH during the suspend
so that the operation may be continued with a resume command. Block erase, chip erase, byte/word program,
and soft protect commands are not accepted when any operation has been suspended. The erase sequence
can be resumed with the erase resume command (DOh). An erase resume command must follow a suspend
command before any other write/erase operation is allowed. ,If Vpp drops sufficiently below VpPH during a
suspended operation, the suspended operation will be aborted and a resume command must be given before
another write/erase operation is accepted.
byte/word program
Byte programming is initiated by the command sequence: program setup (10h) followed by a write confirm
command specifying address and data to be programmed. Addresses are latched during the confirm command
on the falling edge of E. Program data is latched on the rising edge of E. Polling the device will determine when
the program operation is complete. Ones (1 s) cannot be programmed into any bit position and are ignored (e.g.,
programming FFh over an address location does not alter its data and does not return a fail condition).
soft protection
Data in the TMS28F040 is organized into sixteen separate 32K x 8-bit blocks indexed by address A15-A18.
The device features the ability to protect the data stored in individual blocks from erasure and reprogramming.
The protection mechanism is a bank of sixteen flags which can be set or reset through register commands. If
a flag is set, it secures the data in the corresponding block by preventing all program/erase operations pertaining
to that block. Upon power up, all flags are automatically cleared to allow unrestricted modification of the data
array.
Alteration of the protection flags is a two bus-cycle process. On the first bus cycle, the software protect
command, OFh, must be written to the device using the standard write cycle timings. On the next write strobe,
a block address is latched into the address register on its falling edge and a keyword is latched into the data
register on its rising edge. To have effect, the keyword must be one of the four patterns specifying the change
as described in the command table. If data other than one of the four valid patterns is written on the second bus
cycle, no change is made to the flag registers. Protection flags are not altered by Vpp transitions.
The benefit of this feature is that the end user can dynamically configure portions of the array as read-only. An
attempt to alter data located in a protected block has no effect on its data. During an entire chip erase operation,
protected blocks are unchanged and unprotected blocks are erased.
monitoring operation status
The status of the on-chip program and erase operations may be monitored when Vpp= VPPH. The most
complete monitoring method uses the status register. Alternatively, either the data poll bit (007) or the toggle
bit (006) can be analyzed.
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TMS28F040
4 194 304-BIT FLASH ELECTRICALLY ERASABLE
PROGRAMMABLE READ-ONLY MEMORY
SMJS040-0ECEMBER 1992
Table 2. Status Register Bit Definitions
DESCRIPTION
REGISTER BIT
HIGH (1)
LOW (0)
FUNCTION
SR.7 (007)
Ready
Busy
SR.6 (O06)
Suspended
In progress/completed
Erase suspended
SR.S {~OS)
Failure in chip/block erasure
Successful chip/block erasure
Erase status
Write state machine ready
SR.4 (O04)
Failure in byte program
Successful byte program
Program status
SR.3 (O03)
Vpp low detect/operation aborted
Vpp status ok
Vpp low
SRO-SR.2
NOTES:
Reserved
4. Register bits SR.7-SR.O correspond with 007-000 respectively.
5. The SR.7 bit must first be checked to determine program or erase completion before status bits are checked for program/erase
success. The erase status bit (SR.S) and program status bit (SR.4) are set by the write state machine and can only be reset by the
clear status register command (SOh). Program/erase operations are not guaranteed when Vpp drops below VpPH. If a command
sequence error is detected Onvalid confirm command), both the program (SR.4) and erase (SR.S) status bits will be set. Status bits
SR.3-SR.O are reserved and should be masked out when polling the status register.
status register
The status register bit definitions table summarizes this functional description. The status register can be
monitored by issuing the read status register command, 70h, either before or after initiating a program/erase
operation. After the read status register command is given, the status register remains available until the device
is reset to the read array mode by the FFh or OOh commands or read signature mode 90h. Any number of
memory modifications can be performed before returning to the read array mode.
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The contents ofthe status register are updated automatically by the write state machine. After a program/erase
command is issued and confirmed, the ready bit (007) of the status register indicates that the operation is in
progress. No other program/erase commands are effective when the ready bit is low. Polling the ready bit for
VOH determines when the operation is complete. Afterwards, the program status (005). erase status (004)
and Vpp low (003) bits of the status register can be analyzed to validate successful completion. If any of these
are set, they can be cleared by issuing a clear status register command, 50h. To maximize system flexibility,
no requirement is made to verify or clear the status bits before another operation is attempted. The status
register is cleared only by the clear status register command so that any number of memory modifications may
be made between status register checks. Any failure conditions that occur will accumulate in the status register
between clear commands. The clear status register command is available when Vpp =VpPH and while no write
erase operation is in progress or suspended.
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The status register can be used to monitor the state of the device entering and exiting the suspend mode. After
the suspend command (SOh) is given, the suspend bit (006) will be set to VOH. When a breakpoint is reached,
the write state machine sets the ready bit 007 to VOH' Ready bit 007 should be used to monitor when a suspend
request has been granted, and the suspend bit 006 should be used to determine if a resume operation is
necessary. If the write state machine.is not busy, the suspend command is ignored and suspend bit 006 will
not be set. To begin reading the array, one ofthe read array commands, OOh or FFh, must be issued ifthe device
was in the read status register mode. After reading the array, the device can be returned to reading the status
register by again writing 70h. The resume command, DOh, continues the erase operation and resets both the
suspend and ready bits to VOL'
Vpp low status bit 003 indicates a catastrophic Vpp supply failure during a program, erase, or suspend
operation. This bit will be set if Vpp drops significantly below VpPH while the write state machine is busy or
suspended. Any operation that was in progress at that time will be aborted. The Vpp low status bit provides a
valid indication of gross failure of the Vpp supply. Vpp loss for short duration or slightly below minimum operating
levels might still corrupt data without the status register indicating a failure. It is left to the user to provide power
supply integrity.
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INSTRUMENTS
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TMS28F040
4194 304·BIT FLASH ELECTRICALLY ERASABLE
PROGRAMMABLE READ·ONLY MEMORY
SMJS040-DECEMBER 1992
data polling and toggle bits
If the device is set in the read array mode before or during a program/erase operation, the poll bit and toggle
bit will be available. One method to check for operation completion is to use the toggle bit (006). This bit is
available along with the data poll bit (007) when the device is in the read array mode. While the write state
machine is busy, the toggle bit switches logic states with each falling edge of E or G. When the program or
erasure is complete, the output pins automatically return to providing the data stored in the byte specified by
the address pins. Therefore, when 006 stops toggling between two consecutive reads to the same address,
the operation is complete. To confirm successful array modification, the status register may be read by issuing
the read status register command, 70,h.
By addressing an unaltered block, the toggle bit may also be used to determine when a suspend request has
been granted. After the BOh command is given, the toggle bit will continue to switch logic states with each falling
edge of E or G until the current operation is suspended. 006 stops toggling between two consecutive reads
to the same address once the suspend request has been granted.
While the write state machine is busy, the data poll bit (007) reflects the complement of the data stored in the
seventh bit of the target data register. After the operation is complete, the device output pins automatically return
to reading the byte specified by the address pins. Data bit 007 changing from complement to true indicates the
end of an operation. When using this monitor method, the addresses should remain stable throughout the
operation. During a block or chip erasure, the data poll bit (007) is always low and returns high at successful
completion. Should the device fail to erase or program, the data poll bit (007) might not return to its
uncomplemented state. Data polling is available after the second bus-cycle write sequence initiating a
program/erase operation. The success of the modification can be verified when the byte data becomes
available. The status register is always readable by issuing the read status register command, 70h.
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INSTRUMENTS
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6-193
TMS28F040
4194 304-BIT FLASH ELECTRICALLY ERASABLE
PROGRAMMABLE READ-ONLY MEMORY
SMJS040-0ECEMBER 1992
Table 3. Command Definitions
COMMAND
SECOND BUS CYCLE
OPERATION
ADDRESS
DATA
1
Write
OOh
FFh
OPERATION
ADDRESSt
DATAf
Read Array
1
Write
Signature
3
Write
X
X
X
90h
Read
IA
Read Status Register
2
Write
X
70h
Read
X
SRD
Clear Status Register
1
Write
X
SOh
Automated Block Erase
2
Write
Write
BA
DOh
Erase Suspend
1
Write
BOh
Read Array
Erase Resume
1
Write
X
X
X
Automated Byte Program
2
Write
X
10h
Write
PA
PO
Automated Chip Erase
2
Write
30h
Write
X
30h
Soft Protect
2
Write
X
X
OFh
Write
BA
PC
NOTES:
"'C
FIRST BUS CYCLE
BUS
CYCLES
-I
DOh
6. The command data is written through DOD-D07.
7. Following the signature command, two read operations access the manufacturer code (97h) and device code (79h).
t Description of terms:
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20h
IA
BA
PA
SRD
PO
PC
= signature address: OOOOOh for mfr code; 00001 h for device code.
= any address within the block to be selected; latched on falling edge of E.
= address of memory location to be programmed; latched on falling edge of E.
= data read from status register.
= data to be written at location PA. Data is latched on rising edge of E.
= Protect Command.
: OOh = Clear all protection (enable chip W/E)
: FFh = Set all protection (disable chip W/E) ,
: FOh = Clear addressed block protection (enable block W/E)
: OFh Set addressed block protection (disable block W/E)
=
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POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
TMS28F040
4194 304·BIT FLASH ELECTRICALLY ERASABLE
PROGRAMMABLE READ·ONLY MEMORY
SMJS040-DECEMBER 1992
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Figure 1. Automated Chip Erase Algorithm
a:
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Figure 2. Automated Block Erase Algorithm
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6-195
TMS28F040
4194 304·BIT FLASH ELECTRICALLY ERASABLE
PROGRAMMABLE READ·ONLY MEMORY
SMJS04Q-OECEMBER 1992
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Figure 3. Automated Byte Program Algorithm
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INSTRUMENTS
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TMS28F040
4194 304·BIT FLASH ELECTRICALLY ERASABLE
PROGRAMMABLE READ·ONLY MEMORY
SMJS04Q-OECEMBER 1992
absolute maximum ratings over operating free-air termperature range (unless otherwise noted)t
Supply voltage, Vee (see Note 8) .. :................................................ - 0.6 V to 7 V
Supply voltage, Vpp .............................................................. - 0.2 V to 15 V
Input voltage range: All except A9 (see Note 9) ......................................... - 0.6 to 7 V
A9 (see Note 9) ................................................... -0.6 to 15 V
Output voltage ...................................................................... - 0.6 to 7 V
Operating free-air temperature range during read/erase/program
(NL, DDL, DUL) .................................................. O°C to 70°C
Operating free-air temperature range during read/erase/program
(NO, DDO, DUO) ............................................. - 40°C to 125°C
Storage temperature range ....................................................... - 65°C to 150°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 8. All voltage values are with respect to the most negative supply voltage VSS.
9. The voltage on any input pin may undershoot to -2.0 V for periods less than 20 ns.
recommended operating conditions
VCC
Vpp
VIH
MIN
NOM
MAX
Operating Range
4.5
5
5.5
VLKO
Erase/Write Lock-Out
2.5
VpPL
Read Mode
VpPH
Program/Erase Mode
Supply voltage
Supply voltage
High-level input voltage
VIL
Low-level input voltage
VID
A9 signature voltage
TA
Operating free-air temperature
TIL
UNIT
V
V
-2.0:1:
0
11.4
12
VCC+2
V
12.6
V
2
VCC+0.5
V
CMOS
VCC-0.2
VCC+0.5
V
TIL
-0.5
0.8
V
CMOS
-0.5
0.2
V
11.4
13
V
0
70
-40
125
NL, DDL, DUL, suffix
NO, DDO, DUO suffix
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:I: Duration of VPP undershoot must be < 20 ns.
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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
6-197
TMS28F040
4194 304·BIT FLASH ELECTRICALLY ERASABLE
PROGRAMMABLE READ·ONLY MEMORY
SMJS04~DECEMBER
1992
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
VOH
VOL
Low-level output voltage
II
Input current (leakage)
o
MIN
MAX
UNIT
10H = -20!lA
TIL-output level
10H = - 400 !lA
TIL-output level
IOL=2.1 mA
0.45
10L = 20!lA
0.1
V
±1
!lA
CMOS-output level
V
VCC-0.2
2.4
V
VI =OtoVCC
V
10
Output current (leakage)
E = VIH, Vo = OtoVCC
±10
itA
110
A9 signature mode current
A9=VIDMAX
200
!lA
1
mA
ICCl
VCC supply current (Standby)
100
itA
TIL-input level
E=VIH
VCC = 5.5V
CMOS-input level
E =VCC + 0.2 V,
VCC = 5.5 V
ICC2
VCC supply current
(Read mode)
E = VIL, VCC = 5.5 V
f = 6 MHz, lOUT = 0 mA
40
mA
ICC3
VCC supply current
(Program mode)
VCC = 5.5 V, G = VIH
Programming in progress
30
mA
ICC4
VCC supply current
(Erase mode)
VCC = 5.5 V, G = VIH
Chip Erase in progress
30
mA
40
mA
"C
:D
High-level output voltage
TEST CONDITIONS
CMOS-output level
C
ICC5
VCC supply current
(Erase Suspend)
o
VCC = 5.5 V, lOUT = 0 mA
Erase suspended,
Block read at f = 6 MHz
IpPl
VPP supply current
(Standby)
GND "VPP " VCC
E=VIH
±10
!lA
IpP2
VPP supply current
(Read mode)
VPP = VpPH MAX
200
itA
IpP3
VPP supply current
(Program mode)
VPP = VpPH MAX,
Programming in progress
30
mA
IPP4
VPP supply current
(Erase mode)
VPP = VpPH MAX,
Chip erase in progress
50
mA
IpP5
VPP supply current
(Erase suspend)
VPP = VpPH MAX,
Erase suspended,
Block read at f = 6 MHz
200
!lA
C
.....
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:D
m
:S
m
~
capacitance over recommended ranges of supply voltage and operating free-air temperature,
f = 1 MHz
TVP
MAX
CI
Input capacitance
VI = 0, f = 1 MHz
4
6
pF
Co
Output capacitance
Vo = 0, f =1 MHz
6
12
pF
CVPP
VPP input capacitance
VPP = 0, f =1 MHz
6
12
pF
PARAMETER
TEST CONDITIONS
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POST OFFICE BOX 1443· HOUSTON. TEXAS 77001
MIN
UNIT
TMS28F040
4194 304·BIT FLASH ELECTRICALLY ERASABLE
PROGRAMMABLE READ·ONLY MEMORY
SMJS040--DECEMBER 1992
switching characteristics over recommended operating free-air temperature range: read-only
operation
DESCRIPTION
ALT.
SYMBOL
tAVAV
Read cycle time
tRC
tAVQV
Access time from address
tACC
Output hold from Address, E,
or G change
tOH
'28F040-10
'28F040-12
'28F040-15
'28F040-17
MIN
MIN
MIN
MIN
MAX
MAX
120
100
100
150
120
0
MAX
0
MAX
ns
170
150
0
UNIT
170
ns
ns
0
170
ns
tELQV
E to output valid
tCE
tELQX
E to output low Z
tLl
tEHQZ
E to output high Z
tHZ
30
30
35
40
ns
tGLQV
G to output valid
tOE
50
55
60
65
ns
tGLQX
G to output low Z
tOL
tGHQZ
G to output high Z
tDF
\yCS
VCC setup time to valid read
\yCS
20
20
20
20
f's
tGLWL
G read setup time to E hight
tGLWL
20
20
20
20
ns
tGLWH
G read pulse durationt
tGLWH
40
45
50
55
ns
t Required when Vpp
100
120
0
0
0
30
150
0
0
0
30
ns
0
ns
0
40
35
ns
=VpPH.
switching characteristics over recommended operating free-air temperature range: write, erase,
program operations
PARAMETER
ALT.
SYMBOL
'28F040-10
MIN
MAX
'28F040-12
'28F040-15
'28F040-17
MIN
MIN
MIN
MAX
MAX
MAX
W
:>
W
a:
UNIT
a..
I-
tAVAV
Write cycle time
twc
100
120
150
170
ns
tAVWH
Address setup time
tAS
0
0
0
0
ns
twHAX
Address hold time
tAH
45
50
55
60
ns
tGHWL
G write setup time
tGHWL
0
0
0
0
ns
tGHWH
G write hold time
tGHWH
5
5
5
5
ns
\YPWL
VPP setup to E write strobe:!:
\YPS
60
60
60
60
ns
twLWH
E write strobe pulse duration
twp
40
45
50
55
ns
twHWL
E write strobe pulse duration
high
tWPH
20
20
20
20
ns
tDVWH
Data setup to E high
tDS
20
20
20
20
ns
twHDX
Data hold time
tD
10
10
10
10
ns
\YPPR
VPP rise time (90% VpPH)
\YPPR
500
500
500
500
ns
\YPPH
VPP hold time
\YPPH
0
0
0
0
twHWHl
Duration of program operation
tWHWHl
8.6
529
8.6
529
8.6
529
8.6
529
f's
twHWH2
Duration of block erase operation
twHWH2
0.1
62.5
0.1
62.5
0.1
62.5
0.1
62.5
s
twHWH3
Duration of chip erase operation
tWHWH3
2.6
184
2.6
184
2.6
184
2.6
184
s
ns
:!: E must equal VIH during VPP transitions.
TEXAS .."
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
3:
6-199
o
:::>
c
oa:
a..
TMS28F040
4194 304·BIT FLASH ELECTRICALLY ERASABLE
PROGRAMMABLE READ·ONLY MEMORY
SMJS040--DECEMBER 1992
automated erase and programming performance t
PARAMETER
MIN
TYP
MAX
Byte programming time
8.60
45
529
UNIT
Block erase time
0.10
2
62.5
s
Block programming time
0.28
1.5
17.3
s
s
,",S
Chip erase time
2.60
12.2
184
Chip programming time
2.26
23.6
277
s
0
3
10.1
ms
Suspend latency time
t All times include on-chip preconditioning, pulse generation, and verification.
PARAMETER MEASUREMENT INFORMATION
AC input/output reference waveform
2.4V
"'C
O.4V
:c
o
c
c:
o
--------~~~~~~:~~~~--------------------~~~--------
A.C. testing inputs are driven at 2.4 V for logic high and 0.4 for logic low. liming measurements are made at
2 V for logic high and 0.8 V logic low on both inputs and outputs. Each device should have a 0.1 !-IF ceramic
capacitor between Vee and VSS as close as possible to the device pins.
-t
-l
2.08 V
"'C
:c
m
m
S
Output
Under
Test
~
T
Figure 4. Output Load Circuit
TEXAS ~
INSTRUMENTS
6-200
POST OFFICE BOX 1443· HOUSTON, TEXAS 77001
TMS28F040
4194 304·BIT FLASH ELECTRICALLY ERASABLE
PROGRAMMABLE READ·ONLY MEMORY
SMJS04CH>ECEMBER 1992
PARAMETER MEASUREMENT INFORMATION
~
1
Addresses
~
~
1
~_ _ _ _ _ _ _ _ _'t_al_ld_A_dd_r_es_s_ _ _ _ _ _ _~~/I:"~~~~~
~
tACC
i.-
---------+l~
"'------------;.----+
~
..'<4----- tCE ----~~
1
14~----
tLZ
---~~
I
~
T~tOH~
~
!
\
toH
tHZ
1
----.tJ
1
1
~,...I-------iL--f:__.!r
-4 :
tOH
1 ~ 1 14
~
t i l
14-1'--- OL -----.,.1
1 1
14-'<4---
tOE
tDF
14~---- tGLWH --II--+I~~
DQO-DQ7
1 ~
11 11
1
--------------------~<~<{~____~_alld_D_ata
____
1+14---- tvcs
1
1
1
1
:1
l4io11---- tGLWL ---J-I-7"-1
I
1
1
1
3:
w
~i~>>--
:>
w
----~~
a:
VCC
~
tO
:::J
C
Figure 5. AC Waveform for Read Operations
Addresses
~___'t_a_lId_A_d_dr_e_ss_ _ _
14- tAS ----+I
1 141
7~tGHWLJ
tvps
14
1
1
1
1
1
DQO-DQ7
Vpp
1
1
1
tAH
o
a:
1
---'1
~
1
loll-- tGHWH
1
1
1
f\
1 j,..
1
1
1
1
1
1
14
t~ ~
twP
14
I
I
tDS
<({
~
1
14--
7\
twPH~
to ~
Valid Input Data
twc
-.!\
:}2)
1
1
1
1
1
·1
I
NOTE: Addresses are latched on the falling edge of E.
Command and Program data are latched on the rising edge E.
Figure 6. AC Waveform for Write Operations
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
6·201
TMS28F040
4194 304·BIT FLASH ELECTRICALLY ERASABLE
PROGRAMMABLE READ·ONLY MEMORY
SMJS040--DECEMBER 1992
PROGRAM/ERASE INFORMATION
Addresses~.:~:~~
"-
twHWH2
~
E~~~~~
---.114tvps
I
DQ~Q15
~
II
I
Read Array
Write
Cmd4
~
I
I
I
:r)~
G-+! I
"'C
1
C
vppj!
o
c:
I
I
I
lJ
~atab
I"'~
~tvPPR
I
tvPPH
)trj--------~){rj------------~)'~~--------~~r____
o
-I
Command
Cmd1
Cmd2
Cmd3
Read
Cmd4
Read
"'C
Program
10h
data
70h
status
OOh
array
Chip Erase
30h
30h
70h
status
OOh
array
Block Erase
70h
20h
DOh
NOTE: Addresses are latched on the failing edge of E.
Command and Program data are latched on the rising edge E.
status
OOh
array
lJ
m
S
m
::e
Figure 7. AC Waveform for Program/Erase Operations
TEXAS . "
INSTRUMENTS
6-202
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
TMS27LV010A 1 048 576-BIT UV ERASABLE LOW VOLTAGE PROGRAMMABLE ROM
TMS27LV010A 1 048 576-BIT LOW VOLTAGE ONE-TIME PROGRAMMABLE ROM
SMLS113-DECEMBER 1992
• Organization ... 128K x 8
• Single 3.3-V Power Supply
• Operationally Compatible With Existing
1-Megabit EPROMs
J AND N PACKAGEst
(TOP VIEW)
• Industry Standard 32-Pin Dual-In-line
Package (DIP), 32-Lead Plastic Leaded Chip
Carrier (PLCC), and 32-Lead Thin Small
Outline Package (TSOP)
• All Inputs/Outputs Fully TTL Compatible
• Max Access/Min Cycle Time
Vpp
VCC
A16
A15
A12
A?
A6
A5
Vee ± 10%
'27LV010A-20
'27LV010A-25
'27LV010A-30
200
250
300
A4
PGM
NC
A14
A13
A8
A9
All
A3
G
A2
Al0
E
DO?
D06
D05
D04
D03
Al
AO
DOO
DOl
D02
GND
ns
ns
ns
• 8-Bit Output For Use in
Microprocessor-Based Systems
• Very High-Speed Low Voltage SNAP! Pulse
Programming
• Power-Saving CMOS Technology
z
o
~
FM PACKAGEt
(TOP VIEW)
• 3-State Output Buffers
• 400-mV Minimum DC Noise Immunity With
Standard TTL Loads
C\JLO
::i:::i:
• Latchup Immunity of 250 mA on All Input
and Output Pins
• No Pullup Resistors Required
• Low Power Dissipation (Vee = 3.6 V)
- Active ... 54 mW Worst Case
- Standby .•. 0.09 mW Worst Case
(CMOS-Input Levels)
5
A4
A3
A2
Al
AO
DOO
• PEP4 Version Available With 168 Hour
Burn-In and Choices of Operating
Temperature Ranges
4
A?
A6
A5
:!E
() ()
a:
~ ~ I~
<>$>c..z
321
0
ou.
3231 30
29
6
28
7
27
8
26
9
10
25
24
11
23
12
22
21
13
1415 16 171819 20
z
w
o
z
~
c
DO?
C
~
A4
Z
1
0
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
G
A10
E
DO?
D06
D05
D04
D03
Vss
D02
D01
DOO
AO
A1
A2
A3
0
m
-Z
TMS27LV010A OTP PROM
DU PACKAGEt
REVERSE PINOUT
"0
:n
(TOP VIEW)
s:
G
A10
Z
DO?
D06
D05
D04
D03
-0~
E
Vss
D02
D01
DOO
AO
A1
A2
A3
1
32
31
\l
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
NC
PGM
Vee
Vpp
21
t The packages shown are for pinout reference only.
TEXAS ~
6-204
A11
A9
AS
A13
A14
INSTRUMENTS
POST OFFICE BOX 1443· HOUSTON. TEXAS 77001
A16
A15
A12
A?
A6
A5
A4
TMS27LV010A 1 048 576·BIT UV ERASABLE LOW VOLTAGE PROGRAMMABLE ROM
TMS27LV010A 1 048 576·BIT LOW VOLTAGE ONE·TIME PROGRAMMABLE ROM
SMLS11a-OECEMBER 1992
These devices are fabricated using power-saving CMOS technology for high speed and simple interface with
MOS and bipolar circuits. All inputs (including program data inputs) can be driven by Series 74 TTL circuits
without the the use of external pullup resistors. Each output can drive one Series 74 TTL circuit without external
resistors.
The TMS27LV010A EPROM is offered in a dual-in-line ceramic package (J suffix) designed for insertion in
mounting hole rows on 15,2-mm (600-mil) centers. The TMS27LV01 OA EPROM CDIP is also offered with two
choices of temperature ranges, O°C to 70°C and -40°C to 85°C (JL and JE suffixes). The TMS27LV010A
EPROM CDIP is also offered with 168 hour burn-in on both temperature ranges (JL4 and JE4 suffixes). (See
table below.)
The TMS27LV01 OA OTP PROM is offered in a plastic dual-in-line package (N suffix), a 32-lead plastic leaded
chip carrier package using 1,25-mm (50-mil) lead spacing (FM suffix), and a 32-lead thin small-outline package
(DO and DU suffixes). TMS27LV010A OTP PROM is offered with two choices of temperature ranges of
O°C to 70°C (NL, FML, DOL, and DUL suffixes) and - 40°C to 85°C (NE, FME, DOE, and DUE suffixes).
(See table below.)
TMS27LV010A
SUFFIX FOR OPERATING
TEMPERATURE RANGES
WITHOUT PEP4 BURN-IN
O"Cto 70"C
EPROM
OTP PROM
- 40"C to 85"C
SUFFIX FOR PEP4
168 HOUR BURN-IN
VS TEMPERATURE RANGES
O"C to 70"C
z
o
~
- 40"C to 85"C
JL
JE
JL4
JE4
FML
FME
FML4
FME4
NL
NE
NL4
NE4
DDL
DDE
DDL4
DDE4
DUL
DUE
DUL4
DUE4
:!:
a:
These EPROMs and OTP PROMs operate from a single 3.3-V supply (in the read mode), thus are ideal for use
in portable systems. One other 12.75-V supply is needed for programming. All programming signals are TTL
level. These devices are programmable using the Low Voltage SNAP! Pulse programming algorithm. The Low
Voltage SNAP! Pulse programming algorithm uses a Vpp of 12.75 V and a Vee of 5 Vfor a nominal programming
time of thirteen seconds. For programming outside the system, existing EPROM programmers can be used.
Locations may be programmed singly, in blocks, or at random.
o
LL
Z
W
o
Z
~
c
«
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
6-205
TMS27LV010A 1 048 576-BIT UV ERASABLE LOW VOLTAGE PROGRAMMABLE ROM
TMS27LV010A 1 048 576-BIT LOW VOLTAGE ONE-TIME PROGRAMMABLE ROM
SMLSll3-DECEMBER 1992
operation
The seven modes of operation are listed in the following table. The read mode requires a single 3.3-V supply.
All inputs are TIL level except for Vpp during programming (12.75 V for Low Voltage SNAP! Pulse). and 12 V
on A9 for signature mode.
MODE
FUNCTION
»
c
READ
OUTPUT
DISABLE
STANDBY
PROGRAMMING
VERIFY
PROGRAM
INHIBIT
SIGNATURE MODE
E
VIL
VIL
VIH
VIL
VIL
VIH
VIL
G
VIL
VIH
xt
VIH
VIL
VIL
PGM
X
X
X
,VIH
Vpp
Vee
Vee
Vee
VIL
Vpp
X
X
Vpp
Vpp
Vee
. Vee
Vee
Vee
Vee
Vee
Vee
Vee
A9
x
X
x
x
x
AO
X
X
X
X
X
X
X
X
Vee
VH*
I
VH*
VIL
I
VIH
CODE
DOD-D07
Data Out
HI-Z
HI-Z
Data In
Data Out
HI-Z
MFG
97
~
t
z
X can be VIL or VIH.
*VH = 12V±0.SV.
o
m
z
-'TI
o
:c
s:
~
o
z
TEXAS ~
INSTRUMENTS
6-206
POST OFFICE BOX 1443· HOUSTON. TEXAS 77001
I DEVICE
I
D7
TMS27LV010A 1 048 576·BIT UV ERASABLE LOW VOLTAGE PROGRAMMABLE ROM
TMS27LV010A 1 048 576·BIT LOW VOLTAGE ONE·TIME PROGRAMMABLE ROM
SMLS113-DECEMBER 1992
read/output disable
When the outputs of two or more TMS27LV01 OA EPROMs or TMS27LV01 OA OTP PROMs are connected in
parallel on the same bus, the output of any particular device in the circuit can be read with no interference from
competing outputs of the other devices. To read the output of a single device, a low-level signal is applied to
the E and IT pins. All other devices in the circuit should have their outputs disabled by applying a high level signal
to one of these pins.
latchup immunity
Latchup immunity on the TMS27LV01 OA EPROM and OTP PROM is a minimum of 250 mA on all inputs and
outputs. This feature provides latchup immunity beyond any potential transients at the P.C. board level when
the devices are interfaced to industry standard TTL or MOS logic devices. The input/output layout approach
controls latchup without compromising performance or packing density.
power down
Active Icc supply current can be reduced from 15 mA to 250 flA by applying a high TTL input on E and to
25 f-1A by applying a high CMOS input on E. In this mode all outputs are in the high-impedance state.
z
erasure (TMS27LV010A EPROM)
Before programming, the TMS27LV01 OA EPROM is erased by exposing the chip through the transparent lid
to a high intensity ultraviolet light (wavelength 2537 A). The recommended minimum exposure dose (UV
intensity x exposure time) is 15-W·s/cm2. A typical 12-mW/cm2, filterless UV lamp will erase the device in 21
minutes. The lamp should be located about 2.5 cm above the chip during erasure. After erasure, all bits are in
the high state. It should be noted that normal ambient light contains the correct wavelength for erasure.
Therefore, when using the TMS27LV01 OA EPROM, the window should be covered with an opaque label. After
erasure (all bits in logic high state), logic lows are programmed into the desired locations. A programmed low
can be erased only by ultraviolet light.
initializing (TMS27LV010A OTP PROM)
The one-time programmable TMS27LV01 OA OTP PROM is provided with all bits in the logic high state, then
logic lows are programmed into the desired locations. Logic lows programmed into an OTP PROM cannot be
erased.
Low Voltage SNAPI Pulse programming
The TMS27LV010A EPROM is programmed using the TI Low Voltage SNAP! Pulse programming algorithm
illustrated by the flowchart in Figure 1, which programs in a nominal time of thirteen seconds. Actual
programming time will vary as a function of the programmer used.
The Low Voltage SNAP! Pulse programming algorithm uses an initial pulse of 100 microseconds (f-1s) followed
by a byte verification to determine when the addressed byte has been successfully programmed. Up to 10 (ten)
100-f-1s pulses per byte are provided before a failure is recognized.
The programming mode is achieved when Vpp = 12.75 V, Vee = 5 V, E = VIL, IT = VIH' Data is presented
in parallel (eight bits) on pins 000 through 007. Once addresses and data are stable, PGM is pulsed low.
More than one device can be programmed when the devices are connected in parallel. Locations can be
programmed in any order. When the Low Voltage SNAP! Pulse programming routine is complete, all bits are
verified with Vce = Vpp = 3.3 V:!: 10%.
program Inhibit
Programming may be inhibited by maintaining a high level input on the
E or PGM
pins.
program verify
Programmed bits may be verified with Vpp
= 12.75 V when G =VIL, E = VIL, and PGM =VIH.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
6·207
o-
~
:!
a:
oLL
Z
W
o
Z
~
c
«
TMS27LV010A 1 048 576·BIT UV ERASABLE LOW VOLTAGE PROGRAMMABLE ROM
TMS27LV010A 1 048 576·BIT LOW VOLTAGE ONE·TIME PROGRAMMABLE ROM
SMLSll3-DECEMBER 1992
l
Program
Mode
Increment Address
»
c
~
z
o
m
-z
Increment
Address
Interactive
Mode
"T1
o
:II
s:
-~
o
z
No
Yes
Device Failed
Fall
Final
Verification
J
Figure 1. Low Voltage SNAPI Pulse Programming Flowchart
TEXAS
~
INSTRUMENTS
6-208
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
TMS27LV010A 1 048 576-BIT UV ERASABLE LOW VOLTAGE PROGRAMMABLE ROM
TMS27LV010A 1 048 576-BIT LOW VOLTAGE ONE-TIME PROGRAMMABLE ROM
SMLSll3-DECEMBER 1992
signature mode
The signature mode provides access to a binary code identifying the manufacturer and type. This mode is
activated when A9 (pin 26) is forced to 12 V. Two identifier bytes are accessed by toggling AD. All addresses
must be held low. The signature code for these devices is 97D7. AD low selects the manufacturer's code 97
(Hex), and AD high selects the device code D7 (Hex), as shown by the signature mode table below.
signature modet
PINS
IDENTIFIER!
AO
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQO
MANUFACTURER CODE
VIL
1
0
0
1
0
1
1
1
HEX
97
DEVICE CODE
VIH
1
1
0
1
0
1
1
1
D7
t E = G = VIL. Al-A8 = VIL, A9 = VH. A10-A16 = VIL, vPP = vcc.
logio symbol;
EPROM 131072 x 8
AO
Al
A2
A3
A4
A5
A6
A7
A8
A9
Al0
All
A12
A13
A14
A15
A16
E
12
11
10
9
8
7
6
5
27
26
23
25
4
28
29
3
2
0
;>
0
A 131 071
AV
AV
AV
AV
AV
AV
AV
AV
13
14
15
17
18
19
20
21
~
OQO
OQ1
OQ2
DQ3
OQ4
OQ5
OQ6
OQ7
:!:
a:
0
U.
Z
W
0
Z
16
22
~
24
z
0
I'-
~
c
[PWRDOWNI
&
I
«
EN
; This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. J package illustrated.
TEXAS
~
INsrRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
6-209
TMS27LV010A 1 048 576-BIT UV ERASABLE LOW VOLTAGE PROGRAMMABLE ROM
TMS27LV010A 1 048 576-BIT LOW VOLTAGE ONE·TIME PROGRAMMABLE ROM
SMLSII3-DECEMBER 1992
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage range, Vee (see Note 1) ............................................. - 0.6 V to 7 V
Supply voltage range, Vpp .......................................................... - 0.6 to 14 V
Input voltage range, All inputs except A9 ......................................... - 0.6 to vee + 1 V
A9 ............................................................ - 0.6 to 13.5 V
Output voltage range, with respect to VSS (see Note 1) .......................... - 0.6 V to vee + 1 V
Operating free-air temperature range (JL, NL, FML, DOL, and DUL) ....................... ooe to 70°C
Operating free-air temperature range (JE, NE, FME, DOE, and DUE) ................... - 40°C to 85°C
Storage temperature range ....................................................... - 65°C to 150°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to GND.
recommended operating conditions
TMS27LV010A-20
TMS27LV010A-25
TMS27LV010A-30
»
c
~
z
(')
m
z-
."
o
lJ
Vee Supply voltage
Vpp Supply voltage
Read mode (see Note 2)
Low Voltage SNAPI programming algorithm
Read mode (see Note 3)
Low Voltage SNAPI Pulse programming algorithm
VIH High-level dc input voltage
VIL
Low-level dc input voltage
NOTES:
s::
TTL
eMOS
MIN
TYP
MAX
3
3.3
3.6
V
4.5
5
5.5
V
Vee-0.6
Vee
12.5
12.75
Vee+ 0.6
13
2.0
Vee+ 0.5
Vee- 0.2
Vee+ 0.5
TTL
-0.5
eMOS
-0.5
0.8
GND+0.2
V
V
V
V
2. Vee must be applied before or at the same time as VPP and removed after or at the same time as Vpp. The device must not be
inserted into or removed from the board when Vpp or Vee is applied.
3. During programming, Vpp must be maintained at 12.75 V ± 0.25 V.
-o~
z
TEXAS ~
INSTRUMENTS
6-210
UNIT
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
TMS27LV010A 1 048 576·BIT UV ERASABLE LOW VOLTAGE PROGRAMMABLE ROM
TMS27LV010A 1048 576·BIT LOW VOLTAGE ONE·TIME PROGRAMMABLE ROM
SMLS113-DECEMBER 1992
electrical characteristics over full range of operating conditions
PARAMETER
VOH
High-level output voltage
VOL
Low-level output voltage
TEST CONDITIONS
MIN
10H = -100~
MAX
VCC-0.2
V
2.4
10H = -2mA
UNIT
IOL=2 mA
0.4
10L = 100,..A
0.2
V
II
Input current (leakage)
VI = Ot03.6V
:t1
,..A
10
Output current (leakage)
VO=OtoVCC
:t1
,..A
IpP1
Vpp supply current
Vpp = VCC = 3.6V
10
,..A
IpP2
Vpp supply current (during program pulse)
Vpp= 12.75V
30
mA
ICC1
VCC supply current (standby)
ICC2
VCC supply current (active) (output open)
I TIL-input level
E = VIH, VCC = 3.6 V
ICMOS-input level
E =VCC :t 0.2 V, VCC = 3.6 V
25
E = VIL, VCC = 3.6 V,
G = VIH, F = 5 MHz
15
250
itA
mA
capacitance over recommended ranges of supply voltage and operating free-air temperature,
f 1 MHzt
=
TYp:j:
MAX
Ci
Input capacitance
VI = 0, f = 1 MHz
4
8
pF
Co
Output capacitance
Vo = 0, f = 1 MHz
6
10
pF
PARAMETER
TEST CONDITIONS
MIN
UNIT
t Capacitance measurements are made on sample basiS only.
:j: All typical values are at TA = 25°C and nominal voltages.
switching characteristics overfull ranges of recommended operating conditions (see Notes4 and 5)
PARAMETER
talA)
Access time from address
talE)
Access time from chip enable
len (G)
Output enable time from G
Idis
E, whichever occurs first§
tv(A)
Output data valid time after
change of address, E, or G,
whichever occurs first
Output disable time from G or
TEST CONDITIONS
(SEE NOTES 4 & 5)
'27LV010A-20
MIN
CL = 100 pF,
1 Series 74
TIL load,
Input tr " 20 ns,
Input tf " 20 ns
0
0
MAX
'27LV010A-25
MIN
MAX
'27LV010A-30
MIN
MAX
UNIT
200
250
300
ns
200
250
300
ns
75
100
100
ns
35
ns
35
0
0
35
0
0
ns
§ Value calculated from 0.5-V delta to measured output level.
NOTES: 4. For all switching characteristics the input pulse levels are 0.4 V to 2.4 V. Timing measurements are made at 2 V for logic high and
0.8 V for logic low (reference AC testing waveform).
5. Common test conditions apply for tdis except during programming.
TEXAS
~
INSIRUMENTS
POST OFFICE BOX 1443· HOUSTON. TEXAS 77001
6-211
z
o
~
:E
a:
o
LL
Z
W
o
Z
~
c
«
TMS27LV010A 1048 576·BIT UV ERASABLE LOW VOLTAGE PROGRAMMABLE ROM
TMS27LV010A 1 048 576·BIT LOW VOLTAGE ONE·TIME PROGRAMMABLE ROM
SMLSII3-DECEMBER 1992
switching characteristics for programming: Vee = 5 V and Vpp = 12.75 V (Low Voltage SNAP!
Pulse), TA = 25°C (see Note 4)
PARAMETER
lcJis(G)
Output disable time from G
len (G)
Output enable time from G
MIN
NOM
0
MAX
UNIT
130
ns
150
ns
recommended timing requirements for programming: Vee = 5 Vand Vpp = 12.75 V (Low Voltage
SNAP! Pulse), TA = 25°C, (see Note 4)
»
c
<
»
Z
I Low Voltage SNAPI Pulse programming algorithm
MIN
TYP
MAX
95
100
105
tw(PGM)
Program pulse duration
tsu(A)
Address setup time
2
tsu(E)
E setup time
2
tsu(G)
G setup time
2
tsu(D)
Data setup time
UNIT
1'5
1'5
1'5
1'5
1'5
tsuCVPP)
Vpp setup time
2
2
tsuNCC)
VCC setup time
2
1'5
theA)
Address hold time
0
I!S
I!S
Data hold time
2
I!S
th(D)
. .
NOTE 4: For all sWitching characteristics the Input pulse levels are 0.4 V to 2.4 V. Timing measurements are made at 2 V for logic high and
0.8 V for logic low (reference AC testing waveform).
..
o
m
-z
"T1
o
:c
s:
~
o
z
TEXAS ~
INSTRUMENTS
6-212
POST OFFICE BOX 1443.° HOUSTON, TEXAS 77001
TMS27LV010A 1 048 576·BIT UV ERASABLE LOW VOLTAGE PROGRAMMABLE ROM
TMS27LV010A 1 048 576·BIT LOW VOLTAGE ONE·TIME PROGRAMMABLE ROM
SMLS113-DECEMBER 1992
PARAMETER MEASUREMENT INFORMATION
--1
2.08 V
Output
Under Test
T
RL=BOOQ
CL= 100pF
Figure 2. AC Test Output Load Circuit
AC testing Input/output wave forms
v
2.4 v ' - - -.....
O.!~X. . ___
'___..1/\ ~.~ V
0.4 V-
AC testing inputs are driven at 2.4 V for logic high and 0.4 V for logic low. Timing measurements are made at
2 V for logic high and 0.8 V for logic low for both inputs and outputs.
AO-A16
x
Address Valid
I
14
\
E
1
1
I
I
I+----- talE)
1
1
1
i.-ten(G)
OQO-OQ7
HI-Z
~
«««<1
}f
VIH
VIL
I 1
I 1
I 1
1
-----+J
\
G
11
VIH
VIL
I
1
~
talA)
X
VIH
tY(A)
1 I4--tdls~
14
~
I
Output Valid
j»»»}-
HI-Z -
ou.
Z
W
o
Z
:::
«
~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
~
a:
VIL
Figure 3. Read Cycle Timing
TEXAS
Z
o
~
6-213
~
c
TMS27LV010A 1 048 576·BIT UV ERASABLE LOW VOLTAGE PROGRAMMABLE ROM
TMS27LV010A 1 048 576·BIT LOW VOLTAGE ONE·TIME PROGRAMMABLE ROM
SMLS113-DECEMBER 1992
PROGRAMMING INFORMATION
14I0Il-- Verify ------+I
I
141011--- Program --~~
AO-A1B
=X
Address stable
I
~ tsu(A)
DQO-DQ7
---<~ ~"
:
14-
sm.,
~>----+---(C D~,~~
VCC
~
z
o
m
i
:
Vcc
:
I4---+t- tsu(VCC)
I
-+I
I
....
~
o
"
:c
Vcc*
I
I
VCC
I
:
II
th(D)
'L./:141011--I~*-1
:011
I
:
i
tw(PGM)
{>-------VPP
tsu(E) --1'jOIIlt---Pl~1
-z
-+t
I
~i
I
I
E~I
__
I
I
~tsu(VPP)
I
»
c
s:
~
---I:
X,-_A_~_d+_r~_ss
~ tdls(G) t
I4----+t- tsu(D)
VPP
,
th(Al
~I
i
-II tsu(G) I
lol
~
:
1------:
~I ten (G) tl
t lcIis(G) and len (G) are characteristics of the device but must be accommodated by the programmer.
*12.75-VVpp and 5-VVCC for SNAP! Pulse programming.
o
z
Figure 4. Program Cycle Timing (Low Voltage SNAPI Pulse Programming)
TEXAS ~
INSTRUMENTS
6-214
POST OFFICE BOX 1443' HOUSTON, TEXAS 77001
Video RAMs/Field Memories
7-1
Contents
CHAPTER 7.
VIDEO RAMS/FIELD MEMORIES
TMS55160
4 194 304-bit
(256K x 16) Multipart Video RAM ................................. 7-3
TMS55165
4 194 304-bit
(256K x 16) Multipart Video RAM ................................ 7-57
TMS4C1050B
1 048576-bit
(256K x 4) Field Memory ...................................... 7-109
TMS4C1060B
1 048 576-bit
(256K x 4) Field Memory ...................................... 7-121
TMS4C1070B
1 048 576-bit
(256K x 4) Field Memory ...................................... 7-133
7-2
TMS55160
262 144 BY 16·BIT
MULTIPaRT VIDEO RAM
SMVS160B-AUGUST 1992-REVISED JANUARY 1993
•
•
•
•
•
•
•
•
•
•
•
•
•
•
3·State Serial Outputs Allow Easy
Multiplexing of Video Data Streams
All Inputs/Outputs and Clocks TTL
Compatible
Compatible With JEDEC Standards
•
•
•
Texas Instruments EPIC'· CMOS Process
•
Performance Ranges:
BE
Vss
SOlS
0015
S014
0014
VCC
S013
0013
S012
0012
VSS
S011
0011
SOlO
0010
VCC
S09
009
SOS
DOS
VSS
DSF
NC/GND
CASU
OSF
AO
Al
A2
A3
VSS
AS
A?
AS
AS
A4
VCC
DRAM Port is Compatible With the
TMS45160
Up to 45-MHz Uninterrupted Serial Data
Streams
256 Selectable Serial Register Starting
Locations
SE Controlled Register Status QSF
Split Serial Data Register for Simplified
Real-Time Register Reload
SC
VCC
TRG
Vss
sao
000
Sal
001
VCC
S02
002
S03
003
VSS
S04
004
S05
005
VCC
SOS
DOS
SO?
DO?
VSS
CASL
WE
RAS
Enhanced Page-Mode Operation for Faster
Access
CAS-Before-RAS and Hidden Refresh
Modes
Long Refresh Period ... Every 8 ms (Max)
•
•
DGH PACKAGEt
(TOP VIEW)
DRAM: 262 144 Words x 16 Bits
SAM: 256 Words x 16 Bits
Dual Port Accessibility - Simultaneous and
Asynchronous Access From the DRAM and
SAM Ports
Data Transfer Function From the DRAM to
the Serial Data Register
(4 x 4) x 4 Block Write Feature for Fast Area
Fill Operations. As Many as Four Memory
Address Locations Written Per Cycle From
the 16·Blt On·Chip Color Register
Write-Per-Bit Feature for Selective Write to
Each RAM I/O. Two Write-Per-Bit Modes to
Simplify System Design
Byte Write Control (CASL, CASU) Provides
Flexibility
t Package is shown for pinout reference only.
PIN NOMENCLATURE
AO-AS
CASL, CASU
DOO-D015
SE
RAS
SC
SOO--S015
TRG
WE
DSF
OSF
Designed to Work With the
Industry-Leading Texas Instruments
Graphics Family
VCC
VSS
NC/GND
Address Inputs
Column-Address Strobe / Byte Selects
DRAM Data I/O, Write Mask Data
Serial Enable
Row-Address Strobe
Serial Clock
Serial Data Output
Output Enable, Transfer Select
DRAM Write Enable Select
SpeCial Function Select
Special Function Output
5-V Supply (TYP)
Ground
No ConnecVGround (Important: Not connected
internally to VSS)
ACCESSTIME
ROWENABLE
la{R)
(MAX)
ACCESS TIME
SERIAL DATA
la{SO)
(MAX)
DRAM
CYCLETIME
le(rd W)
(MIN)
DRAM
PAGE MODE
le(P)
(MIN)
SERIAL
CYCLE TIME
le(SC)
(MIN)
OPERATING CURRENT
SERIAL PORT
STANDBY
ICC1
(MAX)
OPERATING CURRENT
SERIAL PORT
ACTIVE
ICC1A
(MAX)
70 ns
SO ns
20 ns
25 ns
130 ns
150 ns
45 ns
50 ns
22 ns
30 ns
165mA
160mA
205mA
195mA
TMS55160-70
TMS55160-S0
EPIC is a trademark of Texas Instruments Incorporated.
~~~~~~~:::~: ~nf':r::!~:.I~~U;:~!r~~ :: I.=~~~~:m~~~i
ltand.rd warranty. Production proc ...lng do.. not n.c••••rlly Include
tHUng of ,II parameters.
TEXAS
~
Copyright © 1993, Texas Instruments Incorporated
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
7-3
TMS55160
262 144 BY 16·BIT
MULTIPaRT VIDEO RAM
SMVS160B--AUGUST 1992-REVISED JANUARY 1993
description
The TMS55160 multiport video RAM is a high-speed dual-ported memory device. It consists of a dynamic
random-access memory (DRAM) organized as 262144 words of 16 bits each, interfaced to a serial data register
[serial access memory (SAM)], organized as 256 words of 16 bits each. The TMS55160 supports three basic
types of operation: random access to and from the DRAM, serial access from the serial register, and transfer
of data from any row in the DRAM to the serial register. Except during transfer operations, the TMS55160 can
be accessed simultaneously and asynchronously from the DRAM and SAM ports.
The TMS55160 is equipped with several features designed to provide higher system-level bandwidth and to
simplify design integration on both the DRAM and SAM ports. On the DRAM port, greater pixel draw rates can
be achieved by the device's (4 x 4) x 4 block write feature. The block write mode allows sixteen bits of data
(present in an on-chip color data register) to be written to any combination of four adjacent column address
locations. As many as 64 bits of data can be written to memory during each CAS cycle time. Also on the DRAM
port, a write mask or a write-per-bit allows masking of any combination of the 16 inputs/outputs on any write
cycle. The persistent write-per-bitfeature uses a mask register which, once loaded, can be used on subsequent
write cycles without reloading. The TMS55160 also offers byte control. Byte control can be applied in read
cycles, write cycles, block write cycles, load mask register cycles, and load color register cycles.
The TMS55160 offers a split-register transfer read (DRAM to SAM) feature for the serial register (SAM port).
This feature enables real-time register reload implementation for truly continuous serial data streams without
critical timing requirements. The register is divided into a high half and a low half. While one half is being read
out of the SAM port, the other half can be loaded from the memory array. This real-time register reload
implementation allows truly continuous serial data. For applications not requiring real-time register reload (for
example, reloads done during CRT retrace periods), the single-register mode of operation is retained to simplify
system design.
The SAM port is designed for maximum performance. Data can be accessed from the SAM at serial rates up
to 45 MHz. During the split-register transfer reads, internal circuitry detects when the last bit position is accessed
from the active half ofthe register and immediately transfers control to the opposite half. A separate output, QSF,
is included to indicate which half of the serial register is active at any given time in the split register mode.
All inputs, outputs, and clock signals on the TMS55160 are compatible with Series 74 TTL. All address lines and
data-in are latched on chip to simplify system design. All data-outs are unlatched to allow greater system
flexibility.
The TMS55160 employs state-of-the-art Texas Instruments EPIC'· scaled-CMOS, double-level
polysilicon/polycide gate technology for very high performance combined with low cost and improved reliability.
The TMS55160 is offered in a 64-pin super-small-outline gull-wing leaded package for direct surface mounting.
The TMS55160 and other TI multiport video RAMs are supported by a broad line of graphics processors and
control devices from Texas Instruments.
TEXAS ."
INsrRUMENTS
7-4
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
TMS55160
262 144 BY 16·BIT
MULTIPaRT VIDEO RAM
SMVS160B-AUGUST 1992-REVISED JANUARY 1993
functional block diagram
r--------,
I
~------~I
/1------,
1 of 4 Sub-Blocks
(See Next Page)
DSF
I
I
I _ _ _ _ _ _ _ _ .JI
L
Input 1-----,
Buffer 1-----,
Input
Buffer
1 of 4 Sub-Blocks
(See Next Page)
DQODQ15
I
I
IL _ _ _ _ _ _ _ _ .JI
AO-A8
1 of 4 SubBlocks
(See Next Page)
I
I
L _ _ _ _ _ _ _ _ .J
SQO-SQ15
Serial
Output
Buffer
r--------,
~~~--~
RAS
CASx
TRG
WE
SC
Timing
Generator
I
I
I
II
~--~~
1 of 4 SubBlocks
(See Next Page)
I'v---------'
I
IL _ _ _ _ _ _ _ _ .JI
SE
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
7-5
TMS55160
262 144 BY 16·BIT
MULTIPaRT VIDEO RAM
SMVS160B-AUGUST 1992-REVISED JANUARY 1993
functional block diagram (continued)
OQI
OQI+1
OQI+2
OQI+3
RAS
CASx
TRG
WE
SC
Timing
Generator
512 x 512
Memory
Array
SE
Row
Decoder 1'\,-----.-,
SQI
SQI+1
SQI+2
SQI+3--....--.~ --
I
~
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ JI
Serial
Address
Counter
Refresh
Counter
1 of 4 Sub-Blocks
QSF
TEXAS ~
INsrRUMENTS
7-6
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
TMS55160
262 144 BY 16·BIT
MULTIPaRT VIDEO RAM
SMVS160B-AUGUST 1992-REVISED JANUARY 1993
Table 1. Function Table
CASx
FALL
RAS FALL
DQO-DQ1st
ADDREssll
FUNCTION
CASx:j:
TRG
WE
DSF
DSF
RAS
CASx
RAS
CASL
CASU
WE
MNE
CODE
-
Reserved (do not use)
0
0
0
0
X
X
X
X
X
CAS·before-RAS refresh
(option reset)§
0
X
1
0
X
X
X
X
X
CBR
CAS-before-RAS refresh
(no reset)~
0
X
1
1
X
X
X
X
X
CBRN
Tap
Point
X
X
RT
Read transfer
1
0
1
0
X
Row
Addr
Split-register read transfer
1
0
1
1
X
Row
Addr
Tap
Point
X
X
SRT
Write
Mask
Valid
Data
RWM
DRAM write
(non-persistent write-per-bit)
1
1
0
0
0
Row
Addr
Col
Addr
DRAM block write
(non-persistent write-per-bit)
1
1
0
0
1
Row
Addr
Block
Addr
A2.-A8
Write
Mask
Col
Mask
BWM
DRAM write
(persistent write-per-bit)
1
1
a
0
0
Row
Addr
Col
Addr
X
Valid
Data
RWM
X
Col
Mask
BWM
DRAM block write
(persistent write-per-bit)
1
1
a
a
1
Row
Addr
Block
Addr
A2.-A8
DRAM write (non-masked)
1
1
1
0
0
Row
Addr
Col
Addr
X
Valid
Data
RW
X
Col
Mask
BW
X
Write
Mask
LMR
X
Color
Data
LCR
DRAM block write (non-masked)
1
1
1
0
1
Row
Addr
Block
Addr
A2.-A8
Load write mask register #
1
1
1
1
0
Refresh
Addr
X
1
Refresh
Addr
Load color register
1
1
1
1
X
t DOO-D015 are latched on either the first CASx falling edge or the falling edge of WE, whichever occurs later.
:j: Logic 0 is selected when either or both CASL and CASU are low.
§ CAS-before-RAS refresh (option reset) mode will end persistent write-per-bit mode. Hidden refresh will also end the persistent write-per-bit mode
regardless of the state of DSF at RAS.
~ CAS-before-RAS refresh (no reset) mode will not end persistent write-per-bit mode.
# Load Write Mask Register cycle will set the persistent write-per-bit mode. The persistent write-per-bit mode is reset only by the CAS-before-RAS
(option reset) cycle.
II The column address and block address are latched on the first CASx falling edge.
X = Don't care.
Col Mask
=1: Write to address/column enabled.
Write Mask = 1: Write to I/O enabled.
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
7-7
TMS55160
262144 BY 16·BIT
MULTIPaRT VIDEO RAM
SMVSI60B-AUGUST 1992-REVISED JANUARY 1993
Table 2. Pin Description vs Operational Mode
PIN
TRANSFER
DRAM
AO-AS
Row, column address
Row-address, tap point
CASx
Column address strobe, DO output enable
Tap address strobe
DO
DRAM data I/O, Write mask
DSF
RAS
Block write enable
Write mask register load enable
Color register load enable
CAS-before-RAS (option reset)
Split register transfer enable
Row address strobe
Row address strobe
SAM
SE
SO output enable,
OSF output enable
SC
Serial clock
sa
Serial data output
TRG
DO output enable
WE
Write enable
Transfer enable
Serial register status
OSF
NC/GND
Make no external connection or tie to system GND
VCCt
S-V Supply
vsst
Ground
t For proper device operation, all VCC pins must be connected to a S-V supply, and all VSS pins must be !led to ground.
pin definitions
address (AO-AS)
Eighteen address bits are required to decode one of 262 144 storage cell locations. Nine row address bits are
set up on pins AO-AS and latched onto the chip on the falling edge of RAS. Nine column address bits are set
up on pins AO-AS and latched onto the chip on the first falling edge of CASx. All addresses must be stable on
or before the falling edge of RAS and the first falling edge of CASx.
During the read transfer operation, the states of AO-AS are latched on the falling edge of RAS to select one of
the 512 rows where the transfer will occur. At the first falling edge of CASx, the column address bits AO-AS are
latched. The most significant column address bit (AS) selects which half of the row will be transferred to the SAM.
The appropriate S-bit column address (AO-A7) selects one of 256 tap points (starting positions) for the serial
data output.
During the split register read transfer operation, address bit A7 is ignored at the falling edge of CASx. An internal
counter will select which half of the register will be used. If the high half of the SAM is currently in use, the low
half of the SAM will be loaded with the low half of the DRAM half row, and vice versa. The remaining seven
address bits (AO-A6) are used to select 1 of 127 possible starting locations within the SAM. Locations 127 and
255 are not valid tap paints.
row-address strobe (RAS)
RAS is Similar to a chip enable, so that all DRAM cycles and transfer cycles are initiated by the falling edge of
RAS. RAS is a control input that latches the states of the row address, WE, TRG, CASL, CASU, and DSF onto
the chip to invoke DRAM and read transfer functions of the TMS55160.
TEXAS
~
INSfRUMENTS
7-S
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
TMS55160
262 144 BY 16·BIT
MULTIPORT VIDEO RAM
SMVS160B-AUGUST 1992-REVISEO JANUARY 1993
column-address strobe (CASL, CASU)
CASL and CASU are control inputs that latch the states of the column address and DSF to control DRAM and
read transfer functions of the TMS55160. CASx also act as output enable for the DRAM output pins,
DOo-D015.
In DRAM operation, CASL enables data to be written to or read from the lower byte (DOO-D07), and CASU
enables data to be written to or read from the upper byte (D08-D015).
In read transfer operations, address bits AO-A8 will be latched at the first falling edge of CASx as the start
postion (Tap) for the serial data output (SDOO-SD015).
output enable/transfer select (TRG)
The TRG pin selects either DRAM or read transfer operation as RAS falls. For DRAM operation, TRG must be
held high as RAS falls. During DRAM operation, TRG functions as an output enable for the DRAM output pins,
DOo-D015.
For read transfer operation, TRG must be brought low before RAS falls.
write mask select, write enable (WE)
In DRAM operation, WE enables data to be written to the DRAM.
WE is also used to select the DRAM write-per-bit mode of operation. Holding WE low on the falling edge of RAS
will invoke the write-per-bit operation. The TMS55160 supports both the non-persistent write-per-bit mode and
the persistent write-per-bit mode.
special function select (OSF)
The DSF input is latched on the falling edge of RAS or the first falling edge of CASx, similar to an address. DSF
determines which of the following functions below are invoked on a particular cycle:
•
CBR refresh with reset (CBR)
•
•
CBR refresh with no reset (CBRN)
Block write
•
Loading mask register for the persistent write-per-bit mode
•
•
Loading color register for the block write mode
Split-register read transfer
DRAM data 110, write mask data (000-0015)
DRAM data is written or read through the common I/O DO pins. The 3-state DO output buffers provide direct
TTL compatibility (no pullup resistors) with a fanout of one Series 74 TTL load. Data-out is the same polarity
as data-in. The outputs are in the high-impedance (floating) state as long as eitherTRG or CASx is held high.
Data will not appear at the outputs until after both CASx and TRG have been brought low. Once the outputs are
valid, they remain valid while TRG and CASx are low. Either CASx or TRG going high returns the outputs to a
high-impedance state. In a read transfer operation, the DO outputs remain in the high-impedance state for the
entire cycle.
The write-per-bit mask is latched into the device via the random DO pins by the falling edge of RAS.
serial data output (S00-5015)
Serial data is read from the SO pins. The SO output buffers provide direct TTL compatibility (no pullup resistors)
with a fanout of one Series 74 TTL load. Data-out is the same polarity as data-in. The serial outputs are in the
high-impedance (floating) state as long as serial enable pin, SE, is high. The serial outputs are enabled when
SE is brought low.
TEXAS
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MULTIPORT VIDEO RAM
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serial clock (SC)
Serial data is accessed out of the data register from the rising edge of SC. The TMS55160 is designed to work
with a wide range of clock duty cycles to simplify system design. There is no refresh requirement because the
data registers that comprise the SAM are static. There is also no minimum SC clock operating frequency.
serial enable (SE)
During serial access operations SE is used as an enable/disable for the sa outputs. SE low will enable the serial
data output. SE high will disable the serial data output. SE is also used as an enable/disable for output pin aSF.
IMPORTANT: While SE is held high, the serial clock is not disabled. Thus, external SC pulses will incrementthe
internal serial address counter regardless ofthe state of SE. This ungated serial clock scheme minimizes access
time of serial outputfrom SE low since the serial clock input buffer and the serial address counter are not disabled
bySE.
special function output (QSF)
aSF is an output pin that indicates which half of the SAM is being accessed. When aSF is low, the serial address
pointer is accessing the lower (least significant) 128 bits of the serial register (SAM). When aSF is high, then
the pointer is accessing the higher (most significant) 128 bits ofthe SAM. aSF may change state upon crossing
a boundary between the two SAM halves.
During the read transfer operation (non-split register), aSF may change state upon completing the cycle. This
state is determined by the tap point being loaded during the transfer cycle. During the split-register read transfer
operation, aSF may change state upon crossing a boundary between the two SAM halves.
aSF output is enabled by SE. If SE is high, then aSF output will be in the high-impedance state.
no connect/ground (NC/GND)
The NC/GND pin should be tied to system ground or left floating for proper device operation.
TEXAS ~
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functional operation description
random access operation
Table 3. DRAM Function Table
CASx
FALL
RAS FALL
ADDRESS II
DQO-DQ1St
FUNCTION
CASx*
TRG
WE
DSF
DSF
RAS
CASx
RAS
CASL
CASU
WE
MNE
CODE
-
Reserved (Do not use)
0
0
0
0
X
X
X
X
X
CAS-before-RAS refresh
(option reset)§
0
X
1
0
X
X
X
X
X
CBR
CAS-before-RAS refresh
(no reset)~
0
X
1
1
X
X
X
X
X
CBRN
DRAM write
(non-persistent write-per-bit)
1
1
0
0
0
Row
Addr
Col
Addr
DO
Mask
Valid
Data
RWM
DRAM block write
(non-persistent write-per-bit)
1
1
0
0
1
Row
Addr
Blk Addr
A2-A8
DO
Mask
Col
Mask
BWM
DRAM write
(persistent write-per-bit)
1
1
0
0
0
Row
Addr
Col
Addr
X
Valid
Data
RWM
Blk Addr
A2-A8
X
Col
Mask
BWM
X
Valid
Data
RW
BW
DRAM block write
(persistent write-per-bit)
1
1
0
0
1
Row
Addr
DRAM write
(non-masked)
1
1
1
0
0
Row
Addr
Col
Addr
Blk Addr
A2-A8
X
Col
Mask
X
X
Write
Mask
LMR
X
Color
Data
LCR
DRAM block write
(non-masked)
1
1
1
0
1
Row
Addr
Load write mask register#
1
1
1
1
0
Refresh
Address
1
Refresh
Address
Load color register
1
1
1
1
X
t DOO-D015 are latched on either the first CASx falling edge or the falling edge of WE, whichever occurs later.
*Logic 0 is selected when either or both CASL and CASU are low.
§ CAS-before-RAS refresh (option reset) mode will end persistent write-per-bit mode. Hidden refresh will also end the persistent write-per-bit mode
regardless of the state of DSF at RAS.
~ CAS-before-RAS refresh (no reset) mode will not end persistent write-per-bit mode.
# Load Write Mask Register cycle will setthe persistent write-per-bit mode. The persistent write-per-bit mode is reset only by the CAS-before-RAS
(option reset) cycle.
II The column address and block address are latched on the first CASx falling edge.
X = Don't care.
Col Mask
= 1: Write to address/column enabled.
Write Mask = 1: Write to I/O enabled.
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refresh
CAS-before-RAS refresh
CAS-before-RAS refreshes are accomplished by bringing either or both CASL and CASU low earlier than RAS.
The external row address is ignored and the refresh row address is generated internally. Two types of CSR
refresh cycles are available. The CSR refresh (option reset) will end the persistent write-per-bit mode. The
CSRN refresh (No Reset) will not end the persistent write-per-bit mode. The 512 rows of the DRAM do not
necessarily need to be refreshed consecutively, as long as the entire refresh is completed within the required
time period trf(MA)' The output buffers remain in the high impedance state during the CAS-before-RAS refresh
cycles, regardless of the state of TRG.
hidden refresh
A hidden refresh is accomplished by holding both CASL and CASU low in the DRAM read cycle and cycling
RAS. The output data of the DRAM read cycle remains valid while the refresh is being carried out. Like the
CAS-before-RAS refresh, the refreshed row addresses are generated internally during the hidden refresh.
Hidden refresh will also end the persistent write-per-bit mode, regardless of the state of DSF at RAS.
RAS-only refresh
A RAS-only refresh is accomplished by cycling RAS at every row address. Unless CASx and TRG are low, the
output buffers remain in the high-impedance state to conserve power. Externally generated addresses must be
supplied during RAS-only refresh. Strobing each of the 512 row addresses with RAS causes all bits in each row
to be refreshed.
enhanced page mode
Enhanced page mode operation allows faster memory access by keeping the same row address while selecting
random column addresses. This mode eliminates the time required for row address setup, row address hold,
and address multiplex. The maximum RAS low time and CAS page cycle time used determines the number of
columns that may be accessed.
Unlike conventional page mode operations, the enhanced page mode allows the TMS55160 to operate at a
higher data bandwidth. Data retrieval begins as soon as column address is valid rather than when CASx
transitions low. Valid column address may be presented immediately after row address hold time has been
satisfied, usually well in advance olthe falling edge of CASx. In this case, data is obtained after talC) max ( access
time from CASx low), if ta(CA) max (access time from column address) has been satisfied.
TEXAS ~
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TMS55160
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MULTIPaRT VIDEO RAM
SMVS160B-AUGUST 1992-REVISEO JANUARY 1993
byte control
Byte control can be applied in DRAM read cycles, write cycles, block write cycles, load mask register cycles,
and load color register cycles. In byte operation, the column address (AD-AS) will be latched at the first falling
edge of CASx. In read cycles, CASL enables the lower byte (000-007), and CASU enables the upper byte
(00S-0015) (Figure 1).
RAS~~_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~/
~~i______________~;f
tsu(CA)
I I
~
i
1
AO-A8229<~RO_W~
la(C)
I..
\".._____...J;f
.1
th(CLCA)
I
c+" ~~~~===~~
.1
I"
DQO-DQ7----------------------------~<:~---L~:-w-er-B-Y-te-O-u-tP-u-t--~>~----t~(C)
DQ~DQI5
I"
.1
_______________________________rl------~(~~up-p-e~rB~Y~te~)
I
_ Output . >-----I
i+-
ta(G)
~
---II
~_I _ _ _
Figure 1. Example of a Byte Read
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In byte write operation, CASL enables data to be written to the lower byte (000-007) and CASU enables data
to be written to the upper byte (008-0015). In an early write cycle WE is broughtlow prior to both CASx signals,
and data setup and hold times for 000-0015 are referenced to the first falling edge of CASx (Figure 2).
~~----------~/
~~i----------------~/
i I
tsu{CA)
AO-A8
\
II I
thCLCA)
I~
i
~I
I
~
th{DCL)
~"'-'J;-al-Id-In-p-ut-o-at-a""""'i~
Figure 2. Example of an Early Write
TEXAS ~
INSTRUMENTS
7-14
/
.......- - - - '
229<___~: "'i~H~~~-tsu{OCL)
OQO-OQ15
~ i+J
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TMS55160
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MULTIPaRT VIDEO RAM
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For late-write or read-modify-write cycles, WE is brought low after either or both CASL and CASU fall. The data
is strobed in with data setup and hold times for 000-0015 referenced to WE (Figures 3 and 4).
RAS~_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~I
\ ______---'1
\1......._------/
1\-----'1
tsu(DCL) -toIl
..I-----.!.1
i
I
I
114
.. ----I.~i
-
th(DCL)
DQO-DQ15,.._D_a_ta_ln_p_u_tV_a_li_d_~~~7":7'=~~~:7
Figure 3. Example of a Late Write
RAS~_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~I
\-----_ _ _ _--'1
\'--_ _--J/
I\,.......-----......JI
tsu(DCL)
-+Ol"~:----I.~!
th(DCL)
I"
DQO-DQ15
Data Input Valid
Figure 4. Example of a Late Write
TEXAS
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write-per-bit
The write-per-bit feature allows masking any combination of the 16 DOs on any write cycle. The write-per-bit
operation is invoked when WE is held low on the falling edge of RAS.
If WE is held high on the falling edge of RAS, the write operation will be performed without any masking. The
TMS55160 offers two write-per-bit modes: the non-persistent write-per-bit and the persistent write-per-bit.
non-persistent write-per-bit
When WE is low on the falling edge of RAS, the write mask is reloaded. A 16-bit binary code (the write-per-bit
mask) is input to the device via the random DO pins and latched on the falling edge of RAS. The write-per-bit
mask selects which of the sixteen random I/Os are written and which are not. After RAS has latched the on-chip
write-per-bit mask, input data is driven onto the DO pins and is latched on either the first CASx falling edge or
the falling edge of WE, whichever occurs later. CASL enables the lower byte (000-007) to be written, and
CASU enables the upper byte (008-0015) to be written, perthe mask. If a data low (write mask =0) is strobed
into a particular I/O pin on the falling edge of RAS, data will not be written to that I/O. If a data high (write
mask = 1) is strobed into a particular i/O pin on the falling edge of RAS, data will be written to that I/O
(Figure 5).
~-i________________~I
I
I
I
I
I
I
I
I
I
\
ts (RWM)
u
OQ()-[)QI5
I~
I
I
I
I
ID(
I
I
I
I
I
I
I
I
I
: i
I I
--I I
\~_ _ ____JI
\I..--_ _ _ _---JI
!\"'-----'~=.;.~~~
I I
I
I~
--I
1
1
Write Mask Oala
Ih(RWML)
I"
I
~
I I~
--I
I
1
--I Isu(OWL)
Ih(OWL)
I
Valid Input Oala
~
Figure 5. Example of Non-Persistent Write-Per-Bit (Late Write)
TEXAS
~
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persistent write-per-bit
The persistent write-per-bit mode is initiated only by performing a load mask register cycle first. In the persistent
write-per-bit mode, the write-per-bit mask will not be overwritten but will remain valid over an arbitrary number
of write cycles until another LMR cycle is performed or power is removed.
The load write mask register cycle is performed using DRAM write cycle timing, except DSF is held high on the
falling edge of RAS and held low on the first falling edge of CASx. A binary code is input to the write mask register
via the random I/O pins and latched on either the first CASx falling edge or the falling edge of WE, whichever
occurs later. Byte write control can be applied to the write mask during the load mask register cycle. The
persistent write-per-bit mode can then be used in exactly the same way as the non-persistent write-per-bit mode,
except that the input data on the falling edge of RAS is ignored. When the device is set to the persistent
write-per-bit mode, it will remain in this mode and will be reset only by a CAS-before-RAS refresh with option
reset cycle (Figure 6). A hidden refresh cycle will also end the persistent write-per-bit mode, regardless of the
state of DSF.
I
Load Write Mask Register
RAsh
/
I
I
CAsxi
I
\
/
Persistent Write-Per-Bit
\
I
I
/
I
I
\
/
n
CBR Refresh (Option Reset)
\
I
I
I
I
\
I
I
I
----I
I
I
AG-A8
DSF~~~
WE~~
~~~
~~
DQ1~ WrlteMaSk~
Data
Mask Data
~~
Write
Data
1 : Write to I/O Enabled
o : Write to I/O Disabled
Figure 6. Example of a Persistent Write-Per-Bit
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block write
The block write feature allows up to 64 bits of data to be written simultaneously to one row of the memorY array.
This function is implemented as (4 columns x 4 DOs) repeated· in four quadrants. In this manner, each of the
four one-megabit quadrants may have up to 4 consecutive columns written at a time with up to 4 DOs per column
(see Figure 7).
OQ1SOII]
OQ140II]
OQ130II]
4th Quadrant
OQ120II]
OQ11OII]
OQ100II]
3rd Quadrant
OQ90II]
OQSOII]
One Row of 0--511
OQ70II]
DQSOII]
2nd Quadrant
DQSOII]
OQ40II]
DQ30II]
OQ20II]
1st Quadrant
OQ10II]
DQOW
4 Consecutive Columns of 0--511
Figure 7_ Block Write
Each one-megabit quadrant has a 4-bit column mask to mask off any or all of the four columns from being written
with data. Non-persistent write-per-bit or persistent write-per-bit functions can be applied to the block write
operation to provide write masking options. The DO data is provided by 4 bits from the on-chip color register.
Bits 0-3 from the 16-bit write mask, bits 0-3 from the 16-bit column mask and bits 0-3 from the 16-bit color data
register configure the block write for the first quadrant, while bits 4-7, 8-11, 12-15, control the other quadrants
in a similar fashion.
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001 2
,..I
r - - ..,
...1_.., I
]
-..,
I I
I I II
I ~ .J
D011[IIJ
I'
,;)'I>I§
0010 [ I I J
t:,Ci
r§
009 [ I I J
DOS[
One Row of 0--511
ill r--..,
...1_..,
12 t->I~
13
14
'""
15
~
~
.J
.J
I
I
-.., I
I I I
.-+++-h
S
9
10
11
o~'Ii
-..,
4
:
D01[IIJ
I
I
I I I
r+++M
D02[IIJ
....t
.J
I
...1_..,
D03[IIJ
I ~.J
tl.J
r--'"
D040I]
~
g.'Ii
lo.
-.llo.
~~
I
~~
~
tl.J
.J
.J
7 +++-hQ
...
~
0
c
§
8
2
3 +t-+-I-O
~~
I~
~ lo.
~;lo.
\ 0
1
2
3
4
5
6
7
S
9 10 11
12 13 14 15 /
~------------------------~vr------------------------~
Color Register
Figure 8. Block Write With Masks
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Every 4 columns makes a block, which makes 128 blocks along one row. Block 0 comprises columns 0-3, block
1 comprises columns 4-7, block 2 comprises columns 8-11, etc., as below (Figure 9).
Block 0
Block 1 ...................... Block 127
A""_ _, ,
1~---,A'--_'V~-----1A
One Row of 0-511
I
I·
o
2
I
1
3
4
5
7 .......................... . 511
6
/
'------------~V
Columns
Figure 9. Block Columns Organization
Ouring block write cycles, only the seven most significant column addresses (A2-A8) are latched on the first
falling edge of CASx to decode one of the 128 blocks. Address bits AO-A 1 are ignored. (Each one-megabit
quadrant has the same block selected.)
A block write cycle is entered in a manner similar to a ORAM write cycle except with OSF held high on the first
falling edge of CASx. As in a ORAM write operation, CASL and CASU enable the corresponding lower and upper
ORAM 00 bytes to be written, respectively. The column mask data is input via the OOs and is latched on either
the first CASx falling edge or the falling edge of WE, whichever occurs later. The 16-bit color data register must
be loaded prior to performing a block write, as described below. Refer to the write-per-bit section for details on
use of the write mask capability, allowing additional performance options.
Example of block write:
block write column address
= 110000000 (AO-A8 from left to right)
bit 0
color data register
write mask
column mask
bit 15
1011
1110
1111
1st
Ouad
1011
1111
0000
2nd
Ouad
1100
1111
0111
3rd
Ouad
0111
1011
1010
4th
Ouad
Column address bits AO and A 1 are ignored. Block 0 (columns 0-3) is selected for each one-megabit quadrant.
The first quadrant has 000-002 written with bits 0-2 from the color data register (101 ) to all four columns of
Block O. 003 is not written and retains its previous data due to the write mask register bit 3 being a O.
The second quadrant ( 004'-007) has all four columns masked off due to the column mask bits 4-7 being 0,
so that no data is written.
The third quadrant ( 008-0011 ) has its four OOs written with bits 8-11 from the color data register (1100) to
columns 1-3 of its Block O. Column 0 is not written and retains its previous data on all four OOs due to the column
mask register bit 8 being O.
TEXAS
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The fourth quadrant (0012-0015) has 0012, 0014, and 0015 written with bits 12, 14, and 15 from the color
data register to column 0 and column 2 of its Block O. 0013 retains its previous data on all columns, due to
the write mask. Columns 1 and 3 retain their previous data on all ~Os due to the column mask. If the previous
data for the quadrant was all Os, the fourth quadrant would contain the following data pattern after the block write
operation shown in the previous example.
OQ1511 \ 0 \1 \ 0
OQ1411 \ 0 \1 \ 0
1
I
4th Quadrant
Figure 10. Example of Fourth Quadrant after Block Write
load color register
The load color register cycle is performed using normal ORAM write cycle timing except that OSF is held high
on the falling edges of RAS, CASL, and CASU. The color register is loaded from pins 000-0015, which are
latched on either the first CASx falling edge or the falling edge of WE, whichever occurs later. If only one CASx
is low, only the corresponding byte of the color register is loaded. When the color register is loaded, it retains
data until power is lost or until another load color register cycle is performed (Figure 10, Figure 11).
1
Load Color Register Cycle
1
I
RAS
OQO-OQ15
4
I
I
Block Write Cycle
(No Write Mask)
Block Write Cycle
(Load and Use Write Mask)
I
I
I
1
\'I.. __...JI I
\'1.._ _...Jrl
~,.-!..I
-===~_--J/I
/1\.1
r--\
I
~~[§§l~~
1
1
1
6
Legend:
1. Refresh address
2. Row address
3.
Block address (A2-A8) is latched on the first CASx falling edge.
4. Color register data
5. Write mask data: DQO-DQ15 are latched on RAS falling edge.
6. Column mask data: DQi-DQi+3 (i=O,4,8.12) are latched on either the first CASx falling edge or the falling edge of WE, whichever occurs
later.
~ = Don't Care
Figure 11. Example of Block Writes With Write Masks
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SMVSl60B-AUGUST 1992-REVISED JANUARY 1993
I
I
I
i
RAS r-"'\.'\.~
CASx
I
I
I
Load Mask Register Cycle
____--J/~
i '\.
--JI
! - o l- - - - " " ' \ ' ' -_ _
I
I
I
Load Color Register
/""j\.
I
I
I
I
Persistent Block Write Cycle
(Use loaded Write Mask)
/I
''--_....J/--l
''-__...JI I
Legend:
I . Refresh address
2. Row address
3.
Block address (A2-A8) is latched on the first CASx falling edge.
4.
Color register data
5.
Write mask data: DOO-DOIS are latched on CASx falling edge.
6.
Column Mask Data: DOj-DOi+3 (i~0,4,8, 12) are latched on either the first CASx falling edge or the falling edge of WE, whichever occurs
later.
~ = Don't Care
Figure 12, Example of a Persistent Block Write
DRAM to SAM transfer operation
During the DRAM to SAM transfer operation, one half of a row (256 columns) in the DRAM array is selected
to be transferred to the 256-bit serial data register. The transfer operation is invoked by bringing TRG low and
holding WE high on the falling edge of RAS. The state of DSF, which is latched on the falling edge of RAS,
determines whether the read transfer operation or the split register read transfer operation will be performed.
Table 4, SAM Function Table
CASx
FALL
RAS FALL
FUNCTION
DQO-DQ1st
ADDRESS
MNE
CODE
CASx:t
TRG
WE
DSF
DSF
RAS
CASx
RAS
CASx
WE
Read transfer
I
0
I
0
X
Row
Addr
Tap
Point
X
X
RT
Split register read transfer
I
0
I
I
X
Row
Addr
Tap
Point
X
X
SRT
t DOO-DOIS are latched on either the first CASx falling edge or the falling edge of WE, whichever occurs later.
:j: Logic 0 is selected when either or both CASL and CASU are low.
X: = Don't care.
TEXAS
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INSTRUMENTS
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MULTIPaRT VIDEO RAM
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read transfer
A read transfer operation loads data from a selected half of a row in the DRAM into the SAM. TRG is brought
low and latched at the falling edge of RAS. Nine row address bits (AD-AS) are also latched at the falling edge
of RAS to select one ofthe 512 rows available for the transfer. The nine column address bits (AD-AS) are latched
at the first falling edge of CASx, where address bit AS selects which half of the row will be transferred. Address
bits AD-A? select one of the SAM's 256 available tap points from which the serial data will be read out (Figure
13).
o
AS=O
255 256
AS=1
511
512 x 512
Memory Array
256 Bit
Data Register
o
255
Figure 13. Read Transfer
A read transfer can be performed in three ways: early-load read transfer, real-time or mid-line-load read transfer,
and late-load read transfer. Each of these offers the flexibility of controlling the TRG trailing edge in the read
transfer cycle (Figure 14).
Early Load Read Transfer
1
RAS
1
/T\.
r---'\
1
1
CASx 1
1
\
I
1
1
1
1
Real-Time Reload Read
Transfer
\
Late-Load Read Transfer
1
/T\.
I
1
1
1
1
I
'---./
1
1
1
Tap~1
A
Row
TapORow
Tap A
Row S .
1
Point
1
Point
1
Point
TRG
I \
I
I \
1
1
1
1
n
WEp~~~
f""'\..J
1
1
'--....1,......,
1
Figure 14. Examples of Read Transfer
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443· HOUSTON, TEXAS 77001
7-23
TMS55160
262144 BY 16·BIT
MULTIPORT VIDEO RAM
SMVS160B-AUGUST1992-REVISED JANUARY 1993
split-register read transfer
In the split-register read transfer operation, the serial data register is split into halves. The low half contains bits
0-127, and the high half contains bits 128-255. While one half is being read out ofthe SAM port, the other half
can be loaded from the memory array.
o
AS=O
255256
AS=1
511
512 x 512
Memory Array
256 Bit
Data Register
o
255
Figure 15. Split Register Read Transfer
To invoke a split-register read transfer cycle, DSF is brought high, TRG is brought low, and both are latched at
the falling edge of RAS. Nine row address bits (AO-A8) are also latched at the falling edge of RAS to select one
of the 512 rows available for the transfer. Eight of the nine column address bits (AO-A6 and A8) are latched at
the first falling edge of CASx. Column address bit A8 selects which half of the row is to be transferred. Column
address bits AD-A6 will select one of the 127 tap paints in the specified half of the SAM. Column address bit
A7 is ignored and the split register transfer is internally controlled to select the inactive register half.
AS=O
AS = 1
~
~
511
0
DRAM
SAM
A7=Ot
0
511
AS= 1
AS=O
~
~
A7=1t 511
0
o A7=Ot
511
m m m II
'~
'~~
A
'ihi
B
C
SQ
'~
C
B
SQ
E D
D
SQ
SQ
t A7 shown is internally controlled
Figure 16. Example of Split-Register Read Transfer Operation
A read transfer (non-split register) must precede the first split register read transfer to ensure proper operation.
After the read transfer cycle, the first split-register read transfer can follow immediately without any minimum
SC clock requirement. However, there is a minimum requirement of a rising edge of SC between successive
split-register read transfer cycles.
TEXAS
~
INSTRUMENTS
7-24
POST OFFICE BOX 1443· HOUSTON, TEXAS 77001
TMS55160
262 144 BY 16·BIT
MULTIPORT VIDEO RAM
SMVS160B-AUGUST 1992-REVISED JANUARY 1993
aSF indicates which half of the register is being accessed during serial access operation. When aSF is low,
the serial address pointer is accessing the lower (least significant) 128 bits of SAM. When aSF is high, the
pointer is accessing the higher (most significant) 128 bits of SAM. aSF changes state upon completing a read
transfer cycle. The tap pOint loaded during the current transfer cycle determines the state of aSF. aSF also
changes state when a boundary between two register halves is reached.
Read Transfer
With Tap Point N
Split Register
Read Transfer
I
\
RAS
I
\
CASx
I
\
I
\
1
1
\
TRG
DSF
SC
I
Ii
1
1
1
1
I
1
1
1
I
\
1\
1
1
1
I
~
Point N
I.-- td(CLQSF) ~
X
td(GHQSF)
14
QSF
Figure 17. Example of a Split-Register Read Transfer After a Read Transfer
Split Register
Read Transfer
With Tap Point N
~
\
RAS
\
CASx
Split Register
Read Transfer
1
~
1
I
\1
1
1
1
1
td(RHMS)~ 14
SC
n
I
1
1
DSF~
I
\
1
1
1
TRG~
I
1\
1
~I
td(MSRL)
1 1
1
i4---"~1-1-
QSF ________________________________-J>t~:
td(SCQSF)
______________________
Figure 18. Example of Successive Split-Register Read Transfers
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
7-25
TMS55160
262 144 BY 16·BIT
MULTIPaRT VIDEO RAM
SMVS160B-AUGUST 1992-REVISEO JANUARY 1993
serial access operation
The serial read operation can be performed through the SAM port simultaneously and asynchronously with
DRAM operations except during read transfer operations.
Serial data can be read from the SAM by clocking SC starting at the tap point loaded by the preceding transfer
cycle, then proceeding sequentially to the most significant bit (bit 255) and then wrapping around to the least
significant bit (bit 0) (Figure 19).
Figure 19. Serial Pointer Direction for Serial Read
For split-register operation, serial data can be read out from the active half of SAM by clocking SC starting at
the tap point loaded by the preceding split-register transfer cycle. The serial pointer will then proceed
sequentially to the most Significant bit of the half, bit 127 or bit 255. If there is a split-register read transfer to the
inactive half during this period, the serial pointer will pOint next to the tap point location loaded by that split
register transfer (Figure 20).
Figure 20. Serial Pointer for Split Register Read - Case I
If there is no split-register read transfer to the inactive half during this period, the serial pOinter will pOint next
to bit 128 or bit 0 respectively (Figure 21).
Figure 21. Serial Pointer for Split Register Read - Case II
power up
To achieve proper device operation, an initial pause of 200 !-Is is required after power-up, followed by a minimum
of eight RAS cycles or eight CAS-before-RAS cycles to initialize the DRAM port. A read transfer cycle and two
SC cycles are needed to initialize the SAM port.
After initialization the internal state of the TMS55160 is as follows:
State After Initialization
QSF
Write mode
Write mask register
Color register
Serial register tap point
SAM port
Defined by the transfer cycle during initialization
Non·persistent mode
Undefined
Undefined
Defined by the transfer cycle during initialization
Output mode
TEXAS
~
INSTRUMENTS
7-26
POST OFFICE BOX 1443· HOUSTON. TEXAS 77001
TMS55160
262 144 BY 16-BIT
MULTIPORT VIDEO RAM
SMVS160B-AUGUST 1992-REVISED JANUARY 1993
absolute maximum ratings over operating free-air temperature t
Supply voltage range on any pin except DO and SO (see Note 1) ......................... -1 V to 7 V
Voltage range on DO and SO (see Note 1) ............................................. -1 V to 7 V
Voltage range on Vee (see Note 1) ................................................... -1 V to 7 V
Short-circuit output current ................................................................ 50 mA
Power dissipation ........................................................................ 1.1 W
Operating free-air temperature range ..................................................
to 70°C
Storage temperature range ....................................................... -65°C to 150°C
ooe
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. This is a stress rating only. and
functional operation of the device at these or any other conditions beyond those indicated in the "recommended operating conditions" section of
this specification is not implied. Exposure to absolute-maximum-rated conditions for eX1ended periods may affect device reliability.
NOTE I: All voltage values in this data sheet are with respect to VSS.
recommended operating conditions
MIN
NOM
MAX
4.5
5
5.5
UNIT
VCC
Supply voltage
VSS
Supply voltage
VIH
High-level input voltage
2.4
6.5
VIL
Low-level input voltage (see Note 2)
-I
0.8
V
TA
Operating free-air temperature
0
70
"C
..
..
..
V
V
0
V
NOTE 2: The algebraic convention. where the more negative (less pOSItive) limit IS designated as minimum. IS used In thiS data sheet for logic
voltage levels only.
electrical characteristics over full ranges of recommended operating conditions
PARAMETER
SAM
PORT
TEST CONDITIONS
VOH
High-level output voltage
IOH =-1 rnA
VOL
Low-level output voltage
10L= 2 rnA
II
TMS55160-aO
TMS55160-70
MIN
MAX
2.4
MIN
MAX
UNIT
V
2.4
0.4
0.4
V
Input current (leakage)
VI = 0 to 5.8 V. VCC = 5.5 V.
All other pins at 0 to VCC
±IO
±IO
~A
10
Output leakage current (see Note 3)
Vo = Oto VCC.
VCC = 5.5V
±IO
±IO
~
ICCI
Operating current
See Note 4
Standby
165
160
ICCIA
Operating current
lc(SC) = MIN
Active
205
195
ICC2
Standby current
All clocks = VCC
Standby
ICC2A
Standby current
tc(SC) = MIN
Active
5
5
50
45
ICC3
RAS-only refresh current
See Note 4
Standby
165
160
ICC3A
RAS-only refresh current
tc(SC) = MIN
Active
195
185
ICC4
Page-mode current
tc(P) = MIN (see Note 5)
Standby
100
95
ICC4A
Page-mode current
tc(SC) = MIN
Active
130
125
ICC5
CAS-before-RAS current
See Note 4
Standby
165
160
ICC5A
CAS-belore-RAS current
tc(SC) = MIN
Active
205
195
ICC6
Data transfer current
See Note 4
Standby
165
160
ICC6A
Data transfer current
lc(SC) = MIN
Active
205
195
NOTES:
rnA
sa
3. SE IS disabled for
output leakage tests.
4. Measured with one address change while RAS = VIL. tc(rd).lc(W). tc(TRD) = MIN.
5. Measured with one address change while CASx = VIH
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
7-27
TMS55160
262 144 BY 16·BIT
MULTIPaRT VIDEO RAM
SMVS160B-AUGUST 1992-REVISED JANUARY 1993
capacitance over recommended ranges of supply voltage and operating free-air temperature,
f = 1 MHz (see Note 6)
PARAMETER
MIN
MAX
UNIT
Ci(A)
Input capacitance, address inputs
6
pF
Ci(RC)
Input capacitance, strobe inputs
7
pF
Ci(W)
Input capacitance, write enable input
7
pF
Ci(SC)
Input capacitance, serial clock
7
pF
Ci(SE)
Input capacitance, serial enable
7
pF
Ci(DSF)
Input capacitance, special function
7
pF
Ci(TRG)
Input capacitance, transfer register input
7
pF
CoCO)
Output capacitance, SO and DO
7
pF
9
pF
Co(OSF) Output capacitance, OSF
NOTE 6: VCC equal to 5 V ± 0.5 V and the bias on pins under test is 0 V.
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (see Note 7)
PARAMETER
TEST
CONDITIONS
ALT.
SYMBOL
TMS55160-70
MIN
MAX
TMS55160-S0
MIN
MAX
UNIT
ta(C)
Access time from CASx (see Note 7)
td(RLCL) = Max
tCAC
20
20
ns
ta(CA)
Access time from column address (see Note 7)
td(RLCL) = Max
tAA
35
40
ns
ta(CP)
Access time from CASx high (see Note 7)
td(RLCL) = Max
tCPA
40
45
ns
ta(R)
Access time from RAS (see Note 7)
td(RLCL) = Max
tRAC
70
80
ns
ta(G)
Access time of 0 from TRG low (see Note 7)
tOEA
20
20
ns
CL = 30 pF
tSCA
20
25
ns
CL = 30 pF
tSEA
15
20
ns
ta(SO)
ta(SE)
Access time of SO from SC high (see Note 7)
. Access time of SO or OSF from SE low
(see Note 7)
ldis(CH)
Random output disable time from CASx high
(see Note 8)
CL = 50 pF
tOFF
0
20
0
20
ns
ldis(G)
Random output disable time from TRG high
(see Note 8)
CL = 50 pF
tOEZ
0
20
0
20
ns
tdis(SE)
Serial output or OSF disable time from SE high
(see Note 8)
CL=30pF
tSEZ
0
15
0
20
ns
NOTES; 7. SWitching times for RAM port output are measured with a load eqUivalent to 1 TTL load and 50 pF. Data out reference level:
VOH /VOL = 2 V/O.S V. Switching times for SAM port output are measured with a load equivalent to 1 TTL load and 30 pF. Serial data
out reference level: VOH I VOL = 2 V/O.8 V.
8. tdis(CH), ldiS(G), and tdis(SE) are specified when the output is no longer driven.
TEXAS ~
INSTRUMENlS
7-28
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
TMS55160
262 144 BY 16·BIT
MULTIPORT VIDEO RAM
SMVS160B-AUGUST 1992-REVISED JANUARY 1993
timing requirements over recommended ranges of supply voltage and operating free-air
temperature t
ALT.
TMS55160-70
SYMBOL
MIN
MAX
TMS55160-80
MIN
MAX
UNIT
te(rd)
Read cycle time (see Note 9)
tRC
130
150
te(W)
Write cycle time
twc
130
150
ns
te(rdW)
Read-modify-write cycle time
tRMW
170
195
ns
te(P)
Page-mode read, write cycle time
te(RDWP)
Page-mode read-modify-write cycle time
te(TRD)
Transfer read cycle time
te(SC)
ns
tpc
45
50
ns
tpRMW
85
90
ns
tRC
130
150
ns
Serial clock cycle time (see Note 9)
tscc
22
30
ns
tw(CH)
Pulse duration, CASx high
tCPN
10
10
tw(CL)
Pulse duration, CASx low (see Note 10)
tCAS
20
tw(RH)
Pulse duration, RAS high
tRP
50
tw(RL)
Pulse duration, RAS low (see Note 11)
tRAS
70
tw(WL)
Pulse duration, WE low
twP
10
15
ns
tw(TRG)
Pulse duration, TRG low
20
20
ns
tw(SCH)
Pulse duration, SC high (see Note 9)
tsc
5
10
ns
tw(SCL)
Pulse duration, SC low (see Note 9)
tscp
5
10
ns
tw(GH)
Pulse duration, TRG high
ITp
20
20
tw(RL)P
Pulse duration, RAS low (page mode)
tRASP
70
tsu(CA)
Setup time, column address before CASx low
tASC
0
0
ns
tsu(SFC)
Setup time, DSF before CASx low
tFSC
0
0
ns
tsu(RA)
Setup time, row address before RAS low
tASR
0
0
ns
tsu(WMR)
Setup time, WE before RAS low
tWSR
0
0
ns
tsu(DOR)
Setup time, DO before RAS low
tMS
0
0
ns
tsu(TRG)
Setup time, TRG high before RAS low
ITHS
0
0
ns
tsu(SE)
Setup time, SE high before RAS low
tSER
0
0
ns
tsu(SFR)
Setup time, DSF low before RAS low
tFSR
0
0
ns
ns
10000
20
ns
10000
60
10000
100000
80
80
ns
ns
10000
ns
ns
100000
ns
tsu(DCL)
Setup time, data before CASx low
tDSC
0
0
tsu(DWL)
Setup time, data before WE low
tDSW
0
0
ns
tsu(rd)
Setup time, read command WE high before CASx low
tRCS
0
0
ns
tsu(WCL)
Setup time, early write command, WE low before CASx low
twcs
0
0
ns
tsu(WCH)
Write setup time, WE low before CASx high
tCWL
15
20
ns
tsu(WRH)
Write setup time, WE low before RAS high with
TRG=WE=low
tRWL
15
20
ns
th(CLCA)
Hold time, column address after CASx low
tCAH
10
15
ns
th(SFC)
Hold time, DSF after CASx low
tCFH
10
15
ns
Continued next page.
t Timing measurements are referenced to VIL max and VIH min.
NOTES: 9. All cycle times assume tt = 3 ns.
10. In a read-modify-write cycle, Id(CLWL) and tsu(WCH) must be observed. Depending on the user's transition times, this may require
additional CASx low time [tw(CL)j.
t 1. In a read-modify-write cycle, td(RLWL) and tsu(WRH) must be observed. Depending on the user's transition times, this may require
additional RAS low time [tw(RL)j.
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
7-29
TMS55160
262 144 BY 16·BIT
MULTIPaRT VIDEO RAM
SMVS160B-AUGUST 1992-REVISED JANUARY 1993
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (continued)t
ALT.
SYMBOL
TMS55160-70
MIN
MAX
TMS55160-S0
MIN
MAX
UNIT
th(RA)
Hold time, row address after RAS low
tRAH
10
10
ns
th(TRG)
Hold time, TRG after RAS low
ITHH
10
15
ns
th(RWM)
Hold time, write mask, transfer enable after RAS low
tRWH
10
10
ns
th(RDO)
Hold time, DO after RAS low (write mask operation)
tMH
10
10
ns
th(SFR)
Hold time, DSF after RAS low
tRFH
10
10
ns
th(RLCA)
Hold time, column-address after RAS low (see Note 12)
tAR
30
35
ns
th(CLD)
Hold time, data after CASx low
tDH
15
15
ns
th(RLD)
hold time, data after RAS low (see Note 12)
tDHR
35
35
ns
15
ns
th{WLD)
Hold time, data after WE low
tDH
15
th(CHrd)
Hold time, read, WE low after CASx high (see Note 13)
tRCH
0
0
ns
th(RHrd)
Hold time, read, WE high after RAS high (see Note 13)
tRRH
0
0
ns
th{CLVv'l
Hold time, write, WE low after CASx low
twCH
15
15
ns
th(RLW)
Hold time, write, WE low after RAS low (see Note 12)
twCR
35
35
ns
th(WLG)
Hold time, TRG high after WE low (see Note 14)
tOEH
10
10
ns
th(SHSO)
Hold time, SO after SC high
tSOH
5
5
ns
th(RSF)
Hold time, DSF after RAS low
tFHR
30
35
ns
Id(RLCH)
Delay time, RAS low to CASx high
tcSH
70
SO
ns
Id(CHRL)
Delay time, CASx high to RAS low
tCRP
0
0
ns
Id(CLRH)
Delay time, CASx low to RAS high
tRSH
20
20
ns
Id(CLWL)
Delay time, CASx low to WE low (see Notes 15 and 16)
tCWD
45
td(RLCL)
Delay time, RAS low to CASx low (see Note 17)
tRCD
20
Id(CARH)
Delay time, column address to RAS high
tRAL
35
Id(CACH)
Delay time, column address to CASx high
tCAL
Id(RLWL)
Delay time, RAS low to WE low (see Note 15)
tRWD
td(CAWL)
Delay time, column address to WE low (see Note 15)
Id(RLCH)
45
50
20
ns
60
ns
40
ns
35
40
ns
95
105
ns
tAWD
60
65
ns
Delay time, RAS low to CASx high (see Note IS)
tCHR
10
15
ns
td(CLRL)
Delay time, CASx low to RAS low (see Note 1S)
tcSR
0
10
ns
Id(RHCL)
Delay time, RAS high to CASx low (see Note 18)
tRPC
0
0
.tlS
tdJCLGH)
Delay time, CASx low to TRG high for DRAM read cycles
20
20
ns
td(GHD)
Delay time, TRG high before data applied at DO
tOED
15
15
ns
Id(RLTH)
Delay time, RAS low to TRG high
(real-time reload read transfer cycle only)
tRTH
55
60
ns
Id(RLSH)
Delay time, RAS low to first SC high after TRG high (see Note 19)
tRSD
70
Id(RLCA)
Delay time, RAS low to column address
tRAD
15
Id(GLRH)
Delay time, TRG low to RAS high
tROH
15
Continued next page.
t Timing measurements are referenced to VIL max and VIH min.
NOTES: 12. The minimum value is measured when td(RLCL) is set to td(RLCL) min as a reference.
13. Either th(RHrd) or t(CHrd) must be satisfied for a read cycle.
14. Output-enable-controlled write. Output remains in the high-impedance state for the entire cycle.
15. Read-modify-write operation only.
16. TRG must disable the output buffers prior to applying data to the DO pins.
17. The maximum value is specified only to assure RAS access time.
18. C/iS-before-RAS refresh operation only.
19. Early-load read transfer cycle only.
TEXAS ~
INSfRUMENTS
7-30
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
80
35
15
15
ns
40
ns
ns
TMS55160
262 144 BY 16-BIT
MULTIPORT VIDEO RAM
SMVS160B-AUGUST 1992-REVISED JANUARY 1993
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (concluded)t
ALT.
SYMBOL
TM S55160-70
MIN
MAX
TMS55160-80
MIN
UNIT
MAX
Id(CLSH)
Delay time, CASx low to first SC high after TRG high (see Note 21)
tCSD
20
25
ns
Id(SCTR)
Delay time, SC high to TRG high (see Notes 20 and 21)
ITSL
5
5
ns
Id(THRH)
Delay time, TRG high to RAS high (see Notes 20 and 23)
ITRD
-10
-10
ns
Id(THRL)
Delay time, TRG high to RAS low (see Note 22)
ITRP
tw(RH)
tw(RH)
ns
Id(THSC)
Delay time, TRG high to SC high (see Note 20)
ITSD
10
15
ns
Id(RHMS) .
Delay time, RAS high to last (most significant) rising edge of SC before boundary switch during split read transfer cycles
20
20
ns
Id(CLTH)
Delay time, CASx low to TRG high in real-time transfer read cycles
tCTH
5
5
ns
Id(CASH)
Delay time, column address to first SC in early load read transfer
cycles
tASD
25
30
ns
Id(CAGH)
Delay time, column address to TRG high in real-time transfer read
cycles
tATH
10
10
ns
Id(DCL)
Delay time, data to CASx low
tDZC
0
0
ns
Id(DGL)
Delay time, data to TRG low
tDZO
0
0
ns
Id(MSRL)
Delay time, last (most significant) rising edge of SC to RAS low before boundary switch during split read transfer cycles
20
20
ns
Id(SCOSF)
Delay time, last (127 or 255) rising edge of SC to OSF switching at
the boundary during split read transfer cycles (see Note 24)
tSOD
25
30
ns
Id(CLOSF)
Delay time, CASx low to OSF switching in transfer read or write
cycles (see Note 24)
tCOD
30
35
ns
td(GHOSF)
Delay time, TRG high to OSF switching in transfer read or write
cycles (see Note 24)
ITOD
25
30
ns
Id(RLOSF)
Delay time, RAS low to OSF switching in transfer read or write cycles
(see Note 24)
tROD
70
75
ns
trf(MA)
Refresh time interval, memory
tREF
a
ms
tt
Transition time
50
ns
IT
8
3
50
3
t Timing measurements are referenced to VIL max and VIH min.
NOTES: 20.
21.
22.
23.
24.
Real-time reload read transfer cycle only.
Early-load read transfer cycle only.
Memory to register (read) transfer cycles only.
Late-load read transfer cycle only.
Switching times for OSF output are measured with a load equivalent to 1 TTL load and 30 pF and output reference level is
VOH I VOL ~ 2 V/o.av.
TEXAS ~
INsrRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
7-31
TMS55160
262 144 BY 16·BIT
MULTIPaRT VIDEO RAM
SMVS160B--AUGUST 1992-REVISED JANUARY 1993
PARAMETER MEASUREMENT INFORMATION
~
,
~
,
10lIl
:1'+-
I.,"'"
tcI(RLCA) ~
~
th(RA)
tsu(RA)
:+-
~ tcI(CHRL)
W :I
CASx
I
I
10lIl
1
~ ~
I
,
I
1
'
I
I
J+-- tcI(CLRH)'~
1
i ~ tcI(RLCL) - . l
-+!
,
1
: V:J+-
I
~
~
~
~I
tcI(RLCH)
----.t{ ~
tt
~~
~~4
~
I
I
I
1 1 tsu(CA)
T\~
tw(CL)
0
1
1''----
-+i
1
td(CHRL) - - . :
1
r( -1:-+-:- - - - -......7 \ "
, i~
~IOIII I 1
td(CARH)
I
1 ,
th(RLCA)
1 1 1
1 I 10lIl
--+I
~
-JI':
m
tw(RH)
iOIIIt
1 II
~ 1
10lIl I I
~I
I
1
I
th(CLCA)
1 1
1 1
1 1
I
1
1 1
"---,
tw(CH)
---I~~l
-~:7"m'~
DSF
ts
'~~~~
TRG'!fil1:
, _
~tw(T~G)~1
X
:~
I'II~
1 tsu(rd) ~ 1
I,. -to! II+-- th(RHrd)
~I :
';'OH'" i" : ~i
Figure 22. Read Cycle Timing
TEXAS
~
INSTRUMENTS
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PARAMETER MEASUREMENT INFORMATION
I..
tw(RL)
N
RAS
~I
tc(W)
_ _--.;1 104
.1
I
1
I I...
I
~I 04-
~
t d(CLRH)
CASx
~
th(RA)
I
t+- Id(RLCL) ....1
i1
td(CHRL)
6~
~
Id(RLCA)' 1... 1
1
AO-A8
~Humn
I I
I
td(CARH)
--.l 104+ tsu(SFC)
-+I Jo4t tsu(SFR) I I I
I I I+th(SFRl
th(RSF)
tl r- :::..
1
1 .
!'--
I 1 I
1
I I+j-- tw(CH) ---+I
tsu(CA)
I
..
Vi :
~ th(CLCA)
tBU~~~)1.,. 1 I
~ Io4-tt
~I ~ td(CHRL) --+I
tw(CL)
N-
I :
I ~th(RLCA)
~ jo4- --.l ~
1
·1
I J.,.-- t
+I
I ...•..1 1 w(RH) 1
td(RLCH)
I""...
tt-pj 1-
I
1
L
.0
-+I
I
1
~I
I
I
I
I
I
I
.:~
~II~II
I
-II-!I
~ 1+ th(TRG) I
I I
tBu(TRG) -.! Jo4t I
I I
VwYQ
I
I
I I
I I
t~(RHrd)
td( I LGH)
I
~
I+- talpA)
*- ta(C)
-+i
~I ~ ta(G) +---+i
ta(R);
I
i
.
I I~
td(GLRH) II
~I I
I I_
I
I
I 1 - tw(TRG) ~II .r---+---I
I
I I
I
I
tw(TRG)
I
~I
tdls(CH)
-+I ~
~ th(CHrd) ~
I
I
I I
i
i
i
i+-+I I I+-I
i~
I
I
< v~~~ >
II
II
I
ta(G) ~
i
~ ta(CA) t ~ -+i
ta(CP) t
~I
~ tdls(G)
1<
~I
~I
:
-+l
tsu(WCH)
I+-
I4j--
tw(WL)
I
~I
..
tsu(WRH)
A00§000§
th(CLD) t --+I
th(WLD) t - . I
j.- th(RDQ) -.: I+-*- tsu(DCL) t
,.
~ "(RW)
2
tsu('N,CH)
I
~!!
~
-+l14r: ~
=x::'
I
I
I
I
(see Note A)
1
~
3~
__
t Referenced to the first WE falling edge or the falling edge of CASx, whichever occures later.
NOTE A: To assure page-mode cycle time, TRG must remain high throughout the entire page-mode operation if the late write feature is used.
If the early write cycle timing is used, the state of TRG is a don't care after the minimum period th(TRG) from the falling edge of RAS.
Figure 35. Enhanced Page-Mode Block Write Cycle Timing
Table 12. Block Write Cycle State Table
STATE
CYCLE
1
2
3
Block write operation (non-masked)
H
Don't care
Column mask
Block write operation with non-persistent write-per-bit
L
Write mask
Column mask
Block write operation with persistent write-per-bit
L
Don't care
Column mask
Write mask data 0: I/O write disable
1: I/O write enable
Column mask data DOi - DOi+30: column write disable
(i =0, 4, 8, 12)
1: column write enable
Example:
DOO - column
DOl - column
D02 - column
D03 - column
0 (address Al =0, Ao =0)
1 (address Al = 0, Ao = 1)
2 (address Al =1, Ao =0)
3 (address Al = 1, Ao = 1)
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PARAMETER MEASUREMENT INFORMATION
DQ - - - - - - - - - - - - - HI-Z - - - - - - - - - - - - - - - -
Figure 36. RAS-Only Refresh Timing
TEXAS ~
INSI'RUMENTS
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MULTIPORT VIDEO RAM
SMVS160B-AUGUST 1992-REVISED JANUARY 1993
PARAMETER MEASUREMENT INFORMATION
I'"
10IIII-- tw(RH) ~
N
iT
_ _--J
I...
I
Id(CLRL)
CASx
tc(rd) --------~~I
1041
...1 - - - - - twIRL) ----l~~1 1
~I
td(RHCL)
1
1
~I
I'"
y~----
11
:+-
::
~_~~t":!Il""""'""'\~
td(RLCH)
~
V
~
-
A D - A S .
-~··:r·~
mG
22222§2§22§22~~272HK*z~
tsu(WMR)
I...
WE~
DQ
~I I'"
~I
th(RWM)
-------------- HI-Z---------------Figure 37. CAS-Before-RAS Refresh
Table 13. CBR Cycle State Table
STATE
CYCLE
1
CAS-before-RAS refrash with option raset
0
CAS-bafora-RAS rafresh with no reset
1
TEXAS
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MULTIPaRT VIDEO RAM
SMVS160B-AUGUST 1992-REVISED JANUARY 1993
PARAMETER MEASUREMENT INFORMATION
~ Memory Read Cycle
I
~L
~..,(rd)
tw(RH)
I
I.
i) II.~
-+I
1 I
W IIN.j I
lcI(CHRL)
~
I
CAsxl
lcI(RLCA)
I
I
I
I}
th(RA)
--.J
I
I
I
.1
.1
\.
~\f ~y
td(CARH)
r~
I.
I
td(RLCH)
tw(CL)
~I
-~Ii;r--
(/~i
I
I
I
th(CLCA)
I
tsu(CA)
W
~I
I ~ I !~ I I
r.+
I
.1
I
tw(RH) ~ tc(rd)
I
I
1111"-1
1--'...u...I I I I I
1T""'l I I I
I I It.! I/+-
I 1-+1 ~
I
~~ tc(rd)
)1
~T
RAS
i+-- Refresh Cycle --+I
i+-- Refresh Cycle --.I
-.!
I 1I 1
I III
tsu(RA) I I I
I
I
I
-~l2H~~
I I
os,
WE
I I -+11 I I td(G,LRH)
~ tsu(TRG)
I
I~I ta(~)
I
I
I
I I I
I ~ ~I .th(TRG)
XI/" I ' ! I I I
Y/
I
I I I
I
I
I
I
tsu(RO) ~
I
I
(see Note A)
i'"
I
I
I
tdls(G) -.I I
I I I
/rl
.
I I
I I
I I
r.-
X
((
II
~""*- ~*gXiaX{~~:~
::
I
~
r.- ta(R) +l
OQ
I
th(RHrd)
222~~222222§2JH\i*~~
-+l
TRG
I I I I. ~I
<
ta(C)
tdls(CH)
Valid Output
oata~:
-.!
l+-
r
NOTE A: CAS-before-RAS refresh (option reset) mode will end persistent write-per-bit mode. Hidden refresh will also end the persistent
write-per-bit mode regardless of the state of DSF at RAS.
Figure 38. Hidden Refresh Cycle Timing
TEXAS
~
INSTRUMENTS
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MULTIPaRT VIDEO RAM
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PARAMETER MEASUREMENT INFORMATION
AD-AS
DSF
DO
se
SO
OSF
H
t Early-load operation is defined as th(TRG) min < th(TRG) < td(RLTH) min.
NOTES: A. Random mode (DQ outputs) remain in the high-impedance state for the entire memory to data register transfer cycle. The memory
to data register transfer cycle is used to load the data registers in parallel from the memory array. The 256 locations in each data
register are written into from the 256 corresponding columns of the selected row.
B. Once data is transferred into the data registers, the SAM is in the serial read mode (i.e., the SQ is enabled), thus allowing data to
be shifted out of the registers. Also, the first bit to read from the data register after TRG has gone high must be activated by a positive
transition of SC.
C. AO-A7: Register tap point, AS: which half of the transferred row.
Figure 39. Read Transfer Timing, Early Load Operationst
TEXAS ~
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MULTIPaRT VIDEO RAM
SMVSl60B-AUGUST 1992-REVISED JANUARY 1993
PARAMETER MEASUREMENT INFORMATION
I"
----..1'. \
td(CHRL)
~I
I
:
I
j4- tw(CL)
: I
N
II
I j4---- Id(RLCA) ~ i 1
~I
I ~th(RLCA) II I
tsu(RA) -l+---+I I.
-..I 14-1 t
1
I 1!4- th(RA) -+1- r] I..SU(C~)
1
I
I
~
AO-A8
:
~ow
tSU(SFR)ii
tau(TRG)
t
td(CLT,H)
td(CAGH)
:~Id(RLTH)
:
~ ~I
~(WMR)r
~
I
I
I
I
__
I
I
Y
:I
I
I
I
,
th(CLCA)
~
~RH0X~
I I
~
H
~i~
:..
~ I
I
I
I
~T~f~~nt~~~~~*2~gj*~~~~
~::
OSF
.
y~tW(RH)~\""'--
td(RL~H)
-Jo,4...-----+l.I 14
§f
~I
tc(TRO)
I I"
twIRL)
I ~td(RLCL)~
~
-
14
th(RWM)
~ I..
i
~
I
1
td(THRL)
~ ~ td(THRHl
YI
1:'-
tw(GH)
~
_
--+l
.
. . .
OQ
SC
SQ
Old Osta
I
New Data
Old Data
I
04--
QSF
H
'dIGHQS~ ~I"--2- _ _Tap_Point_bit_A7__
14---Id(CLQSF)
~I
~I
----------------~--------~~~~-------------------------f - - - - - - - - td(RLQSF)
1.
< I.
1
L
t Late load operation is defined as td(THRH) < 0 ns.
.
NOTES: A. Once data is transferred into the data registers, the SAM is in the serial read mode (i.e., the SO is enabled), thus allowing data to
be shifted out ofthe registers. Also, the first billo read from the data register after TRG has gone high must be activated by a positive
transition of SC,
B. Random mode (DO outputs) remain in the high-impedance state for the entire memory to data register transfer cycle. The memory
to data register transfer cycle is used to load the data registers in parallel from the memory array. The 256 locatioris in each data
register are written into from the 256 corresponding columns of the selected row.
C. AO-A7: Register tap point, A8: which half of the transferred row.
Figure 40. Read Transfer Timing, Real·Time Reload Operation/Late Load Operationt
TEXAS ."
INsrRUMENTS
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POST OFFICE BOX 1443· HOUSTON. TEXAS 77001
TMS55160
262 144 BY 16·BIT
MULTIPORT VIDEO RAM
SMVS160B-AUGUST 1992-REVISED JANUARY 1993
PARAMETER MEASUREMENT INFORMATION
AD-AS
tsu(SFR)
-+i
~
II~g~n3RH~
1 IWwwwwwwwwww
DSF
tsu(WMR)
+i
~
~ 1..- th(RWM)
~I
1
!~H,:~m~
----......I---------- HI-Z ---+1-----------td(MSRL) --I4---l.~1
~ *' 4 - - - tc(SC)
.:
~ tw(SCL).1
td(RHMS)
1
:
I Jt-----,.
1
1
~ tc(SC) ---I~
1
. r - -.....
SC
Bit 127 or
Bit 255
SQ
Tap Point M
.1 td(SCQSF)
1
X
QSF
1
td(SCQSF) 101IIII
Bit 127 or
Bit 255
Tap
PolntN
101IIII .1
ta(SQ)
~I
X
MSB Old::
I
NewMSB
H
SE
L
((
JJ
NOTES: A. There must be a minimum of two SC clock cycles between any two split-register reload cycles, and between a transfer read cycle
and a split-register cycle.
B. AD-A6: Tap point of the given half, A7: Don't care, AS: DRAM row half.
Figure 41. Split-Register Read Transfer Timing
1ExAs
~
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TMS55160
262 144 BY 16·81T
MULTIPORT VIDEO RAM
SMVS1 60B-AUGUST 1992-REVISED JANUARY 1993
PARAMETER MEASUREMENT INFORMATION
tsu(TRG)
----'
I
TRG~
I..
1+ tw(SCH) ~
SC
tC(SC)
A \[
_ _ _ _ _..I
SQx
~
SE
tc(SC)
-----1~~I-
\{
!.
4.
1
tw(SCL)
~0
~
!IIIII{ th(SHSQ)
---~~
14
....1------1~~ th(TRG)
..
~ ta(SQ)
--.!
~~~----------------------------~
~
~
th(SHSQ)
V.lId...
tw(SCH)
~ tw(SCL)
~
~
11
~
ta(SQ)
:
th(SHSQ)
M
~ tw(SCH) +:
"'lid 0..
\~
~
~
____
ta(SQ)
:
M"',.
o.
!IIiII- ta(SE)
~~!
____________________________________________________
1
I"
QSF
ta(SE)
------~~~_ _ _ _ _ _ _ _ _ _ _~_a_lI_d_O_u_t_ _ _ _ _ _ _ _ _ _ _ ___
NOTES: A. While reading data through the serial data register, the state of TRG is a don't care as long as TRG is held high when RAS goes
low. This is to avoid the initiation of a register to memory to register data transfer operation.
B. The serial data-out cycle is used to read data out of the data registers. Before data can be read via SQ, the device must be put into
the read mode by performing a transfer read cycle.
Figure 42. Serial Read Timing
TEXAS
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INSTRUMENTS
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SMVSI60B-AUGUST 1992-REVISED JANUARY 1993
PARAMETER MEASUREMENT INFORMATION
tsu(TRG)
-
~1
"tl,..:---------------1oII,...1---I~~ th(TRG)
~~
:4
~
~
te(SC)
~ tw(SCH) ~
1+ tw(SCH) +!
SC
__
\f ..~~ 11
---J~
14
1
~
~
1
ta(SQ)
!e(SC)
\[ 'w~C~ 11 \. .__
~
1
~ ta(SQ)
I4t th(SHSQ)
~ tw(SCH) ~
~
1-
J+- ta(SE)
14
t
a(SQ)
th(SHSQ)
1
SQx
Valid Out
Valid Out
Valid Out
I
1
I
I
lOIII------*-
------~)
tdls(SE)
I
I
~~--------------
NOTES: A. While reading data through the serial data register, the state of TRG is a don't care as long as TRG is held high when RAS goes
low. This is to avoid the initiation of a register to memory to register data transfer operation.
B. The serial data-out cycle is used to read data out of the data registers. Before data can be read via SQ, the device must be put into
the read mode by performing a transfer read cycle.
Figure 43. Serial Read Timing (SE Controlled Read)
TEXAS ~
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SMVS160B-AUGUST 1992-REVISED JANUARY 1993
RAS
CASx
ADDR
OPERATING SEQUENCE INFORMATION
,
I~-+--~\
,-JJ'j
1
\
r,~'r--
~~'r-~....-----I-~~~
~~
RowTap1
(Low)
Row Tap1
1
(High)
1
RowTap2
(Low)
1
1
RowTap2
(High)
TRG
'--I
\.J
'I~~r----
DSF
---_r----I/\
')~~r---1
1
1
1
1
1
I
I
~~lQr~1
1271 (High)
r
!J
--------~----~r---------------~)r__T
255
)
(Low)
127
r
~
1
1
1
1
1
,
1
1
1
1
--------------~~----~~~~lQ1271 (High)
(Low)
--~-4---~\r{
r
I
255
(Low)
127
)~r-r
1
I
1
I
1
I
----------------~----------~~~~lQ(Low)
1271 (High)
--~~~----~\~
Split-Register to the
High Half of the
Data Register
1
I
1
1
255
(Low)
127
\~r-r
Split-Register to the
Low Half of the
Data Register
1
1
I
Split-Register to the
High Half of the
Data Register
NOTES: A. In order to achieve proper split-register operation, a normal read transfer should be performed before the first split-register transfer
cycle. This is necessary to initialize the data register and the starting tap location. First serial access can then begin either after the
normal read transfer cycle (CASE I), during the first split-register transfer cycle (CASE II), or even after the first split-register transfer
cycle (CASE III). There is no minimum requirement of SC clock between the normal read transfer cycle and the first split-register
cycle.
B. A split register transfer into the inactive half is not allowed until Id(MSRL) is met. Id'11
~
-, I
M++t-I
D06 0 ] ]
D04
~
I I I
I l..J
r--,
One Row of 0-511
n,~b
I
I
r-i-Jf+f.,
6
7 -t++-ho.
I II I
I
..J
I..J
..J
r--,
..1_,
-, I
o
r+++t-I
I
I
I I I
I I ..J
I
1
2
3+++-I-QIL
11
7
\ 0
1 2 3
4 5 6 7
8 9 10 11
12 13 14 15 I
~------------------------,V~----------------------~
Color Register
Figure 6. Block Write With Masks
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MULTIPaRT VIDEO RAM
SMVS165B-AUGUST1992-REVISED JANUARY 1993
Every 4 columns make a block, which makes 128 blocks along one row. Block 0 comprises columns 0-3, block
1 comprises columns 4-7, block 2 comprises columns 8-11, etc .., as below (Figure 7).
Block 0
One Row of 0 - 511
Block 1 ...................... Block
127
11'-_____,
r---~II
II
I
V
I
I
6
7 ........................... . 511
4
5
'--------------,v~------------~I
0
2
3
Columns
Figure 7. Block Or.ganization
During block write cycles, only the seven most significant column addresses (A2-A8) are latched on the falling
edge of CAS to decode one of the 128 blocks. Address bits AO-A 1 are ignored. (Each one-megabit quadrant
has the same block selected.)
A block write cycle is entered in a manner similar to a DRAM write cycle except with DSF held high on the falling
edge of CAS. As in a DRAM write operation, WEL and WEU enable the corresponding lower and upper DRAM
DQ bytes to be written, respectively. The column mask data is input via the DQs and is latched on either the first
WExfalling edge orthe falling edge of CAS, whichever occurs later. The 16-bit color data register must be loaded
prior to performing a block write, as described below. Refer to the write-per-bit section for details on use of the
write mask capability, allowing additional performance options.
Example of block write:
block write column address
=
110000000 (AO-A8 from left to right)
bit 15
bit 0
color data register
write mask
column mask
1011
1110
1111
1st
Quad
1011
1111
0000
2nd
Quad
1100
1111
0111
3rd
Quad
0111
1011
1010
4th
Quad
Column address bits AO and Ai are ignored. Block 0 (columns 0-3) is selected for each one-megabit quadrant.
The first quadrant has DQO-DQ2 written with bits 0-2 from the color data register (1 01 ) to all four columns of
Block O. DQ3 is not written and retains its previous data due to the write mask register bit 3 being a O.
The second quadrant ( DQ4-DQ7) has all four columns masked off due to the column mask bits 4-7 being 0,
so that no data is written.
The third quadrant ( DQ8-DQ11 ) has its four DQs written with bits 8-11 from the color data register (1100) to
columns 1-3 of its Block O. Column 0 is not written and retains its previous data on all four DQs due to the column
mask register bit 8 being O.
TEXAS ~
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The fourth quadrant ( 0012-0015) has 0012, 0014, and 0015 written with bits 12, 14, and 15 from the color
data register to column 0 and column 2 of its Block O. 0013 retains its previous data on all columns, due to
the write mask. Columns 1 and 3 retain their previous data on all OOs due to the column mask. If the previous
data for the quadrant was all Os, the fourth quadrant would contain the following data pattern after the block write
operation shown in the previous example.
001511 1 0 11 1 0
001411 1 0 11 1 0
00131 0
I
I
I 0 I0 I 0 I
DQ"W
Columns 0
1
2
3
Figure 8. Example of Fourth Quandrant after Bock Write
load color register
The load color register cycle is performed using normal ORAM write cycle timing except that OSF is held high
on the falling edges of RAS and CAS. The color register is loaded from pins 000--0015, which are latched on
either the firstWExfalling edge or the falling edge of CAS, whichever occurs later. If only one of the write enables
is low, only the corresponding byte of the color register is loaded. When the color register is loaded, it retains
data until power is lost or until another load color register cycle is performed. (Figure 9, Figure 10).
I
I
I
i'
I
I
I
I
Load Color Register Cycle
/
I
3
I
I
I
/I
/
\
2
Block Write Cycle
(Load and Use Write Mask)
ti"\
I
Ij\
\
I
I
I
Block Write Cycle
(No Write Mask)
\
n
2
TRG ~~~----------------~~~------------------~~~------------------~
OOG-:;:~;;:~~~~~=
Legend:
2. Refresh Address
2.
Row Address
2. Block Address (A2-A8)
2. Color Register Data
2. DO Mask Data: DOG-D015 are latched on RAS falling edge.
2. Column Mask Data: DOi-DOi+3 (i=0,4,8, 12) are latched on either the first WEx falling edge orthe falling edge of CAS, whichever occurs
later.
~ = Don't Care
Figure 9. Example of Block Writes With Write Masks
TEXAS
~
INsmuMENTS
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7-73
TMS55165
262 144 BY 16·BIT
MULTIPORT VIDEO RAM
SMVS165B-AUGUST 1992-REVISED ~ANUARY 1993
I
I
I
RAS
CAS
Load Write Mask Register Cycle
i'
I
I
I
I
IT"'
I
I
\
I
I
I
Load Color Register
IT"'
I
/I
I
\
I
I
I
Persistent Block Write Cycle
(Use loaded Write Mask)
AO-AS
n
\
2
WEx
TRG
DSF
DQO-DQ1S
S
4
6
Legend:
1.
2.
3.
4.
5.
6.
Refresh Address
Row Address
Block Address (A2-A8)
Color Register Data
Write mask data: DQO-DQ15 are latched on CAS falling edge.
Column mask data: DQi-DQi+3 (i=O,4,8, 12) are latched on either the first CASx falling edge or the falling edge of WE, whichever occurs
later
Don't Care
fM§!:mm::m$-
Figure 10. Example of a Persistent Block Write
DRAM to SAM transfer operation
During the DRAM to SAM transfer operation, one half of a row (256 columns) in the DRAM array is selected
to be transferred to the 256-bit serial data register. The transfer operation is invoked by bringing TRG low and
holding WEL and WEU high on the falling edge of RAS. The state of DSF, which is latched on the falling edge
of RAS, determines whether the read transfer operation or the split register read transfer operation will be
performed.
Table 4. SAM Function Table
CAS
FALL
RAS FALL
DQO-DQ1St
ADDRESS
CAS
TRG
WEx*
DSF
DSF
RAS
CAS
RAS
CAS
WEL
WEU
MNE
CODE
Read transfer
1
0
1
0
X
Row
Addr
Tap
Point
X
X
RT
Split-register read transfer
1
0
1
1
X
Row
Addr
Tap
Point
X
X
SRT
FUNCTION
t DQO-DQ15 are latched on either the first WEx falling edge or the falling edge of CAS, whichever occurs later.
* Logic 0 is selected when either or both WEL and WEU are low.
X: = Don't care.
TEXAS
~
INsrRUMENTS
7-74
POST OFFICE BOX 1443' HOUSTON. TEXAS 77001
TMS55165
262144 BY 16·BIT
MULTIPaRT VIDEO RAM
SMVS165B-AUGUST 1992-REVISEO JANUARY 1993
read transfer
A read transfer operation loads data from a selected half of a row in the DRAM into the SAM. TRG is brought
low and latched at the falling edge of RAS. Nine row address bits (AD-AS) are also latched at the falling edge
of RAS to select one ofthe 512 rows available for the transfer. The nine column address bits (AD-AS) are latched
at the falling edge of CAS, where address bit AS selects which half of the row will be transferred. Address bits
AD-A? select one of the SAM's 256 available tap points from which the serial data will be read out (Figure 11).
o
AS=O
255 256
AS=l
511
512 x 512
Memory Array
256 Bit
Data Register
o
255
Figure 11. Read Transfer
A read transfer can be performed in three ways: early-load read transfer, real-time or mid-line-load read transfer,
and late-load read transfer. Each of these offers the flexibility of controlling the TRG trailing edge in the read
transfer cycle (Figure 12).
I
Early Load Read Transfer
I
RAS
f"\
fT\
CAS
I
I
I
I
/1
I
\
Real-Time Reload Read
Transfer
I
fT\
I
/1
I
\
Late-Load Read Transfer
/
I
I
I
'-../
AD-AS
I
TRG
f'\..J
I
Point
I
I
I
I
Point
\
/
I \
I
Point
n
I
I
WEXp~~~
SC
I
I
I
I
I
I
Figure 12. Examples of Read Transfer
TEXAS ~
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7-75
TMS55165
262 144 BY 16·BIT
MULTIPaRT VIDEO RAM
SMVS165B-AUGUST 1992-REVISED JANUARY 1993
split-register read transfer
In the split-register read transfer operation, the serial data register is split into halves. The low half contains bits
0-127, and the high half contains bits 128-255. While one half is being read out of the SAM port, the other half
can be loaded from the memory array.
'
o
511
512 x 512
Memory Array
256 Bit
Data Register
o
255
Figure 13. Split Register Read Transfer
To invoke a split-register read transfer cycle, DSF is brought high, TRG is brought low, and both are latched at
the falling edge of RAS. Nine row address bits (AO-AS) are also latched at the falling edge of RAS to select one
of the 512 rows available for the transfer. Eight of the nine column address bits (AO-A6 and AS) are latched at
the falling edge of CAS. Column address bit AS selects which half of the row to be transferred. Column address
bits AO-A6 will select one of the 127 tap points in the specified halfofthe SAM. Column address bit A7 is ignored
and the split-register transfer is internally controlled to select the inactive register half.
AS=O
~
511
0
DRAM
SAM
AS= 1
A8 = 1
~
~
A7=Ot
0
511
A8=O
~
A7=1t 511
0
o A7=Ot
511
m
m m m
'~
'~
'W
A
'&ri
B
C
sa
B
C
E
0
sa
sa
0
sa
t A7 shown is internally controlled
Figure 14. Example of Split-Register Read Transfer Operation
A read transfer (non split-register) must precede the first split-register read transfer to ensure proper operation.
After the read transfer cycle, the first split-register read transfer can follow immediately without any minimum
SC clock requirement. However, there is a minimum requirement of a rising edge of SC between successive
split-register read transfer cycles.
TEXAS
~
INsrRUMENTS
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TMS55165
262 144 BY 16·BIT
MULTIPaRT VIDEO RAM
SMVS165B-AUGUST 1992-REVISED JANUARY 1993
QSF indicates which half of the register is being accessed during serial access operation. When QSF is low,
the serial address pointer is accessing the lower (least significant) 128 bits of SAM. When QSF is high, the
pointer is accessing the higher (most significant) 128 bits of SAM. QSF changes state upon completing a read
transfer cycle. The tap point loaded during the current transfer cycle determines the state of QSF. QSF also
changes state when a boundary between two register halves is reached.
Split Register
Read Transfer
Read Transfer
With Tap Point N
I
\
RAS
I
\
CAS
1
1
\
TRG
I
1
DSF
SC
I
\
Ii
I
1
1
I
I
1
1
1
1
1
I
\
I
\
/\
I
' - - td(CLQSF)
14
QSF
~
Point N
-+J
~
td(GHQSF)
Figure 15. Example of a Split-Register Read Transfer After a Read Transfer
Split Register
Read Transfer
With Tap Point N
\
RAS
Split Register
Read Transfer
1
1
1
~
\
CAS
TRG~
1
\1
1
I
1
td(RHMS)
SC
;h
I
DSF~
I
1
1
I
\
I
I
I
I
1\
I(
-I.-----.i
14
.1
ld(MSRL)
I I
_----1.0+-1- td(SCaSF)
QSF
=================================><~:______________________
Figure 16. Example of Successive Split-Register Read Transfers
TEXAS
~
INSTRUMENTS
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7-77
TMS55165
262 144 BY 16·BIT
MULTIPaRT VIDEO RAM
SMVS165B-AUGUST1992-REVISED JANUARY 1993
serial access operation
The serial read operation can be performed through the SAM port simultaneously and asynchronously with
DRAM operations except during read transfer operations.
Serial data can be read from the SAM by clocking SC starting at the tap point loaded by the preceding transfer
cycle, then proceeding sequentially to the most significant bit (bit 255) and then wrapping around to the least
significant bit (bit 0) (Figure 17).
Tap
1---+ ••• 25412551
I
Figure 17. Serial Pointer Direction for Serial Read
For split-register operation, serial data can be read out from the active half of SAM by clocking SC starting at
the tap point loaded by the preceding split-register transfer cycle. The serial pointer will then proceed
sequentially to the most significant bit of the half, bit 127 or bit 255. If there is a split-register read transfer to the
inactive half during this period, the serial pOinter will point next to the tap point location loaded by that split
register transfer (Figure 18).
Figure 18. Serial Pointer for Split-Register Read - Case I
If there is no split-register read transfer to the inactive half during this period, the serial pointer will point next
to bit 128 or bit 0 respectively (Figure 19).
Figure 19. Serial Pointer for Split-Register Read - Case"
power up
To achieve proper device operation, an initial pause of 200 (.1s is required after power-up, followed by a minimum
of eight RAS cycles or eight CAS-before-RAS cycles to initialize the DRAM port. A read transfer cycle and two
SC cycles are required to initialize the SAM port.
After initialization, the internal state of the TMS55165 is as follows:
State After Initialization
OSF
Write mode
Write mask register
Color reg ister
Serial register tap point
SAM port
Defined by the transfer cycle during initialization
Non-persistent mode
Undefined
Undefined
Defined by the transfer cycle during initialization
Output mode
TEXAS ~
INSTRUMENTS
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TMS55165
262 144 BY 16-BIT
MULTIPORT VIDEO RAM
SMVS165B-AUGUST 1992-REVISED JANUARY 1993
absolute maximum ratings over operating free-air temperature t
Supply voltage range on any pin except DQ and SQ (see Note 1) ......................... - 1 V to 7 V
Voltage range on DQ and SQ (see Note 1) ............................................. - 1 V to 7 V
Voltage range on Vee (see Note 1) ................................................... -1 V to 7 V
Short-circuit output current ................................................................ 50 mA
Power dissipation ........................................................................ 1.1 W
Operating free-air temperature range .................................................. O°C to 70°C
Storage temperature range ....................................................... - 65°C to 150°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. This is a stress rating only, and
functional operation of the device at these or any other conditions beyond those indicated in the "recommended operating conditions" section of
this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values in this data sheet are with respect to VSS.
recommended operating conditions
MIN
NOM
MAX
4.5
5
5.5
UNIT
V
VCC
Supply voltage
VSS
Supply voltage
V,H
High-level input voltage
2.4
6.5
V,L
Low-level input voltage (see Note 2)
-1
0.8
V
TA
Operating free-air temperature
0
70
'c
0
V
V
NOTE 2: The algebraic convention, where the more negative (less positive) limit IS designated as minimum, is used in thiS data sheet for logic
voltage levels only.
electrical characteristics over full ranges of recommended operating conditions
PARAMETER
TEST
CONDITIONS
SAM
PORT
TMS55165-70
TMS55165-80
MIN
MIN
MAX
MAX
UNIT
VOH
High-level output voltage
10H =-1 mA
VOL
Low-level output voltage
IOL=2 mA
0.4
0.4
V
I,
Input current (leakage)
V, = 0 to 5.8 V, VCC = 5.5 V
All other pins at 0 to VCC
±10
±10
~
10
Output leakage current (see Note 3)
VO=OtoVCC,
VCC =5.5V
±1O
±10
~
ICC1
Operating current
See Note 4
Standby
165
160
205
195
2.4
ICC1A
Operating current
!e(SC) = MIN
Active
ICC2
Standby current
All clocks = VCC
Standby
ICC2A
Standby current
tc(SC) = MIN
Active
V
2.4
5
5
50
45
ICC3
RAS-only refresh current
See Note 4
Standby
165
160
ICC3A
RAS-only refresh current
te(SC) = MIN
Active
195
185
ICC4
Page-mode current
tclP) = MIN (see Note 5)
Standby
100
95
ICC4A
Page-mode current
!e(SC) = MIN
Active
130
120
ICC5
CAS-before-RAS current
See Note 4
Standby
165
160
ICC5A
CAS-before-RAS current
!eISC) = MIN
Active
205
195
ICC6
Data transfer current
See Note 4
Standby
165
160
ICC6A
Data transfer current
tc(SC) = MIN
Active
205
195
NOTES:
mA
3. SE IS disabled for SO output leakage tests.
4. Measured with one address change while RAS = V,L; tc(rd), tc(W), tc(TRD) = MIN.
5. Measured with one address change while CAS = V,H
TEXAS ~
INsrRUMENTS
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7-79
TMS55165
262 144 BY 16-BIT
MULTIPaRT VIDEO RAM
SMVS165B-AUGUST 1992-REVISED JANUARY 1993
capacitance over recommended ranges of supply voltage and operating free-air temperature,
f = 1 MHz (see Note 6)
MIN
PARAMETER
MAX
UNIT
Ci(A)
Input capacitance, address inputs
6
pF
Ci(RC)
Input capacnance, strobe inputs
7
pF
pF
Ci(W)
Input capacitance, write enable input
7
Ci(SC)
Input capacitance, serial clock
7
pF
Ci(SE)
Input capacitance, serial enable
7
pF
Ci(DSF)
Input capacitance, special function
7
pF
Ci(TRG)
Input capacitance, transfer register input
7
pF
Co(O)
Output capacitance, SO and DO
7
pF
Co(OSF)
Output capacitance, OSF
9
pF
NOTE 6: VCC equal to 5 V
±
0.5 V and the bias on PinS under test IS 0 V.
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (see Note 7)
PARAMETER
ta(C)
Access time from CAS (see Note 7)
ta(CA)
Access time from column address (see Note 7)
ta(CP)
Access time from CAS high (see Note 7)
TMS55165-70
TMS55165-80
TEST
CONDITIONS
ALT.
SYMBOL
= Max
td(RLCL) =Max
td(RLCL) =Max
td(RLCL) = Max
tGAG
20
20
ns
tM
35
40
ns
tCPA
40
45
ns
tRAC
70
80
ns
td(RLGL)
MIN
MAX
MIN
UNIT
MAX
ta(R)
Access time from RAS (see Note 7)
ta(G)
Access time of
tOEA
20
20
ns
ta(SO)
Access time of SO from SC high (see Note 7)
CL =30 pF
tSCA
20
25
ns
ta(SE)
Access time of SO or OSF from SE low
(see Note 7)
CL =30 pF
tSEA
15
20
ns
ldis(CH)
Random output disable time from CAS high
(see Note 8)
CL = 50 pF
tOFF
0
20
0
20
ns
ldis(G)
Random output disable time from TRG high
(see Note 8)
CL = 50 pF
tOEZ
0
20
0
20
ns
tdis(SE)
Serial output or OSF disable time from SE high
(see Note 8)
CL = 30 pF
tSEZ
0
15
0
20
ns
NOTES:
a from TRG low (see Note 7)
7. SWitching times for RAM port output are measured with a load eqUivalent to 1 TTL load and 50 pF. Data out reference level:
VOH /VOL = 2 V/0.8 V. Switching times for SAM port output are measured with a load equivalent to 1 TTL load and 30 pF. Serial data
out reference level: VOH IVOL = 2 V/0.8 V.
8. tdis(CH), tdiS(G), and ldis(SE) are specified when the output is no longer driven.
TEXAS
~
INSTRUMENTS
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POST OFFICE BOX 1443· HOUSTON. TEXAS 77001
TMS55165
262144 BY 16·BIT
MULTIPaRT VIDEO RAM
SMVSI65B-AUGUST 1992-REVISED JANUARY 1993
timing requirements over recommended ranges of supply voltage and operating free-air
temperature t
TMS55165-70
MIN
MAX
TMS55165-80
MIN
MAX
UNIT
Ie (rd)
Read cycle time (see Note 9)
tRC
130
150
1e(W)
Write cycle time
twc
130
150
ns
ns
le{rdW)
Read-modify-write cycle time
tRMW
170
195
ns
Ie(P)
Page-mode read, write cycle time
Ie(RDWP)
Page-mode read-modify-write cycle time
tc(TRD)
Transfer read cycle time
Ie(SC)
tpc
45
50
ns
tpRMW
85
90
ns
tRC
130
150
ns
Serial clock cycle time (see Note 9)
tscc
22
30
ns
tw[CH}
Pulse duration, CAS high
tCPN
10
10
tw(CL)
Pulse duration, CAS low (see Note 10)
tCAS
20
tw{RH)
Pulse duration, RAS high
tRP
50
twiRL)
Pulse duration, RAS low (see Note 11)
tRAS
70
tw{WL)
Pulse duration, WEx low
twp
10
15
ns
tw(TRG)
Pulse duration, TRG low
20
20
ns
10000
20
ns
10000
10000
80
ns
ns
60
10000
ns
tw(SCH)
Pulse duration, SC high (see Note 9)
tsc
5
10
ns
tw{SCL)
Pulse duration, SC low (see Note 9)
tscp
5
10
ns
tw(GH)
Pulse duration, TRG high
ITp
20
20
tY.1.RL}P
Pulse duration, RAS low (page mode)
tRASP
70
tsu(CA)
Setup time, column address before CAS low
tASC
0
0
ns
tsu(SFC)
Setup time, DSF before CAS low
tFSC
0
0
ns
tsu{RA)
Setup time, row address before RAS low
tASR
0
0
ns
tsu(WMR)
Setup time, WEx before RAS low
twSR
0
0
ns
tsu{DOR)
Setup time, DO before RAS low
tMS
0
0
ns
tsu(TRG)
Setup time, TRG high before RAS low
ITHS
0
0
ns
tsu{SE)
Setup time, SE high before RAS low
tSER
0
0
ns
tsu(SFR)
Setup time, DSF low before RAS low
tFSR
0
0
ns
tsu{DCLl
Setup time, data before CAS low
tDSC
0
0
ns
tsu(DWL)
Setup time, data before WEx low
tDSW
0
0
ns
tsu(rd)
Setup time, read command WEx high before CAS low
tRCS
0
0
ns
tsu{WCL)
Setup time, early write command, WEx low before CAS low
twcs
0
0
ns
tsulWCH)
Write setup time, WEx low before CAS high
tCWL
15
20
ns
tsu(WRH)
Write setup time, WEx low before RAS high with
TRG = WEx = low
tRWL
15
20
ns
th(CLCA)
Hold time, column address after CAS low
tCAH
10
15
ns
th(SFC)
Hold time, DSF after CAS low
tCFH
10
15
ns
100000
80
ns
100000
ns
Continued next page.
t Timing measurements are referenced to VIL max and VIH min.
NOTES: 9. All cycle times assume tt 3 ns.
10. In a read-modify-write cycle, Icl(CLWL) and tsu(WCH) must be observed. Depending on the user's transition times, this may require
additional CAS low time [tw(CL)l.
11. In a read-modify-write cycle, td(RLWL) and tsu(WRH) must be observed. Depending on the user's transition times, this may require
additional RAS low time [tw(RL)l.
=
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
7-81
TMS55165
262 144 BY 16-BIT
MULTIPaRT VIDEO RAM
SMVSI65B-AUGUST 1992-REVISED JANUARY 1993
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (continued)t
ALT.
SYMBOL
TMS55165-70
MIN
MAX
TMS55165-80
MIN
MAX
UNIT
th(RA)
Hold time, row address after RAS low
tRAH
10
10
thCTRG)
Hold time, TRG after RAS low
ITHH
10
15
ns
th(RWM)
Hold time, write mask, transfer enable after RAS low
tRWH
10
10
ns
ns
ns
th(RDO)
Hold time, DO after RAS low (write mask operation)
tMH
10
10
th(SFR)
Hold time, DSF after RAS low
tRFH
10
10
ns
th(RLCA)
Hold time, column-address after RAS low (see Note 12)
tAR
30
35
ns
ns
thlCLD)
Hold time, data after CAS low
th(RLD)
hold time, data after RAS low (see Note 12)
th{VoJLD)
Hold time, data after WEx low
th(CHrd)
tDH
15
15
tDHR
35
35
ns
tDH
15
15
ns
Hold time, read, WEx low after CAS high (see Note 13)
tRCH
0
0
ns
thlRHrd)
Hold time, read, WEx high after RAS high (see Note 13)
tRRH
0
0
ns
th(CLW)
Hold time, write, WExlow after CAS low
twCH
15
15
ns
th(RLW)
Hold time, write, WEx low after RAS low (see Note 12)
twCR
35
35
ns
th(WLG)
Hold time, TRG high after WEx low (see Note 14)
tOEH
10
10
ns
th(SHSO)
Hold time, SO after SC high
tSOH
5
5
ns
thlRSJ=l
Hold time, DSF after RAS low
tFHR
30
35
ns
1d(RLCH)
Delay time, RAS low to CAS high
tCSH
70
80
ns
1d(CHRL)
Delay time, CAS high to RAS low
tCRP
0
0
ns
1d(CLRH)
Delay time, CAS low to RAS high
tRSH
20
20
ns
1d(CLWL)
Delay time, CAS low to WEx low (see Notes 15 and 16)
tCWD
45
45
ns
td(RlCl)
Delay time, RAS low to CAS low (see Note 17)
tRCD
20
td{CARH)
Delay time, column address to RAS high
tRAL
35
40
ns
1d(CACH)
Delay time, Column address to CAS high
tCAl
35
40
ns
1d(RLWl)
Delay time, RAS low to WEx low (see Note 15)
tRWD
95
105
ns
td(CAWl)
Delay time, column address to WEx low (see Note 15)
tAWD
60
65
ns
1d(RlCH)
Delay time, RAS low to CAS high (see Note 18)
tCHR
10
15
ns
1d(CLRLl
Delay time, CAS low to RAS low (see Note 18)
tCSR
0
10
ns
tRPC
20
60
ns
0
0
ns
20
20
ns
15
15
ns
tRTH
55
60
ns
tRSD
70
80
tRAD
15
tROH
15
1d(RHCLl
Delay time, RAS high to CAS low (see Note 18)
td(ClGH)
Delay time, CAS low to TRG high for DRAM read cycles
td(GHD)
Delay time, TRG high before data applied at DO
tOED
1d(RlTH)
Delay time, RAS low to TRG high (real-time reload read transfer
cycle only)
td(RLSH)
Delay time, RAS low to first SC high ------
TMS55165
262144 BY 16·BIT
MULTIPaRT VIDEO RAM
SMVS165B-AUGUST 1992-REVISED JANUARY 1993
PARAMETER MEASUREMENT INFORMATION
~
~~
_ _---.;1 I"
N.
RAS
I I..
I
tt
~
~
twIRL)
b
N:..
Wi ri
·1
td(CLRH):
I io4- td(RLCL) ....1
~ td(CHRL)
CAS
AO-AS
i
tw(CL)
th(SFRl
~ tt
:
!\.-
I I I
1
I Io4j- tw(CH) --+I
I
I
I .1
-+I ~ tsu(SFC)
I
-.I ~ tsu(SFR)1 I I
th(RSF)
-!J
lA :
~Humn
I I I+--
I I
I 14--- tw(RH) -.I
I ,- 1 t
----'o.J
h
~I d(CHRL)----,.,
"I
I I
I 14-- th(RLCA)
th(RA) ~ ~ -.I ~ tsu(CA)
td(RLCA)' 1
.. 1
~ I ~ th(CLCA)
tsu~~1'X'X\.J.I".! I
I td(CARH)
I I
L1
yT
td(RLCH)
:.-
1
.1
-.I
Mr- :::.. •
I
I
I
I
I
DSF~::~!:~
~ I+- th(TRGl I
I I
tsu(TRG) +I ~. 1
I
Y v V Y # 1 1 ·
TRG
'illtI
I I
I I
~
tsu(WMR)
I" I I
I" I I
-+i I I
th(RWM;
~"I+
:
i_I"
.1
tsu(WCH)
tsu(WRH)
th(RLW)th(CLW)
::
~ ~ tsu(WCL)
WEx
~i!
tsu(DQR)
-+i 1..+
I
th(RDQI
I
-+I
+j I+:
~~~~
DQ~
I
~
tw(WL)
Wtsu(DCL)
I-,
I..
th(CLD)
th(RLD)
3
1
.1
---+i
.1
~
Figure 21, Early Write Cycle Timing
Table 5. Write Cycle State Table
STATE
CYCLE
1
2
3
Write operation (non-masked)
H
Don't care
Valid data
Write operation with non-persistent write-per-bit
L
Write mask
Valid data
Write operation with persistent write-per-bit
L
Don't care
Valid data
TEXAS
~
INSTRUMENTS
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262 144 BY 16·BIT
MULTIPORT VIDEO RAM
SMVS165B-AUGUST 1992--REVISED JANUARY 1993
PARAMETER MEASUREMENT INFORMATION
1c(W)
I'"
_ _--.il
!"II
~
I
!
,...
tcI(CLRH)
,
N
--+i
...!
!-.;
,
Id(CHRL)
~ II
~
11"-:-----.. . . .
,,
~
Iw(CL)
,
I~IIII::
Ih(CLCA)
, ,
I
I
I
I
I
I
I
1
~IW(CH)---.I
~~O:lumn~
Ao-A8
I
tsu(SFR)-+i
j+---
~
th(RSF). - - - . :
-.I ~ tSU(S~C)
j+:
I!IIII
·1 ttJ(sFC)
Ih
~
i
~
I"~II
II~I
SFR)
DSF
I I
I I
~
~ II
I
~tsU(rd)
i...f+
I
I...
111
I I
Isu(DQR)
.
~ ~
I -;
I
tsu(DWL)
~ th(RDQ)
1... 1
I'"
1l1li
I
I
I th(RLW)
I
I
I
1l1li
~
~
I
I
I
I
!
I
I
::
~
-.:
tSU(TRG):
I I I
I
Id(GHD)1
I _1l1li
I
-+i ~I tsu~MR)1
th(RWM~ ~
I
DQ
I
-+I
Id(RLCA)! 1l1li
.,
I
Ih(RLCA)
I 'I
~
I I sulCAl - I I - I ,
I I 1l1li
.1
Ih(RA) ~ ~
.*-
.,
,
I.,.
,~ tw(RH) -.:
,.1
i~
tcI(RLCH)
II --+i j+-+i ~ tcI(CHRL)
I I ~ tcI(RLCL)
L
Vi
7\1
: i...
~I
I
.1
twIRL)
tsu~RH) i ~I
tsu~CH) ---.I
Ih(CLW)
.1
I
.1
I
I
th~LG)
'N~'w~L)
lie
I I
+j ~
I
I
I
: . - th~LD)
~
:
I
I
I
1
.1
~~""'~~~~~~
~
--.I
I,
~I
th(RLD)
~3~
Figure 22. Late Write Cycle Timing (Output-Enable-Controlled Write)
Table 6. Write Cycle State Table
STATE
CYCLE
1
Write operation (non-masked)
Write operation with non-persistent write-per-bit
Write operation with persistent write-per-bit
H
L
L
TEXAS
~
INSTRUMENTS
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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
2
Don't care
Write mask
Don't care
3
Valid data
Valid data
Valid data
TMS55165
262 144 BY 16·BIT
MULTIPaRT VIDEO RAM
SMVS165B-AUGUST 1992-REVISED JANUARY 1993
PARAMETER MEASUREMENT INFORMATION
~
~~
_ _--.j,1 I"
N
RAS
I I..
I I
II
CAS
-+i
d-: i
Id(CHRL! }.
I I
Ih(RA)
~
IsUA-+i111
AD-AS
I
r
~Yt
I
I I
I
'h(SFRi~
I'-
~
II
I
I
I
I
I
i
~
--.J"1
Iw(CH)
I
I
I
I
I
~
i " ••
~
§§§W::
I+- 'hfTRGI I
!~:
~
iiiii
I
I
-+i 'I
I"
Ih(RWM) -+l I+-
DQ
I
+-1
Isu(WMR)
WEx
*- Iw(RH) +II
§§§W i i ~"""""".I. .+i --"~""""""""""""'""""""""=~~"""""'""""""""=~=
IsufTRG) ~
TRG
I 1
I
Refresh
R o w .
I I
-+I ~ Isu(SFC)
~ ~ Isu(SFR) I I
I I ~ Ih(RS~ ---+I
DSF
~
I -+l i+-II
I
~I !+-l- Id(CHRL)-+I
Iw(CL)
i1
~
~I
I
Id(CLRH)
I 1+
I
~ Id(RLCL) ~I~
I
L
0
Id(RLCH)
I"
~
~I
Iw(RL)
Isu(WCH)
Isu(WRH)
Ih(RLW)
I .,"
Ih(CLW)
~ Isu(WCL)
I ~1
I~ i
I
I
-+I
I
1
I..
:
~~~~~~~~C
~I
I
~I
~I
1
~
Iw(WL)
Ii
I
I
~I
I" I I
I" I I
1 I I
I
I
I I
~ Isu(DCL)
I..
Ih(CLD)
~
~I
Ih(RLD)
~
WrlleMaskDala
t Load mask register cycle will put the device into the persistent write-per-bit mode.
Figure 23. Load Mask Register Timing (Early Write Load)t
TEXAS
~
INSTRUMENTS
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TMS55165
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MULTIPORT VIDEO RAM
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PARAMETER MEASUREMENT INFORMATION
10lil
_ _--,;1 10lil
N
I 10lil
CAS
I :+-
iliii i :
Ih(RA)
Isu(RA)-+I
~I
10lil
Id(CLRH)
Id(RLCL) --.:
-H 1:+-
I
Vi
i 41
1
N~
.
-1" -
.1
I ~ Iw(RH)
1 ~I I
1
Id(CHRL) ---+i
1 4-i II1II- II
Id(RLCH)
II ~ ~
~ ~ Id(CHRL)
~
~I
Ic(W)
Iw(RL)
~0r+!-----""'l\-
Iw(CL)
I
I i i I
1
I 1
1 ~ Iw(CH) ----..I
~
AD-A8
I ~ Ih(RS!"l~
Isu(SFR)
-.I. ~
--.I IIIIIt
Isu(SFC)
1
I
1
1
DSF
~~
:·i'~ ___~~~~~~~~~~~~~~~
~: i i ~~~I~~~
TRG
~:
I 1
~ ~
1I I
:
WEx
~
td(GHD)
~
10lil
10lil
1
!
Isu(WRH)
tsu(WCH)
Ih(CLW)
Ii+I
I
10lil
--.I
~I
Ih(WLG)
tsu(DWL)
1
~I
~
-jl---~~I
~~
~ ~
I
I
,
rf---th(WLD)~
I
1
~I
th(RLD)
~
Write Mask Data
~
t Load mask register cycle will put the device into the persistent write-per-bit mode.
Figure 24. Load Mask Register Timing (Late Write Load)t
TEXAS
~
INSTRUMENTS
7-88
I
1
I
I
1
i rr--tW(WL)
1
:
I
.1
1 th(RLW)
Isu(WMR)
1 10lil
th(RWM) ---t.j I
I
DQ
I
10lil
Isu(TRG)
i.t-fI 0lil
~ i41
!
1
1
I
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
TMS55165
262 144 BY 16·BIT
MULTIPaRT VIDEO RAM
SMVS165B-AUGUST 1992-REVISED JANUARY 1993
PARAMETER MEASUREMENT INFORMATION
1411
tc(rdW)
1411
RAS
CAS
~I ~~
I
)fl1
I
~I
tsu(RA) - ,
AG-A8
td(CHRL)
~ Id(RLCL)
~III th(RA)
--:C
Id~~
~
ir
~
Y1l
III\{
I
I I ~ tw(CH) ~
I I
I I
II
.1
I4t
I I
I
~
tsu(CA)
I I....
I
I ~
i+-th(CLCA)
I ~th(RLCN~
~
I
1411 I
I
Id(CARH)
~ td(RLCA) +!
I
~
~ ~ow ~ ~Olumn ~Hl~~aj{~
:
th(SFR) ~
,I~
I
I~
I I
I I
.1
I ~ th(SFC)
~ tsu(SFC)
---.I
-I
DSF~::
I
I
I
~i: ~tH9H
~ tsu~
IQ~tWfTRG)
-+i ~
~
su(J'lMR)
I
1
1 1411
1
t
~
, I I
~
tsu(J'lCH)
I!
II
~
II~~
th(J'lLGl 1411
i
¥Wi:411
Ii "': ta(CA)
..
. td(RLWL)
I
II .,
r
~~ ~1(DGL)
.1
.1
I
I
t '\AIL) ~
w, . . . :
~
I_
"" I
I
I ~th(J'lLD)-"'I
lr~a(c): ,n:i i4-~'(DW4
:411
,~)
2
II
I
I I
I I :I I
th(RLW)
I I
I I ,~ I
I I
th(CLW).1 I
I I ~td(C~WL)
I
1411.1 II td(DCL)
I
I I
I I
II I
I
I III
1411 tl
. : td(CLGH) N~~
~ta(R)
-+I 1411+ tsu(DOR)
I
I
~~~~I
~I
I 1411 I II
td(CAWL)
.1 j+- tsu(J'lRH) - r I
I 1411
I I
,
th(RWM)
II
I I
~~~~~~~~~~~~~~~~~
I I
I I
TRGWlll
11111
1111111
-+i 14 tsufTRG)
I I II I
DO
I
~!"--I,\f I
.Ii!
..~ I ,~
rl tw(RH)
tw(CL) -----~
.1 td(CHRL)
I'"~
I ~th(RSF)
~ ~ tsu(SFR)
WEx
.1
Id(RLCH)
~
- I I~
~
.1
twIRL)
~
1411
~ "&~r.
t
alGI
~ l.-
.1 I Id(GHD)
1{tl\
~
3
:
I
~
tdls(G)
Figure 25. Read-Write/Read-Modify-Write Cycle Timing
Table 7_ Write Cycle State Table
STATE
CYCLE
1
2
3
Don't care
Write operation with non-persistent write-per-bit
H
L
Write mask
Valid data
Valid data
Write operation with persistent write-per-bit
L
Don't care
Valid data
Write operation (non-masked)
TEXAS ~
INSTRUMENTS
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7-89
TMS55165
262 144 BY 16·BIT
MULTIPaRT VIDEO RAM
SMVS165B-AUGUST 1992-REVISED JANUARY 1993
PARAMETER MEASUREMENT INFORMATION
tw(RH)
1411
RAS
~
i.
I_
~ ~
IcI(RLCL)
td(CHRL)
I : . - IcI(RLCA) ~
tsu(RA)
+JI
i
1411
IcI(RLCH)
~
tsu(CA)
I ~ th(RA) ~
I"
1
I
j4-- tw(CH) ~
~ I
i*-- td(CLRH)
1411- td(CHRL)
~
I
I
t~L~A)!
I I
I
rf1\-
th(CLf A)
~~411
I
I
II
:
I
I I
I :
I I
~I
tc(P)
I
I
I"
!+-
I
1411
~I
-+!
~I
tw(RL)P
I
~
-~, :.- ~ ~'7' ~ ~I'~ :~
I
I I
I
I
IcI(CARH)
1411
~i I td(CLG~) I
"F_*H2g~
i.
1411
~ ~
I I
I I
.
~I
tsu(TRG)
1
~ ~ tsu(WMR) I
:411
I
th(TR?)
I+-t1
I
I I
I
1
tw(TRG)
i
I
I 1411
td(GLRH) II
~I I
I I~
~ Ii
I
I ~ tw(TRG) ~ I ~--+---1
I
I
I
I
--+I
1
1
I
t~u(rd)
I
I..
tdls(G)
1
~I
t~(RHrd)
I
td( LGH)
I
-+i
!+-
~ th(CHrd) +i
OQ
t Access time is ta(CP) or ta(CA) dependent.
*Output may go from the high-impedance state to an i,walid data state prior to the specified access time.
NOTE A: A write cycle or a read-modify-write cycle can be mixed with the read cycles as long as the write and read-mOdify-write timing
specifications are not violated and the proper polarity of DSF is selected on the falling edge of RAS and CAS to select the desired write
mode (normal, block write, etc.)
Figure 26. Enhanced Page-Mode Read Cycle Timing
TEXAS ~
INSTRUMENTS
7-90
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
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MULTIPaRT VIDEO RAM
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PARAMETER MEASUREMENT INFORMATION
t Referenced to the first WEx falling edge or the falling edge of CAS, whichever occurs later.
NOTE A: A read cycle or a read-modify-write cycle can be intermixed with write cycles, observing read and read-modify-write timing specifications.
To assure page-mode cycle time, TRG must remain high throughout the entire page-mode operation if the late write features is used.
If the early write cycle timing is used, the state of TRG is a don't care after the minimum period th(TRG) from the falling edge of RAS.
Figure 27. Enhanced Page-Mode Write Cycle Timing
Table 8. Write Cycle State Table
STATE
CYCLE
1
L
L
L
Write operation (non-masked)
Write operation with non-persistent write-per-bit
Write operation with persistent write-per-bit
2
3
4
5
L
L
H
Don't care
Valid data
L
L
Write mask
Valid data
Don't care
Valid data
L
*
Load write mask on either the first WEx falling edge or
H
L
H
Don't care
Write mask
the falling edge of CAS, whichever occurs later.
Load write mask cycle will set the device to the persistent write-per-blt mode. Column address at the failing edge of CAS is don't care dUring this
cycle.
*
TEXAS ~
INSTRUMENTS
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7-91
TMS55165
262 144 BY 16-BIT
MULTIPaRT VIDEO RAM
SMVSI65B-AUGUST 1992-REVISED JANUARY 1993
RAS
PARAMETER MEASUREMENT INFORMATION
N"
W~
td(CHRL)
~~)d(RLCL)
I I
1
~
~I
~
!~
~
I
I+- th(RA) I I'"
tsu(CA)
I I I
I I I
I
I
I I tsu(rd)
I r----ld(CLWL)
I I.. I I"': L(R~:~)AWL)
~I
N!
I I
!su(DOR)
-+I
th(RDQ)
~
--.J 1..-
I
-+II+!
tsuCWCH)
I I
~ td(CLGH)
I I
I
I. I
tsuCWRH)
I:
~I'
'U'
II
I
II
I
*'
II II I
I
I I I I
I I fti j+- ts(C) t I
!I
If--iT*I ta(CA) t I t hCWLD) I~I
~ t~(DCL) I -+i *- I I
tsu(DWL)
J,----.,;.-t
I I
~
i-.J
I
I
I
I
I
I
I
!
WEx
I I
__ I
I I
~I
I I.. :
I I...
-+j 14-1- td(DCL)
-::
I I...
--I td(CLG~)
+I ~
II I I
I
!sU(TR%# I I:
I 11 Ii
';W(TRG) :
TRG
W II II II III ~~!}'iI
I I
tsuCWMR) ~! I
I I II I
I
I
I tWCWL)lm
th(RW' )~ j4- II II I
th(TRG)
~
~ I
: .::
~;;-~,q~
!....t tw(TRG)
I
II"
I
I"
II
L'.Ii.~~2
-!J i+f.
tsut\AlLD)
\ ..
thCWLD)--i+--.J
-- f td(GHD) I
I
la( P) t
..
I ~ tw(RH)
I
~
I
I __ I
I I
td(CARH)
: COI+~
1+ tSIj(SFC)
~I th(SFC) 1
I
I I ~su(SFR) I I"
OS,
I
, I
1 I
I I
I'" I
,I
iii th(CLCA) . I
l
l-ld(CLRH)
tw(CH)
td(CHRL)
tc(RDWP).!
~ t~1~~m~
-+I 1,..1 j+- t h (SFRl I
,~
~I
~I tw(CL) ~I
I
td(RLCA):~~i"
tsu(RA) +i
AO-AS
__I
td(RLCH)
~ I~l,.
CAS
~
tw(RL)P
I
DO
1!1'-1-~
I I
I
td(QGL)
I~
-+I
~ ta(R) t
I
*-
I
---.J
I
If
I I
II -+I ~
td(DGL).+j
~ td(GHD)
-+I
*-
tdls(G)
ta(C) t
t Output may go from the high-impedance state to an invalid data state prior to the specified access time,
NOTE A: Aread ora write cycle can be intermixed with read-modify-write cycles as long as the read and write timing specifications are not violated,
Figure 28. Enhanced Page-Mode Read-Modify-Write Cycle Timing
Table 9. Write Cycle State Table
STATE
CYCLE
Write operation (non-masked)
1
2
3
4
5
L
L
H
Don't care
Valid data
Write operation with non-persistent write-per-bit
L
L
L
Write mask
-Valid data
Write operation with persistent write-per-bit
L
L
L
Don't care
Valid data
H
L
H
Don't care
Write mask
*
Load write mask on either the first WEx falling edge or
the falling edge of CAS whichever occurs later,
*
Load write mask cycle will set the device to the persistent write-per-bit mode. Column address at the falling edge of CAS is don't care during this
cycle.
TEXAS
~
INSTRUMENTS
7-92
POST OFFICE BOX 1443' HOUSTON, TEXAS 77001
TMS55165
262144 BY 16·BIT
MULTIPaRT VIDEO RAM
SMVS165B--AUGUST 1992-REVISED JANUARY 1993
PARAMETER MEASUREMENT INFORMATION
yyyyy.Jz
DSF
llli/.
1 1
1 1
ffiW.J
'-
~gX~X~~~
ta(C)
ldls(CH)
{
Valid Output
~ ~
Figure 36. Hidden Refresh Cycle Timing
NOTE A: CAS-before-RAS refresh (option reset) mode will end persistent write-per-bit mode. Hidden refresh will also end the persistent
write-per-bit mode regardless of the state of D$F at RAS.
TEXAS ~
INsrRUMENTS
7-100
. POST OFFICE BOX 1443· HOUSTON, TEXAS 77001
TMS55165
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MULTIPORT VIDEO RAM
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PARAMETER MEASUREMENT INFORMATION
14
tc(TRO)
I 14
i'i: 14
- - - - - . . , . I+-- tcJ(RLCL)
I
I I
vvvvvJ.
~
t
AO-AS
:
ox
i/i+--- tw(RH) -----+I \......._ _
L ~I
tw(CL) M
~ td(CARH) ~
---+I
~ I.
~I
: ... th(RA) ~
~
+w
~ 14
I
OSF
r
.
I
V
Ii'{
II I14- tcJ(RLCA)
I '-I_ _ _ _oJ
I j 4 - - th(RLCA) I I
~
8u(RA) I
tsu(SFR)
:
td(RLCH)
td(CHRL) ~141---"'~1
~
~
4:
twIRL)
I I
II
~ th(CLCA)
---+I I+- t8u(CA)
~T~~~~nt~~*2~*~
~I th(SFR) I
~~~~~~~~~~~~~~~~=
~
}
-II~
OQ
QSF
Tap Point bit A7
H
SE
Id(CLQSF)
1144------ tcJ(RLQSF)
J
~
L ----------------------------------------------------------------
t Early·load operation is defined as th(TRG) min < th(TRG) < td(RLTH) min.
NOTES: A Random mode (DO outputs) remain in the high·impedance state forthe entire memory to data register transfer cycle. The memory
to data register transfer cycle is used to load the data registers in parallel from the memory array. The 256 locations in each data
register are written into from the 256 corresponding columns of the selected row.
B. Once data is transferred into the data registers. the SAM is in the serial read mode (I.e .• the SO is enabled). thus allowing data to
be shifted out of the registers. Also. the first bit to be read from the data register after TRG has gone high must be activated by a
positive transition of SC.
C. AO-A7: Register tap point. AS: which half of the transferred row.
Figure 37. Read Transfer Timing, Early Load Operationt
TEXAS
~
INSTRUMENTS
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7-101
TMS55165
262 144 BY 16·BIT
MULTIPORT VIDEO RAM
SMVS165B-AUGUST 1992-REVISED JANUARY 1993
PARAMETER MEASUREMENT INFORMATION
14
1 14
~I
----~\II~
1
i
~ td(RLCL) ~
1
~I
tc(TRD)
twIRL)
1
if.
~
! ),... _____---r_ _ _--'!.l ~ tw(RH) ~ \..'--_ _
Id(CHRL) .....~t---~~I 14
td(RLdH)
I ~
I
1
wxmL
td(RLCA) -+/
~
14---- th(RLCA) 11 1
I
~
:
~oW
~
lsu(TRG)
11
~ I
I
I I
~
I
I
I
!
th(CLCA)
~Tif:~nt~~~~~~n~~~7'I:m*~~~
~
~~x~aX{~
td(CL~H)
14
l+----td(RLTH)
1
I
~ 14
~(WMR)r
I
td(CAGH)
-j+---+! 14
i
~
I
td(THRL)
~ ~ td(!HRHI
YI
~I
~
1 I
I
1 j4-- tw(GH) ~
1
t
1
II
I
~I
-+/ ~;U(C4)
1
~i~
14
tSU(SFR)M
DSF
i
~I 1.-1 th(RA) ~
I
AO-A8
i+- tw(CL) M
N
I V
I
II
I !+--
'tlii;/
tsu(RA)
I
~ th(RWM) 1
. . .
-
DQ
SQ
Old Data
I
I
Old Data
New Data
-"'IGHQS~?,,-I
_
2-_______
Tap Point bit
QSF
A7
H
SE
r4---Id(CLQSF)
l<1li1.,.------- td(RLQSF)
~I
~I
L -----------------~-~---------------t Late load operation is defined as Id(THRH) < 0 ns.
NOTES: A. Once data is transferred into the data registers, the SAM is in the serial read mode (i.e., the SO is enabled), thus allowing data to
be shifted out of the registers. Also, the first bit to be read from the data register after TRG has gone high must be activated by a
positive transition of SC.
B. Random mode (DO outputs) remain in the high·impedance state for the entire memory to data register transfer cycle. The memory
to data register transfer cycle is used to load the data registers in parallel from the memory array. The 256 locations in each data
register are written into from the 256 corresponding columns of the selected row.
C. AO-A7: Register tap point, AS: which half of the transferred row.
Figure 38. Read Transfer Timing, Real-Time Reload Operation/Late Load Operation t
TEXAS
~
INSI'RUMENTS
7·102
POST OFFICE BOX 1443· HOUSTON. TEXAS 77001
TMS55165
262144 BY 16·BIT
MULTIPORT VIDEO RAM
SMVS165B-AUGUST 1992-REVISED JANUARY 1993
PARAMETER MEASUREMENT INFORMATION
10lIl
~I
tc(TRD)
~I ~ tw(RH) ~
i 10lIl
twIRL)
- - - - " " ' " ~td(RLCL) ~
N
:
I 10lIl
~LCA) 10lIl
td(RLCH) -
~ I
ld(CHRL)
iiiii ::
~
tsu(CA)
SU(RA),
I I
\
yr.:...,:r---------.j~~~~~
lOlll ~\l.
thl~A)~fi:+-:OIII
t
.~
I
'-------~I 1@<
tw(RL)
I
I
I
DATA OUT
~
I
I I
I
I
I
I
I
I
0
lOll
N ----+!
!+---
\ ......_-
tV(OUT)
J@(
N-1
~:
th(RSTR)
I
)@(
N
)@(
0
R
Figure 4. Read Cycle Timing (Reset Read)
~
Disable ~
I
I I
SRCK
I + - N+1
I
I
i
R
\l-
i4f
I I
I ~ th(R) ~
tsu(RL)
-+I
I
lOll
I
I
I
I
I I
'--_.:T1 I
-+I
-+i
i+---- Disable -----+i
--~~I
~
th(R)
1/,
~IOII-----tW(R)
~I
I
1----'lr»)--HI-z----.....
RSTR
((
))
Figure 5. Read Cycle Timing (Read Enable)
TEXAS
~
INSTRUMENTS
7-118
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
TMS4C10S0B
262 264-WORD BY 4-BIT
FIELD MEMORY
SMGSOSOE-JANUARY 19S8-REVISED DECEMBER 1992
PARAMETER MEASUREMENT INFORMATION
Case 1
.!
2
I..
\
R
/
\1
/
SRCK
tdls(CK)
/
1
DATA OUT
;-
\I
:..
.1 ten(CK)
1
(
Case 2
\
/
SRCK
\
R
;-
\
/
fi
I..
.1
1
1
Idls(RL)
ten(RH)
I..
·1
2
DATA OUT
C
Figure 6. Read Cycle Timing (Output Enable and Disable)
0
2
3
599
600
602
601
SWCK
w.J
.J
',I
\
RSTW
DAi~
=x
NewO
X
New 1
'/;
X
New2
X
New3
)(
X
New 599
New 600
X
New601
X
New 602
0
><==
2
SRCK
R
I
'/J
RSTR
,~
,
DATA
OUT
'/;
< NewO
Figure 7. New Data Access Mode
TEXAS
\
X
New 1
><==
~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
7·119
TMS4C1050B
262 264-WORD BY 4-BIT
FIELD MEMORY
SMGS050E-JANUARY 1988-REVISED DECEMBER 1992
PARAMETER MEASUREMENT INFORMATION
o
2
3
119
120
121
122
SWCK
W../
RSTW . . /
DA;~
=:x
NewO
\~------------------------------~\r\-----------------------------------------------------------------X
X
X
X
X
X
><==
New 1
New2
New3 )( Newl19
New 120
New121
New 122
o
2
SRCK
R
---------------------------------------~\\\------~
RSTR
---------------~"r___l
D~~~
------------------'Iir,-------«
Figure 8. Old Data Access Mode
TEXAS
~
INSfRUMENTS
7·120
POST OFFICE BOX 1443· HOUSTON, TEXAS 77001
\'-----Old 0
X
Old 1
x==
TMS4C1060B
262 264·WORD BY 4·BIT
FIELD MEMORY
SMGS060A-JANUARY 1988-REVISED DECEMBER 1992
• Organization ... 262 264 x 4
• Single 5-V Power Supply (± 10% Tolerance)
N PACKAGEt
(TOP VIEW)
• Fast FIFO (First-In First-Out) Operation
- Full Word Continuous Read/Write
- Asynchronous Read/Write
•
•
•
•
Fully Static (Refresh Free)
High-Speed Read/Write Operation
Cascade Connection Capability
Max Access / Min Cycle Time
TMS4C10608-30
TMS4C10608-40
TMS4C10608-60
ACCESS
TIME
(MAX)
25 ns
30 ns
50 ns
CYCLE
TIME
READ
(MIN)
30 ns
40 ns
60 ns
CYCLE
TIME
WRITE
(MIN)
30 ns
40 ns
60 ns
W
16
RSTW
15
SWCK
14
RSTR
DO
D1
D2
D3
13
SRCK
12
VSS
9
00
01
02
03
11
10
So PACKAGEt
(TOP VIEW)
RSTR
• Low Power Dissipation (Average
100 = 50 mA at Minimum Cycle)
• Plastic 16-Pin 300-mil-Wide DIP, 20-Pin
400-mil ZIP, or 20/26-Lead Surface-Mount
(SOJ) Package
VCC
RSTW
DO
NC
OJ PACKAGEt
(TOP VIEW)
W
RSTW
SWCK
DO
NC
VCC
R
RSTR
SRCK
NC
NC
NC
NC
• Texas Instruments EPIC ™ (Enhanced
Performance Implanted CMOS) Technology
D2
VSS
03
01
• Operating Free-Air Temperature
O°C to 70°C
• Fully Compatible With TMS4C1060
VCC
R
02
00
NC
NC
D1
D2
D3
00
01
02
03
VSS
description
t The packages are shown for pinout reference only.
The TMS4C1060B is a Field Memory (FMEM)
which reads and writes data exclusively through
serial ports, 4 bits wide. Maximum storage
capacity is 262 264 words by four bits each.
Addressing is controlled by write address and
read address pOinters which must be reset to zero
before memory access begins.
PIN NOMENCLATURE
00-03
QO-Q3
R
RSTR
RSTW
SRCK
SWCK
Read and write access may occur asynchronously. When read access is delayed relative to write
access, the TMS4C1 060B functions like a First-In
First-Out (FIFO) register. The amount of delay
determines the length of the FIFO register.
W
NC
VCC
VSS
Data-In
Data-Out
Read Enable
Reset Read
Reset Write
Serial Read Clock
Serial Write Clock
Write Enable
No Internal Connection
5-V Power Supply
Ground
Unlike a conventional FIFO register, data may be read as many times as desired after it is written into the storage
array.
Minimum delay between writing into the device and reading out data is 600 SWCK cycles. Maximum delay is
one full field (262 264 write cycles).
The TMS4C1 060B employs state-of-the-art EPIC'" (Enhanced Performance Implanted CMOS) technology for
high performance, reliability, and low power at a low cost.
EPIC is a trademark of Texas Instruments Incorporated.
::
~~o~~~:;T~~~o:l: .1;!~r~~:I~~.I~.~~:~!r: I.~~~i~~~~md:~~i
atandard warranty. Production procelling doe. not n&C888arUy Inc Iud.
tilting 01,11 par.mater••
TEXAS
~
Copyright © 1992, Texas instruments Incorporated
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
7-121
TMS4C1060B
262 264·WORD BY 4·BIT
FIELD MEMORY
SMGS060A..,JANUARY 1988-REVISED DECEMBER 1992
description (continued)
Dynamic data storage cells are employed as the main data memory to achieve high density. Self-refresh and
arbitration logic are implemented within the TMS4C1 060B, supplying a refresh-free system. This logic prevents
any conflict between data-saving/data-Ioading/memory-refresh requests.
The write address counting scheme of the TMS4C1060B has been modified, relative to its read address
counting scheme, to allow easy cascading of several memory devices. The timing of output enabling and
disabling is clock edge controlled.
If the memory is to be used as a delay element only, it is not necessary to reset the address pointers. After the
memory has been completely filled and the write address pointer reaches its maximum value, it will wrap around
again to the first address of the main array (address 120). The read address pointer behaves in the same
manner.
The TMS4C1 060B is offered in a 16-pin dual-in-line plastic package (N suffix) designed for insertion in mounting
hole rows on 7,62-mm (300-mil) centers. The device is also offered in a 20-pin 400-mil ZIP package (SO suffix)
and a 300-mil20/26 J-Iead plastic surface mount SOJ package (OJ suffix). The TMS4C1 0608 is characterized
for operation from O°C to 70°C.
operation
write operation
The write operation is controlled by Wand two clocks, SWCK and RSTW. It is accomplished by cycling SWCK
and holding W high after the write address pointer reset operation (RSTW). Each write operation, beginning with
RSTW, must contain at least 120 active write cycles (SWCK cycles while W is high). To transfer the last data
written into the device (which at that time is still stored in the write line buffer) to the memory array, an RSTW
operation is required after the last SWCK cycle.
reset write (RSTW)
The first positive transition of SWCK after RSTW going high resets the write address pointers to zero. RSTW
setup and hold times are referenced to the rising edge of SWCK. The state of W may be high or low during any
reset operation. Before RSTW may be brought high again for a further reset operation, it must have been low
for at least two SWCK cycles.
data Inputs (DO-D3) and write clock (SWCK)
The SWCK input latches the data inputs on chip when W is high and also increments the internal write address
pointer. Data-in setup and hold times (tsu(D), th(D)) are referenced to the riSing edge of SWCK.
write enable (W)
W is used as a data-in enable/disable. A logic high on the W input enables the input, and a logiC low disables
the input and holds the internal write address pointer.
Note that W setup and hold times are referenced to the rising edge of SWCK.
read operation
The read operation is controlled by R and two clocks, SRCK and RSTR. It is accomplished by cycling SRCK
and holding R high after a read address pointer reset operation (RSTR). Each read operation, which begins with
RSTR, must contain at least 120 active read cycles (SRCK cycles while R is high).
reset read (RSTR)
The first positive transition of SRCK after RSTR goes high resets the read address pointers to zero. RSTR setup
and hold times are referenced to the riSing edge of SRCK. The state of R may be high or low during any reset
operation. Before RSTR may be brought high again for a further reset operation, it must have been low for at
least two SRCK cycles.
TEXAS ~
IN5rRUMENTS
7-122
POST OFFICE BOX 1443· HOUSTON. TEXAS 77001
TMS4C1060B
262 264-WORD BY 4-BIT
FIELD MEMORY
SMGS060A-JANUARY 19S5-REVISED DECEMBER 1992
data out (QO-Q3) and read clock (SRCK)
Data is shifted out of the data registers on the rising edge of SRCK when R is high during a read operation. The
SRCK input increments the internal read address pointer when R is high.
The three-state output buffer provides direct TTL compatibility (no pullup resistor required). Data out is the same
polarity as data in. The output becomes valid after the access time inteNal tAC that begins with the positive
transition of SRCK.
Output valid time [tv(ouT)l is referenced to the rising edge of SRCK in the next cycle.
output enabling and disabling
The state of R is latched in by the read clock. SRCK determines whether the outputs will be enabled or disabled.
If R is high at the rising edge of SRCK, the outputs will be enabled. If R is low at the rising edge of SRCK, the
outputs will be disabled. R setup and hold times are referenced to the rising edge of SRCK.
read enable (R)
R performs a double function. First, R gates the SRCK clock for incrementing the read pointer. When R is high
before the rising edge of SRCK, the read pointer is incremented. When R is low, the read pointer is not
incremented. R setup times [(tsu(RH) and tsu(RL)l and R hold times [th(R)l are referenced to the rising edge ofthe
SRCKclock.
The second function of R is to enable and disable the outputs. See the appropriate section on output enabling
and disabling.
power-up and initialization
When powering up, the device is designed to begin proper operation after at least 100 ~s after V CC has stabilized
to a value within the range of recommended operating conditions. This time is defined as tpOWER-OK. While it
is acceptable to start the initialization sequence during VCC ramp-up (beforetpOwER_oKl, the full sequence must
be repeated at least once after tpOWER-OK' The required initialization sequence for the write pointers is as
follows:
At least one SWCK clock cycle, followed by a reset write operation, followed by at least 130 dummy write
operations with W at high level, followed by another reset write operation. All timing parameters must be within
specifications for the initialization sequence. After initialization, the write address pointers are set to zero, and
writing may begin.
The initialization sequence for the read pointers is analogous to write pointer initialization, and must be
performed at least once after tpOWER-OK.
old/new data access
There must be minimum delay of 600 SWCK cycles between writing into memory and reading out from memory.
If reading from the first field starts with an RSTR operation, before the start of writing the second field, (before
the next RSTW operation), then the data just written in will be read out.
The start of reading out the first field of data may be delayed past the beginning of writing in the second field
of data for as many as 119 SWCK cycles. If the RSTR operation for the first field read-out occurs less than 120
SWCK cycles after the RSTW operation for the second field write-in, then the internal buffering of the device
assures that the first field will still be read out. The first field of data that is read out while the second field of data
is written is called old data.
In order to read out new data, i.e., the second field written in, the delay between an RSTW operation and an
RSTR operation must be at least 600 SRCK cycles. If the delay between RSTW and RSTR operations is more
than 120 but less than 600 cycles, then the data read out will be undetermined. It may be old data or new data
or a combination of old and new data. Such a timing should be avoided.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
7-123
TMS4C1060B
262 264·WORD BY 4·BIT
FIELD MEMORY
SMGS060A-JANUARY 19S5-REVISED DECEMBER 1992
cascade operation
The TMS4C1 0606 has been designed to allow easy cascading of multiple memory devices, in order to obtain
a higher storage depth or a longer delay than can be achieved with only one memory device. See the
interconnection diagram on page 11 for details.
As illustrated in the timing diagram on page 11 , the positive SRCK/SWCK edge at the beginning of a clock cycle
serves to initiate read-out, whereas writing in is initiated by the positive SWCK/SRCK edge at the end of a cycle.
This differs from the functionality of the TMS4C10506, in which both the read-out and the write-in are initiated
at the beginning of a clock cycle.
Internal operation
writing into memory
The first 120 words of data following the initial RSTW operation after power-up are written into a cache line buffer
(A) initially, and will never be stored elsewhere, to allow read-out of data later without the delay involved in
retrieving it from the main memory array.
Starting from address 120, data is written into the write line buffer, top block, until this block (256 words long)
is full. Further writing then occurs to the bottom block of the write line buffer, while the top block is transferred
to the main memory array. 6y the time the bottom block is full, the top block has been transferred to memory
and can be used again to receive new incoming data. The channeling of input data into the top or bottom block
is controlled internally by the device and is transparent to the user.
After the 120-word long cache buffer has been filled with incoming data, the input line selector switches the
connection of the input port over to the 6 line buffer to assure that the next field of data, which will arrive later
after a subsequent RSTW operation, does not overwrite the content ofthe cache buffer. Each subsequent filling
of the cache buffer toggles the connection of the input port between the A and the 6 line buffers with the 121 st
SWCK pulse. The A and 6 line buffers, as well as the input line selector, are static registers.
The connection of the output port will also be toggled between A and 6 line buffers by the 121 st SWCK pulse,
providing no read operation from a cache buffer is in progress at this time. The output port will always be
connected to the line buffers opposite to the one connected to the input port. In case a read operation from a
cache buffer is in progress when the 121 st SWCK occurs, the toggling of the output port connection will be
delayed until the cache buffer has been read out completely.
.
The requirement stated on page 2 that each write operation must contain at least 120 active SWCK cycles, exists
in order to assure that the toggling of the input and output ports between the A line buffer and the 6 line buffer
functions without errors as described above.
The serial write pointer stores the (column) address of the last input data word received, while the write counter
stores the row address.
After the last word of a fun write cycle has been latched in (with a positive transition of the SWCK clock), the write
line buffer most likely will be partially filled without having been transferred to the main memory array. To assure
that the information contained in the write line buffer is stored and cannot be lost, it is required that an RSTW
operation be performed when write clocking has stopped.
In addition to transferring the partially filled write line buffer into the main memory array, this RSTW operation
will also reset the write addresses (serial write pointer) to zero. Regardless of how much later a new write cycle
starts, it is not necessary to perform another RSTW operation again at that time.
reading from memory
After an RSTR operation, data from the main memory array (starting at address 120) will be transferred to a read
line buffer. 6ecause this transfer requires some time, the first 120 words will be read out of the A or 6 line buffers,
where they had been previously stored (see writing into memory above).
TEXAs ~
INSTRUMENTS
7·124
POST OFFICE BOX 1443· HOUSTON, TEXAS 77001
TMS4C1060B
262 264-WORD BY 4-BIT
FIELD MEMORY
SMGS060A--JANUARY 1988-REVISEO DECEMBER 1992
If the first RSTR operation occurs after the first RSTW operation but before the second RSTW operation, read
access will be to the same buffer that data had been written into during the first write cycle. Thus old data will
be read out.
If the first RSTR operation occurs after the second RSTW operation (Le., after the writing in of new data has
already started), then the delay between the second RSTW and the first RSTR operation determines whether
old data or new data will be read out.
If this delay is less than 120 SWCK cycles, data will be read out from the line buffer that was written into during
the previous write cycle; Le., old data will be read out. A delay of less than 120 SWCK cycles also assures that
all following data bits are old data, because replacement of old data by new data in the main memory array will
occur later than the respective read access to each address in the array.
Ifthis delay is more than 600 SWCK cycles, data will be read outfrom the line buffer that it was written into during
the current write cycle; Le., new data will be read out. A delay of more than 600 SWCK cycles also assures that
all following data bits are new data, because replacement of old data by new data in the main memory array
~
will occur before the respective read access to each address in the array.
If this delay is more than 120 but less than 600 SWCK cycles, data read out can be either old or new or a mixture
of old and new data, because it cannot be predicted accurately whether a word accessed for reading has already
.
been replaced by new data or not. Such a situation should be avoided.
After the first 120 words are read out of the A or B line buffer, read transfer from the main memory array to the
read line buffer is finished, and subsequent reading will occur from this buffer. Similartothe write operation, while
one half of this buffer is being read out, the other half will be filled again by a new read transfer from the main
memory array.
The serial read pointer stores the (column) address of the last data word read out, while the read counter stores
the row address.
self-refresh and arbitration logic
The self-refresh and arbitration logic will keep the main memory information refreshed automatically without
requiring any user action, control the address pointers for both read and write, and control the flow of information
both into and out of the main memory.
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
7-125
TMS4C1060B
262 264·WORD BY4·BIT
FIELD MEMORY
SMGS060A-JANUARY 19aB-REVISED DECEMBER 1992
functional block diagram
R
W
DATA
OUT
DATA
IN
(x4)
(x4)
RSTR
SRCK
RSTW
Serial
Read
Timing
Controller
Serial
Write
Timing
Controller
Read Counter
SWCK
Write Counter
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage range on any pin (see Note 1) .......................................... - 1 V to 7 V
Supply voltage range on Vee ........................................................... 0 V to 7 V
Short circuit output current ................................................................ 50 mA
Power dissipation .......................................................................... 1 W
Operating free-air temperature range .................................................. ooe to 70 e
Storage temperature range ....................................................... - 65°e to 150 e
0
0
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. This is a stress rating only, and
functional operation of the device at these or any other conditions beyond those indicated in the "recommended operating conditions" section of
this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values in this data sheet are with respect to VSS.
TEXAS . "
INSTRUMENTS
7-126
POST OFFICE BOX 1443· HOUSTON, TEXAS 77001
TMS4C1060B
262 264·WORD BY 4·BIT
FIELD MEMORY
SMGS060A-JANUARY 19SB-REVISED DECEMBER 1992
recommended operating conditions
MIN
NOM
MAX
VCC
Supply voltage
PARAMETER
4.5
5
5.5
V
VIH
High-level input voltage
2.4
VCC+l
V
VIL
Low-level input voltage (see Note 2)
'-1
0.8
V
TA
Operating free-air temperature
0
70
·C
NOTE 2: VIL = - 1.5 V undershoot IS allowed when device IS operated
In
UNIT
the range of recommended supply voltage,
electrical characteristics over full ranges of recommended operating conditions (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
'4Cl060B-30
MIN
MAX
'4Cl060B-40
MIN
MAX
'4Cl060B-60
MIN
MAX
UNIT
VOH
High-level output voltage
10H =-5 mA
VOL
Low-level output voltage
10L= 4.2 mA
0.4
0.4
0.4
V
II
Input current (leakage)
VCC = 5.5 V, VI = 0 to 6.5 V,
All other pins = 0 V to VCC
±10
±10
±10
~
10
Output current (leakage)
VCC = 5.5 V, Vo = 0 to VCC, R low
±10
±10
±10
~
1001
Average operating current
Minimum write/read cycle,
output open
50
45
35
mA
1002
Stand by current
After 1 RSTW/RSTR cycle,
Wand R low
10
10
10
mA
2.4
2.4
V
2.4
capacitance over recommended ranges of supply voltage and operating free-air temperature,
f = 1 MHzt
PARAMETER
MIN
TEST CONDITIONS
TYP
MAX
UNIT
Ci
Input capacitance
VI = 0, f = 1 MHz
7
pF
Co
Output capacitance
VI = 0, f = 1 MHz
10
pF
t VCC equal to 5 V ± 0.5 V and the bias on pinS under test IS 0 V.
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature
TEST
CONDITIONS
PARAMETER
'4Cl060B-30
MIN
MAX
'4Cl060B-40
MIN
MAX
'4Cl060B-60
MIN
UNIT
MAX
tAC
Access lime from SRCK high
see Note 3
tv(OUT)
Output valid time after SRCK high
see Note 3
6
ldis(CK)
Output disable time after SRCK high
see Note 4
4
15
4
15
4
15
ns
Ien(CK)
Output enable time after SRCK high
see Note 3
0
15
0
15
0
15
ns
NOTES:
25
30
6
50
6
ns
ns
3. The load connected to each output is a 50-pF capacitor to ground in parallel with a 218-Q resistor to 1.31 V as illustrated by
Figure 1.
4, Disable times are specified from the initiating timing edge until the output is no longer driven by the memory. If disable times are to
be measured by observing output voltage waveforms, sufficiently low load resistors and capacitors have to be used, and the RC
time constants of the load have to be taken into account.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
7-127
TMS4C1060B
262 264-WORD BY 4-BIT
FIELD MEMORY
SMGS060A-,JANUARY 1988-REVISED DECEMBER 1992
PARAMETER MEASUREMENT INFORMATION
RL = 218 Q
Q()....Q3 (OutPutS)~ 1.31 V
CL=50pF
T
Figure 1. Load Circuit for Timing Parameters
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (see Note 5)
'4C1060B-30
MIN
MAX
'4C1060B-40
MIN
MAX
'4C1060B-60
MIN
MAX
UNIT
1c(W)
Write cycle time (see Note 6)
30
40
60
Ic(R)
Read cycle time (see Note 6)
30
40
60
ns
tw(R)
Pulse duration, R low
10
10
10
ns
tw(W)
Pulse duration, W low
10
10
10
ns
tw(RH)
Pulse duration, SRCK high
12
17
20
ns
tw(RL)
Pulse duration, SRCK low
12
17
20
ns
tw(WH)
Pulse duration, SWCK high
12
17
20
ns
tw(WL)
Pulse duration, SWCK low
12
17
20
ns
tsu(D)
Data setup time before SWCK high
5
5
5
ns
tsu(RH)
R-high setup time before SRCK high
0
0
0
ns
tsu(RL)
R-Iow setup time before SRCK high
0
0
0
ns
tsu(WH)
W-high setup time before SWCK high
0
0
0
ns
tsu(WL)
W-Iow setup time before SWCK high
0
0
0
ns
tsu(RSTR)
RSTR setup time before SRCK high
3
3
3
ns
tsu(RSTW)
RSTW setup time before SWCK high
3
3
3
ns
th(D)
Data hold time after SWCK high
6
6
6
ns
th(R)
R-hold time after SRCK high
6
6
6
ns
th(W)
W-hold time after SWCK high
6
6
6
ns
th(RSTR)
RSTR hold time after SRCK high
6
6
6
ns
th(RSrwj
RSTW hold time after SWCK high
6
6
6
ns
tr
Transition time
3
NOTES:
3
30
3
30
ns
5. Timing measurements are referencedtoVIH (MIN) =2.4 VandVIL (MAX) = 0.8V. tris measured between VIH (MIN) andVIL (MAX).
6. All cycle times assume tr = 3 ns.
TEXAS ~
INSTRUMENTS
7-128
30
ns
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
TMS4C1060B
262 264·WORD BY 4·BIT
FIELD MEMORY
SMGS060A-JANUARY 1988-REVISED DECEMBER 1992
PARAMETER MEASUREMENT INFORMATION
I+--N~
1
1
1
I+-- tc(W) -----.I
SWCK
~1~
I+-- 0 ---.I
I+-- N-l ---.!
1
.1
1
1
1
1
1
1 1
1
1
1
1
1
1
1
1
1
1 4 - - - - th(RSTW) --~.I
1 1
1
1 1
1
tsu(RSTW) ~
1
1 1
1
1
1
1
1
~ tW(WH):
I~--------""'L
1
1
1
~ 14- tsU(O)
-+I j+- th(O)
1
-J
RSTW
0~3
W
Figure 2. Write Cycle Timing (Reset Write)
~ Disable
SWCK
I+-- Disable ---.l
1
1
1
1
1
1
1
1
1 1
tsu(WL)
W
r.-- N+1 ----+I
---.!
I+-- N ----+I
..... I_!
~ ~
1 14
1
1 1
1_ !
1
tsu(WH) -+I ~
1
14
1 1
I
I
~
th(W)
.1
Y
1
.1
th(W)
1
~
1414---tw(W) - - - " " ' . 1
00-03
RSTW
Figure 3. Write Cycle Timing (Write Enable)
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
7·129
TMS4C1{)60B
262 264-WORD BY 4-BIT
FIELD MEMORY
SMGS060A-JANUARY 1988-REVISED DECEMBER 1992
PARAMETER MEASUREMENT INFORMATION
!+-- N-1 --+i
1
1--
0
N
J+--tc(R)~
SRCK
RSTR
1
11
I
I
tw(RH) 1-I
I
I
1
1
I
I
I
I
tsU(RSTR)~ I
14---- th(RSTR) ---+I
I
I
I
I
I
,--
1
~I
twIRL)
I
\
~tAC-~
I
Qo-a3
N-2
)@(
)@(
N-1
)@(
N
)@(
0
)@(
R
Figure 4. Read Cycle Timing (Reset Read)
J + - - N+1 ~
~Dlsable~
SRCK
14-I
I
N
*-- Disable --.J
-----.,J
1
1 I
I 1
~
tsu(RL)
I I 1__
I
1
i+i
\l
R
I
1
1
1
:--
~
Qo-a3
N-1
>®<
N
tsu(RH) ~
.1 I
y
th(R)
.1
twIRl
I
14- tdls(CK)
)
HI-Z
RSTR
Figure 5. Read Cycle Timing (Read Enable)
TEXAS ~
INsrRUMENTS
7-130
POST OFFICE BOX 1443· HOUSTON, TEXAS 77001
1
I I
I
1 ~
~
I
1
I
th(R)
I
ltAC
I
~
~,
1
1
\
~ ten(CKl
,
,
@9<
N+1
X
TMS4C1060B
262 264·WORD BY 4·BIT
FIELD MEMORY
SMGS060A-JANUARY 1988-REVISED DECEMBER 1992
PARAMETER MEASUREMENT INFORMATION
RSTW,
RSTR
\~-------------------------------
../
0
3
2
SWCK,
SRCK
4
I
----.!
I.-- CLOCK Edge Which
CLOCK Edge Which
Initiates READ for WORD3:
../
W/R
7
6
5
DOUT
I
I
I
I
I
tAC for WORD3
(
-----l4+I
I
X 2X
oX
3
-+l:'-
Initiates WRITE for WORD3
X
4
X
X,-_6_><==
5
tau(D) for WORD3
DIN
Figure 6. Cascade Mode
Reset SignsI
Serial Clock
TMS4C1060B
Data Inputs
4 Bits
-
TMS4C1060B
RSTW
SWCK
RSTR
SRCK
Data In
Data Out
W
R
RSTW
SWCK
Data In
4 Bits
W
RSTR r-SRCK
Data Out
4 Bits
R I---
Enable Signal
Figure 7. Cascade Operation-Signal Connections
TEXAS ~
INsrRUMENTS
POST OFFICE BOX 1443 ~ HOUSTON, TEXAS 77001
7-131
TMS4C10608
262 264·WORD 8Y 4·81T
FIELD MEMORY
SMGS060A-JANUARY 1988-REVISED DECEMBER 1992
PARAMETER MEASUREMENT INFORMATION
2
0
599
3
600
602
601
SWCK
w.J
.J
'I',
\
RSTW
00-03
=x
X
NewO
'/,
X
New 1
X
New2
)(
New 598
X
New 599
X
New 600
X
o
New 601
><===
2
SRCK
R
RSTR
--------------------~\I~\--~/
------------------------~\~
\'-------
QO-Q3 ................................................................~\'~,........................~(
NewO
)(
New 1
~
Figure 8. New Data Access Mode
120
2
0
121
122
SWCK
w.J
.J
\~----------~\\\------------------------
RSTW
00-03
=x
_
....~)(
NewO
)(
New 1
)(
New2){ New 118 )( New119)( New 120 )( New121
o
><===
2
SRCK
R
RSTR
----------------------~\\\--~/
------------------------~\~
\'------
-----"\(~Ol~dO~)(
QO-Q3 - - - - - - - - - - - - - \ ' , ' \ - ' ,
Figure 9. Old Data Access Mode
TEXAS
~
INSTRUMENTS
7·132
POST OFFICE BOX 1443· HOUSTON, TEXAS 77001
Old 1
~
TMS4C1070B
262 264-WORD BY 4-BIT
FIELD MEMORY
SMGS070A-NOVEMBER 1990-REVISED DECEMBER 1992
N PACKAGEt
• Organization ... 262 264 x 4
• Single 5-V Power Supply (±10% Tolerance)
• Fast FIFO (First-In First-Out) Operation
- Full Word Continuous Read/Write
- Asynchronous Read/Write
• Fully Static (Refresh Free)
• High Speed Read/Write Operation
• Cascade Connection Capability
• Max Access I Min Cycle Time
ACCESS
TIME
(MAX)
TMS4C1070B-30 25 ns
TMS4C1070B-40 30 ns
TMS4C1070B-60 50 ns
READ
CYCLE
TIME
(MIN)
30 ns
40 ns
60 ns
WRITE
CYCLE
TIME
(MIN)
30 ns
40 ns
60 ns
(TOP VIEW)
U
IE
1
W
RSTW
SWCK
00
01
2
17
3
4
16 R
15 ] RSTR
5
14
6
J 00
02
03
7
13
12
8
11
02
VSS
9
10] 03
18
Vcc
OE
SRCK
01
t The package is shown for pinout reference only.
PIN NOMENCLATURE
• Write Mask Function By Input Enable
• Low Power Dissipation (Average
100 = 50 mA at Minimum Cycle)
• 18-Pin 300-MIL DIP
• Texas Instruments EPIC'· (Enhanced
Performance Implanted CMOS) Technology
00-03
00-03
R
OE
RSTR
RSTW
SRCK
SWCK
W
IE
• Operating Free-Air Temperature
O°C to 70°C
• 1-Megablt DRAM Compatible Process
Technology
• Fully Compatible With TMS4C1070
VCC
vSS
z
Data Inputs
Data Outputs
Read Enable
Output Enable
Reset Read
Reset Write
Serial Read Clock
Serial Write Clock
Write Enable
Input Enable
5-V Power Supply
Ground
o
.~
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~
o
LL
Z
W
U
description
Z
The TMS4C1070B is a Field Memory (FMEM) that reads and writes data exclusively through serial ports, 4
bits wide. Maximum stoiage capacity is 262 264 words by four bits each. Addressing is controlled by write
address and read address pOinters which must be reset to zero before memory access begins.
Read and write access may occur asynchronously. When read access is delayed ralative to write access, the
TMS4C1 070B functions like a First-In First-Out (FIFO) register. The amount of delay determines the length of
the FI FO register.
Unlike a conventional FIFO register, data may be read as many times as desired after it is written into the
storage array.
Minimum delay between writing into the device and reading out data is 600 SWCK cycles. Maximum delay is
one full field (262264 write cycles).
The TMS4C1 070B employs state-of-the-art EPIC'· (Enhanced Performance Implanted CMOS) technology for
high performance, reliability, and low power at low cost.
Dynamic data storage cells are employed as the main data memory to achieve high density. Self-refresh and
arbitration logic is implemented in the TMS4C1 070B, supplying a refresh-free system. This logic prevents any
conflict between data-saving/data-Ioading/memory-refresh requests.
EPIC is a trademark of Texas Instrumen1S Incorporated.
TEXAS
~
Copyright © 1992, Texas Instruments Incorporated
INsrRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
7-133
~
o
«
TMS4C1070B
262 264·WORD BY 4·BIT
FIELD MEMORY
SMGS070A-NOVEMBER 1990-REVISEO DECEMBER 1992
description (continued)
The TMS4C1 0708 is similar in operation and functionality to the TMS4C1 0508. Compared to TMS4C1 050B,
the TMS4C1 070B has the following additional functions and features:
a. The input enable function of the TMS4C1 070B allows the user to write into selected locations
of the memory only, leaving the rest of the contents unchanged.
b. The write address counting scheme of the TMS4C1070B has been modified relative to its
read address counting scheme to allow easy cascading of several memory devices.
If the memory is to be used as a delay element only, it is not necessary to reset the address pointers. After the
memory has been completely filled and the write address pointer reaches its maximum value, it will wrap around
again to the first address of the main array (address 120). The read address pointer behaves in the same
manner.
The TMS4C1 070B is offered in a 18-pin dual-in-Iine plastic package (N suffix). This device is characterized for
operation from O°C to 70°C.
operation
»
c
write operation
The write operation is controlled by W, IE and two clocks, SWCK and RSTW. The write operation is
accomplished by cycling SWCK and holding Wand IE high after the write address pointer reset operation
(RSTW). Each write operation, beginning with RSTW, must contain at least 120 write cycles (SWCK cycles while
W is high).
~
z
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."
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:xl
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z
To transfer the last data written into the device (which at that time is still stored in the write line buffer) to the
memory array, an RSTW operation is required after the last SWCK cycle.
reset write (RSTW)
The first positive transition of SWCK after RSTW going high resets the write address pointers to zero. RSTW
setup and hold times are referenced to the rising edge of SWCK. The state of W may be high or low during any
reset operation. Before RSTW may be brought high again for a further reset operation, it must have been low
for at least two SWCK cycles.
data inputs (00-03) and write clock (SWCK)
The SWCK input latches the data inputs on chip when Wand I E are high and also increments the internal write
address pointer, when W is high, regardless of the state of IE. Data-in setup and hold times [tsu(D), th(D)l are
referenced to the rising edge of SWCK.
write enable (W)
W is used as a data-in enable/diasble. A logic high on the W input enables the input, and a logic low disables
the input and holds the internal write address pOinter.
Note that W setup and hold times are referenced to the rising edge of SWCK.
TEXAS ~
INSTRUMENTS
7-134
POST OFFICE BOX 1443· HOUSTON. TEXAS 77001
TMS4C1070B
262 264·WORD BY 4·BIT
FIELD MEMORY
SMGS070A-NOVEMBER 1990--REVISED DECEMBER 1992
Input enable (IE)
IE is used to enable/disable writing into memory. A logic high on the IE enables writing, and a logic low disables
writing. The internal write address pointer is always incremented by cycling SWCK when W is high, regardless
of IE logic level. Note that IE setup and hold times are referenced to the rising edge of SWCK.
Write Cycle Function Table
SWCK RISING EDGE
W
IE
H
H
H
L
L
X
Write Address Pointer
Address Pointer Increment
Address Pointer Stop
00--03
Store Data
Not Store
Not Store
X = Don't Care
read operation
The read operation is controlled by four clocks, SRCK, RSTR, R, and OE. It is accomplished bycycling SRCK
and holding Rand OE high after a read address pointer reset operation (RSTR). Each read operation,which
begins with RSTR, must contain at least 120 read cycles (SRCK cycles while R is high).
SRCK RISING EDGE
R
DE
H
H
H
L
L
L
H
Read Address Pointer
Address Pointer Increment
Address Pointer Stop
L
00--03
::2:
Data Out
a:
o
u.
HI-Z
Data Out
HI-Z
z
reset read (RSTR)
The first positive transition of SRCK after RSTR goes high resets the read address pointers to zero. RSTR setup
and hold times are referenced to the rising edge of SRCK. The state of R may be high or low during any reset
operation. Before RSTR may be brought high again for a further reset operation, it must have been low for at
least two SRCK cycles.
data outputs (Qo-Q3) and read clock (SRCK)
Data is shifted out of the data registers on the rising edge of SRCK when Rand OE are high during a read
operation. The SRCK input increments the internal read address pointer when R is high.
The three-state output buffer provides direct TIL compatibility (no pullup resistor required). Data out is the same
polarity as data in. The output becomes valid after the access time interval (tAc) that begins with the positive
transition of SRCK. Output valid time [tv(OUT)l is referenced to the rising edge of SRCK in the next cycle.
read enable (R)
R is used to enable/disable incrementing the internal read address pointer. A logic high on the R input enables
pOinter incrementing by the next following positive SRCK transition, and a logic low disables pointer
incrementing. R setup and hold times are referenced to the rising edge of SRCK. The data at the outputs will
be the data read out during the SRCK cycle prior to R going low.
TEXAS
~
INsrRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
z
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~
Read Cycle Function Table
7-135
w
()
z
:;
c
4 x SWCK cycle time). In this special case, at least 123 SRCK cycles followed by
123 SWCK cycles are necessary before the next RSTR is issued and the reading of new data may begin.
I+--- 123 SRCK cycles ----+i
RSTR
,..--"""'\. i
~ 123SWCKcycles --+i
cascade operation
The TMS4C1 0708 has been designed to allow easy cascading of several memory devices in order to obtain
a higher storage depth or a longer delay than can be achieved with only one memory device. See the
interconnection diagram on page 14 for details.
As illustrated in the timing diagram on page 13, Figure 9, the positive SRCK/SWCK edge at the beginning of
a clock cycle serves to initiate read-out, whereas writing in is initiated by the positive SWCK/SRCK edge at the
end of a clock cycle. This differs from the functionality of the TMS4C1 0508, in which both the read-out and the
write-in are initiated at the beginning of a clock cycle.
TEXAS
~
INSTRUMENTS
7-136
POST OFFICE BOX 1443· HOUSTON. TEXAS 77001
TMS4C1070B
262 264-WORD BY 4-BIT
FIELD MEMORY
SMGS070A-NOVEMBER 1990-REVISED DECEMBER 1992
Internal operation
writing Into memory
The first 120 words of data following the initial RSTW operation after power-up are written into a cache line buffer,
(A) initially, and will never be stored elsewhere, to allow read-out of data later without the delay involved in
retrieving it from the main memory array.
Starting from address 120, data is written into the write line buffer, top block, until this block (256 words long)
is full. Further writing then occurs to the bottom block of the write line buffer, while the top block is transferred
to the main memory array. By the time the bottom block is full, the top block has been transferred to memory
and can be used again to receive new incoming data. The channelling of input data into the top or bottom block
is controlled internally by the device and is transparent to the user.
After the 120-word long cache buffer has been filled with incoming data, the input line selector switches the
connection of the input port over to the B line buffer, to assure that the next field of data which will arrive later,
after a subsequent RSTW operation, does not over-write the content of the cache buffer. Each subsequentfilling
of the cache buffer toggles the connection of the input port between the A and the B line buffers with the 121 st
SWCK pulse. The A and B line buffers, as well as the input line selector, are static registers.
The connection ofthe output port will also be toggled between the A and B line buffers by the 121 st SWCK pulse,
providing no read operation from a cache buffer is in progress at this time. The output port will always be
connected to the line buffer opposite to the one connected to the input port. In case a read operation from a cache
buffer is in progress when the 121 st SWCK occurs, the toggling of the output port connection will be delayed
until the cache buffer has been read out completely.
The requirement stated on page 2 that each write operation must contain at least 120 active SWCK cycles, exists
in order to assure that the toggling of the input and the output ports between the A line buffer and the B line buffer
functions without errors as described above.
The serial write pOinter stores the (column) address of the last input data word received, while the write counter
stores the row address.
After the last word of a full write cycle has been latched in (with a positive transition of the SWCK clock), the write
line buffer most likely will be partially filled without having been transferred to the main memory array. To assure
that the information contained in the write line buffer is stored and can not be lost, it is required that an RSTW
operation be performed when write clocking has stopped.
In addition to transferring the partially filled write line buffer into the main memory array, this RSTW operation
will also reset the write address (serial write pointer) to zero. Regardless of how much later a new write cycle
starts, it is not necessary to perform another RSTW operation again at that time.
reading from memory
After an RSTR operation, data from the main memory array (starting at address 120) will be transferred to the
read line buffer. Because this transfer requires some time, the first 120 words will be read out of the A or B line
buffer, where they had been previously stored (see writing into memory).
If the first RSTR operation occurs after the first RSTW operation but before the second RSTW operation, read
access will be to the same buffer that data had been written into during the first write cycle. Thus old data will
be read out.
If this delay is less than 120 SWCK cycles, data will be read out from the line buffer that it was written into during
the previous write cycle, i.e. old data will be read out. A delay of less than 120 SWCK cycles will also assure
that all following data words are old data, because replacement of old data by new data in the main memory
array will occur later than the respective read access to each address in the array.
TEXAS ~
INsrRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
7-137
z
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TEST
CONDITIONS
25
15
15
'4C1070B-40
MIN
MAX
30
4
15
0
6
15
'4C1070B-60
MIN
MAX
50
4
15
0
6
15
UNIT
ns
ns
ns
ns
NOTES: 3. The load connected to each output is a 50-pF capacitor to ground, in parallel with a 218-Q resistor to 1.31 V. (See Figure 1.)
4. Disable times are specified from the initiating timing edge until the output is no longer driven by the memory. If disable times are to
be measured by observing output voltage waveforms, sufficiently low load resistors and capacitors have to be used, and the RC
time constants of the load have to be taken into account.
Z
0
m
-z
":xJ
0
s:
~
0
Z
TEXAS
~
INSfRUMENTS
7-140
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
TMS4C1070B
262 264·WORD BY 4·BIT
FIELD MEMORY
SMGS070A-NOVEMBER 1990-REVISED DECEMBER 1992
PARAMETER MEASURMENT INFORMATION
00-03 (Outputs)
II
R = 218 Q
~1.31V
CL=50pF
Figure 1. Load Circuit for Timing Parameters
timing requirements over recommended
temperature (see Notes 5 and 6)
r~nges
of supply voltage and operating free-air
'4C 1070B-30
'4C1070B·40
'4C1070B-60
MIN
MIN
MIN
MAX
MAX
MAX
UNIT
leCWl
Write cycle time
30
40
60
ns
le(R)
Read cycle time
30
40
60
ns
twiRl
Pulse duration, R-Iow
10
10
10
ns
tw(W)
Pulse duration, W-Iow
10
10
10
ns
twflE)
Pulse duration, IE low
10
10
10
ns
tw(OE)
Pulse duration, OE low
10
10
10
ns
twfRH)
Pulse duration, SRCK high
12
17
20
ns
twiRL)
Pulse duration, SRCK low
12
17
20
ns
tw(WH)
Pulse duration, SWCK high
12
17
20
ns
twfWL)
Pulse duration, SWCK low
12
17
20
ns
tsu(D)
Data setup time before SWCK high
5
5
5
ns
tsu(RH)
R-high setup time before SRCK high
0
0
0
ns
tsu(RL)
R-Iow setup time before SRCK high
0
0
0
ns
\su(WH)
W-high setup time before SWCK high
0
0
0
ns
tsu(WL)
W-Iow setup time before SWCK high
0
0
0
ns
tsu(lEH)
IE high setup time before SWCK high
0
0
0
ns
tsu(lEL)
IE low setup time before SWCK high
0
0
0
ns
tsu(OEH)
OE high setup time before SRCK high
0
0
0
ns
tsu(OEL)
OE low setup time before SRCK high
0
0
0
ns
tsufRSTR)
RSTR setup time before SRCK high
3
3
3
ns
tsu(RSlW)
RSTW setup time before SWCK high
3
3
3
ns
th(D)
Data hold time after SWCK high
6
6
6
ns
thfRI
R hold time after SRCK high
6
6
6
ns
thCWl
W hold time after SWCK high
6
6
6
ns
th(lE)
IE hold time after SWCK high
6
6
6
ns
th(OE)
OE hold time after SRCK high
6
6
6
ns
thfRSTR)
RSTR hold time after SRCK high
6
6
6
ns
th(RSlW)
RSTW hold time after SWCK high
6
6
IT
Input transition time
3
6
3
NOTES:
30
3
30
ns
30
ns
5. Timing measurements are referenced to VIH (MIN) = 2.4 Vand VIL (MAX) = 0.8 V. IT IS measured between VIH (MIN) and VIL (MAX).
6. All cycle times assume IT = 3 ns.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
7-141
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C:::
~_ _ _
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~
Figure 2. Write Cycle Timing (Reset Write)
1+111-- N --~.I
I+-- Disable ~
1
!+-- Disable ~
14-- N + 1 ------+I
1
1
1
1
1
1 ,.--_"",
1
1
1
1 _-1
1I
1
1
1
SWCK
lJ
'-----*; I
:s:
tsu(WL)
~
o
z
I
III
W - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - VIH
and
~
z
o
m
-z
."
o
:
tw(WL)
:
I+-
1.,-_....
1
~_..,.I
I
I
RSTW
1
1
1+---
W
-+I
~
-+I
I+'
III
th(W)
00-03
~
=><
N-1
~
N
~
---~.j):
1
~I"---------
JI
1
.1
tw(W)
VIL
tsu(WH)
~
1..- th(W) -.I "'"----
_
N+1
>C
.
VIH
VIL
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - VIH
~
Figure 3. Write Cycle Timing (Write Enable)
TEXAS
~
INsrRUMENTS
7-142
VIH
POST OFFice BOX 1443' HOUSTON, TEXAS 77001
TMS4C1070B
262 264·WORD BY 4·BIT
FIELD MEMORY
SMGS070A-NOVEMBER 1990-REVISED DECEMBER 1992
PARAMETER MEASURMENT INFORMATION
I"
.1
Write Mask Cycle
!+-- Disable
1 4 - - - N --+1.1
I.-- Disable ~
SWCK
I
1
1
I
1
I~_
11
I
1I
I
------"""\1..
th(IE)
1
=x
*-:
~
N
tsu(IEH)
~
~ th(IE) ~ ' - - -
1
.1
~I"----- tw(IE)
N-1
I
·Y:
-+I
1
00-03
I.-- N + 3 ~
1
tSU(IEL""")--+j-"'i+J
IE
---J
~
N+3
>C :::
z
W -------------------------------------------------------------Figure 4. Write Cycle Timing (Input Enable
o-
=Write Mask Operation)
~
:E
a:
!+-- N -1 ----+I
I
I+I
.. - - N
r-
SRCK
RSTR
tc(R)
I
I I
--.II
tw(RH)"
I
: twIRL)
--~.I
------+i
1
I.
1
I
I
Ir--~
I I
I I
I
'--.II
1 I tsu(RSTR) ---!+---+I
VIH
VIL
1
I+- th(RSTR) ---.J
.1:
1
fr' --------.;--.;-:..--""'\
VIH
~---------------
VIL
---N---2---~-N---1-~-:..-N--~~___O__~~___~>@K
VIH
I
I+- tAC - :
QO-Q3
o
LL
14--- 0 ------.J
I
-.I ~
tv(OUT)
VIL
VIH
R
and
VIL
OE
Figure 5. Read,Cycle Timing (Reset Read)
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
7-143
Z
W
(.)
Z
~
c
«
TMS4C1070B
262 264·WORD BY 4·BIT
FIELD MEMORY
SMGS070A--NOVEMBER 199o-REVISED DECEMBER 1992
PARAMETER MEASURMENT INFORMATION
--~_I
1+--- N
SRCK
j+-- Disable
j+-- N + 1 ---+j
1
1
1I
1
1
11
1
1
1
~-.,.
---t ~I
tsu(RL)
_ _ _ _ _ _~
-+I
1 I ..
VIL
-If----"':!.
;.-1
VIH
1
.-:'\
j+-- th(R) --+i
\----
VIL
>C
VIH
VIL
VIH
VIL
Figure 6. Read Cycle Timing (Read Enable)
m
14
-z
SRCK
Q~3
_I
j+-- Disable
--+I
j + - - Disable ----+j
j+-- N + 3 ---+j
1
1
1
1
1
1I
1
1
11
tsu(OEL)
1
1
1
--t i+J1
1 I
4
-+I
~
I
I
OE
!:i
N
1
--~
3:
z
VIH
tsu(RL)
14
-I
tAC
ten(CK)~
I
~--N-+-1-
N
~
5
I~__
1
OE - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
z
o
olJ
1
_I
twIRl
Q~3 _ _N_-_1_ _)@(
."
Y
~
"I_ _ _ _ _ _ _ _ _ _ _...-i
l
14
»
o
-I
th(R)
\l
R
--+I
j + - - Disable ----+j
N-1
14 I
tcIls(CK) --l+----+j
-I
th(OE)
I
1
Y
1
1,..-__
1
~ tsu(OEH)
1
I+- th(OE)
I
tw(OE)
-I
ten(CK)
)@(N)HI-Z
j+- tAC
-l+4
~
--.i \.
'-----
4
I
@(--N-+-3->C
R ----------------------------------
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
Figure 7. Read Cycle Timing (Output Enable)
TEXAS .",
INSTRUMENTS
7-144
POST OFFICE BOX 1443· HOUSTON, TEXAS 77001
TMS4C1070B
262 264·WORD BY 4·BIT
FIELD MEMORY
SMGS070A-NOVEMBER 1990-REVISED DECEMBER 1992
PARAMETER MEASURMENT INFORMATION
N
N+1
N+2
N+3
N+4
N+5
N+7
N+6
N+B
SWCK
\
IE
/
W
X
00-03
N
X
N
N+1
N+1
X
N+2
N+2
N+3
X
N+3
~
N+4
N+5
N+6
N+6
X
N+7
N+7
N+B
SRCK
Z
OE
\
0
-
/
~
:!:
R
(New)
QO-Q3
X
N
(New)
) - - - - HI-Z - - - - {
N+3
(Old)
X
N+4
(New)
(Old)
X
N+5
X
N+6
a:
(New)
X
N+7
>C
0
U.
Z
W
Figure 8. Write Mask Operation
0
Z
~
c
5
: . - - CLOCK edge which
!
Initiates WRITE for WORD3
I
tAC for WORD3 -+I
(~o~X~
4
3
c
z~
Figure 9. Cascade Mode
o
m
Reset Signal
-z
Serial Clock
."
TMS4C1070B
o
-
:D
s:
~
Data Inputs
TMS4C1070B
RSTW
SWCK
RSTR
SRCK
Data In
Data Out
4 Bits
-
W
> - - - IE
o
z
RSTW
SWCK
Data In
4 Bits
R
OE
W
IE
Enable SignaI
Figure 10. Cascade Operation-Signal Connections
TEXAS .."
INsrRUMENTS
7-146
POST OFFICE BOX 1443' HOUSTON, TEXAS 77001
RSTR SRCK Data Out
R
OE
-
4 Bits
------<
>
TMS4C1070B
262 264·WORD BY 4·BIT
FIELD MEMORY
SMGS070A--NOVEMBER 199G-REVISED DECEMBER 1992
PARAMETER MEASURMENT INFORMATION
0
2
600
601
602
SWCK
WIlE
J
RSTW
J
DG-D3
:x__..JX
\~--------------------------------New 0
X
New 1
X. . _--JX......_..JX
New 599
X
New 600
X
New 601
o
>e::
2
SRCK
R/OE
RSTR
<»-03
z
f
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _....-J
______________________~f
\~
--------------------«
X
NewO
o
~
_______
Newl
~
x==
a:
oLL
Figure 11. New Data Access Mode
2
0
Z
121
120
122
W
o
SWCK
Z
WilE
~
J
RSTW
J
00-03
:x'--_..JX
:::>
c
e::
2
SRCK
R/OE
______________________-Jf
RSTR
____________________~f
QO-Q3
\~
_______
----------------~(~OI~dO~X Oldl
x==
Figure 12. Old Data Access Mode
TEXAS
~
INsrRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
7-147
TMS4C1070B
262 264-WORD BY 4-BIT
FIELD MEMORY
SMGS070A-NOVEMBER 199o-REVISED DECEMBER 1992
TEXAS ~
INSTRUMENTS
7-148
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
Memory Cards
8-1
Contents
CHAPTER 8.
MEMORY CARDS
CMS405
4 194 304-bit
(2048K x 18) DRAM Memory Card ............................. 8-3
CMS406
4 194 304-bit
(2048K x 16) DRAM Memory Card ............................. 8-3
CMS407
2 097 152-bit
(1 024K x 18) DRAM Memory Card ............................. 8-3
CMS408
2 097 152-bit
(1024 x 16) DRAM Memory Card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 8-3
CMS409
8 388 608-bit
(4096K x 18) DRAM Memory Card ............................ 8-17
CMS410
8 388 608-bit
(4096K x 16) DRAM Memory Card ............................ 8-17
CMS88D8MB36
8 388 608-bit
(2048K x 36) DRAM Memory Card ............................ 8-27
CMS88D4MB36
4 194 304-bit
(1024K x 36) DRAM Memory Card ............................ 8-27
CMS68P256
262144-bit
gi~~R~~ ~~~o~ 19~rd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
8-35
gi~KpR~~ ~~~Ko~ 19~rd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
8-35
~i-~KpR~~ ~~~~~ 19~rd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
8-35
~i-~~R~~ ~~~~~ tg~rd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
8-35
g~~4~RO~o~~~~~ J~~d ....................................
8-35
g~~~RO~O~~~~ryX J:~d ....................................
8-35
CMS68P256N
CMS68P512
CMS68P512N
CMS68P1MB
CMS68P1MBN
262144-bit
524288-bit
524288-bit
1 048 576-bit
1 048 576-bit
CMS68F256
262144-bit
(256K x 8 or 128K x 16) Flash Memory Card. . . . . . . . . . . . . . . . . . .. 8-45
CMS68F512
524288-bit
(512K x 8 or 256K x 16) Flash Memory Card .... : ............... 8-45
CMS68F1MB
1 048 576-bit
(1 024K x 8 or 512K x 16) Flash Memory Card .................. 8-45
CMS68F2MB
2 097 152-bit
(2048K x 80r 1024K x 16) Flash Memory Card ...... . . . . . . . . . . .. 8-45
CMS209
1 048 576-bit
(64K x 16) OTP PROM Memory Card . . . . . . . . . . . . . . . . . . . . . . . . .. 8-65
CMS210
2 097 152-bit
(128K x 16) OTP PROM Memory Card . . . . . . . . . . . . . . . . . . . . . . . .. 8-65
CMS213
524288-bit
(64K x 8) OTP PROM Memory Card . . . . . . . . . . . . . . . . . . . . . . . . . .. 8-65
CMS214
1 048 576-bit
(128K x 8) OTP PROM Memory Card . . . . . . . . . . . . . . . . . . . . . . . . .. 8-65
CMS216
2 097 152-bit
(256K x 8) OTP PROM Memory Card . . . . . . . . . . . . . . . . . . . . . . . . .. 8-65
8-2
CMS405, CMS406 4 MEGABYTE
CMS407, CMS408 2 MEGABYTE
DRAM MEMORY CARDS
SMNS405A-JUNE 1991-REVISED JANUARY 1993
•
Credit Card Size
(85.6 mm x 54 mm x 3.4 mm)
•
•
•
Single 5-V Power Supply (±5% Tolerance)
•
•
•
•
•
•
60-PIN MEMORY CARD
(CONNECTOR VIEW)
CMS405 CMS406 CMS407 CMS408 -
2
Vcc
6
NC
AO
NC
10
Vcc
14
A3
A4
NC/0017
16
20
DO
DO
DO
DO
DO
DO
DO
DO
Vcc
22
00
21
009
0010
0011
24
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
23
00
00
53
DO
DO
57
2M x 18/2RAS/2CAS
2M x 16/2RAS/2CAS
1M x 18/1 RAS/2CAS
1M x 16/1 RAS/2CAS
Operating Temperature ... O°C to 55°C
Standard 60-Pln Two-Piece Connector
CMOS Buffered Inputs on All Inputs Except
RAS and DQ
3-State Unlatched Output
Low Power Dissipation
Performance Ranges:
ACCESS
TIME
CMS40x-7
CMS40x-8
IRAC
70 ns
80 ns
ACCESS
TIME
ICAC
25 ns
27 ns
READ
OR WRITE
CYCLE
IRe
130 ns
150 ns
description
These cards have CMOS buffers added to the
CAS, W, and address inputs to minimize loading
caused by the module. RAS and data in/out
remain compatible with Series 74 TTL.
The cards can operate in enhanced page mode.
All address lines and data are latched on chip to
simplify system design. Data out is unlatched to
allow greater system flexibility.
The common I/O features of the CMS405/6/7/8
dictate the use of early write cycles.
4
8
12
18
26
28
Vcc
30
0012
0013
0014
32
34
36
Vcc
38
0015
0016
A5
40
Vcc
46
AS
A9
RAS2/NC
NC
The CMS405/6/7/8 series are dynamic randomaccess memory cards designed to be used as
internal system memory or as external add-on
memory.
00
00
P03
P02
Enhanced Page Mode Operation
42
44
48
50
52
54
Vcc
56
P04
NC
58
60
1
Vss
3
P01
5
Vii
7
NC
9
Vss
11
13
NC
A1
A2
15
17 Vss
19 OOS/NC
000
001
25 Vss
27 002
29
31
003
004
33 Vss
35 005
39
006
007
41
VSS
43
CASO
A6
A7
37
45
47
49 Vss
51 RASO
55
NC
CAS1
P05
59 Vss
PIN NOMENCLATURE
AD-A9
CASO. CASI
DOD-DO 17
PD1-PD5
RASO. RAS2
Vcc
.VSS
W
NC
Address Inputs
Column-Address Strobe
Data Inputs/Outputs
Presence Detect
Row-Address Strobe
5-V Power Supply
Ground
Write Enable
No Internal Connection
Copyright © 1993, Texas Instruments Incorporated
TEXAS . "
INsrRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
8-3
CMS405, CMS406 4 MEGABYTE
CMS407, CMS40B 2 MEGABYTE
DRAM MEMORY CARDS
SMNS405A-JUNE 1991-REVISED JANUARY 1993
operation
The CMS405/6/7/S cards are divided into separate banks of memory as shown in the functional block diagrams,
Each bank is selectable using RASx and CASx as shown in the table below. RASO and RAS2 control which side
of the DRAM banks are connected to the memory card DQ pins. Therefore, only one RAS signal may be active
during any read or write cycle.
Table 1. Memory Bank Definition
DATA BLOCK
DOO-D07, Doat
D09-DGI6,DOI7t
RASx
Side 1
Side 2
RASO
RASO
RAS2
RAS2
CASx
CASO
CASI
t DOa and 0017 are not available on CMS406 and CMS40a; only side one is available on CMS407 and CMS40a.
power up
To achieve proper device operation, an initial pause of 200 lAS followed by a minimum of eight initialization cycles
is required after full Vee level is achieved. The eight initialization cycles need to include at least one refresh
(RAS-only or CAS-before-RAS) cycle.
specifications
Refresh period is extended to 16 ms. During this period, each of the 1024 rows must be strobed with RAS to
retain data. The nine least significant row addresses (AO-AS) must be refreshed every S ms.
memory card components
- Meets JEDEC standard
- UL approved materials
- Plugs into molex connector part number 53213-6011 or equivalent
TEXAS
-If
INSTRUMENTS
a-4
POST OFFICE BOX 1443· HOUSTON, TEXAS nOO1
CMS40S, CMS406 4 MEGABYTE
CMS407, CMS408 2 MEGABYTE
DRAM MEMORY CARDS
SMNS405A-JUNE 1991-REVISED JANUARY 1993
CMS405 functional block diagram
RASO
1M x9
1M x9
AO-A9
-
AO-A9
-
RAS
CAS
r-
Vi
RAS
CAS
r-
Vi
OQO-DQ8
AO-A9
CASO
OQO-DQ8
~
9
OQO-OQ8
9
CASI
OQ9-0Q17
Vi
1M x9
1M x9
AO-A9
AO-A9
RAS
-
-
CAS
-
Vi
RAS
- '-
CAS
Vi
OQO-OQ8
OQO-DQ8
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS nOOl
8-5
CMS405, CMS406 4 MEGABYTE
CMS407, CMS408 2 MEGABYTE
DRAM MEMORY CARDS
SMNS405A-JUNE 1991-REVISED JANUARY 1993
CMS406 functional block diagram
RASO
1M x8
1M x8
AO-A9
-
AO-A9
-
RAS
CAS
-
W
RAS
CAS
r-
W
DQO-DQ7
AO-A9
CASO
DQO-DQ7
~
8
DQO-DQ7
8
CAS1
DQ9-DQ16
W
1M x8
1M x8
AO-A9
AO-A9
RAS
- -
-
RAS
- -
CAS
W
CAS
W
DQO-DQ71-
TEXAS
DQO-DQ71-
~
INSTRUMENTS
8-6
POST OFFICE BOX 1443· HOUSTON, TEXAS 77001
CMS405, CMS406 4 MEGABYTE
CMS407, CMS408 2 MEGABYTE
DRAM MEMORY CARDS
SMNS405A-JUNE 1991-REVISED JANUARY 1993
CMS407 functional block diagram
RASO
1M x9
1M x9
AD-A9
-
-
AD-A9
RAS
'---
CAS
-
CAS
-
W
RAS
W
DQO-OQ8~
DQO-OQ8 r9
DQD-DQ8
10
AD-A9
9
DQ9-DQ17
CAS1
W
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
8-7
CMS405~ CMS406 4 MEGABYTE
CMS407, CMS408 2 MEGABYTE
DRAM MEMORY CARDS
SMNS405A-JUNE 1991-REVISED JANUARY 1993
CMS408 functional block diagram
RASO
1M x8
1M x 8
AO-A9
'---
;-
AO-A9
RAS
'---
CAS
,--- CAS
W
;-
RAS
w
OQO-OQ71
OQO-OQ7
8
10
OQO-OQ7
AO-A9
8
~ OQ9-0Q16
CAS1
W
TEXAS ~
INSfRUMENTS
8-8
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
CMS40S, CMS406 4 MEGABYTE
CMS407, CMS408 2 MEGABYTE
DRAM MEMORY CARDS
SMNS405A-JUNE 1991-REVISED JANUARY 1993
Table 2. Pin Definition for Presence Detect
CONFIGURATION
I
I
PD1(3)
CMS405-8t
NC
SPEED
I
I
PD2(4)
VSS
PD3(2)
PD4(58)
VSS
VSS
I
I
PD5(57)
VSS
t Presence detect IS defined only for 80 ns version of the CMS405.
Table 3. Pin Definition
DEVICE
RAS2/NC (52)
DQS/NC (19)
DQ17/NC (20)
CMS405
CMS406
CMS407
CMS408
RAS2
RAS2
NC
NC
008
NC
DOB
NC
0017
NC
0017
NC
absolute maximum ratings over operating free-air temperature range (unless otherwise noted);
Supply voltage range on any pin (see Note 1) ................................. -0.5 V to Vee + 0.5 V
Voltage range on Vee .............................................................. -0.5 V to 6 V
Short circuit output current ................................................•............... 50 rnA
Power dissipation (CMS405) ............................................................. 11.5 W
Power dissipation (CMS406) .............................................................. 9.5 W
Power dissipation (CMS407) .............................................................. 6.5 W
Power dissipation (CMS408) .............................................................. 5.5 W
Operating free-air temperature ........................................................ O°C to 55°C
Storage temperature ............................................................. -40 OCto 85 0 C
*Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. This is a stress rating only, and
functional operation of the device at these or any other conditions beyond those indicated in the "recommended operating conditions" section
of this specification is not implied. Exposure to absolute-maximum-rated cond~ions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to VSS.
recommended operating conditions
VCC
Supply voltage
CAS, W, address lines
VIH
High-level input voltage
VIL
Low-level input voltage
(see Note 2)
TA
Operating free air temperature
MIN
NOM
MAX
UNIT
4.75
5
5.25
V
0.7VCC
RAS and DO lines
2.4
CAS, W, address lines
6.5
0.3VCC
RAS and DO lines
-1
0.8
0
55
V
V
·C
NOTE 2: The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used in this data sheet for logic
voltage levels only.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
8-9
CMS405 4 MEGABYTE
DRAM MEMORY CARD
SMNS405A-JUNE 1991-REVISED JANUARY 1993
electrical characteristics over full range of recommended operating conditions
PARAMETER
CMS405
TEST CONDITIONS
MIN
NOM
MAX
UNIT
VOH
High-level output voltage
IOH=-5mA
VOL
loW-level output voltage
IIL= 4.2 rnA
2.4
V
II
Input current for addresses,
CASx, andW
VI = Oto 5.25 V, Vee = 5 V,
All other pins = 0 V to V CC
±10
i!A
II
Input current RASx (leakage)
VI = Oto 5.25 V, VCC = 5 V,
All other pins = 0 V to V CC
±60
i!A
10
Output current (leakage)
Vo = 0 to VCC, VCC = 5.25 V, CASx high
±20
i!A
0.4
V
electrical characteristics over full range of recommended operating conditions (see Note 3)
PARAMETER
TEST CONDITIONS
ICC 1
Read or write cycle current
Minimum cycle, VCC = 5.25 V, Maximum of 2
address transitions per memory cycle. Only one
RAS active at any time.
ICC2
Standby current
ICC3
ICC4
CMS405-7
MIN
MAX
CMS405-8
MIN
MAX
UNIT
602
542
rnA
After 1 memory cycle, RAS and CAS high, All
other signals stable, VCC = 5.25 V.
25
25
rnA
Average refresh current
(RAS only or CSR)
Minimum cycle, VCC = 5.25 V, Maximum of 2
address transitions per memory cycle, RAS
active, CAS high.
1130
1010
rnA
Average page current
tpc = minimum, VCC = 5.25 V, Maximum of 2
address transitions per memory cycle. Only one
RAS active at any time, RAS low, CAS cycling.
542
482
rnA
NOTE 3: VIH = VCC - 0.2 V and VIL = 0 V for all operallng currents.
capacitance over recommended ranges of supply voltage and operating free-air temperature,
f = 1 MHz
CMS405
PARAMETER
MIN
MAX
UNIT
Ci(A)
Input capacitance, address inputs
15
pF
Ci(RASI
Input capacitance, RAS inputs
42
pF
Ci(CAS)
Input capacitance, CAS inputs
15
pF
CilWl
Input capacitance, W input
15
pF
Ci(DO)
InpuVoutput capacitance of DO pins (000-007, 009-0016)
14
pF
Ci(DO)
InpuVoutput capacitance of DO pins (008, 0017)
24
pF
1ExAs
~
INSfRUMENTS
8-10
POST OFFICE BOX 1443· HOUSTON, TEXAS 77001
CMS406 4 MEGABYTE
DRAM MEMORY CARD
SMNS405A-JUNE 1991-REVISED JANUARY 1993
electrical characteristics over full range of recommended operating conditions
PARAMETER
CMS406
TEST CONDITIONS
MIN
NOM
MAX
UNIT
VOH
High-level output voltage
10H =-5 mA
VOL
Low-level output voltage
IIL=4.2mA
II
Input current for addresses,
CASx, andW
VI = 0 to 5.25 V, VCC = 5 V,
All other pins = 0 V to V CC
±10
~
II
Input current RASx (leakage)
VI = 0 to 5.25 V, VCC = 5 V,
All other pins = 0 V to VCC
±40
~
10
Output current (leakage)
Vo = 0 to VCC, VCC = 5.25 V, CASx high
±20
~
V
2.4
0.4
V
electrical characteristics over full range of recommended operating conditions (see Note 3)
PARAMETER
TEST CONDITIONS
ICCl
Read or write cycle current
Minimum cycle, VCC = 5.25 V, Maximum of 2
address transitions per memory cycle. Only one
RAS active at any time.
ICC2
Standby current
After 1 memory cycle, RAS and CAS high. All
other signals stable, VCC = 5.25 V.
ICC3
Average refresh current
(RAS only or CBR)
ICC4
Average page current
CMS406-7
CMS406-8
MIN
MIN
MAX
MAX
UNIT
418
378
mA
17
17
mA
Minimum cycle, VCC = 5.25 V, Maximum of 2
address transitions per memory cycle, RAS active,
CAS high.
770
690
mA
tpc = minimum, VCC = 5.25 V, Maximum of 2
address transitions per memory cycle. Only one
RAS active at any time, RAS low, CAS cycling.
378
338
mA
NOTE 3. VIH = VCC - 0.2 V and VIL = 0 V for all operating currents.
capacitance over recommended ranges of supply voltage and operating free-air temperature,
f = 1 MHz
PARAMETER
CMS406
MIN
MAX
UNIT
CiIA)
Input capacitance, address inputs
15
pF
Ci(RAS)
Input capacitance, RAS inputs
28
pF
CiICAS)
Input capacitance, CAS inputs
15
pF
Ci(W)
Input capacitance, W input
15
pF
Ci(DQ)
InpuVoutput capacitance of DQ pins
14
pF
TEXAS ~
IN5rRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
8-11
CMS407 2 MEGABYTE
DRAM MEMORY CARD
SMNS40SA--lUNE t99t-REVISED JANUARY t993
electrical characteristics over full range of recommended operating conditions
. PARAMETER
CMS407
TEST CONDITIONS
MIN
NOM
MAX
UNIT
VOH
Hig h-Ievel output voltage
10H =-5mA
VOL
Low-level output voltage
IIL=4.2mA
V
II
Input current for addresses,
CASx, andW
VI = 0 to 5.25 V, Vec = 5 V,
All other pins = 0 V to VCC
±10
flA
II
Input current RASx (leakage)
VI = Oto 5.25 V, VCC = 5 V,
All other pins = 0 V to VCC
±60
flA
10
Output current (leakage)
Vo = 0 to Vcc, Vcc = 5.25 V, CASx high
±10
flA
2.4
0.4
V
electrical characteristics over full range of recommended operating conditions (see Note 3)
PARAMETER
TEST CONDITIONS
ICCI
Read or write cycle current
Minimum cycle, VCC = 5.25 V, Maximum of 2
address transitions per memory cycle. Only one
RAS active at any time.
ICC2
Standby current
ICC3
ICC4
CMS407-7
CMS407-8
MIN
MIN
MAX
MAX
UNIT
590
530
mA
After 1 memory cycle, RAS and CAS high, All
other signals stable, VCC = 5.25 V.
13
13
mA
Average refresh current
(RAS only or CSR)
Minimum cycle, VCC = 5.25 V, Maximum of 2
address transitions per memory cycle, RAS
active, CAS high.
590
530
mA
Average page current
tpc = minimum, VCC = 5.25 V, Maximum of 2
address transitions per memory cycle. Only one
RAS active at any time, RAS low, CAS cycling.
530
470
mA
NOTE 3: VIH = VCC - 0.2 V and VIL = 0 V for all operating currents.
capacitance over recommended ranges of supply voltage and operating free-air temperature,
f = 1 MHz
CMS407
PARAMETER
MIN
MAX
UNIT
Ci(A)
Input capacitance, address inputs
15
pF
Ci(RAS)
Input capac~ance, RAS inputs
42
pF
Ci(CAS)
Input capacitance, CAS inputs
15
pF
Ci(W)
Input capacitance, W input
15
pF
Ci(DQ)
InpuVoutput capacitance of DQ pins (DQO-DQ7, DQ9-DQI6)
14
pF
Ci(DQ)
InpuVoutput capacitance of DQ pins (DQB, DQI7)
12
pF
TEXAS
~
INsrRUMENTS
8-12
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
CMS408 2 MEGABYTE
DRAM MEMORY CARD
SMNS405A-JUNE 1991-REVISED JANUARY 1993
electrical characteristics over full range of recommended operating conditions
PARAMETER
CMS408
TEST CONDITIONS
MIN
NOM
MAX
UNIT
VOH
High-level output vo~age
10H =-5 mA
VOL
Low-level output voltage
IIL=4.2mA
II
Input current for addresses,
CASx, andW
VI = 0 to 5.25 V, VCC = 5 V,
All other pins = 0 V to VCC
",10
!lA
II
Input current RASx (leakage)
VI = 0 to 5.25 V, VCC = 5 V,
All other pins = 0 V to VCC
",40
J,tA
10
Output current (leakage)
Vo = 0 to Vcc, Vcc = 5.25 V, CASx high
",10
J,tA
2.4
V
V
0.4
electrical characteristics over full range of recommended operating conditions (see Note 3)
PARAMETER
TEST CONDITIONS
ICCI
Read or write cycle current
Minimum cycle, VCC = 5.25 V, Maximum of 2
address transitions per memory cycle. Only one
RAS active any time.
ICC2
Standby current
ICC3
ICC4
CMS408-7
CMS408-8
MIN
MIN
MAX
UNIT
MAX
410
370
mA
After 1 memory cycle, RAS and CAS high. All
other signals stable, VCC = 5.25 V.
9
9
mA
Average refresh current
(RAS only or CSR)
Minimum cycle, VCC = 5.25 V, Maximum of 2
address transitions per memory cycle, RAS
active, CAS high.
410
370
mA
Average page current
tpc = minimum, VCC = 5.25 V, Maximum of 2
address transitions per memory cycle. Only one
RAS active any time, RAS low, CAS cycling.
370
330
mA
NOTE 3. VIH = VCC - 0.2 V and VIL = 0 V for all operating currents.
capacitance over recommended ranges of supply voltage and operating free-air temperature,
f = 1 MHz
PARAMETER
CMS408
MIN
MAX
UNIT
Ci(A)
Input capacitance, address inputs
15
pF
CI(RAS)
Input capacitance, RAS inputs
28
pF
Ci(CAS)
Input capacitance, CAS inputs
15
pF
Ci{Wj
Input capacitance, W input
15
pF
ei(DO)
Input'output capacitance of DO pins
14
pF
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
8-13
CMS405, CMS406 4 MEGABYTE
CMS407, CMS4082 MEGABYTE
DRAM MEMORY CARDS
SMNS405A-JUNE 1991-REVISED JANUARY 1993
A low-power battery-backup refresh mode is available. Data integrity is maintained using CAS-before-RAS
refresh with a period of 125 lAs, holding RAS low for less than 1 !AS. To minimize current consumption, all other
input levels need to be kept stable at CMOS input levels.
All values remain the same as the standard memory card except the following:
PARAMETER
TEST CONDITIONS
CMS40SL
CMS406L
CMS407L
CMS408L
ICC2
Standby current
RAS and CAS high,
VIH = VCC-0.2V, VIL =0 V
All other signals stable at VIH or VIL
SmA
4mA
3mA
2mA
ICC10
Battery backup current
tRC = 125 ~s, tRAS < 1 ~s,
VIH = VCC-0.2V, VIL =0 V
All other signals stable at VIH or VIL
7mA
SmA
4mA
3mA
tREF
Refresh
1024 Cycle
128 ms
128 ms
128 ms
128 ms
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature
PARAMETER
CMS40x-7
CMS40x-S
MIN
MIN
MAX
MAX
UNIT
tCAC
Access time from CAS low
25
27
ns
tCAA
Access time"from column-address
42
47
ns
tRAC
Access time from RAS low
70
80
ns
tCAP
Access time from column precharge
47
52
ns
tCLZ
CAS low to output in low Z
0
tOFF
Output disable time after CAS high (see Note 4)
0
a
25
ns
0
27
ns
NOTE 4: toFF is specified when the output is no longer driven.
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
CMS40x-7
PARAMETER
I
MIN
MAX
CMS40x-S
MIN
MAX
UNIT
tRC
Read cycle time
130
150
ns
!wc
Write cycle time
130
150
ns
tpc
Page mode read or write cycle time (see Note 5)
52
57
ns
tcp
Pulse duration, CAS high
10
10
ns
tCAS
Pulse duration. CAS low
25
tRP
Pulse duration. RAS high
50
tRAS
Pulse duration. RAS low
70
10000
80
10 000
ns
tRASP
Page mode, pulse duration, RAS low
70
100000
80
100 000
ns
tASC
Column address setup time before CAS low
0
0
ns
tASR
Row address setup time before RAS low
7
7
ns
tDS
Data setup time before CAS low
o
o
ns
Continued next page
NOTE 5: To assure tpc min, tASC should be greater than or equal to 5 ns.
TEXAS
~
INSTRUMENTS
8-14
POST OFFICE BOX 1443· HOUSTON. TEXAS 77001
10000
27
10000
60
ns
ns
CMS405, CMS406 4 MEGABYTE
CMS407, CMS408 2 MEGABYTE
DRAM MEMORY CARDS
SMNS40SA--JUNE 1991-REVISED JANUARY 1993
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (concluded)
PARAMETER
CMS40x-7
CMS4Ox-8
MIN
MIN
MAX
MAX
UNIT
tRCS
Read setup time before CAS low
0
0
ns
twcs
W low setup before CAS low
0
0
ns
tCWl
W low setup before CAS high
18
20
ns
tRWl
W low setup before RAS high
25
27
ns
twSR
W high setup (CAS-before-RAS refresh only)
17
17
ns
tCAH
Column address hold time after CAS low
15
15
ns
ns
tRAH
Row address hold time after RAS low
10
12
tAR
Column address hold time after RAS low (see note 6)
55
60
ns
tDH
Data hold time after CAS low
15
15
ns
tDHR
Data hold time after RAS low
55
60
ns
tRCH
Read hold time after CAS high (see Note 7)
0
0
ns
tRRH
Read hold time after RAS high (see Note 7)
0
0
ns
twCH
Write hold time after CAS low
15
15
ns
twCR
Write hold time after RAS low (see Note 6)
55
60
ns
twHR
W high hold time (CAS-before-RAS refresh only)
10
10
ns
tCSH
Delay time, RAS low to CAS high
70
80
ns
tCRP
Delay time, CAS high to RAS low
7
7
ns
IRSH
Delay time, CAS low to RAS high
25
27
tRCD
Delay time, RAS low to CAS low (see Note 8)
20
47
22
53
ns
tRAD
Delay time, RAS low to column address (see Note 8)
15
28
17
33
ns
tRAl
Delay time, column address to RAS high
42
47
ns
tCAl
Delay time, column address to CAS high
35
40
ns
tCHR
Delay time, RAS low to CAS high (see Note 9)
15
20
ns
tCSR
Delay time, CAS low to RAS low (see Note 9)
17
17
ns
tRPC
Delay time, RAS high to CAS low (see Note 9)
0
0
tREF
Refresh time interval (distributed)
tT
Transition time (see Note 10)
NOTES:
6.
7.
8.
9.
10.
16
3
50
3
ns
ns
16
ns
50
ns
The minimum value is measured when tRCD is set to tRCD (min) as a reference.
Either tRCH or tRRH must be satisfied for a read cycle.
Maximum values specified to assure access times.
CAS-before-RAS refresh only.
All cycle times assume If = 5 ns.
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTQN. TEXAS 77001
8-15
CMS405, CMS406 4 MEGABYTE
CMS407, CMS408 2 MEGABYTE
DRAM MEMORY CARDS
SMNS405A~UNE
1991-REVISED JANUARY 1993
TEXAS ~
INsrRUMENTS
8-16
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
CMS409, CMS410 8 MEGABYTE
DRAM MEMORY CARDS
SMNS409A-JULY 1991-REVISED JANUARY 1993
•
Credit Card Size
(85.6 mm x 54 mm x 3.4 mm)
•
•
•
Single 5-V Power Supply (±5% Tolerance)
60-PIN MEMORY CARD
(CONNECTOR VIEW)
Enhanced Page Mode Operation
CMS409 - 4M x 18/1RAS/2CAS
CMS410 - 4M x 16/1RAS/2CAS
2 DO 1
PD2
4 DO 3
VCC
NC
6 DO 5
8 DO 7
10 DO 9
12 DO 11
14 DO 13
AO
NC
•
Operating Temperature
O°C to 55°C
•
•
Standard 60-Pin Two-Piece Connector
•
•
3-State Unlatched Output
•
Performance Ranges:
ACCESS
TIME
tRAC
tCAC
READ
OR WRITE
CYCLE
tRC
70 ns
80 ns
25 ns
27 ns
130 ns
150 ns
W
NC
VSS
NC
DOlO 26 DO 25 VSS
DOll 28 DO 27 D02
VCC 30 DO 29 D03
D012 32 DO 31 D04
D013 34 DO 33 VSS
D014 36 DO 35 D05
VCC 38 DO 37 D06
Low Power Dissipation
ACCESS
TIME
VSS
PDl
Al
16 DO 15 A2
18 DO 17 VSS
NC/D017 20 DO 19 DOS/NC
VCC 22 DO 21 DOO
D09 24 DO 23 DOl
VCC
A3
A4
CMOS Buffered Inputs on All Inputs Except
RASand DQ
CMS4xx-7
CMS4xx-8
PD3
D015 40 DO
D016 42 DO
A5 44 DO
VCC 46 DO
AS 48 DO
description
The CMS409/10 series are dynamic randomaccess memory cards designed to be used as
internal system memory or as external add-on
memory.
A9
NC
The common I/O features of the CMS409/10
dictate the use of early write cycles.
PIN NOMENCLATURE
AO-Al0
CASO, CASl
DOD-D017
PD1-PD5
RASO
VCC
VSS
VIi
NC
TEXAS
50 DO 49 VSS
52 DO 51 RASO
54 DO 53 Al0
NC
VCC 56 DO 55 CASl
PD4 58 DO 57 PD5
NC ·60 DO 59 VSS
These cards have CMOS buffers added to the
CAS, W, and address inputs to minimize loading
caused by the module. RAS and data in/out
remain compatible with Series 74 TTL.
The cards can operate in enhanced page mode.
All address lines and data are latched on chip to
simplify system design. Data out is unlatched to
allow greater system flexibility.
39 DO?
41 VSS
43 CASO
45 A6
47 A?
~
Address Inputs
Column-Address Strobe
Data Inputs/Outputs
Presence Detect
Row-Address Strobe
5-V Power Supply
Ground
Write Enable
No Internal Can nection
Copyright © 1993, Texas Instruments Incorporated
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
8-17
CMS409, CMS410 8 MEGABYTE
DRAM MEMORY CARDS
SMNS409MULY 1991-REVISED JANUARY 1993
operation
The CMS409/1 0 cards are divided into separate banks of memory as shown in the functional block diagrams.
Each bank is selectable using CASx as shown in the table below.
Table 1. Memory Bank Definition
DATA BLOCK
DOG-D07, D08t
009-0016, DQ17t
RAS
CASx
RASO
RASO
CASO
CAS 1
t 008 and 0017 are not available on CMS41 O.
power up
To achieve proper device operation, an initial pause of 200 I-ts followed by a minimum of eight initialization cycles
is required after full Vee level is aChieved. The eight initialization cycles need to include at least one refresh
(RAS-only or CAS-before-RAS) cycle.
specifications
Refresh period is extended to 16 ms. During this period, each of the 1024 rows selected by AO-A9 must be
strobed with RAS to retain data.
memory card components
- Meets JEDEC standard
- UL approved materials
- Plugs into molex connector part number 53213-6011 or equivalent
TEXAS
~
INSTRUMENTS
8·18
POST OFFice BOX 1443 • HOUSTON. TEXAS no01
CMS409, CMS410 8 MEGABYTE
DRAM MEMORY CARDS
SMNS409A...JULY 1991-REVISED JANUARY 1993
CMS409 functional block diagram
RASO
4M x9
4Mx9
AO-A10
~
AO-A10
RAS
-
CAS
, - - CAS
W
DQO-DQ8
RAS
r-
l
W
DQO-DQ8
9
11
DQO-DQ8
AO-A10
9
~ DQ9-DQ17
CAS1
W
CMS410 functional block diagram
RASO
4M x8
4Mx8
AO-A10
-
AO-A10
-
RAS
CAS
-
W
RAS
CAS
- w
DQO-DQ71
DQO-DQ7
8
DQO-DQ7
11
AO-A10
8
~ DQ9-DQ16
CAS1
W
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS n001
8-19
CMS409, CMS410 8 MEGABYTE
DRAM MEMORY CARDS
SMNS409A-JULY 1991-REVISED JANUARY 1993
Table 2. Pin Definition
DEVICE
DQ8/NC (19)
DQ17/NC (20)
CMS409
CMS410
008
NC
0017
NC
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage range on any pin (see Note 1) ................................. -0.5 V to Vee + 0.5 V
Voltage range on Vee .............................................................. -0.5 V to 6 V
Short circuit output current ................................................................ 50 mA
Power dissipation (CMS409) ............................................................... 20 W
Power dissipation (CMS410) ............................................................... 18 W
Operating free-air temperature ........................................................ O°C to 55°C
Storage temperature ............................................................. -40 OCto 85 °C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. This is a stress rating only, and
functional operation olthe device at these or any other conditions beyond those indicated in the "recommended operating conditions" section of
this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliabil~y.
NOTE 1: All voltage values are with respect to VSS.
recommended operating conditions
VCC
Supply voltage
CAS, W, address lines
VIH
High-level input voltage
VIL
Low-level input voltage
(See Note 2)
TA
Operating free-air temperature
MIN
NOM
MAX
UNIT
4.75
5
5.25
V
0.7VCC
RAS and DO lines
2.4
CAS, W, address lines
6.5
0.3VCC
RAS and DO lines
-1
0.8
0
55
°c
NOTE 2: The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used in this data sheet for logic
voltage levels only.
1ExAs
~
INsrRUMENTS
8-20
POST OFFICE BOX 1443· HOUSTON, TEXAS 77001
CMS409, CMS410 8 MEGABYTE
DRAM MEMORY CARDS
SMNS409A-JULY 1991-REVISED JANUARY 1993
electrical characteristics over full range of recommended operating conditions
PARAMETER
CMS409
TEST CONDITIONS
MIN
NOM
MAX
2.4
UNIT
VOH
High-level output voltage
10H =-5 mA
VOL
Low-level output voltage
IIL=4.2mA
V
II
Inpu!..gurrent for addresses, CASx,
andW
VCC = 5 V, VI = 0 to 5.25 V,
All other pins = 0 V to VCC
±10
J.tA
II
Input current RASx (leakage)
VCC = 5 V, VI = 0 to 5.25 V,
All other pins = 0 V to VCC
±180
J.tA
10
Output current (leakage)
VCC = 5.25 V, Vo = 0 to VCC, CASx high
±20
J-lA
V-
0.4
electrical characteristics over full range of recommended operating conditions
PARAMETER
TEST CONDITIONS
ICCl
Read or write cycle current
VCC = 5.25 V, Minimum cycle, Maximum of 2
address transitions per memory cycle (see
Note 3).
ICC2
Standby current
VCC = 5.25 V, After 1 memory cycle, RAS and
CAS high, All other signals stable (see Note 3).
ICC3
Average refresh current
(RAS only or CBR)
ICC4
Average page current
CMS409-7
MIN
CMS409-8
MAX
MIN
MAX
UNIT
1670
1490
mA
37
37
mA
VCC = 5.25 V, Minimum cycle, Maximum of 2
address transitions per memory cycle, RAS
active, CAS high (see Note 3).
1670
1490
mA
VCC = 5.25 V, tpc = minimum, Maximum of 2
address transitions per memory cycle, RAS low,
CAS cycling (see Note 3).
1490
1310
mA
NOTE 3: VIH = VCC - 0.2 V and VIL = 0 V for all operating currents.
capacitance over recommended ranges of supply voltage and operating free-air temperature,
f = 1 MHz
CMS409
PARAMETER
MIN
MAX
UNIT
15
pF
126
pF
Ci(A)
Input capacitance, address inputs
Ci(RAS)
Input capacnance, RAS inputs
Ci(CAS)
Input capacitance, CAS inputs
15
pF
Ci(W)
Input capacitance, W input
15
pF
Ci(DO)
InpuVoutput capacitance of DO pins
14
pF
TEXAS ."
INSlRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
8-21
CMS409, CMS41 0 8 MEGABYTE
DRAM MEMORY CARDS
SMNS409A-JULY 1991-REVISED JANUARY 1993
electrical characteristics overfull range of recommended operating conditions
PARAMETER
CMS41 0
TEST CONDITIONS
VOH
High-level output voltage
IOH=-5mA
VOL
Low-level output voltage
IIL=4.2mA
II
Inpu!2urrent for addresses, CASx,
andW
II
10
MIN
NOM
MAX
UNIT
2.4
V
VCC = 5 V, VI = 0 to 5.25 V,
All other pins = 0 V to VCC
",10
IlA
Input current RASx (leakage)
VCC = 5 V, VI = 0 to 5.25 V,
All other pins = 0 Vto VCC
",160
IlA
Output current (leakage)
VCC = 5.25 V, Vo = 0 to VCC, CASx high
",20
IlA
0.4
V
electrical characteristics over full range of recommended operating conditions
PARAMETER
CMS41 0-7
TEST CONDITIONS
MIN
CMS410-S
MAX
MIN
MAX
UNIT
ICCl
Read or write cycle current
Vce = 5.25 V, Minimum cycle, Maximum of 2
address transnions per memory cycle (see
Note 3).
1490
1330
mA
ICC2
Standby current
VCC = 5.25 V After 1 memory cycle, RAS and
CAS high. All other signals stable, (see Note 3).
33
33
mA
leC3
Average refresh current
(RAS only or CBR)
VCC = 5.25 V, Minimum cycle, Maximum of 2
address transitions per memory cycle, RAS
active, CAS high (see Note 3).
1490
1330
mA
leC4
Average page current
VCC 5.25 V, tpc minimum, Maximum of 2
address transitions per memory cycle, RAS low,
CAS cycling (see Note 3).
1330
1170
mA
=
=
NOTE 3: VIH = VCC - 0.2 V and VIL = 0 V for all operating currents.
capacitance over recommended ranges of supply voltage and operating free-air temperature,
f = 1 MHz
CMS410
PARAMETER
MIN
MAX
UNIT
Ci(A)
Input capacitance, address inputs
15
pF
Ci(RAS)
Input capacitance, RAS inputs
112
pF
Ci(CAS)
Input capacitance, CAS inputs
15
pF
Ci(W)
Input capacitance, W input
15
pF
Ci(DO)
InpuVoutput capacitance of DO pins
14
pF
TEXAS
~
INsrRUMENTS
8-22
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
CMS409, CMS410 8 MEGABYTE
DRAM MEMORY CARDS
SMNS409A~ULY
1991-REVISED JANUARY 1993
A low-power, battery-backup refresh mode is available. Data integrity is maintained using CAS-before-RAS
refresh with a period of125 /!s, while holding RAS low for less than 1 /!s. To minimize current consumption, all
other input levels need to be kept stable at CMOS input levels.
All values remain the same as the standard memory card except those listed in the following table:
PARAMETER
TEST CONDITIONS
CMS409L
CMS410L
7mA
SmA
ICC2
Standby current
RAS and CAS high, VIH = VCC -0.2, V, VIL = 0 V
All other signals stable at VIH or VIL
ICC10
Battery backup current
tRC = 125 !'S, tRAS < 1 !'S,
VIH = VCc--O.2 V, VIL = 0 V
All other signals stable at VIH or VIL
10mA
9mA
tREF
Refresh
1024 cycle
128ms
128ms
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature
CMS4xx-7
PARAMETER
MIN
CMS4xx-S
MAX
MIN
UNIT
MAX
tCAC
Access time from CAS low
25
27
ns
tCM
Access time from column-address
42
47
ns
tRAC
Access time from RAS low
70
80
ns
teAP
Access time form column precharge
47
52
ns
teLZ
CAS low to output in low Z
0
tOFF
Output disable time after CAS high (see Note 4)
0
ns
0
25
0
27
ns
NOTE 4: tOFF is specified when the output is no longer driven.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
8-23
CMS409, CMS410 8 MEGABYTE
DRAM MEMORY CARDS
SMNS409A-JULY 1991-REVISED JANUARY 1993
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
CMS4xx-7
PARAMETER
MIN
130
130
52
10
25
50
70
70
CMS4xx-8
MAX
MIN
150
150
57
10
27
60
80
80
MAX
tRC
Read cycle time
twc
Write cycle time
tpc
Page mode read or write cycle time (see Note 5)
tcp
Pulse duration, CAS high
tCAS
Pulse duration, CAS low
tRP
Pulse duration, RAS hi9h
tRAS
Pulse duration, RAS low
tRASP
Page mode, pulse duration, RAS low
tASC
Column address setup time before CAS low
a
a
tASR
Row address setup time before RAS low
7
7
ns
tDS
Data setup time before CAS low
a
a
ns
10 000
10 000
100 000
ns
ns
ns
ns
10 000
ns
ns
10000
100 000
ns
ns
ns
tRCS
Read setup time before CAS low
0
0
ns
twcs
W-Iow setup before CAS low
a
a
ns
tCWl
W-Iow setup before CAS high
W-Iow setup before RAS high
18
25
twSR
W-high setup (CAS-before-RAS refresh only)
17
tCAH
Column address hold time after CAS low
tRAH
Row address hold time after RAS low
tAR
Column address hold time after RAS low (see note 6)
tDH
Data hold time after CAS low
tDHR
Data hold time after RAS low
tRCH
Read hold time after CAS high (see Nole 7)
15
10
55
15
55
0
20
27
17
15
10
60
15
60
ns
tRWl
ns
tRRH
Read hold lime after RAS high (see Nole 7)
a
a
a
twCH
Wrile hold lime after CAS low
twCR
twHR
W-high hold lime (CAS-before-RAS refresh only)
ICSH
Delay lime, RAS low 10 CAS high
ICRP
Delay lime, CAS high 10 RAS low
IRSH
Delay lime, CAS low 10 RAS high
IRCD
Delay lime, RAS low 10 CAS low (see Note 8)
IRAD
Delay lime, RAS low 10 column address (see Nole 8)
IRAl
Delay lime, column address 10 RAS high
ICAl
Delay lime, column address 10 CAS high
tCHR
Delay lime, RAS low 10 CAS high (see Nole 9)
ICSR
Delay lime, CAS low 10 RAS low (see Nole 9)
IRPC
Delay time, RAS high 10 CAS low (see Nole 9)
15
60
10
80
7
27
22
15
47
40
20
17
0
ns
Write hold time after RAS low (see Nole 6)
15
55
10
70
7
25
20
15
42
35
15
17
0
IREF
Refresh lime inlerval
IT
Transilion lime (see Note 10)
NOTES:
3
5.
6.
7.
8.
9.
To assure tpc min, IASC should be grealer Ihan or equal 10 5 ns ..
The minimum value is measured when IRCD is sel 10 IRCD(min) as a reference.
Eilher IRCH or IRRH musl be salisfied for a read cycle.
Maximum values specified 10 assure access limes.
CAS-before-RAS refresh only.
10. All cycle times assume IT = 5 ns.
TEXAS ~
INSTRUMENTS
8-24
POST OFFICE BOX 1443· HOUSTON, TEXAS 77001
47
28
16
50
3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
53
33
ns
ns
ns
ns
ns
ns
ns
16
ns
50
ns
CMS409, CMS410 8 MEGABYTE
DRAM MEMORY CARDS
SMNS409A-JULY 1991-REVISED JANUARY 1993
TI memory card nomenclature
CM
2XX
S = Standard
C = Custom
-xx
2=OTP
4= DRAM
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
8-25
CMS409, CMS41 0 8 MEGABYTE
DRAM MEMORY CARDS
SMNS409A-JULY 1991-REVISED JANUARY 1993
1ExAs . "
INSfRUMENTS
8-26
POST OFFICE BOX 1443· HOUSTON, TEXAS 77001
CMS88D8MB36 8·MEGABYTE
CMS88D4MB36 4·MEGABYTE
DRAM MEMORY CARDS
SMNS421 B-NOVEMBER 1991-REVISEO JANUARY 1993
•
Credit Card Size
(85.6 mm x 54 mm x 3.4 mm)
•
•
•
Single 5-V Power Supply (±5% Tolerance)
88-PIN MEMORY CARD
(CONNECTOR VIEW)
Enhanced Page Mode Operation
GNO
000
CMS88D8MB36 - 2M x 36/4RAS/4CAS
CMS88D4MB36 - 1 M x 36/2RAS/4CAS
•
Operating Temperature ... O°C to 55°C
•
Standard 88-Pln Two-Piece Connector
•
CMOS Buffered Inputs on All Inputs Except
RAS and DQ
•
•
001
002
003
004
005
006
Performance Ranges:
ACCESS
TIME
ACCESS
TIME
IRAC
ICAC
READ
OR WRITE
CYCLE
IRC
70
80
70
80
25 ns
27 ns
25 ns
27 ns
130 ns
150 ns
130 ns
150 ns
ns
ns
ns
ns
The CMS88D8MB36 and CMS88D4MB36 series
are dynamic random-access memory cards
designed to be used as internal system memory or
as external add-on memory.
The cards can operate in enhanced page mode.
All address lines and data are latched on chip to
simplify system design. Data out is unlatched to
allow greater system flexibility.
The common I/O features of the CMS88D8MB36
and CMS88D4MB36 dictate the use of early write
cycles.
PIN NOMENCLATURE
NC
5
6
7
8
CASl 24 0 0
NC 25 0 0
RAS2 26 0 0
Vee 27 0 0
P02 28 0 0
P04 29 0 0
P06 30 0 0
NC 31 0 0
NC 32 0 0
0017 33 0 0
009 34 0 0
NC 35 0 0
0010 36 DO
Vee 37 DO
0011 38 DO
0012 39 0 0
0013 40 DO
0014 41 DO
0015 42 0 0
0016 43 0 0
GNO 44 DO
These cards have CMOS buffers added to the
CAS, W, and address inputs to minimize loading
caused by the module. RAS and data in/out
remain compatible with Series 74 TTL.
W
3
4
AO 13 0 0
A2 14 DO
VCC 15 0 0
A4 16 DO
NC 17 DO
A6 18 DO
A8 19 0 0
NC 20 DO
NC 21 0 0
RASO 22 0 0
CASO 23 DO
description
AO-A9
CASO-CAS3
000-0035
PD1-P08
RASQ.-RAS3
VCC
VSS
45
46
0 0 47
0 0 48
0 0 49
0 0 50
DO 51
DO 52
VCC 9 DO 53
007 10 DO 54
NC 11 DO
55
008 12 DO
3-State Unlatched Output
CMS88D8MB36-7
eMS88D8MB36-8
CMS88D4MB36-7
CMS88D4MB36-8
1 0 0
2 DO
Address Inputs
Column-Address Strobe
Data Inputs/Outputs
Presence Detect
Row-Address Strobe
5-V Power Supply
Ground
Write Enable
No Internal Connection
TEXAS
~
56
57
58
59
60
61
62
63
64
65
66
GNO
0018
0019
0020
0021
0022
0023
0024
0025
0026
NC
GNO
Al
A3
A5
A7
A9
NC
GNO
NC
RAS1{NC
CAS2
z
o
~
::2:
IX
ou.
z
GNO
CAS3
69 RAS3{NC
67
68
70
w
(,)
Vii
z
71 POl
72 P03
73 GNO
~
c
74 P05
«
75 P07
76 PD8
77 NC
78 NC
79
80
0035
0027
81
82
83
0028
0029
0030
0031
0032
0033
0034
GNO
84
85
86
87
88
Copyright © 1993. Texas Instruments Incorporated
INSTRUMENTS
POST OFFICE BOX 1443· HOUSTON. TEXAS 77001
8-27
CMS88D8MB36 8·MEGABYTE
CMS88D4MB364·MEGABYTE
DRAM MEMORY CARDS
SMNS421B-NOVEMBER 1991-REVISED JANUARY 1993
operation
The CMS88D8MB36 and CMS88D4MB36 cards are divided into separate banks of memory. Each bank is
selectable using RASx and CASx as shown in the table below. RASO-RAS3 control which side of the DRAM
banks are connected to the memory card DO pins. Therefore, only two RAS signals may be active during any
read or write cycle.
Table 1. Memory Bank Definition
RASx
DATA BLOCK
»c
z~
o
m
-"T1z
o
Side 2
Side 1
Slde2
000-008
RASO
RAS1
CASO
CASO
009-0017
RASO
RAS1
CAS 1
CAS1
0018-0026
RAS2
RAS3
CAS2
CAS2
0027-0035
RAS2
RAS3
CAS3
CAS3
power up
To achieve proper device operation, an initial pause of 200 lAs followed by a minimum of eight initialization cycles
is required after full Vee level is achieved. The eight initialization cycles need to include at least one refresh
(RAS-only or CAS-before-RAS) cycle.
specifications
Refresh period is extended to 16 ms. During this period, each of the 1024 rows must be strobed with RAS to
retain data.
memory card components
- Meets JEDEC standard
II
- UL approved materials
3:
-o~
z
CASx
Side 1
Table 2. Pin Definition for Presence Detect
DEVICE
REFRESH CYClEt
SPEEDt
CONFIGURATION
PD1(71)
PD2(28)
P03(72)
P04(29)
P05(74)
CMS8808MB36
Vss
NC
VSS
VSS
Vss
CMS8804MB36
VSS
NC
VSS
VSS
NC
P06 (30)
P07 (75)
-70 ns
VSS
NC
SLOW
NC
-SOns
NC
VSS
SELF
VSS
t Applies to both CMS8808MB36 and CMS8804MB36 devices.
Table 3. Pin Definition
DEVICE
RAS1/NC (65)
RAS3/NC (69)
CMS8808MB36
RAS1
RAS3
CMS8804MB36
NC
NC
TEXAS
~
INsrRUMENTS
8-28
POST OFFICE BOX 1443· HOUSTON, TEXAS 77001
POS (76)
CMSBBDBMB368-MEGABYTE
CMSB8D4MB364-MEGABYTE
DRAM MEMORY CARDS
SMNS421 B-NOVEMBER 1991-REVISED JANUARY 1993
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage range on any pin (see Note 1) ................................. -0.5 Vto Vee + 0.5 V
Voltage range on Vee .............................................................. -0.5 V to 6 V
Short circuit output current ................................................................ 50 mA
Power dissipation (CMS8D8MB36) .......................................................... 22 W
Power dissipation (CMS8D4MB36) .......................................................... 11 W
Operating free-air temperature ........................................................ DoC to 55°C
Storage temperature range ........................................................ -40 OCto 85 °C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maxi mum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to VSS.
recommended operating conditions
VCC
Supply voltage
CAS, W, address lines
VIH
High-level input voltage
VIL
Low-level input voltage
(see Note 2)
TA
Operating free air temperature
MIN
NOM
MAX
UNIT
4.75
5
5.25
V
0.7 VCC
RAS and DO lines
2.4
6.5
CAS, W, address lines
0.3 VCC
RAS and DO lines
0.8
-1
..
NOTE 2: The algebraic convention, where the more negative (less positive) limit is designated as minimUm,
voltage levels only.
55
0
IS
used
In
V
V
°c
this data sheet for logic
z
o
~
:E
a:
ou.
z
w
()
z
c~
}
I
Output Valid
VIH
VIH
HI·Z VIL
Figure 3. Attribute Memory Read Cycle Timing
4- - - Verify
~
z
o
14-1
~~
----I'A-,"'--__
~
A ftA19 _ _ _
p_ro_gr_am_-_
-_-_-_....
______
Addres;Stable
m
1
-z
~!4----t~1f--
0G-07
08-015
0G-015
."
o
:c
s::
~-I-n
- - - - - - ( I o -_ _
08...
1
I
-o~
z
----.!~
tsu(A)
~X
Address N + 1 :::
I
14
I~
I
I
I
---«,..._O_tT"i:_,~_u_t
S_t_8b_le_-"4;>---+:
_)>------
I
I
I
(II
.1 tdls(G)t
I
I
I
14
~
tsu(O)
I
I
I
I
---~I----~-~---~-.I---------71
i
I
I
i
I
I
1+14--t~oj- tsu(VPP) I
II
II
_ _ _ _..J
1
I
-----'
~
1
I
I
I
I
I
I
I
I
I
:
I+--
tsu(E)
-----+I
-.j
1
I
VIH
I
I
I
I
I
I
VIL
tSU(G)!
I
I:
I
~
I 14
1
.1
ten(G) t
t tdis(G) and ten(G) are characteristics of the device but must be accommodated by the programmer,
*Vpp ~ 13 V and Vee ~ 6.5 V for SNAPI Pulse programming,
Figure 4. Program Cycle Timing (SNAPI Pulse Programming)
~
INSfRUMENTS
POST OFFICE BOX 1443· HOUSTON, TEXAS 77001
VIH
VIL
,1 _ _ _ _ _ _ _ __
~,...I------"'1/"
TEXAS
VCc*
Vcc
I
I
I+- th(O)
'\
I' :4
'\...-J
tw(PGM) \4
.1
PP
Vcc
I
I
I+~--t~of- tsu(VCC) I
!I \ .
V
I
rl--r-----rl--~I--------------; :--+I---I
I
I
I
VCC
::::~
I
I!
Vpp
8-42
th(A)
:::
CMS68P256, CMS68P512, CMS68P1MB
ONE TIME PROGRAMMABLE
READ·ONLY MEMORY MEMORY CARDS
SMNS201 E~UNE 1992-REVISED DECEMBER 1992
PARAMETER MEASUREMENT INFORMATION
Vee
=6.5 V ± 0.25 V, Vpp =13 V ± 0.25 V
Program One Pulse
=tw =100 fis
Increment Address
l
Program
Mode
z
o!;:
~
a:
0
Interactive
Mode
LL
Z
W
o
Z
~
c
Vee = Vpp = 5 V ±0.5 V
oJ
~
talax
1,.-
I
~
(aee Nota A)
~
_
II
I
-./
I
I
I
II+-
-.II
I
'""'--~ I
~ If- tghel
I
I
I
I
I
I I
I
I
D~:' .r HI-Z K~a!~~n)
5V
VCC-./
OV./
12V
I
II
Itt
I J
~ avav(rc) ~
\
!4---+t- tahwh
~tWI~1
'L'---j",,1---!-I---\'',-'---~V
)r
I
I
I
I
I
i++I
)j
I
I
I
I
I
II
II
teleh
-t,
tahdx
.... " ' - '
... - ldV!,h
e-
HI-Z
!h
!Vi \..
I
19lqv(toe>
,••
tahaz(toh)
I
I:
-+\1+-1I
tglqx(tolzl
I
~ I+--
Valid Data Out
---i::;:71
-<~a~~~'j
I
I
J'
I
I
~»:h.
~~~~
14--* talqv(toa)
II
II
:
)j
)j
,_
~
,..---tvpel
I ~ _ _ _ _ _ _ _ _ _ _ _~f(,~ _ _ _ _ _ _ _~rr~ _ _ _ _ _~
VPP - VPPL
!
~
I
taleh
I ~L
I ,... ~ ...hdx
-.I-ldveh
I",
~
I
I
,~fl
I
I
f4-t
I
I
~
I
V)
I I
I H-I
I
tehdx
Vorl......
I
I
I
I
I
I
~
~ taheh ~
I"
I
'4------ tahgl
II
-t,
ldveh
I
I
...
..vav ------.,
I
I
I
I
: :4
14-
I
I
I
~I"'" teleh
~
14-- tahwh
I
I
L..,,..l
I
~L
a
StandbyNCC
)'
~j
I
I
~}»(
,...
~ 14- twlel
tahel
....
Program
~
I
:Z
/
+.:
tavel
talax
twlel-t, 1
I
tahwh ~
I
I
I
I
OE
Wi~
I
I
I
I
t
(t.\ ~I
avav WCl I
!.4
I
I
I
CE
Program
Verify
)j
)j
\
\.
,
'----
NOTE A: CE refers to CEl and CE2.
Figure 6. Write Operations Timing
TEXAS ."
INSfRUMENTS
POST OFFICE BOX 1443' HOUSTON. TEXAS 77001
8-63
CMS68F256, CMS68F512
CMS68F1 MB, CMS68F2MB
FLASH MEMORY CARDS
SMNS301A-NOVEMBER 1992
TEXAS ~
INSTRUMENTS
8-64
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
CMS209, CMS210, CMS212,
CMS213, CMS214, CMS216
CMOS OlP PROM MEMORY CARDS
1993
•
Card Size (85 mm x 54 mm x 3.6 mm)
•
•
•
Organization ... From 64K x 8 to 256K x 16
50-PIN MEMORY CARD
(CONNECTOR VIEW)
Single 5-V Power Supply (Read Mode)
Utilizes QFP (Quad Flat Package) CMOS
OTP PROMs (One Time Progammable
Read·Only Memories)
1
NC
NC
3
A12
A7
5
7
A6 9
A5 11
A4 13
•
•
8·Blt or 16-Blt Data Width
•
Operating Free·Air Temperature Range
O°C to 55°C
•
Standard 60·Pln Two-Piece Connector With
Orientation Guide Allows Memory
Technology/Capacity Upgrade/Downgrade
Low Power Dissipation
A3 15
A2 17
19
AO 21
DO 23
01 25
02 27
Al
•
All Inputs/Outputs and Clocks are Fully TTL
Compatible
•
3-State Output
•
Performance Ranges:
CMS2xx-200 200 ns Access Time (Max)
CMS2xx-250 250 ns Access Time (Max)
GNO 29
03 31
04
05
06
07
37
39
CE 41
Al0 43
OENpp 45
All 47
A9 49
description
The CMS2xx series are TI standard Memory
Cards designed to be used either as an internal
memory system or as an external add-on memory.
These cards are offered with densities of 512K to
4 Megabit, one time electrically programmable
read-only memories organized from 65 536 x 8
bits to 262 144 x 16 bits in a standard card
package. A card is comprised of from 1 to 8
TMS27PC512s in 44-lead plastic quad flat
packages (QFP) and one decoder in a 16-pin
small outline package (SOP) mounted on top of
the substrate together with three 0.1 J.lF
decoupling capacitors.
The TMS27PC512 is described in the
TMS27PC512 data sheet and is electrically tested
and processed according to Tl's MIL-STD-8838
(as amended for commercial applications) flows
prior to assembly.
33
35
00 2
00 4
00 6
00 8
NC
NC
COl
A15
00 10 A16
00 12 A17
00 14 NC
00 16 NC
00 18 NC
00 20 NC
00 22 NC
00 24 08
00 26 09
00 28 010
00 30 GNO
00 32 GNO
00 34 011
00 36 012
00 38 013
00 40 014
00 42 015
00 44 NC
00 46 NC
00 48 NC
00 50 NC
A8 51
A13 53
A14 55
NC 57
00 52 NC
00 54 NC
00 56 NC
00 58 CD2
VCC 59
00 60 VCC
PIN NOMENCLATURE
AO-A17
DO-D15
CE
OE/Vpp
CD1,CD2
GND
VCC
NC
Address Inputt
Data Output:!:
Card Enable
Output Enable/Programming Voltage
Card Detect
Ground
5-V Power Supply
No Connection
t Address signal A17 (pin12) is not connected forCMS209/213 and
CMS210/214cards. AddressSignalA16 (pin 10) is not connected
for CMS209/213 cards.
:!: Data out signals D8-D15 are not connected for all memory cards
CMS213/214/216 organized by 8.
TEXAS
..If
Copyright © 1993, Texas Instruments Incorporated
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
8-65
CMS209, CMS210, CMS212,
CMS213, CMS214, CMS216
CMOS OlP PROM MEMORY CARDS
SMNS209A.,JUNE 1991-REVISED JANUARY 1993
PRODUCT LIST
MEMORY CAPACITY (KB)
ORGANIZATION
ACCESS TIME (ns)
CONNECTOR TYPE
CMS209
128
64K x 16
200/250
Two-piece 60-pin
CMS210
256
128K x 16
200/250
Two-piece 60-pin
CMS212
512
256K x 16
200/250
Two-piece 60-pin
CMS213
64
64Kx8
200/250
Two-piece 60-pin
CMS214
128
128K x 8
200/250
Two-piece 60-pin
CMS216
256
256Kx 8
200/250
Two-piece 60-pin
operation
The CMS2xx series operates as an array of TMS27PC512s and one decoder connected as shown in the
functional block diagrams. The most significant address lines A 16 and A 17 are used to select one of the four
possible device pairs. There are seven modes of operation listed in the following table.
programming
The CMS2xx series can be programmed using the TI SNAP! Pulse programming algorithm; refer to the TI
TMS27PC512 data sheet for details of its operation.
MODE
FUNCTION
READ
OUTPUT
DISABLE
STANDBY
PROGRAMMING
VERIFY
PROGRAMMING
INHIBIT
SIGNATURE MODE
VIL
CE
VIL
VIL
VIH
VIL
VIL
VIH
OElVpp
VIL
VIH
X
Vpp
VIL
Vpp
VIL
VCC
VCC
Vce
VCC
VCC
VCC
VCC
VCC
A9
xt
X
X
X
X
X
X
VH:j:
VH
X
X
X
X
AO
X
VIL
VIH
00-07
Data Out
HI-Z
HI-Z
Data In
Data Out
HI-Z
MFG
DEVICE
97
85
97
85
CODE
08-015
Data Out
HI-Z
HI-Z
Data In
Data Out
t X can be VIL or VIH.
:j: VH = 12 V '" 0.5 V.
Refer to the appropriate TMS27PC512 data sheet for details of its operation.
This card has a device recognition mode.
TEXAS ~
INSTRUMENTS
8-66
POST OFFICE BOX 1443 • HOUSTON. TEXAS n001
HI-Z
CMS209, CMS210, CMS212,
CMS213, CMS214, CMS216
CMOS OlP PROM MEMORY CARDS
SMNS209A-JUNE 1991-REVISED JANUARY 1993
absolute maximum ratings over operating free-air temperature (unless otherwise noted)§
Supply voltage range, Vee (see Note 1) .............................................. -0.5 V to 7 V
Supply voltage range, Vpp (see Note 1) ............................................. -0.5 V to 14 V
Input voltage range (see Note 1): All inputs except A9 ................................ -0.5 V to 6.5 V
A9 ................................ -0.5Vto 13.5 V
Output voltage range (see Note 1) .................................................. -0.5 V to Vee
Operating free-air temperature range .................................................. O°C to 55°C
Storage temperature range ......................................................... -40°C to 70°C
Connector insertion cycle .................................................................. 5000
§ Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. This is a stress rating only, and
functional operation of the device at these or any other conditions beyond those indicated in the "recommended operating conditions" section
of this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: Under absolute maximum ratings, voltage values are with respect to GND.
recommended operating conditions
Vee
Supply voltage
OE/Vpp
Supply voltage
MIN
NOM
MAX
UNIT
Read mode (see Note 2)
4.75
5
5.25
V
Fast programming algorithm
5.75
6
6.25
V
SNAPI Pulse programming algorithm
6.25
6.5
6.75
V
12
12.5
13
12.75
13.0
13.25
Fast programming algorithm
SNAP! Pulse'programming algorithm
V
VIH
High-level input voltage
2
Vee
VIL
Low-level input voltage
0
0.8
V
V
TA
Operating free-air temperature
0
55
'e
NOTE 2: Vee must be applied before or at the same time as OE/Vpp and removed after or at the same time as OE/Vpp.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
8-67
CMS209, CMS210, CMS212,
CMS213, CMS214, CMS216
CMOS OTP PROM MEMORY CARDS
SMNS209A-JUNE 1991-REVISED JANUARY 1993
electrical characteristics over full range of recommended operating conditions
PARAMETER
TEST CONDITIONS
MIN
MAx
High-level output voltage
IOH =-400 rnA
VOL
low-level output voltage
IOl=2.l rnA
0.45
V
II
Input current (leakage)
VI = Oto5.5V
±10
jJA
IOZH
High-level output current (leakage)
All address inputs, CE or OE = VIH, Vo = VCC
+10
jJA
IOZl
low-level output current (leakage)
CE or OE = VIH, Vo = 0 V
-10
jJA
Ipp
OE /Vpp supply current
(during program pulse)
ICC1
VCC supply current
(standby)
PARAMETER
TEST CONDITIONS
Vpp = 13V
CMS209
CMS210
CMS212
UNIT
100
100
100
rnA
CE =VIH
VCC=5.5V
8
16
32
rnA
I CMOS-input level
CE =VCC
VCC = 5.5V
7
14
28
rnA
VCC = 5.5 V, CE = VIL,
tcycle = minimum cycle time,
outputs open, address not
complemented
100
100
100
rnA
TEST CONDITIONS
CMS213
CMS214
CMS216
UNIT
50
50
50
rnA
VCC supply current (active)
Ipp
OE /Vpp supply current
(during program pulse)
ICC1
VCC supply current
(standby)
PARAMETER
Vpp = l3V
ITTL-input level
ICMOS-input level
VCC supply current (active)
CE=VIH
VCC = 5.5V
4
8
16
rnA
CE =VCC
VCC = 5.5V
3.5
7
14
rnA
50
50
50
rnA
VCC = 5.5 V, CE = Vll,
tcycle = minimum cycle
time, outputs
open, address not
complemented
TEXAS
~
INSTRUMENTS
8-68
V
ITTL-input level
ICC2
ICC2
2.4
UNIT
VOH
POST OFFICE BOX 1443· HOUSTON. TEXAS 77001
CMS209, CMS210, CMS212,
CMS213, CMS214, CMS216
CMOS OlP PROM MEMORY CARDS
SMNS209A~UNE
1991-REVISED JANUARY 1993
switching characteristics over full ranges of recommended operating conditions (see Notes 3
and 4)
TEST CONDITIONS
(SEE NOTES 3 AND 4)
PARAMETER
CMS2xx-200
MIN
MAX
CMS2xx-250
MIN
MAX
UNIT
talA)
Access time from address
200
250
ns
t(CE)
Access time from chip enable
200
250
ns
75
120
ns
80
ns
Ien(OENPP) Output enable time from OE /Vpp
!dis
Output disable time from OE /Vpp or CE,
whichever occurs firstt
tv(A)
Output data valid time after change of
address, CE or OE /Vpp, whichever
occurs firstt
CL = 100 PF,
1 Series 74 TTL load,
Input tr " 20 ns,
Input tf " 20 ns
0
0
80
0
0
ns
t Value calculated from 0.5 V delta to measured output level. This parameter is only sampled and not 100% tested.
NOTES: 3. For all switching characteristics the input pulse levels are 0.4 V to 2.4 V. liming measurements are made at 2 V for logic high and
0.8 V for logic low.
4. Common test conditions apply for the tdis except during programming.
capacitance over recommended ranges of supply voltage and operating free-air temperature
f = 1 MHz:!:
PARAMETER
TEST CONDITIONS
CMS213
CI
Input capacitance
CMS210
20
VI =OV
f= 1 MHz
TA = 25°C
40
CMS212
80
CMS213
25
CMS209
CI(OE/VPP)
Co
*
Input capacitance, output
enable/programming voltage
Output capacitance
20
40
CMS216
CMS214
CMS210
50
100
100
CMS212
200
CMS213
15
CMS209
15
CMS210
pF
50
VI =OV
f = 1 MHz
TA = 25°C
CMS216
CMS214
UNIT
10
CMS209
CMS214
MAX
VO=OV
f = 1 MHz
TA = 25°C
30
30
CMS216
60
CMS212
60
pF
pF
Capacitance measurements are made on sample basis only.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 1443' HOUSTON. TEXAS 77001
8-69
CMS209, CMS210, CMS212,
CMS213, CMS214, CMS216
CMOS OTP PROM MEMORY CARDS
SMNS209A-JUNE 1991-REVISED JANUARY 1993
functional block diagram
CMS209/CMS213
21
AO
19
Al
17
A2
15
A3
13
A4
11
AS
9
A6
7
A7
51
A8
49
A9
43
Al0
47
All
5
A12
53
A13
55
A14
8
A15
A16 _1_0_ NC
A17 _1_2_ NC
45
OE/Vpp
COl
C02
23
25
27
31
33
35
37
39
~
~
~
34
r36
~
rfo""
~
r-=-
6
L-....--- AO-A15
VSS
59,60
29,30,32
L....,- AO-A15
OE/Vpp
41
VCC
16
16
~
E
+. . +
C1
...
C2
00-07
P--
-
M1
64Kx8
VCC
VSS
1
E
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443· HOUSTON. TEXAS 77001
08-015
M2t
64Kx8
VSS
VCC
I
O.lI-lF
t Memory device M2 is used for CMS209 only.
8·70
2 E / Vpp
r-L
00
01
02
03
04
05
06
07
08
09
010
011
012
013
014
015
CMS209, CMS210, CMS212,
CMS213, CMS214, CMS216
CMOS OTP PROM MEMORY CARDS
SMNS209A-JUNE 1991-REVISED JANUARY 1993
functional block diagram
CMS210/CMS214
AO
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
21
19
17
15
13
11
9
7
51
49
23
25
27
31
33
35
37
39
24
00
01
02
03
04
05
06
07
08
~
V"---28 09
010
~ 011
012
v---4Q 013
014
V-- 015
43
47
5
53
55
8
v----as
v-----aa
v----42
A17_1_2_NC
/Vpp
45
6
C01~
16
16
CO2
AO--A15
OE/Vpp
Address Oecoder
HCT139
1YO
A16,~ 1A
1Y1
- 2A
1Y2
I - 18
1Y3
I - 28
2YO
2Y1
~1G
2Y2
2Y3
2G
I
-
VCC
GNO
'"
E
8
00--07 ~
~ AO--A15
..-+--;::-
I
16
L-...- AO--A15
OE/Vpp
r--
E
8
00--07 '---'.--
59,60
Vs S
29,30,32
+?< +
1
C5 0.1
08-015
8
~
I
16
L....>,-
-
M3
64Kx8
VCC
VSS
Vc C
E
M2t
64Kx8
VCC
VSS
M1
64Kx8
VCC
VSS
~
-
OE/Vpp
~F
AO--A15
OE/Vpp
E
8
08-015 '---'.--
M4t
64K x8
VCC
VSS
I
t Memory devices M2 and M4 are used for CMS21 0 only.
TEXAS ~
INSIRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
8·71
CMS209,CMS210, CMS212,
CMS213, CMS214,CMS216
CMOS OlP PROM MEMORY CARDS
SMNS209A-JUNE 1991-REVISED JANUARY 1993
functional block diagram
CMS212/CMS216
AO
Al
A2
A3
A4
AS
A6
A7
A8
A9
Al0
All
A12
A13
A14
A15
E/Vpp
21
19
17
15
13
11
9
7
51
49
43
47
5
53
55
8
23
25
27
31
33
35
37
39
~
26
V"-28
V34
v-----as-
v-----aa
Ir40
v--42
v-----=--
45
6
C01~
CO2
Address Decoder
HCT139
lYO A16,~ lA
1Yl 2A
1Y2 A17 .!!- 18
1Y3
28
2YO
2Yl
~ - lG
2Y2
2Y3
2G
GNO
VCC
16
16
AO-A15
OE/Vpp
,..., E
I
8
E
00-07 ~
08-015
VSS
VCC
VCC
E
"
-
~
8
00-07 ~
t-.... E
VCC
E
~
S
00-07 ~
t----;:::
---
E
08-015
VCC
VSS
I
I
16
16
AO-A15
OE/Vpp
8
DO-07
----'<- AO-A15
' - - - OE/Vpp
f---'.-
" E
MSt
64Kx8
VSS
VCC
VcC
Vs S
29,30,32
+:~1: +
VCC
I
1
C9
0.1 I'F
t Memory devices M2. M4. M6 and MB are used for CMS212 only.
TEXAS
..If
INSTRUMENTS
8-72
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
S
08-015
M7
64Kx8
59,60
~
M6t
64Kx8
VSS
E
I
AO-A15
OE/Vpp
M5
64Kx8
VCC
VSS
I
16
16
"-
8
08-015 ~
M4t
64KxS
VSS
AO-A15
OE/Vpp
I
AO-A15
OE/Vpp
M3
64Kx8
VCC
VSS
I
16
16
AO-A15
OE/Vpp
8
f---'.---<
M2t
64KxS
Ml
64Kx8
-
.-
AO-A15
t - - OE/Vpp
~
VSS
DO
01
02
03
04
05
06
07
08
09
010
011
012
013
014
015
Military Products
9-1
Contents
CHAPTER 9.
MILITARY PRODUCTS
Military Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • .. 9-3
DYNAMIC RAMS
SMJ44C256
1 048 576-bit
(256K x 4) Enhanced Page Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 9-5
SMJ4C1024
1 048 576-bit
(1024K x 1) Enhanced Page Mode ............................... 9-27
SMJ44100
4 197 304-bit
(4096K x 1) Enhanced Page Mode ............................... 9-47
SMJ44400
4 197 304-bit
(1024K x 4) Enhanced Page Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 9-67
SMJ416100
16777216-bit
(16 385K x 1) Enhanced Page Mode ............................. 9-87
SMJ416400
16 777 216-bit
(4096K x 4) Enhanced Page Mode .............................. 9-105
SMJ417100
16 777 216-bit
(16 385K x 1) Enhanced Page Mode ............................ 9-125
SMJ417400
16777216-bit
(4096K x 4) Enhanced Page Mode .... ; ......................... 9-143
SMJ417400
16 777 216-bit
(4096K x 4) Enhanced Page Mode .............................. 9-143
SMJ44C250
1 048 576-bit
(256K x 4) Multiport Video RAM ................................ 9-161
SMJ44C251
1 048 576-bit
(256K x 4) Multiport Video RAM ................................ 9-199
SMJ55160
4 194 304-bit
(256K x 16) Multiport Video RAM ............................... 9-239
SMJ55165
4 194 304-bit
(256K x 16) Multiport Video RAM ............................... 9-241
131 072-bit
(16K x 8) CMOS EPROM ...................................... 9-243
VIDEO RAMS
EPROMS
SMJ27C128
SMJ27C256
262144-bit
(32K x 8) CMOS EPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 9-253
SMJ27C512
524288-bit
(64K x 8) CMOS EPROM ...................................... 9-263
SMJ27C040
4 194 304-bit
(512K x 8) CMOS EPROM ..................................... 9-275
SMJ29F816
16384-bit
(2K x 9) 5-V Flash EEPROM Serial JTAG Bus .................... 9-285
9-2
Introduction to Military Data Sheets
This section contains Military MOS Memory data sheets.
For additional information on Military devices and availability. please refer to the Military Selection Guide
(literature number SCYC002). or contact your local TI Field Sales Office.
TEXAS ~
INSTRUMENTS
9-3
Introduction to Military Data Sheets
TEXAS ~
INsrRUMENTS
9-4
SMJ44C256
262144-WORD BY 4-BIT DYNAMIC RANDOM-ACCESS MEMORY
SGMS034A-MAY
• - 55°C to 125°C Operating Free-Air
Temperature Range
• Low Power Dissipation
• Texas Instruments EPIC'· CMOS Process
• Organization... 262 144 x 4
• All Inputs and Clocks Are TTL Compatible
• Single 5-V Supply (10% Tolerance)
• Performance Ranges:
ACCESS ACCESS ACCESS READ
TIME
TIME
TIME
OR
SMJ44C256-BO
SMJ44C256-10
SMJ44C256-12
SMJ44C256-15
ta(C)
(tCAC)
(MAX)
80 ns
100 ns
120 ns
150 ns
20
25
30
40
ns
ns
ns
ns
FEBRUARY 1993
• 3-State Unlatched Output
• Processed to MIL-STD-833, Class B
ta(R)
(tRAC)
(MAX)
198~REVISED
WRITE
ta(CA)
(tcAAl
(MAX)
40
45
55
70
CYCLE
(MIN)
ns
ns
ns
ns
150 ns
190 ns
220 ns
260 ns
• Enhanced Page Mode Operation with
CAS-Before-RAS Refresh
• Packaging Offered:
- 20-Pin 300-Mil Ceramic DIP (JD Suffix)
20-Lead Ceramic Surface-Mount
Package (HJ Suffix)
20-Terminal Low-Profile Leadless
Ceramic Surface-Mount Package
(HL Suffix)
20-Terminal Leadless Ceramic
Surface-Mount Package (FQ Suffix)
20-Pin Ceramic Flat Pack (HK Suffix)
20-Pin Ceramic Zig Zag In-Line Package
(SV Suffix)
• Long Refresh Period ...
512-Cycle Refresh in 8 ms (Max)
JD PACKAGEt
(TOP VIEW)
D01
1 U 20
D02~ 2
W[
RAS
TF
AO[
A1 [
A2[
A3[
Vccl
3
4
5
6
7
B
9
10
19
18
17
16
15
14
13
12
11
IT
VSS
D04
D03
CAS
D03
VSS
D02
RAS
AO
IT
AS
A7
A6
A5
A2
VCC
A5
A7
A4
HJ, HL, AND FQ PACKAGESt
(TOP VIEW)
D01
D02
W
RAS
IT
AO
A1
AS
A7
A6
A5
A4
A2
A3
VCC
t
CAS
D04
D01
W
TF
A1
A3
A4
A6
AS
HK FLAT PACKAGEt
(TOP VIEW)
VSS
D04
D03
CAS
TF
2
4
D01
D02
W
RAS
VSS
D04
D03
CAS
TF
IT
AO
A1
A3
AS
A7
A6
A5
VCC
A4
A2
The packages shown here are for pinout reference only.
The HJ and FQ packages are actually 75% of the length
of the JD pacj
4~
>
17~
C20[ROW]
G23/[REFRESH ROW]
24[PWROWNI
C21/[COLUMNI
G24
W
G
001
31
1~
r--
003
004
23,210
po 23C22
24,2SEN
G25
-,
1
24-
002
&
r
A,220
V26
A,Z26
18
19
t This symbol is in accordance with ANSI/IEEE Std 91-1984 and lEG Publication 617·12. Pin numbers shown are for the JD package.
TEXAS
-If
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS nOO1
9·7
SMJ44C256
262 144·WORD BY 4·BIT DYNAMIC RANDOM·ACCESS MEMORY
SGMS034A-MAY 198&-REVISED FEBRUARY 1993
functional block diagram
I
).
t t t t
Row
Address
Buffere
~
(9)
256K
Array
~
..I.
AD
A1
A2
A3
A4
A5
A6
A7
A8
~
I
,J
II
Row
Decode
(9)
~
-,/
.
256K
Array
Sense Ampllflere
Column
Address
Buffers
I
Timing and Control
Column Decode
~
=::=
I-!:=::=
=::=
I/O
Buffers
40f8
Selection
~
~
:;
~
Data
In
Reg
~
Data
Out
Reg
~
4
Sense Ampllflere
256K
Array
I
II
Row
Decode
256K
Array
DQ1-D Q4
operation
enhanced page mode
Page-mode operation allows faster memory access by keeping the same row address while selecting random
column addresses. The time for row-address setup and hold and address multiplex is thus eliminated. The
maximum number of columns that may be accessed is determined by the maximum RAS low time and the CAS
page cycle time used. With minimum CAS page cycle time, all 512 columns specified by column addresses AD
through AS can be accessed without intervening RAS cycles.
Unlike conventional page-mode DRAMs, the column-address buffers in this device are activated on the falling
edge of RAS. The buffers act as transparent or flow-through latches while CAS is high. The falling edge of CAS
latches the column addresses. This feature allows the SMJ44C256 to operate at a higher data bandwidth than
conventional page-mode parts, since data retrieval begins as soon as column address is valid rather than when
CAS transitions low. This performance improvement is referred to as enhanced page mode. Valid column
address may be presented immediately after th(RA) (row address hold time) has been satisfied, usually well in
advance of the falling edge of CAS. In this case, data is obtained after talC) max (access time from CAS low),
if ta(CA) max (access time from column address) has been satisfied. In the event that column addresses for the
next page cycle are valid at the time CAS goes high, access time for the next cycle is determined by the later
occurrence of talC) or ta(CP) (access time from rising edge of CAS).
TEXAS . "
INSTRUMENTS
9-8
POST OFFICE BOX 1443· HOUSTON. TEXAS 77001
SMJ44C256
262144-WORD BY 4-B11 DYNAMIC RANDOM-ACCESS MEMORY
SGMS034A-MAY 1989-REVISED FEBRUARY 1993
address (AO through AS)
Eighteen address bits are required to decode 1 of 262 144 storage cell locations. Nine row-address bits are set
up on pins AO through AS and latched onto the chip by the row-address strobe (RAS). Then nine column-address
bits are set up on pins AO through AS and latched onto the chip by the column-address strobe (CAS). All
addresses must be stable on or before the falling edges of RAS and CAS. RAS is similar to a chip enable in
that it activates the sense amplifiers as well as the row decoder. In the SMJ44C256, CAS is used as a chip select
activating the output buffer, as well as latching the address bits into the column-address buffers.
write enable (W)
The read or write mode is selected through the write-enable CN) input. A logic high on the W input selects the
read mode and a logic low selects the write mode. The write-enable terminal can be driven from the standard
TIL circuits without a pull up resistor. The data input is disabled when the read mode is selected. When W goes
low prior to CAS (early write), data out will remain in the high-impedance state for the entire cycle, permitting
a write operation with G grounded.
data In (OQ1-0Q4)
Data is written during a write or read-modify-write cycle. Depending on the mode of operation, the falling edge
of CAS or W strobes data into the on-chip data latch. In an early write cycle, W is brought low prior to CAS and
the data is strobed in by CAS with setup and hold times referenced to this signal. In a delayed-write or
read-modify-write cycle, CAS will already be low, thus the data will be strobed in by Wwith setup and hold times
referenced to this signal. In a delayed-write or read-modify-write cycle, G must be high to bring the output buffers
to high-impedance prior to impressing data on the I/O lines.
data out (OQ1-0Q4)
The three-state output buffer provides direct TIL compatibility (no pull up resistor required) with a fanout of two
Series 54 TIL loads. Data out is the same polarity as data in. The output is in the high-impedance (floating) state
until CAS and G are brought low. In a read cycle the output becomes valid after the access time interval ta(C)
that begins with the negative transition of CAS as long as ta(Rl and ta(~) are satisfied. T~e output becomes
valid after the access time has elapsed and remains valid while CAS and G are low. CAS or G going high returns
it to a high-impedance state. This is accomplished by bringing G high prior to applying data, thus satisfying
td(GHO)'
output enable (0)
G controls the impedance of the output buffers. When G is high, the buffers will remain in the high-impedance
state. Bringing G low during a normal cycle will activate the output buffers putting them in the low-impedance
state. It is necessary for both Gand CAS to be brought low for the output buffers to go into the low-impedance
state. Once in the low-impedance state, they will remain in the low-impedance state until either G or CAS is
brought high.
refresh
A refresh operation must be performed at least once every eight milliseconds to retain data. This can be
achieved by strobing each of the 512 rows (AO-AS). A normal read or write cycle will refresh all bits in each row
that is selected. A RAS-only operation can be used by holding CAS at the high (inactive) level, thus conserving
power as the output buffer remains in the high-impedance state. Externally generated addresses must be used
for a RAS-only refresh. Hidden refresh may be performed while maintaining valid data at the output pin. This
is accomplished by holding CAS at VIL after a read operation and cycling RAS after a specified precharge period,
similar to a RAS-only refresh cycle.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443· HOUSTON, TEXAS 77001
9-9
SMJ44C256
262144·WORD BY 4·B11 DYNAMIC RANDOM·ACCESS MEMORY
SGMS034A-MAY 1989-REVISED FEBRUARY 1993
CAS-before-RAS refresh
CAS-before-RAS refresh is utilized by bringing CAS low earlier than RAS [see parameter td(CLRL)Rl and holding
it low after RAS falls [see parameter ~(RLCH)Rl. For successive CAS-before-RAS refresh cycles, CAS can
remain low while cycling RAS. The external address is ignored and the refresh address is generated internally.
The external address is also ignored during the hidden refresh option.
power up
To achieve proper device operation, an initial pause of 200 !-IS followed by a minimum of eight initialization
(refresh) cycles is required after power-up to the full VCC level.
test function pin
During normal device operation the TF pin must either be disconnected or biased at a voltage less than or equal
toVCC·
TEXAS ~
INsrRUMENTS
9-10
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
SMJ44C256
262 144·WORD BY 4·BIT DYNAMIC RANDOM·ACCESS MEMORY
SGMS034A-MAY 1989--REVISED FEBRUARY 1993
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage range, Vee ............................................................. 0 V to 7 V
Voltage range on any pin (see Note 1) ................................................. - 1 V to 7 V
Short circuit output current ................................................................ 50 mA
Continuous total power dissipation ........................................................... 1 W
Operating free-air temperature range, TA .......................................... - 55°C to 125°C
Storage temperature range ....................................................... - 65°C to 150°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maxim urn-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values in this data sheet are with respect to VSS.
recommended operating conditions
MIN
NOM
MAX
4.5
5
5.5
UNIT
V
VCC
Supply voltage
VSS
Supply voltage
VIH
High-level input voltage
2.4
6.5
V
VIL
Low-level input voltage (see Note 2)
-1
0.8
V
TA
Operating free-air temperature
TC
Case temperature
125
°c
°c
0
V
-55
NOTE 2: The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used in this data sheet for logic
voltage levels only.
electrical characteristics over full ranges of recommended operating conditions (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
VOH
H ig h-Ievel output
voltage
10H =-5 rnA
VOL
Low-level output
voltage
IOL=4.2 rnA
II
Input current
(leakage)
10
'44C256-80
MIN
MAX
'44C256-10
'44C256-12
MIN
MIN
MAX
2.4
2.4
2.4
'44C256-15
MAX
MIN
MAX
2.4
UNIT
V
0.4
0.4
0.4
0.4
V
VI =Ot06.5V, VCC=5V,
All other pins = 0 V to VCC
±10
±10
±10
±10
IIA
Output current
(leakage)
Vo = 0 to VCC, VCC = 5.5 V,
CAS high
±10
±10
±10
±10
IIA
ICCI
Read/write cycle
current
tc(rdW) = minimum,
VCC = 5.5V
80
70
60
55
rnA
ICC2
Standby current
After 1 memory cycle,
RAS and CAS high,
VIH = 2.4 V
3
3
3
3
rnA
ICC3
Average refresh
current (RAS-only,
orCBR)
tc(rdW) = minimum,
VCC = 5.5 V, RAS cycling,
CAS high (RAS only),
RAS low,
after CAS low (CBR)
75
65
55
50
mA
ICC4
Average page current
tc(P) = minimum,
~=5.~
RAS low, CAS cycling
50
45
35
30
rnA
TEXAS
~
INsrRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
9-11
SMJ44C256
262144·WORD BY 4·B11 DYNAMIC RANDOM-ACCESS MEMORY
SGMS034A-MAY 1989-REVISED FEBRUARY 1993
capacitance over recommended ranges of supply voltage and operating free-air temperature,
f = 1 MHz (see Note 3)
HLJJD/FQ
PARAMETER
MIN
SV
HK
HJ
MIN
MAX
MAX
MIN
MAX
MIN
MAX
UNIT
Ci(Al
Input capacitance, address inputs
6
7
8
9
pF
Ci(RCI
Input capacitance, strobe inputs
7
7
8
8
pF
Ci(W)
Input capacttance, write-enable input
7
7
7
7
pF
Co
Output capacttance
7
9
10
8
pF
NOTE 3: Capacitance is sampled only at initial design and after any major change. Samples are tested at 0 V and 25'C with a 1 MHz signal applied
to the pin under test. All other pins are open.
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (see Figure 1)
'44C256-80
'44C256·10
'44C256-12
'44C256·15
MIN
MIN
MIN
MIN
PARAMETER
ALT.
SYMBOL
ta(C)
Access time from CAS low
tCAC
20
25
30
40
ns
talCAI
Access time from column-address
tM
40
45
55
70
ns
ta(R)
Access time from RAS low
tRAC
80
100
120
150
ns
talGI
Access time from Glow
tGAC
20
25
30
40
ns
ta{CP)
Access time from column
precharge
tCPA
40
50
60
75
ns
ldis{CH)
Output disable time after CAS high
(see Note 4)
tOFF
20
25
30
35
ns
ldis{G)
Output disable time after G high
(see Note 4)
tGOFF
20
25
30
35
ns
NOTE 4: ldis{CH) and ldis{G) are specified when the output
IS
MAX
MAX
MAX
UNIT
no longer driven. The outputs are disabled by bringing either G or CAS high.
TEXAS
~
INSTRUMENTS
9-12
MAX
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
SMJ44C256
262144-WORD BY 4-BIT DYNAMIC RANDOM-ACCESS MEMORY
SGMS034A-MAY 1989-REVISED FEBRUARY 1993
timing requirements over recommended ranges of supply voltage and operating temperature
Ic(rd)
Read cycle time (see Note 6)
1c(W)
Write cycle time
lc(rdW}
Cycle time.
Read-write/read-modify-write
Ic(p)
Cycle time, page-mode read or
write (see Note 7)
Ic(PM)
Cycle time, page-mode
read-modify-write
'44C256-80
'44C256-10
'44C256-12
'44C256-15
ALT.
SYMBOL
MIN
tRC
150
190
220
260
ns
twc
150
190
220
260
ns
tRWC
225
270
305
355
ns
tpc
50
55
65
80
ns
tpRWC
115
135
150
175
ns
10
15
25
ns
MAX
MIN
MAX
MIN
MAX
MIN
MAX
UNIT
tw(CH)
Pulse duration, CAS high
tcp
10
tw(CL)
Pulse duration. CAS low
(see Note 8)
tCAS
20
tw(RH)
Pulse duration, RAS high
(precharge)
tRP
60
tw(RL)
Pulse duration,
non-page-mode RAS low
(see Note 9)
tRAS
80
10 000
100
10 000
120
10 000
150
10000
ns
tw(RL)P
Pulse duration,
page-mode RAS low
(see Note 9)
tRASP
80
100000
100
100000
120
100000
150
100000
ns
tw(WL)
Pulse duration, write low
twP
15
15
20
25
ns
tsu(CA)
Setup time, column-address
before CAS low
tASC
5
5
5
5
ns
tsu(RA)
Setup time, row-address
before RAS low
tASR
0
0
0
0
ns
tsu(D)
Vii low (see Note 10)
tDS
0
0
0
0
ns
tsu(rd)
Setup time, W high before
CAS low
tRCS
0
0
0
0
ns
tsu(WCL)
Setup time, W low before
CAS low (see Note 11)
twcs
0
0
0
0
ns
tsu(WCH)
Setup time, W low before
CAS high
tCWL
20
25
30
40
ns
tsu(WRH)
Setup time, W low before
RAS high
tRWL
20
25
30
40
ns
th(CA)
Hold time, column-address
after CAS low (see Note 10)
tCAH
15
20
20
25
ns
th(RA)
Hold time, row-address after
RASlow
tRAH
15
15
15
15
ns
NOTES:
Setup time, data before
10 000
25
10000
80
30
10 000
90
40
10 000
100
ns
ns
5.
6.
7.
8.
Timing measurements In this table are referenced to VIL max and VIH min.
All cycle times assume tt ~ 5 ns.
To assure Ic(p) min, tsu(CA) should be greater than or equal to tw(CH)'
In a read-modify-write cycle, td(CLWL) and tsu(WCH) must be observed. Depending on the user's transition times, this may require
additional CAS low time [tw(CL)l.
9. In a read-modify-write cycle, td(RLWL) and tsu(WRH) must be observed. Depending on the user's transition times, this may require
additional RAS low time [t~)l. _
10. Referenced to the later of CAS or W in write operations.
11. Early write operation only.
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
9-13
SMJ44C256
262 144·WORD BY 4·BIT DYNAMIC RANDOM·ACCESS MEMORY
SGMS034A-MAY 198~REVISED FEBRUARY 1993
timing requirements over recommended ranges of supply voltage and operating temperature
(continued)
ALT.
SYMBOL
'44C256-80
MIN
MAX
'44C256-10
MIN
MAX
'44C256-12
MIN
MAX
'44C256-15
MIN
MAX
UNIT
th(RLCA)
Column-address hold time,
after RAS low (see Note 12)
tAR
60
70
80
100
ns
th(D)
Data hold time, after CAS low
(see Note 10)
tDH
15
20
25
30
ns
th(RLD)
Data hold time, after RAS low
(see Note 12)
tDHR
60
70
85
110
ns
th(WLGL)
Hold time, G high after W low
tGH
20
25
30
40
ns
th(CHrd)
Hold time, W high after CAS high
(see Note 14)
tRCH
0
0
0
0
ns
th(RHrd)
Hold time, W high after RAS high
(see Note 14)
tRRH
10
10
10
10
ns
th(CLW)
Hold time, W low after CAS low
(see Note 11)
twCH
15
20
25
30
ns
th(RLW)
Hold time, W low after RAS low
(see Note 12)
twCR
65
75
90
105
ns
ld(RLCH)
Delay time, RAS low to CAS high
tCSH
80
100
120
150
ns
ldCCHRLI
Delay time, CAS high to RAS low
leRP
0
0
0
0
ns
ld(CLRH)
Delay time, CAS low to RAS high
tRSH
20
25
30
40
ns
ld(CLWL)
Delay time, CAS low to W low
(see Note 15)
tCWD
60
70
80
90
ns
tRCD
30
60
30
75
30
90
30
110
ns
tRAD
20
40
20
55
20
65
25
80
ns
Delay time, RAS low to CAS low
ld(RLCL) . (see Note 13)
ld(RLCA)
NOTES:
5.
10.
11.
12.
13.
14.
15.
Delay time, RAS low to
column-address (see Note 13)
Timing measurements In this table are referenced to VIL max and VIH min.
Referenced to the later of CAS or VIi in write operations.
Early write operation only.
The minimum value is measured when td(RLCL) is set to td(RLCL) min as a reference.
Maximum value specified only to assure access time.
Either th(RHrd) or th(CHrd) must be satisified for a read cycle.
Read-modify-write operation only.
TEXAS ~
INSTRUMENTS
9-14
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
SMJ44C256
262144·WORD BY 4·BIT DYNAMIC RANDOM·ACCESS MEMORY
SGMS034A-MAY 1989-REVISED FEBRUARY 1993
timing requirements over recommended ranges of supply voltage and operating temperature
(concluded)
ALT.
SYMBOL
'44C256-10
'44C256-80
MIN
MAX
MIN
'44C256-12
MAX
MIN
'44C256-15
MAX
MIN
MAX
UNIT
Icl(CARH)
Delay time, column-address to
RAS high
tRAl
40
45
55
70
ns
Icl(CACH)
Delay time, column-address to
CAS high
tCAl
40
45
55
70
ns
Icl(RlWl)
Delay time, RAS low to W low
(see Note 15)
tRWD
130
150
170
200
ns
Icl(CAWl)
Delay time, column-address to W
low (see Note 15)
tAWD
80
95
105
120
ns
Icl(GHD)
Delay time. G high before data at
DO
tGDD
20
25
30
40
ns
Icl(GlRH)
Delay time. G low to RAS high
tGSR
20
25
30
40
ns
Icl(RLCH)R
Delay time. RAS low to CAS high
(see Note 16)
tCHR
20
25
25
30
ns
Icl(ClRl)R
Delay time. CAS low to RAS low
(see Note 16)
tCSR
10
10
10
15
ns
ld(RHCL)R
Delay time. RAS high to CAS low
(see Note 16)
tRPC
0
0
0
0
ns
Refresh time interval
tREF
trf
tt
NOTES:
Transition time (see Note 17)
5.
15.
16.
17.
8
8
8
8
ms
ns
IT
Timing measurements in this table are referenced to V,l max and V,H min.
Read-modify-wrHe operation only.
CAS-before-RAS refresh only.
System transition times (rise and fall) are to be a minimim of 3 ns and a maximim of 50 ns.
TEXAS
~
INsrRUMENTS
POST OFFICE BOX 1443· HOUSTON. TEXAS 77001
9-15
SMJ44C256
262 144-WORD BY 4-BIT DYNAMIC RANDOM-ACCESS MEMORY
SGMS034A-MAY 1989--REVISED FEBRUARY 1993
PARAMETER MEASUREMENT INFORMATION
VIH
OQ1OQ4
NOTE A: Output may go from high-impedance to an invalid data state prior to the specified access time.
Figure 1. Read Cycle Timing
TEXAS ~
INSTROMENTS
9-16
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
SMJ44C256
262144·WORD BY 4·BIT DYNAMIC RANDOM·ACCESS MEMORY
SGMS034A-MAY 198&-REVISED FEBRUARY 1993
PARAMETER MEASUREMENT INFORMATION
Figure 2. Early Write Cycle Timing
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
9-17
SMJ44C256
262 144·WORD BY 4·BIT DYNAMIC RANDOM·ACCESS MEMORY
SGMS034.A -MAY 1989-REVISED FEBRUARY 1993
PARAMETER MEASUREMENT INFORMATION
Figure 3. Write Cycle Timing
TEXAS ~
INsrRUMENTS
9-18
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
SMJ44C256
262144·WORD BY 4·BIT DYNAMIC RANDOM·ACCESS MEMORY
SGMS034A-MAY 1989-REVISED FEBRUARY 1993'
PARAMETER MEASUREMENT INFORMATION
f - - - - ta(R)
l '.
II
.I.
i
.:
~ ta(G) -----.j
I
G
~gX~ax{~
NOTE A: Output may go from high impedance to an invalid data state prior to the specified access time.
Figure 4. Read-Write/Read-Modify-Write Cycle Timing
TEXAS ~
INsrRUMENTS
POST OFFICE BOX 1443· HOUSTON. TEXAS 77001
9-19
SMJ44C256
262 144·WORD BY 4·BIT DYNAMIC RANDOM·ACCESS MEMORY
SGMS034A-MAY 1989-REVISED FEBRUARY 1993
PARAMETER MEASUREMENT INFORMATION
tw(RH) ~
14-
I
I
_~!
~VIH
RAS
!I~
e l l I
]t.• - - - - - - - - - - - - - - - - - - - - ' - - - - - - ' " I
I
VIL
------------'.~I
1IIII11111f------------- tw(RL)P
I ~
I ~
td(RLCL) ~
ld(RLCH)
I
14-
I I
I
I
I
I
I
I
~ltsU(RA)
I
I·
~ j4- tS~(CA)
th(RLCA)
I ~
I
I
J"'I
~
tw(CL) ~
I""
T\ X. 0
I
~
II1II
.1 :
th(RA) --.:
i
I
.1
td(CLRH)
14-
~ tw(CH)
\ \i
1
I
I
I
~ th(C~)
--.I
I
I
~ td(CHRL) +I
it---!'-;-I---- VIH
I
I
I
tc(P)
I+-
I I
I
--.!
Ii
:
I
I
~ i
ld(CACH)
::
j.-- ld(CARH) ~
I
/'\7'~,"'\7Ij~~~ VIH
Column
AO-AS
'\Co<~~.c:.c.~~~
I
w
ta(C)
-i~4--~~
I
I
I
I
14--
W~
ta(CA)
(see Note C) I
1
I
I
I
If.
,:\
DQ1DQ4 -------------~l\~alld ouy
14---I
G
~
ta(G)
~
-.I
(see Note C)
(see Note A)
~
104---
b\E~~ybl
ta(G)
IO!II
I
(hi
.~
I
tdls(G)
G
-.J
Valid Out
I"
~
.1
VIL
-.J
II1II
I
II
~ ta(CP)
(see Note A)
th(RHrd)
th(CHrd)
~ VIH
'Q VIL
ldls(CH)
i
:1
VOH
1)--- - - - VOL
.:
tdls(G)
/Illi:.,..,..,.~....,~o....
~~,.,...t~,..,*.....~~.........,,..,.:I:
NOTES: A. Output may go from high-impedance to an invalid data state prior to the specified access time.
B. A write cycle or read-modify-write cycle can be mixed with the read cycles as long as the write and read-modify-write timing
specifications are not violated.
C. Access time is ta(CP) or ta(CA) dependent.
Figure 5. Enhanced Page-Mode Read Cycle Timing
TEXAS ~
INsrRUMENTS
9-20
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
SMJ44C256
262144·WORD BY 4·BIT DYNAMIC RANDOM·ACCESS MEMORY
SGMS034A-MAY 1989-REVISED FEBRUARY 1993
PARAMETER MEASUREMENT INFORMATION
I..
RAS.
~!
!IXC
I
td(RLCH)
td(RLCL)
~I
1
tw(CL) ~
1
I
~:I i+!1
I\\{
I
1
tsu(RA)
AO-M
II
I
I
I
~I
1 1 I
~ td~~LRH) --.j 1 I
1
td(CH~L)-+I
~-- - - - - - - - - - - - - - - - - - - - - - - - -
I I..
I I..
I :
CAS
tw(RH) --.j
~
~I I
I
YrlLVIH
tw(RL)P
1
I
1
I
I..
j4-
tsu(CA) -.:
J4- th(RA) ----+I I
~h(RLCA)
~
:
Row
~:
~td(RLCA)~
I"
I
w
1
1
tC(P)
~
1
1 ~ tw(CH) --+I
1 1
1
i~
0
I
i+ th(CA~
I
1
::
14- Id(CACH) -+j
1
1 I
+" :~
-.:
:..
Id(CARH)
I ~l
1
I
co"m,:
1 I
~I
)00~~g('~~RK*~§0 :::
I
I+-
tsu(WCH) ~
I
I
1114- tsu(WRH) --.!
I
/'m~~V'V'V'V'''''''''''''~
1
......~~~~~~~~~
!aulD)
1
J4- th(D) ---.I
1 1
(see Note B)
1
(see Note B)
:
~ tsu(D) ~th/Dl
~I
1 I..
(see Note B)
th(RLD)
(see Note B)
.1
1"1
1
-+1 I+- td(GHD)
1
G
W
~I
VIH
VIL
th(WLGL)
1
I
~~~C~*)@ VIH
Valid Data In
-/ ~ '---../ \Uf
I
-.j 14- th(WLGL)
I
VIL
I
1
~~~~~~~~~~H-_t-~~~~~~~~~~
D~; ~
VIL
)1<---.....1...;----- VIH
I
1
1
I
1
\\1 I!
I
1
1
1 ~I 1
14;- tsu(WCH~ ~
I..
1 ~I
I1
1 I
"""I 1
1 1
th(RLW)
.AAJV' "
~I I"
~
~
td(GHD)
~*RX~aXeiii&V
VIL
1
~
~~
VIH
VIL
NOTES: A. A read cycle or a read-modify-write cycle can be intermixed with the write cycles as long as the read and read-modify-write timing
specifications are not violated.
B. Referenced to CAS or IN, whichever occurs last.
Figure 6. Enhanced Page-Mode Write Cycle Timing
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
9-21
SMJ44C256
262144-WORD BY 4-BIT DYNAMIC RANDOM-ACCESS MEMORY
SGMS034A-MAY 19S9-REVISED FEBRUARY 1993
PARAMETER MEASUREMENT INFORMATION
tw(RH) -+i
tw(RL)P -----------,.~II
I.
I
I I I
~i
i~
I~
.1
Id(RLCH)
I j+- td(RLCL) ~I
I I
i~
-+:
I
I
'fI \:r :;-;-
i
~ tsu(RA)
I.
tsu(CA) -+i
td(RLCA) 1 . . 1
I
AO-A8
I
I
~I
I
tw(CL)
I t~(RLCN ----+1
j4/ I
I
I"
Column
•
I+--Id(CLRH)
tc 23C22
24EN
A'll
t This symbol is in accordance with ANSI/IEEE Std. 91-1984 and lEG Publication 617-12.
The pin numbers shown are for the 18-pin JD package.
TEXAS ~
INSTRUMENTS
9-30
POST OFFICE BOX 1443· HOUSTON. TEXAS 77001
17
Q
SMJ4C1024
1 048 576-81T DYNAMIC RANDOM-ACCESS MEMORY
SGMS0238-DECEMBER 19S5-REVISED MARCH 1992
functional block diagram
w
+
lJ
AO
A1
A2
A3
A4
A5
A6
A7
A8
A9
r
+
+
Timing and Control
Row
Address
Buffers
(10)
256K
Array
I
1
I Decode
Row I 256K
Array
I
Sense Amplifiers
Column
Address
Buffers
(10)
h
r
Column Decode
~
~
~
i--"
::
::
::
~
I/O
Buffers
10f8
Selection
H
Data In
Reg.
o
Data
Out Reg.
Q
H.
Sense Amplifiers
256K
Array
I
IDecode
Row I 256K
Array
I
TEXAS ~
INsrRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
9·31
SMJ4C1024
1048 576-BIT DYNAMIC RANDOM-ACCESS MEMORY
SGMS023B-DECEMBER 1988-REVISED MARCH 1992
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Voltage range on any pin (see Note 1) ................................................. - 1 V to 7 V
Voltage range on Vee ............................................................... - 1 V to 7 V
Short circuit output current ................................................................ 50 mA
Power dissipation .......................................................................... 1 W
Operating temperature range ...................................................... - 55°G to 70°C
Storage temperature range ....................................................... - 65°C to 150°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. This is a stress rating only, and
functional operation of the device at these or any other conditions beyond those indicated in the "recommended operating conditions· section of
this specification is not implied. Exposure to absolute-maximum·rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values in this data sheet are with respect to VSS.
recommended operating conditions
MIN
NOM
MAX
VCC
Supply voltage
4.5
5
5.5
VIH
High-level input voltage
2.4
6.5
V
VIL
Low-level input voltage (see Note 2)
-1
0.8
V
TA
Minimum operating free-air temperature
TC
Maximum operating case temperature
-55
UNIT
V
·C
125
0
·C
NOTE 2: The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used in this data sheet for logic
voltage levels only.
electrical characteristics over full ranges of recommended operating conditions (unless otherwise
noted)
PARAMETER
TEST
CONDITIONS
VOH
High-level output
voltage
IOH=-5mA
VOL
Low-level output
voltage
IOL=4.2mA
II
Input current
(leakage)
10
'4C1024·80
'4C1024-10
'4C1024·12
MIN
MIN
MIN
MAX
2.4
MAX
2.4
MAX
2.4
'4C1024·15
UNIT
MIN
UNIT
MAX
2.4
V
0.4
0.4
0.4
0.4
VI = Oto 6.5 V,
VCC =5.5V,
All other pins = 0 V to VCC
%10
%10
%10
%10
!lA
Output current
(leakage)
Vo = OtoVCC,
VCC = 5.5 V, CAS high
%10
%10
%10
%10
J,tA
ICC1
Read or write
cycle current
Minimum cycle, VCC = 5.5 V
75
70
60
55
mA
ICC2
Standby current
After 1 memory cycle,
RAS and CAS high,
VIH = 2.4 V
3
3
3
3
mA
ICC3
Average refresh
current
(RAS only or CSR)
Minimum cycle, VCC = 5.5 V,
RAS cycling,
CAS high (RAS-only),
RAS low after CAS low
(CSR)
70
65
55
50
mA
ICC4
Average page
current
50
45
35
30
mA
tpc = minimum,
~=5.~
RAS low, CAS cycling
TEXAS
~
INSTRUMENTS
9-32
V
POST OFFICE BOX 1443· HOUSTON, TEXAS 77001
SMJ4C1024
1 048 576·81T DYNAMIC RANDOM·ACCESS MEMORY
SGMS023B--DECEMBER 1988-REVISED MARCH 1992
capacitance over recommended ranges of supply voltage and operating free-air temperature,
f = 1 MHz (see Note 3)
HL/JD/FQ
PARAMETER
MIN
HJ
MAX
MIN
HK
MAX
MIN
SV
MAX
MIN
MAX
UNIT
CiCA)
Input capacitance, address inputs
6
7
8
9
Ci(D)
Input capacitance, data input
5
5
6
7
pF
CiCRC)
Input capacitance, strobe inputs
7
7
8
8
pF
Ci(W)
Input capacitance, write-enable input
7
7
7
7
pF
Co
Output capac Hance
7
9
10
8
pF
...
pF
NOTE 3: CapacHance IS sampled only at Initial design and after any malor change. Samples are tested at 0 V and 25°C with a 1 MHz signal applied
to the pin under test. All other pins are open.
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (see Figure 1)
PARAMETER
ALT.
SYMBOL
'4C1024-80
MIN
'4C1 024-1 0
MAX
MIN
MAX
'4C1024-12
'4C1024-15
MIN
MIN
MAX
MAX
UNIT
tCAC
20
25
30
40
ns
tM
40
45
55
70
ns
Access time from RAS low
tRAC
80
100
120
150
ns
ta(CPl
Access time from column precharge
tCPA
40
40
60
75
ns
idis(CH)
Output disable time after CAS high
(see Note 4)
tOFF
20
25
30
35
ns
Ia(C)
Access time from CAS low
tICAl
Access time from column address
tCR)
NOTE 4: idis(CH) is specified when the output is no longer driven. The output is disabled by bringing CAS high.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
9-33
SMJ4C1024
1 048 576·81T DYNAMIC RANDOM·ACCESS MEMORY
SGMS023B-DECEMBER 198B-REVISED MARCH 1992
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
PARAMETER
ALT.
SYMBOL
'4C1024-80
'4C1 024-1 0
'4C1024-12
'4C1024-15
MIN
MIN
MIN
MIN
MAX
MAX
MAX
MAX
UNIT
Ic(rd)
Read cycle time (see Note 6)
tRC
150
190
220
260
ns
IcIWl
Write cycle time
twc
150
190
220
260
ns
tc(rdW)
Read-write!read-modify-write
cycle time
tRWC
175
220
265
315
ns
Ic(p)
Page-mode read or write
cycle time (see Note 7)
tpc
50
55
65
80
ns
Ic(PM)
Page-mode
read-modify-write cycle time
tPRWC
75
85
110
135
ns
tw(CH)
Pulse duration, CAS high
tcp
10
10
15
25
ns
tw(CL)
Pulse duration, CAS low
(see Note 8)
tw(RH)
Pulse duration, RAS high
(precharge)
twiRL)
Non-page-mode pulse
duration, RAS low
(see Note 9)
tw(RL)P
Page-mode pulse duration,
RAS low (see Note 9)
. tCAS
20
10000
25
10000
80
30
10000
40
10000
ns
100
90
ns
tRP
60
tRAS
80
10000
100
10000
120
10000
150
10000
ns
tRASP
80
100000
100
100000
120
100000
150
100000
ns
tw(WL)
Write pulse duration
twp
15
15
20
25
ns
tsu(CA)
Column-address setup time
before CAS low
tASC
0
3
3
3
ns
tsu(RA)
Row-address setup time
before RAS low
tASR
0
0
0
0
ns
tsu(D)
Data setup time
(see Note 10)
tDS
0
0
0
0
ns
tsu(rd)
Read setup time before CAS
low
tRCS
0
0
0
0
ns
tsu(WCL)
W-Iow setup time before CAS
low (see Note 11)
twcs
0
0
0
0
ns
tsu(WCH)
W-Iow setup time before CAS
high
tCWL
20
25
30
40
ns
tsu(WRH)
W-Iow setup time before RAS
high
tRWL
20
25
30
40
ns
th(CA) .
Column-address hold time
after CAS low
tCAH
15
20
20
25
ns
th(RA)
Row-address hold time after
RAS low
tRAH
12
15
15
20
ns
NOTES:
5.
6.
7.
8.
9.
10.
11.
limmg measurements In thiS table are referenced to VIL max and VIH mm.
All cycle times assume tt = 5 ns.
To assure tc(P) min, tsu(CA) should be greater than or equal to tw(CH).
In a read-modify-write cycle, td(CLWL) and tsu(WCH) must be observed.
In a read-modify-write cycle, td(RL.\tlL) and tsu(WRH) must be observed.
Referenced to the later of CAS or W in write operations.
Early write operation only.
TEXAS ~
INSIRUMENTS
9-34
POST OFFICE BOX 1443· HOUSTON, TEXAS 77001
SMJ4C1024
1 048 576·81T DYNAMIC RANDOM·ACCESS MEMORY
SGMS023B-DECEMBER 19BB-REVISED MARCH 1992
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
ALT.
SYMBOL
PARAMETER
'4Cl024-80
MIN
'4C1024-10
MAX
MIN
'4C1024-12
MAX
MIN
'4Cl024-15
MAX
MIN
MAX
UNIT
th(RCLA)
Column-address hold time after
RAS low (see Note 12)
tAR
60
70
80
100
ns
th(D)
Data hold time (see Note 10)
tDH
15
20
25
30
ns
th(RLD)
Data hold time after RAS low
(see Note 12)
tDHR
60
70
85
110
ns
th(CHrd)
Read hold time after CAS high
(see Note 15)
tRCH
a
a
0
a
ns
th(RHrd)
Read hold time after RAS high
(see Note 15)
tRRH
10
10
10
10
ns
th(CLW)
Write hold time after CAS low
(see Note 11)
twCH
15
20
25
30
ns
th(RLW)
Write hold time after RAS low
(see Note 12)
twCR
60
70
85
100
ns
1d(RLCH)
Delay time, RAS low to CAS high
tCSH
80
100
120
150
ns
1d(CHRL)
Delay time, CAS high to RAS low
tCRP
0
a
0
0
ns
1drcLRHl
Delay time, CAS low to RAS high
tRSH
20
25
30
40
ns
1d(CLWL)
Delay time, CAS low to W low
(see Note 13)
tCWD
20
25
40
50
ns
1d(RLCL)
Delay time, RAS low to CAS low
(see Note 14)
tRCD
22
60
28
75
28
90
33
110
ns
1d(RLCA)
Delay time, RAS low to column
address (see Note 14)
tRAD
17
40
20
55
20
65
25
80
ns
1d(CARH)
Delay time, column address to RAS
high
tRAL
40
45
55
70
ns
1d(CACH)
Delay time, column address to CAS
high
tCAL
40
45
55
70
ns
1d(RLWL)
Delay time, RAS low to W low
(see Note 13)
tRWD
80
100
130
160
ns
1d(CAWL)
Delay time, column address to W
low (see Note 13)
tAWD
40
45
65
80
ns
1d(RLCH)R
Delay time, RAS low to CAS high
(see Note 16)
tCHR
20
25
25
30
ns
1d(CLRL)R
Delay time, CAS low to RAS low
(see Note 16)
tCSR
10
10
10
15
ns
1d(RHCL)R
Delay time, RAS high to CAS low
(see Note 16)
tRPC
a
0
0
0
trf
Refresh time interval
tt
Transition time (see Note 17)
NOTES: 10.
11.
12.
13.
14.
15.
16.
17.
8
tREF
-
-
8
-
8
-
ns
8
-
ms
ns
Referenced to the later of CAS or W In write operations.
Early write operation only.
The minimum value is measured when td(RLCL) is set td(RLCL) min as a reference.
Read -modify-write operation only.
Maximum value specified only to assure access time.
Either th(RH~ th(CHrd) must be satisfied for a read cycle.
CAS-before-RAS refresh only.
Transition times (rise and fall) for RAS and CAS are to be minimum of 3 ns and a maximum of 50 ns.
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
9-35
SMJ4C1024
1 048 576·81T DYNAMIC RANDOM·ACCESS MEMORY
SGMS023B-DECEMBER 19BB-REVISED MARCH 1992
PARAMETER MEASUREMENT INFORMATION
v
m
--I
IOH/IOL
Output Under Test
T
RL=21SQ
CL = SO pF
CL=SOpF
(A) Load Circuit
(A) Alternate Load Circuit
Figure 1. Load Circuits for Timing Parameters
~
........~I ~
~~
N
~
1
~
~
twIRL)
~
I I
I
I I
I '-------tt---'! [4j4-- td(CLRH) ---+j 14-- tw(RH) ~
I 14- td(RLCL) ~
I I
I
1 I
1
id(CHRL) ~
I 1411
td(RLFH) .1 I I I
I I
tw(CL) -.:.): 1 I
VIL
i+f+
I+-
td(RLCA~ ~.I
~
th(RA)
.1 I
I
I I
~ 1411- r...
I I I
1411
~ t,U(RA) 1411
i
AG-A9
r... I
I th(RLCA) t--+--+I
t
r:"
II
~
11
14
411--+1
1-;'1-- tw(CH)
I
I
I ~ I
I
I
----.r
.
_I
su(rd)?I
th(CA)
I
l41l---+I- th(RHrd)
I
J
1 4 1 1 " ' 1 th(CHrd)
I
I
~§f~Ht~Mr~~mr;;,.t;;,JliI i i
I
I
Q
tsu(CA)
td(CACH)
td(CARH)
~1 CoI'm~:1++1-mH~fxi§M§»<",---_ _ _ :::
I
I
I
Iii
-II~!~------~},---- :::
}],oil
---+1-1411
HI-Z
ta(CA)
(see Note A)
ta(R)
IOIIfoIIf---- tdls(CH) ----i~~
~ _ _ _ _ _ _ _ _ _...1
~
Valid
.1
NOTE A: Output may go from high impedance to an invalid state prior to the specified access time.
Figure 2. Read Cycle Timing
TEXAS ~
INSTRUMENTS
9-36
VIH
VIL
14-- ta(C) ~
1
1411
~~~n~ti~r~~
POST OFFICE BOX 1443· HOUSTON, TEXAS 77001
]>------
VOH
VOL
SMJ4C1024
1 048 576·BIT DYNAMIC RANDOM·ACCESS MEMORY
SGMS023B-DECEMBER 1988--REVISED MARCH 1992
PARAMETER MEASUREMENT INFORMATION
Q
---------------HI-Z - - - - - - - - - - - - - - - -
VOH
VOL
Figure 3. Early Write Cycle Timing
TEXAS ~
INsrRuMENTS
POST OFFICE BOX 1443· HOUSTON, TEXAS 77001
9-37
SMJ4C1024
1 048 576·81T DYNAMIC RANDOM·ACCESS MEMORY
SGMS023B-DECEMBER 19S8--REVISED MARCH 1992
PARAMETER MEASUREMENT INFORMATION
~
1
RAS
~~
lOIII
twIRL)
'+-
II1II
~
tt~
,
~ td(RLCL) ---.I
I,
1
1:
tsu(CA)
~
1\
'4"---1-1-- tw(CH) ----.r~
'4
I
~ ~I_ _ _ _ _ _ _J.1
1 lci(CARH)
I' .1
i'4
i'4
i..,
th(RLCA)
V::
V,H
V,L
~::
U(CACH)
,l1li
,
v
I4----t- lci(CHRL) ~
hi
I:
~ ~ tsu(RA)
I
TL-
~~lci(RLCH)
1"' ' 'r--+-------_\I
~
,tW(CL)"
1l1li
,I
1
~ 14- tw(RH) ~
lci(CLRH)
" I
th(RA)
~
.1
~ 2M ~.]@{ 00,,0; ~Hi~_\--_ :::
td(RLCA)
~
~ iIIII-14-
.!
I
w
"-
~f!HH_
j!<::7 VIH
"'-lo.I:~~~~=~VIL
1
1
.1
I
I
I
th(RHrd) 14
~
jill!-- th(CHrd) - . :
I
I
(see Note C)
II1IIII1II---- ta(CA)
.1
~
I
I
I
I
II1II
ta(R)
Q
NOTES: A. Output may go from high impedance to an invalid state prior to the specified access time.
B. A write cycle or a read-modify cycle can be mixed with the read cycles as long as the write and read-modify-write timing specifications
are not violated.
C. Access time is ta(CP) or ta(CA) dependent.
Figure 6. Enhanced Page-Mode Read Cycle Timing
TEXAS ."
INSTRUMENTS
9-40
POST OFFICE BOX 1443· HOUSTON, TEXAS 77001
SMJ4C1024
1 048 576-81T DYNAMIC RANDOM-ACCESS MEMORY
SGMS023B--DECEMBER 1968-REVISED MARCH 1992
PARAMETER MEASUREMENT INFORMATION
tw(RH) ~
tw(RL)P ---------~~ I
14
N-
td(RLCH)~
tw(CL)
td(RLCL)
I I
I ~
th(RA)
tsu(RA)
AO-A9
---+j
I..
w
H.
I
I
I
I
:
I I
tclPI!
tw(CH)
1
td(RLCA)
I
1
/....---.;....:--1
td(CACHI ~
iIIII
ld(CARH)
th(CA)'
14-
th(RLW)I~-+--+~
I
I
I
I
VL
VIH
VIL
--~.I
I
(see Note 8)
~-- tsuD)
14-
I
14-
I
tsu(WRH)
-.!
~~~~~~~~ I
I
th(D) ~
(see Note 8)
I
th(D)
~
14--
! ~IIIIII---jl-tsu(D) - - . ,
tsu(WCH) ~
1411111-+--~
---+j
I I
I
~ ld(CHRL)
I
I
----.I
Column
.HI''''''\/\').
I
~
td(CLRH) --.:
y \ 'i
.1
Row
/4-
o
14
I 14
tsu(CA)
th(RLCA)'
I j+-
II1II-
~
.1
~~
!
~
I
~VIH
I
I '..
I :..
I I
i
14-
th(R~D)
.:
I
.1
I
Valid Data In
VIL
VOH
Q - - - - - - - - - - - - - - - - - HI-Z - - - - - - - - - - - - - - VOL
NOTES: A, A read cycle or a read-modify-write cycle can be intermixed with write cycles as long as read and read-modify-write timing
specifications are not violated,
B. Referenced to CAS or W. whichever occurs last
Figure 7. Enhanced Page-Mode Write Cycle Timing
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
9-41
SMJ4C1024
1048 576·81T DYNAMIC RANDOM·ACCESS MEMORY
SGMS023S'-OECEMBER 1986-REVISEO MARCH 1992
PARAMETER MEASUREMENT INFORMATION
tw(RH) ~
14101111f-----------tw(RL)P -----------I~~}I
N~--------------------....;~
I I
I""
hi
I
I I""
td(RLCH)
I r'
I,.-- td(RLCL) ~
I
I tsu(CA)
-,
AO-AS
~
tw(CH)
~\X
I ~
: th(RLPA) I
I j'OIIII
~ td(RI-CA) I
t.j I+- th(RA)
I
I
~ tSU(RA) I
I
10IIII
I
I
~
~ ts'l(rd)
I ..l
r"
I i !+
W~· I
I
~I
I
I
I
I
I
o
~
td(CAWL);-:l
:
I
tsu(O)
'"
j..- ta(C) ~
I
I'f--- ta(CA) ~
10IIII141----- ta(R)
"I
N
tsu(WCH) -I"'If-----.!~
:..- tsu(WRH)
I
\L
.,j
III
~
I
&'2~n~~aJ~
I
VIH
VIL
I
,""~~~~~~VIH
Valid
~~~~
I
I
IOIIII-ldls(CH) ~
I
I
141..- - - ta(CP) - - - - . t
I
I
Q
II
I
I
-t:
___J
!"--- VIL
~,.,. .,. .,." '~,J,. ~ n't" '(c" '~E" 'e0<50" " " " ': :
eo.m,
I I ~th(O)
I+:
I
I
I
I II
I II
~
I
~~~~~~~~~I'-
:
I
I
I
VIH
id-----VIH
\"{
~I
~
N
I
~
Id(CHRL
I II
: II
~ tw(W~)
10IIII
I I I
I
I
I
10IIII- td(CLWL)
"?I
_tdfRLWL)
I
th(CA)
)
A
~
14- td(CLRH) ~
I
~
II1II
}1
~
~ ~,'m:
II I
I
~ tw(CL) - . : I
:
I
tc(PM)"
I+-
~
I I
(see Note A)
(see Note A)
VOH
VOL
NOTES: A. Output may go from high impedance to an invalid state prior to the specified access time.
B. A read or a write cycle can be Intermixed with read-modify-write cycles as long as the read and write timing specifications are not
violated.
Figure 8. Enhanced Page-Mode Read-Modify-Write Cycle Timing
TEXAS ~
INSTRUMENTS
9-42
POST OFFICE BOX 1443· HOUSTON. TEXAS 77001
SMJ4C1024
1 048 576·81T DYNAMIC RANDOM·ACCESS MEMORY
SGMS023B-DECEMBER 1988-REVISED MARCH 1992
PARAMETER MEASUREMENT INFORMATION
w~H~1H~:::
D~H~**~VIH
VIL
VOH
Q
---------------HI-Z---------------vOL
Figure 9. RAS·Only Refresh Timing
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
9·43
SMJ4C1024
1 048 576-BIT DYNAMIC RANDOM-ACCESS MEMORY
SGMS023B-DECEMBER 19S8-REVISED MARCH 1992
PARAMETER MEASUREMENT INFORMATION
~
14-- Memory Cycle ~
I
1+ t
I
I
I II1II- twIRL) ~ I
I
I
i
.1
I
I
I
I
!~VIH
I
td(RLCH)R
tw(CL)
Ii
I\;
I I
I
tw(RH)
Y \
I
!
~
~VIH
( I
j
I
!
T""
I
I
I~
I I
I
VIL
14~
I i + ! *-i th(CA)
i I -.I *H-III t s4 (CA)
VIL
I
I
I
1+[-1 I I
tsu(RA) ~ j4- / I I / I
th(RA)
1l1li
I
~ I twIRL)
I
I 1l1li
I
~
"\/
I
II
I I
I I
-.I
'i
11
RAS~
I
w(RH)
Refresh Cycle ~
~ Refresh Cycle ~
I
I
~_HJ~H_~:::
~
~
L
'Bu(rd) 11
WW'l
I
I
I/ w I
~ I
I
:!
I I
/
I
14- th(RHrd)
.
.
~~ 16
3-- 11--
d
e
128KArray
10
128KArray
f
/
TEXAS ~
INSTRUMENTS
9-50
I/O
Buffers
1 of 16
Selection
POST OFFICE BOX 1443· HOUSTON. TEXAS 77001
~.+- o
In
Reg.
~
Out
Reg.
Q
SMJ44100
4194 304-WORD BY 1·BIT
DYNAMIC RANDOM·ACCESS MEMORY
SGMS040B-JANUARY 1991-REVISED JULY 1991
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Voltage range on any pin (see Note 1) ................................................. -1 V to 7 V
Voltage range on Vee ............................................................... - 1 V to 7 V
Short circuit output current ................................................................ 50 mA
Power dissipation .......................................................................... 1 W
Operating temperature ........................................................... - 55°C to 125°C
Storage temperature range ....................................................... - 65°C to 150°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maxim urn-rated conditions for extended periods may affect device reliability.
NOTE I: All voltage values in this data sheet are with respect to VSS.
recommended operating conditions
MIN
NOM
MAX
VCC
Supply voltage
4.5
5
5.5
V
VIH
High-level input voltage
2.4
6.5
V
Vil
low-level input voltage (see Note 2)
-I
0.8
TA
Min operating temperature
TC
Max operating case temprature
-55
..
V
'c
125
..
UNIT
..
'c
NOTE 2: The algebraic convention, where the more negative (less positive) limit IS deSignated as minimUm, IS used In thiS data sheet for logiC
voltage levels only.
electrical characteristics over full ranges of recommended operating conditions (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
VOH
High-level output voltage
IOH =-'-5mA
VOL
low-level output voltage
10l= 4.2 rnA
II
'44100-10
'44100-80
MIN
MAX
2.4
MIN
'44100-12
MAX
2.4
MIN
MAX
2.4
UNIT
V
0.4
0.4
0.4
V
Input current (leakage)
VI = 0 to 6.5 V, VCC = 5.5 V,
All other pins = 0 V to VCC
±10
±IO
±10
f1A
10
Output current (leakage)
Vo = 0 to Vcc,
Vcc = 5.5 V, CAS high
±IO
±IO
±10
f1A
ICCI
Read or write cycle current
(see Note 3)
Minimum cycle, VCC = 5.5 V
85
80
70
rnA
ICC2
Standby cu rrent
After I memory cycle,
RAS and CAS high, VIH = 2.4 V (TTl)
4
4
4
rnA
ICC3
Average refresh current
(RAS-only, or CSR)
(see Note 3)
Minimum cycle, VCC = 5.5 V,
RAS cycling, CAS high (RAS-only),
RAS low, after CAS low (CSR)
85
75
65
rnA
ICC4
Average page current
(see Note 4)
tpc = minimum, VCC = 5.5 V,
RAS low, CAS cycling
50
40
35
rnA
NOTES:
3. Measured with a maximum of one address change while RAS = VIL.
4. Measured with a maximum of one address change while CAS = VIH.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
9-51
SMJ44100
4194 304-WORD BY 1-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SGMS040B-JANUARY 1991-REVISED JULY 1991
capacitance over recommended ranges of supply voltage and operating temperature,
f = 1 MHz (see Note 5)
PARAMETER
MIN
TYP
MAX
UNIT
CilAl
Input capacitance, address inputs
7
pF
CiID}
Input capacitance, data inputs
7
pF
Ci(RG)
Input capacitance, strobe inputs
10
pF
Ci(W}
Input capacitance, write-enable input
10
pF
Co
Output capacitance
10
pF
"
NOTE 5: VCC equal to 5 V:!: 0.5 V and the bias on pinS under test IS 0 V. Capacitance IS sampled only at .Initial
design and after any major change .
switching characteristics over recommended ranges of supply voltage range and operating
temperature
PARAMETER
MIN
'44100-12
'44100-10
'44100-80
MAX
MIN
MAX
MIN
MAX
UNIT
tM
Access time from column-address
40
50
55
ns
tCAC
Access time from CAS low
20
25
30
ns
tCPA
Access time from column precharge
45
50
55
ns
tRAC
Access time from RAS low
80
100
120
ns
Output disable time after CAS high (see Note 6)
20
25
toFF
NOTE 6: tOFF IS specified when the output IS no longer driven. The output is disabled when CAS IS brought high.
30
ns
TEXAS ~
INSTRUMENTS
9-52
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
SMJ44100
4194 304·WORD BY 1·BIT
DYNAMIC RANDOM·ACCESS MEMORY
SGMS040B-,JANUARY 1991-REVISED JULY 1991
timing requirements over recommended ranges of supply voltage and operating temperature
'44100-80
MAX
MIN
'44100·10
MIN
MAX
'44100·12
MIN
MAX
UNIT
tRC
Random read or write cycle (see Note 7)
150
180
210
ns
tRWC
Read-write cycle time
175
210
245
ns
tpc
Page-mode read or write cycle time (see Note 8)
50
60
65
ns
tpRWC
Page-mode read-write cycle time
70
85
95
tRASP
Page-mode pulse duration, RAS low (see Note 9)
80
100000
tRAS
Non-page-mode pulse duration, RAS low (see Note 9)
80
teAS
Pulse duration, CAS low (see Note 10)
20
tcp
Pulse duration, CAS high
10
10
15
ns
tRP
Pulse duration, RAS high (precharge)
60
70
80
ns
twp
Write pulse duration
15
20
25
ns
tASC
Column-address setup time before CAS low
0
0
0
ns
tASR
Row-address setup time before RAS low
0
0
0
ns
tDS
Data setup time (see Note 11)
0
0
0
ns
tRCS
Read setup time before CAS low
0
0
0
ns
tCWL
W-Iow setup time before CAS high
20
25
30
ns
tRWL
W-Iow setup time before RAS high
20
25
30
ns
twcs
W-Iow setup time before CAS low
(Early write operation only)
0
0
0
ns
twSR
W-high setup time (CAS-before-RAS refresh only)
10
10
10
ns
tCAH
Column-address hold time after CAS low
15
20
20
ns
tDHR
Data hold time after RAS low
60
75
90
ns
tDH
Data hold time (see Note11)
15
20
25
ns
tAR
Column address hold time after RAS low (see Note 13)
60
75
90
ns
tRAH
Row-address hold time after RAS low
10
15
15
ns
tRCH
Read hold time after CAS high (see Note 12)
0
0
0
ns
tRRH
Read hold time after RAS high (see Note 12)
0
0
0
ns
twCH
Write hold time after CAS low
(Early write operation only)
15
20
25
ns
twCR
Write hold time after RAS low (see Note 10)
60
75
90
ns
twHR
W high hold time (CAS-before-RAS refresh only)
10
10
10
ns
tAWD
Delay time, column address to W low
(Read-write operation only)
40
50
55
ns
ns
100 100000
120
100000
ns
10 000
100
10000
120
10000
ns
10 000
25
10000
30
10000
ns
Continued next page.
NOTES: 7. All cycle times assume tT = 5 ns.
8. To assure tpc min, tASC should be greater than or equal to tcp.
9. In a read-write cycle, tRWD and tRWL must be observed.
10. In a read-write cycle, tCWD and tCWL must be observed.
11. Referenced to the later of CAS or Vii in write operations.
12. Either tRRH or tRCH must be satisfied for a read cycle.
13. The minimum value is measured when tRDC is set to tRCD min as a reference.
TEXAS ~
INSIRUMENTS
POST OFFICE BOX 1443' HOUSTON. TEXAS 77001
9-53
SMJ44100
4194 304-WORD BY 1·BIT
DYNAMIC RANDOM·ACCESS MEMORY
SGMS040B-.JANUARY 1991-REVISED JULY 1991
timing requirements over recommended supply voltage range and operating temperature range
'44100~10
'44100-80
MIN
tCHR
I
Delay time, RAS low to CAS high
(CAS-before-RAS refresh only)
MAX
MIN
20
'44100-12
MAX
20
MIN
UNIT
MAX
25
ns
tCRP
Delay time, CAS high to RAS low
0
0
0
ns
tCSH
Delay time, RAS lowto CAS high
80
100
120
ns
tCSR
Delay time, CAS low to RAS low (CAS-before-RAS refresh only)
10
10
10
ns
tCWD
Delay time, CAS low to W low {Read-write operation only)
20
25
30
tRAD
Delay time, RAS low to column-address (see Note 14)
15
tRAL
Delay time, column-address to RAS high
40
50
55
tCAL
Delay time, column-address to CAS high
40
50
55
tRCD
Delay time, RAS low to CAS low (see Note 14)
20
40
20
60
25
50
75
20
25
ns
65
ns
ns
ns
90
ns
tRPC
Delay time, RAS high to CAS low
0
0
0
ns
tRSH
Delay time, CAS low to RAS high
20
25
30
ns
tRWD
Delay time, RAS low to W low
(Read-write operation only)
80
100
120
ns
tCLZ
CAS to output in low Z (see Note 15)
tREF
Refresh time interval
IT
Transition time (see Note 16)
16
16
16
ms
..
NOTES: 14. Maximum value specified only to assure access time .
15. Valid data is presented at the output after all access times are satisfied. The output may go from three-state to an invalid data state
prior to the specified access times as the output is driven when CAS goes low.
16. Transition times (rise and fall) for RAS and CAS are to be minimum of 3 ns and maximum of 50 ns.
PARAMETER MEASUREMENT INFORMATION
1.31 V
~
Output Under Test
RL
Vee =5V
=
218 g
~
CL~I00PF
Output Under Test - - - . - -.......
T
CL
(a) Load Circuit
= 100 pF
(b) Alternate Load Circuit
Figure 1. Load Circuits for Timing Parameters
TEXAS
~
INsrRUMENTS
9-54
POST OFFICE BOX 1443· HOUSTON. TEXAS 77001
R2
= 295
g
SMJ44100
4 194 304·WORD BY 1·BIT
DYNAMIC RANDOM·ACCESS MEMORY
SGMS040B-JANUARY 1991-REVISED JULY 1991
PARAMETER MEASUREMENT INFORMATION
NOTE A: Valid data is presented at the output after all access times are satisfied. The output may go from three-state to an invalid data state
prior to the specified access times as the output is driven when CAS goes low.
Figure 2. Read Cycle Timing
ThxAs
~
INSIRUMENTS
POST OFFICE BOX 1443· HOUSTON, TEXAS 77001
9-55
SMJ44100
4194 304·WORD BY 1·B11
DYNAMIC RANDOM·ACCESS MEMORY
SGMS040B-JANUARY 1991-REVISED JULY 1991
PARAMETER MEASUREMENT INFORMATION
VOH
Q---------------HI-Z--------------- VOL
Figure 3. Early Write Cycle Timing
TEXAS
~
INSTRUMENTS
9-56
POST OFFICE BOX 1443· HOUSTON, TEXAS 77001
SMJ44100
4194 304·WORD BY 1·BIT
DYNAMIC RANDOM·ACCESS MEMORY
SGMS040B-,JANUARY 1991-REVISED JULY 1991
PARAMETER MEASUREMENT INFORMATION
~
AO-A10
~
NOTE A: Valid data is presented at the output after all access times are satisfied. The output may go from three-state to an invalid data state prior
to the specified access times as the output is driven when CAS goes low.
Figure 4. Write Cycle Timing
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443· HOUSTON. TEXAS 77001
9-57
SMJ44100
4194 304·WORD BY 1·BIT
DYNAMIC RANDOM·ACCESS MEMORY
SGMS040B--JANUARY 1991-REVISED JULY 1991
PARAMETER MEASUREMENT INFORMATION
,
,
'~4~-------------------tRWC--------------------~.~'
, '4
tRAS
~!
RAS
-----------------+1.,'
,
iX!'-_______________-'!l1
-+i t.- IT
'4
I :----::- ,"CD ------:
i~: t~FR
1
t+
1
.,
I,
~
tCRP -.I
1 14
~
'1 4
N
~
I :"'-________
tRAH
tRAO
tCAS
. J1
~tASC
+l
I
., tCAH
14
14
.,
I4-tcWL5
14
tRWL
1 tAWO
-----.I
1
~
tRP
VIH
~ VIL
tcp ------~.i
II
-+l
14
VIH
l''----VIL
1
IT
:
"~ ~I ~~+" ·_fo~~_'----:::
I .,
I
I
I
1tRCS
I
1tCAH
14:
1 14
.1:
w~}~rPaJW : :
f
~ twp -+i
1
,
1
1
~~~~~*~~.~~aJ~~~~~VIH
}!
~
I)
1
14
1
1
1
1
~tcwo-+i 1
tRWO'
1
1
1
1 tos
1
1
:
1 (see Note A) ~'
VIL
1
1
.1
---+I;'+-
VIH
1
D~~'~f_ VOI~," ~~~~~v"
1
1
:
1
~ tCLZ --.!
---+-1 HI-Z 1
.:_
Q _ _ _-L...
I
1
i
14
1
1
~
~t
I
14- tOFF -+j
OH
Valid Out
1
~
~>-.- - - - - - -
VOH
VOL
14--- tCAC ~
tRAC
~
~
.,
NOTE A: Valid data is presented at the outputs after all access times are satisfied. The output may go from three-state to an invalid data state
prior to the specified access times as the output is driven when CAS goes low.
Figure 5. Read-Write Cycle Timing
TEXAS
~
INsrRUMENTS
9-58
POST OFFICE BOX 1443' HOUSTON. TEXAS 77001
SMJ44100
4194 304·WORD BY 1·BIT
DYNAMIC RANDOM·ACCESS MEMORY
SGMS040B-JANUARY 1991-REVISED JULY 1991
PARAMETER MEASUREMENT INFORMATION
AO-A10
teLZ
NOTES: A. Valid data is presented at the output after all access times are satisfied. The output may go from three-state to an invalid data state
prior to the specified access times as the output is driven when CAS goes low.
B. Access time is tCPA or tAA dependent.
Figure 6. Enhanced Page-Mode Read Cycle Timing
TEXAS ~
INsrRUMENTS
POST OFFICE BOX 1443· HOUSTON. TEXAS 77001
9-59
SMJ44100
4 194 304-WORD BY 1-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SGMS040B-JANUARY 1991-REVISED JULY 1991
PARAMETER MEASUREMENT INFORMATION
VOH
Q - - - - - - - - - - - - - - - - HI-Z -----------~-----
VOL
NOTES: A. Referenced to CAS or W, whichever occurs last.
B. A read cycle or a read-write cycle can be intermixed with a write cycle as long as read and read-write timing specifications are not
violated.
Figure 7. Enhanced Page-Mode Write Cycle Timing
TEXAS
-If
INsrRUMENTS
9-60
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
SMJ44100
4194 304·WORD BY 1·BIT
DYNAMIC RANDOM·ACCESS MEMORY
SGMS040B-JANUARY 1991-REVISED JULY 1991
PARAMETER MEASUREMENT INFORMATION
NOTES: A. Valid data is presented at the output after all access times are satisfied. The output may go from three-state to an invalid data state
prior to the specified access times as the output is driven when CAS goes low.
B. A read or write cycle can be intermixed with read-write cycles as long as the read and write timing specifications are not violated.
Figure 8. Enhanced Page-Mode Read-Write Cycle Timing
TEXAS ~
INsrRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
9-61
SMJ44100
4194 304-WORD BY 1-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SGMS040EMJANUARY 1991-REVISED JULY 1991
PARAMETER MEASUREMENT INFORMATION
VIH
(see Note B)
VOH
Q -----------------------------------------------------------------NOTES: A. Transition times (rise and fall) for RAS and CAS are to be minimum of 3 ns and maximum of 50 ns.
B. A 10 is a don'l care.
Figure 9. RAS·Only Refresh Timing
TEXAS ~
INSTRUMENTS
9·62
POST OFFICE BOX 1443· HOUSTON. TEXAS 77001
SMJ44100
4 194 304-WORD BY 1-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SGMS040B-JANUARY t99t-REVISED JULY t99t
PARAMETER MEASUREMENT INFORMATION
1~~----------------------tRe--------------------~
~I
~I I
~tRP~ ~1~r------------tRAS--------------~
I
I I
I I
RAS
N
AI
I
_ _oJ
_I
tRPe ~
~I
Y
_ _ _ _ _ _ _ _ _ _ _ _ _..Jf
t+- tesR ~ I
~
\{
twSR
i
I'll
I
I
VIH
VIL
1ooII~r-------teHR ----~~I
~I
tr
(see Note A)
.Y
I
~ t...1--+~It- tWHR
VIH
~
D~DiI*I~V'H
VIL
VOH
Q-----'-------------HI-Z - - - - - - - - - - - - - - - VOL
NOTES: A. Transition times (rise and fall) for RAS and CAS are to be minimum of 3 ns and maximum of 50 ns.
B. AtO is a don't care.
Figure 10. Automatic (CAS-Before-RAS) Refresh Cycle Timing
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
9-63
SMJ44100
4194 304·WORD BY 1·B11
DYNAMIC RANDOM·ACCESS MEMORY
SGMS040~ANUARY
1991-REVISED JULY 1991
PARAMETER MEASUREMENT INFORMATION
r
!4- Refresh Cycle -+j
!+-- Memory Cycle -+j
10IIII.
I
I 10II I
II
.1 I
II
11
RASN
I
I I
I
::
r-+l
tRAH-t+l~
~
~ ~tCAH
~tASC
!II I
iOIIII-t}-¥R I I I
I
AG-A10
I
Refresh Cycle ~
I
I 14
~ tRP
I
.1 I tRAS 1r,~1
t\
I
I
Tf::
i ~I
I 10II I
I
I
110II I
N 11
I
I
.
CAS!:
tAR
tRAS
tRp·
/
I I
I
t
CAS
:
tcHR
I
I
I
IH
V
iOIIII
I':!
!
I I
iJ
I I
r ::
·1
:
: :
: :
:
I I
I I
I I
I I
I I
I I
I
I
I
are
IL
I
I
I
I
on'
V
~
~~~4'l~~~~~~~¥~~~~.~\'-~~¥~~~~
j4/oil- !+- twHR
~
JOIIII- twHR
~
J+- tr'HR
VIH
VIL
Vi
~ *-~, -"Wmx
::
~
D~~~~~::
"W Ii I I
~~~
, ...
II
14 I .1 tAA
~ ~tCAC
tOFF
~~,d
Q
~
Valid Data
Figure 11. Hidden Refresh Cycle (Read)
TEXAS ~
INSTRUMENTS
9-64
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
~~
-+i
1.-
I
I
}- :::
SMJ44100
4194 304·WORD BY 1·BIT
DYNAMIC RANDOM·ACCESS MEMORY
SGMS040B-JANUARY 1991-REVISED JULY 1991
PARAMETER MEASUREMENT INFORMATION
Q
- - - - - - - - - - - H I . Z - - - - - - - - - -......',,\-'j-------Figure 12. Hidden Refresh Cycle (Write)
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443· HOUSTON, TEXAS 77001
9·65
SMJ44100
4194 304·WORD BY 1·BIT
DYNAMIC RANDOM·ACCESS MEMORY
SGMS040~ANUARY
1991-REVISED JULY 1991
TEXAS ~
INSTRUMENTS
9-66
POST OFFICE BOX 1443· HOUSTON, TEXAS nOO1
SMJ44400
1 048 576·WORD BY 4·BIT
DYNAMIC RANDOM·ACCESS MEMORY
SGMS041B-JANUARY 1991-REVISED JULY 1991
JD AND HR PACKAGESt
(TOP VIEW)
• Processed to Mll-STD-883, Class B
• Military Temperature
Range ... -55 to 125°C
DQl
DQ2
IN
• Organization ... 1 048 576 x 4
RAS
• Single 5-V Power Supply (±10% Tolerance)
A9
AO
Al
• Performance Ranges:
ACCESS ACCESS ACCESS
READ
TIME
TIME
TIME OR WRITE
SMJ44400-BO
SMJ44400-10
SMJ44400-12
(tRAC)
(MAX)
BO ns
lOOns
120 ns
(tCAC)
(MAX)
20 ns
25ns
30 ns
(tAAl
A2
A3
CYCLE
(MIN)
150 ns
IBOns
210 ns
(MAX)
40 ns
50ns
55 ns
VCC
OE
AS
A7
A6
AS
A4
HM AND CSOJ PACKAGESt
(TOP VIEW)
• Enhanced Page Mode Operation for Faster
Memory Access
- Higher Data Bandwidth Than
Conventional Page-Mode Parts
- Random Single-Bit Access Within a Row
With a Column Address
DQl
DQ2
IN
RAS
A9
• CAS-Before·RAS Refresh
• 3-State Unlatched Output
Vss
DQ4
DQ3
CAS
OE
AO
Al
A2
A3
AS
A7
VCC
A4
• long Refresh Period ...
1024-Cycle Refresh in 16 ms (Max)
• low Power Dissipation
VSS
DQ4
DQ3
CAS
A6
AS
t Packages are shown for pinout reference only.
• Texas Instruments EPIC'· CMOS Process
PIN NOMENCLATURE
• All Inputs/Outputs and Clocks are TTL
Compatible
A~A9
CAS
DQI-DQ4
OE
RAS
• Packaging Options:
- 400-mil 20/26-leadless Ceramic SOlCC
(HM Suffix)
- 20-Pin, 400-Mil Ceramic DIP (JD Suffix)
- 20-Pin Ceramic Flatpack (HR Suffix)
- 20-Pin Ceramic CSOJ
- Additional Package Options Planned
IN
VCC
VSS
Address Inputs
Column-Address Strobe
Data In/Data Out
Output Enable
Row-Address Strobe
Write Enable
5-VSupply
Ground
description
The SMJ44400 series are high-speed 4 194 304-bit dynamic random-access memories, organized as
1 048 576 words of four bits each. They employ state-of-the-art EPIC'· (Enhanced Performance Implanted
CMOS) technology for high performance, reliability, and low-power operation.
The SMJ44400 features maximum row access time of 80 ns, 100 ns, and 120 ns. Maximum power dissipation
is as low as 360 mW operating and 22 mW standby.
EPIC is a trademark of Texas Instruments Incorporated.
~~~~~t~~~~::I: .~:r:C::~~.I~~~~:~!r~~ :: Ie~:~~~~~~mde~:~
.tllndard warranty. Production proc...lng do.. not nec,".rlly Include
tilting of all parameter•.
TEXAS
~
Copyright © 1991, Texas Instruments Incorporated
INSTRUMENTS
POST OFFICE BOX 1443· HOUSTON, TEXAS 77001
9-67
SMJ44400
1 048 576·WORD BY 4·BIT
DYNAMIC RANDOM·ACCESS MEMORY
SGMS041 B-JANUARY 1991-REVISEO JULY 1991
All inputs and outputs, including clocks, are compatible with Series 54 TTL. All addresses and data-in lines are
latched on-chip to simplify system design. Data out is unlatched to allow greater system flexibility.
The SMJ44400 is offered in a 400-mil20/26-leadless ceramic surface mount SOlCC package (HM suffix), a
20-pin ceramic dual-in-line package (JD suffix), a 20-pin ceramic flatpack (HR suffix), and a 20-pin leaded
ceramic chip carrier (CSOJ). All packages are characterized for operation from -55°C to 125°C.
operation
enhanced page mode
Enhanced page-mode operation allows faster memory'access by keeping the same row address while selecting
random column addresses. The time for row-address setup and hold and address multiplex is thus eliminated.
The maximum number of columns that may be accessed is determined by the maximum RAS low time and the
CAS page cycle time used. With minimum CAS page cycle time, all 1024 columns specified by column
addresses AO through A9 can be accessed without intervening RAS cycles.
Unlike conventional page-mode DRAMs, the column-address buffers in this device are activated on the falling
edge of RAS. The buffers act as transparent or flow-through latches while CAS is high. The falling edge of CAS
latches the column addresses. This feature allows the SMJ44400 to operate at a higher data bandwidth than
conventional page-mode parts, since data retrieval begins as soon as column address is valid rather than when
CAS transitions low. This performance improvement is referred to as enhanced page mode. Valid column
address may be presented immediately after row address hold time has been satisfied, usually well in advance
of the falling edge of CAS. In this case, data is obtained aftertCAc max (access time from CAS low), iftAA max
(access time from column address) has been satisfied. In the event that column addresses for the next cycle
are valid atthe time CAS goes high, access time for the next cycle is determined by the later occurrence oftCAC
or tCPA (access time from rising edge of CAS).
address (AD-A9)
Twenty address bits are required to decode 1 of 1 048 576 storage cell locations. Ten row-address bits are set
up on inputs AO through A9 and latched onto the chip by the row-address strobe (RAS). The ten column-address
bits are setup on pins AO through A9 and latched onto the chip by the column-address strobe (CAS). All
addresses must be stable on or before the falling edges of RAS and CAS. RAS is similar to a chip enable in that
it activates the sense amplifiers as well as the row decoder. CAS is used as a chip select activating the output
buffer, as well as latching the address bits into the column-address buffer.
write enable
rN>
The read or write mode is selected through the write-enable (W)input. A logic high on the W input selects the
read mode and a logic low selects the write mode. The write-enable terminal can be driven from standard TTL
circuits without a pullup resistor. The data input is disabled when the read mode is selected. When W goes low
prior to CAS (early write), data out will remain in the high-impedance state for the entire cycle permitting a write
operation independent of the state of OE. This permits early write operation to be completed with OE grounded.
data in/out (OQ1-0Q4)
The three-state output buffer provides direct TTL compatibility (no pullup resistor required) with a fanout of two
Series 54 TTL loads. Data out is the same polarity as data in. The output is in the high-impedance (floating) state
until CAS and OE are brought low. In a read cycle the output becomes valid after all access times are satisfied.
The output remains valid while CAS and OE are low. CAS or OE going high returns it to a high-impedance state.
This is accomplished by bringing OE high prior to applying data, thus satisfying tOED'
TEXAS .".
INSTRUMENTS
9-68
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
SMJ44400
1 048 576-WORD BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SGMS041 B-JANUARY 1991-REVISED JULY 1991
output enable (OE)
OE controls the impedance ofthe output buffers. When OE is high, the buffers will remain in the high-impedance
state. Bringing OE low during a normal cycle will activate the output buffers, putting them in the low-impedance
state. It is necessary for both RAS and CAS to be brought low for the output buffers to go into the low-impedance
state. Once in the low-impedance state, they will remain in the low-impedance state until either OE or CAS is
brought high.
refresh
A refresh operation must be performed at least once every sixteen milliseconds to retain data. This can be
achieved by strobing each ofthe1 024 rows (AO-A9). A normal read or write cycle will refresh all bits in each row
that is selected. A RAS-only operation can be used by holding CAS at the high (inactive) level, thus conserving
power as the output buffer remains in the high-impedance state. Externally generated addresses must be used
for a RAS-only refresh. Hidden refresh may be performed while maintaining valid data at the output pin. This
is accomplished by holding CAS at VIL after a read operation and cycling RAS after a specified precharge period,
similar to a RAS-only refresh cycle. The external address is ignored during the hidden refresh cycles.
CAS-before-RAS refresh
CAS-before-RAS refresh is utilized by bringing CAS low earlier than RAS (see parameter tCSR) and holding
it low after RAS falls (see parameter tCHR)' For successive CAS-before-RAS refresh cycles, CAS can remain
low while cycling RAS. The external address is ignored and the refresh address is generated internally.
power up
To achieve proper device operation, an initial pause of 200 lAs followed by a minimum of eight initialization cycles
is required after full V CC level is achieved. These eight initialization cycles need to include at least one refresh
(RAS-only or CAS-before-RAS) cycle.
test mode
An industry standard Design For Test (OFT) mode is incorporated in the SMJ44400. A CAS-before-RAS with
W low (WCBR) cycle is used to enter test mode. In the test mode, data is written into and read from eight sections
of the array in parallel. All data is written into the array through 001. Data is compared upon reading and if all
bits are equal, all DO pins will go high. If anyone bit is different, all the DO pins will go low. Any combination
read, write, read-write, or page-mode can be used in the test mode. The test mode function reduces test times
by enabling the 1M x 4 DRAM to be tested as if it were a 512K DRAM where column address 0 is not used.
A RAS-only or CBR refresh cycle is used to exit the OFT mode.
TEXAS ~
INSIRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
9-69
SMJ44400
1 048 576-WORD BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SGMS041 B-JANUARY 1991-REVISED JULY 1991
logic symbol t
AO
A1
A2
A3
A4
A5
A6
A7
A8
A9
RAM 1024Kx4
9
10
11
12
20010/2100
14
15
16
17
18
>A 1 04~ 575
5
"
~
4
I'
23
W
OE
OQ1
OQ2
OQ3
OQ4
3
22
~
~
"
&
P 23C22
23210
24,25EN
G25
,-=r
1
2
24
25
20019/2109
C20[Row]
G23/[Refresh Row]
24[Power Down]
C21 [Column]
G24
4-
r:
A,220
'i7 26
A,Z26.
t This symbol is in accordance with ANSI/IEEE Std 91-1984 and lEe Publication 617-12. The pinouts illustrated are for the HM package.
functional block diagram
AO
A1
Column Decode
Sense Amplifiers
128KArray
128KArray
A9
•
•
•
16
128KArray
R
0
w
0
e
c
128KArray
••
•
0
d
e
OQ1-0Q4
128KArray
TEXAS ~
INSTRUMENTS
9-70
POST OFFICE BOX 1443· HOUSTON, TEXAS 77001
SMJ44400
1 048 576·WORD BY 4·BIT
DYNAMIC RANDOM·ACCESS MEMORY
SGMS041 B-JANUARY 1991-REVISED JULY 1991
absolute maximum ratings over operating temperature range (unless otherwise noted)t
Voltage range on any pin (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 1 V to 7 V
Voltage range on Vee ............................................................... - 1 V to 7 V
Short circuit output current ................................................................ 50 mA
Power dissipation .......................................................................... 1 W
Operating temperature
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 55°C to 125°C
Storage temperature range ........................................................ - 65°C to 150°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability,
NOTE 1: All voltage values in this data sheet are with respect to VSS,
recommended operating conditions
UNIT
MIN
NOM
MAX
VCC
Supply voltage
4,5
5
5,5
VIH
High-level input voltage
2.4
6,5
V
VIL
Low-level input voltage (see Note 2)
-1
0,8
V
TA
Min operating temperature
TC
Max operating case temperature
'c
-55
125
,
,
,
,
"
NOTE 2: The algebraic convention, where the more negative (less positive)
limit IS deSignated as minimUm, IS used
voltage levels only,
V
In
'c
this data sheet for logiC
electrical characteristics over full ranges of recommended operating conditions (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
VOH
High-level output voltage
10H ;-5 mA
VOL
Low-level output voltage
IOL;4,2 mA
II
Input current (leakage)
10
'44400-80
MIN
'44400-10
MAX
2.4
MIN
'44400-12
MAX
2.4
MIN
MAX
UNIT
V
2.4
0.4
0.4
0.4
V
VI =0 to 6,5 V, VCC =5,5 V,
All other pins; 0 V to VCC
±10
±10
±10
!JA
Output current (leakage)
Vo =0 to Vcc,
Vcc =5,5 V, CAS high
±10
±10
±10
j.lA
ICC1
Read or write cycle current
(see Note 3)
Minimum cycle, VCC ; 5,5 V
85
80
70
mA
ICC2
Standby current
After 1 memory cycle,
RAS and CAS high, VIH
4
4
4
mA
ICC3
Average refresh current
(RAS-only, or CBR)
Minimum cycle, VCC ; 5.5 V,
RAS cycling, CAS high (RAS only),
RAS low, after CAS low (CBR)
85
75
65
rnA
ICC4
Average page current
(see Note 4)
tpc; minimum, VCC; 5,5 V,
RAS low, CAS cycling
50
40
35
rnA
NOTES:
=2.4 V
3, Measured With a maximum of one address change while RAS = VIL'
4, Measured with a maximum of one address change while CAS = VIH,
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
9-71
SMJ44400
1 048 576-WORD BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SGMS041B-JANUARY 1991-REVISED JULY 1991
capacitance over recommended ranges of supply voltage and operating temperature, f = 1 MHz
(see Note 5)
PARAMETER
Ci(A)
Input capacitance, address inputs
Ci(RC)
MIN
TYP
MAK
UNIT
7
pF
Input capacitance, strobe inputs
10
pF
Ci(W)
Input capacitance, write-enable input
10
pF
Co
Output capacitance
10
pF
NOTE 5: VCC equal to 5 V ± 0.5 V and the bias on pinS under test IS 0 V. Capacitance IS sampled only at Initial design and after any malor change.
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature
'44400-80
MIN
'44400-10
MAX
MIN
'44400-12
MAX
MIN
MAX
UNIT
tM
Access time from column-address
40
45
55
ns
tCAC
Access time from CAS low
20
25
30
ns
tCPA
Access time from column precharge
45
50
55
ns
tRAC
Access time from RAS low
80
100
120
ns
tOEA
Access time from OE low
20
25
30
ns
tOFF
Output disable time after CAS high (see Note 6)
20
25
30
ns
tOEZ
Output disable time after OE high (see Note 6)
20
25
30
ns
..
NOTE 6: toFF and tOEZ are specified when the output is no longer driven. The outputs are disabled by bringing either OE or CA~ high.
TEXAS
~
INSTRUMENTS
9-72
POST OFFICE BOX 1443· HOUSTON. TEXAS 77001
SMJ44400
1 048 576·WORD BY 4·BIT
DYNAMIC RANDOM·ACCESS MEMORY
SGMS041 B-JANUARY 1991-REVISED JULY 1991
timing requirements over recommended ranges of supply voltage and operating temperature
'44400-80
MIN
'44400-10
MAX
MIN
'44400-12
MAX
MIN
MAX
UNIT
tRC
Random read or write cycle (see Note 7)
150
180
210
ns
tRWC
Read-write cycle time
205
245
285
ns
tpc
Page-mode read or write cycle time (see Note 8)
tpRWC
Page-mode read-write cycle time
tRASP
Page-mode pulse duration, RAS low (see Note 9)
80
100000
100
100000
120
100000
ns
tRAS
Non-page-mode pulse duration, RAS low (see Note 9)
80
10000
100
10000
120
10000
ns
10000
25
10 000
30
10 000
ns
50
60
65
ns
100
120
135
ns
tCAS
Pulse duration, CAS low (see Note 10)
20
tcp
Pulse duration, CAS high
10
10
15
ns
tRP
Pulse duration, RAS high (precharge)
60
70
80
ns
twp
Write pulse duration
15
20
25
ns
tASC
Column-address setup time before CAS low
0
0
0
ns
tASR
Row-address setup time before RAS low
0
0
0
ns
tDS
Data setup time (see Note 11)
0
0
0
ns
tRCS
Read setup time before CAS low
0
0
0
ns
tCWL
W low setup time before CAS high
20
25
30
ns
tRWL
W low setup time before RAS high
20
25
30
ns
twcs
W low setup time before CAS low
(Early write operation only)
0
0
0
ns
twSR
W high setup time (CAS-before-RAS refresh only)
10
10
10
ns
tCAH
Column-address hold time after CAS low
15
20
20
ns
tDHR
Data hold time after RAS low
60
75
90
ns
tDH
Data hold time (see Note 11)
15
20
25
ns
tAR
Column-address hold time after RAS low (see Note 10)
60
75
90
ns
tRAH
Row-address hold time after RAS low
10
15
15
ns
tRCH
Read hold time after CAS high (see Note 12)
0
0
0
ns
tRRH
Read hold time after RAS high (see Note 12)
0
0
0
ns
twCH
Write hold time after CAS low
(Early write operation only)
15
20
25
ns
twCR
Write hold time after RAS low (see Note 10)
60
75
90
ns
twHR
W high hold time (CAS-before-RAS refresh only)
10
10
10
ns
tAWD
Delay time, column-address to W low
(Read-write operation only)
70
80
90
ns
Conlinued next page.
NOTES: 7. All cycle times assume tT = 5 ns.
8. To assure tpc min, tASC should be greater than or equal to tcp.
9. In a read-write cycle, tRWD and tRWL must be observed.
10. In a read-write cycle, leWD and tCWL must be observed.
11. Referenced to the later of CAS or Vi in write operations.
12. Either tRRH or tRCH must be satisfied for a read cycle.
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443· HOUSTON. TEXAS 77001
9-73
SMJ44400
1 048 576·WORD BY 4·BIT
DYNAMIC RANDOM·ACCESS MEMORY
SGMS041 B-JANUARY 1991-REVISED JULY 1991
timing requirements over recommended ranges of supply voltage and operating temperature
'44400-80
MIN
tCHR
Delay time, RAS low to CAS high
(CAS-before-RAS refresh only)
tCRP
Delay time, CAS high to RAS low
tCSH
tCSR
'44400-10
MAX
MIN
'44400-12
MAX
MIN
MAX
UNIT
20
20
25
ns
0
80
0
100
0
120
ns
Delay time, RAS low to CAS high
Delay time, CAS low to RAS low
(CAS-before-RAS refresh only)
10
10
10
ns
50
20
20
20
15
40
40
20
0
20
110
60
25
25
25
20
50
50
25
0
25
135
70
30
30
30
20
55
55
25
0
30
160
ns
tCWD
. Delay time, CAS low to W low (Read-write operation only)
tOEH
OE command hold time
toED
OE to data delay
tROH
RAShoid time referenced to OE
tRAD
Delay time, RAS low to column-address (see Note 13)
tRAl
Delay time, column-address to RAS high
tCAl
Delay time, column-address to CAS high
tRCD
Delay time, RAS low to CAS low (see Note 13)
tRPC
Delay time, RAS high to CAS low
tRSH
Delay time, CAS low to RAS high
tRWD
Delay time, RAS low to W low (Read-write operation only)
tREF
Refresh time interval
IT
Transition time (see Note 15)
40
60
16
50
75
ns
ns
ns
ns
65
ns
ns
ns
90
ns
ns
ns
ns
16
16
..
ms
NOTES: 13. Maximum value speCified only to assure access time .
14. Valid data is presented at the outputs after all access times are satisfied but may go from three-state to an invalid data state prior
to the specified access times as the outputs are driven when CAS goes low.
15. Transition times (rise and fall) for RAS and CAS are to be a minimum of 3 ns and a maximum of 50 ns.
PARAMETER MEASUREMENT INFORMATION
1.31 V
~
Output Under Test
Rl
-l
T
VCC =5V
= 218 Q
Output Under Test - - - . - - - - .
CL=100pF
Cl=100pF
R2
(b) Alternate load Circuit
(a) load Circuit
Figure 1. Load Circuits for Timing Parameters
TEXAS
~
INSTRUMENTS
9-74
= 295
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
Q
SMJ44400
1 048 576·WORD BY 4·BIT
DYNAMIC RANDOM·ACCESS MEMORY
SGMS041 B-JANUARY 1991-REVISED JULY 1991
PARAMETER MEASUREMENT INFORMATION
w2Z~*~~t~W!
I
I
DQ1------+il--HI-Z
DQ4
I
I..
i
:.-- tCAC ~
tAA.1
I
I"
t:JJO../:
:I
:..
I
~~*2~*K~
.1
tOFF
tRAC
~tOEA~
IL
I
:
--:1?'>-_______
Valid Data Out
(see Note A) ~'---r. _ _ _ _ _ _
-
I
.1
I
:IH
I
I
OE~~i~c~*~~tROH ~
I
I
VOH
VOL
~tOEZ
I
_~r2f2W2
VIH
VIL
NOTE A: Valid data is presented at the outputs after all access times are satisfied but may go from three-state to an invalid data state prior to
the specified access times as the outputs are driven when CAS goes low.
Figure 2. Read Cycle Timing
TEXAS •
INSTRUMENTS
POST OFFICE BOX 1443· HOUSTON. TEXAS 77001
9-75
SMJ44400
1 048 576·WORD BY 4·BIT
DYNAMIC RANDOM·ACCESS MEMORY
SGMS041~ANUARY
1991-REVISED JULY 1991
PARAMETER MEASUREMENT INFORMATION
DQ1-DQ4~1
Valid Data
~~r0~~:::
1~"----tDHR ----~.I
Figure 3. Early Write Cycle Timing
TEXAS ."
INSTRUMENTS
9-76
POST OFFICE BOX 1443· HOUSTON, TEXAS 77001
SMJ44400
1 048 576·WORD BY 4·BIT
DYNAMIC RANDOM·ACCESS MEMORY
SGMS041B-JANUARY 1991-REVISED JULY 1991
PARAMETER MEASUREMENT INFORMATION
Figure 4. Write Cycle Timing
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443· HOUSTON, TEXAS 77001
9-77
SMJ44400
1 048 576-WORD BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SGMS041 B-JANUARY 1991-REVISED JULY 1991
PARAMETER MEASUREMENT INFORMATION
OQ1-0Q4---..L.
1----------fMt
Valid
OE~
I~
1111
III I
I
~tCWL---.I
I
I
I
I
.1
Valid Out
(see Note A)
.1
tOEH
I
I
I
!~I
ValId
VIHNOH
I
VILNOL
I
'1'"1_ _ _ _ _ _ _
-
In
I:
~
I"
I
.1
tOED
,
,
\..J~----'*'~'l"l'''"'t7':''"''~
. ~~~
. ... t7'.:~. .~~~:::
..
'l''l'.....
NOTES: A
Valid data is presented at the outputs after all access times are satisfied but may go from three-state to an invalid data state prior
to the specified access times as the outputs are driven when CAS goes low.
B. A read or write cycle can be intermixed with read-write cycles as long as the read and write timing specifications are not violated.
Figure 8. Enhanced Page-Mode Read-Write Cycle Timing
TEXAS •
INSTRUMENTS
POST OFfiCE BOX 1443 • HOUSTON, TEXAS 77001
9-81
SMJ44400
1 048 576·WORD BY 4·BIT
DYNAMIC RANDOM·ACCESS MEMORY
SGMS041lhJANUARY 1991-REVISED JULY 1991
PARAMETER MEASUREMENT INFORMATION
I~
.1
IRC
~IRAS-+j
_ _ _ _ _ _ _ _ _ _ _ _ _ _---.il I
I
1
RAS
ICRP~'{
1
J
VIH
~~IRP~\'----VIL
i ~ ii
I I -+I
~
I I..
~I
I..
~I
OQ1-0Q4 _ _ _ _ _
(see Nole A)
r--
j+I
i+- twHR ,
~
tCAC
lAA
IRAC
~
i+- twHR
~ tw/i R
1
-+i l+1 VOH
----1:1-:------.....,,;>tOFF
~r:--....:..::..:.;;..-------v-al-Id-o-a-ta-O-u-t
tOEZ~
I
I
VOL
I...-
tOEA
~
~VIH
OE~
',')
-VIL
NOTE A: Valid data is presented at the outpuis after all access times are satisfied but may go from three-state to an invalid data state prior to the
specified access times as the outputs are driven when CAS goes low,
Figure 11. Hidden Refresh Cycle (Read)
TEXAS ~
INsrRUMENTS
9-84
POST OFFICE BOX 1443· HOUSTON, TEXAS 77001
SMJ44400
1 048 576·WORD BY 4·BIT
DYNAMIC RANDOM·ACCESS MEMORY
SGMS041 B-JANUARY 1991-REVISED JULY 1991
PARAMETER MEASUREMENT INFORMATION
DQ1-DQ4~
Figure 12. Hidden Refresh Cycle (Write)
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443· HOUSTON, TEXAS 77001
9-85
SMJ44400
1 048 576·WORD BY 4·BIT
DYNAMIC RANDOM·ACCESS MEMORY
SGMS041 B-JANUARY 1991-REVISED JULY 1991
TEXAS ~
INSI'RUMENTS
9-86
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
SMJ416100
16777216·BIT
DYNAMIC RANDOM·ACCESS MEMORY
SGMS045-NOVEMBER 1992
•
•
•
Organization ••. 16777216 x 1
Single 5-V Power Supply (10% Tolerance)
Performance Ranges:
SMJ416100-60
SMJ41 61 00-70
SMJ41 61 00-80
SMJ416100-10
•
•
•
•
•
•
•
FNC PACKAGEt
(TOP VIEW)
VCC
ACCESS ACCESS ACCESS READ
TIME
TIME
TIME OR WRITE
tAA
CYCLE
tRAC
tCAC
(MAX)
(MAX)
(MAX)
(MIN)
60 ns
15 ns
30 ns
110 ns
70 ns
18 ns
35 ns
130 ns
80 ns
20 ns
40 ns
150 ns
lOOns
25ns
45ns
180ns
Q
NC
NC
CAS
NC
A9
IN
RAS
A11
Enhanced Page Mode Operation for Faster
Memory Access
CAS-Before-RAS Refresh
Long Refresh Period __ . 4096 Cycles
Refresh in 64 ms
3-State Unlatched Output
Low Power Dissipation
All Inputs, Outputs and Clocks Are
TTL Compatible
Operating Free-Air Temperature Range
•.. - 55°C to 125°C
AS
A1D
AD
A1
A7
A6
A5
A2
A3
VCC
A4
Vss
HKB PACKAGEt
(TOP VIEW)
description
The SMJ416100 series are high-speed
16 777 216-bit
dynamic
random-access
memories, organized as 16 777 216-bit words by
one bit each. They employ EPIC'" (Enhanced
Process Implanted CMOS) technology for high
performance, reliability, and low power at a low
cost.
I
28
2
27
VCC
D
NC
3
26
NC
IN
4
25
CAS
RAS
A11
NC
NC
A1D
AD
A1
5
24
6
7
8
23
22
NC
A9
NC
NC
9
10
II
12
13
14
A2
A3
VCC
These devices feature maximum RAS access
times of 60 ns, 70 ns, 80 ns, and 100 ns.
All inputs, outputs, and clocks are compatible with
Series 54 TIL. All addresses and data-in lines are
latched on-chip to simplify system design. Data
out is unlatched to allow greater system flexibility.
VSS
D
21
20
19
18
17
VSS
Q
AS
A7
A6
A5
16
A4
15
VSS
t Packages are shown for pinout reference only.
PIN NOMENCLATURE
AO--AII
CAS
D
NC
The SMJ4161 00 is offered in 450-mil 24/28-pin
surface mount SOlCC (FNC suffix) and flatpack
(HKB suffix) packages. The packages are
characterized for operation from - 55°C to 125°C.
Q
RAS
operation
IN
enhanced page mode
Vss
VCC
Address Inputs
Column-Address Strobe
Data In
No Internal Connection
Data Out
Row-Address strobe
Write Enable
5-V Supply
Ground
Page mode operation allows effectively faster memory access by keeping the same row address and strobing
random column addresses onto the chip. Thus, the time required to set up and strobe row addresses for the
same page is eliminated. The maximum number of columns that can be addressed is determined by tRAS, the
maximum RAS-Iow width.
EPIC is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA IntormlUon II currant II 01 pubHcaUon
dllt. Productl conform 10 .peclftcltlon. per the tlrml of
Tlxulnllrumentaltlnd.rd warranty. Production proeml"g
do.. not nec....rlfy klclud. ""'ng of ,II parametert.
TEXAS
~
Copyright © 1992. Texas Instruments Incorporated
INSTRUMENTS
POST OFFICE BOX 1443· HOUSTON, TEXAS 77001
9-87
SMJ416100
16777216·BIT
DYNAMIC RANDOM·ACCESS MEMORY
SGMS045-NOVEMBER 1992
The column address buffers in this CMOS device are activated on the falling edge of RAS. They act as a
transparent or flow-through latch, while CAS is high. The falling edge of CAS latches the addresses into these
buffers and also serves as an output enable.
This feature allows the SMJ4161 00 to operate at a higher data bandwidth than conventional page-mode parts,
since retrieval begins as soon as the column address is valid, rather than when CAS transitions low. The
performance improvement is referred to as enhanced page mode. Valid column address may be presented
immediately after row address hold time has been satisfied, usually well in advance of the falling edge of CAS.
In this case, data is obtained after tCAC max (access time from CAS low), if tAA max (access time from column
address) and tRAC have been satisfied. In the event that the column address for the next cycle is valid at the
time CAS goes high, access time is determined by the later occurrence of tCPA or tCAC'
address (AD-A11)
Twenty-four address bits are required to decode 1 of 16 777 216 storage cell locations. Twelve row-address bits
are set on inputs AD through A11 and latched onto the chip by the row-address strobe (RAS). Twelve
column-address bits are set on AD through A 12 and latched onto the chip by the first column-address strobe
(CAS). Row address A 11 is required during a normal access and during RAS-only refresh as the device requires
4096 refresh cycles. All addresses must be stable on or before the falling edges of RAS and CAS. RAS is similar
to a chip enable in that it activates the sense amplifiers as well as the row decoder. CAS is used as a chip select,
activating the output buffer, as well as latching the address bits into the column buffer.
write enable (W)
The read or write mode is selected through the write-enable W input. A logic high on the W input selects the
read mode and a logic low selects the write mode. The write-enable terminal can be driven from standard TTL
circuits without a pullup resistor. The data input is disabled when the read mode is selected. When W goes low
prior to CAS (early write), data out will remain in the high-impedance state for the entire cycle, permitting
common I/O operation.
data in (0)
Data is written during a write or read-modify-write cycle. Depending on the mode of operation, the falling of CAS
or W strobes data into the on-Chip data latch. In an early-write cycle, W is brought low prior to CAS and data
is strobed in by CAS with setup and hold times referenced to this Signal. In a delayed-write or read-modify-write
cycle, CAS will already be low, thus data will be strobed in by W with setup and hold times referenced to this
signal.
data out (Q)
The three-state output buffer provides direct TTL compatibility (no pullup resistor required) with a fan-out of two
Series 54 TTL loads. The output is in the high-impedance (floating) state until CAS is brought low. In a read cycle
the output becomes valid atthe latest occurrence oftRAC, tAA, tCAC, ortCPA and remains valid while CAS is low.
CAS going high returns it to a high-impedance state. In a delayed-write or read-modify-write cycle, the output
does not change, but retains the state just read.
TEXAS
~
INsrRUMENTS
9-88
POST OFFICE BOX 1443' HOUSTON. TEXAS 77001
SMJ416100
16 777 216·BIT
DYNAMIC RANDOM·ACCESS MEMORY
SGMS04!r-NOVEMBER 1992
refresh
A refresh operation must be performed at least once every 64 ms to retain data. This can be achieved by strobing
each of the 4096 rows (AO-A11). A normal read or write cycle will refresh all bits in each row that is selected.
A RAS-only operation can be used by holding CAS at a high (inactive) level, thus conserving power since the
output buffer remains in the high-impedance state. Externally generated addresses must be used for a RAS-only
refresh. Hidden refresh may be performed by holding CAS at VIL after a read operation and cycling RAS after
the specified precharge period, similar to a RAS-only refresh cycle except with CAS held low. Valid data is
maintained at the output throughout the hidden refresh cycle. An internal refresh address provides the refresh
address during hidden refresh.
CAS-before-RAS refresh
CAS-before-RAS refresh is utilized by bringing CAS low earlier than RAS (see parameter tc~and holding
it low after RAS falls (see parameter tCHR)' For successive CAS-before-RAS refresh cycles, CAS can remain
low while cycling RAS. For this mode of refresh, the external addresses are ignored and the refresh address
is generated internally.
power up
To achieve proper device operation, an initial pause of 200 fls followed by a minimum of eight initialization cycles
is required after full V CC level is achieved. These eight initialization cycles need to include at least one refresh
(RAS-only or CAS-before-RAS) cycle.
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
9-89
SMJ416100
16 777 216·811
DYNAMIC RANDOM·ACCESS MEMORY
SGMS045-NOVEMBER 1992
logic symbol t
RAM 16 MEG x 1
AO
A1
A2
A3
A4
AS
A6
A7
A8
A9
A10
A11
10
11
12
13
16
17
18
19
20
23
31023/21011
C30 [ROW]
G33 [REFRESH ROW]
34 [PWR OWN]
f'..
C31 [COL]
G34
&
i> 33C32
,.....
25
o
>A 16 7770 215
9
6
5
Vi
30012/2100
4
2
~
~
~
33310
A, 320
MEN
27
AV
Q
tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and lEG Publication 617-12.
functional block diagram
,
AO
A1
A11
t t t
l
Timing and Control
8
/
•
•
•
Column
Address
Buffers
Column Decode
4
Sense Amplifiers
-I-
256KArrey
256KArray
L
•
•
•
'---
32
Row
Address
Buffers
•
••
11
/
-
~
1..-
:s.
~
256KArray
R
0
w
0
a
c
-±
256KArray
•
•
•
>32
4~
0
d
256KArray e
11
256KArray
'f
/
TEXAS ~
INSTRUMENTS
9-90
I/O
Buffers
1 of 32
Selection
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
1~
~
~
In
Reg.
Out
Reg.
o
Q
SMJ416100
16777 216·81T
DYNAMIC RANDOM·ACCESS MEMORY
SGMS045-NOVEMBER 1992
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Voltage range on any pin (see Note 1) ................................................ - 1 V to 7 V
Voltage range on Vee . . . . . . . . . . . . . . . .. . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . .. - 1 V to 7 V
Short circuit output current ................................................................ 50 mA
Power dissipation .......................................................................... 1 W
Operating free-air temperature range .............................................. - 55°C to 125°C
Storage temperature range ....................................................... - 65°C to 150°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values in this data sheet are with respect to vss.
recommended operating conditions
MIN
NOM
MAX
VCC
Supply voltage
4.5
5
5.5
UNIT
VIH
High-level input voltage
2.4
6.5
V
VIL
Low-level input voltage (see Note 2)
-1
0.8
V
TA
Operating free-air temperature
-55
125
'c
V
NOTE 2: The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used in this data sheet for logic
voltage levels only.
electrical characteristics over full ranges of recommended operating conditions (unless otherwise
noted)
PARAMETER
TEST
CONDITIONS
VOH
High-level output
voltage
10H =-5 mA
VOL
Low-level output
voltage
IOL=4.2 mA
II
Input current
(Ieakage)*
VI = 0 to 6.5 V,
All other pins =
OVtoVCC
10
Output current
(Ieakage)*
~OtoVCC,
ICCl
Read or write cycle
current (see Note 3)
Minimum cycle,
VCC = 5.5 V
ICC2
Standby current
SMJ4161 00-60
MIN
MAX
2.4
CAS high
SMJ4161 00-70
MIN
MAX
2.4
SMJ4161 00-80
MIN
MAX
2.4
SMJ416100-10
MIN
MAX
2.4
UNIT
V
0.4
0.4
0.4
0.4
±10
±10
±10
±10
~A
±10
±10
±10
±10
~A
V
90
80
70
60
mA
After 1 memory cycle,
RAS and CAS high,
VIH = 2.4 V (TTL)
2
2
2
2
mA
After 1 memory cycle,
RAS and CAS high,
VIH =VCC-0.2V
(CMOS)
1
1
1
1
mA
ICC3
Average refresh
current (RAS-only or
CBR) (see Note 3)*
RAS cycling, CAS high
(RAS-only), RAS low
after CAS low (CBR)
90
80
70
60
mA
ICC4
Average page
current (see Note 4)*
RAS low, CAS cycling
70
65
60
55
mA
ICC7
Standby current
output enable*
(see Note 5)
RAS = VIH, CAS = VIL,
Data out = enabled
5
5
5
5
mA
* Minimum cycle, VCC = 5.5 V.
NOTES: 3. Measured with a maximum of one address change while RAS = VIL.
4. Measured with a maximum of one address change while CAS = VIH.
5. Measured with indicated conditions following a normal read cycle.
TEXAS
~
INSfRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
9-91
SMJ416100
16 777 216-81T
DYNAMIC RANDOM-ACCESS MEMORY
SGMS045-NOVEMBER 1992
capacitance over recommended ranges of supply voltage and operating free-air temperature,
f = 1 MHz (see Note 6)
PARAMETER
MIN
TYP
MAX
UNIT
Ci(A)
Input capacitance, address inputs
9
pF
Ci(D)
Input capacitance, data input
8
pF
Ci(RC)
Input capacitance, strobe inputs
8
pF
Ci(W)
Input capacitance, write-enable input
8
pF
Co
Output capacitance
14
pF
NOTE 6:
Capacitance is sampled only at initial design and after any major changes. Samples are tested at 0 V and 25' C with a 1 MHz signal
applied to the pin under test. All other pins are open.
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature
PARAMETER
SMJ416100-60
SMJ4161 00-70
SMJ416100-80
SMJ416100-10
MIN
MIN
MIN
MIN
MAX
MAX
MAX
MAX
UNIT
tAA
Access time from column-address
30
35
40
45
ns
tCAC
Access time from CAS low
15
18
20
25
ns
tePA
Access time from column precharge
35
40
45
50
ns
tRAC
Access time from RAS low
60
70
80
100
ns
tOFF
Output disable time after CAS high
(see Note 8)
25
ns
0
15
a
18
a
20
0
NOTE 7: Valid data is presented at the output after ali access times are satisfied but may go from a high-impedance state to an invalid data state
prior to the specified access times as the output is driven when CAS goes low.
8. tOFF is specified when the output is no longer driven. The output is disabled by bringing CAS high.
TEXAS
~
INSTRUMENTS
9-92
POST OFFICE BOX 1443· HOUSTON, TEXAS 77001
SMJ416100
16 777 216·BIT
DYNAMIC RANDOM·ACCESS MEMORY
SGMS045-NOVEMBER 1992
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
SMJ416100-60
SMJ416100-70
SMJ416100-80
SMJ416100-10
MIN
MIN
MIN
MIN
MAX
MAX
MAX
MAX
UNIT
tRC
Random read or write cycle (see Note 9)
110
130
150
180
ns
tRWC
Read-write cycle time
130
153
175
210
ns
tpc
Page-mode read or write cycle time
(see Note 10)
40
45
50
55
ns
tPRWC
Page-mode read-write cycle time
60
68
75
85
ns
tRASP
Page-mode pulse duration, RAS low
(see Note 11)
60
tRAS
Non-page-mode pulse duration, RAS low
(see Note 11)
tCAS
Pulse duration, CAS low (see Note 12)
tcp
Pulse duration, CAS high
10
10
10
10
tRP
Pulse duration, RAS high (precharge)
40
50
60
70
ns
twp
Write pulse duration
15
15
15
15
ns
tASC
Column-address setup time before CAS low
ns
0
a
a
a
Row-address setup time before RAS low
a
a
a
tASR
0
ns
tDS
Data setup time (see Note 13)
0
0
0
ns
tRCS
Read setup time before CAS low
a
a
a
a
a
tCWL
W-Iow setup time before CAS high
15
18
20
25
ns
tRWL
W-Iow setup time before RAS high
15
18
20
25
I1S
twcs
iN-low setup time before CAS low
(Early write operation only)
0
0
0
0
ns
twSR
W-high setup time
(CAS-before-RAS refresh only)
10
10
10
10
ns
tCAH
Column-address hold time after CAS low
10
15
15
15
ns
tDH
Data hold time (see Note 12)
10
15
15
15
ns
tRAH
Row-address hold time after RAS low
10
10
10
10
ns
tRCH
Read hold time after CAS high (see Note 14)
a
a
a
0
ns
100000
70
60
10 000
15
10 000
100 000
80
100 000
100
100000
ns
70
10 000
80
10 000
18
10 000
20
10 000
100
10 000
ns
25
10 000
ns
ns
ns
--
tRRH
Read hold time after RAS high (see Note 14)
5
5
5
5
ns
twCH
Write hold time after CAS low
(Early write operation only)
15
15
15
15
ns
twHR
W-high hold time
(CAS-before-RAS refresh only)
10
10
10
10
ns
Continued next page.
NOTES: g. All cycle times assume tT = 5 ns, referenced to VIH(min) and VIL(max)
10. To insure tpc min, tASC should be greater than or equal to 'Cpo
11. In a read-write cycle, tRWD and tRWL must be observed.
12. In a read-write cycle, tCWD and tCWL must be observed.
13. Referenced to the later of CAS or VIi in write operations.
14. Either tRRH or tRCH must be satisfied for a read cycle.
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
9-93
SMJ416100
16 777 216·81T
DYNAMIC RANDOM·ACCESS MEMORY
SGMS045-NOVEMBER 1992
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (concluded)
SMJ41610()..60
SMJ4161 00-70
SMJ4161 00-80
MIN
MIN
MIN
MAX
MAX
MAX
SMJ4161 00-1 0
MIN
MAX
UNIT
IAWD
Delay lime, column address 10 W low
(Read-wrile operalion only)
30
35
40
45
ns
ICHR
Delay lime, RAS low 10 CAS high
(CAS-before-RAS refresh only)
20
20
20
20
ns
ICRP
Delay lime, CAS high 10 RAS low
5
5
5
5
ns
ICSH
Delay lime, RAS low 10 CAS high
60
70
80
100
ns
ICSR
Delay lime, CAS low 10 RAS low
(CAS-before-RAS refresh only)
10
10
10
10
ns
ICWD
Delay lime, CAS low 10 W low
(Read-write operalion only)
15
18
20
25
ns
tRAD
Delay lime, RAS low 10 column-address
(see Nole 15)
15
tRAL
Delay lime, column-address to RAS high
30
ICAL
Delay lime, column-address 10 CAS high
30
IRCD
Delay lime, RAS low to CAS low
(see Nole 15)
20
30
45
15
35
15
40
15
55
ns
35
40
45
ns
35
40
45
ns
20
52
20
60
20
75
ns
tRPC
Delay time, RAS high to CAS low
a
0
0
0
ns
IRSH
Delay lime, CAS low to RAS high
15
18
20
25
ns
tRWD
Delay time, RAS low to W low
(Read-wrile operalion only)
60
70
80
100
ns
ICPRH
RAS hold lime from CAS precharge
35
40
45
50
ns
ICPW
Delay lime, W from CAS precharge
35
40
45
50
IREF
Refresh time inlerval
64
64
64
NOTE 15: The maximum value is specified only to insure access time.
PARAMETER MEASUREMENT INFORMATION
1.31 V
~
Output Under Test
VCC
RL
= 218 Q
~
CL=100pF
T
Output Under Test
CL = 100 pF
(b) Alternate Load Circuit
(a) Load Circuit
Figure 1. Load Circuits For Timing Parameters
TEXAS
~
INSTRUMENTS
9-94
=5V
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
ns
64
ms
SMJ416100
16777216·8IT
DYNAMIC RANDOM·ACCESS MEMORY
SGMS04!;-NOVEMBER 1992
PARAMETER MEASUREMENT INFORMATION
NOTE A: Output may go from a high-impedance state to an invalid data state prior to the specified access time.
Figure 2. Read Cycle Timing
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
9-95
SMJ416100
16 777 216·81T
DYNAMIC RANDOM·ACCESS MEMORY
SGMS045-NOVEMBER 1992
PARAMETER MEASUREMENT INFORMATION
Q---------------HI-Z---------------
VOH
VOL
Figure 3_ Early Write Cycle Timing
TEXAS ~
INSTRUMENTS
9-96
POST OFFICE BOX 1443· HOUSTON, TEXAS 77001
SMJ416100
16 777 216·81T
DYNAMIC RANDOM·ACCESS MEMORY
SGMS045-NOVEMBER 1992
PARAMETER MEASUREMENT INFORMATION
Figure 4. Write Cycle Timing
TEXAS ~
INsrRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
9-97
SMJ416100
16777 216·811
DYNAMIC RANDOM·ACCESS MEMORY
SGMS045-NOVEMBER 1992
PARAMETER MEASUREMENT INFORMATION
-+I
I
I
I
I
AO-A11~
NOTE A: Output may go from a high-impedance state to an invalid data state prior to the specified access time.
Figure 5. Read-Write Cycle Timing
TEXAS ."
INsrRUMENTS
9-98
POST OFFICE BOX 1443· HOUSTON. TEXAS 77001
SMJ416100
16 777 216·BIT
DYNAMIC RANDOM·ACCESS MEMORY
SGMS045-NOVEMBER 1992
PARAMETER MEASUREMENT INFORMATION
AG-A11
-~I:
w 23C22
24,25EN
G25
"l
A,220
'V 26
27
tThis symbol is in accordance wi1h ANSI/IEEE Std 91-1984 and lEe Publication 617-12.
TEXAS ~
INsrRUMENTS
9-108
POST OFFICE BOX 1443· HOUSTON. TEXAS 77001
r
A,Z26
SMJ416400
4194 304·WORD BY 4·BIT
DYNAMIC RANDOM·ACCESS MEMORY
SGMS042A-MARCH 1992-REVISED NOVEMBER 1992
functional block diagram
w
I
T
AO
Timing and Control
32
8
/
A1
A11
+ + + +I
•
•
•
Column
Address
Bufferst
2
-
256KArray
256KArray
•
•
•
32
Row
Address
Buffers
/
r-1~
t Column Address 10 and Column Address 11
256KArray
R
0
w
256KArray
11
/
256KArray
•
•
•
0
e
c
0
d
e
11
'--
\-I-
Sense Amplifiers
f--+-
1
•
•
•
Column Decode
32
Lt;
32
I/O
Buffers
40f32
Selection
1 __
2~_
256KArray
~
In
Reg.
~
Data
Out
Reg.
001-004
1
are not used.
TEXAS
~
INsrRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
9-109
SMJ416400
4 194 304·WORD BY 4·BIT
DYNAMIC RANDOM·ACCESS MEMORY
SGMS042A-MARCH 1992-REVISED NOVEMBER 1992
absolute maximum ratings over operating free-air temperature t
Voltage on any pin (see Note 1) ....................................................... - 1 V to 7 V
Voltage range on Vee . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 1 V to 7 V
Short circuit output current ................................................................ 50 mA
Power dissipation ....................................... :.................................. 1 W
Operating free-air temperature range .............................................. - 55°C to 125°C
Storage temperature range ................................................,' ...... - 65°C to 150°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. This is a stress rating only, and
functional operation of the device at these or any other conditions beyond those indicated in the "recommended operating conditions" section of
this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values in this data sheet are with respect to VSS.
recommended operating conditions
MIN
NOM
MAX
VCC
Supply voltage
4.5
5
5.5
UNIT
VIH
High-level input voltage
2.4
6.5
V
VIL
Low-level input voltage (see Note 2)
-1
0.8
V
TA
Operating free-air temperature
-55
125
'c
V
NOTE 2: Then algebraic convention, where the more negative (less positive) limit is designated as minimum, is used in this data sheet for logic
voltage levels only.
electrical characteristics over full ranges of recommended operating conditions (unless otherwise
.
noted)
PARAMETER
TEST CONDITIONS
VOH
High-level output
voltage
10H =-5 mA
VOL
Low-level output
voltage
IOL=4.2 mA
II
Input current
(Ieakage)*
10
ICCI
ICC2
'416400-60
MIN
'416400-70
MAX
MIN
'416400-80
MAX
2.4
2.4
MIN
'416400-10
MAX
MIN
MAX
V
2.4
2.4
UNIT
0.4
0.4
0.4
0.4
V
VI = 0 to 6.5 V,
All other pins = 0 V to VCC
±10
±10
±10
±10
",A
Output current
(Ieakage)*
Vo = 0 to VCC, CAS high
±10
±10
±10
±10
",A
Read or write cycle
current (see Note 3)
Minimum cycle,
VCC=5.5V
90
80
70
60
mA
After 1 memory cycle,
RAS and CAS high,
VIH = 2.4 V (TTL)
2
2
2
2
mA
After 1 memory cycle,
RAS and CAS high,
VIH = VCC - 0.05 V (CMOS)
1
1
1
1
mA
Standby current
ICC3
Average refresh
current (RAS-only or
CBR)*
RAS cycling, CAS high
(RAS-only), RAS low
after CAS low (CBR)
90
80
70
60
mA
ICC4
Average page current
(see Note 4)*
RAS low, CAS cycling
70
65
60
55
mA
ICC7
Standby current
output enable*
(see Note 5)
RAS = VIH, CAS = VIL, Data
out = enabled
5
5
5
5
mA
* Minimum cycle, VCC = 5.5 V.
NOTES: 3. Measured with a maximum of one address change while RAS = VIL.
4. Measured with a maximum of one adddress change while CAS = VIH.
5. Measured with indicated conditions following a normal read cycle.
TEXAS
~
INSTRUMENTS
9-110
POST OFFICE BOX 1443· HOUSTON. TEXAS 77001
SMJ416400
4194 304·WORD BY 4·BIT
DYNAMIC RANDOM·ACCESS MEMORY
SGMS042A-MARCH 1992-REVISED NOVEMBER 1992
capacitance over recommended ranges of supply voltage and operating free-air temperature,
f = 1 MHz (see Note 6)
PARAMETER
MIN
TYP
MAX
UNIT
Ci(AL
Input capacitance, address inputs
9
Ci{RCI
Input capacitance, strobe inputs
8
pF
Ci{OE)
Input capacitance, output enable
8
pF
Ci(W)
Input capacitance, write-enable input
Co
Output capacitance
pF
8
pF
14
pF
NOTE 6: Capacitance is sampled only at initial design and after any major change. Samples are tested at 0 V and 25'C with a 1 MHz signal applied
to the pin under test. All other pins are open.
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature
,41640()-60
PARAMETER
MIN
'416400-70
MAX
MIN
'416400-80
MAX
MIN
'416400-10
MAX
MIN
MAX
UNIT
tAA
Access time from column-address
30
35
40
45
ns
tCAC
Access time from CAS low
15
18
20
25
ns
tCPA
Access time from column precharge
35
40
45
50
ns
tRAC
Access time from RAS low
60
70
80
100
ns
toEA
Access time from OE low
15
18
20
25
ns
toFF
Output disable time after CAS high (see Note 8)
15
18
20
25
ns
Output disable time after OE high (see Note 8)
15
18
20
25
ns
tOEZ
NOTES:
7. Valid data is presented at the outputs after all access times are satisfied but may go from a high-impedance state to an invalid data
state prior to the specified access times as the outputs are driven when CAS goes low.
8. tOFF and tOEZ are specified when the outputs are no longer driven. The outputs are disabled by bringing either OE or CAS high.
TEXAS
~
IN5rRUMENTS
POST OFFICE BOX 1443' HOUSTON, TEXAS 77001
9-111
SMJ416400
4194 304-WORD BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SGMS042A-MARCH 1992-REVISED NOVEMBER 1992
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
'416400-60
MIN
MAX
'416400-70
MIN
MAX
'416400-80
MIN
MAX
'416400-10
MIN
MAX
UNIT
tRC
Random read or write cycle (see Note 9)
110
130
150
160
ns
tRWC
Read-write cycle time
155
161
205
245
ns
tpc
Page-mode read or write cycle time
(see Note 10)
40
45
50
55
ns
tPRWC
Page-mode read-write cycle time
65
96
105
120
ns
tRASP
Page-mode pulse duration, RAS low
(see Note 10)
60
100000
70
100000
60
100000
100
100000
ns
tRAS
Non-page-mode pulse duration, RAS low
(see Note 10)
60
10 000
70
10 000
80
10000
100
10 000
ns
tCAS
Pulse duration, CAS low (see Note 9)
15
10000
18
10000
20
10000
25
10000
ns
tcp
Pulse duration, CAS high
10
10
10
10
ns
tRP
Pulse duration, RAS high (precharge)
40
50
60
70
ns
twP
Write pulse duration
15
15
15
15
ns
tASC
Column-address setup time before CAS low
0
0
0
0
ns
tASR
Row-address setup time before RAS low
0
0
0
0
ns
tDS
Data setup time (see Note 11)
0
0
0
0
ns
tRCS
Read setup time before CAS low
0
0
0
0
ns
tCWL
W-Iow setup time before CAS high
15
16
20
25
ns
tRWL
W-Iow setup time before RAS high
15
18
20
25
ns
twcs
W-Iow setup time before CAS low
(Early write operation only)
0
0
0
0
ns
twSR
W-high setup time
(CAS-before-RAS refresh only)
10
10
10
10
ns
tCAH
Column-address hold time after CAS low
10
15
15
15
ns
tDH
Data hold time (see Note 11)
10
15
15
15
ns
10
10
10
10
ns
tRAH
Row-address hold time after RAS low
tRCH
Read hold time after CAS high (see Note 14)
0
0
0
0
ns
tRRH
Read hold time after RAS high (see Note 14)
5
5
5
5
ns
twCH
Write hold time after CAS low
(Early write operation only)
15
15
15
15
ns
twHR
W-high hold time
(CAS-before-RAS refresh only)
10
10
10
10
ns
Continued next page.
NOTES: 9. All cycle times assume tT = 5 ns, referenced to VIH(min) and VIL(max).
10. To assure tpc min, tASC should be greater than or equal to tcp.
11. In a read-write cycle, tRWD and tRWL must be observed.
12. In a read-write cycle, tCWD and tCWL must be observed.
13. Referenced to the later of CAS or IN in write operations.
14. Either tRRH or tRCH must be satisfied for a read cycle.
TEXAS ~
INsrRUMENTS
9-112
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
SMJ416400
4194 304-WORD BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SGMS042A-MARCH 1992-REVISED NOVEMBER 1992
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (concluded)
'416400-60
MIN
'416400-70
MAX
MIN
'416400-10
'416400-80
MAX
MIN
MAX
MIN
MAX
UNIT
tAWD
Delay time, column address to W low
(Read-write operation only)
55
63
70
80
ns
tCHR
Delay time, RAS low to CAS high
(CAS-before-RAS refresh only)
20
20
20
20
ns
leRP
Delay time, CAS high to RAS low
5
5
5
5
ns
tCSH
Delay time, RAS low to CAS high
60
70
80
100
ns
10
10
10
10
ns
Delay time, CAS low to W low
(Read-write operation only)
40
46
50
60
ns
tCSR
tCWD
~ time, CAS low to RAS low
(CAS-before-RAS refresh only)
tOEH
OE command hold time
15
18
20
25
ns
tOED
OE to data delay
15
18
20
25
ns
tROH
RAS hold time referenced to OE
10
10
10
10
ns
tRAD
Delay time, RAS low to column-address
(see Note 5)
15
tRAl
Delay time, column-address to RAS high
30
35
40
45
ns
tCAl
Delay time, column-address to CAS high
30
35
40
45
ns
20
30
15
35
15
40
15
20
55
tRCD
Delay time, RAS low to CAS low (see Note 5)
tRPC
Delay time, RAS high to CAS low
0
0
0
0
ns
tRSH
Delay time, CAS low to RAS high
15
18
20
25
ns
tRWD
Delay time, RAS low to W low
(Read-write operation only)
85
98
110
135
ns
lePRH
RAS hold time from CAS precharge
35
40
45
50
ns
tcpw
Delay time, W from CAS precharge
55
63
70
80
tREF
Refresh time interval
45
20
64
52
64
20
60
64
75
ns
ns
ns
64
ms
NOTE 15: The maximum value is specified only to assure access time.
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
9-113
SMJ416400
4 194 304-WORD BY 4-B11
DYNAMIC RANDOM-ACCESS MEMORY
SGMS042A-MARCH 1992-REVISED NOVEMBER 1992
PARAMETER MEASUREMENT INFORMATION
1.31 V
~
Output Under Test
VCC =5V
Rl = 828 Q
1T
RL=218Q
Output Under Test - - . - - - .
CL = 100 pF
CL=100pF
(a) Load Circuit
R2=295 Q
(b) Alternate Load Circuit
Figure 1. Load Circuits for Timing Parameters
,I"
RAS ----.i"}
IRC
r
!'\.
-.:
tRAS
.,
l~IRP~\.
11III-"--t-T------------"':1 I
I "--------
I I..
ICSH
.1
I
*-- IRCD ----+j
CAS
I
I I
I..
I
I.:
1
~,
I1I1I-+I-1
I ASR
I
I..
1
I
tRAH-.lI~
I
I
,
/."1\
.,
1
I 1
I~
r-
I
..
I..
I
:
I
I
I
TtCRP----+\
~ Xi I " } . .
'j1IIIl I
tcp
.I \
tCAL
IRAL
_,,~ R~: ~ co,,+: J@0!;~X~a!eJ$W<
~~~
~
~
I
.1
I
~ ~"'"
f~
t1III- tRRH
:" .~
NOTE A: Output may go from a high-impedance state to an invalid data state prior to the specified access time.
Figure 2. Read Cycle Timing
TEXAS
~
INSTRUMENTS
9-114
VIL
VIH
VIL
I I I I
1111
1111
.1 I I I
I .1 I
I
~'tASC
I'
I I
I I
I
tRSH~ !
"} : . - - tCAS
.1 tRAD
I
I
VIH
POST OFFICE BOX 1443· HOUSTON. TEXAS 77001
:::
SMJ416400
4 194 304·WORD BY 4·B11
DYNAMIC RANDOM·ACCESS MEMORY
SGMS042A-MARCH 1992-REVISED NOVEMBER 1992
PARAMETER MEASUREMENT INFORMATION
Figure 3. Early Write Cycle Timing
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
9-115
SMJ416400
4 194 304·WORD BY 4·BIT
DYNAMIC RANDOM·ACCESS MEMORY
SGMS042A-MARCH 1992-REVISED NOVEMBER 1992
PARAMETER MEASUREMENT INFORMATION
Figure 4. Write Cycle Timing
TEXAS ~
INSTRUMENTS
9-116
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
SMJ416400
4194 304·WORD BY 4·BIT
DYNAMIC RANDOM·ACCESS MEMORY
SGMS042A-MARCH 1992-REVISED NOVEMBER 1992
PARAMETER MEASUREMENT INFORMATION
DQ1DQ4
------~----~~~~----~X
(see Note A)
~1..- - - - t R A C ----~~I
I
I
I
I
_1 I
I
1
-IJ ~
II
I
I
14---JI
I
.tOEZ
-I
tOEA -11...- - - - . . .1
OE
§Z~f;~!~~~~
I
!
I
I
~tOEH
I
I
tOED
I
I
~:;~!~*£m
VIH
VIL
NOTE A: Output may go from a high-impedance state to an invalid data state prior to the specified access time.
Figure 5. Read-Write Cycle Timing
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
9-117
SMJ416400
4 194 304·WORD BY 4·BIT
DYNAMIC RANDOM·ACCESS MEMORY
SGMS042A-MARCH 1992-REVISED NOVEMBER 1992
PARAMETER MEASUREMENT INFORMATION
1"1
tRP
'IIII'"
tRASP
I I
I I
I
I
I I
II·..
I I
i""--
tRCD
I
I
I
I
tCSH I
N-- -tT
I
Ao-11~
I
I
tASR
I I
I I"
I
:
1:
L
I
I
I
:
I
I
I I
I 1
....
...1 - - - - tCAL
II
II
-----...1
VIH
VIL
I I
1 :
I
:
.1
I
I
I
I
I
I
I 14111...- - - - tAA ----,Ir---..
•I
I
I
I
tRAD
I
1
I
I
I
I
(see Note A)
tRRH
I..
tAA
I
~
VIL
I
~tOFF~
I
I
DQ1-DQ4---------------<~.
Valid _----<~
(see Note A) ~
~
I
I
I
I
I
I
I
~I
l1li-- tOEA ~
• I
II
I
1Q!I I
~ tASR L..~
I-----..j I
VIL
tASC
I
I
I
I
I"
~II I
.1
I
I
I
.r--~
I
tCAH ft7'.~~""", r - - - ' " " " " \ . ft7'.~~~~1'V'::~1'V'::~rj
I"~ tOEH
I
I" I ~I tAA
I I
I
:
I
I
I
I I"
~i tOH
I
tRAC ,---+I
I
I
I
I
I
.-+1
tos I
I
I
I
I
I
I
I
Valid Out
I
~tCAC I :
~I
I
(see Note A)
I
I
~
~ IIW.
~III~
N i.mQW
W~III
~!I
~VIH
~
i.
r---
i
VIL
i
i
I++-
i
VIHNOH
OQ1- _ _ _ _ _ _ _~I;,
IV~~d,
I
V~~ld ) * 1 1 - - - - - OQ4
V ~ ~"
.
VILNOL
I I Valid Outl
I..
I
1/·
,~ tOED
~1~tOEZ I
I
I
I
I
I
II
i'IIl"r---"'~o!-l tOEH I
j+- tOEA -+j I
I
I
I
~:
/
'T~-~'\XXXXXXXXXXXX~~VIH
OE
~
""'""'.................................. VIL
i
X'x'XXxX>l
"---.../
NOTES: A. Output may go from a high-impedance state to an invalid data state prior to the specified access time.
B. A read or write cycle can be intermixed with read-write cycles as long as the read and write timing specifications are not violated.
, Figure 8. Enhanced Page-Mode Read-Write Cycle Timing
TEXAS . "
INSTRUMENTS
9-120
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
SMJ416400
4194 304-WORD BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SGMS042A-MARCH 1992-REVISED NOVEMBER 1992
PARAMETER MEASUREMENT INFORMATION
Figure 9. RAS·Only Refresh Timing
TEXAS ~
INSfRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
9-121
SMJ416400
4 194 304-WORD BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SGMS042A-MARCH 1992-REVISED NOVEMBER 1992
~~~-------------------tRC------------------~
I+-- tRP ---+j
1
I 1
A
RAS
tRPC CAS
.!
1.
<11
.
1- - - - - - - - - - -
N~'
!+- tCSR
~
-+l
1
___________~Y
1
..- - - - - - -
~:
·1
1
11
tRAS ____________---+1
·1
tCHR
i'IIl
W~
•
VIL
.1
'{.-I..:~==~~I-t~1
__IT__~------------~~
I
twSR
VIH
1,.---..·1 twHR
VIH
~
.
V
IH
VIL
OE~:~~ag~~~~VIH
.
~
VIH
O Q 1 - 0 Q 4 - - - - - - - - - - - - - - - - HI-Z - - - - - - - - - - - - - - -
Figure 10. Automatic (CAS-Before-RAS) Refresh Cycle Timing
TEXAS
~
INSTRUMENTS
9-122
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
SMJ416400
4194 304·WORD BY 4·B11
DYNAMIC RANDOM·ACCESS MEMORY
SGMS042A-MARCH 1992-REVISED NOVEMBER 1992
PARAMETER MEASUREMENT INFORMATION
t4-- Refresh Cycle -+1
!+-- Refresh Cycle ~
~ Memory Cycle ~
,
, I"
, I
.1 I
I
I
I 1
I
I
l't
i!
I I
~I
tRAH+~
~
~
tRAS
V!
N:
I
.,
~
I
I I
i
rt+ t~sc
tASR
I
I
1
r"
N
~ ~tCAH
I II
I
I
tRP
i!
,
, I"
·1
I tRAS I
.,
Y
,
tRP
1.
I I
tCHR
i!
I I
: :
I I
I I
: :
I I
I I
: :
I I
I I
Vi
t'II
!-I
OE
I
I
I
;~~~*E=~V'L
+.J r-
~ tAA
~
I 1
11
1
I
I
I
~tWSR
I
I
h- 1
twHR
~~
~;:
twHR
I
I
I
VIH
~VIL
1
tOFF ~
1
I-~~
Q1-0Q4
1
~VIH
j4- I I * I 1
I
~ 1 twHR
I
I -.I :.-- tWSR
I
I I i + * - twSR
I
I
I
,.
I
I
I
1
1
Wtc~c:-~ ~V
I
VIH
VIL
:1l ~::
i!
II',
I I
~II
I"
1
1
I
1
IL-J
i
I I..
.1
I I
A0-11
I ,tR~H, ---.,
I 1.1 tRCS
I I I I
I I
I
I I
I
I I
II
I
r
fir----{
/
~
tCAS
,
1'1
~
--------~~-------------v-a-lid-O-at-aO-u-t----~~':~;----------~}-VOL
~
<>J - -I
tOEA
tOEZ
~
II
II
~ I.-VIH
nxs:;
tiXlY:>VIL
Figure 11. Hidden Refresh Cycle (Read)
TEXAS •
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
9-123
SMJ416400
4 194 304·WORD BY 4·BIT
DYNAMIC RANDOM·ACCESS MEMORY
SGMS042A-MARCH 1992-REVISED NOVEMBER 1992
TEXAS ~
INSTRUMENTS
9-124
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
SMJ417100
16 717 216·81T
DYNAMIC RANDOM·ACCESS MEMORY
SGMS043-NOVEMBER 1992
•
Organization ... 16777 216 x 1
•
Single 5·V Power Supply (10% Tolerance)
•
Performance Ranges:
SMJ417100·60
SMJ4171 00-70
SMJ4171 00-80
SMJ4171 00-10
FNC PACKAGEr
(TOP VIEW)
VCC
ACCESS ACCESS ACCESS READ
TIME
TIME
TIME OR WRITE
tRAC
tCAC
tAA
CYCLE
(MIN)
(MAX)
(MAX)
(MAX)
60 ns
15 ns
30 ns
110 ns
70 ns
18 ns
35 ns
130 ns
80 ns
20 ns
40 ns
150 ns
100 ns
25 ns
45 ns
180 ns
•
Enhanced Page Mode Operation for Faster
Memory Access
•
CAS·Before·RAS Refresh
•
Long Refresh Period ... 2048 Cycles
Refresh in 32 ms
•
3·State Unlatched Output
•
•
Low Power Dissipation
•
D
VSS
Q
NC
W
RAS
A11
NC
CAS
NC
A9
A10
AO
A1
A8
A7
A6
A5
A4
A2.
A3
VCC
VSS
HKB PACKAGEt
(TOP VIEW)
All Inputs, Outputs and Clocks are
TTL Compatible
Operating Free·Air Temperature Range
- 55°C to 125°C
description
The SMJ417100 series are high-speed
16777 216-bit
dynamic
random-access
memories, organized as 16 777 216-bit words by
one bit each. They employ EPIC'" (Enhanced
Process Implanted CMOS) technology for high
performance, reliability, and low power at a low
cost.
These devices feature maximum RAS access
times of 60 ns, 70 ns, 80 ns, and 100 ns.
VCC
1
D
2
NC
W
RAS
A11
NC
NC
A10
AO
A1
3
26
NC
4
25
CAS
5
6
24
23
NC
A9
7
22
NC
8
21
NC
9
20
10
19
A8
A7
AS
A5
28
27
VSS
Q
11
18
A2.
12
17
A3
13
16
A4
Vcc
14
15
VSS
t Packages are shown for pinout reference only.
All inputs, outputs, and clocks, are compatible with
Series 54 TTL. All addresses and data-in lines are
latched on-chip to simplify system design. Data
out is unlatched to allow greater system flexibility.
PIN NOMENCLATURE
AO-A11
CAS
D
NC
The SMJ417100 is offered in 450-mil 24/28-pin
surface mount SOlCC (FNC suffix) and flatpack
(HKB suffix) packages. The packages are
characterized for operation from - 55°C to 125°C.
Q
RAS
W
VCC
VSS
Address Inputs
Column-Address Strobe
Data In
No Internal Connection
Data Out
Row-Address strobe
Write Enable
5-V Supply
Ground
EPIC is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA Informllon 1. current I. of publlcallon
dltl. Producll conform 10 'peClflcltlonl perth. til"" ofTIUI
In'lrum,nla ItInd,rd .Imnty. Production proc...lng doe.
not nee....'''' Includ. t.lling of III Plramel""
TEXAS
~
Copyright © 1992. Texas Instruments Incorporated
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
9-125
SMJ417100
16777216·BIT
DYNAMIC RANDOM·ACCESS MEMORY
SGMS043-NOVEMBER 1992
operation
~nhanced
page mode
Page mode operation allows effectively faster memory access by keeping the same row address and strobing
random column addresses onto the chip. Thus, the time required to set up and strobe row addresses for the
same page is eliminated. The maximum number of columns that can be addressed is determined by tRAS, the
maximum RAS-Iow width.
The Column Address Buffers in this CMOS device are activated on the falling edge of RAS. They act as a
transparent or flow-through latch, while CAS is high. The falling edge of CAS latches the addresses into these
buffers and also serves as an output enable.
This feature allows the SMJ4171 00 to operate at a higher data bandwidth than conventional page-mode parts,
since retrieval begins as soon as the column address is valid, rather than when CAS transitions low. The
performance improvement is referred to as enhanced page mode. Valid column address may be presented
immediately after row address hold time has been satisfied, usually well in advance of the falling edge of CAS.
In this case, data is obtained after tCAC max (access time from CAS low), if tAA max (access time from column
address) and tRAC have been satisfied. In the event that the column address for the next cycle is valid at the
time CAS goes high, access time is determined by the later occurrence of tCPA or tCAC'
address (AQ-A11)
Twenty-four address bits are required to decode 1 of 16 777 216 storage cell locations. Twelve row-address bits
are 'set on inputs AO through A 11 and latched during a normal access. All addresses must be stable on or before
the falling edges of RAS and CAS. RAS is similar to a chip enable in that it activates the sense amplifiers as
well as the row decoder. CAS is used as a chip select, activating the output buffer, as well as latching the address
bits into the column buffer.
write enable
(iii)
The read or write mode is selected through the write-enable W input. A logic high on the W input selects the
read mode and a logic low selects the write mode. The write-enable terminal can be driven from standard TIL
circuits without a pull up resistor. The data input is disabled when the read mode is selected. When W goes low
prior to CAS (early write), data out will remain in the high-impedance state for the entire cycle, permitting
common I/O operation.
data-in (D)
Data is written during a write or read-modify-write cycle. Depending on the mode of operation, the falling of CAS
. or W strobes data into the on-Chip data latch. In an early-write cycle, W is brought low prior to CAS and data
is strobed in by CAS with setup and hold times referenced to this signal. In a delayed-write or read-modify-write
cycle, CAS will already be low, thus data will be strobed in by W with setup and hold times referenced to this
signal.
data-out (Q)
The three-state output buffer provides direct TIL compatibility (no pull up resistor required) with a fan-out of two
Series 54 TIL loads. The output is in the high-impedance (floating) state until CAS is brought low. In a read cycle
the output becomes valid at the latest occurrence of tRAC, tAA, tCAC, or tCPA and remains valid while CAS is
low. CAS going high returns it to a high-impedance state. In a delayed-write or read-modify-write cycle, the
output does not change, but retains the state just read.
TEXAS ~
INsrRUMENTS
9-126
POST OFFICE BOX 1443· HOUSTON. TEXAS 77001
SMJ417100
16777216·8IT
DYNAMIC RANDOM·ACCESS MEMORY
SGMS043-NOVEMBER 1992
refresh
A refresh operation must be performed at least once every thirty-two milliseconds to retain data. This can be
achieved by strobing each of the 2048 rows (AO-A10). A normal read or write cycle will refresh all bits in each
row that is selected. A RAS-only operation can be used by holding CAS at a high (inactive) level, thus conserving
power since the output buffer remains in the high-impedance state. Externally generated addresses must be
used for a RAS-only refresh. Hidden refresh may be performed by holding CAS at VIL after a read operation
and cycling RAS after the specified precharge period, similar to a RAS-only refresh cycle except with CAS held
low. Valid data is maintained at the output throughout the hidden refresh cycle. An internal refresh address
provides the refresh address during hidden refresh.
CAS-before-RAS refresh
CAS-before-RAS refresh is utilized by bringing CAS low earlier than RAS (see parameter teSR) and holding
it low after RAS falls (see parameter teHR)' For successive CAS-before-RAS refresh cycles, CAS can
remain low while cycling RAS. For this mode of refresh, the external addresses are ignored and the refresh
address is generated internally.
power up
To achieve proper device operation, an initial pause of 200 ~s followed by a minimum of eight initialization cycles
is required after full Vee level is achieved. These eight initialization cycles need to include at least one refresh
(RAS-only or CAS-before-RAS) cycle.
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
9-127
SMJ417100
16777216·8IT
DYNAMIC RANDOM·ACCESS MEMORY
SGMS043-NOVEMBER 1992
logic symbol t
RAM 16 384K xl
AO
Al
A2
A3
A4
A5
A6
A7
A8
A9
Al0
All
10
11
12
13
16
17
18
19
20
23
9
6
30012/2100
0
A 16 777 215
r-..
5
~
f'-,
25
w
o
4
2
~
~
31023/21011
C30 [ROW]
G33 [REFRESH ROW]
34 [PWR OWN]
C31 [COL]
G34
&
P, 33C32
34 EN
33310
A, 320
27
AV
Q
t This symbol is in accordance with ANSI/IEEE Std 91-1984 and lEG Publication 617-12.
functional block diagram
~
I
'f
AO
Al
1
32,
8
/
•
•
•
All
Column
Address
Buffers
•
•
L--
-
Column Decode
4
256KArray
256KArray
R
256KArray
32<
Row
Address
Buffers
W
Sense Amplifiers
f-,L-
L
•
~
~
Timing and Control
0
••
256KArray
•
••
w
•
0
e
c
11
/
1--
d
e
256KArray
11
256KArray
f
/
TEXAS
~
INsrRUMENTS
9-128
32
I/O
Buffera
1 of 32
Selection
41--
0
f--
-±
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
11--
~
~
In
Reg.
Out
Reg.
o
Q
SMJ417100
16777216-811
DYNAMIC RANDOM-ACCESS MEMORY
SGMS043-NOVEMBER 1992
absolute maximum ratings over operating free-air temperature range {unless otherwise noted)t
Voltage on any pin (see Note 1) ...................................................... - 1 V to 7 V
Voltage on Vee ..... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 1 V to 7 V
Short circuit output current ................................................................ 50 mA
Power dissipation .......................................................................... 1 W
Operating free-air temperature range .............................................. - 55°C to 125°C
Storage temperature range ....................................................... - 65°C to 150°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. This is a stress rating only, and
functional operation olthe device at these or any other conditions beyond those indicated in the "recommended operating conditions" section of
this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE I: All voltage values in this data sheet are with respect to vss.
recommended operating conditions
MIN
NOM
MAX
Vcc
Supply voltage
4.5
5
5.5
UNIT
V
VIH
High-level input voltage
2.4
6.5
V
VIL
Low-level input voltage (see Note 2)
-I
0.8
V
TA
Operating free-air temperature
0
70
·C
NOTE 2: The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used in this data sheet for logic
voltage levels only.
electrical characteristics over full ranges of recommended operating conditions (unless otherwise
noted)
PARAMETER
TEST
CONDITIONS
VOH
High-level output
voltage
10H =-5mA
VOL
Low-level output
voltage
IOL=4.2mA
II
Input current
(leakage):!:
VI = 0 to 6.5 V,
All other pins =
o Vto VCC
10
Output current
(leakage):!:
~OtoVCC,
ICC I
Read or write cycle·
current (see Note 3)
Minimum cycle,
VCC =5.5V
ICC2
Standby current
SMJ41 71 00-60
MIN
MAX
2.4
SMJ4171 00-70
MIN
MAX
2.4
SMJ417100-80
MIN
MAX
2.4
SMJ417100-10
MIN
MAX
2.4
UNIT
V
0.4
0.4
0.4
0.4
V
±IO
±IO
±IO
±IO
!lA
±IO
±IO
±IO
±IO
!lA
110
100
90
80
mA
After I memory cycle,
RAS and CAS high,
VIH = 2.4 V (TTL)
2
2
2
2
mA
After I memory cycle,
RAS and CAS high,
VIH = VCC-0.2V
(CMOS)
I
I
I
I
mA
CAS high
ICC3
Average refresh
current (RAS-only or
CBR):!:
RAS cycling, CAS high
(RAS-only), RAS low
after CAS low (CBR)
110
100
90
80
mA
ICC4
Average page current
(see Note 4):!:
RAS low, CAS cycling
70
65
60
55
mA
ICC7
Standby current
output enable:!:
(see Note 5)
RAS = VIH, CAS = VIL,
Data out = enabled
5
5
5
5
mA
:j: Minimum cycle, VCC = 5.5 V.
NOTES: 3. Measured with a maximum of one address change while RAS = VIL.
4. Measured with a maximum of one address change while CAS = VIH.
5. Measured with indicated conditions following a normal read cycle.
TEXAS
~
INSIRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
9-129
SMJ417100
16777216.. 8IT
DYNAMIC RANDOM-ACCESS MEMORY
SGMS043-NOVEMBER 1992
capacitance over recommended ranges of supply voltage and operating· free-air temperature,
f = 1 MHz (see Note 6)
PARAMETER
MIN
TYP
MAX
UNIT
Ci(A)
Input capacHance. address inputs
9
pF
CI(D)
Input capacitance. data input
8
pF
Ci(RC)
Input capacitance. strobe inputs
8
pF
Ci(W)
Input capacitance. write-enable input
8
pF
Co
Output capacitance
14
pF
NOTE 6: Capacitance is sampled only at initial design and after any major change. Samples are tested at 0 V and 25° C with a 1 MHz signal
applied to the pin under test. All other pins are open.
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature
PARAMETER
SMJ4171 00-60
MIN
MAX
SMJ4171 00-70
MIN
MAX
SMJ417100.aO
MIN
MAX
SMJ4171 00-1 0
MIN
MAX
UNIT
tAA
Access time from column-address
30
35
40
45
ns
tCAC
Access time from CAS low
15
18
20
25
ns
tCPA
Access time from column precharge
35
40
45
50
ns
tRAC
Access time from RAS low
60
70
80
100
ns
!oFF
Output disable time after CAS high
(see Note 8)
25
ns
NOTES:
0
15
0
0
20
0
7. Valid data is presented at the output after all access times are satisfied but may go from a high-impedance state to an invalid data
state prior to the specified access times as the output is driven when CAS goes low.
8. tOFF is specified when the output is no longer dirven. The output is disabled by bringing CAS high.
TEXAS . "
INSTRUMENTS
9-130
18
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
SMJ417100
16 777 216-81T
DYNAMIC RANDOM-ACCESS MEMORY
SGMS043-NOVEMBER 1992
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
SMJ417100-60
MIN
MAX
SMJ417100-70
MIN
MAX
SMJ417100-S0
MIN
MAX
SMJ417100-10
MIN
MAX
UNIT
tRC
Random read or write cycle (see Note 9)
110
130
150
180
ns
tRWC
Read-write cycle time
130
153
175
210
ns
tpc
Page-mode read or write cycle time
(see Note 10)
40
45
50
55
ns
tPRWC
Page-mode read-write cycle time
60
68
75
85
ns
tRASP
Page-mode pulse duration, RAS low
(see Note 11)
60
100000
70
100000
80
100000
100
100000
ns
tRAS
Non-page-mode pulse duration, RAS low
(see Note 11)
60
10000
70
10000
80
10000
100
10000
ns
tCAS
Pulse duration, CAS low (see Note 12)
15
10000
18
10000
20
10000
25
10000
ns
tcp
Pulse duration, CAS high
10
10
10
10
ns
tRP
Pulse duration, RAS high (precharge)
40
50
60
70
ns
twp
Write pulse duration
15
15
15
15
ns
tASC
Column-address setup time before CAS low
0
0
0
0
ns
tASR
Row-address setup time before RAS low
0
0
0
0
ns
tDS
Data setup time (see Note 13)
0
0
0
0
ns
tRCS
Read setup time before CAS low
0
0
0
0
ns
tCWL
W-Iow setup time before CAS high
15
18
20
25
ns
tRWL
W-Iow setup time before RAS high
15
18
20
25
ns
twcs
W-Iow setup time before CAS low
(Early write operation only)
0
0
0
0
ns
twSR
W-high setup time (CAS-before-RAS
refresh only)
10
10
10
10
ns
tCAH
Column-address hold time after CAS low
10
15
15
15
ns
tDH
Data hold time (see Note 12)
10
15
15
15
ns
tRAH
Row-address hold time after RAS low
10
10
10
10
ns
tRCH
Read hold time after CAS high (see Note 14)
0
0
0
0
ns
tRRH
Read hold time after RAS high (see Note 14)
5
5
5
5
ns
twCH
Write hold time after CAS low
(Early wr~e operation only)
15
15
15
15
ns
twHR
W-high hold time (CAS-before-RAS
refresh only)
10
10
10
10
ns
Continued next page.
NOTES: 9. All cycle times assume tT = 5 ns, referenced to VIH(min) and VIL(max).
10. To guarantee tpc min, tASC should be greater than or equal to tcp.
11. In a read-write cycle, tRWD and tRWL must be observed.
12. In a read-write cycle, tCWD and tCWL must be observed.
13. Referenced to the later of CAS or Win write operations.
14. Either tRRH or tRCH must be satisfied for a read cycle.
TEXAS ~
INSIRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
9-131
SMJ417100
16777216·8IT
DYNAMIC RANDOM·ACCESS MEMORY
SGMS043-NOVEMBER 1992
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (concluded)
SMJ4171 00-60
MIN
MAX
SMJ4171 00-70
MIN
MAX
SMJ417100-80
MIN
SMJ417100-10
MAX
MIN
MAX
UNIT
tAWD
Delay time, column address to W low
(Read-write operation only)
30
35
40
45
ns
tcHR
Delay time, RAS low to CAS high
(CAS-belore-RAS relresh only)
20
20
20
20
ns
tCRP
Delay time, CAS high to RAS low
5
5
5
5
ns
tCSH
Delay time, RAS low to CAS high
60
70
80
100
ns
tCSR
Delay time, CAS low to RAS low
(CAS-belore-RAS relresh only)
10
10
10
10
ns
tCWD
Delay time, CAS low to W low
(Read-write operation only)
15
18
20
25
ns
tRAD
Delay time, RAS low to column-address
(see Note 15)
15
tRAl
Delay time, column-address to RAS high
30
35
40
45
ns
tCAl
Delay time, column-address to CAS high
30
35
40
45
ns
tRCD
Delay time, RAS low to CAS low
(see Note 15)
20
tRPC
Delay time, RAS high to CAS low
0
0
0
0
ns
tRSH
Delay time, CAS low to RAS high
15
18
20
25
ns
tRWD
Delay time, RAS low to W low
(Read-write operation only)
60
70
80
100
ns
ns
30
45
35
15
20
52
15
20
40
15
60
20
tCPRH
RAS hold time lrom CAS precharge
35
40
45
50
tcpw
Delay time, W from CAS precharge
35
40
45
50
tREF
Refresh time interval
32
32
32
NOTE 15: The maximum value is specified only to assure access time.
PARAMETER MEASUREMENT INFORMATION
1.31 V
~
Output Under Test
VCC = 5V
--±.T
RL = 218
Q
Output Under Test ---..--~
CL = 100 pF
CL= 100pF
(a) Load Circuit
(b) Alternate Load Circuit
Figure 1. Load Circuits for Timing Parameters
TEXAS
~
INSTRUMENTS
9-132
POST OFFICE BOX 1443' HOUSTON. TEXAS 77001
55
75
ns
ns
ns
32
ms
SMJ417100
16777216·BIT
DYNAMIC RANDOM·ACCESS MEMORY
SGMS043-NOVEMBER 1992
PARAMETER MEASUREMENT INFORMATION
NOTE A: Output may go from a high-impedance state to an invalid data state prior to the specified access time.
Figure 2. Read Cycle Timing
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
9-133
SMJ417100
16777 216·81T
DYNAMIC RANDOM·ACCESS MEMORY
SGMS043-NOVEMBER 1992
PARAMETER MEASUREMENT INFORMATION
Q---------------HI-Z---------------
VOH
VOL
Figure 3. Early Write Cycle Timing
TEXAS
-.\J
INSTRUMENTS
9-134
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
SMJ417100
16 777 216·BIT
DYNAMIC RANDOM·ACCESS MEMORY
SGMS043-NOVEMBER 1992 ,
PARAMETER MEASUREMENT INFORMATION
Figure 4. Write Cycle Timing
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
9-135
SMJ417100
16777 216·81T
DYNAMIC RANDOM·ACCESS MEMORY
. SGMS043--NOVEMBER 1992
PARAMETER MEASUREMENT INFORMATION
--+I
I
I
I
I
AO-A11~
NOTE A: Output may go from a high-impedance state to an invalid data state prior to the specified access time.
Figure 5. Read-Write Cycle Timing
TEXAS ~
INSTRUMENTS
9-136
POST OFFICE BOX 1443· HOUSTON. TEXAS 77001
SMJ417100
16777216·BIT
DYNAMIC RANDOM·ACCESS MEMORY
SGMS043-NOVEMBER 1992
PARAMETER MEASUREMENT INFORMATION
Column
AD-All
~---------r..J ,,~~~~~~ vlL
I
-~::
w~
I
lot-- tRAD --.J
1
I
I
1
1
I..
tAA ---'I..
--I~I
(see Note B)
I I..
I
loti-- tRCS --M
1
WN
W
I+-- tCAC ----+I
tRAC
(see Note A)
~I
~
I
Valid
Out
I
I
tCPA ---I-~~I
(see Note B)
~I
Q _ _ _ _ _ _ _ _ _ _ _ _~
m
~
::
1
14
..- - - -
Iotl..- - - tAA
tRRH-.!
tRCH --.I
I
1
1
VIH
VIL
I
1
~ tOFF ----.j
I
I
~
~
Valid Out
?'--
T
V
OH
VOL
NOTES: A: Output may go from a high-impedance state to an invalid data state prior to the specified access time.
B: Access time is tePA or tAA dependent.
Figure 6. Enhanced Page-Mode Read Cycle Timing
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
9-137
SMJ417100
16 777 216·81T
DYNAMIC RANDOM·ACCESS MEMORY
SGMS043-NOVEMBER 1992
PARAMETER MEASUREMENT INFORMATION
I~
tRP
I~
tRASP
1 1
1
14
N
:~
I~
tCSH
1 !.-- tRCO ---.1
1
!
1
I
1
:
1
I
r--
I
141~---1.~I-1
.1
N,
}
!.- tRAH
H
/ir:--+-
N :i
1
I ! . - tCAH
I 1
1 I
+I'
VIL
~ tRSH
1\1
--4I
I
1
1
I
I
.I'+- 'ICRP ---.I
tpc
~ "------"Y:tASC I
I 1
1 ~ tcp --.I
tASR
.1
~~
tCPRH
.1
1 I'"
tCAS -+1 1
1
1
1
1
I - - - - VIH
VIL
1
1
·1
AO-A11
I~
1
I~
1
~:~~:~I~~.I-twp
II:
W
~~~~g~\XXW0
i:
~
I~
1
1
1
I~
1
o
.:
tcwLI
:
:
~tRWL~
1
_~~@~~
~""""~~fr~~~""""'2£22S~
1
VIL
.1,1 1
tos
I 1
.
tos
,
1
~tOH--.I
1
~I~:--,-I-- tOH ---.~I
~
(see Note A)
(see Note A)
1
1
~----------~-v-a-lid-o-a~ta--ln-------------~~_V~~~lId__J~o~~~~{~
-
VIL
VOH
Q - - - - - - - - - - - - - - - - - - - - - - - - - - - - - HI-Z - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
NOTES: A: Referenced to CAS or \N, whichever occurs last.
B: A read cycle or a read-write cycle can be intermixed with write cycle as long as read and read-write timing specifications are not
violated.
Figure 7. Enhanced Page-Mode Write Cycle Timing
TEXAS
~
INSTRUMENTS
9-138
POST OFFICE BOX 1443' HOUSTON, TEXAS 77001
SMJ417100
16 777 216·BIT
DYNAMIC RANDOM·ACCESS MEMORY
SGMS043-NOVEMBER 1992
PARAMETER MEASUREMENT INFORMATION
RAS
-------x! ,
I
I
I..
tRASP
r--
1
i"
tRAO!
~I
1..
I I
~
I
-+I ~ IASR
I I
: I I
I+- IASC +) I
I --41 ~ IR~H
I I
I
I~ICAH-.I
I III
AO-A11~
I
I
I
I"
I
~
~ ICWO
~
I
I
i
I
I
I
I
I
III
~~~~~~~'~}i*~)w~:::
I I I
~tCWL~ I I
I l'OIII-- IRWL ---t.I
ICPW
I I
~I I
I..
!;x)yy;
J
N
':1~
m:i{I
: f1*
_gfr~_ Yo,,' >«~**~X
lOS
I
I
I
I
I
I
:
I"
I"
I I
I..
)0lIl- ICAC
tAA
IRAC
~I
IOH
~
I
~I
~
Q -----------.....
~
:
:
1
I
I
+,
I
ICLZ~
1
I"
I Valid
~
~m~~~o:rVvIIHL
:
1
1
I
VIL
tCRP
lir-;+:- - - - : : :
Column
I
I
I
I
~I
::
I
I
I
I
I
~tRCS--.I I 1
j+- IAWO -r-+I !...- tw --.I
I
I
I IRWO
I ~I I
P
I
w~ i
I
)@(:
C~lu:mn
I
I.. I
: i
~
N,
I
I
VIH
1"--
~I tcp
1:'--- IRSH ~
I
i
~
1
--'Jt,! /"\.
~I
tpRWC
I
tCSH i
~i I..
I :+-- tRCO ~
I 1
I I
I ~tCAS~
CAS
tCPRH
1
I"
1
tRP~
~I 1
ICpA
,..
(see Note A)
Out'
>0$lm~~ :::
~I
I+I
II
-.I
OFF
~I1
~
c
.
I
I
II
r
' - VOH
Valid Out
VOL
NOTES: A. Output may go from a high-impedance state to an invalid data state prior to the specified access time.
B. A read or write cycle can be intermixed with read·write cycles as long as the read and write timing specifications are not violated.
Figure 8. Enhanced Page-Mode Read-Write Cycle Timing
TEXAS ~
INsrRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
9-139
SMJ417100
16 777 216·BIT
DYNAMIC RANDOM·ACCESS MEMORY
SGMS043-NOVEMBER 1992
PARAMETER MEASUREMENT INFORMATION
Q---------------------------------------------------------------
VOH
VOL
Figure 9. RAS-Only Refresh Timing
TEXAS ~
INsrRUMENTS
9·140
POST OFFICE BOX 1443· HOUSTON, TEXAS 77001
SMJ417100
16777 216·BIT
DYNAMIC RANDOM·ACCESS MEMORY
SGMS043-NOVEMBER 1992
PARAMETER MEASUREMENT INFORMATION
~1~r--------------------tRc------------------~
·1
.1 1
14-- tRP -+IIi'III~'----------- tRAS - - - - - - - - - - - + 1
1
I I
11
RAS
I
1
tRPC CAS
N
If
.1
~I
Y
~ICSR~
~
VIL
I ,.I~---- tCHR ----~.I
i I ~I tr
\l
twSR
VIH
_ _ _ _ _ _ _ _ _ _ _ _ _..J:
11'11
W~
•
t..---.r·1 twHR
Y
VIH
~
V
IH
VIL
VOH
Q---------------HI·Z---------------
VOL
Figure 10. Automatic (CAS·Before-RAS) Refresh Cycle Timing
TEXAS ~
INSfRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
9·141
SMJ417100
16777216·81T
DYNAMIC RANDOM·ACCESS MEMORY
SGMS043-NOVEMBER 1992
PARAMETER MEASUREMENT INFORMATION
j4-- Memory Cycle
I
RAS
~I I
N,~
I
CAS
~I
1"11:1
I I"
JI!
I
I
tRP
1 I"
AS
I I
I
I :
~I
I"
~I I tRAS
Y
N
I
I
I
1
r
Refresh Cycle ~
~
1
Refresh Cycle ----+t
I
tRP
1
I
"\
/~
r
•____ ; ~
I I
I
tCAS I :
:
f--+I
tRAH~~
---.j
i
I ::
I+jtASR II
I :
II
I
r
~I
tcHR 1 I"
(::
)
I I
I :
II
VIH
VIL
I
I I
I I
I
: :
II
:
I
:IH
IL
I
AD-A"~~~IE.~:::
ItR~~ ~ i +.J
I
-+l
1
I" I
I~I ItRCS
I I
I I
I
I
I I
I
I
I
ww::
I
I
I
I I
I
'"
I
j4- twHR
I
1
I
I
V
I
I
I
I
joII- tW~R
I
I
--+i
I
~
I
I
I
j+- tWHR
I+- twHR
I
I
~ tw,SR
-+I
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-+I
~W
'<:tt£i:J.§1
I
I
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I
I
1
1
I
I
I
tOFF -+-j
~tCAC
~
VIH
VIL
::
I
I
~I tAA
Valid Oata
Figure 11. Hidden Refresh Cycle (Read)
TEXAS ~
INSTRUMENTS
9-142
I
~
~~~
I
I
I
I
}~K~~ar~.~
o
I" I
~
J4-.
I
POST OFFICE BOX 1443' HOUSTON, TEXAS 77001
~~
1'I
}- :::
SMJ417400
4194 304-WORD BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SGMS044-NOVEMBER 1992
•
•
•
FNC PACKAGEt
Organization ... 4 194 304 x 4
(TOP VIEW)
Single 5-V Power Supply (10% Tolerance)
VCC
Performance Ranges:
SMJ4i7400-60
SMJ417400-70
SMJ417400-80
SMJ417400-10
ACCESS ACCESS ACCESS READ
TIME
TIME
TIME OR WRITE
tRAC
tCAC
tAA
CYCLE
(MAX)
(MAX)
(MAX)
(MIN)
60ns
15ns
30ns
110ns
70 ns
18 ns
35 ns
130 ns
80 ns
20 ns
40 ns
150 ns
lOOns
25ns
45ns
180ns
•
Enhanced Page Mode Operation for Faster
Memory Access
•
•
CAS-Before-RAS Refresh
•
•
•
•
Long Refresh Period ... 2048 Cycles
Refresh in 32 ms
D
VSS
Q
NC
IN
RAS
Aii
NC
CAS
NC
A9
AiD
AD
Ai
A2
A3
AS
A7
A6
AS
VCC
VSS
3-State Unlatched Output
A4
HKB PACKAGEt
(TOP VIEW)
Low Power Dissipation
All Inputs, Outputs, and Clocks are
TTL Compatible
Operating Free-Air Temperature Range
-55°C to 125°C
description
The SMJ417400 series are high-speed
16 777 216-bit
dynamic
random-access
memories, organized as 4 194 304-bit words by
four bits each. They employ EPIC'· (Enhanced
Performance Implanted CMOS) technology for
high performance, reliability, and low power at a
low cost.
Vcc
1
28
D
2
27
NC
IN
RAS
Aii
NC
NC
AiD
3
26
4
25
5
24
6
23
22
7
8
9
10
AD
VSS
Q
19
18
NC
CAS
NC
A9
NC
NC
AS
A7
A6
17
AS
21
20
Ai
A2
A3
11
12
13
16
A4
Vcc
14
15
VSS
t Packages shown are for pinout reference only.
These devices feature maximum RAS access
times of 60 ns, 70 ns, 80 ns, and 100 ns.
PIN NOMENCLATURE
All inputs, outputs, and clocks are compatible with
Series 54 TTL. All addresses and data-in lines are
latched on-Chip to simplify system design. Data
out is unlatched to allow greater system flexibility.
AO-A11
CAS
DQ1-DQ4
NC
The SMJ417400 is offered in a 450-miI24/28-pin
surface mount SOlCC (FNC suffix) and flatpack
(HKB suffix) packages. The packages are
characterized for operation from -55°C to 125°C.
RAS
W
VCC
VSS
Address Inputs
Column-Address Strobe
Data In/Data Out
No Internal Conn.ection
Output Enable
Row-Address Strobe
Write Enable
5-V Supply
Ground
EPIC is a trademark of Texas Instruments Incorporated.
TEXAS
~
Copyright © 1992. Texas Instruments Incorporated
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
9-143
SMJ417400
4 194 304·WORD BY 4·BIT
DYNAMIC RANDOM·ACCESS MEMORY
SGMS044-NOVEMBER 1992
operation
enhanced page mode
Page mode operation allows effectively faster memory access by keeping the same row address and strobing
random column addresses onto the chip. Thus, the time required to set up and strobe row addresses for the
same page is eliminated. The maximum number of columns that can be addressed is determined by tRAS, the
maximum RAS low width.
The Column Address Buffers in this CMOS device are activated on the falling edge of RAS. They act as a
transparent or flow-through latch, while CAS is high. The falling edge of CAS latches the addresses into these
buffers and also serves as an output enable.
This feature allows the SMJ417400 to operate at a higher data bandwidth than conventional page-mode parts,
because retrieval begins as soon as the column address is valid, rather than when CAS transitions low. The
performance improvement is referred to as enhanced page mode. Valid column address may be presented
immediately after row address hold time has been satisfied, usually well in advance of the falling edge of CAS.
In this case, data is obtained aftertCAC max (access time from CAS low), iftAA max (access time from column
address) and tOEA (access time from output enable) have been satisfied. In the event that the column address
for the next cycle is valid at the time CAS goes high, access time is determined by the later occurrence of tCPA
or tCAC'
address (AO-A10)
Twenty-two address bits are required to decode 1 of 4 194 304 storage cell locations. Eleven row-address bits
are set on inputs AO through A 10 and latched onto the chip by the Row Address Strobe RAS. Eleven
column-address bits are set on AO through A 10. All addresses must be stable on or before the falling edges of
RAS and CAS. RAS is similar to a chip enable in that it activates the sense amplifiers as well as the row decoder.
CAS is used as a chip select, activating the output buffer, as well as latching the address bits into the column
buffer.
write enable (W)
The read or write mode is selected through the write .. enable 0N) input. A logic high on the W input selects the
read mode and a logic low selects the write mode. The write-enable terminal can be driven from standard TIL
circuits without a pullup resistor. The data input is disabled when the read mode is selected. When W goes low
prior to CAS (early write), data out will remain in the high-impedance state for the entire cycle, permitting a write
operation independent ofthe state of OE. This permits early write operation to be completed with OE grounded.
data-In/data-out (OQ1-0Q4)
Data is written during a write or read-modify-write cycle. Depending on the mode of operation, the falling of CAS
or W strobes data into the on-chip data latch. In the early-write cycle, W is brought low prior to CAS and data
is strobed in by CAS with setup and hold times referenced to this signal. In a delayed write or read-modify-write
cycle, CAS will already be low, thus data will be strobed in by Wwith setup and hold times referenced to this
Signal.
The three-state output buffer provides direct TIL compatibility (no pullup resistor required) with a fan-out of two
Series 74 TIL loads. The output is in the high-impedance (floating) state until CAS is brought low. In a read cycle
the output becomes valid atthe latest occurrence oftRAC, tAA, tCAC, tCPA, or tOEA and remains valid while CAS
is low. CAS going high returns it to a high-impedance state. In a delayed-write or read-modify-write cycle, the
output does not change, but retains the state just read.
TEXAS
~
INsrRUMENTS
9-144
POST OFFICE BOX 1443' HOUSTON. TEXAS 77001
SMJ417400
4 194 304-WORD BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SGMS044-NOVEMBER1992
output enable (OE)
OE controls the impedance of the output buffers. When OE is high, the buffers will remain in the high-impedance
state. Bringing OE low during a normal cycle will activate the output buffers, putting them in the low-impedance
state. It is necessary for both RAS and CAS to be brought low for the output buffers to go into the low-impedance
state. Once in the low-impedance state, they will remain in the low-impedance state until either OE or CAS is
brought high.
refresh
A refresh operation must be performed at least once every 32 milliseconds to retain data. This can be achieved
by strobing each of the 2048 rows (AQ-A 10). A normal read or write cycle will refresh all bits in each row that
is selected. A RAS-only operation can be used by holding CAS at a high (inactive) level, thus conserving power
since the output buffer remains in the high-impedance state. Externally generated addresses must be used for
a RAS-only refresh. Hidden refresh may be performed by holding CAS at VIL after a read operation and cycling
RAS after the specified precharge period, similar to a RAS-only refresh cycle except with CAS held low. Valid
data is maintained at the output throughout the hidden refresh cycle. An internal refresh address provides the
refresh address during hidden refresh.
CAS-before·RAS refresh
CAS-before-RAS refresh is utilized by bringing CAS low earlier than RAS (see parameter teSR) and holding
it low after RAS falls (see parameter teHR)' For successive CAS-before-RAS refresh cycles, CAS can remain
low while cycling RAS. For this mode of refresh, the external addresses are ignored and the refresh address
is generated internally.
power up
To achieve proper device operation, an initial pause of 200 ~s followed by a minimum of eight initialization cycles
is required after full Vee level is achieved. These eight initialization cycles need to include at least one refresh
(RAS-only or CAS-before-RAS) cycle.
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
9-145
SMJ417400
4194 304·WORD BY 4·BIT
DYNAMIC RANDOM·ACCESS MEMORY
SGMS044-NOVEMBER 1992
logic symbol t
RAM4096Kx4
AO
Al
A2
A3
A4
A5
A6
A7
A8
A9
Al0
10
11
12
20011/2100 ...
13
16
17
18
19
20
0
A 4194303
23
9
20022/21010
L
5
~
J'--,
25
W
OE
OQl
OQ2
OQ3
OQ4
4
24
~
C21 [COLUMN)
G24
~ 23,210
i'-
2
3
C20[ROW)
G23/[REFRESH ROW]
24[PWROWN)
4-
&
> 23C22
24,25EN
G25
r
'"1
A,220
V26
A,Z26
26
27
tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and lEe Publication 617-12.
TEXAS
~
INsrRUMENTS
9-146
POST OFFICE BOX 1443· HOUSTON. TEXAS 77001
SMJ417400
4194 304·WORD BY 4·BIT
DYNAMIC RANDOM·ACCESS MEMORY
SGMS044-NOVEMBER 1992
functional block diagram
w
t
t
L
'!
AO
A1
A10
•
•
Column
Address
Buffers
32
•
•
'-
Sense Amplifiers
-I-
256KArray
256KArray
32
Row
Address
Buffers
·••
'---
1,--
256KArray
•
••
~
32
e
c
0
d
e
/
256KArray
10
- Data
256KArray
R
0
w
0
10
-
~
Column Oecoda
2
L
•
t
9.
/
•
t
Timing and Control
I/O
Buffers
40f32
Selection
21-256KArray
1..-
f-+~
4
In
Reg.
4--;-
Data
Out
Reg.
r+-+-
-
4
OQ1 -OQ4
of
/
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
9-147
SMJ417400
4194 304·WORD BY 4·BIT
DYNAMIC RANDOM·ACCESS MEMORY
SGMS044--NOVEMBER 1992
absolute maximum ratings over operating free-air temperature t
Voltage range on any pin (see Note 1) ................................................. - 1 V to 7 V
Voltage range on Vee ............................................................. , - 1 V to 7 V
Short circuit output current ................................................................ 50 mA
Power dissipation .......................................................................... 1 W
Operating free-air temperature range .............................................. - 55°C to 125°C
Storage temperature range ....................................................... - 65°C to 150°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values in this data sheet are with respect to VSS.
recommended operating conditions
MIN
NOM
MAX
VCC
Supply voltage
4.5
5
5.5
UNIT
VIH
High-level input voltage
2.4
6.5
V
VIL
Low-level input voltage (see Note 2)
-1
0.8
V
TA
Operating free-air temperature
-55
125
'c
V
NOTE 2: The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used in this data sheet for logic
voltage levels only.
electrical characteristics over full ranges of recommended operating conditions (unless otherwise
noted)
PARAMETER
SMJ417400-60
TEST
CONDITIONS
VOH
High-level output
voltage
10H =-5 mA
VOL
Low-level output
voltage
IOL= 4.2mA
II
Input current
(leakage) *
MIN
MAX
2.4
SMJ417400-70
SMJ417400-80
SMJ417400-10
MIN
MIN
MIN
MAX
2.4
MAX
2.4
MAX
2.4
UNIT
V
0.4
0.4
0.4
0.4
V
VI = 0 to 6.5 V,
All other pins = 0 V to VCC
01:10
01:10
±10
±10
",A
10
Output current
(Ieakage)*
Vo =OtoVCC,
CAS high
±10
01:10
±10
±10
",A
ICCl
Read or write cycle
current (see Note 3)
Minimum cycle,
VCC = 5.5V
ICC2
Standby current
110
100
90
80
mA
After 1 memory cycle,
RAS and CAS high,
VIH = 2.4 V (TIL)
2
2
2
2
mA
After 1 memory cycle.
RAS and CAS high.
VIH = VCC-0.2V
(CMOS)
1
1
1
1
mA
ICC3
Average refresh
current (RAS-only or
CBR) (see Note 3)*
RAS cycling, CAS high
(RAS-only); RAS low
after CAS low (CBR)
110
100
90
80
mA
ICC4
Average page
current (see Note 4)*
RAS low. CAS cycling
70
65
60
55
mA
ICC7
Standby current
output enable
(see Note 5)*
RAS = VIH. CAS = VIL.
Data out = enabled
5
5
5
5
mA
* Minimum cycle, Vec = 5.5 V.
NOTES: 3. Measured with a maximum of one address change while RAS = VIL.
4. Measured with a maximum of one adddress change while CAS = VIH.
5. Measured with indicated conditions following a normal read cycle.
TEXAS
~
INsrRUMENTS
9-148
POST OFFICE BOX 1443· HOUSTON. TEXAS 77001
SMJ417400
4194 304·WORD BY 4·BIT
DYNAMIC RANDOM·ACCESS MEMORY
SGMS044-NOVEMBER 1992
capacitance over recommended ranges of supply voltage and operating free-air temperature,
f = 1 MHz (see Note 6)
PARAMETER
MIN
TYP
MAX
UNIT
Ci(A)
Input capacitance, address inputs
9
pF
Ci(RC)
Input capacitance, strobe inputs
8
pF
Ci(OE)
Input capacitance, output enable
8
pF
Ci(W)
Input capacitance, write-enable input
8
pF
Co
Output capacitance
14
pF
NOTE 6: Capacitance is sampled only at initial design and after any major changes. Samples are tested at 0 V and 25'C with a 1-MHz signal
applied to the pin under test. All other pins are open.
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature
PARAMETER
SMJ417400-60
MIN
MAX
SMJ417400·70
SMJ417400-S0
SMJ417400·10
MIN
MIN
MIN
MAX
MAX
MAX
UNIT
tM
Access time from column-address
30
35
40
45
ns
tCAC
Access time from CAS low
15
18
20
25
ns
tCPA
Access time from column precharge
35
40
45
50
ns
tRAC
Access time from RAS low
60
70
80
100
ns
tOEA
Access time from OE low
15
18
20
25
ns
tCLl
CAS to output in low Z
0
tOFF
Output disable time after CAS high
(see Note 8)
0
15
0
18
0
20
0
25
ns
tOEZ
Output disable time after OE high
(see Note 8)
0
15
0
18
0
20
0
25
ns
NOTES:
0
0
0
ns
7. Valid data is presented at the outputs after all access times are satisfied but may go from a high-impedance state to an invalid data
state prior to the specified access times, as the outputs are driven when CAS goes low.
8. tOFF and !OEZ are specified when the outputs are no longer driven. The outputs are disabled by bringing either OE or CAS high.
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
9-149
SMJ417400
4 194 304·WORD BY 4·BIT
DYNAMIC RANDOM·ACCESS MEMORY
SGMS044-NOVEMBER 1992
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
SMJ417400-60
SMJ417400-70
SMJ417400-80
SMJ417400-10
MIN
MIN
MIN
MIN
MAX
MAX
MAX
MAX
UNIT
tRC
Random read or write cycle (see Note 9)
110
130
150
. 180
ns
tRWC
Read-write cycle time
155
181
205
245
ns
tpc
Page-mode read or write cycle time
(see Note 10)
40
45
50
55
ns
tPRWC
Page-mode read-write cycle time
85
96
105
120
ns
tRASP
Page-mode pulse duration, RAS low
(see Note 11)
60
100000
70
100000
80
100000
100
100000
ns
tRAS
Non-page-mode pulse duration, RAS low
(see Note 11)
60
10 000
70
10000
80
10000
100
10000
ns
10 000
18
10000
20
10000
25
10000
ns
tCAS
Pulse duration, CAS low (see Note 12)
15
tcp
Pulse duration, CAS high
10
10
10
10
ns
tRP
Pulse duration, RAS high (precharge)
40
50
60
70
ns
twp
Write pulse duration
15
15
15
15
ns
tASC
Column-address setup time before CAS low
0
0
0
0
ns
tASR
Row-address setup time before RAS low
0
0
0
0
ns·
tDS
Data setup time (see Note 13)
0
0
0
0
ns
tRCS
Read setup before CAS low
0
0
0
0
ns
leWL
W-Iow setup time before CAS high
15
18
20
25
ns
tRWL
W-Iow setup time before RAS high
15
18
20
25
ns
twcs
W-Iow setup time before CAS low
(Early write operation only)
0
0
0
0
ns
twSR
W-high setup time (CAS-before-RAS
refresh only)
10
10
10
10
ns
leAH
Column-address hold time after CAS low
10
15
15
15
ns
tDH
Data hold time (see Note 13)
10
15
15
15
ns
tRAH
Row-address hold time after RAS low
10
10
10
10
ns
tRCH
Read hold time after CAS high (see Note 14)
0
0
0
0
ns
tRRH
Read hold time after RAS high (see Note 14)
5
5
5
5
ns
twCH
Write hold time after CAS low
(Early write operation only)
15
15
15
15
ns
twHR
W-high hold time (CAS-before-RAS refresh
only)
10
10
10
10
ns
Continued next page.
NOTES: 9. All cycle times assume tT = 5 ns, referenced to VIH(min) and VIL(max)'
10. To assure tpc min, tASC should be greater than or equal to tcp.
11. In a read-write cycle, tRWD and tRWL must be observed.
12. In a read-write cycle, tCWD and tCWL must be observed.
13. Referenced to the later of CAS or W in write operations.
14. Either tRRH or tRCH must be satisfied for a read cycle.
TEXAS
~
INSTRUMENTS
9-150
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
SMJ417400
4194 304·WORD BY 4·BIT
DYNAMIC RANDOM·ACCESS MEMORY
SGMS044-NOVEMBER 1992
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (concluded)
SMJ417400-60
SMJ417400-70
SMJ417400-a0
SMJ417400-10
MIN
MIN
MIN
MIN
MAX
MAX
MAX
MAX
UNIT
tAWD
Delay time, column address 10 W low
(Read-wrile operation only)
55
63
70
80
ns
tCHR
Delay time, RAS low 10 CAS high
(CAS-before-RAS refresh only)
20
20
20
20
ns
tCRP
Delay time, CAS high to RAS low
5
5
5
5
ns
tCSH
Delay time, RAS low 10 CAS high
60
70
80
100
ns
tCSR
Delay time, CAS low to RAS low
(CAS-before-RAS refresh only)
10
10
10
10
ns
tCWD
Delay time, CAS low to W low
(Read-write operation only)
40
46
50
60
ns
tOEH
OE command hold time
15
18
20
25
ns
tOED
OE 10 dala delay
15
18
20
25
ns
tROH
RAS hold time referenced to OE
10
tRAD
Delay time, RAS low to column-address
(see Note 15)
15
tRAl
Delay lime, column-address 10 RAS high
30
35
40
45
ns
tCAl
Delay lime, column-address 10 CAS high
30
35
40
45
ns
tReD
Delay time, RAS low to CAS low
(see Note 15)
20
10
30
45
15
20
52
15
20
ns
10
10
35
40
60
15
20
55
75
ns
ns
tRPC
Delay lime, RAS high to CAS low
0
0
0
0
ns
tRSH
Delay time, CAS low to RAS high
15
18
20
25
ns
tRWD
(Read-write operalion only)
85
98
110
135
ns
ns
Delay time, RAS low to W low
ICPRH
RAS hold time from CAS precharge
35
40
45
50
ICPW
Delay time, W from CAS precharge
60
68
75
85
IREF
Refresh time inlerval
32
32
32
ns
32
ms
NOTE 15: The maximum value is specified only to assure access time.
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443· HOUSTON, TEXAS 77001
9-151
SMJ417400
4194 304·WORD BY 4·BIT
DYNAMIC RANDOM·ACCESS MEMORY
SGMS044-NOVEMBER 1992
PARAMETER MEASUREMENT INFORMATION
1.31 V
i
Output Under Test
=-i
CL=100pF
VCC =5V
RL=218Q
Output Under Test - - - . - -___
I
CL=100pF
(a) Load Circuit
(b) Alternate Load Circuit
Figure 1. Load Circuits for Timing Parameters
NOTE A: Output may go from a high-impedance state to an invalid data state prior to the specified access time.
Figure 2. Read Cycle Timing
TEXAS ~
INSfRUMENTS
9-152
POST OFFICE BOX 1443· HOUSTON. TEXAS 77001
SMJ417400
4194 304-WORD BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORY
SGMS044-NOVEMBER 1992
PARAMETER MEASUREMENT INFORMATION
DQ1-DQ4~,--_ _ _ _v_a_lId_D_a_ta_ _ _ _.J~X\*~~ VIH
-
VIL
Figure 3. Early Write Cycle Timing
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
9-153
SMJ417400
4194 304·WORD BY 4·BIT
DYNAMIC RANDOM·ACCESS MEMORY
SGMS044-NOVEMBER 1992
PARAMETER MEASUREMENT INFORMATION
Figure 4. Write Cycle Timing
TEXAS ~
INsrRUMENTS
9·154
POST OFFICE BOX 1443· HOUSTON, TEXAS 77001
SMJ417400
4 194 304·WORD BY 4·BIT
DYNAMIC RANDOM·ACCESS MEMORY
SGMS044-NOVEMBER 1992
PARAMETER MEASUREMENT INFORMATION
CAS
~
I
I
I
I
A(}"A10~
NOTE A: Output may go from a high-impedance state to an invalid data state prior to the specified access time.
Figure 5. Read-Write Cycle Timing
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
9-155
SMJ417400
4194 304·WORD BY 4·BIT
DYNAMIC RANDOM·ACCESS MEMORY
SGMS044-NOVEMBER 1992
PARAMETER MEASUREMENT INFORMATION
Column
A0-10
I
~ tRCS
-~I
W £££AfI
+I:
I
I
I+- tRAD ~
I
1
I
~
I
1
~~~~c..c.~~ VIL
lAA -----I.-~
I I.
I
I
:1
YIX7
I.
1
tRAC
(see Note B)
.1
.1
~
DQ1-DQ4-----------:(-Se-e~N:-ot-e"":'A~)....
I
Valid
Out
I
~
1
I
~t
I
I
_
OFF
~
~
1I
I
1 ~ I+- tOEZ
+l
-ffiVIH
VIL
I
1 .1
tCPA
~tCAC~
1:1
1
/ }~_--JI :::
ii r
I
I
1111 tRAS ·1
Y
N: i i i
:i
~
I
tRP
N
I
-+1
t\.
I I
tCAS
I I
II
I I
I I
tRP
ii
'I',
I I
II
I I
I I
on'tare
A0-10
.1
tCHR -
VIH
I I
VIL
II
I
I I
I
~
I I
I
VIH
~
~~~~~..c...:::...c...:::..c:.t::..c:.t::.~~~~~~~::w,~VIL
tRRH
l+-f--+j••
1-1
---+i
:tRCS
t+-
~
i+- twHR
~ ~tCAC
I
I i'4 I ~
~~~
~
t4- tWHR
i+-
twHR
v~tw~ ~tw\XxxmM I.-t~:::
~f/
tAA
~
tOFF
-+1 1'I~
DQ1-DQ4-----~---------V:-al-ld-D-at-a-O-ut----'l::\-:_ _ _ _ _ _~}- VOL
tCLZ
~~~~
--.1 ~
till--*-
OE~
tOEZ
tOEA
'I',
Figure 11. Hidden Refresh Cycle (Read)
TEXAS . "
INsrRUMENTS
9·160
POST OFFICE BOX 1443' HOUSTON, TEXAS 77001
~I
~VIH
~VIL
SMJ44C250
262144 BY 4-BIT MULTIPaRT VIDEO RAM
SGMS037B-JANUARY 1991-REVISED FEBRUARY 1993
•
•
•
•
•
•
Military Operating Temperature
Range ••• - 55°C to 125°C
Processed to MIL-STD-833, Class B
DRAM: 262144 Words x 4 Bits
SAM: 512 Words x 4 Bits
Dual Port Accessibility - Simultaneous
and Asynchronous Access From the DRAM
and SAM Ports
Bidirectional Data Transfer Function
Between the DRAM and the Serial Data
Register
Write Per Bit Feature for Selective Write to
Each RAM I/O
•
Enhanced Page Mode Operation for Faster
Access
•
CAS-before-RAS and Hidden Refresh
Modes
•
•
•
Vii
AD-AS
CAS
DOD-D03
SE
RAS
SC
SDOO-SD03
TRG
Long Refresh Period ••• Every 8 ms (Max)
Up to 33 MHz Uninterrupted Serial Data
Streams
W
•
512 Selectable Serial Register Starting
Locations
Texas Instruments EPIC'" CMOS Process
Packaging Options
- 28-pin Ceramic Side Brazed DIP
(JD suffix)
- 28-pln Ceramic Small Outline J-Leaded
Chip Carrier (HJ Suffix)
Split Serial Data Register for Simplified
Realtime Register Reload
VSS
SOO3
SOO2
SE
003
002
OSF
CAS
OSF
AO
A1
A2
A3
A7
GNO
RAS
AS
A6
A5
A4
VCC
RAM Output Enable Allows Direct
Connection of DQ and Address Lines to
Simplify System Design
3-State Serial I/Os Allow Easy Multiplexing
of Video Data Streams
•
SC
SOOO
SOO1
TRG
000
OQl
SC
SOOO
SOO1
TAG
000
OQl
Vii
GNO
RAS
AS
A6
A5
A4
VCC
VSS
SOO3
SOO2
SE
003
D02
OSF
CAS
OSF
AO
A1
A2
A3
A7
PIN NOMENCLATURE
•
•
•
HJ PACKAGE
(TOP VIEW)
JDPACKAGE
(TOP VIEW)
DSF
OSF
VCC
VSS
GND
Address Inputs
Column Enable
DRAM Data In-Out/Write Mask Bit
Serial Enable
Row Enable
Serial Data Clock
Serial Data In-Out
Transfer Register/O Output Enable
Write Mask SeleCt/Write Enable
Special Function Select
Split Register Activity Status
5-V Supply
Ground
Ground (Important: not connected
internally to VSS)
•
Performance Ranges:
ACCESS ACCESS ACCESS ACCESS
VCC
TIME
TIME
TIME TOLERANCE
TIME
COLUMN SERIAL SERIAL
ROW
ADDRESS ENABLE
DATA ENABLE
(MAX)
(MAX)
(MAX)
(MAX)
la(SE)
la(R)
la(C)
la(SC)
20 ns
±10%
'44C250-1 0 100 ns
25 ns
30 ns
±10%
30 ns
35 ns
25 ns
'44C250-12 120 ns
description
The SMJ44C250 multiport video RAM is a high speed, dual ported memory device, It consists of a dynamic
random-access memory (DRAM) organized as 262 144 words of 4 bits each interfaced to a serial data register,
or serial access memory (SAM), organized as 512 words of 4 bits each, The SMJ44C250 supports three basic
types of operation: random access to and from the DRAM, serial access to and from the serial register, and
bidirectional transfer of data between any row in the DRAM and the serial register. Except during transfer
EPIC is a trademark of Texas Instruments Incorporated.
~:~~~~: ==.~~:t!r: ::ro:!I~~~~m~~
atlndlrd .Irrlnty. Produdlon prDCUllng doel nat n.celllrily Include
'Mllng of aU pa,amlltrt.
TEXAS
~
Copyright © 1993, Texas Instruments Incorporated
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
9-161
SMJ44C250
262144 BY 4·BIT MULTIPORT VIDEO RAM
SGMS037B-JANUARY 1991-REVISED FEBRUARY 1993
operations, the SMJ44C250 can be accessed simultaneously and asynchronously from the DRAM and SAM
ports. During a transfer operation, the 512 columns ofthe DRAM are connected to the 512 positions in the serial
data register. The 512 x 4 bit serial data register can be loaded from the memory row (transfer read) or else the
contents of the 512 x 4 bit serial data register can be written to the memory row (transfer write).
The SMJ44C250 is equipped with several features designed to provide higher system-level bandwidth and
simplify design integration on both the DRAM and SAM ports. On the DRAM port, a write mask register provides
a persistent write-per-bit without repeated mask loading.
On the serial register, or SAM port, the SMJ44C250 offers a split-register transfer read (DRAM to SAM) option,
which enables realtime register reload implementation for truly continuous serial data streams without critical
timing requirements. The register is divided into a high half and a low half. While one half is being read out of
the SAM port, the other half can be loaded from the memory array. This new realtime register reload
implementation allows truly continuous serial data. For applications not requiring realtime register reload (for
example, reloads done during CRT retrace periods), the single register mode of operation is retained to simplify
design. The SAM can also be configured in input mode, accepting serial data from an external device. Once
the serial register within the SAM is loaded, its contents can be transferred to the corresponding column
positions in any row in memory in a single memory cycle.
,
The SAM port is designed for maximum performance. Data can be input to or accessed from the SAM at serial
rates up to 33 MHz. During a split-register mode of operation, internal circuitry detects when the last bit position
is accessed from the active half of the register and immediately transfers control to the opposite half. A separate
open-drain output, designated QSF, is included to indicate which half of the serial register is active at any given
time in the split register mode.
All address lines and data-in are latched on-chip to simplify system design. All data-outs are unlatched to allow
greater system flexibility.
.
The SMJ44C250 is offered both in a 28-pin 400-mil dual-in-line ceramic sidebrazed package (JD suffix) for
through-hole row insertion, and in a 28-pin ceramic small outline J-Ieaded chip carrier package (HJ suffix) for
surface-mount applications. The L suffix device is tested for operation from O°C to 70°C. The M suffix device
is tested for operation from - 55°C to 125°C.
The SMJ44C250 and other SMJ44C25x multiport video RAMs are supported by a broad line of video/graphic
processors from Texas Instruments, including the SMJ34010 and the SMJ34020 graphics processors.
TEXAS ~
INSTRUMENTS
9·162
POST OFFICE BOX 1443· HOUSTON, TEXAS 77001
SMJ44C250
262144 BY 4·BIT MULTIPORT VIDEO RAM
SGMS037B-JANUARY 1991-REVISEO FEBRUARY 1993
functional block diagram
o BV-----------------,
ut u~--------------------------~
f
P f
OQO
o-.r~;l~~-l ~ ~
+-0 Vee
+-OVSS
OQl
OQ2
OQ3
+-OAO
+-0 Al
OSF
+-OA2
+-OA3
+-OA4
+-0 AS
+-OA6
+-OA7
+-OA8
0-------.,
r n
e
8
t
e
h r
SOOOO-H-I-..
SOQl
SOQ2
SOQ3
Detailed Pin Description vs Operational Mode
PIN
DRAM
TRANSFER
AO-AS
Row, Column Address
Row, Tap Address
CAS
Column Enable, Output Enable
Tap Address Strobe
DOi
DRAM Data 1(0, Write Mask Bits
DSF
Persistent Write-per-bit Enable
Write-per-bit Mask Load Enable
Split Register Enable
Alternate Write Transfer Enable
RAS
Row Enable
Row Enable
Serial-In Mode Enable
SE
se
Serial Enable
Serial Clock
Serial Data 1(0
SDOi
TRG
a Output Enable
Transfer Enable
W
Write Enable, Write-per-Bit Select
Transfer Write Enable
OSF
Vee
SAM
Split Register Active Status
5-V Supply (typical)
VSS
Device Ground
GND
System Ground (Important: not connected internally to VSS)
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
9-163
SMJ44C250
262 144 BY 4·BIT MULTIPaRT VIDEO RAM
SGMS037B--JANUARY 1991-REVISED FEBRUARY 1993
operation
random access operation
Aefer to Table 1, Functional Table (page 7), for random access and transfer operations. Aandom access
operations are denoted by the designator "A" and transfer operations are denoted by a "T."
transfer register select and DQ enable (TRG)
The TAG pin selects either register or random access operation as AAS falls. For random access (DAAM)
mode, TAG must be held high as AAS falls. Asserting TAG high as AAS falls causes the 512 storage elements
of each data register to remain disconnected from the corresponding 512-bit lines of the memory array.
(Asserting TAG low as AAS falls connects the 512-bit positions in the serial register to the bit lines and indicates
that a transfer will occur between the data registers and the selected memory row. See transfer operation for
details.)
During random access operations, TAG also functions as an output enable for the random (0) outputs.
Whenever TRG is held high, the 0 outputs are in the high-impedance state to prevent an overlap between the
address and DAAM data. This organization allows the connection of the address lines to the data I/O lines but
prohibits the use of the early write cycle. It also allows read-modify-write cycles to be performed by providing
a three-state condition to the common I/O pins so that write data can be driven onto the pins after output read
data has been externally latched.
address
(A~A8)
Eighteen address bits are required to decode 1 of 262 144 storage cell locations. Nine row address bits are set
up on pins AO through A8 and latched onto the chip on the falling edge of RAS. Then the nine column address
bits are set up on pins AO through A8 and latched onto the chip on the falling edge of CAS. All addresses must
be stable on or before the falling edges of AAS and CAS.
RAS and CAS address strobes and device control clocks
AAS is a control input that latches the states of the row address, W, TAG, SE, CAS, and DSF onto the chip to
invoke the various DAAM and transfer functions of the SMJ44C250. AAS is similar to a chip enable in that it
activates the sense amplifiers as well as the row decoder. CAS is a control input that latches the states of the
column address and DSF to control various DAAM and transfer functions. CAS also acts as an output enable
for the DAAM output pins.
special function select (DSF)
The special function select input is latched on the falling edges of AAS and CAS, similarly to an address, and
serves three functions. First, during write cycles DSF invokes persistent write-per-bit operation. If TAG is high,
W is low, and DSF is low on the falling edge of RAS, the write mask will be reloaded with the data present on
the DO pins. If DSF is high, the mask will not be reloaded but will retain the data from the last mask reload cycle.
Second, DSF is used to change the internally stored write-per-bit mask register (or write mask) via the load write
mask cycle. The data present on the DO pins when W falls is written to the write mask rather than to the
addressed memory location. See "Delayed Write Cycle Timing" and the accompanying "Write Cycle State Table"
in the timing diagram section. Once the write mask is loaded, it can be used on subsequent masked write-per-bit
cycles. This feature allows systems with a common address and data bus to use the write-per-bit feature,
eliminating the time needed for multiplexing the write mask and input data on the data bus.
Third, the DSF pin is used to invoke the split-register transfer and serial access operation, described in the
sections ''transfer operation" and "serial operation".
TEXAS
~
INSTRUMENTS
9-164
POST OFFICE BOX 1443· HOUSTON. TEXAS 77001
SMJ44C250
262144 BY 4·BIT MULTIPaRT VIDEO RAM
SGMS037B-JANUARY 1991-REVISED FEBRUARY 1993
write enable, write-per-bit enable (W)
The W pin enables data to be written to the DRAM and is also used to select the DRAM write-per-bit mode of
operation. A logic high level on the W input selects the read mode and logic low level selects the write mode.
In an early write cycle, W is brought low before CAS and the DRAM output pins (DO) remain in the
high-impedance state for the entire cycle. During DRAM write cycles, holding W low on the falling edge of RAS
will invoke the write-per-bit operation. Two modes of write-per-bit operation are supported.
Case 1, !f DSF is low on the falling edge of RAS, the write mask is reloaded. Accordingly, a four-bit binary code
(the write-per-bit mask) is input to the device via the random DO pins and is latched on the falling edge of RAS.
The write-per-bit mask selects which of the four random I/Os are written and which are not. After RAS has
latched the write mask on-chip, input data is driven onto the DO pins and is latched on the falling edge of the
later of CAS or W. If a low was strobed into a particular I/O pin on the falling edge of RAS, data will not be written
to that I/O. If a high was strobed into a particular I/O pin on the falling edge of RAS, data will be written to that
I/O.
Case 2. If DSF is high on the falling edge of RAS, the mask is not reloaded from the DO pins but instead retains
the value stored during the last write-per-bit mask reload. This mode of operation is known as persistent
write-per-bit, since the write-per-bit mask is persistent over an arbitrary number of cycles.
See the corresponding timing diagrams for details. IMPORTANT: The write-per-bit operation is invoked only if
W is held low on the falling edge of RAS. If W is held high on the falling edge of RAS, write-per-bit is not enabled
and the write operation is identical to that of standard x 4 DRAMs.
data I/O (000-003)
DRAM data is written during a write or read-modify-write cycle. The falling edge of IN strobes data into the
on-chip data latches. In an early write cycle, W is brought low prior to CAS and the data is strobed in by CAS
with data setup and hold times referenced to this signal. In a delayed write or read-modify-write cycle, CAS will
already be low. Thus, the data will be strobed in by W with data setup and hold times referenced to this signal.
The 3-state output buffers provide direct TTL compatibility (no pullup resistors required) with a fanout of two
Series 74/54 TTL loads. Data-out is the same polarity as data-in. The outputs are in the high impedance
(floating) state as long as CAS or TRG is held high. Data will not appear at the outputs until after both CAS and
TRG have been brought low. Once the outputs are valid, they remain valid while CAS and TRG are low. CAS
or TRG going high returns the outputs to a high-impedance state. In an early write cycle, the outputs are always
in the high-impedance state. In a register transfer operation (memory-to-register or register-to-memory), the
outputs remain in the high-impedance state for the entire cycle.
enhanced page mode
Unlike conventional page-mode DRAMs, the column-address buffers in this device are activated on the falling
edge of RAS. The buffers act as transparent or flow-through latches while CAS is high. The falling edge of CAS
latches the column addresses. This feature allows the SMJ44C250 to operate at a higher data bandwidth than
conventional page-mode parts, since data retrieval begins as soon as column address is valid rather than when
CAS transitions low. This performance improvement is referred to as enhanced page mode. Valid column
address may be presented immediately after row address hold time has been satisfied, usually well in advance
ofthe falling edge of CAS. In this case, data is obtained afterta(C) max (access time from CAS low), ifta(CA) max
(access time from column address) has been satisfied. In the event that column addresses for the next page
cycle are valid at the time CAS goes high, access time for the next cycle is determined by the later occurrence
of ta(C) or ta(CP) (access time from rising edge of CAS).
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
9·165
SMJ44C250
262 144 BY 4·BIT MULTIPaRT VIDEO RAM
SGMS037B-JANUARY 1991-REVISED FEBRUARY 1993
Enhanced page mode operation allows faster memory access by keeping the same row address while selecting
random column addresses. The time for row address setup, row address hold, and address multiplex is thus
eliminated, and a memory cycle time reduction of up to 3 x can be achieved, compared to minimum RAS cycle
times. The maximum number of columns that may be accessed is determined by the maximum RAS low time
and page mode cycle time used. The SMJ44C250 allows a full page (512 cycles) of information to be accessed
in read, write, or read-modify-write mode during a single RAS low period using relatively conservative page
mode cycle times.
During write-per-bit operations, the DO pins are used to load the write-per-bit mask register described above
under the Vii pin description.
refresh
A refresh operation must be performed to each row at least once every eight milliseconds to retain data. Since
the output buffer is in the high-impedance state (unless CAS is applied), the RAS-only refresh sequence avoids
any output during refresh. Strobing each of the 512 row addresses with RAS causes all bits in each row to be
refreshed. CAS can remain high (inactive) for this refresh sequence to conserve power.
CAS-before-RAS refresh
CAS-before-RAS refresh is accomplished by bringing CAS low earlier than RAS. The external row address is
ignored and the refresh address is generated internally.
GND (Pin 8)
This pin is reserved for the manufacturer's test operation. It is an input and should be tied to system ground to
ensure proper device operation.
IMPORTANT: GND is not connected internally to
Vss.
TEXAS
..Jf
INSTRUMENTS
9-166
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
SMJ44C250
262144 BY 4·BIT MULTIPaRT VIDEO RAM
SGMS037B-JANUARY 1991-REVISED FEBRUARY 1993
Table 1. Functional Table
T
CAS
FALL
RAS FALL
Y
P
Et
CAS
TRG
W1I
DSF
SE
DSF
R
L
x§
x
x
x
x
DQG-DQ3
ADDRESS
FUNCTION
CAS
RAS
CASt
Vi
x
x
x
X
CAS-before-RAS Refresh
Tap
Point
X
X
Register to Memory Transfer
(Transfer Write)
RAS
T
H
L
L
X
L
X
Row
Addr
T
H
L
L
H
X
X
Row
Addr
Tap
Point
X
X
Alternate Transfer Write
(Independent of SE)
T
H
L
L
L
H
X
Refresh
Addr
Tap
Point
X
X
Serial Write-Mode Enable
(Pseudo-Transfer Write)
T
H
L
H
L
X
X
Row
Addr
Tap
Point
X
X
Memory to Register Transfer
(Transfer Read)
T
H
L
H
H
X
X
Row
Addr
Tap
Point
X
X
Split Register Transfer Read
(Must Reload Tap)
R
H
H
L
L
X
L
Row
Addr
Col
Addr
Write
Mask
Valid
Data
Load and Use Write Mask.
Write Data to DRAM
R
H
H
L
H
X
L
Row
Addr
Col
Addr
X
Valid
Data
Persistent Write-Per-Bit,
Write Data to DRAM
R
H
H
H
L
X
L
Row
Addr
Col
Addr
X
Valid
Data
Normal Dram Read/Write
(Nonmasked)
R
H
H
H
H
X
L
Refresh
Addr
X
X
Write
Mask
Load Write Mask
t R =Random access operation; T =Transfer operation.
t DOG-D03 are latched on the later of IN or CAS falling edge.
§ X = Don't care.
1IIn persistent wrHe-per-bit function, IN must be high during the refresh cycles
Addr Mask = 1; write to address location enabled
Write Mask = 1; write to I/O enabled.
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
9-167
SMJ44C250
262144 BY 4·BIT MULTIPORTVIDEO RAM
SGMS037~ANUARY
1991--REVISED FEBRUARY 1993
random port to serial port interface
Col
o
Row
o
Random-Access Port
Col
Col
Col
255
256
511
r-----+-----,
oa
Memory Array
262144 Bits
Row
511 L........,._ _- ' -_ _..,....--'
256
TRG
A8
DSF
W
Transfer
Control
Logic
SE
SC
AO-A8
A8
soa
SE
TRG
W
Figure 1. Block Diagram Showing One Random and One Serial I/O Interface
random-address space to serial-address space mapping
The 512 bits in each of the four data registers of the SAM are connected to the 512 column locations of each
of the four random I/Os. Data can be accessed in or out of the SAM starting at any of the 512 data bit locations.
This start location is selected by addresses AO through AS on the falling edge of CAS during any transfer cycle.
The SAM is accessed starting from the selected start address, proceeding from the lowest to the highest
significant bits. After the most significant bit position (511) is accessed, the serial counter wraps around such
that bit 0 is accessed on the next clock pulse. The selected start address is stored and used for all subsequent
transfer cycles until CAS is again brought low during any transfer cycle. Thus, the start address can be set once
and CAS held high during all subsequent transfer cycles and the start address point will not change regardless
of data present on AO through AS.
split-register mode random-address to serial address-space mapping
In split-register transfer operations, the serial data register is split into halves, the low half containing bits D-255
and the high half containing bits 256-511 . When a split-register transfer cycle is performed, the tap address must
be strobed in on the falling edge of CAS. The most significant column address bit (AS) determines which register
half will be reloaded from the memory array. The eight remaining column address bits (AD-A7) are used to select
the SAM starting location for the register half selected by AS.
TEXAS
~
INsrRUMENTS
9-168
POST OFFICE BOX 1443' HOUSTON, TEXAS 77001
SMJ44C250
262144 BY 4·BIT MULTIPaRT VIDEO RAM
SGMS037B-JANUARY 1991-REVISEO FEBRUARY 1993
To insure proper operation when using the split-register read transfer feature, a non-split-register transfer must
precede any split-register sequence. The serial start address must be supplied for every split-register transfer.
(See Split Register Operating Sequence on page 36.)
transfer operations
As illustrated in Table 1, the SMJ44C250 supports five basic transfer modes of operation:
1.
Normal Write Transfer (SAM to DRAM)
2.
Alternate Write Transfer (independent of the state of SE)
3.
Pseudo Write Transfer (SWitches serial port from serial-out mode to serial-in mode. No actual data transfer
takes place between the DRAM and the SAM.)
4.
Normal Read Transfer (Transfer entire contents of DRAM to SAM)
5.
Split-Register Read Transfer (Divides the SAM into a high and a low half. Only one half is transferred to the
SAM while the other half is read from the serial I/O port.)
NOTES: A. All transfer write operations will switch the SDa pins into the input (write) mode. Before data can be clocked into the serial port via
the SDO pins and SC serial clock, it is necessary to switch the SDO pins into input mode via a previous transfer write operation.
B. Pseudo Transfer Write Mode has the same meaning as the term "Write Mode Control Cycle" as used in some VRAM data sheets.
Both modes, or control cycles, serve to switch the direction of the SDOs without an actual data transfer taking place.
C. All transfer read operations will switch the SDO pins into the output (read) operation.
D. All transfer read operations and the pseudo transfer write operation perform a memory refresh on the selected row.
transfer register select (TRG)
Transfer operations between the memory array and the data registers are invoked by bringing TRG low before
RAS falls. The states of W, SE, and DSF, which are also latched on the falling edge of RAS, determine which
transfer operation will be invoked. (See Table 2.)
During read transfer cycles, TRG going high causes the addressed row of data to be transferred into the data
register. Although the previous data in the data register is overwritten, the last bit of data appearing at SDO
before TRG goes high will remain valid until the first positive transition of SC after TRG goes high. The data at
SDO will then switch to new data beginning from the selected start, or tap, position.
transfer write enable
(W)
In register transfer mode, W determines whether a read or a write transfer will occur. To perform a write transfer,
Wand SE are held low as RAS falls. If SE is high during this transition, no transfer of data from the data register
to the memory array occurs, but the SDOs are put into the input mode. The SDOs are put into input mode by
use of a transfer write cycle. This allows serial data to be input into the SAM. An alternative way to perform the
transfer write cycle is by holding DSF high on the falling edge of RAS. In this way, the state of SE is a Don't Care
as RAS falls. To perform a read transfer operation, Wis held high and SE is a Don't Care as RAS falls. This cycle
also puts the SDOs into the read mode, allowing serial data to be shifted out of the data register. (See
Table 2.)
column enable (CAS)
If CAS is brought low during a control cycle, the address present on the pins AO through A8 will become the new
register start location. If CAS is held high during a control cycle, the previous tap address will be retained from
the last transfer cycle in which CAS went low to set the tap address.
addresses (AO through AS)
Nine address bits are required to select one of the 512 possible rows involved in the transfer of data to or from
the data registers. The states of AD-A8 are latched on the falling edge of RAS to select one of 512 rows for the
transfer operation.
To select one of the 512 positions in the SAM from which the first serial data will be accessed, the appropriate
9-bit column address (AD-A8) must be valid when CAS falls. However, the CAS and start (tap) position need
not be supplied every cycle, only when changing to a different start position.
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
9-169
SMJ44C250
262 144 BY 4·BIT MULTIPaRT VIDEO RAM
SGMS037~ANUARY
1991-REVISED FEBRUARY 1993
In the split-register transfer mode, the most significant column address bit (AS) selects which half of the register
will be loaded from the memory array. The remaining eight addresses (AD-A?) determine the register starting
location for the register to be loaded.
special function Input (DSF)
In the read transfer mode, holding DSF high on the falling edge of RAS selects the split-register mode transfer
operation. This mode divides the serial data register into a high order half and a low order half; one active, and
one inactive. When the cycle is initiated, a transfer occurs between the memory array and either the high half
or the low half register, depending on the state of the most significant column address bit (AS) that is strobed
in on the falling edge of CAS. If AS is high, the transfer is to the high half of the register. If AS is low, the transfer
is to the low half of the register. Use ofthe split-register mode read transfer feature allows on-the-fly read transfer
operation without synchronizing TRG to the serial clock.
In the write transfer mode, holding DSF high on the falling edge of RAS permits use of an alternate mode of
transfer write. This mode allows SE to be high on the falling edge of RAS without permitting a pseudo write
transfer with the serial port disabled during the entire transfer write cycle.
serial access operation
Refer to Tables 2 and 3 for the following discussion on serial access operation.
serial clock (SC)
Data (SDO) is accessed in or out of data registers on the rising edge of SC. The SMJ44C250 is designed to work
with a wide range of clock duty cycles to simplify system design. Since the data registers comprising the SAM
are of static design, there are no SAM refresh requirements and there is no minimum SC clock operating
frequency.
serial data Input/output (SDQO-SDQ3)
SD and SO share a common I/O pin. Data is input to the device when SE is low during write mode, and data
is outputfrom the device when SE is low during read mode. The data in the SAM will be accessed in the direction
from least significant bit to most significant bit. The data registers operate modulo 512. Thus, after bit 511 is
accessed, the next bits to be accessed will be bits 00,01,02, and so on.
serial enable (SE)
The serial enable pin has two functions: first, it is latched on the falling edge of RAS, with both TRG and W low
to select one ofthe transfer functions (see Table 2). If SE is low during this transition, then a transfer write occurs.
If SE is high as RAS falls and DSF is low, then a write mode control cycle is performed. The function of this cycle
is to switch the SDOs from the output mode to the input mode, thus allowing data to be shifted into the data
register. NOTE: All transfer read and serial mode enable (pseudo transfer write) operations will perform a
memory refresh operation on the selected row.
Second, during serial access operations, SE is used as an SDO enable/disable. In the write mode, SE is used
as an input enable. SE high disables the input and SE low enables the input. To take the device out of the write
mode and into the read mode, a transfer read cycle must be performed. The read mode allows data to be
accessed from the data register. While in the read mode, SE high disables the output and SE low enables the
output.
IMPORTANT: While SE is held high, the serial clock is NOT disabled. Thus, external SC pulses will increment
the internal serial address counter regardless of the state of SE. This ungated serial clock scheme minimizes
access time of serial output from SE low since the serial clock input buffer and the serial address counter are
not disabled by SE.
TEXAS
..If
INSTRUMENTS
9-170
POST OFFICE BOX 1443· HOUSTON. TEXAS 77001
SMJ44C250
262144 BY 4·BIT MULTIPORT VIDEO RAM
SGMS037B-JANUARY 1991-REVISED FEBRUARY 1993
QSF active status output
QSF is an open-drain output pin. During the split register mode of serial access operation, QSF indicates which
half ofthe serial register in the SAM is being accessed. If QSF is low, then the serial address pointer is accessing
the low (least significant) 256 bits of the SAM. If QSF is high, then the pointer is accessing the higher (most
significant) 256 bits of the SAM.
QSF changes state upon crossing the boundary between the two register halves. When the SAM is not operating
in split-register mode, the QSF output remains in the high-impedance state.
QSF is designed as an open drain output to allow OR-type of QSF outputs from several chips. Thus, an external
pullup resistor is required for the zero-to-one transition on QSF, and the output rise time is determined by the
load-capacitance and the value ofthe pullup resistor. The specification for QSF switching time assumes a pull up
resistor of 820 Q and a load capacitance of 30 pF illustrated as follows.
5V
Q,,-1
T
820Q
30 pF
VSS
Figure 2. QSF Load Circuit
Table 2. Transfer Operation Logic
TRG
SE
W
DSF
MODE
L
L
L
X
Register to memory (write) transfer,
serial write mode enable
L
L
X
H
Alternate register to memory transfer
L
L
H
L
Serial write mode enable
(pseudo write transfer)
L
H
X
L
Memory to register (read) transfer
L
H
X
H
Split-register read transfer
NOTE: Above logic states are assumed valid on the failing edge of RAS.
Table 3. Serial Operation Logic
LAST TRANSFER CYCLE
SE
Alternate register to memory
SDa
H
Input Disabled
Serial write mode enable t
L
Input Enabled
Serial write mode enable t
H
Input Disabled
Memory to register
L
Output Enabled
Memory to register
H
Hi-Z
t Pseudo transfer write.
power up
To achieve proper device operation, an initial pause of 200!1s is required after power up, followed by a minimum
of eight RAS cycles or eight CAS-before-RAS cycles, a memory-to-register transfer cycle, and two SC cycles.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
9-171
SMJ44C250
262 144 BY 4-BIT MULTIPaRT VIDEO RAM
SGMS037EhJANUARY 1991-REVISED FEBRUARY 1993
absolute maximum ratings over operating temperature (unless otherwise noted)t
Input voltage on any pin except DO and SDO (see Note 1) ............................... -1 V to 7 V
Input voltage on DO and SDO (see Note 1) ........................................ -1 V to Vee + 1
Supply voltage range on Vee (see Note 1) ............................................... 0 V to 7 V
Short circuit output current (per output) ..................................................... 50 mA
Power dissipation .......................................................................... 1 W
Operating free-air temperature range:
SMJ44C250, L suffix .......................................................... O°C to70°C
SMJ44C250, M suffix ..................................................... -55°C to 125°C
Storage temperature range ....................................................... -65°C to 150°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values in this data sheet are with respect to VSS.
recommended operating conditions
Vee
Supply voltage
VSS
Supply vo~age
VIH
High-level input voltage
VIL
loW-level input voltage (see Note 2)
TA
Operating free-air temperature
Te
Operating case temperature
MIN
NOM
MAX
4.5
5
5.5
V
Vee + 1
0.6
V
-1
L suffix
Msuffix
0
Lsuffix
TEXAS ~
INsrRUMENTS
POST OFFle" BOX 1443 • HOUSTON. TEXAS 77001
V
'e
-55
M suffix
..
..
..
NOTE 2: The algebraiC convention, where the more negative (less positive) limit IS deSignated as minimUm, IS used
voltage levels only.
9-172
V
0
2.9
UNIT
70
'e
125
In thiS data sheet for logiC
SMJ44C250
262 144 BY 4·BIT MULTIPaRT VIDEO RAM
SGMS037B-JANUARY 1991-REVISED FEBRUARY 1993
electrical characteristics over full ranges of recommended operating conditions
PARAMETER
TEST CONDITIONS
VOH
High level output voltage
IOH=-5mA
VOL
Low level output voltage (see Note 4)
IOL=4.2 mA
II
Input leakage current
10
Output leakage current (see Note 3)
MIN
=
VI 0 to 5.B V, Vee = 5 V,
. All other pins open
Vo = 0 to Vee, Vee = 5.5 V
SAM
PORT
PARAMETER
MAX
2.4
'44C250-10
MIN
MAX
V
0.4
V
",1.0
IlA
",10
IlA
'44C250-12
MIN
MAX
leC1
leC1A
Operation current tc(RW) = Minimum
lc(sC) = Minimum
Standby
100
90
Active
110
100
ICC2
leC2A
Standby current, All clocks = Vec
tc(SC) = Minimum
Standby
15
15
Active
35
35
leC3
ICC3A
RAS-only refresh current, tc(RW) = Minimum
tc(SC) = Minimum
Standby
100
90
Active
110
100
ICC4
leC4A
Page mode current, Ic(p) = Minimum
tc(SC) = Minimum
Standby
S5
so
Active
70
S5
ICC5
ICC5A
CAS-before-RAS current, tc(RW) = Minimum
tc(SC) = Minimum
Standby
90
BO
Active
110
100
ICCS
leCSA
Data transfer current, tc(RW) = Minimum
tc(SC) = Minimum
Standby
100
90
Active
110
100
NOTES:
(see Note 5)
UNIT
UNIT
mA
3. SE IS disabled for SDO output leakage tests.
4. The SMJ44e250 1-megabit video RAM may exhibit simultaneous switching noise as described in Texas Instruments Advanced
CMOS Logic Designer's Handbook. This phenomenon exhibits itself upon the DO pins when the SDO pins are switched and upon
the SDO pins when DO pins are switched. This may cause the VOL and VOH to exceed the data book limit for a short period oftime,
depending upon output loading and temperature. Care should be taken to provide proper termination, decoupling, and layout of the
device to minimize simultaneous switching effects.
5. lec (standby) vs ICCA (active) denotes the following:
ICC (standby) denotes that the SAM port is inactive (standby) and the DRAM port is active (except for ICC2).
leCA (active) denotes that the SAM port is active and the DRAM port is active (except for leC2).
lec is measured with no load on DO or SDO pins.
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
9-173
SMJ44C250
262144 BY 4·BIT MULTIPORTVIDEO RAM
SGMS037~ANUARY
1991-REVISED FEBRUARY 1993
capacitance over recommended ranges of supply voltage and operating temperature,
f = 1 MHz (see Note 6)
PARAMETER
MIN
MAX
UNIT
Ci(A)
Input capacitance, address inputs
7
pF
CilRCj
Input capacitance, strobe inputs
7
pF
ColO)
Output capacitance, SDO and DO
8
pF
Co(OSF)
Output capacitance, OSF
t4
pF
...
NOTE 6: Capacijance IS sampled only at Imllal design and after any malar change. Samples are tested at 0 V and 25°C With a 1 MHz signal applied
to the pin under test. All other pins are open.
switching characteristics over recommended ranges of supply voltage and operating temperature
(see Note 7)
NO.
TEST
CONDITIONS
PARAMETER
"
= MAX
= MAX
Ict(RLCL) =MIN
td(RLCL) =MIN
ALT.
SYMBOL
'44C250-10
MIN
MAX
'44C250-12
MIN
MAX
UNIT
1
ta(C)
Access time from CAS
td(RLCL)
tCAC
25
30
ns
2
ta(CA)
Access time from column address
tdlRLCL)
tCM
50
60
ns
3
ta(CP)
Access time from CAS high
tCAP
55
65
ns
4
ta(R)
Access time from RAS
tRAC
100
120
ns
5
ta(G)
Access time of
tOEA
25
30
ns
6
t------
SMJ44C250
262 144 BY 4-BIT MULTIPaRT VIDEO RAM
SGMS037B-JANUARY 1991-REVISED FEBRUARY 1993
PARAMETER MEASUREMENT INFORMATION
I"
~I
tc(W)
___.....,,1 I"
N
twIRL)
~
td(RLCH)
~I
I..
I
-J--.J ~ th(RA)
AO-AS
I
1
th(RLCA)
i
I
I I
I
I
1 I" I
I
.1
tw(CH)
:
--~.I
~ q:., ~'-------
tsu(SFR)
DSF
Id(CLRH)
tw(CL)
'4-ld(RLCL) --+j..
I ~
~
0
I I.- tw(RH) --I
-+I '-- tr
I
.1 I
td(CHRL) ---+I
I
I..
IT --+I
I
I
+I [4-i-
+i
~ tsu(SFC)
I
I
I
~::: '~'-------
tsu(TRG)
-.I 14+
I
I
n
I
I
I.- th(TRG)
1 1
1 1
1 1
1
1
1
1
1
1
"-
~II
--JI I~:tsu(W;:m;
I
I I I
I I I"
th(RWM)
n
I"
I..
I
I
14-I ~
I
I
I
I
I
I
I
I..
.1
tsu(WCH)
tsu(WRH)
th(RLW)
th(CLW)
[+-ltsu(WCL)
.1
.1
I
W~
~:i
I
13
I
I
I
tSU(OQR).,
th(ROQ)
i+"t
I I I
I" !
1
tSI,I(OCL) ~
r
~
I" I
I
i
I
DQ~
I
.1
~
I
i
tw(WL)
i+7
I..
th(CLO)
th(RLO)
·1
.1
.:
5
~
NOTE A: See 'Write Cycle State Table" for the logic state of "1", "2", "3", "4", and "5",
Figure 5, Early Write Cycle Timing
TEXAS ~
INsrRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
9-179
SMJ44C250
262144 BY 4·BIT MULTIPaRT VIDEO RAM
SGMS037B-JANUARY 1991--REVISED FEBRUARY 1993
PARAMETER MEASUREMENT INFORMATION
144------------ C (W) ---~--------+i~1
_ _ _~I
~14--------lw(RL) _ _ _ _ _ _ _ _-.!~I
N
I
lOll
--I
!.-
IT
lOl
_ _ _.....!-+i+__Id_(R_L_C_L)_~~i4
I I
Ih(RA)
1 I
I
I
I lOl I
~I
I
-+i
I
~
~ ~
tsu(TRG)
1 1
ir-rT
.ii
I
-+I
W~
~:: ISU(wMR).
..
3(
-,
~
I~
~I
~
I
I
I
~I Ih(SFC)
lOl
Iw(CH)
--~~I
I
I
:, ~'-----I
I
I
:
:I
Id(GHD)
4
I 14
I I
I I
I I
lOl
Isu(WRH)
14
Isu(WCH)
Ilh(RLW)
~I
14 :
:
.:
~I
:1'1
Ih(RWM)
:
~I
Ih(CLW)
Isu(DWL) ~
Isu(DQR)
I
~ Ih(RDQ)
1
DQ~
.:
1
I"T
14
I
i
~
I I
1 I I
1
~
W\7\7\~~~lh(RLD)
Iw(WL)
Ih(WLD) ~
1
.1
~:
5
~
NOTE A: See "Write Cycle State Table" for the logic state of "1", "2", "3", "4", and "5".
Figure 6. Delayed Write Cycle Timing
TEXAS ~
INSTRUMENTS
9-180
I
I
I
~:*+'
~~I
~
.+m'
~. . ______
!
I ISU'(SFC)
Ih(SFR) ,-::+I !oJ-
DSF
1
~:
I I
+-.I I+-
1 !+-i--1h(RLCA)
AD-AS
Id(CLRH)
Iw(CL)
~
0
I I.- Iw(RH) ---+I
-+I ~ IT
1
~I I
1
Id(CHRL) ---+I
1
~
Id(RLCH)
1
POST OFFICE BOX 1443' HOUSTON, TEXAS 77001
SMJ44C250
262144 BY 4·BIT MULTIPaRT VIDEO RAM
SGMS037~ANUARY
1991-REVISED FEBRUARY 1993
PARAMETER MEASUREMENT INFORMATION
write cycle state table
CYCLE
STATE
1
2
3
4
5
Valid
Data
Write mask load/use write DOs to 1/05
L
L
L
Write
Mask
Use previous write mask, write DOs to 1/05
H
L
L
Don't
Care
Valid
Data
Load write mask on later of Vii fall and CAS fall
H
L
H
Don't
Care
Write
Mask
Normal early or late write operation
L
L
H
Don't
Care
Valid
Data
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
9-181
SMJ44C250
262144 BY 4·BIT MULTIPORT VIDEO RAM
SGMS037B-JANUARY 1991-REVISED FEBRUARY 1993
PARAMETER MEASUREMENT INFORMATION
NOTE A: See 'Write Cycle State Table" for the logic state of "1", "2", "3", "4", and "5", Same logic as delayed write cycle,
Figure 7. Read-Write/Read-Modify-Write Cycle Timing
TEXAS ~
INSTRUMENTS
9-182
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
SMJ44C250
262 144 BY 4-BIT MULTIPaRT VIDEO RAM
SGMS037B-JANUARY 1991-REVISED FEBRUARY 1993
PARAMETER MEASUREMENT INFORMATION
tw(RH) -+I
~101------------ twIRL) ------------~~I I
~
RASi'l
I
i
~I..- - - td(RLCL) ----.!~I
1.0- tw(CL) -.;
i
T\\l
I I
~ tsu(RA)
I
:..
r-
I
I4--ld(CLRH)
: - tw(CH)
~!
(
~I
~I
,"
I..
I
I
.Ai:
I
I I
tc(P)
th(CLCA)
---+!
14- td(CHRL) -.!
\\1
.-
J-1i
I .td(RLf H) :
I
th(RA) --.j
.r-oI-.l"-----.... th(RLCA)
~I
I
I
I
I
I
td(CARH ---r-Li-><:::-rc+J."",,:k7'i"""~
AD-AS
Column
~
I
I
DSF~
I
N----
t Access time is ta(CP) or ta(CA) dependent.
:j: Output may go from high-impedance state to an invalid data state prior to the specified access time.
NOTE A: A write cycle or a read-modify-write cycle can be mixed with the read cycles as long as the write and read-modify-write timing
specifications are not violated and the proper polarity of DSF is selected on the falling edge of RAS and CAS to select the desired write
mode (normal, block write, etc.).
Figure 8. Enhanced Page-Mode Read Cycle Timing
TEXAS
~
INSfRUMENTS
POST OFFICE BOX 1443· HOUSTON, TEXAS 77001
9-183
SMJ44C250
262 144 BY 4·BIT MULTIPaRT VIDEO RAM
SGMS037B-JANUARY 1991-REVISED FEBRUARY 1993
PARAMETER MEASUREMENT INFORMATION
~
~~
~
I.
I
I..
I
I..
I
I
td(RLCH)
td(RLCL)
tw(CL)
I I
---..I I+t
I I
AO-A8
tsu(RA)
14-- th(RA)
~~.
~::
-.I
I
~I
I
I
f\\i
Y
~
I
I
!
I
th(SFR)
tc(P)
I I-- tw(CH) ---+I
I"
I
-+j I I tsu(SFR)
DSF
~I
-to!
R_
I
I I '-
-.I
~ I I..
I
I..
tsu(CA)
~
I
I
~I
th(CLCA)
.
~ tsu(SFC)
I
I..
I
I
I
th(SFC)
~: f : ~
I I
I..-t tsu(TRG)
I
I
I
I
II
: i
I·
I
I
,I
III I
I I
: ..~:-; _
~
I
I
~I
I
I
~
tw(RH) j,..-.I
I+-- td(GLRH) --.I I
I
I
~ td(CHRL) -+I
f\\l I
krc~ c.~m' : ki
~
~I
tsul (SFC)
14
I
I
,!
'.
I
I
I
I
t Referenced to CAS or W, whichever occurs last.
NOTES: A. See "Write Cycle State Table" for the logic state of "1 ", "2", "3", "4", and "5".
B. A read cycle or a read-modify-write cycle can be intermixed with write cycles, observing read and read-modify-write timing
specifications. TRG must remain high throughout the entire page-mode operation if the late write feature is used, to assure
page-mode cycle time. lithe early write cycle timing is used, the state ofTRG is a Don't Care aiterthe minimum period th(TRG) from
the falling edge of RAS.
Figure 9. Enhanced Page-Mode Write Cycle Timing
TEXAS ~
INSTRUMENTS
9-184
POST OFFICE BOX 1443· HOUSTON, TEXAS 77001
SMJ44C250
262 144 BY 4·BIT MULTIPaRT VIDEO RAM
SGMS037B-JANUARY 1991-REVISED FEBRUARY 1993
PARAMETER MEASUREMENT INFORMATION
1+4------------
RAS
twIRL)
-------------+l~1
~~-------------------------~----------------------~{I
J~i'I1 !14
~I
~
14
i ,_ ~I 14-~I
I
i 1-------t":.....~
14
~I
1 .
," I
• 1101-1------1: ,- J7\1 \lI
.vi 1\ ~
/1
-+I H1 1
1
I
I :
-+j I- ~
I
I
td(RLCH)
tw(RH)
tc(RDWP)
t
___
w(CL)
td(RLCL)
CAS
!su(RA)
td(CLRH)
tw(CH)
td(CHRLI
I
- ~~~~~"m': _:: ~'m~
Ih(RA)
SU(CA)i--'- Ih(CLCA)
1
I I
Ih(S~R) -H
1
I-
!--+- th(SFC)
I I
I
H-itsU(SFcl
~:~::"
I I
I I
tsu(WMR)
-!+-+i
I
I
14 I
I:
1
I
I I
!-i14
I
'I
Ih(RWM) -+I
.
1 I
1 1
I
W )(
~
~
: 14
3'
y:
I
'--r""'Ir-"
I
I
I
I4-l
'4
I!sU(DQR)
I+- Ih(RDQ)
iIsu(RO)
~ id(CLWL)
I
I
1
I I
Id(CAWL)
1!4-4----+t~I- Ih(SFC)
I
1
I
--+I:
I I
~I
...
i
~I
Ild(RLWL)
I
-+II+- la(C)
~I ta(CA) t
I, I
-+I I4j Isu(WCH)
_ _---:\4~1
~
tsu(WCH)
1 1
-1+---+1 1
I
1
I
1
I
~I
I
I
I
I
I
1
1
~
141
I
I
w(WL)
I
su(WRH)
\l
I
1 14 I ~I Ih(WLD)
tsu(DWL) +I i+'
I
i+- la(CP) t ~
~
.......--"""'""''''''''''......''''''''....
1
.F-:~~
, Valid ,,,,,,,,,v"/\/"/\/"/\/\/\/\/\/\/\/\/\/\
OUI
1
I+la(G) +I
I ta(R) ~
\l
:
I
NJy
I
~14------+f~1- Id(GHD)
i+1
:
I
I
Valid
Oul
I
~
~: tSU(~FC)
14::
I I
I
DQ
I
_ : : I,'
I 1
~I
1 I
],-1________---.
I
I+---+\Idls(G)
;,..1___________________
V
I
t Output may go from the high-impedance state to an invalid data state prior to the specified access time.
NOTES: A. See 'Write Cycle State Table" for the logic state of "1 ", "2", "3", "4", and "5".
B. A read or a write cycle can be intermixed with read-modify-write cycles as long as the read and write timing specifications are not
violated.
Figure 10. Enhanced Page-Mode Read-Modify-Write Cycle Timing
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443' HOUSTON, TEXAS 77001
9·185
SMJ44C250
262 144 BY 4-BIT MULTIPaRT VIDEO RAM
SGMS037B-JANUARY 1991-REVISED FEBRUARY 1993
PARAMETER MEASUREMENT INFORMATION
- - - - - - t c ( r d ) - - - - - -......,
I.
+
.I
Y1
I i00<
I
I
"~":
"--I
I
DSF
I
:~~
I
I
\....J
I
-----+---')"~'j
I
RO~8T~~2(L)
I
I
I
:n
:
\....J
:
RO~l~~2(H)
I
I
: >00<
: I',
I
I
I
: /\
: ',',
I
I
/\
I
:
I
SC~~~~
OSF
(RevH
Only)
TAP1 (L) I
I
ROWI
I
I
_ _ _ _ _ _.......1_ _'\"'_-'-.........
I
Ii
I BIT TAP1(HII
1255
ROWlI
I ROWI
I
I','~
\
OSF
\:
Normal Transfer Read
I From TAP1
I
I
I
I SC Cycles
I
Split-Register
I (OSF High
I
I
Half
~~~f.~~~~~:'I~~~: I ~!!f:~I~~
I
Split-Register
~~~s~~I;'b~~~~a
Register
16~ t:~ ~~tlf
Low Hall)
I
I
I"
I
r,',
I SC Cycles
I
:'Ir--J :
I
I BIT TAP2(LI I
1511
ROW) I
I~EI
:'I~
~:~s~,,:.:r;~ad
I SC Cycles
I
I
:
:
I
I
I 6~ ~;~ ~1!lf I
I (OSF Low
I
I
High Hall)
I
I
\
I
~!:f:~I~~
I
I
I
I
Repeat High/low
~:~u~c;,ac~
I
I
I
I
I
I
I
I
I
Low Hall)
I
I
I
I
NOTES: A. In the split-register mode, data can be transferred from different rows to the low and high halves of the data register.
B. When enabling or disabling the split-register mode, ta(QSF) is measured from RAS low in the transfer cycle.
Figure 20. Split"Register Operating Sequence
application notes
1.
In order to achieve proper split-register operation, a normal read transfer followed by a minimum of one
serial clock cycle should be performed before the first split-register transfer cycle. This is necessary to
initialize the data register and the starting tap location. Serial access can then begin after the normal transfer
cycle.
2.
Asplit-registertransfer into the inactive half is not allowed until td(TPRL) is met. td(TPRL) is the minimum delay
time between the rising edge of the serial clock (SC) of the previously loaded tap point and the falling edge
of RAS of the split-register transfer cycle into the inactive half.
3.
After td(TPRL) is met, the split-register transfer into the inactive half must also satiSfy the td(RHMS) condition.
td(RHMS) is the minimum delay time between the rising edge of RAS of the split-register transfer cycle into
the inactive half and the riSing edge of the last serial clock (SC 255 or 511) of the active half.
TEXAS
~
INSTRUMENTS
9-196
POST OFFICE BOX 1443' HOUSTON. TEXAS 77001
SMJ44C250
262 144 BY 4·BIT MULTIPaRT VIDEO RAM
SGMS037B-JANUARY 1991-REVISED FEBRUARY 1993
PARAMETER MEASUREMENT INFORMATION
14
tc(SC)
i.-- tw(SCL)
~i
sc
\
------.101.--
SOQ
~
I.-- tw(SCL) ~
Vi
I _ I
I
I+- tsu(SOS)
I
.1
tw(SCH) ----.:
I
--.!-+--ft1.!.
""lidO"':
~ icI(SESC)
I
'\,
r-
I+- tsu(SOS) ----..: ~ t
I
.~
-I ·h(SCS)
th(SCS)
~
X22222
""1d0".
-I
\{~!__________________________________________________
SE
Figure 21. Serial Data-In Timing
The serial data-in cycle (SO) is used to input serial data into the data registers. Before data can be written into
the data registers via SO, the device must be put into the write mode by performing a write mode control, or
transfer write cycle. Transfer write cycles occurring between the write mode control cycle and the subsequent
writing of data will not take the device out of the write mode. However, a transfer read cycle during that time will
take the device out of the write mode and put it into the read mode, thus disabling the input of data. Data will
be written starting at the location specified by the input address loaded on the previous transfer cycle.
While accessing data in the serial data registers, the state of TRG is a Don't Care as long as TRG is held high
when RAS goes low to prevent data transfers between memory and data registers.
~
tc~q
~
I+-- tw(SCH) ----.I I
j4-- tw(SCL) --+I I
I j4-- tw(SCL) ------.I
I
Y:
SC\
j4- th(SHSO)
14-- ta(SO)
'\
--M
2<
<
soo
~
0
I
i+-- ta(SO)
l
">C
I
--+i
SE
I+-
ta(SE)
~~!_____________________________________________________________
NOTE A: When the odd tap is used (tap addresses can be 0-511, and odd taps are 1,3,5 ... etc.), the cycle time for SC in the first serial data out
cycle needs to be 70 ns minimum.
Figure 22. Serial Data-Out Timing
The serial data-out (SQ) cycle is used to read data out of the data registers. Before data can be read via SQ,
the device must be put into the read mode by performing a transfer read cycle. Transfer write cycles occurring
between the transfer read cycle and the subsequent shifting out of data will not take the device out of the read
mode. But a write mode control cycle at that time will take the device out of the read mode and put it in the write
mode, thus not allowing the reading of data.
While accessing data in the serial data registers, the state of TRG is a Don't Care as long as TRG is held high
when RAS goes low to prevent data transfers between memory and data registers.
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443· HOUSTON, TEXAS 77001
9-197
SMJ44C250
262 144 BY 4·BIT MULTIPaRT VIDEO RAM
SGMS037B-JANUARY 1991-REVISED FEBRUARY 1993
TEXAS ~
INSTRUMENTS
9-198
POST OFFICE BOX 1443· HOUSTON, TEXAS 77001
SMJ44C251
262144 BY 4·BIT MULTIPORT VIDEO RAM
SGMS038B-JANUARY 1991-REVISED FEBRUARY 1993
JD PACKAGEt
(TOP VIEW}
• Military Operating Temperature
Range ..• - 55°C to 125°C
• Processed to MIL-STD-883, Class B
• DRAM: 262 144 Words x 4 Bits
SAM: 512 Words x 4 Bits
• Dual Port Accessibility-Simultaneous and
Asynchronous Access From the DRAM and
SAM Ports
• Bidirectional Data Transfer Function
Between the DRAM and the Serial Data
Register
• 4 x 4 Block Write Feature for Fast Area Fill
Operations. As Many as Four Memory
Address Locations Written Per Cycle From
an On-Chip Color Register
SC
SOOO
SD01
TRG
DOO
001
Vss
S003
S002
SE
D03
D02
DSF
CAS
OSF
AO
A1
A2
W
GND
RAS
AS
A6
A5
A4
VCC
HJ PACKAGEt
(TOP VIEW}
'---'
SC
SOOO
S001
TRG
000
001
Vss
SD03
S002
SE
D03
D02
OSF
CAS
OSF
AO
A1
A2
A3
W
A3
GNO
RAS
AS
A6
A5
A4
A7
VCC
'---'
A7
t Packages shown are for pinout reference only.
• Write Per Bit Feature for Selective Write to
Each RAM I/O
PIN NOMENCLATURE
• Enhanced Page-Mode Operation for Faster
Access
AO-AS
CAS
DQO-DQ3
• CAS-Before-RAS and Hidden Refresh
Modes
RAS
SC
SDQO-SDQ3
• RAM Output Enable Allows Direct
Connection of DQ and Address Lines to
Simplify System Design
W
• Long Refresh Period ... Every 8 ms (Max)
DSF
QSF
• Up to 33 MHz Uninterrupted Serial Data
Streams
VCC
VSS
GND
• 3-State Serial I/Os Allow Easy Multiplexing
of Video Data Streams
Address Inputs
Column Enable
DRAM Data In-Out/Write Mask Sit
Serial Enable
Row Enable
Serial Data Clock
Serial Data In-Out
Transfer Register / Q Output Enable
Write Mask Select/Write Enable
Special Function Select
Split Register Activity Status
5-V Supply
Ground
Ground (Important: Not conneC1ed
to internal VSS)
• 512 Selectable Serial Register Starting
Locations
• Performance Ranges:
• Texas Instruments EPIC'· CMOS Process
• Packaging Options:
- 28-Pin Ceramic Sidebraze DIP (JD Suffix)
- 28-Pin Ceramic Small Outline J-Leaded
Chip Carrier (HJ Suffix)
• Split Serial Data Register for Simplified
Realtime Register Reload
ACCESS ACCESS ACCESS ACCESS VCC
TIME
TIME
TIME
TIME TOLERANCE
ROW
COLUMN SERIAL SERIAL
ADDRESS ENABLE
(MAX)
(MAX)
ENABLE
(MAX)
la(R)
'44C251-10 100 ns
ta(C)
25 ns
ta(SC)
30 ns
ta(SE)
20 ns
±10%
'44C251-12 120 ns
30 ns
35 ns
25 ns
±10%
(MAX)
DATA
description
The SMJ44C251 multipart video RAM is a high speed, dual ported memory device. It consists of a dynamiC
random-access memory (DRAM) organized as 262 144 words of 4 bits each interfaced to a serial data register,
or serial access memory (SAM), organized as 512 words of 4 bits each. The SMJ44C251 supports three basic
EPIC is a trademark of Texas Instruments Incorporated.
TEXAS
~
Copyright © 1993, Texas Instruments Incorporated
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
9-199
SMJ44C251
262144 BY 4·BIT MULTIPaRT VIDEO RAM
SGMS038~ANUARY
199l-REVISED FEBRUARY 1993
types of operation: random access to and from the DRAM, serial access to and from the serial register, and
bidirectional transfer of data between any row in the DRAM and the serial register. Except during transfer
operations, the SMJ44C251 can be accessed simultaneously and asynchronously from the DRAM and SAM
ports. During a transfer operation, the 512 columns ofthe DRAM are connected to the 512 positions in the serial
data register. The 512 x 4 bit serial data register can be loaded from the memory row (transfer read) or else the
contents of the 512 x 4 bit serial data register can be written to the memory row (transfer write).
The SMJ44C251 is equipped with several features designed to provide higher system-level bandwidth and
simplify design integration on both the DRAM and SAM ports. On the DRAM port, greater pixel draw rates can
be achieved by the device's 4 x 4 block write mode. The block write mode allows four bits of data present in an
on-chip color data register to be written to any combination of four adjacent column address locations. As many
as 16 bits of data can be written to memory during each CAS cycle time. Also on the DRAM port, a write mask
register provides a persistent write-per-bit without repeated mask loading.
On the serial register, or SAM port, the SMJ44C251 offers a split-register transfer read (DRAM TO SAM) option,
which enables realtime register reload implementation for truly continuous serial data streams without critical
timing requirements. The register is divided into a high half and a low half. While one half is being read out of
the SAM port, the other half can be loaded from the memory array. This new realtime register reload
implementation allows truly continuous serial data. For applications not requiring realtime register reload (for
example, reloads done during CRT retrace periods), the single register mode of operation is retained to simplify
design. The SAM can also be configured in input mode, accepting serial data from an external device. Once
the serial register within the SAM is loaded, its contents can be transferred to the corresponding column
positions in any row in memory in a single memory cycle.
The SAM port is designed for maximum performance. Data can be input to or accessed from the SAM at serial
rates up to 33 MHz. During a split-register mode of operation, internal circuitry detects when the last bit position
is accessed from the active half of the register and immediately transfers control to the opposite half. A separate
open-drain output, designated QSF, is included to indicate which half of the serial register is active at any given
time in the split register mode.
All address lines and data-in are latched on-chip to simplify system design. All data-outs are unlatched to allow
greater system flexibility.
The SMJ44C251 is offered both in a 28-pin 400-mil dual-in-line ceramic sidebrazed package (JD suffix) for
through-hole row insertions, and in a 28-pin ceramic small outline J-Ieaded chip carrier package (HJ suffix) for
surface-mount applications. The L suffix device is tested for operation from O°C to 70°C. The M suffix device
is tested for operation from - 55°C to 125°C.
The SMJ44C251 and other SMJ44C25x multiport video RAMs are supported by a broad line of video/graphic
processors from Texas Instruments, including the SMJ34010 and the SMJ34020 graphics processors.
TEXAS ~
INsrRUMENTS
9-200
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
SMJ44C251
262 144 BY 4·BIT MULTIPaRT VIDEO RAM
SGMS038B-JANUARY 1991-REVISED FEBRUARY 1993
functional block diagram
o BV----------------,
+-OVcc
+-OVSS
DQOo-+-H-'
OQl
OQ2
OQ3
+-OAO
+-OAl
+-OA2
+-OA3
+-OA4
+-0 AS
+-0 AS
+-OA7
+-OAB
OSFo-----l
SOB
e
r
I
soao
SOQl
SOQ2
SOQ3
e I
~
a
e
G
T e
I n
e
m r
I a
n I
go
r n I
I P I
U
+-0 CAS
+-OTRG
+-OW
+-OSC
+-OSE
I I r
Detailed Pin Description vs Operational Mode
PIN
DRAM
TRANSFER
AO-AS
Row, Column Address
Row, Tap Address
Tap Address Strobe
CAS
Column Enable, Output Enable
DOi
DRAM Data I/O, Write Mask Bits
DSF
Block Write Enable
Persistent Write-per-Bit Enable
Color Register Load Enable
Write-per-Bit Mask Load Enable
Split Register Enable
Alternate Write Transfer Enable
RAS
Row Enable
Row Enable
SE
Serial-In Mode Enable
SAM
Serial Enable
Serial Clock
SC
SDOi
Serial Data I/O
TRG
a Output Enable
Transfer Enable
Vi
Write Enable, Write-per-Bit Select
Transfer Write Enable
Split Register
Active Status
OSF
VCC
5-V Supply (typical)
VSS
Device Ground
GND
System Ground (Important: not connected internally to VSS)
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
9-201
SMJ44C251
262144 BY 4·BIT MULTIPaRT VIDEO RAM
SGMS038IMJANUARY 1991-REVISED FEBRUARY 1993
operation
random access operation
Refer to Table 1, Functional Table (page 9), for random access and transfer operations. Random access
operations are denoted by the designator "R" and transfer operations are denoted by a "T."
transfer register select and OQ enable (TRG)
The TRG pin selects either register or random access operation as'RAS falls. For random access (DRAM)
mode, TRG must be held high as RAS falls. Asserting TRG high as RAS falls causes the 512 storage elements
of each data register to remain disconnected from the corresponding 512-bit lines of the memory array.
(Asserting TRG low as RAS falls connects the 512-bit positions in the serial register to the bit lines and indicates
that a transfer will occur between the data registers and the selected memory row. See transfer operation for
details.)
During random access operations, TRG also functions as an output enable for the random (0) outputs.
Whenever TRG is held high, the 0 outputs are in the high-impedance state to prevent an overlap between the
address and DRAM data. This organization allows the connection of the address lines to the data I/O lines but
prohibits the use of the early write cycle. It also allows read-modify-write cycles to be performed by providing
a three-state condition to the common I/O pins so that write data can be driven onto the pins after output read
data has been externally latched.
address (AO-AS)
Eighteen address bits are required to decode 1 of 262 144 storage cell locations. Nine row address bits are set
up on pins AO through A8 and latched onto the chip on the falling edge of RAS. Then the nine column address
bits are set up on pins AO through AS and latched onto the chip on the falling edge of CAS. All addresses must
be stable on or before the falling edges of RAS and CAS.
RAS and CAS address strobes and device control clocks
RAS is a control input that latches the states of the row address, W, TRG, SE, CAS, and DSF onto the chip to
invoke the various DRAM and transfer functions of the SMJ44C251. RAS is similar to a chip enable in that it
activates the sense amplifiers as well as the row decoder. CAS is a control input that latches the states of the
column address and DSF to control various DRAM and transfer functions. CAS also acts as an output enable
for the DRAM output pins.
special function select (OSF)
The special function select input is latched on the falling edges of RAS and CAS, Similarly to an address,and
serves four functions.
First, during write cycles DSF invokes perSistent write-per-bit operation. If TRG is high, W is low, and DSF is
low on the falling edge of RAS, the write mask will be reloaded with the data present on the DO pins. If DSF is
high, the mask will not be reloaded but will retain the data from the last mask reload cycle.
Second, DSF is used to change the internally stored write-per-bit mask register (or write mask) via the load write
mask cycle. The data present on the DQ pins when W falls is written to the write mask rather than to the
addressed memory location. See "Delayed Write Cycle Timing" and the accompanying "Write Cycle State Table"
in the timing diagram section. Once the write mask is loaded, it can be used on subsequent masked write-per-bit
cycles. This feature allows systems with a common address and data bus to use the write-per-bit feature,
eliminating the time needed for multiplexing the write mask and input data on the data bus.
Third, the DSF pin is used to load an on-chip four-bit data, or "color", register via the Load Color Register cycle.
The contents of this register can subsequently be written to any combination of four adjacent column memory
locations using the 4 x 4-Block Write feature. The load color register cycle is performed using normal write cycle
timing except that DSF is held high on the falling edge of RAS and CAS. Once the color register is loaded, it
retains data until power is lost or until another load color register cycle is performed.
TEXAS
~
INSTRUMENTS
9-202
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
SMJ44C251
262144 BY 4·B11 MULTIPORT VIDEO RAM
SGMS038B--JANUARY 1991-REVISED FEBRUARY 1993
After loading the color register, the block write cycle can be enabled by holding DSF high on the falling edge
of CAS. During block write cycles, only the seven most significant column addresses (A2-A8) are latched on
the falling edge of CAS. The two least significant addresses (AO-A 1) are replaced by the four DO bits, which
are also latched on the later of CAS or W falling. These four bits are used as an address mask and indicate which
of the four column address locations addressed by A2-A8 will be written with the contents of the color register
during the write cycle, and which ones will not. DOD enables a write to column address A 1 = low, AD = low;
D01 enables a write to A 1 low, AD high; D02 enables a write to A 1 high, AD low; and D03 enables a
wiite to A 1 = high, AD '" high. A logic high level enables a write and a logic low leve! disables the write. A maximum
of 16 bits can be written to memory during each CAS cycle (see Figure 1, Block Write Diagram).
=
=
=
=
Fourth, the DSF pin is used to invoke the split-register transfer and serial access operation, described in the
sections ''transfer operation" and "serial operation".
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
9-203
SMJ44C251
262144 BY 4·BIT MULTIPORTVIDEO RAM
SGMS038B--JANUARY I 991-REVISED FEBRUARY ~993
N +1
N
N+2
N+3
Block Write
Enable
Load Color Register Cycle
RAS~
C~
/
I
I
I
I
Block Write Cyclet
(No DO Mask)
\
Block Write Cyclet
(Load and Use DO Mask)
/
'----'~I~I----~\
\
I~+-----~\
/
Block Write Cyclet
(Use Pervlously
Loaded DO Mask)
\
I~+---~\
t Wmust be low during the Block Write Cycle.
t DOD-D03 (CAS) are latched on the later of Wor CAS falling edge. DOD-D03 (RAS) are latched on RAS falling edge.
Legend:
1. Refresh Address
2. Row Address
3. Block Address (A2-AS)
4. Color Register Data
5. Column Mask Data
6. DO Mask Data
GD = Don't Care
Figure 1. Block Write Diagram
TEXAS ~
INSTRUMENTS
9-204
POST OFFICE BOX 1443· HOUSTON, TEXAS 77001
I
I
I
Ii
;l
SMJ44C251
262144 BY 4·BIT MULTIPaRT VIDEO RAM
SGMS03BB-JANUARY 1991-REVISED FEBRUARY 1993
write enable, wrlte-per-blt enable (W)
The W pin enables data to be written to the DRAM and is also used to select the DRAM write-per-bit mode of
operation. A logic high level on the W input selects the read mode and logic low level selects the write mode.
In an early write cycle, W is brought low before CAS and the DRAM output pins (DO) remain in the
high-impedance state for the entire cycle. During DRAM write cycles, holding WIowan the falling edge of RAS
will invoke the write-per-bit operation. Two modes of write-per-bit operation are supported.
Case 1. If DSF is Iowan the falling edge of RAS, the write mask is reloaded. Accordingly, a four-bit binary code
(the write-per-bit mask) is input to the device via the random DO pins and is latched on the falling edge of RAS.
The write-per-bit mask selects which of the four random I/Os are written and which are not. After RAS has
latched the write mask on-chip, input data is driven onto the DO pins and is latched on the falling edge of the
later of CAS or W. If a low was strobed into a particular I/O pin on the falling edge of RAS, data will not be written
to that I/O. If a high was strobed into a particular I/O pin on the falling edge of RAS, data will be written to that
I/O.
Case 2. If DSF is high on the falling edge of RAS, the mask is not reloaded from the DO pins but instead retains
the value stored during the last write-per-bit mask reload. This mode of operation is know as Persistent
Write-Per-Bit, since the write-per-bit mask is persistent over an arbitrary number of cycles.
See the corresponding timing diagrams for details. IMPORTANT: The write-per-bit operation is invoked only if
W is held low on the falling edge of RAS. If W is held high on the falling edge of RAS, write-per-bit is not enabled
and the write operation is identical to that of standard x 4 DRAMs.
data I/O (OQO-OQ3)
DRAM data is written during a write or read-modify-write cycle. The falling edge of W strobes data into the
on-chip data latches. In an early write cycle, W is brought low prior to CAS and the data is strobed in by CAS
with data setup and hold times referenced to this signal. In a delayed write or read-modify-write cycle, CAS will
already be low. Thus, the data will be strobed-in by W with data setup and hold times referenced to this signal.
The 3-state output buffers provide direct TTL compatibility (no pull up resistors required) with a fanout of two
Series 74/54 TTL loads. Data-out is the same polarity as Data-in. The outputs are in the high impedance
(floating) state as long as CAS or TRG is held high. Data will not appear at the outputs until after both CAS and
TRG have been brought low. Once the outputs are valid, they remain valid while CAS and TRG are low. CAS
or TRG going high returns the outputs to a high-impedance state. In an early write cycle, the outputs are always
in the high-irnpedance state. In a register transfer operation (memory-to-register or register-to-memory), the
outputs remain in the high-impedance state for the entire cycle.
enhanced page mode
Unlike conventional page-mode DRAMs, the column-address buffers in this device are activated on the falling
edge of RAS. The buffers act as transparent or flow-through latches while CAS is high. The falling edge of CAS
latches the column addresses. This feature allows the SMJ44C251 to operate at a higher data bandwidth than
conventional page-mode parts, since data retrieval begins as soon as column address is valid rather than when
CAS transitions low. This performance improvement is referred to as enhanced page mode. Valid column
address may be presented immediately after row address hold time has been satisfied, usually well in advance
ofthefalling edge of CAS. In this case, data is obtained afterta(C) max (access time from CAS low), ifta(CA) max
(access time from column address) has been satisfied. In the event that column addresses for the next page
cycle are valid at the time CAS goes high, access time for the next cycle is determined by the later occurrence
of ta(C) or ta(CP) (access time from rising edge of CAS).
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
9-205
SMJ44C251
262144 BY 4·BIT MULTIPORT VIDEO RAM
SGMS038B-JANUARY 1991-REVISED FEBRUARY 1993
Enhanced page mode operation allows faster memory access by keeping the same row address while selecting
random column addresses. The time for row address setup, row address hold, and address multiplex is thus
eliminated, and a memory cycle time reduction of up to 3 x can be achieved, compared to minimum RAS cycle
times. The maximum number of columns that may be accessed is determined by the maximum RAS low time
and page mode cycle time used. The SMJ44C251 allows a full page (512 cycles) of information to be accessed
in read, write, or read-modify-write mode during a single RAS low period using relatively conservative page
mode cycle times.
During write-per-bit operations, the DQ pins are used to load the write-per-bit mask register described above
under the Wpin description.
During block write operations, the DQ pins are used to load the on-chip color register during the load color
register cycle and are also used as a write enable during block write cycles.
refresh
A refresh operation must be performed to each row at least once every eight milliseconds to retain data. Since
the output buffer is in the high-impedance state (unless CAS is applied), the RAS-only refresh sequence avoids
any output during refresh. Strobing each of the 512 row addresses with RAS causes all bits in each row to be
refreshed. CAS can remain high (inactive) for this refresh sequence to conserve power.
CAS-before-RAS refresh
CAS-before-RAS refresh is accomplished by bringing CAS low earlier than RAS. The external row address is
ignored and the refresh address is generated internally.
GND (Pin 8)
This pin is reserved for the manufacturer's test operation. It is an input and should be tied to system ground to
ensure proper device operation.
IMPORTANT: GND is not connected internally to Vss.
TEXAS ~
INSTRUMENTS
9-206
POST OFFICE BOX 1443· HOUSTON. TEXAS 77001
SMJ44C251
262144 BY 4·BIT MULTIPORT VIDEO RAM
SGMS038EMJANUARY 1991-REVISED FEBRUARY 1993
Table 1. Functional Table
T
Et
R
CAS
FALL
RAS FALL
Y
P
CAS
TRG
W1I
DSF
SE
DSF
L
X§
x
x
x
x
DQD-DQ3
ADDRESS
FUNCTION
CAS
RAS
CAS;
W
x
x
x
X
CAS-before-RAS Refresh
Tap
Point
X
X
Register \0 Memory Transfer
(Transfer Write)
RAS
T
H
L
L
X
L
X
Row
Addr
T
H
L
L
H
X
X
Row
Addr
Tap
Point
X
X
Alternate Transfer Write
(Independent of SE)
T
H
L
L
L
H
X
Refresh
Addr
Tap
Point
X
X
Serial Write-Mode Enable
(Pseudo-Transfer Write)
T
H
L
H
L
X
X
Row
Addr
Tap
Point
X
X
Memory to Register Transfer
(Transfer Read)
T
H
L
H
H
X
X
Row
Addr
Tap
Point
X
X
Split Register Transfer Read
(Must Reload Tap)
R
H
H
L
L
X
L
Row
Addr
Col
Addr
Write
Mask
Valid
Data
Load and Use Write Mask,
Write Data to DRAM
R
H
H
L
L
X
H
Row
Addr
Col
A2-A8
Write
Mask
Addr
Mask
Load and Use Write Mask,
Block Write to DRAM
R
H
H
L
H
X
L
Row
Addr
Col
Addr
X
Valid
Data
Persistent Write-Per-Bit,
Write Data to DRAM
R
H
H
L
H
X
H
Row
Addr
Col
A2-A8
X
Addr
Mask
Persistent Write-Per-Bit,
Block Write to DRAM
R
H
H
H
L
X
L
Row
Addr
Col
Addr
X
Valid
Data
Normal Dram Read/Write
(Nonmasked)
R
H
H
H
L
X
H
Row
Addr
Col
A2-AS
X
Addr
Mask
Block Write to DRAM
(Nonmasked)
R
H
H
H
H
X
L
Refresh
Addr
X
X
Write
Mask
Load Write Mask
R
H
H
H
H
X
H
Refresh
Addr
X
X
Color
Data
Load Color Register
t R =Random access operation; T =Transfer operation.
; DOD-D03 are latched on the later of Wor CAS falling edge.
§ X = Don't care.
~ In persistent wr~e-per-bit function, W must be high during the refresh cycles
Addr Mask = I; write to address location enabled
Write Mask = 1; write to I/O enabled.
'TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443· HOUSTON. TEXAS 71001
9-207
SMJ44C251
262 144 BY 4·BIT MULTIPORT VIDEO RAM
SGMS038EhJANUARY 1991-REVISEO FEBRUARY 1993
random port to serial port interface
Col
o
Random-Access Port
Col
Col
Col
255
256
511
Row
o
oa
Memory Array
262144 Bits
Row
511
"'-....,..---"----r---'
256
TRG
AS
OSF
W
Transfer
Transfer
Control
Logic
SE
SC
AO-AS
AS
soa
SE
TRG
W
Figure 2. Block Diagram Showing One Random and One Serial I/O Interface
random address space to serial address space mapping
The 512 bits in each of the four data registers of the SAM are connected to the 512 column locations of each
of the four random I/Os. Data can be accessed in or out of the SAM starting at any of the 512 data bit locations.
This start location is selected by addresses AO through AS on the falling edge of CAS during any transfer cycle.
The SAM is accessed starting from the selected start address, proceeding from the lowest to the highest
significant bits. After the most significant bit position (511) is accessed, the serial counter wraps around such
that bit 0 is accessed on the next clock pulse. The selected start address is stored and used for all subsequent
transfer cycles until CAS is again brought low during any transfer cycle. Thus, the start address can be set-once
and CAS held high during all subsequent transfer cycles and the start address point will not change regardless
of data present on AO through AS.
split-register mode random-access to serial address-space mapping
In split-register transfer operations, the serial data register is split into halves, the low half containing bits 0-255
and the high half containing bits 256-511. When a split-register transfer cycle is performed, the tap address
must be strobed in on the falling edge of CAS. The most significant column address bit (AS) determines which
register half will be reloaded from the memory array. The eight remaining column address bits (AO-A?) are used
to select the SAM starting location for the register half selected by AS.
TEXAS
~
INsrRUMENTS
9-208
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
SMJ44C251
262144 BY 4-BIT MULTIPORT VIDEO RAM
SGMS038EhJANUARY 1991-REVISED FEBRUARY 1993
To insure proper operation when using the split-register read transfer feature, a non-split-register transfer must
precede any split-register sequence. The serial start address must be supplied for every split-register transfer.
(See Split Register Operating Sequence on page 38.)
transfer operations
As illustrated in Table 1, the SMJ44C251 supports five basic transfer modes of operation:
1.
Normal Write Transfer (SAM to DRAM)
2.
Alternate Write Transfer (independent of the state of SE)
3.
Pseudo Write Transfer (Switches serial port from serial-out mode to serial-in mode. No actual data transfer
takes place between the DRAM and the SAM.)
4.
Normal Read Transfer (Transfer entire contents of DRAM to SAM)
5.
Split-Register Read Transfer (Divides the SAM into a high and a low half. Only one half is transferred to the
SAM while the other half is read from the serial I/O port.)
soa
NOTES: A. All transfer wrne operations will switch the
pins into the input (write) mode. Before data can be clocked into the serial port via
pins into input mode via a previous transfer write operation.
the SOO pins and SC serial clock, it is necessary to switch the
B. Pseudo Transfer Write Mode has the same meaning as the term "Write Mode Control Cycle" as used in some VRAM data sheets.
Both modes, or control cycles, serve to switch the direction of the SDOs without an actual data transfer taking place.
C. All transfer read operations will switch the SOO pins into the output (read) operation.
O. All transfer read operations and the pseudo transfer wrne operation perform a memory refresh on the selected row.
soa
transfer register select (TRG)
Transfer operations between the memory array and the data registers are invoked by bringing TRG low before
RAS falls. The states of W, SE, and DSF, which are also latched on the falling edge of RAS, determine which
transfer operation will be invoked. (See Table 2.)
During read transfer cycles, TRG going high causes the addressed row of data to be transferred into the data
register. Although the previous data in the data register is overwritten, the last bit of data appearing at SDQ
before TRG goes high will remain valid until the first positive transition of SC after TRG goes high. The data at
SDQ will then switch to new data beginning from the selected start, or tap, position.
transfer write enable (W)
In register transfer mode, W determines whether a read or a write transfer will occur. To perform a write transfer,
Wand SE are held low as RAS falls. If SE is high during this transition, no transfer of data from the data register
to the memory array occurs, but the SDQs are put into the input mode. The SDQs are put into input mode by
use of a transfer write cycle. This allows serial data to be input into the SAM. An alternative way to perform the
transfer write cycle is by holding DSF high on the falling edge of RAS. In this way, the state of SE is a Don't Care
as RAS falls. To perform a read transfer operation, W is held high and SE is a Don't Care as RAS falls. This cycle
also puts the SDQs into the read mode, allowing serial data to be shifted out of the data register. (See
Table 2.)
column enable (CAS)
If CAS is brought low during a control cycle, the address present on the pins AD through A8 will become the new
register start location. If CAS is held high during a control cycle, the previous tap address will be retained from
the last transfer cycle in which CAS went low to set the tap address.
addresses (AD through AS)
Nine address bits are required to select one of the 512 possible rows involved in the transfer of data to or from
the data registers. The states of AD-A8 are latched on the falling edge of RAS to select one of 512 rows for the
transfer operation.
To select one of the 512 positions in the SAM from which the first serial data will be accessed, the appropriate
9-bit column address (AD-A8) must be valid when CAS falls. However, the CAS and start (tap) position need
not be supplied every cycle, only when changing to a different start position.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
9-209
SMJ44C251
262144 BY 4·BIT MULTIPaRT VIDEO RAM
SGMS03BB-JANUARY 1991-REVISED FEBRUARY 1993
In the split-register transfer mode, the most significant column address bit (AS) selects which half of the register
will be loaded from the memory array. The remaining eight addresses (AO-A7) determine the register starting
location for the register to be loaded.
special function Input (DSF)
In the read transfer mode, holding DSF high on the falling edge of RAS selects the split-register mode transfer
operation. This mode divides the serial data register into a high order half and a low order half; one active, and
one inactive. When the cycle is initiated, a transfer occurs between the memory array and either the high half
or the low half register, depending on the state of the most significant column address bit (AS) that is strobed
in on the falling edge of CAS. If AS is high, the transfer is to the high half of the register. If AS is low, the transfer
is to the low half of the register. Use of the split-register mode read transfer feature allows on-the-fly read transfer
operation without synchronizing TRG to the serial clock.
In the write 'ransfer mode, holding DSF high on the falling edge of RAS permits use of an alternate mode of
transfer write. This mode allows SE to be high on the falling edge of RAS without permitting a pseudo write
transfer, with the serial port disabled during the entire transfer write cycle.
serial access operation
Refer to Tables 2 and 3 for the following discussion on serial access operation.
serial clock (SC)
Data (SDQ) is accessed in or out of data registers on the rising edge of SC. The SMJ44C251 is designed to work
with a wide range of clock duty cycles to simplify system design. Since the data registers comprising the SAM
are of static design, there are no SAM refresh requirements and there is no minimum SC clock operating
frequency.
serial data Input/output (SDQO-SDQ3)
SO and SQ share a common I/O pin. Data is input to the device when SE is low during write mode and data is
output from the device when SE is low during read mode. The data in the SAM will be accessed in the direction
from least significant bit to most significant bit. The data registers operate modulo 512. Thus, after bit 511 is
accessed, the next bits to be accessed will be bits 00, 01,02, and so on.
serial enable (SE)
The serial enable pin has two functions: first, it is latched on the falling edge of RAS, with both TRG and W low
to select one ofthe transfer functions (see Table 2). If SE is low during this transition, then a transfer write occurs.
If SE is high as RAS falls and DSF is low, then a write mode control cycle is performed. The function of this cycle
is to switch the SDQs from the output mode to the input mode, thus allowing data to be shifted into the data
register. NOTE: All transfer read and serial mode enable (pseudo transfer write) operations will perform a
memory refresh operation on the selected row.
Second, during serial access operations, SE is used as an SDQ enable/disable. In the write mode, SE is used
as an input enable. SE high disables the input and SE low enables the input. To take the device out of the write
mode and into the read mode, a transfer read cycle must be performed. The read mode allows data to be
accessed from the data register. While in the read mode, SE high disables the output and SE low enables the
output.
IMPORTANT: While SE is held high, the serial clock is NOT disabled. Thus, external SC pulses will increment
the internal serial address counter regardless of the state of SE. This ungated serial clock scheme minimizes
access time of serial output from SE low since the serial clock input buffer and the serial address counter are
not disabled by SE.
TEXAS
~
IN5rRUMENTS
9-210
POST OFFICE BOX 1443· HOUSTON. TEXAS 77001
SMJ44C251
262144 BY 4·BIT MULTIPaRT VIDEO RAM
SGMS038B-JANUARY 1991-REVISED FEBRUARY 1993
aSF active status output
QSF is an open-drain output pin. During the split register mode of serial access operation, QSF indicates which
half ofthe serial register in the SAM is being accessed. If QSF is low, then the serial address pOinter is accessing
the low (least significant) 256 bits of the SAM. If QSF is high, then the pointer is accessing the higher (most
significant) 256 bits of the SAM.
QSF changes state upon crossing the boundary between the two register halves. When the SAM is not operating
in split-register mode, the QSF output remains in the high-impedance state.
QSF is designed as an open drain output to allow OR-type of QSF outputs from several chips. Thus, an external
pullup resistor is required for the zero to one transition on QSF and the output rise time is determined by the
load-capacitance and the value of the pull up resistor. The specification for QSF switching time assumes a pullup
resistor of 820 Q and a load capacitance of 30 pF illustrated as follows.
5V
~F-1 ~g
T
30pF
VSS
Figure 3. QSF Load Circuit
Table 2. Transfer Operation Logic
TRG
W
SE
DSF
MODE
L
L
L
X
Register to memory (write) transfer,
serial write mode enable
L
L
X
H
Alternate register to memory transfer
L
L
H
L
Serial write mode enable
(pseudo write transfer)
L
H
X
L
Memory to register (read) transfer
L
H
X
H
Split-register read transfer
NOTE: Above logic states are assumed valid on the falling edge of RAS.
Table 3. Serial Operation Logic
LAST TRANSFER CYCLE
SE
Alternate register to memory
SDa
H
Input Disabled
Serial write mode enable t
L
Input Enabled
Serial write mode enablet
H
Input Disabled
Memory to register
L
Output Enabled
Memory to register
H
HI-Z
t Pseudo transfer write.
power up
To achieve proper device operation, an initial pause of 200 ~s is required after power up, followed by a minimum
of eight RAS cycles or eight CAS-before-RAS cycles, a memory-to-register transfer cycle, and two SC cycles.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
9-211
SMJ44C251
262 144 BY 4-BIT MULTIPaRT VIDEO RAM
SGMS038B-JANUARY 1991-REVISED FEBRUARY 1993
absolute maximum ratings over operating temperature (unless otherwise noted)t
Input voltage range on any pin except DO and SDO (see Note 1) .................. ,...... -1 V to 7 V
Input voltage range on DO and SDO (see Note 1) ................................... -1 V to Vee + 1
Input voltage range on Vee (see Note 1) ................................................. 0 V to 7 V
Short circuit output current (per output) ..................................................... 50 mA
Power dissipation .......................................................................... 1 W
Operating free-air temperature range:
SMJ44C251, L suffix .......................................................... O°C t070°C
SMJ44C251, M suffix ..................................................... -55°C to 125°C
Storage temperature range ....................................................... -65°C to 150°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values in this data sheet are with respect to VSS.
recommended operating conditions
MIN
NOM
MAX
4.5
5
5.5
UNIT
vee
Supply voltage
VSS
Supply voltage
VIH
High-level input voltage
2.9
Vee + 1
V
VIL
LOW-level input voltage (see Note 2)
-1
0.6
V
0
Lsuffix
TA
Operating free-air temperature
Te
Operating case temperature
V
V
0
'e
M suffix
-55
Lsuffix
70
Msuffix
125
'e
NOTE 2: The algebraic convention, where·the more negalive (less positive) limit is designated as minimum, is used in this data sheet for logic
voltage levels only.
TEXAS ~
INsrRUMENIS
9-212
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
SMJ44C251
262 144 BY 4·BIT MULTIPaRT VIDEO RAM
SGMS038B-JANUARY 1991-REVISED FEBRUARY 1993
electrical characteristics over full ranges of recommended operating conditions
TEST CONDITIONS
PARAMETER
High level output voltage
10H =-5 mA
VOL
Low level output voltage (see Note 4)
IOL=4.2 mA
IL
Input leakage current
VI = 0 to 5.8 V, VCC = 5 V,
All other pins open
10
Output leakage current (see Note 3)
Va = 0 to VCC, VCC = 5.5 V
SAM
PORT
PARAMETER
MIN
MAX
2.4
VOH
V
0.4
V
±1.0
!lA
±10
!lA
'44C251-10
'44C251-12
MIN
MIN
MAX
MAX
ICC1
ICC1A
Operation current lc(RW) = Minimum
tc(SC) = Minimum
Standby
100
90
Active
110
100
ICC2
ICC2A
Standby current, All clocks = VCC
lc(SC) = Minimum
Standby
15
15
Active
35
35
ICC3
ICC3A
RAS-only refresh current, tc(RW) = Minimum
tc(SC) = Minimum
ICC4
ICC4A
Page mode current, tc(P) = Minimum
tc(SC) = Minimum
ICC5
ICC5A
CAS-before-RAS current, tc(RW) = Minimum
lc(SC) = Minimum
ICC6
ICC6A
Data transfer current, tc(RW) = Minimum
tc(SC) = Minimum
NOTES:
(see Note 5)
UNIT
Standby
100
90
Active
110
100
Standby
65
60
Active
70
65
Standby
90
80
Active
110
100
Standby
100
90
Active
110
100
UNIT
mA
3. SE is disabled for SDO output leakage tests.
4. The SMJ44C251 1-megabit video RAM may exhibit simultaneous switching noise as described in the Texas Instruments Advanced
CMOS Logic Designer's Handbook. This phenomenon exhibits itself upon the DO pins when the SOO pins are switched and upon
the SDO pins when DO pins are switched. This may cause the VOL and VOH to exceed the data book limitfor a short period oftime,
depending upon output loading and temperature. Care should be taken to provide proper termination, decoupling, and layout of the
device to minimize simultaneous switching effects.
5. ICC (standby) vs ICCA (active) denotes the following:
ICC (standby) denotes that the SAM port is inactive (standby) and the DRAM port is active (except for ICC2).
ICCA (active) denotes that the SAM port is active and the DRAM port is active (except for ICC2).
ICC is measured with no load on DO or SOO pins.
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
9-213
SMJ44C251
262144 BY 4·BIT MULTIPORT VIDEO RAM
SGMS038B-JANUARY 1991-REVISED FEBRUARY 1993
capacitance over recommended ranges of supply voltage and operating temperature,
f = 1 MHz (see Note 6)
MIN
PARAMETER
MAX
UNIT
Ci(A)
Input capac~ance, address inputs
7
Ci(RC)
Input capacitance, strobe inputs
7
pF
CoCO)
Output capacitance, SDO and DO
8
pF
Co(OSF)
Output capacitance, OSF
14
pF
pF
NOTE 6: Capacitance is sampled only at initial design and after any major change. Samples are tested at 0 V and 25'C with a 1 MHz signal applied
to the pin under test. All other pins are open.
switching characteristics over recommended ranges of supply voltage and operating temperature
(see Note 7)
NO.
TEST
CONDITIONS
PARAMETER
ALT.
SYMBOL
'44C251-10
'44C251-12
MIN
MIN
MAX
MAX
UNIT
1
ta(C)
Access time from CAS
td(RLCL) = MAX
tCAC
25
30
ns
2
ta(CAl
Access time from column address
td(RLCL) = MAX
tCM
50
60
ns
3
ta(CP)
Access time from CAS high
td(RLCL) = MIN
tCAP
55
65
ns
4
ta(R)
Access time from RAS
td(RLCL) = MIN
tRAC
100
120
ns
5
ta(G)
Access time of
tOEA
25
30
ns
6
ta(SO)
Access time of SO from SC high
tSCA
30
35
ns
7
talSEl
Access time of SO from SE low
= 30 pF
CL =30 pF
tSEA
20
25
ns
8
ta(OSF)
Access time of OSFfrom SC low
CL = 30 pF
60
60
ns
!dis(CH)
Random output disable time from CAS high
(see Note 8)
CL = 80 pF
tOFF
0
20
0
20
ns
!dis(G)
Random output disable time from TRG high
(see Note 8)
CL = 80 pF
toEZ
0
20
0
20
ns
!dis(SE)
Serial output disable time from SE high
(see Note 8)
CL
=30 pF
tSEZ
0
20
0
20
ns
9
10
11
NOTES:
a from TRG low
CL
7. Switching times assume CL = 100 pF unless otherwise noted (see Figure 3).
8. Disable times are specified when the output is no longer driven.
TEXAS
~
INSTRUMENTS
9-214
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
SMJ44C251
262144 BY 4·BIT MULTIPaRT VIDEO RAM
SGMS03B~ANUARY
1991-REVISED FEBRUARY 1993
timing requirements over recommended ranges of supply voltage and operating temperature t
NO,
PARAMETER
'44C251-10
ALT,
SYMBOL
MIN
MAX
'44C251-12
MIN
MAX
UNIT
12
lc(rd)
Read cycle time (see Note 9)
tRC
190
220
ns
13
lc(W)
Write cycle time
twc
190
220
ns
14
lc(rdW)
Read-modify-write cycle time
tRWC
250
290
ns
15
lc(p)
Page-mode read, write cycle time
tpc
60
70
ns
16
lc(RDWP)
Page-mode read-modify-write cycle time
tpRWC
105
125
ns
17
lc(TRD)
Transfer read cycle time
tRC
190
220
ns
18
lc(TW)
Transfer write cycle time
twc
190
220
ns
19
lc(SC)
Serial clock cycle time (see Note 10)
tscc
30
35
ns
20
tw(CH)
Pulse duration, CAS high
tcp
20
30
21
tw(CL)
Pulse duration, CAS low (see Note 11)
tCAS
25
22
tw(RH)
Pulse duration, RAS high
tRP
80
23
tw(RL)
Pulse duration, RAS low (see Note 12)
tRAS
100
24
tw(WL)
Pulse duration, W low
twp
25
25
25
1w(TRG)
Pulse duration, TRG low
25
30
ns
26
tw(SCH)
Pulse duration, SC high
tsc
10
12
ns
27
tw(SCL)
Pulse duration, SC low
tscp
10
12
ns
28
tsu(CA)
Column address setup time
tASC
0
0
ns
29
tsu(SFC)
DSF setup time before CAS low
0
0
ns
30
tsu(RA)
Row address setup time
tASR
0
0
ns
75000
30
ns
75000
90
75000
120
ns
ns
75000
ns
ns
31
tsu(WMR)
W setup time before RAS low
twSR
0
0
ns
32
lsu(DQR)
DQ setup time before RAS low (write mask operation)
tMS
0
0
ns
33
lsu(TRG)
TRG setup time before RAS low
1TLS
0
0
ns
34
tsu(SE)
SE setup time before RAS low (see Note 13)
tESR
0
0
ns
35
tsu(SFR)
DSF setup time before RAS low
0
0
ns
tsu(DCL)
Data setup time before C.\S low
tDSC
0
0
ns
tsu(DWL)
Data setup time before W low
tDSW
0
0
ns
tsu(rd)
Read command setup time
tRCS
0
0
ns
-5
ns
36
37
38
39
tsu(WCL)
Early write command setup time before CAS low
twcs
-5
40
tsu(WCH)
Write setup time before CAS high
tCWL
25
30
ns
41
tsu(WRH)
Write setup time before RAS high
tRWL
25
30
ns
lsu(SDS)
SD setup time before SC high
tSDS
3
3
ns
42
t Timing measurements are referenced to VIL max and VIH min.
NOTES:
9. All cycle times assume tt ~ 5 ns.
10. When the odd tap is used (tap address can be 0-511, and odd taps are 1,3,5, etc.), the cycle time for SC in the first serial data out
cycle needs to be 70 ns minimum.
11. In a read-modify-write cycle, td(CLWL) and tsu(WCH) must be observed, Depending on the user's transition times, this may require
additional CAS low time (tw(CL))'
12, In a read-modify-write cycle, Id(RLWL) and tsu(WRH) must be observed. Depending on the user's transition times, this may require
additional RAS low time (tw(RL))'
13. Register to memory (write) transfer cycles only,
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
9-215
SMJ44C251
262 144 BY 4·BIT MULTIPaRT VIDEO RAM
SGMS038E1-JANUARY 1991-REVISED FEBRUARY 1993
timing requirements over recommended ranges of supply voltage and operating temperature
(continued)t
ALT.
SYMBOL
PARAMETER
NO.
43
th(CLCA)
Column address hold time after CAS low
44
thfSFC)
DSF hold time after CAS low
45
th(RA)
Row address hold time after RAS low
46
thITRG)
47
46
'44C251-10
'44C251·12
MIN
MIN
MAX
MAX
UNIT
20
20
ns
20
20
ns
tRAH
15
15
ns
TRG hold time after RAS low
tTLH
15
15
ns
th(SE)
SE hold time after RAS low (see Note 13)
tREH
15
15
ns
th(RWM)
W hold time after RAS low
tRWH
15
15
ns
49
th(RDO)
DO hold time after RAS low (write mask operation)
tMH
15
15
ns
50
th{SFR)
DSF hold time after RAS low
15
15
ns
51
th(RLCA)
Column address hold time after RAS low (see Note 14)
tAR
45
45
ns
52
th(CLD)
Data hold time after CAS low
tDH
20
25
ns
53
th(RLD)
Data hold time after RAS low (see Note 14)
tDHR
45
50
ns
54
th(WLD)
Data hold time after W low
tDH
20
25
ns
55
th(CHrd)
Read hold time after CAS (see Note 15)
tRCH
0
0
ns
56
th{RHrd)
Read hold time after RAS (see Note 15)
tRRH
10
10
ns
57
th(CLW)
Write hold time after CAS low
tWCH
30
35
ns
58
thfRLw)
Write hold time after RAS low (see Note 14)
tWCR
50
55
ns
59
th(WLG)
TRG hold time after W low (see Note 20)
tOEH
25
30
ns
60
th(SDS)
SO hold time after SC high
tSDH
5
5
ns
61
th(SHSO)
SO hold time after SC high
tSOH
5
5
ns
62
Id(RLCH)
Delay time, RAS low to CAS high
tCSH
100
120
ns
63
Id(CHRL)
Delay time, CAS high to RAS low
tCRP
0
0
ns
64
Id(CLRH)
Delay time, CAS low to RAS high
tRSH
25
30
ns
65
IdlCLWL)
Delay time, CAS low to W low (see Notes 16 and 17)
tCWD
55
65
66
Id(RLCL)
Delay time, RAS low to CAS low (see Note 18)
tRCD
25
67
Id(CARH)
Delay time, column address to RAS high
tRAL
50
60
ns
68
IdfRLWL)
Delay time, RAS low to W low (see Note 16)
tRWD
130
155
ns
69
Id(CAWL)
Delay time, column address to W low (see Note 16)
tAWD
85
100
ns
70
Id(RLCHIR
Delay time, RAS low to CAS high (see Note 19)
tCHR
25
25
ns
71
Id(CLRL)R
Delay time, CAS low to RAS low (see Note 19)
tCSR
10
10
ns
72
Id(RHCL)R
Delay time, RAS high to CAS low (see Note 19)
tRPC
10
10
ns
73
Id(CLGH)
Delay time, CAS low to TRG high
tCTH
25
30
ns
74
Id(GHD)
Delay time, TRG high before data applied at DO
(see Note 16)
25
30
ns
75
Id(RLTH)
Delay time, RAS low to TRG high
90
95
ns
tCAH
tRTH
t Timing measurements are referenced to V,L max and V,H min.
NOTES: 13.
14.
15.
16.
17.
18.
19.
20.
Register to memory (write) transfer cycles only.
The minimum value is measured when td(RLCL) is set to td(RLCLl min as a reference.
Either th(RHrd) or th(CHrd) must be satisfied for a read cycle.
Read-modify-write operation only.
TRG must disable the output buffers prior to applying data to the DO pins.
Maximum value specified only to assure RAS access time.
CAS-before-RAS refresh operation only.
Output enable controlled write. Output remains in the high-impedance state for the entire cycle.
TEXAS ~
INSTRUMENTS
9-216
POST OFFICE BOX 1443· HOUSTON. TEXAS 77001
75
25
ns
90
ns
SMJ44C251
262144 BY 4·BIT MULTIPaRT VIDEO RAM
SGMS038B-JANUARY 1991-REVISED FEBRUARY 1993
timing requirements over recommended ranges of supply voltage and operating temperature
(concluded)t
NO.
ALT.
SYMBOL
PARAMETER
'44C251-10
MIN
'44C25.1-12
MAX
MIN
MAX
UNIT
76
Id(ALSH)
Delay time, AAS low to first SC high after TAG high
(see Note 21)
tASD
130
140
ns
77
td(CLSH)
Delay time, CAS low to first SC high after TAG high
(see Note 21)
tCSD
40
45
ns
78
Id{SCTA)
Delay time, SC high to TAG high (see Notes 21 and 22)
trSL
15
20
ns
79
td(THAH)
Delay time, TAG high to AAS high (see Note 21)
trAD
-10
-10
ns
80
td(SCAL)
Delay time, SC high to AAS low (see Notes 13 and 23)
tSAS
10
20
ns
81
td(SCSE)
Delay time, SC high to SE high in serial input mode
20
20
ns
82
td(AHSC)
Delay time, AAS high to SC high (see Note 13)
tSAD
25
30
ns
83
td(THAL)
Delay time, TAG high to AAS low (see Note 24)
trAP
tw(AH)
tw(AH)
ns
84
td(THSC)
Delay time, TAG high to SC high (see Note 24)
trSD
35
40
ns
85
td(SESC)
Delay time, SE low to SC high (see Note 25)
tsws
10
15
ns
86
td(AHMS)
Delay time, AAS high to last (most significant) rising edge
of SC before boundary switch during split read transfer
cycles
25
30
ns
87
Id(TPAL)
Delay time, first (TAP) rising edge of SC after boundary
switch to AAS low during split read transfer cycles
20
25
ns
trl(MA)
Aefresh time interval, memory
88
tAEF
8
8
ms
t Timmg measurements are referenced to VIL max and VIH min.
NOTES: 13. Aegister to memory (write) transfer cycles only.
21. Memory to register (read) transfer cycles only.
22. In a transfer read cycle, the state of SC when TAG rises is a Don't Care condition. However, to assure proper sequencing of the
internal clock circuitry, there can be no positive transitions of SC for at least 10 ns prior to when TAG goes high.
23. In a transfer write cycle, the state of SC when AAS falls is a Don't Care condition. However, to assure proper sequencing of the
internal clock circuitry, there can be no positive transitions of SC for at least 10 ns prior to when AAS goes low.
24. Memory to register (read) and register to memory (write) transfer cycles only.
25. Serial data·in cycles only.
26. System transition times (rise and fall) are to be a minimum of 3 ns and a maximum of 50 ns.
PARAMETER MEASUREMENT INFORMATION
1.31 V
218Q
Output
Pin
VSS
Figure 4. Load Circuit
TEXAS
~
INSIRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
9·217
SMJ44C251
262 144 BY 4·BIT MULTIPaRT VIDEO RAM
SGMS038B-JANUARY 1991-REVISED FEBRUARY 1993
PARAMETER MEASUREMENT INFORMATION
14
RAS
.1
tc(rd)
----.iN:
1
14
.1
tw(RL)
1-
I
IT ~ ~
1
JA
·1
ld(RLCH)
i-- tw(RH) ~ ~.- - - -
(
~td(CLRH)~
I
I J--ld(RLCL) ~
I I
j4- tw(CL) - : j
CAS
I
I
T-+i
I
I
tsu(RA) -.j
I+-
I
.'
~
t I
.
th(RA)
I
~th(RLCA)
SU(CA)
-'
~
~
I
,
AD-AS
I
tsu(SFR)
~ I.-JI I
I
.,
-----+i
I
~
I '---
I
I
I
II
II
Column
I
I
.,
th(CLCA)
•
_
~'
.~tW.(C.H)
'I
I
I
ld(CHRL)
I--- td(CLGH) -+---.!
I
th(SFR)
I
I
I
I
I..
I
I
I
I
I
I
I
I
·1
.
,
'-------
!+-+ ~Su(SFC) ,
I
'-+t-
II
y!
l.t
ROW.
I
H
N
T\
.
I
th(SFC)
.1
I'
II
~~~~~~~~~
DSF~II~I'!
.
~II~III I
I
I
I
I
~ /4-t tsu(TRG)
I
~ . Ith(TRG)
- +I -I
I
TRG'filj'
DQ
I
I ~\l
I tsu(rd) -.I I
1++
~!!
II
II
14- tW(T~G) +J I
1
I
w
I
I
II
iI!I'1'I~~~':'1r-----
i ~
I
II~
I ---+( II+- th(RHrd)
.
:"(C."" I'
tl
ro------
SMJ44C251
262144 BY 4·BIT MULTIPaRT VIDEO RAM
SGMS03BB-JANUARY 1991-REVISED FEBRUARY 1993
PARAMETER MEASUREMENT INFORMATION
14
4------------1c(W) -------------.{~I
_ _ _-...111 + 4 - - - - - - - - tw(RL)
_ _ _ _ _-'--_ _.-!~I
N
1 I
1 ...
tr --'
1
f.-
---+J..
1 1
AD-AS
I
!+-t----:- th(RLCA)
1
1
-.j
~
1
~:
:
I
0J.-
1
~
--.I
I.- tw(RH)
IT
1
I
td(CHRL) -----.j
1
:
~I
1
I 14 1
:
tw(CH)
---+l~1
~ ~'m" ~I.......
_____
)
y
tsu(SFR)
OSF
td(CLRH)
tw(CL)
j..
'+- td(RLCL)
+.I J-- th(RA)
1
~
td(RLCH)
1
~
+I
+i
H
tSU(SF
1
1
~ ::: '~I.......-----
tsu(TRG)
~
-.I
I 1 1
n '--
I I
I I
th(TRG) I I
I
I
I
I
I
I
"-
1
~II
-J 1~itsu(W1:4R)
1
1
11 1
1 1 14
th(RWM)
14-
1
1
1
1
~I
1
1
1
14
tsu(WCH)
tsu(WRH)
th(RLW)
th(CLW)
j+-ltsu(WCL)
~I
1
13
I
1
1
tsu(OQR) -,
i+-t
~
1
r-
tS~(OCL)
th(ROQ) ~
;
14 1
1 1 1
14 !. +
~
14-71
1
~
1
~I
tw(WL)
1
1+4- - -
1
th(RLO)
OQ~
1
~I
~I
~
~ Ii
I
W
n
14
14
1
1
th(CLO)
5
~I
~i
~
NOTE A: See 'Write Cycle State Table" for the logic state of "1 ", "2", "3", "4", and "5",
Figure 6. Early Write Cycle Timing
TEXAS ~
INSfRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
9-219
SMJ44C251
262 144 BY 4·BIT MULTIPaRT VIDEO RAM
SGMS038B-JANUARY 1991-REVISED FEBRUARY 1993
PARAMETER MEASUREMENT INFORMATION
4 ------------ tc(W) - - - - - - - - - - - - - + 1 · 1
1+
___--...1 ~14------'---- twIRL) ----------+1.1
1
N
1 I.,.~------- td(RLCH)
tr
~
!-
ViI.1
-~-----
'-
tw(RH)
~
~
1
~14----- td(CLRH) _ _ _-i-_4i~~1 1 tT
1
'+- td(RLCL) --+i*i4---- tw(CL) - - - - - + i L-+-...,;~;;..l.(C;;;.;H..;;.R;.;;L::....)_ _•
...,;1- - . . .
1 1
th (RA)
-1-+1 I+1
1
1
14
.1
1
ItSU(CA)+j
:*+'
--+i
~
~
:.-t+
I'
1
~~I.m\jc
~ ~
1
tw(CH)
t~J
1
---+1.1
(
1 14
.1
1
..,
I
1 1
1 1
tsu(WRH)
tsu(WCH)
tsu(DWL)
~ ~ th(RDQ)
·1
.
1th(RLW)
.1
"1
I
"
~IC'W)
iN
1
I !
I .1
1 1
th(RWM)
~ tsu(DQR)
14
14
1
~:: ~,""R)
W~,,3
1
I ~I
4
1
.~'-------
1
td(GHD)
-+I
.1 ~("CI
1
1 1 1
1
1
1
:,
tsu(TRG)
1 1
~
11 1
1
1 1 1
H
~
1
1
1
14
~
~~~1th(RLD)-
DQ~
tw(WL)
th(WLD) ----.I
~I
·1
~
5
NOTE A: See 'Write Cycle State Table" for the logic state of "1", "2", "3", "4", and "5".
Figure 7. Delayed Write Cycle Timing
TEXAS
~
INsrRUMENTS
9-220
1
1
~
.+". ~'-.-----!
1 tsu'(SFC)
DSF
1
!+t-- th(RLCA)
.tSU(RA)~ I.J
AD-AS
1 1
POST OFFICE BOX 1443· HOUSTON, TEXAS 77001
SMJ44C251
262144 BY 4·BIT MULTIPORTVIDEO RAM
SGMS038B-JANUARY 1991-REVISED FEBRUARY 1993
PARAMETER MEASUREMENT INFORMATION
write cycle state table
CYCLE
STATE
1
2
3
4
5
Valid
Data
Write mask load/use, write DOs to I/Os
L
L
L
Write
Mask
Write mask load/use, block write
L
H
L
Write
Mask
Addr
Mask
Use previous write mask, write DOs to I/Os
H
L
L
Don't
Care
Valid
Data
Use previous write mask, block write
H
H
L
Don't
Care
Addr
Mask
Load write mask on later of Wfall and CAS fall
H
L
H
Don't
Care
Write
Mask
Load color register on later of Wfall and CAS fall
H
H
H
Don't
Care
Color
Data
Write mask disabled, block write to aliI/Os
L
H
H
Don't
Care
Addr
Mask
Normal early or late write operation
L
L
H
Don't
Care
Valid
Data
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443 ••HOUSTON. TEXAS 77001
9-221
SMJ44C251
262 144 BY 4·BIT MULTIPaRT VIDEO RAM
SGMS038EhJANUARY 1991-REVISED FEBRUARY 1993
PARAMETER MEASUREMENT INFORMATION
I.
I I.
RAS
I
CAS
th(RA) I
I
Ao-AS
I
i. ~I
J
lfl:1·
tw(CL)
.Yi 1
I '
-+I
~ tsu(SFR)
I
I II+-
:+j.tsU(;t)
~ : ,: ~
th(TRG);
I·
~-+I U
TRG
Isu(TRG)
Isu(WMR)
I I.
-+l
i ~I
I.
I.--.!.- th(SFR) I
I I
! ~
I+-'-
~:
I
: :
f
tsU(rd)~
~
r-
th(SFC)
-.I
tw(RH)
~I ~I(CHRL)
: "-
-+I
)0000202§~}B*~~
I'
j4- tsu(WCH) ~
I
I
Id(CAWL)
-:
\ \)\1\ I:
I I
~ Ih(RWM) I
I
I I
I·
I.
Isu(DQR)
I
I Ih(RLW)
I· I
I. I
1 I+j.
~
4
la(R)
~ th(RDQ)
I
~
I~i
I
r
}@§§6
I;
oV~~~~
I
Ih(CLW)
-I
Isu(WRH)
~
~I
I
i4- Iw(WL) --+I
~ I
---+J r
-'1 --
2W<
I
~
~I
~
N
I.- Id(GHD)
ta(C)
i
Ih(WLG;:.
' I
I
I
Id(CLWL)
II
la/G) -.j 14-
Ih(WLD)
,,,'OW"
5
-J
I
I
~
I
-.j
14-- Idls(G)
NOTE A: See 'Write Cycle State Table" for the logic state of "1", "2", "3", "4", and "5", Same logic as delayed write cycle,
Figure 8, Read-Write/Read-Modify-Write Cycle Timing
TEXAS
~
INSTRUMENTS
9-222
I
~I
I I
I I
'tsu(SFC)
I
W~::3 WL~~~~
i
t~(R~WL):
DQ
~I I.
i :~tsU(R~~C'! ~~
~
~ ~ow ~ ~o,;mn~g*2g*~~
I
os,
I
~(CLRH)
~(RLCL) ~
I
I
:vr-L
I.
I + - - !
I
~I
twIRL)
--'N
I
I
~I
tc(rdW)
I
POST OFFICE BOX 1443· HOUSTON, TEXAS 77001
SMJ44C251
262 144 BY 4·BIT MULTIPORT VIDEO RAM
SGMS038B-JANUARY 1991-REVISED FEBRUARY 1993
PARAMETER MEASUREMENT INFORMATION
tw(RH)
-+I
, . 1 4 - - - - - - - - - - - - tw (RL) ----------------.t~1
RAS
I'l
I i,.
.. - - - td(RLCL)
I '
~
I
I
~ ld(CLRH) ~
I,.... tw(CL) --toi :- tw(CH)
i\ \l
td(RLfH)
~ th(RA) -+I
I
I
I
I
V:l\-
---~~I
tsu(RA)
:..
~
I
V:
I
~I
I..
--:!
14- td(CHRL) --toi
I:
\ \l
~I I"
i!
~I
I
tc(P)
th(CLCA)
I I
I
I
~1..~==~t:!!d(~C~A!!R~HL::~~~~b~~
th RLCA
Column
AG-A8
--+I
I
I
DSF
~
2Sol
I
I
I
w
m
U
I
~
I+- ta(C) I
I
I
I
I
I
I+- ta(CA) -+i
l-ta(G)~
I
I
I"
ta(R)*
I"
~:
wn
"\(f/
JTI
rf-
:I
Ith(RHrd) ~
th(CHrd)
I
I
II
~ta(CA)ti
ta(CP) t
GV
DQ
I
I
~I
II
I
I"
~
-+j
'<28
I4--+f- tdls(G)
~I
ldls(CH)
< ~~: J>-----
t Access time is ta(CP) or ta(CA) dependent.
*
Output may go from high-impedance state to an invalid data state prior to the specified access time.
NOTE A: A write cycle or a read-modify-write cycle can be mixed with the read cycles as long as the write and read-modify-write timing
specifications are not violated and the proper polarity of DSF is selected on the falling edge of RAS and CAS to select the desired write
mode (normal, block write, etc.).
Figure 9. Enhanced Page-Mode Read Cycle Timing
TEXAS
~
INsrRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
9-223
SMJ44C251
262144 BY 4·BIT MULTIPORTVIDEO RAM
SGMS03B~ANUARY
1991-REVISED FEBRUARY 1993
PARAMETER MEASUREMENT INFORMATION
~
~~
~
: 14
tcI(RLCH)
td(RLCL)
tw(CL)
\ 14
1
:
I I
-+iI II+t
I+-
tsu(RA)
tsu(CA)
th(RA) --.!
AO-AS
DSF
~::
!
14
I
i+t tsu(TRG)
-I
\
I
DO=>(
r-
~I tsu(WMR)
~~ th(RWM) -I
W=>(_3
tsu(DOR)
L
\!+- tw(CH) --+\
I+--
i
L
'~I
.
~I
I
1
\
I
_\
1
I
th(CLCA)
I - - f - I
\
1
,I
tsul (SFC)
\4
th(SFC)
I
I
I
I
\
I
I
11\
ItsU(W?H) ---+i
l+-,tW(WL)
--+I
I 1
I I
1
.1 th(SFC)
~~~
,I
tsu(WCH)
~
I
I
I I
I
\
I
\+--
:
I.- tsu(WRH)---.!
ml:i~~
tsu(DWL)t
14- th(RDO) --+\
14
\
4
~
r)
-\
tw(RH) j...-.I
td(GLRH) ~ 1
\
t;" t d (C7 R - l
1\\1. /
1
1
~::: ~
I
\
~\ \
~ tsu(SFC)
1
I
14
WIII
-+\
14
tC(P)
+, :'b[ : ~~:-: _
!
1
I I
--+1
_\
\4
I\\i.
Y
~ \
...,I
~ ~ R_ ~~LC;
~ I I tsu(SFR)
\
I
I
I I I.-- th(SFR) ~
~\
~
~:.-..:
I+- th(CLD)t---+\I
su(DCL)
1 14
th(WLD) t
"I
1 th(RLD)
"I
~
t
5
~
5
~
t Referenced to CAS or IN, whichever occurs last.
NOTES: A. See "Write Cycle State Table" for the logic state of "1 ", "2", "3", "4", and "5",
B. A read cycle or a read-modify-write cycle can be intermixed with write cycles, observing read and read-modify-write timing
specifications, TRG must remain high throughout the entire page-mode operation if the late write feature is used, to assure
page-mode cycle time. If the early write cycle timing is used, the state ofTRG is a Don't Care atterthe minimum period th(TRG) from
the falling edge of RAS.
Figure 10, Enhanced Page-Mode Write Cycle Timing
TEXAS ~
INSTRUMENTS
9-224
POST OFFICE BOX 1443· HOUSTON, TEXAS 77001
SMJ44C251
262144 BY 4·BIT MULTIPaRT VIDEO RAM
SGMS038B--JANUARY 1991-REVISED FEBRUARY 1993
PARAMETER MEASUREMENT INFORMATION
~14------------------------tw(R~------------------------~~1
RAS
-----N~-------------------------------------------------~{iJ.rr.i~
~I
: 14
1
ii'
1 i
7\
I
CAS
tsu(RA)
~
_
H- I+-
,~ J
XI
1tsu CA
~
th(RA) -,
( )~ th(CLCA)
~~"(":'~:,"m":
1
I I
th(SFR)
~
1
1
-41 '-
I
~tsu(SFCI
I I I
I i
14
t i l
su(WMR) M i l
1 I 1 I 1
th(RWM) ~ 1
1 I I I 1
4
: 14
I
I
I
I
I
4
I
w)<3yi
'--r""'I--:#
I
i+J t
14
1 su(DOR)
I+- th(RDO)
DO
I
I
14
I I
~
I+-- td(CLWL) ---I II
I
I
td(CAWL)
Itd(RLWL)
ta(CA) t
I
_--"""'l
I I
I I
I I
I
I
1~4---I~*"I- th(SFC)
I
1
tsu(SFC)
~I
1
:.-1-1 tsu(WCH)
I
I
I ~I
I I
I
I
I ta(R) ~
tsu(WCH)
I
tsu(DW~
I
I
I I
1 I
--l4------+I 1
1
I
I
I
tw(WL)
tsu(WRH) 14
\l
1
1
1
I
~I
~
"--_..u.::.I.~~~~
1
1 14
I ~I th(WLD)
+I i4I
I ! . - ta(CP) t ~
.r-~"~II~d""""
1!'\J~~~~~~~'?'\7'
I va
,v/'~rvvvvvvVVVV'A/'AA
o~
_____..;.14~1
I i
I I
I
Valid
I
I 14- ta(G) ~
/1
NJy
I
I
~ 14- ta(C)
1
1
1
I I
~I ~
I I
~I
I
~I
1 1
1 1
_:: ~"m~ ~
~:: 1,1 ~
~I I tsu(RD)
i4-
TRG
0 7\XI
!--t--- th(SFC)
I I
I I
~:~:I,I
1
r--!
td(RLCH)
tw(RH)
14
tc(RDWP)
1
~I
I+-- td(CLRH)
~I
I
td(RLCLI ~
1 ~ tw(CH\
td(CHRL) 14
~I
I
j4--tw(CL)~
I
I'
..
J.l.1I-----
!
o~
~14----+l- td(GHD)
....
1 _ _ _ _ _---,.
~~I______~I
I
i+---+I- Idls(G)
.,.1__________________
~
t Output may go from the high-impedance state to an invalid data state prior to the specified access time.
NOTES: A. See "Write Cycle State Table" for the logic state of "1 ", "2", "3", "4", and "5".
B. A read or a write cycle can be intermixed with read-modify-write cycles as long as the read and write timing specifications are not
violated.
Figure 11. Enhanced Page-Mode Read-Modify-Write Cycle Timing
TEXAS
~
IN5rRUMENTS
POST OFFICE BOX 1443· HOUSTON, TEXAS 77001
9-225
SMJ44C251
262 144 BY 4·BIT MULTIPaRT VIDEO RAM
SGMS038B-JANUARY 1991-REVISED FEBRUARY 1993
PARAMETER MEASUREMENT INFORMATION
114-~------tc(rd)
--------------...1'1
-------.1-1
I 14--- tw(RL) ------+I-I
RAS
1;7
I
-:
~
I
I
IT -+!
IT
CAS~I
II
tsu(RA) -:14-4--+I-
_~
i
tsu(SFR)
-
-: I
I
I
I I
I
1
hi I14-~---r-1-
I~
r
th(RA)
~,,---RO_W
IIi+~---~I
ii
I
th(SFR)
~
th(TRG)
1
w
DQ
Figure 12. RAS-Only Refresh Timing
TEXAS ~
INSTRUMENTS
9·226
!-- tw(RH) ---l
l-
I
i~
DSF~~~~~~~~~~~~I
tsu(TRG)
~~
I
~
~I~-__t-I-
I
TL
POST OFFICE BOX 1443· HOUSTON, TEXAS 77001
SMJ44C251
262144 BY 4·BIT MULTIPaRT VIDEO RAM
SGMS038B-JANUARY 1991-REVISED FEBRUARY 1993
PARAMETER MEASUREMENT INFORMATION
~
;1
--~ I..
td(CLRL)R
~~
N
~ tw(RH) ~
~I
:4
------~~
lcI(RHCl)R
:
14
twiRL) ---~~I
~
I
y~-----
I
~! ~ td(RlCH)R ~
V
Vi
DSF
DQ
HI-Z - - - - - - - - - - - - - - -
Figure 13. CAS-Before-RAS Refresh
TEXAS ~
INSIRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
9-227
SMJ44C251
262 144 BY 4·BIT MULTIPaRT VIDEO RAM
SGMS038~ANUARY
1991-REVISED FEBRUARY 1993
PARAMETER MEASUREMENT INFORMATION
I~~---------- tc(rd)
------------+1.1
I
i+I
RAS
I I~
It
tcI(RHC~~
.1
N:
~I
td(ClRl)R
\l
~I
:11
i+1
I II~
I
.11
w(Cl)
Y Nil
~I
th(SFR)
I
--t-+i
tw(CH)
~ t
I~
tsu(SFC)"?I
J+-+J-I
I
I
;--
tcI(RlCH)R
I
I I
I
I I
I
hi
I-'c -- :
"'SU(SOS)
~
1
II
I 1
1 I
th(SOS)
SOQ
1
I
~i
ld(SCRL) --14114--"'~1
i
1
1
~
I I
-:-fl.
I
I
I
~~~~~*~n~g~~ri_~~
~
I I
sc
IV
I
~1 14
OQ
r
~
tsu(CA)
Column
'i\
---..I ' - - - I
tw(RH)
~B:~gH~
th(TRG)
TAG~ii
1~
tw(CL)
th(RLCA)'
~,
1
1
~ th(CLCA)
~ow
::'
_I I
,.
tsu(TRG)
14
-.j
I
Vi~
r--
I
1
,
ld(RLCH)
---!o14"'--+1~1 l+- th(RA)
tsu(RA)
--+I
I,
I I
I 14
i 1
~
~,
twIRL)
a
0rr:
tsu(SE)
---+j
1
~
I 1
_
I.
I ~
I.
14- th(SE) ~
~
"'--- t
ro- d(SESC)
1
3
~
:
0rr:
a
"-
th(SOS)
~
---...
-,
NOTES: A. Random mode Q outputs remain in the high-impedance state forthe entire data register to memory transfer cycle. This cycle is used
to transfer data from the data register to the memory array. Every one of the 512 locations in each data register is written into the
corresponding 512 columns of the selected row. Data in the data register may proceed from a serial shift-in or from a parallel load
from one of the memory array rows. The above diagram assumes that the device is in the serial write mode (i.e., SD is enabled by
a previous write mode control cycle, thus allowing data to be shifted-in).
B. See "Register Transfer Function Table" for logic state of "1" and "3".
C. Successive transfer writes can be performed without serial clocks for applications requiring fast memory array clears.
Figure 17. Data Register to Memory Timing, Serial Input Enabled
TEXAS
~
INsrRUMENTS
POST OFFICE BOX 1443· HOUSTON, TEXAS 77001
9-231
SMJ44C251
262144 BY 4·BIT MULTIPORT VIDEO RAM
SGMS038B-JANUARY 1991-REVISED FEBRUARY 1993
PARAMETER MEASUREMENT INFORMATION
register transfer function table
RAS FALL
FUNCTION
TRG
W
DSF
(1)
SE
(3)
Register to memory transfer
L
L
X
L
Register to memory transfer, alternate transfer write
L
L
H
X
Pseudo-transfer soa control, serial input enabled
L
L
L
H
Memory to register transfer
L
H
L
Split-register transfer
L
H
H
X
X
TEXAS ~
INSTRUMENTS
9-232
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
SMJ44C251
262144 BY 4·BIT MULTIPaRT VIDEO RAM
SGMS038B-JANUARY 1991-REVISED FEBRUARY 1993
PARAMETER MEASUREMENT INFORMATION
14
I
_ _ _ _ _......:1
1:-
14-- tw{CL)
N
-+I
th (RA)
th{RLCA)
4
II:!
AO-AB
~
tsu{SFR)
14
1
DSF
I
~ow
..
I
I
I
,Y
I
I
I
i+-fI
tsu (CAl
~I
Column
~
~g~nJ£!~
-+I
I
I
I 1+ th{TRG) -+I
I
I
tsu{TRG) -1+14-..
~1
I
I
iI4~~
~
... th{SFR)
I I
~!i
I
--+I
i\
~ tw{RH) ----+I ' - - - 1~
I
I ~I J
I
td(RLCH;
-j414-~~1 I
I
I
Vi
I
: I
tsu{RA)
I
:
I I
I [4
I I
I
I
~I
tw{RL)
I.------ td{RLCL) ~
N
RAS
~I
tc(TW)
14
I
I
I
~H:~B*~
I
I+- td{THRL)
~ii~
I II
-W
--joIIi4f----+!~1
14
tw{SCH)
---I:
--+I ~ tsu{SDS)
,
I
th(SDS)
SDQ
~
~g~~R*!~
I
II
td{SCRL)
th{RWM)
I
~:
DQ
sc
~I
~~~SU~~M~R~-r1114-~~:1
I
I
HI-Z ------+1---------td{RHSC)
~I
--+014t------.l~1 114-4--_~+-1 tw{SCH)
iii
\\\\\\\\\\\\\\\\\\\\\\\\\\\\\ 1:
~
~ ~
i
~
tw(SCL)
~
14
tsu(SDS)
~I 1
I Ii+'--*~I-th(SDS)
~ D~ts
td{SCSE)
I
-+I
D:;:a
I
~ I+--
I
I+- td(SESC) ---I
I
Figure 18. Alternate Data Register to Memory Timing
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
9-233
SMJ44C251
262144 BY 4·BIT MULTIPORT VIDEO RAM
SGMS038B-JANUARY 1991-REVISED FEBRUARY 1993
PARAMETER MEASUREMENT INFORMATION
14
!e(TRO)
I
I 14
I
----.ii\. I
r--
-I
tw(RL)
-----.j'
!
\ '', y ' ,
,~
N
I'
I:
'4
-l+-----+! ~
i
~
AO-A8
th(RLCA)
th(RA)
' I
20<
Row
tsu(SFR)
tsu(TRG)
~
-I
1
w
~
,
.,,
!
\
' - ta(SQ)
,
th(SHSQ)
14
Old Data
SOQ
--+I
1
, 14
-I ,
X
1
I
~
I
I
1 14
'I
d(RLTH),
-I
:
-r-------+iI ,'4
_--Jl:
:
~~~~g~~~
1
,
t
14-- tw(SCH) ~
I
I,
I
14
SC
Column
1
','
m2W
:V
I
I
lm$_2~m;S:cE~
,'..
,
1
~th(CLCA)
th(SFR) 1
~,
tsu(WMR)
,
-I'
tsU(CA)I!
1
: '
~I
_I
-t---1
tW(CL)
1
~ I!
OSF
-+i 14
-+I
:1;
, '4
-t-----+l ,
I,
ld(RLC'H)
1 :
tsu(RA)
,,'\'-._--
ld(RLCL)
1 14
1
,
I
I
-,
1
th(RWM) ,
I
ld(THRL)
-I
I.-----J-I td(THRH)
1
i/'~-----------------
}!I
I
I 1
~*~I~~
14
I
_I 14
I
I+- td(CLSH)
I td(RLSH)
ld(SCTR)
I
-, td(THSC)
-----+I
_I
1:'4
\
1
-I
I+-
tw(SCL)
Old Data
X
th(SHSQ)
'4
\~--J;I
!e(SC)
ta(SQ)
Old Data
--+I
---~-,
_, ,
X"""'--N-e-w-o-a-ta---
H
SE
L -------------------------------------------------------------------NOTES: A. Random mode (a outputs) remain in the high-impedance state for the entire memory to data register transfer cycle. The memory
to data register transfer cycle is used to load the data registers in parallel from the memory array. The 512 locations in each data
register are written into from the 512 corresponding columns of the selected row. The data that is transferred into the data registers
may be either shifted out or transferred back into another row.
B. Once data is transferred into the data registers, the SAM is in the serial read mode (Le., the SO is enabled), thus allowing data to
be shifted out of the registers. Also, the first bit to be read from the data register after TRG has gone high must be activated by a
positive transition of SC.
Figure 19. Memory to Data Register Transfer Timing
TEXAS ."
INSTRUMENTS
9-234
POST OFFICE BOX 1443' HOUSTON. TEXAS 77001
SMJ44C251
262 144 BY 4·BIT MULTIPORT VIDEO RAM
SGMS038B-JANUARY 1991-REVISED FEBRUARY 1993
PARAMETER MEASUREMENT INFORMATION
14
14
1
~ td(RLCL)
1
14
---~N
1
----I
:
I~:
=~~C
AD-AS
I
:
1
I
1
1
1
Y
N
1
1 -
-
~I ~su(CA)
14
I 14
"'~'G) ~ I
~ ii
~I
td(RLTH)
.'(SFR)
W!$/!IIa
+--: :
td(TPRL)
QSF
r+: td(RHMS)
I
1
14
~I
~I
~
'---.I.,~
~I
14
"----'......---'
~
14
ta(QSF)
I
Bit 255
1
~
1
: "dB
1
I ~I
---JI
tw(SCL)
1
1
1
or 511
ta(SQ)
1
1
th(SHSQ)
-B-lt-2-55-o-r-5-11-.,M....
i ___T_A_P_M_ _ _,jr~'-
SOQ
:
1
tc(SC)
~
M~'256
1
~
1
:
~I
I.
1
ld(RLSH)
OIdMSB
I
-./ i
I
14
14
SC
~
-I
14
1
:
tw(SCH)
:
i '0§2§§2§§§@§§2§2~\Jo~~~f~~
0@W
w
1
",CL"" ~J#"- """'4 ---
-+-.l II+- th(SFR)
OSF
:
I
i--+th(CLCA)
Row
.
tW(CL)
!\----
-I!
---+I
I
1
I
I:::
I
1
~ TAPN+~SB ~~~n~gH~
i I
tsu(RA)
1
11
:.--
II
1
1
ld(RLCH)
I
r.I
~I
twIRL)
I I
th(RA)
~I
1
tc(TRO)
1
1
_______-Jrr(
Bit 255 or 511
E
H
SE
L ------------------------------------
NOTE A: There must be a minimum of two SC clocks cycle between any two split-register reload cycles, and a minimum of one SC clock cycle
between a transfer read cycle and a split-register cycle.
Figure 20. Split-Register Mode Read Transfer Timing
TEXAS ~
IN8rRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
9-235
SMJ44C251
262144 BY 4·BIT MULTIPaRT VIDEO RAM
SGMS038B-JANUARY 1991-REVISEO FEBRUARY 1993
RAS
" ...._ _.,,/
I
1
'I---l--...
~,
). I " - - - - /
1. 1
I
AD DR
I
I--!..,..,
I .J
1\
I
,---"
I
I
I
I
1\
I
~~~~
I
I
I
I
I
I
I
:x::x:x....-------r-:---'I(~
: (1
: >00<
: !l
: >00<
:
ROW! TAP1 (L)
I
R°v:!8T~~1 (H)
RO~8T~~2(L)
I
---+----'l'1---l--...
~,
,.
I
"---/
I .1
\...J
~
I
DSF
Only)
I
I
I
I
I
I
I BIT TAP1(H)1
1255
ROWII
- - - - - -...: _--1',"1-;---<.1-""'\\
I
QSF
/\
I
I
I
RO~8T~~2(H)
II I'Ii
I
I
I
: 1'1
: /\\..._---4
I
I
1
\...J
I
-----..IV'}A-s~~~
TAPl,.&L)
RO I
QSF
(RevH
I
-----+--\I,~';
I
sc
I
\
_
Normal Transfer Read
I
I
','1
I SC Cycles
I From TAP1
I
I
I
I
I
I Split-Register
I
I
I
I
~~~s~~li'b~~~~a
I BIT TAP2(L) I
1511
ROW, I
:::J:
:\~ :
I ' I
I
I,
/
I ',r---'
I SC Cycles
16~ ~~ ~~tlf
Register
I (QSF High
(QSF Low Indicating IlndlCating
Split-Register Mode I Switch To
Low Half)
High Half)
I
I
I
I
I
I
I
I
I
I
I
Split-Register
JI:~s~e,;.:r;~ad
Half
I
I
I
I
I
I
I"~ I
I
1...""'1- - - - - - ;
I SC Cycles
I Repeat High/Low
I
~f;~ ~1!1f
I (QSF Low
I Indicating
I Switch To
Low Half)
I
I
6';
I ~:~u~c;,ac~
I
I
I
I
I
NOTES: A. In the split-register mode, data can be transferred from different rows to the low and high halves of the data register.
B. When enabling or disabling the split-register mode, ta(QSF) is measured from RAS low in the transfer cycle.
Figure 21. Split-Register Operating Sequence
application notes
1.
In order to achieve proper split-register operation, a normal read transfer followed by a minimum of one
serial clock cycle should be performed before the first split-register transfer cycle. This is necessary to
initialize the data register and the starting tap location. Serial access can then begin after the normal transfer
cycle.
2.
A split-register transfer into the inactive half is not allowed until td(TPRL) is met. td(TPRL) is the minimum
delay time between the rising edge of the serial clock (SC) of the previously loaded tap pOint and the falling
edge of RAS of the split-register transfer cycle into the inactive half.
3.
After td(TPRL) is met, the split-register transfer into the inactive half must also satisfy the td(RHMS) condition.
td(RHMS) is the minimum delay time between the rising edge of RAS of the split-register transfer cycle into
the inactive half and the rising edge of the last serial clock (SC 255 or 511) of the active half.
TEXAS
~
INsrRUMENTS
9-236
POST OFFICE BOX 1443' HOUSTON. TEXAS 77001
SMJ44C251
262144 BY 4·BIT MULTIPaRT VIDEO RAM
SGMS038B-.JANUARY 1991-REVISED FEBRUARY 1993
PARAMETER MEASUREMENT INFORMATION
~
I.--- tw(SCL)
~:
SC
~~q
-----./111.--
----1 I+---- tw(SCL) ----+I
Vi
I _ I
II
'\
\
14-- tsu(SOS) ---.! .!
i
.......,
SDO ~
~
tw(SCH)
"'"Dm;
i+-1cI(SESC)
I
L_
... t
....--------rr h(SOS)
I-- tsu(SOS) --+l
I
t+- th(SDS)
~
.L
~
"""D...
-I
\{~_________________________________________________
SE
Figure 22. Serial Data-In Timing
The serial data-in cycle (SO) is used to input serial data into the data registers. Before data can be written into
the data registers via SO, the device must be put into the write mode by performing a write mode control or
transfer write cycle. Transfer write cycles occurring between the write mode control cycle and the subsequent
writing of data will not take the device out of the write mode. However, a transfer read cycle during that time will
take the device out of the write mode and put it into the read mode, thus disabling the input of data. Data will
be written starting at the location specified by the input address loaded on the previous transfer cycle.
While accessing data in the serial data registers, the state of TRG is a Don't Care as long as TRG is held high
when RAS goes low to prevent data transfers between memory and data registers.
I.
I
j4-- tw(SCL) ~
SE
I
I
~ th(SHSO) --I
I
I--
~ tw(SCL) -----./
~
I+-- ta(SO) ~
<
--..:
14-- tw(SCH) ----.! I
Y:
SC\
SOO
~I
tc(sq
)(
lA
~
I
/4--- ta(SO) ~
>C
ta(SE)
~~:_____________________________________________________________
NOTE A: When the odd tap is used (tap addresses can be 0-511, and odd taps are 1,3,5 ... etc.), the cycle time for SC in the first serial data out
cycle needs to be 70 ns minimum.
Figure 23. Serial Data-Out Timing
The serial data-out (SQ) cycle is used to read data out of the data registers. Before data can be read via SQ,
the device must be put into the read mode by performing a transfer read cycle. Transfer write cycles occurring
between the transfer read cycle and the subsequent shifting out of data will not take the device out of the read
mode. But a write mode control cycle at that time will take the device out of the read mode and put it in the write
mode, thus not allowing the reading of data.
While accessing data in the serial data registers, the state of TRG is a Don't Care as long as TRG is held high
when RAS goes low to prevent data transfers between memory and data registers.
TEXAS
~
IN8rRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
9·237
SMJ44C251
262 144 BY4·BIT MULTIPORT VIDEO RAM
SGMS038B-JANUARY 1991-REVISED FEBRUARY 1993
TEXAS ~
INSTRUMENTS
9-238
POST OFFICE BOX 1443' HOUSTON, TEXAS 77001
SMJ55160
262 144 BY 16·BIT
MULTIPORT VIDEO RAM
SGMS052-DECEMBER 1992
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
HKC PACKAGEt
(TOP VIEW)
Military Operating Temperature Range
- 55°C to 125°C
MIL-STD-883, Class B
vcc
TAG
VSS
soo
000
SOl
001
Vcc
S02
002
S03
003
vss
S04
004
S05
DOS
Vcc
S06
006
S07
007
VSS
CASL
WE
RAS
A8
A7
A6
AS
DRAM: 262144 Words x 16 Bits
SAM: 256 Words x 16 Bits
Dual Port Accessibility - Simultaneous and
Asynchronous Access From the DRAM and
SAM Ports
Data Transfer Function From the DRAM to
the Serial Data Register
(4 x 4) x 4 Block Write Feature for Fast Area
Fill Operations. As Many as Four Memory
Address Locations Written Per Cycle From
the 16-Bit On-Chip Color Register
Write-Per-Bit Feature for Selective Write to
Each RAM 1/0. Two Write-Per-Bit Modes to
Simplify System Design
Byte Write Control (CASL, CASU) Provides
Flexibility
Enhanced Page Mode Operation for Faster
Access
CAS-Before-RAS and Hidden Refresh
Modes
Long Refresh Period: Every 8 ms (Max)
Up to 33-MHz Uninterrupted Serial Data
Streams
256 Selectable Serial Register Starting
Locations
SE Controlled Register Status Signal
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
A4
vcc
SC
63
SE
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
vss
SOlS
OQ15
SOH
DOH
Vcc
SQ13
0013
S012
0012
vss
SOll
0011
SOlO
0010
Vcc
S09
DO.
S08
008
VSS
DSF
NC/GND
CASU
OSF
AO
Al
A2
A3
VSS
AO-AS
CASL, CASU
DOO-D015
SE
RAS
SC
SOO-S015
TRG
WE
DSF
OSF
a:
~
=>
vcc
VSS
NC/GND
Address Inputs
Column-Address Strobe/Byte Selects
DRAM Data I/O, Write Mask Data
Serial Enable
Row-Address Strobe
Serial Clock
Serial Data Output
Output Enable, Transfer Select
DRAM Write Enable Selects
Special Function Select
Special Function Output
5-V Supply (TYP)
Ground
No Connect/Ground (Important: Not Connected
Internally to V SS)
ACCESS TIME
ROW ENABLE
ta(R)
(MAX)
ACCESS TIME
SERIAL DATA
ta(SO)
(MAX)
DRAM
CYCLETIME
tc(rd W)
(MIN)
DRAM
PAGEMODE
tc(P)
(MIN)
SERIAL
CYCLETIME
tc(SC)
(MIN)
SO ns
25 ns
150 ns
50 ns
30 ns
EPIC is a trademark of Texas Instruments Incorporated,
PRODUCT PREVIEW Information concern. productlln the formative or
de.lgn ph... of development Characteristic data and other
apatlflc,tlonl Ire d.,lgn goala. TIXlllnltrumentl rlaervea the right to
chang. or dl,continue th... productl without nolic•.
>
W
0
PIN NOMENCLATURE
Designed to Work With the IndustryLeading Texas Instruments Graphics
Family
Ceramic Package:
- O.5-mm Fine Pitch Brazed Flatpack With
Non-Conductive Tie-Bar
- Pin Grid Array
Performance:
~
W
0..
t Package is shown for pinout reference only,
Split Serial-Data Register for Simplified
Realtime Register Reload
3-State Serial Outputs Allow Easy
Multiplexing of Video Data Streams
AlllnputslOutputs and Clocks TTL
Compatible
Texas Instruments EPIC'· CMOS Process
SMJ55160
10
11
12
13
14
15
16
64
TEXAS
~
Copyright © 1992, Texas Instruments Incorporated
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
9-239
C
0
a:
0..
SMJ55160
262 144 BY 16·BIT
MULTIPaRT VIDEO RAM
SGMS052-DECEMBER 1992
TEXAS ~
INSTRUMENTS
9-240
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
SMJ55165
262 144 BY 16-BIT
MULTIPaRT VIDEO RAM
SGMS051-DECEMBER 1992
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Military Operating Temperature Range
- 55°C to 125°C
MIL-STD-883, Class B
DRAM: 262 144 Words x 16 Bits
SAM: 256 Words x 16 Bits
Dual Port Accessibility - Simultaneous and
Asynchronous Access From the DRAM and
SAM Ports
Data Transfer Function From the DRAM to
the Serial Data Register
(4 x 4) x 4 Block Write Feature for Fast Area
Fill Operations. As Many as Four Memory
Address Locations Written Per Cycle From
the 16-Bit On-Chip Color Register
Wrlte-Per-Bit Feature for Selective Write to
Each RAM I/O. Two Write-Per-Bit Modes to
Simplify System Design
Byte Write Control (WEL, WEU) Provides
Flexibility
Enhanced Page Mode Operation for Faster
Access
CAS-Before-RAS .and Hidden Refresh
Modes
Long Refresh Period: Every 8 ms (Max)
Up to 33-MHz Uninterrupted Serial Data
Streams
256 Selectable Serial Register Starting
Locations
SE Controlled Register Status Signal
Split Serial-Data Register for Simplified
Realtime Register Reload
3-State Serial Outputs Allow Easy
Multiplexing of Video Data Streams
All Inputs/Outputs and Clocks TTL
Compatible
Texas Instruments EPIC'· CMOS Process
Designed to Work With the IndustryLeading Texas Instruments Graphics
Family
Ceramic Package:
- O.5-mm Fine Pitch Brazed Flatpack With
Non-Conductive Tie-Bar
- Pin Grid Array
HKCPACKAGE
(TOP VIEW)
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
Vcc
TAG
Vss
SOO
DOO
S01
D01
Vcc
SQ2
D02
S03
D03
Vss
S04
D04
S05
D05
10
11
12
13
14
15
16
17
Vcc
S06
D06
S07
D07
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
Vss
WEL
WEU
AAS
A8
A7
A6
AS
A4
Vcc
SC
SE
Vss
SOlS
D015
S014
D014
Vcc
S013
D013
S012
DQ12
Vss
S011
D011
S010
DOlO
Vcc
S09
D09
SOB
D08
Vss
DSF
NC/GND
CAS
OSF
AO
A1
A2
A3
VSS
ta~
(M
SMJ55165
SO
ns
ACCESS TIME
SERIAL DATA
ta(SQ)
(MAX)
o
::J
PIN NOMENCLATURE
25
DRAM
CYCLETIME
te(rd W)
(MIN)
Address Inputs
Column-Address Strobe/Byte Selects
DRAM Data I/O, Write Mask Data
Serial Enable
Row-Address Strobe
Serial Clock
Serial Data Output
Output Enable, Transfer Select
DRAM Write Enable Selects
Special Function Select
Special Function Output
5-V Supply (TYP)
Ground
No Connect/Ground (Important: Not Connected
Internally to VSS)
DRAM
PAGE MODE
t e(':)
(MI)
150 ns
ns
50
ns
SERIAL
CYCLETIME
te(SC)
(MIN)
30
ns
EPIC is a trademark of Texas Instruments Incorporated.
PRODUCT PREVIEW Inform.Uon concerns productlln the formative or
dtllgn phi.. of development Char.cleri.tlc data and oth,r
:~~::!':;!::'I~~~::'~~~:: !:~c:~~~c~"rv.. the rlg"t to
TEXAS
~
Copyright © 1992, Texas Instruments Incorporated
INsrRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
a:
I-
Performance:
ACCESSTIME
ROW ENABLE
w
>
w
c..
t Package is shown for pinout reference only.
AO-AS
CAS
DOO-D015
SE
RAS
SC
SOO-S015
TRG
WEU, WEL
DSF
OSF
VCC
VSS
NC/GND
3:
9-241
C
oa:
c..
SMJ55165
262 144 BY 16·BIT
MULTIPaRT VIDEO RAM
SGMS051~DECEMBER
1992
TEXAS ~
INSTRUMENTS
9-242
POST OFFICE BOX 1443· HOUSTON, TEXAS 77001
SMJ27C128
131 072·BIT UV ERASABLE PROGRAMMABLE READ·ONLY MEMORY
SGMS006C-AUGUST 1986-REVISED FEBRUARY 1993
•
Military Operating Temperature
Range . .. - 55°C to 125°C
J PACKAGET
(TOP VIEW)
•
Processed to MIL·STD-883, Class B
•
•
Organization ... 16K x 8
"
Pin Compatible V/ith EXisting 64K and 128K
EPROMs
•
•
Vpp
Single 5-V Power Supply
Max Access/Min Cycle Times
±
5%
Vee
±
•
28
PGM
26
A5
24
A4
A3
A2
A1
23
22
G
21
A10
20
E
19
07
06
05
04
03
18
150 ns
01
02
17
'27C128-15
'27C128-17
170 ns
GND
15
'27C128-20
200 ns
120 ns
'27C128-25
250 ns
'27C128-30
300 ns
VCC
27
A13
AS
A9
A11
10%
'27C128-120
•
1
25
All Inputs/Outputs Fully TTL Compatible
Vee
•
•
A12
A7
16
t Package is shown for pinout reference only.
HVCMOS Technology
PIN NOMENCLATURE
3-State Output Buffer
AO--A13
E
G
Low Power Dissipation
- Active ... 138 mWWorst Case
- Standby . .. 1.7 mW Worst Case
(CMOS-Input Levels)
GND
PGM
00--07
400-mV Minimum DC Noise Immunity With
Standard TTL Loads
VCC
Vpp
Address Inputs
Chip Enable/Power Down
Output Enable
Ground
Program
Outputs
5-V Power Supply
12-13-V Power Supply
description
The SMJ27C128series are 131 072-bit, ultraviolet-light erasable, electrically programmable read-only memory.
These devices are fabricated using HVCMOS technology for high speed and simple interface with MOS and
bipolar circuits. All inputs (including program data inputs) can be driven by Series 54 TTL circuits without the
use of external pullup resistors. The data outputs are three-state for connecting multiple devices to a common
bus. The SMJ27C128 is pin compatible with 28-pin 128K ROMs and EPROMs. They are offered in a 600-mil
dual-in-line ceramic package (J suffix) rated for operation from -55°C to 125°C.
Since these EPROMs operate from a single 5-V supply (in the read mode), they are ideal for use in
microprocessor-based systems. One other (12.5 V) supply is needed for programming, but all programming
signals are TTL level. These devices are programmable by either Fast or SNAP! Pulse programming algorithms.
The Fast programming algorithm uses a Vpp of 12.5 Vand a Vee of6 V for a nominal programming time of two
minutes. The SNAP! Pulse programming algorithm uses a Vpp of 13.0 V and a Vee of 6.5 V for a nominal
programming time of two seconds. For programming outside the system, existing EPROM programmers can
be used. Locations may be programmed singly, in blocks, or at random.
operation
The seven modes of operation for the SMJ27C128 are listed in the following table. The read mode requires a
single 5-V supply. All inputs are TTL level exceptforVpp during programming (12.5 Vfor Fast, or 13 V for SNAP!
Pulse) and 12 V on A9 for signature mode.
PRODUCTION DATA Information I, current al of publication date.
Products conform to specification. per the terms of Texas Inatrumenta
standard warranty. Production proc ..sing doe. nol nece••• rlly Include
te.tlng of ,II parameter•.
TEXAS ~
Copyright © 1993, Texas Instruments Incorporated
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
9-243
SMJ27C128
131 072-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY
SGMS006C--AUGUST 1986--REVISED FEBRUARY 1993
FUNCTION
(PINS)
MODE
READ
OUTPUT
DISABLE
STANDBY
PROGRAMMING
VERIFY
PROGRAM
INHIBIT
SIGNATURE
MODE
E
(20)
VIL
VIL
VIH
VIL
VIL
VIH
VIL
G
(22)
VIL
VIH
xt
VIH
VIL
X
VIL
PGM
(27)
VIH
VIH
X
VIL
VIH
X
VIH
Vpp
(1)
Vee
Vee
Vee
Vpp
Vpp
Vpp
Vee
Vee
(28)
Vee
Vee
Vee
Vee
Vee
Vee
Vee
A9
(24)
X
X
X
X
X
X
VH:I:
VH:I:
X
X
X
X
X
X
VIL
VIH
Data Out
HI-Z
HI-Z
Data In
Data Out
HI-Z
MFG
DEVICE
97
83
AO
(10)
CODE
QO-Q7
(11-13,15--19)
t X can be VIL or VIH.
:j: VH = 12 V ± 0.5 V.
read/output disable
When the outputs of two or more SMJ27C128s are connected in parallel on the same bus, the output of any
particular device in the circuit can be read with no interference from the competing outputs of the other devices.
To read the output ofthe selected SMJ27C128, a low-level signal is applied to the E and G pins. All other devices
in the circuit should have their outputs disabled by applying a high-level signal to one of these pins. Output data
is accessed at pins 00 through 07.
latchup immunity
Latchup immunity on the SMJ27C128 is a minimum of 250 mA on all inputs and outputs. This feature provides
latchup immunity beyond any potential transients at the P.C. board level when the devices are interfaced to
industry-standard TTL or MOS logic devices. Input/output layout approach controls latchup without
compromising performance or packing density.
For more information see application report SMLA001; "Design Considerations; Latchup Immunity of the
HVCMOS EPROM Family," available through TI Field Sales Offices.
powerdown
Active Icc supply current can be reduced from 25 mA to 500 IlA (TTL-level inputs) or 300 IlA (CMOS-level inputs)
by applying a high input signal to the E pin. In this mode all outputs are in the high-impedance state.
erasure
Before programming, the SMJ27C128 is erased by exposing the chip through the transparent lid to a high
intensity ultraviolet light (wavelength 2537 A). EPROM erasure before programming is necessary to assure
that all bits are in the logic 1 (high) state. Logic lows are programmed into the desired locations. A
programmed logic low can be erased only by ultraviolet light. The recommended minimum exposure dose
(UV intensity x exposure time) is 15 Wos/cm 2. A typical 12 mW/cm 2, filterless UV lamp will erase the device
in 21 minutes. The lamp should be located about 2.5 cm above the chip during erasure. After erasure,
all bits are in the high state. It should be noted that normal ambient light contains the correct wavelength
for erasure. Therefore, when using the SMJ27C128, the window should be covered with an opaque label.
TEXAS
~
INSTRUMENTS
9-244
POST OFFICE BOX 1443
0
HOUSTON. TEXAS 77001
SMJ27C128
131 072-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY
SGMS006C-AUGUST 1986-REVISED FEBRUARY 1993
SNAPI Pulse programming
The 128K EPROM can be programmed using the TI SNAP! Pulse programming algorithm illustrated by the
flowchart in Figure 1, which can reduce programming time to a nominal of two seconds. Actual programming
time will vary as a function of the programmer used.
Data is presented in parallel (eight bits) on pins 00 to 07. Once addresses and data are stable, PGM is pulsed.
The SNAP! Pulse programming algorithm uses initial pulses of 100 itS followed by a byte verification to
determine when the addressed byte has been successfully programmed. Up to 1a (ten) 1OO-ltS pulses per byte
are provided before a failure is recognized.
The programming mode is achieved when Vpp = 13 V, Vee = 6.5 V, G = VIH, and E = VIL. More than
one device can be programmed when the devices are connected in parallel. Locations can be
programmed in any order. When the SNAP! Pulse programming routine is complete, all bits are verified
with Vee = Vpp = 5 V.
fast programming
The 128K EPROM can be programmed using the Fast programming algorithm illustrated by the flowchart
in Figure 2. During Fast programming, data is presented in parallel (eight bits) on pins 00 through 07. Data
is presented in parallel (eight bits) on pins 00 to 07. Once addresses and data are stable, PGM is pulsed.
The programming mode is achieved when Vpp = 12.5 V, Vee = 6 V, G = VIH, PGM = VIL, and E = VIL.
More than one SMJ27C128 can be programmed when the devices are connected in parallel. Locations can
be programmed in any order.
Programming uses two types of programming pulses: Prime and Final. The length of the Prime pulse is 1
millisecond; this pulse is applied X times. After each Prime pulse, the byte being programmed is verified.
If the correct data is read, the Final programming pulse is applied; if correct data is not read, an
additional 1 millisecond pulse is applied up to a maximum X of 25. The Final programming pulse is 3X
long. This sequence of programming and verification is performed at Vee = 6 V and Vpp = 12.5 V. When
the full Fast programming routine is complete, all bits are verified with Vee =Vpp = 5 V (see Figure 2).
program inhibit
Programming may be inhibited by maintaining a high level input on the E or PGM pin.
program verify
Programmed bits may be verified with Vpp = 12.5 V when G = VIL, E = VIL, and PGM = VIH.
signature mode
The signature mode provides access to a binary code identifying the manufacturer and type. This mode
is activated when A9 (pin 24) is forced to 12 V ± 0.5 V. Two identifier bytes are accessed by AD (pin 10);
i.e., AD = VIL accesses the manufacturer code, which is output on 00-07; AD = VIH accesses the device
code, which is output on 00-07. All other addresses must be held at VIL. Each byte possesses odd parity
on bit 07. The manufacturer code for these devices is 97, and the device code is 83.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
9-245
SMJ27C128
131 072·BIT UV ERASABLE PROGRAMMABLE READ·ONLY MEMORY
-,
SGMS006G-AUGUST 1986-REVISED FEBRUARY 1993
Program
Mode
Increment Address
Interactive
Mode
No
Yes
Device Failed
Final
Verification
J
Figure 1. SNAP! Pulse Programming Flowchart
TEXAS ~
INSTRUMENTS
9-246
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
SMJ27C128
131 072·BIT UV ERASABLE PROGRAMMABLE READ·ONLY MEMORY
SGMS006G-AUGUST 1986-REVISED FEBRUARY 1993
Yes
Increment
Address
Figure 2. FAST Programming Flowchart
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
9·247
SMJ27C128
131 072·BIT UV ERASABLE PROGRAMMABLE READ·ONLY MEMORY
SGMS006C--AUGUST 1986--REVISED FEBRUARY 1993
logic symbol t
AO
A1
A2
A3
A4
AS
A6
A7
A8
A9
A10
A11
A12
A13
E
G
10
9
8
7
6
5
4
3
25
24
21
23
2
26
20
22
EPROM
0
16384x8
0
A 16383
A"l
A"l
A"l
A"l
A"l
A"l
A"l
A"l
11
12
13
15
16
17
18
19
01
02
03
04
05
06
07
08
13
[PWR OWN)
....
&
I
EN
tThis symbol is in accordance with ANSI/IEEE Std 91-1984 and lEe Publication 617-12.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)*
Supply voltage range, Vee (see Note 1) ................................ ,............. -0.6 V to 7 V
Supply voltage range, Vpp (see Note 1) ............................................. -0.6 V to 14 V
Input voltage range (see Note 1), All inputs except A9 ................................ -0.6 V to 6.5 V
A9 .............................................. -0.6 Vto 13.5 V
Output voltage range (see Note 1) ............................................. -0.6 V to Vee + 1 V
Minimum operating free-air temperature ................................................... -55° C
Maximum operating case temperature ..................................................... 125° C
Storage temperature range ....................................................... -65°C to 150°C
*Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maxi mum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to GND.
TEXAS
~
IN5rRUMENTS
9-248
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
SMJ27C128
131 072·BIT UV ERASABLE PROGRAMMABLE READ·ONLY MEMORY
SGMS006C-AUGUST 1986-REVISED FEBRUARY 1993
recommended operating conditions
'27C128-15
'27C128-17
'27C128-20
'27C128-25
'27C128-30
'27C128-120
MIN
Vee
Supply voltage
Supply voltage
MAX
MIN
NOM
MAX
Read mode (see Note 2)
4.75
5
5.25
4.5
5
5.5
V
Fast programming algorithm
5.75
6
6.25
5.75
6
6.25
V
SNAPI Pulse programming algorithm
6.25
6.50
6.75
6.25
6.5
6.75
V
Vee+ 0.6
Vee- 0.6
Vee+ 0.6
V
Read mode (see Note 3)
Vpp
NOM
UNIT
Vee- 0.6
12
12.5
13
12
12.5
13
V
12.75
13
13.25
12.75
13
13.25
V
2
Vee+ 1
2
Vee + 1
V
Vee- 0.2
Vee+ 1
Vee- 0 .2
Vee+ 1
V
TIL
-0.5
0.8
-0.5
0.8
V
CMOS
-0.5
0.2
-0.5
0.2
Fast programming algorithm
SNAPI Pulse programming algorithm
VIH
High-level input voltage
Vil
low-level input voltage
TA
Operating free-air temperature
Te
Operating case temperature
TIL
CMOS
-55
V
-55
°e
125
°e
125
NOTES: 2. Vee must be applied before oralthe same time as Vpp and removed after or althe same time as Vpp. The device must not be inserted
into or removed from the board when Vpp or Vee is applied.
3. Vpp can be connected to Vee directly (except in the program mode). Vee supply current in this case would be ICC + Ipp.
electrical characteristics over full ranges of operating conditions
PARAMETER
TEST CONDITIONS
MIN
TYpt
MAX
UNIT
VOH
High-level output voltage
IOH = -400 rnA
VOL
low-level output voltage
10l = 2.1 rnA
0.4
V
II
Input current (leakage)
VI = 0 to 5.5 V
±1
~A
10
Output current (leakage)
Vo=OtoVee
±1
~A
IpP1
Vpp supply current
Vpp = Vee = 5.5 V
IpP2
Vpp supply current; (during program pulse)
Vpp=13V
lee1
Vee supply current (standby)
lee2
2.4
V
35
100
~A
50
rnA
ITIL-input level
Vee = 5.5 V, E = VIH
500
~A
I CMOS-input level
Vee = 5.5 V, E = Vee
300
~A
10
25
rnA
Vee = 5.5 V, E = Vll,
tcycl e = minimum cycle time,
outputs open
Vee supply current (active)
t TYPical values are at TA = 25°C and nominal voltages.
; This parameter has been characterized at 25°C and is not tested.
capacltance§
TYpt
MAX
ei
Input capacitance
VI = 0, f = 1 MHz
6
10
pF
Co
Output capacitance
Vo = 0, f = 1 MHz
8
t4
pF
PARAMETER
TEST CONDITIONS
MIN
UNIT
t TYPical values are at TA = 25°C and nominal voltages.
§ Capacitance measurements are made on sample basis only.
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443· HOUSTON. TEXAS 77001
9-249
SMJ27C128
131 072·BIT UV ERASABLE PROGRAMMABLE READ·ONLY MEMORY
SGMS006C-AUGUST 19BB-REVISED FEBRUARY 1993
switching characteristics overfull ranges of recommended operating conditions (see Notes 4 and 5)
'27C128-120
TEST CONDITIONS
(SEE NOTES 4 AND 5)
PARAMETER
MIN
MAX
'27C128-15
MIN
'27C128-17
MAX
MIN
MAX
UNIT
talA)
Access time from address
120
150
170
ns
tatE)
Access time from chip enable
120
150
170
ns
ten (G)
Output enable time from G
50
70
70
ns
50
ns
tdis
Output disable time from G or E,
whichever occurs firstt
tv(A)
Output data valid time after change of
address, E, or G, whichever occurs first t
See Figure 3
0
50
0
TEST CONDITIONS
(SEE NOTES 4 AND 5)
PARAMETER
0
50
0
0
0
ns
'27C128-20
'27C128-25
'27C128-30
MIN
MIN
MIN
MAX
MAX
MAX
UNIT
talA)
Access time from address
200
250
300
ns
tatE)
Access time from chip enable
200
250
300
ns
!en(G)
Output enable time from G
75
100
120
ns
105
ns
tdis
Output disable time from Gar E,
whichever occurs firstt
tv(A)
Output data valid time after change of
address, E, or G, whichever occurs firstt
See Figure 3
0
0
60
0
60
0
0
0
ns
t Value calculated from 0.5 V delta to measured level. This parameter is only sampled and not production tested.
recommended timing requirements for programming: Vee = 6 V and Vpp
Vee = 6.5 and Vpp =13 V (SNAP! Pulse), TA = 25°C (see Note 4)
Fast programming algorithm
= 12.5 V
(Fast) or
MIN
NOM
MAX
UNIT
0.95
1
1.05
ms
95
100
105
f.ls
78.75
ms
tw(IPGM)
Initial program pulse duration
tw(FPGM}
Final pulse duration
tsu(A)
Address setup time
2
tsu(G)
G setup time
2
tdis
Output disable time from G
0
tenG
Output enable time from G
tsu(D)
Data setup time
2
f.ls
tsu(VPP)
VPP setup time
2
f.lS
tsu(VCC}
VCcsetuptime
2
f.lS
theA}
Address hold time
0
f.lS
thCD)
Data hold time
2
f.ls
tsu(E)
E setup time
2
f.lS
NOTES:
SNAPI Pulse programming algorithm
Fast programming only
. .
..
f.ls
f.lS
130
ns
150
ns
4. For ali sWitching characteristics and timing measurements Input pulse levels are 0.4 V to 2.4 V. Timing measurements are made at
2.0 V for logic high and 0.8 V for logic low for both inputs and outputs.
5. Common test conditions apply for tdis except during programming.
TEXAS
~
INSTRUMENTS
9·250
2.85
POST OFFICE BOX 1443· HOUSTON. TEXAS 77001
SMJ27C128
131 072·BIT UV ERASABLE PROGRAMMABLE READ·ONLY MEMORY
SGMS006C-AUGUST 19S6-REVISED FEBRUARY 1993
PARAMETER MEASUREMENT INFORMATION
2.08V
Output
Under Test
~
T
RL=800Q
CL=100pF
Figure 3. Output Load Circuit
AC testing input/output wave forms
2.4
v'----"v
O.:~X
'___...J!\ 0.: ~
0.4 V-
____
A.C. testing inputs are driven at 2.4 V for logic high and 0.4 V for logic low. Timing measurements are made at
2 V for logic high and 0.8 V for logic low for both inputs and outputs.
AO-A13 _ _ _...JX1I'o1_ _ _ _ _ _
A_d_dr_es_s_es_V_a_lid_ _ _ _ _
I
1
:
:
1
\
yit"'i-------- VIH
------------"'1 I
VIL
11'0
1
J+-- talE) ~
I I
I
I
it"'1-------- VIH
\~----+:------~}1~
I
i'f- ten (G) ~
141111---- talA)
~I
Q0-07 - - - HI-Z
~::
I
I
----+1-----,.
:
. .-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_
~xr
-----«\...lo.«..lo....l<...J..«~<_ _
tv(A)
I
1111
~I
tdis
~
I
)'--L>-'-'»~)}-
Ou_tPu_t
va_lid_--",2;.L.)
HI-Z -
~::
Figure 4. Read Cycle Timing
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
9-251
SMJ27C128
131 072-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY
SGMS006C-AUGUST 19B6--REVISED FEBRUARY 1993
PARAMETER MEASUREMENT INFORMATION
AO-A13
QO-Q7
Vpp
{
I
~!II
~ tSU(VPP)
I
VCC
--.I~
1
I
l~,
\
tw(FPGM)
I
I
I
I
I
I
I
I
I
I
I
II
:
tSU(VCC):
1
I
tsu(E)
1 l+-
th(O)
I
I I
I I
I
I
________,~
tw(IPGM)
:
i
:
I
I
I
I
~~I~I----~I----~I--~~__-------------
t---{
I~
.1
:~
.:
!~
.I!
1 I
1
I
tSU(G)!
I
:~~----t."1 ten(G):
'{
/r-----
Figure 5. Program Cycle Timing
TEXAS ~
INsrRUMENTS
9-252
POST OFFICE BOX 1443· HOUSTON, TEXAS 77001
Vpp
VCC
VCC
VCC
SMJ27C256
262144·BIT UV ERASABLE PROGRAMMABLE READ·ONLY MEMORY
SGMS005D-MAY 1986-REVISED FEBRUARY 1993
•
•
Military Operating Temperature
Range . .. - 55°C to 125°C
J PACKAGET
(TOP VIEW)
MIL·STD·883C Class B
High-Reliabillity Processing
Vpp
A12
A7
A6
A5
•
Organization ... 32K x 8
•
Single 5-V Power Supply
•
Pin Compatible With Existing 128K and
256KEPROMs
•
•
'27C256-20
'27C256-25
200 ns
A3
A2
A1
AO
00
01
02
250 ns
GND
'27C256-30
300 ns
All Inputs/Outputs Fully TTL Compatible
Max Access/Min Cycle Times
'27C256-15
'27C256-17
150 ns
170 ns
•
HVCMOS Technology
•
3-State Output Buffers
1
VCC
A14
A13
AS
A9
A11
G
A10
E
07
06
05
04
03
t Package is shown for pinout reference only.
PIN NOMENCLATURE
•
400 mV Minimum DC Noise Immunity With
Standard TTL Loads
•
Low Power Dissipation
- Active ... 138 mWWorst Case
- Standby ... 1.7 mW Worst Case
(CMOS Input Levels)
AO-A14
E
G
GND
00-07
vCC
vpp
Address Inputs
Chip Enable/Power Down
Output Enable
Ground
Outputs
5-V Power Supply
Output Enable
description
The SMJ27C256 series are 262 144-bit, ultraviolet-light erasable, electrically programmable read-only
memories. These devices are fabricated using HVCMOS technology for high speed and simple interface with
MOS and bipolar circuits. All inputs (including program data inputs) can be driven by Series 54 TTL circuits
without the use of external pullup resistors, and each output can drive one Series 54 TTL circuit without external
resistors. The data outputs are three-state for connecting multiple devices to a common bus. The SMJ27C256
is pin compatible with 28-pin 256K ROMs and EPROMs. They are offered in a 600 mil dual-in-line ceramic
package (J suffix) rated for operation from -55°C to 125°C.
Since these EPROMs operate from a Single 5-V supply (in the read mode), they are ideal for use in
microprocessor-based systems. One other 12-13 V supply is needed for programming, but all programming
signals are TTL level. These devices are programmable by either Fast or SNAP! Pulse programming algorithms.
The Fast programming algorithm uses a Vpp of 12.5 Vand a Vee of 6 Vfor a nominal programming time of two
minutes. The SNAP! Pulse programming algorithm uses a Vpp of 13 V and a Vee of 6.5 V for a nominal
programming time of four seconds. For programming outside the system, existing EPROM programmers can
be used. Locations may be programmed singly, in blocks, or at random.
operation
The seven modes of operation forthe SMJ27C256 are listed in the following table. Read mode requires a single
5-V supply. All inputs are TTLievel exceptforVpp during programming (12.5 Vfor Fast, or 13 V for SNAP! Pulse)
and 12 V on A9 for signature mode.
PRODUCTION DATA Information I, current .1 of publication date.
Products conform to 'peelfleatlona per the terma of Texas Instruments
atandard warranty. Productlon procelling doea not necessarily Inctude
tilling of ,II paramet,r•.
TEXAS ~
Copyright © 1993, Texas Instruments Incorporated
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
9-253
SMJ27C256
262144-81T UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY
SGMS005D--MAY 1986-REVISED FEBRUARY 1993
FUNCTION
(PINS)
MODE
READ
OUTPUT
DISABLE
STANDBY
PROGRAMMING
VERIFY
PROGRAM
INHIBIT
SIGNATURE
MODE
E
(20)
VIL
VIL
VIH
VIL
VIH
VIH
VIL
G
(22)
VIL
VIH
xt
VIH
VIL
X
VIL
Vpp
(1)
Vee
Vee
Vee
Vpp
Vpp
Vpp
Vee
Vee
(28)
Vee
Vee
Vee
Vee
Vee
Vee
Vee
A9
(24)
X
X
X
X
X
X
VH*
AO
(10)
X
X
X
X
X
X
VIL
VH*
VIH
CODE
00-07
(11-13,15-19)
Data Out
HI-Z
HI-Z
Data Out
Data In
HI-Z
MFG
DEVICE
97
04
t X can be VIL or VIH.
*VH = 12V±0.5V.
read/output disable
When the outputs of two or more SMJ27C256s are connected in parallel on the same bus, the output of
any particular device in the circuit can be read with no interference from the competing outputs of the other
devices. To read the output of the selected SMJ27C256, a low-level signal is applied to the E and G pins.
All other devices in the circuit should have their outputs disabled by applying a high-level signal to one of
these pins. Output data is accessed at pins 00 through 07.
latchup immunity
Latchup immunity on the SMJ27C256 is a minimum of 250 mA on all inputs and outputs. This feature provides
latchup immunity beyond any potential transients at the P.C. board level when the EPROM is interfaced to
industry standard TTL or MOS logic devices. Input/output layout approach controls latchup without
compromising performance or packing density.
For more information see application report SMLA001; "Design Considerations; Latchup Immunity of the
HVCMOS EPROM Family."
powerdown
Active ICC supply current can be reduced from 25 mA to 500!-tA (TTL-level inputs) or 300!-tA (CMOS-level inputs)
by applying a high TTL signal to the E pin. In this mode all outputs are in the high-impedance state.
erasure
Before programming, the SMJ27C256 is erased by exposing the chip through the transparent lid to a high
intensity ultraviolet light (wavelength 2537 A). EPROM erasure before programming is necessary to assure
that all bits are in the logic 1 (high) state. Logic Os (lows) are programmed into the desired locations. A
programmed logic low can be erased only by ultraviolet light.The recommended minimum exposure dose
(UV intensity x exposure time) is 15 W·s/cm 2. A typical 12 mW/cm 2, filterless UV lamp will erase the device
in 21 minutes. The lamp should be located about 2.5 cm above the chip during erasure. After erasure, all
bits are in the high state. It should be noted that normal ambient light contains the correct wavelength for
erasure. Therefore, when using the SMJ27C256, the window should be covered with an opaque label.
TEXAS
~
INSTRUMENTS
9-254
POST OFFICE BOX 1443· HOUSTON. TEXAS 77001
SMJ27C256
262144·BIT UV ERASABLE PROGRAMMABLE READ·ONLY MEMORY
SGMS005D-MAY 198&-REVISED FEBRUARY 1993
SNAPI Pulse programming
The 256K EPROM can be programmed using the TI SNAP! Pulse programming algorithm as illustrated by the
flowchart in Figure 1, which can reduce programming time to a nominal of 4 seconds. Actual programming time
will vary as a function of the programmer used.
Data is presented in parallel (eight bits) on pins 00 to 07. Once addresses and data are stable, E is pulsed.
The SNAPI Pulse programming algorithm uses initial pulses of 100 microseconds (1)5) followed by a byte
verification to determine when the addressed byte has been successfully programmed. Up to 10 (ten) 100-f-ls
pulses per byte are provided before a failure is recognized.
The programming mode is achieved when Vpp = 13 V, Vee = 6.5 V, G = VIH and E = VIL. More than
one device can be programmed when the devices are connected in parallel. Locations can be
programmed in any order. When the SNAP! Pulse programming routine is complete, all bits are verified
with Vee = Vpp = 5 V.
fast programming
The 256K EPROM can be programmed using the Fast programming algorithm illustrated by the flowchart in
Figure 2. During Fast programming data is presented in parallel (eight bits) on pins 00 to 07. Once addresses
and data are stable, E is pulsed. The programming mode is achieved whenVpp = 12.5 V, Vee =6 V, G =VIH
and E = VIL. More than one SMJ27C256 can be programmed when the devices are connected in parallel.
Locations can be programmed in any order.
Fast programming uses two types of programming pulses: Prime and Final. The length of the Prime pulse
is 1 millisecond; this pulse is applied X times. After each Prime pulse, the byte being programmed is
verified. If the correct data is read, the Final programming pulse is applied; if correct data is not read, an
additional 1 millisecond pulse is applied up to a maximum X of 25. The Final programming pulse is 3X
long. This sequence of programming and verification is performed at Vee = 6 V and Vpp = 12.5 V. When
the full Fast programming routine is complete, all bits are verified with Vee = Vpp = 5 V (see Figure 2).
program Inhibit
Programming may be inhibited by maintaining a high level input on the E pin.
program verify
Programmed bits may be verified with Vpp
= 12.5 V when G =VIL, and E =VIH.
signature mode
The signature mode provides access to a binary code identifying the manufacturer and type. This mode is
activated when A9 (pin 24) is forced to 12 V ± 0.5 V. Two identifier bytes are accessed by AD (pin 10); i.e.,
AD = VIL accesses the manufacturer code, which is output on 00--07; AD = VIH accesses the device code, which
is output on 00--07. All other addresses must be held at VIL' Each byte possesses odd parity on bit 07. The
manufacturer code for these devices is 97, and the device code is 04.
TEXAS ~
INSfRUMENTS
POST OFfiCE BOX 1443 • HOUSTON. TEXAS 77001
9-255
SMJ27C256
262 144·BIT UV ERASABLE PROGRAMMABLE READ·ONLY MEMORY
SGMS005D-MAY 19S5-REVISED FEBRUARY 1993
T
Program
Mode
Increment Address
Increment
Address
No
Final
Verification
~
Figure 1. SNAP! Pulse Programming Flowchart
TEXAS ~
INSTRUMENTS
9·256
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
SMJ27C256
262144·BIT UV ERASABLE PROGRAMMABLE READ·ONLY MEMORY
SGMS005D-MAY 1986-REVISED FEBRUARY 1993
Yes
Device
Failed
Increment
Address
Figure 2. FAST Programming Flowchart
TEXAS ~
INsrRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
9-257
SMJ27C256
262144·BIT UV ERASABLE PROGRAMMABLE READ·ONLY MEMORY
SGMS005O-MAY 1986-REVISED FEBRUARY 1993
logic symbol t
AD
Al
A2
A3
A4
AS
A6
A7
A8
A9
A1D
All
A12
A13
A14
E
10
9
8
7
6
5
4
3
25
24
21
23
2
26
27
20
22
0
EPROM 32 768 x 8
0
A 32767
T
r--r---
A'il
A'il
A'il
A'il
A'il
A'il
A'il
A'il
11
12
13
15
16
17
18
19
QO
Ql
Q2
Q3
Q4
QS
Q6
Q7
14
[PWRDWNI
~
EN
t This symbol is in accordance with ANSlflEEE Std 91-1984 and lEG Publication 617-12.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted);
Supply voltage range, Vee (see Note 1) .............................................. -0.6 V to 7 V
Supply voltage range, Vpp (see Note 1) ............................................. -0.6 V to 14 V
Input voltage range (see Note 1), All inputs except A9 ................................ -0.6 V to 6.5 V
A9 ............................................... -0.6 V to 13.5 V
Output voltage range (see Note 1) ............................................. -0.6 V to Vee + 1 V
Minimum operating free-air temperature .................................................... -55°C
Maximum operating case temperature ...................................................... 125°C
Storage temperature range ....................................................... -65°C to 150°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to GND.
TEXAS
~
INSTRUMENTS
9-258
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
SMJ27C256
262144-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY
SGMSOOSD-MAY 1986-REVISED FEBRUARY 1993
recommended operating conditions
PARAMETER
MIN
Read mode (see Note 2)
Vee
Supply Voltage
NOM
MAX
5
5.5
V
Fast programming algorithm
5.75
6
6.25
V
SNAPI Pulse programming algorithm
6.25
6.5
6.75
V
Vee- O.6
V
V
Read mode (see Note 3)
Vpp
Supply Voltage
12
12.5
t3
12.75
13
13.25
V
2
Vee+ 1
V
Vee- 0.2
Vee+ 0.2
V
-0.5
0.8
V
GND-0.2
GND+0.2
Fast programming aigorithm
SNAPI Pulse programming algorithm
VIH
UNIT
4.5
TTL
High-level input voltage (see Note 4)
VIL
Low-level input voltage (see Note 4)
TA
Operating free-air temperature
Te
Operating case temperature
eMOS
TTL
eMOS
-55
V
°e
125
°e
MAX
UNIT
electrical characteristics over full ranges of operating conditions
PARAMETER
TEST CONDITIONS
MIN
TYpt
VOH
High-level output voltage (see Note 4)
10H = -400 IlA
VOL
Low-level output voltage (see Note 4)
10L = 2.1 mA
0.4
V
II
Input current (leakage) (see Note 4)
VI = 0 to 5.5 V
±1
IlA
10
Output current (leakage)
Vo=OtoVee
IpPl
VPP supply current
VPP = Vee = 5.5 V
IpP2
Vpp supply current* (during program pulse) (see Note 4)
I TTL-input level
lee 1
Vee supply curent (standby)
lee2
Vee supply current (active) (see Note 4)
lOS
Output short circuit current (see Note 5)
I eMOS-input level
Vpp = 13V
2.4
V
35
±1
J.tA
100
IlA
50
mA
Vee = 5.5 V, E = VIH
500
Vee=5.5V, E=Vee
300
Vee = 5.5 V, E = VIL,
tcycle = minimum cycle time,
outputs open
10
IlA
25
mA
100
mA
t TYPical values are at TA = 25°e and nominal voltages.
* This parameter has been characterized at 25°e and is not tested.
NOTES: 2. Vee must be applied before or althe same time as Vpp and removed after or althe same time as Vpp. The device must not be inserted
into or removed from the board when Vpp or Vee is applied.
3. Vpp can be connected to Vee directly (except in the program mode). Vee supply current in this case would be lee + Ipp.
4. Valid during programming mode also.
5. Vpp may be one diode drop below Vee. It may be connected to Vee. Also, Vee must be applied simultaneously or before Vpp and
be removed simultaneously or after Vpp.
TEXAS
~
INsrRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
9-259
SMJ27C256
262 144·BIT UV ERASABLE PROGRAMMABLE READ·ONLY MEMORY
SGMS005D-MAY 19S5-REVISED FEBRUARY 1993
capacitance over recommended
temperature, f = 1 MHzt
ranges
PARAMETER
of
supply
voltage
and
TEST CONDITIONS
operating
TYP*
MAX
=1 MHz
S
10
pF
=0, f = 1 MHz
10
14
pF
Ci
Input capacitance
VI = 0, f
Co
Output capacitance
Vo
MIN
free-air
UNIT
t Capacitance measurements are made on a sample basis only.
*Typical values are at TA = 25°C and nominal voltages.
switching characteristics overfull ranges of recommended operating conditions (see Notes 6 and 7)
TEST CONDITIONS
(SEE NOTES 6 AND 7)
PARAMETER
'27C256-15
MIN
MAX
'27C256-17
MIN
MAX
UNIT
talA)
Access time from address
150
170
t~
Access time from chip enable
150
170
ns
len (G)
Output enable time from G
70
70
ns
tdis
Output disable time from G or E, whichever occurs first §
0
55
ns
tv(A)
Output data valid time after change of address, E, or G,
whichever occurs first §
0
See Figure 3
TEST CONDITIONS
(SEE NOTES 6 AND 7)
PARAMETER
MAX
MIN
0
0
'27C25S-25
'27C25S-20
MIN
55
ns
'27C256-30
MAX
MIN
ns
MAX
UNIT
talA)
Access time from address
200
250
300
ns
talE)
Access time from chip enable
200
250
300
ns
tenlG}
Output enable time from G
75
100
120
ns
1ctis
Output disable time from G or E,
whichever occurs first §
105
ns
tv(A)
Output data valid time after change of
address, E, or G, whichever occurs first §
See Figure 3
0
0
so
0
0
60
0
0
ns
§ Value calculated from 0.5 V delta to measured output level. This parameter IS only sampled and not 100% tested. Timing measurements are made
at 2.0 V for logic high and O.B V for logic low for both inputs and outputs.
NOTES: S. For all switching characteristics and timing measurements, input pulse levels are 0.4 V to 2.4 V.
7. Common test conditions apply to tdis except during programming.
TEXAS ~
INSTRUMENTS
9-260
POST OFFICE BOX 1443· HOUSTON, TEXAS 77001
SMJ27C256
262144·BIT UV ERASABLE PROGRAMMABLE READ·ONLY MEMORY
SGMS005[}-MAY 1986-REVISED FEBRUARY 1993
recommended timing requirements for programming: Vcc = 6 V and Vpp
VCC = 6.5 and Vpp =13 (SNAPI Pulse), TA = 25°C (see Note 6)
Fast programming algorithm
= 12.5 V
(Fast) or
MIN
NOM
MAX
UNIT
0.95
1
1.05
ms
95
100
105
tw(IPGM)
Initial program pulse duration
tw(FPGM)
Final pulse duration
tsu(A)
Address setup time
2
tsu(G)
G setup time
2
'dis
Output disable time from G
0
Ien(G)
Output enable time from G
tsui[)J
Data setup time
2
~s
tsu(VPP)
Vpp setup time
2
~s
~s
SNAP! Pulse programming algorithm
Fast programming only
2.85
78.75
~s
ms
fls
~s
130
ns
150
ns
tsu(VCC)
VCC setup time
2
theA)
Address hold time
0
~s
th(D)
Data hold time
2
~s
tsu(E)
E setup time
2
~s
NOTE 6: For all switching characteristics and timing measurements, the input pulse levels are 0.4 V to 2.4 V.
PARAMETER MEASUREMENT INFORMATION
2.08V
Output
Under Test
----1
T
RL
= 800 Q
CL= 100pF
Figure 3. AC Testing Output Load Circuit
AC testing input/output wave forms
2.4
V~----'X
0.4
v-
_ _ _---J
O.:~:X____
~ o.:~
A.C. testing inputs are driven at 2.4 V for logic high and 0.4 V for logic low. Timing measurements are made at
2 V for logic high and 0.8 V for logic low for both inputs and outputs.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
9-261
SMJ27C256
262144·BIT UV ERASABLE PROGRAMMABLE READ·ONLY MEMORY
SGMS005D-MAY 19S6-REVISED FEBRUARY 1993
PARAMETER MEASUREMENT INFORMATION
AO-A14
J
I
104
\
E
I
I
I
J;
I
I
14-- talE) ------.I
I
I
I
I I
14- ten(G)
QO-Q7
VIL
Y
VIH
VIL
[4---- tdls ----1>1
-'1
I..
tv(A)
~~~
HI-Z
VIH
I
I
\
G
VIL
I
I
.1
talA)
VIH
X
Addresses Valid
.1
Output Valid
I
»»»)}-
HI-Z -
:::
Figure 4. Read Cycle Timing
1.
04
.
1-
AO-A14
-
-
-
Program
~I"---~'--I.~I
Verify
---.t
I
I
I
:
~~-------------Ad-d-re-s-s-St~ab-Ie------------~~~~
__A_~_~_r~_ss___
f+- th(A
~ tsu(A)
~
QO-Q7
I
~tsu(D)
VPP
T
------f
Vee
I
I
I
I
I
I
I
vppt
i:
:
:
Vee
I
I
I
Vee t
i
:
Vee
~ th(D)
I
~ tsu(VPP)
I
~~tsu(Vee)
I
I
I
I
~ tsu(E)
I
--.t
I
--------~~
I
I
I I
I
~r~----~----~:--~-----------------
~ ~!--1.~I-+-1
-1<141---+1.1
tw(FPGM) --;..1..1-----.;.1
tw(IPGM)
I
..
I
.1
I
tsu(G)
: I..
I
II
I
ten(G)1
I
)
\{~------.I'
t 12.S-V VPP and S-V Vee for Fast programming, 13-V Vpp and 6.S-V Vee for SNAP! Pulse programming.
Figure 5. Program Cycle Timing
TEXAS
~
INSTRUMENTS
9-262
POST OFFICE BOX 1443· HOUSTON, TEXAS 77001
SMJ27C512
524 288·BIT UV ERASABLE PROGRAMMABLE READ·ONLY MEMORY
SGMS019B-SEPTEMBER 1987-REVISED FEBRUARY 1993
•
Military Operating Temperature
Range ... - 55°C to 125°C
•
•
•
•
Processed to MIL-STD-883C, Class B
•
•
•
•
(TOP VIEW)
A15
A12
Organization '" 64K x 8
Vee
A14
A13
AS
A9
All
GNpp
AID
Single 5-V Power Supply
Pin Compatible With EXisting 512K
EPROMs
A5
All Inputs/Outputs Fully TTL Compatible
A3
A2
AI
AD
QD
Ql
Q2
A4
Max Access/Min Cycle Times
'27C512-20
'27C512-25
'27C51 2-30
•
•
•
J PACKAGEt
200 ns
250 ns
300 ns
HVCMOS Technology
E
07
06
Q5
Q4
Q3
GND
3-State Output Buffers
Latchup Immunity of 250 mA on All Input
and Output Lines
t Package is shown for pinout reference only.
PIN NOMENCLATURE
400-mV Minimum DC Noise Immunity With
Standard TTL Loads
AO-AI5
E
Low Power Dissipation
- Active ... 275 mW (Max)
- Standby ... 1.9 mW (Max)
(CMOS Input Levels)
GND
00-07
Vee
GNpp
GND
Address Inputs
Chip Enable/Power Down
Ground
Outputs
5-V Power Supply
Output Enable
Ground
description
The SMJ27C512 series are 524288-bit, ultraviolet-light erasable, electrically programmable read-only
memories. These devices are fabricated using HVCMOS technology for high speed and simple interface with
MaS and bipolar circuits. All inputs (including program data inputs) can be driven by Series 54 TTL circuits
without the use of external pullup resistors, and each output can drive one Series 54 TTL circuit without external
resistors. The data outputs are three-state for connecting multiple devices to a common bus. The SMJ27C512
is pin compatible with existing 28-pin 512K ROMs and EPROMs. They are offered in a 600-mil dual-in-line
ceramic package (J suffix) rated for operation from -55°C to 125°C.
Since this EPROM operates from a single 5-V supply (in the read mode), it is ideal for use in
microprocessor-based systems. One other 12-13 V supply is needed for programming, but all programming
signals are TTL level. These devices are programmable by either Fast or SNAP! Pulse programming algorithms.
Fast programming uses a Vpp of 12.5 Vand a Vee of 6 V for a nominal programming time of two minutes. SNAP!
Pulse programming uses a Vpp of 13 V and a Vee of 6.5 V for a nominal programming time of four seconds.
For programming outside the system, existing EPROM programmers can be used. Locations may be
programmed singly, in blocks, or at random.
operation
The seven modes of operation forthe SMJ27C512 are listed in the following table. Read mode requires a single
5-V supply. All inputs are TTL level exceptforVpp during programming (12.5 Vfor Fast, or 13 V for SNAP! Pulse)
and 12VonA9forsignature mode.
~~o~~~~~~I: .~::~~~nal~~'ti::=:. :lle~:!'I':~~mde~f~
.tandard warranty. Production procenln; doe. not neceuarlly Include
t"tlng of an p"lm.t,r•.
TEXAS
~
Copyright
© 1993. Texas Instruments Incorporated
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
9-263
SMJ27C512
524 288·BIT UV ERASABLE PROGRAMMABLE READ·ONLY MEMORY
SGMS019B-SEPTEMBER 1987-REVISED FEBRUARY 1993
FUNCTIN
(PINS)
MODE
READ
OUTPUT
DISABLE
STANDBY
PROGRAMMING
VERIFY
PROGRAM
INHIBIT
SIGNATURE
MODE
VIL
VIL
VIH
VIL
VIL
VIH
VIL
VIL
VIH
xt
Vpp
VIL
Vpp
VIL
(28)
Vee
Vee
Vee
Vee
Vee
Vee
Vec
A9
(24)
X
X
X
X
X
X
VH:j:
VH:j:
AO
(10)
X
X
X
X
X
X
VIL
VIH
Data Out
HI-Z
HI-Z
Data In
Data Out
HI-Z
MFG
E
(20)
GNpp
(22)
Vee
00--07
(11-13,15-19)
CODE
97
DEVICE
I
85
t X can be VIL or VIH.
:j: VH = 12 V ± 0.5 V.
read/output disable
When the outputs of two or more SMJ27C512s are connected in parallel on the same bus, the output of any
particular device in the circuit can be read with no interference from the competing outputs of the other
devices. To read the output of the selected SMJ27C512, a low-level signal is applied to the E and GNpp
pins. All other devices in the circuit should have their outputs disabled by applying a high-level signal to one
of these pins. Output data is accessed at pins 00 through 07.
power down
Active Icc supply current can be reduced from 25 mA to 500 ~A (TTL-level inputs) or 350 ~A (CMOS-level inputs)
by applying a high logic signal to the E pin. In this mode all outputs are in the high-impedance state.
erasure
Before programming, the SMJ27C512 is erased by exposing the chip through the transparent lid to a high
intensity ultraviolet light (wavelength 2537 A). EPROM erasure before programming is necessary to assure
that all bits are in the logic 1 (high) state. Logic O's (lows) are programmed into the desired locations. A
programmed logic 0 (low) can be erased only by ultraviolet light. The recommended minimum ultraviolet
light exposure dose (UV intensity x exposure time) is 15 W·s/cm 2. A typical 12 mW/cm 2, filterless UV lamp
will erase the device in 21 minutes. The lamp should be located about 2.5 em above the chip during
erasure. After erasure, all bits are in the high state. It should be noted that normal ambient light contains
the correct wavelength for erasure. Therefore, when using the SMJ27C512, the window should be covered
with an opaque label.
SNAP! Pulse programming
The 512K EPROM can be programmed using the TI SNAP! Pulse programming algorithm illustrated by the
flowchart in Figure 1, which can reduce programming time to a nominal of four seconds. Actual programming
time will vary as a function of the programmer used.
Data is presented in parallel (eight bits) on pins 00 to 07. Once addresses and data are stable,
E is pulsed.
The SNAP! Pulse programming algorithm uses initial pulses of 100 microseconds (~) followed by a byte
. verification to determine when the addressed byte has been successfully programmed. Up to 10 (ten) 1OO-~s
pulses per byte are provided before a failure is recognized.
TEXAS
~
INSTRUMENTS
9-264
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
SMJ27C512
524 288·BIT UV ERASABLE PROGRAMMABLE READ·ONLY MEMORY
SGMS019B-SEPTEMBER 19B7-REVISED FEBRUARY 1993
The programming mode is achieved with GNpp = 13 V, Vee = 6.5 V, and E = VIL. More than one device can
be programmed when the devices are connected in parallel. Locations can be programmed in any order. When
the SNAPI Pulse programming routine is complete, all bits are verified with Vee = 5 V, GNpp = VIL and
E=~~
,
fast programming
The 512K EPROM can be programmed using the Fast programming algorithm illustrated by the flowchart in
Figure 2. During Fast programming, data is presented in parallel (eight bits) on pins 00 through 07. Once
addresses and data are stable, E is pulsed. The programming mode is achieved when GNpp = 12.5 V,
Vee 6 V, and E VIL. More than one SMJ27C512 can be programmed when the devices are connected in
parallel. Locations can be programmed in any order.
=
=
Programming uses two types of programming pulses: Prime and Final. The length of the Prime pulse is 1
millisecond; this pulse is applied X times. After each Prime pulse, the byte being programmed is verified.
If the correct data is read, the Final programming pulse is applied; if correct data is not read, an
additional 1 millisecond pulse is applied up to a maximum X of 25. The Final programming pulse is 3X
long. This sequence of programming and verification is performed at Vee = 6 V. When the full Fast
programming routine is complete, all bits are verified with Vee = 5 V (see Figure 2).
program inhibit
Programming may be inhibited by maintaining a high level input on the E pin.
program verify
Programmed bits may be verified with GNpp and E = VIL.
signature mode
The signature mode provides access to a binary code identifying the manufacturer and type. This mode
is activated when A9 (pin 24) is forced to 12 V ± 0.5 V. Two identifier bytes are accessed by AD (pin 10);
i.e., AD = VIL accesses the manufacturer code, which is output on 00-07; AD = VIH accesses the device
code, which is output on 0D-07. All other addresses must be held at VIL. E.ach byte possesses odd parity
on bit 07. The manufacturer code for these devices is 97, and the device code is 85.
latchup immunity
Latchup immunity on the SMJ27C512 is a minimum of 250 mA on all inputs and outputs. This feature provides
latchup immunity beyond any potential transients at the P.C. board level when the EPROM is interfaced to
industry-standard TTL or MOS logic devices. Input-output layout approach controls latchup without
compromising performance or packing density.
For more information see application report SMLA001, "Design Considerations; Latchup Immunity of the
HVCMOS EPROM Family", available through TI Sales Offices.
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
9-265
SMJ27C512
524 288·BIT UV ERASABLE PROGRAMMABLE READ·ONLY MEMORY
SGMS019B-SEPTEMBER 1987-REVISED FEBRUARY 1993
-I
Program
Mode
Increment Address
Increment
Address
Interactive
Mode
No
Yes
Device Failed
Final
Verification
J
Figure 1. SNAP! Pulse Programming Flowchart
TEXAS ~
INsrRUMENTS
9·266
POST OFFICE BOX 1443· HOUSTON, TEXAS 77001
SMJ27C512
524 288·BIT UV ERASABLE PROGRAMMABLE READ·ONLY MEMORY
SGMS019B-SEPTEMBER 1987-REVISED FEBRUARY 1993
Yes
Increment
Address
Figure 2. FAST Programming Flowchart
TEXAS ~
INsrRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
9-267
SMJ27C512
524 288·BIT UV ERASABLE PROGRAMMABLE READ·ONLY MEMORY
SGMS019B-SEPTEMBER 1987-REVISED FEBRUARY 1993
logic symbol t
AO
Al
A2
A3
A4
A5
A6
A7
A8
A9
Al0
All
A12
A13
A14
A15
E
GNpp
10
9
8
7
6
5
4
3
25
24
21
23
2
26
27
1
20
EPROM
0
65536x8
0
A 65535
A'J
A'J
A'J
A'J
A'J
A'J
A'J
A'J
11
12
13
15
16
17
18
19
00
01
02
03
04
05
06
07
15
T "-
22 ~
(PWRDWNI
~
EN
t This symbol is in accordance with ANSI/IEEE Std 91-1984 and lEG Publication 617-12.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted):j:
Supply voltage range, Vee (see Note 1) .............................................. -0.6 V to 7 V
Supply voltage range, Vpp ......................................................... -0.6 V to 14 V
Input voltage range (see Note 1), All inputs except A9 ................................ -0.6 V to 6.5 V
A9 ............................................... -0.6 V to 13.5 V
Output voltage range (see Note 1) ............................................. -0.6 V to Vee + 1 V
Minimum operating free-air temperature .................................................... -55°C
Maximum operating case temperature ...................................................... 125°C
Storage temperature range ....................................................... -65°C to 150°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to GND.
TEXAS
~
INSTRUMENTS
9-268
POST OFFICE BOX 1443 • HOUSTON, TEXAS 71001
SMJ27C512
524 288·BIT UV ERASABLE PROGRAMMABLE READ·ONLY MEMORY
SGMS019B-SEPTEMBER 19a7-REVISED FEBRUARY 1993
recommended operating conditions
SM/SMJ27C512-20
SM/SMJ27C512-25
SM/SMJ27C512-30
MIN
Read mode
Supply voltage (see Note 2)
VCC
4.5
5
5.75
6
SNAPI Pulse programming algorithm
6.25
6.5
12
12.5
12.75
13
SNAP! Pulse programming algorithm
TTL
High-level input voltage
V,H
V,L
Low-level input voltage
TA
Operating Iree-air temperature
5.5
Vce- O.2
CMOS
V
13
V
13.25
V
VCC+l
V
V
VCC+l
0.8
GND-0.2
GND+0.2
-55
V
V
°C
Operating case temperature
TC
NOTES:
6.75
-0.5
TTL
V
V
6.25
2
CMOS
UNIT
MAX
Fast programming algorithm
Fast programming algorithm
Supply voltage (see Note 3)
GNpp
NOM
125
°C
2. VCC must be applied belore or at the same time as GNpp and removed after or at the same time as GNpp. The device must not
be inserted into or removed lrom the board when GNpp or Vce is applied.
3. GNpp can be connected to VCC directly (except in the program mode). VCC supply current in this case would be ICC + Ipp.
electrical characteristics over full ranges of operating conditions
PARAMETER
TEST CONDITIONS
MIN
TYpt
MAX
High-level ouput voltage
IOH = -400 IAA
VOL
Low-level ouput voltage
10L = 2.1 mA
0.4
V
Input current (leakage)
V, = 0 to 5.5 V
±10
IAA
'0
Ipp
Output current (leakage)
VO=OtoVCC
GNpp supply current (during program pulse)l
GNpp = 13V
ICCI
VCC supply current (standby)
"
leC2
2.4
UNIT
VOH
V
±10
IAA
70
mA
35
ITTL-input level
VCC = 5.5 V, E = V,H
500
IAA
ICMOS-input level
Vee = 5.5 V, E = VCC
325
IAA
50
mA
VCC = 5.5 V, E = VIL,
tcycl e = minimum cycle time,
outputs open
VCC supply current (active)
35
t Typical values are at TA = 25°C and nominal voltages.
l This parameter has been characterized at 25°C and is not production tested.
capacitance over recommended
temperature, f = 1 MHz
PARAMETER
ranges
of
supply
voltage
TEST CONDITIONS
and
operating
MIN
free-air
TYpt
UNIT
Ci
Input capacitance
V, = 0, I = 1 MHz
6
pF
Co
Output capacitance
Vo = 0, 1=1 MHz
8
pF
CGNPP
GNpp input capacitance
GNpp = 0, I = 1 MHz
20
pF
tTYPlcal values are at TA = 25°C and nominal voltages.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
9-269
SMJ27C512
524 288·BIT UV ERASABLE PROGRAMMABLE READ·ONLY MEMORY
SGMS019B-SEPTEMBER 1987-REVISED FEBRUARY 1993
switching characteristics over full ranges of recommended operating conditions (see Note 4)
TEST CONDITIONS
(SEE NOTE 4)
PARAMETER
'27C512·20
'27C512·25
'27C512-30
MIN
MIN
MIN
MAX
MAX
MAX
UNIT
talA)
Access time from address
200
250
300
talE)
Access time from chip enable
200
250
300
ns
ten (G)
Output enable time from G
75
100
120
ns
tdis
Output disable time from G
or E, whichever occurs first t
105
ns
tv(A)
See Figure 3
0
Output data valid time after
change of address, E, or G,
whichever occurs first t
0
60
0
60
0
0
0
ns
ns
t Value calculated from 0.5 V delta to measured level.. ThiS parameter IS only sampled and not production tested.
recommended timing requirements for programming: Vee = 6 V and Vpp = 12.5 V (Fast) or
Vee = 6.5 and Vpp =13 (SNAP! Pulse), TA = 25°C (see Note 4)
Fast programming algorithm
MIN
NOM
MAX
UNIT
0.95
1
1.05
ms
95
100
105
fls
78.75
ms
tw(IPGM)
Initial program pulse duration
tw(FPGM)
Final pulse duration
tsu(A)
Address setup time
2
tdis(G)
Output disable time from G
0
tEHD
Data valid from E low
SNAP! Pulse programming algorithm
Fast programming only
2.85
!,S
130
flS
1
fls
tsu(D)
Data setup time
2
fls
tsu(VPP)
Vpp setup time
2
fls
tsu(VCC)
VCC setup time
2
fls
th(A)
Address hold time
0
flS
th(D)
Data hold time
2
fls
tr(PG)G
Vpp rise time
50
ns
th(VPP)
Vpp hold time
2
flS
trec(PG)
Vpp recovery time
2
flS
. .
..
NOTE 4: For all sWitching characteristics and timing measurements Input pulse levels are 0.4 V to 2.4 V. Timing measurements are made at 2
V for logic high and 0.8 V for logic low (reference page 9, AC testing waveforms).
TEXAS
~
INSTRUMENTS
9·270
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
SMJ27C512
524 288·BIT UV ERASABLE PROGRAMMABLE READ·ONLY MEMORY
SGMS019B-SEPTEMBER 1987-REVISED FEBRUARY 1993
PARAMETER MEASUREMENT INFORMATION
2.08 V
Output
Under Tesl
----1
T
RL = 800 Q
CL=100pF
Figure 3. AC Testing Output Load Circuit
AC'testing Input/output wave forms
2.4
v'----"v
'___oJ!\- 0.: ~
0.: ~:X'-___
0.4V~
A.C. testing inputs are driven at 2.4 V for logic high and 0.4 V for logic low. Timing measurements are made at
2 V for logic high and 0.8 V for logic low for both inputs and outputs.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
9-271
SMJ27C512
524 288·BIT UV ERASABLE PROGRAMMABLE READ·ONLY MEMORY
SGMS019B-SEPTEMBER 1967-REVISED FEBRUARY 1993
PARAMETER MEASUREMENT INFORMATION
=x
AO-A15
1
1..-
\
t
VIH
1
I
I
1
I}-
Output Valid
HI-Z -
Figure 4. Read Cycle Timing
AO-A15
==x
~
jCl
Address Stable
I.•------------------------------------------~ 1
.~ tsu(A)
QO-Q7
G/Vpp
----~~ D~ta
I
1
1
I[ ~
1
I
~ j+-
j>------ ----~~
In Stable
HI-Z
th(VPP)
tr(rG)G
th(D)
-'-----
~---rl----~I--------
1
1
I
----,-~'\
Data Out Valid
1
1
~ ~
1
I I
E tsu(VCC)
VIL
~r----I~~I- th(A)
II
~tsu(D)
1
1
J
VIH
POST OFFICE BOX 1443' HOUSTON,.TEXAS 77001
:::
SMJ27C512
524 288·BIT UV ERASABLE PROGRAMMABLE READ·ONLY MEMORY
SGMS019B-SEPTEMBER 1987-REVISED FEBRUARY 1993
TYPICAL SMJ27C512 CHARACTERISTICS
STANDBY SUPPLY CURRENT
1:
vs
FREE-AIR TEMPERATURE
SUPPLY VOLTAGE
Vee=5V
>-
1.25
c.~
CLog
.......
......
GI
1I)~1oo
>-
:gc
01
E
,
-a
(J
C
e
0.50
-75 -50 -25
........
c;.
>- c; 1.00
"""'- r-- :--
25
50
75
100 125
0.75
,,/
0.50
4.25
(J
4.5
4.75
5
5.25
vs
FREE-AIR TEMPERATURE
SUPPLY VOLTAGE
~
.
.........
i'-.. ..........
.............
r--r-
I
0.50
-75 -50 -25
1.50
:::I
(J
t) 0
~ 0.75
o
25
50
5.5
75
>-
1.25 f-
~ ~
1.00
~~
:::I N
-
I
~
~I ~
~ 0.75
N
(J
(J
0.50
4.25
100 125
I
TA = 25°C
f = Max
4.5
V
4.75
~
5
~
5.25
Vee - Supply Voltage - V
ACCESS TIME
ACCESS TIME
vs
vs
FREE-AIR TEMPERATURE
SUPPLY VOLTAGE
1.50
I
1.25
i=~
V
./
~ ~ 1.00
. ./
/
0.50
-75 -50 -25
..,
/
TA
GI
E
i=:s
~ :; 1.00
~ E
..I~
01 ~
25
50
.........
:l! l!l
,/
0
1.25
75
TA - Free-Air Temperature -
100 125
5.75
--
5.5
TA - Free-Air Temperature - °C
Vee = 5V
~ E
I 0
:J ~ 0.75
~
ACTIVE SUPPLY CURRENT
c:(
E
./
Z
vs
~ ~ 1.00
.-~ ...E
GI
01
ACTIVE SUPPLY CURRENT
a.'il
CLGI
1.50
-g 0
1
Vee - Supply Voltage - V
Vee = 5V
1.25
V
.c E
./
TA - Free-Air Temperature - °C
1.50
!:i
V
~ .~
[)
0
JI>/
~ 1.25
CLog
~ 0.75
[)
II
TA = 25'C
(J
l"-
•
1.50
~:::I
0
01 Z
1
c
1.50
e
!:i
(J
:J
STANDBY SUPPLY CURRENT
vs
5.75
~ 25 ,c i
~ r---
0.75
0.50
4.25
°C
4.5
4.75
5
5.25
5.5
5.75
Vee - Supply Voltage - V
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
9·273
SMJ27C512
524 288·BIT UV ERASABLE PROGRAMMABLE READ·ONLY MEMORY
SGMS019B--SEPTEMBER 1987-REVISED FEBRUARY 1993
TEXAS ~
INSTRUMENTS
9-274
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
SMJ27C040
4 194 304-BIT UV ERASABLE
PROGRAMMABLE READ-ONLY MEMORY
SGMS046--NOVEMBER 1992
•
Military Operating Temperature Range
- 55°C to 125°C
•
•
•
Organization ... 512K x 8
Vpp
32
Vee
Single 5-V Power Supply
A16
31
Industry Standard 32-Pin Dual-In-line
Package
29
•
All Inputs/Outputs Fully TIL Compatible
27
•
Static Operation (No Clocks, No Refresh)
25
A18
A1?
A14
, A13
A8
A9
A11
Max Access/Min Cycle Time
24
G
•
J PACKAGEt
(TOP VIEW)
30
28
26
Vcc
±
A2
A1
10%
'27C040-10
'27C040-12
'27C040-15
100 ns
120 ns
150 ns
•
8-Bit Output For Use in
Microprocessor-Based Systems
•
Power-Saving CMOS Technology
•
3-State Output Buffers
•
400-mV DC Assured Noise Immunity With
Standard TIL Loads
23
A10
22
E
AO
21
DOO
20
D01
D02
19
18
17
t
DO?
D06
D05
D04
D03
Package is shown for pinout reference only.
PIN NOMENCLATURE
•
Latchup Immunity of 250 mA on All Input
and Output Pins
•
•
No Pull up Resistors Required
AD-A18
E
G
GND
DOD-D07
Vee
Vpp
Low Power Dissipation (Vce = 5.5 V)
- Active .•. 385 mW Worst Case
- Standby ... 0.55 mW Worst Case
(CMOS-Input Levels)
Address Inputs
ehip Enable
Output Enable
Ground
Inputs (programming)/Outputs
5-V Supply
13-V Power Supplyl
l Only in program mode.
description
The SMJ27C040 series are 4 194 304-bit, ultraviolet-light erasable, electrically programmable read-only
memories.
These devices are fabricated using CMOS technology for high speed and simple interface with MOS and bipolar
circuits. All inputs (including program data inputs) can be driven by Series 54 TTL circuits. Each output can drive
one Series 54. TTL circuit without external resistors. The data outputs are three-state for connecting multiple
devices to a common bus.
The SMJ27C040 is offered in a 32-pin 600-mil dual-in-line cerdip package (J suffix) rated for operation from 55°C to 125°C.
Since this EPROM operates from a single 5-V supply (in the read mode), it is ideal for use in
microprocessor-based systems. One other (13V) supply is needed for programming. All programming signals
are TTL level. For programming outside the system, existing EPROM programmers can be used.
PRODUCTION DATA Inform.tlon I. current
It
of publication dat•.
Products conform to 'peelncatlonl per the term. of Texas Instruments
standard warranty. Production proc, ..lng doe. not necessarily Include
teatlng of all parameter•.
TEXAS
~
Copyright © 1992, Texas Instruments Incorporated
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
9-275
SMJ27C040
4 194 304·BIT UV ERASABLE
PROGRAMMABLE READ·ONLY MEMORY
SGMS046-NOVEMBER 1992
operation
The seven modes of operation are listed in the following table. The read mode requires a single 5-V supply. All
inputs are TTL level exceptfor Vpp during programming (13 V), and VH (12 V) on A9 for signature mode.
FUNCTION
AO
OQO-OQ7
X
Data Out
Vee
A9
x
x
x
HI-Z
Vee
Vee
X
X
HI-Z
VIH
VPP
Vee
X
X
Data In
VIH
VIH
Vpp
Vee
X
X
HI-Z
VIH
VIL
Vpp
Vee
X
X
Data Out
VIL
VIL
Vee
Vee
VIH T
E
G
Vpp
VCC
Read
VIL
VIL
Vee
Vee
Output Disable
VIL
VIH
Vee
Standby
VIH
X
Programming
VIL
Program Inhibit
Verify
Signature Mode
VIL
MFG eode97
VIH
Device Code 50
t X can be VIL or VIH
*VH=12V±O.5V
read/output disable
When the outputs of two or more SMJ27C040s are connected in parallel on the same bus, the output of any
particular device in the circuit can be read with no interference from competing outputs of the other devices. To
read the output of a single device, a low level signal is applied to the E and G pins. All other devices in the circuit
should have their outputs disabled by applying a high level signal to one of these pins. Output data is accessed
at pins 00-07.
latchup immunity
Latchup immunity on the SMJ27C040 is a minimum of 250 mA on all inputs .and outputs. This feature provides
latchup immunity beyond any potential transients at the P.C. board level when the EPROM is interfaced to
industry standard TTL or MOS logic devices. The input/output layout approach controls latchup without
compromising performance or packing density.
For more information see application report SMLA001, "Design Considerations; Latchup Immunity of the
HVCMOS EPROM Family", available through TI Sales Offices.
power down
Active ICC supply current can be reduced from 70 mA to 1 mA for a high TTL input on E and to 100 I-lA for a high
CMOS input on E. In this mode all outputs are in the high impedance state.
erasure (SMJ27C040)
Before programming, the SMJ27C040 EPROM is erased by exposing the chip through the transparent lid to
a high intensity ultraviolet-light (wavelength 2537 A). The recommended minimum exposure dose (UVintensity
x exposure time) is 15-Ws/cm2. A typical 12-mW/cm2, filterless UV lamp will erase the device in 21 minutes.
The lamp should be located about 2.5 cm above the chip during erasure. After erasure, all bits are in the high
state. It should be noted that normal ambient light contains the correct wavelength for erasure. Therefore, when
using the SMJ27C040, the window should be covered with an opaque label. After erasure (all bits in logic high
state), logic lows are programmed into the desired locations. A programmed low can be erased only by
ultraviolet light.
SNAPI Pulse programming
The SMJ27C040 and TMS27PC040 are programmed by using the SNAP! Pulse programming algorithm. The
programming sequence is shown in the SNAP! Pulse programming flow chart (Figure 1).
TEXAS
~
INSTRUMENTS
9-276
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SMJ27C040
4 194 304·BIT UV ERASABLE
PROGRAMMABLE READ·ONLY MEMORY
SGMS046-NOVEMBER 1992
=
The initial setup is Vpp 13 V, Vee =6.5 V, E =VIH, and G =VIH' Once the initial location is selected, the data
is presented in parallel (eight bits) on pins 001 through DOS. Once addresses and data are stable, the
programming mode is achieved when E is pulsed low (VIU with a pulse duration of tw(PGM)' Every location is
programmed only once before going to interactive mode.
In the interactive mode, the word is verified atVpp =13 V, Vee =6.5 V, E =VIH, and G =VIL. If the correct data
is not read, the programming is performed by pulling G high, then E low with a pulse duration of tw(PGM)' This
sequence of verification and programming is performed up to a maximum of 10 times. When the device is fully
programmed, all bytes are verified with Vee =Vpp =5 V ± 10%.
program inhibit
Programming may be inhibited by maintaining high level inputs on the E and
G pins.
program verify
Programmed bits may be verified with Vpp
=13 V when G =VIL, and E =VIH.
signature mode
The signature mode provides access to a binary code identifying the manufacturer and type. This mode is
activated when A9 (pin 26) is forced to 12 V. Two identifier bytes are accessed by toggling AO. All other
addresses must be held low. The signature code for the SMJ27C040 is 9750. AO low selects the manufacturer's
code 97 (Hex), and AO high selects the device code 50 (Hex), as shown by the signature mode table below.
PINS
003
AO
007
DOS
DOS
004
MANUFACTURER CODE VIL
1
1
0
0
0
DEVICE CODE
0
1
0
1
0
VIH
t E =G =VIL. Al-A8 =VIL. A9 =VH. Alo-A18 =VIL. Vpp =VCC.
IDENTIFIERT
002
1
001
000
1
1
0
0
0
HEX
97
50
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
9-277
SMJ27C040
4 194 304-BIT UV ERASABLE
PROGRAMMABLE READ-ONLYMEMORY
SGMS046-NOVEMBER 1992
l
Program
Mode
Increment Address
Increment
Address
Interactive
Mode
Final
Verification
J
Figure 1. SNAP! Pulse Programming Flow Chart
TEXAS ~
INsrRUMENTS
9-278
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
SMJ27C040
4 194 304·BIT UV ERASABLE
PROGRAMMABLE READ·ONLY MEMORY
SGMS046-NOVEMBER 1992
logic symbol t
EPROM 524 288 x 8
AD
Al
A2
A3
A4
A5
A6
A7
A8
A9
Al0
All
A12
A13
A14
A15
A16
A17
A18
E
12
11
10
9
0'
8
7
6
5
27
26
23
25
4
28
29
3
2
30
31
22
>
0
A 524287
A'll
A'll
A'll
A'll
A'll
A'll
A'll
A'll
13
14
15
17
18
19
20
21
DOD
001
002
003
004
DOS
006
007
18
T
[~WR OWN)
24~
&
IEN
t This symbol is in accordance with ANSI/IEEE Std 91 -1984 and lEG Publication 617-12.
Pin numbers shown are for the J package.
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
9-279
SMJ27C040
4 194 304·BIT UV ERASABLE
PROGRAMMABLE READ·ONLY MEMORY
SGMS046-NOVEMBER 1992
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage range, Vee (see Note 1) .............................................. -0.6 V to 7 V
Supply voltage range, Vpp (see Note 1) ............................................. -0.6 V to 14 V
Input voltage range (see Note 1), All inputs except A9 ................................ -0.6 V to 6.5 V
A9 ................................................ -0.6 V to 13 V
Output voltage range, with respect to Vss (see Note 1) ........................... -0.6 V to Vee + 1 V
Minimum operating free-air temperature .................................................... - 55°C
Maximum operating case temperature ...................................................... 125°C
Storage temperature range ....................................................... -65°C to 125°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to GND.
recommended operating conditions
Vee
Vpp
Supply voltage
Supply voltage
VIH
High-level input voltage
VIL
Low-level input voltage
TA
Operating free-air temperature
Te
Operating case temperature
NOTES:
Read mode (see Note 2)
SNAP! Pulse programming algorithm
Read mode (see Note 2)
TYP
MAX
4.5
8
5.5
6.25
6.5
6.75
V
Vee + 0.6
V
13.25
V
Vee- 0.6
SNAPI Pulse programming algorithm
12.75
TTL
13
2
Vee+0.5
Vee- 0.2
Vee+0.5
TTL
-0.5
0.8
eM OS
-0.5
0.2
CMOS
UNIT
V
V
V
·e
-55
125
·e
2. Vee must be applied before or althe same time as Vpp and removed after or althe same time as Vpp. The device must not be inserted
into or removed from the board when Vpp or Vee is applied.
3. Vpp can be connected to Vee directly (except in the program mode). Vee supply current in this case would be lee + Ipp.
During programming, Vpp must be maintained at 13 V ± 0.25 V.
TEXAS ~
INsrRUMENTS
9-280
MIN
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
SMJ27C040
4 194 304-BIT UV ERASABLE
PROGRAMMABLE READ-ONLY MEMORY
SGMS046-NOVEMBER 1992
electrical characteristics over full ranges of operating conditions
TEST CONDITIONS
PARAMETER
MIN
MAX
2.4
UNIT
VOH
High-level output voltage
10H =-400 flA
VOL
Low-level output voltage
10L= 2.1 mA
0.4
V
V
!!A
f!A
f!A
II
Input current (leakage)
VI = 0 to 5.5 V
±1
10
Output current (leakage)
Vo =OtoVCC
±1
IpP1
Vpp supply current
Vpp = VCC = 5.5 V
IPP2
Vpp supply current (during program pulse);
Vpp = 12.75 V,
TA-25'C
VCC = 5.5 V,
E=VIH
VCC = 5.5 V,
E=VCC
ICC1
ICC2
VCC supply current (standby)
LTTL-Input level
I CMOS-Input level
10
50
mA
1
mA
100
!!A
50
mA
E = VIL, VCC = 5.5 V
!cycle = minimum cycle time,
outputs open t
VCC supply current (active)
t Minimum cycle time = maximum access time.
; This parameter is only sampled and not 100% tested.
capacitance over recommended ranges of supply voltage and operating free-air temperature,
f = 1 MHz§ (Vee =Vpp =5 V ± 0.5 V)
TYP~
MAX
VI =0
4
8
pF
Output capacitance
VO=O
Co
. ..
§ Capacitance is sampled only at Initial design and after any major change .
~ All typical values are at TA = 25'C and nominal voltages.
8
12
pF
PARAMETER
Ci
TEST CONDITIONS
Input capacitance
MIN
UNIT
switching characteristics over full ranges of recommended operating conditions (see Notes 4
and 5)
TEST
CONDITIONS
(SEE NOTE
4AND 5)
PARAMETER
'27C040·10
'27C040-12
'27C040-15
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
talA)
Access time from address
100
120
150
ns
ta(E)
Access time from chip enable
100
120
150
ns
len (G)
Output enable time from G
50
50
50
ns
tdis
Output disable time from G or E, whichever occurs
first#
50
ns
tv(A)
Output data valid time after change of address, E,
or G, whichever occurs first#
(see Figure 2)
Input t r " 20 ns
Input tf S 20 ns
0
0
50
0
0
50
0
0
ns
# Value calculated from 0.5-V delta to measured output level. ThiS parameter IS only sampled and not 100% tested.
NOTES: 4. For all switching characteristics the input pulse levels are 0.4 V to 2.4 V. Timing measurements are made at 2 V for logic high and
0.8 V for logic low. (Figure 2)
5. Common test conditions apply for tdis except during programming.
TEXAS ~
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POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
9-281
SMJ27C040
4194 304·BIT UV ERASABLE
PROGRAMMABLE READ·ONLY MEMORY
SGMS046-NOVEMBER 1992
switching characteristics for programming: Vee = 6.5 V and Vpp = 13 V (SNAP! Pulse), TA = 25°C
(see Note 6)
PARAMETER
'dis(G)
Output disable time from G
len (G)
Output enable time from G
MIN
NOM
0
MAX
UNIT
100
ns
150
ns
recommended timing requirements for programming: Vee = 6.5 V and Vpp = 13 V (SNAP I Pulse),
TA = 25°C, (see Note 4)
MIN
TYP
MAX
95
100
105
I SNAPI Pulse programming algorithm
UNIT
tw(PGM)
Program pulse duration
lsu(A)
Address setup time
2
J.IS.
lsu(E)
E setup time
2
J.IS
tsu(G)
G setup time
2
J.IS
tsu(D)
Data setup time
2
J.lS
tsu(VPP)
Vpp setup time
2
J.lS
tsu(VCC)
VCC setup time
2
J.lS
th(A)
Address hold time
0
J.ls
th(D)
Data hold time
2
J.lS
NOTE 4:
For all switching characteristics the input pulse levels are 0.4 V to 2.4 V. Timing measurements are made at 2 V for logic high and
0.8 V for logic logic low. (Figure 2)
PARAMETER MEASUREMENT INFORMATION
2.0SV
Output
Under Test
X~.~
2.4V - - - - -.....
_ _ _ _ _- - '
O.4V
-II
RL=SOOQ
CL=100pF
O.:~XI<-_____
V
Figure 2. Output Load Circuit and Input/Output Wave Forms
TEXAS ~
INSTRUMENTS
9-282
J.lS
POST OFFICE BOX 1443· HOUSTON, TEXAS 77001
SMJ27C040
4 194 304·BIT UV ERASABLE
PROGRAMMABLE READ·ONLY MEMORY
SGMS046-NOVEMBER 1992
PARAMETER MEASUREMENT INFORMATION
AD-A18
J
~
I
I
I
I
\ X1
14-- ta(E)
I
I
I
:.- ten(Gl
OQD-OQ7
1/
VIL
VIH
Yf
-.!
I I+--
tdis
tv(A)~
~~~
HI-Z
VIH
:(1
I I
1 1
~
\
G
VIL
I
I
~
ta(A)
E
VIH
X
Addresses Valid
--+i
I
~HI-Z-
Output Valid
VIL
VOH
VOL
Figure 3. Read Cycle Timing
14l0III----- Verify
1414---- Program
AD-A18
~;......
---<~
I
} - HI-Z
I
1+---+1- tsu(O)
k= :::
_________
I
Data In Stable
I
I
A_d_d_re,. ~s_S_ta_b_le
________
~ tsu(A)
OQD-OQ7
I
14--- th(A)
{
---.I:
I
I0Il
I
:
T I:
---.I ~ tsu(E) I~ ~!
I
:
~th(O)
~ tsu(VCC) I
-----.i=v=
I
I
tdis(G)
vppt
I
I
I
.1I
__I;......_____- - - -
I
~ tsu(VPP)
Vcc
I
ten (G) -1"'..----.;"1
I
I
-------.;
{D~::b~~t j~------ ~:~~::
i
1.oI.J
r--I~----r--~---
VPP
-----.!~
----.;~
I
I
I
i:
:
141011--I.J~I!-
tsu(G)
VCC
Vee
I
~
I :
I
----~--------~~~--~/~---------tw(PGM)
t 13-V Vpp and 6.5-V Vee for SNAP! Pulse programming.
Figure 4. Program Cycle Timing (SNAP! Pulse Programming)
TEXAS
~
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POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
9-283
SMJ27C040
4 194 304·BIT UV ERASABLE
PROGRAMMABLE READ·ONLY MEMORY
SGMS046-NOVEMBER 1992
TEXAS ~
INSTRUMENTS
9-284
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
SMJ29F816
16 384-BIT SCOPE™ DIARY
JTAG ADDRESSABLE STORAGE DEVICE
SGMS053--NOVEMBER 1
•
Member of Texas Instruments SCOPE'·
Family of Testability Products
•
•
IEEE 1149.1 Serial Test Bus Compatible
•
JANUARY 1
FG PACKAGEt
{TOP VIEW)
0000
zzzZ
2 1 18 17
Organization. •. 2048 x 8-Bit Flash
Memory
TMS o 3
TCK ~ 4
NC P 5
TDI ~ 6
GND ~ 7
TCK Frequency (Vee ± 10%)
'29F816-06 ... 6.25 MHz
•
5-V Program/Erase/Read Operation
•
4 Flash-Erasable Blocks (128, 384, 512,
and 1024-Byte Size)
•
Software Sequence Write/Erase Protection
•
Lockbits
•
•
•
•
Self-Timed Write/Erase Cycles
0
16
VCC
15
DLB
14
NC
13
12
TDO
DLA
8 9 10 11
0000
zzzz
t Package is shown for pinout reference only.
PIN NOMENCLATURE
TMS
TCK
TDI
TOO
DLA
DLB
Streaming Read/Write Modes
32-Byte Page Programming Mode
CMOS Technology
•
Single 5-V Power Supply (± 10% Tolerance)
•
18-Pin Leadless-Ceramic Chip Carrier
Package (FG Suffix)
•
Operating Free-Air Temperature Range
- 55°C to 125°C
VCC
GND
NC
Test Mode Select
Test Clock
Test Data In
Test Data Out
Disable Lock A
Disable Lock B
5-V Power Supply
Ground
No internal connection
description
The SCOPE Diary is a 16 384-bit, programmable storage device that can be electrically block-erased and
reprogrammed. The SCOPE Diary is fabricated using HVCMOS FLOTOX technology for high reliability and very
low power dissipation. It performs the erase/program operations automatically with a single 5-V supply voltage,
and it can program a single byte or up to 32 bytes in one cycle.
All SCOPE Diary operations are accomplished via a 4-wire Test Access Port (TAP) interface. This interface
complies with the IEEE 1149.1 Serial Test Bus standard (JTAG). The interface consists of two control signals:
Test Mode Select (TMS) and Test Clock (Tel<); and two test data pins: Test Data In (TDI) and Test Data Out
(TDO). The JTAG Test Access Protocol defines how this 4-wire test bus is used to scan in instructions and data,
execute instructions, and scan out the resulting data.
All test information is serially loaded into the chip via TDI and out of the chip via TOO. Three mandatory JTAG
components are added to the Flash EEPROM array: a TAP controller, a set of test data registers, and an
instruction register.
The TAP controller interfaces both the test data registers and the instruction register to the 4-wire test bus. The
test data registers load and/or capture test data. The instruction register selects the test data register(s) to be
accessed and the test to be performed. There are three types of test data registers: the Data Scan Registers
(DSR), the Bypass Register (BR), and the Device Identification Register (lOR).
SCOPE is a trademark of Texas Instruments Incorporated.
TEXAS
~
Copyright © 1993. Texas Instruments Incorporated
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
9-285
SMJ29F816
16 384·BIT SCOPETM DIARY
JTAG ADDRESSABLE STORAGE DEVICE
SGMS053-NOVEMBER 1990-REVISED JANUARY 1993
The SCOPE Diary is divided into four independently flash-erasable blocks. These blocks are configured as 128,
384, 512, and 1024 bytes in size. These blocks can be prevented from being programmed or erased by
programming any or all of the four write-once lockbits.
The SCOPE Diary features internal circuitry for self-timed programming, self-timed erasing, and completion
polling. In the erased state, all bits are at a logical 1. To reprogram, all memory bits in a selected block are erased
first, and then those bits (now logical 1s) are programmed accordingly. The SCOPE Diary supports a page
programming mode that allows programming of up to 32 bytes in one cycle. During programming and erasing,
the completion status is available, allowing the system to begin a new operation before the maximum specified
timeout.
An on-chip power supply reference comparator protects the SCOPE Diary from write and erase commands
during power up and power down. During normal operation, software sequences protect against inadvertent
program and erase commands.
The SCOPE Diary is offered in an 18-pin leadless ceramic chip carrier package (FG suffix). It is characterized
for operation from - 55°C to 125°C.
The SCOPE Diary is available in a 1000-cycle endurance version.
terms
clock
The term clock refers to the system test clock used by the controller and its target(s). The clock is input on TCK.
DMA
The SCOPE Diary supports the Direct Memory Access (DMA) extension to the 1149.1 standard. The DMA mode
enables a continuous stream of bits to be scanned in or out of the SCOPE Diary.
host
The term host refers to the device directing the activity of the SCOPE Diary.
JTAG
The Joint Test Action Group (JTAG) is the originator of IEEE Standard 1149.1.
SCOPE
System Controllability and Observability Partitioning Environment (SCOPE) is the family name for Texas
Instruments testability products.
logic symbol t
OLA
OLB
TCK
TMS
TOI
13
15
16
3
6
OLA
OLB
TCK
Scope Diary
SMJ29F816
Flash EEPROM
2Kx8
TMS
TOI
TOO\'
t This symbol is in accordance with ANSI/IEEE Std 91-1984 and lEe Publication 617-12-1991.
TEXAS
~
INSTRUMENTS
9-286
POST OFFICE BOX 1443· HOUSTON. TEXAS 77001
12
TOO
SMJ29F816
16 384·BIT SCOPE™ DIARY
JTAG ADDRESSABLE STORAGE DEVICE
SGMS053-NOVEMBER 199Q-REVISED JANUARY 1993
functional block diagram
2K x8
Flash EEPROM
Memory Core
DOUT
ADDRESS
~;w~;T---Sequence
I
Lockblts
~e~c~!:......l _ _ _ _
Page Programming Buffer
DLA
DLB
TDI--~~--~~---------'
L.---tI,NSTRUCT,ON 8 S I I - - - - - - - - + I
Instruction Register
TMS
TCK
Terminal Functions
Pin
Name
Pin'
I/O
Description
TMS
3
I
Test Mode Select. Controls transition ofTAP finite state machine. This input is sampled on the rising edge
ofTCK.
TCK
4
I
Test Clock. Input clock to TAP finite state machine. All changes in state are synchronous to the test clock
TCK.
TDI
6
I
Test Data In. Data input to the internal register scan path. Data on this pin is sampled on the rising edge
ofTCK.
TOO
12
0
Test Data Out. Data output from the internal register scan path. Data is updated on this pin on the falling
edgeofTCK.
DLA
13
I
o (LCKO) determines whether block 0 can be erased or programmed. When DLA = VIH
DLB
15
I
VCC
16
I
5-V Power Supply, (± 10% operating power supply connection.)
GND
7
I
Ground reference
Disable Lock A. Controls lockbitfunctionality for memory array block O. When DLA = VIL, the state of lockbit
block 0 can be
erased or programmed regardless olthe state of 10ckbitO. When DLA = VH (VH » V cel, the SCOPE Diary
enters a special manufacturing test mode.
Disable Lock B. Controls lockbit functionality for memory blocks 1,2, and 3. When DLB = VIL, the staiEiS
of lockbits 1,2, and 3 (LCK1, LCK2, LCK3) determine whether their respective blocks (1, 2, and 3) can
be erased or programmed. When DLB = VIH, blocks 1,2, and 3 can be erased or programmed, regardless
of the state of their associated lockbits.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
9-287
SMJ29F816
16 384·BIT SCOPE™ DIARY
JTAG ADDRESSABLE STORAGE DEVICE
SGMS053-NOVEMBER 1990-REVISED JANUARY 1993
Internal registers
Note that the most significant bit is farthest from the output (TDO) in all internal registers.
instruction
The instruction register is an 8-bit shift register with parallel inputs to monitor the SCOPE Diary status. The most
significant bit (7) is a parity bit. The SCOPE. Diary status is loaded into the instruction register during the
Capture-IR controller state (see Figure 1). During the Shift4R state, the status bits are shifted out as a new
SCOPE Diary instruction is scanned into the instruction register.
Bll#
I
tR
7
6
5
4
3
2
IRP
PlEBS
SSS
LMS
VMS
PIECES
0
R_1 t
R-O
R-D
R-O
R-D
R-D
R-O
R-1
= Read, -n = Value after resel
Bit 0:
Always loaded with 1.
Bit 1:
Always loaded with 0
Bit 2:
Bit 3:
Bit 4:
Bit 5:
Bit 6:
Bit 7:
PIECES - Program/Erase Contention Error Status
No error detected.
1 = Attempt to write to SCOPE Diary during busy state.
o=
VMS - Verify Mode Status
Normal operating mode.
1 = SCOPE Diary is in either program-verify or erase-verify mode. This bit will remain set until
exit-verify software sequence is issued.
o
LMS - Lock Mode Status
Normal operating mode.
1 = SCOPE Diary is in lockbit mode.
o=
SSS - Software Sequence Status
Normal operating mode.
1 = Valid software sequence detected. The bit will be set within 2 lIS after the SCOPE Diary
detects a valid software sequence. The bit will remain set until one of the following occurs:
a) The sequence timer expires.
b) The active program or erase cycle is complete.
c) The CLRSWS command is issued.
o
PlEBS - Program/Erase Busy Status
Normal operating mode.
1 = Busy state. The SCOPE Diary is executing a self-timed program or erase operation. The bit
will be set within 2 lIs after the BEGOPS instruction is executed. This bit will remain set until
the operation is complete.
o
IRP - Instruction Register Parity
All valid commands to the instruction register are even parity.
Parity error detected in previously loaded instruction. The SCOPE Diary will automatically
place the BYPASS register into the data register scan path.
No parity error in previously loaded instruction.
o
Figure 1. Instruction Register Status
TEXAS
~
INsrRUMENTS
9·288
0
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
SMJ29F816
16 384·BIT SCOPE™ DIARY
JTAG ADDRESSABLE STORAGE DEVICE
SGMS053--NOVEMBER 199(}-REVISED JANUARY 1993
boundary-scan
The boundary-scan register is a 2-bit register. Bit 0 of this register is connected to OLA; bit 1 is connected to
OLB. This register can only be used to sample the connected inputs; therefore, values stored in the
boundary-scan register during the Update-DR controller state will not be applied to the internal core logic.
device-identification
The device identification register returns the following 32-bit code when interrogated with the IOCOOE
command: 0000102Fh. The device iO register is selected into the scan path during power-on reset or upon
entering the Test-Logie-Reset state.
bypass
The bypass register is a 1-bit register. It allows data to transfer from TOI to TOO in one TCK clock cycle. The
bypass register is selected into the scan path when a parity error is detected during the Shift-IR state.
memory-data
The memory-data register is an 8-bit register used to load data into the memory array during write operations.
This register is also used to sample data from the memory array during read operations. The parallel-scan load
path is connected to the memory core data outputs. The output of the register latch is connected to the data input
of the memory core. The operation of the register is shown in Table 1.
Table 1. Memory-Data Register Operation
Opcode
Capture-DR
Shift-DR
Update-DR
DMARD
Memory Data to Scan
Data Stream from Array
Scan to Register Latch
DMAWR
Memory Data to Scan
Data Stream to Array
Scan to Register Latch
BYTERD
Memory Data to Scan
Normal Shift Operation
Scan to Register Latch
BYTEWR
Memory Data to Scan
Normal Shift Operation
Scan to Register Latch
ISTEST
Register Latch to Scan
Normal Shift Operation
Scan to Register Latch
memory-address
The memory-address register is a 16-bit register used to address the Flash EEPROM array during read and
write operations. Bits 10 - 0 are used to address the Flash memory array. Bits 14 - 0 are used to address the
software sequence detector. The operation of the register is shown in Table 2.
Table 2. Memory-Address Register Operation
Opcode
Capture-DR
Update-DR
Shift-DR
LDADDR
Register Latch to Scan
Normal Operation
Scan to Register Latch
DMARD
Hold
Auto-Increment
Hold
DMAWR
Hold
Data Stream to Array
Hold
BYTERD
Register Latch to Scan
Normal Operation
Scan to Register Latch
BYTEWR
Register Latch to Scan
Normal Operation
Scan to Register Latch
ISTEST
Register Latch to Scan
Normal Operation
Scan to Reg ister Latch
TEXAS
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page programming buffer
The programming pages begin on 32-byte boundaries. Data being written to the SCOPE Diary is stored in the
32-byte page programming buffer until the memory-array programming cycle begins. The page buffer address
mechanism does not automatically recognize page programming buffer loads that cross a page boundary. Bits
10 - 5 of the last address presented to the page programming buffer will be used as the page pointer when the
memory array programming cycle begins. After an initial data value is loaded into the page programming buffer,
all remaining bytes within the page programming buffer are initialized to FFh.
erase-select
The erase-select register is a 4-bit register used to select the Flash memory block(s) that will be erased during
an erase cycle. Each bit in the register maps to one of the memory blocks (see Figure 2). To select a block for
erasure, set the block's corresponding memory-control bit to logic 1. The operation of the register is shown in
Table 3.
Blt#
o
3
2
Block 3
Block 2
RW-O
RW-ot
t R = Read, W = Write, -n = Value after reset
Bit 0:
Block 1
Block 0
RW-O
RW-O
Block 0 Erase Enable (address 0000 - 007F)
o =Erase disable
1 = Erase enable
Bit 1:
Bit 2:
Bit 3:
Block 1 Erase Enable (address 0080 - 01 FF)
o =Erase disable
1 = Erase enable
Block 2 Erase Enable (address 0200 - 03FF)
o = Erase disable
1 = Erase enable
Block 3 Erase Enable (address 0400 - 07FF)
o = Erase disable
1 = Erase enable
Figure 2. Erase-Select Register
Table 3. Erase-Select Register Operation
Opcode
Capture-DR
Reg ister Latch to Scan
Scan to Register Latch
ISTEST
Register Latch to Scan
Scan to Register Latch
TEXAS •
INSTRUMENTS
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Update-DR
ERABLK
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16 384·BIT SCOPETM DIARY
JTAG ADDRESSABLE STORAGE DEVICE
SGMS053--NOVEMBER 1990-REVISED JANUARY 1993
lockbits
The lockbit register contains four one-time-programmable, non-erasable bits. The lockbits map one-to-one to
the blocks in the array (bit 0 maps to block 0). The lockbit register is not located on the scan path; it is internal
to the memory core. It can be accessed using the memory-address and memory-data registers.
To prevent a block from being programmed or erased, program a logic 0 in the block's corresponding bit position.
Read and write operations to the lockbits are selected by the SETLOCK instruction. To program the lockbits,
execute the DMAWR or BYTEWR instruction sequences while in the lock mode. The lockbit register is shown
in Figure 3.
Blt#
2
o
3
r------------,-------------,-------------,------------,
Block 3
Block 2
Block 1
Block 0
RW-1+
RW-1
RW-1
RW-1
t R = Read, W = Write, -n = Initial value
Bit 0:
Block 0 Lock Enable (address 0000 - 007F)
o = Block program and erase disable
1 =Block program and erase enable
Bit 1:
Block 1 Lock Enable (address 0080 - 01 FF)
o =Block program and erase disable
1 =Block program and erase enable
Bit 2:
Bit 3:
Block 2 Lock Enable (address 0200 - 03FF)
o =Block program and erase disable
1 =Block program and erase enable
Block 3 Lock Enable (address 0400 - 07FF)
o =Block program and erase disable
1 =Block program and erase enable
Figure 3. Lockbit Register
header
The header register is an a-bit register used to control the mode of operation during a DMAWR instruction. The
register is cleared to zero on power up and upon entering the Test-Logie-Reset state. When the register is
cleared (all bits to logic 0), the SCOPE Diary uses a state-transition mode to synchronize the DMA write
operation. If the register is not cleared, the contents will be used as a shift data input pattern match to
synchronize the start of the DMA write operation.
TEXAS
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INSTRUMENTS
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16 384-BIT SCOPETM DIARY
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Test-Logic Reset
TMS=L
TMS=H
.,----Run-Test/Idle
TMS=H
TMS=L
Figure 4. TAP State Diagram
TEXAS ~
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TMS=L
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16 384-BIT SCOPETM DIARY
JTAG ADDRESSABLE STORAGE DEVICE
SGMS053--NOVEMBER 1990--REVISED JANUARY 1993
TAP state diagram description (see Figure 4)
The SCOPE Diary TAP controller accepts TCK and TMS signals compatible with I EEE Standard 1149.1. There
are six stable states (indicated by a looping arrow) and ten transient states (indicated by two exiting arrows) in
the diagram. A stable state is defined as a state the TAP can retain for consecutive TCK cycles. Any other state
is a transient state.
There are two main paths through the state diagram; one accesses selected data registers, and one accesses
the instruction register.
Test-Logic-Reset
In this state, the test logic is inactive, and an internal reset signal is applied to all registers in the SCOPE Diary.
During SCOPE Diary operation, the TAP returns to the Test-Logie-Resetstate in no more than five TCK cycles
ifTMS is high. The TMS pin has an internal pullup that forces itto a high level when it is left unconnected or when
a board defect causes it to be open-circuited.
Run-Test/Idle
The TAP must pass through this state before executing any test operations. The TAP may retain this state
indefinitely. No registers are modified while the SCOPE Oiary is in the Run-Test/Idle state.
Select-OR-Scan, Select-IR-Scan
No specific function is performed in these states. TAP exits them on the next TCK cycle.
Capture-DR
Selected data registers are placed in the scan path (between TOI and TOO). The current instruction determines
whether or not the data is loaded or captured into the scan path. The TAP exits the state on the rising edge of
TCK.
Shift-DR
In this state, data is shifted serially through the selected data registers, from TOI to TOO, on each TCK cycle.
The first shift occurs after the first TCK cycle after entering this state. (No shifting occurs during the TCK cycle
in which the TAP changes from Capture-DR to Shift-DR or from Exit2-DR to Shift-DR.)
In Shift-DR, on the falling edge of TCK, TOO goes from the high-impedance state to the active state. If the TAP
has not passed through the Test-Logie-Reset state since the last scan operation, TOO enables to the level
present before it was last disabled. If the TAP has passed through the Test-Logie-Reset state since the last
operation, TDO enables to a high level.
Exit1-DR, Exit2-DR
These are temporary states used to end the shifting process. It is possible to return to the Shift-DR state from
either Exit1-DR or Exit2-DR without recapturing the data registers. TOO changes from the active state to the
high-impedance state on the falling edge of TCK as the TAP changes from Shift-DR to Exit1-DR.
Pause-DR
The TAP can remain in this state indefinitely. The Pause-DR state allows you to suspend and resume shift
operations without losing data.
Update-DR
In the Update-DR state, the current instruction determines whether or not the latches in the selected data
registers are updated with data from the scan path.
TEXAS
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TAP state diagram description (continued)
Capture-IR
In the Capture-fR state, the instruction register is preloaded with the I R status word, and then it is placed in the
scan path. The TAP exits the state on the rising edge of TCK.
Shift-IR
In this state, data is shifted serially through the instruction register, from TOI to TOO, on each TCK cycle. The
first shift occurs after the first TCK cycle after entering this state. (No shifting occurs during the TCK cycle in
which the TAP changes from Capture-fRto Shift-fR or from Exit2-fRto Shift-fR.) In Shift-fR, on the falling edge
of TCK, TOO goes from the high-impedance state to the active state.
Exit1-IR, Exit2-IR
These are temporary states used to end the shifting process. It is possible to return to the Shift-fR state from
either Exit1-fR or Exit2-fR without recapturing the instruction register. TOO changes from the active state to the
high-impedance state on the falling edge of TCK as the TAP changes from Shift-fR to Exit1-fR.
Pause-IR
The TAP can remain in this state indefinitely. The Pause-fR state allows you to suspend and resume shift
operations without losing data.
Update-IR
In the Update-fR state, the instruction register latches are updated with the new instruction from the scan path.
instructions
standard SCOPE instructions
The SCOPE Diary supports a subset of the standard SCOPE instruction set. The defined instructions are shown
in Table 4. All other SCOPE instructions select the default BYPASS instruction.
Table 4. Standard SCOPE Instructions
Description
Opcode
Code
BYPASS
FFh
EXTEST
OOh
External Boundary Test (see Note 1)
IDCODE
81h
ID Register Scan
SAMPLE
82h
Boundary Sample
Select Bypass Register
NOTE 1: During operation, the EXTEST instruction behaves identically to the SAMPLE instruction.
SCOPE Diary-specific instructions
The SCOPE Diary supports specific instructions to control the operation of the Flash EEPROM array. The
defined instructions are shown in Table 5. All undefined opcodes select the BYPASS instruction.
TEXAS
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INSTRUMENTS
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16 384·BIT SCOPE™ DIARY
JTAG ADDRESSABLE STORAGE DEVICE
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Table 5. SCOPE Diary-Specific Instructions
Description
Opcode
Code
BEGOPS
69h
Begin Operation in Progress
BYTERD
63h
Byte Read
BYTEWR
E4h
Byte Write
CLRERR
6Ah
Clear Conflict Error Flag
CLRLOCK
66h
Exit Lock Mode
CLRSWS
EBh
Clear Software Sequence
DMARD
Elh
DMARead
DMAWR
E2h
DMAWrite
ERABLK
E7h
Erase Block Register Select
ISTEST
6Ch
Internal Self Test
LDADDR
60h
Load Address Register
LOADHDR
E8h
Header Register Select
SETLOCK
65h
Enter Lock Mode
BEGOPS
Begin Operation in Progress
Scan Path
TDI
---+
bypass
---+
TOO
Description The BEGOPS instruction is used to initiate a program, erase, or verify mode operation after the
appropriate software sequence has been issued. This instruction must be executed within 6 ms of the
last write operation, and the software sequence status bit in the instruction register must be set, or the
selected operation will not begin. If the time-out condition is not met, the software sequence commands
must be re-issued. Once the BEGOPS instruction is loaded, it is not executed until the diary is placed
in the Run-Test/Idle state.
BYPASS
Scan Path
Select Bypass Register
TOI ---+ bypass ---+ TOO
Description The BYPASS instruction conforms to the 1149.1 BYPASS instruction. The one-bit bypass register is
selected in the scan path. A logic 0 is loaded in the bypass register during the Update-DR state.
BYTERD
Byte Read
Scan Path
TOI
---+
memory-data
---+
memory-address
---+
TOO
Description The BYTERO instruction is used to read the value stored in a memory array location. During the read
operation, the contents of the memory-address register point to the value. This value is captured in the
memory-data register during the Update-DR state.
BYTEWR
Byte Write
Scan Path
TOI
---+
memory-data
---+
memory-address
---+
TOO
Description The BYTEWR instruction performs two operations. It can write 8-bit values into both the software
sequence detector and the page programming buffer. The contents of the memory-address register and
the contents of the memory-data register are presented to the memory core during the Update-DR
state. On the rising edge of TCK, upon leaving the Update-DR state, an internal write signal is applied
to either the software sequence detector or the page programming buffer.
TEXAS
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INSTRUMENTS
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CLRERR
Clear Conflict Error Flag
Scan Path
TDI
-+
bypass
-+
TOO
Description The CLRERR instruction is used to reset the program/erase conflict flag. The conflict flag (status bit 2
in the instruction register) will be set if any write operations are issued while the SCOPE Diary is
programming or erasing. After the conflict flag is set, the SCOPE Diary won't recognize any sequence
commands. The conflict flag will remain set until the CLRERR instruction is executed.
CLRLOCK
Exit Lock Mode
Scan Path
TDI
-+
bypass
-+
TOO
Description The CLRLOCK instruction is used to exit the lock mode. When the lock mode is disabled, all read and
programming operations are directed to the memory array. The normal mode is indicated when status
bit 4 is cleared in the instruction register.
CLRSWS
Clear Software Sequence
Scan Path
TDI
-+
bypass
-+
TOO
Description The CLRSWS instruction is used to clear software sequence operations. The iristruction will reset or
cancel any software sequence up until the BEGOPS instruction is executed. The CLRSWS instruction
will also clear status bit 5 (valid software sequence detected) in the instruction register. The CLRSWS
instruction will not interrupt an erase or program operation once the operation has started;
DMARD
DMARead
Scan Path
TDI
-+
(ignored) / memory-data -+ TOO
Description The DMARD instruction is used to perform streaming data reads from the Flash EEPROM memory
array. During the read operation, upon entering the Shift-DR state, the contents of the memory array
will be shifted out beginning with the currently addressed location. The memory-address register is
automatically incremented on each byte boundary while performing the DMARD operation. Input data
on the TDI pin is discarded and does not pass through. to the TOO output pin.
DMAWR
DMAWrite
Scan Path
TDI
-+
memory-data
-+
memory-address
-+
TDO
Description The DMAWR instruction allows a streaming method of writing address/data pairs to the SCOPE Diary.
During the Shift-DR state, the SCOPE Diary will automatically generate write strobes to the memory
core on each 24-bit address/data pair boundary. The SCOPE Diary supports two modes of
synchronizing the write operation with the incoming address/data pairs; state-transition mode and
stream-header mode. The contents of the header register determine the selected mode.
ERABLK
Erase Block Register Select
Scan Path
TDI
-+
erase-block
-+
TOO
Description The ERABLK instruction is used to access the erase-block select register. Data loaded into the ERABLK
register is presented to the memory core during the Update-DR state.
·TEXAS
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INsrRUMENTS
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16 384·BIT SCOPE™ DIARY
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SGMS053--NOVEMBER 199(}-REVISED JANUARY 1993
EXTEST
External Boundary Test
Scan Test
TDI
--+
boundary-scan
--+
TDO
Description The EXTEST instruction is used to check the board connectivity of the DLA and DLB input pins. During
an EXTEST operation, DLA and DLB inputs to the internal control logic can be sampled by the scan
path, but not driven.
IDCODE
ID Register Scan
Scan Path
TDI
--+
id
--+
TDO
Description The IDCODE instruction is used to read the device identification data. During the Capture-DR state, the
32-bit device identification code (0000102Fh) is loaded into the ID register. The IDCODE instruction is
automatically loaded during SCOPE Diary power-on reset or upon entry to the Test-Logic-Resetstate.
ISTEST
Internal Self Test
Scan Path
TDI
--+
boundary-scan
--+
erase-block
--+
header
--+
memory-data
--+
memory-address
--+
TDO
Description The ISTEST instruction is used to test scan path data registers. During the Capture-DR state, all of the
register latched values are transferred to the scan path (except the boundary scan register which
transfers the values of DLA and DLB to the scan path).
LOAD DR
Load Address Register
Scan Path
TDI
--+
memory-address
--+
TDO
Description The LDADDR instruction is used to load the memory-address register. The 16-bit value loaded from the
scan path points to an address and is presented to the memory array during the Update-DR state.
LOADHDR
Header Register Select
Scan Path
TDI
--+
header --+ TDO
Description The LOADHDR instruction is used to access the header register. Loading any value from 01 h to FFh
selects header mode synchronization during DMA write operations. Loading the header register with
OOh selects state-transition mode synchronization for DMA write operations. During the LOADHDR
operation, the header register is selected into the DR scan path.
SAMPLE
Boundary Sample
Scan Path
TDI
--+
boundary-scan
--+
TDO
Description The SAMPLE instruction is used to check the board connectivity of the DLA and DLB input pins. During
a SAMPLE operation, DLA and DLB inputs to the internal control logic can be sampled by the scan path,
but not driven.
SETLOCK
Enter Lock Mode
Scan Path
TDI
--+
memory-data
--+
TDO
Description The SETLOCK instruction is used to enable the lock mode. When the lock mode is enabled, read and
programming operations are directed to the lockbits. The lock mode operation is indicated when status
bit 4 is set in the instruction register. The SCOPE Diary will remain in the lock mode until the CLRLOCK
instruction is executed. While in the lock mode, all read operations capture the state of the lockbits in
the data-memory register. While reading the lockbits, the four most significant bits are set to logic 1.
TEXAS
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SGMS05~OVEMBER
199Q-REVISED JANUARY 1993
operation
TAP state controller
Operation of the TAP state controller conforms to the IEEE 1149.1 Serial Test Bus standard. The state flow
diagram is shown in Figure 4 on page .8.
loading and executing instructions
All bus sequences that load and execute instructions start with the TAP in the Run- Test/Idle state. To initialize
the TAP to Run-Test/Idle from any other state, apply the 6-cycle sequence shown in Table 6.
Table 6. TAP Reset Sequence
Cycle
1
2
3
4
5
6
TMS
1
1
1
1
1
0
TCK
J
J
J
J
J
J
TOil
X
X
X
X
X
X
TOO
(See Note 2)
HI·Z
HI-Z
HI·Z
HI·Z
HI·Z
TAP
State
Undefined
Undefined
Undefined
Undefined
Test·
Logic·Reset
Run·
Test/Idle
t X denotes a don't care.
NOTE 2: TOO will become high-impedance on falling edge of TCK.
sequence timing
The SCOPE Diary contains internal timing logic to simplify programming and erase operations. Once the host
initiates a programming or erasing operation, that operation will automatically continue to completion. The host
does not need to intervene until the operation is finished. To check the status of the operation, poll status bit 6
.
of the instruction register.
software sequence
The host initiates all of the SCOPE Diary's internal memory operations by issuing a sequence of address/data
pairs (forming a specific software sequence) to the SCOPE Diary. The correct address/data pairs must be
received in a specific order and within a specific time period to be recognized as a valid software sequence by
the SCOPE Diary. Once a sequence has begun, the SCOPE Diary starts an internal sequence timer. Each
consecutive address/data pair must be received within a 6 ms time period. After each address/data pair, the
timer is reset to receive the next sequence pair. If the time between consecutive address/data pairs exceeds
the timer limit, the internal state of the sequence detector will be reset, and the host must re-issue the software
sequence from the beginning. If the SCOPE Diary detects a valid software sequence, status bit 5 of the
instruction register will be set within 2 Ils and will remain set as long as the SCOPE Diary is unlocked for the
operation. The host may terminate a software sequence at any point by either letting the internal time limit expire,
or by issuing a CLRSWS command. The software sequences recognized by the SCOPE Diary are shown in
Table 7.
TEXAS
~
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16 384·BIT SCOPE™ DIARY
JTAG ADDRESSABLE STORAGE DEVICE
SGMS053-NOVEMBER 1990-REVISED JANUARY 1993
Table 7. SCOPE Diary Software Sequences
Operation
Address/Data Pair Sequence
Programming
2AAAh /55h
5555h / AAh
5555h / AOh
5555h / AAh
2AAAh /55h
5555h / Bah
Erasing
5555h / AAh
2AAAh /55h
5555h / 10h
5555h / AAh
Program-Verify
2AAAh /55h
5555h / Bah
5555h / AAh
Erase-Verify
2AAAh /55h
5555h / DOh
5555h / AAh
Exit-Verify
2AAAh /55h
5555h / FOh
page programming buffer
The page programming buffer is a 32-byte buffer that the host loads with the data to be programmed into the
memory array. This buffer is internal to memory and can be accessed using the memory-address and
memory-data registers. The page programming buffer is automatically selected by internal control logic after
it detects a valid program software sequence. The contents of this buffer are automatically set to FFh, so any
bits not specifically cleared by the host will not be programmed. Up to 32 bytes can be programmed in one cycle.
Address/data pairs must be loaded into the page programming buffer within the same time constraints as the
software sequence. If the sequence timer is allowed to expire during a page programming buffer load, the
internal control logic will terminate the programming operation and clear the software sequence detector
(indicated by status bit 5 in the instruction register). During a programming operation, data that has been loaded
into the internal page programming buffer is automatically transferred into the memory array.
operation initiation
The SCOPE Diary differs from typical software sequence-contrOlled memory devices because the selected
programming or erasing operation does not automatically begin at the end of the internal sequence time out.
To initiate the selected operation, the host must issue the BEGOPS command to the SCOPE Diary and enter
the Run-Test/Idle state before the internal sequence timer expires. If the timer expires, the internal sequence
detector will be cleared, and the selected operation must be re-initiated from the beginning. Status bit 6 in the
instruction register indicates a successful program or erase operation. This bit will be set within 2 ~s after the
BEGOPS instruction is executed.
TEXAS
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reset
The SCOPE Diary test bus logic is cleared either by internal circuitry at power-up, or by entry to the
Test-Logie-Reset state. All internal data scan path registers are set to logic 0, and the instruction register is
loaded with the IDCODE instruction. Entering the Test-Logie-Reset state will not clear a pending software
sequence or interrupt an executing self-timed program or erase cycle.
erase-verify mode
The erase-verify mode allows the host to verify the adequacy of erasure. Once the SCOPE Diary has been
placed in the verify mode, it will remain in that state (indicated in the instruction register when status bit 3 is a
logical 1) until the exit-verify mode sequence has been issued. When in the erase-verify mode, the internal
voltage applied to the read select lines (wordlines) is reduced by a preset margin. To verify that the array has
been erased, the host reads the memory block and checks that all bits are set to logic 1.
program-verify mode
The program-verify mode allows the host to verify the adequacy of programming. Once the SCOPE Diary has
been placed in the program-verify mode, it will remain in this state (indicated in the instruction register when
status bit 3 is a logical 1 ) until the exit-verify mode sequence has been issued. When in the program-verify mode,
the internal voltage applied to the read-select lines (wordlines) is increased by a preset margin. To verify that
a programming operation was successful, the host reads the previously programmed locations and checks that
the data values are correct.
JTAG extensions
DMAread
The DMA read mode allows any number of sequential bits to be read from the SCOPE Diary while remaining
in the Shift-DR state. During a DMA read operation, the contents of the memory array will be shifted out
beginning with the address location contained in the memory-address register. Upon entry to the Shift-DRstate,
an internal modulo 8 counter is triggered. This counter is used to increment the contents of the memory-address
register on byte boundaries. After the data from the last byte in the memory array has been read, the next data
will be read from the byte at the beginning of the memory array.
DMAwrite
The DMA write mode simplifies data transfer to the SCOPE Diary. This mode allows data to be continuously
streamed into the SCOPE Diary while remaining in the Shift-DR state. Compared to normal modes of data
transfer, the DMA write extensions enable systems with a large number of devices in the scan path to realize
a significant reduction of clock cycles.
In the DMA write mode, an internal modulo 24 counter is used to automatically transfer address/data pairs to
the memory core while bypassing the Update-DR state. To initiate a DMA write data transfer, the internal modulo
24 counter must be triggered (synchronized) when the first bit of an address/data pair is at the TDI input pin.
The SCOPE Diary supports two methods of DMA synchronization: state-transition mode and header mode. The
host determines which method of DMA synchronization is used.
state-transition mode
The host selects state-transition mode by clearing the header register (all bits to logic 0). When the
state-transition mode is selected, incoming scan path data is ignored during first entry to the Shift-DR state. The
first entry to Pause-DR indicates proper alignment at the TDI input pin of the first address/data pair. Re-entry
to the Shift-DR state triggers the modulo 24 counter and enables the address/data pair to be written to the
memory core. Address/data pairs can then be streamed continuously to the SCOPE Diary with internal transfers
occurring automatically on 24-bit boundaries.
TEXAS ~
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header mode
The host selects the header mode by loading the header register with a value from 01 h to FFh. When the header
mode is selected, incoming scan path data is ignored until a byte (matching the contents of the header register)
arrives indicating the arrival of valid address/data pairs. When this header byte is detected, the internal modulo
24 counter is triggered. Address/data pairs can then be streamed continuously to the SCOPE Diary with internal
transfers occurring automatically on 24-bit boundaries.
In either state-transition or header mode, the host places the SCOPE Diary in the Update-DRstateto end a DMA
write operation. Because placing the SCOPE Diary in the Update-DR state ends the operation, the host must
never place the SCOPE Diary in this state until the DMA write operation is complete. The host may place the
SCOPE Diary in the Pause-DR state at any time.
operation examples
Note that in this section, the letter "n" denotes a value from Oh to Fh, and the letter "x" denotes a don't care.
reading examples
reading using the byte mode
Step 1.
Load the BYTERD instruction.
= nnnn and 8-bit data =xx.
= nnnn and 8-bit data = nn.
Step 2.
Scan in 16-bit address
Step 3.
Scan out 16-bit address
reading using
Step 1.
Step 2.
Step 3.
Step 4.
the DMA mode
Load the LDADDR instruction.
Scan in 16-bit address nnnn.
Load the DMARD instruction.
Loop in Shift-DR to shift out a stream of 8-bit memory data values, the address register is
automatically incremented on byte boundaries.
=
lockbit examples
reading /ockbits using the byte mode
Step 1.
Load the SETLOCK instruction.
Step 2.
Load the BYTERD instruction.
Step 3.
Scan in 16-bit address =0000 and 8-bit data =xx.
Step 4.
Scan out 16-bit address =0000 and 8-bit data = Fn.
Step 5.
Load the CLRLOCK instruction.
reading /ockbits using the DMA mode
Step 1.
Load the SETLOCK instruction.
Step 2.
Load the DMARD instruction.
Step 3.
Scan out the 8-bit lock value = Fn.
Step 4.
Load the CLRLOCK instruction.
programming
Step 1.
Step 2.
Step 3.
Step 4.
Step 5.
Step 6.
Step 7.
Step 8.
/ockbits using the byte mode
Load the SETLOCK instruction.
Load the BYTEWR instruction.
Scan in address = 5555 and data = AA, go to Run-Test/Idle.
Scan in address = 2AAA and data =55; go to Run-Test/Idle.
Scan in address 5555 and data = AD; go to Run-Test/Idle.
Scan in address =0000, and data = Fn; go to Run-Test/Idle.
Load the BEGOPS instruction; go to Run- Test/Idle.
Load the CLRLOCK instruction.
TEXAS ~
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JTAG ADDRESSABLE STORAGE DEVICE
SGMS053-NOVEMBER 199o-REVISED JANUARY 1993
programming lockbits using the DMA mode
Step 1.
Load the SETLOCK instruction.
Step 2.
Load the DMAWR instruction.
Step 3.
Synchronize SCOPE Diary using either state-transition mode or header mode.
Step 4.
Loop in Shift-DR to scan in address =5555 and data =AA.
Step 5.
Continue looping in Shift-DR to scan in address =2AAA and data =55.
Step 6.
Continue looping in Shift-DR to scan in address =5555 an.d data =AD.
Step 7.
Continue looping in Shift-DR to scan in address = 0000 and data =Fn.
Step 8.
Load the BEGOPS instruction; go to Run- Test/Idle.
Step 9.
Load the CLRLOCK instruction.
flash erase examples
erasing a block using the byte mode
Step 1.
Load the ERABLK instruction.
Step 2.
Scan in the 4-bit erase-block-select value = n.
Step 3.
Load the BYTEWR instruction.
Step 4.
Scan in address =5555 and data =AA; go to Run-Test/Idle.
Step 5.
Scan in address =2AAA and data =55; go to Run-Test/Idle.
Step 6.
Scan in address = 5555 and data =80; go to Run-Test/Idle.
Step 7.
Scan in address = 5555 and data = AA; go to Run-Test/Idle.
Step 8.
Scan in address = 2AAA and data = 55; go to Run-Test/Idle.
Step 9.
Scan in address = 5555 and data = 10; go to Run-Test/Idle.
Step 10. Poll the SCOPE Diary until valid sequence is detected.
Step 11. Load the BEGOPS instruction; go to Run- Test/Idle.
erasing a block using the DMA mode
Step 1.
Load the ERABLK instruction.
Step 2.
Scan in the 4-bit erase-block-select value =n.
Step 3.
Load the DMAWR instruction.
Step 4.
Synchronize the SCOPE Diary using either state-transition mode or header mode.
Step 5.
Loop in Shift-DR to scan in address =5555 and data = AA.
Step 6.
Continue looping in Shift-DR to scan in address = 2AAA and data = 55.
Step 7.
Continue looping in Shift-DR to scan in address = 5555 and data = 80.
Step 8.
Continue looping in Shift-DR to scan in address = 5555 and data = AA.
Step 9.
Continue looping in Shift-DR to scan in address =2AAA and data = 55.
Step 10. Continue looping in Shift-DR to scan in address =5555 and data = 10.
Step 11. Poll SCOPE Diary until valid sequence is detected.
Step 12. Load the BEGOPS instruction; go to Run- Test/Idle.
verifying block erasure using the byte mode
select the erase-verify mode:
Step 1.
Step 2.
Step 3.
Step 4.
Load the BYTEWR instruction.
Scan in address =5555 and data =AA; go to Run- Test/Idle.
Scan in address = 2AAA and data = 55; go to Run-Test/Idle.
Scan in address =5555 and data =DO; go to Run- Test/Idle.
TEXAS
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INsrRUMENTS
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SMJ29F816
16 384·BIT SCOPE™ DIARY
JTAG ADDRESSABLE STORAGE DEVICE
SGMS053-NOVEMBER 1990-REVISED JANUARY 1993
read out the erased block:
Step 5.
Step 6.
Step 7.
Step 8.
Load the BYTERD instruction.
Scan in 16-bit address = nnnn and 8-bit data = xx.
Scan out 16-bit address =nnnnand 8-bitdata =FF; atthe sametime,scan in 16-bitaddress =nnnn+1
and data = xx.
Repeat Step 7 until entire block is read. All bits will be a logic 1 if the block is properly erased.
exit the erase-verify mode:
Step 9.
Step 10.
Step 11.
Step 12.
Load the BYTEWR instruction.
Scan in address = 5555 and data = AA; go to Run-Test/Idle.
Scan in address = 2AAA and data = 55; go to Run-Test/Idle.
Scan in address =5555 and data = FO; go to Run- Test/Idle.
verifying block erasure using the DMA mode
select the erase-verify mode:
Step 1.
Step 2.
Step 3.
Step 4.
Step 5.
Load the DMAWR instruction.
Synchronize the SCOPE Diary using either state-transition mode or header mode.
Loop in Shift-DR to scan in address = 5555 and data = AA.
Continue looping in Shift-DR to scan in address =2AAA and data =55.
Continue looping in Shift-DR to scan in address = 5555 and data = DO.
read out the erased block:
Step 6.
Step 7.
Step 8.
Step 9.
Load the LDADDR instruction.
Scan in 16-bit data starting address = nnnn of the block you want to verify.
Load the DMARD instruction.
Loop in Shift-DR to shift out a stream of 8-bit memory data values from the addressed block. All bits
will be a logic 1 if the block is properly erased.
exit the erase-verify mode:
Step
Step
Step
Step
Step
10.
11.
12.
13.
14.
Load the DMAWR instruction.
Synchronize the SCOPE Diary using either state-transition mode or header mode.
Loop in Shift-DR to scan in address =5555 and data =AA.
Continue looping in Shift-DR to scan in address =2AAA and data =55.
Continue looping in Shift-DR to scan in address =5555 and data =FO.
verifying programming using the byte mode
select the program-verify mode:
Step 1.
Step 2.
Step 3.
Step 4.
Load the BYTEWR instruction.
Scan in address =5555 and data =AA; go to Run-Test/Idle.
Scan in address = 2AAA and data = 55; go to Run-Test/Idle.
Scan in address = 5555 and data = BO; go to Run- Test/Idle.
read out the programmed data:
Step 5.
Step 6.
Step 7.
Step 8.
Load the BYTERD instruction.
Scan in 16-bit address =nnnn and 8-bit data =xx.
Scan out 16-bit address = nnnn + 1 and 8-bit data = nn; at the same time, scan in 16-bit
address=nnnn + 1 and data = xx.
Repeat Step 7 until desired memory locations are read and verified.
exit the program-verify mode
Step 9.
Step 10.
Step 11.
Step 12.
Load the BYTEWR instruction.
Scan in address =5555 and data =AA; go to Run-Test/Idle.
Scan in address = 2AAA and data =55; go to Run-Test/Idle.
Scan in address = 5555 and data = FO; go to Run-Test/Idle.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
9-303
SMJ29F816
16 384·BIT SCOPE™ DIARY
JTAG ADDRESSABLE STORAGE DEVICE
SGMS053-NOVEMBER 1990-REVISED JANUARY 1993
verifying programming using the DMA mode
select the program-verify mode:
Step 1.
Step 2.
Step 3.
Step 4.
Step 5.
Load the DMAWR instruction.
Synchronize the SCOPE Diary using either state-transition mode or header mode.
Loop in Shift-DR to scan in address = 5555 and data =AA.
Continue looping in Shift-DR to scan in address =2AAA and data =55.
Continue looping in Shift-DR to scan in address =5555 and data = BO.
read out the programmed data:
Step 6.
Step 7.
Step 8.
Step 9.
Load the LDADDR instruction.
Scan in 16-bit starting address =nnnn of the data you want to verify.
Load the DMARD instruction.
Loop in Shift-DR to shift out a stream of 8-bit memory data values starting from the addressed
location. Verify that the output data stream matches the programmed data.
exit the program-verify mode:
Step 10.
Step 11.
Step 12.
Step 13.
Step 14.
Load the DMAWR instruction.
Synchronize the SCOPE Diary using either state-transition mode or header mode.
Loop in Shift-DR to scan in address =5555 and data =AA.
Continue looping in Shift-DR to scan in address =2AAA and data =55.
Continue looping in Shift-DR to scan in address =5555 and data = FO.
programming examples
programming a single byte using the byte mode
Step 1.
Step 2.
Step 3.
Step 4.
Step 5.
Step 6.
Load the BYTEWR instruction.
Scan in address =5555 and data =AA; go to Run-Test/Idle.
Scan in address = 2AAA and data = 55; go to Run- Test/Idle.
Scan in address =5555 and data =AO; go to Run-Test/Idle.
Scan in address = nnnn and data = nn; go to Run-Test/Idle.
Load the BEGOPS instruction; go to Run-Test/Idle.
programming a single byte using the DMA mode
Step 7.
Step 8.
Step 9.
Step 10.
Step 11.
Step 12.
Step 13.
Load the DMAWR instruction.
Synchronize the SCOPE Diary using either state-transition mode or header mode.
Loop in Shift-DR to scan in address =5555 and data =AA.
Continue looping in Shift-DR to scan in address =2AAA and data =55.
Continue looping in Shift-DR to scan in address = 5555 and data = AO.
Continue looping in Shift-DR to scan in address =nnnn and data = nn.
Load the BEGOPS instruction; go to Run-Test/Idle.
programming a page using the byte mode
Step 1.
Step 2.
Step 3.
Step 4.
Step 5.
Step 6.
Step 7.
Load the BYTEWR instruction.
Scan in address = 5555 and data = AA; go to Run- Test/Idle.
Scan in address =2AAA and data =55; go to Run-Test/Idle.
Scan in address = 5555 and data = AO; go to Run-Test/Idle.
Scan in address = nnnn and data =nn; go to Run-Test/Idle.
Go to Step 5 while there are address/data pairs to load within the 32-byte page.
Load the BEGOPS instruction, go to Run- Test/Idle.
TEXAS ~
INSTRUMENTS
9·304
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
SMJ29F816
16 384-BIT SCOPE™ DIARY
JTAG ADDRESSABLE STORAGE DEVICE
SGMS053-NOVEMBER 1990-REVISED JANUARY 1993
programming a page using the DMA mode
Step 1.
Load the DMAWR instruction.
Step 2.
Synchronize the SCOPE Diary using either state-transition mode or header mode.
Step 3.
Loop in Shift-DR to scan in address = 5555 and data =AA.
Step 4.
Continue looping in Shift-DR to scan in address =2AAA and data = 55.
Step 5.
Continue looping in Shift-DR to scan in address = 5555 and data = AD.
Step 6.
Continue looping in Shift-DR to scan in address nnnn and data nn.
Step 7.
Go to Step 6 while there are address/data pairs to load within the 32-byte page.
Step 8.
Load the BEGOPS instruction; go to Run-Test/Idle ..
=
=
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage, Vee (see Note 3) ................................................... - 0.6 V to 7 V
Input voltage range: All except DLA (see Note 3) ..................................... - 0.6 V to 6.5V
Input voltage range: DLA (see Note 3) .............................................. - 0.6 V to 15 V
Output voltage (see Note 3) ................................................. - 0.6 V to Vee + 0.6V
Operating free-air temperature range .............................................. - 55°C to 125°C
Storage temperature range ....................................................... - 65°C to 125°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 3: Voltage values are with respect to GND (substrate).
recommended operating conditions
MIN
Vee
Supply voltage
VIH
High-level input voltage
VIL
Low-level input voltage
TA
Operating free-air temperature
NOM
4.5
TTL
CMOS
TTL
CMOS
5.5
2
Vee + 1
Vee- O.2
Vee + 0.2
-0.5
0.8
GND-0.2
GND + 0.2
-55
Endurance cycles
MAX
5
125
UNIT
V
V
V
°e
1000
Programming operations
100000
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
9-305
SMJ29F816
16 384·BIT SCOPE™ DIARY
JTAG ADDRESSABLE STORAGE DEVICE
SGMS05a-NOVEMBER 199G-REVISED JANUARY 1993
electrical characteristics over full ranges of recommended operating conditions (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
VOH
High-level output voltage
10H =-2mA
VOL
Low-level output voltage
10L = 2.1 mA
OLA,OLB
VI = 2.4 V
MIN
TYpt
MAX
2.4
UNIT
V
0.4
75
165
-10
-50
V
OLA,OLB
VI =OV
TOI, TMS, TCK
VI=0.4
TOI, TMS, TCK
VI = Vee = 5.5 V
±10
Vo = 0.1 to VCC
±10
J.tA
tcvcl e = 160 ns, outputs open
20
mA
tcycle = 15 ms
15
mA
II
Input current (leakage)
10
Output current (leakage)
ICC1
VCC average supply current (active read)
ICC2
VCC average supply current (active write)
:t10
J.tA
t TYPical values are at TA = 25°C and nom mal voltages.
capacitance over recommended ranges of supply voltage and operating free-air temperature,
f = 1 MHz:!:
PARAMETER
TEST CONDITIONS
MIN TYpt
MAX
UNIT
CI
Input capacitance
VI = 0, f = 1 MHz
4
7
pF
Co
Output capacitance
Vo = 0, f = 1 MHz
8
12
pF
t TYPical values are at TA = 25°C and nom mal voltage.
*
CapaCitance measurements are made on sample basis only
switching characteristics over full ranges of recommended operating conditions
MIN
PARAMETER
MAX
UNIT
tOA
TOO valid from falling edge of TCK
74
ns
toz
TOO disable time from falling edge of TCK
45
ns
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
MIN
MAX
UNIT
tcvc
TCK cycle time
tw(TCKH)
Pulse duration, TCK high
50
ns
tw(TCKL)
Pulse duration, TCK low
70
ns
tSU(TMS)
TMS input setup time
15
ns
tIH(TMS)
TMS input hold time
5
ns
tSU(TOI)
TOI input setup time
6
ns
tIH(TOI)
TOI input hold time
15
ns
160
TEXAS
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INSTRUMENTS
9-306
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
ns
SMJ29F816
16 384·BIT SCOPE™ DIARY
JTAG ADDRESSABLE STORAGE DEVICE
SGMS053--NOVEMBER 1990-REVISED JANUARY 1993
Internal timing requirements
PARAMETER
MIN
MAX
UNIT
tsss
Software sequence status bit valid from software sequence
2
tPEBS
Program erase busy status bit valid from BEGOPS execution
2
~s
tST
Sequence timer limit
6
ms
tERA
Erase cycle time
15
ms
15 ,
ms
Program cycle time
, tpGM
,
~s
,
PARAMETER MEASUREMENT INFORMATION
2.08V
RL = 800
Q
Output
Under Test
T
CL=30pF
Figure 5. AC Test Output Load Circuit
AC testing input/output wave forms
2.4 V
0.4V
-------X ~.~v
O.~ ~
_ ___-'
X'--___
AC testing inputs are driven at 2.4 V for logic high and 0.4 for logic low. Timing measurements are made at 2 V for
logic 1 and 0.8 V for logic 0 for both inputs and outputs. Each device should have a 0.1 !-IF ceramic capacitor connected
between Vee and GND as close as possible to the device pins.
~~---- tCYC ----~.I
TCK
~~----I:
i\-----,,-----------------I
+I----l4I
..----~.1 1
1
tW(TCKH)
I
I
INPUT
~:X:
~
1
1
[4TOO
1
1
toz
--+i
~
1
1
.1
1'1
tW(TCKL)
X-......---:
--i
tsu t
I
1
I
j4-- tlH* ~
I
I
.r--~~-
tOA
_____)r--------~(==============
t tsu represents TDI input setup time and TMS input setup time.
* tlH represents TDI input hold time and TMS input hold time.
TEXAS
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INSTRUMENTS
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SMJ29F816
16 384·BIT SCOPE™ DIARY
JTAG ADDRESSABLE STORAGE DEVICE
SGMS053-NOVEMBER 199Q-REVISED JANUARY 1993
TEXAS ~
INsrRUMENTS
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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
Logic Symbols
10-1
10-2
Logic Symbols
EXPLANATION OF IEEE/IEC LOGIC SYMBOLS FOR MEMORIES
Introduction
The International Electrotechnical Commission (IEC) has developed a very powerful symbolic language that
can show the relationship of each input of a digital logic circuit to each output without showing explicitly the
internal logic. At the heart of the system is dependency notation, which will be partially explained below.
The system was introduced in the USA in a rudimentary form in IEEE/ANSI Standard Y32.14-1973. Lacking at
that time a complete development of dependency notation, it offered little more than a substitution of rectangular
shapes for the familiar distinctive shapes for representing the basic functions of AND, OR, negation, etc. This
is no longer the case.
The current standards are IEC Publication 617-12, 1983, and ANSI/IEEE Standard 91-1984. Most of the data
sheets in this data book include symbols prepared in accordance with these standards. The explanation that
follows is necessarily brief and greatly condensed from the explanation given in the standards. This is not
intended to be sufficient for people who will be developing symbols for new devices. It is primarily intended to
make possible the understanding of the symbols used in this book.
Explanation of a Typical Symbol For a Static Memory
The TMS27C400 symbol will be explained in detail. This symbol includes almost all the features found in the
OTP PROMs and EPROMs.
The address inputs are arranged in order of their assigned binary weights and the range of addresses are shown
as A W- where m is the decimal equivalent of the lowest address and n is the highest. The outputs affected by
these addresses are indicated by the letter A, as data inputs would also be if the device were a RAM.
The polarity indicator t:>. indicates that the external low level causes the internal1-state (the active or asserted
state) at an input or that the internal1-state causes the external low level at an output. The effect is similar to
specifying positive logic and using the negation symbol o.
The TMS27C400 Symbol
AO
Al
A2
A3
A4
A5
A6
A7
A8
A9
Al0
All
A12
A13
A14
10
9
8
7
6
5
4
3
25
24
21
23
2
26
27
0
0
A 32767
A'V
A'V
A'V
A'V
A'V
A'V
A'V
A'V
11
12
13
15
16
17
18
19
DQl
DQ2
DQ3
DQ4
DQS
DQ6
DQ7
DQ8
14
20
22
EPROM
32768x8
The 'V symbols indicate three-state outputs.
Three-state outputs will always be controlled by an EN
function. When EN stands at its internal 1-state, the
outputs are enabled; when EN stands at its internal
O-state, the outputs stand at their high-impedance
states. Sometimes the EN is a single input, but in the
illustrated case, it is the output of a two-input AND
gate. Both inputs (pins 20 and 22) are active low, so
if either one of them goes high, the outputs will be
disabled. The upper one of these two inputs (pin 20)
has another function. When nonstandard labels and
explanatory labels are used within symbols, they are
enclosed within square brackets. Here we find the
label "[PWR OWN]". This is intended to indicate that
if pin 20 is high, the memory will go to a low-power
standby state.
T "-
~
[PWRDWNj
~
EN
TEXAS
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INSlRUMENlS
POST OFFICE BOX 1443· HOUSTON, TEXAS 77001
10-3
Logic Symbols
The Basics
The next section illustrates the most common building blocks that are used in constructing symbols for
memories. On the left are shown the symbols that specify the active levels for level-operated inputs, and the
direction of active transition for dynamic inputs ..
It is preferred to show all input lines on the left and all output lines on the right. When an exception is made to
this left-to-right Signal flow, an arrowhead is used to show the reverse signal flow. Three symbols are shown that
indicate three-state, open-drain, and open-source outputs. If none of these are used, the output should be
assumed to be totem-pole. The common control block is a point of replacement for inputs that affect an array
of elements.
The drawings on the right define the three forms of dependency notation used in this book. At an input (or output)
that affects other inputs or outputs, a letter (G, C, or 2) is placed followed by a number. That same number is
placed at the affected inputs and outputs. The letter G indicates that an AND relationship exists; if the affecting
input stands at the a-state, it imposes that a-state on the affected input or output. The letter C indicates a control
relationship, usually between clock and a D (data) input. If the C input stands at its a-state, the affected input
is disabled. A D input is always an input to a storage element, which it either sets to the 1-state or resets to the
a-state, unless the D input is disabled to have no effect. 2 dependency is used to transfer a signal from one place
in a symbol to another, for example from the output at 24 across to a terminal labeled "4", or from the output
at 25 back to the "5" where it serves as an input with no terminal attached.
TEXAS -If
INSTRUMENTS
10-4
POST OFFICE BOX 1443' HOUSTON. TEXAS 77001
Logic Symbols
Diagrammatic Summary
G (AND) DEPENDENCY
INPUTS
.=+~-
Active H (high)
b
Active on L-to-H transition
Active on H-to-L transition
5
a
a
b
b
'=t '
d
5
&
ab
&
ac
&
ad
-c
d
d
C(CONTRO~DEPENDENCY
INPUT/OUTPUT
[STORAGE]
&
a -+--4"""--1
&
S [Set]
R [Reset]
b
Z (INTERCONNECTION) DEPENDENCY
OUTPUTS
---
Active high
Active lowt
...
1'-.....::...--
3-State \l 1 - - - Open-Circuit (L-type)* Q 1--_ _
aiS ZS!
~4+
a
Open-Circuit (H-type)1I <::> 1--_ _
--COMMON CONTROL BLOCK
a
a
t The active-low indicator may be used in combination
with the 3-state and open-circuit indicators.
*L-types include N-channel open-drain and P-channel
b
open-source outputs.
II H-types include P-channel open-drain and N-channel
open-source outputs.
b
c
d
c
d
TEXAS
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INSTRUMENTS
POST OFFICE BOX 1443· HOUSTON, TEXAS 77001
10-5
logic Symbols
Explanation of a Typical Symbol for a Dynamic Memory
The TMS4C1 024 symbol will be explained in detail for each
operating function. The assumption is made that the previous
sections have been read and understood. While this symbol
is complex, so is the device it represents and the symbol
shows how the part will perform depending on the sequence
in which signals are applied.
The TMS4C1 024 Symbol
5
AO
6
Al
7
S
A2
A3
A4
AS
AS
A7
AS
A9
RAM 1024Kx1
20010/2100
10
11
A 1
~575
12
13
14
15
CAS
3~
16~
Vi
2~
o
1
20019/2109
C20[ROW]
G23/[REFRESH ROW]
24[PWR OWN]
C21[COL]
G24
&
23,210
A,220
23C22
24EN
A'V
r-!?-
Q
Addressing
The symbol above makes use of an abbreviated from to show the multiplexed, latched addresses. The blocks
representing the address latches are implied but not shown.
AO
A1
A2
A3
A4
A5
A6
A7
A8
A9
RAS
CAS
20010/2100
A __
O_
1048575
r--- I> C21
CAS
AO
A1
A2
A3
A4
A5
A6
A7
A8
A9
RAS
~
1----
r--t----
r--r--I--t---I--t---I'-
-
~
20019/2109
C20
C21
I>c2o
0
1
2
3
4
5
6
7
8
9
~ 10
t----
0
A 1 048575
11
12
13
-14
-15
16
17
18
19
-
I---
When RAS goes low, it momentarily enables (through C20, [> indicates a dynamic input) the D inputs of the ten
address registers 10 through 19. When CAS goes low, it momentarily enables (through C21) the D inputs of the
ten address registers 0 through 9. The outputs ofthe address registers are in 20 internal address lines that select
1 of 1 048 576 cells.
TEXAS ."
INSlRUMENlS
10-6
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
Logic Symbols
Refresh
RAS
-1
When RAS goes low, row refresh starts. It ends when RAS goes
high. The other input signals required for refreshing are not
indicated by the symbol.
[REFRESH ROW]
Power Down
RAS
CAS
--1
--i
CAS is ANDed with RAS (through G24) so when RAS and CAS
are both high, the device is powered down.
24 [PWR OWN]
G24
Write
By virtue of the AND relationship between CAS and W(explicitly
shown), when either one of these inputs goes low with the other
one and RAS is already low (RAS isANDed byG23), the D input
is momentarily enabled (through C22). In an "early-write" cycle
it is W that goes low first; this causes the output to remain off as
explained below.
23C22
Read
CAS ----t......-'-'''t> C21
G24
RAS
W
24EN
A\l - - -
Q
The ANDed result of RAS and W (produced by G23) is
clocked into a latch (through C21) at the instant CAS
goes low. This result will be "1" if RAS is low and W is
high. The complement of CAS is shown to be ANDed
with the output of the latch (by G24 and 24). Therefore,
as long as CAS stays low, the output is enabled. In the
"early-write" cycle referred to above, a "0" was stored in
the latch by W being low when CAS went low, so the
output remained disabled.
IEEE Standards may be purchased from:
Institute of Electrical and Electronics Engineers, Inc.
345 East 47th Street
New York, New York 10017
International Electrotechnical Commission (lEG) publications may be purchased from:
American National Standards Institute, Inc.
1430 Broadway
New York, New York 10018
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443· HOUSTON. TEXAS 77001
10·7
Logic Symbols
TEXAS ."
INSTRUMENTS
10-8
POST OFFICE BOX 1443· HOUSTON, TEXAS 77001
Q_u_a_l_ity_a_"d_R_e_li_ab_i_li_ty_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
,_,_
L -_ _ _
11-1
11-2
Quality and Reliability
MOS MEMORY QUALITY AND RELIABILITY STRATEGY
Texas Instruments is committed to providing its customers with reliable, high quality memory products. MOS
Memory management has applied a four point quality and reliability strategy to:
• Provide customers with the lowest cost of product ownership through quality, reliability, and service by:
- On-time delivery to minimize customer inventory.
- Quality performance that justifies ship-to-stock certification and eliminates the cost of component testing.
- No system manufacturing fallout.
- No warranty and service costs.
• Develop partnership relationships to service and solve customer problems and anticipate upcoming needs.
• Live quality improvement process from product creation and manufacturing through product sales via our total
quality control approach of:
- Quality Function Deployment.
- Design-in and build-in quality and reliability.
-In-control manufacturing.
- Leadership customer service.
• Measure TI's performance by the customer's measurement and perception. The performance standard is continuous customer satisfaction.
Total Quality Control (TQC)
Total Quality Control at TI is a business management process encompassing all company functions. The goal
of Total Quality Control (TQG) is continuous customer satisfaction. Utilizing a process of improvement through a positive feedback cycle, TQC is deployed in the MOS Memory Division from the initial design-in Q&R stage, in-control
manufacturing, and customer service (see Figure 1).
Proper application ofthe concept of "PLAN-DO-CHECK-ACT" allows a positive feedback loop that creates continuous improvement and breakthrough, as opposed to the "FIX-FIX-FIX-FIX" results of a negative loop (see Figure 2).
Quality Function Deployment
Continuous customer satisfaction can be achieved only by fully understanding customer needs, then introducing
innovative products that satisfy those needs. Quality Function Deployment (QFD) accomplishes both purposes at TI.
QFD is a technique that systematically records the voice of the customer, identifying product and service attributes
most important to the customer. QFD then blends these needs with the talents and innovations of a TI design team
to define a manufacturable, reliable product solution for the customer.
DesIgn-In Quality and Reliability
Quality and reliability improvements at TI start with the chip and package design. The objective of MaS Memory's
Design-I n Quality and Reliability (D IR) thrust is first-pass qualification of new products, internally and at the customer.
The TI approach to DI R has been to understand customer requirements of a product, and to formalize this knowledge
into a database that incorporates both reliability modeling knowledge, and "lessons learned" from historical problems
and engineering evaluations. Before any new design is approved, the design is verified against a DIR "checklist". Design verification is planned to evolve to computer verification utilizing artificial intelligence.
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11·3
Quality and Reliability
PLAN
00
Understand
Customer
Care..bouta
Product
Specification
Deline
Rsqulrements
Design rule8/
Package
Capability
CHECK Customer
Survey
Process
Assurance
ACT
Analysls/
Improvement
Improve
Design
establish
Baseline
Document/Audlt/
Control
Through
Standards/SPC
Measure/Assess
Through
Reliability
Testing
Product/Process
Improvement
Understand Needs
Service - On-time
Delivery,
JIT(Just In Time),
Ship-To-Stock,
Joint Qualification
Support - Field
Through Factory
Verily - Feedback
With Customer
Assessment
Figure 1. Total Quality Control
From Negative Loop
To Positive Loop
Figure 2. TQC Philosophy
In-Control Manufacturing
Documentation/Audit System
To assure in-control manufacturing, TI employs a hierarchical specification system. General specifications on all
aspects of quality, reliability, and customer service are written and controlled by the central Quality and Reliability
group. More detailed specifications control the operating practices of deSign, manufacturing, marketing, and other
support organizations. These specifications follow guidelines set by the higher-level specifications, but concentrate
on the type of business entity.
Regularly scheduled audits are performed within TI to ensure compliance with all specifications. The five types
of audits performed are:
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11-4
POST OFFICE BOX 1443· HOUSTON, TEXAS n001
Quality and Reliability
1. Self audit: An internal audit within each functional operation. This type of audit is conducted by persons within the
operation and an additional person from outside the operation.
2. Cross-audit: An audit by persons independent of the operation being audited.
3. Group audit: An audit of an operation conducted by the Semiconductor Group audits and procedures function,
which is a part of the central Quality and Reliability organization.
4. Procedures audit: An audit of lower-level specifications with respect to higher-level specifications.
5. Compliance audit: An audit of operating practices with respect to specifications.
Statistical Process Control (SPC)
Quality improvement is achieved through Statistical Process Control (SPC). SPC is applied throughout the
manufacturing operations of the MOS Memory division. The objectives of SPC are:
- Control processes on a realtime basis.
-Improve process capability (CP).
- Reduce variability to target value (CPl<).
- Eliminate "out-of-spec" lots.
- Achieve dependable delivery.
- Lower cost-of-quality.
Computer hardware and artificial intelligence software have been coupled to establish interactive control allowing
the computer to generate realtime control charts and prompt adjustments to equipment and processes
(see Figure 3).
Identify Problems and
Data Collection
- Pareto of Defects
U
L...------....J
Training
- SPC
- Design of Experiments
Identify Source of Variation
- Multi-Variable Chart
- Fish-Bone
D
Control Charts
- Control to Target
- Reduce Variability
<,-------'
Capability Studies
- Process Spread
- Spec Spread
Figure 3. Computer-Aided Statistical Process Control
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11-5
Quality and Reliability
Die Fabrication Control
In addition to extensive SPC applications in our MaS fabrication centers, TI implements wafer-level quality and
reliability controls.
Wafer-level quality control focuses on reduction of variability around target values (CPK) for key functionality parameters and controls the processes that affect these parameters. For example: Column access time (tcAd is a key
DRAM parameter. One of the die manufacturing processes that affects tCAC is the photo etch. To reduce variability
of the target value of tCAC, we control polysilicon width dimension at the photo etch process.
Wafer-level reliability controls address process control of known reliability hazards. For example: Excessive
phosphorus use in die processing can lead to corrosion defects in the finished device. Wafer-level reliability controls
require that phosphorus level control is built into the manufacturing process and that action is prescribed for out-ofcontrol material. Other wafer-level reliability controls are shown in the following table.
Table 1. Wafer Reliability Controls
PARAMETER
CONTROL
Metal
Electromigration Testing, Grain Size, Silicon Nodule Monitor
Step Coverage/Metal Necking Monitor
Stress-Induced Metal Void Testing
Protective Overcoat
P.O. Integrity
Stress Testing
Thickness Monitor
Refraction
"
Corrosion
% Phosphorus In Multilevel Oxide Monitor
Gate Oxide Integrity
Breakdown Voltage
Device Assembly Control
TI has also implemented assembly level reliability controls and SPC at critical assembly points (see Table 2) to
ensure highly reliable device packaging. Each parameter has certain controls performed at appropriate frequencies
to ensure that assembly processing is at qualified levels. Controls may be added or reduced after extensive testing
has been performed. Results are carefully studied and fed back to preclude reliability problem introduction into the
assembly process. Some of the parameters and controls are shown in Table 3.
Table 2. Major Assembly Steps Using SPC/SQct
PLASTIC DEVICE ASSEMBLY
Process.
Mount
Control Parameter
% Coverage of Epoxy
Bond
Bond Strength
Mold
Temperature and Molding Parameters
Trim/Form
Lead Deflection (DIP)
CERAMIC DEVICE ASSEMBLY
Bond
Bond Strength
Seal
Seal Furnace Temperature
tStatistical Process Control/Statistical Quality Control
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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
Quality and Reliability
Table 3. MOS Memory Assembly Level Reliability Controls
PARAMETER
CONTROL
P.O. Integrity
Contactless Wafer Mount on Tape Die Mount System
Mold Compound Parameters
Chip/Crack
Visual Inspection
Temp Cycle
Saw Blade Conditions
Poker Pin Height
Wet Etch Monitor (EPROM)
Bond Integrity
Bond Strength Monitor
Bond Parameters
Bake/Bond Pull Monitor
Capillary Change
Package Integrity
Visual Inspection
Mold Press Parameters (Plastic)
X·Ray Inspection (Plastic)
Trim/Form (Plastic)
Package Seal (Ceramic)
Temp Cycle (Ceramic)
Hermeticity Monitor (Ceramic)
Die Mount Integrity
Die·Shear Monitor
Centrifuge Monitor
X·Ray Inspect
Leadframe Poly imide Pattern Inspect
Pick·Up Arm Force
Contamination
Visual Inspection
Product Assessment/Improvement
Reliability Control System
The MOS Memory reliability control system (Figure 4) provides closed-loop-system feedback resulting in corrective actions and ongoing product improvements. Each new product, process, or major change to an existing product
is internally qualified to industry leadership standards prior to production. This is followed by intensive monitoring
during production ramp-up and reliability monitoring each month, once a product achieves final production release.
Reliability Development Issues
Soft Error: TI does extensive work in all phases of device development to minimize the effects of soft errors. Soft
errors are caused by alpha particles emitted by the decay of small amounts of thorium and uranium located in device
packaging materials. TI maintains an aggresive program of evaluating new mold compounds to ensure low alpha emmissivity. Certain device design and processing techniques are also applied to ensure a low soft error rate. The goal
of device design and processing is to maximize the cell capacitance by employing an oxide-nitride dielectric, as opposed to an oxide dielectric. Also, the cell capacitance increases as the dielectric thickness decreases. Testing has
shown that the trench capacitor used in dynamic RAMs has competitive soft error rates.
Channel Hot Electron: Channel hot electrons are caused by impact ionization in the drain pinch-off region.
Electrons are accelerated toward the drain, collide with positive ions, and can be trapped in the gate oxide. This
trapped charge can change the characteristics of the transistor by raising the Vr (threshold voltage). One method
employed to reduce the effects of hot electrons is to add a lightly doped drain to reduce the electric field at the gate.
Testing for channel hot electrons is performed at a low temperature (-1 DOC) and a high drain voltage.
Latch-up: A CMOS device can latch-up when the gain of the parasitic PNP+NPN transistors is greater than 1.
These PNP+NPN transistors act as a silicon controlled rectifier (SCR). If enough current flows through the resistors,
the transistors will turn on and the device will latch-up.
To control latch-up, the SCR gain must be controlled to less than or equal to one. Methods for improving latch-up
immunity include incorporating guard rings between P+ and N+ diffusions, and isolating P+ and N+ diffusions.
Latch-up testing is performed to ensure our CMOS devices meet the minimum holding current for industry
standards.
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11-7
Quality and Reliability
Customer Service
Quality, Reliability, Service, and the Cost of Ownership
The goal of Texas Instruments is to offer the best quality, reliability, and service in the semiconductor industry.
The foundation for this approach is to ship consistent quality. Consistent quality allows ship-to-stock programs that
foster the elimination of the customer's incoming inspection. Ship-to-stock quality, coupled with 100% on-time delivery to narrow shipping windows means support of the customer's just-in-time manufacturing program. This combination of quality, reliability, and service can be measured by a single index called "the cost of ownership". The "cost of
ownership" is defined as being composed of the purchase price, quality adders (for incoming inspection and board
rework), inventory adders (for maintenance of a buffer inventory for suppliers who cannot meet just-in-time delivery),
in-house reliability adders (for system burn-in and rework), and field reliability adders (for warranty and post-warranty
field repairs).
For more information about the cost of ownership concept, contact your local TI sales office and request the
brochure "Texas Instruments Lowers Semiconductor Cost of Ownership", SSYB057.
Quality Improvement
Significant improvement in product quality has been achieved through:
- Better definition of customer's requirements.
- Greater emphasis on quality as a design criterron.
- Improved control of incoming materials.
- Intensive training of supervisors and operators.
- Extensive use of statistical process control.
- More automation of operations to minimize operator-related defects.
QUALIFICATION
PRODUCTION RAMP LOT ACCEPT
Baseline process
Baseline process
3 - 6 diffusion lots
Worst
case
requirements
customer
TESTS
125'C Op life
EFRt
85/85
Temperature cycle
Pressure cooker test
PSP/PVP*
Static bias/storage
Soft error
Data retention bake
Electromigration
Package integrity
ESD
q ualificalion
Reliability lot acceptance concurrent with
qualifications
Review of data once sufficient lots have been
sampled
Ongoing reliability monitor of 125'C op life,
data retention bake, temperature cycle,
85/85, autoclave, package integrity, and
internal cavity moisture
Control limits for each test based on product
capability
TESTS
Early Failure Rate t
High temperature reverse bias§
Temperature cycle
Pressure cooker test
Bake
85/85§
t DRAM - 125'C OPL, 80 hours
EPROM & OTP - 200'C bake, 44 hours (OTP in ceramic package)
; PSP: Pressure cooker, Solder dip, Pressure cooker
PVP: Pressure cooker, Vapor phase, Pressure cooker
§ Non-Volatile only
Figure 4. Reliability Control System
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11-8
FINAL PRODUCTION RELEASE
Control each package/wafer fabrication
site/device combination
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
Early failure rate monitor
Quality and Reliability
As is demonstrated in Figure 5, MOS Memory EPROM and DRAM outgoing quality has dramatically improved
during the last few years. This significant improvement has occurred for all TI product lines and has been recognized
publicly by many of our customers, who have given TI more than 70 major quality awards in the last several years.
Included among these awards are Ford's Q-1 and TQE Awards, the U.S. Naval Quality Award, and the Deming Prize,
which is Japan's most prestigious quality award.
Reliability Improvement
Low IC failure rates are achieved through design-in reliability, computer aided design, stringent qualification testing prior to product release, routine monitoring of released products, and an extensive failure mode tracking and
feedback system for IC failures.
Each generation of MOS Memory products has exhibited a device failure rate improvement trend, and each new
generation shows a step function improvement in quality and reliability over the previous generation (see Figures 5
and 6). Even though the memory device complexity increases in an ongoing manner, Tl's failure rate by function has
improved at an even faster pace. TI continues to emphasize reliability improvement as a major factor in reducing the
total cost of ownership for our customers. Reliability improvement is reflected as a reduction in the expected field failures during system lifetime.
Up-to-date quality and reliability data for MOS Memory products is available. Please contact your local TI sales
office for information.
EFR LEARNING CURVE
300
64K
\
256K
\
\
200
1M
,
,
,,
~,
~
~.
100
••••••
4M
, . ---.,
"
.'...
-----
,
" ' .....
.... ----~
,~
~~
,
~ ........... •\
•
.......
oL-~~--~~--~~--~~--~~
o
3
2
4
5
Years
Figure 5. MOS Memory Quality Improvement
. TEXAS
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11-9
Quality and Reliability
AOQ LEARNING CURVE
~
a.
a.
Years
Figure 6. MOS Memory Reliability Improvement
650
EPROM
600
550
500
450
400
350
III
t: 300
II.
250
200
150
100
50
DRAM
O+----------.----------.----------r---------.----------,---------~
1983
1984
1985
1986
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11-10
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
1987
1988
1989
Electrostatic Discharge Guidelines
12-1
12-2
Guidelines for Handling Electrostatic-Discharge-Sensitive (ESDS)
Devices and Assemblies
Scope
This specification establishes the requirements for methods and materials used to protect electronic parts, devices, and assemblies (items) that are susceptible to damage or degradation from electrostatic discharge (ESD). The
electrostatic charges referred to in this specification are generated and stored on surfaces of ordinary plastics, most
common textile garments, ungrounded person's bodies, and many other commonly unnoticed static generators. The
passage of these charges through an electrostatic-sensitive part may result in catastrophic failure or performance
degradation of the part.
The part types for which these requirements are applicable include, but are not limited to, those listed:
1.
2.
3.
4.
5.
6.
7.
All metal-oxide semiconductor (MOS) devices; e.g., CMOS, PMOS, etc.
Junction field-effect transistors (JFET)
Bipolar digital and linear circuits
Op-amps, monolithic microcircuits with MOS compensating networks, on-board MOS capacitors, or
other MOS elements
Hybrid microcircuits and assemblies containing any of the types of devices listed
Printed circuit boards and other types of assembly containing static-sensitive devices
Thin-film passive devices
Definitions
1.
2.
3.
4.
5.
6.
7.
8.
Electrostatic Discharge (ESD): A transfer of electrostatic charges between bodies at different electrostatic potentials caused by direct contact or electrostatic field induction.
Conductive material: Material having a surface resistivity of 105 Q/square maximum.
Static dissipative material: Material having a surface resistivity between 105 and 109 Q/square.
Antistatic material: Material having a surface resistivity between 109 and 10 14 Q/square
Surface resistivity: An inverse measure of the conductivity of a material and is the resistance of unit length
and unit width of a surface. Note: Surface resistivity of a material is numerically equal to the surface resistance between two electrodes forming opposite sides of a square. The size of the square is immaterial.
Surface resistivity applies to both surface and volume conductive materials and has the dimension of
Q/square.
Volume resistivity: Also referred to as bulk resistivity. It is normally determined by measuring the resistance (R) of a square of material (surface resistivity) and multiplying this value by the thickness (T).
Ionizer: A blower that generates positive and negative ions, either by electrostatic means or from a radioactive energy source in an airstream, and distributes a layer of low velocity ionized air over a work area
to neutralize static charges.
Close proximity: For the purpose of this specification, 6 inches or less.
Device Sensitivity per Test Circuit of Method 3015, MIL-STD·883C
1. Devices are categorized according to their susceptibility to damage resulting from electrostatic discharges (ESD).
Category
ESD Sensitivity
Class 1
OV-1999V
Class 2
2000 V - 3999 V
Class 3
4000 V and above
2. Devices are to be protected from ESD damage from receipt at incoming inspection through assembly,
test, and shipment of completed equipment.
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12-3
Guidelines for Handling Electrostatic-Discharge-Sensitive (ESDS)
Devices and Assemblies
Applicable Reference Documents
The following reference documents (of latest issue) can provide additional information on ESD controls.
1.
2.
3.
4.
5.
6.
7.
8.
MIL-M-38510 Microcircuits, General Specification
MIL-STD-883 Test Methods and Procedures for Microelectronics
MIL-STD-19491 Semiconductor Devices, Packaging of
MIL-M-55565 Microcircuits, Packaging of
DOD-HDBK-263 Electrostatic Discharge Control Handbook for Protection
DOD-STD-1686 Electrostatic Discharge Control Program
NAVSEA SE 003-11-TRN-010 Electrostatic Discharge Training Manual
JEDEC Standard Publication 108
Facilities for Static-Free Workstation
The minimum acceptable static-free workstation shall consist of the work surface covered with static dissipative
material attached to ground through a 1 MQ:!: 10% resistor, an attached grounding wrist strap with integral 1 MQ:!:
10% resistor for each operator, and air ionizer(s) of sufficient capacity for each operator. The wrist strap shall be connected to the static dissipative material. Ground shall utilize the standard building earth ground; refer to Figure 1. Conductive floor tile/carpet along with conductive shoes may be used in lieu of the conductive wrist straps for non-seated
personnel. The Site Safety Engineer must review and approve all electrical connections at the static-free workstation
prior to its implementation.
Air ionizers shall be positioned so that the devices at the static-free workstations are within a 4-foot arc measured
by a vertical line from the face of the ionizer and 45 degrees on each side of this line.
General grounding requirements are to be in accordance with Table 1 .
!
R
Chair
with Ground
(optional)
Personal
Ground
Strap
!
ESD Protective
Trays, etc.
Static
Dissipative
Table
Top
Ionizer
R
All electrical equipment sitting on the conductive table top must be hard grounded but must be isolated from the static disspative work surface.
NOTE: Earth ground is not computer ground or RF ground or any other IimHed-type ground.
Figure 1. Static-Free Workstation
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Guidelines for Handling Electrostatic-Discharge-Sensitive (ESDS)
Devices and Assemblies
Table 1. General Grounding Requirements
Treated With Antistatic
Solution or Made of
Conductive Material
Handling EquipmenV
Handtools
Grounded to
Common Point
Static Dissipative
Material
X
X
Metal Parts of Fixtures and
Tools/Storage Racks
X
Handling Trays{Tubes
X
X
Soldering Irons/Baths
X
X
Table Tops/Floor Mats
X
X
X Using Wrist Strap·
Personnel
• With 1 MQ ± 10% resistor
Usage of Antistatic Solution in Areas to Control the Generation of Static Charges
The use of antistatic chemicals (antistats) should be a supplemental part of an overall organized ESD program.
Any antistatic chemical application shall be considered as a means to reduce or eliminate static charge generation
on nonconductive materials in the manufacturing or storage areas.
The application of any antistatic chemical in a clean room of class 10 000 or less shall not be permitted. Accordingly, any user of antistatic solutions must consider the following precautions:
1.
2.
Do not apply antistatic spray or solutions in any form to energized electrical parts, assemblies, panels,
or equipment.
Do not perform antistatic chemical applications in any area when bare chips, raw parts, packages, and/or
personnel are exposed to spray mists and evaporation vapors.
The need for initial application and frequency of reapplication can be established only through routing electrostatic
voltage measurements using an electrostatic voltmeter. The following durability schedule is a reasonable expectation.
1.
2.
3.
4.
Soft surfaces (carpet, fabric seats, foam padding, etc.): each 6 months or after cleaning, by spraying.
Hard abused surfaces (floor, table tops, tools, etc.): each week (or day for heavy use) and after cleaning,
by wiping or mopping.
Hard unabused surfaces (cabinets, walls, fixtures, etc.): each 6 months or annually and after cleaning,
by wiping or spraying.
Company-furnished and maintained clothing and smocks: after each cleaning, by spraying or adding antistatic concentrate to final rinse water when cleaned.
The use of antistatic chemicals, their application, and compliance with all appropriate specifications, precautions,
and requirements shall be the responsibility of the area supervisor where antistatic chemicals are used.
ESD Labels and Signs In Work Areas
ESD caution signs at workstations and labels on static-sensitive parts and containers shall be consistent in color,
symbols class, voltage sensitivity identification, and appropriate instructions. Signs shall be posted at all workstations
performing any handling operations with static-sensitive items. These signs shall contain the following information
or its equivalent.
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12-5
Guidelines for Handling Electrostatic-Discharge-Sensitive (ESDS)
Devices and Assemblies
CAUTION
STATIC CAN DAMAGE COMPONENTS
Do not handle ESD-sensitive items unless grounding wrist strap
is properly worn and grounded. Do not let clothing or plain plastic
materials contact or come in close proximity to ESD-sensitive
items.
Labels shall be affixed to all containers containing static-sensitive items at a place readily visible and proper for
the intended purpose. Additionally, labels must be consistently placed on containers and packages at a standard location to eliminate mishandling. Use only QC-accepted and approved signs and labels to identify static-sensitive products and work areas. The use of ESD signs and labels, and their information content shall be the responsibility of the
area supervisor to assure consistency and compatibility throughout the static-sensitive routing.
Relative Humidity Control
Since relative humidity has a Significant impact on the generation of static electriCity, when possible, the work area
should be maintained within the 40%-£0% relative humidity range.
Preparation for Working at Static-Free Workstation
A workstation with a static disspative work surface connected to ground through a 1 MQ ± 10% resistor, a
grounding wrist strap with the ground wire connected to the conductive work surface, and an ionizer constitute a
static-free workstation (Figure 1). An operator is properly grounded when the wrist strap is in snug (no slack) contact
with the bare skin, usually positioned on the left wrist for a right-handed operator. The wrist strap must be worn the
entire time an operator is at a static-free workstation. The operator should first touch the grounded bench top before
handling static-sensitive items. This precaution should be observed in addition to wearing the gounding wrist strap.
If possible, the operator should avoid touching leads or contacts even though he or she is grounded.
CAUTION
Personnel shall never be attached without the presence of the
1 MQ ± 10% series resistor in the ground wire.
An operator's clothing should never make contact or come in close proximity with static sensitive items. Operators
must be especially careful to prevent any static-sensitive items (being handled) from touching their clothing. Long
sleeves must be rolled up or covered with antistatic sleeve protector banded to the bare wrist, which shall "cage" the
sleeve at least as far up as the elbow. Only antistatic finger cots may be used when handling static-sensitive items.
Any improperly prepared person, while at or near the work station, shall not touch or come in close proximity with
any static-sensitive item. It is the responsibility of the operator and the area supervisor to ensure that the static-free
work area is clear of unnecessary static hazards, including such personal items as plastic coated cups or wrappers,
plastic cosmetic bottles or boxes, combs, tissue boxes, cigarette packages, and vinyl or plastic purses. All work-rlated
items, including information sheets, fluid containers, tools, and part carriers must be approved for use at the static-free
workstation.
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Guidelines for Handling Electrostatic·Discharge·Sensitive (ESDS)
Devices and Assemblies
General Handling Procedures and Requirements
1.
2.
All static-sensitive items must be received in an antistatic/conductive container and must not be removed
from the container except at the static-free workstation. All protective folders or envelopes holding documentation (lot travelers, etc.) shall be made of nonstatic-generating material.
Each packing (outermost) container and package (internal or intermediate) shall have a bright yellow
warning label attached, stating the following information or equivalent:
........... ELECTROSTATIC
CAUTION
~
~
a
\-:"}
SENSITIVE
DEVICES
DO NOT OPEN OR HANDLE
EXCEPT AT A
STATIC-FREE WORKSTATION
The warning label shall be legible and easily readable to normal vision at a distance of 3 feet.
Static-sensitive items are to remain in their protective containers except when actually in use at the staticfree station.
4. Before removing the items from their protective container, the operator should place the container on the
conductive grounded bench top and make sure the wrist strap fits snugly around the wrist and is properly
plugged into the ground receptacle, then touch hands to the conductive bench top.
5. All operations on the items should be performed with the items in contact with the grounded bench top
as much as possible. Do not allow conductive magazine to touch hard-grounded test gear on bench top.
6. Ordinary plastic solder-suckers and other plastic assembly aids shall not be used.
7. In cases where it is impossible or impractical to ground the operator with a wrist strap, a conductive shoe
strap may be used along with conductive tile/mats.
8. When the operator moves from any other place to the static-free station, the start-up procedure shall be
the same as in Preparation for Working at Static-Free Workstation.
9. The ionizer shall be in operation prior to presenting any static-sensitive items to the static-free station,
and shall be in operation during the entire time period the items are at the station.
10. "Plastic snow" polystyrene foam, "peanuts," or other high-dielectric materials shall never come in contact
with or be used around electrostatic sensitive items, unless they have been treated with an antistat (as
evidenced by pink color and generation of less than:!: 100 volts).
11. Static-sensitive items shall not be transported or stored in trays, tote boxes, vials, or similar containers
made of untreated plastic material unless items are protectively packaged in conductive material.
3.
Packaging Requirements
Packaging of static-sensitive items is to be in accordance with Device Sensitivity, item 1 . The use of tape and plain
plastic bags is prohibited. All outer and inner containers are to be marked as outlined in General Handling Procedures
and Requirements, item 2. Conductive magazines/boxes may be used in lieu of conductive bags.
Specific Handling Procedures for Static-Sensitive Items
Stockroom Operations
1 . Containers of static-sensitive items are not to be accepted into stock unless adequately identified as containing static-sensitive items.
TEXAS
~
INSIRUMENlS
POST OFFICE BOX 1443· HOUSTON. TEXAS 77001
12-7
Guidelines for Handling Electrostatic·Discharge·Sensitive (ESDS)
Devices and Assemblies
2.
3.
4.
Items may be removed from the protective container (magazine/bag, etc.) for the purpose of subdividing
for order issue only by a properly grounded operator at an approved static-free station as defined in Facilities for and Preparation for Working at Static-Free Workstation.
All subdivided lots must be carefully repackaged in protective containers (magazine/bag, etc.) prior to
removal from the static-free work-station and labeled to indicate that the package(s} contain static-sensitive items. If it is suspected that a static-sensitive item is not adequately protected, do not transfer it to
another container, return itto the originator for disposition unless the originator is a customer. In that case,
the QC engineer should contact the customer and negotiate an appropriate disposition.
It is the responsibility of the stockroom supervisor to ensure that all personnel assigned to this operation
are familiar with handling procedures as outlined in this specification. A copy of this specification is to be
posted in the vicinity so that it is accessible to the operators. Stock handlers and all others who might
have occasion to move stock are to be instructed to avoid direct contact with unprotected static-sensitive
items.
Module and Subassembly Operations
1.
2.
3.
4.
Static-sensitive items are not to be received from a stockroom, kitting, or machine insertion area unless
received in approved static-protective packaging, and properly labeled to indicate that its contents are
static-sensitive.
All single station, progressive line manual assembly operators, and visual inspectors prior to wave soldering operations are to be properly grounded with a grounding wrist strap when handling static-sensitive
items.
Progressive lines used as single stations where operators will be working on a mix of boards, both staticsensitive and nonstatic-sensitive, will require that all operators working on the line be properly grounded.
This is necessary to accommodate the sliding of static-sensitive boards along the assembly bench or
across positions not engaged in the assembly of this type board.
It is the responsibility of the area supervisor to ensure that all personnel handling static-sensitive items
are familiar with this procedure and fully aware of the damage or degradation of these units in the event
of noncompliance. A periodic inspection should be made using an electrostatic voltmeter to assure that
the static-free stations are in the proper working order and to ensure that operators are wearing grounding wrist straps properly (snugly in contact with bare skin).
Soldering and Lead-Forming Operations
1 . All soldering machines, conveyors, cleaning machines, and equipment shall be electrically grounded to
ensure that they are at the same ground potential as the grounded operators working on their stations.
No machine surfaces exposed to static-sensitive items are to be above ground potential.
2. All processing equipment shall be grounded, including all loading and unloading stations, that is, the stations before and after each piece of processing equipment.
3. All nonmetallic, static-generating components in the handling systems shall be treated to ensure protection from static.
4. All stations shall be identified by posting signs as outlined in ESD Labels and Signs in Work Areas.
5. Operators are to be properly grounded with a grounding wrist strap during any handling, loading, unloading, inspection, rework, or proximity to static-sensitive items.
6. Unloading operators working at a grounded station shall place static-sensitive items into approved staticprotective bags or containers.
7. All manual soldering,. repair, and touch-up workstations on the solder line are to be static protected. Operators are to wear grounding wrist straps when working on static-senstive items. Only grounded-tip soldering/desoldering irons are allowed when working on static-sensitive items.
TEXAS
~
INSTRUMENTS
12-8
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
Guidelines for Handling Electrostatic-Discharge-Sensitive (ESDS)
Devices and Assemblies
S.
It is the responsibility of the area supervisor to ensure that all personnel handling static-sensitive items
are familiar with this procedure and fully aware of the damage or degradation of these units in the event
of noncompliance. A periodic inspection should be made using an electrostatic voltmeter to assure that
the static-free stations are in proper working order and to ensure that the operators are wearing grounding wrist straps properly (comfortably snug in contact with bare skin).
Electrical Testing Operations
1.
2.
3.
4.
5.
6.
7.
S.
9.
All eiectrical test stations shall be static protected. OperatoiS shall be properly grounded when working
on these items.
Reused antistatic magazines must be monitored for maintenance of antistatic characteristics.
Devices should be in an antistatic/conductive environment except at the moment when actually under
test.
Devices should not be inserted into or removed from circuits or tester with the power on or with signals
applied to inputs to prevent transient voltages from causing permanent damage.
All unused input leads should be biased if possible.
Device or module repairs must be performed at static-free stations with the operator attached to a
grounding wrist strap. Grounded-tip soldering irons shall be used when working on static-sensitive items.
Static-sensitive items shall be handled through all electrical inspections in static protective containers.
Removal of the items from the protective containers shall be done at a static-free workstation as discussed in Preparation for Working at a Static-Free Workstation. The units must be returned to the containers before leaving the station.
All such items shall be shipped with an ESD warning label affixed as listed.
It is the responsibility of the area supervisor to ensure that all personnel handling static-sensitive items
are familiar with this procedure and fully aware of the damage or possible degradation of these units in
the event of noncompliance. A periodic inspection should be made using an electrostatic voltmeter to
assure that the static-free stations are in proper working order and to ensure that operators are wearing
grounding straps properly (snugly in contact with bare skin).
Packing OperatIons
1.
2.
3.
Static-sensitive items are not to be accepted into the packing area unless they are contained in a staticprotected bag or conductive container.
A static-sensitive item delivered to the packer within an approved container or bag and found to be in
order regarding identification shall be packed in the standard shipping carton or other regular packaging
material. Containers are to be labeled in accordance with General Handling Procedures and Requirements, item 2.
Any void-fillers shall be made of an approved antistatic material.
Burn-In operations
1.
2.
3.
4.
Burn-in board loading and unloading of static-sensitive items shall be done at a static-free station.
Shorting clips/shorted connectors shall be installed on the board plug-in tab prior to loading any units into
the board sockets. The clip/connectors shall be taken off just prior to plugging the board into the oven
connector. The clip/connector shall be installed immediately upon removal of the board from the oven
connector. Installation and removal of the clip/connector shall be done by a properly grounded operator.
All automatic or semi-automatic loading and unloading equipment shall be properly electrically grounded.
It is the responsibility of the area supervisor to ensure that all personnel handling static-senstive items
are familiar with this procedure and fully aware of the damage or possible degradation ofthese units inthe
event of noncompliance. A periodic inspection should be made using an electrostatic voltmeter to assure
that the static-free stations are in proper working order and to ensure that operators are wearing grounding straps properly (snugly in contact with bare skin).
TEXAS ~
INSlRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
12·9
Guidelines for Handling Electrostatic-Discharge-Sensitive (ESDS)
Devices and Assemblies
Customer-Returned-Item Handling Procedure
Receipt of ESO sensitive-labeled items is to be done at a static-free workstation and handled in accordance with
applicable sections within this guideline.
Quality Control Provision
Sampling
Each manufacturing, stockroom, and testing operation handling ESO sensitive devices will be audited a minimum
of once each quarter for compliance with all terms of this specification by the responsible process control or ORA
organization. Ground continuity and the presence of uncontrolled static voltages are considered critical and shall be
checked more frequently as specified below.
Ground Continuity (minimum of once a week)
Ground connections (grounding wrist strap, ground wires on cords, etc.) shall be checked for electrical continuity.
The presence of a 1 MQ ± 10% resistor in the ground connections between both the operator wrist straps to the work
surface and the work surface to ground connector must be verified.
Grounded Conditions (minimum of once a week)
A visual inspection shall be made to determine full compliance with this specification at static-free workstations
during handling of static-sensitive items, including operator being grounded as required, static-sensitive items not
being handled in unprotected or unauthorized areas, and no static-generating materials at the grounded workstation.
Sleeve Protectors (minimum of once a week)
A visual check shall be made to determine that each operator wearing loose-fitting or long-sleeved clothing either
has sleeves properly rolled or covered with sleeve protectors properly grounded to the bare skin at the wrist.
Static Voltage LevelS (minimum of once a week)
In addition to the visual inspections, a sample inspection using an electrostatic voltmeter will be used to check for
uncontrolled electstatic voltages at or near electrostatic-controlled work stations.
Conductive Floor Tiles (minimum of once a month)
Conductive floors must have a resistance of not less than 100 kQ from any point on the tile to earth ground. Also,
resistance from any point-to-point on the tile floor three (3) feet apart shall be not less than1 00 kQ. The test methods
to be used are ASTM-F-150-72 and NFPA 99.
Records
Written records must be kept of all these OC audits.
Training
Training is applicable for all areas where individuals come in contact with ESO-sensitive devices. It is the responsibility of each area supervisor to make sure that his/her people receive ESO training initially and every 12 months there:
after to maintain proficiency. Training should include static fundamentals, a review of applicable parts of this specification, and actual applications in the work area.
. TEXAS
.JJI
INSTRUMENTS
12-10
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
Mechanical Data
13-1
Contents
CHAPTER 13.
MECHANICAL DATA
MOS Memory Commercial
50/44-Lead Thin Small-Outline Package (DC Suffix) ................................................. 13-5
32-Lead Plastic Thin Small-Outline J-Lead Package (DD Suffix/DU Suffix) .............................. 13-6
40-Lead Plastic Thin Small-Outline J-Lead Package (DD Suffix/DU Suffix) ............................... 13-7
32-Lead Plastic Thin Small-Outline Package (DE Suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 13-8
20/26-Lead Small-Outline Package (DGA Suffix/DGB Suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 13-9
24/26-Lead Thin Small-Outline Package (DGA Suffix/DGB Suffix) .................................... 13-10
28-Lead Plastic Thin Small Outline Package (DGC Suffix) ........................................... 13-11
24/28-Lead Thin Small-Outline Package (DGC Suffix/DGD Suffix) .................................... 13-12
40/44-Lead Thin Small-Outline Package (DGE Suffix) ............................................... 13-13
64-Lead Small-Outline Package (DGH Suffix) ...................................................... 13-14
20/26-Lead Plastic Small-Outline J-Lead Package (DJ Suffix) ........................................ 13-15
24/26-Lead Plastic Small-Outline J-Lead Package (DJ Suffix) ........................................ 13-16
20/26-Lead Thin Small-Outline J-Lead Package (DN Suffix) ......................................... 13-17
28-Lead Plastic Small-Outline J-Lead Surface Mount Package (DZ Suffix) ............................. 13-18
28/24-Lead Plastic Small-Outline J-Lead Surface Mount Package (DZ Suffix) .......................... 13-19
40-Lead Plastic Small-Outline J-Lead Surface Mount Package (DZ Suffix) ............................. 13-20
18-Lead Plastic Leaded Chip Carrier (FM Suffix) ................................................... 13-21
32-Lead Plastic Leaded Chip Carrier Package (FM Suffix) ........................................... 13-22
44-Lead Plastic Leaded Chip Carrier Package (FN Suffix) ........................................... 13-23
Ceramic Dual-In-Line Package (J Suffix) .......................................................... 13-24
Plastic Dual-In-Line Package (N Suffix) ........................................................... 13-26
42-Lead Plastic Small Outline J-Lead Surface Mount Package (RE Suffix) .............................. 13-27
20-Lead Zig-Zag Plastic Package (SD Suffix) ...................................................... 13-28
60-Lead Memory Card .......................................................................... 13-29
68-Lead Memory Card .......................................................................... 13-30
88-Lead Memory Card .......................................................................... 13-31
30-Lead AD Single-In-Line Memory Module ....................................................... 13-32
30-Lead Single-/Double-Sided BD Single-In-Line Memory Module .................................... 13-33
72-Lead BK Single-/Double-Sided Single-In-Line Memory Module .................................... 13-34
13-2
30-Lead U Single-In-Line Memory Module ......................................................... 13-35
MOS Memory Military
18-Lead Ceramic Chip Carrier Package (FG Suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 13-36
28/24-Lead Small-OutlinQ! Leadless Ceramic Chip Carrier Package (FNC Suffix) ....................... 13-37
20-Lead Small-Outline Leadless Ceramic Chip Carrier Package (FQ and HL Suffixes) .................. 13-38
20-Lead Leaded Ceramic Chip Carrier Package (HJ Suffix) ................................... ~ . . . . .. 13-39
28-Lead Ceramic Small-Outline J-Leaded Chip Carrier Package (HJ Suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . .. 13-40
20-Lead Flatpack (H K Suffix) .................................................................... 13-41
28-Lead Flatpack (HKB Suffix) ................................................................... 13-42
20-Lead Small-Outline Leadless Ceramic Chip Carrier Package (HM Suffix) ........................... 13-43
. 20-Lead Ceramic Flatpack (HR Suffix) ............................................................ 13-44
28-Lead Ceramic Dual-In-Line Package (J Suffix) .................................................. 13-45
18-Lead Ceramic Sidebrazed Dual-In-Line Package (JD Suffix) ...................................... 13-46
20-Lead Ceramic Sidebrazed Dual-In-Line Package (JD Suffix)
13-47
28-Lead Ceramic Sidebrazed Dual-In-Line Package (JO Suffix) ...................................... 13-48
20-Lead Zig-Zag In-Line Ceramic Package (SV Suffix) .............................................. 13-49
13-3
13-4
Mechanical Data
MOS Memory Products - Commercial
50/44-Lead Thin Small Outline Package (DC Suffix}:!:
14--------
r
10,29 (0.405)
10, 03 (0.395)
21,OB (0.B30) t
20,B3 (0.B20) -------~
T
t
10,74
(0.423)
f
11,94 (0.470)
11,56 (0.455)
~ ~On'-~~I~ndneXrM~a~rk~~ ~~~~nr~~
____
L
0, 17B (0.007)
0, 127 (0.005)
1,194 (0.047) MAX
fiup n n nlllUW n !
f
j
l
0,457 (0.018)
0,254 (0.010)
-J I.-
O,BOO (0.031) TYP
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
t Plastic body dimensions do not include mold protrusion. Maximum mold protrusion is 0, 254 mm (0.010) from the edge of the package bottom
plastic.
Applicable MOS Memory Devices:
*
TMS416160
TMS416160P
TMS418160
TMS418160P
TMS426160
TMS426160P
TMS428160
TMS428160P
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
13-5
Mechanical Data
MOS Memory Products - Commercial
32·Lead Plastic Thin Small·Outline J·Lead Package (TSOP) (DO Suffix/DU Suffixtrt:
l+
18, 45 (0.726)
18, 35 (0.722)
o
t
0,600 (0.024)
0,400 (0.002)
~
~~----------~~
0,600 (0.024)
0, 150 (0.006)
t=
19,60(0.772)
19,40 (0.764)
0,300 (0.012)
0,100 (0.004)
1 ,27J~~50)
0, 15 (0.006)
0,00 (0.000)
~
~
20, 20 (0.795)
19,90(0.784)
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
t The DU suffix applies to the reverse form of the DO package shown above, All mechanical dimensions shown are applicable for both the DO
and DU packages, Refer to the pinout drawings in the data sheet for correct pin numbers and index location for the DU package,
:j: Applicable MOS Memory Devices:
TM27LV010A
TMS27PC010A
TMS27PC512
TMS28F010
TMS28F512
TEXAS ~
INsrRUMENTS
13-6
POST OFFICE BOX 1443' HOUSTON, TEXAS 77001
Mechanical Data
MOS Memory Products - Commercial
40-Lead Plastic Thin Small-Outline J-Lead Package (TSOP) (DO SuffixjDU Suffixtrt:
1t+
18, 50 (0.728)
18,30 (0.720)
•
o
t
1 ,20~~0~047)
0,200 (0.008)
0,050 (0.002)
0,600 (0.024)
0,400 (0.002)
0,0300 (0.012)
0, 150 (0.006)
0,700 (0.028)
0,300(0.014)
1=
19,60 (0.772)
19,40 (0.764)
~
20,20 (0.795)
19,80 (0.780)
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
t The DU suffix applies to the reverse form of the DO package shown above. All mechanical dimensions shown are applicable for both the DO
and DU packages. Refer to the pinout drawings in the data sheet for correct pin numbers and index location for the DU package.
*Applicable MOS Memory Devices:
TMS28F040
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
13·7
Mechanical Data
MOS Memory Products - Commercial
32-Lead Plastic Thin Small Outline Package (TSOP) (DE Suffix):!:
14r-----
21, 08 (0.830)
20,83 (0.820)
------+11
t
I
r
tJI
0, 178 (0.007)
0, 127 (0.005)
10,21 (0.405)
10,03 (0.395)
t
1,194 (0.047)::..J
l[,." ,u",""--J3~
6nooonoonnonnnnnrl
h.
fy'i",
-JlO,406
(0.016)
TYP
11,89 (0.468)
11, 63 (0.458)
j
l
1,27
(0.050)
~
TYP
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
t Plastic body dimensions do not include mold protrusion. Maximum mold protrusion is 0,254 mm (0.Q1 0) from the edge of the package bottom
plastic.
*Applicable MOS Memory Devices:
TMS416800
TMS416800P
TMS417800
TMS417800P
TMS427800
TMS427800P
TMS426800
TMS426800P
TEXAS'~
INSTRUMENTS
13-8
POST OFFICE BOX 1443· HOUSTON. TEXAS 77001
Mechanical Data
MOS Memory Products - Commercial
20/26-Lead Small Outline Package (DGA Suffix/DGB Suffixt)§
17,221 (O.678)
*
1 + - - - - - - 17,069 (O.672) -----~
I
7,696 (O.303)
7,544 (O.297)
L
*
0,178 (0.007)
~'127 (0.005)
l",u~~" J
hnnntlJ
j
l
LJjnnnrl
0,457 (O.018)
0,356 (O.014)
--.J !.-
1,27 (0.050) TYP
0,508 (O.020) TYP
t
9,373 (O.369)
9,068 {O.357}
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
t The DGB package suffix applies to the reverse form of the DGA package shown above. All mechanical dimensions shown are applicable for both
the DGA and DGB packages. Refer to the pinout drawings in the data sheet for correct pin numbers and index location for the DGB package.
*Plastic body dimensions do not include mold protrusion. Maximum mold protrusion is 0,254 mm (0.010) from the edge of the package bottom
plastic.
§ Applicable MOS Memory Devices:
TMS44100
TMS44100P
TMS44400
TMS44400P
TMS46100
TMS46100P
TMS46400
TMS46400P
TEXAS •
INsrRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
13-9
Mechanical Data
MOS Memory Products - Commercial
24/26·Lead Thin Small Outline Package (DGA Suffix! DGB Suffix)t§
17,221 (O.678):j:
1 + - - - - - 7.17~,O;;;6;;;9:-i{O;;-.~67:;;2;;')-----+I
7,696 (O.303)
7,544 (O.297)
t
hnnnnnnnnnnnrl
j
l
0,457 (O.018)
-+I i+-
1,27 (O.050) TYP
0,356 (O.014)
0,508 (O.020) TYP
9,373 (O.369)
9,068 (O.357)
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
t The DGB package suffix applies to the reverse form of the DGA package shown above. All mechanical dimensions shown are applicable for both
the DGA and DGB packages. Refer to the pinout drawings in the data sheet for correct pin numbers and index location for the DGB package.
:j: Plastic body dimensions do not include mold protrusion. Maximum mold protrusion is 0,254 mm (0.010) from the edge of the package bottom
plastic.
§ Applicable MOS Memory Devices:
TMS416100
TMS416100P
TMS416400
TMS416400P
TMS417400
TMS417400P
TMS426100
TMS426100P
TMS426400
TMS426400P
TMS427400
TMS427400P
NOTE: The package information on this page also applies to the Product Preview version of the TMS4161 00, TMS416100P, TMS416400,
TMS416400P, TMS417400, and TMS417400P devices.
TEXAS ~
INSTRUMENTS
13-10
POST OFFICE BOX 1443· HOUSTON, TEXAS 77001
Mechanical Data
MOS Memory Products - Commercial
28-Lead Plastic Thin Small Outline Package (TSOP) (DGC Suffix)t
C
18,41 (0.725) NOM
d
19 18 17 16 15
I
10,16 10.400)
TYP
Index
1,20 (0.047) MAX ]
0,127 (0.005) TYP
[
ftJ.[1
10,76 (0.424) TYP
jh.
Jl
f;;6:;:;n;:;:;n;:;:;n:;::;:n:;::;:n:;:;:n:;:;:n:;:;n:;:;n:;:;n::;:;:n:;::n;:;:;n;:;:;a=l
0,508 (0.020)
TYP
j
l ~~
(0.016)
- - - - ,-
1,27 (0.050)
11,76 (0.463) TYP
TYP
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
t Applicable MOS Memory Devices:
TMS44800
TMS44800P
TEXAS ~
INsrRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
13-11
Mechanical Data
MOS Memory Products - Commercial
24/28-Lead Thin Small Outline Package (DGe Suffix/DGD Suffixt)§
18,51 (0.729) t
18,31 (0.721) - - - - - - + 1
r
10,21 (0.402)
10,01 (0.394)
Index
o
[
0,178 (0.007)
0,127 (0.005)
+~JL'
~l
0,508 (0.020):JVP
[blfn55n5rn5Jn5rn5b1~===luEn:un:inBj:n55n5j:d]
-J I..-
0,457 (0.018)
0,356 (0.014)
~
[ , 1 9 4 (0.047) MAX
J
10,74 (0.423) TYP-./
1 ,27 (0.050) TYP
11,86 (0.467)
11 ,66 (0.459)
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
t The DGD package suffix applies to the reverse form of the DGC package shown above. All mechanical dimensions shown are applicable for
both the DGC and DGD packages. Refer to the pinout drawings for correct pin numbers and index location for the DGD package.
t Plastic body dimensions do not include mold protrusion. Maximum mold protrusion is 0.254 mm (0.010) from the edge of the package bottom
plastic.
§ Applicable MOS Memory Devices:
TMS416400
TMS416100
TMS417400
TEXAS ~
INSTRUMENTs
13-12
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
Mechanical Data
MOS Memory Products - Commercial
40/44-Lead Thin Small Outline Package (DGE Suffix)t
r---
18,41 (0.725) NOM
Innnnnnnnnn
44434241403938373635
32 31 30 29 28 27 26 25 24 23
10,16 (0.400)
Index
11,76 (0.463)
~1~2~3~4~5~6~7~8~9~1~0~ ~1~3~14~15~1~6~1~7~18~1~9~2~0~21~2~2~
____
1,20 (0.047) MAX
j
7'
TYP
L
t
0,9(0.035)
0,7(0.028)
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
t Applicable MOS Memory Devices:
SDRAM
TMS44165
TMS44165P
TMS45160
TMS45160P
TMS45165
TMS45165P
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443' HOUSTON, TEXAS 77001
13·13
Mechanical Data
MOS Memory Products - Commercial
64-Lead Small Outline Package (DGH Suffix)t
0,81 (0.032)
0,71 (0.028)
2,10 (0.083)
1,90 (0.075)
r
14,40 (0.567)
14,10 (0.555)
12,10 (0.476)
11 ,90 (0.468)
L
1Irrm0T'T'T"TT'Tm'TI'T'T'T"TT'Tm'TI'T'T'T"TT'Tm'TI'T'T'T"TT'Tm'TI''''''''''''''''
0,40 (0.016)
0,30 (0.012)
0,80 (0.0315) NOM
Seating Plane
2,28 (0.094) MAX
0,150 (0.006) NOM
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
t Applicable MOS Memory Devices:
TMS55160
TMS55165
TEXAS ."
INsrRUMENTS
13-14
POST OFFICE BOX 1443' HOUSTON, TEXAS 77001
0' to 5'
MAX
Mechanical Data
MOS Memory Products - Commercial
20/26-Lead Plastic Small-Outline J-Lead Package (SOJ) (OJ Suffix)f:I:
17,22 (0.678) t
17,07 (0.672)
2625242322
8,64 (0.340)
8,38 (0.330)
Index Notch
7,65 (0.301)
7,49 (0.295)
t
9 10111213
1 2 3 4 5
2,85 (0.112)
2,62 (0.103)
NOM
0,20(0.008)
Excluding Finish
]
~
1,14 (0.045)
0,89 (0.035)
- - Seating Plane~
+----..------"",
1,02 (0.040)
0,76 (0.030)
3,76 (0.148)
3,25 (0.128)
1,27 (0.050)
0,81 (0.032)
1,02 (0.0~40J0'66
(0.026)
_
0,64 (0.025) MIN
0,51 (0.020)
jl
---,-
I I
-.I ~
1,27 (0.050) TYP
0,41 (0.016)
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
t Plastic body dimensions do not include mold protrusion. Maximum mold protrusion is 0,254 mm
(0.010) from the edge of the package bottom
plastic.
:j: Applicable MOS Memory Devices:
TMS4C1024
TMS4C1025
TMS4C1027
TMS4C1050B
TMS4C1060B
TMS44100
TMS44100P
TMS44400
TMS44400P
TMS46100
TEXAS
TMS4610P
TMS46400
TMS46400P
~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
13·15
, Mechanical Data
MOS Memory Products - Commercial
24/26-Lead Plastic Small-Outline J-Lead Package (SOJ) (OJ Suffix);
17,22 (0.678) t
[ - - - 17,07 (0.672) ---~
262524232221
/
191817161514
8,64 (0.340)
8,38 (0.330)
INDEX NOTCH
7,65 (0.301) t
7,49 (0.295)
1 2 3 4 5 6
8 9 10111213 ~
2,85 (0.112)
2,62 (0.103)
1,27 (0.050)
0,20 (D.008) NOM
EXCLUDING FINISH ]
~-----""~
-*-
- - SEATING
1,02 (0.040)
0,76 (0.030)
3,76 (0.148)
3,25 (0.128)
0,81 (0.032)
~
1,02 ( 0 . 0 4 : : : ; :
~
PLAN~
0,51 (0.020)
0,41 (0.016)
1,14(0.045)
0,89 (0.035)
~
jL
I I
---.I 14-- 1,27 (0.050) TYP
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
t Plastic body dimensions do not include mold protrusion. Maximum mold protrusion is 0,254 mm
(0.010) from the edge of the package bottom
plastic.
:t Applicable MOS Memory Devices:
TMS416100
TMS416100P
TMS416400
TMS416400P
TMS417400
TMS417400P
TMS426100
TMS426100P
TMS426400
TMS426400P
TMS427400
TMS427400P
TMS44C260
TMS48C128
TMS48C138
NOTE: The package information on this page also applies to the Product Preview version of the TMS4161 00, TMS416100P, TMS416400,
TMS416400p, TMS417400, and TMS417400P devices.
TEXAS ~
INSTRUMENTS
13-16
POST OFFICE BOX 1443· HOUSTON. TEXAS 77001
Mechanical Data
MOS Memory Products - Commercial
20/26 Thin Small-Outline J-Lead Package (DN)t
n
_I
l
~
0,559 (0.022)
1\ _
8,26 (0.325)
/
1
Index Notch
2
3
4
9 10 11 12 13
5
~~~~
~~I
0,31 (0.012) x 45'
J
LL
-r-((,t-:t::.======::ib t
1,83 J072)
1,73 (0.068)
8,50 (0.335)
7,47 (0.294) --t
18 17 16 15 14
26 25 24 23 22
L
7,57 (0.298)
J
1-------16.51 (0.650)
------.1.
0,15 (0.006)
J
0,84 (0.033)
0,51 (0.020)
0,41 (0.016)
lo:u:u:u:u"'-----'lciiiiitiJJJ
JL
0,81 (0.032)
0,66 (0.026) -
1,27
(O.~~
JL
_
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
t Applicable MOS Memory Devices:
TMS44C256
TMS4C1024
TMS4C1025
TMS4C1027
TEXAS ~
INSI'RUMENTS
POST OFFICE BOX 1443· HOUSTON, TEXAS 77001
13·17
Mechanical Data
MOS Memory Products - Commercial
28-Lead Plastic Small Outline J-Lead Surface Mount Package (DZ Suffix)t
18,67 (0.735)
~-...-I-__-_---______18_,_42_('-0_.7_25)-'-__-_-=--=--=--=--=--=--.~1
Index Mark
10,29 (0.405)
10,03 (0.395)
-jj~_ _ _ _~
2,79 (0.110) NOM
- - - Sealing Plane - 4 - 9,53 (0.375)
9,27 (0.365)
I
I
---r...I----~.
3,76 (0.148)
3,25 (0.128)
0,46 (0.018) NOM
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
t Applicable MOS Memory Devices:
TMS416800
TMS416800P
TMS417800
TMS417800P
TMS426800
TMS426800P
TMS427800
TMS427800P
TMS44800
TMS44800P
TEXAS ~
INsrRUMENTS
13·18
POST OFFICE BOX 1443· HOUSTON, TEXAS 77001
Mechanical Data
MOS Memory Products - Commercial
28/24-Lead Plastic Small Outline J-Lead Surface Mount Package (OZ Suffix):!:
18,542 (0.730) t
18,288 (0.720)
r
28 27 26 25 24 23
+-
-----~i
20 19 18 17 16 15
o
11,303 (0.445)
11,049 (0.435)
r
Index
Mark
10,287 (0.405)
2
3
4
5
6
9
10 1112 13 14
3,251 (0.128)
--J I.--
0,457 (0.018)
NO~ ~
*""--_
"L1"_ _ _ _
l
2,692
(0.106)
NOM
-h
3,759 (0.148)
1,27 (0.050) NOM
10,033 (0.395)
2,083
(0.082)
MIN
__
~
Ir--....----......-1-fl-~...I.
Seating - Plane
0,813 (0.320)
0,661 (0.260)
0,635
(0.025)
MIN
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
t Plastic body dimensions do not include mold protrusion. Maximum mold protrusion is 0.254 mm (0.010) from the edge of the package bottom
plastic.
Applicable MOS Memory Devices:
*
TMS416100
TMS416400
TMS417400
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
13·19
Mechanical Data
MOS Memory Products - Commercial
40·Lead Plastic Small Outline J·Lead Surface Mount Package (OZ suffix)t
4- - - - - - - - - - - - - - - - - - - - - - - - - - - - - 40.
11 , 303(0.445)
11,049(0.435)
r""~~'~l
)
10, 033(0.395)
3,759(0.148)
3,251 (0.128)
2,794
(0.110)
14 1
26, 162(1.030)
25,781 (0.015)
Ref
0,813(0.032)
0,661 (0.026)
1,270 (0.050) TYP
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
t Applicable MOS Memory Devices:
TMS44165
TMS44165P
TMS45160
TMS45160P
TMS45165
TMS45165P
TEXAS ~
INSTRUMENTS
13-20
POST OFFICE BOX 1443· HOUSTON, TEXAS 77001
~J
Mechanical Data
MOS Memory Products - Commercial
18-Lead Plastic Leaded Chip Carrier (PLCC) (FM Suffix)t
r
8,50 (0.335)
8,05 (0.317)
Ii+ 7,47 (0.294)+1
7,2S (O.2BS)
I
J
13, 59 (0.535)
13,13 (0.517)
12,55 (0.494)
12,34 (0.486)
0.81 (0.032)
0,660 (0.026)
Seating
Plane
~
3, 55 (0.140) ----I~======;2
Index
11,18 (0.440)
___-.:1~
r
lr'i:ii~~R~~:R~rnR;;=·.~rnm~···~~rnR~··~~il==:.i
qUH
t
3,18 (0,125)
2,67 (0.105)
0,25 (0.010) REF
1,40 (0.055)
0,89 (0.035)
l
3,18 (0.125)
2,67 (0.105)
2,03 (0.080) TYP
1,78 (0.070)
0,20 (0.008) R
TYP
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
TEXAS ~
INSTRUMENTS
13·36
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
Mechanical Data
MOS Memory Products - Military
20-Lead Small-Outline Leadless Ceramic Chip Carrier (Fa and HL Suffixes)
[~__________ ~17~'~40~(0~.6~85~)________~·1
11
"." ("~l
fr
I
9,07 (0.357)
8,71 (0.343)
:A2========:::=====:::-::::::::::::::U
Index
(1 of 2 Places)
--
15,49 (0.610)
14,99 (0.590)
r
1,22 (0.048) TYP
0,71 (0.028)
~----+'LLIf:1~I: =tJI'F'(t;JI
=, ....,h~=I""-,:I=,'i....i =:.=:=1....:\,:1="....,: J.I=IiJ...:~I:=ii.....' ![I;rfLUI~I--1}- A
0,89 (0.035) REF ..
r -__I L
1,40 (0.055)
1, 14 (0.045)
0,203 (0.008) R
TYP
2,54 (0.100)
2,03 (0.080)
1,40 (0.055) TYP
1,14 (0.045)
PACKAGE SUFFIX
DIMENSION A
Fa
2,29 (0.090)
1,52 (0.060)
HL
2,03 (0.080)
1,52 0.060
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
13-37
Mechanical Data
MOS Memory Products - Military
20-Lead Leaded Ceramic Chip Carrier (HJ Suffix)
E
1
17,40 (0.685)
16,89 (0.665)
15,49 (0.610) ~
14,99 (0.590)
1,22 (0.048)
4- 0,71 (0.028) 4 Places
~[::::::::::::=====~~l-::~+:f~
2,54 (0.100)
~.~
f j L
--J I.-
1,14 (0.045)
0,89 (0.035)
1,40 (0.055)
1,14 (0.045)
0, 58 (0.023)
0,41 (0.016)
1
\4-
3, 56 (0.140)
3,05 (0.120)
j
0,30 (0.012)
I •"
,0,""')
R-',, 0,89(0.035)
7,75 (0.305)..
6,86 (0.270)
•
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
TEXAS ~
IN5rRUMENTS
13-38
POST OFFICE BOX 1443· HOUSTON. TEXAS 77001
0,64 (0.025) R
Mechanical Data
MOS Memory Products - Military
28-Lead Ceramic Small Outline J-Leaded Chip Carrier (HJ Suffix)
~=:~::~:=h
10,719 (0.422)
10,636 (0.408)
l-
1,956 (0.077)
1,499(0.059)
16,764 (0.660)
16,256 (0.640)
---:IJ
G~,~
l.-f
Jl
1,016 (0.030)
r:-
Tj
I.-
1,397 (0.055)
1,143 (0.045)
2,565 (0.101)
2,032 (0.080)
0,330 (0.013)
0,152 (0.006)
~====~--*-
0,889 (0.035)
0,635 (0.025) R
0,584 (0.023)
0,406 (0.016)
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
13·39
Mechanical Data
MOS MemoryProducts - Military
20-Lead Flatpack (HK Suffix)
8,00 (0.315) TYP
7, 49 (0.295)
9,83 (0.387)
9,47 (0.373) -i4-I----~
1,27 (0.050) TYP
L
----+---~
P~
u
f~~1:
I:
1.- ====:• .~::1
I
0,533 (0.021)
0,381 (0.015)
17, 27 (0.680)
16, 77 (0.660)
C===:::J -,.--
r '--------'
2,77 (0.109) _
2,41 (0.095)
2, 41 (0.095)
1, 91 (0.075)
0,89 (0.035)
0, 64 (0.025)
Measured at Ceramic
-.l
I
0, 25 (0.010)
0, 10 (0.004)
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
TEXAS ~
INsrRUMENTS
13·40
POST OFFICE BOX 1443· HOUSTON, TEXAS n001
Mechanical Data
MOS Memory Products - Military
28-Lead Flatpack (HKB Suffix)
3,32 (0.130)
2,29 (0.090)
0,66 (0.026) MIN
(Measured at
Ceramic)
l
f
II
I
l*
'f'
["M~
0,23 (0.009)
'- 0,10 (0.004)
(0.20)
MIN
--t
0,76 (0.030) MIN, 2 Places
r9,40 (0.370) TYP
6,35 (0.250)
1,27
(0.050)
TYP
I
I
11,68 (0.460) - ,
11,18 (0.440)
~
L
J
L
r
0,53 (0.021)
0,38 (0.015) ---.
19,94 (0.785)
19,43 (0.765)
'f'
1,65 (0.065)
1,14 (0.045) ---.
TYP 4 Places
'f'
~
~
1
Pin 1 Identifier
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
13-41
Mechanical Data
MOS Memory Products - Military
20-Lead Small-Outline Leadless Ceramic Chip Carrier (HM Suffix)
~r-----
18,034 (0.710)
17,526 (0.690)
~I
n
10,338 (0.407)
9,982 (0.393)
Index
(1 of 2 Places)
-..P~:::::::=:::::::::=:::::::::=::~U
3,175 (0.125)
2,667 (0.105)
r- IIIIIII
I I I I III
=t
2,337 (0.092)
1 ,727 (0.068)
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
TEXAS
~
INSTRUMENTS
13-42
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
Mechanical Data
MOS Memory Products - Military
20-Lead Ceramic Flatpack (HR Suffix)
9,017 ± 0,381
(0.355 ± 0.015)
TYP
1,27(0.050) TYP
l
i
Lr---f~:.':::'~~1
I
Pin 1
~L
~----~===9u:~~~
J---'-1
C~======
17,780 ± 0,254
(0.700 ± 0.010)
0,457 ± 0,076 =====;~
(0.018 ± 0.003) =====;~
L====
I
rL:::::::==:::..Jl _ _T~
I
2,972 ± 0,407
(0.117 ± 0.Q16)
2,286 ± 0,254
(0.090 ± 0.010)
t
0,178 ± 0,076
(0.007 ± 0.003)
0,762 ± 0,127
(0.030 ± 0.005)
Measured at Ceramic
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
13-43
Mechanical Data
MOS Memory Products - Military
28-Lead Ceramic Dual-In-Line Package (J Suffix)
2,29 (0.090)
1,53 (0.060)
. . r-
B
~ ~.
D
r
0
r
1£~, f 3t~·'~
r-JL
Jl
4,45 (0.175)
3,56 (0.140)
MIN
0,457(,"".
MIN
5,08 (0.200)
3,81 (0.150)
0,599 (0.022)
0,356 (0.014)
_A __
~
L
18,29 (0.720)
16,36 (0.644)
j
MIN REF
1,57 (0.062)
1,14 (0.045)
28
15,85 (0.624)
37,21 (1.465)
14,25 (0.561)
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
TEXAS
~
INSTRUMENTS
13-44
POST OF~ICE BOX 1443 • HOUSTON, TEXAS 77001
I
MAX
0,305 (0.012)
0,203 (0.008)
0,711 (0.028)
2,79 (0.110)
2,29 (0.090)
Lens Protrusion
0,254 (0.010)
Mechanical Data
MOS Memory Products - Military
18-Lead Ceramic Sidebrazed Dual-In-Line Package (JD Suffix)
r---
23,11 (0.910) MAX ~
I!!'~
~I
1,778 (0.070)
1,016 (0.040)
8,13(0,320)-0
7,37 (0.290)
5,08 (0.200)
_
Seating
Plane
_ - y -_ _
0,508 (0.020)
MIN
0,38 (0.015)
0,20 (0.008)
j
Mg
J L JL
3,175 (0.125)
MIN
0,53 (0.021)
0,38 (0.015)
2,54 (0.100) NOM
Pin Spacing
ALL LINEAR DIMENSIONS ARE IN Mill METERS AND PARENTHETICALLY IN INCHES
TEXAS •
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
13-45
Mechanical Data
MOS Memory Products - Military
20.:Lead Ceramic Sidebrazed 300-MII Dual-In-Llne Package (JOB Suffix)
-
25,65 (1.010) ~
25,15 (0.990)
Index Mark
8, 13 (0.320)
7, 37 (0.290)
0, n8 (0.070)
0,016 (0.040)
Seating
Plane
f
5,08 (0.200) Max
(--i--
II
0,53 (0.021)
0,38 (0.015)
-.J I.-
s~~~~g
-
n
II
3,175 (0.120)
5, 08 (0.200)
-+i ~
2,54 (0.100) TYP
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
TEXAS ~
INSIRUMENTS
13-46
POST OFFICE BOX 1443· HOUSTON, TEXAS nOOl
0, 38 (0.015)
0,20 (0.008)
Mechanical Data
MOS Memory Products - Military
.20-Lead Ceramic Sidebrazed 400-Mil Dual-In-Llne Package (JD Suffix)
25,908 (1.020) MAX
I
]".
)
~
3,556
(0.140)
MAX
10,287 ± 0,381
(0.405 ± 0.015)
---.-----I----cr-
:~;:o~~lr~ j
L
~
2,540
(0.100)
22,860 ± 0,254
(0.900 ± 0.010)
0,381
(0.015)
MIN
_*-_ _ _ _~
Seating Plane-
JL
0,279 ± 0,076
(0.011 ± 0.003)
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
13-47
Mechanical Data
MOS Memory Products - Military
28-Lead Ceramic Sidebrazed Dual-In-Line Package (JD Suffix)
Pin 1
1,65 (0.065) MAX
10,688 (0.420)
4,445 (0.175) MAX
9,652 (0.380)
J{E
--1
4, 44 (0.175)
3,180 (0.125)
0,530 (0.021)
0,380 (0.015)
R
Seating Plane -
1, 52 (0.060)
0,381 (0.015)
1,65 (0.065)
0,889 (0.035)
0,380 (0.015)
0,200 (0.008)
2,540 (0.100) NOM
Pin Spacing
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
TEXAS ~
INSTRUMENTS
13·48
POST OFFICE BOX 1443 • HOUSTON. TEXAS 77001
Jl
Mechanical Data
MOS Memory Products - Military
20-Lead Zig-Zag In-line Ceramic Package (ZIP) (SV Suffix)
27,051 (1.0S5)
2S,289 (1.035)
3,05 (0.120) --r---1.
2,54 (0.100)
I'
I r--i
----'-i
Pin 1 Index
9, 525 (0.375)
9,017 (0.355)
=c
!==~~~;T;'n;'V~m~?'Vrg~;T;'n;'V~mT-~
1,27 (:.050)
0,38 (0.015)
L
0,584 (0.023)
JL
U
Plane
5,08 (0.200)
3, 18 (0.125)
O,40S (O.OlS)
l
2,921 (0.115) -+-_+11
23,11 (0.910) - - - - - - + 1
22, Sl (0.890)
(Both Sides)
0= 0:0 =0=0=0=0=0=b=OJ
Seating -
2,159 (0.085)
l
0,38 (0.015)
0,203 (0.008)
1,40 (O.OSO)
1, 14 (0.040) 2 Places
2,540(0.100)
ALL LINEAR DIMENSIONS ARE IN MILIMETERS AND PARENTHETICALLY IN INCHES
TEXAS .."
INsrRUMENTS
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
13-49
Mechanical Data
MOS Memory Products - Military
TEXAS ~
INSTRUMENTS
13·50
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77001
TI Worldwide
Sales Offices
ALABAMA: Huntsville: 4960 Corporate Drive,
Suite 150, Huntsville, AL 35805, (205) 837-7530,
ARIZONA: Phoenix: 8825 N, 23rd Avenue, Suite
100, Phoenix, AZ 85021, (602) 995-1007,
CALIFORNIA: Irvine: 1920 Main Street, Suite
900, Irvine, CA 92714, (714) 660-1200;
San Diego: 5625 Ruffin Road, Suite 100,
San Diego, CA 92123, (619) 278-9600;
Santa Clara: 5353 Betsy Ross Drive,
Santa Clara, CA 95054, (408) 980-9000;
Woodland Hills: 21550 Oxnard Street, Suite 700,
Woodland Hills, CA91367, (818) 704-8100,
COLORADO: Aurora: 1400 S, Potomac Street,
Suite 101, Aurora, CO 80012, (303) 368-8000,
CONNECTICUT: Wallingford: 9 Barnes Industrial
Park South, Wallingford, CT 06492, (203)
269-0074,
FLORIDA: Altamonte Springs: 370 S, North Lake
Boulevard, Suite 1008, Altamonte Springs, FL
32701, (407) 260-2116;
Fort Lauderdale: 2950 N.W. 62nd Street,
Suite 100, Fort Lauderdale, FL 33309, (305)
973-8502;
Tampa: 4803 George Road, Suite 390,
Tampa, FL33634-6234, (813) 885-7588.
GEORGIA: Norcross: 5515 Spalding Drive,
Norcross, GA 30092-2560, (404) 662-7967.
ILLINOIS: Arlington Heights: 515 West
~8~)~~~:2~~~gton Heights, IL 60005,
INDIANA: Carmel: 550 Congressional Drive, Suite
100, Carmel,lN 46032, (317) 573-6400;
Fort Wayne: 103 Airport North Office Park.
Fort Wayne, IN 46825, (219) 489-4697.
KANSAS: Overland Park: 7300 College
Boulevard, Lighton Plaza, Suite 150, Overland
Park, KS66210, (913) 451-4511.
MARYLAND: Columbia: 8815 Centre Park Drive,
Suite 100, Columbia, MD 21045, (410) 964-2003.
MASSACHUSETTS: Waltham: Bay Colony
Corporate Center, 950 Winter Street, Suite 2800,
Waltham, MA02154, (617) 895-9100.
MICHIGAN: Farmington HillS: 33737 W. 12 Mile
Road, Farmington Hills, MI48018, (313) 553-1581;
MINNESOTA: Eden Prairie: 11000 W. 78th Street,
Suite 100, Eden Prairie, MN 55344, (612)
828-9300.
MISSOURI: St. Louis: 12412 Powerscourt Drive,
Suite 125, SI. Louis, MO 63131, (314) 821-8400.
NEW JERSEY: Iselin: Metropolitan Corporate
Plaza, 485 Bldg. E. U.S. 1 South, Iselin, NJ 08830,
(908) 750-1050.
NEW MEXICO: Albuquerque: 2709 J. Pan
American Freeway, N.E., Albuquerque, NM 87101,
(505) 345-2555.
NEW YORK: East Syracuse: 6365 Collamer
Drive, East Syracuse, NY 13057, (315) 463-9291;
Fishkill: 300 Westage Business Center, Suite 140,
Fishkill, NY 12524, (914) 897-2900;
Melville: 48 South Service Road, Suite 100,
Melville, NY 11747, (516) 454-6601;
Pittsford: 2851 Clover Street, Pittsford, NY 14534,
(716) 385-6770.
NORTH CAROLINA: Charlotte: 8 Woodlawn
Green, Charlotte, NC 28217, (704) 527-0930;
Raleigh: 2809 Highwoods Boulevard, Suite 100,
Raleigh, NC 27625, (919) 876-2725.
OHIO: Beschwood: 23775 Commerce Park Road,
Beachwood, OH 44122-5875, (216) 765-7528;
Beavercreek: 4200 Colonel Glenn Highway,
Suite 600, Beavercreek, OH 45431,
(513) 427-6200.
OREGON: Beaverton: 6700 SW. 105th Street,
Suite 110, Beaverton, OR 97005, (503) 643-6758.
PENNSYLVANIA: Blue Bell: 670 Sentry Parkway,
Suite 200, Blue Bell, PA 19422, (215) 825-9500.
~~~~n~~s~if.°~0~~~a~oeA~y~~5RMoo~f~~iI
Plaza
(809) 753-8700.
TEXAS: Austin: 12501 Research Boulevard,
Austin, TX 78759, (512) 250-6769;
Dallas: 7839 Churchill Way, Dallas, TX 75251,
(214) 917-1264;
Houston: 9301 Southwest Freeway, Commerce
Park, Suite 360, Houston, TX 77074,
(713) 778-6592;
Midland: FM1788 & 1-20, Midland, TX 79711-0448,
(915) 561-7137,
UTAH: Salt Lake City: 2180 South 1300 East,
Suite 335, Salt Lake City, UT 541 06,
(801) 466-8972,
WISCONSIN: Waukesha: 20825 Swenson Drive,
Suite 900, Waukesha WI 53186, (414) 798-1001.
CANADA: Nepean: 301 Moodie Drive, Suite 102,
Mallom Center, Nepean, Ontario, Canada K2H
9C4, (613) 726-1970;
Richmond Hili: 280 Centre Street East, Richmond
Hill, Ontario, Canada L4C lBl, (416) 884-9181;
SI. Laurent: 9460 Trans Canada Highway, SI.
Laurent, Quebec, Canada
H4S 1R7, (514) 335-8392.
AUSTRALIA (& NEW ZEALAND): Texas
Instruments Australia Ltd .. 6-10 Talavera Road,
North Ryde (Sydney), New South Wales,
Australia 2113, 2-878-9000; 14th Floor, 380 Street,
Kilda Road, Melbourne, Victoria, Australia 3004,
3-696-1211; 171 Philip Highway, Elizabeth,
South Australia 5112, 8 255-2066.
BELGIUM: Texas Instruments Belgium SA/N,V.,
Avenue Jules Bordellaan II, 1140 Brussels,
Belgium, (02) 242 30 80.
BRAZIL: Texas Instruments Electronicos do Brasil
Ltda .• Av. Eng. Luiz Carlos Berrini, 1461-110,
andar, 04571, Sao Paulo, SP, Brazil, 11-535-5133.
DENMARK: Texas Instruments AlS, Borupvang
2D, 2750 Ballerup, Denmark, (44) 687400.
FINLAND: Texas Instruments OY, Ahertajantle 3,
P,O. Box 86, 02321 Espoo, Finland, (0) 8026517.
FRANCE: Texas Instruments France, 8-10
Avenue Morane-Saulnler, B.P. 67, 78141 VelizyVillacoublay Cedex, France, (1) 3070 1003.
GERMANY: Texas Instruments Deutschland
GmbH., Haggertystrasse I, 8050 Frelsing, (08161)
80-0; Kurfurstendamm 195-196, 1000 Berlin 15,
(030) 8 82 73 65; Dusseldorfer Strasse 40, 6236
Eschborn I, (06196) 8070; Kirchhorster Strasse 2,
3000 Hannover 51, (0511) 64 68-0;
.
Maybachstrasse II, 7302 Osllildern 2 (Nellingen),
(0711) 3403257; Gildehofcenter, Hollestrasse 3,
4300 Essen I, (0201) 24 25-0,
HOLLAND: Texas Instruments Holland B.v"
Hogehilweg 19, Postbus 12995, 1100 AZ
Amsterdam-Zuidoost, Holland, (020) 5602911.
HONG KONG: Texas Instruments Hong Kong Ltd.,
8th Floor, World Shipping Center, 7 Canton Road,
Kowloon, Hong Kong, 737-0338.
HUNGARY: Texas Instruments Representation,
Budaorsi ul.42, 1112 Budapest, Hungary,
(1) 1.666617.
IRELAND: Texas Instruments Ireland Ltd.,
7/8 Harcourt Street, Dublin 2, Ireland,
(01) 755233.
ITALY: Texas Instruments Italia S.pA, Centro
Dlrezlonale Colleonl, Palazzo Perseo-Via
io'!{~m~2; ~J,~~~~~~6a~~~~i~n:~il~g: ~~~y,
~a
00148 Roma, Italy (06) 6572651 ;
Amendola,
17,40100 Bologna, Italy (051) 554004.
JAPAN: Texas Instruments Japan Ltd., Aoyama
Fuji Building 3-6-12 Kita-Aoyama Minato-ku, Tokyo,
Japan 107, 03-498-2111 ; MS Shibaura
Building 9F, 4-13-23 Shlbaura, Mlnato-ku, Tokyo,
Japan 108, 03-769-8700; Nissho-Iwal Building 5F,
2-5-8 Imabashi, Chuou-ku, Osaka, Japan 541,
06-204-1881; Dal-nl Toyota Building Nlshl-kan 7F,
4-10-27 Melekl, Nakamura-ku, Nagoya, Japan 450,
052-583-8691; Kanazawa Oyama-cho Daiichl
Seimei Building 6F, 3-10 Oyama-cho,
~;~~~3~~~~1: ~~l~~;;;~t~~~;';a2gulldln
6F,
1-2-11 Fukashl, Matsumoto-shl, Nagano,
390, 0263-33-1060; Daiichl Olympic Tachlkawa
Building 6F, 1-25-12, Akebono-cho, Tachikawa,
Tokyo, Japan 190, 0425-27-6760; Yokohama
Business Park East Tower 10F, 134 Goudo-cho,
Hodogaya-ku, Yokohama-shl, Kanagawa, Japan
240,045-338-1220; Nihon Seimei Kr.0to Yasaka
Buildin~ 5F, 843-2, Higashi Shlokohj -cho,
Higashl-Iru, Nlshlnotoh-In, Shiokohji-dorl,
Shirmogyo-ku, Kyoto, Japan 600, 075-341-7713;
Sumitomo Seimei Kumagaya Building 8F, 2-44
Yayol, Kumagaya-shi, Saitama, Japan 360,
0485-22-2240; 2597-1, Aza Harudal, Oaza Yasaka,
Kitsuki-shl, Oita, Japan 873, 09786-3-3211.
KOREA: Texas Instruments Korea Ltd., 28th Floor,
Trade Tower, 159, Sam sung-Dong, Kangnam-ku
Seoul, Korea, 2-551-2800.
~apan
~~~X.~!~a~~~~t~~sJ~~~:~~x ~t.I~~~':;r~dn.
Maybank, 100 Jalan Tun Perak, 50050 Kuala
Lumpur, Malaysia, 2306001.
MEXICO: Texas Instruments de Mexico SA de
~l;;i~:o~.~, ~mo,IJ_~I~~~o~f.0dromo Condesa,
NORWAY: Texas Instruments Norge AlS, P.B. 106,
Refstad (Slnsenveien 53), 0513 Oslo 5, Norway,
(02) 155090.
PEOPLE'S REPUBLIC OF CHINA: Texas
Instruments China Inc., Beijing Representative
Office, 7-05 CITIC Building, 19 Jianguomenwal
Dajie, Beijing, China, 500-2255, Ext. 3750.
PHILIPPINES: Texas Instruments Asia Ltd.,
Philippines Branch, 14th Floor, Ba-Lepanto Building,
Paseo de Roxas, Makati, Metro Manila, Philippines,
2-8176031.
PORTUGAL: Texas Instruments Equlpamento
Electronico (Portugal) LOA., lng, Frederico Ulricho,
2650 Moreira Da Maia, 4470 Maia, Portugal
(2) 948 1003.
SINGAPORE (& INDIA, INDONESIA, THAILAND):
~~~\irc~nlsglu~~;~S~~~ta';[,e#~lgl,L~drih:-Jia
-!!1 TEXAS
INSTRUMENTS
Square, Singapore 1130, 3508100,
SPAIN: Texas Instruments Espana SA, c/Gobelas
43, Urbanizasion La Florida, 28023, Madrid, Spain,
(1) 372 8051; c/Diputacion, 279-3-5, 08007
Barcelona, Spain, (3) 317 9180.
SWEDEN: Texas Instruments International Trade
Corporation (Sverigefilialen), Isafjordsgatan Box 30,
164 93 Kista, Sweden, (08) 752 58 00.
SWITZERLAND: Texas Instruments Switzerland
AG, Riedstrasse 6, 8953 Dietikon, Switzerland,
(01) 7442811.
TAIWAN: Texas Instruments Taiwan Limited, Taipei
Branch, 10th Floor, Bank Tower, 205 Tung Hua N.
Road, Taipei, Taiwan, 10592, Republic of China,
2-7139311.
TURKEY: Texas Instruments, DSEG MidEast
Regional Marketing Office, Karum Center,
Suite 442, Iran Caddesl 21, 06680 Kavaklldere,
Ankara, Turkey, 4-468-0155.
UNITED KINGDOM: Texas Instruments Ltd.,
Manton Lane, Bedford, England, MK41 7PA,
(234) 270 111.
A0892
TI North
TI Authorized
American Sales North American
Offices
Distributors
ALABAMA: Huntsvlllo: (205) 837·7530
ARtZONA: Phoenix: (602) 995·1007
CALIFORNIA: Irvlno: (714) 660-1200
San Diogo: (619) 278·9600
Santa Clara: (408) 980-9000
Woodland Hili.: (818) 704-8100
COLORADO: Aurora: (303) 368·8000
CONNECTICUT: Wallingford: (203) 269-0074
AlHance ElectroniCS, Inc. (military product only)
Almae/Arrow
Anthem Electronics
Arrow/Schwaber
Future Electronics (Canada)
GAS Electronics Co., Inc.
Hall-Mark Electronics
Marshall Industries
Newark Electronics
Rochester Electronics, Inc.
(obsolete product only (508) 462-9332)
MICHIGAN: Detroit: Arrow/Schweber (313) 462-2290;
Hall·Mark (313) 416·5800; Marshall (313) 525·5850;
Newark (313) 967·0600.
MINNESOTA: Anthem (612) 944·5454; Arrow/Schweber
(612) 941·5280: Hall·Mark (612) 881·2600; Marshall (612)
559-2211MISSOURI: Arrow/Schweber (314) 567·6888: Hall·Mark
(314) 291·5350; Marshall (314) 291·4650.
NEW JERSEY: Anthem (201) 227·7960; Arrow/Schweber
(201) 227·7880, (609) 596·8000; Hall·Mark (201) 515·3000,
(609) 235·1900; Marshall (201) 882-0320, (609) 234·9100.
NEW MEXICO: Alliance (505) 292·3360.
~~~~~~~~b~(~11~!~~~:.~;ci'3~~a\T.~~r~'fs-16~00;
737·0600: Marshall (516) 273-2424: Zeus (914) 937·7400.
Rochester: Arrow/Schweber (716) 427-0300; Hall-Mark
(716) 425·3300: Marshall (716) 235·7620.
Syracuse: Marshall (607) 785-2345.
NORTH CAROLINA: Arrow/Schweber (919) 876·3132;
Hall·Mark (919) 872·0712: Marshall (919) 878-9882.
OHIO: Cleveland: Arrow/Schweber (216) 248-3990;
~~~~:cte:~~~(~~~~C;hng~bt07) 260·2116
Tampa: (813) 885-7588
GEORGIA: Norcroaa: (404) 662·7967
ILLINOIS: Arlington Heights: (708) 640·3000
INDIANA: Carmol: (317) 573-6400
Fort Wayn.: (219) 489·4697
KANSAS: Overland Park: (913) 451-4511
MARYLAND: Columbia: (410) 964·2003
MASSACHUSETTS: Waltham: (617) 895-9100
MICHIGAN: Farmington Hills: (313) 553·1581
MINNESOTA: Eden Prairie: (612) 828-9300
MISSOURI: St. louis: (314) 821·8400
NEW JERSEY: Isolln: (908) 750·1050
NEW MEXICO: Albuquerquo: (505) 345·2555
NEW YORK: East Syracuse: (315) 463-9291
Fishkill: (914) 897·2900
Molvill.: (516) 454-6600
Pittsford: (716) 385-6770
NORTH CAROLINA: Chorlotte: (704) 527·0930
Rslelgh: (919) 876·2725
OHIO: Beechwood: (216) 765·7258
(205) 837·8700; Marshall (205) 881·9235.
ARIZONA: Anthem (602) 966·6600: Arrow/Schweber (602)
437-0750; Hall·Mark (602) 431·0030: Marshall (602)
496-0290: Wyle (602) 437·2088.
Beavercreek: (513) 427-6200
578·9600: Wyle (619) 565-9171; Zeus (619) 277·9681.
973-6913; Marshall (801) 973·2288: Wyle (801) 974-9953.
WASHINGTON: />Jmac/Arrow (206) 643·9992, Anthem
(206) 483·1700; Marshall (206) 486-5747: Wyle (206)
San Francisco Bay Area: Anthem (408) 453-1200;
881-1150.
Arrow/Schweber (408) 441·9700, (510) 490·9477;
Hall·Mark (408) 432-4000; Marshall (408) 942·4600:
Wyle (408) 727·2500: Zeus (408) 629-4789.
WISCONSIN: Arrow/Schweber (414) 792·0150: Hall·Mark
(414) 797·7644: Marshall (414) 797-8400.
CANADA: Calgary: Future (403) 235-5325;
OREGON: Beaverton: (503) 643·6758
PENNSYLVANIA: Blue Bell: (215) 825·9500
PUERTO RICO: Halo Ray: (809) 753-8700
TEXAS: Auotln: (512) 250·6769
Dalla.: (214) 917-1264
~fdl:~cr:! (~~~) ;~~7~539l
UTAH: Salt Loke City: (801) 466-8972
WISCONSIN: Waukosha: (414) 798·1001
CANADA: Nopaan: (613) 726·1970
Richmond HIli: (416) 884-9181
St. Lourant: (514) 335-8392
Wyle Laboratories
Zeus Components
Dayton: Arrow/Schwaber (513) 435-5563; Marshall (513)
898-4480: Zeus (513) 293·6162.
TI Distributors
ALABAMA: Arrow/Schweber (205) 837-6955; Hall-Mark
CALIFORNIA: Los Angeles/Orange County: Anthem
(818) 775·1333, (714) 768·4444: Arrow/Schweber (818J
Centers
CALIFORNIA: Irvlna: (714) 660·8140
Santa Clara: (408) 748-2222
GEORGIA: Norcross: (404) 662-7945
ILLINOIS: Arlington Halghts: (708) 640-2909
INDIANA: Indlanapollo: (317) 573·6400
MASSACHUSETTS: Waltham: (617) 895-9196
MEXICO: Msxlco City: 491·70834
MINNESOTA: Mlnneapollo: (612) 828·9300
TEXAS: Dalla.: (214) 917·3881
CANADA: Nepean: (613) 726-1970
Customer
Response Center
TOLL FREE:
(800) 336·5236
OUTSIDE USA:
(214) 995-6611
(8:00 a.m. - 5:00 p.m. CST)
OKLAHOMA: Arrow/Schweber (918) 252-7537; Hall-Mark
(918) 254·6110.
OREGON: Almac/Arrow (503) 629-8090; Anthem (503)
643·1114: Marshall (503) 644-5050; Wyle (503) 643·7900.
PENNSYLVANIA: Anthem (215) 443·5150:
f~b~)~~~~;~~( 8ir;h;ff14~~~8~~~15) 922·7037:
~~~~~:~~~)k~¥.~~~~~~;~~~~5(W2n~-i.~~1: Wyle
(512) 345·8853;
~:g~~6~~~:I~J~~:)(tl~'m~~~~~%(;rcs:~~~\~14)
~~n~g~: ~~~h~~~:14~2J~8~~O~~~k(j~lr)4~~35~~~~~~4)
233-5200: Wylo (214) 235·9953: Zeus (214) 783·7010:
(818) 880·9000, (714) 863·9953: Zeus (714) 921·9000,
(818) 889·3838;
Sacramento: Anthem (91S) 624-9744; Hall-Mark (916)
624·9781: Marshall (916) 635·9700; Wyle (916) 638·5282:
879-9953.
UTAH: Anthem (801) 973-8555; Arrow/Schweber (801)
~~~)D~~g~~8~~h~~I_~~~k (g~9~~~;-f~~Ot/~;~:h~?te(~19)
COLORADO: Anthem (303) 790-4500; Arrow/Schweber
(303) 799·0258: Hall·Mark (303) 790-1662; Marshall (303)
451-8383; Wyle (303) 457-9953.
CONNECTICUT! Anthem (203) 575-1575; Arrow/Schweber
(203) 265·7741: Hall-Mark (203) 271·2844: Marshall (203)
265·3822.
FLORIDA: Fort Lauderdale: Arrow/Schweber (305)
429·8200: Halll·Mark (305) 971·9280; Marshall (305)
977-4880.
Orlando: Arrow/Schwaber (407) 333-9300; Hall-Mark (407)
830·5855: Marshall (407) 767-8585; Zeus (407) 788·9100.
Tampa: Hall·Mark (813) 541·7440: Marshall (813)
573-1399.
TI Regional
Technology
Hall-Mark (216) 349-4632: Marshall (216) 248-1788.
Columbua: Hall·Mark (614) 888·3313.
GEORGIA: Arrow/Schweber (404) 497-1300; Hall-Mark
(404) 623-4400: Marshall (404) 923·5750.
ILLINOIS: Anthem (70B) 884·0200; Arrow/Schweber (708)
250-0500; Hall-Mark (312) 860-3800; Marshall (708)
490·0155; Newark (312)764·5100.
INDIANA: Arrow/Schweber (317) 299·2071: Hall-Mark
(317) 872-8875; Marshall (317) 297·0483.
IOWA: Arrow/Schweber (319) 395·7230.
Houston: Arrow/Schweber (713) 530-4700; Hall-Mark
(713) 781·6100; Marshall (713) 467·1666; Wyle (713)
Edmonton: Future (403) 438-2858:
Montreal: Arrow/Schwaber (514) 421-7411; Future (514)
694-7710; Marshall (514) 694·8142
Ottawa: Arrow/Schweber (613) 226-6903; Future (613)
820-8313.
Quebec: Future (418) 897·6666.
~~~~r~t(~ ts')~~~~Z~~~b~~~:~:'1 1:~6r~~~-B046.
Vancouver: Arrow/Schweber (604) 421·2333;
Future (604) 294·1166.0
TI Die Processors
Chip Supply (407) 298-7100
Elmo Semiconductor
Minco Technology Labs
(818) 768-7400
(512) 834-2022
KANSAS: Arrow/Schwaber (913) 541-9542; Hall-Mark
(913) 888-4747; Marshall (913) 492·3121-
MARYLAND: Anthem (301) 995-6640; Arrow/Schweber
(301) 596·7800; Hall·Mark (301) 988·9800; Marshall (301)
622-1118; Zeus (301) 997·1118.
MASSACHUSETTS: Anthem (508) 657·5170;
Arrow/Schwaber (508) 658-0900; Hall-Mark (508)
667·0902; Marshall (508) 658-0810; Wyle (617) 272-7300;
Zeus (617) 246·8200.
~TEXAS
INSTRUMENTS
00892
-!!1
TEXAS
INSTRUMENTS
Printed in U.S.A.
0493-65
SMYD093
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