1993_TI_TSP50C1x_Family_Speech_Synthesizer_Design_Manual 1993 TI TSP50C1x Family Speech Synthesizer Design Manual
User Manual: 1993_TI_TSP50C1x_Family_Speech_Synthesizer_Design_Manual
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TEXAS
INSTRUMENTS
TSP50C1x Family
Speech Synthesizer
1993
Linear Products
TSP50C1x Family
Speech Synthesizer
Design Manual
~TEXAS
INSTRUMENTS
IMPORTANT NOTICE
Texas Instruments Incorporated (Til reserves the right to make changes to its
products or to discontinue any semiconductor product or service without notice,
and advises its customers to obtain the latest version of relevant information to
verify, before placing orders, that the information being relied on is current.
TI warrants performance of its semiconductor products and related software to
current specifications in accordance with TI's standard warranty. Testing and
other quality control techniques are utilized to the extent TI deems necessary to
support this warranty. Specific testing of all parameters of each device is not
necessarily performed, except those mandated by government requirements.
Please be aware that TI products are not intended for use in life-support
appliances, devices, or systems. Use of TI product in such applications requires
the written approval of the appropriate TI officer. Certain applications using
semiconductor devices may involve potential risks of personal injury, property
damage, or loss of life. In order to minimize these risks, adequate design and
operating safeguards should be provided by the customer to minimize inherent
or procedural hazards. Inclusion of TI products in such applications is understood
to be fully at the risk of the customer using TI devices or systems.
TI assumes no liability for applications assistance, customer product design,
software performance, or infringement of patents or services described herein.
Nor does TI warrant or represent that any license, either express or implied, is
granted under any patent right, copyright, mask work right, or other intellectual
property right of TI covering or relating to any combination, machine, or process
in which such semiconductor products or services might be or are used.
Copyright © 1993, Texas Instruments Incorporated
Printed in the U.S.A.
Contents
Section
Title
Page
1
Introduction to the TSP50Clx Family of Devices .................................. 1-1
1.1 Applications........................................................... 1-1
1.2 Description............................................................ 1-1
1.3 TSP50C1x Family Features ............................................... 1-3
1.4 TSP50C12 Features ..................................................... 1-3
1.5 TSP50C14 Features ..................................................... 1-4
1.6 D/A Options ........................................................... 1-4
1.6.1 Two-Pin Push Pull (Option 1) - Accurate to 10 Bits (:t 1/2 LSB) ............ 1-4
1.6.2 Single-Pin Single Ended (Option 2) - Accurate to Only 9 Bits (± 1 LSB) ..... 1-6
1.6.3 Single-Pin Double Ended (Option 3) - Accurate to 10 Bits (± 1/2 LSB) ...... 1-7
1.7 TSP50C10/11 Pin Assignments and Descriptions .............................. 1-8
1.8 TSP50C12 Pin Assignments and Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-11
1.9 TSP50C14 Pin Assignments and Descriptions ................................ 1-12
1.10 Introduction to LPC (Linear Predictive Coding) .............................. 1-13
1.10.1 The Vocal Tract .................................................. 1-13
1.10.2 The LPC Model ................................................. 1-14
1.10.3 LPC Data Compression ........................................... 1-14
2
TSP50Clx Family Architecture ................................................ 2-1
2.1 Read-Only Memory (ROM) ............................................. " 2-3
2.2 Program Counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-3
2.3 Program Counter Stack ................................................. " 2-3
2.4 TSP50ClO/11 Random-Access Memory (RAM) ............................... 2-4
2.5 TSP50C12 Random-Access Memory (RAM) ................................. 2-5
2.6 TSP50C14 Random-Access Memory (RAM) ................................. 2-6
2.7 Arithmetic Logic Unit (ALU) .............................................. 2-6
2.8 A Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-6
2.9 X Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-6
2.10 B Register ............................................................. 2-6
2.11 Status Flag ............................................................ 2-7
2.12 Integer Mode Flag ....................................................... 2-7
2.13 Timer Register ......................................................... 2-7
2.14 Timer Prescale Register .................................................. 2-7
2.15 Pitch Register .......................................................... 2-8
2.16 Speech Address Register ................................................. 2-9
2.17 Parallel-to-Serial Register ................................................. 2-9
2.18 Input/Output Ports ...................................................... 2-9
2.19 Mode Register ......................................................... 2-10
2.20 Speech Synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-11
2.20.1 SynthesizerModeO-OFF ......................................... 2-11
2.20.2 Synthesizer Mode 1 - LPC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-11
iii
Contents (Continued)
Section
2.21
2.22
2.23
2.24
Title
2.20.3 Synthesizer Mode 2 - PCM ........................................
2.20.4 Synthesizer Mode 3 - PCM and LPC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2.20.5 Use of RAM by the Synthesizer .....................................
2.20.6 Frame-Length Control ............................................
2.20.7 Digital-to-Analog Converter ........................................
Interrupts.............................................................
TSP50C12 LCD Functional Description ....................................
2.22.1 TSP50C12 LCD Driver ...........................................
2.22.2 TSP50C12 LCD Drive Type A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2.22.3 TSP50C12 LCD Drive Type B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
TSP50C12 LCD Reference Voltage and Contrast Adjustment ...................
TSP50C12 Clock Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Page
2-12
2-12
2-12
2-13
2-13
2-13
2-14
2-14
2-15
2-17
2-18
2-18
3
TSP50Clx Electrical Specifications ............................................. 3-1
3.1 Absolute Maximum Ratings Over Operating Free-Air Temperature Range .......... 3-1
3.2 TSP50C1x Recommended Operating Conditions .............................. 3-1
3.3 TSP50C1x D/A Options Timing Requirements ................................ 3-1
3.4 TSP50C1x Initialization Timing Requirement ................................. 3-2
3.5 TSP50C1x Write Timing Requirements (Slave Mode) .......................... 3-2
3.6 TSP50C1x Read Timing Requirements (Slave Mode) ........................... 3-3
3.7 TSP50C10/11 Electrical Characteristics Over Recommended Ranges of Supply Voltage
and Operating Free-Air Temperature (unless otherwise noted) .......... . . . . . . . . .. 3-4
3.8 TSP50C12 Electrical Characteristics Over Recommended Ranges of Supply Voltage and
Operating Free-Air Temperature (unless otherwise noted) ....................... 3-5
3.9 TSP50C14 Electrical Characteristics Over Recommended Ranges of Supply Voltage and
Operating Free-Air Temperature (unless otherwise noted) ....................... 3-6
4
TSP50Clx Assembler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
4.1 Description of Notation Used ..............................................
4.2 Invoking the Assembler ..................................................
4.2.1 Command-Line Options ............................................
4.2.1.1
BYTE Unlist Option ......................................
4.2.1.2 DATA Unlist Option ......................................
4.2.1.3 XREF Unlist Option ......................................
4.2.1.4 TEXT Unlist Option ......................................
4.2.1.5 WARNING Unlist Option ..................................
4.2.1.6 Complete XREF Switch ....................................
4.2.1.7 Object Module Switch .....................................
4.2.1.8 Listing File Switch ........................................
4.2.1.9 Page Eject Disable Switch ..................................
4.2.1.10 Error to Screen Switch .....................................
4.2.1.11 Instruction Count Switch ...................................
4.2.1.12 Binary Code File Disable Switch .............................
4.2.2 Assembler Input and Output Files ....................................
4.2.2.1 Assembly Source File .....................................
iv
4-1
4-1
4-1
4-1
4-2
4-2
4-2
4-2
4-2
4-2
4-3
4-3
4-3
4-3
4-3
4-3
4-3
4-3
Contents (Continued)
Section
4.3
4.4
Title
Page
4.2.2.2 Assembly Binary Object File. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-3
4.2.2.3 Assembly Tagged Object File ............................... 4-4
4.2.2.4 Assembly Listing File ..................................... 4-4
Source-Statement Format ................................................. 4-4
4.3.1 Label Field ...................................................... 4-4
4.3.2 Command Field .................................................. 4-5
4.3.3 Operand Field .................................................... 4-5
4.3.4 Comment Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-5
4.3.5 Constants ........................................................ 4-5
4.3.5.1
Decimal Integer Constants .................................. 4-5
4.3.5.2 Binary Integer Constants ................................... 4-5
4.3.5.3 Hexadecimal Integer Constants .............................. 4-6
4.3.5.4 Character Constants ....................................... 4-6
4.3.5.5 Assembly-Time Constants ............ , .. " ................. 4-6
4.3.6 Symbols ........................................................ 4-6
4.3.7 Character String .................................................. 4-7
4.3.8 Expressions .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-7
4.3.8.1
Arithmetic Operators in Expressions .......................... 4-7
4.3.8.2 Parentheses In Expressions ................................. 4-8
Assembler Directives .................................................... 4-8
4.4.1 AORG Directive ............................................... " 4-10
4.4.2 BYTE Directive ................................................. 4-10
4.4.3 COPY Directive ................................................. 4-10
4.4.4 DATA Directive ................................................. 4-10
4.4.5 EQU Directive .................................................. 4-11
4.4.6 END Directive .................................................. 4-11
4.4.7 IDT Directive ................................................... 4-11
4.4.8 LIST Directive .................................................. 4-11
4.4.9 NARROW Directive. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12
4.4.10 OPTION Directive ............................................... 4-12
4.4.10.1 BUNLST - Byte Unlist Option ........................... " 4-12
4.4.10.2 DUNLST-DataUnlistOption ............................. 4-12
4.4.10.3 FUNLST - Byte, Data, and Text Unlist Option ................. 4-13
4.4.10.4 I COUNT - Instruction Count List Option .................... 4-13
4.4.10.5 LSTUNL - Listing Unlist Option ........................... 4-13
4.4.10.6 OBJUNL- Object File Unlist Option ........................ 4-13
4.4.10.7 PAGEOF - Page Break Inhibit Option ....................... 4-13
4.4.10.8 RXREF - Reduced XREF Option . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-13
4.4.10.9 SCRNOF - Screen Error Message Unlist Option ............... 4-13
4.4.10.10 TUNLST - Text Unlist Option ............................. 4-13
4.4.10.11 WARNOFF - Warning Message Unlist Option ................. 4-13
4.4.10.12 XREF - Cross-Reference Listing Enable ..................... 4-13
v
Contents (Continued)
Section
4.4.11
4.4.12
4.4.13
4.4.14
4.4.15
4.4.16
4.4.17
4.4.18
5
vi
Page
Title
4.4.10.13 990- Tagged Object Output Switch ........................ . 4-13
PAGE Directive ................................................ . 4-14
RBYTE Directive ............................................... . 4-14
RDATA Directive ................................................ 4-14
RTEXT Directive ................................................ 4-14
TEXT Directive ................................................. 4-15
TITL Directive .................................................. 4-15
UNL Directive .................................................. 4-15
WIDE Directive ................................................. 4-16
Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-1
5.1 Instruction Format ...................................................... 5-4
5.2 ABAAC - Add B to A ................................................... 5-5
5.3 ACAAC - Add Constant to A Register ...................................... 5-6
5.4 AGEC - A Register Greater Than or Equal To Constant ......................... 5-7
5.5 AMAAC - Add Memory to A Register ...................................... 5-8
5.6 ANDCM - Logical AND a Constant With Memory ............................ 5-9
5.7 ANEC - A Not Equal to Constant ......................................... 5-10
5.8 AXCA - A Times Constant .............................................. 5-11
5.9 AXMA - A Times Memory .......................... . . . . . . . . . . . . . . . . . . . . 5-12
5.10 AXTM - A Times Timer ................................................ 5-13
5.11 BR - Branch If Status Set ................................................ 5-14
5.12 BRA - Branch Always to Address in A Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15
5.13 CALL- Call Subroutine If Status Set ...................................... 5-16
5.14 CLA - Clear A Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-17
5.15 CLB - Clear B Register ................................................. 5-18
5.16 CLX - Clear X Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 -19
5.17 DECMN - Decrement Memory ........................................... 5-20
5.18 DECXN - Decrement X Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-21
5.19 EXTSG - Extended-Sign Mode .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-22
5.20 GET - Get Data From ROM/RAM ........................................ 5-23
5.21 lAC - Increment A Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-25
5.22 IBC - Increment B Register .............................................. 5-26
5.23 INCMC - Increment Memory ............................................ 5-27
5.24 INTGR - Integer Mode ................................................. 5-28
5.25 IXC - Increment X Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-29
5.26 LUAA - Look-up With A Register ........................................ 5-30
5.27 LUAB - Look-up With B Register ......................................... 5-31
5.28 LUAPS - Indirect Look-up With A Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-32
5.29 ORCM - OR Constant With Memory ...................................... 5-33
5.30 RETI - Return From Interrupt ............................................ 5-34
5.31 RETN - Return From Subroutine. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-35
5.32 SALA - Shift A Register Left ............................................ 5-36
5.33 SALA4 - Shift A Register Left Four Bits ................................... 5-37
5.34 SARA - Shift A Register Right One Bit .................................... 5-38
Contents (Continued)
Section
5.35
5.36
5.37
5.38
5.39
5.40
5.41
5.42
5.43
5.44
5.45
5.46
5.47
5.48
5.49
5.50
5.51
5.52
5.53
5.54
5.55
5.56
5.57
5.58
5.59
5.60
5.61
5.62
6
Title
Page
SBAAN - Subtract B Register From A Register .............................. 5-39
SBR - Short Branch If Status Set .......................................... 5-40
SETOFF-Set Processor to Off Mode ...................................... 5-41
SMAAN - Subtract Memory From A Register ............................... 5-42
TAB - Transfer A Register to B Register .................................... 5-43
TAM - Transfer A Register to Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-44
TAMD - Transfer A Register to Memory Direct .............................. 5-45
TAMIX - Transfer A Register to Memory and Increment X Register .............. 5-46
TAMODE - Transfer A Register to Mode Register ............................ 5-47
TAPSC - Transfer A Register to Prescale Register ............................ 5-48
TASYN - Transfer A Register to Synthesizer Register ......................... 5-49
TATM - Transfer A Register to Timer Register ............................... 5-50
TAX - Transfer A Register to X Register ................................... 5-51
TBM - Transfer B Register to Memory ..................................... 5-52
TCA - Transfer Constant to A Register ..................................... 5-53
TCX - Transfer Constant to X Register ..................................... 5-54
TMA - Transfer Memory to A Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-55
TMAD - Transfer Memory to A Register Direct .............................. 5-56
TMAIX - Transfer Memory to A Register and Increment X Register ............. 5-57
TMXD - Transfer Memory Direct to X Register .............................. 5-58
TRNDA - Transfer Random Number into A Register .......................... 5-59
TSTCA - Test Constant With A Register .................................... 5-60
TSTCM - Test Constant With Memory ..................................... 5-61
TTMA - Transfer Timer Register to A Register .............................. 5-62
TXA - Transfer X Register to A Register ................................... 5-63
XBA - Exchange Contents of B Register and A Register ....................... 5-64
XBX - Exchange Contents of B Register and X Register ....................... 5-65
XGEC- X Register Greater Than or Equal to Constant ........................ 5-66
Applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6-1
6.1
6.2
6.3
6.4
6.5
Synthesizer Control ..................................................... 6-1
6.1.1 Speech Coding and Decoding ........................................ 6-1
6.1.2 RAM Usage ..................................................... 6-3
6.1.3 ROM Usage ..................................................... 6-5
6.1.4 Program Overview ................................................ 6-5
6.1.4.1
Initialization ............................................. 6-5
6.1.4.2 Phrase Selection .......................................... 6-6
6.1.4.3 Speech Initialization ....................................... 6-6
6.1.4.4 Level-I-Interrupt Service Routine ............................ 6-6
6.1.4.5 Frame-Update Routine ..................................... 6-6
6.1.5 Synthesis Program Walk-Through .................................... 6-6
Arithmetic Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6-28
Operation of the Multiply Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6-30
Standby Mode ......................................................... 6-30
Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6-30
vii
Contents (Continued)
Section
6.6
6.7
6.8
6.9
Title
6.5.1 Slave-Mode Write Operation .......................................
6.5.2 Slave-Mode Read Operation ........................................
TSP60C18 Interface ....................................................
6.6.1 External ROM Mode .............................................
6.6.2 TSP60C18 I/O Signals ............................................
6.6.3 TSP60C18 Addressing ....... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
6.6.4 TSP60C18 Addressing Modes ......................................
6.6.4.1
TSP60C18 Direct-Addressing Mode .........................
6.6.4.2 TSP60C18 Indirect-Addressing Mode ........................
6.6.5 TSP60C18 Control .... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
6.6.5.1
Initialization of the TSP60C18 .............................
6.6.5.2
Direct-Address Initialization of the TSP60C18 .................
6.6.5.3
8-Bit Indirect-Address Initialization of the TSP60C18 ...........
6.6.5.4 16-Bit Indirect-Address Initialization of the TSP60C18 ..........
6.6.6 Placing the TSP60C18 in a Low-Power Standby Condition ...............
Use of the GET Instruction ...............................................
6.7.1 GET From Internal ROM ..........................................
6.7.2 GET From External ROM .........................................
6.7.3 GET From Internal RAM ..........................................
External ROM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Generating Tones Using PCM ............................................
6.9.1 Operation of the TASYN Instruction in PCM Mode .....................
6.9.2 Timing Considerations in PCM Mode ................................
6.9.3 DTMF Program Walk-Through .....................................
Page
6-31
6-32
6-33
6-33
6-33
6-34
6-34
6-35
6-35
6-36
6-36
6-37
6-37
6-38
6-39
6-39
6-41
6-41
6-42
6-43
6-43
6-43
6-44
6-44
7
Customer Information ........................................................ 7-1
7.1 Development Cycle ..................................................... 7-1
7.2 Summary of Speech Development/Production Sequence ........................ 7-2
7.3 N016 300-Mil Plastic Dual-In-Line Package .................................. 7-3
7.4 FN068 68-Lead Plastic Leaded Chip Carrier (PLCC) Package .................... 7-5
7.5 Ordering Information .................................................... 7-7
7.6 New Product Release Form (TSP50Clx) ..................................... 7-7
7.6.1 New Product Release Form for TSP50CI0A and TSP50CllA .............. 7-8
7.6.2 New Product Release Form for TSP50C12 ............................ 7-10
7.6.3 New Product Release Form for TSP50C14 ............................ 7-12
A
Script Preparation and Speech Development Tools ................................
Al Script Generation .......................................................
Al.l Speaker Selection .................................................
Al.2 Speech Collection .................................................
A.I.3 LPC Editing .....................................................
A.I.4 Pitfalls ..........................................................
A2 Speech Development Tools ...............................................
B
TSPSOC1x Sample Synthesis Program ........................................... B·1
C
External ROM Initialization ................................................... C·1
viii
A·l
A-I
A-I
A-I
A-2
A-2
A-2
Contents (Continued)
Section
Title
Page
D
DTMF Program ............................................................. D-I
E
TSPSOCIO/ll Sample Music Program ..•........................................ E-I
ix
List of Illustrations
TItle
Figure
Page
1-1
TSP5OCI0/11 Functional Block Diagram ....................................... 1-2
1-2
TSP5OC12 Functional Block Diagram ......................................... 1-2
1-3
TSP5OC14 Functional Block Diagram ......................................... 1-3
1-4
D/A Output Waveform for Two-Pin Push Pull (Option 1) .......................... 1-5
1-5
Four-Transistor Amplifier Circuit ........................................... " 1-5
1-6
Operational Amplifier Interface Circuit ........................................ 1-6
1-7
Power Amplifier Interface Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-6
1-8
D/A Output Waveform for Single Ended (Option 2) .............................. 1-7
1-9
One-Transistor Amplifier Circuit ............................................. 1-7
1-10 D/A Output Waveform - Single-Pin Double Ended (Option 3) ...................... 1-8
1-11 Operational Amplifier Interface Circuit ........................................ 1-8
1-12 TSP5OClO/11 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-9
1-13 Power-Up Initialization Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-10
1-14 Oscillator Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ... " 1-10
1-15 TSP5OC12 Pin Assignments
1-11
1-16 TSP5OC14 Pin Assignments
1-12
1-17 LPC-12 Vocal Tract Model ................................................. 1-14
2-1
TSP50Clx System Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-2
2-2
TSP5OClO/11 RAM Map ................................................... 2-4
2-3
TSP5OC12 RAM Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-5
2-4
RAM Map During Speech Generation ........................................ 2-12
2-5
TSP5OC12 LCD Driver Type A Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-16
2--6
TSP5OC12 LCD Driver Type B Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-17
2-7 TSP5OC12 Voltage Doubler ................................................ 2-18
x
3-1
Initialization Timing Diagram ................................................ 3-2
3-2
Write Timing Diagram (Slave Mode) .......................................... 3-2
3-3
Read Timing Diagram (Slave Mode) .......................................... 3-3
6-1
D6 Frame Decoding ....................................................... 6-2
6-2
Speech Parameter Unpacking and Decoding .................................... 6-3
6-3
ACAAC in Extended-Sign Mode ............................................ 6-29
List of Illustrations (Continued)
Figure
6-4
Title
Page
ACAAC in Integer Mode .................................................. 6-30
6-5 Slave-Mode Write Operation ................................................ 6-32
6-6 Slave-Mode Read-Then-Write Operation ...................................... 6-32
6-7 TSP60CI8-to-TSP50Clx Hookup ........................................... 6-36
6-8 Register Connections for GET Instruction ..................................... 6-40
6-9 Parallel-to-Serial Operation for GET 5 Instruction ............................... 6-41
6-10 Operation of TASYN in PCM Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6-44
6-11 Format of Data in A Register Before TASYN .................................. 6-44
7-1
Speech Development Cycle .................................................. 7-1
7-2
TSP50CI0/11/14 16-Pin N Package ........................................... 7-3
7-3
TSP50C12 68-Lead PLCC Package ........................................... 7-5
A-I
SDS5000 ................................................................ A-2
A-2 EVM50CIX .............................................................. A-3
A-3 SEB50CIX .............................................................. A-3
A-4 SEB60CXX .............................................................. A-3
A-5 ADP50C12 .............................................................. A-4
xi
List of Tables
Table
Title
Page
1-1
TSP5OClO/11 Terminal Functions ............................................ 1-9
1-2
TSP5OClO/ll I/O Configurations ............................................ 1-10
1-3
TSP5OC12 Terminal Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-12
1-4
TSP5OC14 Terminal Functions .............................................. 1-13
2-1
Reserved ROM Locations .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-3
2-2
I/O Registers ............................................................ 2-10
2-3
Mode Register ......................................................... " 2-11
2-4
Interrupt-1 Vectors ........................................................ 2-13
2-5
Interrupt-2 Vectors ........................................................ 2-14
2""'{)
TSP5OC12 Display RAM Map ........................ . . . . . . . . . . . . . . . . . . . . .. 2-15
4-1
Switches and Options ...................................................... 4-2
4-2
Summary of Assembler Directives ............................................ 4-9
5-1
TSP50C1x Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-1
5-2
TSP50C1x Instruction Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-3
6-1
D6 Parameter Size ......................................................... 6-2
6-2 Hardware-Fixed RAM Locations ............................................. 6-4
6-3
Other RAM Locations Used in Sample Program ................................. 6-4
6-4
FLAGS Bit Descriptions for Sample Program ................................... 6-5
6-5
ROM Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6-5
6-6
TXA Operation .......................................................... 6-29
6-7 TSP60C18 Pin Functional Descriptions ....................................... 6-34
6-8 TSP6OC18 Pinout ........................................................ 6-34
6-9 TSP6OC18 Addressing Modes .............................................. 6-35
6-10 Indirect Address Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6-35
6-11 Mode Register Control of GET Data Source ................................... 6-40
6-12 Relative Weights of DAC Magnitude Bits ..................................... 6-44
6-13 Sample Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-45
xii
1
Introduction to the TSP50C1x Family of Devices
The TSP50C 1x uses a revol utionary architecture to com bi ne an 8-bit microprocessor, a speech synthesizer,
ROM, RAM, and I/O in a low-cost single-chip system. The architecture uses the same ALU (Arithmetic Logic
Unit) for the synthesizer and the microprocessor, thus reducing chip area and cost and enabling the
microprocessor to do a multiply operation in 1.6 [is. Linear Predictive Coding (LPC) is used to synthesize
high-quality speech at a low data rate.
1.1
Applications
The TSP50C1 x is highly flexible and programmable, making it suitable for a wide variety of applications. Its
low system cost opens up new applications for solid-state speech. They include:
Talking Clocks
Toys
Telephone Answering Machines
Home Monitors
Navigation Aids
Laboratory Instruments
Personal Computers
Inspection Controls
Inventory Controls
Machine Controls
Warehouse Systems
Warning Systems
Appliances
Mailboxes
Equipment for the Handicapped
Learning Aids
Computer-Aided Instruction
Magazine and Direct-Mail Advertisements
Point-of-Sale Displays
1.2
Description
The TSP50C1 x can be divided into several functional blocks (Figure 1-1, 1-2, 1-3). The ALU and RAM are
shared by the speech synthesizer and the microcomputer.
The TSP50C1x implements an LPC-12 speech synthesis algorithm using a 12-pole lattice filter. The internal
microprocessor fetches speech data from the internal or external ROM (TSP60C18), decodes the speech
data, and sends the decoded data to the synthesizer. The microprocessor also interpolates (smooths) the
speech data between fetches. The output of the synthesizer can be used to drive transistor or
integrated-circuit amplifiers. Some digital low-pass filtering is provided inside the TSP50C1x.
The general-purpose microprocessor in the TSP50C1 x is also capable of a variety of logical, arithmetic, and
control functions and can often be used for the nonsynthesis tasks of the customer's application as well.
1-1
Microcomputer
PortA
Port S
~
I
I
I
I/O
I
I
Microprocessorl
I
ROM
I
ALU
Speech
Synthesizer
RAM
~
~
Timing
I
Oscillator
t t
OSC1
I
Analog
Output
I
I
J
DA2
DA1
~
OSC2
Figure 1-1. TSP50C10/11 Functional Block Diagram
SCommon
LCD Outputs
24-Segment
LCD Outputs
Microcomputer
PortA ....-+-.......
PortS ....-+-.......
I/O
Speech
Synthesizer
Microprocessor
RAM
Analog
Output
ROM
Timing
Oscillator
OSC1
OSC2
Figure 1-2. TSP50C12 Functional Block Diagram
1-2
1---+- DA2
1---1-- DA1
Microcomputer
PortA
Port 8
....
I
I
I/O
I
Microprocessor
I
ROM
I
I
I
Speech
Synthesizer
ALU
....
....
.
..
r
.......
RAM
Timing
I
Oscillator
I
...
I
Analog
Output
I
I
DA2
DA1
Figure 1-3. TSP50C14 Functional Block Diagram
1.3
TSP50C1x Family Features
Programmable LPC-12 Speech Synthesizer
8-Bit Microprocessor With 61 Instructions
16 Twelve-Bit Words and 112 Bytes of RAM
4-V to 6-V CMOS Technology for Low Power Dissipation
3 D/A Configurations - Mask Selectable
1a-kHz or 8-kHz Speech Sample Rate
8K-Byte ROM (TSP50C10) or 16K-Byte ROM (TSP50C11/12/14)
10 Software Controllable I/O Lines (9 I/O Lines With Two-Pin D/A Output)
Internal Timer
External Interrupt
Single-Cycle Multiply Instruction
Executes Up to 600,000 Instructions Per Second
Built-in Interface to TSP60C18 Speech ROM
Built-In Slave Mode to Act as Microprocessor Peripheral
1.4
TSP50C12 Features
Direct LCD Drive Capability for an 8 x 24 (192-Segment) Display
1/8 Duty Cycle and 1/4 Bias Drive With On-Chip Voltage Reference
Internal Contrast Adjustment
24 Bytes of Display RAM
Two D/A Configurations - Mask Selectable
Limited Direct Speaker Drive Capability
RC Oscillator Option
1-3
TSPSOC14 Features
1.S
Direct Speaker Drive Capability
Internal Clock Generator That Requires No External Components
Two-Pin D/A Output and 10 Pins of I/O Simultaneously Possible
•
Two D/A Configurations - Mask Selectable
Optional Doubling of the D/A Output
16 Twelve-Bit Words and 48 Bytes of RAM
1.6
D/A Options
The TSP50C1 x offers three D/A (digital-to-analog) output options to match different applications. The DAC
(digital-to-analog converter) is a pulse-width-modulated type with 9 bits or 10 bits of resolution and a 16-kHz
or 20-kHz sampling rate. Each option has a range of 480 to -480 segments per sample period, with two
options having a resolution of ± 1/2 LSB and the third having a resolution of ± 1 LSB.
The DAC produces samples at twice the rate that data is received from the LPC filter. For example, if the
LPC filter is running at approximately 10kHz, then the DAC is running at approximately 20 kHz.
The TSP50C12 and TSP50C14 can be used with a normal-sized pulse width or with the PW2 option. The
PW2 option causes the processor to produce a double-sized pulse width. This results in a higher volume
output, which includes some risk of clipping the output.
1.6.1
Two-Pin Push Pull (Option 1) - Accurate to 10 Bits (±1/2 LSB)
Option 1 works well with a very efficient and inexpensive four-transistor amplifier. It requires two pins, so
the I/O pin B1 is used for the second pin, meaning that only 9 bits of I/O are available. When the DAC is idle,
orthe output value is 0, both pins are high. When the output value is positive, DA1 goes low with a duty cycle
proportional to the output value, while DA2 stays high. When the output value is negative, DA2 goes low
with a duty cycle proportional to the output value, while DA 1 stays high. This option offers a resolution of
10 bits.
Figure 1-4 shows examples of D/A output waveforms with different output values. Each pulse of the DAC
is divided into 480 segments per sample period. For a positive output value x = 0 to 480, DA 1 will go low
for x segments while DA2 stays high. When the DAC is idle or the output value is 0, both DA 1 and DA2 are
high. For a negative value x = 0 to -480, DA2 will go low for Ixl segments while DA 1 stays high.
1-4
480-x
High
DA1
Low
DA2
240
rLJL
x
240
I I
479
High
Low
o
2
0
Output Value = x
where x = 0 to 480
(as shown x = 360)
Output Value = 240
Output Value = 479
1
Output Value
2
= 480
High
DA1
Low
480 + x
High
DA2
Low
lJlJ
Ixl
0
2
Output Value = x
where x = Oto-480
(as shown x = -120)
240
~
240
2
0
Output Value = -240
Output Value = 0
Output Value = -480
Figure 1-4. D/A Output Waveform for Two-Pin Push Pull (Option 1)
Figures 1-5,1--6, and 1-7 show examples of circuits that can be used with this option.
5V
DA1
DA2
Figure 1-5. Four-Transistor Amplifier Circuit
1-5
10kQ
v
1 J.tF
47 kQ
OA1 ----11 f-----f\,/'V'v-_____- i
>----- .. 2.5 V pop
OA2 ----1If-----f\,/'V'v--e-i
10 kQ
V/2
Figure 1-6. Operational Amplifier Interface Circuit
VOO
R1
OA1~-~AA~-----~--__~2
R1
0A2~-~AA~~--e~-~--+-~3
R2
8-Q
Speaker
C1
TSP50C10
2kQ
OUTPUT~-----~~~~~
VSS~------------
NOTES: R1 .. 56 kQ 10%
R2 =2 kQ 10%
C1 =0.022 J.tF 20%
R2 and C1 set low-pass cutoff frequency: fc = 1/(2ltR2 x C1)
For values given above, fc = 3.6 kHz
Gain control can beadded by connecting a 1O-J.tF capacitor in series with a 1O-kQ pot. This series combination
is connected between pins 1 and 8. When this is done, R1 should be increased to approximately 250 kQ.
Figure 1-7. Power Amplifier Interface Circuit
1.6.2
Single-Pin Single Ended (Option 2) - Accurate to Only 9 Bits (± 1 LSB)
Option 2 is designed for use with a single-transistor amplifier, offering the lowest-cost solution and still
retaining all 10 I/O pins. It has only 9 bits of resolution, and the amplifier power consumption is higher than
the four-transistor amplifier mentioned above. It is available on the TSP50C10, TSP50C11, and the
TSP50C14. The duty cycle of the output is proportional to the output value. If the output value is 0, the duty
cycle is 50%. As the output value increases from to the maximum, the duty cycle goes from being high
50% of the time up to 100% high. As the value goes from 0 to the most negative value, the duty cycle
decreases from 50% high to 0%.
°
Each pulse of the DAC is divided into 480 segments per sample period. As shown in Figure 1-8, when the
output value is x = -480 to 480, DA 1 will go low for 1x/2-2401 segments. When the output value is 0, DA 1
goes low for 240 segments.
1-6
NOTE: Using Option 2 causes a click at the beginning and end of speech and (under certain conditions)
during synthesis. Software is available to minimize these clicks.
1x12 + 2401
DA1
High
JlJ
Low
1><12-2401
o
1
2
Output Value = x
where x = 480 to- 480
(as shown x = 240)
DA1
o
1
2
Output Value = 120
o
o
2
Output Val ue = 480
1
2
Output Value = 0
n
~ ~ ~ ~
~: t-
t- Jlf' t- rT- t-
o
2
Output Value = - 480
o
2
Output Value = 2
o
Output Value
2
=478
o
1
Output Value
2
=-240
Figure 1-8. D/A Output Waveform for Single Ended (Option 2)
Figure 1-9 shows an example of a circuit that can be used with option 2.
VDD-------.~------~----~
+
+
O.1-IAF
Disc
SOOO
DA1----~~--_+~
vss-------e------~~--~
Figure 1-9. One-Transistor Amplifier Circuit
1.6.3
Single-Pin Double Ended (Option 3) - Accurate to 10 Bits (±1/2 LSB)
Option 3 is provided for use with operational and power amplifiers. It offers both 10 bits of resolution and
10 I/O pins and is available on the TSP50C1 0, TSP50C11, and the TSP50C12. When the output value is
zero, the D/A output is biased at approximately 1/2 Voo. When the output value is positive, the D/A output
pulses to about 1/2 Voo -1 V. The duty cycle is proportional to the output value. When the output value is
negative, the D/A output pulses to 1/2 Voo+1 V with a duty cycle proportional to the output value.
Figure 1-10 shows examples of D/A output waveforms with different output values. Each pulse of the DAC
is divided into 480 segments per sample period. For a positive output value x = 0 to 480, DA 1 will go low
to 1/2 Voo -1 V for x segments. When the DAC is idle, or the output value is 0, DA1 will go to 1/2 Voo. For
a negative value x = 0 to -480, DA1 will go high to 1/2 VOO + 1 V for Ixl segments.
1-7
1/2VOO+1 V
-rr n.rr
480-x
OA1
1/2VOO
1/2VOO-1 V
x
0
2
0
1/2VOO
_m
--------
479
0
2
2
OU1put Value = 479
OU1put Value = 240
0
2
Output Value = 480
240
Ixl
OA1
1
240
Output Value = x
where x = 0 to 480
(as shown x = 360)
1/2VOO+1 V
T-T---
240
_lliL
480+x
--------
240
1/2VOO-1 V
o
o
2
Output Value = x
where x = 0 to-480
(as shown x = -360)
o
2
1
2
Output Value = 0
Output Value = -240
o
2
Output Value =-480
Figure 1-10. D/A Output Waveform - Single-Pin Double Ended (Option 3)
Figure 1-11 shows an example of a circuit that can be used with option 3.
100 kQ
V
11l-F
47 kQ
OA1 ----lII-----'VV'v-_____---I
>-......-~2Vp·p
10 kQ
VOO/2
Figure 1-11. Operational Amplifier Interface Circuit
1.7
TSP50C10/11 Pin Assignments and Descriptions
Figure 1-12 shows the pin assignments for the TSP50C10/11. Table 1-1 provides terminal functional
descriptions. Table 1-2 shows the possible TSP50C1 0/11 I/O configurations. Figure 1-13 illustrates the
recommended power-up initialization circuit. Note thatthe pull up resistor is required to be lower than 50 kQ.
Figure 1-14 illustrates the recommended clock circuit. Refer to Section 6 for more information on I/O
configuration.
1-8
N PACKAGE
(TOP VIEW)
PA3
PA2
PA1
PA4
PA5
PA6
PAO
PA7
VSS
VDD
INIT
OSC1
OSC2
DA1
PB1/DA2
PBO
Figure 1-12. TSP50C10/11 Pin Assignments
Table 1-1. TSP50C10/11 Terminal Functions
PIN
NAME
NO.
DA1
11
DA2
10t
DESCRIPTION
I/O
a
a
D/A output. Three mask options are available.
D/A output. Three mask options are available.
INIT
6
I
Initialize input. When INIT goes low, the clock stops, the TSP50C10/11 goes
into low-power mode, the program counter is set to zero, and the contents of
the RAM are retained. An INIT pulse of 1 I-ls is sufficient to reset the
processor.
OSC1
7
I
Clock input. Crystal or ceramic resonator between OSC1 and OSC2, or
signal into OSC1. 9.6 MHz for 10-kHz sampling rate or 7.68 MHz for 8-kHz
sampling rate.
OSC2
8
-
PAD-PA7
1-4,13-16
I/O
PBO-PB1
9-10t
I/O
VDD
12
-
5-V supply voltage
VSS
5
-
Ground terminal
Clock return
8-bit bidirectional I/O port
2-bit bidirectional I/O port
t The operation of this pin depends on the D/A option selected.
1-9
Table 1-2. TSP50C10/11 I/O Configurations
MASTER
PIN
4
3
2
1
16
15
14
13
9
10
1·PIN D/A
PAO
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PBO
PB1
1·PIN D/Af
PAO
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PBO
IRQ
2·PIN D/A
PAO
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PBO
OA2
SLAVE
1·PIN D/A
MASTER
1·PIN D/A
6OC18
DO
01
02
03
04
05
06
BUSY/07
CE
CO
C1
C2
C3
PA4
PA5
PA6
SRCK
STR
RIW
RIW
t With external interrupt
VDD
P
1
47 kQ
INIT
Optional
Reset
Switch
O.1I-tF
Figure 1-13. Power-Up Initialization Circuit
TSP5OC1x
eLK
1
OSC1
MQ
OSC2
9.S-MHz or 7.68-MHz
Crystal or Ceramic Resonator
Figure 1-14. Oscillator Circuit
1-10
T
30pF
1.8
TSP50C12 Pin Assignments and Descriptions
Figure 1-15 shows the pin assignments for the TSP50C12. Table 1-3 provides terminal functional
descriptions. The I/O configurations in Table 1-2 also applies to the TSP50C12, but the pin numbers given
are different. Figure 1-13 illustrates the recommended power-up initialization circuit, and Figure 1-14
illustrates the recommended clock circuit. The TSP50C12 is available as a 68-pin PLCC or as a die. Refer
to Section 6 for more information on I/O configuration.
PLCC PACKAGE
(TOP VIEW)
C\J~
~ &5 &5 ~ It:: ~ ~ C\i ~ () () () () () ()
U ()
~OO~~wwwwzzzzzzzz
PB1/DA2
10
VDD
11
12
DA1
VSS
C8
C7
C6
C5
C4
C3
C2
C1
SO
S1
S2
S3
S4
9
8 7
6
5
4 3
2
1 68 67 66 65 64 63 62 61
19
51
NC
NC
NC
NC
NC
S19
S18
S17
S16
S15
20
50
VC1
21
49
VLCD
22
48
VC2
23
47
VX2
24
46
25
45
S14
S13
S12
60
59
58
13
14
57
15
55
16
54
17
53
18
52
56
26
44
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
NC - No internal connection
Figure 1-15. TSPSOC12 Pin Assignments
1-11
Table 1-3. TSP50C12 Terminal Functions
PIN
I/O
DESCRIPTION
NAME
NO.
DA2
10t
12
0
0
D/A output. D/A options 1 and 3 are available.
DA1
PB1
10t
I/O
Bidirectional I/O pin
PBO
9
I/O
D/A output. D/A options 1 and 3 are available.
Bidirectional I/O pin
INIT
5
I
Initialize input. When INIT goes low, the clock stops, the
TSP50C12 goes into low-power mode, the program counter is set
to zero, and the contents of the RAM are retained. An INIT pulse
of 1 [!S is sufficient to reset the processor.
OSC1:j:
7
I
Clock input. Crystal or ceramic resonator between OSC1 and
OSC2, or signal into OSC1. 9.6 MHz for 1O-kHz sampling rate or
7.68 MHz for 8-kHz sampling rate.
OSC2:j:
8
-
PAO-PA7
31-38
I/O
8-bit bidirectional I/O port
C1-C8
14-21
0
LCD common lines (rows)
SEG1-SEG24
1-4,22-26,
28-30,39-41,
43-46, 51 -55
0
LCD segment lines (columns)
VC1
50
-
VC2
48
-
Voltage doubler capacitor connection
VX2
47
5-V supply voltage
Ground terminals
VLCD
49
VDD
11,27
-
VSS
6,13,42
-
Clock return
LCD supply voltage
t The operation of this pin depends on the D/A option selected.
:j: Ceramic resonator requires two pins. RC oscillator requires one pin for timing and one buffered clock output for trim
monitoring.
1.9
TSP50C14 Pin Assignments and Descriptions
Figure 1-16 shows the pin assignments for the TSP50C14. Table 1-4 provides terminal functional
descriptions. The I/O configurations in Table 1-2 apply to the TSP50C14 with the exception of the pin
numbering and the DA2 pin assignment. Figure 1-13 illustrates the recommended power-up initialization
circuit for the TSP50C14. For most configurations, OSC1 should be tied to either Vss or VDD. Refer to
Section 6 for more information on I/O configurations.
N PACKAGE
(TOP VIEW)
PA3
PA2
PA1
PAO
Vss
INIT
OSC1
PBO
PA4
PA5
PAS
PA7
DA1
DA2
VDD
PB1
Figure 1-16. TSP50C14 Pin ASSignments
1-12
Table 1-4. TSP50C14 Terminal Functions
PIN
NAME
NO.
DA1
11
DA2
12
INIT
6
OSC1
DESCRIPTION
I/O
0
0
D/A output. D/A options 1 and 2 are available.t
D/A output. D/A options 1 and 2 are available.t
I
Initialize input. When INIT goes low, the clock stops, the TSP50C14 goes
into low-power mode, the program counter is set to zero, and the contents
of the RAM are retained. An INIT pulse of 1 [.IS is sufficient to reset the processor.
Clock input. When not in use, OSC1 should be tied to VSS or VDD.
7
I
PAD-PA7
1-4,13-16
I/O
8-bit bidirectional I/O port
PBO-PB1
8-9
I/O
2-bit bidirectional I/O port
VDD
10
VSS
5
-
5-V supply voltage
Ground terminal
t Both DA1 and DA2 are driven with the same levels, if option 2 is selected.
1.10
Introduction to LPC (Linear Predictive Coding)
The LPC-12 system uses a mathematical model of the human vocal tract to enable efficient digital storage
and recreation of realistic speech. To understand LPC, it is essential to understand how the vocal tract
works. This introduction, therefore, begins with a short description of the vocal tract, after which the LPC
model and data compression techniques are addressed. A short discussion of the techniques and pitfalls
of collecting, analyzing, and editing speech for LPC synthesis is included in Appendix A. For more
information, contact your TI Field Sales Representative or Regional Technology Center.
1.10.1
The Vocal Tract
Speech is the result ofthe interaction among three elements in the vocal tract-air from the lungs, a restriction
that converts the air flow to sound, and the vocal cavities that are positioned to resonate properly.
Air from the lungs is expelled through the vocal tract when the muscles of the chest and diaphragm are
compressed. Pressure is used as a volume control with higher pressure for louder speech.
As air flows through the vocal tract, it makes little sound if there is no restriction. The vocal cords are one
type of restriction. They can be tightened across the vocal tract to stop the flow of air. Pressure builds up
behind them and forces them open. This happens over and over, generating a series of pulses. The tension
on the vocal cords can be varied to change the frequency of the pulses. Many speech sounds, such as the
A sound, are produced by this type of restriction, which is called voiced speech.
A different type of restriction in the mouth causes a hissing sound called white noise. The S sound is a good
example. White noise occurs when the tongue and some part of the mouth are in close contact or when the
lips are pursed. This restriction causes high flow velocities that cause turbulence that produces white noise,
which is called unvoiced speech.
The pulses from the vocal cords and the noise from the turbulence have fairly broad, flat spectral
characteristics. In other words, they are noise, not speech. The shape of the oral cavity changes noise into
recognizable speech. The positions of the tongue, the lips, and the jaws change the resonance of the vocal
tract, shaping the raw noise of restricted airflow into understandable sounds.
1-13
1.10.2
The LPC Model
The LPC model incorporates elements analogous to each of the elements of the vocal tract previously
described. It has an excitation function generator that models both types of restriction, a gain multiplication
stage to model the possible levels of pressure from the lungs, and a digital filter to model the resonance in
the oral and nasal cavities.
Figure 1-17 shows the LPC model in schematic form. The excitation function generator accepts coded pitch
information as an input and can generate a series of pulses similar to vocal cord pulses. It can also generate
white noise. The waveform is then multiplied by an energy factor that corresponds to the pressure from the
lungs. Finally, the signal is passed through a digital filter that models the shape of the oral cavity. In the
TSP50C1 x, this filter has twelve poles, so the synthesis is referred to as LPC-12.
Pitch
Periodic
...IlIlIL/L
LPC-12
Digital
Filter
i
White Noise
~
Energy
DAC
r
K1-K12
Filter
Coefficients
Figure 1-17. LPC-12 Vocal Tract Model
1.10.3
LPC Data Compression
The data compression for LPC-12 takes advantage of other characteristics of speech. Speech changes
fairly slowly, and the oral and nasal cavities tend to fall into certain areas of resonance more than others.
The speech is analyzed in frames generally from 10 ms to 25 ms long. The inputs to the model are calculated
as an average for the entire frame. The synthesizer smooths or interpolates the data during the frame so
that there is not an abrupt transition at the end of each frame. Often speech changes even more slowly than
the frame.
The Texas Instruments LPC model allows for a repeat frame in which the only values changed are the pitch
and the energy. The filter coefficients are kept constant from the previous frame. To take advantage of the
recurrent nature of resonance in the oral cavity, all the coefficients are encoded with anywhere from seven
to three bits for each coefficient. The coding table is designed so that more coverage is given to the
coefficient values that occur frequently.
1-14
2
TSP50C1x Family Architecture
As shown in the block diagram in Figure 2-1, the major components of the TSP50C1x are a speech
synthesizer, an 8-bit microprocessor, an internal 8K-byte (TSP50C10) or 16K-byte (TSP50C11/12/14)
ROM, and input/output ports.
When synthesis is disabled, instructions are fetched by the microprocessor from the ROM 600,000 (1 O-kHz
speech sample rate) or 480,000 (8-kHz speech sample rate) times per second. These instructions control
the actions of the TSP50C1 x. By placing different instruction patterns in the ROM, the TSP50C 1x can be
programmed to accomplish a wide variety of tasks. To generate speech, the processor accesses speech
data from either the internal ROM or an external source such as a TSP60C18 speech ROM, an EPROM,
or a host processor. Once the data has been read, the processor must unpack and decode the individual
speech parameters and store the results in a dedicated section of the RAM.
The synthesizer shares access to the RAM and addresses the individual parameter locations as needed
when generating speech. The instruction execution rate slows to 280,000 or 224,000 instruction cycles per
second during synthesis because the synthesizer also shares the ALU (Arithmetic Logic Unit) and ROM
data paths with the microprocessor. The microprocessor must perform interpolation during each frame as
well as fetch the data for the next frame.
The I/O consists of one 8-bit bidirectional port (Port A) and one 2-bit bidirectional port (Port B). Each bit can
be software configured for input or output and for push pull or open drain (no pullup driver). There are two
specialized I/O modes for specific functions. Slave mode configures the TSP50C1x to act as a peripheral
to a host microprocessor. External ROM mode allows the TSP50C1 x to interface with a TSP60C18 speech
ROM.
2-1
D/A Output
Figure 2-1. TSP50C1x System Block Diagram
2-2
2.1
Read-Only Memory (ROM)
The TSP50C1 0 has an 8K-byte ROM. The TSP50C11 /12/14 each have a 16K-byte ROM. It can be used
for program instructions and speech data as required by the application. Certain locations in the ROM,
described in Table 2-1, are reserved for specific purposes.
Table 2-1. Reserved ROM Locations
FUNCTION
ADDRESS
0000
Execution start location after INIT rising edge
0010-001F
Interrupt start locations (see Section 2.21)
1FEO-1FFF
Texas Instruments test code for TSP50C1 0
3FEO-3FFF
Texas Instruments test code for TSP50C11/12/14
The ROM may be accessed in the following four ways:
2.2
1.
The program counter is used to address processor instructions.
2.
The GET instruction can be used to transfer 1 to 8 bits from the ROM to the A register. The GET
counter is initialized by the LUAPS instruction. The SAR (speech address register) points to the
ROM location to be used.
3.
The LUAA instruction can be used to transfer a byte from the ROM into the A register. The value in
the A register when LUAA is executed points to the ROM address to be used.
4.
The LUAB instruction can be used to transfer a byte from the ROM into the B register. The value in
the A register when LUAB is executed points to the ROM address to be used
Program Counter
The TSP50C1 x has a 14-bit program counter that points to the next instruction to be executed. After the
instruction is executed, the program counter is normally incremented to point to the next instruction.
The following instructions modify the program counter:
BR
BRA
SBR
CALL
RETN
RETI
2.3
-
branch
branch to address in A register
short branch
call subroutine
return from subroutine
return from interrupt
Program Counter Stack
The program counter stack has three levels. When a subroutine is called or an interrupt occurs, the contents
of the program counter are pushed onto the stack. When an RETN (return from subroutine) or an RETI
(return from interrupt) is executed, the contents of the top stack location are popped into the program
counter.
2-3
2.4
TSP50C10/11 Random-Access Memory (RAM)
The TSP50C10/11 RAM has 128 locations (Figure 2-2). The first 16 RAM locations are used by the
synthesizer and are 12 bits long. The remaining 112 locations are 8 bits long. When not synthesizing speech,
the entire RAM may be used for algorithm data storage. The I/O control registers are also mapped into the
RAM address space from 80 to 87. For more information, see Section 2.18.
11
10
9
8
7
6
5
4
3
2
Address
0
IIIIIIIIIIIII
00 (Synthesis RAM)
01
OE
OF
10 (General-Purpose RAM)
11
7E
7F
80 (I/O)
81
86
I
IIIIIII
I
87
Figure 2-2. TSP50C10/11 RAM Map
2-4
2.5
TSP50C12 Random-Access Memory (RAM)
The TSP50C12 RAM has 1612-bit synthesizer RAM locations and 112 8-bit general purpose RAM locations
(Figure 2-3). The RAM also has 24 8-bit display RAM locations and one 4-bit contrast adjustment register.
The I/O ports are mapped into RAM address space from FO-F7.
11
10
9
8
7
6
5
4
3
2
1
0
Address
I I I I I I I I I I I I I :~y~esISRAM)
OE
OF
10 (General-Purpose RAM)
11
7E
7F
80 (Display)
81
96
97
111111111
98 (Contrast)
FO (I/O)
II I I I I I I I I
F1
I
F6
II I I I I I I I
F7
Figure 2-3. TSP50C12 RAM Map
2-5
2.6
TSP50C14 Random-Access Memory (RAM)
The TSP50C14 RAM has the same RAM layout as the TSP50C1 0/11 (see Figure 2-2) with one exception.
The general-purpose RAM location range is from 10 to 3F.
2.7
Arithmetic Logic Unit (ALU)
The ALU performs arithmetic and logic functions for the microprocessor and the synthesizer. The ALU is
14 bits in length, providing the resolution needed for speech synthesis. When 8-bit data are transferred to
the ALU, they are right justified. The input to the upper 6 bits may be either zeros (integer mode) or equal
to the MSB of the 8-bit data (extended-sign mode) depending on the arithmetic mode selected using the
EXTSG and INTGR instructions. See the description of each instruction for specific information. All bit and
comparison operations are performed on the lower 8 bits. The ALU is capable of doing an 8-bit by 14-bit
multiply with a 14-bit scaled result in a single instruction cycle.
2.8
A Register
The A register or accumulator is the primary 14-bit register and is used for arithmetic and logical operations.
Its contents can be transferred to or from ROM, RAM, and most of the other registers. The contents are
saved in a dedicated storage register during level-1 interrupts and restored by the RETI instruction.
A Register
13 12 11
10
8
9
I I I I I I
2.9
765
4
2
3
o
I I I
X Register
The X register is an 8-bit register used as a RAM index register. All RAM access instructions except for the
direct-addressing instructions TAMD, TMAD, and TMXD use the X register to point to a specific RAM
location. The X register can also be used as a general-purpose counter. The contents of the X register are
saved during level-1 interrupts and restored by the RETI instruction. If a RAM location with an illegal address
is loaded via the X register, the EVM board with the TSE chip will accept it, but a problem will appear on the
TSP chip.
765
I
2.10
X Register
432
I
0
I
I
B Register
The 14-bit B register is used for temporary storage. It is helpful for storing a RAM address because it can
be exchanged with the X register using the XBX instruction. The B register can be added to, subtracted from,
or exchanged with the A register, making it useful for data storage after calculations. The contents of the
B register are saved during level-1 interrupts and restored by the RETI instruction.
B Register
13 12 11
10
9
8
765
I I I I I I I I I
2-6
4
3
2
o
2.11
Status Flag
The status flag is set or cleared by various instructions depending on the result of the instruction. Refer to
the individual description of instructions in Section 5 to determine the effect an instruction has on the value
of the status flag. The BR, SBR, and CALL instructions are conditional, modifying the program counter only
when the status flag is set. The value of the status flag is unknown at power up. Therefore, if the first
instruction after power up is one of these conditional instructions, the execution of the instruction cannot be
predicted. The value of the status flag is saved during interrupts and restored by the RETI instruction.
Status Flag
o
D
2.12
Integer Mode Flag
The integer mode flag is set by the INTGR instruction and cleared by the EXTSG instruction. When the
integer mode flag is set (integer mode), the upper bits of data less then 14 bits in length will be zero filled
when being transferred to, added to, or subtracted from the A and B registers. When the integer mode flag
is cleared (extended-sign mode), the upper bits of data less than 14 bits in length will be sign extended when
being transferred to, added to, or subtracted from the A and B registers. The value of the integer mode flag
is saved during interrupts and restored by the RETI instruction.
Integer Mode Flag
o
D
2.13
Timer Register
The a-bit timer register is used for generating interrupts and for counting events. It decrements once each
time the timer prescale register goes from 00 to FF. It can be loaded using the TATM instruction and
examined with the TIMA instruction. When it decrements from 00 to FF, a level-2 interrupt request is
generated. If interrupts are enabled and no interrupt is being processed already, an immediate interrupt
occurs; if not, the interrupt request remains pending until interrupts are enabled. The timer continues to
count whether or not it is reloaded. The timer will not decrement before it is initialized. However, on the EVM,
the timer will decrement after a STOP/RUN.
Timer Register
765
432
I I
2.14
0
I I I
I
Timer Prescale Register
The a-bit timer prescale register is a programmable divider between the processor clock and the timer
register. When it decrements from 00 to FF, the timer register is also decremented. The timer prescale
register is then reloaded with the value in its preset latch, and the counting starts again.
The timer prescale register clock comes from an internal clock. The internal clock runs at 1/16 the clock
frequency of the chip; thus, the timer prescale register decrements once every instruction cycle when not
in LPC mode. The TAPSC instruction loads the timer prescale register's preset latch. If the timer has not
yet been initialized with the TATM instruction, the TAPSC instruction also loads the timer prescale register.
Timer Prescale Register
765
I I
4
321
I
0
I
2-7
2.15
Pitch Register
Although the 14-bit pitch register and pitch period counter are part of the synthesizer, they affect the
microprocessor in many ways. The pitch period counter controls the timing of the periodic impulse
(excitation function) that simulates the vocal cords. On the TSP50C1 x, the pitch period counter is also used
to control the interpolation of all speech parameters during each frame. This pitch-synchronous interpolation
helps to minimize the inevitable noise from interpolation by making it occur at the lowest energy part ofthe
speech and by making it a harmonic of the speech fundamental frequency.
The pitch register is used when LPC speech is being synthesized. The following discussion presumes that
the LPC mode is active. The pitch register is loaded with the TASYN instruction. When speech starts, the
pitch period counter is cleared. The pitch period counter is decremented by 2016 for each speech sample,
with speech samples occurring at an 8-kHz or 1O-kHz rate. When the pitch period counter decrements past
zero, the pitch register is added to it. When the pitch period counter goes below 20016 or when a pitch register
is added to it with a result less than 20016, a level-1 interrupt occurs. This interrupt can be used for
interpolation. The excitation function is put out when the pitch period counter is between 14016 and 00. For
further information, see Section 6.
13 12 11
10
9
Pitch Register
8
7
6
5
I I I I I
4
3
2
o
I I
I I I
For voiced or unvoiced frames, the LSB and the MSB ofthe A register must be zero when data is transferred
from the A register to the pitch register with the TASYN instruction (see the following illustration). If this is
not done, problems with the TSP50C1 x chip may occur. Also, these problems may not be apparent when
using the TSE50C1x chip.
A Register
13 12 11
10
9
8
7
6
5
4
3
2
o
4
3
2
o
I I I I I I I I I I
0
Pitch Register
13 12 11
10
9
8
7
6
5
I I I I I I I I I
0
For voiced frames, the pitch register must be loaded with a value no higher than 1FFE 16 . In addition, there
are three recommendations for the minimum pitch register value for voiced frames. First, it is required that
the pitch register value be 4216 or higher. If this is not done, problems with the TSP chip may occur which
are not apparent with the TSE Chip. Second, it is strongly recommended that the pitch register be loaded
with a value of 14216 or higher. This permits the complete excitation pulse to be used in the LPC synthesis.
Third, for best results with the recommended software algorithms, a pitch register value of 20216 or higher
is recommended. The requirement that the pitch register value be less than or equal to 1FFE16 and the
recommendation of a value greater than or equal to 14216 result in a pitch range of 39 Hz to 994 Hz when
operating with a 1O-kHz sample rate.
For unvoiced frames, the pitch register is required to be loaded with a value between 4216 and 3FE16. If this
is not done, problems with the TSP chip may occur which are not apparent with the TSE chip.
2-8
2.16
Speech Address Register
The speech address register (SAR) is a 14-bit register that is used to point to data in internal ROM. The
LUAPS instruction transfers the value in A to the speech address register and loads the parallel-to-serial
register (see Section 2.17) with the internal ROM value pointed to by the SAR. The GET instruction can then
be used to bring 1 to 8 bits at a time from the parallel-to-serial register into the accumulator. Whenever the
parallel-to-serial register becomes empty, it is loaded with the internal ROM value pointed to by the SAR,
and the SAR is incremented.
Speech Address Register
13 12 11
10
9
8
I I I I I I I
2.17
7
6
5
4
2
3
o
I I
Parallel-to-Serial Register
The 8-bit parallel-to-serial register is used primarily to unpack speech data. It can be loaded with 8 bits of
data from internal ROM pointed to by the speech address register, internal RAM pointed to by the X register,
or external TSP60C18 speech ROM pointed to by the SAR in the TSP60C 18. The LUAPS instruction is used
to initialize the parallel-to-serial register and zero its bit counter. GET instructions can then be used to
transfer one to eight bits from the parallel-to-serial register to the accumulator. When the parallel-to-serial
register is empty, it is automatically reloaded. When the GET is from RAM, however, the X register is not
automatically incremented. The EXTROM and RAMROM bits in the mode register control the source for the
parallel-to-serial register. See the speech address register description in Section 2.16 for more information.
Parallel-to-Serial Register
765 4 321
0
I I
2.18
I
Input/Output Ports
Ten bidirectional lines - 8-bit Port A and 2-bit Port B - are available for interfacing with external devices. Each
bit is individually programmable as an input or an output under the control of the respective data direction
register. In addition, each output bit can be individually programmed using the pullup enable register for one
of two output modes - push pull or open drain (no pullup). Each input bit can be programmed by the same
register for resistive pull up or high impedance. The four registers associated with each of the two I/O ports
are memory mapped. Only two bits of Port B are available on the outside of the chip, and the states of the
upper six bits of its registers are undetermined. Transfers from any of the I/O port registers to the A register
leave the upper six bits (bits 13-9) of the A register undetermined. Details of the I/O registers are shown
in Table 2-2.
2-9
Table 2-2. I/O Registers
REGISTER
Data Input Register
Pullup Enable Register
Data Direction Register
Data Output Register
LOCATIONt
PORTB
84
85
86
87
TYPE
(DIR)
(PER)
(DDR)
(DOR)
PORTA
80
81
82
83
Read Only
Read/Write
Read/Write
Read/Write
t For the TSP50C12, the register locations are FO-F7.
DESIRED PIN FUNCTION
Input, High Impedance
Input, Internal Pullup
Output, Active Pullup
Output, Active Pullup
Output, Open Drain
Output, Open Drain
DOR
X
X
0
1
0
1
DDR
0
0
1
1
1
1
PER
0
1
0
0
1
1
PIN STATE
High Impedance
Passive Pullup
0
1
0
High Impedance
A read of the DDR, PER, and DOR registers indicates the last value written to them.
A read of the DIR always indicates the actual level on the I/O pin, which is true even when the DDR is set
for output. This allows true bidirectional data flow without having to switch the port between input and output.
To avoid high-current conditions, this should only be attempted on pins set for open drain with a 1 written
to the data register.
Leaving a high-impedance I/O pin unconnected could cause power consumption to rise while the processor
is in run mode. The power consumption will be between VDD and VSS, with no increase in current through
the input. This should cause no problem with device functionality.
When the part is in standby mode, unconnected high-impedance pins have no effect on either power
consumption or device functionality.
The I/O can also be put in slave mode, making the TSP50C1x usable as a peripheral to a host
microprocessor. Port A can be connected to an 8-bit data bus and controlled by R/W (Port B 1) and chip
enable (Port BO). A read (R/W high and chip enable low) puts the Port A output latch values out on Port A.
A write (R/W low and chip enable low) latches the value on the data bus into the Port A input latch. In addition,
bit 7 of the A output latch is cleared. This makes it possible to use A7 as a write handshake line. Any lines
that are to be used on the data bus in this mode should be configured as inputs.
In external ROM mode, the TSP50C1 x can be interfaced easily to a TSP60C18 speech ROM. Port BO is
used as a chip enable strobe output to the TSP60C18, and Port A7 is used as a clock. Port AO to A3 are
used for address and data transfer, and one other bit must be used for read/write control ofthe TSP60C18.
When the two-pin push-pull option is selected for the D/A output on the TSP50C1 0/11/12, Port B 1 is used
for the second D/A pin, making it unavailable for I/O. In this case, no attempt should be made to use the B1
interrupt.
If the PCM and LPC mode register bits are both cleared, a high-to-Iow transition on B1 causes a level-1
interrupt. This can be used to generate an interrupt with an external event.
2.19
Mode Register
The mode register (Table 2-3) is an 8-bit write-only register that controls the operating mode of the
TSP50C1x. When the INIT pin goes low, all mode register bits are cleared. The mode register is not saved
during a subroutine call or interrupt.
2-10
2.20
Speech Synthesizer
The task of generating synthetic speech is divided between the programmable microprocessor and the
dedicated speech synthesizer. The four speech synthesizer modes, which are set by the LPC and PCM bits
in the mode register, are discussed in the following paragraphs.
Table 2-3. Mode Register
654
7
UNV
MASTER
BIT NAME
I RAMROM I EXTROM I
3
2
1
ENA2
PCM
LPC
BIT LOW
o
1 ENA1
BIT HIGH
ENA1
Disables level-1 interrupt
Enables level-1 interrupt
LPG
Disables LPG processor - all instruction cycles
used by the microprocessor.
Enables LPG processor - 53% of instruction
cycles dedicated to LPG synthesis.
PGM
Disables PGM mode. Level-1 interrupt is either
PPG < 20016 in LPG mode or pin 81 otherwise.
Enables PGM mode. LPG high causes an interrupt
rate of fosc/960 and microprocessor control of
LPG excitation value. LPG low causes an interrupt
rate of fosc/480 and microprocessor control of
D/A register.
ENA2
Disables level-2 interrupt
Enables level-2 interrupt
EXTROM
Disables operation of external ROM hardware
interface.
Enables operation of external ROM hardware
interface.
RAMROM
Enables data source for GET instructions to be
either internal or external ROM.
Enables data source for GET instructions to be
internal RAM.
MASTER
Enables I/O master operation. All available I/O
pins are controlled by internal microprocessor.
Enables I/O slave operation. Pin 80 becomes
hardware chip enable strobe, and 81 becomes
R/W. Port A is controlled by 80 and 81.
UNV
Enables pitch-controlled excitation sequence
when in LPG mode (PGM low, voiced).
Enables random excitation sequence when in LPG
mode (PGM low, unvoiced).
2.20.1
SyntheSizer Mode 0 - OFF
When the PCM and LPC bits are both cleared, the synthesizer is disabled. All instruction cycles are devoted
to the microprocessor. The TASYN instruction transfers the A register to the pitch register, making it easy
to load the pitch register before starting the LPC synthesizer. In this mode, the level-1 interrupt is triggered
by a high-to-Iow transition on pin B1.
2.20.2
SyntheSizer Mode 1 - LPC
This is the normal speaking mode. The TASYN instruction loads the pitch register, and the level-1 interrupt
is triggered by the pitch register going below 20016. Fifty-three percent of the instruction cycles are used
by the synthesizer.
The microprocessor controls speech synthesis by unpacking and decoding parameters, by setting the
update interval (frame rate), and by interpolating the parameters during the frame. The speech synthesizer
acts as a 12-pole digital lattice filter, a pitch-controlled or white-noise excitation generator, a 2-pole digital
low-pass filter, and a digital-to-analog converter. Speech parameter input is received from dedicated space
in the microprocessor RAM, and speech samples are generated at 8 kHz or 10kHz. Communication
between the microprocessor and the speech synthesizer takes place via a shared memory space in the
microprocessor RAM. Refer to Section 6 for more information.
2-11
2.20.3
Synthesizer Mode 2 - PCM
This mode is used for tone and music generation or for very-high-bit-rate speech. The microprocessor uses
all the instruction cycles, and the TASYN instruction transfers the A register directly to the D/A register. The
level-1 interrupt occurs at a rate twice the speech sample rate (16 kHz or 20 kHz), giving access to the
unfiltered D/A output.
2.20.4
Synthesizer Mode 3 - PCM and LPC
When both the PCM and LPC bits are set, the LPC synthesizer runs normally with its excitation function
provided by software. The level-1 interrupt occurs at the speech sample rate, and the TASYN instruction
transfers the A register to the excitation function input of the synthesizer. This mode is included for use with
RELPS (Residual Encoded Linear Predictive Synthesis) and similar techniques. The synthesizer takes 50%
of the instruction cycles in this mode.
2.20.5
Use of RAM by the Synthesizer
The synthesizer uses locations 01 to OF in the RAM. When synthesis is taking place, the parameters for the
synthesizer come directly from these RAM locations. The addresses are shown in Figure 2-4.
Address 11
10
9
8
7
6
5
4
3
2
00
not used for synthesis
01
Energy
02
K12 (LPC-12 values)
03
K11
04
K10
05
K9
06
K8
07
K7
08
K6
09
K5
OA
K4
08
K3
OC
K2
00
K1
OE
C1 (low-pass filter)
OF
C2
Figure 2-4. RAM Map During Speech Generation
2-12
Comments
0
2.20.6
Frame-Length Control
The frame length is controlled by: a) The value put into the prescale register and b) The range over which
the timer is allowed to vary. Typical synthesis and interpolation routines let the timer decrement through a
range of fixed size, so the prescale value should be selected to give the proper frame duration based on
the timer's range.
2.20.7
Digital-to-Analog Converter
The TSP50C1x contains an internal digital-to-analog converter (DAC) connected to the output of the
synthesizer. The DAC is available in three pulse-width-modulated forms for the TSP50C10/11 and two
pulse-width modulated forms for the TSP50C12/14. See Section 1.6 for more information. The DAC outputs
samples at a rate given by fosc/480. For a 9.6-MHz oscillator, this results in an output sample rate of 20
kHz. For a 7.68-MHz oscillator, this results in an output sample rate of 16 kHz. The DAC output rate is twice
the speech sample rate, with a digital low-pass filter in all modes except PCM mode. When the synthesizer
is off (mode 0), the DAC goes to an off state. This state is the same as a zero state for the two-pin and
double-ended one-pin modes, but in the single-pin single-ended mode, the DAC goes to the maximum
negative value. This fact must be taken into account to minimize clicks during speech.
2.21
Interrupts
The TSP50C1x has two interrupts: interrupt-1 and interrupt-2. Both are enabled and disabled by bits in the
mode register. Interrupt-1 is a synthesis interrupt and has a higher priority. It also has more hardware
support. When an interrupt-1 occurs, the program counter is placed on the program counter stack, and the
status flag, integer mode flag, A register, B register, and X register are all saved in dedicated storage
registers. The mode register is not saved and restored during interrupts. Then the program counter is loaded
with the interrupt start location and execution of the interrupt routine begins. When the interrupt routine
returns, all these registers are restored, and the program counter is popped from the stack.
Interrupt-1 is caused by 1 of 4 conditions depending on the state ofthe two mode-register bits PCM and LPC.
These conditions, as well as the interrupt routine start address for each case, are shown in Table 2-4.
Table 2-4. Interrupt-1 Vectors
ADDRESS
PCM
LPC
INTERRUPT TRIGGER
0018 16
001A16
0
1
0
0
Pin 81 goes from high to low (see Section 2.18)
001C16
1
1
fosc/960 clock (see Section 2.20.4)
001E16
1
0
fosc/480 clock (see Section 2.20.3)
Pitch counter less than 20016 (see Section 2.15)
Interrupt-2 has a lower priority and cannot interrupt the interrupt-1 routine. It can be interrupted by
interrupt-1. During a level-2 interrupt, the program counter, status bit, and integer mode flag are the only
registers saved. The A register, X register, and B register must be saved by the program if they are used
by both it and the routine being interrupted. The mode register is not saved. Interrupt-2 is always caused
by a timer underflow - the timer going from 0 to FF - but it starts at different addresses depending on the
state of two mode-register bits. Table 2-5 shows the interrupt-2 vectors.
2-13
Table 2-5. Interrupt-2 Vectors
ADDRESS
PCM
LPC
0010 16
0012 16
0
0
1
0
001416
1
1
0016 16
1
0
INTERRUPT TRIGGER
Alilevel-2 interrupts caused by timer underflow
NOTE: All addresses in this manual are in hexadecimal format unless otherwise noted. All
other numbers are in decimal format unless otherwise noted.
The interrupting conditions for interrupt-1 and interrupt-2 set interrupt-pending latches. If an interrupt is
enabled (and in the interrupt-2 case, not overridden by an interrupt-1-pending condition), the interrupt is
taken immediately. If, however, the interrupt is not enabled, the pending-interrupt latch causes an interrupt
to occur as soon as the respective interrupt is enabled in the mode register.
Interrupts will not be taken in the middle of double-byte instructions, during branch or call instructions, or
during the subroutine or interrupt returns (RETN or RETI). A single instruction software loop (instruction of
BRANCH, BRA, CALL, or SBR to itself) should be avoided since an interrupt will never be taken.
Consecutively executed branches or calls delay interrupts until after the execution of the instruction at the
eventual destination of the string of branches (or calls).
If consecutive branches (or calls) are avoided, the worst-case interrupt delay in the main level will be four
instruction cycles. The worst-case delay occurs when the interrupt occurs during the first execution cycle
of a branch and the first instruction at the branch destination address is a double-cycle instruction.
When the interrupt occurs, execution begins at the interrupt address. The state ofthe status bit is not known
when the interrupt occurs, so a BR or CALL instruction should not be used for the first instruction. Two SBRs
may be used, since one of them is always taken, or it may be possible to use some other instruction that
sets the status bit, followed by an SBR.
The mode register is not saved and restored during interrupts. Any changes made to the mode register
during interrupts will remain in effect after the return, including the enabling and disabling of interrupts.
2.22
TSP50C12 LCD Functional Description
The LCD functionality of the TSP50C12 was included without adding instructions to the instruction set. An
additional 192 bits of RAM were added to serve as the display RAM. The display RAM is physically placed
at RAM addresses 80 - 97. As a result, Port A's registers are mapped from FO to F3 and Port B's registers
are mapped from F4 to F7. This RAM mapping is consistent with the SE50C1 0 emulator device used in the
extended RAM mode (pin controllable).
When data is stored into the display RAM locations, it may immediately affect the voltage levels on the LCD
segment outputs. Because the microprocessor access of RAM is time multiplexed with LCD access, there
will be no asynchronous ambiguities on segment outputs. If the display RAM update routines are slow, it
may be necessary to buffer the display data in another area of RAM and then transfer it to the display RAM
in a more time efficient block move.
An LCD voltage reference generator is also included on the TSP50C12. This circuit eliminates the need for
an external voltage reference generator.
2.22.1
TSP50C12 LCD Driver
The TSP50C12 can drive an 8 x 24 (192-segment) LCD display with 1/8 duty cycle. The driver function for
the LCD is controlled by internal timing hardware. Display data for the LCD is stored in a dedicated section
of RAM. This data is stored in pixel form with 24 consecutive 8-bit words. Table 2-6 shows the memory
locations for each pixel.
2-14
Table 2-6. TSP50C12 Display RAM Map
ADDRESS
Isb
S23c1
S22c1
S21c1
S20c1
S19c1
S18c1
s17c1
S16c1
81
S15c1
S14c1
S13c1
S12c1
S11c1
S10c1
S9c1
S8c1
82
S7c1
S6c1
S5c1
S4c1
S3c1
S2c1
S1c1
SOc1
83
S23c2
S22c2
S21c2
S20c2
S19c2
S18c2
s17c2
S16c2
84
S15c2
S14c2
S13c2
S12c2
S11c2
S10c2
S9c2
S8c2
85
S7c2
S6c2
S5c2
S4c2
S3c2
S2c2
S1c2
SOc2
86
S23c3
S22c3
S21c3
S20c3
S19c3
S18c3
s17c3
S16c3
87
S15c3
S14c3
S13c3
S12c3
S11c3
S10c3
S9c3
S8c3
88
S7c3
S6c3
S5c3
S4c3
S3c3
S2c3
S1c3
SOc3
89
S23c4
S22c4
S21c4
S20c4
S19c4
S18c4
s17c4
S16c4
8A
S15c4
S14c4
S13c4
S12c4
S11c4
S10c4
S9c4
S8c4
88
S7c4
S6c4
S5c4
S4c4
S3c4
S2c4
S1c4
SOc4
8e
S23c5
S22c5
S21c5
S20c5
S19c5
S18c5
s17c5
S16c5
S15c5
S14c5
S12c5
S11c5
S10c5
S9c5
S8c5
80
S13c5
8E
S7c5
S6c5
S5c5
S4c5
S3c5
S2c5
S1c5
SOc5
8F
S23c6
S22c6
S21c6
S20c6
S19c6
S18c6
s17c6
S16c6
90
S15c6
S14c6
S13c6
S12c6
S11c6
S10c6
S9c6
S8c6
91
S7c6
S6c6
S5c6
S4c6
S3c6
S2c6
S1c6
SOc6
92
S23c7
S22c7
S21c7
S20c7
S19c7
S18c7
s17c7
S16c7
93
S15c7
S14c7
S13c7
S12c7
S11c7
S10c7
S9c7
S8c7
94
S7c7
S6c7
S5c7
S4c7
S3c7
S2c7
S1c7
SOc7
95
S23c8
S22c8
S21c8
S20c8
S19c8
S18c8
s17c8
S16c8
96
S15c8
S14c8
S13c8
S12c8
S11c8
S10c8
S9c8
S8c8
97
S7c8
S6c8
S5c8
S4c8
S3c8
S2c8
S1c8
SOc8
NOTES:
2.22.2
msb
80
S-Segment or pixel on a given row (common time)
c:-Row (common time)
All addresses in this manual are in hexadecimal format unless otherwise noted. All other
numbers are in decimal format unless otherwise noted.
TSP50C12 LCD Drive Type A
The Type A drive method places limitations on the series resistance and pixel capacitance of the display.
This drive type requires a more complex LCD display. The Type A option must be selected by the customer
and given to TI before releasing the device for mask tooling.
2-15
c1
140--------- 1 Frame Period ----------+1
Vr
-Vr'
Vc'
Vr'
- -Vr
c2
Vr
-Vr'
Vc'
Vr'
-Vr
C8
Vr
-Vr'
Vc'
Vr'
-Vr
51
(C1/c3/C8 on)
Vr
-Vr'
Vc'
Vr'
-Vr
52
(c1/c2/c6 on)
Vr
-Vr'
Vc'
Vr'
-Vr
Vr
-Vr'
Vc'
Vr'
-Vr
53
(c1 -c8 on)
Differential Voltage Across Pixel 51c1 (Vcommon - Vsegment>
4tN
/',.v
O/',.V
51c1 "on"
-/',.V
- -4/',.V
2/',.V
/',.v
51c2 "off"
O/',.V
-/',.V
-UV
Figure 2-S. TSPSOC12 LCD Driver Type A Timing Diagram
2-16
2.22.3
TSP50C12 LCD Drive Type 8
The Type B drive method operates at a lower frequency, allowing the common signal to go high on the first
frame and to go low on the next frame. This option is preferred for applications that have large capacitance
pixel loads and high series trace resistances. This method also might be used if the microprocessor is
operated at higher frequencies. The Type B option must be selected by the customer and given to TI before
releasing the device for mask tooling.
c1
. Vr
-Vr'
- - - - - - - - - - - - - - - - - - -. Vc'
- - - - - - - - - - - - - - - - - - -. Vr'
- - - - - - - - - - - - - - - - - - - . -Vr
---------------------..,....----------1- -.
1 + - - - 1 Frame Period - - - + I
- - - - - - - - - - - - - - - - - - - - - . Vr
, . - - - - - - - - - \ - - . -Vr'
- - - - - - - - - - - - - - - -. Vc'
- - - - - - - - - - - - - . Vr'
- - - - - - - - - - - - - - - - . -Vr
c2
---------------------.
c8
~---------~-------------------
"'--------' - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
S1
(c1/c3/c8 on)
S2
(c1/c2/c6 on)
S3
(c1 -c8 on)
Vr
1----------...,
----. -Vr'
- - - - - - - - - - - - - - - - - - - -. Vc'
. Vr'
- - . -Vr
- -. Vr
- - - . -Vr'
- - -. Vc'
- - -. Vr'
. -Vr
- - - - - - . Vr
- - - - - - . -Vr'
L..._-j_ -. Vc'
- - - - - - - - - - - - - - - - - - - - -. Vr'
- - - - - - - - - - - - - - - - - - - - - - - . -Vr
~----------~--.
W
- - - - - - - - - - - - - - - - - - - - - . -Vr'
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - -.
- - - - - - - - - - - - - - - - - - - - -.
1------------+ ------------------- .
Vc'
Vr'
-Vr
Differential Voltage Across Pixel S1 c1 (Vcommon - V segment>
S1c1 "on"
---------
4tN
tN
OtN
---------I!.V
- - - - - - - - - - - - - - - - - - - . -41!.V
UV
6.V
S1c2 "off"
-----------------
OI!.V
-I!.V
- - - - - - - - - - - - - - - - . -UV
Figure 2-6. TSPSOC12 LCD Driver Type B Timing Diagram
2-17
2.23
TSP50C12 LCD Reference Voltage and Contrast Adjustment
The TSP50C12 contains an internal voltage reference generator to regulate and adjust the LCD reference
voltages. The voltage generator is comprised of a voltage doubler, a bandgap reference, a voltage regulator,
and a final trim DAC. VLCO provides an isolated voltage supply for the voltage doubler. VLCO can be
connected to VOO or, for example, can be connected to a 4.5-V tap of a 4-cell battery supply to improve the
power efficiency ofthe circuit. An external capacitor should be connected between V C1 and V C2. An external
capacitor should be connected between VX2 and VLCO. The bandgap provides a reference voltage for the
voltage regulator. The voltage regulator has a nominal output of 4.9 V (±200 mY). The reference voltage
can be trimmed by writing to the DAC (memory-mapped to the lower four bits at RAM location 98). The trim
control will range from -8 steps (0000) to +7 steps (1111) from nominal with each step being approximately
100 mY. The value of this RAM location will not be initialized and must be set by the initialization software
routine.
TSP5OC12
,..---- VC1
Cpump
0.01 llF
Cstore
0.047 llF
1
T. . .___ VC2
1'---
VX2
T
Figure 2-7. TSP50C12 Voltage Doubler
2.24
TSP50C12 Clock Options
The RC oscillator requires a single external resistor between VOO and OSC1 with OSC21eft unconnected
to set the operating frequency. The frequency shift, as VOO changes, is limited to 10% over the operating
range of 4 V to 6.5 V. The center frequency as a function of resistance will require trimming. For applications
requiring greater clock preCision, a ceramic resonator option is also available. The RC oscillator/ceramic
resonator selection must be made by the customer and given to TI before releasing the device for mask
tooling.
2-18
3
3.1
TSP50C1 x Electrical Specifications
Absolute Maximum Ratings Over Operating Free-Air Temperature Range
Supply voltage range, VDD (see Note 1) ........................... -0.3 V to 8 V
Input voltage range, VI (see Note 1) ....................... -0.3 V to VDD + 0.3 V
Output voltage range, Vo (see Note 1) ..................... -0.3 V to VDD + 0.3 V
Operating free-air temperature range, TA ............................ ooe to 70°C
Storage temperature range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -30°C to 125°C
NOTE 1: All voltages are with respect to ground.
3.2
TSP50C1x Recommended Operating Conditions
MIN
Voo
VIH
Vil
Supply voltage t
High-level input voltage
low-level input voltage
TA
Operating free-air
temperature
fosc
Clock frequency
fclock
ROM clock frequency
NOM
MAX
4
6.5
VOO =4 V
3
4
VOO = 5 V
3.8
5
VOO =6V
4.5
6
VOO =4 V
0
0.8
VOO=5V
0
1
VOO =6V
Device functionality
0
1.3
0
70
10
40
lCO reference spec (TSP50C12 only)
1O-kHz speech sample ratel
9.6
8-kHz speech sample ratel
7.68
External ROM mode interface to
TSP60C18 speech ROMs
UNIT
V
V
V
DC
MHz
MHz
fosc/ 4
t Unless otherwise noted, all voltages are with respect to VSS.
l Speech sample rate = fosc/960.
3.3
TSP50C1x CIA Options Timing Requirements
MIN
tr
tf
Rise time, PA, PS,
O/A options 1, 2
Fall time, PA, PS,
O/A options 1, 2
VOO = 4 V,
NOM
MAX
UNIT
22
ns
10
ns
Cl = 100 pF
3-1
3.4
TSPSOC1x Initialization Timing Requirement
MIN
MAX
INIT pulsed low while the TSP50C1x has power applied
Figure 3-1. Initialization Timing Diagram
3.S
TSPSOC1x Write Timing Requirements (Slave Mode)
MIN
tsu(81)
Setup time, 81 low before 80 goes low
tsu(d)
Setup time, data valid before 80 goes high
th(81)
MAX
UNIT
20
ns
100
ns
Hold time, 81 low after 80 goes high
20
ns
th(d)
Hold time, data valid after 80 goes high
30
ns
tw
Pulse duration, 80 low
tr
Rise time, 80
50
ns
tf
Fall time, 80
50
ns
ns
100
B1
tsu(B1)~
i~ th(B1)
--+I
14
BO
tw
~
t,-.I
~
.1 1
11~---------~
~tSU(d)~
---------~<
tr
1
--t>I 5 ' th(d)
1
PA
14-
D."V.II.
~-----
Figure 3-2. Write Timing Diagram (Slave Mode)
3-2
3.6
TSP50C1x Read Timing Requirements (Slave Mode)
MIN
MAX
UNIT
tsu(81)
Setup time, 81 before 80 goes low
20
th(81)
Hold time, 81 after 80 goes high
20
tdis
Output disable time, data valid after 80 goes high
tw
Pulse duration, 80 low
tr
Rise time, 80
50
ns
tf
Fall time, 80
50
ns
td
Delay time for 80 low to data valid
50
ns
B1
0
ns
30
100
//flT
'..
_ _- - ...;1
I'"
BO
tw
N1I;",.:_ _ _ _
tf
---.I j+td -J j.-
-~Y
\
"I
ns
ns
~\\
I
-+I
tsu(B1) j+- -+I
PA
ns
!+- th(B1)
,
ie--------
~Y!
~
:.-
tr
-+I lOIII- tdis
Data Valid
',---.r--
Figure 3-3. Read Timing Diagram (Slave Mode)
3-3
3.7
TSP50C10{11 Electrical Characteristics Over Recommended Ranges of
Supply Voltage and Operating Free-Air Temperature (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
VT+
VT-
Negative-going
threshold voltage
VOO = 4.5 V
Hysteresis
(VT+-VT-)
VOO = 4.5 V
0.4
Vhys
VOO = 6V
0.5
Ilkg
Input leakage current
Istandby
Standby current (INIT low)
loot
Supply current
IOH
High-level output
current (PA, PB,
O/A options 1,2)
IOL
2.3
V
1
10
O/A option 1, 2, or 3
5
VOH=3.5V
-4
VOO = 5V,
VOH =4.5V
-5
-7.5
VOO =6V,
VOH = 5.5V
-6
-9.2
VOO =4 V,
VOH =2.67V
-8
-13
VOO = 5V,
VOH = 3.33 V
-14
-20
VOO =6V,
VOH =4 V
-20
-29
VOO = 4V,
VOL= 0.5 V
10
17
VOL = 0.5 V
13
20
VOO =6V,
VOL= 0.5 V
15
25
VOO = 4V,
VOL= 1.33V
20
32
VOO = 5 V,
VOL= 1.67V
30
52
41
71
15
30
VOL=2V
Resistors selected with software
connected between pin and VOO
and
fAA
fAA
mA
-6
VOO = 4 V,
VOO =6V,
Pull-up resistance
V
3.15
VOO = 6V
UNIT
V
3.65
VOO = 6V
VOO = 5V,
Low-level output
current (PA, PB,
O/A options 1,2)
MAX
2.7
VOO = 4.5V
Positive-going
threshold voltage
mA
mA
mA
mA
60
kQ
t Operating current assumes all inputs are tied to either VSS or VOO with no input currents due to programmed pullup
resistors. The OAC output and other outputs are open circuited.
3-4
3.8
TSP50C12 Electrical Characteristics Over Recommended Ranges of
Supply Voltage and Operating Free-Air Temperature (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
2.7
VOO =4.5V
VT+
Positive-going threshold
voltage
VT-
Negative-going threshold
voltage
VOO=4.5V
Hysteresis
(VT+-VT-)
VOO=4.5V
0.4
Vhys
VOO = 6V
0.5
LCO reference
voltages
2.3
OAC register = 1000, TA = 25°C,
See Figures 2-5 and 2-6
Vr '
Vr
-Vr
LCO temperature coefficient
OAC step
Ilkg
Input leakage current
Istandby
Standby current (INIT low)
100+
Supply current
IOL
High-level output current (PA,
PB, O/A options 1, 2)
Low-level output current (PA,
PB, 0/A options 1, 2)
5.1
4.033
2.734
2.85
2.966
1.751
1.825
1.899
0.8
0.833
-2.5
74
O/A option 1 or 3
100
-4
124
mV
1
fAA
fAA
VOH=4.5V
-5
-7.5
VOO = 6V,
VOH=5.5V
-6
-9.2
VOO = 4 V,
VOH =2.67V
-8
-13
VOO = 5V,
VOH = 3.33 V
-14
-20
VOO = 6V,
VOH = 4V
-20
-29
VOO = 4V,
VOL=0.5V
10
17
VOO = 5V,
VOL= 0.5 V
13
20
VOO = 6V,
VOL=0.5V
15
25
VOO = 4V,
VOL=1.33V
20
32
VOO = 5V,
VOL= 1.67V
30
52
VOO = 6V,
VOL=2V
41
71
15
30
LCO frame rate
fOSC = 9.6 MHz
mA
-6
VOO = 5V,
OAC buffer drive
(O/A option 1)
V
mV/oC
5
VOH=3.5V
Resistors selected with software
and connected between pin and
VOO
32-Q load connected across DA1
and OA2, VOO = 4.5 V
Pull up resistance
4.9
3.875
10
VOO = 4V,
IOH
4.7
TA = O°C to 40°C
OAC step control ofVr with respect
to -Vr, VOO = 5 V, TA = 25°C
V
3.717
0.767
t
V
3.15
VOO = 6V
Vr
-Vr '
Vc '
V
3.65
VOO =6V
UNIT
mA
mA
mA
mA
60
kQ
60
mA
96
Hz
t This negative temperature coefficient is normally advantageous because it tracks the tem perature variation of most LCO
materials.
:I: Operating current assumes all inputs are tied to either VSS or VOO with no input currents due to programmed pullup
resistors. The OAC output and other outputs are open circuited.
3-5
3.9
TSP50C14 Electrical Characteristics Over Recommended Ranges of
Supply Voltage and Operating Free-Air Temperature (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
VT+
Positive-going
threshold voltage
VT-
Negative-going
threshold voltage
VDD = 6V
Hysteresis
(VT+ -VT-)
VDD= 4.5V
0.4
Vhys
VDD =6V
0.5
Input leakage current
Istandby
Standby current (INIT low)
IDDt
Supply current
IOH
IOL
Low-level output
current (PA, PB, D I A
options 1, 2)
Pullup resistance
fosc
Oscillator frequency+
V
3.15
V
1
10
DAC option 1 or 2
VDD =4V,
High-level output
current (PA, PB, D/A
options 1, 2)
2.3
VDD= 4.5V
5
VOH =3.5V
-27
flA
flA
mA
-41
VDD = 5V,
VOH =4.5V
-34
-51
VDD = 6 V,
VOH =5.5V
-41
-63
VDD = 4 V,
VOH =2.67V
-54
-68
VDD = 5 V,
VOH =3.33V
-95
-136
mA
mA
VDD = 6 V,
VOH =4V
-136
-197
VDD = 4V,
VOL = 0.5 V
27
41
VDD = 5V,
VOL = 0.5 V
34
51
VDD = 6V,
VOL=0.5 V
41
63
VDD = 4V,
VOL = 1.33 V
54
88
VDD = 5V,
VOL=1.67V
95
136
136
197
15
30
60
7.68-MHz target frequency, VDD = 4 V,
TA = 25°C
7.21
7.68
8.15
9.6-MHz target frequency, VDD = 4 V,
TA = 25°C
9.02
9.6
10.2
VDD = 6V,
VOL=2V
Resistors selected with software and
connected between pin and VDD
UNIT
V
3.65
VDD =6V
Ilkg
MAX
2.7
VDD = 4.5V
mA
mA
kQ
MHz
t Operating current assumes all inputs are tied to either VSS or VDD with no input currents due to programmed pullup
resistors. The DAC output and other outputs are open circuited.
:j: The frequency ofthe internal clock has a temperature coefficient of approximately -0.2 %/oC and a VDD coefficient of
approximately + 1.4% IV.
3-6
TSP50C1 x Assembler
4
4.1
Description of Notation Used
The notation used in this document is as follows:
An optional field is indicated by brackets; for example, [LABEL].
User-supplied contents are indicated by braces; for example,
A reseNed keyword is given in capital letters.
A required blank is indicated by a caret (").
EXAMPLE
[]
4.2
A
SBR
A
A
[]
Invoking the Assembler
The assembler is invoked by typing:
ASM10" []
A
where:
Options represents a list of assembler options (see Section 4.2.1).
Source is the name of the source file with the extension optional.
If the extension is not given, then the default extension of" .ASM" is
assumed.
For example:
ASMIO -1 PROGRAM
would run the assembler using the source file "PROGRAM.ASM" and would generate the output object file
"PROGRAM.BIN". No list file would be generated.
4.2.1
Command-Line Options
Several options can be invoked from the command line (Table 4-1). They are invoked by listing their
abbreviation prefixed by a minus sign. For example:
ASMIO -10 PROGRAM.ASM
would assemble the program in file "PROGRAM.ASM" but would not generate either a listing file or an Object
file; however, any errors would be written to the console. The available options are detailed below. See
Section 4.4.10 for information on invoking options from within the source code.
4-1
Table 4-1. Switches and Options
CHARACTER
OR
NUMBER
B or b
D ord
Lists only the first data byte in BYTE or RBYTE
Lists only the first data byte in DATA or RDATA
lor i
Counts the number of times a valid instruction has been used
L or I
Displays error messages without generating a list
o oro
Disables object file output
P or p
Prints listing without page breaks
R or r
Produces a reduced cross-reference list
S or s
Writes no errors on screen unless listing file is generated
Tor t
Lists only the first data byte in TEXT or RTEXT
Worw
Suppresses the warning message
Xorx
Adds a cross-reference list at the end
9
4.2.1.1
ACTION
Generates object file in TI-990 tagged object format
BYTE Unlist Option
Placing a b or B in the command-line option field causes the assembler to list only the first opcode in a BYTE
or RBYTE statement. Normally, if a BYTE or RBYTE statement has n arguments, they are listed in a column
running down the page in the opcode column of the listing, taking n lines to completely list the resulting
opcodes. If the BYTE unlist switch is set, then only the first line (which also contains the source line listing)
is written to the listing file.
4.2.1.2
DATA Unlist Option
Placing a d or D inthe command-line option field causes the assembler to list only the first opcode in a DATA
or RDATA statement. Normally, if a DATA or RDATA statement has n arguments, they are listed in a column
running down the page in the opcode column of the listing, taking n lines to completely list the resulting
opcodes. If the DATA unlist switch is set, then only the first line (which also contains the source line listing)
is written to the listing file.
4.2.1.3
XREF Unlist Option
Placing an x or X in the command-line option field causes the assembler to add a cross-reference listing
at the end of the listing file.
4.2.1.4
TEXT Unlist Option
Placing a tor T in the command-line option field causes the assemblerto list only the first opcode in a TEXT
or RTEXT statement in the listing file. Normally, if a TEXT or RTEXT statement has as an argument a string
containing n characters, the ASCII representation of these n characters is written in a column in the opcode
column ofthe listing. If the TEXT unlist switch is set, only the first line (also containing the source line listing)
is written to the list file.
4.2.1.5
WARNING Unlist Option
Placing a w or W in the command-line option field causes the assembler to suppress WARNING messages.
Warnings are still counted and error messages are still generated.
4.2.1.6
Complete XREF Switch
Placing an r or R in the command-line option field causes the assembler to produce a reduced XREF listing
if one is produced. Normally, all symbols (whether used or not) are listed in the XREF listing. The r option
causes the assembler to omit from the XREF listing all symbols from the copy files that were never used.
4-2
4.2.1.7
Object Module Switch
Placing an
modules.
0
or 0 in the command-line option field causes the assembler to not generate any object output
4.2.1.8
Listing File Switch
Placing an I or L in the command-line option field causes the assembler to not generate the listing file but
to display any error messages to the screen.
4.2.1.9
Page Eject Disable Switch
Placing a p or P in the command-line option field causes the assembler to print the listing in a continual
manner without division into separate pages. When desired, aform feed may still be forced using the PAGE
command.
4.2.1.10
Error to Screen Switch
Placing an s or S in the command-line option field causes the assembler to not write errors to the screen
unless no listing file is being generated.
4.2.1.11
Instruction Count Switch
Placing an i or I in the command-line option field causes the assembler to generate a table containing the
number oftimes each valid instruction was used in the program.
4.2.1.12
Binary Code File Disable Switch
Placing a 9 in the command-line option field causes the assembler to generate the object module in tagged
object format in a file with a ".MPO" extension instead of the normal binary formatted object module in a file
with a ".BIN" extension.
4.2.2
Assembler Input and Output Files
The assembler takes as input a file containing the assembly source and produces as output a listing file and
an object file in either binary format or tagged object format.
4.2.2.1
Assembly Source File
The assembly source file is specified in the command line. If the file name given in the command line has
an extenSion, then the file name is used as given. If no extension is specified, then the extension ".asm" is
assumed.
For example:
ASMIO PROGRAM.SRC
uses the file PROGRAM.SRC as the assembly source file.
ASMIO PROGRAM
uses the file PROGRAM.ASM as the assembly source file.
4.2.2.2
Assembly Binary Object File
The assembly process produces an Object file in binary format by default. The object output is placed in a
file with the same file name as the assembly source except that the extension is ".bin". If the binary file is
not desired, it can be disabled either as a command-line option or with an OPTION statement.
4-3
For example:
ASMIO PROGRAM.SRC
uses the file "PROGRAM.SRC" as the assembly source file and the file "PROGRAM.BIN" as the binary
object output file.
ASMIO -0 PROGRAM.SRC
uses the file PROGRAM.SRC as the assembly source file and produces no object output.
4.2.2.3
Assembly Tagged Object File
If desired, the assembler can substitute an Object file in tagged Object format instead of the Object file in
binary format. If produced, the object output is placed in a file with the samefile name as the assembly source
except that the extension is ".mpo".
For example:
ASMIO -9 PROGRAM.SRC
uses the file "PROGRAM.SRC" as the assembly source file and the file "PROGRAM.MPO" as the tagged
object output file. No binary-formatted object file is produced.
4.2.2.4
Assembly Listing File
The assembly process produces a listing file that contains the source instructions, the assembled code, and
(optionally) a cross-reference table. The listing file is placed in a file with the same file name as the assembly
source except that the extension is ".Ist".
For example:
ASMIO PROGRAM.SRC
uses the file "PROGRAM.SRC" as the assembly source file and the file "PROGRAM.LST" as the assembly
listing file.
4.3
Source-Statement Format
An assembly-language source program consists of source statements contained in the assembly source
file(s) that may contain assembler directives, machine instructions, or comments. Source statements may
contain four ordered fields separated by one or more blanks. These fields (label, command, operand, and
comment) are discussed in the following paragraphs.
The source statement may be as long as 80 characters. If the form width is set to 80 characters (the default),
the assembler will truncate the source line at 60 characters. The user should ensure that nothing other than
comments extend past column 60.
Any source line starting with an asterisk (*) inthefirst character position is treated as a comment in its entirety
and as such is ignored by the assembler and has no effect on the assembly process.
The syntax of the source statements is:
[