1993_Xilinx_Programmable_Logic_Data_Book 1993 Xilinx Programmable Logic Data Book
User Manual: 1993_Xilinx_Programmable_Logic_Data_Book
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~ XILINX'
,
-'
The Programmable Logic
, ' Data Book
1993
The Programmable Logic
Data Book
2100 Logic Drive
San Jose, California 95124
Telephone: (408) 559-7778
© Copyright 1993 by Xilinx, Inc. All Rights Reserved
Patents Pending
£
XlllNX~XACT,
XC2064, XC3090, XC4005, and XC-DS501 are
registered trademarks of Xilinx. All XC-prefix product designations,
XACT-performance, XAPP, X-BLOX, XSI, XChecker, XDM, XEPLD,
XFT, XAPP, XSI, BITA, Dual Block, FastCLK, HardWire, LCA, Logic Cell,
PLUSASM, and UIM are trademarks of Xilinx. The Programmable Logic
Company is a service mark of Xilinx.
IBM is a registered trademark and PC/AT, PCIXT, P5/2 and Micro
Channel are trademarks of International Business Machines Corporation. DASH, Data VO and FutureNet are registered trademarks and
ABEL, ABEl-HDl and ABEl-PLA are trademarks of Data VO Corporation. SimuCad and Silos are registered trademarks and P-Silos and
PIC-Silos are trademarks of SimuCad Corporation. Microsoft is a registered trademark and MS-DOS is a trademark of Microsoft Corporation.
Centronics is a registered trademark of Centronics. Data Computer
Corporation. PAL and PALASM are registered trademarks of Advanced
Micro Devices, Inc. UNIX is a trademark of AT&T Technologies, Inc.
CUPl is a trademark of logical Devices, Inc. Apollo and AEGIS are
registered trademarks of Hewlett-Packard Corporation. Mentor and IDEA
are registered trademarks and NETED, Design Architect, QuickSim,
QuickSim 11 and EXPAND are trademarks of Mentor Graphics. Inc. Sun
is a registered trademark of Sun Microsystems, Inc.
SCHEMAII+ andSCHEMAIil are trademarks of Omation Corporation.
OrCAD is a registered trademark of OrCAD Systems Corporation.
Viewlogic, Viewsim, Viewdraw and ViewSynthesis are registered trademarks of Viewlogic Systems, Inc. CASE Technology is a trademark of
CASE Technology, a division olthe Teradyne Electronic Design Automa-
tion Group. DECstation is a trademark of Digital Equipment Corporation.
Synopsys is a registered trademark of Synopsys, Inc. Verilog is a
registered trademark of Cadence Design Systems, Inc.
Xilinx does not assume any liability arising out of the application or use
of any product described herein; nor does it convey any license under its
patents, copyrights, or maskwork rights or any rights of others. Xilinx
reserves the right to make changes, at any time, in order to improve
reliability, function or design and to supply the best product possible.
Xilinx will not assume responsibility for the use of any circuitry described
other than circuitry entirely embodied in its products. Manufactured
under one or more of the following U.S. Patents: 4,642,487; 4,695,740;
4,706,216; 4,713,557; 4,746,822; 4,750,155; 4,758,985; 4,783,607;
4,820,937; 4,621,233; 4,835,416; 4,647,612; 4,653,626; 4,855,619;
4,855,669; 4,670,302; 4,902,910; 4,940,909; 4,967,107; 5,012,135;
5,023,606; 5,028,821; 5,047,710; 5,068,603; 5,140,193; 5,148,390;
5,155,432; 5,166,856. Xilinx, Inc. cannot assume responsibility for any
circuits shown nor represent that th",y are free from patent infringement
or of any other third party right. Xilinx assumes no obligation to correct
any errors contained herein or to advise any user of this text of any
correction if such be made. Xilinx will not assume any liability for the
accuracy or correctness of any engineering or software support or
assistance provided to a user.
Xilinx products are not intended for use in life support appliances,
devices, or systems. Use of a Xilinx product in such applications without
the written consent of the appropriate Xilinx offirer is prohibited.
SECTION TITLES
1
Programmable Logic Devices
2
FPGA Product Descriptions and Specifications
3
EPLD Product Descriptions and Specifications
4
Packages and Thermal Characteristics
5
Quality, Testing and Reliability
6
Technical Support
7
Development Systems
8
Applications
9
The Best of XCELL
10 Index, Sales Offices
TABI.E OF CONTENTS
1 Programmable Logic Devices
About the Company
Selecting the Right Device
Comparisons
1-1
1-2
1-3
2 FPGA Product Descriptions and Specifications
A Technical Overview For the First-Time User
XC4000 Logic Cell Array Families
XC4000, XC4000A, XC4000H Logic Cell Array Families
XC4000 Logic Cell Array Family
XC4000A Logic Cell Array Family
XC4000H High I/O Count Logic Cell Array Family
XC3000 Logic Cell Array Families
XC3000, XC3000A, XC3000L, XC31 00 Logic Cell Array Families
XC3000 Logic Cell Array Family
XC3000A Logic Cell Array Family
XC3000L Low-Voltage Logic Cell Array Family
XC3100 Logic Cell Array Family
XC2000 Logic Cell Array Families
XC2000 Logic Cell Array Family
XC2000L Low-Voltage Logic Cell Array Family
XC17000 Family of Serial PROMs
2-1
2-5
2-7
2-47
2-65
2-81
2-97
2-99
2-145
2-153
2-161
2-169
2-177
2-209
2-215
2-225
3 EPLD Product Descriptions and Specifications
XC7200 EPLD Family
XC7236/XC7236A Programmable Logic Device
XC7272A Programmable Logic Device
XC7300 EPLD Family
XC73108 Programmable Logic Device
3-3
3-5
3-21
3-41
3-49
4 Packages and Thermal Characteristics
Packages
Thermal Characteristics
Average Mass
Plastic Surface Mount
Sockets
4-1
4-18
4-22
4-23
4-25
5 Quality, Testing and Reliability
Quality Assurance Program
Device Reliability
Outline of Testing
Description of Tests
Package Integrity and Assembly
Data Integrity
Electrostatic Discharge
Latchup
5-1
5-2
5-2
5-5
5-5
5-7
5-8
5-8
TABLE OF CONTENTS
6 Technical Support
Technical Seminars and Users' Group Meetings
Newsletter
Xilinx Technical Bulletin Board
Field Applications Engineers
Programmable Logic Training Courses
Technical Literature
6-1
6-2
6-3
6-5
6-6
6-7
7 Development Systems
Product Packages
Automatic CAE Tools
Bundled Packages Product Descriptions
Individual Product Descriptions
7-2
7-3
7-13
7-29
8 Applications
Application Note Directory
9
8-1
The Best of XCELL
The Best of XCELL
9-1
10 Index, Sales Offices
Index
Sales Offices
10-1
10-5
SECTION 1
1
Programmable Logic Devices
2
FPGA Product Descriptions and Specifications
3
EPLD Product Descriptions and Specifications
4
Packages and Thermal Characteristics
5
Quality, Testing and Reliability
6
Technical Support
7
Development Systems
8
Applications
9
The Best of XCELL
10 Index, Sales Offices
Programmable Logic Devices
About the Company ............................................................................ 1-1
Selecting the Right Device .................................................................. 1-2
Family Architecture Comparison ......................................................... 1-3
Speed and Density .............................................................................. 1-4
Product Comparison ........................................................................... 1-5
Package Options ................................................................................. 1-6
1/0 Pins Per Packages ........................................................................ 1-6
HardWire Gate Array ........................................................................... 1-7
Military Devices ................................................................................... 1-7
About the Company ...
processes assures lowest manufacturing cost, produces
programmable logic devices with well-established
reliability, and provides for an early access to advances in
CMOS technology.
Xilinx was founded in 1984, based on the revolutionary
idea to combine the logic density and versatility of gate
arrays with the time-to-market advantages and off-theshelf availability of user-programmable standard parts.
One year later, Xilinx introduced the world's first FieldProgrammable Gate Array (FPGA). Since then, the
company has continually improved device densities and
speeds, while lowering costs. In fact, over the last six
years, Xilinx devices boasted a 40%-per-year
improvement in speed, a 52%-per-year increase in density
and a 46%-per-year decrease in silicon cost.
The company markets its products in North America
through a network of five direct-sales offices,
manufacturers' representatives in 75 locations, as well as
six distributors. Outside North America, the company sells
its products through direct-sales offices in England,
Germany, Japan, and Hong Kong, and through
representatives and distributors in 27 countries.
In early 1992, Xilinx acquired Plus Logic Inc., a supplier of
advanced EPLD (EPROM technology-based complex
Programmable Logic Devices). It is now the EPLD Division
of Xilinx. For the user, EPLDs can be an attractive
complement to FPGAs, offering simpler software and
more predictable timing.
With 1992 revenues of $163 million, Xilinx is the world's
largest supplier of CMOS programmable logic. It is the only
company that can offer both FPGA and EPLDs.
One Source for FPGAs and EPLDs
For designers most comfortable with the speed, design
simplicity, and predictability of PALs, the XC7200 and
XC7300 Families of complex EPLDs provide a higher level
of integration, with the same familiar PALASM and ABEL
design methodology.
As the market leader in the fastest-growing segment of the
semiconductor industry, Xilinx strategy is to focus its
resources on creating new ICs and development system
software, on developing markets, and on building a
diverse customer base across a broad range of
geographic and market-application segments. The
company avoids the large capital commitment and
overhead burden associated with owning a wafer
fabrication facility by establishing manufacturing alliances
with several high-volume state-of-the-art CMOS memory
manufacturers. Using standard high-volume memory
For a move up to higher density designs that combine an
abundance of gates and I/Os with fast system speed,
Xilinx offers the ideal logic device, the FPGA: Three
complete families with over 20 different devices, including
the world's largest FPGA, the 13,OOO-gate XC4013. There
are more than 300 product types, plus more than 40
1-1
I
Introducticm to Programmable Logic Devices
Selecting the Right Device
varieties of devices for military and aerospace
applications. The design software is also available that is
fully integrated, highly automated, easy to use, and works
with existing CAE tools.
Step 1 - Choos. a Family
The Family Architecture Comparison and Speed and
Densitycharts help you determine whether an XC7200 or
XC7300 series EPLD, XC20oo1XC3000IXC3100 Series
FPGA or XC4000IXC4000AIXC4000H Series FPGA is
right for your application. Comparative information is
provided on product architecture, logic capacity. design
timing, system features, etc.
Programmable Logic vs Gate Arrays
FasterDesign and VeriHcation- Xilinx FPGAs and EPLDs
can be designed and verified in a few days, while the same
process requires several weeks with gate arraYs. There
are no non-recurring engineering (NRE) costs and no
prototypes to wait for.
Step 2 - Choose a Device
Now that you've determined which Family of Xilinx
products works besHor you, use the Product Comparison
chart to select specific device(s) within the Family.
Comparisons are provided for gate-count, number of 1I0s,
flip-flops, RAM bits, CLBs and Macrocells.
Design Changes without Penalty- Because the devices
are software configured via instant prpgramming,
modifications are much less risky and can be made
anytime, in a matter of hours instead of the weeks it would
take with a gate array. This adds up to significant cost
savings in design and production.
Step 3 - Choose a Package
Finally, the charts entitled Package Options and //0 Pins
Per Packageshow the 300+ package/speedltemperature
and qualification level options Xilinx offers. Since many
products come in common packages with common
footprints, designs can often be migrated to higher or lower
density devices without any board changes.
Shortest Time to Market - Designing with Xilinx
programmable logic vs gate arrays, time-to-market is
measured in days or a few weeks, rather than the months
required when designing with gate arrays.
A study by McKinsey & Co. concludes that a six-month
delay in getting to market can cost a product one-third of
its lifetime potential proHt With a custom gate array,
design iterations can easily add that much time, and more,
to a product schedule.
Once the decision has been made to use Xilinx
programmable logic, a choice must be made from a
number of product families, device options- and product
types. The following guides simplify the selection process.
1-2
Family Architecture Comparison
FPGAs
EPLDs
XC7200 Family
XC7300 Family
XC2OOOIXC3000f
XC3100 Family
XC4000IAIH Family
Gate array-like
Many small blocks
Gate array-like
Many small blocks
Architecture
PAL-like, AND-OR plane Advanced PLD - high
speed, high density
Macrocells and product
function block (FB) in
terms
the same device
Logic
Capacity
36 - 72 Macrocells
Integrate 4 - 8 PAU
22V10s
36 - 144 Macrocells
Integrate 4-16 PAU
22V10s
800 - 8,000 gates
Integrate TTL, MSI, PLDs
2,000 - 13,000 + gates
Integrate TTL. MSI, PLDs,
RAM
Design
Timing
Fixed, PAL-like
60 MHz - predictable
for most applications
FIXed, PAL-like
66 MHz - predictable
for most applications
Gate array-like - depends on
application
Can be >100 MHz, typically
25 - 40 MHz (XC3000) or
50 - 80 MHz (XC3100)
Gate array-like - depends on
application
Can be >100 MHz,
typically 30 - 50 MHz
Number of
1I0s
Fewer -like EPLDIPAL
36-72
136-156
Many -like gate array
58-176
Many -like gate array
64-192
NumberofFF
Fewer -like EPLDs
72-144
172-234
Many -like gate array
122-1,320
Very large number- RAM on chip
256 - 1,536 plus RAM bits
Power
Consumption
0.5 - 1.25 W static
0.75 - 1.5 W typical
0.4 - 2.0 W static
0.5 - 2.25 W typical
Programmable power
management
Very low, mW static
Very low, mW static
Dynamic - depends on appIicaIion Dynamic - depends on
application
025 - 1.0 W typical
0.25 - 2.0 W typical
System
Features
Arithmetic carry logic
100% interconnect
guaranteed
ALU per Macrocell
Uke XC7200 plus:
Two global clock buffers
Programmable outpul slew rate
I.ntemal 3-state busses
Power-down mode
8 rnA ouIpuI drive for XC31 00
Eight global clock buffers
Programmable ouIpuI slew rate
Intemal3-state bUsses
RAM for FIFOs and registers
.ITAG for board test
Fast carry logic for arilhmetic
Wide decode
12 rnA ouIpuI driIIe, 24 rnA per peIh
(24 mA/48 rnA for AIH families)
Carry look ahead
High oulpul drive
High performance and
high density FBs in
same device
Process
CMOS EPROM
CMOS EPROM
CMOS static RAM
CMOS static RAM
Programming
Method
PROM programmer
OTP or UV erasable
Configuration on chip
PROM programmer
OTP or UV erasable
Configuration on chip
Programmed in circun
Four modes
Configuration stored extemally
Programmed in circun
Six modes
Configuration stored extemally
Reprogrammable
Yes - after UV erasure
Yes - after UV erasure
Yes - in milliseconds
Reprogrammable in circun
Yes - in milliseconds
Reprogrammable in circun
Factory Tested
Yes
Yes
Yes
Yes
Key
Applications
Complex state machines
Complex counters
Bus & peripheral
Interface
Memory conlrol
PAL-cruncher
Accumulators!
incrementors
Magniludelwindow
comparators
High speed graphics
Mulliport memory
controllers
High speed bus interface
5OMHz.16bn
Simple state machines
General logic replacement
Reprogrammable applications
Battery-powered logic
3Voperation
Very fast counters
Simple state machines
Complex logic replacement
Board integration
Addersfcomparators
Reprogrammable applications
RAM application: FIFOs, buffers
FasVcompact counters
Boundary-8can testability
Bus interfacing
accumulators
1-3
II
Introduction to Programmable Logic Devices
Speed and Density
EPLDs
FPGAs
XC7200 (-1S) XC7300 (-12)
XC3000 (-12S)
XC3100(-3}
XC4000(-5}
16-Bit Synchronous Binary Counter
60 MHz
60 MHz
51 MHz 24 CLBs
102 MHz24 CLBs
111 MHz17CLBs
16-Bit Unidirectional
Loadable Counter
Max Speed
Max Speed
60 MHz
60 MHz
60 MHz
60 MHz
18 MHz 16 CLBs
32 MHz 24 CLBs
31 MHz 16 CLBs
55 MHz 24 CLBs
43 MHz 9CLBs
43 MHz 9CLBs
16-Bit UfD Counter
Max Speed
Max Speed
60 MHz
60 MHz
60 MHz
60 MHz
15 MHz 16 CLBs
30 MHz 27 CLBs
28 MHz 16 CLBs
50 MHz 27 CLBs
43 MHz 9CLBs
43 MHz 9CLBs
16:1 Multiplexer
22ns
15 ns
16 ns
8CLBs
10 ns
8CLBs
16 ns
5CLBs
16-Bit Decode From Input Pad
22ns
15 ns
15 ns
4CLBs
12 ns
4CLBs
12 ns
OCLBs
16-Bit Accumulator
43 MHz
45 MHz
21 MHz 29 CLBs
36 MHz 29 CLBs
39 MHz 9CLBs
Data Path
60 MHz
60 MHz
50 MHz 16 CLBs
95 MHz 16 CLBs
85 MHz 12 CLBs
Timer Counter 2
60 MHz
60 MHz
28 MHz 23 CLBs
52 MHz 23 CLBs
40 MHz 12 CLBs
State Machine 3
60 MHz
60 MHz
18 MHz 34 CLBs
30 MHz 34 CLBs
31 MHz 25 CLBs
Arithmetic 4
12 MHz
22 MHz
17 MHz 23 CLBs
29 MHz 23 CLBs
20 MHz 16 CLBs
nla
nla
1
16 Channel, 32-Bit DMA
Notes:
1. 32 inputs, 4:1 mux, register, 8-bit shift register
2. 8-bit TIC, latch, mux, compare
3. 16 states, 40 transistions, 10 inputs, B outputs
4. 4x4 multiplier, 8-bit accumulator
nla
nla
nla
nla
20 MHz 72 CLBs
A. Benchmark data, including design files is available in Ihe XAPP Application Handbook and on the
Xilinx bulletin board as XAPP files.
B. System speeds for slower parts (e.g. -100, -70) can be approximated by derating wilh the ratio
(e.g. 0.67 for-l00, 0.47 for -70).
C. All speeds are worst-case temperature and vonage.
X3253
1-4
Product Comparison
Typical
EPlDs
Gates"
Typical
Gates
Using RAM
MaxVOs
Flip-Flops
RAM bits
Macrocells
n/a
n/a
n/a
n/a
36
72
68
120
n/a
n/a
36
72
n/a
n/a
120
198
0
108
n/a
0.8K-l.8K
1.2K-l.5K
n/a
n/a
58
74
122
174
0
0
n/a
n/a
100
1.3K-l.8K
2.0K-2.7K
2.0K-3.7K
4.0K-5.5K
5.0K-7.5K
6.5K-9.0K
n/a
n/a
n/a
n/a
n/a
n/a
64
256
360
480
688
928
1,320
0
0
0
0
0
0
n/a
n/a
n/a
n/a
n/a
n/a
100
144
224
320
484
1.6K-2.0K
2.5K-3.0K
2.SK-3.0K
3.2K-4.0K
4.0K-5.0K
4.0K-5.0K
5.0K-6.0K
6.5K-8.0K
B.OK-l0.0K
10.0K-13.0K
2.2K-2.8K
3.5K-4.2K
3.5K-4.2K
4.6K-5.6K
6.0K-7.0K
6.0K-7.0K
7.5K-8.5K
9.7K-ll.2K
12.0K-14.0K
12.0K-16.0K
256
360
200
480
616
392
768
936
1,120
1,536
2,048
3,200
3,200
4,60B
6,272
6,272
8,192
10,368
12,800
18,432
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
100
100
144
196
196
256
324
400
576
Available
CLBs
XC7200 Family
XC7236
XC7272A
n/a
n/a
I
XC7300 Family
XC731 08
FPGAs
XC2000 Family
XC2064
XC2018
64
XC3OOOIXC3100 Family
XC30201XC3120
XC303OIXC3130
XC30421XC3142
XC3064IXC3164
XC30901XC3190
XC3195
80
96
120
144
176
64
XC4000 Family
XC4002A
XC4003A
XC4003H
XC4004A
XC4005IXC4005A
XC4005H
XC4006
XC4008
XC401 0
XC4013
64
BO
160
96
112
192
128
144
160
192
• Assumes 10% of device used as RAM.
64
X3251
1-5
Introduction to Programmable Logic Devices
Package Options
Surface Mount
Standard
Lead Pitch
Body
Temp OptIons
Ordering Code
EPLDFamlly XC7236IXC7236A
XC7272A
XC731 08
FPGAFamily XC2064
XC2018
XC302OIXC3120
XC303OfXC3130
XC3042IXC3142
XC3064IXC3164
XC309OIXC3190
XC3195
Through-hole
PLCC
POFP
TQFP
CQFP
PGA
JEDEC
50 mil
Plastic
C,I
PC
44
68,84 ,
84
44,68
44,68,84
68,84
44,68,84
84
84
84
84
EIN
0.65IO.5mm
Plastic
C,I
PQ
EIN
0.5mm
Plastic
C,I
TQ
JEDEC
25 mil
Ceramic
M,B
CB
JEDEC
100 mil
Ceramic/Plastic
C,I,M,B
PG,PP
160
100
84
84
100
100
208
160
160,208
240
160,208
208
208
208,240
XC4OO2A
XC4003A
XC4003H
XC4OO4IXC4004A
XC4OOSIXC4005A
XC4005H
XC4006
XC4008
XC4010
XC4013
84
84,144
68
84
100
100
100
100
160
160,208
160,208
84
84
100
100
100
84
84
84,132
132
175
175,223
100
164
100
120
120
191
120
156
223
156
191
191
223
100
100
164
196
196
110 Pins Per Packages
Surface Mount
84
100
120 132 144 156 160 164 175 191 196 208 223 240
MaxK) pc,WC PC,PG,WC PC,PG,WC PQ,TQ,C8 PG PG PG PG PQ CB PG PG CB PO PG PO
44
68
EP.LD Family
XC7236IXC723&A
XC72:12A
XC73108
FPGAFaml1y
XC2064
XC2018
36
72
120
36
56
74
34
34
58
64
XC302OOCC312O
XC303OIXC3130
XC3042IXC3142
XC3064IXC3164
XC309OIXC3190
XC3195
64
34
58
58
XC4OO2A
XC4OO3A
XC4003H
XC4OO4A
XC4OO5IXC4005A
XC4005H
XC4006
XC4008
XC4010
XC4013
80
96
120
144
176
64
80
160
96
112
192
128
144
160
192
56
72
72
84
74
74 ('TQ1lIif)
64
74
74
70
70
70
64
80
82
61
61
64
77
120
96
110
120
120
138 142 144
144
138
144
176 176
64
80
160
61
61
95
96
112 112 112
125 128
160
112
192 192
128
144 144 144
160 160 160
160 192 192
HardWire Gate Arrays
Military Devices
The No-Risk Gate-Array Migration Path For Xilinx FPGAs
The HardWire gate array provides an easy, transparent
migration path - providing a low-cost, no-risk solution for
high-volume-production applications.
Xilinx was the first company to offer military FPGAs by
introducing 883 qualified versions of the XC2000 and
XC3000 Families in 1989. The MIL-STD-883 qualified
versions of our XC4000 Family will soon be available.
These products offer a number of key benefits to military
users.
Unlike ordinary, general-purpose gate arrays, the HardWire gate array is architecturally identical to its FPGA
counterpart. The programmable elements in the FPGA are
simply removed and replaced with fixed metal connections. The resulting HardWire gate array die is considerably smaller and lower cost.
Increased Design Aexibility. Xilinx parts are standard
production ASICs, where one spec can be used for
multiple applications. Since there is no fab turnaround
time, design changes can be made in minutes, redUCing
product development time. In addition, our Class B devices are available from distributor stock.
Convert With Confidence
The HardWire gate array offers the same proven, qualified
process technology as the FPGA it replaces. And, since
the architectures are identical, FPGAs and HardWire gate
arrays have similar timing.
Reprogrammability. Because Xilinx parts are reprogrammable, design changes can be made while in production.
And, the same logic can be used for multiple,
nonconcurrent tasks.
Low Total Cost Because there are no non-recurring
engineering (NRE) costs, Xilinx devices are very cost
effective for military volumes.
In addition, the interchangeability of the FPGA and the
HardWire gate array means that FPGAs can always be
substituted - to quickly boost production to meet demand,
or to avoid gate-array inventory worries toward the end of
the product life cycle.
Reliable. Our parts are fully compliant to MIL-STD-883
Class B, with very low FIT rates. Products built and tested
to Standard Military Drawings (SMDs) are also available.
The Fastest, Easiest Way To Save
Converting from an FPGA to a HardWire gate array
couldn't be easier. The mask and test programs are
generated by Xilinx from the user's existing FPGA file.
The time-consuming and costly re-design and resimulation usually associated with FPGA-to-gate array migration
is virtually eliminated, along with the risk.
Fully Tested. Because our parts are fully tested with
100% fault coverage, the user need not generate test
programs or vectors.
Available in die form. Xilinx is the only vendor supplying
FPGAs in die form, tested and qualified for use in
military hybrids and multi-chip modules. These are available through Chip Supply, Melbourne, Florida, at (407)
298-7100.
Xilinx built-in test logic and Automatic Test Generation
(ATG) software guarantee 100% fault coverage, while
eliminating the need for test vectors. With migration this
simple, designers spend less time on rework and more
time on new projects.
For more information on military devices, contact the
nearest Xilinx Sales Office.
In addition to engineering savings from easy conversion
and the elimination of opportunity costs, the HardWire gate
array architecture also means that NRE costs are low usually <$10K (depending on size). The HardWire gate
array offers typical device savings of 50 - 80% over the
equivalent FPGA.
For more information and to request the HardWire Data
Book, contact the nearest Xilinx Sales Office.
1-7
I
Introduction to Programmable Logic Devices
1-8
SECTION 2
1
Programmable Logic Devices
2
FPGA Product Descriptions and Specifications
3
EPLD Product Descriptions and Specifications
4
Packages and Thermal Characteristics
5
Quality, Testing and Reliability
6
Technical Support
7
Development Systems
8
Applications
9
The Best of XCELL
10 Index, Sales Offices
FPGA Product Description
and Specifications
A Technical Overview for the First-Time User .................................... 2-1
Component Availability ........................................................................ 2-3
XC4000 Logic Cell Array Families ...................................................... 2-5
XC4000 Logic Cell Array Family ...................................................... 2-47
XC4000A Logic Cell Array Family ................................................... 2-65
XC4000H High 1/0 Count Logic Cell Array Family .......................... 2-81
XC3000 Logic Cell Array Families ...................................................... 2-97
XC3000 Logic Cell Array Family ...................................................... 2-145
XC4000A Logic Cell Array Family ................................................... 2-153
XC3000L Low Voltage Logic Cell Array Family ............................... 2-161
XC3100L Logic Cell Array Family .................................................... 2-169
XC200Q Logic Cell Array Families ...................................................... 2-177
XC2000 Logic Cell Array Family ...................................................... 2-209
XC2000L Low Voltage Logic Cell Array Family ............................... 2-215
XC17000 Serial Configuration PROMs Family ................................... 2-225
~
A Technical Overview For the First-Time User
In the XC2000, XC3000, and XC4000 devices, Xilinx
offers three evolutionary and compatible generations of
Field Programmable Gate Arrays (FPGAs). Here is a short
description of their common features.
Clock lines are well-buffered and can drive all flip-flops
with < 2 ns skew from corner to corner, even throughoutthe
biggest device. The user need not worry about clock
loading or clock-delay balancing, or about hold-time issues on the chip, if the designated clock lines (eight in the
XC4000 devices, two in all other devices) are used.
Every Xilinx FPGA performs the function of a custom LSI
circuit, like a gate array, but the Xilinx device is userprogrammable and even reprogrammable in the system.
Xilinx sells standard off-the-shelf devices in three families,
and many different sizes, speeds, operating temperature
ranges, and packages. The user selects the appropriate
Xilinx device, and then converts the design idea or schematic into a configuration data file, using the Xilinx development system software running on a PC or workstation,
and loads this file into the Xilinx FPGA.
XC3000/31 00 and XC4000 devices can implement internal bidirectional busses. The XC4000 devices have dedicated fast carry circuits that improve the efficiency and
speed of adders, subtractors, comparators, accumulators
and synchronous counters. XC4000 also supports boundary scan on each pin.
Almost all device pins are available as bidirectional user
1/0, with the exception of 4 to 24 supply connections (V cc
and GND) and a few pins dedicated to the configuration
process. All inputs and outputs within each family have
identical electrical characteristics, but output current capability varies among families: The XC2000 and XC3000
outputs can sink and source 4 mA, XC31 00 can sink 8 mA,
XC4000 12 mA, XC4000H 24 mAo XC2000IXC30001
XC31 00 outputs swing rail-to-rail, while XC4000 outputs
are n-channel-only, ''totem-pole'', with lower VOH for higher
speed.
This overview describes two different aspects of the Xilinx
FPGA,
• what kind of user-defined logic it can implement, and
• how the device is programmed.
User Logic
Different in structure from traditional logic circuits, PALs,
EPLDs and even gate arrays, all Xilinx FPGAs implement
combinatorial logic in small look-up tables (16 x 1 ROMs);
each such table either feeds the D-input of a flip-flop or
drives other logic or 1/0. Each device contains a matrix of
identical logic blocks, usually square, from 8 x 8 in the
XC2064 to 24 x 24 in the XC4013. Short and long metal
lines run horizontally and vertically in-between these logic
blocks, selectively interconnecting them or connecting
them to the input/output blocks.
XC2000/XC3000/XC3100 inputs can be globally programmed for either TTL-like input thresholds or CMOS
thresholds. XC4000 has fixed TTL-like input thresholds.
All inputs have hysteresis (Schmitt-trigger action) of 100 to
200 mY.
All Xilinx FPGAs have a global asynchronous reset input
affecting all device flip-flops. In the XC4000-family devices, any pin can be configured as a reset input, in the
other families, RESET is a dedicated pin.
This modular architecture is rich in registers and powerful
function generators that can implement any function of upto-five variables, all with the same speed. Forwider inputs,
function generators are easily concatenated. Generous
on-chip buffering makes block delays insensitive to loading by the interconnect structure, but all interconnect
delays are layout-dependent and must be analyzed if the
design is performance-critical.
Since all Xilinx FPGAs use CMOS-SRAM technology,
their quiescent or stand-by power consumption is very low,
a few microwatts for XC2000IXC3000 devices and max
25 mW for XC31 00, max 50 mW for XC4000 devices. The
operational power consumption is totally dynamic, proportional to the rate of change of inputs, outputs, and internal
nodes. Typical power consumption is between 100 mW
and 2 W, depending on the device size.
2-1
I
mon, concatenated bitstream. Device utilization does not
change the number of configuration bits.
XC2000 and XC3000 devices can be powered-down and
their configuration can be maintained by a >2.3 V battery.
Current consumption is only a few microamps. The device
3-states all outputs, ignores all inputs, and resets its flipflops, but retains its configuration.
Inside the device, these configuration bits control or define
the combinatorial circuitry, flip-flops, interconnect structure, and the I/O buffers. Upon power-up, the device waits
for Vcc to reach an acceptable level, then clears the
configuration memory, holds all internal flip-flops reset,
and 3-states almost all outputs but activates their weak
pull-up resistors. The device then initiates configuration,
either as a master, clocking a serial PROM to receive the
serial bitstream, or as a slave, accepting an external clock
and serial or 8-bit parallel data from an external source.
XC2000/XC3100/XC4000 devices monitor Vcc continuously and shut down when they detect a Vcc drop to 3 V.
The device then 3-states all outputs and prepares for reconfiguration. XC2000 devices need an external monitor,
if there is any danger of Vcc dropping significantly without
going all the way to ground.
Programming or Configuring the Device
The Xilinx serial PROM is the simplest way to configure the
device, using only four device pins. Typical configuration
time is around 1 Jls per bit, but there are ways to reduce it
by a factor of up to ten. Configuration.thus takes from a few
to a few hundred milliseconds. Xilinx serial PROMs come
in sizes from 18,000 to 128K bits (256K bits in the near
future); PROMs can also be daisy-chained to store a
longer bitstream.
A design usually starts as a block diagram or schematic,
drawn with one ofthe popular CAE tools, e.g. ViewDraw.
Many of these tools have an interface to XACT, the
Xilinx development system, running on PCs or popular
workstations.
After schematic- or equation-based entry, the design is
automatically converted to a Xilinx Nellist Format (XNF).
The XACT software first partitions the design into logic
blocks, then finds a near-optimal placement for each
block, and finally selects the interconnect routing. This
process of Partitioning, Placement, and Routing (PPR)
runs automatically, but the user may also affect the outcome by imposing specific constraints, or selectively editing critical portions of the design, using the graphic Design
Editor (XDE). The user thus has a wide range of choices
between a fully automatic implementation and detailed
involvement in the layout process.
The LCA device can also be configured with byte-wide
data, either from an industry-standard PROM or from a
microprocessor. The LCA device drives the PROM addresses directly, or it handshakes with the microprocessor
like a typical peripheral. The byte-wide data is immediately
converted into an internal serial bitstream, clocked by the
internal Configuration Clock (CCLK). Parallel configuration modes are, therefore, not faster than serial modes.
The user can reconfigure the device at any time by pulling
the DONE pin Low, which instigates a new configuration
sequence. During this process, all outputs not used for
configuration are 3-stated. Partial re-configuration is not
possible.
Once the design is complete, it is documented in an LCA
file, from which a serial bitstream file can be generated.
The user then exercises one of several options to load this
file into the Xilinx FPGA device, where it is stored in
latches, arranged to resemble one long shift register. The
data content of these latches personalizes the FPGA to
perform the intended digital function. The number of configuration bits varies with device type, from 12,038 bits for
the smallest device (XC2064) to 247,960 bits for the
largest device presently available (XC4013). Multiple LCA
devices can be daisy-chained and configured with a com-
After the device has been programmed, the content of the
configuration "shift register" can be read back serially,
without interfering with device operation. XC4000 devices
include a synchronized simultaneous transfer of all userregister information into the configuration registers. This
adds in-circuit-emulation capability to the read back function.
2-2
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2-4
1:
XC4000 Logic Cell Array Families
Table of Contents
XC4000, XC4000A, XC4000H
Logic Cell Array Families .................................. 2-7
XC4000 Compared to XC3000 ............................. 2-8
Architectural Overview .......................................... 2-9
Abundant Routing Resources ............................. 2-12
Development System .......................................... 2-12
Detailed Functional Description .......................... 2-19
Configuration ...................................................... 2-25
Start-Up .............................................................. 2-28
Readback ............................................................ 2-31
Master Serial Mode ............................................. 2-32
Slave Serial Mode ............................................... 2-34
Master Parallel Mode .......................................... 2-36
Synchronous Peripheral Mode ........................... 2-38
Asynch ronous Peripheral Mode .......................... 2-40
General LCA Switching Characteristics .............. 2-42
Configuration Pin Assignments ........................... 2-43
Pin Descriptions .................................................. 2-44
Ordering Information ........................................... 2-46
Component Availability ....................................... 2-46
XC4000A Logic Cell Array Families ........................ 2-65
Absolute Maximum Ratings ................................ 2-66
Operating Conditions .......................................... 2-66
DC Characteristics .............................................. 2-66
Switching Characteristic Guidelines
Wide Decoder ................................................. 2-67
Global Buffer .................................................. 2-67
Horizontal Longline ......................................... 2-68
Pin-to-Pin Parameters .................................... 2-69
lOB ................................................................. 2-70
CLB ................................................................ 2-71
XC4002A Pinouts ............................................... 2-75
XC4003A Pinouts ............................................... 2-56
XC4004A Pinouts ............................................... 2-77
XC4005A Pinouts ............................................... 2-78
Ordering Information ........................................... 2-80
Component Availability ....................................... 2-80
XC4000H High I/O Count
Logic Cell Array Family ....................................... 2-81
XC4000H Compared to XC4000 ........................ 2-82
Architectural Overview ........................................ 2-82
Slew-Rate Control ............................................... 2-84
Absolute Maximum Ratings ................................ 2-86
Operating Conditions .......................................... 2-86
DC Characteristics .............................................. 2-86
Switching Characteristic Guidelines
Wide Decoder ................................................. 2-87
Global Buffer .................................................. 2-87
Horizontal Longline ......................................... 2-88
Pin-to-Pin Parameters .................................... 2-89
CLB ................................................................ 2-90
lOB ................................................................. 2-93
XC4003H Pinouts ............................................... 2-94
XC4005H Pinouts ............................................... 2-95
Ordering Information ........................................... 2-96
Component Availability ....................................... 2-96
XC4000 Logic Cell Array Family ............................. 2-47
Absolute Maximum Ratings ................................ 2-48
Operating Conditions .......................................... 2-48
DC Characteristics .............................................. 2-48
Switching Characteristic Guidelines
Wide Decoder ................................................. 2-49
Global Buffer .................................................. 2-50
Horizontal Longline ......................................... 2-50
Pin-to-Pin Parameters .................................... 2-51
lOB ................................................................. 2-52
CLB ................................................................ 2-53
XC4005 Pinouts .................................................. 2-57
XC4006 Pinouts .................................................. 2-58
XC4008 Pinouts .................................................. 2-60
XC4010 Pinouts .................................................. 2-61
XC4013 Pinouts .................................................. 2-62
Ordering Information ........................................... 2-64
Component Availability ....................................... 2-64
2-5
II
Overview
XC4003A, XC4004A, and XC4005A. At the XC40051evel,
both device types are available; the XC4005A is more
economical, the XC4005 has more routing resources.
Since the devices are pin-compatible, the user can start
the design with the sure-to-route XC4005, then later switch
to the more economical XC4005A, if it is sufficient to
implement the design.
Introduced in 1990, the XC4000 family has found rapid
acceptance by demanding users. The RAM capability
offers a new freedom to design, the dedicated carry logic
speeds up arithmetic and counters, and the wide decoders
eliminate the need for external decoding.
Xilinx has met this enthusiastic user response with the
rapid introduction of new device types. Stretching from
2,000 to 13,000 gate capacity, the XC4000 family now has
11 part types available.
Some applications require more I/O than available in the
XC4000 and XC4000A families. This is especially true in
very large logic emulators where many XC4000 devices
are interconnected in a big matrix of devices. In these
applications, the classical Xilinx FPGA structure with two
lOBs at each end of each CLB row and column represents
an I/O bottleneck. For these and similar applications, Xilinx
offers the XC4003H and XC4005H devices with approximately twice the I/O count of the corresponding XC4000
device.
The XC4005, XC4006, XC4008, XC4010, and XC4013
represent the original concept, a structure with abundant
routing resources to accomodate even the most complex
design. Since smaller devices require disproportion ally
less routing resources, the low-end XC4000A family saves
silicon area and thus cost by having fewer interconnect
lines. The XC4000A family consists of the XC4002A,
2-6
XC4000, XC4000A, XC4000H
Logic Cell Array Families
Product Description
Features
Description
• Third Generation Field-Programmable Gate Arrays
- Abundant flip-flops
- Flexible function generators
- On-chip ultra-fast RAM
- Dedicated high-speed carry-propagation circuit
- Wide edge decoders
- Hierarchy of interconnect lines
- Internal 3-state bus capability
- Eight global low-skew clock or signal distribution
network
The XC4000 families of Field-Programmable Gate Arrays
(FPGAs) provide the benefits of custom CMOS VLSI, while
avoiding the initial cost, time delay, and inherent risk of a
conventional masked gate array.
The XC4000 families provide a regular, flexible, programmabie architecture of Configurable Logic Blocks (CLBs),
interconnected by a powerful hierarchy of versatile routing
resources, and surrounded by a perimeter of programmable Input/Output Blocks (lOBs).
XC4000-family devices have generous routing resources to
accommodate the most complex interconnect patterns.
XC4000A devices have reduced sets of routing resources,
sufficient for their smaller size. XC4000H high 1/0 devices
maintain the same routing resources and CLB structure as
the XC4000 family, while nearly doubling the available 1/0.
• Flexible Array Architecture
- Programmable logic blocks and 1/0 blocks
- Programmable interconnects and wide decoders
• Sub-micron CMOS Process
- High-speed logic and Interconnect
- Low power consumption
The devices are customized by loading configuration data
into the internal memory cells. The FPGA can either actively
read its configuration data out of external serial or byteparallel PROM (master modes), or the configuration data
can be written into the FPGA (slave and peripheral modes).
• Systems-Oriented Features
- IEEE 1149.1-compatible boundary-scan logic support
- Programmable output slew rate
- Programmable input pull-up or pull-down resistors
- 12-mA sink current per output (XC4000 family)
- 24-mA sink current per output (XC4000A and
XC4000H families)
The XC4000 families are supported by powerful and sophisticated software, covering every aspect of design: from
schematic entry, to simulation, to automatic block placement and routing of interconnects, and finally the creation
of the configuration bit stream.
• Configured by L~ading Binary File
- Unlimited reprogrammability
- Six programming modes
Since Xilinx FPGAs can be. reprogrammed an unlimited
number of times, they can be used in innovative deSigns
where hardware is changed dynamically, or where hardware must be adapted to different user applications. FPGAs
are ideal for shortening the design and development cycle,
but they also offer a cost-effective solution for production
rates well beyond 1000 systems per month.
• XACT Development System runs on '386/,486-type PC,
NEC PC, Apollo, Sun-4, and Hewlett-Packard 700
series
- Interfaces to popular design environments like
Viewlogic, Mentor Graphics and OrCAD
- Fully automatic partitioning, placement and routing
- Interactive design editor for design optimization
- 288 macros, 34 hard macros, RAM/ROM compiler
Table 1. The XC4000 Families of Field-Programmable Gate Arrays
XC4002A
Device
Appr. Gate Count
2,000
CLB Matrix
8x8
Number of CLBs
64
Number of Flip-Flops 256
Max Decode Inputs
24
(per side)
Max RAM Bits
2,048
Number of lOBs
64
'Planned
4003A 4003H 4004A 4005/5A 4005H
4008
4010
4013
4006
4016" 4020"
4,000
5,000
8,000 10,000 13,000 16,000 20,000
3,000
3,000
5,000
6,000
10 x 10 10 x 10 12 x 12 14 x 14 14 x 14 16 x 16 18 x 18 20 x 20 24 x 24 26 x 26 30x 30
100
100
144
196
196
256
324
400
576
676
900
200
1120
1768
2280
360
480
616
392
768
936
1536
30
30
36
42
42
48
54
72
78
90
60
3,200
80
3,200
160
4,608
96
6,272
112
2-7
6,272
192
8,192
128
10,368
144
12,800
160
18,432
192
21,632
208
28,800
240
II
XC4000, XC4000A, XC4000H Logic Cell Array Families
Increased number of interconnect resources.
All CLB inputs and outputs have access to most interconnect lines.
Switch Matrices are simplified to increase speed.
Eight global nets can be used for clocking or distributing
logic signals.
TBUF output configuration is more versatile and 3-state
control less confined.
XC4000 Compared to XC3000
For those readers already familiar with the XC3000 family
of Xilinx Field Programmable Gate Arrays, here is a
concise list of the major new features in the XC4000 family.
CLB has two independent 4-input function generators.
A third function generator combines the outputs of the
two other function generators with a ninth input.
All function inputs are swappable, all have full access;
none are mutually exclusive.
CLB has very fast arithmetic carry capability.
CLB function generator look-up table can also be used as
high-speed RAM.
CLB flip-flops have asynchronous set or reset.
CLB has four outputs, two flip-flops, two combinatorial.
CLB connections symmetrically located on all four edges.
Program is single-function input pin,overrides everything.
INIT pin also acts as Configuration Error output.
Peripheral Synchronous Mode (8 bit) has been added.
Peripheral Asynchronous Mode has improved handshake.
Start-up can be synchronized to any user clock (this is a
configuration option).
No Powerdown, but instead a Global 3-state input that
does not reset any flip-flops.
No on-chip crystal oscillator amplifier.
lOB has more versatile clocking polarity options.
lOB has programmable input set-up time:
long to avoid potential hold time problems,
short to improve performance.
lOB has Longline access through its own TBUF.
Outputs are n-channel only, 10werVoH increases speed,
outputs do not clamp to Vcc'
XC4000 outputs can be paired to double sink current to
24 mAo XC4000A and XC400H outputs can each sink
24 mA, can be paired for 48 mA sink current.
Configuration Bit Stream includes CRe error checking.
Configuration Clock can be increased to >8 MHz.
Configuration Clock is fully static, no constraint on the
maximum Low time.
Readback either ignores flip-flop content (avoids need for
masking) or it takes a snapshot of all flip-flops at the
start of Readback.
Readback has same polarity as Configuration and can be
aborted.
IEEE 1149.1-type boundary scan is supported in the I/O.
Wide decoders on all four edges of the LCA device.
Table 2. Three Generations of Xilinx Field-Programmable Gate Array Families
XC4013
XC3090/3190
XC2018
1,536
928
174
192
144
74
18,432
0
0
Function generators per CLB
3
2
2
Number of logic inputs per CLB
9
5
4
Number of logic outputs per CLB
4
2
2
8
2
2
Dedicated decoders
yes
no
no
Fast carry logic
yes
no
no
Internal 3-state drivers
yes
yes
no
Output slew-rate control
yes
yes
no
Power-down option
no
yes
yes
Crystal oscillator circuit
no
yes
yes
Parameter
Number of flip-flops
Max number of user I/O
Max number of RAM bits
Number of low-skew global nets
2-8
Architectural Overview
up to 50 MHz. The use of an advanced, sub-micron CMOS
process technology as well as architectural improvements
contribute to this increase in FPGA capabilities. However,
achieving these high logic-density and performance levels
also requires new and more powerful automated design
tools. IC and software engineers collaborated during the
definition of the third-generation lCA architecture to meet
an important performance goal - an FPGA architecture
and companion design tools for completely automatic
placement and routing of 95% of all designs, plus a
convenient way to complete the remaining few designs.
The XC4000 families achieve high speed through advanced semiconductor technology and through improved
architecture, and supports system clock rates of up to 50
MHz. Compared to olderXilinx FPGA families, the XC4000
families are more powerful, offering on-chip RAM and
wide-input decoders. They are more versatile in their
applications, and design cycles are faster due to a combination of increased routing resources and more sophisticated software. And last, but not least, they more than
double the available complexity, up to the 20,000-gate
level.
Configurable Logic Blocks
A number of architectural improvements contribute to the
increased logic density and performance levels of the
XC4000 families. The most important one is a more
powerful and flexible ClB surrounded by a versatile set of
routing resources, resulting in more "effective gates per
ClB." The principal ClB elements are shown in Figure 1.
Each new ClB also packs a pair of flip-flops and two
independent 4-input function generators. The two function
generators offer designers plenty of flexibility because
most combinatorial logic functions need less than four
inputs. Consequently, the design-software tools can deal
with each function generator independently, thus improving cell usage.
The XC4000 families have 11 members, ranging in complexity from 2,000 to 13,000 gates.
Logic Cell Array Families
Xilinx high-density user-programmable gate arrays include three major configurable elements: configurable
logic blocks (ClBs), input/output blocks (lOBs), and interconnections. The ClBs provide the functional elements
for constructing the user's logic. The lOBs provide the
interface between the package pins and internal signal
lines. The programmable interconnect resources provide
routing paths to connect the inputs and outputs of the ClBs
and lOBs onto the appropriate networks. Customized
configuration is established by programming internal static
memory cells that determine the logic functions and interconnections implemented in the lCA device.
Thirteen ClB inputs and four ClB outputs provide access
to the function generators and flip-flops. More than double
the number available in the XC3000 families, these inputs
and outputs connect to the programmable interconnect
resources outside the block. Four independent inputs are
provided to each of two function generators (F1 - F4 and
G1 - G4). These function generators, whose outputs are
labeled F' and G', are each capable of implementing any
arbitrarily defined Boolean function oftheirfour inputs. The
function generators are implemented as memory look-up
tables; therefore, the propagation delay is independent of
the function being implemented. A third function generator, labeled H', can implement any Boolean function of its
three inputs: F' and G' and a third input from outside the
block (H1). Signals from the function generators can exit
the ClB on two outputs; F' or H' can be connected to the
X output, and G' or H' can be connected to the Y output.
Thus, a ClB can be used to implement any two independent functions of up-to-four variables, or any single function
of five variables, or any function of four variables together
with some functions of five variables, or it can implement
even some functions of up to nine variables. Implementing
wide functions in a single block reduces both the number
of blocks required and the delay in the signal path, achieving both increased density and speed.
The first generation of lCA devices, the XC2000 family,
was introduced in 1985. It featured logic blocks consisting
of a combinatorial function generator capable of implementing 4-input Boolean functions and a single storage
element. The XC2000 family has two members ranging in
complexity from 800 to 1500 gates.
In the second-generation XC3000 lCA devices, introduced in 1987, the logic block was expanded to implement
wider Boolean functions and to incorporate a second flipflop in each logic block. Today, the XC3000 devices range
in complexity from 1,300 to 10,000 usable gates. They
have a maximum guaranteed toggle frequency ranging
from 70 to 270 MHz, equivalent to maximum system clock
frequencies of up to 80 MHz.
The third generation of lCA devices further extends this
architecture with a yet more powerful and flexible logic
block. I/O block functions and interconnection options
have also been enhanced with each successive generation, further extending the range of applications that can be
implemented with an lCA device.
The two storage elements in the ClB are edge-triggered
D-type flip-flops with common clock (K) and clock enable
(EC) inputs. A third common input (S/R) can be programmed as either an asynchronous set or reset signal
This third-generation architecture forms the basis of the
XC4000 families of devices that feature logic densities up
to 20,000 usable gates and support system clock rates of
2-9
I
XC4000, XC4000A, XC4000H Logic Cell Array Families
C1
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H1
G4
G3
-
G2
-
G1
-
LOGIC
FUNg;ION G'
F3
-
G1-G4
LOGIC
FUNCTION
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F2
-
F1
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(C LOCK)
F1-F4
C4
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F'
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Q - YQ
EC
RD
1
~
F'
~
D
V
LOGIC
FUNCTION
OF
H'
F',G',
AND
H1
I
EC
I
-F'
G'
H'
-
-
C3
L~
~
F4
C2
Y
r-
J
D
~
SD
Qe--- XQ
EC
RD
LLV
1
x
F'
D
MULTIPLEXER CONTROLLED
BY CONFIGURATION PROGRAM
X1519
Figure 1. Simplified Block Diagram of XC4000-Families Configurable Logic Block
independently for each of the two registers; this input also
can be disabled for either flip-flop. A separate global SeV
Reset line (not shown in Figure 1) sets or clears each
register during power-up, reconfiguration, or when a dedicated Reset net is driven active, This Reset net does not
compete with other routing resources; it can be connected
to any package pin as a global reset input.
and performance of adders, subtracters, accumulators,
comparators and even counters_
Each flip-flop can be triggered on either the rising or falling
clock edge. The source of a flip-flop data input is programmable: it is driven either by the functions F', G', and H', or
the Direct In (DIN) block input. The flipcflops drive the XQ
and YO CLB outputs.
The flexibility and symmetry of the CLB architecture facilitates the placement and routing of a given application.
Since the function generators and flip-flops have independent inputs and outputs, each can be treated as a
separate entity during placement to achieve high packing
density. Inputs, outputs, and the functions themselves can
freely swap positions within a CLB to avoid routing congestion during the placement and routing operation.
Multiplexers in the CLB map the four control inputs, labeled C1 through C4 in Figure 1, into the four internal
control signals (H1, DIN, SIR, and EC) in any arbitrary
manner.
In addition, each CLB F' and G' function generator contains dedicated arithmetic logic for the fast generation of
carry and borrow signals, greatly increasing the efficiency
2-10
network as well. With XC3000-families CLBs the designer
has to make a choice, either output the combinatorial
function orthe stored value. In the XC4000families, the flip
flops can be used as registers or shift registers without
blocking the function generators from performing a different, perhaps unrelated task. This increases the functional
density of the devices.
Speed Is Enhanced Two Ways
Delays in LCA-based designs are layout dependent. While
this makes it hard to predict a worst-case guaranteed
performance, there is a rule of thumb designers can
consider - the system clock rate should not exceed one
third to one half of the specified toggle rate. Critical
portions of a design, shift registers and simple counters,
can run faster - approximately two thirds of the specified
toggle rate.
When a function generator drives a flip-flop in a CLB, the
combinatorial propagation delay overlapscomplefe/ywith
the set-up time of the flip-flop. The set-up time is specified
between the function generator inputs and the clock input.
This represents a performance advantage over competing
technologies where combinatorial delays must be added
to the flip-flop set-up time.
The XC4000 family can run at synchronous system clock
rates of up to 60 MHz. This increase in performance over
the previous families stems from two basic improvements: improved architecture and more abundant routing
resources.
FastCarry: As described earlier, each CLB includes highspeed carry logic that can be activated by configuration.
The two 4-input function generators can be configured as
a 2-bit adder with built-in hidden carry that can be expanded to any length. This dedicated carry circuitry is so
fast and efficient that conventional speed-up methods like
carry generate/propagate are meaningless even at the
16-bit level, and of marginal benefit at the 32-bit level.
Improved Architecture
More Inputs:. The versatility of the CLB function generators improves system speed significantly. Table 3 shows
how the XC4000 families implement many functions more
efficiently and faster than is possible with XC3000 devices.
A 9-bit parity checker, for example, can be implemented in
one CLB with a propagation delay of 7 ns. Using a
XC3000-family device, the same function requires two
CLBs with a propagation delay of 2 x 5.5 ns = 11 ns. One
XC4000 CLB can determine whether two 4-bit words are
identical, again with a 7-ns propagation delay. The ninth
input can be used for simple ripple expansion of this
identity comparator (25.5 ns over 16 bits, 51.5 ns over
32 bits), or a 2-layer identity comparator can generate the
result of a 32-bit comparison in 15 ns, at the cost of a single
extra CLB. Simpler functions like multiplexers also benefit
from the greater flexibility of the XC4000-families CLB. A
16-input multiplexer uses 5 CLBs and has a delay of only
13.5 ns.
A 16-bitadder requires nine CLBs and has a combinatorial
carry delay of 20.5 ns. Compare that to the 30 CLBs and
50 ns, or 41 CLBs and 30 ns in the XC3000 family.
More Outputs: The CLB can pass the combinatorial
output(s) to the interconnect network, but can also store
the combinatorial result(s) or other incoming data in one or
two flip-flops, and connect their outputs to the interconnect
Faster andMore Efficient Counters:The XC4000-families fast-carry logic puts two counter bits into each CLB and
runs them at a clock rate of up to 42 MHz for 16 bits,
whether the counters are loadable or not. For a 16-bit
The fast-carry logic opens the door to many new applications involving arithmetic operation, where the previous
generations of FPGAs were not fast and/or not efficient
enough. High-speed address offset calculations in microprocessor or graphics systems, and high-speed addition in
digital signal processing are two typical applications.
Table 3. Density and Performance for Several Common Circuit Functions
XC3000 (-125)
16-bit Decoder From Input Pad
24-bit Accumulator
State Machine Benchmark'
16:1 Multiplexer
16-bit Undirectional
Loadable Counter
16-bit UfO Counter
16-bit Adder
Max Density
Max Speed
Max Density
Max Speed
Max Density
Max Speed
15 ns
17 MHz
35 MHz
16 ns
20 MHz
34 MHz
20 MHz
30 MHz
50 ns
30ns
• 16 states, 40 transitions, 10 inputs, 8 outputs
2-11
4CLBs
46 CLBs
18 CLBs
8 CLBs
16 CLBs
23 CLBs
16 CLBs
27 CLBs
3D CLBs
41 CLBs
XC4000(-5)
12 ns
32 MHz
44 MHz
16 ns
40 MHz
42 MHz
40 MHz
40 MHz
20.5 ns
20.5 ns
OCLBs
13 CLBs
13 CLBs
5CLBs
8 CLBs
9CLBs
8CLBs
8CLBs
9CLBs
9CLBs
II
XC4000, XC4000A, XC4000H Logic Cell Array Families
COUT
A1
LOGIC
FUNCTION
OFG1-G4
G'
G2
B1
SUM 1
-+-----'
G1--t----!~~~--i-------~
Higher Output Current: The 4-mA maximum output
current specification of today's FPGAs often forces the
user to add external buffers, cumbersome especially on
bidirectional I/O lines. The XC4000 families solve many of
these problems by increasing the maximum output sink
current to 12 mAo Two adjacent outputs may be interconnected to increase the output sink current to 24 mAo The
FPGA can thus drive short buses on a pc board. The
XC4000A and XC4000H outputs can sink 24 mA per
output and can double up for 48 mAo
CIN1
CIN2
F4
F3
LOGIC
FUNCTION
OFF1-F4
F'
BO
F2
AO
F1
decoder outputs in a CLB. This decoding feature covers
what has long been considered a weakness of FPGAs.
Users often resorted to external PALs for simple but fast
decoding functions. Now, the dedicated decoders in the
XC4000 can implement these functions efficiently and
fast.
SUMO
Figure 2_ Fast Carry Logic in Each CLB
While the XC2000 and XC3000 families used complementary output transistors, the XC4000 outputs are n-channel
for both pull-down and pull-up, somewhat analogous to the
classical totem pole used in TTL. The reduced output High
level (VOH) makes circuit delays more symmetrical for
TTL-threshold systems. The XC4000H outputs have an
optional p-channel output transistor.
up/down counter, this means twice the speed in half the
number of CLBs, compared with the XC3000 families_
Pipelining Speeds Up The System: The abundance of
flip-flops in the CLBs invites pipelined designs_ This is a
powerful way of increasing performance by breaking the
function into smaller subfunctions and executing them
in parallel, passing on the results through pipeline flipflops_ This method should be seriously considered wherever total performance is more important than simple
through-delay_
Abundant Routing Resources
Connections between blocks are made by metal lines with
programmable switching points and switching matrices.
Compared to the previous LCA families, these routing
resources have been increased dramatically.The number
of globally distributed signals has been increased from two
to eight, and these lines have access to any clock or logic
input. The designer of synchronous systems can now
distribute not only several clocks, but also control Signals,
all over the chip, without having to worry about any skew.
Wide Edge Decoding: For years, FPGAs have suffered
from the lack of wide decoding circuitry. When the address
or data field is wider than the function generator inputs (five
bits in the XC3000 families), FPGAs need multi-level
decoding and are thus slower than PALs. The XC4000family CLBs have nine inputs; any decoder of up to nine
inputs is, therefore, compact and fast. But, there is also a
need for much wider decoders, especially for address
decoding in large microprocessor systems. The XC4000
family has four programmable decoders located on each
edge of each device. Each of these wired-AND gates is
capable of accepting up to 42 inputs on the XC4005 and 72
on the XC4013. These decoders may also be split in two
when a large number of narrower decoders are required
for a maximum of 32 per device. These dedicated decoders accept I/O signals and internal signals as inputs and
generate a decoded internal signal in 18 ns, pin-to-pin. The
XC4000A family has only two decoder AND gates per
edge which, when split provide a maximum of 16 per
device. Very large PALs can be emulated by ORing the
There are more than twice as many horizontal and vertical
Longlines that can carry signals across the length or width
of the chip with minimal delay and negligible skew.The
horizontal Longlines can be driven by 3-state buffers, and
can thus be used as unidirectional or bidirectional data
buses; or they can implement wide mUltiplexers or wiredAND functions.
Single-length lines connect the switching matrices that are
located at every intersection of a row and a column of
CLBs. These lines provide the greatest interconnect flexibility, but cause a delay whenever they go through a
switching matrix. Double-length lines bypass every other
matrix, and provide faster signal routing over intermediate
distances.
Compared to the XC3000 family, the XC4000 families
have more than double the routing resources, and they are
arranged in a far more regular fashion. In older devices,
2-12
~XIUNX
inputs could not be driven by all adjacent routing lines. In
the XC4000 families, these constraints have been largely
eliminated. This makes it easier for the software to complete the routing of complex interconnect patterns.
C1
Chip architects and software designers worked closely
together to achieve a solution that is not only inherently
powerful, but also easy to utilize by the software-driven
design tools for Partitioning, Placement and Routing. The
goal was to provide automated push-button software tools
that complete almost all designs, even large and dense
ones, automatically, without operator assistance. Butthese
tools will still give the designer the option to get involved in
the partitioning, placement and, to a lesser extent, even
the routing of critical parts of the design, if that is needed
to optimize the performance.
C2
C3
C4
G4
G3
G2
G'
FUNCTION
GENEAATOR
G1
WE
DATA
IN
F4
Fa
F2
On-Chip Memory
The XC4000, XC4000A and XC4000H family devices are
the first programmable logic devices with RAM accessible
to the user.
F'
FUNCTION
GENERATOR
G
CONFIGURATION MEMORY BIT
F1
Figure 3. CLB Function Generators Can Be Used as
ReadIWtite Memory Cells
An optional mode for each CLB makes the memory lookup tables in the F' and G' function generators usable as
either a 16 x 2 or 32 x 1 bit array of ReadlWrite memory
cells (Figure 3). The F1-F4 and G1-G4 inputs to the
function generators act as address lines, selecting a
particular memory cell in each look-up table. The functionality of the CLB control signals change in this configuration; the H1, DIN, and SIR lines become the two data inputs
and the Write Enable (WE) input for the 16 x 2 memory.
When the 32 x 1 configuration is selected, 01 acts as the
fifth address bit and DO is the data input. The contents of
the memory cell(s) being addressed are available at the F'
and G' function-generator outputs, and can exit the CLB
through its X and Y outputs, or can be pipelined using the
CLB flip-flop(s).
Input/Output Blocks (lOBs), XC4000 and XC4000A
Families (for XC4000H family, see page 2-82)
User-configurablelOBs provide the interface between
external package pins and the internal logic (Figure 5).
Each lOB controls one package pin and can be defined for
input, output, or bidirectional signals.
Two paths, labeled 11 and 12, bring input signals into the
array. Inputs are routed to an input register that can be
programmed as either an edge-triggered flip-flop or a
level-sensitive transparent latch. Optionally, the data input
to the register can be delayed by several nanoseconds to
compensate forthe delay on the clock signal, thatfirst must
Configuring the CLB function generators as ReadlWrite
memory does not affect the functionality of the other
portions of the CLB, with the exception of the redefinition
of the control signals. The H' function generator can be
used to implement Boolean functions of F', G', and 01, and
the 0 flip-flops can latch the F', G', H', or DO signals.
The RAMs are very fast; read access is the same as logic
delay, about 5.5 ns; write time is about 8 ns; both are
several times faster than any off-chip solution. Such distributed RAM is a novel concept, creating new possibilities
in system design: registered arrays of multiple accumulators, status registers, index registers, DMA counters, distributed shift registers, LIFO stacks, and FIFO buffers. The
data path of a 16-byte FIFO uses four CLBs for storage,
and six CLBs for address counting and multiplexing (Figure 4). With 32 storage locations per CLB, compared to two
flip-flops per CLB, the cost of intelligent distributed memory
has been reduced by a factor of 16.
Figure 4. Hi-byte FIFO
2-13
II
XC4000, XC4000A, XC4000H Logic Cell Array Families
pass through a global buffer before arriving atthe lOB. This
eliminates the possibility of a data hold-time requirement
at the external pin. The 11 and 12 signals that exit the block
can each carry either the direct or registered input signal.
Output signals can be inverted or not inverted, and can
pass directly to the pad or be stored in an edge-triggered
flip-flop. Optionally, an ()utput enable signal can be used to
place the output buffer in a high-impedance state, implementing 3-state outputs or bidirectional I/O. Under configuration control, the output (OUT) and output enable
(OE) signals can be inverted, and the slew rate of the
output buffer can be reduced to minimize power bus
transients when switching non-critical signals. Each
XC4000-families,output buffer is capable of sinking 12 mA;
two adjacent output buffers can be wire-ANDed externally
to sink up to 24 mA. In the XC4000A and XC4000H
families, each output buffer can sink 24 mAo
Programmable Interconnect
All internal connections are composed of metal segments
with programmable switching points to implement the
desired routing. An abundance of different routing resources is provided to achieve efficient automated routing.
The number of routing channels is scaled to the size of the
array; i.e., it increases with array size.
In previous generations of LCAs, the logic-block inputs
were located on the top, left, and bottom of the block;
outputs exited the block on the right, favoring left-to-right
data flow through the device. For the third-generation
family, the CLB inputs and outputs are distributed on all
four sides of the block, providing additional routing flexibility (Figure 6). In general, the entire architecture is more
symmetrical and regular than that of earlier generations,
and is more suited to well-established placement and
routing algorithms developed for conventional mask- programmed gate-array design.
There are a numberof other programmable options in the
lOB. Programmable pull-up and pull-down resistors are
useful for tying unused pins to Vee or ground to minimize
power consumption. Separate clock signals are provided
for the input and output registers; these clocks can be
inverted, generating either falling-edge or rising"edge triggered flip-flops. As is the case with the CLB registers, a
global set/reset signal can be used to set or clear the input
and output registers whenever the RESET net is active.
There are three main types of interconnect, distinguished
by the relative length oftheir segments: single-length lines,
double-length lines, and Longlines. Note: The number of
routing channels shown in Figures 6 and 9 are for illustration purposes only; the actual number of routing channels
varies with array size. The routing scheme was designed
for minimum resistance and capacitance of the average
routing path, resulting in significant performance improvements.
Embedded logic attached to the lOBs contains test structures compatible with IEEE Standard 1149.1 for boundaryscan testing, permitting easy chip and board-level testing.
The single-length lines are a grid of horizontal and vertical
lines that intersect at a Switch Matrix between each block.
Figure 6 illustrates the single-length interconnect lines
Willil
:::j
=l
Switch
Matrix
OE
F4
-4<~""---l
OUT
C4
G4
YO
Gl
---+~O++;--\Cl
-+-I#l#t--\K
---+~o++;--\ Fl
--1<»+1'#1--.,--\ x
1
1
1
1
1
CLB
C31--4<~""~
F31--4<~""~
XO
1
1
F2
C2
G2
-I
1
~
1
1
INPUT
CLOCK
Switch
~ Matrix
1
1
1
1
1
- - - __ - - - - - - __ - - - - __ - - ____ I
Switch
~
1mm
X3242
Figure 6. Typical CLB Connections to Adjacent
Single-Length Lines
Figure 5. XC4000 and XC4000A Families
Input/Output Block
2-14
surrounding one CLB in the array. Each Switch Matrix
consists of programmable n-channel pass transistors used
to establish connections between the single-length lines
(Figure 7). For example, a signal entering on the right side
of the Switch Matrix can be routed to a single-length line on
the top, left, or bottom sides, or any combination thereof,
if multiple branches are required. Single-length lines are
normally used to conduct signals within a localized area
and to provide the branching for nets with fanout greater
than one.
I
Compared to the previous generations of LCA architectures, the number of possible connections through the
Switch Matrix has been reduced. This decreases capacitive loading and minimizes routing delays, thus increasing
performance. However, a much more versatile set of
connections between the single-length lines and the CLB
inputs and outputs more than compensate for the reduction in Switch Matrix options, resulting in overall increased
routability.
I
I
,I
I
AI-YH----'~K
yx'-rt
;1
X 'IT-'
'I
-'If--+-+I-I----> 1\'
I'
9II
II
~Switeh1/
Matrices
The function generator and control inputs to the CLB (F1F4, G1-G4, and C1-C4) can be driven from any adjacent
single-length line segment (Figure 6). The CLB clock (K)
input can be driven from one-half of the adjacent singlelength lines. Each CLB output can drive several of the
single-length lines, with connections to both the horizontal
and vertical Longlines.
r--
X3245
Figure 8. Double-length lines
Longlines form a grid of metal interconnect segments that
run the entire length or width of the array (Figure 9).
Additional verticallonglines can be driven by special global
buffers, designed to distribute clocks and other high fanout
control signals throughout the array with minimal skew.
Longlines are intended for high fan-out, time-critical signal
nets. Each Longline has a programmable splitter switch at
its center, that can separate the line into two independent
routing channels, each running half the width or height of
the array. CLB inputs can be driven from a subset of the
adjacent Longlines; CLB outputs are routed to the Longlines
via 3-state buffers or the single-length interconnected
lines.
The double-length lines (Figure 8) consist of a grid of metal
segments twice as long as the single-length lines; i.e, a
double-length line runs past two CLBs before entering a
Switch Matrix. Double-length lines are grouped in pairs
with the Switch Matrices staggered so that each line goes
through a Switch Matrix at every other CLB location in that
row or column. As with single-length lines, all the CLB
inputs except K can be driven from any adjacent doublelength line, and each CLB output can drive nearby doublelength lines in both the vertical and horizontal planes.
Double-length lines provide the most efficient implementation of intermediate length, point-to-point interconnections.
F4
c.
G4
YQ
Gl
Y
Cl
G3
K
CLB
C3
Fl
X
F3
XQ
Six Pa58 Transistors
PerS witch Matrix
Intereonneet Point
X3244
F2
C2
G2
'-v---'
'-v---'
"Globar
Long Lines
Long Lines
"Globat~
X3243
Figure 9. longline Routing Resources with
Typical ClB Connections
Figure 7. Switch Matrix
2-15
II
XC4000, XC4000A, XC4000H Logic Cell Array Families
Communication between Longlines and single-length lines
is controlled by programmable interconnect points at the
line intersections. Double-length lines do not connect to
other lines.
Three-State Buffers
A pair of 3-state buffers, associated with each CLB in the
array, can be used to drive signals onto the nearest
horizontal Longlines above and below the block. This
feature is also available in the XC3000 generation of LCA
devices. The 3-state buffer input can be driven from any
X, Y, XQ, or YQ output of the neighboring CLB, or from
nearby single-length lines; the buffer enable can come
from nearby vertical single-length or Longlines. Another
3-state buffer with similar access is located near each 1/0
block along the right and left edges of the array. These
buffers can be used to implement multiplexed or bidirectional buses on the horizontal Longlines. Programmable
pull-up resistors attached to both ends of these Longlines
help to implement a wide wired-AND function.
The XACT Design Manager (XDM) simplifies the selection
of command-line options with pull-down menus and online help text. Application programs ranging from schematic capture to Partitioning, Placement, and Routing
(PPR) can be accessed from XDM, while the programcommand sequence is generated and stored for documentation prior to execution. The XMake command in
XDM automates the entire process, from design entry to
the generation of configuration and report files.
Similar to that for the XC2000 and XC3000 families, the
XC4000 design flow consists of three steps-Design Entry,
Design Implementation, and Design Verification.
Design Entry
Adesign can be entered using schematic-capture software,
state-machine description or Boolean-equation entry.
Xilinx and third-party vendors have developed library and
interface products compatible with a wide variety of design-entry and simulation environments. A standard interface-file specification, XNF, is provided to simplify file
transfers into and out of the XACT development system.
Special Longlines running along the perimeter of the array
can be used to wire-AND signals coming from nearby lOBs
or from internal Longlines.
Xilinx offers XACT development-system interfaces to the
following design environments.
Taking Advantage of Reconfiguration
LCA devices can be reconfigured to change logic function
while resident in the system. This gives the system deSigner a new degree of freedom, not available with any
other type of logic. Hardware can be changed as easily as
software. Design updates or modifications are easy. An
LCA device can even be reconfigured dynamically to
perform differentfunctions at differenttimes. Reconfigurable
logic can be used to implement system self diagnostics,
create systems capable of being reconfigured for different
environments or operations, or implement dual-purpose
hardware for a given application. As an added benefit, use
of reconfigurable LCA devices simplifies hardware design
and debugging and shortens product time-to-market.
• Viewlogic Viewdraw and Viewsim
• Mentor Graphics V7 and va
• Cadence Composer Schematic Entry, Verilog
Simulator
• OrCAD
Several other environments are supported by third-party
vendors. Currently, more than 100 packages are supported.
Macro Libraries
Along with the standard library of Soft Macros, like those
included with the XC3000 families, the XC4000 family also
include a library of Hard Macros. The Soft Macro library
contains detailed descriptions of common logic functions
such as counters, adders, etc.; it does not contain any
partitioning or routing information. The performance of
Soft Macros depends, therefore, on how the PPR software
processes the macro.
Development System
The powerful features of the XC4000 device families
require an equally powerful, yet easy-to-use set of development tools. Xilinx provides an enhanced version of the
Xilinx Automatic CAE tools (XACT) optimized for the
XC4000 families.
Hard Macros, on the other hand, do contain complete
partitioning, placement, and routing information. These
predefined and tested functions permit the user to build
timing-critical designs with optimized performance.
Designing with Hard Macros is as easy as designing with
MSI/LSI.
The advanced XC4000 XACT features include a memory
compiler, MenGen, that takes advantage of the on-chip
RAM, and Hard Macros that offer consistent performance
for over 30 common logic functions. To address
performance predictability, XACT now includes XACT
Performance, that accepts performance requirements
entered at the schematic level, then partitions, places and
routes the design.
2-16
288 Soft Macros
(Simplify Schematic Entry)
11
43
7
7
8
13
23
16
2
1
16
26
3
2
59
16
12
23
based editor that displays a model of the actual logic and
routing resources of the FPGA. XDE can be used to
directly view the results achieved by the automated tools.
Modifications can be made using XDE; XDE can also
perform checks for logic connectivity and possible designrule violations.
Gates
Flip-Flops
Buffers
Latches
Adders/Subtactors
Comparators
Multiplexers
Decoders
Priority Encoders
Parity Checker
Data Registers
Shift Registers
RAMs
ROMS
Counters
1/0 Circuits
Flags
Special Functions
Interactive point-to-point timing-delay calculations provide
timing analysis and help to determine critical paths. The
user can, thus, identify and correct timing problems while
the design is still in process.
DeSign Verification
The high development cost associated with common maskprogrammed gate arrays necessitates extensive simulation to verify a design. Due to the custom nature of masked
gate arrays, mistakes or last-minute design changes cannot be tolerated. A gate-array designer must simulate and
test all logic and timing using simulation software. Simulation describes what happens in a system underworst-case
situations. However, simulation is tedious and slow; somebody has to write simulation vectors. A few seconds of
system time can take weeks to simulate.
34 Hard Macros
(Pre-Partitioned) Predictable Performance
2
2
4
3
4
1
2
1
9
2
2
2
Adders
Accumulators
Comparators
Multiplexers
Decoders
Encoders
Parity Generators
Prescaler
RAMs, (4, 8, 16 wide, 16, 32 deep)
Data Registers
Shift Registers
Counters
Programmable-gate-array users, however, can use incircuit debugging techniques in addition to simulation.
Because Xilinx devices are reprogram mable, designs can
be verified in the system in real time without the need for
extensive simulation vectors.
The XACT development system supports both simulation
and in-circuit debugging techniques. For simulation, the
system extracts the post-layout timing information from
the design database. This data can then be sent to the
simulator to verify timing-critical portions of the design.
For in-circuit debugging,XACT has a serial download and
readback cable (XChecker) that connects the device in the
system to the PC or workstation through an RS232 serial
port. The engineer can download a design or a design
revision into the system for testing. The designer can also
single-step the logic, read the contents of the numerous
flip-flops on the device and observe the internal logic
levels. Simple modifications can be downloaded into the
system in a matter of minutes.
Design Implementation
The design-implementation tools have been greatly enhanced to cope with the higher density of the XC4000
devices and to satisfy the requirement for a completely
automated design process. Logic partitioning, block placement and signal routing encompass the design implementation process. The partitioner takes the logic from the
schematic or other entry method, and divides the logic to
fit into the blocks available on the device. The placer then
determines the best locations for the blocks, depending on
their connectivity and the required performance. The router
finally connects the placed blocks together.
Summary
The result of eight years of FPGA design experience and
feedback from thousands of customers, the XC4000 families combine architectural versatility, on-chip RAM, in- creased speed and gate complexity with abundant routing
resources and new, sophisticated software to achieve fully
automated implementation of complex, high-performance
designs.
The improved PPR algorithms result in fully automatic
implementation of most designs. The new algorithms also
reduce execution time compared to previous software
generations.
The automated implementation tools are complemented
by the XACT Design Editor (XDE), an interactive graphics-
2-17
II
XC4000, XC4000A, XC4000H Logic Cell Array Families
Barrel Shifters
7400 Equivalents
'42
'48
'83
'85
'138
'139
'147
'148
'150
'151
'152
'153
'154
'157
'158
'160
'161
'162
'163
'164
'165s
'166
'168
'169
'174
'179
'194
'195
'198
'199
'257
'258
'259
'273
'278
'280
'283
'298
'352
'374
'390
'393
'518
'521
#of CLBs
5
8
4
4
4
2
4
6
5
2
2
2
9
2
2
5
6
5
7
4
4
5
9
3
4
3
9
5
2
2
17
brlshft4
brlshft8
Decoders
4
12
4-Bit Counters
c10bcrd
c10cprd
c16bcr
c16bcrd
c16cprd
c16budrd
2
4
2
2
4
5
5, 6, 8-Bit Counters
d2-4e
d3-8e
d4-16
d4-16e
2
4
8
16
Multiplexers
m2-1e
m4-1
m4-1e
m8-1e
m16-1e
0.5
1
2
2
5
Registers
c32budrd
c64budrd
c256bcr
c256bcrd
c256bcpr
6
9
7
5
8
Identity Comparators
1
2
4
9
comp4
comp8
comp16
comp32
Magnitude Comparators
compm4
compm8
compm16
compm32
rd4r
rd8r
rd16r
2
4
8
Shift Registers
rs8p
rsr16
rsr32
4
2
16
RAMs
ram 16x4
2
3
8 (5)
17 (9)
39
4
2
4
2
2
4
2
2
2
Explanation of counter nomenclature:
b=binary, p=synchronous parallelloadable, ud=up/down, c=count enable,
r=synchronOUS reset, rd=asynchronous reset direct.
Note:
When a device is not fully utilized, the automatic partitioner may assign a larger number of CLBs in order to
improve speed and routing. Values in parentheses refer to Hard Macros.
Figure 10. CLB Count of Selected XC4000 Soft Macros
2-18
Detailed Functional Description
Each output buffer can be configured to be either fast or
slew-rate limited, which reduces noise generation and
ground bounce. Each 1/0 pin can be configured with either
an internal pull-up or pull down resistor, or with no internal
resistor. Independent of this choice, each lOB has a pullup resistor during the configuration process.
XC4000 and XC4000A Input/Output Blocks
(For XC4000H family, see page 2-82)
The lOB forms the interface between the internal logic and
the 1/0 pads of the LCA device. Under configuration control, the output buffer receives either the logic signal (.out)
routed from the internal logic to the lOB, orthe complement
of this signal, or this same data after it has been clocked
into the output flip-flop.
The 3-state output driver uses a totem pole n-channel
output structure. VOH is one n-channel threshold lower
than V cC' which makes rise and fall delays more
symmetrical.
As a configuration option, each flip-flop (CLB or lOB) is
initialized as either set or reset, and is alsq forced into this
programmable initialization state whenever the global Set!
Reset net is activated after configuration has been completed. The clock polarity of each lOB flip-flop can be
configured individually, as can the polarity of the 3-state
control for the output buffer.
Family
Per lOB
Source
Per lOB
Sink
Per lOB
Pair Sink
# Slew
Modes
XC4000
4
12
24
2
XC4000A
4
24
48
4
XC4000H
4
24*
48
2
*XC4000H devices can sink only 4 mA configured for SoftEdge mode
EXTEST
TSINV
SLEW
RATE
PULL
DOWN
PULL
UP
3.Slate TS _-------'Tc::SI'-"O;::,E- - - - - I I
Vee
Boundary {TS •
Scan
TS· update
OUTPUT
_---I
----II
Ouput Data 0
Ouput Clock OK
------++--11-.1
O' capture
Boundary { Q • capture
Scan
0- update
1
1. capture
Boundary
Scan
1- update
\ - - - - -.. Input Data 1 11
--+--.-1
\ - - - - -.. Input Data 212
Input Clock IK
-------+-+--IL--I
INPUT
GLOBAL
SIR
X3025
Figure 11. XC4000 and XC4000A I/O Block
2-19
II
XC4000, XC4000A, XC4000H Logic Cell Array Families
The inputs drive TTL-compatible buffers with 1.2-V input
threshold and a slight hysteresis of about 300 mY. These
buffers drive the internal logic as well as the D-input of the
input flip-flop.
Under configuration control, the set-up time of this flip-flop
can be increased so that normal clock routing does not
result in a hold-time problem. Note that the input flip-flop
set-up time is defined between the data measured at the
device I/O pin and the clock input at the lOB. Any clock
routing delay must, therefore, be subtracted from this setup time to arrive at the real set-up time requirement on the
device pins. A short specified set-up time might, therefore,
result in a negative set-up time at the device pins, i.e. a
hold-time requirement, which is usually undesirable. The
optional long set-up time can tolerate more clock delay
without causing a hold-time requirement.
Configurable Logic Blocks
Configurable Logic Blocks implement most of the logic in
an LCA device. Two 4-input function generators (F and G)
offer unrestricted versatility. A third function generator (H)
can combine the outputs of F and G with a ninth input
variable, thus implementing certain functions of up to nine
variables, like parity check or expandable-identity comparison of two sets of four inputs.
The four control inputs C1 through C4 can each generate
anyone of four logic Signals, used in the CLB.
• Enable Clock, Asynchronous Preset/Reset, DIN, and
H1, when the memory function is disabled, or
• Enable Clock, Write Enable, DO, and D1, when the
memory function is enabled.
Since the function-generator outputs are brought out independently of the flip-flop outputs, and DIN and H1 can be
used as direct inputs to the two flip-flops, the two combinatorial and the two sequential functions in the CLB can be
used independently. This versatility increases iogic density and simplifies routing.
The input block has two connections to the internal logic,
11 and 12. Each of these is driven either by the incoming
data, by the master or by the slave of the input flip-flop.
Wide Decoders
The asynchronous flip-flop input can be configured as
either set or reset. This configuration option also determines the state in which the flip-flops become operational
after configuration, as well as the effect of an externally or
internally applied Set/Reset during normal operation.
The periphery of the chip has four wide decoder circuits at
each edge (two in the XC4000A). The inputs to each
decoder are any of the 11 signals on that edge plus one
local interconnect per CLB row or column. Each decoder
generates High output (resistor pull-up) when the AND
condition of the selected inputs, or their complements, is
true. This is analogous to the AND term in typical PAL
devices. Each decoder can be split at its center.
Fast Carry Logic
The CLBs can generate the arithmetic-carry output for
incoming operands, and can pass this extra output on to
the next CLB function generator above or below. This
connection is independent of normal routing resources
and it is, presently, only supported by Hard Macros. A later
software release will accomodate Soft Macros and will
permit graphic editing of the fast logic circuitry. This fast
carry logic is one of the most significant improvements in
the XC4000 families, speeding up arithmetic and counting
into the 60-MHz range.
The decoder outputs can drive CLB inputs so they can be
combined with other logic, or to form a PAL-like AND/OR
structure. The decoder outputs can also be routed directly
to the chip outputs. For fastest speed, the output should be
on the same chip edge as the decoder.
INTERCONNECT
USing Function Generators as RAMs
Using XC4000 devices, the designer can write into the
latches that hold the configuration content of the function
generators. Each function generator can thus be used as
a small Read/Write memory, or RAM. The function generators in any CLB can be configured in three ways.
c
• Two 16 x 1 RAMs with two data inputs and two data
outputs - identical or, if preferred, different addressing for each RAM
C) .....
-4-+---+--+---t-t----4-+---+--+----+-+-----
(Ao B 0
(;) •••••
(A
B C) .... .
--f--+----+--+----+-t---- (A
B C) .... .
• One 32 x 1 RAM with one data input and one data
output
X2627
• One 16 x 1 RAM plus one 5-input function generator
Figure 12. Example of Edge Decoding. Each row orcolumn of
CLBs provide up to three variables (or their complements)
2-20
Cl
C2
C3
C4
G4
G3
LOGIC
FUNCTION
G'
OF
Gl-G4
G2
a
YO
Gl
LOGIC
FUNCTION
OF
H'
F',G',
AND
Hl
L---I--+----------- Y
II
F4
F3
LOGIC
FUNCTION
OF
Fl-F4
F2
a
P
xo
Fl
1----1-IEC
RD
K
(CLOCK)
~-----------------------------------------X
D
MULTIPLEXER CONTROLLED
BY CONFIGURATION PROGRAM
X1519
Figure 13_ Simplified Block Diagram of XC4000 Configurable Logic Block
COUT
Al
G'
G2
61
C1
C2
C3
C4
LOGIC
FUNCTION
OFG1-G4
SUMl
---t-----'
G l - t - - - t - I I t - - {______~
G4
G3
G'
G2
GENERATOR
FUNCTION
CIN 1
G1
CIN2
F4
F3
WE
LOGIC
FUNCTION
OFF1-F4
F4
F3
F'
BD
F2
AO
Fl
SUMO
F2
DATA
IN
p
fUNCTION
GENERATOR
G
CONFIGURATION MEMORY BIT
F1
Figure 15. CLB Function Generators Can Be Used as
ReadlWrite Memory Cells
Figure 14_ Fast Carry Logic in Each CLB
2-21
XC4000, XC4000A, XC4000H Logic Cell Array Families
Boundary Scan
Boundary Scan is becoming an attractive feature that
helps sophisticated systems manufacturers test their PC
boards more safely and more efficiently. The XC4000
family implements IEEE 1149.1-compatible BYPASS,
PRELOAD/SAMPLE and EXTEST Boundary-Scan instructions. When the Boundary-Scan configuration option is
selected, three normal user 1/0 pins become dedicated
inputs for these functions.
user scan data to be shifted out on TDO. The data register
clock (BSCAN.DRCK) is available for control of test logic
which the user may wish to implement with CLBs. The
NAND of TCK and Run-test-idle is also provided
(BSCAN.IDLE).
The "bed of nails" has been the traditional method of
testing electronic assemblies. This approach has become
less appropriate, due to closer pin spacing and more
sophisticated assembly methods like surface-mount technology and multi-layer boards. The IEEE Boundary Scan
standard 1149.1 was developed to facilitate board-level
testing of electronic assemblies. Design and test engineers can imbed a standard test logic structure in their
electronic design. This structure is easily implemented
with the serial andlor parallel connections of a four-pin
interface on any Boundary-Scan-compatible IC. By exercising these signals, the user can serially load commands
and data into these devices to control the driving of their
outputs and to examine their inputs. This is an improvement over bed-of-nails testing. It avoids the need to overdrive device outputs, and it reduces the user interface to
four pins. An optional fifth pin, a reset for the control logic,
is described in the standard but is not implemented in the
Xilinx part.
Table 4. Boundary Scan Instruction
The XC4000 Boundary Scan instruction set also includes
instructions to configure the device and read back the configuration data.
Test
Selected
Instruction
I,
12
10
0
0
0
TOO
Source
I/O Data
Source
Extest
DR
DR
0
0
I
Sample/Preload
DR
Pin/Logic
0
I
0
User I
TOOl
Pin/Logic
0
I
I
User 2
T002
Pin/Logic
I
0
0
Readback
Readback Data
Pin/Logic
I
0
I
Configure
DOUT
Disabled
I
I
0
Reserved
I
I
I
Bypass
Bypass Reg
Pin/Logic
X2679
Bit Sequence
The bit sequence within each lOB is: in, out, 3-state.
From a cavity-up (XDE) view of the chip, starting in the
upper right chip corner, the Boundary-Scan data-register
bits have the following order.
Table 5. Boundary Scan Order
The dedicated on-chip logic implementing the IEEE 1149.1
functions includes a 16-state machine, an instruction register and a number of data registers. A register operation
begins with a capturewhere a set of data is parallel loaded
into the designated register for shifting out. The next state
is shift, where captured data are shifted out while the
desired data are shifted in. A number of states are provided
for Wait operations. The last state of a register sequence
is the update where the shifted content of the register is
loaded into the appropriate instruction- or data-hOlding
register, either for instruction-register decode or for dataregister pin control.
Bit 0 ( TOOemd)
Bit I
Bit 2
TDO.T
TDO.O
{ Top·edge lOBs (Right to Left)
{ Left·edge lOBs (Top to Bottom)
MD
MD1.T
MDI.O
MDI.I
MDO.l
MD2.1
{ Bottom-edge lOBs (Left to Right)
The primary data register is the Boundary-Scan register.
For each lOB pin in the LCA device, it includes three bits
of shift register and three update latches for: in, out and 3state control. Non-lOB pins have appropriate partial bit
population for in or out only. Each Extest Capture captures
all available input pins.
{ Right-edge lOBs (Bottom to Top)
(TDlend)
B SCANT.UPD
X2674
The data register also includes the following non-pin bits:
TDO.T, and TDO.!, which are always bits 0 and 1 of the
data register, respectively, and BSCANT.UPD which is
always the last bit of the data register. These three Boundary-Scan bits are special-purpose Xilinx test signals. PROGRAM, CCLK and DONE are not included in the Boundary-Scan register. For more information regarding Boundary Scan, refer to XAPP 017.001, Boundary Scan in
XC4000 Devices.
The other standard data register is the single flip-flop
bypass register. It resynchronizes data being passed
through a device that need not be involved in the current
scan operation. The LCA device provides two user nets
(BSCAN.SEL 1 and BSCAN.SEL2) which are the decodes
of two user instructions. For these instructions, two corresponding nets (BSCAN.TD01 and BSCAN.TD02) allow
2-22
~XIUNX
DATA IN
sd
0
0
0
0
LE
1ClB.0
IClB.T
sd
0
0
0
0
LE
..................................
..............................
sd
0
0
0
0
LE
OK!
o
Q
0
Q
LE
OK!
o
0
0
0
LE
s.
OK!
o 0
0 01------,
LE
sd
DaD
Q
LE
DATAOUT
UPDATE
SHIFT!
CLOCK DATA
CAPTIJRE'
REGISTER
EXTEST
XI523
Figure 16. XC40DO Boundary Scan Logic. Includes three bits of Data Register per lOB, the IEEE 1149.1 Test Access Port
controller, and the Instruction Register with decodes.
2-23
I
XC4000, XC4000A, XC4000H Logic Cell Array Families
Interconnects
The XC4000 families use a hierarchy of interconnect
resources.
~
?
• General purpose single-length and double-length
lines offer fast routing between adjacent blocks, and
highest flexibility for complex routes, but they incur a
delay every time they pass through a switch matrix.
SECONOARY
/1-
• Longlines run the width or height of the chip with
negligible delay variations. They are used for signal
distribution over long distances. Some Horizontal
Longlines can be driven by 3-state or open-drain
drivers, and can thus implement bidirectional buses
or wired-AND decoding.
:'r-
• Global Nets are optimized for the distribution of clock
and time-critical or high-fan-out control signal. Four
pad-driven Primary Global Nets offer shortest delay
and negligible skew. Four pad-driven Secondary
Global Nets have slightly longer delay and more
skew due to heavier loading.
GLOBAL NETS
""OMARY
GlOBAL NETS
0
0
Xl027
Figure 17. XC4000 Global Net Distribution. Four Lines per
Column; Eight Inputs in the Four Chip Corners.
Each CLB column has four dedicated Vertical Longlines,
each of these lines has access to a particular Primary
Global Net, or to anyone of the Secondary Global Nets.
The Global Nets avoid clock skew and potential hold-time
problems. The user must specify these Global Nets for all
timing-sensitive global signal distribution.
+5V
+5V
X1006
Open Drain Buffers Implement a Wired-AND Function. When all the buffer
inputs are High the pull-up resistor(s) provide the High output.
Xl007
3-State Buffers Implement a Multiplexer. The selection is accomplished by the buffer 3-state signal.
Active High T is Identical to
Active Low Output Enable.
Figure 18. TBUFs Driving Horizontal Longlines.
2-24
Oscillator
An internal oscillator is used for clocking of the power-on
time-out, configuration memory clearing, and as the source
of CCLK in Master modes. This oscillator signal runs at a
nominal 8 MHz and varies with process, V cc and
temperature. This signal is available on an output control
net (OSCO) in the upper right corner of the chip, if the
oscillator-run control bit is enabled in the configuration
memory. Two of four resynchronized taps of the power-on
time-out divider are also available on OSC1 and OSC2.
These taps are at the fourth, ninth, fourteenth and nineteenth bits of the ripple divider. This can provide output
signals of approximately 500 kHz, 16 kHz, 490 Hz and
15 Hz.
Configuration
Configuration is the process of loading design-specific
programming data into one or more LCA devices to define
the functional operation of the internal blocks and their
interconnections. This is somewhat like loading the command registers of a programmable peripheral chip. The
XC4000 families use about 350 bits of configuration data
per CLB and its associated interconnects. Each configuration bit defines the state of a static memory cell that
controls either a function look-up table bit, a multiplexer
input, or an interconnect pass transistor. The XACT development system translates the design into a nellist file. It
automatically partitions, places and routes the logic and
generates the configuration data in PROM format.
Special Purpose Pins
The mode pins are sampled prior to configuration to
determine the configuration mode and timing options. After
configuration, these pins can be used as auxiliary connections: Mode 0 (MDO.l) and Mode 2 (MD2.1) as inputs and
Mode 1 (MD1.0 and MD1.T) as an output. The XACT
development system will not use these resources unless
they are explicitly specified in the deSign entry. These
dedicated nets are located in the lower left chip corner and
are near the readback nets. This allows convenient routing
if compatibility with the XC2000 and XC3000 family conventions of MO/RT, M1/RD is desired.
Modes
The XC4000 families have six configuration modes selected by a 3- bit input code applied to the MO, M1, and M2
inputs. There are three self-loading Master modes, two
Peripheral modes and the Serial Slave mode used primarily for daisy-chained devices. During configuration, some
of the I/O pins are used temporarily for the configuration
process. See Table 6.
For a detailed description of these configuration modes,
see pages 2-32 through 2-41.
Master
The Master modes use an internal oscillator to generate
CCLK for driving potential slave devices, and to generate
address and timing for external PROM(s) containing the
configuration data. Master Parallel (up or down) modes
generate the CCLK signal and PROM addresses and
receive byte parallel data, which is internally serialized into
the LCA data-frame format. The up and down selection
generates starting addresses at either zero or 3FFFF,to
be compatible with different microprocessor addressing
conventions. The Master Serial mode generates CCLK
and receives the configuration data in serial form from a
Xilinx serial-configuration PROM.
Peripheral
Table 6. Configuration Modes
The two Peripheral modes accept byte-wide data from a
bus. A READY/BUSY status is available as a handshake
signal. In the asynchronous mode, the internal oscillator
generates a CCLK burst signal that serializes the bytewide data. In the synchronous mode, an externally supplied clock input to CCLK serializes the data.
Serial Slave
~
In the Serial Slave mode, the LCA device receives serialconfiguration data on the rising edge of CCLK and,after
loading its configuration, passes adpitional data out,
resynchronized on the next falling edge of CCLK. Multiple
slave devices with identical configurations can be wired
with parallel DIN inputs so that the devices can be configured simultaneously.
}
2-25
II
XC4000, XC4000A, XC4000H Logic Cell Array Families
::J
-- "'~
ru.~
om ."'~.
PREAMBLE
CODE
11111111
0010
< 24·BIT LENGTH COUNT>
1111
HEADER
-CONFIGURATION PROGRAM LENGTH (MSB FIRST)
- DUMMY BITS (4 BITS MINIMUM)
o < DATA FRAME # 001 > eeee
o < DATA FRAME # 002 > eeee
o < DATA FRAME # 003 > eeee
PROGRAM DATA
(EACH FRAME CONSISTS OF:
A START BIT (0)
A DATA FIELD
FOUR ERROR CHECK BITS (eeee)
J
o < DATA FRAME # N·1 > eeee
o < DATA FRAME # N > eeee
01111111
REPEATED FOR EACH LOGIC
CELL ARRAY IN A DAISY CHAIN
POSTAMBLE CODE
X1526
Device
XC4002A
XC4003A
Gates
2,000
3,000
3,000
4,000
5000
5,000
CLBs
(Row x Col)
64
(8 x 8)
100
(10x 10)
100
(10 x 10)
144
(12 x 12)
196
(14 x 14)
196
(14x 14)
XC4003H XC4004A XC4005A XC4005/5H XC4006
6,000
XC4008
XC4010
XC4013
8,000
10,000
13,000
256
400
324
576
(16 x 16) (18 x 18) (20 x 20) (24 x 24)
lOBs
64
80
80/.160
96
112
112 (192)
128
144
160
192
Flip·flops
256
360
360/300
480
616
616 (392)
768
936
1120
1536
Horizontal
TBUF Longlines
16
20
20
24
28
28
32
36
40
48
TBUFslLongline
10
12
12
14
16
16
18
20
22
26
Bits per Frame
102
122
126
142
162
166
186
206
226
266
Frames
310
374
428
435
502
572
644
716
788
932
Program Data
31,628
45,636
53,936
62,204
81,332
94,960
119,792
147,504
178,096
247,920
PROM size (bits)
31,668
45,676
53,976
62,244
81,372
95,000
119,832
147,544
178,136
247,960
XC4000, 4000H: Bits per Frame =(10 x number of Rows) + 7 for the top + 13 for the bottom + 1 + 1 start bit + 4 error check bits
Number of Frames =(36 x number of Columns) + 26 for the left edge + 41 for the right edge + 1
XC4000A:
Bits per Frame =(10 x number of Rows) + 6 for the top + 10 for the bottom + 1 + 1 start bit + 4 error check bits
Number of Frames = (32 x number of Columns) + 21 for the left edge + 32 for the right edge + 1
Program Data = (Bits per Frame x Number of Frames) + 8 postamble bits
PROM Size = Program Data + 40
The user can add more "one" bits as leading dummy bits in the header, or, if CRG =off, as trailing dummy bits at the end of
any frame, following the four error check bits, but the Length Count value must be adjusted for all such extra "one" bits,
even for leading extra ones at the beginning of the header.
Figure 25. Internal Configuration Data Structure.
Format
The configuration-data stream begins with a string of ones,
a 0010 preamble code, a 24-bit length count, and a fourbit separator field of ones. This is followed by the actual
configuration data in frames, each starting with a zero bit
and ending with a four-bit error check. For each XC4XXX
device, the MakeBits software allows a selection of CRC
or non-CRG error checking. The non-CRG error checking
tests for a 0110 end of frame field for each frame of a
selected LCA device. For CRC error checking, MakeBits
software calculates a running CRC of inserts a unique
four-bit partial check at the end of each frame. The 11-bit
CRC check of the last frame of an LCA device includes the
last seven data bits. Detection of an error results in
suspension of data loading and the pulling down of the INIT
pin. In master modes, CCLK and address signals continue
to operate externally. The user must detect TNIT and
initialize a new configuration by pulsing the PROGRAM pin
or cycling Vcc. The length and number of frames depend
on the device type. Multiple LCA devices can be connected in a daisy chain by wiring their CCLK pins in parallel
and connecting the DOUT of each to the DIN of the next.
The lead-master LCA device and following slaves each
passes resynchronized configuration data coming from a
single source. The Header data, including the length
count, is passed through and is captured by each LCA
2-26
device when it recognizes the 0010 preamble. Following
the length-count data, any LCA device outputs a High on
DOUT until it has received its required number of data
frames.
Power Applied
After an LCA device has received its configuration data, it
passes on any additional frame start bits and configuration
data on DOUT. When the total number of configuration
clocks applied after memory initialization equals the value
of the 24-bit length count, the LCA device(s) begin the
start-up sequence and become operational together.
Configuration Sequence
Configuration Memory Clear
When power is first applied or reapplied to an LCA device,
an internal circuit forces initialization of the configuration
logic. When V c reaches an operational level, and the
circuit passes {Be write and read test of a sample pair of
configuration bits, a nominal 22-ms time delay is started
(four times longer when MO is Low, Le., in Master mode).
During this time delay, or as long as the PROGRAM input
is asserted, the configuration logic is held in a Configuration Memory Clear state. The configuration-memory frames
are consecutively initialized, using the internal oscillator.
At the end of each complete pass through the frame
addressing, the power-on time-out delay circuitry and the
level of the PROGRAM pin are tested. If neither is asserted, the logic initiates one additional clearing of the
configuration frames and then tests the INIT input.
Master CCLK Goes Active
Initialization
During initialization and configuration, user pins HOC,
LDC and INIT provide status outputs for system interface.
The outputs, LDC, INIT and DONE are held Low and HOC
is held High starting at the initial application of power. The
open drain INIT pin is released after the final initialization
pass through the frame addresses. There is a deliberate
delay of 40 to 160 f.1S before a Master-mode device
recognizes an inactive INIT. Two internal clocks after the
INIT pin is recognized as High, the LCA device samples
the three mode lines to determine the configuration mode.
The appropriate interface lines become active and the
configuration preamble and data can be loaded.
BOUNDARY SCAN
INSTRUCTIONS
AVAILABLE:
SAMPLE/PRELOAD
BYPASS
Configuration
EXTEST
SAMPLE PRELOAD
BYPASS
USER 1
USER 2
CONFIGURE
READBACK
The 0010 preamble code indicates that the following
24 bits represent the length count, Le., the total number of
configuration clocks needed to load the total configuration
data. After the preamble and the length count have been
passed through to all devices in the daisy chain, DOUT is
held High to prevent frame start bits from reaching any
daisy-chained devices. A specific configuration bit, early in
the first frame of a master device, controls the configuration-clock rate and can increase it by a factor of eight. Each
frame has a Low start bit followed by the frame-configura-
)(3211
Figure 9. Start-up Sequence
2-27
II
XC4000, XC4000A, XC4000H Logic Cell Array Families
tion data bits and a 4-bit frame error field. If a frame data
error is detected, the LCA device halts loading, and signals
the error by pulling the open-drain INIT pin Low.
The XC4000 family introduces an additional option: When
this option is enabled, the user can externally hold the
open-drain DONE output Low, and thus stall all further
progress in the Start-up sequence, until DONE is released
and has gone High. This option can be used to force
synchronization of several LCA devices to a common user
clock, or to guarantee that all devices are successfully
configured before any II0s go active.
After all configuration frames have been loaded into an
LCA device, DOUT again follows the input data so that the
remaining data is passed on to the next device.
Start-Up
Start-up Sequence
The Start-up sequence begins when the configuration
memory is full, and the total number of configuration clocks
received since INIT went High equals the loaded value of
the length count. The next rising clock edge sets a flip-flop
ao ( see Figure 28 ), the leading bit of a 5-bit shift register.
Start-up is the transition from the configuration process to
the intended user operation. This means a change from
one clock source to another, and a change from interfacing
parallel or serial configuration data where most outputs are
3-stated, to normal operation with 1/0 pins active in the
user-system. Start-up must make sure that the user-logic
''wakes up" gracefully, that the outputs become active
without causing contention with the configuration signals,
and that the internal flip-flops are released from the global
Reset or Set at the right time.
The outputs of this register can be programmed to control
three events.
• The release of the open-drain DONE output,
• The change of configuration-related pins to the
Figure 27 describes Start-up timing for the three Xilinx
families in detail.
user function, activating all lOBs.
• The termination of the global Set/Reset initialization
The XC2000 family goes through a fixed sequence:
of all CLB and lOB storage elements.
DONE goes High and the internal global Reset is deactivated one CCLK period after the 1/0 become active.
The DONE pin can also be wire-ANDed with DONE pins of
other LCA devices or with other external Signals, and can
then be used as input to bit a3 of the start-up register. This
is called "Start-up Timing Synchronous to Done In" and
labeled: CCLK_SYNC or UCLK_SYNC. When DONE is
not used as an input, the operation is called Start-up
Timing Not Synchronous to DONE In, and is labeled
CCLK_NOSYNC or UCLK_NOSYNC. These labels are
not intuitively obvious.
The XC3000 family offers some flexibility: DONE can be
programmed to go High one CCLK period before or after
the 1/0 become active. Independent of DONE, the internal
global Reset is de-activated one CCLK period before or
after the 1/0 become active.
The XC4000 family offers additional flexibility: The three
events, DONE going High, the internal Reset/Set being
de-activated, and the user 1/0 going active, can all occur
in any arbitrary sequence, each of them one CCLK period
before or after, or simultaneous with, any of the other.
As a configuration option, the start-up control register
beyond ao can be clocked either by subsequent CCLK
pulses or from an on-Chip user net called STARTUP .CLK.
Start-up from CCLK
The default option, and the most practical one, is for DONE
to go High first, disconnecting the configuration data
source and avoiding any contention when the II0s become
active one clock later. Reset/Set is then released another
clock period later to make sure that user-operation starts
from stable internal conditions. This is the most common
sequence, shown with heavy lines in Figure 27, but the
designer can modify it to meet particular requirements.
If CCLK is used to drive the start-up, ao through a3
provide the timing. Heavy lines in Figure 27 show the
defaulttiming which is compatible with XC2000 and XC3000
devices using early DONE and late Reset.The thin lines
indicate all other possible timing options.
Start-up from a User Clock (STARTUP.CLK)
When, instead of CCLK, a user-supplied start-up clock is
selected, a1 is used to bridge the unknown phase relationship between CCLK and the user clock. This arbitration
causes an unavoidable one-cycle uncertainty in the timing
of the rest of the start-up sequence.
The XC4000 family offers another start-up clocking option:
The three events described above don't have to be triggered by CCLK, they can, as a configuration option, be
triggered by a user clock. This means that the device can
wake up in synchronism with the user system.
2-28
needed
I
Figure 27. Start-up Timing
2-29
XC4000, XC4000A, XC4000H Logic Cell Array Families
01fQ4
DONE
IN
STARTUP Q3
Q2
*
lOBs OPERATIONAL PER CONFIGURATION
*
GLOBAL SETIRESET OF
ALL CLB AND lOB FLlp·FLOPS
CONTROLLED BY STARTUP SYMBOL
IN THE USER SCHEMATIC (SEE
LIBRARIES GUIDE)
} - - . - - - - - . . , . - - - - ,GLOBAL 3-STATE OF ALL lOBs
*
, FINISHED'
ENABLES BOUNDARY
SCAN, READBACK AND
CONTROLS THE OSCILLATOR
01
QO
FULL
LENGTH COUNT
S
OI_.....+--1D
K
K
0
02
D
Q4
03
o
0
K
K
*
CLEAR MEMORY ---__JI_-~--__J-t-~~-__J--4-----~-~-__JI_-.....---~
CCLK
STA~~~~.~~ _ _ _ _ _ _-1
*
* CONFIGURATION BIT OPTIONS SELECTED BY USER IN 'MAKEBrrS '
Xl528
Figure 28, Start-up Logic
2-30
~XILINX
11-bit Cyclic Redundancy Check (CRC) signature follow,
before RIP returns Low.
Using Global SeUReset arid Global 3-State Nets
The global Set/Reset (STARTUP.GSR) net can be driven
by the user at any time to re-initialize all CLBs and lOBs to
the same state they had at the end of configuration. For
CLBs that is the same state as the one driven by the
individually programmable asynchronous Set/Reset inputs. The global3-state net (STARTUP.GTS), whenever
activated after configuration is completed, forces all LCA
outputs to the high-impedance state, unless Boundary
Scan is enabled and is executing an EXTEST instruction.
Readback options are: Read Capture, Read Abort, and
Clock Select.
Read Capture
When the Readback Capture option is selected, the
readback data stream includes sampled values of CLB
and lOB signals imbedded in the data stream. The rising
edge of RDBK.TRIG located in the lower-left chip corner,
captures, in latches, the inverted values of the four CLB
outputs and the lOB output flip-flops and the input signals
11 , 12 . When the capture option is not selected, the values
of the capture bits reflect the configuration data originally
written to those memory locations. If the RAM capability of
the CLBs is used, RAM data are available in readback,
since they directly overwrite the F and G function-table
configuration of the CLB.
Readback
The user can read back the content of configuration
memory and the level of certain internal nodes without
interfering with the normal operation of the device.
Readback reports not only the downloaded configuration
bits, but can also include the present state of the device
represented by the content of all used flip-flops and latches
in CLBs and lOBs, as well as the content of function
generators used as RAMs.
Read Abort
When the Readback Abort option is selected, a High-toLow transition on RDBK.TRIG terminates the read back
operation and prepares the logic to accept another trigger.
After .an aborted readback, additional clocks (up-to-one
readback clock per configuration frame) may be required
to re-initialize the control logic. The status of read back is
indicated by the output control net (RDBK.RIP).
XC4000 Readback does not use any dedicated pins, but
uses four internal nets (RDBK.TRIG, RDBK.DATA,
RDBK.RIP and RDBK.CLK) that can be routed to any lOB.
After Readback has been initiated by a Low-to-High transition on RDBK.TRIG, the RDBK.RIP (Read In Progress)
output goes High on the next rising edge of RDBK.CLK.
Subsequent rising edges of this clock shift out Readback
data on the RDBK.DATA net. Readback data does not
include the preamble, but starts with five dummy bits (all
High) followed by the Start bit (Low) of the first frame. The
first two data bits of the first frame are always High.
Clock Select
Readback control and data are clocked on rising edges of
RDBK.CLK located in the lower right chip corner. CCLK is
an optional clock. If Readback must be inhibited for security reasons, the read back control nets are simply not
.
connected.
XChecker
Note that, in the XC4000 families, data is not inverted with
respect to configuration the way it is in XC2000 and
XC3000 families.
The XChecker Universal DownloadlReadback Cable and
Logic Probe uses the Readback feature for bitstream
verification and for display of selected internal signals on
the PC or workstation screen, effectively as a low-cost incircuit emulator.
Each frame ends with four error check bits. They are read
back as High. The last seven bits of the last frame are also
read back as High. An additional Start bit (Low) and an
2-31
I
XC4000, XC4000A, XC4000H Logic Cell Array Families
Master Serial Mode
L
~
MO Ml
M2
TO DIN OF OPTIONAL
DAISY CHAINED
LCA DEVICES WITH DIFFERE NT
CONFIGURATIONS
DOUT
-
-
GENERAL
PURPOSE
USERVO
PINS
,.. TO CCLI< OF OPTIONAL
DAISY-CHAINED
LCA DEVICES WITH DIFFERE NT
CONFIGURATIONS
HDC
--< LOC
--< INIT
-
··• lonER
-
f----- TO CCLK OF OPTIONAL
SLAVE LCA DEVICES WITH IDENTICAL
CONFIGURATIONS
VOPINS
~
XC4000
TO DIN OF OPTIONAL
SLAVE LCA DEVICES WITH IDENTICAL
CONFIGURATIONS
+5V
->-(
r---,
PROGRAM
DIN
CCLK
DONE
Vpp
Vee
DATA SERIAL
CLK MEMORY
CE
10E/RESET
XC17xx
CEO
r----------------~-,
i
I
i
--i DATA
CLK CASCADED I
~J
SERIAL !
CE
MEMORY i
:
OEIRESET
I
:L.__________________ :
..1
(A LOW LEVEL RESETS THE XC17xx ADDRESS POINTER)
><3021
means that DOUT changes on the falling CCLK edge, and
the next LCA device in the daisy-chain accepts data on the
subsequent rising CCLK edge.
In Master Serial mode, the CCLK output of the lead LCA
device drives a Xilinx Serial PROM that feeds the LCA DIN
input. Each rising edge of the CCLK output increments the
Serial PROM internal address counter. This puts the next
data biton the SPROM data output, connected to the LCA
DIN pin. The lead LCA device accepts this.data on the
subsequent rising CCLK edge.
The SPROM CE input can be driven from either LDC or
DONE. Using LDC avoids potential contention on the DIN
pin, if this pin is configured as user-I/O, but LDC is then
restricted to be a permanently High user output. Using
DONE can also avoid contention on DIN, provided the
early DONE option is invoked.
The lead LCA device then presents the preamble data
(and all data that overflows the lead device) on its DOUT
pin. There is an internal delay of 1.5 CCLK periods, which
2-32
Master Serial Mode Programming Switching Characteristics
CCLK
(Output)
Serial Data In
Serial DOUT
n_3
(Output) _ _ _ _ _ _ _-'
n-2
n
n-l
X3223
Description
CCLK
Data In setup
Data In hold
Symbol
TDSCK
TCKDS
1
2
Min
60
0
Max
Units
ns
ns
Notes: 1. At power-up, Vcc must rise from 2.0 V to Vcc min in less than 25 ms, otherwise delay configuration using INIT until
Vee is valid.
_
_
2. Configuration can be controlled by holding INIT Low with or until after the INIT of all daisy-chain slave mode devices
is High.
3. Master-serial-mode timing is based on testing in slave mode.
2-33
II
XC4000, XC4000A, XC4000H Logic Cell Array Families
Slave Serial Mode
-
+5V
I I
.
MO
I
M2
M1
MICRO
COMPUTER
o
DOUT
DIN
02 03 -
01
D4
_ T CCLK OF OPTIONAL
0 AISY-CHAINED.LCA DEVICES WITH
01 FFERENT CONFIGURATIONS
CCLK
DO
VO
TO CCLK OF OPTIONAL
SLAVE LCA DEVICES WITH
IDENTICAL CONFIGURATION
o
-STRB
PORT·
TO DIN OF OPTIONAL
SLAVE LCA DEVICES WITH
IDENTICAL CONFIGURATION
+5V
T CCLK OF OPTIONAL
0 AISY·CHAINED LCA DEVICES WITH
01 FFERENT CONFIGURATIONS
HOC
-
LOC
I>---
XC4000
-
··
·
r----
05
INIT
06
DONE
07
PROGRAM
OTHER {
VOPINS
r--
'---
- - < RESET
X3020
In Slave Serial mode, an external signal drives the CCLK
input(s) of the LCA device(s). The serial configuration
bitstream must be available at the DIN input of the lead··
LCA device a short set-up time before each rising CCLK
edge. The lead LCA device then presents the preamble
data (and all data that overflows the lead device) on its
DOUTpin.
There is an internal delay of 1.5 CCLK periods, which
means that DOUT changes on the falling CCLK edge, and
the next LCA device in the daisy-chain accepts data on the
subsequent rising, CCLK edge.
2-34.
Slave Serial Mode Programming Switching Characteristics
DIN
CCLK
DOUT
(OUTPUT)
I
BITN
B_IT_N_+1_ _ _ _ _ _ _ _ _ _ _ _ __
~I~T= ~'.
' T= ~I'
~.
®-T=
}--
~i----i0-TcCH -----l~L-(i)-T= 71.---------~
BITN-2
Description
CCLK
'i'c..-____
DIN setup
DIN hold
to DOUT
High time
Low time
Frequency
Symbol
1
2
3
4
5
TDCC
TCCD
Tcco
TCCH
TCCL
Fcc
Min
Max
20
0
30
50
60
Note: Configuration must be delayed until the INIT of all daisy-chained LCA devices is High.
2-35
BITN-1
8
Units
ns
ns
ns
ns
ns
MHz
II
XC4000, XC4000A, XC4000H Logic Cell Array Families
Master Parallel Mode
,--_ _ _ _ _ _ _ _ _ _ _..... TO DIN OF OPTIONAL
DAISY-CHAINED
HIGH
LCA DEVICES WITH
or
DIFFERENT
CONFIGURATIONS
LOW +5V
~
MO
-
I
Ml
I
M2
CCLK
DOUT
A17
-_.....
HDC
A16
---< LDC
A15
-
---< RCLK
A14
-
---< INIT
A13
-
...
-
A12
-
...
All
-
...
GENERAL
PURPOSE
USER 1/0
PINS
f-----
} OTHER
I/O PINS
-
USER CONTROL OF HIGHER
ORDER PROM ADDRESS BITS
CAN BE USED TO SELECT FROM
ALTERNATIVE CONFIGURATIONS
...
...
EPROM
(2Kx 8)t
(OR LARGER)
Al0
Al0
A9
A9
A8
A8
A7
A7
D7 ~
D5
A6
A6
D6 ~
D4
A5
AS
DS ~
D3
A4
A4
D4 ~
D2
A3
A3
D3 ~
Dl
A2
A2
D2 ~
DO
Al
Al
Dl
j'.,
AO
AO
DO
~
-----< PROGRAM
r
r
r
r
r
r
r
r
TO CCLK OF OPTIONAL
DAISY-CHAINED
LCA DEVICES WITH
DIFFERENT CONFIGURATIONS
D7
D6
XC4000
DONE
L
OE
CE
8
X3019
DATA BUS
In Master Parallel mode, the lead LCA device directly
addresses an industry-standard byte-wide EPROM, and
accepts eight data bits right before incrementing (or
decrementing) the address outputs.
internal delay of 1.5 CCLK periods, after the rising CCLK
edge that accepts a byte of data (and also changes the
EPROM address) until the falling CCLK edge that makes
the LSB (DO) of this byte appear at DOUT. This means that
DOUT changes on the falling CCLK edge, and the next
LCA device in the daisy-chain accepts data on the subsequent rising CCLK edge.
The eight data bits are serialized in the lead LCA device,
which then presents the preamble data ( and all data that
overflows the lead device) on the DOUT pin. There is an
2-36
Master Parallel Mode Programming Switching Characteristics
Ao-A15
(OUTPUT)
ADDRESS for BYTE n + 1
ADDRESS for BYTE n
DO-D7
RCLK
(OUTPUT)
-~._-®
1---
/
TRCO
u- - - - - - - '
CCLK
(OUTPUT)
II
DOUT
(OUTPUT)
BYTE n-1
110530
Description
RCLK
Delay to Address valid
Data setup time
Data setup time
Symbol
1
TRAC
2
T DRC
3
TRCD
Min
Max
0
60
0
200
Units
ns
ns
ns
Notes: 1. At power-up, Vcc must rise from 2.0 V to Vcc min in less than 25 ms, otherwise delay configuration using INIT until
Vcc is valid.
2. Configuration can be delayed by holding IN IT Low with or until after the INIT of all daisy-chain slave mode devices
is High.
3. The first Data byte is loaded and CCLK starts at the end of the first RCLK active cycle (rising edge).
This timing diagram shows that the EPROM requirements are extremely relaxed: EPROM access time can be longer than
500 ns. EPROM data output has no hold-time requirements.
2-37
XC4000, XC4000A, XC4000H Logic Cell Array Families
Synchronous Peripheral Mode
MO Ml
+5V
Data Bus - - - - - - - \
M2
DO·7
DOUT
XC4000
+5V
HDC
General·
LDC
Purpose
User 1/0
Pins
5k
Other {
Control
Signals
Optional
Daisy·Chained
LCA Devices with
Different
...... Configurations
CCLK
CCL~OPins
lJ --11--_--\ ROYIBUSY
··
INIT
Reprogmm -----qPROGRAM
X3224
The lead LCA device serializes the data and presents the
preamble data ( and all data that overflows the lead device)
on its DOUT pin. There is an internal delay of 1.5 CCLK
periods, which means that DOUT changes on the falling
CCLK edge, and the next LCA device in the daisy-chain
accepts data on the subsequent rising CCLK edge. In
order to complete the serial shift operation, 10 additional
CCLK rising edges are required after the last data byte has
been loaded, plus one more CCLK cycle for each daisychained device.
Synchronous Peripheral mode can also be considered
Slave Parallel mode. An external signal drives the CCLK
input(s) of the LCA device(s). The first byte of parallel
configuration data must be available atthe D inputs ofthe
lead LCA device a short set-up time before each rising
CCLK edge. Subsequent data bytes are clocked in on
every eighth consecutive rising CCLK edge. The same
CCLK edge that accepts data, also causes the RDYIBUSY
output to go High for one CCLK period. The pin name is a
misnomer. In Synchronous Peripheral mode it is really an
ACKNOWLEDGE signal. Synchronous operation does
not require this response, but it is a meaningful signal for
test purposes.
2-38
-----------------
Synchronous Peripheral Mode Programming Switching Characteristics
CCLK
~~
I~
J r-0 TCD
!
®TDC-1~1
1
-y-
~
L!:....J
!
________+-__~------~.~~O~~~l~T
l~
DOUT
RDY/BUSY
X1524
-------1v---l\.'
,
''----_ _ _ _ _ _ _ _
Description
CCLK
Symbol
Min
Max
Units
5
j.tS
T DC
60
ns
TCD
0
ns
ns
INIT (High) Setup time required
1
TIC
DIN Setup time required
2
DIN Hold time required
3
CCLK High time
TCCH
50
CCLK Low time
TCCL
60
CCLK Frequency
Notes:
~i.',',!,~
t
\
Fcc
ns
8
MHz
Peripheral Synchronous mode can be considered Slave Parallel mode. An extemal CClK provides timing, clocking in
the first data byte on the second rising edge of CClK after INIT goes High. Subsequent data bytes are clocked in on
every eighth consecutive rising edge of CClK.
The ROY/BUSY line goes High for one CClK period after data has been clocked in, although synchronous operation
does not require such a response.
The pin name ROY/BUSY is a misnomer; in Synchronous Peripheral mode this is really an ACKNOWLEDGE Signal.
Note that data starts to shift out serially on the DOUT pin 0.5 ClK periods after it was loaded in parallel. This obviously
requires additional CClK pulses after the last byte has been loaded.
2-39
II
XC4000, XC4000A, XC4000H Logic Cell Array Families
Asynchronous Peripheral Mode
+5V
MO
8
DATA
BUS
fl
Ml M2
CCLK
DO-7
/
-
+5V
ADDRESS
BUS
DOUT I - ADDRESS
DECODE
LOGIC
CSO
--
OPTIONAL
DAISY-CHAINED
LCA DEVICES WITH
DIFFERENT
CONFIGURATIONS
HDC I - -
-
XC4000
LDC I>-CSl
RS
WS
RDYIBUSY
CONTROL
SIGNALS
O~'R{
GENERALPURPOSE
USER 1/0
PINS
I--
1/0 PINS
-
INIT
DONE
REPROGRAM
PROGRAM
X3017
Asynchronous Peripheral mode uses the trailing edge of
the logic AND condition of the CSO, CS1; CS2, and WS
inputs to accept byte-wide data from a microprocessor
bus. In the lead LCA device, this data is .loaded into a
double-buffered UART-like parallel-to-serial converter and
is serially shifted into the internal logic. The lead LCA
device presents the preamble data (and all data that
overflows the lead device) on the OOUT pin.
again when the byte-wide input buffer has transferred its
information into the shift register, and the buffer is ready to
receive new data. The length of the BUSY signal depends
on the activity in the UART. If the shift register had been
empty when the new byte was received, the BUSY signal
lasts for only two CCLK periods. Ifthe shift register was still
full when the new byte was received, the BUSY signal can
be as long as nine CCLK periods.
The Ready/Busy output from the lead LCA device acts as
a handshake signal to the microprocessor. ROY/BUSY
goes Low when a byte has been received, and goes High
Note that after the last byte has been entered, only seven
of its bits are shifted out. CCLK remains High with OOUT
equal to bit 6 (the next-to-Iast bit) of the last byte entered.
2-40
Asynchronous Peripheral Mode Programming Switching Characteristics
WRITETOLCA
READ STATUS
WSiCSO
WS.CSl
RS.CS1
____
00-07
~!~.----R-E-AO-Y----~r=__
07
BUSY
CCLK
•
--,
I
II
\---l
1+-----0 Teusy
--------~r_----~-.I
ROY/BUSY
OOUT ______-JX~
_________PR_E_VI_O_US_B_Y_TE_~
________
Description
Write
ROY
Notes:
_JX
07
Symbol
x
00
Min
X
01
E
Max
X1032
Units
Effective Write time required
(CSO, WS = Low, RS, CS1 = High)
1
TCA
100
ns
DIN Setup time required
DIN Hold time required
2
3
Toc
Tco
60
0
ns
ns
ROY/BUSY delay after end of WS
4
TWTRB
Earliest next WS after end of BUSY
5
TRBWT
0
BUSY Low output (Note 4)
6
T BUSY
2
60
ns
ns
9
CCLK
Periods
1. Configuration must be delayed until the INIT of all LCA devices is High.
2. Time from end of WS to CCLK cycle for the new byte of data depends on completion of previous byte processing and
the phase of the internal timing generator for CCLK.
3. CCLK and DOUT timing is tested in slave mode.
4. TBUSY indicates that the double-buffered parallel-to-serial converter is not yet ready to receive new data.
The shortest Tsusy occurs when a byte is loaded into an empty parallel-to-serial converter. The longest Tsusy occurs
when a new word is loaded into the input register before the second-level buffer has started shifting out data.
This timing diagram shows very relaxed requIrements:
Data need not be held beyond the rIsIng edge of WS. BUSY will go actIve wIthin 60 ns after the end of WS.
WS may be asserted Immediately after the end of BUSY.
2-41
XC4000, XC4000A, XC4000H Logic Cell Array Families
General LCA Switching Characteristics
Vee
Jt--------
TPOR
-----+\
RE-PROGRAM
PROGRAM
........................11+-_ _ _
T PI
----+I
CCLK OUTPUT or INPUT
MO,M1,M2
(Required)
X1532
~I <300ns
I/O
----A-
Master Modes
Symbol
Min
Max
Units
TpOR
10
40
40
130
ms
ms
3
20
TCCLK
40
640
100
250
2000
250
Symbol
Min
Max
Units
Power-Dn-Reset
TpOR
10
33
ms
Program Latency
Tpi
3
20
~s per
CLB column
Power-Dn-Reset
MO= High
MO= Low
TpOR
Program Latency
Tpi
CCLK (output) Delay
period (slow)
period (fast)
T 1CCK
TCCLK
~s per
CLB column
~
ns
ns
Slave and Peripheral Modes
CCLK (input) Delay (required)
period (required)
Note:
T 1CCK
TCCLK
At power-up, Vcc must rise from 2.0 V to Vcc min in less than 25 ms,
otherwise delay configuration using INIT until Vcc is valid.
2-42
4
125
~
ns
~XILINX
Configuration Pin Assignments
CONFIGURATION MODE:
SLAVE
<1:1:1>
MASTER-SER
<0:0:0>
~S
....•.••.•.••••••.•......•.•••.
<
I
SYN.PERIPH
<0:1:1>
.·.i.···.·····. · ·.· · · .· · · .·
. . . . . . . . . . . . . i ...·.·.· ·.· .·
('
I
...
....
TOI
TCK
TMS
MS ...• ·.• •.
SYN.PERIPH
<1:0:1>
....
..••
......
TDI
TCK
TMS
...
MASTER-HIGH
<1:1:0>
A16
A17
TDI
TCK
TMS
•.. . .
........
......
Ml (HIGH) (I)
MO (HIGH) (I)
M2 (HIGH) (I)
<....... .. . . . . . .
HDCJHIGH)
LDC(LOW)
INIT-ERROR
......•.
...
DONE
PROGRAM (I)
Ml (LOW) (I)
MO (LOW) (I)
M2 (LOW) (I)
1 Ml (HIGH) (I)
1 MO (HIGH) (I)
1
M2(LOW)(I)
1 Ml (LOW) (1\
1 MO (HIGH) (I)
1
MASTER-LOW
<1:0:0>
A16
A17
TD.I
•..•...
..
TCK.··
Ml (HIGH) (I)
1 MO (LOW) (I)
M2 (HIGH) (I)
1
M2 (HIGH) (1\
TMS<
.'
...
......
(0)
1 Ml (LOW) (I)
MO (LOW) (I)
M2 (HIGH) III
HOC (HIGH)
LDC(LOW)
IN IT-ERROR
HOC (HIGH)
LDC(LOW)
INIT-ERROR
HOC (HIGH)
LDC(LOW)
INIT-ERROR
HOC (HIGH)
LDC(LOW)
INIT-ERROR
HOC (HIGH)
LDC(LOW)
INIT-ERROR
DONE
PROGRAM- (I)
DONE
PROGRAM (I)
DONE
PROGRAM (I)
DONE
PROGRAM (I)
DATA 7 (I)
DONE
PROGRAM (I)
OATAt/11
DATA 6 (I)
DATAs(l)
DATA 6 (I)
DATAS (I).
OAtA6(i)
oAtJ\SlI)
(1\
III
..
J
DATA6(1)
DAtA5-.l1J
....•
......
I.
_I
DOUT
CCLK(I)
TOO
I
•.
DIN (I)
DOUT
CCLK(O)
TOO
·1
....
DATA 4 (I)
DATA 4 (I)
DATA 2 (I)
DATAl (I)
RDY/BUSY
DATA 0 (I)
DOUT
CCLK(O)
TOO
DATA2(1)
DATAl (I)
RDYIBUSY
DATA 0 (I)
DOUT
CCLK(O)
TOO
WS(I)
1
CSl (I)
I
.......
it............. . . .................
DATA-HI)
DATA 3 (I)
....
1
DATA2(1)
DATAl (I)
RCLK
DATAo(l)
DOUT
CCLK(O)
TOO
AO
Al
A2
A3
A4
A5
A6
At
AS
A9
Al0
All
A12
A13
A14
A15
..
DAtA3(1)
DAtA2(1)<)
DATAl(I).·.....
RCLK
DAtA 0 (I)
DOUT
CCLK(O)
TOO
AD
Al
A2
A3
A4
A5
A6
A7
AS
A9
Al0
All
A12
A13
A14
A15
USER
OPERATION
PGI-I/O
I/O
TDI-IIO
TCK-I/O
TMS-I/O
SGI-IIO
PGI-I/O
I/O
1/0
1/0
SGI-I/O
DONE
PROGRAM
1/0
PGI-IIO
1/0
I/O
110
I/O
1/0
110
110
I/O
1/0
flO
SGI-IIO
CCLK(I)
TDO-(O)
1/0
PGI-I/O
1/0
I/O
1/0
1/0
110
110
1/0
1/0
I/O
110
VO
I/O
110
SGJ-I/O
I.··. ·.·.1 REPRESENTS A 50 kQTO 100 kQ PULL-UP
• INIT IS AN OPEN-DRAIN OUTPUT DURING CONFIGURATION
(I) REPRESENTS AN INPUT
X3024
2-43
II
XC4000, XC4000A, XC4000H Logic Cell Array Families
Pin Descriptions
Permanently Dedicated Pins
User I/O Pins that can have Special Functions
Vcc
Eight or more (depending on package type) connections to
the nominal +5 V supply voltage. All must be connected.
RDY/BUSY
During peripheral modes, this pin indicates when it is
appropriate to write another byte of data into the LCA
device. The same status is also available on 07 in asynchronous peripheral mode, if a read operation is performed when the device is selected. After configuration,
this is a user-programmable I/O pin.
GND
Eight or more (depending on package type) connections to
ground. All must be connected.
RCLK
CCLK
During Master parallel configuration, this output indicates
a read operation of an external dynamic memory device.
This output is normally not used. After configuration, this is
a user-programmable 1/0 pin.
During configuration, Configuration Clock is an output of
the LCA in Master modes or asynchronous Peripheral
mode, but is an input to the LCA in Slave mode and
Synchronous Peripheral mode.
MO, M1, M2
After configuration, CCLK has a weak pull-up resistor and
can be selected as Readback Clock.
As Mode inputs, these pins are sampled before the start of
configuration to determine the configuration mode to be
used.
DONE
After configuration, MO and M2 can be used as inputs, and
M 1 can be used as a 3-state output. These th ree pins have
no associated input or output registers.
This is a bidirectional signal with optional pull-up resistor.
As an output, it indicates the completion of the configuration process. The configuration program determines the
exact timing, the clock source for the Low-to-High transition, and enable of the pull-up resistor.
These pins can be user inputs or outputs only when called
out by special schematic definitions.
As an input, a Low level on DONE can be configured to
delay the global logic initialization or the enabling of
outputs
TDO
If boundary scan is used, this is the Test Data Output.
PROGRAM
If boundary scan is not used, this pin is a 3-state output
without a register, after configuration is completed.
This is an active Low input that forces the LCA to clear its
configuration memory.
This pin can be user output only when called out by special
schematic definitions.
When PROGRAM goes High, the LCA finishes the current
clear cycle and executes another complete clear cycle,
before it goes into a WAIT state and releases INIT.
TDI,TCK, TMS
If boundary scan is used, these pins are Test Data In, Test
Clock, and Test Mode Select inputs respectively coming
directly from the pads, bypassing the lOBs. These pins can
also be used as inputs to the CLB logiC after configuration
is completed.
If the boundary scan option is not selected, all boundary
scan functions are inhibited once configuration is completed, and these pins become user-programmable 1/0.
Note:
The XC4000 families have no Powerdown control input; use the global 3-state net instead.
The XC4000 families have no dedicated Reset input. Any user 1/0 can be configured to drive the global SeVReset net.
2-44
HDC
CSO, CS1, WS, RS
High During Configuration is driven High until configuration is completed. It is available as a control output indicating that configuration is not yet completed. After configuration, this is a user-programmable I/O pin.
These four inputs are used in Peripheral mode. The chip
is selected when CSO is Low and CS1 is High. While the
chip is selected, a Low on Write Strobe (WS) loads the data
present on the DO - D7 inputs into the internal data buffer;
a Low on Read Strobe (RS) changes D7 into a status
output: High if Ready, Low if Busy. WS and RS should be
mutually exclusive, but if both are Low simultaneously, the
Write Strobe overrides. After configuration, these are
user-programmable 1/0 pins.
LDC
Low During Configuration is driven Low until configuration.
It is available as a control output indicating that configuration is not yet completed. After configuration, this is a userprogrammable I/O pin.
AO -A17
During Master Parallel mode, these 18 output pins
address the configuration EPROM. After configuration,
these are user-programmable 1/0 pins.
INIT
Before and during configuration, this is a bidirectional
signal. An external pull-up resistor is recommended.
As an active-Low open-drain output, INIT is held Low
during the power stabilization and internal clearing of the
configuration memory. As an active-Low input, it can be
used to hold the LCA device in the internal WAIT state
before the start of configuration. Master mode devices stay
in a WAIT state an additional 30 to 300 Jls after INIT has
gone High.
DO - D7
During Master Parallel and Peripheral configuration
modes, these eight input pins receive configuration data.
After configuration, they are user-programmable 1/0 pins.
DIN
During configuration, a Low on this output indicates that a
configuration data error has occurred. After configuration,
this is a user-programmable 1/0 pin.
During Slave Serial or Master Serial configuration modes,
this is the serial configuration data input receiving data on
the rising edge of CCLK.
During parallel configuration modes, this is the DO input.
After configuration, DIN is a user-programmable 1/0 pin.
PGCK1 - PGCK4
Four Primary Global Inputs each drive adedicated internal
global net with short delay and minimal skew. If not used
for this purpose, any of these pins is a user-programmable
DOUT
1/0.
During configuration in any mode, this is the serial configuration data output that can drive the DIN of daisy-chained
slave LCA devices. DOUT data changes on the falling
edge of CCLK, one-and-a-half CCLK periods after it was
received at the DIN input. After configuration, DOUT is a
user-programmable 1/0 pin.
SGCK1 - SGCK4
Four Secondary Global Inputs can each drive a dedicated
internal global net, that alternatively can also be driven
from internal logic. If not usedforthis purpose, any ofthese
pins is a user-programmable 1/0 pin.
Unrestricted User-Programmable I/O Pins
VO
A pin that can be configured to be input andlor output after
configuration is completed. Before configuration is completed, these pins have an internal high-value pull-up
resistor that defines the logic level as High.
2-45
II
XC4000, XC4000A, XC4000H Logic Cell Array Families
For a detailed description of the device architecture, see page 2-9.
For a detailed description of the configuration modes and their timing, see pages 2-32 through 2-55.
For detailed lists of package pinouts, see pages 2-56 through 2-62.
For package physical dimensions, see Section 4.
Ordering Information
Example:
D"""'Type
IJ
XC4010-5PG191C
I~T.mpe""'MRa""
Speed Grade
Number of Pins
Package Type
Component Availability
PLAST.
CERAM
XC4005
XC4006
XC400B
XC401 0
XC4013
XC4003A
B = MIL-STD-BS3C Class B
Parentheses indicates future product plans
2-46
METAL
CERAM.
PLAST.
METAL
XC4000
Logic Cell Array Family
Product Description
Features
Description
• Third Generation Field-Programmable Gate Arrays
- Abundant flip-flops
- Flexible function generators
- On-chip ultra-fast RAM
- Dedicated high-speed carry-propagation circuit
- Wide edge decoders
- Hierarchy of interconnect lines
- Internal 3-state bus capability
- Eight global low-skew clock or signal distribution
network
• Flexible Array Architecture
- Programmable logic blocks and I/O blocks
- Programmable interconnects and wide decoders
The XC4000 family of Field-Programmable Gate Arrays
(FPGAs) provides the benefits of custom CMOS VLSI,
while avoiding the initial cost, time delay, and inherent risk
of a conventional masked gate array.
The XC4000 family provides a regular, flexible, programmabie architecture of Configurable Logic Blocks (CLBs),
interconnected by a powerful hierarchy of versatile routing
resources, and surrounded by a perimeter of programmable Input/Output Blocks (lOBs).
XC4000 devices have generous routing resources to accommodate the most complex interconnect patterns. They
are customized by loading configuration data into the internal memory cells. The FPGA can either actively read its
configuration data out of external serial or byte-parallel
PROM (master modes), or the configuration data can be
written into the FPGA (slave and peripheral modes).
• Sub-micron CMOS Process
- High-speed logic and Interconnect
- Low power consumption
The XC4000 family is supported by powerful and sophisticated software, covering every aspect of design: from
schematic entry, to simulation, to automatic block placement and routing of interconnects, and finally the creation
of the configuration bit stream.
• Systems-Oriented Features
- IEEE 1149.1-compatible boundary-scan logic support
- Programmable output slew rate (2 modes)
- Programmable input pull-up or pull-down resistors
- 12-mA sink current per output
- 24-mA sink current per output pair
Since Xilinx FPGAs can be reprogrammed an unlimited
number of times, they can be used in innovative designs
where hardware is changed dynamically, or where hardware must be adapted to different user applications. FPGAs
are ideal for shortening the design and development cycle,
but they also offer a cost-effective solution for production
rates well beyond 1000 systems per month.
• Configured by Loading Binary File
- Unlimited reprogrammability
- Six programming modes
• XACT Development System runs on '386/'486-type PC,
NEC PC, Apollo, Sun-4, and Hewlett-Packard 700
series
- Interfaces to popular design environments like
Viewlogic, Mentor Graphics and OrCAD
- Fully automatic partitioning, placement and routing
- Interactive design editor for design optimization
- 288 macros, 34 hard macros, RAM/ROM compiler
For a detailed description of the device features, architecture, configuration methods and pin descriptions, see
pages 2-9 through 2-45.
Table 1. The XC4000 Family of Field-Programmable Gate Arrays
Device
Appr. Gate Count
CLB Matrix
Number of CLBs
Number of Flip-Flops
Max Decode Inputs (per side)
Max RAM Bits
Number of lOBs
'Planned
XC4005
XC400S
XC4008
XC4010
XC4013
5,000
14 x 14
196
616
42
6,272
112
6,000
16 x 16
256
768
48
8,192
128
8,000
18 x 18
324
936
54
10,368
144
10,000
20 x 20
400
1120
60
12,800
160
13,000
24 x24
576
1536
72
18,432
192
2-47
XC401S* XC4020*
16,000
26 x 26
676
1768
78
21,632
208
20,000
30 x 30
900
2280
90
28,800
240
II
XC4000 Logic Cell Array Family
Absolute Maximum Ratings
Units
Vcc
Supply voltage relative to GND
-0.5 to 7.0
V
VIN
Input voltage with respect to GND
-0.5 to 7
V
VTS
Voltage applied to 3-state output
-0.5 to 7
V
TSTG
Storage temperature (ambient)
-65 to + 150
°C
TSOL
Maximum soldering temperature (10 s @ 1/16 in.
+260
°C
TJ
Junction temperature
+ 150
°C
Note:
=1.5 mm)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those listed under Recommended Operating Conditions is not implied. Exposure to Absolute Maximum Ratings
conditions for extended periods of time may affect device reliability.
Operating Conditions
Vcc
Supply voltage relative to GND
Commercial
Supply voltage relative to GND
Industrial
Supply voltage relative to GND
Military
Min
Max
4.75
5.25V
-40°C to 85°C
4.5
5.5 V
-55°C to 125°C
4.5
5.5 V
O°C to 70°C
VIH
High-level input voltage (XC4000 has TTL-like input thresholds)
2.0
VIL
Low-level input voltage (XC4000 has TTL-like input thresholds)
0
TIN
Input signal transition time
Units
VccV
0.8
V
250ns
DC Characteristics Over Operating Conditions
Min
=-4.0 mA, Vcc min
Max
Units
VOH
High-level output voltage @ IOH
VOL
Low-level output voltage @ IOL
Icco
Quiescent LCA supply current (Note 2)
IlL
Leakage current
CIN
Input capacitance (sample tested)
IRIN
Pad pull-up (when selected) @ VIN = OV (sample tested)
0.02
0.25
mA
IRLL
Horizontal Long Line pull-up (when selected) @ logic Low
0.2
2.5
mA
2.4
=12.0 mA, Vcc max (Note 1)
V
0.4
-10
V
10
mA
+10
~
15
pF
Note: 1. With 50% of the outputs simultaneously sinking 12 mAo
2. With no output current loads, no active input or longline pull-up resistors, all package pins at Vcc or GND, and
the LCA configured with a MakeBits tie option.
2-48
Wide Decoder Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-3851 0/605. All devices are 100%
functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing
pattems. The following guidelines reflect worst-case values over the recommended operating conditions. For more detailed, more
precise, and more up-to-date timing information, use the values provided by the XACT timing calculator and used in the simulator.
Speed Grade
Description
Symbol
Full length, both pull-ups,
inputs from lOB I-pins
TWAF
Full length, both pull-ups
inputs from internal logic
Half length, one pull-up
inputs from lOB I-pins
Half length, one pull-up
inputs from internal logic
TWAFL
-6
-5
-4
Device
Max
Max
Max
XC4005
XC4006
XC400S
XC4010
XC4013
10.0
11.0
12.0
13.0
15.0
9.0
10.0
11.0
12.0
14.0
6.0
7.0
S.O
XC400S
XC4006
XC400S
XC4010
XC4013
13.0
14.0
1S.0
16.0
1S.0
12.0
13.0
14.0
1S.0
17.0
XC400S
XC4006
XC400S
XC4010
XC4013
10.0
11.0
12.0
13.0
1S.0
9.0
10.0
11.0
12.0
14.0
I
,~~!:
ns
ns
ns
ns
ns
XC400S
XC4006
XC400S
XC4010
XC4013
13.0
14.0
15.0
16.0
18.0
12.0
13.0
14.0
15.0
17.0
9.0
10.0
11.0
12.0
14.0
ns
ns
ns
ns
ns
.~.:2
i'lXt
!I:::;;
·"""S;p",
~B::~ll
I,J\,Q';
l!3:g~
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
·:;:m jt~::;:;:;
T WAO
T WAOL
.':\:.:.;~:~;:~::::.:.
Note: These delays are specified from the decoder input to the decoder output. For pin-to-pin delays, add the input delay (TPID)
and output delay (TOPF or Tops)' as listed on page 2-52.
2-49
II
XC4000 Logic Cell Array Family
Global Buffer Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-3851 0/605. All devices are 100%
functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing
patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more detailed, more
precise, and more up-to-date timing information, use the values provided by the XACT timing calculator and used in the simulator.
Speed Grade
Description
Global Signal Distribution
From pad through primary buffer, to any clock K
From pad through secondary buffer, to any clock K
-6
-
-5
-4
Symbol
Device
Max
Max
Max
TpG
XC400S
XC4006
XC400B
XC4010
XC4013
XC400S
XC4006
XC400B
XC4010
XC4013
B.O
B.2
B.6
9.0
10.0
9.0
9.2
9.6
10.0
11.0
6.0
6.2
6.6
7.0
B.O
7.0
7.2
7.6
B.O
9.0
'tiS
;q;7
1::6:;1
i.6.• S
:%;S
:fi:7
TSG
:~:~
7.7
B.7
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Horizontal Longline Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing
patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more detailed, more
precise, and more up-to-date timing information, use the values provided by the XACT tirning calculator and used in the simulator.
-6
-5
-4
Device
Max
Max
Max
Units
T 101
XC400S
XC4006
XC400B
XC4010
XC4013
10.0
10.6
11.1
11.7
13.0
7.0
7.S
B.O
B.5
9.S
S.S
6.0
6.S
7.0
7.S
ns
ns
ns
ns
ns
T 102
XC400S
XC4006
XC400B
XC4010
XC4013
10.S
11.1
11.6
12.2
13.S
7.S
B.O
B.S
9.0
10.0
tal§:
l,Z.Q
7.,5
6.0
ns
ns
ns
ns
ns
Speed Grade
Description
Symbol
TeUF driving a Horizontal Longline (L.L.)
I going High or Low to L.L. going High or Low,
while T is Low, i.e. buffer is constantly active
T going Low toto L.L. going from resistive pull-up
High to active Low, (TBUF configured as open drain)
T going Low to L.L. going from resistive pull-up or
floating High to active Low, (TBUF configured as
open drain or active buffer with I Low)
TON
T going High to TBUF going inactive, not driving L.L.
XC400S
XC4006
XC400B
XC4010
XC4013
12.0
12.6
13.2
13.B
1S.1
10.0
10.5
11.0
11.5
12.6
;1;1;~:
ns
ns
ns
ns
ns
TOFF
All devices
3.0
2.0
riJ:!§:
ns
Tpus
XC400S
XC4006
XC400B
XC4010
XC4013
26.0
2B.0
30.0
32.0
36.0
22.0
24.0
26.0
2B.0
32.0
,lsitJ
26.0
ns
ns
ns
ns
ns
XC400S
XC4006
XC400B
XC4010
XC4013
12.0
13.0
14.0
15.0
17.0
10.0
11.0
12.0
13.0
1S.0
B.O
9.0
10.0
11.0
13.0
ns
ns
ns
ns
ns
=
T going High to L.L. going from Low to High,
pulled up by a single resistor
T going High to L.L. going from Low to High,
pulled up by two resistors
'§;9
t~~d;
TpUF
2-S0
t§:?j
;i~;~;
18:Q;
gg:p.
22;:0
Guaranteed Input and Output Parameters (Pin-ta-Pin)
All values listed below are tested directly and guaranteed over the operating conditions. The same parameters can also be derived
indirectly from the lOB and Global Buffer specifications. The XACT delay calculator uses this indirect method. When there is a
discrepancy between these two methods, the values listed below should be used, and the indirectly derived values must be
ignored.
Speed Grade
Description
Symbol
Global Clock to Output (fast~ OFF
.
-
Global Clock·to·Output Delay
(Max)
X3202
Global Clock to Output (sle~d) using OFF
~G
OFF
Global Clock·ta-Output Delay
'---
f----q
.
Input Set-up Time, using IFF (fast)
'~I:t=[]
TPG
(Max)
IFF
..
Input Hold time, using IFF (fast)
'" r ~
set,uK
TPG
IFF
(Min)
Hold
(Min)
X3201
Input Set-up Time, using IFF (with delay)
TPG
IFF
(Min)
X3201
'""':t=[]
set,uK
Hold
Time
I.
TPG
IFF
XC400S
XC4006
XC400B
XC4010
XC4013
XC400S
XC4006
XC400B
XC4010
XC4013
XC400S
XC4006
XC400B
XC4010
XC4013
ns
ns
ns
ns
ns
~
i}
:.
16.0
16.2
16.6
17.0
1B.0
~
1.S
1.3
0.9
O.S
-O.S
~;
}
:;::~:.{.
4.S
4.7
S.1
S.S
6.S
i
Tpsu
Time
Input Hold Time, using IFF (with delay)
13.0
13.2
13.6
14.0
TpHF
Time
I
'"'.~
Units
XC400S
XC4006
XC400B
XC4010
XC4013
TpSUF
X3201
set,uK
Hold
-4
Device
T ICKO
X3202
set,uK
Hold
Time
-5
TICKOF
---q
OFF
TpG
-6
i:
;:1;:
~f'i
... :
,,,:t:
l::::
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
XC400S
XC4006
XC400B
XC4010
XC4013
18.0
17.B
17.4
17.0
16.0
ns
ns
ns
ns
ns
XC400S
XC4006
XC400B
XC4010
XC4013
-5.0
-4.B
-4.4
-4.0
-3.0
ns
ns
ns
ns
ns
TpH
(Min)
X3201
Timing is measured at pin threshold, with 50 pF extemal capacitive loads (incl. test fixture).
When testing. fast outputs, only one output switches. When testing slew-rate limited outputs, half the number of outputs on one side
of the device are switching.
These parameter values are tested and guaranteed for worst-case conditions of supply voltage and temperature, and also with the
most unfavorable clock polarity choice. The use of a falling-edge clock in the lOB increases the effective clock delay by 1 to 2 ns.
The use of a rising clock edge, therefore, reduces the clock-to-Q delay, and ends the hold-time requirement earlier.
The use of a falling clock edge reduces the input set-up time requirement. In the tradition of guaranteeing absolute worst-case
parameter values, the table above does not take advantage of these improvements. The user can chose between a rising clock
edge with slightly shorter output delay, or a falling clock edge with slightly shorter input set-up time. One of these parameters is
inevitably better than the guaranteed specification listed above, albeit by only 1 to 2 ns.
2-S1
II
XC4000 Logic Cell Array Family
lOB Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-3851 0/605. All devices are 100%
functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing
patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more detailed, more
precise, and more up-to-date timing information, use the values provided by the XACT timing calculator and used in the simulator.
-6
Speed Grade
Description
Symbol
Input
Propagation Delays
Pad to 11, 12
Pad to 11, 12, via transparent latch (fast)
Pad to 11, 12, via transparent latch (with delay)
Clock (IK) tol1, 12, (flip-flop)
Clock (IK) to 11, 12 (latch enable ative, Low)
Min
T plO
T plCK
Hold Time (Note 3)
Pad to Clock (IK), fast
Pad to Clock (IK) with delay
T IKPI
TplCKO
Min
4.0
8.0
26.0
8.0
8.0
TpLi
TpOLI
TIKRI
TIKLI
Set-up Time (Note 3)
Pad to Clock (IK), fast
Pad to Clock (IK) with delay
Max
-5
-4
Max
Min
3.0
7.0
24.0
7.0
7.0
7.0
25.0
6.0
24.0
1.0
-8.0
1.0
-8.0
Max Units
2.8
6.0
14.0
6.0
6.0
4.0
12.0
ns
ns
ns
ns
ns
ns
ns
:::) :.i:••••:
::::
TIKPIO
tHy········
-8;:(Yf'····
ns
ns
...........· · i
(..........•
I(
Output
Propagation Delays
Clock (OK) to Pad
(fast)
same
(slew rate limited)
Output (0) to Pad
(fast)
same
(Slew-rate limited)
3-state to Pad begin hi-Z (fast)
same
(slew-rate limited)
3-state to Pad active and valid (fast)
same
(slew -rate limited)
TOKPOF
TOKPOS
T OPF
Tops
TTSHZF
TTSHZS
TTSONF
TTSONS
Set-up and Hold Times
Output (0) to clock (OK) set-up time
Output (0) to clock (OK) hold time
TOOK
T OKO
8.0
0
6.0
0
5.5
0
ns
ns
Clock
Clock High or Low time
TCHlcL
5.0
4.5
4.5
ns
.
Global SeVReset
Delay from GSR net through Q to 11, 12
Delay from GSR net to Pad
GSR width
TRRI
T RPO
T MRW
7.5
11.5
9.0
13.0
9.0
13.0
13.0
17.0
7.0
10.0
7.0
10.0
7.0
10.0
10.0
13.0
14.5
18.0
21.0
~: I;~:~
:;~;:;: i?: .. 5.5
:·····8.5
h··6 .5
::::::~::~:::: }'9.5
:j:it{~~::
::;:::;:::::::.:
;I~~:~
13.5
14.0
13.5
17.0
18.0
18.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
• Timing is based on the XC4005. For other devices see XACT timing calculator.
Notes: 1. Timing is measured at pin threshold, with 50 pF external capacitive loads (incl. test fixture). Slew rate limited output
rise/fall times are approximately two times longer than fast output rise/fall times. A maximum total external capacitive
load for simultaneous fast mode switching in the same direction is 200 pF per power/ground pin pair. For slewrate limited outputs this total is two times larger. Exceeding this maximum capacitive load can result in ground
bounce of >1.5 V amplitude, <5 ns duration, which might cause problems when the LCA drives clocks and other
asynchronous signals.
2. Voltage levels of unused (bonded and unbonded) pads must be valid logic levels. Each can be configured with the
internal pull-up or pull-down resistor or alternatively configured as a driven output or be driven from an external source.
3. Input pad setup times and hold times are specified with respect to the intemal clock (IK). To calculate system setup time,
subtract clock delay (clock pad to IK) from the specified input pad setup time value, but do not subtract below zero.
Negative hold time means that the delay in the input data is adequate for the external system hold time to be zero,
provided the input clock uses the Global signal distribution from pad to IK.
2-52
~XIUNX
CLB Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-3851 0/605. All devices are 100%
functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing
patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more detailed, more
precise, and more up-to-date timing information, use the values provided by the XACT timing calculator and used in the simulator.
Speed Grade
Symbol
Description
Min
Combinatorial Delays
FIG inputs to XIV outputs
FIG inputs via H' to XIV outputs
C inputs via H' to XIV outputs
CLB Fast Carry Logic
Operand inputs (F1,F2,G1,G4) to COUT
Add/Subtract input (F3) to COUT
Initialization inputs (F1,F3) to COUT
CIN through function generators to XIV outputs
CIN to COUT' bypass function generators.
Sequential Delays
Clock K to outputs Q
Set-up Time before Clock K
FIG inputs
FIG inputs via H'
C inputs via H1
C inputs via DIN
C inputs via EC
C inputs via SIR, going Low (inactive)
CIN input via F'/G'
CIN input via F'/G' and H'
-5
-6
-4
Max
Min Max
6.0
8.0
7.0
4.5
7.0
5.0
7.0
8.0
6.0
6.0
4.0
8.0
2.0
6.0
5.0
3.0
Min Max Units
4.0
4.5
ns
ns
ns
5.0
5.5
3.5
5.5
1.5
ns
ns
ns
ns
ns
A3 0
1""1
'",,"""'1 ·
ns
6.0
5.5
1.5
6.0
4.5
8.0
7.0
4.0
7.0
6.0
6.0
5.0
3.0
4.0
4.5
8.0
6.0
10.0
7.5
ns
ns
ns
ns
ns
ns
ns
ns
Hold Time after Clock K
FIG inputs
FIG inputs via H'
C inputs via H1
C inputs via DIN
C inputs via EC
C inputs via SIR, going Low (inactive)
o
o
o
o
o
o
oK::l
o
o
o
ns
ns
ns
ns
ns
ns
Clock
Clock High time
Clock Low time
4.5
4.5
4.5
4.5
ns
ns
Set/Reset Direct
Width (High)
Delay from C to Q
T RPW
TRIO
5.0
Master Set/Reset"
Width (High or Low)
Delay from Global Set/Reset net to Q
TMRW
TMRQ
21.0
2-53
4.0
9.0
• Timing is based on the XC4005. For other devices see XACT timing calculator.
~4;::[:
4.0
8.0
18.0
33.0
7.0
ns
ns
28.0
ns
ns
18.0
31.0
II
XC4000 Logic Cell Array Family
CLB Switching Characteristic Guidelines (continued)
Testing of the switching parameters is modeled after testing methods specified by MIL-M-3851 0/605. All devices are 100%
functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing
patterns. The following guidelines reflect worst-case values over the rec!)mmended operating conditions. For more detailed, more
precise, and more up-to-date timing information, use the values provided by the XACT timing calculator and used in the simulator.
CLB RAM Option
Description
Symbol
-5
-6
Speed Grade
Min
Max
I----~----------~----------+_--~----_r--+_~
Write Operation
Address write cycle time
Write Enable pulse width (High)
16 x2
32
Address set-up time before beginning of WE
x1
16 x2
32
Address hold time after end of WE
x1
x1
DIN set-up time before end of WE
16x2
32 x 1
16x2
DIN hold time after end of WE
32x 1
both
Min Max
B..o
B•.o
4 ..0
4 ..0
2 ..0
2 ..0
2 ..0
9 ..0
9 ..0
5 ..0
5 ..0
2 ..0
2 ..0
2 ..0
2 ..0
4 ..0
5 ..0
2 ..0
16 x2
32
-4
Min Max Units
8.0
ns
B.D
4 ..0
4 ..0
2.D Itr"
ns
2if;~t%'
ns
2itl l-
ns
~~.~
i'~
2J)
2.0
4 ..0
5 ..0
2 ..0
~
l.J~
ns
ns
ns
ns
ns
ns
ns
.,;,.~
Read Operation
Address read cycle time
Data valid after address change
(no Write Enable)
Read Operation, Clocking Data into Flip-Flop
Address setup time before clock K
7 ..0
1.0..0
16x2
32
x1
16 x2
6 ..0
6..0
B..o
16 x2
x1
Read During Write, Clocking Data into Flip-Flop
WE setup time before clock K
16 x2
16 x2
32 x 1
16 x2
Data setup time before clock K
14..0
12..0
15..0
16x2
TOCK
11 ..0
32 x 1
TOCKT
14..0
TWCK
Note: Timing for the 16 x 1 RAM option is identical to 16 x 2 RAM timing
2-54
ns
ns
ns
ns
1.0•.0
12..0
9 ..0
11 •.0
11 ..0
TWCKT
32 x 1
ns
4.5
6 ..0
12..0
15..0
32 x 1
ns
4.5
7 ..0
B..o
32 x 1
32
Read During Write
Data valid after WE going active
(DIN stable before WE)
Data valid after DIN
(DIN change during WE)
5.5
7.5
1.0 ..0
12..0
9 ..0
11 ..0
9 ..0
11 ..0
9 ..0
11 ..0
ns
ns
ns
ns
9.5
ns
11.5
hs
9 ..0
11 ..0
ns
ns
CLB RAM Timing Characteristics
ADDRESS
WRITE
WRITE ENABLE
DATA IN
READ
X,YOUTPUTS
II
READ, CLOCKING DATA INTO FLIP-FLOP
TIcK:----j.i;-==:..T~C~H~=:.~I~----_:_--------
I-
I
CLOCK
XO,YO OUTPUTS
I
VALID
(OLD)
VALID
(NEW)
READ DURING WRITE
Twp
WRITE ENABLE
DATA IN
(stable during WE)
X,YOUTPUTS
DATA IN
(changing during WE)
X,YOUTPUTS
VALID
OLD
NEW
VALID
(PREVIOUS)
VALID
(NEW)
READ DURING WRITE, CLOCKING DATA INTO FLIP-FLOP
WRITE ENABLE
____
~~IWC:K-----~TIWp
~-
DATA IN
CLOCK
XO,YO OUTPUTS
X2640
2-55
XC4000 Logic Cell Array Family
The
Xilinx
2-56
XC4010™
XC4005 Pinouts
Pin
Description
vee
VO(A8)
VO(A9)
VO
110
PC84
2
3
4
-
·
·
·
·
110 (Al0)
110(All)
110
VO
GND
5
6
Bound
PQ160 PQ208 PGl56 Scan
142
183
H3
HI
44
143
184
144
185
Gl
47
145
166
G2
50
146
187
G3
53
188
·
·
·
·
189*
·
·
147
148
149
150
151
Fl
F2
El
E2
F3
56
59
62
65
·
·
·
·
01
02
E3
Cl
68
71
·
-
VO(AI2)
VO(AI3)
7
8
152
153
154
155
·
·
·
.
·
·
156
157
158
159
160
201
202
203
C2
03
Bl
B2
74
77
80
83
C3
-
·
·
-
VO
VO
VO(Al')
SGCKI (A15,110)
vee
·
·
-
·
·
·
·
·
9
10
11
-
·
·
·
·
-
·
·
GNo
12
1
-
20'
205
206
207
208
1
2
3'
4
5
6
7
98
101
·
·
·
·
14
15
16
17
18
19
20'
C6
·
B5
B6
AS
C7
104
107
110
113
·
·
B7
A6
A7
A8
C8
B8
C9
B9
A9
Bl0
116
119
122
125
·
·
·
·
-
·
VO
VO
VO
VO
VO
SGCK3(110)
GND
Cl0
Al0
All
140
143
1'6
1.9
30
31
32
33
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
34
44
.
VO(IDI)
(TCK)
15
16
·
·
·
·
·
·
·
6
7
8
9
-
17
18
10
11
12
13
14
·
·
·
-
·
VO
VO
110
110
GND
·
15
16
17
18
19
20
21
22
23
24
vee
VO
VO
VO
VO
·
19
20
21
22
23
24
·
·
·
·
-
110
VO
VO
25
26
VO
GND
·
·
·
-
110
110
110
·
·
·
·
-
·
·
27
·
·
GND
VO
VO
110
VO
B4
A3
A4
·
·
·
·
·
8
9
10
11
12
13
-
-
·
-
·
110
VO
110 (TMS)
110
VO
VO
IIO(I:DC)
·
2
3
4
5
GND
-
·
66
89
92
95
·
13
14
-
·
·
·
M2
PGCK2(VO)
VO(HDC)
VO
·
·
·
-
·
·
·
·
·
·
B3
AI
A2
C5
-
PGCKI (A16, VOl
VO(Al?)
110
VO
vo
·
vee
·
·
·
·
·
-
·
·
VO
SGCK2(IIO)
Ml
GND
MO
190
191
192
193
194
195
196
197
198
199
200
·
Pin
Descrlpllon
110
·
25
26
27
28
29
-
-
C4
-
Bll
Cll
-
-
·
128
131
134
137
-
·
·
VO
VO
VO
110 (ERR, INIT)
vee
GND
VO
VO
110
VO
·
·
110
110
110
VO
GND
-
PC84
26
29
30
31
·
32
·
·
33
34
35
36
·
·
·
·
37
·
·
·
·
·
·
·
38
39
·
·
40
41
42
43
44
45
·
·
·
·
46
47
·
-
·
·
·
4B
49
·
·
50
51
52
PQl60 PQ208 PG156
35
45
C12
-
36
37
38
39
40
·
·
·
41
42
43
44
45
46
47
4B
49
50
·
-
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
·
71
72
73
74
75
76
77
78
79
-
-
DONE
53
60
-
·
·
·
54
81
·
-
vee
·
-
-
-
·
-
PROO
82
·
·
110(07)
PGCK3(110)
VO
55
56
57
·
as
A12
·
·
·
Pin
Descriplion
110
-
-
-
-
46
47
4B
49
B13
B14
A15
C13
164
167
170
·
-
50
51
52
53
54
55
56
57
58
59
A16
173t
·
·
·
·
·
·
GND
VO
VO
VO(D5)
110 (CSO)
·
·
·
·
·
·
·
59
50
·
·
·
·
·
50
015
184
vee
61
62
63
64
65
66'
67
68
69
70
71
El'
C16
E15
016
187
190
GND
VO(D3)
110 (AS)
VO
110
64
65
-
·
·
.
72'
73
74
75
76
77
78
79
60
81
82
83
64'
85'
86
87
B8
89
90
91'
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
·
110
VO
VO(D4)
VO
·
·
·
·
·
Fl.
F15
E16
F16
G14
193
196
199
202
·
-
110(02)
110
110
VO
GND
-
-
GIS
G16
H16
HIS
H14
J14
J15
J16
K16
K15
205
208
211
214
-
-
·
K14
L16
M16
L15
L14
·
·
N16
M15
P16
M14
N15
P15
N14
R16
P14
·
·
·
217
220
223
226
·
-
67
66
·
·
·
-
-
·
VO(Dl)
110 (RClK-8USYIROY)
110
69
70
-
119
120
121
122
123
-
124*
96
97
98
99
100
101
102
103
104
105
-
106
107
108
109
110
·
·
111
112
113
114
115
·
-
·
·
-
·
·
·
·
Rl'
T16
TIS
R13
259
262
265
-
·
-
-
-
-
66
112
P12
268
A14
158
VO(06)
58
87
113
T14
271
·
VO
VO(CS1,A2)
VO(A3)
·
·
·
-
GND
110
110
VO(A4)
110 (AS)
·
·
110
VO
VO(A6)
VO(A7)
GND
301
304
307
310
·
·
-
P7
T5
R6
T4
313
316
319
322
P6
·
·
R5
·
T3
P5
R4
-
-
·
·
·
325
328
331
160
161
162
163
·
.
N3
Rl
P2
N2
-
·
M3
PI
Nl
M2
Ml
11
14
17
-
126
127
128
129
130
-
·
·
76
77
78
241
244
247
250
253
256
·
·
122
123
124
125
75
·
·
·
121
·
·
289
292
295
298
153
154
155
156
157
158
159
·
·
·
·
TOO
GND
110 (AO,WS)
PGCK4 (AI ,110)
VO
·
·
RIO
T9
R9
P9
R8
P8
T8
T7
T6
R7
119
120
·
·
·
·
277
280
283
286
.
229
232
235
238
·
142
143
144
145
146
147
148
149
·
·
150
151
152
74
·
131
132
133
134
135
136·
137
138
139
140
141
-
-
·
vce
-
125
126
127
128
129
130
Pll
Rll
TIl
Tl0
Pl0
Bound
Scan
274
116
117
118
·
·
-
-
Boundary Scan Bit 0 = TOO.T
Boundary Scan Bit 1 = Too.O
Boundary Scan Bit 343 = BSCANT.UPO
·
66
-
-
91
92
93
94
95
71
72
73
R15
P13
·
-
61
62
63
PQ160 PQ208 PG156
114
T13
B8
115
R12
89
115
R12
89
90
116
T12
117
·
118
·
VO
110 (DO, DIN)
SGCK4 (DOUT, VOl
CCLK
110
2-57
-
-
174t
175
178
181
152
155
* Indicates unconnected package pins.
t Contributes only one bit (.i) to the boundary scan register,
-
PC84
C14
B15
B16
014
CIS
B12
A13
·
-
83
84
Bound
Scan
161
·
-
·
-
·
·
·
·
83
8.
136
137
138
139
140
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
1
141
182
79
80
·
-
·
·
61
B2
131
132
133
134
135
·
R3
P4
T2
R2
334
337
340
P3
-
·
·
·
·
·
T1
l3
L2
Ll
K3
K2
-
·
-
2
5
8
-
·
·
·
·
20
23
26
29
·
·
K1
Jl
J2
J3
H2
32
35
38
41
·
II
XC4000 Logie Cell Array Family
XC4006 Pinouts
Pin
Description
110 (A8)
liD (A9)
liD
liD
PGI56
H3
HI
Gl
G2
G3
PQ160
142
143
144
145
146
-
-
-
110 (Al0)
110 (All)
110
110
GND
Fl
F2
El
E2
F3
147
148
149
150
151
-
-
-
liD
110
110 (AI2)
110 (AI3)
110
110 '
Dl
D2
E3
Cl
C2
D3
Bl
B2
C3
152
153
154
155
156
157
158
159
160
-
-
-
-
GND
C4
-
1
-
PGCKI (AI6, 110)
110 (AI7)
110
liD
I/O (TDI)
110 (TCK)
I/O
110
B3
AI
A2
C5
B4
A3
A4
2
3
4
5
6
7
8
9
-
-
-
GND
I/O
110
110 (TMS)
I/O
C6
B5
B6
AS
C7
10
11
12
13
14
-
-
-
110
110
liD
liD
GND
B7
A6
A7
A8
C8
B8
15
16
17
18
19
20
vee
-
110 (A14)
SGCKI (AI5, 110)
vee
-
-
vee
-
PQ208
183
184
185
186
187
188'
189'
190
191
192
193
194
195'
196'
197
198
199
200
201
202
203
,204
205
206'
207'
208'
I'
2
3'
4
5
6
7
8
9
10
11
12'
13'
14
15
16
17
18
19'
20'
21
22
23
24
25
26
Bound
Scan
Pin
Descrlpllon
110
liD
110
110
PGI56
C9
B9
A9
Bl0
PQI60
21
22
23
24
-
-
-
-
62
65
68
72
liD
liD
110
110
GND
Cl0
Al0
All
Bl1
Cl1
25
26
27
28
29
-
-
-
110
110
I/O
liD
110
I/O
liD
.SGCK2 (110)
Ml
GND
MO
A12
B12
A13
A14
C12
B13
B14
A15
C13
A16
30
31
32
33
34
35
36
37
38
39
40
-
-
-
-
M2
PGCK2(V0)
110 (HDC)
liD
110
I/O
I/O (lOC)
110
110
C14
B15
B16
D14
C15
D15
E14
C16
E15
016
41
42
43
44
45
46
47
48
49
50
-
-
-
-
122
125
128
131
GND
I/O
110
110
liD
F14
F15
E16
F16
G14
51
52
53
-
-
-
110
110
I/O
110 (ERR, INIT)
G15
G16
H16
H15
H14
56
57
58
59
60
50
53
56
59
-
-
74
77
80
83
86
89
92
95'
-
-
vee
98
101
104
107
110
113
116
119
136
137
140
143
-
vee
, Indicates unconnecled package pins.
t Contributes only one b~ (J) to the boundary scan register.
2-58
-
54
55
PQ208
27
28
29
30
31'
32'
33
34
35
36
37
38'
39'
40
41
42
43
44
45
46
47
48
49
50
51'
52'
53'
54'
55
56
57
58
59
60
61
62
63
64
65'
66'
67
68
69
70
71
72'
73'
74
75
76
77
78
Bound
Scan
146
149
152
155
-
158
161
164
167
170
173
176
179
182
185
188
191
194
197t
-
-
198t
199
202
205
208
211
214
217
220
223
226
229
232
235
238
241
244
-
XC4006 Pinouts (continued)
Pin
Description
Pin
Description
PGI56
GND
J14
61
79
-
GND
1/0
J15
80
247
101
102
131
132
81
250
T7
1/0
J16
K16
VO(D3)
VO ('RS)
P8
T8
VO
62
63
64
82
253
1/0
T6
103
104
133
134
349
1/0
K15
65
256
VO
R7
105
135
352
-
-
83
84"
-
-
-
136"
-
-
137"
-
PQ160
PQ208
Bound
Scan
-
-
-
1/0
K14
66
86
259
1/0
67
68
87
262
VO
L16
M16
88
265
268
Bound
Scan
343
346
-
-
1/0(02)
P7
106
138
355
VO
VO
VO
T5
R6
107
108
139
140
358
381
T4
109
141
384
-
GND
P6
110
-
-
-
142
143"
VO
VO
1/0(01)
VO (RCLK-BUSY/RDY)
R5
T3
111
112
113
145
146
147
P5
114
148
1/0
R4
R3
115
98
283
286
99
100
289
292
,1/0 (DO, DIN)
P4
1"2
117
118
149
150
1'51
85"
1/0
LIS
69
89
GND
L14
70
-
-
-
90
91"
1/0
71
72
73
93
94
95
271
274
1/0
N16
MIS
P16
1/0
M14
74
280
VO
NIS
96
97
va
PGI56 PQI60 PQ208
92"
'1/0
P15
75
76
1/0
SGCK3 (VO)
N14
R16
77
78
GND
P14
79
101
-
-
-
102"
DONE
R15
80
-
-
103
104"
vee
-
-
P13
81
-
-
-
PROG
R14
82
lOS"
106
107*
-
277
VO
SGCK4 (DOUT, VOl
CCLK
-
-
-
116
144"
152
367
370
373
376
379
382
385
388
-
R2
119
153
vee
P3
120
-
-
-
154
ISS"
TDO
Tl
121
158"
159
GND
122
160
123
161
2
124
162
5
8
11
-
156"
157"
-
-
VO(D7)
T16
63
108
109
295
1/0 (AO,WS)
N3
Rl
PGCK3(VO)
TIS
84
110
298
PGCK4 (1/0, AI)
P2
1/0
R13
65
111
301
125
163
P12
T14
86
87
112
113
304
307
M3
PI
126
127
184
165
T13
88
114
310
VO
ItO
1/0 (CS1,A2)
1/0 (A3)
N2
VO
VO(D6)
VO
VO
VO
Nl
128
166
17
R12
89
115
313
1/0
M2
129
167
20
T12
90
116
316
1/0
Ml
168
23
-
-
117"
-
-
130
-
169"
170"
GND
GND
1/0
-
14
131
171
-
132
172
26
133
173
29
134
174
32
135
35
-
175
176"
136"
177"
-
118"
Pll
91
119
-
Rll
92
120
319
VO
1/0
TIl
93
121
323
1/0
1/0(05)
Tl0
94
122
325
1/0 (A4)
1/0 (CSO)
Pl0
95
328
1/0 (AS)
-
-
123
124"
l3
L2
Ll
K3
K2
-
125"
-
-
-
1/0
RIO
T9
96
126
331
1/0
Kl
137
178
1/0
97
127
334
1/0
Jl
138
179
38
41
1/0(04)
R9
98
128
337
1/0 (A6)
J2
139
180
44
1/0
P9
99
129
340
VO(A7)
J3
140
181
47
vee
R8
100
130
-
GND
H2
141
182
-
-
" Indicates unconnected package pins.
Boundary Scan Bit 0 = TDO.T
Boundary Scan Bit 1 = TDO.O
Boundary Scan B~ 391 = BSCANT.UPD
2-59
-
-
I
XC4000 Logic Cell Array Family
XC4008 Pinouts
Pin
Description
PG191 PQ208
Bound
Scan
Pin
Description
-
Pin
Description
VO(03)
K16
80
277
1/0 (RS)
U9
133
1/0
K17
81
280
110
V9
134
391
170
173
1/0
K18
82
283
1/0
V8
135
1/0
L18
83
286
1/0
U8
136
394
397
31
176
110
L17
289
110
T8
137
400
Cll
32
179
1/0
L16
64
85
292
110(02)
V7
138
403
33
34
182
185
1/0
1/0
M18
M17
86
87
295
298
110
1/0
Bl1
A12
VO
U7
V6
139
140
406
409
110
GND
U6
141
412
T7
V5-
142
143-
-
PG191 PQ208
010
26
Cl0
27
Bound
Scan
Pin
Description
164
GND
1/0
vee
J4
183
-
vee
VO(A8)
J3
184
56
1/0
1/0 (A9)
J2
185
59
1/0
Bl0
28
167
1/0
Jl
186
62
A9
1/0
Hl
187
65
110
110
Al0
29
30
110
H2
188
68
1/0
All
110
110 (Al0)
H3
Gl
189
1/0
1/0
1/0 (All)
G2
190
191
71
74
77
PG191 PQ208
79
K15
Bound
Scan
110
Fl
192
80
110
B12
1/0
N18
88
301
El
193
83
110
A13
35
36
188
1/0
191
1/0
194
195-
37
38-
-
GND
196-
-
C12
B13-
01-
-
GND
-
G3
F2-
A14-
39-
-
-
89
90
91-
304
GND
P18
M16
N17R18-
92-
-
110
Cl
197
86
1/0
A15
40
194
1/0
T18
93
307
1/0
E2
198
89
110
C13
41
199
92
1/0
B14
42
95
1/0 (A13)
02
200
95
VO
A16
43
203
1/0
P17
N16
T17
94
F3
197
200
1/0
1/0 (A12)
96
1/0
Bl
201
98
110
B15
44
206
1/0
R17
97
45
209
110
P16
98
322
46
47
212
1/0
U18
SGCK3(1/0)
325
328
GND
T16
R16
99
100
101
102-
1/0
-
-
-
-
1/0
VO
E3
C2
202
203
101
1/0
C14
A17
104
SGCK2(1/0)
B16
B2
03
204
107
-
C15
015
48
205
206207-
Ml
GNO
215
218
49
-
-
-
MO
A18
DONE
U17
-
50
51-
221t
-
-
-
-
1/0 (A14)
SGCKl (A15, VOl
vee
GND
-
-
-
04
2081-
-
2
3-
PGCKl (A16,1/0)
C3
4
1/0 (A17)
C4
B3
5
1/0
6
-
-
1/0
C5
A2
-
5253-
vee
PG191 PQ208
132
T9
-
Bound
Scan
365
388
-
V4-
144-
110
1/0
U5
T6
146
310
VO(Ol)
313
V3
V2
316
VO (RGLK-BUSYIRDY)
1/0
U4
149
427
319
110
T5
150
430
147
148
415
418
421
426
U3
151
433
152
153
436
CCLK
T4
Vl
vee
R4
-
-
154
155"
156-
105-
-
R15
106
-
-
lor
-
U2
R3
T3
159
160
161
-
Ul
162
5
-
103
104-
1/0 (DO, DIN)
145
SGCK4 (DOUT,
VOl
157158-
-
PROG
V18
106
-
TOO
GND
110 (AO,WS)
1/0(07)
T15
PGCK4 (VO,Al)
PGCK3(1/0)
U16
109
110
331
57
222t
223
334
-
-
-
1/0
P3
163
8
-
-
-
-
-
226
-
-
58
1/0
T14
111
337
1/0
R2
164
11
C17
017
59
229
U15
V17
112
113
T2
232
110
1/0(06)
1/0 (CS1, A2)
60
VO(A3)
N3
165
166
14
17
-
54-
-
vee
016
55
110
C16
56
113
M2
PGCK2(VO)
B17
116
1/0 (HOC)
E16
-
-
-
7
119
122
VO
8
1/0
-
2
1/0 (TCK)
B4
9
125
1/0
B18
61
235
1/0
V16
114
340
343
346
1/0
P2
167
20
110
C6
10
128
110 (LOC)
E17
62
238
1/0
n3
115
349
1/0
168
23
1/0
A3
B5-
11
131
VO
F16
63
241
1/0
1/0
C18
64
244
-
-
169-
-
116
117-
352
12-
U14
V15-
Tl
RlN2-
170-
V14-
118-
GND
T12
119
1/0
U13
120
1/0
V13
121
1/0 (TOI)
-
-
GND
M3
171
-
1/0
Pl
172
26
1/0
Nl
M2
173
29
174
32
Ml
175
35
176
38
177
178
41
VO
L3
L2
Ll
373
1/0
Kl
179
47
127
376
1/0 (A6)
K2
160
50
-
B6"
13-
65"
C7
14
-
-
018"
GNO
Fl7*
66"
lIO
110
1/0 (TMS)
A4
15
134
GNO
G16
67
-
AS
16
137
VO
E18
68
247
B7
17
140
1/0
F18
69
250
1/0(05)
U12
122
361
1/0
A6
18
123
1/0
149
1/0
H16
124
125
B8
21
152
1/0
H17
73
262
VO
VO
Tl1
Ull
364
367
370
1/0
71
72
253
256
259
V12
19
20
G17
G18
1/0 (CSO)
C8
A7
VO
VO
70
110
143
146
Vll
126
A8
22
155
1/0
H18
74
265
1/0
Vl0
VO
VO
1/0
355
358
VO(A4)
VO(A5)
1/0
44
VO
B9
23
158
1/0
J18
75
268
110(04)
Ul0
128
379
VO (A7)
K3
181
53
1/0
C9
24
161
1/0
J17
76
271
1/0
no
129
382
GND
K4
182
09
25
-
110 (ERR, INIT)
J16
J15
77
272
vee
-
GNO
Rl0
78
-
GNO
R9
130
131
-
vee
* Indicates unconnected package pins.
t Contributes only one bit (.i) to the boundary scan register.
Boundary Scan Bit 0 = TOO.T
Boundary Scan Bit 1 = TOO.O
Boundary Scan B~ 439 = BSCANT.UPO
2-60
XC4010 Pinouts
PIn
Description
Bound
PGI91 P0208 Scan
vee
J4
VO(A8)
J3
J2
VO(A9)
-
Pin
Description
62
1/0
1/0
185
65
I/O
lB6
58
183
184
Bound
PGISI P02D8 Scan
Cl0
BIO
A9
27
28
AIO
30
202
113
SGCK2(VO)
C2
203
116
SGCKI (AI5,1/0)
B2
204
119
VCC
D3
-
-
205
206'
-
E3
1/0 (AI4)
-
-
GND
337
343
346
VO
VO
VO
VO
I/O
P17
1/0
1/0
N16
95
349
VO(OI)
230
T17
96
352
va (RCLK-BUSYIRDY)
F3
VO
-
91
92
224
227
1/0
-
90
42
101
104
110
334
93
94
198
-
89
VO
VO
VO
NI7
RIB
TIB
E2
201
32B
VO
VO
VO
B13
A14
-
110(02)
GND
1/0
1/0
Bl
325
215
VO
92
95
98
-
B6
B7
88
212
-
195
196
197
110
322
39
40
41
194
F2
01
Cl
VO
VO
VO
VO
85
38
G3
107
l16
MIB
M17
PIB
M16
VO
VO
VO
VO
199
200
319
-
GND
02
316
84
209
C12
1/0 (AI2)
1/0 (AI3)
83
l17
36
37
GND
110
lIB
VO
VO
VO
VO
200
89
80
313
33
34
35
86
77
82
Bll
B3
189
190
KIB
197
192
193
H3
BI
307
310
31
191
74
K15
K16
K17
32
Fl
El
71
18B
A12
B12
A13
A15
C13
B14
A16
B15
29
43
44
203
206
21B
221
NIB
451
454
143
457
460
144
145
146
147
463
466
148
469
472
149
475
150
47B
151
481
152
484
153
-
97
355
P16
98
35B
VO
VO
B16
239
VO
UIB
99
361
1/0 (~O, DIN)
Ml
GND
C15
48
242
SGCK3(1I0)
T16
100
364
SGCK4 (DOUr, I/O)
015
49
-
GND
R16
MO
AlB
245t
-
-
50
51'
DONE
-
U17
-
101
102'
vce
R15
108
107'
367
VO(AO,WS)
T3
161
2
370
PGCK4 (VO, AI)
Ul
162
5
-
V18
4
122
PGCK2(I/O)
B17
PROG
VO (07)
T15
108
109
5
B
125
VO(HDC)
E16
58
250
PGCK3(VO)
U16
110
C4
B3
140
141
142
R17
246t
247
C3
442
445
448
136
139
110
56
57
VO (AI7)
VO
439
137
110
55
PGCKI (AI6,1/0)
136
134
236
016
3'
T7
V5
V4
U5
T6
V3
V2
U4
T5
U3
T4
VI
R4
135
430
433
436
133
233
C16
2
-
us
427
45
M2
04
-
T9
U9
V9
VB
UB
TB
V7
U7
V6
131
132
48
47
vee
GND
340
R9
A17
-
I'
-
331
VO(RS)
Bound
PGI91 PQ208 Scan
C14
-
207*
208'
GND
VO(03)
All
VO
VO
lB7
H2
-
Pin
Description
Cll
Gl
G2
HI
79
80
Scan
191
194
VO(Al0)
VO(All)
JI
GND
Bound
PGISI PQ208
VO
VO
VO
VO
VO
VO
VO
VO
VO
VO
VO
VO
VO
VO
VO
VO
VO
VO
VO
VO
VO
182
185
188
PIn
Description
-
-
52'
53'
54'
-
-
-
-
103
104'
105'
-
CClK
VCC
-
154
155'
-
-
TOO
U2
158'
159
GND
R3
160
-
156'
157'
-
-
-
128
-
-
-
-
-
-
-
-
-
-
-
-
-
C17
59
253
111
373
VO
P3
163
B
C5
7
131
017
60
256
VO
VO
T14
VO
VO
VO
VO
U15
112
376
R2
164
11
B18
61
259
1/0(06)
V17
113
379
VO(lOC)
E17
62
63
262
1/0
V16
114
3B2
l/O
VO(CS1,A2)
VO(A3)
-
VO(TDI)
A2
B
I/O (TCK)
B4
9
134
137
VO
VO
VO
VO
C6
10
140
A3
11
12
143
146
1/0
1/0
B5
B6
C7
A4
13
14
149
VO
VO
-
GND
15
152
VO(TMS)
AS
B7
16
17
155
158
I/O
A6
18
161
1/0
VO
C8
A7
19
20
164
167
VO
VO
VO
VO
VO
I/O
B8
21
170
GND
1/0
1/0
110
VO
VO
VO
VO
165
14
166
17
P2
Tl
'167
188
20
Rl
169
26
N2
M3
PI
170
171
172
29
T13
115
385
64
265
26B
I/O
C18
01B
I/O
U14
116
3BB
65
271
V15
117
391
F17
G16
EIB
66
67
274
VO
VO
V14
394
-
GND
68
277
120
397
GND
110
F18
G17
69
70
280
2B3
VO
VO
T12
U13
118
119
V13
121
VO(A4)
Nl
M2
35
122
400
403
173
174
38
G18
71
2B6
U12
V12
123
406
VO(AS)
Ml
175
41
H16
H17
72
73
2B9
292
TIl
Ull
124
125
409
176
177
47
HIB
74
295
VII
126
415
I/O
17B
50
JIB
75
298
VO
VO
Vl0
127
41B
J17
76
301
1/0(04)
Ul0
12B
421
I/O
110 (A6)
l3
L2
II
Kl
K2
K3
K4
44
412
VO
VO
179
lBO
56
lBl
59
lB2
-
F16
1/0(05)
VO(CSO)·
VO
110
-
1/0
I/O
AB
22
173
1/0
1/0
B9
23
176
VO
VO
VO
C9
24
179
I/O (ERR, INIT)
J16
77
304
I/O
Tl0
129
424
110 (A7)
GND
09
25
vee
J15
7B
vee
RIO
130
-
GND
vee
-
010
26
-
T2
N3
-
, Indicates unconnected peckage pins.
t Contributes only one bn (.i) 10 the boundary scan register.
Boundary Scan Bn 0 TOO.T
Boundary Scan Bn 1 = TOO.O
Boundary Scan Bft 487 = BSCANT.UPO
=
2·61
23
-
32
53
II
XC4000 Logic Cell Array Family
XC4013 Pinouts
Pin
Description
vee
110 (A8)
110 (A9)
110
110
110
110
VO(Al0)
110 (All)
vec
VO
VO
110
110
GND
110
VO
110
110
110 (AI2)
VO(AI3)
110
110
110
110
110 (AI4)
SGCKI (AI5,1/0)
vee
-
GND
PGCKI (A16,VO)
110 (AI7)
110
110
110 (TOI)
110 (TCK)
110
110
110
110
110
VO
GND
VO
110
110 (TMS)
110
vee
110
110
110
110
110
110
110
110
GND
vee
MQ208
183
184
185
186
187
188
189
190
191
-
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206"
207"
208'
I'
2
3'
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
-
PG223
J4
J3
J2
Jl
HI
H2
H3
Gl
G2
H4
G4
Fl
El
G3
F2
01
Cl
E2
F3
02
F4
E4
81
E3
C2
82
03
MQ240
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
Pin
Bound
Scan
Description
110
VO
VO
VO
110
110
74
77
80
83
86
89
-
~
92
95
04
C3
C4
83
C5
A2
84
C6
A3
85
86
05
06
C7
A4
AS
87
A6
-
-
07
08
-
-
19
20
21
22
23
24
25
26
C8
A7
88
A8
89
C9
09
010
-
98
101
104
107
011
012
110
110
110
VO
33
34
35
36
37
811
A12
812
A13
C12
013
014
813
A14
A15
C13
814
A16
815
C14
A17
816
CIS
015
A18
GND
VO
VO
VO
110
110
110
110
110
110
110
110
110
113
116
119
122
125
128
131
134
137
140
143
SGCK2(110)
Ml
GND
1
-
-
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22'
23
24
25
26
27
28
29
30
-
-
vee
146
149
152
155
158
161
164
167
170
173
176
179
M2
PGCK2 (110)
110 (HOC)
VO
VO
VO
110 (LOC)
110
110
110
VO
110
110
-
GND
182
185
188
191
110
110
110
VO
-
-
-
vee
-
-
-
PG223
Cl0
810
A9
Al0
All
Cll
110
110
MO
-
MQ208
27
28
29
30
31
32
38
39
40
41
42
43
44
45
46
47
48
49
50
51'
52'
53'
54'
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
016
C16
817
E16
C17
017
818
E17
F16
C18
018
F17
E15
F15
G16
E18
F18
G17
G18
vee
-
-
-
110
110
72
73
H16
H17
200
203
206
209
212
215
-
-
-
110
110
110
110
110
-
GIS
HIS
H18
J18
J17
J16
J15
194
197
-
110 (ERR, INIT)
vee
"" Indicates unconnected package pins.
t Contributes only one bit (.i) to the boundary scan register.
2-62
74
75
76
77
78
MQ240
31
32
33
34
35
36
37'
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
-
-
61
62
63
84
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83'
84
85
86
87
88
89
90
Bound
Scan
218
221
224
227
230
233
236
239
242
245
248
251
254
257
260
263
266
269
272
275
278
281
284
287
290
293t
-
294t
295
298
301
304
307
310
313
316
319
322
325
328
331
334
337
340
343
346
349
352
355
358
361
364
-
I:XIUNX
X4013 Pinouts (continued)
Pin
Descrlplion
GND
VO
1/0
1/0
1/0
VO
110
110
1/0
vee
VO
110208
79
80
81
82
83
84
85
PG223
K15
K16
K17
K18
L18
L17
L16
-
-
-
GND
86
87
88
89
90
1/0
1/0
-
110
110
1/0
VO
110
VO
110
VO
VO
VO
VO
110
SGCK3(11O)
GND
DONE
vee
-
PROG
VO(07)
PGCK3(1/0)
VO
VO
VO
VO
VO(06)
1/0
110
1/0
1/0
I/O
GND
1/0
-
91
92
93
94
95
96
97
98
99
100
101
102"
103
104"
lOS"
106
101"
f08
109
110
111
112
-
-
113
114
115.
116
117
118
119
-
I/O
LIS
MIS
-
M18
M17
N18
P18
M16
N15
PIS
N17
R18
T18
P17
N16
Tl7
R17
P16
U18
T16
R16
U17
-
-
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143"
144
145
146
147
148
149
150
-
-
122
123
U12
V12
I/O
110.(04)
I/O
vee
-
VIS
TIS
U16
T14
U15
R14
R13
V17
V16
Tl3
U14
V15
V14
Tl2
R12
Rl1
U13
V13
120
121
VO
VO
120
121 .
VO
VO
-
-
R15
VCC
1/0(05)
110 (CSO)
VO
MQ240
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
-
-
124
125
126
127
128
129
130
Tll
Ul1
Vll
Vl0
Ul0
TlO
RIO
Pin
Description
GND
VO(03)
110 (RS)
110
Bound
Scan
367
370
373
376
379
382
110
VO
1/0
-
385
388
VO(02)
110
vee
110
I/O
110
110
GND
I/O
110
I/O
391
394
397
400
-
403
406
409
412
415
418
421
424
427
430
433
436
VO
110
VO
1/0(01)
VO (ReLK-BOSV/ROY)
VO
VO
110(00, DIN)
SGCK4 (OOUT, 110
-
CCLK
-
vee
-
-
-
439
442
TOO
GND
IIO(AO,WS)
PGCK4 (110, Al)
445
1/0
448
451
454
457
460
110
110 (eSl,A2)
I/O (A3)
I/O
-
463
1/0
1/0
466
469
472
I/O
I/O
110
475
478
481
GND
1/0
1/0
1/0
484
-
VO
487
vee
1/0(A4)
1/0 (AS)
490
493
496
499
502
505
508
V7
U7
140
141
-
V6
U6
R8
R7
142
T7
-
143
144
145
146
147
148
149
150
151
152
153
154
155"
156"
157"
158"
159
160
161
162
163
164
165
166
-
167
168
169
170
171
172
173
-
-
R6
R5
V5
V4
US
T6
V3
V2
U4
T5
U3
T4
Vl
R4
-
-
U2
R3
T3
Ul
P3
R2
T2
N3
P4
N4
P2c
Tl
Rl
N2
M3
Pl
Nl
M4
L4
-
-
-
1/0
1/0
1/0
1/0
176
177
178
179
180
181
182
L3
GND
2-63
138
139
M2
Ml
VO (A7)
• Indicales unconnected package pins.
Boundary Scan Bil 0 = TOO.T
Boundary Scan Bit 1 = TOO.O
Boundary Scan Bil583 = BSCANT.UPO
PG223
R9
T9
U9
V9
VS
U8
T8
174
175
VO(A6)
-
MQ208
131
132
133
134
135
136
137
-
l2
Ll
Kl
K2
K3
K4
MQ240
151
152
153
154
155
156
157
158"
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
-
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195"
196
197
198
199
200
201
?O2
203
204"
205
206
207
208
209
210
211
Bound
Scan
-
511
514
517
520
523
526
529
532
-
535
538
541
544
547
550
553
556
559
562
565
568
571
574
577
580
-
-
181
2
5
8
11
14
17
20
23
26
29
32
35
38
41
44
47
50
53
-
56
59
62
65
68
71
-
I
XC4000 Logic Cell Array Family
For a detailed description of the device architecture, see page 2-9.
For a detailed description of the configuration modes and their timing, see pages 2-32 through 2-55.
For detailed lists of package pinouts, see pages 2-56 through 2-62.
For package physical dimensions, see Section 4.
Ordering Information
Example:
0""'" Type
Spee~
XC4010-SPG191C
T
J ILT_p,m,"re R~"
Grade
Number of Pins
Package Type
Component Availability
B = MIL-STD-883C Class B
2-64
XC4000A
Logic Cell Array Family
Product Description
Features
Description
• Third Generation Field-Programmable Gate Arraya
- Abundant flip-flops
- Flexible function generators
- On-chip ultra-fast RAM
- Dedicated high-speed carry-propagation circuit
- Wide edge decoders
- Hierarchy of interconnect lines
- Internal 3-state bus capability
- Eight global low-skew clock or Signal distribution
network
The XC4000A family of Field-Programmable Gate Arrays
(FPGAs) provides the benefits of custom CMOS VLSI,
while avoiding the initial cost, time delay, and inherent risk
of a conventional masked gate array.
The XC4000A family provides a regular, flexible, programmabie architecture of Configurable logic Blocks (ClBs),
inte.rconnected by a powerful hierarchy of versatile routing
resources, and surrounded by a perimeter of programmable lOBs.
The devices are customized by loading configuration data
into the internal memory cells. The FPGA can either actively
read its configuration data out of external serial or byteparallel PROM (master modes), or the configuration data
can be written into the FPGA (slave and peripheral modes).
• Flexible Array Architecture
- Programmable logic blocks and I/O blocks
- Programmable interconnects and wide decoders
• Sub-micron CMOS Process
- High-speed logic and Interconnect
- low power consumption
The XC4000A family is supported by powerful and sophisticated software, covering every aspect of design: from
schematic entry, to simulation, to automatic block placement and routing of interconnects, and finally the creation
of the configuration bit stream.
• Systems-Oriented Features
- IEEE 1149.1-compatible boundary-scan logic support
- Programmable output slew rate (4 modes)
- Programmable input pull-up or pull-down resistors
- 24-mA sink current per output (48 per pair)
Since Xilinx FPGAs can be reprogrammed an unlimited
number of times, they can be used in innovative designs
where hardware is changed dynamically, or where hardware must be adapted to different user applications. FPGAs
are ideal for shortening the design and development cycle,
but they also offer a cost-effective solution for production
rates well beyond 1000 systems per month.
• Configured by loading Binary File
- Unlimited reprogrammability
- Six programming modes
• XACT Development System runs on '386f486-type PC,
NEC PC, Apollo, Sun-4, and Hewlett-Packard 700
Series
- Interfaces to popular design environments like
Viewlogic, Mentor Graphics and OrCAD
- Fully automatic partitioning, placement and routing
- Interactive design editor for design optimization
- 288 macros, 34 hard macros, RAM/ROM compiler
For a detailed description of the device features, architecture, configuration methods and pin descriptions, see
pages 2-9 through 2-45.
Table 1. The XC4000A Family of Field-Programmable Gale Arrays
Device
Appr. Gate Count
ClB Matrix
Number of ClBs
Number of Flip-Flops
Max Decode Inputs (per side)
Max RAM Bits
Number of lOBs
XC4002A
2,000
8x8
64
256
24
2,048
64
2-65
XC4003A
XC4004A
XC4005A
3,000
10 x 10
·100
360
30
3,200
80
4,000
12 x 12
144
480
36
4,608
96
5,000
14 x 14
196
616
42
6,272
112
II
XC4000A Logic Cell Array Family
Absolute Maximum Ratings
Units
Vcc
Supply voltage relative to GND
-0.5 to 7.0
V
VIN
Input voltage with respect to GND
-0.5 to 7
V
VTS
Voltage applied to 3-state output
-0.5 to 7
V
TSTG
Storage temperature (ambient)
-65 to + 150
°C
TSOL
Maximum soldering temperature (10 s @ 1/16 in. = 1.5 mm)
+260
°C
TJ
Junction temperature
+ 150
°C
Note:
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those listed under Recommended Operating Conditions is not implied. Exposure to Absolute Maximum Ratings
conditions for extended periods of time may affect device reliability.
Operating Conditions
Vce
Supply voltage relative to GND
Commercial
Supply voltage relative to GND
Industrial
Supply voltage relative to GND
Military
Min
Max
Units
4.75
5.25
V
-40°C to 85°C
4.5
5.5
V
-55°C to 125°C
4.5
5.5
V
Vee
V
O°C to 70°C
VIH
High-level input voltage (XC4000 has TTL-like input thresholds)
2.0
VIL
Low-level input voltage (XC4000 has TTL-like input thresholds)
0
TIN
Input signal transition time
0.8
V
250
ns
Max
Units
DC Characteristics Over Operating Conditions
Min
= -4.0 mA, Vee min
VOH
High-level output voltage @ IOH
VOL
Low-level output voltage @ IOL
leco
Quiescent LCA supply current (Note 2)
ilL
Leakage current
CIN
Inout caoacitance (sam ole tested)
IRIN
Pad pull-up (when selected) @ VIN
IRLL
Horizontal Long Line pull-up (when selected) @ logic Low
2.4
= 24 mA, Vee max (Note 1)
-10
= OV (sample tested)
0.02
0.2
V
0.4
V
10
mA
+10
uA
15
of
0.25
mA
2.5
mA
Note: 1. With 50% of the outputs simultaneously sinking 24 mAo
2. With no output current loads, no active input or longline pull-up resistors, all package pins at Vcc or GND, and
the LCA configured with a MakeBits tie option.
2-66
~XILINX
Wide Decoder Switching Characteristic Guidelines
Testing ofthe switching parameters is modeled after testing methods specified by MIL-M-3851 0/605. All devices are 100% functionally
tested. Since many internal timing parameters cannot be measured directly, there derived from benchmark timing patterns. The following
guidelines relflect worst-case values over the recommended operating conditions. For more detailed, more precise, and more up-todate timing information, use the values provided by the XACT timing calculator and used in the simulator.
-6
-5
Device
Max
Max
XC4002A
XC4003A
XC4004A
XC400SA
8.S
9.0
9.S
10.0
7.S
8.0
8.S
9.0
ns
ns
ns
ns
XC4002A
XC4003A
XC4004A
XC400SA
11.S
12.0
12.S
13.0
10.S
11.0
11.S
12.0
ns
ns
ns
ns
Speed Grade
Description
Symbol
Full length, both pull-ups,
inputs from lOB I-pins
TWAF
Full length, both pull-ups
inputs from internal logic
TWAFL
Max
Units
Half length, one pull-up
inputs from .IOB I~pins .
T WAO
XC4002A
XC4003A
XC4004A
XC400SA
8.S
9.0
9.S
10.0
7.S
8.0
8.S
9.0
ns
ns
ns
ns
Half length; one pull-up
inputs from internal logic
T WAOL
XC4002A
XC4003A
XC4004A
XC400SA
11.S
12.0
12.5
13.0
10.S
11.0
11.S
12.0
ns
ns
ns
ns
Note: These delays are specified from the decoder input to the decoder output. For pin-to-pin delays, add the input delay (TPIJ
and output delay (one of 4 modes), as listed on page 2-70.
Global Buffer Switching Characteristic Guidelines
Testing ofthe switching parameters is modeled afte~testing methods specified by MIL~M-3851 0/605. All devices are 100% functionally
tested. Since many intemal timing parameters cannot be measured directly, they are derived from benchmark timing patterns. The
following guidelines reflect worst-case values over the recommended operating conditions. For more detailed, more precise, and more
up-to-date timing information, use the values provided by the XACT timing calculator and used in the simulator.
-6
-5
Symbol
Device
Max
Max
TpG
XC4002A
XC4003A
XC4004A
XC4005A
7.7
7.8
7.9
8.0
S.7
S.8
5.9
6.0
XC4002A
XC4003A
XC4004A
XC400SA
8.7
8.8
8.9
9.0
6.7
6.8
6.9
7.0
Speed Grade
Description
Global Signal Distribution
From pad through primary buffer, to any clock k
From pad through secondary buffer, to any clock k
TSG
2-67
Max
Units
ns
ns
ns
ns
ns
ns
ns
ns
I
XC4000A logic Cell Array Family
Horizontal Longline Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-3851 0/605. All devices are 100% functionally
tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing patterns. The
following guidelines reflect worst-case values over the recommended operating conditions. For more detailed, more precise, and more
up-to-date timing information, use the values provided by theXACT timing calculator and used in the simulator.
-6
-5
Symbol
Speed Grade
Device
Max
Max
TI01
XC4002A
XC4003A
XC4004A
XC400SA
8.2
8.8
9.4
10.0
6.0
6.2
6.6
7.0
ns
ns
ns
ns
I going Low to L.L. going from resistive pull-up
High to active Low, (TBUF configured as open drain)
T'02
XC4002A
XC4003A
XC4004A
XC400SA
8.7
9.3
9.9
10.S
6.S
6.7
7.1
7.S
ns
ns
ns
ns
T going Low to L.L. going from resistive pull-up
or floating High to active Low, (TUBF configured
as open drain)
TON
XC4002A
XC4003A
XC4004A
XC4005A
10.1
10.7
11.4
12.0
8.4
9.0
9.S
10.0
ns
ns
ns
ns
T going High to TBUF going inactive, not driving L.L.
TOFF
All devices
3.0
2.0
ns
T going High to L.L. going from Low to High,
pulled up by a single resistor
Tpus
XC4002A
XC4003A
XC4004A
XC400SA
23.0
24.0
2S.0
26.0
19.0
20.0
21.0
22.0
ns
ns
ns
ns
TpUF
XC4002A
XC4003A
XC4004A
XC400SA
10.S
11.0
11.S
12.0
8.S
9.0
9.S
10.0
ns
ns
ns
ns
Description
TBUF driving a Horizontal Longline (L.L.)
I going High or Low to L.L. going High or Low,
while T is Low, i.e. buffer is constantly active
T going High to L.L. going from Low to High,
pulled up by two resistors
2-68
Max
Units
-----------
~--,~~~~
Guaranteed Input and Output Parameters (Pin-ta-Pin)
All values listed below are tested directly and guaranteed over the operating conditions. The same parameters can also be derived
indirectly from the lOB and Global Buffer specifications. The XACT delay calculator uses this indirect method. When there is a
discrepancy between these two methods, the directly tested values listed below should be used, and the indirectly derived values must
be ignored.
Speed Grade
Description
Global Clock to Output (fast)
Symbol
Device
TICKOF
XC4002A
XC4003A
XC4004A
XC4005A
(Max)
Global Clock to Output (slew limited)
T ICKO
(Max)
Input Set-up Time, using IFF (fast)
TpSUF
(Min)
Input Hold time, using IFF (fast)
TpHF
(Min)
Input Set-up Time, using IFF (with delay)
Tpsu
(Min)
Input Hold Time, using IFF (with delay)
TpH
(Min)
~t:!~r8
I
Hold
Time
TpG
JJT
Global Clock-to-Oulput Delay
XC4002A
XC4003A
XC4004A
XC4005A
XC4002A
XC4003A
XC4004A
XC4005A
XC4002A
XC4003A
XC4004A
XC4005A
XC4002A
XC4003A
XC4004A
XC4005A
XC4002A
XC4003A
XC4004A
XC4005A
-6
-5
I----
-
-
Units
12.2
12.5
12.8
13.0
ns
ns
ns
ns
15.2
15.5
15.8
ns
ns
ns
ns
~
2.3
2.0
1.7
~
-
ns
ns
ns
ns
3.7
4.0
4.3
4.5
ns
ns
ns
ns
18.8
18.5
18.2
ns
ns
ns
ns
~
-5.8
-5.5
-5.2
-5.0
ns
ns
ns
ns
and also with the most unfavorable clock polarity choice.
The use of a falling-edge clock in the lOB increases the
effective clock delay by 1 to 2 ns.
•
The use of a rising clock edge, therefore, reduces the
clock-to-Q delay, and ends the hold-time requirement
earlier. The use of a falling clock edge reduces the input
set-up time requirement.
•
:
X3192
In the tradition of guaranteeing absolute worst-case parameter values, the table above does not take advantage
of these improvements. The user can chose between a
rising clock edge with slightly shorter output delay, or a
falling clock edge with slightly shorter input set-up time.
One of these parameters is inevitably better than the
guaranteed specification listed above, albeit by only
one to two nanoseconds
Timing is measured at pin threshold, with 50 pF external
capacitive loads (incl. test fixture).
When testing fast outputs, only one output switches. When
testing slew-rate limited outputs, half the number of outputs on one side of the device are switching.
These parameter values are tested and guaranteed for
worst-case conditions of supply voltage and temperature,
2-69
II
XC4000A logic Cell Array Famil!
lOB Switching Characteristic Guidelines
Testing olthe switching parameters is modeled after testing methods specified by MIL-M-38S10/S0S. All devices are 100% functionally
tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing patterns. The
following guidelines reflect worst-case values over the recommended operating conditions. For mOre detailed, more precise, and more
up-to-date timing information, use the values provided by the XACT timing calculator and used in the simulator.
Description
Symbol
INPUT
Propagation Delays
Padtoll,12
Pad to 11, 12, via transparent latch (fast)
Pad to 11, 12, via: transparent latch (with delay)
Clock (IK) toll, 12, (flip-flop)
Clock (IK) to 11, 12 (latch enable, active Low)
-6
-5
Min Max
Min Max
T plO
TpLi
TpOLI
TIKRI
TIKLI
Set-up Time (Note 3)
Pad to Clock (IK), fast
Pad to Clock (IK) with delay
T plCK
Hold Time (Note 3)
Pad to Clock (IK), fast
Pad to Clock (IK) with delay
T 1KP1
TplCKO
TIKPIO
OUTPUT
Propagation Delays
Clock (OK) to Pad
(fast)
Output (0) to Pad
(fast)
3-state to Pad begin hi-Z (fast)
3-state to Pad active and valid (fast)
4
8
26
8
8
3
7
24
7
7
Min Max Units
ns
ns
ns
ns
ns
7
25
6
24
ns
ns
1
-8
1
-8
ns
ns
7.5
TOKPOF
T OPF
TTSHZF
TTSONF
13
7
7
7
10
ns
ns
ns
ns
2
4
6
1.5
3
4.5
ns
ns
ns
9
9
Additional Delay
For medium fast outputs
For medium slow outputs
For slow outputs
Set-up and Hold Times
Output (0) to clock (OK) set-up time
Output (0) to clock (OK) hold time
TOOK
T oKO
8
0
6
0
ns
ns
Clock
Clock High or Low time
TCHlTCL
5
4
ns
Global SeVReset*
Delay from GSR net through Q to 11, 12
Delay from GSR net to Pad
GSRwidth
TRRI
T RPo
T MRW
14.5
18
21
13.5
17
18
ns
ns
ns
• Timing is based on the XC4QOS. For other devices see XACT timing calculator.
Notes: 1. Timing is measured at pin threshold, with SO pF external capacitive loads (incl. test fixture).
2. Voltage levels of unused (bonded and unbonded) pads must be valid logic levels. Each can be configured with the
internal pull-up or pull-down resistor or alternatively configured as a driven output or be driven from an external source.
3. Input pad setup times and hold times are specified with respect to the internal clock (IK). To calculate system setup time,
subtract clock delay (clock pad to IK) from the specified input pad setup time value, but do not subtract below zero.
Negative hold time means that the delay in the input data is adequate for the external system hold time to be zero,
provided the input clock uses the Global signal distribution from pad to IK.
2-70
CLB Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-3851 0/605. All devices are 100% functionally
tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing patterns. The
following guidelines reflect worst-case values over the recommended operating conditions. For more detailed, more precise, and more
up-to-date timing information, use the values provided by the XACT timing calculator and used in the simulator.
Description
Symbol
Combinatorial Delays
FIG inputs to XIY outputs
FIG inputs via H' to XN outputs
C inputs via H' to XIY outputs
Min Max
Initialization inputs (F1 ,F3) to COUT
CIN through function generators to XIY outputs
CIN to C our bypass function generators.
Sequential Delays
Clock K to outputs Q
Set-up Time before Clock K
FIG inputs
FIG inputs via H'
C inputs via H1
C inputs via DIN
C inputs via EC
C inputs via SIR, going Low (inactive)
CIN input via FIG'
CIN input via FIG' and H'
Min
6
T llO
T IHO
T HHO
CLB. Fast Carry Logic
Operand inputs (F1 ,F2,G1 ,G4) to COUT
Add/Subtract input (F3) to COUT
~5
-6
Speed Grade
Max
Min Max Units
8
7
4.5
7
5
ns
ns
ns
TOPCY
T ASCY
T 1NCY
7
5.5
8
ns
ns
TSUM
TSYp
8
2
6
4
6
1.5
ns
ns
ns
T CKO
5
3
ns
6
6
4.5
8
7
4
7
6
6
5
3
4
4.5
8
10
7.5
ns
ns
ns
ns
ns
ns
ns
ns
TICK
T IHCK
T HHCK
T DICK
T ECCK
T RCK
6
Hold Time after Clock K
FIG inputs
FIG inputs via H'
C inputs via H1
C inputs via DIN
C inputs via EC
C inputs via SIR, going Low (inactive)
TCKI
TCKIH
TCKHH
TCKDI
T CKEC
TCKR
0
0
0
0
0
0
0
0
0
0
0
0
ns
ns
ns
ns
ns
ns
Clock
Clock Hightime
Clock Low time
TCH
TCl
5
5
4.5
4.5
ns
ns
SeVReset Direct
Width (High)
Delay from C to Q
T RPW
5
Master SeVReseW
Width (High or Low)
Delay from Global SeVReset net to Q
T MRW
TRIO
21
TMRQ
• Timing is based on the XC4005. For other devices see XACT timing calculator.
2-71
4
9
8
ns
ns
31
ns
ns
18
33
II
XC4000A Logic Cell Array Family
CLB Switching Characteristic Guidelines (continued)
Testing of the switching parameters is modeled after testing methods specified by MIL-M-3851 0/605. All devices are 100% functionally
tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing patterns. The
following guidelines reflect worst-case values over the recommended operating conditions. For more detailed, more precise, and more
up-to-date timing information, use the values provided by the XACT timing calculator and used in the simulator.
CLB RAM OPTION
Description
Write Operation
Address write cycle time
Write Enable pulse width (High)
Address set-up time before beginning of WE
Address hold time after end of WE
DIN set-up time before end of WE
DIN hold time after end of WE
Read Operation
Address read cycle time
Data valid after address change
(no Write Enable)
Read Operation, Clocking Data into Flip-Flop
Address setup time before clock K
Read During Write
Data valid after WE going active
(DIN stable before WE)
Data valid after DIN
(DIN change during WE)
Read During Write, Clocking Data into Flip-Flop
WE setup time before clock K
Data setup time before clock K
Speed Grade
Symbol
Min
16 x 2
32 x 1
16x 2
32 x 1
16 x 2
32 x 1
16 x 2
32 x 1
16 x 2
32 x 1
both
Twc
TWCT
Twp
TWPT
TAS
TAST
TAH
TAHT
Tos
TOST
TOHT
9
9
5
5
2
2
2
2
4
5
2
16 x2
32 x 1
16 x2
32 x 1
T RC
T RCT
T ILO
T IHO
7
10
16 x2
32 x 1
TICK
TIHCK
6
16 x2
32 x 1
16 x 2
32 x 1
Two
TWOT
Too
TOOT
16 x 2
32 x 1
16 x 2
32 x 1
TWCK
TWCKT
TOCK
TOCKT
Note: Timing for the 16 x 1 RAM option is identical to 16 x 2 RAM timing
2-72
-5
-6
Max
Min Max
8
8
5.5
7.5
4.5
7
6
12
15
11
14
10
12
9
11
10
12
9
11
ns
ns
ns
ns
ns
ns
4.5
6
8
12
15
11
14
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4
4
2
2
2
2
4
5
2
8
Min Max Units
ns
ns
ns
ns
ns
ns
ns
ns
CLB RAM Timing Characteristics
ADDRESS
WRITE
WRITE ENABLE
DATA IN
READ
X,YOUTPUTS
I
READ, CLOCKING DATA INTO FLIP-FLOP
,,\.I----TICK_ _! _T C H _ !
CLOCK
XQ,YQ OUTPUTS
I~____________
------~I
VALID
(OLD)
READ DURING WRITE
Twp
WRITE ENABLE
DATA IN
(slabla during WE)
X,YOUTPUTS
DATA IN
(changing during WE)
NEW
VALID
(NEW)
X,YOUTPUTS
READ DURING WRITE, CLOCKING DATA INTO FLIP-FLOP
WRITE ENABLE
DATA IN
CLOCK
XQ,YQ OUTPUTS
X2640
2-73
XC4000A Logic Cell Array Family
2-74
XC4002A Pinouts
Pin
Description
PC 84 PQ100 VQ100 PG120
Bound
Scan
Pin
Description
PC 84 PQ100 VQ100 PGI20
Bound
Scan
Pin
Description
Bound
PC 84 PQ100 VQ100 PG120 Scan
VCC
2
92
89
G3
-
I/O
28
23
20
C9
92
-
-
-
-
L9
-
1/0 (A8)
3
93
90
Gl
26
SGCK2(IIO)
29
24
21
A12
9S
1/0 (06)
S8
S8
55
Ml0
IS7
160
110 (A9)
4
94
91
Fl
29
Ml
30
2S
22
Bll
98
110
S9
56
NIl
-
-
-
9S·
92·
El·
GND
31
26
23
Cl0
-
1/0 (OS)
S9
60
S7
M9
163
-
96·
93·
F2·
-
MO
32
27
24
Cll
101t
1/0 (C"SO)
60
61
S8
Nl0
166
-
62·
S9·
L8·
-
63·
60·
N9·
-
1/0 (Al0)
S
97
94
F3
32
VCC
33
28
2S
011
-
1/0 (All)
6
98
9S
01
35
M2
34
29
26
B12
102t
-
-
-
-
-
E2·
-
PGCK2(I/O)
35
30
27
C12
103
1/0 (04)
61
64
61
M8
169
I/O (AI2)
7
99
96
Cl
38
110 (HOC)
36
31
28
A13
106
1/0
62
6S
62
N8
172
1/0 (AI3)
8
100
97
02
41
-
66
63
M7
-
E3·
-
E,,·
GND
64
67
64
L7
-
Bl·
-
-
63
-
-
VCC
-
-
B13·
-
I/O
-
32
29
012
109
110(03)
6S
68
6S
N7
17S
1/0 (AI4)
9
1
98
C2
44
1/0 (1llC)
37
33
30
C13
112
1/0 (AS)
66
69
66
N6
178
SGCKI (A1S, 1/0)
10
2
99
03
47
1/0
38
34
31
E12
lIS
NS·
3
100
C3
1/0
39
3S
32
013
118
-
67·
11
-
70·
VCC
-
-
M6·
-
-
-
36·
33·
F,,·
-
1/0 (02)
67
71
68
L6
181
37·
34·
E13·
-
1/0
68
72
69
N4
164
GND
12
4
1
C4
-
PGCKI (A16, 1/0)
13
S
2
B2
SO
VO(AI7)
14
6
3
B3
53
1/0
40
38
3S
F12
121
1/0(01)
69
73
70
M5
187
-
-
-
-
AI·
I/O (ERR, INIT)
41
39
36
F13
124
10 (RClK.aulYIRDY)
70
74
71
N3
190
-
A2·
-
VCC
42
40
37
G12
7
4
C5
56
GND
43
41
38
GIl
-
-
-
-
15
-
M4·
1/0 (TOI)
-
L5·
-
1/0 (TCK)
16
8
S
B4
S9
110
44
42
39
G13
127
1/0 (DO, OIN)
71
75
72
N2
193
-
-
-
-
A3·
-
1/0
45
43
40
H13
130
SGCK4 (DOUT, VOl
72
76
73
M3
196
1/0 (TMS)
17
9
6
85
62
-
44·
41·
J13·
73
77
74
L4
18
10
7
A4
65
-
4S·
42·
H12·
-
CCLK
110
-
VCC
74
78
7S
L3
-
-
110
".
-
C6·
46
46
43
Hl1
133
TOO
75
79
76
M2
AS·
-
1/0
8·
1/0
47
47
44
K13
136
GND
76
80
77
K3
-
19
12
9
B6
68
1/0
48
48
4S
J12
139
1/0 (AO, WS)
77
81
78
L2
2
1/0
20
13
10
A6
71
1/0
49
49
46
L13
142
PGCK4 (IIO,Al)
78
82
79
Nl
5
GND
21
14
11
B7
K12·
-
12
C7
-
-
Jl,·
-
-
-
-
-
MI·
15
-
-
22
-
-
VCC
-
-
1/0
23
16
13
A7
74
I/O
SO
SO
47
M13
145
1/0 (CS1, A2)
79
83
80
K2
8
1/0
24
17
14
A8
77
SGCK3(1/0)
51
51
48
L12
148
110 (A3)
80
64
81
Ll
11
-
-
18·
IS·
A9·
-
GND
S2
S2
49
Kll
-
-
-
B8·
-
DONE
53
53
50
Ll1
1/0
25
19
16
C8
80
VCC
S4
54
SI
Ll0
1/0
26
20
17
Al0
83
PROG
55
55
S2
M12
-
1/0
27
21
18
89
86
1/0 (07)
56
56
53
MIl
I/O
-
22
19
All
89
PGCK3 (1/0)
57
57
S4
N13
-
-
-
-
Bl0·
-
-
-
-
-
N12·
-
-
* Indicates unconnected package pins.
t Contributes only one bit (j) to the boundary scan register.
Boundary Scan B~ 0 = TOO.T
Boundary Scan Bit 1 = TOO.O
Boundary Scan Bit 199 = BSCANT.UPO
2-75
J3·
110 (A4)
81
85
82
J2
14
1/0 (A5)
82
86
83
Kl
17
-
-
87"
84·
H3·
88·
85·
Jl·
-
151
110 (A6)
83
89
86
H2
20
154
1/0 (A7)
84
90
87
HI
23
GND
1
91
88
G2
-
II
XC4000A Logic Cell Array Family
XC4003A Pinouts
Pin
Description
vee
VO(A8)
110 (A9)
Bound
PC84
2
3
4
VQ100
89
90
91
92
93
PQ100
92
93
94
110
110
-
110 (Al0)
110 (All)
5
6
94
-
-
110 (AI2)
1/0 (AI3)
7
8
96
99
100
-
-
95
97
95
96
97
98
PG120
G3
Gl
Fl
El
F2
F3
01
E2'
Cl
02
E3'
Bl'
C2
03
C3
-
-
-
VO(AI4)
GNO
PGCKI (AI6,1I0)
VO (AI7)
9
10
11
12
13
14
98
99
100
1
2
3
-
-
-
1
2
3
4
5
6
-
-
A2'
110 (TOI)
VO (TCK)
15
16
4
5
7
8
-
-
-
-
VO (TMS)
1/0
1/0
17
18
6
7
9
10
-
-
-
19
20
21
22
23
24
8
9
10
11
12
13
14
15
11
12
1.3
14
15
16
17
18
-
-
-
25
26
27
16
17
18
19
19
20
21
22
C5
B4
A3'
B5
A4
C6
A5
B6
A6
B7
C7
A7
A8
A9
B8
C8
Al0
B9
All
Bl0'
C9
A12
Bll
Cl0
Cl1
011
B12
C12
A13
B13'
Ell'
012
C13
E12
013
Fll
E13
F12
F13
G12
SGCKI (AI5,1/0)
vee
110
VO
110
GND
vee
110
110
110
110
1/0
110
110
110
-
-
-
-
-
110
SGCK2(1/0)
Ml
GND
MO
28
29
30
31
32
33
vee
M2
PGCK2(1I0)
110 (HOC)
-
110
110 ([DC)
110
110
110
110
110
110 (ERR, lNif)
vec
34
35
36
37
38
39
-
40
41
42
-
-
-
-
20
21
23
24
25
26
27
28
23
24
25
26
27
28
29
30
31
-
-
29
30
31
32
33
34
35
36
37
32
22
33
34
35
36
37
38
39
40
Pin
Description
GND
Scan
-
110
1/0
110
32
35
38
41
44
47
110
110
110
110
110
-
50
53
-
-
110
56
59
-
SGCK3(1/0)
GND
DONE
C4
-
vce
B2
B3
AI'
62
!'ROO
65
110(07)
PGCK3(1I0)
-
-
Bound
PC84
43
44
45
-
46
47
48
49
-
50
51
52
53
54
55
56
57
-
68
71
110(06)
58
-
110
-
74
1/0(05)
110 (CSO)
59
60
1/0
110
-
77
80
83
86
89
1/0(04)
110
vee
-
-
GND
1/0(03)
1I0(l'iS)
92
95
98
101
104
107
110
113
116
119
122
-
-
-
47
48
49
50
51
52
53
54
50
-
-
55
56
57
58
59
60
61
62
63
58
59
60
61
62
63
64
65
-
187
190
-
193
196
199
202
205
208
211
214
217
220
223
226
229
232
235
238
-
68
69
70
71
71
72
73
74
-
-
-
-
l5'
N2
M3
L4
L3
M2
K3
241
244
L2
2
5
-
-
77
78
79
75
76
77
78
79
80
81
82
-
-
110 (CS1, A2)
79
80
81
82
80
81
82
83
-
84
85
83
84
86
87
88
110 (A4)
110 (A5)
110
1/0
110 (A6)
110 (A7)
GND
-
72
73
74
75
76
-
110 (A3)
-
71
72
73
74
75
76
-
2-76
-
-
-
, Indicates unconnected package pins.
t Contribules only one bit (.i) to the boundary scan register.
Boundary Scan Bit 0 ~ TOO.T
Boundary Scan B~ 1 ~ TOO.O
Boundary Scan B~ 247 ~ BSCANT.UPO
181
184
67
68
69
70
-
-
65
66
67
68
69
70
157
160
163
166
169
172
175
178
-
TOO
GND
1/0 (AO, WS)
PGCK4 (Al,I/O)
133
136
139
142
145
148
151
154
64
Scan
110
110(02)
110
110(01)
110 (RCLK-BUSY/ROY)
126T
127
130
-
51
52
53
54
55
56
57
PG120
GIl
G13
H13
J13
H12
Hl1
K13
J12
L13
K12'
Jll'
M13
L12
Kll
Ll1
Ll0
M12
MIl
N13
N12'
L9'
Ml0
NIl
M9
Nl0
L8
N9
M8
N8
M7
L7
N7
N6
N5
M6
L6
N4
M5
N3
M4'
110
vee
-
61
62
63
64
65
66
46
PQ100
41
42
43
44
45
46
47
48
49
66
67
110(00, DIN)
SGCK4 (OOUT, 110)
CCLK
125
-
VQ100
38
39
40
41
42
43
44
45
78
-
1
77
83
64
85
86
87
88
89
90
91
Nl
Ml'
J3'
K2
Ll
J2
Kl
H3
Jl
H2
HI
G2
-
-
8
11
14
17
20
23
26
29
-
XC4004A Pinouts
Pin
Description
PC84 TQt44 PQt60 PG120
Bound
Scan
Pin
Description
PC84 TQI44 PQ160 PG120
Bound
Scan
Pin
Description
PC84 TQI44 PQ160 PG120
vee
2
128
142
G3
-
110
28
32
36
C9
140
-
-
-
90-
110 (A8)
110 (A9)
3
129
143
Gl
38
SGCK2(V0)
29
33
37
A12
143
GND
-
4
130
144
Fl
41
Ml
30
34
38
Bll
146
-
91
92-
VO
1/0
-
131
145
El
44
GND
31
35
39
Cl0
-
-
-
81
8283-
93-
-
132
146
F2
47
MO
32
36
40
Cll
149t
1/0 (D5)
59
84
VO(Al0)
5
133
147
F3
50
vee
33
37
41
Dll
-
I/O(CSO)
60
85
110 (All)
6
53
M2
34
38
42
B12
150t
1/0
-
148
149-
Dl
-
134
135-
PGCK2(I/O)
35
C12
151
150-
VO(HDC)
36
39
40
43
136-
-
44
A13
154
1/0
110 (D4)
61
137
151
E2
1/0
-
41
45
B13
157
1/0
62
42
46
Ell
160
vee
43
47
D12
163
GND
37
44
48
49-
C13
166
-
-
-
-
-
-
-
-
-
-
152-
-
153-
-
-
110 (AI2)
7
138
154
Cl
56
1/0
1/0 (CDC)
110 (AI3)
8
139
155
D2
59
-
110
110
-
140
156
E3
62
-
-
-
141
157
Bl
65
GND
45
46-
51
52-
GND
VO
50-
Bound
Scan
-
-
94
M9
253
95
Nl0
256
86
96
L8
259
87
97
N9
262
86
98
M8
265
89
99
N8
268
63
90
100
M7
64
91
101
L7
-
1/0 (D3)
65
92
102
N7
271
VO (AS)
1/0
66
103
104
N6
N5
274
-
93
94
-
95
105
M6
280
169
1/0
VO(D2)
67
96
106
L6
283
172
1/0
68
97
N4
286
-
-
98-
107
108-
-
-
-
99-
109-
-
110
111-
-
-
-
-
277
110 (AI4)
9
142
158
C2
68
-
-
SGCKI (AI5, 110)
10
143
159
D3
71
-
47-
53-
vee
-
-
11
144
160
C3
48
54
E12
12
1
1
C4
39
49
55
D13
175
178
PGCKI (AI6, 1/0)
13
2
2
B2
74
-
50
56
Fl1
181
GND
-
100
110 (AI7)
14
3
3
B3
77
110
VO
110
VO
38
GND
-
-
51
57
E13
184
-
110
110
-
4
4
AI
80
40
52
58
F12
187
-
-
112-
-
-
5
5
A2
83
110
VO (ERR, INIT)
-
41
53
59
F13
190
110 (Dl)
69
101
113
M5
289
110 (TDI)
15
6
6
C5
86
vee
42
54
60
G12
110 (RCLK-BUSYIRDY)
70
102
114
N3
292
110 (TCK)
16
7
B4
89
GND
43
55
61
GIl
1/0
115
M4
295
-
-
-
-
)/0
44
56
62
G13
193
VO
-
103
-
7
8-
-
104
116
L5
298
45
57
63
H13
196
VO (DO, DIN)
71
105
117
N2
301
-
64
J13
199
SGCK4 (DOUT, 110)
72
106
118
M3
304
-
-
59
65
H12
202
CCLK
73
107
119
L4
-
46
60
66
Hl1
205
vee
74
108
120
L3
VO(TMS)
110
110
VO
110
58
-
-
1/0
VSS
47
61
62-
67
68-
K13
208
TOO
75
109
121
M2
110
-
GND
76
110
122
K3
63-
69-
-
-
111
123
L2
2
70
71-
1/0 (AO,WSj
PGCK4 (1/O,Al)
77
64
-
-
78
112
124
Nl
5
211
1/0
113
125
Ml
8
214
1/0
-
114
126
J3
K2
11
14
L1
17
-
-
9-
8
9-
10
11-
10-
12-
-
17
11
13
B5
92
18
12
14
A4
95
110
110
-
13
15
C6
98
-
-
14
16
AS
101
GND
-
110
19
15
17
66
104
110
20
16
18
A6
107
-
-
-
72-
GND
21
17
19
67
-
110
48
65
73
J12
217
110 (CS1, A2)
79
115
127
vee
22
18
20
C7
-
VO
49
66
74
L13
220
VO(A3)
80
110
23
19
21
A7
110
1/0
67
75
K12
223
24
20
22
A8
113
110
68
76
Jl1
226
-
-
130-
-
21
23
A9
116
1/0
50
69
77
M13
229
GND
110
-
22
24
B8
119
SGCK3(VO)
51
70
78
L12
232
-
-
128
129-
VO
110
-
116
117118
119-
132-
110
110
25
23
25
C8
122
GND
52
71
79
Kl1
26
26
Al0
125
DONE
53
72
80
Ll1
-
27*
28-
-
vee
54
73
81
Ll0
PROG
55
74
82
M12
110 (D7)
56
75
83
MIl
235
-
-
-
PGCK3 (VO)
57
76
84
N13
-
31-
-
-
GND
-
24
25-
-
110
77
85
N12
110
27
28
32
B9
128
1/0
78
86
110
110
-
29
33
All
131
34
Bl0
134
1/0 (D6)
110
79
30
80
31
35
-
137
VO
'I\"
-
2627
29
30-
A3
-
58
Indicates unconnected package pins.
t Contributes only one bit (.i) to the boundal)' scan register.
Boundal)' Scan Btl 0 = TDO.T
Boundal)' Scan Bit 1 = TDO.O
Boundal)' Scan Bit 307 = BSCANT.UPD
2-77
-
-
120-
133-
-
VO(A4)
81
121
134
J2
20
110 (AS)
82
122
23
-
-
135
136-
Kl
-
-
-
123
137
H3
26
29
131
-
238
1/0
1/0
-
124
138
Jl
241
VO(A6)
83
125
139
H2
32
L9
244
1/0 (A7)
84
126
140
HI
35
87
Ml0
247
GND
1
127
141
G2
-
88
89-
NIl
250
-
II
XC4000A Logic Cell Array Family
XC4005A Pinouts
Pin
Description
vec
110 (A8)
110 (A9)
I/O
I/O
-
-
Bound
PC84
2
3
4
-
-
PQI60
142
143
144
145
148
-
-
-
133
134
135
136
137
147
148
149
150
151
-
110 (AI 0)
110 (All)
YO
110
GND
-
-
-
-
-
-
110 (AI2)
110 (AI3)
7
8
138
139
152
153
154
155
-
-
140
141
142
143
144
156
157
158
159
160
110
VO
VO(AI4)
SGCKI (A 15, 110)
vee
5
6
TQI44
128
129
130
131
132
9
10
11
-
-
GND
12
-
-
-
1
1
-
-
PGCKI (AI6,110)
110 (AI7)
110
YO
13
14
-
-
2
3
4
5
2
3
4
5
1/0 (TOI)
VO (TCK)
15
16
-
-
-
GNO
vo
110
110 (TMS)
VO
-
110
110
110
I/O
GND
vee
110
110
110
110
-
110
110
110
110
GND
110
VO
YO
-
17
18
-
19
20
21
22
23
24
25
26
-
27
-
-
-
6
7
6
7
8
9
-
8
9
10
11
12
-
10
11
12
13
14
-
-
13
14
15
16
17
18
19
20
21
22
15
16
17
18
19
20
21
22
23
24
23
24
25
26
27
25
26
27
28
29
-
-
-
28
29
30
-
30
31
32
33
34
PQ208
183
184
185
188
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
1
2
3
4
5
6
7
-
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
PG156
H3
HI
Gl
G2
G3
-
Fl
F2
El
E2
F3
44
47
50
53
-
E3
Cl
68
71
-
-
C2
03
Bl
B2
C3
74
71
-
C4
-
B3
AI
A2
C5
-
-
GND
1/0
110
110
1/0
-
110
I/O
VO
YO (ERR, INIT)
B4
98
vee
101
GND
110
VO
VO
VO
C6
B5
B6
A5
C7
-
97
A6
A7
A8
C8
B8
C9
B9
A9
Bl0
-
34
35
36
37
38
-
A12
B12
A13
A14
-
104
107
110
113
VO
110
110
110
GND
-
-
116
119
122
125
-
128
131
134
137
-
164
167
170
173
C14
B15
B16
014
C15
174
175
178
181
-
-
-
B13
B14
A15
C13
A16
-
83
-
-
48
47
48
49
38
A3
A4
-
-
36
37
32
-
-
PGI56
C12
32
33
-
-
PQ208
45
-
VO
110
110(=)
88
89
92
95
PQI60
35
28
29
30
31
vee
-
-
TQI44
31
-
M2
PGCK2(IIO)
110 (HOC)
VO
80
Bound
PC84
110
SGCK2(IIO)
Ml
GND
MO
-
56
59
62
65
D2
-
Dl
Cl0
Al0
All
Bll
Cll
39
40
41
42
43
44
-
-
-
Pin
Description
110
Scan
-
33
34
35
36
37
-
-
34
35
37
38
39
40
41
-
-
45
51
52
46
48
50
-
47
48
49
54
55
-
-
-
50
51
52
53
54
55
56
57
56
57
40
41
42
43
44
45
38
39
-
-
46
47
-
58
59
-
53
58
59
60
61
62
63
64
65
-
60
66
61
62
63
64
67
68
69
70
-
-
-
-
-
110
110
I/O
110
110
SGCK3(110)
GND
48
49
65
66
67
68
69
70
71
71
72
73
74
75
76
71
78
79
80
50
51
52
-
-
53
72
-
-
-
-
vce
-
-
54
73
-
-
-
-
!'ROO
55
56
57
74
75
76
77
82
83
84
85
-
VO (07)
PGCK3(11O)
110
152
155
158
110(06)
1/0
2-78
41
42
43
44
45
49
-
* Indicates unconnected package pins.
Contributes only one bit (.i) to the boundal)/ scan register,
-
-
DONE
t
-
48
47
-
-
38
39
40
42
43
44
140
143
146
149
-
-
-
-
58
81
-
50
51
52
53
54
55
56
57
58
59
-
60
61
62
63
64
65"
66
67
68
69
70
71
72
73
74
75
76
71
78
79
80
81
62
83
84
85
88
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
-
-
015
E14
C16
E15
016
-
Scan
161
-
-
184
187
190
-
F14
F15
E16
F16
G14
193
196
199
202
-
-
GIS
G16
H16
H15
H14
J14
J15
J16
K16
K15
205
208
211
214
K14
L16
M16
L15
114
229
232
235
238
-
-
N16
M15
P16
M14
N15
P15
N14
R16
P14
R15
-
-
217
220
223
226
-
241
244
247
250
253
256
-
-
-
R14
T16
T15
R13
259
262
265
P13
-
-
-
-
-
-
78
79
86
87
112
113
P12
T14
268
271
XC4005A Pinouts (continued)
Pin
Bound
Descriptions
PC84
VO
-
GND
VO
110
1/0(05)
-
-
-
81
82
-
110 (CSO)
-
-
110
VO(04)
VO
vee
GND
VO(03)
IIO(RS)
1/0
VO
-
1/0(02)
110
VO
VO
GND
-
-
-
-
61
62
63
64
65
66
-
-
91
92
93
94
95
83
84
85
-
-
86
87
88
89
90
91
92
93
96
97
98
99
100
101
102
103
104
105
94
95
-
-
-
-
-
96
97
98
99
100
106
107
108
109
110
-
-
-
-
-
-
1/0(01)
69
70
-
-
67
68
-
1/0 (RCLK-BUSY/ROy)
1/0
PQI60
88
8990
-
-
59
60
1/0
TQI44
80
-
-
111
112
113
114
115
-
101
102
103
PQ208
114
115
116
117
118
119
120
121
122
123
124125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143144
145
146
147
148
149
PGI56
T13
R12
T12
Scan
274
-
-
Pl1
Rl1
Tl1
Tl0
Pl0
277
280
283
286
-
-
RIO
T9
R9
P9
R8
289
292
295
298
P8
T8
T7
T6
R7
-
301
304
307
310
-
-
P7
T5
R6
T4
P6
313
316
319
322
-
-
-
-
-
R5
-
-
T3
P5
R4
325
328
331
-
-
-
-
-
-
-
1/0
VO(OO, DIN)
SGCK4 (OOUT, 110)
CCLK
71
72
73
74
104
105
106
107
108
116
117
118
119
120
R3
P4
T2
R2
P3
334
337
340
-
-
-
-
-
-
-
75
76
77
78
109
110
111
112
113
150
151
152
153
154
155
156
157
158
159
160
161
162
163
Tl
N3
-
Rl
P2
N2
2
5
8
vee
-
-
TDO
GND
1/0 (AO,WS)
PGCK4 (AI ,VOl
VO
VO
VO (CS1,A2)
VO(A3)
-
-
79
80
-
121
122
123
124
125
-
-
-
164
165
168
167
168
169
170
171
M3
PI
Nl
M2
Ml
11
14
17
-
-
L3
-
172
173
174
175
176
177
178
179
180
181
182
L2
L1
20
23
26
29
118
131
1/0
1/0
-
110 (A4)
81
82
119
120
121
122
132
133
134
135
-
-
-
-
-
-
-
-
123
124
125
126
127
136
137
138
139
140
141
1/0
-
VO(A6)
110 (A7)
GND
63
84
1
• Indicates unconnected package pins.
Boundary Scan Bit 0 = TOO,T
-
-
-
-
-
126
127
128
129
130
GND
VO
-
-
-
1/0 (A5)
-
114
115
116
117
--
-
-
K3
K2
-
-
-
Kl
Jl
J3
32
35
38
41
H2
-
Boundary Scan Bit 1 = TOO,O
Boundary Scan Bit 343 = BSCANT,UPO
2-79
II
XC4000A Logic Cell Array Family
For a detailed description of the device architecture, see page 2-9.
For a detailed description of the configuration modes and their timing, see pages 2-32 through 2-55.
For detailed lists of package pinouts, see pages 2-74 through 2-78.
For package physical dimensions, see Section 4.
Ordering Information
Example:
XC4005A-5 PQ160C
""'100 Type ~
Speed Grade
r--T._~,"re R.",.
Number of Pins
Package Type
Component Availability
PINS
CODE
XC4002A
XC4003A
XC4004A
B = MIL·STD·883C Class B
Parentheses indicates future product plans
2-80
XC4000H
High 1/0 Count
Logic Cell Array Family
Preliminary Product Specifications
Features
Device
• Third-generation Field-Programmable Gate Arrays
- Very high number of I/O pins
- Abundant flip-flops
- Flexible function generators
- On-chip ultra-fast RAM
- Dedicated high-speed carry-propagation circuit
- Wide edge decoders
- Efficient implementation of multi-level logic
- Hierarchy of interconnect lines
- Internal 3-state bus capability
- Eight global low-skew clock or signal distribution
network
- IEEE 1149.1-compatible boundary-scan logic support
- Programmable output slew rate with (two modes
including Soft Edge)
Approximate Gate Count
Number of lOBs
CLB Matrix
Number of CLBs
Number of Flip-Flops
Max Decode Inputs
(per side)
Max RAM Bits
XC4003H
XC4005H
3,000
160
10 x 10
100
200
30
5,000
192
14 x 14
196
392
42
3,200
6,272
interconnected by a powerful hierarchy of versatile routing
resources, and surrounded by a perimeter of programmable InpuVOutput Blocks (lOBs).
The XC4000H family is intended for I/O-intensive applications. Compared to the XC4000, the XC4000H devices
have almost double the number of lOBs and I/O pins, and
offer a choice of CMOS- or TTL-level outputs and input
thresholds, selectable per pin. The XC4000H outputs sink
24 mA and offer improved 3-state and slew-rate control.
• Per-pin individually configurable input threshold and
output high level, either TTL or CMOS
- Programmable input pull-up or pull-down resistors
• Flexible Array Architecture
- Programmable logic blocks and I/O blocks
- Programmable interconnects and wide decoders
The devices are customized by loading configuration data
into the internal memory cells. The FPGA can either
actively read configuration data out of external serial or
byte-parallel PROM (master modes), or the configuration
data can be written into the FPGA (slave and
peripheral modes).
• SUb-micron CMOS Process
- High-speed logic and interconnect
- Low power consumption
• Configured by Loading Binary File
- Unlimited reprogrammability
- Six programming modes
The XC4000H family.is supported by the same powerful
and sophisticated software as the XC4000 family, covering
every aspect of design: from schematic entry, to simulation, to automatic block placement and routing of interconnects, and finally to the creation of the configuration
bit stream.
• XACT Development System runs on '386f486-type PC,
NEC PC, Apollo, Sun-4, and Hewlett Packard 700
Series
- Interfaces to popular design environments like
Viewlogic, Mentor Graphics and OrCAD
- Fully automatic partitioning, placement and routing
- Interactive design editor for design optimization
- 288 macros, 34 hard macros, RAM/ROM compiler
Description
The XC4000 family of Field-Programmable Gate Arrays
(FPGAs) provides the benefits of custom CMOS VLSI,
while avoiding the initial cost, time delay, and inherent risk
of a conventional masked gate array.
The XC4000 family provides a regular, flexible, programmable architecture of Configurable Logic Blocks (CLBs),
2-81
Since Xilinx FPGAs can be reprogrammed an unlimited
numberof times, they can be used in innovative designs
where hardware is changed dynamically, or where hardware· must be adapted to different user applications.
FPGAs are ideal for shortening the design and development cycle, but they also offer a cost-effective solution for
production rates well beyond 1000 systems per month.
For a detailed description of the device features, architecture, configuration methods and pin descriptions, see
pages 2-9 through 2-45.
II
XC4000H High VO Count Logic Cell Array Family
XC4000H Compared to XC4000
prevents potential ground-bounce problems when all
outputs turn on simulataneously. A few nanoseconds
later, each output assumes the current-sink capability
determined by its configuration. This soft wake-up operation is transparent to the user.
For readers already familiar with the XC4000 family, here
is a concise list of the major new features in the XC4000H
family.
• Number of lOBs is, roughly, doubled compared to the
XC4000.
Architectural Overview
• Output slew-rate control is significantly improved.
Except for the 1/0 structure, the XC4000H family is identical to the original XC4000 family. A matrix of Configurable
Logic Blocks is interconnected through a hierarchy of
flexible routing resources. The powerful system-integration features of the XC4000 family, such as on-chip RAM,
dedicated fast carry, and wide decoders, are retained in
the XC4000H family.
Resistive Load means a strong pull-down all the way to
ground, capable of sinking 24 rnA continuously. If many
outputs switch simultaneously, the resulting ground
bounce might be objectionable.
Capacitive Load, or SoftEdge, means a more sophisticated pull-down that decreases in strength as it approaches ground. It can only sink 4 rnA at VOL which is
irrelevant when driving capacitive loads. The benefit is
a substantial reduction in ground bounce when several
outputs switch simultaneously.
The XC4000H family almost doubles the number of input!
output pins compared to the XC4000, an attractive feature
for I/O-intensive applications. The output drivers were
redesigned to be more powerful and more flexible.
In the XC4000, limiting the slew rate of the output
reduces ground bounce, but also introduces a significant additional delay. In the XC4000H, the additional
delay in the capacitive-load mode is usually insignificant.
Input/Output Blocks (lOBs)
The lOBs form the interface between the internal logic and
the 1/0 pads of the XC4000H device. Each lOB consists of
a programmable output section that can drive the pad, and
a programmable input section, that can receive data from
the pad. Aside from being connected to the same pad, the
input and output sections have nothing else in common.
• All input and output flip-flops have been eliminated in
the XC4000H family. Use the CLB flip-flops instead.
• Outputs can sink 24 rnA, guaranteed at V = 0.5 V,
compared to the 12 rnA at 0.4 V of the xC48bo family.
Input
In XC4000H devices, there are no input flip-flops.
• Number of decoder inputs per side
The input section receives data from the pad. Each input
can be configured individually with TTL or CMOS input
thresholds. As a configuration option, the input can be
either inverted or non-inverted, before it is made available
to the internal logic.
• Each output may be individually configured as one of
the following.
- TTL-compatible (like the XC4000) that uses
n-channel transistors for both pull-down and pull-up,
Pad
Each 1/0 pad can be configured with or without a pull-up or
pull-down resistor, independent of the pin usage.
- A totem-pole output structure with reduced VOH'
- CMOS-compatible (like the XC2000 and XC3000)
that means n-channel pull-down and p-channel pullup with V oHclose to the Vcc rail.
Boundary Scan
TheXC4000H lOBs have the same lEE 1149.1boundaryscan capabilities as the lOBs in the original XC4000.
• Each input can individually be configured for either TTLcompatible threshold (1.2 V) or for CMOS-compatible
threshold (Vcd2). Each input can be configured to be
inverting or non-inverting.
Output
In an XC4000H lOB, there is no output flip-flop. The output
section receives data and 3-state control information from
the CLB interconnect structure.
• Any combination of programmable input and output
levels on any 1/0 pin is possible, even the dubious
combination of TTL output and CMOS input on the
same 1/0 pin.
• Output 3-state operation is controlled by a two-input
multiplexer.
Under configuration control, the data can be inverted or
non-inverted. The output driver assumes one of the following states.
• The first activation of outputs after the end of the
configuration process, as they change from 3-state to
their active level, is always in the SoftEdge mode. This
- Permanently disabled, making the pad an input only
pad
- 3-state controlled from the internal logic
2-82
There are two potential sources of the 3-state-control
information, selected by a multiplexer. The output of the
multiplexer driving the 3-state control can be inverted as a
configuration option. The signal can be active High 3-state,
which is identical to the more popular connotation of
active-low Output Enable, or it can be active-High Output
Enable, which is identical to active low 3-state.
When the output is configured as CMOS-compatible, an
additional p-channel transistor pulls the output towards the
Vcc rail. This results in an unloaded rail-to-rail signal
swing, ideal for systems that use CMOS input thresholds.
(XC2000 and XC3000 devices have only CMOS-level
outputs).
Each output can be configured for either of two slew-rate
options, which affect only the pull-down operation. When
configured for resistive load, the pull-down transistor is
driven hard, resulting in a practically constant on-resistance of about 10 Q. This results in the fastest High-to-low
transition, and the capability to sink 24 mA with a voltage
of 500 mV. When many outputs switch High to low
simultaneously, especially when they are discharging a
capacitive load, this configuration option might result in
excessive ground bounce.
Each output can be individually configured as either TTlor CMOS-compatible. A TTL-compatible output uses nchannel transistors for both pull-down and pUll-up. As a
result, the output High voltage, VOH' is at least one threshold voltage drop below Vcc' Depending on the load current, this means a voltage drop of 1.0 to 2.4 V. In a system
using TTL input thresholds of 1.2 V, this lower output
voltage results in shorter delays when switching from High
to low, and thus a better delay balance between the two
signal directions. The smaller signal amplitude also generates less noise. The reduction in High-level noise margin
is irrelevant because it is still much better than the lowlevel noise margin. TTL-level outputs are, therefore, the
best choice for systems that use TTL-level input thresholds. (XC4000 and XC4000A devices have only TTL-level
outputs and have only TTL-level input thresholds).
When configured for capacitive load, or SoftEdge, the
High-to-low transition starts as described above, but the
drive to the pull-down transistor is reduced as soon as the
output voltage reaches a value around 1 V. This results in
a higher resistance in the pull-down transistor, a slowing
down of the falling edge, and a significantly reduced
ground bounce.
OUTPUT
SLEW
RATE
a,-StateTS
PULL
DOWN
PULL
UP
-~~~--JL./--I-I
INVERT
OUTPUT
OuputData
a
Boundary Scan
{
a. Capture
o· Update _ - - - - - '
INPUT
Input Data 1 11
-------..---1
Input Data 212 - - - - - '
I- Update
Boundary Scan {
I-Capture _ - - - - - - - '
X3213
Figure 1. XC4000H Input/Output Block
2-83
II
XC4000H High 110 Count Logic Cell Array Family
Slew-Rate Control
The XC4000H outputs use a novel, patent-pending
method of slew-rate control that reduces ground bounce
without any significant delay penalty. Each output is configured with a choice between two slew-rate options. Both
options reduce the positive ground bounce that occurs
when the output current is turned on. They differ in the way
the output current is turned off.
• The slew-rate-limited default mode is called capacitive,
or SoftEdge. At the beginning of a High-to-Low transition, the pull-down transistor is gradually turned on, and
kept fully conductive until the output voltage has
reached +1 V. The pull-down transistor is then gradually
turned off, so that it finally has an on-resistance of about
1000, low enough to sink 4 mA continuously. Gradually
turning off the sink current reduces the max value of
current change (di/dt) that is normally responsible for
the negative voltage spike over the common ground
inductance (bonding wires), called ground bounce.
Thecapacitive, orSoftEdge, mode is the bestchoice for
capacitivelyloadedoutputs, orforoutputs requiring less
than 4 mA of dc sink current
The following figures show output rising and falling edges
when one output drives different loads. The tests were
performed on a multi-ground-plane test PC board, manufactured by Urban Instruments (Encino, CA). Measurements were done with a Tektronix TDS540 digital storage
oscilloscope. The figures below are unedited files from
these measurements, the time scale is2 nsldivision.
The upper trace in each figure shows a second· output
driven from the same internal signal, but unloaded. It acts
as a timing reference, and triggers the oscilloscope.
Resistive mode and capacitive mode transitions start with
practically the same delay from the internal logic.
Resisitive mode falls faster, and has more undershoot;
capacitive mode rises slightly faster. For a 200-0 pull-up,
330-0 pull-down termination, only resisitive mode is
meaningful. A TTL-output with a 1000-0 pull-up, 150-pF
termination has a slow (150 ns) final rise time that extends
outside the 10-ns timing window of these figures.
Trace A shows Resistive mode with CMOS outputs
Trace B shows Resistive mode with TTL outputs
Trace C shows Capacitive mode with CMOS outputs
Trace 0 shows Capacitive mode with TTL outputs
• The non-slew-rate limited mode is called resistive. At
the beginning of a High-to-Low transition, the pull-down
transistor is gradually turned on, and kept fully conductive as long as the output data is a logic Low. The pulldown transistor has an impedance of <20 0, capable of
sinking 24 mA continuously.
Summary
Use resistive mode for applications that require >4 mA of
dc sink current, and for heavy capacitive loads when they
must be discharged fast. Use capacitive mode for all other
applications, especially for light capacitive loads
(50 to 200 pF) and for all timing-uncritical outputs that
require <4 mA dc current. The Low-to-High transition is not
affected by the choice of slew-rate mode.
Resisitive mode is required for driving terminated transmission lines with 4 to 24 mA of dc sink current. The
abrupt current change when the output voltage reaches
zero causes a voltage spike overthe ground inductance
(bonding wire) and can result in objectionable ground
bounce when many outputs switch High-to-Low simultaneously.
ov
2
Figure 2. Falling Edge, 50 pF Load
Figure 3. Rising Edge, 50 pF Load
2-84
ov
ov
1
±
ov
2
.
2
ov
n5
Figure 4. Falling Edge, 2001330 n, 50 pF Load
I
Figure 5. Rising Edge, 2001330 n, 50 pF Load
ov
ov
2
Figure 6. Falling Edge, 200/330 n, 150 pF Load
Figure 7. Rising Edge, 200/330 n, 150 pF Load
ov
2
2~t;;:;::===~":":
Figure 8. Falling Edge, 1000 n, 150 pF Load
Figure 9. Rising Edge, 1000 n, 150 pF Load
2-85
XC4000H High 110 Count Logic Cell Array Family
Absolute Maximum Ratings
Units
Vee
Supply voltage relative to GND
-0.5 to 7.0
V
VIN
Input voltage with respect to GND
-0.5 to 7.0
V
VTS
Voltage applied to 3-state output
-0.5 to 7.0
V
TSTG
Storage temperature (ambient)
-65 to + 150
°C
TJ
Junction temperature
+ 150
°C
Note:
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device.
These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those listed under Recommended Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for
extended periods of time may affect device reliability.
Operating Conditions
Vee
Supply voltage relative to GND
Commercial
Supply voltage relative to GND
Industrial
Supply voltage relative to GND
Military
Min
Max
Units
4.75
5.25
V
-40°C to 85°C
4.5
5.5
V
-55°C to 125°C
4.5
5.5
V
Vee
V
100%
Vee
O°C to 70°C
VIH
High-level input voltage for TTL threshold
2.0
VIH
High-level input voltage for CMOS threshold
VIL
Low-level input voltage for TTL threshold
0
0.8
V
VIL
Low-level input voltage CMOS threshold
0
20%
Vee
Min
Max
Units
70%
DC Characteristics Over Operating Conditions
=-4.0 mA
VOH
High-level output voltage, TTL option @ 10H
VOH
High-level output voltage, CMOS option @ IOH
VOL
Low-level output voltage @ 10L
leeo
Quiescent LCA supply current (Note 2)
IlL
Leakage current
GIN
Input capacitance (sample tested)
lAIN
Pad pull-up (when selected) @ VIN
IALL
Horizontal Long Line pull-up (when selected) @ logic Low
=24
=-1
2.4
mA
V cc"" 0.5
mA, Vee max (Note 1)
V
0.5
V
10
mA
+10
~
15
pF
0.02
0.20
mA
0.2
2.5
mA
-10
=OV (estimate)
V
Note: 1. XC4003H-with 50% of the outputs simultaneously sinking 24 mAo XC4005H-with 33% of the outputs simultaneously sinking 24 mAo
2. With no output current loads, no active input or long line pull-resistors, all package pins at V cc or GND, and the LCA configured with
a MakeBits tie option.
2-86
I:XILINX
Preliminary Wide Decoder Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-3851 0/605. All devices are 100% functionally
tested. Since many intemal timing parameters cannot be measured directly, they are derived from benchmark timing patterns. The
following guidelines reflect worst-case values over the recommended operating conditions. For more detailed, more precise, and more
up-to-date timing information, use the values provided by the XACT timing calculator and used in the simulator.
Speed Grade
-6
-5
Symbol
Device
Max
Max
Full length, both pull-ups,
inputs from lOB i-pins
TWAF
XC4003H
XC4005H
9.0
10.0
8.0
9.0
ns
ns
Full length, both pull-ups
inputs from intemallogic
TWAFL
XC4003H
XC4005H
12.0
13.0
11.0
12.0
ns
ns
Description
Max
Units
Half length, one pull-up
inputs from lOB i-pins
T WAO
XC4003H
XC4005H
9.0
10.0
8.0
9.0
ns
ns
Half length, one pull-up
inputs from intemallogic
T WAOL
XC4003H
XC4005H
12.0
13.0
11.0
12.0
ns
ns
Note: These delays are specified from the decoder input to the decoder output. For pin-to-pin delays, add the Input delay (TPIO) and
output delay (TOPR or Topel, as listed on page 2-93.
Preliminary Global Buffer Switching Characteristic Guidelines
Testing of the switching parameterS is modeled after testing methods specified by MIL-M-3851 0/605. All devices are 100% functionally
tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing patterns. The
following guidelines reflect worst-case values ·over the recommended operating conditions. For more detailed, more precise, and more
up-to-date timing information, use the values provided by the XACT timing calculator and used in the simulator.
Speed Grade
Description
Global Signal Distribution
From pad through primary buffer, to any clock k
From pad through secondary buffer, to any clock k
-6
-
-5
Symbol
Device
Max
TPG
XC4003H
XC4005H
7.8
8.0
5.8
6.0
ns
ns
TSG
XC4003H
XC4005H
8.8
9.0
6.8
7.0
ns
ns
2-87
-
Max
Max
Units
I
XC4000H High 110 Count Logic Cell Array Family
Preliminary Horizontal Longline Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-3851 0/605. All devices are 100% functionally
tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing patterns. The
following guidelines reflect worst-case values over the recommended operating conditions. For more detailed, more precise, and more
up-to-date timing information, use the values provided by the XACT timing calculator and used in the simulator.
-6
-5
Device
Max
Max
XC4003H
XC4005H
8.8
10.0
6.2
7.0
ns
ns
Speed Grade
Description
Symbol
TBUF driving a Horizontal Longline (L.L.)
I going High or Low to L.L. while T is Low, i.e. buffer
is constantly active
T 101
Max
Units
I going Low to L.L. going from resistive pull-up High
to active Low, (TBUF configured as open drain)
T 102
XC4003H
XC4005H
9.3
10.5
6.7
7.5
ns
ns
T going Low to L.L. going from resistive pull-up or floating High to active Low, (TBUF configured as open drain)
TON
XC4003H
XC4005H
10.7
12.0
9.0
10.0
ns
ns
T going High to TBUF going inactive, not driving the L.L.
TOFF
All devices
3.0
2.0
ns
T going High to L.L. going from Low to High,
pulled up by single resistor
Tpus
XC4003H
XC4005H
24.0
26.0
20.0
22.0
ns
ns
T going High to L.L. going from Low to High,
pulled up by two resistors
TpUF
XC4003H
XC4005H
11.0
12.0
9.0
10.0
ns
ns
2-88
Preliminary Input and Output Parameters (Pin-to-Pin)
All values listed below are tested directly and guaranteed over the operating conditions. The same parameters can also be derived
indirectly from the lOB and Global Buffer specifications. The XACT delay calculator uses this indirect method. When there is a
discrepancy between these two methods, the directly tested values listed below should be used, and the indirectly derived values must
be ignored.
Speed Grade
Symbol
Device
Global Clock to Output (fast) using nearest CLB FF
TICKOF
(Max)
XC4003H
XC4005H
Global Clock to Output (slew limited) using nearest
CLB FF
T ICKO
(Max)
XC4003H
XC4005H
Input Set-up Time, using nearest CLB FF
TpSUF
(Min)
XC4003H
XC4005H
TpHF
(Min)
XC4003H
XC4005H
Description
Input Hold time, using nearest CLB FF
Inpul
sel-uK
Hold
Time
I
CLB
FF
-6
-4
-5
Units
-
!;;~/
\i!;~ 'Ii'
,,'\
!;'~
/2;~;': i\':'::>
ns
ns
ns
ns
ns
ns
ns
ns
and also with the most unfavorable clock polarity choice.
The use of a rising-edge clock reduces the effective clock
delay by 1 to 2 ns.
CLB
FF
D-l>--+----------'
The use of a rising clock edge, therefore, reduces the
clock-to-output delay, and ends the hold-time requirement
earlier. The use of a falling clock edge reduces the input
set-up time requirement.
Global Clock-Io-Oulpul Delay
X3192
Timing is measured at pin threshold, with 50 pF external
capacitive loads (inc!. test fixture)_
In the tradition of guaranteeing absolute worst-case parameter values, the table above does not take advantage
of these improvements. The user can chose between a
rising clock edge with slightly shorter output delay, or a
falling clock edge with slightly shorter input set-up time.
One of these parameters is inevitably better than the
guaranteed specification listed above, albeit by only
one to two nanoseconds.
When testing fast outputs, only one output switches. When
testing slew-rate limited outputs, half the number of outputs on one side of the device are switching.
These parameter values are tested and guaranteed for
worst-case conditions of supply voltage and temperature,
2-89
II
XC4000H High I/O Count Logic Cell Array Family
Preliminary CLB Switching Characteristic Guidelines
Testing ofthe switching parameters is modeled after testing methods specified by MIL-M-3851 0/605. All devices are 100% functionally
tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing patterns. The
following guidelines reflect worst-case values over the recommended operating conditions. For more detailed, more precise, and more
up-to-date timing information, use the values provided by the )(ACT timing calculator and used in the simulator.
Description
Symbol
-5
-6
Speed Grade
Min
Max
Min Max
Min Max Units
Combinatorial Delays
FIG inputs to XN outputs
FIG inputs via H' to XN outputs
C inputs via H' to XN outputs
T llO
TIHO
THHO
6
8
7
4.5
7
5
ns
ns
ns
CLB Fast Carry Logic
Operand inputs (F1 ,F2,G1 ,G4) to COUT
Add/Subtract input (F3) to COUT
Initialization inputs (F1 ,F3) to COUT
CIN through function generators to XN outputs
CIN to COUl' bypass function generators.
TOPCY
TASCY
T 1NCY
TSUM
TByP
7
8
6
8
2
5.5
6
4
6
1.5
ns
ns
ns
ns
ns
Sequential Delays
Clock K to outputs Q
TCKO
5
3
ns
Set-up Time before Clock K
FIG inputs
FIG inputs via H'
C inputs via H1
C inputs via DIN
C inputs via EC
C inputs via SIR, going Low (inactive)
CIN input via F'/G'
CIN input via F'/G' and H'
TICK
TIHCK
THHCK
TOICK
TECCK
T RCK
6
8
7
4
7
6
8
10
4.5
6
5
3
4
4.5
6
7.5
ns
ns
ns
ns
ns
ns
ns
ns
Hold Time after Clock K
FIG inputs
FIG inputs via H'
C inputs via H1
C inputs via DIN
C inputs via EC
C inputs via SIR, going Low (inactive)
TCKI
TCKIH
TCKHH
TCKOI
TCKEC
TCKR
0
0
0
0
0
0
0
0
0
0
0
0
ns
ns
ns
ns
ns
ns
Clock
Clock Hightime
Clock Low time
TCH
TCl
5
5
4.5
4.5
ns
ns
Set/Reset Direct
Width (High)
Delay from C to Q
T RPW
TRIO
5
Master Set/Reset'
Width (High or Low)
Delay from Global Set/Reset net to Q
TMRW
TMRQ
21
, Timing is based on the XC4005H. For other devices see XACT timing calculator.
2-90
4
9
8
ns
ns
31
ns
ns
18
33
Preliminary CLB Switching Characteristic Guidelines (continued)
Testing of the switching parameters is modeled after testing methods specified by MIL-M-3851 0/605. All devices are 100% functionally
tested. Since many intemal timing parameters cannot be measured directly, they are derived from benchmark timing patterns. The
following guidelines reflect worst-case values over the recommended operating conditions. For more detailed, more precise, and more
up-to-date timing information, use the values provided by the XACT timing calculator and used in the simulator.
CLB RAM Option
Description
Write Operation
Address write cycle time
Write Enable pulse width (High)
Address set-up time before beginning of WE
Address hold time after end of WE
DIN set-up time before end of WE
DIN hold time after end of WE
Read Operation
Address read cycle time
Data valid after address change
(no Write Enable)
Read Operation, Clocking Data into Flip-Flop
Address setup time before clock K
Read During Write
Data valid after WE going active
(DIN stable before WE)
Data valid after DIN
(DIN change during WE)
Read During Write, Clocking Data into Flip-Flop
WE setup time before clock K
Data setup time before clock K
Symbol
16 x 2
32 x 1
16 x2
32 x 1
16 x2
32 x 1
16 x 2
32 x 1
16 x2
32 x 1
both
Twc
TWCT
Twp
TWPT
TAS
TAST
TAH
TAHT
Tos
TOST
TOHT
16 x 2
32 x 1
16 x2
32 x 1
TRC
TRCT
TILO
TIHO
16 x 2
32 x 1
TICK
T IHCK
16 x 2
32 x 1
16 x2
32 x 1
Two
TWOT
Too
TOOT
16x 2
32 x 1
16 x 2
32 x 1
TWCK
TWCKT
TOCK
TOCKT
Note: Timing for the 16 x 1 RAM option is identical to 16 x 2 RAM timing
2-91
·5
-6
Speed Grade
Min
Max
9
9
5
5
2
2
2
2
4
5
2
7
10
Min Max
8
8
4
4
2
2
2
2
4
5
2
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
5.5
7.5
ns
ns
ns
ns
4.5
7
6
8
12
15
11
14
12
15
11
14
ns
ns
4.5
6
6
8
Min Max Units
10
12
9
11
10
12
9
11
ns
ns
ns
ns
ns
ns
ns
ns
II
XC4000H High I/O Count Logic Cell Array Family
CLB RAM Timing Characteristics
ADDRESS
WRITE
WRITE ENABLE
DATA IN
READ
X,YOUTPUTS
READ, CLOCKING DATA INTO FLIP-FLOP
'""'I.~--TICK_I _ _ _ TCH----j
CLOCK
I~_____________
----~~I
XO,YO OUTPUTS
READ DURING WRITE
TWp
WRITE ENABLE
DATA IN
(stable during WE)
X,YOUTPUTS
VALID
VALID
DATA IN
NEW
(changing during WE)
X,YOUTPUTS
VALID
(PREVIOUS)
VALID
(NEW)
READ DURING WRITE, CLOCKING DATA INTO FLIP-FLOP
WRITE ENABLE
___~E
IWCI< _ _ _
TW1P
DATA IN
CLOCK
XO,YO OUTPUTS
X2640
2-92
Preliminary lOB Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38S1 0/605. All devices are 100% functionally
tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing patterns. The
following guidelines reflect worst-case values over the recommended operating conditions. For more detailed, more precise, and more
up-to-date timing information, use the values provided by the XACT timing calculator and used in the simulator.
Inputs
-5
-6
Description
Symbol
Propagation Delays from CMOS or TTL Levels
Pad to 11,12
Min Max
Min Max
4.0
3.0
TplD
Min Max Units
ns
II
Outputs
-5
-6
Description
Symbol
Propagation Delays to TTL Levels
Output (0) to Pad (Resistive Mode)
Otuput (0) to Pad (Capacitive Mode)
3-state to Pad begin hi-Z (Resistive Mode)
3-state to Pad begin hi-Z (Capacitive Mode)
3-state to Pad active and valid (Resistive Mode)
3-state to Pad active and valid (Capacitive Mode)
Propagation Delays to CMOS Levels
Output (0) to Pad (Resistive Mode)
Otuput (0) to Pad (Capacitive Mode)
3-stateto Pad begin hi-Z (Resistive Mode)
3-state to Pad begin hi-Z (Capacitive Mode)
3-state to Pad active and valid (Resistive Mode)
3-state to Pad active and valid (Capacitive Mode)
Min Max
Min Max
9.5
10.5
10.5
8.0
14.0
16.0
7.5
8.0
8.5
6.5
11.0
12.0
ns
ns
ns
ns
ns
ns
9.5
9.0
10.5
8.0
14.0
14.0
7.5
7.0
8.5
6.5
11.0
11.0
ns
ns
ns
ns
ns
ns
T OPR
Topc
TTSHZR
TTSHZC
TTSONR
TTSONC
T OPR
Topc
TTSHZR
TTSHZC
TTSONR
TTSONC
Min Max Units
Notes: 1. Timing is measured at pin threshold, with 50 pF external capacitive loads (incl. test fixture).
2. Output delays change with capacitive loading as described in the following table.
TTL Levels
CMOS Levels
Units
Resistive Mode
0.03
0.03
ns/pF
Capacitive Mode
0.04
0.03
ns/pF
3. Voltage levels of unused (bonded and unbonded) pads must be valid logic levels. Each can be configured with the internal
pull-up or pull-down resistor, or alternatively, configured as a driven output or be driven from an external source.
2-93
XC4000 High VO Count Logic Cell Array Family
XC4003H Pinouts
Pin
Description
PG191 PQ208
Bound
Scan
Pin
Description
PG191 PQ208
Bound
Scan
Pin
Description
PG191 PQ208
Bound
Scan
Pin
Description
PG191 PQ208
Bound
Scan
vee
J4
183
-
VO
Cl0
27
182
GND
K15
79
-
GND
R9
131
-
VO(A8)
J3
184
62
1/0
610
28
165
1/0
K16
60
307
1/0(03)
T9
132
427
1/0 (A9)
J2
185
65
I/O
A9
29
186
1/0
K17
81
310
1/0 (RS)
U9
133
430
1/0
Jl
186
68
1/0
Al0
30
191
1/0
K18
82
313
1/0
V9
134
433
1/0
HI
187
71
I/O
All
31
194
1/0
L18
83
316
VO
V8
135
436
1/0
H2
188
74
32
197
I/O
L17
84
319
I/O
U8
136
439
H3
189
77
VO
VO
Cll
1/0
611
33
200
I/O
L16
85
322
VO
T8
137
442
1/0 (AI 0)
Gl
190
80
1/0
A12
34
203
1/0
M18
86
325
1/0(02)
V7
138
445
I/O (All)
G2
191
83
I/O
612
35
206
1/0
M17
87
328
1/0
U7
139
448
1/0
Fl
192
86
1/0
A13
36
209
1/0
N18
86
331
V6
140
451
U6
141
454
T7
142
457
1/0
El
193
89
GND
C12
37
-
1/0
P18
89
334
GND
G3
194
-
1/0
613
38
212
M16
90
-
I/O
F2
195
92
A14
39
215
N17
91
337
1/0
V5
143
1/0
1/0
01
196
95
VO
VO
A15
40
218
GND
VO
VO
VO
VO
GND
R18
92
340
VO
V4
144
460
Cl
197
98
1/0
C13
41
221
1/0
T18
93
343
1/0
U5
145
463
1/0
E2
198
101
1/0
614
42
224
1/0
P17
94
346
1/0
T6
146
466
VO (AI2)
F3
199
104
1/0
A16
43
227
1/0
N16
95
349
1/0(01)
V3
147
469
1/0 (AI3)
02
200
107
1/0
615
44
230
VO
Tl7
96
352
vo IRCLK·BUSY/RDY)
V2
148
472
VO
61
201
110
1/0
C14
45
233
1/0
R17
97
355
1/0
U4
149
475
1/0
E3
202
113
1/0
A17
46
236
1/0
P16
98
358
1/0
T5
150
478
I/O (AI4)
C2
203
116
SGCK2 (1/0)
B16
47
239
1/0
U18
99
361
110(00, DIN)
U3
151
481
SGCKI (AI5,1/0)
B2
204
119
Ml
C15
48
242
SGCK3 (I/O)
T16
100
364
SGCK4 (OOUT, VOl
T4
152
484
vee
03
205
GND
015
49
-
GND
R16
101
VI
153
-
206'
MO
A18
50
245t
-
-
102'
vee
R4
154
-
51'
U17
103
-
53'
-
104'
-
-
105'
04
2
-
54'
vee
-
R15
106
-
-
155'
52'
-
-
3'
vee
016
55
-
DONE
-
GND
-
-
CCLK
-
-
-
-
107'
C3
4
122
M2
C16
56
246t
PROG
V18
-
1/0 (AI7)
C4
5
125
PGCK2 (I/O)
B17
57
247
1/0(07)
I/O
63
6
128
I/O (HOC)
E16
58
250
PGCK3(1/0)
VO
C5
7
131
I/O
C17
59
253
I/O (TOI)
A2
8
134
1/0
017
60
256
PGCKI (A1S,
VOl
207'
206'
I'
-
-
156'
157'
TOO
U2
159
108
-
GND
R3
160
Tl5
109
367
1/0 (AO,WS)
T3
161
2
U16
110
370
PGCK4 (I/O, AI)
Ul
162
5
I/O
T14
111
373
VO
P3
163
8
110
U15
112
376
I/O
R2
184
11
158'
I/O (TCI<)
64
9
137
I/O
B18
61
259
1/0(06)
V17
113
379
I/O (CS1, A2)
T2
165
14
I/O
C6
10
140
VO(LOC)
E17
62
262
I/O
V16
114
382
1/0 (A3)
N3
166
17
20
I/O
A3
11
143
I/O
F16
63
265
I/O
Tl3
115
385
I/O
P2
167
I/O
65
12
146
I/O
C18
84
268
110
U14
116
388
I/O
TI
168
23
VO
GND
66
13
149
I/O
018
65
271
110
V15
117
391
I/O
Rl
169
26
C7
14
-
1/0
F17
66
274
118
394
1/0
N2
170
29
A4
15
152
GND
G16
67
-
VO
GND
V14
1/0
Tl2
119
-
GND
M3
171
-
1/0
A5
16
155
I/O
E18
68
277
I/O
U13
120
397
110
PI
172
32
I/O (TMS)
67
17
158
I/O
F18
69
280
I/O
V13
121
400
110
Nl
173
35
I/O
A6
18
161
I/O
G17
70
283
I/O (05)
U12
122
403
VO(A4)
M2
174
38
1/0
C8
19
184
I/O
G18
71
286
I/O (CSO)
V12
123
406
I/O (A5)
Ml
175
41
1/0
A7
20
167
I/O
H16
72
289
1/0
TIl
124
409
I/O
176
44
I/O
68
21
170
I/O
H17
73
292
I/O
Ull
125
412
I/O
L3
l2
177
47
I/O
A8
22
173
I/O
H18
74
295
VO
VII
126
415
110
L1
178
50
I/O
B9
23
176
I/O
J18
75
298
I/O
Vl0
127
418
I/O
Kl
179
53
I/O
C9
24
179
I/O
J17
76
301
110(04)
Ul0
128
421
I/O (A6)
K2
160
56
GND
09
25
J16
77
304
VO
TlO
129
424
1/0 (A7)
K3
181
59
010
26
-
I/O (ERR, IN IT)
vee
vee
J15
78
-
vee
RIO
130
-
GND
K4
182
-
, Indlcales unconecled package pins,
t Conlribules only one bil (.i) 10 Ihe boundary scan regisler.
Boundary Scan BilO = TOO.T
Boundary Scan Bill = TOO.O
Boundary Scan Bil487 = BSCANT.UPO
2-94
~XILINX
XC4005H Pinouts
Pin
Description
vee
Bound
PG223 MCl240 Scan
-
11O
74
VO
77
80
110
110
83
86
89
VO
110
110
J4
J3
J2
Jl
HI
VO
H2
I/O
H3
GND
-
"0 (AI 0)
110 (All)
Gl
G2
221
92
95
vee
-
222
-
110
H4
223
'10
G4
Fl
224
225
98
101
104
GND
El
226
227
228
229
230
231
232
233
234.
107
VO
-
110
110 (AS)
VO(A9)
VO
"0
GND
VO
110
I/O
VO
"0 (AI2)
110 (AI3)
VO
VO
VO
VO
VO(AI4)
SGCKI (A15, VO)
vee
GND
PGCKI (AI6,IIO)
VO(AI7)
VO
11O
VO (TOI)
G3
F2
01
Cl
E2
F3
02
F4
E4
Bl
E3
236
239
vee
-
110
110
Bll
A12
B12
38
39
40
41
42
43
44
45
VO
VO
'10
"0
"0
110
VO
VO
I/O
VO
VO
SGCK2(1I0)
Ml
GND
MO
5
6
7
8
9
10
11
12
13
155
156
161
164
167
170
173
176
179
14
15
16
17
-
VO
182
185
186
GND
D6
C7
A4
110 (TMS)
VO
A6
VO
VO
07
08
GND
-
VO
VO
VO
110
-
vee
M2
PGCK2(IIO)
110 (HOC)
VO
I/O
110
110 (lOC)
I/O
VO
VO
11O
11O
A13
C12
D13
014
B13
A14
A15
C13
B14
A16
B15
C14
A17
B16
C15
015
A18
016
C16
B17
E16
C17
017
B18
E17
F16
C18
018
F17
46
47
48
49
50
51
52
53
54
55
56
57·
56
59
60
61
I/O
SGCK3(I/O)
GND
DONE
vee
301
304
307
310
313
316
319
322
11O
VO
VO
334
337
340
vee
110
110
-
80
-
vee
H16
H17
343
346
VO(05)
I/O (CSO)
GND
I/O
352
355
B8
209
110
110
212
215
VO
VO
HI5
H18
J18
J17
J16
J15
K15
65
86
87
88
89
90
91
110 (ERFI,1Nif)
vee
GND
325
328
110
11O
11O
11O
VO(D6)
77
-
218
I/O
11O
110
78
79
G15
30
31
VO
G17
G18
VO
VO
VO
VO
VO
010
Cl0
-
'10
110
110
11O
I/O
GND
11O
11O
GND
-
293t
VO
VO
VO
73
74
75
76
203
208
29
-
GND
E15
F15
G16
E18
F18
200
D9
M17
N18
P18
298
24
GND
290
-
331
349
110
358
VO
VO
361
364
110(04)
110
-
vee
GND
• Indicates unconected package pins.
t Conlrlbutes only one bH (.i) 10 the bOundary scan register.
Boundary Scan BH 0 = Too.T
Boundary Scan BH 1 = Too.O
Boundary Scan BH 563 BSCANT.UPO
=
2·95
-
I/O
VO
64
65
66
67
68
69
70
71
72
23
C9
284
287
-
M18
PROG
C8
A7
I/O
263
266
269
272
275
278
281
L18
117
L16
VO
I/O
254
257
260
93
vee
VO(07)
PGCK3(VO)
-
VO
-
K15
K17
K18
M15
295
81
82
83
84
25
26
27
28
242
245
248
251
Bound
PG223 MQ240 Scan
VO
VO
294t
VO
VO
194
197
-
GND
62
191
-
230
233
Pin
Description
VO
VO
VO
VO
VO
I/O
63
18
19
20
21
22
A8
B9
VO
011
012
VO
C5
A2
AS
B7
vee
110
GND
146
149
152
B4
vee
236
237
221
224
227
3
4
C6
A3
B5
B6
05
VO
VO
235
110
113
116
119
122
125
128
131
134
137
140
143
32
33
34
35
36
37
238
239
240
1
2
VO
VO
VO
GND
220
-
Bound
PG223 MQ240 Scan
Bl0
A9
Al0
All
Cll
C2
B2
03
04
C3
C4
B3
I/O (TCI<)
I/O
110
I/O
212
213
214
215
216
217
218
219
Pin
Description
M16
N15
P15
N17
R18
T18
P17
.N16
T17
R17
P16
U18
92
94
367
370
373
"0(03
VO(RS)
110
95
96
97
376
379
362
VO
VO
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
388
-
394
397
400
406
409
412
415
418
421
424
427
430
433
T16
R16
. U17
R15
V18
T15
U16
116
117
118
119
120
121
122
123
124
T14
U15
R14
R13
125
126
127
128
445
448
451
V17
V16
T13
U14
V15
129
130
131
132
133
V14
T12
R12
Rl1
134
135
136
137
472
U13
V13
138
139
140
141
142
143
144
145
146
141
498
499
502
505
508
V12
-
Ul1
VII
Vl0
Ul0
Tl0
RIO
R9
PIn
Description
148
149
150
151
436
Bound
'10
GND
VO(02)
457
463
466
469
511
514
517
-
I/O
I/O
I/O
U6
R8
R7
-
GND
T7
VO
VO
R6
R5
V5
V4
U5
T6
V3
V2
U4
T5
U3
T4
VI
I/O
I/O
VO
VO
VO(OI)
110 (RCLK-BUSYIRDY)
VO
I/O
110(00, DIN)
SGC1<4 (COUT,
VOl
439
442
460
152
153
154
155
156
157
156
159
160
161
162
183
164
165
VO
vee
TOO
GND
IIO(AO,WS)
PGCK4 (11O, AI)
454
Scan
T9
U9
V9
V8
U8
T8
V7
U7
-
-
MQ240
'10
eeLK
vee
,-
PG223
VO
110
110 (CS1, A2)
VO(A3)
I/O
VO
VO
I/O
"0
110
R4
U2
R3
T3
Ul
P3
R2
T2
N3
P4
N4
P2
T1
Rl
N2
-
-
-
GND
478
VO
481
110
110
110
M3
PI
Nl
M4
L4
-
484
490
-
-
-
vec
110 (A4)
110 (AS)
GND
110
VO
VO
110
VO(A6)
VO(A7)
GND
Ml
-
L2
Ll
Kl
K2
K3
K4
166
167
168
169
110
520
523
526
529
532
538
541
544
-
550
553
556
171
172
173
174
175
176
177
178
179
180
181
182
183
184
559
562
565
165
186
187
186
189
8
11
14
17
190
191
192
193
194
195'
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
568
571
574
577
560
-
2
5
20
23
26
29
32
35
--
38
41
44
47
-
53
--
59
62
65
68
71
-
I
XC4000H High
VO Count Logic Cell Array Family
For a detailed description of the device architecture, see page 2-9.
For a detailed description of the configuration modes and their timing, see pages 2-32 through 2-55.
For detailed lists of package pinouts, see pages 2-94 through 2-95.
For package physical dimensions, see Section 4.
Ordering Information
Example:
Device Type
XC400SH-S PG223C
~ lLT.mp.m,"reR~'"
Number of Pins
Speed Grade
Package Type
Component Availability
Parentheses indicates future product plans
2-96
~
XC3000 Logic Cell Array Families
Table of Contents
Overview ................................................................. 2-98
XC3000, XC3000A, XC3000L, XC31 00
Logic Cell Array Families .................................... 2-99
Architecture ....................................................... 2-1 00
Programmable Interconnect ............................. 2-105
Crystal Oscillator ............................................... 2-111
Programming .................................................... 2-112
Special Configuration Functions ....................... 2-116
Master Serial Mode ........................................... 2-118
Master Serial Mode Programming
Switching Characteristics ............................. 2-119
Master Parallel Mode .................. ;..................... 2-120
Master Parallel Mode Programming
Switching Characteristics ............................. 2-121
Peripheral Mode ............................................... 2-122
Peripheral Mode Programming
Switching Characteristics ............................. 2-123
Slave Serial Mode ............................................. 2-124
Slave Serial Mode Programming
Switching Characteristics ............................. 2-125
Program Readback Switching
Characteristics .............................................. 2-125
General LCA Switching Characteristics ............ 2-126
Performance ......................................•.............. 2-127
Power ................................................................ 2-128
Pin Descriptions ................................................ 2-130
Configuration Pin Assignments ......................... 2-132
XC3000 Families Pin Assignments ................... 2-133
XC3000 Families Pinouts ................................. 2-133
Component Availability ..................................... 2-143
Ordering Information ......................................... 2-144
XC3000 Logic Cell Array Family ........................... 2-145
Absolute Maximum Ratings .............................. 2-146
Operating Conditions ........................................ 2-146
DC Characteristics ............................................ 2-147
Switching Characteristic Guidelines
CLB ............................•................................. 2-148
Buffer ............................................................ 2-148
lOB ............................................................... 2-150
Ordering Information ......................................... 2-152
Component Availability ..................................... 2-152
XC3000A Logic Cell Array Familiy ........................ 2-153
Absolute Maximum Ratings .............................. 2-154
Operating Conditions ........................................ 2-154
DC Characteristics ............................................ 2-155
Switching Characteristic Guidelines
CLB .............................................................. 2-156
Buffer ............................................................ 2-156
lOB ............................................................... 2-158
Ordering Information ......................................... 2-160
Component Availability ..................................... 2-160
XC3000L Low Voltage Logic Cell Array Family .... 2-161
Absolute Maximum Ratings .............................. 2-162
Operating Conditions ................... ,.................... 2-162
DC Characteristics ............................................ 2-163
Switching Characteristic Guidelines
CLB .............................................................. 2-164
Buffer ............................................................ 2-164
IOB· ............................................................... 2-166
Ordering Information ......................................... 2-168
Component Availability ..................................... 2-168
XC3100 Logic Cell Array Family ........................... 2-169
Absolute Maximum Ratings .............................. 2-170
Operating Conditions ........................................ 2-170
DC Characteristics ............................................ 2-171
Switching Characteristic Guidelines
CLB .............................................................. 2-172
Buffer ............................................................ 2-172
lOB ............................................................... 2-174
Ordering Information ......................................... 2-176
Component Availability ..................................... 2-176
II
Overview
XC3000A Family
The XC3000A is an enhanced version olthe basic XC3000
family, featuring additional interconnect resources and
other user-friendly enhancements. The ease-of-use of the
XC3000A family makes it the obvious choice for all new
designs that do not require the speed olthe XC31 00 orthe
3-volt operation of the XC3000L.
Introduced in 1987/88, XC3000 is the industry's most
successful family of FPGAs, with over 10 million devices
shipped. In 1992193, Xilinx introduced three additional
families, offering more speed, functionality, and a new
supply-voltage option.
There are now four distinct family groupings within the
XC3000 class of LCA devices.
•
•
•
•
XC3000L Family
The XC3000L is identical in architecture and features to
the XC3000A family, but operates at a nominal supply
voltage of 3.3 V. The XC3000L is the right solution for
battery-operated and low-power applications .
XC3000 Family
XC3000A Family
XC3000L Family
XC31 00 Family
XC3100 Family
The XC3100 is a performance-optimized relative of the
basic XC3000 family. While both families are bitstream
and footprint compatible, the XC31 00 family extends toggle
rates to 270 MHz and in-system performance to 80 MHz.
The XC31 00 family also offers one additional array size,
the XC3195. The XC31 00 is best suited for designs that
require the highest clock speed or the shortest net delays.
All four families share a common architecture, development software, design and programming methodology,
and also common package pin-outs. An extensive Product
Description covers these common aspects. (Page 2-99).
The much shorter individual Product Specifications then
provide detailed parametric information for the four individual product families.
The figure below illustrates the relationships between the
families. Compared to the original XC3000 family, XC3000A
offers additional functionality and, coming soon, increased
speed. The XC3000L family offers the same additional
functionality, but reduced speed due to its lower supply
voltage of 3.3 V. The XC31 00 family offers no additional
functionality, but substantially higher speed, and higher
density with its new member, the XC3195.
Here is a simple overview.
XC3000 Family
The basic XC3000 family forms the cornerstone for the
rest of the XC3000 class of devices. The basic XC3000
family offers five different device densities with guaranteed toggle rates from 70 to 125 MHz.
X3177
2-98
XC3000, XC3000A,
XC3000L, XC31 00
Logic Cell Array Families
Product Description
Features
• Complete XACT Development System
- Schematic capture, automatic place and route
- Logic and timing simulation
- Interactive design editor for design optimization
- Timing calculator
- Interfaces to popular design environments like
Viewlogic, Cadence, Mentor Graphics, and others
• Complete line of four related Field Programmable
Gate Array product families.
- XC3000, XC3000A, XC3000L, XC3100
• Ideal for a wide range of custom VLSI design tasks
- Replaces TTL, MSI, and other PLD logic
- Integrates complete sUb-systems into a single
package
- Avoids the NRE, time delay, and risk of
conventional masked gate arrays
Description
The CMOS XC3000 Class of Logic Cell Array (LCA)
families provide a group of high-performance, high-density, digital integrated circuits. Their regular, extendable,
flexible, user-programmable array architecture is composed of a configuration program store plus three types of
configurable elements: a perimeter of 1/0 Blocks (lOBs), a
core array of Configurable Logic Bocks (CLBs) and resources for interconnection. The general structure of an
LCA device is shown in Figure 1 on the next page. The
XACT development system provides schematic capture
and auto place-and-route for design entry. Logic and
timing simulation, and in-circuit emulation are available as
design verification alternatives. The design editor is used
for interactive design optimization, and to compile the data
pattern that represents the configuration program.
• High-performance CMOS static memory technology
- Guaranteed toggle rates of 70 to 270 MHz, logic
delays from 9 to 3 ns
- System clock speeds of up to 80 MHz
- Low quiescent and active power consumption
• Flexible FPGA architecture
- Compatible arrays ranging from 1,300 to 9,000
gate complexity
- Extensive register, combinatorial, and 1/0
capabilities
- High fan-out signal distribution, low-skew clock
nets
- Internal 3-state bus capabilities
- TTL or CMOS input thresholds
- On-chip crystal oscillator amplifier
The LCA user logic functions and interconnections are
determined by the configuration program data stored in
internal static memory cells. The program can be loaded in
any of several modes to accommodate various system
requirements. The program data resides externally in an
EEPROM, EPROM or ROM on the application circuit
board, oron a floppy disk or hard disk. On-chip initialization
logic provides for optional automatic loading of program
data at power-up. The companion XC17XX Serial
Configuration PROMs provide a very simple serial configuration program storage in a one-time programmable
package.
• Unlimited reprogrammability
- Easy design iteration
- In-system logic changes
• Extensive Packaging Options
- Over 20 different packages
- Plastic and ceramic surface-mount and pin-gridarray packages
- Thin and Very Thin Quad Flat Pack (TQFP and
VQFP) options
• Ready for volume production
- Standard, off-the-shelf product availability
- 100% factory pre-tested devices
- Excellent reliability record
Device
XC3020,3020A,3020L,3120
XC3030,3030A,3030L,3130
XC3042,3042A,3042L,3142
XC3064,3064A,3064L,3164
XC3090, 3090A, 3090L,3190
XC3195
CLBs
64
100
144
224
320
464
UserVOs
Max
64
80
96
120
144
176
Array
8x8
10 x 10
12 x 12
16 x 14
16 x 20
22x22
2-99
Flip-Flops
256
360
480
688
928
1,320
Horizontal
Longlines
16
20
24
32
40
44
Configuration
Data Bits
14,779
22,176
30,784
46,064
64,160
94,984
II
XC3000, XC3000A, XC3000L, XC31 00 Logic Cell Array Families
configuration. Program data may be either bit serial or byte
parallel. The XACT development system generates the
configuration program bitstream used to configure the
LCA device. The memory loading process is independent
of the user logic functions.
The XC3000 Logic Cell Array families provide a variety of
logic capacities, package styles, temperature ranges and
speed grades.
Architecture
The perimeter of configurable lOBs provides a programmable interface between the internal logic array and
the device package pins. The array of CLBs performs
user-specified logic functions. The interconnect resources
are programmed to form networks, carrying logic signals
among blocks, analogous to printed circuit board traces
connecting MSI/SSI packages.
Configuration Memory
The static memory cell used for the configuration memory
in the Logic Cell Array has been designed specifically for
high reliability and noise immunity. Integrity of the LCA
device configuration memory based on this design is
assured even under adverse conditions. Compared with
other programming alternatives, static memory provides
the best combination of high denSity, high performance,
high reliability and comprehensive testability. As shown in
Figure 2, the basic memory cell consists of two CMOS
inverters plus a pass transistor used for writing and reading cell data. The cell is only written during configuration
and only read during readback. During normal operation,
the cell provides continuous control and the pass transistor
is off and does not affect cell stability. This is quite different
from the operation of conventional memory devices, in
which the cells are frequently read and rewritten.
The block logic functions are implemented by programmed
look-up tables. Functional options are implemented by
program-controlled multiplexers. Interconnecting networks
between blocks are implemented with metal segments
joined by program-controlled pass transistors.
These LCA functions are established by a configuration
program which is loaded into an internal, distributed array
of configuration memory cells. The configuration program
is loaded into the LCA device at power-up and may be
reloaded on command. The Logic Cell Array includes logic
and control signals to implement automatic or passive
3·State Buffers With Access
to Horizontal Long Lines
Configurable Logic
Blocks
~
y- ------------- y-
p
O D
B
Uy-
y-
p
y-
OD
O yc
y-
y-
Interconnect Area
p
4--
U
a
p
p
y-
4--
4--
0
y-
4--
4--
0
4--
4-J!!
c:
"0
y-
D..
"
E
~
u.
4--
Figure 1. Logic Cell Array Structure.
X3241
It consists of a perimeter of programmable 1/0 blocks, a core of configurable logic blocks and their interconnect resources.
These are all controlled by the distributed array of configuration program memory cells.
2-100
The method of loading the configuration data is selectable.
Two methods use serial data, while three use byte-wide
data. The internal configuration logic utilizes framing
information, embedded in the program data by the XACT
development system, to direct memory-cell loading. The
serial-data framing and length-count preamble provide
programming compatibility for mixes of various LCA device
devices in a synchronous, serial, daisy-chain fashion.
r-----}-+Q
CONFIGURATION
_ CONTROL
I--~,-+Q
READ or
WRITE
DATA
1105 12
Figure 2. Static Configuration Memory Cell.
It is loaded with one bit of configuration program and
controls one program selection in the Logic Cell Array.
The memory cell outputs Q and Q use ground and Vcc
levels and provide continuous, direct control. The additional capacitive load together with the absence of address
decoding and sense amplifiers provide high stability to the
cell. Due to the structure of the configuration memory cells,
they are not affected by extreme power-supply excursions
or very high levels of alpha particle radiation. In reliability
testing, no soft errors have been observed even in the
presence of very high doses of alpha radiation.
(OUTPUT
110 Block
Each user-configurable lOB shown in Figure 3, provides
an interface between the external package pin of the
device and the internal user logic. Each lOB includes both
registered and direct input paths. Each lOB provides a
programmable 3-state output buffer, which may be driven
by a registered or direct output signal. Configuration
options allow each lOB an inversion, a controlled slew rate
and a high impedance pUll-Up. Each input circuit also
provides· input clamping diodes to provide electrostatic
protection, and circuits to inhibit latch-up produced by
input currents.
~r!'":~ -+:.-.--I--------,IL,)--i---..
OUT
DIRECT IN
REGISTERED IN
-..l.Q-...:::JL)-.........---j
--"'-----+------,
---'-"'-----+---1
or
LATCH
R
OK
1}-
PROGRAM
CONTROLLED
MULTIPLEXER
IK
o
= PROGRAMMABLE INTERCONNECTION POINT or PIP
X3029
Figure 3. InpuVOutput Block.
Each lOB includes input and output storage elements and VO options selected by configuration memory cells. A choice of two
clocks is available on each die edge. The polarity of each clock line (not each flip-flop or latch) is programmable. A clock line that
triggers the flip-flop on the rising edge is an active Low Latch Enable (Latch transparent) signal and vice versa. Passive pull-up can
only be enabled on inputs, not on outputs. All user inputs are programmed for TTL or CMOS thresholds.
2-101
II
XC3000, XC3000A, XC3000L, XC3100 Logic Cell Array Families
The input-buffer portion of each lOB provides threshold
detection to translate external signals applied to the
package pin to internal logic levels. The global input-buffer
threshold of the lOBs can be programmed to be
compatible with either TTL or CMOS levels. The buffered
input signal drives the data input of a storage element,
which may be configured as either a flip-flop or a latch. The
clocking polarity (rising/falling edge-triggered flip-flop,
High/Low transparent latch) is programmable for each of
the two clock lines on each of the four die edges. Note that
a clock line driving a risingedge-triggered flip-flop makes
any latch driven by the same line on the same edge Lowlevel transparent and vice versa (falling edge, High
transparent). All Xilinx primitives in the supported
schematic-entry packages, however, are positive edgetriggered flip-flops or High transparent latches. When one
clock line must drive flip-flops as well as latches, it is
necessary to compensate for the difference in clocking
polarities with an additional inverter either in the flip-flop
clock input or the latch-enable input. I/O storage elements
are reset during configuration or by the active-Low chip
RESET input. Both direct input (from lOB pin I) and
registered input (from lOB pin Q) signals are available for
interconnect.
(lOB) pin FT can control output activity. An open-drain
output may be obtained by using the same signal for
driving the output and 3-state Signal nets so that the buffer
output is enabled only for a Low.
Configuration program bits for each lOB control features
such as optional output register, logic signal inversion, and
3-state and slew-rate control of the output.
The program-controlled memory cells of Figure 3 control
the following options.
• Logic inversion of the output is controlled by one
configuration program bit per lOB.
• Logic 3-state control of each lOB output buffer is
determined by the states of configuration program bits
which turn the buffer on, or off, or select the output buffer
3-state control interconnection (lOB pin T). When this
lOB output control signal is High, a logic one, the buffer
is disabled and the package pin is high impedance.
When this lOB output control signal is Low, a logic zero,
the buffer is enabled and the package pin is active.
Inversion of the buffer 3-state control-logic sense (output
enable) is controlled by an additional configuration
program bit.
For reliable operation, inputs should have transition times
of less than 100 ns and should not be left floating. Floating
CMOS input-pin circuits might be atthreshold and produce
oscillations. This can produce additional power dissipation
and system noise. A typical hysteresis of about 300 mV
reduces sensitivity to input noise. Each user lOB includes
a programmable high-impedance pull-up resistor, which
may be selected by the program to provide a constant High
for otherwise undriven package pins. Although the Logic
Cell Array provides circuitry to provide input protection for
electrostatic discharge, normal CMOS handling precautions should be observed.
• Direct or registered output is selectable for each lOB.
The register uses a positive-edge, clocked flip-flop. The
clock source may be supplied (lOB pin OK) by either of
two metal lines available along each die edge. Each of
these lines is driven by an invertible buffer.
• Increased output transition speed can be selected to
improve critical timing. Slower transitions reduce
capacitive-load peak currents of non-critical outputs and
minimize system noise.
Flip-flop loop delays for the lOB and logic-block flip-flops
are about 3 ns. This short delay provides good performance under asynchronous clock and data conditions.
Short loop delays minimize the probability of a metastable
condition that can result from assertion of the clock during
data transitions. Because of the short-loop-delay characteristic in the Logic Cell Array, the lOB flip-flops can be
used to synchronize external signals applied to the device.
Once synchronized in the lOB, the signals can be used
internally without further consideration of their clock relative timing, except as it applies to the internal logic and
routing-path delays.
~
• A high-impedance pull-up resistor may be used to
prevent unused inputs from floating.
Summary of VO Options
• Inputs
- Direct
- Flip-flop/latch
- CMOSITTL threshold (chip inputs)
- Pull-up reSistor/open circuit
lOB output buffers provide CMOS-compatible 4-mA
source-or-sink drive for high fan-out CMOS or TTLcompatible signal levels (8 mA in the XC31 00 family). The
network driving lOB pin 0 becomes the registered ordirect
data source forthe output buffer. The 3-state control Signal
• Outputs
- Direct/registered
- Inverted/not
- 3-state/on/off
- Full speed/slew limited
- 3-state/output enable (inverse)
2-102
Configurable Logic Block
The array of CLBs provides the functional elements from
which the user's logic is constructed. The logic blocks are
arranged in a matrix within the perimeter of lOBs. The
XC3020 has 64 such blocks arranged in 8 rows and 8
columns. The XACT development system is used to compile the configuration data which is to be loaded into the
internal configuration memory to define the operation and
interconnection of each block. User definition of CLBs and
their interconnecting networks may be done by automatic
translation from a schematic-capture logic diagram or
optionally by installing library or user macros.
Each CLB has a combinatorial logic section, two flip-flops,
and an internal control section. See Figure 4. There are:
five logic inputs (A, B, C, 0 and E); a common clock input
(K); an asynchronous direct RESET input (RD); and an
enable clock (EC). All may be driven from the interconnect
resources adjacent to the blocks. Each CLB also has two
outputs (X and Y) which may drive interconnect networks.
Data input for either flip-flop within a CLB is supplied from
the function For G outputs of the combinatorial logic, or the
block input, 01. Both flip-flops in each CLB share the
01
II
r--
DATA IN
0
rF
DIN
MUX I - - -
L--J
1
~
-G
V
'--
A
...
LOGIC
VARIABLES
••
•.•
'--
RD
ax
F
B
C
0
at-<
0
G
V
CLBOUTPUTS
G
oy
r-
•••
F
r-
E
-
ax
r--- x
L
COMBINATORIAL
FUNCTION
r-
oy
'-- F
~rt
r-- y
V
r-----"'
'"""0
MUX
r-
r- r-
a
0
1
...... r-
..........
EC
~>
ENABLE CLOCK
RD
1 (ENABLE)
.........
..........
CLOCK
...
DIRECT
RESET
..
r
L: . . . . .
K
..........
RD
o (INHIBIT)
.........
(GLOBAL RESET)
~
X3032
Figure 4. Configurable Logic Block. Each CLB includes a combinatorial logic section, two flip-flops and a program
memory controlled multiplexer selection of function. It has. five logic variable inputs A, B, C, D, and E
a direct data in DI
an enable clock EC
a clock (invertible) K
an asynchronous direct RESET RD
two outputs X and Y
2-103
XC3000, XC3000A, XC3000L, XC3100 Logic Cell Array Families
A
B
:~
ENABLE=~TFr~~~~~~t)-_ _ _ _ _L
..
OX
ANY FUNCTION
OFUPT04
VARIABLES
F
COUNT
PARALLEL E~t&~
TERMINAL
COUNT
C
D
E
A
B
DUAL FUNCTION OF 4 VARIABLES
OX
QO
ANY FUNCTION
OFUPT04
VARIABLES
C
D
G
E
A
B
5a
OX
FG
MODE
FG
MODE
F
ANY FUNCTION
OF 5 VARIABLES
D1
01
G
C
D
E
5b
A
B
-U+t++::t====1CY
F
FUNCTION OF 5 VARIABLES
MODE
F
MODE
OX
ANY FUNCTION
OFUPT04
VARIABLES
C
F
D
D2
A
B
~=!:=J====:a
02
G
OX
FUNCTION OF 6 VARIABLES
ANY FUNCTION
OFUPT04
VARIABLES
C
D
5c
E
FGM
MODE
FGM
MODE
1105 03A
Figure 5
Figure 6. C8BCP Macro.
Sa.
The C8BCP macro (moduI0-8 binary counter with parallel
enable and clock enable) uses one combinatorial logic block
of each option.
Combinatorial Logic Option FG generates two functions
of four variables each. One variable, A, must be common
to both functions. The second and third variable can be
any choice of of B, C, ax and OY The fourth variable
can be any choice of D or E.
5b. Combinatorial Logic Option F generates any function of
five variables: A, D, E and and two choices out of B, C,
OX,OY.
5c.
Combinatorial Logic Option FGM allows variable E to
select between two functions of four variables: Both have
common inputs A and D and any choice out of B, C, ax
and OY for the remaining two variables. Option 3 can
then implement some functions of six or seven variables.
2-104
I:XltiNX
switch connections to block inputs are unidirectional, as are block outputs, they are usable only for
block input connection and not for routing. Figure 8
asynchronous RD which, when enabled and High, is
dominant over clocked inputs. All flip-flops are reset by the
active-Low chip input, RESET, or during the configuration
process. The flip-flops share the enable clock (EC) which,
when Low, recirculates the flip-flops' present states and
inhibits response to the data-in or combinatorial function
inputs on a CLB. The user may enable these control inputs
and select their sources. The user may also select the
clock net input (K), as well as its active sense within each
CLB. This programmable inversion eliminates the need to
route both phases of a clock signal throughout the device.
Flexible routing allows use of common or individual CLB
clocking.
illustrates routing access to logic block input variables,
control inputs and block outputs. Three types of metal
resources are provided to accommodate various network
interconnect requirements.
• General Purpose Interconnect
• Direct Connection
• Longlines (multiplexed busses and wide AND gates)
General Purpose Interconnect
The combinatorial-logic portion of the CLB uses a 32 by 1
look-up table to implement Boolean functions. Variables
selected from the five logic inputs and two internal block
flip-flops are used as table address inputs. The combinatorial propagation delay through the network is independent of the logic function generated and is spike free for
single input variable changes. This technique can generate two independent logic functions of up to four variables
each as shown in Figure 5a, or a single function of five
variables as shown in Figure 5b, or some functions of
seven variables as shown in Figure 5c. Figure 6 shows a
modul0-8 binary counter with parallel enable. It uses one
CLB of each type. The partial functions of six or seven
variables are implemented using the input variable (E) to
dynamically select between two functions of four different
variables. For the two functions of four variables each, the
independent results (F and G) may be used as data inputs
to either flip-flop or either logic block output. For the single
function of five variables and merged functions of six or
seven variables, the F and G outputs are identical. Symmetry of the F and G functions and the flip-flops allows the
interchange of CLB outputs to optimize routing efficiencies
of the networks interconnecting the CLBs and lOBs.
General purpose interconnect, as shown in Figure 9,
consists of a grid of five horizontal and five vertical metal
segments located between the rows and columns of logic
and lOBs. Each segment is the height or width of a logic
block. Switching matrices join the ends of these segments
and allow programmed interconnections between the
metal grid segments of adjoining rows and columns. The
switches of an unprogrammed device are all nonconducting. The connections through the switch matrix
may be established by the automatic routing or by using
Editnet to select the desired pairs of matrix pins to be
connected or disconnected. The legitimate switching
matrix combinations for each pin are indicated in Figure 10
and may be highlighted by the use of the Show-Matrix
command in the XACT system.
INTERCONNECT
"PIPs'
SWITCHING
MATRIX
r·.:/,
. t-·.:
0·::···:·::0
.. . :
~-
...
Programmable Interconnect
Programmable-interconnection resources in the Logic
Cell Array provide routing paths to connect inputs and
outputs of the lOBs and CLBs into logic networks. Interconnections between blocks are composed of a tWO-layer
grid of metal segments. Specially designed pass transistors, each controlled by a configuration bit, form programmable interconnect points (PIPs) and switching matrices
used to implement the necessary connections between
selected metal segments and block pins. Figure 7 is an
example of a routed net. The XACT development system
provides automatic routing of these interconnections. Interactive routing (Editnet) is also available for design
optimization. The inputs of the CLBs or lOBs are multiplexers which can be programmed to select an input network
from the adjacent interconnect segments. Since the
t·· :
····:·:0
: . J•...
'.
i
~.:.:
CONFIGURABLE
LOGIC BLOCK
"
4.; .:
INTERCONNECT
BUFFER
Figure 7.
An XACT view of routing resources used to form a typical
interconnection network from CLB GA.
2-105
X119,
II
XC3000, XC3000A, XC3000L, XC3100 Logic Cell Array Families
'::'E}
'::1:1
':>:
: ,'r' ,:
, t-'
. : 0,:
+-
t,,~
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,
,
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I
.
.
\ ...
I
..
v- .': .
't- .': •
CLB CONTROL INPUTS
CLB LOGIC INPUTS
CLB X OUTPUT
CLB Y OUTPUT
....... .
. .....
0.... ' ·'.. ......'"" +-0"
\'"
0"
'\' O'.
" ' : '+- " . : . . '
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:
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:
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:
t,
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.... :
r'
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:
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t- . ..
.
:0'
.
~- ..
'::Cl
:
'
.. +-'
:
:
X1196
Figure 8, XACT Development System Locations of interconnect access, CLB control inputs, logic inputs and outputs. The dot
pattern represents the available programmable interconnection points (PIPs).
Some of the interconnect PIPs are directional. This is indicated on the XACT design editor status line:
NO is a nondirectional interconnection.
O:H->V is a PIP that drives from a horizontal to a vertical line.
O:V->H is a PIP that drives from a vertical to a horizontal line.
O:C->T is a 'T' PIP that drives from a cross of a T to the tail.
O:CW is a corner PIP that drives in the clockwise direction.
PO indicates the PIP is non-conducting, P1 is on.
2-106
·: . ·Ef
:
.. t-
..
~-
·:. e
. f:j
t·
...
'\ .
·:. a
SWITCHING
MATRIX
GRID OF GENERAL INTERCONNECT
METAL SEGMENTS
Figure 9. LCA General-Purpose Interconnect.
Composed of a grid of metal segments that may be interconnected through switch matrices to form networks for CLB and
lOB inputs and outputs.
X2664
L~
r
Special buffers within the general interconnect areas provide periodic signal isolation and restoration for improved
performance of lengthy nets. The interconnect buffers are
available to propagate signals in either direction on a given
general interconnect segment. These bidirectional (bid i)
buffers are found adjacent to the switching matrices,
above and to the right and may be highlighted by the use
ofthe Show BIOI command in the XACTsystem. The other
PIPs adjacent to the matrices are accessed to or from
Longlines. The development system automatically defines the buffer direction based on the location of the
interconnection network source. The delay calculator of
the XACT development system automatically calculates
and displays the block, interconnect and buffer delays for
any paths selected. Generation of the simulation netlist
with a worst-case delay model is provided by an XACT
option.
Direct Interconnect
Direct interconnect, shown in Figure 11, provides the most
efficient implementation of networks between adjacent
CLBs or 1/0 Blocks. Signals routed from block to block
using the direct interconnect exhibit minimum interconnect
propagation and use no general interconnect resources.
For each CLB, the X output may be connected directly to
the B input of the CLB immediately to its right and to the C
input of the CLB to its left. The Y output can use direct
interconnect to drive the 0 input of the block immediately
above and the A input of the block below. Direct intercon-
·:. n
:
:
:
..
. t·.;
··
. . ....
:
...
..
.:. (5
. t
~~~
~~ ~~ ~~ ~= Q
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El
::-ff
~~ =~ ~~
1
2
··0··
.. +- ...
'0
3
4
5
••
~
..
..
6
7
8
9
10
. ...
11
16
12
17
13
18
14
..
:
~.:
20
1105 13
Figure 10. Switch Matrix Interconnection Options for Each
Pin. Switch matrices on the edges are different. Use Show
Matrix menu option in the XACT system
:
...
t
. .
..
15
ee
19
.. ..
. .
··
:
~:
~
:
...
..
X1198
Figure 11. CLB X and Y Outputs.
The X and Y outputs of each CLB have single contact, direct
access to inputs of adjacent CLBs
2-107
II
XC3000, XC3000A, XC3000L, XC31 00 Logic Cell Array Families
GLOBAL BUFFER DIRECT INPUT
GLOBAL BUFFER INTERCONNECT
ALTERNATE BUFFER DIRECT INPUT
*UNBONDED lOBs (6 PLACES)
Figure 12. XC3020 Die-Edge lOBs. The XC3020 die-edge lOBs are provided with direct access to adjacent CLBs.
2-108
X1200
nect should be used to maximize the speed of highperformance portions of logic. Where logic blocks are
adjacent to lOBs, direct connect is provided alternately to
the lOB inputs (I) and outputs (0) on all four edges of the
die. The right edge provides additional direct connects
from CLB outputs to adjacent lOBs. Direct interconnections of lOBs with CLBs are shown in Figure 12.
Longlines
The Longlines bypass the switch matrices and are intended primarily for signals that must travel a long distance, or must have minimum skew among multiple destinations. Longlines, shown in Figure 13, run vertically and
horizontally the height or width of the interconnect area.
Each interconnection column has three vertical Longlines,
and each interconnection row has two horizontal
Longlines. Two additional Longlines are located adjacent
to the outer sets of switching matrices. In devices larger
than the XC3020, two vertical Longlines in each column
are connectable half-length lines. On the XC3020, only the
outer Longlines are connectable half-length lines.
Longlines can be driven by a logic block or lOB output on
a column-by-column basis. This capability provides a
common low skew control or clock line within each column
of logic blocks. Interconnections of these Longlines are
shown in Figure 14. Isolation buffers are provided at each
input to a Longline and are enabled automatically by the
development system when a connection is made.
A buffer in the upper left corner of the LCA chip drives a
global net which is available to all K inputs of logic blocks.
Using the global buffer for a clock signal provides a skewfree, high fan-out, synchronized clock for use at any or all
of the lOBs and CLBs. Configuration bits for the K input to
each logic block can select this global line or another
routing resource as the clock source for its flip-flops. This
net may also be programmed to drive the die edge clock
lines for lOB use. An enhanced speed, CMOS threshold,
direct access to this buffer is available at the second pad
from the top of the left die edge.
A buffer in the lower right corner of the array drives a
horizontal Longline that can drive programmed connections to a vertical Longline in each interconnection column.
This alternate buffer also has low skew and high fan-out.
The network formed by this alternate buffer's Longlines
can be selected to drive the K inputs of the CLBs. CMOS
threshold, high speed access to this buffer is available
from the third pad from the bottom of the right die edge.
Internal Busses
A pair of 3-state buffers, located adjacent to each CLB,
permits logic to drive the horizontal Longlines. Logic operation of the 3-state buffer controls allows them to
implement wide multiplexing functions. Any 3-state buffer
input can be selected as drive for the horizontal long-line
bus by applying a Low logic level on its 3-state control line.
See Figure 15a. The user is required to avoid contention
which can result from multiple drivers with opposing logic
ON-CHIP
3-STATE
BUFFERS
PULL-UP
RESISTORS<
FOR ON-CHIP
OPEN DRAIN
SIGNALS
L-T""'I..U.-----rl--,.:x=:;;..-----,-==-----,-=:o:...-ttt--r=x.:..
2 HORIZONTAL LONG LINES
··El
t- ..
.::.i5
...
. 1- .. ;
.::r5
..
. t-·.;
·rt . . :
.. t· ..
X1243
Figure 13. Horizontal and Vertical Longlines. These Longlines provide high fan-out, low-skew signal distribution in each row and
column. The global buffer in the upper left die comer drives a common line throughout the LeA device.
2-109
II
XC3000, XC3000A, XC3000L, XC31 00 Logic Cell Array Families
levels. Control of the 3-state input by the same signal that
drives the buffer input; creates an open-drain wired-AND
function. A logic High on both buffer inputs creates a high
impedance, which represents no contention. A logic Low
enables the buffer to drive the Longline Low. See Figure
15b. Pull-up resistors are available at each end of the
Longline to provide a High output when all connected
buffers are non-conducting. This forms fast, wide gating
functions. When data drives the inputs, and separate
signals drive the 3-state control lines, these buffers form
multiplexers (3-state busses). In this case, care must be
used to prevent contention through multiple active buffers
o '.. .__~~====~~~====~~~==~~====~========~~.---I/OBLOCKCLOCKNETS
~.~
(2 PER DIE EDGE)
.. flR======;~~i=~~IlF=~~i!==~~H~~9ij=~
HORIZONTAL
LONG LINES
3-STATE
BUFFERS
X124(
Figure 14. Programmable Interconnection of Longlines. This is provided at the edges of the routing area. Three-state buffers
allow the use of horizontal Longlines to form on-chip wired AND and multiplexed buses. The left two non-clock vertical Longlines
per column (except XC3020) and the outer perimeter Longlines may be programmed as connectible half-length lines.
vee
f
Vee
~
Z=DA·OS·OC· ... ·ON
,~
DN:
X3036
Figure 15a. 3-StateBuffers Implement a Wired-AND Function. When all the buffer 3-state
lines are High, (high impedance), the pull-up resistor(s) provide the High output. The buffer
inputs are driven by the control signals or a Low.
X1741
Figure 15b. 3-State Buffers Implement a Multiplexer. The selection is accomplished by the buffer 3-state signal.
2-110
option is available to assure symmetry. The oscillator
circuit becomes active early in the configuration process to
allow the oscillator to stabilize. Actual internal connection
is delayed until completion of configuration. In Figure 17
the feedback resistor R1, between the output and input,
biases the amplifier at threshold. The inversion of the
amplifier, together with the R-C networks and an AT-cut
series resonant crystal, produce the 36D-degree phase
shift of the Pierce oscillator. A series resistor R2 may be
included to add to the amplifier output impedance when
needed for phase-shift control, crystal resistance matching, or to limit the amplifier input swing to control clipping
at large amplitudes. Excess feedback voltage may be
corrected by the ratio of C2IC1. The amplifier is deSigned
to be used from 1 MHz to about one-half the specified CLB
toggle frequency. Use at frequencies below 1 MHz may
require individual characterization with respect to a series
of conflicting levels on a common line. Each horizontal
Longline is also driven by a weak keeper circuit that
prevents undefined floating levels by maintaining the previous logic level when the line is not driven by an active
buffer or a pull-up resistor. Figure 16 shows 3-state buffers, Longlines and pull-up resistors.
Crystal Oscillator
Figure 16 also shows the location of an internal high speed
inverting amplifier which may be used to implement an onchip crystal oscillator. It is associated with the auxiliary
buffer in the lower right corner of the die. When the
oscillator is configured by MakeBits and connected as a
signal source, two special user lOBs are also configured to
connect the oscillator amplifier with external crystal oscillator components as shown in Figure 17. A divide by two
BIDIRECTIONAL
INTERCONNECT
BUFFERS
II I
II
19o
I
/
I
3 VERTICAL LONG
LINES PER COLUMN
I
.1
- -
-dJ
~D
t
/
y
A
~
1:0
I
'w'-l
I
1'ilH-1
I
~
J
'-n-
~
-
~
'-n-
:t
:O~
_e:J e:J
~ ...y~-
hJ
~"J
tI:
I1
e:Jeo.
HORIZONTAL LONG LINE
PULL-UP RESISTOR
HORIZONTAL LONG LINE
'P47
r-
110 CLOCKS
p./
1
11
A
-
--~U
I
r-
I
"r--
II
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~
l'\.""\.
1
-
"
~I
--.I
t
GLOBAL NET"
~
'--
~
P
V
V
OSCILLATOR
AMPLIFIER OUTPUT
DI RECTINPUT OF P47
TO AUXILIARY BUFFER
CRYSTAL OSCILLATOR
VIBUFFER
-
- -- ~ r--
3-STATE INPUT
3-STATE CONTROL
,..-...... 3·STATE BUFFER
.q.ok
[J
D
D
D
ALTERNATE BUFFER
D
D
~
X1245
\ OSCILLATOR
AMPLIFIER INPUT
Figure 16. XACT Development System. An extra large view of possible interconnections in the lower right corner of the XC3020.
2-111
II
XC3000, XC3000A, XC3000L, XC3100 Logic Cell Array Families
Internal
Alternate
Clock Buffer
External
XTAL1
D
D
XTAL2
(IN)
R1
Suggested Component Values
R1 0.5-1 MG
R2 0-1 kG
(may be required for low frequency, phase)t
(shift andlor compensation level for crystal Q)
C1, C2 10 - 40 pF
Y1 1 - 20 MHz AT-cut parallel resonant
I XTAL 1 (OUT)
I XTAL2 (IN)
44PIN
68 PIN
PLCC
30
26
PLCC
PLCC
47
43
53
I
__ C1
_
100 PIN
84 PIN
57
I
I
I
PGA
J11
L11
R2
0
Y1
CQFP
67
61
I PQFP
I 82
I 76
IC2
132 PIN
160 PIN
PGA
PQFP
P13
M13
82
76
164 PIN
CQFP
105
99
175 PIN 208 PIN
PQFP
PGA
T14
110
P15
100
X3172
Figure 17. Crystal Oscillator Inverter. When activated in the MakeBits program and by selecting an output network for its buffer,
the crystal oscillator inverter uses two unconfigured package pins and external components to implement an oscillator. An optional
divide-by-two mode is available to assure symmetry.
resistance. Crystal oscillators above 20 MHz generally
require a crystal which operates in a third overtone mode,
where the fundamental frequency must be suppressed by
an inductor across C2, turning this parallel resonant circuit
to double the fundamental crystalfrequency, i.e., 2/30fthe
desired third harmonic frequency network. When the oscillator inverter is not used, these lOBs and their package
pins are available for general user I/O.
Programming
Table 1
Initialization Phase
An internal power-on-reset circuit is triggered when power
is applied. When Vcc reaches the voltage atwhich portions
of the LCA device begin to operate (nominally 2.5 to 3 V),
the programmable I/O output buffers are disabled and a
high-impedance pull-up resistor is provided for the user
I/O pins. A time-out delay is initiated to allow the power
supply voltage to stabilize. During this time the powerdown mode is inhibited. The Initialization state time-out
(about 11 to 33 ms) is determined by a 14-bit counter
driven by a self-generated internal timer. This nominal 1MHz timer is subject to variations with process, temperature and power supply. As shown in Table 1, five configuration mode choices are available as determined by the
input levels of three mode pins; MO, M1 and M2.
In Master configuration modes, the LCA device becomes
the source of the Configuration Clock (CCLK). The beginning of configuration of devices using Peripheral or Slave
modes must be delayed long enough for their initialization
to be completed. An LCA device with mode lines selecting
a Master configuration mode extends its initialization state
using four times the delay (43 to 130 ms) to assure that all
daisy-chained slave devices, which it may be driving, will
2-112
~XIUNX
be ready even if the master is very fast, and the slave(s)
very slow. Figure 18 shows the state sequences. At the
end of Initialization, the LCA device enters the Clear state
where it clears the configuration memory. The active Low,
open-drain initialization signal INIT indicates when the
Initialization and Clear states are complete. The LCA
device tests for the absence of an external active Low
RESET before it makes a final sample of the mode lines
and enters the Configuration state. An external wired-AND
of one or more INIT pins can be used to control configuration by the assertion of the active-Low RESET of a master
mode device or to Signal a processor that the LCA devices
are not yet initialized.
If a configuration has begun, a re-assertion of RESET for a
minimum of three internal timer cycles will be recognized
and the LCA device will initiate an abort, returning to the
Clear state to clear the partially loaded configuration
memory words. The LCA device will then resample RESET
and the mode lines before re-entering the Configuration
state. A re-program is initiated when a configured LCA
device senses a High-to-Low tranSition on the DONE!
PROG package pin. The LCA device returns to the Clear
state where the configuration memory is cleared and mode
lines re-sampled, as for an aborted configuration. The
complete configuration program is cleared and loaded
during each configuration program cycle.
Length count control allows a system of multiple Logic Cell
Arrays, of assorted sizes, to begin operation in a synchro-
nized fashion. The configuration program generated by
the MakePROM program of the XACT development system begins with a preamble of 111111110010 followed by
a 24-bit length count representing the total number of
configuration clocks needed to complete loading of the
configuration program(s). The data framing is shown in
Figure 19. All LCA devices connected in series read and
shift preamble and length count in on positive and out on
negative configuration clock edges. An LCA device which
has received the preamble and length count then presents
a High Data Out until it has intercepted the appropriate
number of data frames. When the configuration program
memory of an LCA device is full and the length count does
not yet compare, the LCA device shifts any additional data
through, as it did for preamble and length count.
When the LCA device configuration memory is full and the
length count compares, the LCA device will execute a
synchronous start-up sequence and become operational.
See Figure 20. Two CCLK cycles after the completion of
loading configuration data, the user 1/0 pins are enabled
as configured. As selected in MakeBits, the internal userlogic RESET is released either one clock cycle before or
after the 1/0 pins become active. A similar timing selection
is programmable for the DONE!PROG output signal.
DONE!PROG may also be programmed to be an open
drain or include a pull-up resistor to accommodate wired
ANDing. The High During Configuration (HDC) and Low
During Configuration (LDC) are two user 1/0 pins which are
driven active while an LCA device is in its Initialization,
Power.()n Delay is
214 Cycles for Non·Master Mode-11 to 33 ms
2 16 Cycles for Master Mode-43 to 130 ms
User 1/0 Pins wijh High Impedance Pull·Up.
HDC~High. LDC~Low
A
tr__________n_ij_s~Jn_a_IL_ow
______
~
I
!
[ PWRDWN
,. Inactive
PWRDWN
Active
I
Low on DONE/PROGRAM and RESET
Clear Is
- 200 Cycles for the
- 250 Cycles for the
- 290 Cycles for the
- 330 Cycles for the
- 375 Cycles for the
XC3020-130 to 400 ~s
XC3030-165 to 500 ~s
XC3042-195 to 580 ~s
XC3064-220 to 660 ~s
XC3090-250 to 750 ~s
Operaleson
User Logic
X3173
Figure 18. A State Diagram of the Configuration Process for Power-up and Reprogram.
2-113
II
XC3000, XC3000A, XC3000L, XC3100 Logic Cell Array Families
Clear or Configure states. They and DONEIPROG provide
signals for control of external logic signals such as RESET,
bus enable or PROM enable during configuration. For
parallel Master configuration modes, these signals provide PROM enable control and allow the data pins to be
shared with user logic signals.
CMOS thresholds. The threshold of PWRDWN and the
direct clock inputs are fixed at a CMOS level.
If the crystal oscillator is used, it will begin operation before
configuration is complete to allow time for stabilization
before it is connected to the internal circuitry.
Configuration Data
User lID inputs can be programmed to be either TTL or
CMOS compatible thresholds. At power-up, all inputs
have TTL thresholds and can change to CMOS thresholds
at the completion of configuration if the user has selected
11111.11 1
0010
< 24-Bit Length Count>
1111
Configuration data to define the function and interconnection within a Logic Cell Array is loaded from an external
storage at power-up and after a recprogram signal. Several
-Dummy Bits'
-Preamble Code
-Configuration Program Length
-Dummy Bits (4 Bits Minimum)
o : 111
o 111
o 111
ForXC3020
197 Configuration Data Frames
Program Data
(Each Frame Consists of:
A Start Bit (0)
A 71-Bit Data Field
Three Stop Bits
.
.
.
o 111
o 111
1111
Repeated for Each Logic
Cell Array in a Daisy Chain
Postamble Code (4 Bits Minimum)
'The LCA Device Requires Four Dummy
B~s
Min; the XACT Development System Generates Eight Dummy Bits
X2952
XC3020
XC3020A
XC3020L
XC3120
XC3030
XC3030A
XC3030L
XC3130
XC3042
XC3042A
XC3042L
XC3142
XC3064
XC3064A
XC3064L
XC3164
XC3090
XC3090A
XC3090L
XC3190
XC3195
Gates
1,300 to
1,800
2,000 to
2,700
2,000 to
3,700
4,000 to
5,500
5,000 to
7,500
6,500 to
9,000
ClBs
Row x Col
64
(8 x 8)
100
(10 x 10)
144
(12 x 12)
224
(16 x 14)
320
(20 x 16)
484
(22 x 22)
lOBs
64
80
96
120
144
176
Flip-flops
256
360
480
688
928
1,320
Horizontal longlines
16
20
24
32
40
44
TBUFslHorizontalll 9
11
13
15
17
23
Bits per Frame
75
(includingl start and 3 stop bits)
92
108
140
172
188
Device
Frame.s
197
Program Data =
14,779
Bits x Frames + 4 bits
(excludes header)
PROM size (bits)
Program Data
+ 40-bit Header
=
14,819
241
285
329
22,176
30,784
46,064
22,216
30,824
46,104
"./',
(373 ')
'-~o//
505
64,160
94,944
64,200
94,984
Figure 19. Internal Configuration Data Structure for an LCA Device. This shows the preamble, length count and data frames
generated by the XACT Development System.
The length Count produced by the MakeBits program = [(40-bit preamble + sum of program data + 1 per daisy chain device)
rounded up to multiple of 8)- (2 .,; K .,; 4) where K is a function of DONE and RESET timing selected. An additional 8 is added
if roundup increment is less than K. K additional clocks are needed to complete start-up after length count is reached.
2-114
~-~-
Last Frame
Data Frame
4
~--------~------~------~~.
•• ~'rj----------~I
.-----------
3
-
DIN
Length Count
Start
Bit
Length Count'
Start
Btt
The configuration data consists of a composite
• 4O-bit preamblellength count, followed by one or
more concatenated LCA programs, separated by
4-btt postambles. An additional final postamble btt
Is added for each slave device and the resuR rounded
up to a byte boundary. The length count is two less
than the number of resuRing bits.
WeakPuil-Up
110 Active
DONE
Timing of the assertion of DONE and
termination of the INTERNAL RESET
may each be programmed to occur
one cycle before or after the 110 outputs
become active.
Intemal Reset
Heavy lines Indicate the defaun condition
X3030
figure 20. Configuration and Start-up of One or More LCA Devices.
methods of automatic and controlled loading of the required data are available. Logic levels applied to mode
selection pins at the start of configuration time determine
the method to be used. See Table 1. The data may be
either bit-serial or byte-parallel, depending on the configuration mode. The different LCA devices have different
sizes and numbers of data frames. To maintain compatibility between various device types, the Xilinx product families use compatible configuration formats. For the
XC3020, configuration requires 14779 bits for each device, arranged in 197 data frames. An additional 40 bits are
used in the header. See Figure 20. The specific data
format for each device is produced by the MakeBits
command of the development system and one or more of
these files can then be combined and appended to a length
count preamble and be transformed into a PROM format
file by the MakePROM command of the XACT development system. A compatibility exception precludes the use
of an XC2000-series device as the master for XC3000series devices if their DONE or RESET are programmed
to occur after their outputs become active.
The Tie Option of the MakeBits program defines output
levels of unused blocks of a design and connects these to
unused routing resources. This prevents indeterminate
levels that might produce parasitiC supply currents. If
unused blocks are not sufficient to complete the tie, the
Flagnet command of EDITLCA can be used to indicate
nets which must not be used to drive the remaining unused
routing, as that might affect timing of user nets. Norestore
will retain the results of tie for timing analysis with Querynet
before Restore returns the design to the untied condition.
Tie can be· omitted for quick breadboard iterations where
a few additional milliamps of Icc are acceptable.
The configuration bitstream begins with eight High preamble bits, a 4-bit preamble code anda 24-bit length count.
When configuration is initiated, a counter in the LCA device
is set to zero and begins to count the total number of
configuration clock cycles applied to the device. As each
configuration data frame is supplied to the LCA device, it is
internally assembled into a data word, which is then loaded
in parallel into one word of the internal configuration
memory array. The configuration loading process is complete when the current length count equals the loaded
length count and the required configuration program data
frames have been written. Internal user flip-flops are held
Reset during configuration.
Two liser-programmable pins are defined in the unconfigured Logic Cell array. High During Configuration (HOC)
and Low During Configuration (LDC) as well· as
DONEIPROG may be used as external control signals
during configuration. In Master mode configurations it is
convenient to use LDC as an active-Low EPROM Chip
Enable. After the last configuration data bit is loaded and
2-115
II
XC3000, XC3000A, XC3000L, XC31 00 Logic Cell Array Families
Daisy Chain
the length count compares, the user 1/0 pins become
active. Options in the MakeBits program allow timing
choices of one clock earlier or later for the timing of the end
of the internal logic RESET and the assertion of the DONE
signal. The open-drain DONEIPROG output can be ANDtied with multiple LCA devices and used as an active-High
READY, an active-Low PROM enable or a RESETto other
portions of the system. The state diagram of Figure 18
illustrates the configuration process.
The XACT development system is used to create a composite configuration for selected LCA devices including: a
preamble, a length count for the total bitstream, multiple
concatenated data programs and a postamble plus an
additional fill bit per device in the serial chain. After loading
and passing-on the preamble and length count to a possible daisy-chain, a lead device will load its configuration
data frames while providing a High DOUT to possible
down-stream devices as shown in Figure 22. Loading
continues while the lead device has received its configuration program and the current length count has not reached
the full value. The additional data is passed through the
lead device and appears on the Data Out (DOUT) pin in
serial form. The lead device also generates the Configuration Clock (CCLK) to synchronize the serial output data
and data in of down-stream LCA devices. Data is read in
on DIN of slave devices by the positive edge of CCLK
and shifted out the DOUT on the negative edge of CCLK.
A parallel Master mode device uses its internal timing
generator to produce an internal CCLK of 8 times its
EPROM address rate, while a Peripheral mode device
produces a burst of 8 CCLKs for each chip select and writestrobe cycle. The internal timing generator continues to
operate for general timing and synchronization of inputs in
all modes.
Master Mode
In Master mode, the LCA device automatically loads
configuration data from an external memory device. There
are three Master modes that use the internal timing source
to supply the configuration clock (CCLK) to time the
incoming data. Master Serial mode uses serial configuration data supplied to Data-in (DIN) from a synchronous
serial sou rce such as the Xilinx Serial Configuration PROM
shown in Figure 21. Master Parallel Low and High modes
automatically use parallel data supplied to the 00-07 pins
in response to the 16-bit address generated by the LCA
device. Figure 22 shows an example of the parallel Master
mode connections required. The LCA HEX starting address is 0000 and increments for Master Low mode and it
is FFFF and decrements for Master High mode. These two
modes provide address compatibility with microprocessors which begin execution from oppOSite ends of memory.
Special Configuration Functions
Peripheral Mode
Peripheral mode provides a simplified interface through
which the device may be loaded byte-wide, as a processor
peripheral. Figure 23 shows the peripheral mode connections. Processor write cycles are decoded from the common assertion ofthe active low Write Strobe (WS), and two
active low and one active high Chip Selects (CSO, CS1,
CS2). The LCA device generates a configuration clock
from the internal timing generator and serializes the parallel input data for internal framing or for succeeding slaves
on Data Out (DOUT). A output High on READYIBUSY pin
indicates the completion of loading for each byte when the
input register is ready for a new byte. As with Master
modes, Peripheral mode may also be used as a lead
device for a daisy-chain of slave devices.
The configuration data includes control over several special functions in addition to the normal user logic functions
and interconnect.
Slave Serial Mode
Prior to the completion of configuration all LCA device
input thresholds are TTL compatible. Upon completion of
configuration, the input thresholds become either TTL or
CMOS compatible as programmed. The use of the TTL
threshold option requires some additional supply current
for threshold shifting. The exception is the threshold of the
PWRDWN input and direct clocks which always have a
CMOS input. Prior to the completion of configuration the
user 1/0 pins each have a high impedance pull-up. The
configuration program can be used to enable the lOB pull-
Slave Serial mode provides a simple interface for loading
the Logic Cell Array configuration as shown in Figure 24.
Serial data is supplied in conjunction with a synchronizing
input clock. Most Slave mode applications are in daisychain configurations in which the data input is driven from
the previous Logic Cell Array's data out, while the clock is
supplied by a lead device in Master or Peripheral mode.
Data may also be supplied by a processor or other special
circuits.
•
•
•
•
•
•
Input thresholds
Readback disable
DONE pull-up resistor
DONE timing
RESET timing
Oscillator frequency divided by two
Each of these functions is controlled by configuration data
bits which are selected as part of the normal XACT
development system bitstream generation process.
Input Thresholds
2-116
up resistors in the Operational mode to act either as an
input load or to avoid a floating input on an otherwise
unused pin.
Readback
The contents of a Logic Cell Array may be read back if it
has been programmed with a bitstream in which the
Readback option has been enabled. Readback may be
used for verification of configuration and as a method of
determining the state of internal logic nodes during debugging. There are three options in generating the configuration bitstream.
• "Never" inhibits the Readback capability.
• "One-time," inhibits Readback after one Readback
has been executed to verify the configuration.
• "On-command" allows unrestricted use of Readback.
Readback is accomplished without the use of any of the
user 1/0 pins; only MO, M1 and CCLK are used. The
initiation of Readback is produced by a Low to High
transition ofthe MO/RTRIG(Read Trigger) pin. The CCLK
input must then be driven by external logic to read back the
configuration data. The first three Low-to-High CCLK
transitions clock out dummy data. The subsequent Lowto-High CCLK transitions shift the data frame information
out on the M1/RDATA (Read Data) pin. Note thatthe logic
polarity is always inverted, a zero in configuration becomes a one in Readback, and vice versa. Note also that
each Readback frame has one Start bit (read back as a
one) but, unlike in configuration, each Readback frame
has only one Stop bit (read back as a zero). The third
leading dummy bit mentioned above can be considered
the Start bit of the first frame. All data frames must be read
back to complete the process and return the Mode Select
and CCLK pins to their normal functions.
Readback data includes the current state of each CLB
flip-flop, each input flip-flop or latch, and each device pad.
These data are imbedded into unused configuration bit
positions during Readback. This state information is used
by the XACT development system In-Circuit Verifier to
provide visibility into the internal operation of the logic
while the system is operating. To readback a uniform timesample of all storage elements, it may be necessary to
inhibit the system clock.
Reprogram
To initiate a re-programming cycle, the dual-function pin
DONEIPROG must be given a High-to-Low transition. To
reduce sensitivity to noise, the input signal is filtered for two
cycles of the LCA device internal timing generator. When
reprogram begins, the user-programmable 1/0 output buffers are disabled and high-impedance pull-ups are provided forthe package pins. The device returns to the Clear
state and clears the configuration memory before it indicates 'initialized'. Since this Clear operation uses chipindividual internal timing, the master might complete the
Clear operation and then start configuration before the
slave has completed the Clear operation. To avoid this
problem, the slave INIT pins must be AND-wired and used
to force a RESET on the master (see Figure 22). Reprogram control is often implemented using an external opencollector driver which pulls DONEIPROG Low. Once a
stable request is recognized, theDONElPROG pin is held
Low until the new configuration has been completed. Even
ifthe re-program request is externally held Low beyond the
configuration period, the LCA device will begin operation
upon completion of configuration.
DONE Pull-up
DONEIPROG is an open-drain 1/0 pin that indicates the
LCA device is in the operational state. An optional internal
pull-up resistor can be enabled by the user of the XACT
development system when MAKEBITS is executed. The
DONE/PROG pins of multiple LCA devices in a daisychain may be connected together to indicate all are DONE
or to direct them all to reprogram.
DONE Timing
The timing of the DONE status signal can be controlled by
a selection in the MakeBits program to occur either a CCLK
cycle before, or after, the outputs going active. See Figure
20. This facilitates control of external functions such as a
PROM enable or holding a system in a wait state.
RESET Timing
As with DONE timing, the timing of the release of the
internal reset can be controlled by a selection in the
MakeBits program to occur either a CCLK cycle before, or
after, the outputs going active. See Figure 20. This reset
keeps all user programmable flip-flops and latches in a
zero state during configuration.
Crystal Oscillator Division
A selection in the MakeBits program allows the user to
incorporate a dedicated divide-by-two flip-flop between
the crystal oscillator and the alternate clock line. This
guarantees a symmetrical clock signal. Although the frequency stability of a crystal oscillator is very good, the
symmetry of its waveform can be affected by bias or
feedback drive.
The following seven pages describe the different configuration modes in detail
2-117
II
XC3000, XC3000A, XC3000L, XC3100 Logic Cell Array Families
Master Serial Mode
• IF READBACK IS
ACTIVATED. A
5-kn RESISTOR IS
REQUIRED IN
SERIES WITH M1
DURING CONFIGURATION
THE 5 kn M2 PULL-DOWN
RESISTOR OVERCOMES THE
INTERNAL PULL-UP.
BUT IT ALLOWS M2 TO
BE USER VO.
J
1 I
MO
M1
T
PWRDWN
OPTIONAL
L.=
GENERALPURPOSE
USERVO
PINS
-
DOUT
-
M2
-
HOC
--<
LDC
--<
INIT
-
L...., DAISY·CHAINED
LCAsWITH
,...
~~~~E~~TlONS
)-
VOPINS
-
XC3000
LCA
DEVICE
f-----.+
,...
~(;~~AS
~g:F:g~~~~~s
+5V
I
RESET-.........c RESET
Vec
DIN
VpP
-
DATA
CCLK
eLK
I
DIP
SCP
CE
CEO
OEiRESET
XC17XX
(LOW RESETS THE XC17XX ADDRESS POINTER)
r----------------1
-I
DATA
CLK
CE
•
CASCADED
,
SERIAL
MEMORY
Il'
OEiRESET
_______________J
X3027
Figure 21. Master Serial Mode
In Master Serial mode, the CCLK output of the lead LCA
device drives a Xilinx Serial PROM thatfeeds the LCA DIN
input. Each rising edge of the CCLK output increments the
Serial PROM internal address counter. This puts the next
data bit on the SPROM data output, connected to the LCA
DIN pin. The lead LCA device accepts this data on the
subsequent rising CCLK edge.
The lead LCA device then presents the preamble data
(and all data that overflows the .Iead device) on its DOUT
pin. There is an internal delay of 1.5 CCLK periods, which
means that DOUT changes on the falling CCLK edge, and
the next LCA device in the daisy-chain accepts data on the
subsequent rising CCLK edge.
The SPROM CE input can be driven from either LDC or
DONE. Using LDC avoids potential contention on the DIN
pin, if this pin is configured .as user-I/O, but LDC is then
restricted to be a permanently High user output. Using
DONE also avoids contention on DIN, provided the early
DONE option is invoked.
2-118
Master Serial Mode Programming Switching Characteristics
CCLK
(OUTPUT)
SERIAL DATA IN
SERIAL DOUT
(OUTPUT) _ _ _ _ _- J ' - -_ _ _ _ _---J
' - - _ _ _ _ _---J ' - -_ _ _ _ _ _ __
Speed Gr~de
Description
CCLK3
Data In setup
Data In hold
Min
Max
Units
Symbol
1 TDSCK
2 CKDS
60
0
Notes: 1. At power-up, V cc must rise from 2.0 V to V cc min in less than 25 ms. If this is not possible, configuration can be
delayed by holding RESET Low until V cc has reached 4.0 V (2.5 V for the XC3000L). A very long V cc rise time of
> 100 ms, or a non-mon~tonically rising V cc may require> 1-llS High level on RESET, followed by a >6-j.1s Low
level on RESET and DIP after V cc has reached 4.0 V (2.5 V for the XC3000L_)._
2. Configuration can be controlled by holding RESET Low with or until after the INIT of all daisy-chain slave-mode
devices is High.
3. Master-serial-mode timing is based on slave-mode testing.
2-119
ns
ns
II
XC3000, XC3000A, XC3000L, XC3100 Logic Cell Array Families
Master Parallel Mode
·,f
+5 V -T-t--r---,
+SlV
Readback is
Activated, a
+5V
5-k Resistor Is
MO MIPWROWN
Required In
Series WIth M1
5k
CCLK
LK
OOUTI--------------------rl,. ~N
HOC
RCLK
Genenol-
\.
AI5
AI5
HOC
AI4
AI4
LOC
AI3
AI3
AI2 EPROM
--, AI2
OIher
,>
All
LCA AID
Master
A9
AIO
07
I>B
05
A7
05
AS
04-
AS
03
A4
D2
A3
01
'A2
DO
OIher{
DOUT
leA
Slave In M2
HPC
Genaral-
LOC
Purpose
User 110
~.r{
I/O Pins
Pins
VOPlns
All
VOPtnB
5k
CCLK
LCA
~~#I M2
M2
Purpose
UaarVO
Pins
5k
DOUT 1+--'>,>------1 DIN
INIT
GeneralPurpose
UserVO
Pins
INIT
A9
DIP
DiP
AS
RESET
Raaat
Note: XC2000 Devices Do Not
Have INIT to Hold Off a Master
Device. Reset of a Master Device
Should be Asaarted by an Extemal
Timing Circuit to Allow for LeA cell<
Variations In Clear State Time.
AI
AD
-DiP
RESET
+5V
5k Each
=-~r-----------------~~----~0pM
Reprogram
Collector
X3159
Figure 22. Master Parallel Mode
In Master Parallel mode, the lead LCA device directly
addresses an industry-standard byte-wide EPROM and
accepts eight data bits right before incrementing (or
decrementing) the address outputs.
The eight data bits are serialized in the lead LCA device,
which then presents the preamble data (and all data that
overflows the lead device) on the DOUT pin. There is an
internal delay of 1.5 CCLK periods, after the rising CCLK
edge that accepts a byte of data, and also changes the
EPROM address, until the falling CCLK edge that makes
the LSB (DO) ofthis byte appear at DOUT. This means that
DOUT changes on the falling CCLK edge, and the next
LCA device in the daisy chain accepts data on the subsequent rising CCLK edge.
2-120
Master Parallel Moc(e Programming Switching Characteristics
AD-A15
ADDRESS lor BYTE n + 1
ADDRESS lor BYTE n
(OUTPUT)
00-07
RCLK
(OUTPUT)
1 4,=- =- =- =- =- _~1"_-7C-C-l.Ks-======-::~--
I
CCLK
(OUTPUT)
II
DOUT
(OUTPUT)
BYTE n-1
Description
RCLK
To address valid
To data setup
To data hold
RCLKHigh
RCLKLow
Symbol
1
2
3
T RAC
TDRC
TRCD
TRCH
TRCL
Min
Max
0
60
0
600
4.0
200
Units
ns
ns
ns
ns
j.lS
...
Notes: 1. At power-up, Vcc must rise from 2.0 V to Vee min in less than 25 ms; If this is not possible, configuration can be
delayed by holding RESET Low until Vcc has reached 4.0 V (2.5 V for the XC3000L). A very long Vcc rise time of
>100 ms, or a non-monotonically rising Vcc may require a> 1-1J.S High level on RESET, followed by a >6-1J.S Low
level on RESET and PIP after Vcc has reached 4.0 V (2.5 V for the XC3000LL
2. Configuration can be controlled by holding RESET Low with or until after the INIT of all daisy-chain slave-mode
devices is High.
ThIs tImIng dIagram shows that the EPROM requIrements are extremely relaxed:
EPROM ac'cBss tIme can be longer than 4000 ns. EPROM data output has no hold time requIrements.
j
F
2-121
XC3000, XC3000A, XC3000L, XC3100 Logic Cen Array Families
Peripheral Mode
r---,.----t-- +5V
CONTROL
SIGNALS
ADDRESS
BUS
DATA
BUS
MO
MtPWR
OWN
00-7
CCLK
DOUT
ADDRESS
DECODE
LOGIC
cso
t---ji-
OPTIONAL
DAISY-CHAINED
LCAs WITH DIFFERENT
CONFIGURATIONS
HOC
t.J~,
LOC
CSt
WS
.5k
M2
+5V
CS2
• IF READBACK IS
ACTIVATED, A
5-k RESISTOR IS
REQUIRED IN SERIES
WITHMt
GENERAL·
PURPOSE
USER 110
PINS
OTHER {
~PINS
RDYIBUSY
INIT
REPROGRAM
DIP
RESET
Figure 23. Peripheral Mode.
X3031
Peripheral mode uses the trailing edge of the logic AND
condition of the CSO, CS1, CS2, and WS inputs to accept
byte-wide data from a microprocessor bus. In the lead LCA
device, this data is loaded into a double-buffered UARTlike parallel-to-serial converter and is serially shifted into
the intemal logic. The lead LCA device presents the
preamble data (and all data that overflows the lead device)
on the oOUT pin.
again when the byte-wide input buffer has transferred its
information into the shift register, and the buffer is ready to
receive new data. The length of the BUSY signal depends
on the activity in the UART. If the shift register had been
empty when the new byte was received, the BUSY signal
lasts for only two CCLK periods. If tlie shift register was still
full when the new byte was received, the BUSY signal can
be as long as nine CCLK periods.
The Ready/Busy output from the lead LCA device acts as
a handshake signal to the microprocessor. ROY/BUSY
goes Low when a byte has been received, and goes High
Note that after the last byte has been entered, only seven
of its bits are shifted out. CCLK remains High with oOUT
equal to bit 6 (the next-to-Iast bit) of the last byte entered.
2-122
Peripheral Mode Programming Switching Characteristics
WRITETOLCA
CS2
00-07
CCLK
ROY/BUSY
.... _-_ ........... _. ' "
I
X3249
Description
Write
ROY
Symbol
Min
Max
Units
Effective Write time required
(Assertion of CSQ, CS1, CS2, WS)
1
TCA
100
ns
DIN Setup time required
DIN Hold time required
2
3
Toc
Tco
60
0
ns
ns
ROY/BUSY delay after end of WS
4
TWTRB
Earliest next WS after end of BUSY
5
TRBWT
0
BUSY Low time generated
6
T BUSY
2.5
60
ns
ns
9
CCLK
Periods
Notes:
1. At power-up, V cc must rise from 2.0 V to Vcc min in less than 25 ms. If this is not possible, configuration can be
delayed by holding RESET Low until V cc has reached 4.0 V (2.5 V for the XC3000L). A very long V cc rise time of
> 100 ms, or a non-monotonically rising Vcc may require a > 1-lls High level on RESET, followed by a >6-1lS Low level
on RESET and DIP after V cc has reached 4.0 V (2.5 V for the XC3000L).
2. Configuration must be delayed until the INIT of all LCAs is High.
3. Time from end of WS to CCLK cycle for the new byte of data depends on completion of previous byte processing and
the phase of the internal timing generator for CCLK.
4. CCLK and DOUT timing is tested in slave mode.
5. T BUSY indicates that the double-buffered parallel-to-serial converter is not yet ready to receive new data. The shortest
T BUSY occurs when a byte is loaded into an empty parallel-to-serial converter. The longest T BUSY occurs when a new
word is loaded into the input register before the second-level buffer has started shifting out data.
This timing diagram shows very relax'ed requirements: Data need not be held beyond the rising edge of Ws. BUSY will
go active within 60 ns after the end of Ws. BUSY will stay active for several microseconds. WS may be asserted Immediately after the end of BUSY.
2-123
XC3000, XC3000A, XC3000L, XC3100 Logic Cell Array Families
Slave Serial Mode
.
+5V
I
MO
Ml
If Readback is
Activated, a
5-k Resistor is
Required in
Series with Ml
1
PWRDWN
Micro
Computer
5k
STRB
CCLK
DO
1/0
Port
DIN
DOUT
01
I---
HOC
02
I---
LDC
03 I--04
I---
05
-
+5V
LCA
07
RESET
~
'---
--
Optional
Daisy-Chained
LCAsw"h
Different
Configurations
GeneraiPurpose
User VO
Pins
-{
1/0 Pins
06
r-<
M2
DIP
INIT
RESET
X3157
Figure 24. Slave Serial Mode.
In Slave Serial mode, an external signal drives the CCLK
input(s) of the LCA device(s). The serial configuration
bitstream must be available at the DIN input of the lead
LCA device a short set-up time before each rising CCLK
edge. The lead LCA device then presents the preamble
data (and all data that overflows the lead device) on its
DOUT pin. There is an internal delay of 1.5 CCLK periods,
which means that DOUT changes on the falling CCLK
edge, and the next LCA device in the daisy-chain accepts
data on the subsequent rising CCLK edge.
2-124
Slave Serial Mode Programming Switching Characteristics
:~ =to,=~.~@,"~J
'J'" @,"~
1-",.~f-.-~~ 0 ----l~,_.
TCCH
DOur
BITN-l
(OUTPUT)
Description
CCLK
Symbol
To DOUT
3
DIN setup
DIN hold
High time
Low time (Note 1)
Frequency
1
2
Tcco
T DCC
TCCD
TCCH
TCCL
Fcc
4
5
0) TCCD
r-
:1.-------)K
Min
60
0
0.05
0.05
BITN
110531
Max
Units
100
ns
ns
ns
I-ls
5.0
10
I!S
MHz
Notes: 1. The max limit of CCLK Low time is caused by dynamic circuitry inside the LCA device.
2. Configuration must be delayed until the INIT of all LCA devices is High.
3. At power-up, V cc must rise from 2.0 V to V cc min in less than 25 ms. If this is not possible, configuration can be delayed by holding RESET Low until V cc has reached 4.0 V (2.5 V for the XC3000L). A very long Vcc rise time of > 100
ms, or a non-m()notonically rising Vcc may require a > 1-J.ls High level on RESET, followed by a >6-J.ls Low level on
RESET and DIP after V cc has reached 4.0 V (2.5 V for the XC3000L).
Program Readback Switching Characterisctics
OONEIPROG
(OUTPUT)
/
RTRIG (MO)
CCLK(1)
ROATA
(OUTPUT)
X3028
RTRIG
CCLK
Notes: 1.
2.
3.
4.
Description
RTRIG High
1
Symbol
TRTH
Min
250
RTRIG setup
RDATAdelay
High time
Low time
2
3
5
4
TRTCC
TCCRO
TCCHR
TCCLR
200
Max
100
ns
ns
5
I!S
I!S
0.5
0.5
During Readback, CCLK frequency may not exceed 1 MHz.
RETRIG (MO positive transition) shall not be done until after one ciock following active I/O pins.
Readback should not be initiated until configuration is complete.
T CCLR is 5 J.ls min to 15 J.lS max for XC3000L.
2-125
Units
ns
II
XC3000, XC3000A, XC3000L, XC31 00 Logic Cell Array Families
General LCA Switching Characteristics
,..--_ _ _--fllil--_--.((4)TMRW )
MOIM11M2
DONEIPROG
_ _ _ _ _ _ __
--f®,J®,~E-----------_________________________
. _
VALID
ll0TPGW~
___J
___-
--.[®TPGI
INIT
(OUTPUT)
USER STATE
-
..J/
______C_LEAoooiRiI-S_TA_T_E_ _ _ _ _ _ _
II
CONFIGURATION STATE
.
\'--_ _--'f
j+- NOTE 3-+j
Vcc(VALlD) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - \ \
:
,;--:;:.:----~
V
\.. - - - _ I t CCPD
1105 28
XC3000
XC31 00
Description
RESET (2)
DONEIPROG
PWRDWN (3)
MO, M1, M2 setup time required
MO, M1, M2 hold time required
RESET Width (Low) req. for Abort
Symbol
Min
4
TMR
TRM
T MRW
1
1
6
Width (Low) required for Re-config.
5
INIT response after Dip is pulled Low 6
T pGW
TpGI
6
Power Down Vcc
VCCPD
2.3
2
3
XC3000A
XC3000L
Max
Min
Max
1
3
6
!-IS
!-IS
!-IS
6
7
Units
7
2.3
!-IS
!-IS
V
Notes: 1. At power-up, Vcc must rise from 2.0 V to Vee min in less than 25 ms. If this is not possible, configuration can be delayed by holding RESET Low until Vcc has reached 4.0 V (2.5 V for XC3000L). A very long Vcc rise time of >100 ms, or
a non-monotonically rising V(;c may require a >1-jUl High level on RESET, followed by a >6-11S Low level on RESET and
DIP after Vcc has reached 4.0 V (2.5 V for XC3000L).
2. RESET timing relative to valid mode lines (MO, M1, M2) is relevant when RESET is used to delay configuration.
3. PWRDWN transitions must occur while Vcc >4.0 V(2.5 V for XC3000L).
2-126
I:XIUNX
Performance
block output is limited only by the resulting propagation
delay of the larger interconnect network. Speed performance ofthe logic block is a function of supply voltage and
temperature. See Figure 26.
Device Performance
The XC3000 families of FPGAs can achieve very high
performance. This is the result of
• A sub-micron manufacturing process, developed and
continuously being enhanced for the production of
state-of-the-art CMOS SRAMs.
Interconnect performance depends on the routing resources used to implement the signal path. Direct interconnects to the neighboring CLB provide an extremely fast
path. Local interconnects go through 'switch matrices
(magic boxes) imd suffer an RC delay, equal to the
resistance of the pass transistor multiplied by the capacitance of the driven metal line. Longliries carry the signal
across the length or breadth of the chip with only one
access delay. Generous on-chip signal buffering makes
performance relatively insensitive to Signal fan-out; increasing fan-out from 1 to 8 changes the CLB delay by only
10%. Clocks can be distnbuted with two low-skew clock
distribution networks.
• Careful optimization of transistor geometries, circuit
design, and lay-out, based on years of experience
with the XC3000 family.
• A look-up table based, coarse-grained architecture
that can collapse multiple-layer combinatorial logic
into a single function generator. One CLB can implement up to four layers of conventional logic in as little
as 2.7 ns.
Actual system performance is determined by the timing of
critical paths, including the delay through the combinatorial and sequential logic elements within CLBs and lOBs,
plus the delay in the interconnect routing. The ac-timing
specifications state the worst-case timing parameters for
the various logic resources available in the XC3000families architecture. Figure 25 shows a variety of elements involved in determining system performance.
The tools in the XACT Development System used to place
and route a design in an XC3000 FPGA (the Automatic
Place and Route [APR] program and the XACT Design
Editor)automatically calculate the actual maximum worstcase delays along each signal path. This timing information can be back-annotated to the design's netlist for use
in timing simulation or examined with X-DELAY, a static
timing analyzer.
Logic block performance is expressed as the propagation
time from the interconnect point at the input to the block to
the output of the block in the interconnect area. Since
combinatorial logic is implemented with a memory lookup
table within a CLB, the combinatorial delay through the
CLB, called TII,O' is always the same, regardless of the
function being Implemented. For the combinatorial logic
function driving the data input of the storage element, the
critical timing is data set-up relative to the clock edge
provided to the flip-flop element. The delay from the clock
source to the output of the logic block is critical in the timing
signals produced by storage elements. Loading of a logicClock to Output
I'
Actual system performance is applications dependent.
The maximum clock rate that can be used in a system is
determined by the critical Path delays within that system.
These delays are combinations of incremental logic and
routing delays, and vary from design to deSign. In a
synchronous system, the maximum clock rate depends on
the number of combinatorial logic layers between resynchronizing flip-flops. Figure 27 shows the achievable
clock rate as a function of the number of CLB layers.
Combinatorial
Setup
1+1' - - - T o p ----I
TcKo-!-Tllo-,j4I'---TlcK----,I
CLB
CLB
Logic
-p
lOB
CLB
I
I
. l
LogK:
I
r-t"""
(I<)
PAD
r--p
(I<)
,;-
CLOCK
I
lOB
f---TcKo-1
--t>-
PAD
,
I-Tp,D ---.1
TOKPO
,I
X3178
Figure 25. Primary Block Speed Factors. Actual timing is a fUnction of various block factors combined with routing
factors. Overall performance can be evaluated with the XACT timing calculator or by an optional simulation.
2-127
I
XC3000, XC3000A, XC3000L, XC31 00 logic Cell Array Families
1.00
0.80
TYPICAL COMMERCIAL
(+ 5.0 V, 2S'C)
.,
•
TYPICAL MILITARY
0.40
~
,,'
==~~W~M~M~E~RC~I~AL~7.~5
N MILITARY .l4..5_.~ - - -.,:
~IN
I" 5. V~:;:~
___ --------blL------
,
I
~---------
0.20
L ____________ _
-55
-40
- - - - MINMI~.A!IY !5~5_V2 _ - --'
------ _ _ _ _ ------------------------------------
__ - - - - - - -
-20
o
25
40
70
80
100
125
TEMPERATURE ('C)
Xl045
Figure 26. Relative Delay as a Function of Temperature, Supply Voltage and Processing Variations
Power
300
250
X~I~!-____------XC3000-125
OL-~~~----~------~------~----~
CLB Levels:
4 CLBs
3CLBs
2CLBs
Gate Levels:
(4-16)
(3-12)
(2-8)
lCLB
(1-4)
Toggle
F\ate
Figure 27. Clock Rate as a Function of Logic Complexity
Power Distribution
Power for the LCA device is distributed through a grid to
achieve high noise immunity and isolation between logic
and 1/0. Inside the LCA device, a dedicated V cc and
ground ring surrounding the logic array provides power to
the ·1/0 drivers. An independent matrix of Vcc and
groundlines supplies the. interior logic of the device. This
power distribution grid provides a stable supply and ground
for all intemallogic, providing the external package power
pins are all connected and appropriately decoupled. Typically a O.1-J.lF capacitor connected near the Vcc and
ground pins will provide adequate decoupling.
(Number of Combinational Levels between
Flip-Flops)
Output buffers capable of driving the specified 4- or 8-mA
loads under worst-case' conditions may be capable of
driving as much as 25 to 30 times that current in a best
case. Noise can be reduced by minimizing external load
capacitance and reducing simultaneous output transitions
in the same direction. It may also be beneficial to locate
heavily loaded output buffers near the ground pads. The
1/0 Block output buffers have a slew-limited mode which
should be used where output rise and fall times are not
speed critical. Slew-limited outputs maintain their dc drive
capability, but generate less external reflections and internal noise.
2-128
E:XIUNX
Dynamic Power Consumption
XC3042
XC3042A
One CLB driving 3 local interconnects
0.25
0.17
0.07
mW per MHz
One global clock buffer and clock line
2.25
1.40
0.50
mWperMHz
One device output with a 50 pF load
1.40
1.40
0.70
mWperMHz
Power Consumption
The Logic Cell Array exhibits the low power consumption
characteristic of CMOS ICs. For any design, the configuration option of TTL chip inputthreshold requires power for
the threshold reference. The power required by the static
memory cells that hold the configuration data is very low
and may be maintained in a power-down mode.
XC3042L
power loss. The Logic Cell Array has built in power-down
logic which, when activated, will disable normal operation
of the device and retain only the configuration data. All
internal operation is suspended and output buffers are
placed in their high-impedance state with no pUll-Ups.
Different from the XC3000 family which can be powered
down to a current consumption of a few microamps, the
XC3100 draws 5 mA, even in power-down. This makes
power-down operation less meaningful. In contrast, Iccpo
for the XC3000L is only 10 ItA.
Typically, most of power dissipation is produced byexternal capacitive loads on the output buffers. This load and
frequency dependent power is 25I1W/pF/MHz per output.
Another component of I/O power is the external dc loading
on all output pins.
Internal power dissipation is a function of the number and
size ofthe nodes, and the frequency at which they change.
In an LCA device, the fraction of nodes changing on a
given clock is typically low (10-20%). For example, in a
long binary counter, the total activity of all counter flip-flops
is equivalent to that of only two CLB outputs toggling at the
clock frequency. Typical global clock-buffer power is between 2.0 mWIMHz for the XC3020 and 3.5 mW/MHz for
the XC3090. The internal capacitive load is more a function .of interconnect than fan-out. With a typical load of
three general interconnect segments, each CLB output
requires about 0.25 mW per MHz of its output frequency.
Because the control storage of the Logic Cell Array is
CMOS static memory, its cells require a very low standby
current for data retention. In some systems, this low data
retention current characteristic can be used as a method
of preserving configurations in the event of a primary
To force the Logic Cell Array into the Power-Down state,
the user must pull the PWRDWN pin Low and continue
to supply a retention voltage to the Vcc pins. When normal
power is restored, Vee is elevated to its normal operating
voltage and PWRDWN is returned to a High. The Logic
Cell Array resumes operation with the same internal sequence that occurs at the conclusion· of configuration.
Internal-I/O and logic-block storage elements will be reset,
the outputs will become enabled and the DONEIPROG pin
will be released.
When Vcc is shut down or disconnected, some power
might unintentionally be supplied from an incoming signal
driving an I/O pin. The conventional electro-static input
protection is implemented with diodes to the supply and
ground. A positive voltage applied to an input (or output)
will cause the positive protection diode to conduct and
drive the Vee connection. This condition can produce
invalid power conditions and should be avoided. A large
series resistor might be used to limit the current or a bipolar
buffer may be used to isolate the input signal.
2-129
I
XC3000, XC3000A, XC3000L, XC3100 Logic Cell Array Families
Pin Descriptions
CCLK drives dynamic circuitry inside the LCA device. The
Low time may, therefore, not exceed a few microseconds.
When used as an input, CCLK must be "parked High". An
internal pull-up resistor maintains High when the pin is not
being driven.
Permanently Dedicated Pins.
Vcc
Two to eight (depending on package type) connections to
the positive V supply voltage. All must be connected.
DONEIPROG (DIp)
DONE is an open-drain output, configurable with or without an internal pull-up resistor. At the completion of configuration, the LCA device circuitry becomes active in a
synchronous order; DONE is programmed to go active
High one cycle either before or after the outputs go active.
GND
Two to eight (depending on package type) connections to
ground. All must be connected.
PWRDWN
A Low on this CMOS-compatible input stops all internal
activity, but retains configuration. All flip-flops and latches
are reset, all outputs .are 3-stated, and all inputs are
interpreted as High, independent of their actual level.
When PWDWN returns High, the LeA device becomes
operational with DONE Low for two cycles of the internal
1-MHz clock. During configuration, PWRDWN must be
High. If not used, PWRDWN must be tied toVcc'
Once configuration is done, a High-to-Low transition bfthis
pin will cause an initialization of the LCA device and start
a reconfiguration.
MOIRTRIG
As Mode 0, this input is sampled on power-on to determine
the power-on delay (214 cycles if MO is Low, 2 16 cycles if MO
is High)~ Before the start of configuration, this input is again
sampled together with M1, M2 to determine the configuration mode to be used.
REseT
This is an active Low input which has three functions.
A Low-to-High input transition, after configuration is complete, acts as a Read Trigger and initiates a Readback of
configuration and storage-element data clocked by CCLK.
By selecting the appropriate Readback option when generating the bitstream, this operation may be limited to a
single Readback, or be inhibited altogether.
Prior to the start of configuration, a Low input will delay the
start of the configuration process. An internal circuit
senses the application of power and begins· a minimal
time-out cycle. When the time-out and RESET are complete, the levels of the M lines are sampled and configura,..tion begins.
If RESET is asserted during a configuration, the LCA
device is re-initialized and restarts the configuration at the
termination of RESET.
WRESET is asserted after configuration is complete, it
provides aglqbal asynchronous RESET of all lOB and
~B st6rag~'elements of the LCA device.
CCLK
During configuration, Configuration Clock is an output of
an LCA device in Master mode or Peripheral mode, but an
input in Slave mode. During Readback, CCLK is a clock
input for shifting configuration data out of the LCA device
M1/RDATA
As Mode 1, this input and MO, M2 are sampled before the
start of configuration to establish the configuration mode to
be used. If Readback is never used, M1 can be tied directly
to ground or Vcc' If Readback is ever used, M1 must use
a 5-kn resistor to ground or Vcc' to accommodate the
RDATA output.
As an active-Low Read Data, after configuration is complete, this pin is the output of the Readback data.
2-130
I:XIUNX
User 110 Pins that can have special functions.
M2
During configuration, this input has a weak pull-up resistor.
Together with MO and M1, it is sampled before the start of
configuration to establish the configuration mode to be
used. After configuration, this pin is a user-programmable
1/0 pin.
'H
HOC
p~
During configuration, this output is held at a High level to
indicate that configuration is not yet complete. After configuration, this pin is a user-programmable VO pin.
c:e
lOC
?
During Configuration, this output is held at a Low level to
indicate that the configuration is not yet complete. After
configuration, this pin is a user-programmable 1/0 pin.
LDC is particularly useful in Master mode as a Low enable
for an EPROM, but it must then be programmed as a High
after configuration.
INIT
This is an active Low open-drain output with a weak pullup and is held Low during the power stabilization and
internal clearing of the configuration memory. It can be
used to indicate statl,ls to a configuring microprocessor or,
as a wired AND of several slave mode devices, a hold-off
sign~"
a. master mode device. After configuration this
pin becomes a user-programmable 1/0 pin.
'or
BClKIN
This is a direct CMOS leve.1 input to the alternate clock
buffer (Auxiliary Buffer) in the lower right corner.
XTl1
This user I/O pin can be used to operate as the output of
an amplifier driving an external crystal and bias circuitry.
XTL2
This user VO pin can be used as the input of an amplifier
connected to an external crystal and bias circuitry. The I/O
Block is left unconfigured. The oscillator configuration is
activated by routing a. netfrom the oscillator buffer symbol
output and by the MakeBits program.
cso, CS1, CS2, WS
These four inputs represent a set of Signals, three active
Low and one active High, that are used to control configuration-data entry in the Peripheral mode. Simultaneous
assertion of all four inputs generates a Write to the internal
data buffer. The removal of any assertion clocks in the 0007 data. In Master-Parallel mode, WS and CS2 are the AO
and A 1 outputs. After configuration, these pins are userprogrammable 1/0 pins.
RClK
During Master parallel mode configuration RCLK represents a "read" of an external dynamic memory device
(normally not used). After configuration is complete, this
pin becomes a user-programmed I/O pin.
ROY/BUSY
During Peripheral parallel mode configuration this pin
indicates when the chip is ready for another byte of data to
be written to it. After configuration is complete, this pin
becomes a user-programmed I/O pin.
00-07
This set of eight pins represents the parallel configuration
byte for the parallel Master and Peripheral modes. After
configuration is complete, they are user-programmed
I/O pins.
AO-A15
During Master Parallel mode, these 16 pins present an
address output for a configuration EPROM. After configuration, they are user-programmable I/O pins.
OIN
During Slave or Master Serial configuration, this pin is
used as a serial-data input. In the Master or Peripheral
configuration, this is the Data 0 input. After configuration is
complete, this pin becomes a user-progr~mmed I/O pin.
OOUT
During configuration this pin is used to output serialconfiguration data to the DIN pin of a daisy-chained slave.
After configuration is complete, this pin becomes a userprogrammed 110 pin;
TClKIN
This is a direct CMOS-level inputto the global clock buffer.
This pin can also be configured as a user programmable
VO pin. However, since TCLKIN is the preferred input to
the global clock net, and the global clock net should be
used as the primary clock source, this pin is usually the
clock input to the chip.
Unrestricted User 110 Pins.
110
An I/O pin may be programmed by the user to be an Input
or an Output pin following configuration. All unrestricted 1/
pins, plus the special pins mentioned on the following
page, have a weak pull-up reSistor of 50 kn to 100 kQ that
becomes active as soon as the device powers up, and
stays active until the end of configuration.
o
I
XC3000, XC3000A, XC3000L, XC31 00 Logic Cell Array Families
Configuration Pin Assignments
...
Configuration Mode
SLAVE
MASTER-SER
MASTER-HIGH
MASTER-LOW
<0:0:0>
PERIPHERAL
<1:0:1>
<1:1:1>
<1:1:0>
<1:0:0>
PWRDWNfil
PWRDWNIII
PWRDWNIII
PWROWNII
PWRDWN I
vee
vee
vr.r.
vcr.
vr.r.
Ml HIGH I
MO HIGH I
M2 HIGH I
HOCIHIGH
Lnr.1I OWl
MllLOWlII\
MO LOWl I
M2 LOW) I
HOC!HIGH)
Lnr.,LQWl
INIT"
GNe
INIT"
NO
Rl'RETII\
RESET 11\
DONE
DONE
Mill nWl 11\
MO HIGH I
M2 HIGHI I
HOCIHIGH
Lnr.1I nWl
7
12
16
17
16
19
Ml H"'''' I
MO LOW I
M2 HIGH I
HOCIHIGH)
Lnr.1I OWl
M LnWlI
MO LOWI I
M2 HIGHlIIl
HOCIHIGH\
Lnr.llnWl
20
iNrr-
iNrT-
GND
GN[
INIT"
GN[
22
23
26
27
~II\
~II\
~II\
OONE
DATA 7 I
OONE
DATA7 I
OONE
DATA7 I
26
30
DATA6 I
DATA5 I
CSO I
DATA4 I
VCC
VCC
DIN I
DOUT
CCLK I
DIN I
DOUT
CCLKfQI
DATA6 I
DATA5 I
DATA6 I
DATA" I
DATA4 I
DATA4 I
vcc
vee
vee
DATA3 I
CSll
DATA2 I
DATAl I
RDY/BUSY
DATAO I
DOUT
CCLKIOl
WSI
CS2 I
DATA3 I
DATA3 I
DATA2 I
DATAl I
RCLK
DATAO I
DOUT
CCLKIO)
AO
Al
A2
A3
GND
GND
...
38
39
40
J6
66
63
L11
Kl0
Jl0
K11
J11
.Hl0
FlO
Gl0
Gll
76
78
73
75
51
53
54
55
56
57
56
60
61
62
52
64
F9
53
54
55
56
57
56
59
60
61
62
65
66
67
70
71
72
F11
E11
El0
010
C11
B11
Cl0
A11
810
B9
Al0
A9
B6
B7
A7
C7
C6
A6
34
35
43
44
45
46
47
63
64
A2
A3
A15
A4
A4
A14
AS
~!
K6'
43
26
27
26
30
65
66
67
68
AS
1
GND
A13
A6
A12
A7
A11
AS
Al0
A9
X
Represents a 58-1dl to 1ao-Idl pull-up
INIT is an open drain output during configuration
Represents an input
Pin assignmnent for the XC3064IXC3090 and XC3195 differ from
tho~e shown. See pages 2-135.
Penpheral mode and master parallel mode are not supported In the
PC44 package. See page 2-133.
Pin assignments for the XC3195 P0208 differ from those shown. See
page 2-142.
1
2
3
4
5
6
7
8
9
X
X
12
22
31
32
33
B2
26
29
41
52
54
56
57
59
65
48
49
34
DATA2 I
DATAl I
RCLK
DATAO I
DOUT
CCLKIO)
AO
Al
A14
A5
GND
A13
A6
A12
A7
A11
Al0
A9
lill!ITli!l
10
18
25
50
A15
GND
....
175
160
44
68
64
64
100
100 132
208
PLCC PLCC PLCC PGA POFP TQFP PGA POFP PGA PQFP
F3
J2
34
Ll
K2
K3
3Il
co'
42
73
74
75
76
n
78
81
82
83
64
1
2
3
4
5
8
9
10
11
X
X
X
X··
X··
X··
AS
B5
C5
A3
A2
B3
Al
X
X
X
C8
49
B13
A14
C13
B14
014
G14
H12
M13
P14
N13
M12
P13
N11
M9
51
53
54
56
62
80
n
81
.82
78
.~
1180
67
64
85
66
88
B9
91
92
93
94
98
99
100
1
2
5
6
8
9
12
13
14
15
16
17
18
19
20
23
24
25
26
X
X
X
Al
38
79
88
89
90
91
95
96
97
98
99
2
3
5
6
9
10
11
12
13
14
15
16
17
20
21
22
26
X
X
N9
N8
M8
N7
P8
M6
M5
N4
N2
M3
Pl
M2
Nl
L2
Ll
Kl
J2
Hl
H2
H3
G2
Gl
F2
El
01
02
Bl
C2
159
20
40
42
44
45
49
59
19
76
78
B2
09
B14
B15
C15
E14
016
H15
J14
P15
R15
R14
N13
T14
P12
T11
Rl0
R9
3
26
48
50
56
57
61
n
100
102
103
106
114
115
119
120
121
124
125
128
129
132
133
136
137
139
141
142
147
148
151
152
155
156
M3
Pl
Nl
Ml
L2
K2
Kl
J3
H2
Hl
F2
El
01
Cl
E3
C2
79
100
102
107
109
110
115
122
123
128
130
132
133
138
145
146
151
152
153
161
162
165
166
172
173
178
179
182
164
185
192
193
199
200
203
204
X
X
X
X
X
X
80
81
82
66
92
93
98
N9
P8
R8
R7
R5
P5
R3
N4
R2
P2
X
X
User
Operation
PWRDWN(I)
VCC
RDATA
RTRIGII\
110
110
110
110
GND
~
110
XTL1 OR 110
110
110
110
110
Vee
110
110
110
110
110
110
I/O
CCLK I
110
110
110
110
110
110
110
110
GND
110
110
110
110
110
110
110
110
XC3020 etc,
XC3030 etc,
XC3042 etc,
XC3064 etc.
XC3090 etc.
XC3195
X3174
Note: Pin assignments of PGA Footprint PLCC sockets and PGA packages are not electrically identical. Generic I/O pins are not shown_
2-132
XC3000 Families Pin Assignments
Xilinx offers the six different array sizes in the XC3000
families in a variety of surface-mount and through-hole
package types, with pin counts from 44 to 223.
Each chip is offered in several package types to
accomodate the available pc board space and manufacturing technology. Most package types are also offered
with different chips to accomodate design changes without
the need for pc board changes.
Note that there is no perfect match between the number of
bonding pads on the chip and the number of pins on a
package. In some cases, the chip has more pads than
there are pins on the package, as indicated by the information ("unused" pads) below the line in the following table.
The lOBs of the unconnected pads can still be used as
storage elements if the specified propagation delays and
set-up times are acceptable.
In other cases, the chip has fewer pads than there are
pins on the package; therefore, some package pins are
not connected (n.c.), as shown above the line in the
following table.
Number of Package Pins
Device
Pads
XC3020
74
XC3030
98
XC3042
118
XC3064
142
XC3090
166
XC3195
44
68
54 unused
30 unused
84
100
132
175
208
9 n.c.
42 n.c.
160
223
6 unused
18 n.c.
82 unused
6 unused
9 n.c.
32 unused 10 n.c. 25 n.c.
114 unused
198
n.c.= Unconnected package pin
unused = Unbonded device pad
XC3000 Family 44-Pin PLCC Pinouts
XC3000, XC3000A, XC3000L and XC31 00 families have idential pinouts
Pin No.
XC3030, etc.
Pin No.
XC3030, etc.
1
2
3
4
5
6
GND
23
24
25
26
GND
7
8
9
10
PWRDWN
TCLKIN-I/O
27
28
29
30
110
:'11
1/0
1/0
32
110
110
110
vee
1/0
110
110
110
110
110
11
12
13
vee
110
33
34
35
1<1
JlG
:'IF>
15
16
17
18
19
20
21
22
110
110
XTl2I1NI-I/O
RESET
DONE-PGM
110
XTL 1(OUTj-BCLK·I/O
110
110
37
110
M1-RDATA
MO-RTRIG
:'Ill
DIN-lID
39
40
41
42
43
44
DOUT-I/O
M2-1/0
HOC-liD
LDC-I/O
I/O
INIT-I/O
Peripheral mode and Master Parallel mode are not supported in the PC44 package
2-133
eCLK
110
110
110
110
II
XC3000, XC3000A, XC3000L, XC31 00 Logic Cell Array Families
XC3000 Families 68-Pin PLCC, 84-Pin PLCC and PGA Pinouts
XC3000, XC3000A, XC3000L and XC31 00 fal1'lilies have identical pinouts
68PLCC
68PLCC
XC3030
XC3020
44
XC3020
XC3030, XC3042
45
DONE-~
46
07-1/0
XTL1 (OUn-BCLKIN-I/O
XC3020
10
11
XC3020
XC3030, XC3042
PWRON
TCLKIN-IIO
-
110·
84PLCC
12
13
14
12
13
VO
VO
15
16
C2
81
Cl
02
-
-
liD
17
01
15
16
14
15
18
19
E3
E2
20
El
49
50
51
21
F2
-
22
F3
52
53
54
55
XC3030
10
11
12
13
14
84PGA
B2
47
46
-
-
16
VO
VO
VO
17
18
19
17
18
110
VCC
19
23
G3
-
-
VO
VO
24
20
20
21
vo
25
26
Gl
G2
Fl
27
28
Hl
H2
57
58
59
32
Jl
Kl
J2
Ll
-
-
84PLCC
RESET
os-vo
I/O
05-VO
cso-vo
D4-1IO
liD
VCC
57
84PGA
Kl0
Jl0
Kll
Jll
58
59
Hl0
Hll
60
61
FlO
Gl0
Gll
54
55
56
•
62
63
64
G9
F9
Fl1
02-110
65
66
67
liD
68
E9
VO·
69
70
011
010
Cll
811
Cl0
76
03-1/0
<::Sf-vo
Ell
El0
21
22
22
110
110
-
VO
23
24
25
26
27
28
29
23
24
25
liD
liD
Ml-ROATA
MO-RTRIG
M2-1/0
29
30
31
33
K2
61
CCLK
AD-WS-IIO
71
72
73
74
75
HOC-I/O
34
35
K3
L2
62
63
Al-CS2-1I0
A2-1I0
77
B9
Al0
38
L3
64
37
K4
-
AS-liD
I/O.
78
79
A9
B9
30
-
26
27
28
29
liD
30
31
mc-IIO
liD
-
56
60
OHIO
ROYIBUSY-RCLK-I/O
~O-DIN-I/O
DOUT-11O
All
810
110*
38
L4
-
110·
8Q
AB
31
32
vb
39
33
I/O
40
41
42
A15-1I0
A4-1I0
Al4-IIO
AS,VO
Al3-IIO
84
1
2
86
B7
A7
C7
J6
J7
65
68
67
68
1
2
81
32
J5
K5
L7
K7
3
4
AS-liD
A12-1I0
3
4
AS
85
33
34
35
36
37
38
39
-
-
110·
34
35
38
37
38
39
40
41
iNiT-IiO
GND
liD
40
liD
46
GND
C6
AS
liD
47
L6
5
A7-1/0
5
C5
VO
46
L6
-
110·
S
A4
VO
49
-
I/O.
7
B4
VO·
50
K6
L9
S
All-liD
8
AS
110·
51
Ll0
7
AB-IIO
9
A2
42
VO
52
XTL2(IN)-I/O
53
8
9
AlO-IiO
43
K9
Lll
10
11
B3
Al
41
42
43
liD
43
44
45
L5
K6
82
63
A9-11O
Unprogrammed lOBs have a default pull-up_ This prevents an undefined pad level for unl:x>nded or unused lOBs. Programmed
outputs are defaultslew-rate limited.
This table describes the pinouts of three different chips in three different packages. The second column lists 84 of the 118 pads on
the XC3042 (and 84 of the 98 pads on the XC3030) that are connected to the 84 package pins. Ten pads, indicated by an asterisk,
do not exist on the XC3020, which hal! 74 pads; therefore the corresponding pins on the 84-pin packages have no connections to
an XC3020. Six pads on the XC3020 and 16 pads on the XC3030, indicated by a dash (-) i" the 68 PLCC column, have no
connection to the 68 PLCC, but are connected to the 84-pin packages.
2-134
XC30641XC3090/xC3195 84-Pin PLCC Pinouts
XC3000, XC3000A, XC3000L and XC3100 families have identical pinouts
PlCC
Pin Number
XC3064, XC3090, XC3195
PlCC
Pin Number
12
J5WIIDN
54
RESET
13
TClKIN-I/O
55
OONE-PG
14
1/0
56
07-1/0
15
1/0
57
XTll (OUTl-BClKIN-I/O
XC3064, XC3090, XC3195
16
VO
58
06-1/0
17
VO
59
18
1/0
60
1/0
05-1/0
19
VO
61
CSO-I/O
20
1/0
62
04-1/0
21
GND*
63
1/0
22
VCC
64
vee
23
1/0
65
GND*
24
1/0
66
03-1/0*
25
1/0
67
eSl-I/O*
26
1/0
68
02-1/0*
27
I/O
69
1/0
28
1/0
70
01-1/0
29
1/0
1/0
71
ROY/BUSY-RClK-I/O
30
72
DO-OIN-I/O
31
Ml-ROATA
73
OOUT-I/O
32
MO-RTRIG
74
eCLK
33
M2-1/0
75
AO-WS-I/O
34
HOC-I/O
76
Al-CS2-1/0
35
1/0
n
A2-1/0
36
LOC-I/O
78
A3-VO
37
1/0
79
I/O
38
1/0
80
110
39
1/0
81
A15-1/0
40
VO
82
A4-1/0
41
INIT/I/O*
83
A14-1/0
42
VCC*
GND
84
AS-I/O
1
GND
1/0
2
VCC*
A13-1/0*
43
44
45
1/0
3
46
I/O
4
A6-i/O*
47
5
A12-I/O*
46
1/0
1/0
6
A7-I/O*
49
1/0
7
110
50
1/0
8
All-I/O
51
1/0
9
AS-I/O
52
VO
10
Al0-1/0
53
XTL2(IN)-I/O
11
A9-I/O
Unprogrammed lOBs have a default pull-up. This prevents an undfined pad level for unbonded or unused lOBs. Programmed
ouptuts are default slew-rate limited.
* Different pin definition than XC3020IXC3030IXC3042 PC84 package
2-135
II
XC3000, XC3000A, XC3000L, XC31 00 Logic Cell Array Families
XC3000 Families 100-Pin QFP Pinouts
XC3000, XC3000A, XC3000L and XC31 00 families have identical pinouts.
100-pin TQFP pinout is identical to 100-pin VQFP pinout
Pin No.
CQFP PQFP TQFP
XC3020
XC3030
XC3042
Pin No.
CQFP PQFP TQFP
XC3020
XC3030
XC3042
Pin No.
XC3020
XC3030
XC3042
VO'
VO'
CQFP PQFP TQFP
1
16
13
GNO
35
50
47
17
14
A13·1/0
36
51
48
vo·
vo·
69
70
84
2
85
81
82
3
18
15
AS-I/O
37
52
49
Ml-RD
71
86
83
I/O
4
19
16
A12-1/0
36
53
50
GNO'
72
87
84
OS-I/O
5
20
17
A7-1/0
39
54
51
MO·RT
73
88
85
CSO-VO
6
21
18
40
55
52
vee'
74
89
86
04·1/0
7
22
19
vo·
vo·
41
56
53
M2-1/0
75
90
87
VO
8
23
20
A1H/0
42
57
54
HDC·I/O
76
91
88
VCC
43
58
55
VO
77
92
89
D3·1/0
44
59
56
IDC-I/O
78
93
90
CS1-1/0
02-1/0
11
26
23
A8-VO
Al0·VO
A9-VO
45
60
57
94
91
27
24
vee'
46
61
58
VO'
VO·
79
12
80
95
92
I/O
13
28
25
GNO'
47
62
59
I/O
81
96
93
14
29
26
PWRDN
48
63
60
I/O
82
97
94
110'
110'
15
30
27
TCLKIN-I/O
49
64
61
VO
83
98
95
DH/O
16
31
28
50
65
62
INIT·I/O
84
99
96
FfC[K-BUSY/RDY-I/O
51
66
63
GNO
85
100
97
DO-DIN-I/O
52
67
64
I/O
86
1
98
DOUT-I/O
CCLK
9
24
21
10
25
22
17
32
29
18
33
30
vo ..
vo·
vo·
19
34
31
I/O
53
68
65
VO
87
2
99
20
35
32
54
69
66
I/O
88
3
100
vcc'
21
36
33
VO
VO
55
70
67
I/O
89
4
1
GNO'
22
37
56
71
68
I/O
90
5
2
AO·WS-I/O
38
34
35
I/O
23
I/O
57
72
69
I/O
91
6
3
Al-CS2-1/0
24
39
36
VO
58
73
70
I/O
92
7
4
110"
25
40
37
I/O
59
74
71
vo·
93
8
5
A2-1/0
26
41
38
vee
60
75
72
VO'
94
9
6
A3·1/0
27
42
39
61
76
73
XTL2-1/0
95
10
7
28
43
40
VO
VO
62
77
74
GNO'
96
11
8
110'
110'
A15·1/0
29
44
41
I/O
63
78
75
RESET
97
12
9
30
45
42
VO
64
79
76
vee'
98
13
10
A4-1/0
31
46
43
I/O
65
80
77
DONE·PG
99
14
11
A14-1/0
32
47
44
I/O
66
81
78
D7·1/0
100
15
12
A5·1/0
33
48
45
67
82
79
BCLKIN·XTL 1·1/0
34
49
46
VO
VO
68
83
80
D6-1/0
Unprogrammed lOBs have a default pull-up. This prevents an undefined pad level for unbonded or unused lOBs.
Programmed outputs are default slew-rate limited .
• Tilis table describes the pinouts of three different chips in three different packges. The third column lists 100 of the 118 pads on the
XC3042 that are connected to the 100 package pins. Two pads, indicated by double asterisks, do not exist on the XC3030, which has
98 pads; therefore the corresponding pins have no connections. Twenty-six pads, indicated by single or double asterisks, do not exist
on the XC3020, which has 74 pads; therefore, the corresponding pins have no connections. (See table on page 2-133.)
2-136
XC3000 Families 132-Pin Ceramic and Plastic PGA Pinouts
XC3000, XC3000A, XC3000L and XC3100 families have identical pinouts
PGAPln
Number
XC3042
XC3064
C4
Al
C3
B2
PGAPln
Number
XC3042
XC3064
GND
B13
J>WFIDI'I
Cll
I/O-TCLKIN
A14
MQ-RT
012
vee
B3
VO
VO
C13
M2-1/0
M12
P13
A2
vo·
B14
HOC-VO
N12
B4
VO
VO
C14
CS
A3
vo·
VO
VO
VO
A4
B7
VO
VO
VO
VO
VO
VO
VO
C7
GND
BS
C6
AS
B6
A6
CS
A7
8S
AS
A9
89
C9
Al0
vee
VO
VO
VO
VO
VO
VO
VO
VO
VO'
VO
E12
013
PGA Pin
Number
XC3042
XC3064
PGAPln
Number
XC3042
XC3064
Ml-RO
P14
RESET
M3
OOUT-I/O
GND
Mll
N13
vee
Pl
CCLK
OONE-PG
M4
07-VO
L3
M2
AO-WS-VO
Nl
Al-CS2-VO
P12
VO
VO
Ml
Nll
06-VO
K3
VO
VO
Ml0
VO
L2
A2-VO
Pl'
Nl0
va'
Ll
A3-VO
VO
VO
K2
J3
VO
VO
M9
OS-VO
Kl
A1S-VO
N9
CSO-VO
J2
A4-VO
014
E13
LOC-VO
F12
Pl0
G13
VO
VO
VO
VO
VO
G14
E14
F13
F14
G12
H12
H14
H13
J14
J13
K14
J12
vo·
XTl1-I/O-BCLKIN
P9
vo'
11
DR
lin'
Hl
-'lO'
A14-VO
INIT-VO
NS
04-VO
H2
AS-VO
vee
P7
VO
MS
vee
GND
GND
VO
VO
VO
VO
VO
VO
VO
M7
N7
GND
H3
G3
G2
A13-VO
03-VO
Gl
A6-VO
P6
CS1-VO
Fl
VO'
N6
va'
F2
A12-VO
PS
VO'
El
A7-VO
02-VO
VO
NS
F3
E2
01
All-VO
02
AS-VO
E3
Cl
VO
VO
K12
VO
VO
P3
I/O
MS
OHIO
M14
I/O
N4
A13
VO'
VO
VO'
C12
VO
Cl0
811
A12
812
K13
L14
l13
vee
M6
VO
VO
VO
810
All
vee
GND
vo·
P4
N14
VO
P2
M13
l12
XTL2(IN)-VO
N3
RCO<-8USY/ROY-VO
VO
VO
GND
N2
OO-OIN-VO
I/O
81
AlO-VO
C2
A9-VO
03
vee
Unprogrammed lOBs have a default pull-up. This prevents an undefined pad level for un bonded or unused 10Bs_ Programmed
outputs are default slew-rate limited.
, Indicates unconnected package pins (14) for the XC3042.
2-137
I
XC3000, XC3000A, XC3000L, XC31 00 Logic Cell Array Families
XC3000 Families 144-Pin Plastic TQFP Pinouts
XC3000A, XC3000L and XC31 00 families have identical pinouts
Pin
Pin
Pin
Number
Xe3042A
Number
Xe3042A
Number
Xe3042A
1
PWRDN
51
98
2
I/O-TCLKIN
52
4
VO
1/0
VO
54
1/0
1/0
DH/O
RCLK-BUSY/RDY-I/O
VO
1/0
56
58
12
VO
1/0
1/0
1/0
IN IT-I/O
vee
GND
1/0
1/0
1/0
59
13
1/0
60
14
1/0
5
7
8
10
11
53
55
100
102
103
104
107
1/0
1/0
DO-DIN-I/O
DOUT-I/O
1/0
108
CCLK
1/0
109
vee
61
I/O
110
GND
57
105
106
16
I/O
62
1/0
111
AO-WSI/O
17
1/0
65
112
Al-CS2-1/0
18
GND
66
1/0
1/0
113
19
vee
67
114
20
1/0
1/0
1/0
1/0
1/0
68
69
1/0
1/0
XTL2-1I0
1/0
1/0
A2-1/0
A3-1/0
70
GND
117
71
RESET
118
21
22
23
24
115
116
1/0
1/0
A15-1/0
72
vee
119
1/0
1/0
73
DONE-PG
120
M-I/O
74
D7-1/0
123
A14-1/0
I/O
1/0
75
BCLKIN-XTL1-1/0
124
AS-I/O
29
76
I/O
126
GND
30
VO
77
1/0
127
vee
33
I/O
78
D6-1/0
128
A13-1/0
35
I/O
79
1/0
129
AS-I/O
36
Ml-RD
81
I/O
133
A12-1/0
37
GND
82
A7-1/0
MO-RT
84
135
39
vee
85
1/0
D5-1/0
CSO-I/O
134
38
40
M2-1/0
88
D4-1/0
137
1/0
1/0
A11-I/O
41
HDCI/O
89
138
A8-1/0
42
1/0
90
1/0
vee
139
43
1/0
91
GND
140
1/0
1/0
44
1/0
92
D3-1/0
141
Al0-1/0
45
LDC-I/O
93
CSl-I/O
142
A9-1/0
47
96
D2-1/0
1/0
143
vee
48
1/0
1/0
144
GND
49
I/O
25
26
27
97
2-138
136
XC3000 Families160-Pin PQFP Pinouts
XC3000, XC3000A, XC3000L and XC3100 families have identical pinouts
PQFP
Pin Number
XC3064, XC3090,
XC3195
PQFP
Pin Number
XC3064, XC3090,
XC3195
PQFP
Pin Number
XC3064, XC3090,
XC3195
PQFP
Pin Number
XC3064, XC3090,
XC3195
CClK
1
1/0-
41
GND
81
07-VO
121
2
1/0-
42
MD-RTRIG
82
XTll-I/O-BClKIN
122
VCC
3
1/0-
43
VCC
83
1/0-
123
GND
4
1/0
44
M2-VO
64
1/0
124
AO-WS-I/O
5
1/0
45
HOC-VO
85
1/0
125
Al-CS2-VO
6
1/0
46
1/0
86
06-1/0
126
VO
7
1/0
47
1/0
87
1/0
127
1/0
8
1/0
48
1/0
88
1/0
128
A2-VO
9
1/0
49
LOC-VO
89
1/0
129
A3-VO
10
1/0
50
90
VO
130
1/0
11
1/0
51
VOVO-
91
1/0
131
1/0
12
1/0
52
1/0
92
05-1/0
132
AI5-VO
13
1/0
53
1/0
93
CSO-I/O
133
A4-VO
14
1/0
54
1/0-
134
1/0
1/0
55
VO
VO
94
15
95
1/0-
135
1/0
16
1/0
56
1/0
96
1/0
136
A14-VO
17
VO
57
1/0
97
VO
137
A5-1/0
18
19
1/0
58
1/0
98
04-110
GND
59
INIT-I/O
99
1/0
138
139
GND
20
VCC
60
VCC
100
VCC
140
VCC
21
VO-
61
GND
101
GND
141
A13-1/0
22
1/0
62
1/0
102
03-1/0
142
A6-1/0
23
VO
63
1/0
103
CSI-I/O
143
1/0-
24
1/0
64
1/0
104
1/0
144
25
1/0
65
1/0
105
1/0
145
26
1/0
66
1/0
106
1/0-
146
VOVO
VO
27
1/0
67
1/0
107
1/0-
147
A12-1/0
28
1/0
68
1/0
108
02-110
148
A7-VO
29
1/0
69
1/0
109
1/0
149
1/0
30
1/0
70
1/0
110
1/0
150
1/0
1/0-
31
1/0
71
1/0
111
1/0
151
A11-VO
32
1/0
72
1/0
112
1/0
152
A8-VO
33
1/0
73
1/0
113
1/0
153
1/0
34
VO
74
1/0
114
01-1/0
154
VO
35
1/0
75
1/0-
115
ROY-BSY/RClK-I/O
155
AlO-I/O
36
VO
76
XTl2-I/O
116
1/0
156
A9-1/0
37
1/0
77
GND
117
VO
157
VCC
38
1/0-
78
RESET
118
1/0-
158
GND
39
1/0-
79
VCC
119
DO-DIN-I/O
159
PWROWN
40
Ml-ROATA
80
OONElPG
120
DOUT-I/O
160
TCLKIN-I/O
Unprogrammed lOBs have a default pull-up_ This prevents an undefined pad level for un bonded or unused lOBs. Programmed
lOBs are default slew-rate limited.
-Indicates unconnected package pins (18) for the XC3064.
2-139
II
XC3000, XC3000A, XC3000L, XC3100 Logic Cell Array Families
XC3000 FamUies
175~Pin
Ceramic and Plastic PGA Pinouts
XC3000, XC300QA,XC3000J,. and XC31 00 families have identical pinouts
PGAPln
Number
B2
04
B3
C4
B4
M
05
C5
B5
AS
C6
06
B6
A6
B7
C7
07
A7
A8
B8
C8
08
09
C9
B9
A9
AID
010
Cl0
Bl0
All
Bl1
011
Cll
A12
B12
C12
012
A13
B13
C13
A14
XC3090, XC3195
PWRON
TCLKIN-I/O
110
110
VO
VO
110
VO
110
110
110
PGAPln
Number
013
B14
C14
B15
014
C15
E14
B16
015
C16
VO
VO
016
F14
E15
E16
F15
F16
G14
G15
G16
H16
110
H15
GND
H14
J14
J15
J16
K16
K15
K14
VO
VO
110
110
110
110
110
vee
VO
110
110
VO
VO
VO
VO
110
110
VO
110
1/0
1/0
I/O
1/0
110
VO
VO
1/0
L16
L15
M16
M15
L14
N16
P16
N15
R16
XC3090, XC3195
110
Ml-~
GND
Mo-RTRIG
PGAPln
Number
R14
N13
n4
P13
vee
R13
T13
N12
P12
R12
n2
Pll
NIl
Rll
TIl
Rl0
Pl0
Nl0
no
T9
R9
P9
M2-VO
HOG-VO
110
VO
VO
roc-vo
110
110
110
110
110
I/O
110
110
110
lNIT-II0
vee
N9
N8
P8
R8
T8
T7
N7
P7
R7
T6
R6
N6
P6
T5
R5
P5
GND
I/O
110
110
110
110
110
110
110
I/O
110
110
VO
110
VO
M14
P15
N14
1/0
XTL2(IN)-VO
R15
RESET
P14
vee
N5
T4
R4
P4
GND
XC3090, XC3195
OONE-PG
07-110
XTLl(OU1)-BCLKIN-IfO
PGAPln
Number
R3
N4
XC3090, XC3195
Oo-OIN-VO
DOUT-VO
CCLK
110
110
110
R2
P3
N3
P2
I/O
M3
Al-CS2-VO
D6-VO
110
110
110
110
Rl
N2
PI
Nl
VO
VO
M2
05-110
CSO-1I0
110
Ml
L2
L1
K3
K2
Kl
Jl
J2
VO
VO
1/0
04-110
110
vee
GND
03-110
CS1-I/o
I/O
110
1/0
I/O
02-110
110
110
VO
1/0
I/O
01-110
ROV/BOSY-RCLK-II0
110
VO
VO
1/0
L3
J3
H3
H2
HI
Gl
G2
G3
Fl
F2
El
E2
F3
01
Cl
02
vee
GND
Ao-WS-VO
110
A2-VO
A3-VO
I/O
110
AI5-VO
M-VO
VO
110
A14-1/0
AS-II0
110
110
GND
vee
Al3-I/O
A6-VO
110
I/O
110
110
A12-1I0
A7-VO
I/O
110
Al1-VO
A8-VO
Bl
E3
C2
110
110
Al0-VO
A9-1/0
03
C3
GND
vee
Unprogrammed lOBs have a default pull-up. This prevents an undefined pad level for unbonded or unused lOBs. Programmed
outputs are default slew-rate limited.
Pins A2, A3, A15, A16, n, T2, T3, T15 and T16 are not connected. Pin A1 does not exist.
2-140
--------~------
XC3090 208-Pin PQFP Pinouts
XC3000, XC3000A and XC31 00 families have identical pinouts
Pin
Number
XC3090
Pin
Number
-
53
GND
PWROWN
Pin
Number
Xe3090
Pin
Number
105
-
157
54
-
106
vee
158
55
vce
107
O/P
159
108
-
160
GNO
109
07-1/0
161
WS-AO-I/O
110
XTL1-BCLKIN-VO
162
CS2-Al-1/0
111
110
163
110
112
110
164
1/0
110
XC3090
1
2
3
4
TCLKIN-I/O
56
M2-1I0
5
57
HOC-liD
6
VO
VO
58
1/0
7
110
59
110
8
110
60
Xe3090
-
9
1/0
61
LOC-I/O
113
1/0
165
A2-1/0
10
1/0
62
1/0
114
1/0
166
A3-1/0
1/0
115
06-1/0
167
1/0
116
1/0
168
VO
-
117
110
169
118
110
170
11
1/0
63
12
1/0
64
13
1/0
65
14
VO
66
-
15
-
67
-
119
-
171
-
16
1/0
68
1/0
120
1/0
172
A15-1/0
17
1/0
69
1/0
121
110
173
M-I/O
18
110
70
110
122
OS-liD
174
110
19
1/0
71
110
123
CSO-I/O
175
110
20
110
72
124
1/0
176
21
110
73
-
125
110
177
-
22
110
74
110
178
A14-1/0
110
75
1/9
1/0
126
23
127
1/0
179
A5-1/0
24
1/0
76
110
128
04-110
180
110
25
GND
77
INIT-IIO
129
1/0
181
1/0
26
vec
78
vce
130
vee
182
GND
27
110
79
GND
131
GND
183
vee
28
110
80
1/0
132
03-1/0
164
A13-1/0
29
1/0
81
110
133
CS1-1/0
185
A6-1I0
30
82
110
134
110
186
110
31
VO
VO
83
135
1/0
187
110
32
1/0
64
-
136
110
188
VO
VO
-
33
85
1/0
137
1/0
189
-
86
1/0
138
02-110
190
110
35
1/0
87
1/0
139
110
191
1/0
36
110
88
110
140
110
192
A12-1/0
37
-
89
1/0
141
110
193
A7-VO
38
VO
90
142
-
194
39
110
91
143
110
195
40
110
92
-
144
1/0
196
-
41
110
93
110
145
01-1/0
197
110
42
110
94
1/0
146
BUSY/RDY-RCLK-I/O
198
110
43
1/0
95
110
147
110
199
All-li~
44
110
96
110
148
1/0
200
AS-I/O
45
110
97
1/0
149
1/0
201
110
46
110
98
110
150
110
202
110
47
110
99
1/0
151
OIN-OO-I/O
203
Al0-1/0
48
Ml-ROATA
100
XTL2-I/O
152
OOUT-I/O
204
A9-1I0
49
GND
101
GND
153
CCLK
205
vec
50
MQ-RTRIG
102
RESET
154
vee
206
51
-
103
-
155
207
104
-
156
-
-
34
52
2-141
208
II
XC3000, XC3000A, XC3000L, XC31 00 Logic Cell Array Families
XC3195 PQ208 and PG223 Pinouts
Pin
Description
PG223
A9-1/0
81
AI 0-110
Pin
Description
PG223
154
1/0
U18
102
V3
153
VO
PIS
101
1/0
R5
152
1/0
T17
100
203
1/0
T4
151
1/0
T18
202
1/0
V4
150
VO
P16
02
201
RDY!BUSY-'R'C'[K·I!O
U4
149
1/0
A8-1/0
E2
200
01-1/0
US
148
All-VO
F4
199
R6
147
Pin
Description
PG223
206
OO-OIN-I/O
U3
E3
205
1/0
1/0
E4
204
1/0
C2
VO
Cl
1/0
PQ208*
PQ20S*
PQ208*
Pin
Description
99
VO
VO
VO
VO
98
1/0
R17
97
1/0
1/0
N15
R18
1/0
F3
198
110
1/0
T5
146
VO
01
197
1/0
U6
145
VO
VO
PG223
816
PQ20S*
49
A16
48
014
47
CIS
46
815
45
1/0
A15
44
96
1/0
C14
43
95
VO
013
42
P17
94
1/0
814
41
N17
93
1/0
C13
40
1/0
F2
196
1/0
T6
144
1/0
N16
92
1/0
813
39
VO
G2
194
VO
V7
141
VO
MIS
89
110
812
38
A7-1/0
G4
193
1/0
R7
140
M18
88
37
G1
192
VO
U7
139
M17
87
110
110
012
A12-1/0
1/0
1/0
A12
36
VO
H2
191
02-1/0
V8
138
1/0
L18
86
VO
811
35
1/0
H3
190
1/0
U8
137
VO
L17
85
1/0
Cll
34
VO
VO
VO
HI
189
1/0
T8
136
1/0
LIS
84
1/0
All
33
H4
188
1/0
R8
135
1/0
L16
83
1/0
011
32
J3
187
V9
134
82
31
186
U9
133
K17
81
110
110
Al0
J2
VO
VO
K18
1/0
VO
CSH/O
610
30
A6-1/0
Jl
185
03-1/0
T9
132
1/0
K16
80
1/0
Cl0
29
AI3-VO
K3
184
GND
R9
131
GND
K15
79
1/0
C9
28
vce
J4
183
vee
RIO
130
vee
J15
78
vee
010
27
GND
K4
182
VO
Tl0
129
INIT
J16
77
GND
09
26
1/0
110
K2
181
04-1/0
Ul0
128
VO
J17
76
110
89
25
Kl
180
1/0
Vl0
127
110
J18
75
110
A9
24
AS-liD
l2
179
1/0
Rll
126
110
H16
74
C8
23
AI4-VO
L4
178
1/0
TIl
125
1/0
H15
73
08
22
1/0
L3
177
1/0
Ull
124
H17
72
88
21
1/0
Ll
176
CSO-I/O
VII
123
VO
VO
VO
VO
VO
H18
71
110
A8
20
VO
Ml
175
05-110
U12
122
1/0
G17
70
1/0
87
19
1/0
M2
174
1/0
R12
121
VO
G18
69
110
A7
18
A4-VO
M4
173
1/0
V12
120
110
G15
68
VO
07
17
A15-1/0
N2
172
1/0
T13
119
VO
F16
67
1/0
66
14
1/0
N3
171
1/0
U13
118
110
F17
66
1/0
C6
13
VO
P2
169
1/0
T14
117
1/0
E17
63
VO
85
12
1/0
Rl
168
VO
R13
116
1/0
C18
62
A4
11
VO
N4
167
U14
115
VO
F15
61
06
10
A3-VO
Tl
166
1/0
06-110
110
1/0
U15
114
1/0
017
60
110
C5
9
.0.2-110
R2
165
110
VIS
113
lOC-I/O
E16
59
110
B4
8
1/0
P3
184
1/0
TIS
112
VO
C17
58
110
B3
7
1/0
T2
163
110
R14
111
1/0
618
57
110
C4
6
VO
VO
P4
162
VO
V16
110
1/0
E15
56
VO
05
5
Ul
161
XTl1 (OUT)BClKN-1/O
U16
109
HOC-liD
A18
55
110
C3
4
Al-CS2-VO
VI
160
07-1/0
T16
108
M2-1/0
A17
54
VO
A3
3
AO-WS-VO
T3
159
DIP
V17
107
vee
016
53
TCLKIN-I/O
A2
2
GND
R3
158
R15
106
MO-RTIG
817
52
PWRON
82
1
vee
vee
R4
157
RESET
U17
105
GND
015
51
GND
04
208
CCLK
U2
156
GND
R16
104
Ml/ROATA
C16
50
vee
03
207
OOUT-I/O
V2
155
XTl2(IN)-I/O
V18
103
'Different pin definition than XC3090 PQ208 package_
2-142
-~-
-~---~--.--.
--~~.
XC3000 Component Availability
PINS
II
=
=
=
C Commercial 0 to +70 C
I Industrial
Parenthesis indicate future product plans
0
0
=-40
0
to +85 C
0
2-143
XC3000, XC3000A, XC3000L, XC3100 Logic Cell Array Families
For a detailed description of the device architecture, see pages 2-100 through 2-117.
For a detailed description of the configuration modes and their timing, see pages 2-118 through 2-126.
For detailed lists of package pin-outs, see pages 2-132 through 2-142
For package physical dimensions, see Section 4.
Ordering Information
Example:
Device Type
IJ
XC313o- 3 PC44C
CT,mpem"reR''''''
Block Delay
Number of Pins
Package Type
2-144
XC3000
Logic Cell Array Family
Product Specification
Features
Description
• Industry-leading FPGA family with five device types
XC3000 is the original family of devices in the XC3000
class of Filed Programmable Gate Array (FPGA) architectures. The XC3000 family has a proven track record in
addressing a wide range of design applications, including
general logic replacement and sub-systems integration.
For a thorough description of the XC3000 architecture see
the preceding pages of this data book.
- Logic densities from 1,300 to 7,500 gates
- Up to 144 user-definable II0s
• Guaranteed 70- to 125-MHz toggle rates, 9 to 5.5 ns
logic delays
• Advanced CMOS static memory technology
- Low quiescent and active power consumption
• XC3000-specific features
- Ultra-low current option in Power-Down mode
- 4-mA output sink and source current
- Broad range of package options includes plastic and
ceramic quad flat packs, plastic leaded chip carriers
and pin grid arrays
The XC3000 Family covers a range of nominal device
densities from 2,000 to 9,000 gates, practically achievable
densities from 1,300 to 7,500 gates. Device speeds,
described in terms of maximum guaranteed toggle frequencies, range from 70 to 125 MHz. The performance of
a completed design depends upon placement and routing
implementation, so, like with any gate array, the final
verification of device utilization and performance can only
be known after the design has been placed and routed.
- 100% bitstream compatible with the XC31 00 family
- Commercial, industrial, military, "high rei", and MILSTD-883 Class B grade devices
- Easy migration to XC3300 series of HardWire maskprogrammed devices for high-volume production
Device
CLBs
Array
XC3020
XC3030
XC3042
XC3064
XC3090
64
100
144
224
320
8x8
10 x 10
12x 12
16 x 14
16 x20
User I/Os
Max
64
80
96
120
144
2-145
Flip-Flops
Horizontal
Longlines
Configuration
Data Bits
256
360
480
688
928
16
20
24
28
40
14,779
22,176
30,784
46,064
64,160
II
XC3000 Logic Cell Array Family
Xilinx maintains test specifications for each product as controlled documents. To insure the use of the most recently
released device performance parameters. please request a copy of the current test-specification revision.
Absolute Maximum Ratings
Symbol Description
Units
Vcc
Supply voltage relative to GND
-0.5 to +7.0
V
VIN
Input voltage with respect to GND
-0.5 to Vcc +0.5
V
VTS
Voltage applied to 3-state output
-0.5 to Vcc +0.5
V
TSTG
Storage temperature (ambient)
-65 to +150
°C
TSOL
Maximum soldering temperature (10 s @ 1/16 in.)
+260
°C
Junction temperature plastic
+125
°C
Junction temperature ceramic
+150
°C
TJ
Note: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These are stress ratings only. and functional operation of the device at these or any other conditions beyond
those listed under Recommended Operating Conditions is not implied. Exposure to Absolute Maximum
Ratings conditions for extended periods of time may affect device reliability.
Operating Conditions
Symbol
Vcc
Description
Supply voltage relative to GND
Commercial
Supply voltage relative to GND
Industrial
O°C to +70°C
-40°C to +85°C
Min
Max
Units
4.75
5.25
V
4.5
5.5
V
VIHT
High-level input voltage - TIL configuration
2.0
Vcc
V
VILT
Low-level input voltage - TIL configuration
0
0.8
V
VIHC
High-level input voltage - CMOS configuration
70%
100%
Vcc
V ILC
Low-level input voltage - CMOS configuration
0
20%
Vcc
TIN
Input signal transition time
250
ns
2-146
~XIUNX
DC Characteristics Over Operating Conditions
Symbol
V OH
Min
Description
High-level output voltage (@ IOH
=-4.0 mA, V cc min)
Max
3.86
Units
V
Commercial
=4.0 mA, Vcc max)
VOL
Low-level output voltage (@ IOL
VOH
High-level output voltage (@ IOH
0.40
=-4.0 mA, Vcc min)
3.76
V
V
Industrial
=4.0 mA, Vcc max)
VOL
Low-level output voltage (@ IOL
V ccpo
Power-down supply voltage (PWRDWN must be Low)
Iccpo
Power-down supply current (VCC(MAX) @ T MAX) 1
Icco
0.40
2.30
V
V
XC3020
50
XC3030
80
XC3042
120
XC3064
170
XC3090
250
IJA
IJA
IJA
IJA
IJA
500
IJA
10
IJA
+10
IJA
Quiescent LCA supply current in addition to Iccpo2
Chip thresholds programmed as CMOS levels
Chip thresholds programmed as TTL levels
-10
III
Input Leakage Current
CIN
Input capacitance, all packages except PGA 175
(sample tested)
All Pins except XTL 1 and XTL2
XTL 1 and XTL2
10
15
pF
pF
Input capacitance, PGA 175
(sample tested)
All Pins except XTL 1 and XTL2
XTL 1 and XTL2
15
20
pF
pF
0.17
mA
3.4
mA
=0 V (sample tested)
IRIN
Pad pull-up (when selected) @ VIN
IRll
Horizontal Longline pull-up (when selected) @ logic Low
Note:
0.02
1. Devices with much lower Iccpo tested and guaranteed at Vcc = 3.2 V, T = 25°C can be ordered with a
Special Product Code.
XC3020 SPC0107: Iccpo = 1 J.LA
XC3030 SPC0107: Iccpo = 21lA
XC3042 SPC0107: Iccpo = 3 J.LA
XC3064 SPC0107: Iccpo= 4 J.LA
XC3090 SPC0107: Iccpo= 51lA
2. With no output current loads, no active input or Longline pull-up resistors, all package pins at Vee or GND,
and the LCA configured with a MakeBits tie option.
2-147
II
XC3000 Logic Cell Array Family
CLB Switching Characteristic Guidelines
CLB OUTPUT (X,V)
(COMBINATORIAL)
CLB INPUT (A,B,C,D,E)
CLBCLOCK
~---@ TCL--~
o
T DICK ---t-l-
CLBINPUT
(DIRECT IN)
®
TECCK
CLBINPUT
(ENABLE CLOCK)
CLBOUTPUT
(FLIp· FLOP)
CLBINPUT
(RESET DIRECT)
CLBOUTPUT
(FLlp·FLOP)
1105 26
Buffer (Internal) Switching Characteristic Guidelines
Speed Grade
-70
-100
-125
Symbol
Max
Max
Max
TplD
6.8
6.5
5.6
ns
T plDC
5.4
5.1
4.3
ns
TBUF driving a Horizontal Longline (L.L.)*
I to L.L. while T is Low (buffer active)
T J, to L.L. active and valid with single pull-up resistor
T J, to L.L. active and valid with pair of pull-up resistors
Tt to L.L. High with single pull-up resistor
Tt to L.L. High with pair of pull-up resistors
TIO
TON
TON
Tpus
TpUF
4.1
5.6
7.1
28.2
19.2
3.7
5.0
6.5
25.2
16.2
3.1
4.2
5.7
19.6
12.6
ns
ns
ns
ns
ns
BIOI
Bidirectional buffer delay
TBIDI
1.4
1.2
1.0
ns
Description
Global and Alternate Clock Distribution·
Either: Normal lOB input pad through clock buffer
to any CLB or lOB clock input
Or:
Fast (CMOS only) input pad through clock
buffer to any CLB or lOB clock input
*
Timing is based on the XC3042, for other devices see XACT timing calculator.
2-148
Units
CLB Switching Characteristic Guidelines (continued)
Testing of the switching parameters is modeled after testing methods specified by MI L-M-3851 0/605. All devices are 100%
functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing
patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more detailed, more
precise, and more up-to-date timing information, use the values provided by the XACT timing calculator and used in the simulator.
Speed Grade
Description
Symbol
Combinatorial Delay
Logic Variables A, B, C, D, E, to outputs X or Y
Sequential delay
Clock k to outputs X or Y
Clock k to outputs X or Y when Q is retumed
through function generators F or G to drive X or Y
Set-up time before clock
Logic Variables
Data In
Enable Clock
Reset Direct inactive
K
A,B,C,D,E
DI
EC
RD
Hold Time after clock K
Logic Variables
Data In
Enable Clock
A,B,C,D,E
DI
EC
Clock
Clock High time
Clock Low time
Max. flip-flop toggle rate
Reset Direct (RD)
RD width
delay from rd to outputs X or Y
-70
Min
-100
Max
Units
-125
Min Max
Min Max
1
TILO
9
7
5.5
ns
8
TCKO
6
5
4.5
ns
TOLO
13
10
8
ns
6
TICK
TDICK
TECCK
8
5
7
1
7
4
5
1
5.5
3
4.5
1
ns
ns
ns
ns
3
5
7
TCKI
TCKDI
TCKEC
0
4
0
0
2
0
0
1.5
0
ns
ns
ns
11
12
TCH
TCl
FClK
5
5
7
4
4
100
3
3
125
ns
ns
MHz
13
9
TRPW
TRIO
8
TMRW
TMRO
25
2
4
Global Reset (RESET Pad)'
RESET width (Low)
delay from RESET pad to outputs X or Y
7
21
23
6
ns
ns
17
ns
ns
6
7
8
20
19
'Timing is based on the XC3042, for other devices see XACT timing calculator.
Note:
The CLB K to Q output delay (TCKO ' #8) of any CLB, plus the shortest possible interconnect delay, is always longer than
the Data In hold time requirement (TCKO!' #5) of any CLB on the same die.
2-149
II
XC3000 Logic Cell Array Family
lOB Switching Characteristic Guidelines
VO BLOCK (I)
-®-TPID~-r----
t-CD
I/O PAD INPUT
-l-"-P-IC-K--------...J
1,---------------,.
I/O CLOCK
(IKlOK)
~---@ TIOL---~----
110 BLOCK (RI)
VOBLOCK(O)
110 PAD OUTPUT
(DIRECl)
_ _ _ _ _ _ _ _ _ _ _ _ _f0TOKPO
I/O PAD OUTPUT
(REGISTERED)
J------1r--0--~--~--------®--~-"~J r-r
VOPADTS
110 PAD OUTPUT
-----------~(
OUT
O'RECT'N
AEGISTEREO IN
j)-
-=--1'-,/
-..;..!.----+------,
--'-"'------+---1
PROGRAM
CONTROLLED
MULTIPLEXER
o '" PROGRAMMABLE INTERCONNECTION POINT
2-150
or PIP
110527C
lOB Switching Characteristic Guidelines (continued)
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/S05. All devices are 100%
functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing
patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more detailed, more
precise, and more up-to-date timing information, use the values provided by the XACT timing calculator and used in the simulator.
Speed Grade
Description
Propagation Delays (Input)
Pad to Direct In (I)
Pad to Registered In (Q) with latch transparent
Clock (IK) to Registered In (Q)
Symbol
3
-70
Min
-100
Max
-125
Min Max
Min Max
4
17
4
6
21
5.5
Units
3
16
3
ns
ns
ns
4
TplD
T pTG
TIKRI
Set-up Time (Input)
Pad to Clock (IK) set-up time
1
T plCK
Propagation Delays (Output)
Clock (OK) to Pad
(fast)
(slew rate limited)
same
Output (0) to Pad
(fast)
same
(slew-rate limited)
3-state to Pad begin hi-Z (fast)
same
(slew-rate limited)
3-state to Pad active and valid (fast)
(slew -rate limited)
same
7
7
10
10
9
9
8
8
T OKPO
T OKPO
T OPF
Tops
TTSHZ
TTSHZ
TTSON
TTSON
Set-up and Hold Times (Output)
Output (0) to clock (OK) set-up time
Output (0) to clock (OK) hold time
5
6
TOOK
T OKO
10
0
9
0
8
0
ns
ns
11
12
T IOH
T IOl
5
5
70
4
4
100
3
3
125
ns
ns
MHz
Clock
Clock High time
Clock Low time
Max. flip-flop toggle rate
Global Reset Delays (based on XC3042)
RESET Pad to Registered In (Q)
RESET Pad to output pad (fast)
(slew-rate limited)
FClK
13
15
15
TRRI
T RPO
T RPO
20
17
13
33
9
29
8
28
14
34
25
35
53
16
10
27
6
23
8
25
12
29
24
33
45
ns
9
24
5
20
7
24
11
27
23
29
42
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes: 1. Timing is measured at pin threshold, with 50 pF external capacitive loads (incl. test fixture). For larger capacitive loads,
see XAPP 024. Typical slew rate limited output rise/fall times are approximately four times longer.
2. Voltage levels of unused (bonded and un bonded) pads must be valid logic levels. Each can be configured with the
internal pull-up resistor or alternatively configured as a driven output or driven from an external source.
3. Input pad set-up time is specified with respect to the internal clock (IK). In order to calculate system set-up time, subtract
clock delay (pad to IK) from the input pad set-up time value. Input pad holdtime with respect to the internal clock (IK) is
negative. This means that pad level changes immediately before the internal clock edge (IK) will not be recognized.
2-151
I
XC3000 Logic Cell Array Family
For a detailed description of the device architecture, see pages 2-100 through 2-117.
For a detailed description of the configuration modes and their timing, see pages 2-118 through 2-126.
For detailed lists of package pin-outs, see pages 2-132 through 2-142
For package physical dimensions, see Section 4.
Ordering Information
Example:
"""" """
JC
XC3030-70PC44C
T
Toggle Rate
T""""m,"" R,",.
Number of Pins
Package Type
Component Availability
2-152
XC3000A
Logic Cell Array Family
Preliminary Product Specifications
Description
Features
The XC3000A family offers the following enhancements
over the popular XC3000 family:
• Enhanced, high performance FPGA family with five
device types
- Improved redesign of the basic XC3000 LCA
Family
- Logic densities from 1,300 to 7,500 gates
- Up to 144 user-definable II0s
The XC3000A family has additional interconnect resources
to drive the I-inputs of TBUFs driving horizontal Longlines.
The CLB Clock Enable input can be driven from a second
vertical Longline. These two additions result in more
efficient and faster designs when horizontal Longlines are
used for data bussing.
• Superset of the industry-leading XC3000 family
- Identical to the basic XC3000 in structure, pin out,
design methodology, and software tools
- 100% compatible with all XC3000, XC3000L,
and XC31 00 bitstreams
- Improved routing and additional features
During configuration, the XC3000A devices check the
bitstream format for stop bits in the appropriate positions.
Any error terminates the configuration and pulls INIT Low.
When the configuration process is finished and the device
starts up in user mode, the first activation of the outputs is
automatically slew-rate limited. This feature, called Soft
Startup, avoids the potential ground bounce when all
outputs are turned on simultaneously. After start-up, the
slew rate of the individual outputs is, as in the XC3000
family, determined by the individual configuration option.
• Additional programmable interconnection points
(PIPs)
- Improved access to long lines and CLB clock
enable inputs
- Most efficient XC3000-class solution to bus-oriented designs
The XC3000A family is a superset of the XC3000 family.
Any bitstream used to configure an XC3000 or XC31 00
device configures an XC3000A device exactly the same
way.
• Advanced 0.8 11 CMOS static memory technology
- Low quiescent and active power consumption
• Performance specified by logic delays, faster than
corresponding XC3000 versions
• XC3000A-specific features
- 4 mA output sink and source current
- Error checking of the configuration bitstream
- Soft startup starts all outputs in slew-limited mode
upon power-up
- Easy migration to the XC3400 series of HardWire
mask programmed devices for high-volume
production.
Device
CLBs
Array
XC3020A
XC3030A
XC3042A
XC3064A
XC3090A
64
100
144
224
320
8x8
10 x 10
12 x 12
16 x 14
16 x 20
User I/Os
Max
64
80
96
120
144
2-153
Flip-Flops
Horizontal
Longlines
Configurable
Data Bits
256
360
480
688
928
16
20
24
32
40
14,779
22,176
30,784
46,064
64,160
II
XC3000A Logic Cell Array Family
Xilinx maintains test specifications for each product as controlled documents. To insure the use of the most recently
released device performance parameters, please request a copy of the current test-specification revision.
Absolute Maximum Ratings
Symbol Description
Units
Vce
Supply voltage relative to GND
-0.5 to +7.0
V
VIN
Input voltage with respect to GND
-0.5 to Vee +0.5
V
VTS
Voltage applied to 3-state output
-0.5 to Vee +0.5
V
T STG
Storage temperature (ambient)
-65 to +150
°C
TSOL
Maximum soldering temperature (10 s @ 1/16 in.)
+260
°C
Junction temperature plastic
+125
°C
Junction temperature ceramic
+150
°C
TJ
Note:
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those listed under Recommended Operating Conditions is not implied. Exposure to Absolute Maximum
Ratings conditions for extended periods of time may affect device reliability.
Operating Conditions
Symbol
Vce
Description
Supply voltage relative to GND
Commercial
Supply voltage relative to GND
Industrial
O°C to +70°C
-40°C to +85°C
Min
Max
Units
4.75
5.25
V
4.5
5.5
V
VIHT
High-level input voltage - TIL configuration
2.0
Vee
V
VILT
Low-level input voltage -
TIL configuration
0
0.8
V
VIHC
High-level input voltage -
CMOS configuration
70%
100%
Vee
VILe
Low-level input voltage -
CMOS configuration
0
20%
Vee
TIN
Input signal transition time
250
ns
2-154
DC Characteristics Over Operating Conditions
Symbol
V OH
Description
Min
High-level output voltage (@ IOH
=-4.0 mA, Vcc min)
Max
3.86
Units
V
Commercial
=4.0 mA, V cc max)
VOL
Low-level output voltage (@ IOL
V OH
High-level output voltage (@ IOH
=-4.0 mA, Vcc min)
3.76
Low-level output voltage (@ IOL
V CCPD
Power-down supply voltage (PWRDWN must be Low)
ICCPD
Power-down supply current (V CC(MAX) @ T MAX)
V
V
Industrial
=4.0 mA, Vcc max)
VOL
Icco
0.40
0.40
2.30
V
V
XC3020A
50
~
XC3030A
80
~
XC3042A
120
~
XC3064A
170
~
XC3090A
250
~
500
~
10
~
+10
~
Quiescent LCA supply current in addition to I)CPD*
Chip thresholds programmed as CMOS evels
Chip thresholds programmed as TTL levels
IlL
Input Leakage Current
C IN
Input capacitance, all packages except PGA175
(sample tested)
All Pins except XTL 1 and XTL2
XTL 1 and XTL2
10
15
pF
pF
Input capacitance, PGA 175
(sample tested)
All Pins except XTL 1 and XTL2
XTL 1 and XTL2
15
20
pF
pF
0.17
mA
3.4
mA
-10
=0 V (sample tested)
IRIN
Pad pull-up (when selected) @ VIN
IRLL
Horizontal Longline pull-up (when selected) @ logic Low
0.02
• With no output current loads, no active input or Longline pull-up resistors, all package pins at Vcc or GND, and the
LeA device configured with a MakeBits tie option.
2-155
II
XC3000A Logic Cell Array Family
CLB Switching Characteristic Guidelines
CLB OUTPUT (X,V)
(COMBINATORIAL)
CLB INPUT (A,B,C,D,E)
CLBCLOCK
@
TCL---r..-@ TCH-----~
o
T01CK --'14-
CLBINPUT
(DIRECT IN)
® TECCK
CLBINPUT
(ENABLE CLOCK)
CLBOUTPUT
(FLIP-FLOP)
CLBINPUT
(RESET DIRECT)
CLBOUTPUT
(FLIP-FLOP)
1105 26
Buffer (Internal) Switching Characteristic Guidelines
Speed Grade
Description
Symbol
Global and Alternate Clock Distribution*
Either: Normal lOB input pad through clock buffer
to any CLB or lOB clock input
Or:
Fast (CMOS only) input pad through clock
buffer to any CLB or lOB clock input
TBUF driving a Horizontal Longline (L.L.)*
I to L.L. while T is Low (buffer active)
T.,J.. to L.L. active and valid with single pull-up resistor
T.,J.. to L.L. active and valid with pair of pull-up resistors
Ti to L.L. High with single pull-up resistor
Ti to L.L. High with pair of pull-up resistors
TplD
ns
T plDC
ns
T IO
ns
ns
ns
ns
ns
TON
TON
Tpus
TpUF ,"
BIOI
Bidirectional buffer delay
ns
• Timing is based on the XC3042A, for other devices see XACT timing calculator.
2-156
CLB Switching Characteristic Guidelines (continued)
Testing of the switching parameters is modeled after testing methods specified by MIL-M-3851 0/605. All devices are 100%
functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing
patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more detailed, more
precise, and more up-to-date timing information, use the values provided by the XACT timing calculator and used in the simulator.
Speed Grade
Symbol
Description
Combinatorial Delay
Logic Variables A, B, C, D, E, to outputs X or Y
Sequential delay
Clock k to outputs X or Y
Clock k to outputs X or Y when Q is returned
through function generators For G to drive X or Y
Set-up time before clock
Logic Variables
Data In
Enable Clock
Reset Direct inactive
Hold Time after clock K
Logic Variables
Data In
Enable Clock
8
Units
TILO
ns
TCKo
ns
TOLO
K
2
4
6
TICK
TDICK
TECCK
A,B,C,D,E
3
DI
5
TCKI
TCKDI
EC
7
A,B,C,D,E
DI
EC
RD
Clock
Clock High time
Clock Low time
Max. flip-flop toggle rate
11
12
Reset Direct (RD)
RD width
delay from RD to outputs X or Y
13
9
Global Reset (RESET Pad)"
RESET width (Low)
delay from RESET pad to outputs X or Y
ns
ns
ns
ns
ns
ns
ns
ns
MHz
TRPW
TRIO
ns
ns
TMRW
TMRO
ns
ns
"Timing is based on the XC3042A, for other devices see XACT timing calculator.
Notes: The CLB K to Q output delay (TCKO' #8) of any CLB, plus the shortest possible interconnect delay, is always longer than
the Data In hold time requirement (TCKD!' #5) of any CLB on the same die. TILO ' TOLO and TICK are specified for 4-input
functions. For 5-input functions or base FGM functions, each specification increases by 0.8 ns (-5), 0.6 ns (-4) and
0.5 ns (-3).
2-157
I
XC3000A Logic Cell Array Family
lOB Switching Characteristic Guidelines
1/0 BLOCK (I)
-®-TPID~-f----
1/0 PAD INPUT
~-Ci)-1---T-PI-C-K------------------I
110 CLOCK
(IKlOK)
1'4-----@
T,OL -----4~----
or-----"TT"--
110 BLOCK (RI)
1/0 BLOCK (0)
1/0 PAD OUTPUT
(DIRECT)
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _f0TOKPO
1/0 PAD OUTPUT
(REGISTERED)
J-rr=-@-aT-TSON--®-gT-_:1 r-
I/OPADTS
VO PAD OUTPUT
-----~(~
_________Ir__
OUT --'-"'--/L/
fliP
flOP
R
DIRECT IN
REGISTERED IN
---'-'-----f------,
--'-"Q----+---I
OK
j)-
PROGRAM
CONTROUED
MUlnpLEXER
I.
o
= PROGRAMMABlE INTERCONNECTION POINT or PIP
2-158
110527C
108 Switching Characteristic Guidelines (continued)
Testing of the switching parameters is modeled after testing methods specified by MIL-M-3851 0/605. All devices are 100%
functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing
patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more detailed, more
precise, and more up-to-date timing information, use the values provided by the XACT timing calculator and used in the simulator.
Speed Grade
Description
Symbol
Propagation Delays (Input)
Pad to Direct In (I)
Pad to Registered In (Q) with latch transparent
Clock (lK) to Registered In (Q)
4
TplD
TpTG
TIKRI
Set-up Time (Input)
Pad to Clock (IK) set-up time
1
T plCK
7
7
10
10
T OKPO
T OKPO
T OPF
Tops
TTSHZ
TTSHZ
TTSON
TTSON
Propagation Delays (Output)
Clock (OK) to Pad
(fast)
same
(slew rate limited)
Output (0) to Pad
(fast)
same
(slew-rate limited)
3-state to Pad begin hi-Z (fast)
same
(slew-rate limited)
3-state to Pad active and valid (fast)
same
(slew -rate limited)
Set-up and Hold Times (Output)
Output (0) to clock (OK) set-up time
Output (0) to clock (OK) hold time
3
9
9
8
8
5
6
Clock
Clock High time
Clock Low time
Max. flip-flop toggle rate
11
12
Global Reset Delays (based on XC3042A)
RESET Pad to Registered In (Q)
RESET Pad to output pad (fast)
(slew-rate limited)
13
15
ns
ns
ns
ns
ns
ns
ns
TIOH
T IOl
FClK
15
ns
TRRI
T RPO
T RPO
ns
ns
MHz
ns
ns
ns
Notes: 1. Timing is measured at pin threshold, with 50 pF external capacitive loads (inc!. test fixture). For larger capacitive loads,
see page XAPP024. Typical slew rate limited output riselfall times are approximately four times longer.
2. Voltage levels of unused (bonded and un bonded) pads must be valid logic levels. Each can be configured with the
internal pull-up resistor or alternatively configured as a driven output or driven from an external source.
3. Input pad set-up time is specified with respect to the internal clock (IK). In order to calculate system set-up time, subtract
clock delay (pad to IK) from the input pad set-up time value. Input pad holdtime with respect to the internal clock (IK) is
negative. This means that pad level changes immediately before the internal clock edge (IK) will not be recognized.
4. TPIO' T PTG' and T PICK are 3 ns higher for XTL2 when the pin is configured as a user input.
2-159
XC3000A Logic Cell Array Family
For a detailed description of the device architecture, see pages 2-100 through 2-117.
For a detailed description of the configuration modes and their timing, see pages 2-118 through 2-126.
For detailed lists of package pin-outs, see pages 2-132 through 2-142.
For package physical dimensions, see Section 4.
Ordering Information
Example:
XC3020A-6PC84C
D~M~~ l~T~m,"reRBlock Delay
Number of Pins
Package Type
Component Availability
Parentheses indicate future product plans
2-160
XC3000L Low Voltage
Logic Cell Array Family
Preliminary Product Specification
Features
Description
• Part of the ZERO+ family of 3.3 V FPGAs
The XC3000L family of FPGAs is optimized for operation
from a nominally 3.3 Vsupply. Aside from the electrical and
timing parameters listed in this data sheet, the XC3000L
family is in all respects identical with the XC3000A family,
and is a superset of the XC3000 family.
• Low supply voltage FPGA family with five device
types
- JEDEC-compliant 3.3 V version of theXC3000A
LCA Family
- Logic densities from 1,300 to 7,500 gates
- Up to 144 user-definable II0s
The operating power consumption of Xilinx FPGAs is
almost exclusively dynamic, and it changes with the square
of the supply voltage. For a given complexity and clock
speed, the XC3000L consumes, therefore, only 44% ofthe
power used by the equivalent XC3000A device. In accordance with its use in battery-powered equipment, the
XC3000L family was designed for the lowest possible
power-down and quiescent current consumption.
• Advanced, low power 0.8 ~ CMOS static memory
technology
- Very low quiescent current consumption, ~ 20~A
- Operating power consumption 56% less than
XC3000A, 66% less than previous generation 5 V
FPGAs
In mixed supply-voltage systems, the XC3000L, fed by a
3.3 V (nominal) supply, can directly drive any device with
TTL-like input thresholds. When a 5 V device drives the
XC3000L, a current-limiting resistor (1 kQ) or a voltage
divider is required to prevent excessive input current.
• Superset of the industry-leading XC3000 family
- Identical to the basic XC3000 in structure, pinout,
design methodology, and software tools
- 100% compatible with all XC3000, XC3000A, and
XC3100 bitstreams
- Improved routing and additional features
Like the XC3000A family, XC3000L offers the following
functional improvements over the popular XC3000 family:
• Additional programmable interconnection points
(PIPs)
- Improved access to Longlines and CLB clock
enable inputs
- Most efficient XC3000-class solution to bus-oriented
designs
The XC3000L family has additional interconnect resources
to drive the I-inputs of TBUFs driving horizontal Longlines.
The CLB Clock Enable input can be driven from a second
vertical Longline. These two additions result in more
efficient and faster designs when horizontal Longlines are
used for data bussing.
• XC3000L-specific features
- Guaranteed over the 3.0 to 3.6 V Vcc range
- TTL-equivalent input and output levels
- 4 mA output sink and source current
- Error checking of the configuration bitstream
- Soft startup starts all outputs in slew-limited mode
upon power-up
- Easy migration to the XC3400 series of HardWire
mask programmed devices for high-volume
production
During configuration, the XC3000L devices check the
bitstream format for stop bits in the appropriate positions.
Any error terminates the configuration and pulls INIT Low.
When the configuration process is finished and the device
starts up in user mode, the first activation of the outputs is
automatically slew-rate limited. This feature, called Soft
Startup, avoids the potential ground bounce when all
outputs are turned on simultaneously. After start-up, the
slew rate of the individual outputs is, as in the XC3000
family, determined by the individual configuration option.
The XC3000L family is a superset of the XC3000 family.
Any bitstream used to configure an XC3000 device configures an XC3000L device the same way.
Device
XC3020L
XC3030L
XC3042L
XC3064L
XC3090L
ClBs
64
100
144
224
320
Array
8x8
10 x 10
12 x 12
16 x 14
16x20
User I/Os
Max
64
80
96
120
144
2-161
Flip-Flops
256
360
480
688
928
Horizontal
longlines
16
20
24
32
40
Configurable
Data Bits
14,779
22,176
30,784
46,064
64,160
II
XC3000L Logic Cell Array Family
Xilinx maintains test specifications for each product as controlled documents. To insure the use of the most recently
released device performance parameters, please request a copy of the current test-specification revision.
Absolute Maximum Ratings
Symbol Description
Units
Vce
Supply voltage relative to GND
-0.5 to +7.0
V
VIN
Input voltage with respect to GND
-0.5 to Vee +0.5
V
VTS
Voltage applied to 3-state output
-0.5 to Vee +0.5
V
T STG
Storage temperature (ambient)
-65 to +150
°C
TSOL
Maximum soldering temperature (10 s @ 1/16 in.)
+260
°C
Junction temperature plastic
+125
°C
Junction temperature ceramic
+150
°C
TJ
Note:
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These are stress ratings only. and functional operation of the device at these or any other conditions beyond
those listed under Recommended Operating Conditions is not implied. Exposure to Absolute Maximum
Ratings conditions for extended periods of time may affect device reliability.
Operating Conditions
Symbol
Description
Commercial
O°C to +70°C
Min
Max
3.0
3.6
Vce
Supply voltage relative to GND
V IH
High-level input voltage
2.0
VIL
Low-level input voltage
-0.3
TIN
Input signal transition time
Vce +0.3
0.8
250
Units
V
V
V
ns
Although the present (1993) devices operate over the full supply voltage range from 3.0 to 5.25 V. Xilinx reserves the
right to restrict operation to the 3.0 to 3.6 V range later. when smaller device geometries might preclude operation at 5 V.
2-162
DC Characteristics Over Operating Conditions
Description
Min
VOH
High-level output voltage (@ IOH = -4.0 mA, Vcc min)
2.40
VOL
Low-level output voltage (@ IOL = 4.0 mA, Vcc max)
VOH
High-level output voltage (@ -100 !lA, V cc min)
VOL
Low-level output voltage (@ 100 !lA, V cc max)
V CCPD
Power-down supply voltage (PWRDWN must be Low)
ICCPD
Power-down supply current (VCC(MAX) @ T MAX)
10
!lA
Icco
Quiescent LCA supply current*
Chip thresholds programmed as CMOS levels
20
!lA
IlL
Input Leakage Current, all 1/0 pins in parallel
+10
!lA
CIN
Input capacitance, all packages except PGA 175
(sample tested)
All Pins except XTL1 and XTL2
XTL1 and XTL2
10
15
pF
pF
Input capacitance, PGA 175
(sample tested)
All Pins except XTL1 and XTL2
XTL 1 and XTL2
15
20
pF
pF
0.17
mA
2.50
mA
Symbol
IRIN
Pad pull-up (when selected) @ V IN = 0 V (sample tested)
IRLL
Horizontal Longline pull-up (when selected) @ logic Low
Max
V
0.40
0.2
2.30
0.02
V
V
Vcc -0.2
-10
Units
V
V
* With no output current loads, no active input or Longline pull-up resistors, all package pins at Vcc or GND, and the
LeA device configured with a MakeBits tie option. Icco is in addition to Iccpo'
2-163
II
XC3000L Logic Cell Array Family
CLB Switching Characteristic Guidelines
CLB OUTPUT (X,Y)
(COMBINATORIAL)
CLB INPUT (A,B,C,D,E)
CLBCLOCK
14----@
o
TCl - -..........
TDICK ----0'14--
CLBINPUT
(DIRECT IN)
CLBINPUT
(ENABLE CLOCK)
CLBOUTPUT
(FLIP-FLOP)
CLBINPUT
(RESET DIRECT)
CLBOUTPUT
(FLIP-FLOP)
1105 26
Buffer (Internal) Switching Characteristic Guidelines
Speed Grade
Description
Symbol
Global and Alternate Clock Distribution*
Either: Normal lOB input pad through clock buffer
to any CLB or lOB clock input
Or:
Fast (CMOS only) input pad through clock
buffer to any CLB or lOB clock input
TBUF driving a Horizontal Longline (L.L.)"
I to L.L. while T is Low (buffer active)
T J- to L.L. active and valid with single pull-up resistor
T J- to L.L. active and valid with pair of pull-up resistors
Ti to L.L. High with single pull-up resistor
Ti to L.L. High with pair of pull-up resistors
TplD
ns
T plDC
ns
T IO
ns
ns
ns
ns
ns
TON
TON
Tpus
TpUF
BIOI
Bidirectional buffer delay
ns
" Timing is based on the XC3042L, for other devices see XACT timing calculator.
2-164
CLB Switching Characteristic Guidelines (continued)
Testing of the switching parameters is modeled after testing methods specified by MIL-M-3851 0/605. All devices are 100%
functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing
patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more detailed, more
precise, and more up-to-date timing information, use the values provided by the XACT timing calculator and used in the simulator.
Speed Grade
Description
Symbol
Combinatorial Delay
Logic Variables A, B, C, 0, E, to outputs X or Y
Sequential delay
Clock k to outputs X or Y
Clock k to outputs X or Y when Q is returned
through function generators F or G to drive X or Y
Set-up time before clock
Logic Variables
Data In
Enable Clock
Reset Direct inactive
K
A,B,C,D,E
01
EC
RD
Hold Time after clock K
Logic Variables
Data In
Enable Clock
A,B,C,D,E
01
EC
Clock
Clock High time
Clock Low time
Max flip-flop toggle rate
Reset Direct (RD)
RD width
delay from RD to outputs X or Y
TllO
8
Units
ns
TCKO
II
TOLO
2
TICK
TDiCK
TECCK
ns
ns
ns
ns
TCKI
TCKDI
ns
ns
ns
11
12
TCH
TCl
FClK
ns
ns
MHz
13
9
TRPW
TRIO
ns
ns
TMRW
TMRO
ns
ns
4
6
3
5
7
Global Reset (RESET Pad)*
RESET width (Low)
delay from RESET pad to outputs X or Y
'Timing is based on the XC3042L, for other devices see XACT timing calculator.
2-165
XC3000L Logic Cell Array Family
lOB Switching Characteristic Guidelines
VO BLOCK (I)
-®-TPID~-f----
VOPADINPUT
~-G)-l--T-P-IC-K-----------------J
r-------------------.
1/0 CLOCK
(IKlOK)
@
~---
TIOL----~----
1/0 BLOCK (RI)
VOBLOCK(O)
VO PAD OUTPUT
(DIRECT)
va PAD OUTPUT
-----------------------------------~f0 TOKPO
(REGISTERED)
VOPADTS
VO PAD OUTPUT
110527C
OUT -+'-~IL'/
DIRECT IN
REGISTERED IN
--"-'-----t------,
--'-"'-----+---1
CK1
=0-
CK2
PROGRAM
CONmOllEO
MULTIPLEXER
o '"
PROGRAMMABLE INTERCONNECTION POINT Of' PIP
2-166
~XILINX
lOB Switching Characteristic Guidelines (continued)
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing
pattems. The following guidelines reflect worst-case values over the recommended operating conditions. For more detailed, more
precise, and more up-to-date timing information, use the values provided by the XACT timing calculator and used in the simulator.
Speed Grade
Description
Propagation Delays (Input)
Pad to Direct In (I)
Pad to Registered In (0) with latch transparent
Clock (IK) to Registered In (0)
Symbol
3
TplD
T PTG
4
TIKRI
ns
ns
ns
T plCK
ns
Set-up Time (Input)
Pad to Clock (IK) set-up time
Propagation Delays (Output)
Clock (OK) to Pad
(fast)
same
(slew rate limited)
Output (0) to Pad
(fast)
same
(slew-rate limited)
3-state to Pad begin hi-Z (fast)
same
(Slew-rate limited)
3-state to Pad active and valid (fast)
(slew -rate limited)
same
Set-up and Hold Times (Output)
Output (0) to clock (OK) set-up time
Output (0) to clock (OK) hold time
Clock
Clock High time
Clock Low time
Max. flip-flop toggle rate
Global Reset Delays (based on XC3042L)
RESET Pad to Registered In (0)
RESET Pad to output pad (fast)
(slew-rate limited)
Units
7
7
10
10
9
9
8
8
T OKPO
T OKPO
T OPF
Tops
TTSHZ
TTSHZ
TTSON
TTSON
ns
ns
5
6
11
12
13
15
15
ns
ns
ns
ns
ns
ns
FCLK
ns
ns
MHz
TRRI
T RPO
T RPO
ns
ns
ns
T 10H
T 10L
Notes: 1. Timing is measured at pin threshold, with 5() pF external capacitive loads (incl. test fixture). For larger capacitive loads,
see XAPP024. Typical slew rate limited output rise/fall times are approximately four times longer.
2. Voltage levels of unused (bonded and unbonded) pads must be valid logic levels. Each can be configured with the
internal pull-up resistor or alternatively configured as a driven output or driven from an external source.
3. Input pad set-up time is specified with respect to the internal clock (IK). In order to calculate system set-up time, subtract
clock delay (pad to IK) from the input pad set-up time value. Input pad holdiime with respect to the internal clock (IK) is
negative. This means that pad level changes immediately before the internal clock edge (IK) will not be recognized.
2-167
II
XC3000L logic Cell Array Family
For a detailed description of the device architecture, see pages 2-100 through 2-117.
For a detailed description of the configuration modes and their timing, see pages 2-118 through 2-126.
For detailed lists of package pin-outs, see pages 2-130 through 2-142.
For package physical dimensions, see Section 4.
Ordering Information
Example:
~Type
===r
XC3042L-8VQ100c
ILTan_~_~
Number of Pins
Block Delay
Package Type
Component Availability
+70·
Parentheses Indicate Mure product plans
2-168
XC3100
Logic Cell Array Family
Product Specifications
Features
• Ultra-high-speed FPGA family with six device types
Speed
Grade
TILO
-3
-4
-5
-125
-100
-70
2.7
3.3
4.1
5.5
7.0
9.0
XC31 00
- 50-SO MHz system clock rates
- Guaranteed flip-flop toggle rates of 190 to
270 MHz
XC3000
- Logic delays of 5 to 3 ns
- Performance 1.7-to-2 times that of the XC3000-125
- Optimized CMOS process
• 100% architecture, pin-out, software and bitstream
compatible with the XC3000 family devices
• XC3100-specific Features
- S mA output sink current and 4 mA source current
The devices are customized by the configuration program
data stored in internal memory cells. The FPGA can either
actively read its configuration data out of an external serial
or byte-parallel PROM (master modes), or the configuration can be written into the FPGA (slave and peripheral
modes). Xilinx offers a variety of companion serial-configuration PROMs for convenient program storage in a
one-time programmable device.
- Minimum power down and quiescent current is
0.5mA
- Additional 22 x 22 array size of the XC3195
- Easy migration to the XC3400 series of HardWire
mask-programmed devices for high-volume
production
Description
The XC3100 is a performance-optimized relative of the
industry-leading XC3000 family. While both families are
bitstream and footprint compatible, the XC3100 family
extends in-system performance to SO MHz and beyond.
The table in the next column provides a comparison between the XC31 00 family and the XC3000.
CLBs
64
100
144
224
320
484
Array
8x8
10x 10
12 x 12
16 x 14
16x20
22x22
270
230
190
125
100
70
The regular, flexible, reprogrammable array architecture is
composed of three standard types of programmable
elements: a perimeter of Input/Output Blocks (lOBs), a
core array of Configurable Logic Blocks (CLBs), and
resources for interconnection. Xilinx FPGAs can be
reprogrammed an unlimited number of times.
• Advanced O.S 11 performance
Device
XC3120
XC3130
XC3142
XC3164
XC3190
XC3195
Max Toggle Rate
The XACT development system delivers a powerful software tool set for design implementation: from schematic
capture, to simulation, auto place-and-route, and finally
the creation of the configuration bit stream.
The XC3100 family follows the XC4000 speed-grade
nomenclature, indicating device performance based on
the internal logic-block delay.
UserUO
Max
64
80
96
120
144
176
2-169
Flip-Flops
256
360
480
688
928
1,320
Horizontal
Longlines
16
20
24
28
40
44
Configuration
Data Bits
14,779
22.176
30,784
46,064
64,160
94.944
II
XC3100 logic Cell Array Family
Xilinx maintains test specifications for each product as controlled documents. To insure the use of the most recently
released device performance parameters, please request a copy of the current test-specification revision.
Absolute Maximum Ratings
Symbol Description
Units
Vcc
Supply voltage relative to GND
-0.5 to +7.0
V
V IN
Input voltage with respect to GND
-0.5 to Vee +0.5
V
VTS
Voltage applied to 3-state output
-0.5 to Vco +0.5
V
TSTG
Storage temperature (ambient)
-65 to +150
°C
TSOL
Maximum soldering temperature (10 s @ 1/16 in.)
+260
°C
Junction temperature plastic
+125
°C
Junction temperature ceramic
+150
°C
TJ
Note: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These
are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed
under Recommended Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for
extended periods of time may affect device reliability.
Operating Conditions
Symbol
Vee
Description
Supply voltage relative to GND
Commercial
Supply voltage relative to GND
Industrial
O°Cto +70°C
-40°C to +85°C
Min
Max
Units
4.75
5.25
V
4~5
5.5
V
VIHT
High-level input voltage - TIL configuration
2.0
Vee
V
VILT
low-level input voltage - TTL configuration
0
0.8
V
VIHe
High-level input voltage - CMOS configuration
70%
100%
Vee
VILe
low-level input voltage - CMOS configuration
0
20%
Vee
TIN
Input signal transition time
250
ns
2-170
~XIUNX
DC Characteristics Over Operating Conditions
Symbol
Description
Min
VOH
High-level output voltage (@ IOH = -B.O mA, Vcc min)
VOL
Low-level output voltage (@ IOL = B.O mA, Vcc max)
VOH
High-level output voltage (@ IOH = -8.0 mA, Vcc min)
Max
3.B6
Units
V
Commercial
0.40
3.76
V
V
Industrial
VOL
Low-level output voltage (@ IOL = B.O mA, Vcc max)
VeePD
Power-down supply voltage (PWRDWN must be Low)
leeo
Quiescent LCA supply current
Chip thresholds programmed as CMOS levels 1
0.40
2.30
Chip thresholds programmed as TTL levels
-10
V
V
5
mA
14
mA
+10
IlA
IlL
Input Leakage Current
CIN
Input capacitance, all packages except PGA 175
(sample tested)
All Pins except XTL 1 and XTL2
XTL1 and XTL2
10
15
pF
pF
Input capacitance, PGA 175
(sample tested)
All Pins except XTL1 and XTL2
XTL1 and XTL2
15
20
pF
pF
'\
IRIN
Pad pull-up (when selected) @ VIN = OV (sample tested)
0.02
0.17
rnA
IRLL
Horizontal long line pull-up (when selected) @ logic Low
0.20
2.BO
mA
Note: 1; With no output current loadS, no active input or long line pull-up resistors, all package pins at Vcc or GND,
and the LCA configured with a MakeBits tie option.
2. Total continuous output sink current may not exceed 100 mA per ground pin. The number of ground pins varies
from two for the XC3120 in the PC84 package, to eight for the XC3195 in the PQ208 or PG223 package.
2-171
II
XC3100 Logic Cen Array Family
CLB Switching Characteristic Guidelines
CLB OUTPUT (X.V)
(COMBINATORIAL)
CLB INPUT (A.B.C.D.E)
CLBCLOCK
~===-i@~121ilT;;;CL-==~'" ® TCH - - - - - + I
o TDtCK ---+I''''
CLBINPUT
(DIRECT IN)
CLBINPUT
(ENABLE CLOCK) _ _ _ _ _--"'--_ _ _ _ _ _-+__=-_1''-______
CLBOUTPUT
(FLIP-FLOP)
CLBINPUT
(RESET DIRECT)
CLBOUTPUT
(FLIP-FLOP)
1105 28
Buffer (Internal) Switching Characteristic Guidelines
Description
Speed Grade
-5
-4
-3
Symbol
Max
Mlix
Max
Units
Global and Alternate Clock Distribution*
Either: Normal lOB input pad through clock buffer
to any CLB or lOB clock input
Or:
Fast (CMOS only) input pad through clock
buffer to any CLB or lOB clock input
TplD
6.8
6.5
5.6
ns
TplOC
5.4
5.1
4.3
ns
TBUF driving a Horizontal Long line (l.l.)*
I to l.l. while T is Low (buffer active)
T J, to l.l. active and valid with single pull-up resistor
T J, to l.l. active and valid with pair of pull-up resistors
T1' to l.l. High with single pull-up resistor
T1' to l.l. High with pair of pull-up resistors
TIO
TON
TON
Tpus
TpUF
4.1
5.6
7.1
15.6
12.0
3.7
5.0
6.5
13.5
10.5
3.1
4.2
5.7
11.4
8.8
ns
ns
ns
ns
ns
BIOI
Bidirectional buffer delay
TBIDI
1.4
1.2
1.0
ns
• Timing is based on the XC3142. for other devices see XACT timing calculator.
2-172
CLB Switching Characteristic Guidelines (continued)
Testing of the switching parameters is modeled after testing methods specified by MIL-M-3851 0/605. All devices are 100%
functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing
patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more detailed, more
precise, and more up-to-date timing information, use the values provided by the XACT timing calculator and used in the simulator.
Description
Symbol
Combinatorial Delay
Logic Variables A, B, C, 0, E, to outputs X or Y
Sequential delay
Clock K to outputs X or Y
Clock K to outputs· X or Y when Q is returned
through function generators F or G to drive X or Y
Set-up time before clock
Logic Variables
Data In
Enable Clock
Reset Direct inactive
Hold Time after clock k
Logic Variables
Data In
Enable Clock
-4
-5
Speed Grade
Min
Max
Min
-3
Max
Min
Max Units
1
T llO
4.1
3.3
2.7
ns
8
T cKO
3.1
2.5
2.1
ns
T olo
6.3
5.2
4.3
ns
K
A,B,C,D,E
01
EC
RD
2
4
6
TICK
T DICK
T ECCK
3.1
2.0
3.8
1.0
2.5
1.6
3.2
1.0
2.1
1.4
2.7
1.0
ns
ns
ns
ns
A,B,C,D,E
01
EC
3
5
7
TCKI
TCKDI
T cKEC
0
1.2
1.0
0
1.0
0.8
0
0.9
0.7
ns
ns
ns
11
12
TCH
TCl
FClK
2.4
2.4
190
2.0
2.0
230
1.6
1.6
270
ns
ns
MHz
13
9
T RPw
3.8
Clock
Clock High time
Clock Low time
Max. flip-flop toggle rate
Reset Direct (RD)
RD width
delay from RD to outputs X or Y
Global Reset (RESET Pad)*
RESET width (Low)
delay from RESET pad to outputs X or Y
T MRW
T MRO
3.2
4.4
TRIO
18.0
2.7
3.7
15.0
17.0
3.1
ns
ns
12.0
ns
ns
13.0
14.0
'Timing is based on the XC3142, for other devices see XACT timing calculator.
Notes:
The CLB K to Q output delay (TCKO' #8) of any CLB, plus the shortest possible interconnect delay, is always longer than
the Data In hold time requirement (TCKD!' #5) of any CLB on the same die.
TILO ' TOLO and TICK are specified for 4-input functions. For 5-input functions or base FGM functiDns, each specification
increases by 0.8 ns (-5), 0.6 ns (-4) and 0.5 ns (-3).
2-173
II
XC3100 Logic Cell Array Family
lOB Switching Characteristic Guidelines
---=-®-TPID~-f----
110 BLOCK (I)
1/0 PAD INPUT
~-G)-l--T-P-IC-K-----------------J
VOCLOCK
(lK/OK)
~--
@
TIOt. --~f----
VO BLOCK (RI)
VOBLOCK(O)
VO PAD OUTPUT
(DIRECn
____________________________~)CG)T~PO
1/0 PAD OUTPUT
(REGISTERED)
VOPADTS
T-_1 r-
J-rr=-@-eTTSON--@-9
VO PAD OUTPUT
------------~(~
_______________~r__
1105270
(OUTPUT
~~:JS ~..)...!--I-----:::)L)--_t-,
OUT ~-"-"'--IL'/
DIRECT IN --"-'-----t----~-_,
REGISTERED IN
-=----+---1
PROGRAM
] - CONTROllED
MULTIPLEXER
o=
PROGRAMMABLE INTERCONNECTION POINT or PIP
2-174
lOB Switching Characteristic Guidelines (continued)
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/S05. All devices are 100%
functionally tested. Since many intemal timing parameters cannot be measured directly, they are derived from benchmark timing
patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more detailed, more
precise, and more up-to-date timing information, use the values provided by the XACT timing calculator and used in the simulator.
-5
Speed Grade
Description
Symbol
Min
-4
Max
Min
-3
Max
Min
Max Units
Propagation Delays (Input)
Pad to Direct In (I)
Pad to Registered In (q) with latch transparent
Clock (IK) to Registered In (Q)
4
TplD
TpTG
TIKRI
Set-up Time (Input)
Pad to Clock (IK) set-up time
1
T plCK
Propagation Delays (Output)
Clock (OK) to Pad
(fast)
same
(slew rate limited)
Output (0) to Pad
(fast)
same
(slew-rate limited)
3-state to Pad begin hi-Z (fast)
same
(slew-rate limited)
3-state to Pad active and valid (fast)
same
(slew -rate limited)
7
7
10
10
9
9
8
8
T OKPO
T OKPO
T OPF
Tops
TTSHZ
TTSHZ
TTSON
TTSON
Set-up and Hold Times (Output)
Output (0) to clock (OK) set-up time
Output (0) to clock (OK) hold time
5
6
TOOK
T OKO
6.2
0
5.6
0
5.0
0
ns
ns
11
12
T IOH
T IOl
2.4
2.4
190
2.0
2.0
230
1.6
1.6
270
ns
ns
MHz
Clock
Clock High time
Clock Low time
Max. flip-flop toggle rate
Global Reset Delays (based on XC3142)
RESET Pad to Registered In (Q)
RESET Pad to output pad (fast)
(Slew-rate limited)
3
FClK
13
15
15
TRRI
T RPO
T RPO
2.8
16.0
2.8
15.0
2.5
15.0
2.5
14.0
5.5
14.0
4.1
13.0
6.9
6.9
12.0
20.0
2.2
13.0
2.2
12.0
5.0
12.0
3.7
11.0
6.2
6.2
10.0
17.0
18.0
24.0
32.0
15.0
20.0
27.0
ns
ns
ns
ns
4.4
10.0
3.3
9.0
5.5
5.5
9.0
15.0
13.0
17.0
23.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes: 1. TIming is measured at pin threshold, with 50 pF external capacitive loads (incl. test fixture). For larger capacitive loads,
see XAPP 024. Typical slew rate limited output rise/fall times are approximately four times longer.
2. Voltage levels of unused (bonded and unbonded) pads must be valid logic levels. Each can be configured with the
internal pull-up resistor or alternatively configured as a driven output or driven from an external source.
3. Input pad set-up time is specified with respect to the internal clock (IK). In order to calculate system set-up time, subtract
clock delay (pad to ik) from the input pad set-up time value. Input pad holdtime with respect to the internal clock (IK) is
negative. This means that pad level changes immediately before the internal clock edge (IK) will not be recognized.
4. T P,o' TPrG' and TPICK are 3 ns higher for XTAL2 when the pin is configured as a user input.
2-175
II
XC3100 Logic Cell Array Family
For a detailed description of the device architecture, see pages 2-100 through 2-117.
For a detailed description of the configuration modes and their timing, see pages 2-118 through 2-126.
For detailed lists of package pin-outs, see pages 2-130 through 2-142.
For package physical dimensions, see Section 4.
Ordering Information
Example:
Device Type
IJ
XC3130 -3 PC44C
CT.m~mrumRM~
Number of Pins
Block Delay
Package Type
Component Availability
C = Commercial = 00 to +700 C
I = Industrial = _40 0 to +850 C
Parentheses indicate future product plans
2-176
~
XC2000 Logic Cell Array Families
Table of Contents
Overview ............................................................... 2-178
XC2000 Logic Cell Array Families ........................ 2-179
Architecture ....................................................... 2-179
Programmable Interconnect ............................. 2-183
Crystal Oscillator ............................................... 2-187
Programming .................................................... 2-188
Special Configuration Functions ....................... 2-191
Master Serial Mode ........................................... 2-192
Master Serial Mode Programming
Switching Characteristics ............................. 2-193
Master Parallel Mode ........................................ 2-194
Master Parallel Mode Programming
Switching Characteristics ............................. 2-195
Peripheral Mode ............................................... 2-196
Peripheral Mode Programming
Switching Characteristics ............................. 2-197
Slave Serial Mode ............................................. 2-198
Slave Serial Mode Programming
Switching Characteristics ............................. 2-198
Program Readback Switching
Characteristics .............................................. 2-199
General LCA Switching Characteristics ............ 2-200
Performance ..................................................... 2-201
Power ................................................................ 2-202
Pin Descriptions ................................................ 2-204
Configuration Pin Assignments ......................... 2-206
Component Availability ..................................... 2-208
Ordering Information ......................................... 2-208
XC2000 Logic Cell Array Family ........................... 2-209
Absolute Maximum Ratings .............................. 2-210
Operating Conditions ........................................ 2-210
DC Characteristics ............................................ 2-211
CLB Switching Characteristic Guidelines ......... 2-212
lOB Switching Characteristic Guidelines .......... 2-214
XC2000L Low-Voltage Logic Cell Array Family .... 2-215
Absolute Maximum Ratings .............................. 2-216
Operating Conditions ........................................ 2-216
DC Characteristics ............................................ 2-217
CLB Switching Characteristic Guidelines ......... 2-218
lOB Switching Characteristic Guidelines .......... 2-220
Ordering Information ......................................... 2-221
Component Availability ..................................... 2-221
2-177
II
XC2000 Logic Cell Array Families
Overview
Introduced in 1985, the XC2000 family has seen continuously increasing sales for 8 years. In 1993, Xilinx introduced the ZERO+ Family of 3.3 V devices, intended for the
fast growing market of battery-operated portable computers and instruments.
While the XC3000/xC3100 families offer more speed, a
wider range of device capacities and more packaging
options, and the XC4000 family offers more advanced
systems features, the XC2064 and XC2018 are the world's
lowest cost FPGAs, and they remain the most economical
solution for all applications where the XC3020 or XC4002A
features are not required.
Detailed performance specifications for the faster XC2000
devices and the XC2000L family of 3.3 V devices were not
available at press time. Contact your sales representative
or the nearest Xilinx sales offices for this information
2-178
XC2000
Logic Cell Array Families
Product Description
Features
• Fully Field-Programmable:
- 1/0 functions
- Digital logic functions
- Interconnections
• General-purpose array architecture
• Complete user control of design cycle
• Compatible arrays with logic cell complexity equivalent to 1 ,000 and 1 ,500 gates
• Available in 5-V and 3.3-V versions
• 100% factory tested
• Selectable configuration modes
• Low-power, CMOS, static-memory technology
• Performance equivalent to TTL SSIIMSI
• TTL or CMOS input thresholds
• Complete development system support
- XACT Design Editor
- Schematic Entry
- Macro Library
- Timing Calculator
- Logic and Timing Simulator
- Auto Place I Route
Description
The Logic Cell Array (LCA) is a high density CMOS
integrated circuit. Its user-programmable array architecture is made up of three types of configurable elements:
Input/Output Blocks, logic blocks and Interconnect. The
designer can define individual 1/0 blocks for interface to
external circuitry, define logic blocks to implement logic
functions and define interconnection networks to compose
larger scale logic functions. The XACT Development System provides interactive graphic design capture and automatic routing. Both logic simulation and in-circuit emulation are available for design verification.
The Logic Cell Array is available in a variety of logic
capacities, package styles, temperature ranges and speed
grades.
Device
Vcc
Typ. Logic
Capacity
(gates)
XC2064
XC2064L
XC2018
XC2018L
5.0V
3.3V
5.0V
3.3 V
800 -1,000
800-1,000
1,200 - 1,500
1,200 - 1,500
User
VO
CLBs
Max
Config.
bits
64
64
100
100
58
58
74
74
12,038
12,038
17,878
17,878
The XC2000 family operates with a nominal 5.0 V supply.
The XC2000L family operates with nominal 3.3 V supply.
The LCA logic functions and interconnections are determined by data stored in internal static-memory cells. Onchip logic provides for automatic loading of configuration
data at power-up. The program data can reside in an
EEPROM, EPROM or ROM on the circuit board or on a
floppy disk or hard disk. The program can be loaded in a
number of modes to accommodate various system requirements.
Architecture
The general structure of a Logic Cell Array is shown in
Figure 1. The elements of the array include three categories of user programmable elements: I/O Blocks (lOBs),
Configurable Logic Blocks (CLBs) and Programmable
Interconnections. The 1/0Bs provide an interface between
the logic array and the device package pins. The CLBs
perform user-specified logic functions, and the interconnect resources are programmed to form networks that
carry logic signals among the blocks.
LCA configuration is established through a distributed
array of memory cells.The XACT development system
generates the program used to configure the Logic Cell
Array which includes logic to implement automatic configuration.
Configuration Memory
The configuration of the Logic Cell Array is established by
programming memory cells which determine the logic
functions and interconnections. The memory loading process is independent of the user logic functions.
2-179
II
XC2000 Logic Cell Array Families
The static memory cell used for the configuration memory
in the Logic Cell Array has been designed specifically for
high reliability and noise immunity. Based on this design,
which has been patented, integrity of the LCA configuration memory is assured even under adverse conditions.
Compared with other programming alternatives, static
memory provides the best combination of high density,
high performance, high reliability and comprehensive testability. As shown in Figure 2, the basic memory cell
consists of two CMOS inverters plus a pass transistor used
for writing data to the cell. The cell is only written during
configuration and only read during readback. During normal operation the pass transistor is off and does not affect
the stability of the cell. This is quite different from the
normal operation of conventional memory devices, in
which the cells are continuously read and rewritten.
affected by extreme power supply excursions or very high
levels of alpha particle radiation. In reliability testing no soft
errors have been observed, even in the presence of very
high doses of alpha radiation.
Input/Output Block
Each user-configurable 1/0 block (lOB) provides an interface between the external package pin of the device and
the internal logic. Each 1/0 block includes a programmable
input path and a programmable output buffer. It also
provides input clamping diodes to provide protection from
electro-static damage, and circuits to protect the LCA from
latch-up due to input currents. Figure 3 shows the general
structure of the 1/0 block.
The outputs Q and Q control pass-transistor gates directly.
The absence of sense amplifiers and the output capacitive
load provide additional stability to the cell. Due to the
structure of the configuration memory cells, they are not
The input buffer portion of each 1/0 block provides threshold detection to translate external signals applied to the
package pin to internal logic levels. The input buffer
threshold of the 1/0 blocks can be programmed to be
compatible with either TTL (1.4 V) or CMOS (2.2 V) levels.
The buffered input signal drives both the data input of an
1/0 BLOCK
D
CONFIGURABLE
LOGIC BLOCK~
o
0
u
U 0 01
U
U 0 OJ
U
U 0 0
U
•
0
0
0
0
INTERCONNECT AREA
•
0
0
0
0
1104 01
Figure 1. Logic Cell Array Structure
2-180
I:XIUNX
READ or
WRITE
DATA
~~
--ii--i-'
~
I
• •.
.:.
::
a
:
Q
CONFIGURATION
CONTROL
__~~r-l~__~~__
It<.;.:.~;.:.:.:.:.~:< <.;.:.:.;.;.:.;.:-
:.:.:.:.;-:.:.:1
1105 12
Figure 2. Configuration Memory Cell
edge-triggered D flip-flop and one input of a two-input
multiplexer. The output of the flip-flop provides the other
input to the multiplexer. The user can select either the
direct input path or the registered input. based on the
content of the memory cell controlling the multiplexer. The
I/O Blocks along each edge of the die share common
clocks. The flip-flops are reset during configuration as well
as by the active-low chip RESET input.
Output buffers in the I/O blocks provide 4-mA drive for high
fan~out CMOS or TIL-compatible signal levels. The output
data (driving I/O block pin 0) is the data source for the I/O
block output buffer. Each I/O block output buffer is controlled by the contents of two configuration memory cells
which tum the buffer ON or OFF or select 3-state buffer
control. The user may also select the output buffer 3-state
control (I/O block pin TS). When this I/O block output
control signal is High (a logic one). the buffer is disabled
and the package pin is high-impedance.
Configurable Logic Block
An array of Configurable Logic Blocks (CLBs) provides the
functional elements from which the user's logic is constructed. The logic blocks are arranged in a matrix in the
TS (OUTPUT ENABLE)
OUT
IN
o
a 1----'--'
VOCLOCK
--fl....... -_
-U-
PROGRAM-CONTROLLEO
MULTIPLEXER
1104 03
Figure 3'. I/O Blc:ick
2-181
I
XC2000 Logic Cell Array Families
X
OUTPUTS
INPUTS
A
B
C
0
G
y
COMB.
LOGIC
F
CLOCK
1104 04
Figure 4. Configurable Logic .Block
center of the device. The XC2064 has 64 such blocks
arranged in an 8-row by 8-column matrix. The XC2018 has
100 logic blocks arranged in a 10 by 10 matrix.
Each logic block has a combinatorial logic section, a
storage element, and an intemal routing and control section. Each CLB has four general-purpose inputs: A, B, C
and D; and a special clock input (K), which may be driven
from the interconnect adjacent to the block. Each CLB also
has two outputs, X and Y, which may drive interconnect
networks. Figure 4 shows the resources of a Configurable
Logic Block.
The logic block combinatorial logic uses a table look-up
memory to implement Boolean functions. This technique
can generate any logic function of up to four variables with
a high speed sixteen-bit memory. The propagation delay
through the combinatorial network is independent of
the function generated. Each block can perform any
function of four variables or any two functions of three
variables each. The variables may be selected from
among the four inputs and the block's storage element
output Q. Figure 5 shows various options which may be
specified for the combinatorial logic.
Ifthe single 4-variable configuration is selected (Option 1),
the F and G outputs are identical. If the 2-function alternative is selected (Option 2), logic functions F and G may be
independent functions of three variables each. The three
variables can be selected from among the four logic block
inputs and the storage element output Q. A third form ofthe
combinatorial logic (Option 3) is a special case of the 2function form in which the B input dynamically selects
between the two function tables providing a single merged
logic function output. This dynamic selection allows some
5-variable functions to be generated from the four block
inputs and storage element Q. Combinatorial functions are
restricted in that one may not use both its storage element
output Q and the input variable of the logic block pin "D" in
the same function.
If used, the storage element in each Configurable Logic
Block (Figure 6) can be programmed to be either an edgesensitive "D" type flip-flop or a level-sensitive "D" latch. The
clock or enable for each storage element can be selected
from:
• The special-purpose clock input K
• The general-purpose input C
• The combinatorial function G
The user may also select the clock active sense within
each logic block. This programmable inversion elimi-nates
the need to route both phases of a clock signal throughout
the device.
The storage element data input is supplied from the
function F output of the combinatorial logic. Asynchronous SET and RESET controls are provided for each
storage element. The user may enable these controls
independently and select their source. They are active
High inputs and the asynchronous reset is dominant. The
2-182
B
A
B
......- f-F
A
D
tc
Any
Function
014
Variables
B
F
C
I
D
B
C
C
A
Any
Function
013
Variables
I-
'--
..... G
C
Q
A
Any
Function
013
Variables
D
F
Any
Function
013
Variables
G
D
A
B
Any
Function
013
Variables
B
G
C
H
D
I
Option 1
Option 2
Option 3
1 Function 01 4
Variables
2 Functions 01 3
Variables
Dynamic Selection 01
2 Functions 01 3
Variables
X3165
Figure 5. CLB Combinatorial Logic Options
Note: Variables D and Q can not be used in the same function.
storage elements are reset by the active-Low chip RESET
pin as well as by the initialization phase preceding configuration. If the storage element is not used, it is disabled.
The two block outputs, X and Y, can be driven by either the
combinatorial functions, F or G, or the storage element
output Q (Figure 4). Selection of the outputs is completely
interchangeable and may be made to optimize routing
efficiencies ofthe networks interconnecting the logic blocks
and 1/0 blocks.
switching matrices are provided to allow interconnections
of metal segments from the adjoining rows and columns.
Switches in the switch matrices and on block outputs are
specially designed transistors, each controlled by a configuration bit.
Logic-block output switches provide contacts to adjacent
general interconnect segments and therefore to the switching matrix at each end of those segments. A switch matrix
Programmable Interconnect
Programmable interconnection resources in the Logic Cell
Array provide routing paths to connect inputs and outputs
of the 1/0 and logic blocks into desired networks. All
interconnections are composed of metal segments, with
programmable switching points provided to implement the
necessary routing. Three types of resources accommodate different types of networks.
SET
F ---------lD
Q
K-·<----I
c-~::----I
• General purpose interconnect
• Longlines
• Direct connection
RES
D-{--....j
General-Purpose Interconnect
General-purpose interconnect, as shown in Figure 7a, is
composed of four horizontal metal segments between the
rows and five vertical metal segments between the columns of logic and 1/0 blocks. Each segment is only the
height or width of a logic block. Where these segments
would cross at the intersections of rows and columns,
2-183
Figure 6. CLB Storage Elememt
XC2000 Logic Cell Array Families
can connect an interconnect segment to other segments
to form a network. Figure 7a shows the general interconnect used to route a signal from one logic block to three
other logic blocks. As shown, combinations of closed
switches in a switch matrix allow multiple branches for
each network. The inputs of the logic or 1/0 blocks are
multiplexers that can be programmed with configuration
bits to select an input network from the adjacent interconnect segments. Since the switch connections to block
inputs are unidirectional (as are block outputs) they are
usable only for input connection. The development system software provides automatic routing of these interconnections. Interactive routing is also available for design
optimization. This is accomplished by selecting a
networkand then toggling the states of the interconnect
points by selecting them with the "mouse". In this mode,
the connections through the switch matrix may be established by selecting pairs of matrix pins. The switching
matrix combinations are indicated in Figure 7b.
CLB
,
-J SEE FIG. 7b
A
B
C
K
CLB
B
x
y
o
Special buffers within the interconnect area provide periodic signal isolation and restoration for higher general
Figure 7a. General-Purpose Interconnect
~-~-~.
II
2 Vertical
Long Lines
,..-A-, ,
!
/
Available Programmable
Switch Matrix Interconnections
of General Interconnect
Segments by Pin
Global
Net
I I/'
0
a
X
d
{~
y
DO
,,
,,
Q-,
, ,
' ,
0
t;Jt;JO
Ot;J 0
- } 4 Horizontal
:
:0
General Purpose
Interconnect
roo
0
0
0
0
_} Horizontal
Long Line
0
0
0
,
0
o
I I I I
I
'---...--'
5 Vertical General
Purpose Interconnects
Between Switch Matries
\ Programmable
Interconnect Points
(Do Not Use More Than
One Per Input Pin)
Figure 7b. Routing and Switch Matrix Connections
2-184
X3175
1104 07
interconnect fan-out and better performance. The repowering buffers are bidirectional, since signals must be able
to propagate in either direction on a general interconnect
segment. DirectiO?;Ontrols are automatically established
by the Logic Cell Array development system software.
Repowering buffers are provided only for the generalpurpose interconnect since the direct and Longline resources do not exhibit the same R-C delay accumulation.
The Logic Cell Array is divided into nine sections with
buffers automatically provided for general interconnect at
the boundaries of these sections. These boundaries can
be viewed with the development system. For routing
within a section, no buffers are used. The delay calculator
ofthe XACT development system automatically calculates
and displays the block, interconnect and buffer delays for
any selected paths.
that must travel a long distance or must have minimum
skew among multiple destinations.
A global buffer in the Logic Cell Array is available to drive
a single signal to all Band K inputs of logic blocks. Using the
global buffer for a clock provides a very low skew, high fanout synchronized clock for use at any or all of the logic blocks.
At each block, a configuration bit for the K input to the block
can select this global line as the storage element clock
signal. Altematively, other clock sources can be used.
A second buffer below the bottom row of the array drives
a horizontal Longline which, in turn, can drive a vertical
Longline in each interconnection column. This altemate
buffer also has low skew and high fan-out capability. The
network formed by this alternate buffer's Longlines can be
selected to drive the B, C or K inputs of the logic blocks.
Longlines
Longlines, shown in Figure 8a, run both vertically and
horizontally the height or width of the interconnect area.
Each vertical interconnection column has two Longlines;
each horizontal row has one, with an additional Longline
adjacent to each set of 1/0 blocks. The Longlines bypass
the switch matrices and are intended primarily for signals
---.I
B B
~t~~ B
B B
SWITCH
MATRIX
L
J
----1
Alternatively, these Longlines can be driven by a logic or
1/0 block on a column by column basis. This capability
provides a common, low-skew clock or control line within
each column of logic blocks. Interconnections of these
Longlines are shown in Figure 8b.
J
SWITCH
MATRIX
L-
L
L-.
TW~o~~~IZ:~-
HORIZONTAL
LONG LINE
r-r5~~JNE
1104 09
Figure Sa. Longline Interconnect
2-185
II
XC2000 Logic Cell Array Families
GLOBAL
BUFFER
~
\ qJ
J.
VERTICAL LONG LINES
(2 PER COLUMN)
HORIZONTAL LONG LINES
(1 PERROW)
~ 1EP~I ~\ !'Jl~~~~f'¥J~
1
1
1/0 CLOCKS
(1PER EDGE)
1/0 CLOCKS
(1 PER EDGE)
I'!'li!'l
I
ALTERNATE
BUFFER
Figure 8b. XC2064 Longlines, VO Clocks, VO Direct Interconnect
2-186
I'jll~
.
n
:{l
OSCILLATOR
AMPLIFIER
X1205
Direct Interconnect
Direct interconnect, shown in Figure 9, provides the most
efficient implementation of networks between adjacent
logic or 110 blocks. Signals routed from block to block by
means of direct interconnect exhibit minimum interconnect propagation and use minimum interconnect resources. For each Configurable Logic Block, the X output
may be connected directly to the C or D inputs of the CLB
above and to the A or B inputs of the CLB below it. The Y
output can use directinterconnectto drive the B input ofthe
block immediately to its right. Where logic blocks are
adjacent to I/O blocks, direct connect is provided to the
I/O block input (I) on the left edge of the die, the output (0)
on the right edge, or both on I/O blocks at the top and
bottom ofthe die. Direct interconnections of 1/0 blocks with
CLBs are shown in Figure 8b.
II
Crystal Oscillator
Figure 8b also shows the location of an internal high speed
inverting amplifier which may be used to implement an onchip crystal oscillator. It is associated with the auxiliary
buffer in the lower right corner of the die. When the
oscillator is configured by MAKEBITS and connected as a
signal source, two special user lOBs are also configured to
connect the oscillator amplifier with external crystal oscillator components as shown in Figure10. A divide by two
option is available to assure symmetry. The oscillator
circuit becomes active in order to allow the oscillator to
stabilize. Actual internal connection is delayed until completion of configuration. In Figure 10, the feedback resistor
R1, between the output and input, biases the amplifier at
threshold. The inversion of the amplifier, together with the
R-C networks and an AT-cut series resonant crystal,
produce the 360.degree phase shift of the Pierce oscillator. A series resistor R2 may be included to add to the
amplifier output impedance when needed for phase-shift
control, crystal resistance matching, orto limitthe amplifier
input swing to control clipping at large amplitudes. Excess
feedback voltage may be corrected by the ratio of C2IC1.
The amplifier is designed to be used from 1 MHz to about
one-half the specified CLB toggle frequency. Use at frequencies below 1 MHz may require individual characterization with respect to a series resistance. Crystal oscillators above 20 MHz generally require a crystal which
operates in a third overtone mode, where the fundamental
frequency must be suppressed by an inductor across C2,
turning this parallel resonant circuit to double !he fundamental crystal frequency, i.e., 213 of the desired third
harmonic frequency network. When the oscillator inverter
is notused, these lOBs and their package pins are available for general user 1/0.
1104 10
Figure 9. Direct Interconnect
ON-CHIP
EXTERNAL
ALTERNATE
CLOCK BUFFER
XTAL1
D
D
R2
SUGGESTED COMPONENT VALUES
RI 0.5 -I Mil
R2 0-1 Kll
(may be required for low
frequency, phase
shift and/or compensation
level for crystal Q)
CI,C210-40pF
VI I - 20 MHz AT cut series
resonant
XTAL1
XTAL2
4!!OIP
33
30
68 PLCC
46
43
68PGA
JIO
LIO
84PLCC
56
53
84PGA
Kit
Lit
1104 11
Figure 10. Crystal Oscillator
2-187
XC2000 Logic Cell Array Families
Programming
signalled by the release of the DONE / PROG pin of the
device as the device begins operation. This open-drain
output can be AND-tied with multiple Logic Cell Arrays and
used as an active-High READY or active-Low, RESET, to
other portions of the system. High during configuration
(HDC) and low during configuration (LDC), are released
one CCLK cycle before DONE is asserted. In master mode
configurations, it is convenient to use LDC as an activeLow EPROM chip enable.
Table 1. Configuration Mode Selection
As each data bit is supplied to the LCA, it is internally
assembled into a data word. As each data word is completely assembled, it is loaded in parallel into one word of
the internal configuration memory array. The last word
must be loaded before the current length count compare is
true. If the configuration data are in error, e.g., PROM
address lines swapped, the LCA will not be ready at the
length count and the counter will cycle through an additional complete count prior to configuration being "done".
Configuration data to define the function and interconnection within a Logic Cell Array are loaded automatically
at power-up or upon command. Several methods of automatically loading the required data are designed into the
Logic Cell Array and are determined by logic levels applied
to mode selection pins at configuration time. The form of
the data may be either serial or parallel, depending on the
configuration mode. The programming data are independent of the configuration mode selected. The state diagram of Figure 11 illustrates the configuration process.
Input thresholds for user I/O pins can be selected to be
either TTL-compatible or CMOS-compatible. At power-up,
all inputs are TTL-compatible and remain in that state until
the LCA begins operation. If the user has selected CMOS
compatibility, the input thresholds are changed to CMOS
levels during configuration.
Table 1 shows the selection of the configuration mode
based on the state of the mode pins MO and M1. These
package pins are sampled prior to the start of the configuration process to determine the mode to be used. Once
configuration is DONE and subsequent operation has
begun, the mode pins may be used to perform data
readback, as discussed later. An additional mode pin,
M2, must be defined at the start of configuration. This
package pin is a user-configurable I/O after configuration
is complete.
Figure 12 shows the specific data arrangement for the
XC2064 device. Future products will use the same data
format to maintain compatibility between different devices
of the Xilinx product line, but they will have different sizes
and numbers of data frames. For the XC2064, configuration requires 12,038 bits for each device. For the XC2018,
the configuration of each device requires 17,878 bits. The
XC2064 uses 160 configuration data frames and the
XC2018 uses 197.
The configuration bit stream begins with preamble bits, a
preamble code and a length count. The length count is
loaded into the control logic of the Logic Cell Array and is
used to determine the completion of the configuration
process. When configuration is initiated, a 24-bit length
counter is set to 0 and begins to count the total number of
configuration clock cycles applied to the device. When the
current length count equals the loaded length count, the
configuration process is complete. Two clocks before
completion, the internal logic becomes active and is reset.
On the next clock, the inputs and outputs become active as
configured and consideration should be given to avoid
configuration signal contention. (AUention must be paid to
avoid contention on pins which are used as inputsduring
configuration and become outputs in operation.) On the
last configuration clock, the completion of configuration is
Initialization Phase
When power is applied, an internal power-on-reset circuit
is triggered. When Vcc reaches the voltage at which the
LCA device begins to operate (nominally 2.5 to 3 V), the
chip is initialized, outputs are made high-impedance and a
time-out is initiated to allow time for power to stabilize. This
time-out (11 to 33 ms) is determined by a counter driven by
a self-generated, internal sampling clock that drives the
configuration clock (CCLK) in master configuration mode.
This internal sampling clock will vary with process, temperature and power supply over the range of 0.5 to 1.5
MHz. LCA devices with mode lines set for master mode
will time-out oftheir initialization using a longer counter (43
to 130 ms) to assure that all devices, which it may be
driving in a daisy chain, will be ready. Configuration using
peripheral or slave modes must be delayed long enough
for this initialization to be completed.
The initialization phase may be extended by asserting the
active-Low external RESET. If a configuration has begun,
an assertion of RESET will initiate an abort, including an
orderly clearing of partially loaded configuration memory
bits. After about three clock cycles for synchronization,
initialization will require about 160 additional cycles of the
internal sampling clock (197 for the XC2018) to clear the
internal memory before another configuration may begin.
2-188
Power-On Delay is
214 Cycles for Non-Master Mode-II to 33 ms
2 16 Cycles for Master Mode-43 to 130 ms
User 110 Pins wHh High Impedance Pull-Up. HDC=High. LDC=Low
,
PWRDWN
Inactive
PWRDWN
Active
II
Low on DONE/PROGRAM and RESET
Clear Is
- 160 Cycles forlhe XC2064-100 to 320
- 200 Cycles for the XC2018-125 10 390
~s
~s
X3037
Figure 11. A State Diagram of the Configuration Process for Power-up and Reprogram
11111111
0010
< 24-BIT LENGTH COUNT>
1111
o < DATA FRAME II 001> 111
o < DATA FRAME II 002 > 111
o < DATA FRAME II 003 > 111
DUMMY BITS (4 BITS MINIMUM). )(ACT 2.10 GENERATES 8 B.
PREAMBLE CODE
CONFIGURATION PROGRAM LENGTH
DUMMY BITS (4 BITS MINIMUM)
CONFIGURATION
FRAMES
DATA BITS
PER FRAME
m I
XC2018
XC2064
196
160
87
71
o < DATA FRAME II 159>
111
o < DATA FRAME II 160> 111
1111
HEADER
PROGRAM DATA
REPEATED FOR EACH LOGIC
CELL ARRAY IN A DAISY CHAIN
1104 15
POSTAMBLE CODE (4 BITS MINIMUM)
START-UP REQUIRES THREE CONFIGURATION CLOCKS BEYOND LENGTH COUNT
Figure 12. XC2064 Internal Configuration Data Arrangement
Reprogramming is initialized by a High-to-Low transition
on RESET (after RESET has been High for at least 6 ~)
followed by a Low level (for at least 6 ~) on both the
RESET and the open-drain OONEIPROG pins. This returns the LCA device to the CLEAR state, as shown in
Figure 11.
Master Mode
In Master mode, the Logic Cell Array automatically loads
the configuration program from an external memory device. The Master Serial mode uses serial configuration
data, synchronized by the rising edge of CCLK, as shown
in Figure 13.
In Master Parallel mode (Figure 14), the Logic Cell Array
provides 16 address outputs and the control signals RCLK
(Read ClOCk), HOC (High during configuration) and LOC
(Low during configuration) to execute Read cycles from
the external memory. Parallel 8-bit data words are read
and internally serialized. As each data word is read, the
least significant bit of each byte, normally 00, is the next bit
in the serial stream.
Addresses supplied by the Logic Cell Array can be selected by the mode lines to begin at address 0 and
incremented to reach the memory (master Low mode), or
they can begin at address FFFF Hex and be decremented
2-189
XC2000 Logic Cell Array Families
(master High mode). This capability is provided to allow
the Logic Cell Array to share external memory with another
device, such as a microprocessor. For example, if the
processor begins its execution from Low memory, the
Logic Cell Array can load itself from High memory and
enable the processor to begin execution once configuration is completed. The Done/PROG output pin can be used
to hold the processor in a Reset state until the Logic Cell
Array has completed the configuration process
Daisy Chain
The daisy-chain programming mode is supported by Logic
Cell Arrays in all programming modes. In master mode and
peripheral modes, the LCA device can act as a source of
data and control for slave devices. For example, Figure 14
shows a single device in master mode, with two devices in
slave mode. The master-mode device reads the external
memory and begins the configuration loading process for
all of the devices.
Peripheral Mode (Bit Serial)
Peripheral mode provides a simplified interface through
which the device may be loaded as a processor peripheral.
Figure 15 shows the peripheral mode connections. Processor Write cycles are decoded from the common assertion of the active-Low write strobe (IOWRT), and two
active-Low and of the active-High chip selects (CSO CS1
CS2). If all these signals are not available, the unused
inputs should be driven to their respective active levels.
The Logic Cell Array will accept one bit of the configuration
program on the data input (DIN) pin for each processor
Write cycle. Data is supplied in the serial sequence described earlier.
The data begins with a preamble and a length count which
are supplied to all devices at the beginning of the configuration. The length count represents the total number of
cycles required to load all of the devices in the daisy chain.
After loading the length count, the lead device will load its
configuration data while providing a High DOUT to downstream devices. When the lead device has been loaded
and the current length count has not reached the full value,
memory access continues. Data bytes are read and serialized by the lead device. The data is passed through the
lead device and appears on the data out (DOUT) pin in
serial form. The lead device also generates the configuration clock (CCLK) to synchronize the serial output data. A
master-mode device generates an internal CCLK of eight
times the EPROM address rate, while a peripheral mode
device produces CCLK from the chip select and write
strobe timing.
Since only a single bit from the processor data bus is
loaded per cycle, the loading process involves the processor reading a byte or word of data, writing a bit of the data
to the Logic cell Array, shifting the word and writing a bit
until all bits of the word are written, then continuing in the
same fashion with the next word, etc. After the configuration program has been loaded, an additional three clocks
(a total of three more than the length count) must be
supplied in order to complete the configuration process.
When more than one device is being used in the system,
each device can be assigned a different bit in the processor data bus, and multiple devices can be loaded on each
processor write cycle. This broadside loading method
provides a very easy and time-efficient method of loading
several devices.
Slave Mode
Slave mode, Figure 16, provides the simplest interface for
loading the Logic Cell Array configuration. Data is supplied
in conjunction with a synchronizing clock. For each Lowto-High input transition of configuration clock (CClK), the
data present on the data input (DIN) pin is loaded into the
internal shift register. Data may be supplied by a processor
or by other special circuits. Slave mode is used for downstream devices in a daisy-chain configuration. The data
for each slave LeA device are supplied by the preceding
LCA device in the chain, and the clock is supplied by the
lead device, which is configured in master or peripheral
mode. After the configuration program has been loaded,
an additional three clocks (a total of three more than the
length count) must be supplied in order to complete the
configuration process.
Operation
When all of the devices have been loaded and the length
count is complete, a synchronous start-up of operation is
performed. On the clock cycle following the end of loading,
the internal logic begins functioning in the reset state. On
the next CCLK, the configured output buffers become
active to allow signals to stabilize. The next CCLK cycle
produces the DONE condition. The length count control of
operation allows a system of multiple Logic Cell Arrays to
begin operation in a synchronized fashion. If the crystal
oscillator is used, it will begin operation before configuration is complete to allow time for stabilization before it is
connected to the internal circuitry.
Reprogram
The Logic Cell Array configuration memory may be rewritten while the device is operating in the user's system.
The LCA device returns to the Clear state where the
configuration memory is cleared, 110 pins disabled, and
mode lines re-sampled. Reprogram control is often implemented using an external open collector driver which pulls
DONE!PROG LOW. Once it recognizes a stable request,
the Logic Cell Array holds DONE!PROG LOW until the
new configuration has been completed. Even ifthe DONE!
PROG pin is externally held LOW beyond the configuration period, the Logic Cell Array begins operation upon
completion of configuration. To reduce sensitivity to noise,
these re-program signals are filtered for 2-3 cycles of the
2-190
LCA internal timing generator (2 to 6 IJS). Note that the
Clear time-out for a master-mode reprogram or abort does
not have the 4 times delay of the Initialization state. If a
daisy chain is used, an external RESET is required, long
enough to guarantee clearing all non-master mode devices. For XC2000-series LCA devices, this is accomplished with an external time delay.
• Input thresholds
• Readback disable
• DONE pull-up resistor
In some applications the system power supply might have
momentary failures which can leave the LCA control logic
in an invalid state. There are two methods to recover from
this state. The first is to cycle the Vcc supply to less than
0.1 V and re-apply valid Vcc' The second is to provide the
LCA device with simultaneous Low levels of at least 6 IJS
on RESET and DONEIPROG pins after the RESET pin
has been High following a return to valid Vcc' This guarantees that the LCA device will return to the Clear state.
Either of these methods may be needed in the event of an
incomplete voltage interruption. They are not needed for a
normal application of power from an off condition.
Input Thresholds
During configuration, all input thresholds are TTL level.
After configuration, input thresholds are established
as specified, either TTL or CMOS. The PWRDWN input
threshold is an exception; it is always a CMOS level input.
The TTL threshold option requires additional power for
threshold shifting.
Battery Backup
Because the control store of the Logic Cell Array is a
CMOS static memory, its cells require only a very low
standby current for data retention. In some systems, this
low data-retention current characteristic facilitates preserving configurations in the event of a primary power loss.
The Logic Cell Array has built in power-down logic which,
when activated, clears all internal flip-flops and latches,
but retains the configuration. All outputs are placed in the
high-impedance state, and all input levels are ignored. The
internal logic considers all inputs to be ones (High). Configuration is not possible during power down.
Power-down data retention is possible with a simple battery-backup circuit because the power requirement is
extremely low. For retention at 2.0 V, the required current
is typically on the order of 500 nA. Screening· to this
parameter is available. To force the Logic Cell Array into
the power-down state, the user must pull the PWRDWN
pin Low and continue to supply a retention voltage to the
Vcc pins of the package. When normal power is restored,
Vcc is elevated to· its normal operating voltage and
PWRDWN is returned to a High. The Logic Cell Array
resumes operation with the same internal sequence that
occurs at the conclusion of configuration. Internal 1/0 and
logic block storage elements will be reset, the outputs will
become enabled and then the DONEIPROG pin will be
released. No configuration programming is involved.
Special Configuration Functions
In addition to the normal user logic functions and interconnect, the configuration data include control for several
special functions:
Each of these functions is controlled by a portion of the
configuration program generated by the XACT Development System.
Readback
After a Logic Cell Array has been programmed, the configuration program may be read back from the device.
Readback may be used for verification of configuration,
and as a method of determining the state of internal logic
nodes during debugging. Three Readback options are
provided: on command, only once, and never.
An initiation of Readback is produced by a Low-to-High
tfansition ofthe MO I RTRIG (Read Trigger) pin. The CCLK
input must then be driven by external logic to read back the
configuration data. The first three Low-to-High CCLK
transitions clock out dummy data. The subsequent Lowto-High CCLK transitions shift the data frame information
out on the M1/RDATA (Read Data) pin. Note thatthe logic
polarity is always inverted, a zero in Configuration becomes a one in Readback, and vice versa. Note also that
each Readback frame has one Start bit (read back as a
one) but, unlike in Configuration, each Readback frame
has only one Stop bit (read back as a zero). The third
leading dummy bit mentioned above can be considered
the Start bit of the first frame.
All data frames must be read back to complete the process
and return the Mode Select and CCLK pins to their normal
functions. Readback data includes the state of all internal
storage elements. This information is used by the XACT
development system In-Circuit Debugger to provide visibility into the internal operation of the logic while the
system is operating. To read back a uniform time sample
of all storage elements, it may be necessary to inhibit the
system clock.
DONE Pull-up
The DONE I PROG pin is an open drain 1/0 that indicates
programming status. As an input, it initiates a reprogram
operation. An optional internal pull-up resistor may be
enabled.
The following seven pages describe the four configuration
modes in detail.
2-191
I
XC2000 Logic Cell Array Families
Master Serial Mode
• IF READBACK IS
ACTIVATED, A
5-kQ RESISTOR
IS REQUIRED IN
SERIES WITH Ml
DURING CONFIGURATION
THE 5 kQ M2 PULL-DOWN
RESISTOR OVERCOMES
THE INTERNAL PULL-UP,
BUT IT ALLOWS M2 TO
BE USER 110.
l I
el-
MO
L
-
-
Ml
+r
PWRDWN
~
DOUT
_
M2
OPTIONAL
DAISY-CHAINED
LCAsWITH
DIFFERENT
CONFIGURATIONS
HOC
---<: LDC
GENE RALPURP OSE
USE R 1/0
PINS
-
}o~"
1/0 PINS
-
~ OPTIONAL
LCA
r-
SLAVE LCAs
WITH IDENTICAL
CONFIGURATIONS
+5V
ET
DO NE
I
RESET
DIN
1->-r-
VCC
DATA
CCLK
1-----<>+
CLK
LDC
f--c
CE
Dip
rOE
r------------------,
VpP
Y
~I
SCP
CEO
XC17XX
(LOW RESETS THE XC17XX ADDRESS POINTER)
P----1
CASCADED
SERIAL
MEMORY
L_________________ _
X3033
Figure 13. Master Serial Mode
In Master Serial mode, the CCLK output of the lead LCA
device drives a Xilinx Serial PROM thatfeeds the LCA DIN
input. Each rising edge of the CCLK output increments the
Serial PROM internal address counter. This puts the next
data bit on the SPROM data output, connected to the LCA
DIN pin. The lead LCA device accepts this data on the
subsequent rising CCLK edge.
The lead LCA device then presents the preamble data
(and all data that overflows the lead device) on its
DOUTpin.
There is an internal delay of 1.5 CCLK periods, which
means that DOUT changes on the falling CCLK edge, and
the next LCA device in the daisy-chain accepts data on the
subsequent rising CCLK edge_
The SPROM CE input can be driven from either LDC or
DONE. Using LDC avoids potential contention on the DIN
pin, if this pin is configured as user-I/O, but LDC is then
restricted to be a permanently High user output. Using
DONE also avoids contention on DIN, provided the "early
DONE" option is invoked
2-192
Master Serial Mode Programming Switching Characteristics
CCLK
(OUTPUn
SERIAL DATA IN
SERIAL DOUT
(OUTPun _ _ _ _ _---J
' - -_ _ _ _ _---J ' - -_ _ _ _ _...J '-_ _ _ _ _ _ __
1105 29
-50
Speed Grade
Description
CCLK2
Data In setup
Data In hold
Symbol
1
2
TDSCK
TCKDS
Min
60
0
Max
-70
Min
60
0
Max
-100
Min
60
0
Units
Max
ns
ns
Notes: 1. At power-up, Vcc must rise from 2.0 V to Vcc min in less than 25 ms. If this is not possible, configuration can be delayed by holding RESET Low until Vcc has reached 4.0 V (2.5 V for XC2000L). A very long Vcc rise time of >100 ms, or
a ~n-monotonically rising Vcc may require a > 1-lls High level on RESET, followed by a >6-!!S Low level on RESET and
DIP after Vcc has reached 4.0 V (2.5 V for XC2000L).
2. Master-serial-mode timing is based on slave-mode testing.
2-193
I
XC2000 Logic Cell Array Families
Master Parallel Mode
.
+5V
5kll
l+
I I
+5V
MO Ml PWROWN
CCLK
-
M2
-
HOC
r-----
-
DIN
1------
HOC
A14
A14
LOC
A13
A13
A12
A12
All
All
Al0
LCA
MASTER
A9
Al0
DIN
...
LCA
SLAVE In
~1
HOC
-
LOC
J--
-
J USERVO
PINS
OTHER {
1/0 PINS
I-,---
A9
,----
DIP
-< RESET
AS
~ 06
A7
A7
07 r-,
r-r--
05
A6
A6
06
04
AS
AS
05 r-,
~ 03
~ 02
A4
A4
04 r--
A3
A3
03 r--
~ 01
A2
A2
02 r-,
~ DO
Al
Al
01r--
AO
AO
00r-,
ir
LOC
OE
0-
M2
GENERALPURPOSE
I--
AS
L
5kll
I-
OOUT
OTHER {
VOPINS
07
o/P
-< RESET
~
' - - - CCLK
5kll
A15
OTHER
VOPINS
I I
MO 1.11 PWROWN
OOUT
M2
A15
.
+5V
~
CCLK
EPROM
-
GENERALPURPOSE
USERVO
PINS
-
DIP
r-' RESET
r-NOTE: RESET OF A MASTER
DEVICE SHOULD BE ASSE RTEO
BY AN EXTERNAL TIMING
CIRCUIT TO ALLOW FOR LCACCLK
VARIATIONS IN CLEAR STATE TIME.
• IF REAOBACK IS
ACTIVATED, A
5-kll RESISTOR IS
REQUIRED IN
SERIES WITH Ml
,--+5V
CE
? 5 kll
8
OPEN
COLLECTOR
REPROGRAM
SYSTEM RESET
I I
11-
LCA
SLAVE 11
-
~
.
MO Ml PWROWN
OOUT
---< RCLK
GENERALPURPOSE
USER 1/0
PINS
+l
v
Lr:
V
"
I
1104 20A
Figure 14. Master Parallel Mode Configuration with Daisy Chained Slave Mode Devices. All are configured from the common
EPROM source. A well defined termination of SYSTEM RESET is needed when controlling multiple LeA devices.
In Master Parallel mode, the lead LCA device directly
addresses an industry-standard byte-wide EPROM and
accepts eight data bits right before incrementing (or
decrementing) the address outputs.
The eight data bits are serialized in the lead LCA device,
which then presents the preamble data (and all data that
overflows the lead device) on the DOUT pin. There is an
internal delay of 1.5 CCLK periods, after the rising CCLK
edge that accepts a byte of data, and also changes the
EPROM address, until the falling CCLK edge that makes
the LSB (DO) of this byte appear at DOUT. This means that
DOUT changes on the falling CCLK edge, and the next
LCA device in the daisy-chain accepts data on the subsequent rising CCLK edge.
Any XC3000 slave driven by an XC2000 master mode
device must use early DONE and early internal reset.
(The XC2000 master will not supply the extra clock required by a late programmed XC3000.)
2-194
l:XILINX
Master Parallel Mode Programming Switching Characteristics
Ao-A15
(OUTPUT)
XXXXXXX
' \_ _ _ _ _ _ _ _ _ _ _ _ _---J ........'-><-.lL.l........'-><-~ '-_ _ _ __
00-07
RCLI<
(OUTPUT)
1+-----
®
T R C L - - - - -......o---
II
CCLI<
(OUTPUT)
OOUT
(OUTPUT)
BYTE n-1
1104 33
Description
RCLK
Note:
From address invalid
To address valid
To data setup
To data hold
RCLKhigh
RCLKlow
Symbol
1
2
3
4
5
6
TARC
T RAC
TORC
TRCO
T RCH
T RCL
Min
Max
Units
0
200
ns
ns
ns
ns
ns
60
0
600
4.0
~
1. CCLK and DOUT timing are the same as for slave mode.
2. At power-up, Vcc must rise from 2.0 V to Vcc min in less than 25 ms. If this is not possible, configuration can be delayed by holding RESET Low until Vcc has reached 4.0 V (2.5 V for XC2000L). A very long Vcc rise time of >100 ms, or
a non-monotonically rising Vcc may require a >1-(.IS High level on RESET, followed by a >6·(.IS Low level on RESET and
DIP after Vcc has reached 4.0 V (2.5 V for XC2000L).
This timing diagram shows that the EPROM requirements are extremely relaxed: EPROM access time can be longer than
4000 ns, EPROM data output has no hold time requirement
2-195
XC2000 Logic Cell Array Families
Peripheral Mode
,..----..---..- +5 V
ADDRESS
BUS
DATA
BUS
• IF READ BACK IS
ACTIVATED, A
5·kll RESISTOR IS
REOUIRED IN SERIES
WITHM1
5kn
DO
10WRT
DIN
CCLK
WRT
DOUT
opnONAL
DAISY·CHANED
LCAs WITH DIFFERENT
CONFIGURATIONS
M2
ADDRESS
DECODE
LOGIC
CSO
HOC
LOC
'----------ctCS1
L:~~~~l
GENERAL·
PURPOSE
USER 110
PINS
' - - - - - - - - - 1 CS2
DONE
RESET
DIP
RESET
1104 1BA
Figure 15. Peripheral Mode. Configuration data is loaded using serialized data from a microprocessor.
Peripheral mode uses the trailing edge of the logic AND
condition ofthe csa, CS1, CS2, and WRT inputs to accept
byte-wide data from a microprocessor bus. In the lead LCA
device, this data is loaded into a double-buffered UARTlike parallel-to-serial converter and is serially shifted into
the internal logic, The lead LCA device presents the
preamble data (and all data that overflows the lead device)
on the DOUT pin.
goes Low when a byte has been received, and goes High
again when the byte-wide input buffer has transferred its
information into the shift register, and the buffer is ready to
receive new data, The length of the BUSY signal depends
on the activity in the UART. If the shift register had been
empty when the new byte was received, the BUSY signal
lasts for only two CCLK periods, If the shift register was still
full when the new byte was received, the BUSY signal can
be as long as nine CCLK periods.
The Ready/Busy output from the lead LCA device acts as
a handshake signal to the microprocessor. RDY/BUSY
2-196
Peripheral Mode Programming Switching Characteristics
CSO
CS1
CS2
II
CCLK(2)
(OUTPUT)
DIN
DOUT(2)
(OUTPUT)
1104 34
Description
Controls 1
(CSO, CS1,
CS2, WRT)
Symbol
Min
Active (last active
input to first inactive)
1
TCA
0.25
Inactive (first inactive
input to last active)
2
TCI
0.25
CCLK2
DIN setup
DIN hold
3
4
Tccc
Toc
TCD
5
Max
Units
5.0
!lS
!lS
75
50
0
ns
ns
ns
Notes: 1. Peripheral mode timing determined from last control signal of the logical AND of (CSO, CS1, CS2, WRT) to transition to
active or inactive state.
2. CCLK and DOUT timing are the same as for slave mode.
3. At power-up, V cc must _rise from 2.0 V to Vee min in less than 25 ms. If this is not possible, configuration can be delayed by holding RESET Low until Vcc has reached 4.0 V (2.5 V for XC2000L). A very long Vcc rise time of > 100 ms, or a
non-monotonically rising V cc may require a > 1-flS High level on RESET, followed by a >6'flS Low level on RESET and
DIP after Vcc has reached 4.0 V (2.5 V for XC2000L).
2-197
XC2000 Logic Cell Array Families
Slave Serial Mode
MO
M1 PWRDWN
51<0
MICRO
COMPUTER
OPTIONAL
STRB I------'-ICCLK
DO
M2
DIN
DAISY-CHANED
LCAs WITH DIFFERENT
CONFIGURATIONS
DOUT
HOC
01
VO
• IF READBACK IS
ACTIVATED, A
5-1<0 RESISTOR IS
REQUIRED IN SERIES
WITHM1
GENERALPURPOSE
USERVO
PINS
LOC
02
PORT
03
LCA
D4
OTHER {
05
VO PINS
D61~'---"r--'
07
X3034
Figure 16. Slave Serial Mode. Bit-serial configuration data are read at rising edge of the CCLK. Data on DOUT are provided on the
falling edge of CCLK_ Identically configured non-master mode LCAs can be configured in parallel by connecting DINs and CCLKs_
In Slave Serial mode, an external signal drives the CCLK
input(s) of the LCA device(s)_ The serial configuration
bitstream must be available at the DIN input of the lead
LCA device a short set-up time before each rising CCLK
edge_ The lead LCA device then presents the preamble
data (and all data that overflows the lead device) on its
DOUTpin.
There is an internal delay of 1_5 CCLK periods, which
means that DOUT changes on the falling CCLK edge, and
the next LCA device in the daisy-chain accepts data on the
subSequent rising CCLK edge_
Slave Serial Mode Programming Switching Characteristics
DIN~
BITN
~ CD Tocc" +- 0
BITN+1
TceD
=::j
@TcCL
CCLK
@TcCH
DOUT
(OUTPUT)
BITN-1
@Tcco",~
VV'I/
BITN
MI\'--_
__
1104 35
Description
CCLK
To DOUT
DIN setup
DIN hold
High time
Low time
Frequency
Symbol
1
2
3
4
5
Tcco
T Dcc
TCCD
TCCH
TCCL
Fcc
Min
Max
65
10
40
0_25
0_25
5_0
2
Unit
ns
ns
ns
JlS
JlS
MHz
Note: At power-up, Vcc must rise from 2_0 V to Vcc min in less than 25 ms_ If this is not possible, configuration can be delayed
by holding RESET Low until Vcc has reached (2_5 V for the XC2000L)_ A very long Vcc rise time of > 100 ms, or a no.!:!monotonically rising Vcc may require a >1-1lS High level on RESET, followed by a >6-1lS Low level on RESET and DIP
after Vcc has reached (2_5 V for the XC2000L)_
2-198
Program Readback Switching Characteristics
OONEIPROG
(Output)
_
-i________________ ________________ _
@TDRTJ-J+-. ®'~1
CCLK(1)
ROATA
d
_
RTRIG
@TRTCC
is\\
~
\'---------
_________~_4_"~C~C~~D_~i,~-----------------------------------~
(Output)
Valid
II
X3168
Description
Symbol
Min
RTRIG
PROG setup
RTRIG high
11
12
TORT
TRTH
300
250
CCLK
RTRIG setup
RDATAdelay
13
14
TRTCC
TCCRO
100
Max
ns
ns
100
Notes: 1. CCLK and DOUT timing are the same as for slave mode.
2. DONE/PROG outpuVinput must be HIGH (device programmed) prior to a positive transition of RTRIG (MO).
3. Readback is not supported for the XC2000L.
2-199
Units
ns
ns
XC2000 Logic Cell Array Families
General LCA Switching Characteristics
PWROWN
_____I
Vee (VALID)
MO/M11M2
OONEIPROG
(I/O)
USER I/O
~0TPGW=r
------~------~.~ .----------------------------USER STATE
~LIN_I_TI_Al_IZA
__T_IO_N_S_T_AT_E________________
~@TCLH
CLOCK
t
Symbol
Min
M2, M1, MO setup
M2, M1, MO hold
Width-FF Reset
High before RESET4
Device Reset4
2
60
60
150
ns
ns
ns
6
6
I1s
Progam width (Low)
Initialization
Device Reset 4
7
8
9
T pGW
TpGI
T OROW
6
I1S
I1S
I1S
10
11
TClH
TCll
8
8
ns
ns
Description
RESET"
DONE/PROG
CLOCK
@TCLL=1~---
Clock (High)
Clock (Low)
3
4
5
6
TMR
TRM
T MRW
TRH
T ORRW
Max
Units
I1S
6
7
Notes: 1. At power-up, Vcc mllst rise from 2.0 V to Vcc min in less than 25 ms. If this is not possible, configuration can be
delayed by holding RESET Low until Vcc has reached (2.5 V for the XC2000L). A very long Vcc rise time of >100
ms, or a non-mon~onically rising Vcc may require a > 1-l1s High level on RESET, followed by a >6-1lS Low level
on RESET and DIP after Vcc has reached (2.5 V for the XC2000L).
2. RESET timing relative to power-on and valid mode lines (MO, M1, M2) is relevant only when RESET is used to
delay configuration.
3. Minimum CLOCK widths for the auxiliary buffer are 1.25 times the T ClH' TCll'
4. After RESET is High, RESET = DIP
=Low for 6 I1s will abort to CLEAR.
2-200
Performance
The high performance of the Logic Cell Array results from
its patented architectural features and from the use of an
advanced high-speed CMOS manufacturing process.
Performance may be measured in terms of minimum
propagation times for logic elements.
L.....
Flip-flop loop delays for the I/O block and logic block flipflops are about 3 ns. This short delay provides very good
performance under asynchronous clock and data conditions. Short loop delays minimize the probability of a
metastable condition which can result from assertion of
the clock during data transitions. Because of the short loop
delay characteristic in the LCA device, the I/O block flipflops can be used very effectively to synchronize external
signals applied to the device. Once synchronized in the
I/O block, the signals can be used internally without further
consideration of their clock relative timing, except as it
applies to the internal logic and routing path delays.
F=Q
rLD
Q
1--'-- x.v
l>
K
X3166
Figure 17. Logic Block Configuration for Toggle Rate
Measurement
Actual Logic Cell Array performance is determined by the
critical path speed, including both the speed of the logic
and storage elements in that path, and the speed of the
particular network routing. Figure 18 shows a typical
system logic configuration of two flip-flops with an extra
combinatorial level between them. To allow the user to
make the best use of the capabilities of the device, the
delay calculator in the XACT Development System determines worst-case path delays using actual impedance
and loading information.
Device Performance
The single parameter which most accurately describes the
overall performance of the Logic Cell Array is the maximum toggle rate for a logic block storage element configured as a toggle flip-flop. The configuration for determining
the toggle performance of the Logic Cell Array is shown in
Figure 17. The clock for the storage element is provided
by the global clock buffer and the flip-flop output Q is fed
back through the combinatorial logic to form the data input
for the next clock edge. Using this arrangement, flip-flops
in the Logic Cell Array can be toggled at clock rates from
33-100 MHz, depending on the speed grade used.
Logic Block Performance
Logic block propagation times are measured from the
interconnect pOint at the input of the combinatorial logic to
the output of the block in the interconnect area. Combinatorial performance is independent of logic function
Combinatorial CLB
Inputs -
-
r-i--
F
i--
Source CLB
Inputs
-
i;----
-
i;----
-
i--
F
I--
D
c-
t>
1--
Destination CLB
Q
'\ 7
General
Interconnect
F
I---
D
r-
t>
Q
f-- ! -
Global
Clock
Global
Clock
X3167
Figure 18. Typical Logic Path
2-201
II
XC2000 Logic Cell Array Families
because of the table look-up based implementation. Timing is different when the combinatorial logic is used in
conjunction with the storage element. For the combinatorial logic function driving the data input of the storage
element, the critical timing is data set-up relative to the
clock edge provided to the storage element. The delay
from the clock source to the output of the logic block is
critical in the timing of signals produced by storage elements. The loading on a logic block output is limited only
by the additional propagation delay of the interconnect
network. Performance of the logic block is a function of
supply voltage and temperature, as shown in Figure 19 .
loading on the signal path at all points along the path. In
calculating the worst-case delay for a general interconnect
path, the delay calculator portion of the XACT development system accounts for all of these elements. As an
approximation, interconnect delay is proportional to the
summation of totals of local metal segments beyond each
programmable switch. In effect, the delay is a sum of R-C
delays each approximated by an R times the total C it
drives. The R of the switch and the C of the interconnect
are functions of the particular device performance grade.
For a string of three local interconnects, the approximate
delay at the first segment, after the first switch resistance,
would be three units; an additional two delay units after the
next switch plus an additional delay after the last switch in
the chain. The interconnect R-C chain terminates at each
repowering buffer. Nearly all of the capacitance is in the
interconnect metal and switches; the capacitance of the
block inputs is not significant.
Interconnect Performance
Interconnect performance depends on the routing resource used to implement the Signal path. As discussed
earlier, direct interconnect from block to block provides a
minimum delay path for a signal.
Power
The single metal segment used for Longlines exhibits low
resistance from end to end, but relatively high capacitance. Signals driven through a programmable switch
will have the additional impedance of the switch added to
their normal drive impedance.
Power Distribution
Power for the LCA is distributed through a grid to achieve
high noise immunity and isolation between logic and 1/0.
For packages having more than 48 pins, two Vcc pins and
two ground pins are provided (see Figure 20). Inside the
LCA device, a dedicated Vcc and ground ring surrounding
the logic array provides power to the 1/0 drivers. An
General-purpose interconnect performance depends on
the number of switches and segments used, the presence
of the bidirectional repowering buffers and the overall
1.00
0.80
~UJ
'"
'~" 0.60
TYPICAL COMMERCIAL
(+ 5.0 V. 25°C)
~
•
•
a:
o
z
TYPICAL MILITARY
0.40
MIN COMMERCIAL 7.5 ~
MIN.,MJIJ1.AP.:! i4~5_V.l_ - --:
MIN COMMERCIAL 5~2: ______ - - - - - - :
_____ - - - - - - - MIN M:~~l'~ 5"5_V} - - - -
0.20
1
------_ ... --
.--...
r------- ---_ __________________
_
I
_----
L __________ _
-55
-40
-20
o
25
40
70
80
100
TEMPERATURE (OC)
Figure 19. Relative Delay as a Function of Temperature, Supply Voltage and Processing Variations
2-202
125
Xl 045
100
90
BO
L 70
60
/
50
40
150-l----+---_+--+---Jf--+----I----Y/'-----+_+---+ 30
/
/v
/
/
loo-l----+---_+--+---Jr_+---+-~-_+_-~_+_+
/v
V
O-l----+---_+--+-~f--+-/~-+--/~-+--+/74-+
20
10
9
Ot---~--_t--+--Jr-~--~~,,/'------r-~/'-----+-+ B
0~--~--_t--+~r-r--~~--~,,'-----1-_t-+
"
(mW)
5
20 CLB Outputs
3Local Segments
/
/
/"
2
/
1
.B
/
/
/
.6
r--/~.-+--/~-r--I--+-+~--r---+--+--r-r.5
+/-T----+-/--7"-+--+--+V--7"l-----t---+--+---+-+.4
~--_b~-_t--+~r-r---+_--+-1-_t-+.3
(3mW/MHz)
/
/
/V
//
Buffer
1-1-~~-+---_+~-+--r_+---+---_+_--I-_+_+.2
(1.25 )t
//
(mWIMHz)
(rnA)
I
/
/
5
r---¥---+.~~_+_t--,,-r-+---+-~--If--t.7
Eaeh3
Global Clock
/
4/ "
"
1 110 Output 0.5 -I----+:.,c--_+--+--f--+-----I----I---I--+_+
(50pF) 0.5
1
4 5
20
10
30 40 50
Frequency MHz
(0.4 mW/MHz) /
1 CLB Output
3 Local
Interconnect
X3176
Figure 20. Typical LCA Power Consumption by Element
independent matrix of V cc and ground lines supplies the
interior logic of the device. This power distribution grid
provides a stable supply and ground for all internal logic,
providing the external package power pins are appropriately decoupled. Typically a 0.1 /IF capacitor connected
between the Vcc and ground pins near the package will
provide adequate decoupling.
GND
r.:;=:;==;:=;=~~=;=::;::=;:~t__::GROUNDAND
II
Vee RING FOR
t--t --t--t --t--t--t--t
,
I
I
I
I
I
I
VODRIVERS
I
+--+-- + --+- -+ --+ --+--+
Vee
I
I
,
I
I
,
,
I
I
I
I
I
I
I
I
I
t --t--t --t--t --t --t--t
t--t--t--t--t--t--t,-t
+-~+.- +--t-- f--f- -t-- +
+--t--+--+--f-- :-_+-__-+~,
+- -+-- +--+ --+--+- -+-- +
..-n---,
LOGIC POWER GRle
+--+--+ --+--+--+--+--+
1104 12
GND
Figure 21. LCA Power Distribution
Output buffers capable of driving the specified 4 mA loads
under worst-case conditions may be capable of driving 25
to 30 times that current in a best case. Noise can be
reduced by minimizing external load capacitance and
reducing simultaneous output transitions in the same
direction. It may also be beneficial to locate heavily loaded
output buffers near the ground pads. Multiple Vcc and
ground pin connections are required for package types
which provide them.
2-203
XC2000 L.ogic Cell Array Families
Power Consumption
Pin Descriptions
The Logic Cell Array exhibits. the low power consumption
characteristic of CMOS ICs. Only quiescent power is
required for the LCA configured for CMOS input levels.
The TTL input level configuration option requires additional power for level shifting. The power required by the
static memory cells which hold the configuration data is
very low and may be maintained in a power-down mode.
Typically most of power dissipation is produced by capacitive loads on the output buffers, where the incremental
power consumption is 251lW / pF / MHz. Another component of I/O power is the dc loading on each output pin. For
any given system, the user can calculate the I/O power
requirement based on the sum of capacitive and resistive
loading of the devices driven by the Logic Cell Array.
Internal power supply dissipation is a function of clock
frequency and the number of nodes changing on each
clock. In an LCA the fraction of nodes changing on a given
clock is typically low (10-20%). For example, in a 16-bit
binary counter, the average clock produces a change in
Slightly less than 2 of the 16 bits. In a 4-input AND gate
there will be 2 transitions in 16 states. Typical global clock
buffer power is about 2.5 mW / MHz for the XC2064 and
3.2 mW / MHz for the XC2018. With a typical load of three
general interconnect segments, each Configurable Logic
Block output requires about 0.22 mW / MHz of its output
frequency. At 3.3 V, the dynamic power consumption is
reduced by the square of the voltage ratio, i.e, about 56%.
Permanently Dedicated Pins.
V
O~~ or two (depending on package type) connections to
the nominal +5 V supply voltage. All must be connected.
GND
One or two (depending on package type) connections to
ground. All must be connected.
PWRDWN
A Low on this CMOS-compatible input stops all internal
activity, but retains configuration. All flip-flops and latches
are reset, all outputs are 3-stated, and all inputs are
interpreted as High, independent of their actual level.
While PWRDWN is Low, Vcc may be reduced to any value
>2.3 V. When PWDWN returns High, the LCA becomes
operational with DONE Low for two cycles of the internal
1-MHz clock. During configuration, PWRDWN must be
High. If not used, PWRDWN must be tied to Vcc'
RESET
This is an active Low input which has three functions.
Prior to the start of configuration, a Low input will delay the
startofthe configuration process. An internal circuit senses
the application of power and begins a minimal time-out
cycle. When the time-out and RESET are complete, the
levels olthe M lines are sampled and configuration begins.
If RESET is asserted during a configuration, the LCA
device is re-initialized and restarts the configuration at the
termination of RESET.
Dynamic Power Consumption
XC2018 at 5.0V
One GL.B driving three local interconnects
0.22 mW/MHz
One device output with a 50-pF load
2.0 mW/MHz
One global clock buffer and line
3.2 mW/MHz
If RESET is asserted after configuration is complete, it
provides a global asynchronous reset of all lOB and CLB
storage elements of the LCA device.
RESET can also be used to recover from partial power
failure. See section on Re-program under "Special Configuration Functions."
CCLK
During configuration, Configuration Clock is an output of
an LCA in Master mode or Peripheral mode, but an input
in Slave mode. During a Readback, CCLK is a clock input
for shifting configuration data out of the LCA.
CCLK drives dynamic circuitry inside the LCA. The Low
time may, therefore, not exceed a few microseconds.
When used as an input, CCLK must be "parked High". An
internal pull-up resistor maintains High when the pin is not
being driven.
2-204
OONEIPROG (O/p)
DONE is an open-drain output, configurable with or without an internal pull-up resistor. At the completion of configuration, the LCA circuitry becomes active in a synchronous order; DONE goes active High one cycle after
the lOB outputs go active.
Once configuration is done, a High-to-Low transition of
this pin will cause an initialization of the LCA and start a
reconfiguration.
MO/RTRIG
As Mode 0, this input and M1, M2 are sampled before the
start of configuration to establish the configuration mode to
be used.
A Low-to-High input transition, after configuration is complete, acts as a Read Trigger and initiates a Readback of
configuration and storage-element data clocked by CCLK.
By selecting the appropriate Readback option when generating the bitstream, this operation may be limited to a
single Readback, or be inhibited altogether.
M1/ROATA
As Mode 1, this input and MO, M2 are sampled before the
start of configuration to establish the configuration mode to
be used. If Readback is never used, M1 can be tied directly
to ground or Vcc. If Readback is ever used, M 1 must use
a 5-kQ resistor to ground or V cC' to accommodate the
RDATA output.
As an active Low Read Data, after configuration is complete, this pin is the output of the Readback data.
User VO Pins that can have special functions.
M2
During configuration, this input has a weak pull-up resistor.
Together with MO and M 1, it is sampled before the start of
configuration to establish the configuration mode to be
used. After configuration, this pin is a user-programmable
I/O pin.
HOC
During configuration, this output is held at a High level to
indicate that configuration is not yet complete. After configuration, this pin is a user-programmable 1/0 pin.
LOC
During Configuration, this output is held at a Low level to
indicate that the configuration is not yet complete. After
configuration, this pin is a user-programmable I/O pin.
LDC is particularly useful in Master mode as a Low enable
for an EPROM, but it must then be programmed as a High
after configuration.
XTL1
This user 1/0 pin can be used to operate as the output of
an amplifier driving an external crystal and bias circuitry.
XTL2
This user 1/0 pin can be used as the input of an amplifier
connected to an external crystal and bias circuitry. The 1/0
Block is left unconfigured. The oscillator configuration is
activated by routing a net from the oscillator buffer symbol
output and by the MAKEBITS program.
CSO,CS1,CS2,VVRT
These four inputs represent a set of signals, three active
Low and one active High, that are used to control
configuration-data entry in the Peripheral mode.
Simultaneous assertion of all four inputs generates a
Write to the internal data buffer. The removal of any
assertion clocks in the DO-D7 data. In Master mode,these
pins become part ofthe parallel configuration byte, D4, D3,
D2, D1. After configuration, these pins ar.e userprogrammable 1/0 pins.
RCLK
During Master parallel mode configuration RCLK represents a "read" of an external dynamic memory device
(normally not used).
00-07
This set of eight pins represents the parallel configuration
byte for the parallel Master mode. After configuration is
complete they are user programmed 1/0 pins.
Ao-A15
During Master Parallel mode, these 16 pins present an
address output for a configuration EPROM. After configuration, they are user-programmable 1/0 pins.
OIN
During Slave or Master Serial configuration, this pin is
used as a serial-data input. In the Master or Peripheral
configuration, this is the Data 0 input.
OOUT
During configuration this pin is used to output serialconfiguration data to the DIN pin of a daisy-chained slave.
Unrestricted User 1/0 Pins.
VO
An 1/0 pin may be programmed by the user to be an Input
or an Output pin following configuration. All unrestricted II
pins, plus the special pins mentioned on the following
page, have a weak pull-up resistor of 40 to 100 ill that
becomes active as soon as the device powers up, and
stays active until the end of configuration.
o
2-205
II
XC2000 Logic Cell Array Families
XC2064 Configuration Pin Assignments
USER
OPERATION
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
«HIGH» IS HIGH IMPEDANCE WITH A 20-50 kn INTERNAL PULL-UP DURING CONFIGURATION
1104 28A
Note: A PLCC in a ·PGA-Foolprinl" socket has a different signal pinout than a PGA device_
2-206
XC2018 Configuration Pin Assignments
USER
OPERATION
110
110
II
110
110
110
110
110
110
«HIGH» IS HIGH IMPEDANCE WITH A 20-5 len INTERNAL PULL-UP DURING CONFIGURATION
2-207
><3260
XC2000 Logic Cell Array Families
For a detailed description of the device architecture, see pages 2-179 through 2-187.
For a detailed description of the configuration modes and their timing, see pages 2-192 through 2-198.
For package physical dimensions, see Section 4.
Ordering Information
Jr.T.mpe~"rn Ra"~
Example:
XC2064-70PC44C
Device Type
T
Toggle Rate
Number of Pins
Package Type
Component Availability
C =Commercial =0° to +70° C
M =Mil Temp
=_55
I = Industrial = _40° to +85" C
B = MIL·STD·B83C Class B
Parentheses indicate future product plans
0
to +125° C
2-208
XC2000
Logic Cell Array Family
Product Specification
Features
• Fully Field-Programmable:
- 1/0 functions
- Digital logic functions
- Interconnections
• General-purpose array architecture
• Complete user control of design cycle
• Compatible arrays with logic cell complexity equivalent to 1,000 and 1,500 gates
• Standard product availability
• 100% factory-tested
• Selectable configuration modes
Description
The Logic Cell Array (LCA) is a high density CMOS
integrated circuit. Its user-programmable array architecture is made up of three types of configurable elements:
Input/Output Blocks, logic blocks and Interconnect. The
designer can define individual 1/0 blocks for interface to
external circuitry, define logic blocks to implement logic
functions and define interconnection networks to compose
larger scale logic functions. The XACT Development System provides interactive graphic design capture and automatic routing. Both logic simulation and in-circuit emulation are available for design verification.
The Logic Cell Array is available in a variety of logic
capacities, package styles, temperature ranges and speed
grades.
• Low-power, CMOS, static-memory technology
Logic
Capacity
• Performance equivalent to TTL SSIIMSI
• TTL or CMOS input thresholds
Device
(gates)
• Complete development system support
- XACT Design Editor
- Schematic Entry
- Macro Library
- Timing Calculator
- Logic and Timing Simulator
- Auto PlacelRoute
XC2064
XC2018
800 -1,000
1,200 - 1 ,500
User
CLBs
Max
Config.
bits
64
100
58
74
12038
17878
VO
The LCA logic functions and interconnections are
determined by data stored in internal static-memory cells.
On-chip logic provides for automatic loading of configuration
data at power-up. The program data can reside in
an EEPROM, EPROM or ROM on the circuit board or
on a floppy disk or hard disk. The program can be loaded
in a number of modes to accommodate various system
requirements.
2-209
II
XC2000 Logic Cell Array Families
Xilinx maintains test specifications for each product as controlled documents. To insure the use of the most recently
released device performance parameters, please request a copy of the current test-specification revision.
Absolute Maximum Ratings
Units
Symbol Description
Vcc
Supply voltage relative to GND
-0.5 to +7.0
V
V IN
Input voltage with respect to GND
-0.5 to Vee +0.5
V
Vrs
Voltage applied to 3-state output
-0.5 to Vcc +0.5
V
TSTO
Storage temperature (ambient)
-65 to +150
°C
TSOL
Maximum soldering temperature (10 s @ 1116 in.)
+260
°C
Note:
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These
are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed
under Recommended Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for
extended periods of time may affect device reliability.
Operating Conditions
Symbol
Vcc
Min
Max
Units
4.75
5.25
V
-40°C to +85°C
4.5
5.5
V
-55°C to + 125°C
4.5
5.5
V
Description
Supply voltage relative to GND
Commercial
Supply voltage relative to GND
Industrial
Supply voltage relative to GND
Military
,
0°Cto+70~C
VIHT
High-level input voltage - TIL configuration
2.0
Vcc
V
ViLT
LOW-level input voltage -
0
0.8
V
VIHC
High-level input voltage - CMOS configuration
70%
100%
Vec
VILC
Low-level input voltage - CMOS configuration
0
20%
Vcc
TIN
Input signal transition time
250
ns
TIL configuration
2-210
E:XIUt>JX
DC Characteristics Over Operating Conditions
Symbol
Description
Min
=-4.0 ma Vcc min)
V OH
High-level output voltage (@ IOH
VOL
Low-level output voltage (@ IOL
V OH
High-level output voltage (@ IOH
VOL
Low-level output voltage (@ IOL
V CCPD
Power-down supply voltage (PWRDWN mustbe Low)
Icco
Quiescent operating power supply current
Commercial
3.86
=4.0 ma Vcc max)
=-4.0 ma Vcc min)
=4.0 ma Vcc max)
Max
V
0.32
Industrial
Military
Units
3.76
V
V
0.37
2.3
V
V
II
CMOS thresholds (@ V cc Max)
5
mA
TTL thresholds (@ Vcc Max)
12
mA
500
~
+10
~
10
15
pF
pF
ICCPD
Power-down supply current (VCC(MAX) @ T MAX)
IlL
Input Leakage Current
C IN
Input capacitance (sample tested) All Pins except XTL 1 and XTL2
XTL 1 and XTL2
-10
2-211
XC2000 Logic Cell Array Families
CLB Switching Characteristic Guidelines
INPUT (A,B,C,D)
x
x
1--0 TILO~
xx:
OUTPUT (X,Y)
(COMBINATORIAL)
® Too
OUTPUT (X,Y)
(TRANSPARENT LATCH)
I-- ®
x;ct
o
TICK
TCKI--
CLOCK(K)
®
1+--0 TICC
CLOCK (C)
I
1-0 TICI
~}TCII-
-
CLOCK (G)
G)
TCKO - - - "
@
Tcco---"
@
TCIO ------
)OC
OUTPUT (VIA FF)
-f
SET/RESET DIRECT (A,D)
I
SETIRESET DIRECT (F,G)
CLOCK (ANY SOURCE)
Tccl-----
f
TCH
___---JI:==-@
.,
@
TRIO
@
TRLO
~~L~_ _ _ __
1104 30
2·212
~XIUNX
CLB Switching Characteristic Guidelines (Continued)
Speed Grade
Description
Logic Input
to Output
K Clock
CClock
Logic Input
toG Clock
Symbol
-50
Min Max
-70
-100
Min Max
Min Max
Combinatorial
Transparent latch
Additional for
through F or G to out
1
2
To output
Logic-input setup
Logic-input hold
9
3
4
TCKO
TICK
TCKI
9
0
To output
Logic-input setup
Logic-input hold
10
5
6
Tcco
Tlcc
Tcci
8
0
To output
Logic-input setup
Logic-input hold
11
7
8
Tclo
TICI
TCII
4
5
12
13
TRIO
TRLO
TMRO
TRS
TRpw
9
9
7
7
6
6
FClK
50
70
100"
TCH
TCL
8
8
7
7
5"
5"
a
Set/Reset direct Input A or D to output x, y
Through F or G to output
Reset pad to output x, y
Separation of set/reset
Set/Reset pulse-width
Flip-flop Toggle
rate
a through F to flip-flop
Clock
Clock High
Clock Low
14
15
Units
TILO
TITO
15
20
10
14
8
10
ns
ns
TOLO
8
6
6
ns
7
6
0
ns
ns
ns
9
5
0
ns
ns
ns
15
10
7
0
19
13
6
0
27
20
22
28
25
13
ns
ns
ns
10
14
17
ns
ns
ns
ns
ns
2
3
3
4
16
21
20
Notes: 1. All switching characteristics apply to all valid combinations of process, temperature and supply with a nominal chip
power dissipation of 250 mW.
"
These parameters are for clock pulses generated within a CLB. For an externally generated pulse, derate these
parameters by 20%.
2-213
MHz
ns
ns
II
XC2000 Logic Cell Array Families
lOB Switching Guidelines
PAD
(PACKAGE PIN) _ _--II'-_ _--r_(IN_)--I '--_ _
OUTPUT SIGNAL
®
INPUT
(DIREcn
L
(I/OCWCK)
INPUT
(REGISTERED)
RESET
1104 31A
Speed Grade
Description
Symbol
-50
-70
-100
Min Max
Min Max
Min Max
Units
Pad
(package pin)
To input (direct)
1
TplD
I/O Clock
To input (storage)
To pad-input setup
To pad-input hold
Pulse width
Frequency
5
2
3
4
Tu
TpL
TLP
TLW
Output
To pad (output enabled)
8
Top
12
9
7
ns
Three-state
To pad begin hi-Z
To pad end hi-Z
9
10
TTHZ
TTON
20
20
15
15
11
13
ns
ns
RESET
To input (storage)
To input clock
6
TRI
TRC
17
ns
ns
7
8
6
15
11
8
6
0
0
7
70
9
50
20
ns
8
ns
ns
ns
ns
4
0
5*
100*
25
30
25
4
MHz
14
Note: Timing is measured at 0.5 Vee levels with 50 pF oLitputload.
*These parameters are for clock pulses generated within an LeA device. For an externally applied clock, derate these
parameters by 20%.
2-214
XC2000L Low-Voltage
Logic Cell Array Family
Preliminary Product Specification
Features
Description
• Part of the ZERO+ Family of 3.3 V FPGAs
The XC2000L family of FPGAs is optimized for operation
from a 3.3 V (nominal) supply. Aside from the electrical and
timing parameters listed in this data sheet, the XC2000L
family is in all respects identical with the XC2000 family.
• Low-power, low-supply-voltage FPGA family with two
device types
- JEDEC-compliant 3.3 V version of the XC2000
LCA Family
- Logic densities from 1,000 to 1,500 gates
- Up to 74 user-definable I/Os
• Advanced, low power 0.8 11 CMOS static-memory
technology
- Very low quiescent current consumption, ~O !lA ,
25 times less than XC2000
- Operating power consumption 66% less than
previous generation 5 V FPGAs; 56% less than
XC2000
• Identical to the basic XC2000 in structure, pin out,
design methodology, and software tools
- 100% compatible with XC2000 bitstreams
• XC2000L-specific features
- Guaranteed over the 3.0 to 3.6 V Vcc range
- TIL-equivalent input and output levels
- 4 mA output sink and source current
- Advanced packaging using thin and very thin quad
flat packs
The operating power consumption of Xilinx FPGAs is
almost exclusively dynamic; it changes with the square of
the supply Voltage. For a given complexity and clock
speed, the XC2000L consumes, therefore, only 44% ofthe
power used by the equivalent XC2000 device. Consistent
with its use in battery-powered equipment, the XC2000L
family was designed for the lowest possible power-down
and quiescent current consumption.
Device
Logic
Capacity
(gates)
XC2064L
800 -1,000
XC2018L 1,200 - 1,500
User
110
CLBs
Max
Config.
bits
64
100
58
74
12,038
17,878
LCA logic functions and interconnections are determined
by data stored in internal static-memory cells. On-chip
logic provides for automatic loading of configuration data
at power-up. Program data can reside in an EEPROM,
EPROM or ROM on the circuit board or on a floppy disk or
hard disk. The program can be loaded in a number of
modes to accommodate various system requirements.
2-215
II
XC2000L Logic Cell Array Family
Xilinx maintains test specifications for each product as controlled documents. To insure the use of the most recently
released device performance parameters, please request a copy of the current test-specification revision.
Absolute Maximum Ratings
Units
Symbol
Description
Vcc
Supply voltage relative to GND
-0.5 to +7.0
V
VIN
Input voltage with respect to GND
-0.5 to V cc +0.5
V
V rs
Voltage applied to 3-state output
-0.5 to Vee +0.5
V
TSTG
Storage temperature (ambient)
-65 to +150
°C
TSOL
Maximum soldering temperature (10
+260
°C
Junction temperature plastic
+125
°C
Junction temperature ceramic
+150
°C
s
@
1/16 in.)
TJ
Note:
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These
are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed
under Recommended Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for
extended periods of time may affect device reliability.
Operating Conditions
Symbol
Description
(Commercial O°C to +70°C)
Min
Max
Units
3.0
3.6
V
Vee
Supply voltage relative to GND
VIH
High-level input voltage
2.0
V IL
Low-level input voltage
0.3
TIN
Input signal transition time
V cc+0.3
0.8
250
V
V
ns
Although the present (1993) devices operate over the full supply voltage range from 3.0 to 5.25 V, Xilinx reserves the
right to restrict operation to the 3.0 to 3.6 V range later, when smaller device geometries might preclude operation at 5 V.
2-216
DC Characteristics Over Operating Conditions
Symbol
<
Description
Min
=-2.0 rnA Vcc min)
Max Units
V
V OH
High-level output voltage (@ IOH
2.4
VOL
Low-level output voltage (@ IOL
V OH
High-level output voltage (@ -100).IA V cc min)
VOL
Low-level output voltage (@ 100).IA V cc min)
VCCPD
Power-down supply voltage (PWRDWN must be Low)
Icco
Quiescent operating power supply current<
20
).IA
ICCPD
Power-down supply current (VCC(MAX) @ T MAX)
10
).IA
IlL
Input Leakage Current, all 1/0 pins in parallel
+10
).IA
C IN
Input capacitance (sample tested) All Pins except XTL 1 and XTL2
10
pF
XTL 1 and XTL2
15
pF
=4.0 rnA Vcc max)
0.4
V
Vcc-0 .2
0.2
2.3
-10
V
V
V
With no output current loads, no active input or Longline pull-up resistors. all package pins at V cc or GND. and the
LeA device configured with a MakeBits tie option. Icco is in addition to Iccpo'
2-217
III
XC2000L Logic Cell Array Family
CLB Switching Characteristic Guidelines
INPUT (A,B,C,D)
x
x
-CDTILO~
XXX
OUTPUT (X,V)
(COMBINATORIAL)
® TITO
OUTPUT (X,V)
(TRANSPARENT LATCH)
- 0 TICK
xx*
8)
TCKI -
CLOCK(K)
- ® TICC
Tccl -
@
CLOCK (C)
-0 Tlcl
CLOCK (G)
@TclI - G ) TCKO @Tcco@Tclo-
XX)
OUTPUT (VIA FF)
-f
SET/RESET DIRECT (A,D)
I
SET/RESET DIRECT (F,G)
CLOCK (ANV SOURCE)
l:
___---11::=
l- @
@
TRIO
@
TRLC
TCH
1104 30
2-218
CLB Switching Characteristic Guidelines (Continued)
Speed Grade
Description
Symbol
Combinatorial
Transparent latch
Additional for Q
through F or G to out
1
2
K Clock
To output
Logic-input setup
Logic-input hold
9
3
4
C Clock
To output
Logic-input setup
Logic-input hold
10
5
To output
Logic-input setup
Logic-input hold
11
Set/Reset direct
Input A or D to output x, y
Through F or G to output
Reset pad to output x, y
Separation of set/reset
Set/Reset pulse-width
12
13
Flip-flop Toggle
rate
Q through F to flip-flop
Clock
Clock High
Clock Low
Logic Input
to Output
Logic Input
to G Clock
6
7
8
14
15
Units
T llO
TITO
ns
ns
ToLO
ns
TcKO
TICK
TCKI
ns
ns
ns
Tcco
Tlcc
Tcci
ns
ns
ns
Tclo
T ici
TCII
ns
ns
ns
TRIO
TRLO
TMRO
TRS .:..
TRPW
ns
ns
ns
ns
ns
FClK
MHz
TCH
TCl
ns
ns
Notes: 1. All switching characteristics apply to all valid combinations of process, temperature and supply with a nominal chip
power dissipation of 250 mW.
2-219
II
XC2000L Logic Cell Array Family
lOB Switching Guidelines
PAD
(PACKAGE PIN)
=m
(IN)
(OUT)
)()Q
@TOp:J
X
OUTPUT SIGNAL
0- TTHZ I--
~ G)TPID-1
INPUT
(DIRECT)
XXX
3-STA
®TpL
@)TLP
L
(110 CLOCK)
1
--+
INPUT
(REGISTERED)
r---
J
-levTLW
+
®TLlrr=
\V
XXX
f4- ® TRI •
o
TRc
~
RESET
1104 311\
Speed Grade
Description
Pad
(package pin)
To input (direct)
liD Clock
To input (storage)
To pad-input setup
To pad-input hold
Pulse width
Frequency
Output
To pad (output enabled)
Three-state
RESET
Symbol
Units
TplD
ns
5
2
3
4
Tu
TpL
TLP
TLW
ns
ns
ns
ns
MHz
8
Top
ns
To pad begin hi-Z
To pad end hi-Z
9
10
TTHZ
TTON
ns
ns
To input (storage)
To input clock
6
TRI
TRC
ns
ns
7
Note: Timing is measured at 0.5 Vee levels with 50 pF output load ..
2-220
For a detailed description of the device architecture, see pages 2-179 through 2-187.
For a detailed description of the configuration modes and their timing, see pages 2-192 through 2-198.
For package physical dimensions, see Section 4.
Ordering Information
=r-J r~'_m,"re ~~,
XC2064-70PC44C
Example:
Device Type
Toggle Rate
Number of Pins
Package Type
II
Component Availability
C
M
=Commercial =0° to +70 C
=Mil Temp =_55 to +125° C
I = Industrial =-40° to +850 C
0
B = MIL-STO-883C Class B
0
Parentheses indicate future product plans
2-221
XC2000L Logic Cell Array Family
2-222
~
XC17000 Family of Serial Configuration PROMs
Table of Contents
Overview ............................................................... 2-224
Component Availability ......................................... 2-224
XC17000 Family of Serial Configuration PROMs. 2-225
Pin Assignments ............................................... 2-226
Number of Configuration Bits
for all Xilinx FPGAs ...................................... 2-226
Serial PROM Pinouts ........................................ 2-226
Controlling Serial PROMs ................................. 2-227
LCA Master Serial Mode Summary .................. 2-227
Standby Mode ................................................... 2-229
Programming .................................................... 2-229
XC1718D, XC1736D, XC1765D, XC17128
AbssoluteMaximum Ratings ......................... 2-230
Operating Conditions ........................................ 2-230
DC Characteristics ............................................ 2-230
XC1718L and XC1765L
Absolute Maximum Ratings .......................... 2-231
Operating Conditions ........................................ 2-231
DC Characteristics ............................................ 2-231
AC Characteristics ............................................ 2-232
Ordering Information ......................................... 2-233
2-223
I
Overview
Serial Configuration PROMs
Xilinx offers several pin- and function-compatible serial
one-time-programmable PROMs in plastic and ceramic
packages.
In early 1993, Xilinx also introduced the L-series of serial
PROMs, the XC1718L and XC1765L. These devices
operate at the new industry-standard low supply voltage of
3.3 V (3.0 to 3.6 V).
Component Availability
The original family consists of the XC1736A, XC1765
followed by the XC17128. (The numbers following the 17
indicate the capacity in kilobits.)
8
PINS
PLAST. CERAM.
DIP
DIP
TYPE
The XC1736A is the only serial PROM that lacks the
programmable Reset polarity option, and the XC17128 is
the only serial PROM that can be clocked atthe full 10 MHz
required by the XC4000 in fast configuration mode. All
other serial PROMs can be clocked at up to 5 MHz.
CODE
XC1718D
XC1736D
XC1765D
XC1718L
XC1765L
XC17128
In early 1993, Xilinx introduced the D-series of serial
PROMs, the XC1718D, XC1736D, and XC1765D, all with
programmable Reset polarity, improved ESD protection,
and all with max 5 MHz clock frequency. These devices are
programmed with a lower voltage and a different programming algorithm than the older parts. The user needs the
appropriate update from the programmer vendor. These
devices will become the mainstream serial PROMs, and,
beyond the traditional packages, they are also available in
the space-saving S08 package.
20
PLAST.
SOIC
PLAST.
PLCC
PD8
008
S08
PC20
CI
!t';!MEM
i M i
i MR i
CI
CI
CI
CI
CI
CI
CI
CI
C = Commercial = Or:> to +70° C
M Mil Temp -55' to +125' C
I = Industrial = -40° to +85° C
R = High Rei = -55' C to +125' C
"17128 C = 0' to +70' C or -40' to +85' C
=
2-224
=
XC17000 Family of
Serial Configuration PROMs
Preliminary Product Specifications
Features
Description
• Extended family of one-time programmable (OTP) bitserial read-only memories used for storing the configuration bitstreams of Xilinx FPGAs
The XC17000 family of serial configuration PROMs (SCPs)
provides an easy-to-use, cost-effective method for storing
Xilinx FPGA configuration bitstreams.
• On-chip address counter, incremented by each rising
edge on the clock input
When the FPGA is in master serial mode, it generates a
configuration clock that drives the SCPo A short access time
after the rising clock edge, data appears on the SCP DATA
output pin that is connected to the FPGA DIN pin. The
FPGA generates the appropriate number of clock pulses to
complete the configuration. Once configured, it disables
the SCPo When the FPGA is in slave mode, the SCP and
the FPGA must both be clocked by an incoming signal.
• Simple interface to the FPGA requires only one user VO
pin
• Cascadable for storing longer or multiple bitstreams
• Programmable reset polarity (active High or active Low)
for compatibility with different FPGA solutions, (the older
XC1736A has active-High reset only)
Multiple devices can be concatenated by using the CEO
output to drive the CE input of the following device. The
clock inputs and the DATA outputs of all SCPs in this chain
are interconnected. All devices are compatible and can be
cascaded with other members of the family.
• XC17128 supports XC4000 fast configuration mode
(10 MHz)
• Low-power CMOS EPROM process
• Available in 5 V and 3.3 V versions
• Available in plastic and ceramic packages, and commercial, industrial and military temperature ranges
• Space efficient 8-pin DIP, 8-pin SOIC or 20-pin surfacemount packages.
For device programming, the XACT development system
compiles the LCA design file into a standard Hex format,
which is then transferred to the programmer.
• Programming support by leading programmer
manufacturers.
vee
vpp
GND
CLKD-i-----L.J
EPROM
Cell
Matrix
Oulput
DATA
X3185
Figure 1. Simplified Block Diagram (does not show programming circuit)
2-225
II
XC17000 Serial Configuration PROM
Pin Assignments
Serial PROM Pinouts
Pin Name
DATA
Data output, 3-stated when either CE or OE are inactive.
During programming, the DATA pin is I/O. Note that OE can .
be programmed to be either active High or active low.
8-Pin
20-Pin
DATA
1
2
ClK
2
4
RESET/OE (OEIRESET)
3
6
ClK
Each rising edge on the ClK input increments the internal
address counter, if both CE and OE are active. Note that
OE can be programmed to be either active High or active
low.
CE
4
8
GND
5
10
RESET/OE
When High, this input holds the address counter reset and
3-states the DATA output. The polarity of this input pin is
programmable as either RESET/OE or OEiRESET. To
avoid confusion, this document describes the pin as
RESET/OE, although the opposite polarity is possible on
all devices except the older XC1736A.
CEO
6
14
V pp
7
17
Vee
8
20
Number of Configuration Bits, Including Header
for all Xilinx FPGAs
CE
When High, this pin disables the internal address counter,
3-states the DATA output, and forces the device into lowIce standby mode.
CEO
Chip Enable output, to be connected to the CE input of the
next SCP in the daisy chain. This output is low when the
CE and OE inputs are both active AND the internal address
counter has been incremented beyond its Terminal Count
(TC) value. In other words: when the PROM has been read,
CEO will follow CE as long as OE is active. When OE goes
inactive, CEO stays High until the PROM is reset. Note that
OE can be programmed to be either active High or active
low.
Device
Configuration Bits
XC2064
12,038
XC2018
17,878
XC3020/3120
14,819
XC3030/3130
22,216
XC304213142
30,824
XC3064/3164
46,104
XC3090/3190
64,200
XC3195
94,984
XC4002A
31,668
XC4003A
45,676
XC4003H
53,967
XC4004A
62,244
XC4005A
81,372
XC4005/4005H
95,000
Vpp
Programming voltage. No overshoot above the specified
max voltage is permitted on this pin. For normal read operation, this pin mustbe connected to Vee. Failure to do so
may lead to unpredictable, temperature-dependent operation and severe problems in circuit debugging. Do not
leave Vppfloatingl
Vcc
Positive supply pin.
GND
Ground pin
2-226
XC4006
119,832
XC4008
147,544
XC4010
178,136
XC4013
247,960
Controlling Serial PROMS
Most connections between the LCA device and the Serial
PROM are simple and self-explanatory.
o
The DATA output of the PROM drives DIN of the LCA
devices.
o
The master LCA CCLK output drives the CLK input of
the Serial PROM.
o
The CEO output of any Serial PROM can be used to
drive the CE input of the next serial PROM in a cascade
chain of PROMs.
o
Vpp muslbe connected to Vcc. Leaving Vpp open can
lead to unreliable, temperature-dependent operation.
There are, however, two different ways to use the inputs
CE and OE.
1. The LCA Dip or LDC output drives both CE and OE in
parallel. This is the simplest connection, but it fails if a
user applies RESET during the LCA configuration process. The LCA device aborts the configuration and then
restarts a new configuration, as intended, but the Serial
PROM does not reset its address counter, since it never
saw a High level on its OE input. The new configuration,
therefore, reads the remaining data in the PROM and
interprets it as preamble, length count etc. Since the
LCA device is the master, it issues the necessary number of CCLK pulses, up to 16 million (224) and Dip goes
High. However, the LCA configuration will be completely
wrong, with potential contentions inside the LCA device
and on its output pins. This method must, therefore,
never be used when there is any chance of external
reset during configuration.
2. The LCA Dip or LDC output drives only the CE input of
the Serial PROM while its OE input is driven by the LCA
RESET input. This connection works under all normal
circumstances, even when the user aborts a configuration before Dip has gone High. The Low level on the OE
input during reset clears the PROM internal address
pointer, so that the reconfiguration starts at the beginning. The reset polarity should be inverted for this mode
to be used. It is strongly recommlilnded that this method,
shown in Figure 2, be used when-ever possible.
LCA Master Serial Mode Summary
The 1/0 and logic functions of the Logic Cell Array and their
associated interconnections are established by a configuration program. The program is loaded either automatically
upon power up, or on command, depending on the state of
the three LCA mode pins. In Master Mode, the Logic Cell
Array automatically loads the configuration program from
an external memory. The Serial Configuration PROM has
been designed for compatibility with the Master Serial
Mode.
Upon power-up or reconfiguration, an LCA device enters
the Master Serial Mode whenever all three of the LCA
mode-select pins are Low (MO=O, M1=O, M2=O). Data is
read from the Serial Configuration PROM sequentially on a
single data line. Synchronization is provided by the rising
edge of the temporary signal CCLK, which is generated
during configuration.
Master Serial Mode provides a simple configuration interface. Only a serial data line and two control lines are
required to configure an LCA device. Data from the Serial
Configuration PROM is read sequentially, accessed via the
internal address and bit counters which are incremented on
every valid rising edge of CCLK.
If the user-programmable, dual-function DIN pin on the
LCA device is used only for configuration, it must still be
held at a defined level during normal operation. The
XC3000 and XC4000 families take care of this automatically with an on-chip default pull-up resistor. With XC2000family devices, the user must either configure DIN as an
active output, or provide a defined level, e.g., by using an
external pull-up resistor, if DIN is configured as an input.
Programming the LCA With Counters Unchanged
Upon Completion
When multiple LCA-configurations for a single LCA are
stored in a Serial Configuration PROM, the OE pin should
be tied Low as shown in Figure 3. Upon power-up, the
internal address counters are reset and configuration
begins with the first program stored in memory. Since the
OE pin is held Low, the address counters are left
unchanged after configuration is complete. Therefore, to
reprogram the LCA with another program, the DIP line is
pulled Low and configuration begins at the last value of the
address counters.
Cascading Serial Configuration PROMs
For multiple LCAs configured as a daisy-chain, or for future
LCAs requiring larger configuration memories, cascaded
SCPs provide additional memory. After the last bit from the
first SCP is read, the next clock signal to the SCP asserts
its CEO output Low and disables its DATA line. The second
SCP recognizes the Low level on its CE input and enables
its DATA output. See Figure 2.
After configuration is complete, the address counters of all
cascaded SCPs are reset if the LCA RESET pin goes Low,
assuming the SCP reset polarity option has been inverted.
If the address counters are not to be reset upon completion, then the RESETIOE inputs can be tied to ground, as
shown in Figure 3. To reprogram the LCA device with
another program, the DIP line goes Low and configuration
begins where the address counters had stopped. In this
case, avoid contention between DATA and the configured
1/0 use of DIN.
Extremely large, cascaded memories in some systems
may require additional logic if the rippled chip enable is too
slow to activate successive SCPs.
2-227
I
XC17000 Serial Configuration PROM
* H Readback is
Acliva1ed, a
5-t-~~-r---1)-~_1
from FastDecode
Units
IIFCIIXt-r--,
1 of 6 Comparator Bits
O/FCO
To
UIM
Load
DISABLE JAM
(from
(from
UIM)
UIM)
(from
UIM)
Figure 4b. FastCompare Schematic
3-9
Output
Selector
FOE
X1B40
XC7236IXC7236A Programmable Logic Device
The FastCompare unit contains two fast programmable 6bit comparators with a common set of six inputs (FCI),
separate from the I=DI inputs. Each comparator compares
the data on the inputs against a pattern stored in its six
latches and drives a designated chip output (FCO). Data
can be loaded into these latches either from the
FastCompare data inputs, or can be preloaded during chip
configuration (Power-up or Reset). Each comparator is
programmable with Don't Care bits and can be conditioned
with the result of one or more of the FastDecode FDO
outputs.
<
.§.
E
~
~
Programming and Using the XC7236/A
The features and capabilities described above are used by
the Xilinx development software to program the device
according to the specification given either through schematic entry, orthrough a behavioral description expressed
in Boolean equations.
The user can specify a security bit that prevents any
reading of the programming bit map after the device has
been programmed and verified.
The device is programmed in a manner similar to an
EPROM (ultra-violet light erasable read-only memory)
using the Intel Hex format. Programming support is available from a number of programmer manufacturers. The
UIM connections and Function Block AND-array connections are made directly by non-volatile EPROM cells.
Other control bits are read out of the EPROM array and
stored into latches just after power-up. This method,
common among EPLD devices, requires either a very fast
100
75
>C.
c.
50
:;,
en
------
125
()
--::: ::::: -:::: :::::
~
-
TA = ·55'C
~ TA = 25'C
-::::::::~ ~
TA = 125'C
25
0
The comparison can be disabled (forced false) and the
polarity of the match response can be chosen.
Since this compare circuitry bypasses the UIM and Macrocells, it is very fast and can also be used as high-speed
address decoder.
150
5
10
15
20
25
30
Frequency (MHz)
35
40
X3255
Typical Power Requirements for XC7236 Configured as
Eight 4-bit Counters (V cc =+5.0 V, V1N =0 or 5 V, all
outputs open)
v cc rise time «5 Ils) or the application of a master-reset
signal delayed at least until Vcc has reached the required
operating voltage. The latter can be achieved using a
simple capacitor and pull-up resistor on the MR pin (the RC
product should be larger than twice the Vee rise time). The
power-up or reset signal initiates a self-timed configuration
period lasting about 350 Ils (tRESET)' during which all
device outputs remain disabled and programmed preload
state values are loaded into the Macrocell registers.
Unused input and I/O pins should be tied to ground or Vcc
or some valid logic level. This is common practice for all
CMOS devices to avoid dissipating excess current
through the input-pad circuitry.
The recommended decoupling capacitance on the three
V cc pins should total 1 IlF using high-speed (tantalum or
ceramic) capacitors.
3-10
--------
----
Absolute Maximum Ratings
Symbol Parameter
Value
Units
Vee
Supply voltage relative to GND
-0.5 to 7.0
V
V IN
Input voltage with respect to GND
-0.5 to 7.0
V
VTS
Voltage applied to 3-state output
-0.5 to 7.0
V
Vpp
Programming voltage
+14
V
T STG
Storage temperature
-65 to + 150
°C
TSOL
Maximum soldering temperature (10 s @ 1/16 in. = 1.5 mm)
+260
°C
Note:
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These are stress ratings only. and functional operation of the device at these or any other conditions beyond
those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for
extended periods of time may affect device reliability.
Operating Conditions
Symbol
Parameter
e
Min
Max
Units
4.75
5.25
V
4.5
5.5
V
VeelNT
Supply voltage relative to GND
Commercial
Veelo
Supply voltage relative to GND
Industrial
Veelo
I/O supply voltage -3.3 V
3.0
3.6
V
V IL
Low-level input voltage
0
0.8
V
V IH
High-level input voltage
2.0
Vo
Output voltage
0
O°C to 70 0
-40°C to 85°C
Vee+ 0.3
V
Veelo
V
DC Characteristics Over Operating Conditions
Symbol
Parameter
Test Conditions
Min
5 V TTL high-level output voltage
I/O = -4.0 mA
Vee = Min
2.4
V
3.3 V high-level output
1/0=-3.2 mA
Vee = Min
2.4
V
5 V low-level output voltage
1/0= 12 mA
Vee = Min
0.5
V
3.3 V low-level output voltage
1/0=10mA
Vee = Min
0.4
V
IlL
Input leakage current
Vee = Max
V IN = GND or Veelo
±10
~
loz
Output High-Z leakage current
Vee = Max
Vo= GND or Veelo
±10
~
CIN
Input capacitance (sample tested)
VIN=GND
f =1.0 MHz
10
pF
VOH
VOL
3-11
Max
Units
I
XC72361XC7236A Programmable Logic Device
AC Timing Requirements
XC7236
Speed Grade
Description
XC7236A
-25
-30
-20
Units
-16
Fig. Symbol Min Max Min Max Min Max
Min Max
Sequential toggle frequency
(with feedback) using FastCLK
5
fCYC
(Note 1)
0
33
0
40
0
50
0
60 MHz
Sequential toggle frequency
(with feedback) using a Product-Term clock
5
fCYC1
(Note 1)
0
33
0
40
0
50
0
60 MHz
Macrocell toggle frequency
using local feedback and FastCLK
fCYC4
(Note 5)
0
42
0
50
0
50
0
60 MHz
Macrocell register transmission frequency
(without feedback) using FastCLK
fCLK
(Nole5)
0
36
0
45
0
50
0
60
Macrocell register transmission frequency
(without feedback) using a Product-Term clock
fClKl
(Note 5)
0
36
0
42
0
50
0
60 MHz
Input register transmission frequency
(without feedback) using FastCLK
fCLK2
(Note 5)
0
42
0
50
0
50
0
60 MHz
25
0
33
0
40
0
60 MHz
MHz
Input register to Macrocell register pipeline
freq. using FastCLK
6
fClK3
(Note 1)
0
FastCLK Pulse width (High/Low)
10
\y
12
10
8
6
ns
Product-Term clock pulse width (active/inactive)
10
\Yl
14
12
9
7
ns
Input to Macrocell register set-up time
before FastCLK
8
tsu
35
29
24
18
ns
Input to Macrocell register hold time
after FastCLK
8
tH
-7
-7
-4
-4
ns
Input to Macrocell register set-up time
before Product-Term clock
7
tSUl
(Note 1)
19
16
14
10
ns
Input to Macrocell register hold time
after Product-Term clock
7
tHl
0
0
0
0
ns
Input register/latch set-up time before FastCLK
9
tSU2
10
8
8
6
ns
Input registerllatch hold time
after FastCLK
9
tH2
0
0
0
0
ns
FastCompare input set-up time
before latch-enable input
11
tSU3
4
2
2
2
ns
FastCompare input hold time
after latch-enable input
11
tH3
18
14
14
12
ns
FastCompare input hold time
after comparator jam asserted
11
tH4
30
25
25
22
ns
Fastlnput to Macrocell register set-up time
before FastCLK
19U5
26
20
18
15
ns
Fastlnput to Macroceli register hold time
after FastCLK
~5
0
0
0
0
ns
SeVreset pulse width (active)
10
\YA
15
12
12
10
ns
SeVreset input recovery set-up time
before FastCLK
10
tRA
36
30
25
20
ns
3-12
~XIUNX
AC Timing Requirements (Continued)
XC7236A
XC7236
Speed Grade
-25
-30
-20
-16
Description
Fig. Symbol Min Max Min Max
Min Max
Min Max Units
SeVreset input hold time after FastCLK
10
tHA
-5
-5
0
0
ns
SeVreset input recovery time
10
tRAl
1B
15
15
12
ns
before P-Term clock
SeVreset input hold time after P-Term clock
10
SeVreset input hold time after reseVset inactive
FastCompare latch-enable pulse width
10
tHAl
12
9
9
B
ns
t HRS
12
10
10
8
ns
lwc
22
16
16
12
ns
Propagation Delays
XC7236
Speed Grade
Description
XC7236A
-25
-30
-20
Fig. Symbol Min Max Min Max
Min Max
FastCLK input to registered output delay
10
tco
5
17
5
14
3
tCOl
10
36
10
30
tAO
10
48
10
40
tpo
10
48
10
P-Term clock input to registered output delay
10
SeVreset input to registered output delay
10
Input to nonregistered output delay
10
-16
Min Max Units
13
3
10
ns
5
24
5
20
ns
5
32
5
25
ns
40
5
32
5
25
ns
(Note 1)
FastCompare or FastDecode input to
FastCompare output
11
tpoc
5
26
5
23
3
23
3
20
ns
FastCompare DISABLE or JAM input to
FastCompare output
11
tpDCl
5
30
5
25
3
24
3
22
ns
tpOC3
5
18
5
15
3
15
3
14
ns
FastDecode data input to FastDecode
output delay
Input to output enable
10
tOE
10
37
10
32
5
25
5
20
ns
Input to output disable
10
100
10
37
10
32
5
25
5
20
ns
Fastlnput to non-registered Macrocell
output delay
tpos
10
39
10
31
5
25
5
20
ns
Fastlnput to Qutput enabled
tOES
5
28
5
23
3
20
3
15
ns
Fastlnput to output disabled
toos
5
28
5
23
3
20
3
15
ns
FOE inp!Jt to output enabl.ed
t FOE
5
18
5
15
3
14
3
12
ns
FOE input to output disabled
t FOO
5
18
5
15
3
14
3
12
ns
3-13
I
XC72361XC7236A Programmable Logic Device
Incremental Parameters
XC7236
Speed Grade
XC7236A
-25
-30
-20
-16
Description
Fig Symbol Min Max Min Max Min Max
Arithmetic carry delay
between adjacent Macrocells
12
tpDT1
(Note 2)
1.5
1.2
1.2
1
ns
Arithmetic carry delay
through 9 adjacent MacroceIls in a Function Block
12
t pOTS
(Note 2)
8
6
5
3
ns
Arithmetic carry delay through 10 Macrocells
from Macrocell #n to MacroceIl #n in next F Block
12
tpDT9
(Note 2)
12
9
6
4
ns
Incremental delay from UIM-input
(for P-Term clock) to registered Macrocell
feedback
13
tCOFt
14
12
7
5
ns
Incremental delay from FastCLK net
to latched/registered UIM-input
13
tCOF2
(Note 3)
1
1
1
1
ns
Incremental delay from UIM-input
to nonregistered Macrocell feedback
13
tpDF
(Notet)
26
22
14
10
ns
Incremental delay from UIM-input (seVreset)
to registered Macrocell feedback
13
tAOF
26
22
14
10
ns
Incremental delay from UIM-input
(used as output-enable/disable)
to Macroeell feedback
13
tOEF'
tODF
15
14
7
5
ns
Propagation delay
through unregistered Input pad (to UIM)
plus output pad driver (from Maerocell)
13
22
18
18
15
ns
tiN +
tOUT
(Note 4)
Min Max Units
Power-up/Reset Timing Parameters
Description
Symbol Min
Master Reset input Low pulse width
Vcc rise time (if MR not used for power-up)
IwMR
trVee
(NoteS)
Configuration completion time (to outputs operational)
tRESET
Typ
Max
100
Units
ns
350
5
IJ.S
1000
IJ.S
Notes: 1. Specifications account for logic paths which use the maximum number of available product terms and the AlU.
2. Arithmetic carry delays are measured as the increase in required set-up time to adjacent Macrocell(s) for an adder with
registered outputs.
3. Parameter k is derived as the difference between the clock period for pipelining input-to-Macrocell registers (1IfCLK3)
and the non-registered input set-up time (tsu).
4. Parameter tiN represents the delay from an input or lID pin to a UIM-input (or from a FastCLK pin to the Fast ClK net);
hIT represents the delay from a Macrocelf output (feedback point) to an output or lID pin. Only the sum of ~N + loor can
tie derived from measurements, e.g., tiN + tOUT = tSl) + tco - lIfevc ·
5. Not tested but derived from appropriate pulse-widths, set-up time and hold-time measurements.
6. Due to the synchronous operation of the power-up reset and the wide range of ways Vcc can rise to its steady state, Vcc
rise must be monotonic. Following reset, the Clock, Reset and Set inputs must not be asserted until all applicable input
and feedback set-up times are met.
3-14
Timing and Delay Path Specifications
Figure 7 defines the set-up and hold times from the data
inputs to the product-term clock used by the output register.
Introduction to XC7236 Timing
Timing calculations and verification for the XC7236 are
straightforward. The delay path consists of three blocks
that can be connected in series.
Figure 8 defines the set-up and hold times from the data
inputs to the FastCLK used by the output register.
Figure 9 defines the set-up and hold times from the data
input to the FastCLK used in an input register .
• Input Buffer and associated latch or register
• Logic Resource (UIM, AND-array and Macrocell)
• Three-state Output Buffer
Figure 10 shows the waveforms for the Macrocell and
control paths.
All inputs have the same delay, regardless of fan-out or
location. All logic resources have the same delay, regardless of logic complexity, interconnect topology or location
on the chip. All outputs have the same delay. The achievable clock rate is, therefore, determined only by the input
method (direct, latched or registered) and the number of
times a signal passes through the combinatorial logic.
Figure 11 defines the FastCompare timing parameters.
Figure 12 defines the carry propagation delays between
Macrocells and between Function Blocks. The parameters
describe the delay from the CIN, D1 and D2 inputs of a
Macrocell ALU to the CIN input of the adjacent Macrocell
ALU. These delays must be added to the standard
Macrocell delay path {tpD or tsu)to determine the perfDrmance of an arithmetic function.
Timing and Delay Path Descriptions
Figure 5 defines the max clock frequency (with feedback).
Any Macrocell output can be fed back to the UIM as an
input for the next clock cycle. Figure 6 shows the relevant
delay path. The parameters fCYC and fCYC1 specify the
maximum operating frequency for FastCLK and productterm clock operation respectively.
Figure 13 defines the incremental parameters for the
standard Macroceillogic paths. These incremental parameters are used in conjunction with pin-to-pin parameters
when calculating compound logic path timing. Incremental
parameters are derived indirectly from other pin-to-pin
measurement.
Figure 6 specifies the max operating frequency {fcLK3)for
pipelined operation between the input registers and the
Macrocell registers, using FastCLK.
UIM
FUNCTION BLOCK
INPUT OR
I/O PIN
OUTPUT
OR I/O PIN
1/fCYC, 1/fCYC1
:~
FASTCLK OR
PRODUCT TERM CLOCK
MACROCELL REGISTER
OUTPUT
~
____~
~X~------------
Figure 5. Delay Path Specifications for fCYC and f CYCl
3-15
II
XC72361XC7236A Programmable Logic Device
UIM
FUNCTION BLOCK
INPUT OR
1/0 PIN
OUTPUT
OR 1/0 PIN
FASTCLK
PIN
FASTCLK
INPUT-PAD
REGISTER OUTPUT
Figure 6. Delay Path Specification for fCLK3
FUNCTION BLOCK
OUTPUT
OR 1/0 PIN
INPUT OR
110 PIN
OUTPUT
DRIVER
INPUT OR
1/0 PIN
CLOCK
INPUT
_____---JI
tSU1
: tH1
~:,------------~.:~
INPUT OR
110 PIN
XXXX,-__
D_AT_A_
Figure 7. Delay Path Specification for tSU1 and tH1
3-16
XXXXX
.......
UIM
FUNCTION BLOCK
OUTPUT
OR I/O PIN
INPUT OR
I/O PIN
FASTCLK
PIN
1>0-----------------..
______----J(
FASTCLK
INPUT
tSU
I,
- IH
INPUT OR
I/O PIN
.:
--,XXXXXXXX
XXXX,,--_DA_TA
Figure 8. Delay Path Specification for tsu and tH
UIM
INPUT OR
I/O PIN
FA~T~LK D(Io----~
FASTCLK
PIN
_____....JI
1HZ,
:.,_---tS-U-2--~:.,~
INPUT OR
I/O PIN
X X X X.....,..-_DA_TA_.."....-IXXXXX
Figure 9. Delay Path Specification for t su2and tH2
3-17
I
XC72361XC7236A Programmable Logic Device
REGISTERED
INPUTS
LX
:
x=
X
tSU2*
tSU2 and tH2 are measured with respect to the high-going
edge of F~stCLK for regIstered inputs, and with respect to
the low-going edge of FastCLK for latched inputs.
Only the high going edge is used for clocking the macroceU registers.
tH2*: tSU2* tH2*:
:~~:~.++:
.
:~
tW
tW'
FASTCLK
=X_A_C_T_IV_E-/X
INPUT USED
AS CLOCK
~:(~.
:.tSU
: tSUt .
tHt
: t PO
~
RESETISET
DE-ASSERTED
tOE
tOD
:
:
~:
--~~~x~----~>~:--~<~--~-----------: tCO :
:
tAO
:~:
:~:
REGISTERED
OUTPUTS
~ :+._t:..:.R.:..:.A:..:.t--+~:
VALID ENABLE
:4
~TIVE
,..-----""'" ~======::t r-=='";'"
:~:~:~~""" ~---"'\
UNLATCHED
INPUTS
NON-REGISTERED
OUTPUTS
:. t HAt
tWA
:
INACTIVE
____~x.========>
<~
______~X~_______
Figure 10. Principal Pin-to-Pin Measurements
.
=x X
tWC
:.
INPUT USED AS
LATCH-ENABLE
~:
tWC
INACTtVE
ACTIVE
~
:
>C
tSU3:tH3
:~:~:
COMPARATOR
INPUTS
MATCHING INPUT
NON-MATCHING tNPUT
~ DISABLED
tNPUT USED AS
COMPARATOR DISABLE
INPUT USE D AS
COMPARATOR JAM
IPDC
tPDC
:+.-------..~: : - :
COMPARATOR
OUTPUT
===x
NO-MATCHX
Figure 11. FastCompare Timing Waveforms
3-18
NON-MATCHING
X. .
_E_N_A_B_LE_D_
··
·····
···
··
··
...
....
....
.
: tPDCt:
: tPDCt
MATCH X
NO-MATCH
:~~
,-----..:
IH4
INA3
:
:~~
.
ACTIVE
X~t_N_AC_T_'V_E_
tPDCt.
:+---+~
X:~~~~~~~M~A~TC~H~~~~~=X=
I
Figure 12. Arithmetic Timing Parameters
UIM
FUNCTION BLOCK
OUTPUT
OR I/O PIN
INPUT
OR I/O PIN
OUTPUT
OR I/O PIN
OUTPUT
OR 110 PIN
tl/\
FAST~~~
D-[>--::::::==========:...._
Figure 13. Incremental Timing Parameters
3-19
XC72361XC7236A Programmable Logic Device
44-Pin LCC Pinouts
In~ut
Pint
1
OutDut
Master Reset
Vpp
2
Input/FCI
3
4
Input/FCI
Input/FCI
MC2-1
5
6
7
Input/FCI
MC2-4
Input/FCI
MC2-5
Pint
23
Input
24
Input/FI
MC4-9fFCO
25
Input/FI
Input/FI
MC4-8fFCO
MC4-7
Input
MC4-6
26
27
GND
Output
V~~ln
28
29
Input
MC4-5
GND
8
Input/FCI
MC2-6
30
Input
MC4-4
9
10
FastCLKO
FastCLK1
MC2-7
MC2-8
31
32
Input
FastOE
MC4-3
MC4-2
11
12
FastCLK2
MC2-9
33
Input
13
Input
MC1-1
14
Input
MC1-2
15
16
17
Input
MC1-3
VCC10
Input
34
35
36
37
38
39
40
41
42
43
44
MC1-4
GND
18
Input
19
20
21
Input
Input/FI
Input/FI
22
FI = Fast Input
MC1-5
MC1-6
MC1-7
MC1-8
Input/FI
MC1-9
FCI = FastCompare input
FDI = FastDecode input
FCO
MC4-1fFDO
V CC1NT
Input/FI
MC3-9fFDO
Input/FI
MC3-8fFDO
Input/FI
MC3-7fFDO
Input/FDI
MC3-6
GND
Input/FDI
Input/FDI
MC3-5
Input/FDI
Input/FDI
Input/FDI
MC3-3
MC3-2
MC3-1
=FastCompare output
MC3-4
FDO
=FastDecode output
Ordering Information
Example:
P
XC7236-25PC44C
De_TypeT
Speed
Tempem,"m
Range
Number of Pins
Package Type
Package Options
PC44 44-Pin Plastic Leaded Chip Carrier
WC44 44-Pin Windowed Ceramic Leaded
Chip Carrier
Device Options
XC7236
XC7236A
Speed Options
-30
30 ns
-25
25 ns
20 ns
-20
-16
16 ns
(33
(40
(50
(60
MHz)
MHz)
MHz)
MHz)
sequential cycle time
sequential cycle time
sequential cycle time
sequential cycle time
Temperature Options
C
Commercial
I
Industrial
3-20
DOC to 70°C
-40°C to 85°C
XC7272A
Programmable Logic Device
Preliminary Product Specifications
Features
metic carry lines running directly between adjacent
Macrocells and Function Blocks support fast adders,
subtractors and comparators of any length up to 72 bits.
• Second-Generation High Density Programmable
Logic Device
• UV-erasable CMOS EPROM technology
• 72 Macrocells, grouped into eight Function Blocks,
interconnected by a programmable Universal
Interconnect Matrix
• Each Function Block contains a programmable ANDarray with 21 complementary inputs, providing up to
16 product terms per Macrocell
• Enhanced logic features:
- 2-input Arithmetic Logic Unit in each Macrocell
- Dedicated fast carry network between Macrocells
- Wide AND capability in the Universal Interconnect
Matrix
• Identical timing for all interconnect paths and for all
Macrocell logic paths
• 72 signal pins in the 84-pin packages:
421/0,12 inputs, 18 outputs
• Each input is programmable:
Direct, latched, or registered
• I/O-pin is usable as input when Macrocell is buried
• Two high-speed, low-skew global clock inputs
• 68-pin and 84-pin leaded chip carrier packages and
84-pin Pin-Grid-Array packages
This additional ALU in each Macrocell can generate any
combinatorial function of two sums of products, and it can
generate and propagate arithmetic-carry signals between
adjacent Macrocells and Functional Blocks.
The Universal Interconnect Matrix (UIM) facilitates unrestricted, fixed-delay interconnects from all device inputs
and Macrocell outputs to any Function Block AND-array
input. The UIM can also perform a logical AND across any
number of its incoming signals on the way to any Functional Block, adding another level of logic without additional delay. This supports bidirectionalloadable synchronous counters of any size up to 72 bits, operating at the
specified maximum device frequency
As a result of these logic enhancements, the XC7272A can
deliver high performance even in designs that combine
large numbers of product terms per output, or need more
layers of logic than AND-OR, or need a wide AND function
in some of the product terms, or perform wide arithmetic
functions.
Automated design mapping is supported by Xilinx development software based on design capture using thirdparty schematic entry tools, PLD compilers or direct textbased equation files. Design mapping is completed in a
few minutes on a PC.
General Description
The XC7272A is a second-generation High Density Programmable LogiC Device that combines the classical features of the PAL-like EPLD architecture with innovative
systems-oriented logic enhancements. This favors the
implementation of fast state machines, large synchronous
counters and fast arithmetic, as well as multi-level generalpurpose logic. Performance, measured in achievable system clock rate and critical delays, is not only predictable,
but independent of physical logiC mapping, interconnect
routing, and resource utilization. Performance, therefore,
remains invariant between design iterations. The propagation delay through interconnect and logic is constant for
any function implemented in anyone of the output
Macrocells.
Architectural Overview
Figure 1 shows the XC7272A structure. Eight Function
Blocks (FBs) are all interconnected by a central Universal
Interconnect Matrix (UIM). Each FB receives 21 signals
from the UIM and each FB produces nine signals back into
the UIM. All device inputs are also routed via the UIM to all
Function Blocks Each FB contains nine output Macrocells
(MCs) that draw from a programmable AND array driven
by the 21 signals from the UIM. Most Macrocells drive a 3state chip output, all feed back into the UIM.
The device also contains two dedicated Fast Comparators
(FCs) for address compare or decode functions. The
following pages describe the elements of this architecture
in detail.
The functional versatility of the traditional programmable
logic array architecture is enhanced through additional
gating and control functions available in an Arithmetic
Logic Unit (ALU) in each Macrocell. Dedicated fast arith-
3-21
I
XC7272A Programmable Logic Device
• = pin not present on 68 LCC
I~~~ d~~d~~~~
FC
FC
\\\~~~llJ-.lll 12
10
Arith.
! !
[10] 12
[9] 11
[8] 10
[7] 9
Carry
( FB4
I/O t--'
I/O t--'
FCLK/O
FCLK/O
MC4-1
MC4-2
MC4-3
MC4-4
MC4-5
M-f4-6
M-f4-7
FB51
A
N
0
0
~
A
R
R
[14]
[13]
[12]
[11]
[26]
[25]
[24]
(23]
[22]
[20]
(19]
(18]
[17]
32
31
30
29
28
26
25
24
23
[34]
[33]
[32]
(30]
(29]
[28]
(27]
42
41
40
39
38
36
35
34
33
,
~.
I/O
110
1/0
1/0
I/U
I/u
I/O
I/O
I/O
t--'
J---J----
f::+--'
1/0
---'
---'
110
1[0
I/O
I/U
M
FB6
A
N
A
N
0
0
+
A
R
R
~
A
---'
---'
---'
---'
---'
---'
0
21
IT'
FB8
0
r-;L
~
A
~1-8 y
MCl-9
\
Arithmetic Carry
Figure 1. XC7272A Architecture
3-22
0
0
0
0
0
J.d..
MC~
u
Mc6-1
~
i
MC7-9
MC7-8
MCn
MC7-6
MC7-5
MC7-4
MC7-3
MC7-2
MC7-1
I--:
I--:
1/0
1/0
I"--I"--I"---
1/0
1'----
I--:
I--:
['---
I/O
I/O
I/O
1/0
1/0
1/0
j
A MC8·9
N MC8-8
A
N
R
R
R
R
y
FB1
A
A
A
~2-8 y
~2-9
~
~
MC6-5
FB7
~
I/O
I"110
I"-cI'-t-- IIO/FCO
['--- I/OIFCO
R MC6-4
R MC6-3
A
N
~2-5 A
! !
~
y
MC2-6 R
R
MC2-7 A
MC1-l
MC1·2
MCl-3
MCl-4
MCl-5
MCl-6
MCl-7
A
J
84
68
LCC LCC
MC6-9
MC6-8
A
y
MC2-1 A
MC2-2 N
MC2-3 0
MC2-4
j
I/O
I/O
I/O
I/O
R
R
A
! FB2
J---J---J---J---J---J----
A
y
I
1 FB3
MC3-1
MC3-2
MC3-3
MC3-4
MC3-5
MC3-6
M-f3-7
MJd..3-8
MG3-9
4
U
A
~4-8 y
0
0
0
0
0
0
0
MC5-9
MC5-8
MC5-7
MC5-6
MC5-5
MC5-4
MC5-3
MC5-2
MC5-1
A
N
MC4-9
21
20
19
18
16
15
14
13
36
36
68
84
LCC LCC
22
0 MC8-7
MC8-6
A MC8-5
R MC8-4
R
MC8-3
A
y MC8-2
MC8-1
)
I"----::
I'--I'--I'--I'--f'---:
f'---:
f'--
"-----
110
1/0
1/0
1/0
I/O
1/0
1/0
I/O
I/O
74 [60]
75 [61]
76 (62]
77 (63]
65
66
67
68
70
71
72
73
[55]
[56]
[57]
[5.8]
54
55
56
57
58
60
61
62
63
[44]
[45]
(46]
[47]
[48]
(50]
[51]
[52]
[53]
..
44
45
46 [36]
47 [37]
48 [38]
50 [40]
51 [41]
52 (42]
53[43]
Function Blocks and Macrocells
The Arithmetic Logic Unit has two programmable modes:
In the logic mode, it is a 2-input function generator, a 4-bit
look-up table, that can be programmed to generate any
Boolean function of its two inputs. It can OR them, widening the OR function to max 16 inputs; it can AND them,
which means that one sum of products can be used to
mask the other; it can XOR them, toggling the flip-flop or
comparing the two sums of products. Either or both of the
sum-of-product inputs to the ALU can be inverted, and
either or both can be ignored. The ALU can implement one
additional layer of logic without any speed penalty.
The XC7272A contains 72 Macrocells with identical structure, grouped into eight Function Blocks of nine Macrocells
each. Each Macrocell is driven by product terms derived
from the 21 inputs from the UIM into the Function Block.
Five product terms are private to each Macrocell; an
additional 12 product terms are shared among the nine
Macrocells in any Function Block. One of the private
product terms is a dedicated clock for the flip-flop in the
Macrocell. See the description on page 3-24 for other
clocking options.
In the arithmetic mode, the ALU block can be programmed
to generate the arithmeti"'~=r.~~<
1~#t'rrS
Fn~M.
••
This dedicated carry chain overcomes the inherent speed
and density problems of the traditional EPLD architecture,
when trying to perform arithmetic functions like add, subtract, and magnitude compare.
,
-.::=r
l~~~~~ c~~~s
I
12
SHARABLE
5 PRIVATE
P-TERMS PER
MACROCELL
P-TERMS
PER
~UNCll0N
fS
o
~
MACRoe _LS
±i2 ;;;ci.1L
/
110 PAD
II
""",,,
I~
BLOCK
3
t01
9
,..
TO 8 MORE
MACROCELLS
rt
iJi.jjJ 2 i
• OE is forced high when p-t&rm is not used
102
f>
...,
<1 .•'•.••~ ••.••.' .••,..•••'
<\(i
lli21::
ARITHMETIC
CARRY-OUT TO
NEXT MACROCELL
FEEOBACK~
I
Figure 2. Function Block and Macrocell Schematic Diagram
3-23
~i•
~i,i
tfiU?
@::t;J
~~1111~ 52
I
XC7272A Programmable Logic Device
The ALU output drives the D input of the Macrocell flip-flop.
Each flip-flop has several programmable options:
One option is to eliminate the flip-flop by making it transparent, which makes the Q output identical with the D
input, independent of the clock.
If this option is not programmed, the flip-flop operates in
the conventional manner, triggered by the rising edge on
its clock input.
The clock source is programmable: It is either the dedicated product term mentioned above, or it is one of the two
global FastCLK signals that are distributed with short delay
and minimal skew over the whole chip.
The asynchr~)Oous Set and Reset (Clear) inputs override
the clocked operation. If both asynchronous inputs are
active simultaneously, Reset overrides Set. Upon powerup, each Macrocell flip-flop can be preloaded with either 0
or 1.
In addition to driving the chip output buffer, the Macrocell
output is also routed back as an input to the UIM. When the
Output Enable product term mentioned above is not active, this feedback line is forced High and thus disabled.
Outputs
Sixty of the 72 Macrocells drive chip outputs directly
through 3-state output buffers, each individually controlled
by the Output Enable product term mentioned above. For
bidirectional 1/0 pins, an additional programmable cell can
optionally disable the output permanently. The buried flipflop is then still available for internal feedback, and the pin
can still be used as a separate input
Inputs
Each signal input to the chip is programmable as either
direct, latched, or registered in a flip-flop. Latch and flipflop can be programmed with either of the two FastCLK
signals as latch enable or clock. The latch is transparent
when FastCLK is High, and the flip-flop clocks on the riSing
edge of FastCLK. Registered inputs allow high system
clock rates by pipelining the inputs before they incur the
combinatorial delay in the device, in cases where a pipeline cycle is acceptable.
The direct, latched, or registered inputs then drive the U1M.
There is no propagation-delay difference between pure
inputs and 1/0 inputs.
OUTPUT, 110
AND FCLKlO
PINS ONLY
Q
0
EN
INPUT AND
110 PINS ONLY
FAST
FAST'
CLOCK CLOCK
o
Figure 3. Input/Output Schematic Diagram
3-24
1
Universal Interconnect Matrix
A Macrocell feedback signal that is disabled by the output
enable product term represents a High input to the UIM.
Several such Macrocell outputs programmed onto the
same UIM output thus emulate a 3-state bus line. If oneof
the Macrocell outputs is enabled, the UIM output assumes
that same level.
The UIM receives 126 inputs: 72 from the 72 Macrocells,
42 from bidirectional I/O pins, and 12 from dedicated input
pins. Acting as an unrestricted crossbar switch, the UIM
generates 168 output signals, 21 to each Function Block.
Anyone of the 126 inputs can be programmed to be
connected to any number of the 168 outputs. The delay
through the array is constant, independent of the apparent
routing distance, the fan-out, fan-in, or routing complexity.
Routability is not an issue: Any UIM input can drive any UIM
output, even multiple outputs, and the delay is constant.
FastCompare
Two 12-bit wide fast identity (equality) comparators are
driven by the 12 dedicated FCI inputs, which also drive into
the UIM. These dedicated circuits compare the input data
againsttwo sets of 12-bit data, either loaded previously from
the same data inputs, or pre-programmed into the device.
When multiple inputs are programmed to be connected to
the same output, this output becomes the AND of the input
signals if the levels are interpreted as active High. By
choosing the appropriate signal inversion in the Macrocell
outputs and the Function Block AN D-array input, this ANDlogic can also be used to implement a NAND, OR, or NOR
function, thus offering an additional level of logic without
any speed penalty.
As a programming option, any bit can be excluded from the
comparison (disabled), the whole comparison can be disabled (forced false), and the polarity of the response can be
chosen. The FCO comparator outputs can substitute the
MC 5-1 and 5-2 outputs. Since this compare circuitry
bypasses the UIM and the AND/OR logic, it is very fast and
can also be used as a high-speed address decoder.
TO UIM
FASTCOMPARE
FROM
I~~T --"-H--,-+...o..,.-~-~--'\\-----'''"'--_~r---...
LOGIC
)t----;
11
M
o
R
TO I/O PAD
LOGIC
E
B
I
T
S
LOAD
(FROM UIM)
DISABLE
JAM
(FROM UIM) (FROM UIM)
Figure 4. FastCompare Schematic Diagram
3-25
FASTCOMPARE
OUTPUT
CONTROL
FROM
MACROCELL
OUTPUT
(MC5-1 OR MC5-2)
II
XC7272A Programmable Logic Device
Programming and Using the XC7272A
common among EPLD devices, requires either a very fast
Vcc rise time «5 Ils) or the application of a master-reset
signal delayed at least until V cc has reached the required
operating voltage. The latter can be achieved using a
simple capacitor and pull-up resistor on the M R pin (the RC
product should be larger than twice the V rise time). The
power-up or reset signal initiates a self-ti~~d configuration
period lasting about 350 Ils (tRESET), during which all
device outputs remain disabled and programmed preload
state values are loaded into the macrocell registers.
The features and capabilities described above are used by
the Xilinx development software to program the device
according to the specification given either through schematic entry, orthrough a behavioral description expressed
in Boolean equations.
The user can specify a security bit that prevents any
reading of the programming bit map after the device has
been programmed and verified.
Unused input and 1/0 pins should be tied to ground or Vcc
or some valid logic level. This is common practice for all
CMOS devices to avoid dissipating excess current
through the input-pad circuitry.
The device is programmed in a manner similar to an
EPROM (ultra-violet light erasable read-only memory)
using the Intel Hex format. Programming support is available from a number of programmer manufacturers. The
UIM connections and Function Block AND-array connections are made directly by non-volatile EPROM cells.
Other control bits are read out of the EPROM array and
stored into latches just after power-up. This method,
The recommended decoupling capacitance on the three
V cc pins should total 1 IlF using high-speed (tantalum or
ceramic) capacitors.
350
= -55°C
_I-- TA
TA = 25°C
300
--j....- ~
~
.s
"E
250
~
200
U
150
>a.
0..
100
:::l
~ t:::= ~ t:- ~
~
-
t:::=:::::t::-
TA= 125°C
~
:::l
C/)
50
0
5
10
15
20
25
30
35
40
Count Frequency (MHz)
Typical Power Requirements for XC7272A Configured as Sixteen 4-bit Counters
(V cc = +5.0 V, VIN = Vcc or GND, all outputs open)
3-26
X3254
Absolute Maximum Ratings
Units
Vee
Supply voltage relative to GND
-0.5 to 7.0
V
V IN
Input voltage with respect to GND
-0.5 to 7.0
V
VTS
Voltage applied to 3-state output
-0.5 to 7.0
V
Vpp
Programming voltage
+14
V
TSTG
Storage temperature
-65 to + 150
°C
TSOL
Maximum soldering temperature (10 S @ 1/16 in. = 1.5 mm)
+260
°C
Note:
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for
extended periods of time may affect device reliability.
II
Operating Conditions
Min
Vee
Supply voltage relative to GND
Commercial
Supply voltage relative to GND
Industrial
O°C to 70°C
-40°C to 85°C
Max
Units
4.75
5.25
V
4.5
5.5
V
Vee+ 0.3
V
0.8
V
V IH
High-level input voltage
2.0
V IL
Low-level input voltage
0
DC Characteristics Over Operating Conditions
Min
Max
Units
VOH
High-level output voltage @ 10H = -4 mA , Vee min
VOL
Low-level output voltage @ 10L = 8 rnA , Vee min
0.5
V
lec
Supply current while idle
250
mA
IlL
Input Leakage current
-10
+10
~
loz
Output High-Z leakage current
-100
+100
~
CIN
Input capacitance (sample tested)
10
pF
3-27
2.4
V
XC7272A Programmable Logic Device
AC Timing Requirements
-25
Speed Grade
Description
Fig
Sequential toggle frequency
(with feedback) using FastCLK
5
Sequential toggle frequency
(with feedback) using a Product-Term clock
5
-16
-20
Symbol
Min
Max
Min Max
Min Max Units
fCYC
0
40
0
50
0
60
MHz
fCYC1
1)
0
40
0
50
0
60
MHz
fCLK
0
59
0
60
0
60
MHz
0
50
0
50
0
60
MHz
0
67
0
67
0
67
MHz
fCLK3
1)
0
40
0
50
0
60
MHz
(Note t)
(Note
Macrocell register transmission frequency
(without feedback) using FastCLK
(NoteS)
Macrocell register transmission frequency
(without feedback) using a Product-Term clock
(NoteS)
Input register transmission frequency
(without feedback) using FastCLK
(NoteS)
fCLK1
fCLK2
Input register to Macrocell register pipeline frequency
using FastCLK
6
FastCLK
Low pulse width
10
~L
7.5
7.5
6
ns
FastCLK
High pulse width
10
~H
7.5
7.5
6
ns
Product-Term clock
pulse width (active/inactive)
10
tW1
10
9
7
ns
Input to Macrocell register set-up time
before FastCLK
8
tsu
24
19
15
ns
Input to Macrocell register hold time
after FastCLK
8
tH
-7
-4
-4
ns
Input to Macrocell register set-up time
before Product-Term clock
7
tsu1
1)
10
8
6
ns
Input to Macrocell register hold time
after Product-Term clock
7
tH1
0
0
0
ns
Input register/latch set-up time
before FastCLK
9
tsu2
8
8
6
ns
Input register/latch hold time
after FastCLK
9
tH2
0
0
0
ns
(Note
(Note
3-28
AC Timing Requirements (Continued)
Description
Fig. Symbol
-20
-25
Speed Grade
Min
Max
-16
Min Max
Min Max Units
FastCompare input set-up time
before latch-enable input
11
tSU3
2
2
2
ns
FastCompare input hold time
after latch-enable input
11
tH3
14
12
10
ns
FastCompare input hold time
after comparator jam asserted
11
tH4
25
22
18
ns
Set/reset pulse width
10
lwA
12
10
8
ns
Set/reset input recovery set-up time before FastCLK
10
tRA
20
20
16
ns
Set/reset input hold time after FastCLK
10
tHA
-5
-3
-3
ns
Set/reset input recovery time before P-Term clock
10
tRAl
6
5
4
ns
Set/reset input hold time after P-Term clock
10
tHAl
9
8
6
ns
t HRs
10
8
6
ns
lwc
16
14
12
ns
Set/reset input hold time after reset/set inactive
FastCompare latch-enable pulse width
10
Propagation Delays
-25
Speed Grade
Description
Fig. Symbol
-20
Min
Max
-16
Min Max
Min Max Units
FastCLK input to registered output delay
10
tco
5
16
3
14
3
12
ns
P-Term clock input to registered output delay
10
tCOl
10
30
6
25
6
21
ns
Set/reset input to registered output delay
10
tAO
13
40
8
32
8
25
ns
Input to nonregistered output delay
10
13
40
8
32
8
25
ns
tpD
(Note
1)
FastCompare input to MATCH output
11
t pDC
8
23
5
22
5
20
ns
FastCompare disable.input to MATCH output
11
tpDC1
8
25
5
22
5
20
ns
FastCompare jam input to MATCH output
11
t pDC2
8
25
5
22
5
20
ns
Input to output enable
10
tOE
11
32
7
25
7
22
ns
Input to output disable
10
too
11
32
7
25
7
22
ns
3-29
II
XC7272A Programmable Logic Device
Incremental Parameters
Speed Grade
Description
Fig
Symbol
-25
Min
-20
Max
-16
Min Max
Min Max Units
1.6
1.2
1
ns
t pOTS
2)
10
8
6
ns
t poT9
14
12
10
ns
tCOF
1
1
1
ns
tCOF1
15
12
10
ns
tCOF2
1
1
1
ns
tpOF
1)
25
19
14
ns
t AOF
25
19
14
ns
13 tOEF'tOOF
17
12
11
ns
13 t lN + tOUT
15
13
11
ns
Arithmelic carry delay
between adjacent Macrocells
12
Arithmetic carry delay
through 9 adjacent Macrocells in a Function Block
12
Arithmetic carry delay through 10 Macrocells
from Macrocell #n to Macrocell #n in next F Block
12
Incremental delay from FastCLK net
to registered output feedback
13
Incremental delay from UIM-input (for P-Term clock)
to registered Macrocell feedback
13
Incremental delay from FastCLK net
to latched/registered UIM-input
13
Incremental delay from UIM-input
to nonregistered Macrocell feedback
13
Incremental delay from UIM-input (set/reset)
to registered Macrocell feedback
13
Incremental delay from UIM-input
tpOT1
(Note 2)
(Note
(Note 2)
(Note 3)
(Note
(used as output-enable/disable)
to Macrocell feedback
Propagation delay
through unregistered Input pad (to UIM)
plus output pad driver (from Macrocell)
(Note 4)
Power-up/Reset Timing Parameters
Symbol
Min
Master Reset input Low pulse width
tWMR
100
V cc rise time (if MR not used for power-up)
t,vee
Description
Configuration completion time (to outputs operational)
tRESET
Typ
Max
Units
ns
350
5
!!S
1000
!!S
Notes 1. Specifications account for logic paths which use the maximum number of available product terms and the ALU.
2. Arithmetic carry delays are measured as the increase in required set-up time to adjacent Macrocell(s) for an adder with
registered outputs.
3. Parameter tCOF2 is derived as the difference between the clock period for pipelining input-to-Macrocell registers (1/fcLK3)
and the non-registered input set-up time (tsu )'
4. Parameter tiN represents the delay from an input or I/O pin to a UIM-input (or from a FastClK pin to the Fast ClK net);
tOUT represents the delay from a Macrocell output (feedback point) to an output or I/O pin. Only the sum of tiN + tOUT can
be derived from measurements, e.g., tiN + tOUT = tsu + 'co - 1/fCYc '
5. Not tested but .derived from appropriate pulse-widths, set-up time and hold-time measurements.
3-30
~XIUNX
Timing and Delay Path Specifications
Figure 7 defines the set-up and hold times from the data
inputs to the product-term clock used by the output register.
Introduction to XC7272A Timing
Timing calculations and verification for the XC7272A are
straightforward. The delay path consists of three blocks
that can be connected in series.
Figure 8 defines the set-up and hold times from the data
inputs to the FastCLK used by the output register.
Figure 9 defines the set-up and hold times from the data
input to the FastCLK used in an input register.
• Input Buffer and associated latch or register
• Logic Resource (UIM, AND-array and Macrocell)
• Three-state Output Buffer
Figure 10 shows the waveforms for the Macrocell and
control paths.
All inputs have the same delay, regardless of fan-out or
location. All logic resources have the same delay, regardless of logic complexity, interconnect topology or location
on the chip. All outputs have the same delay. The achievable clock rate is, therefore, determined only by the input
method (direct, latched or registered) and the number of
times a signal passes through the combinatorial logic.
Figure 11 defines the FastCompare timing parameters.
Figure 12 defines the carry propagation delays between
Macrocells and between Function Blocks. The parameters
describe the delay from the C IN , D1 and D2 inputs of a
Macrocell ALU to the C IN input of the adjacent Macrocell
ALU. These delays must be added to the standard
Macrocell delay path (tpD or tsu ) to determine the performance of an arithmetic function.
Timing and Delay Path Descriptions
Figure 5 defines the max clock frequency (with feedback).
Any Macrocell output can be fed back to the UIM as an
input for the next clock cycle. Figure 6 shows the relevant
delay path. The parameters fCYC and fevc1 specify the
maximum operating frequency for FastCLK and productterm clock operation respectively.
Figure 13 defines the incremental parameters for the
standard Macroceillogic paths. These incremental parameters are used in conjunction with pin-to-pin parameters
when calculating compound logic path timing. Incremental
parameters are derived indirectly from other pin-to-pin
measurement.
Figure 6 specifies the max operating frequency (fcLK~) for
pipelined operation between the input registers and the
Macrocell registers, using FastCLK.
UIM
FUNCTION BLOCK
INPUT OR
110 PIN
OUTPUT
OR 110 PIN
1IfCYC. 1/fCYC1
~:
FASTCLK OR
PRODUCT TERM CLOCK
MACROCELL REGISTER
OUTPUT
____ __________
~x~_·
Figure 5. Delay Path SpeCifications for fevc and f Cyc •
3-31
II
XC7272A Programmable Logic Device
UIM
FUNCTION BLOCK
INPUT OR
1/0 PIN
OUTPUT
OR 1/0 PIN
OUTPUT
DRIVER
FASTCLK,~
PIN
______
~
________________________________________
~
'"
1/fCLK3
:~
FASTCLK
INPUT-PAD
REGISTER OUTPUT
J~ r-\'----~
____~X~___________
Figure 6. Delay Path Specification for feLK>
UIM
FUNCTION BLOCK
INPUT OR
1/0 PIN
OUTPUT
OR 1/0 PIN
OUTPUT
DRIVER
INPUT OR
1/0 PIN
CLOCK
INPUT
________1
tSUl
: tHl ,
~:.------------~.,~
INPUT OR
1/0 PIN
..JXXXXX
-XXXX,.....,~,......'": '-____D_AT_A_ _ _
Figure 7. Delay Path Specification for t su • and t H•
3-32
~XIUNX
UIM
FUNCTION BLOCK
INPUT OR
1/0 PIN
OUTPUT
OR 1/0 PIN
OUTPUT
DRIVER
FASTCLK
PIN
r.g_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _.....
1£
FASTCLK
INPUT
______-J(
tSU
I:
I:
- tH
INPUT OR
I/O PIN
XXXX,--_D_ATA---JXXXXXXXX
Figure 8. Delay Path Specification for t..u and tH
UIM
INPUT OR
1/0 PIN
~
......
...
:...
INPUT-PAD
REGfSTER
Q
D
,...
jJ
FASTCLK
PIN
FASTCLK
PIN
)/I
~
IC..lII
_____-JI
',"
tSU2
: tH2 •
~.------------~I,~
INPUT OR
1/0 PIN
XXXX,-_ _D_AT._A_ - - J X X X X X
Figure 9. Delay Path Specification for tsu.and tHZ
3-33
II
XC7272A Programmable Logic Device
tSU2 and tH2 are measured with respect to the high-going
edge of FastCLK for registered inputs, and with respect to
the low-going edge of FastCLK for latched inputs.
Only the high gOing edge is used for docking the macrocell registers.
REGISTERED
INPUTS
FASTCLK
: tHA
=><
:••=;:::t:W:l=:t~ : «
INPUT USED
AS CLOCK
W1
tRA
:
.
~:
X >C
t
:
:+---+:~:
,
,
,
,
==X_A_C_T_IV_E~X
INAC1WE
UNLATCHED
INPUTS
INACTIVE
~TlVE
RESET/SET
DE-ASSERTED
VALID ENABLE
NON-REGISTERED
OUTPUTS
tAO
REGISTERED
OUTPUTS
__________~x.========)~:--~<~________X~_____________
Figure 10. Principal Pin-ta-Pln Measurements
INPUT USED AS
LATCH-ENABLE
=X. . .
X
A_C_T_IV_E...J
INACTIVE
x=
ISU3:tH3
:~:+-+.
COMPARATOR
INPUTS
r-----~
MATCHING INPUT
NON-MATCHING INPUT
~
INPUT USED AS
COMPARATOR DISABLE
NON-MATCHING
DISABLED *,"_EN_A_B_LE_D_
:
:~~
:
INPUT USED AS
COMPARATOR JAM
INA3
,..-------.~,
tPDC
COMPARATOR
OUTPUT
:==><
IPDC
:
: t PDC t :
: 1 PDC 1 :
:~:
:+---+: :+---+:
NO-MATCHX
MATCH
Figure 11. FastCompare Timing Waveforms
3-34
ACTIVE
X
NO-MATCH
X
INACTIVE
: IPDCt '
x=
:~:
XI.____
M_AT_C_H_ _ _
II
Figure 12. Arithmetic Timing Parameters
UIM
FUNCTION BLOCK
OUTPUT
OR 110 PIN
INPUT
OR 110 PIN
OUTPUT
OR 110 PIN
INPUT
OR 110 PIN
OUTPUT
OR 110 PIN
INPUT
OR 110 PIN
Figure 13. Incremental Timing Parameters
3-35
XC7272A Programmable Logic Device
58-Pin LCC, 84-Pin LCC and PGA Pinouts
68LCC
1
2
-
3
4
5
6
7
8
9
10
11
12
13
14
15
in XC7272A
Master Reset Vpp
InpuVFCI
InpuVFCI
InpuVFCI
InpuVFCI
InpuVFCI
InpuVFCI
GROUND
Fast CLKO
Fast CLKl
Input
Input
MC3-4
MC3-3
MC3-2
MC3-1
-
-
MC4-4
MC4-3
MC4-2
MC4-1
MC3-8
MC3-7
MC3-6
MC3-5
GROUND
-
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
out
Vee
Input
Input
Input
Input
MC2-9
MC2-8
MC2-7
MC2-6
GROUND
Input
Input
Input
Input
Input
Input
Input
Input
Input
MC2-5
MC2-4
MC2-3
MC2-2
MC2-1
MCl-9
MCl-8
MCl-7
MCl-6
GROUND
Input
Input
Input
Input
Input
MCl-5
MCl-4
MCl-3
MCl-2
MC1-l
84LCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
84PGA
F-9
F-ll
E-ll
E-l0
E-9
0-11
0-10
C-ll
8-11
C-l0
A-ll
8-10
8-9
A-l0
A-9
8-8
A-8
8-6
8-7
A-7
C-7
C-6
A-6
A-5
8-5
C-5
A-4
8-4
A-3
A-2
8-3
A-l
8-2
C-2
8-1
C-l
D-2
0-1
E-3
E-2
E-l
F-2
68LCC
35
-
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
-
-
60
61
62
63
64
65
66
67
68
-
3-36
84LCC
43
Input
MC8-9
44
Input
MC8-8
45
MC8-7
46
Input
Input
47
MC8-6
Input
MC8-5
48
GROUND
49
Input
MC8-4
50
Input
MC8-3
51
Input
MC8-2
52
Input
MC8-1
53
Input
MC7-9
54
MC7-8
Input
55
Input
MC7-7
56
MC7-6
57
Input
Input
MC7-5
58
GROUND
59
Input
MC7-4
60
Input
MC7-3
61
Input
MC7-2
62
MC7-1
Input
63
Vee
64
MC6-8
65
MC6-7
66
MC6-6
67
MC6-5
68
GROUND
69
MC6-4
70
MC6-3
71
MC6-2
72
MC6-1
73
Input
MC5-4
74
MC5-3
Input
75
Input
MC5-2/FCO
76
Input
MC5-1/FCO
77
GROUND
78
InpuVFCI
79
InpuVFCI
80
InpuVFCI
81
InpuVFCI
82
InpuVFCI
83
InpuVFCI
84
in
XC7272A
Vee
out
84PGA
F-3
G-3
G-l
G-2
F-l
H-l
H-2
J-l
K-l
J-2
L-l
K-2
K-3
L-2
L-3
K-4
L-4
J-5
K-5
L-5
K-6
J-6
J-7
L-7
K-7
L-6
L-8
K-8
L-9
L-l0
K-9
L-ll
K-l0
J-l0
K-ll
J-ll
H-l0
H-ll
F-l0
G-l0
G-ll
G-9
Device/Package/SpeedITemperature Availability
68 Pin
Windowed
Plastic
Ceramic
PLCC
CLCC
XC7272A-25
CI
84 Pin
Windowed
Ceramic
Plastic
PLCC
CLCC
84 Pin
Windowed
Ceramic
PGA
CI
CI
CI
CI
XC7272A-20
CI
CI
CI
CI
CI
XC7272A-16
CI
CI
CI
CI
CI
Package and User I/O Availability
Number of User 110 Available
68 Pin
84 Pin
XC7272A-25
56
72
XC7272A-20
56
72
XC7272A-16
56
72
II
Ordering Information
TITLL.
XC7272A - 25 PC 84 C
DeViCeTypel-
Temperature
Range
Number of Pins
~
Speed
Package Type
Speed Options
-25
25 ns (40 MHz) sequential cycle time
-20
20 ns (50 MHz) sequential cycle time
-16
16 ns (60 MHz) sequential cycle time
X3209
PC84 84-Pin Plastic Leaded Chip Carrier
WC84 84-Pin Windowed Ceramic Leaded
Chip Carrier
PG84 84-Pin Ceramic Windowed Pin Grid
Array
Temperature Options
Commercial
C
I
Industrial
Package Options
PC68 68-Pin Plastic Leaded Chip Carrier
WC68 68-Pin Windowed Ceramic Leaded
Chip Carrier
3-37
O°C to 70°C
-40°C to 85°C
XC7272A Programmable Logic Device
3-38
~
XC7300 EPLD Family
Table of Contents
Overview ................................................................. 3-40
XC7300 EPLD Family •............••..........•.. ;................ 3-41
Architecture ......................................................... 3-42
3.3 V orS V Interface Configuration ................... 3-46
Power-On Characteristics ................................... 3-46
Power Management ...........•..........•....•................ 3-47
Erasure Characteristics ...................................... 3-47
Design Recommendations .................................. 3-47
Design Security ................................................... 3-47
~ii~~~~~O~:1 ~.~~~~~i~.~.~~~~~~~~~~~.:::::::::::::: ~::~
XEPLD Development System ............................. 3-48
XC73108 Programmable Logic Device ................ ,.. 3-49
Power Management ............................................ 3-49
Absolute Maximum Ratings ................................ 3-51
Recommended Operating Conditions ................. 3-51
DC Characteristics Over Recommended
Operating Conditions ...................................... 3-52
Power-up/Reset Timing Parameters ................... 3-52
Fast Function Block External
AC Characteristics .......................................... 3-53
High-Density. Function Bloc.k External
AC Characteristics .......................................... 3-53
Fast Function Block Internal
AC Characteristics .......................................... 3-54
High-Density Function Block Internal
AC Characteristics .......................................... 3-54
I/O Block External AC Characteristics ................ 3-55
Internal AC Characteristics ................................. 3-55
84-Pin LCC Pinouts .....•..................................•... 3-58
144-Pin PGA Pinouts .......................................... 3-59
Ordering Information ........................................... 3-60
Component Availability ....................................... 3-60
3-39
II
Overview
Introduced in 1993, the XC7300 EPLD family is designed
to address customer needs for high performance and high
density in a single complex programmable logic device.
The XC7300 features an innovative Dual Block architecture consisting 'of two types of FUnctions Blocks (FBs)
interconnected by a Universal Interconnect Matrix (UIM).
The Function Blocks are represented by FAST Function
Blocks that are optimized for high performance and High
Density Function Blocks for highest possible logic density.
This innovative Dual-Block architecture combined with the
100% interconnect capability of the UIM, makes the XC7300
family ideal for converting high-speed and high-density
PAls into a complex PLD.
• Dual-Block architecture offers features for converting
high-speed and high-density PAls into a single
EPLD.
• Unrestricted Universal Interconnect Matrix (UIM) for
guaranteed interconnect
• Dedicated high-speed arithmetic carry logic for
efficient implementation of fast adders, subtractors,
accumulators, and magnitude comparators.
• Mixed voltage 1/0 operation providing 3.3 V or 5 V
interface configurations.
Xilinx XC7300 family offers four distinct advantages over
competing EPLDs.
3-40
XC7300
EPLD Family
Advance Product Information
Features
Description
• High-performance Eraseable Programmable Logic
Devices (EPLDs)
- 12 ns pin-to-pin delays
- SO MHz maximum clock frequency
The XC7300 family employs a unique Dual-Block architecture. Designers can now take advantage of high-speed
paths when required, without sacrificing the ability to do
complex functions or give up timing predictability.
• Advanced Dual-Block architecture
- Fast Function Blocks
- High-Density Function Blocks
This unique capability is achieved by combining two different logic blocks on the same device. Fast Function
Blocks (FFBs) provide fast, pin-to-pin speed and logic
throughput for critical decoding and ultra-fast state
machine applications. High-density Function Blocks (FBs)
provide maximum logic density and system-level features
to implement complex functions with predictable timing for
adders and accumulators, wide functions and state
machines requiring large numbers of product terms, and
other forms of complex logic.
• 100% interconnect matrix
• High-speed arithmetic carry network
- 1 ns ripple-carry delay per bit
- 40 MHz 16-bit accumulators
• Multiple independent clocks
• Each input programmable as direct, latched, or
registered
In addition, the XC7300 architecture employs the Universal Interconnect Matrix (UIM) that guarantees 100% interconnect of all intemal functions. This interconnect scheme
provides constant, short interconnect delays for all routing
paths through the UIM. Constant interconnect delays simplify device timing and guarantee design per-formance,
regardless of logic placement within the chip.
• High-drive 24 mA output
• 1/0 operation at 3.3 V or 5 V
• Meets JEDEC Standard (S-1A) for 3.3 V ±0.3 V
• Power management options
All XC7300 devices are designed in O.S~ CMOS EPROM
technology, supporting 12 ns pin-to-pin delays and system clock rates up to SO MHz.
• Multiple security bits for design protection
• Supported by industry standard design and verification
tools
• Advanced O.S~ CMOS EPROM process
The XC7300 Family
XC7336
XC7354
XC7372
XC73108
XC73144
Typical 22VI0 Eqivalent
4
6
8
12
16
Number of Macrocells
36
54
72
108
144
Number of Function Blocks
4
6
8
12
16
Number of Flip-Flops
36
108
126
198
234
Number of Fast Inputs
18
24
30
42
54
Number of Signal Pins
48
66
84
120
156
3-41
II
XC7300 EPLD Family
Architecture
All XC7300 EPLDs include programmable power management features to specify high-performance or lowpower operation on an individual Macrocell-by-Macrocell
basis. Unused Macrocells are automatically turned off to
minimize power dissipation. Designers can operate
speed-critical paths at maximum performance, while noncritical paths dissipate less power.
The XC7300 architecture consists of multiple pro-grammable Function Blocks interconnected by a UIM as shown in
Figure 1. The Dual-Block architecture contains two types of
function blocks: Fast Function Blocks and High-Density
Function Blocks. Both types of function blocks, and the 1/0
blocks, are interconnected through the UIM.
Xilinx development software supports XC7300-series
EPLD design using third-party schematic entry tools, HDL
compilers, or direct equation-based text files. Using a PC
or a workstation and one of these design capture methods, designs are automatically mapped to an XC7300
EPLD in a matter of minutes.
Fast Function Blocks
The Fast Function Block receives 24 signals and their
complements from the UIM. The 24 inputs can be individually selected from the UIM, 12 fast input pins, or the nine
Macrocell feedbacks from the Fast Function Block. The
programmable AND array in each Fast Function Block
generates 45 product terms to drive the nine Macrocells in
each Fast Function Block. Each Macrocell can be configured for registered or combinatorial logic. See Figure 2.
The XC7300-series devices are available in plastic and
ceramic leaded chip carriers, pin-grid-array (PGA), and
quad flat pack (QFP) packages. Package options include
both windowed ceramic for design prototypes and onetime programmable plastic versions for cost-effective production volume.
Output
Five product terms from the programmable AND array are
allocated to each Macrocell. Four of these product terms
FFB
FB
UIM
FB
1/0
Block
I/O
Block
FB
FB
X3204
Figure 1. XC7300 Device Block Diagram
3-42
are ORed together and drive the input of a programmable
D-type flip-flop. The fifth product term drives the asynchronous active-High Set Input to the Macrocell flip-flop.
The flip-flop can be configured as transparent for combinatorial outputs.
assignment scheme. The product term assignment transfers product terms in increments of four product terms
from one Macrocell to the next. Complex logic functions
requiring up to 36 product terms can be implemented
using product term assignment. When product terms are
assigned to adjacent Macrocells, the product term normally dedicated to the Set function becomes the D-input
to the Macrocell register. Thus, the Macrocell is still usable
while product terms are transferred to adjacent Macrocells
(Figure 3).
The programmable clock source is one of two global FastClK signals (FClKO or FClK1) that are distributed with
short delay and minimal skew over the entire chip.
The Fast Function Block Macrocells drive chip outputs
directly through 3-state output buffers. Each output buffer
can be individual controlled by one of two dedicated FastOE inputs, enabled permanently or disabled permanently. The Macrocell output is also routed back as an
input to the Fast Function Block, and as an input to the
UIM.
High-Density Function Blocks
Each member of the XC7300 family contains multiple,
High-Density Function Blocks linked though the UIM.
Each Function Block contains nine Macrocells. Each
Macrocell can be configured for either registered or combinatorial logic. A detailed block diagram of the XC7300
FB is shown in Figure 4.
Product Term Assignment
The XC7300-series uses a product term assignment
scheme that provides product-term flexibility without disabling Macrocell outputs.
Each FB receives 21 signals and their complements from
the UIM and an additional three inputs from the Fast Input
(FI) pins.
The sum-of-product OR gates for each Macrocell can be
expanded using the Fast Function Block product term
12 from
Fast
Input Pins
2.
Inputs from
UIM
Sum-of-Products
lrom
Fe~a;~C:k;_-L-_ _ _ _ _ _ _ _ _ _ _-+_~
_______--'
X2900
Sum-of-Products
10
Succeeding Macrocell
Figure 2. Fast Function Block Macrocell Schematic
3-43
II
XC7300 EPLD Family
Shared and Private Product Terms
Each Macrocell contains five private product terms that
can be used as the primary inputs for combinatorial functions implemented in the Arithmetic Logic Unit (ALU), or
as individual Reset, Set, Output-Enable, and Clock logic
functions for the flip-flop. Each Function Block also provides an additional 12 shared product terms, which are
uncommitted product terms available for any of the nine
Macrocells within the Function Block.
From Previous
Macrocell
Single-Product Term Assignment
L..-C)o---\ D
Q
Eight-Product Term Assignment
S
~~-L~-----1~---1D
Four private product terms can be ORed together with up
to four shared product terms to drive the D1 input to the
ALU. The D2 input is driven by the OR of the fifth private
product term and up to eight of the remaining shared
product terms. The shared product terms add no logic
delay, and each shared product term can be connected to
one or all nine Macrocells in the Function Block.
Arithmetic Logic Unit
The functional versatility of each Macrocell is enhanced
through additional gating and control functions available
in the ALU. A detailed block diagram of the XC7300 ALU
is shown in Figure 5.
Q
X3205
Figure 3. Fast Function Block Product Term Assignment
The ALU has two programmable modes; logic and arithmetic. In logic mode, the ALU functions as a 2-input function generator using a 4-bit look-up table that can be
programmed to generate any Boolean function of its two
inputs. The function generator can OR its inputs, widen
Feedback
Enable
OVerride
• OE is forced high when P-term is not used
X1829
Figure 4_ High-Density Function Block and Macrocell Schematic
3-44
~Xlur\lX
CLK signals (FCLKO and FCLK1). Global FastCLK signals are distributed to every Macrocell flip-flop with short
delay and minimal skew.
Carry Output
~
-'""'"'"
J
..........
J
The asynchronous Set and Reset product terms override
the clocked operation. If both asynchronous inputs are
active simultaneously, Reset overrides Set.
01
Sum-ofProducts
Function
Generator
02
Sum-ofProducts
In addition to driving the chip output buffer, the Macrocell
output is routed back as an input to the UIM. One private
product term can be configured to control the Output
Enable of the output buffer and/or the feedback to the
UIM. If it is configured to control UIM feedback, the Output Enable product term forces the UIM feedback line
High when the Macrocell output is disabled.
01
JJ)-
02
To Macrocell
Flip-Flop
'~m..~
Carry Control
~
Carry Input
X3206
Figure 5_ ALU Schematic
ing the OR function to a maximum of 17 inputs_ It can
AND them, which means that one sum-of-products can be
used to mask the other_ It can also XOR them, toggling
the flip-flop or comparing the two sums of products_ Either
or both of the sum-of-product inputs to the ALU can be
inverted, and either or both can be ignored. Therefore, the
ALU can implement one additional layer of logic without
any speed penalty.
Input/Output Blocks
Macrocells drive chip outputs directly through 3-state output buffers, each individually controlled by the Output
Enable product term mentioned above. The Macrocell
output can be inverted; an additional configuration optio~
allows the output to be disabled permanently. Two dedIcated FastOE inputs can also be configured to control
any of the chip outputs instead of, or in conjunction with,
the individual Output Enable product term. See Figure 6.
In arithmetic mode, the ALU block can be programmed to
generate the arithmetic sum or difference of the 01 and
02 inputs. Combined with the carry input from the next
lower Macrocell, the ALU operates as a 1-bit full adder
generating a carry output to the. next higher Macrocell.
The carry chain propagates between adjacent Macrocells
and also crosses the boundaries between Function
Blocks. This dedicated carry chain overcomes the inherent speed and density problems of the traditional EPLD
architecture when trying to perform arithmetic functions.
Carry Lookahead
Each Function Block provides a carry lookahead generator capable of anticipating the carry across all nine Macrocells. The carry lookahead generator reduces the ripplecarry delay of wide arithmetic functions such as add, subtract, and magnitude compare to that of the first nine bits,
plus the carry lookahead delay of the higher-order Function Blocks.
Macrocell Flip-Flop
The output from the ALU block drives the input of a programmable D-type flip-flop. The flip-flop is triggered by the
rising edge of the clock input, but it can be configured as
transparent, making the Q output identical to the 0 input,
independent of the clock, or as a conventional
flip-flop.
The Macrocell clock source is programmable and can be
one of the private product terms or one of two global Fast-
3-45
Each signal input to the chip is connected to a programmable input structure that can be configured as direct,
latched, or registered. The latch and flip-flop can use one
of two FastCLK signals as latch enable or clock. The two
FastCLK signals are FCLKO and a global choice of either
FCLK1 or FCLK2. Latches are transparent when FastCLK is High, and flip-flops clock on the rising edge of
FastCLK. The flip-flop includes an active-low clock
enable, which when High, holds the present state of the
flip-flop and inhibits response to the input signal. The
clock enable source is one of two global Clock Enable
signals (CEU and GET). An additional configuration option
is polarity inversion for each input signal.
Universal Interconnect Matrix
The UIM receives inputs from Macrocell feedback lines,
bidirectional 1/0 pins, and dedicated input pins. Acting as
an unrestricted crossbar switch, the UIM generates 21
output signals to each High-Density Function Block and
24 output signals to each Fast Function Block.
Any UIM input can be programmed to connect to any UIM
output. The delay through the interconnect matrix is c~n
stant, regardless of the routing distance and complexity,
fan-out, or fan-in. Furthermore, any UIM input can drive a
UIM output, even multiple outputs, and the delay is constant.
When multiple inputs are programmed to be connected to
the same output, this output produces the logical AND of
the input signals. By choosing the appropriate signal
II
XC7300 EPLD Family
r---------------IX
r-1----------------f,XI
FOEO
FOEl
va. FCLKJO. coo
FOEIO
Pins Only
' - - - - - - I ) ( J Pin
CEO
CEl
ToUIM - - - - - - -
To FuncUon BlocfI:
AND:'~ir!,"u~
_______
FCLKO
Pins Only)
FCLK1
Input and
FClK2
I/O Pins Only
)(2832
Figure 6. Input/Output Schematic Diagram
inversions at the input pins, Macrocell outputs, and Function Block AND-array input, this AND logic can also be
used to implement wide NAND, OR, or NOR functions.
This offers an additional level of logic without any speed
penalty.
components. In addition, the output structure is designed
so that the 1/0 can also safely interface to a mixed
3.3 V and 5 V bus.
A Macrocell feedback signal that is disabled by the output
enable product term represents a High input to the UIM.
Programming several such Macrocell outputs onto the
same UIM output thus emulates a 3-state bus line. If one
of the Macrocell outputs is enabled,. the UIM output
assumes its level.
Like many highly-flexible EPLDs, the XC7300 devices
undergo a short intemal initialization sequence upon
device powerup. During this time, the outputs remain
tristated while the device is configured form its intemal
EPROM array pattem and all registers are initialized.
Note that expect for the short delay during device initialization, this operation is completely transparent to the
user. The initialization typically lasts 200 Ils and not more
than 300 Ils in all cases.
3.3 Vor 5 V Interface Configuration
XC7300devices can be used in systems with two different supply voltages: 3.3 V and 5 V. Each XC7300 device
has separate Vcc connections to the intemal logic and
input buffers (VCCINT) and to the 1/0 drivers (VCCIO).
VCCINT must always be connected to a nominal 5 V supply, but VCCIO may be connected to either 3.3 V or 5 V,
depending on the output interface requirement.
Power-On Characteristics
When VCC10 is connected to 5 V, the input thresholds are
TIL levels, and thus compatible with 3.3 V and 5 V logic.
The output High levels are also TIL compatible. When
VCCIO is connected to 3.3 V, the input thresholds are still
TIL levels, and the outputs pull up to the 3.3 V rail. This
makes the XC7300 ideal for interfacing directly to 3.3 V
3-46
For additional flexibility, an active-Low Master Reset pin
is provided so that EPLD can be reinitialized even after
power is applied. It allows the EPLD to be initialized along
with other devices in the system. When it is switched Low,
all outputs become 3-stated and the initialization
sequence is started. When it retums to High, the outputs
become enabled and the device is ready for operation. If
this flexibility is not needed, simply connect the Master
Reset pin to the device VCCINT.
During the initialization sequence, all FFB Macrocell registers and input registers or latches are preloaded High,
and by default, all FB Macrocell registers are pre loaded
I::XIUNX
Low. The FB Macrocell register preload state can be
selected by the user. Note that since the device inputs
may be active for part of the initialization, key inputs such
as Clock, Reset, or Set should remain inactive during initialization to ensure the preloaded registers maintain the
correct state before operation.
400
C
--..
E
c:
~:::J
300
0
Power Management
>ii
200
Q.
As EPLDs become more complex and system clock frequencies rise, control of on-chip power dissipation
becomes increasingly important. The XC7300 powermanagement scheme permits non-speed-critical parts of
a design to be operated at reduced power. Overall power
disspation is often reduced significantly, since, in most
systems, only a small part is speed-critical.
en
Macrocells can individually be specified for high-performance or low power operation by adding attributes to the
logic schematic, or aeclaration statements to the behavioral description. To further conserve power, unused Macrocells are automatically turned off.
Figure 7 shows typical power requirements for XC73108
device, assuming all Macrocells are enabled and' switching at the indicated clock frequency. The two curves
shown are for the two extreme cases; all Macrocells in
high-performance mode, and all Macrocells in low-power
mode. Actual chip di~sipation will be between the two
curves, The power for each. member of the XC7300 family
can be calculatecl. forspepific operating conditions by
using parameters supplied in the individual data sheets.
:::J
100
o
10
20
40
30
Clock Frequency (MHz)
X3207
Figure 7. Typical Power Requirements for XC73108
I
Design Security
Each member of the XC7300 family has a multibit security system that controls access to the configuration programmed into the device. This security scheme uses
multiple EPROM bits at various locations within the
EPROM array to offer a higher degree of design security
than other EPROM and fused-based devices. Programmed data within EPROM cells is invisible-even
when examined' under a' microscope-:-and Cannot be
selectively erased. The EPROM security bits,and the
device configuration data, reset when the device
erased.
is
Erasure Characteristics
In windowed packages, the content of the EPROM array
can be erased by exposure to Ultraviolet light 01 wavelengths of approximately 4000 A. The recommended erasure time isapproxim~tely 1 hr~ when the device is placed
within 1 in. of an ultraviolet I~mp with a. 12,000 IlW/cm2
power rating. To prevent unintentional exposure,' place
opaque labels over the device window.
When the deviCe is exposed to high intensity UV light for
much longer periods, permanent damage can occur, The
maximum integrated dose the XC7300 EPLD can be
~xposed to witholifdamage is 7000 W. s/cm2, or approxImately one week at 12,000 IlW/Cm2.
,
Design Recommendations
For proper operation, all unused input and 110 pins must
be connected to a valid logic level (High or Low). The recommended decoupling for all Vee pins should total 1 IlF
using high-speed (tantalum or ceramic) capacitors.
Use electrostatic discharge (ESD) handling procedures
with the XC7300-series EPLDs to prevent damage to the
device during programming, assembly, and test.
High-Volume Production Programming
The XC7300 family offers flexibility for lOW-volume prototypes as well as cost-effectiveness for high-volume production. The designer can start' with ceramic window
package parts for prototypes, ramp Lip initial production
using low-cost plastic parts programmed in-house, and
then shift into high-volume production using Xilinx factoryprogrammed and tested devices with competitive pricing
based on volume.
The Xilinx factory-programmed concept offers significant
advantages ov~r competitive "masked PLDs," or ASIC
redesigns. For example:
.
• No redesign is required - Even though masked
devices are advertised as timing compatible, subtle
differen.ces.in Ii chip layout can mean system failure.
• Devices are factory tested- Factory-programmed
devices,iife tested as part of the manufacturing flow,
insuring high-quality products.
3-47
XC7300 EPLD Family
High Density Function Block
~rD!Jr-----'1 L
Input Register
'----
IsUIN
!tiIN
IsUCEIN
IticEIN
CE
'coIN
IsUi
'col
UIM
Delay
\POI
!til
tAOI
tulM
Cicek Lt-------'
._I-L P-Term
\pel
J
._I-I
P-Term OE
toEI
JI t - - - - - - - - - '
High Density Function Block
FAST
INPUT
tiN
~ H----+-+--+--+~-.IrFF:;:ic: Ir P-Term . L
I
FFB Feedback
"'FO
1
h
Assignlll$nt
\prxl
~
I -
IfsUI
"'COl
IfpOI
IfHI
"'AOI
'--~---'
FCLK
C>-------+-~ t~~I~~~-------------~
Figure 8. XC7300 TIming Model
• Shipments are delivered fast - Production shipments
can begin within a few weeks, eliminating masking
delays and qualification requirements.
For factory-programming procedures, contact your local
Xilinx representative.
cally onto a chosen EPLD device, producesdocumentation for design analysis and creates a programming file to
configure the device.
Timing Model
• Familiar design approach similar to TTL and PLD
techniques
Timing within the XC7300-series EPLDs is easily .determined using e~ernal timing parameters from the device
data sheet, using a variety of CAE simulators, or with the
timing model shown in Figure 8.
The timing model is based on the fixed intemal delays of
the XC7300 architecture which consists of four basic
parts: I/O Blocks, the UIM, Fast Function Blocks and
High-Density Function Blocks. The timing model identifies
the intemal delay paths and their relationships to ac characteristics. Using this model and theac characteristics,
designers can easily calculate the timing information for a
particular EPLD.
The following lists some of the XEPLD Development System features.
• Converts netlist to fuse map in minutes using a '486
PC or workstation platform
'
• Interfaces to standard third-party CAE schematics,
simulation tools, and behavioral languages
• Schematic library with familiar and powerful TTL-like
components, including PLDs and ALUs
XEPLD Development System
The designer can create, implement, and' verify digital
logic circuits for EPLD devices using the Xilinx XEPLD
Development System. Designs can be 'represented as
schematics consisting of XEPLD library components, as
behavioral descriptions, or as a mixture of both. The
XEPLD translator maps the design quickly and automati-
3-48
• Predictable timing even before design entry, using'
library components and Boolean equations
• Timing simulation using Viewsim. OrCAD VST, and
other tools controlled by the Xilinx Design Manager
(XDM) program
XC73108
Programmable Logic Device
Advance Product Information
Macrocells configurable for registered or combinatorial
logic and produces nine outputs which feedback to the
UIM. For complete description of device functionality, see
the XC7300 EPLD Family data sheet.
Features
• High-Performance EPLD
- 12 ns pin-to-pin delay
- BO MHz maximum clock frequency
Power Management
• Advanced Dual-Block architecture
- 2 Fast Function Blocks
- 10 High-Density Function Blocks
The XC7310B power management scheme allows
designers to control on-chip power dissipation by configuring individual Macrocells to operate in high-performance or low-power modes of operation. Unused
Macrocells are turned off to minimize power dissipation.
• 100% interconnect matrix
• High-Speed arithmetic carry network
- 1 ns ripple-carry delay per bit
- 35 MHz 16-bit accumulators
Figure 7 in the XC7300 Family data sheet shows typical
power requirements for the XC7310B device, assuming
all Macrocells are enabled and switching at the indicated
clock frequency. The top and bottom curves show the two
extreme cases of all Macrocells in high-performance
mode, and all Macrocells in low-power mode. Actual chip
dissipation will be between the two curves.
• 10B Macrocells with programmable 1/0 architecture
• Up to 90 inputs programmable as direct, latched, or
registered
• 1B outputs with 24 mA drive
• 3.3 V or 5 V 1/0 operation
Power dissipation for each design can be approximated for
specific operating conditions using the following equation.
• Meets JEDEC Standard (B-1A) for 3.3 V ±O.3 V
Icc =(MC LP • 1.35 rnA) + (MC HP ·2.5 mAl + (MC l • fl
0.02 mNMHz) + ... + (MC n • fn • 0.02 mNMHz)
• Power management options
• Multiple security bits for design protection
•
Where:
• B4-pin leaded chip carrier and 144-pin Pin-Grid-Array
packages
MC LP = Number of Macrocells in low-power mode
• Footprint compatible with XC7372 and XC73144
devices
MC HP
mode
General Description
MC 1 = Number of Macrocells operating at frequency
f1 in MHz
The XC7310B is a member of the Xilinx Dual-Block EPLD
family. It consists of two Fast Function Blocks and ten
High-Density Function Blocks interconnected by a central
Universal Interconnect Matrix (UIM).
The Universal Interconnect Matrix connects the Function
Blocks to each other and to all input pins, providing 100%
connectivity between the Function Blocks. This allows
logic functions to be mapped into the Function Blocks and
interconnected without routing restrictions.
The 12 Functions Blocks in the XC7310B (Figure 1) are
PAL-like structures, complete with programmable product
term arrays and programmable multilevel Macrocells.
Each Function Block receives 24 inputs, contains nine
3-49
= Number of Macrocells
in high-performance
MCn =Number of Macrocell operating at frequency fn
in MHz
Note: Number of Macrocells refers to both Fast Function Block
(FFB) and High-Density Function Block (FB) Macrocells.
For example, in a system design with 72 Macrocells in
low-power mode at 20 MHz, 1B Macrocells in high-performance mode at 40 MHz, and 18 Macrocells in high-performance mode at 80 MHz:
Icc =(72 ·1.35) + (36·2.5) + (72 ·20·0.02) + (18 • 40·0.02)
+ (18·80·0.02)
Icc = 97 + 90 + 29 + 14 + 29 =259 mA
I
XC73108 Programmable Logic Device
.
..
..
PLCC
144
PGA
.-=-~-
B3
:: I-'-;:::---l=
81
80
79
01
G3
El
F3
N3
13
P4
15
NO
I.
17
18
I.
20
21
IIFI
IIFI
IIFI
IIFI
~~~:~-~~
r---
· J2r--1--11212
~::::::~FOg:::::::::t::::::J[:::l~I.tC~;I.;\'pFFB~'
MC1-2
PO ~~FOg:::=tjt~I.tC~I-3~
FO
MOI-4
~
:
AS
FO
NO
FO
>~
12
8
>-
12
::~ ;t9l~
~
MC2·7
MC2-8
£~; ~~
MC1-8
MC2-2
~'--
_~
39
Cony
.
iii
I::::
. .~do.l~
i:::
~
MC3-8
MC3-7
MC3-2
~ft
110
AS
A4
B4
B3
110
110
rJO
110
~
I----
MC11-4
MC11-5
i
~ ~
: ~~1IOIF1~1IO~=§tJt:::~:~:~~~~7 ~
A
.."t::::::1IOIF1~~=E=~~~MC~I~'~~~
Mel'"
K2
12
10
MC10-4
MOl0-5
~
O/FCLK1
0iFCLK2
~
~
:~:~
IIOIFI
MC1D-8
~
. ...
87
co
B5
..,
co
IfQ/f1
L1
K1
~
:~
::
...
70
71
72
"""'I'.,~:
110
A1
110
H1
IIOIFt
R1
MC4-7
lIOIFI
R7
:::::
~ 111:"'!UI~~!!I~j:::i~l:
~=
MC4-2
110
N5
~TI
110
A2
IIOIFI
IIOIFI
FI
G2
F2
CI
...,.-9
JJ.-
~"'1/OIF1""".--{:=I+=f-iiMC"I"'o-o-i;l
23
'AS7
MC4-8
...,.~
M3
P3
P2
UIM
1;!,:;Ihf"F6"'i'0
----;;:-l---l-J.-...
0
MC1001
~ 1-0000;;-;;;O:;-LKO;;;;---j.--l+---l-T.:~:~::::;J
M1
11
r
IIOIFI
NI
[ml.tC4~"~~§lIOIFi'~"'
MOl1·'
t.tC11-2
MCl1-3
IIFI
FO
FO
FO
FO
FO
FO
FO
FO
FO
FFB2 MC2-9
MC2-8
39
B10
..
PLCC
~---J---1IF;;1IF'.-:---i ~
-
FO
144
PGA
,..-----J""""-::IIFI;:;----.J
MC5-7
IIOIFI
MC5-8
MC5-8
MC5-4
MC5-3
MC5-2
O/FOEI
O/FOEO
OJCKEN1
O/CKENO
0
o
llFB9
IIOIF'
IIOIF'
2'
25
34
35
IIOIFI
...
110
110
110
29
30
-'-TI
FB7Jl..
MC7-9
"
.
MC7~
32
33
I.tC7-7
r.tC7-8
37
M07-o
3.
M07-4
M07_3
40
"43
MC7-2
~jJ
Figure 1. XC73108 Functional Block Diagram
3-50
""co
B2
E2
EO
77
78
75
7'
. .,.
. .
C8
AS
C8
CI
Dl
83
82
51
110
110
AlO
59
57
""
""""
1'0/1"
AI
58
"
55
1'0/1',
"'"
"
""""
""""
Fl.
GI'
Fl'
110
G15
""
EI'
54
.
....
.
53
50
.7
Notice: The information contained in this data sheet pertains to products in the initial production phases of
develompment. These specifications are subject to change without notice. Verify with your local Xilinx sales office that
you have the latest data sheet before finalizing a design.
Absolute Maximum Ratings
Value
Units
Symbol
Parameter
Vcc
Supply voltage with respect to GND
-0.5 to 7.0
V
VIN
DC Input voltage with respect to GND
-0.5 to 7.0
V
VTS
Voltage applied to 3-state output with respect to GND
-0.5 to 7.0
V
TSTG
Storage temperature
-65 to +150
°C
TSOL
Maximum soldering temperature (1 Os
+260
°C
@
1/16 in.
=1.5 mm)
Warning. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the
device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those listed under Recommended Operating Conditions is not implied Exposure to Absolute Maximum Ratings conditions for extendedperiods of time may affect device reliability.
I
Recommended Operating Conditions
Symbol
Parameter
VCCINTI
VCCIO
Supply voltage relative to GND
@
5V
Commercial
Supply voltage relative to GND
@
5V
Industrial
VCCIO
1/0 supply voltage relative to GND
VIL
VIH
Vo
0° C t0700 C
-40° C to 85° C
Min
Max
Units
4.75
5.25
V
V
4.5
5.5
3.0
3.6
V
Low-level input voltage
0
0.8
V
High-level input voltage
2.0
Vcc+0.3
V
0
VCCIO
V
@
3.3 V
Output voltage
3-51
XC73108 Programmable Logic Device
DC Characteristics Over Recommended Operating Conditions
Symbol
Parameter
Test Conditions
Min
VO H
5 V TTL High-level output voltage
I/O = -4.0 mA
Vee=Min
2.4
V
3.3 V High-level output voltage
1/0= -3.2 mA
Vee = Min
2.4
V
Max
Units
FO = 24 mA
1/0= 12mA
Vee = Min
0.5
V
5 V Low-level output voltage
3.3 V Low-level output voltage
I/O = 10 mA
Vee = Min
0.4
V
IlL
Input leakage current
Vee = Max
VIN = GND or V eelo
±10
!1A
loz
Output high-Z leakage current
Vee = Max
Vo = GND or Veelo
±10
!1A
CIN
Input capacitance for Input and I/O pins
VIN =GND
f = 1.0 MHz
10
pF
CIN
Input capacitance for global control pins
(FCLKO, FCLK1, FCLK2, FOEO, FOE1)
VIN=GND
f = 1.0 MHz
15
pF
COUT
Output capacitance*
Vo=GND
f = 1.0 MHz
20
pF
Max
Units
VOL
• Sample tested
Power-up/Reset Timing Parameters
Symbol
Parameter
Min
tWMR
Master Reset input Low pulse width
100
tveeR
Vee rise time (if MR not used for power-up)**
tRESET
Configuration completion time (to outputs operational)
Type
ns
5
fls
200
flS
··Vcc rise must be monotonic. Following reset, the Clock, Reset, and Set inputs must not be asserted until all applicable input
and feedback set-up times are met in order to guarantee a predictable initial state.
3-52
Fast Function Block (FFB) External AC Characteristics
XC731 08-12
XC731 08-15
XC731 08-20
Units
Min
Symbol
Parameter
fCF
Max count frequency (1,2)
tSUF
Direct input setup time before
FCLK l' (1)
6
0
tHF
Direct input hold time after FCLK l'
leOF
FCLK l' to output valid
t pDFO
Direct input to output valid (1, 2)
t pDFU
I/O to output valid (1, 2)
tcwF
Fast clock pulse width
Max
Min
Max
Min
67
80
7
Max
50
10
0
MHz
ns
0
ns
9
12
15
ns
12
15
20
ns
35
ns
22
6
27
9
7
ns
High-Density Function Block (FB) External AC Characteristics
XC73108-12
XC731 08-15
XC731 08-20
Units
Symbol
Parameter
Min
Max
Min
Max
Min
Max
fc
Max count frequency (1, 2)
tsu
I/O setup time before FCLK l' (1,2)
18
tH
I/O hold time after FCLK l'
-8
tco
FCLK l' to output valid
tpsu
I/O setup time before p-term clock l' (2)
7
tpH
I/O hold time after p-term clock l'
0
tpco
P-term clock
tpD
I/O to output valid (1,2)
lew
Fast clock pulse width
6
7
9
ns
t pcw
P-term clock pulse width
8
10
12
ns
Notes:
45
55
22
-10
9
ns
20
12
ns
ns
0
0
MHz
ns
-13
15
12
l' to output valid
35
28
ns
23
28
36
30
36
45
ns
ns,
1, This parameter is given for the high-performance mode. Inlow-power mode, this parameter is increased due to
additional logic delay of tLOGILP - tLOGI'
2. Specifications account for logic paths that use the maximum number of available product terms for a given Macroc.ell.
3-53
I
XC73108 Programmable Logic Device
Fast Function Block (FFB) Internal AC Characteristics
XC731 08-12
XC73108-15
XC731 08-20
Units
Min
Max
Max
Min
Min
Max
Symbol
Parameter
tFLOGI
FFB logic array delay (2)
2
2
3
tFLOGILP
Low-power FFB logic array delay (2)
7
8
11
t FSUI
FFB register setup time
3
4
6
tFHI
FFB register hold time
3
3
4
tFcol
FFB register clock-to-output delay
t FPDI
FFB register pass through delay
1
1
2
tFAOI
FFB register async. set delay
3
4
tpTXI
FFB p-term assignment delay
1.2
1.5
6
2.0
1
1
1
ns
ns
ns
ns
ns
ns
ns
ns
High-Density Function Block (FFB) Internal AC Characteristics
XC731 08-12
XC731 08-15
XC731 08-20
Units
Symbol
Parameter
Min
t lOGI
FB logic array delay (2)
4
5
6
ns
tLOGILP
Low power FB logic delay (2)
9
11
14
ns
tSUI
FB register setup time
3
4
6
ns
tHI
FB register hold time
4
5
6
ns
tCOI
FB register clock-to-output delay
1
1
1
ns
tpDI
FB register pass through delay
4
4
4
ns
t AOI
FB register async. set/reset delay
4
5
7
ns
IRA
Set/reset recovery time before FCLK i
tHA
Set/reset hold time after FCLK
t pRA
Set/reset recovery time before p-term clock
i
Max
Min
Max
Min
Max
21
25
31
ns
0
0
0
ns
12
15
20
ns
i
i
12
9
8
IpHA
Set/reset hold time after p-Ierm clock
IpCI
FB p-term clock delay
0
0
0
ns
tOEI
FB p-term output enable delay
5
7
9
ns
tCARY8
ALU carry delay within 1 FB
8
12
15
ns
tCARYFB
Carry lookahead delay per additional Functional Block (3)
2
3
4
ns
Notes:
(3)
ns
2. Specifications account for logic paths that use the maximum number of available product terms for a given Macrocell.
3. Arithmetic carry delays are measured as the increase in required set-up time to adjacent Macrocell(s) for adder with
registered outputs.
3-54
I/O Block External AC Characteristics
XC731 08-12
XC731 08-15
XC731 08-20
Units
Symbol
Parameter
fiN
Max pipeline frequency (input register to FFB or
FB register) (2)
tSUIN
Input register/latch setup time
before FCLK l'
8
10
12
ns
tHIN
Input register/latch hold time after FCLK i
0
0
0
ns
Min
Max
Min
FCLK i to input register/latch output
!cESUIN
Clock enable setup time before FCLK i
8
!cEHIN
Clock enable hold time after FCLK i
Min
45
55
!cOIN
Max
4
Max
35
5
6
MHz
ns
12
0
ns
0
10
0
!cWHIN
FCLK pulse width high time
6
7
9
ns
tcwLlN
FCLK pulse width low time
6
7
9
ns
ns
Internal AC Characteristics
XC731 08-12
XC731 08-15
XC731 08-20
Min
Min
Min
I
Units
Note:
Symbol
Parameter
tiN
Input pad and buffer delay
t FOUT
FFB output buffer and pad delay
loUT
FB output buffer and pad delay
tUIM
Universal Interconnect Matrix delay
t FOEI
Fast output enable/disable buffer delay
tFCLKI
Fast clock buffer delay
Max
Max
Max
4
5
5
6
ns
7
9
ns
8
10
12
15
4
14
15
20
5
ns
10
12
3
ns
ns
ns
2. Specifications account for logic paths that use the maximum number of available product terms for a given Macrocell.
3-55
XC73108 Programmable Logic Device
Synchronous Clock Switching Characteristics
FCLK Pin
DATAICE at INPUT
I/O REGISTER
INPUT, I/O REGISTER
to UIM
\L-__
FAST CLOCK
INPUT DELAY
DATA at INPUT
I/O Pin
__~x~____
+-____
~-------------
t LOGI ---7'..
----l.~: t
tHI
t FLOGI
_ : SUI '.....f----1•. . , : - t
FHI
: t FSUI :
DATA from
LOGIC ARRAY
=============X~~:~~=========
tCOI_+:..
_----.,.~;: tOUT : _
t FCOI
: t FOUT :
REGISTER to
OUTPUT Pin
----------------------~~~---X3577
3-56
~XiUNX
Combinatorial Switching Characteristics
=J
~
:'-1
INPUT, VO Pin
i
IN
~
UIMDELAY
IUlu--j
----~~~--~i----------lILOGI
I FLOGI
:
LOGIC DELAY
P-TERM
ASSIGNMENT
DELAY
TRANSPARENT
REGISTER
DELAY
I
OUTPUT Pin
)(3579
Asynchronous Clock Switching Characteristics
INPUT, VO Pin
\'----_1
INPUT, VO DELAY
-:
UIMDELAY
lUlu
----~!~--~\'--_~/~--\~-----------i
CLOCKal
REGISTER
\'---------
--
I LOGI
\~_I
-------,-----<1
_ : lsul :-: - : I HI - -
DATA from
LOGIC ARRAY
------~~~~!~~~------~~~--------j
REGISTER to
UIM
leol
r-
lUlu - :
--------t-l------'X
-i
REGISTER 10
OUTPUT Pin
\~----
lOUT
~
~
:.. I
--- I
-'
~ i ~~
C
:-- lOUT--:
----------------~~--------------
X3580
3-57
XC73108 Programmable Logic Device
XC73108 84-Pin LCC Pinouts
Pin
Description
LCC
Pin
No.
Pin
Description
LCC
Pin
No.
Pin
Description
LCC
Pin
No.
Pin
Description
LCC
Pin
No.
V CC10
-
V CC10
-
V CC10
-
V CC10
-
0/CE1
75
0/FCLK2
12
I/O
33
1I0/FI
54
FO
-
I/O
-
110
-
110
-
O/FOEO
76
FO
13
110
34
1I0/FI
55
0
-
I/O
-
110
-
1I0/FI
-
0/FOE1
77
VCCINT
-
I/O
35
110
56
0
-
FO
14
I/O
-
GND
VCCINTNpp
78
I/O
-
I/O
36
1I0/FI
I/FI
79
FO
15
I/O/FI
-
I/O/FI
-
I/O/FI
-
I/O
-
I/O
37
I/O
-
I/FI
80
GND
16
I/O/FI
-
1I0/FI
-
I/O/FI
-
FO
17
VCCINT
38
110
57
I/FI
81
I/O
-
I/O
39
110
58
I/O/FI
-
FO
18
1I0/FI
-
110
59
I/FI
82
I/O/FI
-
1I0/FI
40
GND
60
I/FI
83
FO
19
1I0/FI
41
1I0/FI
61
I/FI
84
FO
20
GND
-
I/O/FI
62
GND
-
FO
21
GND
42
1I0/FI
63
MR
1
V CC10
22
I/O/FI
43
V CC10
64
I/FI
2
I/O
23
110
44
FO
65
I/FI
3
I/O
24
I/O
45
FO
66
I/FI
4
I/O
25
110
46
FO
67
0
-
I/O
-
110
-
I/O/FI
-
I/FI
5
I/O
26
110
47
FO
68
0
-
1I0/FI
-
110
-
110
-
I/FI
6
GND
27
110
48
FO
69
I/O/FI
-
1I0/FI
28
110
-
110
-
I/FI
7
1I0/FI
-
GND
49
FO
70
GND
8
1I0/FI
29
110
50
110
-
I/O/FI
-
110
-
I/O
-
FO
71
O/FCLKO
9
I/O/FI
30
I/O
51
110
-
0
-
I/O
-
I/O
-
FO
72
0/FCLK1
10
I/O
31
110
52
VCCINT
73
FO
-
I/O
-
I/O/FI
-
I/O
-
I/O/FI
11
110
32
1I0/FI
53
O/CEO
74
GND
-
GND
-
GND
-
GND
-
3-58
XC73108 144-Pin PGA Pinouts
PGA
Pin
Description Pin
No.
V CC10
03
0/CE1
C2
FO
B1
O/FOEO
02
0
E3
0/FOE1
C1
0
E2
01
VCCINTNpp
IfFI
F3
IIOIFI
F2
IIFI
E1
IIOIFI
G2
IIFI
G3
IIOIFI
F1
IIFI
G1
IfFI
H2
IIFI
H1
GND
H3
MR
J3
IIFI
J1
IIFI
K1
IIFI
J2
K2
0
IIFI
K3
0
L1
IIFI
L2
IIOIFI
M1
IIFI
N1
GND
M2
IIOIFI
L3
O/FCLKO
N2
0
P1
0/FCLK1
M3
FO
N3
IIOIFI
P2
GND
R1
Pin
Description
V CC10
0/FCLK2
1/0
FO
1/0
VCCINT
FO
1/0
FO
1/0
GND
FO
1/0
FO
IIOIFI
FO
FO
FO
V CC10
1/0
1/0
1/0
1/0
1/0
IIOIFI
GND
IIOIFI
IIOIFI
IIOIFI
1/0
IIOIFI
1/0
1/0
1/0
1/0
GND
PGA
Pin
No.
N4
P3
R2
P4
N5
R3
P5
R4
N6
P6
R5
P7
N7
R6
R7
P8
R8
N8
N9
R9
R10
P9
P10
N10
R11
P11
R12
R13
P12
N11
P13
R14
N12
N13
P14
R15
Pin
Description
V CC10
1/0
1/0
1/0
1/0
1/0
1/0
1/0
IIOIFI
1/0
IIOIFI
VCCINT
1/0
IIOIFI
IIOIFI
IIOIFI
GND
GND
IIOIFI
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
GND
1/0
1/0
1/0
1/0
I/O
II0IFi
IIOIFI
GND
3-59
PGA
Pin
No.
M13
N14
P15
M14
L13
N15
L14
M15
K13
K14
L15
J14
J13
K15
J15
H14
H15
H13
G13
G15
F15
G14
F14
F13
E15
E14
015
C15
014
E13
C14
B15
013
C13
B14
A15
Pin
Description
V CC10
IIOIFI
1/0
IIOIFI
IIOIFI
1/0
GND
IIOIFI
IIOIFI
1/0
IIOIFI
1/0
1/0
1/0
GND
IIOIFI
IIOIFI
IIOIFI
V CC10
FO
FO
FO
IIOIFI
FO
1/0
FO
PGA
Pin
No.
C12
B13
A14
B12
C11
A13
B11
A12
C10
B10
A11
B9
C9
A10
A9
B8
A8
C8
C7
A7
A6
B7
B6
C6
A5
B5
1/0
A4
FO
A3
B4
C5
B3
1/0
FO
110
FO
VCCINT
1/0
O/CEO
GND
A2
C4
C3
B2
A1
II
XC73108 Programmable Logic Device
Ordering Information
J TLL
XC73108 -12 PC 84 C
Dev"" Type ]
Speed
Tempe,aM" Range
Number of Pins
Package Type
Speed Options
-12
12 ns pin-to-pin delay
-15
15 ns pin-to-pin delay
-20
20 ns pin-to-pin delay
Packaging Options
PC84 84-Pin Plastic Leaded Chip Carrier
WC84 84-Pin Windowed Ceramic Leaded ¥Chip Carrier
PG144 144-Pin Windowed Pin-Grid-Array
Temperature Options
C
Commercial
I
Industrial
0° C to 70° C
-40° C to 85° C
3-60
SECTION 4
1
Programmable Logic Devices
2
FPGA Product Descriptions and Specifications
3
EPLD Product Descriptions and Specifications
4
Packages and Thermal Characteristics
5
Quality, Testing and Reliability
6
Technical Support
7
Development Systems
8
Applications
9
The Best of XCELL
10 Index, Sales Offices
Packages and
Thermal Characteristics
Package Options ................................................................................. 4-1
1/0 Pins Per Package .......................................................................... 4-1
Physical Dimensions ........................................................................... 4-2
Package Thermal Characterization Methods & Conditions ................ .4-18
Thermal Resistance ............................................................................ 4-19
Component Average Mass by Package Type .................................... .4-22
Plastic Surface Mount Components .................................................... 4-23
Sockets ...............................................................................................4-25
Packages and
Thermal Characteristics
Package Options
Surface Mount
Standard
Lead Pitch
Body
Temp Options
Ordering Code
EPLDFamily
FPGAFamily
Through-hole
PLCC
PQFP
TQFP
CQFP
PGA
JEDEC
50 mil
Plastic
C,I
PC
EIAJ
Plastic
C,I
PO
EIAJ
0.5mm
Plastic
C,I
TO
JEDEC
25 mil
Ceramic
M,B
CB
JEDEC
100 mil
Ceramic/Plastic
C,I,M,B
PG,PP
160
100
84
84,144
100
68
84
XC72361XC7236A
XC7272A
XC731 08
0.6510.5mm
44
68,84
84
XC2064
XC2018
44,68
44,68,84
XC30201X.C3120
XC30301X.C3130
XC3042JXC3142
XC30641XC3164
XC309OIX.C3190
XC3195
68,84
44,68,84
84
84
84
84
100
100
100
160
160,208
160,208
84
84
100
100
208
160
160,208
240
160,208
208
208
208,240
XC4002A
XC4003A
XC4003H
XC4OO4IXC4004A
XC4005IXC4005A
XC4005H
XC4006
XC4008
XC4010
XC4013
84
84
84
84
84,132
132
175
175,223
100
100
100
100
164
120
120
191
120
156
223
156
191
191
223
100
100
100
164
196
196
II
X3246
1/0 Pins Per Packages
Package
44
68
84
100
120 132 144 156 160 164 175 191 196 208 223 240
MaxK> PC,WC PC,PG,WC PC,PG,WC PQ,TQ,CB PG PG PG PG PQ CB PG PG CB PQ PG PQ
EPLDFamily
XC72361XC7236A
XC7272A
XC731 08
36
72
120
36
XC2064
XC2018
58
74
34
34
58
64
XC30201X.C3120
XC30301X.C3130
XC3042JXC3142
XC30641XC3164
XC309OlXC3190
XC3195
64
80
34
58
58
56
72
72
84
120
120
FPGAFamily
XC4OO2A
XC4003A
XC4003H
XC4004A
XC4OO5/XC4005A
XC4005H
XC4006
XC4008
XC4010
XC4013
74
74 (monly)
64
74
74
70
70
70
64
80
82
64
80
160
61
61
64
77
96
61
61
96
120
144
176
112
192
128
144
160
192
96
110
120
138 142 144
138
144
144
176 176
64
80
160
95
96
112 112 112
125 128
160
112
192 192
128
144 144 144
160 160 160
160 192 192
)(3247
4-1
Packages and Thermal Characteristics
Physical Dimensions
-1
~===r=;==r=r===j=r~Jo.~
Pin11D
(Optional)
Dimensions in Inches
Top View
1
o.~
0.t8
Min
Max
I
I
0.t2
Min
I
0.06 Typ
I---
0.325.0.025
-I
O.tOTyp
X3077
Side View
S-Pin Plastic DIP (POS)
0.~5R~
Dimensions in Inches
O.tOOTyp
jr-+--+-------,
0.150
0.170
U
._Jl
0.056 • 0.005
-+I
i-
-+I i - 0.018 • 0.002
Side View
S-Pin Ceramic DIP
X3065
(~~S)
4-2
h
_0.196_
0.189
1
8
0.244
0.230
j
Pin 110
Dimensions in Inches
Lead Pitch 50 Mil
TOp View
OT~S;~---~
0.068
~~~r--
~
=~
0.061
___0_.06.1
O~'O_~____~~L______~
la.Ol0
Side View
0.004
III
8-Pin Small Outline (S08)
Pin 110
(Either Pos.)
0.045 ± 0.003
Chamfer
r
---r-1 r;::
0.050 Typ
Non-Cumulative
-f---Fl
~if-;'_-'-_~L"L==L",L_L_U_-'_L
8
0.015 ChamferTyp
r40.353± 0.003
1~0.353±000~~1
Dimensions in Inches
Lead Pitch 50 Mil
-O.390Sq---------....
Top View
I
0.170
r~-=-OO-.00-4"'---
l:.£:J
I
I
I
0.015
-0.320-
-0.320--
I
I
[0.020
)(3041
SldeVlew
20-Pin Plastic PLCC (PC20)
4-3
Packages and Thermal Characteristics
Pin 110
(EHher Pos.)
_I 1-
O.05OTyp
40Non-Cumulative
.-~~-~on~~C)~DL~~
o
39
0.690
29
1 18
28
1,,,..- - - - - 0 . 6 5 3 . 0 . 0 0 3 - - - _•
I
. . - - - - - - 0 . 6 9 0 - - - - -.... (
Top View
Dimensions in Inches
Lead Pitch 50 Mil
biMAiiiiJUiM~'010
~r-=c:-_TO:-.O 4,.,. "r- I.
Lft;::j
0.620
Side View
X3038
44-Pin Plastic PLCC (PC44)
EPROM Window
0.350Dia
1,-'---0.650
Dimensions in Inches
lead Pitch 50 Mil
(~::~)--
1
..- - - - - 0 . 6 9 0 (g:~:~)
----..
Top View
0.172
(~:~~)t
bruuuuuuuuuuJr--------=:..:;r-(&m)
,I
I,..
----0.610(~:~)---...
Side View
44·Pin Windowed Ceramic CLCC (WC44)
4-4
tt ~_c:::.c
_ 0.006
~
-...
X3039
Pin 110
0.22±O.05
(0.007 ±O.OO4)
1
I~_16
Dimensions are in millimeters
Dimensions in parenthesis are in inches
Lead Pnch O.SO mm (0.020)
X3163
II
64-Pin VQFP (VQ64)
0.045 x 45°
1 LrPin11D 61
C>
0.990
0.005
±
0.954
±O.OO4
v
a',ll
11.,+'-----0.954.0.004-------"·
-----0.990 .0.005-----0170
.00050
Top View
~_0~5
1C -j-P'--,----_.--.t Lo045
::::J II ..
r:::::-T::"":":-:r----
~
Dimensions in Inches
lead Pitch 50 Mil
11+0018 0800
- - - - - 0 920±0010
Side View
68-Pin Plastic PLCC (PC68)
4-5
,11-L0020
II:
X3042
Packages and Thermal Characteristics
EPROM Window
Pin 110
0.390 Dia
61
-~-~~~~~~
1 "
·
0.990
(8:~~~)
0.950
( 0.930)
0.965
26
-11~.'C2"'-7~,=-~~~r_""0'C'9"'50r(6'8:'D~"'5)'M-"'-'D-"':...'M_a=_""-",""43;',11
-<----- 0.990 (8:~~)
Top View
44
Dimensions in Inches
Lead Pitch 50 Mil
0.172
( 0.155)
r -_ _ _ _ _ _ _ _ _ _ _~0.~190 ~
I.=~~~~~~~~~~~~~
I
... 11. 0.031 ~ 0.003
+_---
0.800 REF - - - -.....
+ - - - - - 0.910 (8:~8),-----1
Side View
lt~
Ll±J
(8:m)
X3043
68-Pin Windowed CLCC (WC68)
1-----1.000 .0.012 - - - - + I
i"'1'~----1.100 .0.012 Sq ----.~I
H
=
G
F
0.605 Sq
E
o
C
f-(;lf-ffK+l-
B~rG~~~fH~~f»~~~~
Pin11D~
A
2
9
3
10 11
8ottomVJew
Top View
"~l'ilfnni~H··"·
0.018 ± 0.002 Dia
0.055 Dia Max
Side View
68-Pin Ceramic PGA (PG68)
4-6
Chamfer
(4 places)
~
NOTE: Index Pin Mayor May Not Be
Electrically Connected to Pin C2
Dimensions in Inches
X3044
0.045 x 45
Pin lID
0
11
75
.';IT~2O~74
1.154
±O.OO4
_U
1 33
1J..o:::'-----1.154.°.004
1
~!:~~!~~~~ ~jfheS
JUUUUUU
53
~1 54
v.
1.190 ± 0 . 0 0 5 .
Top View
f
~_
0028
-1,0045
0.175
±O.010
r----r~----------------~~
TTI
. tL
.---.------.---'-+----.-
~JI-0.Q18
1000Typ
.1
~L
0.045
O.020
J.
1 120 ± 0 010
Side View
><3045
84-Pin Plastic PLCC (PC84)
r/'
EPROM Window
0.450Dia
Pin 110
75
74
1.190
(1:1~~)
1.150
(1130)
I~
-----11~
••3-3----1.150
J-o._--
(1:1m:::::!11
54
Dimensions in Inches
lead Pitch 50 Mil
----l.l90(m~)~
Top View
0.172
r-----------v.>~
( 0.155)
0.190
~-1...--.-r-=--r:-:-:-:-,
~
...II-O.019.0.002
• 1
~
1.000 Ref
(1:m)
1.110
Side View
84-Pin Windowed CLCC (WC84)
4-7
t
.,.
(0.090)
0.110
X3046
II
Packages and Thermal Characteristics
0.100Typ
1.000 ± 0.012
- fK
H
IT\ IT\
IT\ IT\
;t;t
;t;t
~'t' 't'
.100
,0
Typ
't' 't'~
~~
~~ ~
1.100 > 0.012 Sq
t
H
I
~~
G
1.000
F
0.805 Sq
±O.O 12
E
D
7
~~ ~
C
TypO.070
XPin
f
J"
B
%
't"
A
1
2
3
4
-E ~
Dia I 0.08 Max
J" J"~ ~
~
%%
't" 't"
5
6
7
9
8
10
1
I
11
Top View
BoHomView
Pin 1 10
0.095
.~:~~~ ni If If If If If i IfItt- :,~o
0.018 ±O.002 Dia
--.......11..
0.055 Dia Max
Side View
NOTE: Index Pin Mayor May Not Be
Electrically Connected to Pin C2
Dimensions in Inches
X3047
84-Pin Ceramic PGA (PG84)
0.100Typ
--
K
H
1.000 ± 0.012
l:l:
100
,~.yp
t
l:l:
'H fr't' 't'
~ fr
't' 't'~
~
.~ ~
G
1.000
±O.O 12
E
D
C
7
~~
Typ 0.070
XPin
H
J" J"~ H
Dia/ojoBMax
J"
B
;t
A
2
3
4
.,I
"'1'----1.100>0.012 S q - - - -•
~
0
1
0.600 Sq
Seal Are aUmit
1
;t;t
5
6
7
8
9
@.
10 11
TopYlew
Bottom View
/
Pin 110
NOTE; Index Pin Mayor May Not Be
Electrically Connected to Pin C2
Dimensions in Inches
X2976
84-Pin Windowed PGA (PG84)
4-8
----.-----~-.~--
,;-7'
Dimensions in Inches
Lead Pitch 25.6 Mil
Top View
L;J\
.-::-r--.-
Leli@
l:.£=I
[JJUUUUUUUUUUUUUUUUUUUUUUUUUU
0.057
±
0.006
) \\
0118;0.006
'-'=--l Seating Plane
Side View
X3048
100-Pin Plastic PQFP (PQ100)
II
~'-m.~
75
~
Ejector Pin Mark
Optional (3 Places)
14.0.0.1
Sq
(0.551 .0.002)
~;:;:;:;:;: ; :; ;:;:; :;:;:;:;O~U
25
--JlO.18±O.1
Dimensions in Millimeters
Dimensions in Parenthesis are in Inches
Lead Pitch 0.50 mm
(0.007.0.002)
Top View
(0.055.0.004)
~
___________
1.4±O.1
~
~
~O.13±O.05
,.lL (UUUUUUUUUUUUUUUUUUUUUUUUUJ '\s:;'~'.~:
(oo-!o~-J I
Side View
O.S±O.2--J
(0.020 • 0.005)
100-Pin Plastic TQFP (TQ100)
4-9
t
X3066
Packages and Thermal Characteristics
75
51
om.
76
14.0
~:; : ; : ;: :Pinl: ;: ; :; ID~;:; :;:;:;O;: ; : ; :, ~r
100
II
25
Dimensions in Millimeters
Dimensions in Parenthesis are in Inches
Lead Pitch 0.50 mm
---...j j..- 0.18± 0.1
1.:.1£
0,95
(0.007 ± 0.004)
(0.044)~
~t~r---------'
0"_12"
LSt8nd-Off
0.05 - 0.20 (0.002-0.007)
100-Pin Plastic VQFP (VQ100)
~~0m
0.070 Dia Typ
(120 Places)
Stand'()ff Pin
D
(4 Places)
B
A
0.040 ± 0.010 X 45° --.if
Chamfer Pin #1 Side
000
iF====9000
000
1.360
000
-----+----000
±0.014Sq
000 ±~~2
000
000
000
000000000000
0 000000000@0
000000000000
1
2
3
4
5
6
7
8
9
10
11
12
13
Bottom View
~
I
0.050
J
0.030 ± 0.01 0 X 45°
'0.018±0.002-J1Au Plated Kovar
\
L-
0.091
0 .130 ±0.010
' - - O.OOSR Typ
StdeVlew
120-Pin Ceramic PGA (PG120)
4-10
Gold Plate
TopVtew
Places)
Jl~±0.009
(4PI~~e~~lW!
1mtiii 1f TIIT*l
0.025XO.050~ L
0.010 X 45 0
I
Chamfer
(3
;
"TOP Edge Chamfer
Dimensions in Inches
PinllD
(TopSide)
O.l00Typ
o 000000
0.070
N000 000000
±0.005
DlaTyp
M000 000000
L 000 r-------.....;-'.;:.L.I.;;D:;J..+-,
K 000
000
J 000
000 1
H 000 ___. ___ 000
0.645
G 000
000 "0.\006
F000
000
E000
000
0000
c00000000000000
B00000000000000
AG0000000000000
1
I
0.070
±0.01 Sq
1.460
"O.Ol5Sq
---....!.
1
2
3
4
5
6
7
8
9
10 11 12 13 14
_ - -_ _ 1.3OOTyp _ _ _ __
Oinensions In Inches
"::~Il-l
:to.010
_
-0.085
_View
±0.009
X3051
132-Pin Plastic PGA (PP132)
Pin Kovar
Stand-Off Pin
90112 Sn·Pb
Seider Plated
(4P-')
000000000000
N00000000000000
M00000000000000
L 000
000
K000
000
J 000
000
H 000
+
000
G 000
BIaCkLzed
000
F 000
A1uml~umLId
000
E 000
I
000
o 000
I
000
c00000000000000
B00000000000000
A 00000000000000
0.040" O.OlQ . . /
X 45° (4 Places)
1
2
I.
3
4
5
6
7
8
9
!.~=I=I---l
0.018.1
1.460
"O.Ol5Sq
0.050
,,0.004.
__
Dimensions In Inches
Lead Pilch 0.50 mm
BoIIomVIew
_
:1:0.002
10 11 12 13 14
1.300----_1
l
"~:~:~III
:t:O.010-
-
-
-0.070
Side View
X3052
132-Pin Ceramic CQFP (PG132)
4-11
II
Packages and Thermal Characteristics
Pin 110
108
20.0
(0.787) Sq
22.0
(0.866) Sq
-~----+----
36
72
(8 ".~,.~
Places)
,~.~
1.35
(0.053)
0.10~.05
(0.004 ~.002)
Dimensions are in millimeters
Dimensions in parenthesis are in inches
X3164
Lead Pitch 0.5 mm (0.020)
144-Pin Plastic TOFP (TQ144)
1-"\'-----------
1.575.0.016Sq
----------.~\
O.l00Typ
000000
0000000
0000000
000
000
000
000
0.070 Dia Typ
Window
0.393 Nom
H**~~~--------~--------~~~Ht
G
F
E
D
C
B
A
Pin #1 Index
000
000
000
000
000
000
0000
000
0000000 0000000
0000000 0000000
~000000 000000@l
1
2
3
4
5
6
7
8
9
0.030.0.010 X 45'
/
o
Chamfer (4 Places)
10 11 12 13 14 15
Bottom View
Stand-Off Pin
(4 Places)
O'050Dla )~~rru it i ini'i~:~
0.018.0002
Plated Kovar
-.II..-
Top View
0.060Dia
Index Mark
(Plaling Oplion)
Dimensions in Inches
Lo.180.0010
Side View
X3160
144-Pin Ceramic PGA (PG144)
4-12
Stand..()ff Pin
(4 Places)
T ~lP00000010000000
R0000000~00000000
~=
P0000000000000000~~~~
000
"""""" TypO,.
M000
000
L000
000
K000
000
~~0
+
0~ 0.795
1.660
H 000
000 .0.OO9Sq .0.016Sq
G 000
000
1.500
F000
000
E000
000
0000
~~s
C 000000000000000~r'--oielec1riC
B 00000000i000 0 0000
Coal
A l________ 0000
J 0000
'0000
H 000
000
G 000
000
F 000
000
E 000
000
o 0000
00
0000
00000000000000000
00000000000000S0
0000000000000000
0
Pin #1 Side
12
Oielectric
Coat
15
1.860
o 0.019 Sq
1.700
Tp
" - Top Edge Chamfer'
0.010 X 45 Typ
0
o
718~Chamfer
/
0.030 0 0.010 X 45
(3 Places)
Bottom View
0
Top View
Gold Plate
Pin #1 Index
Top Side
0.050
00.010~
, JI;;;;;;:;:;~;;:;;;~;;;;;;;;;;::;;:;:;rl=;:~r-
0.025Min~
(4PI~=.J~I@1 ~ ~ ~ ~ ~ ~ U~ ~ II lililt±= I
0.050 X 0.025 _
_
0.018 0 0.002 -11-
Au Plated Kovar
0.090
0 0.010
Dimensions in Inches
' - 0.005 R Typ L~· ~3~ 0
Side View
X3004
II
191-Pin Ceramic PGA (PG191)
, - - - - - - - 0.14600.008
1--------1.20500.010 S q - - - - - - - I
1------1.10200.004 Sq - - - - 0.020 0 0.004
-------I.OO4Ref
-----~
0.051 Ref
156
157
104
206
53
Pin11Q
52
Top View
Dimensions in Inches
lead Pitch 0.020
208-Pin Plastic PQFP (PQ208)
4-15
><3060
Packages and Thermal Characteristics
~-----.
1 - - - - - - - - 1.205 ±0.008 Sq
0.145 ±0.070
-------1
-----+,
1 - - - - - - 1.088 ± 0.003 Sq
104
53
52
Top View
Dimensions in Inches
lead Pitch 0.20
X3061
208-Pin Metal MQFP (MQ208)
0.070 Dia Typ
(223 Places)
1.880
±0.019Sq
1.700
Typ
Stand-Off Pin
EE
" - Top Edge Chamfer
0.010 X 450 TYP
(4 Places)
Bottom View
Top View
0.050
±0.010
008
,
(4 Places)
0.
.J
t
0.050 X 0.025 _ _
0.018±0.002_1I_
Au Plated Kovar
Top Side
I]~0.095
.
~II ~ ~ H~ U:U u nilE
0.025 Min"
o
Gold Plate
Pin #1 Index
t
Dimensions in Inches
L o.130
\
' - - 0.005 R Typ
± 0.010
Side View
X3057
223-Pin Ceramic PGA (PG223)
4-16
240
Pin 110
181
#lPin
1.260
1.362
( 1.256)
1.264
(1.352)
1.372
120
61
Top View
II
240-Pin Plastic PQFP (PQ240)
Pin 110.
,
240
181
~180
#lPin
~
1.162
0.020
esC.
1.24
1.362
~2)
2
C·1.25
(1.354)
1.370
L
t
18~
60
61
120
Top View
Dimensions in Inches
~r----------------------'
~
.p::- JJMll.IIIM.lll
. . . . . ._\.~45+
( 0.125)
0.130
.Jl (0.007)
0.108
.J l
Side View
240-Pin Metal MQFP (MQ240)
4-17
(0.140)
0.165
0.020 (0.016)
0.024
X3161
Packages and Thermal Characteristics
Package Thermal Characterization Methods &
Conditions
Method and Calibration
Xilinx uses the indirect electrical method for thermalresistance characterization of packages. The forwardvoltage drop of an isolated diode residing on a special test
die is calibrated at a constant forcing current of 0.520 mA
with respect to temperature over a correlation temperature
range of 22°C to 125°C. The calibrated device is then
mounted in an appropriate environment, e.g. still air,
forced convection, FC-40, etc. Power (Pd) is applied to the
device through diffused resistors on the same thermal die;
usually between 0.5 to 4 W is applied, depending on the
package. The resulting rise in junction temperature (T ) is
monitored with the forward-voltage drop of the pre-dalibrated diode. Typically, three identical samples are tested
at each data pOint. The reproducibility error is close to 6%.
Junction-to-Ambient Measurement - e
d
JA
measure on a 4.5" x 6.0" x .0625" (11.4 cm x
15.2 cm x 0.16 cm) FR-4 board. The data may be taken
with the package in a socket or, for packages used
primarily for surface mount, with the package mounted
directly on traces on the FR-4 board. The copper-trace
density is limited to the pads needed for the leads and the
10 or so traces required for signal conditioning and
measurement. The board is mounted in a cylindrical
enclosure and data is taken at the prevailing temperature
and pressure- between 22°C and 25°C ambient (T ). The
power application and signal monitoring proceelin the
same way as the eJC measurement with enclosure
(ambient) thermocouple substituted for the fluid
thermocouple and two extra thermocouples brought in to
monitor room and board temperatures. The junction-toambient thermal resistance is calculated as follows:
eJA .IS
e
Junction-to-Case Measurement '
t'lon-to-case ch
'
JCmeasured in a 3M
Th e Junc
aractenzation
is
Flourinert (FC-40) isothermal circulating fluid stabilized at
25°C. During the measurement, the Device Under Test
(DUT) is completely immersed in the fluid; initial stable
conditions are recorded, then Pd is applied. Case temperature (Tc) is measured at the primary heat-flow path of
the particular package. Junction temperature (T ) is calculated from the diode forward-voltage drop frori the initial
condition before power is applied, i.e.
eJc =
The setup lends itself to the application of various airflow
velocities from 0 - 800 Linear Feet per Minute (LFM), i.e.,
4.06 mls. Since the board selection (copper trace
density, mounting distance, board thermal conductivity
etc) affects the results of the thermal resistance, the data
from these tests shall always be qualified with the boardmounting information.
o-
Data Acquisition and Package Thermal Database
Data for a package type is gathered for various die sizes,
power levels, cooling modes (airflow and sometimes heatsink effects) with an IBM-PC based Data Acquisition and
Control System (DAS). The system controls and conditions the the power supplies and other anCillary equipment
for a hands-free data taking. Different custom-tailored
setups within the DAS software are used to run calibration,
eJA, eJC' fan test as well as power-effects characteristics of
a package. A package is completely characterized with
respect to the major variables that influence the thermal
resistance. A database is generated for the package.
From the database, thermal resistance data is interpolated
as typical values for the individual Xilinx devices that are
assembled in the characterized package. (See data in
following table.)
TJ - Tc
~
e
The junction-to-isothermal-fluid measurement JL can
also be calculated from the above data as follows:
TJ - TL
eJc = Pd
where T L = isothermal fluid temperature.
The lalter data is considered as the ideal eJA data for the
package that can be obtained with the most efficient heat
removal scheme-airflow, copper-clad board, heat sink or
some combination of these. Since this is not a widely used
parameter in the industry, and it is not very realistic for
normal application of Xilinx packages, the data are not
published. The thermal lab keeps such data for package
comparisons.
4-18
I:.
!NX
"1
V 'IL)i~
_l'%,,~
Thermal Resistance Data
Product and Package
(Socketed unless noted)
Product and Package
9JAoCIW
9JCoCIW
(Socketed unless noted)
9JAoCIW
9JCoCIW
XC1718D DD8
120.5
8.5
XC2018 PC68
40.7
8.1
XC1718D PC20
84.3
26.6
XC2018 PC84
35.1
6.7
XC1718D PD8
80.1
22.9
XC2018 PG84
35.1
6.0
XC1718L DD8
120.5
8.5
XC2018 PG84
38.4
6.9
XC1718L PC20
84.3
26.6
XC2018 PG84
38.4
9.2
XC1718L PD8
80.1
22.9
XC2018L PG84
38.4
6.9
XC1736ACD8
112.0
7.1
XC2018L PG84
38.4
9.2
XC1736A DD8
114.6
6.5
XC2064CD48
38.6
4.8
XC1736A PC20
81.0
20.5
XC2064 PC68
42.1
9.5
XC2064 PC84
36.7
7.9
XC1736A PD8
80.5
19.0
XC1736A PD8
135.0
28.0
XC1736D DD8
120.5
8.5
XC1736D PC20
84.3
26.6
XC1736D PD8
80.1
22.9
XC1736L DD8
120.5
8.5
XC2064 PD48
43.2
11.6
XC2064 PG84
36.7
6.7
XC2318 PC68
42.4
9.9
XC2318 PC84
37.0
8.2
XC3020 CQ100
45.3
7.5
8.3
6.9
XC1736L PC20
84.3
26.6
XC3020 PC68
40.9
XC1736L PD8
80.1
22.9
XC3020 PC84
35.3
XC1765 CD8
108.4
6.4
XC3020 PG84
35.4
6.1
XC3020 PQ100
67.6
9.3
XC3020 PQ100
75.3
XC1765 DD8
111.0
5.4
XC1765 PC20
79.0
17.4
XC1765 PD8
75.0
15.0
XC1765D DD8
120.5
8.5
XC1765D PC20
84.3
26.6
XC1765D PD8
80.1
22.9
XC1765L DD8
120.5
8.5
XC1765L PC20
84.3
26.6
XC1765L PD8
80.1
22.9
XC17128 DD8
106.5
4.4
XC17128 PC20
76.5
14.2
XC17128 PD8
72.6
12.2
4-19
XC3030 PC44
43.6
10.7
XC3030 PC68
39.4
7.0
XC3030 PC84
33.7
5.7
XC3030 PG84
33.7
5.4
XC3030 PQ100
62.7
6.8
XC3030 PQ100
71.1
I
Packages and Thermal Characteristics
Thermal Resistance Data (continued)
Product and Package
(Socketed unless noted)
9JAoC/w
9JCoC/W
Product and Package
(Socketed unless noted)
9JAoC/W
9JCoC/W
XC3042 CQ1 00
44.2
5.6
XC3120 CQ100
45.7
XC3042 PC84
32.3
4.8
XC3120 PC68
41.6
8.1
9.0
XC3042 PG132
26.5
2.5
XC3120 PC84
36.2
7.5
XC3042 PG84
32.3
4.9
XC3120 PG84
36.5
6.2
XC3042 PP132
33.7
2.1
XC3120 PQ100
70.0
10.7
XC3042 PQ100
58.2
5.0
XC3120 PQ100
77.9
XC3042 PQ100
68.1
XC3130 PC44
44.9
11.0
XC3064 PC84
30.5
3.6
XC3130 PC68
40.2
7.7
XC3064 PG132
24.1
2.0
XC3130 PC84
34.6
6.4
XC3064 PG84
30.5
4.4
XC3130 PG84
34.7
5.5
XC3064 PP132
32.9
1.9
XC3130 PQ100
65.4
8.1
XC3064 PQ160
33.0
4.4
XC3130 PQ100
73.2
XC3090 CB164
26.3
1.8
XC3142 CQ100
44.5
6.2
5.4
XC3090 CQ164
32.9
1.5
XC3142 PC84
33.1
XC3090 PC84
29.1
2.8
XC3142 PG132
27.7
2.7
XC3090 PG175
16.4
0.9
XC3142 PG84
33.3
5.0
XC3090 PP175
21.7
1.6
XC3142 PP132
42.6
2.8
XC3090 PQ160
31.8
3.0
XC3142 PQ100
61.1
6.1
XC3090 PQ208
30.5
2.6
XC3142 PQ100
69.9
4-20
XC3164 PC84
31.4
4.2
XC3164 PG132
25.3
2.3
XC3164 PG84
31.4
4.5
XC3164 PP132
41.6
2.5
XC3164 PQ160
33.8
5.2
Thermal Resistance Data (continued)
Product and Package
(Socketed unless noted)
9JAoC/w
XC3190 CB164
26.3
XC3190 CQ164
XC3190 PC84
Product and Package
(Socketed unless noted)
9JCoC/W
2.1
XC4002A PC84
34.2
2.6
29.8
3.3
XC3190 PG175
24.1
XC3190 PP175
9JAoC/W
9JC oC/W
32.9
5.2
XC4002A PQ100
60.3
5.8
XC4003 PC84
31.2
4.1
2.1
XC4003 PQ100
54.6
3.9
32.0
3.0
XC4003A PCB4
31.7
4.4
XC3190 PQ160
32.5
3.B
XC4003A PQ100
56.2
4.4
XC3190 PQ20B
31.2
3.B
XC4004A PC84
30.3
3.5
XC3195 PCB4
27.9
2.2
XC4005 PCB4
2B.5
2.5
XC3195 PQ160
30.5
1.7
XC4005 PQ160-HS
21.5
1.5
XC3195 PQ20B
29.2
1.7
XC4005 PQ20B-HS
22.0
1.3
XC3330 PC44
45.1
12.9
XC4010 PQ20B-HS
21.5
1.3
XC4305 PCB4
32.3
4.B
XC4305 PQ160
34.5
5.9
XC7236 PC44
44.1
12.2
XC3330 PC68
42.6
10.1
XC3330 PCB4
37.2
B.3
XC3330 PQ100
72.B
12.5
XC3330 PQ100
B1.5
XC7236WC44
45.3
7.4
XC3342 PCB4
36.0
7.4
XC7272 PC6B
39.1
6.B
XC3342 PQ100
69.6
10.4
XC7272 PCB4
33.3
5.5
3.3
XC3342 PQ100
77.4
XC7272 WC84
40.3
XC3390 PCB4
33.0
5.3
XC7272WGB4
33.2
5.1
XC3390 PP132
34.0
2.2
XC7310B PCB4
32.2
4.7
XC3390 PP175
27.1
1.B
XC7310B PG144
22.5
3.5
XC3390 PQ160
35.0
6.5
XC7310B PQ160
34.4
5.9
XC73108 WCB4
3B.4
2.4
Measured under the following conditions:
9Jc : Device immersed in FC-40 at 25"C
9JA : Device in still air at 22 to 25"C
Devices were mounted in sockets, then mounted on a
6" by 4.5" FR-4 board.
PQ100 packages were surface-mounted onto traces on
a 6" by 4.5" FR-4 board.
For further information on measuring techniques, see
the Xilinx Thermal Characterization Specification
(MAC0034), or contact Xilinx Package Engineering.
4-21
I
Packages and Thermal Characteristics
Component Average Mass by Package Type
Package Description
CB100-1
CB100-2
CB164-1
CB164-2
CB196
CQ100
CQ164
DD8
MQ208
MQ240
PC20
PC44
PC68
PC84
PD48
PD8
PG120
PG132
PG156
PG175
PG175
PG191
PG223
PG68
PG84
PP132
PP156
PP175
PP175
PP175
PQ100
PQ160
Mass(grams)
NCTB - Top Brazed Ceramic -4K
NCTB - Top Brazed Ceramic -3K
NCTB - Top Brazed Ceramic -3K
NCTB - Top Brazed Ceramic -4K
NCTB - Top Brazed Ceramic
0.025" Unformed CERQuad
0.025" Unformed CERQuad
0.300 CERDip
Metal Quad (EIAJ 28 mm)
32X32mm
PLCC - JEDEC 0.050"
PLCC - JEDEC 0.050"
PLCC - JEDEC 0.050"
PLCC - JEDEC 0.050"
Dual In Line Plastic - 0.600"
Dual In Line Plastic - 0.300"
PGA 13 X 13 Matrix Ceramic
PGA 14 X 14 Matrix Ceramic
PGA 16 X 16 Matrix Ceramic
Heat Sink -16X16 Matrix KCW10
No Heat Sink - 16X16 Matrix
PGA 18 X 18 Matrix Ceramic
PGA 18 X 18 Matrix Ceramic
Cav. Up CPGA 11 X 11 Matrix
Cav. Up CPGA 11 X 11 Matrix
Plastic PGA 14 X 14 Matrix
PPGA 16 X 16 Matrix
16 X 16 PPGA 2 Tier - Hardware Ver.
16 X 16 PPGA Exposed Copper Ver.
16 X 16 PPGA Buried Copper Ver.
EIAJ - Matrix (14X20)
EIAJ - Matrix 1.6 mm Form
10.80
10.5
11.20
11.50
15.30
3.60
8.35
1.07
6.10
0.75
1.20
4.80
6.80
7.90
0.52
11.50
11.75
17.10
28.40
17.70
21.80
26.00
6.95
7.25
8.10
10.60
10.00
9.90
Package
Description
Mass(grams)
PQ208
PQ240
PQ256
S08
TQ100
TQ144
TQ176
VQ100
VQ64
WC44
WC68
WC84
WG84
WG144
EIAJ - 28 mm BODY 1.3 mm Form
32X32mm
EIAJ - 40 X 28 Metric
SOIC Narrow 0.150 Body
Thin QFP 1.4 mm thick
20 X 20 mm 1.4 mm thick
24 X 24 mm 11.4 mm thick
14 X 14 mm 1.0 mm thick
10 X 10 mm 1.0 mm thick
Windowed CERQuad - JEDEC
Windowed CERQuad - JEDEC
Windowed CERQuad - JEDEC
Windowed PGA 11 X 11 Matrix
Windowed PGA 15 X 15 Matrix
5.25
0.08
0.65
0.65
2.85
10.95
10.8
• Data represents average values for typical packages with
typical devices. For accuracy between 7% to 10%, these
numbers will be adequate.
• More precise numbers (below 5% accuracy) for specific
devices may be obtained from Xilinx through a factory
representative.
1.60
5.80
4-22
Plastic Surface Mount Components
Moisture-Induced Cracking During Solder Reflow
The reflow-soldering processes employed in attaching
some plastic surface mount components (PSMC) to circuit
boards expose the components to very high temperatures
and steep temperature gradients. If the component has
absorbed sufficient moisture, the plastic overmold may
crack. The moisture trapped in the encapsulant vaporizes
during the reflow-soldering operation and generates hydrostatic pressure within the package.The pressure may
be sufficient in some package-die combinations to cause
delamination within the package, or worse, an internal or
external crack in the overmold. Cracks in the overmold
allow flux and other contaminants to reach the die area and
subsequently lead to the early failure of these cracked
PSMCs.
Xilinx reliability tests, which include moisture precondition
to 0.12% by package mass, have shown no failures
attributable to the type of failure described herein. However, the cracking conditions have been duplicated in
some package-die combinations under special moisturesaturation conditions. The conditions were part of a general crack-susceptibility characterization to determine what
packages, if any, were likely to experience the failure.
Current findings, confirmed by industry studies, show that
the 20PLCC, 44PLCC and 68PLCC exhibit minimal to no
tendency to moisture-induced cracking. Other packages
have different moisture thresholds for cracking. The important conclusion is that below 0.12% by mass of moisture - corresponding to 168 hours of 30%RH at 85°C none of the Xilinx packages crack.
In view of these findings from the susceptibility studies, it
is necessary to issue special handling precautions for
PSMCs, to be applied prior to reflow soldering operation.
The crack susceptibility of PSMC is affected by several
variables. Among them are the package construction
detail - material, design, geometry, die size, package
thickness, assembly, etc.-, moisture absorbed, the reflow
soldering conditions, etc. One controllable factor is the
level of moisture absorbed by the package prior to reflow.
Xilinx recommends, in line with industry practice, that all
PLCCs, with lead counts above or equal to 44, and all
Plastic Quad Flat Packs (PQFPs) be used dry in surfacemount applications. The recommendation is not applicable to PSMCs intended for use in socket applications.
For the purpose of this note, a package is considered dry
if it has undergone one of the baking schedules listed
below, and has been stored at or below 20% RH before
reflow operation.
Bake schedules:
a.
24 hours at 125 ±5°C, or
b.
16 hours at 150 ±5°C.
4-23
Xilinx Recommendation and Dry Bag Policy
In line with the above recommendation, Xilinx performs dry
bake and dry packing on all PQFP shipments. PLCC
devices can be done on as needed basis. Contact your
Xilinx representative for lead-times, any applicable minimum-order quantities, and pricing. Crack-susceptible
PSMCs that ship out of Xilinx without dry bake carry a
CAUTION statement on the primary shipping form similar
to the Caution Label shown below. Xilinx recommends that
PSMC devices that are not dry baked at Xilinx and are
intended for surface mount be dry baked priorto reflow, per
the instructions on the Caution Label.
Xilinx Dry-Packing Capability
The Xilinx dry-packing program for PQFPs consists of
baking the parts after all electrical testing at 125°C for 24
hours in bakeable trays. For PLCC units, the baking is
done under similar conditions in aluminum tubes, then
transferred to regular shipping forms -tubes or tape.
Baked units in shipping forms are sealed within 24 hours
under controlled environment in special Moisture Barrier
Bags (MBBs).
Enough desiccant pouches are enclosed in the bags to
maintain the content at less than 20% RH for up t012
months from the date of seal. A reversible humidity indicator card (HIC) is enclosed to monitor the internal humidity
level. The loaded bag is then sealed shut under partial
vacuum with an impulse heat sealer. Finally labels are
attached to the MBB to alert the customers of the need for
special handling precautions. Besides the application information found on the bags, the following handling precautions shall be noted.
Handling of Parts in Sealed Bags
Inspection
Note the seal date and verify that the bag has no holes,
tears or punctures that may expose the contents. Review
the content information against the parts ordered. It is
recommended that the bag remain closed until the contents are ready for use.
Storage
The sealed MMB should be stored unopened in a relatively
dry environment of no more than 90% relative humidity
and 40°C. The enclosed HIC is the only verification to show
if the parts have been exposed to moisture or not.
Expiration Date
The seal date is stated on the bag. The expiration date is
12 months from the seal date. If the expiration date has
been exceeded, or if upon opening a bag within its stated
expiration period, the HIC shows humidity over 30%,
proceed as follows. Bake the components per the bake
schedules stated earlier. After baking, any of the following
options may apply.
II
Packages and Thermal Characteristics
Use the parts within 48 hours
Reseal the parts in a MBB within 12 hours after
baking with fresh desiccant pouches and HIC;
Store the baked parts in a controlled cabinet with
less than 20% RH. A desiccator cabinet with
controlled RH would be ideal.
Publication IPC-SM-789. Xilinx characterization confirms
that if the relative humidity in a factory is kept below 60%
with temperature between 25 and 30°C, the parts taken
from the MBB will have acceptable moisture levelS if used
within 48 hours. It is recommended that devices be dry
baked if this floor life is exceeded. The time may be
extended by use of controlled desiccator cabinet for storage on the floor.
Other Conditions
Open the MBB when parts are ready to be used. The bag
may be opened by cutting across the top as close to the
seal as possible. This gives room for possible reseal.
When the bag is opened, follow the guidelines under the
factory-floor-life section to ensure that devices are maintained below the critical moisture levels. Bags opened for
less than an hour (strongly dependent on environment)
may be resealed with the original desiccant and HIC. If the
bag is not resealed immediately, new desiccant or the old
one that has been dried out may be used to reseal,
provided that the factory-floor life has not been exceeded.
Note that the factory-floor life is cumulative. The claybased desiccant pouches used by Xilinx may be dried out
at 120°C ±5°C for 10 to 16 hours. Fresh desiccants may be
purchased from United Desiccant-Gates, USA (Model:
Desi Pack C, 2 unit desiccant in Tyvek bag). Note also that·
the Humidity Indicator Card is reversible and may be
reused.
Obviously, Xilinx devices in various Plastic Surface Mount
packages are not affected in the same way. As stated earlier
some PLCC packages are hardly affected by cracking even
under maximum moisture-saturation conditions. In spite of
this, the Xilinx current floor-life recommendation is for all
PSMCs and is based on data from reliability results on
packages with predetermined moisture levels of 0.12%. In
general, irrespective of factory floor conditions, Xilinx recommends that devices be dried out if the level of moisture
in the package exceeds 0.12% by mass of package. If
factory floor conditions are expected to exceed the 30°C/
60% RH, please consult Xilinx for more information.
CAUTION
THESE DEVICES REQUIRE BAKING
THE ENCLOSED COMPONENTS ARE SENSITIVE TO MOISTURE AND ARE
SUSCEPTIBLE TO PACKAGE CRACKING, BOND WIRE BREAKAGE, AND BOND
SEPARATION FROM CHIP IF THEY ARE NOT BAKED PRIOR TO ANY EXPOSURE TO
HIGH TEMPERATURES OF VAPOR PHASE OR IR REFLOW SOLDERING OR
IMMERSION WAVE SOLDERING.
Factory Floor Life
The maximum life that dry parts may be safely exposed in
a manufacturing ambient condition depends on the specific condition prevailing in the customer's factory. In
addition, it also depends on whether the parts are near the
beginning or the end of the storage life in the sealed bag.
Finally, it depends also on the critical moisture level of the
package that causes moisture-induced cracks.
COMPONENT BAKING SHALL BE DONE AT 125°C FOR 24 HRS PRIOR TO ANY
REFLOW SOLDERING. UNITS IN TAPE AND REEL AS WELL AS THOSE IN PLASTIC
TUBES SHOULD NOT BE SUBJECTED TO THE 125°C BAKE, INSTEAD A LOW
TEMPERATURE BAKE (45°C UNTIL 0.11% MOISTURE BY BODY MASS) WILL
SUFFICE.
Some guidelines have been provided by the Institute for
Interconnecting and Packaging Electronics Circuits in
XILINX CAN PROVIDE BAKING AND DRY PACKING SERVICES UPON SPECIAL
ORDER.
4-24
Sockets
There are no wire-wrap sockets for PLCCs. One solution
is to piggy-back a through-hole PLCC socket mounted in
a compatible PGA socket with wire-wrap pins. Note that
the board-layout then differs from a PGA board layout.
Below are two lists of manufactures known to offer sockets
for Xilinx package types. This list does not imply an
endorsement by Xilinx. Each user must evaluate the
particular socket type.
Zero Insertion Force (ZIF) sockets, recommended for
prototyping with 132 and 175 pin PGA devices, also lack
the wire-wrap option. Piggy-back the ZIF socket in a
normal PGA wire-wrap socket.
PGA Sockets
PLCC Sockets
AMP Inc.
Harrisburg, PA 17105
(717) 564-0100
Burndy Corp.
Richards Ave.
Norwalk, CT 06856
(203) 852-8437
Garry Electronics
9 Queen Anne Court
Langhorne, PA 19047-1803
(215) 949-2300
Honda - MHOtronics
Deerfield. IL 60015
444 Lake Cook Road, Suite 8
(312) 948-5600
ITT Cannon
10550 Talbert Ave.
P.O.Box 8040
Fountain Valley, CA 92728
(714) 964-7400
Maxconn Inc.
1855 O'Toole Ave., 0102
San Jose, CA 95131
(408) 435-8666
Methode Electronics Inc.
1700 Hicks Road
Rolling Meadows, IL 47150
(312) 392-3500
Mill-Max Mfg. Corp.
190 Pine Hollow Road
Oyster Bay, N.Y. 11771-0300
(516) 922-6000
Advanced Interconnections
5 Energy Way
West Warwick, RI 02893
(401) 823-5200
McKenzie Technology
44370 Old Warm Springs Blvd.
Fremont CA 94538
(415) 651-2700
Precicontact Inc.
835 Wheeler Way
Langhorne, PA 19047
(215) 757-1202
AMP Inc.
Harrisburg, PA 17105
(717) 564-0100
Methode Electronics Inc.
1700 Hicks Road
Rolling Meadows, IL 47150
(312) 392-3500
Aries Electronics, Inc.
P.O.Box 130
Frenchtown, NJ 08825
(201) 996-6841
Samtec Inc.
P.O.Box 1147
New Albany, IN 47150
(812) 944-6733
3M Textool
Austin, TX
(800) 328-7732
Thomas & Betts Corp.
920 Route 202
Raritan, NJ 08869
(201) 469-4000
Wells Electronics, Inc.
1701 South Main Street
South Bend, IN 46613
(219) 287-5941
Yamaichi - Electronics, Inc.
1420 Koll Circle
Suite B
San Jose, CA 95112
(408) 452-0792
Augat
33 Perry Ave.
P.O.Box779
Attleboro, MA 02703
(617) 222-2202
Precicontact Inc.
835 Wheeler Way
Langhorne, PA 19047
(215) 757-1202
Bevmar Industries, Inc.
20601 Annalee Ave.
Carson, CA 90746
(213) 631-5152
Samtec Inc.
P.O.Box 1147
New Albany, IN 47150
(812) 944-6733
Bevmar Industries, Inc.
1 John Clarke Rd.
Middletown, RI 02840
(401) 849-4803
Texas Instruments
CSD Marketing, MS 14-1
Attleboro, MA 02703
(617) 699-5206
Electronic Molding Corp.
96 Mill Street
Woonsocket, RI 02895
(401) 769-3800
Thomas & Betts Corp.
920 Route 202
Raritan, NJ 08869
(201) 469-4000
Garry Electronics
9 Queen Anne Court
Langhorne, PA 19047-1803
(215) 949-2300
Yamaichi - Electronics, Inc.
1420 Koll Circle
SuiteB
San Jose, CA 95112
(408) 452-0792
Mark Eyelet Inc.
63 Wakelee Road
Wolcott, CT 06716
(203) 756-8847
4-25
MiII·Max Mfg. Corp.
190 Pine Hollow Road
Oyster Bay, N.Y. 11771-0300
(516) 922-6000
I
Packages and Thermal Characteristics
4-26
SECTIONS
1
Programmable Logic Devices
2
FPGA Product Descriptions and Specifications
3
EPLD Product Descriptions and Specifications
4
Packages and Thermal Characteristics
5
Quality, Testing and Reliability
6
Technical Support
7
Development Systems
8
Applications
9
The Best of XCELL
10 Index, Sales Offices
Quality Assurance
and Reliability
Quality Assurance Program ................................................................ 5-1
Device Reliability ................................................................................. 5-2
Outline of Testing ................................................................................ 5-2
Description of Tests ............................................................................ 5-5
Data Integrity ....................................................................................... 5-7
Electrostatic Discharge ....................................................................... 5-8
Latchup ............................................................................................... 5-8
High Temperature Performance .......................................................... 5-8
Quality Assurance
and Reliability
Quality Assurance Program
stop bit) supporting all of the following communications
protocols: ASCII, Kermit, XModem, -CRC, and Telink.
All aspects of the Quality Assurance Program at
Xilinx
have been designed to eliminate the root cause of
defects, rather than to try to remove them by inspection.
The programs are in full compliance with the requirements of Appendix A of MIL-M-38510. These programs
emphasize heavily the aspects of process control, process documentation, and operator training. These programs and those of the company's subcontractors are
subjected to extensive internal and external audits to
ensure compliance.
Xilinx is committed to customer satisfaction. By adhering
to the highest quality standards, the company has
achieved leadership in the EPLD and FPGA manufacturing areas and in the supporting arena of developmentsystems software.
Quality Assurance encompasses all aspects of company
business. Xilinx continually strives to improve quality to
meet customers' changing needs and expectations. To do
this, the company is dedicated to the following.
Xilinx calculates its outgoing component quality ievel,
expressed in PPM (defective parts per million devices
shipped) using the industry standard methods now
adopted by JEDEC and published in JEDEC Standard
16. These. figures of merit are revised monthly and published quarterly by Xilinx Quality Assurance. Figure 1
details Xilinx efforts to improve the outgoing quality of its
products over the .Iast year. Summary data for this performance will continue to be made available for downloading
from the Xilinx Electronic aulletin Board at (408) 5599372 (1200/2400 baud; eight data bits; no parity; one
158
• To provide a broad range of products and services that
satisfy both the expectations of customers and the
company's stringent quality standards.
• To emphasize open communications with customers
and suppliers, supported with the necessary statistical
data.
• To continually improve the quality of Xilinx products,
services, and company efficiency.
• To maintain a work environment that fosters quality
and reliability leadership and excellence.
_
157
D
~
Electrical PPM
Visuai/Mechanical PPM
:S
Ul
0
0
w
0
..,w
96
C
~
~
71
lii
a.
..
f!
n.
.E
0
~
1992
1993
X3123
Figure 1. Xilinx Avereage Outgoing Quality - Mature, High Volume Products
5-1
II
Quality Assurance and Reliability
Device Reliability
These tests provide an accelerated method of emulating
long-term system operation in severe field environments.
From the performance of the devices during these tests,
predictions of actual field performance under a variety of
conditions can be easily calculated.
Device reliability is often expressed in a measurement
called Failures in Time (FITS). In this measure one FIT
equals one failure per billion (10 9) device operating
hours. A failure rate in FITS must include the operating
temperature to be meaningful. Hence failure rates are
often expressed in FITS at 70°C (or some other temperature in excess of the application).
This report describes the nature and purpose of the various reliability tests performed on finished devices. Updated
summaries are available upon request from the Quality
Assurance and Reliability Department at Xilinx.
Since one billion hours is well in excess of 100,000 years,
the FIT rate of modern ICs can only be measured by
accelerating the failure rate by testing at a higher junction
temperature (usually 125°C or 145°C). Extensive testing
of Xilinx XC2000 and XC3000 devices (performed on
actual production devices taken directly from finished
goods) has been accomplished continuously since 1989.
During the last two years, over 7,500 devices (both
XC2000 and XC3000) have accumulated a total of over
13,000,000 hours of both static and dynamic operating at
125°C (equivalent) to yield the following FIT rates at
70°C.
12191
3192
6192
9/92
XC2000. static
8
6
6
4
5
FITs
XC3000. static
22
20
20
16
15
FITs
9
9
9
4
2
FITs
XC3000. dynamo
Outline of Testing
Qualification testing of devices is performed to demonstrate the reliability of the die used in the device, and the
materials and methods used in the assembly of the
device. Testing methods are derived from and patterned
after the methods specified in MIL-STD-883.
Referral to the test methods of MIL-STD-883 is not
intended to imply that nonhermetic products comply with
the requirements of MIL-STD-883. These test methods
are recognized industry-wide as stringent tests of reliability and are commonly used for nonmilitary-grade semiconductor devices, as well as for fully compliant militarygrade products.
12192
Hermetic packages are qualified using the test methods
specified in MIL-STD-883. The Group D package qualification tests are performed on one lot of each package
type from each assembly facility every twelve months.
From its inception, Xilinx has been committed to delivering the highest quality, most reliable programmable gate
arrays available. A strong Quality Assurance and Reliability program begins at the initial design stages and is carried through to final shipment. An extensive, on-going
reliability-testing program is used to predict the field performance of all Xilinx devices.
A summary of the reliability demonstration tests used at
Xilinx is contained in Table 1.
5-2
~XIUNX
Table 1A. Reliability Testing Sequence for Non-Hermetic Devices
Die Qualification
Lot Tolerance% Defective
Minimum Sample Size!
Maximum Acceptable Failures
Name of Test
Test Conditions
1.
High Temperature
Life
1000 hr min equivalent at temperature = 125°C
Life test circuit equivalent to MIL-STD-883
2.
Biased Moisture
Life
1000 hr min exposure
T = 85°C, RH = 85%
Max rated operating voltage
Biased moisture life circuit equivalent to
MIL-STD-883
LTPD=5,
s = 105, c=2
LTPD=5,
s = 77, c = 1
Non-Hermetic Package Integrity andAssembly Qualification
Name of Test
3.
Unbiased
Pressure Pot
Lot Tolerance % Defective
Minimum Sample Size!
Maximum Acceptable Failures
Test Conditions
96 hr min exposure
T = 121°C, P = 2 atm H2 0 saturated
LTPD=5,
s =45, c =0
MIL-STD-883, Method 1011, Condo C
-65°C to +150°C
100 cycles
LTPD=5,
s =45, c =0
5. Temperature
Cycling
MIL-STD-883, Method 1010, Condo C
-65°C to +150°C
200 cycles
LTPD=5,
s =45, c =0
6. Salt Atmosphere
MIL-STD-883, Method 1009, Condo A
24 hrs
s =25, c = 0
7. Resistance to
Solvents
MIL-STD-883, Method 2015
s=4, c=O
8.
Solderability
MIL-STD-883, Method 2003
s =3, c=O
9.
Lead Fatigue
MIL-STD-883, Method 2004
s =2, c=O
4. Thermal Shock
5-3
I
Quality Assurance and Reliability
Table 1B. Reliability Testing Sequence for Hermetic Devices
Hermetic Package Integrity and Assembly Qualification
Lot Tolerance % Defective
Minimum Sample Sizel
Maximum Acceptable Failures
Name of Test
Test Conditions
1.
Subgroup D1
Physical Dimensions
MIL-STD-883, Method 2016
LTPD = 15,
s =25, c = 1
2.
Subgroup D2
a. Lead Integrity
b. Seal (fine and
gross leak)
MIL-STD-883, Method 2028
MIL-STD-883, Method 1014
(not required for PGAs)
s =25, c = 1
Subgroup D3
a. Thermal Shock-15 cycles
b. Temp. cycling-100 cycles
c. Moisture Resistance
d. Seal (fine & gross leak)
e. Visual Examination
f. End-point electricals
MIL-STD-883, Method
MIL-STD-883, Method
MIL-STD-883, Method
MIL-STD-883, Method
MIL-STD-883, Method
Group A, subgroup 1
s =25, c = 1
3.
4.
5.
6.
7.
Subgroup D4
a. Mechanical Shock
b. Vibration, Variable Freq.
C. Constant Acceleration
LTPD = 15,
LTPD
1011, Condo B
1010, Condo C
1004
1014
1004 and Method 1010
= 15,
LTPD = 15,
s = 25, c = 1
d. Seal (fine & gross leak)
e. Visual Examination
1. End-point electricals
MIL-STD-883, Method 2002, Condo B
MIL-STD-883, Method 2007, Condo A
MIL-STD-883, Method 2001, Condo E
min, Y1 only
(Cond. D for large PGAs)
MIL-STD-883, Method 1014
MIL-STD-883, Method 1010
Group A, subgroup 1
Subgroup D5
a. Salt Atmosphere
b. Seal (fine & gross leak)
C. Visual Examination
MIL-STD-883, Method 1009, Condo A
MIL-STD-883, Method 1014
MIL-STD-883, Method 1009
s = 15, c = 0
Subgroup D6
Internal Water Vapor
Content
MIL-STD-883, Method 1018, 5000 ppm
water at 100°C
s = 3; c =0 or
s = 5; c = 1
Subgroup D7
Lead Finish Adhesion
MIL-STD-883, Method 2025
LTPD = 15,
s = 25 leads,
(3 device min)
LTPD
= 15,
c=O
8.
Subgroup D8
Lid Torque
MIL-STD-883, Method 2024
(for ceramic quad flat pack, CQFP only)
5-4
LTPD = 5,
s = 5, c = 0
intermittent operation at very low temperatures. The
range of temperatures is -65°C to + 150°C. The transition
time is longer than that in the Thermal Shock test but the
test is conducted for many more cycles.
Description of Tests
Die Qualification
1. High Temperature Life - This test is performed to evaluate the long-term reliability and life characteristics of the
die. It is defined by the Military Standard from which it is
derived as a "Die-Related Tesf' and is contained in the
Group C Quality Conformance Tests. Because of the
acceleration factor induced by higher temperatures, data
representing a large number of equivalent hours at a normal temperature of 25°C can be accumulated in a reasonable period of time.
6. Salt Atmosphere - This test was originally deSigned by
the US Navy to evaluate resistance of military-grade shipboard electronics to corrosion from sea water. It is used
more generally for non-hermetic industrial and commercial products as a test of corrosion resistance of the package marking and finish.
7. Resistance to Solvents - This test is performed to
evaluate the integrity of the package marking during
exposure to a variety of solvents. This is an especially
important test, since an increasing number of board-level
assemblies are subjected to severe conditions of automated cleaning before system assembly. This test is performed according to the methods specified by MIL-STD883.
2. Biased Moisture Life - This test is performed to evaluate the reliability of the die under conditions of long-term
exposure to severe, high-moisture environments that
could cause corrosion. AI-though it clearly stresses the
package as well, this test is typically grouped under the
die-related tests. The device is operated at maximumrated voltage, 5.5 Vdc, and is exposed to a temperature
of 85°C and a relative humidity of 85% throughout the
test.
8. Solderability - This test is performed to evaluate the
solderability of the leads under conditions of low soldering
temperature following exposure to the aging effects of
water vapor.
Package Integrity and Assembly
Qualification
3. Unbiased Pressure Pot - This test is performed at a
temperature of 121°C and a pressure of 2 atm of saturated steam to evaluate the ability of the plastiC encapsulating material to resist water vapor. Moisture penetrating
the package could induce corrosion of the bonding wires
and nonglassivated metal areas of the die (bonding pads
only for LCA devices). Under extreme conditions, moisture could cause drive-in and corrosion under the glassivation. Although it is difficult to correlate this test to actual
field conditions, it provides a well-established method for
relative comparison of plastic packaging materials and
assembly and molding techniques.
9. Lead Fatigue - This test is performed to evaluate the
resistance of the completed assembly to vibrations during
storage, shipping, and operation.
Testing Facilities
Xilinx has complete capability to perform High Temperature Life Tests, Thermal Shock, Biased Moisture Life
Tests, and Unbiased Pressure Pot Tests in its own Reliability Testing Laboratory. Other tests are being performed by outside testing laboratories.
Summary
The testing data in Table 2 shows the actual performance
of the devices during the initial qualification tests to which
they have been subjected. These test results demonstrate the reliability and expected long life inherent in the
non-hermetic product line. This series of tests is ongoing
as a part of the Quality Conformance Program on nonhermetic devices.
4. Thermal Shock- This test is performed to evaluate the
resistance of the package to cracking and resistance of
the bonding wires and lead frame to separation or damage. It involves nearly instantaneous change in temperature from -65°C to +150°C.
5. Temperature Cycling- This test is performed to evaluate the long-term resistance of the package to damage
from alternate exposure to extremes of temperature or to
5-5
II
Quality Assurance and Reliability
Table 2. Xilinx Reliability Testing Summary
Processrrechnology: 1.2, 1.08, 0.8 1l2-Metal CMOS
Device Types: XC17XX, XC2000, XC3000,
XC3100, XC4000, XC7200IXC7300
Die Attach Method: Silver Epoxy
Molding Compound: Sumitomo 6300H
Test
Package Type: Varied PLCC/PO/PPG
Date: 40 92
Combined Sample
Failures
Equivalent
Mean
Hrs/Oevice at
TA = 125°C
TotalOevice
Hrs at
T A =125°C
Equivalent
Failure Rate
in FIT at
T J =70°C
7.5-
11,357
21
921
Equivalent
Device Hrs
41,867,856
4,659
23
atTA = 85°C
1,063
atTA = 85°C
4,953,453
2,270
0
150
338,604
1
Mean Cycles
per Device
448
Total Device
Cycles
719,782
1,362
6
Mean Cycles
per Device
511
Total Device
Cycles
696,800
Salt Atmosphere Test
MIL-STD-883, Method 1009,
Cond.A
922
1
24
22,128
Resistance to Solvents Test
MIL-STD-883, Method 2105
88
0
Solderability Test
MIL-STD-883, Method 2003
1420
0
Lead Fatigue Test
MIL-STD-883, Method 2004
1800
0
High Temperature Life TestT
= 145°C (FPGA)
T A = 125°C (EPLD)
A
Biased Moisture Life Test
T = 85°C; RH = 85%
Unbiased Pressure Pot Test
+121°C, 2 atm sat. steam
Thermal Shock Test
-65°C/+ 150°C
200 cycles (min)
Temperature Cycling Test
-65°C/+ 150°C
100 cycles (min)
1,605
- Assumed activated energy 0.90 eV
5-6
(Write operation and a Read operation. In the normal
/ operation, the data in the basic memory element is not
changed. Since the two circularly linked inverters that
hold the data are physically adjacent, supply transients
result in only small relative differences in Voltages. Each
inverter is truly a complementary pair of transistors.
Therefore, whether the output is High or Low, a lowimpedance path exists to the supply rail, resulting in
extremely high noise immunity. Power supply or ground
transients of several volts have no effect on stored data.
Data Integrity
Memory Cell Design in the LCA Device
An important aspect of the LCA device reliability is the
robustness of the static memory cells used to store th
configuration program.
The basic cell is a single-ended 5-transistor memory ement (Figure 2). By eliminating a sixth transistor, w ich
would have been used as a pass transistor for the omplementary bit line, a higher circuit density is achi ved.
During normal operation, the outputs of these ce s are
fixed, since they determine the user configuration Write
and readback times, which have no relation to th device
performance during normal operation, will be slo er without the extra transistor. In return, the user recei es more
functionality per unit area.
The transistor driving the bit line has been carefully
designed so that whenever the data to be written is opposite the data stored, it can easily override the output of
the feedback inverter. The reliability of the Write operation
is guaranteed within the tolerances of the manufacturing
process.
This explains the basic cell, but how is the LCA user
assured of high data integrity in a noisy en ironment?
Consider three different situations: normal ~peration, a
In the Read mode, the bit line, which has a significant
amount of parasitic capacitance, is precharged to a logic
one. The pass transistor is then enabled by driving the
I
/
Vee
!
Configuration Data Shift Regiater
aN.' -------------1Ds
al----------------- Ground
-~r-----~~--Vcc
Input
-~~---<.----------~.........-. Ground
0= Symbol for electrostatic discharge protection circuit
X3132
Pad
/1
Figure 3. Input/Output Protection Circuitry
R:--
Figure 4. SCR Model
5-8
X1825
SECTION 6
1
Programmable Logic Devices
2
FPGA Product Descriptions and Specifications
3
EPLD Product Descriptions and Specifications
4
Packages and Thermal Characteristics
5
Quality, Testing and Reliability
6
Technical Support
7
Development Systems
8
Applications
9
The Best of XCELL
10 Index, Sales Offices
Technical Support
Technical Seminars and User's Group Meetings ................................ 6-1
Newsletter ........................................................................................... 6-2
Technical Bulletin Board ..................................................................... 6-3
Field Applications Engineers ............................................................... 6-5
Training Courses ................................................................................. 6-6
Technical Literature ............................................................................. 6-7
Technical Seminars and
Users' Group Meetings
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Users' Group meetings are intended for experienced users of Xilinx Field Programmable Gate Arrays, and emphasize the use of the various development system tools to
generate LCA-based designs.
Xilinx sponsors technical seminars at locations throughout
North America, Europe, and Asia.
Product-oriented seminars are directed toward new and
potential users of Field Programmable Gate· Arrays.
These seminars include a basic description of the Logic
Cell Array architecture and the benefits ofthis technology.
Experienced users will also find these seminars useful for
learning about newly released products from Xilinx.
Contact your local Xilinx sales office, sales representative,
or distributor for information about seminars in your area.
6-1
II
Newsletter
XC ELL, the quarterly customer newsletter, is dedicated to
supplying up-to-date information to registered Xilinx customers, and is a valuable resource for systems designers.
A typical issue of XCELL contains descriptions of recently-
introduced products, updates on component and software
availability and revision levels, applications ideas, design
hints and techniques, and answers to frequently-asked
technical questions.
6-2
Xilinx Technical
Bulletin Board
FILE COMMANDS
MESSAGE COMMANDS
Use these commands to list, download,
and upload files.
Use these commands to send and receive
messages.
TYPE:
TYPE:
F
[F)ile Directories)
To list the available File Areas, the files
contained in each area, and a short
description of each file.
C
[C)omment to SYSOP)
To leave a message to the System
Operator on BBS issues.
T
[T)ransfer Protocol)
Sets the Transfer Protocol for Uploads!
Downloads. If set to "None", you will be
prompted for a Transfer Protocol before
each Upload/Download.
o [D)ownload a File)
To download a file from the Bulletin Board.
U
[U)pload a File)
To upload a file to the Bulletin Board.
FLAG [FLAG for Download)
To FLAG files for a Batch Download, you
must use Ymodem as your Transfer
Protocol if you use this option.
E
[E)nter a message)
To send a message.
R
[R)ead Messages)
To read messages and reply to messages.
[K)iII a Message)
K
To delete a message.
Y
[Y)our Per. Mail)
To scan the message base for messages
addressed to you.
TS [TX Txt Srch Msgs)
To find a text string in the message
headers and message contents accessible
to you.
DB [DB Download Batch)
To download multiple files at one time, you
must use Ymodem as your Transfer
Protocol if you use this option.
GENERAL COMMANDS
General Bulletin Board Commands.
TYPE:
B
[B)unetln Listings)
To display the available Bulletins.
G
[G)oodbye (Hang up))
To terminate the Bulletin Board session.
H
[H)elp Functions)
To receive Help Texlon any command.
M
[M)ode (Graphics))
Toggles between the Graphics Onl
Graphics Off Modes.
P
[P)age Length Set)
To specify the number of lines the Bulletin
Board displays before it prompts ·More?"
X
[X)pert On/Off]
Toggles between Expert On (no menus)!
Expert Off Modes.
V
[V)iew Settings)
To display your Bulletin Board Mode
settings.
I
W
[W)rite User Info)
To change your password and other User
Registration Information.
NEWS [NEWS file display)
To redisplay the text displayed when you
initially logged on.
UB [UB Upload Batch)
To upload multiple files at one time, you
must use Ymodem as your Transfer
Protocol if you use this option.
N
[N)ew Files (date))
To search for files on the Bulletin Board
newer than a specified date.
L
[L)ocate Files (name))
To search for files on the Bulletin Board by
name.
Z
[Z)ippy DIR Scan)
To search for files on the Bulletin Board by
text. Will search by both file name and file
description.
To provide customers with up-to-date information and an
immediate response to questions, Xilinx provides a 24hour electronic bulletin board. The Xilinx Technical Bulletin Board (XTBB) is available to all registered XACT
customers. Users with full privileges can read files on the
bulletin board, download those of interest to their own
systems or upload files to the XTBB. They can also leave
messages for other XTBB users.
6-3
II
Xilinx Technical Bulletin Board
New bulletin board users must answer a questionnaire
when they first access the XTBB. After answering the
questionnaire callers can browse through the bulletin and
general information file areas. A caller with a valid XACT
protection key or valid host ID will be given full user
privileges within 24 hours.
3. Messages are used to communicate with other XTBB
users; they can be general-available to everyone-or
private.
The XTBB is based on a bulletin board system called
PCBoard. This is a menu-driven system-you choose
commands from menus to decide what happens next. To
choose a menu command, simply type the highlighted first
letter(s) of the command and press return . Listed
below are some helpful hints for using the XTBB.
The software and hardware requirements for accessing
the Xilinx Technical Bulletin Board are:
Baud Rate
Character Format
Phone Number
Transfer Protocols
9600,4800,2400, or 1200 bps
8 data bits, no parity, 1 stop bit
(408) 559-9327
ASCII, Xmodem, (Checksum,
CRC, 1K), Ymodem
• To perform a sequence of commands, type the first letter
of each command, followed by a space, and press
return. For example, typing FA [F)ile Directories
A)II] sends you a listing of all file directories .
Information contained on the XTBB is divided into three
general categories: 1. Bulletins, 2. Files and 3. Messages.
• The XTBB has an extensive help section. To get help,
type H followed by the command in question. A
short explanation ofthe command will be displayed. You
can also type H inside a command, and get an
explanation of the sub-commands.
1. Bulletins contain tidbits of up-to-date information; they
can be displayed on-screen and can be downloaded.
2. Files can contain just about anything (text, user programs, etc.). XTBB users with full privileges can download files to their own systems or upload files to the
bulletin board.
6-4
Field Applications Engineers
939 N. Plum Grove Rd.
SuileH
Schaumburg, IL 60173
Tel: 708-605-1972
5445 DTC Pkwy.
Penthouse 4
Englewood, CO 80111
Tef: 303-220-7541
61 Spit Brook Rd.
Suite 403
Nashua, NH 03060
Tel: 603-891-1096
93 Willow Glen Dr.
Kanata Ontario
Canada K2M 1T8
Tel: 613-592-5522
15615 Alton PkWy.
Suite 280
Irvine, CA 92718
Tel: 714-727-0780
X3661
6494 Weathers Place
Suite202 '
San Diego, CA 92121
Tel: 619-558-5974
6115-C Oakbrook Pkwy.
Norcross, GA 30093
Tel: 404-448-4733
North America
There are 16 Xilinx Field Applications Engineers in the
locations shown above. Additional technical support is
provided by Headquarters Applications.
Dial (408) 879-5199 or (800) 255-7778.
Europe
Each of the Xilinx European sales offices in England and
Germany has a resident Field Applications Engineer:
England (tel 44-932-349401);
Germany (teI49-89-6110851.
The world-wide network of Xilinx Representatives ,and
Distributors also gives technical support.
Japan
Xilinx Japan is located in Tokyo and has a resident Field
Applications Engineer (tel 81-3-297-9191).
6-5
II
Programmable Logic
Training Courses
Xilinx Programmable Logic Training Courses are
comprehensive classes covering Xilinx components and
development system products. All users of Xilinx products
are encouraged to attend one of our Training Courses.
Attending a Xilinx Training Course is one of the fastest and
most efficient ways to learn how to design with
programmable logic devices from Xilinx. Hands-on expert
instruction with the latest information and software will
allow you to implement your own designs in less time with
more effective use of the devices.
advanced options. Advanced Training sessions may also
be presented locally-contact your closest sales office for
information.
Benefits
• Start or complete your design during the training class
• Reduce your learning time
• Make fewer design iterations
Classes
Course
Length
Recommendation
XC3000
2 days
New XC20001
XC3000 Users
$750
XC3000
Advanced
1 day
Current XC2000/
XC3000 Users
Free
Tuition
XC4000
2 days
New XC4000 Users
$750
XC4000
Advanced
1 day
Current XC4000 Users
Free
XC3000 &
XC4000
4 days
New Users of Both
Families
$1000
• Get to market faster
EPLD classes will begin in 1993. Please call for information
and schedules.
• Lower production costs
• Increase quality
Prerequisites
Students need only have a background in digital logic
design. Basic familiarity with PCs and the DOS operating
system is helpful but not required. Regional sites in New
York and Texas offer workstation-based classes. The
Advanced Training sessions require previous experience
with Xilinx products.
Course Outline
All FPGA classes cover the following for their respective
products:
Automatic Translation
XACT DeSign Manager (XDM)
XMake Program
Basic Device Architecture
Locations
Factory (San Jose, CA)
Each class held once/month
Schematic Design Entry Guidelines
(View logic is used as an example)
MemGen RAM/ROM Compiler (XC4000)
30 Regional Centers Worldwide
Typically XC3000IXC4000 class once/quarter
Design Implementation Tools
Incremental and Iterative Design Flows
On-site
According to customer need
Configuration
Bitstream Generator (Make Bits)
PROM Formatter (MakePROM)
Downloading and Readback with the XChecker Cable
Xilinx Training Courses are held in over 15 states across
the United States and more than 12 countries worldwide.
Contact Xilinx Headquarters or your local sales office for
the latest information on classes in your area. Xilinx can
also bring the Training Course to your own facility.
Design Verification Techniques
Simulation
XDelay Static Timing Analyzer
Design Editor (EditLCA)
Enrollment and Information
To enroll or to get information, call the Xilinx Training
Administrator at (408) 879-5090, or your local sales office.
For many classes, registering three weeks early entitles
you to a 10% discount on tuition.
Advanced Training classes follow the two-day XC3000
and XC4000 classes in the factory. Topics to be covered
will depend on the needs of the students, and can include
logic design guidelines, optimization techniques, and more
6-6
Technical literature
Technical Literature
Reference Guides cover details about each Xilinx software
program, including the commands, options, variables, and
arguments related to each program. These guides include
information aboutthe files required and the files generated, as
well as warning and error messages. Reference guides
address software functions and software capability, but do not
always include "how to" information. Reference Guide contents are organized by function, following a "typical" designflow model to provide details about specific functions that may
be needed.
Xilinx provides manuals and supporting documents for development systems, libraries, CAE tool interfaces, and related
software tools such as logic synthesis.These manuals are
organized in several categories - Development System
User Guides, Interface User Guides, Library Guides, and
Reference Guides.
DevelopmentSystemUserGuidesare introductory manuals
that cover basic information about using Xilinx software. They
address such topics as design entry and design verification in
the Xilinx environment. User guides are provided for development system core software and for enhancements such as
the Xilinx-ABEL and X-BLOX tools.
Documentation Sets
New documentation is provided in individual books covering
development system software, CAE interfaces, libraries, and
program reference information. Appropriate books are included with each software package. Additional books and
book sets can be ordered.
Interface User Guides address CAE tools as they relate to the
Xilinx design environment. They address such topics as
design entry and verification in the Xilinx environment using
specific CAE tools. These guides include design flow, creating designs, translating designs into Xilinxformat, verification
and simulation of designs, and implementing designs. Tutorial information about the CAE tool is included in the interface
guides, covering both design entry and design verification.
When appropriate, sections covering CAE tool commands,
options, and variables are also included in Interface User
Guides.
CAE Tool Documents
Xilinx provides manuals covering CAE tools to those customers who buy these tools through Xilinx. These manuals are
reprinted by Xilinx with permission from the CAE tool manufacturers. The content of these manuals is provided by the
CAE tool manufacturers. Questions about the information in
these manuals should be directed to the CAE tool manufacturer. The Viewlogic Workview Series I, Volumes 1,2, and 3
books, and the Viewlogic ViewSynthesis book are examples
of such manuals.
Library Guides include information about primitives, gates,
flip-flops, pads, 1/0 functions, and macros available for Xilinx
programmable logic families. These guides includes appropriate symbols, descriptions, truth tables and schematics for
design resource elements available across all Xilinx programmable logic device families. Functional selection guides
list all elements available in each logic family and all X-BLOX
elements.
6-7
II
Technical Literature
6-8
SECTION 7
1
Programmable Logic Devices
2
FPGA Product Descriptions and Specifications
3
EPLD Product Descriptions and Specifications
4
Packages and Thermal Characteristics
5
Quality, Testing and Reliability
6
Technical Support
7
Development Systems
8
Applications
9
The Best of XCELL
10 Index, Sales Offices
Development Systems
Overview ............................................................................................. 7-1
Product Packages ............................................................................... 7-2
Xilinx Automatic CAE Tools Product Overview ................................... 7-3
Bundled Packages Product Descriptions ............................................. 7-13
Individual Product Descriptions ........................................................... 7-29
Overview
This section describes the Xilinx Automated CAE Tools
(XACT) design environment for Xilinx FPGA and EPLD
devices.
software is integrated under the Xilinx Design Manger
(XDM), providing designers with a common user interface
regardless of their choice of device architecture and tools.
Xilinx offers a variety of development system products
optimized to support Xilinx FPGA and EPLD archi-tectures.
Available products include state-of-the-art design
compilation software, libraries and interfaces to popular
schematic editors and timing simulators, and behavioralbased design entry tools. All Xilinx development system
Xilinx software is availabile in both bundled packages containing entire sets of tools and as separate products. New
enhancements are constantly being developed by the
Xilinx research and development staff, and update services
are available to ensure timely access to the latest versions.
II
7-1
Development Systems
Product Packages
Product Descriptions
Xilinx Development System software is available as bundled
packages or separate products. Packages are designed to
address the needs of different types of users and are
available for a variety of CAD systems and platforms.
Libraries and Interface - Contains symbol libraries for
specified schematic editor, simulation models with timing
information for specified simulator and a program to translate between the schematic editor or simulator's file format
and the XNF file format.
Base Packages
Core Implementation - Provides the software necessary
to process a netlist file into a bit-map file that can be
downloaded into a Xilinx device. Includes tools for logic
reduction, design rule checking, mapping, automatic placement and routing, interactive placement and routing, bitstream generation and bit-map file generation.
The Base package provides schematic capture and simulation interfaces, design implementation tools and download hardware for low-complexity Xilinx devices. These
devices include the complete XC7200IXC7300 EPLD
families, the complete XC2000 FPGA family and the
XC3000IXC31 00 FPGA family of devices up tothe XC3130.
A special version is available for Viewlogic on the PC that
includes the Viewdraw schematic editor and Viewsim
simulator (limited to 5,000 gates).
Logic Synthesis Interface - Provides the tools to use a
third-party high-level description language and synthesis
tool for Xilinx design entry.
Standard Packages
X-BLOXArchitecturalSynthesis- Permits entering FPGA
designs as block diagrams using a familiar schematic
editor. Using built-in expert knowledge, X-BLOX software
automatically optimizes the design to take full advantage
of the unique features of the Xilinx FPGA architecture.
The Standard package provides schematic capture and
simulation interfaces, design implementation tools and
download hardware for a broader range of Xilinx devices.
These devices include the XC7200/XC7300 EPLD family
and the complete XC2000, XC3000IXC31 00 and XC4000
FPGA families. A special version is available for View logic
on the PC that includes the Viewdraw schematic editor and
Viewsim simulator (unlimited gates).
Xilinx ABEL - Supports text-based design entry and netlist
translation using ABEL high-level description language.
The ABEL language supports different design styles including Boolean equations, truth tables and encoded or
symbolic state machines.
Extended Packages
ParallelDownloadCable- Supports downloading of FPGA
bitstreams and PROM files from the parallel port of IBM
PCs and compatibles.
The Extended package provides all the capability of the
Standard package plus X-BLOX Architectural Synthesis.
A special version is available for Viewlogic on the PC that
includes the Viewdraw schematic editor, Viewsim simulator (unlimited gates) and Viewsynthesis with X-BLOX
integration.
XChecker Cable - Supports downloading of FPGA bitstreams and PROM files and readback of configuration
data and internal node values. This cable uses the serial
port of IBM PCs and compatibles as well as workstations.
Stand-alone Packages (/S)
XC3000 Demonstration Board- Provides demonstration
or prototype capability for XC3000/XC31 00 family devices
in 68-pin PLCC packages.
The Base, Standard and Extended packages are also
available as stand-alone systems, denoted by IS, that
include the Viewdraw-LCA schematic capture package
and the Viewsim-LCA logic simulator. These packages
are designed for those who do not already have a schematic capture and simulator design system.
XC4000 Demonstration Board- Provides demonstration
or prototype capability for XC4000 family devices in 84-pin
PLCC packages.
All of the Xilinx Development System software, hardware
and documentation is available as individual products for
adding to an existing package or creating a new one.
7-2
Xilinx Automatic CAE Tools Product
Overview
quality" programmable gate arrays on a PC or engineering
workstation.
EPLD DeSign Flow
FPGA Design Flow
The Xilinx XEPLD development tool also uses a 3-step
design process.
The Xilinx Automatic CAE Tools (XACT Development
System) use a 3-step design process:
•
Step 1
•
Step 2
Design Implementation
•
Step 3
Design Verification
Design Entry
Step 1 -
Design Entry
Step 2 -
Design Implementation
Step 3 -
Design Verification
Designs can be represented as schematics consisting of
XEPLD library components, as behavioral descriptions, or
a mixture of both.
The Xilinx Logic Libraries and XNF Interface Products
support design entry with popular schematic logic drawing
systems supplied by multiple vendors, providing easy
entry to the XACT Development System.
The XEPLD translator reads Boolean equations and schematicnetlists. It minimizes equations, optimizes the design and maps the result onto a selected EPLD device.
Logic synthesis, partitioning, and optimization programs
translate the design specifications into CLBs and lOBs
unique to the LCA architecture. Subsequent programs
perform automatic placement and routing to complete the
LCAdesign.
The DS550 XEPLD translator produces a simulation-model
file for either the View logic Viewsim or OrCAD VST simulator. The overall design flow is illustrated on page 7-4.
While completely automatic implementation is desirable
for both low- and high-complexity designs, the designer
may prefer an interactive process, especially in highperformance designs. This interactive editing can range
from rerouting a few previously automatically routed nets,
to prerouting critical nets or preplacing CLBs prior to
design completion using APRIPPR, to more extensive
control over logic partitioning and placement into CLBs.
The DeSign Implementation software gives the designer
an option for direct control over specific logic mapped into
CLBs (partitioning) to provide better distribution of logic
signal routing through the LCA device. The XACT Design
Editor, XDE, is extremely versatile, ranging from design
entry to CLB and signal routing manipulations. This combination of automatic and interactive deSign editing capability is a unique feature provided by Xilinx.
PlaHorm and Environment Support
The Xilinx Automatic CAE Tools, XACT, are currently
available for the following platforms:
•
'386/'486 PCs, PS/2, and compatibles
•
•
HP700 Series
Sun-4 and SparcStation Series
Xilinx and third-party vendors have developed library and
interface products compatible with a variety of design entry
and simulation environments. Xilinx has provided a standardinterface file specification, XNF, to simplify file transfers into and out of the XACT Development System.
Xilinx directly supports the following design environments:
Logic simulation or actual in-circuit emulation provides for
functional verification, while timing analysis permits verification of critical timing paths under worst-case conditions.
The system contains a compiler to generate bitstream
patterns to configure the LCA device according to the
designer's specification. The overall design flow is illustrated on page 7-3.
•
Viewlogic Viewdraw and Viewsim
•
Mentor Graphics Design Architect and Quicksim II
•
OrCAD SDT and VST
Several other environments are supported by third-party
vendors.
The XACT DesignManager, XDM, simplifies the selection
of command-line options with pull-down menus and online help text. Application programs ranging from schematic capture to APR/PPR can be accessed from the
XDM, while the sequence of program commands is generated and stored for documentation prior to execution. The
XMAKE command in theXDM automates the entire translation, optimization, merging, and mapping process.
An important feature of the XACT Development System is
the capability to incorporate design changes, frequently
encountered during verification. Small changes can be
made to the schematics and then automatically incorporated into the existing design with minimal impact on
existing routing and performance. Using this "incremental
design" capability, the designer can develop "production
7-3
I
Development Systems
Step 1
Macro
&
MSI
Libraries
Design
Entry
Xilinx
ABEL
DS-371
l
l
~
r-
It
J
State
Machine
Entry
Viewlogic
DS-39D-PCl
DS-391-PCl
DS-391-SN2
OrCAD
DS-35
MentorV8.x
DS-344-SN2
DS-344-HP7
Other
Schematic
--d
Entry
r-
J-
Xilinx Logic Library & XNF Interface
JI
I
I
HDLNHDL
Synthesis
DS-401
Interface
J
J
j
l
~
Logic
Synthesis
11
L
I
I
DS-502
J.
")
XNF Netlist
~
J
0
Logic Reduction
Partitioning & Optimization
Translation Into
CLBs& lOBs
0
Step2
1C
Design
Implementatlon
LCA Nellist
--"
Place & Route
"
lb(
LCA Block &
Net Timing
Report
J=u
Interactive
Design Editor
)dJ
Q
XNF Nellis!
Annotated
J
}~ranslated & Routed
Timing Annotation
Bit Stream Compiler
MakeBits & MakePROM
jL.
LJ-,
'----V
Logic
Cell
Array
Step 3
Gate Level
Simulation
Logic &
Timing
Simulation
Design
Verification
7
7
II
In-Circuit Design
Verification
F
Serial Configuration
PROM Programmer
~
~J.
Xilinx
Serial PROMs
J
J
X3259
FPGA Design Flow
7-4
Design Iteration
Design
Entry
Behavioral
Tools
• PALASM-2
• ABEL
'CUPl
• logic IIC
JEDEC
Files
-Viewdraw
'OrCAD
SOT
Boolean
Equations
Netlist
logic
Bit-map
PlUSASM
Complier
Design
Implementation
'JEDEClmporter~______-"
• Partitioner
• Minimizer
'DRC
• Optimizer
• Muncher
• Mapper
• Intercpnnector
Simulation
Model File
Reports
Design
Verification
Simulator
·Viewsim
'OrCAD
VST
• Pin-List
Report
• Mapping
Report
• Resource
Report
Programmer
Bit-map
X3227
EPLD Design Flow
I
7-5
Development Systems
7-6
The Xilinx Design Manager-Simplifies the Design Flow
•
Permits running all Xilinx software from menus
•
•
XMake facility automates design translation
Provides on-line help for all menus, programs and
options
X4042
I
XMake Command
Extensive On-line Help
•
Automatically invokes all other translation programs
as required to compile a design into an FPGA or
EPLD
The Design Manager contains on-line Help for
•
Every menu
•
Supports hierarchically structured designs
•
Every program
•
Every program option
•
Design-flow suggestions
7-7
Development Systems
FPGA Design Flow
STEP 1
XNFNETLIST
OUTPUT
Design Entry
x"',.
•
•
Open development system supports design entry
and simulation on popular CAE systems
Interfaces available from Xilinx for PC- and
workstation-based environments:
•
Standard macro library includes over 300 elements
•
Several other PC and workstation environments are
supported by third-party vendors
•
Xilinx ABEL provides efficient state machine
implementation for lCA architecture
•
Synthesis from behavioral hardware description
languages (HDls) to lCA device with interfaces to
Synopsys and Viewlogic
- Viewdraw, OrCAD, Mentor V8
- XACT-Performance allows designers to enter their
design performance requirements directly in their
schematic
XEPLD Design Flow
STEP 1
Schematic
Design Entry
NETLIST
OUTPUT
Text Editor/HDL
PLUSASM
X1837
Open development system supports design entry and
simulation on popular CAE systems.
• logic Compilers, including state-machine entry ABEL, CUPl, logic IIC
• Schematic Capture tools - OrCAD, Viewlogic
• Boolean Equation format - PALASM-2, PlUSASM
7-8
FPGA Design Flow (continued)
sTEP2
STEP 3
Design
Implementation
BITSTREAM
FILE OUTPUT
Design
Verification
X3237
•
Complete system translates design into programmable gate arrays
•
Performance based on specified timing requirements
•
Partitions gate-level design logic into lCA architecture (ClB/lOB)
•
Automatic logic reduction and partitioning removes
unused logic, e.g. unused counter outputs
•
X-BlOX synthesis software optimizes design for
lCA architecture
•
•
Interfaces available from Xilinx to popular simulators
for logic and full timing simulation
- Mentor Graphics
- Viewlogic
- OrCAD
Several other simulators are supported by third-party
vendors
•
lCA user-programmability permits real time, in-circuit
debugging
•
XChecker download cable allows the lCA device to
be programmed in-circuit during debugging
XEPLD Design Flow (continued)
sTEP2
Design
Implementation
sTEP3
Modeling and
Timing Information
Design
Verification
X1838
•
The Optimizer module optimizes components, such
as ANDs, inverters, flip-flops, so that they, whenever
possible, consume no Macrocell resources and incur
no propagation delay.
•
The DRC module checks the design for EPlD
design-rule violations.
•
The Muncher module identifies and eliminates
unused resources, e.g., unconnected outputs.
•
The Mapper module maps the specified components
onto appropriate resources of the EPlD device.
7-9
•
The Interconnector module connects all components
that were mapped into the EPLD device.
•
The Programmer module generates a fuse map file,
which is down loaded to a third party or XEPlD
programmer unit that is used to program the EPLD
device.
•
The XEPLD translator produces simulation models.
•
The Reporter module generates pin-out information
and resource-utilization results.
I
Development Systems
Packages for the PC
Viewlogic
Base Standard Extended
Feature
Libraries and Interface
Schematic Editor
Simulator (LimHed Gates)
Simulator (Unlimited Gates)
EPLD Devices XC7200, XC7300
FPGA Devices up to XC3130
FPGA Devices 2K, 3K, 4K
Core Implementation Tools
XDE (Xilinx Design EdHor)
Synthesis Tools
X·BLOX
Parallel Download Cable
XChecker Cable
XC3000 Demonstration Board
XC4000 Demonstration Board
Telephone Support
1 Year Support and Updates
./
./
./
./
./
./
./
./
./
./
./
./
./
./
Base
ViewlogiclS
Extended
SIandard
./
./
./
./
./
./
./
./
./
./
./
./
./
./
./
./
./
./
./
./
./
./
./
./
./
./
OrCAD
Base S1andard
./
./
./
./
./
./
./
./
./
./
./
./
./
./
./
./
./
./
./
./
./
./
./
./
./
./
./
./
./
./
./
./
./
./
./
./
./
./
./
./
./
Packages for Workstations
Feature
Libraries and Interface
EPLD Devices XC7200, XC7300
FPGA Devices up to XC3130
FPGA Devices 2K, 3K, 4K
Core Implementation Tools
XDE (Xilinx Design Editor)
Synthesis Tools
X·BLOX
Parallel Download Cable
XChecker Cable
XC3000 Demonstration Board
XC4000 Demonstration Board
Telephone Support
1 Year Support and Updates
Base
./
./
./
./
Viewlogic
S1andard
Extended
Mentor
S1andard
Extended
./
./
./
./
./
./
./
./
./
./
./
./
./
./
./
./
./
./
./
./
./
./
./
./
./
./
./
./
./
./
./
./
./
./
./
./
./
./
./
./
./
./
./
X3229
7-10
Individual Products for pes and Workstations
PC
Individual Products
Workstations
Sun-4
./
./
./
./
ViewloQic FPGA Interface (DS-391)
Viewloaic Schematic Editor (oS-390)
Viewloaic Simulator (oS-290)
DrCAD FPGA Interface (DS-35)
Mentor V8FPGA Interface (OS-344)
Cadence FPGA Interface
Svnoosvs FPGA Interface (OS-401\
FPGA Core Implementation (DS-502)
EPLO Core Implementation (OS-550)
X-BLDX (OS-380)
Xilinx Abel (oS-371\
Parallel Download Cable
XChecker Cable
XC3000 Demonstration Board
XC4000 Demonstration Board
./
./
./
./
./
./
./
./
HP7
./
./
./
./
./
./
./
./
./
./
./
./
./
./
./
./
./
./
X3ZlO
II
7-11
Development Systems
7-12
~
Bundled Packages Product Descriptions
Table of Contents
OrCAD - Base System (PC) ................................ 7-14
OrCAD - Standard System (PC) ......................... 7-15
Viewlogic Viewlogic Viewlogic Viewlogic Viewlogic Viewlogic View logic Viewlogic -
Base System (PC) ............................ 7-16
Standard System (PC) ...................... 7-17
Extended System (PC) ..................... 7-12
BaselS System (PC) ......................... 7-19
StandardlS System (PC) .................. 7-20
ExtendedlS System (PC) .................. 7-21
Standard System (Sun-4) ................. 7-22
Extended System (Sun-4) ................ 7-23
Mentor VB Mentor VB Mentor VB Mentor VB -
Standard System (Sun-4) ................ 7-24
Extended System (Sun-4) ............... 7-25
Standard System (HP700 Series) ... 7-26
Extended System (HP700 Series) .. 7-27
II
7-13
Development Systems
OrCAD - Base System (PC)
Base System
Required System Environment
• Schematic Interface for OrCAD SDT/SDT386+ with
library support for XC2000 and XC3000/XC3100
FPGAs and XC7200/XC7300 EPLDs
• Fully compatible PC386/486
• Functional and Timing Simulation Interface for
OrCAD VSTNST386+
• Core implementation software for XC7200/xC7300
EPLDs and FPGA device support from XC2064
through XC3130
• XC3000 Demonstration Board
• Parallel Download Cable
• MS-DOS version 5.0 or greater
• Minimum 50 Mbyte hard-disk space for Xilinx
software
• One 3.5" or 5.25" high-density floppy disk drive
• VGA display
• One parallel and two serial ports
• 8 Mbyte of RAM
• Mouse
Support and Updates
Package Features - OrCAD PC
• Telephone support, 1-800-255-7778, for six
months
Feature
• Access to Xilinx bulletin board
Libraries and Interface
Schematic Editor
Simulator (Limited)
Simulator (Unlimited)
EPLD
FPGA up to XC3130
FPGA 2K, 3K, 4K
Core Implementation
XDE (Design Editor)
Synthesis Tools
X·BLOX
Parallel Download
XChecker Cable
3K Demoboard
4K Demoboard
Telephone Support
1 Yr Support, Updates
• Apps FAX
Notes
• 1-800 telephone support is included for the first 6
months only. Additional support or Updates may be
purchased separately.
• This package does not include the OrCAD SOT
schematic capture or VST simulation tools. They
must be purchased separately from OrCAD.
Base Std.
,/
,/
,/
,/
,/
,/
,/
,/
,/
,/
,/
,/
,/
./
./
./
./
><3232
7-14
OrCAD - Standard System (PC)
Standard System
• Schematic Interface for OrCAD SDT/SDT386+ with
library support for XC2000, XC3000/xC31 00, and
XC4000 FPGAs and XC7200/XC7300 EPLDs
• Functional and Timing Simulation Interface for
OrCAD VSTNST386+
• Core implementation software for XC7200/XC7300
EPLDs (DS-550) and FPGAs (DS-502) with device
support for all families (XC2000, XC3000/xC3100,
and XC4000)
• XC3000 and XC4000 demonstration boards
• XChecker Diagnostic Cable
• Software Support and Updates for first year
Required System Environment
• Fully compatible PC386/486
• MS-DOS version 5.0 or greater
• Minimum 80 to 100 Mbyte hard-disk space for
Xilinx software
• One 3.5" or 5.25" high-density floppy disk drive
• VGA display
• One parallel and two serial ports
• 8 Mbytes of RAM for devices up to XC4006
• 16 Mbytes of RAM for XC4008 and above
• Mouse
Support and Updates
Package Features - OrCAD PC
• Telephone support, 1-800-255-7778, for the first
year
Feature
Libraries and Interlace
Schematic Ed~or
Simulator (Limited)
Simulator (Unlim~ed)
EPLD
FPGA up to XC3130
FPGA 2K, 3K, 4K
Core Implementation
XDE (Design Editor)
Synthesis Tools
X-BLOX
Parallel Download
XChecker Cable
3K Demoboard
4K Demoboard
Telephone Support
1 Yr Support, Updates
• Access to Xilinx bulletin board
• Apps FAX
• Software Updates for one year
• Documentation Updates
Note
• This package does not include the OrCAD SOT
schematic capture or VST simulation tools. They
must be purchased separately from OrCAD. Xilinx
recommends VST386+ for simulation above 4200
gates.
Base Std.
,/
,/
,/
,/
,/
,/
,/
,/
,/
,/
,/
,/
,/
,/
,/
,/
,/
X3232
7-15
II
Development Systems
Viewlogic - Base System (PC)
Base System
Required System Environment
• Schematic Interface for Viewdraw with library
support for XC2000 and XC3000/xC31 00 FPGAs
and XC7200/xC7300 EPLDs
• Fully compatible PC386/486
• Functional and Timing Simulation Interface for
Viewsim
• Core implementation software for XC7200/XC7300
EPLDs and FPGA device support from XC2064
through XC3130
• XC3000 Demonstration Board
• Parallel Download Cable
Support and Updates
• Telephone support, 1-800-255-7778, for first six
months
• Access to Xilinx bulletin board
• Apps FAX
• MS-DOS version 5.0 or greater
• Minimum 60 Mbytes disk space
• One 3.5" or 5.25" high-density floppy drive
• VGA display
• Three-button serial mouse with driver support of
Mouse System Emulation (5-bytes packed binary
format). Suggested mice include - Logitech:C7,
Cg, Mouseman Combo, Trackman Combo, Mouse
Systems: M4, PC Mouse, White Mouse, PC
Accessories: Budget 260 Serial
• One parallel and two serial ports
• 8 Mbytes of RAM
• Quarterdeck EMM (QEMM-386) provided with
system
• Software Updates for one year
Package Features - Viewlogic PC
• Documentation Updates
Feature
Note
Libraries and Interface
Schematic Editor
Simulator (Limited)
Simulator (Unlimited)
EPLD
FPGA up to XC3t30
FPGA 2K, 3K, 4K
Core Implementation
XDE (Design Editor)
Synthesis Tools
X-BLOX
Parallel Download
XChecker Cable
3K Demoboard
4K Demoboard
Telephone Support
1 Yr Support, Updates
• This package includes 1-800 telephone support for
six months. Additional Hotline Support and
Updates can be purchased.
• This package does not include Viewdraw
schematic capture or Viewsim simulation tools.
They must be purchased separately from Viewlogic
or Xilinx (see IS packages).
• Interface supports Workview 4.X, ProSeries
software and Workview PLUS.
Base Std.
,/
,/
Ext.
,/
Base Std.
Ext.
IS
IS
,/
,/
IS
,/
,/
,/
,/
,/
,/
,/
,/
,/
,/
,/
,/
,/
,/
,/
,/
,/
,/
,/
,/
,/
,/
,/
,/
,/
,/
,/
,/
,/
,/
,/
,/
,/
,/
,/
,/
,/
,/
,/
,/
,/
,/
,/
,/
,/
,/
,/
,/
,/
,/
,/
,/
,/
,/
,/
,/
,/
,/
,/
X3233
7-16
Viewlogic - Standard System (PC)
Standard System
Required System Environment
• Schematic Interface for Viewdraw with library
support for XC2000, XC3000/XC3100, XC4000
FPGAs and XC7200/xC7300 EPLDs
• Fully compatible PC386/486
• Functional and Timing Simulation Interface for
Viewsim
• Core implementation software for XC7200/XC7300
EPLDs (DS-550) and FPGAs (DS-502) with device
support for all families (XC2000, XC3000/xC3100,
and XC4000)
• XC3000 and XC4000 Demonstration Boards
• XChecker Diagnostic Cable
Support and Updates
• Telephone support, 1-800-255-7778, for first year
• Access to Xilinx bulletin board
• Apps FAX
• Software Updates for one year
• MS-DOS version 5.0 or greater
• Minimum 80 to 100 Mbytes hard-disk space for
Xilinx software
• One 3.5" or 5.25" high-density floppy drive
• VGA display
• Three-button serial mouse with driver support of
Mouse System Emulation (5-bytes packed binary
format). Suggested mice include - Logitech:C7,
Cg, Mouseman Combo, Trackman Combo, Mouse
Systems: M4, PC Mouse, White Mouse, PC
Accessories: Budget 260 Serial
• One parallel and two serial ports
• 8 Mbytes of RAM for devices up to XC4006
• 16 Mbytes of RAM for XC4008 and above
• Quarterdeck EMM (QEMM-386) provided with
system
• Documentation Updates
Note
Package Features - Viewlogic PC
• This package does not include Viewdraw
schematic capture or Viewsim simulation tools.
They must be purchased separately from Viewlogic
or Xilinx (see IS packages).
Feature
Libraries and Interface
Schematic EdHor
Simulator (Limited)
Simulator (Unlimiled)
EPLD
FPGA up to XC3130
FPGA 2K, 3K, 4K
Core Implementalion
XDE (Design Editor)
Synthesis Tools
X-BLOX
Parallel Download
XChecker Cable
3K Demoboard
4K Demoboard
Telephone Support
1 Yr Support, Updates
• Interface supports Workview 4.X, ProSeries
software and Workview PLUS.
Base Std.
,/
,/
Ext.
,/
Base Std.
Ext.
IS
IS
IS
,/
,/
,/
,/
,/
,/
,/
,/
,/
,/
,/
,/
,/
,/
,/
,/
,/
,/
,/
,/
,/
,/
,/
,/
,/
,/
,/
,/
,/
,/
,/
,/
,/
,/
,/
,/
,/
,/
,/
,/
,/
,/
,/
,/
,/
,/
,/
,/
,/
,/
,/
,/
,/
,/
,/
,/
,/
,/
,/
,/
,/
><3233
7-17
II
Development Systems
Viewlogic - Extended System (PC)
Extended System
Required System Environment
• Schematic Interface for Viewdraw with library
support for XC2000, XC3000/XC3100, XC4000
FPGAs and XC7200/xC7300 EPLDs
• Fully compatible PC386/486
• Functional and Timing Simulation Interface for
Viewsim
• MS-DOS version 5.0 or greater
• Minimum 80 to 100 Mbytes disk space
• One 3.5" or 5.25" high-density floppy drive
• X-BLOX Architectural Synthesis
• VGA display
• Core implementation software for XC7200/XC7300
EPLDs (DS-550) and FPGAs (DS-502) with device
support for all families (XC2000, XC3000/xC31 00,
and XC4000)
• Three-button serial mouse with driver support of
Mouse System Emulation (5-bytes packed binary
format). Suggested mice include - Logitech:C7,
Cg, Mouseman Combo, Trackman Combo, Mouse
Systems: M4, PC Mouse, White Mouse, PC
Accessories: Budget 260 Serial
• XC3000 and XC4000 Demonstration Boards
• XChecker Diagnostic Cable
• One parallel and two serial ports
Support and Updates
• 8 Mbytes of RAM for devices up to XC4006
• Telephone support, 1-800-255-7778, for first year
• 16 Mbytes of RAM for XC4008 and above
• Access to Xilinx bulletin board
• Quarterdeck EMM (QEMM-386) provided with
system
• Apps FAX
• Software Updates for one year
Package Features - Viewlogic PC
• Documentation Updates
Feature
Note
Ubraries and Interface
Schematic Editor
Simulator (Umited)
Simulator (Unlimited)
EPLD
FPGA up to XC3130
FPGA 2K, 3K, 4K
Core Implementation
XDE (Design Editor)
Synthesis Tools
X·BLOX
Parallel Download
XChecker Cable
3K Demoboard
4K Demoboard
Telephone Support
1 Yr Support, Updates
• This package does not include Viewdraw
schematic capture, Viewsim simulation or
ViewSynthesis tools. They must be purchased
separately from Viewlogic or Xilinx (see IS
packages).
• Interface supports Workview 4.X, ProSeries
software and Workview PLUS.
Base Std.
Ext.
Base Std.
IS
IS
.t
.t
.t
.t
.t
.t
.t
.t
.t
.t
.t
.t
.t
.t
.t
.t
.t
.t
.t
.t
.t
.t
.t
.t
.t
.t
.t
.t
.t
.t
.t
.t
.t
.t
.t
.t
.t
.t
.t
.t
.t
.t
.t
.t
.t
.t
.t
.t
.t
.t
Ext.
IS
.t
.t
.t
.t
.t
.t
.t
.t
.t
.t
.t
.t
.t
.t
X3233
7-18
Viewlogic - BaselS System (PC)
BaselS System
Required System Environment
• Viewdraw Schematic editor with library support for
XC2000 and XC3000IXC3100 FPGAs and
XC7200IXC7300 EPLDs
• Fully compatible PC386/486
• Viewsim Functional and Timing Simulation for
designs up to 5,000 gates
• Core implementation software for XC7200/XC7300
EPLDs and FPGA device support from XC2064
through XC3130
• XC3000 Demonstration Board
• Parallel Download Cable
Support and Updates
• Telephone support, 1-800-255-7778, for first year
• Access to Xilinx bulletin board
• Apps FAX
• Software Updates for one year
• MS-DOS version 5.0 or greater
• Minimum 70 Mbytes hard-disk space for Xilinx
software
• One 3.5" or 5.25" high-density floppy disk drive
• VGA display
• Three-button serial mouse with driver support of
Mouse System Emulation (5-bytes packed binary
format). Suggested mice include - Logitech:C7,
C9, Mouseman Combo, Trackman Combo, Mouse
Systems: M4, PC Mouse, White Mouse, PC
Accessories: Budget 260 Serial
• One parallel and two serial ports
• 8 Mbytes of RAM
• Quarterdeck EMM (QEMM-386) provided with
system
• Documentation Updates
Package Features - Viewlogic PC
Feature
Libraries and Interface
Schematic Editor
Simulator (Limited)
Simulator (Unlimited)
EPLD
FPGA up to XC3130
FPGA 2K, 3K, 4K
Core Implementation
XDE (Design Editor)
Synthesis Tools
X·BLOX
Parallel Download
XChecker Cable
3K Demoboard
4K Demoboard
Telephone Support
1 Yr Support, Updates
Base Std. Ext.
Base Std.
IS
IS
.t
.t
.t
.t
.t
.t
.t
.t
.t
.t
.t
.t
.t
.t
.t
.t
.t
.t
.t
.t
.t
.t
.t
.t
.t
.t
.t
.t
.t
.t
.t
.t
.t
.t
.t
.t
.t
.t
.t
.t
.t
.t
.t
.t
.t
.t
.t
.t
.t
.t
.t
Ext.
IS
.t
.t
.t
.t
.t
.t
.t
.t
.t
.t
.t
.t
.t
><3233
7-19
II
Development Systems
Viewlogic - StandardlS System (PC)
StandardlS System
Required System Environment
• Viewdraw Schematic editor with library support for
XC2000, XC30001XC3100, XC4000 FPGAs and
XC7200/XC7300 EPLDs
• Fully compatible PC386/486
• Viewsim Functional and Timing Simulation
(unlimited gates)
• Minimum 90 to 110 Mbytes hard-disk space for
Xilinx software
• Core implementation software for XC7200IXC7300
EPLDs (DS-550) and FPGAs (DS-502) with device
support for all families (XC2000, XC3000IXC3100,
and XC4000)
• One 3.5" or 5.25" high-density floppy disk drive
• MS-DOS version 5.0 or greater
• VGA display
Support and Updates
• Three-button serial mouse with driver support of
Mouse System Emulation (5-bytes packed binary
format). Suggested mice include - Logitech:C7,
C9, Mouseman Combo, Trackman Combo, Mouse
Systems: M4, PC Mouse, White Mouse, PC
Accessories: Budget 260 Serial
• Telephone support, 1-800-255-7778, for first year
• One parallel and two serial ports
• Access to Xilinx bulletin board
• 8 Mbytes of RAM for devices up to XC4006
• XC3000 and XC4000 Demonstration Boards
• XC hecker Diagnostic Cable
• Apps FAX
• Software Updates for one year
• 16 Mbytes of RAM for XC4008 and above
• Quarterdeck EMM (QEMM-386) provided with
system
• Documentation Updates
Package Features - Viewlogic PC
Feature
Libraries and Interface
Schematic Editor
Simulator (Limited)
Simulator (Unlimited)
EPLD
FPGA up to XC3130
FPGA 2K, 3K, 4K
Core Implementation
XDE (Design Editor)
Synthesis Tools
X·BLOX
Parallel Download
XChecker Cable
3K Demoboard
4K Demoboard
Telephone Support
1 Yr Support, Updates
Base Std.
Ext.
Base Std.
IS
IS
.t
.t
.t
.t
.t
.t
.t
.t
.t
.t
.t
.t
.t
.t
.t
.t
.t
.t
.t
.t
.t
.t
.t
.t
.t
.t
.t
.t
.t
.t
.t
.t
.t
.t
.t
.t
.t
.t
.t
.t
.t
.t
.t
.t
.t
.t
.t
.t
.t
.t
Ext.
IS
.t
.t
.t
.t
.t
.t
.t
.t
.t
.t
.t
.t
.t
.t
X3233
7-20
Viewlogic - Extended/S System (PC)
ExtendedlS System
Required System Environment
• Viewdraw Schematic editor with library support for
XC2000, XC3000/XC31 00, XC4000 FPGAs and
XC7200IXC7300 EPLDs
• Fu"y compatible PC386/486
• Viewsim Functional and Timing, and VHDL
Simulation (unlimited gates)
• ViewSynthesis- VHDL synthesis with X-BLOX
naming integration and synthesis library support for
XC2000, XC3000/XC31 00, and XC4000 FPGAs
• X-BLOX Architectural Synthesis
• Core implementation software for XC7200/XC7300
EPLDs (DS-550) and FPGAs (DS-502) with device
support for a" families (XC2000, XC3000IXC31 00,
and XC4000)
• XC3000 and XC4000 Demonstration Boards
• XC hecker Diagnostic Cable
• MS-DOS version 5.0 or greater
• Minimum 90 to 110 Mbytes hard-disk space for
Xilinx software
• One 3.5" or 5.25" high-density floppy drive
• VGA display
• Three-button serial mouse with driver support of
Mouse System Emulation (5-bytes packed binary
format). Suggested mice include - Logitech:C7,
C9, Mouseman Combo, Trackman Combo, Mouse
Systems: M4, PC Mouse, White Mouse, PC
Accessories: Budget 260 Serial
• One para"el and two serial ports
• 8 Mbytes of RAM for devices up to XC4006
• 16 Mbytes of RAM for XC4008 and above
Support and Updates
• Telephone support, 1-800-255-7778, for first year
• Quarterdeck EMM (QEMM-386) provided with
system
• Access to Xilinx bulletin board
• Apps FAX
Package Features - Viewlogic PC
• Software Updates for one year
Feature
• Documentation Updates
Libraries and Interface
Schematic Editor
Simulator (Limited)
Simulator (Unlimited)
EPlD
FPGA up to XC3130
FPGA 2K, 3K, 4K
Core Implementation
XDE (Design Editor)
Synthesis Tools
X-BlOX
Parallel Download
XChecker Cable
3K Demoboard
4K Demoboard
Telephone Support
1 Yr Support, Updates
Base Std.
./
./
Ext.
./
Base Std.
tS
tS
./
./
./
./
Ext.
IS
./
./
./
./
./
./
./
./
./
./
./
./
./
./
./
./
./
./
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X3233
7-21
II
Development Systems
Viewlogic - Standard System (Sun-4)
Standard System
Required System Environment
• Schematic Interface for Viewdraw with library
support for XC2000, XC3000/XC31 00 and XC4000
FPGAs and XC7200IXC7300 EPLDs
• Sun-4 running SUN OS 4.1.x
• Functional and Timing Simulation Interface for
Viewsim
• Core implementation software for XC7200/XC7300
EPLOs (OS-550) and FPGAs (OS-502) with device
support for all families (XC2000, XC30001XC3100,
and XC4000)
• XC3000 and XC4000 Demonstration Boards
• Graphic monitor (color recommended)
• X-Windows or Open Windows support
• 32 Mbytes of RAM is highly recommended for
XC3090, XC3190, XC3195 or XC4000 designs
• Swap space: 50 Mbytes
• TCP/IP software
• Minimum 80 to 100 Mbytes hard-disk space for
Xilinx software
• XChecker Oiagnostic Cable
Support and Updates
Package Features - Viewlogic Sun-4
• Telephone support, 1-800-255-7778, for first year
Feature
• Access to Xilinx bulletin board
Libraries and Interface
Schematic Editor
Simulator (Limited)
Simulator (Unlimited)
EPLD
FPGA up to XC3130
FPGA 2K, 3K, 4K
Core Implementation
XDE (Design Ednor)
Synthesis Tools
X·BLOX
Parallel Download
XChecker Cable
3K Demoboard
4K Demoboard
Telephone Support
1 Yr Support, Updates
• Apps FAX
• Software Updates for one year
• Documentation Updates
Note
• This package does not include Viewdraw
schematic capture or Viewsim simulation tools.
They must be purchased separately from
Viewlogic.
• Interface supports Workview 4.1 and Powerview
5.0 or higher.
7-22
Std.
Ext.
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./
Viewlogic - Extended System (Sun-4)
Extended System
Required System Environment
• Schematic Interface for Viewdraw with library
support for XC2000, XC3000/xC3100 and XC4000
FPGAs and XC7200/xC7300 EPLDs
• Sun-4 running SUN OS 4.1.x
• Functional and Timing Simulation Interface for
Viewsim
• X-BLOX Architectural Synthesis
• Core implementation software for XC7200/XC7300
EPLDs (DS-550) and FPGAs (DS-502) with device
support for all families (XC2000, XC3000/xC31 00,
and XC4000)
• Graphical monitor (color recommended)
• X-Windows or Open Windows support
• 32 Mbytes of RAM is highly recommended for
XC3090, XC3190, XC3195 or XC4000 deSigns
• Swap space: 50 Mbytes
• TCP/IP software
• Minimum 80 to 100 Mbytes hard-disk space for
Xilinx software
• XC3000 and XC4000 Demonstration Boards
• XChecker Diagnostic Cable
Package Features - Viewlogic Sun-4
Support and Updates
Feature
• Telephone support, 1-800-255-7778, for first year
Libraries and Interface
Schematic Ednor
Simulator (Lim~ed)
Simulator (Unlimned)
EPLD
FPGA up to XC3130
FPGA 2K, 3K, 4K
Core Implementation
XDE (Design Editor)
Synthesis Tools
X-BLOX
Parallel Download
XChecker Cable
3K Demoboard
4K Demoboard
Telephone Support
1 Yr Support, Updates
• Access to Xilinx bulletin board
• Apps FAX
• Software Updates for one year
• Documentation Updates
Note
• This package does not include Viewdraw
schematic capture or Viewsim simulation tools.
They must be purchased separately from
Viewlogic.
• Interface supports Workview 4.1 and Powerview
5.0 or higher.
Std.
Ext.
./
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><3234
7-23
II
Development Systems
Mentor va - Standard System (Sun-4)
Standard System
• Mentor V8 Interface (Mentor Design Architect!
QuickSim II Libraries and Interface)
• Core implementation software for FPGAs (DS-502)
with device support for all families (XC2000,
XC30001XC31 00, and XC4000)
• XC3000 and XC4000 Demonstration Boards
• XChecker Diagnostic Cable
Required System Environment
Sun-4 SparcStation Series
• SUN OS 4.1X
• Mentor Graphics Version 8
• 50 to 200 Mbytes disk space allocated for Xilinx
designs
• 32 Mbytes of RAM
• Color Monitor
Support and Updates
• Telephone support, 1-800-255-7778, for first year
• Access to Xilinx bulletin board
• Apps FAX
• X11 R4 Windows Support
• Open Windows 2.0
• Swap Space: Min 125 Mbytes
• TCP/IP Software
• Software Updates for one year
Recommended Hardware
• Documentation Updates
• All of above plus maximum RAM for SparcStation
Notes
• This package does not include Design Architect
schematic capture, or QuickSim II simulation tools.
Contact your local Mentor Graphics sales office to
purchase these tools.
Package Features - Mentor Sun-4
Feature
• Auto Logic synthesis program, libraries and
interface are available from Mentor Graphics.
Libraries and Interface
Schematic Editor
Simulator (Limited)
Simulator (Unlimited)
EPLD
FPGA up to XC3130
FPGA 2K, 3K, 4K
Core Implementation
XDE (Design Editor)
Synthesis Tools
X-BLOX
Parallel Download
XChecker Cable
3K Demoboard
4K Demoboard
Telephone Support
1 Yr Support, Updates
Std.
Ext.
.I
.I
.I
.I
.I
.I
.I
.I
.I
.I
.I
.I
.I
.I
.I
.I
.I
.I
.I
X3235
7-24
~XILINX
Mentor va - Extended System (Sun-4)
Extended System
Required System Environment
• Mentor V8 Interface (Mentor Design Architect!
QuickSim II Libraries and Interface)
Sun-4 SparcStation Series
• SUNOS4.1X
• Core implementation software for FPGAs (DS-502)
with device support for all families (XC2000,
XC3000/xC3100, and XC4000)
• 50 to 200 Mbytes of disk space allocated for Xilinx
designs
• X-BLOX Architectural Synthesis
• 32 Mbytes of RAM
• XC3000 and XC4000 Demonstration Boards
• Color Monitor
• XChecker DiagnostiC Cable
• X11 R4 Windows Support
• Open Windows 2.0
Support and Updates
• Telephone support, 1-800-255-7778, for first year
• Swap Space: 125 Mbytes minimum
• TCP/IP Software
• Access to Xilinx bulletin board
• Apps FAX
• Software Updates for one year
Recommended Hardware
• All of above plus maximum RAM for SparcStation
• Documentation Updates
Package Features - Mentor Sun-4
Notes
Std. Ext.
Feature
• This package does not include Design Architect
schematic capture, or QuickSim II simulation tools.
Contact your local Mentor Graphics sales. office to
purchase these tools.
Ubraries and Interiace
Schematic Editor
Simulator (Umited)
Simulator (UnlirilHed)
EPLO
FPGA up to XC3130
FPGA 2K, 3K, 4K
Core Implementation
XOE (Design EdHor)
Synthesis Tools
X·BLOX
Parallel Download
XChecker Cable
3K Demoboard
4K Demoboard
Telephone Support
1 Yr Support, Updates
• Auto Logic synthesis program, libraries and
interface are available from Mentor Graphics
7-25
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II
Development Systems
Mentor va - Standard System (HP700 Series)
Standard System
Required System Environment
• Mentor V8 Interface (Mentor Design Architect!
QuickSim II Libraries and Interface)
HP700 Series
• Core implementation software for FPGAs (DS-502)
with device support for all families (XC2000,
XC3000/XC31 00, and XC4000)
• XC3000 and XC4000 Demonstration Boards
• XChecker Diagnostic Cable
• HPUX 8.07
• 50 to 150 Mbytes of hard-disk space allocated for
Xilinx designs
• 32 Mbytes of RAM
• Color Monitor
• X11 R4 Windows Support
Support and Updates
• Telephone support, 1-800-255-7778, for first year
• Access to Xilinx bulletin board
• HP-VUE 2.01
• Swap Space: 140 Mbytes minimum
• TCP/IP Software
• Apps FAX
• Software Updates for one year
• Documentation Updates
Recommended Hardware
• All of above plus maximum RAM for HP700
Notes
Package Features - Mentor Sun-4
• This package does not include Design Architect
schematic capture, or QuickSim II simulation tools.
Contact your local Mentor Graphics sales office to
purchase these tools.
Feature
Libraries and Interface
Schematic Editor
Simulator (Limited)
Simulator (Unlimited)
EPLD
FPGA up to XC3130
FPGA 2K, 3K, 4K
Core Implementation
XDE (Design Editor)
Synthesis Tools
X·BLOX
Parallel Download
XChecker Cable
3K Demoboard
4K Demoboard
Telephone Support
1 Yr Support, Updates
• Auto Logic synthesis program, libraries and
interface are available from Mentor Graphics.
Std.
Ext.
.I
.I
.I
.I
.I
.I
.I
.I
.I
.I
.I
.I
.I
.I
.I
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.I
.I
.I
X3235
7-26
Mentor va - Extended System (HP700 Series)
Extended System
Required System Environment
• Mentor VS Interface (Mentor Design Architect!
QuickSim II Libraries and Interface)
HP700 Series
• Core implementation software for FPGAs (DS-502)
with device support for all families (XC2000,
XC3000IXC31 00, and XC4000)
• X-BLOX Architectural Synthesis
• XC3000 and XC4000 Demonstration Boards
• XChecker Diagnostic Cable
• HPUX S.07
• 50 to 150 Mbytes hard-disk space allocated for
Xilinx designs
• 32 Mbytes of RAM
• Color Monitor
• X11 R4 Windows Support
• HP-VUE 2.01
Support and Updates
• Telephone support, 1-S00-255-777S, for first year
• Swap Space: 140 Mbytes minimum
• TCP/IP Software
• Access to Xilinx bulletin board
• Apps FAX
• Software Updates for one year
Recommended Hardware
• All of above plus maximum RAM for HP700
• Documentation Updates
Package Features - Mentor Sun-4
Notes
Feature
• This package does not include Design Architect
schematic capture, or QuickSim II simulation tools.
Contact your local Mentor Graphics sales office to
purchase these tools.
Libraries and Interface
Schematic Editor
Simulator (Limited)
Simulator (Unlimited)
EPLD
FPGA up to XC3130
FPGA 2K, 3K, 4K
Core Implementation
XDE (Design Editor)
Synthesis Tools
X·BLOX
Parallel Download
XChecker Cable
3K Demoboard
4K Demoboard
Telephone Support
1 Yr Support, Updates
• Auto Logic synthesis program, libraries and
interface are available from Mentor Graphics.
Std. Ext.
,/
,/
,/
,/
,/
,/
,/
,/
,/
,/
II
,/
,/
,/
,/
,/
,/
,/
,/
,/
)(3235
7-27
Development Systems
7-28
~
Individual Product Descriptions
Table of Contents
XACT Development System - OS502 ................. 7-30
XEPLD Translator for EPLDs - DS550 ............... 7-31
Schematic and Simulator Interfaces .................... 7-32
X-BLOX Architectural Synthesis - DS380 ........... 7-33
Xilinx ABEL Design Entry - DS-371 .................... 7-34
Synopsys Interface - DS401 ............................... 7-35
Parallel Download and XChecker Cables .....•...... 7-36
Demonstration Boards ......................................... 7-37
II
7-29
Development Systems
XACT Development System - DS-502
Description
The XACT Development System contains leading-edge,
automatic tools that determine optimal partitioning,
placement, and routing for a design. It includes options
for the user to control the activity of the automated tools
at several levels. Designers often need this capability for
demanding applications. User-controlled partitioning,
placement, and routing information can be specified
right on the schematic or in a text file.
The XACT Development System supports iterative and
incremental design techniques. If minor changes are
required to a completed design, a special "guide" option
permits a proven version of a design to be used as a
guide to implementing a new version. Where the two
designs match, the newer design mimics the old one
exactly, preserving its placement and timing
characteristics. Since the majority of the initial design is
preserved, previous verificatjon results are still valid.
Typically, minor changes can be implemented and
verified in a few minutes. The same option supports the
iterative construction of a large design.
Highlights
• The XACT Development System takes output from
the design entry step, processes the design
(including partitioning, placement and routing),
then creates a bitstream that can be downloaded
to a Xilinx FPGA.
• The XACT Development System may be used on
PC, Sun-4 (Sparc), HPnOO platforms
• The XACT Design Manager (XDM) provides a
framework and user interface for the entire design
process. XDM organizes the various design tools
and utility programs for implementing FPGA
designs into convenient pull-down menus. On-line
help facilities provide a short explanation of each
command and its options.
• XDM supports push-button design. With one
command, the software automatically translates a
design from the schematic to a bitstream that can
be downloaded to an FPGA.
Interactive Design Editor
The automated tools are complemented by an interactive
design editor that allows the user to view and directly
manipulate a model of the actual logic and routing
resources inside the FPGA device. The XACT Design
Editor gives the user visibility into the implementation of
the design, enabling the designer to make intelligent
choices when improving the circuit's implementation or
experimenting with different approaches.
Extensive Third-Party Support
Xilinx supports and is supported by more third-party
software interfaces than any other FPGA company. The
Xilinx Alliance Program facilitates the development and
certification of such interfaces. Designers can choose
from a wide variety of design tools ranging from schematic
entry and/or simulation (Viewlogic, Mentor, OrCAD) to
synthesis (Synopsys, Mentor Autologic, ViewSynthesis,
X-BlOX) and equation-based entry (Xilinx-ABEl).
XACT-Performance
XACT-Performance is an industry-first that permits the
user to specify exact performance requirements for a
design at the schematic level. This feature accepts
performance requirements entered at the schematic
level, then partitions, places and routes the design to
meet those performance requirements.
The Xilinx Design Manager organizes and simplifies the
entire 3-step process. Designs are entered using a
schematic editor and its associated Xilinx library of soft
and hard macros. Boolean equations and state machine
languages can be used along with schematics to describe
the design. After completing design entry, the user runs
the XMake program. Given a top-level schematic, XMake
automatically determines the design hierarchy, partitions,
places and routes the logic, and then generates a
bitstream. Once compiled, the design can be simulated
and downloaded to the target system for verification.
The DS-502 is the core design implementation product
for Xilinx FPGAs. It contains the software that partitions,
places and routes Xilinx designs. Some key product
features are shown below.
DS-502 Features
Push-Button Design
Interactive Design
Iterativeilncremental Design
Partitioning Control
Placement Control
Routing Control
Path Timing Analysis
Hard Macros
Soft Macros
Automatic Deletion of
Unused Logic
XACT-Performance
7-30
XC2OOO/
XC3ooo/XC310o
X
X
X
XC4000
X
X
40'93
X
X
X
X
X
X
X
X
X
X
X
X
40'93
X
X
I:XIIJNX
XEPLO Translator for EPLOs - OS-550
Features
General
• Reads EDIF 2 0 0 netlist files for designs entered
using a supported schematic capture tool
The translator reads Boolean equations and netlists. It
supports PAL design conversion by reading PALASM2-syntax or PLUSASM Boolean-equation files generated
by third-party compilers such as ABEL and CUPL. The
translator also reads PLUSASM-syntax files created
with an ASCII text editor. For designs entered using a
schematic capture tool, such as Workview or OrCAD,
the translator reads netlist files generated by the CAE
tool. Xilinx provides a library of components used to
express schematic designs.
• Reads PALASM-2 or PLUSASM Boolean-equation
files and JEDEC PLD fuse map files for designs
entered using a behavioral compiler tool
• Reads and assembles PLUSASM equation files
allowing complete EPLD design entry without a
front-end tool
• Includes logic minimizing, partitioning and
optimizing algorithms for efficient mapping
• Generates bit-map files for EPLD device
programming
• Generates Pinlist report, Resource report, and
Mapping report for design verification
EPLD device logic and 1/0 pin resources are automatically allocated and interconnected by the integrator,
requiring no intervention by the designer. If desired, the
user can indicate preferred or required pin pOSitions for
selected 110 signals.
• Generates models of completed designs for
simulation using a supported simulator
• Converts netlist or equation file to fuse map in
about one minute on a '486 PC
• Runs on a '386 or 486 (or compatible) PC under
DOS or on Sun-4 SparcStation
II
7-31
Development Systems
Schematic and Simulator Interfaces
Interfaces and libraries for several popular schematic
editors and timing simulators are available as individual
products, for users that already own the editor and
simulator tools. Xilinx-specific versions of the Viewlogic
Viewdraw schematic editor and Viewsim simulator can
be purchased directly from Xilinx.
Features
• Complete set of primitive and macro libraries for all
FPGA and EPLO products
• Supports unlimited levels of hierarchy
The available products are as follows:
• Converts schematic drawings to Xilinx Netlist
Format (XNF) output
OS-390 Viewdraw schematic editor with Xllinx
libraries and interface .
• Converts XNF files to format compatible with logic
and timing simulator
OS-290 Viewsim simulator with Xilinx interface
• Full simulation models provide for accurate postlayout timing analysis
OS-391 Libraries and interfaces for Viewlogic's
Workview, ProSeries, Workview PLUS and
Powerview entry and simulation tools (PC and Sun-4)
• Includes one year of support and updates
OS-344 Libraries and interfaces for Mentor Graphics
V8 Oesign Architect schematic editor and QuickSim II
simulator (HP and Sun-4)
OS-343 Libraries and interfaces for Mentor Graphics
V7 NetEd schematic editor and QuickSim simulator
(HP)
OS-35 Libraries and interfaces for OrCAO STO and
STO 386+ schematic editors and VST and VST 386+
simulators (PC)
7-32
X-BLOX Architectural Synthesis - OS-380
Easy Design
Features
Instead of entering designs tediously at the gate or SSI/
MSI macro level, the user can input them as block
diagrams, using X-BLOX software and a familiar
schematic editor. Using built-in expert knowledge,
X-BLOX software automatically optimizes the design to
take full advantage of the unique features of the Xilinx
XC4000 FPGA family.
• Schematic library with more than 30 frequently
used generic modules (adders, counters,
decoders, registers, MUXes, etc.)
The benefits of designing with X-BLOX software are
immediate and dramatic.
• Shorter design time
• Higher performance
• Maximized chip utilization
• Works with many Schematic Entry Interfaces
(Viewlogic, Mentor, OrCAD and others)
• Expert system that automatically utilizes the
advanced features of the XC4000 family
Support and Updates
• Software Updates for one year
• Documentation Updates
• Telephone support, 1-800-255-7778, for six
months
• Access to Xilinx bulletin board
• Apps FAX
Note
• XC3000NXC3100A families will be supported
4th Qtr. '93
Additional Hardware Requirement
• 5 Mbytes hard-disk space for program and design
files
I
Development Systems
Xilinx ABEL Design Entry - DS-371
The Xilinx ABEL system gives designers the ability to
enter Xilinx designs using the industry standard ABEL
Hardware Description Language (ABEL-HDL).
Designers can describe circuits with Boolean equations,
state machines and truth tables. State machine and
logic optimization software automatically generates
efficient logic for Xilinx devices.
Many designs contain portions of logic that are best
described in a text-based format; some designs can be
completely described in this way. In the Xilinx ABEL
system, Xilinx designs can be created with Boolean
equations, state machines, and truth tables. The ABEL
HDL makes designing quick and simple. Intelligent state
machine and logic optimization software automatically
creates efficient, fast state machines. The ABEL simulator
allows functional simulation of ABEL-HDL designs.
While designs may be entered entirely with ABEL-HDL,
you can also use Xilinx ABEL in conjunction with a
schematic editor to take optimal advantage of the Xilinx
architecture. The recommended design flow is to enter
designs schematically with functional blocks that
reference logic described in ABEL-HDL. From inside the
Xilinx ABEL environment, designers create and compile
the logic in these functional blocks. The Xilinx XMake
program then compiles the complete design to a bitstream
that can be downloaded to a Xilinx device. XMake
automatically calls the software that merges the various
design files (schematics and ABEL-HDL), partitions,
places and routes the design and creates the final
bitstream. The design can then be verified with a simulator
and a timing analyzer, as well as verified in-circuit.
since it uses one flip-flop per state. OHE takes advantage
of the abundance of flip-flops in Xilinx FPGAs to reduce
the levels of logic required to implement a state machine.
This implementation significantly increases performance
over fully encoded state machines, the traditional
technique used in PLDs. Xilinx ABEL automatically uses
OHE on symbolic state machines created in ABEL-HDL
for FPGAs.
Features
• State Machine and Boolean equation entry via
Data lID ABEL language
• ABEL Functional Simulator
• Xilinx-specific ABEL environment, compiler, and
optimizer for FPGAs (XC2000, XC3000, XC4000)
and EPLDs (XC7000)
• Automatic symbolic One-Hot Encoding or fully
encoded state-machine implementation
• Ability to integrate ABEL designs with other
schematic elements
Support and Updates
• Software updates for one year
• Documentation updates
• Telephone support, 1-800-255-7778, for first six
months
• Access to Xilinx bulletin board
One-Hot Encoding
• Apps FAX
For the flop-flop rich, fan-in limited Xilinx FPGA
architecture, One-Hot Encoding (OHE) is the preferred
technique for implementing high-performance state
machines. OHE is also know as State-per-Bit encoding
Additional Hardware Requirements
• 5 Mbytes hard-disk space for program and design
files
7-34
Synopsys Interface - OS-401
This interface-only product supports Synopsys VHDL
and Verilog/HDL synthesis. This package does not
include the Synopsys HDL Compiler; this must be purchased separately from Synopsys. This product does
not support the Synopsys VHDL System Simulator,
gate-level simulation, or the Test Compiler.
Features
• XC3000IXC3100 and XC4000 synthesis library
• Translator from Synopsys to Xilinx XNF
• Ability to integrate models with other design entry
methods
• Available for Sun-4, HP700, and HP400 platforms
• Support and updates for one year
I
7-35
Development Systems
Parallel Download and XChecker Cables
The parallel download or XChecker cable is included in
each of the bundled packages and in the DS-502 Core
Implementation product. Additional cables may be
purchased; contact the nearest Xilinx sales office.
Parallel download Cable package includes the following.
XChecker Cable package includes the following.
• XChecker cable
• Flying wire jumper
• Flat header jumper
• Download cable
• XChecker diagnostics test fixture
• Flying wire jumper
XC hecker Cable Features
• Flat header jumper
Parallel Download Cable Features
• Provides bitstream and PROM file download
capability
• Works with parallel ports on IBM '386/'486 and
compatibles
• Compatible with XChecker diagnostics software
and the XACT Probe utility
• Flying wire and flat header jumpers provide easy
access during prototyping
• Provides bitstream and PROM file download
capability
• Provides readback capability
• Works with serial ports on IBM '386/'486 and
compatibles
• Works with serial ports on Sun and HP/Apolio
workstations
• Compatible with XChecker diagnostics software
and the XACT Probe utility
• Flying wire and flat header jumpers provide easy
access during prototyping
7-36
Demonstration Boards
These demonstration boards are included in the bundled
packages, as applicable, and can be ordered individually. Contact your nearest Xilinx sales office.
XC3000/xC3100 Demo Board Features
XC4000 Demo Board Features
• XC4003 in 84-pin PLCC package
• Two 7-segment displays
• One 8-segment bar display
• XC3020 in 68-pin PLCC package
• 7 -segment display
• 8 dip switches for inputs to LCA devices
• 8 dip switches for inputs to LCA devices
• Test pins for access to alii/Os
• Test pins for access to aliI/Os
• Program and Reset and Spare momentary contact
switches
• Program and Reset momentary contact switches
• Operates from a 5 V power supply
• Operates from a 5 V power supply
• Compatible with XChecker and Parallel Download
Cables
• Compatible with XChecker and Parallel Download
Cables
• Supports Master Serial configuration mode for
interface to Xilinx serial PROMs
• Socket can be used for any XC3000/XC31 00
device in a 68-pin PLCC package
• Supports Master Serial configuration mode for
interface to Xilinx serial PROMs
• Provides sockets for up to three daisy-chained
Serial PROMs
• Socket can be used for any XC4000 device in an
84-pin PLCC package
I
7-37
Development Systems
7-38
SECTIONS
1
Programmable Logic Devices
2
FPGA Product Descriptions and Specifications
3
EPLD Product Descriptions and Specifications
4
Packages and Thermal Characteristics
5
Quality, Testing and Reliability
6
Technical Support
7
Development Systems
8
Applications
9
The Best of XC ELL
10 Index, Sales Offices
Applications
XAPP 000.002
Application Note Directory ....................................................................... 8-1
XAPP 024.000
Additional XC3000/XC3100 Data ............................................................ 8-6
XAPP 011.001
LCA Speed Estimation: Asking the Right Question ................................. 8-16
XAPP 015.000
Using the XC4000 Readback Capability ................................................. 8-17
XAPP 017.002
Boundary Scan in XC4000 Devices ........................................................ 8-25
XAPP 033.000
Implementing Logic in the Universal Interconnect Matrix ........................ 8-34
XAPP 041.001
Comparison of XC3000 Counter Designs ............................................... 8-36
XAPP 001.002
High-Speed Synchronous Prescaler Counter ......................................... 8-39
XAPP 002.002
Simple Loadable Up/Down Counter ........................................................ 8-42
XAPP 003.002
Synchronous Presettable Counter .......................................................... 8-44
XAPP 004.002
Loadable Binary Counters ....................................................................... 8-47
XAPP 014.001
Ultra-Fast Synchronous Counters ........................................................... 8-52
XAPP 023.001
Accelerating Loadable Counters in XC4000 ........................................... 8-56
XAPP 034.001
Complex Full-Featured Counters Run at 40 MHz ................................... 8-60
XAPP 038.001
High Performance Counters Using Xilinx EPLDs with ABEL-HDL.. ........ 8-62
XAPP 040.001
High-Speed Custom Length Binary Counters ......................................... 8-69
XAPP 022.000
Adders, Subtracters and Accumulators in XC3000 .............................•... 8-72
XAPP 013.001
USing the Dedicated Carry Logic in XC4000 ........................................... 8-79
XAPP 018.000
Estimating the Performance of XC4000 Adders and Counters ............... 8-90
XAPP 032.001
Calculating XC7200 Arithmetic Performance .......................................... 8-93
XAPP 039.001
18-Bit Pipeline Accumulator .................................................................... 8-95
XAPP 005.002
Register-Based FIFO .............................................................................. 8-96
XAPP 031.000
Using the XC4000 RAM Capability ......................................................... 8-101
XAPP 006.002
64 x n-Bit RAM-Based FIFO ................................................................... 8-113
XAPP 026.001
Multiplexers and Barrel Shifters in XC3000/XC321 00 ............................ 8-116
XAPP 027.001
Implementing State Machines in LCA Devices ....................................... 8-122
XAPP 028.001
Frequency/Phase Comparator for Phase-Locked Loops ........................ 8-127
XAPP 029.000
Serial Code Conversion between BCD and Binary ................................. 8-129
XAPP 030.000
Megabit FIFO in Two Chips: One LCA Device and One DRAM .............. 8-132
XAPP 007.001
Boundary-Scan Emulator for XC3000 ..................................................... 8-~ 36
XAPP 008.002
Complex Digital Generator ...................................................................... 8-143
XAPP 009.000
Harmonic Frequency Synthesizer and FSK Modulator ........................... 8-145
XAPP 010.001
Bus-Structured SeriallnputiOutput Device ............................................. 8-149
XAPP 012.001
Light-Driven Counter Controller .............................................................. 8-t51
XAPP 036.001
Four-Port DRAM Controller Operates at 60 MHz .................................... 8-154
XAPP 035.001
Digital Mixer in an XC7272 ...................................................................... 8-157
XAPP 037.000
Designing Complex 2-Dimensional Convolution Filters .......................... 8-158
Application Note Directory
XAPP 000.002
~
General
Page
8-6
Additional XC3000IXC3100 Data-XAPP 024.000
This Application Note contains additional information that may be of use when designing with the XC3000 class of LCA
devices. This information supplements the data sheets, and is provided for guidance only.
LCA Speed Estimation: Asking the Right Question-XAPP 011.001
8-16
A simple algorithm is described for determining the depth of logiC, in CLBs, that can be supported at a given clock frequency. The algorithm is suitable for XC3000IXC31 00 or XC4000 LCA devices.
Using the XC4000 Readback Capability-XAPP 015.000
8-17
This Application Note describes the XC4000 Readback capability and its use. Topics include: initialization of the Read·
back feature, format of the configuration and Readback bitstreams, timing considerations, software support for reading
back LCA devices, and Cyclic Redundancy Check (CRG).
Boundary Scan in XC4000 Devices-XAPP 017.002
8-25
XC4000 LCA devices contain boundary scan facilities that are compatible with IEEE Standard 1149.1. This Application
Note describes those facilities in detail, and explains how boundary scan is incorporated into an LCA design.
Implementing Logic in the Universal Interconnect Matrix-XAPP 033.000
8-34
This Application Note describes how to implement logic functions using the AND capability of the Universal Interconnect
Matrix.
Counters
Comparison of XC3000 Counter Designs-XAPP 0041.001
8-36
This Application Note discusses the functional, performance and density characteristics of the various counter designs
available for the XC3000. Differences in these characteristics must be taken into account when choosing the most
appropriate design.
High-Speed Synchronous Prescaler Counter-XAPP 001.002 ~
8-39
Borrowing the concept of Count· Enable Trickle/Count·Enable Parallel that was pioneered in the popular 74161 TIL·MSI
counter, a fast non·loadable synchronous binary counter of arbitrary length can be implemented efficiently in XC3000·
series LCA devices. For best partitioning into CLBs, the counter is segmented into a series of tri·bits. DeSign files are
available for 8,10,12,16,20 and 24·bit versions of this counter.
Length
Maximum Clock Frequency XC31 00·3
Number of CLBs
8
173
5
16 Bits
107 MHz
14
Simple Loadable Up/Down Counter-XAPP 002.002
8-42
The 5-input function generator of the XC3000 family CLB makes it possible to build fully synchronous, loadable up/down
counters of arbitrary length. These use only one CLB per bit, and the ripple carry delay is only 1/2 T 1LO per bit. Design
files are available for 8, 10, 12, 16,20 and 24·bit versions of this counter. A 16·bit higher performance version is also
available.
Length
Maximum Clock Frequency XC31 00·3
Number of CLBs
16 Bits
41 MHz
17
i!J This application directory is available on the Xilinx Technical Bulletin Board as XAPPOOO. DeSign liles 01 other application notes designated wah a disk symbol are
available under their own XAPP number.
8-1
I
Synchronous Presettable Counter-XAPP 003.002
8-44
Presettable synchronous counters are implemented, where the carry path utilizes parallel gating to replace the serial
gating found in ripple-carry counters. The result is fewer CLB delays in the critical path, but more CLBs are used and
the routing is less regular. Design files are available for 8, 10, 12, 16, 20 and 24-bit versions of this counter.
Length
Maximum Clock Frequency XC31 00-3
Number of CLBs
8
63
9
16 Bits
48 MHz
20
Loadable Binary Counters-XAPP 004.002
8-47
The design strategies for loadable and non-Ioadable binary counters are significantly different. This application note discusses the differences, and describes the design of a loadable binary counter. Up, down and. up/down counters are
described, with lengths of 16 and 32 bits. DeSign files are available for all six versions.
Length
Maximum Clock Frequency XC31 00-3
Number of CLBs
16 Bits
54 MHz
23
Ultra-Fast Synchronous Counters-XAPP 014.001
8-52
This fully synchronous, non-Ioadable, binary counter uses a traditional prescaler technique to achieve high performance. Typically, the speed of a synchronous prescaler counter is limited by the delay incurred distributing the parallel
Count Enable. This design minimizes that delay by replicating the LSB of the counter. In this way even the small Longline delay is eliminated, resulting in the fastest possible synchronous counter.
Counter Length
Maximum Clock
Frequency
Number of CLBs
XC4000
(-5)
16
111
17
XC31 00 XC3000
(-3)
(-125)
16
16
204
24
95
24
Bits
MHz
Accelerating Loadable Counters in XC400o-XAPP 0023.001
8-56
The XC4000 dedicated carry logic provides for very compact, high-performance counters. This Application Note
describes a technique for increasing the performance of these counters using minimum additional logic. Using this technique, the counters remain loadable.
Complex Full-Featured Counters Run at 40 MHz-XAPP 0034.001
8-60
This Application Note illustrates the implementation of long high-speed counters in Xilinx EPLDs. The Universal Interconnect Matrix eliminates the speed degradation usually associated with increasing counter length.
8-62
High Performance Counters USing Xilinx EPLDs with ABEL-HDL-XAPP 0038.001
Xilinx EPLDs are capable of implementing counters that operate at the maximum device frequency. This Application
Note explains how ABEL-HDL can be used to implement such counters.
High-Speed Custom Length Binary Counters-XAPP 040.001
8-69
This Application Note describes how to use Xilinx EPLDs for high-speed, binary counters that run at the full rated speed
of the device. These area-efficient, custom-length counters use standard 4- and 8-bit library components.
XAPP 000.002
8-2
Application Note Directory
Counter Performance Summary
12-Bij
8-Bil
10-Bil
16-Bil
20-Bil
24-Bil
32-Bil
Up!
Loadable Up Down Down MHz CLBs MHz CLBs MHz CLBs MHz CLBs MHz CLBs MHz CLBs MHz CLBs
XC31 00-3
XAPP 001
XAPP002
XAAP002
XAPP003
XAPP004
XAPP004
XAPP 014
XC3DOO-125
XAPP 001
XAPP002
XAPP 002
XAPP003
XAPP004
XAPP004
XAPP 014
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
XC4000-5
XAPP 014
•
•
•
•
•
•
•
•
•
•
•
•
173
47
5
8
63
9
116
38
8
10
108
37
9
12
52
15
•
•
•
81
26
5
8
33
9
60
21
8
10
•
•
• Estimated
56
21
9
12
29
15
107
29
41
48
54
46
204'
14
16
17
20
23
27
24
103
22
57
17
24
26
30
25
95'
14
16
17
20
23
27
24
55
13
111'
17
17
20
17
20
103
22
55
11
21
24
37
37
49
56
21
20
49
56
21
24
X3200
Arithmetic Functions
Adders, Subtracters and Accumulators in XC300o-XAPP 022_000
8-72
This Application Note surveys the different adder techniques that are available for XC3000 designs. Examples are
shown, and a speed/size comparison is made.
Using the Dedicated Carry Logic in XC400o-XAPP 013.001
8.-79
This Application Note describes the operation of the XC4000 dedicated carry logic, the standard configurations provided
for its use, and how these are combined into arithmetic functions and counters.
Estimating the Performance of XC4000 Adders and Counters-XAPP018.000
8-90
Using the XC4000 dedicated carry logic, the performance of adders and counters can easily be predicted. This Application Note provides formulae for estimating the performance of such adders and counters.
Calculating XC7200 Arithmetic Performance-XAPP 032.001
8-93
This Application Note describes how to estimate the performance of arithmetic circuits that are implemented using the
XC7200 dedicated carry citcuitry.
18-Bit Pipelined Accumulator-XAPP 039.001
8-95
This Application Note descibes a pipelining technique that significantly improves the throughput of an accumulator.
II
Special Purpose Memory
Register-based FIFO-XAPP 005.002 ~
8-96
While XC3000-series LCA devices do not provide RAM, it is possible to construct small register-based FIFOs. A basic
synchronous FIFO requires one CLB for each two bits of FIFO capacity, plus one CLB for each word in the FIFO.
Optional asynchronous input and output circuits are provided. Design files are available for two implementations of this
design. The fastest of the two implementations uses a constraints file to achieve better placement.
Size
Maximum Clock Frequency XC31 00-3
Number of CLBs
XAPP 000.002
8 x 8 Bits
42 MHz
40
8-3
Using the XC4000 RAM Capability-XAPP 031.000 ~
8-101
The XC4000 family of LCA devices permits CLB look-up tables to be configured as user RAM. This Application Note provides background information for users of the feature, and discusses a variety of applications.
64 x n-Bit RAM-based FIFO-XAPP 006.002 ~
8-113
For a 64 x 8-bit FIFO, 256 bits of RAM are implemented within an LCA device. An innovative address counter scheme,
using the high-performance dedicated carry logic, converts this into a simple FIFO. The address controller hard macro
available for this design may be used for 32 or 64-word FIFOs of any width.
FIFO size
Maximum Clock Rate (-5)
Maximum PUSH Rate
Maximum POP Rate
Number of CLBs
64 x 8 Bits
50 MHz
12.5 MHz
12.5 MHz
30
Miscellaneous Applications
Multiplexers and Barrel Shifters in XC3000IXC310o-XAPP 026.001
8-116
This Application Note provides guidance for implementing high performance multiplexers and barrel shifters in XC3000
LCA devices.
Implementing State Machines in LCA Pevices-XAPP 027.001
8-122
This Application Note discusses various approaches that are available for implementing state machines in LCA devices.
In particular, the one-hot-encoding scheme for medium-sized state machines is discussed.
Frequency/Phase Comparator for Phase-Locked Loops-XAPP 028.001
8-127
The phase comparator described in this Application Note permits phase-locked loops to be constructed using LCA
devices that only require an external voltage-controlled oscillator and integrating amplifier.
Serial Code Conversion between BCD and Binary-XAPP 029.000
8-129
Binary-to-BCD and BCD-to-binary conversions are performed between serial binary values and parallel BCD values.
8-132
Megabit FIFO in Two Chips: One LCA Device and One DRAM-XAPP 030.000
This Application Note describes the use of an LCA device as an address controller that permits a standard DRAM to be
used as deep FIFO.
Boundary Scan Emulator for XC300o-XAPP 007.001
8-136
CLBs are used to emulate IEEE1149.1/JTAG Boundary Scan. The LCA device is configured to test the board interconnect, and then reconfigured for operation.
Tests Supported
Number of CLBs
EXTEST
11 Core Logic
1/2 to 1-1/2 per lOB
1 per 3-State Control
Complex Digital Waveform Generator-XAPP 008.002
8-143
Complex digital waveforms are generated without the need for complex decoding. Instead, fast loadable counters are
used to time individual High and Low periods.
Minimum High/Low Time
Maximum High/Low Time
Resolution
Number of Highs and Lows
Number of CLBs
XAPP 000.002
44 ns
>250 Ils
4 ns
32
40
8-4
Harmonic Frequency Synthesizer and FSK Modulator-XAPP 009.000 ~
8-145
Harmonic Frequency Synthesizer
Uses an accumulator technique to generate frequencies that are evenly spaced harmonics of some minimum frequency.
Extensive pipelining is employed to permit high clock rates.
FSK Modulator
A modification of the Harmonic Frequency Synthesizer that automatically switches between two frequencies in
accordance with an NRZ input.
Harmonic Frequency Synthesizer
Maximum Output Frequency
Minimum Output Frequency
Frequency Spacing
Clock Frequency
Number of Bits
Number of CLBs
FSK Modulator
Operating Frequencies
Jitter
Clock Frequency
Number of CLBs
67 MHz
1 Hz
1 Hz
67 MHz
26
52
10/11 MHz
±8 ns
64 MHz
10
Bus-Structured SeriallnputiOutput Device-XAPP 010.001
8-149
Simple shift registers are used to illustrate how 3-state busses may be used within an LCA device. Dedicated wide
decoders are used to decode an I/O address range and enable the internal registers.
Bus Width
Maximum Bus Speed
Number of Serial Channels
Maximum Serial Speed
Number of CLBs
16 Bits
40 MHz
12
60 MHz
96
Light-Driven Counter Controller-XAPP 012.001
8-151
A simple state machine is used to adapt the output of two photo-cells to control an up/down counter. The state machine
provides hysteresis for counting parts correctly, regardless of changes in direction.
Maximum Clock Frequency
Number of CLBs
-150 MHz
2
Four-Port DRAM Controller Operates at 60 MHz-XAPP 036.001
This Application Note describes a high-performance DRAM controller implemented in a single Xilinx EPLD.
8-154
Digital Mixer in an XC7272-XAPP 035.001
This Application Note describes a simple mixer that operates at video rates, and provides 9 levels of mixing.
8-157
Designing Complex 2-Dimensional Convolution Filters-XAPP 037.000
8-158
This Application Note shows how to design complex 2-dimensional filters for digital image processing systems. The
XC7200IXC7300 dedicated carry logic is used to perform the complex arithmetic functions.
XAPP 000.002
8-5
II
Additional
XC3000IXC3100 Data
XAPP 024.000
Application Note By PETER ALFKE and BERNIE NEW
Summary
This Application Note contains additional information that may be of use when designing with the XC3000 class
of LeA devices. This information supplements the data sheets, and is provided for guidance only.
Xilinx Family
XC3000IXC3000NXC3000UXC31 00
look-up tables, extending the functionality to any two
functions of four variable chosen from seven, provided
two of the variables are stored in the flip-flops. This is
particularly useful in state-machine-like applications.
Introduction
The background information provided in this Application
Note supplements the XC3000, XC3000A, XC3000L
and XC3100 data sheets. It covers a wide range of topics, including a number of electrical parameters not
specified in the data sheets, and unless otherwise noted,
applies to all four families. These additional parameters
are sufficiently accurate for most design purposes;
unlike the parameters specified in the data sheets, however, they are not worst-case values over temperature
and voltage, and are not 100% production tested. They
can, therefore, not be guaranteed.
In the F mode, the function generators implement a single function of five variables that may be chosen from
seven, as described above. The selection of QX and QY
is constrained to be the same for both look-up tables.
The FGM mode differs from the F mode in that QX and
QY may be selected separately for the two look-up
tables, as in the FG mode. This added flexibility permits
the emulation of selected functions that can include all
seven possible inputs.
Configurable Logic Blocks
The automatic logic-partitioning software in the XACT
development system only uses the FG and F modes.
However, all three modes are available with manual partitioning, which may be performed in the schematic. If
FG or F modes are required, it is simply a matter of
including in the schematic CLBMAPs that define the
inputs and outputs of the CLB.
The XC3000IXC3100 CLB, shown in Figure 1, comprises a combinatorial function generator and two D-type
flip-flops. Two output pins may be driven by either the
function generators or the flip-flops. The flip-flop outputs
may be routed directly back to the function generator
inputs without going outside of the CLB.
The function generator consists of two 4-input look-up
tables that may be used separately or combined into a
single function. Figure 2 shows the three available
options. Since the CLB only has five inputs to the function generator, inputs must be shared between the two
look-up tables.
The FGM mode is only slightly more complicated. Again,
a CLBMAP must be used, with the signal that multiplexes between the two 4-input functions locked onto the
E pin. The CLB will be configured in the FGM mode if the
logic is drawn such that the gates forming the multiplexer are shown explicitly with no additional logic
merged into them.
In the FG mode, the function generator provides any two
4-input functions of A, Band C plus 0 or E; the choice
between 0 and E is made separately for each function.
In the F mode, all five inputs are combined into a single
5-input function of A, B, C, 0 and E. Any 5·input function
may be emulated. The FGM mode is a superset of the F
mode, where two 4-input functions of A, B, C and Dare
multiplexed together according to the fifth variable, E.
The two D-type flip-flops share a common clock, a common clock enable, and a common asynchronous reset
signal. An asynchronous preset can be achieved using
the asynchronous reset if data is stored in active-low
form; the Low created by reset corresponds to the bit
being asserted. The flip-flops cannot be used as latches.
If input data to a CLB flip-flop is derived directly from an
input pad, without an intervening flip-flop, the data-pad-
In all modes, either of the Band C inputs may be selectively replaced by QX and QY, the flip-flop outputs. In the
FG mode, this selection is made separately for the two
8-6
I:XILINX
Data In
01
5---"
F
~
0
r--
MUXfD
1
Dt-
~DIN
~G
L-
A
Logic
Variables
B
C
0
E
~ RD
T
OX
F
Combinatorial
Function
G
OY
-q
-DIN
G
Enable Clock
EC
1 (Enable)
Clock
Reset
III
K
~
RD
LJ
Direct
~
0
MUX
f-1
I1T
l)
~
' - - OX
L
F
~ X
I
~L
CLBOutputs
~J
y
t>
...!'g...
11
l)~
o(InhibH)
(Global Reset)
)(3217
Figure 1. Configurable' Logic Block (CLB)
to-clock-pad hold time will typically be non-zero. This hold
time is equal the delay from the clock pad to the CLB, but
may be reduced according to the 70% rule, described
later in the lOB Input section. of this Application Note.
Under this rule, the hold time is reduced by 70% of the
delay from the data pad to the CLB, excluding the CLB
set-up time. The minimum hold time is zero, even when
applying the 70% rule results in a negative number.
teredo The polarities of both the output data and the 3state control are determined by configuration bits. Each
output buffer may be configured to have either a fast or a
slow slew rate.
Table 1. Longline to CLB Direct AcCess
eLB
Longiine
The CLB pins to which Longlines have direct access are
shown in Table 1. Note that the clockenaple pin (EC) and
the TBUF control pin are both driven from to the same
vertical Long Line. Consequently, EC cannot easily .be
used to enable a register that must be 3-stated onto a
bus. Similarly, EC cannot easily be used in a register that
uses the Reset Direct pin (RD).
Right Most Vertical
(ACLK)
Input/Output Blocks
Upper Horizontal
The XC3000IXC3100 lOB, shown in Figure 3, includes a
3-state output driver that. may be driven directly or regis-
XAPP 024.000
8-7
TBUF
A B C D E K EC RD
Left Most Vertical
(GCLK)
T
X
"
Left Middle Vertical
X
Right Middle Vertical
Lower Horizontal
X
X
X
X
X
X
X
X
X
I
Additional XC3000IXC3100 Data
A
B
OX
C
IQY~
E
Q
' IQY~
C
D
...
Any Function
of Up To 4
Variables
f--G
...
I}
...
E
B
Experiments show that the input rise and fall times should
not exceed 250 ns. This value was established through a
worst-case test using internal ring oscillators to drive all
I/O pins except two, thus generating a maximum of onchip noise. One of the remaining I/O pins was configured
as an input, and tested for single-edge response; the
other I/O was used as an output to monitor the response.
~
i
A
r--F
VI}-
D
A
B
Any Function
of UpT04
Variables
Inputs
All inputs have limited hysteresis, typically in excess of
200 mV for TTL input thresholds and in excess of 100 mV
for CMOS thresholds. Exceptions to this are the
PWRDWN pin, and the XTL2 pin when it is configured as
the crystal oscillator input.
Q, IQY~
C
2a
Any Function
of 5 Variables
~
D
E
f:
2b
A
B
Q'~
OY
...
C
These test conditions are, perhaps, overly demanding,
although it was assumed that the PC board had negligible
ground noise and good power-supply decoupling. While
conservative, the resulting specification is, in most
instances, easily satisfied.
FG
Mode
lOB input flip-flops are guaranteed to operate correctly
without data hold times (with respect to the device clockinput pad) provided that the dedicated CMOS clock input
pad and the GCLK buffer are used. The use of a TTL
clock or a different clock pad will result in a data-hold-time
requirement. The length of this hold time is equal to the
delay from the actual clock pad to the GCLK buffer minus
the delay from the dedicated CMOS clock pad to the
GCLK buffer.
F
Mode
Any Function
of Up To 4
Variables
D
To ensure that the input flip-flop has a zero hold time,
delay is incorporated in the D input of the flip-flop, causing
it to have a relatively long set-up time. However, the setup time specified in the data sheet is with respect to the
clock reaching the lOB. Since there is an unavoidable
delay between the clock pad and the lOB, the input-padto-Clock-pad set-up time is actually less than the data
sheet number.
F
M
U
A
B
OX
C
loy~
G
Any Function
of Up T04
Variables
Part of the clock delay can be subtracted from the internal
set-up time. Ideally, all of the clock delay could be subtracted, but it is possible for the clock delay to be less
than its maximum while the internal set-up time is at its
maximum value. Consequently, it is recommended that, in
a worst-case design, only 70% of the clock delay is subtracted.
~
D
E
2c
FGM
Mode
X3218
Figure 2. CLB Logic Options
The lOB input may also be direct or registered. Additionally, the input flip-flop may be configured as a latch. When
an lOB is used exclusively as an input, an optional pull-up
resistor is available, the value of which is 40-150 kil. This
resistor cannot be used when the lOB is configured as an
output or as a bidirectional pin.
Unused lOBs should be left unconfigured. They default to
inputs pulled High with the internal resistor.
XAPP 024.000
8-8
The clock. delay can only be less than 70% of its maximum if the internal set-up time requirement is also less
than its maximum. In this case, the pad-to-pad set-up time
actually required will be less than that calculated.
For example, in the XC3000-125, the input set-up time
with respect to the clock reaching the lOB is 16 ns. If the
delay from the clock pad to the lOB is 6 ns, then 70% of
this delay, 4.2 ns, can be subtracted to arrive at a maximum pad-to-pad set-up time of -12 ns.
I:XILINX
program-Control~d MemOlY Cells
,
Out
Invert
3-State
(OUTPUT ENABLE)
Out
~f}
T
0
Output
Select
3-Stete
Invert
'1
-
~f}
Q-
D
l)
Slew
Rale
Registered In
Passive
Pull Up
'\.....
i!>.
----l
Output
Buffer
FlipFlop
Direct In
Vee
,
~
~
+
I
-Q
Q
r-OK
IK
I/OPed
1
D
FlipFlop
or
Latch
TTL or
CMOS
Input
Threshold
>
~
,,-
+
(Global Reset)
(
l..
~CKI
(
l..
Program
Controlled
o
= Programmable Interconnection Paint or PIP
}-CK2
)(3216
Figure 3_ Input/Output Block (lOB)
The 70% rule must be applied whenever one delay is
subtracted from another. However, it is recommended
that delay compensation only be used routinely in connection with input hold times. Delay compensation in
asynchronous circuits is specifically not recommended. In
any case, the compensated delay must not become negative. If 70% of the compensating delay is greater than
the delay from which it is deducted, the resulting delay is
zero.
The 70% rule in no way defines the absolute minimum
values delays that might be encountered from chip to
chip, and with temperature and power-supply variations.
It simply indicates the relative variations that might. be
found within a specific chip over the range of operating
conditions.
XAPP 024.000
8-9
Typically, all delays will be less than their maximum, with
some delays being disproportionately faster than others.
The 70% rule describes the spread in the scaling factors;
the delay that decreases the most will be· no less than
70% of what it would have been if it had scaled in proportion to the delay that decreased the least. In particular, in
a worst-case design where it is assumed that any delay
might not have scaled at all, and remains at its maximum
value,other delays will be no less than 70% of their maximum.
Outputs
All XC3000/xC3100 LCA outputs are true CMOS with nchannel transistors pulling down and p-channel transistors pulling up. Unloaded, these outputs pull rail-to-rail.
II
Additional XC3000IXC3100 Data
XC3020
XC3142
100 ........ ·.... ,··, ...... "·, ........ ·"· ...... ,.... ,,, .... ·.. ····, ...... · .. ·.. ,, ............ ,..............,...........~.......... ,
100
rnA
90
90
SO
80
70
70
60
rnA
50
60
50
~~~~~-~+~~--~'--'0~'~+~-
~
30
30
20
'
20
101'"f'~0"-~+--0-'--~"~~·""",+,---·
0L-~--~~--~2~~--~3--~--~~~
Volts
Volts
X3225
Figure 4. Current-Voltage Curves
Some additional ac and dc characteristics of the output
are listed in Tables 2 and 3. Figure 4 shows output current/voltage curves for typical XC3000 and XC3100
devices.
Output-short-circuit-current values are given only to indicate the capability to charge and discharge capacitive
loads. In accordance with common industry practice for
other logic devices, only one output at a time may be
short circuited, and the duration of this short circuit to Vee
or ground may not exceed one second. Xilinx does not
recommend a continuous output or clamp current in
excess of 20 mA on anyone output pin. The data sheet
guarantees the outputs for no more than 4 mA at 320 mV
to avoid problems when many outputs are sinking current
simultaneously.
The active-High 3-state control (T) is the same as an
active-Low output enable (OE). In other words, a High on
the T-pin of an OBUFZ places the output in a high impedance state, and a Low enables the output. The same convention is used for TBUFs within the LCA device.
I/O Clocks
Internally, up to eight distinct I/O clocks can be used, two
on each of the four edges of the die. While the lOB does
not provide programmable clock polarity, the two clock
lines serving an lOB can be used for true and inverted
clock, and the appropriate polarity connected to the lOB.
This does, however, limit all lOBs on that edge of the die
to using only the two edges of the one clock.
There is good agreement between output impedance and
loaded output rise and fall time, since the rise and fall time
is slightly longer than two time constants.
lOB latches have active-Low Latch Enables; they are
transparent when the clock input is Low and are closed
when it is High. The latch captures data on what would
otherwise be the active clock edge, and is transparent in
the half clock period before the active clock edge.
Table 2. Additional AC Output Characteristics
Table 3. Additional DC Output Characteristics
AC Parameters
Fast'
Slow'
Unloaded Output Slew Rate
2.8 V/ns
0.5 V/ns
Sinking. near ground
Unloaded Transition lime
1.45 ns
7.9 ns
Sourcing. near Vcc
Additional rise time for 812 pF
100 ns
100 ns
Output Impedance
Output Short Circuit Current
25n
50n
normalized
0.12 ns/pF
0.12 ns/pF
Sinking current by the LCA device
110 mA
Additional fall time for 812 pF
50 ns
64 ns
Sourcing current by the LCA device
80mA
normalized
0.06 nslpF
0.08 ns/pF
, Fast and Slow refer to the output programming option.
XAPP 024.000
8-10
Table 4. Number of Horizontal Longlines
Part Name
Rows x
Columns
CLBs
HLL
To specify the use of TClKIN or BClKIN in a schematic,
connect an IPAD symbol directly to the GClK or AClK
symbol. Placing an IBUF between the IPAD and the clock
buffer will prevent TClKIN or BClKIN from being used.
TBUFs
per HLL
3020
8x8
64
16
9
3030
10 x 10
100
20
11
3042
12 x 12
144
24
13
3064
16 x 14
224
32
15
3090
20x 16
320
40
17
The clock buffer output nets only drive ClB and lOB clock
pins. They do not drive any other CLS inputs. In rare
cases where a clock needs to be connected to a logic
input or a device output, a signal should be tapped off the
clock buffer input, and routed to the logic input. This is not
possible with clocks using TClKIN or BClKIN.
Routing
Horizontal Longlines
As shown in Table 4, there are two horizontal longlines
(Hlls) per row of ClBs. Each Hll is driven by one TBUF
for each column of ClBs, plus an additional TBUF at the
left end of the longline. This additional TBUF is convenient for driving lOB data onto the longline. In general,
the routing resources to the T and I pins of TBUFs are
somewhat limited.
Optionally, Hlls can be pulled up at either end, or at both
ends. The value of each pull-up resistor is 3-10 kQ.
The clock skew created by routing clocks through local
interconnect makes safe designs very difficult to achieve,
and this practice is not recommended. In general, the
fewer clocks that are used, the safer the design. High fanout clocks should always use GClK or AClK. If more
than two clocks are required, the AClK net can be segmented into individual vertical lines that can be driven by
PIPs at the top and bottom of each column. Clock signals
routed through local interconnect should only be considered for individual flip-flops.
General Information
Recovery from Reset
Recovery from Reset is not specified in Xilinx data sheets
because it is very difficult to measure in a production environment. The following values may be assumed for all
XC3000/xC3100 devices and speed grades.
In addition, Hlls are permanently driven by low-powered
latches that are easily overridden by active outputs or
pull-up resistors. These latches maintain well-defined
logic levels on Hlls that are not pulled up and temporarily
are not driven. The logic level maintained is the last level
actively driven onto the line, and in some designs these
latches may be exploited memory devices.
• The ClB can be clocked immediately «0.2 ns) after
the end of the internal Reset Direct signal (RD).
When using 3-state Hlls for multiplexing, the use of
fewer than four TBUFs can waste resources. Multiplexers
with four or fewer inputs can be implemented more efficiently using ClBs.
• The ClB can be clocked no earlier than 25 ns (worst
case) after the release of an externally applied Global
Reset signal, i.e., after the rising edge of the active-low
signal.
Vertical Longlines
There are four vertical longlines per routing channel: two
general purpose, one for the global clock net and one for
the alternate clock net.
Configuration and Start-up
Until the chip goes active after configuration, all I/O pins
not involved in the configuration process remain in a highimpedance state with weak pull-up resistors; all internal
flip-flops and latches are held reset. Multiple lCA devices
hooked up in a daisy chain will all go active simultaneously on the same CClK edge. This is well documented in the data sheets.
Clock Buffers
XC3000/xC3100 devices each contain two high-fan-out,
low-skew clock-distribution networks. The global-clock net
originates from the GClK buffer in the upper left corner of
the die, while the alternate clock net originates from the
AClK buffer in the lower right corner of the die.
The global and alternate clock networks each have
optional fast CMOS inputs, called TClKIN and BClKIN,
respectively. Using these inputs provides the fastest path
from the PC board to the internal flip-flops and latches.
Since the Signal bypasses the input buffer, well-defined
CMOS levels must be guaranteed on these clock pins.
XAPP 024.000
8-11
Not documented, however, is how the internal combinatorial logic comes alive during configuration: As configuration data is shifted in and reaches its destination, it
activates the logic and also "looks at" the lOB inputs.
Even the crystal oscillator starts operating as soon as it
receives its configuration data. Since all flip-flops and
latches are being held reset, and all outputs are being
held in their high-impedance state, there is no danger in
this "staggered awakening" of the internal logic. The operation of the logic prior to the end of configuration is even
II
Additional XC3000/xC3100 Data
~ =u 1
V
r---
0
Q
Vc c
1
OE = High
T=Low
).
System Clock
-V
CLB
---r--
MR
L!W
lOB
------=
RES ET
High-
-----f':
10:-
1
L
X3222
Figure 5. Synchronous Reset
useful; it ensures that clock enables and output enables
are correctly defined before the elements they control
become active.
Once configuration is complete, the LCA device is activated. This occurs on a rising edge of CCLK, when all outputs and clocks that are enabled become active
~i~ultaneously. Since the activation is triggered by CCLK,
It IS an asynchronous event with respect to the system
clock. To avoid start-up problems caused by this asynchronism, some designs might require a reset pulse that
is synchronized to the system clock.
The circuit shown in Figure 5 generates a short Global
Reset pulse in response to the first system clock after the
end of configuration. It uses one CLB and one lOB and
also precludes the use of the LOC pin as 1/0.
'
During Configuration, LOC is asserted Low and holds the
of the flip-flop High, while Q is held Low by the
Internal reset, and RESET is kept High by internal and
external pull-up resistors. At the end of configuration, the
LOC pin is unasserted but 0 remains High since the function generator acts as an R-S latch; Q stays Low, and
RESET is still pulled High by the external resistor. On the
first system clock after configuration ends, the Q is
cl~cked ~igh, resetting the latch and enabling the output
driver which forces RESET Low. This resets the whole
chi~ until the Low on Q permits RESET to be pulled High
again.
~-input
The whole chip has thus been reset by a short pulse instigated by the system clock. No further pulses are generated, since the High on LOC prevents the R-S latch from
becoming set.
XAPP 024.000
8-12
Power Dissipation
As in most CMOS ICs, almost all LCA power dissipation is
dynamic, and is caused by the charging and discharging
of internal capacitances. Each node in the device dissipates power according to the capacitance in the node,
wh~ch is fixed .for each type of node, and the frequency at
which the particular node is switching, which can be different from the clock frequency. The total dynamic power is
the sum of the power dissipated in the individual nodes.
While the clock line frequency is easy to specify, it is
usually more difficult to estimate the average frequency of
other nodes. Two extreme cases are binary counters,
where half the total power is dissipated in the first flip-flop,
and shift registers with alternating zeros and ones, where
the whole circuit is exercised at the clocking speed.
Consequently, most power consumption estimates only
serve as guidelines because they must be based on gross
approximations. Table 5 shows the dynamic power dissipation, in mW per MHz, for different types of XC3000
nodes. While not precise, these numbers are sufficiently
accurate for the calculations in which they are used, and
may be used for any XC3000IXC3100 device. Table 6
shows a sample power calculation.
Table 5. Dynamic Power DiSSipation
XC3020 XC3090
One CLB driving three local
interconnects
0.25
0.25
mW/MHz
One device output with a
50 pF load
1.25
1.25
mW/MHz
One Global Clock Buffer and
line
2.0
3.5
mW/MHz
One Longline without driver
0.1
0.15
mW/MHz
I:XIUNX
Table 6. Sample Power Calculation
XTAL..OUT
Device: 3020
Quantity
MHz
mWIMHz
1
Clock Buffer
Node
40
2.0
80
5
ClBs
40
0.25
50
10
ClBs
20
0.25
50
40
ClBs
10
0.25
100
longlines
20
0.1
Outputs
20
1.25
8
20
mW
Rl
R2
~--~Dr---~--~~
Yl
16
----I
500
Table 7. CClK Frequency Variation
Vee
Temp
Frequency
4.5 V
25°C
687 kHz
5.0 V
25°C
691 kHz
5.5 V
25°C
695 kHz
4.5 V
·3Q°C
966. kHz
4.5 V
+130°C
457 kHz
C2.
r----'
~
L
3RD
Overtone
Only
X3220
Figure 6. Crystal Oscillator
the components surrounding the crystal. Series-resonant
crystals are specified by their manufacturers according to
the lower edge of the frequency band, parallel-resonant
crystals according to the upper edge.
CCLK Frequency Variation
Configuration Clock (CCLK) is the intemally generated
free-running clock that shifts configuration data into and
out of the device. The CCLK frequency is fairly insensitive
to changes Vee, varying only 0.6% for a 10%,change in
Vee. It is, however, very temperature dependent, increasing 40%. as the temperature drops from 25°C to -30°C,
Table 7.
Crystal Oscillator
XC3000 and XC3100 devices contain an on-chip crystal
oscillator circuit that connects to the ACLK buffer. This circuit, Figure 6, comprises a high-speed, high-gain inverting
amplifier with its input connected to the dedicated XTL2
pin, and its output connected to the XTL1 pin. An extemal
biasing resistor, R1, with a value of 0.5 to 1 Mil is
required.
A crystal, Y1, and additional phase-shifting components,
R2, C1 and C2, complete the circuit. The capaCitors, C1
and C2, in parallel form the load on the crystal. This load
is specified by the crystal manufacturer, and is typically 40
pF:The capacitors should be approximately equal:
20
pF each for a 40 pF crystal.
Either series- or parallel-resonant crystals may be used,
since they differ only in their specification. Crystals constrain oscillation to a narrow band of frequencies, the
width of which is «1% of the OSCillating frequency; the
exact frequency of oscillation within this band depends on
XAPP 024.000
T ,~
r
Total Power -800 mW
8-13
The resistor, R2, controls the loop gain and its value must
be established by experimentation. If it is too small, the
oscillation will be distorted; if it is too large, the oscillation
will fail to start, or only start slowly. In most cases, the
value. of R2 is non-critical, and typically is 0 to 1 kn.
Once the component values have been chosen, it is good
practice to test the oscillator with a resistor (-1. kn) .in
series with the crystal. If the oscillator still starts reliably,
independent of whether the power supply tums on quickly
or slowly, it will always work without the resistor.
For operation above 20 to 25 MHz, the crystal must be
operated at its third harmonic. The capacitor C2 is
replaced by a parallel-resonant LC tank circuit tuned to
-213 of the desired frequency, i.e., twice the fundamental
frequency of the crystal. Table 8 shows typical component
values for the tank circuit.
Table 8; Third Harmonic Crystal Oscillator Tank-Circuit
Component
Frequency
(MHz)
lCTank
l (ILH)
C(pF)
Freq (MHz)
R2(n) C1 (pF)
32
60
20.6
430
23
35
44
24.0
310
23
49
31
28.6
190
23
72
18
37.5
150
12
II
Additional XC3000lXC3100 Data
Metastable Recovery
Whenever a clocked flip-flop synchronizes an asynchronous input, there is a small probability that the flip-flop
output will exhibit an unpredictable delay. This happens
when the input transition not only violates the setup and
hold-time specifications, but actually occurs within the tiny
timing window where the flip-flop accepts the new input.
Under these circumstances, the flip-flop can enter a symmetrically balanced transitory state, called metastable
(meta =between).
4.2 ns, once per hour
6.6 ns, once per year
8.4 ns, once per 1000 years
The frequency of occurrence of these metastable delays
is proportional to the product of the asynchronous event
frequency and the clock frequency. If, for example, a 100kHz event is synchronized by a 2-MHz clock, the above
delays (besides being far more tolerable) will occur 50
times less often.
While the slightest deviation from perfect balance will
cause the output to revert to one of its two stable states,
the delay in doing so depends not only on the gain bandwidth product of the circuit, but also on how perfect the
balance is and the noise level within the circuit; the delay
can, therefore, only be described in statistical terms.
The problem for the system designer is not the illegal
logic level in the balanced state (it's easy enough to translate that to either a 0 or a 1), but the unpredictable timing
of the final change to a valid logic state. If the metastable
flip-flop drives two destinations with differing path delays,
one destination might reflect the final data state while the
other does not.
With the help of a mostly self-contained circuit on the
demonstration board that is available to all Xilinx customers, Xilinx evaluated the XC3020-70 CLB flip-flop. The
result of this evaluation shows the Xilinx CLB flip-flop to
be superior in metastable performance to many popular
MSI and PLD devices.
Statistically, when an asynchronous event with a frequencyof approximately 1 MHz is being synchronized by
a 10-MHz clock, the CLB flip-flop suffers an additional
delay, as follows.
The evaluation depended on knowledge that the mean
time between metastable events lasting longer than a
specified duration increases exponentially with that duration. Consequently, the mean time between failure
(MTBF) with a given tolerance for metastability delay can
be determined by estimating the exponential ratio and a
single point on the curve.
Since metastability can only be measured statistically, this
data was obtained by configuring an XC3020 with eight
concurrent detectors. Eight D-type flip-flops were clocked
from a common high-speed source, and their D inputs
driven from a common, lower frequency asynchronous
signal, Figure 7. The output of each flip-flop fed the D
inputs of two more flip-flops, one clocked half a clock
period later and the second a full clock period later.
If a metastable event in the first flip-flop increased the output settling time to more than one-half clock period, the
second two flip-flops would capture differing data. Thus,
the occurrence of a long metastable delay could be
detected using a simple comparator. Deliberate skew in
the input data to the eight metastable circuits ensured that
at most one metastable event could occur each clock.
This permitted the eight detectors to be ORed into a single metastable event counter.
o
,,
,
Q0
//////I,
'./
o
0
Qo
Q1
Clock
Q2
,,,
Cl9ck
I
-
Count Pulse HMetastable
,,
Non·Metastable
M!!I!l ~
1/
1/
Y
,,,
,
,
\..
Delay DetectIon
.
Repeated Eight Times
X3226
Figure 7. Metastable Measuring Circuit
XAPP 024.000
'.L,
,
• ,,
,,,
8-14
~XIUNX
Battery Back-up
MTBF
Since Logic Cell Arrays are manufactured using a highperformance low-power CMOS process, they can preserve
the configuration data stored in the intemal static memory
cells even during a loss of primary power. This is accomplished by forcing the device into a low-power non-operational state, while supplying the minimal current requirement of Vee from a battery.
S
1011
1010
1000 Years
lcP
lOB
107
1 Year
1 Month
106
105
104
Circuit techniques used in XC3100 devices prevent Icc
from being reduced to the level need for battery back-up.
Consequently, battery back-up should only be used for
XC3000 devices.
1 Day
1 Hour
103
fOATA= 1 MHz
102
There are two primary considerations for battery backup
which must be accomplished by external circuits.
fCLOCK= 10 MHz
101
2
4
6
8
• Control of the Power-Down (PWRDWN) pin
ns
• Switching between the primary Vee supply and the
battery.
X3219
Figure 8. Metastable MTBF as a Function of
Additional Acceptable Delay
Important considerations include the following.
As expected, no metastable events were observed at clock
rates below 25 MHz, since a half clock period of 20 ns is
adequate for almost any metastability-resolution delay plus
the flip-flop set-up time. Increasing the clOCk rate to around
27 MHz brought a sudden burst of metastable events.
Careful adjustment of the clock frequency gave repeatable, reliable measurements showing that a 500 ps
decrease in the half clock period increased the frequency
of metastable occurrences by a factor of 41.
To be conservative, to compensate for favorable conditions
at room temperature and to avoid any possibility of overstating a good case, the measurements were interpreted
as follows.
When capturing asynchronous data, the error rate decreases by a factor of 40 for every additional nanosecond of
metastabi/ity-resoluUon delay that the system can tolerate.
This factor of 40 is the exponential ratio of the MTBF curve,
and it is now necessary to determine one point on the
curve. Assuming that the flip-flop metastability window is
0.1 ns wide and the clock period is 100 ns (10 MHz), one
data change in 1000 will fall into the metastability window;
a data change every 1 I.lS (1 MHz) will result in a mean time
between metastable events of 1 ms. H the system has no
tolerance for additional delay caused by metastability,
every metastable event will cause a failure, and the MTBF
will also be 1 ms.
• Insure that PWRDWN is asserted logic Low prior to Vee
falling, is held Low while the primary Vee is absent, and
retumed High after Vee has returned to a normal level.
PWRDWN edges must not rise or fall slowly.
• Insure "glitch-free" switching of the power connections
to the LCA device from the primary Vee to the ~ttery
and back.
• Insure that, during normal operation, the LCA Vcc is
maintained at an acceptable level, 5.0 V ± 5% (±10%
.
for Industrial and Military).
Figure 9 shows a power-down circuit developed by Shel
Epstein of Epstein Associates, Wilmette, IL. Two Schottky
diodes power the LCAfrom either the 5.2 V primary supply
or a 3 V Lithium battery. A Seiko S8054 3-terminal power
monitor circuit monitors Vee and pulls PWRDWN Low
whenever Vee falls below 4 V.
VCC
IN5817
Seiko S8054 Specifications
Detect Voltage 3.995 V min
4.305Vrnax
Hysteresis
208 mV typ
Temp. Coeff. 0.52 mVI"C
Icc@+6V
2.6flAtyp
B35
LHhium
Battery
Combining this data point with the measured exponential
ratio results in the MTBF curve shown in Figure 8. As stated
previously, for other clock and data frequencies, the MTBF
scales in proportion to the product of those frequencies.
An exact measurement of the metastable window width is
unnecessary. Even if the estimated width is low by an
order of magnitude, the additional delay tolerance needed
to achieve any given MTBF is less than 1 ns.
XAPP 024.000
8-15
IN5817
X3221
Figure 9. Counter Speed and Density
II
LeA Speed Estimation:
Asking the Right Question
XAPP 011.001
Application Note
By BERNIE NEW
Summary
A simple algorithm is described for determining the depth of logic, in CLBs, that can be supported at a given
clock frequency. The algorithm is suitable for XC3000IXC31 00 or XC4000 LCA devices.
Speed is always a consideration when deciding whether
a design can be implemented in an LCA devices. Often,
an initial logic design is created and the question asked,
"How fast will this run in an LCA device?"
This is not an easy question to answer. A good speed
estimate requires careful analysis of the logic design;
performance will vary with the logic implementation. To
complicate matters, routing delays are always unknown
at this stage.
When the estimate is complete, it is usually compared to
a given system requirement simply to determine adequacy, and the exact number becomes irrelevant. If a
system requires 30 MHz, for example, being able to
operate at 35, 40 or even 50 MHz makes no difference.
A better question is "Will an LCA implementation meet
the system speed requirements?"
This can often be answered much more easily. Given a
required clock rate, it is easy to estimate the level of
complexity that can be supported. This complexity can
then be compared to the functional requirements to
make an initial determination of feasibility. Only in marginal cases does a full speed estimate become necessary.
A typical data path runs from a register, through some
combinatorial logic to another register. In an LCA device,
this requires, as a minimum, a CLB clock-to-output delay
plus a set-up time. In an XC3000-125 part, these total
10.5 ns. Including routing, 15 ns should be typically
allowed. If combinatorial CLBs are added into the path,
each level of CLBs adds 5.5 ns. Additional routing
delays are also created. Including a typical routing allowance, 10 ns should be added for each level of combinatorial CLBs.
This simple speed-estimating procedure can also be
reversed. If, for example, the system clock frequency is
30 MHz, the 33 ns period typically provides for two combinatorial CLBs.
Clock period
Minimum delay
Combinatorial delay
33 ns
-15 ns
18 ns
+10 ns
-2 CLBs
Including the function generator in the destination CLB,
a total of three function generators can be cascaded. If
the number of function generators that can be cascaded
is known, the design can be analyzed to determine
whether or not it is feasible.
This should not be considered a hard limit. Shorter routing delays can be achieved, allowing deeper logic. However, dependence on short routing delays will probably
necessitate optimization of both the logic design and the
routing.
Nor is the number of function generators guaranteed.
Longer routing delays may be encountered, especially if
a chip is fully utilized or if high fan-out signals are used.
Elimination of these long routing delays may necessitate
manual routing or logic design changes. In any case, the
timing of all LCA designs should be analysed after routing to determine worst-case performance.
Table 1 shows typical minimum delays for various LCA
devices. Also shown are typical increments for combinatorial CLBs. To allow for higher routing delays, these figures should be increased by 5 ns, if more that 60 - 75%
of the CLBs are to be used. If a large LCA device is to be
used and the CLBs are placed automatically, a separate
3 - 5 ns should be added to each delay.
This technique not only simplifies the feasibility study,
it also provides valuable information on which to base
the logic design. Critical areas can be identified prior to
starting the design. It is better to design around the
critical areas than to have to accommodate them during implementation. Conversely, if a design only requires
a fraction of the capability available, it might be possible
to multiplex some functions to provide a less costly
implementation.
Table 1.
Delays,lncluding Typical Routing
XC3000
XC31 00
XC4000
-70 -100 -125 -5
-4
-3
-6
-5
Minimum delay
21
18
15
10
9
7
17
12
ns
Combinational delay
15
12
10
8
7
6
12
9
ns
To each delay add:
8-16
5 ns for high utilization
3 - 5 ns for large LeA Devices
Using the XC4000
Readback Capability
XAPP 015.000
Application Note
By WOLFGANG HOFLICH
Summary
This Application Note describes the XC4000 Readback capability and its use. Topics include: initialization of the
Readback feature, format of the configuration and Readback bitstreams, timing considerations, software support for reading back LCA devices, and Cyclic Redundancy Check (CRC).
Xi/inx Family
Demonstrates
XC4000
XC4000 Readback Capability
Purpose
Readback Highlights
Every LCA device shipped by Xilinx is tested using the
device Readback capability. All CLBs and lOBs are configured and read back using extensive test patterns to
guarantee 100% functionality of the LCA device.
The Readback features and the user interface of the
XC4000 devices are significantly improved over the
XC2000IXC3000 devices.
The Readback operation does not interfere with the LCA
operation. After a valid Readback request, the current
state of LCA internal nodes can be captured into a special shift register. Then the data can be transferred out of
the device using a user-defined clock signal.
An LCA device can be read back at any time after configuration.The Readback data consists of the configuration data and, optionally, the current state of the CLBs
and lOBs.
The following LCA internal configuration data and circuit
nodes are available for Readback (Figure 1).
When is a Readback Necessary or Useful?
The XILINX devices are 100% pretested and the
XC4000 series LCA devices can use Cyclic Redundancy
Checking (CRC) on the configuration bitstream to check
the integrity of the bitstream loaded into the LCA configuration memory.
• Configuration memory bits that define the logic configration of CLBs, lOBs, and the LCA interconnects.
• X and Y output pins of CLB Function Generators.
• XO and YO output pins of CLB flip-flops,
In the configuration bitstream, there are four error-check
bits for each data frame transmitted into the LCA device.
Using this technique, the LCA device detects invalid
data bits and aborts the configuration process. The INIT
status pin is pulled Low, signaling that an error occurred
during loading of the configuration memory.
• 00 output pins of lOB flip-flops,
•
A mask file «design_name>.LL), generated with the
MakeBits program, contains information about the location of the user data bits in the Readback bitstream and
the names of the signals connected.
Therefore, Readback is useful only in few cases.
• Verifying the
environment,
configuration
in
a very
11 and 12 input pins of lOBs
The user can implement comparison logic in CLBs to
perform the comparison with data stored in the configuration PROM. This technique does not work if any CLB
is used as RAM, since changing the RAM contents
alters the data in the configuration memory. In this case,
an additional mask PROM is needed to disable the comparison of Readback bitstream locations that represent
the RAM data.
unstable
• Reading back the internal state of the RAM, CLBs and
lOBs during the LCA development phase,
• In high-reliability applications that require in-system
functional analysis and verification,
• For Xilinx internal testing
The Readback speed is 10kHz min, 1 MHz max. See
the timing diagrams at the end of this application note.
For examples of how to use Readback in your application, contact Xilinx.
The XC4000 family features a Boundary-Scan instruction that initiates a Readback sequence using the standard IEEE 1149.I/JTAG Boundary-Scan ports.
8-17
II
Using theXC4000 Readback Capability
lOB
OE+-+---;
alIT
-+-----1
11+-''--1
12+...1:--1
INPlIT
CLOCK
,READOUT POINTS
CLB
C1
C2
C3
C4
G4
G3
LOGIC
FUNgl'ON G'
D
SD
o
'XO
G1·G4
G2
G1
LOGIC
FUNCTION
OF
H'
F',G',
AND
H1
EC
AD
'x
F4
F3
LOGIC
FUNCTlON
OF
F1·F4
F2
D
P
SD
o
'YO
F1
EC
AD
K
(CLOCK)
,
'y
READOlIT POINTS
X1519A
Figure 1. Readback Capture Enable
XAPP 015.000
8-18
Daisy chaining LCA devices for Readback is not possible.
Each device must be read back individually.
The XChecker Universal Download Cable and Logic
Probe handles configuration and Readback of XC2000,
XC3000, and XC4000 FPGA families. In addition, it displays selected LCA internal nodes on screen.
NO
Performing a Readback
Readback State Diagram
An LCA-internal state machine controls the Readback
process. See Figure 2 for the Readback state diagram.
For an explanation of the terms used, see below.
Readback Primitive
The XC4000 LCA device has a dedicated primitive that
handles all of the Readback functions. It is located in the
lower left and right corners of the LCA device and has two
inputs and two outputs (Figure 3).
The Readback primitive can access general-purpose
interconnects. Therefore, the four signals - rdclk.l,
rdbk.TRIG, rdbk.RIP, and rdbk.DATA - can connect to the
user II0s and to CLBs as follows.
• rdclk.1 - The Clock input can be connected to any
device input pin, or any CLB output. If it is not connected
to a user net, it connects to the device CCLK input pin, if
the appropriate option is selected in the bitstream-generator MakeBits program.
• rdbk.TRIG - A Low-to-High transition on the TRIG
input starts a Readback sequence. The minimum required
pulse width is one rdclk.l cycle. A valid trigger causes the
current value of certain nodes to be latched into an LCA
internal holding register. If ReadAbort was selected as an
option in MakeBits, a High-to-Low on the TRIG input
aborts the Readback. In this case, additional clocks must
be provided until rdbk.RIP signals the end of a Readback.
The rdbk.TRIG cannot be reasserted until at least three
clock periods after the previous Readback has been terminated correctly.
• rdbk.RIP (Readback-In-Progress) - A High on this output indicates that a Readback is being performed. RIP
goes active one Readback clock cycle after a valid Readback trigger has occurred. It goes Low with the last data
rdclk.1
=B
rdbk.DATA
READBACK
rdbk.TRIG
rdbk.RIP
X1785
,,"'"
Figure 3. The Readback Primitive
Figure 2. Readback State Diagram
XAPP 015.000
8-19
II
Using theXC4000 Readback Capability
bit shifted out of the lCA device. In the case of a Readback abort, RIP remains active until the Readback
sequence is terminated correctly.
r
• rdbk.DATA - The Readback data is available on the
DATA output of the Readback primitive. Each rising edge
on rdclk.l shifts one data bit from the lCA-intemal holding
register to the DATA output. The data bitstream is
explained below. There is an option to disable the user
data bits in the Readback bitstream.
~
Note that in XC3000 devices, the input pin MO/RTRIG is
used as a Readback Trigger pin and M1/RDATA as a
Readback Data pin. In XC4000, the MO pin can be used
as an input pin, the M1 pin as a 3-state output.
....
~
X1787
Figure 5. The XACT Readback Primitive
rdbk.TRIG and the rdbk.DATA signals are connected. The
rdclk.1 pin is connected to the CClK pin, if not connected
otherwise. See Figure 5.
Also, XC3000 has a MakeBits option to inhibit Readback.
In XC4000, conventional Readback is possible if the
Readback primitive is used in the design, or if a
Boundary-Scan Readback is performed.
Readback during a Boundary-Scan
No changes are required to prepare a design for Readback through the Boundary-Scan port. Contact Xilinx for
additional information.
Readback Initialization
There are three ways of preparing an lCA design for
Readback.
Configuration and Readback Bitstreams
• Using the Readback primitive on the schematic.
The XC4000 Configuration Bitstream
Figure 6 shows the format of the XC4000 configuration
bitstream, as generated by the XACT MakeBits program.
The bitstream consists of header and program data. The
header consists of four dummy bits, the preamble code,
the configuration-program-Iength count, and an additional
four dummy bits. The program data is divided into frames
consisting of a Start bit (0), the data field, and four error
check bits (eeee). The bitstream ends with eight or more
postamble bits (01111XXX). The exact number of the bits
in the bitstream is determined by the 24-bit programlength count.
• Activating Readback from the XACT Design Editor.
•
PROGRAMMABLE
INTERCONNECT
Performing a Readback during a Boundary-Scan
operation.
Readback from the schematic level
In the Xilinx Design Interface Libraries, there is a Readback primitive that can be called up into the schematic
like any other library primitive. Simply connect the inputs
and outputs of the Readback primitive to your user nets
as desired. See Figure 4 for an example.
Note: If the ClK. input is not connected to any net, the
Place-and-Route software connects it to the CClK input
pin, if the appropriate ClkSelect=Cclk was selected in the
MakeBits program.
The XC4000 Readback Bitstream
The Readback bitstream contains configuration information as well as the state of internal user logic. The Readback bitstream starts with five dummy bits. The Readback
data frame has the same format as the configuration data
frame which eases a bit-by-bit comparison between
Readback from the XD£
In XDE, the Readback primitive is located in the lower left
and lower right corners of the device. It is activated if the
IF UNCONNECTED,
"",......:..:R=EA..::D:=_D:::A.:..:.T:..:.A---t MDI
MDOc>-_.!..!R",EA.:::D=.-T:..:.R::oIG:::G::::E:..:.R_-I ..;.>__..,.T""RIG"
READBACK
RIP
IBUF
"786
Figure 4. Readback Symbol on the Design Schematic
XAPP 015.000
8-20
Readback and configuration data. Each data frame consists of a Start bit (0), the Data field, and four Stop bits
(1111). The bitstream ends with 11 CRC bits, Figure 7.
sent as additional clocks. During this period, the Readback data is High. The rdbk.RIP signal indicates the completion of a Readback process.
Both the configuration data and the internal-logic data are
included in the Readback bitstream. In the Readback bitstream, the configuration data bits are not inverted with
respect to the configuration bitstream. The user-logic
data bits, however, are inverted with respect to their values during Readback capture.
ClkSelect:
The read-back configuration data may differ from the original data downloaded into the device if CLB RAM is used
in the design. The RAM data is stored in the F- and Gfunction tables of the CLB.
The first two bits of the first Readback data frame are variable; they are non-user, non-configuration bits. Their input
state is dependent on the configuration speed and the
configuration error-check mode of the LCA device. The
last seven bits of the last Readback data frame are
always ones.
If Readback capture of user data is disabled in the MakeBits program, logic Highs replace the user data. Note that
the RAM data is not part of the captured user logic data; it
is contained in the read-back configuration data.
The bitstream ends with eleven bits of a CRC signature
appended. If ReadCapture is disabled and the design
does not use any CLB RAM, this signature will be constantin successive Readbacks. See below for more information on the Polynomial Cyclic Redundancy Check
CRC-16.
Software Support for Readback
The user can set Readback options with the MakeBits
program.The following MakeBits options are relevant for
Readback of XC4000 devices.
ReadCapture:
Settings:
Default:
Enable, Disable
Disable
This option determines whether the state of internal user
logic is included in the Readback bitstream. If ReadCapture is disabled, the user data is replaced by ones.
ReadAbort:
Settings: Enable, Disable
Default: Disable
ReadAbort enables the level-sensitive signal rdbk.TRIG
to abort the Readback. A High-to-Low transition stops the
Readback. Additional clocks must be supplied to terminate the Readback correctly. As a minimum, the number
of data frames contained in the device plus three must be
XAPP 015.000
8-21
Settings: CCLK, RDBK (user supplied)
Default: CCLK
The rdclk.1 pin can be connected to any user net or to the
CCLK I/O pin. With this option, the user can choose
between the alternatives.
MakeBits features an option used to create a "logic allocation" file «design_name>.LL) that contains information on
which bit in the Readback bitstream corresponds to which
Signal in the design. This ASCII mask file indicates the offset from the beginning of the Readback bitstream, the
frame number, the offset within a frame, and names of
user signals in the Readback bitstream. Figure 8 shows
an example.
Readback Timing
Minimum Readback frequency is 10kHz; maximum
Readback frequency is 1 MHz. The rdclk.l High time
and Low time are each 0.5 Ils min. See Table 1 for addi~
tional preliminary Readback switching characteristics.
Cyclic Redundancy Check (CRC) for LCA Configuration and Readback
Concept of the Cyclic Redundancy Check
The Cyclic Redundancy Check is a method of error detection in data transmission applications. Generally, the
transmitting system performs a calculation on the serial
bitstream. The result of this calculation is tagged onto the
data stream as additional check bits. The receiving system performs an identical calculation on the bitstream and
compares the result with the received checksum. CRC
Checksum Compare is often referred to as Signature
Analysis.
CRC During LCA Configuration
Each data frame of the LCA configuration bitstream has
four error bits at the end. See Figure 6. If a frame data
error is detected during the loading of the LCA device, the
configuration process with a potentially corrupted bitstream is terminated. The LCA pulls the INIT pin Low and
goes into a Wait state.
CRC During LCA Readback
During an LCA Readback, 11 bits of the 16-bit checksum
are appended to the end of the Readback data stream.
The checksum is computed using the CRC-16 CCITT
polynomial (Figure 9).The LCA checksum consists of the
11 most significant bits of the 16-bit code. A change in the
checksum indicates a change in the Readback bitstream.
Statistically, one in 2048 errors might go undetected.
I
Using theXC4000 Readback Capability
8 Dummy Bits Min
Preamble Code
Configuration Program Length
(MSB First)
4 Dummy Bits Min
111111111
0010 1
24-BIT LENGTH COUNT 1
1111 1
oj
DATA FRAME <0>
01
DATA FRAME <1>
I
I
I
1::::-I}
I
I
I
I
I
I
I
I
I
Program
Data
I eeee I
DATA FRAME
Postamble Code
1111XXX
t
Start
Bit
4 Error Check
Bits
X1791
XC4002A
4003A
4003H
4OO4A
4005l5A
4005H
4006
4008
4010
4013
4016
4020
Appr. Gate Count
2,000
3,000
3,000
4,000
5,000
5,000
6,000
8,000
10,000
13,000
16,000
20,000
ClB Matrix
30X30
Device
8X8
10X 10
10X 10
12 X 12
14X 14
14X 14
16 X 16
18 X 18
20X20
24X24
26X26
Number of ClBs
64
100
100
144
196
196
256
324
400
576
676
900
Number of Flip-Flops
256
360
200
480
616
392
768
936
1120
1536
1768
2280
Max Decode Inputs
(per side)
24
30
30
36
42
42
48
54
60
72
78
90
2,048
3,200
3,200
4,608
6,272
6,272
8,192
10,368
12,800
18,432
21,632
28,800
64
80
160
96
112
192
128
144
160
192
208
240
Max Ram Bits
Number of lOBs
Bits per Frame = (10 X number of Columns) + 7 for the top + 13 for the bottom + 1 + 1 start bit + 4 error check bits
Number of Frames = (36 X number of Rows) + 26 for the left edge + 41 for the right edge + 1
Program Data = (Bits per Frame X Number of Frames) + 8 postamble bits
PROM Size = Program Data + 40
The user can add more one bits as leading dummy bits in the header, or as trailing dummy bits at the end of any frame,
following the four error check bits, but the Length Count value must be adjusted for all such extra one bits,
even for leading extra ones at the beginning of the header.
Note: The configuration bitstreams are subject to change without notice.
Figure 6. XC4000 Configuration Bitstream Format
XAPP 015.000
8-22
5 DUMMY BITS
I
Dummy Bits
1
olxlxl
DATA FRAME <0>
1
01
DATA FRAME <1>
I 1 1 1 11
I
I
I
I
I
1111
I
I
I
1
I
I
I
1
J
Readback
Data
DATA FRAME
o
11 CRC BITS
CRC Checksum
t
Start
Bit
4 Stop
Bits
X1766
Figure 7. XC4000 Readback Bitstream
Offset
Column(Frame)
21
32
41
1
36640
36650
37044
37054
37064
37074
37084
37095
37105
303
303
307
307
307
307
307
307
307
Row(FrameOffset)
100
90
79
1
1
23
13
103
93
83
73
63
52
42
Description
P57 11
V37 11
P60 V1
CD
BD
LD
KD
JD
ID
HD
FD
ED
YQ
YQ
XQ
XQ
xQ
XQ
XQ
xQ
XQ
CFG/TOGGLE
CFG/RDATA_REG/Q9
CFG/RDATA_REG/Q1
CFG/RDATA_REG/Q2
REFDATA_REG/Q5
Figure 8. Sample logic Allocation File
II
XAPP 015.000
8-23
Using theXC4000 Readback Capability
Table 1. Readback Switching Characteristit:s
Finished
Internal Net
/,-----------11 ----------11
--I
1-\
~::=o
rdbk.TRIG
TG)
RTL
1-\- - - - - : - - - - - - -
::1-----
~~
rdclk.1
rdbk.RIP
S
rdbk.DATA
7
VALID
X1790
Limits
Description
rdbk.TRIG
rdclk.1
Symbol
Min
Max
Units
200
-
ns
rdbk.TRIG setup
1
T RTRC
rdbk.TRIG hold
2
T RCRT
50
rdbk.TRIG Low to
abort Readback
3
TRTL
100
rdbk.DATA delay
7
T RCRD
rdbk.RIP delay
6
T RCRR
High time
5
T RCH \
Low time
4
T RCL
~~~~
ns
250
ns
I:~.i5
250
ns
50
~
0.5
50
~
Notes:
1. liming parameters apply to all
speed grades.
2. If rdbk.TRIG is High prior to Finished, Finished will trigger the first
Readback.
ns
-'.C,
\'i
I
I
SERIAL DATA IN :
I
Polynomial: X16 + X15 + X2 + 1
I---------------------------
••• 1
1
1
1
LAST DATA FRAME _
t
1 0 15 14 13 12 11 10 9
~~
8
I
I
I
J
7 6 5
CRC - CHECKSUM--
~
Readback Data Stream
Figure 9. Circuit for Generating the CRC-16
XAPP 015.000
8-24
X1789
Boundary Scan in
XC4000 Devices
XAPP 017.002
Application Note
By LUIS MORALES
Summary
XC4000 LCA devices contain boundary-scan facilities that are compatible with IEEE Standard 1149.1. This
Application Note describes those facilities in detail, and explains how boundary scan is incorporated into an
LCAdesign.
Xilinx Family
Demonstrates
XC4000
Boundary Scan
Introduction
In production, boards must be tested to assure the integrity
of the components and the interconnections. However, as
integrated circuits have become more complex and multilayer PC-boards have become more dense, it has become
increasingly difficult to test assembled boards.
Originally, manufacturers used functional tests, applying
input stimuli to the input connectors of the board, and
observing the results at the output. Later, "bed-of-nails"
testing became popular, where a customized fixture
presses sharp, nail-like stimulus- and test-probes into the
exposed traces on the board. These probes were used to
force signals onto the traces and observe the response.
temporarily removed from the boundary-scan path by
bypassing its internal shift registers, and passing the
serial data directly to the next device.
XC4000 LCA devices contain boundary-scan registers that
are compatible with the IEEE Standard 1149.1, that was
derived from a proposal by the Joint Test Action Group
(JTAG). External (1/0 and interconnect) testing is supported; there is also limited support for internal self-test.
Overview of XC4000 Boundary-Scan Features
However, increasingly dense multi-layer PC boards with
ICs surface-mounted on both sides have stretched the
capability of bed-of-nail testing to its limit, and the industry is forced to look for a better solution. Boundary-scan
techniques provide that solution.
The inclusion of boundary-scan registers in ICs greatly
improves the testability of boards. Boundary scan provides
a mechanism for testing component II0s and interconnections, while requiring as few as four additional pins
and a minimum of additional logic in each IC. Component
testing may also be supported in ICs with self-test
capability.
Devices containing boundary scan have the capability of
driving or observing the logic levels on 1/0 pins. To test
the external interconnect, devices drive values onto their
outputs and observe input values received from other
devices. A central test controller compares the received
data with expected results, Data to be driven onto outputs
is distributed through a chain of shift registers, and
observed input data is returned through the same shiftregister path.
Data is passed serially from one device to the next, thus
forming a boundary-scan path or loop that originates at
the test controller and returns there. Any device can be
8-25
XC4000 devices support all the mandatory boundary-scan
instructions specified in the IEEE Standard 1149.1. A Test
Access Port (TAP) and registers are provided that implement the EXTEST, SAMPLE/PRELOAD and BYPASS
instructions. The TAP can also support two USERCODE
instructions.
Boundary-scan operation is independent of individual lOB
configuration and package type. All lOBs are treated as
independently controlled bidirectional pins, including any
un bonded lOBs. Retaining the bidirectional test capability
even after configuration affords tremendous flexibility for
interconnect testing.
Additionally, internal signals can be captured during
EXTEST by connecting them to unbonded lOBs, or to the
unused outputs in lOBs used as unidirectional input pins.
This partially compensates for the lack of INTEST support.
The public boundary-scan instructions are always available prior to configuration. After configuration, the public
instructions and any USERCODE instructions are only
available if specified in the design. While SAMPLE and
BYPASS are available during configuration, it is recommended that boundary-scan operations not be performed
during this transitory period.
In addition to the test instructions outlined above, the
boundary-scan circuitry can also be used to configure the
LCA device, and read back the configuration data.
I
Boundary Scan in XC4000 Devices
The following description assumes that the reader is
familiar with boundary-scan testing and the IEEE Standard. Only issues specific to the XC4000 implementation
are discussed in detail. For general information on boundary scan, please refer to the bibliography.
boundary-scan logic. Consequently, the operation of
the TAP controller cannot be affected by boundary-scan
test data.
Deviations from the IEEE Standard
Test Access Port
The boundary-scan logic is accessed through the Test
Access Port, which comprises four semi-dedicated pins:
Test Mode Select (TMS) , Test Clock (TCK), Test Oata
Input (TOI) and Test Data Output (TOO), as defined in the
IEEE specification.
Boundary-Scan Hardware Description
The XC4000 boundary scan implementation deviates
from the IEEE standard in that three dedicated pins
(CCLK, PROGRAM and DONE) are not scanned.
It should also be noted that the Test Oata Register contains three Xilinx test bits (BSCANT.UPO, TOO.O and
TOO.T) and that bits of the register may correspond to
un bonded or unused pins.
The TAP pins are permanently connected to the boundary-scan circuitry. However, once the device is configured, the connections may be ignored unless the use of
boundary scan is specified in the design (See "Using
Boundary Scan").
Additionally, the EXTEST instruction incorporates INTESTlike functionality that is not specified in the standard, and
system clock inputs are not disabled during EXTEST, as
recommended in the standard.
If the use of boundary scan is specified, the TAP input
pins (TMS, TCK and TDI) may still be shared with other
logic, subject to limitations imposed by external connections and the operation of the TAP Controller. In designs
The TAP pins (TMS, TCK, TOI and TOO) are scanned, but
connections to the TAP controller are made before the
1
Q
TEST·LOGIC·RESET
~
o
0
RUN·TESTIIDLE
~
)1--------------------------------,
1-_---,_ _ _ (1
SELECT·DR·SCAN
10
_ _ _ _. -_ _- J
(~
)1-1_ _ _ _ _.1
~
__- ,____
~
S_H_I~~.-D-R--~J:)O
____
1
1
(~ PA_U_S~E-.D-R--~J:)
____
0
NOTE: The value shown adjacent to each state transition in this figure
represents the signal present at TMS at the time of a rising edge at TCK.
Figure 1. State Diagram for the TAP Controller
XAPP 017.002
8-26
(
PAUSE·IR
Do
'-----,------"'
X2680
that do not use boundary scan after configuration, the
TAP pins can be used as inputs to or outputs from the
user logic in the LCA device. TMS, TCK and TDI are available as unrestricted I10s, while TOO only provides a 3state output.
TAP Controller
The TAP Controller is a 16-state state machine that controls the operation of the boundary-scan circuitry in
response to TMS. This state machine implements the
state diagram specified by the IEEE standard, Figure 1,
and is clocked by TCK.
A 3-bit status word returned to the central test controller
during an IR cycle comprises a boundary-scan availability
flag, preceded by two mandatory bits; 10 is a one and 11 is
a zero. This flag is High before and after configuration,
when the full boundary-scan capability is available, and
Low during configuration, when only SAMPLE/PRELOAD
and BYPASS are available.
Table 1. Boundary Scan Instructions.
Instruction
12
Upon power-up or assertion of PROGRAM, the TAP
controller is forced into the Test-Logic-Reset state. After
configuration, the controller is disabled, unless its use is
explicitly specified in the user design.
Instruction Register
Loading a 3-bit instruction into the Instruction Register
(lR) determines the subsequent operation of the boundary-scan logic, Table 1. The instruction selects the source
of the TOO pin, and selects the source of device input and
output data (boundary-scan register or input pinluser
logic)
Note: In XC4000, whenever the TAP Controller is in the
Shift-DR state, all data registers are shifted, regardless of
the instruction. DR data is modified even if a BYPASS
instruction is executed
11
TDO
Source
Test
Selected
10
110 Data
Source
0
0
0
EXTEST
DR
DR
0
0
1
SAMPLE!
PRELOAD
DR
Pin/Logic
0
1
0
USER 1
TDOl
Pin/Logic
0
1
1
USER 2
TD02
Pin/Logic
1
0
0
READBACK
Readback Data
Pin/Logic
1
0
1
CONFIGURE
DOUT
Disabled
1
1
0
RESERVED
-
-
1
1
1
BYPASS
Bypass Reg
Pin/Logic
10 is closest to DTO
The Boundary-Scan Data Register
The Data Register (DR) is a serial shift register implemented in the lOBs of the LCA device, Figure 2. Potentially,
each lOB can be configured as an independently controlled
bidirectional pin. Therefore, three data register bits are
sd
Q\-tt---+lD
It---HLE
Q
To Global
Clock Buffer
(CLK Pad Only)
Qhl---H
I
X2672
Figure 2. Boundary Scan Logic in a Typical lOB
XAPP 017.002
8-27
Boundary Scan in XC4000 Devices
instruction and the resulting logic outputs captured during
a subsequent EXTEST. It must be recognized, however,
that all DR bits are captured during an EXTEST and,
therefore, may change.
provided per lOB: for input data, output data and 3-state
control. In practice, many of these bits are redundant, but
they are not removed from the scan chain.
An update latch accompanies each bit of the DR, that is
used to hold injected test data stable during shifting. The
update latch is opened during the Update-DR state of the
TAP Controller when TCK is Low.
Pull-up and pull-down resistors remain active during
boundary scan. Before and during configuration, all pins
are pulled up. After configuration, the lOB can be configured with a pull-up resistor, a pull-down resistor or neither. Internal pull-up/pull-down resistors must be taken
into account when designing test vectors to detect open
circuit PC traces.
In a typical DR instruction, the DR captures data during
the Capture-DR state (on the rising edge of TCK). This
data is then shifted out and replaced with new test data.
Subsequently, the update latch opens, and the new test
data becomes available for injection into the logic or the
interconnect. The injection of data occurs only if an
EXTEST instruction is in progress.
The primary and secondary global clock inputs (PGCK1-4
and SGCK1-4) are taken directly from the pins, and cannot be overwritten with boundary-scan data. However, if
necessary, it is possible to drive the clock input from
boundary scan. The external clock source is 3-stated,
and the clock net is driven with boundary scan data
through the output driver in the clock-pad lOB. If the
clock-pad lOBs are used for non-clock Signals, the data
may be overwritten normally.
Note: The update latch is opened whenever the TAP Controller is in the Update-DR state, regardless of the instruction. Care must be exercised to ensure that appropriate
data is contained in the update latch prior to initiating an
EXTEST. Any DR instruction, including BYPASS, that is
executed aher the test data is loaded, but before the
EXTEST commences, changes the test data.
Figure 3 shows the data-register cell for a TAP pin. An ORgate permanently disables the output buffer if boundaryscan operation is selected. Consequently, it is impossible
for the outputs in lOBs used by TAP inputs to conflict with
TAP operation. TAP data is taken directly from the pin, and
cannot be overwritten by injected boundary-scan data.
The IEEE Standard does not require the ability to inject
data into the on-chip system logic and observe the results
during EXTEST. However, this capability helps compensate for the lack of INTEST. Logic inputs may be set to
specific levels by a SAMPLE/PRELOAD or EXTEST
/1
/
/
sd
Q f#----+J 0
II
IIOIII~D
\
r--'"-~
Q
t---HLE
(To
To TAP
Controller
LCAI~!~onneCI)
vee
Qf#----+JO
\
\\
t----IHLE
\,
10B.O - - - H > - - l - - 4 - - - - - I - - - - + - - - - J '
\ (From LCA Interconnect)
\
10B.T - - h r l - - + - - - - - t - - - - j - - - - - - - t - - r......
"\
Q
\
\
\\
~-~
Towards TOO
\
ShiWCapture
ORCK
Update
Test Logic
Reset
Configured
EXTEST
-:,.,~~_'''''_ _''"',._"_.,''''~'''''''"<~"<<<•..,,...'~_A'_...' .. ~''.~~._.,,.,,~f'<._.~.,<,,'>,y•• >-~'""'''f<.»<·'''''' .•y.f''''<<<.'''AA#<<"''''<<<<._''--.....--lTOI
>------1 TMS
~-From
User Logic
TCK
TOO
--~
TD01
SEL1
TD02
SEL2
To User
Logic
X2676
Figure 6. Typical Non-Boundary-Scan TOO Connection
If the BSCAN primitive is not included, boundary scan is
not selected, and the lOBs used by the TAP inputs pins
are freely available to PPR as general purpose lOBs. The
TOO output pin may used as a logic output by explicitly
connecting the TOO pad primitive to an OBUF or OBUFT
as required, Figure 6.
Boundary scan may also be selected in the XACT Design
Editor. The EditBlk command is used to change the configuration of the BSCAN block, found in the top left corner
of the die. USED is toglgled so that it is highlighted. The
TAP pins are permanently connected to the BSCAN
block, although the connections are not explicitly shown.
Connections to user test logic may be made using the
design editor, if required.
XC4000 Boundary-Scan Instructions
The XC4000 boundary scan supports three IEEE-defined
instructions, EXTEST, SAMPLE/PRELOAD and BYPASS,
two user-definable instructions, USER1 and USER2, and
two LCA-specific instructions, CONFIGURE and READBACK. The instruction codes are shown in Table 1.
EXTEST - While the EXTEST instruction is present in the
IR, the data presented to the device output buffers is
replaced by data previously loaded through the boundary-scan DR and stored in the update latch, Figure 7.
Similarly, the output 3-state controls are replaced, and the
data passed to internal system logic from input pins is
replaced.
When a DR instruction cycle is executed, data arriving at
the device input pins is loaded into the DR. The data from
the system logic that drives output buffers and their 3state controls is also loaded. This action occurs during
the Capture-DR state of the TAP controller, Figure 1. Data
is serially shifted out of the DR during the Shift-DR state;
simultaneously, new data is shifted in. In the Update-DR
state, the new data is transferred into the update latch for
use as replacement data, as described above.
Since the DR and Update latch are modified during any
DR instruction cycle, including BYPASS, the data in the
update latch is only valid if it was loaded in the last DR
instruction cycle executed before EXTEST is asserted.
)(2675
Figure 5. Boundary-Scan Schematic Symbols
XAPP 017.002
~
OBUFT
The replacement of system data with update latch data
starts as soon as the EXTEST instruction is loaded into
the IR. For this data to be valid, it must have been loaded
by a previous EXTEST or SAMPLE/PRELOAD operation.
DRCK
IDLE
From=+-
User
Logic
8-31
I
Boundary Scan in XC4000 Devices
From
Previous
Cell
To
Next
Cell
--+--+-1----+1
DRCK
Update - DR
System
Logic
T
---"--+--1------1---1----1..,)
o
----~--1------1------I..,)
X2677
Figure 7. EXTEST Data Flow
The IEEE definition of EXTEST only requires that test
data be driven onto outputs, that 3-state output controls
be overridden, and that input data be captured. The capture of output data and 3-state controls and the forcing of
test data into the system logic is normally performed during INTEST.
The XC4000 effectively performs EXTEST and INTEST
simultaneously. This added functionality permits the testing of internal logic, and compensates for the absence of
a separate INTEST instruction. However, when performing an EXTEST, care must be taken over what signals are
driven into the system logic; data captured from internal
system logic must be masked out of the test-data stream
before performing check-sum analysis.
BYPASS - The BYPASS instruction permits data to be
passed synchronously to the next device in the boundaryscan path. There is a 1-bit shift register between the TDI
and TOO flip-flop.
USER1, USER2 - These instructions permit test logic,
designed by the user and implemented in CLBs, to be
accessed through the TAP. Test clocks and paths to TOO
are provided, together with two signals that indicate that
user instructions have been loaded. For details, see the
User Registers section above.
SAMPLE/PRELOAD - The SAMPLE/PRELOAD instruction permits visibility into system operation by capturing
the state of the I/O. It also permits valid data to be loaded
into the update register before commencing an EXTEST.
The OR and update latch operate exactly as in EXTEST,
see above. However, data flows through the I/O unmodified.
XAPP Ot 7.002
8-32
User tests depend upon CLBs and interconnect that must
be configured to operate. Consequently, they may only be
performed after configuration.
CONFIGURE - XC4000 LCA devices can be configured,
or reconfigured through the TAP. Like EXTEST, this
instruction is only available before INIT goes High or after
a conventional configuration is finished.
After loading the CONFIGURE instruction, TCK clocks a
normal configuration bit-stream into TDI while the TAP
controller is in the Shift-DR state. The configuration pre-
amble is passed to both TDO and DOUT. Configuration
bits used by the device are not passed to the output, but
are replaced by ones, as in a conventional configuration.
Any bits beyond those required to configure the device
are passed to TDO and DOUT.
READBACK - READ BACK permits the configuration
data of an LCA device to be read back through the TAP.
This instruction differs from other boundary instructions in
two ways.
• The readback logic is triggered (equivalent to CaptureDR) during the Update-IR state when the READBACK
instruction is loaded. To re-trigger the readback logic,
some other boundary-scan instruction must first be
loaded, and then the READBACK instruction reloaded.
order and function of bits in the boundary-scan data register are included in this description.
BSDL files for XC4000 devices can be obtained from your
Xilinx FAE, or by calling the Xilinx Applications Hotline.
These files may also be downloaded from the Xilinx
Technical Bulletin Board (BBS), and have filenames
.bsm.
Bibliography
The following publications contains information about the
IEEE Standard 1149.1, and should be consulted for general boundary-scan information beyond the scope of this
application note.
• TDI does not connect to the input end of the READBACK shift register. Consequently, data from upstream
devices is lost.
Colin M. Maunder & Rodham E. Tulloss. The Test Access
Port and Boundary Scan Architecture. IEEE Computer
Society Press, 10662 Los Vaqueros Circle, P.O. BOX
3014, Los Alamitos, CA 90720-1264.
For details of the read back bit-stream, see the Xilinx
Application Note "Using the XC4000 Readback Capability" (XAPP 015).
John Fluke Mfg. Co. Inc. The ABC of Boundary Scan
Test John Fluke Mfg. Co. Inc., P.O. BOX 9090, Everett,
WA98206.
Boundary Scan Description Language Files
GenRad Inc. Meeting the Challenge of Boundary Scan.
GenRad Inc., 300 Baker Ave., Concord, MA 01742-2174.
Boundary Scan Description Language (BSDL) files
describe boundary-scan-capable parts in a standard format used by automated test-generation software. The
Ken Parker. The Boundary Scan Hanbdbook. Kluwer
Academic Publications, (617) 871-6600.
I
XAPP 017.002
8-33
Implementing Logic in the
Universal Interconnect Matrix
XAPP 033.000
Application Note By FRZAD NEKOOGAR
Summary
This Application Note describes how to implement logic functions using the AND capability of the Universal
Interconnect Matrix.
Xilinx Family
Demonstrates
XC7200IXC7300
Universal Interconnect Matrix
Introduction
The Universal Interconnect Matrix (UIM) provides an AND
function that can be used in various ways. This Application Note describes how to expand the input capacity of a
Function Block, create an OR function using De Morgan's
Theorem, and use the UIM as a decoder or signal
blocker.
Using the UIM
these terms may be factored out and ANDed in the UIM,
using the NODE(UIM) declaration. This technique frees
up Function Block inputs for use by other signals, as
demonstrated by the counter design shown in Figure 1.
The carry signals can be expressed in PLUSASMTM with
the following equations.
CARRY_8
= 00*01*02*03*04*05*06*07
CARRY_16
= CARRY_8*08*09*010*011 *012*013
*014*015
Function-Block Input-Capacity Expander
Each function block has 21 inputs from the UIM. When
the design equations contain common ANDed terms,
FB
Q16
X1816
Figure 1. Function Block Input-Capacity Expansion
8-34
De Morgan OR Gates
The AND function in the UIM can be converted to an OR
function using De Morgan's Theorem. Two or more Function Block outputs are inverted into the UIM and ANDed,
Figure 2; the result is inverted at the Function Block
inputs. Under De Morgan's Theorem, an AND with
inverted inputs and outputs is equivalent to an OR.
Function Block
In PLUSASM, this technique is implemented in two parts.
First, a NOR function is created by inverting the inputs to
the UIMAND.
SUM1_NOR_SUM2
= SUM1
• SUM2
The inverse of SUMCNOR_SUM2 is then used in subsequent equations.
D = SUM1_NOR_SUM2 •
+ E • F ...
Functions larger than 16 p-terms split into intermediate sums
joined by a negative-logic OR gate in UIM with no spaed penalty.
+
Decoding in the UIM
Figure 3 shows how to use the UIM in the XC7200 as a
decoder. The decoder output can feed directly into a
Function Block without additional delay.
X3212
Figure 2. Implementing a DeMorgan OR Gate
PLIN
The PLUSASM equations for the decoder are as follows.
U
=A
UIMAND
PLIN
• B
V = A' B
X
Y
= A'
= A'
B
B
Signal Blocker
A signal can be enabled or disabled in the UIM by ANDing it with a control signal, as illustrated in Figure 4.
A~U
This operation can be expressed in PLUSASM by the following equations.
C
= BUS1
= BUS2
V
X
V
X1810
A = BUSO • GATE
B
B
2-Bit
Decoder
Figure 3. UIM Decoder
• GATE
UIMAND
• GATE
BUSOCJ------~~~--~
UIMAND
BUS1~r-----i=~==r-~~
UIMAND
BUS2~r-----i=~==r-~~
GATE
~-------'
X1809
Figure 4. Using the UIM to EnablefDisable Signals
XAPP 033.000
8-35
I
Comparison of XC3000
Counter Designs
XAPP 041.001
Application Note By BERNIE NEW
Summary
This Application Note discusses the functional, performance and density characteristics of the various counter
designs available for the XC3000. Differences in these characteristics must be taken into account when choosing the most appropriate design.
Xilinx Family
XC3000IXC31 00
Introduction
explanatory, and can often be traded against each other.
However, it must be realized that as a counter becomes
more complex, it usually becomes both larger and
slower.
When selecting a counter design for a specific application, there are three primary considerations: does it meet
the functional requirements, is it fast enough and could it
use fewer LCA resources?
Counter Designs
The functional requirements that must be considered
include binary/non-binary operation, up, down and up/
down counting, loadability, the provision of set/clear,
count enable and synchronous operation to permit output decoding. Speed and resource utilization are self-
All the counters discussed in this Application Note have
predictable binary-count sequences, and are fully synchronous designs. Table 1 summarizes the characteristics of the various counter designs. The same information is shown graphically in Figure 1.
Table 1. Counter Performance Summary
Counter Performance Summary
Up!
8·Bil
10·Bil
12·Bil
16·Bil
20·Bil
24·Bil
32·Bil
Loadable Up Down Down MHz CLBs MHz CLBs MHz CLBs MHz CLBs MHz CLBs MHz CLBs MHz CLBs
XC310D-3
XAPP 001
XAPP 002
XAAP 002
XAPP003
XAPP004
XAPP004
XAPP 014
XC3000-12S
XAPP 001
XAPP 002
XAPP002
XAPP003
XAPP004
XAPP004
XAPP014
•
•
•
•
• •
• •
• •
• •
•
•
•
•
•
•
•
•
•
•
•
• •
•
•
•
173
47
5
8
63
9
116
38
8
10
108
37
9
12
52
15
•
•
•
81
26
5
33
9
8
60
21
8
10
•
• Estimated
56
21
9
12
29
15
107
29
41
48
54
46
204'
14
16
17
20
23
27
24
103
22
57
17
24
26
30
25
95'
14
16
17
20
23
27
24
55
13
17
20
17
20
103
22
55
11
21
24
37
37
49
56
21
20
49
56
21
24
X3200
8-36
Comparison of XC3000 Counter Designs
* XAPP 014
175
~>----o
100
XAPP 001
75
(a)
~003
MHz
__
50
V XAPP 002
XAPP 004
(Up/Down)
"I(
25
'tr-----i; XAPP 002
8
10
12
16
20
24
32
Bits
60
XAPP 004
(Up/Down)
XAPP 004
(b)
ClBs 40
20
8
10
12
16
20
24
I
32
Bits
X3078
Figure 1. Counter Speed and Density (XC31 00)
XAPP 041_001
8-37
High-Speed Synchronous Prescaler Counter
(XAPP 001)
This simple design provides a very basic non-Ioadable, up
counter with a count-enable control. However, this simplicity permits it to be both the densest and the second
fastest design.
A prescaler (CEP/CET) technique is used to gain speed,
permitting the ripple-carry portion of the counter eight
clock periods in which to settle. Without special adaptation, however, this technique precludes loading the
counter. As a non-Ioadable counter, three bits can be
implemented in three CLBs (1 CLB/bit), with the least significant six bits requiring only four CLBs; this explains the
compactness. Only one TILO delay is incurred in the
ripple-carry path for each three bits. This permits good
speed to be maintained, even in long counters.
It is easy to convert the design into a down counter, but n
not possible to convert it into an up/down counter.
Simple, Loadable, Up/Down Counter (XAPP 002)
Being loadable, this counter is unable to benefit from the
prescaler technique, and a simple ripple-carry scheme is
used throughout. Consequently, it is slower than the
above design. The maximum clock frequency is inversely
proportional to the length of the counter; the ripple-carry
path incurs one TILO delay for each two bits.
With two CLBs required for each two bits, the CLB density
is similar to the above counter (1 CLB/bit). However, there
is no equivalent reduction in complexity in the low-order
bits, and the design, therefore, requires more CLBs.
The up/down-control logic is incorporated into the carry
path, but does not impact the speed or the density; these
attributes are determined by the number of outputs rather
than the logic complexity. Optimal up counters and down
counters can be implemented by simply tying the up/down
control to the appropriate logic level. APR will eliminate
any redundant logic, but the speed will not improve, nor
will the CLB count decrease.
A modification to this counter almost doubles the maximum clock rate by dividing the carry path into two halves.
The carry output of the lower half is used as a parallel
count enable in the upper half. This use of a parallel count
enable should not be confused with the prescaler technique; the carry path must still settle within one clock
period. However, with this modification, it settles in
approximately half the time. This technique effectively
implements a conditional-sum incrementer within the
counter.
This modification requires one additional CLB. Enable
Clock is used for the parallel count enable, and the extra
CLB is necessary to ensure that the clock is enabled during loading.
XAPP 041.001
8-38
Synchronous Presettable Counter (XAPP 003)
In this design, speed is increased by replacing the serial
gating of the ripple-carry path with parallel gating. Ideally,
with arbitrarily wide gates, the carry-path settling time
could be reduced to one gate delay.
However, with limited gate width, the settling time
increases logarithmically with counter length; this is still a
significant improvement over the linear increase seen previously, especially in longer counters. The additional
speed is achieved at the cost of using more CLBs with
more complex routing.
The specific implementation in the Application Note is for
a modulo-N counter that could be used as a timer. The
counter reloads whenever its terminal count is reached.
To prevent loading from limiting the counters performance, detection of the terminal count is pipelined, permitting the load operation a full clock period.
The introduction of this pipeline stage essentially prevents
the counter from being loaded at an arbitrary time. However, the pipeline could easily be removed for more general counter applications.
Loadable Binary Counter (XAPP 004)
The loadable binary counter also uses parallel gating to
accelerate the carry path. In this case, however, a more
structured approach is taken. A fast lookahead-carry technique is used, resulting in a carry path with a consistent
depth of gating. Consequently, there are many equally
critical paths.
The regular structure lends itself to hand placement when
maximum speed is the objective. The irregularity and
fewer critical paths of the previous design reduces its
dependence on CLB placement. The previous design will,
therefore, perform better using the automatic placement
tools, and it is possible to improve its performance by rerouting a few critical paths. However, it will not match the
performance of the current design when optimally placed.
Ultra-Fast Synchronous Counters (XAPP 014)
In some applications, such as clock division, the only
requirement of a counter is that it count very fast. This
counter is designed to fill that need. Compared to the first
design described above, this design is approximately
twice as fast, but uses almost twice as many CLBs.
The key to its high speed is the use of a prescaler technique, together with an "active Longline" to distribute the
parallel count enable. This distribution scheme uses replicated flip-flops to eliminate the delay and depends, for its
operation, upon the predictability of the binary sequence.
For a more detailed description of the above designs, see
the individual Application Notes.
High-Speed Synchronous
Prescaler Counter
XAPP 001.002
~
Application Note By PETER ALFKE AND BERNIE NEW
Summary
Borrowing the concept of Count-Enable Trickle/Count-Enable Parallel that was pioneered in the popular 74161
TTL-MSI counter, a fast non-load able synchronous binary counter of arbitrary length can be implemented efficiently in XC3000-series LCA devices. For best partitioning into CLBs, the counter is segmented into a series of
tri-bits. Design files are available for 8, 10, 12, 16, 20 and 24-bit versions of this counter.
SpeCifications
Xi/inx Family
Length
Maximum Clock Frequency
XC31 00-3
Number of CLBs
8
173
5
16 Bits
XC3000IXC31 00
Demonstrates
107 MHz
14
Fast Counter Technique
Introduction
Operating Description
Prescaler-counter designs originated with small, highspeed counters used to divide an incoming clock frequency and, thereby, provide a clock to a larger, slower
counter. This scheme was adapted for use in cascading
the synchronous 74161 counter.
The least significant tri-bit has a Count-Enable Output
(CEO) that is routed to all the Count-Enable-Parallel
(CEP) inputs in the rest of the counter.
The Count-Enable Output from any other tri-bit drives
the next more significant Count-Enable-Trickle (CET)
input. The clock causes any tri-bit to increment only if all
its Count-Enable (CE) inputs are active. CEO is active
when all three bits are set and CET is High. CEP does
not affect CEO.
The Terminal Count of the least significant 74161 was
used as a parallel clock enable to the remaining
counters. This effectively reduced the clock rate to those
counters by a factor of 16, allowing their ripple-enable
path 16 times longer to settle.
Using CEP, the least-significant tri-bit stops the remaining counter chain for seven out of eight clock pulses,
allowing ample time for the CEO-CET ripple-carry chain
to stabilize. The maximum clock rate is determined by
the Clock-to-CEO delay of the first tri-bit (TCKO + T ILO),
plus the CEP input set-up time of the other tri-bits (TICK)
and the routing delay of the CEP net.
This only worked if the counter was not loaded. If it were,
the first parallel enable would typically occur less than
16 clocks after the load. Depending on the value loaded,
the ripple-enable path might not have time to settle.
Techniques exist to overcome this problem, but for a
non-Ioadable counter they are unnecessary. This application note describes a 103-MHz 24-bit non-Ioadable
counter, as shown in Figure 1. For optimal CLB usage,
the counter is partitioned into 3-bit sections (tri-bits), the
first of which acts as the prescaler.
2CLBs
For a 24-bit counter in a -125 device, this critical delay
can be less than 25 ns. The higher tri-bits are not speed
critical if they propagate the CET Signal in less than eight
clock periods, easily achievable for counters as long as
20 tri-bits, i.e. 60 bits.
1
2CLBs
JJ
I
3CLBs
CEP
-
CE
CEO
-.-
CE
CEO
OA
OB
Oc
OA
OB
Oc
I
I
I
I
I
I
r-
CET
I
CEO
I
3CLBs
CEP
I
~}-
CET
OA
OB
Oc
I
I
I
X2013A
Figure 1. 50 MHz Non-Loadable Binary Counter
~ Supporting design files are available on the Xilinx
Technical Bulletin Board under the name XAPPOO1V (Viewlogic)
8-39
I
As shown in Figure 2, the two least-significant tri-bits fit
into two CLBs each. The higher tri-bits have two CountEnable inputs (CEP and CET), and require three CLBs
each.
Adding this pipeline stage reduces the critical CEP delay
to 20 ns, and increases the maximum clock rate to
50 MHz. In an XC3100 the maximum clock rate is
103 MHz.
For faster operation, it is possible to pipeline the CEP,
separating into two clock periods the detection of Term inal Count in the first tri-bit and its distribution as CEP.
The modification to the first tri-bit is shown in Figure 3.
The state before Terminal Count is detected. The flip-flop
is set for the duration of the terminal count state.
Implementation Notes
If this modification is used, the CET input to the first tri-bit
will no longer act correctly as Count Enable for the entire
counter. The EC pin on the CLBs should be used in
its place.
~
"-
g~Dr-------------------
Soft macros are available for 8, 10, 12, 16, 20 and 24-bit
counters. A READ. ME file accompanying these macros
describes the implementation.
cgrn
PERMANENTLY HIGH IN SECOND
TRI·BIT
'
OB
Oc
In this counter, the critical delay is the distribution of the
CEP Signal, and for maximum speed, this should use a
Longline. Consequently, the counter should be partitioned using CLBMAPs and should occupy a row or column ofCLBs.
OB
~------------------ CEO
oc
CEO
CET
CEP
OA
OB
CE~_.----------~I
CET
o
CEP
X2011A
X2012A
Figure 2s. First and Second Tti-bits Use TWo ClBs Each
XAPP 001.002
Figure 2b. All More Significant Trl-blts Use Three ClBs
8-40
High Speed Synchronous Prescaler Counter
Q f----;;--.
CEO
CE
CE
CE
CE
CE
X2014A
Figure 3. Least Significant Tri-bit with Pipeline
I
XAPP 001.002
8·41
Simple Loadable
Up/Down Counter
XAPP 002.002 ID
Application Note By BERNIE NEW
Summary
The 5-input function generator of the XC3000 family CLB makes it possible to build fully synchronous, loadable
up/down counters of arbitrary length. These use only one CLB per bit, and the ripple carry delay is only 1/2 T ILO
per bit. Design files are available for 8, 10, 12, 16, 20 and 24-bit versions of this counter. A 16-bit higher performance version is also available.
Specifications
Length
Maximum Clock Frequency XC3100-3
Number of CLBs
Xi/inx Family
16 Bits
41 MHz
17
XC3000IXC31 00
Demonstrates
Simple Counter Technique
Introduction
Using a ripple-carry technique, this simple counter
requires the least number of CLBs of any XC3000 loadable counter. To improve its performance, the counter is
partitioned into 2-bit segments. While the maximum
clock frequency remains inversely proportional to the
number of bits, this partitioning reduces the incremental
delay to one TILO per bit-pair.
approximately doubled, and the additional resources
consumed are minimal.
As shown in Figure 1, the counter is broken into equal
halves. For up/down counting and loading, the ripplecarry path in both halves must settle within one clock
period, as must the CEP distribution net. This distribution delay is in series with the carry path of the lower
bits, and an unequal split might be used to compensate.
Operating Description
The performance of ripple-carry counters benefits
greatly from hand-placement of the CLBs, in that zerodelay direct interconnects can be exploited in the critical
carry path. With automatic placement, a more complex
counter, with fewer routing delays in the critical path,
offers better performance at the expense of using more
CLBs.
If only an up counter or down counter is required, the up/
down counter may be entered into the schematic with
the up/down control tied to a logic one or zero as necessary. APR automatically eliminates the redundant logic
to create the up or down counter. In this case, however,
the number of CLBs cannot reduced, but routing
resources are conserved. Up and down counter designs
obtained in this manner cannot be improved upon if this
ripple-carry technique is to be used.
The basic counter cell, shown in Figure 2, uses two
CLBs. The first CLB implements two Hype flip-flops.
Along with the trigger inputs, these flip-flops have independent data inputs and a shared parallel enable to
facilitate loading.
The second CLB implements two bits of the ripple-carry
chain. The second carry bit is derived from two counter
bits and a carry input. In this way, only one TILO delay is
incurred per bit-pair. Down counting is achieved by
inverting the counter bits into the carry chain. Counters
0 0•7
P~~!-~~~ ---1>--+---~_-----'
The widely used CEP/CET prescaler technique for
speed enhancement cannot be used in counters that are
up/down or loadable. Up/down counters might reverse
their direction of count at any time, and do not guarantee
the ripple-carry chain a sufficient number of clock periods in which to stabilize. Similarly, loadable counters do
not guarantee adequate time after a load.
PE
CE
°
C~U~~ER
TC
Q
E~~~~~---~-----~
Q0-7
However, some speed improvement may be gained by
using CEP and CET. While this improvement is not as
large as that offered by a prescaler, the clock rate is
~ Supporting design files are available on the Xilinx
Technical Bulletin Board under the name XAPP002V (Viewlogic)
0 8 •15
Q8·15
Xl961A
Figure 1. Loadable Counter Using CEP/CET
8-42
of any length may be implemented by simply cascading
as many of these 2-bit cells as necessary.
gated on zero-delay direct interconnects. Consequently,
the counter should be partitioned using CLBMAPs and
should occupy a row or column of CLBs. This organization also permits CEP to be distributed on a Longline, if
needed.
When implementing the CET/CEP version, the EC pin of
the CLB is used for CEP. This necessitates an additional
OR-gate to enable the clock during loading. If only an upcounter or down-counter is implemented, this OR-gate
may be nested into the CLB that generates CEP.
Soft macros are available for 8, 10, 12, 16,20 and 24-bit
versions of the basic counter. A 16-bit counter using the
CET/CEP technique is also available as a soft macro. A
READ.ME file accompanying these macros describes the
implementation.
Implementation Notes
To minimize the ripple-carry delay, the carry CLBs should
be adjacent to each other, so that the carry can be propa-
CEI--~~~-----------------------,
......------/
UP/DOWN ---+----i~--
}--t--- CEO
L-----------------------------~----------------------------_.QB
Q
PE
Q
II
~--~--+_--------------------------------~
X1962
Figure 2. 2-Bit Counter Cell
XAPP 002.002
8-43
Synchronous
Presettable Counter
Application Note By PETER ALFKE AND BERNIE NEW
XAPP 003.002 i5
Summary
Presettable synchronous counters are implemented, where the carry path utilizes parallel gating to replace the
serial gating found in ripple-carry counters. The result is fewer CLB delays in the critical path, but more CLBs
are used and the routing is less regular. Design files are available for 8, 10, 12, 16, 20 and 24-bit versions of
this counter.
Xi/inx Family
Specifications
Length
Maximum Clock Frequency
XC31 00-3
8
Number of CLBs
9
16 Bits
63 48 MHz
20
Introduction
In most counters, the maximum operating frequency is
determined by the time it takes the carry path to settle
after a clock. Given the new state, each bit must decide
whether or not to toggle on the next clock. If the information, on which this decision is based, does not reach the
bit in time, the counter will malfunction.
In ripple-carry counters, this information is passed from
bit to bit through a chain of AND gates. While this structure can be exploited to obtain very fast routing, the
delay still becomes prohibitive in longer counters.
The counter described in this Application Note replaces
the chain of AND gates with an AND-gate tree. Data
must pass through fewer gates to reach its destination
and the carry path settles faster.
The irregular structure of the counter makes it difficult to
establish an optimum placement. However, the fewer
routing delays in its critical path reduce the dependence
on good placement. This makes it ideal for use with
automated design tools.
The counter detects Terminal Count and loads the value
applied to its parallel input. This allows the counter to
operate with any modulus. Two versions of the counter
are described: an up counter and a down counter.
Operating Description
An 8-bit version of the counter is shown in Figure 1. The
basic counter cell is two loadable T-type flip-flops implemented in a single CLB. The trigger inputs are driven
from the array of AND gates, that combine all lower bits
into a trigger input. In the 8-bit case, there are no more
than two levels of AND gates.
A point of interest
Instead of detecting
count earlier, and a
state. Normally, TC
XC3000IXC3100
Demonstrates
Fast Counter Technique
Parallel Enable within one clock period. The pipeline
separates these two functions, and increases the maximum clock rate.
There is one trivial disadvantage to using this pipeline: if
the counter is loaded with all ones, it does not load again
on the following clock. Instead, it rolls over to all zeros
and counts until it again reaches terminal count.
The TC pipeline flip-flop is provided with a Reset. This is
intended for use immediately after power-up. It eliminates the potentially long delay before the first TC. Until
the first TC, the counter cycle is not controlled by the
load value.
Figure 2 shows how the counter may be converted to a
down counter. The only change is to invert all the inputs
to the AND gates, including the 1-input AND gate that
drives the· trigger input of bit 1. This inversion is
absorbed into the counter cell.
Implementation Notes
For optimum partitioning, this counter should be implemented using CLBMAPs. Soft macros are available for
8, 12 and 16-bit up counters and down counters. A
READ.ME file accompanying these macros describes
the implementation.
Enhancements
The counter may be modified such that it may be loaded
at any time, not just at Terminal Count. The Load
comand is used to reset the TC pipeline flip-flop. This
causes the active-Low Parallel Enable to be be asserted
and the counter loads on the next clock pulse.
However, this technique must be used cautiously. If the
flip-flop is reset when the count is one before TC, the
Parallel Enable is asserted for two clocks. If this situation
cannot be avoided, the active-Low Parallel Enable must
be ANDed with Terminal Count at the input to the flipflop, thus ensuring that a second load cannot occur.
is the pipe lined Terminal Count.
all ones, a value is detected one
flip-flop is set during the all ones
must settle and be distributed as
i5 Supporting design files are available on the Xilinx
Technical Bulletin Board under the name XAPPOO3V (Viewlogic)
8-44
~XILINX
T2
CLK
Q
DO
T3
C
T4
T.
D,
T4
D4
TS
TS
DS
T7
TS
DS
II
'T
7 ,
D
Q
TERMINAL
COUNT
D7
X'963
Figure 1. PreseHable Up Counter
XAPP 003.002
8-45
Synchronous Presettable Counter
T2
CLK
Q
°o--+-+-----------~_1
T3
C
T.
T5
O,--+-+-----------~_1
°2--t-+-----------~__1
13 --+-+----IL_,/
°3--+-+-----------~~
1.
O.
T6
15
05
T7
16
06
T7 --t-t----IL.-/
o
Q
TERMINAL
COUNT
°7--+-+-----------~~
X'984
Figure 2. Presettable Down Counter
XAPP 003.002
846
Loadable Binary Counters
XAPP 004.002
~
.
Application Note By BERNIE NEW
Summary
The design strategies for loadable and non-Ioadable binary counters are significantly different. This application
note discusses the differences, and describes the design of a loadable binary counter. Up, down and up/down
counters are described, with lengths of 16 and 32 bits. Design files are available for all six versions.
Specifications
Xilinx Family
Length
Maximum Clock Frequency XC31 00-3
54 MHz
16 Bits
Number of CLBs
23
XC3000IXC3100
Demonstrates
Fast Counter Technique
Background
Loadable Binary Up Counter
When designing a non-Ioadable counter, the fastest
designs use some form of prescaler technique to exploit
the fact that the more significant bits toggle much more
slowly than the less significant bits.
When designing a loadable binary counter, emphasis
must be placed on balancing the carry delays. Unlike the
prescaler counter, high-speed paths are of no benefit,
and slow paths cannot be hidden. Figure 1 shows a
good example of a loadable binary counter.
The carry chain for the first few bits of the counter can
usually be implemented in parallel and is very fast. However, the carry chain for the more significant bits usually
requires multiple levels of gating and is' much slower.
Using prescaler techniques, the counter can operate at
the speed of the less significant bits, by giving the more
significant bits several clock periods inwhichto settle.
Typically, a 2- or 3-bit prescaler generates ,a high-speed
count-enable signal that is broadcast through the more
significant bits every four or eight clocks. In between
these enables, the more significant bits are stable; the
carry chain for these bits, therefore, has four or eight
clocks periods in which to settle, instead of one.
These techniques depend upon the predictability of the
binary sequence, and the implied low-speed operation of
the more significant bits. When a counter is loaded, however, the binary sequence is disturbed, and its predictability is lost.' To ensure correct operation following a
load, the' carry chain for the entire counter must settle
before the next clock.
This reduces the speed of a prescaler counter significantly. Its operating frequency becomes constrained by
the slow more significant bits rather than by the fast
prescaler.
This counter is based on a 2-bit cell, as shown in
Figure 2. The two. bits are implemented in two CLBs,
using loadable T-type flip-flops. Only one carry-in is
required, the second carry-in being derived within the
.cell. The CLB clock enable may be used as Count
Enable; however, the bits cannot be loaded while disabled. To overcome this, Parallel Enable must be ORed
into the Count Enable line.
To form the carry chain, output bits are ANDed into
groups of two and four, using the propagate cell shown
in Figure 3. The propagate outputs are then ANDed
together to form the even carries, according to the formulae of Table 1. Carries to the odd-weighted bits are
generated within the counter cell.
With the exception of the trivial less significant bits, all
carry delays comprise two levels of combinatorial CLB.
This is longer than the direct paths from the less significant bits found in prescaler counters. However, prescaler .counters typically have longer more-significant-bit
delays, which is the chief speed constraint of a loadable
counter.
The partitioning of the carry logic into the CLBs allows
the counter to be implemented in an N-shaped configuration. A suggested placement of the CLBs is shown in
Figure 4. Restricting the carry chain to a 2 x 4 block of
CLBs minimizes the routing delays among them. With
this organization, simulations show the counter will operate at 54 MHz.
There are techniques such as pulse-swallowing and
state-skipping that can be used to. load a prescaler
counter without loss of speed. However, these result in
non-binary operation for a short time after loading, and
some load values are not permitted.
~ Supporting design files are available on the Xllinx
Technical Bulletin Board under the name XAPP004V (Viewloglc)
8-47
II
PE
n
1-
!0!1
COUNTER
CEll
r--+
~11
--
-
PO-I
COUNTER
CELL
~
Po-s
!4!5
Po-3
COUNTER
CELL
~
~
--
-
C6
P4-7
1
P a•11
C 12
~
~
I
!!
COUNTER
CELL
COUNTER
CELL
!-
r-------+
r-----+ Og
r-------+
I-- all
~
t---'-+
I--
P 12•15
P 12•15
CIa
TC
--.
~
C 16
~
Figure 1. 16-Bit Loadable Binary Counter
XAPP 004.002
r-----+
P 12 P 13
~.tlI5
C 14
P 12·13
r-------+
10 11
1
COUNTER
CEll
r--l
C 12·14
1-1-,-
COUNTER
CELL
n
P a•11
>----+
r!
C 10
P8-g
----
P6 Pg
Ca
C8-10
-1--
COUNTER
CEll
h
PH
r-----+'0 1
7
!61
C6
PH
r-------+ '
8-48
X19C1S
Loadable Binary Counters
C 6 = PO-3· P4-5
CS=PO-3·P4-7
c j _....--+_ _-11
C 10 = P O-3 • P 4-7· P S-9
PI--+-1-----------~
C 12 = PO-3 • P 4-7· P S-11
C 14 = PO-3 • P4 -7 • PS-ll • P12-13
PE~~-+------------~
C 16 = P O-3 • P 4-7· P S-11 • P 12-15
)(2652
Table 1. Carry Logic Equations
°
Pj+l-1---1-----------~
°i+l
Xl966A
Figure 2. 2-Bit Counter Cell
OJ
Q i+1
Q i+2
Q i+3
°0
0,
°2
°3
°4
Os
C8/10
Os
°9
PO.3
P S.l1
°,0
0"
°5
P4-7
P,3·,S
°,2
°,3
°7
c 6l1S
C'2114
°,4
°,5
~
I
I
./
~
~
'\
./
Xl969A
Xl967
Figure 3. Propagate Cell
Figure 4. CLB Placement
For an 18-bit counter, C 16 may be used as carry-in to bits
16 and 17, as shown in Figure 5. Additional TC logic must
also be included. This extension does not involve additional levels of logiC, but may incur additional routing
delays.
Loadable Binary Down Counter
The 18-bit counter may easily be extended to 32 bits by
replicating bits 4 through 17, and using TC/C 1S in the
upper section in place of what was PO-3 ' This entails one
additional combinatorial delay, which reduces the maximum operating frequency to 37 MHz.
If this additional delay is unacceptable, two 16-bit
counters may be concatenated, using C16 as the clock
enable to the counter bits in the upper half. However, this
creates two problems. Clock enable can no longer be
used to provide count enable, and the counter may only
be loaded when the lower half is at terminal count.
Both of these problems can be overcome separately, but
not together. If C 16 is moved to a separate CLB, a fifth
input may be added. This could be Count Enable, whichshould be ANDed with the existing C 16 , or Parallel Enable
which should be ORed with it.
XAPP 004.002
8-49
If the counter bits are viewed as T-type flip-flops, the purpose of the carry chain is to determine which bits of the
counter are to be toggled. For an up counter, a contiguous group of bits is toggled, starting with the least significant bit and extending up to, and including, the first zero.
For a down counter, this group extends up to, and
includes, the first one. The operation of the carry chain is
the same in each case, but with the role of input ones and
zeros reversed. Consequently, an up-counter may be
converted into a down counter by simply inverting the output bits into the carry chain.
This requires two modifications to the up counter. First, all
inputs to the propagate cells must be inverted, as shown
in Figure 6. Second, the counter cell must be modified so
that the direct path from the even bit to the odd bit
becomes inverting, as shown in Figure 7. In all other
respects, the counter remains the same. Performance
and expandability are unaffected.
II
P16 P17
PE
C;
C16 -
0;
0 16
Q i+1
0 17
c;
COUNTER CELL
--.--,...----11
P;-;--T-----~
PO-3 PS-11
P6-7 P12-15
PE~_r_t------~
0 16
P16-17
0 17
~m
t=:u
Q i+1
P;+l-i---t-------t
X1970
Figure 5. Extension to 18 Bits
Figure 7. 2-Bit Down-counter Cell
X1972A
Loadable Binary Up/Down Counter
--t---+-q
o i+l --t-........-t--q
0;
a i+2
°i+3
==t===3-.-/I--+--
To create an. up/down counter, simply make the above
inversions programmable_ For the counter bits, this is not
a problem. An XOR gate is placed in the direct path, as
shown in Figure 8_
Pi. i+3
The propagate cells are more of a problem. The 2- and 4input functions become 3- and 5-input when the up/down
control is added; they can no longer share a single CLB.
X1971A
Figure 6. Down-counter Propagate Cell
The propagate cells must be split in two CLBs each, and
the 3-input functions combined if necessary_ Two or four
additional CLBs are required, and additional routing
delays might be created due to the higher fan-outs and
the longer signal paths among the greater number of
CLBs.
This design results in 16-bit up/down counters that operate at 46 MHz, and 32-bit up/down counters that operate
at more than 37 MHz
XAPP 004.002
8-50
Loadable Binary Counters
PD-V-:
Pj
PE
0
OJ
0
Q i+1
~~
UP/DOWN
-
bSD-v-:
X1973
Figure 8. 2-Bit Up/Down-counter Cell
I
XAPP 004.002
8-51
Ultra-Fast
Synchronous Counters
Application Note By BERNIE NEW
XAPP 014.001
Summary
This fully synchronous, non-Ioadable, binary counter uses a traditional prescaler technique to achieve high performance. Typically, the speed of a synchronous prescaler counter is limited by the delay incurred distributing
the parallel Count Enable. This design minimizes that delay by replicating the LSB of the counter. In this way
even the small Longline delay is eliminated, resulting in the fastest possible synchronous counter.
Specifications
Counter Length
Maximum Clock
Frequency
Number of CLBs
Xilinx Family
XC4000
(-5)
XC31 00
(-3)
16
16
111
17
204
24
XC3000
(-125)
16 Bits
95 MHz
24
XC30001XC3100
XC4000
Demonstrates
Ultra-fast Counter Design
Introduction
Implementation
The use of a prescaler is a common technique for
improving counter performance. Originally, a small highperformance counter was used to divide an incoming
clock, thus providing a slower clock to a larger, lowerperformance counter. This technique has since been
adapted to synchronous counters.
XC3000
The XC3000 design for the ultra-fast counter is shown in
Figure 1. This design uses two parallel count enable signals, Qo and CEP2. Qo acts as a 1-bit prescaler, halving
the effective clock rate in the rest of the counter. It is the
distribution of Qo that is critical, and depends upon replication.
In a synchronous counter, the first few bits of the counter
are decoded to create a parallel Count Enable (CEP).
This clock enable is used to reduce the effective clock
rate. The carry chain in the more significant bits is,
thereby, allowed several clock periods in which to settle.
However, using this technique results in a counter that,
without further adaptation, is non-Ioadable.
Typically, in the LCA implementation of such a counter,
the critical delay is the generation and distribution of
CEP. This delay can be shortened by pipelining CEP and
using a high-speed Longline for its distribution. However,
where ultimate speed is the objective, even the relatively
small Longline delay can be eliminated.
Even with the effective clock rate halv!=,d, it is necessary
to use a second 2-bit prescaler for any significant length
of counter. The parallel count enable signal (CEP2),
generated by this second prescaler, occurs once every
eight clock cycles. Reducing the effective clock rate by a
factor of eight permits the use of a siliiple ripple carry
scheme for the remaining bits of the counter. TheQo
prescaler allows two clock cycles for the distribution of
CEP2, and a Longline is adequately fast
Except for the Q 1 flip-flop, the column of CLBs on the left
consists entirely of replicated LSBs. Only one flip-flop, at
the top of the column, is configured to toggle. The
remaining flip-flops in the column act as slaves to this
one master flip-flop.
To eliminate this delay, the LSB of the counter is replicated to create an "active Longline." This involves locating an LSB replica immediately adjacent to each bit in
the counter. In counter organizations where one CLB
provides the flip-flops for two counter bits, the number of
replicas required is approximately half the number of bits
in the counter.
'
These slave flip-flops are organized as a shift register
with inverters between stages. At each stage there is a
pair of flip-flops (QXOj and QYOj) contained within a single CLB. The two flip-flops operate in parallel. This duplication permits both vertical direct interconnect to the
next stage, and horizontal direct interconnect to the
counter bits.
In XC3000 designs, direct interconnect can be used
between the LSB replicas and the counter bits. This
results in an effective distribution delay of zero. In
XC4000 designs, the residual routing delay is minimal.
The first stage toggles by continuously loading the
inverse of its current state. Stage two loads the inverse
8-52
SD-o
a
01
01
>
-[>0-
0
o~
[>
.>:.:.:,-.
5rlD-o
•
~o
a
oX0 1
>
L[r-o
Lr
a ~Y01
~1
[>
a
1
02
~
a
1
CEP2
0
>
Logic 1
~o
a
h
oSD-o
02
[>
-[>0-
0
0
11
03
a
1
04
[>
a ~Y02
>
-[>0-
a
llbSD=o
>
a I OX03
~o
-
~
[>
>
LV-
E=
I
a
1
05
D
X3203
Figure 1. X3000 Ultra-Fast Counter
XAPP 014.001
8-53
Ultra-Fast Synchronous Counters
of stage one, delayed by one clock period. Given that
stage one is toggling, this combination of inversion and
delay causes stage two to operate in synchronism with
stage one, as shown in Figure 2. Similarly, stage three
operates in synchronism with stage two, and so on. This
slave mode of operation guarantees that all N stages will
operate in synchronism after no more than N-l clocks,
regardless of their initial state.
To avoid unnecessary loading on the direct interconnects,
the 00 output is taken from the last stage of the shift
register. Otherwise, the additional loading would cause a
small increase (-0.1 ns) in the direct interconnect delay,
and this would reduce the maximum clock frequency by
-1 MHz.
The second prescaler, 0 1 and O2 , is a simple 2-bit
counter, enabled by 0 0 . CEP2 is High for two Clock periods while 0 1 and O2 are both High. The CEP2 pipeline
flip-flop is also enabled by 0 0 . In this way, CEP2 changes
at the same time as 0 1 and O2 , and each has two clock
periods in which to set up. CLB input constraints require
that O2 be externally routed to the CEP2 decoder.
CLOCK
00
aX01 aY01
(00 DELAYED)
n L..J11LJ11LJIr
-.J
X1794A.
Figure 2. Operation of LSB Shift Register
XC4000
The XC4000 deSign, shown in Figure 3, is very similar to
the XC3000 design. The principle difference is that the
dedicated carry logic can be used in the more significant
bits of the counter.
The remaining bits of the counter use a ripple-carry
scheme. Pairs of bits are implemented together, using
two CLBs per pair. One CLB provides the two flip-flops,
and is placed adjacent to a 0 0 CLB to exploit the direct
interconnect. The second CLB implements the carry
chain, with each pair of bits adding one TILO delay. To
minimize the cumulative delay and maximize the counter
length, direct interconnect should also be used in the
carry path.
To maximize the performance, all critical paths are
restricted to single-length interconnects, only one of
which is driven from any output. This again requires that
pairs of flip-flops be used in each stage of the LSB shift
register. Using double-length interconnects or driving
multiple single-length lines, the number of flip-flops can
be reduced, with only a slight loss of performance.
With all critical delays reduced to a clock-to-output delay
plus a set-up time, with no routing delay, the minimum
clock period is 10.5 ns (95 MHz). The ripple-carry delay in
the more significant bits in an XC3000-125 counter is
approximately 15 ns plus 5.7 ns per bit-pair. With the
counter running at its minimum clock period, the carry
chain has 84 ns in which to settle. This will permit up to 12
bit-pairs in the ripple carry path. A counter running at the
maximum speed can, therefore, have up to 27 bits
including the prescalers.
The minimum clock period is the clock-to-output delay
plus routing delay and set-up time. With the interconnection strategy described above, this can be kept
below 9 ns (111 MHz). The ripple-carry delay in the more
significant bits is 13 ns plus 1.5 ns per bit-pair. The 72 ns
available permits a theoretical maximum counter length
of 87 bits. In practice, the number of bits will be limited by
the loading on the Long line distributing CEP2. The
available time should allow counters in excess of 20 bits
long to be constructed.
XAPP 014.001
8-54
SD-D
a
0,
0,
>
Lf>o-
0
O~
[>
'&
0
Q
OYO ,
priD-D
a
~XO,
I>
Q
~02
>
D
a
1
Q
1
Q
1
Q
L~
~1
CEP2
0
I>
\7
0
1
I>
[>
0
a
~D-D
CARRY
lOGIC
Q
~X02
l>
~D-D
~
>
lOGIC
~
'V
0
>
Q
OY03
~D-D
~
lOGIC
~
Figure 3. XC4000 Ultra-Fast Counter
XAPP 014.001
8-55
Q
1
II
as
>
Xl 793
Accelerating Loadable
Counters in XC4000
XAPP 023.001
Application Note By BERNIE NEW
Summary
The XC4000 dedicated carry logic provides for very compact, high-performance counters. This Application
Note describes a technique for increasing the performance of these counters using minimum additional logic.
Using this technique, the counters remain loadable.
Xilinx Family
Demonstrates
Vr"'Annn
"'-"""vvv
Dedicated Carry Logic
High-performance Counter Design
Introduction
The dedicated carry logic in XC4000 LCA devices provides a mechanism for very fast and efficient counters.
While the ripple-carry scheme appears simplistic, the
hardware implementation of the dedicated carry logic is
very fast, and requires few CLBs. In fact, the implementation is so efficient that it defeats most attempts to replace
it. It is possible, however, to augment the operation of the
carry logic and obtain higher performance.
To reduce the ripple-carry delay, the effective length of
the carry path must be shortened. This is achieved by
dividing the counter into two sections that settle in parallel, as shown in Figure 1. The carry output of the leSS-Significant section provides a parallel Count Enable (CEP) to
the more-significant section.
The carry delay is reduced to the settling time of the more
significant section, or the settling time of the less
significant section plus the subsequent routing and countenable times, whichever is greater. For optimum
Do - Dj.1
performance, these times should be balanced, requiring
that the counter be divided into two unequal parts.
The use of CEP does not imply that these are prescaler
techniques. In a prescaler counter, CEP is typically
decoded from the least significant two or three bits. The
CEP signal is then used to enable the remaining bits,
such that their effective clock rate is one fourth or one
eighth of the actual clock rate. This allows multiple clock
periods for the remaining bits to settle, and the whole
counter can be operated at the speed of the prescaler.
Using the prescaler technique, it is not possible to load the
counter and guarantee that it will count correctly on the
following clock cycle. The carry chain in the more significant bits is designed to settle in multiple clock periods. If
the loaded data causes these bits to be enabled on the
clock following the load operation, the carry path will not,
in general, have had adequate settling time. Depending
on the value loaded, it might not be possible to resume
counting for several clock periods after the load operation.
OJ - D n_1
-------.1
j
I
PE---I-I--I
l
PE
lS
ClK
1>
CEP PE
0
Counter
0
MS
CEP
Counter
a
I
I
!
a
1
OJ- On·1
Figure 1. Accelerated N-Bit Counter
8-56
X3073
Accelerating Loadable Counters in XC4000
The acceleration technique described in this Application
Note does not depend upon carry chains having multiple
clock periods in which to settle; the entire carry chain settles within one clock period. However, the clock period is
reduced because parallelism is introduced into the carry
chain. The improvement is not as dramatic as with a prescaler, but loadability is retained.
If the counter length is an exact multiple of four, the moresignificant section should be 10 bits longer than the lesssignificant section. A 32-bit counter, for example, should
be split into sections of 11 and 21 bits.
This split creates a 7.5-ns difference in settling times to
accommodate the additional delay. The set-up time is
4 ns, and consequently, 3.5 ns is available for routing. A
Longline should easily meet this requirement, leaving the
speed controlled by the more-significant section of the
counter.
Two versions of the technique are described below. One
version uses two dedicated carry-logic chains, and is
increasingly effective in longer counters. For shorter
counters, a second version uses CLBs for the less significant section, and decreases the clock period by a fixed
amount (1.5 ns in an XC4000-5). While the benefit from
this second version is small, it can sometimes be crucial.
Figure 2 illustrates the benefits derived from the two versions. In either case, one additional CLB is required to
accelerate the counter.
As described in the Application Note, Estimating the Performance of XC4000 Adders and Counters (XAPP 018),
the estimated minimum clock period for an N-bit counter
is the following.
tCLK-CLK
= 13 + 0.75N ns
Assuming that the speed of the accelerated counter is
determined by the more-significant section, this reduces
to the following.
Operating Description
Long-Counter Version
To accelerate long counters, the carry chain must be
divided into two unequal parts. The less significant section
should be shorter to accommodate the distribution and
set-up times of CEP. For optimum performance, each section of the counter should contain an odd number of bits.
!eLK-ClK = 17.5 + 0.375N ns
As a result, the clock period of a 32-bit counter is reduced
from 37 ns to 29.5 ns.
For counters with an even length that is not divisible by
four, the more-significant section should contain eight
15
60
I
N
50
20
40
25
::;:
I
CEP
.:.
~~
-
o
"~~
0
Do
00
i>
'----
CEP
PE
CE
X3076
Figure 4_ Short Accelerated Counter
I
XAPP 023.001
8-59
Complex Full-Featured
Counters Run at 40 MHz
XAPP 034.001
Application Note By JEFFREY GOLDBERG
Summary
This Application Note illustrates the implementation of long high-speed counters in Xilinx EPLDs. The Universal
Interconnect Matrix eliminates the speed degradation usually associated with increasing counter length.
Xilinx Family
Demonstrates
XC7200/XC7300
High-speed Counter Design
STAGE 1
Introduction
Instrumentation, video/graphics and digital-signal-processing (DSP) applications use complex full-featured
counters as building blocks. These counters might be
used for prescalers, pulse generators, frequency
counters or complex address generators. Typical counter
requirements are listed below.
QA
QB
QC
QD
0
QE
E
QF
F
QG
G
QH
H
ENUP SCUP
EN ON SCDN
So
S1
A
B
C
• Up-Down Operation
• Synchronous Load
• Synchronous Clear
• Cascadable to 64 Bits at 40 MHz
QA
QB
QC
QD
0
QE
E
QF
F
QG
G
QH
H
ENUP SCUP
ENDN SCDN
So
S1
A
B
C
PL869P
The Xilinx family of EPLDs is well suited for implementing
high-speed full-featured counters. The wide fan-in of each
Function Block and the Macrocell XOR gate, coupled with
the capabilities of the Universal Interconnect Matrix
(UIMTM), permit high-speed counters with no trade-off
between speed and density. Any counter output can feed
any other Macrocell in the device with no speed degradation thus simplifying real-world systems.
High-speed counters are easily implemented by cascading up to eight instances of the 8-bit counter (PL869P)
from the component library. Each 8-bit counter occupies
nine Macrocells. Any number of 8-bit counters can be
cascaded up to the capacity of the device, yet the 40
MHZ maximum speed is maintained for any length of
counter. Figure 1 illustrates how counters can be cascaded. In this example, two 8-bit counters are cascaded
into a 16-bit counter.
STAGE 2
PL869P
Functional Truth Table
S1
So
ENUP
EN ON
L
L
L
L
L
H
H
L
H
H
H
H
L
H
X
X
L
H
L
H
L
L
H
H
X
X
X
X
FUNCTION
CLEAR
HOLD
COUNT UP
COUNTDOWN
HOLD
LOAD
HOLD
X1795
Figure 1. Cascaded Counter
8-60
Complex Full-Featured Counters Run at 40 MHz
Counter Implementation
operations performed in the UIM cause no additional
delay between Function Blocks. The resulting advantages are demonstrated by the PL869P counter.
Figure 2 shows one bit of the PL869P counter. The XOR
gate reduces the required number of product terms to
four per bit. The remaining 13 product terms are not
shown. The Macrocell output is available through the Universal Interconnect Matrix (UIM) to all Macrocells in the
device. In an XC7200-25, the clock-to-setup time from
any Macrocell flip-flop through the UIM to any Macrocell
flip-flop is 25 ns. This permits a maximum clock frequency
of 40 MHz. Macrocell outputs are also available as device
outputs.
The PL869P counter is actually composed of three elements, as shown in Figure 3. Two of these elements, the
logic for the eight counter bits and a carry lookahead for
the down-counting serial carry (SCDNX) are implemented
in Macrocells. The serial carry outputs (SCUP and
SCDN) for each stage of the counter, however, are
formed in the UIM.
While it appears that the carry Signals ripple through the
AND gates of each stage, the carry outputs are actually
generated in parallel. The critical path limiting the maximum count frequency is the propagation delay from the
carry output of the least significant eight bits to the countenable input of the most significant eight bits. This delay
is constant, independent of the counter length.
The key to implementing long, complex, high-speed
counters is the UIM ability to simultaneously provide interconnect and logic function. Generating product-terms in
the UIM reduces the number of inputs required in each
Function Block, and improves speed and density. AND
Programmed Functionality of Macrocell
X1796
Figure 2. PL869 Counter Bit
ENUP
ENUP
A
A
X
B
C
D
E
PLAND12
F
F
G
H
ENUP
ENDN
So
Sl
Z
SCDN
SCDNX
SCUP
C
D
E
G
H
ENUP
ENDN
So
Sl
X
B
SCUP
Z
PLAND2
PLAND2
ClK
PLB69PX
ENDN
ClK
Pl869PX
ENDN
PL869P
PLB69P
Figure 3. PL869P Counter
XAPP 034.001
SCDN
SCDNX
8-61
X3199
I
High Performance Counters
Using Xilinx EPLDs with
ABEL-HDL
XAPP 038.001
Application Note
By JEFFREY GOLDBERG
Summary
Xilinx EPLDs are capable of implementing counters that operate at the maximum device frequency. This Application Note explains how ABEL-HDL can be used to implement such counters.
Xilinx Family
Demonstrates
XC7200IXC7300
High-speed Counter Design
Introduction
The Xilinx XC7200 and XC7300 families of EPLD devices
are we" suited for implementing large, fully featured,
high-speed counters. Such counters benefit from the
wide fan-in of the Function Blocks (21 inputs) and Macrocells (17 product terms), the XOR gate in the Macrocell,
and the logic capabilities of the Universal Interconnect
Matrix (UIM). Together, these features permit the implementation of high-speed counters with no trade-off
between speed and density.
This Application Note demonstrates the use of ABEL-.HDL
and the ABEL XFER utility to generate counter equations.
ABEL-HDL is a powerful tool for describing high-performance counters. Just as with the more familiar 22V10
low-density PAL device, only minimal knowledge of the
Xilinx EPLD Function Block is required when generating
the source code. Properly used, ABEL-HDL produces
PLUSASM equations that map efficiently into the Xilinx
EPLD architecture, and the resulting equations implement long, complex counters that run at the full speed of
the device.
Architecture Overview
A rudimentary understanding of the Xilinx EPLD architecture is helpful when designing efficient counters. Figure 1
shows the three major components of the architecture.
The Function Blocks are PAL-like logic blocks, where
most, but not a", logic functions are performed. Each
Function Block contains nine Macrocells. These Macrocells share 21 inputs, and every Macrocell has its own
output. In this application, each Macrocell implements
one bit of the counter.
Interconnection among Function Blocks is provided by
the UIM. This fully populated switch matrix connects all
device inputs and Function Block outputs to a" the inputs
of every Function Block. In addition, the UIM can perform
an ANDs of a" Function Block outputs and device inputs.
I/O blocks interface the Function Blocks to the device
pins. They contain input latches and registers that can be
useful for data storage.
The keys to implementing long, complex, high-speed
counters in Xilinx EPLDs are the XOR gate in each Macrocell and the AND capability of the UIM. The XOR gate is
particularly useful when implementing loadable counters,
Figure 2. The XOR gate reduces the required number of
product terms to only four per bit; 13 unused product
terms remain available.
Loadable counters can be implemented more efficiently
with XOR gates and D-type flip-flops than with T-type flipflops. The Xilinx EPLD architecture can force the counter
feedback Low whenever LOAD is asserted. The counter
bit can then be loaded using only one product term.
Counters implemented with T-type flip-flops require two
product terms for synchronous loading, since the conditions that force the flip-flop to toggle depend on both the
data input and the counter state.
This difference is especially important when the counter
is loaded from multiple sources. As shown in Figure 3, the
Xilinx EPLD requires only one additional product term for
each additional source, while a T-type flip-flop would
require two additional product terms.
The UIM is actually a very wide AND array that operates
without introducing additional delay. Implementing product terms in the UIM reduces the number of inputs into
each Function Block, and also improves speed and density. Counters implemented using the UIM can run at the
full device speed, independent of their length.
Figure 4 shows the implement.ation of a 27-b~t counter.
Nine counter bits are mapped Into each Function Block.
Notice how the outputs from the first nine bits (QO ... 8) and
8-62
High Performance Counters Using Xilinx EPLDs with ABEL-HDL
Function BLOCK
~
-
I
r-r,1/0
Block
r
Universal
Interconnect
Matrix
9
-
r
21
-
I
_r-
OR
Array
~
I
AND
Array
r---
Macrocell
r--
I-I-I--
Cell 2
Cell 4
t-t-t--
r---
CeliS
r--
I-I--
CeliS
t-t--
r--r---
CeliS
Cell 3
Cell 7
r-r--
Cell 9
9
9
1
VO
Block
r--
FB
FB
~
~
'---
9
9
1
X3186
Figure 1" Xilinx EPLD Architecture
X3187
Figure 2" Bidirectional, Loadable Counter Bit
ILOAD" 0
lOAD" SEl B" DATA B
ClK
CLOCK
X3188
Figure 3a" Loadable Counter with Multiplexed Inputs, Xilinx EPLD Architecture
I
T
lOAD" SEl S" DATA B"O
0
ClK
CLOCK
X3189
Figure 3b" Loadable Counter with Multiplexed Inputs" T-type Flip-Flop Architecture
XAPP 03S.001
8-63
the Count Enable are ANDed in the UIM to form their Terminal Count, COUNT_FB2. This Terminal-Count signal
enables the second group of nine bits (Q9 ... 17). Similarly,
most significant of nine bits are enabled by Terminal
Count, COUNT_FB3, generated by ANDing the second
group of nine outputs with the least significant nine and
the Count-Enable signal.
The critical path that limits the count frequency runs from
the least significant bit to the Count-Enable input of the
most significant stage. This path delay is independent of
the number of function blocks it spans. Consequently, any
length counter that spans multiple Function Blocks can
operate at fMAX' 60 MHz in an XC7236A-16.
ABEL-HDL Counter Implementation
When generating ABEL-HDL counter descriptions for a
Xilinx EPLD, keep in mind the basic features of the architecture.
•
Each Function Block has 21 inputs, and comprises
nineMacrocelis with one output each.
• Each Macrocell has a D-type flip-flop preceded by an
XOR gate.
• The UIM is a wide AND array
For the highest performance, maximize the number of
counter bits in each Function Block. In unidirectional
counters, nine bits of a loadable up counter or down
counter can fit into a single Function Block. Bidirectional
counters, however, can only fit eight bits into a Function
Block. This reduction is caused by the need for two Terminal Count signals, one for up counting and one for down
counting.
As shown in Figure 5, the up-counting Terminal-Count
signal can be generated in the UIM, just as it would be in
an up counter. The down-counting Terminal Count is the
AND function of the inverted counter bits, i.e., an all-zero
018
}----ID
a H-+-t--
X3190
Figure 4. 27-Bit Loadable Up Counter
XAPP 038.001
8-64
High Performance Counters Using Xilinx EPLDs with ABEL-HDL
detect in place of an all-one detect. This requires the use
of a Macrocell, and consequently, only eight are available
for counter bits.
To avoid additional logic delay, the down-counting Terminal-Count signal is pipelined; the state immediately preceding Terminal Count is detected, and the result is
registered on the same clock that moves the counter into
its Terminal-Count state. To ensure correct operation during loading, the load value is inspected, and the pipeline
flip-flop set appropriately at the load clock.
If the counter outputs must be compared to a dynamic
value, leave one Macrocell available in each Function
Block to perform the comparison. The fitter portion in the
ABEL complier recognizes that the comparator and
counter can share common Function Block inputs, and
maps them into the same Function Block.
Once the number of counter bits that fit into any Function
Block is determined, the ABEL source code can be written. Here are some key points to remember when generating the source code.
• Declare each counter bit with the istype 'reg,xor'
attribute to take full advantage of the XOR functionality
of the Macrocell ALU. Then use the xoUactors keyword to define the signal that drives one input of the
XOR gate. If at all possible, keep this signal down to
one product term.
down_a
• Declare the terminal count look-ahead function of each
stage, e.g., the down terminal count of bidirectional
counters, as node istype 'reg'. This function will be
mapped into a Macrocell.
• Declare the up-terminal count, or a down-counter
down-terminal count, of each stage as node istype
'com'. Since the Function Block outputs and inputs can
be inverted, modulo-n stages can be defined and the
terminal count can still be generated in the UIM. This
function will be mapped into the UIM when it is
declared as NODE (UIM) in the PLUSASM top-level
design file.
• While implementing counters, be sure to completely
specify the function so that ABEL can minimize the
logic. Whenever PLUSASM is generated for a function
declared with an xor attribute, ABEL expresses the
equation in PLUSASM ALU syntax. XEPLD will not further minimize these equations.
• Unless a counter is manually partitioned in the top
level design file using PLUSASM 'Partition' statements, the fitter is free to map the counter bits in any
way it chooses. Consequently, the counter may map
into multiple Function Blocks, achieving what the fitter
considers a best fit given the 1/0 requirements; the fitter may not map the maximum number of counter bits
into each Function Block.
D---+_--------
ClK D - - - I
lOAO C>----1
d[O:15) C>----1
up_a
I
D---++--------X3191
Figure 5.16-Bit Bidirectional Loadable Counter
XAPP 038.001
8-65
Additionally, unnecessary inputs may be consumed in the
Function Blocks that contain the higher order counter bits.
These inputs are consumed by lower order counter bits
that are ANDed in the Function-Block AND array to form
Terminal Count signals, instead of being ANDed in the
UIM.
This may not be a problem. Provided a design can access
all the Macrocells it requires, any additional inputs are
available at no cost. When it is necessary to free up Function Block inputs, first determine from the fitter mapping
report how the counter is mapped. Using this information,
modify the ABEL-HDL source code to create counter
block that correspond to the counter bits that are mapped
into each Function Block. Terminal Count signals can then
be generated using UIM ANDs, thus minimizing the number of inputs used on each Function Block.
XAPP 038.001
In practice, the fitter tends to keep many of the counter
bits together. The best strategy is to assume that the maximum number of bits will be implemented in each Function
Block, and then optimize the source code to free up more
inputs if necessary.
The following examples show how to implement counters
in Xilinx EPLDs using.ABEL-HDL. Example 1 implements
the simple 27-bit loadable up-counter shown in Figure 4.
Example 2 implements an 8-bit loadable, bidirectional
counter, as shown in Figure 2. Example 3 expands upon
Example 2, and uses ABEL-HDL to implement the 16-bit
loadable, bidirectional counter shown in Figure 5. The
ABEL source codes and PLUSASM top level design files
follow.
8-66
High Performance Counters Using Xilinx EPLDs with ABEL-HDL
Example 1. 27-Bit Loadable Up Counter
Example 2. 8-Bit Loadable, Bidirectional Counter
ABEL Source Code
ABEL Source Code
module upcntr
title 'Ioadable 27 bit loadable up counter
each 9 bit stage fits in one fb
up terminal counts formed in uim
Jeffrey Goldberg
Xilinx';
upcntr device;
" Inputs
pin;
Clk,load,count
pin;
dO,d1,d2,d3,d4,d5,d6,d7,d8
pin;
d9,d10,d11,d12,d13,d14,d15,d16,d17
pin;
d18,d19,d20,d21,d22,d23,d24,d25,d26
.. Outputs
qO,q1,q2,q3,q4,q5,q6,q7,q8
pin istype 'reg,xor';
q9,q10,q11,q12,q13,q14,q15,q16,q17
pin istype 'reg,xor';
pin istype 'reg,xor';
q18,q19,q20,q21,q22,q23,q24,q25,q26
" Nodes
node istype 'com';
counUb2,counUb3
" Variables
• data inputs
data_fb1 = [d8 .. dO];
data_fb2 = [d17 .. d9J;
data_fb3 = [d26 .. d18];
.. counter outputs
fb1
= [q8 .. qO];
fb2
= [q17 .. q9];
fb3
= [q26 .. q18];
.. q.d2 = q & !Ioad
xoUactors fb1 := fb1 & !load;
xoUactors fb2:= fb2 & !Ioad;
xoUactors fb3:= fb3 & !load;
equations
.. Function Block 1
fb1 := (fb1 + 1) & count & !load
"count up
.. hold
# fb1 & !count & !load
# data_fb1 & load;
"load
" Function Block 2
"count up
fb2 := (fb2 + 1) & counUb2 & !load
"hold
# fb2 & !counUb2 & !load
# data_fb2 & load;
"load
.. Function Block 3
'count up
fb3 := (fb3 + 1) & counUb3 & !load
# fb3 & !counUb3 & !Ioad
"hold
"load
# data_fb3 & load;
.. Form count enables in uim
counUb2 = count & (fb1 ==511);
counUb3 = count & (fb1==511) & (fb2==511);
end
module updncntr
title 'Ioadable 8 bit loadable up/down counter
up terminal count formed in uim
down terminal count formed in macrocell
Jeffrey Goldberg
Xilinx';
updncntr device;
.. Inputs
Clk,load,up,down
dO,d1,d2,d3,d4,d5,d6,d7
• Outputs
qO,q1,q2,q3,q4,q5,q6,q7
downtc,done
• Nodes
uptc
• Variables
data
= [d7 .. dO];
count = [q7 .. qO];
xor_factors count:= count & !Ioad;
equations
count := (count + 1) & up & !down & !load
# (count -1) & !up & down & !load
# count & up & down & !load
# count & !up & !down & !load
# data & load;
" Form down terminal count in macrocell
downtc := (count == 1) & !up & down & !load
clock
# (count == 0) & up & down & !Ioad
# (count == 0) & !up & !down & !load
# (data == 0) & load;
• Form up terminal count in uim
uptc = up & (count=255);
• Send uptc off-chip
done := uptc;
end
pin istype 'reg,xor';
pin istype 'reg';
node istype 'com';
.. data inputs
" counter outputs
" q.d2 = q & !load
.. count up
" countdown
" hold
'hold
"load
.. count = 0 on next
.. holding at 0
" holding at 0
"loading 0
PLUSASM Top Level DeSign File, UPDNCNT8.PLD
PLUSASM Top Level Design File, CQUNTER1.PLD
TITLE
COUNTER1
AUTHOR
JEFFREY GOLDBERG
COMPANY
XILINX
DATE
3/2/93
INCLUDE_EON 'UPCNTR.PLD'
CHIP COUNTER1
XEPLD
INPUTPIN
LOAD COUNT DO D1 D2 D3 D4 D5 D6 D7 D8 D9 D10
D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21
D22 D23 D24 D25 D26
OUTPUTPIN
00 01 02 03 04 05 06 07 08 09 010 011 012 013
014015016017 018 019 020 021 022023024
025026
COUNT_FB2 COUNT_FB3
NODE (UIM)
FASTCLOCK CLK
EQUATIONS
XAPP 038.001
pin;
pin;
TITLE
UPDNCNT8
AUTHOR
JEFFREY GOLDBERG
COMPANY
XILINX
DATE
3/2/93
INCLUDE_EON 'UPDNCNTR.PLD'
CHIP
UPDNCNT8
XEPLD
INPUTPIN
LOAD UP DOWN DO D1 D2 D3 D4 D5 D6 D7
OUTPUTPIN
00 01 02 03 04 05 06 07 DOWNTC DONE
UPTC
NODE (UIM)
FASTCLOCK CLK
EOUATIONS
8-67
I
Example 3. 16-Bit Loadable, Bidirectional
Counter
PLUSASM Top Level Design File, ABELCNT1.PLD
ABEL Source Code
module abelcntr
title 'Ioadable 16 bit up/down counter
each 8 bit stage fits in one fb
up terminal count formed in uim
down terminal count lookahead generated in macrocell
second stage up and down count enables formed in uim
Jeffrey Goldberg
Xilinx';
abelcntr device;
, Inputs
Clk,load,up_a,down_a
pin;
pin;
dO,d1,d2,d3,d4,d5,d6,d7
pin;
d8,d9,d1 0,d11 ,d12,d13,d14,d15
, Outputs
downtc_b
pin istype 'reg';
"Nodes
a,b,c,d,e,f,g,h
node istype 'reg,xor';
node istype 'reg,xor';
i,j,k,l,m,n,o,p
node istype 'com';
up_b, down_b
node istype 'reg';
downtc_a
, data inputs
data_a = [dO .. d7);
data_b = [d8 ..d15];
counCa = [a,b,c,d,e,f,g,h];
" counter outputs
counCb = [i,j,k,l,m,n,o,p];
uptc_a = (counCa == 255);" terminal counts
uptc_b = (counCb == 255);
xocfactors counCa := counCa & !load; count.d2 = count & !load
xoUactors counCb:= counCb & !load;
equations
counl_a := (count_a + 1) & up_a & !down_a & !load
' count up
# (count_a - 1) & !up_a & down_a & !Ioad
' count down
# count_a & up_a & down_a & !load
' hold
# count_a & !up_a & !down_a & !load
' hold
# data_a & load;
'load
downtc_a := (count_a == 1) & !up_a & down_a & !load" counting
down
, holding
# (count_a == 0) & up_a & down_a & !load
counter= 0
" holding
# (count_a == 0) & !up_a & !down_a & !load
counter= 0
# (data_a == 0) & load;
'loading 0
, form count enables in uim
up_b = uptc_a & up_a;
down_b = downtc_a & down_a;
counCb:= (count_b +1) & up_b & !down_b & !load
# (counCb -1) & !up_b & down_b & !load
# counCb & up_b & down_b & !Ioad
# count_b & !up_b & !down_b & !load
# data_b & load;
downtc_b := (counCb == 1) & !up_b & down_b & !Ioad
# (counCb == 0) & up_b & down_b & !load
# (counCb == 0) & !up_b & !down_b & load
# (data_b == 0) & load;
end
XAPP 038.001
TITLE
ABELCNT1.PLO
AUTHOR
JEFFREY GOLDBERG
COMPANY
XILINX
DATE
312193
INCLUDE_EON 'ABELCNTR.PLO'
CHIP
ABELCNT1
XEPLO
INPUTPIN
LOAD UP_A OOWN_A DO 01 02 03 04 05 06 07 08
09010011 012013014015
OUTPUTPIN
OOWNTC_A
NODE
ABC 0 E F G H I J K L M N 0 P OOWNTC_A
NODE (UIM)
UP_BOOWN_B
FASTCLOCK CLK
EOUATIONS
8-68
High-Speed Custom Length
Binary Counters
Application Note By JEFFREY GOLDBERG
XAPP 040.001
Summary
This Application Note describes how to use Xilinx EPLDs for high-speed, binary counters that run at the full
rated speed of the device. These area-efficient, custom-length counters use standard 4- and 8-bit library components.
Xilinx Family
Demonstrates
XC7200IXC7300
High-Speed Counters
Introduction
voo
High-performance XC7200 binary counters are easily
designed in the XEPLD schematic-capture environment
using standard library components. When properly cascaded, these components provide counters that operate
at fMAX of the EPLD, independent of the counter length
and complexity.
ENPENT
A
The Xilinx EPLD component library contains three binary
up-counters PL161, PL163 and PLCTR8. Individual bits
of these counters are implemented in Function Blocks.
Terminal Count signals, however, are implemented in the
Universal Interconnect Matrix (UIM), shown as an AND
gate in Figure 1.
OA
6
06
C
D
OC
OD
sco
OA
06
OC
OD
SCO_O
LOADCLRA
PL163
voo
Counter Design
A
Optimizing Terminal Count
Cascaded counters can run at f MAX , if the SynchronousCarry-Out Signal (SCQ) is generated in the UIM, Figure 2.
However, since the UIM cannot drive an output directly,
the operating frequency must be reduced if SCO is
required off-the-chip in the same clock cycle. SCO must
pass through an additional Macrocell, effectively halving
the performance.
ENT
ENP
I
1
ENPENT
A
6
C
D
CLK
LOAD
CLRA
A
OA
6
06
C
D
OC
OD
I
OA
06
OC
OD
F=
06
C
D
OC
OD
SCO
LOADCLRA
SCO_l
PL163
sco
A
6
C
D
sco
PLAND8
PLFSTCLK
OAI----
061----
ocl----ODI-----
SCO
LOADCLRA
SCO_2
PL163
voo
LOAOCLRA
J
OA
6
X3194
PL161X
Figure 2. Typical Cascaded Counter
X3193
Figure 1. Typical 4-Bit Up-Counter Component
8-69
II
Customizing Counter Length
Figure 3 shows a technique that avoids this problem, .and
makes SCQ available off-chip within the fMAX cycle tIme.
A Count-Enable look-ahead circuit anticipates by one
clock period when the counter will reach its terminal
count, permitting the signal to be pip~lined. Consequently, SCQ is availble to the output dIrectly from the
flip-flop for the duration of the Terminal-Count clock
period, as shown in Figure 4.
Custom-length counters using standard 4- and 8-bit
library components often leave unsused outputs in the
design. Floating outputs are normally removed by the
XEPLD software to reclaim the unused macrocells.
Counter bits, however, have internal feedback paths that
might be needed for the correct operation of more significant bits, while their individual outputs remain unused. It
is necessary, therefore, to indicate which counter bits
may be eliminated.
Because the LSB of the least significant 4-bit counter is
inverted for the look-ahead circuit, the SCQ output of
those four bits cannot be used without slowing the
counter; instead, the piplined SCQ signal must be used. If
the counter is to be loaded without restriction, the SeQ
pipeline flip-flop must also be loaded.
The easiest way to indicate which bits may be eliminated
is to connect their outputs to VDD; the XEPLD software
then eliminates only those pins.
VOO
ENP ENT
A
B
C
o
QO~----------~
CLKON
CLR
PL74
PLAN04
sco
LOAOCLRS
PL163
CLOCK
voo
A
QA 1------,
B
QBI------~~
QC I-------t-J
o
QO 1------....1
PLAN04
SCO
LOAOCLRS
C
PL163
CLOCK
PLFSTCLK
A
QA
B
C
QB r------r~---========t~----------~O
QC
0
QO
PRE
SCO_2
Q
PLOUT
PLAN04
SCO
LOAOCLRS
PL163
CLOCK
VOO
X3195
Figure 3. Cascaded Counter with Pipelined SCO
XAPP 040.001
8-70
High-Speed Custom Length Binary Counters
CLOCK
FFD
1\
FFE
I
\
sco_O ______________________J
SCO_1
000
FFF
/
/
/
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _- J
\
\
\
X3196
Figure 4. SCQ Waveform Diagram
I
XAPP 040.001
8-71
Adders, Subtracters and
Accumulators in XC3000
XAPP 022.000
Application Note By PETER ALFKE and BERNIE NEW
Summary
This Application Note surveys the different adder techniques that are available for XC3000 designs. Examples
are shown, and a speed/size comparison is made.
Xilinx Family
Demonstrates
XC3000IXC3100
Adder Techniques
Introduction
There are many ways to implement binary adders, subtracters and accumulators in LCA devices. Various approaches
offer different trade-offs between size and speed.
Most compact, but slowest, is a bit-serial technique that
operates on one or two bits per clock cycle, generating
sum and carry. The sum is fed to an output shift register;
the carry is stored and used in the subsequent bit time.
The most compact combinatorial (parallel) adder, subtracter, or accumulator consists of cascaded CLBs. Each
CLB implements a full adder, accepting one bit of each
operand and an incoming carry. The CLB generates the
sum and an outgoing carry. A 16-bit function is completed
in 16 CLB delays, and requires 16 CLBs.
With its 5-input function generator, an XC3000 CLB can
implement additions two bits at a time. Three CLBs can
each handle two input bits of each operand and an input
carry to generate the two sum outputs and an outgoing
carry. A 16-bit function requires 24 CLBs but the operation is completed in eight CLB delays.
For faster operation, a look-ahead carry technique can be
used. Made popular by the 74181 ALU and its descendents, look-ahead carry uses Carry Propagate and Carry
Generate signals to reduce the ripple-carry delay. Using
look-ahead carry techniques in the XC3000, a 16-bit
addition can be completed in five CLB delays, using 30
CLBs.
accumulator register. Since the flip-flop set-up time
through the function generator usually matches the combinatorial propagation delay of the CLB, the set-up time
for accumulator operands is similar to the propagation
delay of the adder.
Bit-Serial Adders
The CLB architecture is ideally suited for bit-serial arithmetic. As shown in Figure 1, the two operands are serialized in shift registers, and presented, LSB first, to the
serial arithmetic unit. The sum is created as a serial bit
stream, again LSB first, that is converted to parallel data
in a third shift register. Alternatively, one of the input shift
registers may serve as the output register, with the sum
shifted in to replace the operand.
The arithmetic unit, Figure 2, comprises a 1-bit full adderl
subtracter and a carrylborrow flip-flop, and can be implemented in a Single CLB. Before commencing an operation (addition or subtraction) the carrylborrow flip-flop
must be cleared. Subsequently, sum or differences are
passed to the output shift register, while carries or borrows are stored for inclusion in the next bit of the serial
operation.
B-Operand
~
An-Ill
I
Ao
I--Serial
Arithmetic
An even faster conditional-sum algorithm was originally
described by J. Sklansky. Using this algorithm, a 16-bit
adder requires 41 CLBs, but settles in only three CLB
delays. With careful layout, the propagation delay through
such an adder can be less than 20 ns in an XC3100-3.
Note that all Xilinx adder structures can be used as accu"
mulators with no size penalty. Unlike conventional gate
arrays and similar structures, LCA devices provide dedicated flip-flops in each CLB that can be used for the
Shift Register
Unit
I
Bn-I
I---
Shift Register
t
t Bo
Sum
'----y----J
B-Operand
ADD/SUB
Figure 1. Serial Bit AdderlSubtracter
8-72
)(3119
Adders, Subtracters and Accumulators in XC3000
II
II
r~-
J)
ADD/SUB
Sj
--.£l!2-
RESET
X3120
Figure 2. Serial Arithmetic Unit
While the number of clocks required to complete the
operation equals the number of bits, the clock period can
be very small because of the shallow logic. For maximum
clock speed, the first bit of the output shift register should
be implemented in the same CLB as the arithmetic unit.
Faster bit-serial operation can be obtained by simultaneously operating on two bits, Figure 3. Odd and even
bits of each operand are loaded into separate shift registers. The arithmetic unit takes in two bits of each operand, and produces two sum bits per clock. These sum
bits are loaded into odd and even output shift registers.
Figure 4 shows the 2-bit arithmetic unit. Both sum bits are
derived in parallel, and a single carry is generated and
stored for the next cycle. This arithmetic unit permits
adders and subtracters to be constructed, but not adders/
subtracters. For adders/subtracter operation, the arithmetic unit should implement an adder; to generate A-B,
the A-operand should be inverted while loading the opeand shift register, and the sum bits should be inverted into
the output register. The carry flip-flop is cleared before
each operation, regardless of whether it is an addition or
subtraction.
While the clock rate is similar to the 1-bit scheme, only half
as many clocks are required to complete the operation.
2·Bit
Arithmetic
Unit
Ripple-carry Adders
The 1-bit serial adder, described above, can easily be
converted into a ripple-carry parallel adder. It is simply a
matter of replicating the arithmetic unit once for each bit,
removing the carry/borrow flip-flops and connecting the
carry/borrow outputs from one bit to the next, Figure 5.
The carry/borrow input of the LSB is set to zero for no
carry in an addition, and for no borrow in a subtraction.
Shift Register
Shift Register
BODO
SUM
B·Operand
X3121
At one CLB per bit, this design uses fewer CLBs than any
other parallel adder. However, this compactness is
achieved at the expense of speed; the settling time is one
CLB delay per bit. By placing the CLBs of the adder adjacent to each other, interconnect delay in the ripple path
can be minimized, or even eliminated.
Figure 3. 2-Bit Serial Adder
XAPP 022.000
8-73
II
AEVEN
BEVEN
~
li
II~U
!i
!i
1
AooD
~
II
IT>
$oDD
BoDO
!
I
1
,CF-
':?,- +
-r
I
-
- :-
I
RESET
X3125
Figure 4. 2-Bit Serial Arithmetic Unit
A faster settling time can be achieved by changing the
replicated cell from a 1-bit adder to a 2-bit adder, Figure 6.
The carry output and the more significant sum of each bitpair are functions of five inputs. Consequently, each
requires an entire CLB, increasing the CLB requirement to
1 1/2 per bit. However, the settling time is reduced to one
CLB delay per two bits, half that of the previous design.
~ =t+~~[>---t=j[:>----t-so
U~=;:~[>-r1--L.J
ADD/SUB ......
The 5-input function generators permit this design to be
used for adders and subtracters, but not for adder/subtracters. To implement an adder/subtracter, one of the
operands to an adder must be modified before being
input into the adder.
For the operation A-B, there are two choices, both of
which require additional XOR gates to invert one of the
operands while subtracting. The technique used in the
bit-serial adder and the one-bit-at-a-time adder is to invert
the A-operand into the carry logic only; the A-operand is
input to the sum logic unmodified. In this case, the carry/
borrow input is active-high for both add and subtract, and
may be tied Low if no input carry or borrow is required.
l-BitAdder
l-BitAdder
X3126
Figure 5. One-Bit-At-A-Time Ripple-Carry Adder
)(APP 022.000
8-74
Adders, Subtracters and Accumulators in XC3000
i
II~U
1
!
I
1
/I
*
,»
I
I
C:!
..,
,
lc
4
X3127
I
Figure 6. Two-Bits-At-A-Time Ripple-Carry Adder
XAPP 022.000
8-75
A more conventional approach is to invert the B-operand
into both the sum and carry logic. However, if no input
borrow or carry is required, the input must be Low during
an addition, and High during a subtraction.
Look-ahead-carry Adders
For faster operation in large adders, look-ahead carry lookahead-carry technique uses two signals, Carry Generate
and Carry Propagate (P and G), that are typically outputs
of an arithmetic block, often of four bits. Since both of
these signals do not depend on the incoming carry signal,
they can be generated immediately from input data.
As the name implies, Carry Generate is asserted if the
block creates an overflow (carry), regardless of incoming
carry. For example, in a 4-bit adder, Carry Generate is
asserted if the sum of the operand bits, excluding the
incoming carry, exceeds 15.
If the block does not generate a carry by itself, but would
generate a carry as a result of an incoming carry, Carry
Propagate must be asserted; its assertion is optional if
the block generates a carry without requiring an incoming
carry. In our 4-bit example, Carry Propagate must be
asserted when the sum, excluding the incoming carry, is
exactly 15, and may optionally be asserted when the sum
is greater.
c;
JJ~U
A;
B;
L.....
S;
~D
Si+l
Pi+2
-
JI~
L
A;+2-
Bi + 2 A;+3-
Gi + 2
"~-'1
2· Bit Look·Ahead
Adder
(As Above)
f----.- S; + 3
Pi+4
Gi + 5
B;+3-
Figure 7. Four-Bits-at-a-time Adder Block with Internal Look-Ahead Carry
XAPP 022.000
::I
f--S;+2
8-76
r
~
f-.c; + 4
X312
Adders, Subtracters and Accumulators in XC3000
In XC3000 LCA devices, look-ahead carry is most effective when used to combine two 2-bit blocks into a 4-bit
block that cascades using ripple carry, Figure 7. The 4-bit
block has a one-CLB delay from carry in to carry out, but
a two-CLB delay from carry in to the sum output of the
more significant bit-pair. The delay from the operand
inputs to the carry output is also two CLBs.
A 16-bit adder may be implemented in two ways. The
most straightforward way is to cascade four 4-bit blocks,
as shown in Figure 8(a). With this design, the carry-in-tocarry-out delay is only four CLBs, while the operand-tosum delay is six CLBs; the operand-to-carry-out and
carry-in-to-sum delays are both five CLBs The carry output is available one CLB delay before the sum, and the
carry input need not be present until one CLB delay after
the operands. The design requires 32 CLBs.
While a shorter carry delay may sometimes be desirable,
the design in Figure 8(b) is faster overall, balancing all
four delays at five CLBs. The 2-bit ripple-carry block,
described in the ripple-carry section, is used to implement
the most and least significant bit-pairs, and only 30 CLBS
are required.
Either design can be adapted to any multiple of four bits
by simply adding or subtracting 4-bit blocks in the center
of the adder. The advantage over the 2-bit ripple-carry
technique increases with the number of bits in the adder.
For even numbers of bits that are not multiples of four,
any of the designs in Figure 9 may be used. For a 14-bit
adder, the Figure 9(a) design balances all four delays at
five CLBs, and requires 25 CLBs. The Figure 9(b) and
9(c) designs each use two additional CLBs, but are one
CLB delay faster in the carry path. In the Figure 9(b)
design the carry out appears one CLB delay before the
sum, and in the Figure 9(c) design, the carry in need not
be present until one CLB delay after the operand. Agai~,
for different length adders, simply add or subtract 4-blt
blocks at the center of the adder.
COUT
COUT
4·Bil
Adder
8 12- 15 -
4-Bil
Adder
810-13
A s . l l4·Bij
_GAdder
S8-11
B8· 11 -
AS.9
-G4-Bij
Adder
8S·9
B6-9-
4·Bij
Pv..7
-G. Adder
84.7
84-7-
A2_5
4-Bij- G Adder
82-5
B2- 5 -
II
4·Bil
Adder
80-3
BO-3 -
Ao-l-
BO_1-
(b)
(8)
Figure 8. 16-Bit Adder Configurations
XAPP 022.000
2-Bil
Adder
8-77
8 0-1
X3130
~XILINX
CaUT
~'''B' ~·"B ~·"D
~-r4 ~"ll~-8- ~'D
COUT
8 12-13 -----'-+
Adder
COUT
12-13
4-8~
Adder
S10-13
8 12-13 _
S12-13
8 10-13-
As-11-
4-8it
Adder
S8-11
B&-11 -----+
Bs-e-I
A..-7-
4-8it
Adder
4-Bit
Adder
8&-9
I
S4-7
84-7-
~B
4-8~
Adder
S2-5
Adder
82-5-
S2-3
80-1 -
80-1 -
Adder
S4-7
84-7-
~D
~'B
~'B
82-3 _
S8-11
88-11-
Adder
50-1
t
50-1
50-3
80-3-
t
t
CIN
CIN
(a)
(b)
(e)
CIN
X3131
Figure 9. 14-Bit Adder Configuration
Conditional-sum Adder
I - - - -.. &l
C2
6 CLBs
2 Delays
1----8.o!
t-t--. S3
t-+-+-+ c OUT
114101A
Conditional-sum adders, originally described by J. Sklansky in the June 1960 issue of the IRE Transaction on
Electronic Computers, reduce settling time at the
expense of. much higher logic complexity. The version
described below was created by Matt Klein of Hewlett
Packard, who modified the algorithm to fit the XC3000
architecture. With careful placement and routing, the total
delay can be kept below 20 ns in an XC3100-3.
Forty-one CLBs are required, 27 of which generate one
function of up to five variables, while the remaining 14
CLBs each generate two functions of four variables. Figure 10 shows how these CLBs are connected. For more
information, please refer to the original paper and the
Xilinx Technical Bulletin Board.
Figure 10. 4-Bit Adder
XAPP 022.000
8-78
Using the Dedicated Carry
Logic in XC4000
XAPP 013.001
Application Note By BERNIE NEW
Summary
This Application Note describes the operation of the XC4000 dedicated carry logic, the standard configurations
provided for its use, and how these are combined into arithmetic functions and counters.
Xilinx Family
Demonstrates
XC4000
Dedicated Carry Logic
Introduction
XC4000-series CLBs contain dedicated, hard-wired
carry logic to both accelerate .and condense arithmetic
functions such as adders arid counters. Adders achieve
ripple-carry delays as low.as 750 ps per bit, while utilizing only half a CLB per bit. This is certainly denser than
any other approach, and in most cases, faster.
As shown in Figure 1, the carry logic shares operand
and control inputs with the function generators. The
carry outputs connect to the function generators, where
they are combined with the operands to form the sums.
A conceptual diagram of a typical addition is shown in
Figure 2.
Only the shared and .carry inputs to the function generators are predetermin~. Any function of these and the
remainingiinputs may be implemented .. For example, in
a loadable counter, the function generator may be used
to both invert the counter bit, under control of the carry
path, and multiplex a load value into the flip-flop. The H
function generator also remains available, and the CLB
flip-flops may be used in counters or accumulators.
configurations permit the dedicated carry logic to be
used without detailed knowledge of its operation, the following description is provided.
Operation of the Carry Logic
A detailed and rather complex Schematic of the dedicated carry logic is shown in Figure 4. Figure 5, however, is much simpler; it shows the same car.ry logic
once it has been configured for an addition and redundant gates have been removed.
Both bits of the carry logic operate in the same way:
First, the A and B Inputs are compared. If they are equal,
COUT is well-defined without reference to C1N • When
both inputs are zero, carry is not propagated and no
carry is generated. Consequently, COUT must be zero.
When they are both one, a carry is generated, and COUT
must also be a one. ~n either case,.COUT is equal to the
A input.
If the A and B inputs are different, the carry is propagated, and COUTis equal to C1N • COUT can, therefore, be
created by multiplexing between the A input and C1N •
This scheme is used because the multiplexers in the ripple path may be implemented using pass transistors;
these introduce the least cumulative delay into this critical path.
The ripple-carry outputs are routed between CLBs on
high-speed dedicated paths. As shown in Figure ;3, carries may be propagated either up or down a column of
CLBs. At the top and bottom of the columns whe~e there
are no CLBs above and below, the carry is propagated
to the right. This enables I)-shaped adders and counters
to be constructed when they cannot be fitted in a single
column.
Referring back to Figure 4, the various configuration
options can now be explained. XOR-gates are provided
as polarity controls for the B operands. According to a
configuration bit, B may be inverted for a subtracter, or
not inverted for an adder. Alternatively, the polarity may
be controlled by F3 (ADD/SUBTRACT) for an adder/
subtracter.
The carry logic may be configured to implement add,
subtract and add/subtract functions. Increment, decrement, increment/decrement and 2's-cornplement functions are all~o available.
The B operands may be gated out using a configuration
bit in conjunction with two AND gates sothat add and
subtract can become increment and decrement.
These functions may.be implemented using pre-defined
CLB configurations provided in XDE. The mnemonics for
these configurations, e.g., ADD-FG"Cr, describe the
arithmetic function supported, the CLB function generators used and the source of the carry input. WlJile these
To determine whether carry is propagated up or down
the column of CLBs, a multiplexer selected the carry output of the CLB below or the CLB above.
8-79
II
Using the Dedicated Carry Logic In XC4000
CARRY
LOGIC
Gil
r---
G
CARRY
;-
Y
~LJ
r-+
..
G4
~
'D
G3
r-G
} r--
G2
tp-
~[}G
0
..
o- YO
F
Gl
I>
COUTO
~
EC
rH
Hl
r--
~
r---
~[}-
F
~
CARRY
r-+
OR
0
I>
F4
G
or--- XO
EC
r--
~
F3
F
r---
F2
~N
Fl
¢'LJ 1
~
I
L.-.-
I
K
C INUP
SIR
x
1
EC
X'997
Figure 1. XC4080.Dedicated Carry Logic
XAPP 013.001
8-80
~XIUNX
CARRY LOGIC
~
~
:::=='
I
G FNGEN
))
r
II
'
,...-/
I
'
----../
F FNGEN
I
-'....-))
II'
X1998A
Figure 2. Conceptual Diagram of a Typical Addition (2 BitslCLB)
CLB
--
! 1
CLB
-- -CLB
! 1
CLB
CLB
CLB
~
CLB
~
! 1
! 1
! 1
CLB
! 1
CLB
CLB
CLB
CLB
! 1
1 1
! 1
CLB
! 1
1 i
CLB
CLB
r---
! 1
CLB
X1999A
Figure 3. Carry Propagation Paths
)(APP 013.001
If only one adder bit is to be implemented per CLB, the
selected carry may be forced to skip the first stage of
carry logic. To do this, a configuration bit is set to one and
selected to replace the output of the comparator. If the bit
is selected and set to zero, an initial value is forced into
the carry chain.
This initial value has three sources, determined by the
configuration bits. The first source is the configuration bit
used to gate out the B operand. When this bit is a one, a
2-operand function is performed, and a one at the carry
input provides add-with-carry or subtract-without-borrow
(borrow is active LOw). When the bit is a zero, a 1-operand function is performed, and the carry chain is initialized with a zero.
The second source is F3. If F3 is not selected as the
add/subtract control, it is a free input to the carry chain. If
it is used to control addition and subtraction, it provides
a zero or one such that the initial carrylborrow is unasserted in both cases.
The final source is F1. When initialization is selected, this
is a free input to the carry chain.
The second stage of the carry logic may also be skipped,
in the same way as the first stage. However, there is no
initialization function in the second stage.
8-81
II
Using the Dedicated Carry Logic in XC4000
G1-------l
G4-----t-----~r_-----~--------~
TO
FUNCTION
GENERATORS
F2 ------1-1
F1-----r-------r-------.
F4
~----_+-~==~---4-----------q
><2000
Figure 4. Detail of Dedicated Carry Logic
C i+2
A i+1 (G1) -
.....- - - - - - - '
B j (F2)
Aj (F1)
X2001A
A= B. COUT =A
Figure Sa. Effective Carry Logic for a Typical Addition
X2OO2A
Figure 5b. Effective Carry Logic for a Typical Addition
XAPP 013.001
8-82
2-0perand Functions
Adders
An adder implemented with the dedicated carry logic must
have at least two sections: a main section and an initialization section. In the main section, shown in Figure 6,
one or two bits of the adder are implemented in each
CLB, and CIN is taken from the dedicated interconnect.
Three standard CLB configurations are provided for this
purpose: ADD-FG-CI is a two-bit adder, while ADD-F-CI
and ADD-G-CI are one-bit adders with the add occurring
in For G, respectively.
CIN can only be driven by other carry logic. At the least
significant end of the adder, special attention must paid to
ensure that the carry path is initialized correctly. This is
the function of the initialization section.
The design of the carry logic does not provide for the
implementation of two adder bits in the initializing CLB.
However, a CLB may be used to initialize the carry path
and implement the LSB of the adder. The standard CLB
configurations for this are ADD-G-F1 and ADD-G-F3-. In
B3 -
_S3
B2 S2
A2
A3 -
ADD·F·CI
ADD·G·CI
ADD·FG·CI
_S2
Bl -
ADD·F-GI
ADD·G·CI
ADD·FG·CI
Sl
Al -
A2-
Bo
Bl _Sl
So
Ao-
Al -
INITiAliZATION
SECTION
1
BoAo-
c o-
ADD·G·Fl
ADD·G·F3·
f-+so
FORCE·O
FORCE·l
FORCE·Fl
FORCE·F3·
C o ·(O.l)
)(2003'
Figure 6. Main and Initialization Sections of Adder
XAPP 013.001
The use of this technique may create bussing difficulties if
other parts of the LCA device have the two LSBs implemented in the same CLB. A second approach that avoids
this problem uses a CLB to initialize the carry path without
implementing part of the adder.
Four standard CLB configurations are provided for this
purpose: FORCE-F1 and FORCE·F3- allow F1 and F3,
respectively, to be used as the carry input, while FORCED and FORCE-1 initialize the carry path with a fixed zero
or one, respectively. FORCE-D and FORCE-1 only involve
the carry logic, and all the non-carry resources of the CLB
are available for other uses.
Optionally, the adder may have a third section at the most
significant end, used to create a carry output (other than
on the dedicated interconnect) or to detect overflow. Two
situations must be considered: where the most significant
CLB contains two bits of the adder, and where it contains
onlyone.
If it contains only one bit of the adder, the standard CLB
configuration, ADD-F-CI, in Figure 7 should be used. Both
CIN and the most significant carry are available as inputs
to the G function generator. The most significant carry
may be passed through this, or XOR-ed with CIN to detect
twos-complement overflow.
MAIN
SECTION
B2-
both cases, the addition occurs in G, and the carry input is
F1 or F3, respectively.
Where both carry and overflow are required, overflow
should be generated in the same CLB as the most significant bit. The most significant carry is passed to COUT, and
an additional CLB may be configured to route it to either
the For G output. The EXAMINE-CI configuration is provided for this purpose.
If the most significant CLB contains two bits of the adder,
the situation is more complex. As shown in Figure 8, the
ADD-F-CI configuration should again be used, despite the
need for a 2-bit adder. The most significant bits of the
operands should be connected to the G1 and G4 inputs,
COUTO selected as the G2 input, and the G function generator manually programmed as if the configuration were
ADD-FG-CI. This causes the most significant sum to be
generated at the G output. However, the second stage of
carry logic will be bypassed.
An additional CLB can then be used to generate the carry
and the overflow. This should be configured as ADD-F-CI
and the most significant bits of the operands connected to
F1 and F2 in addition to the previous connection. This
causes the carry stage, bypassed in the previous CLB, to
be implemented in the first stage ofthis additional CLB.ln
this way, the necessary carries are available in the G
function generator for overflow detection as described
above.
8-83
II
Using the Dedicated Carry Logic in XC4000
I
EXAMINE-CI
~
I
'-+ CARRY OUT =c N
FUNCTION
GENERATION
cN
J
I
FUNCTION
GENERATION
-+ CARR:' OUT = C N
r+
OVERFLOW = C N.1 <±> c N
CARRY
LOGIC
ADD·F·CI
I
FUNCTION
GENERATION
-+
Figure 7. Carry"Out and Overflow Generation
The F function generator may be manually programmed
to create the most significant carry from the operand bits
and C IN • This is permissible as the operation of the carry
logic is ihdependent of the function generators.
Subtracters
Subtraction is, in most respects, identical to addition. The
subtraction may be written in terms of an addition as follows:
A- B =A+ (-B)
Multiplication by -1, or two's complementing, is performed
by logically inverting the operand and adding one. The
final form of the subtraction becomes:
A-B=A+B+1
Using CLB configurations with a SUB prefix, in place of
ADD, causes the B operand to be inverted both into the
carry logic and within the function generator. The one can
be added by forcing the carry into the adder to be High.
XAPP 013.001
8-84
An alternative interpretation is that the inversion changes
the adder into a subtracter, with the carry becoming
an active-Low borrow. Consistent with the first interpretation, the carry input must be High for borrow not to
be asserted. If the carry input is Low, the operation is
A - B-1.
Apart from usihg CLB configurations with the SUB prefix
and ensuring that carry-in has the right polarity, subtracters may be constructed in the same way as adders.
Equivalent configurations exist for all three sections of the
subtracter. The only point to remember is that, when manually configuring function generators for the most significant output or carry output, the B operand must be
inverted. The definition of overflow does not change.
One configuration that exists for subtraction, but not for
addition, is SUB-G-1. In this configuration, the least significant bit of the subtraction takes place in G with the
carry input internally forced to a one (hO borrow).
I::XILINX
CN
...
CARRY
LOGIC
FUNCTION
GENERATION
!-+ OVERFLOW =
C N_1(£) C N_1
ADD-F-CI
I
FUNCTION
GENERATION
OUT
r- CARRY
= A N_1 B N-l +A N_1 C N_1
+B N_1 C N_1
C N_1
FUNCTION
GENERATION
CARRY
LOGIC
i-+ S N-l
= A N_1(£) B N_1(£) C N_1
ADD-F-CI
I
FUNCTION
GENERATION
C N_2
-+
X2005
Figure 8. Carry-Out and Overflow Generation with Duplicated MSB
AdderlSubtracters
The adder may be converted to an adder/subtracter by
making the inversion of the B operand programmable.
This is accomplished using CLB configurations with an
ADDSUB prefix.
The ADD/SUBTRACT control is connected to F3, and
controls the operation of both the carry logic and the
F function generator. If the configuration uses the G function generator, ADD/SUBTRACT must also be connected
toG3.
The carry input to the adder/subtracter must be determined by the operation being performed. When an add is
XAPP 013.001
8-85
in progress, it must be Low for a carry not to be asserted,
and it must be High for a borrow not to be asserted during
a subtraction.
This will generally preclude the use of FORCE-O and
FORCE-1 to initialize the carry chain. Otherwise, the
adder/subtracter is constructed in the same way as the
adder, but using CLB configurations with the ADDSUB
prefix.
As in the subtracter, the programmable operand inversion
must be remembered in any function generators that are
manually configured
I
Using the Dedicated Carry Logic In XC4000
1-0perand Functions
Counters
Incrementers
Essentially, an incrementer is an adder with one operand
zero, and the carry input asserted. Consequently, incrementers are constructed in the same way as adders, but
using CLB configurations with an INC prefix. These gate
out the B operand.
Up Counters
An up counter is constructed by combining an incrementer with a register, as shown in Figure 9. Typically, the
register in the same CLBs as the incrementer is used,
and the sum outputs should be routed to this register. The
output of the register is fed back as the input to the incrementer. Each clock, the register is loaded with a value
one greater than its previous value.
The carry input should be High to increment the A operand, and Low to pass it unchanged. Alternatively, it may
be fixed High for permanent incrementation. This may be
accomplished using CLB configurations equivalent to
those used to initialize adders. In addition, INC-G-1 and
INC.. FG-1 allow the carry chain to be iniiiaiized wiih the
carry asserted, along with one or two bits of the function.
Any incrementer may be used. If it has the ability to increment or pass the operand, this feature may be used as a
count enable.
As shown in Figure 10, counters may easily be made
loadable by adding a multiplexer into the function generators. This multiplexer selects between the incrementer
output and the value to be loaded as the source for the
register.
Decrementers
These are subtracters with the B operand zero and a borrow asserted. CLB configurations with a DEC prefix gate
out the B operand before it is inverted. The carry input
should be Low to decrement the A operand, and High to
pass it.
Down Counters
Down counters are constructed in the same way as
up counters, but using decrementers in place of incrementers.
Alternatively, a fixed Low may be used. DEC-G-O and
DEC-FG-O provide this, along with one or two bits of the
function. FORCE-O may also be used.
Incrementer/Decrementers
Not surprisingly, these are constructed in the same way
as adder/subtracters, but using cells with an INCDEC
prefix that gate out the B operand. When increment is
selected, the carry input should be High to increment or
Low to pass. When decrement is selected, the carry
should be Low to decrement or High to pass. INCDEC~
FG-O implements two least significant bits of the incrementer/decrementer with the carry or borrow input permanently asserted.
2's Complementers
The traditional two's-complement procedure, invert-andadd-one, is not appropriate for use with the dedicated
carry logic. In the increment configuration, the A operand
cannot be inverted at the input to the carry logic, and
using a subtracter for 0 - B consumes unnecessary
resources routing the zero operand.
The answer it to replace invert-and-increment with decrement-and-invert, which produces the same result. A
conventional decrementer is constructed, and an additional output inversion is programmed into the function
generators.
Up/Down Counters
Incrementer/decrementers are used for up/down
counters. The only significant difference comes in the
loadable counter. Because the INC/DEC control is an
C OUT
f-- 0
INCREMENT
I-- 0
Q
~
X2006A
Figure 9. Typical Counter CLB
8-86
Q i+ 1
~
The use of a function generator input allows this inversion
to become programmable. In conjunction with control of
the carry input, this programmable inversion may be used
to twos complement a number or pass it, as required.
XAPP 013.001
Q
o
I+l--+-+---+---+-----lr-l}-V
0
>
INCREMENT
X2007A
Figure 10. Typical Loadable Counter CLB
input to the function generators, there are not enough
inputs available for the load function. One CLB must be
used for each bit of the counter, and there are several
ways in which this can be organized.
One possibility is to use a CLB configuration that only
implements one bit of the incrementer/decrementer function, as shown in Figure 11. The H function generator can
then be used as the load multiplexer. The H1 input acts as
the Parallel Enable, and the value to be loaded is passed
through the second function generator.
A better choice is to construct the incrementer and decrementer separately in two columns of CLBs with two bits
per CLB, as shown in Figure 12. The decrementer is connected as a conventional loadable down counter. In the
incrementer, the function generators are modified with a
multiplexer, as is it were to be a loadable up-counter.
However, the register is not connected, and data is not
fed back.
Instead, the input to the incrementer is taken from the output of the down counter, and the incrementer output is
routed to what would have been the down-counter load
input. The value to be loaded is input to the multiplexer
attached to the incrementer.
XAPP 013.001
8-87
The load control of the down counter becomes the up/
down control, selecting the output of either the incrementer or the decrementer. Data is loaded by replacing
the incrementer output with the value to be loaded, and
selecting count up. An external gate may be required to
force the up/down control.
This second approach has the advantage that its layout is
compatible with other functions that implement two bits
per CLB. More importantly, however, it is faster. The incremental carry delay is incurred per CLB, not per bit, and
implementing two bits per CLB halves the number of carry
delays. Also, the set-up time on the up/down control is
much shorter. The up/down control need only select the
output of the incrementer or decrementer, instead of
selecting the increment or decrement function before
carrylborrow propagation can begin. Both the incrementer
and decrementer operate in parallel, starting immediately
after the clock.
Alternatively, an incrementer/decrementer may be implemented in one column of CLBs, with the register and. load
multiplexers implemented in a second column. A countenable multiplexer can be built into the same function
generator as the load multiplexer. If this is placed logically
in front of the load multiplexer, the load control takes precedence over the Count Enable.
I
Using the Dedicated Carry Logic in XC4000
COUT
PE
[H1
~
G
OJ
UP/DOWN
r
F
- t-
~
H
D
Q
~
INC/DEC
X2008A
Figure 11. Typical UplDown Counter CLB
This scheme eliminates the additional gating required to
ensure that the counter is enabled and counting up during
a load. The Load and Count Enable controls are both
fast, but the set-up time for the up/down control is similar
to the carry-propagation delay.
Timing Analysis
Typically, the critical delay is from the carry input or operand LSB to the output MSB, carry output or overflow flag.
As shown in Figure 13, this delay has three parts: The
delay onto the carry chain from the input, the delay from
the carry chain to the output and the delay of the intervening CLBs.
Individual CLBs are configured using the EditBlk command. Within the Block Editor, the ConfigCarry command
provides a list of the standard CLB carry configurations.
Once a selection is made, the mnemonic for the configuration appears in the Block Editor screen.
If part of the function is performed in the CLB that initializes the carry chain, the delay onto the chain is the
greater of the operand-input-to-COUT (Topcy) and the initialization-input-to-C OUT (TINCY) delays. If a CLB is used
for initialization only, separate delays must be calculated
from the least significant operand input and the initialization input, taking into account the different number of
intervening CLBs.
The output delay (TsuM> is from CIN to the output. Each
intervening CLB introduces a T BYP delay.
To calculate the minimum clock period in a counter, the
clock-to-output delay and a routing delay must be added
to the operand input delay. Typically in a -5 part, this routing delay is 1.5 ns; but this must be verified by simulation
after the implementation is complete. The output delay
must be replaced with the equivalent set-up time, and the
intervening CLBs taken into account, as in the basic
delay calculation.
XAPP 013.001
Configuring the Carry Logic
The dedicated carry logic is accessed through the use of
hard macros. These are blocks of CLBs that are configured and routed in the XACT Design Editor (XDE), and
then converted to macros using HMGEN. When the symbol for the macro is used in a schematic, the relative
placement and configuration of the CLBs are retained.
8-88
The selection causes the F4, G2 and G3 tags to be set
according to the chosen configuration, and the appropriate functions are entered into the F and G function generators. If the tags or function generators had been
previously defined, they are not overwritten. If the settings
values are required, any previous settings must be
cleared before selecting the CLB configuration.
The direction of the carry propagation, up or down, must
be selected by the COIR tag. In addition, check that the
carry inputs and outputs are routed appropriately by the
CIN and COUT tags.
If the standard configuration needs to be modified, the
changes are simply entered on the Block Editor screen.
Once editing of the block is complete, a carry route must
be added between adjacent CLBs.
BOUT
[
I
I
"
INCREMENT
~[J-'
-[}-r
I
-}L
I
~
DECREMENT
i
a
~[}-,
a
~
PE
UP/DOWN
Figure 12. UplDown Counter with Separate Incrementer and Decrementer
II
~
CARRv-+fTl.
IN
T'NeY
TII--lHo
o
o
o
VALID
\-------~~-poP
ROY
X1976
Figure 2. Detail of Synchronous FIFO
quently, data is always being shifted in when the FIFO is
ready. The function of PUSH is simply to identify the data
being shifted in as valid, so that it is retained in the FIFO.
In the diagram, the CLB clock enable (CE) is used as shift
enable. When combining pairs of flip-flops into CLBs, CE
can only be used if adjacent bits oOhe same register are
combined. If it is more convenient, bits of equal weight
from adjacent registers may be combined. In this case,
function generators must be used to implement shift
enable. This entails a simple 2-input multiplexer that
selects input data when shift is enabled, and selects
existing data from the flip-flop when it is not enabled.
The speed of the FIFO is determined by the ripple-OR
time of the shift-control logic, and the distribution and setup times of the shift-enable signals. This defines the setup time for the POP command. The settling time for the
shift-control logic is one CLB delay per two words of FIFO
depth. Longlines shOUld be used to distribute the shiftenable signals.
Asynchronous Input Stage
Asynchronous data may be entered into the FIFO using
the circuit shown in Figure 3. An additional input holding
XAPP 005.002
8-97
register is provided to facilitate edge-triggered input. If
appropriate, this can be implemented in lOB registers.
Oata may only be entered when the ROY flag signals that
the input register is available to accept it. The input clock
(PUSH) also asserts the PUSH INP signal which removes
the ROY flag. On the next internal clock, PUSH INT is
asserted and PUSH INP cleared. When shift is enabled
into the first register of the FIFO, data is transferred out of
the holding register, PUSH INT is cleared and ROY is reasserted.
If data is being input from a synchronous system that is
not synchronized to the FIFO internal clock, the circuit
shown in Figure 4 should be used. Again, an input hOlding
register is provided. However, it is enabled by PUSH,
instead of being clocked by it (an lOB register cannot be
used). As before, PUSH causes PUSH INP to be
asserted. Feedback around the flip-flop sustains PUSH
INP until it is recognized by the internal clock, permitting
the PUSH command to be removed after the one input
clock.
The entry of data into the FIFO proceeds as in the previous scheme. ROY· is registered to synchronize it to the
input clock. The negative clock edge is used for this, so
I
INTCLK
SEO
INPUT CLOCK
0 1 - - - - - - - - - - - - - - - + - + -... D
°O--+--1D
PUSH INP
0
--+--1 D
INPUT
CLOCK
(PUSH)
INTCLK
SE 1
o-r----,
~~
r----<'
-.-+-1>
RD
~>
CE
I
CE
I
PUSH
o--+-+-+I D
NT
a D O I-I-1
r--
0 1 - - - -.. 01 0
01----+-+-+1 D
01-..--+---+-1 D
01--.--
VALID 1
I
>-~
_I'.
V
CE
I
~>
CE
I
L-----~_+~~----_r~-+-----~r_-INTCLK
~~I
RDY·
._.
-.--~
X1977
Figure 3. Asynchronous Input Stage
that, if the FIFO is sufficiently fast and is not full, the ROY
flag will remain set, and data can be entered on successive input clocks. If the positive clock edge had been
used, ROY would always be Low for at least one clock. At
best, this would only permit data to be entered on alternate input clocks, no matter how slow.
Asynchronous Output Stage
The circuit shown in Figure 5 should be used, if an asynchronous output is required. For an immediate, edge-triggered output, a holding register is provided, which is
clocked by the output clock (POP). lOB flip-flops may be
used for this register.
The output register may only be clocked when the ROY
flag signals that data is available in the last register of the
the FIFO. The output clock causes data to be transferred
out of the FIFO, and asserts POP OUT. This removes the
ROY flag. On the next internal clock, POP INT is asserted
and POP OUT is cleared. POP INT is held, and the FIFO
shifts, until the last register again contains valid data. It is
then cleared, and the ROY flag is re-asserted.
If data is being output to a synchronous system that is not
synchronized to the FIFO internal clock, the circuit shown
in Figure 6 should be used. The output register, which
cannot be implemented in lOBs, is enabled by POP. POP
also causes POP OUT to be asserted. Feedback around
XAPP 005.002
8-98
the register sustains POP OUT until it is recognized by
the internal clock, even if POP is removed and another
output clock occurs.
The transfer of data out of the FIFO proceeds as in the
previous scheme. ROY is synchronized with the negative
edge of the output clock. As a result, data can be output
on successive clocks if the FIFO is fast enough and data
is available.
Implementation Notes
The obvious organization for the FIFO is as a rectangular
array of CLBs, with the control logic in the bottom row.
The flip-flops may be partitioned into CLBs in two ways. If
adjacent bits of the same word are combined, the result is
a FIFO that is twice as wide as it is tall (assuming equal
numbers of bits and words).
Alternatively, two bits of equal rank from adjacent words
may be combined. This gives a FIFO that is twice as tall
as it is wide and is potentially faster. The critical path
through the control logic passes through a chain of half as
many gates as there are words. The tall, narrow organization allows these gates to be implemented in adjacent
CLBs with zero-delay direct interconnects.
Both forms of the FIFO are available as macros, using
CLBMAPs.
Register-Based FIFO
INT
CLK
PUSH
INT
SEo CLK
a
0
f-~
-D-
~>
CE
a
I-- 0
a
0
J
PUSH
INT
SE 1 CLK
'----<
"""'' '0-
f->
CE
a
0
CE
J
I
PUSH
INT
0-
0
a
0
0 - ..... VALID 1
0
,-cl
f->
-~
:....
RO
f->
I
I
+d
a
ROY
f-~
CE
I
INTCLK
-<1=f
~
<
~
CE
SE:!
INPUT
CLK
X1978
Figure 4. Asynchronous Input Stage (From Synchronous System)
INT
CLK
INT
CLK
SEN•2
0
OUTPUT
CLIK
SEN•2
a
0
~>
~I>
CE
I
>->
Q
0
a
~~
CE
I
at-
0
a
0
CE
I
0-
0
~I>
POPINT
CE
~
I
INTCLIK
.~
-<1=f
-c~
ROY
I
0----<
f-Q
D-
o
0-1
1:>-
<-
RO
<-
OUTPUT
CLK
(POP)
I
X3204
Figure 5. Asynchronous Output Stage
XAPP 005.002
8-99
~XILINX
INT
ClK
SE N-2
INT
OUTPUT
ClK
POP
ClK
SE N_1
... Oo
~---------+---~D
O~----f-
CE
... RDY
I
}O-,t--------I 0
,------LJ.
VALID N-3 ---1i-1--I
O~----f-
~~
-
'-----'
,',---I
._
~POP
'-0
SEN_2 -~---{
RO
01
]
WE
00
01
WE
Figure 5. Example of a Marginal WE Generation Circuit
RAM Array
Counter
00t-:::[)-~-1
011-
WE
ClK
00
01
WE'
WE
X3099
Figure 6. Example of a Glitch-Free WE Generation Circuit
XAPP 031.000
8-104
matching is not possible in an FPGA environment, where
the possibility of glitches is increased by the high speed
of the logic functions and the relatively long routing
delays. Figure 6 shows a better, glitch-free circuit.
duplication of the address circuitry to drive separate
segments of the RAM array.
• RAM modules which need to run at speed benefit
greatly from manual placement. It pays to create a trial
design that only implements the RAM and its control
logic. This small design can be quickly placed and
routed, and then optimized in the XACT Design Editor
(XDE). The optimized placement can the be incorporated into the main design using location constraints.
Alternatively, the RAM portion can be converted into a
hard macro, thus preserving its relative placement.
In general, some valid techniques used in a discrete
design can create marginal designs in the high-speed
LCA environment. Avoid asynchronous circuits like the
plague. With a little thought, most things that are be done
asynchronously can be better done synchronously. If necessary, use small Gray-code or Johnson counters that
can be decoded in a hazard-free manner. In a Xilinx
FPGA, such counters are as easy to implement as binary
counters.
Creating a RAM Array
The XC4000 RAM is accessed as 16 x 1 and 32 x 1 primitives. In RAM applications requiring less than 16 words,
16 x 1 modules must be used with any unused addresses
tied to ground or Vee. 16 x nand 32 x n arrays can easily
be created by connecting several of these primitives in
parallel with common address signals.
Routing Delay Issues
FPGA routing delays can cause a circuit that works at
speed on paper not to operate under worst-case conditions. In this situation, worst-case conditions must be
interpreted as slow operation, fast operation, or any combination of these that causes a malfunction. The following
issues should be considered.
For depths greater than 32 words, a RAM array must be
constructed as shown in Figure 7. In this example, two
32 x 1 primitives are combined to implement a 64 x 1
RAM. The most significant address bit is used to select
between the primitives, while the remaining address bits
are common to both. During a read cycle, selection
between the primitives involves multiplexing the output
data. For a write cycle, the data is common to both primitives, and the WE pulse is gated to enter the data into
only one.
• The WE signal is skewed in time by the routing delay introduced by its net. Make sure that the circuitry used to control the address and data signals takes this into account.
The tAH and tDH requirements must not be violated.
• Compared to small RAM arrays, large RAM arrays
have higher fan-out address lines with longer routing
delays. Consequently, for a given speed, the addressgeneration circuits have less time in which to operate.
Generally, large, fast RAM arrays require more ingenious control circuitry, and may necessitate partial
TBUFs could be used to create the output multiplexer.
However, at least half of a horizontal Longline would be
RAM32x1
DATA IN
DI
A[4:0]
A4
5
DO
A3
A2
A1
AO
WE
DATA OUT
AS
I
RAM32x1
DI
DO
A4
A3
A2
A1
AD
WE--~--~L-r--------i
WE
'------'
Figure 7. 64 x 1 RAM Array
XAPP 031.000
8-105
X3100
Using the XC4000 RAM Capability
RAM32xl
DATA IN - - . . . - I
1-------101
DO
A4
A3
A2.
A1
AD
WE
5
A[4:D] ---1----,;<------11--1
1 - - - DATA OUT
s
RAM 32 x 1
I---+-r-+-;DI
DO
A4
s
A3
A2.
Al
AD
WE----+---+--4-;WE
~-
____-1___
~~
___-
--_-J
__
)(3101
Figure 8. Alternative 64li: 1 RAM Array
consumed for each bit of RAM width, and TBUFs are
slower than small logic-based multiplexers. Consequently, the use of TBUFs is only recommended for very
deep RAM arrays.
Gating the WE pulse increases the delay in the WE path.
This delay is not usually a problem in slower RAM applications; but, as the write-cycle time decreases, the additional delay can become unacceptable.
Figure 8 shows an alternative technique. While new data is
being written into the selected primitive, the existing data is
re-written into the non-selected RAM primitive. This
technique introduces additional delay into the data input
path, but maintains the minimum delay in the WE path,
which is often the critical path. The circuit choice depends
on the timing requirements of the specific system.
These expansion techniques are directly analogous to
depth expansion in discrete RAMs. The only differences
are the explicit output multiplexer, which would be implemented using 3-state busses in the discrete case, and the
Write Enable gating, which is integrated into discrete
RAMs.
Emulating SRAM with Bidirectional Data Pins
Some commercially available discrete SRAMs have a
single Data InpuVOutput pin. This type of SRAM can be
emulated in the XC4000 using the circuits shown in
Figure 9. In Figure 9a, the multiplexing is performed
using lOB elements; the signals inside the FPGA are
unidirectional.
XAPP 031.000
In Figure 9b, the bidirectional data line is extended into
the FPGA and the RAM uses TBUFs to drive the data
line. This circuit is appropriate where multiple data
sources are required to read/drive the data line at differenttimes.
Note that in Xilinx FPGAs, the 3-state buffers (TBUF,
OBUFT) have enable signals that are active-High 3-state
controls, i.e., when a logic 1 is applied, the output of the
buffer is high Impedance, and when a logic 0 is applied,
the output is active. The T pins can be viewed as activeLow Output Enables.
Recommended Control Logic Schemes
There are many ways to generate the WE signal for the
XC4000 RAM. The choice is design dependent, and a
major factor is. whether the design is synchronous or
asynchronous. In an asynchronous deSign, the WE pulse
is generated from a signal originating outside the FPGA
that may be gated with internally generated signals. In a
synchronous deSign, the WE pulse is generated by logic
that is completely within the FPGA.
Asynchronous Control Logic
In the asynchronous case, each design will be different,
and depend on the extemal signals that are available.
Consequently, it is impossible to make firm recommendations. However, the following discussion should illustrate
some basic techniques.
Asynchronous designs generally take the form shown in
Figure 10. Extemal signals from an interface, usually a
8-106
AD
RAM32xl
a
D
IBUF
A4
A3
A2
AI
AO
a
WE
WE
RD
RAM32xl
D
IBUF
TBUF
AO
AI
A2
A3
A4
b
WE
Data Line to
Other Bus
a
TBUF
Drivers
WE
X3102
Figure 9. Methods of Emulating a RAM that has Bidirectional Data Pins
microprocessor bus or a system backplane, are used to
generate the address, control and data to the RAM. Typically, the designer is required to combine input signals to
control the RAM. While bus transfers are often fast, the
read cycle is usually not a problem; it is the write cycle
that is difficult.
The biggest problems facing the designer are the following.
o
o
How to create a WE signal that, at the same time, is
compatible with the data and address timing of the system bus and meets the set-up and hold-time requirements of the RAM.
How to create such a WE signal with no glitches.
Solving these problems requires creativity. The following
example describes how to solve a typical problem.
Figure 11 shows the system timing for the read and write
cycles of a typical microprocessor. As mentioned previously, the design of the read-cycle control logic is rarely a
problem, since the necessary interface signals are usually present early in the cycle. All that needs to be generated is a subset of the address for the RAM, and an
enable signal to the output drivers. This can be done
using the circuit shown in Figure 12.
XAPP 031.000
The XC4000 wide decoders can be used to generate an
address valid signal that can be gated with other interface
control signals. The resulting signal indicates whether the
RAM is being addressed during the current cycle. If the
current bus cycle is a read, this signal should be registered by a flip-flop on the rising edge of T2. The resulting
Qualified Read signal is used to enable the output buffers. The portion of the microprocessor address routed to
the RAM depends on the size of the RAM.
The write-cycle timing can be generated similarly to the
read-cycle timing, except that the flip-flop generating the
Qualified Write signal would have its CE pin connected
directly to the W/R# signal. This is shown in Figure 13,
which also shows the timing of the Qualified Write signal.
The write-cycle timing is more difficult that the read-cycle
timing, because both the address and data hold times
must be met, even with worst-case timing. It may be necessary to register the address or data to extend the time
during which they are stable, Figure 14. The falling edge
of the ADS# signal is used to register the address lines
driving the RAM. Note that the address lines used in the
control logic gating should not be registered. This would
make it difficult to meet the set-up times of the flip-flops
that generate the Qualified Read and Qualified Write
signals.
8-107
II
Using the XC4000 RAM Capability
n
System
Control
Address
WE
RAM Array
Data In
n
Sy~:~ ---n-r-----i
Data Out
n
'-------'
X3103
Figure 10. General Form of an Asynchronous RAM Interface
T1
Tl
T2
ClK
CLK
\\-_-+-----J/
ADSII
Address
MlIOIl
D/CII
BE3-0II
\\-_-+-----J/
ADSII
Address
MlIOIl
D/CII
BE3-0II
~
W/R#
W/RII"
DATA
T2
--+-------------+---------~
(
DATA
Read Cycle
Write Cycle
Figure 11. Typical Microprocessor Read and Write Cycles
Address
-7"---....,
ADSII----f
MlIOII-----"-'
D/CII
n
DE3-0II
Qualified
Read
Address
/
W/RII
----C><>--....,..---i
RAM Array
ClK----------------~
System
Data
--------r-------------I D
POS
a
NEG
PHO
PHI
PH2
CLK
--------+--I»----...J
PH3
L...----_NEG
X3110
Figure 15. Glitch-Free Sequencer
XAPP 031.000
8-110
The important events are as follows.
ClK
1. A shift cycle is initiated on the rising edge of the 2 X ClK
by asserting Enable High. At this time, the pulse
sequencer is triggered, the input data is captured into a
register and the address counter is incremented. This
action may occur on any rising clock edge, but is ignored
on the rising edge immediately following a trigger.
ENABLE
pos
2. The data written to the RAM 64 clocks previously is
read, and is captured into an output register on the rising
clock edge that initiates PH2. Both data and address
have had a full 2XClK period to set up. The 0 ns hold
time requirement of the ClB is guaranteed, since the
data is stable until the WE pulse.
!----+--+--~~Il
3. New data is entered into the RAM by the WE pulse,
which is PH2 delayed by logic and routing.
!----'---i---!I
4. Address and data cannot change until the end of PH3.
At least half a period of the 2XClK is available for to
remove of WE and satisfy the address and data holdtime requirements.
X3112
Figure 17. Waveforms for the Glitch-Free Sequencer
Valid
Data
Valid
Data
Valid
Data
ENABLE
2xClK
PHO
PH1
PH2
PH3
RAOO [4:0]
i
~~~~~~~~~
I
!
~~~~
vi'--;...--;....~V\'--f--+--~
----H
~~~v-r~+-+-+-+-+-+-+-~!-\~~~v-}~-,~--!(
~~+-~V~+-~~+-+-~~~~~i~V-\
~~~_
-+_~_+-~_-r_~____O_E~~_~_~~X~___+P~Fh~_-¥~~~_~._10~h-r_~iX~+-1~1h~:_
~~--!!r-\~~+-~+-~~__~Ir-\~~~~+-~+-+-
ir-lI\~~____~!·.".r
.
~I ! ! DC
~--+-~--+--+--+--+--+--+--~-+--~-r--~~--~-¥I
X ... I .
~:
--;---+--- ~+---il--,Cl~i-o-ata";'w-rit -ej-~I-O-O+~h----+--+_-li
64 Cycles Previously
i
!
olta Written 100F
h
64 Cycles Previously
i
o~la
Written 10
10h
64 Cycles Previously
X3108
Figure 18. Waveform for Several Shift Cycles of the 64-Bit Shift Register
XAPP 031.000
8-111
II
Using the XC4000 RAM Capability
As can be seen, the pulse circuit allows the orderly
sequencing of the write cycle spacing out the events so
that timing requirements can be satisfied. This type of
sequencing is the preferred technique in synchronous
RAM applications. Its advantage is that it is bulletproof; its
disadvantage is that it requires a clock that is twice as
fast as the cycle time.
The clock does not necessarily need a 50% duty cycle. In
the shift-register example, the only duty-cycle restrictions
are that the clock High time must generate an adequate
WE pulse, and the clock Low time must allow the WE
pulse to be removed with sufficient margin to meet the
necessary hold times. Within these restrictions, an asymmetrical clock might even be beneficial, providing faster
operation.
In previous sections, this circuit would have been referred
to as a glitch generator, but here it is a pulse generator;
that is why it is the last resort!
Using. this circuit, the only signal that is needed to perform a write to the RAM is a 1x clock at the RAM cycle
rate. The leading edge of this clock sets the data and
address, while the trailing edge triggers the WE pulse.
The restrictions on the clock are that the address and
data must set up during the first half of the clock. The
second half of the clock must guarantee the WE pulse
time to complete, at the RAM, with adequate margin to
meet the address and data hold-time requirements.
The Last Resort.
This last solution to the problem is not a nice one, but it
works - most of the time. While its operation is not guaranteed by device characterization, the solution almost
invariably works at room temperature, with nominal
power supplies on typical parts. However, the probability
of failure increases as the restrictions are relaxed.
The use of this method in a production design is particularly riSky. While it will probably work reliably, occasional
failures must be expected due to parts that are close to
their specification limit. Additionally, to avoid field failures,
every unit should be tested over the full range of temperature and voltage that it is expected to encounter.
The pu!se-generater circuit is a self-resetting flip-ffop. The
worst-case loop time is >17 ns on an XC4000-5 device
(2 x tllO) + tRIO + Routing). On the same device, the WE
pulse requirement of the RAM is 4 ns minimum. Within a
single FPGA, the speed of different logic resources tracks
reasonably well (to within 70%). Consequently, the worstcase scenario is the WE pulse width decreasing to 12 ns,
while the RAM continues to require a 4 ns pulse. In a
faster device, with higher Vee or at a lower temperature,
the width of the WE pulse will decrease; but so will the
WE requirement of the RAM. As a result, the pulse width
should never fail to satisfy the WE requirement.
For more reliable timing, this circuit could be converted to
a hard macro in a single CLB. It could then be instantiated in the design as required.
Again, this is the last resort. Use it at your own risk!
Contrary to the advice given earlier, this solution uses an
asynchronous circuit to generate a WE pulse, Figure 19.
vee
FORD
TRIGGER
'----I 0
CE
Q
t-------4~__i;OO_--__,
INV
------------------~c
RO
TEMP02
TEMP01
INV
FMAP
FMAP
WE_PULSE
---
--
11
12
13
14
TEMP01
0
-
Figure 19. Pulse Generator
XAPP 031.000
-11
-- 12
13
14
8-112
TEMP02
0
X3109
64 x n-Bit RAM-Based FIFO
XAPP 006.002
~
Application Note By BERNIE NEW AND WOLFGANG HOFLICH
Summary
For a 64 x 8-bit FIFO, 256 bits of RAM are implemented within an LCA device. An innovative address counter
scheme, using the high-performance dedicated carry logic, converts this into a simple FIFO. The address controller hard macro available for this design may be used for 32 or 64-word FIFOs of any width.
Specifications
Xilinx Family
FIFO size
Maximum Clock Rate (-5)
Maximum PUSH Rate
Maximum POP Rate
64 x 8 Bits
50 MHz
12.5 MHz
12.5 MHz
Number of CLBs
30
XC4000
Demonstrates
Internal RAM
Introduction
While small FIFOs may be constructed in FPGAs using
registers, larger FIFOs are only practical when emulated
with RAM. The user-accessible RAMs in the XC4000series LCA devices make them well suited for this application. The dedicated carry logic is also beneficial, simplifying and compacting the design of the control
counters.
Operating Description
The FIFO design, shown in Figure 1, uses a 64 x 8-bit
RAM implemented in two banks of eight CLBs. An additional five CLBs are used for the distribution of write
enable, the multiplexing of the outputs and the RAM output register. RAM cycles are dedicated alternately to
read and write so that data can be PUSHed or POPed
every two RAM cycles.
Conventional address counters are not used. Instead,
two registers, connected as a recirculating shift register,
are used to store the read and write addresses. Every
RAM cycle, the addresses change places, alternately
presenting the read and write address to the RAM.
Whenever an active read (POP) or write (PUSH)
cycle occurs, the address is incremented while being
recirculated.
The incrementer uses the dedicated carry logiC and is
very straightforward. Three CLBs are configured
together to provide a hard-wired carry path. The carry
outputs from this connect directly to the function generators in the CLBs that are used to create the sums. The
function generators are powerful enough also to provide
the selection function between the incremented and
unincremented values. The flip-flops in the three CLBs
provide the first register.
~ Supporting design files are available on the Xilinx
Technical Bulletin Board under the name XAPPOO6V (Viewlogic)
This approach has several advantages. While the dedicated carry logic embedded in the CLBs of the second
register could be used without cost, converting this register into a counter would also tie up the function generators that might otherwise be used for the comparator.
Additional CLB resources would also be consumed multiplexing the addresses. The major benefit, however, is
time. Read and write addresses are available to the
RAM immediately following the clock, without additional
multiplexing delay.
A simple toggling flip-flop is used to allocate read and
write cycles. Following power-up or a reset, both
counters contain the same value. At this time, they can
arbitrarily be defined as read and write addresses. Subsequently, the recirculating shift register operates in synchronism with the flip-flop.
During the read and write cycles, POP and PUSH,
respectively, are used to determine whether the recirculating address is incremented. In an active write cycle, a
write-enable pulse is generated that enters data into the
RAM. In an active read cycle, the RAM output register is
enabled, and new data. becomes available at the end of
the cycle.
An identity comparator detects when read and write
addresses are equal, signaling that the FIFO is either full
or empty. This ambiguity is resolved by reference to the
last operation performed by the FIFO. Following a PUSH
operation, the FIFO cannot be empty, and equal
addresses must imply that the FIFO is full. Conversely,
following a POP, equality must imply emptiness. A flipflop is used to store the type of operation last performed.
Its output routes the identity signal to the FULL and
EMPTY flags, as appropriate.
8-113
II
64 x n-Bit RAM-Based FIFO
6
DATA IN
8
REG
1+....- -...1ADDRS
INC
RAM
64x8
EC
WE
25 MHz EN
r-------------~--~25MHzEN
Q
Q
R
R
EMPTY
D
FULL
Q
EC
25 MHz EN
EC
o
WRITE = 1
READ=O
L--+---+----______________--<3207
Figure 2. Two PUSH/POP Synchronization Circuits
If a high-speed clock cannot be made available, it is possible to use a clock at the RAM cycle rate. In this case, the
Write Enable pulse is generated using an asynchronous
circuit. While this approach is believed to be reliable, it
cannot be rigorously proven to operate under worst-case
conditions. See page 8-112 The Last Resort, in XAPP031
Using the XC4000 RAM Capabilty.
Implementation Notes
The address generation portion of the FIFO is available
as a hard macro. This may be combined, at the schematic
level, with any width of RAM and output register. An additional control input to the hard macro modifies its operation for use in a 32-word FIFO. When used in a 32-word
FIFO the MSB of the address should be ignored.
II
XAPP 006.002
8-115
Multiplexers and Barrel
Shifters in XC3000IXC3100
XAPP 026.001
Application Note By PETER ALFKE and BERNIE NEW
Summary
This Application Note provides guidance for implementing high performance multiplexers and barrel shifters in
XC3000 LCA devices.
Xilinx Family
XC3000IXC3100
Introduction
Since the function generator in the XC3000 series CLB
has only five inputs, it cannot directly implement a fourinput mUltiplexer, which requires four data inputs and two
select inputs. The CLB does, however, have the logic
capability to implement a 4-input multiplexer.
This applications shows how to access the full logic capability of the CLB for 4-input multiplexers. It also shows
how best to implement larger multiplexers and barrel
shifters.
Multiplexers
Four-Input Multiplexer
CLB function generators have a base-FGM operating
mode that permits certain functions of more than five variables to be implemented. The restriction on the function
is that it must be implementable as a multiplexer selecting
between two functions, each of four variables. Clearly, a
4-input multiplexer meets this requirement; each 4-input
function implements a 2-input multiplexer, and the final
multiplexer selects one of the outputs.
Since the CLB only has five logic inputs to the function
generators, the sixth input to the multiplexer must reach
the function generators via the CLB .di pin, a flip-flop and
the internal feedback path. Routing through a flip-flop has
obvious timing implications, but using this path can result
in through delay and resource savings of 50%. Often the
additional select delay can easily be accommodated, and
sometimes it even saves storage resources elsewhere.
One approach is to pipeline the select lines, Figure 1.
Two bits of the 4-input multiplexer are implemented in two
CLBs. In one CLB, the So select line is registered, while
in the other the Sl select line is registered. In addition to
being used within the CLB, the registered versions are
output for use in the other CLB. This balances the delay
in the select lines. Notice that the order of the multiplexer
ranks is reversed in the two CLBs.
Alternatively, if the design requires one of the multiplexer
inputs to be pipelined, this input may use the flip-flop
route, thus saving an external pipeline register, Figure 2.
In either case, one CLB flip-flop remains available for
optional use registering the multiplexer output.
Wider Multiplexers
If the multiplexer select line can be pipelined, large multiplexers are best implemented using multiple ranks of the
4-input multiplexer described above, together with a 2input multiplexer, if required. Even if a completely combinatorial circuit is absolutely necessary, there are better
alternatives to using multiple ranks of 2-input multiplexers.
While 4-input multiplexers cannot be implemented in a
single CLB, it is possible to implement a 3-input mUltiplexer in one CLB. If this 3-input multiplexer is considered
part of a 4-input multiplexer that is completed elsewhere,
it can be used in expansion schemes, and binary encoding of the select lines can be retained.
The 8-input multiplexer, Figure 3, uses two 3-input multiplexers and a 2-input multiplexer to select one bit from
six; on the two outstanding select codes, Zeroes are
selected. These two select codes are also used to AND
the. corresponding inputs into a 2-input multiplexer. The
output of this multiplexer is Zero whenever one of the
other six select codes is asserted, and consequently, it is
only necessary to OR the two outputs to complete the
multiplexer.
This structure requires four CLBs, as does the 2-input
multiplexer approach. However, the delay is only two
CLBs instead of three, a reduction of 33%.
8-116
Multiplexers and Barrel Shifters in XC300OlXC3100
INAo
INBo
INCO
INDo
:
-~
" UTo
~)
G
E
-
01
Q
0
So
>
-
01
Q
0
>
INAo
INCo
A
~
F
B
~
>-
INBo
INDO
C
-
- G
~~
i>
~
0
I;
E
X3093
Figure 1. Dual 4:1 Multiplexer with Pipelined Select (Two CLBs)
I
XAPP 026.001
8-117
E:XIUNX
INA---it=!
INB
So
INC
Q
A
B
D
C
Q I--'~-- OUTPUT
L-J
D
(Optional)
IND
SI
E
X3113
Figure 2. 4:1 Multiplexer with Pipelined Input
o
OUTPUT
o
2 Levels
4CLBs
Binary Encoded
Select Lines
X3114
Figure 3. 8:1 Multiplexer
XAPP 026.001
8-118
Multiplexers and Barrel Shifters in XC3000IXC3100
10
11
12
0
SOS1
14
15
16
0
0
3 Levels
SoS1
8CLBs
SOS1
Binary Encoded
18
19
110
Select Lines
0
SOS1
112
113
114
OUTPUT
0
SOS1
115
13
17
111
0
S2S3
X311S
Figure 4.16:1 Multiplexer
An output enable control is provided that permits the multiplexer to be expanded by ORing the outputs in an additionallevel of logic. A single CLB can implement a 5-input
OR gate. Consequently, this expansion scheme can
accommodate up to 40-input multiplexers within three
levels of CLBs. The more significant select lines must be
decoded to provided individual enables to each 8-input
multiplexer, but this logic settles in parallel with the first
level of CLBs.
For 16-input multiplexers, the design shown in Figure 4
may be used. It requires eight CLBs in three levels, which
is one CLB fewer than is needed to combine two 8-input
multiplexers, and one less level of CLB than a design
based on 2-input multiplexers.
XAPP 026.001
Barrel Shifters
A four-input barrel shifter has four data inputs, four data
outputs and two control inputs that specify rotation by 0,
1, 2 or 3 positions. A simple approach would use four 4input multiplexers, since each output can receive data
from any input. This approach yields the best solution
only if the select lines can be pipelined, and the 4-input
multiplexer design described above is used. The complete barrel shifter can be implemented in one level of
four CLBs.
If the barrel shifter must be fully combinatorial, it is better
to decompose the barrel shifter into 2-stages, Figure 5.
The first stage rotates the data by 0 or 1 positions, and
8-119
II
INO
--,.---+---1
I-f---t--;
t-t-------
OUTo
r - - - - - O U T1
I - I - - t - - - - - OUT2
IN3
--+--++---+
t - t - - - - - - - OUT3
So
X3116
Figure 5. 4-Bit Barrel Shifter
the second rotates the result by 0 or 2 positions.
Together, these two shifters provide the desired rotations
of 0, 1, 2 or 3 positions. As in the previous design, four
CLBs are required, but the number of levels increases to
two. A combinatorial 4-input multiplexer approach would
have used six CLBs in two levels.
This binary decomposition scheme can be used for any
number of bits. The number of levels required for an N-bit
shifter is log2N, rounded to the next higher number if N is
not a power of two. Each level requires N/2 CLBs. The
first level rotates 0 or 1 positions, and subsequent levels
each rotate by twice as many positions as the preceding
level. The select bits to each level form a binary-encoded
shift control.
For example, an 8-bit barrel shifter can be implemented
in three levels of 2-input multiplexers that rotate by 1, 2
and 4 positions. Each level requires four CLBs, for a total
XAPP 026.001
of 12. For a 12-input barrel shifter, four levels of multiplexer are required. These multiplexers rotate by 1, 2, 4
and 8 positions, and require a total of 24 CLBs.
The 16-bit barrel shifter shown in Figure 6 has only two
levels of CLB, and is, therefore, twice as fast as one
using the 2-input multiplexer approach. However, the shift
control must be pipelined, since it uses the 4-input multiplexer shown in Figure 1. The first level of multiplexers
rotates by 0, 1, 2 or 3 positions, and the second by 0, 4, 8
or 12 positions. Each level requires 16 CLBs, and the
total of 32 is the same as for the 2-input approach. The
shift control remains binary.
Again, this scheme can be expanded to any number of
bits using log4N rotators that successively rotate by four
times as many bit positions. For sizes that are odd powers
of two, the final level should consist of less costly 2-input
multiplexers.
8-120
Multiplexers and Barrel Shifters in XC300OlXC3100
4
r-- INT15
r-- INT14
4
4
4
~
INT13
INT13, 1, 5, 9
~
INT12
INT12, 0, 4, a
4
r4
4
INT11 ,15,3,7
INT10
INT10, 14,2,6
>-
----
>-
4
INg_12
>-
4
r-
INa_ll
-------
4
r-- INTll
~
>-
----
4
INT14, 2, 6,10
r4
-
----
4
INT15, 3, 7, 11
4
i---.. INTg
4
r----
r4
4
r4
4
INTg, 13,1,5
INTa
4
INTa, 12,0,4
4
: - INT7
-
INT7, 11, 15,3
INT6
INT6,10, 14, 2
~
INT5
INT5, 9, 13, 1
r-- INT4
INT4, a, 12, 0
4
4
>-
4
4
INT3, 7,11,15
INT2
INT2,6, 10, 14
r----
r-
4
r-- INT3
4
>-
,....
.....
INT13
INTg
- r---- INTl
I--
INT5
INTl
~
i-
........
2
-
~
INTs
INTo
INTo
~
1
j
INT4
OUTg
OUTa
--
t-- ~ OUTo
~
~
i
2
Figure 6. 16-Bit Barrel Shifter
XAPP 026.001
~
INT12
OUT 10
----------
4
r-
OUT11
8-121
X3117
I
Implementing State Machines
in LeA Devices
Application Note By PETER ALFKE and BERNIE NEW
XAPP 027.001
Summary
This Application Note discusses various approaches that are available for implementing state machines in LCA
devices. In particular, the one-hot-encoding scheme for medium-sized state machines is discussed.
LCAFamily
Demonstrates
XC3000IXC31 00
State Machine Design
One-hot Encoding
Introduction
Synchronous Counters
State-machine methodology defines the contents of
every flip-flop in a design under every circumstance that
might arise. It also defines all the possible transitions that
can cause the design to go from one of these states to
another. In its simplest form, this is just a rigorous way of
designing synchronous logic, like 4-bit counters. For
more complex designs, the state-machine approach
gives the designer a tool to analyze all possible operating
conditions, and so avoid overlooked hang-up states or
undesired transitions. LCA devices with their abundance
of flip-flops lend themselves well to state-machine
designs.
Using only two CLBs, it is possible to construct fully synchronous 4-bit counters with arbitrary count sequences,
Figure 1. The CLB Clock Enable inputs even provide
count-enable control. The count length, count direction,
and even the code sequence is determined by the configuration. The number of possible count sequences is factorial 15, Le., more than 1012 • All four outputs are
available, and while the counter cannot be preset to an
arbitrary value, it can be cleared by an asynchronous
input.
Using the 5-input function generator of the XC3000 family
devices as a 32-bit ROM, a state machine with up to 32
states with no conditional jumps uses only five CLBs.
Five registered CLB outputs drive the five functiongenerator inputs of five CLBs in parallel. This implements
a fully programmable sequencer such as a synchronous
counter.
Table 1 shows four common count sequences. Of particular interest is the Gray code, which offers glitch-less
decoding, since only one bit changes on any transition. A
Gray-code counter can also be reliably read asynchronously. In contrast, if a binary counter is read during its
transition between 7 and 8, for example, any code might
be detected.
Decimal
0
For a smaller number of states, some inputs can be used
as conditional jump inputs. Encoding these condition
codes, however, may require an additional level of logic
which reduces the maximum clock rate.
0
3 ----"
-[3-0
-0 ~02
2
3
4
5
Any Sequence:
3
O 2 ----..
Function
0 1 ----.. Generator
0 0 ----"
~
6
7
8
9
Binary
Gray
BCD
X3
0
3-
0201_
0 0-
Function
Generator
-[3-01
-0---
10
11
12
13
14
15
X3-Gray
Biquinary
Etc.
~
00
Figure 1. Synchronous 4-Bit Counter in 2 CLBs
X3086
Binary
Gray
X3 Binary
X3 Gray
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0000
0001
0011
0010
0110
0111
0101
0100
1100
1101
1111
1110
1010
1011
1001
1000
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
0010
0110
0111
0101
0100
1100
1101
1111
1110
1010
Table 1. Four Common Binary Count Sequences
8-122
Implementing State Machines in lCA Devices
Four-bit counters constructed as described above can
easily be concatenated into longer, four-bits-at-a-time ripple-carry counters. For each 4-bit digit, a third ClB is
used to detect an arbitrary terminal count value, and AND
this with the incoming Count Enable to provide the Count
Enable to the next digit.
Waveform Generator
Arbitrary binary waveforms of any length up to 32 clock
periods can be generated using only three XC3000series CLBs, Figure 2. The waveform generation is fully
synChronous, and may be paused at any time, using the
CLB Clock Enable. It may also be restarted, using the
asynchronous clear.
°
Five flip-flops, 0-4 , form a linear feedback shift-register
counter. The 5-input combinatorial function generator, Fo,
determines both the modulus and the count sequence;
there are no illegal or hang-up states. The function generator, F1 , operates as a ROM, and can be programmed to
provide any conceivable decode of the counter. Flip-flop,
5 , synchronizes and de-glitches the decoder output.
°
-0-
04 3 -
0 02
F
1
0100-
The following examples demonstrate the arbitrary nature
of the waveforms that can be generated.
Example 1. + 28 counter with its output High at times
T2, T3, T10, T22 through T27
Example 2. + 19 counter with its output Low at times
T9, T12, T15, T18.
Simple State Machines
The Simple state machine shown in Figure 3 uses only 10
CLBs, and has up to 16 states. Each of eight outputs
decode/encode any combination of states. The state
machine is based on a 5-CLB next-state look-up table.
Each state corresponds to two look-up table locations
that store two arbitrarily defined next states. From any
state, the C input controls a two-way branching by selecting which of the two possible next states is asserted. For
hold loops, one of the next states should be the current
state; and to avoid branching, both destination states
should be made equal.
Encoded Output
Q
(any pattern)
~
o
27
e.g.
)(3087
Figure 2. Synchronous 5-Bit Waveform Generator in 3 ClBs
L
L-....,.
C
CONTROL B
INPUTS
A
•
32 Word
Next·State
Look-Up
Table
(5CLBs)
-
"u-::
U
State
Reg
Decodel
Encode
(4 CLBs)
State
Machine
~ Output
A
l' (1CLB)
ActIvate a-Way Branch
Figure 3. Simple State Machine
XAPP 027.001
I
I
8-123
X3085
E:XILINX
The state machine can also perform 8-way branches
from any state so programmed. The branch destinations
must all fall in two quadrants (0 ..3, 4 ... 7, 8 ... 11 or
12... 15). The choice of the two quadrants is arbitrarily
programmed into the look-up table; C selects between
the two quadrants, and A and B select the state within the
quadrant.
Activation of the 8-way branch mechanism is controlled
by a fifth state bit that is set during the transition into the
state. This bit controls a multiplexer that replaces the two
LSB of the destination state with the control inputs A and
B. Note that as the fifth bit is independent of A and B, it
must be set, or not, on a per quadrant basis during an 8way branch.
Examples:
• From state 3, if C = High, go to 5, else go to 8
• From state 7, if C = High, go to 3, else stay in 7
• From state 9, unconditionally go to 2
Truth Table
B
C=Low
0
0
12
0
13
0
C = High
0
14
2
15
3
In LCA devices, flip-flops are plentiful, and there is no
need to conserve them. Consequently, for medium-sized
state machines, it is better to use a One-Hot encoding
scheme (OHE). OHE increases the number of flip-flops
required, but reduces the logic complexity associated
with each of them, thereby boosting performance.
In an OHE state machine, one flip-flop is assigned to
each state. it is set during that siate, and oniy during that
state. The state machine is implemented as a shift-register-like structure, where a single One is passed from flipflop to flip-flop, sometimes holding in the same flip-flop,
skipping bits of the shift register or moving to a parallel
shift register, Figure 4a and b.
The control logic associated with each state bit involves
ORing the transitions into the state, including any hold
loop. Each of these transitions will involve a previous
state, which, by design, is represented by a single bit.
This bit may, or may not, be ANDed with some decode of
the control bits inputs.
• From state 6, execute the truth table below
A
used (but ~ log2N), and a unique combination of these
flip-flops is set in each state; each flip-flop is set in several states. While this minimizes the number of flip-flops,
it increases the complexity of the logic controlling each
flip-flop.
One-Hot Encoded State Machines
The state machines described have encoded state bits.
For an N-state state machine, fewer than N flip-flops are
It is the localization of the control logic that leads to the
performance increase. For each state bit, the control
logic only involves the limited number of state bits from
which there are transitions and the conditions that control
those transitions. This permits shallow logic structures
between flip-flops, often only requiring the function generator associated with the state-bit flip-flop. In addition,
no state decoding is necessary, and state encoding can
only require the ORing of state bits.
Control
Bits-r'"
Figure 4a. Prototype OHE State Machine
XAPP 027.001
8-124
Implementing State Machines in LCA Devices
Complex State Machines
Srnall- and medium-sized state machines can easily be
implemented within an LCA device, as shown above.
For large, complex state machines, however, it is better to
use the LeA device to implement a simple microsequencer,
and store the control program externally, Figure 5.
For fastest operation, a high-speed SRAM should be
used for the control program. This may be loaded from a
microprocessor, or shadowed by an EPROM. For slower
operation requiring non-volatility, an EPROM can be used
directly. When an EPROM is used, the number of components can be reduced by storing both the LCA configuration data and the state-machine control program in the
same device.
CBB
If an XC3020 is configured in the Master Parallel mode
and it reads its configuration data out of a 256K (32K x 8)
EPROM, it only requires 6% of the addresses, from the
top location 7FFF (32K) through 77FF (about 30K). The
remaining 94% of the EPROM can be used as a nextstate look-up table With a capacity of 240 states.
Eight state bits are read out of the EPROM and registered in the LCA device which can perform any required
decoding or encoding of the state-machine outputs. The
registered state bits also form part of the new EPROM
address, defining a block of 128 possible next states. The
7-bit condition code completes the EPROM address and
selects which of 128 next states is actually asserted.
Figure 41l. State Diagram for Prototype OHEState Machine
Xc3020
State Machine
Outputs
7
ControI
}
Inputs
::l
-
P
32Kx8EPROM
8
Data
I
Addrs
X3092
Figure 5. Rudimentary Complex State Machine
XAPP 027.001
8-125
Each transition is, in effect, a 128-way branch. However,
the branching complexity will normally be reduced by
assigning identical values to many of the 128 possible
next states.
Since the top 16 address locations are used for configuration data, the state codes, which form the 8 MSBs of
the EPROM address, are limited to 240 different values,
0 ... 239. The control inputs provide the seven LSBs of the
EPROM address. If the control inputs are asynchronous,
they must be registered for reliable operation.
This rudimentary state machine can thus have 240 different states, and can jump from any state to anyone of 128
arbitrarily defined next states, accoiding to a 7..bit condi·
tion code. In its simplest form, this basic design consumes no CLB resources in the LCA, just lOB flip-flops
XAPP 027.001
for the state register. Even so, it permits a number of
states and a multi-way branch complexity far in excess of
any normal need.
The user has all the logic resources of the LCA available
to add features like the following.
• State decoding/encoding
• Stack registers
• Loop counters
• More sophisticated branch logic, etc.
This design is straightforward, inexpensive, compact and
extremely flexible. Its speed is limited primarily by the
control store access time; faster access times can be
obtained using SRAMs in place of EPROMs.
8-126
Frequency/Phase
Comparator for
Phase-Locked Loops
Application Note By PETER ALFKE
XAPP 028.001
Summary
The phase comparator described in this Application Note permits phase-locked loops to be constructed using
LCA devices that only require an external voltage-controlled oscillator and integrating amplifier.
Xilinx Family
XC3000/xC3100
XC4000
Introduction
A Phase-Locked-Loop (PLL) manipulates a local voltagecontrolled oscillator (VCO) so that it is in phase with a reference signal. One popular application is a programmable frequency synthesizer for radio communications.
Here a crystal oscillator is divided down to a low reference frequency of 5 kHz, for example.
As shown in Figure 1, a programmable divider scales the
VCO frequency down to the fixed reference frequency.
The counter output is compared to the reference frequency to generate a signal that, when required, modifies
the VCO frequency up or down until the comparator
inputs are not only of the same frequency, but also in
phase.
This frequency/phase comparator must have a wide capture range, i.e. it must generate the appropriate output,
not only to pull in a small phase error, but also to correct a
large frequency error. It should not generate false outputs
when the input is at a multiple or fraction of the desired
frequency. The well-known circuit shown in Figure 2 performs this function. It generates pump-up pulses when
the VCO frequency is too low, pump-down pulses when
its too high. The multiple feedback network assures
proper operation even with large frequency errors. Figure
3 shows this circuit implemented in two CLBs plus two
lOBs, directly driving the integrator (lOW pass filter) controlling the VCO.
From VCO _ _LY'-T--;:::==r~--l.~OO~W~N~
Integrator
Divided by N
Reference Fa
'----Output Frequency
From
UP
Reference --I~-l---L-===LY,~---
Frequency
X30Bl
Figure 1. Typical Digital Phase-Locked Loop
X3079
Figure 2. Digital Frequency/Phase Detector
8-127
I
Frequency/Phase Comparator for Phase-Locked Loops
From
VCO
Divided
byN
-l----++---'
CLB 1
Reference -t----i;-t----'
Frequency
ToVCO
+2.5 V
X3080
Figure 3. FrequencylPhase Detector Using Two CLBs and Two lOBs
XAPP 028.001
8-128
Serial Code Conversion
between BCD and Binary
Application Note
XAPP 029.000
By PETER ALFKE and BERNIE NEW
Summary
Binary-to-BCD and BCD-to-binary conversions are performed between serial binary values and parallel BCD
values.
Xilinx Family
Demonstrates
XC3000
Serial Arithmetic
Introduction
The LCA architecture with its powerful function generators evenly interspersed between flip-flops lends itself
very well to serial code conversion. Data is entered into a
register in one format, and retrieved from the .same register in a different format. A common application of this
technique is converting binary data to BCD, and BCD to
binary.
Operating Description
Binary-to-BCD Conversion
Binary-to-BCD conversion is performed in a modified shift
register that successively doubles its BCD contents. As
shown in Figure 1, the binary data is shifted into the converter serially, MSB first. Subsequent bits are entered into
the shift register to fill the LSB vacated by the doubling.
The conversion is complete when all bits of the binary
input have been entered, at which time the BCD result is
available in parallel form. Each input bit will have been
doubled and redoubled to regain its original binary
weight, but in BCD format.
To remain a valid BCD number when doubled, a BCD
digit of 5 or greater must not just be shifted, but must be
converted into the proper BCD representation of its doubled value; along with a 1 being shifted into the next
higher digit, a 5 is converted into a 0, a 6 into a 2, a 7 into
a 4, an 8 into a 6, and a 9 into an 8.
The binary-to-BCD converter requires three CLBs for
each BCD digit in the output, Figure 2. To start a new
conversion, INIT should be asserted at the time the
binary MSB is applied to the converter input. INIT clears
all bits except the LSB which is loaded.
BCD-to-Binary Conversion
BCD-to-binary conversion reverses the process
described above, Figure 3. BCD data is parallel loaded
into a modified shift register that successively halves its
contents. The equivalent binary value is obtained serially,
LSB first, from the LSB of the shift register.
To divide by 2, data in the shift register is shifted towards
the LSB. However, when a bit shifts across a digit boundary, its weight in the lower digit is 5. This value is added to
the shifted digit using carry-save adders associated with
bits 0 and 2. The conversion is complete when all bits of
the binary output have been generated.
The BCD-lo-binary converter requires three CLBs per
digit, Figure 4. A new conversion is started by applying
the BCD data and asserting the LD control to load the
data. The MSB of each digit is loaded into the carry flipflop of the bit-2 adder; the carry of the bit-O adder is
cleared.
I
INIT------~~------~------~-----------+
Binary
Data ~_--I
(LSB First)
BCD
BCD
Digit 0
Digit t
Figure 1. Binary-to-BCD Converter
8-129
X3122
Serial Code Conversion between BCD and Binary
1
~~I
'---
o
a
~[»------/1l~"
D
~
'---
~I~
a,
-
DI
MOD
D
IN
1
a
00
~
'---
L~5
-
I
MOD
OUT
X3082
INIT
Figure 2. Binary-to-BCD Converter (Three CLBs per BCD Digit)
BCD
Digit 0
[5
;
~lD
1111
BCD
Digit 1
14 ; ! 111
Binary
Do D, D2 D3
Data _.----1.00
00
(lSB First)
Figure 3. BCD-to-Binary Converter
XAPP 029.000
8-130
LD Do D, D2 D3
00
00
I
.}
+--
To
~:~~r
X3083
I::XIUNX
1
?=1}-~~3
...
I
>
IC3
-
!~
r:
I
)J
>--tJ-~ r- O
>
2
~
t;J-;:
I
01
-
t
'--
~
]
)-~1
C1
>
'---
II
~~
Do
>
J
'---
iJ5
X3084
Figure 4. BCD-ta-Binary Converter (Three CLBs per BCD Digit)
I
XAPP 029.000
8-131
Megabit FIFO in Two Chips:
One LCA Device and
One DRAM
XAPP 030.000
Application Note By PETER ALFKE
Summary
This Application Note describes the use of an LCA device as an address controller that permits a standard
DRAM to be used as deep FIFO.
Xilinx Family
Demonstrates
XC3000IXC31 00
Non-linear Counters
Pseudo-random RAM Addressing
Introduction
A bit-serial FIFO buffer is a general-purpose tool to
relieve system bottlenecks, e.g., in LANs, in communications, and in the interface between computers and peripherals. Small FIFOs are usually designed as asynchronous shift registers, but a larger FIFO with more than 256
locations is better implemented as a controller plus a twoport RAM, or as a controller plus a single-port RAM,
either SRAM or DRAM.
SRAMs are fast and easy to use, but at least four times
more expensive than DRAMs of equivalent size. Dynamic
RAMs offer lower-cost data storage, but require complex
timing and address multiplexing, which makes them unattractive in small designs. For FIFOs with more than 256K
capacity, a DRAM offers the lowest cost solution, if the
controller can be implemented in a compact and costeffective way. An XC3020 Logic Cell Array can easily perform all the control and addressing functions with many
gates left over for additional features. The XC3020 can be
programmed to control one or more DRAMs for a FIFO of
up to 16 megabytes, with data rates up to 16 Mbits per
second serially or 16 Mbytes per second byte-parallel.
Logic Description
A straightforward design would use synchronous binary
counters for the two pointers, but it is far more efficient to
use linear feedback shift-register (LFSR) counters. Such
counters require significantly less logic and are faster
since they avoid the carry propagation delay inherent in
binary counters. LFSR counters have two peculiarities:
they count in a pseudo-random sequence, and they usually skip one state, Le., a 20-bit LFSR counter repeats
after 22°_1 clock pulses. In a FIFO Controller, both these
issues are irrelevant; the address sequence is arbitrary,
provided both counters sequence identically.
The RAS/CAS multiplexing of the 20-bit address is performed without an explicit multiplexer. Every other bit of
the shift-register counter is used to provide the 10-bit
address. Before the incrementing shift, these bits are
used as the Row address. After incrementing, they are
used as the Column address. The Column address of any
position is thus identical with the Row address of the following position, but since the binary sequence of a shift
register counter is pseudo-random anyhow, this is not a
problem.
This FIFO DRAM controller comprises the following.
• InpuVoutput buffer with synchronizing logic
•
•
•
•
When the Write and Read pointers become identical as a
result of a Write operation, the FIFO is full, and further
Write operations must be prevented until data has been
read out to create space in the memory. If the two pointers become identical as a result of a Read operation, the
FIFO is empty and further Read operations must be prevented until new data has been written in. With a singleport RAM, Read and Write operations must be inherently
sequential, and there is no danger of confUSing the full
and empty state, a problem that has plagued some twoport deSigns.
20-bit Write pointer (counter)
20-bit Read pointer (counter)
20-bit full/empty comparator
1O-bit address multiplexer
• Control and arbitration logic
Figure 1 is a block diagram of the FIFO Controller. The
Write pointer defines the memory location where the
incoming data is to be written, while the Read pointer
defines the memory location where the next data can be
read. The identity comparator between the address pointers signals when the FIFO is full or empty.
The address generation logic is shown in Figure 2. With
this design, two shift-register counter bits fit into one
XC3000-series CLB, with the identity comparator using
the combinatorial portion of the same CLB, Figure 3.
8-132
Megabit FIFO in Two Chips: One LCA Device and One DRAM
DIN
n,::
7
IClK
DOUT
n/
.
nc:.
nc:.
RDRB
(Read Ready/Busy)
I-
~
~
Write Pointer
WRRB
(WriteRe ady/Busy)
1
FUll
Control
-1
WRE
RDE
• D
7
OClK
EMPTY
Q
7
I/O
Buffer
Comparator
I
L
r
-
DRAM
10
MUX
AO·9
~
Read Pointer
~
10
3/
/
X3070
Figure 1. Megabit FIFO Controller in an XC3020
The FIFO controller permits the user to perform totally
asynchronous Read and Write operations, while it synchronizes communication with the DRAM. The design
takes advantage of the DRAM internal refresh counter by
using CAS-before-RAS refresh/address strobes.
Both 20-bit pointers, plus their 20-bit identity comparator,
plus the Row/Column multiplexer thus fit into only 20
CLBs; refresh timer and address multiplexer use another
10 CLBs and the data buffer plus control and arbitration
logic take another 23 CLBs, for a total of 53, an easy fit in
an XC3020.
multiple parallel bits, e.g., byte-parallel operation, interrupt-driven control, multiplexed data for multiple parallel-bit
storage, and byte parallel storage with bit-serial I/O. This
latter case requires special attention when the FIFO is
emptied after a non-integer number of bytes has been
entered, and requires direct communication between the
input Serial-to-Parallel converter and the output Parallelto-Serial converter.
This design is available from Xilinx. Call the Applications
Hot Line 408-559-7778 or 1-800-255-7778.
This design can easily be modified for larger or smaller
DRAMs. Other variations that might be considered are:
XAPP 030.000
8-133
I
P~h------------~
IPD-
Shift Register (Write)
I
~
I--I----I--I--Fully
Identity Comprator
Empty
--+
2:1
MUX
--+
DRAM
Address
--+
--+
--+
--+
-1D-
Shift Register (Read)
Pop------------~
X3071
Figure 2. DRAM Address Generation
XAPP 030.000
I
~
8-134
Megabit FIFO in Two Chips: One LCA Device and One DRAM
or----
-D
o-
DIN
DIN
Read
Address
,---
D
F
~D
01--
01--
-
D
F
-
-
r--- D
COMPo
0
Or---
WrHe
Address
Compare
Two
Address
Bits
-
DIN
DIN
Write Address
Read Address
X3072
Figure 3. 2-Blt Slice of 'TWo Counters and Comparator In Two CLBs
I
XAPP 030.000
8-135
Boundary-Scan
Emulator for XC3000
Application Note By BERNIE NEW
XAPP 007.001
Summary
CLBs are used to emulate IEEE1149.1 Boundary Scan. The LCA device is configured to test the board interconnect, and then' reconfigured for operation.
Xilinx Family
Specifications
Tests Supported
EXTEST
XC3000IXC3100
Number of CLBs
11 Core Logic
1/2 to 1-1/2 per lOB
1 per 3-State Control
Demonstrates
State Machine Design
Introduction
With more complex integrated circuits and more densely
packed PC boards, testability is a major issue.
One solution to the testability problem is boundary
scan. The. XC4000-series LCA devices include boundary
scan registers that meet the requirements of the
IEEE1149.1 standard. While this standard provides for
diagnostic testing and supports built-in self-test (BIST),
one of its primary objectives is the testing of the interconnections between ICs. This is achieved using a mandatory external test mode, called EXTEST.
Although the XC3000-series LCA devices do not contain
boundary-scan registers, it is possible to configure an
XC3000 to emulate the EXT EST. This emulation consumes a significant amount of the LCA resources
(almost all in an XC3020), and it is not suggested that
boundary scan be built into a working deSign. However,
because the RAM-based LCA device is reconfigurable, it
can be configured for board testing, and then reconfigured for operation.
The second mandatory test mode, SAMPLE!PRELOAD,
has no meaning because the LCA device must be
reconfigured for testing. It is not, therefore, supported by
the emulator. However, the minimum 2-bit Instruction
Register provides four instructions to select between two
choices, the Test Data and Output Registers. For consistency with other boundary-scanned parts, one of these
instructions could be used to create a dummy SAMPLE!
PRELOAD mode. Functionally, this would duplicate the
EXTEST with the Test Data Register selected.
Four pins must be dedicated to the Test Access Port
(TAP). Due to external interconnection requirements
these pins can probably not be reused in the actuai
design.
The TAP Controller, Instruction Register, Bypass Register and Test Data Output Buffer together with miscellaneous logic require 11 CLBs. The CLB requirement for
the Test Data Register depends upon the number of
lOBs used, and how they are configured. Each requires
between 1/2 and 1-1/2 CLBs, plus 1 CLB for each distinct 3-state control. While this may not allow every lOB
to be bidirectional with an independent 3-state control it
will accommodate most designs.
'
A specific boundary-scan emulation must be created for
each LCA design. This comprises the 11 CLBs of core
logic, which is common to all emulations, and a Test
Data Register concatenated from four standard cells
according to the output usage in the design. The output
pins must be tied to match the design.
Operating Description
Overview
A block diagram of the IEEE1149.1 Boundary-Scan
emulator is shown in Figure 1. The four pins used are
Test Data In (TDI), Test Data Out (TDO), Test Mode
Select (TMS) and Test Clock (TCK). Operation of the
emulator is controlled by the TAP state machine. This, in
tum, is controlled by the serial TMS data stream.
Test data is shifted from TDI, through either the Instruction or Test Data/Bypass Registers, to the TDO. The
choice between Instruction and Test Data/Bypass Registers is made according to the TMS bit-stream. The Test
Data or Bypass Register is selected by the contents of
the Instruction Register.
Before shifting commences, input data is captured by a
parallel transfer into the appropriate shift register. After
~hifting is complete, new data is transferred in parallel
Into a second register where it is available to the outputs.
8-136
Boundary-Scan Emulator for XC3000
TEST DATA REGISTER
TOI---.
TOO
BYPASS
REGISTER
BUFFER
TOO
CONTROL ---------
TMS-TClK
TAP STATE MACHINE
AND
MISCELLANEOUS lOGIC
X1981A
Figure 1. IEEE 1149.1 Emulator Block Diagram
After configuration, the emulator automatically enters the
power-up state required by the specification, and therefore, the Test Reset Signal (TRST) is not implemented.
However, the polarity of all the registers is such that global reset may be used for this, if desired. The input pins
used for TMS and TDI, and TRST if used, should be
pulled up.
TAP Controller State Machine
The state diagram for the TAP Controller state machine is
shown in Figure 2. This is implemented as two linked
state machines, each using "one-hor' encoding.
The state-assignment table for this state machine is
shown in Figure 3. Four state variables are used to create
the states Test Logic· Reset, Run Test/Idle, Select DR
Scan and Select IR Scan.
In the latter two states, the second state machine may be
initiated. This has six state variables, and creates the
states Capture (CAP), Shift (SH), Exit1 (E1), Pause
(PAU), Exit2 (E2) and Update (UPD). These are qualified
by the output of the first state machine to control the Test
Data and Instruction Registers as necessary.
While this second state machine in operating, the first
state machine is held in its current state. Following the
Update state, the first state machine is forced to the
appropriate state determined by TMS.
Figure 4 shows the schematic diagram of the state
machine, together with the equations that determine its
next state. The only point of special interest is the use of
clock enable in the first state machine. When the second
state machine is in any of its first five states, the clock is
disabled in the first state machine, thereby saving complexity in the next-state logic.
XAPP 007.001
8-137
Note that the RTI flip-flop has inverters at its input and
output. This causes the RTI state to be stored in activeLow form, such that this state is activated upon configuration or global reset. The pairs of flip-flops identified by circled numbers may be combined into single CLBs. The
state machine requires six CLBs.
Instruction Register
The Instruction Register, shown in Figure 5, is two bits
long, the minimum according to the specification. The
shift register is enabled when the Instruction Register is
selected by the state machine. In the Capture state, it is
parallel loaded with 01 (Binary), as required by the specification. It shifts data in the Shift state, and holds at other
times.
Data from the shift register is clocked into the parallel register during the Update IR state. This parallel register is
provided with a synchronous reset, which operates during
the Test Logic/Reset state. The data in the parallel register is stored in inverted form, such that the Bypass Register (mandatory code: all ones) is selected after
configuration or following a global reset.
For verification that the correct configuration has been
loaded, additional bits could be added at the TDI end of
the shift register. During Capture, these would be loaded
with a code unique to the configuration. This would then
be shifted out and become available as status bits. The
parallel register need not be extended. Alternatively, the
optional ID Code register could be implemented.
Test Data Register
The Test Data Register contains as many bits as there
are used lOBs, plus one bit for each distinct 3-state control. This is concatenated from four types of 1-bit macros.
Each of these is tied to a specific lOB, and the type of
macro is determined by the function of the lOB.
I
o
NOTE: The value shown adjacent to each state trans~ion in this figure
represents the signal present at TMS at the time of a rising edge at TCK.
X320B
Figure 2. State Diagram for the TAP Controller
The simplest macro, shown in Figure 6, is used for input pins. Data from the pad is loaded during Capture,
when the Test Data Register is selected. This macro uses
1/2 CLB.
The last macro, shown in Figure 9, is an enhanced macro
for bidirectional pins This operates in the same way as the
enhanced 3-state output macro, but has an additional
multiplexer that selects between the input data and the
Figure 7 shows the second macro, which also requires
1/2 CLB. Although this may be used for 3-state and bidirectional outputs, it is most appropriate for simple outputs.
Data from the shift register is clocked into the lOB output
flip-flop by Update DR. During Capture, data from the pad
is loaded into the shift register.
.:>
Q::1:::!l?", ~
I::'Q::Q~ (J"<' ~ II; ~"<'
TEST LOGIC RESET
RUN TEST/IDLE
SELECT DR SCAN
CAPTURE DR
SHIFT DR
EXIT 1 DR
PAUSE DR
EXIT 2 DR
UPDATE DR
SELECT IR SCAN
CAPTURE IR
SHIFT IR
EXITllR
PAUSE IR
EXIT 2 IR
UPDATE IR
If the output is enabled, as is always the case in a non-3state pin, the data captured is the contents of the parallel
register, provided it is not corrupted by an interfering
external signal. If the 3-state output is not enabled, data is
always captured from an external source; or it is undetermined if an external source does not exist.
A better output macro is shown in Figure 8. The lOB flipflop is replaced with a CLB flip-flop. During Capture, the
parallel register is always read back into the shift register.
However, this macro requires 1 CLB per output.
This macro should also be used to control 3-state outputs.
When the design gangs several outputs onto one 3-state
control, only one of these macros need be used to control
the ganged outputs.
XAPP 007.00t
Q
4Y .§
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
o
0
0 0
0
0
0
0
0
0
1 0
0
0
0
0
0
0
0
0 0 000
0 0 0 0 0
0 0 0 0 0
0 0 0 0
0
0 0 0
0 0 1 0 0
0 0 0 1 0
0 0 0 0
0 0 0 0 0
0 0 0 0 0
1 0 0 0 0
0 1 0 0 0
0 0
0 0
0 0 0
0
0 0 0 0 1
0 0 0 0 0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
X1983
Figure 3. State Assignment for the TAP State Machine
8-138
Boundary-Scan Emulator for XC3000
2
~o a~
CD
>
2
CE
2
~~o
>
£--0
RTI
CD a
Q
£--0
DRS
®
Q
SH
®
2
Q
E1
®
>
CE
1
~~o>
3
>
CE
1
~~o>
is--°>
Q~
®
Q
£--0
IRS
®
2
Q
PAU
®
>
CE
£--0
1
Q
E2
®
>
-8- 0
2
Q
UPD
®
>
1
5
TMS
t
TCK
TLR
RTI
DRS
IRS
CAP
II
E2
E1
SH
PAU
UPD
X3209
Figure 4a. TAP State Machine (6 CLBs)
XAPP 007.001
8-139
I:: XiUNX
TLR = CE[(IRS· UPD + TLR) • TMS) + Ce • TLR
TDO Buffer
Figure 11 shOws the Test Data Output Buffer. Data is
selected from the Instruction Register, the Test Data Register or the Bypass Register, and clocked out on the neg~
ative edge of TCK. The 3-state output is only enabled
during Shift. The TOO Buffer uses 1 CLB.
RT1 = CE{(TLR + RTI + UPO) • TMS) + Ce • RTI
DRS = CE{(RTI + UPD) • TMS) + CE· DRS
IRS = CE[DRS • UPD'. TMS) + CE· IRS
CAP = (RDS + IRS) • TMS
SH = (CAP + E2 + SH) • TMS
E1 = (CAP + SH) • TMS
Miscellaneous Logic
The Miscellaneous Logic, shown in Figure 12., uses 1-1/2
CLBs. Its function is to combine states from the state
machine to enable various registers.
PAU = (E1 + PAUl • TMS
E2=PAU·TMS
UPD = (E1 + E2). TMS
CE =CAP+SH + E1 + PAU+ E2
Most registers in the emulator are clocked by TCK (or its
inverse) and controlled by enables. The only exception is
the lOB flip-flop used in tt-je simple ,output macro of the
Test Data Register. Since lOB flip-flops have no clock
enable, a gated clock must used.
X'985
Figure 4b. TAP State Machine Logic Equations
parallel register according to the 3-state control. This
macro uses 1-1/2 CLBs.
Rather than ANDing the clock with a gating signal, a flipflop is used. During Update when the Data Register is
selected, Update DR is clocked High on the negative
edge of TCK. The state maChine can only remain in the
this state for one period, and this defines the length of the
update clock. The ACLK buffer is used to distribute the
Update DR clock.
Bypass Register
The Bypass Register, shown in Figure 10, operates when
the Data Register is selected. A zero is loaded during
Capture, and data is shifted through the register during
Shift. Otherwise, the register holds. The Bypass Register
uses 1/2 CLB
1
,~8=,
QP--
...--U
,~6=,
QP--
...--U
...-1>
...-1>
TLR
SHIFT
TOI
[&T
S
D
Q
O-C
[tj=
S
1-
r->
,CE
.9
0
r->
Q
TDO_I R
CE
CAPTURE
TCK
IRS
I,
10
INSTRUCTION
o
0
TEST DATA REG
o
DUMMY SAMPLEJPRELOAD
BYPASS REG
o
X3210
Figure 5. Instruction Register (2 elBs)
XAPP 007.001
8-140
Boundary-Scan Emulator for XC3000
Implementation Notes
D
NEXT
CELL
Q
PREV6~~~ - - - - - I
CE
SHIFT - - - - - '
DRS (SH+CAP)
TCK
X3211
Figure 6. Data Register Input Cell (112 CLB)
The design support for the XC3000 Boundary-Scan Emulator comprises five soft macros. The first of these contains the 11 CLBs of core logic, including the Test Access
Port. Location constraints must be added to the schematic to specify the desired location of the TAP input and
output pins.
The remaining macros support different types of input/output pins. These macros need to be selected according to
the input/output utilization, and connected to form a shift
register between the data pins of the first macros. Again,
a location constraint must be added to each macro, specifying the pin with which it is associated.
3-STATE
D
Q
lOB
FF
UPDATE_DR
-----------+--1>
Q~~~--------------~~~~~
D
PREVIOUS
CELL
SHIFT _ _ _..J
DRS (SH + CAP)
TCK
X3212
Figure 7. Data Register Output/Bidirectional Cell (112 CLB + lOB Flip-Flop)
D
UPDATE_DR
Q~-----_..--
TO lOB
------------+--f)
Q~-~---------------+~~~
D
PREVIOUS
CELL
CE
SHIFT _ _ _..J
DRS (SH + CAP)
TCK
X3213
Figure 8. Data Register Enhanced Output/3-state Cell (2 bitS/2 CLBs)
XAPP 007.001
8-141
II
~XIUNX
3-STATE
o
UPDATE_DR
Q~-~-~--~
------------+---1
o
PREVIOUS
CELL
Q~-~---------------+~~~
SHIFT _ _ _...J
I DRS (SH + CAP)
TCK
><321.
Figure 9. Data Register Enhanced Bidirectional Cell (1-112 ClBs)
SHIFT - - - - - ,
IRS - - - - - ,
SHIFT
TOO - - - - I
o
Q
DR
~~~r
----I
o
TDO_BYP
CAPTURE - - - - - '
BYPASS _ _ _-----'
(10)
CE
TCK
TCK
DRS
X3215
Figure 11. TOO Buffer (1 ClB)
Figure 10. Bypass Register (112 BlB)
IRS
UPD
D-
-----------l
UPDATE_IR
DRS
UPD
ACLK
TCK
X3217
Figure 12. Miscellaneous logic (1-112 ClBs)
8-142
X3216
Complex Digital
Waveform Generator
Application Note By BERNIE NEW
XAPP 008.002
Summary
Complex digital waveforms are generated without the need for complex decoding. Instead, fast loadable
counters are used to time individual High and Low periods.
Xi/inx Family
Specifications
Minimum High/Low Time
Maximum High/Low Time
Resolution
Number of Highs and Lows
Number of CLBs
44 ns
>250 ~s
4 ns
32
40
XC3000/XC3100
XC4000
Demonstrates
Fast Loadable Counters
CLB ROMs
Complex digital waveforms with unequally spaced transitions are often generated by decoding a counter that
cycles with the same period as the waveform. If precise
placement of edges is required, the counter must be
clocked at high frequency. This increases the burden on
the decoders; not only must they settle faster, but if the
period of the waveform remains constant, they must
become wider. These two requirements are incompatible. Decoders typically become slower as they get wider.
The values stored in the ROM are used to load a presettable counter that times the duration of individual High
and Low segments of the complex waveform. A second
counter is enabled whenever the timer is reloaded, and
tracks the segment number in the waveform. This is
used to address the ROM and access the length of the
next segment.
The least significant bit of the second counter toggles
after each cycle of the timer and thus creates the output
waveform. This output is guaranteed to be glitch free,
since it is generated by toggling a flip-flop.
In LCA devices, this problem can be overcome by using
high-speed counters in conjunction with data stored in
ROM. The data stored in the ROM is not the waveform
itself, but a run-length encoded version of it. A block diagram of the waveform generator is shown in Figure 1.
In an LCA device, the ROM may be implemented in
the CLBs. Each function generator may be used as a
1
NUMBER OF
HIGHS & lOWS
ROM
HIGHILOW
TIME
j>
1
PRESETTABlE
COUNTER
1
1
TC
II
PE
PE
CE
COUNTER
TC
-
~
r
ClK
OUTPUT WAVEFORM
(lSB)
X1927A
Figure 1. Precision Waveform Generator
8-143
Complex Digital Waveform Generator
16 x 2-bit ROM or as a 32 x 1-bit ROM. In the XC3000
series, ROM data may be entered at the schematic level
using 16:1 or 32:1 multiplexers to represent ROM bits.
The ROM values are applied to the data inputs of these
multiplexers as hard-wired ones and zeros. CLBMAPs
are used to lock the multiplexers into CLBs. APR incorporates the ones and zeros into the logic function, and creates the desired ROM as 4- or 5-input function generator
look-up tables.
Using a state-skipping technique, the maximum clock
rate for a presettable counter in an XC3100-series LCA
device is 270 MHz. This provides for defining the duration
of Highs and Lows in 4-ns increments. In such a counter,
the shortest delay is 11 clocks, giving a minimum High
or Low time of 44 ns. While some periods longer than
this are also unavailable, the availability of all periods
of 30 clocks or greater (~120 ns) is guaranteed. The
16-bit timer allows maximum High and Low times of
XAPP 008.002
262 Ils. Up to 32 Highs and Lows can be accommodated
using 32-word ROMs, for total waveform periods of up to
8ms.
The 16-bit timer requires 18 CLBs, and a further six are
used in the segment counter. The 32 x 16-bit ROM adds
16 CLBs, for a total of 40.
ROM values may be used more than once in a waveform.
To do this, the output of the second counter must be
encoded to the appropriate ROM address. With this technique, any waveform length may be accommodated, provided it comprises a limited number of distinct time
intervals.
Multiple waveforms may also be generated using this
scheme. A single timing counter is used to create a
super-set of transition times for all the waveforms. Individual state machines are then used to create the different
waveforms from this timing information.
8-144
Harmonic Frequency
Synthesizer and
FSK Modulator
XAPP 009.000 I::l
Application Note By BERNIE NEW AND WOLFGANG HOFLICH
Summary
Harmonic Frequency Synthesizer
Uses an accumulator technique to generate frequencies that are evenly spaced harmonics of some minimum
frequency. Extensive pipelining is employed to permit high clock rates.
FSK Modulator
A modification of the Harmonic Frequency Synthesizer that automatically switches between two frequencies in
accordance with an NRZ input.
Specifications
Xilinx Family
Harmonic Frequency Synthesizer
Maximum Output Frequency
Minimum Output Frequency
Frequency Spacing
Clock Frequency
Number of Bits
Number of ClBs
FSK Modulator
Operating Frequencies
Jitter
Clock Frequency
Number of ClBs
XC3000/xC3100
XC4000
67 MHz
1 Hz
1 Hz
67 MHz
Demonstrates
Pipelining
26
52
10/11 MHz
±8 ns
64 MHz
10
Introduction
Most frequency synthesizers derive their output by using
programmable counters to divide the clock frequency.
This results in a set of attainable output frequencies that
are sub-harmonics of the clock, and are defined by the
following equation.
fOUT
the clock rate is a power of two, all integer frequencies
up to the clock rate can be generated.
It must be recognized, however, that these frequencies
describe the average rate at which output pulses are·
generated. Output transitions can only be generated an
=fCLK / N
, . . - - - - - - - - OUTPUT
These frequencies are unevenly spaced, and the spacing becomes especially coarse as the required frequency approaches the clock frequency, where only one
half, one third, etc. are available. If more than one exact
frequency is required, the clock must be a common multiple of these frequencies.
.
FREQUENCY
CONTROl(N)
REG
II
A better approach is to use an accumulator to generate
the frequencies, as shown in Figure 1. This results in a
set of harmonic frequencies, defined by the equation:
fOUT
=N X fCLK / 2n
Here the attainable frequencies are evenly spaced. If
multiple frequencies are required, the clock need only be
a binary multiple of a common factor of the frequencies,
.This requirement is often easier to satisfy. In particular, if
~ Supporting design files are available on the Xilinx
Technical Bulletin Board under the name XAPPOO9V (Viewlogic)
ClK
x, ......
Figure 1. Accumulator-based Frequency Synthesizer
8-145
Harmonic Frequency Synthesizer and FSK Modulator
integer number of clock periods apart, and this leads to
jitter. As the output frequency approaches the clock rate,
this jitter becomes severe.
a 2-clock delay into the third bit, and so on. However, this
can be greatly simplified if the input only changes occasionally.
A potential disadvantage of this scheme is the complexity
of the adder and its effect on speed, when compared to
the counter approach. However, this can be overcome
through the use of pipelining.
Figure 2 shows the accumulator cell with its delay equalizer. The accumulator cell is a simple full adder with its
output registered and fed back to one of its inputs. A pipeline flip-flop is introduced into the carry path.
Operating Description
The accumulator input that controls the frequency is
stored in a register. Individual bits of this holding register
are enabled from flip-flops that are connected as a shift
register. When the frequency is to be changed, the appropriate number is input to a holding register, and a Single
one introduced into the shift register. As this one propagates through the shift register, individual bits of the holding register are successively updated. This update occurs
in synchronism with an addition propagating through the
pipelined adder.
Each Xilinx XC3QOO-series and XC4000-series CLB contains two flip-flops. One of these can be used to form the
accumulator register, leaving the other to pipeline the
carry path. A pipeline flip-flop is inserted between all the
bits of the adder. The output skew this creates is not a
problem as only the carry-out is of interest.
Matching the pipeline delay at the input is also not an
issue if only one frequency is required, as the input never
changes. If multiple frequencies are required, the input
might simply be changed, but this would cause a phase
discontinuity. Where this is unacceptable, a delay equalizer must be added, such that each addition into the accumulator is completed with the same input.
For an n-bit accumulator, the data must be held at the
input to the hQlding register for n clocks after the update
pulse. This is the only restriction on how fast the frequency can be changed. Also, it takes n clocks from the
update pulse before the frequency change is reflected at
the output. At this time, however, the change is instantaneous and phase continuity is maintained.
Conceptually, this requires a triangular array of registers,
generating a 1-clock delay into the input of the second bit,
UPOATE IN
c IN
D
Q
I--
....--..
'II
.-
J0
>
Lr;
UPDATE
Q-
~
'8v-
--F;
:==:
I -
Q
OUT
0
Q
r--
>
Xl .....
Figure 2. Bit-slice of the Frequency Synthesizer
XAPP 009.000
D
8-146
This synthesizer design uses two CLBs per bit. Exploiting
the direct interconnect between CLBs in the XC3000series devices, either version can be operated at clock
frequencies in excess of 90 MHz in a -125 part. If placement and routing do not provide for direct interconnect,
the maximum speed is reduced. This is always true when
the accumulator is longer than one column of CLBs in the
target LCA device.
As an example, a 26-bit frequency synthesizer, clocked at
67.108864 MHz (2 26 Hz), generates every integer-valued
frequency up to this clock rate. Fifty-two CLBs are
required, and the synthesizer fits into any XC3000-series
LCAdevice.
A harmonic frequency synthesizer is useful as an FSK
modulator. For FSK modulation, the synthesizer must
alternate between two frequencies. This can easily be
accommodated by modifying the delay equalizer, as
shown in Figure 3.
Two numbers, appropriate to the two frequencies, are
applied to the delay equalizer. If the frequencies must be
programmable, these numbers can come from inputs or
registers. Otherwise, they can be hard-wired at the inputs
of the CLBs, or individual function generators can be
modified to incorporate them.
NRZ data is applied to the shift register. As this propagates through the shift register, multiplexers at the input to
each bit of the holding register detect changes in the data.
When a change is detected, the bit is reloaded from the
appropriate number. Again, changes ripple through the
holding register in synchronism with the additions. The
NRZ data may change every clock, if required.
A typical FSK modulator, as shown in Figure 4, might be
required to switch between 10 and 11 MHz. To give a
square output, a flip-flop is used to divide the synthesizer
output by two. This flip-flop may be the carry pipeline of
the final adder, modified to toggle with the carry rather
than storing it.
The toggle flip-flop must be enabled at frequencies that
are twice the output frequencies. The largest common
factor of 20 and 22 MHz is 2 MHz, and the clock frequency must be a binary multiple of this. Higher binary
multipliers will result in lower jitter. In this case, 64 MHz is
chosen. This is 25 times 2 MHz, and a 5-bit accumulator
must be used. Twenty and 22 MHz are 10 and 11 times 2
MHz, respectively, and these are the numbers that must
be accumulated to generate the frequencies (OA Hex and
OB Hex). This FSK modulator may be implemented in only
10 CLBs.
If an analog output is required, either version of the synthesizer may be used to control a counter, as shown in
Figure 5. The output of this counter is used to access a
look-up table, which provides data to a DAC.
NRZIN
(01)
0
or--
~
....---..
NA j
-,
NB j
0
HI
TO
ACCUMULATOR
l>
NRZ OUT
X1930A
Figure 3. Delay Equalizer for an FSK Modulator
XAPP 009.000
0
8-147
I
Harmonic Frequency Synthesizer and FSK Modulator
In the XC3000-series, the CLB function generators may
be used as ROMs to implement the look-up table internally. The CLBs actually contain RAMs that are written
during configuration. As a result, multiple wave-shapes
can be supported by re-configuring the LCA device. The
XC4000-series provides user-accessible RAM in the
CLB. Wave-shapes, therefore, can be changed on the fly.
An external look-up table may also be used. In particular,
a video RAMDAC can be loaded with the wave-shape.
This is sequentially addressed at appropriate intervals to
generate the waveform with the desired frequency.
n
ClK
NRZDATA
64 MHz
!
~
OA HEX
(10 MHz)
5/
FREQUENCY
/
--+
FREQUENCY
SYNTHESIZER
FSK
MODULATOR
OB HEX
(11 MHz)
5/
I
~
C OUT
EN
+2
COUNTER
f----+
--+
lOOK-UP
TABLE
--+
DAC
10/11 MHz FSK
~
X1931A
X1932A
Figure 4. 10t11-MHz FSK Modulator
XAPP 009.000
ANALOG
--+ WAVEFORM
Figure 5. Analog Waveform Generator
8-148
Bus-Structured Serial
Input/Output Device
XAPP 010.001
Application Note By BERNIE NEW
Summary:
Simple shift registers are used to illustrate how 3-state busses may be used within an LCA device. Dedicated
wide decoders are used to decode an 110 address range and enable the internal registers.
Specifications
Xilinx Family
Bus Width
Maximum Bus Speed
Number of Serial Channels
Maximum Serial Speed
16 Bits
40 MHz
12
60 MHz
Number of CLBs
96
XC4000
Demonstrates
3-state Buffers
Wide Decoders
Introduction
The combination of long data lines and 3-state buffers,
found in Xilinx devices, is ideal for bus-structured applications. In this simple example, multiple shift registers
are implemented to provide a serial input and output
facility. This is purely illustrative, and the shift registers
may easily be replaced with more complex functions.
In an XC4000-series LCA device, there are two horizontal Longlines equipped with 3-state buffers (T-BUFs)
between each row of CLBs. In an XC4005 that has 14
ADDRS 4
rows of CLBs, there are 28 such lines. However, each of
these may be split into two independent halves. This
provides for construction of up-to-56-bit busses,
although the number of potential bus connections is
reduced.
For the purposes of this example, shown in Figure 1, a
16-bit bus is created. The flip-flops in the CLBs are used
to implement the shift registers, with two bits per CLB
(eight CLBs per shift register), as shown in Figure 2. The
function generators preceding the flip-flops are used to
ADDRS N-1
I
1-············1
WIDE DECODER
........... -
ADDRS 0-3 _ _---,.4.--/
READIWRITE
ENABLE DECODERS
X1933A
Figure 1. Serial Input/Output System
8-149
Bus-Structured Serial Input/Output Device
combined into a single, bidirectional bus in the lOBs. Similarly, the shift-register inputs and outputs could remain
separated, or combined for bidirectional operation.
SHIFT
OUT
BUS;+l
-=Q-:
-=y-:
O
t-
If these registers are part of a larger I/O register space,
higher order address bits must also be decoded as chip
select Dedicated iogic is provided aiong the edges of the
chip to serve this exact purpose. Using these decoders is
much faster than using CLBs, and they are free, because
no CLBs are used.
I
0
CE
In the decoder, the address bits from the lOBs are input to
a wired AND. The inputs to this wired AND can be configured to be inverting or non-inverting. In this way, any
fixed combination of ones and zeros can be detected. The
XC4005 allows up to 28 address bits to be decoded in a
single address decoder, and there are 16 such decoders.
~
I
While this totally synchronous I/O system is somewhat
unrealistic, it does illustrate the use of the horizontal Longlines for bussing. If required, each shift register could
have been clocked separately. This would necessitate the
synchronization of the load enables to the individual
clocks. However, only 120 of the 196 CLBs have been utilized, and ample space remains for this minor task and
any other control functions.
BUS;
LOADI
SHIFT
REG SHIFT
IN
IN
REG
OUTPUT
ENABLE
X1934A
Figure 2. Shift Register CLB
select data. For loading, data is taken from the bus; for
shifting, it is taken from the adjacent flip-flop. A register
enable is also provided, that must be asserted for either
loading or shifting the register.
The connections to the bus.are also shown in this diagram. A bidirectional bus has been chosen; both the
inputs and outputs are connected to it. Alternatively, separate input and output busses could have been used.
One Longline would broadcast data to the shift registers,
and a second Longline would use the T-BUFs to multiplex
the parallel outputs of the shift register. These busses
could remain separate through the chip interface, or be
XAPP 010.001
Allowing space for control logic, 12 shift registers may be
comfortably fitted onto the bus. These require a 4-bit bus
address. This can be routed across the top of the shift
registers and decoded at each column. A single CLB can
decode the address, and use it to gate an enable signal.
Two decoders are required for each shift register; one
each for load enable and 3-state enable.
While any combination of functions could be implemented
and bussed together in this way, counters are particularly
interesting. The dedicated carry logic embedded into each
CLB allows loadable counters to be implemented with the
same density as the shift registers; two bits per CLB. This
would permit the construction of a 12-channel, 16-bit
counter/timer.
Note: Implementing the extensive bus structure discussed
in this Application Note requires considerable expertise in
LCA design. The designer must specify the Longlines to
be used, and constrain the placement of logic around
them. The approach is only recommended for experienced LCA designers.
8-150
Light-Driven
Counter Controller
XAPP 012.001
Application Note
By PETER ALFKE AND BERNIE NEW
Summary:
A simple state machine is used to adapt the output of two photo-cells to control an up/down counter. The state
machine provides hysteresis for counting parts correctly, regardless of changes in direction.
Specifications
Xilinx Family
Maximum Clock Frequency
-150 MHz
XC3000/XC3100
Number of CLBs
2
Demonstrates
State-Machine Design
Introduction
A common technique for counting objects is to pass
them through a light beam. Problems can arise, however, if a part dithers on the edge of the light beam and is
counted more than once, or if the direction of motion
changes and a part is recounted rather than uncounted.
These problems may be avoided by using two sensors,
as shown in Figure 1. To be counted, an object must first
obscure one sensor, then obscure the other, clear the
first and finally clear the second. This solves the dither
problem as an object must pass entirely through .the
beam before it can be counted. Sensor Signals resulting
from the object dithering while entering or leaving the
beam will be ignored by the counter.
The direction of motion determines the order in which
the sensors are first obscured and then cleared. A state
machine recognizes the order and controls an up/down
counter to correctly account for parts that pass back and
forth through the beam. The hysteresis in the state
machine even accommodates directional changes while
a part is in the beam.
For the scheme to operate correctly, the object must be
large enough to obscure both sensors. The sensors are
used to control a synchronous state machine, and the
object must move slowly enough that it does not obscure
or clear both sensors within one clock period.
The bidirectionality of this scheme also makes it suitable
for position sensing. The objects discussed above are
replaced by a comb attached to some moving part. The
part position is determined by counting the teeth on this
comb as they pass through the light beam.
Operating Description
The state diagram of the counter controller is shown in
Figure 2. Inputs A and B are High when the sensors are
obscured. While no objects are present, the state
machine holds in the Wait state. As an object moves into
the beam, state variables S1 and S2 simply follow the
inputs with a one clock delay. When the object exits the
,-----------LCA
I
I
I
I
IGHT
~
MoilON ' - - - - - '
PATH
I
UD SYNCRONOUS
UPIDOWN
CE COUNTER
TTL
INTERFACE
OUTPUT
I
I
•
L--------*--------~~------------CLK
Xl994
Figure 1> LCA Light-driven Counter
8-151
I
Light-Driven Counter Controller
01
10
beam, the Count state is entered (83 High) and the
counter is enabled. One clock later, the state machine
automatically moves out of the Count state and into the
Wait state. If a new object is sensed from either direction
during the Count state, the Wait state is omitted and the
appropriate sequence commenced.
The identity of first sensor to be obscured is stored as the
84 variable. This is used to determine which sensor must
be cleared last to ensure that the object has cleared the
beam without reversing its direction. 84 also selects up or
down operation of the counter. The up/down control is set
up at least four clocks before the counter is enabled.
The siaie machine can be irnpiemented in three CLBs, as
shown in Figure 3. The asynchronous TIL-level signals
are brought into the LCA device and registered in the
lOBs. This synchronizes them to the state-machine clock
and eliminates any metastability problems. 81 and 82
share a CLB. 83 is a function of five variables and
requires a whole CLB. 84 occupies the third.
S1 =A
S2=B
S3 = 8," S2" S4" A" B
+ Sl- 52- 84- A· B
(COUNT ENABLE)
s. = s," 5 2"A
(UP/DOWN)
If required, the state machine implementation can be
reduced to two CLBs. Using the DIN input, 81 can be
combined with 83. 82 can then share the second CLB
with 84.
+ S," 52" S4
Input
AB
State Variables S, S2 S3 S4
X2653
Figure 2. Light-driven Counter State Diagram
XAPP 012.001
Any synchronous up/down counter design may be used
in conjunction with this state machine. The maximum
count rate required is one fourth the clock rate.
8-152
~XIUNX
5,
Ae>---{>- 0
Q
0
>
Be>---{>- 0
Q
~
Q
0
>
52
Q-
>
S,5~4AB
-0
Q
53
CE
+5,S~4AB
r
~
~:
Q
5J
U/D
X1996
Figure 3. Light-driven Counter State Machine
I
XAPP 012.001
8-153
Four-Port DRAM Controller
Operates at 60 MHz
Application Note By JEFFREY GOLDBERG
XAPP 036.001
Summary
This Application Note describes a high-performance DRAM controller implemented in a single Xilinx EPLD.
Xilinx Family
Demonstrates
XC7200IXC7300
High-speed State Machines
Introduction
Multi-port memory arrays are used in many applications,
such as telecommunications, graphics and VME cards.
Although these applications serve many different purposes, they share a common need: they must quickly and
efficiently access a shared memory space through several different ports. The control logic must perform a complex arbitration function, yet must run at a high clock
speed.
The XC7236A architecture is well suited for implementing
the fast, complex state machines found in multi-port arbitration schemes. The XC7236A-16 can implement a
quad-ported DRAM memory controller capable of arbitrating among four access requests in one 60-MHz clock
cycle. This DRAM controller is capable of supporting 70Mbyte/s burst transfers over a 32-bit bus, Figure 1.
PORT_A_REQ PORT_A_LOCK
IGRANT_A
The design uses 94% of the available Macrocells, yet
runs at the maximum specified speed of the device.
Familiar third-party tools reduce both the design effort
and time, and XEPLD translator quickly compiles even
the most complex designs.
Theory of Operation
The arbiter implements a round-robin algorithm, where
the priorities for the four ports are arranged in circular
order; the most recently served port is automatically
assigned lowest priority. Each port can also lock the arbiter to retain ownership between back-to-back accesses.
Such locking is necessary for semaphore reading and
writing in multiprocessor systems.
ACCESS_REO
Port
DONE cDoRnAtrMol
Arbiter 1---"""'''-=-1
PORT_B_REO PORT_B_LOCK IGRANT_B
IRAS
ICAS[O:3)
/WE
COL_ADDRESS
PORT_C_LOCK
IGRANT_C
PORT_D_REQ
PORT_D_LOCK IGRANT_D
/WRITE - - - - - - - - - - 1
ffiEADy-----------I
BURST----------I
IBYTE [0:3) - - - - - - - - - - 1
X1817
Figure 1. Quad-Port Memory Controller
8-154
Four-Port DRAM Controller Operates at 60 MHz
The arbiter then goes to the idle state corresponding to
the port that was just serviced, thus placing that port at
the lowest priority level. If another aCcess request is
pending, the arbiter will issue another memory-access
request to the DRAM controller. The data access will
occur as soon as the DRAM controller has precharged
the memory. The interaction between arbiter and DRAM
controller is shown in Figure 2.
The DRAM controller also arbitrates between memory
requests from the ports and refresh requests from the onchip refresh counter, as can be seen in Figure 3. The
address-multiplexer control line and the DRAM strobes
are sequenced by the controller's state machine. They
are enabled by the byte select and write enable outputs of
the port.
The controller informs the port when there is valid data on
the bus by asserting the READY output. If burst access is
enabled, fast 3-clock memory accesses are performed
until the port drops the burst request line. The controller
then begins to precharge the memory, and asserts DONE
to inform the port arbiter that the final memory access is
completed.
Device Utilization
When implemented in PLDs, multi-port-arbiter state
machines tend to be product-term intensive. The
XC7236A is particularly well suited for such applications
since each Macrocell can handle up to 17 product terms.
Arbiter Stete
IIDlEA I
Arbitration
Cycle
_ _ _ _ _ _ _ _A -_ _ _ _ _ _
IIDlEA I
~
,
PORT _A BURST
ACCESS
_ _ _ _ _ _ _ _ _ _- - "
____________
~
Arbitration
Cycle
~
~
,
Arbitration
Cycle
,
The arbiter evaluates incoming access requests while it is
in any of four idle states. The specific idle state depends
on the last request, and determines the priority of the
incoming requests. If the arbiter is not locked, it grants
access to the highest priority request that is pending, and
issues a memory-access request to the on-chip DRAM
controller. During its transition to one of four port-accessactive states, the arbiter asserts the grant signal to the
appropriate port. The grant Signals are used to enable the
port control, address and data busses. The arbiter
remains in its active state until the DRAM controller signals that it has completed the single or burst access.
IIDlEB I
ClK
PORT_A·REO
IGRANT_A
ACCESS_REO
tRAS
'...._________________..J!
J
-.J!
~I..._ _ _ _ _ _ _ _ _ _ _ _ _ _
--1
\........J
'I..._____________________J!
,~
ICAS
_________________J!
'I...._---Jr_\I...._---J!
,~
__________
,~
~!
______~!
'I...._---Jr-__________________Jr_\'-_ _
READY _______________...J/\
r_\~
BURST _ _ _ _ _ _ _ _ _..J!
'...._________________
DONE ____________________________--Jr_\I...________________
~~
-,'-_______'-..Jr-X1818
Figure 2. Quad-Port DRAM Controller Timing Diagram
XAPP 036.001
8-155
I
Of the eight Macrocells required to implement the port
arbiter, one Macrocell uses ten product terms, one uses
nine terms, one uses eight terms; the remaining five Macrocells use seven product terms each. In total, 148 product terms, and 34 of the 36 Macrocells are used. The
Macrocell XOR gates in the XC7236 significantly reduce
the number of product terms used in the 10-bit refresh
counter. In total, the DRAM controller occupies 94% of
the XC7236A.
Design Methodology
The design lends itself very well to a modular behavioral
description of its state machine. The ABEL 4 compiler was
used to generate three Booiean equation files from highlevel descriptions of the refresh counter, and the arbiter
Assert/CAS
Assert ICAS RFRQ
and DRAM controller state machines. A main PLUSASM
file was then derived from the three equation files.
In this design, the main file only defines the external signals to and from the XC7236A. With this design
approach, individual state machines and counters can be
developed in a modular fashion, using the design tools
most appropriate to each module. XEPLD software compiles the files in about five minutes, and generates a single file that can be downloaded into the device
programmer.
Detailed design files are included with the XEPLD software, and are available from Xilinx Applications. They will
soon be availab!e from the Xilinx Technical Bulletin
Board.
RFRQ
IACCESS_REQ + /RFRQ
IACCESS_REQ'/RFRQ
ACCESS_REQ'/RFRQ
Assert/RAS
Assert COLUMN ADDRESS
~......._ _ Assert Enabled NvE
Negate CLR_RFRQ
~-<--
Assert READY
Negate ICAS, READY
BURST_EN
Negate /RAS, ICAS
IBURST_EN
~-<-_
Negate IRAS,/CAS, COLUMN_ADDRESS,IWE
Assert, DONE Negate READY
Negate DONE
X1819
Figure 3. DRAM Controller State Diagram
XAPP 036.001
8-156
Digital Mixer in an XC7272
XAPP 035.001
Application Note
By DAN UJVARI Applied Technical Marketing
Summary
This Application Note describes a simple mixer that operates at video rates, and provides 9 levels of mixing.
Xilinx Family
Demonstrates
XC7200
High-speed Arithmetic
Introduction
A digital mixer provides for controlled transition from one
incoming digitized analog data source to another. A typical application is in broadcast television where the switching between picture sources should be gradual. The
XC7272 can implement such a digital mixer running at a
28-MHz sample rate. It handles two incoming 8-bit data
streams, A and B, and mixes them In nine steps, controlled by a 4-bit coefficient, N.
Coell. -7-'+---------+
B-r-'4-1
Output = A~ -
B~
where N =0,1,2 .... 8
Operation
The design consists of two processing channels, A and B,
combined in an output adder, Figure 1. The two channels
are identical in structure, but are driven by complementary coefficients. Each 8-bit data stream is multiplied by
its coefficient by adding or subtracting the outputs of two
shift arrays, Shift1 and Shift2.
Shift1 can shift by 0,1, 2, or 3 positions, and can disable
its output. Thus, it can multiply the data by 1, 1/2, 1/4, 1/8,
or O. Shift2 can shift by 2 or 3 positions and can also disable its output, thus multiplying the data by 1/4, 1/8, or O.
Table 1 below describes the operation of the complete
mixer.
X1803
Figure 1. 28 MHz Digital Mixer
The design is pipelined for fastest throughput, and has
been implemented in one XC7272. It uses 56 of the available 72 Macrocells and 28 signal pins: 16 data inputs,
four coefficient inputs, eight data outputs and one clock
input. There is room for enhancements such as larger
incoming word length or finer coefficient granularity.
Table 1: Mixer Operation
Coeff
0
2
3
4
5
6
7
8
ASHFT1
0
0.125A
0.250A
0.250A
0.500A
0.500A
0.500A
A
A
ASHFT2
0
0
0
0.125A
0
0.125A
0.250A
0.125A
0
A'
0
0.125A
0.250A
0.375A
0.500A
0.625A
0.750A
0.875A
A
BSHFT1
8
8
0.58
0.58
0.58
0.258
0.258
0.1258
0
8-157
BSHFT2
0
0.1258
0.2508
0.1258
0
0.1258
0
0
0
B'
8
0.8758
0.7508
0.6258
0.5008
0.3758
0.2508
0.1258
0
Output
8
0.125A + 0.8758
0.250A + 0.7508
0.375A + 0.6258
0.500A + 0.5008
0.625A+ 0.3758
0.750A + 0.2508
0.875A+0.1258
A
I
Designing Complex
2-Dimensional
Convolution Filters
XAPP 037.000
Application Note By DAVID RIDGEWAY
Summary
This Application Note shows how to design complex 2-dimensional filters for digital image processing systems.
The XC7200IXC7300 dedicated carry logic is used to perform the complex arithmetic functions.
Xilinx Family
Demonstrates
XC7200IXC7300
High-Performance Arithmetic
Introduction
Image Data
To improve the image quality so that edges can be more
accurately identified, image processing systems use digital filtering. This process creates a new image where the
data is altered to enhance features of interest.
The performance of digital-image-processing filters is usually limited by software algorithms and system throughput.
Faster speeds can be achieved with modified algorithms
and dedicated hardware. USing the high-speed arithmetic
logic functions embedded into the XC7200 architecture,
image-processing systems can perform computationally
intensive tasks, such as edge detection and enhancement, without burdening the processor. This feature significantly improves the overall system performance by maximizing the computational throughput.
Two-Dimensional Convolution
Two-dimensional convolution is a common digital image
filtering technique. A new value is calculated for each
pixel in the image, based on the value of the corresponding pixel in the old image and those that surrounded it.
In industrial applications, a popular filter operator is the
Laplacian edge-enhancement operator, as illustrated in
Figure 1. A 3 x 3 coefficient matrix is overlaid on the
image, and the nine pixels it covers are each multiplied by
the corresponding coefficient. The sum of the nine products is the value in the new image of the pixel that corresponds to the center of the matrix in the original image.
For example, if the matrix is centered over the corner [1] in
the figure, the result is the [5] in the output image.
Laplacian Filter
00 1 1 1
A digital-image-processing system can acquire an image
of an object, process or modify the image data, and use
the result in the performance of a task. In such imaging
systems, edge detection is fundamental to obtaining such
information as contrast, shape, location, and dimension.
However, conditions can occur that make the true image
edges difficult to detect.
0-3 3 00
00 1 1 1
00[1]1 1
00000
Detected Edge
x
-1 -1 -1
0-33 00
-1 8-1
0-2 [5] 3 3
-1 -1 -1
0-1-2-3-3
00000
00000
[5] = Pl, 1 X 11,1 + P2, 1 X 12,1 + ... P3, 3 X 1 3, 3
Figure 1. Laplacian Edge-Enhancement Operator
The Laplacian operator is particularly appealing since all
the coefficients are binary powers. Consequently, the
multiplications can be replaced by shifts, which greatly
simplifies the operation and increases throughput.
The process is repeated with the coefficient matrix centered over each pixel in turn, until new values have been
obtained for each pixel in the image. Effectively, the operator differentiates the image. There is an increase in
magnitude and a sign change in the vicinity of an edge,
and in areas where there is no edge, the output is zero.
After convolution, the data is scaled by a factor of 9, negative values are rectified, and background information is
discarded.
XC7200 Dedicated Carry Logic
XC7200-series Macrocells contain dedicated, hard-wired
carry logic that accelerates and condenses arithmetic
functions such as adders and accumulators. Macrocells
are organized into Function Blocks, each containing nine
Macrocells. The dedicated logic propagates carries
between adjacent Macrocells and adjacent Function
Blocks. This feature makes it possible to develop fast,
wide arithmetic functions. Adders can achieve ripplecarry delays as low as 1.0 ns per bit.
A detailed schematic diagram of the Macrocell dedicated
carry logic is shown in Figure 2. The arithmetic logic unit
(ALU) is a 2-bit function generator that can be programmed to generate any Boolean function of the Dl and
8-158
Designing Complex 2-Dimensional Convolution Filters
ALU
21
CIN
X3068
Figure 2. Macrocell With Detailed Carry Logic
O2 inputs. Combined with the carry input (C IN) signal from
the lower Macrocell, the ALU. can generate either the
arithmetic sum or difference of two operands, and the
carry output (C OUT) to the next higher Macrocell.
Operating Description
Image Convolution
Complete images can be processed at high speeds using
a pipelined algorithm that exploits the architectural features of the XC7200/XC7300 EPLO family. The complete
Laplacian edge-enhancement filter design is shown in
Figure 3.
Image data is input line-by-line. Two shift registers, each
one line long, delay the incoming data such that corresponding pixels from each three consecutive lines are
available simultaneously. The EPLO stores three consecutive pixels from each line in three shift registers, thus
making available a 3 x 3 array of pixels.
These nine pixels are selected in turn as the input to the
accumulator. A second multiplexer at the input to the
accumulator performs the trivial multiplications. Pixels to
be multiplied by eight are shifted three places towards the
most significant bit (MSB); pixels to be multiplied by -1
are inverted and a carry forced into the accumulator completes the subtraction.
XAPP 037.000
A 1-bit slice of the Multiplier-Accumulator is shown in
Figure 4.
Filter Performance
As with any EPLO design, performance can be estimated
with complete accuracy prior to implementation. The data
throughput rate is limited by the propagation delay of the
carry chain from the least significant bit (LSB) input to the
MSB output for the multiply-accumulate function. For the
Laplacian filter design implemented in an XC7272-25
with 8-bit pixels, the maximum propagation delay is
approximately the following.
tpD
= 25 + 15 ns
This gives an accumulation rate of 25 MHz, and a convolution output rate of 2.5 MHz. For a 512 x 512 image
(262,144 pixels), the convolution time for one frame is 104
ms, which is equivalent to 9.6 fps. Higher speed image
convolutions can be achieved by using multiple pipelined
accumulators and summing the output data. In a fully
pipelined deSign, the same 512 x 512 image can have a
convolution time of 10 ms and a frame rate of 100 Hz.
References
1. Louis J. Galbiati, Jr., Machine Vision and Oigitallmage
Processing Fundamentals, Englewood Cliffs: Prentice
Hall,1990.
8-159
I
~XIUNX
110 Block
Image
Input
8
110 Block
""O~
~o
;---
-
'--'--
110 Block
Line
ct
ay
8
~9~
"'"
MUX-t
1/0 Block
Pad
0
U~//
1
Pixel Delay Line
Line
Delay
8
1/0 Block
~o~
TVr~r
Convoluted
Image
-t> r- Output
1
,----
110 Block
Multiply·Accumulator
I
I
Control
Sequencer
Pad
~
4J
2.5 MHz
25 MHz
System
Clock
X3069
Figure 3. LaplaCian Edge-Enhancement Filter
Macrocell
-
2: 1 Multiplexer
PN
01
I'COUT
"'-
r----
V
ALU
Subtract!
Multiply
D2
CIN
V
D
Q
I>
'---
X3067
Figure 4. Bit-Slice of the Multiply-Accumulator
XAPP 037.000
8-160
SECTION 9
1
Programmable Logic Devices
2
FPGA Product Descriptions and Specifications
3
EPLD Product Descriptions and Specifications
4
Packages and Thermal Characteristics
5
Quality, Testing and Reliability
6
Technical Support
7
Development Systems
8
Applications
9
The Best of XCELL
10 Index, Sales Offices
The Best of XCELL
Readback Clarified .............................................................................. 9-2
The Secret of "Tie" .............................................................................. 9-3
The Tilde De-Mystified ........................................................................ 9-3
Configuring LCAs in Parallel ............................................................... 9-4
lOB Options, I/O Clocking; Unused Pins ............................................. 9-4
Don't Overshoot or Undershoot .......................................................... 9-5
Function Generator Avoids Glitches ................................................... 9-5
Worst-Case Input Set-Up Time ........................................................... 9-6
Set-Up and Hold Times ....................................................................... 9-7
Double the Clock Frequency ............................................................... 9-7
Rube Goldberg and the Art of LCA Design ......................................... 9-8
The Effect of Marginal Vcc .................................................................. 9-9
Ground Bounce ................................................................................... 9-10
Three-State vs Output Enable ............................................................. 9-10
Powerdown Operation ......................................................................... 9-11
Input Current Is Zero ........................................................................... 9-11
Don't Pre-Assign Package Pins .......................................................... 9-11
CCLK Max Low Time .......................................................................... 9-11
Just Say No to Asynchronous Design ................................................. 9-12
Internal Bus Contention ....................................................................... 9-14
Loadable Shift Register with Clock Enable ......................................... 9-14
Design Security ................................................................................... 9-15
Powerdown Pin ................................................................................... 9-15
Magnitude Comparator ....................................................................... 9-16
LCA Drives Liquid Crystal ................................................................... 9-16
Comparator, Accumulator ................................................................... 9-17
Sine Wave Generator .......................................................................... 9-18
Volatility ............................................................................................... 9-19
Excessive Idle Power .......................................................................... 9-20
270-MHz Presettable Counter in XC3000 ........................................... 9-20
Don't Drive Mode Pins ........................................................................ 9-22
Faster Multiplexers in XC3000 ............................................................ 9-22
LCA Output Characteristics ............................................................ ,.... 9-23
LFSR Counters ................................................................................... 9-24
Master & Slave Configure Together .................................................... 9-24
Legal Protection .................................................................................. 9-25
High Speed +3 Counter in One CLB ................................................... 9-25
Anatomy of the EPLD Architecture ..................................................... 9-26
Dynamic Power Consumption ............................................................. 9-27
PC-Board Design Hints ....................................................................... 9-28
Crystal Oscillator Considerations ........................................................ 9-30
Two's Complementer .......................................................................... 9-32
THE NEWSLETTER FOR XILINX PROGRAMMABLE LOGIC USERS
Issues 1 through 9
1989 to 1993
1992 Was a Good Year
X
CELL is a quarterly newsletter, sent free-of-charge to
all active Xilinx users. The
purpose is to inform our customers about device and software
availability, about new technical
developments, about designmethodology, problems and workarounds, about additional
electrical parameters not covered
in the Data Book, about clever circuits and tutorial topics, and about
simple solutions to perplexing
problems.
The idea is to bring up-to-date
information to our customers and
make it easier to design with Xilinx
devices and development systems.
To add your name and address to the XCELL mailing list,
call Kathleen Pizzo at:
(408) 879-5377 or fax her at
(408) 559-7114.
Peter Alfke, Editor
Xilinx sales increased from
$130M in calendar 1991 to $163 M
in 1992, maintaining a solid position as the largest manufacturer of
all types of CMOS Programmable
Logic, well ahead of AMD and
Altera. We introduced new products at an ever increasing pace. In
1992, we doubled our product offerings without counting speed
and package options:
We started 1992 with 16 different devices, and we ended 1992
with 32 different devices.
We expect to double the
breadth of our product offering
again in 1993; in the first four
months of 1993 we have already
introduced seven new devices.
Programmable Logic is no
longer a niche product line used
for prototyping. Prices have come
down, speed and density have increased, and our customers appreciate the advantages of a shorter
development cycle and faster timeto-market more than ever.
Number of Available Device Types
Family
JAN'92 JAN'93 APR'93
XC2000
2
2
4
XC3000
5
5
6
8
7
10
3
XC3100
XC4000
3
6
xcnoo
0
2
XC17000
2
3
3
HardWire
4
6
32
6
39
Total
16
9-1
Programmable logic is, therefore, now being used in volume
production. That, in turn, puts
pressure on Xilinx to reduce cost
and prices, and to increase performance and density even more.
One result of this pressure is
product diversification. One product family, or even one technology,
cannot possibly cover all bases.
No single product family can simultaneously be best in cost,
speed, and density for all applications.
The future will see a greater
diversity of programmable logic
device architectures and technologies. Different families will address
different issues. Some will emphasize low cost and high density, sacrificing speed. Some families will
be ultra-fast, but more expensive.
The world is already familiar with
the difference between the register-rich FPGA architecture, and
the more structured and predictable EPLD architecture. Expect
additional architectures and technologies to address different application areas, and expect Xilinx
to remain the leader in this innovation.
Programmable logic has become a significant, and fast growing part of the electronics industry.
Xilinx is totally dedicated to Programmable Logic, in any practical
architecture and technology.
XCELL will keep you informed
about new developments.
PA
II
XC3000 Readback Clarified
The ability to read back configuration data, as well as data
stored in flip-flops and latches, is
crucial for the exhaustive device
testing performed by Xilinx on
every device before it leaves the
factory.
Most of our customers have
no need for this feature, but a few
use Readback to verify that the
configuration is still proper. This
makes sense in applications that
require uninterrupted operation,
e.g. in telecom where the device
may be configured once and then
operates for months or years without ever being reconfigured.
To those few engineers who
really need the readback feature,
we apologize for the user-unfriendly interface and the sometimes sketchy documentation.
Here are some important considerations.
Use Readback only when necessary. Less than 1% of all LCA
applications use it.
Readback does not interfere
with normal LCA operation, but
the flip-flop data being read back
will be almost impossible to interpret unless the LCA device suspends its clocked operation during
Readback.
Readback cannot be daisy
chained. Even when the devices
were configured in a daisy-chain,
they must be read back individually.
Readback data comes out inverted, a configuration 1 becomes
a readback 0, and vice versa.
Readback data contains variable flip-flop or latch data in most
of the locations that were left unused during configuration. If you
want to compare readback data
against the configuration file, you
must disregard (mask out) these
locations as shown below.
Readback has no Preamble,
and no second or third stop bit at
the end of each frame.
The first frame starts with two
dummy zeros instead of the single
start bit (1) preceding every other
frame. Remember, everything is
inverted: Readback start bits are
ones, stop bits are zeros.
Before the device is being configured, Readbackmust be enabled
by the MakeBits menu.
omeans never,
1 means once, and
Cmd means on command.
Readback is initiated by a rising edge on MO. Rising edges on
the CCLK input then clock out the
Readback data, using the MI pin as
an output. The first rising edge of
CCLK does nothing. The second
and third rising edges clock out
the two leading dummy zeros. The
fourth and subsequent rising edges
of CCLK clock out frame information, interspersed with a single a
for stop at the end of each frame,
followed by a single 1 for the start
of the following frame. After the
last frame stop bit has been clocked
out, the MI pin goes 3-state and
further CCLK pulses are ignored.
Verifying Configuration
Bitstream
In order to verify the integrity
of the LCA configuration, you
must compare the Readback
bitstream against the configuration bit stream in all those positions not masked out by a 0 in the
Mask bitstream.
Configuration bitstream and
Mask bitstream have a common
format, both are created from the
MakeBits menu. Since the
Readback bitstream format is different, as described above, you
must adjust the formats before
verification.
9-2
Either: Pad the Readback
bitstream with preamble, two additional stop bits, and change the
two dummy bits preceding the
first frame to a normal start bit,
Or, better: Strip the Configuration and Mask bitstrearns of the
preamble, delete two of the three
stop bits and create the two
dummy bits at the beginning of
the first frame. Always remember
that Configuration and Readback
have opposite polarity.
After the three bitstrearns have
been normalized you can perform
the verification.
There is an error when
(Readback =Configuration AND
Mask = 1.
PA
For XC4000 Readback details,
see the applications section of our
1993 Databook.
Park CClK High
Remember that the CCLK pin
of XC2000 and XC3000 devices
must not be held Low for more
than 5 J.lS. Dynamic circuitry inside the LCA can reach an unknown state when capacitors lose
charge during excessive CCLK
Low time, especially at high temperature, when leakage current is
high.
If CCLK is held Low after configuration, a subsequent Readback
may not function properly, reading back wrong information. Make
sure that CCLK has been parked
High for several milliseconds before the beginning of Readback.
TCW
The Secret of
IITie
The Tilde
De-Mystified
l1
Before generating the configuration bit stream, the user has the
option to tie or not tie the design.
To "tie" means to create additional
interconnects that terminate all
floating transistor inputs or metal
interconnects to well-defined levels or signals.
In a tied design, all inputs and
interconnects are always High or
Low, or are connected to a signal
that switches between defined levels. In a non-tied design, the unused inputs and pieces of
interconnect (there usually are
more unused ones than used ones)
are left floating. This poses no firstorder problem, since these inputs
are really not used. In this respect,
it differs from the well-known
problem of floating TTLinputs that
are supposed to generate a High
level.
The problem with undefined
input levels in CMOS logic is that
they may drift to the midpoint
between Vcc and ground, half turning on both the pull-down and
pull-uptransistor,makingaCMOS
gate draw measurable Icc. Also,
such undefined inputs may be affected by crosstalk from adjacent
lines, thus increasing dynamiC
power consumption.
An untied design is likely to
have increased dc and ac power
consumption and increased onchip noise. That's a good enough
reason to spend the extra effort to
tie every design.
To tie a design, select the -T
option in the XDM MakeBits
menu.
Timing values given by XACT
or APR are sometimes preceded
by the symbol-, called Tilde by its
Spanish name, but really meaning
"approximately" . How should the
user interpret this symbol?
. All non-tilde timing values
given by XACT or APR are carefully simulated, modeled, and
measured worst-case values, guaranteed over the range of processing tolerances and temperature
and supply-voltage variations. The
user can have confidence that no
device will ever exceed these values.
The tilde is a disclaimer. It
means that the delay is generated
by so many concatenated resistor
(or pass-transistor) -capacitor elements, that our design and test
engineers have less confidence in
the accuracy of the model and the
repeatability of the timing value.
Xilinx cannot guarantee it as an
absolute worst-case value.
The number following the
tilde is still a conservative specification; most likely the parameter
in question is better than this value.
But there is not the same guarantee as there is with non-tilde values. What is the user to do?
If a "tilde-value" is critical to
your design, you have two choices:
1. Change the lay-out or routing
such that the long uncertain
delay is broken up into two
"non-tilde" values, either by
passing the net through a BIDI
or through an unused CLB, or
by dividing the net into two
branches.
2. Add 25% to the value and
ignore the tilde, making the
reasonable assumption that
this factor 1.25 compensates
for the modeling uncertainty.
XC2064 and XC2018 ACLK
delay values, though below 10 ns,
are sometimes preceded by a tilde.
You can safely ignore the tilde in
these cases.
There has been a misleading
explanation that the tilde indicates
propagation delay differences between the rising and the falling
edge of a signal. This is not true.
Different from original 2.011 technology XC2000 parts, all newer
technology devices, and especially
the XC3000 family parts, have their
delays finely balanced.
Our designers have painstakingly adjusted n-channel and pchannel geometries to achieve
driving impedances and threshold voltages that guarantee virtually identical propagation delays
for rising and falling transitions.
Maybe we have been overly
pessimistic and caused unjustified
concern with the tilde. Butwe prefer to be cautious and make a distinction between worst-case
guaranteed values and intelligent,
albeit conservative, estimates.
PA
II
9-3
Configuring
Devices in
Parallel
In the special case where several LCA devices contain identical
configuration data, they can be
configured simultaneously to reduce program size and configuration time. When the program is
stored in a Serial PROM, just make
one LCA device the Master, all
others the Slave, interconnect all
CCLKs, and drive all DINs in parallel from the Serial PROM.
There are no timing problems.
Between the 666 ns cycle time and
the 400 ns access plus 60 ns set-up
time, there are over 200 ns available for additional delay. This accommodates at least 250 pF of
additional capacitive loading. The
1 MHz max specification in the
Data Book only applies to
READBACK; during configuration CCLK can be up to 1.5 MHz.
lOB Options
Our Data Book describes the
operation of the XC3000 lOBs and
their configuration options. This
description is not complete: The
activation of the passive pull-up is
really coupled with the Three-State
Enable, giving the following four
choices:
• Passive pull-up activated,
output buffer permanently
three-stated (pin is input only,
with pull-up).
• Passive pull-up de-activated,
output buffer permanently
three-stated (pin is input only,
no pull-up).
• Passive pull-up de-activated,
output buffer active, i.e. threestate control permanently deactivated (pin is ouput only).
output buffer controlled by
three-state control signal (pin
can be I/O).
In other words:
The passive pull-up can only
be used on pure inputs, not on I/O
pins. The three-state control logic
can be permanentlv disabled, resulting • in a perm~nently active
output. The other four options.
OUT INVERT,
THREE-STATE INVERT
OUTPUT SELECT
SLEW RATE
are not interdependent; they operate as described.
The XC4000 output pull-up
and pull-down resistors do not
have this limitation. They can be
used with active outputs.
• Passive pull-up de-activated,
Unused Pins
Xilinx Programmable Gate
Arrays come with an abundance
of user I/O pins, from 58 on the
XC2064 to 144 on the XC3090.
Many applications leave a few, or
even many, of these pins unused,
but even unused pins need some
attention.
Modem CMOS devices have
extremely low input-leakage current, perhaps only a few
nanoamps. (The 10llA guaranteed
specification represents a testing
limitation, not a real input current.)
Left disconnected, such an input could therefore float to any
voltage. Clamp diodes prevent
excursions above the supply voltage and below ground, thus protecting the input gate from
destructive breakdown voltages.
This leaves the problem of inputs
floating uncontrolled between Vcc
and ground.
An input voltage close to the
threshold value 1.2V for TTLlevelcompatibility, 2.5V for CMOS
level-compatibility will tum the
input buffer partially on, thus creating a static current path from
Vcc to ground and causing static
power dissipation. Such a biased
buffer also acts as a fairly high
gain amplifier, making the circuit
very susceptible to noise, crosstalk,
ground-bounce and other undesirable disturbances.
It is, therefore, advisable to
force unused inputs to a proper
logic level.
XC2064 and XC2018
1. Leave unconfigured; externally
connect to a High or Low level.
9-4
2.Configure as active output
driven by an internally
defined signal.
XC3000 and XC4000
Same as above, or
3. Configure as input with internal passive pull-up.
Putting unused 110 to use
An unused XC3000 series lOB
can be used as part of the on-chip
logic, e.g. as a shift register. Note
that the associated package pin
must be left free, and that the speed
is not as high as it is with internal
flip-flops.
Multiple I/O pins can also be
used to perform the "wired AND"
function in conjunction with an
external pull-up resistor.
Donlt Overshoot or Undershoot
Our 1992 Data Book explicitly
forbids input voltage excursions
more than 0.5 V outside the supply voltages (below ground, above
Vcc). Hardly anybody would try
to violate this with a static voltage
or current, but many designs show
PC-board reflections that sometimes exceed these rather tight limits. A better explanation of the
problem is therefore in order.
All CMOS I/O pins are
clamped against Vcc and against
ground through diodes formed by
the respective output transistors.
Pure inputs have equivalent protection diodes. These diodes prevent any excessive voltage on the
gate of the associated input transistor. Without such protection the
input gate might aCcidentally get
charged to a voltage that can rupture the gate oxide and thus destroy the input transistor. All
modern MOS devices have such
input protection.
What happens when the input voltage exceeds the specified
limits?
Below-O.5Y, the ground clamp
diode will start conducting, above
Vcc + 0.5 V the Vcc clamp diode
will start conducting. These diodes are fairly big and will clamp
hundreds of milliamps with a voltage drop ofless than 2 V. The problem is that this clamp current can
stray into an area of the circuit
where it might upset the internal
logic. There is no hard data toquantify this concern, but our circuit
designers feel uncomfortable
about undefined currents of long
duration in parts of the circuit that
were not designed for that purpose.
Very high clamp currents
(more than 100 rnA at elevated
temperature, more than 300 rnA at
room temperature) lastingformilliseconds can cause the parasitic
bipolar input transistors to be triggered like an SCR, which then conducts unlimited Icc and thus
destroys the device. Xilinx devices
are extremely resistant to this latchup.
Conclusion
Try to limit overshoot and
undershoot to 0.5 V, the data sheet
limit. If these values are exceeded,
the clamp diodes will protect the
inputs and limit the voltage swing.
Large clamp currents of millisecond duration must be avoided at
all costs, e.g. by adding current
limiting series resistors.
Never drive inputs with active levels above Vcc, even when
the Vcc supply is turned off.
Strange things might happen during turn-on.
Function Generator Avoids Glitches
The combinatorial logic in all
CLBs is implemented as a function generator in the form of a
multiplexer, built out of transfer
gates. The logic inputs form the
select inputs to this multiplexer,
while the configuration bits drive
the data inputs to the multiplexer.
The Xilinx circuit designers
were very careful to achieve a balanced design with similar (almost
equal) propagation delays from the
various select inputs to the data
output.
The delay from the data inputs to the output is, of course,
immaterial, since the data inputs
do not change dynamically. They
are only affected by configuration.
This balanced design minimizes the duration of possible decoding glitches when more than
one select input changes. Note that
there canneverbe a decoding glitch
when only one select input
changes. Even a non-overlapping
decoder cannot generate a glitch
problem, since the node capacitance will retain the previous logic
level until the new transfer gate is
activated about a nanosecond later.
When more than one input
changes "simultaneously," the user
should analyze the logic output
for any possible intermediate code.
If any such code permutation produces a different result, the user
must assume that such a glitch
9-5
might occur and must make the
system design immune to it. The
glitch might be only a few nanoseconds long, but that is long
enough to upset an asynchronous
design.
If none of the possible address
seque~nces produces a different
result, the user can be sure that
there will be no glitch.
The designer of synchronous
systems generally doesn't worry
about such glitches, since synchronous designs are fundamentally
immune to glitches op all signals
except clocks or direct
SET/RESET inputs.
I
Worst-Case Input Set-Up Time
Timing parameters in programmable devices are more difficult to specify than in
fixed-program devices, because
the user can affect some parameters through routing.
Inside the LCA, a synchronous
design is easy to analyze, because
hold time is not an issue, since
clock skew is much shorter than
the minimum clock-to-Q delay of
any CLB. The only concern is for
performance: Is the sum of propagation delay and set-up time less
than the clock period?
The set-up time at the LCA
input is more complex, since the
clock delay from the clock pad to
the internal clock cannot be ignored.
The data sheet specifies the
lOB set-up time with respect to its
clock (not with respect to the clock
pad!). The unavoidable delay from
clock pad to internal clock must
obviously be subtracted from the
specified set-up time, to arrive at
the system set-up time.
What is the maximum value
for the input set-up time, and what
is its minimum value? Is there a
risk for a hold-time requirement?
Maximum Set-up Time
The longest input pad set-up
time, the one that determines system performance, is the specified
longest lOB flip-flop set-up time
minus the shortest clock delay that
is consistent with such a long setup
time.
The question is:
How well do such delays track
Here is one unrealistic
assumption:
"All delays track perfectly. In a
given part, at any given
temperature and supply voltage,
the ratio of any actual parameter
value to its specified worst-case
value is the same constant. "
If this were true, the max setup time would simply be the difference of the two specified max
values for flip-flop set-up time and
clock delay.
Here is another unrealistic assumption: "There is no delay tracking. Any parameter can vary
between its max and min value,
independent of all other parameters."
If this were true, the max system set-up time would be the difference between the specified max
flip-flop set-up time and the minimum clock delay, whatever small
value that might be.
Both these assumptions
are wrong.
The circuits being evaluated
reside on one piece of silicon. They
were processed together, and they
have a common temperature and
supply voltage. All delay parameters will, therefore, track reasonably well. But since all parameters
do not necessarily depend on the
same physical phenomena (resistance, capacitance, threshold voltage etc.) in the same way, they will
not track perfectly.
We make the assumption that
tracking in anyone device will
be better than 70%.
All ratios of actual delay to
specified worst-case delay for all
parameters on the same device at
any instant will be within a twoto-one range.
• If one delay is close to the
specified max value, then all
the others will be between 70%
and 100% of their respective
max values.
• If the relatively slowest
parameter is at 50% of its
specified max value, then all
the other parameters will be
between 35% and 70% of their
respective max values, etc.
(The user should feel safe with
this conservative assumption.
In reality, parameters track
much better than this.)
.
SPECIFIED WORST-CASE VAlUES
~
..................
1.00
~v.:1
s'-fl
_...u..,.,.'i.~
~GV':.
0.80
0.60
..
.. .' .
'
.. .' .
'
'
..
'
~
_ •.s!) .......
~
~\\..{11'!'.. ~..
I
I
~~......:
l
••••
•
.' .
TYPICAl COMMERCIAL
(+ 5.0 25"C)
v.
•
0.40
0.225 ms), must the user hold
RESET Low until Vcc has reached
a proper level.
After the end of the initialization time-out, each device clears
its configuration memory in a fraction of a millisecond, then tests for
inactive RESET, stores the MODE
inputs and starts the configuration process, as described in the
DataBook. Mter the device is configured, Vcc may dip to about 3.5
V without any significant consequences beyond an increase in
delays (circuit speed is proportional to Vcc), and a reduction in
output drive. IfVcc drops into the
3-V range, it triggers a sensor that
forces the device back to the preinitialization mode described
above. All flip-flops are reset, HOC
goes High; INIT, LDC and Dip go
Low, arid all other outputs are 3stated with a weak resistive pullup. If Vcc dips substantially lower,
the active outputs become weaker,
but the device stays in this preinitialization mode. When Vccrises
again, a normal configuration process is initiated, as described above.
The tiser need not be concerned about power supply dips:
The XC3000/XC4000 device stays
configured for small dips, and is
"smart enough" to reconfigure itself ( if it is a master) or to ask for
recorif~uration by pulling INIT
and DIP Low (if it is a slave ). The
device will not lock up; the user
can initiate re-configuration at any
time just by pulling Dip Low or, if
Dip is Low, by forcing a High-toLow transition on RESET.
II
Ground Bounce
Activating or changing a large
number of output pins simultaneously can lead to voltage spikes
on the ground and Vcc levels inside the chip. The output current
causes a voltage drop in the supply distribution metalization on
the chip, in the bonding wires and
the lead frame. Worse is the inductive voltage drop caused by the
current change over the bondLrlg
wire inductance.
This is a well-known problem
not only with fast bipolar or CMOS
interface devices, but also with
high pin-count gate arrays. It is
commonly referred to as "ground
bounce", because the change in
ground potential is more critical
than the equivalent change in Vcc
potential. (TIL-oriented systems
have far less noise immunity at the
Low level than at the High level).
Xilinx circuit designers have
given the LCA devices a very good
Vcc and ground distribution metal
grid on the chip, as well as double
L
C
A
bonding to every supply pin. Packages below 100 pins have two Vcc
and ground pin pairs, packages
above 100 pins have eight Vcc and
ground pin pairs to reduce supply
lead resistance and inductance.
What can the user do to minimize
ground bounce?
• Provide solid Vcc and ground
levels. Use multi-layer boards
and decoupling. lVire-wrapping
• Stagger the activation or the
change of output drivers by
deliberately introduced unequal
routing delays.
• Move trouble-causing outputs
close to a package ground pin in
order to minimize the device
internal voltage drop. Move
sensitive inputs, like clocks,
close to another package ground
the supply connections is an
invitation to disaster.
• Finally, if there still is a ground
bounce problem on a few
outputs, attenuate and! or filter
these outputs. A50% attenuater
(330Q, 33OQ) perhaps combined
with a 50 pF decoupling of the
center point will reduce VOL and
calm it down. Changing the
upper resistor to a diode might
improve the situation even
more.
• Absolutely always connect all
Vcc and ground pins.
• ConfigureoutputsXC3000slewlimited whenever the required
performance allows this. This is
the defauitoption. Slew-limited
outputs reduce transient
amplitude by 75%.
• Use CMOS input levels
whenever possible. This
increases input noise immunity
from less than 1 V to over 2 V.
OUT
L
3300
J.
y
,
,
50pF :::;:::
3300
C
A
ph!..
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;
-$-
5600
f
Three-State vs Output Enable
The control input that causes
an lOB output or Longline driver
to go into the high impedance state
is called (active High) 'Three-State"
in Xilinx literature and in XACT.
The same signal is commonly
known as (active Low) Output
Enable or OE.
These two signals are identical, i.e. T=OE, as explicitly stated
in our Data Book.
To put it more bluntly: T is not
an active High Output Enable,
rather it is identical with an active
LowOE.
9-10
"Tri-state" is a registered trademark of National Semiconductor
who pioneered this concept on TIL
outputs in the late sixties. The
names "Three-state" or "3-State" are
ways around this trademark. The
name refers to the third state of an
output, beyond active High and
active Low.
Powerdown Operation
A Low level on the PWRDWN
input, while Vcc remains higher
than 3 V, stops all internal activity,
thus reducing Icc to a very low
level:
• All internal pull-ups (on Long
lines as well as on the 1/ a pads)
are turned off.
• All package outputs are three
stated.
• All package inputs ignore the
actual input level and present a
1 (High) to the internal logic.
• All internal flip-flops or latches
are permanently reset.
• The internal configuration is
retained.
• When PWRDWN is returned
High, after Vcc is at its nominal
value, the device returns to
operation with the same
sequence of buffer enable and
Dip as at the completion of
configuration.
Things to Remember
Powerdown retains the configuration, butloses all data stored
in the device. Powerdown threestates all outputs and ignores all
inputs. No clock signal will be recognized. Any input level between
ground and the actual Vcc is allowed. All internal flip-flops and
latches are permanently reset and
all inputs are interpreted as High,
but the internal combinatorial logic
is fully functional.
Things to Watch Out for
Make sure that the combination of all inputs High and all internal Qs Low in your design will
not generate internal oscillations
or create permanent bus con tentionby activating internal bus drivers with conflicting data onto the
same long line. These two situations are farfetched, but they are
possible and will result in increased power consumption. It is
quite easy to simulate these conditions since all inputs are stable and
the internal logic is entirely combinatorial, unless latches have been
made out of function generators.
Make sure that no applied signal
tries to pull any input more positive than the actual supply voltage
(Vcc). This would feed Vcc through
the input protection clamp diode.
Donlt Pre-Assign Package Pins
In theory, FPGAs offer the system designer the option to preassign the package pins and layout
the PC board before completing
the detailed design of the Ie.
This method works well when
the FPGA is sparsely populated
and, therefore, has the additional
routing resources to accommoda te
an imposed pinout.
For typical designs this
method does not work well. We
have seen many cases where the
FPGA could not be routed with
the imposed pin-out, but could be
routed once the pin-out was left
free. This leads to daughter board
unscramblers or to a relay out of
the PC board, headaches and expenses that the user would like to
avoid.
So,asa rule, wait with the pinout assignment until the LCA device has been routed. The exception
to this rule are very sparsely populated designs or designs with very
limited I/O.
9-11
Input Current
is Zero
Some designers keep asking
about input current. Let us state
bluntly:
The input current is negligible,
just nanoamps, if
• The output sharing the same pin
is three-stated,
• The internal pull-up option is
not activated,
• The device is not in
configuration mode where
many pins have internal pullups.
• Vcc is above 4V.
• O:,>VIN:,>Vcc
If you ever observe our inputs
hogging the drive voltage, you
must have done something wrong.
Make sure you counted the pin
number right-and in the right
direction, that you configured the
device properly, and that Vcc is
up. Then use an oscilloscope and
multimeter, but please don't use
the phone. Our inputs don't draw
any current worth talking about,
typically < 100 nA!
PA
XC2000/XC3000
CClK Low Time
Most of the circuitry in our
devices is static, i.e. the chip will
work down to zero clock frequency.
CCLK is the exception. Its circuitry is half-static, half-dynamic
and does not tolerate a Low time
in excess of 5 /lS. For very low
speed operation, you can stretch
the CCLK High time to any desired value, but keep the Low time
short.
XC4000 does not have this restriction.
II
Just Say NO to Asynchronous Design
Synchronous designs are safer
than asynchronous designs, more
predictable, easier to simulate and
to debug. Asynchronous design
methods may ruin your project,
your career and your health, but
some designers still insist on creating that seemingly simple, fast
little asynchronous circuit.
Twenty years ago, TIL-MSI
circuits made synchronous design
attractive and affordable; fifteen
years ago, synchronous microprocessors took over many hardware
designs; more recently, synchronous State Machines have become
very popular, but some designers
still feel the itch to play asynchronous tricks.
The recent popularity ofASICs
has created a new flurry of asynchronous designs in a specially
treacherous environment: Gate
Arrays and Programmable Gate
Arrays are being customized at
the gate level, and may tempt the
designer to develop bad asynchronous habits, especially dangerous
since it is very difficult to inspect
internal nodes, and impossible to
calm them down with capacitive
loads, the BandAidofsimplertechnologies.
Here is a short description of
the ugly pitfalls in asynchronous
design, documented for the benefit of the inexperienced designer.
Veterans are familiar with the problems and may even know their
way around them to design safe
asynchronous circuits.
gate the clock reliably, as shown
below, but this still introduces an
additional clock delay, which can
cause hold time problems.
DISABLE
RISINGE~~
CLOCK
EN~
~...Jt........r
FALLING EDGE
CLOCK
Reliable Synchronous Clock Gating
Ripple Counters
Using the output of one flipflop to clock its neighbor can
generate a binary counter of arbitrary length. The problem occurs
when the counter increments from
2R -1 to 2R. It takes n delays from
the incoming clock to the resulting
change in bit n. In a 16-bit counter,
this delay will be longer than
100 ns. At a 10 MHz clock rate,
certain codes will never exist, the
LSB will have changed before the
MSB reached its new value. Decoding such a counter will produce dangerous decoding spikes.
Note that these spikes are independent of the incoming clock rate.
Designers of slow systems are actually most vulnerable to this problem, since they are less sensitive to
delicate timing issues.
Decoder Driving Clocks and
Reset Inputs
Indiscriminate use of decoder
outputs to clock flip-flops or set/
reset them asynchronously is one
way to invite unpredictable and
unreliable operation. The decoded
outputs from synchronous
counters are even more devious.
While the decoding spikes from
ripple counters are fairly wide and
somewhat predictable, decoding
spikes from synchronous counters
are entirely the result of small but
unpredictable differences in routing and decoding delays.
Using the decoded Terminal
Count as asynchronous Master
Reset input is another popular
method to achieve unreliable operation. The spike might reset some
flip-flops, but not all.
RIPPLE COUNTER
Clock Gating
Gating a clock signal with an
asynchronous enable or multiplex
signal is an invitation to disaster. It
will occasionally create clock
pulses of marginal width, and will
sometimes move the clock edge. A
synchronous signal can be used to
Unreliable Use of Decoders
9-12
Synchronizing One Input In
Several Flip-Flops
Asynchronous Reset of
Multiple Circuits
A single asynchronous input
should be synchronized in only
one flip-flop. There will be an occasional extra metastable delay as
described in the Applications section of our Data Book. This extra
delay is acceptable in all but the
very fastest systems. Synchronizing one input in more than one
flip-flop is another matter. The setup times and input routing delays
of the various flip-flops will inevitably differ by one or several nanoseconds. Any input change
occurring during this time difference will be clocked differently
into the individual flip-flops, and
the error will last for a full clock
period. Synchronize any input
with only one single flip-flop!
A simple RC combination,
perhaps augmented by a diode, is
a popular power-on reset circuit.
When it is used to drive several
ICs in parallel, the system must
accept wide variations in the reset
duration. Differences in input
threshold voltage will cause some
circuits to start operating while
others are still being held reset. If
that is unacceptable, the RC combination must drive only one IC
which, in turn, controls the reset
operation of all others.
Schematic capture packages
have an obsession about details.
Some of them insistthat a connecting dot be put on every T-joint,
even on a connection to a bus. So,
even if you think that it's redundant or ugly, put in the dots. It
saves you from strange problems
later on. One day in the future,
we'll have true Artificial intelligence, and computers will become
our servants,not our masters.
Until then, dot your T's!
PA
~~~CHRONOUS
D
Synchronizing
Multiple Inputs In
One Register
Synchronizing an asynchronous parallel data word can lead
to wrong results when the asynchronousinputs change during the
register set-up time. For the duration of one clock period the register might then contain any
imaginable mixture of old and new
bit values. There is no simple solution, the most popular is to pipeline the result and compare the
previous and present values. Any
difference declares the data invalid. This operation is sometimes
performed in software.
Dot Your Tis!
Q
II:
UJ
ASYNCHRONOUS
DATA
Iii
ffi
II:
Q
10MHz
CLOCK
Dangerous Methods of Synchronizing Asychronous Inputs
1M
TO.
1
Asynchronous Reset of Multiple Circuits
II
9-13
Internal Bus Contention
The XC3000 and XC4000 families have internal3-state bus drivers (TBUFs). As in any other bus
design, such bus drivers must be
enabled carefully in order to avoid,
or at least minimize, bus contention. (Bus contention means that
one driver tries to drive the bus
High while a second driver tries to
drive it Low).
Since the potential overiap of
the enable signals is lay-out dependent, bus contention is the responsibility of the LCA user. We
can only supply the following information:
While two internal buffers
drive conflicting data, they create
a current path of typically 6 rnA.
This current is tolerable, but should
not last indefinitely, since it exceeds our (conservative) current
density rules. A continuous contention could, after thousands of
hours, lead to metal migration
problems.
In a typical system, 10 ns of
internal bus contention at 5 MHz
would just result in a slight increase in Icc.
16 bits x 6 rnA x 10 ns x 5 MHz
x 50% probability =2.5 rnA.
There is a special use of the 3state control input: When it is di-
rectly driven by the same signal
that drives the data input of the
buffer, (i.e. when D and T are effectively tied together, the 3-state
buffer becomes an "open collector" driver. Multiple drivers of this
type can be used to implement the
"wired-AND" function, using resistive pull-up.
In this situation there cannot
be any contention, since the3-state
control inputis designed to be slow
in activating and fast in deactivating the driver.
Connecting D to ground is an
obvious alternative, but may be
more difficult to route.
PA
Loadable Shift
Register with
Clock Enable
CLOCK ENABLE
PREVIOUSQ
SHIFT/U5AD
PARALLEL DATA
Loadable Shift Register (2000 Series)
PARALLEL DATA
SHIFT/LOAD
ENABLE CLOCK
•
PARALLEL DATA
FROM
PREVIOUS
STAGE
9-14
The 2000 Series CLB primitive
shown below is a building block
for a shift register with synchronous load and clock enable, or for
a bidirectional shift register with
clock enable but without parallel
load. The 3000 Series CLB primitive shown below is a 2-bit building block for a shift register with
synchronous load and clock enable, or for a bidirectional shift
register with clock enable but without parallel load.
Design
Security
Some Xilinx customers are
concerned about design security.
How can they prevent their designs from being copied or reverseengineered?
We must distinguish between
two very different situations:
1. The design contains the
configuration data in a serial or
parallel EPROM or in a
microprocessor's memory. This
is the normal case.
2. The
design
does
not
permanently store a source of
configuration, data. After the
LCA was configured, the
EPROM or other source was
removed from the system, and
configuration is kept alive in the
LCA through battery-back-up.
1. In the first case, it is obviously
very easy to make an identical
copy of the design by copying
the configuration data, the
devices, and their interconnect
patterns. Deleting the partidentifying markings on the top
of the ICs would make the
copying slightly more difficult,
but the main defense is legal.
The bitstream is easily protected
by copyright laws that have
proven to be more successfully
enforced than the intellectual
property rights of circuit
designs.
While it is easy to make an
identical copy of the design,
(clearly violating the copyright)
it is virtually impossible to use
the bitstream in order to
understand the design or make
modifications to it. Xilinx keeps
the interpretation of the
bitstream a closely guarded
secret. Reverse-engineering an
LCA would require an
enormously tedious analysis of
each individual configuration
bit, which would still only
generate an XACT view of the
LCA, not a usable schematic.
The combination of
copyright protection and the
almost unsurmountable difficulty of creating a design
variation for the intended
function provides good LCA
design security. The recent
successes of small companies in
reverse-engineering microprocessor support circuits show
that a non-programmed device
can actually be more vulnerable
than an LCA.
2. If the design does not contain
the source of configuration data,
but relies on battery-back-up of
the LCA configuration, then
there is no conceivable way of
copying this design. Opening
up the package and probing
thousands of latches in
undocumented positions to read
out their data without ever
disturbing the configuration is
impossible.
This mode of operation
offers the ultimate design
security.
PA
Nanowatts,
Not Microwatts
LCA power consumption in
the powerdown state has been
somewhat of a mystery. The data
book hints at nanowatts, but the
published specifications only guarantee rnilliwatts.
We tested a representative
sample of parts and found the
powerdown current at room temperature and 5 V mostly below 50
nanoamps. This value is reduced
in half at 2.5 V, but doubles for
every 10°C increase in temperature.
This is good news for batteryback-up. Even the tiniest lithium
battery can power an LCA device
for years.
Why don't we update our
guaranteed specification? One reason is the difficulty of measuring
very small currents on a highspeed production tester. Another
one is the potential yield loss when
this parameter happens to be
higher. No reason to scrap a part
for a parameter that only a few
users are interested in.
PA
Powerdown Pin Must Be High
For Configuration
A Low on the PWRDWN pin
puts the LCA device to sleep with
a very low power consumption,
typically less than one microwatt.
The on-chip oscillator is stopped,
and the low-Vcc detector is disabled. During configuration, the
PWRDWN pin must be High, since
9-15
configuration uses the internal
oscillator. Whenever Vcc goes below 4 V, PWRDWN must already
be Low in order to prevent automatic reconfiguration at low Vcc.
For the same reason, Vcc must first
be restored to 4 V or more, before
PWRDWN can be made High.
PA
II
Magnitude Comparator: Small, Fast, Expandable
A Magnitude comparator is
more complex than an identity
comparator, but simpler than an
adder or subtracter. A magnitude
comparator indicates not only
when two operands are equal, but
also which one is greater if they
PA
are unequal.
Bl
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
AI
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
Truth Table
BO AO A>B AB: = Ao·80·(A1 XOR 8 1
)
Ao
A MCOMP
0
Bo
A,
Bo
A,
B,
B,
A.
B.
>
A MCOMP
0
MCOMP
Ao
A,
Bo
A,
B,
B,
>
Bo
A,
<
B,
<
MCOMP
Ao
Bo
A,
B,
A,
B,
>
<
A MCOMP
0
A,
Bo
A,
B,
B,
>
<
A.
MCOMP
Ao
B.
A,
Bo
A,
B,
B,
MCOMP
Ao
Bo
A,
>
y
B,
>
<
<
Magnitude Comparator Expands to Any Size
+ A 1·81
A
F
Q
x
-
"!
LONG UNE
Q
----Y-
,--
A
Qy
t--
G
I>
' -
o
PA
r----------------..,
A
B
CONFIG X:F Y: DX:DI OV:G CLK:K ASTDIA
C
EQUATE F = - (A@OY)' - (O@OX)
o
0
EQUATE G '" A
o
E
BASE FG
01
ENClK:EC F:A:D:QX'OY
G
EN
EC
ClK
K
HORIZONTAL
LONG LINE
Very Fast Accumulator with Pipelined Carry
The XC3000 family can
implement a very fast (>SOMHz)
accumulator with pipelined carry.
One CLB per bit stores the sum
and the carry in its two flip-flops.
Each clock pulse updates the
two flip-flops with the result of the
addition of incoming operand plus
stored sum.
There is, however, one drawback to this pipelined approach:
Ann-bit accumulator will need up
to n-l additional clock pulses after
the last accumulation in order to
flush out the carry flip-flops.
C IN
+-_-\-____-,
F
C
,N
+-+--.
C OUT
PA
C
A
I
A,-"O"--_----.::B'-jCONFIG X:QX Y:QY OX:F OV:G ClK:K ASTD!R:RD ENCLK:EC F:A:B:OX G:A:B:QX
EN
ClK
RESET
C
EQUATE F=A@(B@QX)
D
E
DI
EQUATE G=(A'B)t(A.QX)+(B.QX)
BASE FG
EC
K
RD
9-17
X
SUM
Programmable Sine Wave Generator
Sine wave frequency synthesizers are used in many applications, like telecom and navigation.
A sine wave of programmable frequency can be generated by sequencing through a look-up table
in ROM that drives a digital-toanalog converter (DAC).
The simplest and most flexible arrangement uses an accumulator to access the look-up table.
(Remember, an accumulator is an
adder / register structure that adds
an input value to the register content each time it is clocked.) The
desired frequency is presented as
a constant (K) to the accumulator
input. Changing K results in an
instantaneous frequency change
(as a result of the next clock edge)
but no sudden phase change, no
"clicks." This is mandatory in modems.
Here is one design example
that fits into 30 CLBs, less than half
of an XC3020: The objective is to
generate any frequency that is an
integer multiple of 1 Hz, the highest frequency being around 250
kHz. The sine wave look-up table
has 64 entries for a 2n (360°) period, i.e. a resolution of 5° to 6°. It
represents the amplitude as a 9-bit
binary word (8 bits plus sign).
These are reasonable parameters,
but each of them could easily be
modified by an order of magnitude without changing the design
concept. The look-up table consists of a 64 x 8 ROM (really a 16 x
8 ROM plus XORs on the address
inputs and data outputs) addressed by the 6 most significant
outputs of the accumulator.
The ratio of max frequency to
frequency resolution determines
the size of the accumulator; in this
case it is 250 kHz + 1Hz = 250,000
or 18 bits. That would, however,
give only one look-up per period
at the top frequency; this design,
therefore, adds four bits to the ac-
cumulator in order to guarantee
sixteen look-ups even at 250 kHz.
The accumulator clock rate is then
determined by the frequency resolution (l Hz) and the accumulator
length (22 bits): If the accumulator
increments by one for every clock
period, it must step through the
whole look-up table once per second. The clock frequency is, therefore, 222 B.z = 4.194304 MB.z.
The four most significant accumulator bits have no data inputs; they can, therefore, be
implemented as a counter. The
look-up table stores only the first
quadrant (90°) of a sine wave, the
other three quadrants are generated by reversing the address sequence (XORing the addresses)
and/ or reversing the sign of the
output (XORing the outputs).
Better frequency resolution
can be achieved by adding stages
to the LSB end of the accumulator
(l CLB for each doubling of the
resolution.) Same clock frequency.
Higher max frequency can be
achieved by adding to the MSB
end of the accumulator and doubling the clock frequency for every
additional bit.
The time granularity of the
look-up table can be doubled to 32
entries per quadrant, increasing
the table from 4 CLBs to 8.
The amplitude granularity of
the look-up table can be changed
in either direction by changing the
number of look-up table planes.
Obviously, the look-up table
can also store other wave shapes
and can be reprogrammed dynamically.
These hints should allow any
designer to custom tailor a similar
frequency synthesizer.
PA
Frequency Synthesizer
Output
Frequency
(Sine Wave Look-Up)
(Hz)
1Hz min
FoUl:
250kHz max
1Hz Resolution
A
C
C
16
18
ClB.
U
4 - Bn Counler
2
ClB.
l
A
T
4 - BII Addr••• XOR
2
ClBs
16x8 ROM
4
ClBs
8 - Bn Output XOR
4
ClBs
3D
ClBs
18 - Bit Accumulator
U
M
K
128
256
0
512
1024
2048
R
Totsl
4096
8192
16384
32768
65536
131072
16 x 8
X
o
ROM
To
R
DAC
Counter
4 Bits
1----------''---22
Clock: 1Hzx2
9-18
= 4.194304 MHz
Sign
Xl341
No Can Do
Xilinx LCAs offer a wide range
of design options and many system-oriented features. There are,
however, some restrictions.
Here are the things you should
not even try to do in the XC3000
family:
The on-chip input pull-up resistor cannot be used if the pin is
configured as I/O, i.e., if the configuration allows the output to be
activated. The resistor cannot be
used to pull up a 3-stated output,
use an external resistor instead.
Bidirectional buses are limited
to the length of one Horizontal
Longline. There is no way to interconnect bidirectional buses. There
is no pass-transistor between the
buses, and two back-to-back amplifiers would latch up.
lOB flip-flops and latches can
be reset only by the global RESET
package pin that resets every flipflop and latch on the chip. Clock
polarity is determined at the
sources of the lOB clock line, not
at each individual lOB.
lOB latches driven from the
same clock line as a flip-flop have
a surprising latch enable polarity:
Active Low latch enable if the flipflop clocks on the rising edge; active High latch enable if the
flip-flop clocks on the falling edge.
This enable polarity must be specified explicitly to avoid a "fatal DRC
error".
The two flip-flops in a CLB
cannot have separate clocks, clock
enable or asynchronous reset inputs. The global clock distribution
network cannot be used for anything else but driving CLB and
lOB clock inputs. The alternate
clock network, however, has limited access to the general-purpose
interconnects.
PA
Volatility
Xilinx FPGAs use latches to
store the data determining logic
configuration and interconnects.
Configuration information is written into these latches after power
has been applied to the device, or
whenever a re-configuration is initiated. Obviously, all configuration
information is lost if power is interrupted. Some users have voiced
concern about this. Here is a detailed explanation.
Configuration informationremains valid provided Vcc stays
>2.0 V. XC3000 and XC4000 devices, however, have an internal
sensor that detects a Vcc drop beIowa critical value (-3 V). Even
though the configuration is valid
when that trip point is reached,
the device goes into shut-down
mode where it 3-states all outputs
and clears the configuration
memory, preparing it for a reconfiguration when Vcc returns to a
more normal value.
There is no possibility of a Vcc
dip causing the device to malfunction, i.e., to operate with erroneous configuration information.
• If Vcc stays above the trip point,
the device functions normally,
albeit at reduced speed, like any
other CMOS device.
• If Vcc dips below the trip point,
the device 3-states all outputs
and waits for reconfiguration.
Some users feel uncomfortable
with logic and interconnects defined by the content of latches.
There is a concern about accidental or spontaneous changes. Xilinx
designers have addressed these
concerns. The Xilinx configura tion
storage latches are simple and rugged, far more rugged than the
latches used in typical SRAMs.
Xilinx configuration latches
consist of cross-coupled inverters
9-19
with active pull-down n-channel
and active pull-up p-channel transistors. The High and the Low level
are thus both defined with active
devices, each having an impedance of -5 kil. Typical SRAMs use
passive polysilicon pull-up resistors with an impedance of about
5,000 Mil. A current of one
nanoamp (!) would be sufficient
to upset the typical SRAM cell,
whereas it would take a million
times more current to upset the
Xilinx configuration latch.
This does not mean that
SRAMsareunreliable,itjustshows
that the levels in Xilinx configuration latches are six orders of magnitude more resistant to upsets
caused by external events, like cosmic rays or alpha particles. Xilinx
has never heard about any occurrence of a spontaneous change in
the configuration store in any of
the 19 million LCA devices sold
over the past eight years.
Xilinx production-tests the
Vcc-dip tolerance of all XC3000
devices in the following way.
• After the device is configured,
Vcc is reduced to 3.5 V, and then
raised back to 5.0 V. Configuration data is then read back and
compared against the original
configuration bit stream. Any
discrepancy results in rejection
of the device.
• Subsequently, Vcc is reduced to
1.5 V and then raised to 5.0 V.
The device must first go 3-state,
then respond with a request for
re-configuration.
Both these tests are performed at
high temperature (> 70·C for commercial parts, >12S·C for military).
Any part failing any of these tests
is rejected as a functional failure.
PA
I
270-MHz Presettable Counter in XC3000
Prescaling is an established
technique for high-speed counters.
Using a derivative of this technique, LCA devices can implement
a presettable counter at the full
270-MHz max toggle rate of the
new XC3100-3. These counters can
be up to 24-bits long.
In a prescaler counter, a small,
very fast counter divides the clock
rate. The divided clock is provided
to a large, slower counter that is
unable to settle at the fast clock
rate. However, even when implemented synchronously, a conventional prescaler counter cannot be
loaded; the technique depends
upon the predictable binary sequence to ensure that the larger
counter has adequate settling time.
If the prescaler counter is
loaded with an arbitrary value,
Excessive Idle Power in XC2000
Some users report a quiescent
Icc consumption of more than 10
rnA in the XC2000 family. This is
usually the result of floating input
pads, especially unbonded ones,
and it can be fixed quite easily.
While the XC3000 and XC4000
devices have default pull-up resistors on all inputs, the XC2000 family lacks this option. Each unused
pin or pad must, therefore, be
forced to a valid logic level, either
by an external connection or resistor, or by using its own output
driver. The Makebits TIe option
does not take care of this, it only
ties internal inputs and interconnects to a defined logic level.
Users tend to overlook the
unbonded pads on XC2064 PC44,
XC20lB PC44 and XC201B PC6B.
These devices have more internal
pads than there are package pins
available. Some pads are, therefore, left unbonded, but these
unbonded inputs must also be
forced to a valid logic level. Otherwise they might cause uncontrolled power consumption, and
even uncontrolled oscillations.
Unused outputs, bonded or not,
can be tied from the schematic diagram. To do this, create dummy
bidirectional pins using OBUFs,
IBUFs, and BPADs or UPADs, as
appropriate. Connect the OBUF
output directly to IBUF input. This
connection creates a tie circuit that
is an input-less latch with no input. After configuration, these tiecircuits attain an unspecified, but
well-defined logic level, and remain there, thus preventing the
input from floating.
In existing designs, tie-circuits
locked to unused pins can be added
to the schematic, which is then
recompiled using the previous
LCA file as a guide. In new designs, an appropriate number of
bonded-pin tie circuits included
in the schematic will automatically
be distributed among the unused
bonded pins.
TIe-circuits cannot be locked
to specific unbonded pins. However, if the correct number of
unbonded tie circuits are included
in the schematic, all unbonded
pads will be tied. TIe circuits may
also be added by editing the LCA
design in XDE.
Unused bonded outputs tied
in this way are active pins, and
cannot, therefore, be used as PCB
feedthroughs. However, unused
pins required as feedthroughsneed
not be tied in the LCA device, since
PA
they do not float.
LOC=P22
X3607
9-20
the binary sequence is broken, and
the settling time. of the larger
counter is no longer guaranteed.
To ensure an adequate settling
time, either the clock frequency
must be reduced significantly, or
the values tha t can be loaded must
be severely restricted.
To provide presettable
prescaler counters, John Nichols
of Fairchild Applications introduced a pulse:swallowing technique in 1970. It uses a
dual-modulo prescaler that can
divide the clock by 2n or 2n +l.
Twenty years later, Xilinx developed a variation of the pulseswallowing technique for use in
LCA devices. This technique,
called state-skipping, uses a dual
modulo prescaler that can divide
by 2n or 2n-l.
In a state-skipping counter, the
prescaler is not loaded. Instead,
the least significant bits of the load
value are used to initiate a correction counter that controls the
modulus of the prescaler. Consequently, the larger counter, that
contains the more significant bits,
always has at least 2n-1 clock periods in which to settle, even after a
load.
Typically, the minimum of
2n-1 clock periods between the load
and the first clock to the larger
counter is longer than is required.
To compensate, the prescaler operates with its shorter cycle until
any extra delay has been nullified.
This compensation is controlled
automatically by the correction
counter.
For example, in a counter using +7/ +B prescaler, the value
loaded might require the first clock
to the larger counter occur 5 clock
periods after the load. In this case,
the minimum 7-clock cycle period
of the prescaler delays the first
clock to the larger counter by two
periods.
To nullify this extra delay, the
prescaler continues dividing by 7
for a further two cycles, canceling
one clock period of the extra delay
each cycle. The third clock to the
larger counter occurs 21 periods
after the load, which is the same as
in a conventional counter (5 + 8 +
8 = 21 clocks). Once the compensation is complete, the prescaler returns to dividing by 8.
Clearly, the counter will operate in a non-binary manner while
the correction is being made. During this time, the counter skips a
state each cycle of the prescaler,
hence the name of the technique.
The maximum time to complete
the correction is 2n-1 cycles of the
prescaler. A further consequence
of state-skipping is that some small
division ratios cannot be used,
because the correction cannot be
completed within the period of
the counter. In addition, the load
must be synchronized with the
prescaler cycle. This happens automatically if the counter is loaded
when it reaches TC. This is common practice for timers and dividers, which are excellent application
for state-skipping counters. With
these exceptions, a state skipping
counter may be loaded exactly like
a conventional binary counter.
There is no need to modify the
load value required for any given
divide ratio, as is necessary with a
pulse-swallowing counter. One
advantage of the state skipping
technique that is peculiar to LCA
implementation, is that a +3/+4
prescaler can be built in a single
CLB. This is the key to the 270MHz presettable counter, shown
in the figure. The counter uses two
state-skipping prescalers in cascade. Each is a 2-bit dual-modulo
prescaler that divides by 3 or 4,
and each has its own correction
counter_ Only the first prescaler is
clocked by the high-speed clock.
The maximum clock rate to the
remainder of the counter is at least
three times slower.
The first prescaler is implemented in a single CLB, and the
counter design allows the control
inputs several clock cycles to set
up. Consequently, the high-speed
clock is limited only by the toggle
rate of the flip-flops in this CLB. In
an XC3100-3 this is 270 MHz.
The remaining counters, including the first correction counter,
are all clockedbyQr Thissynchronous operation permits the correction counters and Q 4 - Q23 to be
loaded by Terminal Count in a
conventional way.
In each cycle of the second
prescaler, only one of the three or
four first-prescaler cycles can be a
correction cycle. Consequently, the
divide ratios of the composite
prescalet are limited to 11,12,15
and 16, depending on which
prescalers are correcting. This gives
the Q4 - Q23 counter at least 11
clock cycles in which to settle, and
distribute the parallel enable
signal.
Each time a prescaler correction cycle occurs, the corresponding correction counter is
decremented. Correction cycles
continue while the correction
counters are non-zero. When zero
is reached in either of the correction counters, the corresponding
prescaler ceases correcting, and
that correction counter remains at
zero until it is reloaded.
Correction can take up to 45
clock periods to complete, and
during this time some counter values will be skipped. However, the
counter behaves in a conventional
binary manner after less than 46
clock cycles. Some divide ratios
below 30 cannot be used, since the
correction time is greater than the
counter period, but all divide ratios of 30 or greater are available.
State-skipping counters are
the subject of an upcoming series
of Applications Notes. Design files
for the 24-bit 27D-MHz Presettable
Counter are available as XAPP021.
BN
PoPl
1
1ST PRESCALER
150
MHz
-~ +3/+~1
~
I
1
2ND PRESCALER
1-
PECORR. TC
COUNTER
""'"
+3/+4
t
•
I·
I rOOM
mh 1,+
I "
COUNTER
""'"
°4-°23
I
!
I
00 (37.51SO MHz CU<)
CEP
27D-MHz Counter
9-21
X2552
Donlt Drive
Mode Pins
Faster Multiplexers in XC3000
We recently debugged a design with unpredictable power-up
behavior. The designer had used
an Altera EPLD device to control
the MO, Ml, M2, and PWRDWN
pins of an XC3042. (MO and Ml
were used for readback. We don't
know why an EPLD powerhog was
used to control the LCA power.)
Upon power-up, the EPLD
puts uncontrolled signals on its
outputs, lasting for up to 100 InS.
That's long enough to make the
XC3042 configure in the wrong
mode, become a master instead of
a slave, thus crashing the system.
Remember, a Low on PWRDWN
causes all inputs, including RESET to be interpreted as High.
Connecting external logic to
the mode and PWRDWN inputs
of an LCA must be done with care
and a thorough understanding of
power-up conditions. Xilinx
FPGAs have been carefully designed to avoid erroneous output
signals during power-up. Other
ICs are not necessarily that friendly.
PA
The traditional building block
for large multiplexers in XC3000 is
a dual2-input MUX. This building
block comprises two functions of
three variables, and uses all five
inputs to the CLB. A 4-input MUX
cannot be constructed in a single
CLB since it requires six inputs.
UsingtheduaI2-inputMUX,larger
multiplexers can be constructed
using a conventional tree approach, with each select bit associated with one CLB level. This
results in 8:1 multiplexers that use
four CLBs in three levels, and 16:1
multiplexers that use eight CLBs
in four levels. However, a 3-input
MUX can be implemented in only
one CLB. Such 3-input MUXs can
implement larger multiplexers that
have less delay, while retaining
the binary encoding of the select
lines. The 8:1 multiplexer, shown
below, also provides an enable input. Again, four CLBs are used,
but with only two levels of delay.
The enable input permits the multiplexer to be expanded using only
one additional level of CLBs. De
coded select lines are used to enable up to five 8:1 multiplexers
into an OR gate. In this way, 3level multiplexers with up to 40
inputs may be constructed. For 16:1
multiplexers, the second design
uses eight CLBs, and again has
three levels of delay. It also has
binary-coded inputs, and uses
fewer CLBs than two 8:1 multiplexers with the necessary expansion logic.
BN
3 Levels
8CLBs
Binary Encoded
Select Lines
Ou1put
Ou1put
So-+~r-.....,
S,
13
-+"f+--'---'
1'5------'
2 Levels
4CLBs
Binary Encoded
Select Lines
X2550
o
X2549
8:1 Multiplexer
16:1 Multiplexer
9-22
LCA Output Characteristics
Here are the first results of our
output characteristics plotting.
Note that one device always
represents a whole family, there is
nodifferencebetween,e.g.,XC3142
and XC3190 outputs.
Note that the XC4000 has nchannel-only outputs that do not
drive any current above 3.5 V.
When pulling a Low output
slightly below Ground, or a High
output slightly above Vcc, the out-
put impedance is the same as it is
on the other side of Ground and
Vcc, i.e., the plot shows a straight
line going through Ground and
Vcc. ( The current direction
changes, of course. )
When the voltage exceeds 0.5
V below Ground or 0.5 V above
Vcc, the protective diodes become
conductive, and the current increases dramatically. That's why
we should not specify a max volt-
Sink Current and Output Low Impedance
Device
1V
XC2018
XC3020
XC3142
XC4005
70
55
35
42
,
2V
Source Current and Output High Impedance
1m edance
4V
3V
2V
Impedance
140
200
300
230
-30
-35
-35
0
-52
-60
-60
-7
-65mA
-75mA
-73mA
-30mA
350
300
300
400
>l00mA
100mA
63mA
85mA
V
100
90
/
-L
J ....
age excursion, but rather a max
current excursion into the forbidden territory below ground and
above Vcc.
This is true for all devices.
Even XC4000 outputs have a
strong clamp diode against Vcc.
Disregard previous statements to
the contrary.
All measurements at25'C and
Vcc=5.00V
All parts are 1993 production
type.
PA
80 ..
:-'..........
70
1·········+·····..,
.... I··:~·::·:.·r·.·-···r·····"":·.!'-..I~"'
. . . . . ..:---.'
. .-.-.. . . . . . .;...._......•.............!.--...i
mA
60
50
:=-L;~"I. _l~~Oi-._::~~~
1:
···1'············_·1\
3
)(3573
40
30
10 .
0
4
X30"
VOlTS
2
3
4
5
VOlTS
100
90
90
80
70
70
60
rnA
rnA
50
60
50
40
40
30
30
I
20
10
0
)(3575
0
VOLTS
X3578
9-23
VOlTS
Linear Feedback
Shift Register Counters
Conventional binary counters
use complex or wide fan-in logic
to generate high end carry signals.
A much simpler structure sacrifices the binary count sequence,
but achieves very high speed with
very simple logic, easily packing
tvV'o bits into every CLE. Linear
Feedback Register(LFSR)counters
are also known as pseudo-random
sequence generators.
An n-bit LFSR counter can
have a maximum sequence length
of 2n-1. It goes through all possible
code permutations except one,
which is a lock-up state. A maximum length n-bit LFSR counter
consists of an n-bit shift register
with an XNOR in the feedback
path from the last output Qn to the
first input Dl. The XNOR makes
the lock-up state the all-ones state;
an XOR would make it the allzeros state. For normal Xilinx applications, all-ones is preferred,
since the flip-flops wake up in the
all-zeros state.
The table below describes the
outputs that must drive the inputs
of the XNOR Amutli-inputXNOR
is also known as an even-parity
circuit. Note that the connections
described in this table are not necessarily unique. Due to the symmetry of the shift register operation
and the XNOR function, other connections may also result in maximum length sequences.
Examples
• A 10-bit shift register counts
modulo 1023, if the input Dl is
driven by the XNOR of Q10 and
the bit three positions to the left
(Q7), i.e. a one is shifted into Dl
when Q10 and Q7 have even
parity, which means they are
identical.
• An 8-bit shift register counts
modulo 255 if the input Dl is
driven by the XNOR of Q8, Q6,
Q5, Q4, i.e., a one is shifted into
Dl if these four outputs have
even parity, (four zeros, or two
ones, or four ones).
r - - D,
1>0,
10-Blt Shift Register
07
0'0
II I I I I I I
~____-a~,(~r_____
X2554
PA
n
XNOR Feedback from Outputs
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
3,2
4,3
5,3
6,5
7,6
8,6,5,4
9,5
10,7
11,9
12,6,4,1
13,4,3,1
14,5,3,1
15,14
16,15,13,4
17,14
18,11
19,6,2,1
20,17
21,19
22,21
23,18
24,23,22,17
25,22
26,6,2,1
27,5,2,1
28,25
29,27
30,6.4,1
31,28
32,22,2,1
33,20
34,27,2,1
35,33
36,25
37,5.4,3,2,1
38,6,5,1
39,35
40,5.4,3
Master & Slave
Configure
Together
All LCA users should know
that daisy-chained devices automatically finish configuration together, and become active
simultaneously. Each device
counts all CCLK pulses, and each
device has its own identical copy
of the common length countvalue.
When the number of CCLK pulses
received equals this value, all devices in the daisy chain start up
together. After a certain number of
CCLK pulses, as determined by
configuration options, all DONE
pins go High, all RESETs are released, and all outputs go active
simultaneously. This CCLK-driven
synchronous start-up is automatically performed by the configuration control logic.
This information is not new,
we only repeat it here because we
got some phone calls that showed
unnecessary concern on the part
of the user.
PA
9-24
Legal Protection for Configuration
Bit-Stream Programs
The bit-stream program
loaded into the LCA may qualify
as a "computer program" as defined in Section 101, TItle 17 of the
United States Code, and as such
may be protectable under the copyright law. It may also be protectable
as a trade secret if it is identified as
such. We suggest that a user wishing to claim copyright and/or
trade secret protection in the bit
stream program consider taking
the following steps.
1. Place an appropriate copyright
notice on the LCA device or
adjacent to it on the PC board to
give notice to third parties ofthe
copyright. For example, because
of space limitations, this notice
on the LCA device could read
"©1992 XYZCompany" or, if on
the PC board, could read "Bit
Stream © 1992 XYZ Company".
2. File an application to register
the copyright claim for the bitstream program with the U.S.
Copyright Office.
3. If practicable, given the size of
the PC board, notice should also
be given that the user is claiming that the bit-stream program
is the user's trade secret. Astatement could be added to the PC
board such as: "Bit-stream proprietary to XYZ Company.
Copying or other use of the bitstream program except as expressly authorized by XYZ
Company is prohibited."
4. To the extent that documentation, data books, or other literature accompanies the LCA
device containing the bit-stream
program, appropriate wording
should be added to this literature providing third parties with
notice of the user's claim of copyright and trade secret in the bitstream program. For example,
this notice could read: "BitStream © 1992 XYZ Company.
All rights reserved. The bitstream program is proprietary
to XYZ Company and copying
or other use of the bit-stream
program except as expressly
authorized by XYZ Company is
expressly prohibited."
5. To help prove unauthorized
copying by a third party, additional non-functional code
should be included at the end of
the bit-stream program. Therefore, should a third party copy
the bit-stream program without
proper authorization, if the non-
functional code is present in the
copy, the copier cannot claim
that the bit-stream program was
independently developed.
These are only suggestions and
Xilinx makes no representations
or warranties with respect to the
legal effect or consequences of the
above suggestions. Each user is
advised to consult legal counsel
with respect to seeking protection
of the user's bit-stream program
and to determine the applicability
of these suggestions to the user's
products and circumstances.
If the user has any questions,
contact the Xilinx legal department
at 408-879-4984.
BH
High Speed +3 Counter in One CLB
Some microprocessors require
a 2/3 duty cycle clock, most conveniently and reliably generated
by dividing a three times faster
crystal oscillator frequency by
three.
The design described below
uses one XC3000 series CLB to
generate a 1/3 High duty-cycle
signal on the X output, and a 2/3
High duty cycle signal on the Y
output. This is just one of many
possible implementations. Max
clock frequency is 100 MHz in a
-125 device.
PA
>
-
cp~
x~
v~
9-25
I
Anatomy of the EPLD Architecture
The XC7200 Architecture
The XC7200 devices provide
multiple Function Blocks (FBs) interconnected by a central Universal Interconnect Matrix (lJIMTM).
Each FB receives 21 signals from
the DIM and produces nine output signals to pins and back into
the DIM.
UIM
FB 1
of fan-in or fan-out loading. Because each FB has identical timing
characteristics and the UIM has a
constant delay, logic mapped into
the device has predictable performance, independent of placement
and routing. The UIM can also act
as one or more AND gates, e.g., to
form terminal count signals within
the interconnect. The following
diagram illustrates how 27
macrocelis can be configured to
implement a 27-bit synchronous
counter.
Arithmetic Logic Unit (ALU)
Unlike other programmable
logic arrays, the XC7200 architecture includes dedicated arithmetic
logic units and fast carry lines running directly between adjacent
macrocells and Function Blocks.
This additional ALU enables the
XC7200 architecture to support fast
adders, sub tractors, and magnitude comparators of any length
up to 72 bits. Tne following diagram illustrates how 18 macrocells
(2 Function Blocks) can be programmed to implement an 18-bit
accumulator.
UIM
Simplified
XC7200 Architecture (n=4,8, ..)
Within each FB there are nine
macrocells, each driven by product terms derived from the 21 DIM
inputs. Each macrocell resembles
a 21V9 PLD architecture. In addition, each macrocell includes an
Arithmetic Logic Unit (ALU) that
can generate and propagate arithmetic-carry signals between adjacent macrocells and Functional
Blocks.
Universal Interconnect Matrix
Unlike other interconnect techniques, Xilinx EPLD's Universal
Interconnect Matrix (UlM) provides 100 % interconnectivity. Any
output of any Function Block can
be connected to any input or any
number of inputs of any other
Function Block using the DIM. The
patented interconnect scheme of
the DIM provides a fast uniform
delay through any of its paths.
This interconnect is independent
)(2027
27-bit Synchronous Counter
Implemented Using
UIM AND Gates
Consistent timing performance for all on-chip signals
greatly simplifies the design process. In addition to interconnection, the UIM is also used for the
following functions:
• Emulating 3-state buses
• Enable/disable signal gates
• Logic decoders
• DeMorgan OR gates
9-26
18-bit Accumulator
Implemented using ALU Chain
The above architectural features introduce innovative systems-oriented enhancements to the
classical features of the PAL-like
CPLD architectures. This favors
the implementation of fast state
machines, large synchronous
counters and fast arithmetic, as
well as multi-level general-purpose logic.
DR
Dynamic Power Consumption
It is impossible to give a max
value for LCA power consumption, because it is totally dynamic.
The power consumption of any
node is proportional to its capacitance multiplied by the frequency
at which it is charged and discharged between +5 V and ground.
To determine total power, you
must know the capacitance of each
node and clock line inside the chip,
and the frequency with which it is
moving up and down; and, you
must know the external capacitive
load and its frequency.
A worst-case maximum number would be very high, and therefore meaningless, because nobody
designsasystem where every node
moves at 60 MHz, for example.
Estimating power consumption usually has one of two goals:
Thermal reliability evaluation, or
power-supply sizing.
Thermal calculations can often be substituted by rough estimates, since CMOS power is so
low. We give e }A values for each
package, describing the thermal
impedance, i.e. the temperature
rise in ·C per Watt of power dissipation. Assuming a very conservative max junction temperature
of 14S·C, a max ambient temperature of 60·C, and a e A of 30·C/W
gives a max allowable power dissipation of 2.8 W. Very few LCA
designs consume that amount of
power, most use a few hundred
milliwatts, whi.ch results in a junction temperature only a few degrees above ambient.
LCA devices are usually not
the dominating power consumers
in a system, and do not have a big
impact on the power supply design. There are, of course, exceptions to these general rules, and
the designer should then use the
data on this page to estimate power
consumption more accurately. PA
Here are the results of recent measurements of the dynamic power
consumption in various Xilinx devices.
The Applications section of our Data Book describes the same
parameters, but those values were based on 1988 measurements of
devices with larger geometries.
XC2018 at 5.0 V
One CLB driving 3 local interconnects O.22mW /MHz
One device output with a SO pF load 2.0mW /MHz
One Global clock buffer & line
3.2mW /MHz
XC2018 at 3.3 V
One CLB driving 3 local interconnects 0.1 mW = 0.03 rnA/MHz
One device output with a SO pF load 0.8 mW = 0.35 rnA/MHz
One Global clock buffer & line
1.0 mW = 0.3 rnA/MHz
XC3020
One CLB driving 3 local interconnects
One device output with a SO pF load
One Global clock buffer & line
One Longline without driver
0.2SmW /MHz
1.2SmW /MHz
2.0mW /MHz
O.lmW /MHz
XC3020L at 3.3 V
One CLB driving 3 local interconnects
One device output with a SO pF load
One Global clock buffer & line
One split Longline without driver
0.1 mW /MHz = 0.03 rnA/MHz
0.5 mW /MHz = 0.15 rnA/MHz
0.8 m W /MHz = 0.25 rnA/MHz
O.04mW /MHz=O.OlrnA/MHz
XC3090
One CLB driving 3 local interconnects
One device output with a SO pF load
One Global clock buffer & line
One split Longline without driver
0.25mW /MHz
1.25mW / MHz
3.5mW /MHz
0.15mW /MHz
XC4003
One CLB driving 3 local interconnects
One device output with a SO pF load
One Global clock buffer & line
One split Longline without driver
0.30mW /MHz
1.2mW /MHz
1.9mW /MHz
0.12mW /MHz
XC4005
One CLB driving 3 local interconnects
One device output with a SO pF load
One Global clock buffer & line
One split Longline without driver
0.30mW /MHz
1.2mW /MHz
3.2mW /MHz
0.17mW /MHz
XC401 0
One CLB driving 3 local interconnects
One device output with a 50 pF load
One Global clock buffer & line
One split Longline without driver
9-27
0.30mW /MHz
1.2mW /MHz
5.1mW /MHz
0.24mW /MHz
I
PC-Board Design Hints for LCA Users
Twenty years ago, CMOS was
hailed as the friendliest form of
logic: no input current, full rail-torail logic swing, high noise immunity, soft edges, low power
consumption, tolerance for large
Vcc variations, etc.
Things have changed. CMOS
devices have lost some of their
user-friendliness as they have become faster and faster, partly in a
deliberate quest for speed, partly
as an unavoidable result of the
smaller device geometries that are
required to lower manufacturing
cost. The output edge rate is now
faster than for TIL, and PC-board
interconnect lines between modern CMOS devices can no longer
be treated a short circuits or
lumped capacitances. The CMOS
0.062" Board
Zo Width
C
0.031 Board
Width
C
H
(0)
(mils)
(pF/ft)
(mils)
(pF/ft)
50
60
70
80
90
100
103
77
57
42
31
23
35
29
25
22
20
18
47
35
26
19
14
10
31
27
23
20
18
16
Imperial units
1.6 mm Board 0.8 mm Board
Width
C
C
Zo Width
(0)
50
60
70
80
90
100
(mm) (pF/cm)
2.6
2.0
1.4
1.1
0.8
0.6
1.15
0.95
0.82
0.72
0.66
0.6
(mm) (pF/cm)
1.2
0.9
0.65
0.5
0.35
0.25
1.02
0.88
0.75
0.66
0.59
0.52
Metric units
Microstrip-Line Impedance
and Capacitance per Unit Length
designer must now cope with the
same transmission-line effects that
concerned the previous generation
of designers using Schottky-TIL
or ECL devices.
Here are some basic rules.
Rule 1: Any PC-board trace is
really a transmission line with distributed capacitance and inductance. The series resistance is
usually unliTlportant. 11le table at
left lists typical values for the capacitance and inductance of a PCboard trace with a ground-plane
below it.
Any voltage change on such a
transmission line causes a correspondingcurrentchange. The voltage-to-current ratio is called the
characteristic impedance, 20 . It is
determined by the line thickness
and width, by the distance to the
ground plane, and by the dielectric constant E of the PC- board
material. 20 is independent of line
length. The table shows typical values for popular constellations.
Rule 2: Signals travel along a
transmission line at roughly half
the speed oflight, or 6" (15 cm) per
nanosecond. More precisely, the
true propagation speed is the freeair speed of light divided by the
square root of the effective dielectric constant, E. The speed of light
is very close to 12" ( 30 cm ) per
nanosecond, and E for typical epoxy material is 4.7. Since some of
the electric field passes through
air, the effective E is closer to 4,
which leads to the rule of
thumb,"half the speed of light".
Rule 3: Whenever the one-way
propagation time along a wire or
PC trace is longer than half the
rise or fall time of the driving
signal, this wire or trace must be
considered a transmission line, not
a lumped capacitive load.
9-28
If the rise- orfall-time is 1.5 ns,
any PC-board trace longer than
4.5 inches (llcm) must be analyzed
for transmission-line effects.
If the rise or fall time is 5 ns,
only PC-board traces longer than
15" ( 38 em ) need to be analyzed
for transmission-line effects.
When a fast rising edge is being driven onto a long transmission line, the driver sees the
characteristic impedance Zo ( 50 to
150 0), and generates a voltage
step that is determined by the ratio
of output impedance, Ri, to Zoo
Typically, an LCA device with an
output impedance of 60 0 drives
a 3.5-V step onto a 100-0 line.
This step propagates to the end
of the line at a speed of 6" (15 cm )
per nanosecond. If the far end is
left open or has a light capacitive
load, e.g., the input to a CMOS
device, a reflected wave is superimposed on the incoming wave,
since only an equal-amplitude reflected wave satisfies the zero-current requirement at the end of the
line. This reflected wave travels
back to the signal source, arriving
therewith almost double the original amplitude, usually well above
Vcc. If the output impedance of
the driver differs from 20, the incoming wave is again reflected,
travels to the far end, where it is
reflected again, etc. This series of
reflections with decreasing amplitude is commonly called "ringing". Theoretically, these are
rectangular steps of alternating
and decreasing amplitude, but
high-frequency imperfections often give it the appearance of a
decaying sine wave.
At best, such reflections result
in poor signal quality and loss of
noise immunity. At worst, they
reduce system performance and
cause functional failures due to
double clocking.
Coping with Transmission
Line Effects
Parallel Termination, Figure 2.
A transmission line of arbitrary length can be terminated at
the far end by a resistor to ground
or Vcc. If this resistor equals the
characteristic impedance Zo, the
driver always sees the transmission line like a lumped resistive
load. Any signal driven onto the
line travels to the far end and is
dissipated in the resistor. There is
no reflection, no ringing or overshoot. Unfortunately, this type of
termination is usually impractical, because it puts undue current
and power requirements on the
driver. It requires 100 rnA to drive
a 5 V signal onto a 50 n line. Only
ECL circuits or special buffer circuits can drive terminated transmission lines conveniently. There
are two popular methods to alleviate the problem.
• Connecting the terminating resistor through a fairly large capacitor to ground instead of
directly to ground or Vcc, reduces static power consumption, but introduces a time
constantthatmust be tailored to
the system speed.
• Terminating the line with two
resistors, one to ground and one
to Vcc, reduces the peak current-requirement. 300 n to Vcc
and 150 n to ground is· the
Thevenin equivalent of a 100 n
termination to 1.6 V.
Series Termination, Figure 3.
In some cases, series termina-
tion at the source can offer the
benefits of termination without the
drawbacks mentioned above.
When an additional series-resistor between the driver and the line
increases the effective drive impedance to the same value as Zo,
the transmission line receives a
starting step of half amplitude.
Adding an external 40-n resistor
to the 60-n LCA output impedance matches the 100-n transmission line, and drives it with a 2.5-V
step. This step travels to the far
end, where it is reflected and thus
doubled in amplitude, as described
above. It then arrives back at the
driven end of the line with full
amplitude ( 5 V ), and is not reflected, since it sees a terminating
resistor that is equal to Zoo
This seemingly ideal solution
has one big drawback: A half-amplitude voltage step travels along
the trace and back. Everywhere
along the line, except at the far
end, this half-amplitude signal can
cause trouble, especially in the vicinity of the driver. Series termination is, therefore, recommended
only for signals that go from a
single source to a single destination. Taps on a series-terminated
have half-amplitude (2.5 V ) levels for fairly long times, which
means poor noise immunity and
potential malfunction.
Practical Rules
• Use slew-rate limited outputs
wherever possible. Their longer
rise and fall times eliminate
transmission line effects for all
short interconnects.
• Keep critical interconnects as
short as possible. It may be better to duplicate some logic in the
LCA device and drive from different sides of the device, if that
shortens the PC-board traces.
• Use multi-layer PC boards with
ground and Vcc planes whenever possible. Always connect
all Vcc and ground pins, and be
generous with Vcc decoupling
capacitors, 0.1 J.LF per Vcc pin.
• Use series termination for lines
that drive a single or lumped
destination, but never put taps
on a series-terminated line.
• In synchronous systems, the synchronous data and control lines
can tolerate poor signal quality
after the clock edge, but all asynchronous inputs, and especially
all clock inputs need good signal quality all the time.
• Pay attention to clock distribution on the PC board. Low-skew
drivers are now available, e.g.,
the NSC CGS74C2525.
• CMOS-level input threshold offers the best noise immunity.
(Not available on XC40(0).
• Remember that a low clock frequency does not make the circuits slow. When the system
clock rate is very low, the flipflops inside the LCA device can
still react to 2-ns clock spikes.
PA
Vee
LeA
LeA
~y
=Zo
Ai~--~---------
LeA
300 0
>-
Destination
ZO=1oo0
Ai~~---------1
Outgoing Wave
. - Aefiec1ed Wave
1500 ;..
Ai
~_~
Zo
R=
ZO-Ri
X2817
X2B15.
X2816
Fig. 1. Transmission Line
Fig. 2. Parallel Termination
9-29
Fig. 3. Series Termination
I
Crystal-Oscillator Considerations
There are two reasons why
many designers feel uncomfortable using the on-chip LCA crystal
oscillator circuit.
• This is analog territory, unfamiliar to many digital designers. Words like reactance
transconductance, gain, dB,
phase response, j roL and s-plane
evoke memories of long-forgotten early college classes.
• IC documentation is usually
skimpy on the issue of specifying crystals and designing reliable oscillator circuits.
Here is additional information.
Let's start with some fundamental
facts. There is nothing Xilinx-specific about the oscillator circuit.
It's a wide-band inverting amplifier, as used in all popular
microcontrollers, like the 8051.
When a crystal and some passive
components close the feedback
path, as shown in our Data Book,
this circuit becomes a reliable and
stable clock source.
The path from XTAL2 to
XTAL1 inside the LCA device
(strangely enough, XTAL2 is the
input, XTALl is the output) is a
single-stage inverting amplifier,
which means it has a low-frequency phase response of 180·,
increasing by 45· at the 3-dB frequency.
Input impedance is 10-15 pF,
input threshold is CMOS; but de
bias must be supplied externally
through a megohm resistor from
XTALl to XTAL2.
Low-frequency gain is about
20, rolling off 3dB at 125 MHz.
Output impedance is between
50 and 100 n and the capacitance
on the output pin is 10 to 15 pF.
Pulse response is a delay of
about 1.5 ns and a rise I fall time of
about 1.5 ns.
For stable oscillation,
• the loop gain must be exactly
one, i.e., the internal gain must
be matched by external a ttenuation,and
• the phase shift around the loop
must be 360· or an integer multiple thereof. The external network must, therefore, provide
180· of phase shift.
Inductiv~
jrnL
A crystal is a piezoelectric mechanical resonator that can be
modeled by a very high-Q series
LC circuit with a small resistor
representing the energy loss. In
parallel with this series-resonant
circuit is unavoidable parasitic
capacitance inside and outside the
crystal package, and usually also
discrete capacitors on the board.
The Lmpedance as a function
of frequency of this whole array
starts as a small capacitor at low
frequencies (Figure 1). As the frequency increases, this capacitive
reactance decreases rapidly, until
it reaches zero at the series resonant frequency.
At slightly higher frequencies,
the reactance is inductive, starting
with a zero at series resonance,
and increasing very rapidly with
frequency. It reaches infinity when
the effective inductive impedance
of the series LC circuit equals the
reactance of the parallel capacitor.
The parallel resonance frequency
is a fraction of a percent above
the series-resonance frequency.
Over this very narrow frequency range between series and
parallel resonance, the crystal impedance is inductive and changes
all the way from zero to infinity.
The energy loss represented by the
series resistor prevents the impedance from actually reaching zero
and infinity, but it comes very close.
:Parallel
'Resonance
f---":7.""""'-----!-----.. Frequency
jrnC
ca~citive
---------~
X2818
Figure 1. Reactance as a Function of Frequency
9-30
~--- _ _ _ _ _ _ I
X2835
Figure 2. Equivalent Circuit
Microprocessor- and FPGAbased crystal oscillators all operate in this narrow frequency band,
where the crystal impedance can
be any inductive value. The circuit
oscillates at a frequency where the
attenuation in the external circuit
equals the gain in the LCA device,
and where the total phase shift,
internal plus external, equals 360'.
Figure 3 explains the function.
At the frequency of oscillation, the
seri.es-resonant circuit is effectively
an mductor, and the two capacitors act as a capacitive voltage divider, with the center-point
grounded. This puts a virtual
ground somewhere along the inductor and causes the non-driven
end of the crystal to be 180' out of
phase with the driven end, which
is the external phase shift required
for oscillation. This circuit is commonly known as a Pierce oscillator.
XC2000/xC3000
Practical Considerations
• The series resonance resistor is a
critical parameter. To assure reliable operation with worst-case
crystals, the user should experimentwithadiscreteseriesresistor roughly equal to the max
internal resistance specified by
the crystal vendor. If the circuit
tolerates this additional loss, it
should operate reliably with a
worst-case crystal without the
additional resistor.
• The two capacitors affect the frequency of oscillation and the
start-up conditions. The series
connection of the two capacitors is the effective capacitive
load seen by the crystal, usually
specified by the crystal vendor.
• The two capacitors also determine the minimum gain required for oscillation. If the
capacitors are too small, more
gain is needed, and the oscillator may be unstable. If the capacitors are too large, oscillation
is stable but the required gain
may again be higher. There is an
optimum capacitor value, where
oscillation is stable, and the required gain is at a minimum.
For most crystals, this capacitive load is around 20 pF, i.e.,
each of the two capacitors
should be around 40 pE
Figure 3. Pierce Oscillator
Sources
Series Resonant or Parallel Resonant?
Crystal manufacturers label
some crystals as series-resonant,
others as parallel-resonant, but
there really is no difference between these two types of crystals,
they all operate in the same way.
Every crystal has a series resonance, where the impedance of
the crystal is extremely low, much
lower than at any other frequency.
At a slightly higher frequency, the
crystal is inductive and in parallel
resonance with the unavoidable
• Crystal dissipation is usually
around 1 mW, and thus of no
concern. Beware of crystals with
"drive-level dependence" of the
series resistor. They may not
start up. Proper drive level can
be checked by varying Vcc. The
frequency should increase
slightly with an increase in V cc.
A decreasing frequency or unstable amplitude indicate an
over-driven crystal. Excessive
swing at the XTAL2 input results in clipping near V cc and
ground. An additional 1 to 2 kQ
series resistor at the XTALl output usually cures that distortion
problem. It increases the amplifier output impedance and assures additional phase margin,
but results in slower start-up.
• Be especially careful when designing an oscillator that must
operate near the specified max
frequency. The circuit needs excess gain at small signal ampli~des to supply enough energy
mto the crystal for rapid startup. High-frequency gain may
be marginal, and start-up may
be impaired.
• Keep the whole oscillator circuit physically as compact as
possible, and provide a single
ground connection. Grounding
the crystal can is not mandatory
but may improve stability.
stray capacitance or the deliberate
capacitance between its pins .
The only difference between
the two types of crystal is the
~an~facturer's choice of specifymg eIther of the two frequencies.
If series resonance is specified, the
actual frequency of oscillation is a
little higher than the specified
~alue. Ifparallel resonance is specifIed, the frequency of oscillation is
a little lower. In most cases, these
small deviations are irrelevant.
9-31
Fick: "Schwingquarz und
Mikroprozessor". Elektronik, Feb.
1987
Horowitz & Hill: The Art of Electronics, Cambridge University
Press, 1989
Motorola High-Speed CMOS Logic
Data Book., 1983.
PA
I
Two's Complementer Packs 2 Bits per CLB
The best known algorithm for
twos complementing a number is
to invert all the bits and then add
one to the result. Using this algorithm, only one data bit can be
generated by each XC3000 CLB,
since the increment operation requires an additional carry output
for each bit. However, an alternate
empirical algorithm exists that
does not have this iimitation, and
generates two bits per CLB.
This alternate algorithm permits the two's complement of a
number to be determined by inspection.Asshownintheexample,
the number is scanned, one bit at a
time, from the least significant end,
until the first" one" is encountered.
The first "one" and any less significant zeros are passed to the
output unchanged. All more significant bits are inverted.
This algorithm may be rewritten in an iterative form: a bit is
inverted only if its less Significant
neighbor is inverted, or is a one.
Trailing zeros and the first "one"
are not inverted because their less
significant neighbors are neither
inverted nor "ones". The bit after
the first "one" is inverted because
its neighbor is a "one", and the
remaining bits are inverted because their neighbors were .
This may be implemented as
shown in Figure 1. The inputs and
outputs of the less significant
MSB
1 0
1
1
o
!
1
one delay per bit-pair. This doubles
the performance of the original
design, without increasing the
number of CLBs required or the
routing complexity.
A further modification, not
shown, permits the delay for an 8bit complementer to be reduced to
two CLBs. However, one additional CLB is required. In this
design, complementers larger than
eight bits use two additional CLBs
per three bits, and the delay increases by one CLB per three bits.
",---1~---------~-0UT,
O N , - + r - - - - - - - - - /I'-"
OUT,
.., - . t - - - - - - - - - /I ' - "
OUT,
. . , - - h r - - - - - - - - - /J'-"
OUT,
O N , - . t - - - - - - - - - /J'-"
•
•
X357'
Figure 1. Simple Two's Complementer
ON, ----l~--l--==-----JL.rtt- OUT,
First ·1·
tnput
neighbors are inspected to determine their value and whether they
were inverted. An XOR is then
used to invert the data according
to the rule described above.
The least significant bit always
remains unchanged when two's
complementing a number. Consequently, no logic is required by the
LSB and no less significant neighbor is required.
Figure 2 shows a modification
of the 2-bit CLB that only incurs
o
lSB
0
...Scan
Invert
Output
Pass
1
0
Two's Complement Example
0
Figure 2. Faster Two's Complementer
9-32
SECTION 10
1
Programmable Logic Devices
2
FPGA Product Descriptions
3
EPLD Product Descriptions
4
Packages and Thermal Characteristics
5
Quality, Testing and Reliability
6
Technical Support
7
Development Systems
8
Applications
9
The Best of XCELL
10 Index, Sales Offices
Index, Sales Offices
Index .................................................................................
10-1
Sales Office Listing ............................................................................. 10-5
>• • • • • • • • • • • • • • • • • •
Index
ABEL ................................................................ 7-2, 7-34
ABEL, High-Performance Counter .......................... 8-62
Boundary Scan, Test Data Register ............ 8-27, 8-137
Boundary Scan, Test Access Port ............... 8-26, 8-137
Accumulator ................................................... 9-17,8-72
Boundary Scan, User Register ................................ 8-29
Accumulator, Pipelined ........................................... 9-95
Buffers, Clock .......................................................... 8-11
Adder ........................................... 8-72, 8-79, 8-90, 8-92
Bulletin Board ............................................................ 6-3
Adder, Conditional Sum .......................................... 8-78
Bus ........................................................................ 2-109
Adder, Look-Ahead Carry ....................................... 8-76
Bus Contention .. ,..................................................... 9-14
ALU .................................................................. 3-7, 3-44
Capacitive Load ...................................................... 8-10
ANDing in the UIM .................................................. 8-34
Carry (XC4000) ..................................................... 8-79
App Note Directory .................................................... 8-1
Carry Look-Ahead ................................................... 3-45
App Notes, Arithmetic ............................................... 8-3
CCLK ......................................................................... 9-2
App Notes, Counters ................................................. 8-1
CCLK Frequency Variation ..................................... 8-13
App Notes, General ................................................... 8-1
Characteristic Impedance ....................................... 9-28
App Notes, Miscellaneous ........................................ 8-4
Clear ................................................. 2-27, 2-113, 2-189
App Notes, Special Memory ...................................... 8-3
Clock Buffers ........................................................... 8-11
Architecture ( EPLD ) ..................... 3-5, 3-21, 3-42, 9-26
Clock Decoding ....................................................... 9-12
Architecture ( XC2000 ) ......................................... 2-179
Clock Frequency Doubling ........................................ 9-7
Architecture ( XC3000 ) ......................................... 2-100
Clock Gating ........................................................... 9-12
Architecture ( XC4000 ) ............................................. 2-9
Code Conversion, Serial ....................................... 8-129
Arithmetic Performance ( EPLD ) ............................ 8-93
Comparator .................................................... 9-16, 9-17
Arithmetic, Serial ..................................................... 8-72
Comparison XC4000 vs. XC3000 ............................. 2-8
Assembly Qualification .............................................. 5-5
Comparison XC4000H vs. XC4000 ......................... 2-82
Asynchronous CLB Preset ........................................ 8-6
Complementer ............................................... 8-86, 9-32
Asynchronous Design ...................................... 9-8, 9-12
Conditional Sum Adder ........................................... 8-78
Backup, Battery ....................................................... 8-15
Configuration Memory Cell .................................... 2-181
Barrel Shifter ......................................................... 8-119
Configuration Modes ......................... 2-25, 2-112, 2-188
Battery Backup ............................................ 2-191, 8-15
Configuration Pins ............................ 2-43, 2-132, 2-206
BCD Serial Converter ............................................ 8-129
Configuration State Diagram ............ 2-27, 2-113, 2-189
BIDI ............... 2-107, 2-148, 2-156, 2-164, 2-172, 2-184
Contention ............................................................... 9-14
Bi-directional Buffer ............ 2-107, 2-148, 2-156, 2-164,
2-172,2-184
Convolution Filter .................................................. 8-158
Copyright ................................................................. 9-25
Bitstream .......................................................... 8-20, 9-2
Counter ............................... 8-36, 8-86, 8-90, 9-20, 9-24
Boundary Scan .............................................. 2-22, 8-25
Counter, Custom Length ......................................... 8-69
Boundary Scan Availability ...................................... 8-29
Counter, Fast Loadable .......................................... 8-56
Boundary Scan Emulator (XC3000) .................... 8-136
Counter, Full-Featured ............................................ 8-60
I
Boundary Scan, Instruction Register ........... 8-27, 8-137
10-1
Index
Counter, High Performance ( ABEL) ...................... 8-62
ESD Protection ......................................................... 5-8
Counter, Loadable ......................................... 8-47, 8-56
F Mode ........................................................... 2-104, 8-6
Counter, Modulo N .................................................. 8-44
FAEs ......................................................................... 6-5
Counter, Presettable ............................................... 8-44
Fast Carry ............................................. 2-11,2-20,8-79
Counter, Ultra-Fast .................................................. 8-52
FastClock .................................................................. 3-7
Counter, Up/Down ................................ 8-42, 8-50, 8-86
FastCompare .......................................... 3-9, 3-25, 3-49
Counter, Gray, Excess Three ............................... 8-122
FastDecode ............................................................... 3-9
Cracking, Moisture-Induced .................................... 4-23
FastFunction Blocks ................................................ 3-42
CRC ............................................................... 2-26, 8-21
FG Mode ........................................................ 2-104, 8-6
Crystal Oscillator .......... 2-111, 2-117, 2-187, 8-13, 9-30
FGM Mode ..................................................... 2-104, 8-6
Daisy Chain ........................................................... 2-190
Field Applications Engineers ..................................... 6-5
Data Integrity ............................................................. 5-2
FI FO ( RAM-Based) ............................................. 8-113
Decoupling ............................................................ 2-129
FIFO ( Register-Based) .......................................... 8-96
Decrementer ........................................................... 8-86
FIFO Controller, Megabit ...................................... 8-132
Delay Path Specification ................................ 3-15, 3-32
FIT ............................................................................. 5-2
Delay Tracking .......................................................... 8-8
Frames ......................................................... 2-26, 2-114
Demonstration Boards ............................................ 7-37
Frequency Doubling .................................................. 9-7
Design Manager .............................. 2-16, 7-3,7-7,7-30
Frequency Synthesizer ......................................... 8-145
Design Security ....................................................... 9-15
Frequency/Phase Comparator .............................. 8-127
Die Qualification ........................................................ 5-5
FSK Modulator ...................................................... 8-145
Direct Interconnect ..................................... 2-107, 2-187
Function Blocks ............................................... 3-6, 3-23
Divide-by-Three ....................................................... 9-25
Function Generator Glitches ..................................... 9-5
Documentation .......................................................... 6-7
Function Generators ............................................. 2-103
Double-Length Lines ...................................... 2-15, 2-24
General-Purpose Interconnect ................... 2-1 05, 2-183
Download Cable ............................................... 7-2,7-36
Glitch-Free Sequencer .......................................... 8-111
DRAM Controller ................................................... 8-154
Glitches from Function Generators ........................... 9-5
Dry-Packing ............................................................. 4-23
Global Buffer ......... 2-24, 2-50, 2-67, 2-87,2-109, 2-148,
2-156,2-164,2-172,2-185
DS-35 ................................................................ 7-47-32
DS-290 .................................................................... 7-32
Global Set/Reset ..................................................... 2-31
DS-343 .................................................................... 7-32
Ground Bounce ....................................................... 9-10
DS-344 .................................................................... 7-32
Gun, Smoking ....................................................... 8-104
DS-371 ............................................................. 7-4,7-34
Header ......................................................... 2-26, 2-114
DS-380 .................................................................... 7-33
High Density Function Block ................................... 3-43
DS-390 ...................................................................... 7-4
Hold Time .................................................................. 9-7
DS-391 .................................................................... 7-32
HP 700 ........................................................... 7-26, 7-27
DS-401 .................................................................... 7-35
Hysteresis, Input ....................................................... 8-8
DS-502 .................................................................... 7-30
I/O Pin Count ............................................................. 4-1
DS-550 .................................................................... 7-31
IN Curves ...................................................... 9-23, 8-10
Electrostatic Discharge ............................................. 5-8
Idle Power ............................................................... 9-20
Erasure .................................................................... 3-47
IEEE 1149.1 ........................................ 2-22, 8-25, 8-136
Error Check ............................................................. 2-26
Incrementer ............................................................. 8-86
Input HystereSis ........................................................ 8-8
10-2
Input Rise/Fall Time .................................................. 8-8
Output Characteristics, Additional. ................. 8-1 0, 9-23
Input Set-up Time .................................................... 2-20
Output Enable ......................................................... 9-10
Input Threshold ............................... 2-102, 2-116, 2-191
Outputs (XC4000H ) ............................................... 2-83
Input Transition Time ............................................ 2-102
Overshoot .................................................................. 9-5
Integrity of Data ......................................................... 5-2
Package Integrity ...................................................... 5-5
JTAG ................................................... 2-22,8-25,8-136
Package Mass ( Weight) ........................................4-22
Latch-Up .................................................................... 5-8
Parallel Resonance ................................................. 9-31
LCD Driver .............................................................. 9-16
Parallel Termination ................................................ 9-29
Legal Protection ...................................................... 9-25
PC-Board Layout .................................................... 9-28
LFSR Counter ......................................................... 9-24
Phase Comparator ................................................ 8-127
Libraries, Macro ...................................... 2-16, 7-2, 7-32
Phase-Locked Loop .............................................. 8-127
Libraries, Symbol .................................... 2-16, 7-2, 7-32
Pipelined Accumulator ............................................ 8-95
Linear Feedback Counter ........................................ 9-24
Pipelined Carry ........................................................ 9-17
Liquid Crystal Driver ................................................ 9-16
PiPs ....................................................................... 2-105
Logic SyntheSis ................................................ 7-2,7-35
PLL ........................................................................ 8-127
Postamble ............................................................. 2-114
Longlines ........................... 2-15, 2-24, 2-50, 2-68, 2-88,
2-109,2-185,8-11
Power Consumption ...... 2-129, 2-203, 3-10, 3-26, 3-47,
8-12,9-15,9-20,9-27
Longlines, CLB Access ............................................. 8-7
Look-Ahead Carry Adder/Subtractor ....................... 8-76
Power Distribution ................................................. 2-128
Low-Power Option ................................................. 2-147
Power Management ....................................... 3-47, 3-49
Low-Voltage FPGAs .................................. 2-161, 2-215
Power-On Delay ............................... 2-27, 2-113, 2-189
Macro Libraries ....................................... 2-16, 7-2, 7-32
Powerdown ........................................... 2-129, 9-11, 9-1
Macrocell .......................................................... 3-6, 3-23
Prescaled Counter ......................................... 8-39, 9-20
Magic Box ................................ 2-14, 2-24, 2-105, 2-183
Product Terms ........................................ 3-6, 3-23, 3-43
Maghitude Comparator ........................................... 9-16
Programming Modes ........................ 2-25, 2-112, 2-188
MakeBits ................................................................... 9-2
Pulse-Skipping Counter .......................................... 9-20
Marginal Supply Voltage ........................................... 9-9
Quality, Average Outgoing ........................................ 5-1
Mass per Package .................................................. 4-22
RAM ........................ 2-13, 2-20, 2-54, 2-73, 2-91,8-101
Memory .............................. 2-13, 2-20, 2-54, 2-73, 2-91
RAM Timing .......................................................... 8-101
Memory Cell .......................................................... 2-181
Readback ......................... 2-31, 2-117, 2-191, 8-17, 9-2
Memory Cell Design .................................................. 5-7
Reflection ................................................................ 9-28
Mentor ...................................... 7-24 through 7-27, 7-32
Reliability ................................................................... 5-2
Metastable Recovery ....................................... 8-14, 9-8
Reprogram ................................................. 2-117, 2-190
MIL-STD-883 ............................................................. 5-2
Reset Recovery ....................................................... 8-11
Mixer ..................................................................... 8-157
Ripple Counter ........................................................ 9-12
Mode Pins ............................................................... 9-22
Ripple-Carry Adder/Subtractor ................................ 8-73
Moisture-Induced Cracking .................................... .4-23
Rotator .................................................................. 8-119
Multiplexer ................................................... 8-116, 9-22
Security .......................................................... 9-15, 9-25
Newsletter ................................................................. 6-2
Seminars ................................................................... 6-1
One-Hot State Machine ......................................... 8-124
Serial Arithmetic ...................................................... 8-72
OrCAD .................................................. 7-14, 7-15, 7-32
Serial PROM .......................... 2-32, 2-118, 2-192, 2-223
Oscillator ...................... 2-25, 2-111, 2-117, 2-187, 8-13
Series Resonance ................................................... 9-31
10-3
I
Index
Series Termination .................................................. 9-29
Tilde .......................................................................... 9-3
Set-Up Time .............................................................. 9-6
Training Courses ....................................................... 6-6
Shift Register ........................................................... 9-14
Transition Time ....................................................... 8-10
Shift Register ( RAM-Based) ................................ 8-110
Transition Time. Input ........................................... 2-102
Sine Wave Generator .............................................. 9-18
Transmission Line ................................................... 9-28
Single-Length Lines ....................................... 2-14. 2-24
Two's Complementer ..................................... 8-86. 9-32
Slew Rate .................................................................. 9-4
UIM ................................................ 3-8. 3-25. 3-45. 8-34
Slew Rate ( XC4000H ) ........................................... 2-84
Undershoot ................................................................ 9-5
Sockets ................................................................... 4-25
Universal Interconnect Matrix ........ 3-8. 3-25. 3-45. 8-34
SoftEdge ................................................................. 2-82
Unused Pins .............................................................. 9-4
Speed Estimation .................................................... 8-16
Start-up after Configuration ............................ 2-28. 8-11
Vcc Rise Time ............. 2-33. 2-37. 2-119. 2-121. 2-123.
2-125.2-197.2-198.2-200
Start-up Timing ...................................................... 2-115
Video Mixer ........................................................... 8-157
State Machine ............................................ 8-122. 8-151
Viewlogic .................................. 7-16 through 7-23. 7-32
Subtractor ............................................. 8-72. 8-79. 8-92
Volatility ................................................................... 9-19
Sun 4 ................................................. 7-22 through 7-25
Waveform Generator ................................. 8-123. 8-143
Supply Voltage Ramp-Up .......................................... 9-9
Weight per Package ................................................4-22
Switch Matrix ........................... 2-14. 2-24. 2-105. 2-183
Wide Decoders ................... 2-12.2-20.2-49.2-67.2-87
Symbol Libraries ..................................... 2-16.7-2.7-32
X-BLOX ............................................................ 7-2.7-33
Synchronizer ........................................................... 9-13
XACT ......................................................................... 7-1
Synchronous LCA Reset ......................................... 8-12
XACT Performance ................................................. 7-30
Technical Overview (FPGAs) .................................... 2-1
XCELL ....................................................................... 6-2
Temperature Dependence ......................... 2-128.2-202
XChecker ................................................................ 7-36
Termination ............................................................. 9-28
XDM ................................................. 2-16.7-3.7-7.7-30
Thermal Characteristics .......................................... 4-18
XEPLD .................................................................... 3-48
Three-State ............................................................. 9-10
XMake ....................................................................... 7-7
Three-State Buffer ....... 2-16. 2-24. 2-109. 2-148. 2-156.
2-164.2-172
XNF ........................................................................... 7-8
Threshold. Input .............................. 2-102. 2-116. 2-191
Zero+ Family .............................................. 2-161. 2-215
Xtal Oscillator ............... 2-111. 2-117. 2-187. 8-13. 9-30
Tie ............................................................................. 9-3
10-4
Sales
Offices
HEADQUARTERS
XILlNX, Inc.
2100 Logic Drive
San Jose, CA 95124
(408) 559-7778
TWX: 510-600-8750
FAX: 408-559-7114
XILlNX, GmbH.
Dorfstr.l
85609 Aschheim
Germany
Tel: (49) 89-904-5024
FAX: (49) 89-904-4748
XILINX
SALES OFFICES
JAPAN
NORTH AMERICA
XILlNX, Inc.
3235 Kifer Road
Suite 320
Santa Clara, CA 95051
(408) 245-1361
FAX: 408-245-0517
XILlNX, Inc.
15615 Alton Parkway
Suite 280
Irvine, CA 92718
(714) 727-0780
FAX: 714-727-3128
XILlNX, Inc.
61 Spit Brook Rd.
Suite 403
Nashua, NH 03060
(603) 891-1096
FAX: 603-891-0890
XILlNX, Inc.
65 Valley Stream Parkway
Suite 140
Malvern, PA 19355
(215) 296-8302
FAX: 215-296-8378
XILlNX, Inc.
939 North Plum Grove Road
SuiteH
Schaumburg, IL 60173
(708) 605-1972
FAX: 708-605-1976
XILlNX, Inc.
5952 Six Forks Road
Raleigh, NC 27609
(919) 846-3922
FAX: 919-846-8316
XILlNX, Inc.
4141 Blue Lake Circle
Suite 217
Dallas, TX 75244
(214) 960-1043
FAX: 214-960-0927
EUROPE
XILlNX, Ltd.
Suite 1B, Cobb House
Oyster Lane
Byfleet
Surrey KT14 7DU
United Kingdom
Tel: (44) 932-349401
FAX: (44) 932-349499
XILINX K. K.
Kyobashi NO.8
Nagaoka Bldg. 8F
20-9 Hatchobori Nichome
Chuo-ku, Tokyo 104
Japan
Tel: (81) 3-3297-9191
FAX: (81) 3-3297-9189
BBS: (81) 3-3297-9195
ASIA PACIFIC
XILINX Asia Pacific
Unit 2520-2525, Tower 1
Metroplaza
Hing Fong Road
Kwai Fong, N.T.
Hong Kong
Tel: 852-410-2740
FAX: 852-418-1600
U.S. SALES
REPRESENTATIVES
ALABAMA
Novus Group, Inc. (Corporate)
2905 Westcorp Blvd.Suite 120
Huntsville, AL 35805
(205) 534-0044
FAX: 205-534-0186
ARIZONA
Quest-Rep Inc.
6494 Weathers PI, Suite 200
San Diego, CA 92121
(619) 622-5040
FAX: 619-622-5047
Norcomp
3350 Scott Blvd., Suite 24
Santa Clara, CA 95054
(408) 727-7707
FAX: 408-986-1947
Norcomp
8880 Wagon Way
Granite Bay, CA 95746
(916) 791-7776
FAX: 916-791-2223
COLORADO
Luscombe Engineering, Inc.
1500 Kansas Ave. Suite 1B
Longmont, CO 80501
(303) 772-3342
FAX: 303-772-8783
CONNECTICUT
John E. Boeing, Co., Inc.
101 Harvest Park, Bldg. lA
No. Plains Industrial Road
Wallingford, CT, 06492
(203) 265-1318
FAX: 203-265-0235
DELAWARE
Delta Technical Sales, Inc.
122 N. York Rd., Suite 9
Hatboro, PA 19040
(215) 957-0600
FAX: 215-957-0920
Quatra Associates
Micro Compo Inc.
4845 S. Lakeshore Dr.
Suite 1
Tempe, AZ 85282
(602) 820-7050
FAX: 602-820-7054
1421 S. Caton Avenue
Baltimore, MD 21227-1082
(410) 644-5700
FAX: 410-644-5707
FLORIDA
ARKANSAS
Bonser-Philhower Sales
689 W. Renner Road
Suite 101
Richardson, TX 75080
(214) 234-8438
FAX: 214-437-0897
CALIFORNIA
SC Cubed
68 long Court, Suite C
Thousand Oaks, CA 91360
(805) 496-7307
FAX: 805-495-3601
SCCubed
17862 17th St. Suite 207
Tustin, CA 92680
(714) 731-9206
FAX: 714-731-7801
Semtronic Assoc., Inc.
657 Maitland Avenue
Altamonte Springs, FL 32701
(407) 831-8233
FAX: 407-831-2844
Semtronic Assoc., Inc.
3471 N. W. 55th Street
Ft. Lauderdale, FL 33309
(305) 731-2484
FAX: 305-731-1019
Semtronic Assoc., Inc.
1467 South Missouri Avenue
Clearwater, FL 34616
(813)461-4675
FAX: 813-442-2234
GEORGIA
KENTUCKY
Novus Group, Inc.
6115-A Oakbrook Pkwy
Norcross, GA 30093
(404) 263-0320
FAX: 404-263-8946
Gen II Marketing, Inc.
4012 DuPont Circle
Suite 414
Louisville, KY 40207
(502) 894-9903
FAX: 502-893-2435
IDAHO (Southwest)
Thorson Company Northwest
12340 NE 8th St., Suite 201
Bellevue, WA 98005
(206) 455-9180
FAX: 206-455-9185
Luscombe Engineering, Inc.
360 East 4500 South, Suite 6
Salt Lake City, UT 84107
(801) 268-3434
FAX: 801-266-9021
ILLINOIS
Beta Technology Sales, Inc.
1009 Hawthorne Drive
itasca, IL 60143
(708) 250-9586
FAX: 708-250-9592
Advanced Technical Sales
13755 SI. Charles Rock Rd.
Bridgeton, MO 63044
(314) 291-5003
FAX: 314-291-7958
INDIANA
Gen II Marketing,lnc.
31 E. Main St.
Carmel, IN 46032
(317) 848-3083
FAX: 317-848-1264
Gan II Marketing, Inc.
1415 Magnavox Way
Sutie 130
Ft. Wayne, IN 46804
(219) 436-4485
FAX: 219-436-1977
IOWA
Advanced Technical Sales
375 Collins Road N.E.
Cedar Rapids, IA 52402
(319) 393-8280
FAX: 319-393-7258
KANSAS
Advanced Technical Sales
610 N. Mur-Len, Suite B
Olathe, KS 66062
(913) 782-8702
FAX: 913-782-8641
LOUISIANA (Northern)
Bonser-Philhower Sales
689 W. Renner Rd., Suite 101
Richardson, TX 75080
(214) 234-8438
FAX: 214-437-0897
LOUISIANA (Southern)
Bonser-Philhower Sales
10700 Richmond, Suite 150
Houston, TX 77042
(713) 782-4144
FAX: 713-789-3072
MAINE
Genesis Associates
128 Wheeler Road
Burlington, MA 01803
(617) 270-9540
FAX: 617-229-8913
MARYLAND
Micro Compo Inc.
1421 S. Caton Avenue
Baltimore, MD 21227-1082
(410) 644-5700
FAX: 410-844-5707
MASSACHUSETTS
Genesis Associates
128 Wheeler Road
Burlington, MA 01803
(617) 270-9540
FAX: 617-229-8913
MICHIGAN
Miltimore Sales Inc.
22765 Heslip Drive
Novi, MI 48375
(313) 349-0260
FAX: 313·349·0756
Miltimore Sales Inc_
3680 44th St., Suite 100-J
Kentwood, MI49512
(616)-554-9292
FAX: 616-554-9210
MINNESOTA
Com-Tek
6525 City West Parkway
Eden Prairie, MN 55344
(612) 941-7181
FAX: 612-941-4322
I
7/9/93
10 - 5
Sales Offices
MISSISSIPPI
NEW JERSEY (Southern)
Novus Group, Inc.(Corporate)
2905 Westcorp Blvd. Suite 120
Huntsville, AL 35805
(205) 534-0044
FAX:205-534-0186
Delta Technical Sales, Inc.
122 N. York Road, Suite 9
Hatboro, PA 19040
(215) 957-0600
FAX: 215-957-0920
Bear Marketing, Inc.
240 W. Elmwood Drive
Suite 1012
Centerville, OH 45459·4248
(513) 436-2061
FAX: 513-436-9137
OKLAHOMA
MISSOURI
NEW MEXICO
Advanced Technical Sales
601 N. Mur-Len, Suite B
Olathe, KS 66062
(913) 782-8702
FAX: 913-782-8641
Quatra Associates
600 Autumwood Place, S. E.
Albuquerque, NM 87123
(505) 296-6781
FAX: 505-292-2092
Advanced Technical Sales
13755 SI. Charles Rock Rd.
Bridgeton, MO 63044
(314) 291-5003
FAX: 314·291-7958
NEW YORK (Metro)
OREGON
Parallax
734 Walt Whitman Road
MellYille, NY 11747
(516) 351-1000
FAX: 516-351-1606
Thorson Company Northwest
9600 S.W. Oak Street,
Suite 320
Portland, OR 97223
(503) 293·9001
FAX: 503-293-9007
MONTANA
Luscombe Engineering, Inc.
360 East 4500 South, Suite 6
Salt Lake City, UT 84107
(801) 268-3434
FAX: 801-266-9021
NEBRASKA
Advanced Technical Sales
375 Collins Road N.E.
Cedar Rapids, IA 52402
(319) 393-8280
FAX: 319-393-7258
Bonser-Philhower Sales
689 W. Renner Rd., Suite 101
Richardson, TX 75080
(214) 234-8438
FAX: 214-437-0897
NEW YORK
PENNSYLVANIA
Electra Sales Corp.
333 Metro Park
Suite Ml03
Rochester, NY 14623
(716) 427-7860
FAX: (716) 427-0614
Delta Technical Sales, Inc.
122 N. York Rd., Suite 9
Hatboro, PA 19040
(215) 957-0600
FAX: 215·957-0920
Electra Sales Corp.
6700 Old Collamer Rd.
E. Syracuse, NY 13057
(315) 463-1248
FAX: (315) 463-1717
Bear Marketing, Inc.
4284 RI. 8, Suite 211
Allison Park, PA 15101
(412) 492-1150
FAX: 412-492-1155
NORTH CAROLINA
PUERTO RICO
The Novus Group, Inc.
102L Commonwealth Court
Cary, NC 27511
(919) 460-7771
FAX: 919-460-5703
Mercantile Plaza Building
Suite 816
Hato Rey, PR 00918
NEW HAMPSHIRE
Com-Tek
6525 City West Parkway
Eden Prairie, MN 55344
(612) 941-7181
FAX: 612-941-4322
NORTH DAKOTA
OHIO
NEW JERSEY (Northern)
Parallax
734 Walt Whitman Road
Mellville, NY 11747
(516) 351-1000
FAX: 516-351-1606
Semtronic Assoc., Inc.
TEXAS
Bonser-Philhower Sales
8240 MoPac Expwy.,
Suite 135
Austin, TX 78759
(512) 346-9186
FAX: 512·346·2393
Bonser-Philhower Sales
10700 Richmond, Suite 150
Houston, TX 77042
(713) 782-4144
FAX: 713·789-3072
Bonser-Philhower Sales
689 W. Renner Rd., Suite 101
Richardson, TX 75080
(214) 234-8438
FAX: 214-437-0897
TEXAS (EI Paso County)
600 Autumwood Place SE
Albuquerque, NM 87123
(505) 296-6781
FAX: 505·292-2092
Bear Marketing, Inc.
3554 Brecksville Road
PO Box 427
Richfield, OH 44286-0427
(216) 659-3131
FAX: 216-659-4823
Luscombe Engineering Co.
360 East 4500 South, Suite 6
Salt Lake City, UT 84107
(801) 268-3434
FAX: 801-266-9021
(809) 766-070010701
FAX: 809-763-8071
The Novus Group,lnc.
1775 Cox Rd.
Weddington, NC 28105
(704) 846-4044
FAX: 704-846-4055
128 Wheeler Road
Burlington, MA 01803
(617) 270-9540
FAX: 617·229-8913
Thorson Company Northwest
12340 NE 8th Street,
Suite 201
Bellevue, WA 98005
(206) 455·9180
FAX: 206·455-9185
UTAH
Quatra Associates
(Las Vegas)
4645 S. Lakeshore Dr., Suite 1
Tempe, AZ 85282
(602) 820-7050
FAX: 602-820-7054
Genesis Associates
WASHINGTON
The Novus Group, Inc.
1722 William Blount Dr.
Maryville, TN 37801
(615) 681-8895
FAX: 615-681-8893
Quatra Associates
NEVADA
Norcomp
(Excluding Las Vegas)
3350 Scott Blvd., Suite 24
Santa Clara, CA 95054
(408) 727-7707
FAX: 408-986-1947
TENNESSEE
RHODE ISLAND
Genesis Associates
128 Wheeler Road
Burtington, MA 01803
(617) 270·9540
FAX: 617-229-8913
SOUTH CAROLINA
The Novus Group, Inc.
102L Commonwealth Court
Cary, NC 27511
(919) 460-7771
FAX: 919-460-5703
SOUTH DAKOTA
Com-Tek
6525 City West Parkway
Eden Prairie, MN 55344
(612) 941-7181
FAX: 612·941-4322
VERMONT
Genesis Associates
128 Wheeler Road
Burlington, MA 01803
(617) 270-9540
FAX: 617-229-8913
WASHINGTON
(Vancouver, WA only)
Thorson Company Northwest
9600 S. W. Oak Street
Suite 320
Portland, OR 97223
(503) 293-9001
FAX: 503-993-9007
WASHINGTON D.C,
Micro Comp, Inc.
1421 S. Caton Avenue
Baltimore, MD 21227-1082
(410) 644-5700
FAX: 410-644-5707
WISCONSIN (Western)
Com-Tek
6525 City West Parkway
Eden Prairie, MN 55344
(612) 941-7181
FAX: 612·941-4322
WISCONSIN (Eastern)
Beta Technology Sales, Inc.
9401 N. Beloit, Suite 409
Milwaukee, WI 53227
(414) 543-6609
FAX: 414-543-9288
WYOMING
Luscombe Engineering, Inc.
360 East 4500 South, Suite 6
Salt Lake City, UT 84107
(801) 268-3434
FAX: 801-266-9021
VIRGINIA
Micro Comp, Inc.
8811Timbertake Rd.
Suite 107
Lynchburg, VA 24502
(804) 239-2626
FAX: 804-239-1333
Bear Marketing, Inc.
4264 RI. 8 Suite 211
Allison Park, PA 15101
(412) 492-1150
FAX:412-492-1155
Distributed in North America By
Hamilton/Avnet
Locations throughout
the U.S. and Canada.
1-800-888-9236
FAX: 406-743-3003
Marshall Industries
Locations throughout
the U.S. and Canada.
(800) 522-0084
FAX: 818-307-6297
Insight Electronics
Locations throughout
the Western & South
Central U.S.
1-800-677-7716
FAX: 619-587-1380
10 - 6
Phase 1 Technology Corp.
46 Jefryn Blvd.
Deer Park, NY 11729
(516) 254-2600
FAX: 516-254-2693
FAX: 516-254-2695(NY sales)
Nu Horizons
Electronics Corp.
6000 New Horizons Blvd.
Amityville, New York 11701
(516) 226-6000
FAX: 516-226-6262
I::XIUNX
INTERNATIONAL
SALES
REPRESENTATIVES
ASEAN
(Singapore, Malaysia,
IndoneSia, Thalland,
Phillippines, Brunei)
MEMEC Asia Pacific Ltd.
10 Anson Rd. #14-02
International Plaza
Singapore 0207
Tel: (65) 222-4962
FAX: (65) 222-4939
AUSTRAUA
ACD
106 Belmore Rd. North
Riverwood, N.S.W. 2210
Sydney, Australia
Tel: (61) 2-534-6200
FAX: (61) 2-534-4910
ACD
UnH 2, 17-19 Melrich Road
PO Box 139
Bayswater VIC 3153
Melboume, Australia
Tel: (61) 3-762-7644
FAX: (61) 3-762-5446
ACD
Enterprise Unit 1
Technology Park
Bentley WA 6102
Australia
Tel: (61) 9-472-3232
FAX: (61) 9-470-2303
ACD
200 William Street
Norwood SA 5067
South Australia
Tel: (61) 8-384-2644
FAX: (61) 8-264-2811
AUSTRIA
Eljapex GmbH.
Eltnergasse 6
A-1232Wlen
Austria
Tel: (43) 1-863211
FAX: (43) 1-861531201
BELGIUM & LUXEMBURG
Rodelco NV
Limburg Stirum 243
1780Wemmel
Belgium
Tel: (32) 2-480-0580
FAX: (32) 2-480-0271
CANADA
(BRITISH COLUMBIA)
Thorson Company Northwest
12340 N.E. 8th Street
Suite 201
Bellevue, WA 98005 USA
Tel: (206) 455-9180
FAX: 208-455-9185
Electro Source
3665 Kingsway, Suite 300
Vancouver, B.C: V5R 5W2
canade
Tel: (604) 275-2734
FAX: 604-275-2736
CANADA (OTTAWA)
Electro Source, Inc.
300 March Road, Suite 203
Kanata, Ontario K2K 2E4
Canada
Tel: (613) 592-3214
FAX: 613-592-4256
CANADA (TORONTO)
Electro Source, Inc.
230 Galaxy Blvd.
Rexdale Ontario M9W 5R8
Canada
Tel: (416) 675-4490
FAX: 416-675-6871
CANADA (QUEBEC)
Electro Source
6600 TransCanada Hwy
Suite 420
Point Claire Quebac H9R 4S2
Canada
Tel: (514) 630-7486
FAX: 514-630-7421
CHINA PEOPLE'S REPUBLIC
MEMEC Asia Pacific Ltd.
UnH No. 3012-3015, Tower 1
Metroplaza, Hing Fong Rd.
Kwai Fong, N.T. Hong Kong
Tel: (852) 410-2780
FAX: (852) 401-2518
CZECH REPUBLIC
EljapexlElbatex G.m.b.H
Prechodni 11
CZ-14O 00 Praha 4
Czech Republic
Tel: 02-692-8087
FAX: 02-471-82-03
DENMARK
Dana Tech AlS
Krogshoejvej 51
DK-2880 Bagsvaerd
Denmark
Tel: (45) 44-37 71 10
FAX: (45) 44-37 71 12
Dana Tech AS
Egsagervej 8
OK 8230 Aabyhoej
Denmark
Tel: (45) 86-253100
FAX: (45) 86-253102
FINLAND
Field OY Instrumentarium
NiittylAntle 5
SF-00620 Helsinki
Finland
Tel: (358) o-n7571
FAX: (358) 0-798853
FRANCE
Rep1ronic
1 Bis, rue Marcel Paul
BAt A
Z.t. La Bonde
F-91300 Massy
France
Tel: (33) 1-60139300
FAX: (33) 1-60139198
AVNET/EMG.
79 Rue Pierre Bemard
92320 Chatilion
France
Tel: (33) 1 496525 00
FAX : (33) 1 49652738
AVNET Composant
Sud-Ouest
Innopolis Hall A
Voie No. 1-BP 404
31314 Labege C9dex
France
Tel: (33) 61 3921 12
FAX: (33) 61 3921 40
AVNET Composant
AquHaine
16 Rue Fran~ois Arago
Zi du Phare
33700 Merignac
France
Tel: (33) 56 55 92 92
FAX: (33) 56 34 39 99
AVNET Composant
RhOne-Auvergne
Parc Cluc du Moulin it Vent
84t26
33 Av. du docteur G. Levy
69200 Vo!nissieux
France
Tel: (33) 78 00 07 26
FAX: (33) 78 01 2057
AVNET Composant
Provence COte D'Azur
8300 Toulon
France
Tel: (33) 94 03 32 56
FAX: (33) 94 36 0215
AVNET Composant
Ouest
Technoparc-BAt.E
4 Av. des Peupliers
35510 casson Sevigne
Franca
Tel: (33) 99 83 84 85
FAX: (33) 99 83 80 83
AVNET Composant
RhOne-Alpes
Miniparc - Zac des Bealieres
23 Av. de Granier
38240 Meylan
France
Tel: (33) 76 90 11 88
FAX: (33) 76 41 04 09
AVNETComposant
Nantes
Le Silion de Bretagne
23e etage-Aile C
8 Av.des Thobaudieres
44802 Saint Herblain
France
Tel: (33) 40 63 23 00
FAX: (33) 40 63 22 88
AVNET Composant
Est
19 Rue de Rennes, BP 163
54186 Heillecourt Codex
Franca
Tel: (33) 83 531234
FAX: (33) 83 56 70 03
10 -7
GERMANY
Avnet E2000
Stahlgruberring 12
81829 Manchen
Germany
Tel: (49) 89-45110-01
FAX: (49) 89-45110-129
Avnet E2000
Kurfiirstenstr. 126
10785 Be~in
Germany
Tel: (49) 30-2110761
FAX: (49) 30-2141728
AvnetE2000
Ivo-Hauptmann-Ring 21
22159 Hamburg
Germany
Tel: (49) 40-645570-0
FAX: (49) 40-6434073
AvnetE2000
Benzstr.l
70826 Ge~ingen
Stuttgart
Germany
Tel: (49) 7156-356-0
FAX: (49) 7156-28084
Avnet E2000
Heinrich-Hertz·Str. 52
40899 Erkrath
Dusseldorf
Germany
Tel: (49) 211-92003-0
FAX: (49) 211-92003-99
Avnet E2000
Schmidtstr. 49
60326 FrenkfurtlM.
Melronik GmbH
Pilotystr.27129
90408 Namberg
Germany
Tel: (49) 911-544966168
FAX: (49) 911-542936
Metronik GmbH
LOwenstr. 37
70597 Stuttgart
Germany
Tel: (49) 711-764033135
FAX: (49) 711-7655181
Metronik GmbH
Liessauer Pfad 17
13503 Berlin
Germany
Tel: (49) 30-436-1219
FAX: (49) 30-431-5956
Metronik Systeme
Grenzstr. 26
06112 Halle
Germany
Tel: (49) 345-823-352
FAX: (49) 345-823-346
Metronik GmbH
Alsfelderstr. 7
64289 Darmstadt
Germany
Tel: (49) 6151-73-0540
FAX: (49) 6151-71-6652
Intercomp
Am Hochwald 42
62319 Starnberg
Germany
Tel: (49) 8151-16044
FAX: (49) 8151-79270
Germany
Tel: (49) 69-973804-0
FAX: (49) 211-7380712
AvnetE2000
Killanstr.251
90411 Namberg
Germany
Te;: (49) 911-995161-0
FAX: (49) 911-515762
Metronik GmbH
Leonhardsweg 2
82008 Unterhaching
Manchen
Germany
Tel: (49) 89-611080
FAX: (49) 89-6116468
Metronik GmbH
Zum Lonnenhohl 38
44319 Dortmund
Germany
Tel: (49) 231-2141741/43
FAX: (49) 231-210799
Metronik GmbH
Gottlleb-Daimler-Str.7
24568 Kallenkirchen
Hamburg
Germany
Tel: (49) 41-91-4208
FAX: (49) 41-91-4428
Metronik GmbH
Siemenstr. 4-6
68542 Heddesheim
Mannheim
Germany
Tel: (49) 6203-4701/03
FAX: (49) 620345543
Intercomp
Meisenweg 19
65527 Niedemhausen
Germany
Tel: (49) 6128-71140
FAX: (49) 6128-72228
GREECE
Peter Caritato & Assoc. S. A.
L1ia lliot, 31
Athens 11743 Greece
Tel: (30) 1-9020115
FAX: (30) 1-9017024
HONG KONG
MEMEC AsI!! Pacnic Ltd.
UnH No. 3012-3015, Tower I
Metroplaza, Hing Fong Road,
Kwai Fong, N.T.
Hong Kong
Tel: (852) 410 2780
FAX: (852) 401 2518
HUNGARY
Dataware KFTlElbatex GmbH
Angol Utca 22
H-1149 Budapest
Hungary
Tel: (36) 11635081
FAX: (36) 1251-5517
EljapexlElbatex GmbH
Vaci u 202
H-1138 Budapest
Hungary
Tel: (36) 1-140-9194
FAX: (36) 1-220-9478
I
Sales Offices
INDIA
Malhar Corporation
507 Montague Expressway
Mlpitas, CA 95053
USA
Tel: (408) 263-7505
FAX: (408) 263-7585
Malhar SaleS&Service Pvt. Ltd.
1214 Hal lind Stage
Indiranagar
Bangalore 560038
India
Tel: (91) 812-568772
FAX: (91 812-542588
Core EI Micro Systems
45131 Manzanita Court
Fremont, Califomia 94539
USA
Tel:(510) 770-1066
FAX: 510-657-1525
IRELAND
Memec Ireland Ltd.
Block H Lock Ouay
Clare Street
Limerick
Ireland
Tel: (353) 61-411842
FAX: (353) 61-411888
ISRAEL
E.I.M International Ltd.
Hamshiloach Street
P.O. Box 4000
Petach Tiqva
Israel 49130
Tel: (972) 3·92 208122
FAX: (972) 3-924 4857
ITALY
ACSIS S.R.L.
Via Alberto Mario. 26
20149 Milano, Italy
Tel: (39) 2-48022522
FAX: (39) 2-48012289
Silverstar-Celdis
Viale Fulvio Testi N.280
20126 Milano, Italy
Tel: (39) 2-661251
FAX: (39) 2·661014275
Silverstar-Celdis
Via Collamarini, 22
40139 Bologna, Italy
Tel: (39) 51-538500
FAX: (39) 538831
Silverstar-Celdis.
Via Bille', 26
Ascoli Piceno Fermo
Tel: (39) 734-226181
FAX: (39) 734-229330
Silverstar-Celdis
Via Paisiello,30
00162 Roma, Italy
Tel: (39) 6-8848841
FAX: (39) 6-8553228
Silverstar-Celdis
Piazza Adriano 9
10139 Torino, Italy
Tel: (39) 11-443275
FAX: (39) 114473306
Silverstar-Celdis
Centro Direzionale Benelli
Via M. Del Monaco, 16
6100 Pesaro, Italy
Tel: (39) 721-26560
FAX: (39) 721-400896
Silverstar-Celdis
Via Masaccio, 175
50019 Firenze, Italy
Tel: (39) 55-572418
FAX: (39) 55-579575
Silverstar-Celdis
Piazza Marini 20110
Lavagna-Genova
Italy
Tel: (39) 185-325325
FAX: (39) t85-303100
JAPAN
Okura & Co., Ltd.
6-12, Ginza Nichome
Chuo-Ku
Tokyo, 104 Japan
Tel: (81) 3-3566-6364
FAX: (81) 3-3566-2887
Fuji Electronics Co., Ltd.
Ochanomizu Center Bldg.
3-2-12 Hongo. Bunkyo-ku
Tokyo, 113 Japan
Tel: (81) 3-3814-1411
FAX: (81) 3-3814-1414
Okura Electronics Co., Ltd.
3-6, Ginza 2-chome,
Chuo-ku,
Tokyo, 104 Japan
Tel: (81) 3-3564-8871
FAX: (81) 3-3564-6870
Okura Electronics
Service Co., Ltd.
Kyoei Bldg.
5-3, Kyobashi 3-chome,
Chuo~ku,
Tokyo, 104 Japan
Tel: (81) 3-3567-6501
FAX: (81) 3-3567-7800
Tokyo Electron Ltd.
P. O. Box 7006
Shinjuku Monolith
3-1 Nishi-Shinjuku 2-chome,
Shinjuku-ku,
Tokyo, 163 Japan
Tel: (81) 3-3340-8193
FAX: (81) 3-3340-8408
T owa Elex Co., Ltd.
Lapre Shinjuku
2-15-2 Yoyogi,
Shibuya-ku, Tokyo, 151
Japan
Tel: (81) 3-5371-3411
FAX: (81) 3-5371-4760
Varex Co., Ltd.
Nippo Shin-Osaka No.2 Bldg.
1-8-33, Nishimiyahara,
Yodogawa-ku,
Osaka, 532 Japan
Tel: (81) 6-394-5201
FAX: (81) 6-394-5449
Inoware 21, Inc.
TSI Nihonbashi Hamacho
Daini Bldg.
3-36-5, Nihonbashi Hamacho
Chuo-ku,
Tokyo, 103 Japan
Tel: (81) 3-5695-1521
FAX: (81) 3-5695-1524
Vostorg
3 Rue des Acacias
91370 Verrieres Ie Buisson
France
Tel: (33) 1-6920-4613
FAX: (330 1-6011-5543
SINGAPORE
MEMEC Asia Pacific Ltd.
Singapore Representative Office
10 Anson Road #14-02
International Plaza
Singapore 0207
Tel: (886) 65-222-4962
FAX: (888)-65-222-4939
AOM Electronics SA
Mallorca 1
08014 Barcelona
Spain
Tel: (34) 3-4266892
FAX: (34) 3-4250544
SLOVAK REPUBLIC
KOREA
MEMEC Asia Pacific Ltd.
3FL, Je Woong Bldg.,176-11
Nonhyun-dong
Kangnam-ku
Seoul,135-010, South Korea
Tel: (82) 2-518-8181
FAX: (82) 2-518-9419
THE NETHERLANDS
Rodelco BV
P.O.Box 6824
Takkebijsters 2
4802 HV Breda
The Netherlands
Tel: (31) 76-784911
FAX: (31) 76-710029
NEW ZEALAND
ACO
106 Belmore Rd., North
Riverwood, N.S.W. 2210
Sydney, Australia
Tel: (61) 2-534-6200
FAX: (61) 2-534-4910
NORWAY
BIT Elektronikk AS
Smedsvingen 4
P.O. Box 194
1360 Nesbru
Norway
Tel: (47) 2-98 1370
FAX: (47)2-98 1371
POLAND
EljapexlElbatex GmbH
UI. Hoza 29/31-6
PL-00-521 Warszawa
Poland
Tel: (48) 2625-4877
FAX: (48) 2221-6331
PORTUGAL
Componenta Componentes
Electronicos LOA
R. Luis De Camoes, 128
1300 Lisboa
Portugal
Tel: (351) 1 362128314
FAX: (351) 13637655
RUSSIA
Scan
10/32 "B" Druzhby SI.
117330 Moscow
Russia
Tel: (7) 095-1436641/47/43
FAX: (7) 095-9382247
10 - 8
SPAIN
ADM Electronics SA
Calle Tomas Breton,
no 50, 3-2
28045 Madrid
Spain
Tel: (34) 91-5304121
FAX: (34) 91-5300164
T opoicianska 23
SO-851 05 Bratislava
Tel: (42) 7831-320
FAX: (42) 7831-320
ADM Electronica, SA
Herriro Gudarien, 8-10
48200 Durango (Vizcaya)
Tel: 34-4-6201572
FAX: 34-4- 6202331
SLOVENIA/CROATIA
SWEDEN
EljapexiElbatex GmbH
Stegne 19, PO Box 19
SLO-61-117 Ljubijana
Tel: (061) 191-126-507
FAX: (061) 192-398-507
DipCom Electronics AB
P.O. Box 1230
S-164 28 Kista
Sweden
Tel: (46) 8 752 24 80
FAX: (46) 8 751 3649
SOUTH AFRICA
South African Micro-Electronic
Systems (PTV) Ltd.
2 Rooibok Avenue
Koedoespoort, Pretoria
Republic of South Africa
Tel: (27) 012-736021
FAX: (27) 012-737084
Interface International Corp.
15488 Los Gatos Blvd.,
Suite 211
Los Gatos, CA 95032
USA
Tel: (408) 356-0216
FAX: (408) 356-0207
SOUTH AMERICA
DTS Ltda.
Rosas 1444
Santiago
Chile
Tel: (56) 2-699-3316
FAX: (56) 2-697-0991
Reycom Electronica SRL
Uruguay 362 Peso 8 - Depto. F
1015 Buenos Aires
Argentina
Tel: (54) 1-45-6459/49-7030
FAX: (54) 1-11-1721
SWITZERLAND
Fenner Eleklronik AG
Abteilung Bauteile
Gewerbestrasse 10
CH-4450 Sissach
Switzerland
Tel: (41) 61 9750000
FAX: (41) 61971 5608
TAIWAN
MEMEC Asia Pacific Ltd.
9F-2, No. 225
Nanking E. Rd, Sec. 5
Taipei
Taiwan R.O.C.
Tel: (886) 2-760-2028
FAX: (886) 2-765-1488
UK
Microcall Ltd.
17 Thame Park Road
Thame
OxonOX93XD
England
Tel: (44) 844-261939
FAX: (44) 844-261678
Cedar Technologies
The Old Water Works
Howse Lane
Bicester
Hitech
Oxfordshire OX6 8XF
Divisao de Hicad Sistemas Ltda. England
Av. Eng. Louiz Carlos Berrini 801 Tel: (44) 869-322366
04571-Brooklin
FAX: (44) 869-322373
Sao Paulo, Brazil
Tel: (55) 11-531-9355
Avnet EMG Ltd.
FAX: (55) 11-240-2650
Jubilee House
Jubilee Road
SOUTHEAST ASIA
Letchworth
Hertfordshire SG6 10H
MEMEC Asia Pacific Ltd.
England
Unit No. 2520-2525, Tower I
Tel: (44) 462 480888
Metroplaza, Hing Fong Road,
FAX: 44 462 682467
Kwai Fong, N.T.
Hong Kong
Tel: (852) 418-0909
FAX: (852) 418-1600
0010170
E: XIUNX®
The Programmable Logic Company '"
2100 Logic Drive, San Jose, CA 95124
/
Tel: (408) 559-7778 EasyLink 62916309 TWX: 5106008750 XILl NX UQ FAX: (408) 559-71 14
Printed in U.S.A.
PN 0401096-01
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